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EK-ADV11-OP-002

April 1977

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Document:	ADV11-A, KWV11-A, AAV11-A, DRV11 User's Manual
Order Number:	EK-ADV11-OP
Revision:	002
Pages:	89
Original Filename:	http://bitsavers.org/pdf/dec/qbus/EK-ADV11-OP-002_ADV11-A_KWV11-A_AAV11-A_DRV11_Users_Manual_Apr77.pdf

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ADV11-A, KWV11-A,
AA V11 -A, D RV11
user's manual

EK-ADV11-0P-002

ADV11 -A, KWV11-A,
AAV11-A, D RV11
user's manual

digital equipment corporation • maynard, massachusetts

1st Edition, July 1976
2nd Printing (Rev) November 1976
3rd Printing (Rev) April 1977

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in U.S.A.

This document was set on DIGITAL's DECset·8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
DECCOMM
DECsystem-IO
DECSYSTEM·20

DECtape
DEeUS
DIGITAL
MASSBUS

PDP
RSTS
TYPESET·8
TYPESET· I I
UNIBUS

CONTENTS
Page
CHAPTER 1

INTRODUCTION

1.1

1.2

GENERAL
REFERENCES

CHAPTER 2

ADVII-A ANALOG-TO-DIGITAL CONVERTER

2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.4
2.4.1
2.4.1.1
2.4.1.2
2.4.2.1
2.4.2.2
2.4.2.3
2.4.3
2.4.3.1
2.4.3.2
2.4.3.3
2.4.4
2.5
2.5.1
2.5.2
2.5.3

GENERAL DESCRIPTION
SPECIFICATIONS
Electrical . .
Coding '"
Performance
Timing . . .
Test Signals
Power Requirements
FUNCTIONAL DESCRIPTION
Channel Selection
A/D Conversion
Interface Functions
Control . " . . .
USER INTERFACING
Analog Inputs
Single-Ended Mode
Quasi-Differential Mode
Avoiding Spurious Signals
Twisted Pair Input Lines
Shielded Input Lines
Allowing for Input Settling with High Source Impedance
Connections . . . . . . . . .
Distribution Panel
External and Clock Starts
Mode Control . . . . .
Vector and Address Selection
PROGRAMMING . . . . . . . . .
Control/Status Register (CSR)
Data Buffer Register (DBR)
Programming Example . . . .

CHAPTER 3

KWVII-A PROGRAMMABLE REAL-TIME CLOCK

3.1
3.2
3.2.1
3.2.2
3.2.2.1
3.2.2.2
3.2.2.3

GENERAL DESCRIPTION
SPECIFICATIONS
Clock . . . . . . . . .
Input and Output Signals
Input Signals
Output Signals
Power Requirements (from LSI-II Bus Power Supply)

2.4.2

1-1
1-1

iii

2-1
2-1
2-1
2-2
2-2
2-3
2-3
2-3
2-3
2-4
2-4

2-6
2-6
2-6
2-6
2-6
2-7
2-9
2-9

2-11
· 2-11
2-11
2-11
2-11
2-12
2-12
· 2-14
2-14
2-16
· 2-17

3-1
3-1
3-1
3-1
3-2
3-3

3-3

CONTENTS (Cont)
Page
3.3
3.3.1
3.3.2
3.3.3
3.3.3.1
3.3.3.2
3.3.3.3
3.3.3.4
3.3.3.5
3.3.4
3.3.5
3.3.6
3.4
3.4.1
3.4.2
3.4.3
3.4.3.1
3.4.3.2
3.4.3.3
3.5
3.5.1
3.5.2
3.5.3
3.5.3.1
3.5.3.2
3.5.3.3
3.5.3.4
3.5.4

3-3
FUNCTIONAL DESCRIPTION
Bus Control
.....
3-3
3-3
Control/Status Register
3-4
Mode Control
Mode 0 (Single Interval)
3-4
3-4
Mode 1 (Rr-peated Interval)
Mode 2 (External Event Timing) . . . . . . . . .
3-5
3-5
Mode 3 (External Event Timing from Zero Base)
3-5
Flag Overrun . . . . . . . . . .
Oscillator, Divider, Rate Control Chain
3-5
. . . . . .. 3-5
Buffer/Preset and Counter Registers .
. . . .. 3-5
Schmitt Triggers . . . . . . . . . . .
3-6
CONNECTORS, SWITCHES, AND CONTROLS
3-6
............ .
40-Pin Connector
3-6
FAST ON Connectors (Clock Overflow and STI Outputs)
3-6
Selector Switches (Address, Vector, and Slope/Reference Level)
Address Selection . . . . . . . . . . . . . . . . . . . . .
3-7
Vector Selection . . . . . . . . . . . . . . . . . . . . .
3-8
Slope and Reference Level Selector Switches and Controls
3-8
PROGRAMMING . . . . . . . .
3-8
CS R Bit Assignments . . . .
3-8
Buffer/Preset Register (BPR)
3-9
Normal Control Sequences .
3-9
3-9
Mode 0 (Single Interval)
3-13
Mode 1 (Repeated Interval)
Mode 2 (External Event Timing)
. 3-13
. 3-17
Mode 3 (External Event Timing from Zero Base)
.. 3-17
Programming Example . . . . . . . . . . . .

CHAPTER 4

AAVII-A DIGITAL-TO-ANALOG CONVERTER

4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.4
4.4.1
4.4.2
4.4.3
4.5
4.5.1
4.5.2

GENERAL DESCRIPTION ..
SPECIFICATIONS
..... .
FUNCTIONAL DESCRIPTION
Bus Control
Control Logic
DACs 0,1, and 2
DAC3 . . . . .
CONNECTORS, SWITCHES, AND CONTROLS
.....
40-Pin Connector
Address Switches . . . . . . . . . .
Mode/Level Selector Jumpers
INTERFACING TO OUTPUT DEVICES
Ground Connections
Tw~~g
............. .

4-1
4-1
4-2
4-2
4-2
4-2
4-2
4-4
4-4
4-5
4-6
4-6
4-6

4-7

CONTENTS (Cont)
Page
4-7
4-7
4-7

4.5.3
4.5.4
4.6

Shielding . . . .
Drive Capability
PROGRAMMING .,

CHAPTERS

DRV11 PARALLEL LINE UNIT

5.1
5.2
5.2.1
5.2.2
5.2.3
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.4
5.4.1
5.4.2
5.4.3
5.4.4

GENERAL DESCRIPTION . . . . . . . . . . . . . .
JUMPER-SELECTED ADDRESSING AND VECTORS
Locations
Addressing . . . . . . . . . . . . . .
Vectors . . . . . . . . . . . . . . . .
INTERF ACING TO THE USER'S DEVICE
General . . . . . . . .
Output Data Interface
Input Data Interface
Request Flags
Initialization . . . . .
NEW DATA READY and DATA TRANSMITTED Pulse
W'idth Modification
PROGRAMMING ..
Addressing . . .
Interrupt Vectors
W'ord Formats
I/O Timing .. '

CHAPTER 6

ADV11-A, KWV11-A, and AAV11-A MAINTENANCE

6.1
6.2
6.2.1
6.2.1.1
6.2.1.2
6.2.1.3
6.2.1.4
6.2.1.5
6.2.1.6
6.2.1.7
6.2.2
6.2.2.1
6.2.2.2
6.2.2.3
6.2.3
6.2.4
6.2.5
6.3
6.3.1
6.3.1.1

MAINTENANCE PHILOSOPHY . . . . . . . . .
ADV11l-A ANALOG-TO-DIGITAL CONVERTER
Installation . . . . . . . . . . . .
Location . . . . . . . . . .
Address and Vector Selection
Board Insertion
Test Connector
Shields
Acceptance ..
Final Connections
ADV11-A Circuitry
ADV11-A Analog Power Supply
ADV11-A A/D Conversion Circuit
The Vernier DAC . . . . . . . . .
ADV11-A Performance Test (MAINDEC-11-DVADA-A)
Maintenance . . . . . . .
Calibration . . . . . . . .
KWV11-A REAL TIME CLOCK
Installation .
Location

5-1
5-1
5-1
5-2
5-2
5-3
5-3
5-3
5-5
5-5
5-6
5-6
5-6
5-6
5-7
5-7
5-7

6-1
6-1
6-1
6-1
6-1
6-1
6-1
6-1
6-2
6-2
6-2
6-2
6-4

6-8
6-8
6-10
6-10
6-10
6-10
6-10

CONTENTS (Cont)
Page
6.3.1.2
6.3.1.3
6.3.1.4
6.3.1.5
6.3.2
6.3.3
6.3.4
6.3.5
6.4
6.4.1
6.4.1.1
6.4.1.2
6.4.1.3
6.4.1.4
6.4.1.5
6.4.2
6.4.3
6.4.4
6.4.4.1
6.4.4.2
6.4.5
6.4.6
6.4.7

Address and Vector Selection
Board Insertion .
Test Connections
Acceptance .
Final Connections
KWVll-A Circuitry
KWVll-A Diagnostic (MAINDEC-ll-DVKWA-A-D)
Maintenance . . . . . . . . . . . . . . . . .
AAVll-A DIGITAL-TO-ANALOG CONVERTER
Installation . . . . . .
Location
Address Selection.
Board Insertion
Test Connectors
Acceptance Test
Final Connections
Mode/Level Selection
AAVll-A Circuitry
AAV ll-A Analog Power Supply
Digital-to-Analog Circuits . . . .
AAVll-A Diagnostic Test (MAINDEC-ll-DV AAA-A)
Maintenance
Calibration . . . . . . . . . . . . . . . . . . . . . .

6-10
6-10
· 6-10
6-10
6-10
· 6-11
· 6-11
6-11
6-11
· 6-11
6-11
· 6-11
· 6-11
6-11
6-11
6-11
6-12
· 6-12
· 6-12
· 6-14
6-14
· 6-14
6-16

ILLUSTRATIONS
Figure No.
2-1
2-2
2-3
2-4

2-5
2-6
2-7
2-8
2-9
2-10

2-11
2-12
3-1
3-2

Title
ADVll-A Functional Block Diagram . . . . . .
Single-Ended Input Referenced to User's Ground
Floating ADVll-A Input Signals . . . . . . . . . .
Single-Ended Versus True Differential Input Modes
ADV ll-A Quasi-Differential Mode . . . . . .
ADVll-A Connectors and Switches . . . . .
ADV ll-A 40-Pin Connector Pin Assignments
H322 Distribution Panel . . . . . . . .
Module Jumpers . . . . . . . . . . . . .
ADV ll-A Address and Vector Switches
..... .
(Rocker or Slide Switches)
ADVll-A Control/Status Register (CSR)
ADVll-A Data Buffer Register (DBR)
KWVll-A Connectors, Switches, and Controls
KWVll-A Real-Time Clock Block Diagram . . .

Page

. . . . . ..

2-5
2-7
2-8
2-9

· 2-10
· 2-12
· 2-13

2-13
· 2-14

· 2-15
· 2-16
2-16
3-2
3-4

ILLUSTRATIONS (Cont)
Figure No.
3-3

3-4
3-5
3-6
3-7

3-8
3-9
4-1
4-2
4-3

4-4
4-5
4-6
5-1

5-2
5-3
5-4
5-5

5-6
5-7
6-1
6-2
6-3
6-4

6-5
6-6
6-7
6-8

6-9
6-10
6-11

Title

Page

Connecting External User-Supplied Slope and Level Controls
40-Pin Connector Pin Assignments
........ .
KWV1l-A CSR Address Switches (Set for 170420) . . . . .
KWV1l-A Vector Address Switches (Set for 000440) . . . .
KWV1l-A Slope/Reference Level Selector Switches and Controls
KWV ll-A Slope Selection
CS R Bit Assignments
............ .
AAV 11-A Block Diagram . . . . . . . . . .
AAV 11-A Connectors, Switches, and Controls
40-Pin Connector Pin Assignments
.... .
AAV11-A Address Decoding
....... .
AAV l1-A Address Switches (Set for 17044n)
Connection to Oscilloscope with Differential Input
DRV11 Parallel Line Unit
DRV11 Jumper Locations
DRV11 Device Address
DRV11 Vector Address
J 1 or J2 Connector Pin Locations
DRV11 Word Formats
.....
DRV11 Interface Signal Sequence
Battery-Operated Potentiometer Box for ADV11-A A/D Converter
Analog Power Supply Block Diagram
DC-DC Converter Signals
........... .
Basic Positive Voltage Doubler
........ .
ADV 11-A A/D Conversion Circuit Block Diagram
A/D During Sample
A/D During Conversion . . . . . . .
~ Node During Conversion
.... .
ADVII-A Troubleshooting Procedure
AAV 11-A Troubleshooting Procedure
Floating the DVM . . . . . . . . . .

3-6
3-7
3-7

3-8
3-9
3-10
3-13
4-3
4-4
4-5
4-6
4-6
4-7
5-1

5-2
5-3
5-3
5-4
5-7
5-10
6-3
6-3
6-4
6-4

6-5
6-5
6-6
6-7

6-9
6-15

6-16

TABLES
Table No.
3-1
3-2

3-3
3-4
4-1
5-1
5-2

Title
KWV 11l-A CSR Bit Definitions
CSR Bit Settings for Mode 0, Single Interval
CSR Bit Settings for Mode 1, Repeated Interval
CSR Bit Settings for Mode 2, External Event Timing
AAV 11-A Digital-to-Analog Conversions
DRVll Input and Output Signal Pins
Word Formats . . . . . . . . . . . . .

vii

Page

3-11
3-14

3-15
. 3-16
4-8

5-5
5-8

TABLES (Cont)
Table No.
6-1
6-2
6-3
6-4

Title
ADV ll-A Voltage/Current/Bit Relationships
Jumper Configurations for Bipolar Operation
Jumper Configurations for Unipolar Operation
AAVll-A Input Code/Output Voltage Relationships

viii

Page
6-8
. 6-12
6-13
6-13

CHAPTER 1
INTRODUCTION

1.1 GENERAL
This manual contains information necessary for the operation, installation, and maintenance of the
family of real-time analog and digital I/0 devices which DEC provides as options for the LSI-II
Processor, i.e., the ADVII-A Analog-to-Digital Converter, the KWVII-A Real-Time Clock, the
AA VII-A Digital-to-Analog Converter, and the DR VI 1 Parallel Line Interface. Operating information for each device is provided in a chapter specific to that device which includes functional description, specifications, theory of operation, and programming background. Installation and maintenance
information is provided for all units in Chapter 6.

All members of the LSI-II real-time I/O family are designed to interface between the processor and
analog or digital signals in the world external to the processor. All devices are configured on one quad
or double-height board designed to mount in an LSI-II backplane or expander box and to receive
power from LSI-II supplies. All communicate with the LSI-II bus and receive interrupt priority as a
function of their location in the backplane. Finally, all have facilities to permit users to assign device
addresses, and where appropriate, interrupt vector locations.
A number of recommendations are made in this text regarding specific interfacing configurations and
general good practice. However, no specific interfacing claims are made over and above those
expressed in the general specifications for each module. The responsibility for connecting DEC modules to external equipment rests ultimately with the user.
1.2

•
•

REFERENCES
Microcomputer Handbook (EB-06583 76 09/53)
LSI-II Bus Specification

I-I

CHAPTER 2
ADVII-A ANALOG-TO-DIGITAL CONVERTER

2.1 GENERAL DESCRIPTION
The ADVII-A is a 12-bit successive-approximation analog-to-digital converter with built-in multiplexer and sample-and-hold for use on the LSI-II bus. The multiplexer section accommodates 16
single-ended or 8 quasi-differential inputs, and the converter section utilizes a patented auto-zeroing
design that measures the sampled signal with respect to the offset of its own internal circuitry and thus
effectively cancels out its own offset error contributions to the measurement.
AjD conversions are initiated either by program command, clock overflow, or external events as
determined by program control of the ADVII-A's Control/Status Register (CSR). The clock overflow
command is supplied by the KWVII-A clock option. External event inputs may originate directly
from user equipment or from the Schmitt trigger output on the KWVII-A clock. Digital AjD conversion data is routed through a buffer register to the LSI-II for programmed transfer into memory.
This buffering optimizes the throughput rate of the converter by allowing data from one conversion to
be transferred to the processor after a subsequent conversion begins.

A vernier offset digital-to-analog converter is included in the ADVI1.-A's analog circuitry to facilitate
very accurate program-controlled trimming of the AjD's offset. Three test signals - two dc levels and
one bipolar triangular waveform - are available for use on any channel input. The triangular wave can
be used in conjunction with diagnostic software and the vernier DAC to produce extremely thorough
and precise analog testing.
2.2

SPECIFICATIONS
Electrical (@ 25 0 C unless otherwise specified)

2.2.1
Inputs

Analog Input Protection

Fusible resistor guaranteed to open at ±85 V within 6.25 seconds. Guaranteed not to open from -20 V to + 15 V at the
input. Overload affects no components other than the fusible
resistor on the overloaded channel; no other channels are
affected.

Logic Input Protection

Fusible resistor guaranteed to open at ± 25 V within 6.25 seconds. Guaranteed not to open from -3 V to +8 V at the input.

Analog Input
Full Scale Range (FSR)

10.24 V bipolar (-5.12 V to +5.12 V)

2-1

Inputs (Cont)
Analog Input
DynamIc Resistance
(/Vin/ ~ 5.12 V)
Analog Input Bias Current
(/Vin/ ~ 5.12 V)

2.2.2

100 MQ, minimum
50 nA, maximum

Logic Input Voltages

Low = 0.0 to +0.7 V; high = +2 V to +5 V

Logic Input Currents

Low = -6.8 rnA at 0 V in.; high = +1.3 rnA at +5 V in

Logic Input Rise/Fall Time

400 ns, maximum

Coding

A/D Converter
Resolution

12 bits, binary weighted

Format

Parallel offset binary, right justified
Output Code

Input Voltage

7777
4000

+FS-l LSB

-FS

(FS = 5.12 V; 1 LSB = 2.5 mY)
Vernier D/A
Resolution

8 bits, binary weighted

Format

Offset binary encoded
Approximate Offset Voltage
+2.5 A/D LSB (+6.4 mY)

Input Code
377
200

o
2.2.3

-2.5 A/D LSB (-6.4 m V)

Performance
Gain Error

Adjustable to zero

Offset Error

Adjustable to zero

Differential Linearity

No skipped states; no states wider than 2 LSB. 99% of statewidths ± 1/2 LSB

I ntegral Linearity

± 1 LSB, maximum non-linearity (referenced to end points)

2-2

Performance (Cont)
Temperature Coefficients

Gain = 6 ppm per degree C
Linearity = 2 ppm of full-scale range per degree C
Offset = 7.5 ppm of full-scale range per degree C

Noise

Module = 0.4 LSB rms; 2 LSB peak
System = 112 LSB rms; 2 LSB peak

Warm-Up Time

5 minutes, maximum

2.2.4 Timing
External Start

Low level pulse, 50 ns minimum to 10 /J.S maximum; conversion
starts on leading edge

Synchronization

o to T

Conversion Time

16T
(T = clock period = 2.14 /J.S ± 6%)

Transition Interval·

9 /J.S ± 12%

Sample and Hold

Aperture Delay = 200 ns
Aperture Uncertainty = 2 ns

2.2.5 Test Signals
The ADVII-A provides three output voltages for test purposes:
1.

Positive de level, +4.4 V (± 15%)

2'.

Negative de level, -4.4 V (± 15%)

Triangular wave, 15 Hz nominal (± 15%)

2.2.6

Environmental (Ref: DEC STD 102, class B)

2.2.7

Power Requirements
+5 Vdc ±5% @2.0 A, maximum
+12 Vdc ±3% @450 rnA, maximum

2.3 FUNCTIONAL DESCRIPTION
The ADVII-A performs its function in seven successive steps:
I.

I t enables the specified channel.

It samples 1 of 16 single-ended (or 1 of8 differential) analog input channels specified by the
control program long enough to acquire a reliable internal reference equivalent.

It accepts a command to perform an AID conversion.

It holds the sarnpled reference equivalent during 12 successive interrogation intervals.

*Reacquisition interval between end of conversion or channel change and start of new conversion.

2-3

When the least significant bit has been resolved in the Successive Approximation Register
(SAR), the ADVII-A transfers the contents of the now-filled SAR to the DATA Buffer
Register (DBR) where that data can be accessed by the processor.

It informs the processor that conversion data is available.

It reacquires and tracks the programmed channel.

These steps are implemented in the ADVII-A by components that can be grouped together in four
functional categories:
I.

Channel selection

A/D conversion

Processor / ADVII-A interface

Control logic that coordinates the above steps with respect to one another and to the needs
of the processor.

These categories are discussed below.

2.3.1 Channel Selection
Channel selection is accomplished under program control by two 8-channel multiplexers and is a
function of the data asserted in bits 8 through 11 of the Control/Status Register (CSR). Each of the 16
analog input channels is routed to the single output channel through a MOS field-effect transistor
which acts as a normally-open switch. During the sample interval, the data pattern in CSR bits 8
through 11 selects one of these transistors and causes it to change from a condition of nearly infinite
resistance (1 GO or more) to one of very low resistance (1000 0 or less). Since in the selected state the
transistor conducts current within the ±5.l2 V limits equally well in both directions, it now functions
as a closed switch, effectively routing to the output line whatever analog signal is connected to its
input.
2.3.2 A/D Conversion
A/D conversions can be initiated in three ways: under program control, on overflow from the
KWVI1-A Real-Time Clock, or on external input. When a conversion is ~ompleted or the control
program writes a mUltiplexer address into the CSR, the control logic initiates the Transition Intervala delay of about 9 J.LS to allow the multiplexer adequate selection and settling time and to permit a valid
representation of the signal level to be established in the sample circuit. If no AjD Start signal has
occurred by the time the Transition Interval has elapsed, the sample circuit merely follows the signal
transmitted to it through the selected multiplexer channel and waits for an AjD Start signal. When an
AjD Start signal occurs - or at the end of the Transition Interval if AjD Start was previously generated by the writing of the CSR GO bit - the sample and hold circuits are switched to hold, sustaining
the sampled level for the next step. The multiplexer output is then set to its hold condition, i.e., to
ground if the single-ended (S.E.) input is set low for single-ended measurement, to the second differental input (return line) if the S.E. input is not set low. Note that if an external or clock start signal occurs
during the Transition Interval, conversion starts immediately without waiting for the Transition Interval to be completed. Bit 15 of the CSR (AD ERROR) is set, however, and an interrupt is generated if
bit 14 (error interrupt enable) is set - alerting the program that conversions are occurring too fast and
are consequently liable to be in error.

2-4

rcH:;;N~ ;;L~~ -

LOW CHANNEL
SELECT

AUTO-ZERO
SWITCH

I
I
II

CH 0:7
ANALOG
INPUTS(S)

r,--------------------,I

I A-D CONVERSION
I
I
I

COMP H

SAMPLE a HOLD
COMPARATOR

HOLD

CH 10:17
ANALOG
INPUTS (S)

II
I
I
I
I
I
I
I
I

________ ...1

tv
I
VI
LOW
CHANNEL
SELECT

HIGH CHANNEL

L ___ ~~ ____ J
r-----1

HIGH
CHANNEL
SELECT

MISC.
CONTROL
LOGIC

LOW ENABLE
HIGH
ENABLE
ADZC L
HOLD

TRANSCE I VER
CNTL
VECTOR H
1-1

...J

I
I
I
I
I

I
II

I
I
BUS MONITOR

a CONTROL LINES
II -4165

Figure 2-1

ADV ll-A Functional Block Diagram

Under normal conditions, it is not until the Transition Interval is complete that the measurement
process is begun. The Successive Approximation Register (SAR) is cycled through 13 states by the
clock. In the first state its output code involves only the most significant bit (MSB) of the 12-bit SAR
word. This output code causes the feedback digital-to-analog converter (DAC) to generate an output
equivalent to that produced by the hold circuits in response to a sample voltage of O. The DAC output
is summed with that produced by the hold circuits and with that coming from the grounded multiplexer output (single-ended mode) or from the second differential input (quasi-differential mode). If
the current from the summing node is negative, the first approximation was too low, and the comparator signals the SAR to maintain the state of bit 11 and repeat the process with bit 10. If the current
from the summing node is positive, the first approximation was too high and the SAR changes the
state of bit II before cycling into the second approximation. This process continues until all 12 bits in
the word have been set, tested, and if necessary, changed. The 13th state (end of conversion, or EOC)
indicates that the measurement is complete and that the SAR now contains an offset binary equivalent
of the sampled voltage and may therefore be transfered to the processor. EOC causes the sample and
hold circuits to return to the sample mode and to reset the SAR, preventing further SAR activity until
the occurrence of the next hold condition.
Note that because the reference point against which the sample voltage is compared is at the output of
the multiplexer itself rather than internal to the sample and hold circuits, all offset voltages generated
by the intervening circuits are common to both sample and hold conditions and are therefore cancelled
out of any measurement. In single-ended mode, grounding the multiplexer output (and thereby establishing this reference point) is identified as auto-zeroing the converter.

2.3.3 Interface Functions
In addition to stopping the SAR clock and reestablishing the sample mode, the end-of-conversion
signal also initiates the process that causes the SAR data to be transferred to the processor. Since this
operation takes a finite amount of time which would interfere with subsequent measuring operations,
the SAR data is first transferred to a holding device, the Data Buffer Register (DBR), where it will
remain until the processor can be notified to read the conversion data for processing. In the meantime,
the channel selection and A/D conversion circuits can begin the next measurement as dictated by
Control/Status Register (CSR) bit conditions controlled by the processor.
Included in the ADVII-A interface is an extension of the DBR designed to accept 8-bit write information from the BUS DATA/ADDRESS lines. This buffer permits programmed setting of the Vernier
DAC (see Paragraph 6.2.2.3). Also included are transceivers that connect the bi-directional BUS
DATA lines to the LSI-II Bus DAT A/ ADDRESS lines. Associated with these transceivers are switches that permit assigning device and vector addresses to any given ADVII-A.

2.3.4 Control
As the above discussion suggests, a large number of signals must be precisely orchestrated each time
the ADV II-A executes a conversion. The control logic contains an assortment of gates, latches, readonly memories, and timing circuits designed to assure that multiplexer channels are properly selected,
sample durations are of adequate length, conversions are not initiated during uncompleted previous
conversions, etc. In general, this logic precludes the need for the user to attend to any but the mostelementary details of the conversion process, e.g., making necessary connections to the system and
writing control programs that make appropriate use of the CSR.
2.4
2.4.1

USER INTERFACING
Analog Inputs

2.4.1.1 Single-Ended Mode* - Single-ended analog. input signals for the ADVVl1-A may be of two
types, grounded and floating. A grounded input is one whose level is referenced to the ground of the
instrument that is producing it, as illustrated in Figure 2-2. Since the instrument may be located at a
*The ADV Il-A is factory-set for differential mode. Single-ended mode must be selected as described in Paragraph 2.4.3.3.

2-6

distance from the computer, there may be some voltage difference between the instrument ground and
the computer ground. The voltage seen by the ADVII-A will be the sum of the undesired ground
differenc~ voltage and the desired instrument signal voltage. In cases where such differences are
encountered, they can be minimized by plugging the instrument into an ac outlet as close as possible to
that providing power to the computer. Do not run a wire from user's ground to the ADVII-A analog
ground. Such a wire can cause ground loop currents which affect results not only on the input channel
in question, but also on other channels.

r:;-11-:- - - - - ---,
I

ruS~';-;~R~ ~,:;,;,

I
I
I
I
I
I

SIGNAL

I
I
I

MUX
ADV11-A
GROUND

-I

L______ -1
=

L ______ _

USER'S
GROUND

I
I
I

_.J
=

COMPUTER
GROUND
11-4166

Figure 2-2

Single-Ended Input Referenced to User's Ground

A floating input is one whose signal voltage is developed with respect to a point not connected to
ground, as illustrated in Figure 2-3. The identifying characteristic of a floating source is that connecting the signal return to the ADVII-A ground does not result in a current path between the
ADV ll-A ground and the instrument ground.
Note that the return of a floating input must be connected to one of the ADVII-A's analog ground
terminals (see Figure 2-3)., Ground points may be shared among channels, as illustrated by the batterypowered sources in Figure 2-3.
2.4.1.2 Quasi-Differential Mode - The "quasi" prefix in "quasi-differential" can best be explained in
the context of a preliminary review of true differential operation. A true differential input involves two
signal lines connected to a differential amplifier in such a way that the output of the device is a function
of the instantaneous difference between the voltages on the two signal lines. One advantage of such a
configuration is illustrated in Figure 2-4.
Figure 2-4(a) assumes a single-ended generating device that produces a signal, Vs , with respect to its
ground and is situated sufficiently far from the receiving device for a significant noise voltage, Vn , to be
developed in the power distribution ground lines. The result is that, at any given instant, the differential amplifier in the receiving device sees both the signal voltage and the noise voltage. Its output, Yo, is
a function of Vs + Vn and is in error with respect to Vs alone.
2-7

r---------l
FLOATING SOURCE
SIGNAL -.

RETURN

:X,

I CHAN 00
I CHAN 01

I CHAN 02
I CHAN 03

I CHAN 04

LOW
MUX

I CHAN 05
I CHAN 06

BATTERY POWERED
SOURCE

I CHAN 07
SIGNAL ,RETURN ;(
SIGNAL ;-~,

CHAN 10

I CHAN 11

I CHAN 12

I CHAN 13
I CHAN 14

INSTRUMENT WITH
ISOLATION TRANSFORMER AND
FLOATING SECONDARY

HIGH
MUX

CHAN 15

• CHAN 16

I CHAN 17

..
SIGNAL ,.
,I

RETURN / ,

HO GROUND

ANALOG
GROUND

IL _________

COMPUTER _

G~~J

11-4167

Figure 2-3

Floating ADVII-A Input Signals

Figure 2-4(b) illustrates the same device connected in true differential mode. The same noise voltage
exists in the power distribution ground system, but this time the generating device ground is connected
directly to the negative input of the receiving differential amplifier. Since the instantaneous noise
voltage is common to both the + and the - inputs, it is cancelled out of the final amplifier output. Vo
now provides a valid representation of Vsalone.
Figure 2-5 illustrates the ADVII-A operating in the quasi-differential mode.
The major contrast between true differential operation as described above and the operation of the
ADVII-A in differential mode is that in the latter, the two sides of the signal are not simultaneously
input to a differential amplifier. Rather, their difference is established by a sequential operation that
first samples the voltage at one of the two inputs and then, holding this value fixed, in effect subtracts
from it the voltage at the second input. For near dc conditions, this procedure produces a result like
that of true differential operation - that is, the output is a function of the difference between the two
input voltages, and common mode voltages are cancelled out. But, since there is a significant time
lapse between taking the sample and completing the final approximation, a possibility for error is
introduced by the ADVII-A that increases as a function of common mode signal frequency. The result

2-8

is that the common mode rejection ratio, while essentially infinite at dc, rolls off for ac signals, and is
about 40 dB at 60 Hz line frequency. In addition, since the holding action of the sample-and-hold
circuit is only in effect on the first (non-inverting, signal) input but not on the second (inverting,
return) input, the voltage rate of change on the second input should be kept below 25 mV /ms. This is
the slope that results in a quarter-LSB change during the conversion interval. Such a rate of change
corresponds to 125 mV peak-to-peak at 60 Hz line frequency. This dynamic response difference
between the two inputs requires us to distinguish the ADVI1-A's differential mode from true differential operation. Hence the term "quasi-differential."

GENERATING

RECEIVING DEVICE

DEVICE

r----l
I

r------l
I v,
I

I
I

__ J

L_____ J

- - - - - ~8~
,_I - - - - o. SINGLE-ENDED MODE (VO=Vl+V n )

r------l

GENERATING DEVICE

r----l

I
I
I

-=~ __ ~~>_--- L~

L _____

'-'

I
Va

-r--

b. TRUE DIFFERENTIAL MODE (Vs =V, +Vn-Vn )
11-4168

Figure 2-4

Single-Ended Versus True Differential Input Modes

2.4.2 Avoiding Spurious Signals
As a preliminary step, confirm that the computer power supply ground is connected to power line
(earth) ground. If continuity checks reveal no such connection, attach a length of 12-gauge wire
between the power supply ground and a convenient point associated with earth ground. (All DECLAB
11/03 systems are provided with this connection at the factory.)
2.4.2.1 Twisted Pair Input Lines- The effects of magnetic coupling on the input signals may be
reduced for floating single-ended or differential inputs by twisting the signal and return lines in the
. input cable. If the inductive pickup voltages of the two leads match, the net effect seen at the ADVII-A
input is zero. Use of twisted pairs has no effect with a single-ended non-floating signal (referenced to
ground at the instrument end).
2-9

r----------------------,
COMP H

LOW MUX

~~-~~"~

GENERATING DEVICE

'----l

SAR

SAMPLE a HOLD
COMPARATOR

DAC

I
I
I

HIGH MUX

01 G I TI Z ED
DATA (V o )

I
I
I
I
I
I
I
I
I

I
I ______________________ JI

tv
I

--------------~-----------

'-"

COMPUTER GROUND
FOR dc CONDITIONS:
Vo = VI - V2 = (Vs + Vn ) -Vn

= Vs

FOR ac CONDITIONS:
Vo = VI (tl) - V2 (t 2 ) = Vs (t I ) + [ Vn (t I ) - Vn (t 2 ) ]
NOTE:
Solid switch positions indicate somple state (t1); dotted positions indicote hold state (t2)
11-4169

Figure 2-5

ADVII-A Quasi-Differential Mode

2.4.2.2 Shielded Input Lines - The effects of electrostatic coupling on the input signals may be reduced by shielding the signal wires. This is especially important if the instrument or transducer has high
source impedance. To prevent the shield from carrying current and thus developing ground loop
voltages within the ADVII-A, connect it to ground at the instrument end only.
2.4.2.3 Allowing for Input Settling with High Source Impedance - All solid-state multiplexers inject a
small amount of charge into their input lines when changing channels, causing a transient error voltage
that is discharged by the input signal's source impedance. The ADVII-A shares this characteristic, and
also injects a small charge into the selected input line at the end of each conversion when the auto-zero
switch is turned off (see Paragraph 2.3.2). After any channel change and after any conversion, the
ADVII-A's control logic allows a 9 J.LS interval (identified as the Transition Interval) during which
conversions cannot start without generating error conditions. Normally, this is sufficient time for the
input transient to settle out. However, more time may be needed when the mUltiplexer is switching into
an input channel with high source impedance, particularly when large amounts of shunt capacitance
exist in the interconnecting cables. Source impedance/cable shunt capacitance products greater than 1
J.Ls should be avoided whenever conversions are to be made at maximum rate with less than 1/2 LSB
error. This means that cable shunt capacitance for a 100012 source should not exceed 1000 pF (10 3 X
10- 9 = 10- 6 ), that shunt capacitance for a 10012 source should not exceed 0.01 J.LF (10 2 X 10-8 = 10-6 ),
etc. Assuming twisted pair cable capacitance of 50 pF /foot, these constraints translate into a maximum run of 20 feet froml a 1000-12 source, 200 feet from a 100-12 source, etc. Note that these values are
consistent with good practice for avoiding noise pickUp in long cable runs. Note also that settling
errors can be eliminated by increasing the time between conversions or incorporating a software delay
between channel changes and program start commands.
2.4.3 Connections
Figure 2-6 illustrates the location of user connectors and switches on the component side of the
ADVI1-A board.
Analog input signals are input to the ADVII-A through the 40-pin connector. Pin assignments for the
connector are shown in Figure 2-7. The proper Berg-to-Berg cable is the BCOSR; the proper Berg to
prepared open-ended cable is the BC04Z. (See Maintenance chapter for further information.)
2.4.3.1 Distribution Panel - Figure 2-S shows an H322 Distribution Panel that is connected on the
rear to the ADVl1-A Berg connector and on the front provides easily identifiable and conveniently
accessible barrier strip connections for user apparatus. Each H322 accommodates two ADVII-As or
one ADVII-A and one other single-connector device. The ADVII-A is shipped with decal sets that
specifically identify ADVll-A inputs and outputs. Note that the H323-B Potentiometer Box may not
be used with the A DVII-A. (See Maintenance chapter for appropriate potentiometer box circuit.)
2.4.3.2 External and Clock Starts - The external start signal line, pin B of the Berg connector or TAB
S (see Figures 2-6 and 2-7), is a TTL-compatible input that presents five unit loads (S.O rnA) to any
driving output. Conversions start on the high-to-Iow transitions of this signal.
In most cases, the external start signal will be produced by a grounded (non-floating) pulse generator
or logic circuitry located in a grounded instrument. The return path for the External Start signal will be
through the power line ground system. For this reason, ground differences between source and computer should be minimized to prevent spurious start pulses due to ground noise. In no case should a
separate return line be run between grounded source and the computer ground. Only with floating
devices should return lines be run between source logic ground and logic ground pins on the ADVII-A
Berg connector. External devices that require buffering can be interfaced to the ADVII-A through
Schmitt Trigger 1 of the KWVI1-A clock (STl). Connection is made by means ofa DEC 7010771 type
jumper (Figure 2-9) to TAB S (Figure 2-6) of the ADVI1-A.

2-11

SI NGLE-ENDED
JUMPER LUGS

c~~~_noo
OFFSET
ADJ

ADDRESS
SWITCHES

BIT2~

[BIT3
S1

P'Q.-TAB C
(CLOCK
S C
OVERFLOW
IN)

S2
BITS
<1>

"-GAIN
ADJ

VECTOR
SW ITCHES

TAB S
(EXTERNAL START)

BIT 11

,,- 4322

Figure 2-6

ADVII-A Connectors and Switches

Conversions that must be initiated in consequence of time intervals or on every nth external event may
be triggered from the KWVII-A through a DEC 7010771 type jumper connected from the clock
output tab (CLK) to the ADVII-A clock overflow tab (C).
2.4.3.3 Mode Control - The ADVII-A is equipped with jumper lugs (see Figure 2-6) that permit
changing operating mode from quasi-differential (no connection) to single-ended (jumper installed).
The single-ended mode can also be selected by connecting Berg connector pin C to logic ground. This
alternative is provided to permit convenient external mode selection in installations that require frequent alternation between one mode and the other.
2.4.4 Vector and Address Selection - Device and vector addresses are assigned to the ADVll-A by
means of two switch packs (S2 and S 1, Figure 2-6). S2 is a pack containing 10 single-pole/single-throw
switches, numbered 1-10, that communicate with data lines BDAL 2-11. Assuming BDAL lines 12-15
to be set by the processor to 1, SI permits assigning any address between 170000 and 177774. The
recommended address for the ADVII-A Status Register is 170400, set as illustrated in Figure 2-10(a).
The Data Buffer Register automatically receives the next even address following that assigned to the
CSR.

2-12

LOGIC GND

-b
A

SI NGLE EN OED L

ANALOG GND

'"
,...

P
ANALOG GND

AA
CC
EE
HH

,...

JJ
LL

+ 15V TEST

,...

-15V TEST

EXT START L

+4 .5V

RAM P
- 4. 5V
CH 17

-CH 07

CH X7

CH 16

-CH 06

CH X6

CH I 5

-CH 05

CH X5

CH I 4

-CH 04

CH X4

CH 07

+CH 07

CH 07

CH 06

+CH 06

CH 06

CH 05

+CH 05

CH 05

CH 04

+CH 04

CH 04

CH 13

-CH 03

CH X3

CH 12

- CH 02

CH X2

CH 1

- CH 01

CH XI

CH I o

- CH 00

CH XO

CH 03

+CH 03

CH 03

CH 02

+CH 02

CH 02

CH 01

+CH 01

CH 01

CH 00

+CH 00

CH 00

SINGLE
ENDED

DIFFERENTIAL

H322
NOMENCLATURE

BOARD SIDE
11· 4170

Figure 2-7

ADVll-A 40-Pin Connector Pin Assignments

8201

Figure 2-8

H322 Distribution Panel

The AjD done interrupt vector address is set by means of Sl, an 8-switch pack of which only six
switches are utilized. These switches communicate with BDAL lines 3 through 8 and can be set in
increments of lOs. The error interrupt vector automatically receives an address that is four locations
higher than the AjD done interrupt vector whose recommended address is 000400 [see Figure 2-l0(b)].

2-13

M-0599

Figure 2-9
2.5

Module Jumpers

PROGRAMMING

2.5.1 Control/Status Register (CSR)
The significance of the CSR bits is defined below:
Bit 15: A/ D ERROR (Read/ Write) - The AID ERROR may be program set or cleared and is cleared
by the processor INITIALIZE. It is set by any of the following conditions:

Attempting an external or clock start during the transition interval (see Paragraph 2.3.2)

Attempting any start during a conversion in progress

Failing to read the result of a previous conversion before the end of the current conversion.

Bit 14: ERROR INTERR UPT ENABLE (Readl Write) - When set, enables a program interrupt upon
an error condition (AID ERROR). Interrupt is generated whenever bits 14 and 15 are set, regardless
of which was set first.
Bits 13-12: Not used.
Bits 11-8: MULTIPLEXER ADDRESS (Readl Write) - Contain the number of the current analog
input channel being addressed.
Bit 07: AI D DONE (Read) - Set at the completion of a conversion when the data buffer is updated.
Cleared when the data buffer is read and by the processor INITIALIZE. If enabled interrupts are
requested simultaneously by both bits 07 and 15, bit 07 has the higher priority.

2-14

Bit 06: DONE INTERRUPT ENABLE (Read/Write) - When set, enables a program interrupt at the
completion of a conversion (A/D DONE). Interrupt is generated when bit 07 and bit 06 are both set,
regardless of sequence.
Bit 05: CLOCK START ENABLE (Read/Write) - When set, enables conversions to be initiated by an
overflow from the clock option.
Bit 04: EXTERNAL START ENABLE (Read/Write) - When set, enables conversions to be initiated
by an external signal or through a Schmitt trigger from the clock option.
Bit 03: ID ENABLE (Read/ Write) - When set, causes bit 12 of the Data Buffer Register to be loaded
to a 1 at the end of any conversion.
Bit 02: MAINTENANCE (Read/Write) - Loads, when set, all bits of the converted data output equal
to Multiplexer Address LSB (bit 08) at the completion of the next conversion. Cleared by the processor
INITIALIZE. Used for "all Os" and "all Is" tests of AjD conversion logic.
Bit 01: Not used.
Bit 00: A / D START ( Read/ Write) - Initiates a conversion when set. Cleared at the completion of the
conversion and by the processor INITIALIZE.
o

r--"----. ,------A----.. ~ ,,----'A~.....,., ,-A-.,

OCTAL EQUIVALENT

CSR ADDRESS
SWITCH (S2)

BDAL BIT

i..--.l...-....L...-+-....L.-.....L....-+-....J....--I--+----'---'---+---I.---1---1......... POS I T I ON
BOARD
-HANDLE

BOARD
FINGERS -

o. CSR ADDRESS SWITCH (SET FOR 170400)

OCTAL EQUIVALENT

~ r~~~r--A---.,-A-.,

VECTOR
SWITCH (S1)

BDAL BIT

~"--"'--+-~-'---+-........--'--+---'---"---+---I.---I~~ POS ITI 0 N
*SWITCHES NOT CONNECTED
b. VECTOR ADDRESS SWITCH (SET FOR 000400)
11-4171

Figure 2-10 ADVII-A Address and Vector Switches (Rocker or Slide Switches)
2-15

ERR

NOT USED

MUX ADDRESS
READ IWRITE

DONE
1NT ENA

ERR
1NT ENA

AD
DONE

MAINT

EX
START
ENA

elK

START
ENA

ENA

AD
START

NOT USED

11-4311

Figure 2-11

ADVII-A Control/Status Register (CSR)

VERNIER D/A (WRITE)
A.

1'5 ,'4 1

1'2

MSB

lSB

09, 08 I 07 I 06, 05 I 04 I 03, 02 I 0'

-y,,__________________~lS~B,

~~M~S~B__________________

CONVERTED DATA (READ)
11-4312

Figure 2-12

ADVII-A Data Buffer Register (DBR)

2.5.2 Data Buffer Register (I1BR)
The DBR is actually two separate registers - one read only, the other write only.
Read Only (Cleared at processor initialize)
Bits 15-13: Not used. Should read as O.
Bit 12: ID (Read) - When ID ENABLE (bit 03) of the CSR has been set, DBR bit 12 will be
loaded to a 1 at the end of conversion .
. Bits 11-410: CONVERTED DATA (Read) - These bits contain the results of the last AID
conversion.

Write Only (Set to 2008 at processor initialize)
Bits 15-418: Not used.
Bits 07-410: VERNIER D/ A (Write) - These bits provide a programmed offset to the converted
value (scaled 1 D/A LSB = 1/50 AID LSB). The hardware initializes this value to 2008 (midrange). Values greater than 2008 make the input voltage appear more positive.

2-16

2.5.3 Programming Example
Read 1008 AID conversions from channel 0 into locations 40008-41768 and halt.

START:
LOOP,

AOSRI
ADB~I

CLR

(lADSP

MOV

.4000,~O

INC
T518
BPL
INC
MOV

IAOSP
LOOP
'AOSR
(lAOBP.,(RO)+

CMP

RO"4200

8NE

LOOP

,CLEAR AID STATUS REGISTE~
,SFT UP FIRST ADDRESS
,START AID CONVE~SION
,CHECI< DONE FLAG
,WAIT U~TIL fLAG SET
,5TAPT NEXT CONVERSION*
,PLACE CONVEPTED VALUE
,FPOM AID AUFFEF INTO ~EMOPY
,LOCATION AND SET UP NEXT
,LOCATION FOR TRANSFEP*
,CHECK IF 100 CONVE~SIONS
,HAVE BEEN cnNE
,NO, GET NEXT CONV~RSION

~ADS""

HALT

,DONE
,AID STATUS REGISTER ADDRESS
,AID BUrrER REGISTEP ADDRESS

1'0400
170402

.END

START

·Starting a subsequent conversion before moving data from a previous conversion is to be recommended only
with systems equipped with non-processor memory refresh, as provided in the REVII options. Without this
capability, data will be lost occasionally by CPU memory refresh intervening between the INC and MOV commands. In general, non-processor memory refresh is essential to realizing the full potential of the ADVII-A.

2-17

CHAPTER 3
KWVII-A PROGRAMMABLE REAL-TIME CLOCK

3.1 GENERAL DESCRIPTION
The KWVII-A is a programmable clock/counter combination that provides a variety of means for
determining time intervals or counting events. It can be used to generate interrupts to the LSI-II
processor at predetermined intervals, to synchronize the processor to external events, or to measure
time intervals or establish programmed ratios between input and output events. It can also be used to
start the ADVII-A Analog-to-Digital Converter either by clock counter overflow or by the firing of a
Schmitt trigger.
The clock counter has a resolution of 16 bits and can be driven from any of five internal crystalcontrolled frequencies (100 Hz to I MHz), from a line frequency input or from a Schmitt trigg~r fired
by an external input. The K WVII-A can be operated in any of four programmable modes: single
interval, repeated interval, external event timing, and external event timing from zero base.
The K WV II-A includes two Schmitt triggers, each with integral slope and level controls. The Schmitt
triggers permit the user to start the clock, initiate A/D conversions, or generate program interrupts in
response to external events.
The physical structure of the KWVII-A is illustrated in Figure 3-1. The unit is contained on one quad
size module whose fingers interface to the LSI-II Bus. User interfacing for the Schmitt triggers and
clock overflow signals is accomplished by means of a multi-pin connector (JI ). FAST ON connectors
(CLK, STI) are provided to permit direct and simple connections of clock overflow and Schmitt
trigger outputs to corresponding terminals on the ADVll-A A/D Converter. Switch packs permit
selecting CSR (Control/Status Register) address, interrupt vector address, and Schmitt trigger slope
and level conditions. Screwdriver controls (R 18 and RI9) permit setting Schmitt trigger levels. Provision is also made via the multi-pin connector JI for external user-provided slope switches and level
controls.

3.2
3.2.1

SPECIFICATIONS (@ 25° C unless otherwise specified)
Clock
Oscillator Accuracy

0.01%

Range

Base frequency (10 MHz) divided into five selectable rates
(I MHz, 100 kHz, 10 kHz, I kHz, lOa Hz); line frequency;
Schmitt trigger 1 input

3.2.2 Input and Output Signals
All inputs and outputs are TTL compatible unless otherwise specified.

3-1

CLK STI

~R18

~R19

BIT 11

BIT 2

o 00

ADDRESS
SWITCHES

BIT 8

BIT 3

VECTOR
SWITCHES

11-4318

Figure 3-1
3.2.2.1
I.

KWVII-A Connectors, Switches, and Controls

Input Signals
STI IN (Schmitt Trigger I Input)
Input Range
(maximum limits)
Assertion Level

-30 V to +30 V

Origin

User device

Response Time

Depends upon input waveform and amplitude; typically
600 ns with TTL logic input

Hysteresis

Approximately 0.5 V, positive and negative

Characteristics

Single-ended input; 100 kn impedance to ground

Depends upon position of slope reference selector switch
and level control; triggering range, -12 V to + 12 V

ST2 IN (Schmitt Trigger 2 Input)
Same description as STI IN

3-2

3.2.2.2
1.

Output Signals
CLK OV (Clock Overflow)
Asserted Level

Low

Destination

User device or ADVII-A

Duration

Approximately 500 ns

Characteristics

TTL open-collector driver with 470 n pull-up to +5 V
Maximum source current from output through load to
ground when output is high (~ 2.4 V): 5 rnA
Maximum sink current from external source voltage
through load to output when output is low (~0.8 V): 8 rnA

ST lOut (Schmitt Trigger 1 Output)
Same description as CLK OV

ST2 OUT (Schmitt Trigger 2 Output)
Same description as CLK OV

3.2.2.3 Environmental (ref: DEC STD 102, class C)
3.2.2.4 Power Requirements (from LSI-II Bus Power Supply)
+5 V
+ 12 V

3.3
3.3.1

l. 75 A typical
10 rnA typical

F'UNCTIONAL DESCRIPTION

Bus Control

Figure 3-2 illustrates the KWVII-A in block diagram form.
The logic associated with the bus control block maintains proper communications protocol between
the processor bus and the KWVll-A. This logic generates and monitors the bus signals involved
during interrupts and data transfers between the processor and the KWVII-A. It permits the KWVllA to recognize when it is being addressed by the processor (address defined by the Address Switch
Pack), to prescribe the location in memory pointing to the starting addresses of interrupt service
routines (by means of the Vector Address Switch Pack), to input control data from the processor, and
to output data to the processor.
I nterrupts can be enabled for both counter overflow and operation of ST2. Since each of these conditions raises a flag bit in the Control/Status Register, and since separate interrupt vectors exist for each
condition, the conditions may be distinguished either by vectors or by testing flag bits.

3.3.2

Control/Status Register

The Control/Status Register (CSR) provides a means for the processor to control the operation of the
KWVII-A and to derive information about its operating condition. Bits are provided for enabling
interrupts, mode selection, maintenance operations, starting the counter, and overflow and Schmitt
trigger event monitoring . (See Figure 3-9 and Table 3-1.)
3-3

COUNTER

RR
(J 1 )

CLK

SEL CLK H

ADDRESS Ii
TIMING CONTROL

BEVNT L

*
V

STI IN

SCHMITT TRIGGERS

STI

~.ST LEV 1

(JIl

~. ST LEV 2
TTST2 IN

(Jl )

f ""

ST2 OUT L HH

(J 1)

:---..,ST SLOPE 1

ST1 H

*" MISCELLANEOUS
INTERNAL CONTROL
SIGNALS

ST SLOPE 2

11-4174

Figure 3-2

K WV ll-A Real-Time Clock Block Diagram

3.3.3 Mode Control
Logic circuitry associated with the mode control block permits KWVI1-A operation in four different
modes as specified by bits 2-1 of the CSR.
3.3.3.1 Mode 0 (Single Interval)
When the GO bit is set in this mode either by the processor or by a Schmitt Trigger 2 event, the counter
is loaded from the Buffer/Preset Register (which has previously been loaded with the 2's complement
of the number of counts desired before overflow). Once loaded, the counter will increment at the
selected rate until it overflows. Overflow clears the GO bit, sets the Overflow Flag, and interrupts the
processor if that function has been enabled. If interrupt has not been enabled, the KWVII-A waits for
processor intervention.
3.3.3.2 Mode 1 (Repeated Interval)
When the GO bit is set in this mode, the counter is loaded from the Buffer/Preset Register (BPR) and
is then incremented to overflow as for Mode O. In Mode 1, however, overflow does not clear the GO
bit; instead, it causes the counter to be reloaded from the BPR, raises the Overflow Flag, initiates an
interrupt sequence if the CSR Interrupt on Overflow bit is set, and causes the count to be continued
with no loss of data.

3-4

3.3.3.3 Mode 2 (External Event Timing)
When the GO bit is set in this mode, the counter is set to 0 and then incremented at the selected rate as
long as the GO bit remains set. An external signal to Schmitt Trigger 2 (ST2) causes the current
contents of the counter to be loaded into the BPR while the counter continues to run. At the same time
the ST2 Flag is set and, if Interrupt 2 is enabled, an interrupt is generated, thus permitting the program
to read the value held in the BPR.
The counter continues to run after the ST2 event and also continues to run after overflow. Interrupt on
Overflow may be enabled to alert the program to the overflow condition.
3.3.3.4 Mode 3 (External Event Timing from Zero Base)
Operation in Mode 3 is identical to that in Mode 2 except that the counter is zeroed each time an ST2
event loads its contents into the BPR.
3.3.3.5 Flag Overrun
I n all modes, if a second overflow occurs before the Overflow Flag is reset (Le., before a prior event is
serviced by the processor), or if ST 2 fires when the ST 2 flag is already set, the Flag Overrun bit is set.
3.3.4 Oscillator, Divider, Rate Control Chain
The circuitry associated with these blocks provides the time base that is fed to the counter. The
K WV II-A permits eight clock conditions to be specified by bits 5-3 of the CSR: STOP, I MHz,
100 kHz, 10 kHz, I kHz, 100 Hz, an external time base applied to STI, and line frequency (50 or 60
Hz) picked up from bus line BEVNT. External periodic or aperiodic pulses may be applied to STI and
counted, provided they meet the criteria in Paragraphs 3.2 and 3.3.6.
3.3.5 Buffer /Preset and Counter Registers
The Buffer/Preset Register is a word-oriented, 16-bit read/write register that can be loaded either
under program control or from the counter. In Modes 2 and 3, the firing of ST2 causes the BPR to be
loaded with the contents of the counter. The BPR cannot be loaded by the program in these modes as
long as the GO bit is set.
The counter is a 16-bit internal register accessible only by way of the BPR; in Modes 2 and 3 it can be
read indirectly through the BPR.
3.3.6 Schmitt Triggers
Both Schmitt triggers are equipped with switches to permit selecting slope direction (+ or -) and
threshold reference level (TTL or -12V to + 12V contin uously variable). Each Schmitt trigger is also
equipped with a screwdriver-operated potentiometer to permit setting the variable threshold level.
Switch-pack and potentiometer terminals are all brought to mUltiple connector 11 to permit attachment of external user-provided slope and level controls. (See Figure 3-3.)
The two Schmitt triggers are used in somewhat different ways:
STI - Performs as an external time base input or external input for aperiodic signals to be
counted. Outputs both to STI FAST ON connector to provide external start signals to ADV ll-A
and, through rate control circuitry, to permit selection as input to the counter. Maximum frequency varies as a function of input waveform.

S T2 - When the ST2 GO ENABLE bit is set, firing ST2 in any mode sets the GO bit and initiates
counter action, causes the ST2 Flag to be asserted, and generates an interrupt if that function is
enabled. When the GO bit is set in Modes 2 and 3, firing ST2 causes the Buffer/Preset Register to
be loaded from the counter, the ST2 Flag to be set, and an interrupt to be generated if enabled.

3-5

J
EXT. STt
LEVEL POT
(5 - 20K)

EXT. ST2
LEVEL POT
(5- 20K)

NN OR PP
(BOTH ARE GND.)

EXTERNAL
SLOPE 1
SWITCH
52

-----0-

--=

EXTERNAL
SLOPE 2
SWITCH

BO ARD
HA NDLE

OFF
ON
OFF
OFF
OFF
UNUSED

BO ARD
FIN GERS

NOTE:
For proper operation of external level controls, both RI8 and R19
on KWVll- A board must be set to approximate mid· pOint of
rotation, and the 52 switches must be set as shown.

Figure 3-3

11- 4337

Connecting External User-Supplied Slope and Level Controls

3.4 CONNECTORS, SWITCHES, AND CONTROLS
Figure 3-1 illustrates the location of user connectors, switches, and controls on the component side of
the KWVII-A board.
3.4.1 40-Pin Connector
Figure 3-4 illustrates the 40-pin connector pin assignments for user inputs and outputs. These pins may
be connected to the optional H322 Distribution Panel· (see Paragraph 2.4.3.1) for convenient external
user access. The proper Berg-to-Berg cable is the BC08R. The proper Berg to prepared open-ended
cable is the BC04Z.
3.4.2 FAST ON Connectors (Clock Overflow and STI Outputs)
Two FAST ON connector tabs labeled CLK and STI are situated in the upper-right corner of the
K WV I1-A board (see Figure 3-1). These tabs are electrically in parallel with pins RR (CLK OV L) and
UU (STI OUT L) on the 40-pin connector and are intended to facilitate connections by means of
module jumpers (shown in Figure 2-9) to the clock overflow and external start inputs on the ADVII-A
(see Paragrapgh 2.4.3).
3.4.3 Selector Switches (Address, Vector, and Slope/Reference Level)
Figure 3-1 identifies three switch packs (SI, S2, and S3) that the KWVII-A provides to facilitate the
selection of CSR address, vector address, and slope/reference level conditions for Schmitt Triggers 1
and 2.
·The KWVII-A is shipped with decals which permit permanent identification of signal lines associated with H322 terminals.

3-6

0
F

E
H

POT 2

+3V

POT 1
SLOPE 2
SLOPE 1

CC
~

~
~

ST 2 OUT L
ST 10UT L

RR
TT

UU
~

ClK (N l

ST 2 IN
ST 1 IN

11-4175

BOARD SIDE

Figure 3-4

40-Pin Connector Pin Assignments

3.4.3.1 Address Selection - Switch Pack SI contains 10 single-pole/single-throw switches that communicate with data lines BDAL 11-2. The KWVII-A reads the BDAL lines only in response to BBS7
which the processor asserts only for an address of 160000 or higher. For this reason, and because the
KWVII-A transceivers are hard wired to respond only when BDAL bit 12 is set to 1, SI permits
assigning the CSR any address ending in 0 or 4 between 1700008 and 1777748 • The recommended
address for the K WV II-A CSR is 170420, set as illustrated in Figure 3-5. The BPR automatically
receives the next even address following that assigned to the CSR.
1

OCTAL EQUIVALENT

(--"-.,----A---,,.---A-----,~,----A---,~

8DAl 81T

II--+---L..--L--II--..L..---L..-+--.I_-'---+----'----L_+-~.....r..~ POS I TI 0 N
BOARD FINGERS - - +

4 - - BOARD HANDLE

NOTE:
1. Switches may be of either
rocker or slide variety.

Figure 3-5

11- 4176

K WV II-A CSR Address Switches (Set for 170420)
3-7

3.4.3.2 Vector Selection - The clock overflow interrupt vector address is set by means of S3, a 7switch pack of which only six switches are utilized. These switches communicate with BDAL lines 8-3
and can be set in increments of 108 • The ST2 interrupt vector automatically receives an address that is
four locations higher than the clock overflow interrupt vector whose recommended address is 0000440
(see Figure 3-6).
o

OCTAL EQUIVALENT

,.....A-..~~~,---A----,~

I I I I I I I 11 I I 11 I I I I I I~?~I~:CUE
0

:~~~~~~ i
~~ lJ ~ ~ lJ ~

I I I I I I I I I I I I I I I I I~g~rT ~6~
'5.4

'2"

10 09: 08 07 06 05 04 03 02 O.

+ - BOARD HANDLE

BOARD FINGERS ----+
NOTE
1. Switches may be of either
rocker or slide variety.

Figure 3-6

11-4177

KWVII-A Vector Address Switches (Set for 000440)

3.4.3.3 Slope and Reference Level Selector Switches and Controls (See Figure 3-7) - Slope and reference level selection for STI and ST2 are accomplished by means of S2, a 7-switch pack of which only
switches 1-6 are used. Two reference modes are selectable for each Schmitt trigger - one that picks a
fixed level appropriate to TTL logic, and one that picks a variable level that permits setting the ST
threshold to any point between -12 and +12 V.
NOTE
User should take care that both TTL and variable
switches for either Schmitt trigger are not on simultaneously. This condition will do no damage to components, but produces unpredictable reference levels.
Note also that if no signal is connected to a Schmitt
trigger input, both threshold switches for that ST
should be open for noise immunity. Alternatively,
STI IN and ST2 IN can be grounded externally.
Slope selection is accomplished by separate switches for STI and ST2, respectively. When the related
switch is on, the firing point effectively occurs on the positive slope of the input waveform. When the
switch is off, the firing point occurs on the negative slope. (See Figure 3-8.)
3.5

PROGRAMMING

3.5.1 CSR Bit Assignments
CSR bit assignments are identified in Figure 3-9 and defined in Table 3-1.

3-8

OFF

~\ON

TTL REFERENCE

BOARD HANDLE

~JI-N} _ _ _

ST LEVEL I
(Jl-Ll
ST LEVEL 2
VARIABLE REFERENCE

-----

ST SLOPE 1 (JI-T)
RI8

ST SLOPE 2 (JI-R)

BOARD FINGERS

NOT USED
S2

~
11-4178

Figure 3-7

KWVII-A Slope/Reference Level Selector Switches and Controls

3.5.2 Buffer/Preset Register (BPR)
The BPR is a 16-bit, word-oriented, read/write register. Any attempt to write a byte into this register
will result in a whole word being written. In Modes 0 and 1 the program may load it with the 2's
complement of the number of counts desired before overflow. In Modes 2 and 3 it permits indirect
reading of the clock counter.

3.5.3

Normal Control Sequences

3.5.3.1 Mode 0 (Single Interval) - Control code for operation in Mode 0 must support the following
sequence:
I.

Control program writes desired count (2's complement) into BPR (see Paragraph 3.3.5).

Program writes control code into Control/Status Register as indicated in Table 3-2.

If GO bit is set high, KWVII-A responds by loading the 16-bit counter (see Paragraph 3.3.5)
from the BPR and enabling the counter; if GO bit is set low and ST2 GO ENABLE bit is set
high, KWVII-A waits for ST2 event, then sets the GO bit and loads and enables the
counter.

Counter increments until overflow, then halts (GO bit is cleared)

KWVII-A raises Overflow Flag and issues interrupt if the CSR INT OV bit is set; if interrupt is not enabled, KWVII-A waits for program intervention.

Program responds to interrupt or intervenes in consequence of other criteria (e.g., testing the
Overflow Flag or the A/D Done Flag if overflow was used to start an A/D conversion).
Program reads the CSR, clears the Overflow Flag, and if no counting or mode changes are
required, sets the GO bit or the ST2 GO ENABLE bit to reenter the sequence at step 3.

3-9

L
I

INPUT WAVEFORM

SELECTED TRIGGER
LEVEL
(RIB OR 19)

I
_ _ ..1..__ _

POSITIVE-GOING THRESHOLD
HYSTERESIS
"0.5V

I
I
I
I

NEGATIVE-GOING THRESHOLD

I
I
I
I
I

OUTPUT

-.I \.-

-..II.-

500 ns

NOTE:
ST is retriggered only ofter input waveform
has moved beyond opposite threshold and
then again passed selected threshold.
(0)

SLOPE SELECTION: SLOPE switch ON (Positive Slope)

W
I

INPUT WAVEFORM

SELECTED TRIGGER
LEVEL
(RIB OR 19)

HYSTERES IS
::::0.5V

OUTPUT

NOTE:

POSITIVE-GOING THRESHOLD

-..J I.-

NEGATIVE -GOING THRESHOLD

U
---..J \.- 500 ns

500ns

ST is retriCJQered only after input waveform
has moved beyond opposite threshold and
then OCJain passed selected threshold.
(b)

SLOPE SELECTION: SLOPE switch OFF (NeQative Slope)

11·4549

Figure 3-8

KWVII-A Slope Selection

Table 3-1
Bit

15 ST2 Flag
Read/Write to 0

14 INT 2
(INTERRUPT
ON ST2)

KWVI1-A CSR Bit Definitions

Set By /Cleared By

Remarks

Set by the firing of Schmitt Trigger
:2 or the setting of the MAINT ST2
bit in any mode while the GO bit or
the ST2 GO ENABLE bit is set.
Cleared under program control.
Also cleared at the" 1" -going transition of the GO bit unless the ST2
GO ENABLE bit has previously
been set.

Must be cleared after servicing an
ST2 interrupt to enable further
interrupts. When cleared, any
pending ST2 interrupt request will
be cancelled. If enabled interrupts
are requested at the same time by
bits 07 and 15, bit 07 has the higher
priority.

Set and cleared under program
control.

When set, the assertion of ST2 Flag
will cause an interrupt. If set while
ST2 Flag is set, an interrupt is
initiated. When cleared, any pending ST2 interrupt request will be
cancelled.

Set and cleared under program control. Also cleared at the" 1"-going
transition of the GO bit.

When set, the assertion of ST2 Flag
will set the GO bit and clear the
ST2 GO ENABLE bit.

Set when an overflow occurs and
the Overflow Flag is still set from a
previous occurrence, or when ST2
fires and the ST2 Flag is already
set. Cleared under program control
and at the" 1" -going transition of
the GO bit.

This bit provides the programmer
with an indication that the hardware is being asked to operate at a
speed higher than is compatible
with the software.

Set and cleared under program
control.

F or maintenance purposes, this bit
inhibits the internal crystal
oscillator from incrementing the
clock counter. Used in conjunction
with bit 10 below.

Set under program control. Clearing is not required. Always read as
a "0."

For maintenance purposes, setting
this bit high simulates one cycle of
the internal 10 MHz crystal
oscillator used to increment the
clock counter.

Set under program control. Clearing is not required. Always read as
a "0."

Setting this bit simulates the firing
of Schmitt Trigger 2. All functions
~initiated by ST2 can be exercised
under program control by using
this bit.

Read/Write
13 ST2 GO
ENABLE

Read/Write
12 FOR
(FLAG OVERRUN)

Read/Write

11 DIO
(DISABLE
INTERNAL
OSCILLATOR)
Read/Write
10 MAINT OSC
Write Only

9 MAINT ST2
Write Only

3-11

Table 3-1

KWVII-A CSR Bit Definitions (Cont)
Remarks

Bit

Set By/Cleared By

8 MAINT STI

Set under program control. Clearing is not required. Always read as

Write Only

a "0."

7 OVFLO FLAG

Set each time the counter overflows. Cleared under program control and at the" 1" -going transition
of the GO bit.

If bit 6 is set, bit 7 set will initiate an
interrupt. Bit 7 must be cleared
after the interrupt has been serviced
to enable further overflow interrupts. If cleared while an overflow
interrupt request to the processor is
pending, the request is cancelled. If
enabled interrupts are requested at
the same time by bits 07 and 15, bit
07 has the higher priority.

Set and cleared under program
control.

When this bit is set, the assertion of
OVFLO Flag will generate an interrupt. Interrupt is also generated if
bit 6 is set while OVFLO Flag is set.
If cleared while an overflow interrupt request to the processor is
pending the request is cancelled.

Set and cleared under program
control.

These bits select clock counting rate
or source.

----.-----------+--------------.----4----------.-----

Read/Write to 0

6INTOV
(INTERRUPT ON
OVERFLOW)
Read/Write

5:3 RATE
Read/Write

Setting this bit simulates the firing
of ST 1. All functions initiated by
ST 1 can be exercised under program control by using this bit.

5 4 3

Rate

a a 0 STOP
a 0 1 IMHz
a 1 a 100 kHz
a 1 1 10 kHz
1 a 0 1 kHz
I a 1 lOa Hz
1 I a STI
I

2:1 MODE

Read/Write

Set and cleared under program
control.
Mode 0:
Mode 1:
Mode 2:
Mode 3:

Read/Write

aGO

1 1 Line (50/60 Hz)

Set and cleared under program control. Also cleared when the counter
overflows in Mode O.

3-12

a a
a I
1 a
1

Setting this bit initiates counter
action as determined by the rate
and mode bits. In Modes 1,2, and 3
it remains set until cleared. In
Mode 0 it clears itself when counter
overflow occurs. Clearing bit 0
zeroes and inhibits the counter.

ST2
FLG

ST2
GO ENA
INT 2

DID
FOR

MAINT
ST2
MAINT
OSC

OVFLO
FLG
MAINT
ST1

RATE
2
INT OV

RATE
0
RATE
1

MODE
0
MODE
1

GO
11-4310

Figure 3-9

CSR Bit Assignments

3.5.3.2 Mode 1 (Repeated Interval) - Control code for operation in Mode 1 must support the following sequence:
I.

Control program writes desired count (2's complement) into the BPR.

Program writes control code into CSR as indicated in Table 3-3.

If GO bit is set high, KWVI1-A responds by loading the 16-bit counter from the BPR and
enabling the counter; if GO bit is set low and ST2 GO ENABLE bit is set high, K WV ll-A
waits for ST2 event, then sets the GO bit and loads and enables the counter.

Counter increments until overflow.

KWVII-A reloads counter from the BPR, reenables the counter, raises the Overflow Flag in
the CSR, and issues interrupt to the processor if interrupt is enabled.

If second overflow occurs before first is serviced (i.e., if Overflow Flag is still high when next
overflow occurs), KWVII-A Flag Overrun (FOR) bit in the CSR is set high to alert program that data has been lost.

Program responds to interrupt or intervenes in consequence of other criteria. Program reads
CSR, clears the Overflow Flag, and if no counting or mode changes are required, sets the
GO bit or the ST2 GO ENABLE bit to reenter the sequence at step 3.

3.5.3.3 Mode 2 (External Event Timing) - Control code for operation in Mode 2 must support the
following sequence:
1.

Program writes control code into CSR as indicated in Table 3-4.

KWVII-A responds by incrementing the counter (zeroed when the GO bit was cleared) at
the selected rate until the GO bit is set to O.

ST2 pulse loads current counter contents into BPR, sets the ST2 Flag, and generates interrupt if INT 2 is enabled.

Overflow sets OVFLO FLG high and, if INT OV bit is high, generates interrupt.

Counter continues to increment until processor sets GO bit to O.

Normally, program enables INT 2 and/or INT OV bits, permitting the processor to synchronize its
operations with the external ST2 events and prevent loss of data by reinitializing the process after step
4.

3-13

Table 3-2

CSR Bit Settings for Mode 0, Single Interval

Bit No.

CSR
Name

Bit Condition
as Written by
Processor

ST2 FLG

Will be set to 1 on ST2 event. Cleared
by leading edge of GO bit assertion
except when ST2 GO ENA has previously been set.

INT2

Set to 1 by program if interrupt on
ST2 event is desired.

ST2GOENA

Set to 1 by program if GO is to be set
by external signal to ST2. Cleared by
leading edge of GO bit assertion.

FOR

(0)

010

MAINTOSC

MAINTST2

MAINTSTI

OVFLOFLG

(0)

Will be set to 1 by counter overflow.
Always cleared by leading edge of GO
bit assertion.

INTOV

Set to 1 by program for interrupt on
counter overflow.

RATE2

RATE 1

RATEO

MODE 1

Set by program to O.

MODEO

Set by program to O.

Set by program to 1 unless ST2 GO
EN A is set; remains 1 until written to
o by program. Cleared when counter
overflows.

Remarks

See Table 3-1.

x = 0 or I, depending on user requirements.
(0) = Automatically cleared by GO bit assertion.

3-14

Table 3-3

CSR Bit Settings for Mode 1, Repeated Interval

Bit No.

CSR
Name

Bit Condition
as Written by
Processor

ST2 FLG

Will be set to 1 on ST2 event. Cleared
by leading edge of GO bit assertion
except when ST2 GO ENA has previously been set.

INT2

Set to 1 by program if interrupt on
ST2 event is desired.

ST2GOENA

Set to 1 by program if GO is to be set
by external signal to ST2. Cleared by
leading edge of GO bit assertion.

FOR

(0)

010

MAINTOSC

MAINTST2

MAINT STI

OVFLOFLG

(0)

Will be set to 1 by counter overflow.
Always cleared by leading edge of GO
bit assertion.

INTOV

Set to 1 by program for interrupt on
counter overflow.

RATE2

RATE I

RATE 0

MODE I

MODEO

Remarks

See Table 3-1.

}set by program to I •.
Same as for Mode 0, except that bit is
not cleared when counter overflows.

x = 0 or 1, depending on user requirements.
(0) = Automatically cleared by GO bit assertion.

3-15

Table 3-4

CSR Bit Settings for Mode 2, External Event Timing

Bit No.

CSR
Name

Bit Condition
as Written by
Processor

ST2 FLG

Will be set to 1 on ST2 event. Cleared
by leading edge of GO bit assertion
except when ST2 GO ENA has previously been set.

INT2

Set to 1 by program if interrupt on
ST2 event is desired.

ST2GOENA

Set to 1 by program if GO is to be set
by external signal to ST2. Cleared by
leading edge of GO bit assertion.

FOR

(0)

DIO

MAINTOSC

MAINTST2

MAINTSTI

OVFLOFLG

(0)

Will be set to 1 by counter overflow.
Always cleared by leading edge of GO
bit assertion.

INTOV

Set to 1 by program for interrupt on
counter overflow.

RATE 2

RATE 1

RATE 0

MODE 1

MODE 0

Remarks

See Table 3-1.

} Set by program to 2,.
Set by program to 1 unless ST2 GO
ENA is set; remains 1 until written to
o by program. Cleared when counter
overflows.

x = 0 or 1, depending on user requirements.
(0) = Automatically cleared by GO bit assertion.

3-16

3.5.3.4 Mode 3 (External Event Timing from Zero Base) - Operation is identical to that in Mode 2
except that counter is zeroed after ST2 pulse. Counter continues to increment until GO bit is set to O.
Note that the interval between two ST2 events may be measured directly in Mode 2 or 3 with processor
assistance if the CSR ST2 GO EN ABLE and Interrupt 2 bits are set before the first event and the GO
bit is left clear. Under these conditions, the first ST2 event will set the GO bit (and thus start the
counting process) and simultaneously issue an interrupt. If the interrupt service routine now clears the
ST2 Flag bit, the next ST2 event will cause the BPR to be loaded from the counter in the normal Mode
2 fashion. The choice of Mode 2 or Mode 3 for such measurements will depend on whether or not an
ongoing accumulation of time after the second event is required by the application. If such an accumulation is necessary, Mode 2 is appropriate since the counter is not zeroed after ST2 events.
3.5.4 Programming Example
Record point in double-precision timeframe for each ST2 event following GO. Program makes use of a
32-bit counter, the low order bits of which are taken directly from the KWVII-A (KWBPR) and the
high order bits of which are taken from a software counter (HICNT) that is incremented with each
K WBPR overflow.

MTPS
MOV

'5T28~V,

.ST2VEC

,C""A~ PIW
,LOAD 512 VECTOR
,ADD~

,SET UP PSW FOR 112

MOV

,1NTEA~UPT

(DX.ABLE

,ALL iUBSEQOENT

Mav

'OVS~V,

MOV

.200,'OVPSW

,OVVEC

,INTERRUPTI)
,LOAD OV VECTOR
,ADOR
,SET UP psw FOR OV
,1NTER~UPT (DISABLE
,AL~ SUBSEQUENT
,lNTE~AUPT8)

•
•

,SET UP POINTER TO
,BEGINNING OF

MOV

,BUt'rEf( AREA

ClJl(GOI

MOV

,DEPOSIT lMHZ, MOOE 2,
,INT OV EN, INT 5T2 EN,
,ANO GO INTO KWCS~

ClJUN'I:

WAIT

,FO~

INTE~RUPT

OVFLO OR 5T2
, IS f'OR 81 T SET?
,NO, CONTINUE
,XES, SERVICE rLA~
,OVEk~UN CONDITION
.IS S12 fLAG SET?
,NO, CONTINUE
,DID ST2 OCCUR 8E~O~E OV?
,NO, ~RANCH
,XES, SERVICE ST2 F1R5T
,~y

O'VS~V:

BIT

.10000,~l<WCSR

BEQ
JMP

COUNT

BlT
BEQ
TST
BPL
~ov

MOV

SIC

F(J~SRV

"00000,~KwCSR

2$
@l!<NBPR

HIe t. T , (fHl ) +
iKWSPR,(PO)+
.1 0 0000, @K~lCSR

,ACKNOWLEDGE ST2
, DCC Uf<fU:NC E

(example continued on next page)

3-17

~s:

MOV

HICr-.T,(ROl+

I>1UV

li~WbPP,(RO)+

,lNCf<t:ASE Msa 8~
J 1 COUNT
,BRANCH IF INCREA:iE
,CAUSES OVERrL(J~
,ACJC.NOwLEDGE OV
,CLiAR OV BIT
,ANi) ~EtURN TO MAIN
,PROGRAM
,GEl t.1Sb fROM sor'!' COUNT
,GE'l lISe. fROM HARU COUNT

BIC

'1000UO,(a!(WCSF

J AC~tIIOWlIEDGt,; 5T2

INC

HICt"T

8t;Q

l:>.D~RV

F.HC

.200,taKwCSP

RTI
S1'2S~VI

FORS~VI

,AND ~ErURN TO MA1N
,PRlJGPAM
,lV~NTS OCCURRING
,TOO ~AST FOR CURt(ENT
,SEJoi,VICe:

C;NDS~VI

,32

PTl

elr OVERFLOW

rOCCU~RE:.D

I(~CSp.:

KWBP~:

OVFVI£C&
S1'2V~CI
~ lC i~ T:
dUF'F'E~1

•

17l1l20
170422

440
444
U

.bLKw

,XXXX8LENGTH OF Ar.;SUl"T
,BUffER

XXXX

3-18

CHAPTER 4
AAVII-A DIGITAL-TO-ANALOG CONVERTER

4.1 GENERAL DESCRIPTION
The AAVII-A is a 4-channel digital-to-analog converter module for use on the bus of the LSI-II
processor. The unit is made up of control and interfacing circuitry, four D/ A converters, a dc-dc
converter to provide power to the analog circuits, and a voltage reference. Each channel provides 12
bits of resolution. Each has its own holding register which can be separately addressed and can be
written and read in either word or byte format. In addition, bits 0-3 of the fourth holding register are
brought to the I/O connector for use as a 4-bit digital output register.
Jumpers permit manual selection of voltage range and operating mode (bipolar or unipolar).
4.2

SPECIFICA TIONS (@ 25° C unless otherwise specified)

Number of D/ A Converters

Digital Input

12 bits (binary encoded for unipolar mode, offset binary
encoded for bipolar mode)

Digital Storage

Read-write, word or byte operable, single buffered

Analog Output Voltage Range

±2.56 V, ±5.12 V, ± 10.24 V bipolar; 0 V to +5.12 V, 0 V to
+ 10.24 V unipolar
Source: 5.2 rnA @ 2.4 V
Sink: 16 rnA @ 0.4 V

Uumper selected)
Digital Output Characteristics
(DAC 3 Holding Register
Bits 3:0)
Resolution

1 part in 4096

Warm-Up Time

5 minutes minimum

Gain Accuracy

Adjustable (factory-set for bipolar ±5.12 V; selection of other
ranges may require recalibration)

Gain Temperature Coefficient

10 ppm per degree C, maximum

Offset Temperature Coefficient

20 ppm of full scale range per degree C, maximum

Linearity

± 1/2 LSB maximum non-linearity

Differential Linearity

± 1/2 LSB, monotonic

Output Impedance

1 n maximum at DAC output; 4 n maximum at end of BC08R
8 ft cable
4-1

Drive Capability

± 5 rnA maximum per converter

Slewing Speed

5 V/ JIS

Rise and Settling Time
(to 0.1 % of final value)

4 JIS; 8 JIS with 5000 pF load in parallel with 1k n

Power Consumption
(from LSI-II bus power supply)

5 V ±5% @ 1.5 A, 12 V @ 0.4 A

Environmental

Ref: DEC STD 102, class C

Packaging

One quad module

Bus Loading

1 bus load

4.3 FUNCfIONAL DESCRIPTION
Figure 4-1 illustrates the AA Vll-A in block diagram form.
4.3.1 Bus Control
The logic associated with the bus control section maintains proper communications protocol between
the processor LSI-II bus and the AA VII-A. This logic generates and monitors the bus signals
involved during data transfers between the processor and the AA VII-A, permitting the AAVII-A to
recognize when it is being addressed by the processor (address defined by setting on the Address
Switch Pack), to accept input data from the processor, and to output data to the processor.
4.3.2 Control Logic
The AA VII-A has no Control/Status Register. The four digital-to-analog converters continually generate voltages at their outputs that reflect whatever digital values have most recently been written into
their respective holding registers. The role of the control logic is to make the necessary discriminations
between requests to change the state of the holding registers (Le., to write into the holding registers),
and requests to put the holding register contents onto the BD lines where they can be picked up
through the transceivers by the processor.
4.3.3 DACs 0, 1, and 2
Digital-to-analog conversion functions are performed in each of the four AA VII-A channels by identical circuits:
•

A holding register which stores the digital value output by the processor

•

A digital-to-analog converter (DAC) proper which generates a current that is a function of
the holding register value and of the mode/level jumper conditions

•

An amplifier that translates the current into a proportional voltage, provides a low output
impedance for the channel, and permits adjustment of signal offset.

4.3.4 DAC 3
DAC 3 is identical to DACs 0, 1, and 2 except that Holding Register bits 0-3 are routed to the I/O
connector as well as to the DAC. This arrangement permits these bits to be routed to external equipment that requires binary control signals at programmable intervals. Control data in these bit positions affects any 12-bit D / A conversion that they coincide with, but since they involve the least
significant bits of the word, the worst-case error is less than 0.5%. Consequently, DAC 3 can be used as
a 12-bit DAC or as an 8-bit DAC plus four output bits for CRT Intensify, Store, Non-Store, Erase,
etc.

4-2

HOLDING
REGISTER

MATCH

IoAZ7;; - - --,
WR DAC :3

L _______ --1

~
I

I
I

(SAME ASDAC0l

I
I

L _____ ---1

L ______________ -.J

11-4179

Figure 4-1

AA V ll-A Block Diagram

4.4 CONNECTORS, SWITCHES, AND CONTROLS
Figure 4-2 illustrates the location of user connectors, switches, and controls located on the component
side of the AA Vll-A board.

DAC0

DACI

DO DODD

R4{
(OFFFET)

~34

DAC2

DAC3

~5 Ri (OFFSET~
~\ ~37

R!
(GAIN) (OFFSET)

(GAIN)

(GAIN)(GAIN)

R49 (OFFSET)

DAC 0
W5

DAC I
W7

Wl0

DAC 2
W12

Wl1

DAC 3
W18

W15

--.0

0---0

0---0 0---0

--.0

0---0

0---0 0---0

0---00---0

W13

W14

W17

WIG

MODE / LEVEL STRAPS

BIT 3
\

BIT 11

Ii------1,
51

(ADDRESS)

11-4319

Figure 4-2

AA VII-A Connectors, Switches, and Controls

4.4.1 40-Pin Connector
Figure 4-3 illustrates the 40-pin connector pin assignments for user outputs. These pins may be connected to the optional H322 Distribution Panel· (see Paragraph 2.4.3.1) for convenient external user
access. The proper cable for this purpose is the BC08R. Also available is a Berg to prepared openended cable, the BC04Z.
Either a VR 14 or VR17 CRT may be interfaced to the H322 via a user-created cable terminating in a
24-pin Amphenol, or equivalent, male plug (DEC #12-03466-00). A user-created cable may be connected to other types of CRT systems using a 25-pin connector such as a male DB25P type plug (DEC
#12-05886-00).

* The AA V Il-A is shipped with decals which permit permanent identification of signal lines associated with H322 terminals.
4-4

A
C

B
D

E
~

L
~

N
~

R
~

T
~

w
~

,...
~

z
BB

CC
~

,...

DAC 1 HQ GND
DAC 2 HQ GND
DAC 3 HQ GND
-15V TEST
+15V TEST
DAC

a HQ GND

HH
KK

MM
pp

-0
~

,...

SS
"-

UU
~

NN
RR
TT
VV

BIT 3 OUT
BIT 2 OUT
BIT lOUT
BIT

a OUT

DAC 3 OUT
DAC 2 OUT
DAC lOUT
DAC

a OUT

BOARD SIDE
11-4314

Figure 4-3

40-Pin Connector Pin Assignments

The BC04Z signal lines may be connected to user-selected pins on a male or female connector. A
female 25 pin connector of the DB25S type (DEC #12-09326-00) may be used for general purposes. A
male 25-pin connector of the DB25P type (DEC #12-05886-00) will interface several popular CRT
systems to the AA VII. Either a VR 14 or VR17 CRT may be interfaced by means of a 24-pin Amphenol, or equivalent, male plug (DEC #12-03466-00) to the BC04Z. Both the AAVll and selected CRT
must be set up and adjusted for electrical compatibility. The CRT manual should define appropriate
connector pins for each AA VII signal line. Appropriate software will be necessary to control a CRT.
4.4.2 Address Switches
Figure 4-2 identifies the location ofSl, a switch pack containing 10 single-pole single-throw switches (l
unused) which, when set, transmit 0 logic levels to the compare inputs of the transceivers. Whenever
the AA VII-A sees BBS7 transmit a logical 1 (indicating that the processor has placed an I/O device
address on the bus), the transceivers compare the pattern created by the switches with that appearing
on Bus Datal Address (BDAL) lines 3-11. If the patterns match, the processor is addressing the
AA V II-A, and the latter prepares to load the DAC holding register identified by decoding bits 1 and 2
of the address word as defined in Figure 4-4.
Since the AA VII-A makes the comparison only in response to BBS7 (which the processor sets to 1
only in response to an address of 160000 or higher) when address line BD12 = 1, SI permits assigning
the four DACs any contiguous set of four even word addresses between 170000 and 177770. The
recommended setting for SI on the first AA VII-A is 170440, illustrated in Figure 4-5. Since LSI-II bus
address assignments for the AA Vl1-A extend from 170440 to 170476, up to four AA VII-As can be
accommodated on the same processor.

4-5

AAVll-A ADDRESS WORD

"0 • 0: WORD OR LOW BYTE
"0 • t : HIGH BYTE

DAC

0
0

0
1
0
1

0
1
2
3

ADDRESS

DAC

MODE

170440
170441
170442
170443
170444
170445
170446

WORD OR LOW BYTE
HIGH BYTE
WORD OR LOW BYTE
HIGH BYTE
WORD OR LOW BYTE
HIGH BYTE
WORD OR LOW BYTE
HIGH BYTE

170447

o
1
2
2
3

I I -4313

Figure 4-4
N

AA V ll-A Address Decoding

OCTAL EQUIVALENT

r----A----. r----A----. r----A----. r----A----.r----A----. rA-.

I I " I " I I I Ia I a I Ia I I a
n

1 11 11

I~PTG ~~~~E

BOARD HANDLE

~~~~~~~~~~ ~

~[J GJ ~ [J ~ ~ [J [J ~ D
BOARD FINGERS

I I I I I I I I I I I I I I I I I~g:~T~6~
00 01

02 0' 04 O' 06 07 08 09

10 11

1
11-4172

Figure 4-5

AA VII-A Address Switches (set for 17044n)

4.4.3 Mode /Level Selector Jumpers
As shipped from the factory, the AA VII-A is set for bipolar operation between -5.12 and +5.12 V.
Unipolar operation and operation with other voltage ranges can be achieved by proper changes in the
mode/level jumpers (illustrated in Figure 4-2). See AA VII-A Installation and Service chapter for
details.
4.5

INTERFACING TO OUTPUT DEVICES

4.5.1 Ground Connections
Analog output devices such as oscilloscopes may be either grounded or floating. If the oscilloscope is
grounded, either through its power plug or through contact between its chassis and a grounded cabinet, the oscilloscope ground should not be connected to any of the AAV11-A ground pins. Doing so
may result in a ground loop which will adversely affect scope control results as well as any ADV11-A
operations. If the oscilloscope is floating, its ground should be connected to the AAVII-A logic
ground, pins L, N, R, or T of the Berg connector. Note that the foregoing assumes that the computer
power supply ground is connected to power line (earth) ground. If continuity checks reveal no such
connection, attach a length of 12-gauge wire between the power supply ground and a convenient point
associated with earth ground.
4-6

Oscilloscope X and Y inputs may be either differential or single-ended. Differential inputs should be
driven as in Figure 4-6.

OSCILLOSCOPE

AAVll-A

=I~N-t--t>+

('~

a:
X OUT (PIN VV)
(-'1-'_ _...:..:.......:=..o....::x
o0~4-~AN~A~LO~G~G~R=OU=N=D~P~IN~U=U~~LJ
(
)
1
'>...~
X RETURN
__1~'~':~
___ ~
W

Z
Z

'_'

o
u
z

~~4-~Y~O.~UT~(~PI=N~T~T~)________~I'-~'I~_~~-_'~_ _ _Y~I=N__~>
"

ANALOG GROUND (PIN H H)

u~'

>.-<

'-'

Y RETURN

11-4523

Figure 4-6

Connection to Oscilloscope with Differential Input

When oscilloscopes with single-ended inputs are involved, the AA VII-A analog grounds (pins UU
and HH) are not used. Return path for X and Y signal currents is through ground for a grounded
oscilloscope or through logic ground (pins L, N, R, or T) for a floating oscilloscope. Since the
grounded, single-ended oscilloscope sees an input voltage which is the sum of the AA VII-A output
and the ground difference voltage between the oscilloscope and the AA VII-A, noise and line frequency errors may be minimized by plugging the scope into an ac socket as close as possible to the computer. Running single-ended scopes in a floating configuration will eliminate noise and line frequency
errors which are due to ground voltage differences.

4.5.2 Twisting
The effect of magnetic coupling into the scope input lines can be minimized for a differential-input
scope by running the AA VII-A output and its return line in a twisted pair. No benefit is derived from
a twisted pair with a single-ended scope input.
4.5.3 Shielding
The effect of electrostatic coupling into the scope input lines can be minimized by shielding the input
I lines from AAVII-A to the scope. The shield should be connected to ground at one end only. Ground
ing the shield at both ends may result in a ground loop which will adversely affect scope control results
and any ADVII-A A/D operations.
4.5.4 Drive Capability
Careful selection of cabling is essential. The D / A outputs are capable of driving a maximum of 5000
pF. Output impedance is I ohm. Output current limit is 5 rnA.
4.6 PROGRAMMING
All four DAC holding registers are automatically set to zero on system initialization. This produces
-5.12 V at the DAC outputs when the mode/level jumpers are connected as delivered from the factory.
Any holding register value remains in effect until changed by the processor in response to a program
instruction. Coding to the D / A converters is offset binary for bipolar operation and straight binary for
unipolar operation. Offset binary defines 0 as maximum negative voltage, mid-point (Le., 40008 for the
12-bit AA VII-A) as 0 V" and all Is (77778) as maximum positive voltage. These relationships are
illustrated in Table 4-1.
4-7

Table 4-1

AAVII-A Digital-to-Analog Conversions·
Unipolar

Bipolar

oV to +5.12 V oV to +10.24 V

Input Code ±2.56 V
(octal)
(volts)

±5.12 V

±10.24 V

(volts)

-2.56
-2.55875
-0.00125
0.0
+0.00125
+2.55875

-5.12
-5.1175
-0.0025
0.0
+0.0025
+5.1175

-10.24
-10.235
-0.005
0.0
+0.005
+10.235

+0.0
+0.00125
+2.55875
+2.56
+2.56125
+5.11875

0000

0001
3777
4000
4001
7777t

(volts)

+0.0
+0.025
+5.1175
+5.12
+5.1225
+ 10.2375

* Offset binary for bipolar, straight binary for unipolar operating modes. Conversions may be made between 2's
complement signed binary and offset binary numbers by subtracting 40008 from the 2's complement number
(or adding 40008 to the offset binary number) and using only the low order 12 bits of the result.

t Note that in all ranges, actual maximum positive voltage output is 1 LSB less than nominal maximum positive
output.

4-8

CHAPTER 5
DRV11 PARALLEL LINE UNIT

5.1 GENERAL DESCRIPTION
The DR VI I is a general-purpose interface unit used for connecting parallel-line TTL or DTL devices
to the LSI-II bus over up to 25 feet of cable. It permits program-controlled data transfers at rates up to
44K words per second (with optimized programming) and provides LSI-II bus interface and control
logic for interrupt processing and vector generation. Data is handled by 16 diode-clamped input lines
and 16 latched output lines. Device address is user-assigned and Control/Status Registers (CSR) and
Data Registers are compatible with 'PDP-II software routines.

I DROUTBUF I

BDALO-15L

BIRO L
BIAKI L
BIAKO L
BDAL 0-15 L
(f)

OUT 0-15

INT ENS A
INT ENS B

J INTERRUPT
J

LOGIC

REO A
CSRI

I NEW DATA ROY

DRCSR

A INIT

:::I

1.0.-

H
(f)

..J

SBS7 L
BSYNC L
BDAL 0-15 L
BWTBT L
BDIN L
SDOUTL
BRPLY L
BINIT L
BDAL 0-15 L

B INIT
ADDRESS
AND I/O
CONTROL
LOGIC

TO/FROM
USER
DEVICE
LOGIC

REO B
CSR 0
DATA TRANS

I DRINBUF l
I

IN 0-15
'--

CP-1808

Figure 5-1
5.2

DRVII Parallel Line Unit

JUMPER-SELECTED ADDRESSING AND VECTORS

5.2.1 Locations
Jumpers for device address and vector selection are provided on the DR VI I as shown in Figure 5-2.
Jumpers are installed at the factory for address 167770 (DRCSR) and vectors 300 (interrupt A) and
304 (interrupt B). These can be cut or removed by the user to program the module for his system
application, as described in the following paragraphs.

5-1

c
c

u
J1

u
J2

v ECTOR--:-UMPERS

I ~~==

I V3-vsl
L ___ =-v~

r--------,
I

I
I

ADDRESS JUMPERS
A3-

-A9

A4-

-AIO

~~==

A7-

==~a

I
I

SL 1

SL2

o---jr---o

OPTIONAL EXTERNAL
CAPACITOR
(SEE PARA.5.3.6l

LA..!=-=- _____ -1

M7941 ETCH REV. C

Figure 5-2

CP-1S09

DR VII Jumper Locations

5.2.2 Addressing
Jumpers involved with addressing include A3 through A12. Only address bits 03 through 12 are programmed by jumpers for DRY11 addressing, producing the 16-bit address word shown in Figure 5-3.
The appropriate jumpers are removed to produce logical 1 bits; jumpers are installed to produce
logical 0 bits.
5.2.3 Vectors
Jumpers involved with vector addressing include V3 through V7. Only vector bits 03 through 07 are
programmed by the jumpers for DRY11 vector addressing, producing the 16-bit word shown in Figure
5-4. The appropriate jumpers are removed to produce logical 1 bits; jumpers are installed to produce
logical 0 bits.
5-2

"---------'
BBS7 L
= 1(Ll

:;x

L - -_ _ _ _ _ _ _---.. ~---------'

ADDRESS JUMPERS:
INSTALLED =0
REMOVED =1

Figure 5-3

I ()

0= low byte (0-7)

DR VI I Device Address

L1=BYTE
SELECT
high byte(B-15l

,...
\

I.D

-t

(DRCSR-15l
REQUEST I NG DEVICE
0= REQ A
1 = REQ B

VECTO R JUMPERS:
I NSTALLED=O
REMOVED =1
CP-1745

Figure 5-4

5.3

DRVII Vector Address

INTERFACING TO THE USER'S DEVICE

5.3.1 General
Interfacing the DRVll to the user's device is via the two board-mounted H854 40-pin male connectors. Pins are located as shown in Figure 5-5. Signal pin assignments for input interface J2 (connector no. 2) and output interface JI (connector no. I) are listed in Table 5-1. The proper Berg-to-Berg
cable is a BC08R. The proper Berg to open-ended cable is a BC04Z. Connection to the DR VI I can be
made through the H322 Distribution Panel (see Figure 2-8). This unit is provided with decals, which
when applied according to instructions on the decal sheet, identify the H322 screw terminals with
respect to the associated pins on the DR VI I Berg connectors (A, B, UU, VV, etc.). Space is provided
on the decal for specific user identification. Note that DR VI I IH322 terminal relationships assumed
by the decal sheet rest on connection of the BC08R cable so that stamped labels on female cable ends
match embossed labels on male connectors - AlB to AlB, UU IVV to UU IVV. This normally means
that any "this side up" labels face away from the board on which the male connector is mounted.
Each BC04Z cable from a DR VII may be terminated in a female 25-pin connector such as a DB25S
type (DEC #12-09326-00) socket. The user may assign the signal and ground lines from the BC04Z to
specific connector pins. User apparatus may be connected into the socket by means of a male 25-pin
connector such as a DB25P type plug (DEC #12-05886-00).
5.3.2 Output Data Interface
The output interface is the 16-bit buffer DROUTBUF. It can be either loaded or read under program
control. When DROUTBUF is loaded by the CPU, the NEW DATA READY H 300 ns pulse is
generated to inform the user's device of the data transfer. In order to allow data to settle on the
interface cable, the trailing edge of this positive-going pulse should be used to strobe the data into the
user's device. The system initialize signal (BINIT L) clears DROUTBUF. When an output line is set to
logical 1, the TTL output is high (~ 2.7 V); when an output is set to logical 0, the TTL output is low
(~ 0.5 V).
5-3

~ l'
I,..

H854
CONNECTOR

H856 CONNECTOR
(SHOWN WITH
CABLE INSTALLED)

11-3294

Figure 5-5

Jl or J2 Connector Pin Locations

All output signals are TTL levels capable of driving five unit loads (8 rnA sink·· @ 0.5 V, 400 p,A
source··· @ 2.7 V) except for the following:

= 16 rnA sink·· @ 0.4 V, 400 p,A

NEW DATA READY = 10 unit loads
INIT (Initialize)· = 10 unit loads/connector
DA TA TRANSMITTED = 30 unit loads

source··· @ 2.4 V

= 48 rnA sink·· @ 0.4 V, 5 rnA
source··· @ 2.7 V

·Common signal on both connectors .
•• Sink refers to current from external +5 V supply through load to output line when output is low.
···Source refers to current from output line through load to ground when output is high.

5-4

Table 5-1

DRVll Input and Output Signal Pins·

Inputs

Outputs

Signal

Connector

Signal

INOO
INOI
IN02
IN03
IN04
INOS
IN06
IN07
IN08
IN09
INIO
INtI
IN12
INl3
INl4
INIS
REQA
REQB

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
11
12

TT
LL
H,E
BB

OUTOO
OUTOI
OUT02
OUT03
OUT04
OUTOS
OUT06
OUT07
OUT08
OUT09
OUTIO
OUTII
OUTl2
OUTl3
OUT14
OUTIS
NEW DATA RDY*
DATATRANS*
CSRO
CSRI
INIT
IN IT

HH
EE
CC
Z

Y
W

V
U
P

N
M
LL
S

Connector Pin

11
11
11
11
11
11
11
11
11
11
11
11
11
11
Jl
11
11
12
12
11
11
12

C
K

NN
U
L
N
R
T
W
X
Z

AA
BB

FF
HH
JJ

VV
C
K

DD
P

RR,NN

*Pulse signals, approximately 300-ns wide. Width can be changed by user.

5.3.3 Input Data Interface
The input interface is the 16-bit DRINBUF read-only register, comprising gated bus drivers that
transfer data from the user's device onto the LSI-II bus under program control. DRINBUF is not
capable of storing data; hence the user must keep input data on the IN lines until read by the LSI-II
microprocessor. When it has read the data, the DRVII generates a positive-going 300-ns DATA
TRANSMITTED H pulse which informs the user's device that the data has been accepted. The trailing edge of the pulse indicates that the input transfer has been completed.
All input and request signals are one standard TTL unit load; inputs are protected by diode clamps to
ground and +5 V. A +2.7 V to +5 V input is read as logical I; 0 V to 0.5 V as logical O.

5.3.4 Request Flags
Two signal lines (REQ A Hand REQ B H) can be asserted by the user's device as flags in the DRCSR
word. REQ B is available via connector no. 2 and can be read in DRCSR bit 15. REQ A is available
via connector no. 1; it can be read in DRCSR bit 7. Two DRCSR interrupt enable bits, INT ENB A
(bit 6) and INT ENB B (bit 5), allow automatic generation of an interrupt request when their respective REQ A or REQ B signals are asserted. Once the user's request signal has been asserted (logical 0 to
logical I transition), it must remain asserted until the CPU completes interrupt processing. At this
time, DATA TRANSMITTED or NEW DATA READY signals (see Paragraphs 5.3.2 and 5.3.3) can
be used to cancel the request. Note that Request A has a higher priority than Request B, and that each
of the interrupt enable bits can be set or reset under program control.

* Ground pins for connector.J1: J, M, S, Y, Y, CC, EE, KK, MM, PP, SS, UU. Connector 12: J, L, R, T, X, AA, DD, JJ,
MM, PP, SS, UU.

5-5

5.3.5 Initialization
The BINIT L processor-generated initialize signal is applied to DRVII circuits for interface logic
initialization. It is also available to the user's circuits via connectors Jl and J2 as follows:
Connector /Pin
Jl/P
J2/RR
J2/NN

Signal
AINITH
BINITH
BINITH

An active BINIT L signal will clear the following: DROUTBUF data; DRCSR bits 6, 5, 1,0; bits 16
and 7 (when the maintenance cable is connected); and Interrupt Request and Interrupt Acknowledge
flip-flops.
5.3.6 NEW DATA READY and DATA TRANSMITTED Pulse Width Modification
An optional capacitor can be added by the user to the DRVII module to extend the pulse width of
both the NEW DATA READY and DATA TRANSMITTED pulses. The module without external
capacitance (as shipped) will produce 300 ns pUlses. The capacitor can be added in the location shown
in Figure 5-2 to produce the approximate pulse widths listed below.
Approximate
Pulse Width (ns)
300
500
600
1200

Optional External
Capacitance (pF)
None
1200
1800
6000
5.4

PROGRAMMING

5.4.1 Addressing
Addresses for the DRVII can range from 160000 through 17777Xs. The least significant three bits
address the desired DRVII register as follows:
Address·
lXXXXO
lXXXX2
lXXXX4

Device Register
DRCSR
DROUTBUF
DRINBUF

Addresses 177560-177566 are reserved for the console device and should not be used for DRVII
addressing. The following address assignments are normally used:
First DRVII
DRCSR = 167770
DROUTBUF = 167772
DRINBUF = 167774
Second DRV11
167760 to 167764
Third DRV11
167750 to 167754

• Address lXXXX6 will not produce a response from the DRVl1.

5-6

Second DRVII
167760 to 167764
Third DRVl1
167750 to 167754

5.4.2 Interrupt Vectors
Two interrupt vectors are jumper-selected in the range of 0 through 37Xs. The least significant three
bits identify the interrupting function.

OOOxxO
OOOxx4

Interrupt A
Interrupt B

Vectors 60 and 64 are reserved for the console device and should not be used for DRVII vectors.

5.4.3 Word Formats
The three word formats associated with the DR VII are shown in Figure 5-6 and are described in Table
5-2.

5.4.4 I/O Timing
I/O transfers through the DR V 11 occur as illustrated in Figure 5-7.

o
DRCSR

CSRI
(READ/WRITE)
CSRO
(READ/WRITE)

REQUEST A
(READ ONLY)
INT ENB A
(READ / WRITE)

DROUTBUF~I ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~~ ~ ~ ~ ~
____

____

DATA OUT
(R EAD/WRITE)

DRINBUF

\~==================~================~
DATA IN
(READ ONLY)
CP-1746

Figure 5-6

DRVII Word Formats

5-7

Table 5-2

Word Formats

Word

Bit(s)

Function

DRCSR

REQUEST B - This bit is under control of the user's
device and may be used to initiate an interrupt sequence or to generate a flag that may be tested by the
program.
When used as an interrupt request, it is asserted by
the external device and initiates an interrupt provided
the INT ENB B bit (bit OS) is also set. When used as a
flag, this bit can be read by the program to monitor external device status.
When the maintenance cable is used, the state of this
bit is dependent on the state of CSRI (bit 01). This
permits checking interface operation by loading a 0 or
1 into CSRI and then verifying that REQUEST B is
the same value.
Read-only bit. Cleared by INIT when in maintenance
mode.

14-08
07

Not used. Read as O.
REQUEST A - Performs the same function as REQUEST B (bit 15) except that an interrupt is generated
only ifINT ENB A (bit 06) is also set.
When the maintenance cable is used, the state of REQUEST A is identical to that ofCSRO (bit (0).
Read-only bit. Cleared by INIT when in maintenance
mode.

INT ENB A - Interrupt enable bit. When set, allows
an interrupt request to be generated, provided REQUEST A (bit 07) becomes set.
Can be loaded or read by the program (read/write
bit). Cleared by BINIT.

04-02

INT ENB B - Interrupt enable bit. When set, allows
an interrupt sequence to be initiated, provided REQUEST B (bit 15) becomes set.
Not used. Read as O.
Can be loaded or read by the program (read/write
bit). Cleared by INIT.

5-8

Table 5-2

Word Formats (Cont)

Word

Bit(s)

Function

DRCSR

CSRI - This bit can be loaded or read (under program control) and can be used for a user-defined command to the device (appears only on Connector No.1).
When the maintenance cable is used, setting or clearing
this bit causes an identical state in bit 15 (REQUEST
B). This permits checking operation of bit 15 which
cannot be loaded by the program.
Can be loaded or read by the program (read/write
bit). Cleared by INIT.

CSRO - Performs the same functions as CSRI (bit 01)
but appears only on Connector No.2.
When the maintenance cable is used, the state of this
bit controls the state of bit 07 (REQ UEST A).
Read/write bit. Cleared by INIT.

DROUTBUF

15-00

Output Data Buffer - Contains a full 16-bit word or
one or two 8-bit bytes: High Byte = 15-8; Low Byte
= 7-0.
Loading is accomplished under a program-controlled
DA TO or DA TOB bus cycle. It can be read under a
program-controlled DATI cycle.

DRINBUF

15-00

Input Data Buffer - Contains a full 16-bit word or
one or two 8-bit bytes. The entire 16-bit word is read
under a program-controlled DATI bus cycle.

5-9

<data-I)

DRINBUF
<IN00: INI!5) ar."t Ire .. t by the
user; the data must remain stabl. until
trailing edge of DATA TRANSMITTED

~::0:><~

<data-I)

______________________~~~
~390ns

DATA TRANSMITTED
Pu lsed by DRV II when the
11/03 reads data from the DRVII
READ DATA FROM
REQUEST B

WAIT FOR A RESPONSE TO
.....- - - THE INTERRUPT REQUEST - - - . .

Set by user when ready to transmit new
data to the 11/03; reset by user upon
trailing edge of DATA TRANSMITTED

DRCSR

<bit 5) Interrupt Enable B
Set by user to allow interrupt-driven
data transfer.

DRCSR
< bit 15)Request B flag
I ndicates state of REQUEST 'A line
11-4588

<data=l)

~:,::

DROUTBUF
<OUT00: OUT 15) are set Ireset
by the DRV II under control of
the 11/03

----------X ________ ~d!!a,:0~
<data=l)

I
I
I

~ 300ns

NEW DATA READY
Pulsed by DRVII when the
11/03 writes data to the DRV11

WRITE DATA TO BUFFERJ

lTRL'NGEDGE'DATA STABLE
I

I
REQUEST A
WAIT FOR A RESPONSE TO
.....- - - THE INTERRUPT REQUEST -----4~

Set by user when ready for new data
from 11/03; reset by user upon
trailing edge of NEW DATA READY

DRCSR
< bit 6) Interrupt Enable A
Set by user to allow interrupt-driven
dato tronsfer.

DRCSR
< bit 7) Request A flag
Indicates stote of REQUEST A line.
11-4589

Figure 5-7

DRVll Interface Signal Sequence

5-10

CHAPTER 6
AD"VII-A, KWVII-A, and AAVII-A MAINTENANCE

6.1 MAINTENANCE PHILOSOPHY
Digital logic circuitry in the ADVll-A, KWVII-A, AAVII-A, and DRVII is to be repaired in the
normal manner. Analog circuitry, however, is to be repaired only at the factory. If any analog failures
occur in the field, modules are to be board-swapped and returned to the factory for repair. Installations performed by DEC include installation of DEC-supplied equipment only. The customer is
responsible for wiring from his equipment to the H322 Distribution Panel or to the end of the DECsupplied cable.
6.2
6.2.1

ADVII-A ANALOG-TO-DIGITAL CONVERTER
Installation

6.2.1.1 Location - The ADVII-A is a single-module option which interfaces to an LSI-II or PDP11/03 through one of the quad locations in the LSI-II backplane or in an expander box. Within the
constraints imposed by the LSI-II bus structure (refer to the LSI-Ii, Microcomputer Handbook - EB06583 76 09/53) the unit may be mounted in any available location and will operate within specifications, regardless of proximity to the processor, memory, or other DEC options. Where circumstances
permit, however, analog performance may be improved beyond specification levels by installing the
unit away from the processor, memory modules, or other noise-producing options. Note that priority
transfer requires that no empty unstrapped locations exist in the backplane between the processor and
any device that communicates with it.
6.2.1.2 Address and Vector Selection - Select and set CSR and Vector addresses as indicated in Paragraph 2.4.3.4. Note that where more than one ADVII-A is involved, CSR addresses must be four
locations apart (e.g., 170400, 170404, 170410, etc.). Vector addresses must be lOs locations apart (e.g.,
000400,000410,000420, etc.). Remember to reinstall any covers removed from switch packs SI and S2.
6.2.1.3 Board Insertion - Select a quad location, and making sure that the keyed edge connector
matches the physical configuration of the terminal block, apply firm pressure alternately to the extractor handles near the opposite corners of the board until it is squarely and fully seated in the connector.
6.2.1.4 Test Connector -. Do not insert I/0 cables into the Berg connector at this point. Instead,
insert the 7012894 test connector, which establishes the conditions required by the ADVII
Wraparound Test - that is, all channel inputs are grounded except 1, 2, 3, and 17, with internallygenerated +4.5 V signal on channell, -4.5 V signal on channel 2, ramp signal on channel 3, and
provision for external reference voltage on channel 17.
6.2.1.5 Shields - Install the 1700021-02 electromagnetic shields on both sides of the ADVII-A.
Shields are insulated on both sides and physically separate the ADVII-A from adjacent modules but
are not electrically connected to the system.

6-1

6.2.1.6

Acceptance - Conduct an acceptance test as specified in A-SP-ADVIIA.

6.2.1.7

Final Connections

Cables
Remove the 7012894 test connector and install the BC08R cable (ADVII-A to H322 Distribution
Panel) or the BC04Z cable (ADVI1-A to user devices) in the ADVII-A Berg connector. Connect
BC08R at both ends so that the stamped labels on the female cable ends match the embossed labels on
the male connectors - AlB to AlB, UU IVV to UU IVV. This normally means that any "this side up"
labels face away from the board on which the male connector is mounted.
NOTE
The BC08R cable is symmetrically wired but for several reasons is unsymmetrically labeled. That is,
wires identified as A and B on one end are identified
as UU and VV on the other end.
To simplify system relationships, the H322 PC
board compensates for this inversion on the PC
board that distributes Berg connector signals to front
panel screw terminals. For this reason, the user can
connect both ends of the BC08R according to the
labels, AlB to AlB and UU IVV to UU IVV. SO connected, signals from the ADVII-A will properly
appear at front panel terminals which have been
labeled according to the instructions on the ADVllA decal sheet. Each BC04Z cable from an ADVII-A
may be terminated in a female 2S-pin connector such
as a DB2SS type (DEC 12-09326-00) socket. The
user may. assign the signal and ground lines from the
BC04Z to specific connector pins. User apparatus
may be connected to the socket by means of a male
2S-pin connector such as a DB2SP type plug (DEC
12-0S886-00).

If K WV1I-A is present, connect Faston terminals, as described in Paragraph 2.4.3.2.
Manual Voltage Control
Applications which require variable dc voltages to be applied to one or more channels of the ADVIIA can be implemented by the circuit illustrated in Figure 6-1. Note that the H323-B Potentiometer Box
may not be used with the ADVI1-A.
6.2.2 ADVII-A Circuitry
The digital interface and control logic of the ADVII-A conforms in general to standard DEC practices
and should be understandable to qualified technicians who have access to ADVII-A print sets and are
familiar with overall ADVII-A functions as described in Chapter 2. Since the analog power supply
and the AID conversion sections involve some nonstandard circuits, they are discussed below.
6.2.2.1

AD VII-A Analog Power Supply

General
The ± 15 V power for the analog circuits is derived from a dc-dc converter which consists of three basic
sections: a 12 V power switch, positive and negative voltage doubler diode-capacitor banks, and a dual
tracking voltage regulator. Output jumpers (WI and W2) are provided to permit removing the load for
troubleshooting purposes.
6-2

---4"1::1

,','
--- ---T -

0--

L ...... _ _ ,

VB+
9V
(MINIMUM)

[

:
-

~I .. to AID .Input

I
1

1
1

I N759A,,~
12V l;'

.22
IlF

5K ~ .. to AID input

;;;c

VB9V
(MINIMUM)

" ./

I
I
I

U ~_-.JVIRI'v--

I
I
.
I
.. to AID Input I

_ _...l..-_ _.L..--_---I_ -

L-_', ', __ 1
I

CH. RET
NOTE:
I.

Value of R in kilohms can be calculated as follows:
R=

VB-6

K.!l

(I)

2.5 (N +2)
Where N = Number of channel pots.

Current drain from battery in milliamps when R is
selected with equation ( I) can be calculated as
follows:

I bat = 2.5 (N + 2) mA

(2)
11-4487

Figure 6-1

Battery-Operated Potentiometer Box for ADV11-A AjD Converter

TP3
POSITIVE
VOLTAGE
DOUBLER
SW A

+ 15V
WI
DUAL
VOLTAGE
REGULATOR

POWER
SWITCH
SW B

TP2
NEGATIVE
VOLTAGE
DOUBLER

- 15V
W2
11-4418

Figure 6-2

Analog Power Supply Block Diagram

Power Switch
Transistors Q15 and Q16 constitute the output stage of the 12 V power switch and provide a 0 V to
+ 12 V switching signal, which is derived from the SW A and SW B signals, and which drives the
voltage doubler diode-capacitor banks. Since saturated transistor switches turn on faster than they
turn off, an idle is included (see Figure 6-3) to ensure that Q 15 and Q 16 are never on at the same time.
V oltage Doublers
The basic voltage doubler consists of a charge transfer stage (0A and CA in Figure 6-4) and a charge
storage stage (DB and C B in Figure 6-3). When the power switch output is at 0 V, CA charges to VIN V DA (+ 11.3 V). When the power switch output goes to + 12 V, DAis reverse-biased and charge is
transferred from CA to CB. The power switch output then returns to 0 V, reverse-biasing DB and
recharging CA - DA. The voltage on CB builds up to approximately + 12 V - VDA + 12 V - VDB.
6-3

CLOCK H

-+, ~

~ "r--

A L

I r- ---111+-4- - -~J
\1

-1 "~
t2

~I~

~I--------~L-

I I

POWER
SWITCH
OUTPUT

+'::

~L-_-----,J

t, = IDLE-TIME
t2 = SWITCH ON TIME
11-4479

Figure 6-3

VIN: + 12 V

POWER
SWITCH
OUTPUT

DC-DC Converter Signals

-I

+12V~

teA

Figure 6-4

• Your

eB
11-4480

Basic Positive Voltage Doubler

The negative voltage doubler operates in a similar manner and consists of two basic doubler circuits in
cascade with an additional input negative voltage generating stage (D26 and C47).
Dual Voltage Regulator
The dual voltage regulator comprises an LM325N (E50) tracking regulator and power boosters (Q17
and Q18). Output current limit sensing is provided by R60 and R61. This stage regulates the outputs
from the doubler circuits to provide the ± 15 V of analog power required by the various analog circuits.
6.2.2.2 ADVII-A AID Conversion Circuit - The ADVII-A AID converter circuit utilizes a patented
auto-zeroing, successive approximation technique. The basic components of this circuit are illustrated
in Figure 6-5.
Analog Multiplexer
The analog multiplexer consists of two 8-channel, single-ended multiplexer ICs (E47 and E48) whose
outputs are connected together, thus forming a 16-channel multiplexer. During sample, when no conversion is in process, the addressed multiplexer channel is on. During hold, two conditions are possible. If single-ended (SE) mode is picked, all channels of the multiplexer are off and the auto-zero
switch is on. If SE mode is not picked, the negative side of the selected quasi-differential pair is
selected.
6-4

J 1-INPUTS

VOLT.
REF.

NODE
FEEDBACK
SIGNAL
SWITCH
}

AUTO-ZERO
SWITCH

ADZC

HOLD
a-BIT
VERNIER
D/A

SUCCESSIVE
APPROXIMATION
REGISTER
14---<
(SAR)

DATA
BUFFER

COMPARATOR

11-4481

Figure 6-5

ADVII-A AID Conversion Circuit Block Diagram

Auto-Zero

During sample, the feedback signal switch (Q5, Q6, Q8, Q9, QI0, and Qll) connects the output of the
feedback preamplifier (Q2 - Q4) to the input of the sample-and-hold (Q13, E51, C67), thus completing
the amplifier feedback path and allowing the sample-and-hold to track the analog input (see Figure 66).

EOS1

.~--~~.--~-+----------~----------~------~
~
Ro
ENODE

>-____-J E SH

* AND
PREAMP, SIGNAL SWITCH
SAMPLE-AND-HOLD

FEEDBACK D/A

VERNIER D/A

" -4482

Figure 6-6

AID During Sample

6-5

Summing currents into the L node:
(1)

EOS t is the offset of the input buffer amplifier (E49) and EoS2 is the offset of the feedback
preamplifier.
When a conversion is initiated, the feedback signal switch disconnects the output of the feedback
preamplifier from the input of the sample-and-hold, thus storing the signal, and connects the preamplifier output to the comparator (Q7 and Q12) input. Next, the AID input, Eb is either switched to
the negative channel or is grounded through the auto-zero switch, E44, depending upon whether or not
single-ended operation was selected.
At the completion of the conversion, the L node is ideally equal to EoS2' (see Figure 6-7).

NODE

4>-COMP
VERNIER D/A

FEEDBACK D I A

11-4483

Figure 6-7

AID During Conversion

Again summing currents into the L node:
(2)

Where I D ' is the feedback D/A current at the completion of the LSB interrogation.
Subtracting equation (2) from equation (1):
I - I '=
D

E - E '
1

_ (I

I ')

DY- Y

EOS1 -

R
D

6-6

OS1

_ EOS2 - E OS2 ' + E SH - E SH '

RF //RD

(3)

Note that since the offset due to the input buffer is the same in both cases,
Easl - Easl ' = East - Easl =0

EOS2 - EOS2' is controlled by R 15 by forcing an offset shift in the feedback preamplifier and is used to
null the offset caused by the sample-and-hold pedestal (ESH - ESH'). Note also that the conversion is
not dependent upon the magnitude of EOS2, but upon the forced shift. Therefore:

If no vernier offset is programmed, Iv = Iv',

and:
I

-I '=
D

E -E '
1
1
R

(4)

AID Conversion
The 12-bit feedback D I A (E46) is initialized to 40008 •

ID = 1/2 I FSR - I LSB

(5)

During conversion, each bit of the feedback D I A is interrogated in sequence by the SAR (E39),
starting with the MSB. At the end of each interrogation interval, the decision of the comparator to
accept or reject that bit is clocked into the SAR where this decision is held. A positive voltage on the L
node will cause the comparator to reject a bit. Because of the overall negative feedback, this process
will cause the L node to work its way toward null (Figure 6-8). After the LSB interrogation, the
contents of the SAR are transferred to the Data Buffer register.

CLOCK
EI

+ CLAMP

-f-

REJECT
OV

-CLAMP

I
COMP

o
LSB

MSB

11 - 4484

Figure 6-8

L Node During Conversion
6-7

Since
In ' min = a (@ code = 7777)
and
In ' max = I FSR - I LSB (@ code = 0000),
equations (4) and (5) permit voltage/current conversions to be derived as illustrated in Table 6-1.
Table 6-1

ADVII-A Voltage/Current/Bit Relationships

Code

In -In'

E 1 -E 1 '

7777

1/2 (I FSR - I LSB)

1/2 (E FSR - E LSB )

1/2 (I FSR)

3777

- ILSB

-E LSB

I FSR - I LSB

0000

-1/2 (lFSR)

-1/2 (E FSR )

ID '

6.2.2.3 The Vernier DAC - The Vernier DAC is a digital-to-analog converter packaged in a single
chip serving to provide programmable small increment offsets to the summing node of the A/D converter. It has been included in the ADVII-A circuit primarily to facilitate automatic testing of the
module and is used by the diagnostic routines in the measurement of noise, offset error, and interchannel settling error. The Vernier DAC is controlled through bits 07:00 of the Data Buffer register
(write-only), accepting 8-bit offset binary code to produce positive and negative full scale offsets of 2.5
A/D LSBs.
6.2.3 ADVII-A Performance Test (MAINDEC-II-DVADA-A)
This diagnostic package permits complete testing of all functional aspects of the ADVII-A. It is
divided into four major routines which are described below. Refer to diagnostic listing MAINDEC-llDV ADA-A for run instructions.
1.

Wraparound Routine - consists of four subtests which can be run individually or
consecutively:
a.

Analog Test - checks all channels and their outputs to ascertain whether or not multiplexing and gross conversion functions are working.

Noise Test - determines whether or not the amount and distribution of short-term
noise within the A/D converter is within limits.

Interchannel Settling Test - Determines whether or not the A/D converter can recover
from measurements at opposite extremes within specified times (switches alternately
between channels I and 2 - i.e., between +4.5 V and -4.5 V).

Differential Linearity and Relative Accuracy Test - makes mUltiple randomized measurements of ramp signal on channel 2 to determine, within 0.01 LSB, the width of the
voltage band corresponding to each of the 4094 finite width states.

Calibration Routine - works interactively with operator to facilitate precise calibration of
A/D. Requires precision voltage source.

6-8

START

RUN LOGIC
TEST

YES

TROUBL ESHOOT
AND REPAIR
LOGIC

RUN WRAPAROUND
ROUTINE

YES

ANALOG

LOGIC

TROUBLESHOOT
AND REPAIR
LOGIC

CHECK +5V
81 +12V
POWER SUPPLY

YES

ADJUST P.S.
FOR +5V OR
+12V

CHECK ANALOG
POWE R SUPPL Y

YES

TROUBLESHOOT
AND REPAIR
ANALOG P.5_

*Calibration routine can be run at
this point if precision voltage
source (EDC VS-llN or equivalent)
is available_
"·4485

Figure 6-9

ADVII-A Troubleshooting Procedure

6-9

Print Values routine - works interactively with operator to execute, and if desired, print out
results of conversions on selected channels.

Logic Test Routine - consists of 23 subtests that run sequentially without operator intervention and check status register read/write operation, initialize conditions, A/D done flag
setting and clearing, error flag setting, interrupt functions, etc.

6.2.4 Maintenance
In general, both routine maintenance and specific troubleshooting efforts will follow the flow defined
in Figure 6-9. Preventive maintenance will consist of removing airborne dust accumulations, checking
the power supply levels whenever new devices are added to the system, and running diagnostics whenever performance confirmation is desired.
6.2.5 Calibration (Requires Precision Voltage Source - EDC VS-IIN or Equivalent)
With test connector installed in ADVII-A Berg socket, connect the floating reference voltage to the
two clip-terminated leads (channel 17). Then, run the Calibration Routine and follow the step-by-step
instructions it issues. The program will specify reference voltage settings and indicate when offset and
gain potentiometers (identified in Figure 2-6) should be adjusted.
6.3

KWVII-A REAL TIME CLOCK

6.3.1

Installation

6.3.1.1 Location - The KWVII-A is a single-module option which interfaces to an LSI-II through
one of the quad locations in the LSI-II backplane or in an expander box. Within the constraints
imposed by the LSI-II bus structure (refer to the Microcomputer Handbook - EB-06583 7609/53), the
unit may be mounted in any available location. Note that LSI-II priority transfer requires that no
em pty unstrapped locations exist between the processor and the last device connected to the LSI -II
bus.
6.3.1.2 Address and Vector Selection - Select and set CSR and Vector Addresses as indicated in
Paragraphs 3.4.3.1 and 3.4.3.2. Note that where more than one KWVII-A is connected to the same
bus, CSR addresses must be four locations apart (e.g., 170420, 170424, 170430, etc.). Vector addresses
for multiple KWVII-As must be lOs locations apart (e.g., 000440, 000450, 000460, etc.). Remember to
reinstall any covers on switch packs S 1 and S3.
6.3.1.3 Board Insertion - Select a quad location, and making sure that the KWVII-A board is oriented so that the keyed edge connector matches the physical configuration of the terminal block, apply
firm pressure alternately to the extractor handles near the opposite corners of the board until it is
squarely and fully seated in the connector.
6.3.1.4 Test Connections - Do not connect user equipment to Berg connector Jl at this time. Diagnostic I/O signal tests will require jumpers between specified pins on J1.

6.3.1.5

Acceptance - Conduct an acceptance test as specified in A-SP-KWVII-A-3.

6.3.2 Final Connections
Install FAST ON connectors between CLK/STI tabs and ADVII-A tabs as required. Install the
BC08R cable (KWVII-A to H322 Distribution Panel) or BC04Z cable (KWVI1-A to user devices)
between the Berg connector (Jl) and the appropriate terminus. Connect the BC08R at both ends so
that the stamped labels on the female cable ends match the embossed labels on the male connectors A/B to A/B, UU/VV to UU/VV. This normally means that any "this side up" labels face away from
the board on which the male connector is mounted. (See Note in Paragraph 6.2.1.7.)

6-10

6.3.3 KWVII-A Circuitry
The digital logic of the KWV ll-A conforms in general to standard DEC practices and should be
understandable to qualified technicians who have access to KWVI1-A print sets and are familiar with
KWVII-A functions as described in Chapter 3.
6.3.4 KWVII-A Diagnostic (MAINDEC-II-DVKWA-A-D)
The KWVII-A diagnostic is divided into two main routines, the first designed to test logic functions
on up to four KWVII-A modules, the second to test selected module I/O functions, STl, ST2, and
clock overflow. Refer to diagnostic listing MAINDEC-II-DVKWA-A-D for run instructions.
6.3.5 Maintenance
Preventive maintenance consists of removing airborne dust accumulations, checking that power supply levels remain within specifications whenever new devices are added to a system, and running
diagnostics whenever performance confirmation is desired.
6.4 AAVII-A DIGITAL-TO-ANALOG CONVERTER
6.4.1

Installation

6.4.1.1 Location - The AAVII-A is a single-module option which interfaces to an LSI-II or PDP11/03 through one of the quad locations in the LSI-II backplane or in an expander box. Within the
constraints imposed by the LSI-II bus structure (refer to the Microcomputer Handbook - EB-06583 76
09/53) the unit may be mounted in any available location and will operate within specifications,
regardless of proximity to the processor, memory, or other DEC options. Where circumstances permit,
however, analog performance may be improved beyond specification levels by installing the unit away
from the processor, memory modules, or other noise-producing options. Note that priority transfer
requires that no empty unstrapped locations exist in the backplane between the processor and any
device that communicates with it.
6.4.1.2 Address Selection - Select and set address as indicated in Paragraph 4.4.2. Note that the least
significant three bits of the address word are reserved for software addressing of the four digital-toanalog converters (DACs) and are therefore not selectable on the switch pack. For this reason, if
several AA V II-As are installed on a system, they must be assigned addresses that are lOs locations
apart.
6.4.1.3 Board Insertion -- Select a quad location on the connector block, and making sure that the
AA V II-A board is oriented so that the keyed edge connector matches the physical configuration of the
connector block, apply firm pressure alternately to the extractor handles near the opposite corners of
the board until it is squarely and fully seated in the connector block.
6.4.1.4 Test Connectors - If AA V l1-A signals are to be routed to the H322 Distribution Panel,
connection may be made to that unit at this time (see Paragraph 6.4.2). Otherwise, leave the Berg
connector empty to allow for monitoring AA VII-A output signals in the next step.
6.4.1.5 Acceptance Test - Conduct an acceptance test as described in the AAVII-A Manufacturing
and Field Acceptance Procedure (A-SP-AAVII-A-3).
6.4.2 Final Connections
Install the BC08R cable (AAVII-A to H322 Distribution Panel) or BC04Z cable (AAVI1-A to user
devices) between Berg connector (J 1) and the appropriate terminus. Connect BC08R at both ends so
that the stamped labels on the female connectors match the embossed labels on the male connectors A/B to A/B, UU IVY to UU IVY. This normally means that any "this side up" labels face away from
the board on which the male connector is mounted. (See Note in Paragraph 6.2.1.7.)

6-11

6.4.3 Mode/Level Selection
As shipped from the factory, the AAVII-A is set for bipolar operation between -5.12 V and +5.12 V.
Unipolar operation and operation in other voltage ranges can be achieved by proper changes in
mode/level jumpers (illustrated in Figure 4-2). Table 6-2 indicates jumper configurations for all bipolar voltage ranges; Table 6-3 indicates those for all unipolar ranges. Note that each of the four DACs
on any given AA V II-A may be set for a different mode/level condition. Note also that any change
from the factory settings may require recalibration of the DAC involved (see Paragraph 6.4.7).

Table 6-2

Jumper Configurations for Bipolar Operation
±2.S6 V

±S.12 V

±10.24 V

DAC 1
W3
W4
W5
W6

IN
OUT
IN
IN

IN
OUT
OUT
IN

OUT
IN
OUT
IN

DAC2
W7
W8
W9
WIO

IN
OUT
IN
IN

IN
OUT
OUT
IN

OUT
IN
OUT
IN

DAC3
WI I
WI2
WI3
WI4

IN
OUT
IN
IN

IN
OUT
OUT
IN

OUT
IN
OUT
IN

DAC4
WI5
WI6
WI7
WI8

IN
OUT
IN
IN

IN
OUT
OUT
IN

OUT
IN
OUT
IN

6.4.4 AA VII-A Circuitry
The digital interface and control logic of the AA VII-A conforms in general to standard DEC practices
and should be understandable to qualified technicians who have access to AA VII-A print sets and are
familiar with overall AA VI1-A functions as described in Chapter 4. The analog power supply and the
digital-to-analog circuitry, however, make use of techniques and components with which DEC technicians may not be familiar. Since the analog power supply and the Dj A conversion sections involve
some non-standard circuits, they are discussed below.
6.4.4.1

AA V ll-A Analog Power Supply

(;eneral (see Figure 6-1)
The ± 15 V power for the analog circuits is derived from a dc-dc converter which consists of three basic
sections: a 12 V power switch, positive and negative voltage doubler diode-capacitor banks, and a dual
tracking voltage regulator.
6-12

Table 6-3

Jumper Configurations for Unipolar 0 peration

o V - +5.12 V
DACI
W3
W4
W5
W6

OUT

OUT
OUT
OUT

IN
OUT

DAC2
W7
W8
W9
WIO

o V - +10.24 V

OUT

OUT
OUT
OUT

IN
OUT

DAC3
Wll
WI2
WI3
WI4

OUT

OUT
OUT
OUT

DAC4
WI5
WI6
WI7
WI8

OUT

OUT
OUT
OUT

Table 6-4

IN
OUT

AA VII-A Input Code/Output Voltage Relationships

Input Code

Unipolar

Bipolar

0000
4000
7777

OV
1/2 FS
+FS -1/2 LSB

-FS
OV
+FS - 1/2 LSB

Power Switch
Transistors Q2 and Q3 constitute the output stage of the 12 V power switch and provide a 0 V to + 12
V switching signal, which is derived from the SW A and SW B signals, and which drives the voltage
doubler diode-capacitor banks. Since saturated transistor switches turn on faster than they turn off, an
idle time is included (see Figure 6-2) to ensure that Q2 and Q3 are never on at the same time.
Voltage Doublers
The basic voltage doubler consists of a charge transfer stage (DA and CA in Figure 6-3) and a charge
storage stage (DB and CB in Figure 6-3). When the power switch output is at 0 V, CA charges to VIN VDA (+11.3 V) through D A. When the power switch output goes to +12 V, DA is reverse-biased and
charge is transferred from C A to C B through DB. The power switch output then returns to 0 V, reversebiasing DB and recharging C A through D A . The voltage on CB builds up to approximately + 12 V VDA +12 V - VDB (+22 V).

6-13

The negative voltage doubler operates in a similar manner and consists of two basic doubler circuits in
cascade with an additional input negative voltage generating stage (D21 /22 and C42/43).
Dual Voltage Regulator
The dual voltage regulator comprises an LM325N (E38) tracking regulator and power boosters (Q4
and Q5). Output current limit sensing is provided by R57 and R58. This stage regulates the outputs
from the doubler circuits to provide the ± 15V of analog power required by the various analog circuits.

6.4.4.2 Digital-to-Analog Circuits - The analog sections of the AA VII-A consist of four 12-bit D/ A
converters (each contained on one 24-pin chip), four 2505 operational amplifiers, and a + 10 V precision reference source.
Each D / A converter (DAC) contains the necesary circuits to generate a 0-2 rnA output current and to
modify that current as a function of the 12 input data bits. A I-LSB change in the data register
corresponds to a change of I part in 4096 of the full scale output, approximately 1/2 p,A.
The output of the DAC is fed into a 2505 operational amplifier which converts the drive current into a
voltage output. The feedback from the output of the amplifier is passed through the selected feedback
resistors. The interconnections between these resistors, determined by the mode/range straps illustrated in Figure 4-2, determine the operating mode (unipolar or bipolar) and voltage range of the DAC
in question.
Gain and offset of each DAC are controlled through the externally-adjustable potentiometers (see
Figure 4-2).

6.4.5 AAVII-A Diagnostic Test (MAINDEC-Il-DVAAA-A)
The AA VII-A Diagnostic Test is divided into four routines. Each is briefly described below.
I.

Logic Tests (starting address: 200) - exercises and monitors behavior of interface and controllogic of all DACs on all AA VII-As in a system. Checks that DAC holding registers can
be loaded, cleared, and modified without error.

Ramp Loop (starting address: 204) - reiteratively increments the holding register for each
DAC to produce full-scale ramp voltages successively at the output of each DAC. Permits
confirmation by oscilloscope of DAC linearity, settling time, and channel isolation.

Static Calibration Loop (starting address: 210) - permits operator to input control data to
all DACs and monitor resulting output conditions. Run with a precision DVM as output
monitor, the Static Calibration Loop permits calibration of gain and offset of each DAC.

Dynamic Calibration Loop (starting address: 214) - reiteratively 'switches each DAC
between maximum and minimum output conditions. Facilitates checking DAC response
and recovery characteristics as well as amplifier slew rates.

6.4.6 Maintenance
In general, both routine maintenance and specific troubleshooting efforts will follow the flow defined
in Figure 6-10. Since the diagnostic program has no way of evaluating AA V II-A analog performance,
pass or failure of all but the logic tests depends on the judgment of the operator. Refer to the AA VIlA Manufacturing and Field Acceptance Procedure (A-SP-AAVII-A-3) for applicable criteria.
Preventive maintenance consists of removing airborne dust accumulations, checking that power supply levels remain within specifications whenever new devices are added to a system, and running
diagnositics whenever performance confirmation is desired.

6-14

YES

RUN
RAMP
LOOP

TROUBLESHOOT
AND REPAIR
LOGIC

YES

CHECK +5V
& +12V
POWER SUPPLY

YES

READJUST

P.S. FOR +5V

CHECK ANALOG
POWE R SUPPL Y

OR +12V

RUN STATIC
CALIBRATION
LOOP
YES

BOARD
SWAP
YES

TROUBLESHOOT
AND REPAIR
ANALOG P.S.

"See AAV11-A Field Acceptance
Procedure for applicable criteria.
114486

Figure 6-10

AAVII-A Troubleshooting Procedure
6-15

6.4.7 Calibration
Prepare the system to permit access to signal line(s) and calibration potentiometers of DAC(s) to be
calibrated. Connect DVM of appropriate precision (note that 1 LSB on ±2.56 V bipolar or 0 -5.12 V
unipolar = 1.25 m V) to output of DAC to be measured. Float the DVM as illustrated in Figure 6-11.
Take care to connect DVM common lead to HQ ground associated with the DAC in question. Then
proceed as follows:
I.

Load DAC holding register with 0000.

Adjust offset potentiometer (see Figure 4-2) for DVM reading appropriate to selected
mode/level condition (see Table 4-1).

Load DAC holding register with 7777.

Adjust gain potentiometer for DVM reading appropriate to selected mode/level condition
(see Table 4-1).

Load DAC holding register with 4000.

Check DVM for reading appropriate to selected mode/level condition (see Table 4-1).

Step 6 should produce a reading accurate to 1-1/2 LSB.

DVM
11!SV POWER

DAC n AAVll-A

+ 1 - - - - - - - 1 OUT

1 - - - - - - - 1 DAC RET

II -4525

Figure 6-11

Floating the DVM

6.5 DRVll PARALLEL LINE INTERFACE
Refer to the Microcomputer Handbook (EB-06583 76 09/53).

6-16

GLOSSARY OF AID TERMS

A hsolute Accuracy
The analog error, expressed as a percentage of full scale, referenced to the National Bureau of Standards volt.
A cquisition Time
The time duration between the giving of the sample command and the point when the output remains within a
specified error band around the input value.
Aperture Delay Time
The time elapsed between the hold command and the point at which the sampling switch is completely open.
Aperture Uncertainty
The variation in aperture delay time for a particular sample-and-hold.
Common Mode Rejection (CMR)
The ability of a differential amplifier to reject noise common to both inputs. Common mode rejection is
expressed as a ratio, the Common Mode Rejection Ratio (CM RR). A differential amplifier with a CM RR of 80
dB (10,000: I) would have an output voltage of 0.5 m V if both inputs were 5 V (5 V 180 dB).
Crosstalk
The amount of signal coupled to the output as a percentage of input signal applied to all off channels.
Differential Inputs (True)
Two external signals applied to the input circuitry of an AID system whereby the first is subtracted from the
second. The difference is applied to the AID system. This is generally used with twisted pair wiring to reduce
noise pickup.
Example

(V+) - (V-)

[V. + V(.) noise] - [V2 + V(2) noise]
[V. - V2 ] + [V(.) noise - V(2) noise]
For twisted pair wiring:
Vel ) noise == V(2) noise

GLOSSARY-}

D(fferential Inputs (Psuedo)

This method of inputting is similar to true differential inputting except that the negative input to the AID system
is common to the other inputs.
Differential Linearity

The maximum deviation of an actual stated width from its theoretical value for any code over the full range of
the converter. A differential linearity of ± 112 LSB means that the width of each code over the range of the
converter is I LSB ± 112 LSB. Missing codes in an AID converter occur when the output code skips a digit. This
happens when the differential linearity is worse than ± I LSB.
Drift

Drift is a function of the temperature coefficients of the components. It is the major contributor to gain and
offset error.
Gain Error

The error, expressed as a percentage, by which the actual full scale range differs from the theoretical full scale
range. This error is adjustable to zero.
Gain Temperature Coefficient

This is the amount of gain that changes with a change in temperature. This may be expressed in ppmlo C or °
C/LSB at full scale. If an AID has a gain temperature coefficient of 20° C/LSB at F.S., the AID converted value
will be off by I LSB at full scale if the temperature rises 20° C above 25° C.
Input Bias Current

The amount of current that flows into the selected AID channel from the source.
Input Impedance (de)

The resistance seen at the input to an AID system.
Linearity

Linearity is defined as the maximum deviation from a straight line drawn between the end points of the converter
transfer function. Linearity may be expressed as a percentage of full scale or as a fraction of an LSB.
Multiplexer

The multiplexer is a set of switches that permits analog data from different sources (channels) to be supplied to
the sample-and-hold (or A ID converter) individually.
Multiplexer Selliing Time

The maximum time required to reach a specified error band around the input value when switching channels.
Of/set Error

The error by which the transfer function fails to pass through the origin. This is usually adjustable to zero.
Quantization Error

Quantization error is defined as the basic uncertainty associated with digitizing an analog signal, due to the finite
resolution of an AID converter. An ideal converter has a maximum quantization error of ± I 12 LSB.
Quasi-Differential

Like true differential operation (see Differential Inputs) in that measurement is (made of the difference between
an input and a return line. Unlike true differential, however, in that measurem~nt is not made at one instant in
time, but rather throughout the variation of the conversion.
Relative Accuracy

This is defined as the input to output error as a fraction of full scale with gain iand offset errors adjusted to zero.
Relative accuracy is dependent on linearity.
GLOSSARY·2

Resolution
The resolution of an AID converter is defined as the smallest analog change that can be distinguished. Resolution is the analog value of the least significant bit.
Full scale
Resolution = ~...;.:,...:~~---Least significant bit
For example, if a system requires a weight measurement range of 2540 Ib, measured to the nearest 3 Ib,
·'
·
= -2540
3 - = 847 co de com b
matIons
Reso IutlOn
The closest standard AID converter resolution available is 10-bits binary. A binary resolution of IO-bits selected.
The new resolution for this channel is recalculated for 10 bits.
. 'f'Icant b')
2540
1 LSB (I east sigm
It = Full scale range = - = 2 .5 Ib
2n
1024

Sample-and-Hold
I n order to ensure that input voltage does not change during a conversion, a sample-and-hold is required. If the
change during a conversion cycle is less than 112 LSB, then a sample-and-hold circuit is not required.
Example
Conversion Speed = 20 J.ls
Full Scale I nput Range (FSR), where w max = 2 TT (BW)
Converter Resolution = 10 bits
LSB Value = .01 V Ibit
1/2 LSB = 0.005 V
Maximum slew = 0.005 V 120 J.lsec = 250 J.l V I J.lsec = 250 V Isec
(Rate required for no sample-and-hold)
for ein = 1/2 (FSR) sin W t
then de/dt = (1 /2)w (FSR) cos w t

:. kle/dt I max = (1/2)wmax (FSR) = (BW) (FSR), where w max = 2 TT (BW)
or 250 V Isec = TT (BW) (FSR)
BW = 250 V Isec ITT (10.24 V) == 7.77 Hz

Slew Rate
The capability of the output of an analog circuit to change its voltage in a given period of time. If the slew rate is
7 V /J.lsec, the analog circuit output will change seven volts in one J.lsec.

GLOSSARY-3

Successive Approximation

A method that is used to transform the analog signal to a digital number.

COMPARATOR

ANALOG INPUT

08-1238

An analog signal is compared to a logic generated signal. The logic always supplies a half range signal initially.
For example, the full scale input to an AID converter system is 10 V and the input to the system is 7 V.

Try*

New Logic VoItage

Is the Input
Greater Than
New Voltage

AID
Buffer
Bits

5V
2.5 V
1.25 V
.625 V
.3125 V
.15625V
.078125 V

5V
5 + 2.5 V
5 + 1.25 V
6.25 + .625 V
6.875 + .3125 V
6.875 + .1562 V
6.875 + .078125 V

Yes

6
5
4
3
2
1
0

Yes
Yes
No
No

Yes

*This is a 7-bit AID
10 1100 1 ~ 7 V in 10 V full scale range.

9
8

4
3
2

08-123'

GLOSSARY4

Decision

AID
Register
Value

Add +5 = +5

1000000
1000000
1010000
1011000
1011000
1011000
1011001

Do nothing
Add 1.25 = 6.25
Add .625 = 6.875
Do nothing
Do nothing

Add .078175

Throughput Speed
The Nyquist sampling theorem states that a minimum of two samples per cycle are required to completely
recover continuous signals in a noiseless environment. In typical instrumentation systems noise does exist and
from 5-10 samples per cycle are required.

For applications with dc and very low frequency signals, sample rate is usually a sub-multiple of the powerIine
frequency to provide essentially infinite rejection of these frequencies.
The minimum sampling speed required is the number of samples per cycle multiplied by the highest frequency
component of the data. For time multiplexed systems, the speed requirement of the A/D converter is dependent
on system throughput speed. System conversion speed is determined from data bandwidth, the number of channels, and the sampling factor by:
System throughput = (N) (n) (B.W.) samples/second
n = number of channels
where N = number of samples/cycle (sampling factor)
B. W. = largest bandwidth of any channel
Example
Channel 1 bandwidth 1()() Hz
Channel 2 bandwidth 200 Hz
Channel 3 bandwidth '250 Hz
throughput = lOX 3 (250) = 7500 sample/second
N = 10

n= 3
BW = 250 Hz
The A/D throughput is comprised of the following:
Multiplexer settling time
Sample & Hold settling time
A/D conversion speed
A/D recovery time
Computer acquisition time (Software)

GLOSSARY-S

Reader's Comments
ADVII-A, KWVII-A, AAVII-A,
DRVII USER'S MANUAL
EK-ADVII-OP-O02

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