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DEC-9L-GRVA-D

June 1968

200 pages

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Order Number:	DEC-9L-GRVA-D
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Pages:	200
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OCR Text

DEC-9L-GRVA-D

PDP-elL
USER HANDBOOK
JUNE 1968

DIGITAL EQUIPMENT CORPORATION. MAYNARD. MASSACHUSETTS

TABLE OF CONTENTS

Chapter

Page
SYSTEM INTRODUCTION
General
Characteristics
Design
Configura tions

SOFTWARE SYSTEM
General
PDP-9/L Compact Software
Assembler
Symbolic Editor
ODT-9
TRACE-9
SCAN
FAST-9
HRM-Puncher
Floating Point Package
Integer Arithmetic
FLIO
TOD
TTYIO
DIP-OPS
DTLIST
MTDUPE
Trig Functions
PDP-9/L Advanced Software
Paper Tape (or Card) System
Device-Independent System
System Components
FORTRAN
Macro Assembler
Debugging System (DDT-9)
Symbolic Editor
Peripheral Interchange Program
(PIP-9) .
Linking Loader
Input/Output Programming
System (lOPS)
Input/Output Monitor
Keyboard Monitor (KM-9)
Expansion of PDP-9 Advanced
Software System
MAINDEC Diagnostic Programs
SYSTEM ORGANIZATION
General
Central Processor Unit
Core Memory
Input/Output Facilities
Program Controlled Transfers
Conditional Skip on Device Status
Input/Output Read Status
Program Interrupt
Data Channels
Add-to-Memory Capability
Options
Extended Arithmetic Element,
Type KE09 A

Chaoter
3
(con't)

1-1
1-1
1-3
1-3
2-1
2-1
2-1
2-1

2-2

2-2
2-2

2-2
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-4
2-4
2-4
2-4
2-5
2-5
2-5
2-6
2-6
2-6
2-6
2-7
2-7
3-1
3-1
3-2
3-2
3-3
3-3
3-3
3-3
3-4
3-4
3-5
3-5

iii

Page
Memory Extension Control,
Type KG09A
Additional Core Memory
Power Failure Protection,
Type KP09A
Memory Protection Option,
Type KX09A
Automatic Priority Interrupt,
Type KF09A

3-5
3-5
3-5
3-5
3-8

PERIPHERALS
General
4-1
Standard Input/Output Equipment
4-1
4-1
Keyboard
4-1
Reader
Teleprinter
4-2
Punch
4-2
4-2
Optional Peripherals
Teletype Model 33 KSR and
4-2
Control
Keyboard
4-3
Perforated Tape Reader Type
PC09A
4-3
4-5
Perforated Tape Punch
Card Reader and Control
Type CR02B
4-7
Automatic Sine Printer
Type 647
4-8
Incremental Plotter and Control
Type 350
4-11
Oscilloscope Display Type 34H 4-14
Precision CRT Display Type
4-14
30D
Photomultiplier Sight Pen
Type 370
4-14
Analog to Digital Converter
and Multiplier Type AFOIB
4-14
Digital to Analog Converter
4-16
Type AAOIA
Multistation Teletype Control
Type LT09A
4-17
Relay Buffer Type DR09A
4-18
Interprocessor Buffers DB99A
4-18
and DB98A
Command Status Register Cori,
4-18
figuration
PDP-9/L to PDP-7 Interprocessor Buffer Type DB97 A 4-20
Data Communications System
4-20
Type DP09A (DPOIB)
4-21
Transmit Flag
4-21
Receive Flag
4-21
Receive End Flag
4-21
Ring Flag
4-21
Data Set Ready Flag

TABLE OF CONTENTS (continued)

Chapter
5

Page
AUXILIARY STORAGE SYSTEMS
General
DEC tape System
DEC tape Format
DEC tape Transport Type TU55
DEC tape Control Type TC02
Command and Status Bit configuration
DEC tape System Programming
Information
DECtape Programming Examples
Magnetic Tape Control, Type
TC59
Magnetic Tape Functions
9-Track Operation
Status or Error Conditions
Command Register Contents
Magnetic Tape Function Summary
Magnetic Tape Transport, Type
TU20 (7 -CHANNEL)
Magnetic Tape Transport, Type
TU20A (9-CHANNEL)
ADDRESSING
General
Direct Addressing
Indirect Addressing
Autoindexing
Extend Mode Addressing
Reserved Addresses

8
(continued)

5-1
5-1
5-1
5-1
5-1
5-4
5-5
S-8
5-12
5-16
5-18
5-18
5-20

CONTROLS AND INDICATORS
Operator Console
Marginal Check Panel

6-1
6-1
6-1
6-2
6-3
6-4

8-6
8-6
8-7
8-7
8-8
8-8
8-8

5-21

8-3

8-3
8-4
8-5
8-5
8-5
8-6

INPUT/OUTPUT CONSIDERATIONS
General
9-1
Program Controlled Transfers
9-1
Input/Output Read Status
Facility
9-2
Input/Output Skip Facility
9-4
Program Interrupt Control
9-4
Automatic Priority Interrupt
9-6
Priority Level
9-7
Channels
9-7
API lOT Instructions
9-7
Dynamic Priority Reallocation
9-7
Programming Examples Queueing
9-11
Data Channel Transfers
9,·11
Add-To-Memory Capability
9-13
Real-Time Clock
9,·13

5-20

8-1
8-1
8-1
8-1
8-2
8-2
8-2

Scaling for Fixed Point Arithmetic
Addition and Subtraction
Multiplication
Division
Scaling on a Binary Computer
Overflow
Programming Techniques for
Scaling
Analysis
Addition Scaling
Multiplication Scaling
Division Scaling
Fixed Point Addition
Fixed Point Subtraction

5-20

INSTRUCTIONS
General
7-1
Memory Reference Instruction
7-1
Format
Augmented Instruction Format
7-1
7-2
Memory Reference Instructions
Operate Instructions
7-4
Input/Output Transfer Instructions 7-8
Clear All Flags
7-10
EAE Instructions
7-10
EAE Setup
7-10
EAE Shifting Instructions
7-14
EAE Arithmetic Instructions
7-17
DAT A FORMATS AND ARITHMETIC INFORMATION
General
Signed Data Notations
Signed and Magnitude Notation
Complement Notation
Data Words
Data Word Formats
Magnitudes of Data Words
Basic Software Floating-Point
Formats

Page

Chapter

10-1
10-1

INTRODUCTION TO INTERFACING
General
11-1
Circuit Modules for Interfacing
11-1
Logic Symbols
11-1
I/O Communications
11-1

THE I/O BUS
General
Physical Description
I/O Power
Interface Signals
Data Lines
Output Control Signals
Device Selection Levels
I/O Run
Input Control Levels
Multiplexed Control Lines
Address Lines

12-1
12-1
12-2
12-2
12-2
] 2-2
12-3
] 2-3
12-3
]2-4
]2-4

TABLE OF CONTENTS (continued)

Page

Chapter
12
(continued)
13

Driving Address and Data
Lines
I/O Bus Interface Summary
PROGRAM CONTROLLED
TRANSFERS
General
Input/Output Transfer Instructions
Reading a Device Buffer into
the AC
Loading a Device Buffer
from the AC
I/O Skip Facility
Status Word Facility
Program Interrupt (PI)· Facility
Automatic Priority Interrupt,
Type KF09A
DATA CHANNEL
General
Latency
Device Interface Hardware
Initial Sequence of Data-In
Transfer (To Computer)
Operations Unique to
Reading (Refer to figure
14-3)

Page

Chapter
14
(continued)

12-4
12-4

13-1
13-1
13-5

13-5
13-6
13-6
13-7

Initial Sequence of Data-Out
Transfer (From Computer)
Operations Unique to Writing (Refer to Figure 14-4)
Expansion to Eight Devices
Signal Definitions
Add-To-Memory Capabilities
Standard Core Register Assignment
INST ALLATION PLANNING
General
Placement of Options
Environmental Requirements
Power Requirements
Cabling Requirements
Adding Special Interfaces

13-8
14-1
14-1
14-2

Appendix
INSTRUCTION SUMMARY

14-2
14-4

PDP-9 I/O CODES

SCALES OF NOTATION

14-4
14-4
14-4
14-4
14-5
15-1
15-2
15-5
15-6
15-6
15-7

LIST OF ILLUSTRATIONS

1-1
1-2
3-1
4-1
5-1
5-2
7-1
7-2
7-3
7-4
7-5

7-6

7-7
7-8
8-1
8-2
9-1
9-2
10-1
10-2
12-1
12-2
12-3
13-]
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
13-11
13-12
13-13
13-14
13-15
13-16
14-1
14-2
14-3
14-4
14-5
15-1
15-2{A)
15-2{B)
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10

Page

Title

Figure

Basic PDP-9/L
Expanded PDP-9/L System Configuration, Block Diagram
Central Processor-Major Register Organization
Perforated Tape Format
DEC tape Format (Sheet 1)
DEC tape Format (Sheet 2)
Location of Block in Opposite Direction
Memory Reference Instruction Format
Augmented Instruction Format
Operate Instructions
LAW Instruction
lOT Instruction Format
lOT Instruction Timing
EAE Instruction Formats (Sheet 1)
EAE Instruction Formats (Sheet 2)
EAE Microinstructions
Data Word Formats
Floating Point Formats
10RS Word-Status Bit Assignment
Program Interrupt, JMS Instruction, or CAL Instruction Storage Word
Format
PDP-9/L Operator Console
Marginal-Check Panel
I/O Bus Connections
I/O Bus Interface
Interface Connectors and Pins
PDP-9/L lOT Instruction Format
lOT Timing Diagram
lOT Pulse Waveforms
Device Selector Configurations
Loading the AC From a Device Buffer
I/O Signals from Buffer to I/O Bus
Loading a Device Buffer from AC
I/O Signals from I/O Bus to Buffer
Device Flag Hardware
Program Interrupt Storage Word
WI04: PDP-9/L I/O Bus Multiplexer
Devices on the Automatic Priority Interrupt
Connections for Trap Addresses Between 1008 and 1378
Gating Flip-Flop Register onto I/O Address Lines
Interface of a Single Device Flag to both the PI and API
Single Device with Multiple Flags
Data Channel Configuration
Type W104 Bus Multiplexer
DCH In Transfer (To Computer)
DCH Out Transfer (From Computer)
DCB Timing
Basic PDP-9/ L Cabinet Specifications
Basic PDP-9/L (Front)
Basic PDP-9/L (Rear, Ba.ck Door Removed)
PDP-9/L With Extra Memories (Front)
19-inch Cabinet Specifications
PDP-9/L With DECtape and PC09 A
Cabinet Configurations
Basic PDP-9/L with DECtape and PC09 A
Memory Expansion and DEC tape Expansion
Typical PDP-9/L System
Cabinet Configurations
c

1-3
1-3
3-1
4-4
5-2
5-3
5-13
7-1
7-2
7-6

7-8
7-9
7-9
7.:.11
7-12
7-13
8-3
8-4
9-3
9-5
10-1
10-5
12-1
12-3
12-5
13··2
13··2
13··2
13-4
13··5
13-5
13-6
13-6
13-7
13-7
13-10
13-11
13-11
13-12
13-12
13-12
14·-3
14·-3
14-4
14-4
14··6
15··2
15··3
15·4
15·4
15-4
15·5
15·5
15·6
15-6
15-6
15-7

LIST OF TABLES

Table
3-1
4-1
4-2
4-3

4-4
4-5
4-6
4-7
4-8
4-9
4-10

4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
5-1
5-2
5-3

5-4
5-5
6-1
6-2
7-1
7-2
9-1
9-2
9-3

9-4
9-5
10-1
10-2

11-1
12-1
13-1
13-2
14-1
14-2
15-1
15-2
15-3

Title
Memory Protection Type KX09 A Instructions
Keyboard Instructions
Reader Instructions
Teleprinter Instructions.
Punch Instructions
Tape Reader lOT Instructions
Tape Punch lOT Instructions
Card Reader CR02B lOT Instructions
Card Reader CR02B, Console Lights, Buttons and Switches
Line Printer Controls and Indicators·
Line Printer Type 647E
Digital Incremental Recorder Characteristics
Incremental Plotter and Control Instructions
Oscilloscope and Precision Display Instructions
A/D Converter Characteristics
AFO 1B A/D Converter and Multiplexer lOT Instructions
Relay Buffer Commands
Interprocessor Buffers DB99A and DB98A lOT Instructions
Bit Synchronous Data Communications System Types DPOIB and
DP09A lOT Commands
TC02 Control lOT Instructions
DECtape function Summary
DECtape Error Summary
DECtape Timing Data
TC59 Control lOT Instrutcions
Memory Extension Control Instructions
Reserved Addresses
EAE Operation Times
EAE Microinstructions
API lOT Instructions
Status Bits Associated With the SPI Instruction
Control Bits Associated with ISA Instruction
Status Bits Associated With the RPL Instruction
Clock lOT Instructions
Operator Console Controls and Indicators
Marginal-Check Panel Controls and Indicators
Data Transfer Rates
I/O Bus Interface Chart
Assigned PDP-9/L Device Selection Codes
Channel and Priority Assignments
Signal Definitions
Standard Core Register Assignment
PDP-9/L, Extra Memory, Free-Standing Options and Their Controls
Wired-In Options
Hardware and Logic Options for 19-1nch Cabinets

vii

Page
3-7
4-1
4-2
4-2
4-3
4-6
4-7
4-8
4-9
4-11
4-12
4-13
4-13
4-15
4-16
4-17
4-18
4-19
4-22

5-4
5-13
5-14
5-14
5-16
6-3

6-4
7-14
7-22
9-8

9-9
9-10

9-11
9-13
10-2
10-6
11-2
12-5
13-3
13-9
14-5
14-6
15-8
15-9
15-10

PDP-9/L Programmed Data Processor
viii

CHAPTER 1
SYSTEM INTRODUCTION

GENERAL

CHARACTERISTICS

The PDP-9/L ® programmed data processing system is a general purpose computer, incorporating
FLIP CHIP hybrid integrated circuits throughout.
The PDP-9/L features:

Complete cycle time of 1.5 microseconds for the
random access ferrite core memory.

• High performance at low cost
• Demonstrated reliability
• Simple input/output interfacing

Real-time clock (option) generates a clock pulse
every 16.7 msec (every 20 msec for 50-Hz systems) to increment a time counter stored in system memory. The counter initiates a program
interrupt when a programmed preset time interval is completed. The clock can be enabled or
disabled under program control.

• Extensive software
Flexible, high capacity, input/output provisions
coupled with a complete line of peripheral equipment allow system planning to satisfy a variety
of applications. The PDP-9/L can be easily configured to perform equally well the role of central data processing facility, control element, or
satellite processor. The ease with which its modular hardware and software adapt to the requirements of data acquisition, process control, and
on-line processing in real-time environments makes
it the ideal small scale system for scientific and
industrial use.
The PDP-9/L system is a single address, fixed
word length (18 bits), parallel binary computer.
The minimum system configuration (see frontispiece) has 4096 words of core memory storage,
paper tape input and output, console teleprinter
keyboard input and printer output at 10-Hz
(ASR-33).
The system readily interfaces to optional peripherals such as punched card equipment, line printers, magnetic tape transports, analog-to-digital
converters, digital-to-analog converters, CRT displays, data communication equipment, and disk
systems. Equipment of special design is easily
adapted for interfacing to the PDP-9/L. The
FLIP CHIP module line offers proven reliability
plus simple, inexpensive fabrication of compatible interface controls for special equipment, or
for the special-purpose equipment itself. Peripherals can be interfaced to the system as processing requirements expand, without modification
of the central processor.

True direct addressing is provided for 4096
18-bit word locations in the basic core memory
module configuration or any memory module
containing up to 8129 words appended to the
system. The system allows indirect addressing up
to the memory expansion limit of 32,768 locations. Core memory is expanded in increments
of 4096 words. System software expands to
make efficient use of all available core memory
storage.

Power failure protection can be optionally implemented to protect against data loss due to internal
power interruptions. With this option, the
PDP-9/L is unaffected by power interruptions of
less than 25 msec duration. In the event of a
longer interruption, the option can save the active register contents and automatically restart the
interrupted program at a specified address when
power is restored. Without the "power failure
protection" option, power interruptions of 10
msec duration, or longer, may result in loss of
active register contents and memory contents.

Automatic readin is provided of binary-coded
programs from paper tape via the ASR-33 paper
tape reader when provided. A user-initiated and
hardware-implemented control transfers 18-bit
words (three tape lines) from tape to a block of
sequentially addressed core memory locations and
executes the instruction defined by the last word
without further user intervention.

® PDP is a registered trademark of the Digital Equipment Corporation
1-1

A built-in test program, user-initiated and hardware-implemented, circulates a self-incrementing
count through all central processor registers for
the purpose of validating both their operation and
the internal transfer paths. The user can monitor and verify register operation by observing
the respective register display on the control console.
All input/output transfers are executed in parallel bytes up to IS bits in length.
Bidirectional input/output bus is provided for
program controlled data/command transmissions
between the central processor and up to 256 external devices. All program controlled I/O transfers pass through the central processor's accumulator (AC), the IS-bit primary arithmetic register. Memory referencing instructions convey
data between the AC and system core memory.
lOT (input/output transfer) instructions select
appropriate devices and effect the data transfer
between the AC and information registers in the
devices.
Eight buffered data channels allow fast, nonoverlapping data transmission between systelTI
core memory and eight devices interfaced to the
I/O bus. Data channel transfers occur via the
memory buffer (MB) register in the central processor and do not disturb the contents of other
major registers in the processor. Thus, a data
channel transfer suspends rather than interrupts
execution of the program in progress. The maximum transfer capacity of the data channel facility is between 160,000 and 220,000 words per
second, depending on the mix of input and output transfers (each output transfer steals four
machine cycles; each input transfer steals three
cycles). Provisions are made in system menlory
for word counter registers and current address
registers unique to each data channel.
Program interrupt control frees the program in
progress from the necessity of monitoring the
status of peripheral devices. The program continues until a device signals a request for service.
A subroutine, entered automatically upon the
processor's granting of the interrupt request,
stores the interrupted program's status, determines the device making the request, and transfers control to the appropriate service subroutine. At completion of the device servicing,
the interrupted program is restored to control.
The program interrupt control facility is suitable
for those peripheral devices having low data rates.
Multilevel automatic priority interrupt option
(API) affords immediate access to device handling
and data handling subroutines on a ranked priority
basis. Of the eight priority levels added by this
1-2

option the four higher levels are assigned to device use, and the lower four are assigned to software use. The priority levels are fully nested;
i.e., a higher priority request can interrupt inprocess servicing of a lower priority. The restoration of an interrupted service subroutine does
not require additional programming considerations. Likewise, the return to an interrupted
main program segment is easily implemented.
The granting of priority interrupt requests, at
completion of the current instruction, is rated
above program and program interrupt activity and
below data channel or direct memory access
channel activity, or real-time clock counting.
The API system has 32 channels of which 2S
are allocated to external device interrupting
(hardware priority levels) and 4 are allocated to
programmed interrupting (software priority levels).
A channel assignment defines the core memory
location of the unique entry to an interrupt subroutine. Device channels function independently
of priority; up to eight device channels may be
assigned to the same priority level. Device
channels also may be multiplexed without limit,
in which case the channel address defines the
entry to a search routine rather than unique entry to one routine.
Additional provisions include dynamic reallocation of device priority level assignments (device
control must be designed with logic circuits to
accomplish reassignment) and programmed raising
of the active interrupt to a priority level higher
than the normal assignment, when the situation
requires exclusion of internlpt requests at specific
priority levels. The API is program enabled or
disabled. Specific devices can be inhibited from
interrupting by appropriate control inputs to
their interfaces.
The basic machine has fixed-point hardware capability and floating-point software capability for
performing binary arithmetic in 1sand 2s complement notations. Floating-point software offers
choice of 6 or 9 decimal digit precision. The
program library supplied includes extensive repertoire of multi- and single-precision subroutines.
Add or subtract (complementary addition) is
performed in 3 microseconds with fetch of operand from effectively addressed core mernory
location. Overflow indication is furnished for Is
complement addition where absolute value of
algebraic summed result exceeds capacity of the
accumulator (2 17 - I). Algorithms for 2s com··
plement addition and subtraction treat overflow
from accumulator as a carry into a I-bit register
called the link.

4,096 WOOD
MEMORY

\
/
v

MEMORY LINKAGE
'I

110
CONTROL
LOGIC

CENTRAL
PROCESSOR

ASR-33
TELEPRINTER

110 BUS

OPERATOR'S CONSOLE

Basic PDP-9/L

Figure 1-1.
Extended arithmetic element option offers fast,
flexible, hardware execution of the following assigned or unassigned functions:

Division, including integer and fractional, in
4.5 to 13.5 microseconds. Divide overflow
indication is furnished when division would
produce quotient exceeding 217 - 1 magnitude.

Shifting the contents of the primary arithmetic registers (AC or MQ), right or left, in
3 to 19 microseconds.

DESIGN

Normalizing the quantity in the primary arithmetic registers; i.e., shifting the contents left
to remove leading binary Os for the purpose of
preserving as many significant bits as possible.
Time required is 3 to 19 microseconds.
Multiplication in 4.5 to 12.5 microseconds.

MEMORY
EXTENSION
CONTROL

The compactness of the PDP-9/L affords maximum computing facility in a minimum of space;
its modular construction provides for ease of
system growth t9 meet future processing requirements-external devices and additional core memory append with minimum effort and no effect
on the central processor. (Chapter 4, Peripherals,

AUTOMATIC
PRIORITY
INTERRUPT

1/0

CENTRAL
PROCESSOR

CONTROL
LOGIC

OPERATOR'S CONSOLE

REAL TIME
CLOCK

I
I
UP

TO EIGHT
4,096 -WORD
MEMORY BANKS

:dJ
I

I _,
r _ ........
- WORD
I 4,096
MEMORY

_ _ _ *...J

r -

AID C~~6ERTERI

L MULTIPLEXER.
_ _ _ .J

r-- -,
OTHER OPTIONS

L - - - - - - I LDE~G~~~~~~sl
_ _ _ .J

* OPTIONAL ACCESSORIES

Figure 1-2.

Expanded PDP-9/L System Configuration, Block Diagram
1-3

presents complete details on interfacing special
purpose or user-designed external device to the
PDP-9/L input/output facilities.) PDP-9/L is
completely self-contained, and does not require
special air conditioning or humidity control. Internal power supplies generate all the required
power from a lIS-volt, 60-Hz, single-phase power
source. Systems can be equipped to operate
with 50-Hz power at a variety of voltage levels.
CONFIGURATIONS
The basic PDP-9/L configuration (figure 1-1) consists of the following.
1. Central processor with integrated control
console, work shelf and chair.
2. Core memory stack of 4096 18-bit words.
3. Teletype ASR-33 provides paper tape reader and punch and teleprinter. It operates at
10 character/second. (Teletype Modes ASR-3S
can be optionally supplied and is recommended
for applications where extreme use is to be
made of the teleprinter's output function.)
4.

Real-time clock (option).

5. Input/output facilities: I/O bus, eight data channels, program interrupt control, I/O

1-4

status word provision, and conditional skip on
external device status.

The PDP-9/L. expands into a variety of configurations by:
Adding a 300 character/second paper tape
reader and 50 character/second paper tape
punch.
Increasing system core memory from the basicsupplied 4096 words up to 32,768 words in
increments of 4096 words.
Adding peripheral equipment selected from the
PDP-9/L line, or interfacing the system to
special purpose or user-designed equipml~nt.
Interfacing a basic expanded PDP-9/L to a
data processing complex.

Incorporating central processor options to increase the system's computing and data.
handling power.
Figure 1-2 illustrates a typical expanded PDP-9/L
system.

CHAPTER 2
SOFTWARE SYSTEMS
GENERAL
PDP-9/L offers two complete software systems,
PDP-9/L COMPACT and PDP-9 ADVANCED,
plus an extensive library of arithmetic subroutines,
utility programs, and maintenance and diagnostic
routines.
The PDP-9/L COMPACT software functions in a
paper tape input/output environment (i.e., source
and object forms of programs reside on paper tape)
with its field-tested components running in standalone fashion to provide the user with powerful
single-job capabilities.
The PDP-9 ADVANCED software is an all new
package of systems and utility programs, combining the latest concepts in device-independent programming with the power of FORTRAN IV and a
macro assembler. PDP-9 ADVANCED software
requires 8192 words of memory and is available in
the following two compatible versions:
Under control of a simple input/
output monitor for PDP-9/L's with
paper tape input/output or card input. This version will greatly expand
the single-job capabilities available with PDP-9/L COMPACT software.
In a more sophisticated monitor environment for all PDP-9/L's with
some form of auxiliary bulk storage
(DECtape, magnetic tape, or disk).
This latter version will permit device independent programming
under control of a keyboard monitor and a sophisticated input/output programming system.
PDP-9/L COMPACT SOFTWARE
Assembler
The PDP-9/L Assembler is a two-pass assembly
which requires less than 3K of memory. It
makes machine language programming on the
PDP-9/L much easier, faster and more efficient.
It permits the programmer to use mnemonic
symbols to represent instruction operation codes,
locations, and numeric quantities. By using symbols to identify instructions and data in his pro-

gram, the programmer can easily refer to any
point in his program without knowing actual
machine locations.
Among the features of the assembler are a
powerful set of pseudo operation instructions
which are used to:
1.

Reserve a block of core.

Set a desired radix.

3. Conditionalize sections of coding.

4. Output text strings.
5. Control the listing produced by the
assembler.
The assembler also allows the user to replace
symbolic data references by representing them as
literals. The PDP-9/L assembler is upward compatible with MACRO-9 at the source language
level. Input and output devices may be assigned
by communicating with the assembler.
Symbolic Editor
The symbolic editor of the PDP-9/L software
system provides the user with the ability to conveniently create, examine and modify symbolic
ASCII text material. The editor operates on lines
of symbolic text, delimited by carriage return
characters and organized into pages or blocks.
These lines can be read into a buffer, selectively
examined, deleted, or modified, and written out.
New text may be substituted, inserted or appended.
Editor operation codes are divided into two
basic categories: control instructions and editor
commands. Control instructions determine the
editor's operation level: input text or edit text.
The input text level is used 'to create new symbolic material. The edit text level uses the
editor commands which fall into four classes:
I/O requests, pointer manipulation, editing requests, and examination requests. The pointer
is a software device which places the current
line in a special work area of core to facilitate
edit request processing.

2-1

The editor is most frequently used to modify
PDP-9/L source programs, but may be used to
edit any symbolic ASCII text. It operates with
all standard PDP-9/L peripheral devices.
ODT-9
ODT-9 (Octal Debugging Technique) is a powerful program checkout aid which allows the user
to carryon an interactive on-line debugging
process with teletype commands and octal numbers. As errors are found, they may be corrected on-line and then the program can be executed immediately to test the correction. In
general, the user types commands to 0 DT-9
which control the following functions:
1. Initiating the user's program.
2.

Stopping and subsequently continuing the
user's program at selected points called
breakpoints.

3. Examining and/or modifying the accumulator and link at breakpoints.

Teletype commands may also be used to specify
functions such as:
1. Suppressing the accumulator printout.
2. Printing only on CAL, JMS, JMP and
SKIP instructions.
3. Tracing the program interrupts.
4.

Halting or continuing the user's programl
upon completion of the trace.

SCAN
SCAN is a small program used to scan areas of
memory for particular bit configurations. The
user specifies the start and stop address for the
area to be scanned, the bit configuration to
look for, and the bit positions to be tested (i.e.,
a mask). SCAN then scans the area. When a
match is found, the address of the match is
printed along with the unmasked matching word.
Proper selection of the operating parameters allows SCAN to be used as a dump.
FAST-9

Examining and/or modifying the contents
of any memory location.

5. Searching user defined areas for memory
locations containing specific bit configurations.
6.

Dumping areas of memory for later loading, debugging and execution.

TRACE-9
TRACE-9 is an on-line debugging tool which allows the user to trace the execution of specified
portions of his program. In general, TRACE-9
generates a listing on the teleprinter which details the flow of control as the program executes.
The information printed includes, for each traced
instruction, the location of the instruction, the
instruction itself, the location of the next instruction to be executed, and the values in the accumulator and link after execution of the instruction. TRACE-9 is controlled through teletype commands which specify tracing parameters
such as:
1.

Start address for tracing.

Stop address for tracing.

3. Various co un ts to specify when to start
and stop.

2-2

FAST-9 (Fast Acquisition of System Tape) is a
loading system for use in the PDP-9/L Software
System to retrieve frequently used progra:ms
from DECtape and to create systern tapes. The
main advantages of the system are speed and
ease of access.
The FAST-9 system tape, as distributed by DEC,
contains commonly used Software System pro-·
grams such as the Symbolic Editor, the PDP-9/L
Assembler and ODT. Since these can be called
from DECtape with only a small bootstrap,
papertape handling is eliminated for systems
programs. This results not only in a significant
time savings, but also in increased reliabillty.
FAST-9 is by no means restricted to Digital
systems programs; it can very conveniently
by employed for frequently accessed user
created programs. This manual contains complete directions· for use of the FAST-9 system
tape as well as directions for adding user programs to the system.

HRM -Puncher
The HRM Puncher is a self·relocating paper tape
dump program. It may be loaded, by the Hardware Read-in (HRI), into any block of memory.
I t relocates itself and then punches out a user
specified area of memory in the HRI format.

Floating Point Package

MTDUPE (Master Tape Duplicator)

These routines perform all arithmetic operations
on normalized floating point 'data. The routines
must be assembled with the user's program. He
can use either single (20-bit accuracy) or double
(35-bit accuracy) precision data. The actual
arithmetic is performed 'using software accumulators by program FPOINT. Programs SINGLE
and DOUBLE are required to perform the setup
for FPOINT.

The MTDUPE duplicates and verifies tapes. The
MTDUPE duplicates any tape. By using switches
the user is allowed to have a title punched in a
readable format. The verifying routine checks
the parity and will stop at every frame where the
parity is off.

Integer Arithmetic
These routines provide PDP-9/L users, without
the EAE option, with simulated logical and signed
multiply and divide routines.
FLIO (Floating Input/Output)
These routines allow the user to input and output signed decimal data in floating point format, from either the teletype or paper tape
reader.
TOD (Teletype Octal Dump)
The TOD allows the user to obtain a typed output of the contents of any register or set of
registers he specifies. This program is provided
in two versions one for loading into high core
(start at 7602) and one for low core (start at
22).

TTYIO (Teletype Input/Output Conversion)
This package consists of routines which allow
text to be input and output through the teleprinter. Formatting routines are also available
in this package.
DIP-OPS (Decimal Integer Print/and Octal Print
Subroutines)
Allows the user to output his data to the teleprinter in any of four modes: 1) signed decimal,
2) right justified octal, 3) left justified octal, and
4) octal with no zero suppression.
PTLIST
This routine lists a paper tape from either the
paper tape reader or the keyboard, and prints it
on the teletype.

Trig Functions
These routines allow the PDP-9/L user to perform trigonometric calculations on his floating
point data in either single or double precision
mode.
PDP-9 ADVANCED SOFTWARE
PDP-9 ADVANCED software is an all-new completely relocatable software package combining
sophisticated programming features with flexibility and ease of use. This new package includes a FORTRAN IV compiler, a macro assembler, an on-line debugging system, a symbolic
editor, a peripheral interchange program, a linkin~
loader, an input/output programming system, and
a monitor.
Two versions of the PDP-9 ADVANCED software system are available: a simple input/output
monitor system with 8K and paper tape input/
output (using optional PC09A) and the option of
punched card input facilities for basic PDP-9
users. The system will also include a more sophisticated monitor-based, device-independent
system for PDP-9s with one or more forms of
auxiliary bulk storage (magnetic tape, DECtape,
or disk). Both systems are compatible.
Paper Tape (or Card) System
Basic or extended-memory PDP-9/L systems
without auxiliary bulk storage use the FORTRAN
IV compiler, macro assembler (MACRO-9), debugging system (DDT-9), Symbolic Editor, peripheral Interchange Program (PIP-9), and Linking
Loader under the control of the Input/Output
Monitor. Only paper tape input/output or card
input is provided. All systems programs have
full features, are completely relocatable, and
handle or produce relocatable code. Maximum
utilization will be made of optional central. processor features, such as the Extended Arithmetic
Element and Automatic Priority Interrupt, when
they are available.

2-3

Device-Independent System
The inclusion of bulk storage in a PDP-9/ L will
allow the use of the key board monitor-based,
device··independent version of PDP-9 ADVANCED
software. The minimum bulk storage requirements are:
DEC tape transports (TV 55) and control
(TC02), or

2
2

IBM-compatible transports (TV20 or equivalent) and control (TC59), or

disk system and control

With the addition of one of these forms of bulk
storage to a PDP-9/L system, the Keyboard
Monitor (KM-9), and the Input/Output Programming System (lOPS) can be used to automatically
store, retrieve, load and execute PDP-9 programs. With this device-independent version of
PDP-9 ADVANCED software, the user can call
his system programs from any bulk storage device (designated the system device), compile or
assemble from any input device to any proper
output device, and (optionally) obtain listings on
any printing device or magnetic tape. By using
the keyboard nlonitor to change the system and
object program device assignment tables, the
operator may designate at load time which devices shall serve as system device, object program
storage, and data input and output devices. The
linking loader, with access to the input/output
programming system, automatically loads the
input/output programs required by the device
assignment tables.
System Components
The component packages of the new PDP-9
ADV ANCED software system are described briefly below. More complete descriptions will be
found in the individual language specification or
operator's manual for each program.
FORTRAN IV
The PDP-9 FORTRAN IV compiler is a twopass system which accepts statements written
in the FORTRAN language and produces re··
locatable object code capable of being loaded by
the linking loader program. It is fully com··
patible with USA FORTRAN IV, as defined in
the USA Standard X3.9-1966, with the exception
of the following few features which were modified to allow the compiler to operate in 8,192
words of core storage:
l.
2-4

Complex arithmetic will not be available.

Adjustable array dimensions will not be
allowed.

Blank COMMON will be treated as named
COMMON.

4. The implied DO feature will be deleted
from the DATA statement.
This FORTRAN IV compiler operates with the
PDP-9 program interrupt facility enabled and
generates real-time programs that both operate
with the program interrupt enabled and can work
in conjunction with assembly language programs
that recognize and service real-time devices.
Subroutines written in either FORTRAN IV or
the Macro Assembler language can be loaded
with and called by FORTRAN IV main programs. Comprehensive source language diagnostics are produced during compilation; a symbol
table is generated for use in on-line debugging.
Macro Assembler (MACRO-9)
With the Macro Assembler, PDP-9/L users are
able to utilize highly sophisticated macro generating and calling facilities within the context
of a symbolic assembler. Among the more
prominent features of MACRO-9 are:
1. The ability to define and call nested and
recursive macros.
2. Conditional assembly based on the com·,
putational results of symbols or expressions.
3.

Repeat functions.

4. A variety of fixed- and floating-point symbolic formats for constants.
5.

Boolean manipUlation.

Optional octal and symbolic listings.

Three forms of radix control (binary, octal,
decimal) and two text modes (ASCII and
6-bit trimmed ASCII).

8. Global symbols for easy linking of separately assembled programs.
9. Choice of output format: relocatable, absolute binary (checksummed); full binary
(unchecksummed), capable of being loaded
via the READ IN key (console).
10. Ability to call input/output system macros
which expand into lOPS calling sequences.

Debugging System (DDT -9)
DDT-9 adds the flexibility of relocatability and
real-time operation to the capabilities of PDP-9
BASIC DDT. With it, the user may load and
operate his program in a real-time environment
while maintaining strict control over running of
each section. DDT-9 allows the operator to insert and delete break-points, examine and change
registers, patch programs, and search for specific
constants or word formats.
The DDT breakpoints features allow for the insertion and simultaneous use of up to four breakpoints and anyone or all of these breakpoints
may be removed with a single keyboard command. The search facility allows the operator to
specify a search through any part, or all of an
object program with printout of the locations
of all registers that are equal (or unequal) to
specified constapt. This search feature also
works for portions of words as modified by a
mask.

With DDT-9, registers may be examined and modified in either instruction format or octal code,
and addresses may be specified in symbolic relative, octal relative, or octal absolute. Patches
may be inserted in either source language or
octal.
Symbolic Editor
The Symbolic Editor of the PDP-9 ADVANCED
software system provides the ability to read symbolic text from any input device (paper tape
reader, card reader, disk, drum, DECtape, magnetic tape, etc.), to examine and correct it, and
to write it on any output device. It can also be
used to create new symbolic programs.
The Editor operates on lines of symbolic text,
delimited by carriage return (C/R) characters and
organized into blocks or pages. These lines can
be read into a buffer, selectively examined,
deleted, or modified, and written out. New text
may be substituted, inserted, or appended.
Among the types of caommands available to the
operator through the Symbolic Editor are:

Input Operations
a.
Read a page of text.
b. Read n lines of text.

c.
Skip a page of text.
d. Skip n lines of text.
Examination Operations
a.
Print the entire buffer.
b. Print n pages
c.
Print lines n through ITL
d. Print line n.
e.
Print the entire buffer without
comments.
f.
Print lines n through m without
comments.
g.
Print line n without comments.
h. Search for and print the next location symbol.
i.
Back up and print the previous line.
Editing Operations
a.
Delete line n.
b. Delete lines n through m.
c.
Append text.
d. Insert text before line n.
e.
Change line n.
f.
Change lines n through m.
g.
Read the nex t n lines and insert
them after line m in the buffer.
h. Erase the buffer.
Move a line.
i.
Output Operations
a. Output the entire buffer.
b. Output line n.
c. Output lines n through m.
d. Punch a form feed.

Several comm~nds which combine input and outpu t commands are also available to the user.
With these, the buffer may be cleared and a new
page automatically read in after the output of
an edited page, or one or more pages may be
read and punched in one operation (for duplication of sections of a symbolic tape).
Peripheral Interchange Program (PIP-9)
The primary function of PIP-9 is to facilitate the
manipulation and transfer of data files from any

2-5

input device to any output device. It can be
used to update file descriptions, delete, insert,
or combine files, perform code conversions,
rewind tapes, and retrieve storage space that
is no longer required by a file device.

gram than to revise individual input/output sections to fit a new configuration. By the use of
lOPS, programs can be changed more rapidly to
fit the expanding configurations.
Input/Output Monitor

Linking Loader
The Linking Loader has the task of loading any
PDP-9 FORTRAN IV or MACRO-9 object program which exists in relocatable or absolute format. Among its tasks are loading and relocation
of programs, loading of called subroutines, retrieval and loading of implied subroutines and
lOPS routines, and loading and relocation of
the necessary symbol tables.

The simple input/output monitor includes the
device assignment tables and input/output routines necessary for programs being run on PDP9/L's without bulk storage. The function of the
monitor is to handle all input and output for
system programs or users' programs so that the
programmer need not be concerned with device
or data manipulation routines. Normally only
paper tape input/output or card input is allowed
by the input/output monitor.

Input/Output Programming System (lOPS)
Keyboard Monitor (KM-9)
lOPS provides a standardized programming interface to all input/output devices in a PDP-9/L
system. Symbolic input/output unit assignments
allow users' programs to select II 0 devices specified symbolically to the macro assembler or the
FORTRAN IV compiler. lOPS consists of a
modular collection of relocatable input/output
and utility subroutines which transmit data to
and from peripheral devices and make data
readily available for processing. lOPS data and
file handling routines include device independence
for all systems programs.
Specifically, lOPS provides the user with three
levels of I/O programs.
1.

KM-9 consists of bootstrap loader, a keyboard
listener program, a monitor command decoder,
lOPS routines, an error diagnostic program, and
device assignment tables (DA Ts).

Device handling - providing the basic sub- _ The bootstrap loader always resides in upper
routines to allow the user to operate a
memory and is responsible for loading the monidevice, doing code conversion where retor into lower memory. Return calls fronl sys,·
quired.
tern or user programs cause restoration of control to the Monitor. The keyboard listener
Data handling - providing the data buf(KLIST) accepts input comInands from the telefering and internal line and character
type and handles Monitor initialization and booktransmission facilities.
keeping.
File handling - providing for the manipulation of named files on the systenl
level.

lOPS completely eliminates the need for the programmer to program the standard peripheral devices. The programmer is no longer concerned
with input/output problems such as timing,
overlap, and the differences in the characteristics
of peripheral devices. This permits him to concentrate on his primary task, the processing of
da ta inside the com pu ter.
lOPS is coded on a modular basis to allow addition of new devices and modifications to the
handling of current devices. I t requires considerably less effort to modify an lOPS subpro2-6

The Keyboard Monitor allows convenient single
job processing through commands to the console
teleprinter. Its primary functions are: to allow
the user direct and immediate access to system
user programs stored on bulk storage devices;
to facilitate the creation and storage of new programs by the user; and to allow input/output
devic&-independent programming with "loadtime" specification of peripherals.

The Monitor command decoder (MCD) recognizes requests for system programs and loads the
system loader to bring in the requested program. In response to keyboard commands, it
also manipulates the device assignment tables to
provide the device-independent programming
features. The Monitor lOPS include data handling subroutines, and device handlers and interrupt service routines for the Teletype keyboard.
and printer. The routines for the system device
will also be present with the Keyboard Monitor,
but all other lOPS routines will be stored on
the system device until required by object programs.
The monitor also contains device assignment
tables. The purpose of the DA Ts is to relate

logical I/O units to the actual hardware devices.
Each input or output reference within a system
or user program refers to a position in a device
assignment table. This table, in turn, contains a
device assignment for each table entry that may
be used. Since the contents of the tables can
be altered by commands to the Keyboard Monitor, actual I/O devices may be changed without
altering the program references to these devices.

MAIN DEC DIAGNOSTIC PROGRAMS

Expansion of PDP-9 ADVANCED Software
System

MAINDEC diagnostic programs are provided for
locating hardware malfunctions within the processor, memory, and I/O equipment.
These programs are designed to make troubleshooting fast and straightforward by selectively
exercising every circuit in the machine. Instructions and procedures for loading, operating, and
interpreting the results of diagnostic tests are
written in clear, simple language, so that beginning maintenance technicians can use them easily.

The above-mentioned features of the PDP-9 ADVANCED software system are available at this
time. Included in the initial system design, but
not scheduled for completion until November
1968 are:

Detailed error messages are printed out to tell
the technician exactly which instruction, or bit
configuration, has failed. Error codes direct the
troubleshooter to specific modules when a fault
condition is detected.

Time-shared use of the PDP-9/L by a protected
priority foreground program and unprotected
system or user background program. This feature will utilize a background/foreground monitor and will require 16,384 words of core,
bulk storage, and the memory protection option.

The program consists of two parts: the Basic
Processor Test and the Extended Processor Test.
The Basic Test incrementally checks the entire
instruction repertoire, performing 1500 unique
tests, and in each case, halts with specific instructions for the troubleshooter. If the Basic
Test fails to detect the trouble, the Extended
Test uses random number techniques to test the
logic for many combinations of data manipulation and addressing problems, runs memory
test patterns, performs system tests on I/O devices and controls, and many other tests.

Batch processing from any peripheral device,
including the ability to accept monitor commands from any system input device.
Although these features will not be available with
the initial versions of PDP-9 ADVANCED software, all necessary provisions have been made for
them in the system programs.

A valuable tool for check-out and troubleshooting, MAINDEC diagnostics contribute to the high
productivity of the PDP-9/L by minimizing downtime.

2-7/2-8 (blank)

CHAPTER 3
SYSTEM ORGANIZATION
GENERAL
The major functional components of the PDP-9/L
system are the central processor, core melnory,
and input/output facilities. This chapter discusses these components and the options offered
for each.
CENTRAL PROCESSOR UNIT
Figure 3-1 illustrates the internal organization of
the PDP-9/L central processor. Employing a
transfer bus system, data is jam-transferred between registers at DC levels to minimize timing
problems (level logic is used instead of pulse
logic in the central processor). All active registers use simple circuit designs (no logic delays).

when the fetched instruction indicates indirect
addressing.
Control Memory (CM) - The CM stores all sequences of internal microinstructions required to
fetch and execute a program's.instructions, to
effect operation of the data channels, and to respond to operator commands initiated at the control console. It is a very fast, read only, magneticcore storage unit, prewired with the sequences.

Control Register (CR) - The CR delivers gate control signals to the transfer busses and to the active
registers. The register supplies new address information to the CM based on conditions sensed.
Maj or registers in the processor are:

FROM
SYSTEM
MEMORY
REGISTER OUTPUT GATES
TO SYSTEM MEMORY

MQ
REGISTER INPUT GATES

I/O

OUT

I/O

Figure 3-1. Central Processor-Major Register
Organization
Control Elements (not illustrated) that govern
the gating of information transfers include:
Instruction Register (IR) - The IR accepts the five
most significant bits of each instruction word
fetched from memory. The four most significant
bits constitute the operation code and, when decoded, indicate the entry point to the control
memory microinstruction sequence necessary to
effect system response. The fifth bit signals

Adder (ADR) - The 19-bit ADR functions as a
fast adder for arithmetic operations, and as the
transfer path for all inter-register transfers and
shift operations. It also increments the PC and MB
registers, as required. Entry to the ADR is via the
A bus and/or the B bus, under control of CRdeveloped gating control levels. The ADR operates
at a 5 mc rate to provide an inter-register transfer
time of 200 nsec.
Accumulator (AC) - The AC, an IS-bit register, retains the result of arithmetic/logical operations for
the interim between instructions. The AC can be
cleared and complemented. Its contents can be
rotated right 'Or left with the link. The contents of
the memory buffer register can be added to the contents of the AC with the result left in the AC. The
contents of both registers can be combined by the
logical operations AND and exclusive OR, the
result remaining in the AC. The inclusive OR can
be formed between the AC and the Data switches
on the operator console and the result left in the
AC. For all program controlled transfers, information is transferred between core memory and an
external device through the accumulator.
Link (L) - This I-bit register is used to extend the

arithmetic capability of the accumulator. In 1s
complement arithmetic, the link is an overflow
indicator; in 2s complement arithmetic, it logically
3-1

extends the AC to 19 bits and functions as a carry
register. The program can check overflow into the
link from the accumulator to greatly simplify and
speed up single and multiple precision arithmetic
routines. The link can be cleared and complemented
and its state sensed independent of the AC. It is
included with the AC in rotate operations and in
logical shifts.

System core memory can be expanded from the
basic 4,096 words up to 32,768 words in 4,096
word increments. Expansion beyond 8,192 words
requires implementation of the optional IVlemory
Extension Control, Type KG09A to extend the
PDP-9/L addressing capability.
INPUT /OUTPUT FACILITIES

Arithmetic Register (AR) - The AR functions
with the AC to perform arithmetic and logical operations. It is not accessible to the programmer. Its
operation is a function of the micro-instruction
sequences in the CM.
Multiplier-Quotient Register (MQ) - The optionally implemented extended arithmetic element
(EAE) adds the logic of the MQ to the basic
PDP-9/L. The MQ is 18 bits long and holds the
multiplier during multiplying instructions and receives the low-order 18 bits of the resulting product.
During division operations it holds the
low-order 18 bits of the dividend and, at the
completion of the divide instruction, it contains
the quotient. It can also be used an an extension of the AC for 36-bit shift operations and
for data normalizing operations.
Program Counter (PC) - The PC determines the
program sequence; that is, the order in which
instructions are performed.
This 13-bit register contains the address of the memory cell
from which the next instruction is to be taken.
Addition of the memory extension control option
expands the PC to 15 bits for the addressing of
up to 32,768 locations.
Memory Buffer Register (MB) - All information
transferred into or out of core memory passes
through the 18-bit MB. Information is read
from a memory cell into the MB and rewritten
into the cell in one cycle time. Instructions and
data are brought from core memory into the
MB for processing. The MB serves also as a buffer for information transferred between core
menlory and an external device in data channel
transfers.

The following text briefly describes the input/
output facilities provided with the PDP-9/L in its
minimum (basic) configuration. Detailed descriptions concerning the operation and use of these
facilities are presented in chapter 9, Input/Output
Operations.
Basic PDP-9 I/O facilities include:

A I/O bus system which chain links aU
the device controls for all peripheral devices to the central processor unit (CPU).

A data channel control governing concurrent (non-overlapping) operation of
eight data channels"

A program interrupt control.

An I/O status-read provision.

A conditional skip-on-device-status pro-vision.

The PDP-9/L apportions I/O control between the
CPU and the various device controls interfaced
to the I/O facilities. The complexity of any device control is thus a function of the type of
device and of the facilities which it must make
use of to accomplish its system purpose. This
scheme has several benefits for the user.
1.

It negates the need for expensive I/O
processors or controllers.

The structure of the I/O system can be
expanded or reconfigured at anytime
without modification of the CPU .

User-designed or special purpose equipment can be easily interfaced to the PDP-9
through the inexpensive fabrication of
the required device: control units.

CORE MEMORY
The PDP-9/L utilizes a 4-wire 30-stack core memory with a complete cycle time of 1.5 microseconds. Each 4,096 word core memory module
contains a core stack, sense amplifiers, drivers,
and a memory address (MA) register. The MA
sets up the memory location (address) to be
used for data retrieval or storage.

3-2

Peripheral equipment may either be asynchronous
with no timed transfer rates or synchronous with
a timed-transfer rate. Devices such as the CRT

displays, teleprinter-keyboard, and the line printer
can operate at any speed up to the maximum
without loss of efficiency. These asynchronous
devices remain on and ready to accept data; they
do not turn themselves off between transfers.
Devices such as magnetic tape, DECtape, and
card equipment are timed-transfer devices and
must operate at or near their maximum speeds
to be efficient.
The I/O bus consists of command lines and bidirectional data lines for use in accomplishing
program-controlled transfers or data channel
transfers; plus the use of the program interrupt
control, the I/O status-read and conditional skipon-device-status provisions, and the Automatic
Priority Interrupt system option Type KF09A,
if implemented. The program-controlled mode
functions with single word or byte (up to 18
bits, parallel) transfers made under control of
programmed instructions. The data channel mode
permits block transfers at high speed without interruption of the program in progress.
All I/O data transfers function with the precedence of the following priority structure.
l.

Data channel requests

2. Real-time clock counting (clock is
considered to be an I/O device)
3. Priority interrupts, 8 levels (optional)

to initiate the specified operation. All program
controlled transfers are executed through the
accumulator (AC) in parallel bytes up to 18 bits
in length.
For an "out" transfer, the program reads a data
word from memory into the AC. A subsequent
lOT instruction places the data on the bus,
selects the device, and causes it to enter the word
in its data buffer register. For an "in" transfer,
the process reverses. An lOT instruction. selects
the device and causes the contents of its data
buffer to be gated onto the I/O bus. In turn,
the word is strobed into the AC and read, by
the program, into memory.
Conditional Skip on Device Status
The PDP-9/L order code has in its lOT family a
group of instructions for testing the status of
peripherals. An instruction of this type directs
the processor to either skip or proceed to the
next instruction as a result of the test. The
feature can be thought of as programmed decision
making. For example, a program accepting
typed input from the console teleprinter might
make use of the following sequence in a teleprinter service subroutine.

KSF
JMP .-1
KRB

/SKIP NEXT IF CHARACTER IN BUFFER
/RECHECK KEYBOARD BUFFER
/READ BUFFER INTO AC

4. Program interrupts
5. Main program in progress (lowest
priority)
A higher priority request for service interrupts
any in-process service of a lower priority at the
end of the current instruction. Program interrupts and priority interrupts require that the
main program transfer control to specific service
subroutines. These routines restore control to
the program at completion of the service interval. Computer-granted breaks satisfy data channel requests; i.e., program execution is delayed
but not disturbed while the data channel transfers information between memory and the requesting device via the MB.
Program Controlled Transfers
Program controlled transfers are made by lOT
(input/output transfer) instructions contained in
the main program or in service subroutines.
These instructions are microcoded to effect response only for a particular device. The microcoding includes issuing a unique device selection
code and appropriate processor-generated pulses

Although simple to implement, I/O servicing of
this form adds to a program's "overhead" as the
subroutine remains in the two-instruction loop
until the skipping condition is satisfied.
Input/Output Read Status
The input/output read status facility provides for
programmed interrogation of external device
status. Upon execution of an 10RS (input/output
read status) instruction, the states of those device
flags (done, busy, not ready, etc.) interfaced to
the facility by the I/O bus are transferred to
specific assigned bit positions of the AC. The
program may check for specific flag conditions
or the user may view the flag states as selectively
displayed in indicators on the control console.
For bit assignments, see Figure 9-l.
Program Interrupt
The program interrupt (PI) facility offers a more
efficient method of I/O servicing. The computer
continues with execution of a program until a
3-3

register, both held in sequential memory locations
for each data channel (30, 318 for data channel
0; 32, 33 for 1; 34, 35 for 2; and 36, 37 for 3).
Memory allocation for the remaining four channels
is at the user's discretion. The word count
register is initialized to minus the nunlber of words
to be transferred plus one. The current address
register is initialized to the starting address minus
one of the sequential block of memory locations
which are to deliver data to or receive data from
the peripheral device.

previously selected peripheral signals that it is
ready. At that time, the program in process
interrupts and transfers control to a service subroutine. When completed, the subroutine restores the computer to the status prior to the
interrupt, allowing the interrupted program segment to continue. Where multiple peripherals are
connected to the PI, a search routine with device status testing (skipping) instructions must
be added to determine which device initiated the
interrupt request. This routine transfers control
to the appropriate I/O service subroutine. The
PI is itself considered an I/O device in that a
program or subroutine thereof can include instructions for enabling or disabling the facility.
When disabled, the PI ignores all services requests.
Such requests normally remain on-line, however,
and are answered when the PI is again enabled.
The PI is automatically disabled when an interrupt request is honored. The interrupt-accessed
subroutine is responsible for re-activating the
facility.

When the data channel request is granted by the
processor, the device transnlits the address of ilts
data channel word count register. During the
first cycle, the contents of this register are incremented by one and then the effective address of
the current address register is established. In lthe
second cycle, the contents of the current address
register are incremented by one to establish the
effective address of the memory location delivering or receiving the data word. During the third
cycle, or fourth cycle in the case of out transfers,
the actual data transfer occurs.

Data Channels
The eight data channels included in the basic
PDP-9/L I/O facilities employ the I/O bus system
for block data transfers between core memory
and high data rate peripherals such as DECtape
and standard magnetic tape transports. The data
channel control can concurrently service up to
eight devices. The priority of service is established by the hardware interface. Data channel
requests for service are answered upon completion of the instruction currently being executed
by the computer. An in-process data channel
transfer cannot be interrupted by a data channel request of lower priority, but it can be interrupted by a direct memory access channel"
request for service at completion of the current
machine cycle. An interrupted data channel
transfer continues with completion of the DMA
channel action. On-line data channel requests
for service are answered in turn on the basis
of their priority relationship.
Each data channel functions with processorgranted breaks to interleave its transfers with execution of the program in progress. These transfers occur via the MB and do not disturb the
contents of other active registers in the processor (AC, PC, etc.). Data is read into memory
in three machine cycles and out of memory in
four cycles (the additional cycle allows I/O bus
settling and the setting of control gates prior to
the strobing of the data word into the device's
buffer register).
The block transfer is initiated by an lOT (input/
output transfer) instruction following initialization
of a word count register and a current address
3-4

The device continues to request service until it
receives an indication that the block transfer has
been completed. At that time, it can initiate a
program interrupt to access a subroutine for the
re-initialization of the data channel's word count
and current address registers. Because the block
transfers are automatic in nature, the programmer
need only concern himself with providing the
appropriate subroutine or subroutines to initialize
data channel operations.
Add-to-Memory Capability

,
This capability permits incrementing the contents
of an externally specified nlemory location in one
memory cycle, or adding the contents of an external register to the contents of a memory word in
four memory cycles. A device on the DCH system
can request these actions by signaling on appropriate lines of the I/O bus. These features were
originally included in the extra-cost KH09A option.
The increment capability (MB+ 1) is comrrlonly
used when data in histogram form is de.;ired (such
as pulse height analysis data). After each data
point is developed by external hardware, it is
placed on the address lines (thereby specifying a
memory location) and an Increment MB request is
made. An I/O OVFLO pulse is returned to the
device if the increment causes the specified word
to go to zero.
The request for an increment cycle is honored
after completion of the current instruction. If
successive increments are requested, one instruction of the current progranl will be executed
between each increment break.

The add-to-memory capability is used in signal
averaging where on successive scans through an
independent variable (such as time), the data
from the dependent variable (such as voltage)
is added into that already collected. Data
placed on the data lines is added to the contents
of the location specified by the data channel
current address counter. A DATA OVFLO
pulse is returned to the device if the sum exceeds 2 18-1.
The request for an add-to-memory operation is
honored after completion of the current instruction. If successive requests are made, they will
be honored back-to-back, every four memory
cycles.
OPTIONS
Incorporation of the following central processor
related options expands the data processing
capabilities of the basic PDP-9 system, provides
increased efficiency for input/output operations,
and simplifies the programming and execution
of arithmetic operations.
Extended Arithmetic Element, Type KE09A
The extended arithmetic element facilitates highspeed multiplication, division, shifting, normalizing, and register manipulation. Installation of
the EAE adds an 18-bit multiplier quotient
register (MQ) to the computer as well as a 6bit step counter register (SC). The contents
of the MQ are displayed by the REGISTER
indicators on the operator's console when the
REGISTER DISPLAY control is in the MQ
position. The option and the basic computer
cycle . op~rate asynchronously, permitting computatIons to be performed in the minimum
possible time. Further, the EAE instructions
are microcoded so that several operations can
be performed by one instruction to simplify
arithmetic programming. Average multiplication time is 11 microseconds; average division
time is 12 microseconds. The PDP-9/L program library offers a complete package of
single- and multi-precision routines for use with
this option. EAE instructions are described
in chapter 7, Instructions.
Memory Extension Control, Type KG09A
The memory extension control allows expansion
of PDP-9/L core memory from 8,192 to 32,768
words in increments of 4,096 words. The option
includes a 2-bit extended program counter
2-bit extended memory address register, a~d an
extend mode control. Locations outside the
current 8,192-word field are accessed by indirect
addressing while in the extend mode. In this

mode, bits 3-17 in the effective address of an
indirectly addressed instruction specify the
memory bank number (bits 3 and 4) and the
memory address (bits 5-17). If not in the
extend mode, bits 3 and 4 of the effective
address are ignored and the bank number is taken
from the extended program counter. Instructions
for the option are discussed in chapter 6 under
Extend Mode Addressing. The state (i.e., on or
off) of the mode is automatically saved in the
event of a program interrupt, or CAL or JMS
instruction (refer to chapter 6 under "reserved
address"). A program interrupt disables the
extend mode. The saved state can be automatically restored by the instruction sequence of
DBR followed immediately by JMP I, where the
address for the latter instruction is 00000,
00020 or Y for, respectively, a program interrupt,
CAL, or JMS (Y refers to the. address previously
specified by the JMS instruction).
Additional Core Memory
Up to seven 4096 word core memory modules
may be added to a PDP-9/L for expansion of
random-access storage up to 32,768 18-bit words.
The memory extension control Type KG09A is
required when more than 8,192 words are
implemented.
Power Failure Protection, Type KP09A
The basic PDP-9/L is not affected by power interruptions of less than 10 msec duration. Active
registers in the processor (AC, AR, PC, etc) will
lose their contents for interruptions of longer
duration but memory is not disturbed. The
power failure protection option extends the
period of nonaffect by power interruption to
25 msec. In addition, the option provides for
the saving of active register contents in the event
of longer power interrupts and the automatic
restart of the system when power is restored.
The restart feature is switch-selected by the
operator to be enabled or disabled. When
enabled, the program in progress resumes
execution at location 00000. The system must
be operating with the program interrupt facility
enabled to sense the option's initiation of a
program interrupt to save the register contents
at the time of the line power failure. The
option adds the following instruction:
70320 18 - Skip next instruction if power-low
flag is set.
Memory Protection Option Type KX09 A
The memory protection feature establishes a
foreground/background environment for PDP-9/L
processing activity by specifying the boundary
3-5

between protected (lower) and unprotected
(upper) regions of system core memory.
Allocation of memory locations (in increments
of 1024 words) to the protected region is
dynaInic and program controlled. A Boundary
Register, added by the option, stores the location of the upper limit of the protected region.
I t is loaded fron1 bits 3-7 of the AC by a
MPLS instruction.
The KX09A monitors the instruction about to
be executed, and transfers control to a monitor
program (should the instruction be in the category of "illegal instructions") before the instruction is executed. If a program tries to reference
a nonexistent memory bank, the KX09A, if it
has been enabled, transfers control to the rnonitor program.
The memory protect (or user mode) may be
enabled either by programmed instruction, or
by placing the PRTCT switch on the console
UP, and pressing the START key. When
enabled, the option will trap the following:
lOT - Input/Output
CAF - Clear All Flags
XCT of XCT - Chained Execute Instructions
HLT - Halt
OAS/LAS - Load AC from Data Switches
References to nonexistent memory
References to locations below the boundary
limit
Trapping causes the execution of an effective
JMS instruction after the machine cycle that
attempts to violate. The address referenced
by the effective JMS instruction will be location absolute 20 if the program interrupt
facility is disabled, or location absolute 0 if
the program interrupt facility is enabled.
The Violation Flag is set.
The NonExistent Memory Flag is also set if
the violation was caused by a program or
DCH reference to nonexistent memory.
User mode is disabled in the following ways:
I/O Reset Key
The detection of a violation
CAL Instruction (which never causes a
violation)
A Program Interrupt
An API Interrupt

3-6

If user mode is enabled when an API break
starts, and the API Channel Address contains
a HLT, OAS, or lOT - rather than the normal JMS - that instruction will be inhibited,
user mode will be disabled in the normal
fashion and no violation will be detected"
If user mode is disabled when a reference
to nonexistent memory is made, the N onExistent Memory Flag is set, no trap
occurs, and the program continues after a
one microsecond pause. If a reference to
nonexistent memory occurs when user mode
is enabled, the Violation Flag is also set and
the trap occurs.

HLT, OAS and lOT instructions are totally
inhibited when the memory protect option
is enabled. If the HLT or OAS is combined with any other operate group instruction (micro-programming), the other parts
of the operate group instruction are executed
before the trap. (The exception is SKP which
is not executed - see Exarrlple 2). The second
XCT in a chain of XCT instructions is trapped
before execution.
The state of the protect nlode (a "1" for user
mode) is stored in bit 2 - the storage word
by those operations that save the state of the
machine (CAL, JMS, PI). The stored PC will
contain one more than the location of the
violating instruction, except for JMP to a protected area. In this case, the stored PC will contain the protected address.
The sole operator control is the PRTCT
switch, which has an indicator above it.
This indicator lights when in user mode. The
PRTCT switch is used in conjunction with the
START key to establish the proper mode at
the beginning of program execution. If the
switch is UP, then the program is started in
user mode. The switch has no further effect.
The 10 RESET key clears the boundary
register, Violation and NonExistent Memory
Flags, and user mode (i.e., memory protect
is turned off).
The option adds the instructions to the PDP-9/L
listed in Table 3-1.

TABLE 3-1

MEMORY PROTECTION TYPE KX09A INSTRUCTIONS
Operation
Executed

Mnemonic

Octal
Code

MPSNE

701741

Skip on NonExistent Memory Flag. The NonExistent
Memory Flag is set whenever the processor attempts
to reference a nonexistent area of core. For a 32K
machine, the flag would never get set.

MPSK

701701

Skip on Violation Flag. The Memory Protect Violation Flag will be set whenever the execution of an .
instruction has violated the provision of memory
protection (see above).

MPEU

701742

Enter user (protect) mode. Memory protect mode
will be entered at the end of the next instruction
that is not an lOT.

MPCV

701702

Clear Violation Flag.

MPCNE

701744

Clear NonExistent Memory Flag.

MPLD

701704

Load the memory protection boundary register with
the contents of AC3-7. The boundary register will
store the number of 1024 word blocks to be protected.

Associated with the option are additional indicators (shown below) which are located on
the main console.

Examples
Example 1

1000000001
PRVN

NEXM

USMD

BR 3

BR 4

BR 5

BR 6

BR 7

PRVN:

Lights when Violation flag is raised.

NEXM:

Lights when NonExistent Memory
Flag is raised

USMD:

Lights to indicate that the memory
protect mode (user mode) has been
entered. Logically identical to the
light above the PRTCT switch on
the console.

BR 3

Indicate the upper limit (in 1K increments of the protected region).

through
BR 7

77 - Main Program
100 - XCT 200
200 - XCT 247
247 - LAC 250
Should the main program reach location 100
with the user mode ON, the second XCT at
location 200 will violate, and control will
transfer to location 20 (assuming program interrupt facility is off). The contents of the PC (101)
together with the state of the link, Extend
Mode and User Mode will be stored in location
20, and the next instruction taken from location
2l.
Example 2

76
77 - Main Program
100 - XCT 200
200 - HLT SKP

3-7

Here, the HLT will cause the violation, (one
XCT :is allowed). The SKP will be ignored and
the PC will be stored as 1a1.
Example 3

76
77 - Main Program
100 - XCT 200
200 - HLT CLA
Same as Example 2 except the AC will be
clearedl before the trap occurs.
Example 4

Assume boundary to be at address 2000, protection is for register a through 1777.
400 - 3000
3000 - TAD I 400
This is legal, although address 400 (which is
below the boundary) has been referenced,
because the final reference is above the
boundary.

Example 5

Boundary again at address 2000
400 - 1000
3000 - TAD I 400
This will be trapped, as address 1000 was the
final reference, and address 1000 is below the
boundary.
AutOluatic Priority Interrupt, Type KF09A
The automatic priority interrupt (API) syste1TI
adds eight additional levels of programming
priority to the PDP-9/L. The upper four
levels are assigned to devices and are initiated
by flags (interrupt requests) from these attached
devices. The lower four levels are assigned to
the programnling system and are initiated by
softw'1-re requests. The priority network insures
that high data rate or critical devices will always
interrupt slower device service routines while
holding still lower priority interrupt requests off
line until they can be serviced. The API identifies
the source of the interrupt directly, eliminating
the need for a service routine to flag search.
The key elements in an interface to the API are
priority level and channel. Each I/O device
interfaced to the API is assigned to one of the
3-8

four device priority levels so as to maximize
performance of the I/O system.
The channel assignment of every device and
software request is fixed and cannot be changed.
Each of the 32 channels has a correspondling
channel address in core memory. This adldress
contains a JMS instruction to the service subroutine. The execution of lout of 32 unique
JMS instructions is the API's method of directly
identifying which source caused the interrupt.
The API operates in the following manner. An
I/O device requests service by transmitting an
interrupt request signal to the processor on a line
corresponding to its specific, preassigned priority
level. If this priority level is higher than the
priority of the device which requested the:
currently active program segment, an interrupt is
granted to the new device. Upon receipt of the
grant signal, the device transmits its channeladdress back to the processor. The processor
executes the instruction in the specified memory
address; this is always a JMS to the device
service subroutine. The new priority level is
remembered and no further servicing of this or
lower priority levels is permitted until the device
service subroutine is exited.
The hardware insures that simultaneous requests
by multiple devices are handled in the proper
priority sequence. If interrupt requests occur
at different priority levels, the highest priority
request will be serviced first. If multiple
interrupt requests occur at the same priority
level, the device closest on the bus to the
processor will be serviced first. The entire
API system may be enabled or disabled with a
single instruction; however, many devices provide facility to separately connect and disconnect their flags from the interrupt.
A chief advantage of this API system lies in
the proper use of the software levels. In the
real-time environment, it is necessary to maintain data input/output flow, but it is not possi-'
ble to perform long, complex calculations at
priority levels which shut out these data transfers. With the API, a high priority data input
routine which recognizes the need for the complex calculation can call for it with a software
level interrupt. Since the calculation is performed at a lower priority than the data handling,
the latter can go on undisturbed. Further, there
is no need to interface the data collection routine
with the lowest priority (background) program
which may run independently of the real-time
system. Refer to chapter 9 for descriptions of
the API instructions and the programming
considera tions

CHAPTER 4
PERIPHERALS
GENERAL
This chapter describes both the standard peripherals and the optional peripherals offered with
PDP-9/L. Information regarding the instruction
word format and the coding of the lOT (input/
output transfer) instructions can be found in
chapter 7 under lOT Instructions.
STANDARD INPUT/OUTPUT EQUIPMENT
Standard input/output equipment supplied with
each PDP-9/L consists of a Model ASR-33 Teletype and control, with associated perforated
tape reader and perforated tape punch.
The Teletype Model ASR-33 consists of four
functional units: keyboard, teleprinter, paper
tape reader, and paper tape punch. All units
operate at 10 characters per second. The input
and output functions are independent, but the
two input units (keyboard and reader) cannot
act independently, nor can the two ou tpu t units
(teleprinter and punch).
The teletype interface is both full duplex and
half duplex. A switch on the back of the I/O
frame is used for selection. The COMPACT
software system uses the full duplex teletype.
The ADVANCED software system uses the half
duplex teletype. (A full duplex interface is one
that permits the input and output operations to
proceed independently. If input characters are
to be printed (echoed), they must be transTABLE 4-1
Mnenlonic
SYlnbol

Octal
Code

KSF

700301

KRB

700312

KRS

700332

mitted back out to the teletype by the computer. A half duplex interface does not permit
independent input and output operations. Input characters are automatically printed without intervention by the program.)
The keyboard and teleprinter device flags are interfaced to the I/O skip facility, the program interrupt control, and to bits 3 and 4, respectively, of the IORS (input/output read status) word.
(Refer to chapter 9, Input/Output Considerations, for a discussion on the use of the IORS
word.) The state of these bits can be seen in
the REGISTER indicators when the machine is
in the stop condition and the REGISTER DISPLA Y control is in the STATUS position.
Keyboard
The keyboard control contains an 8-bit buffer
which assembles and holds the code for the last
character struck on the keyboard. The keyboard
flag becomes a 1 to signify that a character has
been assembled and is ready for transfer to the
accumulator. This flag may be cleared by command.
The keyboard instructions are listed in table 4-1.
Reader
Data from the reader enters the computer in
the same way that keyboard 'data does. There

KEYBOARD INSTRUCTIONS
Operation
Executed
Skip if the keyboard flag is set to 1. If
the flag is a 0, the next instruction is
executed. If it is 1, the next instruction
is skipped. The flag is set only when a
character has been completely assembled by
the buffer.
Read the keyboard buffer. The content of
the buffer is placed in bits 10-17 of the
cleared AC and the keyboard flag is cleared.
Bits 0-9 of the AC remain cleared.
Select the keyboard reader if the START
switch is engaged.

4-1

is an additional lOT instruction to initiate the
reading of paper tape.

The reader instructions are listed in table 4-2.
Teleprinter
The teleprinter control contains an 8-bit buffer
which receives a character code from AC bits
10 through 17. The buffer receives the 8-bit
code from the AC in parallel and transmits it to
the teleprinter serially. When the function called
for by the 8-bit code has been executed, the
teleprin ter flag is set to 1. This flag is connected to the computer program interrupt and
input/output skip facility. It is cleared by
programmed comlnand.
The teleprinter instructions are listed in table 4-3.
A TLS instruction should not be executed until
a TSF instruction verifies that the teleprinter
flag is set. The teleprinter requires 110.04 msec
to conlplete the action called for by an entered
character code (print a character, line feed, carriage return, etc.), The teleprinter flag is again
set at the end of this interval. The time between teleprinter flags is available to the program.
TABLE 4-2

Data for the punch is transmitted in the same
fashion as for the teleprinter. Note that the
punch enable switch on the ASR-33 must be
turned on for punching to take place. The in-·
structions for the punch are the same as for
the teleprinter and are interpreted as directed
in table 4-4.

OPTIONAL PERIPHERALS
Teletype Model 33 KSR and Control
The Teletype Model 33 KSR (keyboard send receive) is usually selected for systems using a high
speed paper tape reader and punch (PC09A).
The 33 KSR can be used to type in or p:rint
out information at a rate of up to ten characters per second. Signals transferred between the
33 KSR and the keyboard printer control logic
are standard serial, II-unit code Teletype signals.
The signals consist of marks and spaces which
correspond to idle and bias current in the Teletype and zeros and ones in the control and computer. The start mark and subsequent 8-character bits are represented by single units of time
duration followed by a 2-unit stop space.

READER INSTRUCTIONS

Mnemonic
Symbol

Octal
Code

Operation
Executed

KSF
KRB

700332
700301
700312

Clear reader flag.
Skip if reader flag is a "1".
Read reader buffer.

TABLE 4-3

4-2

Punch

TELEPRINTER INSTRUCTIONS

Mnemonic
Symbol

Octal
Code

Operation
Executed

TSF

700401

Skip the next instruction if the teleprinter
flag is set to 1.

TCF

700402

Clear the teleprinter flag.

TLS

700406

Load printer buffer. The content of AC bits
10-1 7 are placed in the buffer. The flag
is cleared before transmission takes place and
is set when the character has been printer.

TABLE 4-4 PUNCH INSTRUCTIONS

Mnemonic
Symbol

Octal
Code

TSF
TCF
TLS

700401
700402
700406

Each of the 64 printing characters and 32 control characters are represented by an 8-bit standard ASCII code. The Teletype eight-level character code is listed in appendix 2. As the teleprinter input and output functions are logically
separate, the programmer can consider the printer
and keyboard as individual devices. The console
teletype interface is half duplex.
The keyboard and teleprinter device flags are
interfaced to the I/O skip facility, the program
interrupt control, and to bits 3 and 4, respectively, of the IORS (input/output read status)
word. (Refer to chapter 9, I/O Considerations, for a discussion on use of the IORS word.)
The state of these bits can be seen in the
REGISTER indicators when the machine is in
the stop condition and the REGISTER DISPLAY
control is in the STATUS position.
Keyboard
The keyboard control contains a 8-bit buffer
which assembles and holds the code for the, last
character struck on the keyboard. The keyboard
flag becomes a 1 to signify that a character has
been assembled and is ready for transfer to the
accumulator. This flag may be cleared by command.
The keyboard instructions are listed in table 4-1.
Teleprinter
The teleprinter control contains an 8-bit buffer
which receives a character code from AC bits 10
through 17. The buffer receives the 8-bit code
from the AC in parallel and transmits it to the
teleprinter serially. When the function called for
by the 8-bit code has been executed, the teleprinter flag is set to 1. This flag is connected
to the computer program interrupt and input/
output skip facility. It is cleared by programmed command.
The teleprinter instructions are listed in table 4-3.

Operation
Executed
Ski P if punch flag is a "1".
Clear punch flag.
Load punch buffer.

A TLS instruction should not be executed until
a TSF instruction verifies that the teleprinter
flag is set. The teleprinter requires 110.04 msec
to complete the action called for by an entered
character code (print a character, line feed, carriage return, etc.). The teleprinter flag is again
set at the end of this interval. The time between
teleprinter flags is available to the program.

NOTE: In half duplex mode, the keyboard has
priority over the teleprinter; i.e., if a key is
struck while the teleprinter buffer is transmitting
a character code to the Teletype, the character
code relating to the struck key will be entered
in the keyboard buffer and the keyboard flag
will be set to initiate a program interrupt. The
disruption of the teleprinter function will garble
the character code being sent to the Teletype
from the teleprinter buffer. The Teletype action
defined by this garbled code is unpredictable.
Thus, one character of output data is lost.
Perforated Tape Reader Type PC09A
The perforated tape reader and its associated control are designed and manufactured by the Digital Equipment Corporation. The reader functions
with a stepping motor and feed-hole drive to
photo-electrically sense 8-channel paper tape at
the rate of 300 characters per second. The control requests reader motion, transfers data from
the reader to the reader buffer register, and signals the computer when the buffer has assembled
data for input to the computer. In order to
maintain maximum reader speed (300 cps), a new
select lOT must be issued within 1.67 msec.
Data may be read froln tape in either alphanumeric or binary modes, as determined by lOT
select instructions. In the alphanumeric mode
(figure 4-1 a), each select instruction causes one
line of tape, consisting of eight bits, to be read
and placed right justified in the I8-bit buffer
register. In the binary mode (figure 4-1 b), each
select instruction causes three lines of tape to be

4-3

CHANNEL

8
,--A---.

6
,..--A---,

I 10 I tt I 12 I t3 I 141151 161 I~

UNUSED

L-y-J

'-y----J

"----y-J

CHANNEL

TAPE CHANNEL
7

DIRECTION OF
TAPE MOVEMENT

FEED

READ BY ONE
lOT INSTRUCTiON

00 000
00 00 0
00 000

a. Tape Format and Reader Buffer Register Bit Assignments
in Alphanumeric Mode
FIRST LINE READ

SECOND LINE READ

CHANNEL
6

CHANNEL

CHANNEL
2

,.--"--.,

,---A--,

[a ]

]

--"

"
CHANNEL

CHANNEL

4
~

6
~

CHANNEL
2

]

"--y----J

~-I

"---y--J

CHANNEL

CHANr~EL

CHANNEL

MUST BE PUNCHED

DIRECTION OF
TAPE MOVEMENT

CHANNEL

CHANNEL
2

,....--A-.....,

,..--A---,

'----y---J
CHANNEL
1

FEED

•
000 0000
•
000 0000
.0000 o
•
000 o

NORMALLY NOT PUNCHED

~-'

CHANNEL

*Note: In hardware readin mode,
channel 7 must be punched in line
3 of last data word or read will
not stop (refer to chapter 10 for
description of READ I N key).

TAPE: CHANNEL

}

FIRST LINE READ

}

SECOND LINE READ

}

THIRD LINE REAl:)

h. Tape Format and Reader Buffer Register Bit Assignments
in Binary Mode
Figure 4-1. Perforated Tape Format
4-4

CHANNEL
6

]10 ] 11 ]12 ]13 ] 14]15]16]17]

CHANNEL

THIRD LINE READ
l.....-

}
BY ONE IOT
INSTRUCTION

read. Six bits of each tape line read are assembled in the buffer to form one IS-bit computer
word. The seventh bit of a tape line is ignored.
A line is not read, however, unless the eighth
bit is punched. A "reader buffer" instruction
transfers the contents of the reader buffer to
the computer's accumulator.

The tape reader lOT instructions are listed in
table 4-5.
Tape Reader Use - In loading tape for readin,
observe the following practices:

Reader facilities include a right-hand bin for supply of the tape being read, a left-hand bin for
receiving the tape, and a feed-through control to
complete passage of the tape into the receiving
bin following the readin operation. A snapaction tape retainer on the reader platfornl allows simple tape loading.

Raise the tape retainer and load the tape
into the right-hand bin with channel one
(figure 4-1) toward the rear. Place several folds of the tape leader in the lefthand bin and position the tape on the
platform with the feed holes engaged by
teeth of the drive gear. Snap the retainer down.

Primary power is made available to the reader
when the computer POWER control is set to ON.
All operations of the reader are under program
control.

Momentarily depress the tape feed control. This action corrects any misalignment of the tape with respect to the
drive teeth, and it clears the reader outof-tape flag.

Set the address switches (numbered 3-17
on the console) to the starting address
for the readin and depress the I/O Reset
key and then the READ IN key to initiate
reading of the tape.

The tape reader device flag is interfaced to the
I/O skip facility, the program interrupt control,
and to bit 1 of the 10RS (input/output read
status) word. The tape-reader-no-tape flag* is
interfaced to bit S of the 10RS word. (Refer
to chapter 9, I/O Considerations, for a discussion on use of the 10RS word.) The state
of these status bits can be seen in the REGISTER indicators when the machine is in the stop
condition and the REGISTER DISPLAY control
is in the STATUS position. The tape reader
device flag is also interfaced with the API
(priority level, address 50).
Tape Reader lOT Instructions - Observe the
following sequence for instructions required to
effect the transfer from paper tape to the AC.
1.

Select the mode and clear the buffer. * *

Wait for reader flag (indicates that buffer has been loaded).

3. Transfer buffer contents to the AC.
*Note: All program tapes should be provided
with trailers (i.e., sections of feed-hole only
punched tape) since the reader may not halt
immediately upon detection of a no-tape indication. Reading of a non-trailered tape will result
in the entry of invalid data as the reader indexes
beyond the end of tape point., A no-tape condition, in addition to setting the tape-reader-notape flag, sets the reader flag to 'initiate a program interrupt.
**N ote: A programmed check of tape presence
(i.e. not a no tape condition) may precede
this'sequence (refer to 10RS discussion in
chapter 9).

Perforated Tape Punch
The perforated tape punch unit, pac~aged on the
same chassis as the tape reader, consIsts of a
solid-state control and a mechanical punch mechanism. It perforates paper tape at the rate of 50
characters per second. When the punch is selected by an lOT instruction, data in the accumulator is transferred to the punch buffer and then
without further instruction punched in the tape.
A magazine for unpunched tape and a box for
tape chad are located internally. Both are accessible when the reader-punch drawer is pulled forward on its slides. Power for the punch motor
is available when the computer POWER control
is in the ON position. The motor runs only
when the punch has been, selected, however.
Operation of the punch is by programmed instructions. An out-of-tape switch, on the punch
mechanism and through which the unpunched
tape passes, closes to inhibit punch op~ration
when approximately one inch of tape IS left.
The paper tape punch device flag is interfaced
to the I/O skip facility, the program interrupt
control and to bit 2 of the 10RS (input/output
read st~tus) word. The tape-punch-no-tape flag*
is interfaced to bit 9 of the 10RS word. (Refer
*Note: The tape-punch-no-punch condition will
not initiate a program interrupt.
4-5

TABLE 4-5 TAPE READER lOT INSTRUCTIONS

Mnemonic
Symbol

Octal
Code

Operation
Executed

RSF

700101

Skip the next instruction if reader flag is a 1.

RCF

700102

Read reader buffer. Clear reader flag, then inclusively OR contents of reader buffer into the
AC. RB V AC~AC

RRB

700112

Read reader buffer. Clear reader flag. Clear
AC and then transfer contents of reader buffer
to AC. RB~AC

RSA

700104

Select reader in alphanumeric mode. One 8-bit
character is read and placed in the reader buffer
(right justified). The reader flag is cleared before
the character is read. When transmission is
complete, the flag is set to 1.

RSB

700144

Select reader in binary mode. Three 6-bit characters are read and assembled in the reader buffer. The flag is cleared during assembly and set
when character assembly is completed.

to chapter 9, I/O Considerations, for a discussion
on use of the 10RS word.) The state of these
status bits can be seen in the REGISTER indicators when the machine is in the stop condition
and the REGISTER DISPLAY control is in the
STATUS position,.
Infornlation is handled by the punch in either
alphanumeric or binary modes. In the alphanumeric mode each select instruction causes one
line of tape, consisting of eight bits to be punched. Each hole punched in a tape channel corresponds to a binary 1 in the appropriate bit of
the punch buffer. A feed hole is punched for
each command, even if the buffer contains all
zeros. The correlation between tape channels
and accumulator bits shown in figure 4-1 a applies to the tape punch in alphanumeric mode.
In the binary mode each select instruction causes
one line of tape, consisting of eight bits, to be
punched. Holes are punched in channels 6
through 1 as a function of binary ones in bits
12 through 17 of the accumulator, respectively.
Channel 8 is always punched and channel 7 is
normallly not punched, thereby conforming to
standard binary tape information format.

4-6

Use of Paper Tape Punch - The paper tape punch
is operated by programmed instructions. The
functions of the buttons located on the punch
enclosure are included here for user convenience.

FEED Button - while the button is depressed,
the punch produces feed hole only punched
tape for tape leader or trailer purposes.
Out-of-Tape Button - this button functionally
inhibits program use of the punch by simulating the out-of-tape condition for the punch.
Since punch I/O routines normally verify that
the punch out-of-tape flag is not set before
selecting the device, this simulation pennits
the user to replenish the tape magazine when
its contents have been exhausted, splice the
new tape to the existing tape (the FEED
button can be used to produce whatever length
of feed hole tape is necessary), and then de-,
activate the out-of-tape flag at his convenience.
Without this provision, the punch could be
program operated the instant that the out-oftape switch on the punch mechanism opened
as the new tape was fed in.

TABLE 4-6 TAPE PUNCH lOT INSTRUCTIONS
Mnemonic
Symbol

Octal
Code

PSF

700201

Skip the next instruction if the punch flag is
set to 1.

PCF

700202

Clear the punch flag.

PSA

700204

Punch a line of tape in alphanumeric mode. The
punch flag is immediately cleared and then set
when punching is complete.

PSB

700244

Punch a line of tape in binary mode. The punch
flag is immediately cleared and then set when
punching is complete.

NOTE:

Operation
Executed

The following microcoded instruction causes the punching of just a feed hole.

700214

Card Reader and Control Type CR02B
Overall Description - The CR02B Card Reader
reads 80 column 12-row punched cards at rates
up to 200 cards per minute. A select instruction starts a card moving past the read station.
Information is transferred into a 12-bit register,
one column at a time, and a column flag is
set. Upon sensing the column flag, the computer reads the data register into the AC, under
program control. Once a card is selected, all
80 columns must be read. The card may be
selected in either of two modes. In the binary
mode, information is transferred into the data
register directly as 12 rows of information. In
the alphanumeric mode, the 12 rows of information are encoded into Hollerith card code and
transferred into the data register as a 6-bit code.
Table 4-7 lists the lOT instructions for the
CR02B card reader and control.
Operation - The read sequence is started by the
issuance of a select command. Once the command to select a card is given, the card reader
reads all columns in sequence. To read a column, the program must respond to a column
ready flag and read the data buffer with a read
buffer command. The read buffer command must
be given within 2.0 msec after the column flag
is set or the data will be incorrect. The read
buffer command clears the column flag.

Once a card is selected, a new select instruction
can be used to change the mode from alpha to

Clear AC and punch a feed hole.

binary or vice versa. If the change is from binary
to alphanumeric or if a select alphanumeric command is given when the card is already selected
in alphanumeric, the column data is re-read into the data buffer. This re-read must occur
within 20 microseconds of the column flag to
guarantee accuracy.

There are four flags associated with the CR02B
card reader. These flags are the column flag,
card done flag, end-of-file flag, and the not
ready flag. The card done and column flags are
connected to the program interrupt and may be
individually tested by skip instructions. The
column flag indicates column data is in the data
register ready to read. The column flag is set by
data available and is cleared by the read column
register command. The card done flag is set when
a card is completely read, and is cleared by either
of the select commands. The end-of-file (EOF)
level is set by the EOF button on the reader or
the hopper empty condition and is cleared by the
hopper full condition or the EOF button. The
EOF button is an on-off, push-push button. The
EOF level may be skip tested. It is used to indicate to the program that the last card of the
current deck in the reader has been read. The
not ready level indicates that the card reader is
in the not ready condition. This may be caused
by a read check, feed check, or by the start
button not having been depressed. The not ready
condition may be tested with a skip instruction.

4-7

TABLE 4-7 CARD READER CR02B lOT INSTRUCTIONS
Mnemonic
Symbol

Octal
Code

Operation
Executed

CRSF

706701

Skip if column flag is set

CRSD

706721

Skip if card done flag is set

DRSD

706741

Skip if reader is ready

CREF

706761

Skip if EOF flag is set

706702

Inclusive OR buffer to the AC and clear
column flag

CRRB

706712

Clear the AC, inclusive OR buffer into the
AC, clear column flag

CRSA

706704

Select alphanumeric mode. A card is selected
and the alphanumeric mode is set. If a card
is already selected when this command is given,
a data reread will occur.

CRCD

706724

Clear card done flag

CRSB

706744

Select binary mode. A card is selected and the
binary mode is set.

DA TA FORMA TS - The binary and ALPHA for-

Operator Control and Status - Console lighlts, buttons, and switches associated with the CR02B
Card Reader are described in table 4-8.

data formats are as follows:

(The Hollerith character code is given
in the Appendix, page A2-6.)

DATA FORMATS
Unchanged
...
AC BIT

0 1 2 3 4 5

BINARY
6

7 8 9 10

12 11 0

CARD ROW

12 13

14- 15

16 17

ALPHA
AC BIT

0 1 2 3 4 5

USAGE

Unchanged

7 8 9

10 11

Unchanged

Automatic Line Printer Type 647
The Type 647 Automatic Line Printer prints text
in lines of up to 120 characters at a maximum
rate of 300 lines per minute for the 6470 or
600 lines per minute for the 647E. Printing

4-8

12 13

14 15

16 17

Character Code

is perfonned by solenoid-actuated hammers.
The typeface is engraved on the surface of the
continuously rotating drum. A 64-character set
is provided. Models are available with up to 160
columns and a printing rate of 1000 lines per
minute.

TABLE 4-8

CARD READER CR02B, CONSOLE LIGHTS, BUTTONS, AND SWITCHES

Light

Color

Meaning

NOT READY

white

On whenever the reader is unavailable to the computer.
Turned on by STOP button, empty hopper, full stacker,
malfunction (read check, feed check, or validity check
when the VALIDITY ON switch is activated), or a
power-on sequence. Turned off by pressing the START
button.

READ CHECK

red

Turned on by the failure in the read circuitry. Turned
off by pressing the RESET button.

FEED CHECK

red

Turned on when a card fails to reach the read station
Turned off by pressing RESET.
Reader motors stop when this light comes on.

in the prescribed time.

VALIDITY CHECK

red

Button or Switch

Turned on when VALIDITY ON switch is activated and
an invalid punch combination is read in the alphanumeric
mode. Turned off by pressing RESET.

Meaning

POWER ON

Turns power on to reader and control logic. Button lights
green when power is on. NOT READY light also comes
on.

POWER OFF

Turns power off to reader.

START

Turns off NOT READY light and places reader in the
ready condition if the check lights are off.

STOP

Turns on the NOT READY light and places the reader
in the not ready condition. If the reader is in operation
when this button is pressed, the reader stops when the
current card runs out to the stacker.

RESET

Turns off the three red check lights (READ CHECK,
FEED CHECK, and VALIDITY CHECK). Does not place
the reader in the ready condition; does not turn off the
NOT READY light.

END OF FILE

Signals an end-of-file condition to the computer when
this button is pressed and the hopper is empty. Has no
effect if the hopper is not empty. The button lights
white when an end-of-file condition is present. The light
is extinguished when cards are placed in the hopper.

VALIDITY ON

When this switch is on, validity check errors stop the
reader (see VALIDITY CHECK light above). When off,
validity check errors do not stop the reader. Alternately
pressing the button turns the switch on and off. When on,
the button lights yellow.

Information is transferred from computer to
printer through a printer interface, which contains a core buffer in which a line to be
printed is assembled character by character.
Each character is represented by a 6-bit binary
code. When a print cycle is initiated, the core

buffer is scanned each time a row on the drum
comes up to the print station. As the characters
are printed, the corresponding core buffer positions are cleared so that at the completion of
the print cycle the buffer is clear and ready for
the next line.
4-9

A print cycle is initiated by a command fr01TI
the progranl. Depending on the distribution and
number of different characters in the line to be
printed, a print cycle may take from about 48
to 180 milliseconds, not including vertical spacing of the paper.
Vertical movement of the paper is under control
of a punched fonnat tape. Eight program-selectable channels determine the amount of vertical
spacing by sensing the punches in the tape.
Spacing may be performed at the completion of
a print cycle. The paper and tape then move until a hole in the tape is sensed. The table below
shows the increments punched on the standard
format tape. The user may also create his own
formats for which a special punch is available.
AC Bits
15 - 17

Tape
Channel

Spacing
Increment

Every 2nd line

Every 3rd line

Every line

Every 6th line

Every 11 th line
(1/6th page)

Every 22nd Hne
(I/3rd page)

Every 33rd line
(1/2 page)

Top of next form

Note that spacing is referenced from the top of
the form. A space of one line requires 9 milliseconds. Longer skips vary in time, the first
taking 9 milliseconds and then 2 to 3 milliseconds for every line thereafter. The spacing increments assume a page format of 66 lines.
Operating Controls and Indicators - With the
exception of the main power switch and certain
test pushbuttons, all of the operating controls
are located on two panels. The main panel is
at the left on the front of the printer; the
auxiliary panel is at the rear on the same side
of the machine. The function of line printer
controls and indicators is specified in table 4-9.

In addition to the above paper low alert, no
paper, and yoke open alarms, an alarm can be
generated by a failure in any part of the printer;
such a failure automatically takes the printer offline.
Programming - A line to be printed is assembled
in the printer buffer character by character from

4-10

left to right. When the line is complete, a program command initiates the print cycle. 'Vhen
the cycle is finished, the paper mayor may not
be spaced vertically. Suppressing vertical lnove··
ment makes underscoring and overbarring possible. When spacing is performed, the printer
buffer becomes available approximately 4 milliseconds before the paper comes to a stop. The
program may begin assembling the next line
during this time.
Three loading instructions (table 4-10) allow the
program to transfer one, two, or three characters at a time from the AC to the printer buffer.
If more than one character is transferred, the
characters in the most significant bits of the
AC are transferred before characters in less
significan t bits.
The buffer loading instructions perform the inclusive OR transfer of the contents of the AC
and the current positions of the printer buffer.
Thus, the buffer must be clear before a new
line is loaded. Clearing is done automatically
during the print cycle; an instruction is provided
for initializing the interface and clearing the buffer before starting to print.
The capacity of the printer buffer is 120 characters. The program must keep track of the
number of characters transferred; if more than
120 are sent, the done flag is not set.
Two flags are associated with the Type 647:
done and error. The done flag is set at completion of an lOT-initiated function. The error
flag is set when an alarm signal occurs and can
be reset only when the alarm condition is removed. The done flag is connected to the program interrupt control. Both the done flag and
the error flag may be sensed by skip instructions.
The logical sequence for use of the line printer
is as follows:
1.

Check the error flag (LSEF).

Clear the printing buffer (LPCB)*.

Load the printing buffer (and the spacing
buffer, if required) * .

Print the contents of the printing buffe:r
(since the printing buffer is automatically
cleared *, step 2 may be omitted from
the sequence after an initial print cycle
has been executed).

* The program must wait for the done flag setting before issuing a new command to the line
printer.

TABLE 4-9

LINE PRINTER CONTROLS AND INDICATORS.

Control or Indicator

Function

TRACTOR INDEX

Used for aligning the forms with the format tape when new paper
is loaded. This pushbutton works only when the printer is off-line.

PAPER LOW ALERT

This red indicator lights when the end of the paper is about to pass
through the drag devices below the printer yoke. An alarm signal
is sent to the computer at the same time.

NO PAPER

When the end of the paper has passed out of the forms tractors,
this indicator lights red, and an alarm signal is sent to the computer.

YOKE OPEN

When the printer yoke is open, this red indicator lights. An interlock prevents all but the TOP OF FORM and TRACTOR INDEX
controls from operating.

ALARM STATUS

Whenever an alarm signal is generated, this red indicator lights.

ON,OFF

'These pushbuttons control application of primary power to the
functioning parts of the printer. The main power switch must be
turned on for these switches to function. The rest of the controls
operate only after ON has been pressed.

START

Places the printer on-line; it is then ready to receive information
and print it.

STOP

Takes the printer off-line as soon as the buffer is clear. If there
is information in the buffer, the printer remains on-line until after
the next clear buffer instruction or the completion of the next
print cycle. When the printer goes off-line, an alarm signal is
sent to the computer.

TEST PRINT

'This pushbutton is used for maintenance at the printer and is not
used in normal operation.

TOP OF FORM

Moves the paper to the top of the next page. This pushbutton
works only when the printer is off-line.

Incremental Plotter and Control Type 350
A California Computer Products Incremental
Recorder can be operated with a Digital Equipment Type 350 Incremental Plotter Control.
Characteristics of the available models are provided in table 4-11.
The principles of operation are the same for each
of the models. Bidirectional rotary step motors
are employed for both the X and Y axes. Recording is produced by movement of a pen relative to the surface of the graph paper, with
each instruction causing an incremental step.
X-axis deflection is produced by motion of the
drum; Y-axis deflection, by motion of the pen
carriage. Instructions are used to raise and lower
the pen from the surface of the paper. Each incremental step can be in anyone of eight directions through appropriate combinations of the

X and Y axis instructions. All recording (discrete points, continuous curves, or symbols) is
accomplished by the incremental stepping action.
of the paper drum and pen carriage. Front
panel controls permit single-step or continuousstep manual operation of the drum and carriage,
and manual control of the pen solenoid. The
recorder and control are connected to the program interrupt and I/O skip facilities. The
instructions for this equipment are listed in
table 4-12.
Program sequence must assume that the pen location is known at the start of a routine since
there is no means of specifying an absolute pen
location in an incremental plotter. Pen location
can be preset by the manual controls on the
recorder. During a subroutine, the computer can
track the location of the pen on the paper by
4-11

TABLE 4-10

LINE PRINTER TYPE 647E

Operation
Executed

Mnemonic
Symbol

Octal
Code

LSDF

706501

Skip if the DONE flag is set.

LPCB

706502

Clear the DONE flag, clear control print buffer, enable
DONE interrupt, initiate a clear sequence in the hue
printer. Set the DONE flag when the clear sequence is
finished.

*LPDI

706504
706522
706542
706562

Disable DONE flag interrupt.
Clear DONE flag.
Clear DONE flag.
Clear DONE flag.

LPL2

706526

Load printing buffer with two characters; clear DONE
flag; the contents of AC 6-11 and AC 12-17 aTe transferred to the printing buffer as 6-bit bytes in that
order. The DONE flag will be set when the load
sequence is finished.

LPPS

706646

Print and Space. This instruction accomplishes the
combined actions of LPPB and LPLS instructions. The
DONE flag is cleared; the contents of AC 15-17 are
transferred to the spacing buffer; the contents of th~~
printing buffer are printed; the paper is spaced vertically; the printing and spacing buffers are cleared;
the DONE flag is set upon completion.

*LPEI

706664

The DONE flag interrupt is enabled.

LPLD

706546

Load the printing buffer with three characters. The
DONE flag is cleared; the contents of AC 0-5, 6-11,
and 12-17 are transferred as 6-bit bytes into the printing buffer in that order. The DONE flag is set at the
-completion of the load sequence.

LPLI

706566

Load the printing buffer with one character; dear
DONE flag; the contents of AC 12-17 are transferred
as a 6-bit byte into the printing buffer in that order.
The DONE flag is set at the completion of the load
sequence.

LPEF
LPCF

706601
706602
706622
706642
706662

Skip if the ERROR flag is set.
Clear DONE flag.
Clear DONE flag.
Clear DONE flag.
Clear DONE flag.

* Refer to footnote at the end of this table

4-12

TABLE 4-10

LINE PRINTER TYPE 647E (continued)

Mnemonic
Symbol

Octal
Code

Operation
Executed

LPPB

706606

Select printer and initiate printing. The DONE flag
is cleared; the contents of the printing buffer are
printed; the printing buffer is cleared; the DONE
flag is· set when the printing sequence is completed.

LPLS

706626

Load spacing buffer and space; the DONE flag is
cleared; the contents of AC 15-17 are transferred
into the spacing buffer; the paper is spaced vertically
according to the format selected; the spacing buffer
is cleared; the DONE flag is set.

* These instructions have been added to the Line Printer command set to allow enabling and disabling of the interrupt.
Since power clear returns the system to the interrupt enabled condition, programs generated for the Type 647B Line
Printer (PDP-7), which does not have these instructions, will run correctly.

TABLE 4-11

CCP
Model
563
565

TABLE 4-12

DIGITAL INCREMENTAL RECORDER CHARACTERISTICS
Step
Size
(inches)
0.01 or
0.005
0.01 or
0.005

Speed
(steps/minute)

Paper
Width
(inches)
31

12,000 or
18,000
18,000

INCREMENTAL PLOTTER AND CONTROL INSTRUCTIONS

Mnemonic
Symbol

Octal
Code

PLSF
PLCF
PLPU
PLPR
PLDU
PLDD
PLPL
PLUD
PLPD

702401
702402
702404
702421
702422
702424
702441
702442
702444

Operation
Executed
Skip if plotter flag is a 1.
Clear plotter flag.
Plotter pen up. Raise pen off of paper.
Plotter pen right.
.
Plotter drum (paper) upward.
Plotter drum (paper) downward.
Plotter pen left.
Plotter drum (paper) upward. (same as 702422)
Plotter pen down. Lower pen on to paper.

4-13

counting the instructions that increment the
positions of the pen and the drum.
Oscilloscope Display Type 34H
Type 34H is a two-axis digital-to-analog converter
and an intensifying circuit, which provides the
deflection and intensify signals needed to plot
data on an oscilloscope. Coordinate data is loaded
into an X buffer (XB) or a Y buffer (YB) from
bits 8 through 17 of the accumulator. The binary
data in these buffers is converted to a -10 to 0
volt analog deflection signal. The 30-volt, lOmicrosecond intensify signal is connected to the
grid of the oscilloscope CRT. Points can be
plotted at approximately a 30-kilocycle rate.
The lOT instructions for this display are identical to those for the Precision CRT Display Type
30D, described under the following heading, with
the exception of the DLB command. The 34H
has a 2-bit brightness register (BR), the contents
of which specify the degree of brightness for
the point being displayed. The following indicates the intensity scale:

BR Contents

Intensity Level

no display
dimmest
average
brightest

The instruction 700704 loads the BR with the
contents of AC bits 16 and 17.

quires 50 microseconds to display a point. No
flag is associated with this operation. The lOT
instructions for the Type 30D display are liste:d
in table 4-13.

BR Contents

Intensity Level

brightest

2
1

average

6
5
4

dimmest

Photomultiplier Light Pen Type 370
The high-speed light pen is a photosensitive device which senses displayed points on the face
of the CRT. The Type 370 uses a fiber optic:
light pipe and photomultiplier system, which
gives the pen a response time approximat~~ly five
times faster than that of a photodiode. If the
pen is held in front of 'a point displayed on the
face of the CRT, it transmits a signal whilch sets
the display flag to 1. The Type 370 is equipped
with a mechanical shutter which prevents the
sensing of unwanted information while positioning the pen. Variable fields of view are obtained
by means of a series of interchangeable tips with
fixed apertures. The lOT instructions for the
light pen are listed with the display 'option in··
structions in table 4-13.

Precision CRT Display Type 30D
The Type 30D displays points on the face of a
cathode ray tube. Each point is located by its
X- and Y-coordinates in a square array whose
origin is in the lower left corner of the CRT
screen. The array contains 1024 points on a
side and lneasures 9-1 14 by 9-1 14 inches square.
The X- and V-coordinates each have a 10-bit buffer which is loaded from bits 8-17 of the AC.
In addition, there is a 3-bit brightness register (BR)
which is loaded from bits 15-17 of the AC. The
content of this buffer specifies the brightness
of the point being displayed as designated on the
following scale. The five brightest intensities are
easily visible in a normally lighted room; the
dimmest can be seen in a darkened room.

The X- and V-coordinate buffers (SB and YB) are
loaded separately. Each may be loaded without
intensifying the CRT. The usual procedure is to
load one buffer, then load the second buffer and
select in one instruction. The Type 30D re4-14

Analog-to-Digital Converter and Mu1tiplex{~r
Type AFOIB
The General Purpose Multiplexer AID Converter
Type AFO 1B is used with PDP-9 computer to
multiplex up to 64 analog signals and to convert
the signals to binary numbers. It replaces the
older Type 138E/139E system.

AID Converter - The AID converter is a general
purpose successive-approxinlation type with the
f0 Howing characteristics:
Accuracy:

See table 4-16 (includes
all linearity and tenlperature
errors).

Conversion
Time:
Aperture:

See table 4-16.
Same: as Converstion time
without AH02 sample and
hold option.

ture. All power is contained in the Type AFO 1
for the amplifier and/or sample and hold options.

Converter
None.
Recovery Time:
Analog Input:
V oitage Range
Loading:

o to -IOV standard (see
table for amplifier or
sample and hold options).

± 1 microamper and 125
picofarads for standard input.

The word-length switch selects the A/D Converter
Characteristics listed in table 4-14.
Provision is made for using the Type A400
Sample and Hold Amplifier (AH02 option) between the multiplexer output and A/D converter input to reduce the effective aperture to less
than 150 nanoseconds. The Type A400 may also
be used to scale the signal input to accept ± 1OV,
±5V, or 0 to lOY. The Type A200 amplifier
(AH03 option) may be substituted for the Type
A400 to accomplish the same signal scaling without reducing the effective aperture.
Both the AH02 and AH03 options may be used
to obtain high input impedance and small aperTABLE 4-13

Five convenience switches are mounted on the
control indicator panel: a power switch to control the AC power to the Type AFO 1 System, an
ADC pushbutton switch to initiate a conversion
manually; a CLR pushbutton switch to set the
multiplexer address to channel 0 manually; . an
index pushbutton to increment the multiplexer
address manually; and a rotary word-length
switch to select the word length, conversion
accuracy, and conversion time.
The control indicator panel also contains twelve
indicators to display the contents of the ADC
buffer, six indicators to display the current multiplexer address, and a power off-on indicator.

Multiplexer Switches - The multiplexer can include from 1 to 16 Type A 121 Switch Modules.
Each module contains four single-pole, high
speed, insulated gate FET switches with appropriate gating. The Type A 121 Switches are
arranged as a 64-channel group of series-switch

OSCILLOSCOPE AND PRECISION DISPLAY INSTRUCTIONS

Mnemonic
Symbol

Octal
Code

DXL

700506

Operation
Executed
Load the X-coordinate buffer from ACS-17.
ACS-17 =

XB.

DXS

700546

Load the X-coordinate buffer and display the point
specified by the XB and VB.

DYL

700606

Load the Y-coordinate buffer from ACS-17.
ACS-17 =

VB.

DYS

700646

Load the Y-coordinate buffer and display the point
specified by the XB and VB.

DXC

700502

Clear the X-coordinate buffer.

DYC

700602

Clear the Y-coordinate buffer.

DLB

700706

Load the brightness register from bits 15-17 of the
AC. Note: This instruction clears the display flag
associated with the light pen.

DSF

700501

Skip if display (light pen) flag is a 1.

DCF

700702

Clear display (light pen) flag.

4-15

single-pole switches with a separate continuous
ground wire for each signal input. The switched
signal input wire and the continuous ground for
each channel are run as twisted pairs to the input connectors mounted on the rear panel. The
continuous grounds for all channels are tenninated at the high quality ground of the AFO 1B
System.

sions on a currently selected channel. Conversion
times listed in the word-length table are increased
by 2 microseconds when multiplexer channels are
switched to allow for settling times of the analog
signal at the multiplexer output. (This time is
increased by 5 microseconds when AH03 is used.)
Each successive conversion on a selected channel
requires only the time shown in table 4-14.
Digital-to-Analog Converter Type AAO 1A

Specifications (Measured at input connector)

± 10 V

Input signal (max)
Inpu t current
"On" offset voltage
"On" resistance (max)
Turn-on delay
"Off" leakage (max)
Turn-off delay
Settling time to l-LSB
(source Z ~ 1 ohm)

1.0 111 a

450 ohms
150 nsec
10 na
250 nsec
'$2 microseconds

Operation - The Type AFO 1B System may be
operated in either the random or sequential address rnodes. In the random address mode, the
control routes the analog signal from any selected channel to the A/D converter input. In the
sequential address mode, the multiplexer control
advances its channel address by one each time
an index command is received. After indexing
through the maximum number of channels is
implemented, the address is returned to O.
The ,multiplexer switch settling time is preset
within the control to initiate the conversion process autonlatically after a channel has been selected in either the random or sequential address
mode. Two separate A/D Convert I/O Transfer
Commands may also initiate one or more conver-

This general purpose digital-to-analog converter
converts 12-bit binary computer output numbers
to analog voltages. The basic option consists of
three channels, each containing a 12-bit digital
buffer register and a digital-to-analog converter.
Digital input to all three buffer registers is provided in common by one 12-bit input channel
which interfaces to the PDP-9/L I/O bus. Appropriate precision voltage reference supplies are provided for the converters.
One lOT instruction simultaneously selects a
channel and transfers a binary number into the
selected buffer register. Each converter operates
continuously on the contents of its associated
buffer register to produce an analog output voltage. The analog output voltage of a standard
converter· is from ground to -9.9976 volts (other
voltage ranges are available).
All inputs to the converter are assumed to be
12 bits in length with negative numbers :repre··
sented in 2s complement notation. An input
of 40'00 8 yields an analog output of ground
potential; an input of 0000.a yields an output
of -5 volts; and an input of 17778 yields an
output of -10 volts minus the analog value of
the least significant bit of the input. Output
accuracy is ± 0.0125% of full scale; resolution

TABLE 4-14 A/D CONVERTER CHARACTERISTICS

,--------------------------------.------------------------------,----------------.-Word Length
(No. of bits)

Max Switching
Point Error*

Conversion Time
(microseconds )I

(±)

6
7
8
9
10
11
12

* ± L/2 LSB for quantizing error
4-16

1.6%
0.8%
0.4%
0.2%
0.1%
0.05%
0.025%

9.0
10.4
12.0
13.5
18.0
25.0
35.0

is 0.025% of full scale value. Response time,
measured directly at the converter output, is
3 microseconds for a fun-scale step change to 1
least significant bit accuracy. Maximum buffer
register loading rate is 2 MHz.

The variety of possible configurations makes it
necessary that the user, or interface designer,
define the appropriate instructions and append
them to the symbol table of the Symbolic
Assembler of the BASIC Software system.
Multi-station Teletype Control Type LT09A

Type AAO 1A Converters can be specified in a
variety of basic configuration: with from one
to three channels, with or without output operational amplifiers, and with internally or externally supplied reference voltages. Converters can
be also supplied with two buffer registers per
each channel. This provision permits program
control to load the outer buffer register of each
channel with an appropriate binary number and
then effect a simultaneous transfer of these contents into the inner buffer registers for simultaneous conversion to a summed analog voltage.
A typical instruction for the AA01A is:

Addition of the LT09A option to the PDP-9/L
expands the machine's Teletype facility to
accommodate several Teletype units (KSRs and
ASRs may be used interchangeably). Operation
of the LT09A facility is in full-duplex mode.
Each Teletype line added contains logical elements which are functionally identical to those
of the control for the standard unit. Instructions
and programming considerations are, therefore,
similar to those of the standard unit. The
following device selection codes have been assigned for four lines of LT09A equipment.

Line

Teleprinter

Keyboard

40
42
44
46

41
43
45

Mnemonic:

DAL1

1
2

Octal Code:

705501

3
4

Function:

Load digital-to-analog converter 1.
The contents of the AC are entered in the digital buffer register
of channell.

TABLE 4-15

Instruction mnemonics for the Teletype units
lnust be defined by the user and appended to
the PDP-9/L BASIC Symbolic Assembler. Typi-

AFOIB A/D CONVERTER AND MULTIPLEXER lOT INSTRUCTIONS
Operation
Executed

Mnemonic
Symbol

Octal
Code

ADSF

701301

Skip if converter flag is set. This flag is connected to the program interrupt.

ADSC

701304

Select and convert. The converter flag is
cleared and a conversion of an incoming voltage
is initiated. When the conversion is complete,
the converter flag is set.

ADRB

701312

Read converter buffer. Places the content of the
buffer in the AC, left adjusted. The remaining
AC bits are cleared. The converter flag is cleared.

ADSM

701103

Select MX channel. The content of AC12-17 are
placed in the MAR.

ADIM

701201

Increment channel address. The content of the
MAR is incremented by 1. Channel 0 follows
channel 77 8 .

ADRM

701212

Read MAR into AC12-17.

4-17

cally, the mnemonics are derived by suffixing
'LT' and the line number to the mnemonics for
the standard unit. For example, the instruction
KSF (skip on keyboard flag) could be represented by KSFLT2 for an instruction to "skip on
keyboard flag of line 2".
Relay Buffer Type DR09A
The Type DR09A is a computer output device
that allows data in the computer to control external electrical equipment through relays. The
relay buffer consists of an IS-bit flip-flop register, and IS-bit relay register, filters to reduce
noise due to contact bounce, and a patchboard.
Under program control the flip-flop register can
be set to correspond to the content of the accumulator and can be cleared. The commands
for the relay buffer are listed in table 4-16 .
Interprocessor Buffers DB99A and DB98A
Overall Description - The DB99A and DB98A
are bidirectional interprocessor data buffers
which operate through the data channel facilities
,or with programmed data transfers. The DB99A
will buffer two PDP-9/Ls together, and the
DB9SA will buffer one PDP-9/L and one PDP-So
Data may be transferred through the accumulator or data channel, .or both simultaneously in
full duplex operation. Accumulator word transfer rates as high as 100 kc and data channel
rates as high as 110 kc may be achieved.
General Performance - There are two basic paths
of data flow in the DB99, and DB9S. One path
is from accumulator to accumulator using programlned data transfers and the other path is
memory to memory utilizing the data channel
facilities of both machines. A single register at
each interface is used for both types of data
transfer and the inputs to these registers are
multiplexed.

Programmed Transfers - Programmed transfers
of data occur between the accumulators of
TABLE 4-16

the computers involved. This mode of data
transfer is used primarily for transmission of
control parameters while the data channel system is simultaneously handling a full duplex
(bidirectional) data transfer; however, the
programmed data transfer system can also 1be
used as the primary data transmission method.
The supervisory overhead of operating this system will be significantly higher, however, and
the transfer rates will be slightly lower.
Data Channel Transfers - Data channel transfers can occur between computers in s.imultaneous full duplex fashion. The standard channel facilities are utilized (three cycle Data
Break on the PDP-S; DCH on the PDP-9/L).
The access of data to be transmitted and the
storage of data received is supervised by the
hardware. Each interface has two data channels, one for data transmission and one for
data reception. Each data channel is assigned
two memory locations to contain the word
count and address registers for the channel.
The transmit channel is assigned locations 22
and 23 and the receive channel is assigned locations 24 and 25. (Refer to table 4-17 for lOT
instructions. )
Bit Correspondence - The bit correspondence
for data words in the DB9SA is given below:

Command Status Register Configuration
PDP-8
Bit

PDP-9
Bit

11
10
9

17
16
15

Meaning

Transmit flag.
Receive flag.
Transmit word count
overflow flag.

RELAY BUFFER COMMANDS
Operation
Executed

Mnemonic
Symbol

Octal
Code

ORC

702101

Clear output relay buffer flip-flop register.

ORS

702104

Set output relay buffer flip-flop register to correspond with the contents of the accumulator.

,--------------------------.---------------------------------------4-1S

TABLE 4-17 INTERPROCESSOR BUFFERS DB99A AND DB98A lOT INSTRUCTIONS

Mnemonic
Symbol

Octal
Code

Operation
Executed

PDP-9/L lOT Instructions for DB99A

702201

Skip if no interrupting flag of this device is set.

702202

Inclusive OR command status register into the AC.

PBRS

702212

Read command status register into the AC.

PBXS

702204

Exclusive OR the contents of the AC into the command status register.

PBNB

702221

Skip if data register not busy.

702222

Clear data register if data register not busy.

702224

OR the AC to data register if data register not busy
and set the transmit flag and not busy level and
clear the receive flag.

702241

Skip if transmit flag is set.

702242

Inclusive OR data register into the AC, set receive flag
and clear transmit flag if the transmit flag is set.

702252

Read data register into the AC, set receive flag and
clear transmit flag if the transmit flag is set.

PBNF

PBTF

PBRD

Useful PDP-9/L Microinstructions
PBTL

702227

Skip and load data register from the AC, and set
transmit flag, and receive flag, if all data register
not busy.

PBRL

702253

Skip if transmit flag is set and read data register
into the AC and set receive flag and clear transmit flag, all if transmit flag is set.

PBLD

702226

Clear and load data register from the AC if the not
busy level is set.

PDP-8 lOT Instructions for DB98A
PBNF

6601

Skip if no interrupting flag of this device is set.

PBRS

6602

OR command status register into the AC.

PBXS

*6604

Exclusive OR the contents of the AC (into the command status register).

PBNB

6611

Skip if data register not busy.

*See footnote at end of Table.

4-19

TABLE 4-17 INTERPROCESSOR BUFFERS DB99A AND DB98A lOT INSTRUCTIONS (Con't)
Mnemonic
Symbol

Operation
Executed

Octal
Code

PDP·-8 lOT Instructions for DB98A (Con't)
PBTF

6612

Skip if transmit flag is set.

PBLD

6615

Load data register from the AC set transmit flag,
and clear receive flag. All if data register not busy.

PBRD

6616

Skip if transmit flag is set, read data register into
the AC set receive flag and clear transmit flag.

*If the AC=O when this command is given the not busy flag will be set to the not busy condition, the
CS register will be unchanged.

PDY-8

PDP-9

Bit

Meaning

Not in
PDP-8
CS register

Not in the
PDP-9/L CS
register

Receive word count
overflow flag.
Enable not busy flag
interrupt
Enable transmit and receive flag interrupts.
Enable data channel
overflow interrupts.
Enable receive data
channel.
Select transmit data
channel.
Not busy flag. This flag
may be manipulated by
the XO R to CS instruction, but it may not be
read into the accumulator. Power clear returns
this flag to the one (not
busy) state.
Address extension bit 3.

4-20

Not in the
PDP-9/L CS
register
Not in the
PDP-9/L CS
register

In the PDP-8 an XOR to CS instruction with lthe
AC set to 0 will cause the not busy flag to be:
set to the not busy state. The CS register will
remain unchanged. Power clear also sets the not
busy state.
PDP-9/L to PDP-7 Interprocessor Buffer Type
DB97A
Controls and buffers the flow of information between one PDP-9/L and one PDP-7, using the
program controlled transfer facility of each processor.
Data Communications System Type DP09A
(DPOIB)
General - The Bit synchronous Data Communi-·
cations System Type DP09A provides interface
facilities between a PDP-9/L and a bit serial communications device such as a Type 20 I or 301
Data Set (Bell System). Characters are transferred between the PDP-9/L accumulator and the
DP09 A under program control. The DP09 A
serializes the characters for transmission, and
assembles the serial stream into characters for reception. Operation is full duplex. Both the receive and transmit sections are double-buffered to
permit one full character transmission time for
loading or reading the DP09A.

Address extension bit 2.

Address extension bit 1.

A character may be 6, 7, 8, or 9-bits long. Character length is determined by a series of jumpers
on a 50-pin cannon connector; an appropriate
connector for each character length is provided.

Idle/Active - The DP09A is in the idle state un-

til made active either by the PDP-9/L transmitting a sync character to the DP09A or the
DP09A receiving a sync character from the Data
Set.

flags can cause a program interrupt or API
break (if present) to location 62 at priority level
two.
TRANSMIT FLAG

The sync characters are:
Character
Length (N)
6
7
8
9

Sync Character

Tested by an STF instruction,
skip if flag not set.

010 110

Cleared by a CTF instruction

o 010 110
10 010 110
X10 010 110

RECEIVE FLAG

(X not used in sync character
determination)

While transmitting, idle mode is disabled
and no character has been transferred to
the DP09A from the computer within Nt
microseconds of the transmit flag being
set. (N is the number of bits/character,
t is the time to transmit a bit on the
line. Ntis therefore the time to transmit
a full character on the communications
line.)

Cleared by an RRB instruction
RECEIVE END FLAG

Set when no bit is received
from the sending device within l.5t (t is the normal interbit spacing, the reciprocal of
the baud rate).

RING FLAG

Set when a remote communications device calls up the
DP09 A and is ready to transmit. Only causes an interrupt
if Ring Enable is set (see instruction list).

While receiving, the clear receive active
(CRA) command is issued, or if no character is received from the communication
line for 1.5 bit times.

Idle mode is a feature of the DP09A which permits retaining the communications system in an
active (and synchronous)- state when no new characters are available. When idle mode is enabled,
the last character continues to be transmitted
until such time that a new character is ready.
The transmit flag continues to be raised at the
end of each character transmission.
Idle mode is enabled by the SIM instruction and
disabled by the CIM instruction.
Flags - The DP09A communicates with the computer through a series of flags. Anyone of the

Set when the DP09 A is ready
to transfer a character to the
computer.
Tested by an SRF instruction,
skip if flag not set.

The DP09A will return to the inactive (idle)
state if 1.

Set when the DP09 A is ready
to receive a character from the
computer for transmission.

Tested by an SRI instruction,
skip if flag not set.
Cleared by an CRF instruction
DATA SET READY
FLAG
(This flag can not
cause an interrupt)

Set when the local Data Set
is ready for operation.
Tested by an SSR instruction,
skip if flag is set.
Cleared only when the Data
Set becomes unavailable.

lOT Commands - Following are the lOT commands for the Bit Synchronous Data Communications System. Types DPOlB and DP09A are listed in table 4-18. (If bit 14 of any of these commands is aI, the AC will be cleared at event
time 1 of the lOT.)

4-21

TABLE 4-18

Mnemonic
Symbol
STF

BIT SYNCHRONOUS DATA COMMUNICATIONS SYSTEM TYPES
DPOIB AND DP09A lOT COMMANDS
Octal
DPOIB DP09A
704501

702521

Command
Skip on Transmit Flag
TIlls command causes the program flow to skip the
next instruction if the transmit flag is NOT set.

TAC

704201

702501

Transmit a Character
This command transfers the contents of the accumulator (6, 7, 8, or 9-bits right justified) into the
transmit character buffer. If the transmit logic is
not active, the character will only be transmitted
if it is a sync character.

CTF

704202

702502

Clear Transmit Flag
TIlls command clears the transmit flag. It also
causes the program flow to skip the next instruction
if the transmit interface is active. Thus, the microprogrammed instruction TAC CTF (704203) loads
the next character, clears the transmit flag, and tests
the DP09A to be sure that transmit is still active.

CIM

704204

702504

Clear Idle Mode
TIlls command disables the idle mode.

SIM

704504

702524

Set Idle Mode
This command enables the idle mode.

SRF

704501

702621

Skip on Receive Flag
This command causes the program flow to skip the
next instruction if the Receive Flag is NOT set.

RRB

704502

702522

Read Receive Buffer
This command causes the contents of the receive
buffer (6, 7, 8, or 9-bits right end justified) to be
read into the accumulator. It also clears the
Receive flag.

SEF

704601

702541

Skip on Receive End Flag
TIlls command causes the program flow to skip the
next instruction if the "Receive End Flag" is NOT
set.

CEF

704602

702542

Clear End Flag
TIlls command clears the Receive End Flag.

4-22

TABLE 4-18 BIT SYNCHRONOUS DATA COMMUNICATIONS SYSTEM TYPES
DPOIB AND DP09A lOT COMMANDS (Con't)
Mnemonic
Symbol

SRE

Octal
DPOIB DPO'9A
704604

702544

Command
Set Ring Enable
This command causes the Ring Enable gate to be
turned on. When the Ring Enable gate is turned
on, the Ring flag can cause a program interrupt.

CRE

705004

702604

Clear Ring Enable
This command causes the Ring Enable gate to be
turned off.

SRI

704701

702561

Skip on Ring Indicator
This command causes the program flow to skip the
next instruction if the Ring flag is NOT set.

CRF

704702

702562

Clear Ring Flag
This command clears the Ring flag.

STR

704704

702564

Set Terminal Ready
This command causes the Terminal Ready gate to be
turned on. This gate indicates to the communication
media that the equipment is ready to receive data
from the serial line.

CTR

705002

702602

Clear Terminal Ready
This command turns the Terminal Ready gate off.

SSR

705001

702601

Skip on Data Set Ready
This command causes the program flow to skip the
next instruction if the communication facility is in
a ready condition.

CRA

705402

702622

Clear Receive Active
This command takes the interface (637) out of the
receive active state. No further characters will be
received until a sync character is detected.

4-23/4-24(blank)

CHAPTER 5
AUXILIARY STORAGE SYSTEMS
GENERAL
The PDP-9/L presently includes in its line of
standard peripherals the following auxiliary storage systems: DECtape systems, industry standard magnetic tape systems, and a high-speed disk.
DECTAPE SYSTEM
The DECtape system, a standard option for the
PDP-9/L, serves as a magnetic tape data storage
facility. The system, consisting of TU55 DECtape transports and TC02 DEC tape controls,
stores information at fixed positions on magnetic tape as in magnetic disk or drum storage
devices, rather than at unknown or variable
positions as is the case in conventional magnetic tape systems. This feature allows replacement of blocks of data on tape in an ordered
fashion without disturbing other previously
recorded information. In particular, during the
writing of information on tape, the system reads
format (mark) and timing information from the
tape and uses this information to determine the
exact position at which to record the information
to be written. Similarly, in reading, the same
mark and timing information is used to locate
data to be played back from the tape.
This system has a number of features to improve its reliability and make it exceptionally
useful for program updating and program editing applications. These features are: phase
or polarity sensed recording on redundant
tracks, bidirectional reading and writing, and a
simple mechanical mechanism utilizing aerodynamically lubricated tape guiding (the tape floats
on air and does not touch any metal surfaces).

DECtape Format
DECtape utilizes a 10-track read/write head.
Tracks are arranged in five nonadjacent redundant
channels: a timing channel, a mark channel, and
three information channels (figure 5-1). Redundant recording of each character bit on nonadjacent tracks materially reduces bit drop out
and minimizes the effect of skew. Series connection of corresponding track heads within a
channel and the use of Manchester phase record-

ing techniques, rather than amplitude sensing
techniques, virtually eliminate dropouts.
The timing and mark channels control the timing of operations within the control unit and
establish the format of data contained on the
information channels. The timing and mark
channels are recorded prior to all normal data
reading and writing on the information channels.
The timing of operations performed by the tape
drive and some control functions are determined
by the information on the timing channel. Therefore, wide variations in the speed of tape motion
do not affect system performance. Information
read from the mark channel is used during reading and writing data, to indicate the beginning
and end of data blocks and to determine the
functions performed by the system in each control mode.
During normal data reading, the control assembles
18-bit computer length words from six successive
lines read from the information channels of the
tape. During normal data writing, the control
disassembles I8-bit words and distributes the
bits so they are recorded on six successive lines
on the information channels. A mark channel
error check circuit assures that one of the permissible marks is read in every six lines on the
tape.

A tape contains a series of data blocks that can
be of any length which is an even number of
I8-bit words. Block length is determined by
information on the mark channel. Usually a
uniform block length (256 10 for the PDP-9/L) is
established over the entire length of a reel of
tape by a program which writes mark and timing
information at specific locations. The ability to
write variable-length blocks is useful for certain
data formats. For example, small blocks containing index or tag information can be alternated
with large blocks of data. The maximum number
of blocks addressable is 4096.
Between the blocks of data are areas called interblock zones, consisting of control words. These
words are used for cueing the TC02 control, and
for block by block parity checking.

5-1

DO DO 0 [] 0 0 DO 0 0 DO DO 0 00 00 O/"A-

TIMING TRACK I

MARK TRACK 1
INFORMATION TRACK 1

(

INFORMATION TRACI( 2

INFORMATION TRACK IA
(Some 01 IT 1)

INFORMATION TRACK 2A

INFORMATION TRACK :3

o o

I·

o o o

o o o
o

o
o

~=:===O==O==O==O==:=O===:=O==:==O==:======O===O====::::::::()1

YO"

(Some as IT 2)

REDUNDANT

~~~~~~:ACK 0: 0 0 0 0 0 0: 0 0 0 0 0 0: 0 0 0 0 0: 0 0 0~~ Tl"
0

;

Track Allocation Showing Redundantly Paired Tracks

TIMING TRACK
MARK TRACK
0
INFORMATION
TRACKS

121

1
1
21

DATA OR
4 CONTROL
WORD

141

15
16

REDUNDENT
TRACKS
NOT
SHOWN

Basic Six Line Tape Unit

-I
(}o/fLDCfLDcfE3BElEEEBBa:cfLDCI~\
Cj
.-.
j,.-

ONE COMPlE'rE REEL - 260 FT 4096 BLOCKS (MAX,)

...- - - - - - - - - ONE BLOCK 26 6 10 18 BIT WORD lOCATIONS

TIMING TRACK
MARK TRACK
DATA 1
DATA 2
OATA :3

ILl

I _

CONTROL
WORDS ~

I
256

)

~ i i

ILl

Z
0

ILl

Z
0

10 DATA WORDS

~
ILl

; ~ i i ~
ILl

Z
0

. . I..

Z
0

ILl

Z
0

C~~~~~l _ _

Control and Data Word Assignments

Figure 5- L DECtape Format (Sheet 1)
5-2

V
I

REDUNDANT
TRA(;KS
NO'T
SHO'WN

MOTION OF HEAD

MOTION OF TAPE

1
1

" " " "

10110t

tOI lOt 010101

200,0 INTERBLOCK
SYNC MARKS

~o,obo

° (

III

It 1000

T i

., .. " . . .
1 NEXT
1 BLOCK
1 MAR~

1
1

DATA

I"
2

ONE BLOCK

1:1,011

otono

tOOlO 01

0010

1:0°10

INTER
SYNC MARKS

INTERBI.OCK

ADDITIONAL

SYNC MARKS
DATA

MARKS

DECtape Mark Track Format
Figure 5-1.

DECtape Format (Sheet 2)

Block numbers normally occur on tape in sequence from 0 to N-I, where N is the number
of blocks. The total length of tape is equivalent
to 884,736 data lines per tape which can be
divided into any number of blocks up to 4096 by
prerecording of the mark track. However,
57610 blocks of 256 10 words are considered to
be standard format for a PDP-9/L DECtape.
DECtape Transport Type TU55
The TU 55 is a bidirectional magnetic-tape transport consisting of a read/write head for recording and playback of information on five channels
of the tape. Connections from the read/write
head are made directly to the TC02 control
which contains the read and write amplifiers.

electromagnetic brake mounted on each motor
shaft. When a stop command is given, the
trailing motor brake latches to stop tape motion.
Enough torque is then applied to the leading
motor to take up slack in the tape.
Tape movement can be controlled by commands
originating in the computer and applied to the
TU55 through the TC02 DECtape Control, or
can be controlled by commands genera ted by
manual operation of rocker switches on the
front panel of the transport. Manual control
is used to mount new reels of tape on the
transport, or as a quick maintenance check for
proper operation of the control logic in moving
the tape.
DEC tape Control Type TC02

The logic circuits of the TU55 control tape
movement in either direction over the read/
write head. Tape drive motor control is
exercised completely through the use of solid
state switching circuits to provide fast reliable
operation. These switching circuits contain
silicon controlled rectifiers which are controlled
by normal DEC diode and transistor logic circuits.
These circuits control the torque of the two
motors which transport the tape across the
head according to the established function of the
device, i.e., go, stop, forward, or reverse. In normal tape movement, full torque is applied to the
forward or leading motor and a reduced torque
is applied to the reverse or trailing motor to
keep proper tension on the tape. Since tape
motion is bidirectional, each motor serves as either
the leading or trailing drive for the tape, depending upon the forward or reverse control status
of the TU55. A positive stop is achieved by an

A maximum of eight TU55 DECtape transports
may be connected to one TC02. Of the four
data channels available, DECtape is assigned to
channel 0 (i.e., core memory locations 30 and
31 ).
C(30) = Word Count (in 2s complement form)
- WC
C(31) = Current Address Register - CA
Data transfers may take place to or from only
one transport at any given time at a rate of
one word every 200 microseconds (I block of
25610 words every 53 msec), after the desired
block has been found (see DEC tape summary
for complete timing information).
Since the CA is incremented before the data
transfer (except in search where the CA is not
incremented), the initial contents should be set
5-3

to the desired initial address minus one. The
WC is also incremented before- each transfer
and must be set to the 2s complement of the
desired number of data transfer. In this way,
the word transfer which causes the word count
overflow is the last transfer to take place.

of data recorded during the WRITE DATA
function. It is used for automatic parity checking during the READ DATA function.
Command and Status Bit Configuration

Status Register A (Command Bits)

The number of lOTs required for the TC02 is
minimized by the scheme of transferring all
necessary DECtape control data (i.e., unit,
function, mode, direction, etc.) from the AC
to the control using one set of lOTs (refer
to table 5-1). Similarly all status information
(i.e., aU above information plus status bits,
error flags, etc.) can be read into the AC from
the control unit via a second set of lOTs.

Bit

A 6-bit parity check character is computed (the
XOR of the reverse parity check character
and every 6 bits of every data word) and
recorded by the DECtape control for every block

o
1
2
3

4
5

} Unit selection 1 through 8 0, 2, 3, ........... 7, 0)
Motion:
Motion:
Transfer Mode:

TABLE 5-1

Assignment

Function

Forward-O; Reverse-l
Stop-O; GO-l
Normal (NM)-O; Continuous
Mode (CM)-1
o - MOVE
1 - SEARCH
2 - READ DATA
3 - READ ALL
4 - WRITE DATA
5 - WRITE ALL
6 - WRITE TIMING and
MARK TRACK
7 - SELECT ERROR

TC02 CONTROL lOT INSTRUCTIONS

------------------------------------------------------------------------------------Mnemonic

Octal Code

Description

DTCA

707541

Clear status register A. The DECtape control and
error flags are undisturbed (DTF and EF).

DTRA

707552

Read status register A. The AC is cleared and the
content of status register A is ORed into the
accumulator.

DTXA

707544

XOR status register A. The exclusive OR of th,~
content of bits 0 through 9 of the accumulator and
status A is loaded into status register A, and bits
10 and 11 of the accumulator are sampled to control
clearing of the error and DEC tape flags, respectively.
Any time this command is given with AC bits 0-4
set to 1, the select delay of 120 msec will be
incurred.

DTLA

707545

Load status register A. Combines action of DTCA
and DTXA to load ACO-9 into status register A.
Bits 10 and 11 control clearing of error and DECtap(~
flags, respectively.

DTEF

707561

Skip on error flag. The state of the error flag (EF)
is sampled. If it is set to 1 the content of the
PC is incremented by one to skip the next sequential
instruction.

DTRB

707572

Read status B. The AC is cleared and the cont,ent
of status B is ORed into the accumulator.

DTDF

707601

Skip on DECtape flag. The state of the DECtape
flag (DTF) is sampled. If it is set to aI, the
content of the PC is incremented by one to skip
the next sequential instruction.

------------------------------------------------------------------------------------5-4

9
10
11

Disable (0); Enable (1) DTF and EF to cause
Program Int.
Error Flag - Clear (0); Undisturbed (1)
DECtape Flag - Clear (0); Undisturbed (1)

Status Register B (Flag and Error Status Bits)
Bit

Assignment

Error Flag
Mark Track Error
End of Tape
Select Error
Parity Error
Timing Error
Unused
DEC tape Flag

1
2
3
4
5
6-10
11

All 10 command bits (0-9) of status register A
may be sensed, set or changed via lOTs. Bits
10 and 11 of the AC are not retained by
status A, but enable or disable the clearing of
the DECtape and ERROR flags. The bits in
status register B may be sensed and cleared by
lOTs. To issue a DECtape command, the
command bits 0-9 of status register A are set
as desired by bits 0-9 of the AC with bits 10
and 11 set to O. Bit 11 of register B is set when
a DTF occurs and must be cleared before the
next DTF to avoid a timing error. When any
error occurs, bit 0 of register B and the corresponding bits 1-5 will be set depending on the
error. This bit must be cleared to avoid further
interrupts on the same condition. All error
flags (i.e., status register B) are cleared by issuing
a DTXA instruction with AC bit 10 set to O.

Move - The MOVE function simply sets the
selected unit in motion (forward/reverse).
NM and CM have no meaning and are ignored
in this function alone. When the tape enters
either end zone* (Le., beginning of tape
(BOT) and end of tape (EOT)), and the unit
in question is selected:
1.

the error flag (EF) is set.

the EOT bit (bit 2 of status register B)
is set.

an interrupt occurs**

A program check on the forward/reverse
motion bit (AC bit 3) of the status register
will determine whether EOT or BOT occurred.
However, if the unit is deselected, the tape
runs off the reel with no flags raised and
no interrupt. In order to stop a selected unit
at any time, the GO bit (AC bit 4) must be
set to O. *** Once a unit is deselected, status
information pertaining to that unit is no
longer accessible unless it was saved by the
program prior to deselection.
Search - The search function provides the
capability of random access of data blocks on
DECtape. This function is used to locate the
number of the block to or from which data
transfer will occur. In normal mode at each
block mark until EOT occurs, the DTF is
raised and an interrupt occurs. The block

DECtape System Programming Information
*If either end zone is entered during turn around

The seven functions available with the Te02 and
their octal numbers as specified by the bits 6-8
of the AC are as follows:

and no interrupt occurs.

Function

** All references to the occurrence of interrupts
assume both:

Octal No.

MOVE
SEARCH
READ DATA
READ ALL
WRITE DATA
WRITE ALL
WRITE TIMING and MARK TRACK
Unused at present (select error if given)

o
1
2

3
4
5

or during stopping of tape, the EOT bit is not set

1. The program interrupt is on.
2. The DTF and EF have been enabled to the
program interrupt or API (i.e., bit 9 of status register A is set to a 1). If either of these
is not true, flags are raised and status bits
are set (and may be sensed and/or cleared),
but no interrupt occurs.

All functions take place in either direction and
in either normal mode (NM) or continuous mode
(CM). NM differs from CM only in the fact that
the DECtape flag (DTF) occurs at more frequent
intervals in NM. The DTF settings which occur
in NM are eliminated in the CM until word
count overflow (WC) has occurred.

***When setting the GO bit to 0, the forward/
reverse motion bit and unit selection bits should
not be changed from their current status. The
hardware accepts the change in the TC02 (i.e.,
status A bit 3 changes from its former state) without error indication, but does not pass this change
on to the transport. Programming confusion can
result.
5-5

number is automatically transferred by the
hardware into the memory location specified
by the CA. The CA must have been set previously by the program but the contents are
not incremented. The WC is incremented at
each DTF; the program must clear the DTF
bit in the status register and check the block
number until the desired one is found.
In continuous mode, the WC is set to the 28
complement of the number of blocks to skip.
At each block mark, the block number is
read into the memory location specified by
the CA which is not incremented. The DTF
is raised only at the block mark at which the
WC overflows~ At that time, an interrupt
occurs. Continuous mode provides a virtually
automatic DECtape search.
Read Data - READ DATA is used to transfer blocks of data into core memory with the
transfer controlled by the standard tape format.
The standard block length is 256 18-bit words.
For this and all following functions, the CA
register initially must be set to (the transfer
memory location - 1) because the CA register
is incremented just before each word transfer.,
The WC register is also incremented prior to
each word transfer so must be set to the 2s
complement of the number of words to be
transferred prior to the transfer. Data may be
transferred in forward or reverse.
Any number of words equal to or less than 1
block may be transferred in NM. The DTF
is raised and an interrupt occurs at the end of
each block. The DTF must be cleared before
the beginning of the next block (i.e., 1.7
msec) to avoid an erroneous timing error,
(see summary). When partial blocks are transferred data transmission will have been ended
withWC overflow (i.e., the word which causes
the we overflow is the last one transferred).
However, the remainder of the block is read
and parity checked before the DTF and interrupt occur. Tape motion continues until the
GO bit is reset to 0 by the program. If the
GO bit is not reset to a 0 or a new function
specified before the end of the next block,
a timing error will occur. READ DATA in
NM is intended primarily for single, 256-word,
block transfers. If any other number of words
is to be transferred, it is advantageous to use
CM. However, if the programmer chooses to
use NM for any other number of words, the
program Inust check for WC overflow at each
interrupt since there is no other way to determine when to stop the tape or change to
another function. When the WC overflow
occurs, it is essential that the function be
changed or the GO bit set to O. Otherwise
5-6

transfer begins again (the lOT to clear the
DTF implicitly specifies the same function
again) at the next block (or next word for
the ALL functions) since WC = OOOOOOs
is valid.
Any number of words may be transferred in
CM. However, the DTF and an interrupt occur only once after a WC pverflow and an end
of block. The comments concerning tape continuation apply in CM as well as NM.
Read All - The READ ALL function allows information to be read from an unusually for-matted tape essentially reading all data channels
recorded on DECtape regardless of the mark
track value. During the READ ALL function
the DEC tape control does not distinguish bl~
tween different marks recorded on the mark
track - except to check for mark track errors
(MKTK).
In normal mode (NM), the DTF is raised and
causes an interrupt at the end of each IS-bit
word transfer. Data transfer stops after WC
overflow, but tape motion continues until the
GO bit is set to 0 or a new function is
specified (in both NM and CM). If the DTF is
not cleared after each word transfer, a timing
error occurs at the end of the next word {i.e.,
200 microseconds later).
For continuous mode, the DTF is raised and
causes an interrupt at WC overflow only. If
this interrupt is ignored no more data transfers
occur but tape motion continues to EOT.
Write Data - The write enable switch on the:
TU 55 must be in write enable position for all
WRITE functions. All the details of the READ
DATA function description apply with the
following exceptions.
In normal mode, the DTF is set to a I at the
end of each block. If WCO did not occur in
the block just ended and a new function is
specified, the next block will be written
(provided the DTF has been cleared). If VVC
overflow did occur in the block just ended and
no new function is specified, the tape continues
to move but the writers are disabled. In both
CM and NM, when partial blocks are written,
data transfer from core to DECtape stops at
WC overflow. OOOOOOs are written in the
remaining data words of the block and the
parity check character is computed over the
entire block and recorded.
In continuous mode, the DTF is set at the end
of the block in which WC overflow occurred.
Therefore, if no new function is specified, the
tape continues to move but the writers are
disabled.

Write All
All the details of the READ ALL
function description apply. The WRITE ALL
function is used to write an unusual format
(such as block numbers on DECtape after timing and mark tracks have been recorded). The
word which causes WC overflow is the last
one written in NM or CM. The tape continues to move but the writers are disabled.

Error Conditions - Five types of errors can be
detected in the use of DECtape:

NOTE: Change of function must be delayed
for 90 microseconds to insure recording of
last word. Alternative method: set WC to
1 greater than desired number of word transfers and change function within 40 microseconds after WCO.

For all errors the EF is raised, a bit is set in the
status register and an interrupt occurs (if the
enable-to-interrupt bit has been set). The DTEF
instruction skips on the inclusive OR of those
error bits; hence, each status bit must be checked
to determine the kind of error. For all but the
parity error, the selected transport is stopped and
the EF is raised at the time of error detection.
No DTF occurs. For a parity error, the GO bit
remains 1 (i.e., motion continues) and the EF is
raised simultaneously with the DTF in NM. Only
1 interrupt occurs; hence the program must
check the EF.

Write Timing and Mark Track This
function and only this function may be performed with the selector switch on write
timing and mark track (WRTM) on the maintenance control panel. Whereas the timing
track is actually hardware recorded during
execution of this function, the mark track is
generated and recorded by program. The
value written in the mark track is determined
by bits 0, 3, 6, 9, 12, and 15 of the 18-bit
word being written (Le., the same bits
assigned to channell).
CM may be conveniently used for this function
since the hardware WC provides an automatic
counter and interrupt at WC overflow only;
in NM, the DTF and interrupt occur at every
word until WC overflow. In NM, after WC
overflow, if the GO bit or DECtape flag are
not cleared, a timing error occurs and no more
data is recorded. After WC overflow in CM,
if the GO bit is not set to 0, zeros are written
down on tape.
Enable the Interrupt Feature - The enable-to-theinterrupt feature allows the program to remove
DECtape from the program interrupt line (even
if the interrupt is ON). This is primarily of
value in the automatic priority interrupt system.
When command bit 9 in the status register is
set to aI, the TC02 is connected to the interrupt system. If this bit is 0, the DTF in the
TC02 cannot cause an interrupt even if the
interrupt facility in the PDP-9 is ON. Similarly, any of the five error conditions will
cause an interrupt if bit 9 is set to I in the
status register but cannot cause a program interrupt if bit 9 is a O.
Whether this bit is set or not does not influence
the setting of status bits 0-5 of the status register B upon receipt of an error flag (EF) or DTF.
Similarly, the result of the I/P skip instruction
is independent of the condition of this bit.

Timing Error
Parity Error
Select Error
End of Tape
Mark Track Error

A parity error in CM raises the EF at the end of
the block in which the parity occurs causing an
interrupt (if enabled). If no program action is
taken, e.g., stop transport or reverse and re-read,
data transfer continues and the DTF is raised
and causes an interrupt at WC overflow and end
of final block read.
Timing Error - A timing error (program malfunction) is a 'data miss' or program failure
to clear the DTF status bit. A timing error
occurs also if the program switches to READ
or WRITE DATA function while the DEC tape
is currently passing over a data area on tape.
Parity Error - A parity error occurs only during the READ DATA function for a hardware
computed parity check character (PCC) failure.
Select Error* - A select error will result under
any of the following conditions:
1.

Selection of zero or > 1 unit.

2. Attempt to write on DECtape transport
with WRITE ENABLE/WRITE LOCK switch
in the WRITE LOCK position.
3. Attempt to select unit for any function
with DEC tape transport REMOTE/OFF /
LOCAL switch in the OFF or LOCAL
(off-line) position.

*No-tape or tape-run-off-reel conditions are not
detectable.
5-7

4. Attempt to write timing and mark
tracks with the DECtape controls switch
in any position other than write timing
and mark track.
5. Attempt to perform any function other
than write timing and mark tracks with the
DECtape control switch in the write timing
and mark track position.
6. Attempt to perform any function other
than read all with DECtape controls switch
in the read mark track position.
7. Attempt to execute unused function (7).
End of Tape - An EOT error occurs when the
DECtape enters either end zone with the GO
bit == 1 and the forward/reverse direction bit
set to continue in the same direction. In NM
and CM data transfer stops at the last legitimate
block, the EF is raised, the tape transport
stops and an error interrupt occurs.
Mark Track Error - A mark track error occurs
when the DEC tape control fails to recognize a
legitimate mark on the mark track. The error
may occur in an but the move or write timing
and mark track functions. In both CM and NM,
the EF is raised, the tape transport stops and an
interrupt occurs.
DECtape Programming Examples

The next interrupt will be at the desired block
number.
Read Data {Continuous Mode} - Assuming the
correct block number has been found, exa:mple
2 illustrates a possible way to code a data transfer function in continuous mode. One interrupt
will occur at the end of the transfer. This example continues from and relies on the preceding
example.
Read Data {Normal Mode} -. Normal mode pro-·
vides a convenient tool for double buffering or
processing large amounts of data on a block-byblock basis for economic use of core storage.
(See example 3.) It also allows for transfer of
non-contiguous blocks of data into contiguous
locations or vice versa. This example also con..
tinues from and relies upon example l.
Bootstrap Loading Technique - The data channel
facility and the design of CM allow for linked
loading of data from DECtape where the first
two DECtape data words determine the core location and amount of data which follows. Note
that the following technique will work only for
a data channel device whose CA and WC registers
are in core memory locations. The address into
which data is loaded is specified by CA. Thus
is the CA points to the We-I, the first word
transferred specifies the nunlber of words to be
transferred. After the first data word transfer,
the CA points to itself .and the second word transferred specifies where the following data is to be
loaded. No program interrupts, timing or com..
putation is required to locate the data. Only
the TC02 and DCH features are used.

Illustrated below are a few examples of possible
Problem:
ways to code DECtape functions on the PDP-9/L.
Son1e are intended to illustrate the obvious capaLoad x data words beginning at DECtape block
bilities of DEC tape. Others demonstrate some of
the more obscure features. Assumed as part of the 4 of unit 3 into core locations M to M+X-l,
assuming tape has been positioned at block 4.
hardware configuration is the API option. The
examples are written in PDP-9 Basic Symbolic
IBOOTSTRAP EXAMPLE
Assembler language.
Auto-Search - The combined use of NM and CM
(exarnple 1) provides virtually automatic DECtape
search for a desired block number with a minimum
(2) of interrupts.
l. Search forward in NM to find next block
number.

2. Compute difference between this and the
desired block number.
3. Set WC=2s complement of this difference.
4,

5-8

Switch to search in CM.

DZM 30
LAC (27
DAC 31
LAC IOTD
DTLA

IOTD,

332400

ITO INSURE NO WC OVERFLOW
ITO BEGIN LOADING AT REGISTER
130
ICA
IIOT DATA
ILOAD STATUS REGISTER

IREAD ON UNIT
3, CM, FORWARD,
IGO (1)
IWITH INTERRUPT ENABLE D

The following represents the format of the data
on the tape starting at block 4.

Miscellaneous Information - Additional information concerning DECtape programming is provided in the subsequent paragraphs.

WC (25 COMP)

m -,

BLOCK

4
DATA

BLOCK 5 {

~~=---

WC
X DATA
WORDS

BLOCK 4+ « X I 2 5 6 ) - ' I c = = = J

WHERE X IS

AN INTREGRAL MUL TIPLE

Scatter Read/Gather Write - By program manipulation in CM, it is possible to scatter read
or gather write on DECtape. A separate programmed WC must be maintained and incremented as the hardware increments its WC.
When program WC overflows, the CA may be
reset to the beginning of another core area.
With a 200 microsecond word transfer rate,
(±30%) there is ample time to reset the CA.
Note that this function is impossible if other
interrupts are likely to occur.
Modification of Individual Data Words - This
technique should not be used.

OF 256

Writing and Reading in Opposite Directions As mentioned earlier, it is possible (though nontrivial) to read data from a DECtape in the
opposite direction from which the data was
written via program manipulation. Are-ordering
of both the entire block and individual words is
required, however.
a. Block Re-ordering: A block of words
x n X 1 recorded in one direction is loaded
into core as Xn X 1 when read in the
opposite direction.

b. Word Unscrambling: Data read in backwards comes into core memory locations from
the TC02 in the following IS-bit format:

Data Transfer -- Upper Bound Protection - The
WC controls are data transfers. After WC overflow, no more date transfers take place. Thus,
to protect memory when reading a block of
unknown length, the WC is set to the 2s complement of the difference betwe en the initial
address where data is transferred and the upper bound.
Similar action prevents writing beyond a predetermined point on tape when transferring
an unknown number of words from core.
Special Formats on Tape - The user is cautioned to always specify an even number of
words in his special format. If he does not,
the control will indicate parity errors where
none exist.

o c E - - - - - - - - - - - p 17

Programming Note: When a turn-around command is issued (i.e., complement the direction
bit while the GO bit remains set to 1), the
tape may not be up to speed when the point
at which the command was issued is passed
(in the new direction). The tape will be up
to speed one standard 256 word block length
after the turn-around point. Therefore, to find
a block in the opposite direction it is sufficient
to delay the turn around one block as shown
in figure 5-2.

NOTE: If data is to be re-ordered on the fly,
the routine is limited to 140 microseconds
since the word transfer rate = 200 microseconds (±30%). The probability of such a
routine not working is very high if interrupts
from other devices are encountered.

With this turn around specification finding
blocks next to the end zones requires special
handling. Block 0 forward may be found if
the tape is backed into the end zone twice
before turning around. To prevent this special
end zone handling, a new formatting program
must be written which provides one block
length of inter-block zone marks (no-op marks)

Bits:
15 16 17 12 13 14 9 10 11 6 7 S 3 4 5 0 1 2
In bit positions:

5-9

Example 1:

----~------------------------------------------------------------------------IAUTO-5EARCH EXAMPLE
BEGIN,

LAC (CBLK
DAC 31
DZM 30
LAC (JMP SEARCH
DAC SWITCH
LAC (321600

ICBLK=TEMP STORAGE
ICA - DECTAPE
IINSURE NO WC OVERFLOW

DTLA

/SEARCH DECTAPE UNIT 3, IN FORWARD
IDIRECTION, NM, GO (1), FLAGS ENABLED
ILOAD STATUS REGISTER
.,.

JMS DECTAPE

IDECTAPE=API CHANNEL 44

IINTERRUPT SERVICE ROUTINE

441

YI
DECTAPE,

DAC ACSAV
DTEF
SKP
JMP DECER
DTDF
SKP
JMP SEARCH

SWITCH,

SEARCH,

ISKIP:

ISERVICE DECTAPE ERROR TO BE WRITTEN BY USER
ISKIP ON DTF - REQUIRED ONLY IF OTHER
IDEVICES ON SAME API CHANNEL

lOR JMP REDE

ZI
LAC CBLK
AND (007777
SAD RBLK
JMP RBLKS
CLC
TAD CBLK
DAC TEMP
CLC
TAD RBLK
CMA
ADD TEMP
SMA
JMP REV
DAC 30
LAC (010000·
DTXZ

LAC ACSAV
DBR
JMP I DECTAP

ICURRENT BLOCK NUMBER
IDESI RED BLOCK NUMBER
ISERVICE CORRECT BLOCK
ICOMPUTE BLOCK NUMBER
IDIFFERENCE AND DIRECTION
/OF SEARCH
/53 MS ARE AVAILABLE TO
ISWITCH FROM SEARCH NM
ITO SEARCH CM
IREVERSE DIRECTION
IWC=2'S COMP OF DIFFERENCE
ICM
/XOR STATUS
AC AND
/LOAD STATUS REGISTER
INEXT INTERRUPT WILL BE
IDESIRED BLOCK NUMBER
IEXIT

*If the program were to clear and then load status register A, the control would cause the select delay of
120 msec. However, by simply setting the bit to a 1 in the AC for the corresponding status register bit,
the change is made but no select delay occurs.

Example 2:
IREAD DATA EXAMPLE
AI
RBLKS,

SELRD,

5-10

CLC
TAD ADDR
DAC31
CLC
TAD WDCNT
CMA
DAC 30
LAC (003000
DTXA

ILOAD AC WITH - 1
ISET CA=ADDRESS - 1
ISET WC=2'S COMPLEMENT
10F NO. OF WORDS TO TRANSFER
lAND LOAD STATUS REGISTER
IREAD DATA, FORWARD, GO, CM,
/FLAGS ENABLED, UNIT 3

Example 2 con't:

ADDR,
WDCNT,

LAC (JMP REDE
DAC SWITCH

/RESET INTERRUPT CHAIN
/JMP

LAC ACSAV
DBR
JMP I DECTAP
ADORES
N

/DEBREAK
/EXIT

Example 3:
/DOUBLE BUFFER EXAMPLE
A/
RBLKS,

RESET1,
RESET2;

REDE,

STOP,

/CONTINUES FROM SEARCH EXAMPLE
CLC
TAD WDCNT
CMA
DAC 30
LAC (BUF1
DAC ADDR
CLC
TAD ADDR
DAC 31
LAC (013000
DTXA
LAC (JMP REDE
DAC SWITCH
LAC ACSAV
DBR
JMP I DECTAP
LAC 30
SMA
JMP STOP
LAC (BUF2
SAD ADDR
JMP RESET1
JMP RESET2
LAC (020000
DTXA

/WC=2'S COMPLEMENT OF
/1 NO. OF WORDS TO TRANSFER

/CA = ADDRESS - 1
/LOAD STATUS REGISTER:
/READ DATA, FORWARD, GO, NM
/FLAGS ENABLED, UNIT 3
/RESET INTERRUPT CHAIN JMP

/EXIT
/CHECK WC OVERFLOW
/STOP DECTAPE
/NO OVERFLOW
/RESET ADDR TO
/SWITCH BUFFER
/SET GO = 0, CLEAR DTF AND EF
/LOAD STATUS REGISTER

Example 4:
/SUBROUTINE TO REORDER A DECTAPE BLOCK OF N WORDS WHERE N=EVEN NUMBER
fUSES SUBROUTINE UNSCR TO UNSCRAMBLE INDIVIDUAL WORDS. ENTRANCE
/PARAMETERS: BUFFER LOCATIONS - HIGH AND LOW, HIGH LOC = C(DTHAD)
/LOW LOC = C(DTLAD) 23 DECIMAL REGISTERS, 37 MICROSECONDS FOR EVERY 2 WORDS OR
/24.2 MS FOR REORDERING AND UNSCRAMBLING 256 DECIMAL WORDS.
DTORD,
DTBEG,

DTEXIT,

DTLAD,
DTHAD,
DTTAM,

LAC I DTLAD
DAC DTTAM
LAC I DTHAD
JMS UNSCR
DAC I DTLAD
LAC DTTAM
JMS UNSCR
DAC I DTHAD
ISZ DTLAD
LAC DTLAD

SAD DTHAD
JMP I DTORD
CLC
TAD DTHAD
DAC DTHAD
JMP DTBEG

o
o
o

/SAVE LOWEST UNSCRAMBLED
/WORD OF BLOCK
/UNSCRAMBLE HIGH WORD
/UNSCRAMBLE 1 WORD SUBR
/STORE IN FREE LOW LOC
/UNSCRAMBLE LOW WORD
/STORE IN FREE HIGH LOC
/INCREMENT LOW ADDRESS
/WHEN DTLAD+1 - DTHAD
/REORDERING IS COMPLETE
/EXIT
/DECREMENT HIGH ADDRESS
/UNSCRAMBLE NEXT SET OF 2
/LOW, HIGH BLOCK ADDRESSES
/TEMPORARY STORAGE

5-11

Example 4 con't:
IUNseR, 53 DECIMAL REGISTERS, 76 MICROSECONDS SUBROUTINE TO UNSCRAMBLE ONE 18·BIT
IDECTAPE WORD IN AC. RESULT IN AC
UNSCR,
0
IRETURN ADDRESS
CMA
ICOMPLEMENT
IINITIALIZE INTERMED. RESULT REG
DZM UNT
RALVCLL
RTL
IARG. TEMPORARY STORAGE
DAC UNT1
AND (007000
IBITS 6, 7, 8
IASSEMBLE BITS IN
XOR UNT
DAC UNT
IINTERMED. RESULT REGISTER
LAC UNT1
IRESUME CYCLING
RAL
DAC UNT1
IBITS 15, 16, 17
AND (000007
XOR UNT
DAC UNT
LAC UNT1
RAL
RTL
RTL
DAC UNT1
IBITS 3, 4, 5
AND (070000
XOR UNT
DAC UNT
LAC UNT1
RAL..
DAC UNT1
IBITS 12, 13, 14
AND (000070
XOR UNT
DAC UNT
LAC UNT1
RAL
RTL
RTL
DAC UNT1
IBITS 0, 1, 2
AND (700000
XOR UNT
DAC UNT
LAC UNT1
RAL
DAC UNT1
IBITS 9, 10, 11
AND (000700
XOR UNT
JMP I UNSCR
IEXIT WITH AC = RESULT
UNT,
IINTERMED. RESULT OF UNSCRAMBLING
o
UNT11,
IARG TEMP. STOR.
o

-----------------------------------------------------------------------------------so that program can bounce off the end zone
and find block 0 (if the tape has the new format on it). The end zone problenl is also
solved for either format by not using the
block next to the end zones (block 0, 1101).
When using non-standard format tape (i.e.,
not 1102 8 blocks of 400 8 words) a length
of tape equal to one 18 bit, 256 10 (400 8 )
word block must pass the head before the
turn around command is issued. This is
approximately five inches of tape. However,
when calculating the required delay for a
non-standard format tape it should be computed in equivalent standard block lengths.
Example: Turn around delay calculation
for blocks of 94 10 words.
256 words/block x 1 block delay:: 2.7 block delay
92 words block
required

5-12

DECtape Func tion Summary - The DECtape function summary is provided in table 5:'2.
DECtape Error Summary - The DECtape error
summary is provided in table 5-3.
DECtape Timing Data - The DECtape timing data
on standard format (certified) tape is provided in
table 5-4.

MAGNETIC TAPE CONTROL, TYPE TCS9
The Type TC59 will control the operation of a
maximum of eight digital magnetic tape transports manufactured by Digital Equipment Corporation. The Type TC59 interfaces and uses
the PDP-9/L data channel (DCH) facility to
execute data transfers between system Gore
memory and magnetic tape. Transfers are governed by the in-memory word counter (WC) and
current address (CA) register associated with

HEAD

TAPE MOTION
REV.

+--

STANDARD 18 BIT, 256 WORD, TC02,
PDP-9 BLOCK FORMAT

u...

~
~

a::

u...

DATA

a::

;;:;

FWD.

-----

u...

DATA

;;:;

~
NOTES:

a::

1.) CONSIDER HEAD FIXED WITH TAPE MOVING PAST IT
2.) 31-R-R REVERSE BLOCK;r lie RECOGNIZED ONLY IN REV.)
3. ) 31-F - F FORWARD BLOCK.+' (ie RECOGNIZED ONLY IN FWD.)

TO FIND BLOCK 32 FORWARD:

1. ) SEARCH REVERSE TO BLOCK 30
2.) TURN AROUND AND SEARCH FORWARD FOR BLOCK 32
3.) BLOCK 31 MAY BE FOUND BUT BLOCK 32 IS
GUARANTEED TO BE FOUND.

Figure 5-2 Location of Block in Opposite Direction
TABLE 5-2 DECTAPE FUNCTION SUMMARY
Function
O. Move

DTF:
CA:
WC:

No Interrupt
Ignored
Ignored

1. Search

DTF:

Interrupt at each block
mark
Not incremented
Incremented at each
block mark
Interrupt at end of
each block
Incremented at each
word transfer
Incremented at each
word transfer

CA:
WC:
2. Read Data

DTF:
CA:
WC:

3. Read All

Continuous Mode (CM)

Normal Mode (NM)

DTF:
CA:
WC:

Interrupt at each
word transfer
Incremented at each
word transfer
Incremented at each
word transfer

4. Write Data

Same as 2. Read Data

S. Write All

Same as 3. Read All

6. Write Timing & Mark Tracks

Same as 3. Read All

Same as NM
DTF:
CA:
WC:
DTF:
CA:

we:

Interrupt at block mark where
WC overflows
Not incremented
Incremented at each block mark
Interrupt at WC overflow and
end of block
Incremented at each word
transfer
Incremented at each word
transfer

DTF:

Interrupt at WC overflow

CA:

Incremented at each word
transfer
Incremented at each word
transfer

WC:

7. Unused*
*If used by mistake, the control gives a Select Error (SE).

5-13

TABLE 5-3

DECTAPE ERROR SUMMARY

Function
Move
Search

Read Data

Read All

Write Data

Write All

Write Timing
& Mark Tracks

TABLE 5-4 DECTAPE TIMING DATA

-----------------------------------------------------------------------------.Time
Operation
Time to answer data channel request

Up to 66 microseconds *

Word Transfer Rate

I8-bit word every 200 microseconds *

Block Transfer Rate

256 word block every S3 milliseconds*

Start Time

375 milliseconds (± 20%)

Stop Time

375 milliseconds (± 20%)

Turn Around Time (see programming note on page 5-20)

375 milliseconds (± 20%)

Search ~ Read Data Function change for present block

Up to 400 microseconds*

Search ---+- Write Data Function change for present block

Up to 400 microseconds *

Read --+ Search Function change for next block number

Up to 1000 microseconds *

-------------------------------------------------------------------------,----5-14

TABLE 5-4 DECTAPE TIMING DATA (continued)
Time

Operation
Write ---+- Search Function change for next block number

Up to 1000 microseconds *

DTF to beginning of next data block

1.7 milliseconds *

DTF Occurrenct:
Move: NM, eM

Never

Search: NM
Read Data: NM
Write Data: NM

Every 53 milliseconds*

Search:

(we) X53 milliseconds*

Read Data: eM
Write Data: eM

(No. of blocks) X53 milliseconds*

Read All: NM
Write All: NM
Write Timing & Mark Tracks:

Rea Read All: eM
Write All: eM
Write Timing & Mark Tracks:

Every 200 microseconds *

(we) X200 microseconds *

*(± 30%)

the assigned data channel (memory locations 32
and 33 8 ). Since the CA is incremented before
each data transfer, its initial contents should
be set to the desired initial address minus one.
The WC is also incremented before each transfer and must be set to the 2's complement of
the desired number of data words to be transferred. In this way the word transfer which
causes the word count to overflow (WC becomes zero) is the last transfer to take place.
The number of lOT instructions required for
the Type TC59 is minimized by transferring
all necessary control data (i.e., unit number,
function, mode, direction, etc.) from the
PDP-9/L accumulator (AC) to the control
using lOT instructions. (Refer to Table 5-5.)
Similarly, all status information (i.e., status
bits, error flags, etc.) cari be read into the AC
from the control unit by lOT instructions.
During normal data reading, the control
assembles 18-bit length computer words from
successive frames read from the information
channels of the tape. During normal data
writing the control disassembles 18-bit words
and distributes the bits so they are recorded
on successive frames of the information channels. The control provides for selection of four
recording densities: 200, 556, 800, and 800/9channel.

Although any number of tapes may be simultaneously rewinding, data transfer may take place
to or from only one transport at any given time.
In this context, data transfer includes these
functions: read or write data, write EOF (end
of file), read/compare and space. When any of
these functions are in process, the tape control
is in the "not ready" condition. A transport
is said to be "not ready" when tape is in motion,
when transport power is off, or when it is offline.
Data transmission may take place in either parity
mode, odd-binary or even-BCD. When reading
a record in which the number of characters is
not a multiple of the number of characters per
word, the final characters come into memory
left -j ustified.
Ten bits in the magnetic tape status register
retain error and tape status information. Some
error types are combinations, such as lateral
and longitudinal parity errors (parity checks
occur after both reading and writing of data),
or have a combined meaning, such as illegal
command, to allow for the maximal use of the
available bits.
The magnetic tape status register reflects the
state of the currently selected tape unit. Inter5-15

TABLE 5-5

TC59 CONTROL lOT INSTRUCTIONS

---------------------------------------------------------------------------------Mnemonic

Octal Code

Description

MTSF

707341

Skip on error flag or magnetic tape flag. The status of
the error flag (EF) and the magnetic tape flag (MTF) are
sampled. If either or both are set to 1, the conte lilts
of the PC are incremented by one to skip the next
sequential instruction.

MTCR

707321

Skip on tape control ready (TeR). If the tape control
is ready to receive a command, the contents of the PC
are incremented by one to skip the next sequential
instruction.

MTTR

707301

Skip on tape transport ready (TTR). The next
sequential instruction is skipped if the tape transport
is ready.

MTAF

707322

Clear the status and command registers, and the EF
and MTF if tape control ready. If tape control not
ready, clear MTF and EF flags only.

707302

Inclusively OR the contents of the command register
into bits 0-11 of the AC.

MTCM

707324

Inclusively OR the contents of Ac bits 0-5, 9-1ll into
the command register; jam transfer bits 6, 7, 8
(command function).

MTLC

707326

Load the contents of AC bits 0-11 into the command.
register.

707342

Inclusively OR the contents of the status register into
bits 0-11 of the AC.

MTRS

707352

Read the contents of the status register into bit:; 0-11
of the AC.

MTRC

707312

Read the contents of the command register into bits
0-11 of the AC.

MTGO

707304

Set GO bit to execute command in the command
register if command is legal.

,--------....--------------------------------------------------------------------------------rupts may occur only for the selected unit. Therefore, other units which may be rewinding, for
example, will not interrupt when done.
A special feature of this control is the "Write
Extended Inter-Record Gap" capability. This
occurs on a write operation when Command
Register bit 5 is set. The effect is to cause a
3 inch inter-record gap to be produced before
the record is written. The bit is automatically
cleared when the writing begins. This is very
useful for creating a 3 inch gap of blank tape
over areas where tape performance is marginal.

5-16

Magnetic Tape Functions
For all functions listed below, upon completion
of the data operation (after the end-of-record
character passes the read head), the MTF (magnetic tape flag) is set, an interrupt occurs (if
enabled), and errors are checked.

No Operation - A NO OP command defines no
function in the command register. A MTGO
instruction with NO OP will cause an illegal
command error (set EF).

Space - There are two commands for spacing
records, space forward and space reverse. The
number of records to be spaced (2's comple-,
ment) is loaded into the WC. CA need not be
set. MTF (magnetic tape flag) is set, and an
interrupt occurs at WC overflow, EOF (end
of file), or EOT (end of tape), whichever
occurs first. When issuing a space command,
both the density and parity bits must be set
to the density and parity in which the records
were originally written.

Load Point or Beginning of Tape (BOT) detection during a backspace terminates the function
with the BOT bit set. If a space reverse command is given when a transport is at BOT, the
command is ignored, the illegal command error
and BOT bits are set, and an interrupt occurs.
Read Data - Records may be read into memory
only in the forward mode. Both CA and WC
must be set: CA, to the initial core address
minus one; WC, to the 2's complement of
the number of words to be read. Both density
and parity bits must be set.
If WC is set to less than the actual record

length, only the desired number of words are
transferred into memory. If WC is greater
than or equal to the actual record length, the
entire record is read into memory. In either
case, both parity checks are performed, the
MTF is set, and an interrupt occurs when the
end-of-record mark passes the read head. If
either lateral or longitudinal parity errors or
bad tape have been detected, or an incorrect
record length error occurs (WC not equal to the
number of words in the record), the appropriate
status bits are set. An interrupt occurs only when
the MTF is set.
To continue reading without stopping tape
motion, MT AF (clear MTF) and MTGO instructions must be executed. If the MTGO command
is not given before the shutdown delay terminates,
the transport will stop.
Write Dahl - Data may be written on magnetic
tape in the forward direction only. For the
write data function, the CA and WC registers and
density and parity bits must be set. Write data
is controlled by the WC, such that when the WC
overflows, data transfer stops, and the EOR (end
of record) character and IRG (inter-record gap)
are written. The MTF is set after the EOR has
passed the read head. To continue writing, a
MTGO command must be issued before the shutdown delay terminates. If any errors occur, the
EF will be set when the MTF is set.

Write EOF - The Write EOF command transfers
a single character (17 8 ) record to magnetic tape
and follows it with EOR character. CA and we
are ignored for write EOF. The density bits
must be set, and the command register parity
bit should be set to even (BCD) parity. If it is
set to odd parity, the control will automatically
change it to even.

When the EOF marker is written, the MTF is
set and an interrupt occurs. The tape transport
stops, and the EOF status bit is set, confirming the writing of EOF. If odd parity is required after a write EOF, it must be specifically
requested through the MTLC command.
Read/Compare - The read/compare function compares tape data with core memory data. It can
be useful for searching and positioning a magnetic tape to a specific record, such as a label
or leader, whose content is known in core memory, or to check a record just written. Read/
compare occurs in the forward direction only;
CA and WC must be set. If there is a comparison failure, incrementing of the CA ceases, and
the read/compare error bit is set in the status
register. Tape motion continues to the end of
the record; the MTF is then set and an interrupt occurs. If there has been a read/compare
error, examination of the CA reveals the word
that failed to compare.
Rewind - The high-speed rewind command does
not require setting of the CA or WC. Density
and parity settings are also ignored. The rewind
command rewinds the tape to load point (BOT)
and stops. Another unit may be selected after
the command is issued and the rewind is in process. MTF is set, and an interrupt occurs (if
the unit is selected) when the unit is ready to
accept a new command. The selected unit's
status can be read to determine or verify that
rewind is in progress.
Continued Operation

1. To continue operating in the same mode,
the MTGO instruction is given before tape
motion stops. The order of commands required for continued operation is as follows:
a.

MTCM, if the command is to be changed.

b. MTAF (will only clear MTF and EF flags
since tape control will be in a Not Ready
state).
c. MTGO (if LCM requested an illegal condition, the EF will be set at this time).

5-17

2. To change modes of operation, either in
the same or opposite direction, the MTCM
command is given to change the mode and a
MTGO command is given to request the continued operation of the drive. If a change in
direction is ordered, the transport will stop,
pause, and automatically start up again.
3. If the write function is being perfonned,
the only forward change in command that
can be given is write EOF.
4. If no MTGO instruction is given, the transport will shut down in the inter-record gap.

NOTE: No flags will be set when the control becomes ready or the transport becomes ready, except if the rewind command
is present in the command register and the
selected drive reaches BOT and is ready for
a new command.

~--

Lateral parity bit e.f character 1
Lateral parity bit of character 2
Character 1
9

Bit 0

Character 2

]
17

Read/Compare - A direct comparison of the
characters on tape is made with those in memory. The parity bits are ignored, as are bits 0
and 1 of each memory word.
Core Dump Mode - This mode is used only with
nine-track transports. I t is entered by setting
bit 4 of the command register.

Core dump mode permits the dumping of conlplete memory words in the form of three sixbit characters. The format is as follows.

Character 1

Bits 0

Character :2

Character 3 ]

5. If a write (odd parity) command is changed to write EOF, the parity is automatically
changed to even.

This is accomplished by only utilizing seven of
the nine tracks on the tape.

NOTE: Even parity will remain in the
command register unless changed by a new
command instruction, MTLC, which clears
and loads the entire command register.

Tape written in core dump mode must be read
(read/compare) in the same mode. These operations are the same as for a seven-track transport.
Status or Error Conditions

9-Tra.ck Opera.tion
Nine-· and seven-track transports may be intermixed on the Type TC59 control. When a
transport is selected, it automatically sets the
control for proper operation with its number of
tracks.
Control of nine-track operation is identical to
seven-track except as noted below.
Write - A word in memory is written on tape
with the format shown below.

Twelve bits in the magnetic tape status register
indicate status or error conditions. They are set
by the control and cleared by the program. The
magnetic tape status register bits are as follows.
Bit *

o
1

2
3
4

[x I x
Bit 0

Character 1
2

Character 2
9

~
17

x = these bits are ignored

6
7
8

9
10
11

Function (when set)
Error flag (EF)
Tape rewinding
Beginning of tape (BOT)
Illegal command
Parity error (lateral or
longitudinal)
End of file (EOF)
End of tape (EOT)
Read/ compare error
Record length incorrect
WC = 0 (long)
WC f 0 (short)
Data request late
Bad tape
Magnetic tape flag (M TF)
or job done

----------------------------------------Read - A word is read into memory from tape
with the format shown below.
5-18

*The register bits are equivalent in position to the Ae
bits (Le., SRo = AC 0 etc.).

MTF (SR 11) - The MTF flag is set under the
following conditions.
1. Whenever the tape control has completed
an operation (after the EOR mark passes the
read head).
2. When the selected transport becollles ready
following a normal rewind function.
These functions will also set the EF if any errors
are present. This flag sets bit 11 in the AC if
an IORS instruction is issued.

EOF (SR 5) -End-of-file (EOF) is sensed and may
be encountered for those functions which come
under the heading of read status function, i.e.,
space, read data, or read/compare and write EOF.
When EOF is encountered, the tape control sets
EOF = 1. MTF is also set; hence, an interrupt*
occurs and the EOF status bit may be checked.
EaT (SR6) and BOT (SR2) - End-of-tape (EOT)
detection occurs during any forward command
when the EOT reflective strip is sensed. When
EOT is sensed, the EOT bit is set, but the function continues to completion. At this time the
MTF is set (and EF is set), and an interrupt
occurs.
Beginning-of-tape (BOT) detection status bit occurs only when the beginning-of-tape reflective
strip is read on the transport that is selected.
When BOT detection occurs, and the unit is in
reverse, the function terminates. If a tape unit
is at load point when a reverse command is
given, an illegal command error bit is set, causing
an EF with BOT set. An interrupt then occurs.

Illegal Command Error (SR3) - The illegal command error bit is set under the following conditions.

1. A command is issued to the tape control
with the control not ready.
2. A MTGO command is issued to a tape
unit which is not ready, and the ·tape control
is ready.
3. Any command which the tape control,
although ready, cannot perform, for example.
*All references to interrupts assume the tape
flags have been enabled to the interrupt (command register bit 9 = 1) and that the unit is
selected.

Write with write lock condition.

Nine-channel tape and incorrect density.

BOT and space reverse.

Parity (SR4) - Longitudinal and lateral parity
checks will occur in both reading and writing.
The parity bit is set for either lateral or longitudinal parity failure. A function is not interrupted, however, until MTF is set. Maintenance
panel indicators are available to determine which
type of parity error occurred.
Read/Compare Error (SR 7) - When read/compare
function is underway, SR 7 is set to 1 for a read/
com.pare error (see earlier section on read/ compare for further details).
Bad Tape (SR10) - A bad tape error indicates
detection of a bad spot on the tape. Bad tape
is defined as three or more consecutive missing
characters followed by data, within the period
defined by the real shutdown delay. The error
bit is set by the tape control when this occurs.
MTF and interrupt do not occur until the end
of the record in which the error was detected.
Tape Rewinding (SR1) - When a rewind command has been issued to a tape unit and the
function is underway, the tape rewinding bit
is set in the control. This is a transport status
bit, and any selected transport which is in a highspeed rewind will cause this bit to be set.
Record Length Incorrect (SR8) - During a read
or read/compare, this bit is set when the WC
overflow differs from the number of words in
the record. The EF flag is set.
Data Request Late (SR9) - This bit can be set
whenever data transmission is in progress. When
the data flag causes a break cycle, the data must
be transmitted before a write pulse or a real
pulse occurs. If it does not, this error will
occur, and data transmission will cease. The EF
flag and bit 9 of the status register are set when
the MTF is set.
Error Flag (SR 0) - The error flag (EF) is set
whenever any error status bit is present at the
time that MTF is set. When an illegal command
is given, however, the EF is set and the MTF is
not set. This flag (as well as MTF) sets bit 11
in the AC if an IORS is issued.
5-19

Command Register Contents

SPACE FORWARD

CA:
WC:

Unit Selection (0-7)
Core!
Dump

,------A-

~Gl: [41
Parity
0= even
1 = odd

Command
5

Dens,ity

Write
extended
inter-record
gap (3-in. of
blank tape
before record)

OS:
EN:

-.,

i GJ

SPACE REVERSE

Flags
0= disable
1 = enable
OS:
EN:
READ DATA

Unil' Selection

CA:
WC:

CA:

Densit~ Selection

WC:
Unit Selection Bits
Unit
0

Density

0
0
0

0
0

0
OS:
PR:
EN:

800 bpi
9 channel

200 bpi

556 bpi
800 bpi

Density Bits

0
WRITE DATA
0

WC:

Command Selection -

OS:
PR:
EN:

Bits

Command

NO OP
Rewind
Read
Read/Compare
Write
Write EOF
Space Forward
Space Reverse

CA:

0
0
0
0

0
0
1

0
1
0

1
1
1
1

0
0
1

1
1
1

CA
WC
F
R
DS
PR
EN

Function

Characteristics

Status or Error Type

NO OP

CA: Ignored
WC: Ignored
OS: Ignored
PR: Ignored
EN: Ignored

Illegal
BOT
Tape Rewinding

5-20

Core address Illegal
-1
2s comple- EOF
ment of
number of
words to be
transferred
Must be set Parity
Must be set Bad Tape
Must be set MTF
EOT
Request Late
Record Length I ncorrect
Core address Illegal
-1
2s comple- EOF
ment of
number of
words to be
transferred
Must be set Parity
Must be set MTF
Must be set Bad Tape
Data Request l.ate

CA:
WC:
OS:
PR:
EN:

Illegal
Ignored
EOF
Ignored
Must be set Parity
Must be set MTF
Must be set Bad Tape
Data Request L.ate

READ/COMPARE

CA:

Core Address Illegal
-1
2s comple- EOF
ment of
number of
words to be
transferred
Must be set Read/Compare Error
Must be set Bad Tape
Must be set MTF
EOT
Data Late
Record Length
Incorrect

WC:

OS:
PR:
EN:

= Current Address Register =

32 8
= Word Count Register = 33 8
= Forward
= Reverse
= Density Setting
= Parity Setting
= Enable Interrupt

Illegal
Ignored
2s comple- EOF
ment of
number of
records to
skip
Must be set Bad Tape
Must' be :~et BOT,MTF

WRITE EOF

Magnetic Tape Function Sunlmary
LEGEND:

Illegal
Ignored
2s complle- EOF
ment of
number of
records to
skip
Must be set Bad Tape
Must be set MTF,BOT,EOT

REWIND

CA:
WC:

os:

PR:
EN:

Illegal
Ignored
Tape Rewinding
Ignored
MTF
Ignored
BOT
Ignored
Must be set

MAGNETIC TAPE TRANSPORT, TYPE TlJ20
(7-CHANNEL)
The Type TU20 is a digital magnetic tape trans··
port designed to be compatible with the Type

TC59 Magnetic Tape Control. The transport
operates at a speed of 45 in./sec and has three
selectable densities: 200, 556, and 800 bpi. The
maximum transfer rate is 36,000 six-bit characters
per second. Standard seven-channel IBM-compatible tape format is used. The specifications for
the unit are as follows.
Format - NRZI. Six data bits plus one parity
bit. End and loadpoint sensing compatible
with IBM 729 I-VI.
Tape - Width of 0.5 in. Length of 2400 ft.
(1.5 mil.). Reels are 10.5 in., IBM-compatible with file protect (write lock) ring.
Heads - Write-read gap of 0.300 in. Dynamic
and static skew is less than 14 microseconds.
Tape Specifications - 45 ips speed. Start
time is less than 5 msec. Rewind time for
2400 ft. is less than 3 min. Start distance
is 0.080 in. (±0.035, -0.025 in.). Stop time
is less than 1.5 msec. Stop distance is 0.045
in. (±O.O 15 in.).
Density - 200, 556, and 800 bpi.
transfer rate is 36 kHz.

Maximum

Transport Mechanism-- Pinch roller drive;
vacuum column tension.
Controls - ON/OFF, ON LINE, OFF LINE,
FORWARD, REVERSE, REWIND, LOAD,
AND RESET.
Physical Specifications - Width of 22-1/4 in.,
depth of 27-1/6 in., height of 69-1/8 in.,
weight of 600 lb.
Read (Read/Compare) Shutdown Delay 3.6 msec.
Write Shutdown Delay - approximately
4.5 msec.
MAGNETIC TAPE TRANSPORT, TYPE TU20A
(9-CHANNEL)
The Type TU20A is a digital magnetic tape transport designed to be compatible with the Type

TC59 Magnetic Tape Control. The transport operates at a speed of 45 in./sec and has three selectable densities: 200, 556, and 800 bpi. The maximum transfer rate is 36,000 eight-bit characters
per second. Standard nine-channel IBM-compatible tape format is used. The specifications for
the unit are as follows.

Format· NRZI. Eight data bits plus one parity
bit. End and loadpoint sensing compatible
with IBM.
Tape - Width of 0.5 in. Length of 2400 ft.,
(1.5 mil.). Reels are 10.5 in., IBM-compatible,
with file protect (write lock) ring.

Heads - Write-read gap of 0.150 in. Dynamic
and static skew is less than 14 microseconds.
Tape Specifications - 45 ips speed. Start time
is less than 5 msec. Rewind time for 2400 ft.
is less than 5 min. Start distance is 0.080 in.
(+0.035, -0.025 in.). Stop time is less than
1.5 msec. Stop distance is 0.045 in. (±O.O 15
in.).

Density - 200, 556, and 800 bpi.
transfer rate is 36 kHz.

Maximum

Transport Mechanism - Pinch roller drive;
vacuum column tension.
Controls - ON/OFF, ON LINE, OFF LINE,
FORWARD, REVERSE, REWIND. LOAD,
RESET.
Physical Specifications - Width of 22-1/4 in.,
depth of 27-1/6 in., height of 69-1/8 in.,
weight of 600 lb.
Read (Read/Compare) Shutdown Delay - 3.6
msec.
Write Shutdown Delay - approximately 4.5 msec.

5-21/5-22 (blank)

CHAPTER 6
ADDRESSING
GENERAL
The PDP-9/L can directly address up to 8192
locations (a location consists of an 18-bit word
register) and indirectly address up to 32,768
locations in system core memory. Locations
are addressed, octally, as 00000 through 77777
with the following allocations per separate memory modules or banks.
Memory bank a Memory bank 1
Memory bank 2
Memory bank 3 -

00000 through 17777
20000 through 37777
40000 through 57777
60000 through 77777

4096 words of bank a are included with the
basic PDP-9/L configuration; other banks are appended with expansion of the system.

tion defined by the operation code field considers the contents of the address field as being the
"effective" address for the instruction. This address specifies a location for direct retrieval, entering, or modification of the contents. For example, the directly addressed instruction
LAC 100

directs the central processor unit (CPU) to load
its accumulator register CAC) with the 18-bit
contents of memory location 100.
The 13-bit address field allows direct addressing
of any location of the 8192-word basic memory
module.
INDIRECT ADDRESSING

PDP-9/L also offers autoindexing and extend
For indirect addressing, the indirect address
mode addressing. Eight explicitly addressed locaindicator
(bit 4) is 1. In this case, the contents
tions (10-17) in the basic memory module proof
the
address
field reflect not the effective
vide efficient indexed addressing of up to 32,768
.
address
but
the
address of the location at which
memory locations. An indirect reference to these
the
effective
address
is expressed. For example,
locations increments the existing contents by one
the
indirectly
addressed
instruction
and takes the. result as the effective address for
the operand. Extend mode addressing, impleLAC I 100
mented by the optional memory extension control,
sets up the required parameters for addressing
(where I is the PDP-9 symbolic representation
across the memory module boundaries of an exfor indirect addressing) directs the CPU to load
panded PDP-9/L system.
the AC, not with the contents of location 100,
but the contents of the location that is addressed
by the contents of location 100. If location 100
DIRECT ADDRESSING
contained 000077, the instruction
The instruction word format for PDP-9/L memory reference instructions includes an operation
code field of four bits, and indirect address indicator field of one bit, and a 13-bit address
field, as shown below.

LAC 100

would cause the quantity 000077 to be loaded
into the AC. The instruction

F or direct addressing, the indirect address indicator (bit 4) is O. In this case, the machine ac-

3
OPERATION CODE

LAC I 100

ADDRESS FIELD

INDIRECT ADDRESS INDICATOR

6-1

however, would not enter 000077 in the AC but
the contents of location 00077 (considering the
address field limitation of 15 bits for addressing
up to 32,768 locations).

refer to PDP-9 instructions of the memory referencing and augmented classes. (Refer to chapter
7, Instructions, for descriptions of their actions.)

Indirect addressing adds one machine cycle to an
instruction's execution time. During this interval,
execution is deferred while the effective address
is established. An instruction can have only one
level of indirect addressing.

Example 1:

Eight locations, 00010 through 00017, of
memory bank 0 serve as auto-index registers.
Indirect addressing of an auto-index register
causes its contents to be automatically incremented by one and then taken as the
effective address for the instruction. Thus,
addressing of sequential men10ry locations
can be easily achieved by loading an autoindex register with the initial address Ininus
one, and then indirectly addressing the autoindex register until the required operation is
completed.
The incrementation of an auto-index register's
contents does not add to the instruction execution time. Autoindexing occurs only upon
an indirect address reference of an auto-index
register. When directly addressed, an autoindex register functions in the same manner as
all other memory locations.

ENTRY,
LOOP,

Contents

0010
0040
100
101

100
050
040
041

The following four instructions to load the
accumulator illustrate, by comparison, direct,
indirect, and autoindexed addressing.
LAC
LAC
LAC

100
100
010

LAC

010

Places the number 40 into the AC.
Places the number 50 into the AC.
Places the number 100 into the
AC.
By autoindexing, the contents of
location 10 become 101, then
the number 41 is placed into the
AC.

Autoindexing can be used to process a block
of nUlllbers without the need for address arithmetic. The following three examples demonstrate
typical programming techniques (the mnemonics
6-2

FIRST -1

/FIRST WORD'S LOCATIOI\! -1

-N + 1

/NUMBER OF ITERATIONS
/(2s COMPLEMENT)
/CLEAR AC AND LINK
/PARTIAL SUM
/TEST FOR COMPLETION
IMORE IN TABLE, GO BACK
/SUM 11\1 AC

CLA!CLL
ADD I 10
IS2 COUNT
JMP LOOP
HALT

Example 2:

Ci = Ai + Bi; i = 1, 2, ... N

Three autoindexing locations are used to simplify
the addressing.

10/

L(A) -1

11/

L(B) -1

121

L(C) -1

100/
COUNT,

-N + 1

BEGIN,
LOOP,

Assume that four memory locations are
initialized as follows:
Location

2: Xi
i=1

10/
100/
COUNT,

AUTOINDEXING

Sum of a series of numbers;

CLA!CLL
LAC I 10
ADD I 11
DAC I 12
IS2 COUNT
JMP LOOP

I(THE FIRST LOCATION
IOF THE A ARRAYl-1
/(THE FIRST LOCATION
/OF THE B ARRAY)-1
I(THE FI RST LOCATION
IOF THE C AR RA Y)-1
I(NUMBER OF ITERAITIONS (2s COMPLE··
IMENT)
ICLEAR AC AND LINK
/GET ADDEND
IFORM SUM
ISTORE SUM
/TEST FOR COMPLETION
IMORE IN TABLE, GO
/BACK

Example 3: Cj = Cj + K; j = 1, 2, ... N
This example demonstrates the modification of a
list of numbers by adding a constant to each of
them. In this case, the autoindexing memory
register contains an instruction rather than just
an address.
10/

DAC FIRST -1 /DEPOSIT INTO (FIRST LOCATION
liN TABLE) -1

1001
COUNT,

-N + 1

CONST/,K
GO,
LOOP,

CLA!CLL
LAC I 10
ADD CONST
XCT 10
IS2 COUNT
JMP LOOP
HALT

ITWOS COMPLEMENT OF NUMBER
IOF WORDS IN TABLE
/THE CONSTANT
ICLEAR AC AND LINK
IPICK UP INITIAL VALUE: FROM
/TABLE
/ADD CONSTANT
/REPLACE IN TABLE
/TEST FOR COMPLETION
/MORE IN TABLE, GO BJ\CK

All indirectly addressed reference to locations
10-17 refer to the absolute locations of memory
bank 0, regardless of the memory bank location
of the instruction making the reference or the
condition of the extend mode. A directly
addressed reference to one of these locations
refers to the absolute location, only if the
instruction making the reference is also present
in a location of memory bank O. If the instruction is located in any bank other than Inemory
bank 0, the direct reference is made to the
relative location of that memory bank. Thus,
the use of the instruction
DAC 10

to load auto-index register 10 with a specified
contents for indexing purposes would be effective only if the loading instruction is in memory
bank 0 after the program was loaded. Users
instead are advised to adhere to the following
procedure for loading auto-index registers from
any memory bank other than O. The extend
mode must be enabled.
DAC I A

A,10

This indirect loading sequence accomplishes the
loading regardless of the memory bank storage
of the DAC I A instruction.
EXTEND MODE ADDRESSING
Addition of the optional memory extension control, Type KG09 A, required for expansion of
PDP-9/L core memory (up to 32,768 words in
banks of 8192 words), implements the extend
mode for addressing any memory location in
the expanded system. The mode is enabled and
disabled by programmed instructions and it can
be entered through use of the EXD switch on
the control console (refer to chapter 10, Controls and Indicators).
The memory extension control adds four instructions to the PDP-9/L order code. (Refer to
table 6-1.)
TABLE 6-1

Execution of the EEM instruction enables the
extend mode, and LEM disables the mode. If
the mode is enabled, execution of the SEM
instruction causes the PC to be incremented by
one to effect a skip of the next instruction in
sequence.
While the extend mode is disabled, all instructions to be executed during this interim, and
their operands, must be stored in the same
memory bank, and this bank will be addressed
by the Extended Program Counter (EPC). The
EPC consists of standard 13-bit PC and the
2-bit extension, added by the option to the
high-order end.
With the exception of the PI and API traps to
bank 0, it is impossible to access any instruction
or operand from other memory banks with the
extend mode disabled. Regardless of the extend
mode status, however, an instruction in another
bank can always indirectly address auto-index
registers (locations 10 through 17) of bank 0
to make use of that facility. When the extend
mode is disabled, the auto-index register is used
as an address pointer to the memory bank from
which the reference was made (i .e., the 2-bit
extension of the PC is unchanged and only 13
bits of address in the auto register are taken).
To load the contents of an auto-index register
from any memory bank except 0, the extend
mode must be enabled.
Program interrupts and API interrupts trap to
their proper locations in bank O. In trapping
to location 00000 of bank 0, a program interrupt
stores the existing status of the extend mode (on
or off) and then disables the mode. Through
use of the DBR (debreak and restore) instruction,
the interrupt-accessed subroutine can restore the
mode to its interrupted state at the end of the
routine. (For a description of the DBR instruction, refer to the API discussion in chapter 9.)
An API request transfers program control to the
appropriate channel entry in memory (always
in bank 0). The instruction present at the channel location should be a JMS I Y, which stores
the EPC and the status of the extend mode.
(The JMS should be indirect to permit reloca-

MEMORY EXTENSION CONTROL INSTRUCTIONS

Mnemonic
Symbol

Octal
Code

SEM
EEM
LEM
ERIR

707701
707702
707704
707742

Operation
Skip next instruction if extend mode is active
Enter extend mode
Leave extend mode
Enter extend mode interrupt restore

6-3

tion to any bank.) The mode status is not disturbed.

the use of an instruction word (such as LAW Y)
as an indirect address when the extend mode is
enabled.

While the extend mode is enabled (the normal
state), any location in the memory system may
be indirectly addressed through extension of the
effective address from the normal 13 bits (bits
5 through 17) to 15 bits (bits 3 through 17).
Bits 3 and 4 indicate the memory bank that is
to be addressed, and bits 5 through 17 address
a location in that bank. The PC extension
indicates by its contents which of the memory
banks is currently addressed by the PC. Because
the extension cannot count, the PC functions
as a modulo 8192 counter and therefore does
not increment across memory bank boundaries
(e.g., the location addressed after 17777 is
00000, not 20000). To effect a change in
memory banks, the program must include a jump
instruction with indirect address (JMP I Y, or
JMS I Y if the exit point is to be preserved
for subsequent return). Execution of this instruction enters a l5-bit address in the extended program counter to select a new memory
bank and the starting location in this bank.

Note that execution of a CAL instruction results
in the addressing of location 20 of memory bank
0, when the extend mode is enabled; and
location 20 (relative) of the currently addressed
memory bank, when the extend mode is disabled.

When extend mode is enabled an effective
address for an indirectly addressed location must
be a I5-bit address. This requirement prohibits
TABLE 6-2

XCT instruction always function as if the referenced instructions were fetched. Thus, XCT I
reference of a skip instruction in another memory
bank effects a skip of the instruction immediately
following the XCT I instruction, if the skipping
condition is satisfied (i.e., the EPC is incremented
by one). Similarly, XCT I reference of a JMS or
CAL instruction in another memory bank effects
the appropriate storing of the EPC contents, which
in turn represent the address of the location following the XCT I instructions and not the location
following the referenced instruction.
RESERVED ADDRESSES
Programs prepared for the PDP-9/L should not
make use of locations addressed 00000 through
00077 for data or instruction storage as they
are reserved for the pusposes listed in table 6-2.

RESERVED ADDRESSES

Address

Purpose

Stores the contents of the extended PC, link, extend
mode status, and memory protection status during
a program interrupt.
Stores the first instruction to be executed following a
program interrupt.

2-6

Reserved for PDP-9 system programs.

Stores real-time clock count.

10-17

Autoindex registers.

Stores the contents of the extended PC, link, extend
mode status, and memory protection status upon
execution of a CAL instruction.

Stores the first instruction to be executed following a"
CAL instruction.

22-27

Reserved for PDP-9 system programs.

30-37

Four pairs of word counter-current address registers for
use with data channels 0, 1, 2, and 3.

40-77

Store unique entry instructions for each 3210 automatic
priority interrupt channels.

,------------------------.------------------------------------6-4

CHAPTER 7
INSTRUCTIONS
GENERAL

dressing is indicated, the addressed memory
location is taken to contain the required operand.
If indirect addressing is called for, the contents
of the addressed memory location are taken not
as the operand but the address at which the
operand is located. In either case, the address
specifying the memory location that contains
the operand is taken as the "effective address"
for the instruction.

The PDP-9/L instruction set is subdivided into
two groups: those which address system core
memory and those which do not. An instruction of the former group addresses, either
directly or indirectly, a location in memory for
the purpose of retrieving, entering, or modifying
the contents. These instructions are known as
"memory referencing" instructions. The instructions which do not address memory are known
as "augmented" instructions in that the entire
18-bit instruction word serves as an expanded
operation code to specify a specific action or
actions to be executed. The augmented instruction group has three subclasses: operate (which
provides for skip, rotate, clear, complement,
etc. operations involving the accumulator and/or
the link register); lOT (input/output transfer
of data, status, and command information between the central processor and peripheral devices); and E;AE (optional extended arithmetic
element implementation of hardware multiply,
divide, shift, normalize, etc.).

AUGMENTED INSTRUCTION FORMAT
The augmented instruction word (figure 7-2) has
two parts: an operation code and an instruction
code. The operation code, bits 0 through 3,
denotes the type of instruction specified by the
instruction code. Operation codes for the three
types are: 70 8 for input/output transfer (lOT),
748 for operate, and 648 for the optional
extend arithmetic element (EAE). The instruction code, bits 4 through 17, specifies the
action to be executed. An important and useful feature of the PDP-9/L augmented instruction is its microprogramming capability. Multiple instruction codes having the same operation
code can be combined to form one instruction
word. Execution of all the microprogrammed
functions occurs during the time allocated to the
type of instruction (operate instructions require
one machine cycle, lOTs require four cycles,
and EAEs require two cycles plus a variable
time interval to complete their functions). Thus,
microprogramming decreases program running
time, lessens the number of instruction words
required, and simplifies programming efforts.

MEMORY REFERENCE INSTRUCTION FORMAT
The memory reference instruction word (figure
7-1) consists of three parts: operation code,
indirect address bit, and address. The operation
code, bits 0 through 3, indicates which one of
PDP-9/L's 13 memory reference instructions is
specified. The indirect address bit indicates
whether the 13-bit address (bits 5 through 17)
is to be taken as the direct address (bit 4 is 0)
or indirect address (bit 4 is 1). If direct ad-

OPERATION
CODE=OOe - 60e

ADDRESS

13 114115

INDIRECT
ADDRESS FLAG
(I-INDIRECT)

Figure 7-1.

Memory Reference Instruction Format
7-1

OPERATION CODE:
648 = EAE

70 8 '! lOT
~

748 = OPERATE
____~A~______~\

12 13 114115 16117]

~~--------------.------------~y~----------------------------/
INSTRUCTION CODE

Figure 7-2.

Augmented Instruction Format

MEMORY REFERENCE INSTRUCTIONS
The following information applies to each memory reference instruction;
1. Instruction time is expressed in machine cycle units, where one cycle equals
1.0 microsecond.

2. An instruction with indirect addressing
(bit 4 is 1) requires one additional machine
cycle. PDP-9/L memory referencing instructions can take only one level of indirect addressing; i.e., the indirectly addressed memory location must contain the address of
the operand.
3. The term "effective address" applies to
the address that specifies the memory location containing the operand for the instruction.
4. Numerical memory location addresses
are ex pressed octally.
5. Subscript notations identify specific bit
positions of the respectively identified register or location. Numerical subscripts are expressed decimally.
6. Except for the CAL instruction, all
memory referencing instructions must include
the address (direct or indirect) of an operand. The CAL instruction takes the hardware-fixed address of 20; it ignores the address field in the instruction word.
7. In the symbolic representations for the
JMP, JMS, and CAL instructions, the quotation Inarks enclosing "Y" or "21" for
CAL, indicate that Y, or 21, rather than
their contents, enters the PC, as shown.
Mnemonic: LAC (Load the Accumulator)
Octal Code: 20
7-2

Time: 2 cycles
Operation: The contents of the effectively addressed memory register, Y, are read into the AC.
The contents of Yare unchanged; the previous
contents of the AC are lost.
Symbolic: Y
AC
Mnemonic: DAC (Deposit the Accumulator)
Octal Code: 04
Time: 2 cycles
Operation: The contents of the AC are deposited (written) into the effectively addressed memory register, Y. The contents of the AC are unchanged; the previous contents of Yare lost.
Symbolic: AC
• Y
Mnemonic: DZM (Deposit Zero in Memory)
Octal Code: 14
Time: 2 cycles
Operation: An all-zeros data word is deposited
(written) in the effectively addressed mernory
register, Y. The previous contents of Yare
lost; the contents of the AC are unchanged.
Symbolic: 0
•Y
Mnemonic: ADD (Add, 1s Complement)
Octal Code: 30
Time: 2 cycles
Operation: The contents of the effectively
addressed memory register, Y, are added to the
contents of the AC, following the rules of 1s
complement arithmetic (end around carry) *.
The result is left in the AC. An arithmetic overflow sets the link to the binary 1 state. The
contents of Yare unchanged; the previous
contents of the AC are lost. The previous content of the link is lost. Overflow occurs if the
magnitude (absolute) of the algebraic sum of
the operands exceeds 217-1; i.e., if the operands
were of like sign and the result is signed differently, overflow has occured to set the link.
Overflow cannot occur if the operands are of
different sign.
Symbolic: Y + AC
AC

• L

LV Overflow

Mnemonic: TAD (Add, 2s Complement)
Octal Code: 34
Time: 2 cycles
Operation: The contents of the effectively addressed memory register, Y, are added to the
contents of the AC, following the rules of 2s
complement arithmetic*. The result is left in
the AC. An arithmetic carry from AC o complements the link. The contents of Yare unchanged; the previous contents of the AC are
lost.
• (L,AC)
Symbolic: Y + (L,AC)
Mnemonic: AND (Boolean AND)
Octal Code: 50
Time: 2 cycles
Operation: The contents of the effectively addressed memory register, Y, are logically ANDed
with the contents of the AC on a bit-by-bit
basis. The result is left in the AC. If corresponding Y and AC bits (i) are in the 1 state,
the AC bit remains a 1; otherwise the AC bit
is cleared to the 0 state. The contents of Y
are unchanged; the previous contents of the AC
are lost.
Symbolic: Y 1\ AC
• AC
ACi
AND

o
1

o
o

o
1

Mnemonic: XOR (Boolean Exclusive OR)
Octal Code: 24
Time: 2 cycles
Operation: The contents of the eff~ctively addressed memory register, Y, are exclusively ORed
with the contents of the AC on a bit-by-bit basis. The result is left in the AC. If corresponding
Yand AC bits (i) are in the same binary state
(i.e., 1 or 0), the AC bit is cleared to the 0 state.
If the corresponding bits are not in the same
binary state, the AC bit is set to the 1 state. The
contents of Yare unchanged; the previous contents of the AC are lost.
Symbolic: Y V- AC
AC
ACi
Exclusive OR
0

0
0
1

1
1
0

Mnemonic: SAD (Skip if AC Differs)
Octal Code: 54
Time: 2 cycles
Operation: The contents of the effectively addressed memory register, Y, are compared with
the contents of the AC. If they differ, the PC
is incremented by one to effect skipping the
next instruction. If they have the same binary
quantity, the next instruction is executed. The
contents of Y and the contents of the AC are
unchanged.
Symbolic: If Y t= AC, PC + 1
• PC
Mnemonic: ISZ (Increment and Skip if Zero)
Octal Code: 44
Time: 2 cycles
Operation: The contents of the effectively addressed memory register, Y, are incremented by
one (in 2s complement arithmetic) and tested.
If Y now contains an all-zero word, the PC is
incremented by one to effect skipping the next
instruction. If the contents of Y, after being
incremented, are other than all zeros, the next
instruction is executed. The previous contents
of Yare lost; the contents of the AC are unchanged.
.. PC
Symbolic: If Y + 1 = 0, PC +
Y+ 1
.Y.
Mnemonic: JMP (Unconditional Jump)
Octal Code: 60
Time: 1 cycle
Operation: The next instruction is read from the
contents of the effectively addressed memory
register, Y, thereby breaking the existing program sequence and starting a new sequence from
Y. The previous contents of the PC are lost
when the effective address enters the PC. The
contents of the AC are unchanged.
Symbolic: "Y" (bits 5-17)
• PC
Mnemonic: JMS (Jump to Subroutine)
Octal Code: 10
Time: 2 cycles
Operation: The contents of the PC and of the
link, and the status (on or off) of the extend
mode and of the memory protect mode are
deposited in the effectively addressed memory
register, Y. The next instruction is read from
the contents of memory register Y + 1, breaking the previous program sequence and starting
a new sequence from Y + 1. The contents of
the AC are unchanged.
Symbolic:

*Refer to chapter 8 for discussion of 1sand
2s complement notations and arithmetic.

L-~.~Yo

EM
"-Y 1
MP
.. Y 2
PC
• Y 3-17
"Y" + 1 (bits 5-17)l--~. PC
7-3

the microinstructions associated with each (the
Mnemonic: CAL (Call Uump to) Subroutine)
Octal Code: 00
instructions are indicated by their mnemonics).
Time: 2 cycles
The nature of rotate operations precludes the
Operation: The CAL instruction is the equivalent
microprogramming of other microinstructions durof a JMS 20 instruction. The contents of the PC
and of the link, and the status (on or off) of the
ing the same event times.
extend memory mode and of the memory protect
mode are deposited in memory register 20. The
When noninverted skip actions are Inicropronext instruction is read from the contents of mem- grammed (bit 8 is 0), the conditions to be met
are inclusively ORed. For example: if SZA
ory register 21, breaking the previous program
(741200) and SZL (741400) are specified in a
sequence and starting a new sequence from 21.
The contents of the AC are unchanged. If the
microprogrammed instruction (741600), the skip
API option is present and enabled, priority level
occurs only if both conditions are present (the
contents of the AC are other than 0, the con4 will be activated after the execution of a CAL
instruction.
tent of the link is 0).
Symbolic: L--~"200
EM
• 201
Mnemonic: NOP (No Operation)
MP
• 20 2
Oct~ Code:
740000
PC
, .. 20 3 -17
Time: 1 cycle
"21 "_.---..
.. PC
Operation: The program is delayed for one cycle
before the next instruction is fetched. As. a "do
Mnemonic: XCT (Execute the Instruction at Y)
nothing" cycle, NOP can be used to synchronize
Octal Code: 40
program timing to peripheral timing by delaying
Time: 1 cycle plus time of instruction at Y
execution of an instruction until the appropriate
Operation: The computer executes the instruction time.
located at the effectively addressed memory reSymbolic: Not applicable
gister, Y. The contents of the PC are unchanged
unless Y contains a JMS, CAL, JMP, or skip inMnemonic: CMA (Complement Accumulator)
struction, each of which changes the contents of
Octal Code: 740001
the PC to alter the program sequence. (XCT can
Time: 1 cycle
be thought of as a single-instruction subroutine
Operation: Each bit of the AC is set or cleared
causing a quasi-jump to Y, execution of the into the inverse of its current state. The previous
struction specified there, and return to the procontents of the AC are lost.
gram sequence (i.e., execution of the instruction
.. AC
Symbolic: AC
following XCT) if the instruction at Y has not
changed the PC.)
Mnemonic: CML (Complement Link)
Symbolic: Y
.. IR
Octal Code: 740002
Time: 1 cycle
OPERATE INSTRUCTIONS
Operation: The link is set or cleared to the inof its current state. Its previous content
verse
Operate instructions have an operation code of
is
lost.
748 and are used to sense and alter the contents
•L
Symbolic: L
of the AC and link. Typical functions are: conditional or unconditional skips and complementing,
setting, clearing, or rotating the contents of the
two registers jointly or independently. A HLT
Mnemonic: OAS (Inclusive OR ACCUMULATOR
instruction is included. Operate instructions are
Switches)
fetched and executed in one machine cycle; the
Octal Code: 740004
actions are specified by the microprogran1ming of
Time: I cycle
the instruction code. Each of the 14 bits (figure
Operation: The word set up by manual position7-2) can effect a unique response; hence, these
ing of the ACCUMULATOR switches is inclusivebits are microinstructions to the computer. The
ly ORed with the contents of the AC on a bitimportant feature of the operate instruction is
by-bit basis. The result is left in the AC. If
its microprogramming capability because two or
corresponding AC and AC switch bits (i) are in
three microinstructions can be combined to form
the binary 0 state, the AC bit remains O. If
one instruction word and, therefore, they can be
either or both of the corresponding bits (i) are
executed during one cycle. Microinstructions
in the binary 1 state, the AC bit is set to 1.
that logically conflict and occur during the same
The previous contents of the AC are lost. The
event time should not be microprogrammed.
switch settings are not affected.
Figure 7-3 lists the sequential event times and
• AC
Symbolic: AC V AC Switch

7-4

Operation Code = 748
CLA

CLL

Additional
Rotate

o = OR of
1 = AND of

SNL
SZL

SZA
SNA

SMA
SPA

HLT

0-2

3-5

6-8 9-11 L2-14 15-17

OPR}
NOP

CMA

CML

OAS

RAL

RAR

*HLT} 7
*xx

SMA

SZA

SNL}
SML

SKP

SPA

SNA

SZL}
SPL

RTL

RTR

CLL

(CLL-CML)

STL}
CCL

(CLL-RAL)

RCL

(CLL-RAR)

RCR

(CLA-CMA)

Bit 7 = 0
RAR RAL
RTR RTL
Bit 7 = 1
13 14

OAS

CML

CMA

Event
Time

0
3

No other operation

may take place at

the same event time

as rotates.

RAR, RAL may not be

combined with:

RTR, RTL may not be

combined with:

CLA, CLL, OAS,
CML, CMA.

OAS, CML, CMA

2,3

2,4

9/L Symbolic Assembler accepts

CLA
CLC

7
7

5
5

0
0

2
2,3

(CLA-OAS)

LAS}
LAT

2,5

(CLA-RAL)

GLK

2,4

either HLT or XX as a valid
mnemonic for the operate class
instruction to stop program execution. The latter facilitates
visual scanning of a program
listing to determine the occurrence of program halts.

Figure 7-3

*Programming Note:

The PDP-

Operate Instructions

7-5

Inclusive OR

ACSi

Mnemonic: RAL (Rotate AC and Link Left)
Octal Code: 740010
Time: 1 cycle
Operation: The contents of the AC and the link
are rotated one bit position to the left with AC o
entering the link and the link entering AC 17 .
Symbolic: ACi
• ACi-l· i = 1, 17
• L
'
AC o
L
.......AC 17

Mnemonic: RAR (Rotate AC and Link Right)
Octal Code: 740020
Time: I cycle
Operation: The contents ot the AC and the link
are rotated one bit position to the right with
AC 17 entering the link and the link entering ACo
Symbolic: ACi
• ACi + 1; i = 0, 16
AC 17
• L
L
.... AC o

Mnemonic:

HLT (Halt Program) (see programming footnote, figure 7-3)
Octal Code: 740040
Time: 1 cycle
Operation: Program execution stops at completion of the current machine cycle. The PGRM
STOP indicator is lighted.
Symbolic: 0
• RUN flip-flop
Mnemonic: SMA (Skip on Minus Accumulator)
Octal Code: 740 I 00
Time: I cycle
Operation: Test the contents of the sign bit,
AC o , of the data word in the AC. If the bit is
in the I state, the contents of the PC are incremented by one to effect skipping the next instruction. If ACo is in the 0 state, the next: instruction is executed. The contents of the AC
are unchanged.
Symbolic: If AC o = I, PC + 1
., PC
Mnemonic: SZA (Skip on Zero Accumulator)
Oct~ Code:
740200
Time: I cycle
Operation: Test the contents of the word in
the AC. If all bits are Os, the quantity is taken
to be zero (2s complement notation), and the
contents of the PC are incremented by one to
effect skipping the next instruction. If any

7-6

bit is in the 1 state, the next instruction is executed. The contents of the AC are unchanged.
Symbolic: If AC = 0, PC + 1
., PC
Mnemonic: SNL (Skip on Non-zero Link)
Oct~ Code:
740400
Time: I cycle
Operation: Test the content of the link. If the
link is in the I state, the contents of the PC
are incremented by one to effect skipping the
next instruction. If the link is a 0, the next instruction is executed. The content of the link
is unchanged.
• PC
Symbolic: If L = I, PC + I
Mnemonic: SKP (Unconditional Skip)
Octal Code: 741000
Time: I cycle
Operation: The contents of the PC are incremented by one to effect an unconditional skip of the
next instruction.
Symbolic: PC + I
• PC
Mnemonic: SPA (Skip on Positive Accumulator)
Octal Code: 741100
Time: I cycle
Operation: Test the contents of the sign bit,
AC 0' for a data word in the AC. If the bit is
in the 0 state, the quantity in the AC is taken
to be positive. Therefore, the contents of the
PC are incremented by one to effect skipping
the next instruction. If the bit is in the 1 state,
the next instruction is executed. The contents
of the AC are unchanged.
Symbolic: If ACo = 0, PC + I
.... PC
Mnemonic: SNA (Skip on Non-zero, Accumulator)
Octal Code: 741200
Time: I cycle
Operation: Test the contents of the data word
in the AC. If any bit is in the 1 state, the quantity is not equal to zero (2s complement notation
only), and the contents of the PC are incremented
by one to effect skipping of the next instruction.
If all bits are in the 0 state, the quantity is zero
and the next instruction is executed. The contents of the AC are unchanged.
Symbolic: If AC t= 0, PC + 1
.. PC
Mnemonic: SZL (Skip on Zero Link)
Octal Code: 741400
Time: I cycle
Operation: Test the contents of the link. If
the link is in the 0 state, the contents of the
PC are incremented by one to effect skipping
the next instruction. If the link is aI, the next
instruction is executed. The content of the link
is unchanged.
Symbolic: If L = 0, PC + I
., PC

Mnemonic: RTL (Rotate AC and Link Two Left)
Octal Code: 742010
Time: 1 cycle
Operation: The contents of the AC and the link
are rotated two bit positions to the left with AC o
entering AC 17' AC 1 entering the link, and the link
entering AC 16 .
Symbolic: ACi-~.~ACi-2· i = 2, 17
L
• AC 16 '
AC o
• AC 17
AC 1
• L
Mnemonic:

RTR (Rotate AC and Link Two
Right)
Octal Code: 742020
Time: 1 cycle
Operation: The contents of the AC and the
link are rotated two bit positions to the right
with the link entering AC 1, AC 17 entering ACo,
and AC 16 entering the link.

Mnemonic: CLL (Clear the Link)
Octal Code: 744000
Time: 1 cycle
Operation: The content of the link is cleared to
the 0 state.
•L
Symbolic: 0
Mnemonic: STL (Set the Link)
Octal Code: 744002
Time: 1 cycle
Operation: A microcoded instruction equivalent
to CLL+CML. The link is first cleared to binary
0; it is then complemented to binary 1.
Symbolic: 1
•L
Mnemonic:

RCL (Clear Link, Then Rotate AC
and L Left)
Octal Code: 744010
Time: 1 cycle
Operation: A microcoded instruction equivalent
to CLL+RAL. The link is first cleared to 0;
then the contents of the AC and the link are
rotated one bit position to the left.
' ACi-1' i= 1, 17
Symbolic: ACi
AC o
•L
'
o
• AC 17
Mnemonic:

RCR (Clear Link, Then Rotate AC
and L Right)
Oct~ Code: 744020
Time: 1 cycle
Operation: A microcoded instruction equivalent
to CLL+RAR. The link is first cleared to 0;
then the contents of the AC and the link are rotated one bit position to the right.
Symbolic: ACi
• ACi+ 1; i=O, 16
AC17~L

.AC o

Mnemonic: CLA (Clear the Accumulator)
Oct~ Code:
750000
Time: 1 cycle
Operation: Each bit of the AC is cleared to O.
The previous contents are lost.
Symbolic: 0
, AC
Mnemonic:

CLC (Clear and Complement Accumulator)
Octal Code: 750001
Time: 1 cycle
Operation: A microcoded instruction equivalent
to CLL+CMA. Each bit of the AC is cleared to
O. Then each bit is set to 1. The previous contents of the AC are lost.
• AC
Symbolic: 777777
Mnemonic:

LAS (Load AC from ACCUMULATOR Switches)
Octal Code: 750004
Time: 1 cycle
Operation: A microcoded instruction equivalent to CLA+OAS. Each bit of the AC is cleared to O. Then the word set up by manual positioning of the ACCUMULATOR switches is
entered in the AC. The previous contents of the
the AC are lost. The switch settings are not
affected.
Symbolic: ACS
• AC
Mnemonic: GLK (Get the Link)
Octal Code: 750010
Time: 1 cycle
Operation: A microcoded instruction equivalent to CLA+RAL. Each bit of the AC is
cleared to O. Then the contents of the AC and
the link are rotated one bit position left with
the link contents entering AC 17' The previous
contents of the AC are lost.
Symbolic:. L
• AC 17
o
, AC 0-16

•L

Mnemonic: LAW (Load AC with "n")
Octal Code: 7 60000 + n
Time: 1 cycle
Operation: A single-cycle instruction that loads
itself into the AC for the purpose of generating
a number, n, of the range 0 ~ n ~ 17777 8 ,
Following the fetch, the computer enters the
contents of the MB (the LAW instruction word)
in the AC. The previous contents of the AC
are lost. (Refer to figure 7-4.)
• AC
Symbolic: MB
Some applications of the LAW instruction are:
1. Loading an address for use in establishing
indirect operand addressing (if extend mode
off).
7-7

Figure 7-4 LA W Instruction
2. Loading alphanumeric character codes in
the AC for use with peripherals.
3. Initializing word counters and/or current
address registers.
4.

Presetting the real-time clock counter.

Although the entire LAW instruction word is contained in the AC, only bits 5 through 17 can be
employed to formulate the required quantity.
Bits
through 4 serve as the operation code of
the instruction.

PROGRAMMING NOTE: The PDP-9/L Symbolic Assembler includes in its permanent symbol
table the code for the mnemonic LAM (load
minus 177777 8 . To generate a negative (1 s
complement) number in the AC, the user need
only program a LAM-n instruction. After execution of the instruction, the quantity, n, will
be present in 1s complement form in the AC.
INPUT/OUTPUT TRANSFER INSTRUCTIONS
Input/Output transfer (lOT) instructions initiate
transmission of signals via the I/O bus to control peripheral devices, sense their status, and
effect information transfers between thenl and
the processor. A PDP-9/L lOT instruction contains the following information (figure 7-5):
1. An operation code of 708.
2. An 8-bit device selection code to discriutinate one of 256 peripheral devices
(selection logic in the I/O bus of a device
interface responds only to its preassigned
code). In normal practice, bits 6 through
11 perform the primary device discrimination
among up to 64 devices with bits 12 and 13
coded to select an operational mode or subdevice.
7-8

3. A command code (bits 14 through 17)
capable of being microprogrammed to clear
the AC and issue up to three pulses via the
I/O bus.
The four machine cycles required to execute an
lOT instruction consist of the lOT fetch from
core memory (memory is not accessed thereafter
until completion of the lOT), and there sequential cycles of 1.0 microseconds duration each,
designated event times 1, 2, and 3 (figure 7-6),
Bits 14 and 17 can be coded to initiate clearing
of the AC and generation of an lOP 1 pulse for
testing a device status flag. IOP2 pulses are normally used to effect programmed transfers of
information from a device to the processor. Because the AC serves as the data register for both
"in" and "out" transfers, the "clear AC" microinstruction (bit 4) is usually microprogrammed
with the IOP2 microinstruction; this combination
effects clearing the AC during event time 1 prior
to the IOP2 strobe of information into the AC
during event time 2. IOP4 pulses are normally
used to effect programmed transfers of information from the AC to a selected device.
These conventions do not, however, preclude
use of the lOP pulses to effect other external
functions if the following restrictions are observed.
The usual use of lOPs is:
lOP 1 - normally used in an I/O skip instruction
to test a device flag. May be used as
a command pulse but not to initiate
either a "load of' or a "read from" dea device.
IOP2 - usually used to transfer data from the device to the computer, or to clear a device's information register. May not be
used to determine a "skip" condition.
IOP4 - usually used to transfer data from the
computer to the device. May not be
used to determine a "skip" condition.

OPERATION
CODE 70

CLEAR AC
AT EVENT
TIME 1

DEVICE
SELECTION

UNUSED

L.-y----J

'----y--J

GENERATE
AN lOP 4
PULSE AT
EVENT TIME
3

GENERATE
AN IOP 1
PULSE AT
EVENT TIME
1

lOT Instruction Format

EVENT TIME 2

EVENT TIME f

EVENT TIME 3

NEXT
FETCH

~**
~

,----'----,

131141151161171

SUB-DEVICE
SELECTION

Figure 7-5

FETCH

GENERATE
AN lOP 2
PULSE AT EVENT
TIME 2

IOPI

~**

r--

'V1.5.ilSEC

1.5 .ilSEC

IOP2

.+.

*NOMINAL PULSE WIDTH
**LEADING EDGE UNCERTAIN TO O.15JlSEC

Figure 7-6 lOT Instruction Timing
7-9

Programming Note:
Execution of an lOT instruction and the next instruction in sequence cannot be interrupted; i.e.,
the PDP-9/L will not grant an interrupt request
until the instruction following an lOT (and which
is not an lOT itself) has completed its function.
Clear All Flags
This lOT (703302) is implemented on all
PDP-9/L's. Its purpose is to clear the flags of
any device that can call for I/O interrupt service.
When the CAF instruction is issued, a pulse goes
out on the I/O PWR CLR line of the I/O bus.
Customer-installed equipment should also make
use of this pulse for flags and registers which
should be cleared for system initiation. (This
pulse is also issued at power-on time and when the
I/O RESET key is depressed.)
EAE lNSTRUCTIONS
The extended arithmetic element option adds
the hardware necessary to implement the EAE
instructions. This class of instructions, identified
by an operation code of 64 8 , performs highspeed data manipulation and multiply-divide
operations as specified by microprogramming of
individual instructions. Figure 7-7 illustrates the
microinstruction capabilities for, respectively,
register setup, data shift, normalize, multiply,
and divide.
The time required to execute an EAE instruction
is a function of the operation and/or the shift.
or step, count specified by microprogramming
(see table 7-2). In general, the following considerations apply to the different types of EAE
operations.
1. All set-up instructions require two machine cycles (3.0 microseconds).
2. Long register shift instructions require a
time equal to 2.5 microseconds plus 0.4 microseconds per "n" bit-position shifts, quantized
up to next whole time integer. This count is
specified by the addition of n (octal) to the
instruction code. For example: the input
of the symbolic instruction LLS+ 14 to the
PDP-9/L assenlbler would result in an instruction code that specified a long left shift of
the AC and MQ (taken as a 36-bit register)
1210 bit positions to the left. This instruction
would require 8.5 microseconds.

7-10

3. The ASL and ALSS instruction, respectively, AC left shift and AC left shift signed, also require the specification of "n".
4. The normalizing instructions, NORM and
NORMS, require an execution time equal to
2.5 microseconds plus 0.4 microseconds. per
number of bit positions shifted to normalize:
(AC oFAC 1 ) quantity. These instructions are
microprogrammed to set the six-bit step count
to 448 (36 10 ), Hence, -44+n8 (the step count
is entered in 2s complement notation at execution) equals the biased scale factor of a
normalized quantity.
5. Multiply instructions are microprogramrrled
to set the step count to 22 8( 18 10 ), representing the multiplication of one 18-bit quantity
(sign bit and 17 magnitude bits for signed
quantities) by another to produce a 36-bit
product. The execution time is 12.0 micro-·
seconds. Where such precision is not required,
the microprogrammed step count can be decreased by subtracting the appropriate number
"n" (octal) from the instruction code. The
product is always left justified in the AC, IVIQ.
If "-n" is appended to a multiply instruction,
the "n" low order bits in the long register
are meaningless.
6. Divide instructions are microprogrammed
to set the step count to 23 8(19 10 ), representing division of a 36-bit dividend (actual or
implied) by an 18-bit divisor. The execution
time is 13.0 microseconds. Where such precision is not required, the microprogrammed
step count can be decreased by subtracting
the appropriate number "n" (octal frolm the
instruction code. For example, the symbolic
instruction DIV-12 would result in a rightjustified quotient with the most significant
bit in MQg. The execution time is decreased
in correspondence to the decrease in the step
count.
Figure 7-8 and table 7-2, which follow the discussions describing the EAE instructions, illlustrate the microinstructions of the EAE instructions. Should an existing instruction not suffice,
the programmer may combine the appropriate
nlicroinstructions to achieve the required result.

EAE SETUP
Mnemonic: OSC (Inclusive OR SC with AC)
Octal Code: 640001
Time: 3 microseconds

OPERATION CODE 64
SPEC I FYI NG EAE

CLEARS MQ
AT EVENT
TIME 1

CLEARS AC
AT EVENT
TIME 2

,--A--.,

I 5 16

LOADS THE AC
WITH THE OR
OF THE AC
ANDTHE MQ AT
EVENT TIME 3

UNUSED IN
SET UP

13 1141151161171

'--r-'
SH I FTS
ACOINTO
L AT EVENT
TIME 1

EAE COMMAND 08
FOR SET UP

COMPLEMENTS
THE MQ
AT EVENT
TIME 3

LOADS
THE AC
WITH THE
OR OF THE
CONTENT OF
THE AC AND
THE SC AT
EVENT TIME

3
LOADS THE MQ WITH THE
OR OF THE CONTENT OF
THE AC AND THE MQ AT
EVENT TIME 2

WHEN BIT 6 IS A 1 AND BIT 7 IS A 0
THE NUMBER IN THE AC IS CHANGED
TO ITS ABSOLUTE VALUE.

SHIFTS ACO INTO EAE AC
- - - SIGN FLIP-FLOP AT EVENT
TIME 1

a. EAE Setup Microinstructions
MAY BE USED
IN MICROPROGRAMMING
SAME FUNCTIONS AS FOR
SET UP INSTRUCTIONS

OPERATION
CODE 64
SPECIFYING EAE

STEP COUNTER PRE-SETTING
(SET TO THE NUMBER OF
BINARY POSITIONS TO BE SHIFTED)

'--y---J

SHIFTS
ACO INTO
L AT EVENT
TIME 1 FOR
SIGNED OPERATIONS

EAE COMMAND
58 = LONG RIGHT SHIFT
6 8 = LONG LEFT SHIFT
78= AC LEFT SHIFT

b. EAE Shift Microinstructions

OPERATION
CODE 64
SPECIFYING EAE

------~A~------~

UNUSED WITH
NORMALIZE
COMMANDS

STEP COUNTER PRE -SETTING
(USUALLY 448fOR NORMALIZE)

------~A~------~

'---y---J

SHIFTS
ACO INTO
L AT EVENT
TIME 1 FOR
SIGNED
OPERATIONS

EAE COMMAND
48 FOR NORMALIZE

c. EAE Normalize Microinstructions

Figure 7-7.

EAE Instruction Formats (Sheet 1)
7-11

SHIFTS ACO INTO EAE AC
- - - - - SIGN FLIP-FLOP AT EVENT
TIME'
LOADS THE MQ WITH THE OR
OF THE CONTENT OF THE AC
AND THE MQ AT EVENT TIME
2

OPERATION
CODE 64
SPECIFYING EAE
,_ _ _ _ _ _ _ _

~A~

EAE COMMAND

______

'8 FOR MULTIPLY
_ _ __

r -_ _

'-v----'
BIT 4 IS A
o AND BIT 5

"-v---'

'---v---'

USED WITH
UNUSED
IN DIVIDE
SIGNED
SO THAT
DIVISION
LINK IS
TO SET
NOT DISTURBED THE SIGN
EXCEPT fOR
OF THE
OVERFLOW
DIVIDEND
(ACO) INTO
THE EAE
SIGN FLIP-FLOP

~-----------~~----------~
STEP COUNTER PRE-SETTING
(USUALLY 228 FOR MULTIPLY)

EAE COMMAND

38 FOR DIVIDE
A

1 9

12 11311411511611~~

'---y--/

~-------y---------~

USED WITH
INTEGER
DIVIDE TO
CLEAR THE
AC AT
EVENT
TIME 2

STEP COUNTER PRE-SETTING
(USUALLY 238 FOR DIVIDE)

EAE Division Microinstructions

Figure 7-7.

7-12

12 113 114115116111J

EAE Multiplication Microinstructions

,.-J'--...,

'--y--/

USED WITH
USED WITH
INTE<iER
DIVIDE TO
INTEGER
DIVIDE TO
LOAD THE
CLEAR THE MQ WITH THE
MQ AT EVENT CONTENT OF
THE AC AT
TIME 1
EVENT TIME 2

OPERATION
CODE 64
SPECIFYING EAE

CLEARS AC
AT EVENT
TIME 2

IS A , SO
THAT LINK IS
NOT DISTURBED
AND MQ IS CLEARED
AT EVENT TI ME ,

...JA~

EAE Instruction Formats (Sheet 2)

EAE OPERATION
CODE (64)

IF BIT,'

0
z

EAE COMMAND

\!)

iii

I
I
I
I

w
w
{}

I
I

~---+

~ ~
__IF_BI~'I0t-_~£rl_~_~

I
t- -

-r -

I
:

I
I

SETUP
MULTIPLY
DIVIDE
NORMALIZE
LONG RIGHT
LONG LEFT
AC LEFT

EVENT
TIME'

_____

~ -

::!

..J

000
00'
0'0
0' ,
, 00
'0'
1 10
11'

i ;
~

(If

...I-<l----l_

_+_

____

E~~If~O~Z~~~.

0001

)

--+-----~---.----~

IF BIT"

Figure 7-8

(IF EAE
COMMAND =000)

_-1 _ _ _ .1-___

~
I~

~~
~

~II
~

~y~~~

EVENT
TIME 3

EAE Microinstructions

Operation: The contents of the AC are inclusively
ORed with the 6-bit contents of the step counter
(SC) on a bit-by-bit basis. The result is left in
AC 12-17 . If corresponding SC and AC bits are in
the binary 1 state, the AC bit is set to l. The
previous contents ,of the AC are lost. The contents of the SC are unchanged.
Symb9lic: SC V AC
JI AC
Inclusive OR 0
1
001
ACi
1
1
1
Mnemonic: OMQ (Inclusive OR MQ with AC)
Octal Code: 640002
Time: 3 microseconds
Operation: The contents of the MQ are inclusively ORed with the contents of the AC on a bit-bybit basis. The result is left in the AC. If corresponding MQ and AC bits are in the binary 0 state,
the AC bit is cleared to O. If either of the corresponding bits is in the binary 1 state, the AC bit is
set to 1. The previous contents of the AC are
lost. The contents of the MQ are unchanged.
Symbolic: MQ V AC
JI AC

Mnemonic: CMQ (Complement MQ)
Octal Code: 640004
Time: 3 microseconds
Operation: Each bit of the MQ is set or cleared
to the inverse of its current state. The previous
contents of the MQ are lost.
Symbolic: MQ~ MQ
Mnemonic: LACQ (Load AC from MQ)
Octal Code: 641002
Time: 3 microseconds
Operation: This microcoded instruction clears
each bit of the AC to 0 and then enters the
contents of the MQ in the AC. The previous
contents of the AC are lost. The contents of
the MQ are unchanged.
JI AC
Symbolic: MQ
Mnemonic: LACS (Load AC from SC)
Octal Code: 641001
Time: 3 microseconds
Operation: This microcoded instruction clears
each bit of the AC to 0 and then enters the
contents of the SC in AC 12-17 . The previous
contents of the AC are lost. The contents of
the SC are unchanged
, AC
Symbolic: SC
Mnemonic: CLQ (Clear MQ)
Oct~ Code:
650000
Time: 3 microseconds
Operation: Each bit of the MQ is cleared to O.
7-13

The previous contents of the MQ are lost.
Symbolic: O---+-MQ
Mnemonic:

ABS (Load AC with Absolute Value
to AC)
Oct~ Code: 644000
Time: 3 microseconds
Operation: A microcoded instruction which complements the contents of the AC (I s complement
notation) if the contents of AC o are 1.
Symbolic: If AC o = 1, AC
- AC
Mnemonic: GSM (Get Sign and Magnitude of AC)
Octal Code: 664000
Time: 3 microseconds
Operation: A microcoded instruction which
enters the contents of AC o in the link, and then
complements the contents of the AC (1 s complement notation) if AC o is a 1. The previous
content of the link is lost.
Symbolic: AC o
• L_
If ACo = 1, AC
-AC

Mnemonic: LMQ (Load MQ)
Oct~ Code: 652000
Time: 3 microseconds
Operation: A microcoded instruction which
clears each bit of the MQ to 0 and then enters
the contents of the AC in the MQ. The previous contents of the MQ are lost. The contents of the AC are unchanged.
Symbolic: AC
_ MQ
TABLE 7-1

Mnemonic: EAE+n (Basic EAE Instruction)
Octal Code: 640000
Time: 3 microseconds
Operation: The addition of "n" (octal) to the
mnemonic converts the basic instruction into
a microcoded instruction to acconlplish 3l setup,
shift, or arithmetic operation not already in the
instruction repertoire. Refer to table 7-2 for
descriptions of the functional use of the individual bits of an EAE instruction. The sole
restriction for the development of "n" is that
the microcoded operations must not occur
during the same event time if they logically conflict.
Symbolic: not applicable.
EAE SHIFTING INSTRUCTIONS
Mnemonic: LRS n (Long Right Shift)
Octal Code: (640500)+n
Time: see table
Operation: The AC and the MQ function as a
36-bit register to permit serial shifting of theilr
contents "n" bit positions to the right, "n"
being specified by the contents of the six low
order bits of the instruction word. Shifting
halts when the contents of the step counter,
initialized to the 2s complement of "n", reach
zero. For each shift step:. the contents of A(;7
enter MC20 and the contents shifted out of Mt.217
are lost. The contents of the link, usually
initialized to zero, remains unchanged and enters
ACo at each step to replace the contents of
vacated bits.

EAE OPERATION TIMES

--------------------------------.---------------------------------------------.
Bit Positions
Multiply or

.--..

Shifted

o
1,2,3
4,5,6
7,8,9
10,11,12
13,14,15
16,17,18
19,20,21
22,23,24
25,26,27
28,29,30
31,32,33
34,35,36

Divide, Unsigned
4 microseconds
6 microseconds
7 microseconds
8 microseconds
10 microseconds
11 microseconds
12 microseconds
13 microseconds (divide)

Multiply or
Divide, Signed *

6 microseconds
8 microseconds
9 microseconds
10 microseconds
12 microseconds
13 microseconds
14 microseconds
15 microseconds (divide)

All Shifts or
Normalize'

2.5 microseconds
4.5 microseconds
5.5 microseconds
6.5 microseconds
8.5 microseconds
9.5 microseconds
10.5 microseconds
11.5 microseconds
12.5 microseconds
14.5 microseconds
15.5 microseconds
16.5 microseconds
17.5 microseconds

,---------------------------------------------.--------------------------------------------------------------------*Signed multiply producing a positive signed produce requires the number of
cycles equivalent to unsigned multiply. Signed divide producing a negative signed
quotient with positive signed remainder, if any, requires the number of cycles
equivalent to unsigned divide.

7-14

Symbolic:

(AC-MQ)i---"" (AC-MQ)i+n, i=O,
35-n
• Lost; i=36-n, 35
(AC-MQ)i
L
• (AC-MQ)i; i=O, n-l

° ·

Mnemonic: LRSS n (Long Right Shift, Signed)
Octal Code: (660500) + n
Time: see table
Operation: The content of AC o is entered in
the link. Then, the AC and the MQ function
as a 36-bit register to permit serial shifting of
their contents "n" bit positions to the right,
"n" being specified by the contents of the six
low order bits of the instruction. Shifting halts
when the contents of the step counter, initialized to the 2s complement of "n" reach zero.
For each shift step, the contents of AC 17
enter MQo and the contents shifted out of MQ 17
are lost. The content of the link remain unchanged and enters AC o at each step to replace
the contents of vacated bits.
Symbolic:

AC o
•L
(AC-MQ)i
., (AC-MQ)i+n; i=O,
35-n
(AC-MQ)i
• Lost; i=36-n, 35
L
• (AC-MQ)i; i=O, n-l
.SC

Mnemonic: LLS n (Long Left Shift)
Octal Code: (640600) + n
Time: see table
Operation: The AC and the MQ function as a
36-bit register to permit serial shifting of their
contents "n" bit positons to the left, "n" being
specified by the contents of the six low order
bits of the instruction word. Shifting halts when
the contents of the step counter, initialized to
the 2s complement of "n", reach zero. For
each shift step, the contents of MQ o enter AC 17
and the contents shifted out of AC o are lost.
The content of the link, usually initialized to
zero, remains unchanged and enters MQ 17 at each
step to replace the contents of vacated bits.
Symbolic:

(AC-MQ)i
• (AC-MQ)i-n; i=n, 35
(AC-MQ)i
• Lost; i=O, n-l
L
., (AC-MQ)i; i=36-n, 35

° .

Mnemonic: LLSS n (Long Left Shift, Signed)
Octal Code: ( 660600) + n
Time: see table
Operation: The content of AC is entered in
the link. Then, the AC and MQ function as a
serial 36-bit register to permit serial shifting to
their contents "n" bit positions to the left, "n"
being specified by the contents of the six low
order bits of the instruction word. Shifting halts

when the contents of the step counter, initialized
to the 2s complement of "n" reach zero. For
each shift step, the contents of MQo enter AC 17
and the contents shifted out of AC o are lost.
The content of the link remains unchanged and
enters MQ 17 at each step to replace the contents
of vacated bits.
•L
Symbolic: AC u
(AC-MQ)i
., (AC-MQ)i-n; i=n, 35
., Lost; i=O, n-l
(AC-MQ)i
L
., (AC-MQ)i; i=36-n, 35

° .,

Mnemonic: ALS n (Accumulator Left Shift)
Octal Code: (640700) + n
Time: see table
Operation: The contents of the AC are shifted
"n" bit positions to the left, "n" being specified
by the contents of the six low order bits of the
instruction word. Shifting halts when the contents of the step counter, initialized to the 2s
complement of "n", reach zero. For each shift
step, the content of the link, usually initialized
to zero, enters AC 17 to replace the contents of
vacated bits. The contents shifted out of AC 0
are lost.
Symbolic: ACi ---i"~ACi_n; i=n, 17
AC'
• Lost; i=O, n-l
L 1 ., ACi; i=18-n, 17

° .,

Mnemonic:

ALSS n (Accumulator Left Shift,
Signed)
Octal Code: (660700) + n
Time: see table
Operation: The content of AC o enters the link.
Then, the contents of the AC are shifted "n"
bit positions to the left, "n" being specified by
the contents of the six low order bits of the instruction word. Shifting halts when the contents
of the step counter, initialized to the 2s complement of "n" reach zero. For each shift
step, the content of the link remains unchanged
and enters AC 17 to replace the contents of vacated bits. The contents shifted out of AC 0
are lost.
Symbolic:

AC o

ACi---i"~ACi_n;

ACj
L

i=n, 17
., Lost; i=O, n-l
., ACi; i=18-n, 17

° .,

Mnemonic: NORM (Normalize)
Octal Code: 640444
Time: see table
Operation: The contents of the AC and the MQ
are shifted left (i.e., leading zeros are shifted out)
with the AC and MQ functioning as a serial 36bi t register un til:
7-15

Either the content of AC o does not agree with the
content of AC 1 ; i.e., the bits differ in their binary states.
Or the contents of the step counter reach zero.
This six-bit counter is initialized to the 2s complement of 44g (36 10 steps). The contents of the
six low order bits of the NORM instruction word
specify the step count. For each shift step., the
contents of MQo enter AC 17 and the contents
shifted out of AC 0 are lost. The content of the
link, usually initialized to zero, enters MQ 17 to
replace the contents of vacated bits. If shifting
halts because AC o does not equal AC 1 , the contents of the step counter reflect the number of
steps executed to reach the condition. The
counter's contents (2s complement of the step
count plus the steps executed) are accessible
through use of the OSC or LACS instruction.
Symbolic: n = number of steps required to
normalize = 3610 maximum
• (AC-MQ)i-n; i=n, 35
(AC-MQ)i
• Lost; i=O, n-l
(AC-MQ)i
L
• (AC-MQ)i; i=36-n, 35
• SC
(-448 + n)
Programming Note:
Although a NORM or NORMS (normalize, signed)
instruction cannot be interrupted by a program or
automatic priority interrupt request, the intent of
its execution can be interrupted before completion;
i.e., the central processor can grant an interrupt request after the normalization of a quantity but before the quantity and its representative step count
have been completely extracted from the EAE registers and processed. Hence, if interrupt-accessed
subroutines are to make use of the EAE, the following instruction sequences can be included to
preserve the register contents during the interrupt
and to restore them in the EAE at completion of
the interrupt service.
/SAVE EAE REGISTERS DURING INTERRUPT
JMS SUBENTR
::;UBENTR,
o
/SAVE AC CONTENTS
DAC ACSAVE
/MOVE MO TO AC
LACO
/SAVE MO CONTENTS
DAC MOSAVE
/MOVE STEP COUNT TO
LASC
/AC
DAC SCSAVE
/SAVE STEP COUNT

LAC SCSAVE
XOR (77
TAD (640402
AND (640477
DAC,+1

7-16

/COMPLEMENT STEP
/COUNT
/DEVELOP PSUEDO NORM
/DELETE POSSIBLE STEP
/COUNT OVERFLOW
/PLACE NORM IN SE/QUENCE

HLT*
LAC MOSAVE
LMQ
LAC ACSAVE
DBR

/STEP COUNT TO SC
/LOAD MO
/LOAD AC
/RESTORE PC' LIN K'
/ETC,

JMP I SUBENTR

Restoration of the step count to the step counter requires that the 2s complemented quantity,
taken from the SC at the time of interrupt, be
complemented and then combined with the
psuedo NORM instruction. The step count at
this point is one less than the actual value produced by the previous norrnalization. Execution
of the NORM instruction, however, transfers the
2s complemented step count to the SC and in
shifting the AC and the MQ left one bit position (the 6404XX present in the AC shins to
become 50 I XXX) adds the necessary one to the
SC to produce the correctly stored step count.
The DBR instruction (which precedes the JMP I
subroutine termination) primes the computer for
restoration of the interrupted program. Such
restoration occurs during the JMP I instruction.
During this time, the PC and the Link are restored to the contents existing at the time of h
the interrupt, and the options of memory protection and extended memory, if in the systern,
are restored to their status (on or off) at the
time of interrupt. The DBR instruction is ful:ly described in chapter 8 under th,e dis.cu~sion
of the optional multilevel automatIc pnonty
interrupt system. DBR is a basic machine instruction.
Mnemonic: NORMS (Nonnalize, Signed)
Octal Code: 660444
Time: see table
Operation: The contents of AC o enter the link.
Then, the contents of the AC and the MQ are
shifted left (i.e., leading zeros are shifted out)
with the AC and MQ functioning as a serial
36-bit register until:
Either the contents of AC o do not agree with
the contents of AC 1; i.e., the bits differ in their
binary states.
Or the contents of the step counter reach zero.
This counter is initialized to the 2s complement
of 448 (3619 steps). The cont~nts of .the six
low order bIts of the NORMS InstructIon word
*Good programming practice dictates that instructions to be developed at "run" time be
represented by HLT instructions in the source
program. If the development does not occur,
the HLT will facilitate debugging of the program.

specify the step count. For each shift step,
the content of MQ o enters AC 17 and the content
shifted out of AC o are lost. The content of the
link enters MQ 17 to replace the contents of vacated bits. If shifting halts because AC o does
not equal AC l' the contents of the step counter
reflect the number of steps executed to reach
the condition. The counter's contents (2s complement of the step count plus the steps executed)
are accessible through use of the OSC or LACS
instruction.
Symbolic:

AC o
.. L
n=number of steps required to normalize = 36
.. (AC-MQ)i-n; i=n, 35
(AC-MQ)i
(AC-MQ)·
.. Lost; i=O, n-I
.. (AC-MQ)i; i=36=n, 35
L
(-448 + n)
.. SC

Pre-execution

I xxxx

A
17

Post execution

AC,MQ

Instruction Sequence
Register

Y - 2
Y - 1
Y

Y + 1

Contents
LAC Multiplier
MUL
Multiplicand
Next Instruction

Programming Note:
Refer to the note below the description of the
NORM instruction for restoration of the step
counter contents following an interrupt.
EAE ARITHMETIC INSTRUCTIONS
Mnemonic: MUL (Multiply (unsigned)
Octal Code: 653122
Time: 12 microseconds
Operation: Multiply the contents of memory
register Y (the multiplicand) by the contents of
the MQ (the multiplier), and place the resulting
36-bit product in the AC and the MQ with the
more significant half appearing in the AC. The
address of Y is taken to be sequential to the address of the MUL instruction word. Prior to
this instruction, the contents of the link n1ust be
zero and the multiplier must be entered in the
AC. During the set-up phase of MUL, the multiplier is transferred to the MQ, the AC is
cleared to zero, and the step counter is initialized
to the 2s complement of 228 (1810 steps); the
six low order bits of the instruction word specify
the step count. The arithmetic phase, executed
as multiplication of one unsigned quantity by
another (18 bits, binary point of no consequence),
halts when the step counter counts up to zero.
The content of the link remains zero. The contents of Yare unchanged. The program resumes
at the next instruction (memory register Y + 1).
Symbolic: 0
• SC
Y . MQ
• (AC, MQ)

PC+2
Data Structure:

•L

.. PC

C = A . B

Mnemonic: MULS (Multiply, Signed)
Octal Code: (657122)
Time: 14 microseconds
Operation: Multiply the contents of memory
register Y (the multiplicand) by the contents
of the MQ (the multiplier), and place the signed
product in the AC and MQ with the sign notation and more significant portion in the AC.
Bits AC o and AC 1 each receive the sign of the
product; the remaining AC and MQ bits represent the magnitude of the product in 1s complement form. The address of Y is taken to be
sequential to the address of the MULS instruction word. The contents of Yare taken to be
the absolute value of the multiplicand; the contents of the link are taken to be the original
sign of the multiplicand (MULS assumes previous execution of an EAE GSM instruction,
q.v.). Just prior to this MULS instruction, the
multiplier must be entered in the AC. During
the setup phase of the MULS instruction the
multiplier is transferred to the MQ and 1s complemented if negative, the AC is cleared to zero,
and the step counter is initialized to the 2s complement of 228 (1810 steps); the six low order
bits of the MULS instruction word specify the
step count. The arithmetic phase, executed as
multiplication of one signed quantity by another
(sign bit plus 17 magnitude bits, binary point
position of no consequence), halts when the
step counter counts up to zero. The link is
cleared to zero. The contents of Yare unchanged.
The program resumes at the next instruction
(memory register Y + 1).
Symbolic: 0
.. SC
Y MQ
.. (AC, MQ)
L

° .

7-17

PC+2
Data Structure:

If Y > AC,

~ SC
(AC, MQ)/Y --...~ MQ (quotient,
AC (remainder)
o
•L
PC + 2----\i~.... PC

C= IAI

Pre-executi on

I 5 IB I
1
17
0

xxxx

I 0 1I
0

IAI

=:J

Post Execution

[QJ

AC, MQ

15151

I
35

Y - 4
Y - 3

Y - 2
Y - 1

Y
Y + 1

[?J

]

Post execution
(no overflow)

Contents
LAC Multiplicand
GSM (take absolute
value and save sign
in link)
DAC Y
LAC Multiplier
MULS
Multiplicand (absolute
value)
N ex t Instruction

Mo.

Mnemonic: DIY (Divide (unsigned)
Octal Code: (640323)
Time: 13 microseconds
Operation: Divide the contents of the AC and
the MQ (an unsigned 36-bit dividend) by the
contents of memory register Y (the divisor).
The resulting quotient appears in the MQ; the
remainder is in the AC. The address of Y is
taken to be sequential to the address of the
DIY instruction word. Prior to this, the contents of the link must be zero, and the dividend
must be entered in the AC and MQ (LAC least
significant half, LMQ, LAC most significant half).
If the divisor is not greater than the AC portion
of the dividend, divide overflow occurs (magnitude of quotient exceeds the IS-bit capacity of
the MQ), and the link is set to one to signal
the overflow condition; data in the AC and the
MQ are of no value. A valid division halts when
the step counter, initialized to the 2s complement
of 238 (1910 steps), counts up to zero (the six
low order bits of the DIY instruction word specify the step count). The contents of the Yare
unchanged. The program resumes at the next instruction (memory register Y + I).
• L
Symbolic: If Y ~ AC, I
7-1S

AC,MQ

Instruction Sequence:

Y - 5

5 = L ¥ Sign B

A = BQ + r

Pre-execution

*original sign of A

Data Structure:

(overflow)

AC,MQ

meaningless

1:7

Instruction Sequence:

Y - 2
Y - 1
Y

Y + I

Contents
LAC Dividend (least
significant half)
LMQ
LAC Dividend (most
significan t half)
DIY
Divisor
Next instruction

Mnemonic: DIYS (Divide, Signed)
Octal Code: (644323)
Time: 15 microseconds
Operation: Divide the contents of the AC and
MQ (a 36-bit signed dividend with the sign in
bits AC o and AC 1 and the remaining 34 bits
devoted to magnitude) by the contents of memory register Y (the divisor). The resulting quotient appears in the MQ with the algebraically
determined sign in bit MQo and the magnitude
(I s 'complement) in bits MQ1-17' The remainder
is in the AC with bit AC o containing the sign of
the dividend and bits AC 1-17 containing the mag.nitude (1 s complement). The address of Y is
taken to be sequential to the address of the
DIYS instruction word. The contents of Yare
taken to be the absolute value of the divisor;

the can tents af the link are taken to' be the
ariginal sign af the divisar (DIVS assumes previaus execu tian af an EAE GSM instructian,
q.v.). Priar to' this DIVS instructian, the dividend must be entered in the AC and MQ (LAC
af least significant half, LMQ, and LAC af mast
significant half). The MQ partian af a negative
dividend is 1s camplemented priar to' the divisian. If the divisar is nat greater than the AC
partian af the dividend, divide averflaw accurs
(magnitude af the quatient exceeds the 17-bit
plus sign capacity af the MQ), and the link is
set to' ane to' signal the averflaw canditian; data
in the AC and the MQ are af no. value. A valid
divisian halts when the step caunter, initialized
to' the 2s camplement af 23a (19 10 steps), caunts
up to' zero. (the six law arder bits af the DIVS
instructian ward specify the step caunt). The
cantent af the link is cleared to. zero.. The cantents af Yare unchanged. The pragram resumes
at the next instructian (memary register Y + 1).
Symbalic: If Y ~ IACI, 1
., L (divide averflaw)
If Y >/Acl,
o
.. SC
(AC,MQ)/Y-~" MA (quatient), AC
(remainder)
o
•L
PC + 2
.. PC
Data Structure: IAI= B Q + r
Pre-execution

AC,MQ

[]

lsi sl

01 1 BI
01

o12
*original sign of B

Post Execution

LMQ
LAC Dividend (mast
significan t half)
DIVS
Divisar (a bsalu te value)
N ex t Instructian

Y - 3
Y - 2
Y - 1

Y
Y + 1

Mnemanic: IDIV (Integer Divide (unsigned)
Octal Cade: 653323
Time: 13 microsecands
Operatian: Divide the can tents af the AC and
the MQ (AC is zero., MQ cantains a 18-bit
integer dividend) by the cantents af memary register Y (the divisar). The resulting quatient
appears in the MQ; the remainder is in the AC.
The address af Y is taken to. be sequential to.
the address af the IDIV instructian ward. Priar
to. this instructian, the cantents af the link must
be zero., and the dividend must be entered in the
AC (the setup phase af IDIV transfers the dividend to. the MQ and clears the AC). Divisian
averflaw accurs anly if divisian by zero. is attempted, i.e., the quatient's magnitude will nat
exceed the 17-bit plus sign capacity af the MQ.
The divisian halts when the step caunter, initialized to. the 2s camplement af 23 0 (19 10 steps),
caunts up to. zero. (the six law arder bits af the
IDIV instructian ward specify the step caunt).
The cantent af the link is cleared to. zero.. The
can tents af Yare unchanged. The pragram resumes at the next instructian (memary register
Y + 1).
Symbalic: 0
.. SC
MQ/Y
.. MQ (quatient), AC
(remainder)
O----·~L

(no overflow)
L

PC+2--..~PC

I sI

IsI

101
01

Data Structure:

(S=Sign A Y. L)

(S=Sign A)

Pre-execution

(overflow)

AC,MQ

A = BQ + r

I 0I

meaningless

BI
17

XXX

Post Execution

Instructian Sequence:

Y - 5
Y-4

Contents
LAC Divisor
GSM
DAC Divisar in Y
LAC Dividend (least
significan t half)

Q
17

If Y = 0 {overflow}

AC,MQ

meaningless

7-19

Instruction Sequence:

Pre-execution

AC, MQ

Contents
LAC Dividend
IDIV
Divisor
Next Instruction

Y··2
Y .. 1

Y
Y + 1

Mnemonic: IDIVS (Integer Divide, Signed)
Octal Code: 657323
Time: 15 microseconds
Operation: Divide the contents of tht AC and
the MQ (AC is zero, MQ contains a signed integer dividend) by the contents of memory register
Y (the divisor). The resulting quotient appears
in the MQ with the algebraically determined sign
in bit MQ 0 and the magnitude (1 s complement)
in bits MQ1-17' The remainder is in the AC
with bit AC o containing the sign of the dividend
and bits AC 1-17 containing the magnitude (1 s
complement). The address of Y is taken to be
sequential to the address of the IDIVS instruction
word. The contents of Yare taken to be the
absolute value of the divisor; the contents of the
link are taken to be the original sign of the divisor (lDIVS assumes previous execution of an
EAE GSM instruction, q.v.). Prior to this IDIVS
instruction, the dividend must be entered in the
AC (the setup phase of IDIVS transfers the dividend to the MQ, clears the AC, and I s complements the MQ if the dividend is negative).
Divide overflow occurs only if division by zero
is attempted; i.e., the quotient's magnitude will
not exceed the 17-bit plus sign capacity of the
MQ. The division halts when the step counter,
initialized to the 2s complement of 23 8 (19 10
steps), counts up to zero (the six low order bits
of the IDIVS instruction word specify the step
count). The contents of the link are cleared to
zero. The contents of Yare unchanged. The
program resumes at the next instruction (memory register Y + 1).
Symbolic:

~ SC
MQ/Y---". MQ (quotient), AC
(remainder)

O--..L

PC + 2
Data Structure:

7-20

A =

• PC

/BI Q + r

1s 1 A

17 1

IBI~

1 01
o 1

XXX

*original sign of B
Post Execution

o I

(s=Sign A)

(s = L I,i Sign A)

If Y = 0 (overflow)

AC,MQ

I meaningless

[y-]

Instruction Sequence:

Y - 1
Y
Y+

Contents
LAC Divisor
GSM
DAC Divisor (absolute
value) in Y
LAC Dividend
IDIVS
Divisor (absolute
value)
Next Instruction

Mnemonic: FRDIV (Fraction Divide (unsigned)
Octal Code: 650323
Time: 13 microseconds
OperatIon: Divide the contents of the AC and
the MQ (AC contains an IS-bit fractional dividend, MQ is zeroed at steup) by the contents of
memory register Y (the divisor). The binary
point is assumed at the left of AC o . The quotient
appears in the MQ; the remainder is in the AC.
The address of Y is taken to be sequential to the
address of the FRDIV instruction word. lPrior
to this instruction, the contents of the link must
be zero, and the dividend 11lust be entered in the
AC (the set-up phase of FRDIV clears the MQ).
If the divisor is not greater than the dividend,
divide overflow occurs (magnitude of quotient
exceeds the 18-bit capacity of the MQ), and the
link is set to one to signal the overflow condition;
data in the AC and the MQ are of no value. A
valid division halts when the step counter, initialized to 23 8 (1910 steps), counts up to zero (the

six low order bits of the FRDIV instruction word Yare taken to be the absolute value of the divspecify the step count). The contents of the link isor; the contents of the link are taken to be
remain zero. The contents of Yare unchanged.
the original sign of the divisor (FRDIVS assumes
The program assumes at the next instruction (men previous execution of an EAE GSM instruction,
ory register Y + 1).
q.v.). Prior to this FRDIVS instruction, the divSymbolic: If Y ~ IAcl, l--.~ L (divide overflow) idend must be entered in the AC (the setup
If Y>AC ,
phase of FRDIVS clears the MQ and 1s compleo----.,..~ SC
ments the dividend, if negative, prior to the division). If the divisor is not greater than the divACjY
• MQ (quotient), AC
(remainder)
idend, divide overflow occurs (magnitude of the
o
. L
quotient exceeds the I8-bit capacity of the MQ)
PC + 2
.. PC
and the link is set to one to signal the overflow
condition. Data in the AC and the MQ are of
Data Structure: A = BQ + r
no value. A valid division halts when the step
counter, initialized to the 2s complement of 23 8
(1910 steps), counts up to zero (the six low order
Pre-execution
bits of the FRDIVS instruction word specify the
MQ
Y
AC
L
step count). The contents of the link are cleared
to zero. The contents of Yare unchanged. The
B
xxx
A
program resumes at the next instruction (memory
register Y + 1).
17
0
17
35
0
Symbolic: If Y ~ lAC\,
.. L (divide overPost Execution
flow)
{no overflow}
If Y > AC,
O - -..~SC
Y
MQ
L
AC
ACjY
• MQ (quotient),
AC (remainder)
Q
B

PC + 2

.. LC

{overflow}

AC,MQ

me~ningless

Data Structure:

Pre-execution

Instruction Sequence:

A= /B/ Q + r
MQ

XOX

0 1

10
0

I IBI
17

*original sign of B

Contents

Post Execution
(no overflow)

Y - 2
Y - 1
Y
Y + 1

LAC Dividend
FRDIV
Divisor
Next Instruction

Is I Q I
17
1

Is I
0

I 0 I I BI I
0

{s = L \j. Sign A}

(s = Sign A)
{overflow}

Mnemonic: FRDIVS (Fraction Divide, Signed)
Oct~ Code:
654323
Time: 15 microseconds
Operation: Divide the contents of the AC and
the MQ (AC contains a signed fractional dividend,
MQ is zeroed at setup) by the contents of memory register Y (the divisor). The binary point
is assumed between AC o and AC 1. The resulting
quotient appears in the MQ with the algebraically
determined sign in bit MQ o and the magnitude
(I s complement) in bits MQ1-17. The remainder
is in the AC with bit AC o containing the original
sign of the dividend and bits AC 1-17 containing
the magnitude (I s complement). The address of
Y is taken to be sequential to the address of
the FRDIVS instruction word. The contents of

AC,MQ

101

meaningless

IB I

o 1

Instruction Sequence:

Y - 5
Y-4
Y - 3

Y - 2

Y - I
Y
Y + 1

Contents
LAC Divisor
GSM
DAC Divisor (absolute
value) in Y
LAC Dividend
FRDIVS
Divisor (absolute value)
Nex t Instruction
7-21

TABLE 7-2 EAE MICROINSTRUCTIONS

Bit
Positions

Binary
Code

Function

Enter the content of AC o in the link for signed
operations.

Clear the MQ.

Read the content of AC 0 into the EAE AC sign register prior to carrying out a signed multiply and divide
operation.

6,7

Take the absolute value of the AC. Takes plaetl after
the content of AC o is read into the EAE AC sign
register.

Inclusive OR the AC with the MQ and read into MQ.

Clear the AC.

9, 10, 11

000

Setup. Accompanies code in bits 15, 16, and 17.

9, 10, 11

001

Multiply. Causes the number in the MQ to be multiplied by the number in the memory location foUowing
this instruction. If the EAE AC sign register is 1, thl~
MQ is complemented prior to multiplication. The ex··
elusive OR of the EAE AC sign and the link is entered
in the EAE sign register.
The product is in the AC and MQ, with the lowest
order bit in MQ bit 17. At completion of this instruction the link is cleared and if the EAE sign is 1,
the AC and MQ are complemented.

9, 10, 11

010

Unused operation code.

9, 10, 11

011

Divide. Causes the 36-bit number in the AC and Me>
to be divided by the 18-bit number in the memory .
register following the instruction. If the EAE AC sig:n
is 1, the MQ is complemented prior to starting the
division. The exclusive OR of AC o and the link is
placed in the EAE sign register. The AC portion of
the dividend must be less than the divisor or divide
overflow occurs. In such cases, the link is set and
divide does not occur. Otherwise, the link is c1t~ared.
At completion of this instruction, if the EAE sign
was aI, the MQ is complemented. Thus, the remainder has the sign of the dividend.

9, 10, 11

101

Long right shift. Causes the AC and MQ to be shifted
right together as a 36-bit register the number of times
specified in the instruction. On each step the link
fills AC bit 0, AC bit 17 fills MQ bit 0, and MQ bit
17 is lost. The link remains unchanged.

9, 10, 11

110

Long left shift. Causes the AC and MQ to be shifted
left together the number of times specified in the in
struction. On each step, MQ bit 17 is filled by the
link; the link remains unchanged. MQ bit fills AC
bit 17, and AC bit is lost.

7-22

TABLE 7-2 EAE MICROINSTRUCTIONS (continued)

Bit

Positions

Binary
Code

9, 10, 11

100

Normalize. Causes the AC and MQ to be shifted left
together until the step count is equaled or AC bit a
f AC bit 1. MQ bit 17 is filled by the link; the link
is not changed. The step count of this instruction is
normally 44 (octal). When the step counter is read
into the AC, it contains the number of shifts minus
the initial shift count as a 2s complement 6-bit number.

9, 10, 11

111

Accumulator left shift. Causes the AC to be shifted
left the number of times specified in the shift count.
AC bit 17 is filled by the link, but the link is unchanged.

Function

12-17

Specify the step count for all EAE commands (9-11)
except the setup command.

On the setup command only, causes the MQ to be
complemented.

On the setup command only, causes the MQ to be inclusively ORed with the AC and the result placed in
AC.

On the setup command only, causes the AC to be inclusively ORed with the SC and the results placed in
AC bits 12-17.

7-23/7-24 (blank)

CHAPTER 8
DATA FORMATS AND ARITHMETIC INFORMATION
GENERAL

Complement Notations

This chapter defines the possible formats for
PDP-9/L data words, and presents information
basic to the accomplishment of arithmetic
operations by the PDP-9/L. The information
presented includes: explanations of the three
possible notations for signed data (sign and magnitude, 1s complement, and 2s complement);
a discussion of scaling considerations for fixedpoint arithmetic; and descriptions of the addition and subtraction processes.

In both complement notation (Is and 2s), the
sign indicator (bit 0) is a for positive quantities
and 1 for negative quantities. The 1s complement of a quantity is equivalent to the logical
complement of its magnitude and sign; i.e., all
binary 1s are replaced by as and all binary as
are replaced by 1s. The 2s complement of a
quantity is equivalent to its 1s complement, plus
the addition of one to the lowest order, or
least significant, bit. Positive quantities in either
notation have identical representations. For example: + 1510 is represented in a PDP-9/L data
word as

The multiply and divide processes are presented
in the "Mathematical Subroutines" section of
the Software Reference Manual, DEC-9B-GSAA-D.
This reference source also includes descriptions
of single- and multi-precision arithmetic, plus
use of the Basic Software floating-point arithmetic system. Subroutines in the PDP-9/L arithmetic library take full advantage of the computing
power of the Extended Arithmetic Element (EAE)
when this option is included in a PDP-9/L system.

SIGNED DATA NOTATIONS

000 000 000 000 001

111

in either 1s or 2s complement notation. The 1s
complement of -15 10 is represented by
s

111 111 111 111 110 000
The 2s complement of -15 10 appears as

s
The PDP-9/L uses three notations to represent sign111 111 111 111 110 001
ed data. They are: sign and magnitude, Is complement, and 2s complement. In each, bit 0, or
A quantity of zero has two representations in 1s
the most significant bit of a single- or multi-precomplement notation:
cision data word, serves as the sign indicator:
s
a a for a positive quantity, a 1 for a negative
+010
000 000 000 000 000 000 2
quantity.
and
Sign and Magnitude Notation
s
-0
10
111 11 1 111 111 111 1112
In the sign and magnitude notation, quantities
of equal magnitude but opposite in sign differ
only in the content of the sign indicator bit; i.e.,
The 2s complement notation has one representthe positive number will contain a a in bit 0, and ation for zero:
the negative number will contain a 1 in bit O.
s
For example:

+0 10

+131

071 10

-131

07110

s
all 111 111 111 111 1112
s

111 111 111 111 111 1112

Observe that conversion of a positive number to
a negative number, and vice versa, requires only
the sign bit be complemented; the magnitude
bits are not affected.

000 000 000 000 000 000 2

Minus zero in 2s complement notation likewise
appears in binary form as
s

-0

-0 10

000 000 000 000 000 000 2

since complementing each bit and then adding
one to the low order bit results in the propogation of an arithmetic carry through the entire
word, as follows:
8-1

s
000 000 000 000 000 0002

+010

is complemented to be

data in single- and multi-precision formats.
For signed data words, bit 0 serves as the sign
indicator, with a a for a positive quantity., and
a 1 for a negative quantity.

III III III III III Ill,)
+(

A signed single-precision data word includes a
sign bit and 17 magnitude bits (figure 8-1 a).

with_ plus one
equals
S

-010

Data Word Formats

000 000 000 000 000 0002

The binary 1 carried out of the sign bit "overflows" the 18-bit capacity of the PDP-9/L word.
Since two identical representations of a would
be ambiguous to the computer, convention has
adopted one representation of a in 2s complement notation, namely +0.

A signed double-precision data word consists of
two computer words for a total of 36 bits
(figure 8-1b). The first word contains the sign
bit and the 17 most significant bits; the second
word contains the 18 least significant bits. The
words are normally stored in consecutively
addressed core memory locations for ease of
programming.
Magnitudes of Data Words

Typical PDP-9/L instruction sequences for forming the 2s complement of any number are:
LAC Y
CMA
TAD (1
DAC Y

CLC
TAD Y
CMA
DAC Y

The TAD (2s complement add) instruction must
be used rather than the ADD (1 s complement
add) instruction as ADD permits an end-around
carry into the low order bit.
The following list indicates the representations
in 1sand 2s complement notations of a range
of numbers from +5 to -5; a five-bit word is
used for simplicity.
Number

1s Complement

+5
+4
+3
+2
+1
+0
-0
-J
-2
-3
-4
-5

00101
00100
00011
00010
00001
00000
11111
11110
11101
11100
11011
11010

2s Complement
00101
00100
00011
00010
00001
00000
Not considered
11111
11110
11101
11100
11011

DATA WORDS
PDP-9/L hardware and software capabilities include add, subtract, multiply, divide, etc., of
8-2

For Is complement signed and sign-and-magnitude notations, the permissible magnitude of
any quantity, X, is in the range of:

where n is the number of bits allocated to the
storage of data in a data word. For a sing1eprecision data word (sign bit and 17 data bits),
this relationship becomes:

-131 07110 ~X~+131 071 10
For 2s complement signed notation, the permissible magnitude of any quantity, X, is in the
range of:

_2 n - 1 ~ X ~ 2n -1 -1
where n is again the number of bits allocated
to the storage of data. A single-precision
data word has the range:
_217S X~217-1
or
-131 07210 ~ XS +131 071 10
The position of the decimal point is implied in
the above ranges.

SIGN

0- POSITIVE
1- NEGATIVE

SIGNED NUMBER

,--A-v

11 112

Single-Precision Data

1 141

l17l

1st WORD
SIGN
O-POSITIVE
1- NEGATIVE

141 15

17
}

v
MOST SIGNIFICANT HALF

2nd WORD
LEAST SIGNIFICANT HALF

141 15

b. Double-Precision Data

Figure 8-1 Data Word Formats
Basic Software Floating-Point Formats
Floating-point representation of a binary number
consists of two parts: the exponent and the
mantissa. The mantissa is a fraction with the
binary point assumed to be positioned between
the sign bit and the most significant data bit.
The mantissa is always stored in a normalized
state; i.e., leading as are eliminated from the
binary representation so that the high order bit
is always a 1. The exponent as stored represents the power of 2 by which the mantissa is
multiplied to obtain the number's value for use
in computation.
The PDP-9/L floating-point software system offers
two modes for storage of floating-point numbers:
three-word mode and two-word mode.
The three-word mode requires three memory
locations for storage of a floating-point binary
number (figure 8-2a). The exponent, a signed
17-bit integer in 2s complement notation, occupies
the first word, or memory location. The mantissa, a 35-bit quantity in sign_and magnitude

notation, is stored in the second and third words.
The sign of the mantissa is stored in the highorder bit of the second word.
The two-word mode requires two memory locations for storage of a floating-point binary number, (figure 8-2b). The exponent, an eight-bit
integer in 2s complement notation, and its sign
occupy the nine high-order bits of the first
word. The mantissa, a 26-bit quantity in sign
and magnitude notation, is stored in the nine
low-order bits of the first word and in the I 7
low-order bits of the second word. The sign of
the mantissa is stored in the high-order bit of
the second word.
SCALING FOR FIXED-POINT ARITHMETIC
In the programming of arithmetic operations on
a fixed-point computer, the position of the scale
point (i.e., the binary point in a binary number)
must be kept track of by the programmer. Once
numbers have been entered in the computer, there
is no hardware or movable machine point to
8-3

~ORDS

(2's; COMPLEMENT IF NEGATIVE)

EXPONENT

11'

Is I

MA~ITISSA

I
I

(SIGN CHANGE IF NEGATIVE)

MANTISSA

o. THREE-WORD MODE
~ORDS

(2'S COMPLEMENT IF NEGATIVE)

EXPONENT

MANTISSA

]
17

MANTISSA (SIGN CHANGE IF NEGATIVE)
L - - - L -_ _ _ _ _ _ _ _ _ _ _

]

b. TWO-WORD MODE

Figure 8·-2.

Floating Point Formats

represent the scale points. The scale point exists only in the mind of the programmer, and
only by keeping track of its imaginary position
is he able to correctly interpret the machine's
calcula ted results.
The fundamental properties of scaled numbers
can be simply explained by considering a hypothetical decimal machine capable of manipulating
numbers consisting of a sign and five decimal
digits. As in real computers, this machine acts
as if there were a scale point between the sign
and the leftmost decimal digit. It is called the
machine point. Thus, every number processed
by the computer can be thought of as a signed
decimal fraction.
Example:

+ 1\ 12345

machine point
However, the programmer is free to assign a
decimal point at any position In the number.
For example, the above number could represent
+ 123.45 if the scale point were thought of as
being three places to the right of the machine
point. In that case the number would be
written +1\ 12345 D3, where D3 indicates that
the decimal point is three places to the right
8-4

of the machine point. In other words, D3 is
the decimal scale factor.
Other numbers with different scale factors can
have the same representation in the machine.
Examples:

+ /\ 12345 D2 = + 12.345
+ 1\ 12345 D4 = + 1234.5
+ 1\ 12345 DO = +.12345

The scale factor need not be restricted by the
size of the machine word. Numbers in the
hypothetical computer can be assigned scale
factors that exceed five, or the scale factors can
even be negative.
Examples:

+ 1\ 12345 D7 = + 1234500:
+ 1\ 12345 D-4 = +.000012345

Of course, these are merely programmer's representations; the machine number is always
restricted to a sign and five digits.
Addition and Subtraction
In addition and subtraction, the scale factors of
the numbers to be combined must be identica.l.
Thus, +1\42204 D3 added to +1\23332 D3 gives
a sum of + 1\ 65536 D3 (422.04 + 233.32 =
655.36). This rule has the: same basis as in or-

dinary arithmetic. If the scale factors differ,
one number must be shifted until the scale
points are aligned.
Examples:

+/,)4271 DI (+1.4271)
+1\38496 D3 (+384.96)

The number +/\14271 DI is brought into the
accumulator and shifted right two decimal
places before addition or subtraction. The scale
point changes when the number shifts.
+001.42
+384.96
+386.38

(+.00142 D3)
(+.38496 D3~
(+.38638 D3

Notice that if the number of the higher scale
factor had been shifted left instead, its two most
most significant digits would have been lost and
the resulting sum would have been seriously in
error.
Multiplication
When two numbers are multiplied together, the
scale factor of the product is the algebraic sum
of the scale factors of the multiplier and multiplicand.
Example:
(+ 00200 D3) x (+ 06000 D2) = + 0001200000 )
D5, or 12
Normally the most significant part of the product is in the AC and the least significant part
is in the MQ. Thus, the product in the above
example would appear in the computer with
the machine point between the sign and leftmost digit in the AC. The machine point for
the least significant portion of the product is
ignored.
It is important to remember that the two deci-

mal numbers, + 00200 and + 06000, when
multiplied in the computer will result in the
machine product of + 0001200000 regardless
of the positions of the scale points in the multiplier and multiplicand. The scale points must
be kept track of by the programmer. Thus
fractions, as well as integers, can be multiplied
in exactly the same way.
Examples:
+ 20000 05 x + 00060 03 = +1\0001200000 08
/\
/\
(+20,000 x +.6 = +12,000)
+,,00200 DO x

A06000 DO = ,,0001200000 DO

(+.002 x +.06 = +.00012)
+ 00200 0-2 x +A60000 0-4 = +/\0012000000 0-6
/\
1\
(+.00002 x +.00006 =
.0000000012)

Division
The remarks above for multiplication apply to
division, with the following exception. The
scale point of the result is the algebraic diff~I~l1ce
of the scale points of the operands.
SCALING ON A BINARY COMPUTER

The fundamental properties of scaled numbers in
a com pu ter as outlined previously can now be
applied to the binary and octal numbering systems
as used in a fixed-point, binary computer. The
decimal scale factor becomes the binary scale
factor and is indicated by a B in front of the
scale factor. The machine point is still positioned
between the sign and the leftmost digit, but in
this case the sign is a binary digit. In a 18-bit
computer such as the PDP-9, the leftmost bit
is the sign bit and there are 17 bits for the number.
Because the number system used by the machine
is now different from "that customarily used by
the programmer, conversion is a new consideration.
The programmer may be dealing with decimal or
octal numbers, but because the machine is binary, the scale factors must be determined from
the binary equivalents. As will be explained below, a scaling analysis is performed on each problem so that the binary scale factors chosen result in the most efficient use of the 18-bit word.
Having selected the appropriate scale factor for
a given number, it is expressed in decimal or
octal form followed by the binary scale factor.
For example, the combination 975 B I 0 means
that the decimal number 975, when converted
to binary form, has a binary point ten places
to the right of the machine point.

The decimal number 975 BI0 can be converted
to binary to appear in the machine as follows:
975.0
(decimal)
(octal)
1717.0
(binary) 1111001111.0

BIO
BIO
BIO

Shift binary point left 10-bit positions
. 1 1 1 I 00 1 1 I 10
Add sign bit and trailing 0 bits
s
0.11 110 011 I
000 000
machi~ point
binary point

In octal, the machine word is
363600
8-5

Negative numbers may be expressed in either the
1s cornplement notation or the 2s complement
notation. For example, consider the octal number:

In this connection, the concept of "minimum
binary scale" is helpful. At a binary scale of 5,
the largest positive integer than can be contained
is 25-1 which in decimal is 31.

-3.2 B6
As a positive number, 3.2 B6 would be stored in
the computer as
s
0.00 00 1 101 000 000 000
matftine point
binary point

The programmer may not always be successful in
his attempts to arrange numbers so that overflow
will not occur. If a programmer suspects that
overflow may occur as a result of an addition or
division, he should follow such an operation by a
program sequence that would correct the error or
at least indicate that such an overflow took place.

As a negative nUlnber, it would be stored as:

a O~ 0 111 111 111 (1 s complement)

The proper location of the binary point and the
avoidance of overflow, at best, takes some effort
on the part of the programmer.

~ 1 110 O~ 1 000 000 000 (2s complement)

PROGRAMMING TECHNIQUES FOR SCALING

~ 11

or
One technique used in scaling is to express numbers in a symbolic form that would clearly imply the position of the binary point. The gen··
eral form is:

OVERFLOW
Suppose we are working with signed quantities
and we add the numbers:

where:
Binary Representation

Octal Equivallmt

DAD 010 000 000 000 000

220000 BEi

,Decimi!! Value

S
18 85

S
5 B~)

ORO 101 000 000 000 000

50000 B5

S
2385

OAi 0 111 000 000 000 000

270000 BEi

Notice that there was no carry to the left of the
first machine position (i.e., into the sign bit).
However, if we try to add the numbers:
Decimal Value
-----

Binary Representation

5 m;

S
011 100 000 000 000 000
S
000 010 000 000 000 000

3385

S
100 001 000 000 000 000

28 85

Octal Equivale!nt

340000 BEi
50000 B5
410000 BEi

The result as given in the machine would be
erroneous because the magnitude portion of the
AC is not large enough to hold the sum. This
situation is described as overflow.
Overflow is something which must be avoidedl in
all normal circumstances. To accomplish this, the
programmer working with fixed-point data must
have some knowledge of the magnitude of the
numbers in the program and, accordingly, must
locate each number at such a scale that overflow
cannot occur even in the "worst case".
8-6

X2-q = XI
X is the value of the number.
2 q is the factor such that q is the
smallest integer that makes 2 q greater
than the maximum value of X.
q corresponds to the minimum binary
scale factor which was previously discussed.
X I is the scaled form of X (i.e., X is X I
with the binary point c; places to the
right of the machine point).

A scaling analysis should be performed on each

problem to insure maximum accuracy (i.e., the
most efficient use of the binary word so that
there are no leading insignificant bits). At the
same time, the programmer must insure that
there will be no loss of the most significan t bits
by overflow at any step in the calculation.
These are the two bounds within which the programmer must keep the numbers as they are
stored and manipulated in the machine.

Analysis
In the programming of any given problem or
equation, there are three steps prior to the actual coding which should be taken to insure
maximum accuracy and to prevent error due to
overflow.

Step I: Determine the limits of the values
of all numbers to be used in the problem
(maximum and minimum).
Step 2: Determine the scale factors and set
up the relationships between the true numbers and the scaled fractions.
Step 3: Substitute the scaled quantities into
the original equation and cancel where possible. The scale factors that do not cancel
specify the number of required shift operations. If the scale factor of a term is negative, the number must be shifted right before
manipulation is performed. If the scale factor
is positive, the number must be shifted left
if it is to be stored at minimum binary scale.

Machine Instruction Coding

Assume that the ten values of the numbers are
stored in consecutive locations starting at location A I as a i B7 and that the sum is stored in A.
ADD UP,

DZM
A
lAM -12+1
DAC CNTR
lAC (A1-1

lOOP,

Program the operation specified by:

where aj ~ K for i = I, 2, 3, . . . . n. The
maximum value of A is ~ K . n' that is, the maximum value of the sum is obtained by multiplying
the upper limit of any element in the list to be
summed by the number of elements in the list.
1.

Statement

Solve the above problem for n = 10 and K =
100.0;
2.

A1,

la1
/a2
la3

Step I:

Step 2:
Step 3:

Programming Note:
If the numbers were signed, the instruction sequence of CLL and LRS 3 would be replaced
by LRSS 3.

Multiplication Scaling
When multiplication is performed by the PDP-9 /L,
the product of two "n" bit numbers is one "2n"
bit number. Usually the high-order portion is
stored in the MQ. * The fundamental rule, again,
is:
Scale factor of multiplier + scale factor of
multiplicant = scale factor of product.
I.

Statement

Program the multiplication operation:

x = a.b
2.

Analysis
Step I:

Analysis
aj ~ 100.0 for j = 1, 2, 3, . . . 10
Therefore, A ~ K . n = 100.0 . 10
= 1000
A = 2 10 . A I
aj = 27 . ajl
210 AI 27 al1 + 27 a l2 + . . . . .
+27 al10
A I = 2 -3 a 11 + 2-3 a 12
+2 -3 al10

IINITIALIZE COUNTER FOR NUMIBER OF TERMS
IINITIALIZE AUTOINDEX RERISITER

DAC AUT 1
lAC I AUT 1 IPICK UP TERM
Cll
lRS 3
ISHIFT RIGHT
TAD A
DAC A
ISZ CNTR
JMP lOOP
JMP DONE
IEXIT, SUMMATION COMPLETED

Addition Scaling
As emphasized before, quantities to be added
(or subtracted) must have the same scale factors.
However, in order to prevent an overflow in the
summing process, it is not enough to scale the
final sum according to its limit. Generally the
program must be scaled by the largest limit
which applies to any element in the sum or partial sum generated during the summing process.
Example 1

IINITIALIZE

Therefore

a
b
x

400.0
1000.0
490,000

Step 2:

a = 29 a l
b= 2 10 b l
X = 217 Xl

Step 3:

217 Xl
X I

= 29 a l .2 10 b l
= 22 a l . b l

*MQ if the EAE option is present; otherwise
a memory location.
8-7

Machine Instruction Coding

Assume that the values of a and b are stored
in locations A and B. Assume that they are
scaled B9 and B I 0, respectively.
.MULT,

NOTE:

LAC B
DAC .+3
LAC A
IVIUL
HLT
LLS

IPICK UP B
IPICK UP A
ISHIFT PRODUCT LEFT 2 PLACES

This example assumes use of the EAE.

After the multiplication, the shift brings two
more significant bits into the high-order protion
of the product. Knowing the maximum value
of y more definitely (i.e., if a and b could never be maximum at the same time) would allow
for even more accuracy. In this example, the
limit of y was not known so it was assumed to
be 400,000 as calculated in Step I of the analysis.

Division Scaling
When division is performed in digital computers,
the dividend is a "2n" bit word and the divisor
is an "n" bit word.
Remember that in division the 18-bit divisor
word must be greater in magnitude than the 18
high-order bits of the dividend for division to
occur without overflow. Therefore, the programmer should scale the values so that division
will occur with maximum dividend and nlinimum
divisor. For example, if both dividend and divisor are stored at minimum binary scale, the
dividend should be shifted one position to the
right by a double-shift subroutine prior to division to insure that overflow does not take place.

8-8

FIXED-POINT ADDITION
Fixed-point addition of a number contained in
a core memory location, to a number contained
in the accumulator, is performed directly
through use of the ADD (I s complement add).
instruction, or the TAD (2s complement add) mstruction. This assumes the binary points have
been aligned through scaling of the quantities
and both numbers are properly represented in
the appropriate complement notation. Addition
can be performed without regard for the signs
of the numbers. However, like signed numbers
must be scaled to prevent the possibility of overflow.
FIXED POINT SUBTRACTION
Subtraction in the PDP-9/L is performed by complementary addition; i.e., the subtrahend is converted to its appropriate complement notation
and then added to the minuend. As in addition,
the binary points of both numbers must 1be
aligned through the provisions of scaling, and
both must be represented in the same complement notation. Subtraction can be performed
without regard for the signs of the numbers.
Assuming that two numbers are both stored in
memory locations, typical routines to finel the
value of A-B follows:
15 Complement

25 Complement

LAC B

ILOAD SUBTRAHEND

LAC B

CMA

/FORM lS COMPLE/MENT
/-B+A

CMA

ADD A

TAD (1
TAD A

ILOAD SUBITRAHEND
/FORM ·lS COM·
/PLEMENT
/FORM 28 COM/PLEMENT
/-B+A

Both routines eend with the result in the accumulator.

CHAPTER 9
INPUT/OUTPUT CONSIDERATIONS
GENERAL
This chapter discusses the operation of and the
programming techniques for the basic PDP-9/L
input/output facilities, the real-time clock, and
the Type KF09A Automatic Priority Interrupt
and the Add-to-Memory features. The basic facilities include: provisions for executing program
controlled (single word) transfers and data channel (block) transfers via the I/O bus; the program interrupt control; the I/O skip facility;
and the I/O read status facility.
The PDP-9/L offers two modes for executing I/O
data transfers:
1.
2.

Program controlled transfers. *
Data channel transfers.

Program controlled transfers occur as the result of
lOT (input/output transfer) instruction execution.
These instructions, contained in the body of a
main program or in appropriate subroutines, are
microcoded to effect response of a specific device
interfaced to the I/O bus system. The nlicrocoding includes the issuing of a unique device
selection code and appropriate processor-generated
pulses to initiate device operations, such as taking
data from the bus or placing data on the bus or
clearing device flags. All program controlled
transfers are executed through the accumulator in
parallel bytes up to 18 bits in length.
The data channel facility provides for relatively
high speed transfers of data in blocks between
peripherals (DECtape, magnetic tape, etc.) and
system core memory. The transfers are controlled by word counter registers and current
address registers contained in a memory bank.
Eight pairs of these registers are provided to control non-overlapping data channel transfers to or
from up to eight devices. . A data channel trans-

fer request "breaks" program control at completion of the current instruction * * and suspends
execution of the program in progress until the
current word transfer is completed (three machine cycles for input to memory, four cycles
for output to device). Successive breaks are
granted to either the active device or another
data channel device provided the request for
service is made prior to completion of the
current channel transfer action. The maximum
transfer rate for the facility is between 250,000
and 333,333 words per second, depending on
the mix of input and output transfers.
All I/O data transfers function within the precedence of the following priority structure.
1. Data channel (DCR) requests.
2. Real-time clock counting.
3. Automatic priority interrupts (API),
8 levels (optional).
4. Program interrupts (PI).
5. Main program in progress (lowest
priority).
A higher priority request for service interrupts
any in-process service of a lower priority at the
end of the current instruction. Program interrupts and priority interrupts require that the
main program transfer control to specific service
subroutines. These routines must be programmed
to restore control to the interrupted program at
completion of the service interval. Computergranted breaks satisfy data channel requests; i.e.,
program execution is delayed but not disturbed,
while the data channel transfers information between memory and the requesting device via the MB.

PROGRAM CONTROLLED TRANSFERS
The majority of I/O transfers occur under control of the program, taking advantage of the

*In truth, all I/O transfers are made by program control. The differentiation made throughout
this handbook refers to the relative degree of control; i.e., the program controlled transfer mode
requires the execution of lOT instructions to effect the transfer of each data word, while the
channel modes require only that the program initialize the parameters (word count, starting
address, etc.) of the block transfer.
** An lOT or XCT instruction prohibits interruption of the instruction immediately following
it; i.e., the break is not granted until completion of the instruction following the current lOT
or XCT instruction.
9-1

control elements present in the computer and
in device controls interfaced to the I/O bus.
Programmed transfers require more computer
and actual time than do data channel and direct
memory access transfers. The simplicity and inherent lower cost of the device controls, however,
coupled with the high speed of the computer relative to the operational speed of most peripheral devices offset this time discrepancy.
All program controlled transfers take place through
the accumulator (AC) in bytes up to 18 bits in
length. In transfers within the central processor
and between the processor and core memory, data
are processed as 18-bit words, the sole addressable unit in the PDP-9/L. For bytes of less than
18 bits, unused bits in the data word normally
remain zeroed. Programming techniques of
masking and shifting the contents of words may
be used to pack and unpack bytes for the purpose of reducing core memory storage requirements. The following program sequence represents a single output transfer to a device:

/LOAD THE AC WITH DATA

l.AC Y

I9!...S~I~ I

/TEST DEVICE STATUS

/TEST DEVICE UNTI L READY

lOT WRITE.J

/TRANSMIT DATA TO DEVICE

JMP .-1

The LAC instruction reads the data word from
its effectively addressed core memory location
into the AC. The program then issues the lOT
skip instruction to test the readiness of the
selected device. It remains in the two-instruction
loop completed by the JMP return instruction
until the selected device indicates its readiness to
accept the data by returning a signal via the I/O
skip line to the processor. At that time, the lOT
write instruction places the data on the I/O bus
data lines, selects the device, and causes it to
generate an internal command which strobes the
bus data into its information register.
Each lOT instruction is microcoded to issue both
unique device selection code and appropriate
commands to effect the required device action
(refer to chapter 7, for a description of the ITO
instruction format; refer to chapters 4 and 5 for
description of lOT instructions for peripheral
devices offered in the PDP-9/L line).
For a simple input transfer, the following sequence is typical:

9-2

[~~S..!SI~ I

/TEST DEVICE STATUS

/TEST DEVICE UNTI L READY

lOT READ+i

/ACCEPT DATA FROM DEVICE

DAC Y

/ENTER DATA IN MEMORY

JMP .-1

Again, the program issues the lOT skip instruction
to test the readiness of the selected device and
remains in the two-instruction loop completed by
the JMP return instruction until the device sig..
nals that it is ready to send data to the processor. At that time, the lOT read instruction
selects the device and causes it to generate internal commands which strobe the data onto the
I/O bus data lines and send a read request signal
to the processor. The processor then inclusively
ORs the bussed data into the AC. The DAC instruction deposits the data word in the effectively
addressed core memory location. It is normal
practice in input transfers to have the lOT read
instruction microcoded to effect clearing of the
AC prior to the entry of the data sent by the
device.
The rate at which programmed transfers can be
made is a function of the characteristics of the
devices and the program's use of them. The lOT
instruction capability of the PDP-9/L allows programmed control of up to 256 devices and the
generation of up to three unique commands per
each of the 256 possible device selection codes.
Devices requiring more than three internall commands are simply assigned additional device
selection codes.
INPUT/OUTPUT READ STATUS FACILITY
Execution of the lOT instruction 10RS (octal
code 700314) enters the states of device flags (bipolar signals, i.e., 0 or 1) in specific bits of the AC.
The state of a specific flag or group of flags can be
quickly determined by programmed checks of the
AC contents. Figure 9-1 shows the bit positions
associated with the commonly interfaced flags.
The 10RS word can contain up to 18 flag bits.
Those bits not used are zeroed. The presence of
a flag is indicated by a 1 state in the corresponding
AC bit.
Switching the REGISTER DISPLAY control
(console) to the STATUS position simulates exe~u
tion of the 10RS instruction with the processor In
the "program stop" condition. The c<;>ntents ~)f the
10RS word (i.e., the states of the devIce flags) are
displayed in the REGISTER indicators (console) at
this time.

PROGRAM
INTERRUPT
ON

TAPE
PUNCH
FLAG

TELETYPE
PRINTER

I0 I

FLAG

TAPE
READER
NO TAPE

'---y--J

TAPE
READER
FLAG

TELETYPE
KEYBOARD
FLAG

RESERVED FOR
SPECIAL USERS
DEVICES

DECTAPE
FLAG ~H

I :3 14 I 5

'---y--J

REAL
TIME
CLOCK
OVERFLOW
FLAG

'---y--J
LIGHT PEN
FLAG

REAL TIME
CLOCK
ENABLED

TAPE
PUNCH
NO TAPE

131141 151 161 17

~'~--~y~----~)

'-y--l

MAG
TAPE*tt

DRUM
FLAG

UNASSIGNED

* WILL CAUSE A PROGRAM INTERRUPT
+ INCLUSIVE OR OF TRANSFER COMPLETION AND ERROR FLAGS
* ++

MTF AND EF

Figure 9-1

IORS Word-Status Bit Assignment

The functions of the device flags normally interfaced to the IORS facility are as follows:

ation, normally a CRT-displayed point. The pen
is equipped with a manually operated shutter
which should be opened only when the pen is
Program Interrupt - a 1 bit indicates that the propositioned on the face of the CRT display. The
gram interrupt control is enabled. A a bit indicates flag is also interfaced to the program interrupt
that it is disabled. The program interrupt contro
control to request program interruption when
is automatically disabled upon the grant of a prothe flag goes to the 1 state.
gram interrupt request.
Real-Time Clock Overflow - a 1 bit indicates that
Tape Reader - a 1 bit indicates that the reader
the real-time clock counter (stored in memory lowas previously selected and has assembled a charcation 00007 of bank 0) has overflowed; i.e.,
acter in its buffer for transfer to the AC upon
the initialized clock count (in 2s complement
execution of a "read buffer" lOT instruction.
form) has been incremented to zero. The flag
This flag is also in terfaced to the program in teris also interfaced to the program interrupt conrupt control to request program interruption when
trol to request program interruption when the
the flag goes to the 1 state.
flag goes to the 1 state.
Tape Punch - a 1 bit indicates that the paper tape
punch has punched a line of tape relating to the
contents of the AC at the time of selection. The
flag is also interfaced to the program interrupt control to request program interruption when the
flag goes to the 1 state.

Real-Time Clock Enabled - a 1 bit indicates that
the real-time clock is enabled and incrementing
the contents of location 00007 by one at the
rate of 60 times per second (or 50 times per second for 50 Hz powered PDP-9/L systems). A
a bit indicates that the real-time clock is disabled.
The flag is not interfaced to the program interTeletype Keyboard - a 1 bit indicates that the key- rupt control.
board buffer has assembled a character code relating to a struck key. The flag is cleared when the
Tape Reader No Tape - a 1 bit indicates that the
assembled code is read into the AC by an lOT instruction. The flag is also interfaced to the program paper tape reader has detected a no-tape condition and halted. In the case of a tape break,
interrupt control to request program interniption
since
the break may be skewed, approximately
when the flag goes to the 1 state.
12 lines of previously read tape should be considered as invalid data upon detection of the noTeletype Printer - a 1 bit indicates that the teletape flag going to a 1. Although this flag is not
printer is ready to accept a character code from
interfaced to the program interrupt control, it
the AC. The flag is cleared when the teleprinter
does force the tape reader flag to go to the 1
buffer is loaded and it remains so until the action
state
and hence request program interruption for
called by the code has been executed. The flag is
then again set to 1. The flag is also interfaced to the no-tape condition. A program may make use
of the no-tape flag by executing an IORS inthe program interrupt control to request program
struction and testing the AC contents prior to
interruption when the flag goes to the 1 state.
each selection of the reader. An alternative
method calls for a program interrupt accessed subLight Pen - a 1 bit indicates that the Type 370
routine to execute the IORS instruction and
Light Pen has detected the presence of illumin-

9-3

check the states of the tape-reader and 'tape:reader-no-tape flags to determine which flag initiated the interruption. While the no-tape flag
is aI, the tape reader will not respond to lOT
selection; i.e., the reader is inhibited from reading tape lines. Momentarily depressing the FEED
button on the tape reader after loading a tape
for readin clears the no-tape flag.
Tape Punch No Tape - a I bit indicates that the
supply of unpunched tape in the internal magazine has been exhausted save for approximately
one inch. This length is adequate for the punching of several characters; it may be used also
for splicing purposes. This flag does not request
a program interruption. Users who desire to
make use of this flag must include an execution
of the laRS instruction and a test of the AC
contents prior to each selection of the paper tape
punch.
DECtape - a I bit indicates that the DECtape
flag and/or the error flag (both contained in the
TC02 DECtape control unit) are set. This flag
is interfaced to the program interrupt control
to request program interruption when the flag
goes to the I state. The function of the DECtape and error flags are discussed in the des-cription of the Te02 control (refer to chapter 5).

INPUT/OUTPUT SKIP FACILITY
The input/output skip (lOS) facility, as previously
shown in the program controlled transfer description, permits lOT instruction testing of those
device flags interfaced to it. Such an instruction
issues a unique device selection code and then
tests the state of the respective device flag. If
the flag is in the skip state (normally, the set
state), the processor is directed to increment the
contents of the PC by one and thus skip the
next instruction in sequence. If the flag is found
to be not set, the next instruction in sequence
is executed. The skip conditions for the various
peripherals offered with the PDP-9/L are presented in the lOT instruction descriptions for
these devices (refer to chapters 4 and 5).

Mnemonic

Octal Code

Function

ION
IOF

700042
700002

Enable the PI
Disable the PI

The PI is automatically disabled when an inter-·
rupt is granted or when the I/O RESET key
(Console) is depressed. The PI is temporarily
inhibited while the automatic priority interrupt
system is processing a priority interrupt request
The PIE indicator (console) is lighted while the
PI is enabled.
A program interrupt is granted at completion of
the current instruction (lOT and XCT instructions are exceptions)* provided that the PI is
enabled and no I/O action of a higher priority
is in progress. At the grant of the interrupt,
the program in progress "traps" to memory location 00000. This location stores the following
data (see figure 9-2 for the storage format):
1. The content of the link register.
2. The contents of the I3-bit PC (or the
IS-bit extended PC, if the Type KG09A Memory Extension Control has been included in
the system due to memory expansion).
3. The state of the extend mode (on or off)
if the KG09 A option is present.
4. The state of the memory protection mode
(on or off) if the Type KX09A Memory protection option is present.
If the options are not present, the respective bit
positions of location 00000 remain zeroed. Following the storage action, the extend mode and
the memory protection modes are turned off,
and the instruction stored in location 0000 I is.
executed. This instruction is an enter extend
mode (EEM) instruction (see chapter 6) that
re-enables the extend mode. Immediately thereafter, the instruction in location 00002 is executed. This instruction is a JMP I (indirect address
to allow addressing of any memory bank)**;

PROGRAM INTERRUPT CONTROL
The program interrupt (PI) facility, when enabled
by the program, relieves the main prJgram of the
need for repeated flag checks by allowing the
ready status of I/O device flags to automatically
cause a program interrupt. The program interrupt (PI) control is enabled or disabled by programmed instructions. The following lOT instructions provide for control of this facility:

9-4

*An lOT or XCT instruction prohibits interrup··
tion of the sequence of it and the instruction
immediately following it.
**Both actions (the EEM and JMP I instnlction
execution) assume the presence of expanded
memory and enabled API.

*
4

L
L -_ _ _ _ _ _....
L - -_ _ _ _ _ _ _ _.
- ..

17
}

PC CONTENTS (RETURN ADDRESS)
STATE OF MEMORY PROTECTION MODE
STATE OF EXTEND MODE

LINK CONTENT

* ZERO IF RESPECTIVE OPTION IS NOT PRESENT
Figure 9-2

Program Interrupt, JMS Instruction, or CAL Instruction
Storage Word Format*
LAC ACSAV
fRESTORE AC
hence, core Inemory address 0000 1 must deterION
fTURNS ON PI
mine which device requested an interrupt. The
DBR
fPRIMES SYSTEM TO RESTORE L,
fPC SAVED MODES AT JMP I TIME
interrupt routine interfaced to the PI will service
JMP I 0
fRESTORES SYSTEM TO STATUS
that device. Where multiple devices are interfAT TIME OF INTERRUPT
faced to the PI, the subroutine accessed by the
The DBR (debreak and restore) instruction (octal
JMP I instruction must execute a flag search to
code 703344) is an lOT instruction which sets
determine which device initiated the interrupt
up
the system to restore the Link, PC, extend
request. Although the PI is not priority oriented
mode, and memory protection mode to their sta(Le., the interrupt request line accepts the inclutus at the time of the program interruption;
sive OR of all device request flags), the order
DBR
must immediately precede the JMP I inin which the search routine tests the device flags
struction. The DBR instruction is fully described
does establish a priority sequence of service.
in the discussion of the automatic priority interrupt system, but is implemented on all PDP-9/L's.
Several factors must be considered in the use of
the PI. First, althoug the PI does automaticIf only one device is connected to the PI facility,
ally save the Link, the PC, etc. to facilitate rescontrol can be transferred directly to a
program
toration of the interrupted program at compleroutine
that
services the device when an interrupt
tion of interrupt service, it does not provide
occurs.
This
operation occurs as shown in examfor the saving of the contents of other active
ple 1.
registers. Thus, interrupt-accessed service subroutines should begin with instructions to temIn most PDP-9/L systems numerous devices are
porarily preserve the contents of any registers
connected to the PI facility, so the routine bethat may be used by the subroutines.
ginning in core memory address 00001 must determine which device requested an interrupt. The
interrupt routine determines the device requiring
service by checking the flags of all equipment
Secondly, the PI must not be enabled by exconnected to the PI and transfers program conecution of the ION instruction until the exit
trol to a service routine for the first device enfrom the subroutine. If this precaution is not
countered that has its flag in the state required
observed, a second interrupt request could be
to request a program interrupt. In other words,
granted before the current subroutine is comwhen program interrupt requests can originate in
pleted. The resultant overwriting of location
numerous devices, each device flag connected to
00000 when the latter request traps to this
the PI should also be connected to the lOS.
location will destroy the previously saved data
The program (example 2) illustrates how the
and, hence, prevent restoration of the interrupted
program interrupt routine can determine which
main program. Normally, interrupt requests
device is requesting service (this routine assumes
made during current service of an interrupt rememory and active API).
expanded
main on-line and are answered when the current
interrupt service terminates provided the delay
*PI interrupt turns off extend mode and memdoes exceed device limitations. The third and
ory protection mode. API interrupt and execufinal factor requires that interrupt-accessed
tion of CAL instruction turns memory protection
subroutines terminate with the following instrucmode off; extend mode is not affected.
tion sequence:

9-5

Example 1:
~

Address

Remarks

01000
01001
01002
00000
00001*
02000

SR,

03001
03002
03003
01003
01004

JMP SH
ION
DBR
JMP I 0000

/MAIN PROGRAM
/MAIN PROGRAM CONTINUES
/INTERRUPT REQUEST OCCURS
INTERRUPT OCCURS
/PROGRAM COUNT, ETC ARE STORED IN 00000
/ENTER SERV1CE ROUTINE
/SERVICE SUBROUTINE FOR INTERRUPTING
/DEVICE
/TURN ON INTERRUPT
/RETURN TO MAIN PROGRAM
/MAIN PROGRAM CONTINUES

*Note: This routine illustrates PI programming for a PDP-9/L system without
expanded memory and API.

Example 2:
Address

Instruction

01000
01001
01002

/MAIN PROGRAM
/MAIN PROGRAM CONTINUES
!INTERRUPT REQUEST OCCURS
INTERRUPT OCCURS
/STORE PC, LINK, ETC.
EEM
/ENTER EXTEND MODE
JMP I 00003
/ENTER ROUTINE
101' 3401
/SKIP IF DEVICE 34 IS REQUESTING
JMP SR 34
/ENTER SERVICE ROUTINE 34
101' 4401
/SKIP IF DEVICE 44 IS REQUESTING
JMP SR 44
/ENTER SERVICE ROUTINE 44
101' 5401
/SKIP IF DEVICE 54 IS REQUESTING
JMP SR 54
/ENTER SERVICE ROUTINE 54

00000
00001
00002
FLGCK,

00003, FLGCK

AUTOMATIC PRIORITY INTERRUPT
The API option, Type KF09A, adds eight additional levels of programming priority to the
PDP-9/L. The upper four levels are assigned to
I/O devices and are initiated by flags (interrupt
requests) from these attached devices. The
lower four levels are assigned to the programming
system and are initiated by software requests.
The priority network insures that high data rate
or critical devices assigned to high priority levels
will always interrupt slower device service routines while holding still lower priority interrupt
requests off line until they can be serviced. The
API also identifies the cause of the interrupt
directly, eliminating the need for the service
routines to flag search.
The key elements in the API are priority level
and channel. Each I/O device in a PDP-9/L
system is assigned to one of the 4 hardware
API priority levels or to the program interrupt
facility so as to maximize performance of the
entire I/O systenl. The channel assignment
(API provides for 32) of every device is fixed
and cannot be changed.
The API operates in the following manner.
An I/O device requests service by transmitting
an interrupt request signal to the processor on
9-6

Remarks

a line corresponding to its specific, preassigned
priority level. If this priority level is higher
than the priority of the device which requested
a currently active program segment, an interrupt
is granted to the new device. Upon receipt of
the grant signal, the device transmits its channel address back to the processor. The processor executes the instruction in the specified
memory address; this is always a JMS (or JMS 1)*
to the device service subroutine. The new
priority level is remembered and no further
acceptance of requests on this or lower priority
levels is permitted until the device service subroutine is exited.
The hardware insures that simultaneous requests
by multiple devices are handled in the proper
priority sequence. If interrupt requests occur
at different priority levels, the highest priority
request will be serviced first .. If multiple interrupt requests occur at the same priority level,
the device closest on the bus to the processor
will be serviced first. The entire API system may
be enabled or disabled with a single instruction,
however, many devices provide facility to

------------------------------------,-----*The indirect address permits access of a subroutine stored in a memory bank other than
bank O.

separately connect and disconnect their flags
from the interrupt.
The major advantage of this API system lies
in the proper use of the software levels. In
the real-time environment, it is necessary to
maintain data input/output flow, but it is not
possible to perform long, complex calculations at
priority levels which shut out these data transfers. With the API, a high priority data input
routine which recognizes the need for the
complex calculation can call for it with a software level interrupt. Since the calculation is
performed at a lower priority than the data
handling, the latter can go on undisturbed.
Further, there is no need to interface the data
collection routine with the lowest priority (background) program which may run independently
of the real-time system. Since the priority juggling is handled by the hardware it is quite
efficient.
Priority Level
At any time, the computer is actually executing
instructions from one and only one program segment. However, if the program segment being
executed is the result of an interrupt (due to a
peripheral device flag), then both the interrupted
program and the interrupt service program can
be thought of as concurrently active. Such is
the case in the basic PDP-9/L when the normal
program interrupt facility (PI) is used. The API
options add 8 additional priority levels above the
two available (PI and main program) in the basic
computer. Thus, a total of 10 levels of priority
exist. Priority levels 0-3 are for hardware; levels
4-7 for software. Level 0 is the highest priority.
Each peripheral device attempts to interrupt at
a specific priority level. If there are no active
programs at that or higher priority levels, the
program segment in progress will be interrupted,
return information stored, and the new device
service routine entered. If there is a higher priority level program active, the device request is
ignored until the higher priority program segment
terminates. The high priority levels then go inactive and the requesting device is serviced.
A CAL instruction causes priority level 4 to be
activated after the CAL instruction is executed.
A break to level 4 will occur after all higher
priority level requests are honored.
Channels
Each peripheral device is assigned to a channel
independent of its priority level. The channel
assignment of a device defines a device service

subroutine entry point in the following manner:
When an interrupt is granted to a device, the
device transmits an address to the computer that
is simply related to its channel number. (Channel address = 40 8 + channel number). The assigned priority level flip-flop is turned on and
the instruction at the channel address is executed.
This is always a JMS to the device service subroutine.
There are 32'0 channels numbered 0-37a... with
corresponding core addresses of 40-77. Four
channels (40-43) are used for software priority
levels, leaving 28 for device use. Each of the
four hardware priority levels is multiplexed such
that up to eight devices (channels) may use it.
It is not possible to enable or disable an individual channel. Rather, the more sophisticated
I/O devices connected to the interrupt will have
the ability to enable or disable themselves from
their interrupt lines. Simple devices such as
the reader, punch, etc., will clear their flags to
disconnect, just as they disconnect from the
program interrupt.
API lOT Instructions
The instructions listed in table 9-1 are supplied
with the API option. Note that although the
DBR (debreak and restore) instruction appears
in this listing, it is a basic machine instruction;
hence, DBR may be used in PI-entered subroutines as well as in API-entered subroutines.
Dynamic Priority Reallocation
In order to most efficiently service real-time devices, the hardware includes provision for dynamic priority reallocation. There are three distinct methods.
1. Device dependent - Since channel and priority level are independent, a device may be designed to interrupt at any of several priority
levels without grossly affecting programming.
In a control application, the device could
raise its priority (under program control) when,
for example, the data rate increased. In this
case the device would make use of more than
one device priority level.

2. Program generated service requests - The
program may generate interrupt requests on
any of the four software priority levels. If
the priority level of the request is below an
active priority level, the request will (eventually) be serviced when the higher priority
active levels are dismissed. If the priority
level of the request is above all active levels,
9-7

TABLE 9-1

API lOT INSTRUCTIONS

Mnemonic
Symbol

Octal
Code

SPI *

705501

Skip on priorities inactive. The next instruction is
skipped if any AC bit is set and the corresponding API
condition is true (see table 9-2).

ISA*

705504

Initiate selected activity. The API activity specified by
a set bit in the AC is initiated (see table 9-3).

DBK

703304

Debreak. This instruction is used to release the highest
active priority level. Its use is to return a subroutine's
priority to the normal assignment after the requirement
for an interim ISA-initiated raising of priority has been
satisfied. DBK should not be used to terminate a subroutine as it does not provide for restoration of the PC,
Link, etc.

DBR

703344

Debreak and restore. In addition to releasing the active
priority level, this instruction primes the PDP-9/L to restore the Link, the PC (or EPC), the extend mode, and
the memory protect mode to their status at the time of
interruption. The actual restoration occurs at the execution of the JMP I instruction exiting the subroutine .
DBR must immediately precede the JMP I instruction.
Where DBR is used in subroutines not entered by API
action, the debreak operation has no significance.

RPL

705512

The priority levels are read into the AC according to the
bit usage shown in table 9-4. AC bits 2-9 indicate the
presence of devices requesting service on levels 0-7. AC
bits 10-17 indicate those priority levels that are active.
(A. level becomes active if service at this level has commenced, or if a raise priority level instruction (ISA) has
been executed initiating activity on a higher level.)

Function

*Programming Note: normally, the SPI and ISA instructions are combined (microcoded) to first
test that the program segnlent currently in progress is not already at the requested priority level and then if not, to initiate a raising of priority to the requested level. Hence, if a program
segment cannot raise its priority, the segment must be already at the requested level or higher.
The ISA instruction cannot be used to lower the priority level of an active program segment.
The hardware will not recognize the priority change.
the request will be serviced immediately. The
instruction OMS) in the software priority
level channel will be executed, storing the current program counter and entering a new program segment.
Programmed priority changes - In order
for an interruptable program to change parameters in an interrupt service subroutine, the
priority interrupt system is normally turned
off while the changes are affected. Unfortunately, all interrupts are shut out during this
time including those that indicate machine
errors or are vital to control real-tinIe processes. Thus, the API has been designed
so that a program segment may raise its
priority only high enough to shut out those
devices whose service routines require changes.
3.

9-8

The method of raising priority and lowering
it requires minimum possible time. By issuing
the ISA instruction with the proper bits set
in the accumulator the priority of the currently active program segment is raised. No instruction in a channel is executed. The program merely continues on at its higher priority
level. To restore the program segment to its
original priority level, a DBK instructi.on is
issued.
For example: a priority 2 routine is entering
data in memory locations A through A + 10;
but, based on a calculation made by a priority 6 routine, it becomes necessary to move
the data to memory locations B through
B + 20. The changes in the routine at level
2 must be completed, without interruption,

TABLE 9-2

STATUS BITS ASSOCIATED WITH THE SPI INSTRUCTION
Function

AC Bit

API enable (system is preesntly enabled if 1, disabled if 0)
Unused

Unused

Priority level 0 inactive, hardware*

Priority level 0 and 1 inactive, hardware

Priority level 0-2 inactive, hardware

Priority level 0-3 inactive, hardware

Priority level 0-4 inactive, software

Priority level 0-5 inactive, software

Priority level 0-6 inactive, software

Priority level 0-7 inactive, software**

*Highest priority.
**Lowest priority.

once they are started. This is possible by the
level 6 program raising itself to level 2 (devices on the same or lower priority may not
interrupt), completing the change, and debreaking back to level 6.
Programming Examples
Input 10 Words from AID Converter - A service
routine INAD has been written to input 10
words to a FORTRAN array for later processing.
The core location of the AID channel contains
a JMS INAD. The basic components of INAD
are:

INAD,

DAC SAVAC
lOT

lOT
LAC SAVAC
DBR
JMP I INAD

/ENTRY POINT
/SAVE AC
/READ A/D BUFFER
/STORE IN ARRAY
/TEST FOR LAST WORD - IF
/YES, INITIATE SOFTWARE
/INTERRUPT TO ACCESS DATA
/FORMATTING SUBROUTINE
/ELSE, START NEXT CON/VERSION
/RESTORE AC
/DEBREAK AND RESTORE
/RETURN

The program segment to start the conversion
would look as follows:

9-9

TABLE 9-3

CONTROL BITS ASSOCIATED WITH ISA INSTRUCTION
Function

AC Bit

o
1

API enable (enable API system if bit is aI, disable system if
bit is a 0).
1
AC BIT
For paper tape reader
1
2
Reader priority level
o 0
2
o
1
1
1
0
0
1
1
Remove PTR from API

Unused

Request interrupt at priority level 4

Request interrupt at priority level 5

Request interrupt at priority level 6

Request interrupt at priority level 7

Raise priority to priority level 0

Raise priority to priority level 1

Raise prioirty to priority level 2

Raise priority to priority level 3

Raise priority to priority level 4

Raise priority to priority level 5

Raise priority to priority level 6

Raise priority to priority level 7

,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

lOT

/INITIALIZE INAD
/SELECT CONVERTER FOR
/FIRST CONVERSION
/CONTINUE WITH PROGIRAM

If IN AD were active, one could instruct it to in-

put an additional 10 words with the following
segment:
LAC ()
ISA

DBK

/CONTROL WORD
/RAISE PRIORITY TO
/LOCK OUT INAD
/CHANGE I NAD
/PARAMETERS
/RESTORE PRIORITY TO
/ORIGINAL LEVEL

Simulation of Hardware Interrupt - A hardware
interrupt may be simulated by
LAC ()
ISA
JMS INAD

9-10

/CONTROL WORD
/RAISE TO HARDWARE PRIOR
/PRIORITY
/ENTER INAD

Use of Software Levels - The organization of a
program on 5-levels might be as follows (in order of decreasing priority).

Interrupt level 0 - highest priority alarm conditions, computer or process lnalfunction
Interrupt level 1 - control process A/D-D/ A,
sense and control input/
output routines
Interrupt level 3 - Teletype I/O routines for
operator interface, operator
can inquire or demand
changes as required.
Interrupt level 4 - FORTRAN subroutines to
(Software)
calculate process control in-

TABLE 9-4 STATUS BITS ASSOCIATED WITH THE RPL INSTRUCTIONS
AC Bit

Function
API enabled
Unused

Device requesting service on priority level 0

Device requesting service on priority level 1

Device requesting service on priority level 2

Device requesting service on priority level 3

Device requesting service on priority level 4

Device requesting service on priority level 5

Device requesting service on priority level 6

Device reguesting service on priority level 7

Priority level 0 active

Priority level 1 active

Priority level 2 active

Priority level 3 active

Priority level 4 active

Priority level 5 active

Priority level 6 active

Priority level 7 active

Interrupt level 4 - put/output data. Direct
(continued)
digital control routines.

Main Program

- lowest priority-operator interface programming, requested readouts, etc.

Queueing
High priority/high data rate/short access routines
cannot perform conlplex calculations based on
unusual conditions without holding off further
data inputs. To perform the calculations, the
high priority program segment must initiate a
lower priority (interruptable) segment to perform
the calculation. Since, in general, many data
handling routines will be requesting calculations,
there will have to be a queue of calculation jobs
waiting to be performed at the software level.
Each data handling routine must add its job to

the appropriate queue and issue an interrupt request (ISA instruction) at the corresponding software priority level.
DATA CHANNEL TRANSFERS
The data channel control offers a relatively highspeed data path (via the I/O bus) for the transfer of data in blocks between core memory and
high data rate devices, such as DECtape and standard magnetic tape transports. The data channel
control can service up to eight devices. The
priority of service is established by the physical
order in which the devices are interfaced to the
I/O bus.
Device requests for data channel transfer action
are honored at completion of the current instruction, provided that such completion is interruptable; i.e., the current instruction cannot be an
lOT instruction or an XCT instruction. Each

9-11

type prohibits interruption of the instruction sequence until the instruction which immediately
follows the current instruction (and which is not
itself an lOT or XCT instruction) completes its
execution. A data channel request made during
the current instruction has priority over an API
or PI request made during the same interval. An
in-process data channel transfer cannot be interrupted. Device requests for data channel transfer action which occur during an in-process data
channel transfer will be honored at completion
of the current channel operation on the basis of
their priority relationship; i.e., a higher priority
device will be serviced immediately while the
lower priority device or devices wait for service.
A data channel device functions with processorgranted program breaks to interleave its data
transfers with execution of the program in progress. These breaks suspend rather than interrupt
the program's execution. The transfers are made
via the MB and do not disturb the contents of
other active registers in the processor (AC, PC,
etc.). Data is read into memory in three n1achine
cycles and out of memory in four cycles (the
additional cycle allows I/O bus settling and the
setting of control gates prior to the strobing of
the data into the device's buffer register). The
maximum data rate capacity of the data channel
control lies between 160,000 and 220,000 words
per second, depending on the mix of input and
output transfers.
Each data channel device is associated with a
unique pair of memory locations which function
as a word counter (WC) register and a current
address (CA) register for controlling data transfers made to and from the device. These registers must be initialized by the program prior
to the device request for data transfer action.
The register (memory location) assignments for
the four standard data channels are as follows:

Data Channel

o
1
2
3

4-7

WC (octal)

CA (octal)

30
32
34
36
Not Assigned

31
33
35
37

PDP-9/L systems programs presently provide for
the assignment of DECtape to data channel 0
and the assignment of standard magnetic tape
to channel 1 (refer to chapter 5 for discussions
of these devices).
The 'WC register (whose memory address must
be even and the lower numerical quantity of the
9-12

data channel pair) is initialized to contain the
number of words to be transferred; this number
must be entered in 2s complement notation, as
the WC counts up towards zero and indicates by
the all-zero condition that the transfer has been
completed. The CA register is initialized to contain the starting address minus one of the sequential block of memory locations which are
to deliver data or receive data from the device.
When the processor honors a data channel request, the respective device transmits the address
of its assigned WC register. During the first cycle of the channel transfer, the contents of the
WC are incremented by one and the address of
the CA register is established. In the second cycle, the contents of the CA are increlnented by
one to establish the effective address of the
memory location delivering or receiving the data
word. During the third cycle, or fourth cycle in
the case of out transfers, the actual data trans··
fer occurs.
The device normally continues to request data
channel service until the WC overflows (goes to
all-zeros), indicating that the initialized number
of data words will have been transferred at the
completion of the current data channel action.
A signal sent to the device at this time TIl1ay
be used to initiate API or PI access of a subroutine for the purpose of again initializing the
channel's WC and CA registers. * Because the
block transfers are primarily automatic in nature,
the programmer need only concern himself with
providing the appropriate subroutines to ;lnitialize the data channel WC and CA registers and to
initiate the device request for data channel service.
Since Data Channel requests are only honored at
completion of instructions, the type of instruction in progress determines the waiting time until the interrupt is granted.. The following considerations apply.
1. The lOT instruction and subsequent instruction are noninterruptable. The interrupt
request will be honored at the completion of
the instruction which follows the lOT.

2. The EAE instructions delay interruption
until they complete. This may be as long as
17 microseconds.
3. The XCT instruction is noninterruptable.
The interrupt request will be honored at the
*The "overflow" signal normally shuts down the
device to prevent further transfer requests until
WC and CA are re-initialized.

completion of the instruction referenced by
the XCT.
4. Lower priority channel-interfaced devices
wait for the completion of data transfers on
the requesting higher priority channel. Hence,
if four requests come up simultaneously, the
lowest priority device may wait 12 microseconds.
Long XCT chains on sequential lOT instructions
can lock out channel requests for indeterminate
periods of times. These should be avoided in
programs operating devices requiring fast response
to their requests. EAE instructions requiring
more than 12 microseconds are uncommon but
possible. Unfortunately, requests tend to stack
up during these waiting periods so that lower
priority devices may wait even longer.
ADD-TO-MEMORY CAPABILITY
When the Increment MB (memory) capability is
used, the device data register is gated to the
address lines using the ENA (1) level generated
by aWl 04 module (see figure 14-2). A break
is initiated in the usual manner by the WI 04
module. The ENA (1) level from this module
should be used, through an inverter, to ground
the INC MB control line. The overflow pulse
I/O OVFLO should be gated with ENB (1) to
produce a control pulse for the device indicating that a location has been incremented to
zero.
A device utilizing the add-to-memory capability
is cunne~tcd to the DCH in the normal manner.
The word count memory location is specified
by the device and gated to the address lines

by the WI 04 module. The data to be added is
gated onto the I/O data bus in the usual fashion
(see figure 14-3) with IOP2 during the CA cycle.
ENB (1) is used to request both READ RQ and
WRITE RQ. If there is an add overflow, a
pulse, DATA OFLO, (200 nano, -3v) comes back
on I/O bus line A27E. If desired, the sum may
be gated into an external register with IOP4 during the DATA cycle.
REAL-TIME CLOCK
The real-time clock produces clock pulses at the
rate of one every 16.7 msec (or every 20 msec
for 50 Hz powered systems). While the facility
is enabled, each such pulse occurrence initiates
a request for a program "break" at the completion of the current instruction. At the grant
of the break, the contents of the clock counter
register (memory location 00007) are incremented
by one. This register is program initialized to
contain the 2s complement of the desired number of clock pulses. Clock breaks continue to
be requested until the register overflows (i.e.,
reaches the all-zeros condition). At this time,
the clock flag is set to initiate interruption of
the program in progress. The clock flag is interfaced to the program interrupt control and to
the API system if the latter is included in the
PDP-9. The real-time clock facility's incrementing of the clock register functions like a one
cycle data channel transfer; i.e., at the break,
the contents of 00007 are extracted, incremented
and then rewritten in the same location, all
within one cycle. Hence, the restrictions of
"current instruction" apply here also.
The lOT instructions which are provided for use
with the clock are listed in table 9-5.

TABLE 9-5 CLOCK 10T'INSTRUCTIONS
Mnemonic
Symbol

Octal
Code

CLON

700044

Clock 011. The real-time clock's incrementing of
location 00007 is enabled and the clcok flag is
cleared.

CLOF

700004

Clock off. The clock's incrementing of location
00007 is disabled and the clock flag is cleared.

CLSF

700001

Skip on clock flag.

Function

The next instruction is skipped.

9-13

The eLK switch (console) must be in the down
position to permit programmed control of the
facility. In the up position, the facility remains
disabled. Depressing the I/O RESET key (console) disables the facility and clears the clock
flag.

9-14

While the facility is enabled, requests for clock
breaks have priority of acceptance over API and
PI requests. The first clock break may occur at
any time up to 17 msec after the facility has
been enabled. Subsequent breaks occur at the
clock rate (60 or 50 times per second).

CHAPTER 10
CONTROLS AND INDICATORS
OPERATOR CONSOLE

Table 10-1 details the functional use of items on
the control console. Indicators on the panel
show the existing binary states of specific register bits and control flip-flops by being lighted
for binary 1s and being extinguished for binary Os.
The operator console can be electrically locked
by a control on the marginal-check panel to prevent undesired alteration of the program in progress. While the console is locked, operation
of any switch, etc., will not affect the system.

The PDP-9/L operator console (figure 10-1), an
integral part of the main computer frame, includes a work shelf and a control console equipped with rocker switches, rotary switches, and
indicators for operator control and monitoring
of system operation. Typical console uses are:
Manual entry of instruction and/or data; start/
stop/ continue control of program execution.

MARGINAL CHECK PANEL

Stepping through a program sequence by instruction or by machine cycle for debugging
or maintenance purposes.

The marginal check panel (figure 10-2) is concealed behind the red hinged panel on the
front of the central processor. Table 10-2 details the functions of the panel-mounted controls
and indicators.

Visual examination of register contents and/or
of system status.

PS ACTIVE

EMA
3

M;MORY EXT;'NSI~N
[PC E CXD

EM
4

DCH
eK

eLK

API

PIE

SING
STEP

SING
INST

REPT

blNK

MEMORY PROTECTION
PRVN NEX'" USMD
8#3 SR4
BR5

EMIR

c::==t'----__

BR6

SR7

---IJLI_ _ _..,.jL_ _ _.....Jl.-_ _----J

INST REG
PRGM
STOP

15 ADDRESS SWITCHES

18 DATA SWITCHES

Figure 10-1. PDP-9/L Operator Console
10-1

TABLE 10-1

OPERATOR CONSOLE CONTROLS AND INDICATORS

Name

Function

START and START HOLD switches

Depressing START starts program execution at the location specified
by the ADDRESS switches. The START HOLD switch is used for
maintenance purposes.

10 RESET switch

Two positions: off (center) and operate (down, spring-loaded retu:rn).
Depressing switch generates the CAF (clear all flags) instruction to clear
all I/O device flags, clears the AC, MQ, and the link, turns off the
real-time clock, program interrupt facility, and API system and disables
the memory protection and extended memory modes.

STOP switch

Two positions: off (center) and operate (down, spring-loaded return).
Operate halts program execution at completion of the current instruction.

CONT and CONT HOLD switches

Depressing CONT resumes program execution from the point at which it
stopped. The CONT HOLD switch facilitates use of the REPT (repeat)
function for the single instruction and single step provisions.

EXAMINE THIS and EXAMINE NEXT
switches

Depressing the EXAMINE THIS switch transfers the contents of the
memory location specified by the ADDRESS switches from memory to
the MB. Mter the transfer, the contents of the ADDRESS switches
appear in the AR as the address of the memory location examined.
Depressing the EXAMINE NEXT switch increments the contents of the
AR by one and transfers the contents of the newly addressed memory
location from memory to the MB. EXAMINE NEXT facilitates monitoring of sequential memory locations as the ADDRESS switches need
only be set to the lowest memory location. The use of EXAMINE
THIS t.ransfers the contents of this location to the MB and enters
the lowest order address in the AR. Thereafter, use of EXAMINE
NEXT step advances the addresses through the sequential memory
locations.

DEPOSIT THIS and DEPOSIT NEXT
switches

Depressing DEPOSIT THIS switch deposits the contents of the DATA
switches in the memory location specified by the ADDRESS switches.
After the transfer, the contents of the ADDRESS switches appear in
the AR as the address of the memory location in which the data was
entered.
Depressing the DEPOSIT NEXT switch increments by one the AR
contents, and deposits the contents of the DATA switches in the memory location specified by the new address. DEPOSIT NEXT facilitates
the entering of data and/or instruction words in sequential memory
locations as the ADDRESS switches need only be set to the lowes,t order
address.
The DEPOSIT THIS function deposits the DATA switch word in this
location and transfers the address to the AR. Thereafter the DEPOSIT
NEXT function step advances the addresses through the sequential memory locations.

READ IN switch

Two positions: off (center) and operate (down, spring-loaded return).
Depress switch to initiate readin of paper tape punched in binary code
(each set of three 6-bit lines read from tape forms one 18-bit computer
word). Storage of words read in begins at the memory location specified by the ADDRESS switches. At the completion of tape readin, th(~
computer reads the last word from core memory and executes it. Readin occurs at the selected repeat speed.

-------------------------------------------------------------------------.-

10-2

TABLE 10-1

OPERATOR CONSOLE CONTROLS AND INDICATORS (continued)

Narne

Function

REPT (repeat) control and System
ON-OFF switch

With REPT switch and CONT HOLD up, the control establishes one of
four speeds at which single-step or single-instruction operations repeat
without operator intervention. The repeating speeds range from approximately 40 microseconds (position 1) to 8 seconds (position S).

Eleven-position switch: Each position interrogates a specific register and
displays its contents in the REGISTER DISPLAY indicators. REGISTER
DISPLAY indicators display the contents of selected register only when
machine is stopped. Moving selection switch while program is running
has no effect. The functions of the positions are as follows:
RDR

Display contents of the .paper tape reader information buffer.

TTl

Display contents of the teleprinter keyboard information
buffer.

STAT

Display status of flags for I/O devices connected to status
reading facility of I/O system (see figure 9-1 for standard
status bit assignments).

API

Display activity of automatic priority interrupt system's
four device-oriented priority levels.

DPY

Display 34 display x, y buffers. The x buffer is displayed
in the nine most significant REGISTER indicators; the y
buffer is displayed in the nine least significant indicators.
The least significant bit of each buffer is not displayed.

lOA

Display IS-bit address word present on address lines of
I/O bus for data channel and API operation.

lOB

Display I8-bit data word present on data lines of I/O bus
for program controlled and data channel data transfers.

Display contents of the AC.

Display contents of the AR.

Display contents of the PC and status bits as stored during
this instruction.

Display contents of the MQ.

PRTC switch and indicator

The up position causes the memory protection mode to be entered by
operation of the START switch. In either position, the mode may be
enabled or disabled by program control. While the console is locked,
the switch is electrically in the down position, regardless of its actual
position. The indicator is lit while the mode is in effect. (Memory
protection is a system option.)

EXD switch and indicator 1

The up position causes the extend .mode of addressing to be entered
by operation of the START switch. In either position, the mode may
be enabled or disabled by program control. While the console is locked,
the switch is electrically in the down position, regardless of its actual
position. The indicator remains lit while the mode is in effect. (Extend
mode is a system option.)

CLK switch and indicator

The up position disables the real-time clock facility. The down position
allows program control to enable or disable the clock. The indicator
remains lit while the clock is enabled. While the console is locked, the
switch is electrically in the down position, regardless of its actual position.

10-3

TABLE lO-1

OPERATOR CONSOLE CONTROLS AND INDICATORS (continued)

N arne

Function

SING STEP indicator and switch

The indicator lights when the associated switch is up. This enables
the single-step mode which halts program execution at each machine
cycle. Repetitive depressing of the CONT HOLD switch, while the
mode is enabled, steps the program through the sequence one cycle
at a time. When the console is locked, this switch is disabled.

SING INST indicator and switch

The indicator lights when the associated switch is up. This enables
the single instruction mode which halts program execution at completion
of each instruction. Repetitive depressing of the CONT HOLD switch,
while the mode is enabled, steps the program through its sequence one
instruction at a time. When the console is locked, this switch is disabled.

TTYH/TTYF switch

Determines whether teletype operation is half or full duplex.

REPT indicator and switch

The indicator lights when the associated switch is up. This enables
the repeat function. This function causes operations initiated by
actuation of CONT HOLD, EXAMINE NEXT, or DEPOSIT NEXT
switches to repeat while the key remains in an operator position. The
repeat speed control establishes the rate of repetition.

ADDRESS switches (0-17)

Establish a I8-bit core memory address to be entered in the PC by
operation of the START switch, or in the AR by operation of the
EXAMINE THIS or DEPOSIT THIS switch. Switch is placed up for a
1 bit and down for a 0 bit. The 18 switches to the right (0-17) set
up the: address of a location within an 8192-word memory block. The
two switches to the left (0 and 0) are for extended memory addressing
of locations, in up to three other 8192-word memory blocks of the
system.

DATA switches

Establish an I8-bit data or instruction word to be read into memory by
DEPOSIT THIS or DEPOSIT NEXT operation, or to be entered in the
AC by a programmed LDS (load DATA switches) instruction. Up
position of the switch is a binary 1; down position is a binary O.

PRGM STOP indicator

Lights when the "run" flip-flop has been cleared to stop program
execution.

INST REG

The five indicators reveal the contents of the IR, being lit for 1 bits
and extinguished for 0 bits, to show the operation code of the instruction just executed or in progress, and indirect address occurnmce.

DCH BK

Lights to indicate that data channel activity is in progress; i.e., data
is being transferred between core memory and a data channel I/O device via the I/O bus.

PS ACTIVE indicators

Each indicator, relating to one of the API system's eight priority levels ~
individually lights to show the priority program interrupt request currently being serviced. Indicators 0, 1, 2, and 3 show activity resulting
from device-initiated requests; indicators 4, 5, 6, and 7 show activity
resulting from program-initiated requests. The priority levels for each
set decrease'in rank from left to the right with any device request hav-,
ing higher priority than any program request.

PIE indicator

Lights when the PI system has been enabled by program control.

API indicator

Lights when the PI system has been enabled by program control.

LINK indicator

Shows the content of the link register.

MEMORY BUFFER indicators

Shows. the contents of the MB register.

10-4

LEGEND:
1. Marginal-check voltmeter
2. Marginal-check voltage
control
3. Maintenance switch
4. Marginal-check selector
switch
5. Elapsed-time meter

Figure 10-2. Marginal-Check Panel

10-5

TABLE 10-2 MARGINAL CHECK PANEL CONTROLS AND INDICATORS

Function

Name
Marginal-check voltmeter
(1, figure 10-2)

Indicates the selected voltage output of the marginal check power supply.
The ,center of the scale relates to the reference voltage slected, either
+10 or -15 volts dc. Movement of the pointer to the right indiGates
an increase in magnitude for the marginal check voltage.

Marginal-check voltage control
(2, figure 10-2)

Establishes the marginal check voltage level of the selected output.
Voltage is increased with cw rotation.

Maintenance switch
(3, figure 10-2)

Five positions:
LOCK - electrically locks the control console. With the console in th,~
locked condition, operation of any console con trio cannot affect the
program in progress.
NORMAL - Control console is not locked; all controls may be used.
MAIN - With the switch in this position and the REPT switch (I;ontrol
console) in the up position, the built-in maintenance test program circulates a self-incrementing count through all active CPU registers to
verify both their operation and the internal transfer paths. The program
proceeds at the rate selected by the repeat speed control (control console ).
EXAMINE - simulates the "examine" function. With the switch in this
position, the CPU responds as if the EXAMINE THIS switch (control
console) was being actuated at the rate selected by the repeat speed
control (control console). With the REPT switch in the down (inopeJative) position, each movement of the selector switch to position
EXAMINE simulates an actuation of the EXAMINE THIS switch.
DEPOSIT - Simulates the "deposit" function. With the switch in this,
position and the REPT switch (control console) in the up position,
the CPU responds as if the DEPOSIT key was being actuated at the
rate selected by the repeat speed control (control console). With
the REPT switch in the down (inoperative) position, each movement
of the selector switch to position DEPOSIT THIS simulates an actuati.on
of the DEPOSIT THIS switch.

Marginal-check selector switch
(4., figure 10-2)

Three positions:
OFF - center

+10 MC - selects the +1O-bolt output of the marginal check power
supply.
-15 MC - selects the -IS-volt output of the marginal check powt~r
supply.
Elapsed-time meter
(5, figure 10-2)

10-6

Indicates, to the nearest tenth of an hour, the cumulative number of
hours in which the system has been in the "power on" state. Meter
counts from 00000.0 to 99999.9.

CHAPTER 11
INTRODUCTION TO INTERFACING

GENERAL

CIRCUIT MODULES FOR INTERFACING

PDP-9/L offers a complete line of standard peripheral equipment and compatible interface controls. Selections from this line may be appended to a PDP-9/L system at any time without
modification of the central processor unit.
Where applications require that the system operate special purpose equipment ·or user-designed
external devices, the PDP:"9/L I/O control scheme
affords simple and economical implementation
of the necessary interfacing.

The following FLIP CHIP circuit modules are
typical of those recommended for use in fabricating device interfaces compatible with the
PDP-9/L I/O facilities. Their input, output, and
power requirements are as specified in the
"Digital Logic Handbook".

This section contains information of interest to
the interface designer. It describes the PDP-9/L
I/O facilities and defines the requirements for
interfacing a device to them. The information
presented includes: definitions of signal characteristics; timing relationships; and, where appropriate, schematic representations of typical
interfaces configured from Digital's line of inexpensive FLIP CHIP hybrid integrated circuit
modules. The PDP-9/L is designed to be compatible with the 2 mHz, R series FLIP CHIP
modules.
Complete descriptions of all standard FLIP CHIP
modules, compatible power supplies, and hardware (mounting panels, cables, etc.) can be
found in the "Digital Logic Handbook", sent
free of charge upon request to any of the Corporation's local offices. Items are readily available for low cost fabrication of external devices
and/or special interface controls.
Customers are invited to consult Digital System
and Application Engineering personnel for assistance in the design of devices and interface
controls. Their knowledge of data processing
disciplines and their applied experience in answering industrial and scientific needs offer fast resolution of data handling problems.
Digital Equipment Corporation makes no representation that the interconnection of its circuit
modules in the manner described herein will not
infringe on existing or future patent rights.
Nor do the descriptions contained herein imply
the granting of license to use, manufacture, or
sell equipment constructed in accordance therewith.

Type Number

Function Name
Inverter
Diode Gate
Flip-Flop
Flip-Flop
Flip-Flop, Dual
Flip-Flop, Triple
Flip-Flop, Quadruple
Flip-Flop, Dual
Device Selector
High Impedance Follower
Pulse Amplifier
Inverter

RI07
Rl23
R200
R201
R202
R203
R204
R20S
WI03
WSOO
W640
BIOS

LOGIC SYMBOLS
The symbols used to indicate logic circuits and
signals in the schematic illustrations included in
this manual are defined below.

Represents

Symbol

----1[>

•

---0
- -....
~..
~

Negative or negative-going
pulse.
Positive or positive-going
pulse.
Negative level.
Positive level.
Direction of flow.
ISv load resistor clamped at
-3v

I/O COMMUNICATIONS
The PDP-9/L offers facilities for communicating
with external devices by program control and
data channel. Devices using program controll~d
and data channel facilities interface to the I/O
bus cables. Program controlled transfers may
make use of direct, program interrupt (PI) or

11-1

automatic priority interrupt (API) access of subroutines.
The data rates, the latency times (i.e., the time
which a device Illust wait before its request for
service is answered), and the representative degrees of efficiency for the PDP-9/L modes of
I/O service are presented in table II-I. The
"direct" mode refers to program controlled trans-

TABLE 11-1

fers made to or from a single device without
interruption by other I/O facilities.
~hapter 12 describes the total I/O bus system
mterface. Subsequent chapters describe the interface requirements for use of the program controlled transfer mode (including use of the program interrupt control, input/output skip facililty,
input/output read status facility, and the auto··
matic priority interrupt option), and the data
channel transfer mode.

DATA TRANSFER RATES

,-------~;;::;""".:,.:....:-..;:.:.:.:..::..:-:.:.:.:.:~..:::.;:;..~~-------.-

Latency
(maximum/typical)

Mode

Data Rate
(maximum/typical)

Direct

100 kHz

25 kHz/l kHz

45 microseconds for
one device; 100+ microseconds for two devices/
100 microseconds

API

35 kHz/iO kHz

30 microseconds/50
microseconds (average
per channel)

DCH

250 kHz/50 kHz

20 microseconds/5
microseconds

25%

Efficiency
10%

------------------------------------------------------_.-

11-2

CHAPTER 12
THE I/O BUS
GENERAL

PHYSICAL DESCRIPTION

The PDP-9/L I/O bus consists of cables which
chain link all I/O device controls to a common
interface point at the central processor (figure
12-1). Each device control must have input
and output connector provisions to receive the
bus and pass it on to the next device. The bus
is the major I/O communication path for a PDP9/L configuration. It provides signal lines for
command and data transmissions arising from
programmed transfers, data channel transfers,
and operation of the multilevel automatic priority interrupt, program interrupt, I/O status read,
and I/O skip facilities.

Two cables of 36 two-wire pairs each comprise
the I/O bus cables. The ground sides of all
pairs are connected in common at the connectors. Female connector ends are used in device
controls; male connectors are on both ends of
the bus cables. The female connector is the
DEC Type H800, available in the DEC Type
1943 (FLIP CHIP) Mounting Panel. The connector may be purchased separately. Two such
connectors are needed for each device, one to
bring in the I/O bus and one to send it out to
the next device. Each such female connector
receives the two male connectors of the two I/O
bus cables.

FREE
STANDING
DEVICE

PROCESSOR

DEVICE C

1/0 BUS CABLES

TO NEXT
I/O DEVICE

Figure 12-1. I/O Bus Connections
12-1

Each I/O bus cable is a DEC Type BC09 cable
assembly; completed cables may be purchased.
The connectors have a special locking provision
which insures against accidental removal and,
.if properly strain relieved at each end, may be
conveniently run between free standing cabinets.
In free standing cabinet devices, the I/O connect0rs are located at the left (when viewed from
wiring side) end of the lowest 1943 Mounting
Panel. The "input" bus connector is to the
left of the output connector. In devices requiring only a few mounting panels, the "input"
bus connector is located at the lower left corner, the "output" connector at the upper lefthand corner.
I/O POWER
The device input I/O bus cable connector must
be supplied with -15 volts on each pin B. A
total of 600 ma is required. The output cable
connector need not be supplied with power.
INTERFACE SIGNALS
The following describes the function of all I/O
bus signal lines linking the central processor
with the external I/O devices. Electrical characteristics and line terminating requirements are
included. Figure 12-2 illustrates the interface.
Maximum total length of the I/O bus is 50 feet
(15.24 meters).
Data Lines
Eighteen data lines constitute the bidirectional
facility for transferring data in bytes up to 18
bits in length between the central processor and
all I/O devices. Transfers are made on a de
basis with the processor or device allowing bus
settling time before data on the lines is strobed
into the receiving register. The data lines convey
transfers between the AC and a selected device
buffer register for data channel operation. The
bidirectional characteristic requires that the device use unclamped collectors for data transmission to the processor. Emitter followers must
be used in a device for data reception to avoid
loading the bus on a dc basis. The data lines
are terminated in the central processor by I5-ma
clamped loads.
Output Control Signals
Seven output control signals are generated within the processor to effect specific functions in a
selected device. The signals are bus driven at
the CPU-I/O interface.
I/O Power Clear - issued by power turn-on
warm-up, by occurrence of a CAF instruction

12-2

(mnemonic for clear all I/O flags), and by
actuation of the I/O RESET key on the control console. The signal resets all flip-flops
storing device-to-processor flag indications
(e.g., ready, done, busy). It is developed as
a 400 nsec, nominal width, negative-going
pulse.
I/O Sync - issued every memory cycle. The
signal may be used to synchronize I/O device
control timing to execution of the program
in progress. The signal is developed as a 400
nsec, nominal width, negative-going pulse.
lOP1, IOP2, IOP4 - microprogrammable sig··
nals to effect lOT instruction-specified operation within a selected I/O device. Processor automatically generates IOP2 and IOP4
for, respectively, data channel input and output transfers. Although they may be used
for any control function, the common uses
of the lOPs are:

lOP 1 - normally used in an I/O skip instruction to test a device flag. It may be
used as a command pulse, but it cannot be
used to initiate loading of or reading from
a device buffer register.
IOP2 - usually used to effect transfer of
data from a selected device to the processor, or to clear a device register. It
may not be used to determine a skip condition.
IOP4 - usually used to effect transfer of
data from the processor to a selected
device register. It may not be used to
determine a skip condition or to effect
transfer of data from a selected device
to the processor.
The lOP signals occur as 1 microsecond, nominal width, negative-going pulses.
Read Status - issued by execution of the IORS
instruction (mnemonic for input/output read
status). Loads the AC with an I8-bit word
containing device flag indications for devices
interfaced to read status facility. The signal
occurs as a I microsecond, nominal width,
negative-going pulse. The signal also occurs
when the REGISTER DISPLAY switch (console) is placed in the STATUS position and
the processor is stopped..
Overflow - issued during the first cycle of a
data channel transfer if the contents (2s complement) of the word counter assigned. to the
currently active data channel device become
zero when incremented. This indicates that

BIDIRECTIONAL DATA
TRANSFER LINES OB)

'-'

I/O SYNC PULSE
IOP1
f-----.-~--

IOP2
IOP4

"-'

SKIP REQUEST

"-"

PROGRAM INTERRUPT
REQUEST

k>-~---

READ STATUS

--.....

READ REQUEST

P
R
C
E
S
S

"'--'

POWER CLEAR
DEVICE SELECTION
LINES (6)
SUB DEVICE SELECTION
LINES (2)

---

.....

...

I
/

0
D
E
V
I
C
E
S

k>----------- ADDRESS LINES (15)
API REQUEST
LINES (4)
API GRANT
LINES (4)
API ENABLE
LINES (4)
DATA CHANNEL
REQUEST

---

DATA CHANNEL
GRANT

......

DATA CHANNEL
ENABLE

......

DATA CHANNEL
OVERFLOW

WRITE REQUEST
+1 -;0. CURRENT
ADDRESS INHIBIT
INCREMENT MB
I/O RUN

Figure 12-2.

I/O Bus Interface

the program specified number of words will
have been transferred at completion of the data channel transfer in progress. I t is normally
used to turn off the respective device, preventing further data channel action by that device
until a service subroutine reinitializes the channel word counter and current address registers,
and the program turns on the device request
flag. The overflow signal may also be used
to initiate a program interrupt through the
program interrupt or automatic priority interrupt facilities for access to the initializing
subroutine. The signal occurs as a 400 nsec,
nominal width, negative-going pulse.
Device Selection Levels
Detection of the current instruction as being an
lOT causes the bit pattern placed in MB 6 -13
at the fetch of the instruction to be bus driven
and sent via eight bus lines to Type WI 03 Device Selection modules, contained in the control

logic for each device. These eight levels form
a 6-bit device selection code, DSO-DS5 (relating
to MB 6-11) and a subdevice or mode select code
extension, SDO and SD I (relating to MB 12-13).
Assertion, or binary 1, is defined as a -3v. Negation, or binary 0, is defined as ground level.
Each WI 03 is configured for response to only
one of the 64 possible DS codes. Cooperating
pairs of WI 03s permit unique response to any
of the 256 DS-plus -SD codes. Each selection
code configured in a device permits the internal
generation of up to three associated commands
through the WI 03 ANDing of lOPs and the device selection code.
I/O RUN
The I/O run signal is available at the interface
for use as the interface designer requires. This
bus driven level switches to the -3v level and
remains there while the "run" flip-flop in the
CPU is set. A ground level indicates that the
"run" flip-flop has been cleared.
Input Control Levels
Six input control level signals arrive at the I/O
control section in the central processor. These
levels are at ground for assertion and at -3v for
negation. Each signal line is terminated in the
processor with a 15 rna clamped load. The
line must be driven from the unc1amped collector of a saturated transistor whose emitter is
grounded. The individual functions of the input
control levels are:

Skip Request - the return of this level to the
processor indicates that an lOT instruction
test for a skip condition in a selected device
has been satisfied (e.g., a test of ready status).
The PC is subsequently incremented by one
to effect a skip of the next instruction of the
program in progress.
Program Interrupt Request - a device delivers
this level to request interruption of the program in progress. The program traps to location 00000 when no I/O transfer action of
higher priority is in progress. The instruction
resident in location 00001 is fetched and
executed. This instruction is usually a JMP
to a subroutine which determines through a
search process ("skip chain") the device making the program interrupt request. Access
is then made of the appropriate service subroutine. Up to 64 devices may be interfaced
to the program interrupt request line. The
limiting factor is solely the program overhead
incurred in the search for the requesting device.
12-3

Read Request - this level requests that the processor execute a read transfer of device-offered
data word.
Write Request - this level requests that the processor execute a data channel write transfer of
a data word into the selected device's information register.
IItB Increment - this level requests that the processor increment by one the contents of the
memory location addressed by the IS-bit address on the I/O bus address lines. The provision is available when the Type KH09A Addto-Memory option is included.

Current Address Inhibit - this is a special signal line required by devices which automatically search for records, etc. Typical are
DECtape and magnetic tape. The presence of
the level inhibits normal incrementing of the
device-assigned current address register during
a data channel transfer.
Multiplexed Control Lines
Fifteen control lines, constituting five multiplexed subsets of three lines each, provide processor-device control information paths for the
multiplexed data channel and the four priority
levels on which the automatic priority interrupt
option processes device channel requests for service. The functions of the lines in the subsets
are as follows:

Request - a device transmits a service request
to the processor via the appropriate request
line. Each request line is terminated in the
processor by a IS-ma clamped load. The
line must be driven to ground for assertion
by an unclamped collector of a saturated
transistor whose emitter is grounded.
Grant - the processor indicates a grant of the
service request by driving the associated grant
line negative. All grant lines are buffered by
bus driver modules in the processor.
Enable - the enable signal controls the priority
order for answering service requests of devices interfaced to the data channel control
or to one of the API's 28 device channels.
Each API channel may be uniquely assigned
to one device for fast access of the appropriate
service subroutine, or interfaced to any number of devices. The latter case requires a
search subroutine to determine the requesting
device. Priority for a channel (data or API)
is allocated in descending order from the device nearest the processor I/O bus interface.
12.. 4

Occurrence of an enable signal permits service of the requesting device with the high·,
est channel priority and inhibits all lower
priority devices from making requests during
the interval of service. A bus driver module
in the processor buffers each enable line.
Address Lines
Fifteen lines, of which only the least significant
six are normally used, constitute an input bus
for the devices which must deliver address data
to the processor. The lines are terminated in
the processor by IS-ma clamped loads. Each
line must be driven to ground for assertion by
an unclamped collector of a saturated transistor
whose emitter is grounded. There are two uses
for the address bus:

l. When a device interfaced to the multilevel, automatic priority interrupt option receives a processor grant of its interrupt request, it delivers to the processor a hardwaredefined address, relating to its API channel
assignment. This channel address indicates
the unique entry point to the device's service subroutine. The instruction resident in
the addressed memory location is always a
JMS (or JMS I or XCT of a JMS), offering
fast access to the appropriate service routine.
2. When a data channel device receives a processor grant of its transfer request, it delivers
to the processor a hardware-defined address,
relating to the memory location of the assigned
channel word counter register.
Driving Address and Data Lines
Connection to the Address Lines and Data Lines
is made by AND gates without clamp loads.
Each gate must be capable of driving 30 mils at
ground. Suggested gates include the S 123 and
the Rill. The RIll requires a 2 mil clamp
load tied to its input mode to deliver the required current.
I/O BUS INTERFACE SUMMARY
The following summarizes the I/O bus interface
at the processor. Figure 12-3 illustrates the key
for determining the connector and associated
pin for each bus line. Provision is made for
two I/O bus connections at the computer; I/O
block No.1, and I/O block No.2.
Reference Symbols:
CO - Collector Output, no clamped load, nor··
nally Type R III or S 123. Can drive a 30-rna
load at ground. O-ma at -3v.
BD - Bus Driven output. Can drive 2S-ma load
at ground, 7-ma load at -3v.

SLOTS

A25

A26

A27

A28

•

• B
A •
•

C
D ..

• E
F •

PIN S -<

•

M
N •

•

S
T ..

N •

,~ ----

PIN A27N

R •

MOUNTING

• u

v •

'--

BAR

v•

~
I"

•

A
B •

•

C
D •

• E
F •
•
PIN S -<

H
J

•

• A

(
•

•

M
N •

•

P
R •

•

S
T •

L •

• v
u ..
SLOTS

----

PIN B26K

B25

v •
B26

B27

B28

Figure 12-3 Interface Connectors and Pins
TABLE 12-1 I/O BUS INTERFACE CHART
I/O Block No. 1

I/O Block No.2

Type

Assertion

Signal Name

A2~D

A2sE
A2sH
A2sK
A2sM
A2sP
A2sS
A2sT
A2sV

A29D
A29E
A29H
A29K
A29M
A29P
A29S
A29T
A29V

CO
CO
CO
CO
CO
CO
CO
CO
CO

<>
<>
<>
<>
<>
<>
<>
<>

I/O BUS 00
I/O BUS 01
I/O BUS 02
I/O BUS 03
I/O BUS 04
I/O BUS OS
I/O BUS 06
I/O BUS 07
I/O BUS 08

A26D
A26E
A26H
A26K
A26M
A26P
A26S
A26T
A26V

A30D
A30E
A30H
A30K
A30M
A30P
A30S
A30T
A30V

BD
BD
BD
BD
CO
CO
CO
BD
BD

••
••
<>
<>
<>
••

I/O SYNC
lOP 1
lOP 2
lOP 4
SKIP RQ
PROG INT RQ
READ RQ
RD STATUS
I/O PWR CLR

12-5

TABLE 12-1 I/O BUS INTERFACE CHART (Continued)
I/O Block No. 1

I/O Block No.2

Type

A27D
A27E
A27H
A27K
A27M
A27P
A27S
A27T
A27V

A31D
A31E
A31H
A31K
A31M
A31P
A31S
A31T
A31V

BD
BD
CO
CO
CO
CO
CO
CO

A28D
A28E
A28H
A28K
A28M
A28P
A28S
A28T
A28V

A32D
A32E
A32H
A32K
A32M
A32P
A32S
A32T
A32V

CO
CO
CO
CO
BD
BD
CO
BD
BD

B25D
B25E
B25H
B25K
B25M
B25P
B25S
B25T
B25V

B29D
B29E
B29H
B29K
B29M
B29P
B29S
B29T
B29V

CO
CO
CO
CO
CO
CO
CO
CO
CO

B26D
B26E
B26H
B26K
B26M
B26P
B26S
B26T
B26V

B30D
B30E
B30H
B30K
B30M
B30P
B30S
B30T
B30V

BD
BD
BD
BD
BD
BD

B27D
B27E
B27H
B27K
B27M
B27P
B27S
B27T
B27V

B31D
B31E
B31H
B31K
B31M
B31P
B31S
B31T
B31V

CO
CO
CO
CO
CO
CO
CO
CO
CO

12-6

BD
BD

Assertion

•
•<><>

<>
<>
¢
<>
<>
<>
<>
<>

••<>
••
<>
<:>

<>
<>
<>
<>
<>

<:>

-'Signal Name
I/O RUN (1)
ADD OVFLO
I/O OVFLO
I/O ADDR 03
I/O ADDR 04
I/O ADDR 05
I/O ADDR 06
I/O ADDR 07
I/O ADDR 08
WRITE RQ
INC MB
+ I-+CA INH
API 0 RQ
API 0 GR (1)
API 0 EN
API 1 RQ
API 1 GR (1)
API 1 EN
I/O BUS 09
I/O BUS 10
I/O BUS 11
I/O BUS 12
I/O BUS 13
I/O BUS 14
I/O BUS 15
I/O BUS 16
I/O BUS 17

•••
•••
••

DS 0
DS 1
DS 2
DS 3
DS 4
DS 5
SPARE
SD 0
SD 1

<>
<>
<>
<>
<>
<>
<>
<>
<>

I/O ADDR 09
I/O ADDR 10
I/O ADDR 11
I/O ADDR 12
I/O ADDR 13
I/O ADDR 14
I/O ADDR 15
I/O ADDR 16
I/O ADDR 17

TABLE 12-1 I/O.BUS INTERFACE CHART (Continued)
I/O Block No. 1

I/O Block No.2

Type

Assertion

Signal Name

B28D
B28E
B28H
B28K
B28M
B28P
B28S
B28T
B28V

B32D
B32E
B32H
B32K
B32M
B32P
B32S
B32T
B32V

CO
BD
BD
CO
BD
BD
CO
BD
BD

API 2 RQ
API 2 GR (1)
API 2 EN
API 3 RQ
API 3 GR (1)
API 3 EN
DCH RQ
DCH GR (1)
DCHEN

••
<>
••<>
••

NOTE: All pins C, F, J, L, N, R, U, should be connected together and wired into the ground mesh of the device.

12-7/12-8 (blank)

CHAPTER 13
PROGRAM CONTROLLED TRANSFERS
GENERAL
The majority of I/O transfers occur under control of the program, taking advantage of control
elements present both in the computer and in
the device controls interfacing to the I/O bus.
Program-controlled transfers require more computer and actual time than data channel and direct memory access transfers, but the simplicity
and inherent lower cost of the device controls
coupled with the high speed of the computer
relative to the operational speed of most peripheral devices offset this extra cost in time.
All programmed I/O transfers take place through
the accumulator (AC) in bytes up to IS bits in
length. In transfers within the central processor,
and between the processor and core memory,
data are processed as IS-bit words, the sole addressable unit in the PDP-9/L. For bytes of
less than IS bits, unused bits in the data word
normally remain zeroed. Programming techniques of masking and shifting the contents of
words are also used to pack and unpack bytes
of less than IS bits, to reduce core memory
storage requirements.
The rate of programmed transfers is a function
of the device characteristics and the program
manipulation required for each data byte transferred. The lOT instruction capability of the
PDP-9/L allows programmed control of up to
256 devices, as well as the generation of up to
three unique commands for each of the 256
possible device selection codes. Devices requiring more than three internal commands are assigned additional device selection codes.
The bussed system of input/output data transfers imposes the following requirements on peripheral equipment using the programmed data
transfer facility:
1. The ability of each device to sample the
select code generated by the computer during
lOT instructions and, when selected, to be
capable of producing sequential command pulses in accordance with computer-generated
lOP pulses. Circuits performing these functions
in peripheral devices are called device selectors (DS). A single double-sized module, the
W103, provides all of these functions.

2. Each device receiving output data from
the computer must contain gating circuits at
the input of a receiving register capable of
strobing the data on the I/O bus into the
register when triggered by a command pulse
from the DS. Such gates are called device
input gates.
3. Each device supplying input data to the
computer must contain gating circuits at the
output of the transmitting register capable of
strobing the information from the output register to the I/O bus, and furnishing a read
request signal level to the computer when
triggered by a command pulse from the DS.
Such gates are called device output gates.
4. Each device must contain a busy/done
flag (flip-flop) and gating circuits that can output a signal to the computer input/output skip
bus upon command from the DS. The flag is
set to indicate that the device is ready to transfer another byte of information.
INPUT/OUTPUT TRANSFER INSTRUCTIONS
Input/output transfer (lOT) instructions initiate
transmission of signals through the I/O bus to
control peripheral devices, sense their status, by
means of the I/O skip facility, and effect programmed transfers between them and the processor. A PDP-9/L lOT instruction has the
format shown in figure 13-1.
The PDP-9/L lOT instruction has the following
characteristics:
1.

An operation code of 708 ,

2. An S-bit device selection code to discriminate among up to 256 peripheral devices (selection logic in a device's I/O bus interface
responds only to its preassigned code). In normal practice, bits 6 through 11 perform tbe
primary device discrimination among up to 64
devices, with bits 12 and 13 coded to select
an operational mode or subdevice.

13-1

OPERATION
CODE 70

DEVICE
SELECTION

GENERATE
AN lOP 2
PULSE AT EVENT
TIME 2

CLEAR AC
AT EVENT
TIME I

121131141151161nJ
,

UNUSED

SUB-DEVICE
SELECTION

* IOP4 IS ASSIGNED TO THIS B(T BECAUSE OF ITS BINARY RELATIONSHIP

'--y---J

'----y----'

GENERATE
AN lOP 4
PULSE AT
EVENT TIME

GENEFIATE
AN lOP I
PULSE AT
EVENT TIME

TO THE OTHER lOP BITS. THERE IS NO IOP3.

Figure 13-1

PDP-9/L lOT Instruction Format

Table 13-1 indicates the device selection codes
assigned to standard PDP-9/L device and facilities. Codes not so used are available for assignn1ent to user-designed interfaces or specialpurpose equipment.

10 SYNC

3. A command code (bits 14 through 17)
capable of being microprogrammed to clear
the AC, and issue up to three pulses through
the I/O bus.

IOP1

Any lOT instruction may be microcoded to produce more than one lOP pulse by setting one,
two, or three bits of bits 15-17 of the instruction word to a 1. The resulting device lOT
pulses appear in the time sequences defined by
the lOT timing diagram (see figures 13-2 and
13-3).

IOP4

lOP 1

-1

15.liSEC

a,L----.J

-3

0-lOP 2
-3

a
lOP 4

-3

lOT 1

S-L

-3 -=::10 4
....._
r _ _ _ _ _ _ _ __
..uSEe

~_ _ _ _ _ _ __

lOT 2

_: _ _

lOT 4

_:__________~rl. . ._________
NOTE·

lOT PULSE MAY BE 100 OR 400 Mac WIDE
BOTH POSITIVE (- 3V TO GROUND) AND NEGATIVE (GROUND TO -3V) PULSES ARE
AVAILABLE

Figure 13-2 lOT Timing Diagram
13-2

10 SYNC AND lOP
SIGNALS GENERATED
AT PROCESSOR

Figure 13-3 lOT Pulse Wavefonns
The MB bits corresponding to the device selection
levels are buffered by B213 Bus Drivers. Bus
Driver outputs are labeled DSo-DS 5 (device selector), with the following correspondence:

lOT TIMING DIAGRAM

MEM CYCLE START

IOP2

MB6
MB7
MBa
MBg
MB10
MB11

DS o
DS 1
DS 2
DS 3
DS 4
DS 5

MB bits 12 and 13 are also bus driven, and
available at the interface as sub-device bits (SD).
These are labeled:

Each peripheral device contains at least one Device Selector module WI 03. This module produces specific device lOT pulses upon receipt of
a unique 6-bit device selection code (device number) and the lOP pulses.

TABLE 13-1. ASSIGNED PDP-9/L DEVICE SELECTION CODES
001 RT Clock
2 Prog. Interrupt
4 RT Clock

20 Memory
Increment
KH09A

40 LT09A
Line 1
Teleprinter

01 Standard
Perforated Tape Reader

11 Analog-toDigital or
Digital-toAnalog
Converter

21 Relay Buffer
DR09A

41 LT09A
Line 1
Keyboard

02 Standard
Perforated Tape Punch

12 AID or
D/A

42 LT09A
Line 2
Teleprinter

03 1 Keyboard
2 Keyboard
410RS

13 AID

33 1 33 KSR Skip
2 Clear All
Flags
4 DBR,DBR

43 LT09A
Line 2
Keyboard

73 Tape Control
TC59

04 Teleprinter

24 Incremental
Plotter
Control
Type 350

44 LT09A
Line 3
Teleprinter

74 Tape Control
TC59

05 Displays
Types 34F,
300,

25 DP09A

45 LT09A
Line 3
Keyboard

55 Automat i c
Priority
Interrupt
KF09A

65 Automatic
Line Printer
Type 647

75DECtape
Control
TC02

06 Displays

26 DP09A

46 lT09A
Line 4
Teleprinter

66 Automatic
Line Printer
Type 647

76DECtape
Control
TC02

07 Display
and
Light Pen

17 Memory
Protection
KX09A

27 Memory
Parity
MP09

47 LT09A
Line 4
Keyboard

67 Card Reader
Type CROI E
or Type CR02B

77 Memory
Extension
KG09A

Converter

1
Vol
I
Vol

I
t

For example the instruction:

by clipping out diodes from the board.
figure 13-4.)

(See

703401
applies 348 to the I/O bus device selection lines.
The device selector module in device nmnber 34
responds and, at lOP 1 time, issues lOT 3401.
The device number of any WI03 is determined

<llOT 3201

,r ,r

---

I--

f--

I--

DEVICE
SELECTOR

f--

--- I

f--

--- I

lOT 3204

<:}

lOT 3202

I
I

lOT Pulse I - normally used in an I/O skip
instruction to test a device flag. May be

FORCE
SELECT

lOP
4

The usual use of the three lOPs is given below.

~
~
:I

~
:I
I

W103

I
'U

J
'V

I
I

J
'U

-4<}--

1 DS2

DS3

1 DS4

R107

DIODE LEFT ON THE MODULE (W103)
DIODE CLIPPED OUT OF THE MODULE (W103)

13-4

1 DS1

Figure 13-4. Device Selector Configuration

DS O

,.
p

.-L

DSs

used as a command pulse, but not to initiate
either a "load" or "read" from adevice.
lOT Pulse 2 - usually used to transfer data
from the deyice to the computer, or to
clear a register. May not be used to determine a "skip" condition.
lOT Pulse 4 - usually used to transfer data
from the computer to the device. May not
be used to determine a "skip" condition or
to effect transfer of data from a selected
device to the processor.

(i.e., MBI4=1).
figure 13-6.

I/O waveforms are shown on

DATA IN TRANSFER
10 SYNC

IOP2

DATA, RD RQ

INTERNAL READ
SIGNAL

Reading a Device Buffer into the AC
The reading of a device buffer into the computer is accomplished in the following manner:
1. lOT Pulse 2 is generated in the device
selector module, and used to trigger a W640
Pulse Amplifier (which must be in each input device) jumpered to produce I-microsecond pulses.
2. This I-microsecond pulse is used to gate
the device data buffer onto the I/O data bus.
3. Simultaneously a read request positive
pulse is generated (by an RIll or S 123) on
the read request line.
4. The central processor receives the request
signal and allows time for the data bus to
settle completely.
5. The I/O bus is strobed into the AC.
*The output of the W640 ought to be a I-microsecond pulse, which is regarded by the I/O bus
system as a level. Either pulse or level notation
may be used, provided this definition is kept in
mind.
Since the I/O bus is ORed into the AC (figure
13-4), the read lOT instruction is usually micro
programmed to clear the AC prior to reading

DATA IS READ INTO AC
ON TRAILING EDGE OF
INTERNAL READ SIGNAL

Figure 13-6 I/O Signals from Buffer to I/O Bus

Loading a Device Buffer from the AC
The loading of a device buffer from the AC
(figure 13-7 and 13-8), is usually accomplished
by, but not restricted to, the following two
steps. The first lOT clears the device buffer, and
the second lOT ORs the contents of the AC into
the cleared buffer. For such a transfer the de'
tails are as follows:
1. Prior to the end of the first cycle the
AC is placed onto the I/O bus. Note that
in any output transfer, lOP 1 must not be
used to transfer the AC to an external register.
2. IOT2 is generated in the Device Selector
module WI 03, and transmitted to all
"clear" inputs of the flip-flops in the device
buffers.

1/0 BUS

READ

BIT 0

BIT 1

BIT 16

BIT 17

REQUEST

Figure 13-5

Loading the AC from a Device Buffer
13-5

--o"----~--L----____c:.a-----"""T""---'

15<I1<J---------.I5<]<:::}-- -

R200

SER,I_ES{>L-_ _- - , _ ' - -_ _ _{>I-_ _- - , , - ,

lo'r

----I5<.:J<J---------I5<:lI<J-XXCl4

EEJ - - - - -I/O BUS
BIT 0

I/O BUS
BIT '!

I/O BUS
BIT 16

I/O BUS
BIT 17

ICIT

Figure 13-7 Loading a Device Buffer from AC
DATA OUT TRANSFER

10 SYNC

10F'4

15 rna to -15v load for the skip bus line is
located at its termination in the processor. The
signal on the skip line is sampled 600 nsec after
lOP 1 is issued. An RIll without a c1alnped
load or a S 123 Diode Gate must be used in the
device.
The sensing of a device flag (figure 13-9) is accomplished in the following manner:

DATA

1. lOT pulse 1 is generated in the device
selector module.
DS LEVELS

DATA IS READ I NTO DEVICE
BUFFER AT LEADING EDGE
OF 10F'4

Figure 13-8 I/O Signals from I/O Bus to Buffer
3. IOT4 is generated in the WI03 and applied to the DCD input gates of the device
buffer. Note that the input DCD gates for
each bit in each output device must be buffered from the I/O bus by Emitter Fol10wersW 500.
I/O SKIP FACILITY
When lOT pulse 1 is used in a I/O skip instruction (example CLSF = lOT 0001 = 700001), it
is gated with the device flag flip-flop through a
diode gate and returned to the computer on the
I/O skip request bus line. A positive pulse, 1
microsecond wide, is returned to the proces.sor,
if the tested flag is a binary 1. The skip flipflop in the processor is set, and the instruction
following the lOT instruction in the program
sequence is not executed -- it is skipped. The
13-6

2. This pulse is gated with the 1 output
of the device flip-flop (Le., flag) through a
diode gate (undamped RIll or S 123) tied
to the "I/O skip line".
3. If (and only if) the sensed flag is in the
1 state, a 1-msec pulse is returned to the
central processor via this I/O skip line.
4. This pulse sets the I/O skip flip-flop in
the processor. In this instance, the instruction following the lOT instruction is not
executed.
STATUS WORD FACILITY
The lOT instruction 10RS (=IOT 0314 = 700314)
loads the accumulator with a word comprised
of various device flags and control flip-flops.
External devices, having status bits assigned, use
the read status level to gate the device flag onto
the corresponding I/O bus bit line. (Bits 15,
16, and 17 have been reserved for special customer devices.)
The status word is readable at the console when
the register function switch is in the STATUS
position. Figure 9-1 illustrates the AC bit pos.:i-

PROGRAM INTERRUPT
LINE

10 SKIP
LINE

rf-

BUS
BIT N
0

READ
STATUS

rv
1\

J .....

......

W640

......
.....

-::r-

f<r- lOT XX01

toDEVICEo ~.
FLAG
rlJ

rl.J

Figure 13-9 Device Flag Hardware
tions associated with the standard IORS assignments.
PROGRAM INTERRUPT (PI) FACILITY
When computer time is at a premium, it is
advantageous for the computer to perform other
tasks rather than wait for some peripheral device
to complete its operation. The program interrupt facility allows the program to ignore the
peripheral device until it signals completion of
operation. At that signal, the computer program
can enter a subroutine to service the device.
In case several devices are connected to the PI,
a chain of I/O skip instructions and JMPs are
issued by the program to determine which device caused the interrupt.
If the computer is servicing an API initiated interrupt, a PI request is not granted until all the
API channels are dismissed.

LINK

MEMORY
PROTECT
MODE

Figure 13-9 shows the device hardware required
for the program interrupt facility. The device
flag is connected to the program interrupt request line by a Type RIll or S 123 Diode Gate
(unused input left floating). This request line
is terminated in a 1S-ma clamped load in the
computer I/O frame.
Interrupts occur only when the program
interrupt facility is enabled. lOT instructions
associated with the PI are:

Mnemonic

Code

Operation

IOF
ION

700002
700042

turn off PI
turn on PI

When an interrupt is recognized, the computer
stops execution of the main program. The 1Sbit address of the next main program instruction
and certain flags are stored in memory address
00000. The word is stored as shown on figure
13-10.

PC
,

4
~

~,--~.~~

EXTEND
MODE

EXTENDED
PC

Figure 13-10 Program Interrupt Storage Word
13-7

AUTOMATIC PRIORITY INTERRUPT, Type

KF09A

In real-time computer systems such as the PDP9/L a small number of peripheral devices with
relatively few timing problems or priority considerations can be handled quite easily by the
standard program interrupt facility without 3l
significant loss in central processor efficiency.
However, if the number of peripherals is large,
with a hierarchy of priorities, or the desired data
rate is over 50,000 words per second, signficant
econornies in central processor overhead time can
be achieved by the use of a multi-channel au tomatic priority interrupt system.
The Type KF09A Automatic Priority Interrupt
(API) option for the PDP-9/L provides the
necessary hardware to handle a multiplicity of
input/output devices with a mnimum of pro··
gramming effort and a maximum of efficiency.
Its priority interrupt structure permits high data
rate devices to interrupt the service routines
of slower devices with a minimum of system
overhead. The API also permits the device service routines to be entered directly from hardware-generated entry points, eliminating the need
for time-consuming flag searing to determine the
identity of the device causing the interrupt.
The Type KF09A provides thirty-two channels,
or unique entry points for device service routines,
and eight levels of priority. The four highest
priority levels are for device service requests~
and interrupts on these levels are initiated by
hardware service requests (i.e., device flags). The
four lower priority levels are assigned to the
processor for software routines; activities on these
levels are always initiated by program requests,
and four channels (or service routine entry
points) are reserved for these priority levels.
Each device interfaced to the Automatic Priority' Interrupt system must specify its "trap
address" or unique entry point to its service! routine. Locations 408 -778 are reserved as these
service routine entry points, and "trap address"
and channel numbers are related as follows:
(TRAP ADDRESS~ = (CHANNEL NUMBER~
+ (40)8
Locations 40 8 -778 should contain JMS or JMS I
instructions to provide linkage to the actual service routines.

13-8

Table 13-2 shows the relationship between channel number and trap address, the channel assignments for standard PDP-9 I/O devices, and their
suggested priority levels. All devices listed in
Table 13-2 are connected to the API as shown,
if the API option is purchased. The channel
number-assignments should remain fixed for software compatibility, but priority levels may be
changed at the user's option.
Devices are interfaced to the API in the same
manner as they would be to the Program Inter··
rupt (PI) facility for all signals except the device
flag. For API devices, the device flag is tied to
one of the API levels on the I/O bus through a
Wl04 module in the device interface. (Device
flags tied to an API level must AND their respective API RQ (1) level with the Device Flag
to request PI.)
The WI 04 module is used to establish priority
among devices tied to the same priority level;
it also gates the trap address (channel nunlber)
onto the I/O Address (10 ADDR) lines at the
appropriate time. Figure 13-11 shows the
Wl04 module and its pin connections.
As Table 13-2 shows, there need not be any
fixed relationship between channel number and
priority level (except for the four software priority levels). The priority interrupt level of a
device may be chosen by the user; it is determined by the set of lines to which the user
interfaces.
The I/O bus contains twelve lines unique to the
API; these include an API RQ (request), API
GR (1) (grant), and API EN (enable) line for
each of the four levels. Since these control
lines are part of the standard I/O bus and pass
through all devices, it is relatively easy to change
a device's priority by disconnecting from one set
of lines and attaching it to another. Because of
the time delay encountered in propagating signals
through aWl 04 module, no more than eight devices should be interfaced to one priority level.
Figure 13-12 shows an exaluple of four devices
tied to the API (only API-related lines are shown).
In this example, the following relationship exists
between device number and priority level.
Device
A
B
C
D

Priority Level
3
2

0
2

TABLE 13-2 CHANNEL AND PRIORITY ASSIGNMENTS
Channel
Number
Octal

Trap
Address

Standard Device

Software channel 0

Suggested
Priority
Level

10 ADDR
Bits 12-17

100 000

Software channel 1

100 001

Software channel 2

100 010

Software channel 3

100 011

DECtape (TC02)

100 100

Magtape (TC59)

1
1

Drum (RM09)
Disk

1
1

50
51

Papertape Reader
Clock Overflow
Power Fail (DP09)

2
3
0

101 000
101 001
101 010

Parity (MP09)
Ught Pen (34H)

0
2

101 011
101 100

Card Readers (CR01E, CR02A)

101 101

11
12
13
14
15

52
53
54
55

100 101
100 110
100 III

Une Printer (647)

101 110

A/D (AF01)

101 111

57
60

110 000

DB99 A/DB98A
Data Unk to System 360

110 001

Data Phone (DP09A)

110 010

110011

Reserved for Systems Device
Unassigned
Unassigned
Unassigned

110 110

110 100
110 101

65
66

Unassigned

110 111

Unassigned

111 000

71
72

Unassigned

III 001

Unassigned

111 010

Unassigned
Unassigned

111 011
111 100

Unassigned

111 101

Unassigned
Unassigned

111 110
111 111

32
33
34
35
36
37

73
74
75
76
77

13-9

,--------0--0---<>
CONNECT AS NEEDED

G
S~3

10 ADDR 12

-o---<>

THROUGH
}

10 ADDR 17

t,J
t,K

~:~
t,S

t,u

~ENAIII

'----,y~--~

------------

--l------------------~ ENOUT

.---_-+-_ _ _ _ _ _ _ _ _ _-=AV~ ENA (0)

,------r---+----------~RO

I - - - - - - - - -- AD ~S~E~ I
I
I
I

EN IN ---"'BH-'--_ _---<~

:~~~~~~.:~
10

PWR CLR

'U
R107

~ENB(1l

I
I
I
-1VV---.---oA-,.--:.:..:~____I:_--:---C>i-_r__.:..:..:..::.:=__,.....J

L-

EN IN -ot>\----....,.....I

----~-----+---

~ENB(O)

ONL Y USE D WITH
DATA CHANNEL. NOT
NECESSARY WITH API

I
I
I
I
I
I
I
I

~BF~_ _ _ _ _ _ _ _~~

""" '"

FLAG

ENAIO)

ENAII)

I
I
I
I

r---4---'---------~ CLR FLAG

~BS::!..--_ _ _ _ _ _ _ _ _ _____1

GR -",BE=--_

Figure 13-11

W104:

PDP-9/L I/O Bus Multiplexer

If all four devices request service simultaneously,
they are serviced in the following order: C, B,
D, and A. Although Band D are on the same
priority level, device B is serviced before D because it is closer to the computer on the I/O
bus.
Each WI 04 module contains six address selection lines (pins AJ, AK, AL, AN, AS, AU).
These lines are normally connected to the 10
ADDR lines of the I/O bus to form the trap address. For standard API devices, pin AJ is connected to line as (4° 8 ) and pins AK-AU from
the channel number.
In some cases, trap addresses above 778 may be
used, although standard PDP-9 peripherals should
be restricted to 4°8-778. Figure 13-13 shows
the possible connections -for trap addresses between 1008 and 1378 .
If a single device is required to generate a number of different addresses on the basis of a single

13-10

flag, the WI 04 can be used to gate the address
from a flip-flop register onto the 10 ADDR
lines. Figure 13-14 shows an example of this
situation.
Figure 13-15 shows the proper connection of a
device flag to the API system and also (optionally) the PI system.

Figure 13-16 shows the case of a single device
with multiple flags, anyone of which can cause
a trap to a unique address. In this case, the
different flags are all tied into the same request
line. They may be tested individually by lOT
instructions (I/O SKIP), so they should also be
tied to the I/O SKIP line. They are also cleared
individually, as shown. The flags are also con-nected to the ENA (1) line (as shown) to assure
that the ENA flip-flop will be cleared when aU
of the flags are cleared, regardless of whether
or not the API break is granted.

DEVICE A

6 10 ADDR LINES
AND OTHER
CONTROL SIGNALS)

DEVICE B

DEVICE C

DEVICE D

CONNECT AS RE()JIRED
-TO DESIGNATE lrRAP
ADDRESS

APIO RO ~
APIO GR(1)
APIO EN

..-

:=.
....

.-.

:=.
....

Wl04
?FLAG

DE'geE
IOT
CLR
FLAG

API 1 RO'---'
API 1 GR(I)
API 1 EN

.......

PDP-9

API2 RO :::.
API2 GR(1)
API2 EN

=.
.....

.......

.::
....

Wl04

.-.
~

.....

yFLAG

FLAG

DEVICE
D

DEVICE
B
.....
API3RQ ~
API3 GR(I)
API3 EN

•....

..Wl04

.-.

? FLAG
DEVICE
A

Figure 13-12 Devices on the Automatic Priority Interrupt

IO ADDR 10 ADDR
11
12
0

13
<;>

14
<;>

16
<;>

17
<;>

CONNECT AS REOUI RED

1'\

I I I I I

W104

Figure 13-13 Connections for Trap Addresses
Between 100 8 and 1378

13-11

10 ADDR

10 AOOR

ENA(ll

AP
W104

~------------------~-------------------~
R200 SERIES
FLIP - FLOPS

Figure 13-14 Gating Flip-Flop Register onto I/O Address Lines

W104

1-=__--_-<> REQ(1)

OPTIONAL IF
DEVICE FLAG
ALSO TIED
TO PI
L....

IOT-~~----

______

-I

Figure 13-15 Interface of a Single Device Flag
to both the PI and API

r-------~~B~U------...- - - - - - - - - - < l• • REQ (1)
FLAG

W104

L-_ _ _ _ _----II----------+--------I....

lOT CLEAR A - - { > L - - - - - - - J

lOT CLEAR B

-I
--

1
FLAG B

•••
lOT CLEAR N --C>'---------'

Figure 13-16 Single Device with Multiple Flags
13-12

~~;/G~~~Dl

CHAPTER 14
DATA CHANNEL
GENERAL
The PDP-9/L data channel, multiplexed to permit interfaced service to eight peripheral devices,
provides a relatively high-speed interface to the
core memory along the I/O bus. Requests for
data from I/O devices are honored by the channel at the completion of the instruction in progress at the time the grant signal is issued. The
channel is controlled by word count and address
registers held in core memory; each request
updates these registers, and transfers the data
between the memory and the device.
Each of the eight devices has a unique pair of
(sequential) core memory registers associated
with it. (The system software assumes that devices 0-3 use registers 30-37 8 ,) These registers
must be initialized by the program, before the
peripheral device may begin transferring data
through the channel. The first (word count)
register, of lower numerical value, must be even,
and is initialized to contain the 2s complement
of the number of words to be transmitted. The
second (address) register is initialized to contain
1 less than the first address of the data word
block.
These registers may be examined at the end of
channel operation to check for final address, if,
for example, the device indicates that a short
record was read. Peripheral devices nornlally
issue a program interrupt (API) request at the
completion of the transfer when the word count
'register has counted up to O.
The maximum transfer capacity of the channel
is between 160,000 and 220,000 words per seccond, depending on the mix of input and output
rates. Each input transfer steals three processor
cycles; each output transfer steals four processor cycles. The latency time (maximum wait
before service is granted after a request is made)
may be as high as 30 microseconds under adverse conditions (see latency section). Special
care is necessary, however, when designing software for devices whose channel usage is greater
than 50,000 words per second.

Priority among I/O devices making simultaneous
requests is determined by their physical placement on the I/O bus, with devices closer to
the processor having priority over devices further
away. The establishnlent of priority requires
that each device quickly propagate an enable
signal to the next device on the bus, and a special module, the WI04 Bus Multiplexer, has been
designed for this purpose.
LATENCY
Since data channel requests are only honored
between instructions, the type of instruction in
progress determines the waiting time until the
interrupt is granted. The following considerations apply:
1. The lOT instruction is noninterruptible.
The interrupt request is honored at the
completion of the instruction which follows
the lOT.
2. The EAE instructions delay interruption
until they complete, which may be as long
as 17 microseconds.
3. The XCT instruction is noninterruptible.
The interrupt request is honored at the
completion of the instruction referenced by
the XCT.
4. Lower priority devices wait for the completion of data transfers on the requesting
higher priority channel. Hence, if four
requests come up simultaneously, the lowest
may wait 12 microseconds, and indefinitely
if a higher priority device is taking successive breaks.
Long XCT chains on sequential lOT instructions
can lock out channel requests for indeterminate
periods of times. These are to be avoided in
programs operating devices requiring short latency.
EAE instructions requiring more than 12 microseconds are uncommon, but possible. Unfortunately, requests tend to stack up during these
waiting periods, so that lower priority devices

14-1

must wait even longer. I/O system design must
insure that the latency time requirement of each
peripheral is satisfied.

5. The device data flag is used to request a
break through a synchronizing flip-flop, whiGh
drives the request line (DCH RQ). The device
data flag must be cleared when the break is
granted (DCH GR).

DEVICE INTERFACE HARDWARE
Each device connected to the data channel must
have the interface hardware outlined below. The
first four requirements are essentially the same
as those met by devices connected to the program interrupt. They insure that the device
hardware ITlay also be checked by maintenance
routines using special lOT instructions. Requirements 5, 6, and 7 are met by the Type WI04
Bus Multiplexer module, strongly recommended
for use in the interface. Basic connections are
shown on figure 14-1. The WI 04 is shown on
figure 14-2.
1. Each device must have the ability to decode the 6-bit selection code transmitted by
the processor on the device selection lines.
When selected, the device must be capable of
producing internal command pulses in response
to lOP pulses transmitted on the bus. The
module performing such functions in the peripheral device is called the device selector.
Furthermore, the device must have the ability
to force selection of the device selector, regarclless of the address on the selection lines.
The Type W103 Device Selector module
possesses this property.
2. Each device receiving output data fr01ll the
conlputer must contain gating circuits at the
input of the receiving register capable of strobing the I/O bus information into the register
when triggered by a command pulse from. the
device selector.. In addition, the device must
supply a write request level to the channel
during the period wherein it is selected.
3. Each device supplying input data to the
conlputer must include gating circuits at the
output of the transmitting register capable of
gating this register onto the I/O bus, when
triggered by a command pulse from the device selector. In addition, the device must supply a read request level to the channel while
it is selected.
4. Each device must contain a request flag
(flip-flop), which is set whenever the device is
ready to receive (or transmit) another word
of information: This flag is normally cleared
when the transfer is complete.

14-2

6. Each device must be capable of propagating the enable signal (DCH EN) to the next
device to establish priority of devices along
the bus in case of simultaneous requests. The
next device must be enabled if the current
device is enabled, and is not itself requesting.
7. Each device must contain the gating circuits necessary to transmit the core memory
address of the word count register assigned
to the device. The address is transmitted by
the selected device upon receipt of the grant
signal (DCH G R) from the channel.
8. Each device must contain an "active" fliipflop which controls whether or not the device periodically requests data transfers through
the channel. This flip-flop is normally turned
on by the program with an lOT instruction,
and off by the 10 OVFLO signal trans1nitted
to devices by the channel.
INITIAL SEQUENCE OF DATA-IN TRANSFER
(TO COMPUTER)
The device flag is raised asynchronously by SOlrne
state change in the I/O device control or associated mechanical hardware. This flag is synchronized by the W104 Multiplexer, which requests a data channel interrupt through the DCH
RQ line. If more than one device on the channel is requesting, the multiplexer insures that the
lower priority device is shut out by driving its
enable (DCH EN) input line to ground (disabled
state). This request is recognized by the processor and, at the end of the current instruction,
control is relinquished to the channel hardware.
The channel hardware begins operation by identifying the device requesting service. This is
performed by issuing a grant signal (DCH GR)
to all connected devices. Upon receipt of the
grant signal, the device which supplied the DCH
RQ transmits the core menlory address of its
word count register along the I/O address lines.
The specified register is read from memory,
incremented, and rewritten. If, in this word
count updating procedure, the count reaches
0, an I/O overflow signal is sent to all devices.
The device hardware interprets the overflow signal as a shut down command. No further trans-

RD RO, WR RO, or
OTHER FUNCTION RO

WI04

10 PWR CLR

ENB

'9"1

IO SYNC
DCH EN OUT

DCH REO

DCH GR
~

DCH EN IN

.....
.....

REMOVE
APPROPRIATE
DIODES FOR
WC ADDRESS
CODE

FLG

""
r--

CLR
FLG

10 ADDR LINES
~

(6)

COMPUTER

IOP2

...

IOP4

...

DEVICE
FLAG
CIRCUITRY
TRANSFER COMPLETE

~-,

SELECT

.....
.....

I
RII1 or S123
II

(TO NEXT W104
FOR DCH DEVICE)

OS AND SO
LINES (8)

TO
COMPUTER

10 OVFLO

I
R111 or S123
f\

W103
REMOVE
APPROPRIATE
DIODES FOR
SELECTION
CODE

TO
DEVICE
CONTROL

lOT XX02

lOT XX04

Figure 14-1

,..

Data Channel Configuration

IOADDR12
CONNECT AS NEEDED

THROUGH:~

:
}

IOAODRI7:~

-~ENA(11
~----~y~----~

-r--------------~B~M~ENOUT

.--__-+_______________..c:AV.:.....,,~ ENA (01

+-__~-----------------~B~V0 RQ

r - - - - -_ _

REO (01
REO (11

,------------

I
I
I
I

EN IN -=.:...-----~

...,=-----..--.!

t--_---'-'A.=..E. . . ENB (11

.--__-+______----'A""r...... ENB (01

)0
PWR CLR

CLR FLAG ....:B'-F_ _ _ _ _ _ _ _ _ _--t:>[;<~

ONLY USED WITH
DATA CHANNEL, NOT
NECESSARY WITH API

10
PWR CLR

ENA(Ol

ENA(1l

I--~~-----------___~B~D·_~ CLR FLAG

FLAG ...,:;B:.,::5:....-_ _ _ _ _ _ _ _ _ _ _ _ _ _-1

MU5T BE TIED TO
BF EXTERNALLY
l _ _ _ _ _ _ _ _ _ _ _ _ __

GR ....:B~E~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~~

figure 14-2 Type W104 Bus Multiplexer
14-3

fers are made until the device is re-initialized by
the programmer.
After incrementing the word count register,
the channel reads the next sequential word
from memory. This is taken as the current address register, which is incremented and rewritten
into memory. The update value is used to
specify the location into (from) which the data
is to be transferred.

the fourth cycle. At the beginning of the fourth
cycle, IOP4 is issued instrilcting the device to
clear its buffer, and to gate the data on the
bus into its receiving register. DCD gates must
be used. The sequence then ends, apd the channel relinquishes control to the processor.

J:;rt0>]
R200

~--------~~--~~--

Operations Unique to Reading (Refer to
figure 14-3)

-----e

SET FOR
0.5 MSEC

If the read request (RD RQ) signal is present,

and the write request (WR RQ) signal is not
present, the transfer is taken as an into-computer
data transfer. At the beginning of the second
(current address) cycle, IOP2 is issued. At this
time the device is expected to gate its data onto
the I/O bus for subsequent readin by the channel. A t the end of the second cycle, the data
is read into the AR register. The third cycle
stores the data word in the memory. This
ends the sequence, and the channel relinquishes
control to the processor.
10 BUS
BIT 0

Figure 14-3

10 BUS
BIT 17

DCH In Transfer (To Computer)

INITIAL SEQUENCE OF DATA-OUT TRANSFER (FROM COMPUTER)
. The initial sequence of the data-out transfer is
the same as the previously described data-in
transfer.
Operations Unique to Writing (Refer to figure
14-4)

10 BUS
BITO

10 EIUS
BIT 17

Figure 14-4 DCH Out Transfer (From Computer)
EXPANSION TO EIGHT DEVICES
The number of devices connected to the channel is limited only by the maximum cOlnbined
transfer rate capability and the propagation
delay per device of the enable signal (DCH EN).
Approximately 600 nsec are available between
I/O SYNC and DCH GR, wherein the enable
signal may propagate through the four multiplexers. This is always possible with maximum
permissible I/O bus cable length and use of the
Type WI 04 Bus Multiplexer module in each
device. If cable lengths are kept to a minimum,
it may· be possible to attach mote devices to
the multiplexer. The limit with extremely short
cabling and use of the WI 04 Bus Multipllexer is
eight devices.
SIGNAL DEFINITIONS
Table 14-1 lists I/O signals and their respective
definitions. See chapter 12 for details of I/O
connector and figure 14-5 for DCH timing .
ADD-TO-MEMORY CAPABILITIES
With the add-to-memory capability, certain facilities are available. These include add-to-:memory
instructions, specified by sending both RD RQ
and WR RQ, and memory increment, specified
by sending a signal on the NEM INC line.

If the write request signal is present, and the

read request signal is not present, the transfer
is taken as an out-of-computer data transfer.
During the middle of the third (data) cycle,
the channel places the requested data onto the
I/O bus for subsequent readin by the device.
The data remains available until the middle of

14-4

The add-to-memory operation is a combination
of reading and writing. The data transmitted
by the device is added to the word read fronl
memory and re-written into memory. The sum
is transmitted back along the I/O bus. Four
cycles are required. Since the sum is re-trans-

TABLE 14-1

SIGNAL DEFINITIONS

Signal

Definition

DCH RQ

The request signal from the device to the channel indicating that the device requires
service. The line must be driven by a saturated transistor whose emitter is grounded.
A IS-rna load to -lSv terminates the line at the processor.

DCH EN

A bus driven signal which establishes priority along the device. Each device must
supply a noninverting bus driver with a total transition time of 100 nsec into S feet
of bus cable.

DCH GR

A bus driven signal emanating in the processor which instructs the selected device
to transmit its address back to the processor. Maximum load is eight Type WI04
Bus Multiplexer modules or equivalent.

RD RQ

The request signal from the device to the channel indicating that the device wishes
the transfer to be in the "in" direction. The line must be driven by a saturated
transistor whose emitter is grounded (RIll or S123). A IS-rna load to -lSv terminates the line at the processor.

WR RQ

As RD RQ except specifies "out" direction.

I/O ADDR

Fifteen lines, of which only the least significant six are normally used. The device
transmits the address of the core memory register specifying word count along these
lines. Loading is the same as RD RQ.

I/O DATA

Eighteen lines of bidirectional data transfer between the channel and the device.
Loading is the same as RD RQ. Receiving registers in output devices must buffer
the incoming lines with WSOO Emitter Follower modules.

A special signal line used by devices which automatically search. The presence of
the +1 CA INH signal inhibits the normal incrementing of the current address word
driving the second cycle. Load is the same as RD RQ.

CA INH

MEM INC

Load is the same as RD RQ.

I/O OVFLO

A pulse originating in the channel logic which indicates the transfer of the. specified
number of data words has been completed. It is transmitted during the first cycle
if the word count register increments to zero.

mitted to the device at IOP4 time, the device
may detect overflow.

O. Maximum rate is 160,000 increments per
second, but this may be unattainable if long instructions are encountered.

The memory increment operation is the first
cycle only of a channel transfer. The word
specified on the I/O address lines is incre.mented.
An overflow signal (10 OVFLO) is transmitted
to the device if the data word is incremented to

STANDARD CORE REGISTER ASSIGNMENT
Standard core register assignments of the DECtape; Magtape and Interprocessor Buffers are
listed in table 14-2.

14-5

10 SYNC

d t t t
wc

OUT

•

DATA

1 t

t t

400 NS MIN TO INSURE GETTING BREAK
0

~-------------~/

FLAG

-3
DCH
RQ
DCH EN
PROPAGATION
DCH
GR

-3
0

\~----------.-----------

___________________~r--\~______________________

~-r-------------------~~~------------------------L _____
~------------~/

-3
-3
0

CLRF~

• ADDR STROBE
ENA(O),
ADD 2
ENB(O),
SELECT

-3
0

-3
-3

10 OVFLO

___----'I
(IF REQUIRED)

IOP2
0
DATA
AVAILABLE

\'-------

600NS
r----~
_______
SE_T_U_P_T_IM_E~/
\~________________~/

-3

\'--__________/

'---.----'

\~---

. ~.----.--------------~
, D~TA STROBE

~--------------

______________~r--\~____________________________________
~

-3

r-\

500 NS SETUP TIME
(I'S ARE OV)

------------------------------------------~I~.....--A \~______
500~NS

-3
IOP4
0

MIN

-------------------------------------------------------,
Figure 14-5

DCR Timing

TABLE 14-2 STANDARD CORE REGISTER ASSIGNMENT

'Nord Count

Initial Address

DEC tape

Magtape

lnterprocessor Buffers

Not presently assigned

Device

14-6

CHAPTER 15
INSTALLATION PLANNING
GENERAL
This chapter describes the physical dimensions
of a basic PDP-9/L and expander cabinets. Power
requirements, heat produced, and the physical
sizes of options are detailed in tables 15-1 through
15-3. Several typical configurations are shown.
PHYSICAL CONFIGURATION
The basic PDP-9/L is housed in a single cabinet,
32-Y2 in. wide (with end panels), 27-% in. deep,
and 69-V2 in. high. The operator's table projects forward 22 in. and a rear clearance of 31
in. is needed for access to the logic. Physical
dimensions of the basic PDP-9/L are shown in
figure 15-1.
The PDP-9/L .is painted black, with grey end
panels, and has a red accent panel on the front.
The rear door also contains a red accent stripe.
A black chair is supplied with the PDP-9/L.
In the basic PDP-9/L cabinet, the paper tape
reader/punch and operator's console are rnounted
on the front, while most of the logic is mounted
on the rear door. In the center of the front is
an operator's console, with the standard paper
tape reader/punch unit mounted above and a table
mounted below. The power supplies are underneath the table. Behind the red accent door, to
the left of the paper tape reader/punch, is the
marginal check panel, the maintenance panel, and
the console lock switch. Above the paper tape
reader/punch unit, space is reserved for the Type
ME09B Option Panel which contains the wiring
for the Type KG09A Memory Extension Control,
and the Type KX09A Memory Protection Option.
Figure 15-2(A) shows the front of the PDP-9/L
cabinet.
Most of the PDP-9/L logic is contained on the
rear door (see figure l5-2(B)). The logic is contained on three wire-wrapped frames, self-contained, with fans, fuses, and marginal check switches.
The top frame contains a 16,384 word memory
wing, the center frame is the central processor,
while the bottom frame contains the I/O logic.
These three frames are bolted together to form
a solid door, and connections are made from
frame to frame with ribbon cables. Hold-down
bars are available as an option.

Cooling is accomplished by the fans built into
the frames. Air is sucked in'through vents in
the rear door, blown past the logic by the fans,
and exits through vents in the top of the cabinet.
Several options are wired into the frames of the
basic PDP-9/L for easy implementation. The central processor frame contains the logic for the
Exterided Arithmetic Element, Type KE09A. The
I/O frame has the Automatic Priority Interrupt,
Type KF09A, the Power Failure Protection Option,
Type KP09 A, and the Oscilloscope Display Control,
Type 34H, already wired in. Space is reserved in
the basic cabinet for the Type ME09B (KG09A,
KX09A) option to keep it as close as possible to
the central processor logic.
Memory above 8192 words is expanded by adding the Memory Extension Control, Type
KG09 A (housed in the Type ME09B option
above the paper tape reader/punch), and extra
memory logic in the memory wing. The second
16,384 words of memory are housed in a
second 32-inch cabinet to the left (facing the
system) of the basic PDP-9/L. This is shown
in figure 15-3. The cabinet contains room for
the second 16,384 words of memory on the
front door, while power supplies are mounted
in the rear. The rear door of this additional
32-inch cabinet also contains a red stripe, but
the front door is solid black.
Other options are added to the PDP-9/L by
attaching standard 19-inch cabinets to the right
of the basic cabinet (facing it). The dimensions
of these cabinets are shown in figure 15-4.
Connections to these options are made from the
PDP-9/L I/O logic via I/O Bus Cables, Type
BC09A. Figure 15-5 shows a one-bay expansion
of a PDP-9/L with the addition of a DECtape
Control, Type TC02, and four (4) DEC tape
Transports, Type TV 55.
Several options, including the Type 30D, and
the Type TU20 and TU20A tape transports,
are composed, in part, of free-standing units. _
These are housed in one or more 19-in. cabinets
and are interfaced to the PDP-9/L via 25-ft.
cables.
15-1

27 3/4

493/4

~~-- 32 1/2 -----t.,~

691/8

277/16

Figure 15-1. Basic PDP-9/L Cabinet Specifications
PLACEMENT OF OPTIONS

PDP-9/L systems are assembled according to the
following guide-lines*:
*Customers may request deviations fronl these
procedures at extra cost.
15-2

1. Cabinets are numbered 0 through n (or
1 through n, if no extra memory is required),
with the numbers always running from left to
right (figure 15-6), and the central processor
cabinet is always designated no. 1. Bays 0
and I are 31-in. cabinets, and 2 through n are
19-in., cabinets. All cabinets except no. 1 have

RESERVED FOR

ME09B*

MARGINAL
CHECK
MAINTENANCE
PANEL

D
rJ

POWER

COVERS

SUPPLY

OFF

RED
DOOR

OPERATOR'S

COVER

COVERS

CONSOLE

PANEL

Figure lS-2(A). Basic PDP-9/L (Front)
15-3

16K
MEMORY

....
14718

FANS + FUSES
CENTRAL
PROCESSOR

+ MARGINAL
CHECK

SWITCHES

5011/16
271/16

I/O
PACKAGE
83/4

........- - 221/4 -

Figure 15-2 (B). Basic PDP-9/L (Rear, Back Door
Removed)

-69 1/8

..-

..L()

1---14----

64"

--...

Figure 15-3. PDP-9/L With Extra Memories (Front)
their logic mounted on the front. The 19-in.
cabinets can hold eleven standard 5%-in.
mounting panels of logic; these are lettered
A through K. The bottom panel space cannot be utilized ..

15-4

Figure 15-4. 19-Inch Cabinet Specifications
2. The options listed below are wired in and
require no additional space.
a. Extended Arithmetic Element, Type
KE09A

BASIC

- - - - - - - - - r - - - r - - - - , - - - - - -.., - - - - - - r - - - - -..,

_____ J ______ ~ _____ JA

PDP-9/L

L7o~

DDDDD

~---4

00 ===:J
L7o~

I B

-----..,------,-----,

_____ J ______ ~ _____ JO
I

-----~------'_-----4

DDLJOO

00 ===:J
L7o~

----~------~-----4

r---~

UP TO

DD~DD

===:J

DEC TAPE
TRANSPORTS

L7o~

D[)~DD

4 TU55

1---------

-----~------~-----~G

=====J======[=====~H
I

-----~------~-----..,

_____ ~------~-----JJ
I

00 ~

I K

---------~~--~

Figure 15-6 Cabinet Configurations
DEC TAPE CONTROLS
(BEHIND COVERS)

1 4 1 . f - - - - - - - - 5 3 1 1 2 " - - - - -___
.. 1

Figure 15-5

PDP-9/L with DECtape and PC09A

b. Automatic Priority Interrupt, Type
KF09A
c. Power Failure Detection Option
Type KP09A
d. Oscilloscope Display Control
Type 34H
3. Several options requiring additional logic
will also be housed in bay no. 1, in 19-in.
mounting panels, above the paper tape reader/
punch unit. The Memory Extension Control,
Type KG09 A, and the Memory Protection Option, Type KX09 A are wired into one pair of
panels (Type ME09B) which fit in the two
spaces immediately above the reader/punch unit.
4. All memory in excess of 16,384 words is
housed in bay no. O. No other options are
permitted in this cabinet.
5. All cabinet-mounted input/output options
and interfaces to free-standing options are
housed in bays no. 2 through n, with the
following priorities governing proximity to the
central processor.
a. DECtape
b.

All other standard DEC options

Special systems built by DEC

Special systems (or the cabinets for
them) built by customers.

6. DECtape, when included in the system
will occupy bay no. 2 and, if necessary, bay
no. 3. Even if the DECtape does not completely fill bay no. 2, no other options will
be permitted in the bay with it. This allows
room for expansion of the DECtape system.
If bay no. 3 is also used for DECtape, the
bottom three panels (I through K) are available for other options (figures 15-7 and 15-8).
7. Oscilloscope displays are mounted at the
top of the cabinet closest to the central processor after DEC tape (see figure 15-9).
8. Analog-to-digital converters and output
relay buffers are mounted as near to the top
of the cabinets as possible.
9. Interfaces to large-screen CRTs, card readers, line printers, and interprocessor buffers
will be mounted as low as possible to shorten
the length of external cables going out of the
bottom of the cabinet.
10. Magnetic Tape Controls, Type TC59, will
be mounted at the bottom of the cabinet and
as far to the right as possible (figure 15-9).
ENVIRONMENTAL REQUIREMENTS
PDP-9/L systems operate satisfactorily under
ordinary conditions of humidity, shock, and vibration. They are tested in the plant between
50 degrees and 122 degrees F. The best operating temperatures, however, are between 70 degrees and 85 degrees F and a humidity between
30 and 80% are recommended. If room air conditioning is planned, consult tables 15-1 through
15-3 for heat outputs of the system components.

15-5

TU 55 III 4

RESERVED
FOR
ME09B*

TU55*3

PAPER TAPE
READER AND
PUNCH

TU55# 2

OPERATOR'S
CONSOLE

TU55"" 4

TlI 55#E!:

ME09B*
KG09A

TU!55# 3

TU 55# 7'

PAPER TAPE
READER AND
PUNCH

TU55f1f6 2

TU 55# 6,

OPERATOR'S
CONSOLE

TU55# 1

EXTRA 16K
MEMORY

r-----------

TU55# 1

TABLE

TC02

AVA IlABlE
FOR
01THER·.
OF' T10NSi

TC02

>< ""
"

Figure 15-8 Memory Expansion and
DECtape Expansion

Figure 15-7 Basic PDP-9/L with
DECtape and PC09 A
POWER REQUIREMENTS

lent) to mate with equipment power cables. Exceptionally large PDP-9/L systems may require 50
amp sources. If in doubt, consult tables 15-1
through 15-3 or your DEC representative.

The PDP-9/L requires a source of liS-v, 60-Hz,
single-phase power. Upon order, all equipment
can be factory-wired for 50 Hz at 115, 230, or
250 v. The power source must maintain the nomi- All free-standing cabinets, magnetic tape transports,
card readers, line printers, etc.) require independent
nal voltage to ± 10% and the frequency to + 0.5
115v (or equivalent) receptacles. Power on/off,
Hz. The electrical characteristics of individual
components are given in tables 15-1 through 15-3.
however, will be under control of the PDP-9/L
console switch.
CABLING REQUIREMENTS
Cables are connected to cabinets through drop
Most PDP-9/L systems will require 115v, 30 amp,
panels in the cabinet bottoms. Sub-flooring is
Hubbel Twistlock flush receptacles (or their equivanot necessary because the ca.binets are elevated

RESERVED
FOR

RM503
SCOPE

ADDITIONAL
ME09B

AF01B
TU5S'S
TU5S".. 2

OPERATOR'S
CONSOLE
TABLE

TUSS,..'

AVA!ABLE
~t

•

i
TC02
I

TCS9
I

><><=

-ME09B IS TWO·PANEL OPTION CONTAINING WIRING FOR KG09A AND KX09A

Figure 15-9 Typical PDP-9/L System
15-6

OPTIONS

INDICATOR
PANELS

"'- "-...
,.......,.. f.....
-----I

FRENCH
DOORS

SNAP-ON
FULLLENGTH
SINGLE
DOORS

/
69 7/8"

.---

COVERS

1------tV
¥

I--HANDL~ ---.
ON LEFT,
HINGED
ON RIGHT

--.JL ll:::::====::::iJ
1~'9 3/4~

221/4

CAB- 1 B

-1

CAB - 9A

CAB-9B

CAB-9C

CAB- 90

Figure 15-10 Cabinet Configurations

sufficiently by feet or casters to allow clearance
for the cables.

CAB-1B:

French doors front and rear;
without indicator panel.

ADDING SPECIAL INTERFACES

CAB-9A:

single full doors front and rear;
without indicator panel.

CAB-9B:

single full doors front and rear;
with indicator panel.

CAB-9C:

black snap-on covers front, full
single door rear; without indicator panel.

CAB-9D:

black snap-on covers front, full
single door rear; with indicator
panel.

Special interfaces may be constructed by using
compatible FLIP CHIP modules and mounting
hardware (see Digital Logic Handbook, C-l 05,
for details).
A choice of cabinets is available for use with
PDP-9/L systems. All hold standard FLIP CHIP
mounting hardware (19-in. panels) and are available with or without end penels. Rotary fans
are contained in the bottom, and power supplies
may be purchased for mounting on the rear
plenum doors.
The available cabinet options are illustrated in
figure 15-10. A brief description of each is
as follows:

All special interfaces should be designed to interface to the PDP-9/L I/O bus by using I/O bus
cables, Type BC09 A.

15-7

TABLE 15-1 PDP-9/L, EXTRA MEMORY. FREE-STANDING OPTIONS AND THEIR CONTROLS

Name

Cabinet Dimensions
Height Width Depth
(in.) (in.). (w/table)

Standard PDP-9/L

69-1/8

Magnetic Tape Transports, Type TU20
TU20A

69-1/8

22-1/4 27-1/16

200 cpm Card Reader,
Type CR02B

Line Printer, Type 647

52-57

Incremental Plotter,
Calcomp Model 563
Calcomp Model 565

9-3/4
9-3/4

Options
Required

Service
Clearance
Weight Front Rear
(lb.)
(in.) (in.)
900

Chair
Space

TC59

400

DA09A*

200

30-114

DA09A*

1350

39-3/8
18

14-3/4
14-3/4

350
350

53
53

DA09A*

350

Precision CRT, Type 343 69-1/8
Type 300

22·1/4 51

Slave Display, Type 343

69-1/8

22-1/4 51

Data Communications
System, Type 680

(See 680 Handbook)

Empty Cabinet

69-1/8

22-1/4 27-1/16

Height of
AC Current
Heat
Interface
Nominal Surge Dissipation
(19 in. logic) (amps) (amps) (btufhr)
17

2300

0.62

10 ft

6-5/8

1.3

7.0

495

0.15

10 ft

2700

1.56

10 ft

DB98A

See TC59

See 350
Control

1.12
1.5

2
3

425
580

0.125
0.17

10 ft
10 ft

5-1/4

3140

0.9

25 ft

2350

0.69

25 ft

See
DB98A
100

Power
Cable
Dissipation Length
(kw)

Comments

Op. Temp.
55-100o F
Humidity
25-95%

12 ft

*No charge for required options marked with an asterisk (*).

00
I

.....
V)

TABLE 15-2 WIRED-IN OPTIONS

Name

Included In

AC Current (amps)
Surge
Nominal

Heat Dissipation
(btu/hr)

Power Dissipation
(kw)

Extended Arithmetic
Element, Type KE09A

PDP-9
CPU

108

0.032

Automatic Priority
Interrupt, Type KF09A

PDP-9
I/O Logic

0.018

Power Failure Detection,
Type KP09A

PDP-9
I/O Logic

0.021

Oscilloscope Display Control
Type 34H

PDP-9
I/O Logic

408

0.012

Memory Extension Control
Type KG09A

ME09B

0.030

Memory Protection Option,
Type KX09A

ME09B

0.008

Included in Basic
PDP-9/L Power
System

15-9

TABLE 15-3 HARDWARE AND LOGIC OPTIONS FOR 19-INCH CABINETS

Logic
Height
(in.)

Number of
Mounting
Paneis

Parity-E xtension-Protection
Chasis, Type ME09B

10-1/2

I/O Bus Adapter, Type DA09A

10-1/2

0.44

0.8

156

0.046

IPB, Type DB99A

10-1/2

0.39

0.72

133

0.042

IPB, Type DB98A
PDP-9 End
PDP-B End

10-1/2
10-1/2

2
2

0.39
0.31

0.72
0.6

133
111

0.042
0.032

IPB, Type DB97A
PDP-9/L End
PDP-7 End

5-1/4
5-1/4

0.29

0.54

0.031

0.47

0.86

170

0.050

0.60

1.0

207

0.058

0.5

3.0

410

0.170

2.0

5.0

1000

0.23

0.014

100

0.029

Name

Options
Required

Approx
Weight
(ib.)

Output Relay Buffer,
Type DR09A

5-1/4

DECtape Controi, Type TC02

15-3/4

DECtape Transport,
Type TU55

10-1/2

Magnetic Tape Control,
Type TC59

Incremental Plotter Control,
Type 350

10-1/2

Teletype Control, Type L T09A

10-1/2

Bit Sync Data Comm. System,
Type 637 (DP09A, DP01 Bl

TC02

LT09A
10-1/2

Heat
Dissipation
(btu/hr)

Power
Dissipation
(kw)

Comments

Line Unit, Type L T09B

AC Current (amps)
Nominal
Surge

0.13

0.24

0.27

0.50

o
I

lI)

APPENDIX 1
INSTRUCTION SUMMARY

MEMORY REFERENCE INSTRUCTIONS
Mnemonic
Symbol

Octal
Code

Machine
Cycles

Operation
Executed

CAL

Ca II subroutine. The address portion of th is instruction is ignored. The action is identical to
JMS 20.

DAC Y

Deposit AC. The content of the AC is deposited
in the memory cell at location Y.

JMS Y

Jump to subroutine. The content of the PC and
the content of the L are deposited in memory cell
Y. The next instruction is taken from cell Y + 1 •

DZMY

Deposit zero in memory. Zero is deposited in
memory cell Y.

LAC Y

Load AC. The content of Y is loaded into the AC.

XORY

Exclusive OR. The exclusive OR is performed between the content of Y and the content of the AC,
with the result left in the AC.

ADD Y

Add (lis complement). The content of Y is added
to the content of the AC in lis complement arithmetic and the result is left in the AC.

TAD Y

Twols complement add. The content of Y is added
to the content of the AC in 2 1s complement arithmetic and the result is left in the AC.

XCTY

Execute. The instruction in memory cell Y is executed.

ISZ Y

Increment and skip if zero. The content of Y is incremented by one in 2 1s complement arithmetic. If
the result is zero, the next instruction is skipped.

AND Y

AND. The logical operation AND is performed between the content of Y and the content of the AC
with the result left in the AC.

Al-1

MEMORY REFERENCE INSTRUCTIONS (continued)
Mnemonic
Symbol

Octal
Code

Machine
Cycles

Operation
Executed

~==================================:===========================================

SAD Y

JMP Y

Skip if AC is different from Y. The content of Y is
compared with the content of the AC. If the num-'
bers are different, the next instruction is skipped.
Jump to Y. The next instruction to be executed is.
taken from memory ce II Y.

EAE INSTRUCTION LIST
Mnemonic
Symbol

Octal
Code

Operation
Executed

EAE

640000

Basic EAE command. No operation.

LRS

640500

Long right sh ift.

LRSS

660500

Long right shift, signed (AC sign = link).

LLS

640600

Long left sh ift.

LLSS

660600

Long left shift, signed (AC sign = L).

ALS

640700

Accumulator left sh ift.

ALSS

660700

Accumulator left shift, signed (AC sign = L).

NORM

640444

Normalize, unsigned. Maximum shiff' is 44 •
S

NORMS

660444

Norma lize, signed (AC sign = L).

MUL

653122

Multiply, unsigned. The number in the AC is multiplied by the number in the next c;ore memory address.

MULS

657122

Multiply, signed. The number in the AC is multiplied by the number in the next core memory address.

DIY

640323

Divide, unsigned. The 36-bit content o~f both the AC
and MQ is divided by the number in tlhe next core
memory location.

DIVS

644323

Divide, signed. The content of both the AC and MQ
as a lis complement signed number is divided by the
number in the next core memory location.

Al-2

EAE INSTRUCTION LIST {continued}
Mnemonic
Symbol

Octal
Code

Operation
Executed

IDIV

653323

Integer divide, unsigned. Divide the number in the
AC as an l8-bit unsigned integer by the number in the
next core memory location.

IDIVS

657323

Integer divide, signed. Same as IDIV but the content
of the AC is a 17-bit signed number.

FRDIV

650323

Fraction divide, unsigned. Divide the 18-bit fraction
in the AC by the 18-bit fraction in the number in the
next core memory location.

FRDIVS

654323

Fraction divide, signed. Same as FRDIV, but the content of the AC is a 17-bit signed number.

LACQ

641002

Replace the content of the AC with the content of the
MQ.

LACS

641001

Replace the content of the AC with the content of the
SC.

CLQ

650000

Clear MQ.

ABS

644000

Place absolute value of AC in the AC.

GSM

664000

Get sign and magnitude. Places AC sign in the I ink
and takes the absolute value of AC.

OSC

640001

Inc I usive OR the SC into the AC.

OMQ

640002

Inclusive OR AC with MQ and place results in AC.

CMQ

640004

Complement the MQ.

LMQ

652000

Load MQ.

INPUT/OUTPUT TRANSFER INSTRUCTIONS
Mnemonic
Symbol

Operation
Executed

Octal
Code
Program Interrupt

IOF

700002

Interrupt off. Disable the PIC.

ION

700042

Interrupt on. Enable the PIC.

Al-3

INPUT/OUTPUT TRANSFER INSTRUCTIONS (continued)
Mnemonic
Symbol

Octal
Code

Operation
Executed

=== ==============================:======================================-==
Rea I Time Clock
CLSF

700001

Skip the next instruction if the clock flag is set to 1 •

CLOF

700004

C lear the c lock flag and disable the clock.

CLON

700044

C lear the c lock flag and enable the clock.
Perfolrated Tape Reader

RSF

700101

Skip if reader is a 1 •

RCF

700102

Clear reader flag, then inclusively OR the content of
reader buffer into the AC •.

RRB

700112

Read reader buffer. C lear reader flag and AC, and
then transfer content of reader buffer into AC.

RSA

700104

Select reader in a Iphanumeric mode. One 8-bit char'acter is read into the reader buffer.

RSB

700144

Select reader in binary mode. Three 6-bit characters
are read into the reader buffer.
Perforated Tape Punch

PSF

700201

Ski P if the punch flag is set to 1 •

PCF

700202

C lear the punch flag.

PSA or
PLS

700204
700206

Punch a line of tape in alphanumeric mode.

PSB

700244

Punch a line of tape in binary mode.
~/O Equipment

IORS

700314

Input/output read status. The content of given flags
replace the content of the assigned AC bits.

TTS

703301

Test Teletype and skip if KSR 33 is connected to
computer.

CAF

703302

C Iear a II flags.

SKP7

703341

Skip if processor is a PDP-7 or PDP-9

Al-4

INPUT/OUTPUT TRANSFER INSTRUCTIONS (continued)
Mnemonic
Symbol

Operation
Executed

Octal
Code
Teletype Keyboard

KSF

700301

Skip if the keyboard flag is set to 1 •

KRB

700312

Read the keyboard buffer. The content of the buffer is
placed in AC10-17 and the keyboard flag is cleared.
Teletype Teleprinter

TSF'

700401

Skip if the teleprinter flag is set.

TCF

700402

C lear the te leprinter flag.

TLS

700406

Load teleprinter buffer. The content of AC 10-17 is
placed in the buffer and printed. The flag is cleared
before transmission takes place and is set when the
character has been printed.

Types 30 and 34 Oscilloscope and Precision CRT Displays
DXC

700502

Clear the X-coordinate buffer.

DYC

700602

Clear the V-coordinate buffer.

DXL

700506

Load the X-coordinate buffer from AC8-17.

DYL

700606

Load the Y -coordi nate buffer from AC8-17 •

DXS

700546

Load the X-coordinate buffer and display ·the point
specified by the XB and VB.

OYS

700646

Load the V-coordinate buffer and display the point
specified by the XB and VB.

DSF

700501

Skip if display flag = 1 •

OCF

700702

Clear display flag.

OLB

700706

Load the brightness register from AC 15-17 • (for Type 30)

700704

Load the brightness register from AC 16-17. (for Type 34)

Al-5

INPUT/OUTPUT TRANSFER INSTRUCTIONS {continued}
Mnemonic
Symbol

Operation
Executed

Octal
Code

Type AF01 B Analog-to-Digital Converter and Multiplexer
ADSM

701103

Select MX channel. The content of AC 12-17 is placed
in MAR.

ADIM

701201

Increment channel address. The content of the MAR is
incremented by 1. Channel 0 follows channel 77 .
8

ADRM

701212

Read MAR into AC12-17.

ADSF

701301

Skip if converter flag is set.

ADSC

701304

Select and convert. The converter flag is cleared and
a conversion is initiated.

ADRB

701312

Read converter buffer. Places the content of the buffer
into the AC.

Type 139E General Purpose Multiplexer Control
ADSM

701103

Select MX channel. The content of AC 12-17 is placed
in the MAR.

ADIM

701201

Increment channel address. The content of the MAR is
incremented by 1. Channel 0 follows channe I 77 ,
8

ADRM

701212

Read MAR into AC

_ .
12 17

Type 138E Analog-to-Digital Converters
ADSF

701301

Skip if converter flag is set.

ADSC

701304

Select and convert. The converter flc:Jg is cleared and
a conversion is initiated.

ADRB

701312

Read converter buffer.
in the AC.

Places .the content of the buffer

~ DR09A Relay Buffer

ORC

702101

Clear output relay buffer flip-flop reigster.

ORS

702104

Set output relay buffer flip-flop regis"ter to correspond
with the contents of the accumu lator.

Al-6

INPUT/OUTPUT TRANSFER INSTRUCTIONS (continued)
Mnemonic
Symbol

Operation
Executed

Octal
Code

Type 350 Incremental Plotter and Control
PLSF

702401

Skip if plotter flag is a 1 •

PLCF

702402

C lear plotter flag.

PLPU

702404

Plotter pen up. Raise pen off of paper.

PLPR

702421

Plotter pen right.

PLDU

702422

Plotter drum (paper) upward.

PLDD

702424

Plotter drum (paper) downward.

PLPL

702441

Plotter pen left.

PLUD

702442

Plotter drum (paper) upward.

PLPD

702444

Plotter pen down.

Lower pen on to paper.

Type KF09A Automatic Priority Interrupt
SPI

705501

Skip on priorities inactive.

ISA

705504

Initiate selected activity.

DBK

703304

Debreak.

DBR

703344

Debreak and restore.
Type 647 Line Printer

LSDF

706501

Skip if the DONE flag is set.

LPCB

706502

Clear the DONE flag, c lear control print buffer, enable
DONE interrupt, initiate a clear sequence in the hue
printer, set the DONE flag when the clear sequence is
finished.

*LPDl

706504

Disable DONE flag interrupt.

706522

Clear DONE flag.

*These instructions have been added to the Line Printer command set to allow enabling and disabling of
the interrupt. Since power clear returns the system to the interrupt enabled condition programs generated
for the PDP-71ine printer (647B) , which does not have these instructions, will run correctly.

Al-7

INPUT/OUTPUT TRANSFER INSTRUCTIONS {continued}
Mnemonic
Symbol

Operation
Executed

Octal
Code

706542

Clear DONE flag.

706562

Clear DONE flag.

lPL2

706526

L.oad printing buffer with two characters; clear DONE
FLAG: THE CONTENTS OF AC6-11 and AC12-17 are
transferred to the printing buffer as 6-bit bytes in that
order. The DONE flag wi II be set when the load sequence
is finished.

LPLD

706546

l.oad the printing buffer with three characters. The DONE
flag is cleared; the contents of AC 0-5,6-11, and 12-'17
eIre transferred as 6-bi t bytes into the pri nti ng buffer in that
order. The DONE flag is set at the completion of the load
sequence.

LPL 1

706566

l.oad the printing buffer with one character; clear DONIE
flag; the contents of AC 12- 17 are transferred as a 6-bi t
byte into the printing buffer. The DO~IE flag is set at the
completion of the load sequence.

LPEF

706601

Skip if the ERROR flag is set.

LPCF

706602

Clear DONE flag.

706622

Clear DONE flag.

706642

Clear DONE flag.

706662

Clear DONE flag.

LPPB

706606

Select printer and initiate printing. The DONE flag is
cleared; the contents of the pri nti ng buffer are pri nted;
the printing buffer is cleared; the DONE flag is set when
tlhe printing sequence is completed.

L.PLS

706626

Load spacing buffer and space; the DONE flag is cleared;
the contents of AC 15-17 are transferred into the spac in~J
buffer; the paper is spaced vertically according to the format selected; the spacing buffer is cleared; the DONE flag
is set.

l.PPS

706646

Print and space. This instruction accomplishes the com-'
bined actions of LPPB and LPLS instructions. The DONE
fllag is cleared; the contents of AC 15-17 are transferred
to the spacing buffer; the contents of the printing buffer
are printed; the paper is spaced vertically; the printing
and spacing buffers are cleared; the DONE flag is set
upon completion.

Al-8

INPUT/OUTPUT TRANSFER INSTRUCTIONS (continued)
Mnemonic
Symbol

Octal
Code

* lPEI

706664

Operation
Executed

The DONE flag interrupt is enabled.
Type CR02B Card Reader

CRSB

706744

Select and read a card in binary mode. A card is started
through the reader and 80 columns are read as 12-bit numbers. The card done flag is cleared.

CRSA

706704

Select and read a card in alphanumeric mode. A card is
started through the reader and 80 columns are read in 6-bit
BCl codes.

CRRB

706712

Read the card reader buffer into AC bits 6-17. The column
flag is cleared.

CRSF

706701

Skip on column data ready flag.

CRSD

706721

Skip on card done flag.

CRSR

706741

Skip on reader ready condition.

CREF

706761

Skip on reader EOF flag.

CRCD

706724

Clear done flag.
Tl~e TC59 Taee Control lOT Instructions

MTSF

707301

Skip on error flag or magnetic tape flag (EF and MTF).

MTCR

707321

Skip on tape control ready (TCR).

MTTR

707341

Skip on tape transport ready (TTR).

MTAF

707322

Clear status and command registers and EF and MTF.

707324

Inc lusive Iy OR content of AC _
into command register.
O 11

707326

Load content of AC _ into command register.
O 11

MTLC

*These instructions have been added to the Line Printer command set to allow enabling and disabling of
the interrupt. Since power clear returns the system to the interrupt enabled condition programs generated
for the PDP-7 line printer (647B), which does not have these instructions, wi II run correctly.

Al-9

INPUT/OUTPUT TRANSFER INSTRUCTIONS (continued)
Mnemonic
Symbol

Octal
Code

Operation
Executed

Type TC59 Tape Control lOT Instructions (continued)
707356

Terminate write continuous mode.

707342

Inc Iusive Iy OR content of status regi ster into AC _

707352

Read content of status register into AC _

707302

Inclusively OR content of command register into AC _

MTRC

707312

Read command register into AC _ .
O 11

MTGO

707304

Set "go" bit to execute command in command register.

MTCC

MTRS

O 11

•

O 11

TC02 DEC-tape Control lOT Instructions
DTCA

707541

Clear status register A.

DTRA

707552

Read status reg i ster A.

DTXA

707544

XOR status register A.

DTLA

707545

Load status register A.

DTEF

707561

Skip on error flag.

DTRB

707572

,Read status B.

DTDF

707601

Skip on DECtape flag.
KG09A Memory Extension Control

SEM

707701

Skip if in extend mode.

EEM

707702

Enter extend mode.

LEM

707704

Leave extend mode.

KX()9A Memory Protection
MPSNE

701741

Skip on NonExistent Memory Flag

MPSK

701701

Skip on Violation Flag

MPEV

701742

Enter Protect Mode

MPCV

701702

Clear Violation Flag

A1-10

•

INPUT/OUTPUT TRANSFER INSTRUCTIONS (continued)
Mnemonic
Symbol

Octal
Code

Operation
Executed
KX09A Memory Protection (continued)

MPCNE

701744

Clear NonExistent Memory Flag

MPLD

701704

Load boundary register from AC _
3 7
KP09A Power Failure Protection
Skip if Power-Low Flag is set

703201

OPERATE INSTRUCTIONS
Mnemonic
Symbol

Octal
Code

OPR or
NOP

740000

CMA.

740001

Complement accumulator.
plemented.

CML

740002

Complement link.

OAS

740004

Inclusive OR ACCUMULATOR switches. The word set
into the ACCUMULATOR switches is OR combined with
the content of the AC, the result remains in the AC.

RAL

740010

Rotate accumulator left. The content of the AC and L
are rotated one position to the left.

RAR

740020

Rotate accumulator right. The content of the AC and L
are rotated one position to the right.

HLT

740040

Halt. The program is stopped at the conclusion of the
cycle.

SMA

740100

Skip on minus accumulator. If the content of the AC is
negative (2 1 s complement) number the next instruction is
skipped.

SZA

740200

Skip on zero accumulator. If the content of the AC
equals zero (2 1s complement), the next instruction is
skipped.

SNL

740400

Skip on non-zero Iink. If the L contains a 1, the next
instruction is skipped.

Event
Time

Operation
Executed
Operate group or no operation. Causes a 1-cyc Ie program delay.

A 1-11

Each bit of the AC is com-

OPERATE INSTRUCTIONS {continued}
Event
Time

Operation
Executed

Mnemonic
Symbol

Octal
Code

SKP

741000

Skip. The next instruction is unconditIonally skipped ..

SPA

7411 00

Skip on positive accumulator. If the content of the AC
is zero {2 1 s complement} or a positive number, the next
instruction is skipped.

SNA

741200

Skip on non-zero accumulator. If the content of the AC
is not zero {2 1s complement}, the next instruction is
skipped.

SZL

741400

Skip on zero I ink. If the L contains a 0, the next instruction is skipped.

RTL

742010

2,3

Rotate two left. The content of the AC and the L are
rotated two positions to the left.

RTR

742020

2,3

Rotate two right. The content of the AC and the L ar~e
rotated two positions to the right.

CLL

744000

C lear link. The L is cleared.

STL

744002

2,3

Set link. The L is set to 1.

RCL

744010

2,3

Clear link, then rotate left. The L is cleared, then the
Land AC are rotated one position left.

RCR

744020

2,3

C lear I ink, then rotate right. The L is cleared, then the
Land AC are rotated one position right.

CLA

750000

Clear accumulator. Each bit of the AC is cleared.

CLC

750001

2,3

C lear and complement accumulator. Each bit of the AC
is set to contain a 1 •

LAS

750004

2,3

Load accumu lator from switches. The word set into the
ACCUMULATOR switches is loaded into the AC.

GLK

750010

2,3

Get Iink. The content of L is set into AC 17.

LAW N

76XXXX

Load the AC with 76XXXX.

A1-12

APPENDIX 2
PDP-9 I/O CODES

MODEL 33, 35 ASR/KSR TELETYPE CODE (ASCII) IN OCTAL FORM

Character

A
B
C
0
E
F

a-Bit Code
(in Octal)

301
302
303
304
305
306
307
310
311
312
313
314
315
316
317
320
321
322
323
324
325
326
327
330
331
332

0
1
2
3
4
5
6
7
a
9

260
261
262
263
264
265
266
267
270
271

G
H
I

J
K
L
M
N

0
P
Q
R
S
T

U
V
W
X
Y

Character

$
0/0

<
=

>
?
@
[

/
J

a-Bit Code
(in Octal)
241
242
243
244
245
246
247
250
251
252
253
254
255
256
257
272
273
274
275
276
277
300
333
334
335
336

337
Leader/Trai ler
200*
Line-Feed
212*
215
Carriage-Return
240
Space
Rub-out
377*
Blank
000*
375
ALT Mode
* Ignored by the operating system

A2-1

(!] "" HOLE PUNCHED - MARK .. , BIT

MOST SIGNIFICANT BIT

o - NO HOLE PUNCHED - SPACE· 0 BIT

LEAST SIGNIFICANT BIT

8 7 654 S 3 2 ,

IA,* SP"ACE
~*
r----~

r--c

7
7

--0

f--c;-

f---

~
r----J

r----a*
r--;-- *
~*
~*
r----

r---;-

• *
r---+
I------

t----!--

r-c-

r----

~
~

f--'-

~
V

t-w

rx
~
r-z

f--'-

ACK
ALT MODE
RUB OUT
j

f---

0 0

LINE FEED

0
0
0
0
0
0

ARE YOU (RU)

VERTICAL TAB
FORM FEED

: READER ON

~
~

READER OFF
(AUX OFF)

TAPE (AUX ON)

f----

~
~

ERROR
SYNCHRONOUS IDLE
LOGICAL END OF MEDIA

~
~

f----

I * ~r-:
-r- *

•

0 0
0
0

•

• •o
•o

•• •• •
•• •• •• o•
o
•o
••
•
• o•
••• •• •o
o
•
•• • •o
•• • • •o
• •
••• •• •• o•
0

0
0

0 0
0 0

0
0

0 0
0 0

r---7-

•
•
••

0 0
0

0
0

+:* +- *

HORIZONTAL TAB

WHO ARE YOU (WRU)

r---!:--

J'"

BELL
FORMAT EFFECTOR

END OF MESSAGE (EOM)
END OF TRANSMISSION (EOT)

DCO

I-----2

• o•
•
•• o•
•• •• •o
o

SHIFT IN

r---o-

0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0

START OF MESSAGE
END OF ADDRESS (EOA)

CARRIAGE RETURN
SHIFT OUT

r--o
r---Tr--p-

r---o

NULL (IDLE)

0
0

S4
S5
S6
S7
j

.-J

NON-TYPING

* OBTAINED WITH SHIFT KEY

A2-2

,
..-~
•
. •• • •
•••
0 0
0

SAME
SAME

TELETYPE CODE COMPARISON
Character
Name

Flexowriter
FIODEC Code

28 KSR
Baudot Code

33 or 35 KSR
ASCII Code

0-9

a-z
A-Z

A-Z
$A-$Z

A-Z
A-Z

;

(

)

&
!

)
+
t

period
minus sign
center dot, period
center dot, comma

multiply

t
x

*
"

$"
$'
$:
$(

<
>

$$&
$?
$,
$/

<
>

$;
$!

::>

vertical stroke
underbar
center
overbar

0/0
!
&

none

#
stop code
.

tab

A2-3

none

form feed

~e~1

tab

LINE PRINTER ASCII CODE IN OCTAL FORM
Character

A
B
C
D

6-Bit Trimmed
Code
(in octal)

Character

6
7

G
H

01
02
03
04
05
06
07
10

0/0

J
K

12
13
14
15
16
17
20
21
22
23
24
25
26
27
30
31
32
60
61
62
63
64
65

L
M
N
0

P
Q

R
S
T
U
V
W
X
Y
Z

0
1
2
3
4
5

8
9
II

*
+

<
=

>
?
@
[

]

Space

A2-4

6-Bit Trimmed
Code
(in octal)
66
67
70
71
41
42
43
44
45
46
47
50
51
52
53
54
55
56
57
72
73
74
75
76
77
00
33
34
35
36
37
40

TYPE CROl E CARD READER, INTERNAL ALPHANUMERIC CODES

~2110

ZONE

~:9~~--~N~0~P~u-nc~h------'-------~0~----~------~1~1------~--~1~2----~
No Punch

Internal
00*

029
Blank

026
Blank

Interna I 029 026
60
& + [&j

Internal
20*

029
0

026
0

Internal
40

029
-

026
-

.--------+------+----~----~----+_--4_--_+----~----~--+_--.--~--+--.~

w w

G G

8-2

8-3

::: r#]

8-4

[@]

8-5

8-6

8-7

) [e]

* A blank column appears as code 00 and a O-zone punch (alone) appears as 20. To transform this
to IBM compatible tape BCD, a programmed reversal of these two codes must take place.
+ Non-printing character.

A2-5

TYPE CR02B CARD READER CODE (HOLLERITH) IN OCTAL FORM

Cha racter

A
B
C
D

E
F
G
H
I
J

K
L

Octal
Code

61
62
63
64
65
66
67
70
71
41
42
43

Character

N
0
P
Q
R
S
T
U
V
W

Octal
Code

Character

44
45
46
47
50
51
22
23
24
25
26
27

0
1
2
3
4
5
6
7
8
9

A2-6

Octal
Code

30
31
12
01
02
03
04
05
06
07
10
11

Character

Octal
Code

)

60
40
21
13
33
53
73
14
34
54
74

blank

-I-

/
--

,
$
I

(

TYPE CR02B CARD READER CODE (HOLLERITH) IN BINARY FORM

Hi gh order bits
01

Low order
bits

+ [&]

0000

blank

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

=[#]

1100

[@]

$
([%J

A2-7

[ oJ

HOLLERITH CARD CODE - TYPE 26 PUNCH
Zone

digit

no zone

.blank

+ [&]

1
2
3
4
5
6
7
8

A
B

8-3
8-4

= [ #]

no punch

C
0
E
F
G
H
I

[@]

) [C]

A2-8

K
L
M
N

5
T
V

( [ 96 ]

HOLLERITH CARD CODE - TYPE 29 PUNCH
Zone

digit
no zone

no punch

0
0

blank

1
2

S
T
U

C
D
E
F
G
H
I

L
M
N
0
P
Q
R

1
2
3
4
5
6
7
8

3
4
5
6
7
8

8-2
8-3
8-4
8-5
8-6
8-7

#
@

V
W

X
Y
Z

0/0

(

A2-9

APPENDIX 3

SCALES OF NOTATION
X

2 IN DECIMAL
X

0.001
0.002
0.003
0.004
0.005
0.006
0.007
0.008
0.009

1.00069 33874 62581
1.00138 72557 11335
1.00208 16050 79633
1.00277 64359 01078
1.00347 17485 09503
1.00416 75432 38973
1.00486 33204 23785
1.00556 05803 98468
1.00625 78234 97782

0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09

1.00695 55500 56719
1.01395 94797 90029
1.02101 21257 07193
1.02811 38266 56067
1.03526 49238 41377
1.04246 57608 41121
1.04971 66836 23067
1.05701 80405 61380
1.06437 01824 53360

0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9

1.07177 34625 36293
1.14869 83549 97035
1.23114 44133 44916
1.31950 79107 72894
1.41421 35623 73095
1.51571 65665 10398
1.62450 47927 12471
1.74110 11265 92248
1.86606 59830 73615

10±n IN OCTAL
n

10-"

1
12
144
1 750
23 420

0
1
2
3
4

1.000 000 000 000 000 000 00
0.063 146 314 631 463 146 31
0.005 075 341 217 270 243 66
0.000 406 111 564 570 651 77
0.000 032 155 613 530 704 15

112 402 762 000
1 351 035 564 000
16 432 451 210 000
221 411 634 520 000
2 657 142 036 440 000

10
11
12
13
14

0.000 000 000 006 676 337 66
0.000 000 000 000 537 657 77
0.000 000 000 000 043 136 32
0.000 000 000 000 003 411 35
0.000 000 000 000 000 264 11

303 240
3 641 100
46 113 200
~75 360 400
7 46 545 000

5
6
7
8
9

0.000 002 476 132 610 706 64
0.000 000 206 157 364 055 37
0.000 000 015 327 745 152 75
0.000 000 001 257 143 561 06
0.000 000 000 104 560 276 41

34 327 724 461 500 000
434 157 115 760 200 000
5 432 127 413 542 400 000
67 405 553 164 731 000 000

15
16
17
18

0.000 000 000 000 000 022 01
0.000 000 000 000 000 001 63
0.000 000 000 000 000 000 14
0.000 000 000 000 000 000 01

10"

n 10910 2, n log 2 10 IN DECIMAL
n

n IOS2 10
3.32192 80949
6.64385 61898
9.96578 42847
13.28771 23795
16.60964 04744

n IOSlo 2
0.30102 99957
0.60205 99913
0.90308 99870
1.20411 99827
1.50514 99783

1
2
3
4
5

n IOS2 10
19.93156 85693
23.25349 66642
26.57542 47591
29.89735 28540
33.21928 09489

n IUSlo 2
1.80617 99740
2.10720 99696
2.40823 99653
2.70926 99610
3.01029 99566

6
7
8
9
10

ADDITION AND MULTIPLICATION TABLES
Addition

Multiplication
Binary Scale

oxO=O
ox 1 = 1 x0 = 0
1 x 1 = 1

o to0=
= 0
1

0+1=1
1

1 = 10

Octal Scale
1

13.

MATHEMATICAL CONSTANTS IN OCTAL SCALE
71'= 3011037

552421.

e= 2.55760

521305.

,,=

0.44742 147707.

In" = -

0.43127 233602.

71'-1 =

0.24276

301556.

e·-I =

0.27426

530661.

VTi =

1.61337

611067,

Ve= 1.51411

230704,

log2"

= 0.33626 75425lt

V2=

In 71'

= 1.11206 404435.

loglo e

1.51544

163223.

1082e =

1.34252

166245.

In 2

V1O= 3.12305

407267.

108210 =

3.24464

741136.

In 10 =

108271' =

A3-1

= - .0.62573 030645,
1.32404

746320.

0.54271 ·027760.
2.23273

067355.

POWERS 0 F TWO
2

n
a

2
4
8

1
2
3

16
32
64
128
256
512
1 024
2 048
4 096
8 192
16 384
32 768
65 536
131 072
262 144
524 288
1 048 576
2 097 152
4 194 304
8 388 608
16 777 216
33 554 432
67 108 864
134 217 728
268 435 456
536 870 912
1 073 741 824
2 147 483 648
4 294 967 296
8 589 934 592
17 179 869 184
34 359 738 368
68 719 476 736
137 438 953 472
274 877 906 944
549 755 813 888
1 099 511 627 776
2 199 023 255 552
4 398 046 511 104
8 796 093 022 208
17 592 186 044 416
35 184 372 088 832
70 368 744 177 664
140 737 488 355 328
281 474 976 710 656
562 949 953 421 312
1 125 899 906 842 624
2 251 799 813 685 248
4 503 599 627 370 496
9 007 199 254 740 992
18 014 398 509 481 984
36 028 797 018 963 968
72 0~)7 594 037 927 936
144 115 188 075 855 872
288 230 376 151 711 744
576 460 752 303 423 488
1 152 921 504 606 846 976
2 305 843 009 213 693 952
4 611 686 018 427 387 904
9 223 372 036 854 775 808
18 446 744 073 709 551 616
36 893 488 147 419 103 232
73 786 976 294 838 206 464
147 573 952 589 676 412 928
295 147 905 179 352 825 856
590 295 810 358 705 651 712
1 180 591 620 717 411 303 424
2 361 183 241 434 822 606 848
4 722 366 482 869 645 213 696

4
5

6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72

-n

1.0
0.5
0.25
0.125
0.062 5
0.031 25
0.015 625
0.007 812 5
0.003 906 25
0.001 953 125
0.000 976 562 5
0.000 488 281 25
0.000 244 140 625
0.000 122 070 312 5
0.000 061 035 156 25
0.000 030 517 578 125
0.000 015 258 789 062 5
0.000 007 629 394 531 25
0.000 003 814 697 265 625
0.000 001 907 348 632 812 5
0.000 000 953 674 316 406 25
0.000 000 476 837 158 203 125
0.000 000 238 418 579 101 562 5
0.000 000 119 209 289 550 781 25
0.000 000 059 604 644 775 390 625
0.000 000 029 802 322 387 695 312 5
0.000 000 014 901 161 193 847 656 25
0.000 000 007 450 580 596 923 828 125
0.000 000 003 725 290 298 461 914 062 5
0.000 000 001 862 645 149 230 957 031 25
0.000 000 000 931 322 574 615 478 515 625
0.000 000 000 465 661 287 307 739 257 812 5
0.000 000 000 232 830 643 653 869 628 906 25
0.000 000 000 116 415 .321 826 934 814 453 125
0.000 000 000 058 207 660 913 467 407 226 562 5
0.000 000 000 029 103 830 456 733 703 613 281 25
0.000 000 000 014 551 915 228 366 851 806 640 625
0.000 000 000 007 275 957 614 183 425 903 320 312 5
0.000 000 000 003 637 978 807 091 712 951 660 156 25
0.000 000 000 001 818 989 403 545 856 475 830 078 125
0.000 000 000 000 909 494 701 772 928 237 915 039 062 5
0.000 000 000 000 454 747 350 886 464 118 957 519 531 25
0.000 000 000 000 227 373 675 443 232 059 478 759 765 625
0.000 000 000 000 113 686 837 721 616 029 739 379 882 812 5
0.000 000 000 000 056 843 418 860 808 014 869 689 941 406 25
0.000 000 000 000 028 421 709 430 404 007 434 844 970 703 125
0.000 000 000 000 014 210 854 715 202 003 717 422 485 351 562 5
0.000 000 000 000 007 105 427 357 601 001 858 711 242 675 781 25
0.000 000 000 000 003 552 713 678 800 500 929 355 621 337 890 625
0.000 000 000 000 001 776 356 839 400 250 464 677 810 668 945 312 5
0.000 000 000 000 000 888 178 419 700 125 232 338 905 334 472 656 25
0.000 000 000 000 000 444 089 209 850 062 616 169 452 667 236 328 125
0.000 000 000 000 000 222 044 604 925 031 308 084 726 333 618 164 062 5
0.000 000 000 000 000 111 022 302 462 515 654 042 363 166 809 082 031 25
0.000 000 000 000 000 055 511 151 231 257 827 021 181 583 404 541 015 625
0.000 000 000 000 000 027 755 575 615 628 913 510 590 791 702 270 5u7 812 5
0.000 000 000 000 000 013 877 787 807 814 456 755 295 395 851 135 253 906 25
0.000 000 000 000 000 006 938 893 903 907 228 377 647 697 925 567 626 953 125
0.000 000 000 000 000 003 469 446 951 953 614 188 823 848 962 783 813 476 562 5
0.000 000 000 000 000 001 734 723 475 976 807 094 411 924 481 391 906 738 281 25
0.000 000 000 000 000 000 867 361 737 988 403 547 205 962 240 695 953 369 140 625
0.000 000 000 000 000 000 433 680 868 994 201 773 602 981 120 347 976 684 570 312 5
0.000 000 000 000 000 000 216 840 434 497 100 886 801 490 560 173 988 342 285 156 25
0.000 000 000 000 000 000 108 420 217 248 550 443 400 745 280 086 994 171 142 578 125
0.000 000 000 000 000 000 054 210 108 624 275 221 700 372 640 043 497 085 571 289 062 5 .
0.000 000 000 000 000 000 027 105 054 312 137 610 850 186 320 021 748 542 785 644 531 25
0000 000 000 000 000 000 013 552 527 156 068 805 425 093 160 010 874 271 392 822 265 625
0.000 000 000 000 000 000 006 776 263 578 034 402 712 546 580 005 437 135 696 411 132 812 5
0.000 000 000 000 000 000 003 388 131 789 017 201 356 273 290 002 718 567 848 205 566 406 25
0.000 000 000 000 000 000 001 694 065 894 508 600 678 136 645 001 .359 283 924 102 783 203 125
0.000 000 000 000 000 000 000 847 032 947 254 300 339 068 322 500 679 641 962 051 391 601 562 5
0.000 000 000 000 000 000 000 423 516 473 627 150 169 534 161 250 .339 820 981 025 695 800 781 25
0.000 000 000 000 000 000 000 211 758 236 813 575 084 767 080 625 169 910 490 512 847 900 390 625

A3-2

OCTAL-DECIMAL INTEGER CONVERSION TABLE
0
0000

0000

tJ777

0.511

IOetol)

(Oecima/)

Octal

Decimal

10000· .4096
20000· 8192
30000 - 12288
.40000 - 1638.4
50000 - 20"SO
60000·2"516
70000 . 28672

0.512
to

1023

(Octal)

IOecimol)

0002 000,1 0004 0005 0006 0007
0010 0011 0012 0013 0014 0015
0018 0019 0020 0021 0022 0023
0026 0027 0028 0029 0030 0031
0034 0035 0036 0037 0038 0039
0042 0043 0044 0045 0046 0047
0050 0051 0052 0053 0054 0055
0058 0059 0060 0061 0062 0063

0400 0256 0257 0258 0259
0410 0264 0265 0266 0267
0420 0272 0273 0274 0275
0430 0280 0281 0282 0283
0440 0288 0289 0290 0291
0450 0296 0297 0298 0299
0460 0304 0305 0306 0307
0470 0312 0313 0314 0315

0260 0261
0268 0269
0276 0277
0284 0285
0292 0293
0300 0301
0308 0309
0316 0317

0262 OlfS3
0270 0271
0278 0279
0286 0287
0294 0295
0302 0303
0310 0311
0318 0319

0100 0064 0065
0110 0072 0073
0120 0080 0081
0130 0088 0089
0140 0096 0097
0150 0104 0105
0160 0112 0113
0170 0120 0121

0066 0067
0074 0075
0082 0083
0090 0091
0098 0099
0106 0107
0114 0115
0122 0123

0068 0069 0070 0071
0076 0077 0078 0079
0084 0085 0086 0087
0092 00Sj3 0094 0095
0100 0101 0102 0103
0108 0109 0110 0111
0116 0117 0118 0119
0124 0125 0126 0127

0500 0320
0510 0328
05:t0 0336
0530 0344
0540 0352
0550 0360
0560 0368
0570 0376

0321
0329
0337
0345
0353
0361
0369
0377

0322
0330
0338
0346
0354
0362
0370
0378

0323
0331
0339
0347
0355
0363
0371
0379

0324 0325
0332 0333
0340 0341
0348 0349
0356 0357
0364 0365
0372 0373
0380 0381

0326 0327
0334 0335
0342 0343
0350 0351
0358 0359
0366 0367
0374 0375
0382 0383

0200 0128
0210 0136
0220 0144
0230 0152
0240 0160
0250 0168
0260 0176
0270 0184

0130
0138
0146
0154
0162
0170
0178
0186

0131
0139
0147
0155
0163
0171
0179
0187

0132
0140
0148
0156
0164
0172
0180
0188

0133
0141
0149
0157
0165
0173
0181
0189

0134
0142
0150
0158
0166
0174
0182
0190

0167
0175
0183
0191

0600 0384 0385
0610 0392 0393
0620 0400 0401
0630 0408 0409
0640 0416 0417
0650 0424 0425
0660 0432 0433
0670 0440 0441

0386
0394
0402
0410
0418
0426
0434
0442

0387
0395
0403
0411
0419
0427
0435
0443

0388 0389
0396 0397
0404 0405
0412 0413
0420 0421
0428 0429
0436 0437
0444 0445

0390
0398
0406
0414
0422
0430
0438
0446

0192 0193 0194 0195
0200 0201 0202 0203
0208 0209 0210 0211
0216 0217 0218 0219
0224 0225 0226 0227
0232 0233 0234 0235
0240 0241 0242 0243
0248 0249, 0250 0251

0196
0204
0212
0220
0228
0236
0244
0252

01~7

0205
0213
0221
0229
0237
0245
0253

0198
0206
0214
0222
0230
0238
0246
0254

0199
0207
0215
0223
0231
0239
0247
0255

0700
0710
0720
0730
0740
0750
0760
0770

0450 0451
0458 0459
0466 0467
0474 0475
0482 0483
0490 0491
0498 0499
0506 0507

0
1000

0000 0000 0001
0010 0008 0009
0020 0016 0017
0030 0024 0025
0040 0032 0033
0050 0040 0041
0060 0048 0049
0070 0056 0057

0300
0310
0320
0330
0340
0350
0360
0370

1777

0129
0137
0145
0153
0161
0169
0177
0185

0135
0143
0151
01~9

0448
0456
0464
0472
0480
0488
0496
0504

0449
0457
0465
0473
0481
0489
0497
0505

0391
0399
0407
0415
0423
0431
0439
0447

0452 0453 0454 0455
0460 0461 0462 0463
0468 0469 0470 0471
0476 0477 0478 0479
0484 0485 0486 0487
0492 0493 0494 0495
0500 0501 0502 0503
0508 0509
0510 0511
----,

1000 0512 0513
1010 0520 0521
1020 0528 0529
1030 0536 0537
1040 0544 0545
1050 0552 0553
1060 0560 U561
1070 0568 0569

0514 0515 0516 0517 0518 0519
0522 0523 0524 0525 0526 0527
0530 0531 0532 0533 0534 0535
0538 0539 0540 0541 (l542 0543
0546 0547 0548 0549 0550 0551
0554 0555 0556 0557 0558 0559
0562 0563 0564 0565 0566 0567
0570 0571 0572 0573 0574 0575

1400 0768
1410 0776
1420 0784
1430 0792
144D 08DO
1450 0808
1460 0816
1470 0824

1100 0576 0577
1110 0584 0585
1120 0592 0593
1130 0600 0601
1140 0608 0609
1150 0616 0617
1160 0624 0625
1170 0632 0633

0578
0586
0594
0602
0610
0618
0626
0634

0579
0587
0595
0603
0611
0619
0627
0635

0580
0588
0596
0604
0612
0620
0628
0636

0581
0&89
0597
0605
0613
0621
0629
0637

0582
0590
0598
0606
0614
0622
0630
0638

0583
0591
0599
0607
0615
0623
0631
0639

1500 0832 0833
1510 0840 0841
1520 0848 0849
1530 0856 0857
1540 0864 0865
1550 0872 0873
156() 0880 0881
1570 0888 0889

1200 0640
1210 0648
1220 0656
1230 0664
1240 0672
1250 0680
1260 0688
1270 0696

0642
0650
0658
0666
0674
0682
0690
0698

0643
0651
0659
0667
0675
0683
0691
0699

0644
0652
0660
0668
0676
0684
0692
0700

0645
0653
0661
0669
0677
0685
0693
0701

0646
0654
0662
0670
0678
0686
0694
0702

0647
0655
0663
0671
0679
0687
0695
0703

1600 0896 0897 0898 0899 0900 0901 0902 0903
1610 0904 0905 0906 0907 0908 0909 0910 0911
1620 0912 0913 0914 0915 0916 0917 0918 0919
1630 0920 0921 0922 0923 0924 0925 0926 0927
1640 0928 0929 0930 0931 0932 0933 0934 0935
1650 0936 0937 0938 0939 0940 0941 0942 0943
1660 0944 0945 0946 0947 0948 0949 0950 0951
1670 0952 0953 0954 0955 0956 0957 0958 0959

0641
0649
0657
0665
0673
0681
0689
0697

1300 0704 0705 0706 0707
1310 0712 0713 0714 0715
1320 0720 0721 0722 0723
1330 0728 0729 0730 0731
1340 0736 0737 0738 0739
1350 0744 0745 0746 0747
1360 0752 0753 0754 0755
1370 0760 0761 0762 0763

0708 0709 0710 0711
0716 0717 0718 0719
0724 0725 0726 0727
0732 0733 0734 0735
0740 0741 0742 0743
0748 0749 0750 0751
0756 0757 0758 0759
0764 0765 0766 0767

A3-3

0769
0777
0785
0793
0801

077Q
0778
0786
0794
0802
080~ 0810
0817 0818
0825 0826

0771 0772 0773
0779 0780 0781
0787 0788 0789
0795 0796 0797
0803 0804 0805
0811 0812 0813
0819 0820 0821
0827 0828 0829

0834 0835
0842 0843
0850 0851
0858 0859
0866 0867
0874 0875
0882 0883
0890 0891

0774 0775
0782 0783
0790 0791
0798 0799
080e 0807
0814 0815
0822 0823
0830 0831

0836 0837 0838
0844 0845 0846
0852 0853 0854
0860 0861 0862
0868 0869 0870
0876 0877 0878
0884 0885 0886
0892 0893 089"

1700 0960 0961 0962 0963 0964 0965
1710 0968 0969 0970 0971 0972 0973
1720 0976 0977 0978 0979 0980 0981
1730 0984 0985 0986 0987 0988 0989
1740 0992 0993 0994 0995 0996 0997
1750 1000 1001 1002 1003 1004 1005
1760 1008 1009 1010 1011 1012 1013
1770 1016 1017 1018 1019 1020 1021

0839
0847
0855
0863
0871
0878
0887
0885

0966 0967
0974 0975
0982 0983
0990 0991
~98 0999
1006 1007
1014 1015
1022 1023

OCTAL-DECIMAL INTEGER CONVERSION TABLE (continued)
--------0

2400
2410
2420
2430
2440
2450
2460
2470

1280
1288
1296
1304
1312
1320
1328
1336

1281
1289
1297
1305
1313
1321
1329
1337

1282
1290
1298
1306
1314
1322
1330
1338

1283
1291
1299
1307
1315
1323
1331
1339

1284
1292
1300
1308
1316
1324
1332
1340

1285
1293
1301
1309
1317
1325
1333
1341

1286
1294
1302
1310
1318
1326
1334
1342

1287
1295
1303
1311
1319
1327
1335
1343

1095
1103
1111
1119
1127
1135
1143
U51

2500
2510
2520
2530
2540
2550
2560
2570

1344 1345
1352 1353
1360 1361
1368 1369
1376 1377
1384 1385
1392 1393
1400 1401

1346
1354
1362
1370
1378
1386
1394
1402

1347
1355
1363
1371
1379
1387
1395
1403

1348
1356
1364
1372
1380
1388
1396
1404

1349
1357
1365
1373
1381
1389
1397
1405

1350
1358
1366
1374
1382
1390
1398
1406

1351
1359
1367
1375
1383
1391
1399
1407

1158
1166
1174
1182
1190
1198
1206
1214

1159
1167
1175
1183
1191
1199
1207
1215

2600
2610
2620
2630
2640
2650
2660
2670

1408
1416
1424
1432
1440
1448
1456
1464

1409
1417
1425
1433
1441
1449
1457
1465

1410
1418
1426
1434
1442
1450
1458
1466

1411
1419
1427
1435
1443
1451
1459
1467

1412
1420
1428
1436
1444
1452
1460
1468

1413
1421
1429
1437
1445
1453
1461
1469

1414
1422
1430
1438
1446
1454
1462
1470

1415
1423
1431
1439
1447
1455
1463
1471

1221
1229
1237
1245
1253
1261
1269
1277
..-.-------.-------.---

1222
1230
1238
1246
1254
1262
1270
1278

1223
1231
1239
1247
1255
1263
1271
1279

2700
2710
2720
2730
2740
2750
2760
2770

1472
1480
1488
1496
1504
1512
1520
1528

1473
1481
1489
1497
1505
1513
1521
1529

1474
1482
1490
1498
1506
1514
1522
1530

1475
1483
1491
1499
1507
1515
1523
1531

1476
1484
1492
1500
1508
1516
1524
1532

1477
1485
1493
1501
1509
1517
1525
1533

1478
1486
1494
1502
1510
1518
1526
1534

1479
1487
1495
1503
1511
1519
1527
1535

1799
1807
1815
1823
1831
1839
1847
1855

2000
2010
2020
2030
2040
2050
2060
2070

1024 1025
1032 1033
1040 1041
1048 1049
1056 1057
1064 1065
1072 1073
1080 1081

1026
1034
1042
1050
1058
1066
1074
1082

1027
1035
1043
1051
1059
1067
1075
1083

1028
1036
1044
1052
1060
1068
1076
1084

1029
1037
1045
1053
1061
1069
1077
1085

1030
1038
1046
1054
1062
1070
1078
1086

1031
1039
1047
1055
1063
1071
1079
1087

2100
2110
2120
2130
2140
2150
2160
2170

1088
1096
1104
1112
1120
1128
1136
1144

1089
1097
1105
1113
1121
1129
1137
1145

1090
1098
1106
1114
1122
1130
1138
1146

1091
1099
1107
1115
1123
1131
1139
1147

1092
1100
1108
1116
1124
1132
1140
1148

1093
1101
1109
1117
1125
1133
1141
1149

1094
1102
1110
1118
1126
1134
1142
1150

2200 1152
2210 1160
22201"68
2231) 1176
2240 1184
2250 11192
226011200
2270 1.208

1153
1161
1169
1177
1185
1193
1201
1209

1154
1162
1170
1178
1186
1194
1202
1210

1155
1163
1171
1179
1187
1195
1203
1211

1156
1164
1172
1180
1188
1196
1204
1212

1157
1165
1173
1181
1189
1197
1205
1213

2300 1216
2310 1224
2320 1232
2330 1240
2340. 1248
235011256
2360 i 1264
2370 1272

1217
1225
1233
1241
1249
1257
1265
1273

1218
1226
1234
1242
1250
1258
1266
1274

1219
1227
1235
1243
1251
1259
1267
1275

1220
1228
1236
1244
1252
1260
1268
1276

~-----

I-

3000
3010
3020
3030
3040
3050
3060
3070

1536
1544
1552
1560
1568
1576
1584
1592

--------

1538
1546
1554
1562
1570
1578
1586
1594

1539 1540
1~47 1548
1555 1556
1563 1564
1571 1572
1579 1580
1587 1588
1595 1596

1541
1549
1557
1565
157.3
1581
1589
1597

1542
1550
1558
1566
1574
1582
1590
1598

1543
1551
1559
1567
1575
1583
1591
1599

3400 1792 1793 1794 1795
3410 1800 1801 1802 1803
3420 1808 1809 1810 1811
3430 1816 1817 1818 1819
3440 1824 1825 1826 1827
3450 1832 1833 1834 1835
3460 1840 1841 1842 1843
3470 1848 1849 1850 1851

1796
1804
1812
1820
1828
1836
1844
1852

1797
1805
1813
1821
J829
1837
1845
1853

1798
1806
1814
1822
1830
1838
1846
1854

3100 1600 1601
3110 1608 1609
3120 1616 1617
3J 30 1624 1625
3140 1632 1633
3150 1640 1641
3160 1648 '1649
3170 1656 1657

1602
1610
1618
1626
1634
1642
1650
1658

1603
1611
1619
1627
1635
1643
1651
1659

1604
1612
1620
1628
1636
1644
1652
1660

1605
1613
1621
1629
1637
1645
1653
1661

1606
1614
1622
1630
1638
1646
16.>4
1662

1607
1615
1623
1631
1639
1647
1655
1663

3500 1856 1857
3510 1864 1865
3520 1872 1873
3530 1880 1881
3540 1888 1889
3550 1896 1897
3560 1904 1905
3570 1912 1913

1858
1866
1874
1882
1890
1898
1906
1914

1859
1867
1875
1883
1891
1899
1907
1915

1860
1868
1876
1884
1892
1900
1908
1916

1861
1869
1877
1885
1893
1901
1909
1917

1862 18'83
1870 1871
1878 1879
1886 1887
1894 1895
1902 1903
1910 1911
1918 1919

3200 1664
3210 1672
3220 1680
3230 1688
3240 1696
3250 1704
326011712
3270 1720

1665
1673
1681
1689
1697
1705
1713
1721

1666
1674
1682
1690
1698
1706
1714
1722

1667
1675
1683
1691
1699
1707
1715
1723

1668
1676
1684
1692
1700
1708
1716
1724

1669
1677
1685
1693
1701
1709
1717
1725

1670
1678
1686
1694
1702
1710
1718
1726

1671
1679
1687
1695
1703
1711
1719
1727

3600 1920
3610 1928
3620 1936
3630 1944
3640 1952
3650 1960
3660 1968
3670 1976

1921
1929
1937
1945
1953
1961
1969
1977

1922
1930
1938
1946
1954
1962
1970
1978

1923
1931
1939
1947
19J5
1963
1971
1979

1924
1932
1940
1948
1956
1964
1972
1980

1925
1933
1941
1949
1957
1965
1973
1981

1926
1934
1942
1950
1958
1966
1974
1982

3300 1 1728
331011736
3320 1744
3330 1752
3340 1760
3350 1768
l3360 1776

1729
1737
1745
1753
1761
1769
1777

1730
1738
1746
1754
1762
1770
1778

1731
1739
1747
1755
1763
1771
1779

1732
1740
1748
1756
1764
1772
1780

1733
1741
1749
1757
1765
1773
1781

1734
1742
1750
1758
1766
1774
1782

1735
1743
1751
1759
1767
1775
1783
1791

3700 1984
3710 1992
3720 2000
3730 2008
3740 2016
3750 2024
3760 2032
~770 2040

1985 1986
1993 1994
2001 2002
2009 2010
2017 2018
2025 2026
2033 2034
2041 2042

A3-4

102.1
(Oecim'ol)

to
1.53~5

Octal DecimlClI
10000· 4096·
20000· 819::1'
30000 - 12288
40000 - 1638~

50000 • 204801
60000 - 24576
70000 • 28672

1537
1545
1553
1561
1569
1577
1585
1593

~]!Q...1784 _~~~~~_~~1789 12~0

2000
to
2777
(Octal)

1927
1935
1943
1951
1959
1967
1975
1983

1987 1988 1989 1990 1991
1995 1996 1997 1998 1999
2003 2004 2005 2006 2007
2011 2012 2013 2014 2015
2019 2020 2021 2022 2023
2027 2028 2029 2030 2031
2035 2036 2037 2038 2039
2043 2044 2045 2046 2047

3000

1.531~

to
3777
(Octal)

204:'

(Oeci"lol)

OCTAL-DECIMAL INTEGER CONVERSION TABLE (continued)
0
.. 000 I·
10

,048
10

.. 777
(Ocloll

2.5.59
IDf'cimoP

Octal

Decimal

10000 - 4096
20000 - 8192
30000 - 12288
40000 - 16384
50000 - 20480
60000 - 24576
70000 - 28672

4100 2112 2113
4110 2120 2121
4120 2128 2129
'4130 2136 2137
4140 2144 2145
4150 2152 2153
4160 2160 2161
4170 2168 2169

2114 2115
2122 2123
2130 2131
2138 2139
2146 2147
2154 2155
2162 2163
2170 2171

5777

3071

(Oclol)

(Decimol)

5000 2560
5010 2568
5020 2576
5030 2584
5040 2592
5050 2600
5060 2608
5070 2616
5100
5110
5120
5130
5140
5150
5160
5170

2117 2118
2125 2126
2133 2134
2141 2142
2149 2150
2157 2158
2165 2166
2173 2174

4
2561
2569
2577
2585
2593
2601
2609
2617

2562 2563 2564 2565
2570 2571 2572 2573
2578 '2579 2580 2581
2586 2587 2588 258!1
2594 2595 2596 2597
2602 2603 2504 2605
2610 2611 2612 2613
2618 2619 2620 2621

2624 2625 2626 2627
2632 2633 2634 2635
2640 2641 2642 2643
2648 2649 2650 2651
2656 2657 2658 2659
2664 2665 2666 2667
2672 2673 2674 2675
2680 2681 2682 2683

5200 2688 2689 2690 2691
5210 2696 2697 2698 2699
5220 2704 2705 2706 2707
5230 2712 2713 2714 2715
5240 2720 2721 2722 2723
5250 2728 2729 2730 2731
5260 2736 2737 2738 2739
5270 2744 2745 2746 2747

2631
2639
2647
2655
2663
2671
2679
2687

2692 2693 2694 2695
2700 2701 2702 2703
2708 2709 2710 2711
2716 2717 2718 2719
2724 2725 2726 2727
2732 2733 2734 2735
2140 2741 2742 2743
2748 2749 2750 2751

5300 2752 2753 2754 2755 2756 2757 2758 2759
5310 2760 2761 2762 2763 2764 2765 2766 2767
5320 2768 2769 2770 2771 2772 2773 2774 2775
5330 2776 2777 2778 2779 2780 2781 2782 2783
5340 2784 2785 2786 2787 2788 2789 2790 2791
5350 2792 2793 2794 2795 2796 2797 2798 2799
5360 2800 2801 2802 2803 2804 2805 2806 2807
5370 2808 2809 2810 2811 2812 2813 2814 2815

A3-5

2307 2308 2309 2310 2311
2315 2316 2317 2318 2319
2323 2324 2325 2326 2327
2331 2332 2333 2334 2335
2339 2340 2341 2342 2343
2347 2348 2349 2350 2351
2355 2356 2357 2358 2359
2363 2364 2365 2366 2367
2,372
2380
2388
2396
2404
2412
2420
2428

2373 2374 2375
2381 2382 2383
2389 2390 2391
2397 2398 2399
2405 '2406 2407
2413 2414 2415
2421 2422 2423
2429 2430 243.

2433 2434 2435 2436
2441 2442 2443 2444
2449 2450 2451 2452
2457 2458 2459 2460
2465 2466 2467 2468
2473 2474 2475 2476
2481 2482 2483 2184
2489 2490 2491 2492

2437 2438 2439
2445 2446 2447
2453 2454 2455
2461 2462 24~3
2469 2470 2471
2477 2478 2479
2485 2486 2487
2493 2494 2495

4700 2.496 2497 2498 2499
4710 2504 2505 2506 2507
4720 2512 2513 2514 2515
4730 2520 2521 2522 2523
474012528 2529 2530 2531
4750 2536 2537 2538 2539
4760,2544 2545 2546 2547
,477012152 2553 2554 2555

2500 2501 2502 2503
2508 2509 2510 2511
2516 2517 2518 2519
2524 2525 2526 2527
2532 2533 2534 2535
2540 2541 2542 2543
2548 2549 2550 2551
2556 2557 2558 2559

540012816
541°1282.
5420 2832
5430 2840
5440 2848
5450 2856
5460 2864
5470 2872

2817
2825
2833
2841
2849
2857
2865
2873

2818
2826
2834
2842
2850
2858
2866
2874

2819
2827
2835
2843
2851
2859
2867
2in5

2820
2828
2836
2844
2852
2860
2868
2876

287.1
2829
2837
2845
2853
2861
2869
2877

2822 2823
2830 2831
2838 2838
2846 :847
2854 2855
2862 2863
2870 2en
2878 287~

5500
5510
5520
5530
5540
5550
5560
5570

2881
2889
2897
2905
2913
2921
2929
2937

2882
2890
2898
2906
2914
2922
2930
2938

2883 2884
2891 2892
2899 2900
2907 2908
2915 2916
2923 2924
2931 2932
2939 2940

2885
2893
2901
2909
2917
2925
2933
2941

2886 2887
2894 2895
2902 2903
2910 2911
2918 2919
2926 2927
2934 2935
2942 2943

2566 2567
2574 2575
~5"82 2583
2590 2591
2598 2599
2606 2607 1
2614 2615
262~ 2623

2628 2629 2630
2636 2637 2638
2644 2645 2646
2652 2653 2654
2660 2661 2662
2668 2669 2670
2676 2677 2678
2684 2685 2686

4400 2304 2305 2306
4410 2312 2313 2314
4420 2320 2321 2322
4430 2328 2329 2330
4440 2336 2337 2338
445012344 2345 2346
4460 2352 2353 2354
4470 2360 2361 2362

4600 2432
4610 2440
4620 2448
'4630 2456
4640 12464
4650 2472
4660 2480
4670 2488

2247
2255
2263
2271
2279
2287
2295
2303j

4500 2368 2369 2370 2371
4510 2376 2377 2378 2379
4520 2384 2385 2386 2387
4~30 2392 2393 2394 2395
4540 2400 2401 2402 2403
4550 2408 2409 2410 2411
4560 2416 2417 2418 2419
4570 2424 2425 2426 2427

2119
2127
2135
2143
2151
2159
2167
2175

2182 2183
2190 2191
2198 2199
2206 2207
2214 2215
2222 2223
2230 2231
2238 2239

2243 2244 2245 2246
2251 2252 2253 2254
2259 2260 2261 2262
2267 2268 2269 2270
2275 2276 2277 2278
2283 2284 2285, 2286
2291 2292 2293 2294
2299 2300 2301 2302

1 2560
10

2116
2124
2132
2140
2148
2156
2164
2172

2177 2178 2179 2180 2181
2185 2186 2187 2188 2189
2193 2194 2195 2196 219':'
2201 2202 2203 2204 2205
2209 2210 2211 2212 2213
2217 2218 2219 2220 2221
2225 2226 2227 2228 2229
2233 2234 2235 2236 2237

4300 2240 2241 2242
4310 2248 2249 2250
4320 2256 2257 2258
4330 2264 2265 2266
4340 2272 2273 2274
4350 2280 2281 2282
4360 2288 2289 2290
4370 2296 2297 2298

·1000 2048 2049 2050 2051 2052 2053 2054 2055
4010 2056 2057 2058 2059 2060 2061 2062 2063
4020 2064 2065 2066 2067 2068 2069 2070 2071
4030 2072 2073 2074 2075 2076 2077 2078 2079
4040 2080 2081 2082 2083 2084 2085 2086 2087
4050 2088 2089 2090 2091 2092 2093 2094 2095
4060 2Q96 2097 2098 2099 2100 2101 2102 2103
4070 2104 2105 2106 2107 2108 2109 2110 2111

4200 2176
4210 2184
4220 2192
4230 2200
4240 2208
4250 2216
4260 2224
4270 2232

5000

2880
2888
2896
2904
2912
2920
2928
2936

5600 2944 2945
561012952 2953
562012960 2961
5630 2968 2969
5640j2976 2977
5650 2984 2985
5660 2992 2993
5670 3000 3001

2946 2947 2948 2949 2950 2951
2954 2955 2956 2957 2958 2959
2962 2963 2964 2965 2966 2967
2970 297: 2972 2973 2974 2975
2978 2979 2980 2981 2982 2983
2986 2987 2988 2989 2990 2991
2994 2995 2996 2997 2998 2999
3002 3003 3004 3005 3006 3007

3008 3009 3010 3011 3012 3013
5710 3016 3017 3018 3019 3020 3021
5720 3024 3025 3026 3027 3028 3029
5730 3032 3033 3034 3035 3036 3037
5740 3040 3041 3042 3043 3044 3045
5750 3048 3049 3050 3051 3052 3053
5760 3056 3057 3058 3059 3060 3061
5770 3064 3065 3066 3067 3068 3069

~700

3014 3015
3022 3023
3030 3031
3038 3039
3046 3047
3054 3055
3062 3063
3070 3071

OCTAL-DECIMAL INTEGER CONVERSION TABLE (continued)
'---'

3332
3340
3348
3356
3364
3372
3380
3388

3333
3341
3349
3357
3365
3373
3381
3389

3334 3335
3342 3343
3350 335J
3358. 3359
3366 3367
3374 3375
3382 3383
3390 339J

8000 3072 3073
8010 3080 3081
8020 3088 3089
8030 3096 3097
8040 3104 3105
8050 3112 3113
8080 3120 3121
6070 3128 3129

30 74
30 82
3090
3098
31 06
31 14
31 22
31 30

3075
3083
3091
3099
3107
3115
3123
3131

3076
3084
3092
3100
3108
3116
3124
3132

3077
3085
3093
3101
3109
3117
3125
3133

3078 3079
3086 3087
3094 3095
3102 3103
3110 3111
3118 3119
3126 3127
3134 3135

3137
3145
3153
3161
3169
3171
3185
3193

31 38
31 46
31 54
31 62
31 70
31 78
31 86
31 94

3139
3147
3155
3163
3171
3179
3187
3195

3140 3141 3142 ~143
3148 3149 3150 3151
3156 3157 3158 3159
3164 3165 3166 3167
3172 3173 3174 3175
3180 3181 3182 3183
3188 3189 3190 3191
3196 3197 3198 3199

6500 3392 3393
6510 3400 3401
&520 3408 3409
6530 3416 3417
6540 3424 3425
6550 3432 3433
6560 3440 3441
6570 3448 3449

3394
3402
3410
3418
3426
3434
3442
3450

3395
3403
3411
3419
3427
3435
3443
3451

3396 3397
3404 3405
3412 3413
3420 34·21
3428 3429
3436 3437
3444 3445
3452 3453

3398
3406
3414
3422
3430
3436
3446
3454

3204 3205
3212 3213
3220 3221
3228 3229
3236 3237
3244 3245
3252 3253
3260 3261

15600
6610
6620
6630
6640
6650
6660
6670

3456
34&4
3472
3480
3488
3496
3504
3512

3457
3465
3473
3481
3489
3497
3505
3513

3458
3466
3474
3482
3490
3498
3506
3514

3459
3467
3475
3483
3491
3499
3507
3515

3460 3461
3468 3469
3476 3477
3484 3485
3492 3493
3500 3501
3508 3509
3516 3517

3462 3463
3470 3471
3478 3479
3486 3487
3494 3495
3502 3503
3510 3511
3518 3519

6700 3520 3521
6710 3528 3529
6720 3526 3537
6730 3544 3545
6740 3552 3553
675'0 3560 3561
6760 3568 3569
6770 3576 3577

3522
3530
3538
3546
3554
3562
3570
3578

3523 3524 3525 3526 3521
3531 3532 3533 3534 3535
3539 3540 3541 3542 3543
3547 3548 3549 3550 3551
3555 3556 3557 3558 3559
3563 3564 3565 3566 35&7
3571 3572 3573 3574 3575
3579 3580 3581 3582 3583

8100
8110
6120
8130
8140
8150
6160
8170

3136
3144
3152
3160
3188
3176
3184
3192

8200 3200 3201
'1210 3208 3209
6220 3216 3117
6230 3224 3225
6240 3232 3233
6250 3240 3241
n80 3248 3249
6270 3256 3257

32 02 3203
32 10 3211
32 18 3219
32 26 3227
32 34 3235
32 42 3243
32 50 3251
32 58 3259

3206
3214
3222
3230
3238
3246
3254
3262

3207
3215
3223
3231
3239
3247
3255
3263

&300 3264 3265 32 66 3267 3268 3269 3270 3271
8310 3272 3273 32 74 3275 3276 3277 3278 3279
8320 3280 3281 32 82 3283 3284 3285 3286 3287
6330 3288 3289 32 90 3291 3292 3293 3294 3295
1340 3296 3297 32 98 3299 3300 3301 3302 3303
8350 3304 3305 33 06 3307 3308 3309 3310 3311
8360 3312 3313 331 4 3315 3316 3317 3318 3319
6370 3320 3321 33 22 3323 3324 3325 3326 3327

------0

&400
6410
&420
6430
&440
6450
6460
6470

3328 3329 3330 3331
3336 3337 3338 3339
3344 3345 3346 3347
3352 3353 3354 3355
3360 3361 3362 3363
3368 3369 3370 3371
3376 3377 3378 3379
3384 3385 3386 3387

L.~

3399
3407
3415
3423
3431
3439
3447
3455

7400 3840 3841 3842 3843 3844 3845 3846 3847
7410 3848 3,849 3850 3851 3852 3853 3854 3855
7420 3856 3857 3858 3859 3860 38&1 3862 3863
7430 3864 3865 3866 38&7 3868 3869 3870 3871
7440 3872 3873 3874 3875 3876 3877 3878 3879
7450 3880 3881 3882 3883 3884 3885 3886 3887
7460 3888 3889 3890 3891 3892 3893 3894 3895
7470 3896 3897 3898 3899 3900 3901 3902 3903

7100 3648 3649 3650 3651 3652 3653 3654 3655
7110 3656 3657 3658 3659 3660 3661 3662 3663
7120 3664 3665 3666 3667 3668 3669 3670 3671
7130 3872 3673 3674 3675 3676 3677 3678 3679
7140 3680 3681 3682 3683 3684 3685 3686 3687
7150 3688 3689 3690 3691 3692 3693 3694 3695
7160 3696 3697 3698 3699 3700 3701 3702 3703
7170 3704 3705 3706 3707 3708 3709 3710 3711

7500 3904 3905 3906 3907 3908 3909
7510 3912 3913 3914 3915 3916 3917
7520 3920 3921 3922 3923 3924 3925
7530 3928 3929 3930 3931 3932 3933
7540 3936 3937 3938 3939 3940 3941
7550 3944 3945 3946 3947 3948 3949
7560 3952 3953 3954 3955 3956 3957
7570 3960 3961 3962 3963 3964 3965

3910 3911
3918 3919
3926 3927
3934 3935
3942 3943
3950 395R
3958 3959
3966 3967

37 18 3719
3726 3727
3734 3735
3742 3743
3750 3751
3758 3759
3766 3767
3774 3775

7600
7610
7620
7630
7640
7650
7660
7670

3968 3969
3976 3977
3984 3985
3992 3993
4000 4001
4008 4009
4016 4017
4024 4025

3970 3971 3972 3973 3974 3975
3978 3979 3980 3981 3982 3983
3986 3987 3988 3989 3990 3991
3994 3995 3996 3997 3998 3999
4002 4003 4004 4005 4006 4007
4010 4011 4012 4013 4014 4015
4018 4019 4020 4021 '022 4023
4026 4027 4028 4029 4030 4031

7300 3776 3777 3778 3779 3780 3781 3782 3783
7310 3784 3785 3786 3787 3788 3789 3790 3791
7320 3792 3793 3794 37515 3796 3797 3798 3799
7330 ~8oo 3801 3802 3803 3804 3805 3806 3807
7340 3808 3809 3810 3811 3812 3813 3814 3815
7350 3818 3817 3818 3819 3820 3821 3822 3823
7380 3824 3825 3826 3827 3828 3829 3830 3831
7370 3832 3833 3834 3835 3836 3837 3838 3839

7700
7710
7720
7730
7740
7750
7760
7770

4032 4033
4040 4041
4048 4049
4056 4057
4064 4065
4072 4073
4080 4081
4088 4089

4034 4035
4042 4043
4050 4051
4058 4059
4066 4067
4074 4075
4082 4083
4090 4091

3713 3714 3715 3716 3717
3721 3722 3723 3724 3725
3'l29 3730 3731 3732 3733
3737 3738 3139 3740 3741
3745 3746 3747 3748 3149
3753 3754 3755 3758 3757
3761 3782 3763 3764 3765
3769 3770 3771 3772 3773

A3-6

3072

6777

3.513

(Octal)

(Oeci"Iol)

Octal

DecirWilal

10000·· 4094~
20000·· 819:Z
30000·· 122811
40000 .. 1638·.
50000 .. 20481)
60000 .. 24574~
70000 .. 2867:!

7000 3584 3585 3586 3587 3588 3589 3590 3591
7010 3592 3593 3594 3595 3596 3597 3598 3599
7020 3600 3601 3602 3603 3604 3605 3606 3607
7030 3608 3609 3810 3611 3612 3613 3614 3615
7040 3616 3617 3618 3619 3620 3621 3622 3623
7050 3624 3625 3626 3627 3628 3629 3630 3631
7060 3632 3633 3634 3635 3636 3637 3638 3639
7070 3640 3641 3642 3643 3644 3645 3646 3647

7200 3712
7210 3720
7220 3728
7230 3738
7240 3744
7250 3752
7280 n80
7270 3788

6000

4036 4037 4038 4039
4044 4045 4046 4047
4052 4053 4054 4055
4060 4061 4062 4063
4068 4069 4070 4071
4076 4077 4078 4079
4084 4085 4086 4087
4092 4093 4094 4~5

7000
to
7777
IOctol)

3.51:.
to

"ot'.5
(Decimal)

OCTAL-DECIMAL FRACTION CONVERSION TABLE
OCTAL

DEC.

OCTAL

DI::C •

OCTAL

DEC.

OCTAL

m:c.

.000
.001
.002
.003
.004
.005
.006
.007
.010
.011
.012
.013
.014
.015
.016
.017
.020
.021
.022
.023
.024
.025
.026
.027
.030
.031
.032
.033
,034
,035
.036
.037
.040
.041
.042
.043
.044
.045
.046
.047
.050
.051
.052
.053
.054
.055
.056
.057
.060
.061
.062
.063
.064
.065
.066
.067
.070
.071
.072
.073
.074
,075
.076
.077

.000000
.001953
· (f03906
.005859
.007812
.009765
.011718
.013671
.015625
.017578
.019531
.021484
.023437
.025390
.027343
.029296
.031250
.033203
.035156
.037109
.039062
.041015
.042968
.044921
.046875
.048828
.050781
.052734
.054687
.056640
.058593
.060546
.062500
.064453
.066406
.068359
.070312
.072265
.074218.076171
.078125
.080078
.082031
.083984
.085937
.087890
.089843
.091796
.093750
.095703
.097656
.099609
.101562
.103515
· 105468
.107421
.109375
.111328
.113281
.115234
• 117187
.119140
.121093
• 123046

.100
• 101
.102
.103
.104
.105
.106
.107
.110
.111
.112
.113
.114
.115
.116
.117
.120
• 121
.122
.123
.124
.125
.126
.127
.130
· 131
.132
.133
.134
.135
.136
.137
.140
· 141
.142
.143
.144
.145
· 146
.147 .

• 125000
· 126953
· 128906
.130859
· 132812
.134765
• 136718
.138671
.140625
• 142578
• 144531
.146484
.148437
• 150390
.152343
• 154296
.156250
.158203
.160156
.162109
.164062
.166015
• 167968
.169921

.200
.201
.202
.203
.204
.205
.206
.207
.210
.211
.212
.213
.214
.215
.216
.217
.220
.221
.222
.223
.224
.225
.226
.227
.230
.231
.232
.233
.234
.235
.236
.237
.240
.241
.242
.243
.244
.245
.246
.247
.250
.251
.252
.253
.254
.25.5
.256
.257
.260
.261
.262
.263
.264
.265
.266
.267
.270
.271
.272
.273
.274
.275
.276
.277

.250000
.251!l53
.253!l06
.255859
.25i812
.259765 .
.261718
.263671
.265625
.267578
.269531
.271484
.273437
.275390
.277343
.279296
.281250
.283203
.285156
.287109
.289062
.291015
.292968
.294921
.296875
.298828
.300781
.302734
.304687
.306640
.308593
.310546
.312500
.314453
.316406
.318359
.320312
.322265
.324218
.326171
.328125
.330078
.332031
.333984
.335937
.337890
.339843
.341796
.343750
.345703
.347656
.349609
.351562
.353515
.355468
.357421
.359375
.361328
.363281
.365234
.367187
.369140
.371093
.373046

.300
.301
.302
.303
.304
.305
.306
.307
.310
.311
.312
.313
.314
.315
.316
.317
.320
.321
.322
.323
.324
.325
.326
.327
.330
.331
.332
.333
.334
.335
.336
.337
.340
.341
.342
.343
.344
.345
.346
.347
.350
.351
.352
.353
.354
.355
.356
.357
.360
.361
.362
.363
.364
.365
.366
.367
.370
.371
.372
.373
.374
.375
.376
.377

.375000
.37G953

.150
.151
.152
.153
.154
.155
.156
.157
.160
.161
.162
.163
.164
.165
.166
.167
.170
• 171
.172
.173
.174
.175
.176
.177

· l71875
.173828
.175781
• 117734
.179687
.181640
.183593
· 185546
· 187500
· 189453
.191406
· 193359
.195312
.197265
.199218
.201171
.203125
.205078
.207031
.208984
.210937
.212890
.214843
.216796
.218750
.220703
.222656
.224609
.226562
.228515
.230468
.232421
.234375
.236328
· 238281
.240234
.242187
.244140
.246093
.248046

A3-7

• 37890r.

.380859
.382812
.384765
.386718
.388671
.390625
.392578
.394531
.396484
.398437
.400390
.402343
.404296
.406250
.408203
.410156
.412109
.414062
.416015
.417968
.419921
.421875
.423828
.426781
.427734
.429687
.431640
.433593
.435546
.437500
.439453
.441406
.443359
.445312
.447265
.449218
.451171
.453125
.455078
.457031
.458984
.460937
.462890
.464843
.466796
.468750
.470703
.472656
.474609
.416562
.478515
.460468
.482421
.484375
.486328
.4882~1

.490234
.492187
.494140
.496093
.498046

OCTAL-DECIMAL FRACTION CONVERSION TABLE (continued)
OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC.

.000000
.000001
.000002
.000003
.000004
.000005
.000006
.000007
,000010
,000011
,000012
,000013
.000014
,000015
.000016
,000011
,000020
.000021
.000022
.000023
,000024
.000025
.000026
,000021
.000030
.000031
.000032
.000033
,000034
.000035
.000036
.000031
.000040
.000041
.000042
,000043
.000044
.000045
.000046
• (\00047
.000050
.000051
.000052
.000053
.000054
.000055
,000056
,000057
.000060
.000061
.000062
,000063
,000064
.000065
.000066
.000061
.000070
.000,011
.000072
.000073
,000074
,000075
.000076
.000077

.000000
.000003
.000007
.000011
.000015
.000019
.000022
,000026
.000030
,000034
,000038
,000041
.000045
,000049
,000053
,000057
,000061
.000064
.000068
,000072
.000076
.000080
.000083
,000081
.000091
.000095
.000099
.000102
.000106
.000110
,000114
.000118
.000122
.000125
' ,000129
.000133
.000137
.000141
.000144
.000148
.000152
.000156
.000160
.000164
,000167
.000111
,000115
.000119
.000183
.000186
.000190
.000194
.000198
.000202
.000205
.000209
,000213
.000211
.000221
.000225
.000228
.000232
.000236
.000240

.000100
.000101
.000102
.000103
.000104
.000105
.000106
,000107
,000110
,000111
,000112
.000113
.000114
.000115
.000116
.000117
.000120
.000121
.000122
.000123
.000124
.000125
.000126
.000127
.000130
.000131
.000132
.000133
.000134
.000135
,000136
.000131
.000140
,000141
.000142
.000143
.000144
.000145
,000146
.000141
.000150
.000151
.000152
.000153
.000154
.000155
.000156
.• 000151
.000160
.000161
.000162
.000163
.000164
.000165
.000166
.000167
.000170
.000111
.000172
.000173
.00017"
.000175
.000176
.000177

.0002"
.000241
.000251
.000255
.000259
.000263
.000261
,000210
,000214
,000278
,000282
.000286
,000289
.000293
,0,00291
.000301
.000305
,000308
.000312
.000316
.000320
.000324
.000328
.000331
.000335
.000339
.000343
.000341
.000350
.000354
.000358
.000362
.000366
.000310
.000373
.00031T
,000381
.000385
,000389
,000392
.000396
.000400
.000404
.000408
.000411
.000415
.000419
.000423
.000427
.00M31
.000434
.000438
.000442
,000446
.000450
.000453
,000457
,000461
.000465
.000469
,OOM73
.000476
.000480
.000484

.000200
.000201
.000202
.000203
.000204
.000205
.000206
,000201
,000210
,000211
,000212
.000213
.000214
.000215
,000216
,000211
.000220
.000221
,000222
,000223
.000224
.000225
.000226
.000227
.000230
.000231
.000232
.000233
.000234
,000235
.000236
.000231
.000240
.000241
.000242
.000243
.000244
.000245
.000246
.000241
.000250
.000251
.000252
.000253
.000254
.000255
.000256
.000257
.000260
.000261
.000262
.000263
.000264
.000265
.000266
.000267
.000270
.000211
.000272
.000273
.000274
.000275
.000276
.000271

.000488
.000492
.000495
.000499
.000503
.000501
,000511
,000514
,000518
,000522
,000526
.000530
,000534
,000531
,000541
.000545
.000549
.000553
.000556
.000560
,000564
.000568
,000572
.000576
.000579
.000583
.000581
,000591
.000595
.000598
.000602
.000606
.000610
,000614
.000617
,000621
,000625
,000629
,000633
,000631
.000640
.000644
.000648
,000652
.000656
.000659
.000663
.000661
,000611
.000675
.000679
.000682
,000686
,000690
.000694
.000698
.000701
.000705
.000709
.000113
.000117
.000720
.000724
.000728

.000300
.000301
.000302
.000303
.000304
.000305
,000306
,000301
,000310
,000311
,000312
,000313
,000314
.000315
.000316
.000311
.000320
,000321
.000322
.000323
.000324
.000325
.000326
.000321
.000330
.000331
.000332
.000333
,0003.34
.000335
.000336
.000331
.000340
.000341
.000342
.000343
.000344
.000345
.000346
.000347
.000350
.000351
.000352
.000353
.000354
.000355
,000356
.0003S1
.000360
.000361
.000362
.000363
.000364
,000365
,000366
.000367
,000370
,000311
.000372
.000373
.000374
.000375
.000316
.000377

.000732
.000736
,000740
,000743
,000747
,000151
.000755
,000159
,000162
,000766
,000770
,000774
.000178
.000782
,000785
,000789
.000793
,000791
.000801
,000805
,000808
.000812
,000816
.000820
,000823
,000821
, 000831
,000835
.000839
.000843
,000846
.000850
,000854
,000858
,000862
.00,0865
.000869
,000873
,000877
,000881
,000885
.000888
.000892
.000896
,000900
.000904
,000907
.000911
.000915
,000919
.000923
.000926
.000930
.000934
,000938
.000942
,000946
,000949
.000953
,000957
.000961
.000965
.000968
.000972

A3-8

OCTAL-DECIMAL FRACTION CONVERSION TABLE (continued)
OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC •

.000 .. 00
.000401
.000402
.000403
.000404
.000405
.000406
.000407
.000410
.000411
.000412
.000413
.000414
.000415
.000416
.000 .. 17

• 000976
.000980
.000984
.000988
.000991
.000995
.000999
.001003
.001007
.001010
.001014
.001018
.001022
.001026
.001029
.001033

.000500
.000501
.000502
.000503
.000504
.000505
.000506
.000507
.000510
.000511
.000512
.000513
.000514
.000515
.000516
.000517

.001220
.001224
.001228
.001232
.001235
.001239
.001243
.001247
.001251
.001255
.001258
.001262
.001266
.001270
.001274
.001277

.000600
.000601
.00060'2
.000603
.000604
.000605
.000606
.000607
.000610
.000611
.000612
.000613
.000614
.000615
.000616
.000617

.001464
.001468
.001472
.001476
.001480
.001483
.001487
.001491
.001495
.001499
.001502
.001506
.001510
.001514
.001518
.001522

.000700
.000701
.000702
.000703
.000704
.000705
.000706
.000707
.000710
.000711
.000712
.000713
.000714
.000715
.000716
.000717

.001708
.001712
.001716
.001720
.001724
.001728
.001731
.001735
.001739
.001743
.001747
.001750
.001754
.001758
.001762
.001766

.000420
.000421
.000422
.000U3
.000424
.000425
.000426
.000427
.000430
.000431
.000.. 32
.000433
.000434
.000435
.000436
.000437

.001037
.001041
.001045
.001049
.001052
.001056
.001060
.001064
.001068
.001071
.001075
.001079
.001083
.001087
.001091
.001094

.000520
.000521
.000522
.000523
.000524
.000525
.000526
.000527
.000530
.000531
.000532
.000533
.000534
.000535
.000536
.000537

.001281
.001285
.001289
.001293
.001296
.001300
.001304
.001308
.001312
.001316
.001319
.001323
.001327
.001331
.001335
.001338

.000620
.000621
.000622
.000623
.000624
.000625
.000626
.000627
.000630
.000631
.000632
.000633
.000634
.000635
.000636
.000637

.001525
.001529
.001533
.001537
.001541
.001544
.001548
.001552
.001556
.001560
.001564
.001567
.001571
.001575
.001579
.001583

.000720
.000721
.000722
.000723
.000724
.000725
.000726
.000727
.000730
.000731
.000732
.00CJ733
.000734
.000735
.000736
.000737

.000«0
• 000441
• 000442
.000443
.000444
• 000446
• 000446
• 000447
.000450
.000451
.000452
• 000453
.000454
.000455
.000456
.000457
.000460
.000461
.000 .. 62
.000463
.000464
.000 .. 65
.000466
.000467
.000"70
.000471
.000472
.000473
.000474
.000475
.000476
.000477

• 001098
• 001102
• 001106
• 001110
.001113
• 001117
• 001121
• 001125
• 001129
• 001132
• 001136
• 001140
.001144
.001148
.001152
.001155
.001159
.001163
.001167
.001171
.001174
.001178
.001182
.001186

• 000540
• 000541
• 000542
.000543
.000544
• 000545
.000546
.000547

• 001342
.001346
• 001350
• 0'01354
.001358
• 001361
.001365
.001369

• 000550
.000551
.000552
.000553
.000554
.000555
.000556
.000557
.000560
.000561
.000562
.000563
.000564
.000565
.000566
.000567
.000570
.000571
.000572
.000573
.000574
.000575
.000576
.000577

• 001373
.001377
.001380
• 001384
.001388
.001392,
.001396
.001399
.001403
.001407
.001411
.001415
.001419
.001422
.001426
.001430
.001434
.001438
.001441
.001445
.001449
.001453
.001457
.001461

• 000640
• 000641
· 000642
• 000643
• 000644
.000645
• 000646
• 000647
· 000650
· 000651
• 000652
• Q00653
.000654
.000655
.000656
.000657
.000660
.000661
.000662
.000663
000664
.000665
,000666
000667
,:;Q0670
.000671
.000672
.000673
.000674
.000675
.000676
.000677

• 001586
.001590
.001594
.001598
.001602
.001605
.001609
.001613
.001617
• 001621
• 001625
.001628
.001632
.001636
.001640
.001644
.001647
.001651
.001655
.001659
.001663
.001667
.001670
.001674
.001678
.001682
.001686
.001689
.001693
.001697
.0017.Dl
.001705

• 000740
.000741
• 000742
• 000743
• 000744
.000745
• 000746
• 000747
• 000750
.000751
.000752
.000753
.000754
.000755
.000756
.000757
.000760
.000761
.000762
.000763
.000764
.000765
.000766
.000767
.000770
.000771
.000772
.000773
• 000774
.000775
.000776
.000777

.001770
.001773
.001777
.001781
.001785
.0017!l9
.001792
.001796
.001800
.001804
.001808
.001811
.001815
.001819
.001823
.001827
.001831
.001834
.001838
.001842
.001846
.001850
.001853
.001857
.001861
.001865
• 001869
.001873
.001876
.001880
.001884
.001888
.001892
.001895
.001899
.001903
.001907
.001911
.001914
.001918
.001922
.001926
.001930
.001934
.001937
.001941
.001945
.001949

• 001190
.001194
.001197
.001201
.00120~

.001209
.001213
.001216

A3-9