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Document:	Unibus Troubleshooting User's Manual
Order Number:	EK-FS002-OP
Revision:	001
Pages:	108
Original Filename:

OCR Text

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manual

Unibus

Troubleshooting
user’'s manual

EK-FS002-OP-001

COMPANY CONFIDENTIAL

digital equipment corporation - maynard, massachusetts

Ist Edition, February 1977

The material in this manual is for informational
purposes and is subject to change without notice.

This manual is intended for use by authorized

DIGITAL personnel only.

The information

contained in this manual is intended to be used
for analyzing product performance.
Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

DECtape

DECCOMM

DECUS

PDP
RSTS

DECsystem-10

DIGITAL

TYPESET-8

DECSYSTEM-20

MASSBUS -

TYPESET-11

UNIBUS

CONTENTS

Page

INTRODUCTION

1.1

SYSTEM OVERVIEW . . . . . . . . . . . it L.

UNIBUS TROUBLESHOOTING TECHNIQUES

1.
1.

whn W

CHAPTER 1

HI/LO TERMINATOR MARGIN CARDS

. . .. ... .. ... ...

1-2

. . . . ... ... .. ... ..

UNIBUS VOLTAGE MARGIN TESTER BOX

. . . ...
. ... R

SINGLE-ENDED MARGINING TECHNIQUE

. . ... .. ... .. .. ..

1-2

CHAPTER 2

UNIBUS CONFIGURATION

2.1

GENERAL

2.2

UNIBUS DEFINITIONS
. . . . . . . . . . ..
Bus Segment
. . . . . ... L

2.2.1

... ........ L ee - 2-1

. ..

... ... e

. ... .. SO
e
e e

e e e e e e e ee

e e e e e

2-1
2-1

2.2.2

Bus Cable

e e e e

2-2

2.2.3

224

Bus Element
. . . . ... ... ....... e e
Lumped Load
. .. ........... e
e e e e e e

2-2
2-2

2.2.5

Bus Jumper

2-2

2.2.6

Bus Terminator

2.2.7

Semi-Lumped Load

2.2.8

ACUnitLoad

. ... ... ... ... e

2.2.9

DCUnitLoad

. . . ... .. . . ...

. ... ... .. P e e e e e e e e e
. . . . . . . . . . . .

. ...

... ..e

12.2.10

Unibus Length and Loading

2.3

UNIBUS CONFIGURATION RULES

e e

e e e e e

e e

2-4

e e

2-4

2-5

. . . . . . . . . . .. ...
. . . . . . . . . .

2-6

... ...

2-6

. ...

2-7

2.3.1

Maximum Cable Length (Rule No. 1)

. . . .. .. ... .. ... ...

2-8

2.3.2

Maximum dc Loading (Rule No.2)

. . . . . . . . . . ... ... ...

2-8

- Maximum Lumped Loading (Rule No.3)
. . ... ... ... ... .. 28
Skewed Cable Lengths (Rule No.4)
. . .. . ...
.e
e
2-11
Skewed Cable Lengths, Supplement (Rule No.5)
. . .. ... ... .. 2-13

2.3.3
2.3.4

2.3.5
-

2.3.6

Rule Violations (Rule No. 6)

2.3.7

System Acceptance (Rule No.7)

2.3.8

Actual Bus Loading
UNIBUS LATENCY

2.4

2.4.1

. . . . . . . . ... e e 2-16
. . . . . . . . . . . . ... .. .. .. 2-16

. . . . . . . . . ... oL. 2-17

. . . . . .

Device Categories

e e e e e d e e e e e e e e 2-19

. . . . . . . . . . .. oL e

2.4.2

NPR Calculations for T1

. . . ...
. ... e

2.4.3

Latency Tolerance Calculations

2.4.4

BR Devices

2.4.5

Unibus Loading Rules

2.5

BUS BUSY TEST TECHNIQUES

2.5.1

2922

e e 2-22

. . . . . . . . . . . . ... .. .... 2-23

. . . .. ...
... e

e e e e e e e

. . . . . . . ... ... .... e

e e 2-23

e e e e e 2-23

. . . . . . . . . . ... .. . ... .... 2-24

Bus Busy and Latency Tolerance

. . . . . . ... .. ... e 2-24

2.5.2

Calculating Nominal Bus Busy Times

2.5.3

Measuring Bus Busy Times

2.5.4

Configuration Tables

. . . . . . . . . . ... .. ... 2-25

. . . . . . . . . . . . .. ..., 2-27

. . . . . .. .. ... .. e

e e e e e e e e e e - 2-30

CONTENTS (Cont)

Page

CHAPTER 3
3.1
3.2

TROUBLESHOOTING
- GENERAL

. . ... ... ....... e

TIMING CONSIDERATIONS
DATO-DATOB

e e e

3.2.2

DATI-DATIP

3.2.3

Interrupt Transactions

3.24

High-Frequency Cable Losses

3-1

e e

3-1

e e

3-5

. . . . . . . . ... .. ... .

3-5

. . . . ...
. e
. . .

3-1

e e e

... ... e

Peripheral Data Rate

e e

. . . . . . . .

3.2.1

3.2.5

. .

e e e e e e e e
e e e e e e

e e e e

e e e e e e e e e

. . . .. ee e e

e e

. . . . . . . . . . . . . . . .
. . . . .

3-6

e e e e d d e

PROPAGATION DELAY

3.3.1
3.4

Line Termination Technique . . . . . . . . . . . v v v v v i v
.. 3-11
CABLE AND CONTACT RESISTANCE LOSSES
. . . .. .. e 3-12

CHAPTER 4

BUS MARGINING

4.1

GENERAL

4.2

BUS QUIESCENT LEVELS

e e e

Multiple Bus System Considerations

e e e e e

. . . . . . . . . ..e

HI/LO TERMINATOR BUS MARGINING

4.4

UNIBUS VOLTAGE MARGIN TESTER BOX

4.4.2

4.5

4.5.1

e e e e e e e e

... ... .. e

e e e

. . . . . ... ... .. ...

UVM-TA Operation and Test Procedures

(\\

. . . . . . . . ... ... ..

SINGLE-ENDED MARGINING . . .. .. .. e
e e e e e e e
Setup and Operation (Using M9308 Single-Ended Margin Head) . . . . .

4.5.2

Single-Ended Circuit Consideration
SACK Timeout

4.6.1

. . . . . . . . .. J

4.5.3
4.6

. . . . . . . . . .. e ..

4.3

Functional Description

. . . . .

“Quiescent Conditions

4.4.1

e e[

4.2.2

Grant Line Termination

e e e e

. . . . .. ...
..e

4.2.1

4.2.3

e e e

3-6

3.3

. . . .

. . .

. . . . . . . . . . . . . . ... .. |

. . . . . .

e e e e e e e

MODIFYING M930 TERMINATOR CARD
Equipment Required

4.6.2

Modifyingthe M930

4.6.3

Procedure forUse

. . .

. .

e e e e

. . . . . . .. ... ... ...
.

.. ..

.. e

e e e e

. . . . . . . . .. ... ... .. e
e e e
.

. . .

. .. e e e e e e e

e e e e

CHAPTER 5

UVM-TA TESTER

5.1

UVM-TA OVERVIEW

5.2

TESTER KIT COMPONENTS

. . . . . . . . . .

5.3

TESTER SPECIFICATIONS

. . . .. e S
. . . . . . . . ..o

. . . .. e e e e e

5.4

UNPACKING PROCEDURE

5.5

ACCEPTANCE TEST

e e

. . . . . . . . . . o o

o
oo

..
oL

oo oo

5.6

CONTROLS AND INDICATORS

5.7

OPERATING PROCEDURE

5.8
5.9

MAINTENANCE PHILOSOPHY
PREVENTIVE MAINTENANCE

. ... .. ... ... ..e
. . . . . . .. ... .
... |

5.10

CORRECTIVE MAINTENANCE

. . . . .

5.11

DISASSEMBLY/ASSEMBLY

. . ...
. EPe
.

. . ..

.. ...

. . . .

. . . . . . . . o

..o

o oo

CONTENTS (Cont)

APPENDIX A

ECO HISTORY AND REWORK

APPENDIX B

M9202-2 UNIBUS JUMPER INSTALLATION

APPENDIX C

AC AND DC LOAD TABLE

APPENDIX D

BUS LOADS

- FIGURES

Title

Page

e e e e e

2-3

. . . . . T...

Figure No.

2-1

Lumped Loads (Example A)

2-2

Lumped Loads (Example B)

. . . . . . . .. ..

2-3

Semi-Lumped Loads (Example C)

2-4

Bus Load Example

. . . . .. .. e

Rule No. 3 Violation (Block Diagram)

2-6

‘Rule No. 3 Violation (Waveform Example)

2-7

Rule No. 3 Implementation (Block Diagram)

2-10
2-11
2-12

e e e e e e

e e

2-5

. . . . . . . ... - 2-7

2-5

2-8

... e

. . . . . . . . . . . ... ... ...

. . . . .. .. ... ... ....

. . . . . .
Rule No. 3 Implementation (Waveform Example) . . . .
Multiple Bus System Example . . . . . . . . . . . . ..
Rule No. 4 Violation (Block Diagram)
. . . . . . . . .
Rule No. 4 Implementation (Example A) Block Diagram
Rule No. 4 Implementation (Example B) Block Diagram

2-8

2-9

... ... ... .. - 29

. . .. .. ... ..
.00
. . .. ... ...
. . . . . . . .. ..
. . . . . ...
. ..

2-13

Rule No. 4 Violation (Waveform Example)

2-14

Rule No. 4 Implementation (Waveform Example) . . . .. .. .. ... ...
Skewed Cable Length Violation . . . . . . . . . . . ... ... ... .
Skewed Cable Length Violation (Waveform Example)
. . . .. . .. .. ..
Violation of Rule No. 5 (Waveform Example) . . . ... .. ... ... ...
Implementation of Rule No. 5 (Waveform Example)
. . . . . ... ... ..

2-10
2-10
2-11
2-11
2-12

. . . . . . . . . . . ... . ... 2-12

2-20

2-13
2-14
2-14
215
2-15
Actual Bus Loads Example
. . . . . . . . . . . . .
oL Lo 2-17
Algorithm to Determine NPR Sequence . . . . . . . . . .. ... ... ... 2-20

2-21

Unibus Length Between Device and Memory

1 2-22

Single-Cycle Transaction
. . . . . . .. .. e
e e e e e e e e e
e 2-29
Double-Cycle Transaction . . . . . . . . . . .. .. e
e e e e e e e e 2-30
DLT Configurations . . . . . . . . . . . ... .. ... e
e e e e e e e 2-31

2-15

2-16
2-17

2-18
2-19

2-23

2-24

. . . . . . . . . . . .. .. .. 2-28

3-3

Unibus Troubleshooting Flowchart
. . . . . . . . . . . .. ... ... ...
System Cabling Configuration Example . . . . . . . ... ... ... ....
Transmission Line Circuit Example
. . . . . . . .. . ... .. e
e e

3-2
35
3-7

3-1
3-2

3-4

BC11-A Unibus Cable Delay Example

3-5

BC11 Unibus Cable Impedance Example

. . . . . . . . . . o v oo v v v

3-7

. . . . . . ... .. e e

3-6

Impedance Mismatch Example

3-8

. . . . . . . . . . ..o
o L,

3-9

3-7

Impedance (Low Resistance) Mismatch Example

3-8

Mismatch Reflection Curve Example

. . . . . . .. . .. ...

. . . . . . . .. e

e e e e e e e 3-10

FIGURES (Cont)

Title

Figure No.
3-9

BCl1 Unibus Cable Mismatch (Waveform Example)

3-10

System Device Impedance Example

3-11

Line Termination Technique Example

3-12

Cable Resistance Problems Example

4-1

Unibus Slot Backplane Signals

4-2

Low True Unibus Line

4.3

Equivalent Unibus Line Circuit

4-4

Quiescent dc Level Example

4-5

Load Current Leakage Example

. .. ... ... ... L

. . . . . . . .

. .. ... .. . 0.,

. . . . . . .. ... ... .. ....
. . . . . . . . . .. ... ... .....

. . . . . . . . . . . . ... ... ... ...,

. . . .. . ... .. ...
.

. . . . . . . .

. . .

. . . . . . . . .

4-6

Quiescent Level vs. Bus Loading (Worst Case)

4-7

Margining Multiple Bus Systems

. .

. . . . . . .

4-8

Grant Line Bus Margining Technique

. . . . . .

4.9

Margining Cards

....e e L

... ..

. .
o v

...,

Lo 00
v v v v i

. . . . . . . . .. ... ....
. . ... ... ... e
.

. .

... ... ...

. . . . . . . . . .. .. T e

4-10

Hi/Lo Terminator Circuit Example

4-11

UVM-TA Circuit Representation

. . . . . . . . . .

4-12

Controls and Indicators

4-13

UVM-TA Block Diagram

4-14
4-15

Single-Ended Circuit Example . . . . . ... ... .. e
e e e
Quiescent Voltage vs UVM-TA Voltage
. . . . . . ... ... ... .....

4-16

M9308 Termination Circuit Example

4-17

M9308 SACK Turnaround Logic

4-18

M930 Modification Example

5-1

Unibus Voltage Margin Tester Box

5-2

Controls and Indicators (Indexed)

. . . . . . . . . .

5-3

UVM-TA Troubleshooting Flowchart

. . . . . . . .. e

. . . . . . . . . ..

. ... .. .....
e e e e e e e.

... oo, e

. . . . . . . . . . . .

. i i

e e e e

i i it i i

. . . . . . . e

e e

. . . . . . . . . . . . . ... ... ....

. . . . . . ... ...

... ... ... .. L

. . . . . . .. e

e e e e e e

. o v o v o v v

...

. . . . . . . . . . .. ... ... ...

TABLES

Table No.

2-1
- 2-2

Realistic Load Values

.............. I .

Maximum NPR Rates of the NPR Dewces w1th Varlable Speed

. . . ...
.

2-3

Device Delay (Ddv)

2-4

Memory Access Delay (Dma)

2-5

Transmitter/Receiver Delay (Dtr)

. . . . . .. B

4-1

Bus Quiescent Levels

. .

4-2

Terminator Application Data

. .

. . . . .

. .. . .. .. e

. .

e e

e I

. . . . . . . ...
.

..e

........... L

. e

. .

. . . . . . . e e e e

...

.. ... ..

5-1

Tester Kit Components

5-2

Controls and Indicators (Indexed)

. . . . . . . . . .

5-3

Preventive Maintenance Schedule

. . . . . . . . . . . . .. ...

e
. .

. . . .. ... ...

PREFACE

This user’s manual is a detailed troubleshooting and reference guide for isolating Unibus problems
related to (a) systems which are inoperative and (b) systems which are marginal.

Due to the complexities and terminology associated with the Unibus, this manual also contains

descriptions, definitions and reference material relative to the Unibus and associated hardware.
NOTE

This manual does not define the optimum system
configurations for throughput or latency tolerence
which may be dependent on customer usage and
applications environment.

This manual supersedes Unibus Margin Tester user’s guide, document number EK-FS002-OP-PRE.

NOTE

The M9308 Margin Heads are direct replacements
for the M9303 Margin Heads. However, the M9308

allows for greater margining voltage (2.93 to 7.85 V)

than the M9303 (4.2 to 7.0 V).

CHAPTER 1

INTRODUCTION

SYSTEM OVERVIEW

NOTE
This manual is intended for use by authorized DIGITAL EQUIPMENT CORPORATION personnel
only. Information contained in this manual is neither
intended to be a product specification nor to supersede or replace any other published information that
is available to customers or users of DIGITAL
products.

Some PDP-11 system configurations experience permanent and intermittent bus failures due to
improper signal termination and loading techniques. (These problems can exist even when the proper
guidelines and rules for system configurations are followed.) This manual will assist in the proper
procedures for isolating configuration and Unibus problems, and corrective action that can be implemented for better system operatlon
Due to complexity of system configuration and operation, all Unibus systems are subject to additional
electrical and mechanical factors which may become even more relevant when, and if, these factors
interact. If this interaction becomes large enough, it can cause false signal levels that can seriously
effect system operation. Some of the signal conditions that can occur because of these additional
electrical and mechanical factors follow.
ARGl
e

1.1

Most of the PDP-11’s internal electronic components and system periplierals are connected to and
communicate with each other through the Unibus. There are 56 lines on the bus that handle such
signals as address, data and control information. Each device, including memory locations and peripheral device registers, 1s assigned one address on the Unibus.
|

Signal caused by dc loading of receivers and drivers
Signal loss caused by nonzero resistance of BC11 jumper cable
Signal loss caused by connector contact resistance
Standing wave reflections from devices on the line
Increased propagation delay caused by devices on the line and hlgh frequency cable losses
Crosstalk on bus lines caused by the cable or by devices attached to the bus
Signal skew caused by multiple high-frequency loading on different lines by a device

1-1

1.2

UNIBUS TROUBLESHOOTING TECHNIQUES

Currently, there are three troubleshooting aids that can be used to troubleshoot and isolate Unibus
problems.

1.
2.
3.

Hi/Lo Terminator Margin Cards
Unibus Voltage Margin Tester Box
Single-Ended Margining Technique

A fourth troubleshooting aid is the flowchart (refer to Chapter 3) which is organized into a general
flow and reference diagram which points out partlcular sections that contain troubleshooting techniques and supportive information. The supportive information will aidin the understandlng of, and
provide background for, the use of the Unibus Troubleshooting techniques outlinedin Chapter 3 of
this manual.

1.3

HI/LO TERMINATOR MARGIN CARDS

The Hi/Lo Terminator Margin Cards are used to replace the M930 bus terminator in the PDP-11
system for margmmg purposes. The Hi/Lo Terminator Cards are used as a go/no go test and are not
to be installed in the system on a permanent basis. (Refer to Chapter 4 for additional operational
procedures and descriptions.)

1.4

UNIBUS VOLTAGE MARGIN TESTER BOX

The Unibus Voltage Margin Tester Box is des1gned to test Unibus driver and receiver termmatmg
networks for the PDP-11 system. The tester is connected to the Unibus through special terminator
cards called margining heads. When the tester is cabled to the Unibus, the operator can select which

signal(s) (single, groups, or all) is to be tested. (Refer to Chapter 4 for additional operational pro-

cedures and descriptions.)

1.5

SINGLE-ENDED MARGINING TECHNIQUE

For some PDP-11 processors (e.g., PDP-11/04 and PDP-11/34), it is not possible to use the M930
margining heads with the Unibus Voltage Margin Tester Box. Thisis due to additional hardware on
the terminator module (boot strap function, sack turnaround, etc.) which must be present in order for
the processor to operate normally. It is for these processors that the Unibus Tester Box single-ended
margining technique has been developed. However, this technique can be used with any Unibus processor. (Refer to Chapter 4 for additional operational procedures and techniques.)

CHAPTER 2

UNIBUS CONFIGURATION

2.1

GENERAL

After the Unibus option configuration (based on NPR latency, physwal location, etc.) is determined,
these options must be interconnected using the correct procedure and techniques.

The definitions, rules and guidelines outlined in this section are designed to aid you in configuring an
electrically reliable Unibus. These rules and guidelines are intended for new systems and are not to be
considered as a justification for any changes in existing systems, unless Unibus related problems are
encountered and cannot be resolved in any other way.

The configuration rules (Paragraph 2.3) ensure, with reasonable confidence, that Unibus segments will

be electrically reliable, i.e., resulting dc bus levels will guarantee an adequate noise margin, and reflections from lumped loads w111 not be excessive.

To configure a Unibus system, the required order of options on the Unibus, based on NPR latency,

physical location, etc., should first be determined. The rules will then determine the length the Unibus
cable interconnecting the options and the number and location of bus repeaters. If the number of bus
~ repeaters is excessive, total cable length can sometimes be reduced
by rearranging the order of options
on the bus (again, paying close attention to NPR latency, etc.). Then, after reapplying the rules in this
. guide, one or more bus repeaters may be eliminated or located further down the bus to optimize system
speed. For large systems, more than one pass of this procedure may be necessary to achieve satisfactory results

A reasonable effort should always be made to ensure total cable lengthis as short as poss1ble particularly if one or more bus repeaters can be eliminatedin the process. Bus repeaters are costly and slow
down the system. Before implementing configuration rules, the user should carefully read and understand the definitions that follow.
2.2

UNIBUS DEFINITIONS

Prior to configuring the Unibus, review the definitions outlinedin Paragraphs 2.2.1 through 2.2.10.
2.2.1

Bus Segment

The Bus Segmentis defined as that portion of a Unibus system between and including two terminators.
A bus segment consists of: a terminator, a 120 ohm transmission path (cable) with options contalnlng
~drivers and receivers attached to it, and another terminator in that order. A single bus system is one
which has one bus segment. A multiple bus system is one which has more than one bus segment,
usually separated by bus repeaters (DB11s) or bus switches (DT03s - which contain bus repeaters).

2-1

2.2.2

Bus Cable

A Bus Cable is defined as cable connecting two backplanes which acts as a 120 ohm transmission line
with a length of two feet or more. A BC11A cable is defined to be both a cable and a bus element. For
our purposes, the cable is a subset of the bus element and should be treated as such. The following bus
|

elements are Unibus cables:

2-foot Unibus cable (60.96 cm)
BC11A-2
3-foot Unibus cable (91.44 cm)
BC11A-3
5-foot Unibus cable (1.52 m)
BC11A-5
BC11A-6
6-foot Unibus cable (1.82 m)
BC11A-8F 8.5-foot Unibus cable (2.59 m)
BC11A-10 10-foot Unibus cable (3.04 m)
BC11A-15 15-foot Unibus cable (4.57 m)
BC11A-20 20-foot Unibus cable (6.07 m)
BC11A-25 25-foot Unibus cable (8.60 m)
BC11A-30 30-foot Unibus cable (9.14 m)
24-inch folded Unibus cable (60.96 m)
M9202

The M9202 is considered to be a cable (for the purposes of this manual) because it contains 2 feet of
2.2.3

120 ohm cable.

Bus Element

A Bus Element is defined as any module, backplane, cable or group of these items that has a common
designation which has a direct electrical connection to one or more Unibus signal lines (other than AC
LO L or DC LOL). For example, an M930 terminator, an M7821 module, a BB11 backplane, a BC11

~ cable, and an RK 11 controller are Unibus elements. An H720 power supply, an LA36 DECwriter and
~ a BA11 expander box are not Unibus elements.
2.2.4

Lumped Load

‘

A Lumped Load is defined as a group of Unibus elements, other than cables or jumpers, which are
interconnected via Unibus jumpers and direct wiring (backplane wire, PC etch) only. The group is not
a lumped load if it uses a Unibus cable to interconnect the Unibus elements or if the elements are
separated by a bus repeater. (Be certain the difference between “‘jumper’ and ‘““cable” is understood see Figures 2-1 and 2-2.)

2.2.5 Bus Jumper

A Bus Jumper is defined as a Unibus element connecting two backplanes which contains less than two
feet of cable. The following elements are Unibus jumpers:

M920
jumper
|
M9200
jumper with boards 1.27 cm (0.5 in) apart
|
- jumper/terminator
M981
6-inch cable (15.24 cm)
BC11A-0

The BC11A-0 is considered to be a jumper (for the purposes of this manual) because it contains less
than 60.96 cm (2 feet) of 120 ohm ‘cable.

CABLE

-——-——1

rk11-0 | mse20

mMmi1-L |—] BC11A-16

me3o | 170

——T

|4 bp11-8 |—{ M9301

JUMPER

DL11-A

LUMPED LOAD

—

LUMPED LOAD

)

CP-2615

Ve
(

In this system, there are two lumped loads:
1.
2.

M930, 11/05 CPU, and MMI11-L
RKI11-D, DDI11-B, DL11-A,and M9301

Suppose the M920 is replaced by an M9202:

(‘

mM930 | 1;;?]5 L1 Mm11-L

_CABLE _
CABLE
BC11A-16 r—- ak11.-0 | me202 | pp11-8 |—| ms301
1A

LUMPED LOAD

—

LUMPED LOAD
CP-2616

Now there are three lumped loads:

M930, 11/05 CPU, and MM11-D
RKII-D

DD11-B, DL11-A, and M9301

Figure 2-1 Lumped Loads (Example A)

2-3

———

JUMPER

M9301

mozo — 11/45 |4 me200 |—f maz20 [—- ‘DB11-A }-—{ mM920 }
|

DL11-A

LUMPED LOAD

DL11-A

LUMPED LOAD
@

E___._
[

UNIBUS

SEGMENT

b
|

UNIBUS
SEGMENT

D
-

CP-2617

This system has two Unibus segments separated by a bus repeater, so the system has two lumped loads:
1.
2.

TMM930, 11/45 CPU, DBII-A (left side)
|
DBI11-A (right side), DDll B, four DL11-As, M9301
NOTE
These examples are for illustrative purposes only and
do not represent practical configurations.

Figure 2-2

2.2.6

Lumpeld Loads (Example B)

Bus Terminator

A Bus Terminator is defined as a Unibus element or part of an element containing a resistive network
which connects to the end of a Unibus segment and matches the 120 ohm characteristic impedance of
the Unibus transmission path. The M930 and M9306 are Unibus terminators if they connect to the
Unibus. The following bus elements contain Umbus terminators:
M981
M9300
M9301

jumper/ terminator
Unibus B terminator (M930 + NPR logic)
bootstrap/terminator

DTO03

bus switch

DB11-A

bus repeater

M9302

M930 with SACK return

PDP-11/04 CPU (NOTE other CPUs also contain termmators)

A Unibus segment must always have a Unibus terminator at each end of its 120 ohm transmlssmn
path.

2.2.7

Semi-Lumped Load

A semi-lumped loadis defined as a group of lumped loads interconnected by 91.44 cm (3 ft) or less of
cable (M9202, BC11-2 or BC11-3) and not separated by a bus repeater. Refer to Figure 2-3.

C
2-4

‘(I:‘L/L(j)5

BC11A-10

DD11-B |— M9301|
|

LUMPED | LUMP;D

LUMPED LOAD

— |

)

—~—

———

DL11-A

SL11A

LOA

LOAD

DL11-A

:
I
S

DL11-A

ISEM|-LUMPED

SEMI-LUMPED LOAD

LOAD

‘

LUMPED LOAD

|
|

‘

UNIBUS

SEGMENT

)

.
v

SEMI-LUMPED LOAD

UNIBUS

SEGMENT

R
Cp-2618

This system has two Unibus segments, with a total of four lumped loads and three semi-lumped loads.
Lumped loads:

1.
2.
3.
4.

M930, 11/45 CPU
DBI11-A (left side)
DBI11-A (right side)
DDI11-B, four DL11s, M9301

Semi-lumped loads:
1.
2.
3.

M930, 11/45 CPU, DBI11-A (left side)
DBI1-A (right side)
DDI11-B, four DL11s, M9301

Figure 2-3

Semi-Lumped Loads (Example C)

2.2.8

AC Unit Load
An ac unit load is defined as a number related to the impedance that a Unibus element presents to a
Unibus signal line (due to backplane wiring, PC etch runs, receiver input loading, and driver output
loading). This impedance load on a transmission line causes a “reflection” to occur when a step is sent
down the line. This reflection shows up on an oscilloscope as a spike occurring shortly after asserting
or unasserting edge. An ac unit load is nominally 9.35 pF of capacitance. Nine lumped ac loads reflect
20 percent and 20 lumped ac loads reflect 40 percent of a 25 ns risetime step. AC loads must be
distributed on the Unibus in the manner described by the rules in this manual in order to provide bus
operation with reflections guaranteed to be at or less than a tolerable level.

2-5

The ac unit load rating of Unibus elements is usually based on the greatest of the capacitances that the
element presents to the BBSY, SSYN, and MSYN Unibus signal lines. Appendix C contains the ac

loading specifications of the Unibus elements. If the element is customer-designed, its ac unit loading
must be determined from a reasonable estimate of the equivalent capacitance presented to the Unibus.

2.2.9

DC Unit Load

A dc unit load is defined as a number related to the amount of dc leakage current that a Unibus
element presents to a Unibus signal line which is high (undriven). A dc unit load is nominally 105 uA
(80 uA - receiver plus 25 uA - driver). However, the dc unit load rating of a bus element is not strictly
based on the element’s signal line that has the greatest leakage, (e.g., dc leakage is less important on D
lines than it is on SSYN). The dc unit loading of an element should always be obtained from the
specification for that element (see Appendix D). It should not be obtained from a calculation of the
receiver and driver leakage current, unless the element is custom-designed and is not listed in the
applicable documentation.
2.2.10

Unibus Length and Loading

The Unibus is a transmission line on which data transfers are asynchronous and interlocked. Significant electrical delay affecting system operation may, therefore, be imposed through unnecessarily long
Unibus cables.

‘

With ribbon cable the maximum length is 15.24 m (50 ft). For proper operation, the length of taps or
stubs must be minimized. The Unibus signals should have receivers and transmitters in one place (near
the Unibus cable) to act as a buffer between the Unibus and the signal lines carrying Unibus signals
within the equipment. The maximum length of ribbon cable is obtainable only if the individual tap
lengths are less than 5.08 cm (2 in), including printed circuit etches and if the loading is not more than
one standard bus load. One bus load is defined as one transmitter and one receiver (see Figure 2-4).

The Unibus is limited to a maximum of 20 bus loads. This limit is set to maintain a sufficient noise
margin. For more than 20 bus loads, a Unibus repeater option (DB11-A) is used.

2-6

TRANSMITTER

8881

/ Recelvsn

1 BUS LOAD =1 TRANSMITTER + 1 RECEIVER
CP-2564

Figure 2-4

Bus Load Example

2.3 UNIBUS CONFIGURATION RULES
|
The following rules and guidelines are intended to be used for new systems and/or existing systems

that experience Unibus problems. The seven rules are listed below for quick reference. A more detailed
description, comments, and suggestions are described in the following paragraphs.
Rule No. 1 (Maximum cable length)
- The total length of Unibus cablein a Unibus segment should
not exceed 15. 24 m (50 ft).
Rule No. 2 (Maximum dc loading) - The total number of dc unit loads on a Unibus signal line should
not exceed 20. (See Appendix D.)
Rule No. 3 (Maximum lumped loading)~ No lumped load on a Unibus segment should contain more
than 20 ac unit loads unless the entlre segment consists of one lumped load.

Rule No. 4 (Skewed cable lengths)- If (a) a lumped load (called the “affected lumped load”) has 2.59

m (8.5 ft) or longer cables connected to both busin and bus out and (b) the sum of the ac unit loadsin

the two lumped loads connected to the opposite ends of the cables exceeds 18, or (c) the sum of the ac
unit loads in the two semi-lumped loads connected to the opposite ends of the cables exceeds 36, then

the lengths of these cables should differ by 1.52 m (5 ft) or more with the longer cable being on the end
with the greatest number of ac unit loads (if there is a practical choice).

2-7

Rule No. 5 (Skewed cable lengths, supplement) — If the length of one of the cables connected to the
affected lumped load in Rule No. 4 must be increased because of that rule, then the longer cable should
have at its opposite end of the semi-lumped load with the greater number of ac unit loads. This rule
should be implemented only if it is practical to do so, i.e, in cases where its implementation will not
increase total cable length more than 1.52 m (5 ft).

Rule No. 6 (Violation of Rules No. 1 through No. 5) - Rules No. 1 through No. 5 should not be
grossly violated. If a bus segment violates a rule slightly, and for practical reasons reconfiguring is
undesirable, then the segment must pass voltage-margin tests (a) when the system is originally configured and (b) when any Unibus element is added, deleted, or swapped (including the swapping of a
defective module or backplane).

Rule No. 7 (SyStem 'acceptance) ~ Even if rules No. 1 through No. 5 are implemented, all Unibus

segments of a system should be voltage margined after the system is configured.
2.3.1

Maximum Cable Length (Rule No. 1)

If Rule No. 1 is violated, (a) the dc drop across the bus, when driven at one end and received at the
other, may be excessive, and (b) far-end crosstalk may be excessive. In calculating lengths, the M920
should be considered as zero feet, the M9202 as 60.96 cm (2 ft), and the BC11A-0 as 15.24 cm (6 in).

If the length of a ‘segr“nent: exc_éeds- 15.24 m (50 ft), reconfiguring (changing the order of bus elefnents)

may reduce the length. If that fails, a DB11-A busrepeater will be necessary.
2.3.2

Maximum dc Loading (Rule No. 2)

If too many dc loads are put on a Unibus segment, the quiescent undriven voltage may be lowered to a
level where bus receivers become susceptible to reflections from lumped loads and the overall noise
margin on the high end (bus undriven) may become too small. DB11 bus repeaters should be used (as
required) to implement this rule.

2.3.3. Maximum Lumped Loading (Rule No. 3)

If a lumped load is too large, it may generate a reflection on the Unibus large enough to create a false
logic signal and cause a failure (see Figures 2-5 and 2-6). M9202 folded cables (or BC11A-2s, if M9202
is unavailable) should be used
in place of M920s in order to separate large lumped loads. The effect of
the M9202 is to cause the peak reflections from the lumped loads it separates to occur at slightly
different times. The following examples (see Figures 2-7 and 2-8) illustrate implementation of Rule No.

I AFFECTED ELEMENT

178Q

BC11A-15

LUMPED LOAD

WITH 40 AC

UNIT LOADS

]

CP-2565

Figure 2-5

Rule No. 3 Violation (Block Diagram)

2-8

The system shown in Figure 2-5 violates Rule No. 3. When the driver in the affected bus element
unasserts the bus, the receiver in that element will see the following waveform:

8640
THRESHOLD

(DRIVER WAVEFORM)

(REFLECTION

(NET WAVEFORM

FROM LUMPED

AT RECEIVER)

LOAD)

CP-2566

Figure 2-6

Rule No. 3 Violation (Waveform Example)

The reflection may cause the threshold of the 8640 receiver to be crossed a second time, and a failure

may result. To implement Rule No. 3, the lumped load must be split into two equal loads by adding an
M9202 in place of an M920 (see Figure 2-7).
|

AFFECTED ELEMENT
+5V

178

LUMPED LOAD
BC11A-15

WITH 20 AC
UNIT LOADS

LUMPED LOAD

M9202
.

WITH 20 AC
UNIT LOADS

383 (!

@_‘—_O 8640
—Q

CP-2567

Figure 2-7

Rule No. 3 Implementation (Block Diagram)

The conditions to satisfy Rule No. 3 are now implemented. When the driver in the affected bus element

unasserts the bus, the receiver in that element will see the following waveform (Figure 2-8).

(

(NET WAVEFORM

(REFLECTION

(DRIVER WAVEFORM)

AT RECEIVER)

OF TWO LUMPED
LOADS)

CP-2568

(

' Figure 2-8 Rule No. 3 Implementation (Waveform Example)
Now the 8640 threshold is not crossed and the danger of a failure is reduced.

Rule No. 3 states that there is no limit to the number of ac unit loads on a Unibus segment (unless the

“entire segment consists of one lumped load). The reason for this statement is that there is no 120 ohm
cable in the segment on which reflections can travel. The following segment (Figure 2-9) is an example.

oB11-A

]I
|

M920

DD11-B

M920 -

DD11-B

DL11-A

M920

DL11-A

—
|
B

DD11-B

M920

DL11-A

DD11-B

DL11-A

M920

DD11-A

|
|

{

LUMPED LOAD

UNIBUS SEGMENT

='|

cm—

M920

CP-2569

Figure 2-9

Multiple Bus System Example

2-10

This segment obeys all configuration tules. It has zero (0) feet of cable, 20 dc unit loads, and an
irrelevant number of ac loads. In this configuration none of the M920s have to be replaced by M9202s.

2.3.4 Skewed Cable Lengths (Rule No. 4)

the following bus segment (Figure 2-10).
There may be several ways to implement Rule No. 4.Consider

LUMPED LOAD

WITH 18 AC

UNIT LOADS

—[

BC11A—-10 J-_——

AFFECTED

———-L BC11A-10

LUMPED
LOAD

LUMPED LOAD

l____ WITH 9 AC

UNIT LOADS
CP-2619

Figure 2-10

Rule No. 4 Violation (Block Diagram)

This segment violates Rule No. 4 because the sum of the lumped loads that are connected to the
opposite ends of the cables exceed 18 unit loads. AC unit loads equal 27 (18 + 9 = 27) lumped at the
ends of the BC11As of equal length. One way to implement Rule No. 4 is to increase the length of one
cable to 4.57 m (15 ft) (see Figure 2-11).

LUMPED LOAD

WITH 18 AC

‘1l UNIT LOADS

’

AFFECTED

——{ BC11A-15 1— LUMPED
LOAD

-——[ BC11A-10

LUMPED LOAD

9 AC
WITH

UNIT LOADS

CP-2570

Figure 2-11

Rule No. 4 Implementation (Example A) Block Diagram

2-11

Another way is to split the lumped load on the left into two lumped loads using an M9202 (see Figure
2-12).

LUMPED LOAD

WITH S8 AC

M9202

UNIT LOADS

LUMPED LOAD

AFFECTED

LUMPED LOAD

WITH 9 AC

LUMPED

BC11A-10

WITH9 AC
UNIT LOADS

LOAD

UNIT LOADS

——

—

SEMI-LUMPED LOAD WITH

SEMI-LUMPED

18 AC UNIT LOADS

LOAD WITH

9 AC UNIT
LOADS

CP-2572

Figure 2-12 Rule No. 4 Implementation (Example B) Block Diagram

When this rule is violated énd when a driver in the affected lumped load unasserts the bus, reflections

from the ends of its bus in and bus out cables will arrive at the affected lumped load simultaneously
and superimpose. The net reflection may cross the 8640 threshold and cause a failure (see Figure 2-13).

— — —

8640 THRESHOLD

v
|
|

—~

DRIVER

REFLECTION

WAVEFORM

FROM END

REFLECTION

NET WAVEFORM

FROMEND

AT AFFECTED

OF BUS IN

OF BUS OUT

LUMPED LOAD

CABLE

CABLE
CP-2571

Figure 2-13

Rule No. 4 Violation (Waveform Example)

2-12

When the rule is implemented by making the lengths of the bus in and bus out cables different, the
reflections will arrive at slightly different times (see Figure 2-14):

— — +—+ —

— 8640

THRESHOLD

b1
1)

112

~""

. :

REFLECTION
FROMEND

DRIVER
WAVEFORM

OF BUS OUT

OF BUSIN

NET WAVEFORM
AT AFFECTED

LUMPED LOAD

CABLE

CP-2573

Figure 2-14

Rule No. 4 Implementation (Waveform Example)

Now the reflection does not cross the 8640 threshold and the danger of a failure is reduced.
The configuration in Figure 2-12 does not violate Rule No. 4 because the sum of the ac unit loads
lumped at the ends of the BC11A-10 cables is 18 (9 + 9 = 18) and the sum of ac unit loads in the semilumped loads at the BC11A-10’s ends of the cables is 9 plus the lumped loads (18) for a total of 27 unit
loads (9 + 18 = 27).

Either of these methods could be used to implement Rule No. 4 but the second is more desirable in this
example because it minimizes the total cable length of the segment.
2.3.5

Skewed Cable Lengths, Supplement (Rule No. 5)

To understand why this rule is necessary, consider the following example (Figure 2-15).

2-13

LUMPED LOAD

WITH 20 AC

M9202

WITH 20 AC

M9202

UNIT LOADS

WITH 20 AC

UNIT LOADS

SEMI-LUMPED LOAD WITH 60

AC UNIT LOAD

CABLE #1

LUMPED

AFFECTED

LUMPED

CABLE #2

WITH 20

== 2.59 m (8.5 ft)

AC UNIT
LOADS

SEMI-LUMP

LOAD WITH
20 AC UNIT

CP-2574

LOADS

Figure 2-15 Skewed Cabl.e Length Violation

Suppose that the length of cable no. 1 equals the length of cable no. 2. This violates Rule No. 4. In this
case, the affected lumped load will see the following waveform (Figure 2-16) when its driver unasserts
the bus.

8140

—_—

~
DRIVER
WAVEFORM

~ THRESHOLD

NJ
'

N .

REFLECTION
FROM END OF

!
—_—

REFLECTION
FROM END OF

—~—_

NET WAVEFORM
AT AFFECTED
CP-2575

Figure 2-16 SK.éWed Cable Length Violation (Waveform Example)

2-14

Thereflection in this waveform crosses the 8640 threshold and may cause a failure. The best way to
implement Rule No. 4 in this example is to increase the length of either cable no. 1 or cable no. 2 by
1.52 m (5 ft). Suppose the length of cable no. 2 is increased by 1.52 m (5 ft). (This violates Rule No. 5
because this is the end with the smaller lumped load.) In this case, the affected lumped load will see the
following waveform (Figure 2-17) when its driver unasserts the bus.

8640

—_

|
|

—+

THRESHOLD-

t2
|

‘tz

2
,

NET WAVEFORM
AT AFFECTED

REFLECTION
FROMEND

REFLECTION
FROM END OF

DRIVER
WAVEFORM

LUMPED LOADS

OF CABLE #2

CABLE #1

CP-2576

Figure 2-17 Violation of Rule No. 5 (Waveform Example)

The reflection in this waveform also crosses the 8640 threshold and may cause a failure.

Now suppose the length of cable no. 1 is increased by 1.52 m (5 ft) instead of cable no. 2. This will
implement Rule No. 5 correctly. In this case, the affected lumped load will see the following waveform
(Figure 2-18) when its driver unasserts the bus.

8140

|
I

I
| t2

THRESHOLD

—

_|_

I
|

»
DRIVER
WAVEFORM

REFLECTION
FROM END OF

CABLE #1

REFLECTION
FROM END OF

CABLE #2

NET WAVEFORM
AT AFFECTED

LUMPED LOAD

CP-2577

Figure 2-18

Implementation of Rule No. 5 (Waveform Example)

2-15

The reflection from the ends of cables no. 1 and no. 2 do superimpose somewhat but not much. As a
result, the 8640 thresholdis not crossed.

2.3.6

Rule Violations (Rule No. 6)

Rules No. 1 through No. 5 should be implemented if possible. On rare occasions it may not be practical to do so. For example, the last bus segment on a system may exceed the 15.24 m (50 ft) maximum
length rule by 1.52 m (5 ft), and implementing Rule No. 1 may require another DB11-A repeater,
which may require another BA11-ES expander box, which may require another H960 cabinet. In this
case, it is acceptable to violate Rule No. 1, providing that the system is tagged so that Rule No. 6 is
always followed when the system undergoes change or corrective maintenance. Common sense has to
be exercised if any of Rules No. 1 through No. 5 is violated.

The voltage marg1n1ng procedure follows.

1.
2.

Replace the two terminators of the segment (M930, M9300, M9301, M9302, M981) with the

appropriate low-margin cards (M9304, M9305).

Run complete diagnostics and system exercisers.

Replace the two low-margin cards by the correspondlng high-margin cards (M9304-YA,
M9305-YA).

Run complete diagnostics and system exercisers.

Replace the two high-margin cards with the original terminators.

If any diagnostic or system exerciser fails during this procedure, the system has a problem. It may be
necessary to implement a rule violation in order to correct the problem. A Unibus voltage margining
tester box (Chapter 4) may be necessary to isolate the problem. To determine if there is a margin
problem, failures during margining must correspond w1th (or compared to) no failures when not
|
margining.
2.3.7

System Acceptance (Rule No 7 )

On rare occasions, Rules No. 1 through No. 5 may not be sufficient to ellmlnate all reflection problems. On these occasions, a Unibus voltage margin tester box (UVM-TA) should be used (along with
common sense) to isolate the problem and implement solutions. When an option fails (gives data
errors, hangs the bus, etc.) during a margining test, particularly the low-margining test, be suspicious
of reflections from surronding options after eliminating weak drivers, leaky receivers, etc. The solution
may be to replace an additional M920in those surrounding options w1th an M9202 (or even a BC11A3)in order to further spread out and reduce reflections. If Rules No. 1 through No. 5 do not eliminate
a reflection problem, please consult F.S.11 Product Support in Maynard.

2-16

2.3.8

(

Actual Bus Loading

PDP-11 systems are configured to have no more than twenty loads or 15.24 m (50 ft) of Unibus cable
on a given bus. Most devices are specifiedin terms of whole number loads butin fact thisis not always
the case. Table 2-1 lists realistic numbers for various options and using the system shown (Figure 2-19),
it is seen how loading may differ from that determined by conventional configuration guidelines.
NOTE
If quiescent voltages are correct, then dc loading
is
probably not a problem.

11/40
CPU

873

KW11P

DL11

MF11
(48K)

RK11

TM11

DH11
4

CR11

LP11

BUS LOADS

(

CONVENTIONAL

ACTUAL (380 RECEIVERS)

23.2

ACTUAL (8640 RECEIVERS)

18.7

CP-2578

Figure 2-19

Actual Bus Loads Example

Caution must be exercised in customer situations - the published loading specifications for each device
Lo

(as listedin Appendix D) must be usedin discussions with non-DEC personnel. Table 2-1 is included
only for your information. (Refer to Chapter 3, Paragraph 3. 3)

Realistic Load Values

Option
AAllA
AAl1l1B
AA11C
AA11D
AAI11E
ADO1
AFC11
BM792Y
BM873
- CBl11
CDl11
CM11
CR11
DAI11B
DAI11F
DBI11A
DCl11
DHI11
DJ11
DKI11
DLI11
DMI11BB
DNI11
DP11
DRI11A
DR11B
DR11C
DTO3F
DX11
GT40
KEl1A
KGl11
KWI11L
KWI11P
LCI11A
LP11
LPS11
LS11
LVl11
M792
MEI11
MF11
MMI11

No. of

Drivers

5
5
5
5
5
3
-2
1
0
2
3
4
4
2
2
1
3
1
2
2
4
2
2
3
4
2
4
2
2
3
1
2
1
3
4
2
2
2
2
1
1
1
1

Driver

Type

8881
8881
8881
8881
8881
8881
8881
8881
NONE
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
- 8881
8881
8881
8881
8881

8881
8881
8881
8881
8881
8881
74HO1-1
74HO1-1
74HO1-1

No. of

Rcvrs

2
2
2
2
2
1
1
1
2
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1

2-18

Max. No.
unit
loads if

Rcvrs

Reyvrs

are 380s

are 8640s

1.52
1.52
1.52
1.52
1.52
1.119
1
.8809
1.523
1
1.119
1.238
1.238
1
1
.8809
1.119
2.404
1
|
1.238
1
1
1.119
1.238
1
1.238
1
1
1.119
.8809
1
.8809
1.119
1.238
1

16
16
16
16
76
7380
6190
S
7619
6190
71380
8571
8571
6190
6190
S
7380
1.261
6190
6190
8571
6190
6190
7380
8571
6190
.8571
6190
.6190
7380
.5
6190
5
7380

1.52
1
1
.8809
1.952
1.952
1.952

8571
6190
16
6190
6190
S
1.571
1.571
1.571

Max. No.
unit
|
loads if

Table 2-1

Realistic Load Values (Cont)

Max. No.

Option

MRI11
MS11
PCl11
PR11
RCI11
RF11
RKI11C
RKIi11D
RP11
TA1l
TC11
- TMI11
UDCI11

No. of
Drivers
|
2
4
4
3
2
2
2
2
3
2
2

Driver
Type
8881
8881
8881
8881
8881
8881
8881
- 8881
8881
8881
8881
8881
8881

No. of
Rcevrs
1
|
1
1
1
1
1
1
1
1
1
1
2

Max. No.

unit

loads if
Revrs
are 380s

loads if
Rcvrs
are 8640s

.8809
1
1.238
-1.238
1.119
1
1
1
1
1.119
1
1
1.52

)
6190
8571
8571
.7380
6190
6190
6190
6190
7380
.6190
6190
16

2.4 UNIBUS LATENCY
This section is designed to familiarize the Field Service Engineer with the recommended NPR Device

Sequence on the Unibus and also provide the ability to determine and minimize possible ‘“Data Late”
errors.

The device sequences for a glven PDP-11 System (CPU, memories, and devwes) can be obtained by
applying the algorlthm given in Figure 2-20 and Table 2-2.
|

Tabie 2-2 Maximum NPR Rates of the N PR
‘Devices with Variable Speed
-

Device
CDI11-E
CDI11-A
DA11-B/DR11-B |
DHI11
DQI11-DA
DQ11-EA
|

GT40

Maximum Data
- Transfer Rate

Maximum
NPR Rate

1000 card /min
1200 card/min
500,000 word/s
16 X 9600 Baud
10,000 Baud
1 Megabaud

1.33kHz
1.6 kHz
500 kHz
154kHz
1kHz
100 kHz

20 us/point

- 2-19

50 kHz

NPR DEVICE SEQUENCE ON UNIBUS
CPU

— MEMORY

GIVEN:

CPU, MEMORIES,
AND DEVICES IN
PDP11 SYSTEM

> 90 KHz (NPR RATES) —

PLACE MEMORIES

— RK11/RKO05 (90 KHz)

CLOSEST TO CPU

—— TM11/TU10 (36 KHz2)

RATE OF DEVICE

< 90 KHz
> 36 KHz —
IS
DATA XFER

| FIXED?

< 36 KHz > b KHz

YES

~— TC11/TU56 (6 KHz)

IS
DATA XFER
RATE OF DEVICE
| KNOWN?

ASSUME
MAXIMUM
XFER RATE FROM

£ 5 KHz > 1.7

NPR SEQUENCE

KHz —p—

CHART

!
— RJSO4 (T1 = 87us)
DOES
DEVICE BELONG

| RJPO4 (T1 = 132us)

TO CATEGORY 2?

(SEE TEXT)
IS
DEVICE ON

__ RK611/RKO6 (T1 = 212 ps)

RATE OF

NPR CHART

DEVICE |

CALCULATE

COMPUTE NPR

DEVICE

L RJS03 (4us/wd)(T1 = 231us)

__ RP11C/RPO3 (T1 = 463us)

NPR CHART ?

(SEE TEXT)

YES

T1 (SEE TEXT)
% ]
LR

IS
NPR RATE

— RJSO03 (8us/wd) (T1 / 487us)

IN ORDER OF

PLACE DEVICE |

INCREASING T1

IN ORDER OF

VALUES (BEFORE

—— TJU45 (T1 = 900us)

DEVICES WHOSE

PLACE DEVICE IN
ORDER OF

17 KHe

DEVICES (SEE

ANY CATEGORY 1

NPR RATE IS
LESS THAN

—— TJU16 (T1 = 1801pus)

(SEE TEXT)

]

< 1.7 KHz?

PLACE DEVICE |

DECREASING NPR
RATES AFTER

TEXT)

DECREASING
NPR RATES
‘BEFORE

CATEGORY 2

DEVICES (SEE

TEXT) ***+

—— RF11/RS11 (T1 = 100 ms) y

< 1.7 KHz

I = 1+1

NO AES
{

= NUMBER OF
DEVICES

——DH11
DB 11-A

YES

DH11

Figure 2-20

Algorithm To Determine NPR Sequence (Sheet 1 of 2)

2-20

DOES THE

CONFIGURATION

VIOLATE UNIBUS
LOADING RULES?

(SEE SEC 2.3.5)

ADD A BUS
REPEATER AT
THE END IF NOT
ALREADY ADDED

ARE

THERE ANY

CATEGORY 1

YES

DEVICES

—

BETWEEN
THE LAST TWO

MOVE THE LAST

REPEATERS*

CATEGORY 1

DEVICE**
BEFORE THE

LAST BUS
REPEATER TO
IMMEDIATELY

ARE

AFTER IT.

THERE ANY

CORE MEMORIES

YES

BETWEEN THE

LAST TWO BUS
- REPEATERS*

MOVE THE
HIGHEST BANK

OF CORE
MEMORY
THIS IS AN

BEFORE THE LAST

ACCEPTABLE

REPEATER TO

SYSTEM

IMMEDIATELY
AFTER IT

bone

)

* If only one BUS REPEATER, this means between the CPU and the BUS REPEATER.
** Or the least frequently used category 1 device.

*** T1 = Maximum tolerance between bus cycles
****Except asyncheonous communication devices

(e. g., DH11) which have great latency tolerance
capacity.

DH11 can be placed in rear of all

other devices.

NOTES:
1.

Throughput is conditional and is well studied at the CPU. 1/0 bandwidth is more
difficult to determine but has been investigated by Engineering.

BR de\)ice can be put behind repeaters or behind NPR device. BR device should be
placed

front

of asynchronous

devices.

{i.e.

NPR11

DMC11,

DVM11

DC11)???

CP-2686

Figure 2-20

Algorithm To Determine NPR Sequence (Sheet 2 of 2)

2-21

Using the procedure outlined in Figure 2-20 and the maximum NPR rates specified in Table 2-2, the

following steps should be used to approach a DATA LATE problem.

Determine the correct sequence of devices on the Unibus. If the configuration is incorrect,
correct it.

2.
3.

Determine from the configuration tables whether or not the system is expected to experience
DLTs due to Unibus bandwidth (refer to Figure 2-24).

If the system is not expected to experience DLTs but nevertheless does, isolate the hardware

malfunction with the bus busy measurement technique.

In some cases, it may be useful to apply the Bus Busy' measurement technique to systems

which may experience Data Lates due to Unibus bandwidth. In such instances, the technique helps to demonstrate that the hardware is functioning correctly.
NOTE

For the purposes of this manual, bandwidth is defined
as the number of bus cycles that can be accommodated and still provide successful execution of the
application software.
2.4.1

Device Categories

All existing NPR devices that are connected to the Unibus are considered to be in one of the two
defined categories. Note the fact that all communication devices are considered to bein category 1
classification even though some devices have data buffers of more than six words (usually, these
devices multiplex more than one line).

Category 1 - Devices whose controllers have six or fewer words of data buffer (excluding
RF11/RS11 which, although it has only a one-word data buffer, falls more closely into
category 2 simply because it can wait for a maximum of three disk revolution time or 100 ms

without getting ““data late” errors). Other devicesin this category are: CD11, DA11, DHII,
DQI11, DR11, GT40, RK11/RKO0S5, TM11/TU10, and TC11/TUS56.

Category 2 - Devices whose controllers have more than six words of data buffer (including
RF11/RS11 as described under category 1). Devices included in this category are: RJS04,
RJP04, RK611/RK06, RJS03, RP11C/RPO03, TJU45, TJU16, and RF11/RS11.
2.4.2

NPR Calculations for T1

NPR rates of category 1 devices can be computedin one of the following ways.
NPR RATE = baud rate /10 (may be different for different devices), or
= word/s, or

= card/min X 1.33

Within Category 1, devices with higher NPR rates should be placed before devices with lower NPR
rates.

2-22

Latency Tolerance Calculations*

2.4.3

The processof determining category 2 device sequence can be simplified by comparing T1 (maximum
tolerance between bus cycles) of each device, which can be computed as follows:
"T1 = TDBS - TBBLUP X 2

where: TDBS

= Time to transfer DBS words to /from the device (in us)

= Data buffer size of the device controller (for RH11, DBS = 66)
DBS
TBBLUP = Typical data bubble up time of the device controller (for RH11, TBBLUP = 16
us)

Please note the following information carefully.

If the sector size of a device is larger than DBS, TDBS is s1mply the product of the
instantaneous data transfer rate of the device and the DBS of the device controller. For
example, the sector size of RP04is 256 words (DBS
= 66 words), and the 1nstantaneous data
transfer rate is 2.48 us/word, so TDBS = 2.48 X 66 = 164 us.

If the sector size of a deviceis smaller than DBS, the sector gap and interleaved sector and
gap (if any) must be accounted for to compute TDBS. The situation can be clarified better
with the examples that follow. RS03 has sectors of 64 words, sector gaps of 25.6 us and an
instantaneous data transfer rate of 3.6 us/word. Its DB (or silo) has two more words than a
sector; therefore, two words must be gotten to/from the next sector.

Sector-noninterleaved (4ls/wd): TDBS = 3.6 X 64 + 25.6 + 3. 6 X 2 =263 us

Sector-interleaved (8 us/wd) TDBS = (3.6 X 64 + 25. 6) X2+ 3.6X2=1519us
NOTE

Within category 2, devices with greater T1 should be
placed after devices with smaller T1. All category 2
devices should be placed before category 1 devices
with NPR rate less than 1.7 kHz, except for asynchronous communication devices (e.g., DH11) which
have great latency tolerance capacity. DH11 can be
placed
in rear of all other devices.
2.4.4

BR Devnces

2.4.5

Unibus Loading Rules

All the BR devices should be placed after NPR devices. However sometimes for convenience sake
some BR devices may be put before NPR devices (e.g., a DECwriter may be placed next to the CPU).

.
2.

Maximum loading before the first bus repeater is 19 dc bus loads; between two adjacent bus

repeaters is 18 dc bus loads.

Maximum Unibus cable length between the first bus repeater and the CPU or between the
adjacent bus repeaters is 15.24 m (50 ft). For example, configure a system with 11/45, 128K
of MF11-UP, DL11-A/LA30, KW11-L, RK11/RKO05, RJS04, RIP04, DH11, DQI1-EA (at
12.5K baud), RF11/RS11, TJU16, GT40, CD1I1-E.

*Latency tolerance capacities of devices in category 2 are defined and computed using ““Latency Tolerance

Capacities of NPR Controllers/Devices and Configuration Guidelines”. 4/23/75.

2-23

After going through Figure 2-20 and Table 2-2, the following sequence results.
Device

Unibus Loads

11/45
KWI11-L
DL11A/LA30
128K MF11-UP
RK11/RKO05 (90 kHz)
GT40 (50 kHz)
RJS04
RJPO4
TIJU16
RF11/RS11
DH11 (15.4 kHz)
CDI11-E (1.33kHz)
DQI11-EA (1.25 kHz)

TOTAL

2
1
1
8
|
1
|
1
1
1
2
1
1
22 UNIT LOADS

There are a total of 22 unit loads. Therefore, a DB11-A is added at the end and DH11, DQ11-EA and
|

CDI11-E are repositioned after DB11-A.

NOTE

The NPR device sequence algorithm does not take
into account the measures of the usage of the devices.
For example, suppose that in the system given above
GT40 is seldom used. GT40 may be placed behind
RF11/RS11 to improve system throughput.

2.5

BUS BUSY TEST TECHNIQUES

The following description is designed to aid in determining “‘nominal” device bus busy times for PDP-11
system configurations. It is intended for use in cases where a system under test is configured correctly,
but is still incurring Unibus “Data Late’ errors.

Almost every PDP-11 I/0 device, transferring data at the NPR level, has a period of time in which a
word or byte of data can remain in its data buffer before the next incoming word displaces it. This
period of time is known as a device’s latency. If, during this period of time, the device is unable to
- complete a Unibus transfer, the word in the data buffer will be displaced and lost. A data late error will
result and the transfer operation must be aborted and restarted. This is obviously an undesirable
condition.

Latency, or Data Late, errors may occur as a result of many factors, e.g., device and memory types,
Unibus configurations, software in use, and hardware malfunction. This document will address hard-

ware malfunctions.

2.5.1

Bus Busy and Latency Tolerance

In many instances stand-alone diagnostics and system exercisers will provide sufficient information to
allow the problem to be identified and isolated. This generally leads to a traditional troubleshooting

approach.

2-24

Sometimes, however, the malfunction will be more subtle, eluding even the most rigorous diagnostics.

In the past, large devices were slow (by today’s standards) and there was little concern about how long

a device took to complete a transaction on the Unibus. As systems have expanded in size and devices
have become faster and software more stringent in its I/O demands, the need for NPR devices to
complete their transactions and release the Unibus to another device as soon as possible has become
imperative.

If an NPR device holds BBSY asserted on the Unibus for an abnormally long period of time, that

device (in some configurations) could “crowd out” another NPR device competing for Unibus time
forcing an error condition to occur. It should be evident, then, that Data Lates being reported by one
~ device may be caused by another device on the system being a ‘“bus hog”.

The following paragraphs will show how to predict nominal BBSY time for a given configuration and
-

how to measure the actual BBSY times. Guidelines are included to help determine whether or not the
measured BBSY times fall within an acceptable range around the predicted value.
2.5.2

Calculating Nominal Bus Busy Times
NOTE
It doesn’t matter if the calculations necessary to pre-

dict a BBSY time are performed first or if the measurements are made first. In some cases however it is

necessary to determine if a device is conducting
“single cycle’ or “double cycle’’ transactions, as this
will affect the calculations that must be made. This
will be true of some Massbus devices (RH11). If in
doubt, proceed to Paragraph 2.4.3 and make this
determination.
This section deals with calculating or predicting a BBSY time for a device within a given configuration.

Component tolerances throughout the system make exact calculations impossible, but typically a
device should fall within a plus-or-minus 30 percent range of the predicted value. If, after measuring
the real BBSY time, it exceeds the predicted value by more than 30 percent, a potential problem area
has been found and steps should be taken to bring the offending device nearer to specification.
For the purposes of this manual, BBSY can be thought of as composing four separate components:
1.

Ddv

This is the internal timing delay of the device itself. The figure can be obtained from

Table 2-

Dma

This is memory access time or the time it takes memory to assert SSYN after it sees MSYN.
This figure can be obtained from Table 2-4.
Dtr

This is the delay associated with Unibus transmitters and receivers. This figure may be
obtained from Table 2-5.

This is the propagation delay of the Unibus itself, taking into account its length and loading
properties. This must be calculated from a formula.

2-25

Table 2-3

Device Delay (Ddv)
Ddyv (in nanoseconds)

Single
Cycle

Controller
Type

TC,TM, RP11-C, RK11-C, RF11 | 1100
|

DHI11
RK11-D

1350
935
1355

RH11 680

Double
~ Cycle

N/A

N/A
N/A

Table 2-4 Memory Access Delay (Dma)
Memory

Dma (in nanoseconds)
Single

Double

365

730

Cycle

Type

8K MF11-L

8K MF11-LP
16K MF11-U
16K MF11-UP
Other Core

Table 2-5

430
375
460
410

Cycle
860
740
920
820

Transmitter/Receiver Delay (Dtr)
Dtr (in nanoseconds)

Transmitter /Receiver
Type

Single
Cycle

Double
Cycle

Dt 8881
Dt 8838
Dt 380
Dt 8640

60
40
40
40

120
80
80
80

Single Cycle = Dp = (3.4 X UL) + (3.5 X dc unit loads)
Double Cycle = Dp = (6.8 X UL) + (7 X dc unit loads)

The summation of these four components yields a BBSY value unique to particular device and
configuration.

BBSY = Ddv + Dma + Dtr + Dp

The first three components of the formula (Ddv, Dma and Dtr) are easily obtained by referring to the
referenced tables. Locate in the table the appropriate device, memory'type or transmitter /receiver type
and extract the number from either the “single cycle” or ‘“double cycle column as it pertains to the device. Determining ‘“‘single cycle’ or ‘“double cycle” is explainedin Paragraph 2. 5 3.
:
The fourth component of the formula (Dp) may be derivedin the following manner.
|
Dp = (3.4 X Ul) + (3.5 X dc unit loads)
|

Single Cycle
or

Double Cycle

Dp = (6.8 X Ul) + (7 X dc unit loads)
where:

U1l
= Unibus lengthin meters (feet) between the device and memory
DC Unit Loads
= the number of DC Unit Loads between the devices and memory, mcludmg the dc
unit loads presented by memory itself.

To illustrate this, look at the sample configuration shown in Figure 2-21. If the device under test were
the RK11-D the value of U1l would be 60.96 cm (2 ft) and the dc unit loads would be 3 (1 dc unit load
for each 16K bank of memory). If the device under test were the TM 11, Ul would equal 2.13 m (7 ft)
and dc unit loads would equal 4.
NOTE
If the device under test is located behind one or more
DR11 bus repeaters add 375 ns (for devices doing
“single cycle” transfers) or 750 ns (for devices doing
“double cycle” transfers) to the caleulations for each
bus repeater between the device and memory.

2.5.3

Measuring Bus Busy Times

A dual-trace oscilloscope with three probes will be needed to conduct the following tests. The third
probe will be used to monitor MSYN in order to determine if some of the NPR devices (such as
RH11s) are doing *“‘double cycle” transactions. If it is certain that all the devices to be tested will be
conducting *‘single cycle” transfers only, the third probe may be eliminated and all calculations will be
made from figures extracted from the “single cycle” columns in Tables 2-3, 2-4, and 2-5.

2-27

60.96 cm (2 ft)

1.52 m (5 ft)

2.43 m (8 ft)

1.52 m (5 ft)

UNIBUS M /
———

MF11-U

0-16K
& PC11
SPC

KW11-L

FIS

MF11-U

32-48K

—

TM11

I [ UI

l
|[
____1

RP11-C

—

—
|

I I

RH11

RS04

l' 1
l

e
- =

=== .
!

KD11

16-32K

RK11-D

EIS
KT11

MF11-U

e —

CP-2683

Figure 221 - Unibus Length Between Device and Memory

Set up the oscilloscope as follows:
Coupling = dc
~
Trigger = External positive

Mode = Alternate
=~
Vols/Div = .1 (with X10 probes)

Time/Div = .5 microseconds.

Now locate a convenient access to the Unibus. The TCI 1 (DECtape) is a good access point if available,
otherwise any backplane with Unibus-in or Unibus-out will do.

Connect the probe corresponding to external trigger to SACK L at pin AR2.

Connect the probe' correSponding to channel 1 to BBSY L at pin AP2.
Connect the probe COrresponding to channel 2 to MSYN L at pin BV1.
The software to be run during these tests will be DEC/X11. Before proceeding, note that Table 2-4
(Dma) doesn’t include data on MOS or bi-polar memory systems. For this reason, ensure that
DEC/X11 doesn’t use MOS or bi-polar as write buffer space. If the system under test is an all core
system this will not be of any concern. If the system does include MOS or bi-polar it will be necessary
to lock the run-time exerciser in memory (via the RUNL command) so that the beginning of
DEC/X11s write buffer space (which coincides with the last address + 2 or the last module) is in core.
It is acceptable if the DEC/X11 code exercises from MOS or bi-polar as long as the write buffer space
is in core. Finally, inhibit write buffer rotation via the ROTOFF command.

2-28

Beforeissuing the RUNL command, DESelect all modules and SELect the module corresponding to
the first device to be tested.
NOTE
By testing only one device at a time and by trlggermg

the scope from SACK, it is ensured that the signals
seen will be those issued by the device under test.

Once DEC/X11 has been started and the scope trigger has been properly adjusted, the brace should
correspond to one of the two figures shown in Figures 2-22 and 2-23. Figure 2-22 shows a device doing
single-cycle transaction, and Figure 2-23 shows a device performing double cycle transactions.
The key here is the channel 2 trace displaying MSYN. If MSYN is seen being asserted once during the
BBSY time displayed on channel 1, the device is performing single-cycle transfers and the “single
cycle” column in Tables 2-3, 2-4 and 2-5 should be used. If MSYN is seen being asserted twice during
the BBSY time the deviceis performing double cycles and the “double cycle” column in the tables
should be used for the calculations on that device.
The BBSY time being displayed on channel 1 is the time to be ultimately concerned with. This is the
value that should coincide (plus-or-minus 30 percent) with the calculated value.

Once the measurements have been taken for a device, issue a control C from the keyboard to stop the
run-time exerciser. When DEC/X11 is ready to accept new commands DESelect the device just tested
and SELect the module corresponding to the next device to be tested and repeat these procedures until
all NPR devices on the system have been measured.

BBSY TIME

—

CHANNEL 1

CP-2684

MSYN

Figure 2-22 Single-CycIe Transaction

2-29

Ll
r

BBSY TIME

CHANNEL 1

CHANNEL 2

1st MSYN

Figure 2-23

2nd MSYN

CP-2685

Double-Cycle Transaction

2.5.4 Configuration Tables
The configuration table (Figure 2-24)is presented here to familiarize the user with Data Late (DLT)
occurrence possibilities of some common PDP-11 systems. No attempt is madein this manual to cover
all possible configurations because of the complexity of the problems that could be encountered.

In all configurations, the general rules are:
1.

If a configuration runs DLT-free, then a subset of the configuration should also run DLTfree.

If a configuration runs with DLT, adding more devices to the system should also give DLT.

2-30

(

. RK11D-TC11-RJS04-RP11C-TJU16-1~4DH11

2. RK11D-TC11-RJP04-RP11C-TJU16-1~4DH11

]

‘

]

|
|

4. RK11D-TM11-TC11-RJS03(4s)-RP11C-1~4DH11

6. RK11D-TM11-TC11-RP11C-RJS03(8/Ls)-1~4DH11

7. RK11D-TC11-RP11C-RJS03(8Us)-1~4DH11

5. RK11D-TC11-RJS03(4(1s)-RP11C-TJU16-1~4DH11

|
|

3. RK11D-TC11-RJP04-RJSO3(8s)-TJU16-1~4DH11

16Kp

S8Kp**

16Knp

8Knp*

RJS04-RJP04-RP11C \

RJPO4-RJSO3(4/is)-RP11C
DLT-Free region.

The configurations that

fall in this region should run without
DLT errors when all devices are

transferring data to/from the main memory

*8Knp = non-parity memory
*»*8Kp = parity memory

simultaneously.

DLT region. The configurations that fall

NN in this region will give us DLT errors

when all devices are transferring data to/
from the main memory simultaneously.
CP-2776

Figure 2-24

DLT Configurations

2-31

CHAPTER 3

TROUBLESHOOTING

3.1

GENERAL

This section is designed to aidin 1solat1ng and troubleshooting Unibus failures. The Unibus Trouble-

shooting Flowchart (Figure 3-1) is designed to provide a step-by-step procedure for checking and
correcting Unibus problems. The flowchart references chapters and paragraphs (which contain additional information and possible solutions to solve Unibus problems) are included for reference.
3.2

TIMING CONSIDERATIONS*

Some system failures such as address errors, missing data, illegal traps and system halts can occur
because of bus timing relationships.
3.2.1

DATO-DATOB

The Unibus specification states that MSYN must be asserted 150 ns (minimum) after the address,
control, and data (for DATO and DATOB transactions). This delay includes 75 ns to allow internal
logic in the slave device to decode the address. If MSYN is asserted before 150 ns, insufficient deskew
and signal decoding at the slave may result in errors. An 8881 driver and an 8640 receiver combination
can cause up to 60 ns of skew leaving as little as 15 ns as the allowable skew because of the Unibus
transmission media. The most timing-sensitive lines have been found to be BBSY, MSYN, SSYN and
INTR. Cable length and configuration can be a noticeable factor in these lines.
3.2.2

DATI- DATIP

For a DATI or DATIP operation, the slave puts requested data on the D lines and then asserts SSYN.
The slave should not assert SSYN at the driver input before the data and enable lines are valid at the
data driver inputs. The critical point seems to be around 35-40 ns skewin SSYN vs. DATA at which
point it is poss1ble for high-speed systems (such as the 11 /45 which allows only the 75 ns maximum
skew) to clockin erroneous data.

Some memories have a potential problem with this timing relationship in certain systems. When a
system is upgraded from an 11/05 or 11/20 to an 11/45 or when more of this memory is added in an
extended cabinet by a longer Unibus cable, the risk factor for problems becomes greater. If problems
are experienced with these memories (MM11-L, MM11-S, MM11-E, MM11-F)iin hlgh speed systems,
consult F.S. Product Support.

*Refer
to the 1975 Peripherals Handbook for Unibus timing information.

3-1

D)
CORRECT
TERMINATORS

BEING USED

INSTALL
YES

TERMINATORS

(SEE APPENDIX A)
ARE

UNIBUS

CABLES

FORMED

INSTALL FOAM
ON UNIBUS

YES

CABLES

(SEE APPENDIX A)

ARE

GRANT LINES

PROPERLY

ERMINATED,

TERMINATE

GRANT LINES

YES

WITH PROPER

PULL-UP

RESISTORS

(SEE APPENDIX A)

ARE

QUIESCENT
LEVELS

CORRECT

ISOLATE SOURCE

YES

OF PROBLEM

(BREAK BUS
SEGMENTS

SYSTEM

AND TERMINATE

CONFIGURATION

SUCCESSIVELY

RULES FOLLOWED

SMALLER
SECTORS

. NO

:
REFER TO

OF THE UNIBUS

YES

WHILE

SECTION

MONITORING

2 FOR SYSTEM

THE QUIESCENT

CONFIGURATION

LEVEL ON THE

RULES - IF

BAD LINE)

CHANGES

ARE MADE

RETURN TO(R)

BAD

DRIVER OR

RECEIVER

CHECK PBWER‘
SUPPLIES,

TERMINATORS,
SHORTS
REPLACE BAD
DRIVER OR

RECEIVER

AND/OR OPENS
ON THE

UNIBUS -

RESOLVE THE

PROBLEM

BEFORE

CONTINUING

CP-2584

Figure 3-1

Unibus Troubleshooting Flowchart (Sheet 1 of 3)

3-2

DOES
PROCESSOR

HAVE SACK

TIMEOUT OR

BOOTSTRAP
LOADER

YES

HI/LO

TERMINATOR

lDO

HI/LO

SINGLE-ENDED

TERMINATOR

MARGINING

CARDS FROM

CARDS

REFER TO

REGIONAL

OFFICE

SINGLE-ENDED

MARGINING

CARDS

OBTAIN

YOU HAVE

OBTAIN

YOU HAVE

YES

SECTION 4
AND PERFORM

CARDS FROM

HI/LO

REGIONAL

TERMINATOR

OFFICE.

TEST.
NO

DO YOU
HAVE UVM-TA
TESTER BOX

DOES
OBTAIN

UVM-TA TESTER

YES

BOX FROM
REGIONAL

1. DOULBLE
CHECK THE

WITH HI

‘

REFER TO

OFFICE.

SYSTEM OPERATE

TERMINATOR
CARDS

SECTION

1. DOUBLE CHECK

4 AND PERFORM

THE QUIESCENT

YES

SINGLE-ENDED

VALUES

MARGINING

2. TRY REPLACING

TEST.

THE 380

RECEIVERS

QUIESCENT

WITH 8640°S

VALUES.

3. YOU MAY

2. TRY REPLACING

HAVE TO OBTAIN

380 RECEIVERS

UVM-TA FROM

ON FAILING LINE

REGIONAL

WITH 8640'S

OFFICE

3. POSSIBLE
CAUSE IS

REFLECTION

ON UNIBUS OR
MARGINAL

POSSIBLE

RECEIVER (TRY
INSTALLING A

CAUSE
IS

M9202-2

REFLECTIONS

BUS JUMPER

ON UNIBUS

DOES

OR A MARGINAL

SYSTEM

BUS RECEIVER

OPERATE

(TRY INSTALLING

PROPERLY

AN M9202-2

NOwW

REFER TO

BUS JUMPER

DOES
SYSTEM
OPERATE WITH
LO TERMINATOR

CARDS

IF MULTIPLE
BUS SYSTEM, -

REPEAT HI/LO

MARGIN TEST

FOR REMAINING
BUS SEGMENTS

SECTION 2
FOR SYSTEM

CONFIGURATION
RULES - IF

CHANGES MADE

RETURN To®

Figure 3-1

Unibus Troubleshooting Flowchart (Sheet 2 of 3)

3-3

YOU HAVE

UVM-TA TESTER

FIND CRITICAL

BOX

LINE OR LINES.

(START WITH

MSYN, SSYN,

OBTAIN

UVM-TA TESTER
BOX FROM
REGIONAL
OFFICE

INTR, SACK
AND BBSY) IF
PROBLEM NOT
HERE TRY

REFER TO
SECTION 4

AND PERFORM
UVM.TA

OTHER SECTIONS
OF THE BUS.

MARGINING

TEST

1. LOW BYTE

DATA

2. ADDRESS AND

C LINES
3. REQUEST LINES
4. HIGH BYTE

DATA
DOES

SYSTEM OPERATE

NORMAL

TERMINATION

UVM-TA

MARGINING

WILL NOT

(+5v)
{

TIME.
DISCONNECT

P
:

REPLACE

\\_

::fi:;'xmofis

PROPERLY

| DEVICE AND
REPAIR IT.

REPLACE THE
BUS RECEIVER

_NO

AND/OR DRIVER

ON THE FAILING

LINE)

START AT

JERMINATORS

START)

SYSTEM

POINT WHERE

[ ves

OPERATES AND

SLOWLY ADJUST

WITH 4.2V

‘

TERMINATOR

DOES SYSTEM

OPERATE

CRITICAL

.
:

WITH 7V APPLIED TO _~

(RETURN TO

" FIND THE

(POSSIBLY

DOES SYSTEM

OPERATE

;

(

YES

UVM-TA AND

HELP AT THIS

PROPERLY WITH

VOLTAGE

PROPERLY

APPLIEDTO

TERMINATORS
N

UNTIL FAILURE

OCCURS {RANGE

OF 4.2 TO 7V)

START AT +5V
AND SLOWLY

| YES

DISCONNECT

MARGIN BOX

AND REPLACE -

ISTHIS A

;

MULTIPLE

WITH REMAINING
BUS SYSTEM

UNTESTED BUS

N\ SEGMENTS
pd

DECREASE

TERMINATOR

’

]

VOLTAGE UNTIL

FAILURE

Q
,

|
.

YES

SYSTEM
TERMINATORS

REPEAT FOR
ALL OTHER

BUS SEGMENTS

—

B
CP-2603

Figure 3-1

Unibus Troubleshooting Flowchart (Sheet 3 of 3)

3-4

3.2.3

Interrupt Transactions

A typical 11/45 system will experience problems if the data lags the INTR line on the cable by more
than 30-40 ns. Most DEC interfaces assert the vector address and INTR at exactly the same time and
Unibus skew times may cause a timing problem if the bus is long. Experiments with a typical system
show the vector address lagging INTR on the cable by as much as 30 ns with 9.14 m (30 ft) of Unibus
cable and a TC11 or 45 ns with 9.44 m (31 ft) of bus and a DL11. The electrical configuration rules as
|
listed in Chapter 2 will minimize these problems when properly applied.

|
3.2.4 High-Frequency Cable Losses
may
effect,
skin
as
known
frequencies,
high
at
resistance
The increase in transmission line conductor
be a factor in bus analysis. This function exhibits a very fast rise time to 50 percent of the input, but a
very slow dribble up from 50 percent to 90 percent of the input.

A 15.24 m (50 ft) bus cable could theoretically have a dribble up noticeable for up to 170 ns in response
to a step function at the input.

The bus should, therefore, be kept as short as possible to avoid potential timing problems. The published (i.e., allowable) Unibus length is 15.24 m (50 ft), but it is desirable to use as little cable as

possible for a given configuration (see Figure 3-2). Devices should be physically arranged in the same
order as they are electrically connected, if possible. (If M9202 folded cables are needed due to physical
arrangement, they should not be replaced by M920s in order to decrease bus length.)

]

]
CABINET

CABINET

THIS

NOT THIS

CP-2587

Figure 3-2

System Cabling Configuration Example

3-5

3.2.5

Peripheral Data Rate

Itis possible to support only a certain rate of data transfer on the Unibus - beyond this rate, data late
situations will occur. A method for roughly determining permissible combinations of simultaneous
peripheral device activity (such as would occur when executing DECX11) follows.

Determine a window for a given system based on the slowest NPR device transfer rate (us).4
If you have an RK11, RPI1, TM11 and TCl1, the slowest device will be the TC11 with a

transfer rate of 200 us /word

Window = 200 us (in this case)

Determine how many transfers the faster devices will perform in the window time.
(Window Time)/(Transfer Rate)
RK11(11.1 us/word)
TM11 (27.7 us/word)
RP11 (7.5 us/word)

200/11.1 = 18.02
200/27.7 = 7.22
200/7.5 = 26.66

Calculate the total number of transfers occurring within the window.
TCIll =1
RKI11 = 18.02
RPI1
= 26.66
TM11 = 7.22

Total = 52.90 transfers will occur within 200 us window.

Calculate the time per transfer by dividing the total number
of transfers into the window
time.
200 + 52.9 = 3.78 us/transfer rate

If this figureis greater than 2.5 us*, the system should run without data lates. (Thisis approx1mately a
rate of 400 kHz.)

3.3

PROPAGATION DELAY

If a voltage is supplied between any two conductors, they may be considered as a transmission line.
The ideal transmission line input impedance looks like pure resistance but, in fact, is mainly a combination of capacitance and inductance (see Figure 3-3).

When the voltage at one end of the transmission line is changed, that change does not instantaneously
appear at the other end. There is some delay, which is called propagation delay (see Figure 3-4). The
propagation delay of BC11 Unibus cable is approximately 1.4 to 1.9 ns per foot (or .0348 m).

*Bus repeaters and bus switches will decrease the data rate supportable on the bus. A figure of 3.0 may be more
applicable on a repeated line.

M
/1

AY!

|
1
CP-2588

Transmission Line Circuit Example

Figure 3-3

15.24 m (50 ft) BC11 CABLE

(B)

(A)

I
|

I
I

I_ PROPAGATION

TIME

L
_

|
I

DELAY
CP-2589

Figure 3-4

BC11-A Unibus Cable Delay Example

3-7

A lossless transmission line of infinite length looks like a pure resistance of value Z L/C.If such a
= Z), the line will behave like an infinitely
lineis broken and terminated with a resistor of this value (R
long line, i.e., appear resistive (see Figure 3-5). The impedance (Z) of Unibus BC11 cableis approximately 120 ohms with Unibus foam and as low as 60-80 ohms unfoamed.

Z = 1204
|

R (TERMINATION)

CP-2590

Figure 3-5

BCI11 Unibus Cable Impedance Example

When a voltage is applied to the line, the instantaneous power consumed will be:

= E2/Z

P = E2?/120

Suppose now that the terminating resistor (R)is not equal to the characteristic impedance of the line.

The power which is traveling down the line before it reaches the termination (during propagatlon
delay) is equal to E?/Z, but the power d1ss1pated in the resistor after propagation delayis approximately equal to E2/R.

If resistance (R) is greater'than the impedance (Z), there will be extra energy available at the termi-

nation and since energy cannot simply disappear, it will be reflected back into the line. After one more
propagation delay (for the return Journey) this reflection will be seen back at the source (see Figure 36A)

3-8

(

(A)

I
|
(SOURCE)

|
|
|

(B)

I
I

—_—

|
|
'
Pds
—l@—
Pds
—"I"— Pd:z —‘DI“"— Pds —.I‘—!
I

(TERMINATION)

CP-2591

Figure 3-6

Impedance Mismatch Example

Some of this reflection will be dissipated by the source impedance and some will be re-reflected back
into the line. When this re-reflection is seen at the termination (Figure 3-6B), (after still another propagation delay), the energy difference will be reflected back to the source. Eventually both source and
termination will arrive at the same level. The important point to note here is that what was intended to
be a level change with a clean transition did not turn out that way on the line due to a termination

mismatch between R and Z.

Essentially the same situation occurs when the termination resistor is smaller than the characteristic
impedance of the line. If resistance (R) is less than impedance (Z), there will be a mismatch and this
will also be reflected back to the source (see Figure 3-7).

(SOURCE)

(TERMINATION)

—_———
e

REFLECTION

CP-2592

Figure 3-7

Impedance (Low Resistance) Mismatch Example

3-9

Note that: (a) transmission line which is not terminated in its characteristic impedance will have reflections and (b) the voltage seen at any point on the line or at any instant in time will be a combination of
the incident and reflected voltage.

The amount of reflection depends on the mismatch, and approaches 100 percent for either a shorted or
an open line (see Figure 3-8).

+100%

REFLECTION

R=2

R>
2

-100%
CP-2593

Figure 3-8

Mismatch Reflection Curve Example

Essentially the same thing happens on the negative going edge of a level change so that what seemed to
be a clean transition as in Figure 3-9A, may look more like Figure 3-9B.

CP-2594

Figure 3-9

BCI11 Unibus Cable Mismatch (Waveform Example)

3-10

To further compound the problem, each dev1cein the bus contrlbutes its own unique 1mpedance and
mismatchin complex time relationships (Figure 3-10).
-

SOURCE

DEVICE

—_—

|
|

SOURCE

DEVICE

CP-2595

Figure 3-10

System Device Impedance' Example

All of this impedance and resistance mismatch is normal and to be expected in Unibus systems. The
objective here is to point out the possible impedance mismatch and how to use the appropriate tools to
minimize the effects of reflections and “noise’’. Reference the techniques listed in the following

paragraphs.

3.3.1

Line Termination Technique
The question may be asked, how can a 178 and 383 ohm resistor properly terminate a line which has an
impedance of 120 ohms?

3-11

A perfect power supply has an ac resistance (impedance) of zero ohms, so for ac considerations the

Q
178

Z2=120Q

(A)
383 ()

(B)

wA——w\~

termination diagram changes somewhat to that shown in Figure 3-11B and simplified in Figure 3-11C.

Z =120
()

, 3839%

178 0 i:
+5V
POWER

SUPPLY

L
|

Z=1200
(C)
A

A
A A A4

R1 <

178 Q) 1

> R2

Y (383) Q)

CP-2596

Figure 3-11

Line Termination Technique Example

The choice of these two values satisfies both the quiescent condition and the required termination
impedance.

3.4

CABLE AND CONTACT RESISTANCE LOSSES

The threshold point at which a bus receiver switches (asserted) fromaQOtoalis approximately 1.3V.
If a driver cannot pull the line low enough to completely assert the line, erratic system operat1on will
occur. There must be adequate low-threshold margin to prevent this problem
In the asserted (low true) condition, wire and contact resistance may cause the input voltage at a
receiver gate to be higher than the driver output.

3-12

(

178 )

383 ()

%
ol
+5

178
Q

AAA

T
V Rub

(DRIVER)

(RECEIVER)

CP-2597

Figure 3-12

Cable Resistance Problems Example

Referring to Figure 3-12, assume a pure cable resistance of 0.62/.3048 m (1 ft)* and ignore contact
resistance (which would only aggravate the problem). If the cable between the driver (A) and receiver
(B) were 15.24 m (50 ft), then Ryg = 30, or 0.6Q2 X 15.24 (50) = 9.14 (30).

A voltage will be developed acr}c)ss Ry;p with the polarity as indicated when the driver asserts the line.
This voltage could be as great as 0.7 V.

V;, will not be 0.8 V, but instead
Vin =08V + VRUB

In this case, V;, might be as high as 1.5 V (0.8 +0.7) and erratic system operation may result. Unibus
cable card contacts must be clean (to minimize contact resistance) and cable length should be as short
as possible (to minimize wire resistance).

*BCI11A cable is typically 0.1Q/0.3048 m (ft). Considering the return path in addition to the signal line, cable

resistance is approximately 0.22/0.3048 m (ft) of cable length.

3-13

CHAPTER 4
BUS MARGINING

4.1

GENERAL

Experience has shown that a properly functioning Unibus will operate with terminator source voltages
of between 4.2 and 7.0 volts without any adverse effects. If the voltageis varied between these values, it
may be possible to detect and /or aggravate bus problems and thus make it easier to define and correct
the failures. At present, there are two methods that can be used to change the quiescent levels on the
Unibus for margining purposes.

1.
2.

‘

Use a Unibus Voltage Margin Tester Box to vary the source voltage applied to the termi-

nator network.

Use Hi/ Lo Terminator Cards to vary the terminator network (rather than the Voltage) The
hardware required for this method is less expensive and more portable than the Unibus
Voltage Margin Tester Box, however, this method is more difficult to use for troubleshooting Unibus failures.

NOTE
~ A third method, referred to in this manual as the

single-ended margining techniques, is an extension of
the UVM-TA method described in item 1. This
method must be used for those processors that
employ Sack turnaround or Bootstrap functions on
the terminator cards.
4.2

BUS QUIESCENT LEVELS

Normal bus quiescent levels are listed in Table 4-1. Any level that deviates from the normal level
should be considered as a potential failure. In many instances the improper level will be the result of
either a defective bus receiver or driver. In the case of AC/DC LOW, these levels are power supply
dependent.
Table 4-1

Bus Quiescent Levels

Signal

Quiescent Level

BG 7:4

+.45V (£0.35)

NPG
AC Low
DC Low

+4.9V (£0.35)

All Others
(Except BBSY wh1ch depends on CPU type)

4-1

+3.4V (0.2 V)

To measure quiescent Unibus levels:

Turn the system on with the processor halted. Press the START key and release it (with

Usea calibrated oscflloscope (or voltmeter) to measure the Unibus signal lines. (See chart of

HALT down).

Unibus slot backplane pins, Figure 4-1.)
NOTE

To obtain meaningful readings of bus grant lines (BG
4:7 and NPG), they should be measured at the grant
input of each device down the length of the bus.

All buses should be checked in multiple bus systems.
4.2.1

Qulescent Conditions

Low true lines: (Address, Data, Control and Arbitration)

The low true Unibus lines are characterized by a termination at both ends and some number of
“loads’ determined by the system configuration as shown in Figure 4-2.

In the quiescent conditions we are dealing with dc levels. Ignoring loads for a moment, consider the

equivalent Unibus line circuit based on termination alone as shown in Figure 4-3.

The quiescent dc level on the line may be calculated using Ohms law, where:

I = E/RI+R2 = I = 5/89+191.5 = 0.0178A
E

0.0178X191.5

(IXR2)

3.4087 (3.41) volts

If the potential on the line were measured (with respect to ground), it would be 3.41 volts as shownin
Figure 4-4.

In theory, the loads should not affect the quiescent level of the bus lines, but in practice this is impossible to achieve. To be considered acceptable, one load cannot contribute more than 210 uA of leakage
current (see Chapter 2 for definition of dc unit load), but even this level will have an effect on the
quiescent level of the line.

If 20 loads are added to the original example (Figure 4-5), with each drawing 210 p,A of current, the
calculatmn changes somewhat.
(20 X 210 uA = 0.0042 amps of leakage current)

The total current through R1 now increases which inéreases the 1R! drop.
The quiescent level of the line will now be approximately 3 volts.

4-2

(VIEWED FROM BACKPLANE)
1

INIT
L

A o/ @— +5

INTR L

s @ O
c® @

ce @

r e

05 g
08

oo
Q-

K ‘/

LQ/

N D
PO

(

R @

(

k__

BBSY

|[
@-

SACK
_

NPR

il vty

BR6

|
BG6

BRS |

BR4 |

N
r@

s®

)

sd @

+ 3% _|

§§\

06
o >

|
FC

ADDRESS LINES

10
12

16 _J

o
SSYN
€0 mswn

KEY
@® 34viz2v
O

45VvI(+35V)

49V (+35V)

@ GND

@D +5

Figure 4-1 Unibus Slot Backplane Signals
4-3

Lo -E

l pcio !

P ®
e e

|
|

r@ @

PB
'

6o
w
A

15J_’PA

@—+5

—11

[

vo
Al

DATA LINES

|
LOAD

LOAD

CP-2579

1781

3830

Low True Unibus Line

iF—wW—t A

AW —————AW— +

Figure 4-2

891

178Q

191.56Q

3830}

j
|

I = .0178A

CP-2580

Figure 4-3

Equivalent Unibus Line Circuit

4-4

CP-2581

Figure 4-4

Quiescent dc Level Example

S
R1 pS

R2 2

)

r’

D ,

(
=

210U a

‘:‘

2104a

D <.

©@

<‘o

0 <

20 |

210 U a

CP-2582 |

“

Figure 4-5

Load Current Leakage Example

4-5

3.7

3.6 b

QUIESCENT

‘

LEVEL

3.3

3.2

TERMINATORE

—

=5 V

3.0

29 —

{

}

— TERMINATORE = 4.5V

2.8llllllll\l_\[lllllLllll
5

10~

~
@——

BUS LOADS

(WORST CASE)

—

2.7

TM~

_ 2.6

S~
\

Figure 4-6

CP-2583

Quiescent Level vs. Bus Loading (Worst Case)

By Unibus convention, these lines are asserted true when low (=1) and negated when high (=0). The
threshold point at which a receiver switches from a one to a zero is approximately 2.5 V using a DEC
to force
380 Receiver Module (or 1.7 V with an 8640 Receiver Module). If enough loading is present
- the quiescent level low enough (see Figure 4-6), system operation may become extremely erratic.
(There must be an adequate noise margin above the threshold level to allow for crosstalk and
~ reflections.)

4.2.2

Multiple Bus System Considerations

~ Multiple bus systems are those which include bus repeaters or bus switches; the entire Unibus is re- -

| propagated (see Figure 4-7). When margining techniques are employed with multiple bus systems, it is
desirable to margin all bus sections on an individual basis. (It is not necessary to margin multiple buses |
simultaneously.)

asnsg

+“"’ —AN——T— A

0 AN——AA={

H31lv3id3d

sng

0 ——aM—— A

sSNaINN 8

0 Al

JSNYIN

S+

M —a—]li

S+

NdJ.SN8INVv“

S+

sng

§+

4-7

&—AM—-{N

It is important that the correct termination'pbints are used for any given bus in a system - do not guess.
Refer to the module utilization prints to determine which terminators go with which bus.

4.2.3 Grant Line Termination

The grant lines on the Unibus represent a special case of termination and assertion levels (high = true).
Grant lines may not always run from one physical end of the bus to the other. The Grant line is broken
at each device wired to it and repropagated if that device is not requesting (see Figure 4-8). It should be
noted that changing the bus quiescent levels at the terminator will not affect grant lines which have
been repropagated. To measure the quiescent level of grant lines or to observe grant line waveforms, it
|

is necessary to check at the specific point of interest.

DEVICE A

178 Q"

UNIBUS l——

* M930 TERMINATORS

DEVICE B

p— =%

—F UNIBUS F%—D
CHANGING QUIESCENT LEVELS

1780 ¢

UNIBUS

CP-2598

(BY CHANGING TERMINATOR
VOLTAGE OR NETWORK) DOES

NOT AFFECT GRANT LINES
WHICH HAVE BEEN REPROPAGATED

Figure 4-8

4.3

Grant Line Bus Margining Technique

HI/LO TERMINATOR BUS MARGINING

The Hi/Lo Terminator cards (see Figure 4-9) are designed to test the high and low bus margining
voltages by varying the terminator network (rather than varying the voltage when using the UVM-TA
tester). The M930 terminators must be removed from the system under test and be replaced by M9304
low margin or by the M9304-Y
A high margin terminator cards.

There is a special terminator used in the 11/35 and 11/40 processors which combines the functions of a
terminator and a unibus jumper module (M981). There are Hi/Lo terminator cards to fit this application also (M 9305 low margin and M9305-Y
A high margin).

4-8

Margin terminators are used as a go/no go test and are not to be installed in the system on a permanent
basis. (They are too lar ge to fit in an expander box with the covers closed which will help avoid this
mistake.) Figure 4-10 illustrates the circuit representation of the Hi/Lo terminator cards plus representative load v»alues.
|
WARNING
When using special terminators, it is important that

the same type (Hi or Lo) be installed at both ends of
the bus for the test to have meaning.

Figure 4-9

Margining Cards

4-9

tov
121

+5V
121 ()

+5V
196 (!

196 )

UNIBUS

301 ()
'

(HIGH)

301
¢

(LOW)
CP-2601

Figure 4-10

Hi/Lo Terminator Circuit Example

High Margin

1.
2.

M9304-YA
(Replaces the M930 Terminator)
M9305-YA

(Replaces the M981 special case 11-35/11-40 terminator)

Quiescent = 5 V(1R drop caused by loads)

Failures here usually caused by weak drivers, receiver with marginal threshold or dirty bus cable
contact fingers.

Low Margin

1.
2.

M9304
(Replaces the M930)
MB9305

(Replaces the M981 special case 11-35/11-40 terminators)
Quiescent = 3.03-(1R drop caused by loads)

Failures here usually caused by a receiver with marginal threshold or reflections on MSYN, SSYN,
INTR, BBSY.

4.4

UNIBUS VOLTAGE MARGIN TESTER BOX

The Unibus Voltage Margin Tester (UVM-TA) is a portable tester designed to check all Unibus
receivers and drivers in a system, either singly or as a group. Figure 4-11 illustrates the circuit representation of the UVM-TA plus representative load values. The control panel (Figure 4-12) furnishes a
switch for each of the designated bus signals and is used to provide fixed (+5 V) or variable termination voltage to special terminator boards (called Margining Heads - M9303) which are used in place
of the standard M930 terminators. The margining heads cards allow the voltages selected to be applied
to each terminating network on an individual basis. Refer to Figure 4-13 for a block diagram overview
of the UVM-TA.
NOTE
This does not change the effective Unibus length.

4-10

]

UNIBUS

3 383 ()
fl

UVM-TA

2 1780

VARIABLE
ZSZVPEL':(

3178 Q

)

S 3830
<

"
CP-2602

Figure 4-11

UVM-TA Circuit Representation

Figure 4-12

Controls and Indicators

UNIBUS VOLTAGE MARGIN TESTER (UVM-TA)

VARIABLE

DC POWER

SUPPLY

VARIABLE DC

Ldb s
T

T T

(66 SWITCHES -- ONE FOR

EACH LINE ON THE BUS.)

$4dd

TTT{

FIXED DC +5V
FIXED

+5V DC

POWER SUPPLY

' | l

" BC11 CABLE

WARNING: Do NOT plug this
cable directly into a UNIBUS
slot -- it comes directly

from the power supplies and

may damage UNIBUS drivers

EITHER +5 V FIXED

MARGINING HEAD

¥~ __ OR VARIABLE DC

(11/:

)

AS SELECTED BY

[

)

180 &

SWITCH IN MARGIN

regT02.

390

PIN COMPATIBLE WITH/ n
M930 TERMINATOR

D-q
CP-2604

Figure 4-13

UVM-TA Block Diagram

4.4.1

Functional Description

Functionally the UVM-TA consists of a fixed supply, a variable supply, a control panel, Unibus
cables, and terminator cards that enable the user to margin voltagesin the Unibus sections.
NOTE

The use of the Unibus cable with this tester is as a
power transmission cable.

The fixed supply provides the voltage for normal system operation. The variable supply (when
selected) provides the variable voltage, for system margining purposes. The front panel controls and
indicators control the choice of fixed or variable voltage, vary the voltage, display the voltage, indicate
both ac and dc power on, and select individual Unibus signal lines.
CAUTION

This Unibus cable must never be plugged directly
into a CPU, option or peripheral while connected to
the tester — it should be plugged into the margining
head only.

With the recommended program (DECXI11 or operating system) running in the system, the user now
selects any or all lines to be margined. The respective switches should be placed in the VARIABLE
position. The margin voltage can then be varied by using the VARIABLE potentiometer. The voltage
level at which the system fails or when the limits of the supply are reached, may be obtained by viewing the metered display.

4.4.2 UVM-TA Operation and Test Procedures
1.

Unlatch and remove the top cover from the suitcase tester and place to one 51de This allows
room for the cabling to be connected into the tester box.
'

Remove test heads M9303, M9303-Y
A and BC11-A from inside the top cover pocket. Place
all signal switches (56 total) in the “down’ or FIXED position. Place power switch in the
OFF position.

3. Turn system power off. Remove the M930 terminators from both ends of a section of bus in

the unit under test and replace w1th the M9303 margining heads (M9303-YA for 11/40
CPUys).

4.
5.

Plug the Unibus cabl;: (BC11A) into the margining heads.
Plug the (BC11-A) power cable into the margining heads. Plug the BC11-A cable into tester
slots 1 and 2.
CAUTION

Plugging the BC11-A Unibus cable directly into a
CPU or peripheral without the test heads M9303YA may cause the Unibus drivers to burn up.

4-13

Plug tester box ac cord into a convenient power source. Power can now be applied to the
system and the tester.
Place power switch in the ON position and adjust the variable voltage to +5 V.

Load recommended programs (DECXI11 or operating system).
NOTE
Slgnal switches must not be switched while the system is running. Always halt the system before
attempting to change selection switch setting.

There is one switch for each of the designated bus signals and is labeled on the tester box

control panel. By setting a switch in the VARIABLE *“‘up” position, the margin voltage
displayed is applied to the individual pull-up resistors and thus the signal lines can be margined by varying the VARIABLE potentiometer.

With the system halted, put all (56) bus signal switches in the VARIABLE ““up” position.
Restart system running the selected program. Adjust the variable voltage to 6 V and run
system for 15 minutes (or longer) with all options selected. Then, increase in .5 V steps (or
smaller increments if necessary) until the failure occurs. Record thls value.

CAUTION

Halt and restart the program each time a new voltage is selected when running DECX11.
10.

Adjust variable voltage to 4.5 V and run system for 10 minutes (or longer). Then, decrease in
.5 V steps (or smaller if necessary) until a failure occurs. Record this value.
|
|
CAUTION
Halt and restart the program each time a new voltage is used when running DECXI11.
|

11.

Every system must run between 4.2 V and 7 V. If a system failure occurs, margin the follow-

ing five signals only:

SSYN, MSYN, INTR, SACK, BBSY

12. If it is not one of these signals that failed, continue to margin sections of the bus until a line
a0 o

failure or group of linesis 1solated as the problem area. Repair the defective line and recheck
the margins for:

13.

Low byte data
Address and C lines
Request lines (NPR/BR)
High byte data
Remaining lines

When tests are complete, turn power off, remove the special test equipment, replace the
terminator cards and remove tester from power source.

4-14

4.5

SINGLE-ENDED MARGINING

For some processors, it is not possible to use the M9303 series of margin heads with the voltage margin
tester. This is because some machines include additional hardware on the terminator module (bootstrap function, sack turnaround, etc.) which must be present for the machine to operate normally. For
these machines, a single-ended margining technique has been developed (PDP-11/04; 11/34). This
|

technique may be used with any Unibus machine.

Single-ended margining is accomplished by placing a voltage margin terminator on only one end of a
bus segment and varying the voltage applied to it ((see Figure 4-14). This accomplishes the same results,
but the considerations are slightly different.

NOTE

Using the M9308 single-ended margin terminator, a
system should operate successfully between 7.85 V
(high margin) and 2.93 V (low margin) as displayed
by the panel meter on the voltage margin tester.

+5V

SYSTEM TERMINATOR

180 0

| s |

)

UNIBUS VOLTAGE

|| ‘L: :I
1 |

390 0 3

BUS LINE

MARGIN TESTER

M9308 SINGLE ENDED

MARGIN TERMINATOR
CP-2605

Figure 4-14

4.5.1

Single-Ended Circuit Example |

Setup and Operation (Using M 9308 Single-Ended Margin Head)

Unlatch and remove the top cover from the suitcase tester and place to one side. This allows
room for the cabling to be connected into the tester box.

2. Remove test head M9308 and BC11-A from the inside cover top pocket. Place all signal

switches (56) in the “down” or FIXED position (). Place power switch in the OFF
|

position.

4-15

Turn system power off. Remove the M930 system terminator (see application table) and

(

install the M9308 margin head. If the M9308 is not used at the electrical end of the bus,

disable SACK turnaround with the switch located on the M9308 module.

Plug the Unibus cable (BCl1 1A) into the M9308 margining head.

CAUTION

Connecting the BC11 power cable directly into a
CPU or peripheral without the margin head may
cause equipment damage.

Connect the BC11 power cable into tester slots 1 or 2.

|
|

\
|

Plug tester box ac cord into a convenient power source. Power may now be applied to the
system and the tester.

Place power switch in the ON position and ‘adjust the variable voltage to +4.34 V.
Load recommended programs (DECX11 or operating system).
"NOTE

There is one switch for each of the designated bus signals and is labeled on the tester box
control panel. By setting a switch in the VARIABLE “‘up” position, the margin voltage
displayed is applied to the individual pull up resistors - thus, the signal lines can be mar-

Signal switches must not be switched while system is
running. Always halt the system before attemptmg to
change selection switch setting.

gined by varying the VARIABLE potentiometer.

With the system halted, put all (56) bus signal switches in the VARIABLE position. Adjust
variable voltage to 6 V and restart system running program selected. Then, increase in .5 V
steps (or smaller increments, if necessary) until a failure occurs. Record this value.
CAUTION
Halt and restart the program each time a new volt-

age is selected when running DECX11.

10.

Adjust variable voltage to 4.0 V and run system for 10 minutes or longer. Then, decrease in
.5 V steps (or smaller, if necessary) until a failure occurs. Record this value.
CAUTION
Halt and restart the program each time a new voltage is used when running DECX11.

11.

Every system must run between 293 V and 7.85 V. If system failure occurs, margin the

following five signals only:

SSYN, MSYN, INTR, SACK, BBSY

12.

If the problemis not with one of the above signals, continue to margin sections of the bus
until a failing line or group of linesis isolated as the problem area. Repair the defective line

o oo

and recheck margins for:
Low byte data
Address + C lines

Request lines

High byte data
Remaining lines

13. When tests are compl.ete, turn power off, remove the special test equipment, replace the
terminator module and remove tester from ac power source. If margin values are recorded
for future use, be sure to note that these values were obtained with single-ended techniques.

4.5.2

Single-Ended Circuit Consideration

The user of the single-ended margining technique should be aware of the theory and application of the
Quiescent Voltage versus UVM-TA Voltage considerations. Calculations are not necessary because
Figure 4-15 is designed to provide this information. However, the difference must be made between
single-ended and double-ended margining techniques because of the different voltages that must be
applied by the UVM TA tester under these conditions.

Table 4-2 supplies terminator apphcatlon data for the M9308 single-ended margin head plus doubleended terminators, and how they relate to particular CPU bus segments. In bus segments not 1nclud1ng
a CPU, the same procedures apply.

According to Thevinen’s Theorem, any line or network of impedance and generators, when viewed

from any two points in the network, can be replaced by an equivalent voltage source and an equivalent
impedance in series. As an example, consider the termination network used on the M930 Unibus

terminator.

The voltage lookmg “back’ into the network will be 3.42 V because of the voltage divider action of R1
~and R2. Thisis an equivalent voltage source of 3.42 V.

1802

390¢2

CP-2560

4-17

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4-18

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4-19

The Thevinen equivalent impedance, Rty of the circuit is found by shorting the generator and calculating the circuit impedance.

CP-2561

The equivalent voltage source can be represented by a circuit consisting of a 3.42 V source in series
with an impedance of 123.157 ohms.

79 (X)
|

118.4Q)

APPLIED

VOLTAGE

CP-2562

The termination network used on the M9308 single-ended margin terminator consists of 180 ohms to
the voltage source and 562 ohms to ground (see Figure 4-16).

If this network is considered a Thevenin generator, it becomes a source of 78.9 percent X voltage
applied (because of the voltage divider action) in series with 118.4 ohms.

+ 5V

%18052

150(2

1231}

3900

\— BUS LINE

BUS LINE 562&2%
Figure 4-16

118.4

M9308 Termination Circuit Example

4-20

CP-2563

The voltage seen on the bus line may be computed by considering what happens when these two
generators are connected together. For example, if the M9308 has 7.85 volts applied to it:
.

E=616-342=274V

Rt 123Q + 118.4Q = 241.4Q

I=E/R=1135mA

Voltage drop across R

Voltage on the bus line = 3.42 + 1.396 = 4.8 V

11.35 mA X 123Q = 1.396 V

In this appli_cation (since the Thevenin equivalent impedances are similar), a simple rule of thumb is:
342

(0.79

UVM-TA)/2

V bus line

4.5.3

SACK Timeout
In some processors, if SACK is not received within ten ms after a grant is 1ssued the processor will
timeout and proceed as if no grant had been issued (unless, of course, a request llne continues to be
asserted). In others, the processor will continue to wait for the return of sack; this will cause the bus to

hang. This problem is solved on some terminators by turning bus grant around and sending SACK
back to the CPU. The processor will then release BBSY and, if no device is requesting, will immediately regain control of the bus through the passive bus release mechanism. The M9308 margin head
will turn bus grant around into SACK and set a latch. There is a LED installed on the M9308 to
“remember’’ the fact that a grant was received (not a normal condition at the end of the bus). Switches
are provided to enable SACK turnaround and reset the latch (see Figure 4-17).
|
NOTE
If SACK turnaroundis enabled, the M9308 must be
used at the electrical end of the bus.

4.6

MODIFYING M930 TERMINATOR CARD

/—\\

\\‘

If the test equipment previously described is not avilable, it is still possible to employ voltage margining techniques.
|
4.6.1

Equipment Required

Variable dc power supply with a 1 percent a regulation (or better) and a 2 amp output rating
(m1n1mum)

Modified M930 Terminators (two each).

4-21

BUS NPG H

A A A4

“ENABLED"

j_'_/o

BUS BG7 H

BUS BG6 H

BUS SACK L

BUS BG6 H

BUS BG4 H
|

D—@———W\- +5V

CLK
* THE switches and

“RESET"

-SL__/

L.E.D are labeled

on the M9803 Module

NOTE: If SACK turnaround is enabled, the M9308 must be

used at the electrical END of the bus.

CP-2607

Figure 4-17

4.6.2

M9308 SACK Turnaround Logic

Modifying the M930

On side 2 of the M930, cut etch at pin AA2,

On side 2 of the M930, cut etch at pin BA2.

Attach one end of a 4.57 m (10 ft) piece of No. 16 gauge (or lai'ger) insulated wire to the etch

as indicated in Figure 4-18 (step 3). This will be the plus (+) lead to the variable power
supply.

Attach one end of a 4.57 m (10 ft) piece of No. 16 gauge (or larger) insulated wire to the etch

as indicated in Figure 4-18 (step 4). This will be the minus (-) lead to the variable power
supply.
|

4-22

M930

STEP 3

U ]

€,<>/

\EP 4

STEP 1

Figure 4-18

M930 Modification Example

{

/A~

CP-2608

4.6.3 Proceduré for Use
1.

Turn all system power off.

Connect modified terminators to the variable power supply (double check polarity).

Reflmove system M930 terminators from Unibus.

Install modified terminators in system where stafidard terminators were.

Turn on variable péwer supply and adjust output to +5 V.

Turn on system power.

| 7.

Proceed with bus margining as described in Paragraph 4.3.

4-23

CHAPTER 5

UVM-TA TESTER

5.1 UVM-TA OVERVIEW
This chapter provides DIGITAL Field Service personnel with sufficient information to operate and
maintain the Unibus Voltage Margin Tester (UVM-TA) and use it to troubleshoot Unibus Problems.

The UVM-TA is a portable device (see Figure 5-1) designed to check all Unibus receivers and drivers
in a system by applying a margining voltage to the Unibus lines. The tester provides a dc termination
voltage to special terminator boards. These special terminator boards, called margining heads, are
used in place of the standard M930 terminator. The margining heads do not change effective Unibus
length.
5.2

TESTER KIT COMPONENTS
The complete tester kit consists of the components shownin Table 5- 1
Table 5-1

Number

Description

‘

Tester Kit Components

Part Number

UVM-TA Tester
|

Margining head

| M9303

Margining head

M9303 YA

TBS

Unibus Cable

BCI11-A

UVM-TA Troubleshooting
Guide

The UVM-TAis a relatively simple electrical Unibus testing device. It contains two dc power supplies
(a fixed supply and a variable supply), a digital voltmeter (DVM) to monitor the power supplier, and
56 SPDT switches.

The fixed 5 Vdc power supply prov1des the Voltage normally used to terminate the Unibus lines. Any
of the 56 Unibus line switches placedin the fixed position will connect the terminating network of the
selected line to the fixed supply This allows the operator to keep certain lines at the normal terminating voltage while varying the terminating voltage on other lines. The fixed supply also supplies
power to the DVM.

The variable dc power supply provides between 2 and 8 Vdc to margin Unibus lines. The supply is
adjustable via a front panel control andis monitored by a DVM also located on the front panel. Any
of the Unibus line terminating networks can be connected to this supply by setting the correspondlng
data switch to VARIABLE.
5-1

Unibus Voltage Margin Tester Box

5.3

TESTER SPECIFICATIONS

The tester contains two dc power supplies, a fixed supply and a variable supply.
Fixed supply
Variable supply

5 Vdcat 2 amps
2Vto3dVat2amps

The tester is designed for use in the field. It is packaged in a brief case type carfying case and weighs 35

pounds. The carrying case holds the tester, margining heads, cables and the manual. The tester
requires 115 or 230 Vac (10 percent), 50 or 60 Hz single-phase power.

The front panel DVM normally monitors the variable supply. When the DISPLAY FIXED VOLTAGE button is pressed, the DVM displays the voltage of the fixed supply.

Figure 5-1

5.4 UNPACKING PROCEDURE.
To unpack the UVM TA:
1.

5.5

Remove the carrying case from the shipping carton and 1nspect for exterior damage Damage claim should be d1rected to the respons1ble shipper.

Open the carrying case and 1nspect the components for damage

Verify that all components are present (See Paragraph 5 2 for K1t Components)

ACCEPTANCE TEST

The UVM-TA is shipped ready-to--use. If the unit is not operatmg properly, refer to Preventive
Maintenance (Paragraph 5.9) to diagnose and correct the problem. Service should be performed by
qualified personnel only. A Tripplet (model 630-NA) or Slmpson (model 260) multlmeteris required

to perform the acceptance test
To check out the UVM-TA
1.'

Plug tester ac cord into power source |

Place 56 srgnal switchesin the down posmon |

. Turn tester on. Verify v1sua11y that power 1nd1cator is on, FIXED DC INTERNAL
indicatoris on, and DVMis displaying a voltage between 1 and 9 Vdc. An internal fan will
come on. This can be verified by listening for the sound of the fan.

Using the VARTABLE potentiometer, vary the internal variable dc supply between 2 and 8

volts. This can be verified by observing the DVM. Set the variable dc supply to 6 volts. The
VARIABLE DC INTERNAL 1nd1cator will be lit. Press DISPLAY FIXED VOLTAGE.
DVM will read 5 V.

Using the multimeter, probe pin BS1 of the test connector 1. Voltage will read 5 Vdc. Put
ADDRESS REGISTER switch in up or VARIABLE position. Voltage will read 6 Vdc. Put
switch into FIXED or down position and probe similar pin on test connector 2. Voltage will
read 5 Vdc. Switch to up position. Voltage will read 6 Vdc. Leave switch up to indicate it has
been tested.
6.

5.6

Repeat step 5 for remaining 55 Unibus signal switches.

CONTROLS AND INDICATORS

All controls and indicators for the UVM-TA are located on the front panel of the unit (Flgure 5-2).

The function of each control and indicatoris listedin Table 5-2.

577

OPERATING PROCEDURE

Refer to Chapter 4, Paragraph 4.4.2 for operating procedures.

5-3

7534-2

Figure 5-2

Controls and Indicators (Indexed)

5-4

Table 5-2

Function

Index No.

FUSE 2.5 AMP - Protects tester from current overload.

ON/OFF - Switch controls ac power to tester. |

ON/OFF Indicator - Lights when tester is on.

4 N

- 56 single-pole double-throw switches - control margining volt-

age to each of 56 individual Unibus lines. When in the down
position the selected line is connected to a 5 Vdc fixed voltage
supply. When in the up position the selected line is connected to
variable dc voltage supply.

Tester connectors — connects selected voltage levels to margining heads.

5.8

Controls and Indicators (Indexed)

Controls output voltage of variable voltage.

When depressed, digital voltmeter monitors voltage of fixed
supply voltage. DVM normally monitors variable supply

voltage.

Digital V.oltmeter monitors voltage of selected power supply.

| 9"' ‘:'

| |

| 10

VARIABLE llghts when variable supply is operating. Brightness is proportional to selected voltage.

- FIXED lights when fixed supply is operating.

MAINTENANCE PHILOSOPHY

Tester maintenance consists of preventive and corrective mamtenance procedures. The preventive
maintenance procedures should be performed regularly in order to detect any damage caused by
improper handling of the unit. A troubleshooting flow diagramis provided to aid service personnelin
isolating and repairing faults within the tester circuits. The troubleshooting flowchart and corrective
maintenance information given in this chapter covers only the tester unit. The flow diagram makes use
of the acceptance test procedure outlinedin Paragraph 5.5.

To perform drsassembly /assembly and preventive and correction maintenance, only a multimeter and
standard hand tools are required. Recommended multlmeters are: (1) Triplett model 630-NA or (2)
Slmpson model 260.
5.9

PREVENTIVE MAINTENAN CE

As preventive maintenance, the acceptance test procedure should be performed from time to time to
ensure complete operational readiness and to check the unit adjustments. The frequency of the checkouts depend on hours of handling, and envrronmental conditions. The schedule given in Table 5-3 is
suggested as a minimum time table.

Table 5-3 Preventive Maintenance Schedule
Performance Interval

Test or Procedure

Monthly

Visually inspect for physical damage; correct if required.
Clean externally.

Quarterly

Clean internally with vacuum cleaner or a soft brush
Check for looseness of the knobs, switches, and indicators.
Perform acceptance test procedure (Paragraph 3.5)

5.10 CORRECTIVE MAINTENANCE
If the tester fails the acceptance test or fails while testing a Unibus system, corrective maintenance
must be performed. The flowchart (Figure 5-3) will pinpoint the faulty tester component. However,
before using the flowchart, unscrew and lift up the control panel and perform a visual inspection. Look
for burnt or damaged wires or components. Replace any faulty wires and component(s), if found, and
perform the acceptance test procedure
to determine if the tester has been repaired. If not, begin using
the flowchart.
|
CAUTION
Certain circuits in the tester operate at 110 Vac.
Special care must be taken when probing near these
circuits. Before disconnecting, replacing and/or
reconnecting any part other than a fuse, turn tester
off and unplug it.
NOTE
Turn tester off when replacing front panel fuse.

5.11

DISASSEMBLY /ASSEMBLY

Many of the components within the tester are also accessible and can be replaced without performing
any disassembly. The switches, indicators, and plugs on the tester control panel are easily accessible for
repair or replacement. However, to remove either power supply, the transformer, or the fan, the tester
must be disassembled. To disassemble the tester, perform the following procedure:
1.

Unplug line cord.

Remove the tester from its carrying case by slipping it out of the case.

Unscrew and lift up the control panel.

Toremove the power supplies, remove the power supply bracket using a so'cket_ screwdriver.

4.
5.

Remove the transformer, unscrew the four mounting bolts at the base of the transformer

using a screwdriver. Unsolder the transformer connecting leads.

To remove the fan, first remove the fan mounting bracket assembly from the tester using a
Phillips head screwdriver. Unsolder the fan connecting leads. Then remove the fan from the
mounting bracket using a socket head screwdriver and a Phillips head screwdriver.

5-6

—
e
f

DC POWER

LAMPS 11 AND 12
s

BOARDS LIT

AC LINE

REGUALTOR

USE VARIABLE

CONTROL AND
ADJUST FOR

DISCONNECT

3 VvDC ON DVM

P2 FROM J1 ON

A,‘

CORD PLUGGED
’
PROBABLY BAD.

REPLACE

BOARD. SHOULD

NECESSARY

MEASURE 56 VDC

DVM

READS 3 vDC

BETWEEN PINS
TESTER

2 AND

OF J1.

TURNED

YES

I":\IODVIVCE:T(O)N

FUSE

CHECK FUSES

OPERATING

ON REGULATOR

PROPERLY _

BOARDS AND

REPLACE IF

FUSEHOLDER,.

NECESSARY

MEASURE AC

VOLTAGE

OF T1. REPLACE
FAN IF

NECESSARY

’

REPAIR

‘

POI\\IfI:ER

INDICATOR

LIT

,
'

REGULATOR

AND REPAIR.
POSSIBLE

PROBLEM

REGUALTOR

ADDRES

ADDRESS

'
|

YVES

BOARD(S) AS
REQUIRED

LIT

DVM IS

YES

PROBABLY

‘

BOARD OR BAD
-

DVM

‘

PROBLEM

| VES

INDICATOR

J1.

BOTH BOARDS

LAMP

+5 VDC ON

REPLACE

MEASURED

LIT

POWER

AND

LUGS T1 AND T2

VOLTMETER

FUSE

BETWEEN

ves

DIGITAL
REPLACE

BETWEEN PINS

110 VAC TM\

“MEASURED

MEASURE 5 VDC

2
FAN

YES

BLOWN OR
MISSING

ISOLATE

REGULATOR

BOARD. SHOULD

FROM J1 ON

VARIABLE

‘%

LIT

~AC

(o)

DISCONNECT
|

. REPLACE

?FA'\?ECESSARY

PRESS DISPLAY

FIXED VOLTAGE

PUSHBUTT

ON
ON

CONTROL PANEL
REFER TO

NOTE
1
BAD

AC POWER

DVM
READS 5 VDC

CORD
BAD

ON-OFF
SWITCH

REMOVE AND

IF DC POWER

TESTER

LAMPS ON

BLOWING

REGLATOR

FUSES

USE VARIABLE

CONTROL AND
ADJUST FOR 6
VDC ON DVM.

BOARDS ARE
LIT REPLACE

REPLACE BAD

(OR REPAIR)

POWER CORD

FIXED VOLTAGE

REPLACE

DISCONNECT

ON-OFF

UNIT FROM

SWITCH

AC POWER

SOURCE AND

PUSHBUTTON

DVM

READS 7 VvDC

ISOLATE

PROBLEM(S).

CP-2609

Figure 5-3 UVM-TA Troubleshooting Flowchart
5-7

APPENDIX A
~
|
ECO HISTORY AND REWORK

A.1

UNIBUS TERMINATORS (M930)

The initial ECOs to the M930 (dated 1970) changed the termination of bus AC and DC LO, which
brought the M930 to etch revision B. This etch revision is now obsolete. If system bus problems are
suspected for failure, later etch terminators than the B etch should be tried.

A.1.1

Revision C Etch

ECO No.3 to the M930 Unibus Terminators changed the termination resistors tolerance from 5 percent to 1 percent. This change improves the worst case noise tolerance and with suspected bus problems. 1 percent terminators should be used.

CAUTION

Some “C”’ etch terminators were manufactured with
missing etch runs. Pins AN1, AP1, AR1 and ASI1
should be connected to pin BE1. These runs were
omitted. The missing etch runs are grounds and if not
present may contribute to system noise.

A.1.2

Revision D Etch

ECO No.4 to the M930 Unibus Terminators adds four decoupling capacitors and improved grounding. This change significantly decreases noise on the bus. Rev D is the optimum etch revision currently
used (Sept. 1976) and should be used if bus problems are suspected because of old type etch boards.

There are other terminators which will be available for new processors and systems in the near future.
A.2

BUS RECEIVERS

A number of integrated circuit types (i.e., chips) have been or will be used as Unibus receivers (Table
A-1). Of these, the DEC 380 was most common. It has been phased out and is no longer available. A
recent series of ECOs to most options which used the DEC 380 now uses DEC 8640 Bus receivers. The
DEC 8640 is a pin-compatible replacement for the DEC 380 and is used in Unibus applications
because it has more closely defined specifications and higher noise immunity (see Figure A-1). Substituting one DEC 8640 on a module does not necessitate changing all DEC 380s, these chips may
reside in any combination. (This is a phase-in and field rework is not intended except for repair
purposes.)

A-1

3.0
|

(HIGH)
2.5

2.0 -1/
s

////////7

(1.3)

/// (1.7)

o///////z//////////////// //

NOT DEFINE

1.0 -

(LOW)

|
1

DEC 380

Figure A-1

]

DEC 8640

Comparison of 8640 vs. 380 Threshold (Worst Case)

- Table A-1

Unibus I.C. Types

Receivers
Type

DECP/N

Function

Note

Input Voltage
Low

380

19-09485
19-11469
19-11113
Not assigned
19-12128
19-09704
19-09486
19-11116

Quad nor
Quad nor
Quad nor
Hex inverter
7 input nor
7 input nor
Quad or
“Hex inverter

1
2
1
3
3
4
1
4

1.3
1.3
Hysteresis
1.3
1.3
1.3
1.3
1.3

19-09705
19-09849

Quad nand
Quad nand

250

19-11579

Quad transceiver

19-11117

Quad transceiver

100

8640
11380
8644
8645

314
384
8837

Drivets
8881
74HO1

Transceivers

8641
8838

High

Leakage

2.5
1.7

160
80

1.7
1.7
2.5
2.5
2.5

160
160

160

Notes

Not allowedin new de31gns
Replaces the DEC 380in Unlbus applications.
Availablein July ‘75.
To be usedin new designs only until pin compatible replacements are available.
- LC.

314
8837

Replacement

8645
8644

A-2

100

n
{

A.2

BUS DRIVERS

The DEC 8881 is the standard Unibus driver. Others which have been used are listed in Table A-1.
Unibus pin assignments are illustrated in Figure A-2.

A.3

GRANT LINE TERMINATION

The terminators on each of the Unibus do not terminate grant lines which are received and repropagated. Grant lines are terminated as shown in Figure A-3 (between devices receiving a grant line). A
recent series of ECOs that includes all devices using grant lines has changed the previous termination
techniques as discussed previously. (A 1802 pull up resistor has been added to the grant receivers of
each device). This significantly reduces reflections and false grants on the bus, i.e., traps to 0, traps to 4
and undefined interrupts.
A.3.1

Rework Procedure

Obtaina supply of 1809 resistors. (These may be ordered under DEC P/N 13-01322).

Using the proper print set for each option, locate the grant receiver input.

If no 180Q pull up resistor is installed from the input of the grant receiver to +5 V, install

.//‘

one (refer to the applicable ECO:s).

'NOTE

Bus switches and repeaters already have these resistors installed.

CAUTION

Some devices receive more than one grant line and
many devices receive both NPG and BGxx signals.
All grant receivers should be terminated in this
manner.

NOTE

- To maintain termination consistancy, a 1802 pull up
could be added at the receiver and a 3902 pull down
could be added at the driver. If a device with the driver pull down were used with a device which did not
have the receiver pull up, the assertion level would not
be high enough to ensure reliable operation.
A.4

BCl11 CABLE FOAM

The BC11A cable (see Figure A-4) consists of two (60 conductor) mylar Flex-print cables used to
connect system units in different mounting cabinets or to connect peripheral devices not located within
the cabinets. The two Flex-print cables are taped together to form a single flat 120 conductor cable. In
system applications, there is little control over how this cable is routed. Impedance of the BC11 cable
can vary widely due to physical routing and has been found to be in the range of 60-80{ in typical
systems. (Design specification is 1209).

ECO No. BC11A-004 corrects this low-impedance problem with the addition of foam between the two
mylar cables. The impedance of the cable is stabilized at 1202 and is not too sensitive to physical
configuration when this foam is installed.

A-3

==b
-t

hmaw-o'__n

|
1 = GND

8 = VCC

I-{D—— 10

314/7314

2
1

8 = GND
16 = VCC

8838/8641

TRANSCEIVER

1 = GND

8 = VCC
380/7380/8640

}8
}6
}3

7 = GND

14 = VCC

8881

74HO1

DRIVER

7 = GND

14 = VCC

CP-2586

Figure A-2

Pin Assignments of Unibus I.C.s

A-4

=‘ <

S- N

2610

: o0

Jav]

Figure A-4

BCl11

=—O

A-5

Cable

(

Foam Installation Procedure

A.4.1

Obtain sufficient foam to do the job. This may be ordered under DEC part number 90-08881 (see
Figure A-5). The length required will be twice the sum of all BC11 cable lengths in the system, plus
twice the length of all parallel cable runs.

fil

= Foam Tape
(Part

Figure A-5

#90-08881)

Foam Tape Installation

Perform the following steps for all BC11 cables in the system:

Remove the tape holding the two mylar Flex-print cables together.

2.
3.

Examine the cables for any nicks, cuts or sharp creases, discard the cable if unserviceable.
Separate the cables and apply the foam tape to both edges for the entire length of the cable.

Retape the two mylar cables together with electrical tape. (Foam is sandwiched between
cables and a single flat cable results. Do not squeeze the cables together at the taped points.)
NOTE
If two BC11 cables run parallel to each other for any
distance, foam should be placed between them. See
Figure A-6 for multiple cable foam installation.

Figure A-6

Multiple Cable Foam Installation
A-6

APPENDIX B

M9202-2 UNIBUS JUMPER INSTALLATION

B.1

GENERAL

Reflections on the Unibus can be caused by termination mismatch, stubs, or loads. (Stubs cannot be
matched, any stub will cause a reflection.) Backplanes have wires attached to the Unibus which act as
stubs. In addition to this, individual modules may have bus lines carried on etch which adds length to
the backplane stub. Individual device options cause reflections on the Unibus which are called signa- tures. These signatures combine to form the composite waveform seen on the bus. (See Figure B-1.)

—
nyy

CP-2611

- Figure B-1

Composite and Signature Waveforms

B-1

A level change, in theory, should be a clean transition.

Devices placed on the bus may contribute signature reflections.
Many devices in close prox1m1ty may contribute to composite reflectlons great enough to cross over
the threshold level of bus receiver.
The M920 Unibusjumper module (double module) connects the Unibus from one system unit device
to the next. Its length is very short electrically. If device options are installed in close proximity to each
other (lumped loads), their signatures may combine to place a large reflection and false information on
the bus.

If these signatures could be separated, they would not present such a problem. The M9202-2 Unibus
Jumper Module is physically compatible with the M920; however, it induces some delay and lessens
the effect of lumped loads. The same signatures shown in Figure B-2 can be separated to reduce the
composite signal. This will prevent composite signal from crossing the bus receiver threshold and thus
from presenting false information due to large reflections.

RECEIVER
THRESHOLD

MULTIPLE REFLECTIONS
SEPARATED IN TIME TO
PREVENT THIER PEAKS

FROM COMBINING

CP-2612

Figure B-2

Separation of Multiple Reflections

This does not altogether eliminate the source of the problem, however, it does offer a reasonable
alternative for reducing the effect of reflections.
B.1.2

Jumper Installation

A first pass approximation is to install one M9292-2 bus jumper between each 4 to 8 unit loads (replace
the existing M920 with a M9202). (Refer to Chapter 2 for detailed configuration rules.)
NOTE
The M9202 is a useful troubleshooting aid and
should be left in the system on a permanent basis if
required. The M9202 will not fit in BA11-Cs or
BA11-Es mounting boxes. In these systems, use
BC11A-2 cables.

B-2

l—-

M920

11/45

MF11LP

DD11

s:::

24K)

BM873

BC11A-10

M930

(10 BUS CABLE)
RK11C

TA11

KW11L
PC11

:
4

DL11

Configuration Using M920

Figure B-3

CP-2613

Using the configuration shown in Figure B-3, the following waveforms (see F iguré B-4) were obtained
at SSYN on the RK11C backplane.

(1 V/em @40 nsec/div)

380 THRESHOLD

(FALSE SSYN)

REAL SSYN

SSYN AS SEEN AT RK11C

SSYN as seen at RK11C with

M920 jumpers replaced by
2’ bus jumpers
CP-2614

Figure B-4 J umpef Threshold Levels

B-3

APPENDIX C

AC AND DC LOAD TABLE

AC & DC LDAD TABLE
o B 40 g W 08 O SN OB ON TN Ul W O U K U o

PEVICE
OPTIONS

LOAD
AC
DC

TDR RESULTS
DRSY
MSYN

§8YN

NOTE §MEASURE DATE
(OR OTHER INFOR,)

w&“-&&&&&bb&&&&&-&‘u&&.&&#*fi&&L*&&fi“%*‘&“%fiufi“&&“&&%&“&“

AAY 1=K

)

4
6

AD}1eK
AR11(M73@9)

BM792

BMET3

CR11l

cD3t
DA} leB

?
9

DCil
0D11«A(OBSOLEYE)

{2
3

DB11=A(LEFY)
OB11=A(RIGHT)

6
)

4,00
5.89

1,91

3,84

l
1

5¢75
5,19

he24
3,38

he33%
3,19

i?
A

12,24
1,94

4,18

DDiieC

3,24

2,63
7

DDi1eP(3L0Y|=4)
.
(SLOYS=9)

4
“

a
@

|
0J11
CLi1=A(M7800)

S
-3

3
i

5,79
1,64

DH1 j»DMy1=-B8
PLileC

OL11eE

OL11eH(MT856)

OMCL Y

2,26
5,16

.20

“

3.2°

1,39
3,42

1,91

B,75

0DijeB

OD11«D(5L0Y1=4)

1,80

2,07

i
!

21
)

6,89
1,76
3,48

2,18

2,75
|

1", 79
2,51
5,38

3,89

3,68

121576

g51Aa76
292375

121575

292375
892275
@9227%

ea1274
81976
1201 T4(NEW

1215876

121576(SLOTl=
2FT=8L0TS)

121576(8L0THe
2FT=8LOTS)

2,96
@,79

5,08
2,49

11,12

PB217%

1,76

@,98

2,712

830375

3,13

1,48

2,47

13,38
|

2,05

6,22

e, 80

Ce37

121874
@3a37%
A38375

121576

238375
181775
124775

0P1l
0011
OR1i1=8

g
8
9

1
1?7
|

0,56
7,27
9,17

4,75
6 h6
8,45

4,16
7,87
7,88

DR} jeK

4,83

2,16

3,48

i
|

2,90
467

A,82
2.96

2,59
6,52

232775

@
a
a
B

1,78
1,82
2.9
2,78

1,75
1,59
1,47
2,29

1,23
1,74
1,34
2.9%

81770
881776
881776
081776

@,54
10,45
3456

121576
1015875
1@1{575

PR11=C(HMT860)

DR1igel

CRijeM
- 0TA3(CPU)

DTA3(SHARED)

PTA6(LUINIBUS &)
(UNIBUS B)
(A IN & $S)
(8 IN & §8)

(SR & A OUT)
(SR & B OUT)

- DUP11
Vil
0X311

KE11=B

3
7

-2
2
3
2

2
3
3
12
6

“

1
1

@
2
31?
4
i
i

4,3%

2,97

3,15

1,69
3,1%

ha93

@,82
3,87

1,06
1,76

1,79
3,.A3
11,63 5,24
5,26
3,82
S

-l

Ha11

2,59

2,73

1,05
2,087

REV,

LOAD IS IN PROCESS)

101675
121775

230775

817706
881776

11745(BUS
(BUS

A,KWl1lal)
B)

(BUS B

(BUS B
#(MINNTYRONICS

PDP 11760

1 MOS)

2 MDS)
CACHE)

PDP 11/6B(BACKPLAME)

POP

11/70(SLOT1=39)

($L0T4A0=44 BACKPLAMNE)S

RK&La

RLY
Rleac(flR E)

RX31

TAlY

RH11
RK31=D(OLD)
RKi1=D(NEW)

RF11

-2 B

3,45

BIO Ul

RH74
RC1!

=i Pub G Pt Pt

2,19

Pt Puis Gub Poud Sub Pui Pob

3.0/

1412

3.83

2.,n2

3,50

10227%

1,13

4,57
3,00

1,56

122975
121576
101675
52776

2&1

50275

@,22

2,05

121576

599

124576

T.47

881976
281976 (LST,)
881976
281976
212376

3,87

2.95

3,77

Lol
B |

121575

211477

3,65

3,89

Celll
1,88

§,70

~
A A

e N 5= U N N = s Bt ) B B Sut s B Dot
DTt e D

DWW
AU

UL UT 62N N A
T D

(SLOT1«39 BACKPLANE) 5

QNI

PDP

PDP 13/35

Ve = P

PC11(NENW)

PDP xx/magn7zes,mvsax)
PDP 11705
POP 11/34(WITH MO93a))

-3

MFiielP(2X16K)

MFileH
MMy jekD
PC11C(OLD)

DA PPt Pt Pt P DL Pt PP Pt N NEC

MFiiel (2X8K)

HF3ilel (3X8K)
MF11ed(2X16K)
MELielUP(IX]6K)

DO DO FUIN om s

1A
1)10CC+D0]

2)10CC(99550@,99581)
3)1PDI(99556)
4)1CALCULATUR(°9319)
MMy §=DP
M$1ieJP
MF11eL(BACKPLANE)
MFilelL (1X8K)

ded

HODULE)
MT&59 (PROGRAM CONSOLE)
MALL
aHOORE SYSYEM DEVICES:

DEEC 0

LPLy
LP2O
LSi1
Lvil
.
M93d}
M?SSBCPAflle

LK1l

e O s

KYiisLA

KYLieLP(M7859)

—_—ry

KWii=P(NEW M7228 REV,FP
cs J)

KWijeP (OLD M7228)

NENC OUIN

KG13

KWyielL (M787)
KN leK

2,517

4,99

UeT2

'u.a3'

.78
3,12

2,33

1,18

@, 74

2,30

2,%6

1,33

a,486

.12

1.16

2,10
3,00
5,50
3,76
2,11

1.029

4,90
Idu
B,67
1,12

7,58
2,39

85175

818576

121975

4,98

fh,un

7.40
8,70
8,00
5,59

6,09
7,40
6,20
440

3,76

g9tavTe
230975
291975

8,00

6,0m

@9197S

1,86

8,46

h,u9

N,79

7,89
9,953

862170

121576

6,93
H,a7

3,58
12,14
11,78

2.7

4,61

5«89

2.56

7.25

B A3

5. 24

1,80

6,13

8,45

4,31

10,63

10,19

2.57

8,50
5,38

3,19

7,109

3,26

0.21

3,22

2,98

2.51

5419

2,33
3,32

2.79

236

0,16

5.12

6,80
9,17

515

3,45
5,20
7.33
5,32

1,01
4,10

6,80

go{97%

120874

121674
1@1@75(DC
CPU)
@70775
211877
211477
(PC LOADSIKW11L,CPU,

ARHTB1SLOT39e2F
TuKN 1L e
2FT=SLOTHRIREY, J}
811477)
- 092375
181375
g9Bs7s
g9esTs

3,90

18,7

6,51
8,27
2,78

5.96

4,97

4,92

4,10

R,627

121576
121576

2,78

121874

6,79

3,09
2,15

C-2

4,97

2,94

LOADSIKW11L,

892575

V360

6,92

5,67

)

.11

@
)

(Mge1)
TMIL

TMALL
TMB11
TR79«F

TCi1

TERMINATOR(M934)

2
a

T.4@

4,79

291975

1.22

6,44

1e2974

4,62

6,05

5,32

6,69

4,68

3,22

2.9

7,50

3,54

2,63

S.11

{ea974

121576

g92275%

121576

‘Q-“CCQQQO‘DD"-flflm’fl.fi‘flfl‘-.-.‘fl-‘----Q--.fl‘----—--.-O-‘-.flflfi-’flfl-utfiqqfl

DATE$P1» 19«77

NOTE§
§, DPTIMIZE NPR DEVICES SEQUENCE t RK{1=D,TM1l,TCI1,
RJSB4,RIPBA, RKO11,RISBZ,RP11C, DMCIL(INB) ,TIVU1G,
RF11,DMC11(56KR),DH11L,

3,
4,

» FOREIGN DEVICES,
1F yOU DOURT SNME OF THE YALUCS IN THE TABLE,

MEANS

DATA

SUSPICINUS

L J

CONTACT CHIN LI (PK3-2/817, OR X5229),

C-3

PLFASE

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APPENDIX D
BUS LOADS

eviH| ovev| —

AST+ @ (V1) 8 —

(Q-096H) Alddns Jamod ZYLH

D-1

$0dY | 92€-v —

0 1e damod aseyd g —| o802 | 2est 0 9 ZEX IEX OF S4 ¥oed %sia y0dY

Maynard, Massachusette

dijgliltjall

DIGITAL EQUIPMENT CORPORATION, Corporate Headquarters: Maynard,

Massachusetts 01754, Telephone: (617) 897-5111
SALES AND SERVICE OFFICES
UNITED STATES—ALABAMA, Huntsville ¢ ARIZONA, Phoenix and Tucson e
CALIFORNIA, El Segundo, Los Angeles, Oakland, Ridgecrest, San Diego, San
Francisco (Mountain View), Santa Ana, Santa Clara, Stanford, Sunnyvale and Woodland
Hills ¢« COLORADO, Englewood ¢ CONNECTICUT, Fairfield and Meriden ¢ DISTRICT

OF COLUMBIA, Washington (Lanham, MD) ¢ FLORIDA, Ft. Lauderdale and Orlando e
GEORGIA, Atlanta ¢« HAWAII, Honolulu ¢ ILLINOIS, Chicago (Rolling Meadows) e
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KINGDOM, Birmingham, Bristol, Edinburgh, Leeds, London, Manchester and Reading
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printed in U.S.A.