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DEC-9A-I3BA-D

November 1967

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Document:	TC-59
Order Number:	DEC-9A-I3BA-D
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Pages:	82
Original Filename:	http://bitsavers.org/pdf/dec/pdp9/DEC-9A-I3BA-D_TC-59_Nov67.pdf

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INSTRUCTION MANUAL

MAGNETIC TAPE CONTROL

TC-59

DIGITAL EQUIPMENT CORPORATION. MAYNARD, MASSACHUSETTS

DEC-9A-I3BA-D

TC-59
MAGNETIC TAPE CONTROL
INSTRUCTION MANUAL
November 1967

CONTENTS

CHAPTER 1
INTRODUCTION AND DESCRIPTION

1.1

Introduction

1-1

1.2

Purpose of Equipment

1-1

1.3

7-Track Tape Format

1-2

1 .3. 1

Load Point and End Point

1-3

1.4

9-Track Tape Format

1-4

1 .4. 1

CRC Character

1-5

1.5

Referenced Documents

1-5

CHAPTER 2
OPERATION AND PROGRAMMING

2. 1

Introduction

2-1

2.2

lOT Instructions

2-3

2.3

Magnetic Tape Functions

2-4

2.3.1

No Operation

2-4

2.3.2

Space

2-4

2.3.3

Read Data

2-4

2.3.4

Write Data

2-5

2.3.5

Write EOF

2-5

2.3.6

Read/Compare

2-5

2.3.7

Rewind

2-5

2.3.8

Write Extended Inter-Record Gap

2-6

2.4

Continued Operation

2-6

2.5

Flags

2-6

2.6

Status Reg ister

2-7

2.6.1

Error Flag (ER)

2-7

2.6.2

Tape Rewinding

2-7

2.6.3

Beg inning of Tape (BOT)

2-7

2.6.4

Illega I Command

2-7

2.6.5

Parity Error

2-8

2.6.6

End-Of-File (EOF)

2-8

iii

CONTENTS (conr)
~ag~

2.6.7

End-Of-Tape (EaT)

2-8

2.6.8

Read/Compare Error

2-8

2.6.9

Record Length Incorrect

2-8

2.6.10

Data Request Late Error

2-8

2.6.11

Bad Tape

2-8

2.6.12

Magnetic Tape Flag (MTF)

2-9

2.7

Magnetic Tape Function Summary

2-9

CHAPTER 3
PRINCIPLES OF OPERATION
3. 1

Introduction

3-1

3.2

System Description

3-1

3.3

NRZ Recording

3-3

3.4

Programming Sequence

3-4

3.5

Inter Re cord Gap De lay

3-5

3.6

WRITE

3-6

3.7

Write Continue

3-8

3.8

Write End-Of-File Mark

3-8

3.9

Read

3-8

3.10

Read/Compare

3-9

3. 11

Dens ity Modes

3-10

3.12

Errors

3-10

3. 12. 1

Data Late Errors

3-10

3.12.2

Parity Error

3-10

3.12.3

Read/Compare Error

3-10

3.12.4

Record Length Incorrect

3-10

3.12.5

Bad Tape Error

3-11

3.13

Illegal Commands

3-11

3.14

Space

3-11

3.15

Data Channel Oper:Jtion

3-12

3.16

Automat i c Priority Interrupt

3-13

CONTENTS (cont)
Pa~

CHAPTER 4
MAINTENANCE
4.1

Maintenance Equipment

4-1

4.2

Module Locations

4-1

4.3

Preventive Ma intenance

4-·2

4.3.1

Power Supply Checks

4-2

4.4

Troubleshooting Procedures

4-2

4.5

Module Utilization

4-3
CHAPTER 5
INSTALLATION

5. 1

PDP-9 to TC-59 Connection

5-1

5.2

TC-59 to TU-20 Connection

5-1

CHAPTER 6
ENGINEERING DRAWINGS

ILLUSTRATIONS
Page
1-1

7-Track Tape Format

1-3

1-2

9-Track Tape Format

1-4

3-1

Simplified System Block Diagram

3-2

Tape Write and Read Signa I Flow

3-4

TABLES
Pag~

2-1

TC-59 Command Register Control Data

2-2

TC-59 Control lOT Instructions

2-3

Status Reg ister

2-7

2-4

Magnetic Tape Function Summary

2-9

4-1

Power Supply Output Checks

4-3

4-2

Module Util ization

4-3

CHAPTER 1
INTRODUCTION AND DESCRIPTION

1 .1

INTRODUCTION
This manual, together with referenced documents, provides operation and ma intenance infor-

mation for the Te-59 Magnetic Tape Control Unit. The level of discussion assumes familiarity with the
PDP-9 Programmed Data Processor, and a working knowledge of DEC logic symbology.
The TC-59 Magnetic Tape Control Unit controls a magnetic tape transport conforming to the
transport bus specification, such as DEC Model TU-20 or TU-79 Tape Transports. The TU-20 operates at
45 in/s with a maximum transfer rate of 36 kc. The TU-79 operates at 75 in/s with a maximum transfer
rate of 60 kc.

Both transports are capable of operating either 7-track or 9-track head configurations.

The basic system consists of a PDP-9 interface cabl ing and an attached tape transport.

Nor-

mally, a 10-ft cable is connected between the PDP-9 bus and the TC-59, and a 10-ft cable between the
TC-59 and the associated magnetic tape transport.
The TC-59 can mount anywhere within a standard 19-in. cabinet and contains three standard
DEC Type 1943 Mounting Panels and one standard 5-1/4 in. indicator panel. The total system requires
four mounting panel locations.
1.2

PURPOSE OF EQUIPMENT
The TC-59 control unit consists of tape control logic which, under the direction of the PDP-9

central processor, controls the operation of up to eight tape transport units. The TC-59 control unit operates under PDP-9 program control to transfer data between core memory and the selected tape transport. To transfer data to or from core memory, the TC-59 tape control util izes the data channel fac i I ity
of the PDP-9i the data channel WC (word count) register specifies the record length (no. of words) and
CA (current address) register specifies the starting core memory address of the data transfer.
The TC-59 functions in either 7-track operation or 800 bpi 9-track operation; either 200,
556, or 800 bpi density modes are selectable in 7-track operation. It can operate in either binary or
BCD parity mode.

For writing on tape, the l8-bit data words are transferred from core memory to the

dota buffer in the tape control logic. The data buffer logic supplies the character to the tape transport
write logic as three 7-bit (6-bit character plus parity bit) characters for 7-track operation (two 9-bit
characters for a 9-track operation).

For reading, the sequence is reversed, information is read from

tape as 7-bit characters and is sent to the data buffer.

When a complete l8-bit word has been assembled

in the data buffer I a data-channel break (word transfer) is initiated to transfer the data buffer word into
core memory.
The operations that can be performed by the tape transport I under the control of the TC-59,
are as follows.
1-1

REV" IND

The transports rewinds th'3 tape to the load point and stops.

WRITE

N words are written on tape as specified by the we reg is'ter. The CA reg ister

specifies the memory block address.
WR ITE EOF
READ

An EOF {end-of-fi Ie} mark character (17 g) is writ1'en on tope.
N words are read from tape as specified by the we register. The eA register

specifies the memory block which is to receive the words.
N words are read from tape as specIfied by the WC register. After

READ/COMPARE

each complete word is read, it is compared to a word in memory {specified by CA} producing
a read-compare error when they don't compare.
SPACE FORWARD

The tape is spaced forward

N records as specified by the we register.

If EOT {end-of-tape} is encountered, the tape stops.
SPACE REVERSE
register.

1.3

The tape is spaced in reverse for N records as specified by the we

If BOT (beginning-of-tape) is encountered, the tape stops.

7-TRACK TAPE FORMAT
The 7-track system uses 1/2 in. tape with seven information channels. The format is shown

in Figure 1-1. The left side of the figure shows the tape in relation to the read and write heads. The
tape moves by the heads vertically, with forward direction down. The tape is composed of a mylar base
coated on one side with an iron oxide compositions The oxide, or dull side of the tape, faces the heads
with the left edge toward the transport drive plate. The recording density is 200 cpi (characters per
inch), 556 cpi, or 800 cpi. The method of recording is non-return-to-zero {NRZ}.
Although the tape has two basic states of remanent magnetization

the remanent magneti c

state of the tape at a given position does not determine the value of t-he bit. A logical 'I is represented
by a change of magnetization in either direction. A logical 0 is represented by a constant state of
magnetization; therefore, writing a series of characters containing aliOs is equivalent to writing a section of blank tape. Each time a character is transferred into the tape transport write buffer, the NRZ
writers produce an equivalent character on the tape. Because of the NRZ method of recording, however, a transfer into the write buffer is not a normal ls transfer; instead, whenever a 1 bit is to be
written in a given tape channe I, the corresponding fl ip-flop is compl,emented to produce a change in
the tape magnetization. When a 0 is to be written, the correspondin!~ bit of the buffer remains in the
initial stage, and there is no change in tape magnetization.
The structure and relative spacing of the individual tape characters are shown in the right
portion of Figure 1-1. Each la-bit computer word is divided into three 6-bit characters. The writers

1-2

OXlDE (DULL) SIDE
OF TAPE FACES
HEADS
WRITE
HEAD

READ
HEAD

TAPE\SKEW

EOR DELAY
4 CHARACTER

...-------J:-~--H-_
I

-----....,

END POINT
END-OF - TAPE
REFLECTiVE STRIP
ON NONOXIDE
(SHINY) SIDE
OF TAPE

111111111
1111111111
1111111111
11111111111
111111111111

I
I

I~!!!

11111111

I
I
I
I

11111111
11111111
11111111
11111111
1111111

III

: I

-1/r- ~\

30"

~ ~
w

: :

L----,
SPACES

111111
11111111:

RECORD GAP

____ _

PARITY CHANNEL

3"-----.j

--3/4"

ONE CHARACTER
SPACE

LOAD POINT
BEGINNING-OF --TAPE
REFLECTIVE STRIP
ON NONoxlDE
(SHINY) SIDE
OF TAPE

EOR MARK
(LONGITUDI NAL
PARITY CHECK
CHARACTER)

TAPE MOTIO_N_ _

Figure 1-1

7-Track Tape Format

contain seven fl ip-flops, however, corresponding to the seven tape channels. The seventh channel is
a lateral parity channel. The parity of the character may be either odd (binary) or even (BCD) as specified by the program. In reading the tape, only 1s are detected. The smallest unit of information that
can be written on the tape is a record. Since each computer word contains three 6-bit characters, a
record contains N x 3 data characters, where N is the number of words that the processor transfers.
After the last data character of the record is written the tape travels sl ightly over four character spaces of blank tape (EOR gap), and then clears the write buffer to produce an end-of-record
character, the EOR mark. The bit configuration of the EOR mark produced by clearing the write buffer
leaves an even number of 1 bits in each of the seven channels of the tape. All bits of the write buffer
start in the 0 state; to end in the 0 state, they must undergo an even number of transitions. For this
reason, the EOR mark is referred to as the longitudinal parity-check character. Besides detecting
changes in magnetization through the read heads, the tape transport also includes a photoelectric system
for sens i ng the beg inn ing and end of the tape.

1 .3. 1

Load Point and End Point
The load and end points of the tape are marked by reflective strips mounted on the side of the

tape away from the head (Figure 1-1). These strips are detected by photo diodes which sense light

1-3

reflected from them.

In writing on a new Iy mounted or rewound tape! a gap of about 3 in. is left from

the load point before writing can begin. When load point is sensed during a fast rewind condition, the
sensing device shuts off the high speed rewind.

Before the tape movement stops, however I the load

point will be passed and the forward tape motion will be enabled to advance the tape back to the loadpoint strip.

1 .4

9-TRAC K TAPE FORMAT
The 9-track tape format shown in Figure 1-2 is similar to T-track format except that 9-track

format has 9 tracks, the addition of the CRC (cye! ic redundancy check) character f and operation is only
in the 800 bpi mode.

r rLPCC

--- ..

CRC

TRACKS

-------

----

1 - --,

I I I I

--1
Figure 1-2

I I I I

, I I I

I I I I

I--

BOT

_--1

4 CHARACTER SPACES

9-Track Tape Format

The tape control assembles two 8-bit characters per 18-bit word for recording on tape. Each
8-bit character is recorded with a parity bit which can be either odd or even. The first" character
recorded contains the most-significant bits of the PDP-9 l8-bit word.

Since 2 characters represent 16

bits of information, the first two bits are not recorded or read back frctm the tape transport as data.
Therefore, the first chara =ter represents bits 2 through 9. The second character represents bits 10
through 17. While recording, the parity of the first character is stored in bit 0, and the parity bit of
the second character is stored in bit 1. This a Ilows the program to perform error detection.

1-4

1 .4. 1

CRC Character

To write the CRC character, the TC-59 control incorporates a 9-position register C through
1
C with the following track assignments:
9
Register Position

Tra ck Number

To derive the CRC character, all data characters are exclusive ORed into the CRC register.

Between

character transfers, the CRC is shifted one position, C to C , etc., and C9 to C1. If shifting causes
1
2
a 1 in Cl, then the bits shifted into C4, C5, C6, and C7 are inverted. After the last data character
has been added (exclusive ORed), the CRC register is again shifted and if C1 is 1 the C4, C5, C6, and
C7 are inverted.
To write the CRC character on tape, a II bit positions except C4 and C6 are inverted. The
parity of the CRC character will be odd if the number of data characters within the block is even, and
even if the number of data characters within the block is odd. The CRC character may contain all

o bits, in that the case the number of data characters was odd.
The LPCC character for 9-track format is the same as for 7-track format.

1 .5

REFERENCED DOCUMENTS
The following documents contain information related to the TC-59 Magnetic Tape Control

Unit.
F-97

PDP-9 Maintenance Manual

F-95

PDP-9 User Handbook

DEC-00-I4AA-D

TU-20 Instruction Manual

C-105

DEC Logic Handbook

1-5

CHAPTER 2
OPERATION AND PROGRAMMING

2.1

INTRODUCTION
The TC-59 controls the operation of a maximum of eight magnetic tape transports. The

TC-59 uses the PDP-9 data channel facility to transfer data between system core memory and magnetic
tape. The data transfers are controlled by the resident-memory word counter (WC) and current address
(CA) registers associated with the assigned data channel. The TC-59 is assigned memory location 328
and 33 for WC and CA, respectively. The CA is incremented before each data transfer; therefore, the
8
initial contents should be set to the desired initial address minus one. The WC is also incremented
before each transfer and must be set to the 2s complement of the desired number of data transfers.

this way, the word transfer which causes the word count overflow (WC becomes 0) is the last transfer
to take place.
To control operation, the TC-59 maintains a command register (Table 2-1); the program
specifies the desired operation by transferring control data (un it selection, density, mode, etc.) from
the AC to the command register using lOT instructions (Table 2-2). Tape status information (EOT, BOT,
error flags) can be read into the AC from the control unit by lOTs. Similarly, the control unit command
reg ister can be read into the AC.
During normal data reading, the control assembles l8-bit computer length words from successive frames read from the information channels of the tape. During normal data writing, the control
disassembles l8-bit words and distributes the bits so that they are recorded on successive frames of the
information channels. The control provides for selection of four recording densities: 200, 556, 800,
and 800/9-channe I.
Although any number of tapes may be simultaneously rewinding, data transfer may take place
to or from only one transport at any given time; data transfer includes these functions: read, write,
write EOF (end-of-file), read/compare and space. When any of these functions are in process, the tape
control is in the not ready condition. A transport is said to be not ready when tape is in motion, when
transport power is off, or when it is off-line.
Data transmission may take place in either odd-binary or even-BCD parity mode. When
reading a record with an odd number of characters, the final characters come into memory left justified.
Ten bits in the magnetic tape status register retain error and tape status information. Some
error types are combines, such as lateral and longitudinal parity errors (parity checks occur after both
reading and writing of data) or have a combined meaning such as illegal, for maximal use of the available bits.

2-1

Table 2--1

CORE
DUMP

UNIT SELECT ION
(0-7)
0

TC-59 Command Reg ister Contro I Data

DENSITY***

COMMAND**
5*

INTERRUPT
ENABLE/DISABLE

PARITY
O=EVEN
4=ODD

*Bit 5 specifies write extended inter-record gap whereby 3-inches elf blank tape is erased {or passed
over} before recording occurs.
**Bits 6, 7 and 8 decoding is as follows:
BITS
COMMAND

NO OP

REWIND

READ

READ/COMPARE

WRITE

WRITE EOF

SPACE FORWARD

SPACE REVERSE

***Bits 10 and 11 decoding is as follows:
DENSITY

BITS
10

200 BPI

556 BPI

800 BPI

800 BPI/9-TRACK

2-2

2.2

lOT INSTRUCTIONS
Table 2-2 shows the lOT instructions fOf' the Te-59 .

Table 2-2
Mnemonic

TC-59 Control lOT Instructions
Description

Octal Code

~"----------+-----------~--------'----------------------------------------~

MTSF

707341

Skip on error flag or magnetic tape flag. The states of the
error flag (EF) and the magnetic tape flag (MTF) are sampled.
If either or both are set to 1, the content of the PC is incremented by one to skip the next sequential instruction.

MTCR

707321

Skip on tape control ready (TCR). If the tape control is ready
to receive a command, the PC is incremented by one to skip
the next sequential instruction.

MTTR

707301

Skip on tape transport ready (TUR). The next sequential
instruction is skipped if the tape transport is ready.

MTAF

707322

Clear the status and command registers, and the EF and MTF,
if TCR. If not, TCR clears MTF, EF flags only.

MTCM

707324

Inclusively OR the contents of the AC bits 0 through 5,
9 through 11 into the command register; JAM transfer bits
6, 7, 8 (command function).

MTLC

707326

Load the contents of AC bits 0 through 11 into the command
register. (MTLC is the summation of MTAF and MTCM.)

707342

MTRS

707352

707302

Inclusively OR the contents of the status register into bits

o through 11 of the AC.

Read the contents of the status register into bits 0 through 11
of the AC.
Inclusively OR the contents of the command register into bits

o through 11 of the AC.
MTRC

707312

Read the contents of the command register into bits 0 through
11 of the AC.

MTGO

707304

Set "gO" bit to execute command in the command register,
if command is legal.

L -_ _ _ _ _ _ _ _- 4____________~________"____~~_________________________________ _

The magnetic-tape status register reflects the state of the currently selected tape unit.
Therefore, other units which may be rewinding, for example, will not interrupt when done.

2-3

2.3

MAGNETIC TAPE FUNCTIONS
The magnetic tape functions are specified by bits 6, 7, and 8 of the command register. When

any of the tape functions has completed its data operation (after the end-of-record character passes the
read head) the MTF (magnetic tape flag) is set, an interrupt occurs (if enabled), and errors are checked.
The following Iist defines the tape function.

2.3.1

,No Operation
A NO OP command defines no function in the command n~gister. A MTGO instruction with

NOP specified by the command register causes an illegal error.

2.3.2
There are two commands for spacing records -

space forw,crd and space reverse. The 2s

complement of the number of records to be spaced is loaded into the 'WC register. The CA register
need not be set. The space function terminates when a WC overflow occurs, or EOF (end-of-file) or
EOT (end-of-tape), whichever occurs first; the M TF (job done) flag is set and, if enabled, an interrupt
occurs. When issuing a space command, both the density and parity bits must be set to the density and
parity in which the records were originally written. For IBM compatiibility, BOT (load point or beginning-of-tape) detection during a backspace terminates the function with the BOT bit set. If a reverse
command is given when a transport is at BOT, the command is ignored, the illegal error and BOT bits
are set, and an interrupt (if enabled) occurs.

2.3.3

Read Data
Records may be read into memory on Iy in the forward mode~. Both CA and WC must be set;

CA to the initial core address -1; WC to the 2s complement of the number of words to be read. Both
density and parity bits must be set.
If we is set to less than the actual record length, onl y we words are transferred into memory.
If we is greater than or equal to the actual record length, the entire record is read into memory.

In any

case, both parity checks are performed. The MTF is set I and an interrupt (if enabled) occurs when the
LPec mark passes the read head. If either lateral or longitudinal parity errors or bad tape have been
detected, or if an incorrect record-length error occurs (We not equal to the number of words in the
record), the appropriate status bits are set; but the interrupt occurs only when the MTF is set.
To continue reading without tape stopping, issue MTAF (clear MTF) and then issue MTGO.
If the MTGO is not given before the shut down delay terminates, the transport will stop.

2-4

2.3.4

Write Data
Data may be written on magneti c tape in the forward direction only. For the write data

function, CA, we, and density and parity must be set. The write function is controlled by the we,
such that when WC overflows, data transfer stops, and the EOR {end-of-record} character and IRG
(inter-record = gap) are written. The MTF is set after the EOR has passed by the read head. To con'tinue writing, MTAF and MTGO must be issued before the shut down delay terminates.

If any errors

occur, the EF {error flag} wi II be set when the M TF is set.

2.3.5

Write EOF

The write EOF command transfers a single file-mark character (17 ) to magnetic tape plus
8
the EOR character. CA and WC are ignored for write EOF. The density bits must be set and the
command register parity bit should be set to even (BCD).

If it is set to odd, the control will automatic-

ally change it to even. When the EOF marker is written, the M TF is set and an interrupt {if enabled}
occurs. The tape transport stops, and the EOF status bit is set confirming the writing_

If odd parity is

required after write EOF, it must be specifi cally requested through the MTLC command.

2.3.6

Read/Compare
The read/compare function compares tape data with core memory data.

It can be useful for

searching and positioning a magnetic tape to a specific record, such as a label or leader, whose content
is known in core memory or to check a record just written. Read/compare occurs in the forward direction; CA and WC must be set. For each word read from tape, it is compared to the memory location
specified by CA.

If there is a comparison failure, CA incrementation stops and the read/compare error

bit is set in the status register. Tape motion continues to the end of the record when the MTF is set and
interrupt (if enabled) occurs.

If there has been a read/compare error f examination of the CA revea Is

the word that fa i led to compare.

2.3.7

Rewind
The high-speed rewind command does not require setting of the CA or WC.

Density and

parity settings are also ignored. The rewind command rewinds the tape to loadpoint (BOT) and stops.
Another unit may be selected after the command is issued and the rewind is in process. MTF is set and
an interrupt occurs (if the unit is selected) when the unit is ready to accept a new command. The
selected units status can be read to determine or verify that rewind is in progress.

2-5

2.3.8

Write Extended Inter-Record G5:!E.
This feature, which occurs when bit 5 of the command register is set, permits a 3-in. inter-

record gap to be produced before a record is written. Using this feature, areas of bad tape can be
expediently passed over. Bit 5 is automatically cleared when writing begins.

2.4

CONTINUED OPERATION
The presence of the MTF flag signifies the end of the specified operation. To continue oper-

ation in the same mode, the MTAF and MTGO instructions should be executed before the inter-record
gap delay terminates operation. Since the tape control status will not be ready, MTAF does not clear
the command register; therefore, operation continues in the same mode. The MTGO instruction prevents
tape control status from reverting to not ready, therefore, tape motion continues.

If the operation is a

data transfer function, the WC and CA should be reinitialized. Operation continues until the new set
of parameters (WC register) terminate operation by setting the MTF fklg.

If it is desired to continue

operation, the MTAF and MTGO instruction must be issued again.
To change modes of operation, in either the same or reverse direction, the MTLC and MTGO
instructions should be issued.

If a change in direction is specified, the transport wi II stop, pause, and

automatically start up again.
For the write function, no change in direction can be effected; the only mode change that
can be performed is to a write EOF.

2.5

FLAGS
There are four flags that can be sensed by the I/O ship foci Iity. They are the job done (MTF),

error (ER), tape control ready (GO), and tape transport ready (TUR). The MTF and ER are sensed by the
same lOT (instruction).

If the interrupt is enabled, the MTF and ER flags generate an interrupt.

The MTF flag and the ER flag (if an error occurs) are set at the completion of the specified
function. An exception, however, is when an illegal command occurs; it sets the ER flag as soon as the
illegal command is detected. The ER is set by an illegal command or any of the following events:
BAD TAPE ERROR
BOT (Beginning of Tape)
DA TA LATE ERROR
PARITY ERROR
EOF (end-of-file)
EOT (end-of-tape)
READ COMPARE ERROR
RECORD LENGTH INCORRECT

2-6

If an error occurs as sensed via the ER, the status register can be examined to determine the
exact cause of the ER flag.

2.6

STATUS REGISTER
The TC-59 status register may be examined by issuing the MTRS instruction which reads the

content of status register bits 0 through 11 into bits 0 through 11, respectively, of the AC. The status
register format is as shown in Table 2-3; each bit is defined as follows:
Table 2-3

Status Register

Bit

Function (when set)

Bit

Function (when set)

Error flag (EF)

Read/compare error

Tape rewinding

Beginning of tape (BOT)

Record length incorrect
WC = 0 (long)
WC f 0 (short)

Illega I command

Data request late

Parity error (Lateral or
Longitudinal)

Bad tape

End of fi Ie (EOF)

End of tape (EaT)

Magnetic tape flag (MTF)
or job done

Error Flag (ER)
The error flag was defined in Section 2.5.

2.6.2

Tape Rewinding
When a rewind command is issued to a tape unit and the function is underway, the tape

rewinding bit is set by the control. This status is a transport status and any selected transport which is
in a high speed rewind wi II display this bit.

2.6.3

Beginning of Tape (BOT)
The BOT bit is set when BOT reflective strip is detected on the selected tape transport.

2.6.4

Illegal Command
The illegal command bit is set when the MTLC or MTCM is issued to load the command

register and the tape control is not ready and the MTF is not set. The illegal command bit is also set by
the MTGO instruction when any of the following events occur.

2-7

a. 9-track operation spec ified with a density other than 800 bpi.
b. The write lockout bit from the selected tape transport is set and a write EOF specified.
c. The se lected tape transport not ready and the tape contro I is ready.
d. A NOP Command is selected.
e. A reverse direction and BOT status.
2.6.5

Parity Error
The parity bit is set by either a longitudinal or lateral parity error.

2.6.6

End-Of-Fi Ie (EOF)
The end-of-fi Ie bit is set when the EOF mark is detected during space I read, read/compare,

or write EOF operation.
2.6.7

End-Of-Tape (EOT)
EOT detection occurs during any forward command when the EOT reflective strip is sensed.

\A/hen EOT is sensed, the EOT bit is set; but the function continues to completion at which time the
MTF is set (and EF is set).
2.6.8

Read/Compare Error
This bit is set by a read/compare error (defined in Section 2.3.6).

2.6.9

Record Length Incorrect
During read or read/compare, this bit is set when the number of words read does not agree

with the initial content of WC. If the record read was longer than that specified, then WC is 0; if
shorter WC "I O.
2.6.10

Data Request Late Error
The error occurs during a tape function that requires a memory access. If the dala flag ini-

tiates a memory access, the data must be transmitted before the next read or write pulse; if it does not,
this error cit is set. In addition to setting the error flag, this error forces a WC overflow within the
tape control to terminate the present operation and prevent any further data transmission.
2.6. 11

Bad Tape
Bad tape error indicates detection of a bad spot on tape. !Bad tape is defined as three or

more consecutive characters missing followed by data within the period defined by the shutdown delay.
The error bi t is set by the tape control when this occurs. MTF and inl-errupt do not occur until the endof-record in which the error was detected.

2-8

:2.6.12

Magnetic Tape Flag (MTF)
The MTF for job done flag was described in paragraph 2.5.

2.7

MAGNETIC TAPE FUNCTION SUMMARY
Table 2-4 provides a summary of the tape functions. The legend below is used in conjunction

with Table 2-4.

LEGEND:

CA
WC
F
R
DS
PR
EN

= Current Address Reg ister = 32
= Word Count Reg ister = 33
Forward
Reverse
Density Setting
Parity Setting
Enable Interrupt
Table 2-4

Function

Magnetic Tape Function Summary
Characteristi cs

Status or Error Types

NO-OP

CA:
WC:
DS:
PR:
EN:

Ignored
Ignored
Ignored
Ignored
Ignored

Illegal
BOT
Tape Rewinding

SPACE FORWARD

CA:
WC:

Ignored
2s complement of number
of records to skip
Must be set
Must be set
Must be set

Illegal
EOF

DS:
PR:
EN:
SPACE REVERSE

Same as Spa ce Forward

READ DATA

CA:
WC:

DS:
PR:
EN:

Core Address - 1
25 complement of number
of words to be transferred
Must be set
Must be set
Must be set

2-9

Parity
Bad Tape
MTF
BOT, EOT
Illegal
EOF
Parity
Bad Tape
BOT
MTF
Illegal
EOF

Parity
Bad Tape
MTF
EOT
Request Late
Record Length Incorrect

Table 2-4

Magnetic Tape Function Summary (cont)

I----·----.....--------·-'-·--·---·-~-,--·--,---------·----·-

Function

Characteristics

WRITE DATA
Same as READ DATA

WRITE EOF

CA:
WC:
DS:
PR:
EN:

Ignored
Ignored
Must be set
Must be set
Must be set

READ/COMPARE

Same as READ DATA

REWIND

CA:
WC:
DS:
PR:
EN:

Ignored
Ignored
Ignored
Ignored
Must be set

2-10

Status or Error Types
Illegal
EOT
Parity
MTF
Bad Tape
Data Request Late
Same as WRITE DATA
Except EOF

Illegal
EOF
Read/Compare Error
Bad Tape
MTF
EOT
Data Late
Record Length Incorrect
III ega I
Tape Rewinding
MTF
BOT

CHAPTER 3
PRINCIPLES OF OPERATION

3.1

INTRODUCTION
This chapter describes system and detailed logic for each of the functions of the TC-59 Tape

Control Unit. The logic drawings in Chapter 6 are referenced in the text for the convenience of the
reader.

3.2

SYSTEM DESCRIPTION
A simplified overall block diagram of the TC-59 Magnetic Tape Control is presented in

Figure 3-1. Assuming a write operation, the programming first sets up CA (current address) and WC
(word count) registers in the data channel of the PDP-9 processor; the CA specifies the core memory
address from wh i ch to obta in data to be written; the WC specifies the number of words to be written on
tape. The program then loads the command register from the AC with appropriate commands (write,
density mode, parity, etc.) and issues the M TGO instruction which initiates operation. The appropriate
motion commands are transferred to the tape transport se lected. A short delay is implemented to provide
the tape inter-record gap. During this delay, the data flag is set to initiate a word transfer from core
memory to the data buffer via the PDP-9 data channel.
After the inter-record gap delay and data buffer loading, the write operation begins.
Assuming 7-track operation, the data buffer 18-bit word must be divided into three 6-bit characters for
writing on tape. The character counter sequences the 6-bit character from the data buffer; as a 6-bit
character is written from the high-order bits of the data buffer, the character counter is incremented to
sequence the next low-order 6-bit character. After the three 6-bit characters from the data buffer are
written, the DATA FLAG is set to initiate another word transfer to the data buffer via the data channel.
Operation continues in this manner until the WC register is reduced to zero, at which time
the tape control is notified. The LPCC character is written and write operation terminates. The tape
continues in the forward motion until the read circuits detect the end-of-record passing under the read
head. Tape motion ceases, the dece leration de lay is in itiated (time a Ilotted for tape to stop), and the
job done (MTF) flag is set.
For the read operation, the initial programming sequence is similar to write. As 6-bit characters are read from tape, they are sequenced into the data buffer by the character counter. When the
data buffer is full, the DATA FLAG initiates a data channel transfer of the data buffer word into core
memory. Operation continues unti I the read circu its detect the end-of-record.
As shown in Figure 3-1, the command reg ister and tape control status can be transferred to
the PDP-9 AC by using the appropriate lOT instructions. Moreover the job done flag and the error
I

3-1

TC 59

TAPE CONTROL

TAPE TRANSPORT

READ BUFFER

_1-1
I

PDP - 9

DATA

BUFFER

WRITE BUFFER

L-.-.----J

CHARACTER
COUNTER

UNIT
SELECTION
DECODER

UNIT SELECTION
(3 SIGNALS)

PARITY

_4_-<>

CORE DUMP
WRITE EXTENDED GAP

TAPE
COMMAND
REGISTER

(12)

NO OF: REWING
READ,READ/COMPARE
WRITE, WRITE EOf,
SPACE FORWARD
SPACE REVERSE
9

',~ ~
( 12)

ENABLE
INTERRUPT

OECOO£O

TAPE FUNCTION COMMAND

O'NSITY

READ
COMMAND
REGISTER

TRANSPORT STATUS:
JOB DONE OR ERROR FLAG

JOB DONE, TAPE UNIT
READ"!' TAPE CONTROL
READY, OR ERROR FLAG

ENABLE
INTERRUPT

K>+---------------------------~

~
_

___
D_A_T_A__
CHANNEL

~L.~I----~D~A~T-~A~R~E~O~U~E~S-T--------~~D_A_T_A
C_H_A_N_N_E_L~
f'
_ ~~~:~flD
__

DATA FLAG

rop
GENERATOR
II
MEMORY
BUFFER

ciL____SELECTOR
D_E_V_lc_E____~L.. IOPPULSES
.______________
-c{
!~

Figure 3-1

Simpl ified System Block Diagram

3--2

TAPE UNIT READY
BEGINNING OF TAPE (BOT)
END OF TAPE (EOT)
WRITE LOCKOUT (WLl
TAPE REWINDING

flag can be enabled to generate a computer interrupt. Through the I/O skip foci Iity, the processor can
examine the job done (MTF), tape unit ready (TUR), tape control ready (GO), or the error (ER) flag.

3.3

NRZ RECORDI NG
The actual technique of recording on magnetic tape is called the non-return-to-zero (NRZ)

method.

In this method, a reversal of the direction of magnetization in a channel represents a 1 bit, a

lack of reversa I represents a 0 bit. Writing is achieved by using a fl ip-flop to control the direction of
magnetizing current in each channel write head; the group of flip-flops is called the write buffer.

applying the ls lines to the complement inputs of the write buffer, each channel reverses its flux only
when a 1 bit is to be written for a character. Further, the write buffer accumulates the LPCC (Iongitudina I parity check character) to be written as an EOR character. When the write buffer is reset at
EOR time, the LPCC character is written automatically because of the nature of NRZ recording.
The NRZ recording method provides self-checking during reading since a transition (or flux
reversa I) in any channel, signifying a 1 bit for that character in that channe I, is used to strobe or sense
all seven channels for that character.

Ideally, all transitions for a single character would be sensed

simultaneously by the 7-channel read head.

In fact, tape skew makes these transitions (if more than one

in a single character) non-simultaneous on reading. There may be a difference, however, in alignment
of the read head with respect to the write head recording the tape (static skew). There are apt to be
changes that vary during tape travel (dynamic skew) in tape alignment to the read head from its alignment during writing. To accommodate these timing variations between channels due to skewing, the
first detected transition for a character initiates a delay before the character is strobed. This delay is
selected to accept the maximum skewing produced at the linear tape transport speed with the designated
tape density.
A simpl ified block diagram of the tape system write and read paths for a single channel is
presented in Figure 3-2. The write path (WP) is shown at the top of the figure. The WRITE fl ip-flop in
the write amplifier is complemented at each WP pulse, if the data buffer for that particular character
contains a 1. When gated by a write-enable signa I, the write amplifier drives one or the other of the
two opposing directions at the write head.

If the WRITE ENABLE level is not present, no current flows

through either coil. Whenever a 1 is to be written on a tape, the WRITE flip-flop is complemented by
the WP pulse. The transition of the WRITE flip-flop terminates the current through one coil and starts
it in the other direction, changing the direction of the tape magnetization, and thus writing a 1 on tape.
As long as the WRITE flip-flop remains in the same state, the current flows through the same coil, and Os
are written on the tape. The tape is then magnetized in the same direction over a series of character
spaces.

3-3

The read path is shown at the bottom of Figure 3-2. The tope reaches the read heads shortly
after transversing the write head. As long as the direction of tape magnetization remains constant, no
current flows through the read head coil.

Each change in the directicm of tape magnetization induces

a current in the read head. The read current produced by two consecutive tape 1s is shown in the waveform near the read head. These signals are applied to a differential read amplifier to provide amplification for different signals, but only fractional amplification for common mode signals. The output of the
read amplifier is then sent through a slicing rectifier. The rectifier output pulse is of the same polarity
for an input pulse of either polarity from a read ampl ifier.

No sl ice ()utput is generated, however,

un less the input exceeds a designated specia I leve I. A low-Ieve I noise input cannot generate an output
pulse.

Next, the slicing rectifier output is applied to a peak detector.

The peak detector produces a

logic pulse output at the peak of the input pulse.

0
I

TAPE

I
TWO STATES OF
MAGNETIZATION

o
NRZ
WRITE
AMPLIFIER

WRITE
ENABLE

o
WRITE HIEAD
WRITE PATH
PEAK
DETECTOR

SLICING
RECTIFIER

lJV
DB

READ
ENABLE

Figure 3-2

3.4

~DIFFERENTIAL
AMPLIFIER

Tape Write and Read Signal Flow

PROGRAMMING SEQUENCE
The following paragraphs, which contain detailed discussion of logic circuits, must assume

that there is some program control. Therefore, the following programming sequence is shown to provide
this control:

3-4

LAC TPFN

/LOAD AC WITH TAPE FUNCTIONS
;TO BE TRANSMITTED TO TAPE
/CONTROL COMMAND REGISTER

MTCR

;TAPE CONTROL READY

JMP . -1

/WAIT

MTLC

/AC TO COMMAND REGISTER

MTRR

;TAPE TRANSPORT READY

JMP XXX
/SET GO FLIP-FLOP

MTGO

The first instruction loads the contents of symbol i c location TPF N into the AC.

Location

TPFN should be appropriately coded to the desired tape functions which are to be transmitted to the
tape control command reg ister. M TCR checks to see if tape control is ready.

If ready, the program

skips to the MTLC instruction. The MTLC instruction generates two lOT pulses - MTAF and LCM (refer
to drawing TC59-0-3).
Since GO (tape control ready) is reset at this time, the first pulse, MTAF, generates CLEAR
ALL (drawing TC50-0-3 Sh 2) which clears all flags, the command register, and normalizes key flipflops.

The LCM pulse then strobes the AC content into the command register (CMO-CM 11 on drawing

TC50-0-2 Sh 1).

The command reg ister now specifies the desired tape functions - parity, density,

tape transport se lection, etc. The tape transport is now se lected and the next instruction MTTR examines tape transport status.

If not ready, the next instruction can be a wait instruction (JMP . -1) to

loop unti I tape transport ready or it can be a jump to some routine to se lect another transport or determine why the presently selected transport is not ready.
If tape transport is ready, the program skips to the MTGO instruction.

Before MTGO is

executed, the tape control will have determined whether the command was legal (see drawing
TC50-0-2 Sh 2).

If legal, the GO flip-flop (drawing TC50-0-2 Sh 1) is enabled so that the MTGO

instruction can set the GO flip-flop.

3.5

INTER RECORD GAP DELAY
According to tape format, between each record there is an inter-record gap. Assuming that

the tape is in a stopped position, before reading or writing can occur, the tape must attain operating
speed within the inter-record gap. To provide the inter-record gap, the tape control timing circuits
incorporate a timing delay which is explained as follows.
The next sequential instruction MTGO (from above programming sequence) sets the GO fl ipflop (drawing TC50-0-2 Sh 2).

The GO signal then performs the following functions.

3-5

Sets the ALPHA (acceleration delay) flip-flop (TC50··0-4 Sh 1).

b. Generates the SET TAPE FUNCTION pulse (TC50-0-2 Sh 1) which turns the transport
status off the bus and sends to the transport, the command direction, forward reverse, rewind, rewindunload, and write. The transport that receives the command sets the function into the tape transport
reg ister.
c.

Generates the MOVE signal to move the tape in the specified direction.

d. Enables CM4 to revise the 9-track status to 7-track status. CM4 is the core dump bit
and causes a 9-track transport to appear as a 7-track system.
The ALPHA flip-flop being set generates ENABLE MUC (drawing TC50-0-4 Sh 1) which enables the motion-up counter (MUC on TC50-0-1). For the write command, the ALPHA signal initiates
the data break cycle to transmit the first word to be recorded to the elata buffer. ENABLE MUC now generates MUC pulses at the 800 bpi clock frequency of the selected tape transport. The MUC bits are
decoded so that the thirtieth MUC pulse sets the DELAY SYNC flip-flop (DELAY TRANSFERRED will be

o at this time) . DELAY SYNC synchronizes the motion transfer seque'nce to enable the motion-delay
characteristi cs from the se lected tape transport to appear on the read buffer lines. The octa I number f
representing motion delay characteristics, represents the start-stop characteristics and operating speed
of the attached tape transport. The next MUC pulse generates the STROBE DELAY pulse which strobes
the content of the read buffer lines into the T-register (TC50-0-4 Sh 1);

the T-register is the timing

reg ister that provides the necessary acce leration or deceleration de lay.

STROBE DELAY then sets the

DELAY TRANSFERRED flip-flop {indicating transfer complete} and resets the DELAY SYNC flip-flop.
The next MUC pulse generates a DOWN COUNT pulse and begins to count down the T-register. The
MUC pulses continue producing DOWN COUNT pulses on every thirty-second MUC pulse. Since the
DELAYED TRANSFERRED flip-flop is set thereafter, the thirtieth and thirty-first pulse will not reinitialize the T-register. When the T-register has counted down to a one-count, the next DOWN COUNT
pulse strobes the T-register to 0 and produces the JRD OVER (inter-record delay over) pulse. The JRD
OVER pu Ise clears the cC and DE - c!'fl ip-flops, thus ending the acce 14~ration or dece leration delay.

should be noted that the delay sequence just described is used for deceleration of the tape following a
tape spacing function as well as the acceleration of the tape before a tape spacing function.
The IRD OVER pulse, enabled by the ALPHA signal, generates the BEGIN OPERATION
pulse (TC50-0-4 Sh 2) which initiates the write and write end-of-file' operations.

If the rewind com-

mand is selected, the BEGIN OPERATION pulse resets the GO flip-flop which frees the tape control
for a new command to a different tape transport while the previously selected tape transport rewinds.

3.6

WRITE
The write operation is initiated by the BEGI N OPERATION pulse which sets the WRITE

ENABLE flip-flop (TC50-0-4 Sh 2).

The WRITE ENABLE signal then enables the CLOCK pulses

3-6

(TC50-0-2 Sh 2) to produce WP (WRITE pulses). The WRITE pulses complement the character count
circuits (CCO and CCl on TC59-0-2 Sh 1) in order to disassemble the l8-bit word in the data buffer
into the appropriate 6-bit (7-track operation) or 8-bit (9-track operation) characters that are to be
recorded.

In 7-track operation there are three characters per word.

In 9-track operation, there are

two characters per word.
For 7-track operation, the character count circuits sequentially generate 1ST CHAR 7
CHANNEL, 2ND CHAR 7 CHANNEL, and 3RD CHAR 7 CHANNEL signals (TC59-0-2 Sh 1) which
sequentially disassemble the 18-bit data buffer word into 6-bit characters and apply them to the bus of
the tape transport.

In a similar manner, the 9-track decoding signals are formed.

Drawing TC50-0-1

shows the decoding of the 18-bit data buffer word for both 7-track and 9-track operation.
The WRITE pulse also produces RECORD DATA pulses (TC50-0-4 Sh 2) which are sent to the
tape transport to record the characters on the tape. For 9-track operation the WRITE pulse exclusive
ORs the characters into the CRC register (TC50-0-3 Sh 1), one character at a time. The CRC register
then performs the necessary manipulation of the data to conform to 9-track format.

The characters are

also decoded in the write parity circuit (TC50-0-3 Sh 2) and the parity bit pertaining to that character
is sent to the tape transport to be recorded.
When a complete word has been written on, the DATA FLAG flip-flop is set (if the word
count overflow WCO is in the 1 state). The DATA FLAG initiates a data break cycle to transfer a new
word into the data buffer. The DATA FLAG fl ip-flop is set in the following manner. The 2ND CHAR 9
CHANNEL or 3RD CHAR 7 CHANNEL (TC59-0-2 Sh 1) generates ENABLE DATA FLAG which in turn
permits the WP to generate the WRIT ING SET DF pulse (TC59-0-2 Sh 2). This pulse generates the
+l~DF pulse (TC50-0-2 Sh 2) which sets the DATA FLAG flip-flop (TC50-0-2 Sh 1).

The subsequent

data channel discussion describes in detail the data channel transfer.
Operation continues until the desired number of words are transferred as indicated by the
word-count overflow (I/O OFLO) pulse from the processor. The I/O OFLO pulse resets the WCO fl ipflop (TC59-0-2 Sh 2); when the last character of the last word has been written WCO (0) generates
LAST WORD (TC59-0-2 Sh 1). LAST WORD enables the WP to reset the WRITE ENABLE flip-flop which
in turn sets the WRITE EOR flip-flop (TC50-0-4 Sh 2). Since we are at the end of record, a 4-character
space must be left on tape and then the LPCC character must be written. This is accompl ished as follows.
The WR ITE EOR (1) signal enables CLOCK pulses to count up the EOR 1 and EOR2 counter
(TC50-0-4 Sh 2) to produce the required 4-character space signified by the 4 CHAR pulse. For the
7-track system, the 4 CHAR puise generates the WRITE LPCC pulse (TC50-0-4 Sh 1) which is sent to the
tape transport to write the long itudina I parity=check character.
For a 9-track system, the CRC character is written follow ing the first 4-character space. The
EOR 1 and EOR2 counter recycles for second 4-character space count and then the LPCC is written.

3-7

Tape motion continues in the forward motion until the read circuits detect the end-of-record
passing under the read head in the tape transport. When the read circuits detect the end of record the
RECORD OVER pulse is generated which initiates the deceleration delay. At the start of the deceleration
delay, STROBE delay ANDed with STOP sets the MTF (job done) flip··flop.

If the interrupt is enabled,

MTF interrupts the main program to signify that the record has been wlritten. Subsequently at the end
of the deceleration delay, the IRD OVER pulse is produced and is enabled by STOP (DE- (£ (1) and NOT
SPACING) to produce the CLEAR GO pulse (TC50-0-4 Sh 1). The CLEAR GO pulse resets the GO flipflop which terminates the MOVE signal and stops the tape thus complE~ting the write operation.

3.7

WRITE CONTINUE
To continue writing record, the MTAF and MTGO must be issued before the deceleration

delay terminates. The MTAF resets key flip-flops and registers. The MTGO pulse sets the CONTINUE
flip-flop (TC50-0-3 Sh 2).

Note that the MTGO pulse is enabled only when the inter-record delay is

not complete (GO is 1) and no change of direction has been specified.

With the CONTINUE fl ip-flop

set, the CLEAR GO pulse at the end of the inter-record delay cannot reset the GO flip-flop. With the
CONTINUE fl ip-flop set, the IRD OVER pulse resets DE-cC, the tran!iition of DE-c!'is enabled by
CONTINUE (1) to set the cC flip-flop which initiates the acceleration delay. Operation from this point
is as described for the write operation.

3.8

WRITE END-OF-FILE MARK
After the inter-record delay, the BEGIN OPERATION pufse sets the SYNC EOF flip-flop

(TC50-0-4 Sh 2) which synchronizes the tape operation to write the 178 EOF character.
enables the next CLOCK pulse to set the WRITE EOR flip-flop.

SYNC EOF

The transition of WRITE EOR, enabled

by SYNC EOF, generates the RECORD DATA pulse which is sent to the tape transport to write the EOF
character on tape. WRITE EOR then enables the 4-character sequence prior to LPCC character; WRITE
EOR enables the CLOC K pulses to increment EOR 1 and EOR2 to a 4-c:ount and generate the 4 CHAR
pulse. For a 7-track system, 4 CHAR generates WRITE LPCC (TC50-0-4 Sh 1) which writes the LPCC
character. For a 9-track system, the first 4 CHAR pulse writes the CRC character; a second 4 CHAR
pulse is generated to write the LPCC. Operation terminates when the read circuits detect missing data
and begin the deceleration of the tape.

3.9

READ
After the initial programming sequence sets up for reading c:md issues the MTGO instruction,

and the inter-record delay sequence is complete, operation begins when the read circuits in the tape
transport detect data. For each character detected, the tape transport sends to the tape control a

3-8

READ SKEW OVER pulse; the READ SKEW OVER pulse becomes the READ STROBE pulse (TC50-0-2 Sh 2);
READ OR READ COMPARE and ERF (0) enable the READ STROBE to generate the READ pulse. The character counter (CCO and CC1 on TC59-0-2 Sh 1) is zero at this time; therefore, 1 ST CHAR 7 CHANNEL
signal enables the READ pulse to strobe the 6-bit character from the tape transport into the high-order
bits of the data buffer (TC59-0-1). The READ pulse also increments the character counter.

Parity is

checked by the READ STROBE (TC50-0-3 Sh 1) by setting the LATERAL PARITY ERROR flip-flop when
an error occurs. The READ STROBE also accumulates the LPCC character by complementing the LPCC
register for those bits that are 1. Operation continues in this manner until the data buffer is full.

The

character count will be two (assuming 7-track operations) which initiates a data break cycle to transfer
the data buffer content to the processor. This is accomplished by the READ pulse generating READI NG
SET DF (TC59-0-1) which generates the +l~DF pulse (TC50-0-2 Sh 2) which in turn sets the DATA
FLAG flip-flop.
Operation continues in this manner until the read circuits detect missing data, thus signifying
end-of-record.

It should be noted that if the WC is less than the record length, only the number of

words specified by WC are transferred to memory.
record, of course, is transferred into memory.

If WC is greater than the record length, the entire

In any case, the detection of end-of-record by read cir-

cuits is the determining factor for stopping operation. This is accompl ished as follows.
The READ STROBE, which signifies that a character has been read from tape, is enabled by
MOTION FORWARD AND DE -(('(0) to set the DATA PRESENT flip-flop (TC50-0-4 Sh 1). DATA
PRESENT then permits the CLOCK pulse to toggle the EOR3 flip-flop (TC50-0-4 Sh 2). As long as data
is present, the READ STROBE resets EOR3 before EOR4 can be set. When data is missing, the READ
STROBE does not occur and EOR4 gets set. The next CLOCK PULSE generates the RECORD OVER pulse
which sets DE -(('to initiate the deceleration delay and thus terminate operation. The LPCC register
shou Id be 0 at this time; if not, LPCC f 0 (TC50-0-3 Sh 2) generates a PAR lTV ERROR (TC50-0-3 Sh 1).
To continue operation the program must issue M TAF and MTGO as described in the section on Writing.

3.10

READ/COMPARE
In the read/compare operation, a complete 18-bit word is read from tape and assembled into

the data buffer. After the word is assembled, the data break cycle is initiated to obtain the word from
memory for comparison. The word from memory is exclusive ORed into the data buffer. Consequently,
the data buffer should contain all Os; if not, the READ/COMPARE ERROR is set.
Operationally, the read/compare mode is similar to the read mode except as follows.

In the

read/compare mode of operation, the data break cycle is initiated (via READI NG set DF, TC59-0-1) to
obtain a word from memory in which to compare to the data buffer.

During the word transfer, the READ/

COMPARE signal permits the LDB pulse to exclusive OR the word from memory (I/O BUS) into the data

3-9

buffer (TC59-0-1). The data buffer is then decoded to determine if i1- contains a II Os. The CHECK
DB = 0 pulse (TC59-0-1) samples the decoded data buffer signal and if DB I- 0, then the READ COMPARE
ERR OR fl ip-flop (TC50-0-2) is set.
The READ/COMPARE ERROR being set inhibits the +l-;::'DF pulse (TC50-0-2) which prevents
any future data break cycles (until flags are cleared.) This prevents the CA in the processor from being
incremented even though operation continues. Operation continues ulntil the read circuits detect the
end-of-record. At that time the program may examine read/compare status and if a read/compare error
is found, the program can further examine the CA to determine the memory location that was in error.

3.11

DENSITY MODES
Three different tape densities are ava i lable: 800, 556, and 200 cpi (character per inch) .

Bits 10 and 11 of the command register select the densities (see TC50-0-2 Sh 1). The different recording
densities are effected by chang ing the clock pulse frequency.

For 800 cpi operation, the 800 bpi clock

pulses from the tape transport are enabled to produce the TC-59 clock: pulse (TC50-0-4 Sh 2); for 556 cpi
operation, the 556 bpi clock pulses from the tape transport are enabled. For 200 cpi operation, the
800 bpi clock is counted-down by flip-flops A and B (TC50-0-4 Sh 1) which produce ENABLE 200 every
fourth count to enable the 800 bpi clock to produce clock pulses.

3.12

ERRORS

3. 12. 1

Data Late Errors
The data late error indi cates that an extraneous word was either written or read from tape

before the data break cycle could supply another word for write or store the present data buffer word for
read. The DATA LATE flip-flop (TC50-0-2 Sh 1) is set when DATA FLAG is still set (indicating that the
data break cycle has not occurred) when STROBE DATA LATE pulse (VVP or READ PULSE) occurs.

3.12.2

Parity Error
As discussed during write and read operation, the parity error is the result of either a longi·-

tudina I or latera I parity error.

3.12.3

Read/Compare Error
The read/compare error was discussed in the read/compare discussion.

3.12.4

Record Length Incorrect
During read or read/compare operation, this error signifies that the record length specified

by the WC reg ister differs from the record-length read from tape. The RECOR D LENGTH INCORRECT
3-10

flip-flop (TC50-0-2 Sh 2) is set for a long record by the READ STROBE (enabled by WCO{O) indicating
WC is 0) and by the RECORD OVER pulse (enabled when the WC register specifies more data) for a short
record.
3.12.5

Bad Tape Error
This error indicates that data was in the inter-record gap. The BAD TAPE ERROR fl ip-flop

(TC50-0-2 Sh 1) is set by the READ STROBE (indicating data present) which is enabled by DE-<!'and
INTO RECORD.
All errors are combined, along with BOT, EOF, and EOT, to generate ERROR which sets the
ERROR FLAG fI ip-flop (TC50-0-2 Sh 1) following end-of-record. The ERROR FLAG status is sampl ed
by MTSF to generate a SKIP RQ (skip request) as shown on TC59-0-2 Sh 2).

If interrupt is enabled (CM9=1), the ERROR FLAG generates an interrupt as shown on
TC59-0-2 Sh 2.
3.13

ILLEGAL COMMANDS
The ILLEGAL flip-flop (TC50-0-2 Sh 2) is set by the MTGO pulse when one of the following

events occur.
a.

9-track operation specified and density not set to 800 bpi.

Write or write EOF operation specified and the write-lockout bit (WL) from the tape

transport is set.
c.

Beginning-of-tape status and a reverse motion specified.

Tape control (GO=l) and tape transport not ready.

A NO-OP (no operation) specified by the command register.

The ILLEGAL flip-flop is also set by the load command (LCM) when tape control is not ready
(GO(1)=1) and job done flag (MTF) is not set.

3.14

SPACE
There are two commands for spacing records -- space forward and space reverse. The 2s com-

plement of the number of records to be spaced is set into the WC register. The CA register need not be
set. The operation of space forward or space reverse is accomplished in a simi lar manner to read or write.
The program initiates operatiol1 by setting the WC register, loading the command register, and issuing
the MTGO which starts the tape and initiates the acceleration delay. Subsequently, the read strobe
is monitored for end-of-record. While spacing over a record, no data is transferred; however, the last
character of the record initiates a data transfer.

3-11

The end-of-record detection, as in normal operation, produces the RECORD OVER pulse which
initiates the deceleration delay. However, in a spacing operation it in itiates a data channel transfer,
if the WC is not 0i that is, it generates + l;::"'DF which initiates the tnmsfer (TC50-0-2 Sh 2). The we
register is incremented in this manner. The CA is not incremented, since the spacing operation generates INC· MB (TC59-0-2 Sh 2) which prevents the CA from being incremented. (The INC· MB
causes the data channel break (DCH) in the PDP-9 to be a l-cycle break rather than the normal 3- or 4cycle break. Only the we register is incremented during the break.) Since GO is still set, the MOVE
signal maintains tape motion.
After spacing over the required number of records, the WC flip-flop is reset, thus enabling
the STOP signal (TC50-0-4 Sh 1). The IRD OVER pulse generates CLEAR GO which resets the GO flipflop to terminate operation.
The detection of end-of-record in the space reverse mode is different from that for a forward
motion, since the LPeC is always the first character detected. This is accomplished by the INTO RECORD
flip-flop (TC50-0-4 Sh 1). The READ STROBE, which occurs as the result of the LPCC character, sets
the INTO RECORD flip-flop.

Note that DATA PRESENT will not be set by this READ STROBE. The

next READ STROBE occurs when the last character of the record (the first in reverse motion) moves under
the read headi this READ STROBE sets the DATA PRESENT fl ip-flop.

When no more READ STROBES

occur, EOR 3 (TC50-0-4 Sh 2) remains set and the next CLOCK pulse sets EOR 4i the following CLOCK
pulse generates RECORD OVER, which initiates the deceleration delay.

3.15

Dt..TA CHANNEL OPERATION
The PDP-9 data channel, multiplexed to permit interfaced service to four peripheral devices,

provides a high-speed interface to the core memory along the I/O bus.. Requests for data from the tape
control are honored by the channel at the completion of the instruction in progress at the time the request
is made. The channel is controlled by word count (WC) and address registers (CA) held in core memory;
each request updates these registers and transfers the data between the memory and the tape control.
Each of the four devices has a unique pair of (sequential) core memory registers associated
with it. The tape control is allocated to locations 32 and 33. These registers must be initial ized by the
program, before the peripheral device may begin transferring data through the channel. The first (word
count) register, location 32 I is in itial ized to contain the 2s compl ement of the number of words to be
transmitted.

The second (address) register, location 33, is initia I ized to contain one less than the first

address of the data word block.
These registers may be examined at the end of channel opemtion to check for final address,
if, for example, the tape control indicates that an incorrect record length was read.
The maximum transfer capacity of the channel is between 250,000 and 333,000 words per
second, depending on the mix of input and output rates. Each input tronsfer steals three processor
3-12

cycles; each output transfer steals four processor cycles. The latency time {maximum wait before service
is granted after a request is made} may be as high as 30 I-'sec under adverse conditions.
Priority among I/O devices making simultaneous requests is determined by their physical placement on the I/O bus, with devices close to the processor having priority over devices further away. The
establishment of priority requires that each device quickly propagate an enable signal (ECH EN) to the
next device on the bus.
The DATA FLAG, as explained previously, is raised asynchronously by a request for data
transfer within the tape control. This flag is synchronized by the Wl04 Multiplexer, which requests a
data channel interrupt through the DCH RQ line (TC59-0-2 Sh 2).

If more than one device on the channel

is: requesting, the multiplexer insures that the lower priority device is shut out by driving its enable (DCH
EN IN) input line to ground and thus maintaining its DATA RQ flip-flop in the reset state. This request is
rE!cognized by the processor and, at the end of the current instruction, control is re Iinquished to the channel hardware.
The channel hardware begins operation by identifying the device requesting service. This is
performed by issuing a grant signal (DCH GR) to all connected devices. Upon receipt of the grant signal,
the device which supplied the DCH RQ transmits the core memory address of its word count register along
the I/O address Iines. The specified reg ister is read from memory, incremented, and rewritten.

If, in

this word count updating procedure, the count reaches 0, an I/O overflow signal is sent to all devices.
The device hardware interprets the overflow signal as a shut down command.
made until the device is reinitialized by the programmer.

No further transfers are

Note that the READ RQ and WRITE RQ are con-

ditioned by DATA EN B; this assures that only the selected device propagates the read or write request.
After incrementing the word count register, the channel reads the next sequential word from
memory. This is taken as the current address reg ister, which is incremented and rewritten into memory.
The updated value is used to specify the location into (from) which the data is to be transferred.

3.16

AUTOMATIC PRIORITY INTERRUPT
The priority interrupt operates in a manner somewhat similar to the priority scheme of the data

channel.

Both make use of the W104 modules.

Priority is establ ished by putting the W104 modules in

tcmdem. The API EN IN signal coming into the high-priority module with the API RQ flip-flop set will
generate a ground signal on API EN OUT which disables the API RQ flip-flop in the lower-priority chain.
Interrupt requests start when the MTF or ERROR FLAG (enabled by CM9) generate ENABLE API
RQ, which in turn sets the INT flip-flop.

INT enables the I/O SYNC pulse to set API RQ; API RQ

remains set if there are no higher priority requests and sends the PROG INT RQ (interrupt request) to the
processor. The API GR pulse (priority grant) then transfers the core location address of the program subroutine unique to the tape control to the processor. The API GR also resets the interrupt request (INT)
flip-flop.
3-13

CHAPTER 4
MAINTENANCE

This chapter contains the information required for maintaining the Type TC-59 Magnetic Tape
Control. Three categories of maintenance are provided: preventive, troubleshooting procedures, and
corrective.
Preventive maintenance includes routine periodic checks, such as visual inspections, standard
procedures involving cleaning and lubricating, minor mechanical adjustments, and occas:onal marginal
checking to expose weakening conditions before they become malfunctions.

It is primarily concerned

with mechanical operations of the tape transport.
It should be emphasized that good maintenance procedures are predicted upon a thorough
knowledge of not only the tape control unit but a Iso the tape drive and the PDP-9 processor interface.
Therefore, if the maintenance technician is not familiar with the theory of operation, he should review
Chapter 3 of this manual or the applicable sections of the tape transport manual and the PDP-9 Maintenance Manua I.
Troubleshooting procedures range from basic power-supply checks to intricate logic troubleshooting techniques involving programmed operation of the PDP-9.
Corrective maintenance outlines the measures required for correcting any malfunction, after
it has been isolated, by replacement of the module or defective part.
In addition to maintenance information, this section includes assembly-location information,
to faci Iitate locating the circuits and parts within the system.

4.1

MAINTENANCE EQUIPMENT
The maintanance equipment specified in the PDP-9 Maintenance Manual is adequate for per-

forming tests on the TC-59 Magnetic Tape Control. The Datamec Manual references special adjustment
tools for a Iigning the tape transport.

4.2

MODULE LOCATIONS
Drawings D-MU-TC50-0-13 and A-MU-TC59-0-5 in Chapter 6 of this manual show the loca-

tion of the modules within the mounting panels, as viewed from the wiring side. The key functions or
signals associated with each circuit on the module ,:Ire I isted within the module location and grouped
according to the alpha pin designations.

4-1

4.3

PREVENTIVE MAINTENANCE
Preventive maintenance consists of tasks performed periodic:ally I during operating time of the

equ ipment, to ensure satisfactory operation. Performance of such tasks foresta lis fa i lures induced by
progressive deterioration or minor damage, which, if not corrected, cause eventual down-time.

Data

obtained during the performance of each task is recorded in a log book. Analysis of this data indicates
the rate of circuit operation deterioration and provides information for determining when components
must be replaced to prevent failure of the system.
The following mechanical checks must be performed at spec:ified intervals determined by
operating time and operating environment. Following is a list of the periodic checks and procedures
required.
a. Clean the exterior and the interior of the equipment cabinet with a vacuum cleaner or
clean cloths moistened in nonflammable solvent.
b. Clean the air filters at the bottom of the cabinets. Remove each filter by taking out the
fan and housing {held in place by two knurled and slotted captive screws}, and wash in soapy water and
dry in an oven or by spraying with compressed air. Spray each filter with Filter-Kote {Research Products
Corporation, Madison I Wisconsin}.
c.

Lubricate door hinges and casters with a I ight machine oil, wiping off excess oil.

d. Inspect all wiring and cables for cuts, breaks, fraying, wear, deterioration, kinks,
strain, and mechanical security. Tape, solder or replace any defective wiring or cable covering.
e. Inspect the following for mechanical security -- switches, control knobs, lamp assembl ies, jacks, connectors, transformers, fans, and capacitors. Tighten or replace as required.
f.

Inspect all module mounting panels to assure that each module is securely seated in its

connector.
g. Inspect power supply capacitors for leaks, bu Iges, or discoloration. Replace any capacitors showing these signs of malfunction.

4.3.1

Power Supply Checks
The power-supply output checks described in Table 4-1 are performed by using a multimeter

for the output voltage measurements with the normal load connected. The oscilloscope is used to measure
the peak-to-peak ripple content on all dc outputs of the supply. The +10 and -15V supplies are not
adjustable; therefore, if the output voltage or ripple content is not wahin specifications, the power
supply is considered defective and troubleshooting procedures are required.

Refer to engineering draw-

ing RS-B-728 for the power supply schematic.

4.4

TROUBLESHOOTING PROCEDURES
The troubleshooting procedures make use of two programs: TC-59 Control Test (MA INDEC

9A-D4AA-D) and the TC-59 Uti I ity Program. Program descriptions of both are provided as part of the
documentation supplied with the equipment; they should be consulted for maximum troubleshooting

4-2

efficiency. The TC-59 Control Test exercises the tape control circuits and provides error printouts.
The Te-59 Uti! ity Program, through its pseudo commands, provides a means to expediently program tapecontrol functions to exercise and test specific functions in conjunction with the DDT program. Test programs can be easily written, coded and typed in for immediate execution.

4.5

MODULE UTILIZATION
Table 4-2 contains a list of the number of modules used within the TC-59 Magnetic Tape

Control Unit.
Table 4-1
Measurement
Term ina Is at
Power Supply
Output

Power Supply Output Checks

Nominal
Output
(Vdc)

Acceptable
Output
Range (V)

Maximum
Output
Current
(A)

Maximum
Peak-to-Peak
Output Ripple (V)

Red (+) to
Yellow (-)

+10

+9.5 to 11 .5

7.5

0.7

Yellow (+) to
Blue (-)

-15

- 14 . 5 to 16. 5

8.5

0.4

Table 4-2

Module Utilization

Number
Required

Description

B130

3-Bit Parity Circuit

R002

Diode Gate

R107

Inverter

S107

Inverter

Rlll

Diode Gate

Rl13

Diode Gate

R123

Diode Gate

R141

Diode Gate

R151

Binary-to-Octal Decoder

R201

Flip-Flop

R202

Dua I F I ip-F lop

R203

Triple Flip-Flop

R205

Dual Flip-Flop

R601

Pulse Ampl ifier

4-3

Table 4-2

Module Utilization (cont)

-Number
Required

Description

R602

Pulse Ampl ifier

R603

Pulse Ampl ifier

WOO5

Clamp Loads

W640

Pulse Amplifier

ROO2

Diode Network

R107

Inverter

R1l3

Diode Gate

R123

Diode Gate

S123

Diode Gate

R202

Dual Flip-Flop

R203

Triple Flip-Flop

R205

Dual Flip-Flop

R602

Pulse Amplifier

R603

Pulse Amplifier

W103

Device Selector

W104

Device Selector

W107

Device Selector

W640

Pulse Ampl ifier

4-4

CHAPTER 5
INSTALLATION

The magnetic tape control is usually mounted in the main frame of the central processor separate from the magnetic tape transports. Therefore, the magnetic tape transports are packed individually
<md the cables connecting the transport and tape control are removed.

In most cases, the interconnection

between the tape control and the associated processor remains intact, unless the t::1pe control is located in
s,ome place other than the main frame of the processor. There are five cables wh ich connect to the transport; they are single 9-conductor coax with W021 Connector Boards attached at each end and are approximately 10ft in length. To install the tape control unit to the tape transport, proceed as follows.

5.1

PDP-9 TO TC-59 CONNECTION

a. If the TC-59 is shipped for field installation, connect the PDP-9 cabinet to the TC-59
cabinet according to the fie Id attachment kit instructions.
b. With a II power off, connect the 30A tw ist-Iock from the 834 Power Control in the TC-59
to its power outlet. Connect the standard 115 Vac 3-prong cable to the available outlet in the PDP-9
841A Power Control.
c. Connect the I/O cables (7-ft W850s) to the PDP-9 and TC-59 as follows.
PDP-9 Connection

TC-59 Connection
Cable 1
Cable 2

EF 1 and 2
EF 3 and 4

AB 25 and 26
AB 27 and 28

d. The TC-59 834 Power Control Circuit Breaker can be turned on with the 834 Power Control
in remote selection. Do not turn on PDP-9 power.

5.2

TC-59 TO TU-20 CONNECTION
a. With the TU-20 Power Switch off, connect the 30A twist-lock to its power outlet.
b. Connect the transport cables (five 10-ft W021;WOll cables) as follows.
TC-59 Connection

TU-20 Connection

Cable 1 AOl
Cable 2 A02
Cable 3 A03
Cable 4 BOl
Cable 5 B02

C04
CO2
C05
COl
C03

or
or
or
or
or

D04
D02
D05
DOl
D03

c. Turn on circuit breaker on the TU-20 841A, with the 841A in the local position.
d. Push the POWER switch on the TU-20 control panel to the ON position. The DC POWER,
RESET, and OFF LINE lamps should turn on.

5-1

e. Turn on the PDP-9i the TC-59 power should come on with all control panel indicators off
except the write buffer.

At the tape transport, select un it 0 and put the tape at loadpoint and ON LINE.

g. The READY and 7-track indicators should come on with the write buffer off.
This completes the installation.

Now run the diagnostics; TC-59 Control Test and Utility Test.

If a malfunction occurs, refer to the maintenance chapter of this manual for guidelines to troubleshooting
this equipment.

5-2

CHAPTER 6
ENGINEERING DRAWINGS

This chapter contains the standard block schematics, circuit schematics, and engineering
drawings necessary for understanding and maintaining the TC-59 Magnetic Tape Control Unit. The
drawings are listed in the same order as they appear in the manual.

Engineering Drawings
Title

Drawing Number

Revision

D-BS-TC59-0-1

DB Register

D-BS-TC59-0

Data I/O Control (2 sheets)

D-B S-TC59-0-3

Device Selector

D-BS-TC59-0-4

TC59 Bus

D-MU-TC59-0-5

Module Utilization

D-BS-TC50-0-1

Motion Up Counter and Writing Data

D-BS-TC50-0-2

Command (2 sheets)

D-BS-TC50-0-3

Data Flow (2 sheets)

D-B S-TC50-0-4

Timing (2 sheets)

D-IC-TC50-0-5

Indicator Connections

D-FD- TC50-0-6

General Motion Timing

D-FD- TC50-0-7

Write Flow

D-FD- TC50-0-8

Isolated Flow Logic

D-FD-TC50-0-9

General Flow Graph

D-FD-TC50-0-1 0

Data Flow Delay Sequence

E-FD-TC50-0-1 "

Timing Flow

D-MU-TC50-0-13

Module Utilization

O-IC-TC50-0-14

Power Wi ring

Module Schematics
B130

3-Bit Parity Circuit

R002

Diode Gate

R107

Inverter

5107

Inverter

R1ll

Diode Gate

R113

Diode Gate

B
6-1

00du I :._Sche~ati~~ (con_~
R123

Diode Gate

R141

Diode Gate

R151

Binary-to-Octal Decoder

R201

Flip-Flop

R202

Dual Flip-Flop

R203

Triple FI ip-Flop

R205

Dual FI ip-Flop

R601

Pulse Amplifier

R602

Pulse Amplifier

R603

Pulse Amplifier

WOO5

Clamp Loads

W640

Pulse Amplifier

S123

Diode Gate

W103

Device Selector

W104

Device Selector

W107

Device Selector

6-2

-+"''----_...J T
,-~~_ _ _ _ _ _ _ _ _
V~~__________'----~~r-~STROBE

~r1
T

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I REA~/COMPARE:

S
R !/3 (I)

LD8

RB~

DBG-DBII

.-----------.---DClEAR DB
READ

ClEA R /'t'lTF" ... E:F"

I )~T ECHAR 7CHANNEL
READ PULSE.

L
ENABLE RB-+
DBG-DBII

S'RO'8E.
~ l"R.AC K ~ DB

DB~I/o BUS (¢9-17)

--t-----=--WR ITE"

READ

DB 14 (~) T
DBI5"(¢) u

Rt:AO PULSE D

CLEAR DB

B
I/O BU5-'>-DB
L

I/O BU S QS~ (I)

1./0 BuS 14(1) I'A

STROBE" RB ~

T
1./0 BU:; 15" (I)

I/O BUS IGlI) M

DBG-DBII

:')

R'7S(I)

R%(I)

CHECK D'i3= ¢
!---<t----1>READING SE, D.F.

RB- 08 (2..-~)

-=--+ RB -- D8(2.-9)

RBS (n

COB K
L

2ND CHilI< '7CH~NNEl

3 RD. OIAR 7CHANNEL ..

READ! COMPARE

WC~ 0)

1'51 CHAR.

DEC FORM NO

2
D-BS-TC59-0-1

6-3

DB Register

~__________________________~L~~;
~________-,--,M:.....,

~--<> LAST

WORD

R 1\ "3
E.2"1

(PDP 8) 1ST CHA.R 9 C\-IANNEL OR.
C \-\p. R 7 C\-I P. NNE L.

+-:--------.. 2. N D
,P

ENABLE. RS-'
DB (j,-DB I I

90\ eND CHf\R

~-------.. 1ST CHAR 7CHANNEL

D
E

L-o

'1Cl-IANNE.L

\~T CHAR

w,p.

PULSE.. K

'----+---<10-- 7 C H
I

CCI(¢l

DEC FORM NO

2
D-BS-TC59-0-2

Data and I/o Control (Sheet 1)

6-5

~KIP

F\-I

API.IE.N IN

-~'-'-'-<.·I

1:iOADOR \7 I

APIIEN~U
,c.,p:

IR~!

~u..=./

\OJ

I
PROG IN, RG:!
I

ENABLE.

DATA FLAG

ERRORFLAG(l)

FU FJ

47J1

WRITING
5E.T Dr

WP,

I/O ADDR \5

r---~--~
1~~7 I

:/0 AODR \e..

WIC4
EF" 17

10 PWR CLR

TAPE

MTCR

G0 (¢)

API

GR
AF'l R~ l\l

~
p

t--___-

FA
H
R6(t3 r - - - - - - - - - - F2'
I/OADDR 13

WI¢4

CM9(1\ J
WRIT E'

.. DB~"I/O SUS
(<,?j'1- 17)

.H, ~.. - - - -

READ CO/'ll?IIRE. J

EF 18
OCH EN

READ
'f CL~ARED sy DATA LATE (I)

B
10

PWR C.LR ---II"' VI

lO SY\,\C ---,E.=:.H.:...,'.v'Vl
DATA FLAG (I)----;:::=-_ _ _---.J

CLEAR ;ViTF+E.F••~D-p-.~.:...==--.,--J

-------I

DEC FORM NO
!)~J

!02

D-BS-TC59-0-2

1
Data and I/o Control (Sheet 2)

6-7

W850
EF07

'vVS50
EF~3---

EF03

E D

I:. D

E E

IE K

E K

IE P E P

e: S

E T

s: T

EVE V

EF'C2l4

I/O ADDR ¢':'J

r/o ADDR 191
IIOOFLO

I/OADDRII

I/O AODR 133

rio ADDR Ie.

F..E

J; H

IE .K-+--+-E...K4~::>-_ PI P:l ¢ 1'<.<>/

I/O ADDR~5
I/O ADOR 1217

t= 0
FE

ADD R ¢8

-+-1.......--+---. A F 1 3 G R
-H--+-+-"'~

F H

iF J<.

Del-!

EN IN

~-------"'.DCH

052-

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10 P I

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10 P "i

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F P

F p

E PEP

F 5

r 5

F T

PROG INT RQ
ESE 5
e---,r-t----..--IO- REA D R Q
I:: T
ET

D5S

.-.,I-+.....-+-...... 5 D~

SKIP RQ

RQ STATUS

SDI

r/o PWR. CLR.

EN OUT
EE

MTTR

WlTeR

DSS-

E H

IE H

D
I/O SYNC

API 3 EN

Del-! GRANT

API I EN (IN)

EE
PA

D'5~

053

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F I:.

DSI

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- H........-i<>-- DC H

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API 2. GR

_+-1.......--+-____• -A PI

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EF¢'=>

EF~e.

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-t--t--K>--A PI 3 RQ

' - - - - -...... API I EN (OUT)

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-.,r-t-+--f--...... ,I>. P I I GR

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W850
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EF08

F D

.-11-+_+-...... F\ P 1 0 G R
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.-11-+-+-+-...... A PI ¢ EN
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I/O ADDR ¢G

e---jr------t-.....--t-- I/O

EF04

-!:.I-C,A INHIBIT

I/O ADDR !254

~F(i'}8

ED
ED
.-1I--t--+--tC___ W RITE RQ
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.....-;r-t--+-j()- I NC WI B
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W850

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DEC FORM ~c

DPD:02

D-BS-TC59-0-3

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6-9

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EF01

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r/o BUS ill", (I)

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DEC FORM NO

D-BS-TC59-0-4

6-11

TC59 Buss

I I 2 I 3 I 4 I 5 I 6 I 7 I 8 I 9 10 III 112 13 14 15 16 117 118 119120121 122123124125126127128129130 131 132133134135 136 137 138139140 141 1421431441
1 1
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cell

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39 I 40 I 41

43 44

INDEX
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36 I 37
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DEC FORM NO
ORO 105

D-MU-TC59-0-5

TC59 Module Utilization
6-13

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DEC FORM NO.

DRD 102

D-BS-TC50-0-1

Motion Up Counter and Writing Data
6-15

Ir~ SET TAPE"

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DEC FORM NO.
DRO 102

2
D-BS-TC50-0-2

Command (Sheet 1)

6-17

~
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DEC FORM NO.

ORO 102

1
D-BS-TC50-0-2

Command (Sheet 2)

6-19

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DEC FORM NO.
ORO 102

2
D-BS-TC50-0-3

1
Data Flow (Sheet 1)

6-21

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DEC FORM NO.

2
D-BS-TC50-0-3

Doto Flow (Sheet 2)

6-23

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7- CHANI\lEL

DEC FORM NO.
OAO 102

1
D-BS-TC50-0-4

Timing (Sheet 1)

6-25

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*B~5

I-

rr - SnmBI! -

28
RI~7

REAn EIV EOF
COMP,
- DATA
TO
PRESNT STOP

R6B3

SIB7

R2D5

I RD

RB5
_ (1)

(I)

EOF

R2J15

ERROR

r- 0

DATE
lATE ILLEGAL

COUNT

ALL

OR
rtBlTE

R21l5

'Il

STROBE ~

CLEAR

DELAY CHG
TRANS
FERRE, 0 IF>.

FU~~~~

!T~OR

rEOF -

8/4(0)1 '/5 (" IZ/6(." 1/7(.Il) CHAR

JVll(ll)

RII~

'Em:

RIll

RBll3

RB
17 8

ERROR

20
R2112

~R80p, ~

~EVERSE

ENABLE
MTF

-1M - -111-

~Tf03E

R141

ViRI TE
tPAR I TY

FLAG

STt,RT

I" 1'1

STR CBE ~

GO (,ll)

DELAY

DATA

r---

K 14

! !

'I lLEGA

IL~~~~~ f;j SYNC

SPACE

~nT I ~N

K 14

IFiiiIi(T

STROBE
C R C RFr:nRn

1RZIl3

MOVE

16 I 17 I 18

15
K14

LLEGAL
STROBE ~
B/2(.0) A/3(.0)

OJ)

S1117

PAiiiTY EOF
REPORT
-

14
IK141

HEAD

t-STIP

IRECDRD WCD(Il)

CONT

~ cI-RROR_

MOVE
1.17(,11) START;
STOP
WRITE WRITE
, PARITY LPCC
, ,~/I(1) ENABLE

Ko:ll3

~ECT

["ER~

4/5(0)

R123

I lPCC8
I

TIMING

B 2/6(11) SEL2

RZll2

OC(I)

READ
RIl/O( 1) SCRom
\'j1l21 WIl21
RECORD
S/2(Il) niT'

B/4(1l) SEll

RI,1l7

ERROR

mCK

Rl>1l2

556
CLOCK

ROil (1)1

PAR I TV

Rl/7( 1)1 7CH
RBP( 1)

R5112

LAT.

556

R4/5( I)

A R2/6(1) w. L.

6
R5113
~t 1

8m 1)!, ?~f'; 2,69
RA/3( 1

5
R2Q2

STiP
WRESENT r-

r-----

ILLEGAL r - - -

f---

r - BIlII
RECORD

- MOTION LENGTH READ

ORWARD

MUC
5

rERF

FOR'llAR[ I~~~~-

DELAY

SYNC

PULSE

DEC F"ORM NO.
ORO 105

D-MU-TC50-0-13

Module Utilization

6-43

I
D

OEC F'ORM NC.

ORO 102

0:h

BID

INDICATOR

PANEL

3
D-IC-TC50-0-14
6-45

Power Wiring

,~3 ,

r,r

..l

)

,~8 ~ r~ r>
~

....J

~~H ~

~12, ~13

...

)

~14. ~1!5. ~6
~

~8
DEC2894-1B

RI6
• 7,!500

R20
7,500

R23
7,!500

;----

R7
~C2
220 ;: 1'.01
MFD

,GY

~7
DEC2894-IB

DEC2894~B

Rl2
7,500

01
~894-18

~!5

DEC2894~.

R4
>~I
1,500 1,1100

)

I--R3
220

OUT

R2
1,!500

;:~~

fr
\b.
~I

1,000

~gt ;:: r;CII

100
10..

I uhy

...--

,~g~2

~D ' rg~~82
~ r8!~2

R21 ~L2
100 oluh~
10110

~-2.2V

~, g~9862
,~ gl~862

08
DEC3009A

,~ g~~62

OUT"I·~

04
SDA-8 ~

;.7J'..

R22
!58
10..

MFD
RI4

~102
DEC3009A

"er5--

RI9
!56
10..

RII
1,!500

Rill
220

MFD

10..

~
WI0
1\

Rli
1,Il00

R9
1,!500

A+IOV(")
C GND

-4.5V

~. ~

RI3
1,!500

RI7
1,!500

R24
1,000

R~
1,000

R26
1,000

)F
v

-2.2V

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W, 11%
DIODES ARE 0884

1::::::::::;:::::::1

B130

3 Bit Parity Circuit

010

0664
011

}

0664
09

0664
04

.1
0664
08

0664
03

0664
07

',:

'-1

0664
02

'-1
0664

a-I

0664
01

0664

1::::::::::;:::::::1

R002

Diode Gate

6-47

B-IIIV

; EXAMPL.E-i
I

DGL2

--------o---------l~----+-I---~ 1.(+1011.)

100,000

R4
100,000

100,000

100,000 I

100,000

r----- j

r-----,

i--t-+----<IIo------;_--H~---+-o C(GND)

08
I
0662 I

I
MFDI
I

I
I
I
I
I
I
I

D9
I
06e2 I

g~~2 :
011

0662 I

I
RIS
I,SOO

I
:

-+1-+--3-V-~'-0 B (-1511.)

~~T.!l~!..E_J

R22
:
IS,OOOI
I
I
____ .JI

v
UNLESS OTHERWISE INDICATED,
RESISTORS ARE 114W\ a..
DIODES ARE 0-.4
TRANSISTORS ARE DEC 3639B
PRINTED· CIRCUIT 'REV. FOR
DGL BOARD IS SIA

R107

Inverter

r------.,

--.----+-,---'--oC
GNO
I
08

0-662

:
1

09
I
0-6621
I
DID
I
0-662 :
011

--+-~-~---+--~~~-++--_4-----__--~6

-----,

RI4

3,000 :

___~~___.-_~2~
I

R22

:
15,000 I
I

I
----j

UNLESS OTHERWISE INDICATE 0:
RESISTORS ARE 1/4W;5%
DIODES ARE 0-664
TRANSISTORS ARE DEC 3639
PRINTED CIRCUIT REI/. FOR
OGL BOARD IS SIA

USE THE ETCH BOARD OF THE R 107

1::::::::::::::::::1

S107

Inverter

6-48

0-662 1

RIS
I,SOO

---t-O B -1511.

-311.

L STRATE
______ j I

r-----------------------------~._------------------------------._-----------------------------~OA+10V(AI

r------,1

GNO

019
0-662
018
0-662
017
0-662

00----.....,......

Ro----1....-

05
D-864

Eo---_etrl-....--Q'

010
0-884

018
0-882

so---...--.....--<>

----,
RS

7,800 I
D'IIo
1

L-----~--_2~1------------------~------__----------------------~----~~------------_r~----~_oB-~V
EXAMPLE DGL2

-3V

1... _____________ -'

LSTRATE
______ JI

UNLESS OTHERWISE INDICATEO:
RESISTORS ARE 1/4W; 5%
PRINTED CIRCUIT REV. FOR
DGL BOARD IS SIB

Rl11

Diode Gate

0 B-UW

R2
15,000
04
0~64

....

R6
010
().664 7,500

R8
15,000
"F

... 08....

"" ""

R4
100,OOC

014
0:'64

H
02
OEC36398
J~

020

RI2

RI4
15,000

0-66~ 7,500
~K

016 018

....

.....

...

"" ""

DI3

....

... ....

027 028

....

"" ""

025

OEC36398

RI6
7,500
~N

026
0~64

\!!:, 04

RIO
100,000

02~

0-664

RI5
100,000

0~64

.....

05
OEC363.B

A+ 10V

II --1
RI
15,000

02
0:"64
... - ,

R5
7,500

£! ....07
"" ""

019
RII
0664 7,500

R7
15,000
~S

01
0.:.f4
R'"'
.'"

09
-664

012

0:'64
fP'
T"
R3~ 01DEC3639B DII
100,000
0~64
..,
P"l

R 13

I
~V

015 ?}.7

.... ,....

~5oo ,

:~ ~O 241

f"'II

R9
100,000

CI
~ .023, ;:: ~.OI

OEC3639BI~ .022'

1_- __

-:IV STRATE

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4 W, 5%
DIODES ARE 0662

I ::;:;:;:;:; -; : :; --; -; :; :; :; :- :; :1

Rl13

Diode Gate

6-49

MFO

• D21 I

0 C GNO

r--------------4~------------~~------------~~------------~~------------~~--------~A+IOV

R 2

R 5

100,000

R II
100,000

R8
100,000

R 14
100,000

(AI

R 17
IC>qOOO

.-------+----.--------+---+----0 C GNO

010
09

013

RI
IS,OOO

R4
IS,OOO

R7
IS,OOO

RIO
IS ,000

~------------~~------------~~------------~~------------~~------------~~--------~OB-ISV

UNLESS OTHERWISE INOICATm:
TRANSISTORS ARE DEC 3639
RESISTORS ARE 1/4W,so4
DIODES ARE 0-664

USE THE ETCH BOARD OF W 101

1------------------1
....... '. f....
I I

R123

O.!..~

...

,...
K

0.:.3

r'L

..
....

,...
T

,...

~
"'-1

,...

~
...

IJIoI

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W, II°A.
DIODES ARE 0664

....
""

0~--;2

CI
.01

.....
r"I

.....

D24
0882

018
R4

«to.
U D23

0882

RII
I,!IOO

C eND

OEC3839 8

OEC300n

~'025

~~D

019
R5

RIO
100,000

-tD~1

...

022

15.000

1
T

·R9
7,800

15,000

1
L

!1
"'-1

r"I

020

~
....-.

A +IOV (A)

RC.
27,000
10%

O~I

15,000

...

III

Diode Gate

IS ,000

tal

......

017
R3
15,000

?!.6
R2

r"I

15,000

0111
~

....
0 8 -18V

15,000

1------------------J
........................

RI41

Diode Gate

6-50

.....- - - - - -.....-----+_----_<II-----_+-----------~A+IOV(Aj

.------~~----_<II~----

~ R4
'<"100,000
>. R5
<:.
R6
S
R7
~R8
<>100,000
<>100,000
<>100,000
100,000
'
<
<
_<>
.--------oD
<
<
>
>
>
>
>
..---.----0 C
.---~-~~--~-~~---~--<II------~--.---+--+-----+--.---~---~

~
R2
<>100,000

RI
<:>100,000

R3
<>100,000
<
>

«L, ~, ~, «L', ~. ~, ~~
III

~~D26

.4~D25
R17n <>
7,500<

RI8,<
7,500<>

~~027

.4~D28

~, 045

~, 048

~, 049

0-662

D-662

~'D50

[}-662

~.,J __

RIO
033 15 ,000 <
0-662

5,000 <

A~DI ~~.02 ~~_03

5> ••
RI2.~
~ ~03515,000';>

RII
03415,000(>
0-662

D-662

D3r5,000<>
0-662
>

0-662

MFU

[}-:~

.... 044
D-662
>R25

~------<>
.......--_+---....- - -.....

.......--_+-4-.....-+_-+-~r_+---<IIRI5

.4~032

•

~, 052

051

RI3>~, RI4,~ ~.~03815,Q00<>
n~~'

.,
, '-D3615,000 <>
[}-662
>

D-662
CI
- ......01
~,

R24,<
7,500<>

D-662

r----1t--~~t___i-----t-_<IIr__i---<~_..-_+---<II'--

R9,~~,

0-662

..,

~~D31

~ ,

D-662

~~041

R23 <>
7,500>
>

7,500<>

1,500

0-662

~
~ ~~D40

RI6
'-039 15,000
0-662
>

.-~~-,

GND

~~7 ~'042

R22_~

R21.?
7,500~

R20,<

7,500~

D-,

I---

~~D30

.4~D29

<
RI9.?
7,500<>
>

IO,v

0-662

.-~~~

~~.D5 A~OS ~lD7 ~~08 ~~D9 ~~010 ~~011 A~012 ~~013 H 014 ~lD1!i .4~016 A~DI7 .4~.4~
H
~~D21 .4~022 .4~023 .4~D24
DI8 Dl9
020

f~lo-~-t_-t_-t--+--t---t--t_-~~t-_+---i---<II'--~~---i---i--r-~--~-~-~~-~~~-4--~-
KOo-~-r--r-~~-+--~------r--r-~~~-~-------1~-~--~--r-~---r----1r-~

2~fF'o--+---+----+--r-----+--t---~--~~---r----1~--~-~---+-----t----r-~

UNLESS OTHERWISE INDICATED:
RESISTORS ARE V4 W; 5%
DIODES
ARE 0-664
TRANSISTORS ARE DEC 3639B

EOo---+-------+---t-----+-----~------r_--<II~--~-~

2~I~o--t--------+--------t------+--------~~-------~-------~-----~

2JOo__-~------~-------~------~

R151

Binary-to-Octal Decoder

.----------e-·------t--------------------------<OA+IO~A)

.--.-----1~----_+-------------------------<II~~CGNO

H
.., ~4

~~2
~

03
~I

...

~~8

-+ 09

........

05
F

CI
Iqp

"'-1
C2
IBO

~'~~662

... pt0
,n 011

...

~
...

Q2
DEC 3639C ~

( P

~g~~82

....

....-. ~ ....
023

025

.....

!l
021

D49.4~

~29
~~32
... [J34
41l
030
033
03!1
028 •
R ........
....J.t--.....i~
e - UT . - -....:..II-+--t.....-ov

~~27

...

......

~
....

~~ D48

~24

~~22

~~g~8662

D4 7~~

.4lD44

~~g~:82

......- - - - - -............----------0--.. - ---.--.-.... ~- f - - - -

RIO
100,000

QI
o C 3639C

I?P

I~f

026

031

.J~~

:;:~C6

r M

RI
: 15,000

R2
15,000

~ R3

~ R4

1!I,ooo

15,000

0-662

"'l~20

pnwr

~,D38

M~~~,g:J62

11111 "Oil

~,039

....

l?f

15,000

4,700

15,000

( RII
~ I!I,OOO

RI2
I!I,OOO

RI3

>15,000
>

RI4
15,000

Rill

: 15,000

RIS

:> 15,000

RI7
I,!IOO

....-----4~----------~----~--~----~--------~~--~....------~----....--------._----._------~-<08B-'!lV

~----~------

UNLESS OTHERWISE INDICATED'

~~lrJ':s

A:iE I=:~~

DIDOES ARE 0-664

R201

FI ip-Flop
6-51

....

,.------ -----_._---_._-_.-

~---------.-----~--------

043

OSO

-~~-------_.--~r_------+_--4--_oA+IOV

--+-~_H_-OCGNO

038

R20
15,000

---------t - -

--+f----r--t+O~

1,500

UNLESS OTHERWISE IfoIDICATED:
RESISTORS ARE 1/4W;S.o/ct
CAPACITORS ARE MMFO
DIODES ARE 0-664

R202

Dual FI ip-Flop

052

A+IOV (A)

042

-OC GNO
046
0-662
045
0-662
C4
.01
MFO

R24
15,000

044
0-662
043
0-662

B-15V
R25
1,500

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W\5%
CAPACITORS ARE MMFD
DIODES ARE 0-664
TRANSISTORS ARE DEC 3639C

R203

Triple Flip-Flop

6-52

,fo~3

-f~-~ ~D59

~~D56

~~D54

~~D61

"'A+IO\I(A)
( L

( K

R4
: 100,000

~'D3 ~ ,D6

RB
100,000

* ~
...

~
.... ,

~ ,g~662

ro-

?!
r ...

. .
~k:

"".

R5
4,700

C4
I~O

ro-

...,

....

_p.!.
RI
R2
>15,000; 15,000

DI7

02
DEC 3639C

~ ,09
D-662

C3
I?J>

...

DEC 3639C

I?P

• RIS
~~ D27 ~ ,D30 100,000

~rD21 ~ ,D24

~~2

,P13
' r D-662

...

,~g:~62

r'l

,....

~
04
DEC 3639C

~ 'D33
D-662

~2B""

. •

(

-. ----< ...-

'A"

Dj4

,.....

...

C GND

CS
100

D41

~~~
',D52 ;;:

~ 'D38

~6
....
,

,~g~~62
;:~g

...,

(

'g~62

MFD ~

c ~,%Oc

D-662 MFD

0-662

_~ ,~

c RI3 .c
>,R15. c RI7
I!!POO. ~I~~>15{X)0 4,700

~ ,D45 , ,D4B

......

..,!..

531

( T

-'
DEC'3639C

D29
....t

~~IO
,< RI2
5poo( 15,000

:,~ooc 15,000

~R20
100,000

,~g~:62

I~ 15,000

~~o

B-15V

-- I - - )F
RII

:I~OO· 15,000
p'!'6

...

UNLESS OTHERWISE INDICATED'
RESISTORS ARE 114W; 5 %
CAPACITORS ARE MMFD
DIODES ARE D-664

.....

C2
0
119

?3.2

.. t

D55

R23
(:~O 15,000

p!3

,....

p.!:.

(

D"':O •

....

s"" ~9

--j~~'

D58

,....

R25
( 1,500

o..!,2

,....

(

L---

l{jO

p'!'s "v

,....

*'D62

Dual Flip-Flop

R205

A+IOV (AI

---<>

r------3V
,

IbO

~:~~I
D3 ~ D9 ....
R2
I!!,OOO
5% C2

J...~

~
!!

'D~ ~.D8""

RI
15,000 5%

....

~ ~9

4~0;6

D26

....

~~
,..
... J~""

H ~e
D22
~25

R 16
10,000

......

D53

C7
330

D4I
D!e

J:.

...

D52

....

042

....

D~2 ~2

tv ~~9C ~
QI

()

....

R 19
47

~D43

0
D,:>

1cB
;;:F'SBO

1!!p00 5%

RI7
7,500
5%

F
()

~~D35

R7
15.0005%

15,000 5%

UNLESS OTHERWIS INDICATED:
RESISTORS ARE 114W\ 10%
CAPACITORS ARE MMFD
DIODES ARE 0-664

-..

1100
032

~~D7

0,!9 N

D~3

RI5

7.g~0

C~
I~O

1,500
~
5%
5%

"13

1~5%

ISPOO 5%

:~ LJP~
eo.-

RI2

R5
15,0005%

R9
15pOO 5%

....

.hb
~4

O.! y- .. 030
...
....
21
j?2';
?,.27
DI!
,..

<;~

E_ . .

R8
I!\OOO 5%

'Ul~

~~~4

~~ g~62
02
DEC

~ 2894-28

..., ;3 ~

D~5

•

g~6e62

...J

1">

C,~

~~D40

.~~

MFD

~r
.0IMFD

1::::::::::;:::::::1

Pu Ise Ampl ifier

6-53

~~~ ~ g~6762 I

R601

~~ g~62

91
~
,....

RIO
15,0005%

Ibb

I
8
STRATE
.J......<)-'5V
I
RI6
1
1,500 1
5%

C GND

0 AHOV
R4
100,000

0-~2 ~2

~ II

--...

DEC
;39C
I\C5
330

03.2

.....

....

RII
15,000

t6.)~
R21

\t:::::

47
10"1.

...

RI4

.01
042 ~ ~
MFD
04
DEC
r
2894-28041 ~

'~D8

'05

....
0;0

"013

R9
15,000

'014

T --

.....

0;;

C3
100

CoN GNO

:~ ,035
0-662

~~ '030

~g~ ~ '02'

~.012

~~Oll

()J

<)R

, ~044

~~O 45

"ro46 , '047

~~ "024

RIO
15,000

( F

~~02

C7:::r: I

MO~O

'~:62

:"
I
1~'0-33
I
0-662
B-15V

.01
t~9
MFO
J'" g~:62

-vU
RIS
7,5004 .031

640

".D2~ 1,500

r---- --1

r:,~0 '

"043

~OO

o.!3

't-

RI7

~X3
0~~2 \!::::::.
D}1

C8
.00IMFO

DEC
2894-28

~l:'
R5
R7
1,500 d3"s ~4 .015

~~Og

R3
15,000

RI
15,000

;;

Ht-o
-I(

R20

1'f3~

~
c.,.

- ..... >~OOO

RI3
100,000

~~,
\t:::::

01
DEC
3639C

.... ....

:g~o

....

0~2

·~'029 -: C6

....

RI8
15,000

I
I
I

6
RI9
1,500
I

I -3V
L~:r_~g_ J

100

026
,•• 028
T

,r048

'r.049

"'050

.----- -----_ ......

UNLESS OTHERWISE INO'CATEO:
RESISTORS ARE 114W, 5 ..
CAPACITORS ARE MMFO
DIODES ARE 0-884

I ------------------}
..........

11'

R602

R3
100,000
5%

\!:::::,

~
~'g:~662

06
,0-662

.. ....
~2 -

~""Oll

R23
4·7

.. r-

C2
330

...~

.. P.!l

pl"\..~

~010

~ ,0-662

( R7 ~ .012

:: ... ~jo

04
OEC2B94-26

P'l

.. ,....

gNHdN,u

10,000

R 25
47

C6
, .... 330

...

~'g~g6

06
DEC 2894-26

~ffoiM~ ,C7

~!3

030
",0-662

RI4 ~ .024
7,500
5%

.. .035

v"
• 5%

,..

~'g:~62

....

~ ·022

-" A+IOV(A)

100,001)
5%

I ....

>~~OOO • I~OO

~7,500

0t!.2

RI2

.5%

l'rl

~
R 24
47

OIB

-" ~-

~ 10,000

Pulse Ampl ifier

~023

~'g-~62

fl':':l
....

....-.-...

R5 )
: ~~OO ( 1,500
~5'11.
( 50/.

'?
br

02
OEC2B94-2B

..............

T
~

C9
01

;;;0

MFD

"g:~6

.01
MFO ~ ,038
0-66

~
,......~

)R21 ~
7,500
5%

(R19 .. • 034
~;,.OOO 1,500
5%

RI6

•

~036

R22
1,500
5%

~'g:~6

8-15V
• RI
C R4 .~ , 09
.'5,000. 15WO
.5%
C 5%
CI

"iP

-*0:4

~
...

045

DI3
L

'D;6

)RII
R8
15,000
5%
C3

~ r 021

RI5
b\OOO

bsr

~""I<

016
..."....

UNLESS OTHERWISE INDICATED'
RESISTORS ARE 114W; 10%
CAPACITORS ARE MMFO
DIODES ARE 0-664
TRANSISTORS ARE DEC 3639-0

R603

'D:

Pu Ise Ampl ifier

6-54

......

028

RI8 ~ '033
15,000
5%

.......

032
R

to"

.....- - ! - - - - < ) B -I!IV

3,000

0111

110

3,000

3.000

C2
.01
0

liFO

C eND

C3
.01
liFO

.01
lifO
07

011

Dl3

-3V

UNLESS OTHERWISE INDICATED:
RESISTORS ARE V4W". II ....
DIODES ARE 0-114

-----------------<II

•

...

W005

...............

II>

Clamp Loads

019

:]11

R32

R24

R27

R31

-------oC
GNO

017
016
-1.5V

UNLESS OTHERWISE INDICATED:
CAPACITORS ARE .01 MFO
RESISTORS ARE 1/4W; 5%
RESISTORS ARE 3,000; 5%
DIODES ARE 0664
TRANSISTORS ARE OEC3639
TRANSFORMERS ARE T2051

015

RIB

011

CI5

014

~ ]11-.........--.-·
7

DB
T

R23

CI6

--+------J04

R6
100
10%

RB
100
10%

RI6

R20

R26

R2B
B

-15V

W640

Pulse Amplifier
6-55

r-------------~~------------_1--------------_.--------------_.--------------~----------_oA

100,000

+IOV (A)

100,000

r---------+---~~--------r_--_1~------_;----_.--------_f----_.--------_+----~-----oC

GND

~
W
'"

U1
0-

o·

Q..

CD
RI
7.500

S.
CD

7,500

RIO
7,500

7,500

R3
7,500

RI6
7,500

~------------~~------------~~----------------------------~--------------~----------_o

UNLESS OTHERWISE INDICATED:
TRANSISTORS ARE DEC3639
RESISTORS ARE 1/4W, 5%
DIOOES ARE D664

USE THE ETCH BOARD OF THE WIOI

I ::::::;:::;;:::::~

DEC FORM NO.
ORB 102

B-15V

~AA+ 1ov (A)
"AB - 15

RI
15,000

R2
IOOpoQ

R3
R5
3,000 15,000

RII
10,000
10%
,n02~

R6
R8
100,000 1,!500
025 ~,

~r04

3~
1\

021

...

,,~ f~,-,-

AR ~...

'02--;
0-662

~ 02

0-662

.....

045

RI5
1,500

039

"o~ 0:j62,-,-

R32
47

1"01~
0-662

;:)~~

10"1.

Alii

•

0-662

C~t?

010

~~060

C9
56

012

R 36
1,500

AK ~ . . . . r-.O~

~'055

3fP

0-;3

047
0:!62...

R37
3,000

R34
3,000

-'-L

R33
10,000

~~0521O"/o

051 ~,
C8

(

R26
R28
R30
15,000 >100,000 >1,500

'~42

0:.s

()

R24
3,000

'----< ~

RIO
47
10%

;:1.~0

I~,~~

R20
15,000

~~034

~'031

~ 03

b~..

RI7
>3,000

0':"9

RI3
3,000

(

013

0
AM

" B0

I
IJ1

'-I

~017

ro -+

~DI6

BE~

(")

(f)

~015
~014

ro
(")

-+-

""1

BM
BN
BP
BR
BS
BT

~013

::=:012

...

:.; 011
~

R4
15,000

R7
100,000

R9
3,000

~'024
~

RI2
15,000

:: 08

::'06

RI6
R 18
3,000 15,000

RI9
,500
100,000 ~~21

'ro 33

......-

041 ~

0-~2 '-'r-.

Or;2
0-662

0;'5

...

036
0-c!6;:'

~037
0-662

AO~

0~9
...

030

~L.66~

., 012
0-662

fP
~

R25
IOPoo
10%
~ ~043

~~p

020

"Jo.lDIO
~ : 09

~ :. 07

toO

;:~~6

R3I
3,000

~'049

...

~~g.sl62
~.g_5~2

...

046

R29
1,500

(

A..I

05
(

~500

"050

R 35

1>44
R23
47
10%

R27
3,000

~.g~l62
'------4

~~g::62

CIO
;: r:.0 1
MFO

011
AF

... 05

BV
-"'AC,BC GNO
UIliLESS

OTHERWISE

INDICATED:

TRANSISTORS ARE DEC 3639
RESISTORS

ARE 1/4 W, 5 %

CAPACITORS

ARE

DIODES

0-664

ARE

MMFO

1------------------1
c . . . . . . . . z ........ z ......... :::J>

DEC FORM NO.
DRC 102

Ale

10 ADDR 12

AL
( 10 ADDII 14

10 AODR 13

AS
910 ADOR 16

10 AOOR 15

10 AOOR 17

AA
+lOV
R2
10,000
10%

R.
100,000

ItS
100.000

RI3

,~ DI7

~..

..... --'-"L

Dil 019
0$82 04162

....

~~I
"
OEC28.4-2a
CLR.
10~8.
~ .. 02

021~

R3
1,500

R8
7,500

CS
100
0,!f

~ '!32

~~ Dill

J.!.3

MMFO

030 011
0862 0682

~ D40
R22
100,000

~ ~DI4
100,000

fin

U7
100,000

.. ... ff:(0'

~O'

.....

041 042
0862 011112

...

044

D~5
r

060
0882

05r

04162

D107
0682

t 047
..:..

"g~:1

~Q14

QI2

OB4

.....

~t100

024

AE
ENS "I"

_F
RI2

RIS

RI7
7,!100

>R18
S,ooo

R20

R21

R25
7,!500

3,000

R28

e5
100

~g:~2

M~~

R30

RS5
1,300

"08.
08S2

DIOI

AD
SELEC

....

"088
0882

R52

RS4

R58

10,000

7,500

08T

ENS"O"
AFa----.

~~g~~~

07i

•• 1'0

lDIl
RII
T,!lOO

~
....,.,..-

QI,

"084

083

.....
~,gg:2

056

... ,gU2

C8
.01
MFO

~~g~0:2

...

RIO
3,000

R45
100.000

R5'
100.000

-.7V

~r
100

.. ...

RI.
100.000

-: C7
- Mc:.IO

....

~
...

RI
3,000

DI2
08112

I" g~1I2

'~027

~O'

010

CI
.001
MFO

RIS
100,000

~IOO,oOO

................AH
f""1'0
SYNC.

072

.......

~0100

rl°63
RS8
3,000

~R41

R44

R48

R4.

7,500

3,000

10..

R31
100,000

R24
100,000

R4S
100,000

R48
100,000

-3V

c R63
3,000 ~ 7,500

R82

R65
1,500
Aa

R57
100,000

0.8"

0.7

.....

CB
100

,4~D99

'r!6

UNLESS OTHEltWISE INDICATED:
DIODES ARE D664
TRANSISTORS ARE OEC3113.a
RESISTORS ARE IS,ooO
RESISTORS ARE 1/4W, 5%

.......

IOPWR.C~

EN. OUT

1
RU
7,!500

F'LG.

"'--1'1...1--+--<--<> IS

034

1t21
7. SOD

0~2 '"""

EN.IN~

D4II~.

oft

04.,4 .,DIII

1t51
8,000

_....t

075

1t84
I,SOD

RS8
7,!500

R40
1,500

R42
7,500

F
R47

rl°85
R50
1,000

R53
5,000

R58

R5.

RBI

1------------------1
OII'u . . . . . . . . . . . . . . . . . . . .

:..

DEC FORM NO.

DAD 101

W104

Device Selector

6-59

-15V

R6
470,000

RI4
470,000

C3
.01
MFD

R22
470,000

+IOV

r-----.-----~--------_;----._----~----_r--------~r_--~----~--._--~~----~~_.~---o~~D

C2
.01
MFD

R3
68,000

-.....,J

RI9
68,000

L----------t--~~--~~----~------------~~----~----~--------------~----~------074---~--+_~-----o_15V

R2
470,000

(I)

<
n

RI7
1,500

RIO
470,000

(I)

VI
(I)

(I)

n-to

Q
R5
1,500

R7
68,000

RI3
1,500

RI5
68,000

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W; 5%
DIODES ARE D662
TRANSISTORS ARE DEC36398

DEC FORM NO
ORB 102

R21
1,500

R23
68,000

R29
1,500

DIGITAL EQUIPMENT CORPORATION. MAYNARD, MASSACHUSETTS
Printed in U.S.A.