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DEC-09-I9AB-D

April 1972

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Document:	DM09A
Order Number:	DEC-09-I9AB-D
Revision:
Pages:	33
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OCR Text

Oigi~al Equipment Corporation

~Vlaynard, Massachusetts

PDP-9
Maintenance Manual

OM09A
Adapter/Multiplexer

DEC-09-19 AB-D

OM09A
ADAPTER/MUL TIPLEXER
MAINTENANCE MANUAL

digital equipment corporation · maynard. massachusetts

1st Pri nti ng October 1968

2 nd Pri nti ng October 1969
3rd Pri nti ng Apri I 1972

The material in this manual is for informational purposes and is subject to change
without notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL

PDP
FOCAL
COMPUTER LAB

CONTENTS
Page

1•

Introducti on

1 .1

Related Documentation

1 .2

Engineering Drawing References

Specifications

2.1

Environmental

2.2

Power Requirements

2
2

2.3

Physical

2.4

Controls and Indicators

2.5

Performance

Installation

4.
4.1

Principles of Operation

4.2

Basic

Detailed

4.2.1

Power Turn-On

4.2.2

Internal Control Pulse Train

4.2.3
4.2.4

Single-Fast-Input Cycle

4
5

Single-Slow-Output Cycle

4.2.5

Double (Back to Back) - Fast-Output Cycles

Acceptance Test Procedure

6.
6.1

Maintenance

General

6.2

Delay Adjustments

6.3

Module Complement

Engineering Drawings
ILLUSTRATIONS

1-1

Basic DM09A System Block Diagram

3-1

Insta Ilati on Diagra m

4-1

Control Pulse Train Circuitry

3
5

4-2

Control Pulse Train Time Relationship

iii

CONTENTS (Cant)

TABLES
1-1

Reference Documents

4-1

Single-Fast-Input Cycle Signal Flow

4-2
4-3

Single-Slow-Output Cycle Signal Flow

Double (Back to Back)-Fast-Output Cycles Signal Flow

6-1

Module Complement

7-1

Engineering Drawings

1•

INTRODUCTION
The DM09A Adapter/Multiplexer an option to the PDP-9 manufactured by Digital Equipment

Corporation (DEC), provides an interface through which three I/O devices may gain access to the
PDP-9 memory via the DMA channel. A basic system block diagram is given in Figure 1-1.

Figure 1-1

Basic DM09A System Block Diagram

This document and the documents referenced herein provide the information necessary for
installation, operation and maintenance of the option. The leve I of discussion assumes that the user
is fami liar with the basic PDP-9.

1 .1

Related Documentation
The DEC documents listed in Table 1-1 contain material which supplements information in

this document.

Table 1-1
Reference Documents

Document Number

Description

PDP-9 User Handbook

F-95

Operation and programming information
for the PDP-9.

PDP-9 Maintenance Manual
Volumes I and II

F-97

Operation and maintenance information
for the PDP-9 including basic PDP-9
engineering drawings. Basic DM09A
theory of operation.

DIGITAL Logic Handbook

C-105

Specifications and descriptions of most
FLIP CHIP modules used in the DM09A.

Title

1 .2

Engineering Drawing References
Engineering drawings wi II be referenced using an abbreviated code. As an example,

drawing D-BS-DM09-A-2, DMA Adapter Multiplexer Control, sheet 1 of 2, will be referenced as
[DM-2(2)] •

SPECIFICATIONS

2. 1

Environmental
The DM09A consists entirely of modules of the type used in the PDP-9 central processor.

Therefore, PDP-9 environmenta I specifications apply to the DM09A.

2.2

Power Requirements
The option obtains a II necessary operating power from the PDP-9 power supply system.

No additional power supplies, power control or fan assemblies are necessary.

2.3

Physical
The DM09A consists entirely of modules which are housed by two DEC standard 1943 mount-

ing panels, thus requiring 10-1/2 in. of mounting space. Placement of these panels is given in Section 3, IN ST ALLATION •

2.4

Controls and Indicators
No controls or indicators are associated with the DM09A. The option is entirely under the

control of the PDP-9 and the I/O devices.

2.5

Performance
The multiplexer operates at two speeds. I/O devices with 10 mHz ·Iogic may request the

high speed and thus achieve a 1 .,.s/transfer rate; I/O devices with low speed logic should request the
low speed of 3 ~/transfer to permit sufficient data-line settling time. It should be remembered that
the speed range applies only to the DM09A. The PDP-9 DMA channel and the memory require only
1 .,.s/transfer.

INSTALLATION
Implementation of the option involves insta II ing the option modules into their preassigned,

prewired locations in the basic PDP-9 cabinet. The location in which the option mounts is shown in
Figure 3-1 •
RESERVED
FOR
DM09A
RESERVED
FOR
ME09B
PAPER TAPE
READER AND
PUNCH
OPERATOR'S CONSOLE
TABLE

Figure 3-1

Insta Ilation Diagram

The following engineering drawings provide all necessary interface information.

Draw i ng Number

Title

D-CD-DM09-A-9 (Rev. A)

Memory Interface

Interface between the DM09A and the basic
PDP-9 memory.

CD-D-DM09-A-10

Interface Cabling
DM09 Memory

Interface between the DM09A, ME09A memory
extension control and MM09A extended memory
bank.

CD-D-DM09-A-11

Cabling DMA
Inter-Memory

Interface between the MC70B basic PDP-9 memory
and MM09A, Band C extended memory banks.

PRINCIPLES OF OPERATION

4.1

Basic

Description

A basic description of DM09A logic operation can be obtained from Section 3.8.3, DMA
Channel Transfers, of the PDP-9 Maintenance Manual, Volume 1. A detailed DM09A block diagram
is also contain in that section.
This document describes in detai I the operation of the DM09A DMA Adapter/Multiplexer.

4.2

Detailed
A variety of transfer type combinations are possible with the DM09A. To avoid excessive

repetition, only three types will be described herein; Single-Fast-Input cycle, Single-Slow-Output
cycle and Double (Back to Back)-Fast-Output cycles.
Certain DM09A operations are executed regardless of transfer type; namely, control circuitry
initialization via power turn-on and interna I DM09A control pulse train generation. Transfer type
descriptions assume I/O device 0 is being acted upon. All reference will be made to I/O device O.
Similar operations wi II result when any other device is acted upon.
All transfer types can be thought of as consisting of a number of "time states" each commencing with a PDP-9 ClK pulse. Single transfers consist of time states in which either an I/O device is
made ready, in which a device is synchronized to the PDP-9, or in which a data transfer takes place.
With multiple transfers, synchronization is established during the previous data transfer.
When reading the logic descriptions, the user should refer to the engineering drawings
referenced on the signal flow tables. In addition, DM09A timing diagrams, drawings DM-8(1) and
DM-8(2) should be referenced for specific timing information.

4.2. 1

Power Turn- On
When the system is first turned on, PK ClR (power and key clear) pulses arrive at the DM09A

control logic and produce PWR ClR POS (power clear positive) pulses to condition the control logic.
The operations performed are as follows:
Clear SYNC 0
Clear SET AO
Clear SET DO
C lear DEY 0 CONT
Clear SLOW CYCLE A

4.2.2

Interna I Contro I Pu Ise Tra i n
Following PK ClR, ClK (clock) pulses arrive at the DM09A control logic and are used to

generate an interna I DM09A control pulse train via the circuitry of Figure 4-1.
Time re lationships are illustrated in Figure 4-2. The pulse train is generated whenever the
system is ope rat i ng •

D
D
ClK -----+-----eI

t5en

Figure 4-1

ClK

A PHASE

I
~oon.jl

I
lOAD AMEMA

I
D PHASE

650n.

7OOn.

Control Pulse Train Circuitry

n
n
n

n
n

Figure 4-2 Control Pulse Train Time Relationship

4.2.3

Single-Fast-Input Cycle
The DM09A adapter/multiplexer is uti lized during the memory read/write cycle. During

this time the I/O device break request flag is set providing the DM09A with a CH 0 SK RQ level.
Referring to Table 4-1 and the referenced engineering drawings, internal control logic operations serve
to generate an AM RQ level. This level is applied to the PDP-9 memory control circuitry shown on
drawing D-SS-MC7Q-S-1 (sheet· 2). A ClK pulse marking the beginning of the SYNCING time state
is then produced. During SYNCING, the central processor has access to core memory. ClK, delayed
100 ns, generates SYNC ClK to set the AM SYNC flip-flop in memory control via AM RQ(l). AM

SYNC(l) produces AM SYNC(1)B and AM SYNC BUS(l). AM SYNC(l)B is utilized by CM (control
memory) timing to prevent SM(1) from restarting the CM on the next ClK pulse which marks the beginning of the DATA XFER time state.
The DATAXFER time state is entered via another PDP-9 CLK pulse. ClK, delayed 50 ns,
is POST ClK and resets the MODE flip-flop conditioned by AM SYNC(l). MODE(O) signifies AM
access to memory while MODE(l) signifies CP access to memory. PRE-WRITE OFF of the previous core
memory cycle (SYNCING) sets the MEM DONE flip-flop and produces AM GRANT. If on EAE or an
lOT instruction immediately precedes the DM09A request, AM GRANT is not produced. In this case
AM SYNC(l)B is delayed to generate AM GRANT SMlTD (simulated).
During the current time state, I/O device 0 address bits are present at the input gating
circuitry of the AM REGISTER (refer to drawing DM-3(2». Address bits utilized by a PDP-9 with basic
memory are designated CH 0 ADDR BIT 05 through CH 0 ADDR BIT 17. The bits are applied to the
inverter modules shown. ADDR 0, the result of DEV 0 CONT(O) and SET 00(1), allows the address
bits access to the jam input gates of the AM REGISTER as LAM 05 through LAM 17.
An AMI (adapter multiplexer input) pulse jam transfers the 13-bit address into the register.
AMI is the result of AM GRANT* or AM GRAND SMlTD. The flip-flops designated AMEMA 03 and
AMEMA 04 are used with PDP-9 systems containing extended memory banks. Inverter inputs are CH 0
ADDR BIT 03 and SET AO(l) for AMEMA 03 and CH 0 ADDR BIT 04 and SET AO(l) for AMEMA 04.
lOAD AMEMA jam transfers the extended memory addressing bits into their respective flip-flops. This
pulse is produced 650 ns after CLK by the control pulse train circuitry described in Section 4.2.2.
Following memory addressing, an la-bit data word is jam transferred into the AM REGISTER.
I/O device 0 data word consists of CH 0 DATA BIT 00 through CH 0 DATA BIT 17. The data word is
also applied to a network of inverter modules. The enabling signal is DEV O. The data word is jam
transferred into the AM REGISTER by a second AMI pulse which is produced by AM STROBE.

4.2.4

Single-Slow-Out·put Cycle
Table 4-2 illustrates the signal flow associated with a Single-Slow-Output cycle. The

I/O device is programmed to indicate that an output transfer is to take place, the number of words to
be transferred and the address of the first word, DM09A control logic operations which result from this
type of data transfer are basically simi lar to those of the Single-Fast-Input cycle. The I/O device
requests multiplexer service via CH 0 BK RQ. The control logic proceeds to generate AM RQ and
AM RQ NEG. SYNC 0(1) and CH 0 FAST RQ condition the set DCD gate of the SLOW CYCLE A
*Both may be present but the circuit is a logical OR.

flip-flop which is set by the positive going transition of AM RQ NEG. Following logic operations in
the multiplexer and in the PDP-9, an AM GRANT pulse is issued to produce AMI. With input transfers,
this pulse jam transfers the device supplied address into the AM register. This is not necessary with the
current type of transfer.
Following further DM09A control logic operations, simi lar to those of Single-Fast-Input
cycle, PDP-9 AM STROBE arrives at the DM09A. This pulse is gated with CH 0 RQ IN and SET 00(1)
to produce SAl (sense amplifier input) thus allowing PDP-9 sense amplifier bits SA 00 through SA 17
access to the jam input gates of the AM register. A second AMI pulse is produced at this time to jam
transfer these bits into the AM register.

4.2.5

Double (Back to Back)-Fast-Output Cycles
Signa I flow for the current transfer type is given in Tab Ie 4-3. Initia I signa Is sent to the

DM09A control logic are CH 0 BK RQ, CH 0 FAST RQ and CH 0 RQ IN. CH 0 BK RQ signals the
DM09A that service is requested. This signal and internal SLOW CYCLE A(O) produce SYNC 0 EN to
condition the set DCD gate of the SYNC 0 flip-flop. The 0 PHASE pulse preceding the SYNCING 1
time state sets SYNC 0 to establish device priority. This conditions the CH 0 FAST CLR and sets the
DCD gate to produce AM RQ and AM RQ NEG. AM RQ signals the PDP-9 that a DMA cycle is desired; the computer responds with AM SYNC(l) B.
The A PHASE pulse of SYNCING 1 sets SET AO and generates CLR SYNC. This clears
SYNC O. SET AO(l) and AM SYNC(l)B generate SET DO EN which conditions the set DCD gate of the
SET DO fl ip-flop.
The following D PHASE pulse sets SET DO. SET AO(l) and SET DO(l) produce CLR SLW CYC
EN which with A PHASE, maintains SLOW CYCLE A (0) , a characteristic of fast transfers. SYNC 0 is
set again because SLOW CYCLE A(O) and CH 0 BK RQ are sti II present. Setting SYNC 0 generates
another AM RQ signal. Because this signal is applied to the PDP-9 AM SYNC flip-flop prior to SYNC
CLK, the flip-flop remains set.
The PDP-9 produced AM GRANT arrives at the multiplexer control circuitry as the DATA
XFER 1 and SYNCING 2 time states are entered. The pulse jam-transfers address information into
the AM REGISTER. During these time states the data transfer associated with the preceding syncing
operations, and syncing operations for the next data transfer take place.
AM STROBE arrives from the PDP-9 and generates SAl and AMI, thus allowing the sense
amplifier bits, SA 00 through SA 17, access through the AM register gating circuitry and into the
AM reg ister •
DATA XFER 2 is entered. SET AO is cleared and operations similar to DATA XFER 1 take
place to jam transfer the data bits of the second word into the AM register. The 0 PHASE pulse at
the end of the current time state clears SET DO.
7

Table 4-1
Single-Fast-Input Cycle Signal Flow
Time
State

Control
Pulse

D PHASE
SYNCING

A PHASE

D PHASE
DATA XFER

A PHASE

D PHASe

Signal
SYNC 0 EN
SYNC 0(1)
AMRQ
AM SYNC(l)B
SET AO(l)
CLR SYNC
SET DO EN
CH 0 FAST CLR
SYNC 0(0)
SET DO(l)
CLR SLW CYC EN
AM GRANT
CH OADDRACC
IN
DEY 0 CONT(l)
DEVICE 0
SET AO (0)
CH o ADDRACC
SLOW CYCLE A(O)
AM STROBE
CH 0 DATA RDY
IN
INH 0 DAP(O)
CH 0 DATA RDY
CH 0 DATAACC
seT 00(0)

Conditions

Drawing
Number

CH 0 BK RQ * SLOW CYCLE A(O)
D PHASE * SYNC 0 EN
SYNC 0(1)
From PDP-9
A PHASE * SYNC 0(1)
A PHASE * AM SYNC(l)B(B)
AM SYNC(l)B * SET AO (1)
CLR SYNC * SYNC 0 (1)
SYNC 0(1) * CLR SYNC
D PHASE * SeT DO EN
SET AO(O) * SET DO(l)
From PDP-9
A PHASE * SET AO(l) * SeT DO(l)

DM-2(2)
DM-2(l)
DM-2(2)
MC-l(2)
DM-2(1)
DM-2(2)
DM-2(2)
DM-2(1)
DM-2(1)
DM-2(1)
DM-2(1)
MC-l(2)
DM-2(1)

CH 0 ADDR ACC IN * SET DO(l)
DEV 0 CONT(l) * seT DO(l) * CH 0 RQ IN
A PHASE * SYNC 0(0) * SET DO(l)
CH 0 ADDR ACC IN
A PHASE * CLR SLW CYC EN
From PDP-9
D PHASE * SET DO(l) * SLOW CYCLE D(O)

DM-2(1)
DM-2(2)
DM-2(1)
DM-2(1)
DM-2(1)
MC-2
DM-2(2)

CH 0 DATA RDY IN
CH 0 DATA RDY IN
D PHASE *CH ORQ IN * INH 0 DAP(O)~ S~T qO{l)
D PHASE * SET AO(O) * SLOW CYCLE 0(0)

DM-2(2)
DM-2(2)
DM-2(1)
DM-2(l)

Table 4-2
Single-Slow-Output Cycle Signal Flow
Time
State

Control
Pulse

SYNC
D PHASE

SYNCING

A PHASE

D PHASE
DATA XFER

A PHASE

Signal

Conditions

CH 0 BK RQ * SLOW CYCLE A(O)
D PHASE * SYNC 0 EN
SYNC 0(1)
SYNC 0(1) * CH 0 FAST RQ * AM RQ NEG ... 0
From PDP-9
A PHASE * SYNC 0(1)
A PHASE * AM SYNC(l)B(B)
AM SYNC(l)B * SET AO(l)
CLR SYNC * SYNC 0 (1)
CLR SYNC * SYNC 0(1)
D PHASE * SET DO EN
From PDP-9
A PHASE * SET AO(1) * SET 00(1)

SYNC 0 EN
SYNC 0(1)
AMRQ
SLOW CYCLE A(l)
AM SYNC(l)B
SET AO(l)
CLR SYNC
SET DO EN
CH 0 FAST CLR
SYNC 0(0)
SET DO (1)
AM GRANT
CH 0 ADDR ACC
IN
DEY 0 CONT(1)
SET AO(O)
CH 0 ADDR ACC
CLR SLW CYC EN
SLOW CYCLE A(O)
AM STROBE
AMI
SAl

CH 0 ADDR ACC IN * SET DO(1)
A PHASE * SYNC 0(0) * SET DO(l)
CH 0 ADDR ACC IN
SET AO(O) * SET D(1)
A PHASE * CLR SLW CYC EN
From PDP-9
AM STROBE + AM GRANT
AM STROBE * CH 0 RQ IN * SET DO(l)

SET DO(O)

D PHASE * SET AO(O) * SLOW CYCLE D(O)

Drawing
Number

DM-2(2)
DM-2(1)
DM-2(2)
DM-2(1)
MC-l(2)
DM-2(l)
DM-2(2)
DM-2(2)
DM-2(1)
DM-2(1)
DM-2(l)
MC-l(2)
DM-2(1)
DM-2(l)
DM-2(1)
DM-2(1)
DM-2(1)
' DM-2(1)
MC-2
DM-2(2)
DM-2(2)

D PHASE
DM-2(1)

Table 4-3
Double (Back to Back)-Fast-Output Cycles Signal Flow

Time
State

Control
Pulse

o PHASE
SYNCING 1

A PHASE

o PHASE
.....

DATA XFER 1
SYNCING 2

A PHASE

o PHASE

DATA XFER 2

A PHASE

o PHASE

Signal

Conditions

Drawing
Number

SYNC 0 EN
SYNC 0(1)
AM RQ
AM SYNC(l)B
CLR SYNC
CH 0 FAST CLR
SET AO(1)
SET DO EN
SYNC 0(0)
SET 00(1)
SYNC 0(1)
AMRQ
AM GRANT
CH 0 AODR ACC
IN
CH 0 ADDR ACC
OEV 0 CaNT (1)
AM STROBE
SAl
SYNC 0(0)
CH 0 FAST CLR
CH 0 DATA ROY
IN
CH 0 DATA ROY
AM GRANT
CLR SLW CYC EN
SLOW CYC LE A (0)
CH 0 AOOR ACC
IN
CH 0 AODR ACC
AM STROBE
SAl
SET 00(0)

CH 0 BK RQ * SLOW CYCLE A(O)
o PHASE * SYNC 0 EN
SYNC 0(1)
From POP-9
A PHASE * AM SYNC(l)B(B)
CLR SYNC * SYNC 0(1)
A PHASE * SYNC 0(1)
SET AO(l) * AM SYNC(l)B
CLR SYNC * SYNC 0(1)
o PHASE * SET DO EN
o PHASE * SYNC 0 EN
SYNC 0(1)
From POP-9
A PHASE * SET AO(l) * SET 00(1)

OM-2(2)
OM-2(1)
OM-2(2)
MC-1(2)
OM-2(2)
OM-2(l)
OM-2(1)
OM-2(2)
DM-2(l)
OM-2(l)
OM-2(1)
OM-2(2)
MC-2(1)

. ,

CH 0 ADDR ACC IN
SET 00(1) * CH 0 ADDR ACC IN
From PDP-9
CH 0 RQ IN * SET 00(1) * AM STROBE
CLR SYNC * SYNC 0(1)
CLR SYNC * SYNC 0(1)
o PHASE * SET 00(1) * SLOW CYCLE 0(0)
CH 0 DATA ROY IN
From PDP-9
SET AO(O) * SET OO( 1)
A PHASE * CLR SLW CYC EN
A PHASE * SET AO(l) * SET 00(1)
CH 0 AOOR ACC IN
From POP-9
CH 0 RQ IN * SET 00(1) * AM STROB'E
o PHASE * SET AO(O) * SLOW CYCLE 0(0)

DM-2(l)
DM02(l)
DM-2(l)
MC-2
DM-2(2)
DM-2(1)
OM02(1)
DM-2(2)
DM-2(2)
MC-2(1)
DM-2(1)
MC-2(1)
OM-2(1)
OM-2(1)
MC-2
OM-2(2)
.OM-2(1)

ACCEPTANCE TEST PROCEDURE
Acceptance testing of the DM09A option consists of executing Test Procedure DM09A-O

with the DM09A Tester at both normal operating conditions and the voltage margins specified below.
Aggravation
Condition

Trial

Test

DM09A-O

None

DM09A-O

Margin rack A

DM09A-O

Margin rack B

Minimum margin specifications for rack A and rack B are listed below.
Margin
-15V

+10V

+6V

MAINTE NANCE

6.1

General

+4V 1-4V

-6V

The general maintenance procedures described in the PDP-9 mainteoonce manual also
apply to the DM09A option.

6.2

Delay Adjustments
Adjust the R302 Delay at A27 according to the data given on engineering drawing DM-2(2).

603

Module Complement
Table 6-1 lists the module complement of the DM09A option.

Table 6-1
Module Complement
DEC Type

Module Type

Quantity

Recommended Spare Quantity

8169

Inverter

8213

Jam Flip-Flop

R002

Diode Cluster

R111

Diode Gate

S107

Inverter

S202

Dual Flip-Flop

S203

Triple Flip-Flop

5603

Pulse Amplifier

Woo5

Clamped Loads

W300

Delay Line

W612

Pulse Amplifier

R302

One-Shot Delay

*Contained in the basic processor spare parts kit.

ENGINEERING DRAWINGS
Table 7-1 lists the DEC engineering drawings associated with the DM09A option.
Table 7-1
Engineering Drawings

Drawing Number

Title

Revision

DM-2(1)

DMA Adapter Multiplexer Control BS-DM09-A-2 Sheet 1 of 2

DM-2(2)

DMA Adapter Multiplexer Control BS-DM09-A-2 Sheet 2 of 2

DM-3(1)

AM Register BS- DM09-A-3 Sheet 1 of 2

DM-3(2)

AM Register BS-DM09-A-3 Sheet 2 of 2

DM-4(1)

Cable Diagram BS-DM09-A-4 Sheet 1 of 2

DM-4(2)

Cab Ie Diagram BS- DM09-A-4 Sheet 2 of 2

DM-5

Module Uti lization MU-DM09-A-5

DM-8(1)

DM09A Timing Diagram TD-DM09-A-8 Sheet 1 of 2

DM-8(2)

DM09A Timing Diagram TD-DM09-A-8 Sheet 2 of 2

0 ADDR Ace ~N

CH I AOOR ACC XN

CH 2 "'OOR Ac.e IN

D
CH ¢

AClOR ACC

CH I ADOR

ACC

CH 2. AODR ACC

SeT A2(1)
SET D 10). L

CH (/J O"TA ACC

CH 0 RQIJN-~-=-t~ N' 1\ I

SET 02(1)

we(i1S
CI9

A PH,AS£ K

SLOW'· CYCLE 0(1)

:It

.AI PIfASF --t>I5~-«52'1

ACC

CH 2. DATI>. ACe

Wal05

vrfJr,Js

el9

CI9

PWR' CLf{ POS-~::r'""-...:..O.,.....

C.H Z RQ IJi'---.-:v----'-"'I

011 Rq IN

11 PHIISE

flMRQ-'IEG.

SLOW CYCLE 0(1)

CLR

A PHASE

CH '2. F .....ST C.LR

o;:;,ET 0 (6(1)

CH 2.

PWR

CLR

PO~ ~~UL~~-L----~~~~~~----~~fU~~~----~~~~~~-------~~~~~~~______~~~~~~

D PHASE
CL R

'5YN C .:::..{;tg;J----+----------....:.N~Zl---_+_---------'::O"018J

~------_+-------_+--OCLR

:SET 0 Z.(I")
SYNC 1])(1)

:SYNC. 1(1)

:SYNC eel)

CH ¢ DATA ROY Ij,j

CH I DATA RD,{ IN

CH If> AOOR. ACe. IN

CH 2 Oo'o.TA RDY IN

CH I "OOR Ace. IN

SL VI' eye EN

SETIl~(I)
SET D '1(1)

CH Z ADDR ACC IN

BS-DM09-A-2 Sheet 1 of 2 DMA Adapter
Multiplexer Control

SET D 2

E.N

AM RQ. NEG.

~---'--':'-=-.IrN7\l--.AM SYNC(I)S(e.)

SYNC ¢ (I)

SYNC. I (I)
DEVICE ~

SYNC.

e \;:N
SYNC e(l)

CH ~ RQIN

6K RQ

DEV 'Ii CONTROL(t)
SE.T D¢(I)

RDY

CH ~ DATil RDY IN

AMI
H

DEVI(.\;'
CH I RQ IN

•

DEV 1 CONTROL(I)
SET

o I (I)

.11M G.RIjNT
SMLTD

SAl.

WI!J¢5
1'.2.3

I.. 011 D
.IIMEMII

CH a RQ IN

1\
V

I'lM SYNC(I)B---£~~

DEV a CONTROL(I;
SE.T D 2.(1)

CHa1RQTI'l

I1DJUST AM GR/Jf(T SMLTO

TO occuR AT AM GRIII"r
TIME.

B
PWR ("LA. p05
SYNC Z (¢)

'" PHASE (6)
A f>HjI,.SE

PK CLR
ISqI./I..

snlC 2. (91)

BS-DM09-A-2 Sheet 2 of 2 DMA Adapter
Multiplexer Control

SAO"
SAl

a DATA-BIT()0'
DEY fI

CH I ~TA-BIT0'0'

DEVI

CH 2DATA-BlT~

c
C

=NOTE:
loon,

tw,

-=-

10". TERM I NATORS TO GROUND

MUST BE PUT ON SA!Il0 THRU SA 17.

loon

8
SA 12
SAl

01 0 DATA-BIT 12
DEv0
CH I {)I.TA-BIT 12

DEVI
CH 2 DATA-BIT 12

-=-

BS-OM09-A-3 Sheet 1 of 2 AM Register

fM
D

i-C~J

AYE",A
LAM £15

CH0ADDR
BIT 05

CH (\ ADOF\ 81T03-

SET A0111
CH I ADDR BIT 03

CHIADDR
BIT 05

CH I AODR S
BIT 04

SET AI II)
CH 2 ADDP. 81T03

CH 2ADOR

IIj

CH 0AODR
BIT 06

CH2AOOR V
BIT 05

BIT 04

LAM (67

CH '" ADDP
BIHJ7

IIj

LAM~9

LAM 08

CH0ADDR
BIT 08

CHI2lADDR
BIT 09

CHi2IADDP
BIT II

CH 0ADDR
BIT IfIJ

CHIADDR
BIT 06

CHIADDR
BIT 1217

CHIADDR
BIT 08

CHIAOOR
BIT 09

CH 2 ADDR
BIT 06

CH 2 AODR
BIT 07

81T 1iJ8

CH 2 ADDR V
BIT 09

LAM 13

LAM 12

LAM II

BIT II

CH I ADDR
BI T 12

CH I ",uDR S
81 T 13

C H 2 ADD ~ V
BIT II

81 T 12

C H 2 A DOR V
BIT 13

CH 2ADDR
BIT 10

DDI\

SET A2 III
M

-=-

':'

-=-

C
W!1l05
'A23

LAM 14

ADDR iJ
CH I J.OORBIT 14

C'" IAODR
BIT 15

ADDR

LAMI7

ADDR fJ

ADDR I

ADDR

DEV

CH2 ADDR V
BIT 15

CH2 ADDRBIT 14

LAM 16

(H0 ADDR
BI T ,5

:H0ADDR BI T

ADDR

LAM 1'5

CH2ADDR V
BI T 17

SET 0 0( I )-,--T.-."" - "

SET 0 2 (I)

,H-,-~--,.,------,K

BS-DM09-A-3 Sheet 2 of 2

AM Register

G795

W(/J33

AIS

A(/JI

W(il33
A02

CLK

SA 1/J0

CH ¢ BK RO

AM SYNC(I)8

RO IN

AM RO

AM GRANT

PK CLR

1/J5

f/JI

~~~: :~~
DATA ROY

AMEMA 03(01--.1.,----1..

FAST RO

AM STROBE

(/;7

SA 17

V
AMEMA 04 (0} ........" __+-_t-e

CH 0 FAST CLR

*
W¢31

W031

D08

013

USED FOR TERMINATION ONLY NOT A CABLE.(OPTIONAL)

W¢31
DI/J2
rJj'

W!2l31

A03

CH rtJ 8K RQ

AM f/J0 (I)

AM (/J(/J (I)

CH 0 RO IN

CH I BK RO

CH ¢ FAST RO

1/J2

RO IN

CH I BK RQ

CH I RO IN
CH I FAST

W031
006

WI/l31

(0'

(!5'

010

!/J4

-P

DATA

CH 2 BK RO

f/J6

CH 2 FlO IN

--..

FAST RO

AM (jI8 (I)

'-"
(CH I)

(CH 2)

CH 2 FAST RQ

CH I FAST

AM 08 (IJ

--"T

'-"
t::Hc;J)

Wf/J31
DI2

09 (I)

(CH 2)

W¢31
0~J7

W031

DII
NOTE:

AM ¢9 (Il

PINS C,F, J,L,N,R,U

Ic;l

ARE GNO FOR ALL
w031's AND WI/J33'S

CH 2 BK RO
RO IN

ADOR ACC

DATA ACC

FAST

(CH r)

CH 2 FAST CLR

AM 17 (Il

AM 17 IJ)

BS-DM09-A-4 Sheet 1 of 2

Cable Diagram

D
iW~¢Io-·'
I

c'"' \" C'f-Tf- a,T ¢¢

cf> I

ClIO

W031

W{!I31

: CQlI

- - , - - -......, .

CH ¢

q)'2. . --:----~ ~

r-.1)t:>R SI\" QJ9

cb~ ..........;---....:...;...~

I-!

<:bch

(M. .

-'--+--''"""'1eI •

12-

1'2..

PI
\<,
--;--~I~·

¢~

RI
M
- - - . - - -....
1 .. •

¢a,-

,: ~

¢.-, ---:-I---~·

1<0

--;--.,:.:-.1 •

I
V
¢B -7--.........,,....
1

CI4 0 DA,"" S\, 11

---'-I--~I"·

L _ _ _ .....l

I/J\

--;--~I,.

I'::>

IJI

\<0

CI-I(/) "-OOR SrT ¢s

CH (/> M)DR. SIT \"7

rw¢¢i5il
: CI<O
¢9

--,----1,....
L:

I(j,

--;--~;...IItI.

---:----I~·

¢~

1'2.

--;--"R~IItI:-,

cpa,

1<+
5

--;--....r...,

\10

CH \ "'DD~ '0\\ n

F'I

~:
---:----,....
. ,-I -;:,
p

---:----:...,I~·
\}I

"::

--;----I~·
\/1
V

-+---~.

....
-'----....·
....
--:----.....
....
-'----.
FI

¢ro

.........,...--_-41

¢"1

--;----.

-;----~.

IZ.
\~

.........,...---.

CI-l \ 01>.,,,", '0\\ ~'e,

1-1

\-\

-;:.

"'-

~--~I"·
-;-~:-:-..J~I~ •

---'-1----4~i~

LC~':_J

c.¢'7
CI-! I I>.DDR BIt

I~/lr-pl

I--'A-?: ~!
\(j) -:---~.'

iwa'>c:t>:. I

W~31

(It..:

: ':;."/;'<>

CH 1 D"-,,,, an' t:p9

EI E
-;---~I" •

¢'O

1wcbct>=- ~
L~~ __ J

CH I ,t..ODR EIT

CH I Di'.T~ 51\

--:--+-'-....
1 eI •

¢5 ~--"----;-<"
¢/&
~
CH (/J DI>.TA BIT

I ell

¢a,- -;-----=~

rw~¢~-;tl

lC{N

CIjZI~

-!..--~~.

'I! V
--'----,...
___ J

CI4 2. DATA. SI\"

¢¢
q,\

¢'2..
O~

I
I

,,-I '6.
-";'--~I'-44 •
1""1

rvj~¢5"""il

W¢31
c.¢"?J

1-1

--,---_1'-44 1-11
K

-..;.----I~ •
J,
M

I CIS

CH2. D"""''''' BIT o;zl'?J

1-1

1-\

...........:.--~-41.

\'2.

-;.--

\'4

--i----~.

<$'1

.
Rl

\q,

d>s

Li '5
¢xe. ...........:._--,....

W(ll31

¢4 - " ; ' - - FI:-4oI\'(1

I W031
I CI~

....T:ul,.-K

--;----1-41

:
Ml T
I
NI V
--i-I---I~ •

CHZ Dt>..\"A. BIT ¢-e, -..;._ _..N...;.;I'-44 ~
L ___

I
CH Z. ADDR. BIT ¢~

Iq,

•

12-

... -

Iq.
IS

--;----,....V

<:"IZ-

•

-;----,....

.........,...--_.-

CH 2. t--DDR B\\" ¢~

·M
-;---~I·101
P
-;---"I~
1-\1
'5

-;----~I

I W<!S31

CH '2. ""DDR.

-;:r.::-:-=--=-~-:::l· •
I

--,---+-'-"" •

fW"0-~5~

I CI'::.

ell

\(0

CH Z. I>..t>OR e l l \ I

---:---FI~·

__..T-,-,I,.;

.........;.--..ul
--.---,,....

T
v-:,...~

L ___~

iWci>¢5 :

LC~:""'_J

B
·OPTIONAL CLAMPED LOADS.

BS-DM09-A-4 Sheet 2 of 2

Cable Diagram

11833

1833

U33

W~33

'lYJL33

~213

Jl1ll Jl213

8213

B213

&213

s~n"

1.12

HII:

Kill

_~'7

~2~

_1!J11

ClM

2QL

A2111

All

III

11.

All

8-2

9-17

(,21-8

9-17

,,.
All

CONT.

All

,1.8

AM
12

All

AlII
14

,81

AM
'5

All

A1811

r--

All
SJI

---'-'-

~169

--"-169

LAM

iAMEMA

118

112

(63

8189

8169

8189

9169

B189

9189

B 69

8119

9189

l¥l-

LAM

LAII

LAM

LAII

LAM

,84

liS

III

'---

:A PHAS

8213

ADDR

lDOR DEVICE r - 1

l18li2

c
LAII

B7JI't

111

J~4 J

2
W0.31

W031 W~31

B28v

r----

r--

IAMEMAj LAII

LAII

LAM

LAII

LAM

LAII

LAM

.07

,89

1.3

ADOR
I-- ~i7ii_

DATA
BI T

'K~31 jWl2l3

'K0M U't£l~J

CHB

8-8

ADDR
BI T
3-8

DA.TA
BIT
9-17

ADDR
BI T
9-17

8
W~ 31

IW031 W031

W031 IW0.31

l1li5" l1li5 • 1 _ -

l1li5"

_5"

l1li5" _5

19
~

--"'I2.l
ClIBS

f----

DATA
BIT

11-8

I DATA
BI T
9-17

ADDR
BI T
3-8

AD DR
BIT
9-17

DATA
BIT

'-8

DATA
BIT
9-11

ADDR
BIT
3-8

ADDn
BIT
9-17

CH
'.
AODR
BITS
83-11

CH 1
AOOR
BITS

83-11

CH 2
AODR
BITS
83-11

CH,
CH 1
DATA
DnA
BITS
BITS
18-14 ,88-14

CH 2
DATA
BITS
,88-14

B
W~31

4--

SPARE

W£l31

W031 WIZ'31

1831

We:J31 W031

CH 1

All

1-8

9-17

(NEG)

1831

(NEG)

CONTRO
SIGNAL

AM
SPARE

,8-8
(NEG)

CONTRO
All
9-17 SIGNAL
(NEG)

All
SPARE

lI-a

(NEG)

1831

W612

G7115

eH
AM
ONTIIOL' ',1,2
9-'17 IGNALS LEYEl
TERM
(NEG)

CH ,"
ADDR
ACC

W612

CH 2
AODR
ACC

'612

CH 1
AODR
ROY

WU2

CH.
FUT
CLR

20 21
~

r--

CH I
AOOR
ACC

eH '.
DATA
RDY

CH 2
DATA
RDY

CH I
FAST
CLR

Ol8F

B27D
92711
B27R
0240

~
~

913

1612

CH 2
DAn
CLR

CH 1
DATA
ACC

CH·ICH2
DATA
DATA
ACC
ACC

RIll
CH $I
ADDR
ACC
IN

'"~ ~

r-~

S6.0i
CH 0'

SLOW
CYCLE
A

IG~'4

~
25

EN
r----

DEY I

Clf\

- CONTROl

SLW

30 31

--.S2.I.L l..S2I.2.

-.S2U

~?.II?

~?.II7

~YNC

t-~TD
, EN

SET

SYNC

o ,8

A 1

SYNC

SET

SYNC

r- 2 Ell ~E~D_

A 2.

S-6.1II"

Rill

S6!iJ~

S203

f\DY
IN

33 34

rJ<25E_

C2BP

C25P

C27E _

I-SET 0
1 (,n

SEl

CYC
EN

-Rll

CH¢

40 41

CH 2

ONTROl fJ261..

DEY 2

C27P

""~
39

'" '"
~./,/

INH

DAP

J.
OAP

INH

DI71!... DATA
t-°f~ &. D20P.
P.DY
IN

/
D

OAP

'"'"
41

'"'"
43

INH

t-Df~ L D2rdF

ClR

CH I
DI1F _ DATA

OEV ,!

~ll

Rill

r-- CONTROl r - -

SLOWrYCLE

CH I

ACe.

fi!o

OISR_ DATA t-D~~B.. 019P.
f\OY
IN

CH 2

R
Clf\
SlW
CYC

AOOP.
ACC
IN

ADDP.

S7JI':

H!'-

SYNC

CH 1
AOOR AODP.
ACC
ACC
IN
IN
CH 2
ADDR
ACC
IN

SLW
r--- RQif; PHASE r---- r 92. t - - CYC

SPARE ~V~'ir

DI~F

024H
024L
1112

AM
GRNT
SMlT[ ISMlT

~MEMA

I EN

LI.'

SPARE

C2.311

casT
C23N
CBSV
C2.3U
Cl'S SYNC B
C1.IT ISYNC E DleR

33 34

I'tlASE

B21L fllMEMA j'lMEMA

1_5 15603
.C23f
C23L

1::>110 (

B21V

can

~ r-

DEVICE ~EYICE

30 31

Al50

8zl~

r---AllL

1
824P
ISNN

8213

G~~T

r----

8213

~ 1::>61Z'~

r-r--

~~~)1.

r--

919Y

r--

25
-.!W.

AZ8i
I BZ8T
B19J

A17L

~AlIK

24
!i12

F-

r--

R I

23
~5

I!:'~ r---- A
_'2IfI_ SPARE r---

iPHASi
(B)

r-- 2

B19L

8169

(I)

f - - r-A1BR~ AleF

I
B169

All

r - - SYNC

AIIH ""' 18S _

A23F

rsYMC fMi~

r--

ONTROL
FROM
E/IORY LEVEL
TERM.

MEM.
All

All

FRO!,!
AM

~'"I"'~

• OPTIONAL MOOUlES.
NOTE: FOR IIODULE COIIIT SEE A-PL-DI&89-A-5

MU-DM09-A-5

Module Utilization

COMPUTER BASIC. C.YC.LE

SINGLE'FA5T'INPUT CYCLE
SYN IN

SINGLE. SLOW, OUTPUT CYCLE:
SYNCiNG

A PHASE PULSES (i20 NS)

(INTERNAL DM09A)

D PJ-1ASE PULSES (I20NS)
(INTERNAL DM0911)

C.HX 81'1 R~
(F"ROM DEV X TO DIVl09A)

~~J------------------~~-_-_~-L

__~__-3___~-L~_~-~-'--------------------~~-_-_-'~________~/~~/~-----------------

~OW CYCLE (D). 01)( SK RQ (-3)'D PHASE

AM 5 ,(NC (I) B·1l PHASE

SYNCX-I~,--_ _S_Y_N_C._X___O
___________________~r::''---________________________________________~,~---------------------------

AM RGI
(rRO,'vl

----

SYNC X

(INTERNAL DN/0911)

ADDR ACCEPTED X

FAST CLEAR:,

Dl'r') 0 9fi TO ""Etr'ORY)
:

200
NS
MAX

AM SYNC (i) B

200NS--:

~ r---\
f---

MAX

.!!----------.'-L--____________________________ MAX

4_0_0_N_S
__---.----'-'-------'/r'
........
- - - - - - - - - , 1 . . -_______________________

(FROM M£MORYTO DM0911)
YNC X (I)-A PHASE

SErf!

(If'lTERNfiL DM0911)

'--__---'I

'----J
SYNC x(o)· SET D X (I). i9 PHIlSE

CH X FIIST Rq
(FROM DM091l TO DE.V x)
CHXRQIN

(FROM DEV X TO DM0911)

5£TM.A.""("B.~

SET D X
(iNTERNAL D/'IJO 9/1)

SLOW CYCL£:(O)-SETAX(O)'D

SLOW CYCLE
(INTERNAL DM0911)

PHASE
.
-----------------------~

CHX FAST RQ (-3)'SYNC.X(I}·Il'M RG/---3
to 9 /'liS

/lI

TD-DM09-A-8 Sheet 1 of 2
Timing Diagram

DM09A

Ai';, GRANT

U(120 NS)

(F i' (;M ME/IIOR f TO DWi0911)

AM STROBE
(FROM MEMORY TO DM091i)
~SET D X (I)' SET II x{I)· A

ADDR ACC£. PTED (Ui X)

PHIISE

- - - - - - - - - - - t U (320 NS)

(FROM DM09-"l TO DEV X)

_ _ _ _ _ _ _ _ _ _ _----I~ SLOW C yeL£. (!IS) 'SET D X (I). D PHASE.

Dt'iTA READy (U/X)

U(320 N5)

(FROM DM09A TO DEY X)

_ _ _ _ _ _ _ _ _ _ _----I~CHX RQ IN (-3)' SET D )«(1)'D PHASE
CA-:-A ACCEPTED (CHX) .
(FROM DIVI() '7/1 TO DEli X)
C H X IlDOR
(FROM DEY X TO D/Vi091l)

Uf320 N5)
ADPR ACC.EPTED X="

---.l /

' - - - - - - " - - - - - -~'I

DATI'! ACCEPTE.D X

~/~~~~~------------------------------~--~

DATA
(FROM D£V' X TO DM09!1)
CH X

5ET'lS£. /l MPS
((",,<a.VI MEi/lORY TO D1YI0911)

U(320 NS)
AM

STROBE

'~-D-A-T-~-~-~-~I-D----------------~~~;'~~DA~T~A~V.~A~L~ID-----------------------------y

AM LOADED
(F ROM DfYl09fl TO DH X ¢
MEMORY)

~SYNC x-¢

---------------1U(32 0 NSj

C H X FIlST CLEItR

~ ~

GRANT

(FROM DIYl091i TO

~----~--------~

D£V)()

TD-DM09-A-8 Sheet 2 of 2
Timing Diagram

DM09A

lot

r---------------------~~--------------------~~---------------------4~------------~--------OGND

t_--------~~+_--------O +IOV

R4
100,000

R8
100,000

RI2
100,000
CI
.01

.... 0

~------------+_----~----------------+_----~----------------+_----~--------------~----------~~_e-------G-15V

C
.-------------;-~~~--~~GND

R2
100,000

038
0662
037
0662
036
0662

06
0662
05
0662

033
RI7
1,500

No--t...........

RI9
1,500

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W; 5 %
DIODES ARE 0664
TRANSISTORS ARE 2N425e

B-CS-B 169-0-1

Inverter

r-------------------~----------------------------------~._------------------.~------------------------<)A

+IOV

( M GND

r---~._----+_----~------------------~------t_----._--------~~C

GND

RI9
1,000

RI8
100
10%

)
p

R20
6,800

R23
6,800

. "r;

::~fo9~13

:::r-~;
IotMFD

1~~D8

RZ4
100
10%

DI9~~

~~ 020

r-------~--t_------~~--------~~--_+--~~~~~----~._------~--+_----~~~--------~r_-~2~.~~~ .~'g~~2

,,_ID~+-fj;'" ~,~.l

O-......,I-_>-.....

\'-.

R3
7,500

3639B

y1-+-lJ ~~l ~ "'fEj~, -1--,m..l

>:~o

. ~~

M~~ ~~D

RI3

'-.

DEC
3639B

~"~%:" J;"
T

RI4
1,500

RI5
1,500

RI6
750

RI7
7,500

-."

~~~

"% ,,~~':~:~%

R7
1,500

3639B

R21
1,500

DEC
3639B

R27
100
10%
R26
7,500 ()
J

,----4

R28
1,500

R29
>750

R30
>750

L----+-----r-----r--------;-~

-1!lV

UNLESS OTHERWISE INDICATEO;
RESISTORS ARE 114W; !I'
DIODES ARE 0664TRANSISTORS ARE DEC 3009B

B-C5-B213-0-1

Jam Flip-Flop

DID

0664
OS

IiI1

0664

0864
04

0664
08

0684
03

IiI1

0864
07

',:

0864
02

0664
06

0664
01

IiI1
0684

J
I
I
I

B-CS- R002-Q- 1

Diode Cluster

r-----------------------------~~----------------------------~~------------------------------OA+IOV(Al

r------,

r-----------------~------~----------------------_+------._--------~--~I_e--~C
:
I
:

01
DEC3639

DE 3639

GND

:
I

019

o-ee2 ~

I
I

Oil
I
0-882 :
017

I
I

o-el2 :
I

,,0-..........-.

00---..1....,.....
Eo--",~,--ol

De
0-M4
L 0---1....-..--0111

010

0-884

O-ee2 :
I
I

I
I

Oil

I
I

1l1,000

i ~----~--~~----------------~~----~----------------------~~----~------------~~~----~.-~V
-3V
I
I

: _____________
EXAMPLE DGL2 .J:
I..

LSTRATE
______ JI

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W; SOt.
PRINTED CIRCUIT REV. FOR
OGL BOARD IS SIB

B-CS-Rl11-0-1 Diode Gate

r-----------_.------------~------------~------------._------------~----------~._--.--~--------------OA.IOV(A)

.. ------j

r------r----~~----~----~------+_----._------r_----~------+_--~~----r_rr--_.----~~~~~2----4I--oCGNO

08
:
0-662,
09
I
0-6621

010
1
0-662 j

~--~----4-~~~------~_4~_+----~--~--~----~~_4--_+----~--~~~r_--+_~~~--+_.6

011
1
0-662'
:
I

RI5
1,500

I
:

_.'--=+---7-4>------1--0 B -15V
I

-3V
I
L STRATE
______ JI

R22
:
15,000 I
I

____ .JI

M
UNLESS OTHERWISE INDICATE 0:
RESI STOfIS ARE 1/4 W; 5%
DIODES ARE 0-664
TRANSISTORS ARE DEC 36399
PRINTED CIRCUIT REV. FOR
OGL BOARD IS SIA

B-CS-S 107-0- 1

]~O 43

~~044

~~045

I--OE

I-()L

~~46 4 ~049

Inverter

~~047

~~048

~~050

,... A.IOV(A)

----R4
100,000

"'04
CI
';.1

...

~l
1\

...

~~~ '
F ..

08
R3

~IJ 09,H

Oil

~~
1\

rP14....

~ f-0-662
.. ~ '8~62

~ '8~62

?J
.....
RI
12,000
10%

r080,ooo~ '016

~'025
C3

....

rozo
...

...

~~07

R5
3,000

R6
3,000 ~~012

12,g~/~

~..

OTHERWISE

0";'4

.a .. ~ '8~~62

~ '8_ l62

...~

Ot7
R 13

"9T 1 S

0-662
3

RI7

....

12rg~~

RII
12,000
10%

R 12

121g~/~

.4. 026

D51

INDICATED

RI5
3,000

....
052

TRANSISTORS ARE DEC 3639C
RESISTORS ARE 15,000
RESISTORS ARE 114W\5%
CAPACITORS ARE MMFO
DIODES ARE 0- 664

B-CS-S202-0- 1

Dual Flip-Flop

1~,g~262

0j7

....

~, g~~2

030

?;.I
RIO

,... C GNO

~ ,0:B'

UNLESS

:b'g,ooo~ '035

~~~~ , \1
v

...

R2
12,000
10%

R 14
100,000

RI6
3.000

~~D31

~,g~~62

...

RI9
12,000
10"1.

C5
.01
MFO

:.::

R20
12,000
10%

g:~62
~

~
1,500

B-15V

A.IOV(A)

C GND
046
0-662
0411
0-662
044
0-662
043
0-662
B-I!5V

R211
1,Il00

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W; 5"1.
CAPACITORS ARE MMFO
DIODES ARE 0-664
TRANSISTORS ARE DEC 3639C

B-CS-S203-0-1

Triple Flip-Flop

A-IOV(A)
R3
IOODO
5"1.

~
.....,

,,~Oll

...

R 23
47

DEC
\b 2894-2B

....

R2
15pOO
5"1.

R5 ..
I,!SOO
5"1.

_ ~1
P

~010

R 7 ..
3,000
5%

:~4

~'8~~62

)

...

..012

10,000

M
()

RII

V-

~ ~024

~ .022

...

RI4
3,000
5"1.

GND
,,040
0-66

~ ~g~2

C,H,N.U

10,000

:~5

~'8~~62

0.1.2

RI2
1.'500
5"1.

-..

DEC
\b. 2894-28

...-

....

4 ~D35

15%

~_~'62 ....-;:: : : iio
R9
15,000
5"1.

100,000

;:r-i~o

~~023

t¥ 03

Ojl

,'8?662

J~ ~

~-2,ooc

10,000

,,&..6662

'~!

RIO

....

;;:

...

1'-----4

~~~oo
5"1.

RI9 ..
1.s00
5%

R 15

RI8

2iit2B

:::i~o

)

.034

R21 ..
3,000
5%

~036

.01

~t
~

"g~:6
C7

MFa;: =-..01

MFO ~

.--

~8:36

,,037
0-68

R22
ItlOO
5%
B-15V

.....

~'D44

~09
RI
R4 '
12,000 ~2d/~00
5"10
CI
B~,
1\

,...

O...!

~20&200
0
)

f"'IIJ

"045

L
) 0':"3

~ '021

~2~~00

~2~00

..,

'''046

0..!.8

...

C3
DjO

,....-

"047

...

8~1

"04B

UNLfSS OTHERWISE INOICATEO
RESISTORS ARE 1/4Wi 10"10
CAPACITORS ARE MMFO
010 OE S ARE 0 - 664
TRANSISTORS AR E DEC 3639-C

~A7.°0

C5
0':"5

f"'IIJ

B-CS-S603-0-1

~ '033

Pulse Amplifier

.........

032

R
()

~~049

r------,

r-----------~--------_.--------_1~------~~--------~--------~~------~._--------~--------.--~~--~,------Os-lev

,
,
I
I

5,000

R8
3,000

R8
5,000

02:S
I
0-862 I
I
022
I
0-862 I
I
021
I
0-682 I

[10

C2
.01
IIIFO

III

020 I
0-882:

L2 -----t

t-----~._----~~--~C

018

GNO

0-e82:

0-'.82 1
I

1111'1>

017
I
0-882 1
I
018
I
0-e821

.01

.01
IIIFO

,
I

I
I

,
I

UNLESS OTHERWISE INDICATED:
RESISTORS ARE V4W-, 5 ..
DIDOES ARE 0-""

-3V

'STRATE
L.. _____ ..JI

B-CS-W005-0- 1

Clamped Loads

RIO

:S:SO

~ !l~

5
0

III

AI-lev
eA.IOV
AC CJNO
RII

R8
1,100

1,100

C:s

.01
IIIFO

7,!IOO

R9
7,eoo

!I"Io

5°/.

.01
MFD

aBB -lev

IN.ESS OTHERWISE INDICATED'
RESISTORS ARE 114W; 10 ..
DEI - DE4 ARE DEC NO. 330-25E-I

B-CS-W300-0- 1

Delay Line

M GNO

C GNO

r-------------------------~----_+--------_4~----------------------~~----r_------__oA
+IOV
RI2
100,000

015

K~9

RI6
10,000

10'"1.

470
MMFO

IOOV

5"10

022
0662
021
0662
020
0662
019
0662
-7. !IV

RI7
1,500

.---+---O B
-15V
UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W; 5 %
DIODES ARE 0664

B-CS-W612-0-1

Pulse Amplifier

018

032
0662

.....,:.::..:JL...:.::::...=..._____-I-_____.. 0662
0 III

031
0862
030
0682

0662
014
0682
013
0662
H

028
0662
027
0662

0682
011
0882
RI4
1,500

R26
7,1100

AI3
1,000

R28
1,1100
R27
1,000

<:r-'"V\Ar-......---Q U

All
20,000
112W

BOURNS OR
DAYSTROM

018

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W; II ...
CAPACITORS ARE .. MFO
DIODES ARE 0664
TRANSISTORS ARE OEC3839

B-CS-R302-0-1

+CIO
39
-MFO

029
0682

....·-+-.012

RI2
7,500

+IOV
CGNO

One-Shot De lay

021

023

R211
20,000
1/2W
BOURNS OR
OAYSTROM

B -IIiV

Digital Equipment Corporation
Maynard, Massachusetts

printed in U.S.A.