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DEC-09-I9AA-D

October 1968

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Document:	DM09A
Order Number:	DEC-09-I9AA-D
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Pages:	42
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INSTRUCTION MANUAL

DMOSA

ADAPTER/MULTIPLEXER

DIGITAL EQUIPMENT CORPORATION. MAYNARD, MASSACHUSETTS

DEC-09-19AA-D

DMDSA
ADAPTER/MULTIPLEXER
INSTRUCTION MANUAL

DIGITAL EQUIPMENT CORPORATION. MAYNARD. MASSACHUSETTS

October 1968

The following are registered trademarks of Digital
Equipment Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL

PDP
FOCAL
COMPUTER LAB

CONTENTS
Page

1•

Introducti on

1. 1

Related Documentation

1 .2

Engineering Drawing References

Specifications

2.1

Environmental

2.2

Power Requirements

2.3

Physical

2.4

Controls and Indi cators

2.5

Performance

Installation

Principles of Operation

4.1

Basic

4.2

Detailed

4.2.1

Power Turn-On

4.2.2

Internal Control Pulse Train

4.2.3

Single-Fast-Input Cycle

4
5

4.2.4

Single-Slow-Output Cycle

4.2.5

Double (Back to Back) - Fast-Output Cycles

Acceptance Test Procedure

Maintenance

6.1

General

6.2

Delay Adjustments

6.3

Module Complement

Engineering Drawings
ILLUSTRATIONS

1-1

Basic DM09A System Block Diagram

3-1

Installation Diagram

4-1

Control Pulse Train Circuitry

4-2

Control Pulse Train Time Relationship

iii

CONTENTS (Cant)

TABLES
1-1

Reference Documents

4-1

Single-Fast-Input Cycle Signal Flow

4-2
4-3

Single-Slow-Output Cycle Signal Flow

Double {Back to Back)-Fast-Output Cycles Signal Flow

6-1

Module Complement

7-1

Engineering Drawings

1•

INTRODUCTION
The DM09A Adapter/Multiplexer an option to the PDP-9 manufactured by Digital Equipment

Corporation (DEC), provides an interface through which three I/O devices may'gain access to the
PDP-9 memory via the DMA channel. A basic system block diagram is given in Figure 1-1.

Figure 1-1

Basic DM09A System Block Diagram

This document and the documents referenced herein provide the information necessary for
installation, operation and maintenance of the option. The level of discussion assumes that the user
is fami liar with the basic PDP-9.

1 •1

Related Documentation
The DEC documents listed in Table 1-1 contain material which supplements information in

this document.

Table 1-1
Reference Documents

Document Number

Description

P DP-9 User Handbook

F-95

Operation and programming information
for the PDP-9.

PDP-9 Maintenance Manual
Volumes I and II

F-97

Operation and maintenance information
for the PDP-9 including basic PDP-9
engineering drawings. Basic DM09A
theory of operation.

DIGITAL Logic Handbook

C-105

Specifications and descriptions of most
FLIP CHIP moduies used in the DM09A.

Title

1 .2

Engineering Drawing References
Engineering drawings wi II be referenced using an abbreviated code. As an example,

drawing D-BS-DM09-A-2, DMA Adapter Multiplexer Control, sheet 1 of 2, wi II be referenced as
[DM-2(2)] •

SPECIFICATIONS

2.1

Environmental
The DM09A consists entire Iy of modu les of the type used in the PDP-9 centra I processor.

Therefore, PDP-9 environmenta I spec ifications apply to the DM09A.

2.2

Power Requirements
The option obtains a II necessary operating power from the PDP-9 power supply system.

No additional power supplies, power control or fan assemblies are necessary.

2.3

Physica I
The DM09A consists entirely of modules which are housed by two DEC standard 1943 mount-

ing panels, thus requiring 10-1/2 in. of mounting space. Placement of these panels is given in Section 3, INSTALLATION.

2.4

Controls and Indicators
No controls or indicators are associated with the DM09A. The option is entirely under the

control of the PDP-9 and the I/O devices.

2.5

PeITormance
The multiplexer operates at two speeds. I/O devices with 10 mHz logic may request the

high speed and thus achieve a 1 iJS/transfer rate; I/O devices with low speed logic should request the
low speed of 3 iJS/transfer to permit sufficient data-line settling time. It should be remembered that
the speed range applies only to the DM09A. The PDP-9 DMA channel and the memory require only
1 iJS/transfer.

INSTALLATION
Implementation of the option involves insta II ing the option modules into their preassigned,

prewired locations in the basic PDP-9 cabinet. The location in which the option mounts is shown in
Figure 3-1 •
RESERVED
FOR
DM09A
RESERVED
FOR
ME09B
PAPER TAPE
READER AND
PUNCH
OPERATOR'S CONSOLE

TABLE

Figure 3-1

Insta Ilation Diagram

The following engineering drawings provide all necessary interface information.

Description

Drawing Number

Title

D-CD-DM09-A-9 (Rev. A)

Memory Interface

Interface between the DM09A and the basic
PDP-9 memory.

CD-D-DM09-A-10

Interface Cabling
DM09 Memory

Interface between the DM09A, ME09A memory
extension control and MM09A extended memory
bank.

CD-D-DM09-A-11

Cabling DMA
Inter-Memory

Interface between the MC70B basic PDP-9 memory
and MM09A, Band C extended memory banks.

PRINCIPLES OF OPERATION

4. 1

Basic
A basic description of DM09A logic operation can be obtained from Section 3.8.3, DMA

Channel Transfers, of the PDP-9 Maintenance Manual, Volume 1. A detailed DM09A block diagram
is also contain in that section.
This document describes in detail the operation of the DM09A DMA Adapter/Multiplexer.

4.2

Detai led
A variety of transfer type combinations are possible with the DM09A. To avoid excessive

repetition, only three types will be described herein; Single-Fast-Input cycle, Single-Slow-Output
cyc Ie and Doub Ie (Back to Back)-Fast-Output cyc les.
Certain DM09A operations are executed regardless of transfer type; namely, control circuitry
initialization via power turn-on and interna I DM09A control pulse train generation. Transfer type
descriptions assume I/O device 0 is being acted upon. All reference wi II be made to I/O device O.
Simi lar operations wi II result when any other device is acted upon.
All transfer types can be thought of as consisting of a number of "time states" each commencing with a PDP-9 ClK pulse. Single transfers consist of time states in which either an I/O device is
made ready, in which a device is synchronized to the PDP-9, or in which a data transfer takes place.
With multiple transfers, synchronization is established during the previous data transfer.
When reading the logic descriptions, the user should refer to the engineering drawings
referenced on the signal flow tables. In addition, DM09A timing diagrams, drawings DM-8(1) and
DM-8(2) should be referenced for specific timing information.

4.2.1

Power Turn-On
When the system is first turned on, PK ClR (power and key clear) pulses arrive at the DM09A

control logic and produce PWR ClR POS (power clear positive) pulses to condition the control logic.
The operations performed are as follows:
Clear SYNC 0
Clear SET AO
Clear SET DO
Clear DEV 0 CaNT
Clear SLOW CYCLE A

4.2.2

Interna I Contro I Pu Ise Tra i n
Following PK ClR, ClK (clock) pulses arrive at the DM09A control logic and are used to

generate an internal DM09A control pulse train via the circuitry of Figure 4-1.
Ti me re lationships are illustrated in Figure 4-2. The pulse train is generated whenever the
system is operat i ng •

WI)05
A23

W005
A23

PHASE

W005
A23

ClK ---+---JII

'VA
RIll
A21

F
U

150fl

Figure 4-1

ClK

Control Pulse Train Circuitry

-----.U

I
A PHASE

~oons-n~------'n'---------

I
!-14-------650ns----n

lOAD AMEMA

----:-1-----------'

.....- - - - - - - - - - '

.~----7oons----n

D PHASE _ _--'-_ _ _ _ _ _ _ _

----=.J

~---

L.._ _ _ _ _ _ _ _- - I

L.._ __

I
I
I
I
Figure 4-2 Control Pulse Train Time Relationship

4.2.3

Sing le-Fast-Input Cycle
The DM09A adapter/multiplexer is uti lized during the memory read/write cycle. During

this time the I/O device break request flag is set providing the DM09A with a CH 0 BK RQ level.
Referring to Table 4-1 and the referenced engineering drawings, internal control logic operations serve
to generate an AM RQ level. This level is applied to the PDP-9 memory control circuitry shown on
drawing D-BS-MC70-B-1 (sheet 2). A ClK pulse marking the beginning of the SYNCING time state
is then produced. During SYNCIN G, the centra I processor has access to core memory. C LK, delayed
100 ns, generates SYNC ClK to set the AM SYNC flip-flop in memory control via AM RQ{l). AM

SYNC(l) produces AM SYNC(l)B and AM SYNC BUS(l). AM SYNC(l)B is utilized by CM (control
memory) timing to prevent SM(l) from restarting the CM on the next ClK pulse which marks the beginning of the DATA XFER time state.
The DATA XFER time state is entered via another PDP-9 ClK pulse. ClK, delayed 50 ns,
is POST ClK and resets the MODE flip-flop conditioned by AM SYNC(l). MODE(O) signifies AM
access to memory whi Ie MODE (1) signifi es CP access to memory. PRE-WRITE OFF of the previous core
memory cycle (SYNCING) sets the MEM DONE flip-flop and produces AM GRANT. If an EAE or an
lOT instruction immediately precedes the DM09A request, AM GRANT is not produced. In this case
AM SYNC(l)B is delayed to generate AM GRANT SMlTD (simulated).
During the current time state, I/O device 0 address bits are present at the input gating
circuitry of the AM REGISTER (refer to drawing DM-3(2». Address bits uti lized by a PDP-9 with basic
memory are designated CH 0 ADDR BIT 05 through CH 0 ADDR BIT 17. The bits are applied to the
inverter modules shown. ADDR 0, the result of DEY 0 CONT(O) and SET DO(1), allows the address
bits access to the jam input gates of the AM REGISTER as lAM 05 through lAM 17.
An AMI (adapter multiplexer input) pulse jam transfers the 13-bit address into the register.
AMI is the result of AM GRANT* or AM GRAND SMlTD. The flip-flops designated AMEMA 03 and
AMEMA 04 are used with PDP-9 systems containing extended memory banks. Inverter inputs are CH 0
ADDR BIT 03 and SET AO(l) for AMEMA 03 and CH 0 ADDR BIT 04 and SET AO(l) for AMEMA 04.
lOAD AMEMA jam transfers the extended memory addressing bits into their respective flip-flops. This
pulse is produced 650 ns after ClK by the control pulse train circuitry described in S.ection 4.2.2.
Following memory addressing, an 18-bit data word is jam transferred into the AM REGISTER.
I/O device 0 data word consists of CH 0 DATA BIT 00 through CH 0 DATA BIT 17. The data 'word is
also applied to a network of inverter modules. The enabling signal is DEY O. The data word is jam
transferred into the AM REGISTER by a second AMI pulse which is produced by AM STROBE.

4.2.4

Single-Slow-Output Cycle
Table 4-2 illustrates the signal flow associated with a Single-Slow-Output cycle. The

I/O device is programmed to indicate that an output transfer is to take place, the number of words to
be transferred and the address of the first word, DM09A control logic operations which result from this
type of data transfer are basically simi lar to those of the Single-Fast-Input cycle. The I/O device
requests multiplexer service via CH 0 BK RQ. The control logic proceeds to generate AM RQ and
AM RQ NEG. SYNC 0(1) and CH 0 FAST RQ condition the set DCD gate of the SLOW CYCLE A

*Both may be present but the circuit is a logical OR.

flip-flop which is set by the positive going transition of AM RQ NEG. Following logic operations in
the multiplexer and in the PDP-9, an AM GRANT pulse is issued to produce AMI. With input transfers,
this pulse jam transfers the device supplied address into the AM register. This is not necessary with the
current type of transfer.
Following further DM09A control logic operations, similar to those of Single-Fast-Input
cycle, PDP-9 AM STROBE arrives at the DM09A. This pulse is gated with CH 0 RQ IN and SET DO(l)
to produce SAl (sense amplifier input) thus allowing PDP-9 sense amplifier bits SA 00 through SA 17
access to the jam input gates of the AM register. A second AMI pulse is produced at this time to jam
transfer these bits into the AM register.

4.2.5

Doub Ie (Back to Back)-Fast-Output Cyc les
Signal flow for the current transfer type is given in Table 4-3. Initial signals sent to the

DM09A control logic are CH 0 BK RQ, CH 0 FAST RQ and CH 0 RQ IN. CH 0 BK RQsignals the
DM09A that service is requested. This signal and internal SLOW CYCLE A(O) produce SYNC 0 EN to
condition the set DCD gate of the SYNC 0 flip-flop. The D PHASE pulse preceding the SYNCING 1
time state sets SYNC 0 to establish device priority. This conditions the CH 0 FAST CLR and sets the
DCD gate to produce AM RQ and AM RQ NEG. AM RQ signals the PDP-9 that a DMA cycle is desired; the computer responds with AM SYNC(l) B.
The A PHASE pulse of SYNCING 1 sets SET AO and generates CLR SYNC. This clears
SYNC O. SET AO(l) and AM SYNC(l)B generate SET DO EN which conditions the set DCD gate of the
SET DO fl ip-flop.
The following D PHASE pulse sets SET DO. SET AO(l) and SET DO(l) produce CLR SLW CYC
EN which with A PHASE, maintains SLOW CYCLE A(O), a characteristic of fast transfers. SYNC 0 is
set again because SLOW CYCLE A(O) and CH 0 BK RQ are sti II present. Setting SYNC 0 generates
another AM RQ signa I. Because this signal is applied to the PDP-9 AM SYNC fl ip-flop prior to SYNC
CLK, the flip-flop remains set.
The PDP-9 produced AM GRANT arrives at the multiplexer control circuitry as the DATA
XFER 1 and SYNCING 2 time states are entered. The pulse jam-transfers address information into
the AM REGISTER. During these time states the data transfer associated with the preceding syncing
operations, and syncing operations for the next data transfer take pla.ce.
AM STROBE arrives from the PDP-9 and generates SAl and AMI, thus a Ilowi ng the sense
amplifier bits, SA 00 through SA '17, access through the AM register gating circuitry and into the
AM reg ister •
DATA XFER 2 is entered. SET AO is cleared and operations simi lar to DATA XFER 1 take
place to jam transfer the data bits of the second word into the AM register. The D PHASE pulse at
the end of the current ti me state c Iears SET DO.

Table 4-1
Single-Fast-Input Cycle Signal Flow

Time
State

Control
Pulse

D PHASE

SYNCING

A PHASE

D PHASE

DATA XFER

A PHASE

D PHASE

Signal
SYNC 0 EN
SYNC 0(1)
AM RQ
AM SYNC(l)B
SET AO(l)
CLR SYNC
SET DO EN
CH 0 FAST CLR
SYNC 0(0)
SET DO(l)
CLR SLW CYC EN
AM GRANT
CH 0 ADDR ACC
IN
DEV 0 CONT(l)
DEVICE 0
SET AO (0)
CH 0 ADDR ACC
SLOW CYCLE A(O)
AM STROBE
CH 0 DATA RDY
IN
INH 0 DAP(O)
CH 0 DATA RDY
CH 0 DATA ACC
SET DO(O)

Conditions

Drawing
Number

CH 0 BK RQ * SLOW CYCLE A(O)
D PHASE * SYNC 0 EN
SYNC 0(1)
From PDP-9
A PHASE * SYNC 0(1)
A PHASE * AM SYNC(l )B(B)
AM SYNC(l)B * SET AO (1)
CLR SYNC * SYNC 0 (1)
SYNC 0(1) * CLR SYNC
D PHASE * SET DO EN
SET AO(O) * SET DO(l)
From PDP-9
A PHASE * SET AO(l) * SET DO(l)

DM-2(2)
DM-2(1)
DM-2(2)
MC-1 (2)
DM-2(1)
DM-2(2)
DM-2(2)
DM-2(1)
DM-2(1)
DM-2(1)
DM-2(1)
MC-1 (2)
DM-2(1)

CH 0 ADDR ACC IN * SET DO(l)
DEV 0 CONT(l) * SET DO(l) * CH 0 RQ IN
A PHASE * SYNC 0(0) * SET DO(l)
CH 0 AD DR ACC IN
A PHASE * CLR SLW CYC EN
From PDP-9
D PHASE * SET DO(l) * SLOW CYCLE D(O)

DM-2(1)
DM-2(2)
DM-2(1)
DM-2(1)
DM-2(1)
MC-2
DM-2(2)

CH 0 DATA RDY IN
CH 0 DATA RDY IN
DPHASE *CH ORQIN * INHODAP(O)*SETDO(l)
D PHASE * SET AO(O) * SLOW CYCLE D(O)

DM-2(2)
DM-2(2)
DM-2(l)
DM-2(1)

Table 4-2
Single-Slow-Output Cycle Signal Flow

Time
State

Control
Pulse

SYNC
D PHASE

SYNCING

A PHASE

D PHASE
DATA XFER

A PHASE

Signal

Conditions

Drawing
Number

SYNC 0 EN
SYNC 0(1)
AM RQ
SLOW CYCLE A(l)
AM SYNC(l)B
SET AO(l)
CLR SYNC
SET DO EN
CH 0 FAST CLR
SYNC 0(0)
SET 00 (1)
AM GRANT
CH 0 ADDR ACC
IN
DEV 0 CONT(l)
SET AO(O)
CH 0 AD DR ACC
CLR SLW CYC EN
SLOW CYCLE A(O)
AM STROBE
AMI
SAl

CH 0 BK RQ * SLOW CYCLE A(O)
D PHASE * SYNC 0 EN
SYNC 0(1)
SYNC 0(1) * CH 0 FAST RQ * AM RQ NEG -+ 0
From PDP-9
A PHASE * SYNC 0(1)
A PHASE * AM SYNC(l)B(B)
AM SYNC(l)B * SET AO(l)
CLR SYNC * SYNC 0 (1)
CLR SYNC * SYNC 0(1)
D PHASE * SET DO EN
From PDP-9
A PHASE * SET AO(l) * SET 00(1)

DM-2(2)
DM-2(1)
DM-2(2)
DM-2(1)
MC-1(2)
DM-2(1)
DM-2(2)
DM-2(2)
DM-2(1)
DM-2(1)
DM-2(1)
MC-1 (2)

CH 0 ADDR ACC IN * SET DO(1)
A PHASE * SYNC 0(0) * SET 00(1)
CH 0 ADDR ACC IN
SET AO(O) * SET D(l)
A PHASE * CLR SLW CYC EN
From PDP-9
AM STROBE + AM GRANT
AM STROBE * CH 0 RQ IN * SET DO(l)

DM-2(1)
DM-2(1)
DM-2(l)
DM-2(1)
DM-2(1)
DM-2(l)
MC-2
DM-2(2)
DM-2(2)

SET DO(O)

D PHASE * SET AO(O) * SLOW CYCLE D(O)

DM-2(1)

D PHASE

Table 4-3
Double (Back to Back)-Fast-Output Cycles Signal Flow

Time
State

Control
Pulse

D PHASE

SYNCING 1

A PHASE

D PHASE

DATA XFER 1
SYNCING 2

A PHASE

D PHASE

DATA XFER 2

A PHASE

D PHASE

Signal

Conditions

SYNC 0 EN
SYNC 0(1)
AM RQ
AM SYNC(l)B
CLR SYNC
CH 0 FAST CLR
SET AO(l)
SET DO EN
SYNC 0(0)
SET DO(l)
SYNC 0(1)
AM RQ
AM GRANT
CH 0 ADDR ACC
IN
CH 0 ADDR ACC
DEV 0 CONT (l)
AM STROBE
SAl
SYNC 0(0)
CH 0 FAST CLR
CH 0 DATA RDY
IN
CH 0 DATA RDY
AM GRANT
CLR SLW CYC EN
SLOW CYCLE A(O)
CH 0 ADDR ACC
IN
CH 0 ADDR ACC
AM STROBE
SAl
SET DO(O)

CH 0 BK RQ * SLOW CYCLE A(O)
D PHASE * SYNC 0 EN
SYNC 0(1)
From PDP-9
A PHASE * AM SYNC(l)B(B)
CLR SYNC * SYNC 0(1)
A PHASE * SYNC 0(1)
SET AO(1) * AM SYNC(l)B
CLR SYNC * SYNC 0(1)
D PHASE * SET DO EN
D PHASE * SYNC 0 EN
SYNC 0(1)
From PDP-9
A PHASE * SET AO(l) * SET 00(1)
CH 0 ADDR ACC IN
SET DO(1) * CH 0 ADDR ACC IN
From PDP-9
CH 0 RQ IN * SET DO(l) * AM STROBE
CLR SYNC * SYNC 0(1)
CLR SYNC * SYNC 0(1)
D PHASE * SET DO(1) * SLOW CYCLE D(O)
CH 0 DATA RDY IN
From PDP-9
SET AO(O) * SET DO(1)
A PHASE * CLR SLW CYC EN
A PHASE * SET AO(l) * SET DO(l)
CH 0 ADDR ACC IN
From PDP-9
CH 0 RQ IN * SET DO(l) * AM STROBE
D PHASE * SET AO(O) * SLOW CYCLE D(O)

Drawing
Number

DM-2(2)
DM-2(1)
DM-2(2)
MC-1 (2)
DM-2(2)
DM-2(1)
DM-2(1)
DM-2(2)
DM-2(1)
DM-2(1)
DM-2(1)
DM-2(2)
MC-2(1)
DM-2(1 )
DM02(l)
DM-2(1)
MC-2
DM-2(2)
DM-2(l)
DM02(1)
DM-2(2)
DM-2(2)
MC-2(l)
DM-2(l)
MC-2(1)
DM-2(1 )
DM-2(1 )
MC-2
DM-2(2)
DM-2(1)

ACCEPTANCE TEST PROCEDURE
Acceptance testing of the DM09A option consists of executing Test Procedure DM09A-O

with the DM09A Tester at both normal operating conditions and the voltage margins specified below.
Aggravation
Condition

Trial

Test

DM09A-O

None

DM09A-O

Margin rack A

DM09A-O

Margin rack B

Minimum margin specifications for rack A and rack B are listed below.
Margin

+10V
+6V

MAINTENANCE

6.1

General

-15V

I -6V

+4V , -4V

The general maintenance procedures described in the PDP-9 maintenance manual also
apply to the DM09A option.

6.2

Delay Adjustments
Adjust the R302 Delay at A27 according to the data given on engineering drawing DM-2(2).

6.3

Module Complement
Table 6-1 lists the module complement of the DM09A option.

Table 6-1
Module Complement
DEC Type

Module Type

Quantity

Recommended Spare Quantity

B169

Inverter

B213

Jam Flip-Flop

R002

Diode Cluster

R111

Diode Gate

S107

Inverter

S202

Dual Flip-Flop

S203

Triple Flip-Flop

S603

Pulse Amplifier

W005

Clamped Loads

W300

Delay Line

W612

Pulse Amplifier

R302

One-Shot De lay

*Contained in the basic processor spare parts kit.

ENGINEERING DRAWINGS
Table 7-1 lists the DEC engineering drawings associated with the D"A09A option.
Table 7-1
Engineering Drawings

Drawing Number

Title

Revision

DM-2(1)

DMA Adapter Multiplexer Control BS-DM09-A-2 Sheet 1 of 2

DM-2(2)

DMA Adapter Multiplexer Control BS-DM09-A-2 Sheet 2 of 2

DM-3(1 )

AM Register BS-DM09-A-3 Sheet 1 of 2

DM-3(2)

AM Register BS-DM09-A-3 Sheet 2 of 2

DM-4(1)

Cab Ie Diagram BS- DM09-A-4 Sheet 1 of 2

DM-4(2)

Cable Diagram BS-DM09-A-4 Sheet 2 of 2

DM-5

Module Uti Iization MU-DM09-A-5

DM-S(l )

DM09A Timing Diagram TD-DM09-A-S Sheet 1 of 2

DM-S(2)

DM09A Timing Diagram TD-DM09-A-S Sheet 2 of 2

¢ ADDR ~ee LN

CH I ADDR Ace IN

CH 2 ADDR Ace IN
1'\

CH ¢

ADOI'< ACC

CH I ADDR

D
CH 2. ADDR Ace

Ace

SET AI(I)

58" A2 (I)

S=:T 0 1(1)

SET D2(1)

¢ DATA Ace

DPHASE:

H..J

SLOW· CYCLE 0(1)

;:,

A PIfAS£' ---1>Ei;;;:"\--;;>f)<:]

PWR C L R POS----'---t:I--r==-:----=.-f--L--------O'-i'=-.!-='-i-...l-------C>J--i==-'--'::.....;:...l

Ace

D PHASE.

CH 2. DATA Ace

\...

S=:T A ¢ (rf;)

SLOW c.YCl:E:Otf), =:

wl1Jr/is

W~rj5

CI9

C.19

PWR CLR POS --;;:O-=;=-''-=--=T-'

eN 2 RQIN_~~~

CH I Rq IN

PHitS~

fl M. RQJi EG.

SLOW CYCLE 0 (I)

eLR

A PHAS.E

CH '2. F .....ST

C.LR

CH i

'.3ET D ¢(I)

CH 2

PWR CLR
D PHASE

CLR

SYNC .=:..(:{;?3:}---+------'.N,,-o!8j--+--------'D~C8:I

t----------...-------+-----<O CLR SLW eye EN

:E.N
'SYNC I (I)

'SYNC 2..(I~

¢ OAT A RDY HJ

CH I DATA RD'I IN

CH if; ADDR. ACe. ~N

CH 2 D"TA RDY IN

CH I "'-DDR ACC IN

SHA¢(;)
SET D <)(1)

e ADOR Ace IN

BS-DM09-A-2 Sheet 1 of 2 DMA Adapter
Multiplexer Control

2
W¢¢5

I\M RQ
',7?5
r

2.(.'

• EN

I--_ _--'-K~

~5ET

~SET

.. I---~~N

D Z

A2?

AM RQ NE~.

AM SYNC(i)e.CB')
p

L
K

SYNC ¢ (I)
SYNC 1(1)
DEVICE Q

SYNC. 2. EN

CHQRQIN

/\
V

CH
DEV ¢ CONTROL(I)
SET 0 i/'J(I)

ROY

CH ¢ DATA RDY IN

AMI
H

DEVIC.£ \
CH 1 RQ IN

/\
L

DEV \ CONTROL(I)
SE.T D 1 (I)

/1 M GRIiNT
SNiLTD

SAL

A2d

LOflD
/lMEMA

CH Z RQ IN

/1 M S Y N C. (I) B --_£PI.2;sJ

B
DEV 2 CONTROL(I)

SET D2.(I) U

liDJUS r /t/J/I GR/jf'{T SMLTD.
TO occuR AT AM GRliNT

TIME.

C H 0 RQTN --q~("V
IS/()7

824
PWR ClR pas
SYNC

2. (¢)

A PHASE (B)

PK CLR

A. PHASE
I!>¢A

SnlC. 2. (91)

BS-DM09-A-2 Sheet 2 of 2 DMA Adapter
Multiplexer Control

SA0£!
SA I

CH 0 DATA-BITll0
DEV ~

CH I DATA-BIT.0'.0'
DEVI

CH 2 DATA-BIT¢¢

DEV2

NOTE:
loon,

tw,

C
::-

lOt, TERM I NATORS TO GROUND

MUST BE PUT ON SA00 THRU SA 17.

loon
8
SA 12

SAl
CH 0 DATA-BIT 12
DEV 0

CH I DATA-BIT 12
DEV I
CH 2 DATA- BIT 12

BS-DM09-A-3 Sheet 1 of 2 AM Register

P,.,.....,..------,...-,

D
LAM.0'5

CH \) ADDP. BIT03SET A(11)

CH I ADD!?

CH I ADDR BIT 03

BIT

SET AI (I)
CH 2 ADOP. BIHl3

0'4

CH 2AooR

-=-

LAM 10

LAM II

LAM 13

LAM 12

CH 0ADoR
BIT 1216

CH 0 AODP
BIT07

CH 0AoOR

BIT 08

CHrllAODR
BIT 0'9

CH 0 AODP
BIT II

CH,AoOR
BIT 05

CH IAOoR
BIT 06

CHIAoORS
BIT 07

CH I AOOR
BIT (lj8

CHIAOoR
BIT 09

CH IADDP
BiT II

BIT 13

CH 2 AOoP
BIT 1216

CH 2 AoOR V
BIT 07

CH2 AODP
81T £18

CH2ADDRV
BIT 1'19

CH 2 AOOR V
BIT II

CH2ADDRV
BiT 13

M
':'

LAM 09

LAM I2IB

LAM (67

CH iZlAooR
BIT 05

CH2ADDR
BIT 05

BIT 04

LAM 06

-=-

C
W005
A23

LAM 14

CHiZlAOOR BIT
ADD!? JIJ
C" IAOORBITI4
ADDIl

CH 2 ADOP BIT 14

AODR

LAM 16

LAM 15

LAMI7

CH0AODR
B!T 15

BIT 17

C,.,I"'OOR
BiT 15

BIT 16

CWI AOO~
BIT 17

CH2ADOR V
BIT 15

CH2AOOR
BIT lEi

CH 2 ADDP
BI T 17

ADDR

DEV

CONTROL (0) U

DEV 2CONTROL(0)K

BS-DM09-A-3 Sheet 2 of 2 AM Register

W¢33
AI/J5

WC/J31
DC/J4

G795
AI5

•E

CLK

¢i/J

QlI

1(/1

CH 0 BK RQ

AM SYNC(I)B

RQ IN

AM RQ

•p
•S

T
FAST

AM STROBE

CH 0 FAST

AMEMA 134 (0)

•

"*
W031

013

CH I BK RQ
RQ IN

¢4

(/15

06
07

(/18

SA 17

USED FOR TERMINATION ONLY NOT A CABLE.IOPTIONAL)

W!Il31
Af/)3

W031

D¢2
(IT'

00 (I) -4

CH 0 6K RQ

AM i/JC/> (I)

CH I/J RQ IN

I/JI

-4H

CH 0 FAST RQ

1/J2

-41(

CH I BK RQ

¢3

CH I RQ IN

CH I FAST

DATA

CH 2 BK RQ

1/J6

FAST RQ

CH 2 RQ IN

CH 2 FAST RQ

CH I FAST

CH 2 BK RQ

08 (I)

AM (/)9 (il

AM C/J9 (I)

l\il

llil

-4

(1)8 (I)

(15'
E

-4M
-4p

DATA ACC

16
AM

-4S
.-

AM 17 (Il

CH 2 FAST CLR

(IT'

FAST RQ

-4""
-4p

~(IT'

ADOR ACC

W031

RQ IN

(IT'

(CH 2)

(t5'

W¢31
0¢7

A04

W031
010

(CH I)

Wy)33

W031
012

W031
0¢6

"-"

'--'

(CH~)

(CH Il

(CH 2)

011

~T
-4

17 0)

~,V

NOTE:
PINS C,F, J, L,N,R,U
ARE GND FOR ALL

WQl31'S AND Wr/J33'S

'-'

BS-DM09-A-4 Sheet 1 of 2

Cable Diagram

iWQ)cz,-s-i<1 \1'1031
C~(,i'DP.-f'.b-;- rj;¢

,ClIO

eH ¢ OAT/'- 611

~I ~----~~~
r:P 2.. -,------:-.1 \-\
\<:
r:P3 ----;------~.

··•
o

¢g

CH (/> I\DDR 61T

(j)'7
Crl

l't

----;-----ec...:.~.
t

q:, '2>AT/,- BIT ¢5 ----;-I----ec...:.,..

Irb

\-\

¢~:

eH q; r>.DDR SII cjJ9

'E.

¢q. ----;-------=-~.

CP5 -;----+-'~

iwi>"¢S-"'
iI W~31
ICI~
cal"\-

W031
C¢3

C(;llI

CI-I r:/J DAIA 'ell 1/

. I

L ___ -.-l

CI-\ ¢

eH I DI>.T'" 'ell

E
----;----+-''-41 •
1-\

¢~

12-

-,-----,...

\'\

l't

¢ci>

CH \ '0"',(>... So\\" ¢9

(/:;\

cD?..

¢~

1'2..

¢q

cps

¢ro

\CO

¢.,

\<0

I>.D'OR 8\1 ¢s

CH C(:J I\DDR 'CIT \'7

CH I D"'\" '8.1\ ¢'6

CI-\ I D(>...''''' 'C\\ \ro,

fW¢¢5"V ""d31
V' 'P

W¢31
C¢7
CH I P\DDR \3\\

~----~I:-.I •

I<:D

--;------I~

··

Crl I i'-'ODR 8\T

g\~
I

1:'\

rjJ4

¢'"

•\-\

?
I"\-

\'\1

•

\-I

\<:

-:-----·R~I:-.I :.

os:

~----'-=I:-.I:
II
->

-,---_'""1I i .

01
\"
---.,----+-.,-41 •

lCO

--'-----,41 •

"'!

CHI ",DD~ '8\\\'1

L _ _ _ -l

'I! v
--'-----:-./
L ___ J

CH 2. DATt>. B\\

1 CI <0

'01

C¢~
0

1';.1

(/jet>

------,----+=~.

dJl

------,-----,....1~.
FI

\-I

1-11

CP2 ----.,.----'"'1~.
O~

cPo,

""! ~ 5
-;----+'-:,-.1

.I.!

1_~:1

31='1 • .

i ....vv-:si
1

I·

I~-:-I";.

:~'Ji

t<"

II:

~---l

"'.

\-11_

:~0:

iwalc;i>5

L~I~ __ J

•

I e--'V\-

i
LC"':'~_J

:W<P¢5 !

:-=%

I~V-ol

I
~----~~.
~,----~,:-./

wz,¢"5-ot-, f!t3:
lei",

dJs
¢t:C

~--Flc.f·

M
---7----+='-;I~ •
\'\1
P

----'-----41.

Ml '•
<:$'1 ---:-::---7-401
I
Nt
~
CI-IZ D"-,'" BIT ¢'8.
I
L
___ ...JI

.•

CH 2. I>.'O'OR 'CIT

Iq,

rj,7:!,

12-

iJq

¢s

Ic\-

r/>r::a

It:>

I<D

¢..-,

c.1-I2. DA,\A. BIT \'7

CH L ",bOR '5\, ¢>~

CH 2. ADDR 811

14-

1 c..1'Z...
LI
D

•
'to

\-j

-,-I----*-'-~ 1

\"2-

¢?>
Icf;

1-\

-;----~I~ •

lvVarQ5s'il
I C.IS I will 3 I

W~31
CII

CH 2. DF>.'(>" BIT 09

•

?I
'"
~----+---,..

______..R_:~ M

-...,------<l.=..~

CH'C I'\\:>DR '61\ \ I

T: So
u:
--+1--_+---:-.1 •
T

L ___

I·
~

B
·OPTIONAL CLAMPED LOADS.

BS-DM09-A-4 Sheet 2 of 2

Cable Diagram

1933 WG'.33 W1J33

le33

11IIP

8213

~213

B213

8213 I ~213

11213

6213

8213

16795" 1612

R8IJ2

RIll

Sl8

I 8213

RIll

CLR

A21Y

D
SA

0-8

9-17

11-2

Ali

·1l2

·111

ji8

I·e

f----AMI

(Il)

f--ONTROl
FROM
I, ~HASI
EMORY f----- AISH ~IBS_
f--(B)
lEVEL
f--TERM.
f---

MEM.

9-17

AlaM

AM
·91

All

·93

115

·99

All

111

AI6F

~
~
~

f---

BI69

B169

8169

LAM

LAII

.04

llS

.9S

.S8

.sa

B169

trl69

LAW

LAM

~MEM,A

.~Jl

.02

8169

B169

8169

B169

~IB9

B169

R1S9

R169

LAM

1·9

1;9

B213

R213

ADOR

~DDR

J-----

c
LAM

LAM

g.l!a2

R213

.91

·S3

OEV I CE > - -

BZIIl

A18L

AMl ,~

iAMEMA
~3

LAM

LAII

LAM

.87

.89

~ A17H_

DEV I CE OEV ICE

f-R.

I - - 52(02

Ba~N

I;WN
I~~IN

SLOW

134

~?Q2

I-

f+-- CH9

C 0m om A~~~

ADBDI RT

1 8-8

9-171 3-8

BIT
9-17

I BIT
I

I DATAl OAT A I ADOR

BIT
9-17 I ·0-8

3-8

AODR
BIT
9-17

+--

I ADDR
I AOOR
I 9-17
BIT
BIT
BIT
3-8
9-17

DATA I DATA

BIT
.9-8

CH.8
AODR
BITS
S3- 17

CH 1
ADDR :
BITS
113-17:

CH 2
AOOR
81TS
83- 17

CH:S
CHI
DATA
DATA
BITS
BITS
:88-14 811-14

CH2
DATA

Cll2T

C23l
-[)?1S

C.\lSS

C.z.3H

C.\lST

Cl3N

DISF

f---

B2B11' J-----

PHASE
SLOW fCYCLE
D

rGAR~

+----OEV I

- CONTRO

W031

W~31

W0]31 W031

11131

W031 w031

CH I

1iS31

'195

W612

~?A7

<:'?IJ?

S?A?

S?.A?

R111

SET 0
.8 EN

SET

SYNC

1612

1---+----1 09

0:1

A 1

SEl

RIll

S6,0~

CHJd
AODR

CH0

RIll

s-6]J3

RIll

SET

SYNC

A Jd

CH 1

CH I
ADDR.

CH I
D11F_ DATA I-0~V L D2.¢F

CH 8
US-T
CLR

CH 2
DAn
CLR

CH I
DATA
ACC

~~C

V
D

~ 1/
V

33 34

V
35

V
36

""~~

~
42

43 44

t--

C27E

DEY 2

ONTROLf...£26L

C27P

INH

f---+---+--t--+---+--I ADDR

CH 1
AODR
ROY

40 41

S6~31S203

CH¢
D1SR_ DATA ,-OEV .11. D19f'.
P.oy
IN
IN

CH 2
ADOR
ACC

SET

ADOf'.
ACC
IN

CHji
AOOR
ACC

SYNC ...&25E_1- C26P

C25P
jSVNC-E OISR SPARE !-~Y~~ '-SH,,..,;Dt--_-+_-t_ _t--_-+_-+

024H
024L
W812

'6~2

W612

CYC
EN

~?"7

0,,--24_0-+-____ DI9 F
1-

CLR
SLW

.14I--::B2'""7-=-0+----I
~.;,.;1i22;.,.tK.-I---+---l
j-.;B;':27~R+-----1

eye
EN

CLR
SLW

II I2N

/1'.

R11

~YNC

~~:~ fsy:~
C1.S'F
CI.D

I BITS

20 21

r.II'V

R
CLf'.
SLW
eyC

OEV!
EN
CYCLE f - - CONTROl +-----

a21V

'"1'"~

B21L iAMEMA ~MEMA
AODR

A
PHASE

I L62"D

f---

0485

GRNT GR.NT
SMLT[ 15MLT

8213 15107

8Z11V f--.....-

J---LAM

32 33 34

~
S24N

f---

I
i

f---

B19V

I-A 18K

f---

A2SD

>--

AI7L
RIll

15603

~ f--r-.2Jl1S.. SPARE >
--

B169

~~h~

J----

BI9l

B169

>-f----- I---AIBR~

24
IRI2

coo:::

F=-

23
1lIII5

f---

f--- 2

S~I

A23F

r{~:c A~ )~Y~~ AM
f - - - SYNC 1

~g~~.

[6
DAP

AM
SPARE
9-8
I (NEG)

AM
CONTRO
9-17 SIGNAL
(NEG)

SPARE

All
.8-8
(NEG)

CONTRO
AM
9-17 ISIGNALS SPARE
(NEG)

All
.9-8
(NEG)

9~~7 ~~m~i~E~Et S~ARE
(NEG):

~~C

' TERM

ACC
IN

R.DY
IN

1
DAP

CH I

eHS

I ADOR

DATA
ROY

INH

ACC

CH 2
OATA
ROY

·1

CH I
FAST

I CLR

I eH.8

DATA
ACC

CH 2
DATA
ACC

CH 2
ADDR

~~C

CH 2.
ADDP.
ACe
IN

C H 2.
0171L DATA I- DEV L D20R
RDY
IN
IN

INH

2.
DAP

*" OPTIONAL MOOULES.
NOTE! FOR MODULE COUNT SEE A_PL_OMS9_A_5

MU-OM09-A-5

Module Utilization

~
I

COMPUTE.R

BASIC C.YC.LE

SiNGLE.,FAST,iNPuT CYCLE
SYN

fll Ii

SiNGLE, SLOW, OUTPUT CYCLE
SYNCING

au y

A PHASE PULSES (120 NS)

(INTE R NAL DNl09A)

o PH ASE: PULSE S (leO NS)
(INTERNAL DMO'7I1)

C.HX6KRG,

(FROM DEV X TO DM09A)

ADDR ACCEPTED X ~

"liST CLEAR\,

\ ~"1------------------~===~~_-'__-_3___~~~_-~~'----------------------r~~_~~________~/~I
~Ow CYC.LE: (0) ·CHX BK RQ (-3)-D PHIIS!

SYNC X
(INTERNAL DM0911)

------~

AM '3 YNC (I) B -A PHASE

,.r-SYNc.x_o

SYNCX-I,,_,

-1: :r'_
_________________________~~'_______________________________~~'---------------------

AM RG.

(FROM DIVlO 9fl TO MEMORY)

200 NS - - :
AM SYNC (ll8
(FROM MEMORYTO DM09f/)

MAX

r-t

:r----\

--------cc
YNC

ss:rll x
(INTERNIlL DNl09A)

I
I

200NS--. ---

MAX

;!----\~

400 NS

-i

'--

________________________________M_A_X____~/~'

- - - - - - - - - , L -_______________________

x (I) - fI PHASt::

SYNC x(o)· StT D X(I)·/9 pHASE

CH X FAST RQ
(FROM DM091l TO DEV X)

CHX RGI IN
(FROM DEV X TO DIVI091i)

SHM'.M'Y"""'~

SET D X
(INTERNAL DM091l)

SLOW CYCLE (0). SET Ii )«(O)·D

SLOW CYCLI::
(INTERNAL DM09A)

PHASE

(

--------------------------------------~

CH X FA 5T RQ (-3). SYNC. X (I) ·AM RGl--~
1.9 MS

Jl/

TD-DM09-A-8 Sheet 1 of 2
Timing Diagram

DM09A

C:CMPlF-ER BASIC CYCLE::

A/II GRANT
(FROM MEMORY TO DIfl09A)

SINGLE, SLOW, OUTPUT CYCLE
SYNC-tNG.

_ _ _ _ _ _ _ _ _ _-r'~SET D X (I). SET II X (i) • A PHIlSE

DATA READy (CHX)

-1

SYNCJ"G. 1
!lATA X>ER 1 DIlT;) xFERZ

I
I

U(320 !'Is)

(PROM DM09A rODEYX)

O~TPUT CYCLES

U (320 NS)
_ _ _ _ _ _ _ _ _ _ _---1~SLOW (yc.LI:: (¢)'SHD x(l)· D PHASE.

DOUllLE (BIlCXTO BACX), "AST,

U(120 NS)

flDDR ACCEPTED (er/x)
(FROM DMo'?h TO DEV X)

U(120N5)

AM STROBE
(PROM MU;70RY TO DM091i)

_ _ _ _ _ _ _ _ _ _ _---1~CHX RQ IN (-3)· SET D X(I)·p PHASE
CATA ACCEPTED (CHX)
(FROM DMO 914 TO DEV X)

C H X ADDR
(PROM D.£V X TO DfYl09A)
CH X DATA
(FROM D£V X TO DI'II09/1)

lJ(320 NS)
flDDR ACCEPTED X~r--,---------r-__,
__

SENSE /IMPS
(FROM MEMORY TO DM091l)

-.-_ _--,

~/
~ DATR ACCEPTED X

STROBE

~-D-A-TA--V-~~-,-D----------------------~~8~,~-D~-.T~A~~-~~L-.ID------------------------------------~

AM LOADED

(F ROM DII'I091l TO On X ¢
MEMORY)

~SYNC !\-+¢

U(320 NS)

C:.RANT

CH X FI7ST CLU~R
(Ff:eofVI DfYlO 91i TO DEV X)

\.....- - - ' - - - - - -~

'-----'------~~

~--~------_~~~/~==~~----------------------------------~\--~

- - - - - - - - - , U ( S Z O NS)

TD-DM09-A-8 Sheet 2 of 2
Timing Diagram

DM09A

M
GND
A
+IOV
R4
100,000

R8
100,000

RI2
100,000

RI6
100,000
Q8
CI
.01

MFD

034
RI8
1,500
B
-15V
C
R2
100,000

038
0662

GND

D31
D662
D36
D662

D6
D662
D5
D662

033

RI
1,500

RI1
1,500

RI9
1,500
I
- 3V

L~T~A..!"-.J

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W; 5 %
DIODES ARE D664
TRANSISTORS ARE 2N4258

B-CS-B 169-0-1

Inverter

r-------------------~--------------------.----------------._------------------_.------------------------~A
+IOV
GND
( H
)M

( S

( R

~.DIO
R5
1,000

>R4

IIIo..l

>II~/o

RII"'l

R6
6,800

R9
6,800

( F

,,..

- - - - 1 - - - "'l

HE--<

~. DI6
Rig

1,000 ~.D9fv

MFD

7\....
Q1,-=,

"
012

~. 022

~-H""

"'lrn<

~3V

1,000 ~""'B MFD

~'D24

\ t:...
'-.::II 014

...

RIO
100
10%

R25

> 1,000

CIO

RI8
100
10%

011

R20
6,800

R23
>6,800

R24
100
10%

_,-C7
r'IO

-r:fri

MMFO

MMFD

~~020

DI9~.

07 ...

-3.5V

"_. h ~,D25

.-------~--r--------.----------~~---+--~~~(M-I~~~----~~-------r--+---~~~~--------~r-~-2~.~~~, _~

"D~Q3 ~5
~
05

...

Dfs)9B

'-.

R2
150

R3
1,500

M~ri

~~D

D3i~
~'f
~

RI3

~,
~~':~:%?
:I~;OOl~t9B

L;-----;-----+--------~--~

YE--<~

R8
470

RI
1,500

DEC
3639B

~'OI~QIO. ~0~g9B
~

017

.....

'-.

."." '"

1,500

150

+-____+-____

L __. __

DEC
3639 B

>R22

7,500

0662

-4.2V

16~.

R27

rl~t-7\-JVIOVO'"

~;~
....~;;,"
~1~;60 r ~39B

r-------4
R28
1,500

R29
750

R30
150

~------~~~

-1!lV

UNLESS OTHERWISE INDICATED;
RESISTORS ARE 1/4W; 5 %
DIODES ARE D664.
TRANSISTORS ARE DEC3009B

B-CS-B213-0-1

Jam Flip-Flop

DID

0884
011

0884
09

0664
04

..I

0664
08

0664
03

0664
07

'.:

..I

0684
02

..I

0664
06

0664

8-CS-R002-0-1

Diode Cluster

r-----------------------------~----------------------------_.------------------------------<>A+IOWAI

,-- 1----'
112

r------l
,

r-----------------~----_1~--------------------_+----~._------~._--+_._----~I~C

,
I

GNO

100,000,

~~82l

Q2
DEC 3639

018
I
1
0-882
017
0-882

013
0-882
012
0-884
II

015

Eo-_____....+-'-.....-o'

D-884

Lo--t....-

.....-o

010
0-884

---,
II.
1

T
R7
115,000

7,Il00 1

018
0-882

Dli

0-884

II.
7,1500
15~

~----~--~2~1~----------------~----~~--------------------_4------e_------------~e-----~o.-ev

EXAMPLE OGL2 .J:
L.. _____________

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W; 5"1.
PRINTED CIRCUIT REV. FOR
OGL BOARD IS SIB

8-CS- R111-0- 1 Diode Gate

r-ExAMPCE--l
r-__________-.~___________.------------~------------~------------~----------~~0-G-L-5--_+,-------------oA.IOV(A)

r-------,

r-----~----~~----~----_.------+_----~------+_----_.------~----~----~+4--~~----~--~~----+-OCGNO

08
:
0-862,
09
I
0-6621

1
010
1
0-662~

Oil

~~r-----+-~~~------~~~-+----~--'~---~------r-~~~-----+--~-+-++---~~~~---r~6

0-662 1
:
I

I
I

r-----~------~----.-----~-~--_.~--~--~~~----r_OB-15V

UNLESS OTHERWISE INDICATE 0:
RESISTORS ARE 1/4W;!I%
DIODES ARE 0-664
TRANSISTORS ARE DEC 3639B
PRINTED CIRCUIT REV. FOR
OGL BOARD IS SIA

B-CS-S 107-0-1

~.O 43

~~044

~~045

Inverter

~~46~ ~049

~~047

~~050

~~048

r-. A.IOV(A)

~'04
~I
()

...

?l
1\

R4
100,000

DI~~ ~

0-66

~ F .. ' ~g~62
D5
~

080Poo' ~016

08
R3

.ql 09,
J

C2
o..!;

~ '8~i:2
,g~62
.. '

Orl

R2
12,000
10%

~07

R5
3,000

N~fi¥
....

...

'029),
0-662

R6
012
3,000 .4.

~7
R9
12,000
10%

Folg,OOO ~ '035

...

.a ... ~ ~8l~62
023

....

RI
12,000
10%

~'025
C3

~~
1\

RI4
100,000

0.1.1

027
RI3

r- C GNo
~

0].4

~ ,O~
0-662

-'IIo.L '

9T 1 S

'8_3l62

12rg~~

1"8~262

oj7

r-.

...

RI7

.~~ ;: r::

...,

RII
12,000
10%

RI2

121g2/~

1~~026

RI5
3,000

030

r-.
RIO

RI6
3POO

~~031

RI9
12,000
10"1.

MFO
R20

011

INDICATED

0'52

TRANSISTORS ARE DEC 3639C
RESISTORS ARE 15,000
RESISTORS ARE 1/4W 15%
CAPACITORS ARE M MFO
DIODES ARE 0- 664

B-CS-S202-0-1

Dual Flip-Flop

8~~2

~'g~~62
~ , g:~62

121'8~~
~

1
UNLESS OTHERWISE

LWI !l00

B-I!lV

U
A+lOY(A)

C GNO
048
0-882
045
0-882
044
0-882
043
0-882
B-IIIV

1,Il00

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W; 5%
CAPACITORS ARE MMFO
DIODES ARE 0-864
TRANSISTORS ARE DEC 3639C

B-CS-S203-0-1

R3
10000
5"4

,,~Oll

R23
47

...

",2

~
,.....
R2
15pOO
5..,.

....

...-R5 .4
l,eoO
5%

R4 ~
RI
12,000 12dOOO

P~010

~012

8~1

"044

,.....

DJl

R9
15,000

RI2
1,500
5"10

~2~00

5 ¥o

..I '045

UO:

I>J.6

013

;::
~

5..,.

'09
0

R24
47

~~
1\

:;iio

DEC
\h 2894-28

...

.. ~035

V...,
RI4 ..
3,000

.,024

....

5"10

RI5
~2~00
S

O!O
.'047

·'048

8~(
1\

,.....-

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W; 10..,.
CAPACITORS ARE MMFO
DIODES ARE 0-664
TRANSISTORS AR E DEC 3639-C

B-CS-S603-0-1

)

>f~~oo

RII ~ '021
~2~00

~9 -----.
....

Pulse Amplifier

RI9 ..
1,500
5"10

RI8

~034

R21 .4
3,000
5..,.

~&200

DEC
~ 2894-28

;:~~;O

A.. IOV(A)
C,H,N,U
GNO

~,040
0-68

?j3

~'B~2

5..,.

.;.

R25
47

10,000

~'B~J62

0.1.2

~ .,022

,..

", ~
100,000
5%

.. ...

5..,.

...

....

R7 .4
3,000

10,000

~ 03

.. ~.18-662

~ ~023

~·~~62

:::i~o

DEC
\.b:. 2894-28

O..!,I
;:

100pa
",0
5"4

~'B?662
~ ~8-8862

"~~

10,000

Triple Flip-Flop

~036

~i
~

.01
C7
MFD;: ~.Ol

Ug~:6

MFO ..

......-

R22
1,500
5..,.

~g~:6

~'g~:8

..., B-IIIV

'033

..
,... .

032

'049

r-__________~--------._--------~--------._--------~--------_.--------_.--------_.----------~r~-.---------~'------OB-IIIV

R2
3,000

3,000

012

010

Dl4

0111

Rill
3,000

023
0-662

02
,01
MFO

021
0-682

C aND
I
Oil
0-882:
N

I
018
0-682 :

CI
,01
liFO
011

011

I
017
0-882\
I
\
016
0-6821

013

-3V

I
\
I

I
:

-3V

1
L STRATE
_____ ...J\

UNLESS OTHERWISE INDICATED:
RESISTORS ARE V4W', II..
DIODES ARE 0-884

B-CS-WOOS-O- 1 Clamped Loads

RIO
330

R7
7,500
!5%

lMLESS OTHERWISE INDICATED'
RESISTORS ARE 1/4W; 10..
DE I - DE 4 ARE DEC NO. 330-2I1E-6

B-CS-W300-0- 1 Delay Line
35

C3
,01
liFO

M GNO

C GNO

r-------------------------~----_+--------~~----------------------~~----+_--------OA

+IOV
RI2
100,000

Ol~

RI6
10,000

10·1.

Ko---1

470
MMFD
100V

100
10%

022
0662
021
0662

C2
.01
MFD

020
0662

019
0662
-7.~V

CIO
RI5
390
10"10

6.8

RI7

MFO

I,~OO

~g~o +

~----------~----~~----~----~----~--------------_4------~----~~----~----~------~~~------~__oB

-I~V

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 114W; ~ 'Y.
DIODES ARE 0664

Pulse Amplifier

B-CS-W612-0-1

A
+IOV
r--1~--~--------~----~-------------.-------.~o~le~-.----~~-.----~--------.-----~------------~------~~0~52~~-oCGNO

+CII
..-=..=....:..!c...;.;;.;-=-______-I-______... 0662
015
59
0662
014
0662
013
0662

RI2
7,500

RI4
1,500

- MFO

.-.-+-41 028

0662
011
0862
R2
1,500

+CIO
at

0662
030
0662
029
0662

.-.-+-41 012

RI
1,500

0682

.-=.=..:...0..=:...:.._____-1-______... 051

-MFO

0882
027
0882

D25
RI5
1,500

RI8
1,500

R28
7,500

R28
1,000

~----~--~._----~~_.----~------------~~--~~~----~~--~~--~~----~--~----_+------------~----~~------_oB-IIIV

RI3
1,000

R27
1,000

T u-"V'.Ar__----U U

KC>-"V\,."......---o L

RII
20,000
1/2W
BOURNS OR
OAYSTROM

018

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 114Wj 5'l1o
CAPACITORS ARE MMFD
DIODES ARE D864
TRANSISTORS ARE OEC3839

B-CS-R302-0-1

One-Shot Delay

021

023

R211
20,000
1/2W
BOURNS OR
OAYSTROM

DIGITAL EQUIPMENT CORPORATION. MAYNARD. MASSACHUSETTS
Printed in U.S.A.