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DEC-09-I2AA-D

February 1969

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Document:	KE09A
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INSTRUCTION MANUAL
EXTENDED
ARITHMETIC ELEMENT
KE08A

DIGITAL EQUIPMENT CORPORATION. MAYNARD. MASSACHUSETTS

Cvrf~
DEC-b9-I2AA-D

INSTRUCTION MANUAL

KE09A
EXTENDED ARITHMETIC ELEMENT

DIGITAL EQUIPMENT CORPORATION. MAYNARD. MASSACHUSETTS

1 st Printing July 1968
2nd Printing February 1969,...-...

Instruction times, operating speeds and the like are included in this manual for reference only; they are not to
be taken as specifications.

.
The following are registered trademarks of Digital
Equipment Corporation, Maynard, Massachusetts:
PDP
FOCAL
COMPUTER LAB

DEC
FLIP CHIP
DIGITAL

CONTENTS

Page
CHAPTER 1
INTRODUCTION
1.1

Purpose

1-1

1.2

Related Documents

1-1

1.3

Power Requirements

1-1

1.4

Engineering Drawings and References

1-1

1.5

Spec ifi cations

1-2

1 .5. 1

Functional Characteristics

1-2

1.5.2

Operating Characteristics

1-2

CHAPTER 2
INSTALLATION AND OPERATION
2.1

Insta Ilation

2-1

2.2

Manual Controls and Indicators

2-1

2.3

Programming Considerations

2-1

CHAPTER 3
PRINCIPLES OF OPERATION
3. 1

Instruction Fetch and Op Code Decoding

3-1

3.2

EAE Command Decoding

3-1

3.3

Timing and Flow

3-2

3.4

Setup Instructions

3-2

3.5

Shift Instructions

3-9

3.6

Normalize Instructions

3-21

3.7

Multiply Instructions

3-24

3.8

Divide Instructions

3-33

3.8. 1

DIV(S) Instructions

3-34

3.8.2

IDIV(S) Instruction

3-45

3.8.3

FRDlV(S) Instruction

3-46

3.8.4

Divide Overflow

3-46

3.9

EAE Instruction Development

3-48

iii

CONTENTS (Cont)
".......,

Page
CHAPTER 4
MAINTENANCE
4. 1

General Maintenance

4-1

4.2

Maintenance Program Tapes

4-1

4.3

Replaceable Parts

4-1
CHAPTER 5
ENGINEERING DRAWINGS

5. 1

Signal Mnemonic Index

5-1

5.2

Drawing List

5-2
ILLUSTRATIONS

3-1

EAE Timing

3-3

3-2

LRS, LRSS Register Manipulation (One Position)

3-13

3-3

LLS, LLSS Register Manipulation (Two Positions)

3-19

3-4

ALS, ALSS Register Manipulation (Three Positions)

3-20

TABLES
2-1

Operating Controls and Indicators

2-1

2-2

EAE Instructions

2-2

2-3

EAE Operation Times

2-5

3-1

EAE SETUP Instruction Format

3-4

3-2

OSC Functions

3-4

3-3

OMQ Functions

3-5

3-4

CMQ Functions

3-6

3-5

LACS Functions

3-6

LACQ Functions

3-7

ABS Functions

3-7

3-8

CLQ FtJnctions

3-8

3-9

LMQ Functions

3-8

3-10

GSM Functions

3-9

3-11

EAE Shift Instruction Format

3-10

3-12

LRSS Functions

3-11

3-13

LLSS Functions

3-14

TABLES (Cont)
Page

3-14

ALSS Functions

3-16

3-15

EAE NORM Instruction Format

3-21

3-16

EAE MUL Instruction Format

3-24

3-17

MULS Functions

3-26

3-18

MULS Arithmetic

3-31

3-19

MULS Functions

3-32

3-20

MULS Functions

3-32

3-21

MULS Functions

3-33

3-22

EAE DIV Instruction Format

3-34

3-23

DIVS Functions

3-36

3-24

DIVS Arithmetic

3-43

3-25

DIVS Functions

3-44

3-26

DIVS Functions

3-44

3-27

DIVS Functions

3-45

3-28

DIV OV Functions

3-47

3-29

EAE Microinstructions

3-48

4-1

EAE Module Complement

4-1

CHAPTER 1
INTRODUCTION

This manual contains operation and maintenance information for the KE09A Extended Arithmetic
Element (EAE) of the Programmed Data Processor PDP-9, manufactured by Digital Equipment Corporation,
Maynard, Massachusetts. For a complete understanding of the option and its relation to the basic PDP-9
system, the user must be thoroughly familiar with the contents of the PDP-9 Maintenance Manual, F-97.

1.1

PURPOSE
The EAE option facilitates high-speed multiplication, division, shifting, normalizing, and

register manipulation. Installation of the EAE adds an lS-bit multiplier-quotient register (MQ) and a
6-bit step counter (SC) to the basic PDP-9 system. The option logic occupies space in the central processor wing of the basic PDP-9 system, as indicated in the CP UML drawing KCS. All logic module locations have been prewired into the system. The contents of the MQ can be selected by the REGISTER
DISPLAY switch on the PDP-9's operator console for display in the REGISTER indicator.
The EAE operates asynchronously with the basic system, permitting computations to be performed in the shortest possible time. Furthermore, instructions can be microcoded so that several nonconflicting EAE operations can be performed by one instruction, thereby simplifying arithmetic programming. Maximum multiplication and division time is 12 \JS.

1.2

RELATED DOCUMENTS
The PDP-9 library offers a complete package of single- and multiple-precision programming

routines for use with the EAE. These and other related documents and tapes are listed in Chapter 1 of
the PDP-9 Maintenance Manual.

1.3

POWER REQUIREMENTS
The EAE needs no source of primary or dc power other than that already furnished with the

basic PDP-9 system. All necessary power is prewired to the module locations.

1.4

ENGINEERING DRAWINGS AND REFERENCES
Throughout this manual all references to EAE option drawings and basic PDP-9 system drawings

are abbreviated as in the PDP-9 Maintenance Manual. Refer to Chapter 1 of the Maintenance Manual
for abbreviation codes.

As an aid to understanding the EAE, a simplified version of LINC Control

drawins KC15 alons with a portion of EAE logic appears on an illustration at the end of this manual.

1-1

Chapter 5 of this option manual contains a complete set of EAE option drawings indexed by
their full drawing number codes, along with all module circuit schematics.

1.5

SPECIFICA TIONS

1 .5.1

Functional Characteristics
The EAE enables fast, flexible, hardware execution of the following signed or unsigned

functions.
a.

Shifting the contents of the primary arithmetic registers (AC, MQ) right or left, requires

4 to 18 ,",S.

b. Normalizes the quantity in the primary arithmetic registers, i.e., shifts the contents
left to remove leading binary Os for the purpose of preserving as many significant bits as possible. The
time required is 4 to 18 ,",S.
c.

Multiplication is performed in 5 to 12 ,",S.

d. Division including integer divide and fraction divide require 5 to 12 fJS. Divide overflow indication is furnished by the LINK when signed division produces a quotient exceeding ± 3777778
in magnitude, or unsigned division produces a quotient exceeding 7777778 in magnitude.
e. Basic setup instructions to manipulate the data in the registers preparatory to execution
of the above instructions requires 2 ,",S.

1.5.2

Operating Characteristics
Heat Dissipation

108 BTU/hr

Power Dissipation

0.032 kW

1-2

CHAPTER 2
INSTALLATION AND OPERATION

2.1

INSTALLATION
Complete installation of the EAE option merely involves plugging the logic modules into their

assigned locations in the central processor wing ,and ascertain ing that certain jumpers are removed. The
following jumpers are in place to allow FORTRAN programming without the EAE. They must be removed
for EAE operations (refer to drawing KC27).

2.2

ACO -

LINK from E04R to E04B.

ADRL(B) from B03D to B03N.

MQI(l )/EAE OR ARO from D22P to D23J.

TEMP 1(1) from B03C to B03T.

SCO(1) from B31C to B31P.

MANUAL CONTROLS AND INDICATORS
The EAE option contains no manual controls and indicators other than those prewired into the

PDP-9 operator's console. Table 2-1 lists and describes these controls and indicators. Refer to the
PDP-9 Maintenance Manual for details.

Table 2-1
Operating Controls and Indicators
Control/Indicator

Function

MQ position displays contents of the MQ register in the REGISTER indicator when the computer is in a stop condition.

2.3

EAE position is presently not used (not wired).

PROGRAMMING CONSIDERATIONS
The EAE option adds the instructions listed in Table 2-2 to the basic PDP-9 instruction reper-

toire. See Table 2-3 for execution times.

2-1

Table 2-2
EAE Instructions
Octal
Code

Mnemonic

Operation

640000

EAE

Basic EAE instruction. Acts as a NOP instruction.

640001

OSC

Inclusive-OR the SC with the AC. The contents of the AC are inclusive-ORed with the contents of the 6-bit SC on a bit-for-bit basis,
and the results are left in AC12 through 17. If corresponding SC and
AC bits are 0, the result is O. If corresponding bits are 1 or differ,
the result is 1. The previous contents of the AC are lost, the LINK
and the SC remain unchanged.

640002

OMQ

Inc lusive-OR the MQ with the AC. The contents of the AC are inclusive-ORed with the contents of the MQ on a bit-for-bit basis,
and the results are left in the AC. If corresponding MQ and AC bits
are 0, the result is O. If corresponding bits are 1 or differ, the result
is 1. The previous contents of the AC are lost, the LINK and the
MQ remain unchanged.

640004

CMQ

Complement the MQ. The previous contents of the MQ are lost, the
LINK and the AC remain unchanged.

641001

LACS

Load AC12 through 17 with the contents of the SC. The previous
contents of AC 12 through 17 are lost, the LINK and the SC remain
unchanged.

641002

LACQ

Load the A.C with the contents of the MQ. The previous contents of
the AC are lost, the LINK and the MQ remain unchanged.

644000

ABS

Get the absolute value of the AC. If the sign (ACOO) of the contents
of the AC is negative, the contents are 1s complemented. The LINK
remains unchanged.

650000

CLQ

Clear the MQ. The previous contents of the MQ are lost, the LINK
and the AC remain unchanged.

652000

LMQ

Load the MQ with the contents of the AC. The previous contents of
the MQ are lost, the LIN K and the A.C remain unchanged.

664000

GSM

Get the sign and magnitude of the AC. Places the sign (ACOO) of
the AC contents in the LINK, and if negative, 1s complements the
contents.

6405XX

LRS

Long Right Shift. Shifts the contents of the LINK, AC, and MQ
right the number of positions indicated in bits XX. The LINK is
usually initialized to 0 and shifted unchanged on each step.

6605XX

LRSS

Long Right Shift, Signed. Shifts the contents of the LINK, AC and
MQ ri9ht the number of positions indicated in bits XX. ACOO is
initially stored in the LINK, then shifted unchanged on each step.

2-2

Table 2-2 (cont)
EAE Instructions
Octal
Code

..~

Mnemonic

Operation

6406XX

LLS

Long Left Shift. Shifts the contents of the LINK, AC and MQ left
the number of positions indicated in bits XX. The LINK is usually
initialized to 0 and shifted unchanged on each step.

6606XX

LLSS

Long Left Shift, Signed. Shifts the contents of the LINK, AC and
MQ left the number of positions indicated in bits XX. ACOO is initially stored in the LINK, then shifted unchanged on each step.

6407XX

ALS

Accumulator Left Shift. Shifts the contents of the LINK and AC left
the number of positions indicated in bits XX. The LINK is usually
initialized to 0 and shifted unchanged on each step.

6607XX

ALSS

Accumulator Left Shift, Signed. Shifts the contents of the LINK and
AC left the number of positions indicated in bits XX. ACOO is initially stored in the LINK, then shifted unchanged on each step.

640444

NORM

Normalize. Shifts the contents of the LINK, AC and MQ left until
ACOO and ACOl differ or until the maximum of 36 shifts (44g) occur.
The LINK is usually initialized to 0 and shifted unchanged on each
step.

660444

NORMS

Normalize, Signed. Shifts the contents of the LINK, AC and MQ
left until ACOO and ACOl differ or until the maximum of 36 shifts
(44g) occur. ACOO is initially stored in the LINK and then shifted
unchanged on each step.

6531XX

MUL

Multiply. Multiplies the number in the AC (multiplier) by the number in the next core memory location (multiplicand) to form a product
in the AC and MQ. MUL transfers the multiplier to the MQ, clears
the AC, and fetches the multiplicand from memory. Bits XX command
the desired precision of the product (228 or 1810 steps for maximum
36-bit precision). The LINK must be cleared previously and remains
unchanged.

6571XX

MULS

Multiply, Signed. Multiplies the number in the AC (multiplier) by
the number in the next core memory location (absolute value multiplicand) to form a signed product in the AC and MQ. ACOO and
ACOl receive the product sign. A previous LAC/GSM/DAC CAND
sequence places the multiplicand sign in the LINK and the absolute
value in memory. MULS transfers the multiplier to the MQ, performs
ls complements of the multiplier if its sign is negative, fetches the
absolute value multiplicand from memory, and clears the LINK. Bits
XX command the desired precision of the product (228 or 18 10 steps
for maximum 36-bit precision).

2-3

Table 2-2 (cont)
EAE Instructions
Octal
Code

Mnemonic

Operation

6403XX

DIV

Divide. Divides the number in the AC and MQ (dividend) by the
number in the next core memory location (divisor) to form a quotient
in the MQ and remainder in the AC. DIV fetches the divisor from
memory. Bits XX command the desired precision of the quotient and
remainder (238 or 1910 steps for maximum 36-bit precision). The
LINK must be cleared previously and remains unchanged unless divide
overflow occurs. Overflow occurs if the divisor is not numerically
greater than the AC portion of the dividend.

6443XX

DIVS

Divide, Signed. Divides the number in the AC and MQ (36-bit
double-signed dividend) by the number in the next core memory location (absolute value divisor) to form a signed quotient in the MQ
and remainder in the AC. MQOO receives the sign of the quotient
and ACOO receives the original sign of the dividend. A previous
LAC/GSM/DAC sequence places the divisor sign in the LINK and
the absolute value in the memory. DIVS fetches the absolute value
divisor, 1s complements the MQ portion of the dividend if the dividend sign is negative, and clears the LINK. Bits XX command the
desired prec ision of the quotient and remainder (238 or 19 10 steps for
maximum 36-bit precision). The LINK remains cleared unless divide
overflow occurs. Divide overflow occurs if the divisor is not numerically greater than the AC portion of the dividend.

6533XX

IDIV

Integer Divide. Divides the number in the AC (integer dividend) by
the number in the next core memory location (divisor) to form a quotient in the MQ and remainder in the AC. IDIV fetches the divisor
from memory, transfers the contents of the AC to the MQ, then clears
the AC. Bits XX command the desired precision of the quotient and
remainder (238 or 19 10 steps for maximum 36-bit precision). The
LINK must be previously cleared and remains unchanged unless divide
overflow occurs. Overflow occurs only if the divisor is O.

6573XX

IDIVS

Integer Divide, Signed. Divides the number in the AC (signed integer
dividend) by the number in the next core memory location (absolute value
divisor) to form a signed quotient in the MQ and remainder in the AC.
MQOO receives the sign of the quotient and ACOO receives the original
sign of the dividend. A previous LAC/GSM/DAC sequence places the
sign of the divisor in the LINK and the absolute value in memory.
IDIVS fetches the absolute value divisor, transfers the contents of the
AC to the MQ, 1s complements them if the dividend sign is negative,
and clears the AC and LIN K. Bits XX command the desired prec ision
of the quotient and remainder (238 or 1910 steps for maximum 36-bit
precision). The LINK remains cleared unless divide overflow occurs.
Overflow occurs only if the divisor is O.

2-4

Table 2-2 (cont)
EAE Instructions
Octal
Code

Mnemonic

6503XX

FRDIV

Fraction Divide. Divides the number in the AC (fraction dividend)
by the number in the next core memory location (divisor) to form a
quotient in the MQ and remainder in the AC. The binary point is
assumed to be at the left of ACOO. FRDIV fetches the divisor from
memory and clears the MQ. Bits XX command the desired precision
of the quotient and remainder (238 or 19 10 steps for maximum 36-bit
precision). The LINK must be previously cleared and remains unchanged unless divide overflow occurs. Overflow occurs if the divisor is not numerically greater than the dividend.

6543XX

FRDIVS

Fraction Divide, Signed. Divides the number in the AC (signed
fraction dividend) by the number in the next core memory location
(absolute value divisor) to form a signed quotient in the MQ and remainder in the AC. The binary point is assumed at the left of AC01 •
MQOO receives the sign of the quotient and ACOO receives the original sign of the dividend. A previous LAC/GSM/DAC sequence
places the sign of the divisor in the LINK and the absolute value in
memory. FRDIVS fetches the absolute value divisor, clears the MQ
and LINK, and 1s complements the contents of the AC if the dividend
is negative. Bits XX command the desired prec ision of the quotient
and remainder (238 or 19 10 steps for maximum 36-bit prec ision). The
LINK remains cleared unless divide overflow occurs. Overflowoccurs if the divisor is not numerically greater than the dividend.

Operation

Table 2-3
EAE Operation Times
Number of Shifts*
0
1
2,3,4
5,6,7
8,9,10
11,12,13
14,15,16
17,18,19
20,21,22
23,24,25
26,27,28
29,30,31
32,33,34

35,36

SETUP ,SHIFT,
NORM Instructions
2**
4
5
6
7
8
10
11
12
13
14
16
17
18

MUL, DIV Instructions
5***
5
6
7
8
10
11
12

* In itia I step count.
**SETUP Instructions.
***DIV OV causes divide operation to stop here. MUL and DIV instructions containing initialized step
count of 0 stop here with no arithmetic operations undertaken.
2-5

•

CHAPTER 3
PRINCIPLES OF OPERATION

This chapter describes the EAE option in terms of its instruction repertoire and the logic that
implements those instructions. The discussions include references to the logic drawings in Chapter 5 and
to pertinent drawings of the basic PDP-9 system.

3.1

INSTRUCTION FETCH AND OP CODE DECODING
EAE instructions are fetched from core memory through the fetch cycle processes as are all

PDP-9 instructions. The PDP-9 Maintenance Manual explains the fetch cycle processes in detail.
Briefly, the BGN process word (10) which concludes a previous execute cycle transfers the current address held in the PC to the MB and starts the next core memory and control memory read operations.
MA JAM transfers the current address from the MB to the MA, the core memory cycle starts, and the
fetch entry process word (21) is extracted from control memory. Process word 21 increments the address
in the MB and transfers it to the PC for the next following fetch cycle (MBO, + 1, PCI).
The next CM process word(12) occurs while the core memory reads the addressed memory
word into the sense amplifiers. Processes evolved from process word 12 transfer this (instruction) word
from the sense amplifiers to the MB, and also gate the op code portion into the IR (SAO, MBI, IRI).
The contents of the AC are gated into the AR (ACO, ARI).
The next process word address held in the address portion (CMAOO through 05) of process word 12
is 24. On drawing KCI2, the op code detection circuits decode the op code bits IROO, IROl, IR03.
These bits, all in the 1 state for an EAE op code of 648 , produce the REP signal. REP allows the IR bits
to modify the control memory address on drawing KCI7, boosting this next CM address from 24 to 75.
This is the third and last process word extracted during the normal, I-fJs fetch cycle. All EAE operations
start from this" EAE execute entry" process word.

3.2

EAE COMMAND DECODING
The EAE option contains an instruction register (see drawing KE4) which accepts bits SA09

through 11 of the instruction word during process 12. These bits contain the code for a particular EAE
instruction class, and are fed directly from the register EIR09-11 into the Binary-to-Octal Decoder
S151-H02. The 5151 module decodes the octal class code to supply an output command level denoting
one of the following seven EAE instruction classes.
08

SETUP instructions

MUL (Multiply) instructions

3-1

Not used

DIY (Divide) instructions

NORM (Normalize) instructions

LRS (Long Right Shift) instructions

LLS (Long Left Shift) instructions

ALS (Accumulator Left Shift) instructions

The pertinent command level remains on throughout the succeeding EAE execution processes
to determine the particular execute operation, starting with process word 75. The paragraphs that follow discuss each instruction class in detail.

3.3

TIMING AND FLOW
Figure 3-1 is a compasite timing diagram for all EAE instruction classes, showing machine

cycle time versus process word branching for the various classes. The diagram can be correlated with
the operation times listed in Table 2-3 and the flow diagrams KE5 and KE6. Examination of Figure 3-1
reveals the following general features on operating times.
a. All SETUP instructions require two machine cycles, progressing toward the BGN process
word (10) that starts the next instruction fetch cycle.
b. All SHIFT instructions, including NORM, branch to process word 50 and continue in accordance with the number of shifts (steps) programmed in bits 12 through 17 of the shift instruction word.
c. All MUL and DIY instructions branch to process word 51 and continue in accordance with
the number of sh ifts (steps) programmed in bits 12 through 17 of the instruction word.
Important features not apparent in Figure 3-1 are: for/all instructions other than MUL or DIY,
core memory is idle after the initial instruction fetch; for MUL and DIY instructions a core memory cycle
occurs during process word 51 in which a multiplicand or divisor is fetched. Thereafter, core memory is
not needed by the EAE during the execute cycles, and may be accessed by the DMA channel as a timesaving feature. Ordinarily, the last process word in the fetch cycle contains an SM (start memory) bit
in order to read an operand from memory during the execute cycle. In process word 75 this SM bit is
absent (O), leaving the memory idle. In process word 51, the SM bit is present (1) to start a memory
cycle for MUL or DIY.

3.4

SETUP INSTRUCTIONS
Nine 2-cycle SETUP instructions manipulate the data in the prime arithmetic registers (AC,

MQ) in preparation for execution of the arithmetic operations commanded by succeeding MUL and DIY
instructions. Table 3-1 shows the instruction format. Table 3-2 through 3-10 list the logic functions
that implement the instructions, referencing the appropriate logic drawings.

3-2

•

"ADVP" Checks that the memory location following the multiply and/or divide

instruction is not modified by the execution of the instruction and that the program address counter is
properly incremented during the execution of the instruction.
b.

liNEAE" Set up check - Checks the set-up of all EAE signed, unsigned, integ0r

and fraction, multiply and divide instructions. These instructions are executed with a shift count of
zero.
c.

"SHCT" Shift Counter Test - Executes the Multiply instruction sequentially starting

at a shift count of 1 and incrementing it up to a shift count of 22.
d.

"STMUl" Sign multiply and divide test - Test all signed multiply and divide

"MUlTST" Multiply and Divide Test - This test using worse-case number patterns

instructions.

acts as both a EAE and Adder Test.
f.

"MSPEED" Speed Multiply and Divide - This test is in three operations: (1) a

sequence of multiply instructions are executed back to back, (2) then a sequence of divide instruc'ions
~re executed, (3) followed by a sequence of MUl, DIY, MUl, and DIY executed back to back.

4.2.2

Section 2 Random Data Multiply and Divide Test - The Random Data Test verifies that the

EAE will multiply and divide random numbers at shift counts 1 through maximum (22 for multiply, 23 for
divide) and checks that the liNK is set on divide averflow.
The sequence of testing is as follows:
a.

Test the Multiply
(1)

Generate a random number

(2)

Do a software multiply

(3)

Do a hardware multiply

(4) Compare the results of both operations
(5)
b.

LOOP BACK TO 1 Till DONE

Test the Divide
(1)

Generate a random number

(2)

Do a software divide

(3)

Do a hardware divide

(4) Compare the results of both operations
(5)

lOOP BACK TO 1 TILL DONE

'P$

234567890

12t-+2---~-175-+3--14t--l54140--ltO
2

50 --142--155

ns (HUNDREDS)

NEXT FETCH (SETUP)
SHtFT
MUL,Dtv

NEXT FETCH (tSHIFT)
SHIFT

56-.157140

-I-

_ItO

NEXT FETCH (8,9,tO SHIFTS)

50--l42--155--l53-156-157140--ltO~_- NEXT FETCH (tt,t2,t3 SHIFTS)

50-142-155---1- SHIFT

(t4,t5,t6 SHIFTS)

o
40
t2

234

--ltO

234567890

-I..

50-142-155-153--156--157--140

--ltO

ns (HUNDREDS)

--=1=

150--l42-155--l53 --156

NEXT FETCH (t7,t8,t9)
NEXT FETCH (20,2t,22)
SHIFT

(23,24,25)
(26,27,28)

(29,30,3tl

40
t8

--ItO

_I..

50--142-155-153--156 - 1 57 --1 40

NEXT FETCH (32,33,34)

-------1~ojtO -----0_*1••-

Figure 3-1

EAE Timing

..-...,

3-3

NEXT FETCH (36 SHIFTS)

Table 3-1
EAE SETUP Instruction Format
SETUP
08

Op Code
648
0

Not Used
12

OSC

OMQ

CMQ

LACS

LACQ

ABS

CLQ

LMQ

GSM

Table 3-2
OSC Functions
640001

Inclusive-OR the SC with the AC

Process

Function

(ACO ,ARI, EAE, LI,CONT ,CMA43)
ACO(I) = ACOO-17 - A BUSOO-17
A BUSOO- 17 - ADROO-17
NOSH = ADROO-17 - 0 BUSOO-17
ARI(l) == 0 BUSOO-17 - AROO-17
LI(l) == ADRL = LINK - LAR
LI(l) = ADRL = LINK - TEMP3
SA09(0)ASA 1O(O)ASA 11 (0) == SETUP
EAE(l)AARI(l) = SUI (1)
SUI (1) = 0 - SCOV ,SCOV2,FIRST ,EAE RUN, EAE SIGN,MQ
SIGN
SUI (1)AMB05(0) = EAE OR MQO
CM STROBEACONT(1) = GO TO 43

(ACI,EAE,CONT ,CMA41)

Drawing No.
KC18
KC20
KC21
KC20
KC20
KC15
KE3
KE4
KE3
KE2-3
KE3
KC16
KC18

CM STROBEAEAE OR MQO == MQO(I)
MQO(l) = MQOO-17 - A BUSOO-17
A BUSOO-17 - ADROO-17
NOSH == ADROO-17 - 0 BUSOO-17
ACI(1) = 0 BUSOO-17 - ACOO-17
LI(O) = LAR - LINK
CM STROBEACONT(1) = GO TO 41

3-4

KC19
KC20
KC21
KC20
KC20
KC15
KC16

Table 3-2 (cont)
OSC Functions
640001

Inclusive-OR the SC with the AC

Process

Function

(ACO ,MQI/EAE/CONT ,CMA54)
ACO(l) = ACOO-17 - A BUSOO-17
A BUSOO-17 - ADROO-17
NOSH = ADROO-17 - 0 BUSOO-17
MQI(l) = 0 BUSOO-17 - MQOQ-17
EAE(l)AMQI(l)ASETUP == SU3(1)
SU3(l) = SCOV(l)
SU3(l) = SCOV2(l)
MQI(l)AMB08(0)AEAE(1) == EAE OR ARO
CM STROBEACONT(l) = GO TO 54

(ACI I EAE-R I CONT I CMA40)

(EAE I DONE ,CMA 10)

KC20
KC21
KC20
KC20
KE3
KE3
KE3
KE3
KC16

KC19
KE2
KC20
KC21
KC20
KC22
KC20
KE3
KC16
KC18

CLK(B) + 670 ns A EAE(l)ADONE(l) = INPUT 10 RESTART
INPUT 10 RESTART == 10 REST ART
10 RESTART == GO TO 10
10

KC18

CM STROBEAEAE OR ARO == ARO(l)
EAE-R(l)AMB17(l)ASETUP = SCO
ARO(l) == AROO-17 - A BUSOO-17
A BUSOO-17 - ADROO-17
NOSH = ADROO-17 - 0 BUSOO-17
SCO = SC 12- 17 - 0 BUS 12-17
ACI(l) = 0 BUSOO-17 - ACOO-17
EAE-R(l) == 0 BUS L - TEMP2
CM STROBEACONT(l) = GO TO 40
40

Drawing No.

(PCO / SM / CMA21)

KD3(3)
KD3(3)
KC16
KC18

BGN next fetch

Table 3-3
OMQ Functions
640002

Inclusive-OR the MQ with the AC

Process

Function

Drawing No.

Same as OSC

Same as OSC plus
SU3(l)AMB16(l) == EAE OR MQO

KE3

(ACI I EAE-R I CONT I CMA40)

KC18

CM STROBEAEAE OR ARO = ARO(l)
CM STROBEAEAE OR MQO = MQO(l)

3-5

KC19
KC19

Table 3-3 (cont)
aMQ Functions
640002

Inc lusive-OR the MQ with the AC (cont)

Process

Function

54 (cont)

ARO(l) = AROO-17-A BUSOO-17
MQO(l)= MQOO-17-A BUSOO-17
A BUSOO-17-ADROO-17
NOSH = ADROO-17-0 BUSOO-17
ACI(l) = 0 BUSOO-17-ACOO-17
EAE-R( 1) = 0 BUS L- TEMP2
CM STROBEACONT(l) = GO TO 40

Drawing No.
KC20
KC20
KC21
KC20
KC20
KE3
KC16

asc

Same as

Same as OSC

Table ~-4
CMQ Functions
640004

Complement the MQ

Process

Functions

asc
Same as asc

Same as OSC plus:

Same as

SU3(l)AMB15(l) = CMPL
CMPL = ADROO-17 BUSOO-17

Drawing No.

KE3
KC20

Same as OSC except:
MB17(0) =

Same as OSC

sca

Table 3-5
LACS Functions
641001

Load the AC with the SC

Process

Function

Same as OSC

Same as OSC except:
MQI(1 )J\MB08(l )AEAE(l) = EAE OR ARO

3-6

Drawing No.

Table 3-5 (cont)
LACS Functions
641001

Load the AC wi th the SC

Process

Functions

Drawing No.

Same as OSC except:
CM STROBEAEAE OR ARO = ARO(O)

Same as OSC

Table 3-6
LACO Functions
641002

Load the A.C with the MO

Process

Function

Same as OSC

Same as OSC plus:

MOI(l)AMB08(l)AEAE(1) = EAE OR ARO
SU3(l)AMB 16(1) = EAE or MOO
(ACI, EAE-R, CONT, CMA40)

Same as OSC

KE3
KC18

CM STROBEAEAE OR MQO = MQO(l)
MOO(l) = MOOO-17-A BUSOO-17
A BUSOO-17-ADROO-17
NOSH = ADROO-17-0 BUSOO-17
ACI(1) = 0 BUSOO-17-ACOO-17
EAE-R(l) = 0 BUS L- TEMP2
CONT(l)ACM STROBE = GO TO 40
40

Drawing No.

KC19
KC20
KC21
KC20
KC20
KE3
KC16

Table 3-7
ABS Functions
644000

Get Absolute Value of AC

Process

Function

Drawing No.

Same as OSC plus:

If ACOO ::; 1, then SU1 (1 )AMB06(1 )AMB07(0)AACOO(1) = CMPL
CMPL = ADROO-17 - 0 BUSOO-17
43

Same as OSC

3-7

KE3
KC20

Table 3-7 (cont)
ABS Functions
644000

Get Absolute Value of AC

Process

Function

Drawing No.

Same as OSC except:
MBI7(0) = SCO

Same as OSC

Table 3-8
C LQ Functions
650000

Clear the MQ

Process

Function

Drawing No.

Same as OSC except:
MB05(l) = EAE OR· MQO

Same as OSC except:
CM STROBEAEAE OR MQO = MQO(O)
MQO(O) = 0 - A BUSOO-17

Same as OSC

Same as OSC except:
MBI7(0) = SCO

Same as OSC

Table 3-9
LMQ Functions
652000

Load the MQ with the AC

Process

Function

Drawing No.

Same as OSC except:
MB05(1) = EAE OR MQO
MB07(l) = EAE OR ARO

KE3

(ACI, EAE, CONT, CMA4l)

KC18

CM STROBEAEAE OR ARO ::; ARO(l)
ARO(l) = AROO-17 - A BUSOO-17
A BUSOO-17 - ADROO-17
NOSH = ADROO-17 - 0 BUSOO- 17
ACI (1) = 0 BUSOO-17 - ACOO-17
LI(O) ::; LAR - LINK
CM STROBEACONT(l) ::; GO TO 41

3-8

KC19
KC20
KC21
KC20
KC20
KC15
KC16

Table 3-9 (cont)
lMQ Functions
652000

load the MQ with the AC

Process

Function

Same as OSC

Same as OSC except:

Drawing No.

MBI7(0) = SCO
40

Same as OSC

Table 3-10
GSM Functions
664000

Get Sign and Magnitude of AC

Process

Function

Drawing No.

Same as OSC except:
If ACOO = 1, then
SUI (l)I\MB06(l)I\MB07(O)I\ACOO(l) = CMPl
CMPl = ADROO-17 - 0 BUSOO-17
SUI (l)I\MB04(1)I\ACOO{l) = A BUS LINK
A BUS LINK = ADRl
SHIFT = ADRl - 0 BUS l
LI(l) = 0 BUS l - LAR(l)

Same as OSC

Same as OSC except:

KE3
KC20
KE3
KC15
KC15
KC15

MBI7(O) = SCO
40

Same as OSC

3.5

SHIFT INSTRUCTIONS
long left, long right, and accumulator-left shift instructions include a step count in bits 12

through 17 which commands the number of bit positions to be shifted. Preliminary operations governed
by the early shift entry process words transfer the 2s complement of the step count into the step counter
SC12 through 17 in the EAE logic, drawing KE2. The SC, then, becomes binary up-counter which steps
toward 0 with each shift process. When the SC reaches 0, it sets a pair of overflow flip-flops SCOV and
SCOV2, in turn, which shut off the shift processes and cause the computer to branch to the BGN next
fetch process word.

3-9

The data to be shifted may be signed or unsigned. For signed data shifts, an early process
word (43) transfers the sign (ACOO) into the LINK, and the LINK is shifted thereafter unchanged. For
unsigned data shifts, the LINK is usually initialized to 0 and shifted thereafter unchanged. Table 3-11
shows the SHIFT instruction format.

Bit 04 of the instruction commands the signed or unsigned operation.

Table 3-11
EAE Shift Instruction Format
Op Code
648
0

Commands Number
of Shifts

Shift
Code
6

LRS

LRSS

LLS

LLSS

ALS

ALSS

* May be used for same functions as EAE SETUP.

Bits 12 through 17 can contain step codes of up to 448 for long register shifts of up to 36 bit
positions. For accumulator left shifts (ALS, ALSS) bits 12 through 17 can contain step codes of up to
228 for AC left shifts of up to 18 bit positions.
Table 3-12 through 3-14 and Figures 3-2 through 3-4 illustrate the operations involved for
LRSS, LLSS, and ALSS instructions caHing for one, two, and three shift steps, respectively. A comparison
of the three reveals the pattern for shifting the data and terminating the instruction.
While the NOSH level generated on drawing KC13 commands direct bit-for-bit transfers between registers, the shift operations make use of the SHLl and SHR1 levels on the same drawing to shift
a bit one position left or right into the receiving register. Register input/output gating and data flow is
as usual from output register to A bus to ADR to 0 bus to input register. These functions are abbreviated
in the tables for conven ience.

3-10

Table 3-12
lRSS Functions
660501

long Right Shift Signed (One Position)

Process

Function

Drawing No.

(ACO,ARI, EAE,LI,CONT ,CMA43)

KC18

ACO(l)AARI(l)ANOSH = AC - AR
SA09(l)ASA 1O(O)ASA 11 (l) = lRS
EAE(l)AARI(l) = SU1(l)
SU1(1) = 0 - SCOV,SCOV2,FIRST,EAE RUN,EAE SIGN,MQ SIGN
SU1(l)ASETUP = SC ClR
SC ClR = 0 - SC
SU1 (l)AMB05(0) = EAE OR MQO
If ACOO = 1, then SU1 (l)AMB04(l)MCOO(l) = A BUS LINK
A BUS LINK - ADRl
LI(l) = ADRl - lAR
LI(l) = ADRl - TEMP3
CM STROBEACONT(l) = GO TO 43
43

15 Comp
to SC

(ACI,EAE,CONT ,CMA4l)

KC18

CM STROBEAEAE OR MQO = MQO(l)
MQO(l)ANOSHAACI(l) = MQ - AC
EAE(l)MCI(l)ASETUP = SU2(l)
~~
SU2(1) = MB12-17= 111110 _ SC (ones ~r
LI(O) = LAR - LINK
CM STROBEACONT(l) = GO TO 41
I

(ACO ,MQI, EAE,CONT ,CMA54)

25 Comp
to SC

-6 (;)i.9')

KC19
KC20-21
KE3
KE2
KC15
KC16
KC18

ACO(l)ANOSHAMQI(l) = AC - MQ
eAt{t)AMQI(l)AMB08(0) = EAE OR ARO
CM STROBEACONT(l) = GO TO 54
54

KC20-21
KE4
KE3
KE2-3
KE2
KE2
KE3
KE3
KC15
KC15
KE3
KC16

(ACI, EAE-R,CONT ,CMA40)

KC20-21
KE3
KC16
KC18

CM STROBEAEAE OR ARO = ARO(l)
ARO(l)ANOSHAACI(l) = AR - AC
EAE-R(l)ASCOV(O) = R-PUlSE
R-PUlSE = 111111 - SC = SC FUll
EAE-R(1)ASCOV2(0) = ADDR 10
EAE-R(l) = 0 BUS L = LINK - TEMP2 (not used)
CMA40AADDR 10 = CMA50
CM STROBEACONT(l) = GO TO 50
(MQO ,ARI, EAE-P ,CONT ,CMA42)
MQO(l)ANOSHAARI(l) = MQ - AR
EAE-P(l)AEAE RUN(O) = FIRST(l)
EAE-P(l)ASCOV2(0) = EAE RUN(l)
EAE-P(l) = 0 BUS l = LINK - TEMP1 (not used)
EAE-P(l) = TEMP2 = LINK - END BITOO (not used)
EAE-P(l) = TEMP3 = LINK - END BIT17 (not used)
CM STROBEACONT(l) = GO TO 42

3-11

KC19
KC20-21
KE2
KE2
KE3
KE3
KC17
KC16
KC18
KC20-21
KE3
KE3
KE3
KC15
KC15
KC16

Table 3-12 (cont)
LRSS Functions
Process
42
I'

3h ift 1

Function
(ACO ,MQI, EAE-R,CONT ,CMA55)

KC18

EAE-R(l)I\SCOV(O) = R-PULSE
R-PULSE = 000000 - SC
EAE-R(1)I\SC FULL = SCOV(1)
EAE-R(1)I\SCOV2(0)I\EAE RUN(1)I\EIRl O(O)I\EIRll (1) = IN SHRl
INSHR1=SHRl
ACO(1)I\SHR 1I\MQI(1) = ACn - Mq,+l)
SHRl = ADR17 - 0 BUS L
EAE-R(1) = 0 BUS L - TEMP2
EAE-R(1) = ADRL - END BITOO
EAE-R(1) = TEMPl = LINK - END BIT17 (not used)
MQI(1)I\SHRl = END BITOO - MQOO
CM STROBEI\CONT(1) = GO TO 55
(ARO ,ACI, EAE-P ,CONT ,CMA53
EAE-P(1)I\EAE RUN(1) = FIRST(O)
FIRST(0)I\SCOV2(0)I\EAE RUN(1)I\EIRl O(O)I\EIR 11 (1) = IN SHR 1
IN SHRl = SHRl
ARO(1)I\SHR1I\ACI(1) = ARn - ACn+l
SHRl = ADR17 - 0 BUS L
EAE-P(l) = 0 BUS L - TEMPl (not used)
EAE-P(l) = TEMP2 - END BITOO
EAE-P(1) = TEMP3 - END BIT17 (not used)
SHRl = END BITOO - ACOO
CM STROBEI\CONT(1) = GO TO 53

(EAE,DONE,~MAI0)

KE3
KE3
KC20-21
KC16
KC18

II.O:;·-}

Cll~(8} I Q "sAeAE{1-)~DOt>Hi(H

KC20-21
KC16
KC18

(ARO ,ACI,EAE-R,CONT ,CMA40)

KE2
KE4
KE2
KC20-21
KC18

(ACO ,MQ I, EAE-P ,CONT ,CMA57)

EAE-R(1 )I\SCOV2(1) = EAE RUN(O)
EAE RUN(0)I\SCOV2(l) = ADDR 10
ARO(1)I\NOSHI\ACI(l) = AR - AC
CM STROBE CONT(l) = GO TO 40
40

KE3
KE4
KC13
KC20-21
KC15
KE3
KC15
KC15
KC20
KC16
KC18

(MQO,ARI,EAE-R,CONT ,CMA56)

ACO(l)I\NOSHI\MQI(1) = AC - MQ
CM STROBEI\CONT(1) = GO TO 57
57

KE2
KE2
KE2
KE4
KC13
KC20-21
KC15
KE3
KC15
KC15
KC20
KC16
KC18

EAE-R(1)I\SCOV(1) = SCOV2(1)
SCOV2(l) = IN SHRl
SCOV(1) = R-PULSE
MQO(1)I\NOSHI\ARI(1) = MQ - AR
CM STROBEI\CONT(l) = GO TO 56
56

Drawing No.

INPUT 10 RESTART = 10 RESTART
10 RESTART = GO TO 10
(PCO ,SM,CMA21)
BGN next fetch

3-12

= INPUT 10 RESTART

KD3(3)
KD3(3)
KC16
KC18

NOTE
CML 42 Set SCOV, CML 53 Set SCOV2, and CML 57
reset EAE RUN which inhibited the generation of ADDR
10. If the shift process has not reset EAE RUN when
CML 40 is pointed to, it will go back through CMLls
50, 42, 55, 53, 56, 57, and then to 40.

LINK

6
L

~
L

AC •• -17

MO• • -17

AC •• -17

MO •• - 17

MO • • -17

~
AC •• -17

MOM - 17

I L

lAC . . - 16 1

LOST

~31

I ACI7 I Mo.,,- ,6 1

I L lAC •• - 16 1

f
~61

I Ac,17JM o•• - ,6 1

I ACI71 MO•• - ,6 1

f
L

lAC •• - I

L.--,--I_----'-f_--'f
~71

lAC." - I 6

I I

AC I 7

MO •• - I 6

I L

lAC •• - 16 1

4. DONE

Figure 3-2

LRS, LRSS Register Manipulation (One Position)

3-13

Table 3-13
LLSS Functions
660602

Long Left Shift, Signed (Two Positions)

Process

Function

Same as LRSS except:
SA09(l)ASA lO(1)ASA 11 (0) = LLS

Drawing No.

KE4

Same as LRSS except:
SU2(1) = 111101- SC

Same as LRSS

Same as LRSS except:
R-PULSE= 111110-SC

Shift 1

(MQO ,ARI, EAE-P, CONT, CMA42)
EAE-P(1 )AEAE RUN (0) = FIRST(l)
EAE-P(1)ASCOV2(0) = EAE RUN(1)
EAE-P(1)ASCOV(0)AEIR09(1)AEIR11(0)=" IN SHL 1
IN SHL1 = SHL1
MQO(1)ASHL1AARI(l) = MQn -ARn-1
SHL1 ADROO ... 0 BUS L
EAE-P(1) = 0 BUS L -TEMP1
EAE-P(1) = TEMP2-END BITOO
EAE-P(1) = TEMP3-END BIT17
SHL1 = END BIT17-AR17
CM STROBEACONT(1) = GO TO 42

(ACO, MQI, EAE-R, CO NT ,CMA55)
EAE-R(1 )ASCO V(O) = R-PULSE
R-PULSE = 111111- SC = SC FULL
EAE-R(1y\SCOV2(0)AEAE RUN(1)AEIR09(1)ALRS = IN SHL 1
IN SHL1= SHL1
ACO(1)ASHL1AMQI(1)= ACn-MQn-1
SHL1 = ADROO-O BUS L
EAE-R(l)= 0 BUS L-TEMP2 (lost)
EAE-R( 1) = TEMP 1- EN D BIT17
SHL 1= END BIT17-MQ17
CM STROBEACONT(l) = GO TO 55

Shift 2

(ARO ,ACI, EAE-P, CONT ,CMA53)
EAE-P(1)AEAE RUN(1) = FIRST(O)
EAE-P(ly\SCOV(O)AEIR09(1)AEIR11(O) = IN SHL1
IN SHL1 = SHL1
ARO(1)ASHL1AACI(l)= ARn -ACn-l
SHL 1 = ADROO-O BUS L
EAE-P(1) = 0 BUS L -TEMPl
EAE-P(l)= TEMP2-END BITOO (lost)
EAE-P(l)= TEMP3-END BIT17
SHL1 = END BIT17-AC17
CM STROBf,.\CONT(l)= GO TO 53
3-14

KC18
KE3
KE3
KE4
KC13
KC20-21
KC15
KE3
KC15
KC15
KC20
KC16
KC18
KE2
KE2
KE4
KC13
KC20-2l
KC15
KE3
KC15
KC20
KC16
KC18
KE3
KE4
KC13
KC20
KC15
KE3
KC15
KC15
KC20

Table 3-13 (cont)
LLSS Functions
660602

Long Left Shift, Signed (Two Positions)

Process

Function

Shift 2

(MQO, ARI, EAE-R, CONT, CMA56)
EAE-R(l) ASCOV(O) = R-PULSE
R-PULSE = 000000 .... SC
R-PULSE ASC FULL = SCOV(l)
EAE-R(l) ASCOV2(0)AEAE RUN(l) AEIR09(l) ALRS = IN SHLl
MQO(l) ASHLl AARI(l) = MQn .... ARn-l
SHLl = ADROO .... 0 BUS L
EAE-R(l) = 0 BUS L .... TEMP2 (lost)
EAE-R(l) = TEMPl .... END BITl7
SHLl = END BITl7 .... AR17
CM STROBE ACONT(l) = GO TO 56
(ACO, MQI, EAE-P ,CONT ,CMA57)
SCOV(l) = IN SHLl
ACO(l)ANOSHAMQI(l) = AC .... MQ
CM STROBEACONT(l) = GO TO 57

(ARO ,ACI, EAE-R,CONT ,CMA40)
EAE-R(l)ASCOV(l) = SCOV2(l)
SCOV(l) = R-PULSE
SCOV2(l) = IN SHLl
ARO(l )ANOSHAACI = AR .... AC
EAE-R(l)AEAE RUN(l) = APDR 10
CMA40MDDR 10 = CMA50
CM STROBEACONT(l) = GO TO 50

(MQO ,ARI,EAE-P ,CONT ,CMA42)
SCOV(l) = IN SHLl
MQO(l )ANOSHAARI(l) = MQ .... AR
CM STROBEACONT(l) == GO TO 42

(ACO ,MQI,EAE-R,CONT ,CMA55)
EAE-R(l )ASCOV2(1) = EAE RUN(O)
SCOV2(1) = IN SHLl
ACO(l )ANOSHAMQI(l) = AC .... MQ
CM STROBEACONT(l) = GO TO 55

(ARO ,ACI,EAE-P ,CONT ,CMA53)
SCOV(l) = IN SHLl
ARO(l)ANOSHAACI(l) = AR .... AC
CM STROBEACONT(l) = GO TO 53

(MQO ,ARI,EAE-R,CONT ,CMA56)
SCOV2(l) = IN SH L1
MQO(l)ANOSHAARI{l) = MQ .... AR
CM STROBEACONT(l) = GO TO 56

3-15

Drawing No.
KC18
KE2
KE2
KE2
KE4
KC20
KC15
KE3
KC15
KC20
KC16
KC18
KE4
KC20-21
KC16
KC18
KE2
KE2
KE4
KC20-21
KE3
KC17
KC16
KC18
KE4
KC20-21
KC16
KC18
KE3
KE4
KC20-21
KC16
KC18.
KE4
KC20-21
KC16
KC18
KE4
KC20-21
KC16

Table 3-13 (cant)
LLSS Functions
660602

Long Left Shift, Signed (Two Positions)

Process

Function

(ACO,MQI,EAE-P ,CONT,CMA57)

KC18

SCOV(l) = IN SHLl
ACO(l)ANOSHAMQI(l) = AC - MQ
CM STROBEACONT(l) = GO TO 57
57

(ARO,ACI,EAE-R,CONT ,CMA40)

(EAE,DONE,CMA 1~)

KE4
KC20-21
KE3
KC16
KC18

. "l')

e. tL-D,

CU«B)+670 nsAEAf(1) N)O/lo~f1-) = INPUT 10 RESTART
INPUT 10 RESTART = 10 RESTART
10 RESTART = GO TO 10

KE4
KC20-21
KC16
KC18

SCOV2(1) = IN SHL 1
ARO(l)ANOSHMCI(l) = AR - AC
EAE RUN(0)ASCOV2(l) = ADDR 10
CM STROBEACONT(l) = GO TO 40
40

Drawing No.

(PCO,SM,CMA21)

BG N next fetch

KD3(3)
KD3(3)
KC16
KC18

Table 3-14
ALSS Functions
660703

Accumulator Left Shift Signed (Three Positions)

Process

Function

Same as LRSS except:
SA09(l }ASA 1O(1)ASA 11 (1) = ALS

Drawing No.

KE4

Same as LRSS except:
SU2(l) = 1111 00 - SC

Same as LRSS

Same as LRSS except:

KE2

R-PULSE = 111101 - SC

KE2

Same as LRSS

(ACO,MQI, EAE-R,CONT ,CMA55)
EAE-R(1 )ASCOV(O) = R-PULSE
R-PULSE = 111110 - SC
EAE-R(1)ASCOV2(0)AEAE RUN (l)AEIR09(1 )ALRS = IN SH U
IN SHU = SHLl
ACO(l)ASHLlAMQI(1) = ACn - MQn-l
SHLl = ADROO - 0 BUS L

3-16

KC18
KE2
KE2
KE4
KC13
KC20-21
KC15

Table 3-14 (cont)
ALSS Functions
660703

Accumulator Left Shift, Signed (Three Positions)

Process

Function

42(cont)

EAE-R(1) = 0 BUS L-TEMP2
EAE-R(1}= TEMP1-END BITl7
SHLl = END BIT17 - MQ17
CM STROBE"CONT(l) = GO TO 55
(ARO,ACI,EAE-P ,CONT ,CMA53)
EAE-P(1)"EAE RUN(l) = FIRST(O)
ARO(l)"NOSHMCI(1) = AR - AC
EIRll (1) = IN SHU
SHIFT = ADRL - 0 BUS L
EAE-P(I} = 0 BUS L - TEMPI
EAE-P(1) = TEMP2 - END BITOO (lost)
EAE-P(1} = TEMP3 - END BIT17 (not used)
CM STROBE"CONT(1) = GO TO 53

Shift 2

j
56

(MQO ,ARI, EAE-R,CONT ,CMA56)
EAE-R(1 )"SCOV(O) = R-PULSE
R-PULSE = 111111 - SC = SC FULL
EAE-R(1 )"SCOV2(0)"EAE RUN(1)"EIR09(1 )"LRS = IN SH Ll
IN SHLl = SHLl
MQO(1)"SHLl"ARI(1) = MQn - ARn-1
SHL1 = ADROO - 0 BUS L
EAE-R(1) = 0 BUS L - TEMP2
EAE-R(1) = TEMP1 - END BIT17
SHLl = END BIT17 - AR17
CM STROBE"CONT(1) = GO TO 56
(ACO ,MQI,EAE-P ,CONT ,CMA5?)
EIR11(1) = IN SHLl
ACO(1)"NOSH"MQI(1) = AC - MQ
SHIFT = ADRL - 0 BUS L
EAE-P(1) = 0 BUS L - TEMP1
EAE-P(1) = TEMP2 - END BITOO {lost}
EAE-P(1) = TEMP3 - END BIT17 (not used)
CM STROBE"CONT(1} = GO TO 57

57
q\

Shift 3

(ARO ,ACI, EAE-R,CONT ,CMA40)
EAE-R(1 )"SCOV (0) = R-PULSE
R-PULSE = 000000 - SC
R-PULSE"SC FULL = SCOV(1)
EAE-R(1)"SCOV2(O)"EAE RUN(1)"EIR09(1)"LRS = IN SHL1
IN SHL1 = SHLl
ARO(1)"SHL1"ACI(1) = ARn - ACn-l
SHLI = ADROO - 0 BUS L
EAE-R(1) = 0 BUS L - TEMP2 (lost)
EAE-R(1) = TEMP1 - END BIT17

3-17

Drawing No.
KE3
KC15
KC20
KC16
KC18
KE3
KC20-21
KE4
KC15
KE3
KC15
KC15
KC16
KE18
KE2
KE2
KE4
KC13
KC20-21
KC15
KE3
KC15
KC20
KC16
KC18
KE4
KC20-21
KC15
KE3
KC15
KC15
KC16
KC18
KE2
KE2
KE2
KE4
KC13
KC20-21
KC15
KE3
KC15

Table 3-14 (cont)
ALSS Functions
660703

Accumulator Left Shift, Signed (Three Positions)

Process

Function

57(cont)

SHL1 = END Bln7 - AC17
EAE-R(1)/\EAE RUN(l) !:: ADDR 10
CMA40/\ADDR 10 = CMA50
CM STROBE/\CONT(l) = GO TO 50
(MQO ,ARI, EAE-P ,CONT ,CMA42)
SCOV(1) = IN SHL1
MQO(l)/\NOSHMRI(l) = MQ - AR
CM STROBE/\CONT(l) = GO TO 42

(ACO ,MQI ,EAE-R,CONT ,CMA55)
EAE-R(l )/\SCOV(l) = SCOV2(1)
SCOV(l) = R-PULSE
SCOV2(l) = IN SH L1
ACO(l)/\NOSH/\MQI(l) = AC - MQ
CM STROBE/\CONT(l) = GO TO 55

(ARO,ACI,EAE-P ,CONT ,CMA53)
SCOV(l) = IN SHLl
ARO(l)/\NOSH/\ACI(l) = AR .... AC
CM STROBE/\CONT(l) = GO TO 53

(MQO ,ARI, EAE-R,CONT ,CMA56)
EAE-R(l)/\SCOV2(1) = EAE RUN(O)
SCOV2(l) = IN SH Ll
MQO(l)/\NOSHMRI(l) = MQ .... AR
CM STROBE/\CONT(1) = GO TO 56

(ACO ,M91,EAE-P ,CONT ,CMA57)
SCOV(l) = IN SHLl
ACO(l)/\NOSH/\MQI(l) = AC .... MQ
CM STROBE/\CONT(l) = GO TO 57

(ARO ,ACI, EAE-R,CONT ,CMA40)
SCOV2(1) = IN SHLl
ARO(l)/\NOSH/\ACI(l) = AR - AC
EAE RUN(0)/\SCOV2(l) = AD DR 10
CM STROBE/\CONT(l) = GO TO 40

(EAE,DONE,CMA10)

~K~8)-k67D nsAEAffl)~) = INPUT 10 RESTART

INPUT 10 RESTART = 10 RESTART
10 RESTART = GO TO 10
10

(PCO ,SM,CMA21)

Drawing No.
KC20
KE3
KC17
KC16
KC18
KE4
KC20-21
KC16
KC18
KE2
KE2
KE4
KC20-21
KC16
KC18
KE4
KC20-21
KC16
KC18
KE3
KE4
KC20-21
KC16
KC18
KE4
KC20-21
KC16
KC18
KE4
KC20-21
KE3
KC16
KC18
KD3(3)
KD3(3)
KC16
KC18

BGN next fetch

3-18

LINK

Ma.e -17

ARee -17

TEMP 3

75
I

I
I
I
I

541

5el

421

551

531

AC •• -17

f
AC •• -, 7

I Moel -17 1 L 1

lAC.' -, 71MO•• I

1Moe2 - 1 1 1
I7

LOST

I"C.,2 -, 71Moe. -." 1
I,.C.2- 17 1Moee-e' 1 IMoe2-'7I L IL

1Ace2 -,71 MO.,.,-It 1

IAce2 -,71 M08e -e,·1

1M082 -'7 1L 1 L

I,.ce2 - 1Mo.,e-e, 1 IAce2 -,71 ..08e -e, 1 I..082 -'7 1 1
17

l ..oe2 -,71

1 1 1,.ce2 -,71 .. 0 .,e-e, 1 1..082 - 1 1 1
I
]
t t
L

[AC.,2-,71 M08e-e, I

f
IMO.2 -t7 1 1 I IMoe2 -171
L

57 ...I_L_...

I I

I ,.C.2- 17 1 Moee-el I

1 I I ~ce2 -,71 ..088 -e, 1
L

f f

IAC.,2 -17 1Moee-.II

4. DONE

Figure 3-3

LLS, LLSS Register Manipulation (Two Positions)

3-19

ACIZIIZI - 17

MOIZIIZI - 17

AC01Z1 - 17

MOIZIIZI-17

MOlZl0 - 17

LINK

54 I

~
ACIZIIZI - I 7

51Z1

f
LI_--l

MOIZIIZI-17

IACIZII- 17

M000 - I 7

f
L---~TEMP 'J-------------------~~~~~~

531

MOIZIIII - 17

MaN -17

MQIlIII- 17

1 ACIII2 - I 7

'-___3
1_---'

L.i:J

421

1 AC.3 - 17 1 L

56 1

571

1010,,-17

MOG. - 17

MQeIll-17

I AC.3- 17 1 L 1 L 1 L 1

I AC.3 - 17 1 L I L

1 AC.3 - 17

I
1010" -17,

1010111. - I 7

f
53 1

I AC.3 - 17 1 L 1 L 1 L

551

MOIlIII- 17

57 ....

I I I

MO"

-17

I I

101011. -17

I I

AC.3- 17 1 L

[

1L I L I L 1

1 AC.3 - 171 L

1010. . -17

1 L

f
1 L

f
1 AC.3- 17

101011. -17

AC.3 - t 71

I I
L

I
1

4' DONE

Figure 3-4 ALS, ALSS Register Manipulation {Three Positions}

3-20

3.6

NORMALIZE INSTRUCTIONS
The NORM and NORMS instructions, Table 3-15, are commonly used within a subroutine to

convert an integer into a fraction and exponent for use in floating-point arithmetic. The algorithm for
normalize is to shift the contents of the AC and MQ left until ACOO differs with ACOI. For signed,
normalized positive numbers this results in ACOO(O) and ACOI (1). For signed, normalized negative
numbers the result is ACOO(I) and ACOI (0). For signed normalized numbers the sign (ACOO) is first
duplicated in the LINK.

For unsigned numbers the LINK is usually initialized to O. In both cases the

content of MQOO enters AC 17, the content sh ifted out of ACOO is lost, and the content of the LIN K
enters MQ17, on each shift. When shifting halts, the contents of the SC reflect the number of shifts
executed to reach the normalized condition. The SC contents are available through the use of the EAE
OSC or EAE LACS instruction.

Table 3-15
EAE NORM Instruction Format
Op Code
648
0

NORM

Not
Used
4

Number of
Shifts

48
8

NORM

NORMS

For normalized numbers, the binary point is assumed to be between ACOO and AC01, the
mantissa of the fraction extends from ACOI to MQ17, the sign is in ACOO, and the value of the exponent
is in the SC. The number in the SC after normalize is actually the sum of the pre-established characteristic and the exponent (n) in 2s complement form. The characteristic is a number equivalent to the
total number of bit positions in the AC and MQ, 36 10 or 448 , The NORM(S) instruction contains this
number in bits 12 through 17 and loads it into the SC in 2s complement to establish the exponent in excess 44 code. This means that the exponential range of the fraction when normalized is 2 0 to 2 35 , or
-448 + n.
For example, if the integer +3 is stored in the MQ (MQ 16, MQ17 are Is) and it is desired to
convert th is to a fraction and exponent, the following program sequence is required.
NORM(S)
DAC
LACQ
DAC
LACS
TAD (44
DAC

/NORMALIZE CONTENTS OF AC, MQ
/DEPOSIT AC IN MEMORY
/MOVE MQ TO AC
/DEPOSIT MQ IN MEMORY
/MOVE SC TO AC
/SUBTRACT CHARACTERISTIC FROM STEP COUNT
/DEPOSIT RESULT (EXPONENT) IN MEMORY

3-21

In the process of normalizing, a total of 33 shifts is required to shift MQ16(l) into AC01.
This leaves the SC with a step count of:
011100
100001
111101

initialized step count
plus 33 steps
final step count

Since the step count is in 2s complement, the TAD (448 instruction (2s complement add) in
effect subtracts the characteristic from the final step count to arrive at the exponent:
111101
100100
100001

final step count
TAD characteristic
exponent

The NORM(S) logic functions are very similar to the LLS(S) functions. Table 3-13 lists the
functions for a two-position LLSS instruction. The functions for a NORMS instruction requiring only
two shifts to normalize can be correlated with those of Table 3-13.
In the NORMS case, any positive integer whose most-significant 1 bit is located in AC03
requires two shifts to normalize. Likewise, any negative integer whose most-significant 0 bit is in AC03
requires two shifts to normalize. Substituting the positive-integer NORMS case in the listings of
Table 3-13, the following NORMS functions become apparent.
75

SA09(1 )I\SA 1O(O)I\SA 11 (0) = NORM

KE4

SU2(l) = 011011 -

KE2

Same

R-PULSE = 011100 -

Same, first shift

Same, first shift, plus:

KE2

R-PULSE = 011101 - SC
EAE STROBE DLYDI\EAE-R(1)I\NORMI\O BUSOOI\O BUSOl = SCOV(l)
55

Same, second sh i ft

Same, second shift, plus:

KE2

R-PULSE =011110 - SC
KE2
EAE STROBE DLYDI\EAE-R(l)I\NORMI\OBUSOOI\O BUSOl = SCOV(l) KE2
56,57,50,42,55,53,56,57,40,10

Same

Although the execution of a NORM(S) instruction cannot be interrupted by a program interrupt
(PI) or an automatic priority interrupt (API) request, the central processor can grant such a request before the executed NORM(S) results can be extracted from the EAE registers and processed. Therefore,
if interrupt-accessed subroutines are to make use of the EAE, the following instruction sequences are
suggested to preserve the register contents during the interrupt and to restore them to the EAE upon completion of the interrupt service routine.

3-22

/SAVE EAE REGISTERS DURING INTERRUPT
JMS SUBENTR

SUBENTR,

/SAVE AC CONTENTS
/MOVE MQ TO AC
/SAVE MQ CONTENTS
/MOVE SC TO AC
/SAVE SC CONTENTS

DAC ACSAVE
LACQ
DAC MQSAVE
LACS
DAC SCSAVE

LAC SCSAVE
XOR (77
TAD (640402
AND (640477
DAC.+1
HLT*
LAC MQSAVE
LMQ
LAC ACSAVE
DBR
JMP I SUBENTR

/COMPLEMENT STEP COUNT
/DEVELOP PSEUDO NORM
/DELETE POSSIBLE STEP COUNT OVERFLOW
/PLACE NORM IN SEQUENCE
/STEP COUNT TO SC

/
/LOAD THE MQ
/LOAD THE AC
/RESTORE PC,LINK,ETC

Restoration of the step count to the SC requires that the 2s complemented quantity, taken
from the SC at the time of interrupt, be complemented, then combined with the pseudo NORM instruction. The step count following TAD,AND is one lless (ls complement) than the actual value produced
by the previous normalization (2s complement).

Execution of the pseudo NORM instruction, then, 2s

complements this step count into the SC, and in shifting the AC and MQ left one bit position adds the
necessary 1 to the SC to produce the correctly restored step count (the 6404XX present in the AC from
TAD, AND shifts to become 501XXX). From the previous two-shift NORM(S} sample:

64048
64048
64048
NORM

011110
111111
100001
000010
100011
111111
100011

TAD (640402

011100
011101
011110

1s complement _ SC
2s complement - SC
shift once, step SC

LAC ACSAVE
XOR (77

AND (640477
DEPOSIT IN HL T* == 640443 == NORM

The DBR instruction preceding the JMP I subroutine termination primes the computer for restoration of the interrupted program. This restoration occurs during JMP I. During this time, the PC and

* Good programming practices dictate that instructions to be developed at "run" time be represented by
HLT instructions in the source program. If the development does not occur, the HLT will facilitate debugging the pro9ram.

3-23

LINK are restored to the contents existing at the time of interrupt. The memory protect and extended
memory options, if in the system, are restored to their on or off status. Refer to the PDP-9 Maintenance
Manual and option manuals for details.

3.7

MULTIPLY INSTRUCTIONS
The MUL{S} instruction, Table 3-16, multiplies the contents of the AC {multiplier} by the

contents of the next sequential core memory location (multiplicand) to form a product in the AC and
MQ. Bits 12 through 17 in the instruction are usually programmed for a step count of 228 (18 1O ), representing the multiplication of one 18-bit quantity (sign bit and 17 magnitude bits for MULS) by another
to produce a 36-bit product. When such prec ision is not required, the microprogrammed step count can
be decreased by subtracting the appropriate number "n" from the instruction code. The product is always scaled 18-n from MQ17. If "n" is programmed in the instruction, the 18-n lower order bits in the
long register are meaningless.

Table 3-16
EAE MUL Instruction Format

Op Code

MUL

648

Commands Product
Precision
11

MUL

MULS

For a MUL instruction the LINK must previously have been initialized to 0 and remains O.
During the preparatory phase the multiplier is transferred from the AC to the MQ, the AC is cleared,
and the SC is set to the 2s complement of the step count in bits 12 through 17 of the instruction. A core
memory cycle takes place to read the multiplicand into the MB. The arithmetic phase, executed as
multiplication of one unsigned quantity by another (binary point of no consequence), halts when the SC
counts up to O.
For a MULS instruction a previous LAC/GSM/DAC CAND sequence stores the absolute value
of the multiplicand in memory and places the original sign of the multiplicand in the LINK. During the
preparatory phase of MULS, a core memory cycle reads the absolute value multiplicand into the MB,
transfers the LINK content to a TEMPorary storage flip-flop in the EAE, and resets the LINK. The multiplier is transferred to the MQ and is ls complemented if negative, the AC is cleared to 0, and the SC
is initialized to the 2s complement of the step count in bits 12 through 17 of the instruction. The arithmetic phase, executed as multiplication of one signed quantity by another {sign bit plus 17 magnitude

3-24

bits, binary point of no consequence), halts when the SC counts up to O. Bits ACOO and AC01 each
receive the sign of the product; the remaining AC and MO bits represent the magnitude.
From the above description of MULS, it can be seen that the arithmetic phase always starts
with positive, like-signed quantities in the MQ (multiplier) and the MB (multiplicand). The TEMPorary
storage flip-flop which receives the original sign of the multiplicand (TEMP3, drawing KE3) acts upon
the MO SIGN and EAE SIGN flip-flops which perform certain complementary functions during the
arithmetic phase to arrive at the correctly signed product.
Thus, the complementary functions govern the four signed multiply situations as follows.
+x +=+

(behaves as simple unsigned multiply, no complementing
of the final product)

+x-=-

(negative multiplier is first complemented in preparatory
phase, final product complemented after arithmetic phase)

-x+=-

(EAE GSM sets LINK, complements multiplicand; MULS
complements final product after arithmetic phase)

-x-=+

(EAE GSM sets LINK, complements multiplicand; MULS
complements multiplier in preparatory phase; no complementing of final product)

The algorithm for multiplication using the EAE is sample, add, and shift right. Each bit of
the"multiplier is sampled, starting with the least significant bit. If the sampled bit is a 1, the multiplicand is added to the partial product. The partial product and the multiplier are then shifted right
one position for the next multiplier bit sampling. If the sampled bit is a 0, zeros are added to the
partial product. With each shift the content of the least significant bit is lost. Multiplication ends
when the SC, up-counted with each shift, reaches O.
A sample program for signed multiplication of two positive numbers, 28 x 58 follows. The
logic functions that perform the MULS operations are tabulated in Table 3-17. Table 3-18 is a listing
of the arithmetic operations by process word functions.* The sample program and the microprogrammed
bits 12 through 17 in the MULS instruction reflect an initial step count of 048 , resulting in a product
precision of eight bits. The MULS instruction is used here to explain EAE SlGN operations; actually,
the sample program can be modified for MUL by eliminating the GSM sequence if dealing with unsigned
numbers. Tables 3-19,3-20, and 3-21 list the ramifications of Table 3-17 for different sign situations.
/MUL TIPLY 28 x 58
ST,

0200
0201

200100
100500

LAC CAND
JMS MPY

0202
0203

200101

LAC PLIER

/LOAD MULTIPLICAND INTO AC
/STORE MAIN PROGRAM ADDRESS IN 0500
/ AND JUMP TO MPY SUBROUTINE
/LOAD MULTIPLIER INTO AC
/MAIN PROGRAM RE-ENTRY

*Table 3-18 utilizes 4-bit binary numbers for simplicity. The actual result obtained in multiplying
28 x 58 is 0000008 in the AC and 500000 8 in the MO. Fourteen more shifts to the right would align
tl1e answer as 128 (MOOOOO128)'

3-25

MPY

CAllo

PJ..l~'

0500
0501

000202
664000

PC
GSM

0502
0503
0504

040505
420500
657122

DAC .+3
XCHl'MPY
MULS

0505
0506
0507

000002
440500
620500

ISZ
JMP~_fAP-(

0100
0101

000002
000005

MULTIPLICAND
MULTIPLIER

/MAIN PROGRAM ADDRESS
/STORE CAND SIGN IN LINK AND
/ ABSOLUTE VALUE IN AC
/DEPOSIT CAND IN 0505
/LOAD MULTIPLIER INTO AC
/FETCH CAND AND MULTIPLY

Jtl\Py

/INCREMENT MAIN PROGRAM ADDRESS
/JUMP TO MAIN PROGRAM

Table 3-17
MULS Functions

0010
0101

657104

Multiply, Signed (Four Steps)

28 x 58

Process

Function

Drawing No.

(ACO ,ARI,EAE, LI,CONT ,CMA43)
ACO(l )ANOSHAARI{l) = AC - AR
SA09(O)ASA 1O(O)ASA 11 (1) = MUL
EAE(l)AARI(l) = SUl (1)
SU1(1) = 0 - SCOV,SCOV2,FIRST,EAE RUN,EAE SIGN,MQ SIGN
SUl (l)ASETUP = SC CLR
SC CLR = 0 - SC
SUl (l)AMB07(1) = EAE OR ARO
LI(l) = ADRL - LAR(O)
LI(l) = ADRL - TEMP3(O)
EAE(l) = 0 - EN CMPL
TEMP3(O) = condition MQ SIGN
MUL = condition MQ SIGN
CM STROBEACONT(1) = GO TO 43

KC19
KC20-21
KE3
KE2
KC15
KC16
KC18

(ACO,MQI,EAE,CONT ,CMA54)
ACO(l)ANOSHAMQI(1) = AC - MQ
CM STROBEACONT{l) = GO TO 54

KC20-21
KE4
KE3
KE2-3
KE2
KE2
KE3
KC15
KE3
KE3
KE3
KC16
KC18

(ACI, EAE , CON T ,CMA41 )
CM STROBEAEAE OR ARO = ARO(1)
ARO(l)ANOSHAACI(l) = AR- AC
EAE(1)AACI(l)ASETUP = SU2(1)
SU2{l) = MB12-17 - SC = 111011
LI(O) = LAR(O) - LINK(O)
CM STROBEACONT(1) = GO TO 41

KC18

(ACI, EAE -R, C 0 NT , CMA40)

KC20-21
KC16
KC18

ACI(l) = 0 - AC
EAE-R(1)ASCOV(O) = R-PULSE
R-PULSE = 111100 - SC
EAE-R(1) = 0 BUS L = LINK - TEMP2(0)
EAE(0)ATEMP3(O) = MQ SIGN(1)

3-26

KC20
KE2
KE2
KE3
KE3

Table 3-17 (cont)
MUlS Functions
657104

Multiply, Signed (Four Steps)

Process

Function

54(cont)

I Drawing No.

MQ SIGN(1) = condition EAE SIGN
EAE-R(1)I\SCOV2(0) = ADDR 10
EAE-R(1)I\EIR09(0)ASCOV2(0)I\EAE RUN(O) = ODD ADDR
CM STROBEACONT(1)I\CMA401\ADDR 101\0DD ADDR = GO TO 51

KC18

(PCO, SM, MBI, CMA52)
PCO(1) /\NOS HI\MBI(1) = PC - MB (CAND ADDRESS)
SM(1)I\ClK = FETCH CAND
SM(1)I\CLK = CM STROBE
CM STROBE = GO TO 52

Sample

42
II'

ADD,

Sh ift 1

KC20-21
MC2
KC16
KC17
KC18

(MBO ,+1, PC I, L1,CMA50)
+1 (1) = CIl7
MBO(1)"NOSHI\CI17"PCI(1) = MB (CAND ADDRESS) +1 - PC
+1 (1) = A BUS LINK - ADRL
LI(1)= ADRL -LAR(O)
LI(l) = ADRL - TEMP3(0)
L1(1)I\CONT = EAE CLR RQ
EAE CLR RQ = IN CLR, CLR
INC LR = C LR I = 0 - PC I, MBO
C LR = 0 - +1, 1 - SAO
IN CLR = 1 - MBI
SAO(1) = A BUS LINK - ADRL (Since +1 is cleared by CLR,
SAO(1) inhibits erroneous setting
of lAR)
SAO(1)"NOSH"MBI(1) = SA(CAND) - MB
MEM STROBE = GO TO 50

KE3
KE3
KE3
KC16

(MQO ,ARI, EAE-P ,CONT ,CMA42)
EAE-P(l )I\EAE RUN(O) = FIRST(1)
EAE-P(l )I\SCOV2(0) = EAE RUN(l)
FIRST(1)I\EAE RUN(1)I\MQ SIGN(l )=CMPL EAE SIGN=EAE SIGN(l)
FIRST(1)"MUL = MQ SIGN (1)
MQ SIGN(1) = condition EAE SIGN
MQO(1 )1.\ NOS HI\AR 1(1) = MQ - AR
EAE-P(1tAMUL"SCOV(O)I\O BUS17(1) = EAE OR MBO
EAE-P(1) = 0 BUS L = LINK = ADRL - TEMP1 (not used)
L1(0) = LAR(O) _ LINK(O)
CM STROBEI\CONT(1) = GO TO 42
(ACO,MQI, EAE-R,CONT ,CMA55)
EAE-R(l)"SCOV(O) = R-PULSE
R-PU LSE = 1111 01 - SC
CM STROBE"EAE OR MBO = MBO(l)
EAE-R(1)I\SCOV2(0)"EAE RUN(l)"EIRl O(O)I\EIRll (1) = IN SHR1
IN SHR1 = SHR1
(ACO(l)"SHR1I\MQI(1) = ACn - MQn+'i1 /V' (¥1i3 -_7'iIJ,n
~BO(l)I\SHR1J\MQI(l) = MBn - MQn+Jj f'lvi
r-....,
3-27

KC14
KC20-21
KC15
KC15
KE3
KC16
KC19
KC19
KC19
KC15
KC20-21
KC16
KC18
KE3
KE3
KE3
KE3
KC20-21
KE3
KE3
KC15
KC16
KC18
KE2
KE2
KC19
KE4
KC13
KC20-21
KC20-21

Table 3-17 (cont)
MULS Functions
657104

Multiply, Signed (Four Steps)

Process

Function

42 (cont)

Shift 1,
Sample

1
53

Shift 2,
Add Zeros

Shift 2,
Sample

~eM@ 8j
EAE-R(l) = ADRL - END BITOO
SHR1 = END BITOO - MQOO
SHRl = ADR17 - 0 BUS L
EAE-R(l) = 0 BUS L - TEMP2
EAE-R(l) = TEMP1 = LINK - END BITl7 (lost)
CM STROBEACONT(l) = GO TO 55

(ARO ,ACI, EAE-P ,CONT ,CMA53)
EAE-P(1)AEAE RUN (1) = FIRST(O)
EAE-P(l)AFIRST(O)ASCOV2(O)AEAE RUN (l)AEIR 1O(O)AEIR 11 (1)
= IN SHR1
IN SHR1 = SHR1
ARO(l)ASHR 1AACI(1) = ARn - ACn+1
EAE-P(l)AMULASCOV(O)AO BUS17(O) = EAE OR MBO
SHR1 = ADR17 - 0 BUS L
EAE-P(l) = 0 BUS L - TEMP1 (lost)
EAE-P(l) = TEMP2 - END BITOO
SHR1 = END BITOO - ACOO
CM STROBEACONT(l) = GO TO 53
(MQO ,ARI,EAE-R,CONT ,CMA56)
EAE-R(1)ASCOV(O) = R-PULSE
R-PULSE = 111110 - SC
EAE-R(l)ASCOV2(O)AEAE RUN(l)AEIR10(O)AEIR11 (1) = IN SHR1
IN SHR1 = SHR1
MQO(l)ASHR1AARI(l) = MQn - ARn+1
EAE-R(1) = ADRL - END BITOO
SHR1 = END BITOO - AROO
SHR1 = ADR17 - 0 BUS L
EAE-R(l) = 0 BUS L - TEMP2
CM STROBEACONT(l) ~ GO TO 56
(ACO ,MQI,EAE-P ,CONT ,CMA57)

KC1B
KC20
KC15
KE3
KC15
KC16
KC1B
KE3
KE4
KC13
KC20-21
KE3
KC15
KE3
KC15
KC20
KC16
KC1B
KE2
KE2
KE4
KC13
KC20-21
KC15
KC20
KC15
KE3
KC16
KC1B

EAE-P(l )AFIRST(O)ASCOV2(O)AEAE RUN(l )AEIR 1O(O)AEIR 11 (1)

= IN SHR1
IN SHR1 = SHR1
ACO(1)ASHR1AMQI(l) = ACn - MQn+1
EAE-P(1)AMULASCOV(O)AO BUS 17(1) = EAE OR MBO
SHR1 = ADR17 - 0 BUS L
EAE-P(l) 0 BUS L - TEMP1 (lost)
EAE-P(l) = TEMP2 - END BITOO
SHR1 = END BITOO - MQOO
CM STROBEACONT(l) = GO TO 57
0=

Drawing No.

3-2B

KE4
KC13
KC2Q-21
KE3
KC15
KE3
KC15
KC20
KC16

Table 3-17 (cont)
MUlS Functions
657104

Multiply, Signed (Four Steps)

Process

Function

(ARO,ACI,EAE-R,CONT ,CMA40)

Add,
Shift 3

,.
50

Shift 3,
Sample

Shift 4,
Add Zeros

EAE-R(l)ASCOV(O) = R-PUlSE
R-PUlSE = 111111 ..... SC = SC FUll
EAE-R(1)ASCOV2(0)AEAE RUN(l)AEIR 10(0)AEIR11 (1) = SHR1
IN SHR1 = SHR1
CM STROBEAEAE OR MBO = MBO(l}
~RO(1)ASHR1AACI(1) = ARn ..... ACn-i-~
MBO(1)ASHR1AACI(1) = MBn ..... ACn+1
EAE-R(l) = ADRl ..... END BITOO
~
SHR1 = END BITOO ..... ACOO
SHR1 = ADR17 ..... 0 BUS l
EAE-R(l) = 0 BUS l ..... TEMP2
EAE-R(l) = TEMP1 ..... END BIT17 (lost)
EAE-R(1)ASCOV2(0) = ADDR10
CM STROBEACONT(1)ACMA40AADDR 10 = GO TO 50

(MQO ,ARI, EAE-P ,CONT ,CMA42)

Drawing No.
KC18
KE2
KE2
KE4
KC13
KC19
KC20-21
KC20-21
KC15
KC20
KC15
KE3
KC15
KE3
KC16
KC18

EAE-P(1)AFIRST(0)ASCOV2(0)AEAE RUN(1)AEIR 1O(O)AEIR 11 (1)

= IN SHRl
IN SHRI = SHRl

MQO(1)ASHR1AARI(1) = MQn ..... ARn+l
EAE-P(1)AMUlASCOV(O)AO BUS17(0) = EAE OR MBO
SHRl = ADR17 ..... 0 BUS l
EAE-P(1) = 0 BUS l ..... TEMPl (lost)
EAE-P(1) = TEMP2 ..... END BITOO
SHRl = END BITOO ..... AROO
CM STROBEACONT(1) = GO TO 42
(ACO ,MQI,EAE-R,CONT ,CMA55)
EAE-R(1)ASCOV(O) = R-PUlSE
R-PUlSE = 000000 ..... SC
EAE-R(1)ASC FUll = SCOVO)
EAE-R(1)ASCOV2(0)AEAE RUN(1)AEIR10(0)AEIRll(1) = IN SHRl
IN SHRl = SHRl
ACO(1)ASHR1AMQI(l) = ACn ..... MQn+l
EAE-R(l) = ADRl ..... END BITOO
SHRl = END BITOO ..... MQOO
SHRl = ADR17 ..... 0 BUS l
EAE-R(1) = 0 BUS l ..... TEMP2
EAE-R(l) = TEMPl ..... END BIT17 (lost)
CM STROBEACONT(1) = GO TO 55

3-29

KE4
KC13
KC20-21
KE3
KC15
KE3
KC15
KC20
KC16
KC18
KE2
KE2
KE2
KE4
KC13
KC20-21
KC15
KC20
KC15
KC15
KC15
KC16

Table 3-17 (cont)
MULS Functions
657104

Multiply, Signed (Four Steps)

Process

Function

Shift 4
No Sample

(ARO ,ACI, EAE-P ,CONT ,CMA53)
EAE-P(1 )AFIRST(0)ASCOV2(0)AEAE RUN (1 )AEIR 1O(O)AEIR 11 (1)
= IN SHR1
IN SHR1 = SHR1
ARO(l}ASHR1AACI(1) = ARn - ACn+1
EAE-P(1)AMULASCOV(l) = EAE OR MBO
SHR1 = ADR17 - 0 BUS L
EAE-P(1) = 0 BUS L - TEMP1 (lost)
EAE-P(1) = TEMP2 - END BITOO
SHR1 = END BITOO - ACOO
CM STROBEACONT(1) = GO TO 53

Drawing No.
KC18
KE4
KC13
KC20-21
KE3
KC15
KE3
KC15
KC20
KC16

(MOO ,ARI, EAE-R,CONT ,CMA56)
EAE-R(l}ASCOV(l) = R-PULSE
EAE-R(1)ASCOV(1) = SCOV2(l)
SCOV2(1) = IN SHR1
MOO(l}ANOSHAARI(l) = MO - AR
CM STROBEACONT(l) = GO TO 56

(ACO ,MOl, EAE-P ,CONT ,CMA57)
SCOV2(l) = IN SHR1
EAE-P(1)AACO(l)AMQI(1)AEIR09(0)ASCOV2(1) = EN CMPL(l)
EN CMPL(1)AMULAMQ SIGN(1)=CMPL EAE SIGN = EAE SIGN(O)
EAE SIGN(O) = CMPL
ACO(l )ANOSHAMOI(1)ACMPL = AC - MQ
CM STROBEACONT(l) = GO TO 57

(ARO ,ACI, EAE-R,CONT ,CMA40)
SCOV2(1) = IN SHR 1 tIW
EAE-R(l)ASCOV2(l) =.. RUN(O)
EAE-R(1)t\SCOV2(1)ARUN (0) - AD DR 10
EN CMPLAEAE SIGN (0) = CMPL
ARO(l)ANOSHAACI(1)ACMPL= AR - AC
CM STROBEACONT(1)AADDR 10- GO TO 40

(EAE, DONE, CMA 10)

KE2
KE3
KE4
KC20-21
KC16
KC18
KE4
KE3
KE3
KE3
KC20-21
KC16
KC18
KE4
KE3
KE3
KE3
KC20-21
KC16
KC18

CLK(B) DL YDAEAE(l)ADONE(l) = INPUT 10 RESTART
10 RESTART = GO TO 10
10

KC18

(PCO,SM,CMA21)

KD3
KC16
KC18

BG N next fetch

3-30

Table 3-18
MULS Arithmetic
28 x 58

~sample

0101

0000
0010
CRY~0010

CAND
SHRl

PLIER

> 0101

> 0001

0101

~Iost

0010,

0001
SHRl

0010

0001

plost
0010
SHRl
~sample

~0011

r 0101--;. sample

SHRl

> 1001

0000

1001

0010
CAND
CRY~ 00l10,

SHRl
50

0001

1001
SHRl
l;'lost
sample

..-.."

>0000

•

>0100

=- 0000

0100

1010~

0000
SHR 1

,0100

1010

0000

> 0000

1010

:> 1010

0000

OOOO~

1010

,0000

SHRl

~Iost

answer
128

3-31

Table 3-19
MULS Functions
657104

Multiply, Signed (Four Steps)

Process

Function

TEMP3(O) = condition MQ SIGN
MUL = condition MQ SIGN
ACOO(l) = condition EAE SIGN
EAE(l) == 0 - EN CMPL

SU2(l)AMB06(l)AACOO(l) = EAE SIGN (1)
SU2(1)AEIR09(O)AEAE SIGN(1)AEIR11(1) = CMPL
CMPL = AR -AC

AC-MQ

EAE(O)ATEMP3(O) = MQ SIGN(l)
MQ SIGN(l) = condition EAE SIGN
0 - AC

CAND fetch

MB+l -

FIRST(1)AEAE RUN(l)f\MQ SIGN(l)AEAE SIGN (1) = EAE SIGN(O)
FIRST(1)AMUL = MQ SIGN(l)

42,55,53

same as MULS 28 x 58

EAE-P(1)ASCOV2(l)AMQI(l)AEIR09(O)AACO(l) = EN CMPL(l)
MULAEN CMPLAMQ SIGN(1)AEAE SIGN (0) = EAE SIGN(l)
EN CMPL(1)AEAE SIGN(1) = CMPL
CMPL =AC -MQ

EN CMPLAEAE SIGN (1) = CMPL
CMPL = AR -AC

Table 3-20
MULS Functions
657104

Multiply, Signed (Four Steps)

Process

Function

TEMP3(l) = no conditioning of MQ SIGN
ACOO(O) = no conditioning of EAE SIGN
EAE(1) = 0
MUL = condition MQ SIGN

EN CMPL

AR -AC

AC- MQ

o -AC

CAND fetch

MB+1 -

FIRST(1)AMUL = MQ SIGN (1)
FIRST(1)AEAE RUN(1) = no effect on EAE SIGN

3-32

Table 3-20 (cont)
MULS Functions
657104

Multiply, Signed (Four Steps)

Process

Function

42,55,53

same as MULS 28 x 58

EAE-P(l)ASCOV2(1)AMQI(l)AEIR09(0)AACO(1) = EN CMPL(l)
EN CMPL(1)AMULAMQ SIGN(1)AEAE SIGN (0) = EAE SIGN (1)
EN CMPL(l)AEAE SIGN (1) = CMPL
CMPL =AL..... MQ

EN CMPLAEAE SIGN (1) = CMPL
CMPL =AR..... AC

Table 3-21
MULS Functions
657104

Multiply, Signed (Four Steps)

Process

Function

TEMP3(1) = no conditioning of MQ SIGN
ACOO(l) = condition EAE SIGN
MUL = condition MQ SIGN
EAE(1} = 0 ..... EN CMPL

SU2(1)AMB06(1)AACOO(1) = EAE SIGN (1)
SU2(l)AEIR09(0)AEAE SIGN(l)AEIR 11 (1) = CMPL
CMPL = AR ..... AC
AC ..... MQ

o ..... AC

CAND fetch

MB+1 ..... PC

FIRST(1)AMUL = MQ SIGN(l)
FIRST(l)AEAE RUN(l) = n~ effect on EAE SIGN

42,55,53

same as MULS 28 x 58

EAE-P(l)ASCOV2(1)AMQI(l)AEIR09(0)AAC0(1) = EN CMPL(1)
EN CMPL(l)!\MULAMQ SIGN(l)AEAE SIGN (1) = EAE SIGN (0)
EN CMPL(1)AEAE SIGN(O} = CMPL
AC ..... MQ

EN CMPL(1)AEAE SIGN(O} = CMPL
AR ..... AC

3.8

-2 x-5

DIVIDE INSTRUCTIONS
Six divide instructions including integer divide and fraction divide, Table 3-22, divide the

contents of the AC and MQ (integer dividend, fraction dividend, long register dividend) by the contents

3-33

of the next sequential core memory location (divisor) to form a quotient in the MQ and remainder in the
AC. Bits 12 through 17 in the instruction are usually programmed for a step count of 23a (19 10),
representing division of a 36-bit dividend (actual or implied) by an 18-bit divisor. When such precision
is not required, the microprogrammed step count can be decreased by subtracting the appropriate number
"n" from the instruction code. The quotient is always right-justified in the MQ and the remainder rightjustified in the AC. If "-n" is programmed in the instruction, the n high-order bits in the MQ and AC
are meaningless.
Table 3-22
EAE DIV Instruction Format
DIV
38

Op Code
648
0

1 2

Commands Precision of
QUOT/Remainder

DIV

DIVS

IDIV

IOIVS

FRDIV

FRDIVS

Instructions may be programmed for division of signed or unsigned quantities. Divide overflow occurs if the quotient exceeds the capacity of the MQ (7777778 , unsigned; ±3777778' signed).
The LINK sets to indicate an overflow, divide execution ends in 5 computer cycles, and the register
contents are meaningless. The computer goes on to the next instruction.
3.8.1

DIV(S} Instruction
The DIV(S} instruction divides the contents of the AC and MQ (long register dividend) by the

contents of the next sequential core memory location to form a quotient in the MQ and remainder in
the AC.
For a DIV instruction the LINK must previously have been set to 0 and remains 0 unless divide
overflow occurS (Section 3.8.4). During the preparatory phase, the SC is set to the 2s complement of
the step count in bits 12 through 17 of the instruction. A core memory cyc Ie takes place to read the
divisor into the MB. The arithmetic phase, executed as the division of one unsigned quantity by another (binary point of no consequence), halts when the SC counts up to O.
For a DIVS instruction, a previous LAC/GSM/DAC DIVR sequence stores the absolute value
of the divisor in memory and places the original sign of the divisor in the LINK. During the preparatory

phase of DIVS, a core memory cycle reads the absolute value divisor into the MB, transfers the LINK

3-34

content to the temporary storage register TEMP3 in the EAE, and resets the LINK. The SC is set to the
2s complement of the step count in bits 12 through 17 of the instruction. The arithmetic phase, executed
as the division of one signed quantity by another (binary point of no consequence), halts when the SC
counts up to O. The dividend contains a double sign in bits ACOO and AC01. MQOO receives the sign
of the quotient, and ACOO receives the original sign of the dividend.
As with the execution of MULS, the arithmetic phase of DIVS starts with positive, like-signed
quantities in the divisor and dividend. TEMP3, MQ SIGN, and EAE SIGN flip-flops act to ls complement the MQ portion of a negative dividend during the preparatory phase and to perform other complementary functions during the arithmetic phase to arrive at the correctly signed quotient as follows.

+ ++ = +

(behaves as simple unsigned divide, final quotient
complemented after arithmetic phase)
(EAE GSM sets LINK, complements divisor; final
quotient not complemented)

- ++= -

(MQ portion of dividend complemented during preparatory phase; quotient not complemented; remainder
complemented after arithmetic phase)

- +- =+

(EAE GSM sets LINK, complements divisor; MQ portion of dividend complemented during preparatory phase,
quotient complemented after arithmetic phase).

The algorithm for divide using the EAE is sample, add or subtract, and shift left. The divisor
is first subtracted from the AC portion of the dividend, and the result is shifted left. The LINK and
TEMP3 receive the most significant bit of the result for sampling. If the result is a negative number, the
divisor is added to the quotient; if the result is a positive number, the divisor is subtracted from the quotient. The result is then sh if ted left one position for the next sampling. If in the first subtraction the
divisor is not greater than the AC portion of the dividend, divide overflow occurs, stopping divide operations (Section 3.8.4). The subtract operation takes the form of a 2s complement add.
Following is a sample program for the signed division of two positive numbers, 128 + 58. The
logic functions that perform the DIVS operations are listed in Table 3-23. Table 3-24 is a listing of the
arithmetic operations by process word functions. The sample program and the microprogrammed bits 12
through 17 in the DIVS instruction reflect an initial step count of 05 8 , resulting in a four-bit precision
of the quotient and remainder. The DIVS instruction is used here for purposes of explanation of the
EAE SIGN operations; actually, the sample program can be modified for DIV by eliminating the GSM
sequence if dealing with unsigned numbers. Tables 3-25, 3-26, and 3-27 list the ramifications of
Table 3-23 for different sign situations.
/DIVIDE 128 + 58
ST,

0500
0501

200100
100200

LAC DIVR
JMS DIV

/LOAD DIVISOR INTO AC
/STORE PROGRAM ADDRESS IN 0200 AND
/ JUMP TO DIV SUBROUTINE

0502

/MAIN PROGRAM RE-ENTRY
3-35

DIV

DIVR

0200
0201

000502
664000

PC
GSM

'0202
0203
0204
0205
0206
0207
0210

040207
200101
652000
200102
644323
000005
620200

DAC. +5
LAC DIVDl
LMQ
LAC DIVD2
DIVS

/PROGRAM ADDRESS
/STORE DIVR SIGN IN LINK AND ABSOLUTE
!VALUE IN AC
/DEPOSIT DIVR IN 0207
/LOAD HALF DIVIDEND INTO AC
/MOVE TO MQ
/LOAD HALF DIVIDEND INTO AC
/FETCH DIVR AND DIVIDE

JMP 1200

/RETURN TO MAIN PROGRAM

0100
0101
0102

000005
000012
000000

DIVISOR
DIVIDEND (LEAST SIGNIFICANT)
DIVIDEND (MOST SIGNIFICANT)

NOTE: The following discussion of a divide signed operation is usinga4bit divisor and 8bit dividend instead
of 18and 36. References toa given register bit 17 are referring to the least significant bit of the applicable
register.
Table 3-23
DIVS Functions

01 Ot} 0000 101 0

644305

Divide, Signed (Five Steps)

128 + 58

Process

Function

prawing No.

(ACO ,ARI, EAE , LI, CONT ,CMA43)
ACO(l)ANOSHAARI(l) = AC ... AR
SA09(0)ASA 10(1 )ASA 11 (1) = DIV
EAE(1)AARI(1) = SUl (1)
SU1(1) = 0 ... SCOV,SCOV2,FIRST,EAE RUN,MQ SIGN,EAE SIGN
SUl (1)ASETUP = SC CLR
SC CLR = 0 ... SC
SUl (1)AM BOO (0) = EAE OR MQO
LI(1) = 0 BUS L = ADRL ... LAR(O)
LI(1) = ADRL = LINK ... TEMP3(0)
TEMP3(0) = condition MQ SIGN
EAE(1) = 0 ... EN CMP~
ACOO(O) = no conditioning of EAE SIGN
CM STROBEACONT(1) = GO TO 43

(ACI,EAE,CONT ,CMA41)

KC20-21
KE4
KE3
KE2-3
KE2
KE2
KE3
KC15
KE3
KE3
KE3
KE3
KC16
KC18

EAE(1)AACI(l)ASETUP = SlJ2(1)
SU2(1) = MB12-17 = 111010 ... SC
SU2(1)J\MB06(1)AACOO(0) = no effect on EAE SIGN (EAE SIGN 0)
CM STROBEAEAE OR MQO = MQO(1)
MQO(1)ANOSHAACI(l) = MQ ... AC
U(O) = LAR(O) ... LINK(O)
CM STROBEACONT(1) = GO TO 41
41

KC18

(MQI,ACO, EAE,CONT ,CMA54)

KE3
KE2
KE3
KC19
KC20-21
KC15
KC16
KC18

ACO(1)ANOSHAMQI(1) = AC ... MQ
MQI(1)AMB08(O) = EAE OR ARO
CM STROBEt\CONT(l) = GO TO 54
3-36

KC20-21
KE3

KC16

Table 3-23 (cont)
DIVS Functions
644305

Divide, Signed (Five Steps)

Process

Function

KC18

(ACI, EAE-R,CONT ,CMA40)
CM STROBE/\EAE OR ARO = ARO(l)
ARO(l )/\NOSHMCI(l) = AR - AC
EAE-R(l}/\SCOV(O) = R-PULSE
R-PULSE = 111011 - SC
EAE-R(l )/\SCOV2(0) = ADDR 10
EAE-R(l )/\EIR09(0)/\SCOV2(0)/\EAE RUN(O) = ODD ADDR
EAE(0)/\TEMP3(0) = MQ SIGN(l)
MQ SIGN(l) = condition EAE SIGN
EAE-R(l) = 0 BUS L = LINK - TEMP2(0)
CM STROBE/\CONT(1)/\CMA40MDDR 10/\ODD ADDR = GO TO 51

Shift 1,
Sample

KC20-21
MC2
KC16
KC16

MB (DIVR ADDRESS)

KC18

(MBO, + 1,PCI, LI, CMA50)
+1 (1) = CIl7
MBO(l)/\NOSH/\CIl7/\PCI(1) = MB (DIVR ADDRESS) +1 +1 (1) = A BUS LINK - ADRL
LI(l) = ADRL - LAR(O)
LI(l)/\CONT(O) = EAE CLR RQ
LI(l)AADRL = TEMP3(0)
EAE CLR RQ = IN CLR, CLR
IN CLR = CLR 1= 0 - PCI, MBO
CLR=O-+l,l-SAO
IN CLR = 1 - MBI
SAO(1) - A BUS LINK - ApRL
SAO(l)/\NOSH/\MBI(l) = SA (DIVR) - MB
MEM STROBE = GO TO 50

KC19
KC20-21
KE2
KE2
KE3
KE3
KE3
KE3
KE3
KC16
KC18

(PCO ,SM,MBI,CMA52)
PCO(1)/\NOSH/\MBI(1) = PC SM(l)/\CLK = FETCH DIVR
SM(1)/\CLK = CM STROBE
CM STROBE = GO TO 52

Drawing No •

(MQO ,ARI, EAE-P ,CONT ,CMA42)
EAE-P(l)/\SCOV2(0) = EAE RUN(l)
EAE-P(l}/\EAE RUN(O) = FlkST(l)
FIRST(l)/\EAE RUN(l)/\MQ SIGN(l)=CMPL EAE SIGN=EAE SIGN(l)
EAE-P(l )/\SCOV2(0)/\DIV = IN SH Ll
IN SHLl = SHLl
MQO(1)/\SHL1/\ARI(1) = MQn - ARn-1
SH Ll = ADROO = MQOO(l) - 0 BUS L
EAE-P(l) = 0 BUS L - TEMP1 (l)
EAE-P(l) = TEMP2(0) - END BITOO (lost)
EAE-P(l} = TEMP3(0) - END BIT17
SHLl = END BIT17 - AR17(0)
LI(O) = LAR(O) - LINK(O)

3-37

KC14
KC20-21
KC15
KC15
KE3
KE3
KC16
KC19
KC19
KC19
KC15
KC20-21
KC16
KC18
KE3
KE3
KE3
KE4
KC13
KC20-21
KC15
KE3
KC15
KC15
KC20
KC15

Table 3-23 (cont)
DNS Functions
644305

Divide, Signed (Five Steps)

Process

Function

50 (cont)

42
j

Sub,
Sh ift 1

~
55
II'

Shift 2,
Sample

Add,
Shift 2

EAE-P(l )I\SCOV(O)A TEMP3(0)AD N = EAE OR SUB
EAE-P(l)ASCOV2(0)ADIV = EAE OR LI
CM STROBEACONT(l) = GO TO 42
(ACO,MQI, EAE-R,CONT ,CMA55)
CM STROBEAEAE OR SUB = SUB(1)
CM STROBEAEAE OR LI = LI(1)
EAE-R(1 )ASCOV(O) = R-PULSE
R-PULSE = 111100 - SC
EAE-R(1)ASCOV(O)AEAE RUN(1)ADIV = IN SHU
IN SHU = SHU
EAE-R(l)ASUB(1) = CIl7
SUB(1)ASHL1ACI17AMQI(1) = MB+l - MQn-l
ACO(1)ASHUAMQI(1) = ACn - MQn-l
SHL1 = ADROO(1) - 0 BUS L
EAE-R(1) = 0 BUS L - TEMP2(1)
U(l) = 0 BUS L - LAR(l)
EAE-R(l) = TEMP1 (1) - END BIT17
SHU = END BIT17-MQ17(1)
LINK(O)ASUB(l)AEAE R(1) = A BUS LINK
A BUS LINKA'COOO = ADRL
LI(1) = ADRL - TEMP3(1)
CM STROBEACONT(l) = GO TO 55
(ARO ,ACI, EAE-P ,CONT ,CMA53)
EAE-P(1)ASCOV2(0)ADIV = IN SHL1
IN SHU = SHU
EAE-P(1)AEAE RUN(1) = FIRST(O)
ARO(1)ASHUAACI(1) = ARn - ACn-l
SHLl = ADROO(O) - 0 BUS L
EAE-P(1) = 0 BUS L - TEMPl (0)
EAE-P(1) = TEMP2(1) - END BITOO (lost)
EAE-P(l) = TEMP3(1) - END BIT17
SHU = ENDBIT17 - AC17(1)
EAE-P(1)ASCOV2(0)AEAE OR SUBJ\O BUS 17ADIV = EAE OR MBO
LI(O) = LAR(1) - LINK(1)
EAE-P(1 )ASCOV2(0)ADIV = EAE OR U
CM STROBEACONT(1) = GO TO 53
(MQO ,ARI,EAE-R,CONT ,CMA56)
CM STROBEAEAE OR MBO = MBO(1)
CM STROBEAEAE OR LI = LI(l)
EAE-R(1)ASCOV(O) = R-PULSE
R-PULSE = 111101 - SC
EAE-R(l)ASCOV(O)AEAE RUN(1)ADIV = IN SHU
IN SHU = SHL1
MQO(1)I\SHLlI\ARI(l) = MQn -t ARn-l

3-38

Drawing No.
KE3
KE3
KC16
KC18
KC19
KC19
KE2
KE2
KE4
KC13
KE3
KC20-21
KC20-21
KC15
KE3
KC15
KC15
KC20
KC15
KC15
KE3
KC16
KC18
KE4
KC13
KE3
KC20-21
KC15
KE3
KC15
KC15
KC20
KE3
KC15
KE3
KC16
KC18
KC19
KC19
KE2
KE2
KE4
KC13

KC2Q-21

Table 3-23 (cont)
DIVS Functions
644305

Divide, Signed (Five Steps)

Process

Function

53 (cont)

Shift 3,
Sample

57
I

Add,
Shift 3

MBO(l)ASHL1AARI(l) = MBn ..... ARn-l
SHt 1 '="ADROO(l) ..... 0 BUS L
EAE-R(l) = 0 BUS L ..... TEMP2(1)
LI(l) = 0 BUS L ..... LAR(1)
LI(l) = ADRL ..... TEMP3(1)
EAE-R(l) = TEMPl (0) ..... END BIT17
SHL1 = END BIT17 ..... AR17(0)
LIN K(1 )ASUB = A BUS LIN K
A BUS LINIQ\COOO = ADRL
CM STROBEACONT(1) = GO TO 56
(ACO,MQI,EAE-P ,CONT ,CMA57)
EAE-P(1)ASCOV2(1)ADIV = IN SHU
IN SHU = SHL1
ACO(1)ASHUAMQI(l) = ACn ..... MQn-l
SHU = ADROO(l) ..... 0 BUS L
EAE-P(l) = 0 BUS L ..... TEMPl (1)
EAE-P(1) = TEMP2(l) ..... END BITOO (lost)
EAE-P(l) = TEMP3(1) ..... END BIT17
SHU = END BIT17 ..... MQ17(l)
EAE-P(1)ASCOV2(0)AEAE OR SUBAO BUS 17ADIV = EAE OR MBO
LI(O) = LAR(l) ..... LINK(l)
EAE-P(1)ASCOV2(O)ADIV = EAE OR LI
CM STROBEACONT(1} = GO Tb 57
(ARO ,ACI, EAE-R,CONT ,CMA40)
CM STROBEAEAE OR MBO = MBO(l)
CM STROBEAEAE OR LI = LI(1}
EAE-R(1}ASCOV(O) = R-PULSE
R-PULSE = 111110 ..... SC
EAE-R(l)ASCOV(O)AEAE RUN(l}ADIV = IN SHU
IN SHLl = SHU
ARO(1)ASHLlAACI(l) = ARn ..... ACn-l
MBO(l)ASHLlAACI(l) = MBn ..... ACn-l
SHLl = ADROO(1} ..... 0 BUS L
EAE-R(l} = 0 BUS L ..... TEMP2(1)
EAE-R(l) = TEMPl (1) ..... END BIT17
SHU = END BIT17 ..... AC17(l)
LI(1) = 0 BUS L ..... LAR(l)
LINK(1)ASUB = A BUS LINK
A BUS LINKACOOO = ADRL
LI(1) = ADRL ..... TEMP3(1)
EAE-R(1)ASCOV2(0) = ADDR 10
CM STROBEACONT(1)1\CMA4MADDR 10 = GO TO 50

3-39

Drawing No.
KC20-21
KC15
KE3
KC15
KE3
KC15
KC20
KC15
KC15
KC16
KC18
KE4
KC13
KC20-21
KC15
KE3
KC15
KC15
KC20
KE3
KC15
KE3
KC16
KC18
KC19
KC19
KE2
KE2
KE4
Kt13
KC20-21
KC20-21
KC15
KE3
KC15
KC20
KC15
KC15
KC15
KC15
KE3
KC16

Table 3-23 (cant)
DIVS Functions
644305

Divide, Signed (Five Steps)

Process

Function

Shift 4,
Sample

42
~

Add,
Shift 4

Shift 5,
Sample

(MQO ,ARI, EAE-P ,CONT ,CMA42)
EAE-P(l)/\SCOV2(0)/\DIV = IN SHLl
IN SHLl = SHLl
MQO(l)/\SHLlMRI(l) = MQn .... ARn-l
SHLl = AD ROO(O) .... 0 BUS L
EAE-P(l) = 0 BUS L .... TEMPl (0)
EAE-P(l) = TEMP2(l) .... END BITOO (lost)
EAE-P(l) = TEMP3(1) .... END BITl7
SHLl = END BIT17 .... AR17(1)
LI(O) = LAR(l) .... LINK(l)
EAE-P(l )/\SCOV2(0)/\EAE OR S UB/\O BUS 17/\D N. = EAE OR MBO
EAE-P(l)/\SCOV2(0)/\DN = EAE OR LI
CM STROBE/\CONT(l) = GO TO 42
(ACO, MQ I, EAE-R, CONT, CMA55)
CM STROBE/\EAE OR MBO = MBO(l)
CM STROBE/\EAE OR LI ;;; LI(l)
EAE-R(l)/\SCOV(O) = R-PULSE
R-PULSE = 111111 .... SC = SC FULL
EAE-R(l)/\SCOV(O)/\EAE RUN(l )/\D N = S HLl
IN SHLl = SHLl
ACO(l)/\SHLl/\MQI(l) = ACn .... MQn-l
MBO(l)/\SHLl/\MQI(l) = MBn .... MQn-l
SHLl = AD ROO(O) .... 0 BUS L
EAE-R(l) = 0 BUS L .... TEMP2(0)
U(l) = 0 BUS L - LAR(O)
EAE-R(l) = TEMPl (0) - END BIT17
SHU = END BIT17 .... MQ17(0)
LINK (1)/\S UB = A BUS LINK
A BUS UNKACOOO = ,A.DRL
LI(1) = ADRL .... TEMP3(0)
CM STROBE/\CONT(l) = GO TO 55
(ARO ,ACI, EAE-P ,CONT ,CMA53)
EAE-P(l)/\SCOV2(0)/\DIV = IN SHU
IN SHU = SHU
ARO(l)/\SHU MCI(l) = ARn - ACn-I
SH L1 = ADROO(O) - 0 BUS L
EAE-P(l) = 0 BUS L .... TEMPI (0)
EAE-P{l) = TEMP2(0) .... END BITOO (lost)
EAE-P(l) = TEMP3(0) .... END BIT17
SHU = END BITl7 .... ACI7(0)
EAE-P(1)/\SCOV2(0)/\DIV = EAE OR LI
EAE-P(l)/\SCOV(O)/\ TEMP3(0)/\DIV = EAE OR SUB
LI(O) = LAR(O) .... LINK(O)
CM STROBEACONT(l) = GO TO 53

3-40

Drawing No.
KC18
KE4
KC13
KC20-21
KC15
KE3
KC15
KC15
KC20
KC15
KE3
KE3
KC16
KC18
KCl9
KCl9
KE2
KE2
KE4
KCl3
KC20-21
KC20-21
KCl5
KE3
KC15
KC15
KC20
KCl5
KCl5
KE3
KC16
KCI8
KE4
KCI3
KC20-2I
KCI5
KE3
KC15
KC15
KC20
KE3
KE3
KCI5
KC16

Table 3-23 (cont)
DIVS Functions
644305

Divide, Signed (Five Steps)

Process

Function

Sub

Shift 5,
Sample

Add

(MQO ,ARI, EAE-R,CONT ,CMA56)
CM STROBEAEAE OR SUB = SUB(l)
CM STROBEAEAE OR LI = LI(l)
EAE-R(l) = R-PULSE
R-PULSE = 000000 - SC
R-PULSEASC FULL = SCOV(l)
SCOV(l) = IN SHL 1
SUB(l)AEAE-R(l) = CIl7
SUB(l)ANOSHACIl7AARI91) = MB+1 - AR
MQO(l)ANOSHAARI(l) = MQ - AR
SUB(l)AEAE-R(l)ALINK(O) = A BUS LINK
A BUS LINKACOOO = ADRL
SHIFT= ADRL - 0 BUS L
EAE-R(l) = 0 BUS L - TEMP2(l)
LI(l) = 0 BUS L - LAR(l)
LI(l) = ADRL - TEMP3(1)
CM STROBEACONT(l) = GO TO 56
(ACO,MQI,EAE-P ,CONT ,CMA57)
EAE-P(1)ASCOV2(0)ADIV = IN SHU
IN SHU = SHU
ACO(l)ASHUAMQI(l) = ACn - MQn-l
SHU = ADROO(l) - 0 BUS L
EAE-P(1) = 0 BUS L - TEMPl (1)
EAE-P(l) = TEMP2(1) - END BITOO (lost)
EAE-P(1) = TEMP3(l) - END BITl7
SHU = END BITl7- MQ17(1)
EAE-P(l)ASCOV2(0)AEAE OR SUBAO BUS 17ADIV = EAE OR MBO
EAE-P(l)J\SCOV2(l)ADIV = EAE OR LI
LI(O) = LAR(l) - LINK(1)
CM STROBEACONT(l) = GO TO 57
(ARO ,ACI, EAE-R,CONT ,CMA40)
CM STROBEAEAE OR MBO = MBO(l)
CM STROBEAEAE OR LI = LI(l)
EAE-R(l)ASCOV(l) = SCOV2(1)
SCOV(l) = IN SHLl
ARO(l )ANOSHAACI(l) = AR - AC
MBO(l)ANOSHAACI(l) = MB - AC
A BUS LINKACOoo = ADRL
SHIFT = ADRL - 0 BUS L
EAE-R(l) = 0 BUS L - TEMP2(0)
LI(1) = 0 BUS L - LAR(O)
LI(l) = ADRL - TEMP3(0)
EAE-R(l)ARUN(l) = ADDR 10
CM STROBEACONT(1)ACMA4()'\ADDR 10 = GO TO 50

3-41

Drawing No~
KC18
KC19
KC19
KE2
KE2
KE2
KE4
KE3
KC20-21
KC20-21
KC15
KC15
KE3
KC15
KE3
KC16
KC18
KE4
KC13
KC20-21
KC15
KE3
KC15
KC15
KC20
KE3
KE3
KC15
KC16
KC18
KC19
KC19
KE2
KE4
KC20-21
KC20-21
KC15
KC15
KE3
KC15
KE3
KE3
KC16

Table 3-23 (cont)
D IVS Functions
Divide, Signed (Five Steps)

644305

Function

Process
50

(MQO ,ARI, EAE-P ,CONT,CMA42)
SCOV2(1) = IN SHL 1
SCOV2(1} = EAE OR MBO, EAE OR SUB, EAE OR LI
MQO(1}ANOSHAARI(1} = MQ - AR
LI(O) = LAR(O) - LINK(O)
LlNK(O) = ADRL
SHIFT = ADRL - 0 BUS L
EAE-P(l) = 0 BUS L - TEMP1 (0)
EAE-P(1) = TEMP2(O) - END BITOO (lost)
EAE-P(1} = TEMP3(0) - END BIT 17
CM STROBEACONT(l) - GO TO 42

(ACO, MQ I, EAE-R, CO NT, CMA55)
EAE-R(1}ASCOV2(l) = EAE RUN(O)
ACO(1)ANOSHAMQI(l) = AC - MQ
CM STROBEACONT(1) = GO TO 55

(ARO ,ACI, EAE-P ,CONT ,CMA53)
ARO(l )ANOSHAACI(l) = AR - AC
CM STROBEACONT(1) = GO TO 53

(MQO ,ARI, EAE-R,CONT ,CMA56)
MQO(1)ANOSHAARI(l) = MQ - AR
CM STROBEACONT(l) = GO TO 56

(ACO ,MQI, EAE-P ,CONT ,CMA57)
EAE-P(l)AMQI(l)AACO(l)AEIR09(0)ASCOV2(l) = EN CMPL(l)
EN CMPL(l)AEAE SIGN(l) = CMPL
ACO(l )ANOSHAMQI(l )ACMPL = AC - MQ
CM STROBEACONT(1} = GO TO 57

(ARO ,ACI, EAE-R,CONT ,CMA40)

Drawing No.
KC18
KE4
KE3
KC20-21
KC15
KC15
KC15
KE3
KC15
KC15
KC16
KC18
KE3
KC20-21
KC16
KC18
KC20-21
KC16
KC18
KC20-21
KC16
KC18
KE3
KE3
KC20-21
KC16
KC18

EAE-R(1)ADIV!\EN CMPLAMQ SIGN(1)AEAE SIGN(1) = EAE SIGN(O) KE3
EAE SIGN(O) = CMPL
KE3
KC2o-21
ARO(1)ANOSHAACI(l)ACMPL = AR - AC
EAE-R(l)ASCOV2(l)ARUN(0) = ADDR 10
KE3
CM STROBEACONT(l) = GO TO 40
KC16
40

(EAE, DONE, CMA 10)

KC18

CLK(B) DL YDAEAE(1)ADONE(l) = INPUT 10 RESTART
10 RESTART = GO TO 10
10

(PCO,SM,CMA21)

KD3
KC16
KC18

BGN next fetch

3-42

Table 3-24
DIVS Arithmetic
128 + 58

L TEMP3
i

0000

1010

MB 1010~CIl7
l~CRy-T6Tl
SHLl

:> 0111

V
t
1
1

1001-SHLl
'JSHLl
1011

0011

1011
MB 0101
0E--CRY-1 OOOO-SHll
r+sample
I
t~SHLl
11 1
0

1110

1110 -SHLl

55
53
56

0100

1000
MB 0101
1101
I

>SHLl~Ollf

0011
~

:> 0000

0111

0000
MB 101O-C1l7
CRY-lOll

0111

> sample

:> 1011

f~sample

SH L1 ---;.; 00*

CRY

if
50

0100
0100

0111
MB 0101
"ClrY-I100
rsample
:>001

1001

i>sample
SHLl

SHLl

sample
100 <

~110

0000 E

1101

1011
MB 0101
CRY- 1
0000 --,

0000

1101

11 01

0000

:> 0000

1101

1101 c:

0000

1101

1 101

0000

>0000

1101

:>0010

0000

0000 E

0010

0000

CMPL

answer
28

3-43

Table 3-25
DIVS Functions
Process

Function

TEMP3(1) = no conditioning of MQ SIGN
ACOO(O) = no conditioning of EAE SIGN
EAE(1) = 0 - EN CMPL

MQ -AC

AC-MQ

EAE(O)A TEMP3(1) = no effect on MQ SIGN

51 through last 53 same as DIVS 128 + 58
56

EN CMPL(l)AEAE SIGN(O) = CMPL
AC-MQ

CMPL = AR - AC

Table 3-26
DIVS Functions
Process

Function

TEMP3(0) = condition MQ SIGN
ACOO(1) = condition EAE SIGN
EAE(l) = 0 - EN CMPL

MB06(1)J\SU2(1) = EAE SIGN(1)
SU2(1)AEAE SIGN(l) = CMPL
CMPL=MQ - AC

AC-MQ

EAE(0)ATEMP3(0) = MQ SIGN(l)
MQ SIGN(1) = condition EAE SIGN

51,52

same as DIVS 128 + 58

FIRST(l)AEAE RUN(l)AMQ SIGN(1)AEAE SIGN(l) == EAE SIGN(O)

42 through last 53 same as DIVS 128 + 58
56

EN CMPL(1)AEAE SIGN(O) == CMPL
AC-MQ

EAE-R(l)A EN CMPL(l)AOIV AMQ SIGN(l)AEAE SIGN(O) == EAE SIGN(l)
EAE SIG.t!i1)AEN CMPL(1) == CMPL
CMPL==AR -AC

3-44

Table 3-27
DIVS Functions
-12 +-5

TEMP3(l) = no conditioning of MQ SIGN
ACOO(l) = condition EAE SIGN
EAE(l) = 0 - EN CMPL

MB06(1)J\SU2(1) = EAE SIGN (1)
SU2(1)J\EAE SIGN(1) = CMPL
CMPL = MQ - AC

AC -MQ

EAE(O)J\ TEMP3(1) = no effect on MQ SIGN

through last 53 same as 128 + 58

EN CMPL(1)J\EAE SIGN(1) = CMPL
CMPL=AC - MQ

EAE-R(1)J\EN CMPL(1)J\DIVJ\MQ SIGN(O) = no effect on EAE SIGN(1)
EAE SIGN(I)J\EN CMPL(1) = CMPL
AR .... AC

3.8.2

Function

Process

IDIV (S) Instruction
The IDIV(S) instruction divides the contents of the AC (integer dividend) by the contents of

the Relict sequential core memory location to form a quotient in the MQ and a remainder in the AC.
The arithmetic phase of the instruction(s) is identical to that of DIV(S). The preparatory
phase transfers the contents of the AC to the MQ and clears the AC. Thereafter the arithmetic phase
in reality performs the division on the long register dividend just as for DIV. The exception here is that
I

the most significant portion of the dividend (AC) is at O.
Therefore, the DIV(S) functions of Table 3-23 hold true for IDIV(S) with the following preparatory exceptions.
75) SUI (1)J\MB07(1) = EAE OR ARO
AC .... AR (same)
43) AR .... AC
41) MB08(l) = EAE OR ARO
AC .... MQ (same)
54) ACI(1) = 0 .... AC
The rule for divide overflow, Section 3.8.4 is the same. In the IDIV(S) case overflow occurs
on Iy if the computer attempts to divide by 0, since this is the on Iy quantity not larger than the AC portion of the dividend.
The sample divide in Table 3-23, although performed by a DIVS instruction, could in fact be
used as a sample IDIVS operation since the arithmetic phase also starts with a zero quantity in the AC.

3-45

3.8.3

FRDIV(S} Instruction
Th.e FRDIV(S} instruction divides the contents of the AC (fraction dividend) by the contents

of the next sequential core memory location to form a quotient in the MQ and a remainder in the AC.
The arithmetic phase of the instruction (s) is identical to that of DIV(S}. The preparatory
phase clears the MQ. The arithmetic phase thereafter is in reality a division of the long register with
the MQ at O. For FRDIV the binary point is assumed at the left of ACOO. For FRDIVS the binary point
is assumed between ACOO and ACOI. The divide overflow rule, Section 3.8.4, is the same.
The DIV(S} functions of Table 3-23 hold true for FRDIV(S} therefore, with the following
exceptions.
75} SUI (l)AMB05(1) = EAE OR MQO
SUI (l)AMB07(0) = EAE OR ARO
AC - AR (same)
43} ACI(l) = 0 - AC
41) AC -

MQ (same)

54) AR - AC (same)

3.8.4

Divide Overflow
For all divide instructions the first subtract operation of the arithmetic phase checks for a

divide overflow situation. Divide overflow exists when the computer attempts to divide a dividend by
a divisor which is not numerically greater than the most significant portion (AC) of the dividend. If
the divide operations were carried out, the result would exceed the capac ity of the 18-bit MQ register,
and the MQ contents would be erroneous. For unsigned division, the capacity of the MQ is 2 18 _1, or
7777778 . For signed division the capacity is+2 17_1, or +3777778 •
For all divide instructions process word 52 during the divisor fetch from memory blocks the
recirculation of the LINK into the LARi process word 50 transfers the lAR content(O) into the LINK and
starts the arithmetic phase of the instruction. The arithmetic phase therefore always starts with the
LINK in the reset state. The LINK returns to the reset state at the end of all valid divide instructions.
If, however, the EAE logic encounters the divide overflow situation, the LINK sets and the instruction

execution is halted after five machine cycles as a time-saving feature. The computer will then go on
to the next instruction, which is usually an instruction which tests the status of the LINK (OPR SZl,
OPR SNl, etc.).
Table 3-28 lists the functions that provide the overflow indication to the LINK and stop the
divide operations. The listing starts with process word 50, at wh ich point the preparatory phase has
been completed, the divisor is in the MB, and the dividend is correctly placed in the AC and MQ. The
operation attempts to divide 32 10 by 2 10 for a quotient of 16 using a 4-bit MQ register, resulting in

overflow since the register capacity is 15 for unsigned divide.
3-46

Note from Table 2-3 that a valid five-step arithmetic divide operation requires seven machine
cycles for completion, whereas divide overflow stops the operation after the first step and five cycles.
For the overflow situation the step count in the SC does not matter since the DIV OV flip-flop controls
the SCOV, SCOV2, and RUN functions.

Table 3-28
DIV OV Functions
640305

Divide, Unsigned (Five Steps)

Process

Function

(MQO ,ARI,EAE-P ,CONT ,CMA42)
EAE-P(l)AEAE RUN (0) = FIRST (1)
EAE-P(l)ASCOV2(0) = EAE RUN(l)
EAE-P(l) etc. = SHU
FIRST(l)J\EAE RUN(l)J\MQ SIGN(l)J\EAE SIGN(O) = EAE SIGN(l)
LI(O) = LAR(O) - LINK(l)
EAE-P(l)ASCOV(0)ATEMP3(O)ADIV = EAE OR SUB
EAE-P(1 )ASCOV2(0)ADIV = EAE OR LI
MQO(l)ASHLlAARI(l) = MQn - ARn-l
SHU = ADROO(O) - 0 BUS L
EAE-P(l) = 0 BUS L - TEMPl (0)
EAE-P(l) = TEMP2 - END BITOO (lost)
EAE-P(l) = TEMP3(0) - END BITl7
SHL 1 = END BITl7- AR 17(0)
CM STROBEACONT(l) = GO TO 42

(ACO ,MQI, EAE-R,CONT ,CMA55)
CM STROBEAEAE OR SUB = SUB(l)
EAE-R(l)ASUB(l) = CI17
CM STROBE EAE OR LI = LI(l)
EAE-R(l), etc. = SHLl
ACO(l)ASHLlJ\MQI(l) = ACn - MQn-l
SUB(l)ASHUAMQI(l)ACI17 = MB+l - MQn-l
EAE-R(l)J\SUB(l)AUNK(O) = A BUS LINK
A BUS LINKJ\COOO = ADRL
ADRL = ADRL(B)
EAE-R(l)AFIRST(l)J\ADRL(B)ADIV = DN OV(l)
SH L1 = ADROO(O) - 0 BUS L
EAE-R(l) = 0 BUS L - TEMP2(0)
EAE-R(l) = TEMPl (0) - END BIT1?
SHLl = END BITl7 - MQ17(0)
LI(l) = DIV OV(l) - LAR(l)
LI(l) = ADRL - TEMP3(0)
CM STROBEACONT(l) = GO TO 55

(ARO ,ACI, EAE-P ,CONT ,CMA53)
EAE-P(l)ARUN(l) = FIRST(O)
EAE-P(l)ADIV OV(l) = DN NO GO
DIV NO GO = SCOV(1),SCOV2(1),EAE RUN(O)

3-47

Drawing No.
KC18
KE3
KE3
KE4
KE3
KC15
KE3
KE3
KC20-21
KC15
KE3
KC15
KC15
KC20
KC16
KC18
KC19
KE3
KC19
KE4
KC20-21
KC20-21
KC15
KC15
KC15
KE3
KC15
KE3
KC15
KC20
KC15
KE3
KC16
KC18
KE3
KE2
KE2-3

Table 3-28(cont)
DIV OV Functions
640305

Divide, Unsigned (Five Steps)

Process

Function

55 (cont)

Drawing No.

U(O) = LAR(l) - LINK(l)
SCOV2(l) = IN SH L1
ARO(l )ANOSHAACI(l) = AR - AC
CM STROBEACONT(l) = GO TO 53

KC15
KE4
KC20-21
KC16

(MQO,ARI, EAE-R,CONT ,CMA56)

KC18

MQO(l)ANOSHAARI(l) = MQ - AR
CM STROBEACONT(l) = GO TO 56
56

(ACO ,MQI, EAE-P ,CONT ,CMA57)
ACO(l)ANOSHAMQI(l)ACMPL = AC CM STROBEACONT(l) = GO TO 57

KC20-21
KC16
KC18
MA

(ARO ,ACI,EAE-R,CONT ,CMA40)

KC18

ARO(l )ANOSHAACI(l) = AR - AC
EAE-R(l)ASCOV2(l)AEAE RUN(O) - AD DR 10
CM STROBEACONT(1)ACMA40AADDR 10 - GO TO 40
40

KC20-21
KE3
KC16
KC18

(EAE, DONE ,CMA 10)
CLK(B) DL YD EAE(l) DONE(l) = INPUT 10 RESTART
10 RESTART = GO TO 10

KC20-21
KC16

(PCO ,SM,CMA21)

KD3
KC16
KC1S

BG N next fet ch

3.9

EAE INSTRUCTION DEVELOPMENT
The addition of nS bits to the basic EAE op code 64S converts the basic instruction to a micro-

coded instruction to accomplish a setup, shift, or arithmetic operation not already in the instruction
repertoire. Refer to Table 3-29 for descriptions of the functional use of the individual bits. The sole
restriction for development of "n" is that the microcoded operations must not occur during the same
process word if they logically conflict.

Table 3-29
EAE Microinstructions
Bit

Binary
Code

Function

Enters ACOO into the LIN K for signed operations.

Clears the MQ.

3-48

Table 3-29 (cont)
EAE Microinstructions
Bit

Binary
Code

Function

Reads ACOO into the EAE SIGN register prior to a signed multiply
or divide operation.

6,7

Takes the absolute value of the AC after the ACOO bit is read
into the EAE SI GN register.

Inclusive-ORs the AC with the MQ and places the result in the
MQ.

Clears the AC.

9,10,11

000

SETUP instruction code. Accompanies code in bits 15, 16, 17.

9,10,11

001

MUL instruction code.

9,10,11

010

Unused instruction code.

9,10,11

011

DIY instruction code.

9,10,11

101

LONG RIGHT SHIFT instruction code.

9,10,11

110

LON G LEFT SHIFT instructions code.

9,10,11

100

NORMALIZE instruction code.

9,10,11

III

ACCUMULATOR LEFT SHIFT instruction code.

12-17

Specifies the step count for all EAE codes (9-11) except SETUP.

For SETUP instruction code on Iy, complements the MQ contents.

For SETUP instruction code only, inclusive-ORs the MQ with the
AC and places the result in the AC.

For SETUP instruction code on Iy, inc lusive-ORs the AC with the
SC and places the result in the AC.

3-49

CHAPTER 4
MAINTENANCE

4.1

GENERAL MAINTENANCE
The general maintenance practices described in the PDP-9 Maintenance Manual also apply

to the EAE option.

4.2

MAINTENANCE PROGRAM TAPES
Chapter 1 of the PDP-9 Maintenance Manual lists the diagnostic tapes and documents for

use with the EAE.

4.3

REPLACEABLE PARTS
Table 4-1 lists a" logic modules used in the EAE option by DEC type and quantity. The CP

UML drawing KC8 shows the module locations in the central p'rocessor wing of the PDP-9 frame. DEC
has available a spare modules kit, SP09A, for use with the basic PDP-9 system and including spares for
the E:AE option. If the kit is not on hand, it is recommended that one spare module of each logic type
be stocked to reduce equipment down-time while repairing faulty modules.

Table 4-1
EAE Module Complement
DEC Type

t()

Module Type

Quantity

t/B105"

Inverter

v"B 133"

Inverter

A213 J

Flip-Flop

vROO2

Diode Network

tAll 1

NAND/NOR Gate

~151 .I

Binary-to-Octal Decoder

",. S 181

DC Carry Chain

.,.S206 v

Flip-Flop

'/wOO5

Clamped Load

4-1

CHAPTER 5
ENGINEERING DRAWINGS

This chapter contains a complete set of engineering drawings pertaining to the EAE option
along with circuit schematics of all logic modules. DEC engineering drawings are encoded as to type,
major assembly, and series. Drawing number codes and signal conventions are explained in Chapter 5
of the PDP-9 Maintenance Manual.

5.1

SIGNAL MNEMONIC IND1:X
All signals originating on the EAE logic drawings are listed below in alphanumeric order.

The Origin column locates the source of the signals to the specific logic drawing, using the abbreviated
drawing number system.

Signal

Origin

A BUS LINK

KE3

Enter ACOO into LINK

ACO -

KE3

Recirculate LINK via LAR

ADDR 10

KE3

Add 10 to next Control Memory address

ALS

KE4

Accumulator Left Shift command

CMPL

KE3

Complement the register contents in transfer

CI17

KE3

Initiate a carry into the Adder

DIV

KE4

Divide command

DIV NO GO

KE2

Stop divide operations

DIV OV

KE3

Divide Overflow

EAE CLR RQ

KE3

Clear CM gating bits for argument fetch

EAE OR ARO

KE3

Set ARO bit on next CM STROBE

EAE OR LI

KE3

Set LI bit on next CM STROBE

EAE OR MBO

KE3

Set MBO bit on next CM STROBE

EAE OR MQO

KE3

Set MQO bit on next CM STROBE

EAE OR SUB

KE3

Set SUB bit on next CM STROBE

EAE PWR CLR

KE3

Clear flip-flops on power turn-on

EAE RUN

KE3

Start EAE instruction execution

EAE SIGN

KE3

Store ACOO

EIR09-11

KE4

EAE instruction register

EN CMPL

KE3

Enable complement function

FIRST

KE3

Start first arithmetic operation

LINK

Description

5-1

Signal

Origin

Description

IN SHU

KE4

Enable Sh ift left Functi on

IN SHR1

KE4

Enable Sh ift Right function

llS

KE4

long left Shift command

lRS

KE4

long Right Shift command

MQ SIGN

KE3

Store divisor or multiplicand sign

MUl

KE4

Multiply command

NORM

KE4

Normalize command

ODD ADDR

KE3

Add 1 to next CM address

o BUS17(B)

KE3

END Bit shifted into next register

R-PUlSE

Kf2

Up-date the Step Count

SC12-17

KE2

Step Counter register

SC ClR

KE2

Clear the Step Counter

SC FUll

KE2

Step Counter up-dated to 778

SCO

KE2

Step Counter output gate

SCOV

KE2

Step Counter up-dated to 008

SCOV(l)

KE2

Set SCOV on normalize condition

SCOV2

KE2

Step Counter up-dated to 008

SETUP

KE4

Setup command

SUl-3

KE3

Setup or preparatory instruction phase

TEMPl-3

KE3

Te"!porary LINK and END Bit storage

5.2

DRAWING LIST
Below is a list of all drawings included in this chapter. Other related EAE logic is included

in the Chapter 5 drawings of the PDP-9 Maintenance Manual as part of the prewired, basic system.

Drawing Number

Title

Revision

Page

B-CS-B105-0-1

Inverter B1 05, Circuit Schematic

5-4

B-CS-B133-0-1

Inverter B133, Circuit Schematic

5-4

B-CS-B213-0-1

Flip-Flop B213, Circuit Schematic

5-5

B-CS-ROO2-0-1

Diode Network R002, Circuit Schematic

5-5

B-CS-R 111-0-1

NAND/NOR Gate R111, Circuit Schematic

5-6

B-CS-S 151-0-1

Binary-to-Octal Decoder S151, Circuit
Schematic

5-6

B-CS-S181-0-1

DC Carry Chain S 181, Circuit Schematic

5-7

B-CS-5206-0-1

Flip-Flop 5206, Circuit Schematic

5-7

5-2

,--.

Drawing Number

Title

Revision

Page

B-CS-WOO5-0-1

Clamped Load WOOS, Circuit Schematic

5-8

D-BS-KE09-A-2

EAE Step Counter and Control, Block Schematic

5-9

D-BS-KE09-A-3

EAE Operand Fetch Gating, Block Schematic

5-11

D-BS-KE09-A-4

EAE Execution Gating, Block Schematic

5-13

D-BS-KE09-A-5

EAE Data Flow, Flow Diagram

5-15

D-BS-KE09-A-6

EAE Flow, Flow Diagram (Sheet1)

5-17

D-BS-KE09-A-6

EAE Flow, Flow Diagram(Sheet2)

5-19

Link Control for EAE Instructions

5-3

5-21

r:T~~~E-l

r-----------~----------_1~----------._----------_.------------~,~I~~,~~~O.-15V
I

RII

l,soo :

.. 5Y'

119

1,500

I
:

09
:
662,

.01

MFO

.(II

MFO

r---------------------._---------------------.--------------------~~----~~~~~~--+,~~~C
_ _ _ _ ...J

CI
RI2
100
10'110

C5
.11
MFO

eND

00-...."",.,.....-+1

UNLESS OTtERWISE INDICATEO'

RESISTORS lIE 1/4Wi " '
CAMCllORS ME 111"'0
TRANSISTORS ARE DEC 2894 .. 11

B-CS-Bl05-0-1

Inverter Bl05, Circuit Schematic

r-------------------~------------------~~------------------~----_o~)

•.-.v

r-------------.-------~------------_1~------~------------~--------+_------------~------~~----_O
R7
7.500

RI
7,500

0-"1. &

011

011
OM
e-ea
0-_

~--------------------~~._----------------~----~------~~--~~_o'c 8MD

C•

.GI

I -IV

1
I

L
_____ ",I
I STRATE

UllLDI ~ _"Tallo
. . . ._
. . AU
...... 5%
_
__
0-. . ."4111
~1

USE THE ETCH lOARO

THE 8115

. . , ........ , .... .. , ,
1------------------1
,

B-CS-B133-0-1

;

Inverter 8133, Circuit Schematic

•
D'

••

1,000 A
"D.(v

.04
liFO

••

••6,100

6,s00

100

IO~.

CI
10
liFO

P'
U

QT\t!

ell;;
ole

A~DID

1,000

DT A~

010
100
10%

A
013

•

+ lOY

OMS

1,600 A

RI'

02.
6,800

IO~.

I ~~ 020

DItA

\ '-..

..... ~

047

10-'.

2T
100
"'MFO 10".

4TO

1,500

TOO

R'
7,500

~.
R7

I,~

DEC
36398

AI2
7,500

UNLESS OTHERWISE INDICATED;

.01
MFD

'-..

.01

01'

0,.
1,500

R22
470
10OV.

I.~O

.,0

750

R"
7,500

MMFO

010

0664
09

0664

D664

066.
DT

0664

02
RO

0664

D664

1::::::::::::;:::::1

B-CS-ROO2-0-1 Diode Network ROO2,
Circuit Schematic

5-5

,02T

O.62

,02 o
DO 02

-.~

•

,02
0 862

~
J

R2.
1.500

R2.

R.O

TOO

-15\1

B-CS-B213-0-1 Flip-Flop B213,
Circuit Schematic

0664

100
10,".
R26

DEC

.....

D664

R2T

7,500

R21

~.500

I ::::::::~:::::::::I

HJ:

6
02

DEC

MFO

~
T

R[SISTORS ARE 1/4Wi 5"'DIODE S ARE 0664TRANSISTORS ARE DEC 3009B

"g~

-2.ZV

y~ ~J eMii
•
• 'O~O
..... ~

•

,,~2862

r-<

012

' 0 : w OEC
.

' 0. .

-3.5\1

I
~

030

02.

C9,fV 013

10
IIMFD

"'0..2

~B ~:O,

.2'
100
10%

-.V

CIO

Hf-<

~Q14
.20
6,800

100

•••

1,000

01.

012

J~'

I~~D.

(p'

•

M OND

,..-

,----,

r---------------------------.---------------------------~--------------------------~A.,~I
"2

r----------------t-----1~------------------~r_--~t_------_.--_+r--~-~-------~l~,c

01.
I
~-,

DEC 3139

DEC 3U9

I
D4
1
0 .... :

D-MI

01 I

:
I
I

11-4184

••

11.000

DII
D-_
"0--tM-....
D-_
o-.............+-oT

DIS4 I 5

CI
.DO

0664,

D...

01
I
~-,

Do--tM-;....

GND

.-l

7. BOO I
ft

.~D

1Il,000

0-88. 1

DOl

DID
~"4

L 0--111-.....-0.

1
Dl7
1
0-. .1 :

-...

...s7,..

~8DO

2 I

:'- _____________
EXAMPLE DGL2 .J:

-3V

LSTRATE
_____ _

UNLESS OTHERWISE INDICATED:

"ESISTORS ARE 114.; 511.
PRINTED CIRCUIT REV. FOR
OIL IOMD IS SIB

1------------------1
... Y'

t'".

,. t

••

, ..

8-CS-R1l1-0-1 NAND/NOR Gate R1ll,
Circuit Schematic

r---------~--------~~--------~--------_.--------~~------~~--------~------------------~A.IOV~J
03
R4
01
01
02
AS
100,000
100,000
IDO,DOC
100,000
100POO
100,000
100,000

i(':
~D
0---

~~Z5

18,000

RID
033 ..,000
0-662

A..
034 1Spoe

0-662

,
OIS
031 11,000
0-862

AI2
035 "POD
0-662

USE THE ETCH BOARD OF THE RI~I

B-CS-S151-o-1

Binary-to-OctaI Decoder S151,
Circuit Schematic

5-6

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 114W, 511TRANSISTORS ARE DEC 363'.
DIODES ARE 0-814

r-----------.-----------~----------~----------_.----------~----------_.---------------------oA+IOV

r-----r---~.-----;_--=1~----;_--~~----_r--~=t----;_----~----_r----~------~--_.---oCGND

+-----+-_1~~----_r_1~~----_r_,~~----_t--~~~--_r----~_1~_t----~~~--~-------oa-IBV

~~~¥~~

'---------------------0 D

8-CS-S181-0-1 DC Carry Chain S181,
Circuit Schematic

~DII3

~L
I

'os

J.5
r

~
r

D".

~D54

R4
100,000

~
I 0

01
RZ
R'
7,SOD 7,500

>-OK

100POO

Da
Deez

•

010

Oil

~~ ;,~

DIll

DB'

>-OIl. RI •
1 017

DZ4

'~~e.

Dza

025

0"
RIO
7,l100

01.

""
C2

,!!S
H

*055

I 0

034

"17

~,':OO

;,~ RII
7,Il00

...
Di

RI4
RIS
~::oo 7,SOD 7,500 l,soo

'040 '04&

"!'

038
DMZ
037
1 DMI

1 052
De..

Oil

0...

os..

iii.

Re
R7
1,500 7,soo

100,000

.;.

~l"

030

A+IOV

RiO
100POO

* ~
C4
82

C3
az

eez

RElllTO.S ME 114.; a..
CANeITO"1 ALU .... '0

TRAN_TORS ARE ... 4313

1 OZI

UNLESS OTHERWISE INDt(:AT£D:

OIOOEI ARE Dee4

D07
N

C IND

C6
8Z

~o:.

051
DAI

..
038

C7
.01
D,!J

Dee.

04.

RII
7,500

Dee.

RU
R24
7,SOD 7,Il00

ml -

;,~ 7,500
D~

D~"

CS
81

on
II

tON

8-CS-S206-o-1 Flip-Flop S206,
Circuit Schematic

5-7

DSO

"'"'

RIS

t,SOO

D4S
V

DIO

* 0. .

.01
".0

r------,

B·ISV

I' 0"
I ',000
I

I•

.."

>POO
C2

.0'

Mrn

C eND

c:a

.(II

.01

Mrn

M'O

>POD
-!V

,, ....
,
"
,
I

',Il00

or._.
_'_O-.u

: -3V
IL..STRATE
_____ .J

.... 01
..aIeATED:
.IIITOIII AIlE 114", ...

I ::::::;::::;::::;: I

B-CS-W005-0-1 Clamped Load W005,
Circuit Schematic

5-8

)

CML
~c:,.:.~CO"

-..J:>

A IllS LINK

SUIIIl
MBe4111

UIII

Acelill

LIlli

UI
I

....
I>.)

•

•
TEMP211l~'"

AXSlel

EAE-PI1l~

EAE-PIII

TEMP311l

TEMPI III

EAE-RI1l

EI.E-Rlel

iNSHRt ---.I,,,,,,,,,
iNsiiIT~
DIV DVm

link Control for EAE Instructions

E,:D BIT e

DIGITAL EQUIPMENT

CORPORATION

Printed in U.S.A.

MAYNARD. MASSACHUSETTS