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DEC-09-I1AA-D

April 1972

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Document:	KG09B
Order Number:	DEC-09-I1AA-D
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Digital Equipment Corporation
Maynard, Massachusetts

PDP-9
Maintenance Manual

KG09B
Memory Extension Control

DEC -09-11 AA- D

KG09B
MEMORY EXTENSION CONTROL
MAINTENANCE MANUAL

DIGITAL

EQUIPMENT

CORPORATION • MAYNARD, MASSACHUSETTS

1st Pri nti ng Ju Iy 1968
2nd Printing Apri I 1969
3rd Pri nti ng October 1969
4th Pri nti ng Apri I 1972

The material in this manual is for informational purposes and is subject to change
without notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL

PDP
FOCAL
COMPUTER LAB

CONTENTS
Page
CHAPTER 1
INTRODUCTION
1• 1

Scope

1-1

1.2

Purpose

1-1

1.3

Rei ated Documents

1-2

1.4

Power Requirements

1-2

1.5

Engineering Drawing References

1-2

1.6

Specifi cations

1-3

1.6. 1

KG09B

1-3

1.6.2

MM09A/B/C

1-3
CHAPTER 2
INSTALLATION AND OPERATION

2. 1

Installati on

2-1

2.2

Interface Cabling

2-1

2.2. 1

Memory Extension Control KG09B

2-1

2.2.2

Memory Modules MM09A/B/C

2-1

2.2.3

Level Terminators

2-2

2.3

Power Wiring

2-2

2.3. 1

Memory Extension Control KG09B

2-2

2.3.2

Memory Modules MM09A/B/C

2-2

2.4

Manual Controls and Indi cators

2-2

2.4. 1

Basi c System Console

2-2

2.4.2

Indi cator Panel

2-3

2.5

Programming Considerations

2-3

CHAPTER 3
PRINCIPLES OF OPERATION
3. 1

Manual Operations

3-1

3.1.1

START Key

3-1

3.1.2

DEPOSIT/EXAMINE Keys

3-2

3. 1.3

READ IN Key

3-2

3. 1.4

I/O RESET Key

3-2

3.2

3-3

lOT Instructions

iii

CONTENTS (Cont)
Page
3.2. 1

SEM (707701)

3-3

3.2.2

EEM (707702)

3-3

3.2.3

LEM (707704)

3-3

3.2.4

EMI R (707742)

3-3

3.2.5

DBR (703344)

3-4

3.3

Address i ng Another Bank

3-4

3.4

Changing The Currently Active Bank

3-5

3.4. 1

JMP I (Op Code 60)

3-5

3.4.2

JMS I (Op Code 10)

3-6

3.4.3

CAL (Op Code 00)

3-6

3.5

Autoindexing

3-7

3.6

Memory Protection Violations

3-8

3.7

PI Breaks

3-8

3.8

API Breaks

3-8

3.9

DCH/RTC Breaks

3-9

3. 10

DMA Breaks

3-10
CHAPTER 4
MAINTENANCE

4. 1

General Maintenance

4-1

4.2

Test Programs

4-1

4.3

Module Replacement

4-1
CHAPTER 5
ENGINEERING DRAWINGS

5. 1

Drawing List

5-1
ILLUSTRATIONS

1-1

Extended Memory Configuration, Front View

1-1

TABLES
1-1

Related Test Programs

1-2

2-1

Extended Memory lOT Instructions

2-3

4-1

Module Complement I KG09B

4-1

4-2

Module Complement I MM09

4-2

CHAPTER 1
INTRODUCTION

1 .1

SCOPE
This manual contains operation and maintenance information for the memory extension options

KG09B and MM09A/B/C of the PDP-9 Digital Data Processor. For complete understanding of the options
and their relation to the basic PDP-9 system, the user should be thoroughly familiar with the contents of
the PDP-9 Maintenance Manual, Document No. F-97.

1 .2

PURPOSE
The KG09B Memory Extension Control allows expansion of the basic 8192-word PDP-9 core

memory to 32,768 words in increments of 8192 words, using the MM09A, MM09B, and MM09C Memory
Modules, respectively.
The KG09B option includes a 2-bit extended program counter (EPC), a 2-bit extended memory
address register (EMA), and associated control logic. The KG09B is installed in the two DEC Type 19430
Mounting Panels located above the basic PDP-9 tape reader/punch, Figure 1-1. The mounting panels
comprise the ME09B chassis which also houses the MP09C Memory Parity and KX09A Memory Protection
options. An indicator panel, suppl ied as part of the ME09B and installed above the marginal check
panel, contains indicator lamps for all three options.

MM09A

MM09B
CONSOLE
TABLE

MM09C

EXTENDED MEMORY
BAY

Figure 1-1

BASIC BAY

Extended Memory Configuration, Front View

1-1

The MM09/A/B/C Memory Modules are installed in a separate DEC Type CAB-31 cabinet
bolted to the basic cabinet. Each memory module is assigned its own memory bank designation as
follows:

1 .3

MC70B

Basic Memory

Bank 0

MM09A

First added 8K module

Bank 1

MM09B

Second added 8 K modu Ie

Bank 2

MM09C

Third added 8K module

Bank 3

RELATED DOCUMENTS
In addition to certain documents listed in Chapter 1 of the PDP-9 Maintenance Manual, the

KG09B and MM09A/B/C options are supported by the test tapes indicated in Table 1-1. Refer to
Chapter 4 for test conditions.

Table 1-1
Related Test Programs

Number

Title

Form

MAINDEC-9A-D lCC-PH

KG09A/B Extended
Memory Contro I Test

Hardware Read-In{HRI) paper tape

MAIN DEC-9A-D 1DA-LA-PH

Extended Memory Test

Hardware Read-In{HRI) paper tape

MAIN DEC-9A-D 1FA-PH

Extended Memory Address Test

Hardware Read-In{HRI) paper tape

1 .4

POWER REQUI REMENTS
The KG09B option draws its + 10, -15V logic power from the basic PDP-9 s 709 Power ~upply.
I

The MM09A/B/C modules take the ir -30V memory power from the 709 supply.

Additionally each module

requires a separate 783 Power Supply for its +10, -15V logic power. These 783 suppl ies are located in
the memory module cabinet.

1 .5

ENGINEERING DRAWING REFERENCES
Throughout this manual all references to option drawings and basic PDP-9 drawings are

abbreviated. Refer to Chapter 5 of the PDP-9 Maintenance Manual for descriptions of drawing number
codes. Chapter 5 of this manual contains a set of option drawings and circuit schematics of all logic
modules.

1-2

1 .6

SPECIFICATIONS

1 .6.1

KG09B

1 .6.2

Heat Dissipation

94 BTU/hr

Power Dissipation

0.030 kW

MM09A/B/C
Cabinet Height

69-1/8 in.

Cabinet Width

32-1/2 in.

Cabinet Depth

27-3/4 in.

Door Clearance (rear)

31 in.

Cabinet Weight

400-800 lb.

Heat Dissipation

421 BTU/hr/8K

Power Dissipation

0.134 kW/8K

1-3

CHAPTER 2
INSTALLATION AND OPERATION

2. 1

IN ST A LLA TI 0 N
PDP-9 systems which include the extended memory options are shipped with the ME09B chassis

and associated panel installed, and the memory module cabinet bolted to the basic system cabinet.

special installation instructions are required. Certain jumpers in the basic cabinet must be removed when
the KG09B and MM09A/B/C options are installed:
EXD (1) B from F36C to F37E (drawing KC27)
EPC03 (1) from F37C to F37K (drawing KC27)
EPC04 (1) from F37M to F38C (drawing KC27)
Indicator wiring from D26C to D25A (drawing ME3)
Indicator wiring from D25A to D25B (drawing ME3)
Indicator wiring from D25B to D25C (drawing ME3)

2.2

INTERFACE CABLING

2.2.1

Memory Extension Control KG09B
Eight flex-print cables carry signals between the KG09B and the CP, I/O bus, and the first

MM09A memory extension module.

Drawing KG6 presents a pictorial view of the cab I ing configuration

and a listing of the cable connectors.
The two memory module cables carry the EMA03-04 bits to the memory control circuits from
the KG09B option, and the MB01, MB03, MB04 bits to the KG09B from the memory module interface.
The connectors are shown on drawing KG3. These are chain-connected from the basic MC70B memory,
Section 2.2.2.
Two cables connect the standard I/O bus to the KG09B, drawing KG4, three cables interconnect the CP/KG09B signals, drawing KG3, and one cable carries the indicator drive power to the
associated indicator panel suppl ied as part of the ME09B hardware.

2.2.2

Memory Modules MM09A/B/C
Each memory module is chain-connected to the previous one by means of six flex-print cables

as shown on drawing MM2. A full complement of three memory modules therefore requires 18 cables,
with MM09C connected to the MC70B as shown.

Not shown on drawing MM2 are the two cables which

connect EMA03-04 and MB01, MB03-04 from MM09A to the KG09B, Section 2.2. 1 •

2-1

2.2.3

Leve I Term i nators
Two G795 Level Terminators are normally furnished and installed in locations D38, E38 of

the basic MC70B memory. These provide proper termination for bits MBOO-17, as shown on drawing
MC9. Installation of extended memory modules requires that the terminators be removed and replaced
by the W033 Flexprint Cable Connectors as listed on drawing MM2. The terminators are then relocated
to D38, E38 of the last memory module in use.

For example, a fully extended, 32K memory system

requires the relocation of the terminators to D38, E38 of MM09A, the last chain-connected module.

2.3

POWER WIRING

2.3. 1

Memory Extension Control KG09B
Drawing ME2 shows the wiring to the power terminals on the ME09B chassis and the associated

indicator panel. The logic power is distributed from the terminals to all modules installed in the chassis
via the marginal check switches on the 1943D mounting panels. Both the fixed +1 OV, -15V and the
marginal checking +1 OV, -15V power come from the matching color-coded terminals as indicated on
drawing IC-9-0-1. The power is controlled from the basic system's 841 A Power Control as explained
in Section 3.7, PDP-9 Maintenance Manual.

2.3.2

Memory Modules MM09A/B/C
Memory module power wiring is shown on drawing MM1.

Primary ac power switched on from

the basic system's 841A unit energizes the 783 Power Supplies and the fans in the MM09 fan housings.
The 783 Power Supplies provide the fixed +10V, -15V logic power to the MM09 memory modules. The
marginal checking +10V, -15V power comes from the basic system's 709 Power Supply, as controlled
by the marginal check panel. The 709 supply also provides the -30V memory stack power to the MM09
modules. The color coding scheme for the power terminals on the fan housings is the same as that shown
for the basic system, drawing IC-9-0-1 •
2.4

MANUAL CONTROLS AND INDICATORS

2.4. 1

Basi c System Console
The basic PDP-9 console contains a prewired EXD mode switch and indicator lamp. The

switch is used in conjunction with the START key to enter or leave the extend mode at the start of a
program.
Thereafter, the programmed lOT instructions control the status of the extend mode regardless
of the EXD switch position. The indicator illuminates when the PDP-9 is in the extend mode, regardless

2-2

of the setting of the EXD switch. In the off (down) position the EXD switch is grounded. The LOCK
position of the maintenance panel switch has no effect on the EXD switch.
The memory extension control logic permits the console DEPOSIT, EXAMINE, READ IN, and
I/O RESET functions to operate within the extended memory system as described for the basic system in
the PDP-9 Maintenance Manual.

2.4.2

Indicator Panel
The ME09B includes an indicator panel installed above the marginal check panel of the

basic PDP-9 system. This panel contains prewired indicator driver transistors and lamps for all three
options assigned to the ME09B chassis, including six lamps for the KG09B: EPC03-04, EMA03-04, EMIR,
and EXD. A" illumination signals come from connector W018-D25 in the ME09B chassis. The KG09B
indicators show the status of the respective fl ip-flops in the control logic.

2.5

PROGRAMMING CONSIDERATIONS
The KG09B logic adds four lOT instructions to the basic PDP-9 repertoire and makes use of

the DBR instruction existing in program interrupt (PI) and automatic priority interrupt (API) service
routines.

Table 2-1 briefly describes these functions.

Table 2-1
Extended Memory lOT Instructions
Octal
Code

Mnemonic

Description

707701

SEM

Skip next instruction if extend mode enabled

707702

EEM

Enter the extend mode.

707704

LEM

Leave the extend mode.

707742

EMIR

Extend mode interrupt restore.

703344

DBR

Debreak and restore.

Execution of the EEM instruction enables the extend mode, and LEM disables the mode. If
the mode is enabled, execution of the SEM instruction increments the PC contents by 1, causing the
program to skip the next sequential instruction.
The PI, API, and DCH/RTC breaks trap to their proper locations in bank 0 regardless of the
extend mode status. In trapping to bank 0, a PI break stores the existing status of the LIN K, extend
mode, memory protect mode, and EPC along with the current program count (PC) in location 00000,

2-3

then disables the mode. An API break transfers program control to the appropriate channel entry location
in bank o. The instruction present in the channel location should be a JMS or a JMS I, which stores
the existing status of the LIN K, etc., in the location referenced by the JMS instruction. With the
extend mode enabled, JMS I permits this storage location to reside in any bank.

For this reason in

particular, the API break does not disable the extend mode.
A DCH break traps to bank 0 for the WC cycle.

During the CA cycle the CA register contains

a 15-bit address of the data entry or retrieval location, in which case bits 03-04 may point at any bank.
An RTC break of course is a one-cycle (WC) break which remains in bank o.
A DMA break does not effect the extend mode operations since its control logic employs a
separate addressing scheme to access any bank.
A memory protect violation from the Memory Protection option KX09A causes an immediate
fetch of a JMS 20 instruction if the PI facility is disabled, or a JMS 0 instruction if the facility is enabled,
with a trap to bank 0 in either case. The current program count and program status information is stored
in location 00020 or 00000, and a monitor program begins from 00021 or 00001. This is true regardless
of extend mode status.
EMIR primes the computer to restore the status of the extend mode and EPC along with the
interrupted program count upon completion of the PI, API, or protect violation breaks.

Like EMIR, DBR

also restores the status of the extend mode and EPe. Additionally it restores the status of the LIN K and
the memory protect mode.

Normally the next to the last instruction in the PI/API/protect violation

routine, DBR or EMIR is followed by a JMP I to the storage location. JMP I performs the actual program
and status restoration. As for all lOT instructions, another interrupt cannot occur until completion of
the subsequent instruction, i. e., completion of JMP I. The following sequence, for example, reestablishes the interrupted conditions upon completion of the PI service routine:

ION
EEM*
DBR or EMIR
JMPI

/REENABLE THE PI FACILITY
/ENABLE EXTEND MODE
/PRIME SYSTEM TO RESTORE PROGRAM
/RESTORE PROGRAM

* If the interrupt occurred in other than bank 0 with extend mode disabled.
While the extend mode is enabled, any operand in the memory system can be indirectly accessed. The effective address in an indirectly addressed location in the current memory bank must be a 15bit address.

Bits 03-04 in the effective address indicate the memory bank that is to be accessed, and

bits 05-17 indicate the operand location in that bank. The EPC indicates the current bank and does
not change.

Because the EPe cannot count in conjunction with the PC, the PC does not increment across

memory bank boundaries (i.e., the location addressed after 17777 is 00000, not 20000).

2-4

To change the currently active bank, the program must include a jump instruction with indirect
address (JMP I, or JMS I if the exit point is to be preserved for subsequent restoration). The extend mode
must be enabled.

Execution of the jump instruction enters bits 03-04 of the effective address into the

EPC to select the new memory bank. Bits 05-17 enter the starting address of the new bank in the PC.
The CAL instruction addresses location 00020 in bank 0 when the extend mode is enabled
and the relative location 00020 in the current memory bank when the mode is disabled.

(A CAL I

instruction in any case is invalid and will be treated like a JMS I20).
The XCT instruction always functions as if the referenced instruction was fetched. Thus an
XCT I reference to a skip instruction in another bank effects a skip of the instruction immediately following XCT I if the skip condition is satisfied.

Similarly, XCT I reference to a JMS or CAL instruction in

another bank effects the appropriate storage of the PC and EPC contents, which represent the address of
the location following XCT I and not the location following the referenced instruction.
Whi Ie the extend mode is disabled, all instructions and operands to be executed must be stored
in the same {current} memory bank. This current bank is addressed by both the PC and the EPC. It is
impossible to enter other banks with the extend mode disabled, except as noted for traps to bank 0 above,
and for traps to autoindex registers 00010-17 in bank O.
Regardless of extend mode status, an instruction which indirectly addresses an autoindex
register traps to bank o. When the extend mode is enabled the 15-bit effective address in the autoindex
location points to any bank. When the extend mode is disabled, the effective address in the autoindex
location points to memory bank o. That is, only 13 bits of the effective address in the autoindex register are accepted by the control logi c. The EMA whi ch was zeroed in order to address the autoindex
location is restored from the EPC at the end of the instruction. To load an autoindex register from any
memory bank other than 0, the extend mode must be enabled. In this case a DAC I instruction references
an effective address location in the current bank (other than 00010-17), and the effective address points
to bank o.

2-5

CHAPTER 3
PRINCIPLES OF OPERATION

This chapter describes the Memory Extension Control option KG09B in terms of its instruction
repertoire and the logic that implements the instructions. The discussions include references to the logic
drawings in Chapter 5 and to pertinent drawings in the basic PDP-9 system.
The MM09A/B/C Memory Module options are exact duplicates of the basic PDP-9 memory
system MC70B. Refer to Section 3.6 of the PDP-9 Maintenance Manual for control logic details.

3. 1

MANUAL OPERATIONS

3.1.1

START Key
The on (up) position of the console EXD switch enables the extend mode in conjunction with

the START key. Regardless of the setting of the switch, a program can be started in any memory bank
by setting the ADDRESS switches and pressing START. The negative SW EXD level goes from the switch
to W034-F37 on drawing KC28, to G796-A06 and W034-B06, drawing KG3.

From B06 the level goes

to the control logic on drawing KG2.
With the console ADDRESS switches set to the program's starting address, the operator depresses
the START key to start the program as described in Section 3.7.4.2, PDP-9 Maintenance Manual. The
START operations involve the extraction of process word 06 from control memory as described.

Process

word 06 contains the processes ADSO, PCI, MBI, SM, and CMA21. The first three processes gate the
15-bit starting address from the ADDRESS switches into the MB and the 13 least-significant bits into the
PC.
ADSO (1), PCI (1) B, and the SW EXD level produce EXD (1) on drawing KG2, which sets
the EXD flip-flop via collector pulling and lights the EXD indicator on the console via W018-D25, also
shown on drawing KG2. The absence of both PCO (1) and EXT (1) allows MB03-04 to appear at the jam
input gates of the EPC and EMA flip-flops.

MB03-04 represent the extended address bits set earlier into

ADDRESS switches 03-04.
ADSO (1) B triggers the 65 ns delay B310-CD24. This delay allows the MB03-04 bits to settle
before the delay output triggers pulse amplifiers C21 and D21 to strobe the EPC and EMA jam input gates.
The EPC will be strobed from pulse amplifier C21 because of ADSO (1) and PCI (1). Thus the extended
address bits get into the flip-flops at some time before the CP's RUN flip-flop sets to permit the issuance
of the first ClK pulse. The time, of course, depends on the REPEAT SPEED switch selection.

3-1

EMA03-04 go from W033-B07 on drawing KG3 to W033-F40 on drawing MC8 for comparision
with the bank selection switches in the basic MC70B memory (bank 0), drawing MC2. The bits are also
chain-connected from F38 of the basic memory to F40 of the next (MM09) memory bank, etc., so that
SM (1) and the ClK pulse activate the appropriate bank as selected by the EMA bits. SM(1) and ClK
thus start the core memory and control memory to fetch the addressed instruction and to extract the
fetch entry process word (21).

3.1.2

DEPOSIT/EXAMINE Keys
The DEPOSIT and EXAMINE operations described in Sections 3.7.4.5 through 3.7.4.8 in

the PDP-9 Maintenance Manual hold true for any memory bank as selected by ADDR SW03-04.

For these

operations neither the PC nor the EPC is involved. ADSO (l) appears in process word 01 to strobe the
MB03-04 bits into the EMA as for the START operations above. The absence of PCI (1) in the process
word precludes the strobing of the EPC fl ip-flops and the production of the EXD (1) level. Thus the
use of the EXD switch is ineffective and the extend mode remains unchanged.

3.1.3

READ IN Key
The READ IN operations described in Section 3.7.4.9 of the PDP-9 Maintenance Manual hold

true for any memory bank as selected by ADDR SW03-04. ADSO (l) appears in process word 01 to strobe
the MB03-04 bits into the EMA as for the START operations above. The absence of PCI (1) in the process
word precludes the strobing of the EPC flip-flops at this time and inhibits the EXD (1) signal. Thus the
use of the EXD switch is ineffective and the extend mode remains unchanged.
During this time the tape reader logic is issuing RD START RQ, which conditions the DCD
input gate to pulse amplifier R603-C18. On the subsequent process word 25 ADSO (1) is removed, so
that ADSO (1) B tri ggers the ampl i fier to strobe the EPC. Thus the EPC contai ns MB03-04, representi ng
the ADDR SW03-04 selection. This is done to accommodate the execution of the last word read into
memory from the tape. As described, the last word is usually a JMP instruction to the starting address
of the program just read into memory. The PCO (1) level at the end of the JMP execution gates the
EPC status into the EMA jam input gates and PCO (1) B strobes the gates. In this manner the program
continues in the current memory bank.

3.1.4

I/O RESET Key
The I/O RESET key clears all flip-flops in the KG09B logic in addition to the basic system

flip-flops as explained in Section 3.7.4.10, PDP-9 Maintenance Manual.

3-2

3.2

lOT INSTRUCTIONS

3.2.1

SEM (707701)
The SEM instruction (skip on extend mode enabled) is decoded in the I/O control logic, draw-

ing K03, to produce the IOT7701 pulse at the device selector Wl03-C014, drawing KG2. If the extend
mode is enabled, IOT7701 sets the EX SKIP flip-flop.

EX SKIP (1) generates SKIP RQ at Rll1-016U

which goes back to the I/O control logic via the I/O bus.
SKIP flip-flop on drawing KC14.

SKIP RQ results in 10 SKIP which sets the

See Section 3.8.1 .6, POP-9 Maintenance Manual.

The 10 SYNC level resets the EX SKIP flip-flop. 10 SYNC is obtained on each computer
ClK POS pulse where no AM request has been received, drawing K03 (2), and where no lOT instruction
is in progress, drawing K03 (1).

3.2.2

EEM (707702)
The EEM instruction (enter the extend mode) is decoded in the I/O control logic, drawing

K03, to produce the IOT7702 pulse at the device selector Wl03-C014, drawing KG2. IOT7702 sets
the EXO fl ip-flop to enable the extend mode.

3.2.3

lEM (707704)
The lEM instruction (leave the extend mode) is decoded in the I/O control logic, drawing

KD3, to produce the IOT7704 pulse at the device selector Wl03-CD14, drawing KG2. IOT7704 resets
the EXD fl ip-flop to disable the extend mode.

3.2.4

EMI R (707742)
The EMIR instruction (extend mode interrupt restore) is included to provide compatibility from

the PDP-7 to the PDP-9. Its use is described in the PDP-7 User Handbook.

EMIR is decoded in the I/O

control logic, drawing KD3, to produce the IOT7703 pulse at the device selector W103-CD14, drawing
KG2. Additionally, bit 12 in the instruction word produces the SDOO level which conditions the DCD
set gate to the EMIR flip-flop. The IOT7702 pulse therefore sets the EXD and EMIR flip-flops simultaneously.
EMIR always precedes a JMP I instruction to the program storage location upon completion of
a PI or API break. During the JMP I fetch cycle, the IR04 (1) bit is detected on drawing KC12 to cause
the computer to go into a defer cycle. The defer cycle fetches the effective address word previously
stored by the PI or API break entry processes, now indirectly addressed by the JMP I instruction. The
effective address word contains the interrupted program count in bits 05-17 plus the interrupted LINK,
extend mode, memory protect mode, and EPC status in bits 00-04.

3-3

DEI (1) in the defer cycle entry process word (31) sets the EXCY flip-flop, conditioned by
EXD (1) and IR04 (1). The CLR pulse which follows process word 31 gates the effective address word
into the MB.
DEI (1) also resets IR04 so that the JMP op code produces REP on drawing KC12, causing the
computer to enter the JMP execute cycle. The JMP execute process word 74 contains MBa, PCI, DONE,
LI, CaNT, and CMA10. MBa (1) and PCI (1) place the effective address word (bits 05-17) in the pc.
At the same time PCI (1) B samples the original extend mode status bit MBOl (0) B in conjunction with
EXCY (1) and EMIR (1) at R111-D15H. If MB01 was at 0 when stored, then EXD (0) ensues to reset the
EXD fl ip-flop via collector pull ing. If MB01 was a 1, then the EXD fl ip-flop remains set.
EXCY (1) and PCI (1) B trigger pulse amplifier W612-C21 to strobe the EPC jam input gates.
The MB03-04 bits are thus restored to the EPC.
The main program count and the extend mode and EPC status are now fully restored.

Process

word 10 (BGN) prepares the computer for the resumption of the main program by gating the PC contents
into the MB with processes PCO and MBI. PCO (1) B strobes the EMA jam input gates which now receive
the EPC bits from B169 AND/NOR gates. When the first instruction has been fetched, IRI (1) in the
fetch cycle process word 12 resets the EMIR and EXCY fl ip-flops.

3.2.5

D BR (703344)
The DBR instruction (debreak and restore) which always precedes a JMP I instruction, is decoded

i'n the I/O control logic, drawing KD3, to produce the DBR level as described in Section 3.8.1 .7,
PDP-9 Maintenance Manual. The DBR pulse occurring during process 74 of JMP I causes restoration of
the interrupted LIN K, memory protect mode, and PC status as described. Additionally, DBR samples the
interrupted extend mode status bit on drawing KG2 as reflected in MB01 of the effective address word.

If 0, DBRAMBOl (0) produce EXD (0) at Rll1-D17 to hold the EXD flip-flop in the reset state. If 1,
DBRAMBOl (1) produce EXD (l) and EXCY (1) at R002-C25 to set the respective fl ip-flops. Thereafter,
these fl ip-flops act to restore the EPC as for EMIR.

3.3

ADDRESSING ANOTHER BANK
With the extend mode enabled, all memory reference instructions in a currently active bank

can indirectly address a location in any other bank.
During process word 12 of the instruction fetch cycle the instruction word containing the
indirect address is placed in the MB and the op code portion is placed in the IR. The IRI (1) process
which gates the op code into the IR also resets the EXCY fl ip-flop, drawing KG2. IR04 (1), indicating
an indirect address, conditions the DCD set gate to the flip-flop in conjunction with EXD (l).

3-4

Process word 24 detects IR04 (1) to force the computer into a defer cycle. At the start of
the defer cycle the DEI (1) process sets EXCY (1) and resets IR04. The core memory read half-cycle
reads out the effective address word, and other processes place it in the MB. MB03-04 designate the
memory bank to be accessed. These bits are presented to the EPC and EMA jam input gates via the B169
AND/NOR gates in the absence of the PCO (1) and EXT (1) levels.
MEM STROBE occurs in core memory at the same time that STROBE SAR and STROBE SAL
read out the effective address word into the MB. MEM STROBE, DEI(l), and EXCY(l) produce EMA
STROBE, which strobes the MB03-04 bits into the EMA. The EPC retains the current bank designation
because of the absence of a strobing pulse at this time.
Process word (24) determines if the computer shall go into an execute cycle or into the special
lAO cycle, as indi cated by the op code in the IR. The execute or the lAO cycle fetches the operand
from the memory bank designated by the EMA, and the instruction is executed. In either case, the
BGN process word (10) at the end of the cycle transfers the next sequential instruction address from the
PC to the MB for the next fetch cycle. PCO (1) of the BGN word also gates the EPC bits into the EMA.
Therefore, the program returns to the current bank from whi ch the indirect address word was originally
fetched.
3.4

CHANGING THE CURRENTLY ACTIVE BANK

3.4. 1

JMP I (Op Code 60)
With the extend mode enabled, a JMP I instruction fetched from the currently active bank

may change the EPC contents and consequently activate another bank.

During the JMP I fetch cycle

IR04 (1) is detected on drawing KC12 to cause the computer to go into a defer cycle. The defer cycle
fetches the effective address word addressed by JMP I. The effective address word contains a 15-bit
address, with MB03-04 designating the new memory bank to be accessed and MB05-17 containing the
starting address in that bank.
DEI (1) in the defer entry process word 31 sets the EXCY fl ip-flop, conditioned by EX D (1)
and IR04 (1), while other processes gate the effective address word into the MB.

DEI (1) also resets

IR04 (1) so that the JMP op code produces REP on drawing KC12, causing the computer to enter the
JMP execute cycle.
The JMP execute process word 74 contains MBO, PCI, DONE, tI, CONT, and CMA10.
MBO (1) and PCI (1) place the effective address bits MB05-17 in the PC. At the same time PCI (1) B
and EXCY (1) trigger pulse ampl ifier W612-C21 to strobe the MB03-04 bits into the EPC.
Processes PCO (1) and MBI (1) in process word 10 (BGN) gate the PC contents into the MB
for the start of the next fetch cycle. PCO (1) B also strobes the EMA jam input gates which now receive the new EPC information from the B169 AND/NOR gates. Thus the next fetch cycle takes its
3-5

instruction word from the newly activated memory bank at the address jammed into the MA from the MB.
When the instruction is fetched, IRI (1) in the fetch cycle process word 12 resets the EXCY flip-flop.
Thereafter the EPC remains set to the new bank designation as long as the program continues in that bank.
3.4.2

JMS I (Op Code 10)
With the extend mode enabled, a JMS I instruction fetched from the currently active bank

may change the EPC contents and consequently activate another bank.

During the JMS I fetch cycle,

IR04 (1) is detected to cause the computer to go into a defer cycle. The defer cycle fetches the effective
address word addressed by JMS I. The effective address word contains a 15-bit address, with MB03-04
designating the new memory bank to be accessed, and MB05-17 containing the address in that bank in
which the current program count and status information is to be stored. A later JMP I to this address
returns the program sequence to the currently active bank.
DEI (1) of the defer entry process word 31 sets the EXCY fl ip-flop, drawing KG2, whi Ie
other processes gate the effective address word into the MB. DEI (1) also resets IR04 so that TI (1) in
the next process word (24) detects JMS to force the computer into the lAO cycle.

During the defer

cycle, MEM STROBE (B), DEI (1), and EXCY (1) produce EMA STROBE which jams the contents of
MB03 and MB04 into EMA03 and EMA04, respectively.
The lAO entry process word 32 gates the current program count and program status information
into the AR as the core memory read half-cycle starts.

During read the contents of the addressed

location are ignored (lost), the MB contents are incremented by 1, then placed in the PC by a 1 .... PCI
signal evolved from process word 23.

On drawing KG2 EXCY (1) and 1 .... PCI strobe the MB03-04 bits

into the EPC.
During write, the contents of the AR, containing the disrupted program count and status
information, are stored in the addressed location by process word 62. The next process word is BGN (10),
which gates the new address in the PC into the MB, while PCO (1) B and RUN (1) strobe the new EPC
contents into the EMA. Thus the next fetch cycle addresses the newly-activated memory bank and the
program continues from there.

3.4.3

CAL (Op Code 00)
With the extend mode enabled, a CAL instruction in the currently active bank traps to

location 00020 in bank 0, storing the current program count and status information at that location and
taking the next instruction from location 00021.

A later DBR or EMIR and JMP I to 00020 returns the

program sequence to the currently active bank.
During the third process word (24) of the CAL fetch cycle, CAL (1), TI (1), and EXD (1) are
all present to produce TI·EXD·CAl at Rll1-D15N, drawing KG2. This level clears the EMA flip-flops.
At ClK time a short time later, address 00020 is placed in the MB.

3-6

The decoded CAL (1) signal leads the computer into a subsequent lAO cycle. The lAO entry
process word 32 gates the current pro'gram count and status information into the AR as the lAO core
memory read half-cycle starts.

During read the contents of location 00020 are ignored (lost), the MB

contents (address 00020) are incremented by 1, then placed in the PC by a 1 -. PCI signal evolved
from process word 23. On drawing KG2 this 1 -. PCI signal in NANDed with CAL (1) and EXD (1)
to clear the EPC flip-flops.
During memory write, the contents of the AR, containing the disrupted program count and
status information, are stored in location 00020 by process word 60.

The next process word is BGN (10)

which gates address 00021 from the PC into the MB, with EMA and EPC remaining reset to address bank o.
The new program sequence continues from there.
With the extend mode disabled the operations are basically the same except the EMA and
EPC are not cleared; the CAL instruction references location 00020 in the current memory bank.

3.5

AUTOINDEXING
An instruction word in the current memory bank which indirectly addresses an autoindex

During the third process word

(24) of the fetch cycle, TI (1) detects IR04 (1) to force the computer into a defer cycle. At the same
time, TI (1) and IR04 (1) detect bits MB05-17 to set the AUT INX flip-flop on drawing KC14. AUT
INX (1) immediately clears the EMA flip-flop, drawing KG2. Thus the defer cycle will address bank o.
During defer, the core memory read half-cycle reads out the effective address word from the
autoindex location, the effective address word is incremented by 1, then placed in the MB. The write
half-cycle writes the incremented address back into the autoindex location. The incremented address
also remains in the MB for the upcoming execute or lAO cycle.
During defer, if the extend mode is enabled, EMA STROBE occurs at MEM STROBE time to
strobe the effective address bits MB03-04 into the EMA. If the extend mode is disabled, the EMA
flip-flops remain cleared. In this case the upcoming execute or lAO cycle remains in bank o. The
EPC retains the current bank designation in either case because of the absence of a strobing pulse at
this time.
The subsequent process word in the defer cycle (24, 70, or 74) determines if the computer
shall go into an execute cycle or into the special lAO cycle as indicated by the op code in the IR.
TI (1)/\ IR04 (0) resets AUT INX during process word 24 or 70, and PCI (1) resets it during process word
74. The execute or lAO cycle fetches the operand from the bank designated by the EMA, and the
instruction is executed. The BGN process word (10) at the end of the cycle transfers the next sequential
instruction address from the PC to the MB for the next fetch cycle.

PCO (1) of the BGN word also gates

the EPC bits into the EMA, so that the program returns to the currently active bank for the instruction fetch.

3-7

3.6

MEMORY PROTECTION VIOLATIONS
A protect violation forces the computer into a fetch cycle to fetch a JMS 20 or JMS 0

instruction, depending on the on/off status of the PI facility.

During the JMS fetch, TI (1) of process

word 24 turns on a PVO EMA signal in conjunction with a PV level in the KX09A option.

PVO EMA

clears the EMA flip-flops so that the subsequent lAO cycle addresses bank 0 to store the current program
count and program status' information in location 00020 or 00000.
The 1 .... PCI signal in process word 23 of the lAO cycle produces PVO EPC in the KX09A
optiOn.

PVO EPC occurs as address 00020 or 00000 is incremented by 1 and placed in the PC for the

next computer fetch cycle. This signal clears the EPC so that the computer continues in bank 0 with a
monitor program starting from location 00021 or 00001.

3.7

Refer to the KX09A manual for details.

PI BREAKS
When a PI break is entered, the break entry word (11) places address 00000 in the MB, clears

the IR for a pseudo CAL op code, and leads the computer into an lAO cycle, as described in Section
3.8.1.7, PDP-9 Maintenance Manual.
EXT (1) of the break entry process word sets the BK flip-flop, drawing KD3 (2), gates 10
ADDR 03, 10 ADDR 04 onto the EPC, EMA jam input gates, and strobes the gates to clear the EMA
(00 from 10 ADDR 03-04).

The EPC retains the current bank designation. The lAO cycle will address

bank 0 as designated by the cleared EMA.
BK (1) sets the PROG SYNC flip-flop. This places a negative PROG SYNC (1) B level at
the DCD input gate to pulse amplifier R603-C18, drawing KG2. The lAO cycle performs the pseudo
CAL execution, storing the PC contents and program status information in location 00000 in bank o.
An 10 CLR pulse, 500 ns after lAO entry, resets PROG SY, PROG SYNC, BK, and PIE,
drawing KD3 (2). Reset PROG SYNC triggers the pulse amplifier R603-C18 to produce the lOT PWR
CLR (B) V PICY pulse. This pulse clears (disables) the extend mode control flip-flops and the EPC, so
that the program continues from 00001 in bank 0 at PCO (1) time of the BGN process word in the lAO
cycle.
At the conclusion of the PI break, an EMIR or DBR and JMP I sequence retrieves the stored
program count and status information for a return to the current bank.

3.8

API BREAKS
When an API break is entered, the break entry process word (11) places the API channel

address in the MB, clears the IR, and leads the computer into an XCT cycle, as described in the API
option manual.

3-8

EXT (l)gatesIOADDR 03andl0 ADDR04 onto the EPCand EMAjam input gates, and strobes
the gates to clear the EMA (00 for 10 ADDR 03-04). The EPC retains the current bank designation.
The XCT cycle will address bank 0 as designated by the cleared EMA.
The XCT cycle fetches the instruction located in the API channel address. This instruction
is either a JMS or a JMS I. For JMS the computer goes into an execute cycle to store the current
program and status information at the addressed location in bank O.
At DONE (1) time in the JMS execution, DONE (1) and 0 EPC LATCH generate PVO EPC
which clears the EPC and generates 0'-+ EPC UNLATCH. Thus at the BGN process word, PCO (1) B
strobes the EPC bits into the EMA, so that the API service routine continues in bank 0 from the next
sequential location after the JMS storage. 0 -+ EPC UNLATCH disables PVO EPC.
These events occur regardless of the extend mode status. If the API channel location contains a JMS I instruction, the extend mode must be enabled so that the effective address obtained from
bank 0 during the defer cycle can point to a storage location in any bank. Processor word (23) which
produced 1-+ PCI will generate the 0 -+ EPC UNLATCH pulse which loads MB03 and 04 into EPC.
0-+ EPC UNLATCH prevents PVO EPC from being generated at DONE (1) time. API service will now
continue in the bank designated by the JMS I instruction. At the conclusion of the API break, JMP I
retrieves the stored program count and status information for a return to the current bank.

3.9

DCH/RTC BREAKS
When a DCH/RTC break is entered, the break entry word (11) places the device's WC re-

gister address in the MB, clears the IR, and leads the computer into a WC cycle, as described in
Section 3.8.2, PDP-9 Maintenance Manual.
EXT (1) of the break entry word gates 10 ADDR 03, 10 ADDR 04 (normally, both in the 0
state) onto the EPC, EMA jam input gates and strobes the gates to load the EMA flip-flops. The EPC
retains the current bank designation. The WC cycle will address the bank designated by the EMA
(bank 0).
The WC cycle fetches the word count in the WC register, increments both the word count
and its reference address, checks for word count overflow, and steps the break counter to 10 (BKO = 1,
BK 1 = 0). The incremented address is stored in the AR and represents the address of the next sequential
location in memory bank O. This location is the current address register (CA) which is initialized to
the address -1 of the data transfer location. The CA register is referenced during the CA cycle to
increment its contents and to place them in the MB.
An RTC break, of course, ends with the WC cycle, in which case the last process word is
BGN (10). PCO (1) B from BGN strobes the current bank designation into the EMA from the EPC, and
the program thus returns to the currently active bank for the next fetch cycle.

3-9

For DCH breaks, the CA cycle steps the break counter to 11 (BKO = 1, BK1 = 1).

drawing KC10 (1), BK1 (1) Band ARI (1) of prdcess word 13 produce BK CA as the device data is
transferred from the I/O bus to the AR (for input data operations), or as Os are placed in the AR (for
output data operations).
BK CA occurs while the CA register contents are in the MB. BK CA strobes MB03-04 into
the EMA so that the subsequent input/output data cycle accesses the designated memory bank.
The last process word in the data cycle(s) is BGN, during which PCO (1) B strobes the EMA
with the EPC bits to return the program to the currently active bank.

3.10

DMA BREAKS
A DMA break does make use of the memory extension control. When the DMA channel steals

a memory cycle, the control logic in the DMA multiplexer option issues its own AM EMA bits to each
memory bank for bank selection in conjunction with the MODE flip-flop in the memory control circuits.
Refer to the DM09A option manual for details.

3-10

CHAPTER 4
MAINTENANCE

4.1

GENERAL MAINTENANCE
The general maintenance practices described in the PDP-9 Maintenance Manual also apply

to the KG09B and MM09A/B/C options.

4.2

TEST PROGRAMS
The KG09B and MM09A/B/C options can be tested using MAINDEC-9A-D1CC-PH, MAIN-

DEC-9A-D1 FA-PH, and MAINDEC-9A-Dl DA-LA-PH respectively under marginal check conditions of
+10 ±4V and -15 ±2.5V. Refer to the associated program documents.

4.3

MODULE REPLACEMENT
Tables 4-1 and 4-2 list the full complement of logic modules comprising the KG09B and one

MM09 option respectively. The spare modules kit SP09A offered by DEC as a replacement stock level
for the entire PDP-9 system provides at least one spare o'f all module types used in the KG09B and MM09
options. It is recommended that the user maintain this minimum stock level to avoid equipment downtime due to repair of faulty modules.
Table 4-1
Module Complement, KG09B
DEC Type

Module Type

Quantity

B169

AN D/NOR Gate

B213

Dual FI ip-Flop

B310

Delay

G795

Leve I Term i nator

G796

Leve I Term i nator

R002

Diode Network

R111

NAND/NOR Gate

R603

Pulse Amplifier

5107

Inverter

5205

Dual FI ip-Flop

W005

Clamped Load

W103

Device Selector

W612

Pulse Amplifier

4-1

Table 4-2
Module Complement I MM09
Module Type

DEC Type

Quantity

Bl04

Inverter

Bl05

Inverter

B169

AN D/NOR Gate

B213

Dual FI ip-Flop

B310

Delay

B360

Delay

B602

Pulse Amplifier

G008

Master SI ice Control

G009

Sense Amplifier

G010

Sense Amplifier Selector

G219

Address 5e Iector

G622

Resistor Board

G795

Level Terminator

G796

Level Terminator

2**

G804

Power Control

G805

Power Regulator

R002

Diode Network

Rl11

NAND/NOR Gate

5107

Inverter

W005

Clamped Load

W612

Pulse Amplifier

*Including 2 for last MM09 in use.
**If parity option not installed.

4-2

CHAPTER 5
ENGINEERING DRAWINGS

This chapter contains a set of KG09B, MM09A/B/C, and ME09B engineering drawings along
with circuit schematics of all logic modules used in the KG09B.

DEC engineering drawings are encoded

as to drawing type, major assembly, and series. These drawing number codes are explained in Chapter 5
of the PDP-9 Maintenance Manual.

5.1

DRAWING LIST
Below is a I ist of all drawings inc luded in this chapter. Other related drawings are included

in the Chapter 5 drawings of the PDP-9 Maintenance Manual, as part of the prewired, basic system.
Memory Extension Control KG09B
Title

Drawing Number

Revision

Page

B-C S-B 169-0-1

AN D/NOR Gate B169, Circuit Schematic

5-3

B-CS-B213-0-1

Flip-Flop B213, Circuit Schematic

5-3

B-C S-B31 0-0-1

Delay B310, Circuit Schematic

5-4

B-C S-G795-0-1

Level Terminator G795, Circuit Schematic

5-4

B-C S-R002-0-1

Diode Network R002, Circuit Schematic

5-5

B-C S-R 111-0-1

NAND/NOR Gate Rl11, Circuit Schematic

5-5

B-CS-R603

Pulse Amplifier R603, Circuit Schematic

5-6

B-CS-S107-0-1

Inverter S107, Circuit Schematic

5-6

B-C S-S205-0-1

Flip-Flop S205, Circuit Schematic

5-7

B-C S-W005-0-1

Clamped Load W005, Circuit Schematic

5-7

C-CS-W103-0-1

Device Selector Wl03, Circuit Schematic

5-8

B-C S-W612-0-1

Pulse Amplifier W612, Circuit Schematic

5-9

D-BD-KG09-B-1

Extended Memory Control, Block Diagram

D-BS- KG09-B-2

Extended Memory Control, Block Schematic

D-IC- KG09-B-3

Cable Connections

5-15

D-IC-KG09-B-4

10 Interface

5-17

D-MU- KG09-B-5

Module Utilization

5-19

A-PL- KG09-B-5

Parts List

5-21

D-IC- KG09-B-6

Cable Diagram

5-11

5-1

5-13

5-23

Extended Memory Modules MM09A/MM09B/MM09C
Drawing Number

Title

Revision

Page

B-C S-783-0-1

Power Supply 783, Circuit Schematic

5-25

C -C S- G 796-0-1

Level Terminator G796, Circuit Schematic

5-26

C-UA-MM09-A-0

Unit Assembly

5-27

A-PL-MM09-A-0

Parts List

5-28

D-IC-MM09-A-l

Power Wiring

5-29

D-IC-MM09-A-2

Cable Diagram

C-UA-MM09-B-0

Unit Assembly

5-33

A-PL-MM09-B-0

Parts List

5-34

C-UA-MM09-C-0

Unit Assembly

5-35

A-PL-MM09-C-0

Parts List

5-36

MC70-B-0
through
MC70-B-20

5-31

Memory Module Logic Drawings
(included in Chapter 5, PDP-9
Maintenance Manual)
Memory Parity, Protection, and Extension Chassis ME09B

D-UA-ME09-B-0

Unit Assembly

5-37

A-PL-ME09-B-0

Parts List

5-39

A-WL-ME09-B-l

Wiring List

5-40

D-IC-ME09-B-2

Power Wiring

A-CP-ME09-B-3

External Components List (Sheet 1)

5-43

A-CP-ME09-B-3

External Components List (Sheet 2)

5-44

D-AD-7005684-0-0

Assembly Drawing

5-45

A-PL-7005684-0-0

Assembly Parts List

5-47

5-41

5-2

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B-CS-B213-0-1 Flip-Flop B213, Circuit Schematic

5-3

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B-CS-B310-0-1

Delay B310, Circuit Schematic

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B-CS-G795-0-1 Level Termi nator G795,
Ci rcui t Schemati c

5-4

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B-CS-Rlll-O-l NAND/NOR Gate Rlll,
Circuit Schemati c

5-5

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~
...

3,g~1I1I2

...

;; F'330

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.. P11

~,~~ ~0I2
5'"

l1'li.

~ '8'-\&2

.....

1111

b\OOO

R24
47

EC2894-28

D~2

:::::: ~;O

~ ,0-882

011

• 112

2,111

D":I

Oil
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02

DEC 2894-2B

~~3

2,.27

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•

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~ ~ f- O~

DEC2894-2rB-+~_-+

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1122
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7,!IOO
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I

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049

UN..ESS OTl£RWISE INDICATED-

~~~Sci~~=SANE 1:::~bO'll.
OlooES ARE 0-884
TRANSISTORS ARE DEC 3839-C

8-CS-R603 Pulse Ampl ifier R603,
Circuit Schematic

r--------,
:

EXt:~5LE

r---------~~--------~~--------~~----------._----------~---------+~----_4----------__oA.IOV(Al
I
RI
R2
R3
114
R7
I
RII
R8

100,000

100.000

100,000

I~~~~~-J

r------,

r-----r_--~._----r_--~~----r_--~~----+_----._----_+----._--_4_+r_~~--~~~~2---~I-oCGND

0-882

:
1

09
I
D-6621
1
DIO
I
0-662 :

DII
~~---+--~~-----+--~-;-----+~~~r_--~r--+--;----;--~~1;~=±~~~--+-t6

0-662 1

:
I

Rill
1,1100

I
:

: STRATE

I
I

- - 71 ...._-3-Y--t-O B -IllY

,......----+-----._----+-----._----+----,......----;----+---~---_+_---H--._-_"+I

1122:
15,000

____ JI

UNLESS OTHERWISE INDICATE D:
RESISTORS ARE 1/4Wjll'Mo
DIODES ARE 0 -664
TRANSISTORS ARE DEC 3839B
PRINTED CIRCUIT REV. FOR
DGL BOARD IS SIA
PARTS LIST A-PL-SI07-0-0

8-CS-S 107 -0-1 Inverter S 107, Circuit Schemati c

5-6

L. ______ J

No-__~.~_10_57_~4~~0~_9___________________________-rA~_10_61-,

r----------.....-----+--t------+---+--.......

---------------4p---------t---t-----+-------o~A .. IOV(A

~L. R 4
"03

~'D8

100POO

---

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100,000

....

DI9

R9
RII
15,000 15,000

1[;.4
...

~35
p

RI8
3,000

R 22
R24
15,000 15,000

RI9
15,000

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022

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100

•

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pj7

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100,000

RI3
RI4
RI5
RI7
15,000 15,000 15,000 3,000

RIO
RI2
115,000 I~

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RESISTORS ARE 1/4W; 5 %
CAPACITORS ARE MMFD
DIODES ARE D- 664
TRANSISTORS ARE DEC 3639C

,...

R20

~~D27'~030 ,100,000

....

.
R8
R7
3,000 15,000

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~U R 16

t---OK

R25
1,500

___

....
D46
...

PARTS L.IST A-PL-S205-0-0

8-CS-S205-0-1 Flip-Flop S205, Circuit Schematic

.....-------~~-~~-__oB-15v

r-------,~---~-----~t------t-----~----~---~~-----

023
0-862
I
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I
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I
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I
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I
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I

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IL STRATE
_____ ...JI

UNL.ESS OTHERWISE INDICATED:
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DIODES ARE D-884

8-CS-W005-0-1 Clamped Load W005,
Circuit Schematic

5-7

CII
.01
MFO

ClNO

~AA.

I Ov (A)
AS - 15

RI
15,000

R2
IOOpoQ

R3
R5
3,000 15,000

R6
R8
100,000 1,500

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0-662

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R22

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051 "

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56

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BF~
BH~

R4
15,000

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100,000

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CJJ
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BP~

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3,000

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15,000

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IOPOO

!P
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66

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0~9

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057
4 ~0-662
056
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=-.01
MFO

(

AC,BC GNO
UNLESS

OTHERWISE

INDICATED:

TRANSISTORS ARE DEC 3639
RESISTORS ARE 1/4 W, 5%
CAPACITORS ARE MMFD
DIODES ARE 0-664

C-CS-W103-0-1 Device Selector W103,
Ci rcuit Schemati c

'''111

IfHlllnN 1-0-319M

1~13~11

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT It •• BY DIGITAL EQUIPMENT CORPORATION

M GND

C GND

r---------------------------~----~~------._~--------------------------~--·--~~~------OA

+IOV

R3
470

R6
100.000

R23
1,500

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T-2021
T 2 f l 7 0L

,,-

RI
1,500

UNLESS OTHERWISE INDICATED:
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DIODES ARE 0664
TRANSISTORS ARE DEC3639B
PARTS LIST A-PL-W812-0-0
COllOQ

~R-+-+--+-~
iii

~ I-S+-t;,-,I=hi:=-:"'i

+ I!

R25
1,500

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1------------------1
TRANSISTOR & DIODE CONVERSION CHART

MO-OO-O
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~~~~~~{!j~W!jjjqINWJC=H===+=====lCORPORATION

B-CS-W612-0-1 Pulse Amplifier W612,
Circuit Schematic

5-9

TITLE

PULSE AMPLIFIER W612
SIZE

CODE

NUMBER

B CS W612-0-1

10 AOOR 03
10 PlDDR 04

lOPI
lOPZ
10P4

BUS

lNTERFACE:

..,

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D5 2.

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Extended Memory Control,
Block Di agram

5-11

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5-13

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D-IC-KG09-B-3

Cable Connections
5-15

D
W8S¢

W85~

W&5¢

W85¢

C001

C002

C003

CD~4

IO BUS ¢¢

IO SYNC

rORUN(I)

WRITE RQ

IO BUS ¢I

rop

API'" EN OUT

INC MB

IO BUS ¢2

lOP 2

IO OFLO

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IO AOOR ¢;3

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IO BUS 12

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API ;3 RQ

IO BUS 13

OS 4

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IO BUS 14

OS 5

IO AOOR

API 3 EN IN

! 0 AOOR

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API 2

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IO BUS 16

SO 0

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IO BUS 17

IO ADDR

DCH

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NOTE

ALL

W85~'S

HAVE

PINS

C,F,J, L,N,R,U

GROUNDED.

*" THIS IS SPECIALLY WIRED FOR KG09B IN KOO9A
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D-IC-KG09-B-4

5-17

10 Interface

3 ~ 4

5 I 6

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DENOTES MODULE HEINS, USED IN MP,B9-A
DENOTES MODULE BE I NG usm IN KXS9-A

D-MU-KG09-B-5

Module Utilization

5-19

PARTS LIST
PART
NO.

DRWG. NO.

DIGITAL EQUIPMENT CORPORATION
MAYNARC,MA8SACHU8ETT8

NO.
REQD.

DESCRIPTION
ITEM -

STOCK SIZE-CAT. NO. -

WOOS CLAMPED LOAD

R111 DIODE GATE

W103 DEVICE SELECTOR

R002 DIODE CLUSTER

S205 DUAL FLIP-FLOP

R603 PULSE AMP.

B213 FLIP-FLOP

W612 PULSE AMP.

B169 INVERTER

B'BJOO~L.AY

S107 INVERTER

G795 CLAMPED CABLE CONN

LlNE

A-PL-K G09-B-5

5-21

Parts Li st

MFG.

DEC.
STOCK NO.

D
A1Bl c I DIE I F I H I

JIHIFIE,D,CIB, ,..,
I
I
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LOC

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TYPE

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GT-l6

ME0qe

H35

G79G

KC~9A

CONT

BQ5

G7%

MEQc:re

J35

G7"16

KC~9A

CONT

5¢6

W~-j4

MEQ)98

f37

Wa"34

KC~9A

CONT

CD 1,2

WB5~

ME(P98 A829,30 W85¢

KDlti9A

10 BuS

KD~9A

10 BUS

C[l3,4

W85Q'l

MErtl'lB AB31,32 W85rtJ

Aill 3

G795

ME~qB

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WcP33

MMQl9A MB Q-8

B(]l7

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W~33

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IN tl Icl'lro'f:
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D25

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MC7~B

ME.M

MEM
MMQjC!A

FROM

COMME.NT

/'11 [¥'qe

-CI2'34

CABL.E.5 "4,5
ARE. STD 10
BUS CABLES
(36
PAIRS)

lJo1fn H

D38

CABLES -4,S,8
NE.E.D NOT BE.
TAPED WITH

IND.
PANEL

POL.yr.sn:.R

25 ,

CP
KCQjCjA

FOAM

UNLESS OTHERWISE DENOTED ALL CABLES ARE 19 COND F"LEXPR.INT I
WIDE ADHESIVE. HACXEDPOLYESTER FOAM STRIPS (DEC PAR-JlI2-~58~7)
AlJI-IESED TO ONE SIDE OF EACH FOR SEPARATION. CABLES TO BE
BUNDLED IN ZIPPER TUBING (DEC PARi"'12- (])5808).

H35

J35

F37

10
KD'1i9A

B
- I AB :9/30
::::::r::::: AB 31,32

B
FRONT EXTENDED
MEMORY BAY

FRONT

BASIC

BAY

R£AR

BASIC BA'f

D-IC-KG09-B-6

Cable Diagram

5-23

1'110*
...-_ _---..;,.R;,;:E..:;.O_------<>+IOV

+
-

CZ
1150,000MFO
ZOVDC

RI
III, II ..

YEL •

25W

COM
YEL

INPUT
IIIIV AC
801'\.)

CI
110,000 MI'O
ZOVDC
r:'BLUE·

--.--=-___I-----.....:B-L-U-------...

... ,_"'---........t-_ _
L.: _____ -'
NOTE:
IN ORDER TO KEEP OUTPUT VOLTAGE WITHIN
THII'OLLOWING LIMITe:
+ 10V: +9.11 TO +IIV
-III V: -14.IITO-I8V
THE LOADING SHOULD IE WITHIN THI! FOLLOWING LIMITS:
+IOV 0 TO 7.0 AMPS
-IIIV 1.0 TO 1.0 AMPS
+IOV 0 TO 7.11 AMPS
-IIIV 1.0 TO 8.11 AMPS

* HEYMAN MFG. CO. TAl TERMINALS

B-CS-783-0-1

Power Supply 783,
Circuit Schematic

5-25

L.--o....... _III V

Tl"'ilS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THEJ
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1•• 1 By DIGITAL EQUIPMENT CORPORATION

T
~

r----+--~----~~~--~--~----~--~--~--~----~--~--~--~~--_+--~----~~~--_+--~----+_~~--_+--~----+-~~--_+------,-------o_15V

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RI2

RII

RI4

RI9

RII

RI6

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~'""""""""
~1--1
~I-~~Oll
~ r.013
~~019
'021
~~023
"025
~~028
~~03D
~ '032
~ '038
110

~ .. 012

010

R5
1,500

~1I-014

~1I-020

R7
47

~ 110022

~ 110024

~ 110026

RIO
1,500

~~031

n029

RIS
1,500

RI7

R20
1,500

...,

r;C3

r:
(

)

~ ~ 0662

017
~ .. 0662

036
0662

~ ~:62
.. g~~2

~r-C2

;: C4

;: CS

~~ g:!2

~~g::2

)
L

oS7

Oil

~110 0662

y
FLEICPRINT
UNLESS OTHERWISE INDICATED:
RESISTORS ARE 114.: 5,.
RESISTORS ARE 7,500
CAPACITORS ARE .01 MFO
DIODES ARE 0664

C-CS-G796-0-1 Level Terminator G796,
Circuit Schematic

1
NOTES:
I FOR MO'...lN"T\NG \...C :'~\\()N Ct:"
IV\M O~-A. -RE.t="E'R \ 0 W'-I\tS ~ -:::)-

AR- ~-s -7.

SEE NOTE.: I

C-UA-MM09-A-O

Unit Assembly

PARTS LIST
PART
NO.

DRWG. NO.

DIGITAL EQUIPMENT CORPORATION
MAYNARC, MASSACHUSETTS

NO.
REQD. ITEM -

DESCRIPTION
STOCK SIZE-CAT. NO. -

A-PL-MC70-B-O

MC70-B MEMORY UNIT

A-PL-700S4S0-0-0

CABLE SET MM09-A

A-PL-783-0-1

783 POWER SUPPLY

A-PL-MM09-A-O

5-28

Parts List

MFG.

DEC.
STOCK NO.

i
I
I

MMOCfB
I

!
:

ft
\

D
OP.N
::lED
S:"'K

BLU
G~N

WHT
::lED

I
I

ITIIIIIJ

II II

;

MM OgA

BRN

----

:e~

oRN

I RED Beu YEe

n~ U~
70""

G.r:N

1>l'

~.~~U ~l~ltr

841 \

BRN~L~ m#m

I\;

MM 09A fIRST BK nTENDED MEMORY

(

783

MM 098'5ECOND

MM 0'1(, THIRD

MM09C

C, ............

-------

BAY

----

~~~~c
1ST
INTERIOR

I\--.I'I::RIOR FRONT

NOTE'S',

I iii iii

m[ D ~.

~
BASIC

rnIIJDf

2.ND

WHT

'-./

< ..-=,.1
i3RO
783

B
RED

REO BLK BLU

)
1

OJJ

(

[]]]]

ITIIIIIJ

783
INTERI~R

REAR Of' niENDED
MEMORY BAY

fRONT OF EXTE.NDED
MEMORY BAY

I. ALL. WIRING. \'5 -14 ~\NG 5TRA.Nt:l'C.D.
C. O"-lE 18:' ?O\NER ~\)'?PL.y IS I>..'D'DEC
~O~ ~p..c.\-\

MM09.

D-IC-MM09-A-l

5-29

Power Wiring

---

we --yp=::

S:::CT. LOC "TYPE

SECT.

'liC'::3

MC1mB C4¢ W~33

MM~9A

C3~

SIGNAL

E~G11

D38

D4¢

MB~-8

[3'<'

E4¢

MB 9-17 86 "

.1.

F38

F4¢

CONT ql

5 10.37

i
I

MEM

MC7QlB

MM<i>ClA

D38

M(/J

MBO-B 8\ I

Me q-17 86

Ilil
TO

SECI. LOC TYPE
MC70B CI¥/J W(1l33

SECT

MM(/jqB CONT

ILMt~
IN.

F38

F40

CONT '11

A4~

SAC/J-B 64

837

Me7QB B4¢

MM(j)'19 SA q-17 7(/>"

A37

1'2 837 W(/)33

A37 837 C3B D38 E38 F38

MM¢CfA CON'T

Mf/I B4¢ C40 D4~ E4~ F4¢

MB qJ-8 38~

E4r}

M8'H7 44 "

IF4(6

cOtn

F38

F40

CONT '11

A37

AMP

SArP-8 64

837

MC7G'B 840

MM(/JG)C SA'H7 7~

7 C38

MMalQC C4¢

MM0'1B CONT

D4r)

M8 C)l-9 3B~

E4(/J

MB'H7 44-

[38

I(]) F3a

CONT

A37

A40

SAO-8

21~

12 837

MM~'lC 84$

MM~qB SA"i-I7

13 C38

MM(flQS c4(}J

MMQ'!qA

Sri;

..... L
A37 837 C3S D38 E38 F3S

MM0CfA SA'1-17 27'

N01ES:

CONI

D4-¢

MBr/J-8 38~

E38

i
i

E4$

MB 9-17 44

F38

IF4(1i

CONT 5(/1

17 jA3?

A44l

5ACfJ- 8 21~i

MEM
MM(6QC

18 1837 W(/J33

8 D3S

14 D38

IO
KD0GA

SA@-9 21 ~'

A4~

D4r}

I'I1M(jJ'1S B41P WiJJ33

MM¢9B

KC¢QA

A37

IF38

MEM
CP

8 ID38

COMMEN'T

75"

MB9-17 86 "

MM¢qB C4¢

MB(/J-8 81 "

SIGNAL

D4tP

A4(/)' 840 C4qj o4f E4<jI F4¢

CO~,~;E~n

75,

E:4¢

E4¢

Ir:t>

MM¢CfC CONT

D38

E38

MC7¢B c4!/J wi/J33

E38

C38 W¢33

D40

7 C38

I
I,

f~OM

TO
FROM
11:$
SIGNAL
• LaC TYPE SECT. LOC iYPE
LElS1I!
SteT.

lOC TYPE

C38 VI/(/; 33

SA (7)-8 64

o
32K (MM 09A + MM09B+MM09C)

24K(MM(V9A + MM09 B)

A,i:3 I C,DIEIFIHI J
I
1
I
J
I
I
1

A'37 B37 C38 D38 E38 F3S

NO.

MC70B B4¢ W¢3'3 MM¢'1A SA 9-17 7(/J

837 W(/J33

A, e I c IDIEIF,HIJ

COMMEN"T

CONT 75

f-.

FR'I'vl
~~ I).

MM09sjB4¢ WcJ;33

i
MM~CfA

SACf-17 27

I\--

OTHERWISE DENO'TED ALL CABLES ARE 101 COND FL~PRINT WITH
,!\DHESIVE BACKED POLYESTER FOAM STRIPS (DEC PAR'''12-~58ill7)
ADHES[D TO ONE SIDE OF EACH CABLE FOR SEPJ'..RATION. CABLES TO BE
BUNDLED IN ZIPPER TUBING (DEC PART "1'2-0S5(P8).

I. UNLE SS

2. MEM S1ROBE MlJST BE. TERMINATED WITH
IN THE MM¢CJA ONLY.

3, 'fJHEN THE MEMORY PARIH (MP¢qA)
THE MMill'1A REQUIRE A G7'17.

15¢n. FROM

A4f1; B4i;! C4Qi D40 E40 F4~

IYy

REAR BASIC BAY

FRONT, E.'fTENOED
MEMORY BAY

E32L'T0 ('32.C

is NOT USE.D A37 AND 837 OF

D-IC-MM09-A-2

5-31

Cable Diagram

NOTES:
I. FOR MOUNTING. LOCA"TION c=
MMO~-B REFE:R TO DVvSAli~
AR - ~-O-7.

~V /~

Set. NOTE. I

I
I

W
W

~'---

Y
~

_ _J

C-UA-MM09-B-O

Unit Assembly

DIGITAL EQUIPMENT CORPORATION

PARTS LIST
PART
NO.

DRWG. NO.

MAYNARO, MASSACHUSETTS

NO.
REQD. ITEM -

DESCRIPTION
STOCK SIZE-CAT. NO. -

A-PL-MC70-B-O

MC70-B MEMORY UNIT

A-PL-700S4S1-0-0

CABLE SET MM09-B

A-PL-783-0-1

783 POWER SUPPLY

A-PL-MM09-B-O

5-34

Parts List

MFG.

DEC.
STOCK NO.

NOTES
MOUN"T\NG LOCA."'T\ON 0\=
'REFER \ 0 'Dv.J<::. >I< DA'R. - ='-0-(

I. FOR

MMO~ -

c..

01
1

C-UA-MM09-C-O

Unit Assembly

DIGITAL EQUIPMENT CORPORATION

PARTS LIST
PART
NO.

DRWG. NO.

MAYNARC,MAaaACMua.TTa

NO.
REQD. ITEM -

DESCRIPTION
STOCK SIZE-CAT. NO. -

A-PL-MC70-B-O

MC70-B MEMORY UNIT

A-PL-700S4S2-0-0

CABLE SET MM09-C

A-PL-783-0-1

783 POWER SUPPLY

A-PL-MM09-C-O

5-36

Parts List

MFG.

DEC.
STOCK NO.

CJ
10
"" NOT SHOWN

12
B

PDP-9 C ASI NET

D-UA-ME09-B-O

5-37

Unit Assembly

PARTS LIST

DIGITAL EQUIPMENT CORPORATION
MAYNARp,MA88ACHU •• TT.

PART
NO.

DRWG. NO.

D-AO-7005684-0-0

WIRED ASS'Y ME09-B

7005864

C-IA..,S4 O'2'S 26-0,..0

MARGINAL CHECKING PANEL

5"402526.

C-MD",'S302486 ... Q-O

RIGHT END PANEL

5302486

POP RIVET 1/8D #AD43ABS UaSaMaC.

90-06509

NO.
REQD. ITEM -

DESCRIPTION
STOCK SIZE-CAT. NO. - - MFG.

DEC.
STOCK NO.

C-MO-7405633-0-0

CABLE DUCT #1

7405633

D-MO-7405327-0-0

CABLE HOLD DOWN BRACKET

7405327

SCR PHI. ED PAN ~8-32 x 1/2 SST

9f'\f'\e::.f'\':lQ_l

NUT KEPS #8-32 SST

90-06563

SCR PHI

9006075-1

WASH EXT TOOTH #10

90-06635

TRUSS :1:1:1 O-~? X 3/4 SST

D-AD-7005320-0-0

INDICATOR PANEL ASS'Y ME09B

7005320

B-AD-7005449-0-0

CABLE SET

7005449

A-PL-ME09-B-O

5-39

Parts List

REVISIONS
REV ECONO
LTR

DATE

ENG

'. i (
A 167 /Jl-tJ/-6) If)
8 186 I-J6~1ft 6J [4)
/1.)
C 209 5-J..~45 A·{t.

....

I-

....

I-

A-WL-ME09-B-l

5-40

Wiring List

ME.Oqe
~E7D~

ORN

~BLK

-ew
~

I'iDICA"TO'f

II~N~

G.RN

BLlI BLK

+10'1 -1'10
VAR FiXED

F~~~D-~~~ GND F:~GH
}

\.,

WIRED iO

M.e.

PAI'\EL

BASIC BAY

NOTES:
I. BASIC BAY POWER WIRING IS
AWG :;;'/4- STRANDED.

D-IC-ME09-B-2

5-41

Power Wiring

COMPONENT NAME

VALUE

POL.

FROM PIN

TO PIN

I KOHM ~W~ 10%

B05R

B05A

RES (IO PWR CLR MEM DONE) 100 OHM ;!..rW±lO%

C!07F

C!07M

RES (STROBE READ PARITY)

Co 7".,

n07C!

(IO PWR CLR (B) )

nIl".,

nll("

(WRITE DATA EN)

C08H

CD8C

~i &

(READ DATA EN)

C08F

CORM

-.o·c
.. !

(SA18)

C07tJ

C!OF;C!

~'a~
ci~i
Co

(STR WR PAR)

B19J

B19C

(CLKD)

D32R

D32C

47 OHM

J38T

J38M

JUMPER *

D24C

D25H

;1: 6

D25H

D25J

~o e
._ C ~

D25J

D25K

D25L

D2~E

D2~C

e~
8:;

POL.

MP09-C

. . 1/1

;.8
E"
.9-:fj

RES

::11/1
III

Iff

-t:

i&
C.5
'06
~"
,,15 g.
Q.j .e .~

0..5 E

e::l C

.5"2 ~

(c LK D)

.l:OO

1/1

!'It!

(MA JAM PAR)

!E ::1.-

&~'O WIRE (INDICATORS)

2'.!!
'0';':
1/1

t! iii III

'Oi-S
.!!!'O i

t=iE

PAF(ITY

MEM DONE

100 OHM

....

KGQ9-B
RES(0~EPC UNLATCH)

100 OHM

A2~U

A2t;fC

100 OHM ~W±lO%

C19H

C19M

(CLR EPC)

C20H

C20M

(JAM EMA)

C!l q,T

C!lq("

(JAM EPC)

C20J

C20C

(DBR)

D32K

D31C

D26e

D25A

D25B

D25C

RES (CLR EMA)

WIRE (INDICATORS)

JUMPER *

A-CP -ME09-B-3

External Components Li st
(Sheet 1)

5-43

NOTES:
\. CONNECTION5 ON ITEM5 <l:F1 ;#2 TO 8E
SOLDERED AND LOCATED AT MINIMuM
PRACTICAL HEIGHT ABOVE 8-=':-<.
ALL CONN BLOCKS TO BE GROuNDED
TO GND LUGS AS SHOWN.
3. USE YELLOW WIRE (ITEM >t3) FOR
MACHINE WRAPPED ( BLUE WIRE
(ITEM ~4) FOR HAND WRAPPED WIRING.

3, 4, 5,

SEE NOTE

c:.

r SEE DETAil A
I

F.I---F
Jt--'-J

K--+--!-+--+'
p--+--!-+--+

~'--L
N-,.--N
"'--F\

M -t--+---1!--iM

u--u

-+I

-+7

10 JG

J +--+--t-J
~

F\+-+--+-p.

REF

-7-- I

I
--t--

-+I

+---+--+-L

+--+--+--N

I REF

F
J
L
N

19 R~F

NOTE I

:::0

+ •

DETAIL A
8 PLACES

SEE NOTE 2

D-AD-7005684-0-0

Assembly Drawing

5-45

PARTS LIST
PART
NO.

DIGITAL EQUIPMENT CORPORATION
MAYNARC,MASSACHUSETT8

NO.
REQD.

ITEM -

SEE ML

REF

WIRE LIST

SEE ML

REF

EXTERNAL COMPONENTS LIST

AIR

CHAIN VOLTAGE

AIR

#24 AWG SOLID KYNAR WET

AIR

#24 AWG SOLID TEF YEL

AIR

#24 AWG SOLID KYNAR BLU

DRWG. NO.

DESCRIPTION
STOCK SIZE-CAT. NO. -

MFG.

DEC.
STOCK NO.

1202188

D-AD-1943-D-0

1943D MTG PANEL

1943-D

A-DC-7406371-0-0

AIR

LOGIC FRAME DECALS (CLEAR)

7406371

A-PL-7005684-0-0

Assembly Parts List

5-47

Digital Equipment Corporation
Maynard, Massachusetts

printed in U.S.A.

momoomo