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DEC-09-H9ZA-D

July 1970

198 pages

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Document:	RF09
Order Number:	DEC-09-H9ZA-D
Revision:
Pages:	198
Original Filename:	http://bitsavers.org/pdf/dec/pdp9/DEC-09-H9ZA-D_RF09_Jul70.pdf

OCR Text

Digital Equipment Corporation
r~aynard, Massachusetts

PDP-9
Maintenance Manual

RF09/RS09
DECDISK SYSTEM
Volume I

DEC-09-H9ZA-D

RF09/RS09
DECDISK SYSTEM
MAINTENANCE MANUAL
VOLUME 1

DIGITAL

EQUIPMENT

CORPORATION •

MA YNA~D, MASSACHUSETTS

1st Printing July 1970

The material in this manual is for information purposes and is subject to change without notice.

The following arc trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL

PDP
FOCAL
COMPUTR LAB

CONTENTS
Page

CHAPTER"} DECDISK SYSTEM
1.1
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.2
1.2.1
1.2.2
1.2.2.1
1.2.2.2
1.2.2.3
1.3
1.3.1
1.3.2
1.3.3
1.4
1.5
1.6
1.7
1.8
1.9

Introduction
DECdisk System Description
Storage of Digital Data on Fixed-Head Rotating Disks
Storage of Data in a Serial Format
Random Accessing of Data
Data Accessing at Selectable Speeds
Data Protection from Over-Writing
DECdisk Operation
Disk Surface Recording Format
DECdisk Architecture
The Control Section
The Data Transfer Section
Maintenance Section
The Operator's Controls
Transfer Rate Selection
Disk Address Selection Jacks
Write Lockout Switches
The Operator's Indicators
Programming Examples
Programming With the ADS Register
Programming Multiple Disk Systems
Using DECdisk in a System
Summary of DECdisk Characteristics

1-1
1-1
1-1
1-3
1-3
1-3
1-3
1-3
1-3
1-6
1-6
1-10
1-15
1-16
1-16
1-19
1-19
1-21
1-22
1-25
1-27
1-27
1-29

CHAPTER 2 DECDISK MODULES
2.1
2.1.1
2.1.2
2.1.3
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11

2-1
2-1
2-2
2-2
2-3
2-7
2-10
2-13
2-16
2-16
2-16
2-16
2-21
2-21

Introduction
Types of Modules
Measurement Definitions
Loading
G085 Disk Read Amplifier
G285 Series Switch
G286 Centertap Selector
G290 Writer Flip-Flop
G681 B Track Matrix
G711 RF08 Terminator Board
G775 Indicator Panel
" G789 Signal Simulator Connector
G790 Signal Simulator Generator
G821 Regulator Control

iii

CONTENTS (Cont)
Page
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20

M 104 Multiplexer Mod ule
M216 Six Flip-Flops
M3 11 Tapped Delay Line
M149 9 X 2 NAND "Wired OR" Matrix
M500 Negative Receiver Module

2-24
2-29
2-31
2-33
2-33
2-38
2-41
2-41
2-45

M632 Negative Driver Module
705B Power Supply
716 Indicator Supply
855 Power Control

CHAPTER 3 RS09 DISK DRIVE
3.1
3.2
3.3
3.4
3.5

Read/Write Heads
Digital Recording Techniq ues

3-1
3-4
3-5
3-7
3-12

The Read/Write Head Electronics
The DECdisk Signal Format
The Timing Track Writer

CHAPTER 4 DECDISK LOGIC
4.1
4.1.1
4.1.2
4.1.3
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.5.1
4.3.5.2
4.3.5.3

Signal Error Detecting Circuits
Error Detection Logic for the A Timing Track
Error Detection Logic for the Band C Tracks
Error Detection Logic for the Data Tracks
The Control Section Logic
The lOT Decode and Trap Logic
The Function Register
The Timing Generator
The Unlock Seq uence Logic
The Track and Disk Address Register
The Word Address Register
The Disk Segment Register and Transfer Rate Select Logic
Equal Comparison Gating
The Address of the Disk Segment Register (ADS)
The Data Section Logic
The Buffer and Shift Registers
The WRITE Operation and its Associated Logic
The READ Operation and its Associated Logic
The WRITE CHECK Operation and its Associated Logic
Error Flags
WRITE CHECK Error
Error and FReeZe
Address Parity Error

4-1
4-1
4-5
4-6
4-7
4-7
4-10
4-10
4-10
4-10
4-17
4-17
4-23
4-24
4-25
4-25
4-25
4-25
4-37
4-37
4-37
4-41
4-41

CONTENTS (Cont)
Page
4.3.5.4
4.3.5.5
4.3.5.6
4.3.5.7
4.3.5.8
4.3.5.9
4.3.5.10
4.3.6
4.3.7
4.3.8
4.3.9

Missed Transfer Error
Data Parity Error
NonExistent Disk Error (PSLER)
Write LockOut Error
NonExistent Disk (SEQ ER)
Data Channel Timing Error
Program Error
Automatic Priority and Program Interrupt Logic
The A TEST and Read Disable Signal
The Gap
The Maintenance Logic

4-41
4-42
4-44
4-44
4-44
4-46
4-46
4-46
4-48
4-49
4-49

CHAPTER 5 FIELD INSTALLATION
5.1
5.2
5.3
5.4
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.6
5.7
5.7.1
5.7.2
5.7.3
5.8

5-1
5-1
5-1
5-4
5-4
5-4
5-4
5-6
5-6
5-6
5-9
5-11
5-11
5-11
5-11
5-11

Installation Location
Environmental Considerations
Primary Power Requirements
Accessories
Unpacking and Installation
Cabinet Unpacking
Cabinet Installation
RF09 Controller Installation
RS09 Unpacking
RS09 Installation
Power-U p Sequence
Acceptance Procedure
Acceptance Forms
Diagnostics
System Software
Shipping

CHAPTER 6 ORGANIZATIONAL MAINTENANCE
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.3

6-1
6-3
6-3
6-4
6-4
6-8
6-8

Preventive Maintenance
RS09 Adjustments
Measuring the Gain
Measuring the Slice
Calibrating the Read Amplifiers
Changing the Timing Tracks
Diagnostics

CONTENTS (Cont)
Page
CHAPTER 7 FIELD LEVEL MAINTENANCE
7.1
7.1.1
7.1.2
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.3
7.3.1
7.3.2
7.3.3

7-1
7-1
7-2
7-2
7-3
7-3
7-9
7-10
7-10
7-14
7-14
7-16
7-19

Field Level RS09 and RF09 Maintenance
RF09 Off-Line Checkout Without the RS09
RF09 Off-Line Checkout With the RS09
Field Level Disk Assembly Repairs
Removing the Disk Assembly
Removing the Disk Surface
Replacing the Shoes
Replacing the Disk Surface
Rewriting the Timing Tracks
Field Level RS09 Calibration
Measuring Surface Modulation
Analyzing the Gain of the Data Tracks
Calibrating the Gain of the Data Readers

APPENDIX A RF09 SIGNAL SUMMARY
APPENDIX B RS09 SIGNAL SUMMARY

ILLUSTRATIONS
Figure No.
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
1-11
1-12
1-13
1-14
1-15
2-1
2-2
2-3
2-4

Title
DECdisk System Configurations
RS09 Disk Drive
RF09 Controller
Disk Surface Recording Format
DECdisk Control Section
DECdisk Data Transfer Section
Simulating the Disk Surface with the Maintenance Logic
Simulating the RS09 with the Maintenance Logic
AC Bit Usage for lOT DGSS
AC Bit Usage for lOT DGHS
Transfer Rate Selection Switch and Disk Address Select Jacks
Write LockOut Switches
Indicator Panel
Calculating Fast Access Calling
Flow Diagram of the Subroutine That Uses the ADS Register
Voltage Spectrum of Negative Logic System
Voltage Spectrum of TTL Logic
G085 Disk Read Amplifier and Slice, Block Schematic
G085 Disk Read Amplifier and Slice, Circuit Schematic

Art No.

Page

09-0361
5003-5
5030-2
09-0407
09-0413
09-0358
09-0393
09-0359
09-0388
09-0360
5003-20
5003-1
5003-18
09-0420
09-0421
15-0070
15-0070
09-0357
C-CS-G085-0-1

1-2
1-2
1-4
1-5
1-7
1-9
1-17
1-18
1-19
1-19
1-20
1-20
1-21
1-26
1-28
2-1
2-1
2-3
2-4

ILLUSTRATIONS (Cont)
Figure No.

Title

Art No.

Page

2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
2-31
2-32
2-33
2-34
2-35
2-36
2-37
2-38
2-39
3-1
3-2
3-3

Disk Read Amplifier and Slice, Parts Location Diagram
G285 Series Switch, Block Schematic
G285 Series Switch, Circuit SChemftic
G285 Series Switch, Parts Location Diagram
Centertap Selector, Block Schematic
G286 Centertap Selector, Circuit Schematic
G286 Centertap Selector, Parts Location Diagram
The G290 Writer Flip-Flop, Block Schematic
G290 Writer Flip-Flop, Circuit Schematic
G290 Writer Flip-Flop, Parts Location Diagram
G681 Track Matrix, Circuit Schematic
G711 RF08 Terminator Board, Circuit Schematic
G775 Connector-Card Indicator Panel, Circuit Schematic
G789 Signal Simulator Connector, Circuit Schematic
G790 Signal Simulator Generator, Circuit Schematic
G82l +5V Regulator Control, Circuit Schematic
M104 Multiplexer, Block Schematic
MI04, Multiplexer Timing Diagram
M104 Multiplexer, Circuit Schematic
MI04 Multiplexer, Parts Location Diagram
M216 Six Flip-Flops, Circuit Schematic
M311 Tapped Delay, Block Schematic
M3l1 Tapped Delay, Circuit Schematic
M1499 x 2 NAND Wired OR Matrix
M500 Negative Receiver, Block Schematic
M500 Negative Receiver, Circuit Schematic
M500 Negative Receiver, Parts Location Diagram
Negative Driver, Block Schematic
M632 Negative Driver, Circuit Schematic
M632 Negative Driver, Parts Location Diagram
705B Power Supply
705B Power Supply, Circuit Schematic
716 Indicator Supply, Circuit Schematic
855 Power Control
855 Power Control, Circuit Schematic
Disk Assembly With Cover Removed
Disk Assembly with Cover and Surface Removed
(a) DECdisk Head Assembly and (b) Simplified Diagram
of the Magnetic Recording Process
NRZ and RZ Recording Formats
DECdisk READ/WRITE Electronics
READ/WRITE Electronics Waveforms
DECdisk Format
Timing Track Writer

09-0392

15-0087
15-0105
15-0134
B-CS-M2 16-0-1
09-0353
B-CS-M3 11-0-1
B-CS-M 149-0-1
15-0073
C-CS-M500-0-1
15-0138
15-0079
C-CS-M632-0-1
15-0140
5003-17
C-CS-70 5 B-1
B-CS-716-0-1
5003-14
C-CS-855-0-1
5003-23
5003-26
08-0458

2-5
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-17
2-18
2-19
2-20
2-22
2-23
2-25
2-26
2-27
2-28
2-30
2-31
2-32
2-34
2-35
2-36
2-37
2-38
2-39
2-40
2-42
2-43
2-44
2-45
2-46
3-2
3-3
3-4

09-0364
09-0362
09-0363
09-0406
5099

3-4
3-6
3-7
3-9
3-11

3-4
3-5
3-6
3-7
3-8

vii

09-0356
C-CS-G285-0-l
09-0391
09-0355
C-CS-G 286-0-1
09-0389
09-0354
C-C S-G 2 90-0-1
09-0390
B-CS-G681-0-l
B-CS-G711-0-l
B-CS-G775-0-1
B-CS-G789-0-l
B-CS-G790-0-l
B-CS-G821-0-1

ILLUSTRATIONS (Cont)
Figure No.
3-9
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
4-32
4-33
4-34
4-35
4-36
4-37
5-1
5-2
5-3
5-4
5-5

Title
Timing Track Writer, Block Diagram
A Track Error Detection
A Track Error Detection, Timing Diagram
B Track Error Detection
B Track Timing Diagram
Data Track Error Detection Logic
Data Track Timing Diagram
lOT TRAP Logic
Function Register
Timing Generator
Timing Generator, Timing Diagram
UnJock Seq uenee Logic
Track and Disk Address Register
Disk Segment Register and Transfer Rate Select Logic
Disk Segment Register, Timing Diagram
Equal Comparison Gating
ADS Register Logic
Buffer Register and Shift Register Interconnections
DCH Control for WRITE and WRITE CHECK
WRITE Circuitry
WRITE Operation for One Word in Address 1251
READ and WRITE CHECK Logic
DCH Control for Read and WRITE CHECK
READ Timing Diagram for One Word in Address 1251
WRITE CHECK Error
WRITE CHECK Timing Diagram for One Word in Address 1251
Error and Freeze
Address Parity Error
Missed Transfer Error
Data Parity Error
Write LockOut Error
NonExistent Disk by Program Selector Error
NonExistent Disk by Sequence Error
Data Channel Timing Error
Program Error
Automatic Priority Interrupt and Program Interrupt Logic:
Disk Run Logic
Read Disable Logic
The RF09 Cabinet
Hubbell Wall Receptacle Connector Diagram
Cabinet Bolting Diagram
The RS09 Electronics
DECdisk Cabling

viii

Art No.

Page

09-0365
09-0404
09-0405
09-0399
09-0400
09-0401
09-0402
09-0377
09-0378
09-0396
09-0417
09-0379
09-0380
09-0398
09-0146
09-0381
09-0382
09-0383
09-0395
09-0397
09-0418
09-0375
09-0374
09-0419
09-0373
09-0415
09-0387
09-0385
09-0386
09-0384
09-0934
09-0366
09-0367
09-0368
09-0369
09-0370
09-0371
09-0372
15-0033
09-0414
15-0098
5030-2
09-0376

3-12
4-3
4-5
4-5
4-6
4-6
4-7
4-8
4-11
4-13
4-15
4-17
4-18
4-19
4-21
4-24
4-24
4-26
4-27
4-29
4-31
4-33
4-34
4-35
4-37
4-39
4-41
4-41
4-42
4-42
4-43
4-44
4-45
4-46
4-47
4-47
4-48
4-49
5-2
5-3
5-5
5-7
5-8

ILLUSTRATIONS (Cont)
Figure No.
5-6
5-7
6-1
6-2
6-3
6-4
6-5
6-6
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-] 2
7-13

Title
The Disk Assembly with Desiccant Pan
Disk Assembly with Pan Removed and Motor Leads Connected
Purge Unit and Filters
Measuring Gain, The A Track Over One Revolution
Measuring the Slice of the A Track
Measuring the Slice of the B Track
Measuring the Slice of the C Track
RS09 Electronics Showing Posted Data
Disk Assembly Dismantling Kit
Removing the Disk Assembly from the Cabinet
Disconnecting Motor Leads and Purge Hose
Disk Assembly With Cover Removed
Disk Assembly With Cover and Surface Removed
Shoe Assembly Removed
Aligning the Heads
Aligning the Heads
Timing Track Writer
Measuring Surface Modulation on the A Track
Maximum Gain, Minimum Slice
Minimum Gain, Maximum Slice
RS09 Test Data Sheet

Art No.

Page

5003-14

5-9
5-10
6-2
6-3
6-5
6-6
6-7
6-9
7-4
7-5
7-6
7-7
7-8
7-9

5003-4
5056-1-10A
09-0403
5056-2
5056-4
5003-16
5003-11
5003-5
5003-14
5003-22
5003-25
5003-10
09-0411
09-0412
5099
5056-1-10B
5053-3-14
5056-3-13

7~11

7-12
7-13
7-15
7-20
7-21
7-22

TABLES
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
4-1
4-2
5-1
6-1
7-1
7-2

DECdisk Model Numbers
The Function Register Bit Configuration
Status Register Bit Functions
The DECdisk Instruction Set
Maintenance lOTs
The Indicator Panel
Adjusted ADS Register for Medium and Low Transfer Rates
Disk Data Checks
lOT Decode Effect on Trap Logic
Rotating the Disk Segment Register
Statistics for DECdisk Installations
Visual Inspection Checklist
Setting Up RF09 Delays
Jumpers to Increase Gain

1-1
1-10
1-11
1-13
] -15
1-21
]-27
1-29
4-9
4-23
5-2
6-1
7-2
7-18

Chapter 1
DECdisk System

1.1

INTRODUCTION

The DECdisk system is a computer peripheral that stores digital data on fixed-head rotating disks in a serial
format. The data can be randomly accessed at selectable speeds and, when necessary, protectl~d from overwriting.
1. 1. 1 D ECdisk System Description
DECdisk is a peripheral designed for the PDP-9, PDP-9L, and PDP-IS computers Each DECdisk system consists
of a controller and from one to eight disk drives. The controller connects to the computer's I/O Bus and communicates to the processor for control and status information. For data information, the controller communicates to memory through the data channel. Each disk drive connects to the controller through a parallel disk
bus. Both control and data information pass through the parallel disk bus.
There are two models of controllers and one type of drive. Table 1-1 lists these models and the computers on
which they are used. Figurc 1-1 illustrates the system configurations. This manual is primarily concerned with
the RF09/RS09 DECdisk system used with the PDP-9 and PDP-9L computers.
Table 1-1
DECdisk Model Numbers
Controller Model

Disk Drive Model

Related Computer System

RF09

RS09

PDP-9, PDP-9L

RFIS

RS09

PDP-IS

1.1.2 Storage of Digital Data on Fixed-Head Rotating Disks
Each RS09 disk drive consists of a rotating disk, a hysteresis synchronous motor, a matrix of 128 fixed read/
write heads, and the electronics required to drivc the heads (see Figure 1-2).
Thc 128 magnetic read/write hcads ride on thc surface of the rotating disk, which is nickel-cobalt plated. Each
read/writc head covers a separate track on the nickcl-cobalt surfacc: thus, disk action is similar to the operation
of many circular tapes running simultaneously in continuous loops.
Each track on thc disk can storc 2048 eighteen-bit data words. As a track fills, the system automatically moves
to the next track. The disk rotates at 1800 rpm (60 Hz power) and can, thercfore, transfer a word every 16 MS.

1-1

I/O BUS
PDP-9 t e - - - - ,

RF09
CONTROLLER

11 I I I
DISK BUS

RS09

~---I

RSO(

-- -

~
7

DISK DRIVES
09 - 0361

Figure 1-1 DECdisk System Configurations

RSOB-M
DISK ASSEMBLY-_ __

RS09
ELECTRONICS

Figure 1-2 RS09 Disk Drive

1-2

The storage capacity of each disk is 262,144 words (2048 words x 128 heads). Total system capacity is
2,097,152 words (8 disk drives x 262,144 words).

1.1.3 Storage of Data in a Serial Format
The DECdisk system stores the data on each disk in a serial format. The serial format causes the bits of each
word to be recorded one at a time along a single track, rather than all at once across eighteen tracks. Therefore,
only I of a possible 128 data heads is actively reading or writing data at a single time.

1.1.4 Random Accessing of Data
The DECdisk is a random-access storage system. Each disk is logically segmented into 2048 slices or words, and
each slice is preassigned a number or address from I to 3777 8 , The controller, in response to the computer, can
select at random any track of a disk and any address along that track to read or write a word (see Figure 1-3).

1.1.5 Data Accessing at Selectable Speeds
There are three speeds (switch-selected by the operator) at which data can be transferred between the disk surface
and the computer. The highest speed transfers a data word with each successive address, covering a track in one
revolution. The medium speed transfers every second word of a track in the first revolution, and then transfers
the alternate words on the same track during the second revolution. The slowest speed takes four revolutions to
cover a complete track. Once the operator has selected the desired speed, the controller hardware controls proper
interleaving of the words. However, the data should be read back at the same speed at which it was written to
avoid scrambling the data.
1.1.6 Data Protection from Over-Writing
Sixtl'en switches are available on each RS09 drive to protect disk-stored data. Each switch can inhibit the computer
from over-writing on eight separate tracks.

1.2 DECDISK OPERATION
Information flow within the DECdisk system is determined by the recording format on the disk surface and the
internal architecture of the controller. The following paragraphs describe the operation of the disk recording format and the system architecture.

1.2.1 Disk Surface Recording Format
As previously described, 128 read/write heads covering 128 concentric tracks ride on each disk surface. The circumference of each disk is logically divided into 2048 data segments or addresses, and in each segment of any
track a complete 18-bit computer word can be stored. A 2049th segment called a gap is provided to give the
heads time to switch tracks. This segment has no address and stores no data or timing tracks. It is used as a
marker to notify the controller each time a revolution has been completed.
Each data segment must store, in addition to its data word, two control bits; and each disk, in addition to its data
tracks, must contain six control tracks. The control bits are recorded with the data bits; the control tracks are prerecorded on the disk surface at the factory. Figure 1-4 illustrates the location of these bits and control tracks.
Data is recorded serially on each track in 20 bit words; 18 bits are data bits, and two bits are parity and guard bits,
respectively. Each 20-bit word unit is identified by an address that is prerecorded on a special track before the
disk is connected to the computer in the plant. This address is recorded serially on the B track (see Figure 1-4)

1-3

Figure 1-3 RF09 Controller

1-4

IIIIIIIIIIIIIIIIIIIIIII

PREFORMATTED
TRACKS
ICTI1711611511411311211111019I s I71

SECTION OF 16" DISK

l
ESSES
77sADDR
37

ADDRESS FOR 1251

-1

c
EJS]
T

~:E~~:~

SAMPLE
DATA
r=-=.......,-- -'-'-'''''''''''''' TRACK

1 4 4 t - - - - - - - - - DATA FOR 125 0 --------I~~

Note: 1
A= Timing Track
B = Address Track
C = Delimitter Track
0= Sample Data Track
CT= Control Bit
G= Guard Bit
P= Parity Bit

......
I

Note: 2
The heads are built in groups of S (called shoes) -and mounted
around the disk surface.
09-0407

Figure 1-4 Disk Surface Recording Format

exactly one word before the word with which it is associated. The controller can then assemble and identify the
address before the heads reach the word itself. Each address is 13 bits long; 11 bits supply addressing data, 1 bit
is a control bit, and 1 bit is a parity bit.
There are five additional prerecorded tracks on the disk surface. The A track is a prerecorded track with pulses
800 ns apart that are used to strobe data into or out of the data tracks. The C track is a track used to delimit each
word unit. The controller relies on the C track to signal when a word has been assembled or written. The controller can then notify the computer to accept the word read or to supply another word to be written. Each of
the three prerecorded tracks described - the A, B, and C tracks - are copied on three spare tracks that are used
if one of the original tracks is accidently erased in the field. If the spare tracks are damaged, all the timing tracks
can be rewritten in the field with a special timing track writer (see Chapter 7).
1.2.2 DECdisk Architecture
In this manual, the DECdisk system architecture is presented in three parts; the Control section, the Data Transfer
section, and the Maintenance section (shown in Figures 1-5, 1-6, and 1-7 and 1-8, respectively). Through the
Control section, the software operating system initializes the controller by selecting the disk drive (RS09) to be
used, the track address within that drive (Data Track Matrix) to be used, and the first address within the track to
be used. One of three functions is then selected: READ the disk; WRITE on the disk; or WRITE CHECK what
has already been read or written. The Data Transfer section assembles the word off the selected track for a READ
operation, or writes the word bit by bit onto the track during a WRITE operation. This section also notifies the
computer when it has assembled a word or needs another word to write, and the data is transferred through the
three-cycle data channel. When the last word has been transferred, the computer issues an overflow pulse to the
controller. An interrupt then occurs, and transfers are stopped. The Maintenance section simulates either the
disk surface head signals or RS09 output signals and is used exclusively for testing the DECdisk system.
1.2.2.1 The Control Section - The block diagram of the Control section in Figure 1-5 shows 11 relatively independent sections. Some of these sections contain registers, and the bits of these registers are numbered according to the position they occupy when they are read from or into the accumulator of the Central Processor.
Three of these registers - the Disk Number, the Track Address, and the Word Address - are set by the software
system to select the disk (one of a possible eight), the track within that disk (the read/write head matrix), and
the starting address within the track. Each time a word is transferred, the word address is automatically incremented by one to prepare for the next word. When the Word Address Register overflows, the track address is
automatically incremented; and when all tracks have been exhausted, the Disk Number Register is incremented.
TIlese registers continually step from word to word, track to track, and disk to disk until the system has been
covered.
NOTE
Incrementing occurs during a valid operation only.
After the system has been covered, the computer is notified that it has run out of disks. The dead space (gap)
shown in Figure 1-4 is used to give the controller time to switch tracks when it needs to do so.
The Word Address Register is constantly being compared to the contents of the Segment Register, which in turn
is sampling the "B" or address track. When the "C" or delimiter track indicates that a valid address in the
Segment Register, the word address is compared with the assembled address; and if the two match, an
ADDRESS OK signal is passed to the data transfer logic. This signal informs the data transfer logic that the data

1-0

NOTES:
1. The READ/WRITE data heads are mounted on shoes in groups of 8 and each shoe
is mounted on a card. The cards are mounted around the underside of the disk so
that each head covers a different track. The timing card has 1 shoe.
2, The cords are cabled from the RS09 READ/WRITE logic and selection matrix ,which
in turn cable to the controller
3, Each RS09 has both input and output cable slots. The signals are cabled in
parallel from drive to drive toa maximum of 8.
4, The track address register selects the head according ta the folowing bit
configuration:

RS09

~ RS,oa-M DISK
~---/~V
HEAD CABLES -

\ h
------~-v

HEAD

DATA
CARDS
8 HEADS /

TIM ING CARD

HEAD CABLES

SHOE

16)

L-_"'----::;;""/!.-__-+__________________--,

ISHOE
MATRIX

HEAD CABLE {'
CONNECTORS

~MAJ~oIX ~MAJ.~IIX
0

TIMINGiTRACKS
READ/ WRITE
LOG IC

SELECT

DATA SIGNALS

DATA TRACK MATRICES
SELECT AND
READ/WRITE LOGIC

A,B,C SIGNALS

OUT

RF09

CONTROL SECTION

(o")

r--r-I-

DATA SIGNALS TO
DATA SECTION Figure 1-6

ADS REGISTER

SELECTION
PANEL
B (ADDRESS)
TRACK SIGNALS-I--

I
SEGMENT ADDRESS
REGISTER

INTERLACE BUSY
AND WRITE

BINARY-OCTAL
DECODER

IORS ----

OVERFLOW ----

,...

,....

STATUS REGISTER

FUNCTION
REGISTER

DISK NUMBER
REGISTER

10111213141516171 e l91 10 1

115 1161171

1151161171

DI SK
FLAG

I
TRACK ADDRESS
REGISTER

I
WORD ADDRESS
REGISTER

INCREMENT

t-- ~~-fER EACH

f4--

WORD

L..-J

ADDR ESS O. K.

TIMING

707001
lOP
PULSES
AND
DEV I CE
AND
SUBDEVICE
CODES
I/O BUS
CABLE
PDP- 9

f-- SKIP IFDISK FLAG

707021

f-- CLEAR CONTROL

707022

f-- OR TRACK AND WORD ADDRESS INTO AC

a C TRACK SIGNALS

GEN:~tTOR
CONTROL

~ TIMING CONTROL

! SIGNAL TO
f-1.-. ALL REGISTERS

707062 f-- OR DISK NUMBER INTO AC
DEVICE
AND
SUBDEVICE
DECODING
AND
rOT TRAP
LOGIC

707024 f--.+ LOAD AC INTO TRACK AND WORD ADDRESS
707064 f--.+ LOAD AC INTO DISK NUMBER
707041

f--.+ CLEAR FUNCTION REGISTER

707042 f---. XOR AC TO FUNCTION REGISTER
707044 f--.+ EXECUTE FUNCTION REGISTER
707202 f--.+ OR ADS REGISTER INTO AC

I
I/O eus
00-17
0

.....

'-'

707242

f-- CLEAR STATUS REGISTER

707262

f----- OR STATUS REGISTER INTO AC

I/O BUS
DRIVERS AND
RECEIVERS

Figure 1-5 DECdisk Control Section

1-7

09-0413

MULTI CYCLE
DATA CHANNEL
PROGRAM INTERRUPT
AND
AUTOMATIC
PRIORITY INTERRUPT
CONTROL

110 BUS
00-

CONTROL
LINES

.........
OVERFLOW

AP 1
or
PI
FLAG

DCH
FLAG

~
BUFFER REG I STER

I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 I 8 1 9 I 10 111 1121131141151161171

t
READ

t
~
SHIFT REGISTER

7 8 9
0 1 2 3
5
1 1 1 1 141 1 61 1 I 110 111 1121131141151161171

WRITE
~

T O/FROM
DATA
SI GNALS
09-0358

Figure 1-6 DECdisk Data Transfer Section

it wants to read is presently passing over the read head of its selected channel, or that the space in which the
data transfer logic wants to write is about to come under the read/write heads.
TIle interlace logic is used by the operator to reduce the transfer rate of the disk to either a medium or a low
speed. The medium speed cuts the rate in half by adjusting the final address of the Disk Segment Register so that
only every second address is used in the first revolution of the disk, and the alternate addresses are picked up from
the same track on the subsequent revolution. The low speed cuts the transfer rate by four. Each address is then
adjusted to require four revolutions of the disk before a complete track is filled. Bits X4 and X2 indicate low and
medium speed, respectively, and are set if these speeds are selected by the operator. The flag BZ sets whenever
a valid operation is under way, and WB sets when writing is taking place. All of these bits can be read into the accumulator under program control.
rOle ADS Register receives each valid current segment address from the Segment Register. The current segment
address is then available to the accumulator in the ADS Register under program control. Note that the ADS
Register receives the current address, and not the adjusted address for low or medium speed transfers.
There are three bits in the Function Register, which is double buffered. Bits 15 and 16 specify the function that
is to be performed by the controller. The function is loaded into the first buffer, and an execute lOT (DSCN) is
issued to load it info the second buffer for execution. At the end of an operation, or if an error occurs, the
second buffer is cleared and execution stops. The operation can then be continued by issuing a DSCN lOT execute. Table 1-2 shows the bit configuration needed to select each function. Bit 17, also contained in the
Function Register, enables the interrupt and API logic of the control.
Table 1-2
The Function Register Bit Configuration
Function

Bit 15

Bit 16

No Effect

Read

Write

Write Check

The timing generator and control logic receive the A and C track signals and generate all of the system timing and
control pulses necessary to carry out the various macro operations (such as shifting the Segment Register and incrementing the Word Track and Disk Address Registers).
The 100bit Status Register reflects the state of the system after it has perfonned its specified operation. Any timing or parity errors that have occurred during the operation are indicated here. Table 1-3 summarizes the function
of each bit.
1.2.2.2 The Data Transfer Section - The data transfer section, shown in Figure 1-6, has 4 subunits; two 18-bit
registers and two controls. During a READ operation, a word is assembled into the Shift Register. If the word
has been assembled from the selected address (ADDRESS OK), and the C track indicates that a valid word has been
assembled; the contents of the Shift Register are then jammed into the Buffer Register. The computer is notified
that a word is ready for transfer, and a multi-cycle data break occurs. At the same time, the Shift Register is assembling the next word. The word count (WC) and current address (CA) for the DECdisk are in locations 368 and
37 8 , respectively.
1-10

During the WRITE operation, the computer transfers the word to be written into the Buffer Register where it
waits for the ADDRESS OK signal. When this signal arrives, the word is immediately transferred to the Shift
Register and is serially shifted from there onto the selected track.
During a WRITE CHECK operation, which is designed to allow the programmer to compare data in memory with
corresponding data on the disk, the memory word is fed into the Buffer Register and then into the Shift Register
where it is compared bit by bit with the serial data directly from the disk. If a discrepancy or a parity error exists,
the DISK flag is posted.
The instruction set, listed in Table 1-4, allows the computer to clear, load, or read from each of seven registers
in the control section. The following points should be noted:
a.

The DISK flag is posted under two conditions;
(1)

at the end of the operation, and

(2) if one of the six error conditions occur.
The DISK flag causes either a PI or an API interrupt if these interrupts are enabled in both the
controller and the computer.
b.

Whenever the DISK flag is posted, the second buffer of the Function Register is cleared, and the
operation stops. The first buffer does not clear; and the operation can either be continued by
issuing the execute lOT, or altered by changing its code and then issuing the execute instruction.

The ADS Register reflects the current position of the disk and not the adjusted address. A program can read its contents and calculate the nearest possible address to which it could transfer
its first word (taking into account the speed setting), set the address into the Address Register.
and, thereby, reduce the initial latency time. (The ADS Register can be one address late.)

The disks are not synchronized with each other. When the control transfers from disk to disk,
the control itself has no way of knowing the next disk location in its revolution. The ADS Register
locates the next disk.

During an operation, the Disk, Track, and Word Address registers automatically increment as the
system rotates from word to word, track to track, and disk to disk. At all other times, these
registers remain constant.

Table 1-3
Status Register Bit Functions
Bit

Flag Name

Function

ERR

This ERRor flag is the logical OR of the error conditions of bits 1
to 7. When this bit is set, it causes an interrupt and conditions the
skip lOT. It also inhibits the current operation until a continue
lOT is issued.

HDW

The disk HarDWare Error is set if the control detects missing bits
from the A, B, or C track. A set HDW causes the control to freeze
for further evaluation. (During a "freeze" condition, writing is
stopped and the A timing pulses are inhibited.)
A freeze is disabled with an I/O RESET, a CAF, or the DECdisk
clear lOT.

1-11

Table 1-3 (Cont)
Status Register Bit Functions
Function

Bit

Flag Name

APE*

The Address Parity Error flag is set if a parity error occurs when
the address is being assembled, provided that the control has been
programmed to READ/WRITE or WRITE CHECK. This flag does
not set if the disk is idling. APE also freezes the control.

MXF

A Missed X (Trans)Fer flag is set if the disk requested a data transfer
from the computer and did not get it for 2-3 revolutions. A 130 ms
timer triggers to post the MXF flag. Either a data channel failure or
a data channel overload initiates this flag.
When analyzing an MXF error, the following points should be considered:
a.

The computer increments its current address in the cycle before
it transfers its data.

The controller increments its disk or track address when it requests a transfer during a read operation, but only after a transfer is acknowledged during a WRITE or WRITE/CHECK
operation.

WCE

When the Write Check Error flag is set, the controller has discovered
during a WRITE CHECK that the word from memory differs from
its corresponding word on the disk. The error flag is raised and all
further checking is stopped. The word being checked is in disk location WA-I (Word Address minus I), and its corresponding word
is in memory address CA-I (Current Address minus I).

DPE*

The Data Parity Error status bit is set whenever the data parity bit
does not agree with the computed parity of the data word just read.
The control transfers the data word containing the parity error and
raises the error flag. No further transfers occur until the program intervenes. The WA-I contains the disk address of the word in error.
The CA contains the memory address of the word in error.

WLO*

The Write LockOut error bit is set when an attempt is made to write
into a protected region on the disk. READ or WRITE CHECKING
a protected area is permitted. (See the Operator's Controls Section,
paragraph 1.3, for details of this protection.)

NED

If a disk which does not exist is called for under program control or
sequenced into during data transfers, the Non Existence Data flag
is raised to signal the error. (For details on how disks are assigned,
see the Operator's Controls Section, paragraph 1.3.)

DCH

The Data CHannel Timing Errors status bit is set whenever the
processor has not completed a DCH transfer before the disk control
is ready to transfer data. No error flag is raised. This status bit is intended as a warning that the DCH channel is overburdened.

*Note that the hardware is designed to a1l0w only the first of these thw: errors to set during an operation.

1-12

Table 1-3 (Cont)
Status Register Bit Functions
Bit

Flag Name

Function

PGE

The ProGramming Error status bit is set whenever the program issues
an illogical command to the disk. Furthermore, if the command directly conflicts with the operation of the control, the command is
ignored. No error flag is raised. This status bit is provided as a warning to the programmer.

XFC

When the job requested via the program (either READ, WRITE, or
WRCHK) is finished, the (X) TransFer Complete flag indicated by this
bit interrupts the processor and conditions the SKIP lOT.

Table 1-4
The DECdisk Instruction Set
Code

Mnemonic

Description

707001

DSSF

Skip if Disk Flag. The Disk flag is raised for either an error condition
(ERR) or when transfer is complete (XFC). This flag is indicated on
bit 13 of the Input/Output Read Status (lORS) facility. If the Program
Interrupt (PIE) and/or Automatic Priority (API) is enabled, the DSSF
flag causes the program to be interrupted.

707021

DSCC

Clear the Disk Control and disable the "freeze" status of the control.
This lOT is the only command honored by the control when a "freeze"
is caused by either a timing track hardware or an Address Parity Error
and forces the control to abort the operation in progress. It effectively
Power Clears the DISK CONTROL.

707022

DRAL

OR the contents of the Address Pointer 0 (APO) into the AC. Bits 0
through 6 contain the track address and bits 7 through 17 contain the
word address of the next word to be transferred.

707062

DRAH

OR the contents of the Disk Number (API) into the AC. Bits 15, 16,
and 17 contain the Disk Number. Bit 14 is read back if a data transfer
has exceeded the capacity of the Disk Control (causes a NED error
status).

707024

DLAL

Load the contents of the AC into the APO.

707064

DLAH

Load the contents of the AC (15, 16, 17) into the Disk Number (API).

707041

DSCF*

Clear the Function Register, Interrupt Mode.

707042

DSFX*

XOR the contents of AC bits 15-17 into the Function Register (FR).
The use of each bit is the same as described for bits 15-17 of the Status
Register.

707044

DSCN*

Execute the condition held in the FR. Since the AP contains the next
available word (because it is incremental), this lOT can be used to continue after having changed the Word Count (WC) and Current Address
(CA) held in core memory, or it can be microcoded with the Clear (DSCF)
and XOR (DSFX) instructions to execute a new function at different
address.

*These instructions may be microcoded
in any combination.

1--13

Table 1-4 (Cont)
The DECdisk Instruction Set
Code

Mnemonic

Description

707202

DLOK

OR the contents of the II-bit Disk Segment Address (ADS) into the AC.
The ADS Register contains the real-time segment address, which is useful
for minimizing access times. The address read always indicates the physical position of the disk (that is, one address of 2048 for one revolution
(360°) of the disk, independent of the transfer rate being used).
Register Configuration
X4

ADDRESS OF DISK SEGMENT
(ADS)

When reading the ADS Register, the most significant four bits contain the
status condition explained below.

AC Bit

Name

Function

Busy. The disk has been commanded to transfer data and it is not finished. When reading
the ADS Register, this is an indication that if
the A.ddress Pointer is used by the programmer
to determine the Track Address (TA), the Track
Address may not be valid if the ADS Register
contains 3777 (since the TA may be changing
at this time).

The control is set to transfer every fourth word.
The effective transfer rate is, therefore 64 J.lS
per word.

The control is set to transfer every other word.
The effective transfer rate is, therefore, 32 J.lS
per word.

If neither X4 nor X2 is set, the control is operating at its highest rate or
16 J.lS per word.

ACBit

Name

Function
Write Bit. This bit is used primarily for maintenance purposes. It is the intermediate storage location for the data being transferred to
the disk during WRITE.

707242

DSCD

Clear the Status Register and Disk Flag.

707262

DSRS

OR the contents of the Disk Status Register with the Accumulator
(AC). Status at the point of interrupt is as follows:
AC

o
1

Error (ERR)
Disk Hardware Error (HDW)

1-14

Table 1-4 (Cont)
The DECdisk Instruction Set
Code

Mnemonic

Description

707262
(Cont)

2
3
4
5
6
7
8
9
10

Address Parity Error (APE)
Missed Transfer (MXF)
Write Check Error (WCE)
Data Parity Error (DPE)
Write Lockout (WLO)
Non Existent Disk (NED)
DCH Timing Error (DCH)
Program Error (PGE)
Transfer Complete (XFC)

AC 15, 16, and 17 Function Register states are as follows:
(If Bit 17 is aI, the API and PI logic in the controller is enabled.)
Bit 15 (FO)

Bit 16 (Fl)

0
0
1
1

0
1
0
1

No Effect
READ
WRITE
WRCHK

1.2.2.3 Maintenance Section - The Maintenance section provides a means to test each unit of the DECdisk system without running the other units. Signals that usually come from the read/write heads of the disk surface can
be simulated by the controller under lOT control with the logic shown in Figure 1-7. Similarly, signals from the
RS09 output cables can be simulated by the controller with the logic shown in Figure 1-8. In this way, the controller can be tested without the disk drive, and the RS09 electronics can be tested without the disk surface. A
more detailed explanation of these signals is found in Chapter 2.
The Buffer Register, which is normally available to the data channel alone, can be accessed from the Central
processor under the control of maintenance lOTs.
The Maintenance section also allows signals transmitted over cables between the controller and the RS09 disks to
perform active functions while they are themselves active. Therefore, if a wire in the cable is broken, a function
is disabled rather than uncontrollably activated.
Table 1-5 lists the maintenance lOTs, and Figures 1-9 and 1-10 shown simplified versions of some of the maintenance logic for the simulator section.
Table 1-5
Maintenance lOTs
Code

Mnemonic

707204

DGHS

Description
Generate Simulated Head signals. This maintenance lOT causes the
control to generate analog signals that simulate the disk head signals,
as received directly from the head. The AC is used to determine the
sequence of pulses to be generated, and the bit rate is controlled by
the diagnostic program. Each lOT, in effect, is treated as though it
were one cell space on the disk. The function of the AC bits is shown
in Figure 1-9.

1-15

Table 1-5 (Cont)
Maintenance lOTs
Code

Mnemonic

707204

Description
The bits are arranged as shown to provide for data packing, since only
the bits that appear in the AC in bit cell 1 position are used when the lOT
is generated. An RAR can then be used to position the data for the next
Simulated Head Signal.
When either of the maintenance lOTs (707204 or 707224) is used, a
Maintenance Control flip-flop is set that inhibits the effect of control
delay timeouts, which are a result of the lower data rates encountered
under program simulation. If subdevice Bit 0 (MB 12) is used when
issuing the above lOTs, the Maintenance Control flip-flop is cleared.

707224

DGSS

Generate Simulated Disk signals. This lOT causes the control to generate Simulated Disk Interface signals within the control. No disk is necessary. The AC is used to determine the sequence of pulses to be generated and the bit rate is controlled by the diagnostic program. Each lOT,
in effect, is treated as though it were one cell space on the disk. The
function of the AC bits is shown in Figure 1-10.
The bits are arranged as shown to provide for data packing, since only
the bits which appear in the AC in bit cell I position are used when the
lOT is generated. An RAR can then be used to position the data for the
next Simulated Head Signal.

707002

DRBR

OR the contents of the Buffer Register with the AC. This is a function
normally performed by the data channel.

707004

DLBR

Load the contents of the AC into the Buffer Register. This is a function
normally performed by the data channel.

1.3 THE OPERATOR'S CONTROLS

There are three groups of operator controls on the disk system. These include a three-position switch to select
the transfer rate, a jumper panel to assign the address of each disk, and a series of write lockout switches to pro··
tect regions from being written onto each disk. The fIrst two controls are part of the controller itself, and the
write lockout switches are available on each disk drive.
1.3.1 Transfer Rate Selection
The operator can select a high, medium, or low transfer rate by positioning the rate selection switch at HI, MED,
or LOW.
At the high speed, data is transferred to or from each word on a disk channel every 16 J.Ls.
At the medium speed, the rate is halved to every 32 J.Ls, not by slowing down the disk, but by requiring the disk
to rotate twice in order to fill a channel completely. During the first rotation, every second address is read from
or written into; in the second rotation the remaining addresses are used. All this is done automatically without
extra coding. However, the programmer must ensure that the disk is read at the same speed at which it was written,
or the data becomes unintelligible.
At the low speed, every fourth address is used on the first revolution, and the remaining addresses are picked up
on the successive three turns. The transfer rate is one word every (4 x 16) 64 J.LS. The programmer is not

1-16

TO R S 0 9 HEAD CABLE
) CONNECTOR SLOTS

(

SPECIAL HEAD SIMU LATOR CABLE
G789 -G790B

(

ATT

ITOGI

(

03o OF CONTROLLER

BTT CTT DATA

--..
1

I I
5

lOP PULSES
AND
SELECT CODES

DEVICE
AND
SUBDEVICE
DECODING

707204

707224
1/0 BUS
00-17

DGHS

---.DGSS

1/0 BUS
RECEIVERS

NOTES:
1. TOG is complemented when DGHS is released.
2. Bits 13,9, and 5 are set from corresponding AC bits.
3. The letters ABCD indicate which track is simulated.
o is for all data tracks.
09- 0393

Figure 1-7 Simulating the Disk Surface with the Maintenance Logic

1-17

SIMULATED SIGNALS
FOR MAINTENANCE

OR OF SIMULATED SIGNALS
AND RS09 SIGNALS

SIGNALS TO
REGISTERS

----~-----~y -------~----

IOT DGSS

SYNC
SCOPE

BUS

021 N2
OTN

3--r---L_~

DATA SIGNALS
POSITI VE AND NEGATIVE
OTP

5 ----4----1

CTN
7 ----I----l

C TRACK
SIGNALS
CTP

9 ----41-----1

BTN
11 - - - - 1 - - -.....

B TRACK
SIGNALS
BTP

13--+----1

15--+----1
~----------------- ATNM

A TRACK
SIGNALS

BUS

17 --+----1
ATPM
NOTE:
SYNC provides a point on which to synchronize an oscilloscope at any place needed
in the program.The probe location is 021 N2 on D-BS-RF09-0-09.
09-0359

Figure 1-8 Simulating the RS09 with the Maintenance Logic

1-18

BIT CELL 1

BIT CELL 2
09-0388

Figure 1-9 AC Bit Usage for lOT DGSS

BITCELLI

BITCELL2
09-0360

Figure 1-10 AC Bit Usage for lOT DGHS

required to do any extra coding, as the hardware completes the operation. The programmer must, however, ensure that the data is read and written at the same speed. Table 4-2 explains address modification for the two lower
speeds by the Segment Register. Note that the PDP-9/L Computer should be used only at medium or low speeds.
1.3.2 Disk Address Selection Jacks
The jacks shown in Figure 1-11, which are part of the controller, are used to assign selection numbers to the RS09
disk drive. The select wire of each drive is wired to an individual plug in the DISK bank. The select decoder of
the controller is wired to the DISK SELECTION jacks. Each disk can be assigned any address by plugging the appropriate DISK SELECTION jack into that disk's plug of the DISK bank. Any jacks that are not assigned should
be plugged into one of the NONEXISTENT DISK plugs; a selected nonexistent-disk error can then be detected.
1.3.3 Write Lockout Switches
There are 16 lockout switches on each disk drive (labeled 00 through 74). Each switch protects 8 tracks on the
disk. Switch 00 protects tracks 0 to 78 , switch 04 protects tracks 108 through 17 8 , and so on, up to track 1708'
When anyone of these switches is set to DISABLED, the 8 tracks that they protect cannot be written on. If the
program tries to write in such a protected area, the WLO flag (Write LockOut) is posted and writing is inhibited.
Figure 1-12 shows the lockout switches. Note that switch 00 actually protects the first head of each shoe, switch
04 the second head, etc. For the programmer, this translates into successive tracks in blocks of 8.

1-19

Figure 1-11 Transfer Rate Selection Switch and
Disk Address Select Jacks

Figure 1-12 Write LockOut Switches

1-20

1.4 THE OPERATOR'S INDICATORS
The operator has at his disposal an extensive indicator panel that reflects the state of the DECdisk system (see
Figure 1-13). If a light on the panel is lit, the bit it reflects is set. Table 1-6 summarizes the meaning of each
light.

Figure 1-13 Indicator Panel

Table 1-6
The Indicator Panel
Indicator Name

Indication When Lit

STATUS

ERR,HDW,
APE, MXF,
WCE, DPE,
WLO,NED,
DCH,PGE,
XFC

The Status Register bits described in Table 1-3 are set.

FUNCTION

Three bits of the Function Register decoded in
Table 1-2 are set.

DISK

Three bits of the Disk Selection Register are set.

Indicator Group

ADDRESS
POINTER
FLAG

{DISK
DATA

OFLO

PARITY

{ ADDR
DATA

The first 7 bits from left to right indicate the contents
of the Track Address Register, and the following 11
bits indicate the content of the Word Address Register.
This level is the logical OR of the two conditions that
cause an API or PI break - the ERROR flag and the
TRANSFER COMPLETE flag.
The flag that requests a multicycle data break is set.
The computer has overflowed its Word Count Register
and has set this flag to stop further transfers.
A parity error on the B or address track has been
detected.
A parity error on the current data track has been
detected.

1-21

Table 1-6 (Cont)
The Indicator Panel
Indicator Group

ITL

The disk is presently BUSY and engaged in a data
transfer.

When this bit is set, the operator has selected the LOW
transfer rate, and every fourth bit is being transferred.
(ITL = interlace.)

Same indication as X4, except that the operator has
selected the MED transfer rate.

DOFL

During a transfer, the control sequenced into the ninth
disk, which does not exist. (NED = Non Existent Disk.)

SEQ

During a transfer, the control sequenced into a disk unit
that does not exist. The difference between DOFL and
SEQ is that in SEQ a disk could be added, i.e., the system capacity was not exceeded. With DOFL, the control asked for a disk :address greater than 78 ,

r
,.

NED

Indication When Lit

Indicator Name

PSL

A nonexistent disk unit was specified by the program.
It was not sequenced under a transfer; the error was a

direct programming mistake.

HDWRERR

I
I

WRITE

A WRITE operation is taking place.

RUN

The control is busy and properly synchronized.

A missing negative pulse or extra positive pulse from
the AIT track bipolar signal pair was detected.

A missing positive or extra negative pulse from the ATT
track bipolar signal pair was detected.

Any pulse of the bipolar signal pair from the BIT track
was detected as missing or extra.

Any pulse of the bipolar signal pair from the CIT
track was detected as missing or extra.

Any pulse of the bipolar signal pair from.the addressed
data track was detected as missing or extra.

MAINT

The controller is in Maintenance mode, which is explained in detail in Chapter 4.

1.5 PROGRAMMING EXAMPLES
The following program can be used to READ, WRITE, or WRITE CHECK any number of words that can be accommodated in core memory. The program is set up from a calling sequence table that lists the word count,

1-22

current address, disk number, track number, the address of the first word in the track, and the function to be
performed. The execute subroutine that follows enters these variables in their respective registers and commands the disk to execute.
/Calling Sequence Table
JMSDO
o (WC)
o (CA)
o (APO)
o (API)
o (FR)
X

CALTAB

/Jump to execute subroutine
/2's complement of number of words to be transferred
/Start of memory core data table less 1
/Disk starting word address and track
/Disk number
/Function (READ, WRITE or WRITE CHECK) desired
/Continue program sequence
/Execution Subroutine

LAC DO
DACIO
LAC * DO
DAC 36
LAC * 10
DAC 37
LAC * 10
DLAL
LAC * 10
DLAH
LAC * 10

{DSCF
DSFX

DSCN
JMP * 10

/Enter execution subroutine
/Fetch pointer
/Deposit pointer in Auto Index Register
/Fetch word count
/Deposit in Word Count Register
/Fetch current address
/Deposit it in CA Register
/Fetch disk starting word and track address
/Deposit it into its registers
/Fetch disk number
/Load into Disk Number Register
/Fetch the function
/Clear the Function Register
/XOR the Function Register
/Execute the condition held in the Function Register
/Exit the disk subroutine

t Notc that these instructions are usually microcoded into 707047.

In this example, a pointer (DO) is set into Auto Increment Register 10. Each time the register is indirectly addressed, it is first incremented by a one. The effective address for the first entry is the WC; for the second, the
CA; and so on, down the calling sequence table to the FR. With this technique, the execution subroutine sets
up the disk and the multi-cycle data break to carry out the .prescribed operation.
The DISK flag is posted if either an error occurs during the transfer or the transfer is completed successfully. The
DISK flag causes a PI or API break (if they are enabled) to locations 0 8 or 63 8 , respectively, and the program tests
for an error or sets up the next transfer from the selected location. The DISK flag can also be tested by the DSSF
instruction if PI or API are not used. The following subroutine lists this procedure.
NOTE
laRS may be used to better advantage. DECdisk Flag is
indicated in laRS bit 13.
PI

/Store the link, extend mode (PDP-9) protect and PC + I

JMP FLGS
lOT SKPA
SKP

FLGS

/Skip if device A flag
/Go to next device
1-23

FLGS (cont)
JMS DEVA

/Handle device A

lOT SKPB
SKP
JMS DEVB

/Skip if device B flag
/Go to next device
/Handle device B

DSSF
SKP
JMS DISK

/Skip if DISK flag
/Go to next device
/Handle disk

ION
JMP * PI

/Tum PIE on
/Retum to main program

For systems with API, the following instruction is required:
63

JMS DISK

/API setup

The program is now aware that the DISK flag has been set. To determine if a successful transfer has taken
place, read the status word into the AC by the DSRS lOT. ~C bit 0 is the logical OR of all significant error
conditions, and it can be quickly tested by the skip on positive accumulator (SPA) instruction. If no skip occurs,
an error exists; and the next step is to determine the error and take the required action. The following program
illustrates these points.
DISK

o
DSRS
DACSAVE
SPA
JMPER
JMP XFC
DBR
JMP I DISK

/Store PC + I, link, EXD (PDP-9) and protect
/Disk read status
/Save the status
/Test for an error condition
/Go to error routine
/Go to transfer complete routine. Set program flag.
/ API debreak and restore command

The API and PI subroutines normally differ in that the API is kept as short as possible so that it does not tie up
the API channel and hold up other devices. Techniques for programming the API are explained in its manual.
For simplicity, the same handler for both PI and API is used in this manual.
The error flags that cause an interrupt or API break can be classified into three categories, according to the action
that should be initiated upon their occurrence. HDW (APE and MXF) and timing errors such as BT, CT, etc.,
indicate hardware malfunctions; and, if they persist, the need for a Field Service Engineer. WLO and NED show
that either an operator error was made when the system was initiated, or that the data transferred exceeds the
capacity of the system to store it. This situation can be corrected by the operator. If WCE or DPE occur, the
program itself can take corrective action by checking if the error persists, and then rewriting the erroneous data.
Only if a parity error persists should the operator be notified.
The first two classes of error flags should be tested first. If they caused the interrupt (HDW, APE, and MXF;
WLO and NED), the program is stopped; and the status is left in the accumulator for the operator to interpret.
If the last set of errors occurs, further action can be expected from the program.

1-24

EXAMPLE:
ER

LAC STATUS
AND (346000
SNA
JMP REWRIT
LAC STATUS

/Get the status
/Mask out all but the first two classes
/Skip if an error occurs
/It was a soft error, go to rewrite
/It was a hard error, store the status and
notify the operator

Note that the error flags are arranged in descending order of importance so that they can also be tested by
successive RTL's and skips on link and SMA's.
REWRIT

/The parity error was discovered during a READ or a
/WRITE CHECK.
/The program can either halt, go back and repeat the
/operation several times to see if the error is still there, or
/go back and rewrite all the data that has been written
/erroneously and then retest it, or both.

1.6 PROGRAMMING WITH THE ADS REGISTER
The contents of the ADS Register reflect the current position of the disk surface. This information is available
to the program through the lOT instruction DLOK, and can be used to reduce the time it takes to transfer a
file between the disk and core memory. Consider the following example, which is illustrated in Figure 1-14.
Assume that a file 17778 words long is to be transferred from core memory onto a disk. Let the current
address (CA) and the word count (WC) be 20008 and the 2's complement of 17778 (1024 10 ), respectively.
Let address pointer 0 (APO) = 050000 and let address pointer 1 (API) = O. The function is set to WRITE and
the transfer rate to HIGH.
Assume further that after the calling sequence has been set up by the program, the ADS Register is read into the
AC and found to be set to location 6608. The program would then determine the nearest address that it could
begin transferring data, taking into account the amount of coding that must be processed before the start lOT
is issued, and the time it takes to switch tracks if a track must be switched (200 /ls), plus set up time. About
240 /lS or 15 10 addresses later is a reasonable figure. The projected ADS address (PADS) is 6778 in this example,
therefore.
The PADS falls within the area on the disk where the file is to be transferred. The program can now make one of
two decisions. It can wait until the disk rotates around to location 0 before it starts to transfer data, or it can
begin transferring the file at location 677 8 . One way to manage this is to divide the file in core into two sub files.
The first subfile will start at core location 2677 8 and transfer to disk location 677 8 . It will overflow 1101 8 words
later. The second subfile will start at the original CA location 20008 , transfer to disk location 0, and overflow
6778 words later. In this way, the file is transferred in one revolution in its proper sequence, and the time saved
from the previous method is approximately the time it takes for one quarter of a revolution.

1-25

TRANSFER RATE SET TO HIGH

660 8 ADS
6778 PADS

APO

.-.......

1 7778
(A) TH E FILE ON THE DISK

200°8

2676 8
2677 8

3777 8

(8) THE FILE IN CORE
09-0420

Figure 1-14 Calculating Fast Access Calling

1-26

The more general problem of calculating the two subfiles and determining the PADS address for all three transfer
rates is somewhat more complicated. Recall that the ADS Register does not give the adjusted address of the Disk
Segment Register during medium or low speed transfers. During medium transfer rates, this adjusted address can
be found by rotating the ADS Register (the 11 least significant bits) one to the right. During low speed transfers,
the adjusted address is calculated by rotating the 11 least significant bits 2 places to the right. The first address
for which this is done may not be an address that falls into one of the revolutions where the data is stored for this
file. The next address should be tried, and if the transfer rate is LOW, then the following two until either all four
Jfevolutions are exhausted; and the program concludes that the disk is not over the file area on any revolution, or
until a valid PADS is determined. The flow diagram of Figure 1-15 illustrates the process. Assume for example
that a PADS is calculated and falls into the section shown in Table 1-7. If the transfer rate is HIGH, then any
address from 74 to 105 is acceptable to test to determine if it falls within the file area. If the transfer rate is
medium, it is possible that only every second address belongs to the file. The second line converts the high speed
addresses to their appropriate medium speed address. If, for example, it is found that address 75 converted to
2036 does not fall within the data file, then the program must go on to address 76. Converted, this address is 37
to the medium speed transfer. It may be that 37 does fall within the file area, and the program can begin transferring its file at that point. If low speed transfer rates were used, then four addresses (one for each revolution),
may have to be tested for valid PADS points.
Table 1-7
Adjusted ADS Register for Medium and Low
Transfer Rates
Transfer
Rate
HIGH
MEDIUM
LOW

Address
74
36
17

75
2036
1017

76
37
2017

77
2037
3017

100
40
20

101
2040
1029

102
41
2020

103
2041
3020

104
42
21

105
2042
1021

1.7 PROGRAMMING MULTIPLE DISK SYSTEMS
Sequencing from track to track and disk to disk is program transparent except for the latencies that occur
when switching from disk to disk. The disks are not synchronized. The latency can be reduced by using the
ADS Register. Ensure that when the ADS register is read, the correct disk has been selected; i.e., that address
pointer 1 has been properly set up.
If API is set to a disk that does not exist in the system, or if the program sequences into a nonexistent disk

such as disk 9 in an 8 disk system, then an error flag is posted. Note that the eighth disk does not overflow
and wrap around to disk O.
1.8 USING DECDISK IN A SYSTEM
There are several points which should be considered when DECdisk is programmed into the system. DECdisk
is almost as reliable as the main core memory and considerably more reliable than industry compatible tape.
However, the disk should always be supported by another bulk memory unit, typically DECtape or industry
compatible tape. It takes about 30 seconds to fill a DECtape reel from DECdisk, and each disk surface fills
two such reels. Data files should be regularly dumped from the disk into its support memory, as the data files
are generated. How often this is done depends on the application; in most systems, this job can become a background activity except when very important files are under construction.
1-27

SET AP1
READ ADS

YES

GENERATE THE
FOUR POSSIBLE
PADS, ONE FOR
EACH REVOLUTION

GENERATE THE
TWO POSSIBLE
PADS,ONE FOR
EACH REVOLUTION

COMPARE EACH
PADS WITH THE
01 SK FILE ADDRESS

YES

USE THE INITIAL
CALLING SEQUENCE

ESTABLISH THE
CALLING SEQUENCE
FOR THE TWO
SUBFILES AND
BEGIN TO
TRANSFER

09-0421

Figure 1-15 Flow Diagram of the Subroutine That
Uses the ADS Register

1-28

DECdisk may cause one irretrievable error in 2 x 109 bits transferred. With most information, this is not a
problem. However, if the error occurs during the transfer of system software or the accumulation of a payroll
file, the result could be disastrous. For this reason, several error detecting technqiues have been devised. These
are listed with short explanations in Table 1-8.

Table 1-8
Disk Data Checks
Name

Explanation

Lateral Parity Checking

This test is automatically performed by the hardware each time a
word is read, written or write checked.

WRITE CHECK

This function checks the disk itself. It compares the file in core with
the file as it should have been written in memory. The checking is
done at the controller, however, so that consistent errors in the data
paths are not detected.

WRITE then READ

This technique copies the file onto the disk, and then reads it back
into core into a different area. The two files are then checked for
consistency. This technique tests the disk, the data paths, and core
memory itself. The overhead is high.

Longitudinal Parity Check

When a table or file is built, a longitudinal checksum is calculated
with it. Whenever the table is transferred, the checksum is recalculated and compared with the original. This technique tests the disk
and the data paths and core, but the overhead is very high.

Error Detecting and
Correcting Codes

Hamming codes that automatically correct some errors when they
occur can be generated for each word. The overhead when this is
done with software is usually prohibitive.

One additional short test can be run on a file after it has been transferred: Add the original word count to the
original APO and compare the result to the APO just after the transfer. They should be identical.

1.9 SUMMARY OF DECDISK CHARACTERISTICS
The following is a summary of the DECdisk System characteristics:
a.

Storage Information
(J)

fixed head

(2)

serial, random access

(3)

8 disks per controller

(4)

128 data tracks per disk

(5)

2048 eighteen-bit words per track

(6)

262,144 eighteen-bit words per disk

(7)

2,097,152 eighteen-bit words per disk system

1-29

System Transfer Rates
Three switch-selectable speeds:

16 JlS per word;
32 JlS per word;
64 JlS per word.

Protection
Tracks on ea(..l disk are protected from a WRITE operation in groups of eight (a total of
16,384 words).

Access
(J)

16.7 ms (average) when the ADS Register is not used

(2)

240 JlS if the ADS Register is used

Reliability
Six recoverable errors and one nonrecoverable error in 2 x 10 9 bits transferred. (A recoverable
error is defined as an error that occurs only once in four successive reads.)

Core Locations
Automatic Priority Interrupt - 63 on level 1
Data Channel
- 36 (WC)
- 37 (CA)

1-30

Chapter 2
OECdisk Modules

2.1 INTRODUCfION
This chapter provides descriptions of special modules used in the DECdisk system.
2.1.1 Types of Modules
DEC builds three series of compatible below-ground logic (the B-, R- and S-series), two series of compatible
above-ground logic (K- and M-series), an extensive line of modules to interface different types of logic (W-series),
a line of special purpose modules (G-series), and a line of support hardware for its module line (H-series).
With few exceptions, the DEC below-ground logic operates with logic levels of ground to -O.3V (upper level) and
-3.2V to -3.9V (lower level), using diode gates that draw input current at ground. Figure 2-1 shows the voltage
spectrum of negative logic systems.

OV
UPPER LE VEL { - O. 3 V
INDETERMINANT{- O.8V
- 2.0V
LOWER LEVEL{-3.2V
- 3.9V

~
~~
15-0070

Figure 2-1 Voltage Spectrum of Negative Logic Systems

The compatible above-ground logic generally operates with levels of ground to +O.4V (lower level) and +2.4 to
+3.6V (upper level), using TTL or TTL-compatible circuits with inputs that supply current at ground and outputs that sink current at ground. Figure 2-2 shows the TTL logic voltage spectrum.

UPPER LEVELi+3.6V
+2.4V
+2.0V
I NDETERMINANT
+O.8V
LOWER LEVEL
,

+ O.4V
OV

====b
15-0070

Figure 2-2 Voltage Spectrum of TTL Logic

2-1

The use of DEC's Digital Logic Handbook, 1970 edition, is recommended for readers of this manual who are not
familiar with the basic principles of digital logic and the type of circuits used in DEC logic modules.
2.1.2 Measurement Definitions
Timing is measured with the input driven by a gate or pulse amplifier of the series under test and with the output
loaded with gates of the same series (unless otherwise specified). Percentages are assigned with 0 percent indicating the initial steady-state level and 100 percent indicating the final steady··state level, regardless of the direction of change.
Input/output delay is the time difference between input change and output change, measured from 50 percent
input change to 50 percent output change. Rise and fall delays for the same module are usually specified
separately.
Risetime and falltime are measured from 10 percent to 90 percent of waveform change, either rising or falling.

2.1.3 Loading
Input loading and output driving for TTL Logic are specified in "units", with one unit equivalent to 1.6 rnA.
The inputs to low-speed gates usually draw 1 unit of load. High speed gates draw 1.25 low-speed units, or 2 rnA.

2-2

2.2 G08S DISK READ AMPLIFIER
Circuit Description: The G085 Disk Read Amplifier is a double-height module.consisting of an ac-coupled amplifier with a bandwidth (-3 dB) from 20 kHz to approximately 1 MHz, followed by a slicer (see Figures 2-3,
2-4, and 2-5). The maximum voltage gain (under potentiometer control) is approximately 60 dB (1000). Common mode rejection ratio is approximately 40 dB. The amplifier is insensitive to any power supply ripple voltage
less than 5 percent. Pin AM reduces the gain by approximately 30 percent when its input is low. The nonrectified slice output is gateable, and the slice point can be varied by logic inputs. A potentiometer is provided to
adjust the slice. Pins at AT and AV are provided as amplifier test points. Proper groundi~g is critical in this module. G085 ground pins should not be bussed. Pins AS and AC should be connected to analog ground, and BF
and BC should be connected to logical ground. All amplifier connections must be isolated from fast rise-time
signals.
Inputs:

Voltage levels are 0 and -3V, except at the input to pins AE and AF.

Outputs:

Function

Load or Input Voltage

AE,AF
AM
BU,BV
BS,BT
BP,BR

Read Head Input
Read Gain Control
Read Slice Control
Read Slice Control
Enable Output

approx. 15 m V peak-to-peak
2mA
2mA
2mA
2mA

Voltage levels are 0 and -3V except at AV, which provides +20V for the
timing track center taps.
Pin

Function

Drive

BE,BD

Signal Output

lOrnA

Input/Output Delay:

120 ns

Power Dissipation:

2W at +20V
I.SW at -ISV

Application:

The G08S module is used to detect and amplify timing tracks and data
signals for the disk systems RS08 and RS09.

AE
AV

BE
BS
BT
09-0357

BU
BV

Figure 2-3 G08S Disk Read Amplifier and Slice, Block Schematic

2-3

THIS SCHEMATIC IS FuRNIShED ONLY FDR TEST AND MAINTENANCE PURPOSES. THE
CIRCuiTS AflE PROPRIETARY IN NATURE: ANO SHOULO BE TREATED ACCORDINGLY
COPYRIGHT 1968 BY DIGIT .... L EQUIPMENT CORPOR .... TION

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UNLESS OTHERWISE INDICATED
CAPACITORS ARE 35V
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DIODES ARE 0662
TRANSISTORS ARE OEC3009B
R21,R32 ARE POTS 76 PR SOD HELITRIM
I/BW, 1% RESISTORS ARE 100MF

CHK~HALLER :;~
ENGS. SANBERT

TRANSISTOR & DIODE CONVERSION CHART

mamaama
••

D664

DEC65348

•

TITLE

DISC READ AJvP MD SLICE 0085

MPS6534B

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Figure 24 G08S Disk Read Amplifier and Slice, Circuit Schematic

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r--09-0392

Read Am \'f'
Figure 2-5Parts
Disk
LocatIon
. D'P.I ler and S\'Ice
lagram
'

2-5

2.3 G285 SERIES SWITCH
The G285 Series Switch is a single-height module consisting of two 4-input AND gates, each driving the base of
two driver transistors (see Figures 2-6, 2-7, and 2-8). When a gate is enabled, it in turn switches its corresponding
transistors that form part of the select and read/write matrix of the disk or memory.
Inputs:

Voltage levels to the gates are 0 and -3V. In levels to the signal inputs
Land Mare 0 and -15V.
Pin

Outputs:

Function

Load

D,E,F,H,S
T,V,M

Gate Enabling Inputs

L,M

Signal Inputs

I rnA shared among
inputs at ground

Voltage levels are 0 and -15V (i.e., the input signal gated through the
transistor). Each switch pole can drive up to 150 rnA. Reverse voltage
transients up to 100V do not destroy the switch circuits. Output pins J,
K, R, and P must be returned through the load to +IOV. The common
pins (L and M) to both sets of switches must be returned to -15V. The
switches will pass 1 MHz current. The voltage drop for 100 rnA is appro x, imately 1V.

L ---------------------~

o
E
F
H - - ' " " ' -_ __

s ----,."
T
U -------,~

V ---""-_ _.....

M ---------------~.-~

-p
09-0356

Figure 2-6 G285 Series Switch, Block Schematic

Input/Output Delay:

1 J.1.s

Power Dissipation:

1.5W

Application:

This series switch is used together with the G290, the G286, and the
G085 to form the Read/Write head matrix described in Paragraph 3.1"

2-7

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PuRPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT . . . 7 BY DIGITAL EQUIPMENT CORPORATION

RS
3;300
1/2W
5%

R7
3,300
1/2W
5%

RI2
100,000

100,000
K

RI4
3;300
1/2W
5%

Rle
3,300
1/2W
5%

RI7
100,000

IOV FOR DF32
+20V FOR RS08
RS09
RSIO

P
QIO

MPS
6531

NPS
6531

DI8

013
0870

019
D870

~--------------+-------~------------~~-----oL
L---------------------------------~------~__oM
Q9 MPS 81131
D4

o
03

F 0--.1--.

H o-__+--.

RI
IS,OOO
10%

C2
22 MFO
311VDC

R2
10,000
10%
DI8
0662

D20
0662

.----------r----~--------_+--~._--~----~--~C QND

CI
.0IMFD

R4
15,000
10%
UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W; S%
TRANSISTORS ARE OEC6S34B
DIODES ARE D684

..-----4--------..------------------_oB

~------------------------r_--------

1------------------1
c . u a _ ..

...

lEZ

.........

:::»

PARTS LIST IS A-PL-G285-0-0

Figure 2-7 G285 Series Switch, Circuit Schematic

-I5V

P
8
m::
n
05

BE v

BIB
D19

-.b

~
~

R11

R15

09-0391

.
Figure 2-8 G285 Series Switch , Parts Loca!"Ion DIagram

2.4 G286 CENTERTAP SELECTOR
The G 286 Centertap Selector is a single-height module consisting of four AND gates, each of which drives a
power output stage that applies a +20V level to its output pin when enabled by the gate (see Figures 2-9, 2-10,
and 2-11).

v
D -----cr-I--,.,
E ------CJII

F --.----c[J
H--r-...---c...1--.....-"
K --+--t--Cli-'--......
L --+--+----<

...

N --+--+-~rP --+--+--LI

s--I---1----rr-----L.-..,
T ---+--+-~u

u
09-0355

Figure 2-9 Centertap Selector, Block Schematic

Inputs:

Voltage levels are 0 and -3V.
Pin

Function

Load

D,E,K,L,N,P,
S,T,F,H

Gate inputs
Gate inputs

1 rnA shared among
inputs at ground in
each circuit

Outputs:

Each output is +20V when the AND gate is enabled and OV when the gate
is not enabled. Each output drives 150 rnA at +20V.

Input/Output Delay:

500 ns

Power Dissipation:

lAW

Application:

This module supplies the +20V read/write level to the coil of each head it
drives in the matrix. Refer to Paragraph 3.4 for a more detailed description.

2-10

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1967 BY DIGITAL EQUIPMENT CORPORATION

R6
10,000

RI2
10,000

(f.IOV FOR DF32
A S120V FOR RS08
+20V FOR RS09
+20V FOR RS 10
020
0662

RI8
10,000

017
0662

R27
10,000

019
0662

C
R26
10,000

oo-----1~1t-I
Eo----IIH

RI
15,000
5%

GND

R2
15,000
5'!1t

R7
15,000
5%

R8
15,000
5 '!It

RI4
15,000
5%

RI3
15,000
5%

R20
15,000
5%

R21
15,000
5%

35V

'13
V
CI
.01
MFD

018
0662

B
-15V

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W; 10%
DIODES ARE 0664

1------------------1
.......

......

z: ....

K~:lEZ

......

~::I>

PARTS LIST IS A-PL-G286-Q-O

EIA

2NS009
NONE

IIPsallS4
IN6411
INS606

litO-DOmD

~=====I=====l~ ~

TRANSISTOR & DIODE CONVERSION CHART
DEC

DECS009.
MPS6531
DEC6I1S4.
D6n
0664

DEC

EIA

f - - - - - t - - - - - - 1 E QUI P MEN T

TITLE

CENTERTAP
SELECTOR G286

SIZE

f - - - - - t - - - - - - 1 COR P 0 R A TI 0 Nf-l-B---1---'------r-r-T----r-r-r-Lr--,----i

Figure 2-10 G 286 Centertap Selector, Circuit Schematic

8 8 §§ 8

R27

D20
R12
RII

I RB

RIO

0 8
G 18 8
8Bj G
RIa

B8
8I I
88
R4

RI3
RI4

R17

RI6

R25

DI7

R20

R24

R23

R22

R21

R19

8
8
8

G286

09-0389

Figure 2-11 G286 Centertap Selector, Parts Location Diagram

2.5 G290 WRITER FLIP-FLOP
The G290 Writer Flip-Flop is a single-height board containing one JR flip-flop driving two AND gates and two
power drivers. There are several gates to the input of the flip-flop (see Figures 2-12, 2-13, and 2-14).

K -+---~~
J -+--"--~JI
N ---;-~----~r--~-~'-~_~

___

~--F

L - -........-~
M ---L-J

o ~---+--+--e~UI

'---r--"

"","~--F

U---L-J

s
09-0354

Figure 2-12 G290 Writer Flip-Flop, Block Schematic

Inputs:

Outputs:

Voltage levels are 0 and -3V.
Pin

Function

Load

N,M,T,V,
L
S
K,J

Inputs to flip-flop
Input to flip-flop
Direct Clear
Enable input to out;put driver gate

Each gate is almA
load shared among
its grounded inputs

The E and F outputs are -15V or an open collector. The P and R outputs
are 0 and -3V.
Pin
E,F
P,R

Function
Output to G285 Series Switch
Test output of flip-flop

Drive
150mA
lOrnA

Input/Output Delay: 90 ns
Power Dissipation:

Application:

This module supplies the -15V write voltage to the G285 Series Switch.
Details are given in Paragraph 3.4.

2-13

~~H~J~~~ ~~~T~~~~:I~ ~:~~HI~~D ~i;!~YR ;o:~ ~ E;:JAL~~ ~~! ~ ~~~;~;~;~;:gl~E~l y~H EI
COFYRiGHT " •• BY DIGITAL EQUIPMENT CCRPORATlON

.
i

~~~~t'M

RIO

RlI

~e~:i'L

---<: A +10'1
R27

Rill
046
029

t-----o N

t 028

Oll

~I~:;~ S

,---~~----,-~------------+-~~~----------~----------~----oC GNO

042
021

RI3

R22

R21

R23

L - - - - -____________......._ _ _- - - -.......- -.......----------------------4o-----0 B -llIV

~i~:~ U o-__D.iH ...-.1 t.-.......-40•17_ _ _0 T ~~;~
C2

*08
I

016
0506
0408
03,07
01 02
RI9,R24
R!6
RI5 R27
RI4 R28
R25, R26
: R7, R8,R13,R17,R18,R20-R23,
RlI,RIO
I RI-R4,R6,R9 RII,RI2
1037,039,040,041,043
1014 Dill 024025031-034
: 035, 036, D3B,D42,D44-D.:~

,~! ~~3 D~
-C

150211111
11I03409-01
1503100
11505321
1300229
1300170
1300481
1300439

TRANSISTOR OECI008-S
TRANSISTOR OEC6534B
TRANSISTOR OEC3009B-S
TRANSISTOR 2N4258
RES. 100 114W 5% CC
RES. 10
114W 10%CC
RES. 10K 114W 10% CC
RES. 3.3K 1/4W 5% CC
5% CC

1300391

RES. lOOK 114W 5% CC
RES. 7.5K 114W 5% CC

1302466
1301422

I DIODE 0662

1100113

1.5K 1/4W

! RES.

iDI.ODE 0664

1100114

0~!.:!l~AP:-"5"6-t.l;-M~F:,.--~10;0~V~5~%~~D-.~M-;::,..-=-~~-=--1~0~OO-;0~1~2~-_-j

- 023,
--_ .... --- --.....---- - -CA-P.--Z20MMF 100V 5% D. ....

1000021

CAP.

1000079

47MFD 20V 20% S.TANT

I PARTS

REFERENCE DESIGNATION _
DRN

TRANSISTOR & DIODE CONVERSION CHART

LIST
A-PL-G290-0-o
____ DESCRIP_!lQ.tL____----'----'P-"A-'-'-RT-'----"N~O.~
PARTS LIST

~~tK·~~_~"-:zlj~~~T~~E_.~,lbo~68~2~i,N~84f5;~0£~C~,O~o.~'~3 mamaom

TITLe

WRITER FLIP FLOP G290

=H====t===::j ~g~~;R~~I ~ ~ S~E C~~E 90:UO~~

~EN~~?-"'""'---l~1~~T!~,
~-1~~~:4~8:~5.~::m~~~~e~:;".;8
PROD
DEC30098 2N 3009
O£C6514B

"PS6~34

Figure 2-13 G290 Writer Flip-Flop, Circuit Schematic

R1
D21

R12

Rl'

D30

D27

R16

Rl0

I
I

D34

D26

D14

D31
D24

II D13 I

R15
R27

r R5 I
R14

D28

8
8

R18
C7
R2l
Cll
R25
D4l
D40

R23
R20

D37

D38

D43

D35
D36
D46

D23

~8 8

D44

II D45 I

I Dl0
I
I R3
II
II

I I D22 I
R8

II D1S I

R28

D29

D25

D32

Hila B
D15

D33

8
8

C9
R 22

D39

D42
D19
D20
Dl1

R26
R17

R24
R19

R6
R13
D12
C2

D17

I
I

m
D8

Figure 2-14 G290 Writer Flip-Flop, Parts Location Diagram

G290

09 - 039 0

2.6 G681 B TRACK MATRIX
The G681 Track Matrix is a single-height board containing the resistors and diodes for eight DECdisk read/write
heads (see Figure 2-15). A complete description of the G681 's use in the read/write circuitry is given in Chapter 3.
2.7 G711 RFOS TERMINATOR BOARD
The G711 RF08 Terminator Board is a single-height board containing 15 terminating resistors that present loon
to ground at each input pin (see Figure 2-16).
Inputs:

loon to ground

Outputs:

None

Power Dissipation:

Approximately 90 mW per terminator

Application:

This board must plug into the output cable slot of the last RS09
on each DECdisk cable bus.

2.S G775 INDICATOR PANEL
The G775 Indicator Panel is a connector card that provides isolation for logic levels and allows these levels to
directly drive indicator bulbs without using light drivers (see Figure 2-17). The connector is designed to be
used with the indicator panel, which supplies the necessary bias voltage.
Inputs:

All inputs are 0 and -3V with 3 units of load each.

Outputs:

The output connects a Flexprint cable to the indicator board.

Power Dissipation:

150mW

2.9 G789 SIGNAL SIMULATOR CONNECTOR
The G789 Signal Simulator Connector is a connector board for Flexprint used on the RF09 side of the headsimulator cable (see Figure 2-18).

2-16

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1967 BY DIGITAL EQUIPMENT CORPORATION

I
PAD CONNECTOR
P-

(I
()

3
()

~~DI

"
JI

0--

D2~ ~~ ~D3

D4~

~~ ~ 05

o <;>

()

0--

)

.........0

0--

D6~ ~~ ~ D7

D8~ ~~ ~ D9

)

~4 l~

RIO

RII

1 R"

DIO~ ~~ ~DII

O--~

D12~

~~ ~D13

R" 1

16 \

R<51

RI4

0--

RI6

.........0

0--

D14~ F:~ ~ DI5

DI6~'
A2
62

1------------------1
c

•

..,Q

...

z _ ¥ ... l z . . . . . . . .

:I>

I DIODE 0672
I RES. 750 I/SW 1% 100 MFP

01 THRU 016
RI THRU RI6
REFERENCE DESIGNATION

<t '"
~~ r-- -;

Q~ "',.,
~(!J g 8 8
c
> J:

5~~ ~
~~

DRN

DATE

?n.~

1l-·1.7-!i.

CHK'D

DATE

I~NG/' /"
IPROD

/
lj.'

D;;;.~;:.
IDATE

TRANSISTOR & DIODE CONVERSION CHART
DEC
EIA
EIA
DEC
0670

IN3653

1105275
1302955
C-UA-G6SI-0-O
PART NO.

I PARTS LIST
DESCRI PTION
I
PARTS LIST
TITLE

MATRIX G681
~DmDDmD 8 TRACK
I I

I R~
101 1 1 I 1 1 1

EQUIPMENT SIZE CODE
NUMBER
CS G6SI-O-1
CORPORATION B
MAVNARD, MASSACHUSE.TTS
PRINTED CIRCUIT REV.
3'
~ j r, i
I

1]1)

Figure 2-15 G681 Track Matrix, Circuit Schematic

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRiGHT 1968 BY DIGiTAL EQUIPMENT CORPORATION
I

GND
C

E
~

I
I

(

rr r
RI

, R2 , R3

>RIO

RII

R 12

RI3

RI4 ~ RI5

~ 1- RI5

REFERENCE DESIGNATION

iRES. 100
1/4W 5% CC
IPARTS LIST
DESCRIPTION
PARTS LIST

Figure 2-16 G711 RF08 Terminator Board, Circuit Schematic

1300229
IA-PL-G711-0-0
PART NO

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES, T, HE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

R2
AI

-'\/\J'.
CI

R58

J\~4~
V

R37
vv

R55

1
1
1

-{)

R57

R44

R20
VV

R41

~
I

100

R64

R63

LI~

R48

~
R478
I R66 MI~
~

R657

~ NI:-l~
R49

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 3K, 1/4W, 5%
NUMBERS IN PARENTHESIS ARE FOR
FLEXPRINT CONNECTOR 2
WHEN USING ONLY ONE FLEXPRINT
CABLE I SIDE 2 MUST BE USED
0---0 INDICATES JUMPER

RI A
v

R3
1 J\rV\,

(2)

.:0

RI9
(3)
C2o----+---'\1\1\
R21
1 J\r\.tv
1 J\~
E2"D2v

R26

vo-_1.
.......
1

Ii 2",

(4)
-{)

(5)
-{)

V2~\r_-~_06)

-J\,\/RA'V

(7)

J\ I\J"v

-{)

1~
J2~
R25

(8)

(9)
(10)

RIO

J..

JOy V

~v------,

B2v

46JI~

+5V

~
R4313
I R62 HI~
~
_R_6~
12
R45

A2v-

R59

o-__4_--"\.fV'v---{)Q
Bi~
"V'V\/"
~

R40

+5V

FLEX PRINT
CONNECTOR I

K2v

J\ R28

- --Q--()

L2~)

R30

M2v-

.. ~

A
V

RII

-.-

"vA

v v

R32

(12)
-u

R29

(13)

RI3

(14)

~vvv--u

~
R31
(15)
i
RI6
R2~

~~_Ji~

Rl~

R51
SI ~O-_ _~"V\v.I'v-v-o

R70

,.. -'\/\J'.
I
!

R54

1
_

~6~
V

-0

R532
~
R72

R71

VI~

IDR~A' ',' i' 'c

DAr~

j-O /Y'd

!~D;},rJr:rr ~Jt.U9

lE!JfrL

IPROD

"",,"'

n;;M
DATE

~
I

R34

RI8

RI5

(16)

R33

(17)

S2~

~
i

FLEXPRINT
CONNECTOR 2

T2~

~I
.,RI177 ('!C8)
{
I R36
U2~

TRANSISTOR & DIODE CONVERSION CHART
EIA
EIA
DEC
DEC

R35

(19)1

V2~J

~DmDDmD

TITLECONNECTOR CARD
INDICATOR PANEL

EQUIPMENT SIZE
CORPORATION B
""',AVN"''''D. ""''' • • '''CMUSETTS

Figure 2-17 G775 Connector-Card Indicator Panel, Circuit Schematic

ICODE
I
CS

PRINTED CIRCUIT REV

NUMBER

G775-0-1

G775

I ~v

IAlslc I 1 1 11

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THEj
'CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 196B BY DIGITAL EQuiPMENT CORPORATION

R4
'VV\,

FO
R3

H""

~
10

J "

- >-

FLEXPRINT

II,...
~

K ......

N
o

12,...
13,..

14,...

15
16

M'"'"

t ::~

------------------1
"

.....

....

:z:. ...

z ........

:;0

RI - R4

REFERENCE DESIGNATION
>

'"
Zo f--r0
UJ~

DRN.

?>?~

DATE

''''-I
....'
DATE

15J;~/>IL V-g·L~

>:1:

EK'&-t~n(!) ~~'"/

UJ", 0
0

..,~

PROD.

DATE

TRANSISTOR & DIODE CONVERSION CHART
DEC

EIA

DEC

EIA

13048~
I
I A-PL-G789-0-0
PART NO.
I

IRES. 316
1/8W 1% MF
IPARTS LIST
DESCRIPTION
I
PARTS LIST
TITLE

momoama I I

SIGNAL SIMULATOR
CONNECTOR G789

EQUIPMENT
CORPORATION

SIZE

CODE

MAYNARD, MASS .... CHUSETTS

PRINTED CIRCUIT REV

Figure 2-18 G789 Signal Simulator Connector, Circuit Schematic

NUMBER

G789-0- I

IR~V

IAI I I I I I I

2.10 G790 SIGNAL SIMULATOR GENERATOR
The G790 card is on the RS09 side of the head-simulator cable. The card consists of 4 transformer networks
that accept the outputs of the maintenance flip-flops and convert their transitions to signals that resemble the
signals from the read heads of the disk assembly (see Figure 2-19).
2.11 G821 REGULATOR CONTROL
The G821 Regulator Control is a single-height board serving as a voltage regulator that supplies +5 Vdc to the
TTL logic of the timing track writer. It is capable of supplying a maximum current of 6A, provided it is supplied
with an air circulation of at least 200 cfm. Without cooling, the G821 is rated at 2A. This module was designed
to be used with the PDP-IS memory and incorporates several features specifically serving the PDP-IS memory.
For example, it supplies a IA driver that is enabled when a memory OK signal is returned from memory. However, this feature is not used by the timing track writer.
Inputs:

Ordinarily, the inputs are rated at 8 Vdc, II V dc, and -15 V dc supplied
by the PDP-IS power supply. However, the timing track writer uses
+ 10 Vdc and -I 5 V dc.

Outputs:

The timing track writer uses the regulated +5 V dc output. This output
can be varied between 4.5 and 5.5 Vdc by a potentiometer on the module.
At 5 Vdc the regulation is 2 percent with a ripple of 25 mV peak-to-peak.
The circuit schematic is given in Figure 2-20.

2-21

THIS SCHEMATIC is FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. ThE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1968 BY DIGITAL EQUIPMENT CORPORATION

"..

0 3
4

0
0

< 0

0"
12
-13

",-17

1"
t" 1
J
R6

",16

RII

::r:

R20

C2
~

~JI
~ E2
~KI

RI9

~ F2

~ g;J :::
~ ~a~;
RI7

,
; RIO

~
~
TI

c R9

~T2

~ ~
~ ~

RI4

_ U2

1
RI3

",18

TI - T4

~3 -R20

r-,-------- .

R9-R12
R5 -R8
RI- R4
C5 -C8

CI-C4
REFERENCE DES IGN ATION

~ '"

~~ I-="f0

Qz
cJ')o
I

~ D2

~
~

~
~
T3

::!'C3

RI2

*C8

FLEXPRINT

'1 R~
C4

0
0
0

5~r,
~

~N.~

~'J;/.,:,
ENG

,J ~ •
PRO'D

DATE

/0-2-68
DATE

('.13(',,,-

., DATE
" ,,!
DATE

TRANSISTOR & DIODE CONVERSION CHART
DEC

EIA

DEC

EIA

TRANSFORMER T-2006
RES: 750 1/8W 1% 100MFP
RES. 330 1/4W 5% CC
RES. 30K 1/4W 5% CC
RES.
IK
1/4W 5% CC
CAP. 330MMF 100V 5% D. M.

5200645
1304805
1300295
1302394
1300365
1000023

CAP. 82MMF 100V 5% D.M.
PARTS LIST
DESCRI.PTlON
PARTS LIST

1000015
A- PL-G790-0-0
PART NO.

TITLE

SIGNAL SIMULATOR
GENERATOR G790

EQUIPMENT
CORPORATION

SIZE

CODE

MAYNARD. MASSACHUSETTS

PRINTED CIRCUIT REV

momoomo I es I

Figure 2-19 G790 Signal Simulator Generator, Circuit Schematic

NUMBER

G790-0-1

I R~V

leI I I I I I I

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

r---~--------

__----__

---'~--

R4
.1
5W
R5

I 3

RI3

100

I. 5K

RI6
IK

BNI

~~4W + ?50

+IIV

I 5

I cr-+--+--....6

BPI

MFD
20V
10%

R27
330

R24
330

BM 2

I 70-+-+----'

RII
IK

RI5
IK

I
L __ J
BR I --1H---'<---:--

R25
330

DI
2N
'4441

R2a
IK

~~~~~--~~----~------~.-----~--

+
-15V

~~~ ~~_ _ _ _ _ _':"::"':_ _ _ _-1

C9
10MFD
20V
10%

Cii

3/4W
Ria
IK
GND

AC2,AH2
AK2,AL2
ATI,BC2

__----e-----e----e----....------~.---~.---__----e---__------__------~~~~~----BD2,B~
BK2,BL2

UNLESS OTHERWISE INDICATED
PIN 7 ON EI=GND
PfIII4 ON EI=t5V
E I IS DEC740 IN
E2 IS LM300
CAPACITORS ARE IMFD,35V,10%
DIODES ARE D664
RESISTORS ARE I14W 5%
R3,R17 ARE POTS .76PR
TRANSISTORS ARE DEC3009B

BTl

DEC
0
0
0
0

HI-4I~--< IK

CIO

TRANSISTOR & DIODE CONVERSION CHART

en
z

RI7

RI9
IK

R7
47

AB2

ABI,ACI
ADI,AEI
AFI,AHI
AJI,AKI

C7
56MMF
100V
5%

,l...t-----<....."'R3

I
I 4

BBI,BCI
BDI,BEI

Ali

~~Kl

I I

I 2o-T-~~~~--~<
I

RIO

(+SEN)
ASI

r--

+5V

--~~--~--~'-----------~~--AA2,B~

0664
0672
I N748A
CEC3009B
OEC6534B

EIA
IN3606
IN36
SAME
2N3009B
MPS6534

DEC
2N2904

SAME

2N3055

NONE

~DmDDmD

EQUIPMENT
CORPORATION
MAVNA"O, M .... SACHU.ETT.

Figure 2-20 G821 +5V Regulator Control, Circuit Schematic

TITLE

+5V REGULATOR C(J\JTRCL G821

2.12 M104 MULTIPLEXER MODULE
The M I 04 Multiplexer Module is an M-series single-height module that contains a single multiplexer subsystem
(see Figures 2-21, 2-23, and 2-24).
Inputs:

Outputs:

Input Pin

Load (Units)

H2
S2
HI
E2
NI
F2
K2
S2

2.5
I
6
3
I
1-1/4
68n Termination
I

The output gates can drive as follows:
Output Pin

#Loads It Can Drive

U2
J2
PI
Sl
EI
FI
M2

8
9
10
10
10
PDP-IS I/O Bus Compatible (30 units)
7

Power:

Application:

The M 104 module has been designed specifically for positive logic controllers of PDP-9 or PDP-IS peripherals. It is used in all controllers that
make use of the API or data channel facilities in the I/O processor. It
accepts a request from the controller logic at its FLAG (1) H input and
synchronizes this request to the I/O SYNC H pulses issued from the I/O
processor. These pulses are fed into SYNC of the M I 04 and immediately
set the REQ flip-flop. The REQ flip-flop can be monitored through pins
J2 and U2. The I/O processor responds to a request with a GRANT, and
ENA is set. This flip-flop is generally used to gate any address information
onto the bus; e.g., the API trap address or the word count address of the
multicycle data break. The next SYNC pulse sets ENB. This flip-flop is
generally used to control data-gating and transfer direction; e.g., device
selector enable and RD RQ.

2-24

EN IN H

~-------=D-----1~>----------"""O
+"V'
REQ (0) H

EN OUT H M2

LEVEL CONVERTER

ENB

ENA (1) L SI

0
HI

ENA (1) H PI

SYNC H

0
ENB (1) L Fl

MI04
MULTIPLEXER

ENB (1) H El

0
REQ (1) L J2

0
REQ(1 ) H U 2

O~-----------+------------1----------'--~

GRANT H

u----_e_-------{)

CLEAR FLAG L J I

LJ
30-200n5

PWR CLR H

O~-------~~;
Jf.~--+--;JI

REQ

C
F2

CLR REQ L

o
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _

--Q

FLAG(1) L S2
15-0088

Figure 2-21 M 104 Multiplexer, Block Schematic

2-25

The REQ flag can be reset through pin F2 (CLR RQ) by the controller
logic. Pin NI should be tied to POWER CLEAR or its equivalent.
The enabling level ENABLE IN holds REQ off if it arrives as a negative
level. When REQ is set (if ENABLE IN is positive), ENABLE OUT goes
negative and the next peripheral on the bus receives it as a negative
EN ABLE IN. In this way the M I 04 est·ablishes priorities among devices
on the same API level or among devices that use the data channel. A
timing diagram for the M104 is given in Figure 2-22.

I/O SYNC

1
0

REQ EN

1
0

REQ

GRANT H

* 01

CLR REQ

ENA

1
0

ENB

1
0

*Jl IS ASSUMED TO BE WIRED TO F2
15 -0087

Figure 2-22 M104, Multiplexer Timing Diagram

2-26

C8
100MMF
100V, 5%

L-H

EN IN H

CLR FLAG L

L~
10~

8
2

I
I

1 +3V
1

f"1 f" H=l

R4
470
8

o r----<I-- J2

E4
REQ
12

r
D

K2~

~U2

DL2

II 100 ns

1
1
L

Rl1
220

_ _ Jl

GRANT H

----

PWR CLR H

~ ~

UN LESS OTHERWISE INDICATED
CAPACITORS ARE 01MFD,100V,2%
RESISTORS ARE 1/4W,5%
El,E4 ARE DE7474N
E2 IS DEC7400N
E3 IS DEC74H40N
PIN 7 ON EACH IC=GND
PIN 14 ON EACH IC = +5V

1"8

R8
1K

R9
IK
DLI

II lOOns

1
1

~I
13

+3V

_..J

L>;;PI

11.---ll..:.:8
C
0

+5V
A2

C5
6.8 MFD
35V,20%
- +
\I
/I

Rl
330

R2
750
GND
C2,TI

EI
EN8

EI
ENA

r---- - - - - -

~r-l~
3 C
0 6
2

'F' '20500°:.~t%

IR
K l;-Y

RIO
470

I - C 0E4
I
2
5
D

R3
82

RI2
IK

I
1

I
E2

r------ ------

I
FLAG H

R5
68
1/2W
5%

R7
470

IO SYNC H

EN OUT

E3 " ' 6

12::1

DEC30098

R6
220

'..h

rP)Ql

5
I t------- S I

Figure 2-23 M104 Multiplexer, Circuit Schematic

E1
C7

II
I

R1
R2

DELAY 1
R9

R10
R11

E2
R3
R4

C9
R5
N

N
00

8
R6

DELAY 2

R12

R13

;.4;04

15-0134

Figure 2-24 M104 Multiplexer, Parts Location Diagram

2.13 M216 SIX FLIP-FLOPS
M216 is a single-height module containing six D flip-flops (see Figure 2-25). All flip-flops operate independently
except for their clear line, which is shared among three flip-flops.
Data must be present at the D input 20 ns before the clock pulse and should remain 5 ns after the leading edge of
the clock pulse has passed the threshold voltage. The flip-flop settles in 50 ns. The CLOCK, DIRECT SET, and
CLEAR inputs must be present for at least 30 ns.
Inputs:

Voltages are standard TTL levels.
Pin

Function

Load

BI ,D2,HI ,L2,NI ,S2
CI ,E2,J 1,M2,PI ,T2
Dl ,F2,KI ,N2,RI ,U2
AI,K2

C Inputs
D Inputs
DIRECT SET
DIRECT CLEAR

2 units
1 unit
2 units
9 units

Outputs:

Voltages are standard TTL levels. Each output is capable of driving
10 unit loads.

Input/Output Delay:

50 ns

Power Dissipation:

435mW

2-29

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1987 BY DIGITAL EQUIPMENT CORPORATION

I
+5V - - - - A2
NOT USED -15V - - - - B 2

DIRECT

CLEAR ~
AI--

I', 1'.
0

EI
C

1
BI

DIRECT
4 SET
01

..12

\6
10

D
2

I" r

13J 0
1<2

1 C

~o E3

10
N2

15
I

RI
0

1
KI

D
3

1
HI

..I I

Vje

VI:

ICI

lc2

T I

+5V
C3
GND

10
U2

12
1
NI

~O E2

112

15
I

GND - - - - C 2 , TI

Rfe
19
I

112

NOTES:
PIN 7 ON EACH IC = GND
PIN 14 ON EACH IC = +5V

I INTEGRATED CKT. DEC7474N

EI THRU E3
CI THRU C3

I CAP•. 01 MFD 100V
1PARTS LIST

REFERENCE DESIGNATION

I
PARTS

DRN.

G:; CI CD

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TRANSISTOR & DIODE CONVERSION CHART
DEC

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DEC

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~
PROD.
DATE

5~~

DATE
L(·/~~

Figure 2-25

M2l6 Six Flip-Flops, Circuit Schematic

EIA

20% DISC

DESCRIPTION
LIST

1905547
1001610
IA-PL-M216-0-0
PART NO.
I

TITLE

M216
~DmDDmD SIXI FLIP-FLOPS
I

EQUIPMENT
CORPORATION

SIZE

CODE

MA,VNARD. MASSACHUSETTS

PRINTED CIRCUIT REV

NUMBER

M2IS-0-1

I R~V

lei I I I I I I

2.14 M311 TAPPED DELAY LINE

M311 is a single-height board containing two tapped delay lines (see Figures 2-26 and 2-27). Each delay line has
ten taps, providing fixed delays from 25 ns to 250 ns. An input NAND gate to the delay line provides an additional delay of IOns. Input impedance of the delay line is loon at ±5%.
Inputs:

Voltages are standard TTL levels. Input loading is 1.25 units.

Outputs:

Voltages are standard TTL levels. Each output can drive 1.25 units.
Maximum total drive is 6 units. Wire lengths should be kept to a
minimum (less than 6 inches).

Input/Output Delay:

Power Dissipation:

Delay

K2,J2
L2,KI
M2,Ll
N2,MI
P2,Nl
R2,Pl
S2,Rl
T2,Sl
U2,UI
V2,Vl

35 ns
60 ns
85 ns
100 ns
135 ns
160 ns
185 ns
210 ns
235 ns
260 ns

850mW

g~-------->T< : : : : :)
J2

09-0353

Figure 2-26 M311 Tapped Delay, Block Schematic

2-31

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

r-----------------------------------------------~~~---+5V
RI

lc,

-------,

100

.01 MFO

02.....:........r----.....

,~1~1~0~0r__.--4_--e---~~~1

E2
F2
H2----...___"
R2

------,

100

CI - " : ' . . . . r - - - ,
01
EI

I
~~~~~~~~~I
I

100

FI - - . . .___"

UNLESS OTHERWISE INDICATED:

Ei is DEC 74H40N
DELAYS ARE 0-250NS IN 25NS STEPS
RESISTORS ARE 1/4W 5"10
PIN 14 ON IC =5V
PIN 7 ON IC = GND

TRANSISTOR & DIODE CONVERSION CHART

~D.DD.

§rt~~ffi~J t=~DE~C~t~EI~A~t:jD~EC~J:~E~IA~~~ W ~D
I"I,,,/~... "----_+----H----_+---_l E QUI PM EN T

TiTLE

TAP DELAY M311

~~"--'-'''::''-~~'+i 1-----1-------11-----+------1 ~~!!:_~.~4~~~<;.~ I-----L---L----T-r-T--r-r--r-Lr-....--I

Figure 2-27 M311 Tapped Delay, Circuit Schematic

2.15 M149 9 X 2 NAND "WIRED OR" MATRIX
The M 149 is a single-height module containing two sets of 9-open collector NAND gates wired together in an
OR function to form nine output pins. The M 149 also includes a pulse amplifier (see Figure 2-28).
Inputs:

Voltages are standard TTL levels. Input loading is I unit per input.

Outputs:

Voltages are standard TTL levels. Each output except VI is an open
collector that can sink 16 rnA. The output at V I can drive 10 unit
loads.

Input/Output Delay:

10 ns at output

Power Dissipation:

350 mW

Application:

This module is generally used to gate signals onto an open collector bus.

2.16 M500 NEGATIVE RECEIVER MODULE
M500 is an M-series single-height module containing eight I/O bus receivers that can accept negative logic levels
and convert them to positive levels (see Figures 2-29, 2-30, and 2-31). Each M500 receiver has a negative input
clamped to OV and -3V. The threshold switching level is -1.5V with an 'input current of 100 /lA.
Inputs:

Minimum input impedance at OV: 30 kQ
Maximum current load to bus: 100 /lA
Inputs are standard negative logic levels of 0 and -3V.

Outputs:

Fan Out Output No. I: 12 units
Output No.2: II units
Input/Output No. I delay: 50 ns
Input/Output No. 2 delay: 40 ns
Outputs are standard TTL logic levels.

Power Dissipation:

750 mW max from -15V
800 mW max from +5V

Application:

The M500 module was designed to receive PDP-9 I/O bus signals
for devices using positive logic. It provides a high input impedance.

2-33

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT _
BY DIGITAL EQUIPMENT CORPORATION

lr----------------------_.--CI
AI

K2
H2------1f--..!:..!

D----------+------------_.~F

l---t--....=..j

t/---------+-------------_.-- F 2
~

N2
L2---t--~

D----------+-------------......--II: I

SI
PI ---t--.:..::.;

......--S2

rr--------~------------

P2------"'i
V2----+-------------------CY

U I ----t---=.j
RI
330
+3V
UNLESS OTHERWISE I NO ICATED·
PIN 7 ON EACH iC = GND
PIN 14 0111 EACH IC =+!5V
E I, E2, E4,E!5,E6 ARE DEC740lN
E 3 IS DEC7400N
RESISTORS ARE 1/4W 10%
CAPACITORS ARE .OIMFD,100V,20%
TRANSISTOR & DIODE CONVERSION CHART

<J)

z
o

~
a::

o
o
o
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0.0

11•••

~~=~§fi=:JI~~D~EC=t:~E~IA::;~:gD~EC=4=~E~I"~_WII ~
.

I.-------+------t 1_------+----------1 E a U I P MEN T

TITLE

9X2 NAND WI~T~90R MATRIX

~~.c~~~~I~------~-----4rr------------++------------~~£:~~~~.~A~~~~~I-~--~------~-r,-~~~-r,

Figure 2-28 M 149 9 x 2 NAND Wired OR Matrix

H1
H2

R1
K2

S2
S1

Ml
M2

Ul
V2

15 -0073

POWER

...

A2---+5V

4 - - - - C2,T1 - - GNO

Figure 2-29 M500 Negative Receiver, Block Schematic

2-35

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD 8E TREATED ACCORDINGLY.
COPVRIGHT
BY DIGITAL EQUIPMENT CORPORATION

'9"

A2
+5
..

"f"

~. ~. ~. ~. ~ ~. ~.
~ 1
1
~
i
1
R4
1.5K
5".

~5K

~~010

,~" ~

.~.'~

~~D2
R2

~~08

H.~

£?

R5
~Q3

~" ~~

~~03

~~Oll

R8
KQ5

~ ~06

~, ~" ~
~09

R27

R28

R29

-1.5V

>;~.

R6
3K
5%

R9
3K
5%

~M2

~ ~012

~~,
RI2
3K
5%

~'025

~~022

l~.'~

RI4
~Q9

~015

R31

t--S2

J.. 021

"~017

R20
~QII

~~ ~

R25
1.5K
5%

C5
6.BMFO
35V

+3V

~,,019

~~020

RI5
3K
5%

....l

~,:

~" ~ ~"'
~018

R21
3K
5%

'-0662

C9 i'-

~(~2

~, 028

0662
GND
C2. F2.
J2, L2,
N2,TI

... ~ 023

RI7
~Q13

-3V

D662

~'026

~~014

RII
KQ7

_H2

r"C6

V2_

T2 .......

,.M

SI_

PI-

+3V

~~Ol

R22
15K
5%

RI6
1.5K
5%

RI9

15K
50/.

MI---4

RI3
1.51<
5%

KI_

HI~

fC3

RIO
1.5K
5%

01--<

1.5K
5%

~ [024

R32

fi
QI5

, ... C8

~'~2

QI6

~~~

R34
-1.5V

RIB
3K
5%

~~~~2

R24
3K
5%
-3V

- 1.!lV

~~gM2
R26
1.5K

5·'0

UNLESS OTHERWISI;.'triOICATEO;
TRANSISTORS ARE OEC30098
DIODES ARE 0664
RESISTORS ARE 114W,10%
IC·S ARE OEC74HOON
PIN 7 ON EACH IC=GNO
PIN 14 ON EACH IC = +5V
CAPACITORS ARE .01 MFD
RESISTORS ARE 470

Figure 2-30 MSOO Negative Receiver, Circuit Schematic

82
15

R27
02S
:J26
"128

:;2 7
R29
D28
R30
J29
P 31
N

D30

-.....l

R33

l)31
R32
E:32
P34
C7

0 Q

00
80
88
G8

R25
R26

I
RE

°8
G

RI
R2

06
R7

I
RI'i

I
R21

RIO

I R14

012
RI3
015

R17

I R23

07
08

II DI

018

Oil

014

DI7

D20

013

I
02 ,

R 22
024

016

010

I
II

l)I9

R16
R20

R24

RI9

Ri8

Rl1

Qi3

Q15

I
R5

R12

C9
R3

022

II
I

D23

I
M500

15 -0138

Figure 2-31

M500 Negative Receiver, Parts Location Diagram

2.17 M632 NEGATIVE DRIVER MODULE
The M632 is an M-series single-height module containing eight driver circuits (see Figures 2-32, 2-33, and 2-34).
It accepts positive logic signals and converts them to negative logic levels.

Each driver consists of a TTL input gate and a negative open-collector output driver clamped to ground and -3V.
Inputs:

Standard TTL levels - input current load at OV is 1.25 units.

Outputs:

Outputs are standard negative logic levels.
Risetime: 15 ns
Falltime: 15 ns with].5 kn to -15V at output

Input/Output Delay:

50 ns max

Power Dissipation:

600 mW from -15V max
900 m W from +5V max

Applkation:

The M632 is used to convert positive logic signals to negative logic
levels that drive the PDP-9 negative [/0 bus. The M632 is pin compatible with the M622.

02
Bl~

~__

M632

E2
01~

M632

K2
Jl~

~
-H1

~
~
~
~
M2

M632

POWER

---A2-+5V

M632

15-0079

...-C2,Tl-GNO

Figure 2-32 Negative Driver, Block Schematic

2-38

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

A2
+5'"
RI
470
10%

;;

R5
470
10%

R3
470
10%

R9
470
10%

R7
470
10%

~~D7

~~ 04

~~DI

;;

~~DIO

D2~~

~
EI

13 I

109

D8~~

R6
3.9K

R4
3.9K

R2
3.9K

D5"~

~~DI6

,j~013

~ ~~~ ~ ~~" ~~~"' ~ ~~"

0--

R8
3.9K

RI5 +
470
10% -

j"C8

,j~DI9

014"~

RIO
3.9K

017 ,j~

RI2
3.9K

C2
CI
6.8MFD
35V

~r-V2
t--

RI4
3.9K

3 2

5 4
EI

9 10
FI

13 I

3 2

5 4

E3
9 10
LI

E3
13 I
MI

E3
3 2
NI

E3
5

9 10

4
PI

13 I

6 4

2 3

1-032

.... 031
~ ~ 0662
~

D23~~

RI6
3.9K

~ ~ 0662

'-..

g:-

D20~~

~~g~ 62
GNO
C2,F2,J2 ,L2,
N2,R2,U 2,TI

I,
~I'

024

~·~2
;; CIO
C4

5
~~g~ 62

~~~ ~r~ ~~~ ~~~ ~.~ '.~ ~r~
EI

r---

RI7
1.5K

D2~~

~~.' ~~~~ ~ ~~"

DII~~

RI3
470
10"1.

RII
470
10%

j"C7

11---0
ug~~2
U~l2

+3V

.. ,g~~2

- .6V
- 3V

RI8
1.5K
82
15'"

UNLESS OTHERWISE INDICATED:
RESISTORS ARE I/4W, 5"10
DIODES ARE 0664
TRANSISTORS ARE DEC36398
I
ARE DEC74H50
PIN 7 ON EACH IC =GND
PIN 14 ON EACH IC =+5'"
CAPACITORS ARE .01 MFD

c·s

,~~~~:~.TE~E~TR~A;NS3'S;,TO~R~&~0~IO~0~E~CO;N~V~ER;Sl;ONECH;A~RTs

111.....0

TITLE

POSITIVE INPUT

'564
IN'OOO
~ WIlUIii CONVERTER DRIVER M632
~~~~~~I:£lDIo[!&2ill::jj~~N36!!4.~.~~t===::t==~~g~~;R~~I~~ S~E ~ M6;~~~'

Figure 2-33 M632 Negative Driver, Circuit Schematic

.EV

U
C ::;
C' ~

.- "

0'
R1
04

J :t.1

(-.J

.):,.
0

D 25

R 11
D' 6

R13
D19

030

R15

D22

Q Q

D11

R10

Q GJ
Q Q
I

D20

D23

Q Q

I D3 II
R4
I
I D6 II
R6

R2
02

G GJ

R18

D13

D27

829

II
I

D26

L) 28

Q Q
Q Q

01:)

R17

0 G

S 32

D14
R12
D17
Q14

R16

I
I
I
I
I
I
I
I
I
I
I
I

D 12

D15

D18

D21

D24

G
E2

G
E3

M632

~5-0'4C

Figure 2-34 M632 Negative Driver, Parts Location Diagram

2.18 705B POWER SUPPLY
The 705B Power Supply provides the logic power needed for the DEC disk system (see Figures 2-35 and 2-36).
It is designed for 50/60 Hz single-phase input.
The 70SB can be driven from the following voltage and frequency combinations by selection of the appropriate
taps.
100 Vac ± IS%
11SVac±IS%
200 Vac ± 15%
21S Vac ± 15%
230 Vac ± IS%

SO Hz ± 2%
50 Hz ± 2%
50 Hz ± 2%
50 Hz ± 2%
50 Hz ± 2%

120 Vac ± 15%

60 Hz ± 2%

240 Vac ± 15%

60 Hz ± 2%

The 70SB supply includes a primary autotransformer to supply SA at 120 Vac, regardless of any line voltage
fluctuations.
Logic Power:

The dc-output voltages, as stated below, must be maintained under
the following conditions:
Line variations of ± 15% of nominal line voltage.
Load variations of 1/2-10ad to full load.
Line frequency variations of ± 2% nominal line frequency.

Output Voltages:

+10 Vdc

I (max)
Regulation
Ripple (max)

3.5A
+9.4 Vdc to + 11.0 Vdc
300 mV

-IS Vdc

I (max)
Regulation
Ripple (max)

24A
-14.S Vdc to -16 Vdc
700mV

Each

I (max)
Regulation
Ripple (max)

4A
9.4 Vdc to 11.0 Vdc
300mV

Two Floating 10 V dc:

Under loss of power for 25 milliseconds, the drops for the various output
dc-voltages are as follows:
+IOVdc
±19Vdc
-15 Vdc

IV
IV
2.5V

Input Surge Current Under Full Load:
7.SA at 120 Vac, 60 Hz input
Recurrent Peak Current Input:
5.0A at ] 20 Vac, 60 Hz input
2.19 716 INDICATOR SUPPLY
The 7] 6 Indicator Supply is designed to be used with the PDP-IS system indicator panels (see Figure 2-37).
Its output is between 7 and 9 Vdc at 4.5A (black and orange terminals). An ac-signal source is also supplied at
the white and blue terminals. Neither terminal should be grounded. This signal can be used as a clock or trigger
for a synchronizing system.
2-41

Figure 2-35 705B Power Supply

2-42

FLOATING SUPPLY
COM

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PARTS LIST
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THIS SCHEMATIC IS FURNISHED DNLY FOR TEST AND MAINTENANCE PURPOSES. THEJ
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COPYRIGHT
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PRINTED CIRCUIT REV.

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2.20 855 POWER CONTROL
The 855 Power Control accepts a 30A power cord at either 115 or 230 Vac, filters the voltage, and delivers the
voltage to either a switched or an unswitched output. A circuit breaker at the input controls all power. The
switched output can be controlled locally or remotely by setting the LOCAL, REMOTE, OFF switch. Both sides
of the ac line are switched. Figure 2-38 shows the unit, and Figure 2-39 shows its circuit schematic.

CAUTION: OUTPUT VOLTAGES
OETI;RMiNED BY INPUT VOlTAGE
JMPOT;j1fS/'230V 50-60 Hz
<"':»' ,,::10 AMP <- SIN(UE PHASE
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Figure 2-38 855 Power Control

2-45

THIS SCHEMAnc IS FURNISHEe ONLY FOR TEST ANO MAINTENANCE PURPOSES. THEJ
CIRCUITS ARE PROPRIETARY IN NATURE A.ND SHOUL.D BE TREATED ACCORDINGLY.

BV DIGITAL EQUIPMENT CORPORATION

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Chapter 3
RS09 Disk Drive

The RS09 disk drive (see Figures 3-1 and 3-2) consists of two assemblies; the RS08-M disk assembly, and the
RS09-P disk electronics. The two units are functionally integrated and shall be referred to in Chapter 3 as a
single unit, the RS09.

3.1 READ/WRITE HEADS
There are three basic considerations involved in designing and constructing a magnetic recording for reproduction.
These are:
1.

A device that can translate an electrical signal into a magnetic field.

A magnetizable medium that conforms to and retains the field.

A device that can detect the magnetic field and convert it to a signal that can be identified
with the original.

These three elements take the physical form of the record head, the disk surface, and the reproduce head. With
electronic amplification and a disk drive added to these elements, a basic magnetic disk is formed. In some applications the record head and reproduce head are combined into one head, the read/write head.
The read/write head can be compared to a transformer with a single winding. When current flows in the winding,
the current produces a magnetic flux similar to that in the core of a transformer. The core is made of a closed
ring with a nonmagnetic gap. The gap is bridged by the magnetic surface of the disk, and the flux detours around
the gap into the disk surface to complete its path. When the disk is moved across the gap, the magnetic material
is subjected to a flux (polarity) that is proportional to the signal current on the head winding. As the material
leaves the head gap, each particle retains the state of the magnetization that was last imposed on it by the protruding flux. Thus, the actual recording takes place at the trailing edge of the gap. Figure 3-3 illustrates this
process.
To reproduce this signal, the magnetic pattern on the disk surface is moved across the head; and the magnetic gap
detours the magnetic flux through the core itself. The flux lines are proportional to the magnetic gradient of the
magnetized surface, and the induced voltage of the head winding follows the law of electromagnetic induction:
e = NJtq, -. Thus, the output is the differential of the input. The waveforms recorded on the disk surface are determined by the method of recording used. There are two basic recording schemes used in digital systems, RZ and
NRZ. In general, both methods operate by saturating the magnetic coding in one of two directions.

3-1

DISK

MOUNTING SQUARE - - -

Figure 3-1 Disk Assembly With Cover Removed

3-2

8 HEADS EACH

TI M1NG
TRACK SHOE

Figure 3-2 Disk Assembly With Cover and Surface Removed

3-3

RECORDING
CURRENT

DISK
SURFACE

08-0458

Figure 3-3 (a) DECdisk Head Assembly and (b) Simplified Diagram
of the Magnetic Recording Process

3.2 DIGITAL RECORDING TECHNIQUES
There are two basic methods of recording digital data on a magnetic disk, return to zero (RZ) and nonreturn to
zero (NRZ). The names refer to the nature of the head current, which in the first case stabilizes at zero when a
bit is not being written, and in the second case stabilizes at either a positive or a negative head current between
bits. There are several different ways of recording binary digits with these two methods. One technique in RZ
recording recognizes one state of saturation as a binary one, and the other state as a zero; the zero state represents
nothing. DECdisk, which uses NRZ, has no fixed state of magnetization assigned to either digit; rather, the state
of magnetization is reversed every time a binary one is to be recorded, but left where it is if a binary zero is to be
recorded. The NRZ method is more efficient than the RZ method in that more data is recorded with fewer flux
reversals. However, the RZ technique provides for a self-clocking format. Figure 3-4 illustrates differences in the
head current waveform of the two methods.

C LOCK TRACK
:.oo+-t-+-+-+ RETURN TO ZERO (RZ)

RECORDING +
HEAD a
CURRENT
BINARY DIGIT

NON RETURN TO ZERO (NRZ)

09-0364

Figure 3-4 NRZ and RZ Recording Formats

3-4

The fact that the DECdisk NRZ does not present a self-clocking format (some form of reference clock must be
present to determine where the zeroes fall) suggests that a clock must also be recorded along with the data. A
clock track called the A track is recorded on one channel of the disk, and used as a timing reference to read and
to write digits. Two more tracks called Band C are also recorded to identify individual data words on the disk
so that they can be retrieved.
3.3 THE READ/WRITE HEAD ELECTRONICS
In the DECdisk system, data is stored serially on 128 tracks around the disk surface (refer to Chapter 1). Only
one of these tracks is engaged in reading or writing at anyone time, although 128 heads are continually riding
over each track. At the same time, the A, B, and C tracks are continually being read and used to clock data onto
or out of the data tracks. A particular track is selected by the controller through a matrix selection system. Once
selected, a particular head reads or writes according to instructions from the controller. Since all of the heads in
the matrix are identical, only one has been selected to illustrate the read/write operation. Refer to Figure 3-5.
(The characteristics of the modules in this figure are given in Chapter 2.)
The data bit to be recorded is clocked by the A time clock into the G290 flip-flop, which drives the electronics
of the head.
The coil L represents the head winding, which is the center leg of a simple bridge consisting of resistors R 1 and
R2; diodes DI and D2; and the switching transistors Tl and T2. When the control reads or writes from this head,
it does so by selecting the appropriate G286 Center Tap Selector and the corresponding G285 Series Switch. This
combination applies +20V to node A, switches on transistors TI and T2, and forward biases the diodes Dl and
D2. Current (approximately 5 rnA) flows into the G085 read amplifier to -15V. If the G290 writer has not been
selected, this condition leaves the bridge balanced and no current flows through the coil. This is the case during
a READ operation; the changing magnetic field from the disk surface induces a voltage into the coil that is seen
across the input of the G085 reader, subsequently amplified, and sliced to appear at OUT. The polarity of the
voltage across the coil, which is a function of the direction of flux change induced into the head, determines the
relative polarity of the + and - OUT signal.
During a WRITE operation, the same voltages are applied by the G285 and G286 modules, but the bridge is unbalanced by a -15V level applied to the emitter of either TI or T2 by the G290. This forces approximately 45 rnA
through the head coil in one of two directions, depending on which transistor sees the -15V. The transistor selected
is a function of the writer flip-flop in the G290.
When a one is to be written, the flip-flop is complemented by the clock; the -15V is switched from one transistor
to the other; the current changes direction; and the resultant change in magnetic flux produces the field that is
recorded on the disk surface. Note that current is always flowing in the coil; the current never returns to zero
(NRZ). Because the three timing tracks are always selected, the G286 is replaced with the +20V center tap from
the G085, and the diodes feed directly into the read amplifier's input.
Figure 3-6 shows some of the waveforms that occur in the read/write head circuitry. The read voltage, a bell
shaped pulse, peaks approximately 400 ns after the CLOCK pUlse. This voltage is amplified and sliced to appear
either at +OUT or -OUT, depending on the voltage polarity. Note that the NRZ format used by this system
always produces alternate pulses at +OUT and -OUT. A positive pulse cannot be followed by another positive
pulse, nor a negative pulse by another negative pUlse. This characteristic is utilized to detect errors in the A, B,
C, and data tracks.

3-5

PART OF WORD
ADDRESS CODE

CENTER TAP
SELECTOR

-.:;::--+-.. +20V
READING VOLTAGE = 5mV
R 1 = R2 = 750!l
RCOIL=5!l
LCOIL=33Jl.h
WRITING CURRENT = 45mA

-15V

DATA BIT TO
BE WRITTEN
(HIGH IF LOGI C 1)

-15V

+OUT

WRITE
CLOCK -.---t--l~/I
G085

G290

- OUT
CURRENT
SOURCE
SELECT

-15V

SER IES
SWITCH
-15V
09-03Sl

'---y--J
PART OF WORD
ADDRESS CODE

Figure 3-5 DECdisk READ/WRITE Electronics

3-6

CLOCK

WRITE FF
CORE WRITE CURRENT
UPPER SLICE LEVEL
LOWER SLICE LEVEL

CORE READ VOLTAGE
+ OUT
- OUT

09-0363

Figure 3-6 READ/WRITE Electronics Wavefonns

3.4 THE DECDISK SIGNAL FORMAT
The selection of specific areas on the disk to write into or read out of is accomplished on DECdisk by dividing
the circumference of the disk into 2048 segments (37778) in such a way that each segment of any track records
a complete word. One track (the B track) is then assigned to record the address of each segment, and this track
is made available to the controller, which assembles and identifies these segments. Another track (the C track)
is needed to delineate the segment, since the length of the address is less than that of the words. Each of the
three prerecorded tracks (the A, B, and C tracks) are duplicated on three more tracks, to be used if the first set
is destroyed in the field. If this occurs, the Field Engineer reverses the position of one end of the timing track
head cable to activate the spare tracks.
Thus, the disk surface is actually divided into 134 tracks by 134 read/write heads, each riding slightly above the
disk and covering a narrow circular ribbon of the disk surface. The heads are mounted in groups of 8 on a unit
called a shoe. The data shoes are set on cards, which are then inserted into slots under the disk surface. The slots
are spread around the circumference of the disk as shown in Figure 3-2.
The shoe that contains the six prerecorded tracks is mounted alone on a card (shown in Figure 3-2).
The relative positions of all the timing and data tracks are shown in Figure 3-7. The signal counter is a reference,
not a track itself. The gap area shown is a breather space for the DECdisk system at the point where it switches its
head from track to track. The timing pulses stop during this period. There is also a buffer zone on either side of
the gap where no data or addresses are recorded.
It is important to note that:

The address refers not to the segment in which it is but to the following segment. This allows the controller time to assemble the address and identify the address before the actual data area appears under the data heads.

The first bit of each address, the control bit, is always a binary one. The first bit of each data word,
a guard bit, is always a binary zero.

Each address and data bit calculate a parity bit, which they deposit at the end of the word. Parity
ensures that an even number of ones is in each word.

3-7

TIMING TRACK

ADDRESS TRACK

I I III I
-

C DELIMITER TRACK

I I I

I II II I

III III I

I I I II

I I I I I I I I I I I I I I I I I I I I I I I I I I I I

W;;;;;;;;;;;ii;;14

ADDRESS 3777 ---------+0_

' - ! - - - - - - - S E G M E N T 3 7 7 6 - - - - - -...........
I - - - - - - S E G M E N T 3777------~.1

TIMING TRACK

ADDRESS TRACK

pi/)j;j}//iiiJ;ii//li41 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I
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ADDRESS 0000
-I

...- - - ADDRESS 0 0 0 1 - - -....

DELIMITER TRACK

D FIRST DATA TRACK

IG117\ls115b4b311Z11d1019181ds1514131z11101pl

I..

SEGMENT 0000

COUNTER TRACK
09-0406

Figure 3-7 DECdisk Format

3-9

Figure 3-8 Timing Track Writer

3-11

The address always starts at bit 0 of the counter or bit 14 of the data word in its segment. The
C track pulses are recorded at bits 15 and 16 of the reference counter.

The preceding observations are particularly important when the disk is to be preformatted; that is, when the A,
B, and C tracks are to be prerecorded at the factory onto the disk surface (this function is performed by the
Timing Track Writer, which is explained in the Paragraph 3.5).
3.5 THE TIMING TRACK WRITER
The Timing Track Writer (see Figure 3-8) is the device used in the depot to record the A, B, and C timing and
address tracks on the surface of the RS09 disk .. The writer is built of M-series modules and mounted in a single
H911 panel. It needs no computer and cables directly to the read/write heads of the RS09. This allows the
RS09 units to be preformatted before they are checked out (if the heads, disk, and disk drive are functional).
Figure 3-9 is the block diagram of the Timing Track Writer. It consists of a clock, an II-bit serial counter, a
5-bit modulo 20 counter, the logic to measure the length of the gap, and the drivers and receiver for the read/
write heads. When the clock is enabled by a manual switch, and the WRITE OFF switch is turned on, equipment operation begins. The disk must be rotating and the writer cabled to it. The counter keeps track of the
number of bit cells, the decoding of the correct time when the C track pulses should be written, and the times
at which the shift counter should start and stop its shifting.

OFF

CLOCK
FREQUENCY
ADJUSTMENT

WRITE OFF

r--+-!----.

CLOCK
LOGIC

A,B,C TRACK
WRITE
ELECTRONICS
TO/FROM
RS09

11 BIT SHIFT SERIAL
COUNTER
STAR1
COUN
COUNTER

0-19 10

J
-

STOP
COUNT

WRITE C TRACK

ATT FROM A TRACK READ HEAD

1 - - - - INCREMENT THE GAP
MEASURING
LOGIC FOR 1 - - - - THE GAP IS OK, BETWEEN 250-350},ls
THE GAP
1 - - - - DECREMENT THE GAP
09-0365

Figure 3-9 Timing Track Writer, Block Diagram

3-12

The II-bit serial counter starts at all zeroes and then shifts its contents from the least significant bit onto the B
or address track and, at the same time, back into its most significant bit. The counter then automatically increments itself by one for the next address.
Meanwhile, the clock is recording the A or timing track. When the gap comes up at the end of the revolution,
the gap-measuring logic examines the time between the last clock bit and the first appearance of an A timing
track pulse. If the time is less than 250 J.ls, a light (INC) flashes on to inform the operator to increase the clock
frequency. If the time is greater than 350 J.ls, light DEC flashes on; and the operator should decrease the clock
frequency. When the clock frequency is set so that the gap lies between 250 and 350 J.ls, the OK light flashes on,
and the operator knows that the disk has been preformatted properly. Both sets of timing are recorded at the
same time.
NOTE
The Engineering Drawings of the DECdisk system ~re identified
by a code; i.e., Drawing D-BS-RS09-TA-3. Consult Volume 2
of this manual for the drawings referred to in the following description.
Assume that the WRITE OFF switch is enabled. The switch shown in Drawing D-BS-RS09-T A-3 is set, and it
triggers a 100 ms delay that times out and issues a CLR (H) to initiate the system. During this delay, the disk is
cleared of any signals. The CLR H signal clears the WA serial counter and the BC counter shown in Drawing
D-BS-RS09-TA-4. It also sets the Write Enable flag (WR EN), which in turn enables the M401 clock. The clock
drives a 2-bit ring counter made up of flip-flops CLK and A CLK. These flip-flops provide the main timing pulses
for the counters and timing tracks. The two flip-flops are 90° out of phase.
The BC counter begins to count; the level COO EN is asserted on a count of 19, and the next pulse sets COO. At
the saine time, the guard bit is written. COO also enables the Word Address Register to start writing into the B
track by setting WR ADR and gating WA 00 to the input of the G290. Meanwhile, the A CLK has been writing
timing pulses 800 ns apart onto the A track. The WA serial counter shifts its address, and at the same time
serially increments itself by shifting its least significant bit into the flag CRY, detecting the first 0 to appear, and
forcing a 1 into the most significant bit at that point. All 1s before this 0 are shifted back as Os, and all bits after
this point are shifted back the way they emerge. The feedback function is the exclusive OR of CRY and
WAOO. CRY is initialized to aI, and reset on the first 0 it sees from the WA Register.
When the counter reaches 11, the C 11 flag (Drawing D-BS-RS09-TA-2) is set and the address writing stops. The
flag WR ADR is reset, as is the G290 if an odd parity existed in the address. (This parity is written.)
When the counter reaches 15, the C track writing is enabled and the CTP and CTN pulses are recorded. The flag
LADR (Last Address) is set when CII is cleared while CRY is still on a 1. This signifies that the last segment is
approaching, i.e., that CRY stayed on through a complete string of Is for address 3777 .. WhenWAOI comes up,
at the count of 2 after overflow the WR CLR flag shown on Drawing D-BS-RS09-TA-3 is set by CII to prepare
the logic for the approaching gap. The WR EN flag is cleared on COO, and' all writing stops. The R303 delay of
print disables the output of the read amplifier until it recovers after writing; when the read amplifier sets, it passes
the A track through its reader. At the same time two M302 delays are also set, and they time out to 250 J.lS and
350 J.lS. If the A track passes any timing track pulse before 250 J.lS are up, the flag INC is set to tell the operator
to increase the clock frequency (increase the gap time). If the next A track timing pulse comes between 250 J.lS and
350 J.ls, the OK flag is set. The DEC flag sets if the A pulse arrives after 350 J.lS, and the operator should decrease the
clock frequency (decrease the gap time). If either INC or DEC occur, the system is cleared out and starts again.
Otherwise, the system stops formatting, having completed its job.

3-13

Drawing D-BS-RS09-TA-3 shows a SYNC flag that sets as soon as the clock begins to issue pulses. This flag is
useful as a sync' point because it switches precisely at the start of the format.
Drawings D-FD-RS09-TA-5 and D-TD-RS09-TA-6 show the flow diagram and timing, respectively, for the writer.
Note that the preceding explanation applies when the PDP-9/PDP-15 switch is turned to PDP-9.

3-14

Chapter 4
DECdisk Logic

The logic of the DECdisk system is explained in this chapter by presenting the logic of the DECdisk subsections.
(L on logic diagrams used in this chapter indicates LOW when true.) Simplified logic diagrams are presented in
this chapter. For a more detailed description, consult the appropriate Engineering Drawings in Volume 2 of this
manual.
4.1 SIGNAL ERROR DETECTING CIRCUITS
There are four circuits in the controller that detect errors in the signals from the disk drive on the A, B, C, and
data tracks. These error detecting circuits are explained below.
4.1.1 Error Detection Logic for the A Timing Track
The A track records the main clock pulse for each disk of the DECdisk system. A pulse train with a period of
1.6 J.1.S is recorded. On playback, both negative and positive transitions are detected by the read electronics.
The receiver slices each transition at a predetermined level, and the two pulses are combined to form a pulse
train with a period of 800 ns.
Figure 4-1 shows the logic which is used by the controller to detect either a dropout or an extraneous pulse on
the A timing track. The logic flows from left to right.
The positive and negative sliced outputs from the A timing track head appear as ATTP H 31 and ATTN H 31,
respectively. These outputs drive M602 pulse amplifiers, which in turn trigger M302 delays set for 1.2 J.1.S. These
delays feed back to the input gate that enabled them, and for the period that they are set, they inhibit any other
pulses from passing into the system. During this time, there should be no other pulses except noise spikes. The
two delays are then logically OR'd together to produce the signal ATOK (A Timing Track OK). ATOK releases
registers in the controller, and a start up sequence begins. Whenever the gap is reached, or an A track pulse is
dropped; ATOK is removed and the controller is essentially turned off. When ATOK returns, the controller starts up
up again. Figure 4-2 is the A Track Error Detection Timing Diagram.
The outputs of the two amplifiers are also logically OR'd, and the resultant pulse train is called ATPN H 1. These
pulses, together with the original pulse amplifier outputs, are fed into four flip-flops. If the circuit sees a negative
pulse, immediately after a negative pulse, this logic sets the MPEN flip-flop. The error could have been caused
by a dropped positive pulse or an extraneous H added negative pulse. If the circuit sees a positive pulse immediately following a positive pulse, the flip-flop MNEP is set. Note that as soon as either error flip-flop is set, it inhibits any additional sliced inputs from entering the controller.
The signals APE (1) L, ATPN L 9, ATNM L 9, and A TEST L are related to other parts of the controller and are
covered in later portions of this text. BTER and CTER are flags posted when similar errors occur on the B or C
track respectively.

4-1

CD
A TEST L
APE ( 1) L

ATPM L 9
(MAINTENANCE)

ATT PH 31 --+--f

o
ATOK L I

ATF
SAVE

ATT N H 31 --+-;

CTER(I)L2
BTER (1) L 2

C 0

A TEST L

09-0404

Figure 4-1 A Track Error Detection

4-3

ATTN

ATF

--t:t:tt:'tW

MNEP
MPEN ~____-+__~__+-__~-+__~~~_
FREEZES ALL
.......-;..-......-t-INCOMING SIGNALS
ON A TRACK

-FRZ H 10

09-0405

Figure 4-2 A Track Error Detection, Timing Diagram

4.1.2 Error Detection Logic for the Band C Tracks
On the B track, the disk has stored the address of each segment. Since this is not a predictable clock-pulse, it is
not possible to inhibit the time between signals. However, the preceding explanation of the A track applies with
respect to positive and negative outputs; that is, a positive pulse cannot be followed immediately by another positive pulse, and a negative pulse cannot be followed by another negative pulse. Furthermore, the B track is
strobed into its register by a narrow A track pulse at the optimum time, and is, therefore, extremely reliable.
The logic of Figure 4-3 shows the error detection techniq ue designed for the B track. (The C track logic is identical.)

HDWR
, - - - - - - - ERR H
10

BTP (B) H 9
ATPN HI

BTN (B) H 9
BTER

.-----fC
DISK RUN
(0) L 3

CTER (1) L 2
MNEP(l)Ll
MPEN (t) L t

---ctr--__

Ol---------~:JC----

HDWR
ERR L
10

PC + lOT
CLR L 5

ATPN L 1
DISKRUN(I)L3
09-0399

Figure 4-3 B Track Error Detection

4-5

The JK flip-flop BTF is enabled by BTP and BTN, and clocked by ATPN. If two positive or negative signals
follow in sequence, the error flag BTER is set. The ATPN signal is inhibited (Figure 4-1), and all action stops.
This testing occurs only when the disk is on RUN, or performing an operation. When it is rotating but not
performing, no errors are detected. Figure 44 is the B track timing diagram.

M I 55 I N G P U L 5 E
BTP (B) H 9

ATPN H 1 ~;::ttl:;;;:;:t~;J
BTF·

BTER
1)9-0400

Figure 4-4 B Track Timing Diagram

4.1.3 Error Detection Logic for the Data Tracks
The delay inhibit circuits of the A track cannot be employed in the data track. (The data track logic is shown in
Figure 4-5.) However, if two identical pulses are detected in tandem, the DTER flag is posted, followed by DTE.
The two flip-flops PDT and NDT follow the input pulses and store them, a procedure that is necessary to compensate for skew between the data heads and the timing track heads. This skew does not occur among the A, B,
and C tracks because the heads are all mounted on the same shoe; that is, they are mechanically interconnected.

OTP(B)H 9

TP2H17
'----+--~(1

~-------f K

NOT
OTN (B) H 9

---t---; C

0 ~------------'

CLR L

CTP 2 (t) H :3
TP2 L 17

TP 2 H 17 - - r - - -......
Fl sv (1 ) H 4
CTPI (0) H 3
CTP2 (0) H 3 - - - ' - - 09· 0401

Figure 4-5 Data Track Error Detection Logic
4-6

TP2 L 17 is the ATPN pulse delayed, and CTP2 (1) L3 is a counter generated by the B track. Note that ATPN
is not inhibited; DTER latches and stays on until it is cleared. DTE sets at the end of the word. Figure 4-6 is
the timing diagram of the data track.

SI GNAL

TIMI NG

AT PN H 1
TP 2 H
DTP
DTN
PDT
NDT
I
~

~ -- -

.
.-i-.-t

DTER

-t-t<

-< -

Itt-I
-t - -~--

• +

• ~. ~

" . '

t - ~:.

J_. -; ~

.-, j.
09-0402

Figure 4-6 Data Track Timing Diagram

4.2 THE CONTROL SECTION LOGIC
There are 11 major subsections in the control section logic that interact to establish the primary functions performed by the system.
4.2.1 The lOT Decode and Trap Logic
The lOTs listed in Table 4-1 are decoded in the controller (Drawing D-BS-RF09-0-05). A related logic feature,
the lOT Trap Logic, is shown in Figure 4-7.
If a program issues an lOT that conflicts with the then current DECdisk system operation, the erroneous lOT is
trapped by the lOT trap logic; and an error flag is posted. The trap logic consists of a STOP flag, three pulse
amplifiers, and three flip-flops. Critical lOTs set the STOP flag and inhibit the pulse amplifiers from setting the
corresponding lOP flip-flop. These flip-flops are used in the control rather than the control pulses themselves for
such lOTs. The pulse amplifiers give the STOP flag time to examine each lOT and, when necessary, inhibit the
lOT from setting its flag. The lOP 4 pulse is double-buffered, which serves to provide a clear and load series for
several registers. D lOP 4 is used to clear, and L lOP 4 sets the data into the applicable register. Some lOTs are
allowed to function even though they occur during an operation because they do not affect the controller. These
particular lOTs use the lOP pulses directly. Table 4-1 summarizes the effect that lOTs have on the trap logic.
The mnemonic PE indicates that when a related lOT is issued during a valid disk operation, the Program Error
flag is set. IN indicates that the lOT is stopped.

4-7

rop 1 L 29

lOP lOP 45
WOPIOP4H5
L

IOP 2 L 29

IOP4L29

10 P 1 R H 25
X4 H 5

09-0377

Figure 4-7 lOT TRAP Logic

Table 4-1
lOT Decode Effect on Trap Logic
Device Select Code A (DSA) = 70

lOP 1

SD = 08

SD= 28

SD =48

DSSF
(SKP)

DSCC

~DSL(-;;:-

(lOT CLR)

DRBR
(BR~AC)

lOP 2
DLBR
(AC~BR)

PE
t--

DRAL
(AP~AC)

DLAL
(AC~APO)

(CLR FNRG)

~
PE
I---

DSFX
(AC¥FNRG)
DSCN
(lOT CaNT

SD = 6 8
PE
t---

IN
PE
rIN

DRAH
(API ~AC)

DLAH

(AC~API)

r---

~
PE

STATUS CLR)
lOP 4

Device Select Code B (DSB) = 72

SD = 08

SD = 28

SD = 6 8

SD= 48

lOP 1
DLOK
lOP 2

lOP 4

DSCD
(ST ATUS CLR)

(ADS~AC)

DGHS
(DISK MAINT)

DGSS
(CTL MAINT)

FNRG = Function Register (Fa, ~1, INT)
PE
= Program Error
IN
= Inhibit lOT

- PE
IN

DISK MAINT
(CLR MAINT MODE)

DSRS
(STATUS~AC)

CTL MAINT
CLR MAINT MODE

4.2.2 The Function Register
There are three bits to the Function Register, each of which is double buffered. Figure 4-8 shows the logic and
tabulates the purpose of each bit. The first three flip-flops - FO SV, F 1 SV, and INT SV - are loaded from the
computer under lOT command. When the system is ready to execute the command, an lOT CONTINUE is
given, which jams the instruction word into the next three flip-flops. The controller now acts on the order. If,
during the operation, a major error occurs, bits FO or F 1 of the second Buffer Register are cleared and the operation stops until the error can be repaired. When the programmer wants to resume the operation, he should
issue the continue command to continue the process.
FO and Fl are cleared when the correct number of transfers are completed between the processor and control.
FI is cleared by the I/O OFLO pulse ANDed with EN B (DCH channel multiplexer). FO, however, is not
cleared until SRI and the OFLO flag is set. This guarantees transfer of the last word from the processor buffer
during WRITE and WRITE CHECK operations.
4.2.3 The Timing Generator
Figure 4-9 shows the timing generator logic, which begins in the RS09 disk drive and is cabled to the controller.
Much of this logic has been covered in detail under the description of A track error detection (Paragraph 4.1.1).
Note that ATOK L clears the CTP register. ATPN, the combined timing pulses, is fed through several delays
to generate TPI L 17 and TP2 L 17.
The first CTP of the C track initializes a 3-bit Shift Register (CTP1, CTP2 and CTP3), which is subsequently
shifted by ATP. Pulses appear on the C track only at the end of each word cell. The three flip-flops are used to
set up the data transfers to and from the Shift Register after the word is assembled. Figure 4-10 is a timing diagram for the timing generator. Fami1iarization with this circuit is important because the timing generator signals
are used throughout the controller.
4.2.4 The Unlock Sequence Logic
Figure 4-11 illustrates the use of both ATOK and the C track. The first time CTP3 is set after ATOK is asserted
and a valid operation is specified in the Function Register, the DISK RUN flag is posted. DISK RUN resets when
ATOK falls out; this occurs during the gap or when an A track pulse is lost, or when the Function Register is
cleared and CTP3 occurs. When DISK RUN is set, the controller is assured that a valid C track signal has been
detected with at least three valid ATPN pulses, and meaningful address decoding can begin.
The following sequence must be completed: *
1.

ATOK

ATP and CTP

3 good ATP's (no ATOK) sets CTP3 and enables DISK RUN.

ATP CTP3 set DISK RUN

Continued good ATP's and CTL shifted through 12 positions into CTL FF

4.2.5 The Track and Disk Address Register
The Track and Disk Address Registers are initiated by the computer with an 101' instruction. When the disk is
on RUN (that is, when the disk is performing an operation in the data area of the disk), these registers

*ATOK must be present alway s.

4-10

BIT 15 BIT 16 BIT 17 FUNCTION
CHDSAH5
DIOP1(1)H5
X4 H 5

1/0 BUS 15 H 14

INT

0
0

X
X

READ

WRITE

WRITE CHECK

~-----------"'-4J

M500

NOTE:
INTenobles the PI or AP I
logic in the controllers.

FO SV

NOTHING

(/)
~

I/O BUS 16 H 14

~-----------4-"'-~J

M500

"'--""--1 F 1 S V

I/O BUS 17 H 14

~----------4-e-~J

M500

"'--""--11 NT SV
K

CH DSA H 5
D]OP2(1)H5

INT EN

PC + lOT CLR L 5

X4 H 5

~~{
....
O~

CH DSA H 5
DIOP4(1)H5
X4 H 5

-lOT CONT H 6

OVERFLOW{OFLO (l)H 7
LOGIC

SRI (1)H 4
PC + lOT C L R L 5

M "1

ERROR L 10

I/O OFLO • ENB L 7
Ml11

Figure 4-8 Function Register
09-0378

4-11

,---- ----------

RS09 DISK LOGIC

-----+ATT L

r---- - - - - - - - - - - - - - - - - - - - - - CONTRO

I I

+ 3V

I I

M302
1.2jJs
M111
M 113

B TRACK
HEAD

-ATOK H 1

ATN (8) L 9

G085

ATP(B) L9

-ATT L

I I

M602
-FRZ H 10
M302
1.2jJs

I I

+3V

Mill

I I

I I
P

-ATOK L 1

I
CTN (B)H 9

I
I
I
I

C TRACK

G085

HEAD

CTP (B)H 9

SELECT H

L ___ _

RI07

I I
I I
---- ---- ----- -- ----------- -.J L

--~---------

---------

1 I-I I

CONTROLLER

----~--------

-l
I
I
I

+ 3V

I I

M302
1.2j.1s

ATPN H 1

TPI L 17

M111
M 113

M ltl

-ATOK HI

ATN (B1 L 9

ATPN H 1
ATP(B) L9

I I

-FRZ H 10
M302
1.2j.1s

I I

+3V

M111
M310

I I

I I
I

M627

-ATOK L 1
CTN (B1H 9

TP2 L 17
(50 ns PULSE)

MIll

Mltl

CTP2

CTP3

CTPI
~_C~T~P~(=B~lH~9------------------------------------------------------------------------------------;0

~--~O

~--~

~--~O

~--~

I I
J L-----------

--------~-------------Figure 4-9 Timing Generator

4-13

09-0396

1111111111111111111111111111111111111111111 1111111 IIIIIIIIIIII;:I!IIIIII 1111111 1111111/ 111111 1111111111111111111111 1111111 !II!III II!II!I !IIII!I
~
~
~
~
~
~
~
~
~
~
1

SLICE LEVEL

I'\.

A TRACK
SLICE LEVEL
ATN (81H 9

I\.

i\.

I\.

\.
,

\.
\.

I"
\.

+3V

ATP (B1H 9

I"
\.

+3V

ATPN H 1

350ns

-+I

TP1 H 17

I+-

-+I 1--150ns
TP2 H 17

n n

NOTE:
C TRACK is 90 0 out of phase with A
TRACK end in phase with DATA TRACK
(200ns) = 90 0
SLICE LEVEL

n
n

/(r....:'\.

CTRACK--------+---~--~--~---+--~----r---+_--~--~---r--_+--~----r_--+_--~~,~T,T_r_r-+---~---r

SLICE LEVEL

CTPI (l)H 3

CTP2 (llH 3

CTP3 (11H 3

: -:

CTP (BlH 9

CTN (B)H 9

n.J-:
:'-;

-+-~

L--+-

CTP ·ATPN-

CTP1·ATPN -

(r------i
r------i
(

CTP2·ATPN -

11111111111111 11111111111111 1111111111111111111111111111111111111111111111111 IIIIIIIIIII!I! 1111111111111111111111111111111111111111111111111.
09- 0417

Figure 4-10 Timing Generator, Timing Diagram

4-15

FO (l)L 4
FI (1)L 4
LD SR (1)L 4

BUSY L 4

BUSY H 4

~~-----------aC

DISK

RUN

CTP3 (1)H 3

-ATOK H 1
09-0379

Figure 4-11

Unlock Sequence Logic

automatically increment as each channel and each disk fills up. The incrementing is done in the gap when the
DISK RUN flag clears. Figure 4-12 shows the logic of these registers. WA 07 (0) H 13 is the most significant
bit of the Word Address Register. When this bit clears (because the word address overflows), it sets INC TA.
When the disk reaches the gap (and, therefore, after the last word has been read or written); INC T A is cleared
when DISK RUN clears, and the TA Register is incremented. Similarly, the INC DA is set when the Track Address Register overflows at the beginning of the gap and the Disk Address Register is incremented. When DISK
RUN sets, INC DA is cleared.
4.2.6 The Word Address Register
The Word Address Register is loaded from the computer and incremented each time a word is read or written by
the flags SRO (1) L 3 and SRI (1) L 4. These flags are covered in the read/write logic explanation (Paragraphs 4.3.2
and 4.3.3).
The Word Address Register is continually being compared to the Disk Segment Register, which holds the address
of the segment cell about to rotate under the read/write head.
4.2.7 The Disk Segment Register and Transfer Rate S~lect Logic
Figure 4-13 shows a simplified version of the logic used by the Disk Segment Register and its associated interleave
logic. Timing for the logic is given in Figure 4-14. The address pulses enter the Segment Register at gate I.
Initially all flip-flops are held on zero until the disk reaches its normal speed. DISK SYNC then sets. CTP 3 (1) L 3
then clears the system at the end of each word.
When the Segment Register begins to fill, the first bit of every address is always a 1. When this bit reaches the CTL
flip-flop, the logic sees that a valid address has been assembled. The CTL then inhibits the B track inputs at gate 1
and enables the register to rotate. The clock pulse DS CLK L 12 may not stop, however, depending on the states
of the three transfer rate switches HIGH H 12, MED H 12, and LOW H 12. Only one of these levels can be enabled at a time. If HIGH H 12 is on, then CTL is gated with it; and the DS CLK L 12 is stopped. Simultaneously,
EQ CMP EN H 12 is sent to the comparison logic, and the contents of the Segment Register are compared to the
contents of the Word Address Register. However, if MED H 12 is enabled, the contents of CTL are pulsed into the
X MED Register before the comparison signal is sent out. The Segment Register is rotated once to the right by
the same pulse. If LOW H 12 has been enabled, another clock pulse is allowed to shift the CTL bit into the
X LOW Register before a comparison is made, and the Segment Register is rotated twice with its original address.

4-17

lOR 16 H 24

lOR 05 H 24

Ml13

MI01

10ROO H 24

lOR 06 H 24

lOR 17 H 24

lOB TO API H 6
(lOT INSTRUCTION)

lOB TO APO H 13
(lOT INSTRUCTION)

TA
00

INC
TA
WA 07 (O)H 13

INC

DA
14

L..-_ _.....

DISK RUN (0)l3

PC + lOT ClR L 5

API ClR L 6

ClR H 6

API CLR H 6

\~--------------~v~-----------------JI
(

CH DSA H 5

DISK RUN (1)H 3

lOT INSTRUCTION

lOT .dDP lOP 4 H 5
INSTRUCTION
X2 H 5

+3V
09-0380

Figure 4-12 Track and Disk Address Register

,---

TcoNT'RolliR--- r-BT~;--- - - -

RS09

II TR!"

HEAD

M500

~------

L_-=':c~

- - - - - - - - ---- ---- ---CONTROLLER

...-----JI

HIGHH12

MED H 12

I
I
I

CTL (1) H

D508

D517

CTL (0) H

L -__

~ ~~ ~
__

______

X MED

CTL

t-________________

____

~__-+____~__-+__~~__

4-________

~D~5~C~L~K~L_1~2~

______

DSCLRL12

--~

-ATOK L 1

--- - - - -

--- --- ---- -

--- -

NOTES:
1. CTL,XMED,XLOW determine when the EQ COMP EN H 12 ·signol comes, i.e, the comparison check between the two addresses.
2. The DS shifts until CTL is set, then it starts to shift around.

09-0398

3. At the end of the word the registers are cleared.

Figure 4-13 Disk Segment Register and Transfer Rate Select Logic

4-19

1111111111111111111111 111111111111111111111111111111111111 1111111 [1111111 11111 Iii II III II 1111111 1111111 1111111 1111111 1111111 1111111 1111111
(GUARD)
P

ATPN H 1

CTP H 31

~TP

]16

(PARITY)

h14

I-

4
I

r --,

ADDRESS CELL 1251

, n
< <

I --,

CTN

CTN H 31

CTPI

CTPI (llH 3

CTP2

CTP2 (I)H 3

CTP3

CTP3 (I)H 3

DISK SYNC 0

ASSUME SET BY PREVIOUS WORD

DS CLR L 12

(GUARD)
STP

BTP H 31

,,
")

DS07 (I)H 12
DS08 (llH 12

(PARITY)

BTN

BTN H 31

\~-

~~
I

CTL (llH 12

I -,

DS INPUT

WHE.N MED

I
L

WHEN LOW

~
1

"
I

1
!

(IF DISK RUN (IlL 3
AND
A PA R ( 0) H 12 1

L
ADR OK H 15 H

"
I

M
L
I

n <\

I
I

,,
. , ,
,,

' ,

" \\
I

LOW

I
(

SPEED

I........

)
MED SPEED

LOW SPEED

I~
~
~
J

IK.

)

~
i

HIGH

/
I

"" \

< <

(

\ \.

, ,
I

CTL

MED

WHEN HIGH

DS CLK L 12 H

L LOW (IlH 12

)

)
\

HIGH

( I --,

X MED (I)H 12

EO CMP
EN H 12

~
\

'l--

1/'\

.>>n

DS17 (I)H 12

BTN

(

" ADR OK HIGH

I ADR OK MED
i ADR OK LOW

I
I

n
n
~

I
I

IL
II

1111111 111111111111111111111111111111111111111111111111111111 11111111111111111111111111111111111111111111 1111111 111111111111111 111111111111111
09-0416

Figure 4-14 Disk Segment Register,
Timing Diagram

4-21

Rotating the register once or twice to the right forces the disk to accept every second or fourth address as the
valid address it was seeking. By rotating once, every second address is transformed into a number that is equal
to every successive address. Alternately, by rotating twice, every fourth address transforms into a number that
equals every successive address. The Word Address Register sees no difference; it takes either twice or four
times as long to get the comparison. Table 4 ..2 illustrates the way this transformation occurs for a 3 bit register.
(Table 4-2 assumes that the Word Address Register was loaded with 2, and the Segment Register was at I.)

Table 4-2
Rotating The Disk Segment Register
Contents of Word
Address Register

Contents of Disk
Segment Register

010

011
100

Contents of Disk
Segment Register
Rotated Once

001
010
all
100
101
110
111

100

Equal
Comparison

111

NO
NO
NO
YES
NO
YES
NO

000
001
010
011
100
101
110
111

000
1.00
001
1.01
010
1.10
all
111

NO
YES
NO
YES
NO
YES
NO
YES

000
001
010
all
100
101

QOO

YES
NO
YES
NO
YES
NO

Q01

101
QIO

110
Ql1

FIRST
ROTATION

.
GAP

101
110
111

000
001
010
all

100
QOl

101

.Q1O
110

..
'I

SECOND
ROTATION

GAP
FIRST
ROTATION
NEXT
TRACK

When an equal comparison is found, the Word Address Register is incremented; and the data is transferred to or
from that address.

4.2.8 Equal Comparison Gating
Figure 4-15 shows a simple block diagram of the equal-comparison gating between the Disk Segment Register and
the word Address Register. The two registers are compared in parallel with a series of EXCLUSIVE OR gates. If
they compare favorably without a parity error on the address track to invalidate the comparison, and if the controller is performing and DISK RUN is set; then ADDRESS OK (ADR OK HIS) informs the control logic to continue its operation.

4-23

DISK SEGMENT REGISTER

\~------------~---------~

EXCLUSIVE
OUTPUT HIGH IF BOTH REGISTERS COMPARE r - - - .
OR
-+ ~+-~~~~~~~~~~~~~~~~~
GATING

MI17
APAR (O)H 12

ADROKH15

-------~

WORD ADDRESS REGISTER

I
09 -0381

Figure 4-15 Equal Comparison Gating

4.2.9 The Address of the Disk Segment Register (ADS)
After a valid address has been assembled into the Disk Segment Register, the address is transferred to the ADS
Register (see Figure 4-16) and becomes available to the programmer under lOT command. The transfer takes
place when CTL sets but before XMED, provided that the programmer is not reading the current contents of
the ADS. The flip-flop that strobes the DS into the ADS is reset when CTL resets or at TP2 (if XMED is set).
Note that the address placed into the ADS Register is the real segment address, and not the address calculated
by the disk segment logic for low or medium transfer speeds. The address is accurate to within one segment.

DS07(I)HI2

DSOS'(I)HI2

OS 17 (I)HI2

o
ADS
17

-ADS TO lOB H 5CTL1H12

M627

XMEDOH12

+3V
TP2 H 17

C
r.....-_
_01------<1
....

OS TO ADS H 32

+3V
CTL (O)L 12
09-0382

Figure 4-16 ADS Register Logic

4-24

4.3 THE DATA SECTION LOGIC
4.3.1 The Buffer and Shift Registers
The Buffer and Shift Registers are continually passing data back and forth during the course of a data transfer.
The Buffer Register accepts the data word from the computer during a multi-cycle data break and passes the
word down to the Shift Register for writing on the disk surface. Alternately, during a READ operation, the
Shift Register assembles a word off the disk and passes it on to the Buffer Register to be transferred to the computer. Figure 4-17 shows the data paths between the two registers. The Buffer Register is filled from the bus
(lOR 00 - lOR 17) with the pulse lOB TO BRH H 19. The Buffer Register transfers data to the Shift Register
under the command BR TO SR H 17. The Shift Register in turn transfers an assembled word to the Buffer
Register with the BR TO SR H 17 signal. The logic that controls these signals is explained in conjunction with
READ/WRITE and WRITE CHECK operation (Paragraphs 4.3.2,4.3.3, and 4.3.4).
4.3.2 The WRITE Operation and its Associated Logic
Figures 4-18, 4-19, and 4-20 show the logic and timing affecting the controller during a WRITE operation. Assume that the WRITE function has been loaded into the Function Register and that all other registers have been
duly initiated (see Figure 4-18). The continue lOT is issued (lOT CONT H 6), and it posts the first DATA FLAG.
The three-cycle data break responds by loading the first word into the Buffer Register with the signal lOB TO BR
H 19. At the same time the WB FULL flag is set, indicating to the controller that the Buffer Register has valuable
information in it that must not be written over. The disk rotates and checks for equal comparison between the
Segment Register and the Word Address Register. As soon as ADR OK is seen, the level LS EN H 4 enables the
AND gate, which drives the D input to the critical flip-flop SRI. On the first CTP (1) H 3, which indicates that
the cell to be written into is almost under the read head, SRI is set. SRI then increments the Word Address Register, jams the Buffer Register into the Shift Register with the signal BR TO SR H 17, sets LD SR (1) H 4, and
clears WB FULL.
The Shift Register immediately begins to shift the data word out into flip-flop WR DA, which is driven down a
cable to the disk drive itself. (See Figure 4-20.) The data bits are clocked into the G290 writer and through the
heads to be written as flux changes on the surface of the disk. Note that the disk must be selected, a WRITE
operation must be in process (LD SR and FI SV (0) H 4), and no lockout switch can be enabled (LOCK H), or
the data bits are disabled at the input gates of the writer.
Gate 1, which AND's CTT (L) and ATT (L), clears the G290 Register before and after the data word is written.
If the G290 flip-flop ends the word on a zero, the word had even parity; i.e., an even number of Is in it. This
gate has no effect. If the word had odd parity, the G290 ends up a 1 and is cleared by this gate; the flux change
records another 1 and also generates the even parity that a complete word should have. In this way, each word
is guaranteed to have the even parity for which it is checked during READ operation.
4.3.3 The READ Operation and its Associated Logic
Figures 4-21, 4-22, and 4-23 show the logic and timing affecting the controller during a READ operation. (See
Figure 4-21.) The logic up to DASV was explained in the description of the error detection circuitry (Paragraph
4.1.1). Each time PDT or NDT is set and subsequently reset by TP2, indicating that a 1 bit has arrived, DASV
goes to a 1. The SR CLK H 17 pulse then shifts the data down the Shift Register until the word is completely
assembled.

4-25

lOR 00 H 24
rOB TO BR H 19
(WIDE PULSE)

lOR 01 H 24

lOR 17 H 24

MIni

,,!

11----

,-- 0

1f---

.---- 0

BRS

~---+---fC

.---- 0

-, - - -

BRS

I- -

~--'---IC

1,SR TO BR H 19
BR ClR l1B
(NARROW PULSE)
BR TO SR H 17

M113

(')

DA S V (1) H 16 -

_ _ _ _--I 0 c) 1

SRS

SR ClR l16

r--C

~-+------i ,~ J
0

SRS

"'--C

1
~

SR ClK H 17
09-0583

Figure 4-17 Buffer Register and Shift Register Interconnections

4-26

CLR L 6

R
OFLO

,.......--....

DCH ENA (I)H

r---------------------------------------~

M 113

~---CJS

I/O OFLO R H 25

M104

lOB TO BR H 19

WRITE RQ H 25

MUL T I PLEXER

o
DSA L 5

XO H 5
M112

L IOP4 (I)H 5

t------1C

FLAG (1 )L

CLR REQ L

r----------------------A
o

NOTE:
LDSR is needed here because these bits of the
function register are reset by OFLO. During the
write operation, OFLO happens before the
operation has been completed; and LD SR fills
in until writing has been finished.

lOT CON T H 6

WB FULL (O)H 6

Q:~

FO SV (1)H 4

+3V

~a::
~

TP2 H 17

BR TO SR H 17

SRl(1)H4
OFLO {O)H 7

SRO (1) L 3
INC WA H 13

DCH ENA (1)L 7
PC

+ lOT C LR L 5

A-------------------------------------------------~
CTP (I)H 3
M115

D--OD

SRI

WRITE CHECK

-TPI H 17

ADR OK

WRITE

{

FI SV (O)H 4
FO (1l H 4

BUSY L4 - - -

"Yl---" 0

Ol-----J

FO (l)H 4
FI SV (1) H 4

MIll
PC +

-RD DIS H 3

ADROKH15

- LOCK H 31

CTP3(I)H3

01 SK
RUN
C

LS EN H 4

M 1f 3
ATPN H 1
-ATOK H

CTN (B)H 9

-ATOK H L

PC+ lOT CLR H 5
09-0395

Figure 4-18 DCH Control for WRITE and WRITE CHECK

4-27

,--------

-------~---------CONTROLLER
BR 00 (l)H

BR 01 (I)H

TP2 H 17
Fl SV (1 )H
CTP1 (O)H
CTP2(0)H

M311

+3V

SR 00
M216

SR 01
M216

RSO~

I
I

BR 17 (l)H

I
i

B R TO S R H 17 - . -_ _ _ _-+......._ _ _ _ _+-_ _.......J

READ {
OR
WRITE
CHECK

-------

SR 17
M216

WR
DA
M216
C
0

+ CTT (L)

+ ATT (Ll

RI07

Fl SV (1) L 3

SR CLK H 17
M 111
Fl SV (O)H 3
WRITE ONLY

WRITE OR WRITE CHECK

{

M115

WR CLK H

ATPN H 1

FO(1)H3
TP1 H 17
CTP1(I)H3

M 115

SR CLR L 16

LD SR (1)H 4
WRITEONLY

{

M113
F1 SV (OlH 4
R 107

Rl07

M500
LOCK L
R107
-LOCK (B) L

0+--'-;-- ~ !______
I

O134)------

S_E_L_E_C_T_H_L
___

I
I

L ________________________ _

05
:
06
o SELECT 07

----~.--,---------

BR1~

---------

I
I I
I I
I I

RS09

-------

SR 00
M216

SR 01
M216

-------

SR 17
M216

WR
DA
M216
C
0

T06 (0) L -

+ DSL 00

I I

- - - - - - - - - - - - - ,I

I
I
I
I
II

+ CTT (L)
+ ATT (L)
T06 (1) L

Rl07

+OSL 01

TO HEADS 100-177
F1SV(I)L3

CLK H 17

-OSL 01

WR eLK H

-=r-L...-_-

I
I
I

LD SR (1)H 4
WRITEONLY

{

MI13
Fl SV (O)H 4

M500

I
I
I

Rl07
-LOCK (8) L

o SELECT 00

----------~~~

I
I
I
I
I

02
SELECT H L
03-------------.

05
I
:
06
SELECT 07

- - - - - -__ J

09 .... 0397

Figure 4-19 WRITE Circuitry

4-29

1111111'1111111'111111[1111111'1111111 '1111111 1111111111111111111111111111111 111I111 1111111 1111111 1111111111111\11111111"11 II 111111111111111 111I111 11111111111I11 1111111 1111111 1111111 11111111111111111111111"11111 111111, IIIIIIII"IIIII[

1I0SYNCRH25

~JLkf-~-ILU1

-..r--

~ If /rG2-ULl-J1LJ~rL-JL---m-s c-ILULUl~r-IL{JLUl-~ "-n----~I

[aT CaNT H6
~.A
\
I
"
!
DATA FLAG (1)H 7 - . . )
DCH REQ (I IH 7
I
J
\
i "
DCHGRH7 ~-+_-_r--~~('
'~'+-~\~-~\-~+---+--~---+---ri-~----+---~l'--~----+----+----r_--+---~"--r_-~I---~--~--~I--+---~--~
DCH ENA (1)H 7 f - - - - + - - - - f - - - - - f - - - - - 1 ' 1 Y1'----1,I::-~?-_t_-_+---r_-_t_--_+--~----+----+---r_-_t_--_+----~-+_--"t'H_---~--"""t""_-_+_----i_--__+'----+_-~---I
DCH ENB (I)H 7 ~--+_--_r----~--+_--_I
IOBTOBRHI9 ~--+_--_r----t__--+---_+----t__--+---_+~,r-'L--t-~,~----+----t-!--~---+!'---t---_t_--~----t__--_t_---+----~--~--~~---~-4---_+-----~-_+----i-~
AND L IOP4 (I)H 5
~\.Irl--+-""~"t---t---+i---+-1----I--+-"1l
~~(1~4
1
t
IT
~
m
M
1
~
~
3
2
1
~~~~~-~~-~,1~6-~--~-~-~~~~-~--~-+--~-~~-~-~-~
ATPNHI 1~_~~_-Ih'_ _~L__~~_~L___~nL__~L-_ _;~_~L_~~~,,~~hL~-~L--~--IhL----I1L--~~--IL-~IL--~~-~L---lL--~L_~1_~~lL-_~L__-11___\L___~L__-11L-__IL___~L---4I_
.-1-.
f--+----,--- ADDRESS (;oRO 1251:---+--0011
~
CTP (BI H9 ~-+----t-----'I CTP~
'_+---t__-~-_+--t_-_t_-_+---t<'-t__-~-_+---t__-_t_----'icf1'----r-----i--+---+--t-----t---+---r?-~--t----+--__1------'----'
CTN(B)H9
I
CTPI (J)H 3 '----_t_-_+----Ir-cTPii
r
-lCI~l
\ ,"
~~--_t_--_+---+_-------+---t_~t>+-----+----t_--~----+--~
!""""Ci'P2t----+---__iI---+---+----+-~~+----+----+--t----I-----+--~
CTP2 (J)H 3 f---+----t--_+-__j

}----bt

t----t---+---+-~----'~~i

~~_+----t__--_t_--~---~--~--~----t_--~--_+----t---~~

hm--

CT.P3 (I IH 3
t----_t_--_+----t---_t_~~,,~+I----t_--_t_--_+--~-_t_--++-__j~t__--~--------r_--_t_-~~---t_--,_--_+---+_--_t_---+-~
I
BUSY
BUSY H 4
"
DISK RUN (IlH 3
i
i
I
I
i
I
refPl
BTP (8) H9 ~--+---_r----t__---I----_+----t__--_t_----'
i
I
I
B~(B)H9 t---_t_--_+----t_--_t_--_+----t---_t_---+----f--~I";T';1
I
I
!
CTl
SE
ADR OK H15 t----_t_---t-----t----t--_+----t---;---_+----r----_t_~-----f E
i/
HEn
n,
n
n
n
n
n
TP1H17 ~'--+-,L-+-~~~~L-+~L~~L--~'---+_,L-~'---l---'I~+_J~~~~~_+_~L_+~L_4~L--~n~~II-,n~~+-~n~~~n~++~IL-4-~nl~~~+_IL-4_~~?~~L_+~L_4-JI~~~~
,,fJ
n
n
n
n
n
n
n
TP2H17~~~+--~~r_~~~~L+-~L4-~L~~I_+_----'I~~~~IL+~~y--Jy~~~+__~~r_JL-+_~n~\+-~I~--Jny--~nl~t_Jn,~~n~~IL+--JL4--J~~~~~r_IL-+_~~+_~L+_~L4_~L~-JI~-JI~
,

rsb

NOTE·
1. TheWR CHER (write check errorlis posled her.
because SR17 and DASV ore not fhe same at
this point. Since parity Is ok it suggests that
the word was read into the computer wrong.

2 The write check timing is very similar to the

write timing,except thet the write amplifiers
are inhibited and the shift register is allowed
to read the disk data. Reading is done after
the data to be compared is in the shiH reg-

ister. SR17 and DASVare compared bit by
bit as the SR is shifted.

3. 110 sync is Clsynchronous with all controller
timing pulses.

SRI (IlH 4~ '---_t_-_+----t+--+--_+----t_-_t_---+---t__--_t_~~_+---+_--_t_--_+--__1f_--_I_~~ fSRil~+--_+_+_~---+_-_r--~-~~~--_r--~---+---_r-~~~+_-_+_--~
ClEARn \
"
i
SRClRl16 t----4--_+----+__'~+_-_+---+__--_t_--_+----f_-_t_~~~--+__--+_--_+--~r_~~~~~---~-~-_+---+__-_t_---+-~~+_--_t_--_+----t__--+_--_+--------+_-~
ldAD

INC~HI3,

.Irrl

~ro~HI7 t---+----r+---r+----~I----+,----r+-----t----+---rf---~I-,,~~~r--_+_
r-~---+---~--~~/~'~-~f---"--+----+-\-~
~I---~+-~?~,--~'---+'---~---t-r---+I---ri--Jl-t---~r'

(:0 ~t~ ~ l1J, ----11--__1I--~ l---t----+--~ l-_---'r ----It----'t__~r ~~ I----J ~'

r~ ~ ~

/rl-_II-_-+____t--__J L-_-I\

~~,

,,rj

D~S:~ ,\1 ~H I: t--_ _t_--_+---t----:---_+----t----t!---+---_+_--~--~~:2_..__--_+_-__+j----+_--_+_-__+...;\>,_r-Lo+_rSR
__
DO_ES_rI-NO-T-I~NR:Gh::~~;LATIOI
Lr-IL-~r~
____--...,
i i i
,.~
,J-~
BIT
i

MI7(I)HI71-----t!----+I----+----4i----+_-~I------i----+----+--I--+--~:+!,----+----41----+-__~---+~'MIT(IIH

WR CHER (I) H10

,,_

,1-----1!
[~I
L~I
!

~
"

V;'I
i'-'"

DFlO (IlH 7 1-1-11-11-11'--11-1i -I-Ii-Ii1-11-11-11+--[1-1-II-IIr1-11-11-11
!
+-1-11---'1111[1111111 i 111111111111111: 1111111 111111111111111 i 1111111 ! 111111111111111 1111111 1111111 1111111 111111111111111 1111111 1111111 i111111111111111 1111111 1111111 111111111111111111111111111111111111111111111111

Figure 4-20 WRITE Operation for One Word
In Address 1251

4-31

r - --- --- --- --- -- -- --RS'09""' - - I

I
I

TOG (O)l

++-<t__~

(rH_E_A_D_S-,0pO_-_7_7_l

::AO~S f

00- 77

1:t------,

GOBS
D---+-O-+-

I ,~E~i7{
'I

D-----t-o+__ B
T

GOBS

(1 II
HEADS TOG
100-177)

::'T ____________________J
L- -____________
- - - - - --- --- C'ONT'ROlliR-- - - - - --- - - - - --- --}-;R7IT --,
,
II
w1,
I
I
I
I
I
I
I
M",
II
I
SELECT H

BROO(I)H

BR01(I)H

BRI7(llH

~~ITE

CHECK

BRTOSRH17

D31

SRClKH17

B -+o-+--e--DI

WRITE{

WROI~E

CHECK

FO(llH3
TPI H 17
CTPI (1)H 3

READ{
TP2 H 1 7 B - r T P 2
l 17_
OR
FISV(I)H4
WRITE CTPI (OlH 3
M311
CHECK

CTP2 (O)H 3

RD TEST L 17

NOTE:
This delay gives the write check error flog
time to compare SR 17 with DASV before
shifting to compare the next pair during
the write check. It also allows time for
the SROO from DASV.

L -- --- --- -- --- --Figure 4-21

FOR {FI SV
WRITE

_____
O_N_l Y _ _A_T P_N_H_l_ _ _ _ _ _ _ _ _ _ _ _ _

--.-I
09 -0375

READ and WRITE CHECK Logic

4-33

DCH ENA (1) H

o
1/0 OFLO R H 25

+ 3V
lOB TO BR H 19

DSA L '

M104
INCWAH13

DCH ENB (OIL 7

-lOP 2 R L 25

'1111111111111111111111111'111111111111111:1111111:11:llllllllil:lllliilillllillllllliilillillllliliiliiiiiiiiilliiliiilillillilli! iiiiiiiiiii!i!i'i!i!ll!illliii!!!llllllllilll!I:llii!!1111111111111111111111111111111111111111111111111111111IIIIIIIIIIIIIIIIIIIIIjlllllllllllllllllllllllllllliliII,III\!,III\ IIUI

ATPN H 17 1

n
n

TPI H 17
TP2

H'7

n
n
n
n
n; n ' n n

n
n

h ,h

h h h

n I n ADDRESIi '251
n
n,
n

---nn

n
n

~
n

n
n

CTP 181 H9 ~P '--!------r--+--+--i---t_-t----(,'+---t---t---t---+----I CTp
CTN 181 H9
[(TN'
I
I
I
'
eT N
eTPI 1 'IH 3 r---- C'i'Pl1--_.L----+---+--f---+---+---tl"'+'-___t--+---+--+'---!~

n
n

ICtp-,

31---t_~~

eTP3 IIIH 3
D'SK

RUN

'C'T'P"2:

stL--

~CTPrctN,
CT '----t---t---t---j--+---t--r2+---t---t---+--+--t----j
i~
" L !
~

CTP2 (1)H

I
h4 0 h I ~ 0 ,,~ 0 h thO h I 0 0 h h ~
'; 15 h4 h h ; 3 h 1 h Jt I
n ~nDDRESS ~2
n i ri
n
n
n
n' n
n
n
n n--TA~DRESS ' h5
n
rl n n i n , n
n
n
n
n,
n
n
n
_~
~
n Inn
n
n
n
n
n,
n
n
n
n
n
n

,,'-

1 - 'I,N

-»

I !

1---+---f----flf~;C~TP~3_t:=+==t==+==t==:j-,~;=::t==ti==t=::::j'==t==t==tC!-r-=::-=--~CT:,=P~3_t:=+=+==+==l==$t~=+==+==+=+=+1==t==+-~C:..:T.:::P3+==t==t==+i==l=~n~==t:==tI==t=::::t==i~~
\I

I IIH 3

"rf

8TP 181 H9 r.---+--+---+'----+--1-'----' 8T P'--+------J--'<'<+----!'--t--,f__-t--+---t---t--t-t---+---+--'8TP'---+----+-~,~,I-t---t----t---t---t--t-_t_-t--+--+_--,IG~~DI I
!
r;T~'--;;",,*,""--+-_~_--+'_---1
,---+--,
I
r:b 'b,
b '?-:b,,, 1 IPARITYI I
8TN 181 H 9 1---+'1----'----+\1----1--1BTN '---+---+--+---+----t---+-+---+_--+I----t--+_--'-' BTN '-----<' ~T".",N--i----+---1,--+---+---tI----t--I---+--+--+----'rs! NL-( ~TL"TN '----r---r--t---\
, --+---+------'-1 8T NL-(<'-I
I
CTL IIiH 12 1---+-----"---+---+---+---+----+---<"'<'-!.'----'<--1l)!
eTL
f---+---"----t---4--f__-'<'<'-t_----I
CTL
"
I
!
I
I
"'...1'---+--+--+---+---+------'"
'----+---+-A-DR-+-OK--+---+---I
: ~ote ~~~t i~~~Rbg~o~~ ~~ible to set
ADR OK H15 ~-+-'i --i--~-___j--~-+--+--+----i>~---!
I
ADR
,OK
1-\-===t====t===j====t===t==~~4===j~-~-+_~~~+----+----+==+=::::;:t;;::;:;:b:::;:::;:~~+=::j~+==::t:::+==+=~=~=~
i !
!
I
'rf
I

~~11~3~-+_-+-II-~-___j--~-+--+--+-~n~--"-----+--t-___j--~-t-~~
(RS EN)

}

~~--

I
j
i
!
DTP L 31 ~-+_-+_-+---4---'---+---I-----+---<'~'r----7--+---t----:,--~-t_-_+f'
I

~~~m~.~~~~~.m

400ns affer it was actually wr~

~!~!~~~~ll~

~-~~--~ii~-

_______________________ ~ ___ ,
I

'-~~--+-~-::;~~~:~~~~;~~~:~~~:~~~:~~~:~~:::~~~;~~~~~~~:~~~:~~~~1~1~~~~!
I

:~[II=I=!=:I=1==1==!;:1==1=I=:~n==:1:i=:1=1==:==:lh---l'~~:~7~:1!~~('--lr-(:t=~:1'=,====1:,==1=I=n=~==1:1==1=1==:=1
-.R-+--'~--'~~~LJLsL-S nSRLR.cm'TP1\r~

SRCLKHI7Wi.\--,

\r~ j

~Lr~ \r (nSR~LROCTPI~TPI JL--Jl_J~I---,r'!----2c'-j_--,r~'f-

rf-----'1r-.,-----'1'!---n~;

-.J

SRCLRLI6~--~IL-t---+----4---~---+----+---4----<'~----~--+---+_--_r---r-'~~~~~--j----~--r---+----t----i~---+---+---4--___jf__--~I~~~~~~---r---+---+---+--~~----t_--+_--+---+----4-~L~

f~~ :::::

II R8 FULL

~OB"'R-"(SRO::.rI;,.:..II;,;,:,HI_r--+--t--_\+--t-___i,<'+_--+--+--4---j--i--~

::::,:::~JL--I ~~~~ "-JW-n-W-r-fL-JL--IL~ ~~fn-~,--I r-r1-JLW-\~r~--+-WL-L-_~"=-~h,~,:==~r--t-1~f---t-~-<H-...r1l-----+---IL---j---.r--!--~--+:-L-.fl---+-:
1

_-Ii

,~@i.~: = = = : : = = ~=:+I=~_-=~- I+-I!=~_-=~_-,-:~_-=~_4:'~_-=~_~:I~_-=~_-:!- I=~_-=~ : ':~- =~-+:'~_-=~_;:!~_-=~_-:!- l=~_-=~ l=~_-=~_+:l~_-=~_+:!~_-=~_~: ~_-=~_-:~I:=~_-=~ ~'~-=~_-=:+_I~_-=~_~:,~_-=~: !- I=~_-: ~ <-I'+i-'=~_-=~_+:'~_-=~_~: ~:=~_-:I!- :=~_-=~- I+-il=~:=~: 1~_-=~_~: ~_-=~_~I:~_-=~_~:~o:_:H:_H ~:LI~OrC~0~EN~;:~: :~:R~RrI-: -!-2~:=- ~=~:=~ :~: :j:~ =~: ~ ~=~ :.,If- ~=~ :+-i=- ~=~ 'I=~ =~- Il:~ =~ :
======:i1

OfLO IIIH 7

::--,:,:,,"1

I i ;

" i

OFLO f 11 H I ; '

'i'

IIIIII::;!'III!I:IIIIIIIIIIIIIIIIIIII Illilll!IIIIII:IIIIIII:IIII,II:111111111111111 111111111111111111111, illllllllll,llllilllllll)lllllllllllii;lilllllilll,1111illllllllllllillillllill 1IIIIIIIIIIIIIIIIIIIII'IIIIIIIIIIIII'Iillllllllllllili 1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIilllllllllllillil1IIIIIIIIIIIIIiilii 1

Figure 4-23 READ Timing Diagram for One
Word in Address 1251

4-35

At CTPI time, the SRO flag (Figure 4-22) is enabled (provided ADR OK H5 is present, indicating that this word
is the word needed) and sets with TPI. SRO generates SR TO BR H 19, and the contents of the Shift Register
are jammed into the Buffer Register. At the same time, SRO sets the DATA flag, and a three-cycle request is
started. CTPI and TPI clear the Shift Register for the next transfer. SRO sets RB FULL, which will stay set until the computer takes the word in the Buffer Register, and releases it to the Shift Register for the next word.
During the data break, DCH ENB of the MI04 module clears RB FULL when IOP-2 disappears. At this time, the
I/O processor has just taken the data, and the next word can be transferred.
The flag RD SR is assumed to be set in this discussion. It sets on the first CTP (I) H 3 after the READ function
is selected, provided that the level RD DIS L 3 is present (i.e., the READ operation has not been disabled); and
ADR OK has been generated by the comparison logic. (RDSR remembers that a valid word is being assembled.)
RD DIS L 3 is explained in Paragraph 4.3.7 with the Start Up circuits.
4.3.4 The WRITE CHECK Operation and its Associated Logic
WRITE CHECK combines the logic and timing of both the READ and the WRITE functions. The purpose of
WRITE CHECK is to compare the data in memory to corresponding data in the disk. Each word in memory is
transferred into the Buffer Register as though a WRITE operation were in progress. The data is moved to the
Shift Register under the same conditions as it is moved for a WRITE. Now, however, the logic starts to READ.
(See Figure 4-21.) The disk word is shifted into DASV and the low end of the Shift Register, while the memory
word is shifted out of the high end. SR I 7 and DASV always have related bits; that is, the words are compared
bit by bit between DASV and SR 17 as they are shifted into and out of the Shift Register. Figure 4-24 shows the
comparison logic. If the two do not compare favorably, the error flag WR CHER is set. The effects of this flag
are discussed in Paragraph 4.3.5. Figure 4-25 shows the timing for the WRITE CHECK operation.

SR 17 (0) l17
DA SV (0) l 16
SR 17 (1) l 17
DA SV (1) l16

~------------------~D

lD SR (1) H 4
RD ClK l 17

WR
CHER

ClR l 6
09 - 0-3 7 3

Figure 4-24 WRITE CHECK Error

4.3.5 Error Flags
The following paragraphs describe the logic that sets the various error flags .

•
4.3.5.1 WRITE CHECK Error - The WRITE CHECK error (WR CHER) is closely associated with the WRITE
CHECK operation described in Paragraph 4.3.4 (see Figure 4-24). The WR CHER flip-flop is set if SRI7 and
DA 17 logic levels differ at LDSR time. Because WR CHER (1) L is fed back, WR CHER remains set until
cleared by CLRL.

4-37

110 SYNC R H 25

lOT CONT H 6

~~~~lliU~~~~U=L~~~~L~~~~L~~J~~~~U:
hT =r
f-_+-_-+-....JJoc~

DCH GR R H 26

f_--~--~----+_~(

lOB TO BR H 19 a
L IOP4 (1) H 5

ATPN HI

/ \

(

':,

(

L-+_--~----~~~>rr----r----r--~----+---~----+----+----+----+----r----+----f-~,,>r-f---~--~----+---_+----+_--_+----r---_+----r_--~

DCH GR

DCH ENA 11) H 7

_~ 1_ (

,--

\rl---~--r-~~/

•

f'.1

DCH ENA

•

~--4_--_+----~--~--~JJ

DCH ENS (1) H 7

WB FULL (1)H 4

ED~E

SET BUSY ON TRAILING

DCH RQ D L 7

DATA FLAG (1) H 7

DCH

ENB

~--_r--~f---~--~----+_--_+----+_--_+--~~IO~L--+--~,~>~----f----r--~----+----+----+----+----+---_+----r_--_+----f_~~_r--------+_--~----+_--_+----+_--_+----r_--_r--~

~--~--~f_--~---4---~I~--~--_*~--*_-J~~w~B-Fu-L-L4---~~----~~,----+----+----+----+~R=ES~E~T=B~Y=SRtl~ll~)--~--_+I--~~--_t--~~~r~'--~I~--~--_4----+----+----+---_±----~--~--~
17
16
15
In
Iff
Iii
4
I
n
17
16
1~
1~
V 1hZ n
iJ
17
16
Ii
~ADDRESS WORD@ 1251

..... 1--0

I---,ADDRESS

WORD

1252

--...L

-I

CTP (B) H 9

f_--4_--~--~'cTP~'_+----+_--_r----r_--_r--~----+_--f~----+_--_+----+_--_+~C1TPL--+----+----+----r_---r-,--_r--~--~«>~----+_--~----+_--_+~~~-+----+----+----+---~

CTN IB) H 9

f---~--~f_--4_~CTNL-_+----+_--~----r_--~--~--_T,H_--_1----+_--_+----+_--_+~CTN~_+----r_--~--__~--~--~--7r4_--~----+_--_+----+_--_+--JCTN~_+----+_--_+--~

CTPI 11JH 3

f---+----+--__lrc-r-;;;--

CTP2 11JH 3

r---_rl__

"
~~

CTP3 (1)H 3

BUSY H 4

BTP (B)H 9

BTN IBJH 9

~f__--~----f_--4_--___1
~~--4_--_+--~

LD SR -

r-c,:-p-;--f---~--~

~~r_~--~--~--_+--f~--_+--~--_r--~I--~I--~~~--~---+--~
1--~--~~(~--~--~--~--~--+_--vJ!

DISK RUN (llH 3

t-zm-:!

~f---~--~ICTP2 r----r--~----4---~----+_--r~----+_--_+----r_--_r----!r_-~\~

f----+- -+---+--+--~
I
!
I i i ~
1
f-+-/I-------1-__1
f---~!--~f_--4_--_1----+_--_+----+_~BTIPL--+---~-+--~~+----+----r----r--~----~I----4~-r--~'----+----+i--~~IPL-~----~P-$--~*~+---~----+----+'----+---~----r-+-\~--------4------1
I

~--4---_+I----r_--~--_+----~--~--_4----~;--JJBTNL~,~~BTN~_T----r_--~I----+,----H_--4___~----r_--_r--~--~BTN ~BTNL-_+----+_--_r--~----+_--~~~--------_+--~ NOTES
"

ADR OK H 15
TPI H 17

TP2 H 17
SRI II)H 4
INC WA H 13

1. The write amps are turned on early to wipe out

n
n

SR CLK H 17
LD SR 11lH 4
WR DA 11lH 16
WR CK H IRS09)

n
n

n I

CLEAk~ \

CLEAR

~~~h,--~h~-~h~~h,~--lh,~~n~~h,---,h~~h~~,.~h,~~h,--~hL--~h,~__lh,~~ll
~
I

n
n

r h ~
I

(1l1H 7

f -__~--~---+---_t----~I--~!OFLO

II'
,! , !
I

h
I

~
1
~
~~[ l
~
h
~I ~
I l ~1 ~ ~ ' H '
--,--l ~r---;--'h1----'--!~1"'1,~ 1 (~ 1
1

AMP [

, (,,® (h (h ""n (h ~, ~~ (h \ h 'h
,1

"II

' 0

PARITY GUARD

0 ~'.

I
I

I PARITY GUARD

CLEA~ D

1 WRITE

+DSL OO}ASSUMES
ET~~CT
I RS09)
-DSL 00 ENABLED

OFLO (1)H 7

f---~--~f_--4_--_4----+_--_+----+_--_+----r_--~--~~f_--~--_4----+_--_+----+_~~~~+_--_4----+_--_+1____+_--_+--~r~I----r_--~N-O-S-RI-B~E-CA-U-S~E~O-FL-O-P~RE-V-E-NT_E~D-D-M-A-F~LA-G-F-R-OM+_BE-IN-G-S+E-T--__1

SR CLR L 16

BR TO SR H 17

:
,

I
I

'",

... 1

"11

h~~~~~h

(LDI SR CIlH

~n.

Cl possible garbage area where sneak bits may
have been written due to disk jitter.
2. Because of logic and heCld delays the track is
actually written 400ns later thon eoch ATT.
3. ATPN a 110 SYNC are asynchronous.
4. In 1his write operation ,one word was transferred
to address 1251 with the disk at high speed.
The word transferred was 252525.
5. The address word comes one word before its
related data word to allow time for the address
to be shifted into its register and acted upon.

BECAUilSE SRI WAS NOT UP

i
h

!O FllRITY

0 GUARD 10

I OFLO III RESET BY rOT

"
'

* WRITTEN
I
1
I
BY EACH RS09

Ii 1I111I1111 i i II i i II i i I11I iii iii i Iiii ,I iii ill , 1111111i III! II i ,i' iii iii iii II i [ II i i 'IIi 1111111I1111111 1111111, II iii I! 111I1 Illll 11111 I IIIIIII! 1111111 , 1111111, 111111 ,I! 1I111 ,1111111.1111111,1111111,1111111.1111111,111111, 11111111111111111111111111111111111111111111111,1111:
!

09-0418

Figure 4-25 WRITE CHECK Timing Diagram
for One Word in Address 1251

4-39

4.3.5.2 Error and FReeZe - A FReeZe (FRZ) condition occurs if an A, B, or C track error is detected, or if
the address track indicates a parity error (see Figure 4-26). The ERROR flag that causes an interrupt, either
PI or API, is the OR of the flags shown in Figure 4-26.

PSlER (l)l 10
WlO(1)Ll0
DPE(I)Ll0
APE (I)L 10-____~
WRCHER(I)Ll0
MXFR(I)Ll0
DTER (I)L 2

SEQ ER (1)L 10

CTER (1)l 2---'~--
BTER(1)l2
MNEP (l)l 1
MPEN (1)l 1--<J-----

ERROR H 10

FRZ H 10
APE (1) L
09-0387

Figure 4-26 Error and Freeze

4.3.5.3 Address Parity Error - The APAR (Address Parity) flip-flop continually examines the address bits (see
Figure 4-27). Parity must be even; if on the last address bit, APAR is set, a parity error has occurred. As a result, the APE (Address Parity Error) flop is set at CTP2 time. The APAR flop remains set until cleared by
CTP3 or DISK RUN.

BTP (B)l 9
BTN (B)L 9
APAR
ATPN L 1

0L---------------------~A~P~A~R~(1~)~L~120~D~~

-CTN (B)l 9
CTP2 (1)L 3
APE (1)l 10

CTP3 (1)H 3

APE

OPE (1)L 10
WLO (1)l 10

DISK RUN (O)H 3

09 - 03 8~

Figure 4-27 Address Parity Error

4.3.5.4 Missed Transfer Error - The MXFR (Missed TransFeR error) flag is set if there is no DCH ENB (1) L 7
signal (see Figure 4-28). (For example, no data transfer through the three-cycle data break after BUSY has been
on for 130 ms, or two or three revolutions.)

4-41

DCH ENB (llL 7
-BUSY L4
FRZ L 10

MXFR(1)Hl0

MAINT(1)L9

MXFR (OL 10

09-0;386

Figure 4-28 Missed Transfer Error

4.3.5.5 Data Parity Error - The DPAR (Data PARity) flag should be reset when the data word has been completely assembled (even parity) (see Figure 4-29). If the word is not completely assembled, DPAR remains set,
indicating a data parity error. As a result, the DPE (Data Parity Error) flip-flop is set at CTP2 time, if a READ
operation has been specified and either RD SR is asserted (indicating valid data has been transferred) or LD LY
is set (indicating a WRITE CHECK operation has been performed).

DPAR
DA SV (1)H 16

CTP2 (1)L 3-

READ OR { FO SV (O)L 4
WRI TE
C H EC K
F I S V (1 1L 4

) - - - - - 1 MIl 5

~-----------------~D

DPE

C
LD SR (1 lL 4-

CLR L 6
LD
LY

CTP3(1lH3

Ol------rl

RD lD H 10
lD SR (Oll 4 - - - - '

RD SR (1 )L 3

C T P 2 (1 1l 3---r"r--APE (1)l10
DPE (l)l10
WlO (1)L 10~--09-0384

Figure 4-29 Data Parity Error

4-42

,--I

-----------RS09 DISK

+ DSL 00 L

SEL (BA) L

I
Ii -

T02 (0) L
72

TO 1 (1) L

W033

TOO (0) L
34
N

CT07 X H

DSL 0 L

DISABLE
WRITING

(20V WHEN SELECTED)
tENABLE
WRITING

~
!

580

LOCK H
T03 (1) L
T04 (1)L
T05 (1) L
T06 (0) L _ _ _...J

I
I
L ______ _

-3V

----~

C;;;T~ER

-LOCK B L 28

- LOCK H 31

"""~---:-------------_f

100

M 11 3

I
I
I
I

SELECT (B)L

r--- - - - - -

----I
I
I
I

~-W--L-0-E-N--L-4----------------~D

M500

I~{:DR OK H15
I
L __ _ ----------~
CTP2(1)L3
APE (1)L 10

WLO

FI SV (O)H 4
~
FO(1)H4

DPE(1)L10

WLO (l)L 10

CL R L 6

09-0394

Figure 4-30 Write LockOut Error

4-43

4.3.5.6 NonExistent Disk Error (PSLER) - The PSLER (Program Select Error) flip-flop sets if there- is a SEL ERR
(nonexistent disk selected) after a program-controlled disk selection (lOB TO API) (see Figure 4-30). The difference
between PSLER and SEQER is that PSLER is the result of a program error rather than an error caused by stepping
over bounds during a transfer. The 1.5 /lS delay allows the selection logic (SEL ERR) to settle. The PSLER flag
causes an NE DSK (NonExistent DiSK) error signal.

SE L ERR L 30

0
PSLER

lOB TO AP1 L 6

M302
(1.5 p.SEC)

SEQER(1)L~
-C/.NEDSKH10

~----tC

SER CL R L 6

+3V

09-03,66

Figure 4-31 NonExistent Disk by Program Selector Error

4.3.5.7 Write LockOut Error - The CT07 xH output of the G286 is +20 dc when selected (see Figure 4-31).
The +20V signal is applied to the B683 driver when switch 34 is set to DISABLE WRITING. If the disk has
been selected, a negative level is applied to the controller, converted, and gated to the WLO (Write LockOut)
flip-flop. The gating signals are generated before a valid WRITE operation.
At CTP2 time, WLO is set (if no data or address parity errors have been detected). Simultaneously, the WRITE
operation is interrupted by LOCK H 31, as shown in Figure 4-18, and the SRI flip-flop cannot be set.
4.3.5.8 NonExistent Disk (SEQ ER) - The NE DSK error signal can also be produced by the SEQ ER (Sequence Error) flag (see Figure 4-32). The Sequence Error flag is set under the following conditions:

If SEL ERR is enabled, indicating that a nonexistent disk has been selected.

If DA 15 overflows, indicating that the system capacity has been exceeded and the 9th disk
was selected.

The flag is set by INC DA, which is delayed to wait for the settling time of the Disk Select logic. It is then gated
with BUSY and RB FULL (0) to the SEQ ER flip-flop. RB FULL (0) is only asserted if OFLO has not occurred
indicating that this was not the last word and an error condition actually exists. The SEQ ER flag causes an
NE DSK error signal.
NOTE
The SEQ ER flag is set only during a job transfer and not by an
error in program control transfer.

4-44

PSLER (1) H

NE
DSK H 10

SEL ERR L 30

CLR L 6

CH DSA H 5
DP rop 4 H 5
X2 H 5

09-0367

Figure 4-32 NonExistent Disk by Sequence Error

4.3.5.9 Data Channel Timing Errol' - (See Figure 4-33.) The DCH TE (Data Channel Timing Error) flag sets
under the following conditions:

During READ, if RSTE does not get reset by SRO after CTPI and before CTP3. This indicates
that the data was not read by the data channel before SR was ready with the next word.

During WRITE or WRITE CHECK, if LSTE does not get reset by SRI after CTP 1 and before
CTP3. This indicates that the data channel did not load the BR in time to transfer the SR to be
written on the disk.

SRI (1) L 4
09-0368

Figure 4-33 Data Channel Timing Error

4.3.5.10 Program Error - The PE (Program Error) flag is set if the computer issues an illegal lOT while the
machine is doing a preset operation (see Figure 4-34). The STOP flag is set on these lOTS when BUSY is on.
Under these conditions, PE is set directly by STOP.
4.3.6 Automatic Priority and Program Interrupt Logic
When an operation has been completed, the computer word count overflows and the OVERFLOW flag is posted
(Figure 4-35). This flag generates the XFER CPLT L 17 signal, which is gated with INT EN (1) L to cause an
API or PI break. A break can also occur if the ERROR L 10 signal, which is the logical OR of a number of errors
that may occur during an operation, occurs. These errors are covered in Paragraph 4.3.5. Note that the BUSY
signal is gated with OFLO to post the interrupt, which ensures during a WRITE operation that the function is
finished before the interrupt is posted. (Note that during a WRITE operation OFLO happens after the word is
transferred but before it has been written.

4-46

MAINT (0) H 9
BUSY H 4

IOP 1 RH 25

X4 H 5

~.--~
~RL25

r------,

IOP4RL25

STOP (1) L

DSA L 5

>---+-~P-=-E (0) H 10

CLR L 6 - - + - - - { ) /

L ______ ...JI

DSB L 5

09-0369

Figure 4-34 Program Error

API RO (l)H 8

M104

FLAG H

OFLO (l)H 7
M113

XFER CPLT L 7

-BUSY H4

ERROR L 10

INT EN (1)L 4

DISK FLAG H 8
APIRO(1)H8
INTEN(1)H4

M115

PROG INT RO D L 8

09 - 0370

Figure 4-35 Automatic Priority Interrupt and Program Interrupt Logic

4-47

4.3.7 The A TEST and Read Disable Signal
Several flags in the controller sense when the system is in a position to perform. The most critical of these flags
is the DISK RUN flag (see Figure 4-36). This flag sets if there is a valid operation specified in the Function
Register, the A track timing pulses are arriving on time, and a CTP3 (L) H3 level has asserted itself. Only if
DISK RUN is set will ADR OK be allowed to happen (thereby allowing a READ, WRITE or WRITE CHECK
operation). Note that DISK RUN resets as soon as ATOK goes away. This happens only if one of the A track
pulses is dropped because of an error or because of the gap, as described in Paragraph 4.1. One of two error
flip-flops also sets to indicate where the error occurred. The R303 delay, which is held high by DISK RUN,
times out and resets, disabling A TEST L I and stopping all timing track signals. The time it takes for the delay
to reset gives the A track error detection logic a chance to set the appropriate error flag.
The R303 is triggered when DISK RUN is set. It does not reset until 5 JJ.s after DISK RUN is reset, allowing
A TEST L an extra 5 JJ.S to function and the MNEP and MPEN flip-flops to set on the error condition.
Note that if ATOK was used (in place of A Test), no A timing error could ever exist.

FO (1) L 4
Fl (1) L 4
LD SR (1) L 4

A
TEST

r--------,
I
I
I
I
API CLR L 6
INCDA(I)LI4
ERROR L 10

1:1

L _____ ,__ .J

NOTE:
The R303 is trig-oered when DISK RUN 1& set. It does not reset until 5J1.88C ~r DISK RUN II reset,
ollowing A TEST Lon extro 5J1.18c to functlon,and the MNEP and MPEN flip-fiopi to .. t on the
error condition.
If ATOK was used (In place ofATEST),no Atlmlng error con exist.
09- 0371

Figure 4-36 Disk Run Logic

4-48

The Read Disable signal is developed in Figure 4-37.
NOTE
A READ operation is inhibited from starting for 200 J.ls when
the controller is not in Maintenance mode after any of the following conditions:
a.

The Track Address Register is incremented (INC TA (1)
H 14).

The Track Address Register is cleared by an lOT.

A WRITE operation is performed.

The Disk Register is cleared.

The 200 J.ls is necessary to give the Disk Data Amplifiers
time to settle for a READ. In all cases, they are either reselected or going from WRITE to READ mode.

L[)SR(l)H4
FII sv (0) H 4

API CLR L 6 - - ( k -__
INC TA (I) L 14
TA CLR L 14

RD DIS
L 3

--Ql.--MAINT

NOTE
A read operation is inhibited from starting for 200J,Ls when the controller Is not in
maintenance mode after any of the following conditions:

(0) H 9

a. The Track Address Register is incremented (INC TA (I) H14).
b. The Track Address Register Is cleared by on rOT.
c. A WRITE operation is performed.
d. The Disk Register is cleared.
The 200J,Ls is necessary to give the disk data amplifiers time to settle for a READ. In all calis they are
uither reselecte~ or going from WRITE to READ mode,
'
09-0372

Figure 4-37 Read Disable Logic

4.3.8 The Gap
Before and after the gap, there is an area where the A track timing pulses are present, but no address or C track
data is present. In these dormant areas, the controller does nothing because no valid address is decoded. In the
gap proper, however, the A timing track stops. This causes DISK RUN to clear and the TA Register to increment.
The Disk Address Register increments when the TA Register overflows and sets INC DA. When the A track returns,
either because the prese.nt disk reached the end of the gap or a new disk is selected, DISK RUN sets, provided the
disk control is still BUSY. DISK RUN resets INC DA in preparation for the next TA Register overflow.
4.3.9 The Maintenance Logic
Engineering Drawing D-BS-RF09-0-09 shows the logic that has been designed into the controller specifically for
maintenance purposes. There are two distinct sections shown; the first section, which is made up of the four flipflops MAT, MBT, MCT, and MDT, is used to simulate the signals coming from the heads of the disk surface. Three
of the flip-flops are complemented (when the AC bit is a 1) under lOT command, and the MAT is toggled by the
lOT. Their outputs are cabled to the input cable of the disk head. (The special cable used is a head simulator

4-49

cable. For more details on how to perform this operation, refer to the maintenance section description in
Chapter 7.) The second maintenance logic section is used to simulate the complete RS09 unit. Under lOT
command, the output pulses from the RS09 can be generated from the accumulator using the AND gates of
this logic. The flip-flop MAINT is set each time a maintenance lOT is issued, and it is reset by a clear lOT.
MAINT disables the error-detecting signal circuitry and ATOK (which would ordinarily prevent the controller
from functioning because, under lOT command, the A track signals cannot be generated quickly enough).
Chapter I lists the maintenance lOT instructions.

4-50

Chapter 5
Field Installation

5.1 INSTALLATION LOCATION
Limitations on the length of the I/O bus generally require that the DECdisk system be located in the same room
as the computer. Engineering Drawing D-AR-RF09-0-37 illustrates various DECdisk system configurations.
Weights, dimensions, and service clearances are listed in Table 5-1 and Figure 5-1. Special attention should be
paid to access routes (such as the size of doors, elevators, and passage ways) to be used when the system is delivered.
Any special packaging requirements should be communicated to the DEC Special Systems Group when the system
is ordered.
Cables should be as short as possible and protected from damage. Low frequency vibration (such as that caused
by a hand forklift truck operating on a wooden floor) can cause data errors. The DECdisk system is not designed
to operate in aircraft, trucks, or ships.
5.2 ENVIRONMENTAL CONSIDERATIONS
The DECdisk system is designed to operate in a temperature range from 65°F 08°C) to 90°F (35°C) at a relative
humidity of 10 percent to 55 percent with no condensation. The air should be free of dust and corrosive pollutants,
and the air pressure should be kept higher than that of adjacent areas to prevent dust infiltration. If air-conditioning is required, the size of the unit requirement can be calculated from the heat dissipation figures listed in Table
5-1. Computer room air-conditioning should conform to the requirements of the "Standard for the Installation of
Air-Conditioning and Ventilation Systems (nonresidential) N.F.P.A. No. 90A"; as well as to the requirements of the
"Standard for Electronic Computer Systems N.F.P.A. No. 75."
5.3 PRIMARY POWER REQUIREMENTS

The DECdisk system can be operated from either 115 or 230 Vac single-phase, 50 or 60 Hz power. Line voltages
must be maintained to within flO Vac, and the line frequency should not drift more than .1 Hz/sec. A constant
frequency should be provided for installations with unstable power supplies.
Table 5-1 shows the power required for various configurations. The primary power line must terminate in Hubbell
wall receptacles (shown in Figure 5-2), or their equivalent, to be compatible with the DECdisk power line Hubbel1
connector.
The PDP-9 cabinet should be grounded to the building power transformer ground or the building ground point.
Duplex ac-outlets should be provided to power test equipment. The outlets should be close to the equipment,
separately fused, switch-controlled, and rated at 115 or 230 Vac, 15 or 20A.

5-1

Table 5-1
Statistics for DECdisk Installations

Configuration
(Number of
Disks)

Number
of
Cabinets

1
2

Current
(115 Yac)

Dissipation

Total Weight
(lb)

Start
(Amperes)

Run
(Amperes)

Heat
(BTU/HR)

)ower
(KW)

Crated

Uncrated

1
1

14.0
23.0

6.5
8.0

2550
3140

.75
.92

590
690

500
600

3
4
5

2
2
2

33.5
42.5
52.0

11.0
12.5
14.5

4310
4900
5690

1.27
1.44
1.75

1090
1190
1290

1000
1100
1200

6
7
8

3
3
3

62.5
71.5
81.0

17.5
19.0
21.0

6860
7450
8230

1.01
2.18
2.42

1690
1790
1890

1600
1700
1800

NOTES:

Cabinets are 30 in. x 21-11/16 In. x 71-7/16 in. All cabinets of the DECdisk system are
shipped singly or bolted together in pairs (unless otherwise specified). These cabinets
cannot be bolted to the PDP-9.

Disks should not be turned on simultaneously, or the circuit breaker may trip. Approximately 20 sec should be allowed before each successive disk is turned on.

Floor Loading = weight of cabinet/ I in. 2 , since each caster covers approximately 1/4 in. 2
of floor space.

. . <-

SWINGING MOUNTING FRAME DOOR R.H .

18-7/32

",\
II

LEVELER 4 PLACES
- REMOVABLE END PANEL

REMOVABLE END PANEL

67-17/32

FANS
--~

-CABLE ACCESS

CASTER SWIVEL RADIUS 2-13132
(4 CASTERS)

SWINGING DOOR R.H.

,
---+-

19-5116

HEIGHT- 71-7/16
NOTE:
ALL DIMENSIONS IN INCHES
FRONT
15-0033

Figure 5-1 The RF09 Cabinet
5-2

SERVICE OUTLET
120V 60Hz SINGLE PHASE
15A/UGND
NEUTRAL~LINE

FRAME GROUND

~
CAUTION

When neutral is not oval/able for tntl
ab(Jve service, a receptacle of the
above design 511011 be used, but botll
parallel slots 511011 be sllort to prevent
polarized parallel blade plugs (cops)
from fiffing.

FRAME GROUND
NEUTRAL OR
....--LINE 2
LINE 1
RECEPTACLE No. 3330-G
CAP No. 3331-G
115V 60Hz SINGLE PHASE
30 A TW 1ST-LOCK

.....>iIr---

FRAME GROUND

NEUTRAL OR
LIN E 2

LINE t

RECEPTACLE No.7310-G
CAP No.3321-G
230 V 50 H z SIN G L E PH AS E
20A TWIST-LOCK
09-0414

Figure 5-2 Hubbell Wall Receptacle Connector Diagram

5-3

5.4 ACCESSORIES
If carpeting is installed in the computer room, it should be designed to minimize static electricity and resist
fire.
5.5 UNPACKING AND INSTALLATION
The equipment may arrive either as a complete system (with controller, disks and power supplies mounted in
their appropriate cabinet), or as an add on (with disk drives to be mounted in cabinets already available at the
site).
5.5.1 Cabinet Unpacking

If the equipment arrives in cabinets, the following procedure should be followed to unpack and position them.
Step

Procedure
Remove the outer shipping container, which may be either heavy corrugated
cardboard or plywood. Remove all straps first, and then any fasteners and
cleats securing the container to the skid. Remove any wood framing and
supports.

Remove the Polyethylene covers from all cabinets.

Remove the tape or plastic shipping pins from the rear access doors.

Unbolt the cabinets from their shipping skids. The bolts can be reached
through the rear doors.

Raise the leveling feet so that they are above the level of the roll-around
casters.

Form a ramp with wooden blocks and planks from each cabinet skid to the
floor, and roll each cabinet down this ramp.

Roll the system to its proper location.

5.5.2 Cabinet Installation
The DECdisk cabinets are equipped with roll-around casters and adjustable leveling feet. They do not have to
be bolted to the floor. In multiple cabinet installations, cabinets are shipped either individually or in pairs.
DECdisk cabinets should be connected together at the site, but they cannot be bolted to any PDP-9 cabinets
because the two cabinet types are not compatible. To install the cabinets, the following procedure should be
used.
Step

Procedure
Cabinets are joined by filler strips (see Figure 5-3). After the cabinets
are positioned, put the cabinets together and bolt both filler strips and
cabinets together. Do not tighten the bolts securely.

Lower the leveling feet until they support the cabinet. Using a spirit level,
check that all cabinets are level and that the feet are firmly against the floor.

Tighten the bolts that hold the cabinets together and again check the leveling.

Remove the shipping bolts and tape from the slide runners of each disk drive.

Run a ground strap from the DECdisk cabinets to the PDP-9 cabinet.
5-4

71 7/16

FILLER STRIPS
NOTE:
ALL DIMENSIONS IN INCHES

Figure 5-3 Cabinet Bolting Diagram

5-5

5.5.3 RF09 Controller Installation
The controller shown in Figure 5-4 comes mounted in a cabinet (No.1) with at least one disk. Three steps must
be followed to install it.
Procedure

Step

Remove any tape from the modules and check that existing wiring is not
damaged, that hold down bars are in place, and that no modules have fallen
out.
2

Install the I/O bus cables in accordance with Figure 5-5.

Connect the ac remote turn-on cable between the computer and the 855
power control unit at the back of the cabinet (see Figure 5-6). Check that
the line voltage is correct and that the transformer has been properly wired.
(Refer to Engineering Drawing D-IC-RF09-0-35.) Note that on 220V systems
only the 705B and the optional transformer must be wired for 220V. All
other accessories are already wired for 115V. Make sure that the circuit
breaker is OFF on the power control, and then plug the primary power cable
into the line voltage receptacle.

5.5.4 RS09 Unpacking
When the RS09 is shipped as an addition to an already installed system, it must be unpacked at the site and installed in its prelocated cabinet. The procedure for RS09 unpacking is as follows:
Step

Procedure
Turn off the system and the 855 circuit breaker.

Remove the disks from their shipping containers and identify each according to
its tag number.

Carefully install each disk into its proper position in the cabinet according to
Engineering Drawing D-AR-RF09-0-37. Cables should be placed toward the front
of the cabinet.

Install the disk cable bus according to Figure 5-5.

5.5.5 RS09 Installation
It is assumed at this point that the disks have been installed into their cabinets either at the site or in the factory.
For each new disk, perform the following procedures (see Figures 5-6 and 5-7):

Step

Procedure
Remove the silver cloth tape from the pan containing desiccant (Drierite) and
remove the pan from the motor.

Unwrap the blue, green, yellow, red, and black motor leads from the motor.

Connect these wires to the proper color-coded connections on the back of the
RS09 motor control chassis.

Remove the motor lock and hold down the bracket.

5-6

+5V SUPPLY

CABLES _
TO RS09

INPUT SIDE OF 1/0 BUS CABLES

Figure 5-4 The RS09 Electronics

5-7

TO NEXT PERIPHE~AL
1-12 FT se098 OR SC09C

__ E04, E05
F04, F05

PDP-9

E02,E03
...'---'-2-F-T-S-C..
O-g-C-.... F02 F 0 3
j

CABLE

4-W021-W0I1
9FT CABLES
t---------tA27 -

4-W021-WOtl
9 FT CABLES
A25 t - - - - - . . . - - - - - t A27- A25

~--'------~A28 -

A 26 ~------------IA 28 -

A 26

......----------t827 -

S 25 1-------.,...------IB27 -

B2 5

t-------~__tB28 -

B 26 t - - - - - - - - - - - - I B 2 8 -

B 26

RS09

INSERT TERMINATOR
CARDS TYPE G723
IN LOCATIONS A25,
A26, B26, AND TYPE
G711 IN 825

RS09

DECDISK CABLING

\,-:--""'\v~~_..J1

CABLES HARD
WIRED

NOTES:
1. Maximum I.ngth of 110 Bus is 50 ft.
Maximum lengt h of disk bus is 100 ft.
2. If more than 5 RS09 disks are connected
to one confrol, each set of disk bus cables
must be replaced with one BC09A coble.

INDICATOR PANEL
09-0376

Figure 5-5 DECdisk Cabling

DESICCANT PAN

Figure 5-6 The Disk Assembly with Desiccant Pan

Step

Procedure

Turn the motor switches on the back of the RS09 motor control chassis to
the OFF position.

Ensure that the circuit breaker on the 855 Power Control is OFF and that
the LOCAL, OFF, REMOTE switch is in the OFF position.

Connect the ac- and dc-power wiring in accordance with Engineering
Drawing D-IC-RF09-0-35.

Switch the 855 Power Control circuit breaker to On. {At this point, the
hose on the purge unit has not been connected.} Thus, the purge unit itself
is purged, and should continue to be purged for at least 30 min. The disk
motor must be off at this time.

After the 30 min. purge period, remove the cap from the disk unit and connect the purge unit's hose in the cap's place.

5.6 POWER-UP SEQUENCE
Before starting the power-up sequence, all wiring should be double checked, the primary ac-power source should
be tested for the correct voltage, and the positions of all relevant controls verified. The sequence to be followed
to power-up the DECdisk system is as follows:

5-9

MOTOR LEADS

Figure 5-7 Disk Assembly with Pan Removed and Motor Leads Connected

Procedure

Step

Turn off the 855 circuit breaker and all power switches on the Disk Control
chassis. Turn the REMOTE switch to OFF. Plug in the 855 power cord and
turn on the circuit breaker.
2

Turn the DISK POWER switch of the first disk ON. The START and OPERATE
lights should illuminate. The START light should extinguish in approximately
20 sec; until it does, the disk is inoperable.

Check that the disk is running and the blower is operating. If any unusual noises
are heard, turn off the disk immediately and notify the local DEC office that
depot repair is necessary.

Repeat this sequence for each disk. Do not turn on all disks simultaneously, or
the surge current may trigger the circuit breaker. Do not attempt to use one disk
while turning on another; noise transients can cause interference between disks
during turn on.

Turn the REMOTE switch to REMOTE.

5-10

5.7 ACCEPTANCE PROCEDURE
The following paragraphs describe customer acceptance procedures after the DECdisk system is installed and
opera ting properly.
5.7.1 Acceptance Forms
After the system is properly installed, successful operation is demonstrated to the customer by running diagnostics
and the system software. Three forms contained in the accessory kit are used during the customer acceptance
procedure. These forms are:

The Customer Acceptance Form, in which is recorded any exceptions to normal operation
found in the system during the acceptance procedure. Such items should include missing parts,
manuals, or engineering drawings.

The Software Checklist, which catalogues all software that is normally supplied with the system.
Each item should be checked off by the customer and the DEC Field Representative.

The Accessory Checklist, which catalogues all of the hardware items normally supplied with the
system. Each item should be checked off by the customer and the DEC Field Representative.

RS09 Data Sheets, which supply further information for the DEC Field Service Engineer.

5.7.2 Diagnostics
Three diagnostics are run. They are:

Disk Data (MAINDEC-09-D5AA), which is a series of address and data reliability routines that
verify to the user correct operation of the control and disk.

Multi Disk (MAINDEC-09-D5BA), which is a high speed confidence test that operates in two
modes. In the first mode (SAVE MODE), the disk tested is restored to its original state after it
is exercised with random data. In the second mode, the original data on the disk is destroyed.

Diskless (MAINDEC-09-D5CA), Part I; which checks-out the RF09 logic in detail. The diagnostic
requires several minor hardware changes that are described in the diagnostic writeup.

5.7.3 System Software
The system is operated using the checkout procedure in the Advanced Software System Checkout Package for
Bulk Storage Systems. If the computer system has DECtape, this package includes a complete set of advanced
software manuals, a DECtape monitor for RF09 bulk storage, and peripheral routines for bulk storage on DECtape. If the computer system does not have DECtape, the package then consists of a complete papertape advanced software system and a complete set of advanced software manuals.
The successful demonstration of both the diagnostics and the system software constitutes the acceptance
procedure. Any discrepancies found must be listed in the Customer Acceptance Form.
5.8 SHIPPING
If a DECdisk System is to be shipped from one point to another (as a complete unit or in parts), it should be
prepared and packed according to the packing instructions of Engineering Drawings PI 3700006 and PI 3700014.

5-11

Chapter 6
Organizational Maintenance

Organizational or first level maintenance refers to maintenance that can be performed on the equipment at the
site without using special test equipment. Organizational maintenance is subdivided into three areas: preventive
maintenance; adjustment procedures; and diagnostics.
6.1 PREVENTIVE MAINTENANCE
Preventive maintenance includes visual inspection of the DECdisk system according to the list in Table 6-1 , and
performance of the maintenance tasks listed below.
a.

The prefilter of the purge unit must be removed and cleaned once each month. The prefilter
part number is 7407181 (see Figure 6-1).

The absolute filter of the purge unit must be replaced every six months. The absolute-filter part
number is 12-09388 (see Figure 6-1).
Table 6-1
Visual Inspection Checklist
Item

Mechanical Connections

Wiring and Cables

Air Filters

Check
a.

Check that all screws are tight and that all mechanical
assemblies are secure.

Check that all crimped lugs are secure and that all lugs
are properly inserted in their mating connectors.

Check all wiring and cables for breaks, cuts, frayed
leads, or missing lugs. Check wire wraps for broken
or missing pins.

Check that no wire or cables are strained in their normal
positions or have severe kinks. Check that cables do not
interfere with doors, and that they do not chafe when
doors are opened and closed.

Check all air filters for cleanliness and for normal air movement
through cabinets. Check the purge unit and purge hose for cracks.

6-1

Table 6-1 (Cont)
Visual Inspection Checklist
Check

Item
Modules and Components

Check that all modules are properly seated. Look for areas of
discoloration on all exposed surfaces. Check all exposed capacitors for signs of discoloration, leakage, or corrosion. Check
power supply capacitors for bulges.

Indicators and Switches

Check all indicators and switches for tightness. Check for
cracks, discoloration, or other vjsual defects.

PRE-FILTER

ABSOLUTE
FILTER

Figure 6-1

Purge Unit and Filters

6-2

6.2 RS09 ADJUSTMENTS
Organizational level adjustment procedures on the RS09 include calibrating the five GOB5 read amplifiers for
gain and slice. (The output voltage of each GOB5 for the three timing tracks should be an average of 6V peakto-peak, and the slice level for all readers should be 1.1 V.)
6.2.1 Measuring the Gain
The output of a properly calibrated reader varies around the track because of variations in the surface.
Figure 6-2 shows the output for a complete revolution from an A track. The gain is calculated by estimating
the average voltage around the track. This is done by measuring the peak-to-peak voltage at the lowest point
and the highest point, adding the measurements together, and dividing by two.

Figure 6-2 Measuring Gain, The A Track Over One Revolution

6-3

6.2.2 Measuring the Slice
The slice level for all readers should be set at 1.1 V. To measure slice, set up the oscilloscope as shown in
Figure 6-3. The output of the amplifier is added to the output of thc slicc. The two peaks of the resultant
waveform are averaged after the sHce overshoot is subtracted, and the reuslt is the slice level.
The equation to calculate slice is
A + B - Overshoot
2

,which must be = 1.1V.

To establish the zero crossing, locate the gap and set the zero line on the trace as it passes through the gap as
shown in Figure 6-2. Increase the trace frequency until the waveform of Figure 6-3 is displayed.
6-2.3 Calibrating the Read Amplifiers
This procedure uses a dual trace oscilloscope (such as the Tektronix 453). Pull the RS09 electronics out on its
rack and remove the protective plate which covers the pins, as shown in Figure 6-6.
To calibrate the A Track, perform the following steps:
Step

Procedure
Place the first probe on location B02E and place the probe's ground strap
on B02C.

Place the second probe on location A02T and place the probe's ground strap
on B02e.

Set the average voltage to 6V peak-to-peak.

Set the slice to 1.1 V. Waveforms are shown in Figure 6-3.

To calibrate the B Track, perform the following steps:
Step

Procedure
Place the first probe on location B03E and place the probe's ground strap
on B03C.

Place the second probe on location A02T and place the probe's ground
strap on B03C.

Set the average voltage to 6V peak-to-peak.

Set the slice to 1.1 V. Waveforms are shown in Figure 6-4.

To calibrate the C Track, perform the following steps:
Step

Procedure
Place the first probe on location B04E and place the probe's ground strap
on B04C.

Place the second probe on location A04T and place the probe's ground strap
on B04e.

Set the average voltage to 6V peak-to-peak.

Set the slice to 1.1 V. Waveforms are shown in Figure 6-5

6-4

GAIN+SLlCEJ

GAIN

OS CI LLOSC OPE
AC

AE
AV

G085

AF
BS
1 st PROBE
BT

2 nd PROBE

BU
.5J.1s/cm

1 volt Icm
09-0403

Figure 6-3 Measuring the Slice of the A Track

6-5

GAIN+SLICE

5 LICE

GAIN

200ns/em
1V/em

Figure 6-4 Measuring the Slice of the B Track

6-6

GAIN+ SLICE

SLICE

GAl N

2.J.L se e/ em
t VI em

Figure 6-5 Measuring the Slice of the C Track

6-7

The Data Track Reader is calibrated from the average track of each matrix. The average output voltages per
matrix and their gain are posted on the disk itself for these two tracks. (This information is also listed on the
disk data sheets.) These tracks were selected at the factory, and their outputs were recorded when all 1s were
written on the disk. The first step is to load the Disk Data program and write all 1s. The average track is then
locked into, using the STAMP portion of Disk Data (starting address 171, push continue).
To calibrate the Data Tracks, use the following procedure:
Procedure

Step

Place the first probe on location BOSE and place the probe's ground strap
on BOSC.
2

Place the second probe on location AOST and place the probe's ground
strap on BOSe.

Set the average voltage to the value indicated on the front of the disk.

Set the slice to 1.1 V.

Repeat this process for the matrix 1 amplifier located at AB07.

6.2.4 Changing the Timing Tracks
An extra set of timing tracks is always recorded on the disk. This set is to be used if the first set is accidentally
erased in the field. To bring the second set into operation, reverse the timing track head cable connector at the
RS09 electronics, slot AOl. (The gain settings on the A, B, and C Tracks should be recalibrated.) This procedure disconnects the damaged tracks and connects the spares. If the spares are also damaged, the timing tracks
must both be rewritten, using the Timing Track Writer explained in Chapter 3 and used in Chapter 7.
A view of the RS09 electronics with posted data is shown in Figure 6-6.
6.3 DIAGNOSTICS
There are three programs that are run to verify that the system is operating properly or to locate faults. These
programs are available from the program library, along with complete descriptions of how they are used. The
pro gram s are:
a.

Disk Data (MAINDEC-09-0SAA), which is a series of address tests and data reliability routines
that verify for the user correct operation of the control and the disks.

Multi Disk (MAINDEC-09-0SBA), which is a high-speed confidence test that exercises each disk with
random data. It can operate in one of two modes: in SAVE MODE the original contents of the disk
are restored after the exercise, and in the normal mode the original contents are destroyed.

DISKLESS Part I (MAINDEC-09-DSCA), which checks out the RF09 controller. The set-up instructions are given in the DISKLESS description with the procedure, Note that Part 2 is to be run
by a qualified Field Service Engineer only.

6-8

POSTED DATA

PROTECTIVE

Figure 6-6 RS09 Electronics Showing Posted Data

6-9

Chapter 7
Field Level Maintenance

Field or second level maintenance includes complex work performed on the equipment using special repair kits
and diagnostics. This chapter is to be used by DEC Field Engineers. Only qualified DEC Field Engineers with
the necessary special service equipment should attempt to perform the following procedures.

7.1 FIELD LEVEL RS09 AND RFQ9 MAINTENANCE
If problems occur in the RF09 or RS09 that cannot be solved using the methods of Chapter 6, the following
checkout procedures should be followed. The primary tool for this checkout is the DISKLESS
(MAINDEC-09-DSCA) diagnostic, which allows the Field Engineer to first test' the RF09 alone, and then to test
the RF09/RS09 combination. In both cases, the disk assembly itself is not used.

7.1.1 RF09 Off-Line Checkout Without the RS09
The following equipment is needed for this checkout:

1 PDP-9 or PDP-9/L

1 Tektronix 453 oscillosoope or equivalent.

I DISKLESS program complete with listings and writeup

I RP09

Perform the following steps:
Step

Procedure
Load the DISKLESS program, and then follow the set-up instructions.

Verify the delays in the cautroner by running the appropriate section of
DISKLESS listed in Table 7-1, and observing on the oscilloscope the points
indicated. Note that these delays are fixed. If they are outside the specification, the external component should then be checked.

Run Part 1 of DISKLESS. When the RF09 allows the program to sequence
through all tests, the controller is ready to accept an RS09.

7-1

Table 7-1
Setting Up RF09 Delays
Scope Points
Check Channel
B

Delay

Program

Sync Channel
A

MXFR

Part I
Test #23

Cl8BI

D20F2

130 ms
±20%

SEQ ERR

Part 1
Test #22

D13H2

Dl3F2

500 ns
±20%

A Test

Part I
Test #22

C27NI

F28KI

5 MS
±20%

ATP Noise
Suppressor

Part I
Test #15

E30H2

E30F2

1.2 MS
±20%

ATN Noise
Suppressor

Part I
Test #15

E30M2

E30T2

1.2 MS
±20%

INh RD

I/O Reset
Test

CI8R2

D25CI

200 MS
±20%

INh RD

Part 1
Test#15

CI8S2

D25CI

200 MS
±20%

INh RD

Part 1
Test #22

C18T2

D25C1

200Ms
±20%

INh RD

I/O Reset
Test

CI8U2

D25C1

200 MS
±20%

PSLER

Part I
Test #7

DI3M2

DI3T2

1.5 ms
±20%

Limits

7.1.2 RF09 Off-Line Checkout with the RS09
A complete description of this procedure is given in Part 2 of the DlSKLESS program. The equipment needed is:

I PDP-9 or PDP-9/L

1 Tektronix 453 oscilloscope or equivalent

c.
d.

1 DISKLESS program with listings and writeup
1 RF09
I RS09
I Head Simulator cable
I M908 Y A module

f
g.

After the DISKLESS program sequences through Part 2 of the test, the RF09/RS09 combination is ready to
accept the disk assembly.

7.2 FIELD LEVEL DISK ASSEMBLY REPAIRS
The RS08-M disk assembly is the most sensitive of the DECdisk units. The parts of the disk assembly usually requiring replacement are the shoes and the surface itself. A shoe can be damaged electrically (by a burned out
diode or resistor on the G681 B card) or mechanically (if the shoe crashes into the surface or breaks a lead from
the head to its card). In either case, the assembly must be removed from its cabinet and disassembled.

7-2

The disk surface itself may be damaged electromagnetically (by stray fields or accidental currents through the
heads from multimeter, for example) or mechanically (by a crashing head). In the first case, the two sets of
timing tracks may have to be rewritten with a portable timing track writer designed for this purpose. The assembly does not have to be disassembled for this procedure. The procedure is outlined in Paragraph 7.2.4. If
the disk surface is damaged mechanically, the'surface must be replaced. The assembly must be removed from
its cabinet and taken apart. When a new disk is mounted (or even if the old disk is removed and remounted),
the timing tracks must be rewritten with the timing track writer.

Each time a shoe or a surface is replaced, the system should be recalibrated following the procedures of Paragraph 7.3.
7.2.1 Removing the Disk Assembly
In order to gain access to the shoes or the disk surface, the disk assembly must be removed from its cabinet and
dismantled on its mounting square. The kit shown in Figure 7-1 is provided for this purpose.
Turn off all power to the system and proceed as follows:
Procedure

Step

Pull the disk electronics out on its rack as shown in Figure 7-2.
2

Unplug the head cables from the RS09 electronics.

Unplug the purge hose and the motor power leads shown in Figure 7-3.

Remove the four bolts that hold the assembly to its rails.

Pull the disk out of its cabinet and mount it on the mounting square found
in the kit.

Remove the twelve mounting screws that hold the cover on. Note that
these screws are found along the sides of the assembly. On some diskassembly versions there are four Il10re screws in each corner that holds the
shock mounts in place. Do not remove these screws.

Remove the cover (see Figure 7-4). The cards which hold the shoes are now
accessable as shown in Figure 7-5. Be careful not to contaminate the heads or
the disk surface itself.

7.2.2 Removing the Disk Surface
To remove the disk surface, perform the following steps:
Procedure

Step

Dismantle the assembly, following the instructions of Paragraph 7.2.1.
CAUTION
Do not turn the disk clockwise while it is in contact with the
heads.

Remove the four hex screws on the disk hub (see Figure 7-4).

7-3

ALIGNMENT DISK

SURFACE STAND
DIAL INDICATOR
SPARE HEAD
ASSEMBLY

Figure 7-1

Disk Assembly Dismantling Kit

7-4

HEAD CABLES

PURGE HOSE

Figure 7-2 Removing the Disk Assembly from the Cabinet

7-5

PURGE HOSE
---DISCONNECT
POINT

e '.
MOTOR LEADS
DISCONNECTED
HERE

•

••
...
•
o

•1

Figure 7-3 Disconnecting Motor Leads and Purge Hose

7-6

DISK SURFACE

Figure 7-4 Disk Assembly With Cover Removed

7-7

HEAD CABLES

Figure 7·5 Disk Assembly With Cover and Surface Removed

7-8

Step

Procedure

Remove the disk surface by lifting it straight up while giving it a slight counterclockwise twist in order to clear the heads.

Note'which surface was used. Place the disk on its stand. Be careful that it is
not contaminated with dirt.

7.2.3 Replacing the Shoes
To replace the shoes, perform the following steps:
Step

Procedure
Dismantle the assembly according to the instructions of Paragraph 7.2.1, and
then remove the surface using the procedures outlined in Paragraph 7.2.2.

Locate the damaged shoe (see Figure 7-6). If it is an inside shoe, the outside
shoe must then be removed first. Remove the damaged shoe.

Examine the new shoe. If it must be cleaned, flush it with Methanol spray
and blow it dry. If any contaminants remain, saturate a cotton swab with
Methanol and carefully wipe the head. Insert the new head.

To align the heads, cut out a single layer of Kimwipe approximately 4 in. x 4 in.,
and lay the Kimwipe over the motor hub to ensure a tight fit for the alignment
disk.

. " . " " , - - - 0 0_ _ _ _

"".~-...'"".,.

- -- --

Figure 7-6 Shoe Assembly Removed

7-9

----

Step

Procedure

Gently fit the alignment disk over the tissu~ and hub until it is well seated.
Ensure that the heads are seated firmly against the "disk.

The outermost track on every pad must be in line with its scribe line on the
disk, as shown in Figure 7-7.

Start with the outermost track on pad 0 (see Figure 7-8) and set it so that its
inner edge is just touching the inside edge of the outside scribe line. Rotate
the motor so that the radial line is over the next pad. Check that its outside
track is lined up with the next track on the disk.

If any track is off center, loosen the three mounting screws on the bottom of
the block and position it properly.

7.2.4 Replacing the Disk Surface
To replace the disk surface, perform the following steps.
Step

Procedure
Clean the disk surface that is to be replaced with a mild soap and Kimwipes.
Do not forget which side is to be used.

Place the platter down on the hub and rotate it slightly counterclockwise.

Check the disk surface with the dial gauge. The disk surface must be flat
to within 1 mil through 3600 •

Tighten the four hex nuts just enough to lock the washers.

Recheck Step 3. Adjust the hex nut pressure to compensate for any TIR
(Total Indicated Runout), that does not meet specifications.

Replace the cover.

7.2.5 Rewriting the Timing Tracks
When a new surface is installed or an old surface removed and replaced, the timing tracks must be rewritten. This
is done with the Timing Track Writer (shown in Figure 7-9) as follows:
Step

Procedure
Install the disk into its rack, following the instructions of Chapter 5.

Remove the de voltage from the RS09 logic. This can be accomplished
by turning the power off at the main console of the computer. The ac
power to the disk unit and the purge unit must remain on.

Remove the timing track cable from the RS09 unit. The cable is located
in SLOT A 1 of each RS09.

Remove the cover from the RS09 Timing Track Writer and remove the dcwiring cable from the box. The dc-wiring cable contains four wires with
Heco Tab connectors on the ends. The wire color coding is:
a.
YelJow +20V
b.
Red
+10V
c.
Blue
-15V
d.
Black
GND

7-10

L:]
I

~ LINE UP OUTERMOST
I~
TRACK WITH THE

SCRIBE LINE - I

RESPECTIVE SCRIBE LINE

OUTER CIRCUMFERE NCE
OF DISK

MOUNTING BLOCK

_MOUNTING SCREWS

09-0411

Figure 7-7 Aligning the Heads

7-11

Step

Procedure

Mount the Timing Track Writer box in the cabinet via the holding pins on
the rear of the tester box. These pins should slide into the prepunched holes
in the cabinet frame directly above the RS09 logic.

Insert the dc-power cable for the Timing Track Writer between the disk unit
and the disk logic. The cable plugs into the de power bus on the rear of the
RS09's disk chassis. Insert the individual wires into the proper voltages as indicated on the rear of the RS09 chassis. (All wires and tabs are color coded
for easy identification.)

Insert the timing track cable from the disk into the slot provided in the front
of the tester.
NOTE
This cable is a dual connector and may be plugged in on either
side.

Turn power on. Power (de) should be applied to the RS09 logic as well as the
tester.
NOTE
Complete steps 9 and 10 as quickly as possible after turning the
WRITE VOLTAGE switch ON. Failure to do so will damage the
head center tap resistors that are inside the disk enclosure.

;;:;

e;~

TIMING TRACK PAD

J-~~

OUTERMOST TRACK OF
PAD 0 LINES UP WITH
OUTERMOST SCRIBE LINE

NOTE:
The numbering system used to designate pads is only for
representation. It is not necessarily the way the pads are
actually numbered.
09-0412

Figure 7-8 Aligning the Heads

7-12

Figure 7-9 Timing Track Writer

7-13

Step

Procedure

Select the proper disk Control (PDP-9 /PDP-IS) and motor speed; i.e., SO or 60
cycles via the switch on the front of the tester. (Note that the PDP-9/PDP-IS
switch is not shown on the model of Figure 7-9. This switch is included in later
modek)

Set the WRITE VOLTAGE enable switch on the front panel to the ON position.
The red indicator light should illuminate.

Press the WRITE button under the freq uency selector to begin the actual writing.
The Timing Track Writer automatically recycles if the gap is not correct and indicates this via a flashing INC (increase) or DEC (decrease) light. To correct the
gap, turn the knob clockwise if INC is flashing, and counterclockwise if DEC is
flashing. When the gap is correct, OK lights and the writer stops.
To ensure that writing has been successful, push thl~ WRITE button once more
without adjusting the knob. The OK light should come on without flashing either
the INC or DEC lights.

Set the WRITE VOLTAGE switch to OFF. Turn the power off and remove the dc
power lines from the RS09 and tester. The Timing Tracks should now be properly
recorded.
NOTE
Use the Timing Track Writer as little as possible. The Timing
Track Writer drives 1W through 1/8-W head resistors. If it is
used for too long a period, these resistors burn out. Writing
stops when the OK light illuminates.

Plug the Timing Track cable from the RS08-M into slot AO I of the RS09 Logic
Panel.

Turn system power ON. Adjust the three Timing Track read amplifiers (G08S)
for 6V peak-to-peak and 1.1 V slice, using the methods outlined in Chapter 6,
Paragraph 6.2.
Be sure to test both sets of tracks. By reversing the Timing Track cable at location AO 1, the second set of tracks is available to the RS09.

After writing new timing tracks, the unit should be thoroughly tested with its diagnostics. This is done by writing
data usinR one set of timing tracks, then swapping this set for the other and reading the same data back. Before
this is done, the Timing Track Readers should be adjusted for gain and slice following the procedures of Chapter 6,
and the surface modulation of the disk should be checked according to the procedure of Paragraph 7.3.1. The
procedure to calibrate the data heads should be carried out, as outlined in Paragraph 7.3.2 and 7.3.3.
7.3 FIELD LEVEL RS09 CALIBRATION
If a new surface or new shoes have been installed, calibration should be carried out and recorded on the sheets

illustrated in Figure 7-13. The tests include one test to measure surface modulation and several tests to measure
the mean voltage of each matrix and establish an optimum gain for the readers.
7.3.1 Measuring Surface Modulation
This test is done on the A track only. Surface mod ulation is the result of variations in the properties of the
surface around the disk. It is measured using the following procedure.

7-14

Step

Procedure
Connect a calibrated oscilloscope probe to pin A02T of the RS09 (A Timing
Track read amp).

Connect the oscilloscope ground strap to A02C.

Place the oscilloscope setting on dc.

Trigger the oscilloscope on LINE.

Set the time base to 5 ms/CM.

Measure Vmax pp and Vmin pp, as shown in Figure 7-10. Surface modulation =
Vmax pp - Vmin pp
x 100 (Surface modulation should be less than 20%.)
Vmax pp + Vmin pp

Figure 7-10 Measuring Surface Modulation on the A Track

7-15

7.3.2 Analyzing the Gain of the Data Tracks
When a new disk surface is installed or heads are replaced, the data tracks should be recalibrated. This process
involves measuring the mean voltage from each head, the mean value for each shoe, and the percentage deviation
for each matrix. Percent deviation is a measure of the difference in the readings. The smaller this value is, the
more consistent the readings are in the matrix. In order to reduce this deviation, the shoe with the lowest
reading is given a 20 percent boost in gain; and the deviation is recalculated. If the result is a reduction, a jumper
is then installed in the RS09 to affect the increase in gain when that shoe is selected. The next lowest shoe is
tried to see if a 20 percent increase in gain for it reduces the percentage of deviation further. If the percentage
of deviation is reduced another jumper is installed. This process continues until adding more gain to the next
shoe does not decrease the percentage of deviation.
The readings taken during this calibration are recorded on the Head Data Sheet. When all of the readings have
been taken, the average shoe for each matrix is located; and its readings posted on the disk as a calibration
standard to set the G085 readers in the future. The procedure to carry this out is as follows:
Procedure

Step

Obtain the following equipment:

a.
b.
c.
d.

1 PDP-9 or PDP-9/L
1 DECdisk system
I Tetronix 453 oscilloscope or equivalent
I Disk Data diagnostic (MAINDEC-09-D5AA)

Load the Disk Data diagnostic and write all 1s on all tracks.

Go to the STAMP test of Disk Data. This test allows the operator to select
any track he wishes to examine by loading its number into the Switch
register. (The relationship between the selection lines at the RS09 and the
Switch register bits 11 to 17 are transferred by STAMP into bits 0 to 6 of
the AC, and from there into bits 0 to 6 for the Track Address register. Bits
o to 6 of the Track Address register are in turn translated into T06 to TOO
at the RS09 selection matrix. The sequence is summarized below.)
Matrix

Head

Shoe

Switch Register

12,13,14

15,16,17

Track Address
Register

1,2,3

4,5,6

RS09 Track
Select Lines

T06

T05, T04, T03

T02, TOI, TOO

Calibrate the oscilloscope and compensate the oscilloscope probes.

Take arithmetic mean peak-to-peak readings on each head of matrix,
according to the techniques outlined in Chapter 6. Probe I should go
on A05T and probe 2 on B05E. (Refer to Engineering Drawing
D-BS-RS09-0-5.)

Repeat Step 5 for matrix 1. Probe I goes on A07T and probe 2 on
B07E. Record the reading on the Head Data Sheet.

7-16

Step
7

Procedure
From the previous readings, find the percentage of deviation for each shoe,
using the formula:
Vmax - Vmin
Vmax+Vmin

X 100 = % deviation

where: Vmax is the largest mean peak-to-peak voltage taken on that shoe, and
Vmin is the smallest mean peak-to-peak voltage taken on that shoe.
This value should be less than 20 for any shoe. If it is more than 20, the shoe
should be replaced.
8

Find the mean peak-to-peak voltage for each shoe with the formula:
Vmax + Vmin
2

A mean

From the mean for each shoe, calculate the percentage of deviation for each
matrix with the formula:
Amax - Amin X 100 = 01/0 deVIa
. t·Ion
Amax + Amin
where: Amax = the maximum mean of all shoes
Amin = the minimum mean of all shoes
Attempt to reduce the percentage of deviation by adding 20 percent of the
lowest reading to itself. Repeat this for the next lowest reading and check to
see if it reduces the result. Continue this procedure until 7 shoes have been
added to, or the percentage of deviation starts to increase. If the percentage
of deviation decreases further when an eighth jumper is added, the computation has been done incorrectly. An average of four jumpers are used. This
process is illustrated in the following example:
Example:
A Mean
0
1

2
3
4
5
6
7
%

A Mean

7.62
6.35 (Min) + 20% = 7.62
7.21 (Min) + 20% = 8.65 (Max)
7.21
7.47
7.46
7.46
8.00 (Max)
8.00
8.00
7.65
7.65
7.65
7.40 (Min)
7.40
7.40
7.65
7.65
7.65
7.46
7.46
7.46
Dev
11.5 %

5.2 %

7.8 %

(a)

(b)

(cJ

Look for minimum % deviation.
a.

8.00 - 6.35
1.65
- - - - - x 100 = - - x 100
14.35
8.00 + 6.35

7-17

11.5%

Procedure

Step
9 (Cont)

0.79
15.21

% Dev = - - = 5.2%
1.25
% Dev = - - x 100 = 7.B %
16.05

By increasing shoe 0 by 20 percent, the deviation was reduced to a minimum.
In order to effect this increase in gain on this shoe, a jumper must be installed
in the logic of Engineering Drawing D-BS-RS09-0-1. Table 7-1 indicates the
proper jumper for each shoe. In this case, assuming matrix 0 was under test,
pin B 17M would be jumpered to pin B20D.
Example b in step 9 is now the true set of means for the shoes in that matrix.
Using these means, calculate the average track from the formula:

Amax + Amin
2

- - - - - - = Average track

Find a track that is within 10 percent of the mean peak-to-peak voltage, but
that is not in a shoe that has a gain jumper, and identify it as the average of
that matrix. Repeat the procedure for the other matrix. From the example:
8.00 + 7.21
2

7.655

Since the track's means are not part of this example, the actual average track
cannot be shown. (It is most likely to be in shoe #4, however.)
If a track without a gain jumper within 10 percent of the average track cannot
be found, multiply the average track value times 5/6 and look for a track in a
shoe with a gain jumper that comes within 10 percent of this number. Once a
track has been selected, multiply that track value by 6/5 to take oscilloscope
readings.
Table 7-2
Jumpers to Increase Gain
Shoe #

Matrix
o Gain

Matrix
1 Gain

XXO
XXI
XX2
XX3
XX4
XX5
XX6
XX7

Bl7M
Bl7N
Bl7P
B17R
B17S
B17T
BI7U
B17V

B20D
B20E
B18D
Bl8E
B18H
B18)

B20K
B20L
BIBL
BIBM
B18P
BI8R

To Matrix 0 gain
OR Matrix 1 gain

If 7 shoes req uire gain, run the matrix wire B IBV to B 18K (Matrix 0) or to
B18S (Matrix 1); and add a jumper B 18T or B 18U. No matrix should ever
need more than 7 jumpers.
11

Using the RS08-M test data sheet that accompanies the RSOB-M, list the
Arithmetic Mean (A mean) on the next column after each shoe.

7-IB

Step
11 (Cont)

Procedure
2.

Star those shoes requiring gain jumpers.

Circle the track in each matrix used as the reference for the G085 gain
adj ustment.

Record each reference track and its respective peak-to-peak voltage
setting (computed on the RS09 Test Data Sheet) on both the RS08-M
Test Data Sheet and the cover of the disk.

7.3.3 Calibrating the Gain of the Data Readers
In the previous paragraph, the optimum configuration for minimum percentage of deviation was established
among the shoes. In this paragraph, the optimum gain for each reader is determined. This is done by determining the operating range of the slice-to-gain ratio. The highest operating gain with the smallest operating
slice is found; and, conversely, the lowest possible gain with the highest possible slice. When these two ratios
are found, the gain is set to the point that lies midway between the two at a normalized slice of 1.1 V.
The Disk Data program is used to run optional test patterns. Proceed as follows:
Step

Procedure
Run the optional pattern on the entire disk.
first word
second word

525252
00000 I

Go to READ mode. Set the slice of the first matrix reader to 1.1 V from the
average track. Raise the gain of that reader until one failing point occurs. If
no failure occurs, leave the gain on maximum and start to lower the slice below 1.1 V. When a failure occurs, scope these points and determine the reason
for the failure. Figure 7-11 illustrates the waveforms.

Repeat Step 2 for the other matrix.

Run the optional pattern on the entire disk
first word
second word

00000 1
525252

Repeat Steps 2 and 3.

Go to READ mode. Set the slice of the first matrix reader to 1.1 V from the
average track. Lower the gain of the reader until a failure occurs. If there is
no failure at the lowest gain, start to raise the slice level above 1.1 V until a
failure does occur. Scope these points and determine the reason for the
failure. Record these readings. Figure 7-12 illustrates the waveforms.

Repeat Step 6 for the other matrix.

Run the optional pattern on the entire disk.
first word
second word

525252
00000 1

Repeat Steps 6 and 7.

7-19

Step
10

Procedure
Calculate the optimum gain for each reader from these readings. This is done by
taking the lowest maximum gain and the highest minimum gain from the two
tests, normalizing to 1.1 V and finding the center point between the two gains.
Example:
High gain = 14 failed at slice .8V.
Low gain = 4.8 slice at 4.6V.
Normalized gain

14 x 1.1
8
= 19 for high
4.8 x 1.1
4.6

- - - = 1.15
Gain setting should be

]9-1.15
2

= 8.9

The average track should be selected, and its mean peak-to-peak output voltage
set at 8.9V. This step should be repeated for the other matrix.

SYNC ON RO SR
2}1lec tern 1V tern

Figure 7-11

Maximum Gain, Minimum Slice

7-20

SYNC ON RD SR
10 jJ.sec /cm 2V /cm

Figure 7-12 Minimum Gain, Maximum Slice

7-21

Rs~8M

DATE:

BY:

DISK
_ _ _ MFG.&#

SCOPE
PREAMP
TYPE & #: _~f_5'_3___ TYPE & 1/:

AGe

POS.

DATA SHEET

GRAMS
PER SIDE
~

13J-

HEAD
TESTER II:

!1&"e.

TYPE
PROBES:

SIGNAL READING

AFTER
A
MEAN GAIN COMMENTS

~hOf7

C.d- t.i 5.1 /.. () t.t, /,.8 (,. 7 t.' h.3~ 7. t, J-

7. D 7.1 7.~ 7.1 7./ r-7. tf- 17.0 7.3 7.J.1 /. J- \
~.)- lb 7.~ 7.d- 7,D 7.~ 7.~d- ~. ~ 1.ito /.iff.,
B.O 8.5 7.~ 7.D 7. J. r..7.b 8.S to 8.0 B.()

7.J.~ 7. ~

to.S t.' 1.0 ~.~ (,.1 7.8 1.D 7.0 1.Lf

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~.~ 1.~ 7.D

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10.0 ~.8 ~.5 5. 5 5.1 ~ 5.~ 5.8 ~.7S ~.7S

5't, ~.Io 5.8 1.1 ~,\ s.~ 5.L/- 5. J(
5.J- {.O 5.D {.Io 53 ~} 1.~ 1./0 j.1 Ie./).
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~D 1,1 1·8 '1.1 1., 1.8 J.j.b if,;;: J-j,~ 5·sJ-

13
14
15
16
17

*
~

16
17

X /0

o3ff.)/~

MOTOR
FREQ. :

----_._---_._-----

"'--

1-~

17 l.b 7.~ 8.D /.3 '7.~{ 7.C~

\.~ 1,\ 1,'} 1.B 1"

I.~

5.~ 5.~

01234567

DEC 3-1073

Figure 7-13 RS09 Test Data Sheet (Sheet 1)

7-22

RS09 TEST DATA SHEET
RS08M# _ _ _ _ _ _ _ _ _ _ _ __
Date _ _ _ _ _ _ _ _ _ _ __
RSO~

# _______________________

RF09

# __________________

Namc _ _ _ _ _ _ _ _ _ _ __

Surface Modulation on A Track _ _ _ _ _ _ _ _ 0/0
MAX GAIN/SLICE RA

no
Matrix 0

Matrix I

High Gain Setting

Low Slice Setting

c
- - - =[)-

Matrix 0

Reason for Failure _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___

Matrix I

Reason for Failure _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Matrix 0

MIN GAIN/SLICE RATIO

Matrix I

Low Gain Sctting

High Slice Setting

Matrix 0

Reason for Failure _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___

Matrix I

Reason for Failure _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Using the reading obtained above - Compute:

Matrix 0 =B = XO = - - - - - - - - - -

Matrix I ="0'" XI = - - - - - - - - - - j=YI
XO + YO = lO = _ _ _ _ _ _ _ _ _ _ _ _X_I_+_Y_I = l I = _ _ _ _ _ _ _ _ _ __

Setting slice to 1.1 V compute:

lOx 1.1 = _______
II x 1.1 = _______

= Voltage setting of Ave track in each matrix respectively

Now set slice to 1.1 V and set the voltage gain settings of the Ave track to the values obtained above.
Compute figurc of merit.
XO-YO
XO + YO x 100 = FM

XI - YI
-+-- x 100 = _ _ _ _ _ -X-I-+-Y--I x 100

Figure 7-13 RS09 Test Data Sheet (Sheet 2)

7-23

-+-·x 100= _ _ __

Appendix A
RF09 Signal Summary

Signal

Summary

ADROK

ADdRess OK logic signal. A true signal exists whenever the DS Register
equals the WA Register, APAR is a zero, and the CTL bit has successfully
shifted through all positions of the DS Register.

ADS TO lOB

Signal that places the ADS Register on the I/O Bus.

ADS

Address of Disk Segment. Bits of a register that save the D.S. shift register
for real-time program control read-back.

APAR

Address PARity flip-flop. Computes parity of address read from Disk.
Includes the Control (CTL) Bit.

APE

Address Parity Error

API ENA

Automatic Priority Interrupt ENable A. API Control signal indicating time
for API Address to be put on the I/O Bus.

API I EN IN

Automatic Priority Interrupt level 1 ENable IN. True if no higher priority
device on level 1 is requesting a priority break.

API 1 GR

Automatic Priority Interrupt level 1 GRant. Device requesting API break
was granted service.

API I RQ

Automatic Priority Interrupt level 1 ReQuest to Processor.

APICLR

Address Pointer #1 - CLEAR. The lOT that clears the Disk Address
Register.

API TO lOB

Address Pointer # I to I/O Bus. The lOT that reads the Disk Address
Register onto the I/O Bus.

ATEST

This signal allows A track pulses to enter the A track error detection
circuitry.

ATF SAVE

A Timing track Flip-flop. Remembers which polarity ATT came last.

ATOK

A Timing OK. A timjng pulses are occurring at their normal rate.

ATP

A Timing Pulses. Regenerated OR of the ATT's and AAT's.

ATPM

A Timing Pulse generated by the Maintenance logic.

ATPN

Logical OR of the A Timing Pulses.
A-I

Summary

Signal
ATTN

A Timing Track Negative. Level converted or buffered RS09 signal- ATT.

ATTP

A Timing Track Positive. Level converter or buffered RS09 signal + ATT.

ATT

A Timing Track. RS09 interface clocking signal. Unrectified signal pairs
of this signal are designated + ATT and - ATT.

Buffer Register.

BR TO lOB

Place BR on I/O Bus.

BRCLR

CLeaR the Buffer Register.

BR TO SR

Transfer the Buffer Register TO Shift Register.

BTER

B Timing track ERror. Missing or extra signal from the BTT.

BTF

B Timing track Flip-flop. Remembers which polarity BTT came last.

BTN

B Timing track Negative. Level converted or buffered RS09 signal - BTl'.

BTP

B Timing track Positive. Level converted or buffered RS09 signal + BTT.

BUSY

Requested Disk transfer not completed.

BTT

B Timing Track. RS09 interface signal containing the eleven bit address
of the disk segment. Unrectified signal pairs of the address track are
+BTT and -BTT.

CHDSA

Data CHannel and Device Select A. lOT (code 70) OR'd with DCH ENB.

CLR

CLeaR - the OR of all clear signals.

CTER

C Timing track ERror. Missing or extra signal on the CTT lines.

CTF

C Timing track Flip-flop. Remembers which polarity of CTT was last
present.

CTL

ConTrol. First bit read from the BTT. Used to control checkit;lg of the
DS with the WA and shifting of the DS register.

CTN

C Timing track Negative. Level converted or buffered RS09 signal- CTT.

CTP

C Timing track Positive. Level converted or buffered RS09 signal + CTT.

CTP 1

C Timing Phase 1. First bit of a one bit 3-position ring counter used for
word boundary control functions.

CTP2

C Timing Phase 2. Second bit of counter described in CTP 1.

CTP3

C Timing Phase 3. Third bit of counter described in CTP I.

CTT

C Timing Track. RS09 interface word boundary indicator. Unrectified
signal pairs of this signal are designated +CTT and -CTT.

A-2

Signal

Summary

Disk Address. Bits of a three-bit register indicating which disk of eight
is selected.

DASV

DAta SaVe. Accepts each data bit to be shifted into the SR.

DATA ERROR

The OR of a data parity error and a data hardware error flag.

DATA FLAG

Flag raised by the control when DCH Break required. Effectively makes
the DCH RQ.

DCH EN IN

Data CHannel ENable IN. True if no higher priority DCH device requesting a break.

DCHEN OUT

Data CHannel ENable OUT. True if no higher priority DCH devices and
this device (RF09) are requesting a break.

DCHENA

I/O Bus Data CHannel ENable A. Time to place channel address on I/O
Bus for DCH break.

DCH ENB

I/O Bus Data CHannel ENable B. Time to place DCH control signals on
I/O Bus (e.g., RD RQ or WR RQ).

DCHGR

I/O Bus Data CHannel GRant. Sets DCH ENA.

DCHRQ

I/O Bus Data CHannel ReQuest. I/O Bus control signal that requests
DCH Break.

DCHTE

Data CHannel Timing Error. Processor had not completed DCH transfer
before Disk control was ready for the next.

DIOP

Delayed lOP. Provides time for the control to determine its BUSY state.

DISK FLAG

Flag raised by either an ERROR or a XFER CPLT that may be skip tested
under program control and cause an API or PI break request to the
processor.

DISK RUN

Disk transfer requested (BUSY) and a word boundary has been found
(CTP3).

DISK SYNC

DISK SYNChronized flip-flop. Shows a valid CTP3 pulse has occurred.

DPAR

Data PARity flip-flop. The flip-flop that calculates the data parity.

DPE

Data Parity Error. A flag set if there is a parity error in a data word.

DSCLR

Disk Segment register CLeaR.

DSTOADS

Disk Segment TO ADdresS of the Disk Segment Transfer signal.

Disk Segment. Bits of the Disk Segment address II-bit shift register.

DSA

Disk Segment Address. Bits of a register that contain the real-time
DS address readable under program control.

DSAB

Device Select A and B decoded (70 and 72).

DSB

Device Select B (code 72) decoded.

A-3

Summary

Signal
DTE

Data Timing Error. Missing or extra signal on the DIT lines detected here.

DTER

Data Timing ERror. Missing or extra signal on the DTT lines stored here.

DTN

Data Track Negative. Level converted or buffered RS09 signals - DTT.

DTP

Data Track Positive. Level converted' or buffered RS09 signal + DTT.

DTT

DaTa Track. RS09 interface read data signal. Unrectified signal pairs of
this signal are +DTT and -DTT.

EQCMPEN

EQual CoMParison ENable. A signal that enables the WA and DS to
compare.

ERROR

ERROR - the OR of the error flags.

FRCHNG

CHaNGe the Function Register lOT.

FRCLR

CLeaR the Function Register.

FRZ

FReeZe. Signal disables clock input to control as a result of a HDWR ERR
or an APE.

FOO

Function Register bit 0 controlled by AC bit 12.

FOSV

Function Register bit 0 SaVe. Controlled by AC bit 12.

FOI

Function Register bit 1 controlled by AC bit 13.

FISV

Function Register bit 1 SaVe. Controlled by AC bit 13.

HDWRERR

HarDWaRe ERRor. The OR of MNEP, MPEN, BTER, CTER, or DTER.

HIGH

Level indicating that the high-speed transfer rate has been selected.

INCDA

INCrement Disk Address. Occurs after the last word of each disk has been
successfully transferred.

INCTA

INCrement Track Address. Occurs after the last word of each track has
been successfully transferred via the DCH channel.

INCWA

INCrement Word Address register. Occurs for each successful transfer on
the DCH channel.

INHRD

INHibit ReaD. Signal disables the read portion of the control logic to allow
time for the RS09 read amplifiers to recover from an input overload.

INTEN

INTerrupt ENable. Control flip-flop that determines if the DISK FLAG
will cause an interrupt via the API or PI facility. Prog Skip is honored
independently of the state of INT EN.

INTSV

INTerrupt Enable SaVe. Second part of Function Register bit 2 controlled
by AC bit 14.

A-4

Signal

Summary

lOB

I/O Bus driver inputs.

lOB TO APO

Strobe contents of I/O Bus into Address Pointer O.

lOB TO API

Strobe contents of I/O Bus into Address Pointer 1.

lOB TO BR

Strobe contents of I/O Bus into the Buffer Register.

10D

I/O Bus Driver outputs.

lOP 1

Input/Output Pulse 1.

[OP2

Input/Output Pulse 2.

lOP 4

Input/Output Pulse 4.

lOR

I/O Bus Receiver. Level converters and/or buffers for the I/O Bus
interface.

lOT CLR

lOT CleaR. RF09 program controlled "power clear". Only control
lOT recognized when a FRZ condition exists.

10TCONT

lOT CONTinue. The execute lOT that starts the controller executing.

I/O ADDR

I/O ADDRess. I/O Bus address lines used to determine API channel
address as well as DCH channel address.

I/O BUS 00-17

Computer I/O BUS data lines.

I/O OFLO ENB

OR of I/O OFLO and DCH ENB.

I/O PWR CLR

I/O PoWeR CLeaR. I/O Bus power clear line.

I/O OFLO R

I/O OverFLOw Receiver. I/O Bus signal indicating the last DCH break
is in process.

I/O SYNC

The computer SYNC pulse train.

10TCONT

lOT CONTinue. Program command that transfers the contents of the
Function Register Flip-Flop (FO, FI, INT) to the Function Register
Flip-Flop.

LDSR

LoaD Shift Register. Control has found the location of the word to be
Written or Write Checked, has transferred the BR to SR, and is shifting
the data onto the WRITE OATA line.

LDLY

Load DeLaY. A flag set during the Write Check operation to check for
data parity errors.

LIOP4

Load lOP. A delayed OIOP. Provides for a Clear/Load cycle by using
OIOP to Clear and LIOP to Load.

LOCK

RS09 interface signal signifying that the Disk and Track selected is
Write Protected.

A-5

Summary

Signal
LOW

A level that is asserted when the disk is set to the low transfer rates.

LSEN

Load Shift Register ENable. Control signal that allows loading of Shift
Register (SR) during Write or Write Check.

LSTE

Load Shift Register Timing Error. A flag that is set and reset when the
Buffer Register is filled during a Write or Write Check operation. If it
resets too slowly, a DCH timing error is posted.

MAINT

MAINTenance flip-flop. Holds off RF09 delay time-outs during maintenance instructions.

MAT

Maintenance A Timing signal. Program control maintenance logic that
simulates the RS09 head signal to the ATT read amplifier.

MBT

Maintenance B Timing signal. Program control maintenance logic that
simulates the RS09 head signal to the BTT read amplifier.

MCT

Maintenance C Timing signal. Program control maintenance logic that
simulates the RS09 head signal to the CTT read amplifier.

MCTL

Maintenance ConTroL lOT. Simulates RS09 interface signals by transferring AC bits directly into the RF09.

MDT

Maintenance DaTa signals. Program control maintenance logic that
simulates the RS09 head signal to the DTT read amplifier.

MED

A level that is asserted when the disk is selected for MEDium transfer
rates.

MNEP

Missing Negative or Extra Positive pulse from ATT's. Causes HDWR ERR
status.

MPEN

Missing Positive or Extra Negative pulse from the ATT's. Causes
HDWR ERR status.

MTO

Maintenance TOggle. Same as MTOG slightly advanced.

MTOG

Maintenance TOGgle. Maintenance lOT that uses the AC bits to produce
MAT, MBT, MCT, and MDT.

MXFR

Missed X (Trans)FeR. Disk was BUSY and missed transferring data twice
in succession from the same address. More than one Disk revolution
occurred without a transfer.

NDT

Negative DaTa Flip-flop that stores the negative data bit.

NEDSK

NonExistent DisK. Error status indicating an attempt to use a
nonexistent disk. May be caused either by sequencing into or by direct
program command.

OFLO

OverFLOw flag set when the Data Channel overflows during a DECdisk
transfer.

A-6

Signal

Summary

PC + 10TCLR

Power Clear and lOT CLeaR.

PDT

Positive DaTa - Flip-flop that stores the positive data bit.

Program Error.

PIOP4

Pulsed IOP-4. The IOP-4 pulse slightly delayed through a pulse amplifier.

PROGINTRQ

PROGram INTerrupt ReQuest. I/O Bus signal for PI break request.

PSLER

Program SeLect ERror. A nonexistent disk was selected by the program.
One of the inputs to the NE DISK status.

RB FULL

Read Buffer FULL. Control has loaded the BR from the SR and the
processor has not as yet taken the data.

RDCLK

ReaD CLocK. Pulse used to shift the SR during Read or Write Check.
Occurs at ATPD time.

RD DIS

ReaD DISable. OR of INH RD and MAINT. Allows maintenance control
to nullify effect of INH RD.

RDLD

ReaD LoaD. During READ or WRITE CHECK this signal is one of the
elements that enables data parity error detection.

RDRQ

ReaD ReQuest. Signal to processor requesting a read operation during a
data channel transfer.

RDSR

ReaD (into the) Shift Register. Control has found word to be read from
RS09 and is shifting the data into the SR.

RD STATUS

ReaD STATUS. lOT that causes the RF09 Status Register to be read
into the AC.

RD TEST

ReaD TEST. A pulse that clocks the data error flag.

READ

Signal from controller to RS09 enabling the read amplifiers.

RSEN

Read Shift register ENable. Signal used at the word boundary being read.
AND of RDSR and OFLO.

RSTE

Read Shift register Timing Error. A flag that is set and reset when the
Shift Register is filled and loaded into the Buffer Register. If a timing
error occurs, this DCH timing error flags.

SubDevice levels.

SEL ERR

SELect ERRor. Signal return from jumper panel that allocates available
disks to specific SEL lines. Unavailable disks return the SEL ER.

SEL

SELect. Unary decoded signals from the DA register for selecting one
disk of eight.

SELECT

SELECT line from each disk.

A-7

Summary

Signal
SEQER

SEQuence ERror. A nonexistent disk was selected during ajob transfer.

SERCLR

Shift Register CLeaR.

SKIP RQ

SKIP ReQuest to C.P.U.

SRCLK

Shift Register CLocK Pulse.

SRCLR

Shift Register CLeaR Pulse.

SR to BR

Shift Register to Buffer Register transfer pulse.

Shift Register. Serial/parallel disk data converter.

SRI

Shift Register In. Command to transfer data from BR to SR during
Write or Write Check.

SRIF

Shift Register In flag ANDed with the reset Overflow flag to enable
the Data Flag.

SRO

Shift Register Out. True whenever the SR has as~em bled the data word
to be read and the BR is ready to receive it.

STATUS CLR

CLeaR the STATUS register.

STATUS TO lOB

STATUS onTO I/O Bus data lines.

STOP

Prohibits execution of lOTs while RF09 is BUSY.

SYNC

Scope SYNC point when running Diskless.

'fA

Track Address Register.

'fACLR

Track Address CLeaR.

'fA WACLR

Track Address and Word Address CLeaR pulse.

TPI

Timing Pulse # 1.

TP2

Timing Pulse #2.

TOO- T06

Track address lines to RS09.

WACLR

Word Address CLeaR.

Word Address Register. An eleven-bit register containing the address
desired on the disk. The WA is compared with the DS to give ADROK.

Write Buffer FULL. Processor has loaded the BR with data requested
during Write or Write Check and the control has not transferred the data
from the BR to SR.

WLOEN

ENable Write LockOut. If any tracks are locked out, this signal effects
the lockout.

WLO

Write LockOut. Error Status bit that occurs whenever an attempt is made
to Write in an address that is Write Protected.

A-8

Signal

Summary

WR CKER

WRite ChecK ERror. Indicates a comparison error exists between the word
from core memory and the word read from the disk during Write Check.

WRDA

WRite DAta flip-flop that receives the Shift Register output to be written
on the disk.

WRITE

WRITE function decoded from Function Register.

WRITE DATA

RS09 interface signal line over which the RF09 sends the serial data to be
written.

XFER CPLT

X (Trans)FER ComPLeTe. The last word has been transferred to/from
the disk.

XL OW

LOW speed transfer rate selected.

XMED

MEDium speed transfer rate selected.

A-9

Appendix B
RS09 Signal Summary

Signal

Summary

CT 00 X - CT 17 X

Center Tap Selector output signal +20V when selected. Applies current
through the coil of its head.

:tATT (B)

A Timing Track. The positive or negative side of the clocking signal,
Buffered.

±BTT (B)

B Timing Track. The positive or negative side of the address track signal,
Buffered.

±CTT (B)

C Timing Track. The positive or negative side of the delimitter track,
Buffered.

±DATA

The positive or negative side of the data signal.

±DSL 00-01

Data Signal Lines. Bidirectional data lines (positive or negative) between
matrices and Read/Write amplifiers.

LOCK

Interface signal signifying that the disk and track selected is write
protected.

MTRX 0 (1) GAIN

MaTRiX 0 (1) GAIN. Signal that is applied to the G08S of the corresponding matrix to increase its gain by 20 percent when a particular
shoe is selected.

READ

Signal from RF09 to condition the RS09 to read.

SEL (BA)

SELECT line, Buffered.

SELECT

Signal showing that the RS09 unit has been selected.

SELECT 00-07

SELECT lines. Eight lines used to select the disk units.

TOO (0) - T06 (1)

Track address select lines that select one of 128 tracks.

WRITE DATA

Interface line over which the controller sends the data to be written.

WRITE CLK

The OR of the two timing track signals used to clock the G290
Write flip-flop.

B-1