Digital PDFs

DEC-09-H2AB-D

May 1971

33 pages

Original

1.2MB

Document:	LT-19 Multi-Station Teletype Control Instruction Manual Volume 2
Order Number:	DEC-09-H2AB-D
Revision:
Pages:	33
Original Filename:	http://bitsavers.org/pdf/dec/pdp9/datacomm/DEC-09-H2AB-D_LT19_May71.pdf

OCR Text

Digital Equipment Corporation
Maynard, Massachusetts

PDP-15 Systems
Instruction Manual
Volume 1

L T19 Multi-Station
Teletype Control

DEC-09-H2AB-D

LT19
MUL TI-STATION
TELETYPE CONTROL
INSTRUCTION MANUAL

DIGITAL EQUIPMENT CORPORATION • MAYNARD, MASSACHUSETTS

1st Printing December 1968
2nd Printing May 1971

The material in this manual is for informational purposes and is subject to change
without notice.

The following are registered trademarks of Digital
Equipment Corporati on, Maynard, Massachusetts:
PDP
FOCAL
COMPUTER LAB

DEC
FLIP CHIP
DIGITAL

CONTENTS
Page

CHAPTER 1

GENERAL DESCRIPTION

1.1

Introduction

1-1

1.2

Functional Description

1-2

1.3

LT19H Data Communications Cable Option

1-4

1.4

Programming

1-5

1.4.1

LT19B - (1 through 5) Device Selection Codes

1-5

1.4.2

LT19 lOT Instruction Set

1-6

1.4.3

Program Interrupts

1-7

1.5

Engineering Drawing References

1-7

1.6

Signal Mnemonics

1-7

CHAPTER'2

INSTALLATION

2. 1

Insta Ilati on

2-1

2.2

Power Requirements

2-1

2.3

Interface

2-3

2.4

LT19E Baud Rate Selection

2-4

2.5

Channel Assignments

2-5

2.6

Insta \lati on Checkout

2-7

2.6.1

LT19D Tests

2-7

2.6.2

LT 19F Tests

2-7

2.6.3

LT19H Test

2-7

2.6.4

LT19H System Verification

2-8

CHAPTER 3

PRINCIPLES OF OPERATION

3. 1

Block Diagram Description

3-1

3.1.1

Transmit Operation

3-3

3.1.2

Receive Operation

3-4

3.2

Detailed Transmit Operation

3-5

3.3

Detailed Receive Operation

3-6

CHAPTER 4

MAINTENANCE

4.1

General Maintenance

4-1

4.2

LT 19E Clock Ad i ustments

4-1

4.3

Engineering Drawings

4-2

iii

ILLUSTRA no NS
Figure No.

Title

Page

1-1

LT19 System, Typical Configuration

1-2

lOT Instructi on Format

1-5

2-1

Interface Connecti ons

2-2

LT 19-Devi ce Interface Connecti ons

2-3

3-1

LT19 Detailed Block Diagram

3-2

Transmit Operation Timing Diagram

3-5

3-3

Read Operation Timing Diagram

3-7

TABLES
Table No.

Title

Page

1-1

Differences Between Models

l-l

1-2

Related Documentati on

1-3

Specifi cati on Summary

1-3

1-4

Device Select Codes

1-5

LT19 lOT Instruction

1-6

2-1

Baud Rate Selection

2-4

2-2

Channel Assignments for One LT19

2-5

2-3

Channel Assignments for Two l T19s

2-6

2-4

Channel Assignments for Three lT19s

2-6

2-5

Channel Assignment for Fourth lT19

2-7

4-1

Recommended Spare Modules

4-1

4-2

lT19 Multi-Station Teletype Control Drawing
Index list

4-2

CHAPTER 1
GENERAL DESCRIPTION

1.1

INTRODUCTION

This manual describes the LT19 Multi-Station Teletype Control used with both the PDP-9 and PDP-15
Programmed Data Processors manufactured by Digital Equipment Corporation, Maynard, Massachusetts.
The LT19 Multi-Station Teletype Control increases the basic teletypewriter facility by permitting data
transfers between the processor and any combination of up to five teletypewriters or level-operated
data terminal devices that are EIA-compatible*.
The LT19 consists of three logic subgroups: I/O bus interface logic; optional Teletype ® control logic;
and optional EIA-Ievel converter logic (refer to Table 1-1). Initially, this manual covered only the
A, B, and C versions of these logic subgroups. Because the D, E, and F versions are used with the
PDP-15, portions of this manual are updated to cover these models, where they differ.

Table 1-1
Differences Between Models
Logic Subgroup

PDP-9

PDP-15

Differences

Interface Logic

LT19A

LT19D

LT19D includes wiring changes
to permit separate transmit
clocks for each channel.

Teletype Control Units

LT19B

LT19E

LT19E has an additional R401
Variable Clock module for the
separate transmit clock.

EIA-Ievel converters

LTl9C

LT19F

Identical

*Logic levels specified in Electronic Industries Association (EIA) Standard RS-232C "Interconnection of
Data Terminal Equipment with a Communication Channel".
® Teletype is a registered trademark of Teletype Corporation.

1-1

Unless otherwise indicated, references in text or illustrations to LT19A, B, or C type numbers are
interchangeable with their corresponding LT 19D, E, or E type numbers. Similarly, references to
PDP-9 I/O operations are valid for the PDP-15, as well.

1.2

FUNCTIONAL DESCRIPTION

Figure 1-1 shows a typical LT19 configuration utilizing three Teletypes and two EIA devices. Under
program control, the PDP-9 sends control signals, device select signals, and parallel data words to the
LT19A through the I/O bus. The LT19A serves as an interface and control between the PDP-9 I/O bus
and a specific LT19B or LT19C unit.

,---------------------,
I

L T 19

SYSTE M

CONTROL
SIGNALS

PARALLEL
DATA
PDP-9

DEVICE
SELECT
SIGNALS

SERIAL
DATA

EIA

SERIAL
DATA

S~:i~

SERIAL
DATA

I
I
I
I
I
I

L ____ _

--~

TTY

TTY
2

TTY

EIA

DEVICE
I

DEVICE
2

* ANY COMBINATION OF UP TO FIVE L Tl9B AND LT19C
CONTROL

Figure 1-1

UNITS

MAY BE USED

WITH

THE LT19A

LT19 System, Typical Configuration

Each LT19B includes the logic that comprises one Teletype control unit for operation with ASR, KSR,
RO, or SO Teletype devices. Under control of the LT19A, the LT19B converts parallel data words
from the PDP-9 to serial information which can be applied to the Teletype device. In a similar manner, the LT19B receives serial information from a Teletype and converts it to parallel data which can
be transmitted to the PDP-9.
The LTl9C adds EIA-Ievel converter logic, which permits data transfers between the PDP-9 computer
and a device using EIA levels.
Since the PDP-9 can service a device in approximately 4 flS (one lOT instruction time), all of the
slower operating devices (TTY and EIA) can operate simultaneously and indicate a servicing requirement to the PDP-9 via the Program Interrupt Enable (PIE) faci Iity. To allow this type of operation,
each device is assigned its own specific device code which enables the PDP-9 to address the device
when servi cing is requi red.

1-2

This manual contains operation and maintenance informati on for the LT 19 Multi -Stati on Teletype Control. Maintenance and operation descriptions for the PDP-9 are contained in the documents listed in
Table 1-2.

Table 1-2
Related Documentation
Title

Description

Document Number

PDP-9 User Handbook
or
PDP-15 User's Handbook

F-95

PDP-9 Maintenance Manual,
Volumes I and II
or
PDP-15 Maintenance Manual

F-97

Digital Logic Handbook

C-I05

Specifications and descriptions of
most FLIP CHIP modules, plus simplified explanations for selecting
and using these modules in numerous applications.

KF09A Automatic Priority
Interrupt Instruction Manual

DEC-09-15AA-D

Operation and maintenance information for the PDP-9 Automatic
Priority Interrupt option.

Technical manual for Model 32
and 33 ASR, KSR, and RO/SO
Tel etype sets.

Teletype Bulletin 273B
Volumes I and II

Volume I contains installation,
disassembly, reassembly, lubricati on and operati on documentati on.
Volume II includes adjustment informat i on on a II component un i ts
of these Teletypes.

Parts list for Model 32, and 33
ASR, KSR, and RO Teletype
sets

Teletype Bulletin 1184B

Provides complete parts documentation for these Teletypes.

LT19 Diagnostic PDP-9
PDP-15

MAINDEC-09-D8CC
MAINDEC-15-D8CA

Fault isolating maintenance program.

LT 19 Diagnosti c

MAINDEC-09-D8CC-D
MAINDEC-15-D8CA-D

Program description.

DEC-15-H2DC-D

Contains lOT instruction format
and program controlled transfer
considerati ons •
Provides maintenance techniques
and lOT device selection information.

DEC-15-H2BB-D

Table 1-3
Specification Summary
Specification

C haracteri sti c
Character code

5- or 8-bit* character code

Start code

1 unit start code*

*Standard Unit

1-3

Table 1-3 (Cont)
Specification Summary
C haracteri sti c

Spec i fi cati on

Stop codes

1-, 1 .5-, or 2-units* stop code

Operation

Full duplex

Service

Up to five units per LT19A or LT19D

Speed
LT19B

10,000 baud, maximum. All units operate at the
same speed.

LT19E

Variable to 30,000 baud. See Note.

Transmission distance

2000 ft, maximum. 20 mA Current Loop only 110 baud. Maximum length of LT19H is 250 feet.

Operating temperature range

55-122'1= (15-50°C)

Operating humidity range

10-95%

Primary power requirements

115V, 60 Hz, 250W (approx.)

*Standard Unit

NOTE
The overall speed for all LT19E channels is limited to
30,000 baud, for all N channels combined, where N = 1
to 16. This limitation is imposed so that the normal processor service routines may handle all N channels simultaneously.
Assign the highest speed channels to the first channels in
the system to keep the skip chain short. In a multiple
LT 19D System, all high-speed channels must be first to
prevent a low-speed channel from locking out a highspeed unit.

1.3

LT19H DATA COMMUNICATIONS CABLE OPTION

The LT19H is a data communications cable option used for interprocessor buffer applications. It is used
between an LT19 and PT08, between two LT19s, or between the LT19 and other devices with equivalent
interface and timing characteristics. The cable is available in five lengths:
Option

Length
(ft. )

LT19HA
LT19HB
LT19HC
LT19HD
LT19HE

50
100
150
200
250

1-4

1.4

PROGRAMMING

Communication between the POP-9 or POP-15 and the LT19 units is accomplished by lOT instructions.
The keyboard and teleprinter circuits of a Teletype are considered independent devices. Therefore
each circuit is assigned a different device code to control its operation. The first Teletype has a device code of 400X assigned to its teleprinter circuit and a device code of 410X assigned to its keyboard
(or paper-tape reader) circuit.
The LT19 employs the lOT instruction format discussed in the POP-9 and POP-15 User Handbook. The
format example in Figure 1-2 shows the bit assignments.

OSO-OS5

OPERATION CODE

o 1 1 1 2

CLEAR
AC

lOP 2

,-A---"

10
1

'--y---J
SOO-SOI

UNUSED

Figure 1-2

lOP 1

IOP4

lOT Instructi on Format

The main components of the lOT instruction are as follows; four operation code bits, six device selection bits (050 through 055), two subdevice selection bits (500 and 501), and three lOP bits (lOP1, 2,
and 4). In all lOT instructions the operation code is 70 • The device selection bits identify the deS
vice selected and the type of operation to be performed. The subdevice selection bits identify the selected circuit within the LT19 and the lOP pulses initiate the required function within the selected
circuit. A 1 in bit 14 clears the processor accumulator prior to an input data transfer. Bits 4 and 5 are
not used.

1 .4. 1 LT 19B - (1 through 5) Device Selection Codes
The lOT format for the first five LT19B units is shown in Table 1-4. The specific device select coding
for each control unit is underlined. Channel assignments for systems with more than one LT19 unit are
described in Paragraph 2.5 of Chapter 2, Installation.

Table 1-4
Device Select Codes

Unit

Transmitter Code
(T e Iepri nter)

Receiver Code
(Keyboard)

LT19B-1

70400X

70410Y

LT19B-2

70402X

70412Y

(continued on next page)

1-5

Table 1-4 (Cont)
Device Select Codes

Unit

Transmitter Code
(T e Iepri nter)

Receiver Code
(Keyboard)

LT19B-3

70404X

70414Y

LT19B-4

70406X

70416Y

LT19B-5

7042ZX

7043ZY

The letter X in the transmitter codes represents either lOP 1, IOP2 or IOP4. The letter Y in the receiver codes represents either IOP1 or IOP2. The subdevice code for LT19B-5 (the fifth unit in each
LT19 system) is represented by the letter Z in Table 1-4 because subdevice codes have not been assigned
to this unit. The subdevi ce code assigned to this I ine is dependent upon the number of Teletypes (or
EIA devices) that are connected to the processor via the LT 19 interface(s). These subdevice codes
therefore, are hand wired after the user's requirements have been determined.
Device selection and the functions performed within the LT19B units are accomplished by W103 Device
Selector modules which decode the device selection signals, subdevice signals and lOP pulses. The
appropriate diodes are removed from the inputs of the W103 modules to obtain the proper selection codes.

1.4.2

LT19 lOT Instruction Set

Table 1-5 shows the complete set of lOT instructions for the LT19 teleprinter and keyboard circuits and
identifies the function(s) of each instruction. Identical functions are performed by the LT19-1 through
LT19B-5 lOT instructions. Programming examples are provided in the PDP-15 User's Handbook, Volume 2, Chapter 4.

Table 1-5
LT19 lOT Instructions
Teleprinter Instructions
lOT

Function

704001

Skip if transmitter flag is set

704002

Clears transmitter flag

704004

Loads transmitter module and sends character to teleprinter
(continued on next page)

1-6

Table 1-5 (Cont)
LT19 lOT Instructions
Keyboard Instructi ons
Function

lOT

1 .4.3

704101

Skip if receiver flag is set

704102

Reads contents of receiver module and clears receiver flag.

Program Interrupts

The LT19A or LT19D supplies API and program interrupt {PI} facilities for each of the Teletype controls.
All transmit flags are ORed together to cause interrupts on either PI or API. When API is implemented
in the processor, a transmit interrupt causes a trap to location 748 on priority level 3. A receive interrupt causes a trap to location 75 on priority level 3.
8

1.5

ENGINEERING DRAWING REFERENCES

Engineering drawings provided in Volume 2 of this manual are referenced by the letter-number combination appearing at the end of the complete drawing designation. For example, drawing D-8S-LT19-A-1
is referred to as drawing A-1. Similarly, drawing D-8S-LT 198-1 (sheet 1 of 5) is referred to as drawing 8-1-1 while drawing D-8S-L T 198-1 (sheet 4 of 5) is referenced as drawing 8-1-4. In the LT198
and LTl9C units, sheet numbers correspond to channel numbers.

1.6

SIGNAL MNEMONICS

Uncommon signal mnemonics are explained parenthetically the first time they are mentioned in the
discussion, e.g., TSO (Teletype Serial Output).

1-7

CHAPTER 2
INSTALLATION

2. 1

INST ALLA no N

The LT19 system is contained within two module mounting panels of a standard PDP-9, 19-in. optional
cabinet. Complete installation consists of inserting the LT19A interfacing modules and additional
LT19B/LT19C control modules into prewired locations on the mounting panels. The LT19 operates via
program control, therefore, location on the I/O bus is not critical.
The exact number of LT19B and LTl9C subsystems contained within the LT19 depends upon each user's
requirements. One LT19B subsystem is required for each Teletype and an LT19B with an LT19C is required for each EIA-Ievel operated device. Any combination of up to five of these subsystems may be
incorporated into an LT19 system. Because device codes assigned to the LT19 will handle up to 16 devices, additional LT19 systems can be connected to the PDP-9.

2.2

POWER REQUIREMENTS

The LT19 receives dc operating power from one DEC Type 728 Power Supply. This supply is mounted on
the back door of the optional bay in which the LT19 is installed. When the PDP-9 is turned on, primary ac power from a Type 841A Power Control, mounted in the optional bay, energizes the 728 Power
Supply. In a simi lar manner, ac power is removed from the 728 when the PDP-9 is turned off. The
LTl9 does not require any special power controls or fan assembl ies other than those uti Iized in the
PDP-9 multibay system. The maximum load for the + 10V supply is 7 .2A and 2 .8A for the -15V supply.
The following chart indicates typical current drain for each supply for various LT19E configurations:

Number of
LT 19Es

+ 10V Supply
{amperes}

-15V Supply
{amperes}

1
2
3
4
5

1.47
2.88
4.30
5.72
7.14

1.58
1.86
2.14
2.42
2.70

2-1

L T 19

POP ~ 9

OUT

10 SIGNAL

10 BUS 10
10 BuS II
10 BUS

10 BUS

10 BUS 14
10 BUS 15
10 BuS 16
10 BUS 17
01

B25

05
OUT

PDP - 9

10 SYNC
lOP

lOP 2
lOP 4
SKIP RQ
PROG

INT RQ

RO RQ
10 PWR CLR
C6

A26

OuT

PDP - 9

OSO
DS1
OS 2
OS3
OS4
OS5
SOO
SO,
B26

[]=",

3 GR (' J

API

3 EN OUT

API

3 RQ

62B

10 AOOR

I I

API 3 EN OUT

10 AOOR '3
10 AOOR , .
10 AOOR '5
10 AOOR '6
10 AOOR ,7
B27

P+APIENIN
632

Figure 2-1

3-~-+---o
Interface Connecti ons

2-2

2.3

INTERFACE

All connections between the LT19 and the PDP-9/15 Processor are made through the I/O bus, using
standard I/O bus cables. Each teletypewriter (TTY) or EIA-Ievel device is connected to the LT19 by a
single control cable supplied with the device. The TTY cable is terminated with DEC W078A cable
connector modules that plug into assigned locations in the logic mounting panels. EIA-Ievel devices
are connected with a data set cable, DEC part no. 70-05717.
Each LT19 receives all I/O bus signals and sends them to the next device on the I/O bus. Figure 2-1
shows only those interface connections between the processor that are pertinent to LT19 operation. The
interface between the LT19 and its devices is shown in Figure 2-2. For additional interface information, refer to the PDP-9 User Handbook or the PDP-15 Interface Manual.

LTI9B-1

TSO - }

PSM

-------+

RRE

----<>

DEVICE I

DI3
LTI9B-2

TSO - }

PSM

-------+

RRE

----<>

DEV I CE 2

021
LTI9B-3

TSO-}

PSM

RRE

----<>

DEVICE 3

A02

PSM

-j

RRE

----<>

LTI9B-4

TSO

DEVICE 4

BIO
LTI9B-5

TSO_}

PSM

RRE

----<>

DEVICE 5

BI8
TSO - TELETYPE
PSM- PRINT

SERIAL

RRE - READER RUN

Figure 2-2

OUTPUT

SELECTOR MAGNET
ENABLE

LT19-Device Interface Connections

2-3

2.4

LT19E BAUD RATE SELECTION

Each R401 Clock module provides a selectable clock frequency that is twice the baud rate for the associated channel. The doubled output frequency is required by the W706/W707, which divides the
clock frequency by two.
To select a specific baud rate, locate the appropriate range in Table 2-1. Connect a jumper from
pin R on the R401 to the indicated pin (L, M, N, or P). Then connect the indicated resistor (Rx) between pins Rand T. Fine tune the R401 Clock output by adjusting the internal potentiometer (R11) on
the R401 •
NOTE
The Rx values listed in Table 2-1 are design center
values, with 10 percent capacitor and resistor tolerances. Other values of Rx may be used if necessary.
Use the lowest value of Rx that allows adjustment to
the required frequency.
Some examples of common baud rates are:
110 baud:

Jumper pin R to L, Rx = 1.2K

2000 baud:

Jumper pin R to M, Rx = 750

2400 baud:

Jumper pin R to M, Rx = 470

11,000 baud:

Jumper pin R to N, Rx = 3.3K

30,000 baud:

Jumper pin R to P, Rx is open circuit.

Table 2-1
Baud Rate Selection
Baud Rate Range

Connect Rx Between Rand T

Jumper Pi n R to -

59 - 106
106 - 122
116 - 146
133 - 142
137 - 146
146 - 155
155 - 161

3.3K
lo2K
loOK
750
680
560
470

L
L
L
L
L
L
L
(continued on next page)

2-4

Table 2-1 (Cont)
Baud Rate Selection
Baud Rate Range

Connect Rx Between Rand T

Jumper Pin R to -

159 - 860
860 - 1297
1560 - 1795
1710 - 1910
1910 - 2084
2010 - 2150
2150 - 2265
2270 - 2400

open
3.3K
lo2K
loOK
750
680
560
470

M
M
M
M
M
M
M
M

1590 - 8600
8600 - 12,970
15,600 - 17,950
17,100 - 19,100
19 , 100 - 20,840
20,100 - 21,500
21,500 - 22,600
22,700 - 24,000

open
3.3K
lo2K
loOK
750
680
560
470

N
N
N
N
N
N
N
N

18,600 - 98,000*

open

*Maximum baud rate is 30,000

2.5

CHANNEL ASSIGNMENTS

Table 2-2 lists the channel assignments for one LT19 that includes from one to five channels.
NOTE
When the system includes an LT 15, it becomes
logical unit number 1.

Table 2-2
Channel Assignments for One LT19
Unit No.

Transmitter Code

Receiver Code

Logical Unit No.

1
2
3
4
5

xx400x
xx402x
xx404x
xx406x
xx420x

xx410x
xx412x
xx414x
xx416x
xx430x

1
2
3
4
5

Table 2-3 I ists the channel assignments for a system with two LT 19s, containing up to 10 channels.

2-5

Table 2-3
Channel Assignments for Two LT19s
Unit No.

Transmitter Code

Receiver Code

Logical Unit No.

xx400x
xx402x
xx404x
xx406x
xx440x

xx41 Ox
xx414x
xx414x
xx416x
xx450x

1
2
3
4
11

xx420x
xx422x
xx424x
xx426x
XX442x

xx430x
xx432x
xx434x
xx436x
xx452x

5
6
7
10
12

LT19 #1
1
2
3
4
5
LT19 #2
1
2
3
4
5

Table 2-4 lists the channel assignments for a system with three LT19s, containing up to 15 channels.

Table 2-4
Channel Assignments for Three LT19s
Unit No.

Transmitter Code

Receiver Code

Logical Unit No.

xx400x
xx402x
xx404x
xx406x
xx460x

xx410x
xx412x
xx414x
xx416x
xx470x

1
2
3
4
15

xx420x
xx422x
xx424x
xx426x
xx462x

xx430x
xx432x
xx434x
xx436x
xx472x

5
6
7
10
16

xx440x
xx442x
xx444x
xx446x
xx464x

xx450x
xx452x
xx454x
xx456x
xx474x

11
12
13
14
17

LT19#1
1
2
3
4
5
LT19 #2
1
2
3
4
5
LT19 #3
1
2
3
4
5

2-6

For a system containing four LT19s, the channel assignments for the first three LT19 units would be the
same as listed in Table 2-4. Table 2-5 lists the channel assignment for the single channel serviced by
the fourth LT19.

Table 2-5
Channel Assignment for Fourth LT19
Unit No.

Transmitter Code

Receiver Code

1
2

Not Used
Not Used
Not Used
Not Used
xx466x

Not Used
Not Used
Not Used
Not Used
xx476x

3
4
5

2.6
2.6.1

Logical Unit No.

INSTALLATION CHECKOUT
LT190 Tests

Test each LT19 unit using program tape MAINOEC-09-0SCC-PH or -15-0SCA-PH and test procedure
MAINOEC-09-0SCC-0 or -15-0SCA-0 under normal +10V and -15V margins.

2 .6 • 2

LT 19F Tests

The LT19F EIA-Ievel converters are intended to drive a Dataset cable or an LT19H option. To simulate
the cable and perform test procedures, add the following temporary jumpers to slot A25, A26, A27,
A2S or A29:
Jumper pin 5 to H
Jumper pin T to V
Jumper pin E to P (output-to-input jumper)
Then run the appropriate sections of diagnostic -09-0SCC or -15-0SCA. Remove temporary jumpers on
completion of test procedure.

2 .6 .3

LTl9 H Test

The LTl9H test procedure consists of two parts. Part 1 is to run the LT 19F tests described in Paragraph
2.6.2, with the LT19H option installed. Perform part 2 as follows:
Procedure
Insert one end of the LT19H cable into the appropriate output slot for
the channel under test.
(continued on next page)
2-7

Procedure

Step

2.6.4

Insert the opposite end into the unused slot A32.

Remove the jumper between pins E and P and install between pins A32E
and P.

Repeat test described in Paragraph 2.6.2.

LT19H System Verification

Verify the LT19H system in the field as follows:
Procedure

Step

Perform the checkout procedure described in Paragraph 2.6.2.

Check the opposite terminal on the data communications link. This
may be another LT19 or a PT08-F. Use MAINDEC-08-D8PA if it is
the latter.

Verify that the baud rates are identical. Then connect the LT19H
cable into both terminals of the data communications link.

Load the most recent version of the LT19 diagnostic program into the
PDP-9/15.

Instead of adding the output-to-input jumper, use a "turnaround II
program in each processor.
a.

A sample PDP-8 turnaround program is as follows:
LaC

Content

Comment

20
21
22
23
24
25
26
27

6401
5020
6406
3040
1040
7000
6416
5020

Skip on R flag
JMP .-1
Read lOT
DCA 40
TAD 40
Nap
XMIT
JMP 20

A sample PDP-9/15 turnaround program is as follows:
LaC

Content

Comment

200
201
202
203
204
205

704101
600200
704112
740000
704006
600200

Skip on R flag
JMP .-1
Read
Nap
XMIT
JMP 200
(continued on next page)

2-8

Procedure
NOTE
Both sample turnaround programs assume channell.
Revise lOT codes as required for each specific channel.
6

Check the channel as described in Paragraph 2.6.2.

2-9

CHAPTER 3
PRINCIPLES OF OPERATION

The LT19 system performs two types of programmed-controlled operations during which data is transferred between a processor and a Teletype or EIA device {for example, dataphone interface}. A transmit
operation is performed to transfer data from a processor to a teleprinter (or EIA device) and a receive
operation is performed to transfer data from a Teletype keyboard (paper tape reader or EIA device) to a
processor.

3. 1

BLOCK DIAGRAM DESCRIPTIO N

Figure 3-1, a detailed block diagram of the LT19 system, shows the LT19A and LT19B-1 control unit
{one of the LT19B units}. the other four LT 19B units (L T19B-2 through LT 19B-5) are connected to the
LT19A in a similar fashion and operate in a similar manner. The LT19B-l receives data from the Teletype keyboard via the TSO (Teletype Serial Output) line and sends data to the teleprinter via the PSM
(Print Selector Magnet) line. A signal sent to the Teletype over the RRE (Reader Run Enable) line advances the paper tape reader if the Teletype is equipped with a relay controlled paper tape reader. To
communicate with an EIA-Ievel operated device instead of a Teletype, EIA-Ievel converters which
change DEC standard logic levels to EIA levels are added to the control unit. The control unit is then
designated LT19C.
The transmit and receive lOT decoders are used to decode the signals on the device select, subdevice,
and lOP lines and to generate the required control signals. The control signals are sent to the transmitter and receiver modules and the lOT control register. The control register consists of three fl ipflops which are set to perform LT19 control functions. The flip-flops within the register are cleared by
either the CLR lOT 1 CONTROL or CLR lOT 2 CONTROL signal. These signals are initiated by an
lOP 1 or IOP2 pulse, respectively. They are also generated during initial processor turn-on by the 10
PWR CLR signal or whenever the 10 SYNC signal is generated. Output signals from the lOT control
register generate a SKIP RQ, RD RQ, or initiate a receive operati on.
LT19 system operation can be controlled via the Program Interrupt Enable (PIE) facility or the Automatic
Priority Interrupt (API) facility. In the description of the transmit or receive operations, both types of
operation are discussed.
3-1

LTI9A
lOT 431)1 (0
lOT 42ctl (1)
lOT 4t61(1)
lOT 486t (I)

FROM
LT 19B-2
THROUGH
LT 198-5

IOT4t41(1)
lOT 4041(1)

SKIP
REOUEST
GATE

LTI9B-1
lOT 4121(11
JOT 402.1)
lOT 4!>0t(t)

SKP RO

lOT 4t0t (t)

lOT 4te2 (1)
RD

READ

JOT 4t22(1) }
lOT 4142(t)
lOT 4162 (1)
lOT 431)2(0

1 0 - - - - - - - - - - - I REOUEST
GATE

FROM
LT19B-2
THROUGH
LT t 9B-5

r- RRE

RECVR FLG I

lOP 2
RECEIVER
MODULE
(W7061
PDP- 9
10
CONTROL
LOGIC

KEYBOARD
OR
PAPER
TAPE
READER

TSO

10 PWR CLR
INVERTER
10 PWR

10 SYNC

INVERTER

I-----<l~.

TELETYPE

CLRI

10 SYNC
10 BUS

to-17

W
I

TELEPRINTER

to.)
PSM
IOPt ,2,4

IOPt,2
D50(BI - D55(B)
TRANSMtT

D51J - 055

L.:.:..:l!~=.Jr,-=-°S:..:0--0-S_54 DE~~ER
(Wte3)

DS0 - OS5
500(BI - SOt (BI

RECEIVE
lOT
DECODER
(Wt03)

RANSMTR

XMTR
FLG I

~+--------DI MODULE

(W707)

500 _ SOt
PROG INT RO

500-S0t

lOT 4002 , lOT 4004

SEE
NOTE
~-"-'-'''''''---'

PROG

INT RQ

XMTR FLG t

API 3 RQ
TRANSMTR
FLAG
GATE

XMTR FLG 2} FROM
XMTR FLG 3 ~~~~~
XMTR FLG 4 LT 19B-5
XMTR FLG 5
RECVR FLG t

10 AODR t2 -t7

I<>'='::'~-=+

_ _ _ _ _ _~ RECEIVER
FLAG
GATE

API 3 EN IN
API 3 GR (t)

RECVR FLG 2} FROM
RECVR FLG 3 LTI9B-2
THROUGH
RECVR FLG 4 LTt 9B-5
RECVR FLG 5

RECVR API 03 RQ (81
NOTE
IN LTI90, THE XMTRCLK IS
LOCATED IN EACH LTI9E CHANNEL

IL-API
CONTROL
__
_ _ _ _ _ _ _ _ ...l

Figure 3-1 LT19 Detailed Block Diagram

3.1.1

Transmit Operation

The transmit operation is performed to print a single character on the teleprinter. An lOT 704004 instruction is used to initiate a character print on the teleprinter connected to LT19B-1. Prior to executing the instruction, the 8-bit code of the character is placed in bits 10 through 17 of the accumulator
(AC) (bits 13 through 17 for 5-bit character codes). During the execution of the instruction, the contents of the AC are present on the I/O bus. The signals on the 10 BUS 10 through 17 lines are applied
to emitter followers and the resultant signals are sent to the transmitter module (y/707).
The device code for the lOT 704004 instruction is decoded by the transmit lOT decoder (y/103 module)
and the IOP4 pulse produces the lOT 4004 pulse. The lOT 4004 pulse strobes the signals on the lOB
10 (B) through 17 (B) I ines into the transmitter module shift register and the module shifts the character
to the teleprinter in a serial fashion via the PSM line. The rate of transfer is determined by the TCLO
clock pulse from the LT19A.
After the transfer is complete, a stop signal is placed on the PSM line, the transmitter flag is set generating the XMTR FLG 1 signal. The XMTR FLG 1 signal is sent to the transmitter flag gate generating
the XMTR FLG signal. The XMTR FLG signal conditions the transmitter API module, generating the
API 3 RQ that is sent to the processor (if a receiver flag is also raised, the receiver has a higher priority
and the XMTR EN IN signal disables the transmitter API module).
The processor detects the request and sends the API 3 GR (1) signal to the transmitter API module in the
LT19 order of priority. The API 3 GR (1) signa I enables the transmitter API module sending a preset
address to the processor via the 10 ADDR 12 through 17 lines and the program executes the preset location. In this case, the program executes location 74 • The processor performs a series of lOT instruc8
tions which checks for a raised transmitter flag because the API has identified a transmitter interrupt.
When the lOT 704001 instruction is executed, the lOT 4001 signal is ANDed with the XMTR FLG 1
signal generating the lOT 4001 (1) signal. The skip request gate is enabled and the SKP RQ is generated
indicating that the next character can be sent.

If API is not used in a particular system, the PIE facility of the processor must be turned on to generate
a program interrupt. In this case, the XMTR FLG signal is inverted generating the XMTR API 03 RQ
(B) signal that is sent to the transmitter module. The PROG INT RQ is generated and sent to the processor. After detecting the PROG INT RQ, the PDP-9 enters a routine to check all its I/O devices for
a raised flag. When the processor executes an lOT 704001 instruction, the skip request gate is enabled
and the SKP RQ is generated and sent to the processor.
The SKP RQ causes program control to be transferred to a service routine and the next character is sent
and an lOT 704004 is performed. If the processor does not have additional data for the transmitter
module, it can clear the transmitter flag and remove the XMTR FLG 1 signal by performing an lOT
704002 instructi on.

3-3

The XMTR FLG 1 signal removes the XMTR FLG signal when the lOT 704002 instruction is performed if
the XMTR FLG 2 through XMTR FLG 5 signals from the other LT19B (or LTl9C) units are not present.
If one or more of these signals is present, the API 3 RQ is generated and/or PROG INT RQ remains in
the true condition. The processor must enter the appropriate checking routine to locate the raised flag
and perform the necessary service routine.

3.1.2

Receive Operation

The receiver operation is performed when the shift register in the receiver module is loaded via the
TSO line. It can be initiated in one of the following ways: a Teletype key is pressed, a paper tape
reader is enabled sending out a character, or an EIA device is enabled.
When a receive operation is initiated, a start bit appears on the TSO line, it is followed by the serial
word bits and triggers the Wl06 receiver module.
The presence of data on the TSO line causes the RCLE signal to enable the receiver 1 clock. The RCLO
signals are generated and sent to the receiver module loading the serial data into the shift register of
the module. After the last data bit is loaded, the receiver flag is set and the RECVR FLG 1 signal is
generated. The RECVR FLG 1 signal is used to generate the API 3 RQ, if API is used, and the PROG
INT RQ. These signals perform functions that are similar to the functions explained in the transmit operation with the following differences: the receiver API module causes a program execute of location
75 when it receives the API 3 GR{l) signal from the PDP-9; the PDP-9 enters a subroutine which
8
checks for the raised receiver flag; if the PIE facility is in use instead of API, the PDP-9 must check
all of its I/O devices for a raised flag.
When the lOT 704101 instruction is performed, a SKP RQ is generated by ANDing the RECVR FLG 1
and lOT 4101 signals which generate the lOT 4101 (1) signal. The PDP-9 detects the SKP RQ and
transfers program control to a service routine.
To fetch the data from the receiver module, the PDP-9 performs an lOT 704102 instruction and the receiver lOT decoder generates the lOT 4102 pulse. The lOT 4102 pulse is sent to the lOT control register generating the lOT 4102 (1) signal. The lOT 4102 (1) signal enables the read request gate generating the RD RQ that enables the PDP-9 AC to accept data, transfers the data to the PDP-9 in parallel
form via the 10 BUS 10 through 17 lines, and removes the RECVR FLG 1 signal by clearing the receiver
module flag. The API 3 RQ and/or PROG INT RQ are also removed if all RECVR FLG and XMTR FLG
signals from the other LT19B (LTl9C) unit are cleared.

3-4

3.2

DETAILED TRANSMIT OPERATION

Figure 3-2 shows the timing sequence of a transmit operation within the lT19B-1. Engineering drawings
A-1, A-2 and B-1 are used as a reference during the following discussion.

lOT
OV
INITIATE TRANSFER
INITIATE NEXT TRANSFER
4004 -3V ---.J11-4;..:::0.::...0.:.:..:NS~e.:..:cs_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

--t

T C LO

--,!!.._ __

I+- 45 Msec/."400 NSecs

_~: -L.......II~IL......L.-I..L.-I. .1. -1. . 1-.1. . . LI---LI-..J.I---.JI~I. 1. -1. .L. .I-L-I-LI. . . LI---LI-..J.I---.JI---L-I. 1. -1. .L. .I-L-I-LI--LI---LI---.JI_I~I.l..-I. .L. .I

PSM

STOP t STOP 2
-3V

XMTR
Ov
FLAG 1 -3V _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-.J
JOT
OV-------------------------------~~<
4001 (I) -3V
j.l-Sec

-U-'

SKIP RQ

Ov
-3V

lOT
OV
4002 -3v

~
1
Sec

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - j 5rr- - - - - - - - - ----------------------------------fI--'lS

--:

Figure 3-2

~
- - 400 NSecs
IL..-----

:- ~L~ ~UET~~~R CLR

Transmit Operation Timing Diagram

During initial processor turn-on, the 10 PWR ClR pulse generates the ClR lOT 1 CONTROL and ClR
lOT 2 CONTROL pulses (drawing A-1) clearing the lOT control register flip-flops (B-1). The 10 PWR
ClR pulse also clears the transmitter module (W707 - CD 15) and the transmitter API module (W104 CD32).
The PDP-9 gates the character to be transferred into its AC register and onto the 10 BUS 10 through 17
lines. The signa Is are buffered by inverters and applied to the parallel data inputs of the transmitter
module. To initiate the transfer, the PDP-9 executes an lOT 704004 instruction that is decoded by the
transmitter lOT decoder (W103 - CD16) generating the lOT 4004 pulse. The lOT 4004 pulse is applied
to the transmitter module gating the data into the shift register of the transmitter module. At this time,
the transmitter module is enabled to transfer the character in a serial fashion to the teleprinter via the
PSM line. Shifting commences with the first TClO pulse following the lOT 4004 pulse. The TelO
pulse is a 400 ns pulse generated by the XMTR clock (R401 - D09) every 4.5 ms. The frequency of the
TClO pulse is twice the baud rate which allows for sampl ing each bit during the middle of the bit time.
The first bit on the PSM line is a START bit which synchronizes operation between the Teletype and the
lT19. Bit 1, which corresponds to the original information on the 10 BUS 17 (B) line, is sent to the
teleprinter via the PSM Iine and bits 2 through 8 are shifted out in a simi lar manner. Jumper connections on the W707 transmitter module allow selection of either an 8-bit or 5-bit code and either a 1.0,
1.5 or 2.0 unit stop code.

3-5

As data is shifted out of the register, binary Os are shifted into the other end of the register. When
the register contains aliOs (after bit 8 is sampled), transfer of the character is complete and the transmitter module generates a STOP bit(s) that is sent to the teleprinter via the PSM line.
One-half unit after the STOP bit is placed on the PSM line, the XMTR FLG 1 signal is generated and
either the API or PIE facility is enabled. The operation of the PIE facility is described first.
The XMTR FLG 1 signal is sent to a NOR gate (drawing A-1) generating the XMTR FLG signal that is
inverted generating the XMTR API 03 RQ (B) signal. The XMTR API 03 RQ (B) signal is applied to the
CV terminal of the 'W707 module and causes the PROG INT RQ line to go to OV. After receiving the
PROG INT RQ, the PDP-9 enters a subroutine to check all its I/O devices for the raised flag. When
an lOT 704001 instruction is performed, the transmitter lOT decoder generates the lOT 4001 pulse that
is applied to the DCD gate at the set side of the lOT 4001 fl ip-flop (drawing B-1). Since the XMTR
FLG 1 signal has conditioned the DCD gate, the lOT 4001 flip-flop is set. The lOT 4001 (1) output
signal from the flip-flop is applied to a NOR gate generating a SKP RQ (drawing A-l) and causing the
PDP-9 to jump to a service routine. The lOT 4001 flip-flop is cleared by the CLR lOT 1 CONTROL
pulse that is generated by the lOP 1 signal.
For API, the XMTR FLG signal enables the transmitter API module (drawing A-2) sending an API 3 RQ
signal to the PDP-9 (assuming no receiver flag is set). The PDP-9 services the interrupt request by
sending the API 3 GR (1) signal to the transmitter API module in the LT19 order of priority. A 748
address is sent to the PDP-9 via the 10 ADDR 12 through 15 lines. The program executes this location
and enters a routine which checks the LT19 transmitter flags. An lOT 704001 instruction causes a SKP
RQ to be generated and program control is transferred to a service routine.
At this time, the PDP-9 can send the next character by executing an lOT 704004 instruction. If it does
not have additional data for this teleprinter, it clears the XMTR FLG 1 signal by performing an lOT
704002 i nstructi on •
The transmit operation of the other four LT19B (or LTl9C) units takes place in a manner that is similar
to the LT 19B-1. The main difference between the units is in the transmitter lOT decoders which are
coded for their specific codes.

3.3

DETAILED RECEIVE OPERATION

Figure 3-3 shows the timing sequence of the serial input from a paper tape reader. The tape is placed
into the reader and the START lever is pressed. The paper tape is advanced one line, the content of
the line is read and shifted to the receiver module 0N706 - CD18) in a serial fashion via the TSO line
(the TSO line also carries the data from the keyboard or EIA device).

3-6

The first bit on the TSO Iine is a START pulse that causes the RCLE pulse to go to -3V enabling the
ClK module (R401 - D19). The ClK module generates the 400 ns RCLO pulses at a 4.5 ms rate to
synchronize the incoming signa Is on the TSO Iine and load the character bits into the shift register of
the receiver module. After all character bits have been loaded, the receiver module flag is set and
the RECVR FLG 1 signal is generated.

rOT
ov
INITIATE TRANSFER
INITIATE NEXT TRANSFER
4102 (1) -3V ----.J1'-1..;..).l._S_ec_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-'.L...._ _ __

OV------,
TSO

-3V

BIT 8

STOP t STOP 2

RRE_~:~----------------------~------~
I

RCLE

OV---~I----,
- 3V
ov

RCLO

I
I

--I
14- 45 MSecs
/ i 400 NSecs
I
_~....L..--L..I. . J. .I---LI----'I~I. 1. . -1. .J. . .I. . J. .I--LI---LI~I-,--I...l--.1-....J.........J----'I_IL....--L-.....I...--...I--L-_--L-~
I
I
OV~

_ 3V

~~~-3V~I----------------------~I
rOT

OV---------------------~~'---------------

. 4101 (1) -3V

SKIPRQ

t }.I, S.c.

ov
-tJ-lS,c
-3V--------------------~..

L-------------

Figure 3-3

Read Operation Timing Diagram

The function performed by the RECVR FLG 1 signal is dependent upon which interrupt facility is in
use. If the PIE facility is used, a RECVR FLG 1 signal is applied to a NOR gate (drawing A-l) generating the RECVR FLG signal. The RECVR FlG signal is inverted generating the RECVR API 03 RQ (B)
signal (drawing A-2) which enables the receiver module to generate a PROG INT RQ. After detecting
the PROG INT RQ, the PDP-9 enters a subroutine to check all I/O devices. When an lOT 704101
instruction is performed, the receiver lOT decoder (Wl03 - CD17) generates the lOT 4101 pulse that
enables the DCD gate at the set side of the lOT 4101 flip-flop. Since the RECVR FLG 1 signal has
conditi oned the DCD gate, the lOT 4101 flip-flop is set and the lOT 4101 (l) signal is generated.
The lOT 4101 (1) signal from the flip-flop is applied to a NOR gate (drawing A-l) generating a SKP
RQ that causes the program to enter a service routine. Flip-flop lOT 4101 is cleared when the lOP 1
signal goes true generating the CLR lOT 1 CONTROL pulse.
With API, the RECVR FLG signal enables the receiver API module (W104 - CD31) if the API 3 EN IN
line is at -3V (drawing A-2) and sends the API 3 RQ signal to the PDP-9. The PDP-9 returns the API
3 GR (1) signal to the receiver API module in the LT19 order of priority. The API 3 GR (1) signal

enables the receiver API module sending a 75 address to the PDP-9 via the 10 ADDR 12 through 17

lines. The program executes locati on 75 and enters a routine that checks the receiver flags. When
8
the lOT 704101 instruction is performed, the SKP RQ is generated causing the program to enter a service routine.
3-7

After detecting a service requirement, the PDP-9 executes an lOT 704102 instruction and the receiver
lOT decoder generates the lOT 4102 pulse setting the lOT 4102 flip-flop. The lOT 4102 (1) signal performs the following functions: it is sent to the read request gate (drawing A-l) generating the RD RQ
that goes to the PDP-9 and enables its AC to receive the data from the receiver module; it is applied
to the DT terminal of the receiver module gating the data in the shift register onto the 10 BUS 10
through 17 lines (if an 8-bit character is read); it is applied to the CD terminal of the receiver module
clearing the RECVR FLG 1 signal; and it causes the receiver module to generate the RRE pulse that advances the paper tape to the next line. The lOT 4102 flip-flop is cleared by the IOP2 signal generating
the CLR lOT 2 CONTROL pulse. The next receive operation is performed in an identical manner.
The receive operation of the other four LT19B (or LT19C) units is similar except that the receiver lOT
decoders are coded for the specific codes.

3-8

CHAPTER 4
MAINTENANCE

4.1

GENERAL MAINTENANCE

The general maintenance practices described in the PDP-9 Maintenance Manual also apply to the LT 19
System. No special data formats, status bits, programming considerations, operator control or indicators are required for the LT19.
With the assumption that the processor is operating properly, faults within the LT19 system will be
detected by the LT19 diagnostic program. This program determines which Teletype, EIA device, or
control unit is at fault by error ha Its. Because of the simpl i city of the system, most faults can be
localized to a few modules. Defective modules are replaced by spares to restore proper operation
while the defective module is repaired. Table 4-1 lists recommended spare modules.

Table 4-1
Recommended Spare Modules
Unit

4.2

Modules

LT19A/D

S 123 Input Bus Gate
S603 Pulse Amplifier
S 107 Inverter
W107 Bus Driver
W104 I/O Bus Multiplexer

LT19B/E

R401 Variable Clock
S203 Triple Flip-Flop
W005 Clamped Load
W078 Teletype Connector
W103 Device Selector

LTl9C/F

W511 Negative Input Converter
W602 Bipolar Output Converter
(plus modules listed for LT19B/E)

LT19E CLOCK ADJUSTMENTS

The following steps are recommended to set up clocks for each channel:

4-1

Procedure
Setup and adjust the free-running transmit clock first. Baud rate selection
data is presented in Paragraph 2.4.
2

Remove the W706 Receiver module to allow the receive clock to run free.
Set the oscilloscope to ALTERNATE Sweep, INT. Trigger. Do not trigger
on CH1; this will allow the pulses from the receive clock to be matched to
the transmit clock.
NOTE
For 110-baud channels, each data bit is 9.09 ms duration, which requires an R401 Clock to be set for 4.545
ms. Each character has 11 bits of 9.09 ms, so that
character duration is 100 ms. Because it is difficult to
measure a clock interval of 4.545 ms, set up to measure an entire character of 100 ms. The oscilloscope
calibration can be checked by displaying six complete
cycles of 60 Hz in exactly 10 cm. With the oscilloscope calibrated to 100 ms, fine-tune the R401 to provide 23 clock pulses in 10 cm (22 clock pulses plus the
first pulse of the next character).

4.3

ENGINEERING DRAWINGS

A complete set of LT19 Multi -Station Teletype Control engineering drawings is provided in Volume 2 of
this manual. The drawings are under DEC revision control and are updated as required by ECOs {Engineering Change Orders}. The Drawing Index List, Table 4-2, lists the drawings included in Volume 2
in the sequence that they appear.

Table 4-2
LT19 Multi-Station Teletype Control Drawing Index List
Size

Type

Number

Title
LT19D

LT19-D-0

Teletype Control, Unit Assembly

LT19-D-0

Teletype Control, Parts List

LT19-D-l

I/O Bus Interface Logic

LT19-D-2

I/O Bus Interface

LT19-D-3

Module Utilization
LT19E

LT19-E-l

Teletype Control Unit Channel 1

LT19-E-2

Teletype Control Unit Channel 2
{continued on next page}
4-2

Table 4-2 (Cont)
LT19 Multi-Station Teletype Control Drawing Index List
Size

Type

Number

Title
LT19E (Cont)

LTl9-E-3

Teletype Control Unit Channel 3

LT19-E-4

Teletype Control Unit Channel 4

LT19-E-5

Teletype Control Unit Channel 5
LT19F

LT19-F-1

Teletype Control Unit Channel 1

LT19-F-2

Teletype Control Unit Channel 2

LT19-F-3

Teletype Control Unit Channel 3

LT19-F-4

Teletype Control Unit Channel 4

LT19-F-5

Teletype Control Unit Channel 5
LT19H

7005891-0-0

Data Communications Cable

Module Circuit Schematics
B

R401-0-1

R401 Variable Clock

S107-0-1

S 107 Inverter

S 123-0-1

S123 Diode Gate

S203-0-1

S203 Triple Flip-Flop

S603-0-1

S603 Pulse Amplifier

W005-0-1

W005 Clamped Loads

W078-0-1

W078 Teletype Connector

W103-0-1

W103 Device Selector

W104-0-1

W104 I/O Bus Multiplexer Control

W107-0-1

W107 I/O Bus Receiver Circuit

W511-0-1

W511 Negative Level Converter

W602-0-1

W602 Bi-polar Level Amplifier

W705-0-1

W705 +3 .6V Integrated Circuit Power Supply

W706-0-1

W706 Teletype Receiver

Wl07-0-1

W707 Teletype Transmitter

4-3

Digital Equipment Corporation
Maynard, Massachusetts

printed in U.S.A.