Digital PDFs

DEC-8E-HMM3A-C-D

July 1973

542 pages

Original

30MB

Document:	PDP-8e Maintenance Manual Volume 3 External Bus Options
Order Number:	DEC-8E-HMM3A-C-D
Revision:
Pages:	542
Original Filename:	http://bitsavers.org/pdf/dec/pdp8/pdp8e/DEC-8E-HMM3A-C-D_PDP-8e_Maintenance_Manual_Volume_3_External_Bus_Options_Jul73.pdf

OCR Text

external bus options
maintenance manual
volume 3

t---t-r-

r---f:l,

I-f-

~ ,...,... t-----

-=-

ff-

- r---

:::::::",

f-l

-- -

.....

-......

r---r-

r---

IL rJ

-......-

~
.......

.---

- - -

1---1-1-

I'
'---------,

r---r--- 1"-_

I- I-I-r-

I-

r-I'- I'-r---

l.----

[

I-

1'--

I""'

IL t-~

~r--- 1-_

r---

r---->

l- I- I-r-

Jrn

urn

I'
I<--

-l""-

I----

------,
1"-1""-

rI<-

t- I'-

,...

t-r--f- -

-l""- t-_

....

t-_

r-r- 1""-_

........

I?. . . t-

'------;

I'-r-----

-- --

I-f-

h
h

h
l-

i- iff-

[ v---- ---

-,
d.

1-1-

i-I- f-I-

I"'"

i-- -~

:-::.

=::.

m m

l""-

::::.
.....

L - - -_ _ _ _ _ ~

t-t-

1-"'-

----

~ooo

MAINTENANCE MANUAL
VOLUME 3

For additional copies order No. DEC-8E-HMM3A-C-D from Direct Mail, Digital
Equipment Corporation, Maynard, Massachusetts 01754

Price: $25.00

digital equipment corporation · maynard. massachusetts

1st Edition, July 1972
2nd Printing (Rev) July 1973

The material in this manual is for informational purposes and is subject to change without

notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

CONTENTS

Page
PART 1 CONSOLE TELEPRINTER
CHAPTER 1

LC8-E DECWRITER CONTROL

Section 1 Introduction
Section 2 Installation
Section 3 Description
Section 4 Detailed Logic
1.1

1.2
1.3

1.4

lOT DECODER LOGIC
PRINTER RECEIVE LOGIC
KEYBOARD TRANSMIT LOGIC
.....
INT/SKIP LOGIC

1-3
1-3
1-7
1-8

Section 5 Maintenance
Section 6 Spare Parts

PART 2 PAPER-TAPE READER/PUNCH
CHAPTER 2

PC8-E HIGH-SPEED PAPER-TAPE READER/PUNCH

Section 1 Introduction
Section 2 Installation
Section 3 Description
Section 4 Detailed Logic
2.1
2.2
2.3

2.4

2.5
2.6

2.7
2-8

2.9
2.10

2-5
2-5
2-9
2-9

lOT DECODER LOGIC
TAPE READ LOGIC ..
CLOCK LOGIC
READER MOTOR CONTROL LOGIC
RDR INT/SKIP LOGIC
RDR BUFFER LOGIC
TAPE STATUS LOGIC
TAPE PUNCH LOGIC
PUNCH BUFFER LOGIC
INT/SKIP LOGIC

2-11
2-11
2-11

2-16
2-18
2-18

Section 5 Maintenance
Section 6 Spare Parts

iii

CONTENTS (Cont)
Page
PART 3 XIV PLOTTER
CHAPTER 3

XY8-E PLOTTER CONTROL
Section 1 I ntraduction
Section 2 Installation
Section 3 Block Diagram
Section 4 Detailed Logic

3.1
3.2
3.3
3.4

3-3

lOT DECODER LOGIC
TIMING LOGIC
DIRECTION TRANSFER LOGIC
INTERRUPT/SKIP LOGIC

3-5
3-5
3-5

Section 5 Maintenance
Section 6 Spare Parts

PART 4 LINE PRINTER
CHAPTER 4

LES-E LINE PRINTER
Section 1 Introduction
Section 2 Installation

4.1
4.2

4-1
4-2

UNPACKING
CHECKOUT
Section 3 Block Diagram Description
Section 4 Detailed Logic

4.3
4.4

4.5

4-5

SELECT LOGIC . . . .
INTERRUPT LOGIC
DATA TRANSFER LOGIC

4-7
4-8

Section 5 Maintenance
Section 6 Spare Parts

CONTENTS (Cont)
Page
PART 5 DATA COMMUNICATIONS EQUIPMENT
CHAPTER 5

DP8-E SYNCHRONOUS MODEM
Section 1 Introduction
Section 2 Installation
Section 3 Block Diagram Description

5.1
5.2
5.3

TRANSMITIER-MODEM DIALOGUE . . . . . . . . . . .
MODEM-RECEIVER DIALOGUE . . . . . . . . . . . . . .
DP8-E DATA BREAKS . . . . • • . . . . . . . . . . . .

. . . . . . ..

5-7

.••.... ,

5-8
5-8

Section 4 Detailed Logic

5.4

5.5
5.6

5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16

5.17
5.18

. . . . . 5-13
lOT DECODER LOGIC
CONTROL WORD LOGIC . . . . . . . . . . . . . . . . • . . . . . . . . . . . .
. .. 5-13
BREAK RQST, RECEIVE LOGIC . . . . • • . . . . • . . . . . • • . . . . . . .
. .. 5-13
RECEIVE DATA REGISTER LOGIC . . . . . . • . . . . . . . . . . . . . . .
. .. 5-19
BREAK RQST, TRANSMIT LOGIC . . . . . . . . . . . . . . . . . . . • .
. . 5-21
TRANSMIT DATA REGISTER LOGIC . . . . . . • . . . . . . . . . . .
. . 5-23
BRK RQST LOGIC
..........
. . . . . . . . . . . . . .
. . 5-24
BREAK GRANT LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 5-24
ACCESS ADDRESS COUNTER LOGIC . . . . . . • . . . . . . . • • . . . . . .
. .. 5-28
CURRENT/ACCESS ADDRESS REGISTER LOGIC
. . . . . . . '.
. . . . . 5-30
LOAD FIELD LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . • . 5-30
DETECTED CHARACTER REGISTER LOGIC . . . . • • . . . . • • • . . . • . • . . . . 5-33
INT/SKIP LOGIC
. . . . . . . . • . . . . . . . . . . . . . . . . . . . • • . . . . . . . . 5-33
READ STATUSfTEST PULSE LOGIC
. . . . . . . . . • . . . . . . • . . . . . . . . . . 5·36
LEVEL CONVERSION CI RCUITS . . . • . . . . . . . . . . . • • . . . • . . . . • . . • 5-39
Section 5 Maintenance
Section 6 Spare Parts

CHAPTER 6

KG8·E GENERATOR/DETECTOR
Section 1 Introduction
Section 2 Installation and Checkout
Section 3 Parity Check/Block Diagram

6.1
6.1.1
6.1.2
6.1.3
6.2

PARITY CHECK
VRC Parity Check
L RC Parity Check
CRC Parity Check
BLOCK DIAGRAM

6-2
6-2
6-2
6-4
6-6

CONTENTS (Cont)
Page
Section 4 Detailed Logic

6.3
6.4
6.5

6.6
6.7

6.8

10TDECODER LOGIC
CONTROL REGISTER LOGIC
VRC LOGIC . . . . . .
BCC CLOCK LOGIC ..
I/O TRANSFER LOGIC
BCC LOGIC . . . . . .

. 6·10
. 6-10
6-12
6-15
6-16
6-17

Section 5 Maintenance
Section 6 Spare Parts

PART 6 CARD READERS
CHAPTER 7

CM8-E/CR8-E CARD READERS
Section 1 Introduction
Section 2 Installation
Section 3 Block Diagram Description
Section 4 Detailed Logic

7.1
7.2
7.3
7.4

7.5
7.6

7-5
7-7
7-7

lOT DECODER LOGIC
SELECT CARD LOGIC
READ DATA LOGIC
INTERRUPT/SKIP LOGIC
STATUS LOGIC . . . .
READ GATING LOGIC

7-9

7-10
7-13

Section 5 Maintenance
Section 6 Spare Parts

PART 7 MAGNETIC TAPE
CHAPTER 8

TD8-E DECTAPE CONTROL
Section 1 Introduction
Section 2 Installation

8.1
8.2

8.3

8-2
8-2
8-2

INSTALLATION
ACCEPTANCE TEST
TD8-E INTERFACE

CONTENTS (Cont)
Page
Section 3 Functional Description
8.4
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.6
8.6.1
8.6.2
8.6.3

INSTRUCTION AND STATUS BITS
FUNCTIONAL OPERATION
I/O Decoder
Command Register ..
Data Register . . . . .
Mark Track Register
Flags and Status Bits .
Time Pulse Generator
TD8-E TIMING
..... .
Timing for Writing Time and Mark Tracks
Write Data Timing
Read Data Timing _ . . . . . . . . . . .

8-4
8-5
8-6
8-6
8-7
8-7
8-7
8-8
8-8
8-8
8-8
8-8

Section 4 Detailed Logic
8.7
8.7.1
8.7.1.1
8.7.1.2
8.7.1.3
8.7.1.4
8.8
8.8.1
8.8.2
8.8.3
8.8.4

8.9
8.10
8.10.1
8.10.2
8.11
8.11.1
8.11.2
8.11.3
8.12
8.13
8.14
8.15
8.16

INPUT/OUTPUT DECODER LOGIC
..... .
Control Logic
C Line Select Logic
Time Pulse 3 Logic .
I nitialize Logic . . . .
R un Signal and CON AL L H LT Logic
COMMAND REGISTER . . . . . .
Unit Select Logic . . . . . . .
Forward/Reverse (F/R) Logic
Stop/Go Logic .
ReadlWrite Logic
UTS DELAY LOGIC .
TIME PULSE GENERATOR
Write Time Track Pulses
Read Time Track Pulses
FLAGS AND SKIP LOGIC
Single Line Flag
Quad Line Flag and Counter Logic
Time Error Flag
........ .
MARK TRACK REGISTER . . . . . .
DATA REGISTER AND GATING LOGIC
DATA GATING LOGIC . . . . . . . . .
WRITE FUNCTION REGISTER . . . . .
WRITE ECHO AND SELECT ECHO CIRCUITS
Section 5 Maintenance
Section 6 Spare Parts

vii

· 8-17
· 8-17
· 8-17
· 8-18
· 8-18
8-18
· 8-18
· 8-18
· 8-18
· 8-18
· 8-20
· 8-20
· 8-20
· 8-21
· 8-22
· 8-23
· 8-23
· 8-23
· 8-25
· 8-25
· 8-26
· 8-27
· 8-27
· 8-27

CONTENTS (Cont)
Page
CHAPTER 9

TMS-E DECMAGTAPE CONTROL
Section 1 Introduction

9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.1.7
9.2
9.3

RECORDING METHODS AND DECmagtape FORMATS
NRZI Recording Method
9~Track Tape Format
.......... .
7-Track Tape Format
.......... .
Cyclic Redundancy Check Characters (CRC)
Longitudinal Redundancy Check Character (LRC)
Data Files
..... .
Track Assignments ..
COMPANION DOCUMENTS
SOFTWARE DOCUMENTS

9·2
9-2
9-3
9-5
9-5
9-7
9-7
9-7
9-8
9-8

Section 2 Site Preparation, Installation, and Acceptance Test
9.4
9.5
9.6
9.7

SITE PLANNING AND CONSIDERATIONS
INSTALLATION
ACCEPTANCE TEST
TM8-E INTERFACE

9-8
9-9
9-10
9-10

Section 3 Principles of Operation
9.8
9.8.1
9.8.1.1
9.8.1.2
9.8.1.3
9.8.1.4
9.8.1.5
9.8.2
9.8.2.1
9.8.2.2
9.8.2.3
9.8.2.4
9.8.2.5
9.8.3
9.8.3.1
9.8.3.2
9.8.3.3
9.8.3.4
9.8.3.5
9.8.3.6
9.8.4
9.8.4.1
9.8.4.2
9.8.4.3

BLOCK DIAGRAM DESCRIPTION
M8321 Output Control Module
lOT Instruction Decoder
Function Decoder
Gating Logic . . . . . .
Read/Compare Error Detection Logic
Skip Logic . . . . . . . . . .
M8327 Registers Module . . . . . .
Multiplexer and Data Register
Command Register . . .
Function Register
Current Address Register
Word Count Register . .
M8323 Transport Status and Control Module
Main Status Register .
Second Status Register . .
ERROR Flag . . . . . . .
Illegal Function Detection
PRESET and SET Pulse Generator
Control Busy (CNTL BSY) . . . .
M8322 Control and Data Break Module
Data Break Control Logic
Function Decoder
Interrupt Logic . . . . .

viii

9-17
9-17
9-17
9-17
9-18
9-18
9-18
9-18
9-18
9-18
9-19
9-20
9-20
9-21
9-21
9-21
9-22
9·22
9-22
9-22
9-22
9-22
9-23
. 9-23

CONTENTS (Cont)

Page
9.9
9.10
9.10.1
9.10.1.1
9.10.1.2
9.10.1.3
9.10.1.4
9.10.1.5
9.10.1.6
9.10.1.7
9.10.1.8
9.10.1.9
9.10.1.10
9.10.2
9.10.2.1
9.10.2.2

INSTRUCTIONS AND STATUS BITS
OPERATION AND PROGRAMMING
Single Cycle Data Break
Signal Conventions • . . .
Write Data
•.....
Read Data
Read/Compare
Extended Gap
Write End of File
Space Forward
Space Reverse
Rewind . . . .
Continuous Operation
Programming Notes'and Examples
Programming Notes
Programming Examples

· 9·24
· 9·35

.9·44
• 9·45
.. 9·45
.. 9·45
.. 9·48
.. 9-48
.. 9-48
.. 9-59
· . 9-59
.. 9-59
• • 9-59
· 9-59
· 9-59
· 9-59

Section 4 Detailed Logic
9.11
9.11.1
9.11.2
9.11.3
9.11.4
9.11.5
9.11.6
9.11.7
9;11.8
9.11.9
9.12
9.12.1
9.12.2
9.12.3
9.12.4
9.12.5
9.12.6
9.12.7
9.13
9.13.1
9.13.1.1
9.13.1.2
9.13.1.3
9.13.1.4
9.13.1.5
9.13.1.6
9.13.1.7
9.13.1.8
9.13.1.9
9.13.1.10

M8321 OUTPUT CONTROL MODULE
I nput/Output I nstruction Decoder
C Line Select Logic
TP3 Logic
CLR ALL Logic
AC ENABLE Logic
Skip Logic . • . . •
Output Control Function Decoder
Read/Compare Logic . . .
Write Data Select Logic
TM8-E REGISTERS (M8327)
Data Buffer Register and MUltiplexer
AC Input Gating . . . . . . .
Current Address (CA) Register ..
Word Count (WC) Register
Function Register . • . . . • . .
Command Register . . . . . . . . . . . . .
Buffered Command Register (BCM)
M8323 TRANSPORT STATUS AND CONTROL MODULE
Main Status Register . . . . . .
SC-2 ERROR Flag Logic
Illegal Function Logic
Data Late Logic . . . . .
Record Length I ncorrect Logic
Tape Rewinding
End of Tape
Beginning of Tape
Read/Compare Error
Parity Error
File Mark (EOF) ..

· 9-61
· 9-61
· 9-61
• . 9-61
9-63
.. 9-63

· 9-63
· 9-63
· 9-65
· 9-65
· 9-65
· 9-65
· 9-65
· 9-71
· 9-71
· 9-71
· 9-72
· 9-75
· 9-75
· . 9-75
· . 9-75
· . 9-75

· . 9-77
· . 9-79
· . 9-79
· . 9-79
· 9-79
· . 9-79
· . 9-79
• . 9-79

CONTENTS (Cont)
Page
9.13.1.11
9.13.1.12
9.13.2
9.13.2.1
9.13.2.2
9.13.2.3
9.13.2.4
9.13.3
9.13.4
9.13.5
9.13.6
9.13.7
9.14
9.14.1
9.14.2
9.14.2.1
9.14.3
9.14.4
9.14.5
9.14.6
9.14.7
9.14.8
9.14.9
9.14.10
9.14.11
9.14.12
9.14.13

Select Remote
File Protect
Second Status Register
EMA 7 I ncrement Error
Vertical Parity Error (C VPE)
LRC ERROR
...... .
CRC ERROR
...... .
Main and Second Status Register Multiplexer
Extended Memory Address Increment Logic
Control Busy (CNTL BSY) . . . .
PRESET and SET Pulse Generator
Data Late Error Check Logic
M8322 CONTROL MODULE
Control Function Decoder
Data Break Request Logic
Word Count Overflow Logic
Data Break Priority Logic
Processor Control Logic
MTTF (JOB DONE) Logic
Interrupt Logic . . . . . .
Change Transport Control Logic
Change Direction Control Logic
Write Data Ready Logic
Read and Write Control Logic
Data Multiplexer Control Logic
POWE R 0 K Logic
Initialize Logic ..

9·79
9·79
9·80
9·80
· 9·81
9·81
9·81
9·81
9·83
9·83
9·83
9·83
· 9·85
· 9·85
· 9·85
9·85
9-86
9·89
9·89
9·89
· 9·89
· 9·90
· 9-90
· 9·91
9·91
9·93
9·95

Section 5 Maintenance
Section 6 Spare Parts
Section 7 IC Descriptions
DEC 741531C
DEC 741741C
DEC 74175 IC
DEC 74197 IC
CHAPTER 10

· 9-97
· 9·99
9·100
9·101

TA8-E CASSETTE SYSTEM INTERFACE
Section 1 Introduction

10.1
10.2
10.3
10.4

PHYSICAL DESCRIPTION
POWER REQUIREMENTS
TAPE FORMAT ..
DOCUMENTATION . . .

10·2
10·2
10-2
10·3

CONTENTS (Cont)

Page
Section 2 Installation and Acceptance Test
10.5
10.6
10.7

10-4
10-5
10-5

INSTALLATION
ACCEPTANCE TESJ'
TAS-E INTERFACE
Section 3 Functional Description

10.S
10.8.1
10.S.2
10.S.3
10-S-4
10.S.5
10.8.6
10.9
10.9.1
10.10
10.10.1
10.10.1.1
10.10.1.2
10.10.1.3
10.10.1.4
10.10.1.5
10.10.1.6
10.10.1.7
10.10.1.S
10.10.1.9
10.10.1.10
10.10.1.11
10.10.2
10.10.2.1
10.10.2.2
10.10.2.3
10.10.2.4
10.10.2.5
10.10.2.6
10.10.2.7
10.10.2.S
10.10.2.9
10.10.2.10

FUNCTIONAL DESCRIPTION
lOT Decoder ..
Status A Register .
Function Register
Status B Register .
Read/Write Buffer Register
Data Flag . . . . . . . . .
INSTRUCTION AND STATUS BITS
Programming Sequence
INPUT AND OUTPUT INTERFACE SIGNALS
Output I nterface Signals .
SELECT ENABLE L
DRIVE B L
START L
REWIND L
BACK BLOCK GAP L
BACK FILE GAP L .
READ/WRITE FILE GAP L
WRITE MODE L
TRANSFER L . . . .
R EAD/WR ITE CRC L
INITIALIZE L
I nput I nterface Signals
OFF LINE L
READY L .
END FILE L
EOT/BOT L
REWIND L
WRITE PROTECT L
WRITE STATUS L
TRANSFER REQUEST L
TIME ERROR L
CRC BLOCK ERROR L

10-6
10-6
lO-S
10-9
10-9
10-9
10-9
10-9
10-9
10-9
10-12
10-12
10-12
10-12
10-12
10-13
10-13
10-13
10-13
10-14
10-14
10-14
10-14
10-14
10-14
10-14
10-14
10-14
10-14
10-14
10-15
10-15
10-15

Section 4 Detailed Logic
10.11
10.12
10.12.1
10.12.2
10.12.3

DEVICE SELECT AND lOT DECODER
CONTROL LOGIC . . . .
C Line Select Logic
Time Pulse Logic ..
Initialize and Clear All Logic

10-15
10-15
10-15
10-17
10-17

CONTENTS (Cont)
Page

10.13
10.14
10.15
10.16
10.16.1
10.17
10.18
10.19

10-18
10-18
10-20
10-20
10-22
10-22
10-23
10-23

STATUS A REGISTER
FUNCTION REGISTER
START LOGIC
.•.••.
READ/WRITE BUFFER REGISTER
Data Flag . .. • . . • . .
INTERRUPT LOGIC
••..•.
SKIP . • . . . . . . • . . . • .
OUTPUT DATA MULTIPLEXER
Section 5 Maintenance

10.20
10.21
10.21.1
10.21.2
10.21.3
10.21.4
10.21.5

10-24
10-24
10-25
10-25
10-26
10-26
10-27

PREVENTIVE MAINTENANCE
CORRECTIVE MAINTENANCE
lOT Decoder Check
Status A Register Check ..
Status B Check .. . . . • .
Read/Write Buffer Check
Command Decoder Check .
Section 6 Spare Parts
Section 7 IC Descriptions

. . . . . . . . . . . . . . . . . . . 10-27

DEC 74421C . . . . .

PART 8 DISKS
CHAPTER 11

RK8-E DISK DRIVE CONTROLLER
Section 1 Introduction

11.1
11.2
11.2:1
11.3
11.3.1
11.3.2
11.3.3
11.3.3.1
11.3.3.2
11.3.3.3
11.3.3.4
11.4
11.4.1
11.4.2
11.4.3

PURPOSE
PHYSICAL DESCRIPTION
RK05 Disk Drive •..
RECORDING METHODS AND FORMATS
Double Frequency Recording Method
Disk Addressing
Sector Format . . .
HEADER Word
CRC Character
Formatting A Cartridge
Write Protect
MAJOR REGISTERS
Command Register • . • . .
Current Address Register . .
Disk Address Register

xii

11-1
11-2
11-2
11-2
11-3
11-4
11-4
11-4
11-5
11-6
11-6
11-6
11-6
11-6
11-6

CONTENTS (Cont)
Page
11.4.4
11.4.5
11.4.6
11.4.7
11.4.8
11.4.9
11.5
11.5.1

Status Register . . . •
Data Buffer Register .
CRC Register . . . • .
Major State Register .
Bit Counters . . . . .
128· or 256·Word Counter
COMPANION DOCUMENTS
Software . . . . . . . . .

11·8
11·8
11·8
11·8
11·11
11·12
11·12
11·12

Section 2 Site Preparation, Installation, and Acceptance Test
11.6
11.7
11.8
11.9

SITE PREPARATION
INSTALLATION
ACCEPTANCE TEST
RK8·E INTERFACE .

11·12
11·13
11·13
11·15

Section 3 Operation and Programming
11.10
11.11
11.11.1
11.11.1.1
11.11.1.2
11.11.1.3
11.11.1.4
11.11.1.5
11.11.1.6
11.11.1.7
11.11.1.8
11.11.1.9
11.11.1.10
11.11.1.11
11.11.1.12
11.11.2
11.11.2.1
11.11.2.2
11.11.2.3
11.11.2.4
11.11.2.5
11.11.2.6
11.11.2.7
11.11.2.8
11.11.2.9
11.12
11.12:1
11.12.2
11.12.3
11.12.4

SINGLE CYCLE DATA BREAK DESCRIPTION
INSTRUCTIONS AND STATUS BITS . • . •
Command Functions .
Read Data
Read All
Write Data
Write All .
Write Protect ..
. • . . .
Seek Only
. . . . .
. •.•.
I nterrupt Enable . . . . •
• . . • • .
TRANSFER DONE on SEEK COMPLETE
Read or Write Half Block (128 Words) . . . .
Extended Memory Addressing •
Unit Select . . . . • • • .
Extended Cylinder Address
Maintenance Functions
Maintenance Mode .
Shift Enable . . . . . . . . . .
Check CRC Register . . . . . .
Check Command Register
Check Surface/Sector Register .
Check Data Buffer . . . .
Check Data Break Request
Check Lower Data Buffer
Maintenance Data
PROGRAMMING SEQUENCES . . .
Format A New Disk Cartridge .
Normal Read/Write
Bootstrap Loader
Seek Only

xiii

11·34
11·34
11·40
11·40
11·41
11·41
11·41
11·42
11·42
11·42
11·42
11·42
11·42
11·42
11·42
11·43
11·43
11·43
11·43
11·43
11·43
11·43
11·44
11·44
11·44
11·44
11·44
11·45
11·45
11·45

CONTENTS (Cont)

Page
11.12.5
11.12.6
11.12.7
11.13
11.13.1
11.13.2
11.13.3
11.13.4
11.13.5
11.13.6
11.13.7

.•.........
Overlapped Seeks
Recalibrate Selected Drive . . . . . . .
Data Transfers on Consecutive Sectors
PROGRAMMING EXAMPLES
Write All .
Recalibrate . . .
Seek Only
Overlap Seek
Write Data . . . . . • . . . . . . . . . . . . . . . . . . . .
Read All . . . . . . . . . . . . . . . . . . . . . . • . . . .
Read Data

11·46 .
11·46
11·46
11·46
11·47
11·47
11·48
11·49
11·50
11·51
11·51

Section 4 Theory of Operation

11.14
11.14.1
11.14.2
11.14.3
11.14.4
11.14.5
11.14.6
11.14.7
11.14.7.1
11.14.7.2
11.14.7.3
11.14.7.4
11.14.7.5
11.14.7.6
11.14.7.7
11.14.7.8
11.14.7.9
11.14.7.10
11.14.7.11
11.14.7.12
11.14.7.13
11.14.8
11.14.8.1
11.14.8.2
11.14.8.3
11.14.8.4
11.14.8.5
11.14.9
11.15
11.15.1
11.15.1.1
11.15.1.2

BLOCK DIAGRAM DESCRIPTION ..
I/O Bus Interface ..
Command Register . . . . .
Status Register . . . . . . .
. . . . .
Data Break Control Logic
Data Buffer Register . . . . . . . . . . . . . . . . . .
CRC Register . . . . . . . . . . . . . . . . . . . . . .
Control Sequencer
........... .
Major States
. . . . . . . . .
IDLE State .
. ......... .
RESTORE State
STROBE State .
HEADER A State
HEADER B State
HEADER C State
SECTOR SEEK State
HEADER 0 State
HEADER EState
DATA State
CRC State
END State . . . . . .
Read/Write Delays, Clocks, and Counters
Write Data Clock
Write Sync Delay
Read Delay . . .
Read Clock Data
Counters . . . .
Maintenance Logic . . . . . . . .
DETAILED LOGIC DESCRIPTION .
I/O Bus Interface . . . . .
MD Receivers
lOT Decoder Logic .

xiv

11·52
11·52
11·54
11·54
11·54
11·55
11·55
11·58
11·58
11·58
11·61
11·61
11·61
11·61
11·61
11·61
11·61
11·61
11·71
11·71
11·71
11·71
11·71
11·71
11·71
11·71
11·72
11·72
11·72
11·72
11·72
11·73

CONTENTS (Cont)
Page

11.15.2
11.15.2.1
11.15.2.2
11.15.2.3
11.15.2.4
11.15.2.5
11.15.2.6
11.15.3
11.15.3.1
11.15.3.2
11.15.4
11.15.4.1
11.15.4.2
11.15.4.3
11.15.4.4
11.15.4.5
11.15.4.6
11.15.4.7
11.15.4.8
11.15.4.9
11.15.4.10
11.15.4.11
11.15.5
11.15.6
11.15.7
11.15.7.1
11.15.7.2
11.15.7.3
11.15.7.4
11.15.8
11.15.8.1
11.15.8.1
11.15.8.3
11.15.8.4
11.15.8.5
11.15.9
11.15.10
11.15.10.1
11.15.10.2
11.15.11
11.15.11.1
11.15.11.2
11.15.11.3
11.15.12
11.15.13
11.15.13.1
11.15.13.2
11.15.13.3
11.15.13.4

........ .
Control Logic
C Line Select Logic
Time Pulse 3 (TP3) Logic
IDLE . . . . • .
Clear Logic •..
Interrupt Logic .
Skip Logic . • .
Command Register ..
Function Decoder
Unit Select Decoder
Status Register .. . • . . .
TRANSFER DONE
HEADS IN MOTION
SEEK FAIL
DRIVE STATUS ERROR
CONTROL BUSY ERROR
TIME OUT ERROR
WRITE LOCK ERROR
CRC ERROR
•.....
DATA REQUEST LATE .
DRIVE STATUS ERROR
CYLINDER ADDRESS ERROR
ERROR Flag . . . . . . .
Sector Address Comparator
Data Break Control Logic
Current Address Register.
. . . . • .
Data Transfer Control Logic . . . . . . . . . • .
Priority Logic
..........••.••.•.•
CPU Control Logic • . . . . • • . • • . • . . . .
Data Buffer Register and Control Logic • . . . .
Data Buffer Register Control Logic
.•••..•
Data Buffer Control 1 and Data Buffer 1
Data Buffer Control 2 and Data Buffer Register 2
Data Buffer Control 3 and Data Buffer Register 3
Data Buffer Control 4 and Data Buffer Register 4
Output Data Multiplexer
. . . • . . . . . .
ReadlWrite Logic
. . • • . . • • . • . . . • . • •
Write Clock
. . • . . . . . • •
Read Delay
..••..•....
CRC Register . .
. . . . . . . • • • . • • . . . .
Disk Address
. . . . . .
. . • • • . • •
CRC Character Computation
CRC Character Check
Major States
R K8-E Counters ..
12-Bit Counter
Word Counter
16-Bit Counter
Break Counter

11-75
11-75
11-75
11-75
11-75
11-76
11-76
11-76
11-76
11-76
11-78
11-78
11-78
11-78
11-78
11-78
11-78
11-78
11-80
11-80
11-80
11-80
11-80
11-80
11-81
11-81
11-84
11-84
11-84
11-85
11-85
11-87
11-87
11-89
11-89
11-90
11-90
11-90
11-92
11-92
11-92
11-94
11-95
11-95
11-95
11-95
11-95
11-99
11-99

CONTENTS (Cont)

Page
Section 5 Maintenance
11.16
11.17
11.17.1
11.17.2
11.17.3
11.17.4
11.17.5
11.17.6
11.17.7

PREVENTIVE MAINTENANCE
CORRECTIVE MAINTENANCE
Check Data Buffers
Checking the Command Register . . • • . . • •
Check Surface and Sector Register •••••••
Check CRC Register • • . . • . • . . . • • • •
Single Cycle Data Break Transfers (Read Operation)
Single Cycle Data Break Transfers (Write Operation)
Single Cycle Data Break Transfers (Write then Read)

•••• 11·99
. . .. 11·99
11·100
11·101
11·102
11·103
11·104
11·105
11·106

Section 6 Spare Parts
Section 7 IC Descriptions
11.18
11.,19
11.20
11.21

DEC 74155 IC .
DEC 74193 IC •
DEC 74851C ..
DEC 74161 IC •

11·109
11·109
11·109
11·115

PART 9 DISPLAYS
CHAPTER 12

VT8-E HIGH SPEED VIDEO DISPLAY TERMINAL AND CONTROL
Section 1 Introduction

12.1
12.1.1
12.1.2
12.1.2.1
12.1.2.2

SYSTEM OPERATING SPECIFICATIONS
CRT Operating Specifications (Motorola Raster Display)
Visible Display Specifications
. • • • .
Alphanumeric Mode .
Graphic Mode . . . • . . . . • . • .

12·2
12·2
12·3
12·3
12·3

Section 2 I nstallation and Acceptance Test
12.2
12.2.1
12.2.2
12.2.3

UNPACKING
Primary Power •.
VT8·E Installation
Acceptance Test .

12·4
12·4
12·5
12·8

Section 3 Operation and Programming
12.3
12.3.1
12.3.1.1
12.3.1.2
12.3.1.3

FUNCTIONAL DESCRIPTION
VT8·E Printer/Keyboard Control Module (M8335)
MD Bus Gating . . . . . . . . • . . . • . .
lOT Decoders
..••.•.
Data Bus Gating

xvi

12·8
12·8
12·8
12·9
12·9

CONTENTS (Cont)
Page

12.3.1.4
12.3.1.5
12.3.1.6
12.3.1.7
12.3.1.8
12.3.1.9
12.3.1.10
12.3.1.11
12.3.1.12
12.3.2
12.3.2.1
12.3.2.2
12.3.2.3
12.3.2.4
12.3.2.5
12.3.2.6
12.3.2.7
12.3.2.8
12.3.2.9
12.3.2.10
12.3.2.11
12.3.2.12
12.3.2.13
12.3.3
12.3.3.1
12.3.3.2
12.3.4
12.3.4.1
12.3.4.2
12.3.4.3
12.3.5
12.3.5.1
12.3.5.2
12.3.6
12.3.6.1
12.3.6.2
12.3.7
12.3.7.1
12.3.7.2

Keyboard Buffer . . . .
I/O Transfer Control ..
Interrupt and Skip Logic
Interrupt Logic . . . . .
Starting Address Register and Counter (SAR)
Extended Starting Address Register
Printer Buffer
.... .
PRINT DONE Flag . . . . . .
Higher Priority Detection
VT8-E Line Buffer Module (M8337)
Line Buffers A and B .
ASCII Decoding ROMs . . . .
Graphic Video Buffer
Character Display Mode Detection Logic
Visible Field Detection Logic
Single Cycle Data Break Control Logic
Processor Control Signals
Break Counters . . . . .
MA and EMA Bus Gates
Data Bus Gates . . . . .
Maintenance Enable
Frequency Divider Board (M8336)
Display lOT Decoder . . . . . . .
VT8-E Clock and Frequency Divider (M8336)
Real Time Clock Flag
...... .
Video and Sync Combining Circuits
lOT Instructions . . . . . .
Display Instructions
Keyboard Instructions
Printer Instructions
Display Data Format . . . .
Alphanumeric Data Format
Graphic Data Format
Display Monitor and Keyboard Switches and Controls
Display Monitor Switches and Controls
Keyboard Controls . . . . . . . .
Programming Examples
......... .
Graphic Display Program Example ..
Alphanumeric Display Program Example

12-10
12-10
12-10
12-10
12-10
12-10
12-10
12-10
12-10
12-11
12-11
12-11
12-11
12-11
12-11
12-12
12-12
12-12
12-12
12-12
12-12
12-12
12-12
12-12
12-12
12-13
12-13
12-13
12-14
12-16
12-17
12-17
12-18
12-18
12-18
12-18
12-22
12-22
12-22

Section 4 Detailed Logic Description

12.4
12.4.1
12.4.1.1
12.4.1.2
12.4.1.3
12.4.1.4

12-23
12-24
12-25
12-25
12-29
12-30

INTRODUCTION
Keyboard/Printer Logic
lOT Decoder Logic
Printer Receive Logic
Keyboard Transmit Logic
INT/SKIP Logic

xvii

CONTENTS (Cant)
Page
12.4.2
12.4.2.1
12.4.2.2
12.4.2.3
12.4.2.4
12.4.2.5
12.4.2.6
12.4.2.7
12.4.2.8
12.4.2.9
12.4.2.10
12.4.2.11
12.4.2.12
12.4.2.13
12.4.2.14
12.4.2.15
12.4.2.16
12.5
12.5.1
12.5.2
12.5.2.1
12.5.2.2
12.5.2.3
12.5.2.4
12.5.2.5
12.5.2.6
12.5.2.7
12.5.2.8
12.5.2.9

Display Logic
..... .
VT8-E Timing
VT8-E Timing Logic
Starting Address Register Logic
Data Break Counting Logic
Data Break Control Logic
Data Break Halt, Line Feed, and End-of-Screen Logic
Priority Logic
............... .
Line Buffer Register and Control Signal Logic . . . .
ROM Character Generator Logic . . . • . .
Alphanumeric Video Buffer Control Logic
Graphic Video Buffer and Control Logic
Visible Field Logic ..
Display Mode Logic . . . . . .
Maintenance lOT Logic
Display Interrupt and Skip Logic
Bell Logic
.....
DISPLAY MONITOR CIRCUITS
Keyboard Logic
Motorola CRT Display
Video Amplifier
Sync Separator .
Phase Detector .
Horizontal Oscillator
Pulse Shaper and Horizontal Drive
Horizontal Output . . . . . . . .
Vertical Oscillator Driver and Output
Retrace Blanking
Power Supply
.......... .

12-31
12-34
12-35
12-39
12-40
12-44
12-47
12-47
12-47
12-53
12-56
12-58
12-59
12-61
12-63
12-63
12-64
12-64
12-64
12-66
12-66
12-66
12-66
12-67
12-67
12-67
12-67
12-68
12-68 .

Section 5 Maintenance
12.6
12.6.1
12.6.2
12.6.3
12.6.3.1
12.6.4
12.6.4.1
12.6.4.2
12.6.4.3

INTRODUCTION
Equipment Required ..
Diagnostic Programming
Preventive Maintenance
Mechanical Checks
Troubleshooting
System Troubleshooting
Module Troubleshooting
VT8-E Assembly/Disassembly

APPENDIX A

ROM PATTERN TABLES

xviii

12-68
12-69
12-69
12-69
12-70
12-70
12-70
12-70
12-70

ILLUSTRATIONS
Figure No.

1-1
1-2
1-3
1-4
1-5
1-6
1-7
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13

3-1
3-2

3-3
3-4
3-5
3-6
4-1
4-2
4-3
4-4
4-5
4-6
5-1
5-2
5-3

5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16

Title
LC8-E Block Diagram
LC8-E lOT Decoder
Printer Receive Logic
Timing, Printer Receive Logic
Keyboard Transmit Logic
Timing, Keyboard Transmit Logic
I NT/Skip Logic
...... .
PC8-E Control, Block Diagram
lOT Decoder Logic
Tape Read Logic
Reader Timing
Clock Logic
Clock/Shift Pulse Timing
Reader Motor Control Logic
RDR INT/Skip Logic
Reader Buffer Logic
Tape Status Logic
Tape Punch Logic
Punch Buffer Logic
Punch INT/Skip Logic
XY8-E Block Diagram
lOT Decoder Logic . .
Timing Logic . . . . .
Function Timing; Pen Up, Pen Down, Start Zip (Encoded Plotter)
Direction Transfer Logic . . . . . . . . .
INT/Skip Logic
............ .
LE8-E Line Printer Control Block Diagram
LE8-E Control Timing
Select Logic
Interrupt Logic ..
Skip Logic
Data Transfer Logic
Simple Block Diagram, DP8-E
Detailed Block Diagram, DP8-E
Timing, Receive Break Request
Timing, Transmit Break Request
DP8-E lOT Decoder Logic .
Control Word Logic
..... .
Break ROST, Receive Logic
Sync Character Detection, Timing Diagram
Receive Data Register Logic
Break Request, Transmit . .
Transmit Data Register Logic
BRK ROST Logic
Break Grant Logic . . . . .
Access Add Counter Logic .
Current/Access Address Register Logic
Load Field Logic . . . . . . . . . . .

xix

Page

1-2
1-4
1-6
1-7
1-8
1-9
1-9
2-3
2-6
2-7
2-8
2-10
2-11
2-12
2-13
2-14
2-15
2-17
2-19
2-20
3-2
3-4
3-6
3-7
3-9
3-10
4-3
4-4

4-6
4-7
4-7
4-9

5-4
5-9
5-10
5-11
5-14
5-15

5-16
5-18
5-19
5-22
5-23
5-25
5-26
5-28
5·31
5-32

ILLUSTRATIONS (Cont)
Figure No.
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
7-1
7-2
7-3
7-4
7-5
7-6

7-7
7-8
7-9
7-10

7-11
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14

Title
Detected Character Register Logic
. . • • . . . . . . .
INT/Skip Logic (RING, CARRIER/AGC) '. . . . . . . . . . .
INT/Skip Logic (Character Detected, Bus Error, WC Overflow)
Read Status Logic . . . . . .
Test Pulse Logic . . . . . . .
DP8-E Input Circuit (Receiver)
DP8-E Output Circuit (Driver)
Self-Test Interconnection
LRC BCC Accumulation for Four 8-Bit Characters
CRC BCC Accumulation for Two 12-Bit Characters
KG8-E Block Diagram
lOT Decoder Logic . .
Control Register Logic
VRC Logic . . . .
VRC Logic Timing ..
BCC Clock Logic . . .
9.5 MHz Clock Pulse Generation
I/O Transfer Logic . . . . . . .
BCC Logic, Block Diagram .. .
6-, 7-, and 8-Bit LRC BCC Accumulation
BCC Generating Logic (Using LRC Technique - 6-Bit Character)
Logic Block Diagram: LRC-12, LRC-16
Logic Block Diagram: CRC-12, CRC-16
CR8-E/CM8-E Control Block Diagram
Timing, CR8-E/CM8-E Control
lOT Decoder Logic
Select Card Logic
Read Data Logic
I NT/Skip Logic
Status Logic
Timing, Transition Network
Data Gating, RCRB Instruction
Data Gating, RCRA Instruction
Data Gating, RCRC Instruction
TD8-E Block Diagram . . . . .
TD8-E Functional Block Diagram
Format of Data Loaded into the Command Register
Format of Word Transferred to AC
Timing for Writing Mark and Time Tracks
Write Data Timing . . . . . . . .
Read Data and Mark Track Timing
DECtape Data Format . . . . . .
I/O Decoder Detailed Logic
Command Register and UTS Logic
Time Pulse Generator Logic
Read Time Track Pulse Timing ..
Single Line Flag, Quad-Line Flag, and Skip Logic
Mark Track Register . . . . . . . . . . . . . . .

Page
5-34
5-35
5-37
5-38
5-39
5-39
5-40
5-43
6-3
6-7
6-8
6-10
6-11
6-13
6-14
6-15
6-15
6-16
6-18
6-19
6-21
6-22
6-23
7-2
7-3
7-6
7-8
7-9
7-11
7-12
7-12
7-14
7-15
7-15
8-1
8-5
8-6
8-7
8-9
8-14
8-15
8-16
8-17
8-19
8-21
8-22
8-24
8-25

ILLUSTRATIONS (Cont)
Figure No.
8-15
8-16
8-17
8-18
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
9-19
9-20
9-21
9-22
9-23
9-24
9-25
9-26
9-27
9-28
9-29
9-30
9-31
9-32
9-33
9-34
9-35
9-36
9-37
9-38
9-39
9-40
9-41
9-42
9-43
9-44

Title
Data Register . . . . . .
Data Gating Logic
Write Function Register
Write Echo and Select Error Circuits
TM8-E DECmagtape Control and TU10 Master System, Block Diagram
Data Recording Structure
9-Track Tape Format
7-Track Tape Format
TM8-E Module Installation
TM8-E Block Diagram
Contents of Command Register
Contents of Function Register
Contents of Main Status Register
Contents of Function and Second Status Register
LWCR and RWCR Instruction Data Flow
LCAR and RCAR Instruction Data Flow
LCMR and RCMR Instruction Data Flow
LFGR and RFSR Instruction Data Flow
LDBR and RDBR Instruction Data Flow
RMSR Instruction Data Flow
Single Cycle Data Break Data Transfer Data Flow
Core Dump Data Flow . . . . . . . . .
Single Cycle Data Break Timing Diagram
TM8-E Flow Diagrams
lOT Decoder Logic . . . . . . . .
Skip Logic . . . . . . . . . . . .
Output Control Function Decoder
Read/Compare and Write Data Select Logic
Input Data Multiplexer and Data Register
Data Register and Function Register Output Multiplexer
AC Input Gating and Holding Buffer Register
Current Address and Word Count Registers
Function Register
........ .
Command Register and Multiplexer
Error Flags . . . . . . . . . . . . .
Illegal Function Flag and Control Logic
Data Late and EMA I ncrement Error Flags
Record Length Incorrect Error Detection Logic
.............. .
Parity Error Flags
Main Status Register and Second Status Register Multiplexer
PRESET and SET Pulse Generation Logic
Data Late Error Check Logic
Control F unction Decoder . . . . •
Data Break Control Logic
.....
Priority and Processor Control Logic
MTTF (JOB DONE Flag) and Interrupt Request Logic
Change Transport and Buffered Command Register Control Logic
Change Direction Detection Logic . . . . . . . . . . . . . . . .

xxi

Page
8-26
8-28
8-29
8-30
9-1
9-3
9-4
9-5
9-10
9-17
9-19
9-20
9-21
9-21
9·25
9-26
9-27
9-27
9-30
9-31
9·46
9-47
9-48
9-49
9-62
9-64
9-64
9-66
9-67
9-68
9-69
9-70
9-72
9-73
9-74
9-76
9-77
9-78
9-80
9-81
9-82
9-84
9-84
9-86
9-87
9-88
9-90
9-91

ILLUSTRATIONS (Cont)
Figure No.
9-45
9-46
9-47
9-48
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
10-15
10-16
10-17
10-18
10-19
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
11-13
11-14
11-15
11-16
11-17
11-18
11-19
11-20
11-21
11-22
11-23
11-24
11-25

Title
Write Data Ready Logic
Read and Write Control Logic
Data Multiplexer Control Logic
Initialize and Clear Logic _ . _
TA8-E Interface and TU60 Cassette Drive, Block Diagram
Typical TU60 Format . . . . . . . . . . _ .
TU60 Capacity and Data Rate vs Block Length
T A8-E and TU60 Cabling
TA8-E Block Diagram . . . . . .
Contents of the Status A Register
Contents of the Status B Register
..... .
TA8-E Flow Diagram
Device Select and lOT Decoder Logic
Data Transfer Control Logic
Status A Register
Function Register
Start Logic . . .
Read/Write Buffer Register
TA8-E Flags . . . . . .
Interrupt and Skip Logic .
Output Data Multiplexer _
lOT Decoder Output Signal
DEC 74421C . . . . . . .
RK8-E Controller and RK05 Disk Drive System Block Diagram
Double Frequency Recording Method
Disk Format . . . . . . . . .
Contents of Command Register
Disk Address Register
Contents of Status Register
Read and Write Flow Diagram
RK8-E Module Installation
RK8-E Block Diagram
Data Break Control
Data Buffer Register
CRC Register . . . .
Major States Register
Read/Write Delays and Counters
RK8-E Flow Diagrams . . . . .
Maintenance Logic .. _ . . . .
MD Receivers and lOT Decoder
INITIALIZE, CLEAR ALL and Time Pulse 3 Logic
Interrupt and Skip Logic
Command Register . _ ..
Status Register . . . . _ .
Sector Address Comparator
Current Address Register .
Single Cycle Data Break Control Logic
Data Buffer Register . . . . __ . . .

xxii

Page
9-91
9-93
9-93
9-94
10-1
10-2
10-3
10-4
10-7
10-8
10-8
10-10
10-16
10-17
10-18
10-19
10-20
10-21
10-22
10-23
10-24
10-25
10-28
11-1
11-4
11-5
11-7
11-7
11-8
11-11
11-14
11-53
11-54
11-56
11-57
11-59
11-60
11-62
11-73
11-74
11-75
11-76
11-77
11-79
11-81
11-82
11-83
11-86

ILLUSTRATIONS (Cont)
Figure No.
11-26
11-27
11-28
11-29
11-30
11-31
11-32
11-33
11-34
11-35
11-36
11-37
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
12-10
12-11
12-12
12-13
12-14
12-15
12-16
12-17
12-18
12-19
12-20
12-21
12-22
12-23
12-24
12-25
12-26
12-27
12-28
12-29
12-30
12-31
12-32
12-33
12-34
12-35
12-36

Title
Data Buffer Register Control Logic
Output Data MUltiplexer . . . .
....... .
ReadlWrite Logic
CRC and Surface Sector Register
CRC Computation Block Diagram
Disk Address Output Buffers
Major States Register . . .
RK8-E Counters . . . . .
DEC 741551C Illustration
DEC 74193 IC Illustration
DEC 7485 IC Illustration
DEC 74161 IC Illustration
VT8-E Display Monitor
VT8-E Module Installation
VT8-E Block Diagram
Extended Address and Sense Switch Data
Keyboard Data Format
Printer Data Format . . . . . . . .
Alphanumeric Display Data Format
VT8-E Functional Block Diagram
Printer/Keyboard Block Diagram
lOT Decoder Logic . . . . .
Printer Receive Logic
Printer Receive Logic Timing
Keyboard Transmit Logic
Keyboard Transmit Logic Timing
Keyboard/Print Interrupt and Skip Logic
.....
Display Logic Block Diagram
Video Presentation for the Letter F
Two Alphanumeric Characters Displayed on the CRT
Sweep and Sync Signals
Clock Pulse Generator
.....
4-Bit Counter
VT8-E Timing Chain ..
Horizontal and Vertical Sync Circuits
Horizontal and Vertical Zone Flip-Flops
Alphanumeric and Graphic Line Timing
Starting Address Register Logic
Starting Address Register Control Logic
...... .
Data Break Control Logic
Data Break Counting for 32 Characters/Line
PRESET BRK Generation Graphic Mode
Data Break Control Logic . . . . . .
Data Break Halt, Line Feed/EOS Logic
Priority Logic
.....•....
Line Buffer Register Logic . . . .
Line Buffer Register Control Logic
Line Buffer Register . . . . . . .

xxiii

Page
11-88
11-90
11-91
11-93
11-94
11-94
11-96
11-98
11-110
11-112
11-114
11-116
12-1
. 12-8
. 12-9
12-14
12-15
12-16
12-17
12-24
12-24
12-26
12-27
12-28
12-29
12-30
12-31
12-32
12-33
12-34
12-35
12-36
12-36
12-37
12-38
12-39
12-40
12-41
12-42
12-43
12-44
12-44
12-45
12-46
12-48
12-49
12-50
12-51

ILLUSTRATIONS (Cont)
Figure No.
12-37
12-38
12-39
12-40
12-41
12-42
12-43
12-44
12-45
12-46
12-47
12-48
12-49
12-50
12-51
12-52
2-53
12-54
12-55

Title

Page

line Buffer Timing for 32 Character Line
line Buffer Timing for 64 Character line
Line Buffer Timing ........
ROM Character Generation Logic
ROM Functional Logic Diagram
Alphanumeric Video Buffer
Character Timing for a 32 Character line
Character Timing for a 64 Character line
Graphic Video Buffer Control Logic
Graphic Word Timing
12-Bit Data Word Format
Display Control Logic
BBF and EBF Timing
Display Mode Logic
Maintenance lOT Logic
Display Interrupt and Skip Logic
...........
Bell Logic
CRT Horizontal Oscillator Waveforms
CRT Vertical Oscillator Waveforms

12-52
12-52
12-53
12-54
12-55
12-57
12-58
12-59
12-60
12-61
12-61
12-62
12-62
12-63
12-64
12-65
12-65
12-67
12-68

TABLES
Table No.
1-1
1-2
2-1
2-2
2-3
3-1
3-2
3-3
3-4
4-1
4-2
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9

6-1
6-2
7-1

Title
LC8-E lOT I nstruction list
LC8-E Recommended Spare Parts
PC8-E lOT Instructions
.....
Cable/Connector Pin Assignments
PC8-E Recommended Spare Parts
XY8-E lOT Instruction list
List of Plotter Directions . _ . . .
Pin Assignments, Interconnecting Cable
XY8-E Recommended Spare Parts
LE8-E lOT Instruction List
LE8-E Recommended Spare Parts
Jumper Connections, M839 Module
Jumper Connections, M866 Module
DP8-E lOT Instruction List
Signal Level Terminology
.....
EIA/Current Mode Electrical Specifications
Modem-Interface Cable Pin Information ..
M866-M839 Top-Connector Signals
Equivalent E IA and CCITT Circuit Designations
DP8-E Recommended Spare Parts
KG8-E lOT Instruction List
KG8-E Recommended Spare Parts
CM8-E/CR8-E Instruction List ..

xxiv

Page
1-5
1-10
2-4
2-21
2-21
3-3
3-8
3-11
3-11
4-5
4-8
5-3
5-4
5-5
5-41
5-41
5-43
5-44
5-45
5-46
6-9
6-24
7-4

TABLES (Conti
Table No.
7-2
7-3
7-4
7-5
8-1
8-2
8-3
8-4
8-5
8-6
8-7
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
9-19
10-1
10-2
10-3
10-4
10-5
10-6
10-7
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11

Title
Translation, Hollerith Code - Alphanumeric Code
Translation, Hollerith Code - Compressed Code
Connector Pin Assignments, J1-J5, J1-J2
CR8-E/CM8-E Recommended Spare Parts
TD8-E Signal Interface
M960 Module Jumpers . . . . . . .
...... .
Device Code Jumpers
TD8-E Signals and Signal Functions
CoLine Select Levels and Transfer Operations
Write Echo and Select Echo Signal and Voltage Levels
TD8-E Recommended Spare Parts
A Five-Character Record . . . . . . . . . . .
CRCC In Register When Writing . . . . . . .
TU10 Track Assignments for Data and Parity
TM8-E Module Power Requirements . . . . .
M8321 Output Control Module Signals and Interface
TM8-E M8323 Transport Status Control Module Signals and Interface
TM8-E M8321 Output Control Module Top Connector Signals
TM8-E M8322 Control Module, Top Connector Signals
TM8-E M8327 Register Module, Top Connector Signals . . .
TM8-E M8323 Transport Status and Control Module, Top Connector Signals
Command Register Contents and Function
Function Register Contents and Functions
Main Status Register Contents and Indications .
Second Status Register Contents and Functions
TM8-E Signals and Signal Functions . . . . . .
C Line Select Levels for TM8-E Transfer Operations
Data Multiplexer Selection Levels . . . . .
Read and Write Control Logic Signal Levels
TM8-E Spare Parts . . . . . . . . . . . .
Device Code Selection Jumper Installation
TA8-E Input and Output Signals .
TA8-E Instructions . . . . . . . .
Contents of the Status A Register
Contents of the Status B Register
C Line Select Levels for Transfers to the AC
T A8-E Spare Parts • • • . . . .
RK05 Disk Drive Specifications
Major States . . . . . . . . . .
Device Select Jumper Installation
RK8E Priority Selection
RK8-E-RK05Interface Cable (P2)
RK8-E-RK05Interface Cable (P1)
M7104 Top Connector Signal List
M7105 to M71 04 Top Connector Signal List
M7105 to M7106 Top Connector Signal List
M7106 Top Connector Signal List . . . . .
Clear Operations Using the DCLR Instruction

xxv

Page
7-16
7-17
7-18
7-18
8-3
8-4
8-5
8-10
8-18
8-29
8-31
9-6
9-6
9-7
9-9
9-11
9-12
9-13
9-14
9-15
9-16
9-23
9-28
9-32
9-33
9-35
9-63
9-68
9-92
9-96
10-4
10-5
10-11
10-12
10-13
10-15
10-27
. 11-3
. 11-9
11-14
11-14
11-15
11-17
11-19
11-23
11-26
11-30
11-34

TABLES (Conti
Table No.
11-12
11-13
11-14
11-15
11-16
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-S
12-9
12-10
A-1
A-2
A-3

Title
Contents of Status Register
Command Functions . . .
Maintenance Functions
CoLine Select Levels and Transfer Operations
RKS-E Spare Parts . . . . . . . . . . .
AC Power Cable . . . . . . . . . . .
Device Code Select Jumper Installation
Priority Jumper Installation . . . . .
Switches and Controls . . . . . . . .
VTS-E Transmit Codes - Full ASCII Operation ..
VTS-E Transmit Codes - Half ASCII Operation (switch in position 2)
VTS-E Receiving Codes
..... .
Character H, EVEN ROM Data Bits
Character H, XTRA ROM Data Bits
Equipment Required . . . . . . .
ROM Pattern Table (EVEN ROM)
ROM Pattern Table (ODD ROM)
ROM Pattern Table (XTRA ROM)

xxvi

Page
11-36
11-39
11-41
11-75
. 11-10S
12-4
. 12-6
. 12-7
12-1S
12-19
12-20
12-21
12-55
12-56
12-69
A-1
A-5
A-9

PREFACE
This manual, the third in a series of three, describes peripheral controller options of the PDP-8/E, PDP-8/F, and PDP-8/M.
The content of this manual includes installation procedures, theory of
operation, and maintenance procedures for the options described. It
is assumed that the reader is thoroughly familiar with Volume 1 of
this series, and with the applicable sections of the 1972 PDP-8IE &
PDP-81M Small Computer Handbook.

xxvii

PART 1
CONSOLE TELEPRINTER

CHAPTER 1
LC8-E DECWRITER CONTROL

SECTION 1 INTRODUCTION
The LC8-E DECwriter Control interfaces the parallel version of the LA30 DECwriter (LA30P) to the PDP-8/E.
The Control consists of a single M8329 quad module that plugs into the OMNIBUS and connects to the
DECwriter with a signal cable that is supplied with the module.
The LA30 DECwriter is discussed here only to the extent necessary to both fully describe LC8-E Control
operation and present supplementary information concerning installation and checkout. Details concerning the
installation, operation, troubleshooting, and maintenance of the LA30, itself, can be found in the LA30
DECwriter Maintenance Manual, DEC-OO-LA30-DA. Other publications and documents relevant to the LC8-E

are:
a.
b.

c.
d.

PDP-8IE & PDP-81M Small Computer Handbook - DEC, 1972
PDP-8IE Maintenance Manual, Volume 1
LA30 DECwriter Diagnostic, MAINDEC-8E-D2FA
DEC Engineering Drawing, DECwriter Control, E-CS-M8329-0-1.

SECTION 2 INSTALLATION
The LC8-E DECwriter Control is installed on site by DEC Field Service personnel. The customer should not
attempt to unpack, inspect, install, checkout, or service the equipment.
Insert the LC8-E Control in the PDP-8/E OMNIBUS. See Table 2-3, Volume 1, for information concerning
recommended module priorities (the LC8-E is a "non-memory" option).
Connect the LC8-E to the DECwriter with the signal cable provided. Jl of the LC8-E, a 40-pin Berg Connector,
connects to module slot A02 of the LA30P logic rack.
See Chapter 2 of the LA30 DECwriter Maintenance Manual for additional information concerning system
installation and for procedures to be followed to checkout both the Control and the DECwriter.

SECTION 3 DESCRIPTION
Figure 1-1 is a block diagram of the LC8-E Control. Pin assignments for OMNIBUS signals and connector Jl
signals can be found on engineering drawing no. E-CS-M8329-0-1. Information concerning pin assignments of
the interconnecting cable is given in Section 5.

1-1

I
OMNIBUS

KYBD(O)L

DATA 4-11 L~----------------------------------.
rOT,
CONTROL
SIGNALS
'---+----1 XMIT STROBE L
' - - - - - - - - j - - - t BI T 1-7 L

SKIP L~---------------------------------------'
rNTRQSTL~---------------------------------'

INTERNAL 110 L 1+-----,
CO L,CI L 1----,

rIo PAUSE L

rOT
INSTRUCTIONS

MD 3-11 L

rOT,
CONTROL
SIGNALS

.-------+lBI T t-7
.-----+1 RCVR STROBE L
rOT,
CONTROL
SI GNALS
DATA5-11LL---------------------------------~

I
I

'--------' DE MAN D

I
BE-Q385

Figure 1-1 LC8-E Block Diagram

The LC8·E has two distinct functions: transfer of data from the CPU AC Register to the LA30 Printer Buffer
Register and transfer of data from the LA30 Keyboard Buffer Register to the AC Register. The transfer of data
to the LA30 Printer Buffer is carried out by the printer receive logic. When the LA30 is able to receive data, it
asserts the DEMAND signal. This signal sets the printer flag in the printer receive logic. The resulting PRNT (0) L
signal causes the I NT/skip logic to assert OM N IBUS INT RQST L if the LC8-E has been logically connected to
the interrupt system. Alternatively, PRNT (0) L can be tested by a program skip instruction in the I NT/skip logic.
In either case, the computer ultimately proceeds to a program subroutine that begins the data transfer. When
this subroutine is executed, the information is transferred from the AC Register to the DATA 5-11 lines and
clocked into a 7-bit register in the printer receive logic. The register outputs are available at J1 as the
BIT 1-7 signals. The logic then generates a RCVR STROBE L signal that clocks the BIT 1-7 data into the
Printer Buffer Register, clears the Printer flag, and causes the LA30 to negate the DEMAND signal.
The transfer of data from the LA30 Keyboard Buffer Register to the AC Register is carried out by the keyboard
transmit logic, When an LA30 key is depressed, information is applied, via the BIT 1-7 lines, to a 7-bit register
in the keyboard transmit logic. When the LA30 generates an XMIT STROBE L signal, the information is clocked
into the 7-bit register and the KYBD (0) signal is asserted. The KYBD (0) L signal can be tested in the INT/skip
logic with a skip instruction, or the interrupt system can be used to cause the program to enter an appropriate
subroutine. When the subroutine is executed, the information is gated from the register in the keyboard transmit
logic to lines DATA 5-11 (the logic asserts the DATA 4 L signal separately so that the input character is compatible with the modified·ASCII Teletype@ code), then to the AC Register. The AC is loaded and, simultaneously,
KYBD (0) L is negated.
®reletype is a registered trademark of Teletype Corporation.

1-2

SECTION 4 DETAILED LOGIC
1.1

lOT DECODER LOGIC

The lOT decoder logic is shown in Figure 1-2. The LC8-E uses 12 lOT instructions, 6 for the keyboard functions
and 6 for the printer functions (one of the listed printer lOTs - Skip on Printer or Keyboard Interrupt - applies
to both functions). More than one LA30 DECwriter can be interfaced to the PDP-8/E at the same time. The
LC8-E Control associated with each LA30 must have a unique device selection code. Therefore, the M8329
Control Module is fabricated with machine-inserted jumpers and solder terminals that allow the user to assign
any two of 64 possible device selection codes to a particular LC8-E (care should be taken when assigning device
selection codes to preclude mUltiple assignments of the same code). Figure 1-2 illustrates the octal codes and
mnemonics that pertain when the LC8-E Control is manufactured. The octal codes and mnemonics are listed in
Table 1-1 and the respective functions, which remain constant regardless of the code or mnemonic, are detailed.
Figure 1-2 identifies the 12 machine-inserted jumpers, Wl through W12, and 6 groups, lettered from A to F, of
4 numbered solder terminals (jumper and terminal designations are etched on the quad module for each identification). To change a control device selection code, first cut a selected "W" jumper (or jumpers); then, solder a
new jumper between designated terminals associated with the "W" jumper(s). For example, the device selection
code for the keyboard functions can be changed from 03 to 13 by removing W5 and connecting terminals C3 and
C4; the printer functions device code can be changed from 04 to 10 by removing W6 and W8 and connecting
terminals C2 and C4 and 02 and 03.
As Figure 1-2 shows, the device selection code signals, 603X and 604X, are applied to separate DEC 7442 Decoder
ICs. The device operation codes represented by bits MD 9, 10, and 11 are then decoded by E9 and E6 to provide
the listed lOT instruction signals. Note that the device selection code signals assert the OMNIBUS INTERNAL
I/O L signal; thus, the positive I/O bus interface ignores the lOT instruction.
Three of the keyboard lOT instruction signals cause OMNIBUS "C" lines to be activated. When the KeC L
signal is generated, both the CO Land Cl L signals are asserted; the resulting transfer of Os clears the AC Register.
The KRB L signal also results in a transfer to the AC; however, this transfer involves data from the keyboard,
rather than Os. Finally, the KRS L signal causes only the Cl L signal to be asserted; the result is an inclusive-OR
transfer of data to the AC.
1.2 PRINTER RECEIVE LOGIC
The printer receive logic is shown in Figure 1-3. The 7-bit register is shown only in part, the logic associated with
bits DATA 10-6 being similar to that illustrated for bits 11 and 5. Significant signals are related by the timing
diagram in Figure 1-4. Refer to both figures when reading the logic description.
The LA30 printer routine is initiated by the program instruction TFL, Set the Printer Flag. At TP3 time of this
instruction, NAND gate E7 is enabled, causing the PRNT flip-flop to be set. This flip-flop is also set by the
DEMAND signal, which is asserted by the printer each time it completes a print cycle (Figure 1-4 illustrates this
signal rather than the TF L L signal). If the LC8-E is logically connected to the interrupt system, as Figure 1-4
and this discussion assume, PRNT (0) L causes the INT/skip logic to assert OMNIBUS INT RQST L. The program
proceeds to an interrupt servicing routine to determine the identity of the requesting device. The TSK instruction
in the routine causes the program to jump to an LC8-E routine that determines if the printer or keyboard
requested the interrupt (other options are open to the programmer, this is but one example). Ultimately, the
LC8-E printer routine executes the TLS instruction.

'·3

I/O PAUSE L - - - c i

"P--------,

cF)b----

CO L

'-----

~/
-

M03 L

UE14

~E14
INTERNAL
I/O L

603X

~
L_+_<

M04 L

'--b-+-+-+- KCF L (6030)
b-+-+-+- KSF L (6031)
7~£2 b-_+-+- KCC L (6032)
~~g~

c-f--< E13 ~+--+----lEll!Xl>---+--+-+-klI

] E35

M09 L -+----<:j

KRS L (6034)

D--+-- KIE L (6035)
b-~~- KR8

L (6036)

'}--t-+-r-.

_~__-djE35
\-- ~
~

M06 L

MOIO L -

we
WIO

......---

E35 \ - MOll L - --------oI
01.....-.../

. - - 0 - - - - TFL L (6040)
0 - - - - TSF L (6041)

M07 L

~ 7~~2 b - - - - TCF L

'---- 6~~~
l--< E 1 ,}---,-----.----I E 21

MOB L
604X

Figure 1-2 LC8-E lOT Decoder

(6042)

TPC L (6044)
TSK L (6045)
TLS L (6046)

)b-~~-Cl L

'-----

Table 1-1
LC8-E lOT Instruction List
Octal Code

Mnemonic

6030

KCF

Clear the Keyboard flag. Clears the KYBD flip-flop.

6031

KSF

Skip on the Keyboard flag. Senses the state of the KYBD
flip-flop. If the flip-flop is set, increments the program
counter so that the next sequential instruction is skipped.

6032

KCC

Clear the flag, clear the AC. Clears both the KYBD flipflop and the AC Register.

6034

KRS

Read the keyboard buffer. Gates character information
from the keyboard transmit logic and ORs it into AC
Register bits 5 through 11. Sets AC4.

6035

KIE

Set/clear interrupt enable. Sets the I NT ENA flip-flop if
AC11 is logic 1; clears the flip-flop if AC11 is logic O.

6036

KRB

Read the keyboard buffer, clear the flag, clear the AC.
Gates character information from the keyboard transmit
logic and jams it into AC Register bits 5 through 11. Sets
AC4. Clears the KYBD flip-flop.

6040

TFL

Set the printer flag. Sets the PRNT flip-flop.

6041

TSF

Skip on the Printer flag. Senses the state of the PRNT
flip-flop. If the flip-flop is set, increments the program
counter so that the next sequential instruction is skipped.

6042

TCF

Clear the Printer flag. Clears the PRNT flip-flop.

6044

TPC

Load the printer buffer and print. Causes the character
information to be gated to the BIT 1-7 lines. Sets the
RCVR STROBE flip-flop. At TS2 of the next instruction,
the information is loaded into the LA30 input buffer.

6045

TSK

Skip on a keyboard/printer interrupt request. Skips the
next sequential instruction if the I NT ENA flip-flop is set
(the LC8-E is logically connected to the interrupt system)
and if either the KYBD flip-flop or the PRNT flip-flop is
set.

6046

TLS

Load the printer buffer and print. Clears the flag. The
character information is gated to the BIT 1-7 lines. Sets
the RCVR STROBE flip-flop. At TS2 of the next instruction, the information is loaded into the LA30 input buffer.
Clears the PRNT flip-flop.

Function

During TS2 of the T LS instruction, information is gated from the AC Register to the DATA lines and remains on
the DATA lines through TS3. When TLS L is decoded in the lOT Decoder logic, it enables NOR gates E5B and
E5D (Figure 1-3). The enabled output of E5D causes the information on lines DATA 5-11 to be gated to the
D-inputs of the register flip-flops, while at the same time providing a high level on the D-input of E27B, the
RCVR STROBE L flip-flop. At TP3 time of the instruction the register flip-flops are clocked, flip-flop E27B is
set, and the PRNT flip-flop is cleared. The register data is applied, via the BIT 1-7 lines, to the printer buffer

1-5

register. During TS2 of the instruction following TLS, NAND gate E29 asserts the RCVR STROBE L signal
(flip-flop E27B is cleared at TP3 time of this instruction). This signal loads the printer buffer register and negates
the DEMAND signal. When the print cycle ends approximately 30 ms later, the DEMAND signal is again asserted
and a new transfer is begun.

+5V

BIT 1
I

BITS 2-6
SIMILAR
I
I

>---<~------ BIT 7

+5V

TLS L
TPC L - " - -__

----DATA 10-6 L---DATA 11 L SIMILAR
DATA 5 L

TP3

TCF L

TLS L

INITIALIZE-------... '---"L-J--

DEMAND

8£-0387

Figure 1-3 Printer Receive Logic

1-6

I
DEMAND

PRNT (0) L

INT RQST L

TSK L

SK I P L

TLS L

TS2 L

TP3

DATA 11-5 L

I:
I
I
I
I

I
I

",30MS

I
I

INSTRUCT I ON

I
I

RCVR STROBE L

_ _ PRINT CYCLE

I
I

XXXX

II
I
II

1-7

BIT

I
I

NOTE
T1, T2 and T3 are distinct time periods.
The amount of time between periods ;s
Q function of program-rou1ine ey.ecuticr'\ tim€'
8E-0388

Figure 1-4 Timing, Printer Receive Logic

1.3 KEYBOARD TRANSMIT LOGIC
The keyboard transmit logic is shown in Figure 1-5. The 7-bit register is shown only in part. Significant signals
are related by the timing diagram in Figure 1-6. Refer to both figures when reading the logic description.
The user initiates the keyboard sequence by depressing a key on the LA30. The character information is placed
on the BIT 1-7 lines. After a period of time that allows the BIT lines to settle, the keyboard generates the
XMIT STROBE L signal. This signal clocks the information into the 7-bit register and sets the KYBD flip-flop.
If the LC8-E is logically connected to the interrupt system, as assumed, KYB D (0) L causes the INT/skip logic to
assert the OMN IBUS I NT RQST L signal. The program proceeds to an interrupt servicing routine to determine
the identity of the requesting device. The TSK instruction in the routine causes the program to jump to an
LC8-E routine that determines if the printer or keyboard requested the interrupt. Ultimately, the LC8-E keyboard
routine executes the KRB instruction.
1-7

DATA 4 L----------------------------------------------------------------,
DATA5L--,~--------------------------------------------------_,

DATA 6-10 L
SIMILAR
I

DATA11L--~1----~--------------------------------,

KRS L
K RB L___'---""

BIT 7 L
I

I
I
I
I

I
I

BITS 2-6
SIMILAR
I

I
I

I
I
I

...-......- - - - - - - BIT 1 L

BE-Q389

Figure 1-5 Keyboard Transmit Logic

When the KRB instruction is decoded, the lOT decoder logic generates the KRB L signal and activates the CO and
C1 lines. The KRB L signal enables NOR gate E8D; the output signal from E8D gates the information from the
register outputs to DATA lines 5-11, and also causes NAND gate E18C to assert DATA 4 L. The DATA lines
are gated to the AC Register and the information is clocked into the register at TP3 time. Also at TP3, the KYBD
flip-flop is cleared, readying the logic for a new data transfer.
1.4 INT/SKIP LOGIC
The INT/skip logic is shown in Figure 1-7. The PRNT (0) L signal and the KYBD (0) L signal can cause program
skips when tested by instructions TSF and KSF, respectively. The signals can also be tested by the TSK instruction, provided the INT ENA flip-flop, E10, has been set, logically connecting the LC8-E to the interrupt system.
When E10 is set, the TSK L signal enables NAND gate E4D, which, in turn, enables AND-NOR gate 1:15 if
either the PRNT (0) L signal or the KYBD (0) L signal is asserted. Simultaneously, NAND gate E17 asserts the
INT RQST L signal.
The I NT ENA flip-flop is set by the OMNIBUS INITIALIZE signal for the PDP-8 Family program compatibility.
To clear the flip-flop, removing the LC8-E from the interrupt system, load AC11 with logic 0 and then program
the KIE instruction. The logic 0 in AC11 keeps the DATA 11 L signal negated. Thus, the D-input of E10
remains high. At TP3 time, NAND gate E7 provides a clock pulse for E10, clearing the flip-flop. E10 can be set
at any time with the same instruction merely by loading AC11 with logic 1.
1-8

BIT

1-7

XMIT STROBE

L~
L~~_ _ _ _ _ _ _ _ _ _ _ _~_ _ _ _ _ _ _ _ _ _ _ _ _ __ _

KYBD (0)

L~~__________________________~____________________~

INT RQST

L~~__________________________~____________________~

TSK L

SKIP

KRB L

DATA 11-4 L

GOL,G1L

TP3 __________________________

~r__l~__~------------------~r--l~----------SE· 0390

Figure 1-6 Timing, Keyboard Transmit Logic

TSF L - - - < I f

PRNT (0) L _ - - < I f

KS F L ---+--<If

KYBD (0) L ---+_-01
SKIP L

P - - - - - - - - - - - - - - - I N T RQST L

DATA 11 L

8E- 0391

Figure 1-7 INT/Skip Logic

1-9

SECTION 5 MAINTENANCE
Refer to Volume 1 and to the LA30 DECwriter Maintenance Manual for maintenance information that pertains
to both the LC8-E Control and the LA30 DECwriter. The LA30 DECwriter Diagnostic, MAINDEC-8E-D2FA,
should be run when an error is suspected.

SECTION 6 SPARE PARTS
Table 1-2 lists recommended spare parts for the LC8-E. These parts can be obtained from any local DEC office
or from DEC, Maynard, Massachusetts.
Table 1-2
LC8-E Recommended Spare Parts
DEC Part No.

Description

19-10394
19-10392
19-10391
19-10046
19-9929
19-9973
19-9686
19-9056
19-9004
19-5580
19-5579
19-5575
19-5547
10-1610
10-0067
10-0024
70-8417

IC DEC 5384
IC DEC 5380
IC DEC 5314
IC DEC 7442
ICDEC7417
IC DEC 97401
IC DEC 7404
IC DEC 74HOO
IC DEC 7402
IC DEC 7450
IC DEC 7440
IC DEC 7400
IC DEC 7474
Capacitor, 0.01 JiF, 100V, 20% Disk
Capacitor, 6.8 JiF, 35V, 20% Tant
Capacitor, 47 pF, 100V, 5% DM
Signal Cable

1-10

Quantity

PART 2
PAPER-TAPE READER/PUNCH

CHAPTER 2
PC8-E HIGH-SPEED PAPER-TAPE READER/PUNCH

SECTION 1 INTRODUCTION
The PCS-E (or the desk-top model, PCS-EB) Reader/Punch option consists of a control module and a high-speed
paper-tape reader/punch manufactured by DEC [Model PC04BL (60 Hz) or PC04BM (50 Hz)]. The control
(DEC MS40) plugs into the PDP-S/E OMNIBUS and connects to the external reader/punch via two signal cables
that are supplied with the system.
The PC04 Reader/Punch is discussed here only to the extent necessary to fully describe control operation and
present supplementary information concerning installation and checkout. Details concerning the installation,
operation, troubleshooting, and maintenance of the reader/punch, itself, can be found in the PC04/PC05
Paper- Tape Reader/Punch Maintenance Manual [DEC-OO-PCOA-D (1)]. Other publications and documents rele-

vant to the PCS-E are:
a.
b.

c.
d.

PDP-8/E & PDP-8/M Small Computer Handbook - DEC, 1972
PDP-8/E Maintenance Manual, Volume 1
Roytron Model 500 Maintenance Manual
PCS-E Diagnostic, MAINDEC-SE-D2CA
DEC Engineering Drawing, Reader/Punch Control, E-CS-MS40-0-1.

SECTION 2 INSTALLATION
The PCS-E Reader/Punch and Control is installed on site by JEC Field Service personnel. The customer should
not attempt to unpack, inspect, install, checkout, or service the equipment.

Insert the PCS-E Control Module in the PDP-S/E OMNIBUS. Refer to Table 2-3, Volume 1, for information
concerning recommended module priorities (the PCS-E is a "non-memory" option).
Connect the control to the reader/punch with the two signal cables provided. J1 of the control, a 40-pin Berg
Connector, connects to reader/punch module slot B 1, a DEC M955 Connector. J2 of the control connects to
module slot A 1 (refer to Section 5 for cable and connector pin assignments).
Refer to Chapter 2 of the PC04 High-Speed Perforated Paper- Tape Reader/Punch Maintenance Manual
(DEC-OO-HGPA-D) for additional information concerning system installation and for procedures to be followed
to checkout both the control and the reader/punch.

2-1

SECTION 3 DESCRIPTION
Figure 2-1 is a block diagram of the PC8-E Control. The functions of the control can be grouped conveniently
according to reader functions and punch functions, as illustrated by the block diagram. Consider the reader
functions, represented by the logic blocks above the broken line.
The control logic generates signals that control the PC04 tape-feed operation. As the paper tape passes over the
PC04 photoarray, signals representing the punched characters are strobed into the Control Buffer Register. The
buffered information is then transferred to the PDP-8/E AC Register and operated on by subsequent program
instructions.
The tape-feed operation can be initiated under program control or by activation of the Reader FEED switch on
the PC04 front panel. If the switch is used, the tape feeds through the read station but data is not transferred
from the Control Buffer Register. If data is to be transferred, the tape-feed operation must be program-initiated.
Two lOT instructions, 6014 (Fetch Reader Character) and 6016 (Read Buffer, Fetch Reader Character), read the
information currently over the photoarray and then initiate tape feed. When either of these instructions is
decoded by the lOT decoder logic, the read tape logic generates an ENAB LE signal that triggers the clock logic.
The first CLOCK PULSE produced enables the read tape logic to generate an RDR DATA STROBE pulse. This
pulse clocks the RDR Buffer Register, loading the register with the information present on the READ HOLE 1-8
lines.
In addition to clocking the RDR Buffer Register, the RDR DATA STROBE signal sets the RDR FLAG flip-flop
in the INT/skip logic and clears the RDR RUN flip-flops in the tape read logic. If the control has been logically
connected to the computer interrupt system by a previous 6010 instruction, or by the INITIALIZE signal, the
OMNIBUS INT RQST L signal is asserted. The computer enters the interrupt servicing routine to determine the
identity of the requesting device. The 6011 instruction in the routine causes the computer to proceed to the
PC8-E subroutine to service the interrupt request (refer to Table 2-1 for lOT instruction descriptions).
After producing the first CLOCK PU LSE, the clock logic generates a SH I FT PU LSE. This causes the motor
control logic to provide stepping signals for the PC04 Reader Motor. The motor shaft turns, feeding the tape
through the read station. After two steps, the next character on the tape appears over the photoarray; the current
read operation is completed. If a new 6014 or 6016 instruction has been issued, another RDR DATA STROBE
is generated and this character is loaded into the RDR Buffer Register. Each RDR DATA STROBE loads a
character into the register. The register data is transferred to the CPU AC Register by the 6012 or 6016 instruction. If a 6014 or 6016 instruction is decoded between each RDR DATA STROBE and the next CLOCK PULSE,
reader operation is continuous, at a rate of 300 characters/second. Otherwise, the character rate is limited to
25 characters/second.
The tape status logic monitors the FEED HOLE signal from the PC04. When the tape-read mechanism is out of
tape, the tape status logic provides a signal that inhibits program generation of the motor stepping signals and
clears the tape read logic.
Now consider the punch functions, represented by the logic blocks below the broken line in Figure 2-1. The
punch motor operates continuously when power is applied to the PC04. The punch mechanism (Roytron Model
500) provides a PUNCH SYNC signal at the beginning of each punch mechanical cycle. This signal synchronizes
the control timing and the rotating motor shaft. If a 6024 or 6026 instruction is decoded, the ENAB LE PUNCH
BUFFER L signal is generated by the lOT decoder logic. Whatever information is on the DATA 4-11 lines can
now be clocked into the Punch Buffer Register. At TP3 time of the instruction the PUNCH STROBE signal
clocks the register, transferring the character signals from the DATA 4-11 lines to the HOLE 1-8 lines.

2-2

OMNIBUS
SIGNALS
DATA 4-11 L

Cl L

I
I
I

I
I

6012,6016

INTERNAL I/O L

DATA 4-11 L

6014,6016

RDR
IOT's

TAPE
READ
LOGIC

:::j

MOTOR
CONTROL
LOGIC

-l

CLOCK
LOGIC

t
SH I FT PULSE

[

!
r

6010,6011,6012,
6014,6016,6020

TAPE
STATUS
LOGIC

I CLOCK PULSE

I
I

INT/SKIP
LOGIC

IOT
DECODER - - LOGIC

Te--

RDR MOTOR
STEPPING SIGNALS

I
I
I

RDR FEED SW.
FEED HOLE

RDR OFF/ON LINE SW

RDR FUNCTIONS ~

---------

ENABLE PUNCH BUFFER

6024, 6026

READ HOLE 1-8

I
I

--l--- --L-.
I

INT RQST L

I
I

I
I
SKIP L

I
I
MD3-11 L

-l
ENABLE

I/O PAUSE L

I
i

RDR
DATA
STROBE

I
I
I

INT RQST L

RDR
BUFFER
LOGIC

SYNC SIGNAL

SKIP L

PC04 SIGNALS

CONTROL

PUNCH FUNCTIONS

I
PUNCH

BUFFER
LOGIC

CLR PUNCH BUFFER

PU!CH

'--to

STi BE

6024,6026

PUNCH
IOT's

I
6010,6021,6022,6026

TAPE
PUNCH
LOGIC

J INT/SKIP

·1

LOGIC

1.---1

iI
I

Figure 2-1 PC8-E Control, Block Diagram

PUNCH FEED SW

PUNCH SYNC
PUNCH DONE

HOLE 1-8

SE-024'

Table 2-1
PC8-E lOT Instructions
Octal Code

Function

Mnemonic

6010

RPE

Set the I NT E NA fl ip-flop. The PC8-E is logically connected to the computer interrupt system.

6011

RSF

Skipon Reader flag. Senses the state of the RDR FLAG
flip-flop. If the flip-flop is set, the program counter is incremented so that the next sequential instruction is skipped.

6012

RRB

Read the RDR Buffer Register. Causes the RDR Buffer
Register to be ORed into the AC Register, clears the RDR
FLAG flip-flop.

6014

RFC

Fetch a character from the tape. Clears the RDR FLAG
flip-flop, loads a character into the RDR Buffer Register
from the tape, sets the R D R F LAG flip-flop when the
RDR Buffer Register is loaded.

6016

RRB, RFC

Microprogram of 6012 and 6014. RDR Buffer Register
contents are ORed into AC Register, RDR F LAG flip-flop
is cleared, character is loaded into Register, and RDR
F LAG flip-flop is set.

6020

PCE

Clear the I NT ENA flip-flop. The PC8-E is disconnected
from the computer interrupt system.

6021

PSF

Skip on Punch flag. Senses the state of the PUNCH FLAG
flip-flop. If the flip-flop is set, the program counter is
incremented so that the next sequential instruction is
skipped.

6022

PCF

Clear the Flag. Clears the PUNCH FLAG flip-flop.

6024

PPC

Load Punch Buffer Register, punch character. Transfers
the AC4-11 contents to the Punch Buffer Register,
punches the character, sets the PUNCH FLAG flip-flop
when done.

6026

PLS

Microprogram of 6022 and 6024. Clears the PUNCH
F LAG flip-flop, transfers AC4-11 contents to the Punch
Buffer Register, punches the character, sets the PUNCH
FLAG flip-flop when done.

At the same TP3 time, the tape punch logic is prepared for the punch cycle. When the PUNCH SYNC signal is
generated at the start of the punch cycle, the tape punch logic asserts the PUNCH DON E signal. This signal
lasts for 10 ms, during which time the punch solenoid drivers are activated and the character is punched onto the
tape. At the end of the PUNCH DONE signal, the PUNCH FLAG flip-flop is set. If the punch logic has previously been logically connected to the computer interrupt system, the PUNCH FLAG flip-flop asserts the
OMNI BUS I NT ROST L signal. The computer enters the interrupt servicing routine to determine the identity of
the device. The 6021 instruction in the routine causes the computer to proceed to the PC8-E subroutine to
service the interrupt request.

2-4

SECTION 4 DETAILED LOGIC
2.1

lOT DECODER LOGIC

Figure 2-2 shows the lOT decoder logic. Table 2-1 lists the PC8-E lOT instructions and a description of each.
Bits MD3-8 and I/O PAUSE L are gated to produce signals 601 X and 602X representing reader and punch lOTs,
respectively. Both signals cause the OMNIBUS INTERNAL I/O signal to be asserted, thereby ensuring that the
positive I/O bus interface ignores the lOT instruction.
The 601 X signal and bits MD9-11 are applied to the BCD-to-Decimal Decoder, E31 (refer to Appendix A,
Volume 1, for details); the decoder provides the reader lOT signals, as illustrated. The 602X signal and bits
MD9-11 are applied to decoder E27, which provides punch lOT signals; in addition, the 602X signal causes the
ENABLE PUNCH BUFFER L signal to be asserted each time a punch lOT is generated.
2.2 TAPE READ LOGIC
The tape read logic is shown in Figure 2-3. This logic generates control basic timing signals in response to an lOT
instruction or a signal from the PC04 FEED switch. Assume that the PC04 Reader motor is stopped (either the
reader is between blocks of characters or has just been put on-I ine).
When the tape is stopped, a character is always directly over the PC04 photoarray. (Refer to Paragraph 4.1 of
the PC04 High-Speed Perforated Paper- Tape Reader/Punch Maintenance Manual for a detailed description of the
tape-feed operation.) When an lOT instruction (6014, for example) is decoded, the control logic first causes the
character to be loaded into the RDR Buffer Register by the RDR DATA STROBE signal. It then generates
stepping signals that cause the PC04 Reader Motor to turn.
Refer to Figure 2-3. The 6014 L signal sets the RDR RUN flip-flop. Both the CLOCK PULSE L signal and the
RDR MOTOR STOPPING L signal are negated at this time; thus, the RDR ENA flip-flop is set via NAND gate
E5 (the clock logic is disabled until the ENABLE signal turns it on; the RDR MOTOR STOPPING L signal applies
only when the stepping signals are removed). The ENAB LE signal generated by the O-output of the RDR ENA
flip-flop initiates both the clock logic and the reader motor control logic. The clock logic first produces a single
CLOCK PULSE that is applied to NAND gate E32 and to the C-input of the RDR ENA flip-flop. Because the
flip-flop D-input is high at this time, the flip-flop remains set. The NAND gate must be enabled if an RDR DATA
STROBE signal is to be generated. The second high input to this NAND gate is produced by either the (AoB) L
signal or the (AoB) L signal (one of these. two sync signals, generated by the reader motor control logic, is high
when the paper-tape holes are directly over the PC04; assume, for this discussion, that (A-B) L is asserted). The
negative pulse from E32 sets the R/S flip-flop. The FEED HOLE signal, produced by the PC04 photoarray,
enables the 1-output of the R/S flip-flop to activate E23. The negative-going edge of E23's output resets the
R/S flip-flop after a small delay determined by the RC network. Consequently, the RDR DATA STROBE signal
generated by NOR gate E35 is a narrow pulse (approximately 100-ns wide) and occurs only when the tape-feed
hole is over the photoarray. The RDR DATA STROBE signal resets the RDR RUN flip-flop.
After the RDR DATA STROBE signal is generated, the clock logic produces a SHIFT PULSE that causes the
reader motor control logic to generate a stepping signal. The tape holes move from over the photoarray; the
FEED HOLE signal and the (AoB) L signal are negated. The D-input of the RDR ENA flip-flop is now low. If
a 6014 L is not provided before the clock logic generates another CLOCK PULSE, the RDR ENA flip-flop is
cleared, initiating a controlled motor-stopping operation. The clock logic is disabled and the reader motor
control logic generates a final stepping signal. The reader motor stops and the tape halts with the holes directly
over the photoarray. The FEED HOLE signal is again asserted and now the (AoS) L signal is high. The RDR
RUN flip-flop can be set by an lOT instruction any time after the RDR ENA flip-flop is cleared. However, tt)e
RDR ENA flip-flop can be set again only after a 40-ms delay (the reader motor control logic asserts RDR
MOTOR STOPPING L for 40 ms after the RDR ENA flip-flop is cleared).
2-5

~----~~--------------------------INTERNAL 1/0 L

601X
lIO PAUSE L - - - d - -.....

6010(RPE) L
6011 (RSF) L
E31
ROR

6012(RRB) L
6014 (RFC) L

M03 L

DEC
8251

----t-(lL_/

M04 L---1~~.

6016 (RRB, RFC) L

M09 L

__~

M05 L --+-CL_~

M06 L --+-<L_~

M 07 L .....--+--C~

6020(PCE)L

.J'

6021 (PSF) L
E27
PUNCH

6022(PCF) L
6024(PPC) L

M08 L

-+--1. . . . .~_.../

DEC
8251

6026 (PLS) L

602X
ENABLE
PUNCH BUFFER L

8E-0242

Figure 2-2 lOT Decoder Logic

.-------,1--_ ~~~P~IONTGO~
(A· B) L

.....--r--...J-- (A. B) L

RDR FEED SW

L-~-----~~

CLOCK PULSE L
CLOCK PULSE

READER MOTOR
STOPPING L
CLOCK PULSE L

(A·B)L --+----~~-~

CLOC K PULSE

(Ii· B) L -+-----+-f--._.a

6014L
6016L

+5V

RDR DATA
STROBE

BE -02.43

Figure 2-3 Tape Read Logic

If the RDR RUN flip-flop had been set by an lOT instruction before the second CLOCK PULSE occurred, the
RDR ENA flip-flop would remain set. The second CLOCK PULSE would then be followed by the second SHIFT
PULSE. At this SHI FT PULSE time the (AoS) L and the FEED HOLE signals are asserted. The third CLOCK
PULSE causes RDR DATA STROBE to be generated and the RDR RUN flip-flop is again cleared. Thus, a 6014
or 6016 instruction must be decoded at least once for every other clock pulse in order to maintain a 300
character/second rate of operation.
Figure 2-4 is a timing diagram that illustrates the tape read logic signals, as well as those of the reader motor
control logic and the clock logic. The first clock period illustrated shows the RDR RUN flip-flop being cleared by
an RDR DATA STROBE. A 6014 lOT is decoded before the next CLOCK PULSE. However, between the third
and fourth CLOCK PU LSES, no lOT is decoded and, therefore, the controlled motor-stopping operation is begun
(this is covered fully in Paragraph 2.4).

----+I

1+1-- - 1 .67ms

CLOCK PULSE

,I'
r'

~ "II
~

ROTATE PULSE

I
\U

SHIFT PULSE l

POWER

n
1

RDR DATA
STROBE

+1
!

(A'BIl

(A'SI l!

i ,: . ]

RDR ENA
ENABLE

Ol)

I
I

ii'

I I i i i ,j, I'!
i

Ii'

'I i II ,'II
I

II'

,!:

'I,'!,
I

',I

I
I

:,1
II i i i

~-t-,

I " I I, I

\ ,;

II i I

[,ii

I! I

I",

'i: I

i'll!

!!!! I

Ii
!

I,!

I I

,11111*

'I'

IT II

-H!~,~

+ - - :.,...-,-,

<--f-H-+-+-+I

iI I i

~1~,I,li,"!

+++-++-tI '

I,:

I I I!
I

'I ' ' [' I :

~W-:!,

I!~,,h,1

I I li,lrrTT
I rt+;l,1"

T T l rTT ,

I,!'

'~i

1 ,l I , : n
:t" ' !I I!,
!I
'I

,i'j'l

1 11+++++++4

14,! :I ::! 111H

r- . I I ' 11
I
I"

1+-+-+-1--4--4-1-1

!i,I"!':I;

RDR RUN (11

I+-+-l~

ill
I

III I

,I III I:

I,i

\ I

40ms----.<·1

I+-- 2.5ms --I

;

lii!:I\,

,I I

~i~11 I:
I I

I '

I'll

; 'I'

'i!
I

I : ! ~I

iii

---4I-r-!H

! \-'

1_1',111:
8£- 0244

NOTE,
All times are approximate

Figure 2-4 Reader Timing

2-8

2.3 CLOCK LOGIC
The clock logic is shown in Figure 2-5. The logic consists of a ramp generator, a triggered free-running multivibrator, and two pulse-forming delay networks.
During continuous operation, the reader motor is stepped once every 1.67 ms. However, when the motor must be
started from a dead stop, the inertia of the motor and the tape drive wheel must be overcome. Initially, the shaft
turns more slowly, and, consequently, the tape moves over the photoarray mor~ slowly than at continuous
operating speed. With each step of the motor the speed of the tape approaches continuous operating speed. In
order to maintain a nearly constant ratio of tape speed to CLOCK PULSE frequency, the ramp generator, which
includes transistors 01 and 02, is used.
When the ENABLE signal is asserted by the tape read logic, the free-running multivibrator, 04/05, is triggered on
via 03. At the same time, the ramp generator is triggered. The emitter of 02 provides the charging potential for
the multivibrator. This potential is initially such that the first CLOCK PULSE period is 5 ms. The emitter
potential of 02 rises at a rate determined by the RC time constant, which can be varied by R27 (refer to
Paragraph 5.3.8 of the PC04 High-Speed Perforated Paper-Tape Reader/Punch Maintenance Manual for adjustment procedures). As the potential rises, the capacitors in the base circuits of 04 and 05 take less time to charge.
Thus, the on/off cycle of 04 and 05 decreases. Ultimately, when the ramp has ended, the CLOCK PULSE period
is 1.67 ms.
The method used to generate the SH 1FT PU LSE L signal and the CLOCK PU LSE signal is illustrated in Figure
2-6. The RC delay circuits are used extensively in the control logic. Because the circuit in Figure 2-5 is more
detailed than others, it has been selected as an example of the technique. The timing diagram is mainly selfexplanatory. The RC delays indicated can be roughly calculated by using the formula Delay = 0.7 RC.
2.4 READER MOTOR CONTROL LOGIC
The reader motor control logic is shown in Figure 2-7. (Refer to Paragraph 4.1.1 ofthe PC04 High-Speed
Perforated Paper- Tape Reader/Punch Maintenance Manual for a detailed description of how the reader motor

control logic stepping signals control the reader motor.) When the ENABLE signal is asserted by the tape read
logic, the two one-shot multivibrators, E4 and E7, are readied for triggering. During continuous operation, the
clock logic generates SH 1FT PU LSEs, the first of which sets the PWR flip-flop, thereby asserting the POWE R
signal. Each SHI FT PULSE L signal generates a ROTATE PULSE that clocks the AlB end-around shift register.
At every other ROTATE PULSE either the (A· B) L signal or the (A ·S) L signal is asserted, indicating to the tape
read logic that a character is over the photoarray.
If, as explained in Paragraph 2.2, the RDR ENA flip-flop is cleared, the ENABLE signal is negated (provided the
reader FEED switch is not activated). The down-going edge of the ENABLE signal triggers E4 and E7 (Figure
2-4). After 2.6 ms, E4 times out and a CATCH PULSE L signal is generated. This pulse produces the ROTATE
PULSE that steps the motor a final time. The motor stops with either (A·B) Lor (A·S) L asserted and the
FEED HOLE signal high.
The E7 one-shot remains set for 40 ms before timing out. During this 40-ms period, the R D R MOTO R
STOPPING L signal is asserted and prevents the RDR ENA flip-flop from being set. At the end of the period,
the O-output of E7 clears the PWR flip-flop, negating the POWER signal. Reader operation can be restarted by
again setting the RDR ENA flip-flop.
The 40-ms delay provided by E7 ensures that the motor, if not pulsed for continuous operation, has sufficient
time to come to a complete stop before it is activated again. If the complete stop were not allowed, undesirable
oscillations in the drive motor would result, causing possible false data outputs.

2-9

MULTI OUT

SHIFT PULSE L
(150n5)

rvv.......---!4

":-l
.....

ENABLE--~~-'--~

+5V

__________________ CLOCK PULSE
(150n5)

L _______________________ CLOCK PULSE L

~---Jk---------~~----~-----------4----~----15V
R27

Figure 2-5 Clock Logic

(150n5)

BE-0245

1+4----------1.67 MS -----------+l~1
MULTI OUT

~~______________~

I
E5, PIN I . - J

I
I

E5, PIN 2

1 1--------------1

1,...1-----1 I

CLOCK PULSE L

--U--------T

r-------~Ur------I

El B, PIN 11

i'--.

- -.....
I---J~

EIA, PIN 5 1
I

I
1

150ns-V-

I
1

1--"2I'S--1

CLOCK PULSE

-=:It:

I I

U-

~----__--~h~------__

150n$

~-------~I

-H--"1

~
1

1
I

SHIFT PULSE L

EIA, PIN 4

i'----L
1---------11
I

I
I

8E-0246

Figure 2-6 Clock/Shift Pulse Timing

2.5 RDR INT/SKIP LOGIC
The RDR I NT/skip logic is shown in Figure 2-8. When an RDR DATA STROBE signal is generated it sets the
RDR FLAG flip-flop (the RDR RUN flip-flop provides the necessary high at E12's D-input before being cleared,
itself, by RDR DATA STROBE). Because RDR DATA STROBE also loads the RDR Buffer Register, the RDR
FLAG flip-flop being set indicates that the control is ready to transfer data. If the INT ENA flip-flop has been
set previously, either under program control or by INITIALIZE, the OMNIBUS INT RQST L signal is asserted.
When the computer enters the PC8-E servicing subroutine, an appropriate lOT instruction reads the Buffer
Register and clears the RDR FLAG flip-flop via NOR gate E1.

2.6 RDR BUFFER LOGIC
The reader buffer logic is shown in Figure 2-9. Data supplied on the READ HOLE 1-8 lines is clocked into the
register by the RDR DATA STROBE signal. Either 6012 Lor 6016 L gates the character onto the OMNIBUS
DATA 4-11 lines. At the same time, the lOT instruction asserts the OMNIBUS C1 L signal, resulting in an
ORing of the DATA 4-11 bits and the CPU AC Register contents.

2.7 TAPE STATUS LOGIC
The tape status logic is shown in Figure 2-10. The logic monitors both the FEED HOLE signal and the RDR ENA
flip-flop, generating an OUT OF TAPE signal when tape is not loaded in the PC04 Tape Feeder. This signal
ensures that the tape read logic cannot be triggered by a program instruction read command. The complementary
signal, HAVE TAPE, is generated when tape is in the feeder, enabling the tape-feed operation to begin when
progra m-d i rected.
2-11

(A·B) l

(A·B)l

+5V
BA(1)l

BA(O)l

BB (1) l

r:->
......

+5V

CATCH
PULSE
ONE-SHOT

BB(O)l

POWER

+5V
ENABLE

RDR MOTOR
STOPPING
ONE-SHOT
SHIFT
PULSE l

Figure 2-7 Reader Motor Control Logic

8E-0241

INT

RQST L

TP3
~----------BTP3

6010 L
6020 L ----------------a
+5V

IN ITIALI ZE

SKIP L

....r:->
W

6011 L

CLOCK PULSE
OUT OF TAPE
6012

L---------~O

6016

L--------.-~a

BTP3

6014 L ----------------0

HAVE T A P E - - - - - - - - - - - - - - - - - - - - - - '

8E-0248

Figure 2-8 RDR INT/Skip Logic

elL

DATA 4 L

DATA 5 L

DATA 6 L

DATA 7 L

DATA 8 L

DATA 9 L

DATA 10 L

DATA 11 L

6012 L
6016 L

RDR DATA----4--------r--~~____~----~------_r--~~------r_--~------_r----~------t_---4~----_t----~
STROBE
READ
HOLE 8

READ
HOLE 7

READ
HOLE 6

READ
HOLE 5

READ
HOLE 4

READ
HOLE 3

READ
HOLE 2

READ
HOLE 1
SE - 0249

Figure 2-9 Reader Buffer Logic

+5V

HAVE
TAPE

>--_--------- 0TAPE
UT 0 F
FEED~~~~v-~

HOLE

RDR

OFF--------------------------------------------------------------------~

8E-02!50

LINE L

Figure 2-10 Tape Status Logic

If no tape has been inserted in the feeder, the FEED HOLE signal is high, just as it is when an actual feed hole is
detected by the photoarray. The RDR FEED HOLES one-shot, E19, is in its stable state; thus, the OUT OF
TAPE signal is asserted. If a read command is issued by the program, the RDR RUN flip-flop (Figure 2-3) is prevented from being set by the HAVE TAPE signal that is low atthistime. Therefore, the RDR ENA flip-flop is
not set and the clock logic is not triggered.
When a tape is inserted in the feeder, the photoarray light source rays are interrupted briefly by the tape web.
The FEED HOLE signal goes low, and the negative-going edge causes one-shot E19 to be triggered; thus, the
HAVE TAPE signal is asserted. At the same time that E19 is triggered, the flip-flop consisting of the cross-coupled
NOR gates is cleared. Because the RDR ENA flip-flop is also clear, flip-flop E23 is latched in the clear state.
NAND gate E17 is enabled; the resulting low at pin 11 of E19 holds the one-shot in the triggered state, i.e., the
1-output stays high. The HAVE TAPE signal remains high indefinitely, if the program does not issue a read
command.
When a read command is issued, the RDR RUN flip-flop is set, causing the RDR ENA flip-flop to be set, also.
The O-output of the RDR ENA flip-flop triggers the clock logic, which generates a CLOCK PULSE, and sets
flip-flop E23, which disables NAND gate E17. The one-shot enters the timeout state, during which it can be retriggered by each trailing edge of the FEED HOLE signal. A ROTATE PULSE, generated by the clock logic
approximately 2 /.lS after the CLOCK PULSE (Figure 2-4), causes the tape to begin feeding through the read
station. The resulting negative transition of the FEED HOLE signal re-triggers the one-shot (note that flip-flop
E23 is held in the set state by the O-outputof the RDR ENA flip-flop). If another trailing edge occurs within
10 ms, the one-shot is again re-triggered (a 10-ms period is necessary because the reader motor is being started
from a dead stop and, consequently, the tape moves more slowly than at continuous operating speed; in continuous operation, a trailing edge occurs at 3.34-ms intervals). If the program issues read commands at such a rate
that continuous operation results (at least one command between each RDR DATA STROBE and the next
CLOCK PU LSE), one-shot E19 is re-triggered continuously, and the HAVE TAPE signal remains asserted.
Suppose that at some point during this continuous operation a read command is not issued within approximately
3.34 ms of the preceding command. In such a situation, the motor-stopping operation is initiated. At the
moment this operation begins, the RDR ENA flip-flop is cleared, and the FEED HOLE signal is low. Therefore,
flip-flop E23 is again latched in the clear state, and one-shot E 19 is held in its triggered state. The HAVE TAPE
signal remains high while the motor is stopped.
If r~ad commands are issued at a continuous rate and the tape runs out of the tape feeder, the OUT OF TAPE
signal must be asserted. When the last portion of tape web uncovers the light source, the FEED HOLE signal
goes high and remains high. One-shot E19 times out approximately 8.5-ms later, and the OUT OF TAPE signal
goes high. During this 8.5-ms period, three RDR DATA STROBE pulses occur. Each of these pulses loads the
Reader Buffer with 1s. Consequently, at least two transfers, possibly three, of 1s to the AC Register take place
before the RDR RUN flip-flop is cleared and the clock logic is disabled.
2.8 TAPE PUNCH LOGIC
When the punch ON/OFF switch is in the ON position, the punch motor runs continuously. A tape that is loaded
in the punch feeder mechanism can be punched if the FEED switch is in the FEED position, or if the program
issues a punch command lOT instruction, 6024 or 6026. Either method results in the PUNCH DONE signal
being generated in the tape punch logic (Figure 2-11).

2-16

+5V

PUNCH
DONE

+5V

+5V--~~--------------~

+5V
INITIALIZE

r-----------------t----------------t-----------BTP3
£r---+-----------------+-----------6024 L
tr--~----------------+-----------6026 L

CO I L B I AS ---JWv---..-----~>--___,

PUNCH SyNC---JW-.---......--H

8E-0251

Figure 2-11 Tape Punch Logic

When the 6026 lOT instruction is issued, for example, the PUNCH RUN flip-flop, E10, is set. Setting E10 causes
the D-input of the SYNC PUNCH REQ flip-flop, E14, to go low. A PUNCH SYNC signal from the tape punch
mechanism can clear E14, thereby triggering the PUNCH BUSY one-shot, E 15. This PUNCH SYNC signal occurs
once during each punch motor revolution and signals the start of the punch mechanical cycle. The signal is
applied to the Schmitt trigger, Q9 and Q 10, and the output at the collector of Q 10 clears E 14. The resulting
10-ms PUNCH DONE signal enables the PC04 solenoid drivers to activate the punch mechanism. The tape is
punched with the character that was placed on the HOLE 1-8 lines by the punch buffer logic, shown in Figure
2-12 and discussed briefly in Paragraph 2.9.
2.9 PUNCH BUFFER LOGIC
The punch buffer logic is shown in Figure 2-12. Either the 6024 L signal or the 6026 L signal enables the Buffer
Register to be loaded at TP3 time with the information carried on the DATA 4-11 lines. This information is
then gated to the HOLE 1-8 lines, respectively. Note that the information loaded at this time remains in the
register until another punch instruction is issued or until the FEED switch is activated.
2.10 INT/SKIP LOGIC
After the tape has been punched and the punch mechanical cycle ends, the PUNCH BUSY one-shot times out. The
PUNCH RUN flip-flop is cleared and the O-output of the flip-flop sets the PUNCH FLAG flip-flop (Figure 2-13).
If the I NT ENA flip-flop, E14, is set at this time, the OMNI BUS I NT RQST L signal is asserted. The computer
enters the interrupt routine and proceeds from there to the punch subroutine.

SECTION 5 MAINTENANCE
Refer to Volume 1 and the PC04Hiuh-Speed Perforated Paper-Tape Reader/Punch Maintenance Manual for
PC8-E maintenance information.
Table 2-2 presents cable and connector pin assignments for the two cables that connect the control and the PC04.

SECTION 6 SPARE PARTS
Table 2-3 lists recommended spare parts for the PC8-E. These parts can be obtained from any local DEC office
or from DEC, Maynard, Massachusetts.

2-18

HOLE 8

HOLE 7

HOLE 6

HOLE 5

HOLE 4

HOLE 3

HOLE 2

HOLE 1

PUNCH FEED
SWITCH L
--------+-------,

6024
6026

DATA 4L

DATA 5L

DATA 6L

DATA 7L

DATA 8L

DATA 9L

DATA lOL

DATA llL

8E-0253

Figure 2-12 Punch Buffer Logic

6021

L----------------------------------------------------~n

0-------- SKI P L

6022 L
6026 L

+5V

0---------- INT RQST L

BTP3
TP3

~-------BTP3

6010 L

6020 L -----------~d

+5V

INITIALIZE

BE-0252

Figure 2-13 Punch I NT/Skip Logic

Table 2-2
Cable/Connector Pin Assignments
Control Connector

Signal Name

M955 Connector

J1 (Connects to 81)

J2 (Connects to A 1)

0
F
J
L
N
R
T
V

PUNCH FEED SWITCH
SCR ACTIVE
PUNCH SYNC
N/C
PUNCH DONE
PUNCH NOT UP TO SPEED
HOLE 8
HOLE 7
HOLE 6
HOLE 5
COIL BIAS
HOLE 4
HOLE 3
HOLE 2
HOLE 1
N/C
N/C
N/C

N/C
RDR ON/OFF LINE
GND
READ HOLE 1
READ HOLE 2
READ HOLE 3
READ HOLE 4
READ HOLE 5
READ HOLE 6
READ HOLE 7
READ HOLE 8
FEED HOLE
BA (0)
BA(1)
BB (0)
BB (1)
POWER
RDR FEED SWITCH

A
B
C
0
E
F
H
J
K
L
M
M
P
R
S
T
U
V

X
Z
BB
DO
FF

JJ
LL
NN
RR
TT
GND PINS
A,B,C,E,H,K,M,P,S,
U,W, Y,AA,CC,EE,HH,
KK, MM, PP, SS, UU, VV

Table 2-3
PC8-E Recommended Spare Parts
DEC Part Number

Description

19-05547
19-05575
19-05576
19-09486
19-09487
19-09686
19-09971
19-09972
19-09973
19-09594
19-05579
19-10087
15-03409
15-09338
11-00113
11-00114
10-01610

IC DEC 7474
IC DEC 7400
IC DEC 7410
IC DEC 384
IC DEC 9601
IC DEC 7404
IC DEC 6380
IC DEC 6314
IC DEC 97401
IC DEC 8251
IC DEC 7440
IC DEC MC4015P
Transistor, 6543 0
Transistor, PMS 6531
Diode, 0662
Diode, 0664
Capacitor, 0.01 pF, 100V, 20%

2-21

Quantity

1
2

2
2

PART 3
X/V

PLOTTER

CHAPTER 3
XV8-E PLOTTER CONTROL

SECTION 1 INTRODUCTION
The XY8-E Plotter Control interfaces a digital incremental plotter with the PDP-8/E. The XY8-E operates with a
variety of plotters, both encoded and unencoded types, to display data on paper or film. All XY8-E logic is contained on a single quad module that plugs into the OMNIBUS. The XY8-E connects to the incremental plotter
with a signal cable that is supplied.
The XY8-E transmits directions to the plotter that originate in the computer AC Register. Data is transferred in
six parallel bits that cause pen or drum movement (the plotter can be either a drum or flatbed type) in the plotter.
All plotter operations, except the setting of the coordinates at which plotting begins, are guided by the XY8-E
logic and the CPU. A series of functions, specified by lOT instructions, initialize the XY8-E logic, initiate plotter
operation, and generate program interrupts to indicate completion of the operation.
The XYB-E will interface readily with any of the following incremental plotters:

a.
b.

CalComp Plotters - Series 500, 600, 700, and 800.
Houston Instruments Plotters - Types 6400, DP-1, and DP-10.

Four Plotter Control/plotter systems, featuring plotters from those listed, are offered by DEC. Details concerning
installation, operation, troubleshooting, and maintenance of these plotters can be found in the respective CalComp
or Houston Instruments instruction manual. DEC publications and documents relevant to the XY8-E are:
a.
b_

PDP-8IE & PDP-81M Small Computer Handbook - 0 EC, 1972PDP-8IE Maintenance Manual, Volume 1

XY8-E Plotter Control and Display Diagnostic, MAINDEC-BE-D6AB
DEC Engineering Drawing, Plotter Control, E-CS-MB42-0-1.

SECTION 2 INSTALLATION
The XY8-E Plotter Control is installed on site by DEC Field Service personnel. Customers should not attempt to
unpack, inspect, install, checkout, or service the equipment.
Insert the XY8-E Control Module in the PDP-8/E OMNIBUS. Refer to Table 2-3, Volume 1, for information concerning recommended module priorities (the XYB-E is a "non-memory" option)_
Connect the Plotter Control to the plotter with the signal cable provided (if the plotter is one of those listed in
Section 1). If the plotter is an unencoded type, J2 of the Plotter Control, a 40-pin Berg Connector, connects to
the plotter 19-pin Cannon Plug; if the plotter is an encoded type, J1 of the Plotter Control connects to the plotter
Cannon Plug (refer to Section 5 for cable and connector pin assignments)_

3-1

The XY8-E can be checked for correct operation by running the diagnostic program, MAl NDEC-8E-D6AB_
Refer to the plotter instruction manual for checkout procedures for the plotter itself.

SECTION 3 BLOCK DIAGRAM
Figure 3-1 is a block diagram of the XY8-E Plotter Control. Programmed lOT instructions are decoded by the
lOT decoder logic. Signals representing the lOT instructions are then applied to the timing logic, the interrupt!
skip logic, and the direction transfer logic.

OMNIBUS
SIGNALS
IN ITf ALiZE . . . . - - - - - - - - - . . . . - - - - - - - - - - - - - - ,
SKIP L .....- - - - - - - - - + - - - - - - - - - - - - ,
INT RQST L

_--------+---------,

I
I
I

I
INTERNAL 1/0 L _ - - - - - - - - - ,
110 PAUSE L L - - _ . r - - - - - - - ,

6500L
6501L
6502L
6506L
6507L

....----------+10
SET
FLAG L

DIRECTION REGISTER
OUTPUT r---+IIDni

MO 3-11 L
6503L
6504L
6505L

F
J
L
N
R

~~~E~~ r---~--'

F
J
L
N
R
JI
(ENCODED PLOTTER
OUTPUT)

(UNENCODED PLOTTER
OUTPUT)

I-C-L--:R-R=-E=-G'"'"I-ST=-E=-'R L
DATA 6-11

L~------------~---------~

BE-0256

Figure 3-1 XY8-E Block Diagram

Plotter directions are gated from the AC Register via the DATA 6-11 lines to a 6-bit Decision Register in the
direction transfer logic. The Direction Register outputs are transferred to the plotter, which begins the directed
operation. At the same time, the timing logic is triggered; after a delay period the timing logic generates a signal,
CLR REGISTER L, that clears the Direction Register, readying it for the next direction_ After a further delay
period that ensures completion of the direction by the plotter, the timing logic generates the SET FLAG L
signal. This signal is applied to the interrupt!skip logic where it sets the PLOTTER FLAG flip-flop. This action
causes the Plotter Control to request a program interrupt, resulting in the transfer of another direction from the
AC Register.

3-2

SECTION 4 DETAILED LOGIC
3.1

lOT DECODER LOGIC

The lOT decoder logic is shown in Figure 3-2. The I/O PAUSE L signal gates bits MD3-8 to generate the
SE LECT signal that indicates an XY8-E instruction has been decoded. See Table 3-1 for the XY8-E instruction
list and a description of each instruction.
Table 3-1
XY8-E lOT Instruction List
Function

Octal Code

Mnemonic

6500·

PLCE

Clear the INT ENA flip-flop.

6501

PLSF

Skip on the Plotter flag. Senses the state of the PLOTTER
FLAG flip-flop. If the flip-flop is set, the program counter
is incremented so that the next sequential instruction is
skipped.

6502

PLCF

Clear the PLOTTER FLAG flip-flop.

6503

PLPU

Pen up. Raises the plotter pen from the surface of the graph
paper (unencoded plotters only).

6504

PLLR

Load Direction Register, clear Direction Register, set Plotter
flag. Loads the Direction Register from AC06-11 (see Table
3-2 for the list of directions), clears the register after the
plotter has had enough time to carry out the direction, sets
the PLOTTER FLAG flip-flop.

6505

PLPD

Pen down. Lowers the pen to the surface of the graph paper
(unencoded plotters only).

6506

PLCF,
PLLR

Microprogram of 6502 and 6504. Clears the PLOTTER
F LAG flip-flop, loads the Direction Register, clears the
Direction Register, sets the PLOTTER FLAG flip-flop.

6507

PLSE

Set the INT ENA flip-flop.

The SELECT signal asserts the OMNIBUS INTERNAL I/O L signal that directs the positive I/O bus interface to
ignore the lOT instruction; also, it gates bits MD9-11 to provide inputs for E21, the BCD-to-decimal decoder
(see Appendix A, Volume 1, for details). With one exception, E21 provides the signals that represent the XY8-E
lOT commands. The exception is the signal that represents the 6501 instruction, Skip on the Plotter Flag. Note
that the lOT signals generated by E21 are produced at TP3 time. However, the OMNIBUS SKIP L signal is
sampled at TP3 time by the CPU skip logic. Therefore, the XY8-E Plotter Control must assert the SKIP L signal
before TP3 time; this is the reason for generating the 6501 L signal separately_

3-3

INTERNAL

1/0 L

lIO PAUSE L

6501 L
MD3 L
SELECT
MD4 L
MD5 L
E21
6500 L

MD6 L

6502 L
6503 L
MD7 L

6504 L
6505 L
6506 L

MD8 L

DEC
8251

6507 L

8E-0251

Figure 3-2 lOT Decoder Logic

3.2 TIMING LOGIC
The timing logic is shown in Figure 3-3. This logic generates delay periods that allow the plotter to carry out the
direction contained in the Direction Register. The delay periods are initiated simultaneously with the loading of
the Direction Register. When the first delay ends, the Direction Register is cleared; when the second delay ends,
the PLOTTER FLAG flip-flop is set. Then, if the XY8-E is logically connected to the computer interrupt system,
a program interrupt is requested and another direction is transferred from the AC Register to the Direction
Register.
Three one-shot multivibrators are shown in Figure 3-3. For directions other than Pen Up/Pen Down, only oneshots E1 and E7 are triggered. Either the 6504 L or the 6506 L signal, in addition to clocking the Direction
Register, triggers both E1 and E7. The plotter begins the directed operation and the direction remains in the
Direction Register for 3.3 ms (an arbitrary but optimal period of time). At this time, E1 times out and the CLR
REGISTER L signal is asserted. This signal is applied to the direction transfer logic and clears the Direction
Register. E7 times out after 7.5 ms (more than enough time for the plotter to carry out the mechanical operation), causing the SET FLAG L signal to be asserted. This signal is applied to the interrupt/skip logic, Figure 3-6,
where it sets the PLOTTER FLAG flip-flop.
If the direction to be carried out by the plotter is either Pen Up or Pen Down, the third one-shot, E4, is triggered.
This situation is illustrated by the timing diagram, Figure 3-4. The timing shown applies to an encoded plotter.
However, an unencoded plotter could be represented by replacing the 6504 Li6506 L signal with either 6503 L
or 6505 L. If the Pen Up direction is to be carried out by an encoded plotter, for example, AC Register bits 6-11
must be loaded with octal code 31 (Table 3-2). This code is placed on the DATA 6-11 lines and loaded into the
Direction Register by the leading edge of the 6504 Li6506 L signal. At the same time, NAND gateE3A, Figure
3-3, is enabled, and both E1 and E7 are triggered. DR11 is set, enabling NOR gate E3B to trigger one-shot E4.
As before, the CLR REGISTER L signal is asserted after 3.3 ms. However, the SET FLAG L signal, rather than
occurring after 7.5 ms, is delayed for 72.7 ms. This period of time is required to satisfy the plotter's pen stabilizing time. Note that one-shot E7 is superfluous in this operation.
If the Pen Up instruction, 6503, is issued for an unencoded plotter, E4 is triggered in essentially the same way as
for the encoded plotter. The 6503 L signal dc-sets DR 11. NOR gate E3 is enabled, triggering E4 which, in turn,
triggers El (E7 is not triggered in this situation). The two delays generated carry out their respective functions as
detailed earlier.
3.3 DIRECTION TRANSFER LOGIC
The direction transfer logic is shown in Figure 3-5. Directions are placed on the DATA 6-11 lines from the AC
Register by lOT instruction 6504 or 6506. At TP3 time, the 6504 L signal or the 6506 L signal loads the
Direction Register. Separate transistor driver outputs are provided for encoded and unencoded plotters; unencoded outputs undergo a transition from -15V to +5V, while encoded outputs go from ground to +15V. The
Direction Register is cleared by the IN ITI ALiZE signal that is asserted both at power turn-on and by the CAF
(6007) instruction.
3.4 INTERRUPT/SKIP LOGIC
The interrupt/skip logic is shown in Figure 3-6. The Plotter Control is logically connected to the computer interrupt system when the I NT ENA flip-flop is set. The flip-flop is set under program control by the 6507 (PLSE)
lOT instruction or by the 6007 (CAF) lOT instruction that asserts the INITIALIZE signal; in addition, the
INITIALIZE signal sets the flip-flop at power turn-on. The XY8-E is disconnected from the interrupt system by
the 6500 (PLCE) lOT instruction that clears the flip-flop under program control.

3-5

+5V
1
E7
7.5MS
DEC
9601
0

SET
FLAG L
+5V

CLR
REGISTER
L
6503 L
6505 L

+5V

6504 L
6506 L

6503 L

SELECT ----..--\

DATA6 L

DATA7 L

DATA8 L

DATA9 L

DATA10 L

DATA11 L
BE-0258

Figure 3-3 Timing Logic

SELECT

I
1

TP3

I
I

6504 L or 6506

1
1

1
AC REGISTE R
TO DATA 6- 11--+1

72.7MS (0)

rn
I
I

1_ LOAD DIRECTION REGISTER
1
1

CLEAR PLOTTER

FLAG

I
I

l
I
I

7.5MS (0)

1
1

3.3 MS (0)

I
I
I
I

CLR

))- i)- -

i
I

I
SET

FLAG

I
BE-0259

Figure 3-4 Function Timing; Pen Up, Pen Down, Start Zip (Encoded Plotter)

Table 3-2
List of Plotter Directions
AC06-11
Octal Code
01
02
04
10
11
12
13
14
15
16
17
20
21-27
30
31
32
33
34
35
36
37
40
41-47
50
51
52
53
54
55
56
57
61-67
70
71
72
73
74
75
76
77

Direction
Encoded Plotter
Paper
Film

Unencoded
Plotter

Pen up
Pen down
Drum up
Drum down

+y
+x+y
+x
+x-y
-y
-x-y
-x
-x+y

Pen left

Pen up
Pen down
Start zip
Block code
Plot code
Start incr
Sync
-

Pen right
-

+y/2
+x/2+y/2
+x/2
+x/2-y/2
-y/2
-x/2-y/2
-x/2
-x/2+y/2
+x+y/2
-x+y/2
+x/2+y
-x/2+y
+x-y/2
-x-y/2
+x/2-y
-x/2-y

3-8

+y
+x+y
+x
+x-y
-y
-x-y
-x
-x+y
-

CRT shift
Beam off
Beam on
-z (+Aux 1)
+z (+Aux 2)
Sync
-

J2-D
(UNENCODED OUTPUT)

J 1-D
(ENCODED OUTPUT)

-15V

+5V

+15V

DR7-DRll
OUTPUTS S I MILAR
TO DR6

6504 L
6506

SELECT

DATA9 L

DATA10

DATAI1 L

+5V--~~--~~~------------------------------------J

INITIALIZE

L - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * _ - C L R REGISTER L
8E· 0260

Figure 3-5 Direction Transfer Logic

6501 L
SKIP L

INT RQST L

6500 L
6506 L
6502 L

6507 L
SET FLAG L
INITIALIZE
BE-0261

Figure 3-6 I NT/Skip Logic

When the INT ENA flip-flop is set, the OMNIBUS INT RQST L signal can be asserted by the PLOTTER FLAG
flip-flop. The PLOTTE R F LAG flip-flop is set by the SET FLAG L signal when a direction has been carried out
by the plotter. The computer identifies the requesting device by entering the interrupt servicing routine. The
6501 (PLSF) lOT instruction in the routine directs the computer to the XY8-E subroutine and another direction
is transferred to the Direction Register. The PLOTTER FLAG flip-flop is cleared under program control by the
6502,6506, and 6007 (via the INITIALIZE signal) lOT instructions, as well as at power turn-on by INITIALIZE.

SECTION 5 MAINTENANCE
The relative simplicity of the XY8-E logic precludes the necessity of a detailed maintenance procedure. Use the
diagnostic program to isolate problems that occur in the XY8-E Plotter System. Standard troubleshooting techniques, using the logic drawings and an oscilloscope, will enable the technician to isolate faulty components.
Table 3-3 shows the connector pin assignments for the Plotter Control/plotter interconnecting cable.

SECTION 6 SPARE PARTS
Table 3-4 lists the recommended spare parts for the XY8-E. These parts can be obtained from any local DEC
office or from DEC, Maynard, Massachusetts.

3-10

Table 3·3
Pin Assignments, Interconnecting Cable
Signal Name
Significant For
Unencoded Plotter Only

From
Cannon 19·Pin
Connector Pin
1
2
3
4
9
10
15
Pins 5-8, 11-14,
16-19 not used

Houston Inst. Plotter

CalComp Plotter

CHART RIGHT (-Xl
CHART LEFT (+Xl
CARRIAGE UP (+Yl
CARRIAGE DOWN (-Yl
PEN UP
PEN DOWN
GND

DRUM UP (-Xl
DRUM DOWN (+Xl
PEN LEFT (+Yl
PEN RIGHT (-Yl
PEN UP
PEN DOWN
GND

To
Berg 40·Pin
Connector Pin
L

J
F
D
R
N
S
Pins T, V, X, Z, BB, DD,
FF, JJ, LL, NN, RR, TT,
not used
Pins A, B, C, E, H, K, M,
P, S, U, W, Y, AA, CC,
EE, HH, KK, MM, PP,
SS, UU, VV are gnd.

Table 3·4
XY8·E Recommended Spare Parts
DEC Part Number

Description

15·03409·1
15·03100
19·09705
19·09704
19·09686
19·09594
19·09373
19·09485
19·05577
19·05576
19·05575
19·05547
13·000391

Transistor DEC 6534B
Transistor DEC 3009B
IC DEC 8881
IC DEC 314
IC DEC 7404
IC DEC 8251
IC DEC 9601
IC DEC 380
IC DEC 7420
IC DEC 7410
IC DEC 7400
IC DEC 7474
Resistor 1.5K, 1/4W, 5%

3·11

Quantity

PART 4
LINE

PRINTER

CHAPTER 4
LE8-E LINE PRINTER

SECTION 1 INTRODUCTION
The LES-E Line Printer Control interfaces an SO- or 132-column line printer to the PDP-S/E. All logic is contained on a single quad module that plugs into the OMNIBUS. The LES-E connects to the line printer via a
signal cable that is supplied with the system.
The LES-E Line Printer is discussed here only to the extent necessary to both fully describe LES-E operation and
present supplementary information concerning installation and checkout. Details concerning the installation,
operation, troubleshooting, and maintenance of the printer itself can be found in Data Products Corporation
Technical Manual DPC-214163A (SO-column printer) or DPC-215656A (132-column printer). Other publications
and documents relevant to the LES-E are:

a.
b.

PDP-8IE & PDP-81M Small Computer Handbook - DEC, 1972
PDP-8IE Maintenance Manual, Volume 1

c.
d.

LES-E Line Printer Diagnostic, MAINDEC-SE-D2BA
DEC Engineering Drawing, Line Printer Control, E-CS-MS41-0-1.

SECTION 2 INSTALLATION
The LES-E Line Printer and Control are installed on site by DEC Field Service personnel. The customer should

not attempt to unpack, inspect, install, checkout, or service the equipment.
4.1

UNPACKING

Place the LES-E Line Printer close to the ac power source and proceed as follows:
Procedure

Step

Cut the two steel straps that secure the telescoping cap and stitched sleeve to
the shipping skid.
2

Remove the Tri-wall clips from all four sides of the stitched sleeve.

Remove the four bolts, washers, and nuts securing the line printer to the
shipping skid, then remove the printer from the skid and install on the site.

(continued on next page)

4-1

Step

Procedure

Unpack the LE8·E Control and the signal cable. Plug the LE8·E into the PDP·8/E
OMNIBUS and connect itto the line printer with the cable (refer to Table 2·3, Volume 1,
for information concerning module installation order). The cable connects to the
control via a Berg Connector and to J1 of the line printer via a Winchester MRAC·50
Connector (refer to Section 1 of the Data Products Corporation technical manual for
the location of J1).

Inspect both printer and control as outlined below and report any damage to the local
DEC sales office.
a.

Inspect external surfaces of the printer and control for surface, bezel,
switch, and light damage.

Open the printer doors and inspect for internal damage.

Inspect the wiring side of the printer logic mounting panels and the control
module for bent pins, cut wire, loose external components, and foreign
matter. Also inspect the signal cable for damage.

Check equipment received against the packing list to be certain that all
equipment has been unpacked.

4.2 CHECKOUT
Use the following procedure to check out the LE8·E Line Printer and Control.
Step

Procedure
Insert the ribbon in the printer, following the ribbon installation procedure detailed in
Section 3 of the Data Products Corporation technical manual (referred to hereafter as
the technical manual).

Load the printer with continuous·form paper, following the paper loading procedure
detaiJed in Section 3 of the technical manual.
NOTE
The READY indicator on the printer control panel
should light 10-15 seconds after the last step of the
procedure (close and latch drum gate, etc.) has been
completed.

See the paper positioning (vertical) procedure in Section 3 of the technical manual.

Check that the TOP OF FORM and PAPER STEP switches operate as in Table 3·1 of
the technical manual.

Set the ON LI NE/OF F LI N E switch to the ON LI N E position and check that the TOP
OF FORM and PAPER STEP switches do not operate.

Hold the MASTER CLEAR switch in the "up" position and check that the READY
and ON LINE indicators go out. Release the switch; the READY indicator should light.

Check the right tractor for correct adjustment and make sure that the COPI ES
CONTROL switch is set to the 1-2 position.

Set the ON LINE/OFF LINE switch to the ON LINE position and run the MAINDEC
diagnostic program, starting at Part 1 of Test 1. While the program is running, adjust
the vertical paper adjustment vernier.
(continued on next page)

4·2

Step

Procedure

Stop the program and set the PRINT INHIBIT switch to the "up" position; set the
ON LI NE/OF F LI NE switch to the ON LI NE position and restart the program from
Part 1 of Test 1. The PRINT INHIBIT indicator should light and the program should
run as in Step B. Run the program for one minute.

Set the PRINT INHIBIT switch to the "down" position and check for printout errors.

Replace the continuous-form paper with single-part paper. Run all parts of the program
(except Part 1 of Test 1) for one hour.

I nspect all printouts for errors and print quality and compare to the enclosed factoryprinted samples.

SECTION 3 BLOCK DIAGRAM DESCRIPTION
Figure 4-1 is a block diagram of the LEB-E Control. OMN I BUS pin numbers and pin assignments for both ends
of the signal cable can be found on engineering drawing E-CS-MB41-0-1. Connector receptacle J 1 on the line
printer is a 20-pin connector with a return pin for each of the 10 signal pins. Figure 4-2 is a timing diagram of
the control; Table 4-1 presents the LEB-E lOT instructions. Refer to the figures vyhile reading this description.

PDP-S/E OMNIBUS

r-- -- -

~8~ ~N~L- -

-----,

LES-E LINE PRINTER

INT RQST L
SKIP L

6661,6662
6663,6666
SKIP
LOGIC

INITIALIZE

~
i

J1
I

(DEMAND)

r--

MD3-11 L
1/0 PAUSE L

SELECT
LOGIC

6662,6665
6666,6667

INTERRUPT
LOGIC

INTERNAL 1/0 L

6664
6666
SELECT L
DATA 5-11 L

(READY)

J (STROBE)
DATA
TRANSFER
LOGIC

TP3

L _________________ .....J

I
I
I
I
I
I

B,F,L, (DATA ,-7)
R,V,Z,n

BE- 0240

Figure 4-1 LEB-E Line Printer Control Block Diagram

When the line printer is ready to be placed on-line, a READY indicator on the line printer lights, At the same
time, the READY signal is asserted. After the line printer has been placed on-line, it asserts the DEMAND signal
when it is able to accept a character. The DEMAND signal sets the FLAG flip-flop in the interrupt logic. If the
INT ENA flip-flop is set, the FLAG flip-flop asserts the OMNIBUS INT RQST L signal. The computer then
begins to execute the interrupt servicing routine to determine the identity of the requesting device.

4-3

I
READY

I
I

I
II

DEMAND

STROBE

1--'

I
i

I-

I
JJS MAX.---j

I I

I ~

i
\\

i
I

I
I

INT RQST L

I
!

6666 L

TP3

i
I

DATA

~mr,J~1;);

1-7

'-------v----'
CHARACTER A

I
I

ll_
I

I
i

I
i
I

*FLAG F/F

II .

1.5jJs MIN.

i
*INT ENA F/F - -

I I

r% 1//;

'----y- - - - J

CHARACTER
B

* SEE INTERRUPT LOGIC.
8E- 0239

Figure 4-2 LE8-E Control Timing

Table 4-1
LES-E lOT Instruction List
Octal Code

Mnemonic

Function

6661

PSKF

Skip on the Flag. Senses the state of the F LAG flip-flop.
If it is set, the program counter is incremented so that the
next sequential instruction is skipped.

6662

PCLF

Clear the Flag. Clears the FLAG flip-flop.

6663

PSKE

Skip on an Error. Senses the state of the READY signal.
If it is low, indicating an error condition in the line
printer, the program counter is incremented so that the
next sequential instruction is skipped.

6664

PSTB

Load Line Printer Buffer Register. A character is transferred from the CPU AC Register, via the OMNIBUS
DATA 5-11 lines and the Line Printer DATA 1-7 lines,
to the Printer Buffer Register.

6665

PSIE

Set I NT ENA flip-flop. The LE8-E is logically connected
to the computer interrupt system. Both the READY
signal and the DEMAND signal can cause a program interrupt.

6666

PCLF, PSTB

Clear the Flag, Load Line Printer Buffer Register. Microprogram of 6662 and 6664.

6667

PCIE

Clear INT ENA flip-flop.

When the 6661 instruction in the servicing routine is decoded, the skip logic asserts the OMNIBUS SKIP L signal.
The computer then proceeds to the subroutine associated with the LE8-E. When the 6666 instruction (as an
example) in the subroutine is decoded, the FLAG flip-flop is cleared and the information in the AC Register is
placed on the OMNIBUS DATA 5-11 lines; at TP3 time the information is clocked into the Buffer Register of
the data transfer logic. At the trailing edge of the 6666 instruction signal, the STROBE signal is generated and
the information is clocked from the DATA 1-7 lines of the line printer into the 20-character Shift Register
within the line printer. The DEMAND signal is then negated and, in turn, negates the STROBE signal.

SECTION 4 DETAILED LOGIC
4.3 SELECT LOGIC
The select logic is shown in Figure 4-3. Both the SELECT L and INTERNAL I/O L signals are asserted when a
666X instruction is decoded. The I NTE RNAL I/O L signal causes the positive I/O bus interface to ignore the
lOT instruction; the SE LECT L signal is gated with bits MD9-11 to provide inputs for the BCD-to-decimal
decoder, E17 (refer to Appendix A, Volume 1, for details about the DEC 8251 IC). The decoder supplies the
signals that represent lOT instructions 6661 through 6667.

4-5

b - - - - - - - - - - - - - - INTERNAL 1/0 L
MD3
MD4
MD6
MD7

L
L
L
L
~_.------------SELECT L

MD5 L

6661 (PSKF) L

.j>.

E17
DEC
8251

MD8 L

6662 (PCLF) L
6663 (PSKE) L
6664 (PSTB) L
6665 (PSIE) L

1/0

PAUSE L
6666 (PCLF, PSTB) L
A
MOil L

6667 (PCIE) L

0
6E-0238

Figure 4-3 Select Logic

4.4 INTERRUPT LOGIC
The interrupt logic is shown in Figure 4-4. When the I NT ENA flip-flop is set, the control is logically connected
to the computer interrupt system. This flip-flop is cleared at computer power turn-on by the OMNIBUS
INITIALIZE signal and can be cleared and set under program control by instructions 6667 (or 6007, CAF) and
6665, respectively.

READy-------------(]
INT RQST L

INITIALIZE
6665 L

6667 L ------+-..._<1

6662 L - - - - - - - - Q
6666 L - - - - - - - q
' - - - ' v v v - - - - - + 5V
8E-0237

Figure 4-4 Interrupt Logic

When the I NT ENA flip-flop is set, both the READY signal and the DEMAND signal can cause a program interrupt. If the READY signal is low, indicating an error condition in the line printer (drum gate open, excessive
temperature in paper drive motor, insufficient drum motor speed, or printer out of paper) NAND gate E13 asserts
the INT RQST L signal and the computer begins the interrupt servicing routine. Instruction 6663 senses the state
of the READY line and causes a skip in the CPU program counter if READY is low (Figure 4-5).

READY------------------~~

6663 L

---------------0

6661 L - - - - - - - - - - - - - - 0
p----SKIP L

---------0

6666 L
6662 L - - - - - - - - - - ( ]
INTIALIZE

8E-0236

Figure 4-5 Skip Logic

4-7

The DEMAND signal causes a program interrupt by setting the FLAG flip-flop, as outlined in Section 3.
Instruction 6661 senses the state of the FLAG flip-flop and causes a program skip when the FLAG is set
(Figure 4-5). The FLAG flip-flop is cleared by the INITIALIZE signal and by program instructions 6662 and
6666.
4.5 DATA TRANSFER LOGIC
The data transfer logic is shown in Figure 4-6. The 7-bit code transmitted from the CPU AC Register to the
printer 20-character Shift Register represents characters that appear on the 64- or 96-character printer drum
(refer to the table of code/character relationship in Volume 1, Section 4). The coded information is gated from
the AC Register to the OMNIBUS DATA 5-11 lines when the 6666 or 6664 instruction is decoded in the CPU.
The SELECT L signal enables the DATA lines to condition the D-inputs of the 7-stage Buffer Register. When the
control decodes the 6666 or 6664 instruction, the buffer is loaded at TP3 time and the coded character is placed
on the printer DATA 1-7 lines.
Each character is followed by the STROBE signal that is generated when the STROBE flip-flop is set by the trailing edge of the instruction. The printer samples the DATA 1-7 lines and negates the DEMAND signal, clearing
the STROBE flip-flop.

SECTION 5 MAINTENANCE
Refer to Volume 1 and the Data Products Corporation technical manual for maintenance information that pertains to both the control and the printer. The LE8-E Diagnostic, MAl NDEC-8E-D2BA, should be run when an
error in the LE8-E is suspected.

SECTION 6 SPARE PARTS
Table4-2 lists recommended spare parts for the LE8-E. These parts can be obtained from any local DEC office
or from DEC, Maynard, Massachusetts.
Table 4-2
LES-E Recommended Spare Parts
DEC Part Number

Description

19-05547
19-05576
19-05590
19-09485
19-09594
19-09686
19-09704
19-09705

IC DEC 7474
IC DEC 7410
IC DEC 7401
IC DEC 380
IC DEC 8251
IC DEC 7404
IC DEC 314
IC DEC 8881

4-8

Quantity

+5V

STROBE

DATA II

DATA 10

DATA 9

DATA 8

DATA 7

DATA 6

DATA 5

SELECT L------------------------------------------~~----------*-----------~----------~~----------~----------~-----------"
6E -0235

Figure 4-6 Data Transfer Logic

PART 5
DATA

COMMUNICATIONS

EQUIPMENT

CHAPTER 5
DP8-E SYNCHRONOUS MODEM

SECTION 1 INTRODUCTION

The PDP-S/E can communicate with remote data terminals and other computers when it is interfaced to fullduplex or half-duplex synchronous modems. A maximum of four DPS-E Synchronous Modem Interfaces can be
plugged into the OMNIBUS; each interface provides a means of transferring data between the computer and a
communication channel.
The interface consists of two quad modules, MS39 and MS66, that are connected by an HS5l Edge Connector.
A signal cable, supplied with the option, connects the MS66 Module to the synchronous modem. The interface
provides level conversion so that the computer can operate with communication channels using bipolar (EIA
standard), current mode, or TTL signals. A DPS-E that interfaces bipolar or TTL signals is designated DPS-EA;
one that interfaces current mode or TTL signals is designated DPS-EB. The DPS-EA Interface is designed to
operate with Bell System 200-series synchronous modems, or equivalent; the DPS-EB Interface is designed to
operate with Bell System 300-series modems, or equivalent. Each type of interface connects to its modem with a
special cable assembly, viz., assembly BCOl V for the DPS-EA and BC01W for the DPS-EB.
Data transfers between a modem and the computer are accomplished by 3-cycle data breaks, initiated and controlled by the DPS-E Interface. A modem-to-computer transfer involves a modified 3-cycle data break operation
that uses seven computer timing cycles, rather than the normal three cycles. The extra four timing cycles enable
the program to detect selected characters that might appear in the modem transmission.
Modems are discussed only to the extent necessary to fully describe the interface operation and to present supplementary information concerning installation and checkout of the option. Details of the installation, operation,
troubleshooting, and maintenance of the modems can be found in their technical manuals. Publications and
documents relevant to the DPS-E are:
a.
b.

c.
d.

POP-8IE & POP-81M Small Computer Handbook - DEC, 1972
POP-8IE Maintenance Manual, Volume 1
DPS-E Diagnostic, MAINDEC-OS-DHDPA-A
DEC Engineering Drawings, Synchronous Modem Interface, E-CS-MS39-0-l and E-CS-MS66-0-1.

SECTION 2 INSTALLATION

The DPS-EA/EB Interface is installed on-site by DEC Field Service personnel. The customer should not attempt
to unpack, install, checkout, or service the equipment.

5-1

Before the interface can be plugged into the PDP-8/E OMNIBUS, each module must be carefully checked to
ensure that it is wired correctly. Each module contains many split lugs that can be selectively connected or
disconnected so that the interface can meet the requirements of the PDP-8/E data break system and function
with any of the compatible modems, which have diverse operating characteristics. The split lugs on each module
are paired. Each pair of lugs is identified by a number, a letter, or a combination of the two (one symbol - .:1
(delta) - and two words - ON and OFF - are used, also). The identification is etched on the printed circuit
board between or near the two lugs and also appears on the schematics and logic diagrams.
Tables 5-1 and 5-2 list characteristics that relate to the PDP-8/E data break system and to the diversity of compatible modems. Those jumpers that connect the pairs of split lugs are also listed. Each jumper bears the same
identification as the two lugs it joins. These tables show the jumpers that must be connected to achieve the
desired characteristic. For example, if the modem transfers characters that have seven data bits, the M839 module
jumpers B7, C7, and B78 must be connected. All other jumpers in this group (B6, B8, and C8) must be disconnected.
All the pairs of lugs, except those labeled C and .:1, are connected by machine-inserted jumpers when the boards
are manufactured. Selected jumpers are then removed so that each module can be production tested. The
characteristics selected for production testing are listed in paragraphs a. through h. which follow. Unless otherwise specified, the two modules are wired for these characteristics when received by the user. Therefore, the
jumper selections might have to be changed to suit the user's needs.

The access addresses, the lOT codes, and the break priority for each interface should be assigned on
the basis of channel designations, as follows:
Channel

Access Addresses

lOT Codes

7720-7730
7700-7710
7660-7670
7640-7650
7620-7630
7600-7610

640X,641X
642X,643X
644X, 645X
646X, 647X

3
4
Spare
Spare
b.

8 bits/character

Normal clock phase

EIA level conversion (DP8-EA)

Current mode level conversion (DP8-EB)

Sync code 226

CARRIER/AGC interrupt for both ON and OFF transitions

Full-duplex operation.

Break Priority

5
4

3
2

When correct jumper selection has been completed, insert the interface in the PDP-8/E OMNIBUS and connect
the modules with the edge connector. See Table 2-3, Volume 1, for information concerning recommended
module priorities (the DP8-E is a "non-memory" option).
Connect the M866 Module to the synchronous modem with the signal cable provided. Refer to Section 5 for
cable and connector pin assignments.
The DP8-E option can be checked for correction operation by running the diagnostic program. If a problem
arises, refer first to Section 5 for ideas. Refer then to the modem instruction manual for modem checkout
procedures.

5-2

Table 5-1
Jumper Connections, M839 Module
Connect Jumper(s)
(Remove Others)

To Select

Figure Reference

Bits/Character
6
7
8

86,C8
87,878,C7
878, 88 (2), C7, C8

5-7,5-9,5-10

P1
P2
P3
P4
P5
P6
P7

5-12

BR K Priority
1
2
3
4
5
6
7
Access Address
7700-7710
7720-7730
7640-7650
7660-7670
7600-7610
7620-7630

A5
A5,A7
A6
A6,A7
NONE
A7

5-15

Device Code
6400-6407,6410-6417
6420-6427,6430-6437
6440-6447,6450-6457
6460-6467,6470-6477

N6, N7
N6,7
N7,6
6, 7

5-5

Sync Code (Examples)
000
226
377
Any code from 000-377
is possible by selectively
connecting the '5' jumpers

NONE
54,57,59,510
54,85,86,87,88,89,810,811

5-9

SECTION 3 BLOCK DIAGRAM DESCRIPTION
The DP8-E includes a receive channel and a transmit channel, each of which can initiate a data break when information is to be transferred between the DP8-E and the PDP-8/E. The channels synchronize the modem and
computer logic and convert computer parallel data to modem serial data, and vice-versa. Figure 5-1 is a simple
block diagram showing the signals used by the interface to synchronize the modem and the computer.

5-3

Table 5-2
Jumper Connections, M866 Module
Connect Jumper(s)
(Remove Others)

Figure Reference

NONE
Pl
Pl,P2
Pl, P2, P3
Pl, P2, P3, P4
Pl,P2,P3,P4,P5
Pl,P2,P3,P4,P5,P6

5-12

ON
OFF
ON, OFF

5-18

E, CE (2)
C (6), CE (2), CT
T (2), CT

E-CS-M866-0-1

To Select
BR K Priority

2
3
4

5
6
7
Carrier/AGC Interrupt
ON
OFF
ON & OFF
Level Conversion
EIA
*Current Mode
TTL
**Clock Phase
Normal
Inverted

.1 (2)

Half-Duplex

N (2)

E-CS-M866-0-1
E-CS-M866-0-1

*If Bell 303 modem is used, jumpers D and X must be connected; if Bell 301 modem is used, jumpers
D and X must be disconnected.
**For maintenance clock (Section 5) connect jumper F. If testing receive circuits, connect jumper.1.;
if testing transmit circuits, connect jumper N.

PDP/8E
OMNIBUS

TIM IN G S I G N A LS

RING

DATA BREAK CONTROL SIGNALS

CARRIER/AGC

MD 0-.11 L SIGNALS

SCR

DATA 0-11 L SIGNALS

SCT

EMA 0-2 L SIGNALS

INTERLOCK /DATA
SET READY

MA 0-11 L SIGNALS
SKI PL. I NT RQST L

DP8-E
INTERFACE

CLEAR TO SEND
RD (RCV DATA)

SYNC
MODEM

SEND DATA

OVERFLOW L

TERM READY
SEN 0 RQST
EXTERNAL TIMING

8E-0458

Figure 5-1 Simple Block Diagram, DP8-E

5-4

The modem generates the INTERLOCK/DATA SET READY signal when it is turned on and able to take part in
a data transfer. The status of this signal can be tested in the DP8-E by the program lOT instruction, SRS1 (see
Table 5-3 for a list of DP8-E lOT instructions). When the status check indicates that the modem is on, the program can issue an SLCC lOT instruction, causing the DP8-E to assert the TERM READY signal. The modem,
which provides the interface with SCT (Serial Clock Transmit) pulses from the moment it is turned on, begins
transmitting SCR (Serial Clock Receive) pulses when it receives the TERM READY signal.
Table 5-3
DP8-E lOT Instruction List
Octal Code

Mnemonic

Description

6400/6420
6440/6460

SSCD

Skip if character detected. Causes the program to skip the
next instruction if the CHAR(acter) DET(ected) flip-flop
is set. The flip-flop is set if an assembled character is found
to compare to one of the stored characters in the access address locations. This instruction clears the flip-flop. If the
program must identify the test character that compared to
the contents of the Receive Data Register, an SRCD instruction should be used. See the SRCD instruction for
details.

6401/6421
6441/6461

SCSI

Clear DP8-E. Initializes all active functions in the DP8-E.

6402/6422
6442/6462

SSRO

Skip if receive word count overflow. Skips the next instruction if the ROFLO L (receive overflow) signal is
asserted, and negates the signal. The signal is asserted if,
during a receive data break operation, the OMNIBUS
OVERFLOW L signal is generated.

6403/6423
6443/6463

SSTO

Skip if transmit word count overflow. Skips the next instruction if the TOFLO L (transmit overflow) signal is
asserted, and negates the signal. The signal is asserted if,
during a transmit data break operation, the OMNIBUS
OVERFLOW L signal is generated.

6404/6424
6444/6464

SGRR

Receiver go. Sets the R-GO flip-flop. The instruction
implies that the program is ready to receive data from the
modem, i.e., the current address (CA) and the word count
(WC) have been updated. The hardware begins memory
references if two consecutive synchronizing characters are
received on the incoming serial data line. Memory references cease when the word count increments to 0 and
SG R R is not issued in less than one character time.

6405/6425
6445/6465

SGTT

Transmitter go. Sets the T-GO flip-flop. The instruction
implies that the program is ready to transmit data, i.e., the
current address and the word count have been updated. If
the CLEAR TO SEND signal has been asserted in response
to the SEND ROST signal, the hardware begins memory
references. References cease when the word count increments to 0 and SGTT is not issued within one character
time. SEND ROST should be asserted by the SLCC instruction; it should not be negated until two bit times after
the last bit has been transmitted, i.e., 1/ [Baud rate x (bits/
character + 2) 1 second after word count overflow.
(continued on next page)
5-5

Table 5-3 (Cont)
DP8-E lOT Instruction List
Octal Code

Mnemonic

Description

6406/6426
6446/6466

SCSD

Clear the sync detect flip-flops. Clears the SYNC 1 and
SYNC 2 flip-flops in the break request, receive logic. The
instruction enables the programmer to initialize the sync
detection circuits and to clear the receive circuits without
initializing the DP8-E.

6407/6427
6447/6467

SRTA

Read Current/Access Address Register. Transfers the contents of the register to the AC Register. The instruction is
used, primarily, for diagnostic and/or program debugging.

6410/6430
6450/6470

SSRG

Skip if the RING flip-flop is set. Skips the next instruction
if the RING flip-flop is set. Clears the flip-flop.

6411/6431
6451/6471

SSCA

Skip if the COl AGC flip-flop is set. Skips the next instruction if the CO/AGC flip-flop is set. Clears the flip-flop.

6412/6432
6452/6472

SLCC

Load control word. Transfers the contents of ACOO-05 to
the control word logic. AC bits 00-03 are loaded into the
CNTL Register; functions selected by each bit are listed
below.
ACOO: TERM RDY; permits the modem to enter into
the data mode.
AC01: IDLE; allows continuous transmission from the
same location in core without program intervention. The hardware enters the Idle mode
when the word count goes to O. Word count and
current address are not incremented. Access to
the last transfer address continues until the SGTT
instruction is issued or the Idle bit is negated.
AC02: ENAB LE; allows program interrupts and data
break cycles.
AC03: SEND ROST; activates the SEND ROST line (see
SGTT instruction description).
AC04: Available for customer use. When modem timing
AC05: signals are used, one EIA (or current mode) trans·
mitter is available for use with AC04 or AC05.

6413/6433
6453/6473

SLFL

Load field. Transfers the contents of ACOO-AC05 to the
load field logic. Bits 00-02 select the receive EMA bits 0-2,
while bits 03-05 select the transmit EMA bits 0-2. The
selected EMA bits, combined with the current address, form
the 15-bit address to or from which data is transferred.

(continued on next page)

5-6

Table 5-3 (Cont)
DP8-E lOT Instruction List
Octal Code

Mnemonic

Description

6414/6434
6454/6474

SRS2

Transfers information from the read status logic to ACOOAC07, as follows:
ACOO: COl AGC L
AC01: RS (1)
AC02: TERM RDY
AC03: CS
AC04: TEMA 0
AC05: TEMA 1
AC06: TEMA 2
AC07: RD

6415/6435
6455/6475

SRSl

Transfers information from the read status logic to ACOOAC07, as follows:
AGOO: RROST L
AC01: TROST L
AC02: Sync 2 L
AC03: Sync 1 L
AC04: REMA 0 L
AC05: REMA 1 L
AC06: REMA 2 L
AC07: MODEM RDY L

6416/6436
6456/6476

SSBE

Skip on bus error. Skips the next instruction if the BUS
ERROR flip-flop is set. Clears the flip-flop. The flip-flop is
set if a transmit or receive break request is not serviced in
less than l/baud rate. This implies that the break system is
overloaded or inoperative.

6417/6437
6457/6477

SRCD

Read detected character. The contents of the 2-bit register
that contains the identity of the detected character are transferred to AC 10 and AC 11. The two bits correspond to the
low-order bits of the access address where the characters
for detection are stored.

Maintenance Instruction - When ACOO is logic 1, the SRCD instruction causes a
single clock pulse to be generated. The pulse is placed on the maintenance clock
line to the modem. In the test configuration (see Section 5, Maintenance), this line
is returned as the transmit and receive clocks enabling single-step testing of the
transmit and receive circuits.

5.1 TRANSMITTER-MODEM DIALOGUE
After this exchange of ready signals, a data transfer can be initiated by either the modem or the computer. A
computer-to-modem transfer is initiated by the computer under program control. An SLCC instruction (either
the same one that causes the TE RM READY signal, or a later one) enables the modem free-running SCT pulses
to set a flip-flop in the DP8-E. The setting of this flip-flop results in the SEND ROST signal being asserted by
the interface. The modem responds to this signal by transmitting the CARRIER/AGC signal, followed by the
CLEAR TO SEND signal. The CARRIER/AGC signal can cause the interface to generate an interrupt request,

5-7

assuming that the DP8-E has been logically connected to the interrupt system. The program proceeds to a DP8-E
subroutine that initializes certain memory locations (Word Count (WC) and Current Address (CA) Registers) and
issues the SGTT lOT instruction. This instruction, along with the asserted CLEAR TO SEND signal, enables the
transmit channel to request a data break. During this data break, a character is transferred from memory to a
shift register in the DP8-E. Subsequently, SCT pulses cause the character to be shifted from the transmit channel
to the modem via the SEND DATA line. At least the first two characters transmitted must be sync characters;
this requirement enables the remote receiving station to assemble each 6, 7, or 8 successive bits to form the
correct character.

5.2 MODEM-RECEIVER DIALOGUE
After the initial exchange of the two ready signals, a modem can initiate a data transfer in response to a ringing
signal on the transmission line. The modem generates the RING signal, thereby causing the DP8-E to generate an
interrupt request. The program proceeds to a subroutine that sets up the WC and CA registers and then waits for
the modem to transmit the CAR R I E RI AGC signal. This signal, which indicates that the modem is in the data
transmission mode, causes the subroutine to issue the SG R RIOT instruction. Data transmitted by the modem
on the RD line is shifted into the receive channel by SCR pulses. The lOT instruction enables the receive channel
to request a data break after two successive sync characters have been recognized in the transmission (the sync
characters enable the receive channel to assemble each 6, 7, or 8 successive bits thereafter into data characters).
During the data break, which must be completed between 2 successive SCR pulses, the character that was shifted
into the receive channel input register from the RD line prior to the data break is transferred to memory. When
the data break ends, SCR pulses shift the next character in the transmission into the register.

5.3 DP8-E DATA BREAKS
A detailed block diagram of the DP8-E is shown in Figure 5-2. This block diagram illustrates the interface operation during the data break. Figures 5-3 and 5-4 are timing diagrams that relate the signals shown in the block
diarlram (each timing diagram depicts 6-bit character operation). All three figures should be studied and used as
reference material.
Data transfers between the PDP-8/E and a synchronous modem interface are of the data break type. A data break
is carried out in the Direct Memory Access (DMA) state of the CPU. This state provides direct communication
between a data break device and memory by allowing the device interface to assume control of CPU major
register gating. When the DP8-E interface is ready to begin a data break transfer, it asserts a number of OMNIBUS
control signals to force the CPU into the DMA state. One of the first of these control signals to be asserted (at
TP3 time) is the CPMA DISAB LE L signal that causes the CPMA Register outputs to be disconnected from the
MA lines at TP4. During TS4, the interface makes a priority check. If no higher priority device has requested a
data break, the DP8-E places on the MA lines (at TP4 time) the address of the memory location that is to be
accessed during the first timing cycle of the data break. At the same time, the MS, I R D ISAB LE L signal is
asserted, forcing the next timing cycle to be carried out in the DMA state. If the synchronous modem were a
1-cycle data break device, data could be transferred, during this DMA cycle, to or from the addressed memory
location. At the end of the cycle, the DP8-E would relinquish control of the CPU until a new transfer were to
take place. The data break operation would be repeated as often as necessary to transfer the entire block of data
words.

5-8

INT RQST L
SKIP L

I
SSRO L,SSTO L,SSBE L SSCD L

OVERFLOW L

INT/SKIP
LOGIC

I
RING
CARRIER/AGC

DATA 10,11 L
DATA 0-11 L
MA 0-11 L
EMA 0-2 L

DATA 0-5 L

.1 LOAD FIELD I

MD 0-11 L

DATA BRK CONTROL SIGNALS
DATA 0-6 L
DATA 0-5 L

(PRIORITY)

-I
cO
DATA 4-11 L

ITEMA/REMA L

(SEE DETAILED LOGIC)

INT STROBE

tTl

CURRENT /ACCESS
ADD REG LOGIC

SRTA L

LOGIC

SGRR L

03 L-D3 L

!
I

CURRENT ADD L
ACCESS ADD L

ACCESS ADD

DETECTED
CHARACTER
REG LOGIC

ill

LOAD CURRENT
ADD L

BRK RQST/
BRK GRANT
LOGIC

ISRCD L

I GTP 4

ACCESS ADD
CTR LOGIC

COMPARE

RRQST L

DETECTED
CHARACTER 10

J=:

DO L-D9 L

TRQST L

BRK RQST RCV/
RCV DATA REG
LOGIC

I
t

BRK RQST XMIT /
XMIT DATA REG
LOGIC

RD TO BUS L

SO L

CLEAR TO SEND
SCT - P L
RD
SCR- P L

MD4-11 L
INTERNAL lIO L
I/O PAUSE L
MD 3-11 L

SSCD, SCSI, SSRO,SSTO
SGRR,SGTT, SCSD,SRTA
SSRG, SSCA,SLCC, SLFL
SR S 1, SRS2 ,SSBE,SRCD

DATA 0-7 L
SRS1/2 L
STATUS SIGNALS
SLCC L

8E-:J4 5 9

CONTROL SIGNALS

DATA 0- 5 L

Figure 5-2 Detailed Block Diagram, DP8-E

rBIT 6

SCR-PL

rBITI

FI----------------------------------------------~I~

I
'-------;1
...------\1
1-\- - - I
R RQST L L ____________________________________---'
E 5, M SB

1-\_ _ _ _ _ _ _ __

TPI

TP2

TP3
T P4
B RK RQST

PRIORITY GO

'r-' '------' L . . -

-+1----------------------------------'1'-'-,1

\1-_ _ __

'rl
----I

""I

CPMA DISABLE L - - - - ,
BR K IN PROG L

I:
1

I II

~ II
:

II:
I
: \1
I I ----H-----

L..

r-r-r---------\

1-'1- - - -

BRK PRIORITY L

1,1
1.1

BRK GRANT ____----J
ACCESS ADDRESS L

MS,IR DISABLE L

LD CNTL (I) _ _ _ _....J

1 I

BREAK CYCLE L
MALC L
COMPARE

f r

I J

-,L____________________________________,I_I,....______~
I

DO L

II
II
II

DI L
D2 L

D3 L
D4 L

I'I

I I

l';1

f r

I J

H
f I

I J

fj rI

~
1
---------------.~r~I-Ir----~\'1

D5 L

INC,

INC, .---....
1 ....
1 ______

DATA 11 L

I i I

Ur"""TI~I--------~1.1

LOA~~~:E~E:r

CURRENT ADDRESS L

D6 L ----------------~I~I~I---~

REMA L
BREAK DATA CONT L
R D TO BUS L

DATA+MD .... MB

II
1\

--Ll.......

~'------\1\

--------------------------------------iU.---------IH
8£-0460

Figure 5-3 Timing, Receive Break Request

However, the synchronous modem is not a 1-cycle data break device; i.e., it does not continuously update the
memory address to or from which data is transferred and, within its hardware, it does not keep track of the
number of transfers made. Data break devices that do not perform these two necessary tasks are defined as
3-cycle data break devices. The transfer count and the transfer address are retained in the separate memory locations that were introduced earlier, viz., the Word Count (WC) Register and the Current Address (CA) Register,

5-10

respectively. During a data break operation, each location is addressed separately and the data in each location
(the word count or the current address) is updated by the interface.· A single timing cycle is required for each
updating operation. Thus, three timing cycles are required for each data word transferred: the word count is
updated during the first cycle; the current address is updated during the second cycle; the data word is transferred
during the third cycle.
rBIT 6
SCT-P L

rBIT 1

FI------------------'l,1 \-',--..,U

E10. MSB 1

~------__\', \)-_ _ _ _ _ _ __

TROST L

S--------J,\ '\-,- - - - - - - -

\..1_ _ _ _ _ _ _ _ _

TPI
TP2
TP3
TP4

--.11

'---------J,'I

BRK IN PROG L

----'1

...--------\',

PRIORITY GO

.--.11

BRK ROST
CPMA DISABLE L

-.<;-i-+---------'

'I "
\-1,- - - - - - - -

~--------~\\\-------------r--------~\\---------

BRK PRIORITY L
BRK GRANT _ _---I

L -_ _ _ _ _ _ _ _~\\~_ _ _ _ _ _ _ _ _ _- -

r--------~\

ACCESS ADDRESS L
MS. IR DISABLE L

'\_j_ _ _ _ _ _ __

' \ - j-

r------~\I\-J-------------

"-----------'

--------------

LD CNTL (1) _ _ _---..I

~----~\'\-,

r-------I\I\-,---------------

BRK CYCLE L

'----------'

,-----__J,\I\-,______________

MALC L
D7L
D8 L

-----"

------~,

LOAD CURRENT ADDRESS L
CURRENT ADDRESS L
TEMA L
BREAK DATA CONT

,r---------\\I\-,------------

L...-:..-..J

D9 L _ _--,INC
DATAl1 L

,r------------J,\'\-,------------

INC'------------1j

\-j\--_-_-_-_-_-_-_-_-_-_-_-.:-_-_-_

W.;.,;C'--_ _" " ' c A - ' - ' I "

""I

-------~u~----------J,\\-\-----------------------,1

,~----------I\\-\---------------

---------~I

,~----------I\\-\------------

~
~

I DATA+ MD ---MB

.-------~\'\-,---------

SO L ----------------------------~\\-\--~L -_ _ __
8E-0461

Figure 5-4 Timing, Transmit Break Request

If the data transmission is from the DP8-E to memory, the 3-cycle data break operation is modified somewhat.
The DP8-E Interface is capable of identifying selected data characters that might appear in the data transmission.
The identification is accomplished by comparing each data character in the transmission with a test character.
Four test characters are provided; thus, the interface can identify four different data characters. The test characters are stored in four separate memory locations that are successively addressed at the beginning of the data

5-11

break operation. Each comparison requires a single timing cycle. Therefore, a receive data break operation
requires seven timing cycles, rather than three, for each data word transferred. However, the operation is still
considered a 3-cycle data break.
A receive data break operation can begin only after the data character has been shifted completely into the interface Receive Data Register. When the last data bit is shifted in, the interface requests a data break and asserts the
CPMA DISAB LE L signal to remove the CPMA Register from the MA lines. Then the interface places an "access
address" on the MA lines. The memory location represented by this address is one of a group of eight specialpurpose memory locations assigned to the modem/interface in question (each modem/interface occupies one
communication channel). These locations are assigned to the communication channels as indicated in Section 2.
To simplify the discussion, only Channel 1 is considered. Locations 7720 through 7723 contain the four test
characters; locations 7724 and 7725 contain the receive word count and current address, respectively; locations
7727 and 7730 contain the transmit word count and current address, respectively.
The first access address to be placed on the MA lines at the beginning of the receive data break operation is 7720.
This address originates partly in the Current/Access Address Register logic and partly in the Access Address
Counter logic. The test character stored in this location is gated to the Receive Data Register logic and compared
with the received character stored there. This action can have one of three results: a) if the two characters are
not equal, no further action occurs during this timing cycle; b) if the two characters are equal, an interrupt
request can be generated during this timing cycle; c) if the two characters are equal, the data break operation can
be terminated near the end of this timing cycle, i.e., the received character is stripped. If either a) or b) results
from the comparison, the access address is incremented by the Access Address Counter logic at the end of the
timing cycle. The test character in location 7721 is gated to the Receive Data Register logic during the second
timing cycle and compared with the received character. This comparison can have one of the three results indicated. Again, the access address is incremented at the end of the cycle, provided the received character is not
stripped. The comparison process is carried out for the four test characters. If a successful comparison occurs
during the first, second, or third test cycle, the remaining test characters must still be compared. When the
fourth test character has been compared, the access address increments to 7724, which represents the memory
location of the word count. During the fifth timing cycle, or WC cycle, the word count is incremented. The
access address then increments to 7725 and, during the sixth timing cycle, the CA cycle, the current address is
incremented.
This incremented current address is the address of the location to which the received character is to be transferred
during the seventh, or data transfer, timing cycle. This "current address" is placed on the MA lines at the end of
the CA cycle. During the data transfer cycle, the received character is gated from the Receive Data Register to
the OMNIBUS DATA lines and from the DATA lines to the location specified by the current address. At the end
of this timing cycle, the data break operation is terminated.
To carry out a transmit data break operation, the DP8-E asserts the same control signals as it does during a receive
data break. However, no test character timing cycles are necessary; consequently, only three timing cycles are
used to transfer each data character.
Each logic block indicated in Figure 5-2 is discussed in detail in Section 4. The separate sections are arranged to
present the information in the most logical progression; however, some points, because of their complexity, are
covered in more than one section, albeit from a different viewpoint.

5-12

SECTION 4 DETAILED LOGIC
5.4 lOT DECODER LOGIC
The PDP-8/E can accommodate four separate communication channels. Hence, four sets of lOT instructions are
needed. A set consists of 16 instructions, each instruction represented by an octal code and a mnemonic code.
The same 16 mnemonic codes are used with each set of instructions; however, the octal codes vary from set to
set. The octal codes for each channel are determined by the selective connection of certain jumpers on the M839
Module. When this module is fabricated, the octal codes are assigned to the channels as detailed in Section 2.
The lOT decoder logic portion of the M839 Module is shown in Figure 5-5. Locations are indicated on the figure
where jumpers can be connected to provide the 16 octal codes for a particular channel. These locations are designated 6, 7, N6, and N7. Assume that this interface is assigned to Channell. Octal codes 6400 through 6407 and
6410 through 6417 must be selected. This is accomplished if jumpers are connected at locations N6 and N7.
Thus, NAND gate E19 asserts the THIS CODE signal during TS3 of lOT instructions 640X and 641 X.
Bit MD 8 is gated with the THIS CODE signal to provide an enabling signal for one of the DEC 8251 Decoders.
If bit 8 is logic 0, E38 is enabled, and a 640X instruction can be decoded; if bit 8 is logic 1, E26 is enabled, and
a 641X instruction can be decoded.
The three least significant bits of the instruction are determined by MD bits 9,10, and 11. These bits are gated
to both decoders; the enabled decoder produces the assigned octal code.
Note that the THIS CODE signal causes NAND gate E33 to assert the OMNIBUS INTERNAL I/O L signal. This
signal ensures that the positive I/O bus interface ignores the lOT instruction.
5.5 CONTROL WORD LOGIC
The control word logic is shown in Figure 5-6. The SLCC instruction gates the contents of the AC Register to
the DATA lines. The user can load AC bits 0-5 to assert selected DP8-E enabling signals.
The information on DATA lines 0-3 is loaded into the CNTL Register at TP3 time of the instruction. Each of
the four possible enabling signals is discussed in later sections. Flip-flops E27 allow the user to enable functions
of his own choosing. The l-output of each flip-flop can be taken from the board at the "H" top connector or
at connector J 1, if jumpers are installed at locations FF and JJ. Note that these outputs are TTL-level rather than
E IA-level Signals.
5.6 BREAK RQST, RECEIVE LOGIC
The Break RQST, Receive logic is shown in Figure 5-7. When communication in the receive mode has been
established between the modem and the PDP-8/E, the modem begins transmitting data to the interface. Each
character bit is shifted into the Receive Data Register (Paragraph 5.7) by an SCR-P L pulse. Each SCR-P L pulse
also clocks the RCV CNT binary counter, E5 in Figure 5-7 (note that the counter is wired for 6-bit/character
operation). When an entire character has been shifted into the Receive Data Register, the most significant bit
(MSB) of the RCV CNT counter becomes logic 1. If both the R-GO flip-flop and the SYNC 2 flip-flop are set,
NAND gate E3 generates the R RQST L signal, and a data break operation can begin. During this operation, the
character in the Receive Data Register is transferred to the PDP-8/E memory.

5-13

E38
8251

THIS CODE

SSCD L

MD3 L

SCSI L
INTERNAL
I/O L

MD4 L

SSRO L

640X
642X
644X
646X

SSTO L
SGRR L

DCDR

SGTT L
SCSD L

MD5 L

SRTA L

MD9 L
MD6 L -->-+---01

MDW L

MD 11 L --+--1---41
r-4---------~0,,7

MD7 L ~---1-0I

" 0------01
~N;~

r
I
I

Pia M866

I
I
I

TS 2 L ----1---1

I
I

I /0 PA US E L --------------------------d

--------,
E26
8251

I
SSRG L
SSCA L
SLCC L

641X
643X
645X
647X

SLFL L
SRS2 L

DC DR

SRSI L

SSBE L

I
MD8 L-------------------------------~----~--~

SRCD L

I
I

IL _______________________ I
~

NOTE:
Unless noted ,logic is P/O

M839 module.
8E-0462

Figure 5-5 DP8-E lOT Decoder Logic

TERM RDY
+3V

r--,

t - - - - - - - - - 1 E 1 2 ':>0-----1 NOTE 2 I - - TERMINAL READY
L _ _ .J
(J1DD)
IDLE

DATAO L

t-------jE21 ' ) 0 - - - - - - - -

DATA 1 L--'---"'--"'"

ENABLE
E14
74197
CNTL

ffif) L

~-------(!CN;,)RQST L
. -_ _ _ _ _ (BF'i,,~)RQST

...-:::---!..,
SEND
RQST

r - - .....,
. - - - - - - 1 NOTE 2 I-- SEND RQST
L __ -l
(J1V)

,---,
r:
ch

IN! L

NOTE 2 f--FJ~nRNAL TIMING

I - _ _ ...J

SCT L

HAl

F
FF (2)

(J1FF)

DATA4 L

HBl
JJ (2)1-------(J1JJ)

DATA5L--'---~-'~I--_ _ _ _ _ _ _~_ _ _ _ _~_ _ _~

NOTES:
1. Logic is Pia M866 module.
2. See DEC Eng.Drng. E-CS-M866
for gating circuity.

TP3

SLCC L
8E-0478

Figure 5-6 Control Word Logic

The R-GO flip-flop, which is cleared at INITIALIZE time, must be set by the SGRR lOT instruction during the
time that communication is first established. The SYNC 2 flip-flop is set only when two successive sync characters have been transmitted by the modem. The detection of the sync characters is carried out by a comparison
process in the Receive Data Register logic (the comparison is performed in the hardware and does not use the
special break locations). The character in the Receive Data Register is compared with the jumper-selected interface sync code.

5-15

NOTES:
1. Logic is PIG M839 module.
2. ReV CNT Counter wired for 6 Bit/Character Operation.

INI
SCSD L ----.6

+5V

_-'

+3V
11

12
E5
74197
RCV
10 CNT

MSB

R R QST L

SCR-P L -......- - - d

COMPARE

SGRR L

INI L

ROFLO L
TP3

RD TO BUS L - * - - - - - - - - - - - - - - - - - - - - - - - - '
8E-0463

Figure 5-7 Break RQST, Receive Logic

Assume that the first character in a particular transmission is a sync character (Figure 5-8 is helpful in visualizing
the sync character detection process). As the SCR-P L pulse shifts the sixth character bit into the Receive Data
Register, the COMPARE signal is asserted, because each of the six character bits is the same as the corresponding
sync code bit. The COMPARE signal is applied to the D-input of the SYNC 1 flip-flop, and the flip-flop is set,
indicating that one sync character has been detected (the SYNC 1 flip-flop is set by the trailing edge of the
SCR-P L pulse; the delay of a few nanoseconds is exaggerated in the timing diagram). Until this first character is
detected, the RCV CNT counter, E5, is prevented by the 1-output of the SYNC 1 flip-flop from counting SCR-P L
pulses. The 1-output causes the count/load input, pin 1, of the counter to be held low. This low not only prevents E5 from counting, but also presets E5 with a count of 0010.
When the 1-output of the SYNC 1 flip-flop goes high, E5 can begin counting pulses. If the next character shifted
into the Receive Data Register is another sync character, the COMPARE signal is asserted again. The MSB output
of E5 goes high with the trailing edge of the SCR-P L pulse. The low at the D-input of the SYNC 2 flip-flop
enables the output pulse from NOR gate E8 to set the flip-flop. NAND gate E3 asserts the RROST L signal.
If priority requirements are met, the receive data break operation begins at the next occurrence of a TP4 pulse.
The operation takes place between the two bits indicated on the timing diagram. Even the fastest modem available is so slow compared to the computer timing cycle that approximately 15 timing cycles can occur in the time
space indicated by the dashed lines. Figure 5-3 is a timing diagram of a receive data break operation. Bit 6 and
bit 1 in each timing diagram correspond, to call attention to the relative timing of the computer and modem
(Figure 5-3 should be referred to when considering any of the receive circuits).
If the first occurrence of a sync character is not followed by a second, the SYNC 1 flip-flop is cleared at the time
that the MSB of E5 goes high. In such a case, the timing reverts to that indicated at the beginning of Figure 5-8.
Therefore, two sync characters must occur successively somewhere in the transmission. When this happens, both
the SYNC 1 and the SYNC 2 fl ip-flops remain set throughout the transmission, and can be cleared only by the
SCSD lOT instruction, or at INITIALIZE time.
Each time the MSB of E5 goes high, a break request results. During the data transfer cycle the RD TO BUS L
signal gates the character in the RCV DATA Register onto the OMNIBUS DATA lines. At this time, pin 1 of
the RCV CNT counter is taken low, presetting the counter with a count of 0010. The MSB goes low and the
RROST L signal is negated. After six SCR-P L pulses a new break request can be generated.
Requests are generated until the last character is transferred. During the WC cycle immediately preceding the last
data transfer cycle, the OMNIBUS OVERFLOW L signal is asserted, causing ROFLO (0) L to be asserted by the
INT/Skip logic (Figure 5-19). The RD TO BUS L signal then clears the R-GO flip-flop, thereby disabling NAND
gate E3.
Note that the RCV CNT counter can be reset to the initial count by the STRIP L signal that enables NOR gate
E3. This signal is asserted when a received character has compared successfully with one of the stored test characters and the O-bit of the test character is logic 1, i.e., MDO is logic 1. In this case, the data break operation ends
after the break cycle in which the comparison took place. Consequently, neither the word count nor the current
address is incremented, and the character in the Receive Data Register is not transferred to memory. Refer to
Paragraph 5.15 for a discussion of the events that occur when MDO is logic O.

5-17

SCR- P L

SYNC 1 ( 1 ) - - - - - - - - - - - j J 1 .

W~/;I$_$fl$)w_t/;l$~@fl/;l/;l~
I

I
I
I

~I__+1_______________

I
I

E8'P8~

I
I

mL~
I-

SYNC2(1)

E8, p3

COMPARE _ _ _ _ _ _ _ _- J

________

I
E5,p8

i I

E5, p1 _ _ _ _ _ _ _ _ _---'

----:nL---+-_______---Jf

E5, MSB _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

I
R-GO(1)---

I
I
I

-----------------------------,U
R RQST L

/
/

I
I

I
\

\
8E-0464

Figure 5-8 Sync Character Detection, Timing Diagram

5.7

RECEIVE DATA REGISTER LOGIC

The Receive Data Register logic is shown in Figure 5-9. The logic has two functions: a) to compare received
data with either the interface sync code or test characters stored in memory; b) to transfer the received data to
the OMNIBUS DATA lines.
+5V
+5V

MOll L

MOlD L- -

r--

,.....--.

r
tD
tD t-o r

JE»-

I---OSII

E45
8266

t-<>SlO

M09 L- -

t---<>S8

MD8 L -

~COMPARE

~&
~&

,-J&

+3V

+,d

.----tr--- DATA 11 L

INT L

L:Cr

SCSD L

I>-- DATA 10 L

E37 9
8271
RCV
DATA 7

E53
8235

I>-- DATA 9 L

SCR-P

L.1L

.-----

~+rVC=

1 10
14
11

p- DATA 7 L

«
1'5V

B6~B78

(

B7~8'?>
'V

15 E37 9
8271
RCV
3 DATA 5

E36
8235

C B8

"<T

jf3

+5V
MD7

I
L-=D
LI
~ ~S6
r
~
"'S7

MD6

1
2

~S5

SYNC 2 III

REMA L
TS2

~S4

p- DATA 5 L
~ DATA 4 L

L-)&
E25
8266

~ DATA 6 L

=;&

,-----:....

MD5 L

MD4 L -

f>- DATA 8 L

NOTE'
Logic is Pia M 839 module.

)}00-

RD TO BUS L

E35

8E-0465

Figure 5-9 Receive Data Register Logic

5-19

The data is received in serial form as the RD signal (this signal is high, representing logic 1, when the mark
condition exists). Each data bit is shifted into the Receive Data Register, E37 and E54, by its accompanying
SCR-P L pulse. Jumpers B6, B7, B8, and B78 must be selectively removed or connected so that the Receive Data
Register corresponds to the number of bits per character of the received data (see Table 5-1 for information concerning jumper selection). For example, if the data being received contains 6 bits per character, only jumper B6
is connected. Only two bits of the 4-bit shift register, E37, are used; thus, E37 and E54 comprise a 6-bit shift
register. The register is filled each time an entire character has been received. Note that although E54 is in the
"right-shift" mode, as one expects (see Volume 1, Appendix A for 8271 details), E37 is always in the "parallelload" mode. However, because of the way E37 is externally wired, the IC operates as a right-shift register.
When an entire character has been shifted into the register, the character is compared and/or transferred to the
DATA lines. A comparison is always made at the beginning of a transmission to determine if the character
received is a sync character. If it is, it coincides with the interface sync code. If two successive sync characters
are received, two successful comparisons are made and the interface requests a data break of the CPU.
The received character and the sync code are compared, bit for bit, by Exclusive-NOR gates E32 and E55, each
of which acts as a comparator. Each bit of the received character is applied to one input of a comparator. The
other comparator input is taken from E25 or E45, DEC 8266 ICs (see Volume 1, Appendix A for details). These
ICs are 4-bit logic elements (multiplexers) that are used as selectors. For example, E25 provides an output at
pin 3 that represents the state of the input signal at either pin 1 or pin 2. The selection is determined by the state
of the control signals at pins 7 and 9. If pin 9 is low, E25 provides an output at pin 3 of the same state as the
input at pin 2; if pin 9 is high, the output state at pin 3 is the inverse of the input state at pin 1.
When the received character is being compared to the interface sync code, the SYNC2 (1) signal is low. Thus,
pin 3 is the same state as pin 2. The state of pin 2 depends on whether or not jumper S7 is connected. Likewise,
the state of each other output pin of E25 and E45 depends on whether or not a corresponding jumper is connected. The jumpers are connected or removed to select the desired sync code. Assume that the desired sync code
is 268 (the LSB of the sync code/character corresponds to the LSB of the PDP-8/E data word; the LSB of the
received character is the first bit transmitted from the modem). Jumpers S7, S9, and S10 are connected, all others
being removed. The signal at each of the following 8266 output pins is low; E25, pin 3; E45, pins 13 and 4.
If the character in the Receive Data Register is a sync character, the signal at each of the following 8271 output
pins is low: E37, pin 11; E54, pins 7 and 9. The input signals at each comparator coincide and, thus, the
COMPARE signal is high. As the first bit of the next character is shifted into the Receive Data Register, the
COMPARE signal goes low. When this next character has been shifted in completely, the COMPARE signal again
goes high, assuming that this character, likewise, is a sync character. The SYNC2 (1) signal is asserted, indicating
that two successive sync characters have been received from the modem, and the interface requests a data break
(see Paragraph 5.6 for further details and for a timing diagram that includes the COMPARE signal and the·
SYNC2 (1) signal).
Any further comparisons that are made during this transmission involve the received data and a test character
stored in a memory location. Because the SYNC2 (1) signal remains high throughout the entire transmission,
information on the MD4-11 lines is gated through selectors E25 and E45 for comparison with the received data.
This comparison process is described in detail in Section 3, and Paragraph 5.11.
The character in the Receive Data Register is transferred to the PDP-8/E memory via the OMNIBUS DATA lines
during the data break operation (unless the character is to be stripped). The RD TO BUS L signal gates the data
through the 8235 4-bit logic ehiments to the DATA 4-11 lines. Note that DATA bits 4 and 5 are negated if the
received data contains 6 bits per character, as has been assumed throughout this discussion. If the data in a
memory location is to be compared with a received character of 6 bits, bits 4 and 5 of the selected location must
be logic O. The same reasoning applies to bit 4 when the received data contains 7 bits per character.

5-20

5.8 BREAK ROST, TRANSMIT LOGIC
When the modem is turned on, it begins to transmit SCT pulses. After the program has issued an SLCC lOT
instruction, an SCT L pulse sets the RS flip-flop in the DP8-E (see Paragraph 5.5, Control Word Logic); the
resulting SEND ROST signal causes the modem to activate the CLEAR TO SEND line. The CLEAR TO SEND
signal enables the Break ROST, Transmit logic, Figure 5-10, to assert the TROST L signal.
NAND gate E3 asserts the TROST L signal if flip-flop E2 is set and if the MSB signal is high (the third input to E3
must be high if E2 is set). E2 can be set by an SCT-P L pulse if the T-GO flip-flop is set and if the CLEAR TO
SEND signal has been asserted. The SGTT instruction sets the T-GO flip-flop; consequently, the transmit
synchronization process is, essentially, a program function (note that the initial count of the XMIT CNT counter,
E10, is unimportant). When the last character is transferred, the T -GO flip-flop is cleared and TROST L is
negated, unless the Idle mode was previously loaded into the Control Word logic. If this was done, E13 remains
enabled and the TROST L signal remains asserted, allowing continuous transmission from the last addressed core
memory location.
When the TROST L signal is asserted, the transmit data break operation can begin at the next occurrence of a
TP4 pulse. Figure 5-4 is a timing diagram of such an operation and should be referred to when considering any
of the transmit circuits. During the data transfer cycle, represented by the D9 L signal, the character to be transferred from memory is gated onto the MD lines. At TP3 time, the character is parallel-loaded into the XMIT
DATA Register (Paragraph 5.9). The register is shifted by each succeeding SCT-P L pulse, until all six bits, for
example, have been shifted out of the interface via the SD (Serial Data) line.
When TS3 of the data transfer cycle is first entered, the XMIT CNT counter, El0, is reset to the initial count of
0010 via NAND gate E18. Each SCT-P L pulse that shifts the XMIT DATA Register is counted by the XMIT
CNT counter. Thus, the sixth pulse not only shifts the MSB of the character onto the SD line, but also causes
the MSB of the counter to become logic 1. The TROST L signal is asserted again and another break request can
be generated.
Requests are generated until the last character is transferred. During the WC cycle immediately preceding the
last data transfer, the OMNIBUS OVERFLOW L signal is asserted, causing the TOFLO (0) L to be asserted by
the INT/Skip logic (see Figure 5-19). The T-GO flip-flop is then cleared when NAND gate E26 is enabled at the
beginning of TS3. The TROST L signal is negated, unless the Idle mode was programmed previously.
Note that when the T-GO flip-flop is set, NAND gate E34 asserts the OMNIBUS DATA 11 L signal during the
CA and WC cycles (represented by the D7 L signal and the D8 L signal, respectively) of the transmit data break
operation. The BRK Grant logic asserts the BREAK DATA CONT L signal throughout the transmit data break,
thereby enabling the CPUgating to add MD bits and DATA bits and transfer the sum to memory. The process is
represented symbolically as DATA+MD-*MB. Because the MDll L signal is asserted during the WC and CA
cycles, both the word count and the current address are incremented and returned to memory.
If the Idle mode is entered after the T-GO flip-flop is cleared, a continuous transmission from the last addressed
core memory location takes place. The D7 Land D8 L signals are repeatedly asserted, in turn, throughout such
a transmission. Consequently, NOR gate E47 is ena,bled in the Idle mode. To prevent both the word count and
the current address from being incremented, the l-output of the T-GO flip-flop is applied to NAND gate E47.
Thus, the word count and the current address are incremented only when T-GO is set.
The DATA 11 L signal is asserted during the CA and WC cycles (represented by the D4 L signal and the D5 L
signal, respectively) of the receive data break operation, also. Again, the result is an incremented word count
and transfer address. Because an Idle mode is not possible during a receive data break, the gating requires only
the D4 L signal or the D5 L signal and the B R K G RANT signal to enable E34.

5-21

INI L

+5V
+3V
TRQST L
MSB
11
C7

E10
74197
XMIT
CNT

13
IDLE L

LSB

CLEAR TO
SEND
07 L
08 L
DATA 11 L

SCT-P L -

.......-~:II

SGTT L

BRK
GRANT

09 L
TS3 L

LD CNTL (il
NOTES:
1, Logic is PIO M839module,
2, XMIT CNT counter wired for 6 bit/character operation.
8E- 0466

Figure 5-10 Break Request, Transmit

5.9 TRANSMIT DATA REGISTER LOGIC
The Transmit Data Register logic is shown in Figure 5-11. This logic transmits data from the OMNIBUS MD lines
to the synchronous modem input.

SO L

INI L

+3V ---.~
1

MOil L

10
11~------------------------~------~

MOIO L
E39
8271
XMIT

M09 L

DATA

MD8 L

+3V_~>--

M07 L

10
11

M06 L
E16
8271
XMIT
M05 L

DATA

M04 L

09 L

TS3 L - - - . . .

LO CNT L (1) ----------------'

TP3

SCT-P L----------------------------------~~------------------------~
NOTE:
Logic is PIO M839 module.
8£ - 0467

Figure 5-11 Transmit Data Register Logic

5-23

The character stored in the current address location is gated onto the MD lines during TS2 of the data transfer
cycle. During TS3 of the cycle, NAND gate E18 is enabled, placing the Transmit Data Register in the parallelload mode. At TP3 time, the register is clocked via the E35-E18B-E20 path, and the character on the MD lines is
loaded into the register. When TS3 ends, 50 ns later, NAND gate E18A is disabled, placing the register in the
right-shift mode. At this time the LSB of the character is applied to the D-input of the SEND DATA flip-flop.
The first-occurring SCT-P L pulse after the data break ends clocks the SEND DATA flip-flop. This action places
the LSB of the character on the SD L line. Simultaneously, the Transmit Data Register is right-shifted and the
next character bit is applied to the SEND DATA flip-flop's D-input. Six SCT-P L pulses shift-out the register; the
sixth pulse can cause the Break Request, Transmit logic to assert the TROST L signal and another data break can
begin.
5.10 BRK ROST LOGIC
The BRK ROST logic is shown in Figure 5-12. Either the RROST L signal or the TROST L signal can cause the
INT STROBE signal to set the BRK ROST flip-flop. Note that the flip-flop is cleared when the OMNIBUS
INITIALIZE signal is generated, if the ENABLE signal has been asserted by Control Word logic. If the ENABLE
signal has not been asserted, the BRK ROST flip-flop is held in the clear state.
When the B R K ROST signal goes high, both the B R KIN P ROG Land CPMA D ISAB LE L signals are asserted.
The CPMA DISABLE L signal results in the CPU CPMA Register being disconnected from the OMNIBUS MA
lines, while the BRK IN PROG L signal ensures that only data break devices place priority information on the
OMNIBUS DATA lines during TS4.
When TS4 is entered, the BRK PRIORITY L signal is asserted; i.e., the priority of this interface is placed on the
DATA B US. Simultaneously, all other data break devices place their priorities on the DATA B US. There can be
as many as 11 other data break devices, including up to three DP8-Es, connected to the OMNIBUS via their
respective interfaces. However, only six of these can have a higher priority than this modem.
Assume that there are, indeed, six data break devices that have a higher priority. This means that this DP8-E
has priority 7. To establish this priority, one must ensure that the following jumpers on the two interface modules
are connected: P7 on the M839 Module; P1 through P6 on the M866 Module (Figure 5-12). Thus, this interface
places its priority on the DATA 6 line. The priority of all other data break devices is established by connecting
selected jumpers on similar networks within the respective interfaces. The device having highest priority, which
is usually the fastest device, places its priority on the DATA 0 line. The second-highest priority device uses the
DATA 1 line, and so on. If, during a particular TS4, no other device is requesting a data break, or, if a requesting
device is of lower priority than this interface, the DATA 0 L through DATA 5 L signals are negated. NAND gate
E9 is enabled, causing E23 to assert the PR 10 R ITY GO signal. This signal causes the break request to be granted.
If any of the six higher-priority devices requests a data break at the same time as this interface, the device places
its priority on its assigned DATA line. Thus, one, or more, of the DATA line signals, DATA 0 L through
DATA 5 L, is asserted. NAND gate E9 is disabled and the PRIORITY GO signal remains negated. This interface
must wait until the next TS4, when it again places its priority on the DATA BUS.
5.11

BREAK GRANT LOGIC

When the DP8-E asserts the PRIORITY GO signal, the Break Grant logic completes the CPU takeover process
that was begun by the B R K ROST logic. The Break Grant logic is shown in Figure 5-13.

5-24

r---------------------------------,
P/O M839

*
PI er--- DATA 0 L
BRK
PRIORITY L

* TS4 L -~---...

P2 er---*DATA I L
P3 er---*DATA 2 L

~-----I--"'"

P4 er---*DATA 3 L
P5 er---*DATA 4 L
*BRK IN PROG L

P6 er---*DATA 5 L
P7 er---*DATA 6 L

*CPMA DISABLE L

L ___________ _
BRK ROST

+3V

--------------------~
+5V

PRIORITY
GO
*DATA 0 L

INI L

ENABLE

* INT

STROBE

DATA I L
P2

..
(Pia M839 - - - - ,
I
I
I

I
TROST L
I
L _______ -1
RROST L

DATA 2 L
P3

ROST

~+---~--~

*OMNIBUS SIGNALS
NOTE:
Unless noted, log i c is P/O M8G6 module.

* DATA 3 L
P4

DATA 4 L
P5

..DATA 5 L
P6

8[-0468

Figure 5-12 BRK RQST Logic

[([D7 L+DB L]oT-GO(1))L+D4 L+D5LJ

+3V

DATA 11 L

D6 L

+3V

* MS, IR

BRK CYCLE L

BREAK DATA
CO NT L

MALC L
DISABLE L

+5V
REMA L

TEMA L

ACCESS L....oT---;y......J
ADDRESS
RESET L

BRK GRANT

CURRENT
ADDRESS L

ACCESS
ADDRESS L

---,

r----P/O M866

I
I
I

INI L

D5 L

D8 L

GTP41

PRIORITY GO -

...- - - - - - - - - - - - - - - - - -.....~L_/

L. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ...J

* Omnibus signals

LOAD CURRENT
ADDRESS L

NOTE:
Unless noted, logic is PIO M839 logic.
8E-0469

Figure 5-13 Break Grant Logic

The PRIORITY GO signal enables the TP4 pulse to set the B R K GRANT flip-flop and, also, to generate the GTP4
pulse. The l-output of the flip-flop enables NAND gate E22 to assert the OMNIBUS MS, IR DISABLE L signal.
This signal forces the CPU to enter the DMA state and disables the CPU I R Register. At the same TP4 time, the
output of the CPMA Register is removed from the MA lines, the BRK RQST logic having asserted the CPMA
DISABLE L signal at the previous I NT STROBE time. The interface now specifies the address of the memory
location that is to be affected during the next memory timing cycle, which is the first cycle of the data break
operation.
This address is placed on the MA Iines by the Current! Access Address Register logic, which is discussed in detail
in Paragraph 5.13. Briefly, this logic places either an access address or a transfer address on the MA lines. Because
the modem is a 3-cycle device, the data transfer cycle is preceded by at least 2 cycles of operation, word count
(WC) and current address (CA). If the data character is to be transferred from the DP8-E to memory - a receive
break request - the WC and CA cycles are preceded by 4 test character recognition cycles. Test characters, the
word count, and the current address are stored in memory locations specified by access addresses. Thus, the first
cycle of a Data Break operation, whether of a Receive Break Request or of a Transmit Break Request, involves an
access address. Although this address is placed on the MA lines by the Current/Access Address Register logic, the
Break Grant logic, by asserting either the ACCESS ADDRESS L signal or the CURRENT ADDRESS L signal,
determines which type of address is selected.
Thus, when the BRK GRANT flip-flop is set at TP4 time, NAND gate E26 asserts the ACCESS ADDRESS L
signal (flip-flop E23 is cleared by the GTP4 pulse). Simultaneously, NAND gate E34 asserts the BREAK DATA
CONT L signal, which provides a convenient method of updating the word count and the current address, as well
as re-writing recognition characters in memory. This method is explained fully later in this section.
At TP1 time of the next memory cycle, the LD CNTL (Load Control) flip-flop is set, causing NAND gates E22 to
assert the BRK CYCLE L signal and the MALC L signal. The BRK CYCLE L signal is applied to the programmer's
console and can be monitored on the display panel. The MALC L signal prevents the CPMA Register from being
clocked during the data break operation (see Volume 1, Paragraph 3.34.1 for details). During the data break cycle
begun by this TP1 pulse, the information in the access address is placed on the MD lines. The type of information
depends on the type of break request that is being carried out.
If a receive break request is starting, the information on the MD lines is a test character. This character is compared to the received character in the Receive Data Register logic. When the comparison has been made, the test
character is returned to memory during the write half of the timing cycle. The re-write in memory is made
possible by the BREAK DATA CO NT L signal that results in the CPU operation DATA+MD to the MB. Since
the DATA lines carry no information at this time, only the information on the MD lines, the recognition character, is returned to the memory location. If the received character compares bit-for-bit with the test character, an
interrupt request can be generated by the interface, or the received character can be stored with no other action,
or the data break can be terminated immediately (the character is "stripped"). If a successful comparison is made
and the character is not stripped, or if the received character and the test character differ, the data break operation continues. During each of the next three break cycles, a new access address is provided by the Access
Address Counter logic (Paragraph 5.12), and a new test character is placed on the MD lines and compared to the
received character. If a successful comparison occurs between the received character and one (or more) of the
test characters, that fact is retained by a flip-flop in the Detected Character Register logic described in Paragraph
5.15.
During the 5th and 6th cycles of the receive break request data break, the information in the memory location
defined by the access address is the word count and the current address, respectively. The word count and the
current address are placed on the MD lines in turn. During each timing cycle, designated D4 L for WC and D5 L
for CA, NAND gate E34 in the Break Grant logic asserts the DATA 11 L signal. Thus, the DATA+MD to the MB

5-27

operation forced by the BREAK DATA CONT L signal increments both the word count and the current address.
At TP3 time of the CA cycle, the Break Grant logic asserts the LOAD CURRENT ADDRESS L signal. At TP4
time flip-flop E23 is set, causing the ACCESS ADDRESS L signal to be negated, while the CURRENT ADDRESS L
signal is asserted. The combination of the LOAD CURRENT ADDRESS L signal and the CURRENT ADDRESS L
signal causes the current address to be gated through the Current! Access Address Register logic to the MA lines.
During the data transfer cycle, D6 L, the RD TO BUS L signal is asserted in the BRK RQST Receive logic. The
character in the Receive Data Register is gated onto the DATA lines and placed in the memory location specified
by the current address. The data break ends after this timing cycle, and six more SCR-P L pulses must be received
before a new break request can be generated.
If a transmit break request is carried out, only the WC and CA cycles precede the transfer cycle. The same
OMNIBUS control signals are asserted by the Break Grant logic; differences occurring during the transmit operation can be noted in the timing diagram, Figure 5-4.
5.12 ACCESS ADDRESS COUNTER lOGIC
The Access Address Counter logic is shown in Figure 5-14. The logic includes the Increment Enable flip-flop,
E57, the Increment Counter, E52, and a BCD-to-Decimal Decoder, E46.

INI L

DO L

13
11

12 MSB

Dl L

2
E46

3 7~~~7 2
8251
INC
BDC-TO10 CTR 91-------114 g:g6~:~
LSB
4
5 1--.--l15
R RQST L

ACCESS ADD

RESET L

NOTE:
Logic is PIO M839 module

8E-0470

Figure 5-14 Access Add Counter logic

5-28

D2 L
D3 L
D4 L
D5 L
D6 L

D7 L
D8 L
D9 L

When the OMNIBUS INITIALIZE signal is generated, the resulting INI L signal clears the Increment Counter and
the Increment Enable (INC ENA) flip-flop. The BCD output from E52 is 0000; thus, E46 asserts the DO L signal.
Unless a break request is generated, the Increment Counter, the Decoder, and the flip-flop remain in the state
described.
If the DP8-E requests a data break and has highest priority, the TP4 pulse immediately preceding the first data
break cycle (the same TP4 pulse that sets the B R K Grant flip-flop) generates a GTP4 pulse. The resulting
ACCESS ADDRESS RESET L signal from NAND gate E31A sets the INC ENA flip-flop. This signal is also
applied to the count/load input of the Increment Counter, E52. A negative-going signal at this input loads the
counter with the information present at the data inputs, pins 3,4, 10, and 11. If this is a receive data break
operation, the R ROST L signal is asserted and E52 remains in the 0000 output state. However, assume that this
is a transmit data break operation. The R ROST L signal is not asserted. Therefore, E52 is loaded with a BCD
count of 0111; E46 decodes this to assert the D7 L signal. When this signal is asserted, the access address 7727 is
placed on the MA lines by the Current/Access Address Register logic. This is the access address of the word count
location. Thus, the first cycle of the transmit data break operation is the WC cycle.
When the word count has been incremented and returned to memory, TP4 of the WC cycle generates another
GTP4 pulse. Because the first GTP4 pulse sets flip-flop E57, the second GTP4 pulse enables NAND gate E24,
rather than E31. E52 is clocked, the BCD count is incremented to 1000, and E46 asserts the D8 L signal. When
this signal is asserted, access address 7730 is placed on the MA lines and the CA cycle is entered. The address in
location 7730 is incremented to produce the current address. This address, rather than an access address, is
placed on the MA lines at TP4 of the CA cycle. At the same TP4 time, E52 is again clocked, the BCD count is
incremented to 1001, and E46 asserts the D9 L signal. This signal is asserted throughout the data transfer cycle
and is used to gate the data character into the Transmit Data Register, to end the transmit break request (by
negating the TROST L signal), and to clear the INC ENA flip-flop at TP3 time of the transfer cycle. Because a
GTP4 pulse is not generated during the data transfer cycle, the Increment Counter is not clocked at the end of
this cycle. Thus, the data break operation ends with E52 holding the BCD count of 1001 and E46 asserting the
D9 L signal. This condition exists until a new data break operation, either receive or transmit, is initiated.
If the next data break operation is of the transmit type, location 7727 is again addressed to begin the WC cycle.
However, a receive data break request would cause the BCD count in E52 to change from 1001 to 0000 at the
first GTP4 time. Therefore, location 7720, which contains a test character, is addressed by an access address.
At each GTP4 time of the receive data break operation, the Increment Counter is clocked. The decoder asserts
the DO L through D6 L signals in succession. The DO L through D3 L signals are asserted during the four test
character cycles, D4 L is asserted during the WC cycle, and D5 L is asserted during the CA cycle. When D6 Lis
asserted, the current address, which was loaded into the Current! Access Address Register logic during the CA
cycle, is placed on the MA lines. The D6 L signal is asserted throughout the data transfer cycle and enables TP3
of the cycle to clear the INC ENA flip-flop. Because a GTP4 pulse is not generated during the data transfer
cycle, the Increment Cou nter is not clocked at the end of the cycle. Thus, the data break operation ends with
E52 holding the BCD count of 0110 and E46 asserting the D6 L signal. This condition exists until a new data
break operation, either receive or transmit, is initiated.
Note that the INC ENA flip-flop can be cleared in three ways. Two of these have been indicated. The third way
of clearing the flip-flop is by causing a detected character to be stripped_ If a test character and the received data
character are the same, the COMPARE signal is asserted. If the O-bit of the test character is logic 1, the MDO L
signal causes NAND gate E35 to assert the STRIP signal. This signal causes the receive data break operation to
be terminated at the end of the current test character cycle and clears flip-flop E57. E52 and E46 remain in
the state that represents the last cycle completed. For example, if the test character in location 7722 compared
successfully with the received character, the data break operation would be terminated with E52 holding a BCD
count of 0010 and E46 asserting the D2 L signal.
5-29

5.13 CURRENT/ACCESS ADDRESS REGISTER LOGIC
The Current/Access Address Register logic is shown in Figure 5-15. This logic places a memory address on the
OMNIBUS MA lines. Since two types of addresses, Access and Current, are encountered during a data transfer,
a method of selecting one or the other is required. This requirement is fulfilled by the DEC 8235 ICs E48, E21,
and E 1, which are 4-bit logic elements.
The type of address gated to the MA lines by these ICs depends on the control signal that is asserted by the Break
Grant logic. If the CURRENT ADDRESS L control signal is asserted, pin 7 of each IC is low, and the current
address, which is applied to the inverting input of the IC, is placed on the MA lines. On the other hand, if the
ACCESS ADD R ESS L control signal is asserted, pin 9 is low, and the access address, which is applied to the
noninverting input (indicated by the circle), is placed on the MA lines.
An access address is formulated from two sources. The state of each of the first eight bits, MAO through MA7, is
determined by the logic in Figure 5-15. Each of MA bits 0 through 4 is logic 1, since the IC inputs corresponding
to these MA bits are grounded. The user determines the state of each of MA bits 5, 6, and 7 by selectively connecting or removing one or more of jumpers A5, A6, and A7. The selection depends on the channel access
address assignment. For example, if the logic in Figure 5-15 represents Channel 1, access addresses 7720 through
7725, 7727, and 7730 are assigned. Therefore, jumpers A5 and A7 are connected, while A6 is disconnected.
The state of each of the last four bits of the access address is determined in the Access Address Counter logic.
During each data break operation, the Increment Counter in that logic counts from 0000 to 0110 (receive data
break) or from 0111 to 1001 (transmit data break). The count is incremented at the end of each timing cycle of
the data break. For example, consider a receive data break. The Increment Counter holds a count of 0000 just
before the first timing cycle of the data break is entered. Thus, each of MA bits 8 through 11 is logic 0 (the signal
at each noninverting input of E48 is high). The first memory location addressed is 7720. At the end of the first
data break cycle, the Increment Counter is incremented. MA bit 11 becomes logic 1, and the second memory
location addressed is 7721. In this manner, memory locations 7722, 7723, and 7724 are successively addressed.
When the Increment Counter increments to 0101 at the end of the fifth data break cycle, access address 7725 is
placed on the MA lines. The next data break cycle is the CA cycle. During the CA cycle, the current address that
is stored in location 7725 is gated onto the MD lines and incremented. The Break Grant logic asserts the LOAD
CURRENT ADDRESS L signal that loads the current address into the register consisting of the DEC 8271 ICs
E7, E12, and E50. At the end of the CA cycle, the ACCESS ADD R ESS L signal is negated and the CU R RENT
ADD R ESS L signal is asserted. The outputs from the register, which represent the current address, are placed on
the MA lines. Thus, during the next (seventh) cycle a data character is transferred to the memory location specified by the current address.
Note that the contents of the register can be gated to the DATA lines by the S RT A lOT instruction. Th is instruction is used for maintenance and program debugging.
5.14 LOAD FIELD LOGIC
The PDP-8/E basic 4K of memory can be extended inAK increments to a maximum of 32K. Therefore, a 15-bit
address is required to specify completely a memory location. The three most significant bits of the 15-bit address
are carried by the EMA 0, EMA 1, and EMA 2 lines, the EMA 0 bit being the most significant bit.
A data break option can use an extended memory address only when specifying the location that is to take part
in the data transfer. The word count and the current address locations (and test character locations when considering the DP8-E) must be stored in memory field 0, the basic 4K.

5-30

NOTE:
Log ic is PIa M839 module.

3)-- MAIl L

I
2

INCREMENT
COUNTER
BITS

.-n

MDII L

MDIO L

MD9 L

MD8 L

E48
8235

r--

'f
p--IDATA II L

E50
8211

p- DATA 10 L
p- DATA 9 L

E53
8235

1>-'DATA B L
6

4 13

~
+5V

r::r-'
R=>

I>- MA7 L

,-0A1 ~

~A6'"

t:::::=J.

r--

~A5~ ~

I>- MA6 L
E21
8235

p- MA5 L
P-'MA4 L

MD5 L -

MD4 L

_'f

I
Ir- DATA 7 L

I>- DATA 6 L

EI2
8211

to
~

I 10

-.-/

MD6 L. -

MD1 L. -

) - - MA9 L

) - - MAB

r---

10 7

-H=)
H=)

-to

)--1MAIO

V
MSB-~

;r
I

E36
8235

l>- DATA 5 L

p- DATA 4 L
e

6 4 13

p- MA3 L

l>- MA2 L
p- MAl L

CURRENT ADDRESS L I-(

ACCESS ADDRESS L -

EI
8235

o-(

p- MAO L

I-(

MD3 L

MD2 L

MDI L

K=> ...

J
p- DATA 3 L

p- DATA 2 L

E7
8211

EI'
8235

p- DATA I L

p- DATA 0 L

MOO L

LOAD

I 10

K=>
-to

.-~

e 7

6413

CUR~ENT ADDRESS L - U

SRTA L

Y
BE-047t

Figure 5·15 Current!Access Address Register Logic

5·31

Some data break devices can directly address an extended memory field via the EMA lines. However, if such a
field is used with a synchronous modem, the field can be addressed only under program control. The load field
logic, shown in Figure 5-16, enables the programmer to select the memory field to or from which a data character
is to be transferred.

r-.-.-- +3V
REMA

DATA 0 L

13
13

EMA

REMA 1

E 11
74197

DATA 1 L

EI
8235

REMA

EMA 1 L

REMA 2
DATA 2 L

EMA 2 L

.---._._- +3V
REM A L

DATA 3 L

' - - - - - - TEMA L

TEMA 0 L

DATA 4 L

74197
TEMA
TEMA 1

DATA 5 L

TEMA 2 L

TP3 - - - - -.....

SLFL L
NOTE:
Logic is Pia M866module.

8E-0472

Figure 5-16 Load Field Logic

The program can specify a separate field address for the receive data break and the transmit data break operations.
AC Register bits 0, 1, and 2 are loaded with the receive extended memory field address, while AC bits 3, 4, and
5 are loaded with the transmit extended memory field address. These addresses are gated onto the DATA 0-5
lines by the SLF L lOT instruction. At TP3 time of this instruction, these addresses are parallel-loaded into
DEC 74197 shift registers, the receive field address into Ell, and the transmit field address into E2.
If a receive data break operation is being carried out, the Break Grant logic asserts the REMA L signal throughout
the timing cycle in which the received character is gated onto the DATA lines. The REMA L signal gates the
outputs from E 11 onto the EMA lines (the Ell outputs are inverted by selector E 1). Thus, the character gated
onto the DATA lines by the RCV Data Register logic is transferred to a location in the extended memory field
specified by the EMA bits. If the PDP-8/E has only 4K of memory, the EMA bits are logic O.

5-32

The TEMA L signal, asserted throughout the data transfer cycle of a transmit data break operation, gates the
output from E2 onto the EMA lines. Therefore, the character to be transferred to the modem is gated onto the
MD lines from an extended memory field location and shifted onto the SD line by the Transmit Data Register
logic.
5.15 DETECTED CHARACTER REGISTER LOGIC
The Detected Character Register logic is shown in Figure 5-17. The logic is used to generate an interrupt request
if a received character matches a test character, and to identify which test character the received character
matched. For example, assume that the received character compares, bit-for-bit, with the test character stored in
location 7722. This location is addressed at the same time that the D2 L signal is asserted by the Access Address
Counter logic. The D2 L signal is asserted because the Increment Counter in that logic has been incremented to
a count of 0010 (the Increment Counter is included in Figure 5-17 for information).
When the test character in location 7722 is gated onto the MD lines near the beginning of the third data break
timing cycle, the COMPARE signal is asserted in the Receive Data Register logic. At TP3 time NAND gate E42,
Figure 5-17, is enabled. If the O-bit of the test character is logic 0 (i.e., the MDO L signal is logic 0), the received
character is to be stored. NAND gate E56 is enabled. Its output clocks the two E41 flip-flops and sets the
CHAR DET flip-flop via the inverter. The D-input of E41 is high because of the count in the Increment Counter;
therefore, the E41 B flip-flop is set. The E41 flip-flops hold the count of 10 for one character period; i.e., until a
new character has been completely shifted into the Receive Data Register. Note that if the received character is
to be stripped, none of the three flip-flops is set. If the same test character is stored in more than one location,
and if the received character matches this test character and is to be stored, the E41 flip-flops contain the highest
location.
The O-output of the CHAR DET flip-flop can cause an interrupt request to be generated when the data break has
ended. An appropriate program routine is entered, and the SRCD lOT instruction gates the identifying count
onto the DATA 10 and DATA 11 lines for further action.
5.16 INT/SKIP LOGIC
The INT/Skip logic (RING, CARRIER/AGC) is shown in Figure 5-18. The logic enables the RING and
CAR R I E R/ AGC signals to cause program interrupts and/or program instruction skips.
When the DP8-E senses a ringing signal from the modem, it generates a Ring flag, indicating that a modem-tocomputer transmission is to take place. This signal is applied to the interface at pin J 1 X. If a jumper is in place
at location X (the jumper is removed if the modem is a Bell 301 type), NAND gate E18 is disabled. The positive
transition at the output of the gate sets the RING flip-flop. If the interface has been enabled under program
control, setting the RING flip-flop causes NAND gate E19D to assert the OMNIBUS INT RQST L signal. The
computer enters the interrupt servicing routine to determine the identity of the requesting device. The SSRG
instruction in the routine causes the lOT Decoder logic to generate the SSRG L signal throughout TS3 of the
instruction. The SSRG L signal causes NAND gate E19C to assert the OMNIBUS SKIP L signal; thus, at TP3
time the CPU SKIP flip-flop is set and the program instruction following SSRG is skipped. When the SSRG L
signal is negated at the end of TS3, the RI NG flip-flop is cleared. The program proceeds to a subroutine that sets
up the WC and CA Registers and then either waits for the modem to generate a CAR R IE R/ AGC signal or exits
the subroutine.

5-33

DATA 10 L
SRCD L
DATA 11 L

TP3

E52
INC
CTR

9
LSB
5

4 1

NOTE:
Logic is PIa M839 module.

8 6

RRQST L

8E-0473

Figure 5-17 Detected Character Register Logic

INT RQST - - - - - \
RQST L
ENABLE

+5V

J1X

RING

+3V

r--------------~~

SSCA

E1B

~_--i

L--~OI

(J'1

* TP4----\

INI L

~ON
+5V

r -______,

Jl BB
CARRIER IAGC

}---<_ _- - - l ~ OFF

+5V
NOTES:

1. Logic is PIO Ma66 module.
2.* Indicates Omnibus signals.
8E-0474

Figure 5-18 INT/Skip Logic (RING, CARRIER/AGC)

If a computer-to-modem transmission is to take place, a RING signal is not generated. Instead, a program subroutine sets up the registers and then enables the modem SCT L signal to set the RS flip-flop in the Control Word
logic. The setting of this flip-flop causes the interface to generate the SEND ROST signal that is applied to the
modem. The program then either waits for the modem to generate a CAR R IE RI AGC signal or exits the subroutine.
When the modem generates the CAR RI ERI AGC signal, whether a transmit or receive operation, the COl AGC L
signal is applied to Schmitt trigger E5. The output signal from E5 takes two paths; only the path to the ON
jumper is significant when the CAR R IE RI AGC signal is generated at the beginning of a transmission. If the jumper
is in place, NO R gate E 15 is enabled, and its output sets flip-flop E24. The path leading to the OF F jumper is
significant when the CAR RI ER/AGC signal is negated. This happens when TERM READY has been negated by
either receiver or transmitter, or when a modem malfunction has interrupted the data stream. If the jumper is in
place when this occurs, NOR gate E 15 is enabled and flip-flop E24 is set again. Thus, the circuit can respond to
either or both transitions of the CAR R IE RI AGC signal.
When E24 is set, the next occurring TP4 pulse sets the COl AGC flip-flop, and E 19D can assert the INT ROST L
signal. When the SSCA L signal goes low, the SKIP L signal is asserted, and the CPU SKIP flip-flop is set at TP3
time. The SSCA L signal is negated at the end of TS3, causing flip-flop E24 to be cleared. At TP4 time the

COl AGC flip-flop is cleared, causing the INT ROST L signal to go high.
The I NTISkip logic (WC overflow, character detected, and bus error) is shown in Figure 5-19. The logic enables
an interrupt request to be generated when one of the events in the parentheses occurs.
During the WC cycle immediately preceding the last data transfer cycle, the OVERFLOW L signal is asserted by
the CPU. One or the other of AND gates E49A and E49C is enabled, setting either flip-flop E27 or flip-flop E29,
respectively. The a-output of the set flip-flop enables NO R gate E43 to assert the INT ROST signal. This signal
causes NAND gate E19D, Figure 5-19, to assert the OMNIBUS INT ROST L signal. The interrupt request is
recognized by the CPU during the first timing cycle following the data transfer cycle, provided another data break
device does not assume control of the CPU. When the program enters the interrupt servicing routine, either the

SSRO or the SSTO lOT instruction causes the SKIP L signal to be asserted and clears the flip-flop that caused
the interrupt request. The program then proceeds to a subroutine that services the request.
If a test character has been detected in the transmission, the CHAR DET flip-flop is set; the a-output enables
NOR gate E43. When the data break has ended, the SSCD lOT instruction in the servicing routine causes an instruction skip after clearing the CHAR DET flip-flop. The program proceeds to a subroutine to determine the
identity of the detected character.
The third event that can cause an interrupt request is a bus error. If either the TROST L signal or the R ROST L
signal is asserted and a serial clock pulse is received by the interface, the BUS ERROR flip-flop is set. Such an
occurrence indicates that the particular break request was not serviced by the computer because of an overloaded
or inoperative break system. Again, an lOT instruction, SSBE, in the servicing routine causes the SKIP L signal
to be asserted and clears the flip-flop that caused the interrupt request.
5.17 READ STATUS!TEST PULSE LOGIC
The Read Status logic is shown in Figure 5-20. Significant signals in the interface are gated onto DATA lines
a through 7 by either of two control signals, SRS1 Land SRS2 L. The information on the DATA lines is loaded
into the AC Register at TP3 time. The logic and lOT instructions SRSl and SRS2 are intended primarily for
maintenance and program debugging, but can be used to monitor the state of CARRIER, EMA, etc.

5-36

RO FLO L

TOFLO L

INT ROST

I NI L - 4 -......-...;nI

SSTO L _ * _ - . . 1
* SKIP L

SSRO L -

....- - - - '

*OVERFLOW L
La CNTL (0) L

SSCO L

-----..----01
S SBE L --..----d

IN! L
TROST L
SCT-P L
RROST L
SCR-P L

NOTES:
1. Asterisk indicates OMNIBUS signal
2. Logic is PIa M839 module
8E-Q475

Figure 5-19 INT/Skip Logic (Character Detected, Bus Error, WC Overflow)

DATA 7 L

MODEM RDY L
TEMA 2
REMA 2 L

DATA 6 L
E10

8235

TEMA 1
REMA 1 L

DATA 5 L

TEMA 0
REMA 0 L

DATA 4 L

0-------._----- DA TA 3 L

SYNCI L------------+-~a
SY N C 2 L

------------t--t-1:l1

0-------+-._--- DA TA 2 L

Ell

8235
T RQ S T L ------------t--HC'li P/O M839

0-------+-+---.-- DA TAl L

RRQSTL

DATAOL
7

SR S ' L

------------t-_------....J

SR S 2 L -------------~DI

CS----------------------~_4

TERM RDY----------------------~_4

RS(l) ----------------------~~

COl AGC L -"VVv-<_.__--1

NOTE:
Unless noted otherwise, logic is P/O M866 module.
BE-0476

Figure 5-20 Read Status Logic

Another instruction that can be used during maintenance is the SRCD instruction that is normally used to gate
detected character information onto the DATA 10 and DATA 11 lines. When used with the Test Pulse logic,
shown in Figure 5-21, the SRCD instruction can cause a single clock pulse to be generated. This pulse is routed
through a test connector and returned to both the SCR and SCT input lines of the interface, enabling single-step
testing of the receive and transmit circuits.
The ACO bit must be logic 1 when the SRCD instruction is issued. NAND gate E23, Figure 5-21, sets the E23
NOR-gate flip-flop. This flip-flop is cleared by the BTP4 pulse; thus, a negative pulse of approximately 600-ns
width is produced at the emitter of 01 and gated to the emitter of 02, as a positive pulse. If a jumper is in place
at location F, and if the test connector P1 is connected to J 1, the pulse is returned on the SCR and SCT lines
(see Section 5, Maintenance, for further information about the test connector).

5-38

SCR (TEST PULSE)--

SCT (TEST PULSE)--

JIR -

17~

JIN -

F~ J I F F - II

PIO
TEST
CONN. PI
L~JIL
(EXT TIMING)

+15V

I-~

EXT C ~=O C K L

..i

NOTE:
Logic is PIO M866 module

t---+---'
-15V

+6.4V

Figure 5-21 Test Pulse Logic

The four-transistor gating circuit can also be used to gate an external clock to the modem, which has an external
timing mode. The external clock is applied at the input designated EXT CLOCK L (etched on the printed circuit
board as EXT CLOCK), and a jumper must be installed at location L.

5.18 LEVEL CONVERSION CIRCUITS
The M866 Module contains the DP8-E level conversion circuits. Figure 5-22 illustrates the method used to convert
either EIA or current mode signals to the TTL levels required by the DPB-E. The CLEAR TO SEND signal conversion circuit is used as an example.

+5V

CS
CLEAR

SEND

8E- 0480

Figure 5-22 DP8-E Input Circuit (Receiver)

5-39

If the CLEAR TO SEND signal is an EIA-type signal (bipolar), a "mark" is represented by a voltage level of -5V
to -15V; a "space" is represented by a voltage level of +5V to +15V. A mark, which indicates that the CLEAR
TO SEND signal is not asserted, turns off 017, and the CS signal is negated (logic 0); a space turns on 017,
thereby asserting the CS signal.
If the CLEAR TO SEND signal is a current mode signal, a jumper is connected at location C. An input current of
less than 5 mA represents a mark, which indicates that the CLEAR TO SEND signal is negated. 017 is nonconducting, and the CS signal is low. A space is represented by an input current of greater than 23 mA, which produces a base voltage sufficiently high to turn on 017, thereby asserting the CS signal.
Figure 5-23 illustrates the method used to convert the DP8-E TTL signals to either E IA or current mode signals.
The SEND DATA L signal conversion circuit is used as an example.

+15V

6.4V
R1

CE
026

011
Q16

SEND DATA L
012
Q8

T
0 CE
04
025

-6V

-15V
NOTE!
Connect jumper as indicated in table

SIGNAL TYPE

CONNECT JUMPERS
(REMOVE OTHERS)

EIA

E, CE (2)

CURRENT MOOE

CE(2),CT

TTL

T(2),CT

SO L

BE -0481

Figure 5-23 DP8-E Output Circuit (Driver)

The output transistors, 08 and 016, are connected for push-pull operation and are controlled by transistors 07
and 015. As the table in Figure 5-23 indicates,jumpers E and CE are connected forTTL-to-EIA level conversion.
If the SD L signal is high, logic 0, both 07 and 015 are nonconducting. Diode D12 is reverse-biased, while D11
is forward-biased. Thus, 016 connects the SEND DATA line to a voltage that varies between 5V and 15V,
depending on the load.
If the SEND DATA L signal must be current mode, the CE and CT jumpers are connected. If the SD L signal is
high, logic 0, 016 provides the load current of greater than 23 mA, indicating a space condition. When the SD L
signal is asserted, diode D12 is forward-biased; 08 provides the load current of less than 5 mA, indicating a mark

5-40

condition on the SEND DATA line. Note that the CT jumper, by placing D12's plate just below ground rather
than at -6V, changes the operating point of Q8 from what it was during E IA conversion.
Table 5-4 lists the control signals and data signals and relates the two types to mark/space, logic 1/logic 0, etc.
Table 5-5 lists the EIA and current mode specifications for reference.
Table 5-4
Signal Level Terminology
Control Signals

Data Signals

...,
RING
CARRIER/AGC
SCR
SCT
INTERLOCK/DATA SET READY)
CLEAR TO SEND
TERMINAL READY
SEND REQUEST
EXTERNAL TIMING

RECEIVE DATA L}
SEND DATA L

Mark/
Space

High/
Low

Asserted
Not Asserted

Mark

Low

Not Asserted

Space

High

Asserted

Mark
Space

Low
High

Asserted
Not Asserted

Table 5-5
EIA/Current Mode Electrical Specifications
Current mode specifications (applicable to Bell 300 Series Modem, or equivalent).
EIA (RS-232-C) Electrical Specifications
Driver output logic levels with 3K to 7K load

15V> V oh > 5V
-5V > VOl >-15V

Driver output voltage with open circuit

Va < 25V

Driver output impedance with power off

Zo > 300n

Output short circuit current

10 <5A

Driver slew rate

dt< 30V/lls

Receiver input impedance

7 kn > R.In > 3 kn

Receiver input voltage

±15V compatible w/driver

Receiver output with open circuit input

Mark

Receiver output with 300n to ground on input

Mark

Receiver output with +3V input

Space

Receiver output with -3V input

Mark

(continued on next page)

5-41

Table 5-5 (Cont)
E lA/Current Mode Electrical Specifications

::5

W~
&} Logic "0" =Space= Control On

:~ ><~~<~~~~~<~}
~~5 ~~
ffi}

Transition Region

Logic "1" = Mark = Control Off

Current Mode Electrical Specifications (Applicable to the Bell 300 Series Modem or equivalent)
Receiver Input Current/Voltage levels with
100n Termination

Mark

Driver Output Impedance with Power Off

Not Specified

Driver Output Short Circuit Current

Not Specified

Driver Slew Rate between the 7 mA and the
21 mA levels

5mA(-0.7<Ew<1)

Typical 14 mA/100 ns
Maximum14 mA/50 ns
Minimum 14 mA/200 ns

Receiver Input Impedance

120> Z.In >90

Receiver Output with Open Circuit Input

Logic 1 - Mark-Off

Receiver Output with Input> 23 mA

Logic 0 - Space-On

Receiver Output with Input < 5 mA

Logic 1 - Mark-Off

Driver Distortion Limits

Mark to Space or Space to Mark must be achieved
within 25% of bit interval

Receiver Open Circuit Voltage

-O.SV to -1.3V

SECTION 5 MAINTENANCE
General instructions concerning preventive and corrective maintenance are given in Volume 1, Chapter 4. Two
maintenance aids are available when corrective maintenanceof the DPS-E is required. One, the diagnostic program, MAINDEC-OS-DHDPA-A, can help the technician to determine the nature of the problem. The other, a
self-test feature, enables the technician to single-step test both the receive and transmit logic.
To use the self-test feature, the technician must connect the test connector to the plug on the modem side of the
interconnecting cable. The internal wiring of the test connector enables software simulation of the modeminterface signals. Figure 5-24 is a pictorial representation of the signals involved in the self-test feature. Note that
the MS66 "F" jumper and either the "N" or "A" jumper (Table 5-2) must be connected. When the technician
wishes to check the receive or transmit logic, he can, by careful selection of lOT instructions, assert or negate
any of the signals shown in Figure 5-24. The SRCD instruction generates a single clock pulse that is returned on
both the SC Rand SCT lines, thereby enabling all other signals to be generated. See Paragraph 5.16 for additional
information concerning the self-test feature.

5-42

P2
M866
J1

CABLE
BC01V /
*BC05C

PI
F

SEND DATA

J
SCT

f----\

0N0-- N
SCR
060-- R
SELF -TEST PULSE
CLEAR TO SEND
SEND REQUEST

--\

\ - - - - - - - 1 11 )

f----\
f----\

RING
X

I-------------- :: )

f------4

INTERLOCK / DATA SET RDY

--\

T
V

TEST
CONNECTOR
PI

--\
--\

RECEIVE DATA

F
0---0-FF

(MODEM
CONNECTOR)

CARRIER / AGC

f------4

TERMINAL READY

f----\

* Preferred cable

8E-Q479

Figure 5-24 Self-Test Interconnection

When performing corrective maintenance, the technician should refer to the option schematics, E-CS-M839-0-1
and E-CS-M866-0-1, rather than to the logic extracts in this volume. Table 5-6 lists the modem-interface signals
and the corresponding cable connector pin information. Top-connector "H" on the M866 Module, an alternate
input/output connector, is shown in parentheses with the J1 pin number. Table 5-7 lists the M866-M839 Module
interconnecting signals and indicates the source module.
Table 5-6
Modem-Interface Cable Pin Information
Signal Name

J1 (H) M866

P1
40-Pin Berg

P2 (DP8-EA)
25 Pin Cinch

P2 (DP8-EB)
12-Pin Burndy

SEND DATA

F (HE2)

RECEIVE DATA L

J (HF2)

EXTERNAL TIMING

L (HH1)

SCT

N (HH2)

SCR

R (HJ2)

CLEAR TO SEND

T(HK2)

SEND REQUEST

V (HL2)

RING

X (HM2)

No Connection (Bell 301)
F-Shield (Bell 303)

INTERLOCK/DATA
SET READY

Z(HN2)

CARRIER/AGC

BB (HP2)

(continued on next page)

5-43

Table 5-6 (Cont)
Modem-Interface Cable Pin Information
Signal Name

Jl (H) M866

Pl
40-Pin Berg

P2 (DP8-EA)
25 Pin Cinch

P2 (DP8-EB)
12-Pin Burndy

TERMINAL READY

DO (HR2)

No Connection (Bell 301)
M-Shield (Bell 303)

USER FUNCTION
AND SELF-TEST
PULSE

FF (If Jumpered)
(HAl)

USER FUNCTION

JJ (If Jumpered)
(HB1)

FRAME/SIGNAL
GROUND

C
VV (HT1, HC2)

C
VV

25
7

-6V

(HC1)
No Jl Connection

6.4V

(HS2)
No Jl Connection

EXTERNAL TIMING,
TTL LEVEL

(HV2)
No Jl Connection

Table 5-7
M866-M839 Top-Connector Signals
Signal Name

"F" Connector Pin Number

SRCD L
THIS CODE
INT ROST
RD
REMA L
TEMA L
SCR-P L
BREAK GRANT
INI L
GTP4
BREAK ROST
SSBE L
SCT-P L
CS
SO L
IDLE L
ROST
SRS1 L
GROUND

FAl
FBl
FCl
FD1
FEl
FFl
FHl
FJl
FKl
FLl
FM1
FNl
FPl
FR1
FSl
FTl
FUl
FVl
FA2

GROUND

FV2
5-44

Source Module
M839
M866

*
*
*
*

*
*
*
*
*
*
*
*
*
*
*

*
*
*

Table 5-8
Equivalent EIA and CCITT Circuit Designations

P2 (DP8-EA)
Pin Number

EIA Circuit

CCITT Circuit

FRAME/SIGNAL
GROUND

1
7

AA
AB

101
102

PROT!OCTIVE GROUND
SIGNAL GROUND/COMMON RETURN

SEND DATA

103

TRANSMITTED DATA

DP8-E Signal Name

EIA/CCITT Circuit Description

RECEIVE DATA L

104

RECEIVED DATA

SEND RQST

105

REQUEST TO SEND

CLEAR TO SEND

106

CLEAR TO SEND

INTERLOCK/DATA
SET READY

107

DATASET READY

TERMINAL READY

108_2

DATA TERMINAL READY

RING

125

RING INDICATOR

CARRIER/AGC

109

RECEIVED LINE SIGNAL DETECTOR

CG
CH
CI

110
111
112

SIGNAL QUALITY DETECTOR
DATA SIGNAL RATE SELECTOR (DTE)
DATA SIGNAL RATE SELECTOR (DCE)
TRANSMITTER SIGNAL ELEMENT
TIMING (DTE)
TRANSMITTER SIGNAL ELEMENT
TIMING (DCE)

NOT USED
IN DP8-E

EXTERNAL TIMING
(IF JUMPER 'L' IS
CONNECTED)

113

114

SCR

115

RECEIVER SIGNAL ELEMENT
TIMING (DCE)

14
16
19
13

SBA
SBB
SCA
SCB

118
119
120
121

SECONDARY TRANSMITTED DATA
SECONDARY RECEIVED DATA
SECONDARY REQUEST TO SEND
SECONDARY CLEAR TO SEND

USER FUNCTION

SCF

122

SECONDARY RECEIVED LINE SIGNAL
DETECTOR

USER FUNCTION
AND SELF-TEST PULSE

11,18,15 ARE UNASSIGNED.

NOT USED
IN DP8-E

NOT USED IN DP8-E
FRAME/SIGNAL GROUND

9,10,18
25

9, 10ARE RESERVED FOR DATA SET TESTING.

Table 5-8 relates the DP8-E interface signal designations to both the equivalent EIA (RS-232-C) and the equivalent CCITT circuit designations. For example, the DP8-E signal called SEND DATA is brought out to pin 2 of P2
(DP8-EA). The EIA circuit designation for this signal is "BA", while the CCITT circuit designation is "103".

SECTION 6 SPARE PARTS
Table 5-9 lists the recommended spare parts for the DP8-E. These parts can be obtained from any local DEC
office or from DEC, Maynard, Massachusetts.
Table 5-9
DP8-E Recommended Spare Parts
DEC Part Number

Description

19-09667
19-10035
19-09057
19-09931
19-09056
19-09935
19-09934
19-09712
19-09705
19-09704
19-09686
19-09615
19-09854
19-09486
19-09485
19-09004
19-05577
19-05576
19-05575
19-05547
19-09267
19-05578
19-09373

IC 74H74
IC 74197
IC 74Hl0
IC 74H04
IC 74HOO
IC 8235
IC 8266
IC 8242
IC 8881
IC 314
IC 7404
IC 8271
IC 8251
IC 384
IC 380
IC 7402
IC 7420
IC 7410
IC 7400
IC 7474
IC 74H 11
IC 7430
IC 9601

11-00114
11-00113
15-03100
15-03409-2
11-01938
11-00124

Diode, D664
Diode, D662
Transistor, 3009B
Transistor, 7534C
Diode, 114M, 2.4 AZ
Diode, IN750A, 1/4W 4.7J

5-46

Quantity

2
1

3
1
2

5
2

5
4

CHAPTER 6
KG8-E GENERATOR/DETECTOR

SECTION 1 INTRODUCTION
The KGS-E BCC Generator/Detector option consists of a single quad module that plugs into the PDP-S/E
OMNIBUS. The option operates under program control to provide the computer with a parity-check capability.
Although intended to be used with data communication equipment, the option is independent of such equipment
and can be used with other devices.
Parity checks are carried out in the KGS-E on data characters that are transferred from the PDP-S/E memory by
a programmed I/O transfer. The KGS-E can perform three types of parity checks: a vertical redundancy check
(VRC) can be performed on a 6-, 7-, or S-bit character; a longitudinal redundancy check (LRC) can be made on a
message consisting of 6-,7-, S-, 12-, or 16-bit characters; and a cyclic redundancy check (CRC) can be carried out
on a message consisting of 6-, S-, 12-, or 16-bit characters. A VRC can be performed separately or as part of either
an LRC or a CRC.
Publications and documents that are relevant to the KGS-E are:

a.
b.
c.
d.

PDP-8IE & PDP-81M Small Computer Handbook - DEC, 1972
PDP-8IE Maintenance Manual, Volume 1
KGS-E Diagnostic Program, MAl NDEC-SE-DSCA
DEC Engineering Drawing, E-CS-MSS4-0-1.

SECTION 2

INSTALLATION AND CHECKOUT

The KGS-E option is installed on site by DEC Field Service personnel. The customer should not attempt to
unpack, install, checkout, or service the equipment.
Insert the module in the PDP-S/E OMNIBUS. See Table 2-3, Volume 1, for information concerning recommended
module priorities (the KGS-E is a "non-memory" option).
The KGS-E can be checked for correct operation by running the diagnostic program. If maintenance is necessary,
refer to Chapter 4, Volume 1.

6-1

SECTION 3 PARITY CHECK/BLOCK DIAGRAM
6.1

PARITY CHECK

The three types of parity checks performed by the KG8-E are VRC, LRC, and CRC. A general description of
each type follows.
6.1.1

VRC Parity Check

A VRC is carried out on each character of a message. The summation of all logic-1 bits within the character
must be even or odd, whichever is desired. The KG8-E examines each character: when the character is part of a
message that is to be transmitted to some external device from memory, the option adds a parity bit (logic 1), if
one is needed; when the character is part of a message transmitted from an external source to memory, an errordetecting software routine is entered, if the character does not exhibit the correct parity. In one instance parity
is generated; in the other, parity is tested. Although each operation is different, the terms VRC and parity check
are used to refer to either operation. The logic implementation of a VRC is detailed in Paragraph 6.5.
6.1.2 LRC Parity Check
A distinction similar to that expressed in the preceding paragraph is unnecessary when either an LRC or a CRC is
performed. Each of these parity checks is the same, regardless of the direction of the message transfer. The LRC
parity check is based on the accumulation of a block check character (BCC). The KG8-E generates this BCC by
Exclusive-DRing the contents of corresponding bit positions in each character of the message. For example,
consider a message consisting of the following four 8-bit characters:
MSB
Character 1
Character 2
Character 3
Character 4

LSB

o 1 1 000 1 0
001 000 1
1100000
001 101 0

o0 0 1 0 0 1

BCC

If one Exclusive-DRs corresponding bit positions, the BCC shown results. Figure 6-1 illustrates how ExclusiveDRing is implemented by the KG8-E logic; the chart shows the state of the BCC Register at various stages of BCC
accumulation for the four characters.
The first character is parallel-loaded into the Parity Register from the DATA lines by a program instruction.
Clock pulses shift the character into the BCC Register (although shown as an 8-bit register, for convenience, the
BCC Register is 16 bits in length; characters are loaded into the register in a right-justified format). With each
clock pulse, the bit in the LSB position of the Parity Register is Exciusive-ORed with the bit in the LSB position
of the BCC Register. The result is shifted into the MSB of the BCC Register by the next clock pulse. Eight clock
pulses shift the entire character into the BCC Register. The second character is then loaded into the Parity
Register, although an appreciable amount of time might pass before this happens (because data transfers between
the KG8-E and memory are of the programmed I/O type, the operation can be interrupted by program interrupts
or data breaks after each character transfer).

6-2

~~~~~~~--------------------------------------~
8E- 0482.

CHARACTER 1: 01100010
CHARACTER 2: 10010001
CHARACTER 3: 11100000
CHARACTER 4: 10011010
CHARACTER/BIT LOADED

C8
0
0
1

C9
0
0
0

BCC REGISTER CONTENTS
C14
C10
C11
C12
C13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

CLOCK PULSE

C15
0
0
0

CHARACTER 1, BIT 1
CHARACTER 1, BIT 2

START
1
2

CHARACTER 1, BIT 8
CHARACTER 2, BIT 1
CHARACTER 2, BIT 2

8
9
10

1
0
1

1
1
0

0
1
1

0
0
1

1
1

0
0

0
1
0

CHARACTER 2, BIT 8
CHARACTER 3, BIT 1
CHARACTER 3, BIT 2

16
17
18

1
1
1

0
1
1

0
0
1

1
0
0

1
1
0

CHARACTER 3, BIT 8
CHARACTER 4, BIT 1
CHARACTER 4, BIT 2

24
25
26

0
1
0

0
0
1

0
0
0

1
0

0
0
1

1
0
0

1
1

0
1
0

CHARACTER 4, BIT 8

~
I

BCC

Figure 6-1 LRC BCC Accumulation for Four 8-Bit Characters

When all four characters have been shifted into the BCC Register (32 clock pulses), the result in the register is the
BCC. If the message is to be transmitted from memory, the BCC is transmitted as the last character of the
message. Similarly, if the message was received from an external device, the four characters already considered
are followed by a BCC that was generated in the transmitting device. The BCC is treated as a character and loaded
into the Parity Register. When it has been shifted into the BCC Register by eight clock pulses, the register contents will be zero, if the message has been received free of error. If not, an error detecting software routine is
entered by the computer.

6-3

Note that there is no reason why a VRC cannot be performed before an LRC (or before a CRC, for that matter).
Such a procedure enhances the error-detecting capability provided by the KG8-E. In such a case, bit position 0
or 7 of the example would contain the parity bit. Although the example illustrates the LRC BCC accumulation
for an 8-bit character, the LRC can be carried out for 6-,7-,12-, and 16-bit characters, as well. The procedure is
the same, as will be demonstrated in Paragraph 6.8.
6.1.3 CRC Parity Check
A CRC is also based on the accumulation of a BCC; however, the generation of the BCC is more intricate than
during an LRC. A number of different CRC codes can be used, but the KG8-E implements only two, viz.,
CRC-12 and CRC-16. Unlike LRC, CRC concepts are best understood through a mathematical background,
followed by a description of the logical implementation of the mathematics.
A CRC code message consists of a specific number of data bits and a BCC that is generated by the KG8-E. Let n
equal the total number of bits in the message and k equal the number of data bits; then, n-k equals the number of
bits in the BCC. The code message is derived from two polynomials that are algebraic representations of two
binary words. The generator polynomial, P (X), reflects the type of code used (CRC-12, CRC-l6), and the message polynomial, G (X), represents the string of serial data bits. The polynomials are usually represented algebraically by a string of terms in powers of X, as Xn+ ... +X3+X2+X+l. In binary form, a 1 is placed in each position
that contains a term; the absence of a term is indicated by a O. The convention followed in this manual is to
place the LSB (XO, or 1) at the right. For example, if a polynomial is given as X4+ X+l, its binary representation
is 10011 (third and second degree terms are not present).
Given a message polynomial, G (X), and a generator polynomial, P (X), the objective is to construct a code
message polynomial, F (X), that is evenly divisible by P (X). This is accomplished as follows:
a.

b.
c.
d.

Multiply the message, G (X), by X n.k , where n-k is the number of bits in the BCC.
Divide the resulting product, X n-k G (X), by the generator polynomial, P (X).
Discard the quotient; add (bi nary addition) the remai nder, C (X), to the product of Step a.
The result is the code message polynomial, F (X), represented by xn-kG (X)+C (X).

The division is performed in binary without carries or borrows. In this case, the remainder is always one bit less
than the divisor. The remainder is the BCC, and the divisor is the generator polynomial. Thus, the bit length of
the BCC is always one less than the number of bits in the generator polynomial. A simple example is carried out
in the following steps:

Given: Message polynomial, G (X) = 110011 (X 5 +X 4 +X+1)
Generator polynomial, P (X) = 11001 (X 4 +X3+1)
G (X) contains 6 data bits; P (X) contains 5 bits and yields a BCC of 4 bits; thus, n-k=4.

Multiplying G (X) by X n-k gives
Xn-kG (X) = X4 (X 5 +X 4 +X+l) = X9+X8+X5+X4
The binary equivalent of the product is 1100110000.

Dividing the product by P (X) gives
100001 +- Quotient
P (X) -+ 11001 11100110000 +- Xn-kG (X)
11001
10000
11001
1001 +- Remainder=C(X)=BCC
(continued on next page)

6-4

Adding the BCC to the product of Step b. gives
F (X) = 1100111001

The code message polynomial is transmitted. The receiving station divides it by the same generator polynomial.
If there is no error, the division produces no remainder. A remainder indicates an error. The result of the division
is shown below, with the result indicating an error-free message.

P(X)->11001

100001
\1100111001 +11001
11001
11001
00000 +-

F(X)

Remainder of a

A more practical example, the mathematical derivation of a CRC-12 BCC, is now detailed. This example derives
the BCC of a 2-character message. The KG8-E logic implementation of the mathematics is then presented.
The message characters are: character 1, 000 000 000 101; and character 2, 000 000 001 000 (PDP-8/E convention is followed throughout; i.e., LSB position is on the right). When a character is transferred to the KG8-E
from memory, the LSB of character 1 is the first bit shifted into the BCC Register. Therefore, G (X) = X 15 +X2+1
(000 000 001 000 000 000 000 101). P (X) for CRC-12 is X12+Xll +X3+X2+X+1 (1100000001111). The BCC
is always one bit less than the P (X); thus, the quantity n-k is 12. Because of the way that the KG8-E implements
the mathematical derivation, the message polynomial, G (Xl, is modified and re-designated G' (X). The modification merely reverses the order of the character bits of G (X). Thus, G' (X) in this example is X 23 + X21 + X 8
(101 000 000 000 000 100 000 000). The quantity G' (X)X n .k = (X 23 +X 21 +X8) X12 = X35+X33+X20. The long
division of G' (X)X n -k by P (X) follows.
110 000 000 111 100 111 001 100

11 0000000 1111

I 101 000 000 000 000 100 000 000 000 000 000 000

11 a 000 000 111 1
11 000 000 111 1a
11 000 000 011 11
100 010 100 000
110000000 1111
10 010 100 111 10
11 000 000 011 11
1010 100 100010
1100000001111
110 100 101 1010
11 a 000 000 111 1
100 101 010 100 a
11 a 000 000 111 1
10 101 010 011 10
11 000 000 011 11
1 101010 000 010
1 100 000 00 1 111
1010 001 101 000
1100000001111
110001 100 111 a
110000000 1111
001 100 000 100 +- BCC

t
LSB

6-5

The remainder is the BCC of the two-character message. Note that the LSB is on the left. The BCC is logically
added to the quantity G' (X)X n-k (MSB is added to MSB) to obtain the code message polynomial, F (X), as
shown below.

The F (X) is transmitted. The receiving station divides the F (X) by the P (X). An errorless transmission results
in a remainder of zero (this division is not shown; the reader can verify the fact that the division produces a zero
remainder).
Figure 6-2 is a representation of the BCC Register in its CRC-12 configuration (the configuration is different for
CRC-16). The accompanying chart indicates the content of the register after selected bits of the two example
characters have been shifted into the register (space limitations prevent each step from being shown). The bit in
the LSB position of the character is Exciusive-ORed with the bit in the LSB position of the BCC Register. The
result is either shifted directly into the register or Exclusive-ORed again and then shifted.

Either way, the shift

takes place after the Exclusive-O R has been accomplished. The chart carries the process through 36 clock pulses.
The first 24 pulses shift the two characters into the register. After the 24th clock pulse, the BCC has been
accumulated, as shown. Note that the LSB is on the right.
If the message is to be transmitted, the BCC is added to the G' (X)Xn-k, as indicated earlier; then, the F (X) is
transmitted. However, if the message was received from an external source, the two characters are followed by
the BCC computed by the external device. In this case, the BCC is shifted into the KG8-E BCC Register by the
next 12 clock pulses, as illustrated in the chart. The result, zero, indicates no error in the transmission.
The procedure is the same for CRC-16, except that the P (X) is different. The BCC Register logic is manipulated
by control signals to implement the mathematical derivation. The logic is explained in detail in Paragraph 6.8.
6.2 BLOCK DIAGRAM
The block diagram of Figure 6-3 presents the various logic sections of the KG8-E and illustrates their interrelationship. A detailed discussion of each section follows the block diagram description.
The lOT Decoder logic decodes bits MD3-11 to generate the lOT signals shown in the figure (see Table 6-1 for
a complete list of the KG8-E lOT instructions). The type of parity check carried out by the KG8-E is determined,
basically, by the lOT instruction issued, viz., RCCV, RCGB, or RCTV. The way that the selected type of check
is performed is determined by control signals generated in the Control Register logic.
The Control Register logic is loaded from the AC Register, via DATA lines 5-11, by the RCLC instruction. This
instruction is issued before the type of parity check is selected. The control signals generated in response to the
RCLC instruction determine how the parity check is carried out: the PAR ITY signals (2 signals) determine where
a generated parity bit is placed in a character during a VRC; the VRC (RCGB) signals (3 signals) are generated
when a VRC is to be carried out along with an LRC/CRC; the CRC/LRC (0) signal manipulates the BCC Register
so that either an LRC or a CRC is carried out; finally, the BIT signals select the BCC Register configuration and
the number of clock pulses per burst appropriate for the message character bit length.
A character is transferred from the AC Register, via DATA lines 4-11, to the VRC logic in response to either an
RCCV instruction or an RCGB instruction. If a VRC check (as opposed to a test) is carried out, the generated
parity bit and the character are returned to the AC Register, again on DATA lines 4-11. The COMPUTE VRC
signal is asserted and applied to the I/O XFER logic to control CPU timing during the return transfer. If a VRC
test is performed, the character is not returned to the AC; rather, the PA R ITY signal is used to check that the
character exhibits the correct parity.

6-6

SER IAL INPUT
FROM PAR ITY
REGISTER
BE-0483

MSB

LSB

CHARACTER 1: 000000000101
CHARACTER 2: 000000001 000
CLOCK
PULSE

SERIAL
FEEDBACK
INPUT

Cl0

Cll

C12

C13

C14

C15

1
2
3

0
1
1
0

0
1
0
1

0
1
0
0

0
0
1
0

0
0
0
1

0
0
0
0

0
1
1
0

1
0
1
0

1
1
0
0

11
12
13
14
15
16

1
1
1
0
0
1

0
0
0
1
0
1

0
1
1
0
1
1

0
1
0
1
0
0

1
0
1
0
1
0

0
1
0
1
0
1

0
0
1
0
1
0

0
0
0
1
0
1

0
0
0
0
1
0

1
0
0
0
0
1

0
1
0
0
0
0

1
1
0
0
0
1

0
0
0
0
1
0

1
1
0
0
1
1

23
24

0
0

1
0

0
0

1
0

1
1

0
1

0
0

25
26
27

0
0
0

0
0
1
0
LBCC
1
0
0
0
0
0

0
0
0

0
0

1
0

0
1
1

0
0
1

0
0
0

32
33
34
35
36

0
0
0
0
0

1
0
0
0
0

0
1
0
0
0

0
0
0
0
0

NOTES:
1. 0 = BCC Register Stage; C-Number refers to the bit used (see Paragraph 6.8)
2. EB = Exclusive-OR operation

3. P (X) = X12+Xl1+X3+X2+X+1
Figure 6-2 CRC BCC Accumulation for Two 12-Bit Characters

6-7

1
0
0

0
0
0
0

DATA 0-11 L

,,,. H'1

TP3

I
I
BCC PARITY

YRC
LOGIC

LEFT PARITY

PAR ITY
BCC

RIGHT PARITY

LOGIC

YRC (RCGBl! 1)
CONTROL
REG I STER
LOGIC

COMPUTE YRC

YRC (RCGBIIO), YRC TEST (RCGBII1)
6,7, 8,12,16 BITS L
CRCI LRC (0)

DATA 5-11 L - - 0 >

6,7,12 BITS L

L
INTERNAL IIO L

liD PAUSE L
MD 3-11 L
TS2 L

----

9.5 MHZ

"ocr

CLiCK
RCCY L, RCGB L

lOT
DECODER
LOGIC

RCRL L, RCRH L, RCCB L
RCGB L, RCTC L
RCRH L, RCRL L

BCC
CLOCK
LOGIC

RCGB L, RCTY L

4
1/0
XFER
LOGIC
~

t----l-

t
CO, Cl L
I

.:~__________________________________________________________~

SKIP L
NOT LAST XFER L -

BUS STROBE L.r----------------------------------------------------------------8E-0484

Figure 6-3 KG8-E Block Diagram

Table 6-1
KG8-E lOT Instruction List
Octal Code

Mnemonic

Function

6110

RCTV

Test VRC and Skip. If the VRC logic is wired for an odd
parity check, the next program instruction is skipped when
the character exhibits odd parity; if the logic is wired for an
even parity check, the next program instruction is skipped
when the character does not exhibit even parity.

6111

RCRH

Read BCC high. Jam-transfers the 8 most significant bits
of a BCC to AC4-11 (the MSB goes to AC4); used for a
16-bit accumulation.

6112

RCRL

Read BCC low. Jam-transfers the BCC to the AC Register.
The number of bits involved depends on the type of parity
check performed. The LSB of the BCC is transferred to
AC11.

6113

RCCV

Compute VRC. Transfers a character from AC4-11 to the
Parity Register and clears the AC; causes the VRC logic to
check for odd or even parity and add a parity bit to the
character if necessary; returns the character to the AC with
the parity bit being jammed into either AC4 or AC11.

6114

RCGB

Generate BCC. Generates an LRC or CRC BCC; the BCC is
either transmitted as part of the message or compared to a
BCC that has been received. This instruction causes the
RCTV and RCCV operations to be carried out before the
BCC generation, providing the Control Register logic has
been properly programmed (see the RCLC instruction).

6115

RCLC

Load Control Register. Defines the type of parity check
carried out, and programs the logic for the correct number of bits per character. See the Control Register logic,
Paragraph 6.4, for the relation between AC bit and Control
Register function.

6116

RCCB

Clear BCC Register. Clears the 16-bit BCC Register.

6117

RCTC

Maintenance Test Clock. If test point DA 1 on the module
is grounded, this instruction causes a single clock pu Ise to
be applied to the logic; the technician can use this pulse for
single-step testing of the KG8-E.

When a CRC/LRC follows the VRC, or when such a check is performed alone, each character is first loaded into
the VRC logic Parity Register. 9.5 MHz clock pulses shift the character from the VRC logic, via the BCC parity
line, to the BCC logic. A BCC is accumulated in the BCC Register in either CRC or LRC format. The generated
BCC is transferred to the AC Register on DATA lines 0-11 in a format determined by the type of check performed and by the number of bits per message character. The transfer is directed by either the RCR L instruction
or the RCR H instruction, or both.

6-9

SECTION 4 DETAILED LOGIC
6.3 lOT DECODER LOGIC
The lOT Decoder logic is shown in Figure 6-4. Bits MD3-8 are gated with the I/O PAUSE L signal to generate
the 611 X signal. NAND gate E3 asserts the OMNIBUS I NTERNAL I/O L signal, causing the positive I/O bus
interface to ignore the lOT instruction. During TS3, the 611 X signal is gated with bits MD9-11 in the 8251
BCD-to-decimal decoder to produce the listed lOT signals.

TS2 L

I/O PAUSE L - f - - - - - - - < 1
M 03 L --i--<1

M 04 L

------,i---Q-....,

M 0 5 L -f-------Q
M 06 L -f---<1

M 07 L -+---<1--'

1 > - - - - - INTERNAL 1/0 L

MOB L - - - - - - - d

6E-0485

Figure 6-4 lOT Decoder Logic

6.4 CONTROL REGISTER LOGIC
The Control Register logic is shown in Figure 6-5. The logic includes seven flip-flops and a BCD-to-decimal
decoder, E8. When the RCLC lOT instruction is issued, the information in the AC Register is gated onto the
DATA lines during TS2; the information remains on the lines for the rest of TS2 and throughout TS3. At TP3
time, all seven flip-flops in the logic are clocked. The resulting state of each flip-flop depends on the state of the
appropriate AC Register bit. The AC Register bits are related to the control signal functions as follows:
AC5 = 1: CRC BCC
0: LRC BCC
AC678
000 16-bit BCC
001 12-bit BCC
010 8-bit BCC
o 1 1 7-bit BCC
100 6-bit BCC
AC9 = 1: Generated parity bit to ACll
0: Generated parity bit to AC4
AC10 = 1: A VRC check (RCCV) is performed prior to a BCC accumulation.
AC11 = 1: A VRC test (RCTV) is performed prior to a BCC accumulation.

6-10

CRClLRC (0)

RCLC L
TP3

MSB

DATA 5 L

16 BITS L

12 BITS L
E8
8251
DATA 6 L
8 BITS L

7 BITS L

6 BITS L

DATA 7 L
LSB

DATA 8 L -+---(1

r - - - - - - - - - - - - - - - LEFT PAR ITY
r - - - - - - - - - - - RIGHT PARITY

DATA 9 L -+-<f----..,

~--------+-------------------~

r - - - - - - - - - - - - - - VRC (RCGB)(O)
, - - - - - - - - - - - - VRC (RCGB)(1)

DATA 10 L -+----<:1

r - - - - - - - - - - - VRC TEST (RCGBI( 1)

DATA 11 L --1---<1

8E-0486

Figure 6-5 Control Register Logic

6-11

6.5 VRC LOGIC
The VRC logic is shown in Figure 6-6. The logic includes an Exclusive-OR circuit, comprising gates E16, E20,
and E1, and jumper locations E and 0, and an 8-bit Parity Register, comprising ICs E14 and E34. Both the
Exclusive-OR circuit and the Parity Register are used when an RCCV instruction is issued. This instruction causes
a character to be gated from the AC Register onto the DATA lines. The Exclusive-OR logic examines the character and generates a parity bit, if one is required. The character and the parity bit are then loaded into the Parity
Register (the parity bit is loaded into either bit position 4 or bit position 11). gated from the register onto the
DATA lines, and returned to the AC Register.
Only the Exclusive-OR circuit is used when an RCTV instruction is issued. This instruction also causes a character
to be gated from the AC Register to the DATA lines and examined by the Exclusive-OR circuit. However, a
parity bit is not generated, and the Parity Register is not loaded. Rather, the I/O Transfer logic monitors the
PARITY signal to determine if a program instruction must be skipped (Paragraph 6.7). Thus, the RCCV instruction is used to provide the correct parity for characters that are to be transmitted from memory; conversely, the
RCTV instruction is used to check the parity of characters that have been received and stored in memory (the
term "a VRC" is used to indicate the execution of either an RCCV or an RCTV instruction). The RCTV instruction logic is described in Paragraph 6.7; the discussion that follows details how the VRC logic provides the correct
parity for characters destined for transmission.
A VRC can be performed independently or in conjunction with either an LRC or a CRC. If only a VRC of a
character is to be made, the program issues an RCCV lOT instruction. This instruction gates the character from
the AC Register onto the DATA lines and causes the lOT Decoder logic to generate the RCCV L signal. This
signal enables NOR gate E28 (Figure 6-6) to assert the COMPUTE VRC signal and causes the Parity Register to
be placed in parallel-load mode (pin 13 of both E 14 and E34 is taken low).
The VRC flip-flop in the Control Register logic will have been set or cleared by a previous RCLC instruction.
Therefore, either the LEFT PARITY signal or the RIGHT PARITY signal is high when the COMPUTE VRC signal is asserted. This discussion assumes that the LEFT PARITY signal has been asserted; thus, the character bits on
DATA lines 5-11 are gated to the parallel-load inputs of the Parity Register and to the Exclusive-OR circuit,
which checks for odd or even parity (the state of the DATA 4 line is immaterial, because NAND gate EgA is
disabled). The discussion assumes that an odd-parity check is desired; thus, jumper 0 is connected. If the character contains an odd number of 1s in bits 5-11 (odd parity), the PAR ITY signal is asserted; the DATA 4-bit
input of E 14 (pin 3) is low, i.e., a parity bit need not be added to the character. However, if the character contains an even number of 1s in bits 5-11, the PAR ITY signal is negated. AND-NOR gate E32B is enabled, and
pin 3 of E14 is high. The Parity Register is loaded with an odd number of 1s, a parity bit being loaded into the
bit 4 position.
If an even-parity check is desired, the E jumper, rather than the 0 jumper, is connected; if the character gated
from the AC Register contains an odd number of 1s, a parity bit is added. The parity bit can be loaded into the
bit 11 position if the RIGHT PARITY signal, rather than the LEFT PARITY signal, is asserted.
The Parity Register is loaded at TP3 time of the RCCV instruction, on the leading edge of the pulse at pin 6 of
both E14 and E34. At the same TP3 time, but on the trailing edge, the VRC XFER CNTL flip-flop is set, gating
the character in the Parity Register onto the DATA lines. The character is gated to the AC Register and loaded
into the register at BUS STROBE time (see Paragraph 6.7 for details).

6-12

+5V
+3V

LEFT PARITY L - - - - - ,

DATA 4 L

DATA 5 L

DATA 6 L

DATA 7 L

DATA B L
DATA 8 L

DATA 9 L
DATA 9 L
DATA 10 L
DATA 10 L

DATA 11 L
RIGHT PARITY

9.5 MHZ CLOCK

BCC PAR ITY

TP3

RCCV

VRC _ _ _ _ _~
(RCGS) (1)
RCGS L

BE-0487

Figure 6-6 VRC Logic

As noted earlier, a VRC can be performed in conjunction with either an LRC or a CRC. The VRC (RCGB) flipflop in the Control Register logic must be set by an RCLC lOT instruction. Then, an RCGB instruction causes
the lOT Decoder logic to generate the RCGB L signal. This signal causes the COMPUTE VRC signal to be generated (via NAND gate E28 and NOR gate E28) and the Parity Register to be placed in the parallel-load mode.
Thus, the VRC is carried out in the same way as the RCCV instruction. However, after the character in the
Parity Register has been gated to the AC Register and loaded, the same character must be transferred to the BCC
Register so that a BCC can be computed. When the RCGB L signal goes high, pin 13 of both E14 and E34 goes
high, placing the Parity Register in the right-shift mode. The BCC Clock logic (Paragraph 6.6) begins generating
9.5 MHz clock pulses; each pulse shifts the Parity Register. As a bit is shifted out of the Parity Register, it is
shifted into the LSB position of the BCC Register. After eight clock pulses, for example, the character has been
shifted out of the Parity Register and into the BCC Register. Figure 6-7 is a timing diagram that includes the
important signals of the VRC logic. Some of the signals shown have yet to be explained in detail; however, this
diagram is helpful in understanding VRC logic operation.

I/O PAUSE L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----'

TS3 L

________________~r_

TP3 _ _ _ _ _ _ _ _ _ _~r___l~

_________

RCCV L - - - - - ,
• RCGB L

COMPUTE VRC _ _ _ _...I

VRC X FER CNTL (1) _ _ _ _ _ _ _ _ _ _ _ _---'

NOT LAST XFER L

________________--;~L~

BUS STROBE L

CO L. CI L

-------------(1

L-j-DATA TO AC

'-1---

Jm_;~~""'""::::

PA RITY

,::,;:,,:~','~:::::::::::~
PARITY REG TO DATA L1NES ...........1

LSU

"9.5 MHz CLOCK

"BCC REGISTER BITS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~"'""""'"'"'"''''"''''''"'"

"IF A BCC ACCUMULATION FOLLOWS THE VRC.
8E-0488

Figure 6-7 VRC Logic Timing

6-14

If the VRC (RCGB) flip-flop in the Control Register logic is not set by an RCLC instruction, the COMPUTE VRC
signal cannot be asserted when the RCGB instruction is issued (NAND gate E28 is disabled). Thus, a VRC is not
performed; rather, an LRC or a CRC, alone, is carried out, and the VRC logic is used as the input network for the
BCC logic. When the RCGB instruction is issued, it causes a character to be placed on the DATA lines. Neither
the LEFT PARITY L signal nor the RIGHT PARITY L signal is asserted; consequently, the character bits on
DATA lines 4-11 (if the character contains eight data bits) are gated to the Parity Register inputs, and the output
of the Exclusive-OR circuit is ignored by the logic. As before, the register is parallel-loaded at TP3 time; however,
because the VRC XFER CNTL flip-flop is not set, the register outputs are not gated onto the DATA lines. When
the RCGB L signal goes high, 9.5 MHz clock pulses begin shifting the Parity Register contents to the BCC Register.
6.6 BCC CLOCK LOGIC
The BCC Clock logic is shown in Figure 6-8. The logic generates clock pulses that shift both the Parity Register
and the BCC Register. Figure 6-9 is a timing diagram that helps explain the logic operation.

+3V

13
12

3
E2
74197
10

12 BITS L

6 BITS L

7 BITS L
}(}--.--9.5MHz
CLOCK

ReGB L

BE-0489

Figure 6-8 BCC Clock Logic

6 BITS L __________________________________________________________

RCGB L

lL.____________________

....J

E43. P12

E40, P3 ______________________

9.5MHZ CLOCK

MSB

l'--____________________________________~
6E-Q490

Figure 6-9 9.5 MHz Clock Pulse Generation

6-15

The logic includes a 4-bit binary counter, E2, and a free-running multivibrator, comprising NAN D gates E43 and
E40, and the RC network. The binary counter is preset with a count that is determined by the signals at the
parallel inputs. Figure 6-9 indicates that the 6 BITS L signal has been asserted by the Control Register logic.
Thus, when the RCGB L signal goes low, E2 is preset with a binary count of 0010. When the RCGB L signal goes
high, the free-running multivibrator is triggered. The multivibrator output alternately enables and disables ANDNOR gate E31, thereby producing clock pulses at a frequency of approximately 9.5 MHz. Six clock pulses advance
the binary count in E2 to 1000, at which count the MSB signal is asserted. This signal cuts off the multivibrator
and no more clock pulses are generated.
The RCTC L signal is generated by the lOT Decoder logic when the maintenance test clock instruction, RCTC, is
issued. If test point DA 1 is grounded, the RCTC L signal causes a single pulse to be produced; thus, single-step
testing of the BCC generating logic is possible.
6.7 I/O TRANSFER LOGIC
The I/O Transfer logic is shown in Figure 6-10. The logic asserts OMN IB US control signals to enable transfers of
data characters and BCCs from the KG8-E to the AC Register. In addition, the logic is used to assert the
OMNIBUS SKIP L signal when odd parity is detected during a character parity test (RCTV).

E44B b----~---------NOT LAST XFER L
,-------.-~

BUS STROBE L
CO M PUTE V RC ----40-----+-----'
TP3

RCR L L - - - - - - - - - - - - - - c j
RCRH L--------------~

C1 L

CO L
VRC (RCGB)(O) -~------1

RCGB L
VRC TEST(RCGB) (1) - - - - - - - 1
RC TV L - - - - - - - - - - - '
PAR I TY - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1

SKIP L
8E-0491

Figure 6-10 I/O Transfer Logic

When a VRC is performed on a character transferred from the AC Register (as a result of an RCCV instruction or
an RCGB instruction), the character and the parity bit must be returned to the AC from the Parity Register. In
normal operation, the AC Register is loaded at TP3 time. However, the Parity Register outputs are not gated
onto the DATA lines until TP3 time; consequently, with normal computer timing, the information on the DATA
lines would appear at the AC Register data inputs too late to be loaded into the register. The I/O Transfer logic

6-16

solves this difficulty by asserting the NOT LAST XFER L signal. This signal prevents the AC Register from being
loaded at TP3 time; instead, the register is loaded when the I/O Transfer logic asserts the BUS STROBE L signal
(see Volume 1, Section 6, for more details).
The timing diagram of Figure 6-7 demonstrates how the NOT LAST XFER L signal affects the character transfers
from the Parity Register. The NOT LAST XFER L signal is asserted by NAND gate E44B, Figure 6-10, when the
VRC logic asserts the COMPUTE VRC signal. At TP3 time (trailing edge), the VRC XFER CNTL flip-flop is set,
gating the Parity Register outputs onto the DATA lines (see VRC logic) and causing E44B to negate the NOT
LAST XFER L signal. At the same time, both the CO L signal and the C1 L signal are asserted, via NOR gate E43,
and NAND gate E4 is enabled. The output of E4 rises exponentially until, approximately 200 nanoseconds later,
it causes the BUS STROBE L signal to be asserted. Because the C1 L and CO L signals are asserted, the BUS
STROBE L signal jam transfers into the AC the information on the DATA lines. The long delay in asserting the
BUS STROBE L signal ensures that the AC Register input lines have settled before the register is clocked.
When an LRC or a CRC is performed on a message, the generated BCC must be transferred to the AC Register.
This is accomplished by the RCRL instruction, alone, or by both the RCRL and RCRH instructions. Either
instruction generates a signal that enables NO R gate E43. The output of this gate enables NAN D gates E25C and
D to assert the C1 L and CO L signals. The BCC is gated onto the DATA lines and jam transferred into the AC
Register at TP3 time of the RCR Lor RCRH instruction (the BUS STROBE L signal is not asserted by the I/O
Transfer logic).
A V RC can be carried out on a character in response to an RCTV instruction; i.e., a parity test is made on the
character. This instruction causes the RCTV L signal to be asserted, thereby enabling NO R gate E28. The
resulting TEST VRC signal enables NAND gate E3 to pull the OMNIBUS SKIP line low, if the PARITY signal is
asserted by the VRC logic. Remember that the PAR ITY signal, when asserted, indicates that the tested character
either does exhibit correct parity (VRC logic wired for an odd parity check) or does not exhibit correct parity
(VRC logic wired for an even parity check). Therefore, in the case of an odd parity check, the asserted PARITY
signal would cause the program to skip over an error-handling instruction; in the case of an even parity check, the
asserted PAR ITY signal would cause the program to skip to an error-handling instruction.
Note that the TEST VRC signal also asserts NAND gate E44A, thereby asserting the CO L signal. This action
results in the AC Register being cleared at TP3 time of the RCTV instruction (to be exact, the AC is loaded with
zeros at TP3 time). Because the character is merely tested by the RCTV instruction, it need not be returned to
the AC, as is the case with the RCCV instruction. A similar situation exists when only an LRC or a CRC is performed. Each character is transferred from the AC Register to contribute to the BCC generation. The character
need not be returned to the AC. Consequently, the RCGB L signal causes NAND gate E44D to be enabled,
thereby asserting the CO L signal (remember that the VRC (RCGB) flip-flop is set only if a VRC is to be initiated
by the RCGB instruction).
6.8 BCC LOGIC
A block diagram of the BCC logic is shown in Figure 6-11. The logic is used to generate a BCC for either an LRC
or a CRC. Each character that contributes to the BCC accumulation is parallel-loaded into the 8-bit Parity
Register at TP3 time of the RCGB lOT instruction. The character is then shifted from the Parity Register into
the 16-bit BCC Register by 9.5 MHz clock pulses. The accumulation is held in the BCC Register until either an
RCRL or an RCRH lOT instruction is issued.
Each bit of the character in the Parity Register is Exciusive-ORed with the bit in the LSB position of the BCC
Register. The result is placed on the SERIAL QUOTIENT line and shifted into the BCC Register. The particular
bit position into which the SE RIAL QUOTI ENT signal is shifted depends on the state of the control signals

6-17

shown in the bottom of the figure. The LRC/CRC (0) signal manipulates the register for an LRC or a CRC, while
the X BITS L signal produces the correct gating configuration for the bit length of the characters.

DATA ~-11 L

RCRL L

GATING

r-------------r-+-~~------~_r~_+------_r~_+_+------_+_+~~LSB

1
I
I
J

CLOCK

CRC PARALLEL INPUTS

LRC/CRC

SHIFT RIGHT/PARALLEL LOAD

B BITS L

12 BITS L 16 BITS L LRC/CRC (0)

SERIAL QUOTIENT--+--------'

6 BITS L

7 BITS L

8E-Q492

Figure 6-11 BCC Logic, Block Diagram

Consider an LRC parity check, which can be carried out on 6-, 7-,8-,12-, and 16-bit characters. The BCC is
accumulated in the BCC Register with the LSB right-justified. Therefore, a number of left-most bit positions in
the BCC Register must be ignored when a BCC of less than 16 characters is accumulated. For example, the 8
left-most bit positions (CO-C7 in Figure 6-11) must be disregarded when an 8-bit BCC is accumulated. This configuration is illustrated in Figure 6-12, a logic-block diagram that also shows the configuration for 6- and 7-bit
characters.
When the character is parallel-loaded into the Parity Register, the LSB of the character is Exciusive-ORed with the
bit in the C15 position (E42). The result is placed on the SERIAL QUOTIENT line. The first clock pulse of the
burst (see the VRC logic and the BCC clock logic) shifts the SE RI AL QUOTI ENT bit into either the C8, C9, or
C10 position of E22, while at the same time shifting the next character bit into the LSB position of the Parity
Register.
Assume that the data character loaded into the Parity Register is 6 bits in length. The 6 BITS L signal and the
CRC/LRC (0) signal are asserted by the Control Register logic (consequently, the 16 BITS L signal is negated).
Therefore, each SERIAL QUOTIENT bit is shifted into the C10 position of the BCC Register and shifted right
by each succeeding clock pulse (note that although E22 is in the parallel-load mode, a right-shift operation is
carried out because of the IC's external wiring). After six clock pulses, the character has been shifted out of the
Parity Register. Each bit of the character has been Exciusive-ORed and shifted into the 6 most significant bit
positions of the BCC Register. Each character of the message is handled in the same way. When the last character
has been operated on, the BCC has been accumulated. The RCR L instruction can then be issued, causing the
character to be gated to the AC Register via DATA lines 4 through 11, as shown. If the last character of the message is a BCC accumulated by a transmitting station, the final content of the BCC Register is 0, if no errors
occurred.
6-18

DATA 4-11 L

___________A____________

RCRL L

PAR ITY
REGISTER
E14, E34

E18

C13 C14 C15

C4 C5 C6 C7

E42

E38

+3V

DATA 4-11 L
CLOCK __------------~~----------------------~~~_+--+_----r_~

SERIAL
QUOTIENT
8 BITS L

NOTES

1. E22 and E42 in right-shift mode when pin 13 is high.

2. CRCI LRC (0) signal is high for LRC.

BITS L

CRC/LRC(O)
8E - 0493

Figure 6-12 6-, 7-, and 8-Bit LRC BCC Accumulation

Figure 6-13 shows the actual logic involved in the 6-bit LRC BCC accumulation. Note that many connections
shown have been left off the logic block diagram of Figure 6-12. One should study Figure 6-13 thoroughly to
pick up fine points not illustrated in the logic block diagram. Refer to engineering drawing no. E-CS-M884-0-1 for
the complete logic presentation.
An LRC can be used to accumulate a 12-bit or 16-bit BCC, also. The BCC Register configuration in each case is
shown in Figure 6-14. Consider the 12-bit BCC first.
To accumulate such a BCC, the 12 BITS L signal and the CRC/LRC (0) signal are asserted by the Control Register
logic. Therefore, ICs E18 and E42 are placed in the right-shift mode, while E22 is in the parallel-load mode.
IC E38 is wired so that it is always in the right-shift mode. The output of E38, the C7 bit, is applied t'o the serial
input line of E22. However, E22 is in the parallel-load mode and ignores the output of E38. Instead, the C3 bit
is gated to pin 10 of E22, the parallel-load input of the C8 bit. Thus, the 12 register bits used for the 12-bit BCC
are CO-C3 and C8-C 15.
To fill these 12 register bits, a 12-bit character must be transferred from the PDP-8/E memory, Because the Parity
Register can accommodate only 8 bits, one must use the following technique:

The 12-bit character is brought from memory and loaded into the AC Register by a TAD instruction.

The RCGB instruction is issued, causing the character to be gated via the DATA Iines to the Parity
Register. At TP3 time, the 8 least significant bits are loaded into the Parity Register (bit 11 of the
character is loaded into the LSB position). The AC Register is cleared (see the I/O XFER logic).

The BCC Clock logic generates a burst of 6 clock pulses, shifting the 6 least significant bits of the
character into the 6 most significant bit positions of the BCC Register (CO-C3, C8, C9).

While the registers are being shifted, another TAD instruction loads the same character into the AC
Register.
(continued on next page)

6-19

A BSW instruction (swap bytes in AC) is issued, causing the 6 most significant bits of the character to
be placed in the 6 least significant bit positions of the AC (the MSB of the character goes to AC bit 6).

Another RCGB instruction is issued. Now the Parity Register is loaded with the 6 most significant bits
of the character; bit 0 of the character is loaded into the Parity Register LSB position. The AC Register
is cleared.

Six clock pulses shift the 6 most significant bits of the character into the BCC Register and shift the 6
least significant bits of the character to the right.

The 12-bit character is now contained in the 12-bit BCC Register. Each succeeding character is handled
in the same way.

When the BCC has been accumulated, the RCR L instruction causes the character to be gated to the AC Register.
The 4 most significant bits are gated via DATA lines 0 through 3, as shown. If the last character of the message is
a BCC accumulated by a transmitting station, the final content of the BCC Register is 0, providing no errors
occurred in transmission.
When a 16-bit BCC is accumulated, all 16-bit positions of the BCC Register are used, and each IC is placed in the
right-shift mode, as Figure 6-14 illustrates. Because the PDP-8/E cannot store an entire 16-bit character in one
memory location, two locations are required. The 8 most significant bits of the character are stored in location
"A", in a right-justified format, while the 8 least significant bits of the character are stored in location "B", also
in right-justified format. A TAD instruction brings the contents of location B to the AC Register first. An RCGB
instruction transfers the 8 least significant bits to the Parity Register; clock pulses then shift the bits into the
8 most significant bit positions of the BCC Register. Another TAD instruction brings the contents of location A
to the AC. A second RCGB instruction results in the 8 most significant bits of the character being shifted into the
8 most significant bit positions of the BCC Register. At the same time, the 8 least significant bits of the character
are right-justified into the 8 least significant bit positions. As Figure 6-14 indicates, the 8 least significant bits of
the BCC are transferred to the AC Register via DATA lines 4 through 11 by the RCR L instruction, while the 8
most significant bits are transferred by the RCRH instruction.
The BCC accumulation during a CRC parity check is basically the same as during an LRC: the message characters
are parallel-loaded into the Parity Register; the bits in the LSB positions are Exciusive-ORed; the result is placed
on the SERIAL QUOTIENT line and shifted into the BCC Register. However, to implement the generating
polynomial, P (X), additional Exciusive-ORing is carried out, as illustrated in Figure 6-15.
The logic block diagrams shown in Figure 6-15 illustrate Exclusive-O R gating for both CRC-12 and CRC-16. The
gating enables the logic to implement the two generating polynomials. For industry-compatible application,
CRC-12 is used with 6-bit characters, while CRC-16 is used with 8-bit characters. CRC-12 could be used to generate the BCC of a message consisting of 12-bit characters, but this would require the same sort of program manipulation as described for LRC-12. The same can be said when considering CRC-16 with 16-bit characters. Because
the CRC logic is so similar to the LRC-12 and LRC-16 logic, no further logic description is presented.

SECTION 5 MAINTENANCE
See Volume 1 for maintenance information that can be applied to the KG8-E option. The diagnostic program
and the single-step test feature should be used to isolate problems that are traced to the KG8-E.

6-20

RCRL L

16 BITS .L

RCCV L

SER IAL
QUOTIENT

RCGB L ---<J
~
RCCB L - - - - - - - ,
INITIALIZE

'-,
I

DATA 4-11 L

I
I
I
I
I
---l
I
I
I
I
I
I

+3V

8271
E14

DATA 6 L
6 BITS L

DATA 7 L

+3V

DATA 8 L

4
RCLC L
B271
E34

DATA 9 L

TP3
6

DATA 10 L

L_..J

DATA 11 L

LOAD P -----~
9.5 MHZ
CLOCK
PULSES

NOTE'

8271 Ie: Pin 13 LO, Ie in parallel lood mode.
Pin 13 HI, Ie in right-shift mode.
8E-0494

Figure 6-13 BCC Generating Logic (Using LRC Technique - 6-Bit Character)

DATA 4-11 L

DATA 0-3 L

RCRL L -----<f-4.--r~~~_r_J

GATING

CLOCK

RCRH L

DATA 4 -11 L

DATA 4-11 L

GATING

RCRL L

CLOCK

NOTES'
1, E18, E 38, E22 ,E42 in right -shift mode when pin 13 is high.
2, CRC/LRC (0) signal is high for LRC.

16 BITS L

LRC-f6

8E- 0495

Figure 6-14 Logic B lock Diagram: LRC-12, LRC-16

SECTION 6 SPARE PARTS
Table 6-2 lists recommended spare parts for the KG8-E_ These spare parts can be obtained from any local DEC
office or from DEC, Maynard, Massachusetts.

6-22

DATA 0-3 L

RCRL L

DATA 4-11 L

--~----~--~~N(~~

GATING

SERIAL QUOT

CLOCK --~------~---------*---+-------+~rr~-r--+-~~--------------~----~---------+~

16 BITS L

CRCI LRC (0)

(CRC-12)
P(X) '" X12 +Xll+ X 3 +X 2 +X+1

CRC-i2
DATA 4-11 L

CRC-i6

RCRH L
SERIAL QUOT

DATA4-11L

--------.[~~==~~==~G~A~T~I~N~G~:==:==:==:J

GATING

RCRL L

CLOCK--~------~---------4---t--~--1----t+-----+-~------------~~~~-------------+~

DATA 4-11 L

16 BITS L

(CRC-16)
p(X)=XI6+XI5+X2 +1

CRC/LRC(O)

NOTES,
I. E18,E38,E22,E42 in right-shift mode when pin 13 is high.
2. eRC/ LRC(O) signal is low for eRG.

SE-0496

Figure 6-15 Logic Block Diagram: CRC-12, CRC-16

Table 6-2
KG8-E Recommended Spare Parts
DEC Part Number

19-09704
19-09485
19-05575
19-09004
19-09686
19-05576
19-05580
19-05547
19-10011
19-09594
19-09615
19-09705
19-10035
10-00016
10-01610
10-00027
13-00293
13-01401
13-00271

Description

Quantity

IC DEC 314
IC DEC 380
IC DEC 7400
IC DEC 7402
IC DEC 7404
IC DEC 7410
IC DEC 7450
IC DEC 7474

IC DEC 7486
IC DEC 8251
IC DEC 8271
IC DEC 8881
IC DEC 74197
Capacitor, 100 pF, 100V, 5%
Capacitor, 0.01 J.1F, 100V, 20%, DISC
Capacitor, 820 pF, 100V, 5%
Resistor, 330n, 1/4W, 10%
Resistor, 750n, 1/4W, 5%
Resistor, 220n, 1/4W, 5%

6-24

1
2
2

PART 6
CARD

READERS

CHAPTER 7
CMS-E/CRS-E CARD READERS

SECTION 1 INTRODUCTION
Two card reader options are available for use with the PDP-S/E. Both transfer data from E lA-standard data cards
to the CPU AC Register. The CMS-E Optical Mark Card Reader option reads data from pencil-marked or punchedhole data cards; the CRS-E Card Reader option reads only from punched-hole cards. Each option uses the same
control module to interface the card reader and the computer. This module, DEC MS43, plugs into the OMNIBUS
and connects to the external card reader via a signal cable that is supplied with the option.
The card reader used with the CMS-E option is the GDI Model 100-M Optical Mark Reader. That used with the
CRS-E option is the Documation Model M200 Card Reader. These card readers are discussed only to the extent
necessary both to fully describe the control operation and to present supplementary information concerning installation and checkout of the option. Details of the installation, operation, troubleshooting, and maintenance
of the card reader, itself, can be found in the respective technical manual. Other publications and documents
relevant to the CMS-E and CRS-E are:

a.
b.

c.
d.

PDP-8IE & PDP-81M Small Computer Handbook - DEC 1972
PDP-8IE Maintenance Manual, Volume 1
CMS-E Diagnostic, MAINDEC-SE-D2DA, CRS-E Diagnostic, MAINDEC-SE-D2EA
0 EC Engineering Drawing, Card Reader Control, E-CS-MS43-0-1.

SECTION 2 INSTALLATION
The CRS-E/CMS-E Card Reader option is installed on site by DEC Field Service personnel. The customer should
not attempt to unpack, install, checkout, or service the equipment.
Insert the option control module (DEC MS43) into the PDP-S/E OMNIBUS. Refer to Table 2-3, Volume 1, for
information concerning recommended module priorities (the CRS-E/CMS-E is a "non-memory" option).
Connect the control to the card reader with the signal cable provided. J 1 of the control connects either to J2
(CRS-E) or to J5 (CMS-E) of the card reader. See Section 5 for cable and connector pin assignments.
The CRS-E/CMS-E option can be checked for correct operation by running the appropriate diagnostic program.
Refer to the respective card reader instruction manual for card reader checkout procedures.

7-1

SECTION 3 BLOCK DIAGRAM DESCRIPTION
Figure 7-1 is a block diagram of the CRS-E/CMS-E Control. OMNIBUS pin numbers can be found on DEC engineering drawing E-CS-MS43-0-1. The pin assignments for connector receptacle J 1 are given in Table 7-4.

OMNIBUS

I
I
I

1
INTERNAL 110 L 1 - - - - - - - - - - - - - - ,

Cl L~I------------,
I/O PAUSE L t - - - - - - - . f I O T I
MD 3-11 Lt-I-------4.~~:.J

READ
roT 6631,6632

~~~i:~~iI
6674,6675

1..______________6_6_7_7 _ _ ___

SKIP L ...

eIR
READY/ON-LINE

INT RQST L 1 + - - - - - - - - - - - - - - - - - - - ,
6631,6635
6671,6672,6675

DATA 0,1,2,3 L

DATA 0-11 L 1 + - - - - - - - - - - - ,
DATA 6-11 L : _ - - - - - - - - - ,
DATA 0,4-11 L 1 4 - - - - - - - - ,

1
I
I
I
I
I
1
I

6677
6637

6632 _---I....J...~::;_'__,
6634

-+-.---1

6636 II~-=~~.J

DATA READY (1)

INDEX MARKER/ DATA STROBE
ZONE INPUTS 12,11,0-9

8E-0354

Figure 7-1 CRS-E/CMS-E Control Block Diagram

The signals shown on the block diagram are related in the timing diagram, Figure 7-2. The lOT instructions are
listed in Table 7-1 (the same instruction set is used by both the CRS-E and the CMS-E; thus, the two card readers
cannot be used in the same system). Refer to Figures 7-1 and 7-2 and Table 7-1 while reading the block diagram
description.
The card reader asserts the signal READY/ON LI N E when the reader is clear of errors and ready to receive a card
read command. When the 6672 instruction is issued, the control's lOT decoder logic asserts the 6672 L signal.
At TP3 time, the select card logic asserts the READ signal that initiates the card pick cycle in the card reader.
A card is brought into the reader card track and advanced toward the read station. The CI R signal is asserted by
the reader when the card has arrived at the read station,
The card columns pass sequentially before the read station sensors beginning with column 1 (note that an SOcolumn card is illustrated in the timing diagram; this applies only to the CRS-E, the CMS-E being limited to use
with 40-column cards). The information in the 12 data rows of the column is transferred, via the Zone Input
lines, to the 12-bit Zone Register of the read data logic. The reader generates an INDEX MARKER/DATA
STROB E signal for each card column; this signal clocks the information on the Zone Input lines into the Zone
Register. At the same time, INDEX MARKER STROBE causes the read data logic to assert the DATA READY (1)
signal.
7-2

READY/ON LINE

6672

J~------------------------------------------~\\~-----------------------------------------)(~)---------------------------------------------~

TP3

----------~------------------------------------------~\(rl----------------------------------------------~---

READ

~--------------------------------~)(r)----------------------------------------------~r--
rl--------------------------------~\(~I--------------------------------------'

CIR

1
1

160M. (CM8-E) ~-------.~'~-----------------------------130MS (CM8-E) ______________________________~"'
24M. (CR8-E):"
":"
170Ms (CR8-E)
I

-...J

ZONE INPUTS

------------------________~~s:;(;:~~r)----------~~59~~;i~L----------------

INDEX MARKER/
DATA STROBE

_____________________~n~--------~((I__----------~n~----------------1

DATA

READY (1)

___________________________~tl~____________~((\_---------------~IlL-------------------II
U
1

,--

\(~j---------------------,u

INT RQST L

I
1

1
I

LJJr------------~\\

6634 L
1
1

TP3

i Ii

-------------------------I~·~I---------~\r\----------------~----------------

LJ
I

DATA 0-11 L

CARD DONE

I I

----------------------,U

I, \-()

(1)------------------------------------------------------~\(r)------------------------------________~

NOTE:

TIME RELATIONSHIP OF WAVE FORMS
IS OFTEN DISTORTED.

Figure 7-2 Timing, CR8-E/CM8-E Control

L
8E-0355

Table 7-1
CMS-E/CRS-E Instruction List
Octal Code

Mnemonic

Function

6631

RCSF

Skip on the Data Ready flag. Senses the state of the DATA
READY flip-flop. If the flip-flop is set, the program counter
is incremented so that the next sequential instruction is
skipped.

6632

RCRA

Read alphanumeric. Causes a 6-bit alphanumeric code, which
is translated from the 12-bit code of a card column, to be gated
to AC bits 6-11. Clears the DATA READY flip-flop.

6634

RCRB

Read binary. Causes the 12-bit code of a card column to be
gated to AC bits 0-11 (column rows 12, 11, and 0 are gated to
ACO, 1, and 2, respectively; rows 1-9 are gated to AC3-11,
respectively). Clears the DATA READY flip-flop.

6635

RCNO

Read conditions out to card reader. Selectively sets or clears
two flip-flops that control the I NT/skip logic. If AC11 is logic
1, the RCNO instruction sets the DATA AND CARD INT flipflop, thereby enabling the DATA READY flip-flop and the
CARD DONE flip-flop to cause a program interrupt and an
instruction skip. If AC10 is logic 1, the RCNO instruction
sets the ROY/TROUBLE INT flip-flop, thereby enabling a
transition in the READY/ON LI N E signal to cause a program
interrupt and an instruction skip.

6636

RCRC

Read compressed. Causes an S-bit code, which is translated
from the 12-bit code of a card column, to be gated to AC bits
4-11. Gates a logic 1 into AC bit 0, if a hardware validitycheck circuit has detected more than one hole or mark in
rows 1-7 of a card column. Clears the DATA READY flipflop.

6637

RCNI

Read conditions in from card reader. Causes the state of the
DATA READY flip-flop and the state of the CARD DONE
flip-flop to be placed on DATA lines 0 and 1, respectively.
Causes the transition of the READY/ON LINE signal to be
represented by DATA bits 2 and 3. If the signal has gone
high, the DATA 3 L signal is asserted, while the DATA 2 L
signal is negated; if the signal has gone low, the DATA 3 L
signal is negated, while the DATA 2 L signal is asserted.

6671

RCSD

Skip on Card Done flag. Senses the state of the CARD DONE
flip-flop. If the flip-flop is set, the program counter is incremented so that the next sequential instruction is skipped.

6672

RCSE

Select card and skip if ready. If the card reader has asserted
the READY/ON LI N E signal, the program counter is incremented so that the next sequential instruction is skipped; a
card is started toward the read station. Clears the CARD
DONE flip-flop.

(continued on next page)

7-4

Table 7-1 (Cont)
CM8-E/CR8-E Instruction List
Octal Code

Mnemonic

6674

RCRD

Clear Card Done flag. Clears the CARD DONE flip-flop.

6675

RCSI

Skip if interrupt being generated. If anyone of four conditions
has caused a program interrupt, the program counter is incremented so that the next sequential instruction is skipped.

6677

RCTF

Clear Transition flag. Clear the TRANSITION flip-flop in the
status logic.

Function

If the control is programmed to operate in the interrupt mode, as the timing diagram illustrates, DATA READY (1)
causes the I NT/skip logic to assert the OMN IBUS I NT ROST L signal. The computer then begins to execute the
interrupt servicing routine. When the appropriate instruction (6631 in this example) in the servicing routine is
decoded, the I NT/skip logic asserts the OMNIBUS SKIP L signal. The computer proceeds to an appropriate subroutine to transfer the data from the read data logic to the OMNIBUS DATA lines, via the data gating logic. The
6634 instruction is used in the present example to transfer the data; this instruction is decoded and the resulting
signal, 6634 L, gates the data through the data gating logic to the DATA 0-11 lines. At TP3 time, the information is loaded into the AC Register and the DATA READY (1) signal is negated. When the data from all
columns has been transferred, the CI R signal is negated and the select card logic asserts the CAR D DONE (1)
signal. This signal asserts the I NT ROST L signal, the card pick subroutine is entered, and a new 6672 instruction
is decoded.
The control status logic allows the program to check the status of the DATA READY (1) signal, the CARD
DONE (1) signal, and the READY/ON LINE signal. The significance of this status logic is explained in detail in
Paragraph 7.5.

SECTION 4 DETAILED LOGIC
7.1

lOT DECODER LOGIC

The lOT decoder logic is shown in Figure 7-3. Bits MD3-8 are decoded by NAND gates E12 and E16 to produce
signals 667X, and 663X, respectively. Each of these signals causes the OMNIBUS INTERNAL I/O L signal to be
asserted, ensuring that the positive I/O bus interface ignores the lOT instruction. Also, each signal is gated with
bits MD 9, 10, and 11 in decoder E3 to produce the lOT signals shown. The inverted 663X signal, likewise, is
gated with bits MD 9, 10, and 11, but in decoder E2. This decoder produces the six lOT signals shown, four of
which cause the OMNIBUS C1 L signal to be asserted. When the C1 L signal is asserted, information placed on
the DATA lines is gated through the CPU Major Register Gating and ORed into the AC Register (a jam transfer is
unnecessary because a card reader program always clears the AC Register before data is transferred from the card
reader control).

7-5

RCSO (6671) L
E3
8251

RCSE (6672) L
RCRO (6674) L
RCSI (6675) L

M03 L - - - - - - - - - - . - - 0

RCTF (6677) L
M04 L - - - - - - - -.....+--0
667X

M05 L

o-_..+++------INTERNAL I/O L
MOB L -1--------.-+-++-'--U

M07 L -1'-------<1>-4-+-++--0
M09 L

M06 L -H>----_H-+-+-+--<".I

C1 L

RCRA (6632) L
E2
B251

RCRB (6634) L
RCRC (6636) L
RCNI (6637) L
RCSF (6631) L
ReNO (6635) L

8£-0356

Figure 7-3 lOT Decoder Logic

7.2 SELECT CARD LOGIC
The select card logic is shown in Figure 7-4. When the 6672 lOT instruction is decoded, the lOT decoder logic
generates the RCSE L signal. If the card reader is ready, the signal at pin J1J, READY or ON LINE, is high and
NAND gate E20 asserts OMNIBUS SKIP L. The two E40 NAND gates at the READY/ON LINE input comprise
a Schmitt trigger that prevents noise on the input line from triggering the select card logic (a Schmitt trigger is
placed in the J 1N input for the same reason).
At TP3 time of the 6672 instruction NAND gates E24 and E27 are enabled. Thus, the CARD DONE flip-flop is
cleared and the READ flip-flop is set, the latter flip-flop causing NOR gate E39 to assert the READ signal. This
signal causes the card reader to begin processing the data card. When the card is in the read station, the signal at
pin J1 N, CI R (Card In Reader), goes high, clearing the Read flip-flop. When the card has been processed the CI R
signal is negated. The negative-going edge of the signal sets the CARD DONE flip-flop.
Note that both the CARD DONE flip-flop and the READ flip-flop are cleared by the OMNIBUS INITIALIZE
signal via NOR gate E29. The CARD DONE flip-flop, in addition to being cleared by this signal and by the RCSE
instruction, can be cleared by the RCRD instruction (Clear Card Done flag). Normally, the CARD DONE flip-flop
generates an interrupt request when it is set; the result of the program interrupt is a re-issue of the RCSE instruction. Thus, another card is fed into the read station and processed. However, the programmer might wish to halt
the reading operation when a particular card has been processed. Such a halt can be carried out easily by a subroutine; but, the subroutine must issue the RCRD instruction so as to clear the CARD DONE flip-flop and
remove the ground signal from the OMNIBUS INT RQST line.
The READ flip-flop can also be cleared by a signal other than IN ITIALI ZE. This other signal is taken from the
J1J input Schmitt trigger, as Figure 7-4 illustrates. Thus, when the READY/ON LINE signal goes low, the READ
flip-flop is cleared, negating the READ signal. This action prevents an uncontrolled start of the card reading
operation when the reader is manually re-started following a trouble condition.
7.3 READ DATA LOGIC
As each card column passes the read array in the card reader, 12 data row bit signals and one INDEX MARKER/
DATA STROB E signal can be generated (a data row bit signal is generated if a hole/optical mark is present in a
data row). The data row bit signals are transferred to the Zone Register in the read data logic, as illustrated in
Figure 7-5. Each bit is applied to the data (D) input of the corresponding Zone Register flip-flop; i.e., the Data
Row 12 bit is applied to the ZONE 12 flip-flop, the Data Row 0 bit is applied to the Zone 0 flip-flop. The INDEX
MARKER/DATA STROBE signal is also transferred to the read data logic. However, before it is applied to the
clock (C) input of the Zone Register flip-flops, it is delayed for approximately 2 J1S by a network that includes
the one-shot multivibrators E32 and E45. This network ensures that the D-input lines of the Zone Register flipflops have settled before the flip-flops are clocked by the INDEX MAR KER/DATA STROBE signal. This precaution must be taken because some card readers do not provide a sufficient amount of time between generation
of the Data Row bit signals and the INDEX MARKER/DATA STROBE signal (those listed in Section 1 do provide sufficient time; see the various card reader instruction manuals for clarification).

7-7

CARD DONE(1)

6674 (RCRD) L
6672(RCSE)L~~-4V

+5V

E36

rr--~-------------------f--------------~---------------SKIP L

......

Co
READY (CRS-E)

J1R READ

ON LINE (CMS-E)l

J1N CIRo-~A-~-.~r---~

Figure 7-4 Select Card Logic

8E-0357

DATA 11 L
RCRA L-----'
RCRB L----l
RCRC L______

DATA 0 L

_1_ -- -- - _L_...,
FI~,~A~_~".J:~~_9
• •

-I

.--+-- - - - - _ _ _ _ _ _ _ _ _ _ _
LL
'--_ _ _~(DATA ROW 9)

BB
(DATA ROW12)

>---*-STROBE/MARKER

J1Lo--...-.----..
DATA STROBE
(CMS/E)
IN D'EX MA RKER
(CRS/E)

8E-0358

Figure 7-5 Read Data Logic

The INDEX MARKER/DATA STROBE signal clocks not only the Zone Register flip-flops, but also the DATA
READY flip-flop. Thus, when the data from a card column is loaded into the Zone Register, the DATA READY
(1) signal is asserted. The state of this signal can be tested by a program instruction or by using the interrupt
mode. I n either case, the program then enters a subroutine that contains one of the read instructions, RC RA,
RCRB, or RCRC. As illustrated in Figure 7-5, these instructions generate signals that cause the data in the Zone
Register to be gated through the read gating logic to the OMNIBUS DATA lines. At TP3 time of the instruction
the DATA READY flip-flop is cleared and the procedure is repeated for the next card column of data.
7.4 INTERRUPT/SKIP LOGIC
Four conditions in the Card Reader option can cause a program interrupt; viz., the data from a card column is
ready to be placed on the DATA lines, all columns of the present card have been read, the READY/ON LINE
signal has gone high, the READY/ON LINE signal has gone low. The first two conditions are represented,
respectively, by the set state of the DATA READY flip-flop and of the CARD DONE flip-flop; the last two conditions are represented by the set state of the TRANSITION flip-flop. These three flip-flops are illustrated in
Figure 7-6.
Also shown in Figure 7-6 are two interrupt control flip-flops, identified as DATA AND CARD INT and RDY/
TROUB LE I NT. These two flip-flops are set under program control and enable the three condition flip-flops to
assert the OMNIBUS INT RQST L and SKIP L signals. Specifically, consider the DATA AND CARD INT flipflop, E23A. This flip-flop can be set at TP3 time of the RCNO instruction, if the ACll bit is logic 1 (this flip-flop
is set by the INITIALIZE signal for program compatibility with other PDP-8 family computers; if the programmer
does not want the set state, he must clear the flip-flop by programming the RCNO instruction with a logic 0 in
the AC11 bit). The l-output of E23A is applied to two NAND gates, E15, and an AND/NOR gate, E19. The E15
gates enable the CARD DONE flip-flop and the DATA READY flip-flop to assert the INT RQST L signal. Gate
E19 enables the same two flip-flops to assert the SKIP L signal when an RCSI instruction is issued. The RDY/
TROUBLE INT flip-flop, E23B, operates like E23A. It, too, is under program control of the RCNO instruction;

7-9

however, AC bit 10 determines if the flip-flop is set or cleared (note that this flip-flop is cleared, rather than set,
by the INITIALIZE signal). Its l-output is also applied to gates E15 and E19; however, in this case, E15 and
E19 are enabled by the TRANSITION flip-flop rather than by the DATA READY or CARD DONE flip-flops.
As with many other PDP-S/E options, the Card Reader option can engage in a programmed I/O transfer of data or
it can operate in the more efficient interrupt mode of data transfer. If the interrupt control flip-flops, E23A and
E23B, are not set, a background program must execute a loop that tests for a desired condition. For example,
the program can repeatedly test the DATA READY flip-flop with the RCSF instruction. When the flip-flop is
set the RCSF L signal causes NAND gate E20 to assert the SKIP L signal. The program then proceeds to an
appropriate subroutine. The same method can be used to test the CARD DONE flip-flop with the RCSD instruction, and to test the READY/ON LI NE signal with the RCSE instruction.
If the programmer wishes to use the interrupt mode, he can proceed in a number of ways. For example, if E23A
is set, the DATA READY flip-flop, when set, causes NAND gate E 15 to assert the I NT ROST L signal. The program executes the interrupt servicing routine; the RCSF instruction in the routine results in a jump to the appropriate subroutine. The same method can be used for the CARD DONE flip-flop. However, note that the
READY/ON LINE signal does not directly cause an interrupt request. Rather, the TRANSITION flip-flop, which
reflects the state of the READY/ON LI NE signal, is used to assert the INT ROST L signal. Thus, if E23B is set,
the TRANSITION flip-flop, when set in response to a transition of the READY/ON LINE signal, causes NAND
gate E15 to assert the I NT ROST L signal; the appropriate subroutine is ultimately carried out.
Perhaps the most efficient way of using the interrupt capability of the Card Reader option is that which tests all
the interrupt flip-flops simultaneously with the RCSI instruction. If both E23A and E23B are set, AND/NOR
gate E19 is enabled when any of the interrupt flip-flops is set. The RCSI instruction in the interrupt servicing
routine causes NAND gate E20 to assert the SKIP L signal. A card reader routine is then entered and the specific
reason for the interrupt request must be determined. This determination involves testing with the skip instructions, which is a satisfactory method in the case of the CARD DONE and DATA READY flip-flops. However,
when the TRANSITION flip-flop has caused an interrupt request another method is necessary. Because the flipflop is set by a transition of the READY/ON LINE signal, the program must also determine if the signal went
from low to high or vice-versa. The RCSE instruction could determine a low to high transition by causing an
instruction skip via NAND gate E20; however, the opposite transition could be detected only if the absence of
such a skip caused an error routine to be entered. Another method of making the transition determination is provided by the status logic, shown in Figure 7-7 and discussed in the following paragraphs.
7.5 STATUS LOGIC
As detailed in Paragraph 7.4, any of four conditions can cause a card reader interrupt request. Two conditions
involve the READY/ON LI NE signal; the status logic has been devised, primarily, to deal effectively with these
two conditions. The READY/ON LI NE signal is applied to the Schmitt trigger, E40 (Figure 7-7). The Schmitt
trigger provides an input signal for NAN D gate E5D and for a delay network consisting of inverterES, delay line
DL 1, and AND/NOR gate E19. The delay network gates the Schmitt trigger output in such a way that gate E19
is enabled when the READY/ON LINE signal undergoes a transition. Figure 7-S is a timing diagram illustrating
how the output is obtained.

7-10

REA DY / ON L ~~ ~ o---"y'V\.----<r--'~q,.__/

RCSF L

SKIP L

INT

JO----<t-- RQ ST
L

DATA"

BE - 0359

Figure 7-6 INT/Skip Logic

DATA 1 L

DATA 0 L

INITIALlZE---4

RCTF L--=------<lr--.....
TP3

RCNIL---------------------~
8E-036Q

Figure 7-7 Status Logic

E40,P.13

E8,P.8

DL1,P.3

E8,P.6

~--------------~\~\--------------~

~-------------~\~\-------------~
L-----~\(~i-----------~
r-----~\\~----------,
~

____~\I~)--------------~

E19,P.6

8E - 03 61

Figure 7-8 Timing, Transition Network

When a change in the READY/ON LINE signal occurs, the output from E19 sets the TRANSITION flip-flop, E7.
The O-output of E7 is one input of NAND gate E35. The other input of E35 is asserted when the RCNI instruction is issued. When E35 is enabled, NAND gate E5C or E5D is enabled, depending on the direction of the
READY/ON LINE signal transition. For example, if the READY/ON LINE signal has gone from low to high,
E5D asserts the DATA 3 L signal when the RCN I L signal enables E35. Note that the RCN I L signal also enables
NAND gate E1. This gate, in turn, can enable gates E5A and/or E5B, depending on the state of the CARD DONE
flip-flop and the DATA READY flip-flop. Thus, a signal representing the status of each of the card reader

7-12

conditions can be placed on a DATA line by the RCNI instruction. The DATA line information is then gated to
the AC Register and loaded at TP3 time. Although the status logic is more sensibly applied in the interrupt mode,
it could be used to advantage in the programmed I/O transfer mode, particularly when the DATA READY flipflop is considered. For example, the program could concern itself with a task, periodically issuing a RCN I instruction, followed by a SMA Operate microinstruction. If the DATA READY flip-flop were set, the ACO bit would
become logic 1 at TP3 time of the RCN I instruction. This is defined as a "minus AC"; thus, a program instruction
would be skipped and a subroutine could be entered. This procedure could conceivably be extended to the other
three DATA bits (1, 2, and 3) by making use of the rotate microinstructions.
The status logic is more efficient when used in the interrupt mode. The program can be interrupted when one of
the card reader conditions becomes true. The RCSI instruction can then direct the program to a card reader
routine that checks each bit of the status word with the rotate microinstructions. This method is particularly
effective in monitoring the state of the READY/ON LINE signal.
7.6 READ GATING LOGIC
The read gating logic is illustrated in Figures 7-9,7-10, and 7-11. Each figure shows the logic for one of the three
read instructions, RCRA, RCRB, and RCRC.
The simplest form of reading is that which is accomplished by the RCRB instruction, Read Binary. This logic is
shown in Figure 7-9. The RC RB L signal gates the Zone Register bits through the 12 NAND gates to the DATA
lines; the bit-for-bit correspondence is as indicated. The DATA bits are gated to the AC Register and loaded at
TP3 time.
A more complex form of reading is that which is accomplished by the RCRA instruction, Read Alphanumeric.
This form of reading converts the code represented by the holes or marks of each card column to a 6-bit alphanumeric code. The alphanumeric code is gated onto DATA lines 6 through 11 by the RCRA L signal (Figure 7-10)
and loaded into the AC Register at TP3 time.
The data card can be punched or pencil-marked to represent any code desired by the user. However, the most
common code in use, particularly with punched cards, is the Hollerith code. The 47 characters of the Hollerith
code can be converted easily to the 6-bit alphanumeric code, thereby minimizing the size of translation tables.
Table 7-2 shows the relationship between the Hollerith code and the alphanumeric code carried by the DATA
lines. Each character of the topmost group, numerals 1 through 9, is translated into an alphanumeric code as
follows: The numeral is represented in BCD code in the four least-significant DATA bits; the two most significant
DATA bits are logic O. The next three groups of characters are translated in a similar manner; the BCD code for
numerals 1 through 9 is repeated (the fourth group repeats 2 through 9) in each group, but DATA bits 6 and 7 are
changed. The last group is translated with less extensive but still noticeable similarities.
The third form of reading, RCRC (Read Compressed), is accomplished by the logic shown in Figure 7-11. This
form of reading is designed to handle a proposed expansion of the Hollerith code. The expanded Hollerith code
is converted to a 9-bit compressed code that features a validity-check bit. The 9-bit compressed code is gated onto
DATA lines 0 and 4 through 11 by the RCRC L signal and loaded into the AC Register at TP3 time.
Table 7-3 shows the relationship between the Hollerith code (excluding whatever characters may be added as a
result of expansion) and the compressed code. Note that DATA bit 0 is always logic O. This bit is the validitycheck bit. Only one of rows 1 through 7 in a card column can contain a hole or mark. If more than one row is
punched or marked, an error exists and the DATA 0 bit becomes logic 1. This error condition could be checked
by the program, for instance, with a SMA Operate microinstruction.

7-13

ZONE 9 (1)
DATA 11 L

ZONE 8 (1)
DATA 10 L

ZONE 7 (1)
DATA 9 L

ZONE 6 (1)
DATA 8 L

ZON E 5 (1l
DATA 7 L

ZONE4(1)
DATA 6 L

ZONE 3 (1)
DATA 5 L

ZONE 2 (1)
DATA 4 L

ZONE

1 (1)
DATA 3 L

ZONE 0(1)
DATA 2 L

ZONE 11 (1)
DATA 1 L

ZONE 12 (1)
DATA 0 L

RCR8 -_--<r~'
(6634) L

BE-0362

Figure 7-9 Data Gating, RCRB Instruction

DATA bits 4 through 11 represent the Hollerith code characters in compressed code. Each character of the topmost group, numerals 1 through 9, is translated into compressed code as follows: numerals 1 through 8 are
represented in BCD code in the four least-significant DATA bits (all other bits are logic 0); numeral 9 is represented by logic 1 in DATA bit 4. The next three groups of characters are translated in a similar manner; the code
for numerals 1 through 9 is repeated (the fourth group repeats 2 through 9) in each group, but DATA bits 5,6,
and 7 are changed. The last group is translated with less extensive but still noticeable similarities.

7-14

ZON E 7 (0) -----<:lr--~
ZONE 5 (0) -------<::1
ZONE 3 (0) -------<C'J
ZONE 1 (O)---(~--

D-----DATA 11 L

ZONE 7 ( O ) - - - { ) , - - _
ZON E 6 (0) - - - ( : ; 4
ZON E 3 (0) - - - ( J /
ZONE 2 (0) - - - £ 1 ' - -.....

p - - - - - DATA 10 L

ZONE 7 (0) -------j~-_

p - - - - - DATA 9 L

ZONE 6 (0) - - - ( : ; 4
ZONE 5 (0) -------<~
ZONE 4 ( O ) - - - ( Y - - ZONE 9 (0)-----(::>.
ZONE 8 (0) - - - - 0

p - - - - - DATA 8 L

ZONE 0 (0) - - - - 0 1

D - - - - - DATA 7 L

ZONE 12 (O)----Qi

ZONE 11 ( 0 ) - - - - 0

D - - - - - DATA 6 L

ZONE 1 2 ( 0 ) - - - - 0

RCRA (6632) L

-_--0
8E-0363

Figure 7-10 Data Gating, RCRA Instruction

DATA 11 L

DATA 10 L
ZONE 1 (0)
ZONE 3 (0)
ZONE 5 (0)

DATA 9 L

ZONE 7 (0)

ZONE8(1)

DATA 8 L
ZONE 2 (0)
ZONE 0(1)

ZONE 3 (0)
ZONE 6 (0)

DATA 7 L

ZONE 7 (0)

ZONE 11 (1)

DATA 6 L
ZONE 4 (0)
ZONE 12 (1)
ZONE 5 (0)
ZONE 6 (0)

DATA 5 L

ZONE 1 (0)
ZONE 2 (0)
ZONE 3 (0)

ZONE 7 (0)

DATA 4 L
ZONE 1 (0)
ZONE 4 (0)
ZONE 5 (0)

DATA 0 L
ZONE 2 (0)
ZONE 4 (0)
ZONE 6 (0) ---...._ _.....

RCRC (6636) L --_+----<J\

8E-0364

Figure 7-11 Data Gating, RCRC Instruction
7-15

Table 7-2
Translation, Hollerith Code - Alphanumeric Code
Character
1
2
3
4
5

6
7
8
9
A
through
I
J
through
R

S
through
Z
0

/
=

,
&

(

*
)

Hollerith Code

DATA Bit

(card row punched or marked)

1
2
3
4

0
0
0
0
0
0
0
0
0
1

0
1
1
0
0
1
1
0
0
0

1
0
1
0
1
0
1
0
1
1

1
1

1
0

0
0

1
1

1
0

0
1

1
0

0
0
0
0
0
1
1
0
0
1
1
1
1

1
1
1
0
1
0
1
0
1
0
1
1
0

0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
0
0
through
1
0
0
0
through
1
0
0
0
through
1
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0

0
0
0
1
1
1
1
0
0
0
0
0
0

1
0
1
1
1
1
1
0
0
0
0
0
0

5
6
7
8
9
12,1
through
12,9
11,1
through
11,9
0,2
through
0,9
0
0,1
3,8
0,3,8
11,3,8
12,3,8
4,8
0.4,8
11.4,8
12.4,8
12
11

I
I

SECTION 5 MAINTENANCE
Refer to Volume 1 and the respective card reader instruction manuals for maintenance information that pertains
to both the control and the card readers. The diagnostic program should be used to isolate problems that occur in
the system.
Table 7-4 shows the connector pin assignments for the control and the respective card reader.

SECTION 6 SPARE PARTS
Table 7-5 lists recommended spare parts for the CR8-E/CM8-E. These parts can be obtained from any local DEC
office or from DEC, Maynard, Massachusetts.

7-16

Table 7·3
Translation, Hollerith Code - Compressed Code
Character

Hollerith Code

DATA Bit

(card row punched or marked)

1
2
3
4

6
7
8
9

6
7
8
9
12,1

0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
1

0
0
0
0
0
0
0
0
0
0

0
0
0

0
1
0

1
1
0

0
0
0

0
1
0

0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
1
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
1
0
0
0
1
1
0

A
through
H
I
J
through
Q

R
S
through
y
Z

=
,
&

(

*
)

+
.

through
12,8
12,9
11,1
through
11,8
11,9
0,2
through
0,8
0,9
0
0,1
3,8
0,3,8
11,3,8
12,3,8
4,8
0,4.8
11,4,8
12,4,8
12
11

7·17

0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
through
0
1
0
0
0
0
1
0
0
through
1
0
1
1
0
0
1
0
0
through
1
0
1
1
0
0
1
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
0
0
0
1
0
0

0
0
0
1
1
1
1
0
0
0

0
1
1
0
0
1
1
0
0
0

1
0
1
0
1
0
1
0
0
1

0
0
0

0
0
1

0
0
0

0
0
1

0
0
0

0
0
0
0
0
0
0
0
1
1
1
1
0
0

0
0
0
0
1
1
1
1
0
0
0
0
0
0

0
0
0
1
1
1
1
1
0
0
0
0
0
0

Table 7-4
Connector Pin Assignments, J1-J5, J1-J2
M843 Module
J1 (DEC 1209941)

GDI100M
J5 (AMPHENOL 57-40240)

Documation M200
J2 (ELCO 00-8016-038-000-707)
Pin

Signal

READY/ON LINE

ON LINE X+

RDY (Ready)

INDEX MARKER/
DATA STROBE

DATA STROBE X+

1M (Index Mark)

CIR

CARD IN READER X+

BSY (Busy)

READ

READ COMMAND X+

PC (Pick Command)

ZONEINPUT12

DATA ROW 12 X+

D12

ZONE INPUT 11

DATA ROW 11 X+

D11

ZONE INPUT 0

DATA ROW 10 X+

ZONE INPUT 1

DATA ROW 1 X+

ZONE INPUT 2

DATA ROW 2 X+

ZONE INPUT 3

DATA ROW3 X+

ZONE INPUT 4

DATA ROW4 X+

ZONE INPUT 5

DATA ROW 5 X+

ZONE INPUT 6

DATA ROW6 X+

ZONE INPUT 7

DATA ROW 7 X+

ZONE INPUT 8

DATA ROW8 X+

ZONE INPUT 9

DATA ROW 9 X+

Signal

Table 7-5
CR8-E/CM8-E Recommended Spare Parts
DEC Part Number
19-9971
19-9705
19-9704
19-9373
19-9686
19-9594
19-9050
19-9004
19-5580
19-5579
19-5577
19-5576
19-5575
19-5547

Description

Quantity

IC DEC 6380
IC DEC 8881
IC DEC 314
IC DEC 9601
IC DEC 7404
IC DEC 8251
IC DEC 7475
IC DEC 7402
IC DEC 7450
IC DEC 7440
IC DEC 7420
IC DEC 7410
IC DEC 7400
IC DEC 7474
(continued on next page)

7-18

Table 7-5 (Cont)
CRB-E/CMB-E Recommended Spare Parts

DEC Part Number

Description

16-5528
10-0025
10-0016
10-0067
10-1610
70-7252

Delay Line, 30 ns
Capacitor, 560 pF, 100V, 5% DM
Capacitor, 100 pF, 100V, 5% DM
Capacitor, 6.8 /IF, 35V, 20% S. TANT.
Capacitor, 0.01 /IF, 100V, 20% DISK
Cable, Card Reader Interface

7-19

Quantity

PART 7
MAGNETIC TAPE

CHAPTER S
TOS-E OECT APE CONTROL

SECTION 1 INTRODUCTION

The TD8-E Simple DECtape Control is used to control a TU56M or TU56MH Tape Drive Unit (Figure 8-1). The
TD8-E controls the assembly and disassembly of data to be read from or written onto the DECtape and provides
control signals to the drive unit. The TD8-E logic is on one quad board, Module M868, that is inserted into the
PDP-8/E OMNIBUS and connected to a single or dual TU56M Tape Drive by a 7008447 cable.
The TD8-E controls the direction and motion of the tape drive unit with signals generated by flip-flops in the
Command Register. The Command Register allows the TD8-E to select even or odd tape drive, start and stop, move
forward or reverse, and read or write by changing the state of four flip-flops. These flip-flops are controlled by an
instruction (SDLC) that loads the Command Register with four bits of data from the AC.
The assembly and disassembly of the 12 data bits takes place in the Data Register. The Data Register contains the
gating and register necessary to receive data from and place data on the OMN IBUS. The Data Register takes serial
data from the tape during a read operation and puts serial data on the tape during a write operation. *
INT 1/0

~
1/0
DECODER

-CONTROL SIGNALS
I--

DATA 0-11
FROM AC
TO AC

DATA 0-11

READ

DATA
REGISTER

WRITE

TU56M
OR
TU56MH
TAPE
DRIVE

MARKTRACK SIGNALS
CONTROLS
STATUS AND
MARKTRACK

CONTROL
LOGIC

8E-0277

Figure 8-1 TD8-E Block Diagram
*See the PDP-8IE & PDP-BIM Small Computer Handbook, page 7-161, for more detailed information on DECtape formatting.

8-1

SECTION 2 INSTALLATION
The TDB-E is installed on site by DEC Field Service personnel. The customer should not attempt to unpack, inspect,
install, checkout, or service the equipment until a Field Service representative is present.
S.1

INSTALLATION

Perform the following to install the TDB-E System.

Step

Procedure
Ensure power is off.

Ensure jumpers are installed on the MB6B to select the correct I/O code for this TDB-E
System (see Table B-3 for a list of device code jumpers to be installed and unit numbers).

Insert the MB68 Module into the OMNIBUS (see Volume 1 for module priority).

Ensure that the jumpers are installed on the M960 Module (Table 8-2).

Connect the 7008447 cable. P3 goes to J1 on the M868 Module and P1 to location A6 or A7
and P2 to location AB10 or AB11 in the TU56M (Table 8-11.

Ensure that the G742 Module has been installed in place of the M531 and the GB88s are
installed in the TU56M Drive Unit.

Ensure that the power is wired according to power wiring print TD8-E-3 for the
configuration used.

S.2 ACCEPTANCE TEST
Perform the following to check the TD8-E System.

Step

Procedure
Run the Formatter Program (DEC-8E-EUZC-D) on each drive. Follow instructions in the
formatter document. If testing a TU56M (Dual Drive) swap the formatted tapes from one
drive to the other to run the diagnostic test.
NOTE
The Formatter will run only on TDS-Es with device code 677X
(only on units 0 and 1).

Run the Diagnostic Programs (MAINDEC-08-DHTDA). Refer to the diagnostic document
for instructions necessary to run the diagnostic.

S.3 TDS-E INTERFACE
A 7008447 cable is used to interface with the TU56M Tape Transport (Table B-1). M960 and M961 Connector
Modules are used to connect to the TU56M. The M960 Module is used as connector P1 and the M961 Module as
connector P2. The M960 Module has unit selection jumpers that must be installed to select the correct unit. Jumpers
are installed between split lugs as indicated in Table B-2 to select the proper unit code for the unit.
8-2

Table S-1
TDS-E Signal Interface
J1 (P3)
on TDS-E

Wire
Color

NN
MM

Black
Brown
Red

SS
JJ

Orange
Yellow

HH
RR
PP
LL

Green
Blue
Violet
Gray

Logic on
M9600r M961

M960 Module
Pin No.
M1
C2
E1
H1
C2
B1
D1
C2
J1
C2
V2
E2
H2
K2
M2
P2
S2
T2
C2
P1
C2
S1
C2
C2

t{>
--~-o

~u --:--0
----0

- - -~--o
c n~-O

c -- f--~-O

__6__ 0

n--I._o
KK
N
M

T
S
AA
BB

White
Black
Brown
Red
Orange
Black
Brown

EE
FF

Red
Orange

H
J
E
F
W

Yellow
Green
Blue
Violet
Gray
White

CC
DD

Black
Brown

Y
Z
K
L
C
D
U
V

Red
Orange
Yellow
Green
Blue
Violet
Gray
White

M961 Module
Pin No.

AA1

C{;

AB1
AC2
AC1
AD1
AC2
AK1
AC2
AM1
AC2
AR1
AS1
AC2
An
AV1
AC2
SA1
AC2
BBl
AC2
BEl
AC2
BKl

t{>
t{>
L¢

8-3

Description
Time Mark Enable
Ground
Reverse
Forward
Ground
Stop
Go
Ground
Con All Halt
Ground
Unit 0
Unit 1
Unit 2
Unit3
Unit4
Unit 5
Unit 6
Unit 7
Ground
Select Echo
Ground
Write Echo
Ground
Ground
Write Time
Track Pulses
Write Time
Track Pulses
Ground
Word 0
Ground
Read Time Track
Ground
Read Mark Track
Ground
Word 2
Word 2
Ground
Word 1
Word 1
Ground
Word Enable
Ground
Read 1
Ground
Read 0
Ground
Read 2

Table 8-2
M960 Module Jumpers
Octal Code

Unit Numbers

677X
676X
675X
674X

I nstall Select Jumpers

o and 1

2 and 3
4 and 5
6 and 7

SECTION 3 FUNCTIONAL DESCRIPTION
The TDB-E M868 Quad Module is inserted into the OMNIBUS and used to control either the TU56M or TU56MH
Tape Drives. The PDP-8/E System can have as many as four TD8-E Modules on the OMNIBUS to control a
maximum of 8 tape units (4 dual drive). For each TD8-E System purchased, the user also receives one H716 Power
Supply to supply +5 Vdc and -15 Vdc to the TU56M DECtape. The TU56MH (tabletop model) does not receive the
H716 Power Supply.
8.4 INSTRUCTION AND STATUS BITS
The TD8-E uses the following instructions:
Simple DECtape Skip on Single Line Flag (SDSS)
Octal Code: 67X1
Operation:
Skip if Single Line flag is set.
Simple DECtape Skip on Time Error (SDST)
Octal Code: 67X2
Operation:
Skip if Time Error flag is set.
Simple DECtape Skip on Quad Line Flag (SDSQ)
Octal Code: 67X3
Operation:
Skip if Quad Line flag is set.
Simple DECtape Load Command Register (SDLC)
Octal Code: 67X4
Operation:
Load Command Register from the AC, clear Time Error, and start UTS Delay if UNIT,
DIRECTION or STOP/GO flip-flops are changed.
Simple DECtape Load Data Register (SOLD)
Octal Code: 67X5
Operation:
Load Data Register from the AC, do not clear the AC, and clear Single Line and Quad
Line flags.
Simple DECtape Read Command Register (SDRC)
Octal Code: 67X6
Operation:
Load contents of Command Register, Mark Track Register, and Status bits into the AC.
Clear Single Line and Quad Line flags.
Simple DECtape Read Data Register (SDRD)
Octal Code: 67X7
Operation:
Load contents of Data Register into the AC, and clear Single Line and Quad Line Flags.

8-4

The X in the octal code of the instruction indicates one of four different I/O codes used so that four TD8·E modules
can be used on the PDP·8/E OMNIBUS. The I/O codes used are 677X, 676X, 675X, and 674X. The first two TD8·Es
ordered will have I/O codes 677X and 676X, respectively. If three or four TD8·Es are ordered, they will have codes
675X and 674X, respectively. The jumpers to be installed to select the correct device code and the unit number to
select the correct unit on the TU56M are shown in Table 8·3.

Table 8·3
Device Code Jumpers
Octal Code

Install Select Jumpers

Unit Numbers

677X
676X
675X
674X

W2 and W4
W2 and W3
Wl and W4
Wl and W3

o or 1
2or3
4 or 5
6 or 7

8.5 FUNCTIONAL OPERATION
Figure 8·2 is a functional block diagram of the TD8·E Simple DECtape Control. For discussion purposes the TD8·E
is broken into functional groups of logic. Section 4 contains a detailed discussion of each logic group.

PDP8-E

TD8-E

TU56

RUN 101

CON ALL HALT

-I UTS
MO 3-8
MO 9-11

JIO
DECODER

110 PAUSE

f------<
I-----

INTERNAL I/O
8 C1
TP3

GEN

TIM
WRT
ClK

I"eo",
WRITE TIME TRACK

TIM ENABLE
READ TIME TRACK

lD 8 RD

~
DATA

DATA

DATA 0-11

SINGLE LINE

REG
0-11

SKIP

~ LQUAD LINE

~tr"'
~

1
1

~
~

%
DATA

fFr11

COMM REG

~ I TIME ER

- - -

UNIT
r- == =S{G=
=

FIR

WRITE

DATA
LINES

(WR MARK TRACK)

READ

DATA

LINES

UNIT 0 OR 1
GOISTOP
}

FWD IREV

MOTION
CONTROL

RD/WR

RIW

~RC

[ 1
'----

M.T.
REG

SEL ECHO

WRT ECHO

BITS

v----,.
1'-----1"

READ MARK TRACK

8£-02 is

Figure 8·2 TD8·E Functional Block Diagram

8·5

8.5.1

I/O Decoder

As stated before, there are four sets of I/O codes that determine which of four possible TD8·Es is being addressed.
The decoding is done by two jumpers connected to MD7 and MD8. When the correct code for the TD8-E goes to the
I/O decoder and an I/O PAUSE is present an INTERNAL I/O is generated to allow decoding of bits MD 9-11 and
generate an INTERNAL I/O L. The INTERNAL I/O L will prevent the positive I/O bus interface from generating
lOTs while this operation is under way and will generate an enable signal (CC67X) to allow bits MD 9-11 to be
decoded. MD 9-11 are decoded and control the transfer of data and commands to the Data Register, Command
Register, and Mark Track Register. TP3 is used as a timing signal throughout the control logic. CO and Cl determine
the direction of data flow to and from the AC, and determine if the AC is cleared or not.
8.5.2 Command Register
The Command Register is made up of four flip-flops which are loaded from the DATA BUS by the SDLC
instruction. 1s set the flip-flop and Os clear it.
UNIT

Selects which drive on the TU56M is to be used. If UNIT is cleared, Unit 0 is selected.

F/R

Determines which direction the tape is to move. If F/R is cleared, direction is Forward (CW).
CAUTION
Because of circuit delays in the TU56M, the SDLC instruction to
simultaneously change the F/R flip-flop and the S/G flip-flop should
not be executed. If this instruction is executed, the brake signal in
the TU56M will be applied to the wrong motor, causing the tape
drive to drift much further down the tape (in the direction it was
going) than it normally would if the brake were applied to stop tape
movement.

S/G

Tells the selected unit to move tape or stop. If S/G is cleared, the selected tape will stop. The
GO signal is delayed 200 ns after an SDLC instruction to ensure that the unit select line has
had time to switch in the Tape Drive Unit before the tape starts to move.

R/W

Instructs the selected unit to read or write data. If R/W is cleared, a read operation will take
place; if it is set, a write operation is executed.

The SDLC instruction also starts the UP TO SPEED (UTS) delay time and clears the TIME ERROR flip·flop. Figure
8-3 shows the format of data loaded into the Command Register when the SDLC instruction is executed.

0
UNIT

FIR

SIG

R/W

I·

NOT USED TO LOAD
COMMAND REG I STER

I
·1

8E-0289

Figure 8-3 Format of Data Loaded into the Command Register

Any time an instruction is executed to change the Command Register, except when the R/W flip-flop is changed, it
starts a new delay timeout of 120 ms; at the end of this time, the UTS will set again. UTS will not set when the S/G
flip·flop is cleared.

8-6

The R/W flip·flop is cleared (set to a read condition) by any of the following:
a.
b.
c.
d.
e.

SEL ERR
TIME ERROR
WRITE LOCKOUT
POWER NOT OK
INITIALIZE (Clears all logic)

8.5.3 Data Register
The Oata Register contains the gating and register necessary to take data from the OMNIBUS and put data in the
OMN IBUS. It also receives data from the tape during a read operation and places data on the tape during a write
operation.
8.5.4 Mark Track Register
After UTS is set, the Mark Track (MT) Register constantly reads data from the mark track. The mark track data is
read bit by bit, and tested by a Single Line Flag (SLF). Each time SLF is set, a new bit has been shifted into the MT
Register. All decoding of mark track data must be done by the program.
The MT Register is cleared by the start of a UTS delay to ensure that no erroneous codes are left in from a previous
operation. The program must be delayed at least six Single Line flags after UTS has timed out to ensure at least one
complete mark track code has been shifted into the Mark Track Register. This delay ensures a valid code has been
shifted into the register.
The contents of the MT Register are transferred to the AC using an SORC instruction which also transfers the
STATUS bits and the contents of Command Register at the same time. Figure 8·4 shows the format of the word
used for this transfer.

0
UNIT

FIR

SIG

R/W

WLO

SEll
TIMING
ERROR

MTRO

MTRI

MTR2

MTR3

MTR4

MTR5

8E-0288

Figure 8-4 Format of Word Transferred to AC

8.5.5 Flags and Status Bits
The Single Line flag is set each time the OECtape reads one line of tape and is used to detect codes on the Mark
Track as discussed in Paragraph 8.5.4. The Single Line flag is cleared by a not·up·to·speed condition and when an
SOLO, SORC, or SORO instruction is executed.
A Quad Line flag is set once for each four lines of data read from the tape. Testing the Quad Line flag allows the
program to read or write a full 12·bit word. The Quad Line flag is cleared by NOT UTS or by SOLO, SORC, or
SORO instructions.
TIME ERROR is an indication that the program did not go back to the control in time to work on the Oata Register
before.the next transfer of the OECtape took place or that the program was executing an SOLO, SORO, or SORC
instruction when the OECtape requested another transfer. If the control has been writing data, TIME ERROR clears
the R/W flip·flop to ensure that erroneous data is not written on the tape. TIME ERROR is ORed with SEL ERR
and put onto the OMNIBUS during an SORC instruction (Figure 8·4).

8-7

SEL ER R is sent to the TD8-E by the TU56M to indicate that no unit has been selected or more than one unit has
been selected. SEL ERR has no effect on the TD8-E logic, but is transferred from the Command Register to allow
the program to make decisions on what to do about the error.
WRITE LOCKOUT is sent to the TD8-E by the TU56M to indicate that the unit selected for writing was not write
enabled. WRITE LOCKOUT clears the R/W flip-flop and has a status bit for transfer to the AC during an SDRC
instruction (Figure 8-4).
8.5.6 Time Pulse Generator
The Time Pulse Generator and its logic reads a signal from the time track and produces full- and half-cycle pulses on
the rising and falling edges of the time track signal. These pulses are required to read data from and write on the
tape.
The time pulses are gated with and synchronized by the UTS flip-flop so that pulses will be produced when the tape
is up to speed. There is a discriminating delay in the Time Pulse Generator to ensure that noise crosstalk picked up
by the time track head during write operation is not converted into extra time pulses.
The Time Generator has a clock to produce the time pulses required to write the time and mark tracks. The time
track is written directly from a complementing flip-flop in the Time Generator, and the mark track is written from
DATA bit O. The read time track line is gated off while writing the time and mark tracks to ensure that noise coming
off the time track does not generate ~nwanted pulses.
8.6 TD8-E TIMING
The TD8-E timing discussed in this section does not indicate the correct way or the only way to program the TD8-E.
The information presented here is meant only to show the interaction between groups of logic when various
instructions are executed.
8.6.1 Timing for Writing Time and Mark Tracks
The time and mark tracks are written to format the DECtape for writing and reading data. Data to be written on the
mark track is transferred from the AC to the DATA BUS in bit positions 00, 03, 06, and 09 (see the PDP-8/E &
PDP-8/M Small Computer Handbook for the format of data on the tape). Figure 8-5 is a timing diagram for writing
the mark. arid time tracks (formatting). Note that the TIM Enable switch, S 1, must be set to WTM to enable writing
the time and mark tracks (Table 8-4 for signal functions). DEC-8E-EUZC-D gives instructions for formatting
DECtapes and the DEC-8E-EUZC-PD Tape Formatter should be used to format all tapes.
8.6.2 Write Data Timing
The timing diagram in Figure 8-6 shows the timing necessary to write data on the DECtape using the TD8-E. The
data to be written is transferred to the TD8-E from the AC and written on the tape in four 3-bit bytes in the tape
block determined by the programmed instructions. Note that the RTT time pulses must be written on tape using the
Formatter prior to writing data.
8.6.3 Read Data Timing
Figure 8-7 shows the timing required to read data and the mark track from the TU56M DECtape (see Table 8-4 for
signal functions).

8-8

I-.n""~~..
~EENOTE3
8.3",---1

---Ir-"'OONS

TPG elK H

iP==

TPG 0 (01
(WTT (1))

TPG I (01 _ _ _J

SYNC (I)

TT EDG

NOISE DLY (1)

OTP

DTPQ
OTPI _ _ _ _ _ _- J '-_ _ _ _ _ _Jl..._ _--I

SDLe ---SOME TIME IN PROGRAM---------------

UNIT

FIR

S/G

R/W

_ _ _ _ _ _ _ _ _ _ _ _ _ _--' SEE NOTE 1
W

Q.L.F. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

L......_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

SOLD

COMP

WO _ _ _~

(TO

SEE NOTE 2

NOTES
1

The GO s'qnall\ 'wItched on by COmp"lp.r TP4 to "liow SftllHHI of tile U'lIl S~leel LInes

DLJronq formalHng the M"r~ Tr~tk" written from tha B,\ 0 L{HjIC

Al rh,s llmH the IdS! of the Enn ZOCle Code, hos been w"w'"

The p'oq'dn SlOp, 1hO' t"pp ,,,,,I tllP WTr.l

Figure 8.. 5 Timing for Writing Mark and Time Tracks

[ZI/Zwf>//;
NOTE 3-

Table 8-4
TDS-E Signals and Signal Functions
Signal

Function

CON ALL HALT

Signal sent to the TU56M to stop the tape drive if the computer program stops. The loss
of the RUN signal from the processor will cause the TU56 to stop. CON ALL HL T stops
an unselected drive that might be moving tape, clears the S/G command flip-flop to stop
the selected drive, and clears the R/W command flip-flop to keep from writing while the
drive comes to a stop.

F/R

F/R (Forward/Reverse) will control the direction of tape rotation. If F/R and S/G in the
Command Register are set, the tape, moves in reverse (CCW); if F/R is cleared and S/G is
set, the tape will move forward (CW).

INITIALIZE

Signal generated by Clear key, Power Up, and CAF instruction used to clear all flags and
control registers.

RDO
RDl
RD2

Four bits of serial data are taken from the three parallel tracks and assembled in the Data
Register as a 12-bit word. The word is then transferred as 12 parallel bits to the DATA
BUS as indicated below:
RDO
RDl
RD2

RMT

Data, 00, 03, 06, 09
Data, 01, 04, 07,10
Data, 02, 05, 08, 11

Read Mark Track is 6-bits of serial data from the mark track of the tape. The mark track
codes and their functions are as follows (Figure 8-8):

Code

Name

Function

REVERSE END ZONE MARK

This code identifies the code for end zone
located at the beginning of the tape. When
moving in the reverse direction, this code
will be read as 22 meaning the end of tape is
near and the program should HALT or
change the direction of tape movement.

INTER BLOCK SYNC

Code 25 is another NO-OP code which lies
between blocks and for several feet in the
inside of the end zone. This code allows for
turnaround time when reading the first and
last block; it is used by the program to
synchronize its timing logic between blocks.

FORWARD BLOCK MARK

The number assigned the block by the Formatter is stored on this cell. When the computer is searching for a block, it transfers
this number into the AC and examines it.
When code 26 is decoded by the program, it
knows that the block number is in the Data
Register and ready to be read into the AC
and compared with the block wanted.

8-10

Table 8-4 (Cont)
T08-E Signals and Signal Functions
Signal

Function

RMT (Cont)
Code
32

Name

Function

REVERSE GUARD MARK
LOCK MARK

These two cells are NO-OP conditions which
give the program time to decide what to do
with the block it has identified.

REVERSE PCC MARK

This is the last cell before a data cell. It is
used to initiate the parity checksum routine.
If the computer is writing, the first 12-bit
word to be written is transferred to the controller during this cell and every four lines
thereafter.

10
10

REVERSE FINAL MARK
REVERSE PREFINAL MARK

These two codes indicate the first and
second data words, respectively; otherwise,
they have no special significance.

DATA MARK

This code simply indicates that a data word
is written on the data tracks. The program
continuously checks to see that the mark
track is coded.

73
73

PREFINAL MARK
FINAL MARK

These codes indicate that the last two words
of data are being transferred.

PCC MARK

The parity checksum which was being calculated by the program during the transfer is
either written here during a write operation
or compared by the program during a read
operation.

73
51

REVERSE LOCK MARK
GUARD MARK

These are NO-OP spaces which become
useful when the tape is traveling in the
reverse direction.

REVERSE BLOCK NUMBER

The block number is stored here to be
picked up by the program when the tape is
traveling in the reverse direction.

INTER BLOCK SYNC

Has the same function as INTER BLOCK
SYNC at the beginning of the tape.

END ZONE MARK

When this code comes up, the program
knows that it has just run out of tape (refer
to REVERSE END ZONE) and that it had
better do something about it. Note that this
code is the complement of 55, the
REVERSE END ZONE MARK.
8-11

Table 8-4 (Conti
TD8-E Signals and Si nal Functions
Function

Signal
RTT

Read Time Track is a 16.6-t.ts square wave signal coming from the time track. Pulses
produced on the rising and falling edges of the time track signal are used to sync the
TDS-E to read and write data.

SEL ERR

Select Error indicates no unit has been selected or that both units have been selected
simultaneously. The software must decide what to do about the error.

SEL ECHO

Select Echo is sent to the TDS-E by the TU56M in response to command signals to
indicate TU56M is on line.

S/G

Stop/Go is sent to the TU56 by the TD8-E to command the tape drive to move in the
direction determined by F/R. This signal is generated by the S/G flip-flop in the
Command Register.

TIME ERROR

Time Error is an indication that the program did not come back to the control in time to
work on the Data Register before the next transfer occurred.

T/M ENABLE

Time Mark Enable allows tape to be formatted by writing on the time and mark tracks
when Sl on the M86S Module is set to WTM.

WOO
WDl
WD2

Twelve bits of parallel data transferred from the DATA BUS to the Data Register and
disassembled by the Data Register to form four 3-bit bytes of serial data. The four bytes
of serial data are written by these three signals on parallel tracks on the DECtape as
indicated below.
WOO
WD1
WD2

Data, 00, 03, 06, 09
Data, 01, 04, 07,10
Data, 02, 05, OS, 11

WTT

Write Time Track is a 16.6-~s square wave signal written on the time track when the tape
is formatted.

WRITE LOCKOUT

Write Lockout is sent to the TDS-E by the TU56M to indicate that the unit to be written
on is not write enabled. This signal will clear R/W in the Command Register and select the
Read mode.

WD ENABLE

Word Enable is generated when R/W on the Command Register is set and UTS is set to
allow writing data on tape.

UTS

Up To Speed is negated by any change in the Command Register except R/W. After a
delay of 120 ms to allow tape to come up to speed, UTS is again asserted to allow reading
or writing data. UTS is used to enable RTT or WTT time pulses.

TPGO
TPG1

Time pulses from the Time Pulses Generator which are produced by the rising and falling
edges of the RTT signal (WTT signal while formatting).

QLF

The Quad Line flag is set each time four lines of data are transferred to or from the tape,
so that by testing this line the program will know when a full 12-bit word has been read
or written. QLF is cleared by NOT UTS, instructions SOLD, SDRC, SDRD or
INITIALIZE.
8-12

Table 8-4 (Cont)
T08-E Signals and Signal Functions
Signal

Function

SLF

The Single Line flag is set each time the OECtape transfers one line of data and is used to
detect mark track codes. SLF is cleared by NOT UTS, instructions SOLD, SDRC, SDRD
or INITIALIZE. SLF is ignored while reading or writing data.

NOISE DLY

Noise Delay is a 10-I1S delay generated by the Time Pulse Generator to prevent the noise
picked up by the time track head during a write operation from generating extra time
pulses.

SYNC

The SYNC is used to generate and separate the TPO and TP1 pulses required to read or
write.

8-13

RRT
(FROM R/W AMP)
DTPO

__~~~~~~~__~~~~~~~~~~~:II I I I

DTPl

S.L.F.

: ~,---~~=·. ~=/~=a=/8ii=.·/"=;

SDRC

~'S-E-E--N-O-TE--l------------~UJr-S-E-E--N-OT-E--2-----------------------------------------------------------11 1!-----------------------nr-S-E-E-N-O-T-E--2-a--4-----

Q.L.F.

1st Q.L.F.
[J2ndi.l I 130th Q.L.F.
__________________________~.~.____________________~.~.____________________~~A~FT~E~R~R~E~V~.C~K~S~U~M~____~.
~L~A~FT~E~R~R~E~V~.~CK~S~U~M~--__~L------------------

SDLC

RI W R ____________________________- - '

WD ENAB
(TO TU 56)
SOLD

REV. CHECKSUM
TO DATA REG.

1st DATA

WORD

SR 0
SEE NOTE #3
WFO (0)
COMP WD
WOO
(TO R/W A.M.P.)

NOTES

At this point the COMMAND REGISTER is set for the correct UNIT, Fl,IIID, REV, GO. and READ. The
correct block number has been found and at this SLF the REV ERSE GUARD is in the MT register
2.

This SORC loads the status 01 the COIV1 REG into the AC so that the write bit can be out, in, or removed
without changing any other COM REG condition. This also dears the OlF which the SOLe does not

The other two parallel write bits work identically to SRO, VVFO. and WDO.

At this point If any COM REG function other than R/W IS changed, UTS disappears and the TllV'E pulses
stop until UTS DElA Y times out and UTS IS set.

Figure 8-6 Write Data Timing

BE _ 0342

RTT

OTP'----1 ~----L---~--~--~~--~--~--~----L---~---L---J----~~----L---~---L--~~--L---~--~----L---~--~
SOLe
S/G

:~ErE--N-O-TE--'------------------------------~-----------------------1r---------------------------------------------------

::'40m!.r-________________________________________________________
I

~r--------------------------

UTS ----1

RMT~~~~~--Ol
SEE NOTE 2

MTR5

~ SEE NOTE 3

LJI'----_-----'Io:

770)]",.--------,1
r---l
MTR4
L-.J
1

'--______-'!o: ~

,.,~'7A---------------,~

MTRO~

SEE NOTE 4

~:~

LJon

MTR2%a

c::p

'---------~: ~
,0

MTR3

MTR'

,:,

.-------,~jl
,

--------~

LJI

r-D:

S, L. F. ____________-'

.....
(J'1

SORe

Q L. F

-------------------------------------------------------------------1

SDRO

ROO
SR9
SEE

NOTE 6

SR6
SR3
SRO
SEE NOTE 7

TIME
BREAK

nil' GO "qn.I" ,witched on hy c[)mpute! TP4 to allow ,.tlllnq !Orne fo' the UNIT select lin", The UNIT, lJtRECTfON ,,,,,I READ c"""""n,1> ,He ,"' hy

Th" ITlr"t; to dmJ outputs lrom the Md,k T'dck Re9 d'~ ,ed~flned

th,,::'OlC

A 1

Tl1e othe, two 1"""lId R~,'n line, wor~ ,dp"IOc.,lly 'n RlJO, SR~, SR6 SR3, "nrl SRO

Any !Om~ th~ UTS rlel .. y ""dried, the MTR ",e' to <Ill 0, ih.qh o"tr.J11

0,,1." '~" (,,,,,,,, I>lnck ,.",1 n', RE VE RSE GUARD codp., l1.ve b~en 10"n'l th. Sln4'~ L,,,,· F I,'q' ,",. "1"","<1

The MTH " ",>1 I"

k~<I ."

.Iq."n ""1,, ,,,,,,,hl"

Figure 8-7 Read Data and Mark Track Timing

_________________________

I--

CElL

---1

REv END ZONE

INTEA8LOC-K

REVERSE

FORWARD REVERSE GUARD

SYNC

BLOCK MARK

POC

PREfINAL

REVERSE

FINAL MARl< PREFINAl MARK

REVERSE

GUARD
MARK

REVERSE
BLOCK MARK

INTERBLOCK
SYNC

END ZONE
MARK

MARK

TIMING TRACK

~
- -_ _ _ OIRfenON OF MonON

MARK TRACK
MAGNETIC
}

_ _-'---_ _ _' -_ _----'_ _ _--'-_ _ _--'--_ _ _-'--_ _ _' -_ _- '_ _ _-.J

[)AlA STORED HERE

--------+1

- - - - - - I -BLOCK

Figure 8-8 DECtape Data Format

}OATA TRAC"

TAPE

SECTION 4 DETAILED LOGIC
The logic in the TD8-E will be broken into functional groups for discussion purposes. The block diagram, Figure 8-2,
should be used to understand the interaction of the logic, the signal flow within the module, and the input or output
signals.
8.7

INPUT/OUTPUT DECODER LOGIC

The I/O decoder decodes instructions from the Memory Data Bus and generates signals to control the operation of
the TD8-E (Figure 8-9). Bits MD 3-11 are gated by the I/O PAUSE when an I/O instruction is generated. Bits MD 3
to MD 8 generate a signal CC67XH applying bits MD 9, MD 10, and MD 11 to the 8251 IC. The 8251 IC is a
BCD-to-Decimal decoder (see Volume 1, Appendix A, for truth table logic and pin locations) which decodes MD
9-11 and produces a low on one output line. The low out of the 8251 IC indicates which instruction is to be
executed. As an example MD 9 Low, MD 10 and MD11 High (100) produces a low on pin 4 which indicates an
SDLC instruction was programmed. The jumpers for MD 7 and MD 8 will select the device code (see Table 8-3 for
device codes) for multiple TD8-E Systems.

INTER-::L;~~D

CC MD 9 H

/w'O-,-------C4

CC MD '0 H

,------o<"!2
MD7 >----<~

H;s5=COL

JUMPERS

MD 3
MD 4
MD 5
MD 6

C, L

Vee ,..--_ _--,

CC 67X

MD8>-+---4>-(l

CC MD9 H

M D9 >--1---0

I/OPAUSE~

CC MD 10 H

MDlO>--I---O

MD11>----Q

TP3~
-=
CC BTP3 H

2
3
4
5
6
7
8
9

CC SOSS L
CC SDST L
CC SDSQ L
CC SDLC L
CC SDLD L
CC SORC L
CC SDRO L

DEC
825'

CC TP3 L

INITIALlZE:>>--~-f'.- .....
~~~i"-V--- CC INIT L

RUN>----(l(

-CON ALL HALT H

'--- - - - CC INIT H

CC RUN L
'-------CCRUNL
BE-0286

Figure 8-9 I/O Decoder Detailed Logic

8.7.1

Control Logic

8.7.1.1 C Line Select Logic - The C line logic (Figure 8-9) controls the direction of data flow between the DATA
BUS and the AC and determines if the AC is clear or not. Table 8-5 shows the status of CO and C1 to transfer data
between the AC and the DATA BUS using the SDLC, SOLD, SDRC, and SDRD instructions.

8-17

Table 8-5
CoLine Select Levels and Transfer Operations
Instruction

Transfer Operation

SDLC
SOLD
SDRC
SDRD

Low
High
Low
Low

High
High
Low
Low

AC""* Data Bus then a ""* AC
AC""* Data Bus
Data Bus""* AC
Data Bus""* AC

8.7 _'_2 Time Pulse 3 Logic - TP3 shown in Figure 8-9 is used throughout the module to enable gates for execution
of instructions.
8.7.1.3 Initialize Logic -INITIALIZE clears all logic when the computer power is first turned on, when the
CLEAR key on the console is operated, or when the CAF instruction is executed.
8.7.1.4 Run Signal and CON ALL HLT Logic - The loss of the RUN signal from the computer will generate CON
ALL HLT, stopping the tape drive unit regardless of the status of the Command Register. RUN is negated any time
the program stops.
8.8 COMMAND REGISTER
The Command Register (Figure 8-10) consists of the UNIT, ForwardlReverse (FIR). StoplGo (S/G) and ReadlWrite
(R/W) flip-flops. The flip-flops in the Command Register are set or cleared by AC 0-3 when the Command Register
is loaded by the SDLC instruction (Paragraph 8.5.2).
8.8_1

Unit Select Logic

The UNIT SEL flip-flop determines which TU56M unit is selected. The UNIT flip-flop sets when bit a from the AC
is a 1, and it is clocked into the flip-flop by TP3 during the execution of an SDLC instruction. If UNIT flip-flop is
cleared, Unit a is selected. SDLC and TP3 clear the UNIT flip-flop if the data input is low (AC bit a is 0)_
8.8.2

ForwardlReverse (FIR) Logic

The FIR flip-flop (Figure 8-10) determines the direction of tape movement. When an SDLC instruction is performed
and bit 1 from the AC is a 1, the FIR flip-flop sets and directs the tape drive to move backward. If the data input is
a (bit 1 from the AC is 0) FIR clears when the SDLC instruction and TP3 are applied to the clock (C) input, and the
drive is directed to move forward.
8.8_3 Stop/Go Logic
The stop/go logic (S/G) flip-flop (Figure 8-9) enables the tape to move in a direction determined by the FIR
flip-flop. If AC bit 2 is a 1 when the SDLC instruction is performed, the SIG flip-flop sets. The output of the
flip-flop is applied to a latch which also has TP4 as an input. TP4 clocks the latch 300 ns after SIG is set and pulls
latch output low. The 300-ns delay allows the unit select lines to settle before the S/G signal is applied to the
TU56M. S/G is ANDed with POWER OK to remove the GO signal from the TU56M during a power down. Power in
the TU56M does not drop as quickly as power on the PDP-8/E and the tape may continue to run and write
erroneous data.
Loss of the RUN signal from the processor generates CON ALL HL T to the TU56M and clears the SIG flip-flop.

8-18

Vee

S/G (11 H

OF DB 2 H
CC FIR (1) H
OF DB

1 H

CC UNIT (1)H
OF DB 0 H
OF O B O H - - - - - - - - - - I O
CC INIT H
UNIT
CC TP3 L
CC SOLC L---.,,--,""---_/

CC S/G (0) H

TP 4

l----.- c

0
SET
OLY
C

CC CLR TE L

OF DB 1 H

-+----+---1----1 0
FIR
O~------~

CC INIT L

.....

OF DB 2H

0
S/G
C

CC INIT H
-CC RUN H

CC OTP 0 L
OF DB 3 H

0
R/W

OF SEL ER L
OF WLO L
OF TIME ER L
CC RUN L
CC INIT L

CC WRT OK H

-POWER OK

8E - 0287

Figure 8-10 Command Register and UTS Logic

8.8.4 ReadlWrite Logic
The Read/Write flip·flop (R/W) (Figure 8·10) selects the read or write mode in the TU56M. If bit 3 from the AC is a
o when the SDLC instruction is executed, R/W will clear and the TU56M will not write on the tape. If bit 3 is 1
when the SDLC instruction is executed, RIW sets, and its output is applied to-the reset input of a latch. D TPO is
applied to the set input of the latch. When D TPO is received from the Time Pulse Generator, the outputs of the
latch will be low if R/W is set. The latch output is ANDed with NOT CC T/M EN, which enables the gate when Sl is
set to OFF (Figure 8-11). The output of the first gate is ANDed with POWER OK H to generate WD ENAB, causing
the TU56M to write on the DECtape. WD ENAB is ANDed with POWER OK to remove WD ENAB from the TU56M
during a power down of the system. RIW is also cleared by any of the following conditions to select read mode and
remove WD ENAB from the TU56M.
a.
b.
c.
d.
e.
f.

SEL ERR
TIME ERROR
WRITE LOCKOUT
POWER NOT OK
INITIALIZE
NOT RUN

The DECtape can read or write in both directions, but the program must take care of the obverse complement data.
8.9 UTS DELAY LOGIC
The UTS delay logic starts a 120-ms delay after S/G is set, to ensure the tape is up to speed before data is read from
or written on the DECtape (Figure 8-10). Any change in the Command Register, except R/W, clears the UTS
flip-flop and starts a new 120-ms timeout. The D input of SET DL Y is enabled by the Exclusive-OR gates which
cause SET DL Y to set if the UNIT, S/G, or F/R flip-flops are changed, thus clearing UTS and starting another
120-ms delay. The following conditions set the SET DL Y flip-flop clearing UTS:
a.
b.
c.

S/G =1= DF DB 2 (AC Bit 2)
F/R =1= DF DB 1 (AC Bit 1)
UNIT =1= DF DB 0 (AC Bit 0)

If SET DLY is set, the 74123 IC is triggered and starts a new 120-ms timeout. After 120 ms, if no new changes are
made in the Command Register, the clock input of the UTS flip-flop goes high. This transition causes UTS to set if
S/G is set supplying a true (high) to the D-input. UTS will not set if the S/G flip-flop is cleared. Any time UTS is
cleared the TT ENABLE flip-flop (Figure 8-11) will clear and disable the Time Pulse Generator logic. The SET DL Y
flip-flop is cleared by TP4 of each CC SDLC instruction that changes the Command Register. This is to ensure that
the 120 ms (74123) can trigger on each CC SDLC and the only timeout is 120 ms after the last SDLC.
When SET DLY clears it also clears the Mark Track Register (Figure 8-14, Paragraph 8.11).
8.10 TIME PULSE GENERATOR
The Time Pulse Generator (Figure 8-11) has two functions, one is to produce pulses to write the time and mark
tracks (formatting) and the other is to produce timing pulses from the time track signal (RTT) to allow reading and
writing of data. The WIT signal, a 33.2-J,Ls square wave, is written on the time track of the DECtape when the tape is
formatted. The Time Pulse Generator reads the RTT signal from the timing track of the tape when data is read from
the tape or written on the tape. Full- and half-cycle pulses (Figure 8-5, signals DTP, DTPO, and DTP1) are produced
on the rising and falling edges of the time track signal. The time pulses are synchronized with the UTS flip-flops so
pulses will be produced only when the tape is up to speed.

8-20

OTP

CC OTP1 L

) - 4 - - - c c OTP' H
o
CC TPG

a (1 ) H
CC DTPO L

} 4 - - - c c DTPO H

CC TPG a (0) H
CC TIM EN H

CCUTS(l)L

-cc TIM EN L
[CCT/MENHl

TT EN

o
CC UTS (0) L

cc TPGO (1) H
TPG elK H

~~'-+-~-L----'
~
IQ[F]

TPGl

CC TIM EN H

CC TIM EN L
BE-0279

Figure 8-11

Time Pulse Generator logic

8.10.1 Write Time Track Pulses
The Write Time Track (WTT) pulses are produced by a 74123 IC (Figures 8-5 and 8-11) and two flip-flops (TPG 0
and TPG 1) arranged in a conventional switch-tail ring counter. The 741231C outputs a pulse every 8.3 IlS when 51
is set to WTM. 51 removes the low level from the clear input in the 74123 IC and enables the input gate, which
allows the 74123 IC to be triggered. The TIM ENAB signal is also sent to the TU56M to allow writing on the time
and mark tracks. CC T/M EN is ANDed with WRT OK to remove TIM ENAB from the TU56M during a power down
of the PDP-8/E, and any other condition that clears the R/W flip-flop.
The 74123 used to generate TPG ClK H is a retriggerable monostable multivibrator (one shot) that is set for 8.3 IlS.
External circuitry causes this one shot to retrigger itself on its own trailing edge. An inverter and integrator on the
output of the 74123 IC delays the triggering process for 100 ns, establishing a minimum width for TPG ClK H. TPG
o and TPG 1 produce overlapping 33.2-lls square wave pulses (Figure 8-5). The leading edge of TPG 0 occurs 8.3115
before the leading edge of TPG 1. The 0 output of TPG 0 is applied to the time track (WTT) signal. The outputs of
TPG 0 and TPG 1 are also used to produce DTPO and DTPl when writing the time and mark tracks. Gates C and D
(Figure 8-11) must be enabled to apply these signals to the control logic to allow writing on the time and mark
track. CC T/M EN H is applied to C and D when 51 is set to WTM during a write operation and CC TPG 0 (1) H or
CC TPG 0 (0) H are applied to the gates during a write. The source of the DTP signal is explained below.

8-21

CC TPG is combined in an Exclusive-OR gate with the output of SYNC. The output of the Exclusive-OR gate goes
high when SYNC (1) Hand CC TPG 1 (0) H are equal. The 741231C is triggered only on the rising edge of its input
signal, and the SYNC flip-flop is complemented each time the 10-J,ls 74123 times out. Thus, the SYNC flip-flop
changes state about 7 J,lS before CC TPG 1 changes state, this allows TT EDG to go low for about 7 J,ls. When CC
TPG 1 switches to the same level as SYNC, then TT EDG again goes high retriggering the 10-J,ls 74123 (NOISE
DL YI. Once the NOISE DL Y is triggered its output holds TT EDG high (through an OR gate) thus preventing any
cross-talk noise coming from RTT (0) from retriggering the delay.
Note (Figure 8-5) the rising edge of NOISE DL Y occurs in the center of CC TPG 0 (WTT). This produces a 90 degree
phase shift between the writing of the time track and mark track. The phase shift is required so that when the time
track (RTT) is read back during a normal data transfer, the time pulses used to strobe in the mark track occur in the
center of the mark track signal.
The rising edge of the 10-J,ls 74123 IC (NOISE DLY) triggers the 100-ns 74123 and produces a 100-ns pulse (DTP).
DTP is produced on every edge of CC TPG 1 and is applied to AND gates C and D. When CC TPG 0 (0) is high, D is
enabled and CC DTP 0 H is produced; when CC TPG 0 (1) is high, C is enabled and CC DTP 1 L is produced. This
separates the DTP pulses into two pulse trains, one has pulses on the rising edge of CC TPG 1 and the other has
pulses on the fall ing edge of DTP 1.
Most signals in the Time Pulse Generator (Figure 8-11) are gated against CC TM EN. This is done to ensure the logic
required for writing the time and mark tracks is enabled only for that operation and the logic to read and write data
is gated off. The reverse is true when reading the time track and transferring data.
8.10.2 Read Time Track Pulses
The RTT signal read from the time track is used to produce time pulses (Figures 8-11 and 8-12) which allow data to
be transferred to or from the DECtape. To supply time pulses (CC DTPO and CC DTP1) AND gates A and B must be
enabled by DTP, SYNC, and TT EN. TT EN is set by the first falling edge of NOISE DL Y after UTS is set. This
ensures that time pulses are not produced while the tape is getting up to speed. TT EN is cleared by the loss of the
UTS signal.

RTT
(FROM TU561--!

SYNC

1--'6.6~s

I'I _ _~

TT EOG

NOISE

OLYI'I

~
OT P

I-- '" lO~s

'" 100NS

---I..1--L1--L1--L1--L1--11---11--J1'--I...-1.1...-1.L--I..1..-1..1..-1...1.-1...1.-1-,--I-L. . .I. . .1-1-,-I-,-I-,-I-,-I--,-I--,-I--1. .1____1--,-1_

UTS I' I _ _ _ _- '

---II

TT ENI,, _ _ _ _

",lOONS

DTPO _ _ _ _ _~I

__:1L_33_.3_U_S~~

_ _L__~_ _L__~_ _~_~_ _~_ _ _ _ _ ___

" 100NS

1~3_3_.~_S_'r~_~_~~_ _'__~_ __'__~_ _ __'__~___________

DTP' _ _ _ _ _ _ _

Figure 8-12 Read Time Track Pulse Timing

8-22

Note the WTM switch must be OFF when tapes are not being formatted. If it is in the WTM position and the tape
moves (but it is not being formatted) the time and mark tracks will be destroyed and the tape must be formatted.
The third leg of gates A and B is enabled by DTP out of the 100-ns monostable multivibrator which is triggered by
the rising edge of the 10-J,Ls NOISE DL Y.
The logic to produce CC DTPl and CC DTPO is the same as that for writing the time track. The only difference is
that now the signal that generates these pulses is the time track (RTT) coming from the TU56M, rather than being
generated on the M868. The SYNC flip-flop separates the DTP pulses through gates A and B, rather than CC TPG 0
and gates C and D.
As before SYNC is one input to the Exclusive-OR gate which triggers the NOISE DL Y every time RTT and SYNC
are at equal levels. The result is that DTP is produced on each edge of the RTT signal (Figure 8-12). When SYNC is
set gate A is enabled and the DTP produced on the rising edge of RTT goes through gate A and comes out as CC
DTPO. When SYNC is cleared, gate B is enabled and DTP produced on the falling edge of RTT goes through gate B
and comes out as CC DTP1.
Thus, the time pulses are produced to shift in the data, set the flags, set WD ENAB (Figure 8-10) and shift the data
out for writing, etc.
8.11

FLAGS AND SKIP LOGIC

The Single Line flag and Quad Line flag are used to count lines of data read from or written onto the tape and to
enable skip logic when the CC SDSS or CC SDSQ instructions are performed (Figure 8-13). Time Error flag indicates
the timing of a transfer was not correct and enables the skip logic when the SDST instruction is executed.
8.11.1

Single Line Flag

The Single Line flag (SLF) is used to detect codes on the mark track. SLF is set by CC DTP1 each time a line of data
is read from the DECtape. If SLF is set and the SDSS instruction is executed, the SKIP line on the OMNIBUS is
grounded, causing the program to skip to the next instruction. The SKIP could cause a subroutine to be performed
to determine what code is in the Mark Track Register and take action accordingly; i.e., is the code a Block Mark? If
so, read the Data Register, and check to see if it is the block number required. Is it an End Zone Mark? If it is, then
you have run out of tape; stop, then reverse direction to continue. SLF is ignored by the program after the correct
block of data has been found, as the program must keep track of the number of words being transferred and put the
parity word at the end of the data.
8.11.2 Quad Line Flag and Counter Logic
The Quad Line Flag (OLF) (Figure 8-13) sets each time the counter made up of flip-flops Band C counts up to four,
indicating four lines of data have been read from or written onto the DECtape. DTPl is applied to the clock (C)
input to cause the counter to increment each time a line of data is transferred. When OLF is set and the SDSO
instruction is performed, the SKIP line on the OMNIBUS is grounded causing the program to skip to the next
instruction and call a routine to either load or read the Data Register. The 1 output of OLF is also applied to the
logic to detect a TIME ERROR (Figure 8-13), as stated before SLF and OLF are cleared by instructions CC SDRC,
CC SDRD, or CC SOLD, and the loss of UTS.

8-23

r----'

CC SDSS L
SKIP CS1

1r--t--------------------------------~__~

SINGLE

CC DTP1 H - - - - - - - - - - - - - - - H r - - - - - - - a C LINE
A

o
CC SDSQ L

CC SDST L
~--------+_~aC

CC UTS ( O l L - - - - - - - - - ,
CC B TP3 H - - - - - - - - - - I

CC SDRC
CC SDRD
CC SDLD

L
L
L
DF TIME
ER H

CC IN IT
CC CLR TE

DF TIME
ER L
8E-02e t

Figure 8-13 Single Line Flag, Quad-Line Flag, and Skip Logic

8.11.3 Time Error Flag
The Time Error flag (Figure 8-13) is a latch made from two 7410 gates which sets and generates a TIME ERROR to
indicate the program did not transfer data to or from the Data Register before the next byte has transferred to or
from the tape. Any of the following conditions will generate a TIME ERROR:
a.

QLF (1), DTPO H, and R!W Set (1) (Write Operation)

QLF (11. DTPl H, and R!W Cleared (O) (Read Operation)

If SDRC, SDRD, or SDLD is executed just as the tape is ready to transfer another byte.

TIME ERROR is cleared by INITIALIZE or an SDLC instruction. When TIME ERROR is set and the SDST
instruction is executed, the SKIP line is grounded, causing the program to skip the next instruction.
8.12 MARK TRACK REGISTER
The Mark Track (MT) Register (Figure 8-14) receives serial data from the mark track (RMT) containing the mark
track codes and outputs 6 bits of parallel data for transfer to the AC. The MT Register is made up of two 8271 ICs.
(See Appendix A.8, Volume 1, for timing diagram pin locator and truth table). The 8271 IC is a 4-bit shift register
that receives a parallel serial input and provides a parallel output. The parallel output is applied to the Data Register
(Figure 8-16) for the transfer to the AC during an SDRC instruction.

Vee

Figure 8-14 Mark Track Register
The output of the MT Register has been redefined; i.e., 1 is a low level and a 0 is a high level output.
The MT Register is cleared when SET DL Y is cleared. When SET DL Y is set UTS is cleared, so the CC UTS (1) signal
on the shift input is low. When SET DL Y is cleared it enables the clock input of the 8271, and as the parallel data
output are held high the outputs all go high (redefined as 0 output). As stated before, the program must wait at least
six SLFs before the MT Register holds a real mark track code.
8-25

8.13 DATA REGISTER AND GATING LOGIC
The Data Register (Figure 8-15) receives data from the DATA BUS and converts it to serial data to be written on the
DECtape or takes serial data from the DECtape and converts it to parallel data to be gated to the DATA BUS for
transfer to the AC. The Data Register consists of three 8271 ICs (see Volume 1, Paragraph A.8, for timing diagram,
pin location, and logic diagram) and logic to select the input from the DATA BUS (parallel) or the input from the
tape (serial). The output (the data being written on tape) is taken from SRO, SR 1, and SR2.

Vee

-CC OSLO H
DATA 9

LOAD R
SHIFT
CLOCK
A
SR9
SR6

8271

DATA :3

SR3
SRO

CC SOLD L
CC TP3 L
DATA 10 >--+----<1"

SHIFT
CLOCK

~----------1+--I A

~----------<~ .. ~
DATA 4>---i---<f

SR10

~-~f.--< B

SR7

8271

~----------1~--I C

DATA 1

SR4

}..:....~-I-~-I 0

SR 1

--1--.-+-+--1----1 SERIAL IN

DATA 11 >--+---d

SRll

DATA 8

~----IB

DATA5>--+----<r-~}_---------__4C
},=,:,--=-::'="":':""""-I 0

SR8

8271
SR5
SR 2

CC 67XL--~~------_q

SERIAL IN
8E-0282

Figure 8-15 Data Register

8-26

Three outputs are shifted into the Write Register (Figure 8-17) to be written on tape. The serial input from the
DECtape, ROO, RD1, or RD2 are shifted in by the CC DTP1 pulse and taken from the register as parallel data for
transfer to the DATA BUS (Figure 8-16). The SOLD instruction is applied to the shift input to enable parallel
transfer of data from the OAT A BUS at TP3 time during a loading operation. At other times, the shift input is held
high to enable serial shifting of data through the SR.
8.14 DATA GATING LOGIC
The data gating logic (Figure 8-16) will select the data to be applied to the DATA BUS for transfer to the AC by an
SDRC or SDRD instruction, The SDRD instruction enables AND gates to transfer SRO-SR11 to the DATA BUS.
SRO-SR 11 are the 12 data bits read from the tape, applied to the Data Shift Register as serial data, and output to
the data gating logic as 12 bits of parallel data. The SDRC instruction enables AND gates to transfer the contents of
the Command Register, Status Bits, and MT Register to the DATA BUS.
8.15 WRITE FUNCTION REGISTER
The Write Function Register (WFO, WF1, WF2) receives data from SRO, SR1, and SR2 (Figures 8-17 and 8-6) and
outputs the data to the TU56M at the correct timing pulse times.
At CC DTPO (rising edge of RTT) the data from the Shift Register is loaded into the WF Register. At the same time,
the Complement Word (COMP WD) output of the latch goes high. COMP WD is then compared to the complement
of the data loaded into WF through the Exclusive-OR gates and if they are the same level, the Word (WD) lines go
high. If a 1 had been loaded into WFO at the CC DTPO, then its output would have been low. At CC DTP1 (falling
edge of RTT) COMP WD goes low and WFO will go high. The positive transition at CC DTP1 causes a 1 to be written
on tape. If a 0 had been written into WFO, then between CC DTPO and CC DTP1 the WOO signal would be high.
When COMP WD switches low at CC DTP1, there is a negative transition at WOO and a 0 is written on tape. By
examining the write timing diagram (Figure 8-6) you can see how alternating 1s and Os always produce a negative
transition for a 0 and a positive transition for a 1.
8.16 WRITE ECHO AND SELECT ECHO CIRCUITS
WRITE ECHO and SELECT ECHO (Figure 8-18) are supplied to the TD8-E by the TU56M. A SEL ERR condition
exists if no unit has been selected or both units have been selected. Write Lockout exists if the selected drive unit is
not Write Enabled. The voltage level for these signals and the resulting error condition are shown in Table 8-6.
The SEL ERR and WRITE LOCKOUT ERROR signals are applied to the data gates (Figure 8-16) as status bits to be
transferred to the AC by an SDRC instruction. The software must decide what to do when these errors are detected.
Both errors clear the R/W flip-flop to keep from writing under an error condition.

SECTION 5 MAINTENANCE
Recommended preventive maintenance should be scheduled on a regular basis to maintain the reliability and
performance of the DECtape. Preventive maintenance schedules are found in the TU56 DEC tape Transport
Maintenance Manual, Chapter 6, Paragraph 6.2.
TD8-E DECtape Diagnostic (MAINDEC-OB-DHTDA) and TD8-E Formatter (DEC-8E-EUZC-PB) were written to
checkout and test the TDB-E DECtape Control with TU56M DECtape Transports. The diagnostic program and
formatter check all logic, as well as the ability to read and write. The diagnostic also provides subroutines for
monitoring TDB-E signals with an oscilloscope and display data in the AC. When a malfunction is suspected the
TD8-E Diagnostic should be used to checkout and troubleshoot the TD8-E. Refer to the TU56 Maintenance Manual
for test equipment, troubleshooting aids, and adjustments.

8-27

DF SR 11 H

OF MTR 5 L

-+---<:]

OF MTR 4 L

DF SR

9H-{:>--

DF MTR 3 L

CC SDRD L
READ DATA REG
OF SR

DATA 7

DATA 6

TIME

ER H

SELECT

ER H

DATA 5

DATA 4

OAT A 3

DATA 2

CC
CC SORe L

,~~~~N~R~~~ ------~
+ STATUS BITS

DATA 1

DATA 0

UNIT (1) L

8£-0283

Figure 8-16 Data Gating Logic

8-28

DF SRO H

0
Vee

WFO
C

OF SR 1 H

D
Vee

WFl
C

D F SR 2 H

0
WF2

Vee

CC DTPO L - + - - - - - - r t
>-~---4~- COMP

CC DTP\ L-----~
8E-0285

Figure 8-17 Write Function Register

Table 8-6
Write Echo and Select Echo Signal and Voltage Levels
Signal Voltage Level

Resulting Condition

WRITE ECHO OV (Write Enable)
WRITE ECHO -3V (Write Lockout)
SELECT ECHO -3V (2 units selected)
SELECT ECHO -5V (1 unit selected)
SELECT ECHO -15V (No unit selected)

Write Lockout False
Write Lockout True
Select Error (True)
Select Error (False)
Select Error (True)

8-29

+5V

OF WLO L

ll~
-15V-_--r-----t----r----~----t_----t_--~~~~~~~-+5V
SELECT ECHO

N~r-----~--~~~~~-t~

-9V

-4.7V

>------- OF SEL ER H
' - - - - - - - OF SEL ER L

-15V-4-~~~~~~---------------------------------·----~
8[-0284

Figure 8-18 Write Echo and Select Error Circuits

SECTION 6 SPARE PARTS
Table 8-7 lists recommended spare parts for the TD8-E. These spare parts can be obtained from any local DEC office
or from DEC, Maynard, Massachusetts.

Table S-7
TDS-E Recommended Spare Parts
DEC Part Number
19-10436
19-09935
19-09931
19-09929
19-09712
19-09705
19-10391
19-09686
19-09615
19-09594
19-10394
19-10392
19-09054
19-09050
19-09004
19-05590
19-05578
19-05576
19-05575
19-05547
15-09338
11-00114
11-00113

Description
IC74123
IC 8235
IC DEC 74H04
IC DEC 7417
IC DEC 8242
IC DEC 8881
IC DEC 5314
IC DEC 7404
IC DEC 8271
IC DEC 8251
IC DEC 5384
IC DEC 5380
IC DEC 7493
IC DEC 7475
IC DEC 7402
IC DEC 7401
IC DEC 7430
IC DEC 7410
IC DEC 7400
IC DEC 7474
Transistor DEC 6351
Diode, D664
Diode, D662

8-31

Quantity

2
1
2
1
1
1
2
2
2
2
2
2

CHAPTER 9
TMS-E OECMAGTAPE CONTROL

SECTION 1 INTRODUCTION

The TMS-E DECmagtape Control interfaces the PDP-S/E with the TU1 0 Master System (Figure 9-1).
To perform this function the TMS-E:

Decodes programmed instructions.

Accepts and stores word count, current address, command, and function words.

Selects a program-designated transport (eight maximum in the system) and starts the operation
designated by the program.

Generates break requests to initiate a Single Cycle Data Break.

Generates interrupts and skips for flag checking .

Buffers the input/output data and assembles a 12-bit word into two 6-bit characters to be written on a
7-track transport; also controls the writing of the S LSBs of a 12-bit word on 9-track transports.

Performs housekeeping chores for Single Cycle Data Breaks, i.e., increments Word Count and Current
Address Registers.

Provides ERROR and JOB DONE flags.

Provides lOTs for TMS-E maintenance.

0 ----,
I

I
TM8-E
DECMAGTAPE

PDP-8/E
COMPUTER

TU10
DEC MAGTAPE
MASTER
SYSTEM
AND
TRANSPORT

I
I

I
I
I

TU10
TRANSPORTS
(7 MAXIMUM)

C2!:!..T!!..E~~U~

V
Figure 9-1

6E-0498

TMS-E DECmagtape Control and TU10
Master System, Block Diagram
9-1

The following quad modules comprise the TM8-E:
M8321 Output Control Module
M8322 Control and Data Break Module
M8323 Transport Status and Control Module
M8327 Registers Module
These quad modules must be inserted into the OMNI BUS and connected together via H851 Top Connectors. Two
BC08-L cables are used to connect the TM8-E (input and output) to the TU10 Master System. The TM8-E receives
+5V logic power from the PDP-8/E OMN I BUS. No power is supplied to or received from the TU 10 Master System
by the TM8-E or PDP-8/E.
The TU10 DECmagtape Transport operates at 45 ips and is available in the following formats:

9.1

7-track version, with recording densities of 200, 556, or 800 bpi.

9-track version, with recording density of 800 bpi.

RECORDING METHODS AND DECmagtape FORMATS

The DECmagtape system (TM8-E and TU10 Master/Slave System) is an on-line mass storage system for programs or
data. Data is recorded on tape in vertical rows, termed characters. On a 7-track transport, each character consists of
six data bits and one vertical parity bit; on a 9-track transport, each character consists of eight data bits and one
vertical parity bit. The vertical parity bit is program selected as even or odd on 7- and 9-track transports. The odd
parity bit guarantees that each character records at least one 1 bit, including an all zeroes character.
The parity bit is generated according to the rule that the number of 1s in a character (parity bit included) is odd or
even; for example, when odd parity is used if the character contains an even number of 1 bits, a parity bit is
generated to record an cdd number of 1 bits. If an even number of bits is read from tape using odd parity, a vertical
parity error is generated to notify the program that the data is in error.
The data characters are recorded in blocks of characters, termed records (Figure 9-2). Each record contains a
specified number of characters determined by the word count and transport selected (7- or 9-track transport). The
minimum record length is 4 characters, which is two 12-bit words for a 7-track transport or the eight LSB from 4
words on a 9-track transport. The minimum word count for a 7-track transport is the 2's complement of 2 or 7776 8 ;
the minimum word count on a 9-track transport is the 2's complement of 4 or 7774 8 • If a write operation is
attempted for a record with less than 4 characters, there is no Cyclic Redundancy Check (CRC) or Longitudinal
Redundancy Check (LRC) character and the tape transport runs away. When this occurs, an Initialize operation
must be performed to stop the transport.
Records are separated by interrecord gaps (I RG). The I RG is approximately 0.5 inch at minimUm, but may be
extended to 3 inches by performing an Extended Gap operation. Tape I RGs (unrecorded areas) provide areas on the
tape for the transport to start or stop and also separate data records.

9.1.1

NRZI Recording Method

The TU10 employs the NRZI (non-return-to-zero change on one) recording method. In the NRZI method, a 1 bit is
represented by a reversal in the direction of tape magnetization on a track; a 0 bit is represented by no change in
tape magnetization.

9-2

140-------- FILE --------I~I

FILE MARK
178 ON 7 TRACK
238 ON 9 TRACK

FILE MARK
178 ON 7 TRACK
23 8 ON 9 TRACK

DATA PREVIOUS~''''''o------IRG
.,'
DATA NEXT
R ECOR D
:.
3".012'
'RECORD
I
4-0.06'~

I+--APPROX 3.8 1,--'_ _......0 - - - _ 311 -------.1
,
,
4

III r-*-1
J "L

LAST DATA
CHARACTER
OF PREVIOUS
FILE

1111 r- *--1

r-*-1

"J"),, j

LAST DATAl
CHARACTER
OF PREVIOUS
RECORD

FIST DATA
CHARACTER
N EXT FILE

LJCC

7 TRACK FILE MARK AND GAP FORMAT

-APPROX 3.8"

O.611~

.1 ...

11111
t

FIRST DATA CHARACTER
OF NEXT RECORD

7 TRACK IRG FORMAT

DATA PREVIOUS
RECORD

.,.
I RG
'1'
,
,
1+------0.6" ~g:1~'" ~

111~*+*1

CRtC

LRCC
LAST DATA
CHARACTER
OF PREVIOUS
FILE

* = 4 CHAR. SPACE

~**---1
FILEtMARK

LRCC

1111 ~*+*-i

'II

LAST DATA
CHARACTER
OF PREVIOUS
RECORD

FIRST DATA
CHARACTER
OF NEXT
FILE

9 TRACK FI LE MARK AND GAP FORMAT

DATA NEXT
RECORD

J CRL i

LRCC

'IIII1
LFIRST DATA
CHARACTER
OF NEXT
RECORD

9 TRACK I RG FORMA T
8E-0497

* * = 8 CHAR.SPACE
Figure 9-2 Data Recording Structure

9.1.2 9-Track Tape Format
The 9-track format (Figure 9-3) is composed of from 18* to 2048 9-bit characters spaced 1/800th of an inch apart,
followed by 4 character spaces, a CRC character, 4 more spaces, and an LRC character. This unit of data is called a
record. At 800 characters per inch, the record is between 1/32 inch (minimum) and 5 inches (maximum). Between
each record is a gap of at least 1/2 inch. The tape structure consists of a number of records followed by a File Mark
(Figure 9-2). Since data is recorded and read at high speed, I RGs are used to provide space for starting and stopping
the TU 10 Transports. The TU10 Transport accelerates from standstill to full speed or vice versa in approximately
0.2 inch of tape; thus, the 0.5-inch IRG provides adequate space for starting and stopping the tape transport.
The CRC character (Paragraph 9.1.4) is generated in the TU 10 Master System during a Write operation and written
at the end of a record. The check character performs the same function to a record as the parity bit does to a
character. A CRC character is not used on 7-track transports.
*UASCII program standards, not a hardware limit.

9-3

The LRC is the final character in the record and is generated so that for each track the sum of 1 bits (CRC character
included) is even. The LRC character is written on tape by clearing the write buffer in the Master System after the
CRC character is written. The LRC Register is gated to the write buffer and a 1 is written on each track containing
an odd number of 1s; a 0 is written on each track containing an even number of 1s.

/i
L

REFERENCE EDGE
(FRONT FLANGE
OF REEL)

LRC

0.005":t1D% (NOTE 3)

CRC 0.005":t 10%

_800 CPI
0.00125":t3%

INTEO~~~O~~NGAP_~---c;'-----:;'- BLOCK

WR ITE TRACK

(NOTE 2)

-1

0.043" MIN

2048 MAX USASCII CH
18 MIN USASCII CH
LOAD POINT
BEGINING OF
TAPE REFLECTIVE
~~~~~~R~~_~STRIP ON
NONOXIDE(SHINY)
SIDE OF TAPE

r----------

~(--+--PARITY (ODD)

BEGINING
OF
TAPE

END POINT
END OF TAPE
REFLECTIVE
STRIP ON NONOXIDE
(SHINY) SIDE OF
TAPE
L . . . . . - -_
__
TAPE MOTION

BOT
LRC
CRC

8E-0500

NOTES:

LEGEND
BPI

Tape Bits Per Inch
Beginning of Tape
Longitudinal Redundancy Check
Cyclic Redundancy Check

Tape is shown with oxide side up, Read/Write head
on same side as oxide. Tape shown representing "1"
bits in all NRZI recording; "1" bit produced by reversal of flux polarity, tape fully saturated in each
direction.

Tape to be fully saturated in the erased direction in
the inter-record gap and the initial gap.

An LRC bit is written in any track if the longitudinal
count in that track is odd. Character parity is ignored
in the LRC character.

CRC - Parity of CRC character is odd if an even
number of data characters are written, and even if an
odd number of characters are written.

Figure 9-3 9-Track Tape Format

9-4

9.1.3 7·Track Tape Format
In 7-track format (Figure 9-4), the CRC character is not written but the LRC character is written at the end of each
record. Tape character density may be 200, 556, or 800 bpi, with even or odd parity selected by the program.
I RGs are approximately 0.75 inch instead of 0.5 inch (minimum). A record consists of 4 * characters (minimum) to
8192 data characters (maximum) followed by 4 character spaces and an LRC character (Paragraph 9.1.5). A 0.75
inch I RG between each record allows the tape to be started and stopped (Paragraph 9.1.2).

OXI DE (DULL) SI DE
OF TAPE FACES
HEADS

REFERENCE EDGE
(FRONT FLANGE
OF REEL)

WRITE

READ

HE\

TAPE
SKEW

~r-

... ,

EOR DELAY
4 CHARACTER
SPACES

LOAD POINT
BEG INN I NG-OF- TAPE
REFLECTIVE STRIP
ON NONOXIDE
(SHINY) SIDE
OF TAPE

(RDll-

I
I

(RD6)N

END
OF
TAPE

if)

(RD5) <t

I>::
I

~ (RD4)co I
'" (RD3)<I I
(RDZ)m I

BEGINING
OF
TAPE

h-RECO~D/ G~P
(RDP)o

END POI NT
END-OF -TAPE
REFLECT IVE STRIP
ON NONOXIDE
(SHINY) SIDE
OF TAPE

ONE
CHARACTER
SPACE
,
I
( 800,566

I "rARITY TRACK

~ 3"--------1

3/4"
MINIMUM

EOR MARK
(LONGITUDINAL
PARITY CHECK
CHARACTER)

2~0 -INCH)
TAPE MOTION

"'-

L - - - -_ _

8E-0499

Figure 9-4 7-Track Tape Format

9.1.4 Cyclic Redundancy Check Characters (CRC)
The CRC character provides a method of error detection and correction on 9-track TU 10 DECmagtape Transports
only. The code has nine check bits that form a check character at the end of each record on 9-track TU 10
DECmagtape Transports. To perform a correction, a record in which an error has been detected must be re-read into
memory with the LRC and CRC characters for program evaluation. Errors involving more than one track can be
detected but not corrected.
The CRC character is generated as follows:

The CRC Register, located in the Master System, is cleared at the beginning of each record. As each data
bit is written on tape, it is Exciusively-ORed with its corresponding bit in the CRC Register.

The CRC Register is shifted one position to the right after the Exclusive-OR operation has taken place.

*Hardware limit.

9-5

The bits entering CRC 2, CRC 3, CRC 4, and CRC 5 of the CRC Register are inverted if the bit entering
CRCP is a 1 (Tables 9-1 and 9-2). Data is shown in Table 9-1; the resultant CRC character is shown in
Table 9-2.

Steps a, b, and c are repeated for each data character of record.

At CRC time, all positions of the CRC Register, except CRC 2 andCRC 4, are complemented and the
resultant CRC character is written on tape.

The CRC Register is cleared for the next record.

Table 9-1
A Five·Character Record

Bit

Data
Character 0

Data
Character 2

Characters
Data
Character 3

Data
Character 4

0
0
0

1
1
1
1

0
0
0

1
1
1

0
0

1
2
3
4
5
6
7

0
0

1
1

0
0

1
1

1
1
1
1

Data
Character 5

Table 9-2
CRCC In Register When Writing
CRC Register
CRC Bits

CRC
Cleared

(a) CRCP
(b) CRCO
(c) CRC1
(d) CRC2
(e) CRC3
(f) CRC4
(g) CRC5
(h) CRC6
(i) CRC7

0
0
0
0
0
0
0
0
0

Character 1

Character 2

Character 3

0
0

0
0
0
0

0
1

0
0
1

0
0
0
0

0
0
1

1
1

9-6

Final
CRC

CRCC
On Tape

0
0
0
0
0

0
0

1
1
1
1
1
1
1
1

Character 4

1
1
1

0
1

0
0
0

9.1.5 Longitudinal Redundancy Check Character (LRC)
The LRC character is written four spaces after the last data character on a 7·track transport or four spaces after the
CRC character on a g·track transport. The vertical parity bit is always written on the LRC character; the vertical
parity of LRC is never checked. The LRC character makes the longitudinal parity even for the entire record,
including the CRC. The LRC is generated in the Master System by the LRC Register in the following manner:

The LRC Register is cleared at the beginning of a record.

As characters are written on tape, corresponding 1 bits complement the LRC Register at the time data is
written on tape.

At LRC time, the LRC Register is cleared and 1s are written on tape in only those channels for which
the LRC is 1 prior to clearing.

Following this method, the LRC character forces an even number of bits to be recorded on each track of
the tape. The CRC character is included in determining the LRC character (CRC is used on g·track
transports only).

9.1.6 Data Files
As previously stated, a record is a group of characters preceded by an I RG and terminated by four spaces and an
LRC character. A file is a group of records separated by I RGs and terminated by a 3·inch gap followed by a File
Mark. The File Mark is a record consisting of a single data character [the end of file (EOF) character] followed by
three blank characters and an LRC character. The CRC character is not written on an EOF record. The LRC
character with a File Mark is a duplicate of the EOF character. On 7· and g·track TU10 Transports, the EOF
characters are 178 and 23 8 , respectively.
9.1. 7 Track Assign ments
The track assignments for Read, Write, and Parity bits are shown in Table 9·3.

Table 9-3
TU10 Track Assignments for Data and Parity
9-Track
Transport
Track Number

Write
Data
Bits

Read
Data
Bits

7-Track
Transport
Track Number

Write
Data
Bits

Read
Data
Bits

1 (inside)
2
3
4
5
6
7

WD5
WD7
WD3
WOP
WD2
WD1
WDO
WD6
WD4

RD5
RD7
RD3
RDP
RD2
RD1
RDO
RD6
RD4

1
2
4

WD7
WD6
WD5
WD4
WD3
WD2
WDP

RD7
RD6
RD5
RD4
RD3
RD2
RDP

8
9 (outside)

8
A
B
C

9-7

9.2 COMPANION DOCUMENTS
The following documents and publications are necessary for the operation, installation, and maintenance of the
TM8-E:

a.
b.
c.
d.
e.
f.

PDP-8IE & PDP-81M Small Computer Handbook, 1972
PDP-8IE Maintenance Manual, - Volumes 1 and 2
Introduction to Programming, DEC 1972
DEC Engineering Drawing, Magnetic Tape (DEC-OO-TM8-E-O-O)
TU 10 DECmagtape Master System Manual (DEC-OO- TU 1OM -D)
TU10 DECmagtape Maintenance Manual (DEC-OO-TU10S-DC)

9.3 SOFTWARE DOCUMENTS
The following diagnostics and programs are available for the TM8-E:

a.
b.

c.
d.

e.
f.
g.

TM8-E Control Test Part 1, MAINDEC-08-DHTMA-A
TM8-E Control Test Part 2, MAINDEC-08-DHTMB-A
Drive Function Timer, MAINDEC-08-DHTMC-A
TM8-E Data Reliability Test - 9-Track, MAINDEC-OS-DHTME-A
TMS-E Data Reliability Test - 7-Track .. MAINDEC-OS-DHTME-A
TMS-E Random Exerciser, MAINDEC-OS-DHTMF-A
TMS-E DECmagtape System Module for DEC/SX, MAINDEC-SX-DHTMA-A

The diagnostics have instructions for loading and running to check the TMS-E.

SECTION 2 SITE PREPARATION, INSTALLATION, AND ACCEPTANCE TEST
The TMS-E is installed on site by DEC Field Service personnel. No attempt should be made by the customer to
unpack, inspect, install, test, or service the TMS-E until a DEC Field Service representative is present.

9.4 SITE PLANNING AND CONSIDERATIONS
Adequate site planning and preparation can simplify the installation process and result in a more efficient and
reliable TMS-E installation. DEC Sales Engineers or Field Service Engineers are available for consultation with user
personnel regarding installation. The customer should refer to the TU10 DECmagtape Master System Manual and
TU10 DECmagtape Maintenance Manual for TU1 0 space requirements, environmental requirements, and installation
procedures to ensure that the installation site has adequate space, cooling, and power.
Primary planning considerations for TMS-E installation are:

Adequate power on the OMNIBUS for the TMS-E modules (Table 9-4).

A 33 ASR Teletype and programmer's console to run diagnostic and MAINDEC programs.

Space for the TU 10 Tape Transports.

TMS-E software for acceptance test and system operation.

9-S

Table 9-4
TMS-E Module Power Requirements
Module

Power Requirements

MS321
MS322
MS323
MS327

+5V, 1,000 mA
+5V, 775 mA
+5V, 900 mA
+5V, 1,500 mA
Total

9.5

4,175mA

INSTALLATION

Perform the following procedure to install TMS-E modules:
Step

Procedure
Ensure that power is removed from the PDP-S/E and the TU10.

Ensure that the PDP-S/E and the TU 1 cabinets are tied to the same ground or install a
ground wire between the cabinets.

Unpack the TMS-E modules and visually inspect each module for shipping damage.

Ensure that the jumpers are installed correctly to select the priority assigned to the
TMS-E (Paragraph 9.14.3).

Insert the TMS-E modules into the OMNIBUS in the order shown in Figure 9-5. (Refer to
Figure 2-3 of PDP-8/E Maintenance Manual, Volume 1, for module priorities.)
WARNING
The modules must not be installed upside down. The +5V,
0.01 pF capacitors should be at the bottom (next to the
OMNIBUS) on all modules installed on the OMNIBUS.

Install two HS51 Top Connectors between the following modules (Figure 9-5):

a.
b.

MS321 and MS327
MS327 and MS322
MS322 and MS323

Insert an M9S9 Terminator Module in slot A06 of the TU10 Master System.

Connect one BCOS-L cable as follows:

a.
b.

Pl to Jl on the MS321 Output Control Module.
P2 to J2 on the MS321 Output Control Module.
Insert the M954 Connector Module into slot A07 of the TU10 Master
System.

9-9

Connect the other BCOS-L cable as follows:

P1 to J1 on the MS323 Status and Control Module.
P2 to J2 on the MS323 Status and Control Module.
Insert the M954 Connector Module into slot B07 of the TU10 Master
System.

NOTE
Route cables between the PDP-8/E and TU10 so that they
are protected and out of the way.
Check TU10 slave terminators (refer to TU10 Print Set).

ONE

M8321
F

TO
TRANSPORT

TWO

POSITION

M8323

(N)

M8322

(N + 1)

M8327

(N + 2)

M8321

(N + 3)

I I
F

M8327
E

M8322
F

I I
F

M8323
TO
TRANSPORT

8(-0525

Figure 9-5 TMS-E Module Installation

9.6 ACCEPTANCE TEST
Run the Acceptance Test specified in the TMS-E Print Set (D-TD-TMS-E-1).

9.7 TMS-E INTERFACE
Two BC08-L cables are used to connect the TMS-E to the TU10 Master System. One BCOS-L cable is connected
between the MS321 Output Control Module and slot A07 of the TU10 Master System to provide control signals to
the tape drive and data to be written on the TU10 DECmagtape (Table 9-5). The other BCOS-L (Table 9-6) cable
connects the MS323 Status and Control Module and slot B07 of the Master System to provide status information
and data read from the TU10 DECmagtape to the TMS-E Control. An M9S9 Terminator Card must be installed in
slot A06. The signals on the H851 Top Connectors are shown in Tables 9-7 through 9-10. The signal prefix indicates
the origin of the signal, i.e., all signals prefixed by C originate at the TU 1O. The following is a list of prefixes and
their origin.

9-10

Prefix

Origin

C
OC
CB
SC
RE

TU10
M8321 Module
M8322 Module
M8323 Module
Registers Module

a.
b.

c.
d.

The numeral following the prefix indicates the sheet of the module print where the signal originates, i.e., R E-1
indicates the signal originates on the M8327 Module, sheet 2.

Table 9-5
M8321 Output Control Module Signals and Interface
On
TU10
M954
(Slot A07)
Pin No_

J1
M8321
Pin No_

A1
B1
C1
D1
E1
F1
Sl
J1
K1
L1
M1

D
F
J
L
R
N
LL
V
X
Z
BB

J2
M8321
Pin No.

Signal

Description

C SEL 0 H
C SEL 1 H
C SEL 2 H
CSEL 16 H
C DEN 5 H
C DEN 8 H
C FMK L
CWXG H
C FWDH
C RWDH
CWRE H

*Buffered SELECT 0
*Buffered SELECT 1
*Buffered SELECT 2
Not used
*Density 5
*Density 8
File Mark
Extended gap
Move tape forward
Move tape reverse
Write Enable with CFWD H, go
off line with CREW H
Write bit 0
Write bit 1
Write bit 2
Write bit 3
Write bit 4
Write bit 5
Write bit 6
Write bit 7
Rewind
Initialize
Begin tape operation
Write Data Ready
Generate or check for even parity
when asserted
Write File Mark

D2
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
S2
T2

L
N
R
T
V
X
Z
BB
DD
FF
JJ
LL
NN

CWDOH
CWD1 H
CWD2H
CWD3H
CWD4H
CWD5H
CWD6H
CWD7 H
CREW H
C IN IT H
CSET H
CWDR H
C PEV W H

CWFMK H

*Refer to Table 9-11. Some pins not used are tied to ground.

9-11

Table 9·6
TM8·E M8323 Transport Status Control Module Signals and Interface
On
TU10
M954
(Slot B07)
Pin No.

J1
M8323
Pin No.

J2
M8323
Pin No.

Signal

Description

C ROS L
CSOWN L
CTUR L
C ROO L
C R01 L
C R02 L
C R03 L
C R04 L
C R05 L
C R06 L
C R07 L
CROP L
C FMK L
CWRS L

C CRCS L

F2
K2
L2
M2
N2
P2

R
X
Z
BB
DO
FF

C RWS L
C BOT L
CWRL L
C VPE L
C SELR L
C 7CH L

R2
S2
T2
U2

JJ
LL
NN
RR

C EOT L
C CRCE L
C LRCE L
C LRCS L

Read Data strobe
Tape motion is stopping
Tape Unit Ready
Read bit 0 from tape unit
Read bit 1 from tape unit
Read bit 2 from tape unit
Read bit 3 from tape unit
Read bit 4 from tape unit
Read bit 5 from tape unit
Read bit 6 from tape unit
Read bit 7 from tape unit
Read Parity bit
File Mark (end of file)
Write Strobe indicates data on CWO
lines has been written on tape
CRC strobe, appears with CRC
character
Tape Rewinding
Beginning of Tape
Write Lock prevents writing on tape
Vertical Parity Error
Existing transport is on line
7 channel asserted when 7 channel
tape unit is selected
End of Tape
CRC Error
LRC Error
LRC strobe appears with the LRC
character

A1
B1
C1
F1
Hl
J1
K1
L1
M1
N1
P1
R1
Sl
02

0
F
J
R
T
V
X
Z
BB
DO
FF
JJ
LL

9·12

Table 9-7
TMS-E MS321 Output Control Module Top Connector Signals
To MS327 Connector F
Signal
Pin No.
Not used
OC-2 RWCR L
RE-l DB7 H
RE-l FRO H
RE-l DB5 H
CB-l WR 1st 7 H
Not used
RE-l DB3 H
RE-l DB2 H
Not used
CB-3 MTTF L
SC-2 ERROR L
OC-2 LCAR L
SC-l TUR L
OC-2 LCMR L
CB-3 CLR ALL L
OC-2 LCM/F/DB H
OC-2 LFGR L
Not used
Not used
RE-1 DB6 H
Not used
OC-l RIC ERROR L
RE-l CBl H
OC-2 LWCR L
OC-l RDB L
RE-1 DBO H
OC-2 CCAR L
RE-1 FR3 L
OC-2IBCM L
OC-2 CLF L
SC-1 CONTROL BSY L
OC-2 5BRM L
OC-2 LDBR L
Not used
Not used

To MS327 Connector H
Signal
Pin No.

Al
Bl
Cl
Dl
El
Fl
Hl
Jl
Kl
Ll
M1
Nl
Pl
R1
Sl
Tl
U1
V1
A2
B2
C2
D2
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
S2
T2
U2
V2

CB-2 MAC 2 H
RE-l SEL 16 H
RE-l PEVN H
SC-l SET H
Not used
RE-l DB8H
Not used
RE-l DB9 H
Not used
RE-l DB10 H
Not used
CB-l WR 2nd 7 H
RE-l DEN 8 H
RE-l FRl H
RE-l FR2 H
OC-2 CWCR L
OC-2 RMSR L
OC-2 RCAR L
Not used
Not used
CB-l WDR H
Not used
CB-3INIT H
RE-l BSEL2H
RE-1BSEL1H
RE-1 BSELO H
CB-l WR9 H
RE-1 DB11 H
RE-l DEN5 H
OC-2 AC ENABLE L
OC-2 B TP3 H
OC-2 RF5R L
OC-2 RCMR L
RE-1 DB4 H
Not used
Not used

9-13

Al
Bl
Cl
Dl
El
Fl
Hl
Jl
Kl
Ll
Ml
Nl
Pl
Rl
Sl
Tl
Ul
Vl
A2
B2
C2
D2
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
52
T2
U2
V2

Table 9-8
TM8-E M8322 Control Module, Top Connector Signals

To M8327 Connector E
Signal
SC·2 RD3 H
SC·2 RDP H
SC·2 RD5 H
Not used
Not used
SC·l CONTROL
BSY L
OC·2 IBCM L
SC·1TURL
SC·l EMA INC L
SC·2 RDO H
Not used
SC·l 7 CHANNEL H + DEN 5 L
SC·2 RD7 H
RE·l B SEll H
RE·l B SELO H
CB·2 DBC 2 L
RE·2WCO L
OC·2 LDBR L
OC·2SBRM L
CB·l WDR L
OC·2CLF L
SC·l SET H
RE·l ENABLE
CHECK CHAR L
SC·2 RDl H
SC·2 ERROR L
RE·l SELO H
RE·1SELl H
CB·3 LBC M L
RE·l BSELOH
RE·2CA 0 L
SC·2 RD2 H
CB·2 DB MPX B H
RE·l DBC 1 H
CB·2 CB MPX A H
Not used
Not used

Pin No.

To M8323 Connector F
Signal
Pin No.

To M8323 Connector H
Signal

Pin No.

To M8327 Connector J
Signal
Pin No.

Tl
Ul
Vl
A2
B2
C2

SC·l PRESET H
SC·l TUR L
SC·l FM L
SC·l Test
Not used
SC·l SDWN L

Tl
Ul
Vl
A2
B2
C2

CB·l SP REV L
CB·l REWIND L
CB·l BRK RQST H
Not Used
Not used
RE·l DEN8 H

D2
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
Al
Bl
Cl
Dl
El
Fl

CB·2 CHG DIR L
SC·2 RDP H
SC·2 RD5 H
SC·2 RD3 H
SC·2 RD2 H
RE·2 CAD L
SC·l RD7 H
SC·2 RDl H
Not used
SC·2 RDO H
SC·l EMA INC L
SC·2 ERROR L
SC·l DATA LATE L
CB·3 CLR STATUS L
CB·l OFF LINE
CB·2 BTP3 H
CB·l SPACE H

D2
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
Al
Bl
Cl
Dl
El
Fl

OC·2 RMSR L
OC·l RC ERROR L
OC·2 LCM/F/DB H
RE·2 EMA 7
SC·l COUNT CA L
RE·2 GO H
SC·2 RD4 H
OC·2 RFSR L
RE·l DEN 5 H
RE·' EMA INC ENABLE L
RD6 H
CB·l R/RC H
RE·l WR/WFM
CB·2 R/RCAFT WR
Not used
Not used
SC·l RDS • R + RCH

D2
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
Al
Bl
Cl
Dl
El
Fl

Hl
Jl
Kl
Ll
Ml
Nl
Pl
Rl
Sl

CHG TRANS L
SC·2 EOT L
CB·3 MTTF L
Not used
SC·2 REWINDING L
SC·2 BOT L
CB·3 SEL ERROR L
SC·l WRS L
SC·l SELR L

Hl
Jl
Kl
Ll
Ml
Nl
Pl
Rl
Sl

RE·lIEMF
SC·l COUNT CA L
Not used
Not used
CB·l WR9H
OC·2 LCM/F/DB H
OC·l RC ERROR L
OC·2 RMSR L

Hl
Jl
Kl
Ll
Ml
Nl
Pl
Rl
Sl

S2
T2
U2
V2

OC·2IBCM L
CONTROL BSY H
Not used
Not used

S2
T2
U2
V2

SC·l WRS H
CB·l WCOV H
SC·l SET H
SC·2 B LRCS L
CB·2 MAC ACC L
SC·l 7 CHANNEL + DEN 5 L
CB·3 BTP4 H
CB·3 CLR ALL
SC·l RECORD LENGTH
INCORRECT H
Not used
SC·2 SP REV· BOT H
Not used
Not used

S2
T2
U2
V2

CB·3INIT H
RE·l DEN 8 H
Not used
Not used

S2
T2
U2
V2

Ul
Vl
A2
B2
C2

CB·l WR 2nd 7 H
CB·3 CLR ALL L
CB,l WR 1st 7 H
Not used
Not used
RE·l EMA INC
ENABLE L
CB·2 DBC 1 L
RE·l DEN 5 L
OC·2 RFSR L
SC·2 RD4 H
CB·3 MTTF L
RE·l GO H
RE·2 EMA 7 H
CB·2 MAC 2 H
RE·l F2H
RE·l FRO H
RE·1FR1H
SC·2 RD6 H
CB·l CONT WC L
CB·2 MACl H
OC·2 LCMR L
RE·l SEL 16 H
RE·l IEEF

T1
Ul
Vl
A2
B2
C2
D2
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
Al
Bl
Cl
Dl
El
Fl

Table 9-9
TMS-E MS327 Register Module, Top Connector Signals
To M8322 Connector E
Signal

....
C11

OC·2 LDBR L
OC-2SBRM L
CB-l WDR H
OC-2 CLF L
SC-l SET H
RE-l ENABLE CHECK
CHAR L
SC-2 RDl H
SC-2 ERROR L
RE-l SEL2 H
RE-l SEL 1 H
CB-3 LBCM L
RE-l B SELO H
RE-2 CAO H
SC-2 RD 2 H
CB-2 DB MPXB H
SC-2 RD3 H
SC-2 RDP H
5C-2 RD5 H
Not used
Not used
5C-l CONTROL B5Y L
OC-2IBCM L
5C-l TUR L
5C-l EMA INC L
5C-2RDOH
Not used
5C-l 7 CHANNEL H + DEN 5 H
5C-2 RD 7 H
RE-l B5ELOH
RE-l SEL H
CB-2 DBC 2 L
RE-2WCO H
RE-l DBC 1 H
CB-2 DB MPX A H
Not used
Not used

Pin No.

To M8321 Connector F
Signal
Pin No.

To M8321 Connector H
Signal

Pin No.

To M8322 Connector J
Signal
Pin No.

Al
Bl
Cl
Dl
El
Fl

Not used
OC-2 RWCR L
RE-l DB7
RE-l FRO H
RE-l DB5
CB-l WR 1st 7 H

Al
Bl
Cl
Dl
El
Fl

CB·2 MAC 2 H
RE-1SEL16H
RE-l PEVN H
SC-1SETH
Not used
RE-l DBB H

Al
Bl
Cl
Dl
El
Fl

SC-2 RD 6 H
CB·l COUNT WC L
CB-2 MAC 1 H
OC-2 LCMR L
RE-l SEL16 H
IEEF L

Al
Bl
Cl
Dl
El
Fl

Hl
Jl
Kl
L1
Ml
Nl
Pl
Rl
51
Ul
Vl
A2
B2
C2

Not used
RE-l DB3
RE-l DB2
Not used
CB-3 MTTF L
SC-2 ERROR L
OC-2 LCAR L
SC-l TUR L
OC-2 LCMR L
CB-3 CLR ALL L
OC-2 LCM/F/DB H
OC-2 LFGR L
Not used
Not used
RE-l DB6

Hl
Jl
Kl
Ll
Ml
Nl
Pl
Rl
51
Tl
Ul
Vl
A2
B2
C2

Not used
RE-l DB9 H
Not used
RE-l DB10 H
Not used
CB-l WR 2nd 7 H
RE-l DEN 8 H
RE·1FR1H
RE-l FR2 H
OC-2CWCR L
OC-2 RMSR L
OC-2 RCAR L
Not used
Not used
CB-l WR 7 H

Hl
Jl
Kl
L1
Ml
Nl
Pl
Rl
51
Tl
Ul
Vl
A2
B2
C2

D2
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
52
T2
U2
V2

Not used
OC-l RC ERROR L
RE-l DBl
OC-2 LWCR L
OC·l RD B L
RE-l DBO
OC·2 CCAR
RE·l FR3 H
OC-2IBCM
OC-2 CLF
SC-l CONTROL B5Y
OC-25BRM
OC-2 LDBR
Not used
Not used

D2
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
52
T2
U2
V2

Not used
CB-3INIT H
RE-l B5EL2H
RE-l B 5EL 1 H
RE-l B5ELOH
CB-l WR 9 H
RE-l DBll H
RE-l DEN 5 H
OC-2 AC ENABLE L
OC-2 BTP 3 H
OC-2 RF5R L
OC-2 RCMR L
RE-l DB4 H
Not used
Not used

D2
E2
F2
H2
J2
K2
L2
M2
N2
"2
R2
52
T2
U2
V2

RE-l IEEF L
SC-l COUNT CA L
Not used
Not used
CB-l WR 9 H
OC-2 LCM/F/DB H
Not used
OC-l RC ERROR L
OC-2 RMSR L
CB-2 WR 2nd 7 H
CB-3 CLR ALL L
CB-l WR 1st 7 H
Not used
Not used
RE-l EMA INC
ENABLE L
CB-2 DBCl L
RE-l DEN 5 H
OC-2 RFSR L
5C-2 RD 4 H
CB-3 MTTF L
RE-l GO H
RE-2 EMA 7 H
CB-2 MAC 2 H
RE-l FR2 H
RE-l FRO H
RE-l FRl H
CB-3INIT H
RE-l DEN 8 H
Not used
Not used

D2
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
52
T2
U2
V2

Table 9-10
TMB-E MB323 Transport Status and Control Module, Top Connector Signals
To MB322 Connector F
Signal
Pin No.
CB-1 R/RC H
RE-1 WR!WFM
R/RC AFTWR
Not used
Not used
SC-1 RDS • R' + RCH
SC-1 WRS H
CB-1 WCOV H
SC-1 SET H
SC-2 B LRCS L
CB-2 MAC ACC L
SC-1 7 CHANNEL + DEN 5 L
CB-3 BTP4 H
CB-3 CLR ALL
SC-1 RECORD LENGTH
INCORRECT H
CB-1 SP REV L
CB-1 REWIND L
CB-1 BRK RQST H
Not used
Not used
RE-1 DEN 8 H
OC-2 RMSR L
OC-1 RC ERROR
OC-2 LCM/F/DB H
RE-2 EMA 7 L
SC-1 COUNT CA L
RE-2 GO H
SC-2 RD 4 H
OC-2 RFSR L
RE-1 DEN 5 H
RE-1 EMA INC ENABLE L
SC-2 RD 6 H
Not used
SC-2 SP REV BOT H
Not used
Not used

To MB322 Connector H
Signal
Pin No.

A1
B1
C1
D1
E1
F1
H1
J1
K1
L1
M1
N1
P1
R1
S1

SC-2 ERROR L
SC-1 DATA LATE L
CB-3 CLR STATUS L
CB-1 OFF LINE L
CB-2 B TP 3 H
CB-1 SPACE H
CB-3 CHG TRANS L
SC-2 EOT L
CB-3 MTTF L
Not used
SC-2 REWINDING L
SC-2 BOT L
CB-3 SEL ERROR L
SC-1 WRS L
SC-1 SELR L

A1
B1
C1
D1
E1
F1
H1
J1
K1
L1
M1
N1
P1
R1
S1

T1
U1
V1
A2
B2
C2
D2
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
S2
T2
U2
V2

SC-1 PRESET H
SC-1 TUR L
SC-1 FM L
SC-1 Test
Not used
SDWN L
CB-2 CHG DI R L

T1
U1
V1
A2
B2
C2
D2

SC-2 RDP H
SC-2 RD 5 H
SC-2 RD 3 H
SC-2 RD 2 H
SC-1 RD 7 H
SC-2 RD 1 H
Not used
SC-1 RD 0 H

E2
F2
H2
J2
L2
M2
N2
P2

SC-1 EMA INC L
OC-2 LBCM L
SC-1 CONTROL BSY H
Not used
Not used

R2
S2
T2
U2
V2

9-16

SECTION 3 PRINCIPLES OF OPERATION
9.S BLOCK DIAGRAM DESCRIPTION
Figure 9-6, a block diagram of the TMS-E DECmagtape Control, depicts the flow of signals between the modules,
OMNIBUS, and the TU1 a DECmagtape Master System and slaves. The modules are inserted into the OMNI BUS and
signals are carried between the modules by HS51 Top Connectors. The TMS-E is connected to the TU10
DECmagtape System by two BCOS-L cables. The TMS-E modules are described in the following paragraphs.

TM8-E REGISTER MODULE
(M8327)
(1) DATA REGISTER
(2) COMMAND REGISTER
(3) FUNCTION REGISTER
(4) WORD COUNT
REGISTER
(5) CURRENT ADDRESS
REGISTER
(6) BUFFERED COMMAND
REGISTER

EMAOO-EMA02
MAOO-MA11
MDOO-MDll

READ DATA
CONTROLS

,..--

TM8· E TRANSPORT
STATUS AND CONTROL
MODULE (M8323)
(1) MAIN STAUS REGISTER
(2)SECOND STATUS
REGISTER
(3)CONTROL LOGIC
(4) ERROR FLAG

TRANSPORT
STATUS
WRITE DATA

STATUS TO AC

0
M
N
I
B
U
S

READ
DATA

TM8-E CONTROL MODULE
(M8322)
(1) FUNCTIDN DECODER
(2)PRIORITY LOGIC
(3)DATA BREAK CONTROL
LOGIC
(4)INTERRUPT LOGIC
(5) CONTROL LOG I C
(6) JOB DONE FLAG
(MTTF)

TM8-E OUTPUT CONTROL
MODULE (M8321)
TRANSPORT
(1) INSTRUCTION
CONTROL
DECODER
(2)FUNCTION DECODER
(3)SKIP LOGIC
(4) READ COMPARE LOGIC

CONTROLS
TU10
DECMAGTAPE
MASTER
SYSTEM
AND
TRANSPORT

WRITE DATA

READ DATA

TUlO
TRANSPORT
(7 SLAVES
MAXIUM)

STATUS

DATA 00- DATA 11

...

BE-0501

Figure 9-6 TMS-E Block Diagram

9.S.1

MS321 Output Control Module

The MS321 Output Control Module comprises three lOT instruction decoders, a Function Decoder, Read/Compare
Error detection logic, buffers, gating logic to multiplex data to be written on DECmagtape during a Write operation,
and Skip logic.
9.S.1.1 lOT Instruction Decoder - The three decoders (device codes 70, 71, and 72) provide control signals in
response to the lOT instructions listed in Paragraph 9.9. The lOT decoders generate control signals that are
distributed to the logic of the other TMS-E modules to control data transfer between the TU 1a DECmagtape and
core memory. The control signals also control the loading and reading of TMS-E Registers and enable the error
detection logic to monitor data transfer operations.
9.S.1.2 Function Decoder - The Function Decoder receives three function bits from the Function Register and
decodes them to select one of the following DECmagtape functions (Paragraph 9.S.2.3).

a.
b.
c.
d.

Offline
Rewind
Read
Read/Compare

e.
f.
g.

Write
Write End of File
Space Forward
Space Reverse

The function signals generated by the Function Decoder are sent to the TU 1a DECmagtape Master System to
control the selected TU10 DECmagtape.
9-17

9.8.1.3 Gating logic - The WD bits are gated to the Write Data Buffers in response to control signals from the
TMS-E control module and transferred to the TU10 DECmagtape. On a 7-track transport, data is written on tape in
two 7-bit characters (6 data bits plus parity); on a 9-track transport, data is written in 9-bit characters (S data bits
plus parity). Parity for each character is generated in the TU1 0 by the Master System.
9.8.1.4 Read/Compare Error Detection logic - The Read/Compare error detection logic compares data read from
the DECmagtape with data in memory during the Break cycle and generates a Read/Compare error if the data is
different. This operation is accomplished by Exciusively-ORing the memory data with the data read from the
DECmagtape. Note the parity bit is not checked by Read/Compare.
9.8.1.5 Skip logic - The Skip logic grounds the Skip line and causes the program to skip the next instruction when
the following conditions exist:

a.
b.

c.
d

Tape Unit Ready (TUR) and an SKTR instruction is executed by the program.
ERROR flag is set and an SKEF instruction is executed by the program.
Control not busy and an SKCB instruction is executed by the program.
JOB DONE (MTTF) is set and an SKJD instruction is executed by the program.

This logic is used by the programmer for flag and error checking operations.
9.8.2 M8327 Registers Module
The MS327 Registers Module contains all of the TMS-E registers except the Main Status Register and Second Status
Register. Each of the registers on the MS327 module is described in the following paragraphs.
9.8.2.1 Multiplexer and Data Register - The MUltiplexer and Data Register stores information to be multiplexed to
or from the transport or OMNIBUS. It accomplishes this task in the following manner:

a.
b.

c.
d.

It receives data to be written on tape from the MD lines during a Write Break cycle.
It receives data from the AC via lOT instructions.
The OMNIBUS receives data from the tape transport during a Read operation via the Data Bus.
The Data Register receives data from the tape transport.
The Master System receives data from Data Buffers during a Write Break cycle.

9.8.2.2 Command Register - The Command Register (Figure 9-7) is loaded with a 12-bit word from the AC by an
LCMR instruction. The Command Register is used to select a tape transport (0-7), enable or disable interrupts,
select parity mode (odd or even), select memory field, and select DECmagtape recording densities. The contents of
the Command Register are transferred to the AC for program evaluation by an RCMR instruction.
9.8.2.2.1 Buffered Command Register (BCM) - The Buffered Command Register is loaded with SEL 0 through
SEL 2 when lBCM is asserted by the control logic. The output of BCM (B SEL 0 through B SEL 2) is compared
with SEL 0 through SEL 2 to determine when a new transport has been selected by the program. If the program
selects a new transport, CHG TRANS is asserted to inform the controller that a new transport has been selected.
LBCM is asserted when the following conditions exist:

a.
b.

The CHG TRANS flip-flop is set and the Rewind status from the selected transport is asserted.
CLR ALL is asserted.
At TP4 time, if anyone of the following conditions exist.
1.
C TU R L asserted.
C SDWN L asserted.
2.
3.
C SELR L negated.

9-1S

DENSITY
CSELECTION

~~~~~~~~--~~~,~~,
o

1 1 2

SEL~CTION ~

UNIT
TRANSPORT 0- 7

'J J
1

10 111 I

L
L
l

LDEN5

DEN 8

PARITY: 0= EVEN
1 = ODD

SEL 16 (UNUSED)

EXTENDED MEMORY,
ADDRESS 2 (EMA2)

INTERRUPT ENABLE ON
ERROR FLAG (I EEF)

EXTENDED MEMORY,
ADDRESS 1 (EMA1)

I NTERRUPT ENABLE
ON MAGTAPE FLAG
(MTTF) (JOB DONE) (IEMF)

EXTENDED MEMORY,
ADDRESS 0 (EMA 0)
8E-0614

Figure 9-7 Contents of Command Register

9.8.2.3 Function Register - The Function Register (Figure 9-S) is loaded from the AC by an LFGR instruction.
The three most significant bits (FO-2) are decoded by Function Decoders in the MS321 Output Control Module and
the TMS-E MS322 Control Module to select the following DECmagtape functions.
Offline

Selected transport is taken OFFLINE and rewound to beginning of
tape (BOT).

Rewind

The selected transport rewinds to BOT and stops.

Read

Data is transferred from tape to memory in the forward direction
only.

Read/Compare

Data read from the tape is compared to data in core memory; if
there is a comparison error, the Current Address (CAl Register stops
incrementing and the CA Register holds the memory address in error
at the end of the operation.

Write

Data is written on tape in the forward direction only.

Write End of File

The transport leaves a 3-inch gap and writes a File Mark that consists
of one character followed by three character spaces and an LRC
character.

Space Forward

The transport moves forward, at 45 ips, the number of records
specified by the Word Count (WC) Register (Paragraph 9.S.2). If File
Mark is encountered, the transport stops at I RG; if EOT is
encountered, the transport stops at the next I RG.

Space Reverse

The transport spaces in reverse, at 45 ips, the number of blocks
specified by the WC Register (Paragraph 9.S.2). If at the beginning
of tape (BOT) a File Mark is encountered, the tape stops.

9-19

I 3 I 4 I 5 I 6 I 7 I 8 I 9 I 10

FU~CTIONJ

SELECTION

LUNUSED

EMA INC ENABLE

000
001
010
011
100
101
110
111

OFF LINE
REWIND
READ
READ/COMPARE
WRITE
WRITE FILE MARK
SPACE FORWARD
SPACE REVERSE

GO WHEN EQUAL
TO A ONE

ENABLE CHECK
CHARACTER
EXTEND GAP

BE-0613

Figure 9-8 Contents of Function Register

The remaining bits of the Function Register enable the following operations if they are set by a 1 from the AC.
Extended Gap

If bit 3 is a 1, there is a 3-inch gap between records. This bit is used
only during Write functions.

Enable Check Character

If bit 4 is a 1 and a 9-track transport is selected, the LRC and CRC
are transferred to memory at the end of a record during Read
operations. This operation is accomplished by executing two more
Data Breaks after the WC Register overflows. Record Length
Incorrect is disabled at this time.

When bit 5 is a 1, the controller asserts GO, sets CNTL BSY (Control
Busy). generates PRESET, and if no Illegal Functions exist, SET is
asserted to start an operation. A GO command is issued to the
transport if it is ready (TUR is true, and SELECT REMOTE is low).

EMA I NC Enable

If bit 6 is a 1, the EMA bits in the Command Register and the CA
Register are used as a 15-bit register to address all PDP-8/E core
memory as a block instead of in 4K segments.

Continuous Operation

The MTTF (JOB DONE) signifies the end of a specified operation. If
an LFGR instruction is desired immediately, prior to TUR, this
instruction may be executed by the program.

9.8.2.4 Current Address Register - The CA Register is loaded from the AC by an LCAR instruction with a memory
address that is one location less than the desired starting memory location. The CA Register is incremented before
each data transfer to sequentially address a block of memory during a data transfer operation. The contents of the
CA Register are placed on the MA lines during a Single Cycle Data Break to address memory.
9.8.2.5 Word Count Register - The WC Register counts the number of words in a block of data transferred to or
from memory by the TM8-E. The 2's complement of the number of words to be transferred is loaded into the WC
Register by an LWCR instruction at the beginning of a data transfer. The WC Register is incremented before each
data character is transferred until the WC Register contains all Os, causing an OVERFLOW. When the WC Register
overflows, data transfer is stopped. This register is also used in spacing operations to count records to be spaced over.

9-20

9.8.3 M8323 Transport Status and Control Module
The TM8·E transport status and control logic contains the majority of the Main Status Register, the second Status
Register, the Error detection logic (ERROR flag), an illegal Function detection logic, and receives Read data
(ROO-R07) from the OECmagtape before it is applied to the Data Register.
9.8.3.1 Main Status Register - The Main Status Register (Figure 9-9) retains transport status information that is
transferred to the AC by an RMSR instruction for evaluation by the program.

ERROR FLAG.-J
TAPE REWINDING

BEGINNING OF
TAPE (BOT)
SELECT REMOTE

L,,~;~:::;:'
ERROR

FILE PROTECT

END OF TAPE (EOT)

PAR ITY ERROR (VERTICAL,
LRC, OR CRC ERROR)

DATA REQUEST LATE
RECORD LENGTH
INCORRECT

FILE MARK (EOF)

8E-0612

Figure 9-9 Contents of Main Status Register

9.8.3.2 Second Status Register - The Second Status Register (F igure 9-10) retains additional transport status
information that is transferred to the AC by an RFSR instruction for evaluation by the program.

FUNCTION
__
+.o------sECOND STATUS
_I
•
I~-----REGISTER
BITS
REGISTER BITS ~
___e
..

,----y---~

FUNCTION

000
001
010
011
100
101
110
111

::oJ

OFF LI NE
REWI N D
READ
READ COMPARE
WRITE
WRITE FILE MARK
SPACE FORWARD
SPACE REVERSE

l
9

111

LLONGITUDINAL
PARITY ERROR

CRC ERROR

LATERAL
PARITY ERROR

EMA INCREMENT ERROR
NOT USED
TRANSPORT CHANNEL
(9 CH ; 1 )

EXTENDED GAP
ENABLE CHECK
CHARACTER

GO BIT (1)
8E- 0611

Figure 9-10 Contents of Function and Second Status Register

9-21

9.8.3.3 ERROR Flag - The ERROR flag is set by anyone of the following error conditions:

a.
b.

c.
d.

e.
f.
g.

End of Tape (EDT)
Read/Compare (R/C) ERROR
Parity Error
Beginning of Tape (BOT)
EMA 7 INC ERR
RECORD LENGTH INCORRECT
DATA LATE
ILLEGAL FUNCTION
FILE MARK

9.8.3.4 Illegal Function Detection - The ILLEGAL FUNCTION flag sets, setting the ERROR flag, if any of the
following are attempted:

A Rewind is attempted when tape is at BOT.

A Space Reverse is attempted when tape is at BOT.

An attempt is made to select other than SOO bpi density on 9-track transports.

An attempt is made to Read after Write on the same transport.

lOTs are executed to load the Data Buffer Register, Command Register, or Function Register while the
Control is busy.

Issue a Write or Write File Mark to a tape transport with the Write Ring removed.

An attempt is made to start an operation when the following conditions exist:

1.
2.
3.

CHG TRANSPORT L is true.
TUR H is true.
PRESET is true.

9.8.3.5 PRESET and SET Pulse Generator - PRESET is a fixed delay that is generated to allow adequate time for
interrogation of the control in order to check for errors and illegal functions prior to asserting the SET pulse. If
there are no illegal functions or errors, the SET pulse is asserted, thus asserting the C SET H signal to the tape
transport and starting tape motion.
9.8.3.6 Control Busy (CNTL BSY) - CNTL BSY is set when the GO bit is issued to indicate that an operation is
pending.
9.8.4 M8322 Control and Data Break Module
The MS322 Control and Data Break Module comprises the Data Break Control logic, a Control Function Decoder,
and the Interrupt logic.
9.8.4.1 Data Break Control Logic - The Data Break Control logic allows the TMS-E to transfer large blocks of data
between the TU10 DECmagtape and memory. When the TMS-E asserts BRK ROST, a priority check is made by the
controller. A priority network on the MS322 module is compared with priorities of other peripherals requesting a
data break and, if the TMS-E has the highest priority, the Break Control allows the TMS-E to assert the Break
Control lines. This action enables the TMS-E to assume control of the CP Major Register gating and to address
memory using the Current Address logic and Data Break Control logic. When BR K ROST is granted by the TMS-E,

9-22

data is transferred from the TMB-E Data Register to the Data Bus (read) or from the MD lines to the M8321 Output
Control Module (Write or Read/Compare). The TMB-E is is capable of one Single Cycle Data Break approximately
every 28 flS until a complete record is transferred to or from memory. The CRC and LRC characters are also
transferred to memory during a Read operation if the ENABLE CHECK CHARACTER bit in the Function Register
is set.
9.8.4.2 Function Decoder - The Control Function Decoder decodes FRO-FR2 from the Function Register and
generates the same function as the Output Control Function Decoder on the M8321 Output Control Module
(Paragraph 9.8.1.2). The outputs of this Function Decoder are applied to the control logic on the control module.
The FRO-FR2 function bits are applied to the Control Function Decoder from the Function Register.
9.8.4.3 Interrupt Logic - The Interrupt logic on the TM8-E control module generates an interrupt request (INT
ROST) when the following conditions exist (Table 9-11):

a.
b.

Bit 4 in the Command Register (IEEF) is set (1) and the ERROR flag is set.
Bit 5 in the Command Register (IEMF) is set (1) and the JOB DONE flag (MTTF) is set.

Table 9-11
Command Register Contents and Function
Function

SEL 2
(Bit 2)

o
o
1

o
o

Transport 0
Transport 1
Transport 2
Transport 3
Transport 4
Transport 5
Transport 6
Transport 7

Bit 3

o = Even Parity; 1 =Odd Parity

Bit 4

If bit 4 is a 1, enable interrupt ERROR flag.

Bit 5

Enable interrupt on JOB DONE (MTTF) if bit 5 is a 1.

Bits 6, 7, and 8

Extended Memory Address (EMA), these bits determine
which memory field the controller uses for data transfer
operations during a Data Break. Function Register bit 6
(Table 9-12) determines if the EMA address is to be incremented or used in the wrap-around mode.

9-23

Table 9-11 (Cont)
Command Register Contents and Function
Function

Bit No.

Bit 6
(EMA 0)

Bit 7
(EMA 1)

Bit 8
(EMA 2)

a
a

Field a
Field 1
Field 2
Field 3
Field 4
Field 5
Field 6
Field 7

Bit 9

Reserved for future use.

Bits 10 and 11

Density bits, these bits select the density for tape transport operation and are referred to as Den 8 (bit 10) and
Den 5 (bit 11).

Bit 10
Den 8

Bit 11
Den 5

a
a

a
1

200 bpi, 7 track
556 bpi, 7 channel
800 bpi, 7 channel*800 bpi, 9 channel

*This mode is also referred to as Core Dump Mode. When this command is issued to a 9-track transport, zeroes are
written on tracks 0 and 1 of the DECmagtape and the 9-track transport operates as a 7-track transport.

9.9 INSTRUCTIONS AND STATUS BITS
The following instructions are used to program the TM8-E. Refer to the appropriate table for the status bits
associated with each instruction.
Load Word Count Register (LWCR)

Octal Code:

6701

Operation:

Loads the WC Register with the contents of the AC (F igure 9-11) and clears the AC. The WC Register
should not be loaded when the control is busy. If the register is loaded during CNTL BSY, data
reliability and tape compatibility are not ensured. The WC Register is loaded with the 2's complement
of the number of words to be transferred or number of blocks to be spaced. The WC Register is
incremented at TP1 of a Data Break cycle during data transfers, at LRCS during a Space Forward, or
at the first word of a record during a Space Reverse operation.

9-24

RE-2 WCO H

RE-1 BACO

RE-2 DATA 0 L

RE-1 BAC1

RE-2 DATA 1 L

RE-l BAC2

RE-2 DATA 2 L

RE-l BAC:3

RE-2 DATA :3 L

RE-1 BAC4

RE-2 DATA 4 L

RE-l BAC5
RE-l BAC6

HOLDING
BAC

WORD
COUNT
REGISTER

DATA
BUS
GATING

RE-2 DATA 5 L
RE-2 DATA 6 L

RE-1 BAC7

RE-2 DATA 7 L

RE-l BACB

RE-2 DATA e L

RE-1 BAC9

RE-2 DATA 9 L

RE-l BAC10

RE-2 DATA 10 L

RE-1 BAC11
(RE-2)
OC-2 BTP:3 H

RE-2 DATA 11 L

(RE-2)
CLK

(RE-2)

OC-2
LWCR L

OC-2
RWCR L
BE-0703

Figure 9-11

LWCR and RWCR Instruction Data Flow

Clear Word Count Register (CWCR)

Octal Code:

6702

Operation:

Clears the WC Register. This instruction is used primarily in maintenance operations and should never
be used during CNTL BSY.

Load Current Address Register (LCAR)

Octal Code:

6703

Operation:

Loads the CA Register with the contents of the AC (Figure 9-12) and clears the AC. The CA Register
is loaded to one less than the memory address of the first word to be transferred. If this instruction is
executed during CNTL BSY, one of the following occurs:
1.
In the wrap-around modes (Function bit 6 = 0), the location of the data transfer cannot
be ensured within the selected memory field.
2.

In the EMA INC ENABLE mode (Function bit 6 = 1), the location of the data transfer
cannot be ensured within memory.

The CA Register is incremented at each BRK ROOT.
Clear Current Address Register (CCAR)

Octal Code:

6704

Operation:

Clears the CA Register. This instruction is used primarily for maintenance and should never be used
during CNTL BSY.
9-25

RE-2 CAO H

RE-1 BACO

RE-2 DATA 0 L

RE-1 BAC1

RE-2 DATA 1 L

RE-l BAC2

RE-2 DATA 2 L

RE-l BAC3

RE-2 DATA 3 L

RE-1 BAC4

RE-2 DATA 4 L

RE-1 BAC5
RE-1 BAC6

HOLDING
BAC

CURR
ADDR
REGISTER

DATA
BUS
GATING

RE-2 DATA 5 L
RE-2 DATA 6 L

RE-1 BAC7

RE-2 DATA 7 L

RE-1 BAC8

RE-2 DATA 8 L

RE-1 BAC9

RE-2 DATA 9 L

RE-l BAC10

RE-2 DATA 10 L

RE-l SAC11
(RE-2)
OC-2 B TP3 H

RE-2 DATA 11 L

(RE-2)
CLK

(RE-2)

OC-2
LCAR L

OC-2
RCAR L
BE - 0704

Figure 9-12

LCAR and RCAR Instruction Data Flow

Load Command Register (LCMR)

Octal Code:

6705

Operation:

Loads the Command Register with the contents of the AC and clears the AC (Figure 9-13). This
instruction must not be issued during CNTL BSY. The LCMR instruction selects tape transport,
Parity mode, memory field, recording densities, and enables or disables interrupts (Table 9-11 and
Figure 9-7).

Load Function Register (LFGR)

Octal Code:

6706

Operation:

Loads the Function Register with the contents of the AC and clears the AC (Figure 9-14). The
Function Register is the last register loaded because it contains the GO bit. This instruction
determines the function the t~ansport is to perform (Table 9-12 and Figure 9-8).

Load Data Buffer Register (LDBR)

Octal Code:

6707

Operation:

Loads the Data Buffer Register with the contents of the AC, clears the AC, and sets the MTTF flag
(Figure 9-15). This instruction is used, for maintenance purposes.

9-26

OC-2 LCMR
DATA

DATA 1 L
DATA 2 L
DATA :3 L
DATA 4 L
DATA

5 L

DATA 6L
DATA 7 L
DATA 8L
DATA 9L
DATA 10 L
DATA 11 L

RE-l BACO

~ RE- l t ACl

RE-15ELO H

~ RE-1BAC3 COMMAND

~ RE-\BAC6

(RE-ll

P-- RE-1 DATA 0 L

RE-1 B5EL 1 H

~ RE-l

RE-1 BSEL2 H

RE-l PEVN H

P-- RE-l DATA :3 L

;:::J.J RE-1 BACS

~ RE-l DATA 4 L

RE-l IEMF
OC-2 LCMR

(RE-ll

DATA
BUS
GATING

RE-l CEMAO H

fPIO

r- R~~~SMTAEN~

HBAC

(RE-ll

DATA 1 L

P-- RE-l DATA 2 L

RE-l IEEF H

~ RE-\BAC7

:D
:D

BUF
COM
REG

RE-l SEL 2 H

RE-l B5ELO H

RE-1 BAC4

~ RE-\ BAC5

;:u

RE-1 SELl H

~ RE-11BAC2

OC-2 RCMR

(RE-2)

RE-l CEMAl H

P-- RE-l DATA 5 L
P-- RE-l DATA 6 L
~ RE-l DATA 7 L

RE-1 CEMA2 H

>-- RE-l DATA 8 L

RE-\BAC9
RE-l SEL16 H
RE-1tAC10

>-- RE-l DATA 9 L

PIO
COMMAND
REGISTER

RE-l SEL S H

:>-- RE-l DATA 10 L

RE-ltAC11

;::u

(RE-l)

OC-2
A C ENABLE

RE-l DEN 5 H

:>-- RE-l DATA 11 L

(RE-ll

OJ2
LCMR

EMAO L
BRK
::LY--EMAl L } FIELD
~

;::=LJc>-- EMA2 L
CB-2 MAC1 H
8E~ 0709

Figure 9-13 LCMR and RCMR Instruction Data Flow

(6716)
OC -2 LFGR

OC-2 RFSR L

RE-1 BACO

RE-l FRO L

RE-l DATA 0 L

RE-1 BAC1

RE-1 FR 1 L

RE-1 DATA 1 L

RE-1 BAC2

RE-1 FR 2 L

RE-1 DATA 2 L

RE-l BAC:3

RE-1 FR:3 L

FUNCTION
REGISTER

RE-1 DATA:3 L

RE-l BAC4

ENABLE CHECK CHAR L

RE-1 BAC5

RE-l GO L

RE-l BAC 6

RE-l EMA INC
(RE-1)

DATA
BUS
GATING

RE-l DATA 4 L
RE-l DATA 5 L

SC-1 7 CHAN+ DEN 5 L

RE-1 DATA 6 L

ENABLE L
RE-1 DATA -7 L

NOT USED
(RE-2)

-----SC-1 EMA 7 INC

SC-2 DATA S L

SC-2 VP ERROR H
5C-2 CRC ERROR H

5C-2 DATA 9 L
DATA
BUS
GATING

5C-2 LRC ERROR H

5C-2 DATA 10 L
SC-2 DATA 11 L

(5C-2)

OC- 2 RF5R L
(6716)
SE-0710

Figure 9-14

LFGR and RFSR Instruction Data Flow
9-27

Table 9·12
Function Register Contents and Functions
Function

Bit No.
Bit 0,1, and 2

Function Selection: These bits determine the function
the transport is to perform.

Bit 0

Bit 1

Bit 2

Rewind: The transport rewinds at high speed (150 ips)
to BOT and stops. The MTTF is set when the transport
responds to the Rewind function. The controller can
select and use another transport. The WC and CA
Registers need not be loaded.

Offline: The selected transport is taken Offline and
rewound to BOT. The MTTF is set when the transport
responds to this function and the controller can select
and use another transport. The transport must be
manually reset to the on·line state. The WC and CA
Registers need not be loaded.

Read: Data is transferred from the tape to memory in
the forward direction only. All registers must be loaded.
Read/Compare: Tape data is compared to data in core
memory. All registers must be loaded. If there is a
comparison error, CA incrementation ceases, the R/C
ER ROR bit is set, and tape motion continues to the
end of the record. The CA Register contains the
address of the word that produced the error.

Write: Data is written on the tape in the forward dir·
ection only. All registers must be loaded. The Write
function is controlled by WC OVERFLOW (which
disables the Write) ; the transport writes the appro·
priate check characters to end the block.
Write End of File (File Mark): The transport writes
the File Mark, which consists of a one word record.
The CA and WC Registers need not be loaded.

Space Forward: The tape moves forward at 45 ips
the number of records specified by the WC Register,
or until a File Mark is read. If EOT is read, Space
Forward stops at the first interrecord gap. The CA
Register need not be loaded for Space Forward to
occur.

9·28

Table 9-12 (Cont)
Function Register Contents and Functions
Bit No.

Function

Bit 0, 1, and 2 (Cont)
Bit a

Bit 1

Bit 2
Space Reverse: The tape moves in the reverse direction
at 45 ips the number of blocks specified by the WC
Register, or until a File Mark or BOT marker is read.
The CA Register need not be read during a Space
Reverse.

Bit 3

Extended Gap: When bit 3 is a 1, the transport writes
with an additional 3-inch gap between records.

Bit 4

Enable Check Character: When this bit is set (1) and a
9-track transport is selected, it allows the check characters to be read into the computer during a Read
function. When the Word Count overflows, this bit
allows two breaks during 9-track operation for the CRC
and LRC to be transferred to memory. If a Record
Length I ncorrect error occurs, the check character is
considered bad and is not used. This bit is used
primarily for 9-track error correction.

Bit 5

Go: This bit causes the controller to issue a Set command to the transport when the transport is capable
of accepting it. The Set command is not issued if the
specified function is illegal.

Bit 6

EMA I NC Enable: If this bit is not set (0), the TMS-E
(like all other PDP-S data break options) treats the
extended memory the same way, i.e., each 4K block
is used in a wrap-around mode. If this bit is set (1),
the extended memory is treated as a continuous
memory rather than 4K blocks. When the last location
in one field is reached, the EMA bits are incremented
and the transfer continues in the next field; i.e., if a
word is placed in Field 2, location 7171, the following
word is placed in Field 3, location 0000 if the EMA
increment bit is set. If bit 6 is not set, the word is
placed in Field 2, location 0000.

9-29

Table 9-12 (Cont)
Function Register Contents and Functions
Bit No.

Function

Bit 6 (Cont)

I n both modes of operation, the Current Address is set
to one less than the first location to be accessed. In
EMA increment mode, the 12-bit CA Register and the
three EMA bits are treated as one 15-bit register with
the EMA bits most significant. For example, to access
Field 2, location 20, load EMA = 2 and CA = 0017; to
access Field 2, location 0, load EMA = 1 and CA = 7777.
If Field 7 is selected, the EMA cannot increment, but
wraps around in Field 7 and an EMA 7 INCREMENT
ERROR occurs.

RE-I DBC2 L

),
RE-I BAC 0 H

RE-3 MPX 0 H

RE-I DB 0 H

RE-I DATA 0 L

RE-I BAC I

RE-3 MPX I H

RE-l DB I H

RE-l DATA I L

..
RE-I BAC2

RE-3 MPX 2 H

RE-IDB2H

RE-l DATA2L

RE-lBAC3

RE-3 MPX 3H

RE-IDB3H

RE-l DATA 3L

RE-I BAC4

RE-3 MPX 4 H

RE-I DB4H

RE-I DATA 4L

RE-I BAC5

RE-3 MPX 5 H

MULTIPLEXER

DATA
- - -BUFFER - -

RE-I DB5H

DATA
BUS
GATING

RE-I DATA 5L

RE-I BAC6 H

RE-3 MPX 6 H

RE-lDB6H

RE-IBAC7H

RE-3 MPX 7 H

RE-1 DB7H

RE-1 DATA 7 L

RE-I BAC8 H

RE-3 MPX 8H

RE-I DB8 H

RE-IDATA8L

RE-I BAC9 H

RE-3 MPX 9H

RE-IDB9H

RE-IDATA9L

RE-1 BACIO H

RE-3 MPX 10 H

RE-IDBIOH

RE-IDATA10L

RE-I BACI1 H

RE-3 MPX 11 H

RE-1 DB 11 H

RE-I DATA II L

IRE-31

IRE-ll

CB-2 MPX
A

CB-2 MPX
B

Figure 9-15

CB-2 DBCI L

RE-1 DATA 6L

IRE-I)

'I'
OC-I RDB

8£- 070 ('

LDBR and RDBR Instruction Data Flow

Read Word Count Register (RWCR)
Octal Code:

6711

Operation:

Clears the AC and transfers the contents of the WC Register into the AC (Figure 9-11). This
instruction is used primarily for maintenance, but it can also be used during error check routines.

Clear Transport (CL T)
Octal Code:

6712

Operation:

Clears the transport master registers and all TMS-E registers and flags.

9-30

Read Current Address Register (RCAR)

Octal Code:

6713

Operation:

Clears the AC and transfers the contents of the CA Register to the AC (Figure 9-12). This instruction
is used pri marily for maintenance, but it can be used for error check routines.

Read Main Status Register (RMSR)

Octal Code:

6714

Operation:

Clears the AC and transfers the contents of the Main Status Register to the AC (Figure 9-16). The
12-bit Status Register contains the status of the transport and control logic (Table 9-13 and Figure
9-9).

SC-2 ERROR L

DATA 0 L

SC -2 REWINDING L

DATA I L

SC-2 BOT L

DATA 2 L

SC-1 SELR H

DATA 3 L

SC- 1 PARITY ERR L
SC-2 FM L
SC-1 R ECO RD LENGTH
INCORRECT L

DATA 4 L
MS
DATA
BUS
GATING

DATA 5 L
DATA 6 L

SC -1 DATA LAT E L

DATA 7 L

SC-2 EOT L

DATA 8 L

SC-2 WRL L

DATA 9L

o C-1 RC ERROR L

DATA 10 L

SC-2 ILLEGAL
FUNCTION L

DATA 11 L
(SC-2)

'(
OC-2 RMSRL
BE-070a

Figure 9-16 RMSR Instruction Data Flow

Read Command Register (RCMR)

Octal Code:

6715

Operation:

Clears the AC and transfers the contents of the Command Register to the AC. The contents of the
Command Register for this instruction are the same as that for the Load Command Register
instruction shown in Table 9-11 and Figure 9-7.

9-31

Table 9-13
Main Status Register Contents and Indications
Bit No.

Status Indication

Error: The ERROR flag interrupts the processor if bit 4 in the Command Register is set (1).
An ILLEGAL FUNCTION or SELECT ERROR sets the MTTF flag immediately and stops
Data Break operations. The following errors, if they occur during any operation, set the
ERROR flag after the MTTF flag is set.
a.
b.
c.
d.
e.
f.
g.
h.

BOT
EOT
READ/COMPARE ERROR
Parity Error (VPE, CRCE, or LRCE)
RECORD LENGTH INCORRECT
File Mark (EOF)
DATA LATE
EMA 7 INCREMENT ERROR

Rewind Status (RWS): A 1 indicates the selected transport is rewinding.
2

-Beginning of Tape (BOT): A 1 indicates the BOT reflective strip is sensed by the selected
transport.

Select Remote: A 1 indicates the selected transport is not on-line.

Parity Error: A 1 indicates a longitudinal parity error, vertical parity error, or CRC error has
been detected.

File Mark (FMK): A 1 indicates the selected transport has detected a File Mark during a
Write FMK, Space, Read, or Read/Compare operation.

Record Length Incorrect: A 1 indicates that during a Read or Read/Compare operation, the
record length was different from the contents of the WC Register. The WC Register is read to
determine whether the record was long or short.

Data Request Late: A 1 indicates the computer failed to service the BR K RQST before the
next data transfer to or from the transport.

End of Tape (EOT): A 1 indicates the EOT reflective strip has been sensed by the selected
transport.

File Protect: A 1 indicates the selected transport has a write lockout ring removed, and no
write functions are accepted.

R/C ER ROR: A 1 indicates a comparison failure occurred during the Read/Compare
function. The CA Regjster contains the address of the word that produced the error.

9-32

Table 9-13 (Cont)
Main Status Register Contents and Indications
Bit No.
11

Status Indication
A 1 indicates one of the following Illegal Functions has been programmed.
1.
2.
3.
4.
5.
6.

Execution of LCMR, LFGR, or LDBR while the control is busy.
Specifying any density but 800 bpi for a 9-track transport.
A Space Reverse function when the transport is at BOT.
Read, Read/Compare, or Space Forward after a Write or Write End of File
(WEOF) command on same transport.
Changing to transports that are not ready (TUR is false).
Attempting to rewind when tape is at BOT.

Read Function Register and Second Status Register (RFSR)

Octal Code:

6716

Operation:

Clears the AC and transfers the contents of the Function Register and Second Status Register to the
AC (Figure 9-14). The contents of the Second Status Register and Function Register are shown in
Table 9-14.

Table 9-14
Second Status Register Contents and Functions
Bit No.

Function

Not used.

EMA 7 INC ERROR: EMA 7 INC ERROR occurs if an attempt is made to increment the
EMA from Field 7 to Field O. The data wraps around in Field 7.

Vertical Parity Error (VPE): A 1 indicates that a VPE error has been detected. This bit is set
only on the character that is bad and cleared by the next good character.

CRC Error (CRCE): A 1 indicates a CRC error has been detected.

Longitudinal Parity Error (LPCE): A 1 indicates an LPCE has been detected.

Read Data Buffer Register (RDBR)

Octal Code:

6717

Operation:

Clears the AC and transfers the contents of the Data Buffer Register to the AC (Figure 4-15). This
instruction can be used in an error check routine to read the contents of the LRC Register.

9-33

Skip If ERROR Flag Is Set (SKEF)

Octal Code:

6721

Operation:

Skip the next instruction if the ERROR flag is set.

Skip Control Not Busy (SKCB)

Octal Code:

6722

Operation:

Skip the next instruction if the control is not busy. Control is busy when the transport is in a GO
condition, control is not busy when MTTF is set at the End of Job (data transfer completed).

Skip Job Done (SKJD)

Octal Code:

6723

Operation:

Skip the next instruction under following conditions.

When JOB DONE (MTTF) is set at LRCS time of a Read, Read/Compare, Write, or
Write File Mark operation.

At the I RG following EOT, FM K, or WCOV during space operations.

MTTF is set by OFFLINE function, SELECT ERROR, or REWINDING status.

MTTF is set by an LDBR (Load Data Buffer Register) instruction.

Skip if Tape Unit Ready (SKTR)

Octal Code:

6724

Operation:

Skip the next instruction if TUR is true.

Clear All Registers and Flags (CLF)

Octal Code:

6725

Operation:

Clear all TMS-E registers and flags if TU R is true. If TU R is false clear MTTF, ERROR flag, and status
registers.

Check for Data Late Error (CKDL)

Octal Code:

6726

Operation:

Force a DATA LATE error condition during a data transfer. This instruction is used only for
maintenance (Paragraph 9.13.6).

Set Break Request (SBRM)

Octal Code:

6727

Operation:

Set BRK RQST for one Data Break. This instruction is used for maintenance only.

9-34

9.10 OPERATION AND PROGRAMMING
TMS·E operation and programming for each of the DECmagtape functions is described in the following paragraphs.
The timing necessary to perform each function and an example of the method used to program the TMS-E are
illustrated for each DECmagtape function. A flow diagram of TMS-E functions is illustrated in Figure 9-20. The logic
used to accomplish these operations is discussed in Chapter 4; the signals on the timing diagrams are defined in Table
9-15.
Table 9-15
TMS-E Signals and Signal Functions
Signal

Origin

Function

BAC O-BAC 11

Processor
AC

A 12-bit data word transferred from the Processor AC to load
TMS-E registers.

OC-2 AC ENABLE

MS321

AC ENABLE is asserted any time a 670X instruction is
executed to enable bits on the Data Bus to be applied to the
TMS-E registers.

CBOT

TU10

BOT indicates the reflective strip at the beginning of the tape
is being sensed by the tape transport. If the transport is
REWINDING or doing a SPACE REVERSE operation when C
BOT is asserted, the transport stops.

*BREAK CYCLE L

MS322

* BRK IN PROG L

MS322

* BRK ROST

MS322

The BRK ROST flip-flop is set by an SBRM instruction or
during the Write, Read, and Read/Compare operations to
initiate the Single Cycle Data Break and transfer data.

RE-1 B SEL 0
RE-1 B SEL 1
RE-1 B SEL 2

MS327

RE-1 B SEL 0 through RE-1 B SEL 2 are outputs of the
Buffered Command Register applied to the TU10. They are
compared with RE-1 SEL 0 through RE-1 SEL 2 on the
MS323 module; if they are different, the CB-2 CHG TRANS L
signal is asserted.

*BUSSTROBE

Processor
MS323

***

OC-2 CCAR

MS321

OC-2 CCAR is asserted when a 6702 instruction is executed to
clear the CA Register.

*CO and C1

MS321

OC-2 CLF

MS321

Clear all Flags (CLF) is asserted when the 6725 instruction is
executed to clear the TMS-E and the Transport Master System
Register if tape unit is ready (TUR). If tape unit is not ready,
clear status register, MTTF, and ERROR flag.

*OMNIBUS signals.
**Refer to Table 9-3, PDP-8IE & PDP·8IM Small Computer Handbook.
***Refer to Table 9·2, PDP-8IE & PDP-81M Small Computer Handbook.

9-35

Table 9-15 (Cont)
TM8-E Signals and Signal Functions
Origin

Function

CB-3 CLR ALL L

Processor
M8322
M8321

Signal asserted by INIT from processor, SC-' TUR AND OC-2
CLF, OC-2 CL T, and the INITIALIZE instruction to clear all
TM8-E and TU10 Master System registers.

CB-3 CLR STATUS

M8322

CB·3 CLR STATUS is asserted to clear the status registers,
ERROR flag, and MTTF if a CLF instruction is executed and
C TUR is not asserted by the transport.

SC-1 CONTROL BSY

M8323

The Control Busy flip-flop is set by an RE·1 GO command at
the Command Register (bit 5 = 1) on the next TP4 time and
cleared by MTTF.

SC-1 COUNT CA L

M8323

SC-1 COUNT CA L is asserted at Break Request time. If the
Read/Compare (R/C) ER ROR flag is set to stop incrementing
the CA Register, the address of the data that produced a
Read/Compare error is left in the CA Register.

C REV H

M8321

C REV H is asserted by the Space Reverse function.

CB-2 CHG DIR L

M8322

The Change Direction flip-flop is set any time a change in
direction is sensed.

C SOWN L

TU10

Tape Settling Down (C SOWN L) is asserted 2.3 ms after the
MTTF flag sets for 10 ms.

C LRCS L

TU10

LRC Strobe (C LRCS) is asserted by the TU10 when a LRC
character is read from the tape.

C CRCS L

TU10

CRC Strobe (C CRCS) is asserted when a CRC character is
read from tape.

C VPE L

TU10

Vertical Parity Error (C VPE L) is asserted when the TU 10
detects a vertical parity error to set the VPE flip-flop.

C CRCE L

TU10

Cyclic Redundancy Check Error (C CRCE L) is asserted when
the TU 1 0 detects a C RC error.

C LRCE L

TU10

Longitudinal Redundancy Check Error (C LRCE L) is asserted
when the TU10 detects an LRC error.

C SELR L

TU10

Select Remote (C SELR L) is asserted when the transport is
selected and on-line. Other status signals are not valid until C
SELR L is asserted.

CSEL16H

M8327

For future use.

C FWD H

M8321

C FWD H is asserted by Read, Read/Compare, Write, Write
File Mark, and Space Forward functions.

Signal

9-36

Table 9-15 (Cant)
TMS-E Signals and Signal Func~ions
Signal

Origin

Function

C RWS L

TU10

Rewind Status (C RWS L) is asserted any time the selected
transport is rewinding.

C CRCE

TU10

The CRC Error (CRCE) is set when the TUl 0 detects a CRC
error.

CB-3 T INIT L

MS322

T INIT (tape initialize) is asserted by Space Reverse at BOT,
Select Error, and CLR ALL L.

C INIT L

MS321

C INIT L (initialize transport) is asserted by INIT from
processor.

CSET H

SET (C SET H) is generated by the TMS-E to initiate transport
operation.

CREW H

MS321

CREW H is asserted when lXXX is loaded into the Function
Register and initiates the Rewind operation. The three bits are
decoded by the Output Control Function Decoder and applied
to the tape transport. The transport rewinds to BOT and stops.

CWDR H

MS322

Write Data Ready (C WO R H) is asserted by SC-l SET during a
Write operation and is negated when Word Count goes to zero
by Word Count Overflow (CB-l WCOV).

CWFMK H

MS321

Write File Mark (C WFMK) is asserted when 5XXX is loaded
into the Function Register. The 3 bits (FRO-FR2) are
decoded by the Output Function Decoder, and C WFMK is
asserted to cause the TU10 to write the End of File Mark
(EOF).

CWRE H

MS321

Write Enable (C WRE H) is asserted to inform the TU10 that
the TMS-E is ready to Write, Write File Mark, or Rewind.

CWDOH
CWDl H
CWD2 H
CWD3H
CW04H
CWD5H
CWD6H
CWD7H

MS321

C WOO H through C WD7 H are data bits to be written on tape
during a Write operation. C WOO Hand C WDl H are not
written on 7-track transports, and they are zero values when
core dump mode is called for on a 9-track transport.

CWXG H

MS321

Extended Gap (C WXG H) is asserted when bit 3 in the
Function Register is a 1 to cause the transport to leave a
3-inch gap between records.

9-37

Table 9-15 (Cont)
TMS-E Signals and Signal Functions
Signal

Origin

Function

SC-l DATA LATE L

M8323

SC-l DATA LATE L is asserted when the computer fails to
service a BRK RQST before the next data transfer to or from
tape.

C RDOL
C RDl L
C RD2 L
C RD3 L
C RD4 L
C RD5 L
C RD6L
C RD7 L

TU10

C RDO L through C RD7 L are data bits read from the tape
during a Read or Read/Compare operation. C RDO and C RDl
are not read from 7-track transports; they are zero values when
the core dump mode is called for on a 9-track transport.

C PEVN L

M8321

C PEVN L is asserted when bit 3 in the Command Register is a
1 to select odd parity. The 7-track transports can use even or
odd parity, but bit 3 must always be 0 when writing on a
9·track tape. Even parity operation on 9-track tapes causes a 1
to be written on channel 3 (on the Parity track) if Data is all
Os.

C RDS L

TU10

Read Strobe (C RDS L) is a 100-ns pulse asserted by the TU10
each time a data character is read from DECmagtape.

CTUR L

TU10

Tape Unit Ready (C TU R L) is asserted by the TU 10 when the
selected tape unit is ready.

C 7CH L

TU10

Seven channel (C 7 CH L) is asserted by the selected transport
if it is a 7-track transport. When C 7 CH L is not asserted a
9-track transport has been selected and eight data bits are
transferred.

CB-3 CHG TRANS L

M8322

The CB-3 CHG TRANS flip-flop sets and asserts CB-3 CHG
TRANS L when RE-l BSEL 0 through RE-l BSEL 2 from the
Buffered Command Register and RE-l SEL 0 through RE-l
SEL 2 are different. CB-3 CHG TRANS is cleared by the next
SC-l SET Pulse.

CPMA DISABLE

M8322

OC-l R/C ERROR L

M8321

The OC-l R/C ERROR flag is set to assert OC-l R/C ERROR
if an error occurs during a Read/Compare operation (data read
from DECmagtape is different from data in memory).

* Refer to Table 9-3, PDP-8IE & PDP-81M Small Computer Handbook.

9-38

Table 9-15 (Cont)
TMS-E Signals and Signal Functions
Signal

Origin

Function

RE-1 DBOO-RE-1 DB11

M8327

R E-1 DB 00 through R E-1 DB 11 is a 12-bit word from the
Data Register which could be data read from tape, data from
the AC, or data from the Memory Data lines_ The input to the
Data Register is controlled by a Data Multiplexer on the input
of the Data Register. These bits are applied to the
Read/Compare Error detection logic to compare them with
memory data during a Read/Compare operation_

CB-2 DB MPX A L

M8322

Selects data for input to the Data Register (Table 9-17).

CB-2 DB MPX B L

M8322

Selects data for input to the Data Register (Table 9-17).

RE-1 DEN 5 H (bit 10)

M8321

See Table 9-12 for these function bits.

RE-1 IEEF

M8327

Enable Interrupt when ERROR flag (RE-1 IEEF) is asserted if
bit 4 in the Command Register is a 1.

RE-1 IEJF

M8327

Enable Interrupt when JOB DONE (RE-1 IEJF) is asserted if
bit 5 in the Command Register is a 1.

RE-1 EMAO
RE-1 EMA 1
RE-1 EMA 2

M8327

RE-1 EMA 0 through RE-2 EMA 2 are used to address
extended memory (Table 9-11). Bit 6 in the Function Register
must be a 1 to use Extended Memory Addressing.

RE-2 EMA 7 INC ERR L

M8327

RE-2 EMA 7 INC ERR L is asserted when the program tries to
increment beyond memory fields 7 and sets bit 8 in the
Second Status Register.

RE-1 EMA INC EN L

M8327

Extended Memory Address Increment (R E-1 EMA INC EN L)
is asserted when bit 6 in the Function Register is a 1 to allow
memory to be treated as a continuous memory rather than 4K
blocks.

RE-1 ENAB CHK CHAR L

M8327

Enable Check Character (R E-1 ENAB CH K CHAR L) is
asserted and sets bit 4 of the Second Status Register if bit 4 of
the Function Register is a 1 to read the CRC and LRC
character from 9-track transports.

RE-1 DEN 8 H

9-39

Table 9-15 (Cont)
TM8-E Signals and Signal Functions
Signal

Origin

Function

SC-2 EOT L

TU10

End of Tape (SC-2 EOT) is asserted if the EOT reflective strip
is sensed by the selected transport. C EOT sets bit S of the
Main Status Register.

SC-2 ERROR L

M8323

The SC-2 ERROR flag is set by anyone of the following
conditions:

a.
b.

c.
d.

e.
f.
g.

h.
i.
j.

EOT
R/C ERROR
PARITY ERROR
BOT
EMA 71NC ERR
REC LENGTH INCORRECT
DATA LATE
EOF
ILLEGAL FUNCTION
SELECT ERROR

The ERROR flag allows the SKIP line to be grounded if the
SKEF instruction is executed by the program.
RE-1 FRO-FR2

MS327

Function bits FRO through FR2 are decoded by Function
decoders in the TMS-E output control module and TMS-E
control module to determine TU10 DECmagtape functions
and generate TMS-E control signals (Table 9-121.

RE-1 GO

MS327

RE-1 GO is asserted when bit 5 in the Function Register is a 1.
R E-1 GO must be a 1 to allow tape operation to start.

SC-2 ILLEGAL FUNCTION

MS323

SC-2 ILLEGAL FUNCTION is asserted by any of the
conditions listed in Table 9-13 to set bit 11 in the Main Status
Register.

INTSTROBE H

Processor

INT I/O L

MS321

INIT

Processor

*Clears all flags in the TMS-E and TU10 Master System. It is
asserted by pressing the CLEAR key on the front panel or by a
6007 lOT instruction.

* Refer to Table 9-3, PDP·8IE & PDP-8IM Small Computer Handbook.)
**Refer to Table 9-1, PDP-8IE & PDP-81M Small Computer Handbook.

9-40

OMNIBUS SIGNALS

Table 9-15 (Cont)
TMS-E Signals and Signal Functions
Signal
*CB-3INT ROST L

Origin
M8322

Function
CB-3 I NT ROST L is asserted by one of the following
conditions:

Bit error in the Command Register is a 1 and the
SC-2 ERROR flag is set.

Bit 5 in the Command Register is a 1 and the JOB
DONE (CB-3 MTTF) flag is set.

I/O PAUSE L *

M8321

C LRCE L

TU10

LRC ERROR (C LRCE L) is set by the TU10 when a LPE is
detected by the Master System.

OC-2 LWCR L

M8321

OC·2 LWCR is asserted to load the WC Register when a 6701
instruction is executed by the program.

OC-2 LDBR

M8321

Load Data Buffer Register (OC-2 LDBR) is asserted when a
6707 instruction is executed by the program to transfer the
contents of the AC to the Data Buffer Register. This
instruction also sets CB-3 MTTF (JOB DONE).

MAO-MA11

OMNIBUS

MAO through MA 11 are used to address 4096 possible
memory locations. During a data break, the CA Register
controls the MA lines to select a memory location for a data
transfer between memory and the DEC magtape.

CB-2 MAC ACC L

M8322

CB-2 MAC ACC is asserted when a BR K ROST is granted to
enable the data transfer and clear BR K ROST.

SC-2 NOT LAST XFER L

M8322

MDO-MD11

Processor

***

MSIR DISABL

M8322

****

CB-l OFFLINE L

M8322 and
M8321

CB-1 OFFLINE is asserted when OXXX is loaded into the
Function Register by a LFG R instruction and the selected
transport rewinds to beginning of tape and stops. The
transport must be manually reset to on-line condition.

SC-l PARITY ERROR L

M8323

The SC-1 PARITY ERROR flip-flop is set when an LRC, CRC,
or VPE error is detected by the selected TU 10 Tape Transport.

* Refer to Table 9-1, PDP-8IE & PDP-81M Small Computer Handbook.
**Refer to Table 9-2, PDP-8IE & PDP-81M Small Computer Handbook.
* * * Refer to Table 9-4, PDP·8IE & PDP-81M Small Computer Handbook.
****Refer to Table 9-3, PDP·8IE & PDP-81M Small Computer Handbook.

9-41

Table 9-15 (Cont!
TM8-E Signals and Signal Functions
Signal

Origin

Function

RE-1 PEVN H

M8327

If RE-1 PEVN is high, the TU10 generates and checks for even
parity; if it is low, the TU 10 generates and checks for odd
parity. The level of RE-1 PEVN is controlled by bit 3 of the
Command Register (when bit 3 is a 1, RE·1 PEVN is low).

POWER OK H*

Processor

POWER OK goes high when a PDP-8/E power failure occurs
and generates a CB-3 CLR ALL to stop all transports and end
any operation occurring at the time of a power failure.

SC-1 PRESET H

M8323

SC-1 PRESET H is a 2.5-ps pulse that is triggered by setting
the RE-1 GO bit in the Function Register to a 1 if the selected
transport is ready (C TUR is true). RE-1 PRESET H triggers
the RE-' SET pulse.

RE-1 RCAR L

M8321

Read CA Register (RE-1 RCAR) is asserted when the 6713
instruction is executed by the program to transfer the contents
of the CA Register to the AC.

OC-1 ROB L

M8321

Read Data Buffer (OC-1 ROB) is asserted by an RDBR
instruction or by CB-2 MAC 1 H during a read data break to
transfer the contents of the Data Buffer Register to the Data
lines.

RE-1 RDBR L

M8321

Read Data Buffer Register (RE-1 RDBR) is asserted when a
6717 instruction is executed by the program to ground OC-1
ROB L and transfer the contents of the Data Buffer Register
to the AC.

SC-1 RECORD LENGTH
INCORRECT H

M8323

SC-1 RECORD LENGTH INCORRECT is asserted and sets bit
6 in the Main Status Register if the record length differs from
the WC Register. The WC Register must be read by the
program to determine if the record was too short or too long.

RE-1 REWIND

M8321

RE-1 REWIND is asserted by the Function Decoders if a
1 XXX is loaded into the three most significant bits of the
Function Register.

RE-1 RFSR L

M8321

RE-1 RFSR is asserted when a 6716 instruction is executed to
transfer the contents of the Second Status Register and
Function Register to the AC.

OC-2 RMSR L

M8321

OC-2 RMSR is asserted when a 6714 instruction is executed
by the program to transfer the contents of the Main Status
Register to the AC.

*OMNIBUS signals.

9-42

Table 9-15 (Cont)
TM8-E Signals and Signal Functions
Signal

Origin

Function

OC-2 RWCR L

M8321

OC-2 RWCR is asserted when a 6711 instruction is executed
by the program to transfer the contents of the WC Register to
the AC.

RE-1 SEL 0 H
RE-1 SEL 1 H
RE-1 SEL 2 H

M8327

RE-1 SEL 0 through RE-1 SEL 2 are loaded into the three
most significant bit positions of the Command Register by an
LCMR instruction. These bits are used to select one of the
eight (maximum) transports for a data transfer operation
(Table 9-11).

SC-1 SET H

M8323

SC-1 SET H is approximately a 5-Jls pulse that is triggered by
setting the GO bit in the Function Register to 1. SC-1 SET H
is applied to the selected TU 10 transports to start tape
movement if TUR is true (Tape Unit Ready).

OC-2 SKIP L

M8321

The OC-2 SKIP line is grounded when one of the following
conditions exist:

SKEF instruction
ERROR flag is set.

SKCB instruction is executed and SC-1 CONTROL
BSY is not set.

SKTR instruction is executed and C TUR is
asserted.

SKJD instruction is executed and the JOB DONE
(CB-3 MTTF) flag is set.

is executed and the SC-2

CB-1 SPACE H

M8322

CB-1 SPACE H is asserted during Space Reverse or Space
Forward operation and continued until EOT, FMK, or WCOV,
is encountered. File Mark is read from the tape.

CB-1 SP FWD L

M8322

CB-1 SP FWD is asserted when 6XXX is loaded into the three
most significant bit positions of the Function Register. The
transport spaces forward the number of records specified by
the WC Register.

CB-1 SP REV L

M8322

CB-1 SP REV is asserted when 7XXX is loaded into the three
most significant bit positions of the Function Register. The
transport spaces in reverse the number of records specified by
the WC Register.

9-43

Table 9·15 (Cont)
TM8·E Signals and Signal Functions
Signal

Origin

Function

SC·1 SELR L

M8323

Select Remote (SC·1 SELR L) indicates to the control that the
selected transport is on·line.

OC-2 SBRM L

M8321

Set BRK RQST Maintenance (OC·2 SBRM) is asserted when a
6727 instruction is executed by the program to initiate one
Single Cycle Data Break.

SC·1 TUR L

TU10 and
M8322

Tape Unit Ready (SC·' TUR L) is asserted when the selected
tape transport is ready.

RE·2 WCOL

M8327

Word Count 0 (WCO) is asserted when the WC Registers read
aliOs to indicate the data transfer is complete. RE·2 WCO is
used to generate CB·1 WCOV (Word Count Overflow).

CB·1 WCOV L

M8322

Word Count Overflow (RE·2 WCOV) is asserted when the WC
Register contains all Os to negate C WDR and end a Data
Transfer operation.

CB·' WR 9 L

M8322

Enables logic to apply 8 bits of data to the selected 9·track
transport during a Write operation.

CB·1 WR 1st 7 L

M8322

Enables the logic to apply the six most significant bits of a
12·bit data word from memory to the selected 7· or 9·track
transport during a Write operation. Tracks 0 and 1 of a 9·track
transport are Os if it is used as a 7·track format.

CB·1 WR 2nd 7 L

M8322

Enables logic to apply the six least significant bits of a 12-bit
data word to the selected 7- or 9-track transport during a Write
operation. Tracks 0 and 1 of a 9·track transport are Os if it is
used to record a 7·track format.

SC·1 WRS L

TU10

Write Strobe (SC·1 WRS) is asserted by C WRS from the TU 10
when the selected transport is ready to write new data: C
WRS is a 100'ns pulse that is asserted once for each character
written on tape.

9.10.1 Single Cycle Data Break
The Single Cycle Data Break is used for data transfers between PDP·8/E core memory and the TU10 DECmagtape
Transports (Figure 9·17). The concept of data transfers and the interrelationship of the Data Break Interface are
explained in Chapter 6 of the PDP-8IE & PDp·8IM Small Computer Handbook, 1972. A detailed description of the
Data Break Interface is explained in Chapter 10, Volume 2. Figure 9·18 is a timing diagram of the Single Cycle Data
Break Interface; reference this diagram during the discussion of the TM8·E functions and programming that follows.
Data flow for the core dump mode of operation is shown in Figure 9·18.

9-44

NOTE
The programs and timing diagrams presented here are not
necessarily the best or only way to program the TM8-E. They
are shown to illustrate TM8-E functional operation and the
interaction of functional groups of logic. The timing diagram
referred to in the description of TM8-E functions is part of the
TM8-E Print Set (Drawing D-TD-TM8-E-1)'
9.10.1.1 Signal Conventions - The following signal conventions are used in the TM8-E.

Interface signals. All signals that are used to interface the TM8-E with the TU1a are preceded by C, e.g.,
C SET L. All signals applied to the TU 1 a are asserted when they are low (O.OV); all signals from the
TU 1 0 are asserted when they are high (+3.0V).

All signals on the TM8-E modules followed by L, e.g., SBRM L, are asserted (true) when they are a.ov.
All signals followed by H, e.g., SEL 1 H, are asserted (true) when they are 3.0V.

All signals on the TM8-E preceded by B, e.g., BTP3 L, are inverted signals or the outputs of holding
registers, e.g., B SEL 0 H.

All signals on the TM8-E have a prefix to indicate their origin as shown in Paragraph 9.7.

9.10.1.2 Write Data - Data can be written on a 7- or g-track DECmagtape only in the forward direction (see
D-TD-TM8-E-1, sheets 7 and 8 for timing diagram). The CA Register must be loaded with the starting memory
address minus one; the WC Register must be loaded with the 2's complement of the number of words to be
transferred. The density and parity bits in the Command Register (Table 9-11) must be set to select tape density,
parity mode, and tape unit. The Write function is controlled by the WC Register such that when WCOV occurs the
data transfer stops. CB-3 MTTF is set when the LRC character passes under the read heads. Note that the WC, CA,
and Command Registers must be loaded prior to the Function Register because the Function Register contains the
GO bit, which initiates tape movement and sets SC-1 CNTL BSY (control busy). If any errors other than illegal
functions or select errors occur during a write operation, the ERROR flag is set after MTTF is set. Operation may be
continued on the same transport in the same direction immediately if the registers are reloaded following MTTF. A
continuous operation may still be achieved when a change direction or change transport is encountered; however C
TU R from the selected transport must be asserted.
9.10.1.3 Read Data - Records are read from a 7- or g-track DECmagtape transport and transferred to memory
only in the forward direction (D-TD-TM8-E-1, sheets 1 and 6 for timing diagrams). The WC, CA, and Command
Registers must be loaded because they are for a Write operation. Density tape unit, and parity must be selected;
density and parity must be the same as they were when the data was written on tape. During a Read operation, the
number of words loaded into the WC Register (in 2's complement) is transferred to memory. If the WC Register is
set to less than the actual record length, only the number of words in the WC are transferred. If the WC Register is
greater than or equal to the actual record length, the entire record is transferred to memory. I n either case, a Record
Length Incorrect Error (SC-1 REC LNG INCORRECT) is generated for evaluation by the program. The WC and CA
Registers contain the number of words read from tape and the address where the last word was stored. The contents
of the WC Register can be checked by the program to determine the cause of error (record too long or too short).
Parity checks are made by the TU 10 as data is read from tape. If any parity errors are detected, the SC-2 E R RO R
flag is set at the same time as CB-3 MTTF. The Second Status Register must be read and evaluated by the program to
determine what caused the error. CB-3 MTTF (JOB DONE flag) is set when the LRCS character is read from tape.
Note that if a 9-track transport is used, a B R K ROST is made for each character read from tape; a 7-track transport
reads two characters before a BRK ROST is made. Core dump mode causes a 9-track transport to operate the same
as a 7-track transport. Continuous operation may be obtained under the same conditions as a write operation. Read
after Write operations set the Illegal Function flag. To read the CRC and LRC characters, bit 4 in the Function
Register must be 1.

9-45

~~-------------------------------------- TU8E CONTROLLER ---------------------------------------------------~~.---PDP8E--+
rCB-lOBCI L

rv"

CRD7

SC-2RD7 H

RE-3MPXll H

RE-IDBII H

RE-lOATA II L

CRD6

SC-2 RD6 H

RE-3MPXIO H

RE-1DBIO H

RE-IDATA 10 L

CRD5

SC-2 RD5 H

RE-3MPX9 H

RE-IDB 9 H

RE-IDATA 9 L

-V

SC-2RD4 H

RE-3MPX8 H

RE-IDB8 H

RE-1DATA 8 L

-V

SC-2RD2 H

CRD4

RE-3MPX7 H

SC-2RD3 H

CRD3
CRD2

CLR

MULTIPLEXER

RE-3MPX6 H

RE-IDATA 7 L

RE-IDB7 H
DATA

------BUF FER

RE-IDB6 H

DATA
BUS
GATING

RE-IDATA 6 L

CRDI

SC-2RDI H

RE-3MPX5 H

CRDO

SC-2 RDO H

RE-3MPX4 H

RE-IDB4 H

CRDP

SC-2RDP H

RE -3MPX3 H

RE-l DB3 H

RE-IDATA 3 L

RE- 3MPX2 H

RE-IDB2 H

RE-IDATA2 L

RE-IDBI H

RE-IDATA I L

W
M8323
Jl

RE-3MPX I H

RE-3MPXO H

-J,

(RE-3)

I
MPX
A

(RE-l)

RE-IDB5 H

(RE-l)

L -

MPX
B

RE-IDATA4 L

RE-IDBOH

CLR

RE-1MPXO H

MDO L

RE-IMPXI H

MOl

RE-I DBO H
TUlO

RE-I DBI H
RE-IDB2H

OC-ICWDO
OC-ICWDI

RE-IDB5 H

DATA

- - - --

MD2 L

RE-IMPX3 H

MD3

RE-1MPX4 H

MD4

MD5

RE-IMPX5 H

OC-ICWD3
OC-ICWD4
OC-ICWD5

OC-ICWD6

OC-ICWD7

M8321
J2

RE-IDB6 H

RE-IMPX6 H

MD6

RE-lOB7 H

RE-IMPX7 H

M07

RE-IDB8 H

RE-l MPX8 H

RE-IDB9 H

RE-1MPX9 H

MD9 L

RE-l DBIO H

RE-1MPXIO H

MDlO L

RE-1DBll H

RE-1MPXll H

MDII L

CB-1WR9 H

OMNIBUS

MULTIPLEXER

BUFFER
OC-ICWD2

RE-1MPX2 H

RE-IDB3 H
RE-IDB4 H

RE-IDATA 0 L

L RDB

CB 2DBC2 L

CB-1DBCL

RE-IDATA 5 L

CB-2DBCl L

MD8 L

CB-2 MPX

CB-2MPX

Figure 9-17 Single Cycle Data Break Data Transfer Data Flow

8E-0706

CB- 2 DBC1 l

~
C RD7

RE-3 MPX11 H

5C-2 RD7 H

C RD6

5C-2 RD6 H

RE-3 MPX9 H

C RD5

5C-2 RD5 H

RE-3 MPX7 H

C'RD4

5C-2 RD4 H

MULTI PlEXER

C RD2

E
R

5C-2 RD2 H

C RDI

,0-> ' "

C ROO

DATA
BUFFER

NOT

RE-l DB6 H

RE-3 MPX4 H

RE-1 DB4 H

5C-2 ROO H U5ED
CB-~ ~
FOR 7
MPX
5C- 2 RDP H CHANNEL A

CROP

""VI

' H "'" "

L CB-1
MPX

DATA
BU5
GATING

0---

RE-l DATA 6 L

p--- RE-l DATA 5 L
~ RE-l DATA 4 L

p--- RE-l DATA 3 L

RE-l DB2 H

~ RE-l DATA 2 L

RE-l OBI H

p--- RE-l DATA 1 L

RE-1 DBO H
(RE-1)

LCB-2
DBC2 l

CBB_1
W Rlst7
, - - .__+_DB
__0~

MB323
Jl

(RE-l)
ClK

RE-l DATA 10 l

p--- RE-l DATA 7 L

RE-l DB3 H
DATA
BUFFER

RE-1 DATA 11 l

p - - RE-l DATA B L

RE-l DB7 H

- - - - - - - RE-l DB5 H

~ RE-l DATA 9 L

RE-l DBB H

RE-3 MPX6 H

RE-3 MPXl H
(RE-3)

RE-l DB9 H

RE-3MPX5 H

RE-3 MPX2 H

"}"-t-

RE-l DBll H
RE-l DB10 H

RE-3 MPX3 H

T
U
1
0

r--

CRD3..J' 5C-2 RD3 H

ClK

RE-3 MPX10 H
RE-3 MPXB H

OC-1
ROB

p---- RE-l DATA 0 L

-.J

CB-2
LDBC2 l
ClK

RE-3 MPXO H

MDO L
MDI L

MD2 L
C WOO

MD3 L

C WDI

MD4 L

CWD2

MD5 L

C WD3

MULTIPLEXER

P
E

0
M
N
I
B
U
5

MD6 L

C WD4
MD7 l
C WD5
MD8 L
CWD6

MD9 L

CWD7

MD10 l

(oC-l)
(RE-1 )

MB321
J2

MOll L

-------'.----------------.,-114----- PDP8E -----i_~1
BE- 0705

Figure 9-18 Core Dump Data Flow

TPl
TP2

n
---1l

TP3
TP4
*INT STROBE
* BRK RQST L

n
n

I
U

CB-2 E26

rLfL
L-

I
U

CB-2 MAC ACC L

TM8-E NO-GO
PRIORITY CB-2GO

* CPMA DISABLE L
* BRK IN PROG L
CB-2 MACl (1)

CB-2 MAC2 (1)

* MS,IR DISABLE L
*MA,MS,LD CNTL

CB-l COUNT WC L
SC-1 COUNT CA L

* BRK CYCLE L
*OMNIBUS SIGNALS AS CONTROLLED BY THE TM8-E
8E-0502

Figure 9-19 Single Cycle Data Break Timing Diagram

9.10.1.4 Read/Compare - The Read/Compare operation (see D-TD-TM8-E-1 sheet 2 for timing diagram) compares
data read from tape with data from memory that is addressed by the CA Register. The WC and CA Registers must be
loaded and density and parity modes must be set. If an OC-1 R/C ERROR occurs, the incrementation of the CA
Register stops and the CA Register contains the address of the data that produced the error. An OC-1 R/C ERROR
also sets bit 10 in the Main Status Register (Figure 9-9). Tape motion continues to the end of record and MTTF is
set. If interrupt is enabled (Figure 9-7), the program is interrupted by an OC-1 R/C ERROR and the Main Status
Register is read to determine if the error was a OC-1 R/C ERROR. The CA Register must be read by the program to
determine the memory location where data was stored that caused the error. Note a Read/Compare operation
cannot follow a Write operation, the tape must be backspaced before starting a Read/Compare operation.
9.10.1.5 Extended Gap - Extended Gap is used with Write operation (bit 3 in the Command Register must be set)
to cause the transport to leave a 3-inch blank space (gap) at the beginning of a record (Drawing No. TD-TM8-E-1,
sheets 1 through 9). This feature is used to leave spaces to separate records or groups of records and to space over
bad spots on tape. Note that the only difference between this operation and a normal Write operation is the time
required to obtain the first write strobe pulse from the TU1 0 (Table 9-15 for definition).
9_10.1.6 Write End of File - The Write End of File operation (D-TD-TM8-E-l, sheet 4) writes a single character on
tape to designate the end of a record or group of records. A 178 is written on 7-track transports and 238 is written
on 9-track transports. On 7- and 9-track transports, the EOF character is followed by an LRC character that is
identical to the EOF character. The WC and CA Registers do not have to be loaded for this operation.

9-48

ONLY

DURING

MAINTENANCE

NO SET OR PRESET
TU10 WILL NOT RUN

OPERATIONS

YES

8E-0570

Figure 9-20 TMS-E Flow Diagram (Sheet 1 of 10)

REWIND

OFFLINE

GO "

K .. GO

LfR

L~GR

GO
CONT

CHG

1
CHG

SEND C SET

C RWD, AND

SEND CREW

C WAD TO THE

TO TRANSPORT

TRANSPORT

BE-0571

Figure 9-20 TM8-E Flow Diagram (Sheet 2 of 10)

9-50

YJ
WRITE

BREAK

INCREMENT'we
CLR 8RK ROST
CLR DATA LATE

MD--'>DB

8E-0572

Figure 9-20 TMS-E Flow Diagram (Sheet 3 of 10)

9-51

~
WRITE

YES

CLR CNTl BSY
CLR GO

CHECK

flAGS

BE-0576

Figure 9-20 TM8-E Flow Diagram (Sheet 4 of 10)

9-52

WRITE FILE MARK

GO'" 0

CHG DIR
OR
CHG TR

YES

WRITE
----~

FILEMARK
SETS ERROR

PROGRAM STOP

FLAG

8E-0573

Figure 9-20 TMS-E Flow Diagram (Sheet 5 of 10)

9-53

READ OR READ/COMPARE

GO=O

GO= 1

READ/COMPARE

1 TRACK TRANSPORT

9 TRACK TRANSPORT

READ/COMPARE

BE-O~74

Figure 9-20 TM8-E Flow Diagram (Sheet 6 of 10)

9-54

YES

SHORT
RECORD

CLR GO
CLR BRK RQST
ClR CNTL BSY
SET
RECORD
LENGTH
CHECK FLAGS

CLRGO
CLEAR BRK ROST

NOTE
IF BIT 4
IN THE COMMAND
REGISTER IS SET

CLEAR CNTL BSY

DO TWO MORE
BREAKS TO READ LRC AND CRC

Figure 9-20 TMS-E Flow Diagram (Sheet 7 of 10)

9-55

7 TRACK TRANSPORT
READ/COMPARE

CLR GO
CLR BRK RQST

ClR CNTl BSY

CHECK FLAGS

STOP
INCREMENT

8E-0577

Figure 9-20 TM8-E Flow Diagram (Sheet 8 of 10)

9-56

C)J
9 TRACK TRANSPORT
READ/COMPARE

SET ERROR IF ANY
CLR GO

CLR BRK ROST
CLR CNTL BSY

CHECK FLAGS

CLR BRK RQST AND
DATA LATE

DISABLE
CA

INCREMENT

LONG
RECORD

8E-0518

Figure 9-20 TMS-E Flow Diagram (Sheet 9 of 10)

9-57

~
SPACE

GO==O

YES

CHECK
FlAGS

YES

8E-0579

Figure 9-20 TM8-E Flow Diagram (Sheet 10 of 10)

9-58

9.10.1.7 Space Forward - The Space Forward operation (see D-TD-TM8-E-1, sheet 5 for timing diagram) causes
the tape to space forward a number of records specified by the WC Register. The WC Register must be loaded with
the 2's complement of the number of records to be spaced over. The WC Register is incremented by the C LRCS
pulse at the end of each record. CB-3 MTTF sets when the WC Register overflows and the last record has been passed
over. Note that an attempt to Space Forward when the tape is at EOT is an error that sets the SC-2 ERROR flip-flop
after CB-3 MTTF is set. Space Forward is terminated if a File Mark is encountered. SC-2ILLEGAL FUNCTION is
set if Space Forward is initiated after a Write or Write File Mark function.
9.10.1.8 Space Reverse - The Space Reverse operation (see D-TD-TM8-E-1, sheet 3 for timing diagram) causes the
tape to space reverse a number of records specified by the WC Register. The WC Register must be loaded with the 2's
complement of the number of records to be spaced over. CB-3 MTTF sets when the WC Register overflows and the
last record has been passed over. Note that an attempt to do a Space Reverse operation when tape is at BOT is an
illegal function that sets the SC-2 I LLEGAL FUNCTION flip-flop and ends the operation. A Space Reverse
operation is terminated if a File Mark, BOT, or WCOV is encountered.
9.10.1.9 Rewind - The Rewind operation causes the tape to rewind at high speed (150 ips) to BOT. The WC and
CA Registers need not be loaded for this operation. CB-3 MTTF is set when the selected transport asserts Rewind
Status. After one transport is given the command to rewind another transport can be selected for other operations.
If the selected unit is rewinding, C TUR is false (not ready) and no operations can be performed on that transport.
9.10.1.10 Continuous Operation - As previously stated, an operation ends when the CB-3 MTTF (JOB DONE) flag
is set. To continue an operation after CB-3 MTTF sets, the program must execute the LFGR instruction before
SOWN (tape settling down time) to restart the transport and continue the operation. Note that the WC and CA
Registers may have to be loaded to select new Word Count and Memory Address parameters. The operation
continues until the WC Registers overflow and the operation is terminated.
9.10.2 Programming Notes and Examples
This section is not designed to teach programming but to give some programming notes and examples to be used in
programming the TM8-E. For programming information, refer to the following PDP-8/E handbooks:
a.
b.

Introduction to Programming, 1970
PDP-8IE & PDP-81M Small Computer Handbook, 1972

9.10.2.1 Programming Notes - The only programming restrictions to be considered are those that generate SC-2
I LLEGAL FUNCTIONS (Table 9-13), which includes attempting to perform Read operations after Write operations.
To read after writing a record, the program must do at least one tape move operation, i.e., Space Reverse or Rewind.
9.10.2.2 Programming Examples - The following routine is an example of the method to be used to program the
TMS-E. Note that in this particular example program interrupts are not used.
The general method of calling this TMS-E routine is as follows:

Set locations "COMMAND" (Figure 9-8), "CUR ADR," "WRD CNT," and "FUNCTN" (Figure 9-9) as
indicated at the end of the TMS-E routine.

Execute" JMS TM8-E."

The routine returns to the next location if and only if the CB-3 ERROR flag is set with the final contents of the
Function/Status Register in the MQ and the final contents of the Main Status Register in the AC. Refer to Table
9-13 for conditions to set the CB-3 ERROR flag. The routine returns to the second location following "JMS TM8" if
the ERROR flag is cleared (the AC is all Os and the MQ is unchanged).

9-59

TM8E,

o
ClA
ClF
TAD
lCMR
ClA CMA
TAD
lCAR
TAD

TM8ENO,

TM8EOK,

lWCR
TAD
lFGR
SKEF
SKP
JMP
SKTD
JMP
SKEF
JMP
RFSR
MOL
RMSR
SKP
ISZ
ClF
JMP 1

COMMAND,

FUNCTION,

CURADR,

WRDCNT,

COMMAND

Enter here.
Ensure AC = 0000
Clear TM8·E flags.
Get drive, parity, field, and density.
load Command Register.
Get starting address minus one.

CURADR
WRDCNT

FUNCTION

TM8ENO

load CA Register.
Get 2's complement of the number of words to be transferred
or records to be spaced.
load WC Register.
Get Function, Gap, GO bit, and EMA Increment.
load Function Register and GO.
Wait for ER ROR flag or MTTF flag.
ERROR flag set.

.-4
MTTF set? ERROR flag set?
No. No errors reported for this operation.
ERROR flag set. Read Function/Status.
Register and load into MO.
Read Main Status Register and leave in AC.
Bypass return address update if in error.
TM8E
No error reported then update return address.
Clear TM8·E flags.
TM8E
Exit.
This location must contain all information to be loaded into the TM8·E Command
Register.
This location must contain all information to be loaded into the TM8·E Function
Register.
This location must contain the first memory address minus one to be used in
Write, Read, or Read/Compare operations.
This location must contain the 2's complement of absolute value of the number
of words to be transferred in Write, Read or Read/Compare operations, or the
absolute number of records to be spaced in Space Forward or Space Reverse
operations.
TM8EOK

The following is an example of a TM8·E routine using the Program Interrupt System.
TM8·E

0
ClA
ClF
TAD
IOF
lCMR
ClACMA
TAD
lCAR
TAD
lWCR

COMMAND

WRDCNT

Enter here.
Clear AC (AC = 0000).
Clear TM8·E flags.
Get drive, parity, field, and density (Table 9·12).
Turn PDP·8/E Interrupt System off.
load Command Register (Table 9·11).
Get starting address minus one.
CURADR.
load CA Register.
Get 2's complement of number of words to be transferred or
records to be spaced.
load WC Register.

9·60

TM8-E (Cont)

Poll another
Device
TM8-E No,

TM8EOK,

TAD
lFGR
ION
INTSET,
TM8-EOK

FUNCTN

Get F unction, Gap, GO bit, and EMA Increment (Table 9-13).
load Function Register and GO (Table 9-13).
Turn on program interrupt system.
ERROR flag set.
Service another device if Interrupt Request is made_
If ERROR flag is set then Read Function/Status Register and
load into MO.

RFSR
MOL
RMSR
ISZ
ClF
JMP 1
INT SER

TM8-E

Read Main Status Register and leave in AC.
No error reported then update return address.
Clear TM8-E flags.

2
Continue servicing other devices.

SECTION 4 DETAILED LOGIC
The logic in the TM8-E is broken into functional groups for discussion purposes. Figure 9-21 should be used to
understand the interaction of the logic, signal flow between groups of logic, and the input or output signals_ The
purpose of each group of logic is discussed in Paragraph 9.8.
NOTE
The signals on the TM8-E print set are preceded by two letters
and a number to indicate the origin of the signal, i.e., a signal
with SC1 in front of it originates on sheet 1 of the status and
control module prints. Signals without prefixes are OMNIBUS
signals.

9.11

M8321 OUTPUT CONTROL MODULE

9.11.1

I nput/Output I nstruction Decoder

The I/O Instruction Decoders (Figure 9-21) decode instructions from the Memory Data Bus and generate signals to
control the operation of the TM8-E. Bits MD 3 through MD 11 are gated by I/O PAUSE when an I/O instruction is
executed by the processor. Bits MD 3 to MD 6 generate a signal, 67XX, which partially enables the gates to the I/O
Decoders. MD 7 and MD 8 generate a signal (670X, 671 X, or 672X) to apply bits MD 9, MD 10, and MD 11 to the
I/O Decoder. Each I/O Decoder is an 8251 IC; the 8251 IC is a Binary-to-Decimal Decoder (see Appendix A of
Volume 1 for a truth table, logic diagram, and pin locations), which decodes MD 9 through MD 11 and produces a
low on one output line. The low out of the 8251 IC indicates which instruction is to be executed. As an example, a
670X instruction with MD 9 low and MD 10 and 11 high (100) produces a low on pin 4 of the 670X Decoder to
indicate that a lFGR instruction (6706) was executed by the program. I NT I/O l is grounded to prevent execution
of lOT instructions by the processor while TM8-E instructions are underway.
9.11.2 C Line Select Logic
The C line Select logic (Figure 9-21) controls the direction of data flow between the Data Bus and AC and
determines if the AC is to be cleared or not. Table 9-16 shows the status of CO and C1 to transfer data between the
AC and Data Bus using the TM8-E lOT instructions.
9.11.3 TP3 Logic
TP3 is used to enable the selection Of the 670X I/O Decoder and is used throughout the TMS-E to enable the
execution of instructions (Figure 9-21) and to enable data transfers using the Single Cycle Data Break Interface.

9-61

P/O M8321 (OC-2)
6721 (SKEF)
E26
(672X) p::.==-='-'"'-=
P"-~~

8fgl

MD 7 --.-~

Table 9-16
C Line Select Levels for TMS-E Transfer Operations
Instruction

LWCR
LCAR
LCMR
LFGR
LDBR
RWCR
RCAR
RMSR
RCMR
RFSR
RDBR

Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low

High
High
High
High
High
Low
Low
Low
Low
Low
Low

Transfer of Operation
AC ~ Data Bus 0 ~ AC
AC~ Data Bus O~ AC

AC ~ Data Bus 0 ~ AC
AC ~ Data Bus 0 ~ AC
AC~ Data Bus O~AC
Data Bus~ AC
Data Bus~ AC
Data Bus~ AC
Data Bus~ AC
Data Bus~ AC
Data Bus~ AC

9.11.4 CLR ALL Logic
CLR ALL L (Figure 9-21) is asserted to clear TM8-E logic under the following conditions:

At TP3 time, if a CLT (6712) instruction is executed by the program.

When a CLF (6725) instruction is executed by the program if C TUR is true.

When PWR OK H from the processor is lost due to a power failure.

When the processor asserts INIT H. This occurs during power up or when the CLEAR key is depressed
on the PDP-8/E console.

9.11.5 AC ENABLE Logic
OC-2 AC ENABLE (Figure 9-21) is asserted when a 670X instruction is executed by the program to enable gates to
apply the Data Bus information to the TM8-E registers that are loaded from the AC (Figure 9-27) and Control CO
andC1Ievels(Paragraph9.11.1).
9.11.0 Skip Logic

The Skip logic (Figure 9-22) asserts OC-2 SKIP BUS L and causes the processor to skip an instruction when the
following conditions exist.

a.
b.

c.
d_

The 6721 (SKEF) instruction is executed and the SC-2 ERROR flag is set.
The 6722 (SKCB) instruction is executed and SC-1 CNTL BSY flag is set.
The 6723 (SKJD) instruction is executed and CB-3 MTTF flag is set.
The 6724 (SKTR) instruction is executed and C TUR L is true.

9.11.7 Output Control Function Decoder
The Output Control Function Decoder (Figure 9-23) is an 8251 IC, which decodes the three most significant bits of
the Function Register and determines what function the TU10 Transport performs (Table 9-12). The 8251 IC is a
BCD-to-Decimal Decoder (see Appendix A, Volume 1, for truth table, logic, and pin locations) which decodes FRO,
FR 1, and FR2 and produces a low on one output line. The low out of the 8251 IC indicates the function to be
performed. As an example, if FRO is low, and FR1 and FR2 are high, pin 9 is low indicating a Write operation is to
be performed. The outputs of the Function Decoder, applied to the TU10, are defined in Table 9-15 and Figure 9-7.

9-63

P/O M8321(OC-2l
SC -2 ERROR L
OC - 2 6721 L -~.. ~

~./

SC-l CON BUSY L
OC-26722L
OC-2
SKIP BUS L
CB-3 MTTF L
OC-2 6723 L

SC - 1 TUR L
OC - 2 6724 L
8E-0548

Figure 9-22 Skip Logic

P/O M8321 (OC-I)

+5V

+3V

r -.....- - - - . - - - - - J 2 - DO CREV H
+3V
JI -x C FWD H

CB-! SPACE REVERSE
RE-l
FRO H
RE-l
FR! H
RE-I
FR2 H

+5V

CB-! SPACE FORWARD
EI2
OUTPUT
CONTROL
FUNCTION
DECODER

>-......

CB-! WRITE

--~-----

CB-I READ/COMPARE

JI-BB C WRE H

CB-l REAO
CB-I REWIND

CB-3INIT H

+3V

CB-! WRITE ENO OF FI LE

+5V

+3V

CB-! OFFLINE

+3V

J2-RR C WFMK H

JI-ZCRWDH

J2-V CWXG H

RE-! FR3 L
E7

CB-2 MAC 2 H
C8-2 RDB L
8E-0547

Figure 9-23 Output Control Function Decoder

9-64

9.11.8 Read/Compare Logic
The Read/Compare logic consists of 12 Exciusive·OR gates and the OC-1 R/C ERROR flag (flip-flop). The 12 bits of
data from the Memory Data Bus (data read from memory) are Exciusively-ORed with 12 bits of data from the Data
Register (data read from tape). During the data break, at TP3 time, if the data from memory is different from data
read from DECmagtape the SC-1 R/C ERROR flag is set and CA incrementation stops. Tape motion continues until
an LRC strobe is obtained at End of Record. RE-1 DEN 5 Hand RE-1 DEN SHare used to enable a gate on the
outputs of the Exclusive-OR gates for the four most significant bits to prevent them from causing a Read/Compare
Error when a 9-track transport is selected. RE-1 R/C ENABLE is always high when a Read/Compare function is
selected by the program. Refer to D-TD-TMS-E-1, sheet 2, for the timing during a Read/Compare operation.
9.11.9 Write Data Select Logic
The Write Data Select logic selects 6 or S bits of data from memory to be written on DECmagtape (Figure 9-24). To
write on a 9-track transport, the gates labeled C on Figure 9-24 are enabled by CB-1 WR 9 H to apply S bits of data
from the Data Buffer Register to the selected transport (see D-TD-TMS-E-1, sheet S, for timing).
When writing on a 7-track transport, CB-1 WR 1st 7 H enables the gates (labeled B in Figure 9-24) for the six most
significant bits and then the gates (labeled A in Figure 9-24) are enabled by CB-1 WR 2nd 7 H for the six least
significant bits. The control signals for the gates originate in the control logic shown in Figure 9-46. The outputs to
the transport are limited to O.OV and +3V levels by the diode and resistor networks tied to the output lines.
9.12 TM8-E REGISTERS (M8327)
The TMS-E Registers are used to address memory, count the words in a data transfer, select DECmagtape operations,
and generate command signals for the TMS-E control logic and the TU 10 Tape Transports. Each of the registers used
in the TMS-E are discussed in the following paragraphs; the Status Register is discussed with the Transport Status
and Control logic in Paragraph 9.13.1 .
9.12.1

Data Buffer Register and Multiplexer

The Data Buffer Register and Multiplexer (Figure 9-25) provides temporary storage for data manipulation (transfers
and Read/Compares). Inputs to the Data Multiplexer come from memory (MD 0 through MD 11), from the AC
(DATA 0 - DATA 11), or from the tape (CRD 0 through CRD 7). The Data Multiplexer is a 741531C (refer to
Section 7 for logic diagram, truth table and pin locations) which selects one of the four data inputs to be applied to
the Data Buffer Register. CB-2 DB MPX A and CB-2 DB MPX B controls the selection of data that is supplied to the
Data Buffer Register. Table 9-17 shows the levels required to load the Data Buffer Register for each operation. CB-1
DBC 1 and CB-1 DBC 2 are used to clock the output of the multiplexer into the Data Buffer Register. The Data
Buffer Register is two 74174 ICs (refer to Section 7 for truth table, logic diagram, and pin locations) each containing
six flip-flops that are set or cleared by the input from the Multiplexer. The contents of the Data Buffer Register are
applied to the Read/Compare logic, to output control logic, and to an S235 IC (refer to Appendix A, Volume 1, for
truth table, logic diagram and pin locations) as shown in Figure 9-26. During a Read operation or when a RDBR
instruction is executed, the data is transferred to the Data Bus. During a Read operation, data is transferred to a
memory location selected by the Current Address Register during Single Cycle Data Break. If the RDBR (6717)
instruction is executed, the data is transferred to the AC via Data Bus. Refer to the flow diagram (Figure 9-20 and
Figure 9-15) for an illustration of this operation. The timing diagrams for these operations are shown in Drawing No.
D-TD-TMS-E-1, sheets 1 through 9.
9.12.2 AC Input Gating
The AC Input Gating (Figure 9-27) is used as a buffer between the Data Bus (inputs from the AC) and the TMS-E
Registers. OC-2 AC ENABLE L is asserted (low) any time a 670X instruction is executed by the program to transfer
data from the AC to the TMS-E Registers. The outputs of the NAND gates enabled by OC-2 AC ENABLE are
applied to the Command, Data, and Function Registers, and to two 74174 ICs, which provide a Holding Buffer for
inputs from the AC. The 74174 ICs (refer to Section 7 for truth table, logic diagram, and pin locations) are 6-bit
buffer registers for inputs to the WC and CA Registers and bits 6 through S of the Command Register. SC-1 B TP3 is
used to clock the outputs of the NAND gates into the AC Holding Buffer Register. The outputs of the AC Holding
Buffer Register are applied to the WC and CA Registers (Figure 9-2S).
9-65

+5V
CB-l WR 1st 7 H -...........~~
MOO L

MOIL

M02 L

+3V
M03L
CWOO H
M04L
CWO 1 H
M05 L
CW02 H
M06L
CW03 H

M07L
CW04 H
MOB L
CW05 H
M09L
CW06 H
M010L
CW07 H
+5V
MOIl L

OC-2 CLR RC
ERROR L
+5V

+5V

L-----------~--------------------------~------------~O

OC-l READ COMPARE L

E3
RC
ERROR
C
0
+3V

Figure 9-24

Read/Compare and Write Data Select Logic

OC-! RC ERROR L

8E-0584

P/O M8327

iCB-2 DB MPX B H

RE-l
BAC 0 HSC-2
R02 H-

MoOL~

~
MOl L f---<f::\
~

.----------,I

.---------.1------.12

I
I

MPX

74153
E13

SC-2
R03 H-

MPX

CB-1R 1st 7L~

I ~B-2
I
I
I ______
-.J ~
I
_ _ _ ..J

RE-l
BAC1H-

P/O M8322(CB-2)

CB-2 MAC2 H
......-CB-2 B TP3 H =lEI9,."\J?E31 )o----;;--d
CB-l WRITE H---l:.-J-

oBC2

CB-l R 9 CH L

OC-2 LoBR L

-.J

114
RE-3 MPXO H
RE-l
BAC 2 H-

M02 L

J~4~MD3L

BACR~-~-

RE-3 MPX' H

MPX

r-I-lL -_ _ _ _ _ _RE-3
____
____
MPX2
H_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

74153
E12

...-<L.:::J SC-2 R05 H- MPX

I-+-J

M05L

RE-l
BAC4H-

E20
~

RE-I

- oBo
-

RE-'
OBI

RE-'
DB2

RE-'
DB3

E19
74174

RE-3 MPX3 H

RoP H -'-r-3"--rr'
114

M04L

RE-3 MPX4 H

RE -3 MPX5 H

RE-'
oB4
RE- ,
oB5

+3V
(RE-ll

MPX
4

SC-2 R06 HSC-2 ROD H- 74153
RE-1 BAC 5 H- E26

:FoJ
--.-1
E20

SC-2 R07 H MPX
SC-2 Rol H-L-r...;5~..-J

114
M06L

I-----------,
P/O M8322(CB-2)
I
I
~...r..
{>E'9*~A
I
I
I
L __ ~:::~:... ___ J

RE-l

~BAC6t-i-

CB-l R 2nd7 L

MPX
6

CB-2 MAC2 H
CB-2 B TP3 H
CB - 1 WR ITE H

SC-2 R02 H L 74153
E25
M07L ~RE-1BAC7H
E20
MPX
SC - 2 R 0 3 H-*-L...,-.:.7..........J

t--d

---

E31

CB-2
oBC1-L

CB-1R9CH"""

114

RE-3 MPX6 H

---<f::\.

RE-,_........1..;;.2~..,
BAC 8 H
MPX
8

RE-'

r- oB6

RE-l

RE-3 MPX7 H

r- oB7
RE-l
RE-3 MPXB H
~----------------------4
r- oBB
SC-2 R04 H L 74153
74174
RE-3 MPX9 H
RE-l
E43
E44
M09 L ~~RE-l BAC 9 H
r- oB9
E36
RE-t
MPX'O H
r MPX -I- r - - - -RE-3
r- oB1O
SC-2 RD5 H -+-....,;--9-n--'
-------------------j
RE-3 MPXtl H
RE-t
114
r- oB11
MOB L

-'n

RE-l
Mol0L ~BAC l o H E36

t--d

~C-2 R06HL

Mol1 L : 8 R E - 1 BAC 11 H
E36

12
MPX
10

(RE-ll

74153
E42

MPX
SC-2 R07 H ....... ....,_1.;..;1'n--'

*Same AND gate
shawn twice an this illustration.

14L

CB-2 DB MPX A H--"'---~

8E-O~B1

(RE-3l

Figure 9-25 Input Data Multiplexer and Data Register

9-67

Table 9-17
Data Multiplexer Selection Levels
Operation

CB-2 DB MPXA H
(pin 14)

CB-2 DB MPXB H
(pin 2)

Load Data Buffer
Write
Read 7 Channels
Read 9 Channels

low
high
low
high

low
low
high
high

PIa M8327

RE-l FRO L

(RE-l)

RE-l DBO
RE-1FR1L
RE-1DBl
RE-l FR2 L
RE-l DB 2

DATA 0
8235
E4

DATA 1
DATA 2
DATA 3

RE-1FR3 L
RE-l DB 3

(RE-l)

RE-l EN CHECK CHAR L
RE-1 DB 4
+5V

I
I
L _____________ ..J
OC - 1
READ L

RE-l GO

DATA 4

RE-1DB5
SC-l 7 CHAN + DEN5 L

~~~~~R~E~-I~D~B~6________~~

8235
E23

DATA 5
DATA 6
DATA 7

+3V
RE-l DB 7

(RE-l)

+3V
RE-1DBS
DATA 8
RE-l DB9
RE-l DB10
RE-l DB 11

8235
E35

DATA 9
DATA 10
DATA 11

(RE-l)

+3V
8E-0569

Figure 9-26 Data Register and Function Register Output Multiplexer

9-68

P/O M8327 (RE-l)

DATA 0 L

BTP3
*RE-I B
ACO H
DA

DATA 1 L

DATA 2 L

DATA 3 L

DATA 4 L

DATA 5 L

DATA 6 L

*RE-I B
AC lH

HBAC
DB

*RE-I B
AC 3 H

9 L

DATA 10 L

DATA 11 L

HBAC 3H

*RE-I B
AC 4H
HBAC4H

*RE-I B
AC 5H
HBAC 5 H

TO WORD COUNT AND
CURRENT ADDRESS REGISTERS

+3V
"RE -1 B '-------,
AC 6H

*RE -I B
AC 7 H

HBAC 6H

HBAC
QB

HBAC 7H

TO BITS 6-8 OF
COMMAND REGISTER

"RE-I B
AC 8H
QC

DC
DATA

HBAC 2 H

74174
E9

DB
DATA

HBAC 1 H

*RE-I B
AC 2H

DA
DATA

HBAC 0 H

"RE-I B
AC 9H

HBAC 8H

74174
E39
DD

HBAC9H

*RE-IB
AC 10H
HBAC 10H

"RE-I B
AC II H
QF

HBACllH

AC ENABLE L

+3V

8E-0551

"OUTPUTS TO COMMAND REGISTER, DATA REGISTER AND FUNCTION REGISTER.

Figure 9-27 AC Input Gating and Holding Buffer Register

9-69

OC -2 LWCR L

P/O M8327(RE-3)

RE -1
HBAC OH
RE-l
HBAC 1 H
RE-l
HBAC 2H
RE-l
HBAC 3H

RE-l
HBAC 4H
RE-l
HBAC 5H
RE-l
HBAC 6H
RE-l
HBAC 7H

DATA OL
8235
E2

DATA 2L
DATA 3L

RE-2
CA 4
RE-2
CA 5

DATA lL

DATA 4L
8235
El7

RE-2
CA 6

DATA 5!,
DATA 6L
DATA 7L

RE-2
CA 7
RCAR L
RE-l
HBAC BH

r;/O-;8;;; (;;

- -

1l-

RE-l
HBAC 9H
RE-l
HBAC 10H

RE-2
CA 8
RE-2
CA 9

RE-l
HBAC 11 H

RE-2
CA 10
RE-2
CA 11

I OC-2
SBRM L

DATA 8L
8235
E33

DATA 9 L
DATA 10L
DATA IlL

E27 }------\--....,
SC-2
BLRCS L CB-l SPACE H

)O--~

L __ "':C-~M:-'

~"--~

J RE-I
HBAC OH

RE-2 CAO L

RE-l
HBAC 1 H
RE-I
HBAC 2H
RE-l
HBAC 3H

RE-l
HaAC 4H
RE-l
HaAC 5H

r
I
I
I
I
I
I

RE-l
HaAC 6H
RE-I
HBAC 7H

P/O M8323 (SC-ll
CB-l
BRK RQST
+3V

SC-2
RC ERROR L

CB-3 CLR
STATUS L
E23

IL _ _ _ _
+3V

I
I
I

RE-l
HBAC 8 H
RE-l
HBAC 9H
RE-l
HBAC 10 H
RE-l
HBAC 11 H

8 E-0583

Figure 9-28 Current Address and Word Count Registers

9-70

9.12.3 Current Address (CA) Register
The Current Address Register (Figure 9-28) is a ripple counter that sequentially addresses locations in memory by
incrementing before each data transfer. The CA Register is loaded with a 12-bit address that is one less than the
desired starting address. The CA Register is incremented by the leading edge of SC-1 COUNT CA L (Figure 9-28)
each time a BRK ROOT is made by the TM8-E. CB-2 MAC ACC is asserted after a BRK RQST is granted to the
TM8·E and removes the SC·1 COUNT CA L signal from the CA Register. The CA Register is not incremented when
SC·1 COUNT CA L goes high because the counter increments only a high-to·low transition of the signal. The CA
Register is loaded by the LCAR instruction before each DECmagtape operation and must not be loaded during
CNTL BSY.
The output of the CA Register is applied to the MA lines when CB·2 MAC 1 H enables the NAND gates (Figure
9-28) to select a location in memory which contains data to be read or a location to store data from the
DECmagtape. The contents of the CA Register are also applied to an 8235 IC (refer to Appendix A of Volume 1 for
truth table, logic diagram, and pin locations) for transfer to the AC when an RCAR instruction is executed by the
program. The CA Register is read by the program during error check routines and maintenance operations to
determine what address in memory generated an error. The CA Register is cleared by an CCAR instruction.
9.12.4 Word Count (WC) Register
The Word Count Register is a ripple counter that (Figure 9-28) counts the data words transferred to or from the
DECmagtape during data transfers and counts the records during space operations. The WC Register is loaded from
the AC with the 2's complement of the number of words to be transferred or number of records to be spaced when a
LWCR instruction is executed by the program.
The output of the WC Register is applied to an 8235 IC (see Appendix A, Volume 1, for truth table, logic diagram,
and pin locations) and is transferred to the AC when an RWCR instruction is executed by the program. When bit 0
makes the transition from the high to low state. RE·2 WC 0 is applied to the CB-1 WCOV flip·flop (Figure 9-21).
CB-1 WCOV indicates to the control logic that the data transfer is complete (the specified number of words have
been transferred). Word Count is incremented during the Break cycle when SC·1 COUNT WC makes a high to low
transition by asserting one of the following:
8.

CB·2 MAC ACC L during a Read or Write operation.
C LRCS L during a CB·1 SPACE operation if a File Mark is .not detected.

9.12.5 Function Register
The Function Register (Figure 9-29) is loaded with 6 bits of data from the AC by an LFGR instruction. The 6 bits
determine the function (Table 9-12) the TU 10 Transport is to perform and provide control signals to initiate
DECmagtape operations. The Function Register consists of two 74175 ICs (refer to Section 7 for truth table, logic
diagram, and pin locations) which contain the flip·flops that are set or cleared by bits from the AC. The three most
significant bits of the Function Register (FRO through FR2) are applied to the output control Function Decoder
(Figure 9·23) and the control Function Decoder (Figure 9·39). FR3 through FR6 are applied to the control logic to
accomplish the functions shown in Table 9·12. The CB·3 MTTF input to the 74175 IC clears the three least
significant bits FR4 through FR6 when the CB-3 MTTF (JOB DONE) flag is set at LRCS time (Figure 9·42).
The outputs of the Function Register are also applied to an output multiplexer (Figure 9·28) for transfer to the AC
when an RFSR instruction is executed by the program. The 8235 IC (refer to Appendix A, Volume 1, for truth
table, logic diagram, and pin locations) transfers the Function and Status to the Data Bus for display in the AC or
evaluation by the program when RE·1 RFSR L is asserted. RE·1 RFSR L is asserted when an RFSR instruction is
executed by the program.
NOTE
The Function Register must be the last register loaded
because it contains the GO bit, which initiates CNTL BSY,
PRESET, and SET to start the tape transport.
9-71

P/O M8327 (RE-l)
E21
OC-2 LFGR L

I
RE-f FRO H
RE-l BAC OH
RE-! BAC 1 H
RE-! BAC 2H

FR
E14
74175

RE-! BAC 3H

RE-f FRO L
RE-! FRI H
RE-j FRI L
RE -1 FR 2 H
RE-j FR2 L

(RE-ll

RE-! FR3 H
RE-l FR3 L

J
o--RE-f ENABLE CHECK CHAR L .
-RE-f GO H

RE-! BAC 4
RE-! BAC 5
RE-! BAC6

FR
E27
74175

o--RE-I GO L
0-- RE-I EMA INC ENABLE

(RE-ll
CB-3 MTT F L

J
BE-OSSO

Figure 9-29 Function Register

9.12.6 Command Register
The Command Register (Figure 9-30) consists of nine flip-flops and a 3-bit ripple counter that are loaded from the
AC when an LCMR instruction is executed by the program (Table 9-11).
The four flip-flops that receive RE-l BAC 0 through RE-l BAC 3 (Table 9-11) as inputs are on a 741751C (refer to
Section 7, for truth table, logic diagram, and pin locations). Three of the flip-flops on this IC generate SEL 0
through SEL 2 for indication of selection of one of the TU10 Transports and provide an input to the Buffered
. Command Register for TU10 Transport selection (Paragraph 9.12.7). AC 03 is used to select odd or even parity
mode for the TU10 Transport. If this flip-flop is in a 0 state, even parity is selected and C PEVN L to the TU10
Master System is asserted.
RE-l BAC 4, RE-l BAC 5, and RE-1 BAC 9 through RE-l BAC 11 are applied to a 74174 IC (refer to Section 7 for
truth table, logic diagram, and pin locations), containing six flip-flops that are loaded by the inputs from the AC
(Table 9-11).
The remainder of the bits from the AC (AC 6 through AC 8) are applied to a 74197 I (refer to Appendix A, Volume
1, for truth table, logic diagram, and pin locations containing three flip-flops to select a memory field during data
transfer. The 74197 IC is a 3-bit ripple counter that is incremented by SC-l EMA INC L if bit 6 in the Function
Register is set (1). The output of the 74197 IC (RE-l EMA 0 - RE-1EMA 2) is applied to the OMNIBUS when CB-2
MAC 1 H enables the three AND gates (Figure 9-0) during a Single Cycle Data Break. Refer to Paragraph 9.13.3 for a
discussion of the SC-1 EMA INC L signal generation.
The contents of the Command Register are transferred to the Data Bus when the progam executes an RCMR
instruction to assert the control input of the 8235 ICs (Figure 9-30). The Command Register is cleared by CB·3 CLR
ALL L (Paragraph 9.11.4).
9-72

~;; ;S;-2;(O"Z-;J -

P/O

.------ RE - I B SEL 0 H
~RE-I B SEL I H
r - RE-I B SEL 2 H

MS327 (RE-ll

E37

I
I
DATA OL I

CB-3 LBCMLl

RE-IBAC OH

RE-I SELOH

RE-I BAC I H

RE-I SEL I H

CM
0-3
74175
EI5

RE-I BAC 2H
RE-\ BAC 3H

RE-I SEL 2 H

c--<
BCM
7495
EIO

DATA I L

8235
E5

I-<

DATA 2L
DATA 3L

I-0-(

+3V

RE-I BAC4H

RE-\ IEEF H

RE-I BAC5H

RE-I IEMF H

RE-I BAC 9H
RE-I BAC10H
RE-I

CM
4,5,
9 -11
74174
E45

r
OC-2
>- LCMR L

r- -

CB-3

~A~-<j

H BAC 6H

H BAC 7H

H BAC 8H

I
I
I

E28
CM
6-8
74197
E3\

RE-2
E28

RE-2

SC - I EMAINC L

l!/~8::7(~-2_)_

I
I
I
I

~EMAI

E2B

EMA2

-CB-2 MAC I H

DATA 9 L

RE-I EMA 2 - - ,

RE-2
EMA 0

I
I

I
I
I
I

- - - - - J

+5V~

DATA 5 L
B235
E29

-+3V

=
+5V

E39

DATA 4 L

DATA 7 L

OC - 2 RCMR L -

J I-T
C SEL 16 H

-+3V

E32

J 1- N
C DEN 8 H

DATA 6 L

J I-J
C SEL 2 H

J 2-NN
C PEVN H

+ 3V

+3V

+5V

E32

J 1- F
C SEL I H

E38

DATA 8 L

+3V

DATA IlL

+5V

DATA IOL
8235
E40

J 1- D
C SEL 0 H

E38

~EMA7H
E30

+5V

E38

I
I

I
I
I

RE-I DEN 5 H

RE-2

RE-I DEN 8 H

BAC 11 H

+3V
E7

- - - - --,

=
-

+3V

E32

J l-R
C DEN 5 H

=
L ____________
....J
8E-0564

Figure 9-30 Command Register and Multiplexer

P/O M8323(SC-2)

+5V

+5V
E19
E23

CB-3 MTTF L

C EOT L

SC-2
ILLEGAL
FUN. L

SC-2 B BOT L

+3V

DATA LATE L --''4--_

C FM L
SC-] RECORD LENGTH
INCORRECT L

SC-l PARITY ERROR L
SC-] EMA 7 INC ERROR L
OC-] RIC ERROR L
SC-] SEL ERROR H ----~
OFFLINE L ----~

E1
ERROR
(MS)

SC-2
ERROR L

CR -3 CLR STATUS L
8E-0559

Figure 9-31 Error Flags

9.12.7 Buffered Command Register (BCM)
The Buffered Command Register (Figure 9·30) receives RE·1 SEL 0 through RE-1 SEL 2 as inputs from the
command register. RE-1 B SEL 1 through RE-1 B SEL 2 out of the BCM are applied to the TU1 0 Master System to
select a transport and provides an input to a comparison circuit to determine when a new transport has been selected
(Figure 9-43). CB-2 CHG TRANS L is asserted if RE-1 SEL 0 through RE-1 SEL 2 from the command register and
RE-1 B SEL 0 through RE-1 B SEL 2 from the Buffered Command Register are different; thus CB-2 CHG TRANS L
is asserted if a new transport is selected by the program. The output of the BCM holds the select lines to the
previously selected transport in the same state until C SDWN L (settled down) is obtained from the transport. Then
the BCM is loaded by RE-2 LBCM L to select a new transport. Thus the BCM allows the program to load the
command and select a new transport without deselecting the previously selected transport before it stops.
9.13 M8323 TRANSPORT STATUS AND CONTROL MODULE
The M8323 Transport Status and Control Module consists of the Main Status Register (Table 9-13), Second Status
Register (Table 9-14), logic for generation of timing and control signals, and a Data Multiplexer to transfer the
contents of the Status Registers to the Data Bus.
9.13.1

Main Status Register

The logic elements that make up the Main Status Register perform as follows.
9.13.1.1 SC-2 ERROR Flag Logic - The SC-2 ERROR flag (Figure 9·31) is set immediately if the program
attempts an illegal function or if SC-2 SEL ERROR is asserted by the selected transport. The SC-2 ERROR flag is
set after CB-3 MTTF is set if any of the following errors are detected.

a.
b.

c.
d.

e.
f.
g.

EOT
BOT
DATA LATE
PARITY ERROR (LRCE, CRCE, or VPE in Second Status Register)
REC LNG INCORRECT
EMA 7 INC ERROR (Second Status Register)
R/C ERROR
File Mark (FM)

9.13.1.2 Illegal Function Logic - The SC-2 I LLEGAL FUNCTION flip-flop (Figure 9-32) is set if the program
attempts any of the following SC-2 ILLEGAL FUNCTIONS:

The program executes an LCMR, LFGR, or LDBR instruction when the SC-1 CNTL BSY flip-flop is set
(Paragraph 9.13.5).

Selection of any density other than 800 bpi if a 9-track transport is selected.

Selection of a Space Reverse operation when the selected TU10 Transport is at BOT.

Selection of Read, Read/Compare, or Space Forward after a Write or Write End of File operation if the
same transport is used.

Changing to a transport that is not ready (C TUR is false) and SC-1 PRESET is issued.

Attempting a Rewind when tape is at BOT.

Any Write command issued to a transport with write lockout set.

9·75

P/O M8323(SC-2)

+5V
CB-1 REWIND L

C BOT L-_---j
SC-2
' - - - - - ~6TR~V.

SC-1 C 7 C H L
RE-I DEN 8 H

SC-1 TUR L

rpl~8~l(07-2)- -

SC-1
CONTROL
BSY L

OC.2 LCMR
OC-2 LFGR
OC-2 LDBR

ILL.
FUN.
(MS)
C E13 0

SC-2
ILLEGAL
FUN. L

L __
SC -1
CLR STATUS L

+5V

r: - - -

---,C WRLL

P/O M8322(CB-l)

CB-1 WRITE

SC-I
PRESET H

WF
-:"" : '

CB -1 SP
FWD L

CB -1 READ L

CB-1 RIC L

fP/OM8322iCB- ij

I
I
I

CB-1 WFM L
E42 }-~-4D 1r-----j
CB-1
WRITE
L
__
__
___ J
E35
SC-1 SET H

CB-3 CHG
CLEAR L

L ________ _

SC -1
PRESET H

SE -0565

Figure 9-32

Illegal Function Flag and Control Logic

9-76

9.13.1.3 Data Late Logic - The SC-l Data Late (Figure 9-33) flip-flop is set if the computer fails to service a B R K
ROST before the next word is transferred to or from tape. A counter made up of flip-flops A, B, and C (Figure 9-33)
counts the Read Strobe or Write Strobe pulses generated by the TU 10 each time a character is read from or written
on tape. SC-l WRS Lor SC-1 B RDS L clocks the three flip-flops (A, B, and C). CB-2 MAC ACC L (Figure 9-33) is
asserted after a BRK ROST is granted to the TMS-E by the processor to clear the counter and prevent the SC-'
DATA LATE flip-flop from setting when the next SC-l WRS or SC-l B RDS pulse occurs. If a 9-track transport is
selected and C8-2 MAC ACC is not asserted by the time the next SC-1 WRS or SC-' B RDS pulse occurs, the set side
of the B flip-flop causes SC-1 DATA LATE to set. The set output of the B flip-flop is applied to the clock input of
SC-1 DATA LATE if the NAND gate tied to the set output is not disabled by C 7 CH Lor RE-1 DEN 5 H. When a
7-track transport is selected, SC-1 DATA LATE sets after three SC-' WRS Lor SC-1 B RDS L pulses if the counter
has not been cleared by CB-2 MAC ACC L. Note that a 7-track transport requires only one Data Break cycle to
transfer two data characters to or from tape. The SC-l DATA LATE flip-flop is always cleared during a Space
operation since no data is transferred. SC-1 DATA LATE is also cleared when a File Mark (C FMK) is detected
during a Read operation or by CB-3 CLR STATUS L.

PIO M8323 (SC-ll
+3V1

+3V

+5V

+3V1

+3VI

E12
A

+5V

EI2
B

+3Vl
CB -1
WCOV H

E11
C

Ell
DATA
LATE
(MS)

SC -1
TEST " ..

C WRS L

SC-I
DATA
LATE L

SC -1
BRDS H
CB-l
R+RC H
C 7 CH L

RE-I DEN 5 H
CB-3 CLR STATUS L
E23

SC-2 SPACE H

CB -2 B TP3 -..-----....
}---~);.

C B -1 BRK RQST H

+5V

RE-2 CAO H

E2
INC
EMA
CB-3 CLR STATUS L
RE-I GO H

SC -I
EMA 7 INC ERR H

+3VI
RE-I EMA INC EN L
RE-2 EMA 7 H

L_______f-_-fD-W."""7l
D

sc - I

EMA 7 INC ERR H

EI3
EMA
INC
ERROR
(5S)

"SAME INVERTER
""TEST POINT NOT ON THE TOP OF CONNECTOR

SC -1
EMA 7 INC ERR L
8E-0582

Figure 9-33 Data Late and EMA Increment Error Flags

9-77

ip7c; -;;;;;;('ZB~) - - -:

PIO M8323 (SC-ll

I CB -1 READ L
I
I CB-1READI
I
COMPARE L
I
L ________ .J

+3Vl

D
RECORD
LENGTH
I NCORRECT
E26

SC-l
RECORD
LENGTH
INCORRECT L

E31
+3Vl

+3Vl
SC-2
SPACE H

CB - 1 WCOV H -------4~----_l D

D
CB·3 CLR
STATUS L

E15A

E15B

E31

S C-l

RD S • R

+ RC L -----__<1>-----01

+3V
C LRCS L

C RDS L
C LRCS L

8E-0556

Figure 9-34 Record Length Incorrect Error Detection Logic

9.13.1.4 Record Length Incorrect Logic - The SC-l RECORD LENGTH INCORRECT flip-flop (Figure 9·34) is set
when the number of data words read from the tape and the contents of the WC Register are different (record too
long or too short). As previously stated, the WC Register is loaded with the 2's complement of the number of words
to be transferred. Word Count is incremented during the data transfer. The WC Register should contain aliOs and
generate CB-1 WCOV L before the LRC character is read from tape. If C LRCS H occurs before CB-1 WCOV, gate
E33 (Figure 9-34) is enabled, and the SC-1 RECORD LENGTH INCORRECT flip-flop sets. This condition occurs if
the WC Register has been loaded with a Word Count greater than the number of words in the record (record is
short). To detect a record that is too long, a counter made up of flip-flops A and B (Figure 9-34) counts the RDS
pulses that occur after CB-1 WCOV H. If two or more C RDS L pulses occur after C8-1 WCOV and there are no C
LRCS Lor C CRCS L pulses, the SC-1 RECORD LENGTH INCORRECT flip-flop sets. This condition occurs if the
Word Count Register is loaded with a Word Count less than the number of words transferred (record is long). Note
that flip-flop A is cleared by C CRCS L or C LRCS L so that SC-1 RECORD LENGTH INCORRECT is not set
during the termination of a normal operation.
CB-1 SPACE Hand C FILE MARK L keep the SC-1 RECORD LENGTH INCORRECT flip-flop cleared during a
Space or Write File Mark operation. CB-3 CLR STATUS L clears the SC-1 RECORD LENGTH INCORRECT
flip-flop when the Status Register is cleared by a CLF instruction.
9.13.1.5 Tape Rewinding - Tape Rewinding (C RWS L) is asserted (Figure 9-36) if the selected transport is
rewinding.
9.13.1.6 End of Tape - End of Tape (C EOT) is asserted if the End of Tape reflective strip has been detected by
the TU10 (Figure 9-31). If C EOT is detected before CB-3 MTTF (JOB DONE) is set, the SC-2 ERROR flip-flop sets
and the Main Status Register must be read by the program to determine the cause of the error.
9.13.1.7 Beginning of Tape - Beginning of Tape (C BOT) is asserted when the BOT reflective strip is detected by
the TU10. If BOT is detected before CB-3 MTTF (JOB DONE) is set, the SC-2 ERROR flip-flop (Figure 9-31) sets.
The Main Status Register must be read by the program to determine the cause of the error.
9.13.1.8 Read/Compare Error - The Read/Compare operation is discussed in Paragraph 9.1.8.
9.13.1.9 Parity Error - The SC-1 PARITY ERROR flip-flop (Figure 9-35) is set if the TU10 detects any of the
following errors.
8.

C LRCE (Longitudinal Parity Error)
C CRCE (Cyclic Redundancy Check Error)
C VPE (Vertical Parity Error)

If SC-1 PARITY ERROR is set, the SC-2 ERROR flip-flop (Figure 9-31) sets when MTTF (JOB DONE) sets. SC-1
PARITY ERROR is cleared any time a File Mark is read from tape. During space operations, CB-1 SPACE H keeps
SC-1 PARITY ERROR cleared (Figure 9-35) to prevent generation of erroneous parity errors. Note that the C VPE
is cleared by the next good word read from tape and will not be seen unless it occurs as the last word read from tape.
9.13.1.10 File Mark (EOF) - The FILE MARK flip-flop (Figure 9-35) is set any time the TU10 detects a File Mark
during a Space, Read, or Read/Compare operation (Paragraph 9.1).
9.13.1.11 Select Remote-SC-l SELR L (Select Remote) (Figure 9-37) is true when the selected transport is
OFFLINE (not ready). SC-1 SEL ERROR is set if SC-1 SELR L is lost during data transfer operation.
9.13.1.12 File Protect - File Protect is a 1 when Write Lockout (C WRL L) is asserted by the TU10, indicating that
the selected transport has the Write Lockout ring removed. Transports without a Write Lockout ring will set the
ILLEGAL FUNCTION flag during SC-l PRESET time (Figure 9-32) if they are selected for a Write or Write File
Mark operation.

9-79

PIO M8323 (SC-ll

C LRCE L
E34
LRC
ERROR
(SS)
BROS H

SC-l LRC ERROR H

C VPE L

E31
C RDS L

E26
PARITY
ERROR
(MS)

E34
VPE
ERROR
(SS)

SC-l VPE H

SC-l
PARITY
ERROR L

+3Vl
CLEAR
STATUS L

r- ---,
U5

I SP;2E-~

FMK
(MS)

I SC-2

SC-1FML

SC-l CRC ERROR L

C CRCE L

C RDS

E32 ...JI
____

C
C FM

E35
CRC
ERROR
(MS)

C CRCS L

SC-l CRC ERROR H

+3Vl

BE-0549

Figure 9-35 Parity Error Flags

9.13.2 Second Status Register
The Second Status Register is read using the RFSR lOT (Figure 9-14). This lOT transfers the condition of the
Second Status Register to the AC for evaluation by the program. The logic elements in the Second Status Register
perform as follows.
9.13.2.1 EMA 7 Increment Error - RE-2 EMA 7 flip-flop (Figure 9·33) is set if the program tries to increment
from Field 7 to Field 0 (RE-1 EMA INCREMENT bit must be set). If RE·2 EMA 7 H (Figure 9-30) is applied to the
data input and RE-1 EMA INC L is asserted, the RE-2 EMA 7 flip-flop sets, which in turn sets the SC-2 ERROR flag
when C8-3 MTTF is set (Figure 9-31). Refer to Paragraph 9.13.3 for a discussion of the EMA INC logic. The Second
Status Register must be read by the program after C8-3 MTTF is set to determine the cause of the error.
9-80

9.13.2.2 Vertical Parity Error (C VPE) - The SC-l VPE flip-flop (Figure 9-35) is set during a Read or
Read/Compare operation if the TU10 Master System detects a Vertical Parity Error and asserts C VPE L. SC-l VPE
is cleared when the next good word is read from tape. If SC-l VPE is set at the end of an operation, the last word in
the record was the one that set SC-l VPE.
9.13.2.3 LRC ERROR -The SC-l LRC ERROR flip-flop (Figure 9-35) sets if the selected TU10 detects an LRC
error when the LRC character is read. The TU10 asserts C LRCE L when an error is detected and sets SC-l PARITY
ERROR and SC-l LRC ERROR.
9.13.2.4 CRC ERROR - The SC-l CRC ERROR flip-flop (Figure 9-35) sets if the TU10 detects a CRC error when
it reads the CRC character from tape. The TU10 Master System asserts C CRCE L when a CRC error is detected to
set the SC-l CRC ERROR flip-flop and the SC-l PARITY ERROR flip-flop.
9.13.3 Main and Second Status Register Multiplexer
The contents of the Main Status Register and Second Status Register (Figure 9-36) are applied to three 8235 ICs
(refer to Appendix A, Volume 1, for truth table, logic diagram, and pin locations). The 12 bits (Figures 9-9 and
9-16) from the Main Status Register are applied to the Data Bus if an RMSR instruction is executed by the program
and the 4 bits from the Second Status Register (Figures 9-10 and 9-14) are transferred to the Data Bus if an RFSR
instruction is executed by the program. Note that 8 bits of the Function Register (Figure 9-29) are also applied to
the Data Bus when the RFSR instruction is executed by the program.

PIO M8323

SC- 2 ERROR L
SC-2
REWINDING L

C RWS L

DATA 0
~

SC - 2 BOT L
SC -,
SELR

C 5ELR L

-=
sc -,

MS
0-3
E9
8235

DATA 1
DATA 2
DATA 3

(SC-2)

Y '1'

+~V

PARI TY ERR L
c---

DATA 4

SC-' FM L
~

SC-l REC L ENGTH INCORRECT L
~

MS
4-7
E21
8235

DATA 5
DATA 6
DATA 7

SC -, DATA LATE
~

(SC-2)

\' \'
+3V

SC-2 EOT L
SC- , EMA 7 INC ERROR H
CWRL L

M5
AND
S5
8-"
E37
8235

SC -, VP ERR H
OC -, RIC ERR L
SC-' CRC ERR H

DATA 8
DATA 9
DATA 10
DATA 11

S C - 2 ILLEGAL FUN L
(SC-2)

SC-' LRC ERR H

r I'I

OC-2 RMSR L

oc - 2 RFSR L

8E-0552

Figure 9-36 Main Status Register and Second Status Register Multiplexer

9-81

P/O M8323 (SC-l)
~----------------------------------------~---SC-l

STOP L

SC-l CLR STATUS L

C SELR L

+5V

C TUR L -----------------,

R36
C39
+5V
SC-l
PRESET

SC-l CNTL BSY H - - -.....
CB-2 CHG 01R L
CB-3 CHG TRANS L---t-_/

R38

C41

Q;2.5"s

+3V--------~------~

SC-l
1 SETH

I-----~C

+3V
E2
RE-l GO H

C SOWN L

SC-l STOP L

+3V

~_R~E-~I~G~O~H~_____10

CNTL
BSY
E7
CB-3 B TP4 H

rp;;- ;;3~ I
I

+5V
+5V

I
I
I

C SETHI
J2-J

I
I
I
L_____ J

SC -1
CNTL BSY H

SC-l
CNTL BSY L

CB-3 MTTF L ~..------....
+3V
~----------------------------------------~
CB-3 CLR ALL L

Figure 9-37 PRESET and SET Pulse Generation Logic

8E-0567

9.13.4 Extended Memory Address Increment Logic
The EMA bits (6, 7, and 8) in the Command Register (Figure 9-30) are used to select one of the memory fields
during a Data Break operation if bit 6 in the Function Register is a 1. When bit 6 is set, the PDP-8/E memory is
treated as continuous memory instead of 4K blocks (Table 9-12). To accomplish this the EMA bits must be
incremented when the last memory location (7777) in each field is addressed and SC-1 COUNT CA L is asserted.
The RE-1 EMA INC flip-flop (Figure 9-33) is set when the Current Address Register goes to all Os and RE-1 EMA
INC EN L is asserted (bit 6 in the Function Register is 1). The EMA bits in the Command Register are incremented
each time bit 0 in the CA Register makes a 1 to 0 transition until the EMA bits are all 1s (RE-2 EMA 7). When RE-2
EMA 7 H is asserted, the NAND gate on the output of RE-1 EMA INC is disabled. If an attempt is made to
increment beyond Field 7, the RE-1 EMA INC ERROR flip-flop is set by RE-2 EMA 7 H and the set side of RE-1
EMA INC. The R E-1 EMA I NC flip-flop is cleared at TP3 time of B R K RQST and remains cleared until R E-2 CA 0 L
makes a high-to-Iow transition at the end of a memory field.
9.13.5 Control Busy (CNTL BSY)
The SC-1 CNTL BSY flip-flop (Figure 9-37) is set by R E-1 GO and OC-2 B TP4 when bit 5 in the Function Register
is loaded with a 1. SC-1 CNTL BSY is cleared when MTTF (JOB DON E) sets at the end of an operation or by CB-3
CLR ALL.
9.13.6 PRESET and SET Pulse Generator
Figure 9-37 shows the SC-1 PRESET and SC-1 SET pulse generation logic. The 74123 ICs are monostable
multivibrators that generate a pulse on the output when the input signal makes a high-to-Iow transition. The
duration of the output pulse is determined by an external resistor and capacitor, i.e., C39 and R36.
SC-1 PRESET is a 2.5-I1S pulse (approximate time) that is triggered when the RE-1 GO bit (bit 5) in the Function
Register is set. Note that C SELR Land C TUR L must be asserted to enable the gate when starting from a standstill
condition. In a continuous mode of operation, C SDWN L allows the RE-1 GO signal to trigger the 74123 IC if CB-2
CHG DI R or CB-2 CHG TRANS are both high (false). If CB-3 CHG DI R or CB-3 CHG TRANS are asserted the
TM8-E must wait for C SELR Land C TUR L. When SC-1 PRESET returns to the clear state, E2 is clocked, and if
the SC-2 ERROR flag is not set the second 741231C is triggered. When the second 74123 IC is triggered, it outputs
a 1.0-l1s pulse (approximate time) that is applied to the selected TU10 to initiate tape motion. The E2 flip-flop is
cleared by CB-3 CLR STATUS L, the SC-1 SET pulse, or the SC-2 ERROR flag.
9.13.7 Data Late Error Check Logic
The logic shown in Figure 9-38 is used to check the Data Late Error logic (Figure 9-33). The processor timing is
stopped at TP3 time by the assertion of SC-1 NOT LAST XFER and restarted by asserting SC-1 BUS STROBE.
The 74123 ICs are monostable multivibrators that are triggered on a high-to-Iow transition of the input signal to
generate an output pulse. The duration of the output pulse is determined by an external capacitor and resistor, i.e.,
C40 and R37. When the CKDL instruction is executed by the program, OC-2IBCM L is asserted to trigger the first
74123 IC and generate a long timing pulse, which is ANDed with E1 flip-flop and applied to the OMNIBUS as SC-1
NOT LAST XFE R to stop processor timing. E 1 is cleared at TP3 time and the trailing edge of the first 74123 causes
the second 74123 IC to output a pulse. This pulse asserts SC-1 BUS STROBE L and restarts processor timing. During
the time processor timing was stopped, an attempt was made by the TM8-E to transfer data. The SC-1 DATA LATE
ERROR flip-flop (Figure 9-33) should be set, because the TM8-E would normally transfer several words in a time
period this long. If the SC-l DATA LATE ERROR flip-flop does not set, this group of logic is not working properly.

9-83

P/O M8323(SC-2)

SC-2
NOT LAST XFER L

+5V

+5V
C40

R37
C38

R35

OC-2
IBCM L
RE-1 GO H

SC-2
):)--.......-BUS STROBE L

74123
ONE
SHOT
E8

~3V

+3V

El
E19

'>------IC

CB-2
B TP3 H

8E-0558

Figure 9-38 Data Late Error Check Logic

P/O M8322 (CB-ll
CB - 1
OFFLINE L

RE-1 FRO H

CB -1
REWIND H
CB -1
READ L
RE-1 FRI H

CB -1
R + RIC H

C B-1
R+R/C+WR L

CB-1

RIC L
FR
8251
E43
(CB-I)

RE-1 FR2 H

CB -1
WRITE L

CB -1
WFM L

CB -1
WRITE H
CB -1
R+R/C+WR+WFMK L

CB-l
WR +WFM H

CB -1
R+R/C+SP FWD H

CB-1
SP FWD L

CB -1
SP REV L

CB -1
' - - - - - - - - SP FWD L

CB -1
SPACE H

8E-0568

Figure 9-39 Control Function Decoder

9-84

9.14 M8322 CONTROL MODULE
The logic elements of the M8322 Control Module are described in the following paragraphs.
9.14.1 Control Function Decoder
The Control Function Decoder (Figure 9-39) is an 8251 IC that decodes the three most significant bits (FRO-FR2)
of the F unction Register (Table 9-12) to set up the control logic for a TU 10 Transport operation.
NOTE
This decoder is identical to the output Control Function
Decoder (Paragraph 9.11.7).

The 8251 IC is a BCD-to-Decimal Decoder (refer to Volume 1, Appendix A, for truth table, logic diagram, and pin
numbers) that decodes bits FRO through FR2 and produces a low on one output line of the IC for each 3-bit
combination, i.e., 1002 causes pin 9 to be low and indicates a Write operation. The outputs of the IC are NORed to
generate one signal to represent a combination of operations, i.e., CB-1 SP REV Land CB-1 SP FWD L are NORed
to generate CB-1 SPACE H, to reduce the number of signals that are applied to elements of the control logic.
9.14.2 Data Break Request Logic
Figure 9-30 shows the logic used to make a BRK ROST during data transfer operations. The CB-l BRK RQST
flip-flop is cleared and CB-1 BRK ROST H is asserted when the following conditions exist during Read, Write, and
Read/Compare operations.

Write operation and SC-1 SET H are asserted for the first CB-l BRK ROST at the beginning of a Write
operation.

If CB-1 WRITE 1st 7 H is low and SC-1 WRS L (write strobe) is asserted during a Write operation. Refer
to Paragraph 9.14.10 for origin and discussion of these signals.

If CB-1 READ 9 or SC-2 READ 2nd 7 is asserted (Figure 9-35) during a Read operation.

If an SBRM instruction (for maintenance only) is executed by the program.

Note that the CB-1 BRK ROST flip-flop is set for only Write, Read, or Read/Compare operations, which are the
only operations requiring data transfers. CB-1 BR K ROST is set and CB-1 B R K ROST H is negated by CB-1 MAC
ACC L at TP1 time when the BRK ROST is accepted by the processor. The BRK ROST flip-flop is negated by SC-1
DATA LATE, CB-3 CLR ALL, RECORD LENGTH INCORRECT, or CB-1 WCOV if RE-l ENAB CHK CHAR is not
asserted. E24 is cleared at the beginning of each data transfer operation by SC-l PRESET H so that SC-1 R ECO RD
LENGTH INCORRECT, CB-1 WCOV, or SC-2 ERROR can be reported during the operation and stop data transfers
if these errors occur.
9.14.2.1 Word Count Overflow Logic - The CB-1 WCOV flip-flop (Figure 9-41) is set by RE-2 WCO L when bit 0
in the WC Register makes a high-to-Iow transition (Figure 9-29). The set side of CB-1 WCOV is applied to NAND
gate E32, which has as its other input RE-1 ENAB CHK CHAR L. If bit 4 in the Function Register (Table 9-12) is 0,
RE-1 ENAB CHK CHAR is high and CB-l WCOV (Figure 9-40) sets E24 flip-flop which causes CB-1 BRK ROST to
negate and stop data transfers. If bit 4 in the Function Register is a 1, RE-1 ENAB CHK CHAR l is asserted and
CB-1 WCOV does not set E24. This allows two more data breaks to transfer the CRC and the LRC character on a
Read from a 9-track transport to memory. CB-l WCOV is cleared by CB-3 ClR STATUS when a ClF instruction is
executed by the program.

9-85

P/O M8322(CB-l)
RE-1
GO H

o
CB-J OVER L
E40

RE-2
WCO H

SC-2 ERROR L

+3V

o
E24

CB-3 CLR
STATUS L

SC-J REC LENGTH INCORRECT H

CB-2
MAC ACC L-......---.....

o CB-J FJNJSHL

L-.....-~

)o----d

SC -1 PRESET H

CB-3 CLRALL L--------~------------------------------------~

CB-l READ L
CB-l RIC L -_____

SC-1SETH

)(>----10

BRK
RQST
E24

RE-l WRITE H
OC-2 SBRM L
CB-J READ 9 CH L
CB-1 READ 2nd 7 L

) O - - - - - - - - - - - - - - - - - - - - - - ( l I E37

CB-1 WRITE lsI 7 H

)-----1

+3V
8[-0546

SC-1 WRS L

Figure 9-40 Data Break Control Logic

9.14.3 Data Break Priority Logic
The priority of the TM8-E (Figure 9-41) is established by removing one of the A jumpers (AO-A5) and installing
one of the B jumpers (BO-B5); thus to establish a 0 priority (the highest priority) for the TM8-E, remove AO and
install BO. By this action all five NAND gates are disabled and the output of E9 is high, which enables E21. This
enables the set side of E26 to be applied to the CB-2 MAC 1 and CB-2 MAC 2 flip-flops and allows the TM8-E to
begin a Data Break operation at TP4, because the TM8-E has been assigned the highest priority. No other peripheral
using the Data Break I nterface can have its AD jumper removed and its BO jumper installed. Note that when NAND
gate E34 is enabled at TS4 time, DATA 0 line is low (the TM8-E BO line is in place). Since all of the other
peripherals are monitoring the Data Bus, one of the NAND gates in their priority logic is enabled and their BRK
ROST is not accepted.
As a further example, consider what happens if the TM8-E ranks third in the priority structure. This priority is
established by removing jumper A2 and installing jumper B2. Because jumpers AO and A 1 are left in place. two other
peripherals can keep the TM8-E from making a BRK ROST. If the second highest priority peripheral has a BRK
ROST at the same time as the TM8-E, its interface brings the DATA 1 line low during TS4 and NAND gate E5B is
enabled. The output of E5B causes the output of E9 to go low and disable AND gate E21. This prevents the set side
of E26 from setting CB-2 MAC 1 and CB-2 MAC 2 until the other peripheral completes its Data Break operation. As
implied, priority decreases from 0 through 11, and the TM8-E is assigned any priority between 0 and 5 by removing
the correct A jumper and installing the correct B jumper.

9-86

P/O M8322 (CB-2)

.---_---o:BO
DATA 0 -4>-----"'---<1---..,

+3V

+3V
*CB-2
MA, MS LOAD CONT. L

....._ _ _0:B1

DATA 1 -4~'--d

~_ _<lB2
DATA 2 -4H:--<f--"'"

+3V

~_ _-a:B3

CB- 2 MAC ACC L

CB-2
MAC 2 H

1-----4~--tD

MAC 2
E22

D AT A 3 --4~i--<1-

*C B- 2
MSIR DISABLE L

0
+3V

DATA 4 ~t---i----d
*CB - 2
BRK CYCLE L

D AT A 5 --<~+--d
*CB- 2
BREAK IN PROG L

DATA6 P
,
• B6
I----b
6-.---vv..- + 5 V
CB-3 CLR ALL L - - - - - - - . - - - - - + - l - - - - - - - - - - - - * - - - - - - - . - I
*INT STROBE H

*CB - 2
BREAK DATA CO NT L
CB-l READ L

E26
CB-l
BRK RQST H - - - - - - 1 D

*CB-2
CPMA DISABLE

+3V

*OMNIBUS SIGNALS
BE-0561

Figure 9-41

Priority and Processor Control Logic

P/O M8322(CB-3)

+5V
+3V

CB-l WCOV H
OC-2 LDBR L

CB- 1 REW1ND H

D
El0

CB-l OFFLINE L
CB -3 SEL ERROR H

SC-l SETH

CB-3 CLR STATUS L
SC-2 REWINDING L

SC-l FM L
CB-l WCOV L
RE-l IEEF H

+3V

CB-l ERROR H
SC-2 EaT L
RE-l
IEMF H

PRESET H

CLR

CB-3
11------1 E34 b--~-INT RQST L
MTTF
(JOB
DONE)
SC-2 B LRCS L C E3 0 CB-3 MTTF L

~_ _-ID

CB-l READ
CB-l READ/COMPARE

CB-l WFMK
CB-3 CLEAR STATUS L
8E-0553

Figure 9-42

MTTF (JOB DONE Flag) and Interrupt Request Logic

9.14.4 Processor Control Logic
The logic shown in Figure 9-41 is used to control the PDP-8/E processor during a Single Cycle Data Break operation.
If E2l is enabled by the priority logic and the set side of E26, CB-2 MAC 1 and CB-2 MAC 2 are set to assert the
OMNIBUS signals (the OMNIBUS signals are explained in Chapter 9 of the PDP-8IE & PDP-81M Small Computer
Handbook) and take control of the processor for a Single Cycle Data Break operation. Note that MA, MS is not
asserted until TPl time. CB-2 BREAK DATA CONT L, which controls direction of data flow on the Data Bus, is
controlled by READ L. During a Read operation, CB-l READ L is asserted and data is transferred from tape to
memory. During Write and Read/Compare operations, CB-l READ L is high to transfer data from memory to the
TM8-E. CB-2 MAC 1 and CB-2 MAC 2 are cleared by the output of AND gate E21 at TP4 time if B R K ROST is
removed. CB-l BRK ROST (Figure 9-40) is cleared by CB-2 MAC ACC L at the same time CB-2 MAC 1 and CB-2
MAC 2 are set to start a Single Cycle Data Break. The TM8-E continues to make break requests and to transfer data
to or from memory until the WC Register reads all Os (WCOV).
9.14.5 MTTF (JOB DONE) Logic
MTTF (JOB DONE flag shown in Figure 9-42) is set by one of the following conditions to indicate that a specified
function is complete or cannot be performed.

C LRCS (LRC character read from tape at the end of a record) during a Read, Read/Compare, Write, or
Write File Mark operation.

The C LRCS is read from tape during a Space operation.

If File Mark, EOT, or WCOV are encountered during a Space operation.

The selected transport is given a command to rewind and C RWS is asserted by the selected transport to
indicate Rewind has started.

The selected transport is given the CB-l OFFLINE command and C SEL ERR L is asserted by the
se lected TU 1 O.

If lOT LDBR is executed by the program and CB-l WCOV L is asserted.

9.14.6 Interrupt Logic
The Interrupt logic (F igure 9-42) asserts INT ROST L, which is serviced by the processor (i.e., perform a flag check
routine) when one of the following conditions exist.

Bit 6 in the Command Register (Interrupt Enable on SC-2 ERROR flag) is a 1 and the SC-2 ERROR flag
is set (Figure 9-32). Note that the SC-2 ERROR flag does not set until after CB-3 MTTF is set unless
CB-3 SEL ERR or SC-2ILLEGAL FUN is set at the beginning of an operation.

Bit 5 in the Command Register (Interrupt Enable on JOB DONE flag) is a 1 and the CB-3 MTTF flag is
set.

9.14.7 Change Transport Control Logic
Figure 9-43 shows the logic used to generate the CB-3 CHG TRANS L signal when a new transport is selected by the
program. If an LCMR instruction is executed by the program, flip-flop E3 clears (Figure 9-43) and enables NAND
gate E7. At TP4 time, the output of E7 supplies a clock input to E8 and if any of the inputs (RE-l SEL O-RE-l
SEL 2 and RE-l B SEL O-RE-l B SEL 2) to the E4 Exclusive-OR gates are different, E8 zeroes and asserts CB-3
CHG TRANS L. The output of E7 also clocks the E3 flip-flop, causing it to set and disable E7. If C TUR Land C
SOWN L are asserted or SEL REM L is negated, NAND gate Ell is enabled at TP4 time. LBCM L is asserted to load
the Buffered Command Register with bits RE-l SEL 0 through RE-l SEL 2 from the Command Register (Figure
9-30). If CB-3 CHG TRANS is set and C RWS L is asserted, RE-l LBCM L is asserted to load the BCM (Figure 9-43).
CB-3 CLR STATUS resets the CB-3 CHG TRANS flip-flop. The Buffered Command Register is also loaded with
RE-l SEL 0 through RE-l SEL 2 when CB-3 CLR ALL is asserted (CLF instruction executed by the program).
9-89

P/O M8322(CB-3)

+3V

C
+5V

OC - 2
LCMR L

RE-1 SEL 0 H - - \
RE-1 BSEL 0 H~

CB-3B
INITIALIZE L
CB-2CHG
DIR L

+3VI

RE-1 SEL 2 H=J.

E8
CHG
TRANS

E12
C

E18

CB-3 CHG
CLR L

CHG TRANS L

RE-1 B 5EL 2 H

tlO
I

M832,:J
(CB-l)
OC-2
LBCM L

CB -3 CLR
STATUSL

5C-2 REWINDING L - - - - - {
CB-3 B TP4 H

CB-3
CLR
ALL
L

SC-2 TUR L - - - Q .
5C-2 SDWN L--~
5C-1

5ELR H - - - - - - - - - '

8£-0563

Figure 9-43 Change Transport and Buffered Command Register Control Logic

9.14.8 Change Direction Control Logic
Figure 9-44 shows the logic used to detect a change in direction of tape movement. E35 flip-flop is cleared by SC-1
SET H at the beginning of all operations except Space Reverse, Rewind, or Offline. This applies a high to the input
of E4, which is the same as the high out of E 19. E4 has a high output if both inputs are equal and a low output if
the inputs are unequal. If CB-1 SP REV L, CB-1 REWIND L, or CB-1 OFFLINE L are asserted, the output of E19
goes low and the output of E4 (CB-3 CHG 01 R L) is asserted. CB-3 CHG DI R L forces the control to wait for C
TUR Land C SELR L before starting a new operation.
9.14.9 Write Data Ready Logic
Figure 9-45 shows the Write Data Ready logic. C WDR H is applied to the selected transport when the TM8-E is
ready to start a Write operation. SC-1 SET Hand CB-1 WRITE H enable NAND gate E32 to set flip·flops E23A and
E23B. This enables E27 A if a 7-track transport is selected and E27B if a 9-track transport is selected to assert CB-1
WDR H. If a 9-track transport is selected, E23A is cleared when CB-1 WCOV L is asserted, which in turn disables
NAND gate E27B and CB-1 WDR H goes low. If a 7-track transport is selected, E23A is cleared by the first SC-1
WRS L pulse after CB-1 WCOV L is asserted and E23B is cleared by the second SC-1 WRS L pulse. This operation
disables NAND gate E27A and C WDR H goes low. SC-1 DATA LATE Land SC-2 ERROR L clear both E23
flip·flops if these errors occur during a Write operation. If a CLF instruction is executed by the program, CB-3 CLR
STATUS sets E23A and E238 to cause CB-1 WDR H to go low, which terminates a Write operation.

9-90

PIO M8322(CB-2)

+3V

CB-l SP REV L
CB - 1 REWIND L
CB - 1 OFFLINE L

~~~~~IRL

SC -1

SET H

8E-0554

CB-3 CHG CLEAR L

Figure 9-44 Change Direction Detection Logic

P/O M8322 (CB-l)
CB- 3 CLR STATUS L
SC-l DATA LATE L
SC - 2 ERROR L ---.,~.-'

rpiOM8321 Wc-2'l- -1

CB-IWRSL

+5V

CB-I wcov L - - - - - - - 1

I
I

+5V

SC - 1 SET H
CB-l WRITE H

CB-I 7 CHANNEL
+ DEN5 H

E32

I
I
I
~
I
~J2-LL I
+5V

L _ _ _ _ _ _ ...J

SC-17CHANNELL _ _ _ _ _ _ _ _ _ _ _ _ _---l
+ DEN 5 L

8E-0560

Figure 9-45 Write Data Ready Logic

9.14.10 Read and Write Control Logic
The logic shown in Figure 9-46 is used to generate control signals during Read and Write operations. Table 9-18
shows the levels of the control signals and the logic used to assert each signal for each Read and Write operation on
7- and 9-track transports. E40 is used only if a 7-track transport is selected. E40 is clocked on the rising edge of the
SC-1 RDS or SC-1 WRS pulses.
The Read and Write control signals are applied to the CB-1 BRK ROST control logic to determine when a BRK
ROST is to be made by the TM8-E (Figure 9-40). CB-1 BRK ROST is clocked on the falling edge of the SC-1 RDS or
SC-1 WRS pulses. Refer to Drawing D-TD-TM8-E-1, sheets 1 through 8, for the timing diagrams that illustrate these
operations.
9.14.11

Data Multiplexer Control Logic

Figure 9-47 shows the Data Multiplexer Control logic used to select data read from tape, from memory, or from the
AC as input to the Data Register (Figure 9-25). Table 9-17 shows the level of CB-2 DB MPXA Hand CB-2 DB MPXB
H for all TM8-E operations.

9-91

Table 9-18
Read and Write Control logic Signal levels
Operation

Read a
Character
From 9-Track
Transport
Read 1st 7
Character
From 7-Track
Transport
Read 2nd 7
Character
From 7-Track
Transport
Write
Character on
a 9-Track
Transport
Write 1st
Character
on 7-Track
Transport
Write 2nd
Character
on 7-Track
Transport

SC-1
RDS L

SC-l
WRSL

C8-1
READ 9 L

C8-1 READ
1st 7 L

C8-1 READ
2nd 7 L

C8-1
WRITE 9 L

C8-1
WRITE 1st 7 L

C8-1 WRITE
2nd 7 L

Enabled
Gate

low
pulse

high
level

low
pulse

high
level

E32

low
pulse

high
level

low
pulse

high
level

E37A

Set to 1
state on rising
edge of C RDS

Condition
of E40

low
pulse

high
level

low
pulse

high
level

E37B

Reset to
state on the
rising edge
of RDS

high
level

low
pulse

high
level

low
pulse

high
level

E41C

E41A

Set to 1
state on
rising edge
of C WRS

E41B

Reset to
state on
rising edge
of C WRS

high
level

low
pulse

high
level

low
pulse

high
level

low
pulse

high
level

*Condition of E40 does not matter on 9-track transports.

high
level

low
level

high
level

P/O M8322(CB-l)
CB-l
WRITE H

CB- 3 CLR STATUS
CB-l
RD 1st 7 L

SC-l WRS L

01-._--1--+__.--1

CB-l WR 1st 7 H

E40

E39

CB -1
RD 2nd 7 L

CB-l WR 2nd 7 H
CB -1
RD 9 L

+3V

CB-17
CH + DEN 5 H

E39

CB -1 WR 9 H

SC-17CH
+ DEN 5 L
SE-0555

Figure 9-46 Read and Write Control Logic

CB - 1 WRITE L - - - - ,

P/O M8322(CB-2)

CB-l 7 CHANNEL + DEN 5 L

CB-2
MPXA H

E1B
r--~C

CB -3 CLR ALL L
+3V
OC -2 LDBR L
CB-l
WRITE L

~/;-M;;-2~~ -

+3V

--,

CB-1R+RCH
+3 v
SC-1 SET H ----. __ ~

CB-2
MPXB H

}-r-+-------I C

EIB
D

L _____ ...J
Figure 9-47

Data Multiplexer Control Logic

9.14.12 POWER OK Logic
The POWER OK logic shown in Figure 9-48 is used to assert CB-3 CLR ALL if PDP·8/E power falls below a certain
level. If PWR OK H goes low, NAND gate E16 is enabled to assert CB-3 CLR ALL. This initializes all TM8-E logic
and the selected transport.

9-93

Pia M8322(CB-3)
*POWER

IP;O' M8323(SC-2i' ..,

I SC-2 BOT L
I
I SP R€~-~ ~L-~
L ______ .J

+5V
CB-3 B INIT L

SC-2 SP REV -BOT L

*INIT H -->.~-...

r---------,

I
I
I

CB-3 CLR ALL L

E15

OC-2 CLF L

+5V

>-----4~ C INIT H

L!/~ ~8~ ~a~::2.

SC-1
TUR L

CB-3
CLR
STATUS L

SC-l PRESET H

J2-FF

I
I
I
I
I
I
I

___ .J

SC -1
SELR H

E12

CB-3 SEL ERR L

*OMNIBUS SIGNALS
+3V
BE-0566

Figure 9-48 Initialize and Clear Logic

9.14.13 Initialize Logic
INIT H (Figure 9-48) is asserted when the PDP-8/E is powered up or by depressing the CLEAR key on the PDP-8/E
power control console. Note that INIT H is not the same signal as C INIT H; C INIT H is used to clear all logic on
the selected transport when the following conditions exist.

INIT H is asserted by the processor.

If the tape unit is ready (C TUR l true) when a ClF instruction is executed by the program (CB-3 ClR
All is asserted).

If a Space Reverse operation is attempted and transport is at BOT.

If the ClT instruction is executed to assert CB-3 ClR All.
SECTION 5 MAINTENANCE

Recommended preventive maintenance should be scheduled on a regular basis to maintain the performance and
reliability of the DECmagtape system. Preventive maintenance schedules are included in the TU10 DECmagtape
Maintenance Manual, Chapter 5, Paragraph 5.1.1. TM8-E DECmagtape diagnostics (Paragraph 9.3) are provided to
test and troubleshoot the TMS-E controller and the TU 10 DECmagtape Transports. Preventive maintenance on the
TMS-E modules consists of running the TMS-E diagnostics periodically to check system operation.
SECTION 6 SPARE PARTS
Table 9-19 lists the recommended spare parts for the TMS-E.
SECTION 7 IC DESCRIPTIONS
Only those ICs not included in Appendix A of Volume 1 are discussed in this section.

9-95

Table 9·19
TM8·E Spare Parts
DEC Part Number

Description

10·00007
10·00042
10·00067
10·01610
12·09941
13·00204
13·00229
13·00275
13·00286
13·00293
13·00317
13·00443
13·00498
13·00534
13·01316
13·01401
13·01420
15·10015
19·05547
19·05575
19·05576
19·05578
19·05570
19·09004
19·09055
19·09056
19·09057
19·09058
19·09267
19·09485
19·09486
19·09584
19·09667
19·09686
19·09704
19·09705
19·09712
19·09928
19·09929
19·09935
19·09937
19·09955
19·10035
19·10435
19·10651
19·10652

Capacitor, 15 pF, 100V
Capacitor, 1000 pF, 100V
Capacitor, 618 pF, 35V
Capacitor, 0.01 JlF, 100V
Connector, 40 pins
Resistor, 47n, '4W
Resistor, lOOn, '4W
Resistor, 220n, '4W
Resistor, 270n, '4W
Resistor, 330n, '4W
Resistor, 470n, '4W
Resistor, 417n, '4W
Resistor, 18 Kn, '4W
Resistor, 100 Kn, '4W
Resistor, 8.2 Kn, '4W
Resistor, 750n, '4W
Resistor, 27n, '4W
IC, DEC 4008
IC, DEC 7474
IC, DEC 7400
IC, DEC 7410
IC, DEC 7430
IC, DEC 7401
IC, DEC 7402
IC, DEC 7495
IC, DEC 74HOO
IC, DEC 74Hl0
IC, DEC 74H2l
IC, DEC 74H 11
IC, DEC 380
IC, DEC 384
IC, DEC 8251
IC, DEC 74H74
IC, DEC 7404
IC, DEC 314
IC, DEC 8881
IC, DEC 8242
IC, DEC 7416
IC, DEC 7414
IC, DEC 8235
IC, DEC 74153
IC, DEC 7412
IC, DEC 74197
IC, DEC 74123
IC, DEC 74175
IC, DEC 74174

9·96

Quantity

2
2

2
2
3
3

3
2
2
2
2
1
2
2

1
1
3
3
2
1
2
3

2
2

DEC 741531C

The DEC 74153 IC is a Dual 4-Line to 1-Line Data Selector/Multiplexer (see below for truth table, logic diagram,
and pin numbers). The IC can be used in one of two modes, a 4-line to 1-line multiplexer or a parallel-to-serial
converter. A strobe enable signal line is provided to select each of the input lines as an output. In the TM8-E, the
strobe lines are tied together to allow the selection of signals from the MD lines, Data Bus, or data read from the
TU 1 0 Transport.

CONTROL INPUT

STROBE

OUTPUT

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

DON'T CARE
TRUTH TABLE

(EACH HALF)

Vee

PIN LOCATOR
(TOP VIEW OF IC)
8E-0138

DEC 74153 IC (Sheet 1)

9-97

CONTROL
INPUTS

F
OUTPUTS

2B
DATA
INPUTS

20
2G

STROBE - - - - - - - 0

LOGIC DIAGRAM

DEC 74153 IC (Sheet 2)

9-98

DEC 741741C
The 74174 IC contains six flip-flops with single rail output with a buffered clock and direct clear input. Each
flip-flop has an individual data input. The truth table and logic diagram are shown below.

Input

Outputs

tn+1

D
H
L

H
L

L
H

TRUTH TABL E
INPUT OU TPUTS
In + 1
In

Q
H L
L
L
H
In = Bil lime before
clock pul se.
In+1 =Bil lime after
clock pu Ise.
D
H

A (3)

QA ~

DA
J-

CLOCK
CLEAR

j
B (4)

QB ~

-.r CLOCK

CLEAR

l'
C (6)

QC ~

CLOCK
CLEAR

Y
QD ~

(11)

DO
-.r

CLOCK
CLEAR

~
E (13)

QE ~

CLOCK
CLEAR

Y
F
CLOCK

CLEAR

(14)

X>
(1)

""
.~

QF ~

CLOCK
CLEAR

Pin (16)= VCC. Pin (8)= GND

IHI12

DEC 741741C

9-99

DEC 74175 IC
The 74175 IC contains four flip-flops with double rail outputs with a buffered clock and direct clear input. Each
flip-flop has an individual input. The truth table and logic diagram are shown below.

TRUTH TABLE
INPUT
tn

OUTPUTS
tn +1

H
L

L
H

tn = Bit time before
clock pulse.
tn+1 = Bit time after
clock pulse.

r--~(lCLK QA
CLEAR

(7)

(5)

o---1t---+--f°B

.--t----l::lCLK OB
CLEAR

(12)

o---1I---+--f0 C

(10)

t--t----4(lCLK QC
CLEAR

",(_13"';')-+--~'----l
~

(15)

CLOCK
~--""-+--ClCLK

QO
CLEAR

CLEA R o--C.--a

Pin (16)= Vce. Pin (8)=GNO
11- rrr3

DEC 74175 IC

9-100

DEC 741971C
The DEC 74197 IC is a pre-settable binary counter that can also be used as a latch. The IC consists of four
dc-coupled master-slave flip-flops connected to provide a divide-by-2 counter and a divide-by-8 counter. The logic
diagram, a truth table, and a pin locator are shown in the 74153 description.
The 74197 can be used in anyone of three modes, viz; the divide-by-2/divide-by-8 mode, requiring no external
interconnection or IC pins, the latch mode, and the binary counter mode. If the first listed mode is used, an input at
pin 8 is divided by 2 by flip-flop A and the result is taken from pin 5; an input at pin 6 is divided by 8 by flip-flops
B, C, and D and the result is taken from pin 12. Transfer of information to the outputs takes place on the
negative-going (trailing) edge of the clock pulse.
To use the latch mode, enter data at the four data inputs (pins 4, la, 3, and 11) and enter a strobe pulse at pin 1.
The output pins, 5, 9, 2, and 12, respectively, will follow the inputs when pin 1 is low, but will remain unchanged
when pin 1 is high and the clock inputs are inactive.

Count
Clock 1 Input

a
1
2
3
4
5

6
7
8
9
10
11
12
13
14
15

0
0

a
a
a
a
a
a
1
1
1
1
1
1
1
1

Output
OC OB

a
a
a
a

a
a

1
1
1
1

a
a

1
1

a
a
a
a

a
a

Vee

CLEAR

DATA C

DATA A

DATA D

DATA 8

CLOCK 2

GND

CLOCK 1

1
1
1
1

1
1

a
a

1
1

1
1
1
1

COUNT/LOAD

1
1

BE-0372

a
1

DEC 74197 IC (Sheet 1 of 2)

9-101

DATA A - - - - - - - - - - - 1

COU NT ILOAD ----<1\-......
CLEAR --+----'01
t----QA

DATA S - - - - - - - - + - + - - l _ - - "

t---.--QS

DATA C--------+--+--I_~

I--__-QC

DATA D--------+----l_~

I----QD

DEC 74197 IC (Sheet 2 of 2)

9-102

CHAPTER 10
TAS-E CASSETTE SYSTEM INTERFACE

SECTION 1 INTRODUCTION

The TAS-E interfaces the PDP-S/E, M, or F Computers and the TU60 Cassette Tape Transport System (2 drives)
(F igure 10-1). To perform this function, the T AS-E:
a.

Decodes lOT instructions to generate control signals and transfer data.

Transmits control signals to the TU60 and receives signals from the TU60 that indicate TU60 status.

Selects (in conjunction with the TU60) one of the TU60 drives to perform an operation (i.e., read or
write).

Provides flags to indicate ERRORS and generates SKIP or INTERRUPT REQUEST.

Buffers the input/output data.

Provides TU60 and TAS-E status information to the computer.

lOT INSTRUCTIONS
0
M
N
I
B
U
S

DATA(WRITE)
DATA (READ)
TA8-E
INTERFACE
(M8331)

DATA (AC4-AC11)

CONTROLS

TU60
CASSETTE
DRIVE
(DUAL DRIVE)

STATUS

8E-0663

Figure 10·1

TAS-E Interface and TU60 Cassette Drive, Block Diagram

10-1

10.1

PHYSICAL DESCRIPTION

The TAS-E consists of the MS331 Interface Module that is inserted into the OMNIBUS to provide an interface for
the TU60. The TAS-E and TU60 can be ordered in two rack mounted configurations. These configurations are
outlined below:
•

TAS-AA -

MS331 Module, TU60 AA, and 2 BCOSR cables (rack mounted), 115 Vac

•

TAS-AB -

MS331 Module, TU60 AB, and 2 BCOSR cables (rack mounted), 230 Vac

The basic system consists of one TU60 Cassette Tape Transport System (2 drives) and one MS331 Interface Module
with interface cables. Jumpers on the MS331 module permit the selection of lOT device codes 70 through 77. These
device codes allow the user to install a maximum of eight TAS-E modules on one processor and to use eight dual
drive cassettes (16 drives).
10.2 POWER REQUIREMENTS
The MS331 module requires +5V at 2.4A. This logic power is supplied by the processor power when the MS331
module is inserted into the OMN IBUS. Power is not supplied to the TU60 by the T AS-E or vice versa.
10.3 TAPE FORMAT
The tape format (Figure 10-2) is S-bit serial words with programmable block length (Figure 10-3). Block length is
limited only by the length of the tape, and up to 92K words can be recorded on one cassette cartridge. Each block
of data is preceded by a PREGAP and PREAMBLE to identify the data block. A Cyclic Redundancy Check (CRC)
character is recorded at the end of the data block and is followed by a POST GAP. Gaps are erased areas on the tape
that are used to separate blocks of data and to provide a space to start and stop the tape drive.
The CRC character is computed by the TU60 hardware during a write operation and written at the end of a block of
data. The CRC character computed during a write operation is compared with the CRC character computed during
read operations to determine if data bits were picked up or lost. The CRC character is generated and checked by the
TU60 electronics, and if a CRC ERROR occurs, the CRC BLOCK ERROR flag is set by a signal from the TU60. The
TU60 Maintenance Manual contains a complete discussion of CRC character generation and error checking
operations.
The PREAMBLE is a word generated by the TU60 to identify a block of data and to provide sync pulses to read and
write data.

TAPE
rSPLICE
0:
W

«
w

..J

w
..J
U

0«
LOAO POI NT GAP

..J

::.
«

'" '"

DATA

r--"----,

,.---J--...

0:
0-

DATA

a::

~
0-

« «

W
..J

'" '" ::.«'"

8 8 8 8 eRe f- w
(f)

0:
0-

O-~

8 8 8 8 8 8 eRe f-

(f)

a::

FI LE
GAP

D..

Figure 10-2 Typical TU60 Format

10-2

::.
«
a::

«
8 8 8 eRe f-

BOTI~·_________________r-___D_A__TAD:~::~~________________________~·1

..J

'"w '"w

0::
D..

TAPE
\SPLICE

'"
(f)

FIL E
GAP

0:
W

W
..J

W
..J
U

IEOT

PEAK CAPACITY

--- --90K

600

--- --PEAK RATE
500

75K

400

60K

AVERAGE
RATE
(BYTES/SEC)

CAPACITY
(BYTES)
300

45K

200

30K

100

15K

128
BLOCK LENGTH (BYTES/BLOCK)

256

92K

CP-0377

Figure 10-3 TU60 Capacity and Data Rate vs Block Length

10.4 DOCUMENTATION

Reference documents are required to program and maintain the T AS-E as follows:
a.

PDP-8/E, PDP-S/F, and PDP-S/M Small Computer Handbook - DEC, 1973

PDP-S/E, PDP-S/F, and PDP-S/M Maintenance Manual Volume 1, DEC-SE-HR1B-D

DEC Engineering Drawing, TAS-E Cassette System Interface, 8-DD-TAS-E-0-0

TAS-E Diagnostic, MAINDEC-OS-DHTAA-A

TAS-E Data Reliability Test, MAINDEC-OS-DHTA8-A

TU60 Cassette Tape Transport Maintenance Manual, DEC-00-TU60-DA

TU60 Engineering Drawings, 8-DD-TU60-0-0

10-3

SECTION 2 INSTALLATION AND ACCEPTANCE TEST

The TAS-E Cassette System Interface is installed on site by DEC Field Service personnel. The customer should not
attempt to unpack, inspect, checkout, or service the equipment.
10.5 INSTALLATION
Install the TAS-E as follows:
1.

Ensure PDP-S/E power is off.

Ensure the correct device code select jumpers are installed (see Table 10-1 and refer to drawing
MS331-0-1l.

Connect the BCOSR cable to the MS331 module as shown in Figure 10-4.

Insert the MS331 module into the OMNIBUS. Refer to Table 2-3 in Volume 1 of the PDP-8/E
Maintenance Manual for module installation priority and placement on the OMNIBUS.

Unpack and install the TU60 Cassette Drives as specified in Chapter 2 of the TU60 Maintenance Manual.

Connect the other end of the cable to the TU60 Cassette Drive as shown in Figure 10-4.
Table 10·1
Device Code Selection Jumper Installation
Install Jumpers

Device Code
70
71
72
73
74
75
76

X
X
X
X

X
X

X
X
X
X

X
X

X
X
X
X

X
X

X designates jumper to be installed.

M7760

TU60
BC08R CABLES

M8331

COMPUTER

PIN NUMBERS ON THE CONNECTOR
AND THE CONNECTOR NAME
ARE UPSIDE DOWN WHEN THE
CABLES ARE INSTALLED
CORRECTLY

Jl L . h - - + - - - '
J2L.h_ _;.-._ _......

RACK MOUNT CABLING
BE-06GS

Figure 10-4 TAS-E and TU60 Cabling
10-4

10.6 ACCEPTANCE TEST
To test the TA8·E, run the following diagnostics in the order shown. The instructions for running the diagnostics are
on the document accompanying the binary tape.
a.

TA8·E Diagnostic, MAINDEC-08-DHTAA-A

TA8-E Data Reliability Test, MAINDEC-08-DHTAB-A

Refer to the Field I nstallation and Acceptance Test procedure in the T A8-E print set for acceptance test
requirements.
10.7 TAS-E INTERFACE
The rack-mounted system is provided with two BC08R cables to connect the TAS-E on the OMNIBUS to the TU60
Cassette Drives. The signals on these cables are shown in Table 10-2, and a complete description of each signal is
provided in Paragraph 10.10.

Table 10-2
TAS-E Input and Output Signals
MS331 , J1
Pin Number

MS331, J2
Pin Number

TAS-E Input
or Output

Signal

R/W 05 L

Input

DRIVE EMPTY L

Output

BACK BLOCK GAP L

Output

WRITE MODE L

Input

REWIND L

Output

BACK FILE GAP L

Output

REWIND CMD L

Input

WRITE LOCK OUT L

R/W 01 L

R/W 02 L

R/W 03 L

R/W 04 L

Output

READ/WRITE CRC L

10-5

Table 10-2 (Cont)
TAS-E Input and Output Signals
MS331, J1
Pin Number

MS331. J2
Pin Number

TAS-E Input
or Output

Output

READ/WRITE FILE
GAP L

Output

START L

Output

INIT L

Output

TRANSFER L

Input

EOF L (End of FILE)

Input

EOT/BOT L (End of
Tape or Beginning of
Tape)

Input

TIME ERROR

R/W 06 L

R/W 08 L

R/W 07 L

CRC BLK ERR L

Signal

*R/W 01 through R/W 08 are bidirectional lines used to transfer data in both directions.
NOTE
Pins not listed are tied to ground.

SECTION 3 FUNCTIONAL DESCRIPTION
This section provides a functional description of the major groups of logic, a list of TA8-E instructions, and a
description of each signal transmitted and received by the TA8-E_
10.S FUNCTIONAL DESCRIPTION
The TA8-E logic is divided into functional areas for descriptive purposes_ Figure 10-5 is useful in understanding
signal flow and the interrelationship of groups of logic_ Section 4 provides detailed discussion of each group of logic_
10_S_1

lOT Decoder

There are eight sets of I/O device codes that determine which of eight possible TA8-E modules is being addressed_
The decoding is done by jumpers connected to MDB, MD7, and MD8 (Table 10-1). When the correct code for the
TA8-E goes to the I/O decoder and I/O PAUSE is present, a SELECT H signal is generated to allow the decoding of
MD09-MD11 and to generate an INTERNAL I/O L. I/O PAUSE is present anytime an lOT instruction is executed
by the program_ INTERNAL I/O L prevents the processor from executing other lOTs while this instruction is
executed. MD09-MD11 are decoded to control data transfers and to generate control signals that enable the TA8-E
to load the Status A Register_ The Status A Register generates control signals that are transmitted to the TUBO_
The lOT decoder also controls the CO and C1 lines, which control the direction of data transfers between the AC
and the T AS-E registers_
10-6

.0/

TU60
(DRIVE A AND B)

INT RQST L
SKIP L
INT ENABLE
KCLR (67XO)

ERROR

KSDR (67X1)

END OF FILE

KSEN (67X2)

MD03-MD11

SKIP
LOGIC

KSBF (67X3)
lOT DECODER

KGOA(67X6)

INT I/O L
CO AND C1

CLINE
CONTROL
LOGIC

DATA FLAG

READ STATUS A

•

NOT LAST TRANSFER
BUS STROBE

TRANSFER
CONTROL

...

TRANSFER

IOT6
READ

READ/WRITE
BUFFER
REGISTER

RWO-RW08

ENABLE INTERRUPT
DRIVE SELECT

~-+

f---

TRANSFER
REQUEST

READ---

AC4-AC11

DATA FLAG
READY

KLSA (67X4)

KRSB(67X7l

EOT/BOT

KSAF(67 X5)

I/O PAUSE L

0
M
N
I
B
U
S

r--

f-INTERRUPT
LOGIC

STATUS
REGISTER A

SELECT ENABLE

FRO-FR2

READ
REWIND
WRITE
FUNCTION
REGISTER

BACK SPACE TO FILE GAP
WRITE GAP
BACK SPACE BLOCK GAP
READ/WRITE CRC CHARACTER
SPACE FORWARD FILE GAP

DRIVE EMPTY
READY

L-..-.
READ STATUS B

STATUS
REGISTER B

END OF FILE
EOT/BOT
CRC/BLOCK ERROR
TIME ERROR
8E-Q677

Figure 10-5 TAS-E Block Diagram

10.8.2 Status A Register
The Status A Register (Figure 10-6) is loaded from AC04-AC11 by the KLSA instruction and used to enable
interrupts, select one of two drives (drive A or B), enable the TU60 transmitters and receivers, and provide signals
FRO-FR2 to the Function Register. Signals FRO-FR2 are decoded to select one of the TU60 functions. The KLSA
instruction also transfers the complement of the Status A Register to the AC during maintenance operations.

ENABLE INTERRUPTS
NOT USED
NOT USED

FUNCTION REGISTER
} (SEE TABLE 10-3)

DRIVE AlB O=A 1=B
SELECT ENABLE
8E-0666

Figure 10-6 Contents of the Status A Register

READY FLAG
WRITE LOCK OUT
REWIND
DRIVE EMPTY
END OF FI LE FLAG
EOT I BOT
TI M I NG ERROR

CRCI BLOCK ERROR
8E-0665

Figure 10-7 Contents of the Status B Register

10-8

10.8.3 Function Register
The Function Register (Table 10-4) decodes FRO-FR2 and provides control signals to the TU60. These control
signals determine the operation the TU60 will perform, i.e., read or write.
10.8.4 Status B Register
The Status B Register contains the current status of TU60 (Figure 10-7), which can be transferred to the AC for
evaluation by the program. The KRSB instruction transfers the contents of this register to AC4-AC11.
10.8.5 Read/Write Buffer Register
-

The Read/Write Buffer Register provides temporary storage of data to be written on the tape or read from the tape.
Without this register the TAS-E would have to transfer data to the processor within 230 /lS in order to prevent a
TIME ERROR. Using the Read/Write Buffer Register, 1.S4 ms is allowed between transfers, or the time required by
the TU60 to read or write an S-bit byte.
10.8.6 Data Flag
The Data flag is set for every byte read or written including the two CRC bytes. The Data flag is cleared by the
KGOA instruction. Data flags normally occur once every 1.S4 ms (Paragraph 10.11.1.10).
10.9 INSTRUCTION AND STATUS BITS
The instructions used to program the TAS-E are shown in Table 10-3. The status bits associated with these
instructions are explained in Tables 10-4 and 10-5.
The KLSA instruction (Table 10-3) has two functions: 1) to transfer data from AC4-AC11 to the Status A
Register and 2) to clear the AC and transfer the complement of the Status A Register to the AC. To accomplish
this, the C lines, CO and C1, must be switched during execution of the instruction. Processor timing must be stopped
during TS3 by NOT LAST TRANSFER L to allow time to switch the C lines. After the C lines are switched,
processor timing is restarted by BUS STROBE and the complement of the Status A Register is read into the AC.
10.9.1

Programming Sequence

Figure 10-S is a flow diagram of TAS-E operations showing the TAS-E programming and operation sequences.
10.10 INPUT AND OUTPUT INTERFACE SIGNALS
The input and output signals are O.OV (low) when true and +3V (high) when false. Note that the following signals
must be present at the TU60 during an entire operation.
a.
b.
c.
d.
e.

SELECT ENABLE L
DRIVE B L
BACK BLOCK GAP L
BACK FI LE GAP L
READ/WRITE FILE GAP L

REWIND L, READ/WRITE CRC L, TRANSFER C, and WRITE MODEL signals are transmitted to the TU60 and
stored in the TU60 until an operation is completed.

10·9

START AN OPERATION
READ

OR SelECT A NEW OP
ERATION AFTER THE

IF KSBF OR INT ROST IF
INT ENABLE

TU60 COMPLETES THE
PREVIOUS OPERATION

KGOA
CLEAR R/W
BUFFER AND

INITIALIZE

ISSUE START l
IF TAPE IS READY

THE SYSTEM
LOAD STATUS A (SEE
TABLE 10·4)
(1) SELECT DRIVE

(2) SELECT ENABLE
(3) SELECT FUNCTION

WRITE
TRANSFER THE WORD
IN THE AC TO MEMORY

KGOA
(1) lOAD R/W BUFFER
(2) ISSUE START l

KGOA READ R!W

IF TAPE IS READY

BUFFER INTO THE
AC

<;'

....
o
lOAD AC WITH WORD TO
BE WRITTEN AND KGOA
AC - R/W BUFFER

"KGOA ASSERTS START L AND STARTS
TAPE MOVEMENT IF THE SELECTED
DRIVE IS READY TO EXECUTE THE
FUNCTION

Figure 10-8 TA8-E Flow Diagram

Table 10-3
TAS-E Instructions
Operation

Mnemonic

Octal
Code

KCLR

67XO

Clear All: Clear the Status A and Status B Registers (Tables 10-4 and 10-5).

KSDR

67Xl

Skip the next instruction if the Data flag is set during read or write operations.

KSEN

67X2

Skip the next instruction if any of the following are true:
a.

Tape is at EOT/BOT (End of Tape or Beginning of Tape).

The TU60 is not ready or the selected drive is empty.

KSBF

67X3

Skip the next instruction if the Ready flag is set.

KLSA

67X4

Load Status A from AC4-ACll, clear the AC, and load the complement of
Status A back into the AC (Table 10-4).

KSAF

67X5

Skip on any flag or error condition.

KGOA

67X6

Assert the contents of the Status A Register and transfer data into the AC during
a read operation or out of the AC to the Read/Write Buffer during a write
operation. This instruction has three functions.

KRSB

67X7

Enables the command in the Status A Register to be executed by the
TU60.

For read operations, the first KGOA instruction causes the tape to
start moving, and when the Data flag sets, a second KGOA transfers
the first byte from the Read/Write Buffer to the AC. The Data flag
sets after each 8-bit byte is read from the TU60.

For write operations, the Status A Register is set up for a write, and
the AC contains the first byte to be written on tape. When the
KGOA instruction is executed, the tape starts to move and the first
byte is transferred to the TU60.

Transfer the contents of the Status B Register into AC4-ACll (Table 10-5).

10-11

10.10.1

Output Interface Signals

The T AS-E provides the following output signals to control the TU60.
10.10.1.1 SE LECT ENABLE L - This signal, at a logical 1, enables the TU60 input/output transmitters and
receivers if bit 04 in the Status A Register is set (1).
10.10.1.2 DRIVE B L- This signal is asserted by bit 05 in the Status A Register to select one of the dual tape
drives. A logical 1 (low) selects drive B or a logical 0 (high) selects drive A.
10.10.1.3 START L- This signal, at a logical 1, is used in conjunction with a specific command to initiate
command execution. If a command is to be performed, the drive must be in the READY state (READY L asserted)
and the command must be present and stable one microsecond prior to START L. If this is the case, when START L
is received, the TU60 removes the READY L signal and initiates execution of the tape command. When READY Lis
removed, the TAS-E then removes START L. While the command is being executed, any additional START L signals
are ignored by the drive.
10.10.1.4 REWIND l - This signal, at a logical 1 (low), is clocked by the START L signal to cause the TU60 to
rewind to Beginning Of Tape (BOT).

Table 10-4
Contents of the Status A Register
AC
Bit

Function

When bit 11 is a 1, enable the interrupt logic.

Not Used.

OS-06

ACOS-AC06 are applied to the Function Register to select one of the TU60 operations as follows:
AC06
(FRO)

AC07
(FR1 )

AC08
(FR2)

0
0
0
0

0
0

0
1
0
1
0

1
1

0
0

Operation
Read
Rewind
Write
Back Space to File Gap
Write Gap
Back Space to Block Gap
Read/Write CRC Character
Space Forward to File Gap

Select TU60 Drive A if bit 5 is a 0 and Drive B if bit 5 is a 1 (high).

Enable the TU60 input receivers and most of the output transmitters.

10-12

Table 10-5
Contents of the Status B Register
AC
Bit

Function

Ready flag: The Ready flag is set (1) when the selected drive is ready to accept commands from
the TAB-E. A cassette must be installed and the selected tape drive must be stopped, which would
indicate that previous tape operations have been completed.

WRITE LOCK: WRITE LOCK is set (1) if the selected drive is empty or if the cassette installed is
write protected.

REWIND: REWIND is set (1) if the selected drive is performing a rewind operation.

DRIVE EMPTY: DRIVE EMPTY is set (1) if the selected drive does not have a cassette installed
or the cassette installed is not a digital grade cassette.

End of File: The End of File (EOF) flag is set (1) if a file gap is detected or the TU60 reads a
blank space on the tape.

EaT/BOT: End of Tape or Beginning of Tape (EaT/BOT) is asserted if the photosensor on the
TU60 is uncovered when the tape is at the beginning or end of tape (F igure 10-2).

TIMING ERROR: TIMING ERROR is set (1) if the TAB-E does not respond to a TRANSFER
REO from the TU60 within 230 JlS.

CRC/BLOCK ERROR: CRC/BLOCK ERROR is set (1) if a CRC ERROR is detected during a
read operation.

10.10.1.5 BACK BLOCK GAP L - This motion command signal, at a logical 1 (low), is clocked by the START L
signal to cause reverse tape motion at read/write speeds across a data block to the preceding PREGAP.
10.10.1.6 BACK FILE GAP L - This signal, at a logical 1 (low), is clocked by the START L signal to cause reverse
tape motion at search speed across a data file and the tape drive stops at two-thirds of the preceding file gap.
10.10.1.7 READ/WRITE FILE GAP L - This signal, at a logical 1 (low), is used in conjunction with the WRITE
MODE L signal to initiate either forward tape motion or a write file gap operation. If WRITE MODE L is a logical 1
when this signal is clocked by the START L signal, 535 ms of tape is erased. If the gap is a load point gap (at the
Beginning Of Tape), 1.4 seconds of tape is erased. If WRITE MODE L is a logical 0 when this signal is clocked, tape
on the selected drive moves forward, stopping at the beginning of the next file gap.
10.10.1.8 WRITE MODE L - This signal selects either the read or write logic. For a write or write file gap
operation, this signal, at a logical 1 , is clocked by the START L signal to set the TU60 Write flip-flop.
For a read operation, this signal, at a logical 0, allows the START L signal to reset the Write flip-flop in the TU60.
Once the specific operation is initiated, the Write flip-flop remains either set or reset until the next operation is
started.

10-13

10.10.1.9 TRANSFER l - During a write operation, this signal, at a logical 1, is transmitted to the TU60 in
response to a TRANSFER REO l signal. If this is the case, TRANSFER L sets the TRANS REO flip-flop and the
8-bit byte is loaded into the TU60 Data Buffer.
During a read operation, this signal, at a logical 1, is transmitted to the TU60 in response to a TRANSFER REO l
signal. TRANSFER L sets the TRANS REO flip-flop to indicate that the 8-bit byte has been loaded into the
Read/Write Buffer.
10.10.1.10 READ/WRITE CRC l - During a write operation, this signal, at a logical 1, causes the accumulated
eRC character to be recorded on the tape. R/W eRe L is transmitted to the TU60 while the final data byte is being
recorded. When this occurs, the next TRANSFER REO L signal is inhibited and the eRe character is recorded after
the final data bit is written (Paragraph 10.8.6).
During a read operation, this signal, at a logical 1, tests the eRe Register for an error. At the start of a read
operation, the CRe ERR flip-flop is set and remains set while the data block is being read. After the first eight eRe
bits have been read, the TA8-E interface transmits READ/WRITE CRC L. READY L inhibits eRe ERROR (if one
occurs) until the transfer is completed. When the final TRANSFER REO L signal is generated, the eRe Register is
checked for O. If the register is not 0 (data read incorrectly), the eRe ERR flip-flop remains set and when READY
L is generated, a eRe ERROR L signal is also generated. If the data has been read correctly, the eRe ERR flip-flop
resets and a eRe ERROR L signal is not generated.
10.10.1.11 INITIALIZE l - This signal, at a logical 1, removes all TU60 flags (except EOT/BOT or eRe ERROR),
generates READY L, and except for a rewind operation stops tape motion regardless of the tape position.
10.10.2 Input Interface Signals
The following input signals are received from the TU60 and applied to Status B, the interrupt logic, and the skip
logic.
10.10.2.1 OFF LINE l - This signal, at a logical 1, indicates that the appropriate tape cassette is not properly
loaded on the selected drive, or that the clear leader sensing lamp has failed.
10.10.2.2 READY l - This signal, at a logical 1 (low), indicates that the appropriate tape cassette has been
properly loaded and tape motion is not occurring on the selected drive. I n general, READY L is generated when all
command functions have been completed and the drive is ready for the next operation, or when a clear leader on the
tape is encountered.
10.10.2.3 END FilE l - This signal, at a logical 1, indicates that a file gap has been detected or the tape is blank.
10.10.2.4 EOT/BOT l - This signal, at a logical 1, indicates that the drive has reached the End-of-Tape or
Beginning-of-Tape (clear leader uncovers photosensor). When this occurs, tape motion stops and the READY Land
EOT/BOT L signals are generated.
10.10.2.5 REWIND l - This signal, at a logical 1, indicates that the selected drive is performing a rewind
operation.
10.10.2.6 WRITE PROTECT l - This signal, at a logical 1, indicates that a write-protected cassette is loaded on
the selected drive, or that the drive is empty. If the cassette is write protected, the selected drive will not perform
any write operations.
10.10.2.7 WRITE STATUS l - This signal, at a logical 1, indicates that a write or write file gap operation is being
performed on the selected drive.

10-14

10.10.2.8 TRANSFER REQUEST L - During a write operation, this signal, at a logical 1, indicates that the drive is
ready to receive an S-bit byte from the ReadlWrite Buffer Register. The TRANSFER REO L signal is generated one
bit time before a byte is needed, and this signal is removed when the interface responds with a TRANSFER L signal.
During a read operation, TRANSFER REO L, at a logical 1 (low), indicates that a byte from the drive is ready to be
transferred to the Read/Write Buffer Register. The TAS-E must then respond with a TRANSFER L signal within one
bit (230 /1s) after the TRANSFER REO L signal is generated or a TIME ERROR occurs.
10.10.2.9 TIME ERROR L - This signal, at a logical 1, indicates that the interface has not responded to a
TRANSFER REO L signal within the allotted time (230 /1s).
10.10.2.10 CRC BLOCK ERROR L - This signal, at a logical 1, indicates that a CRC error has occurred during a
read operation. At the start of the read operation, the CRC ERR flip-flop is set. When the final CRC character is
read, the CRC Register is checked for O. If the register is not 0, the CRC ERR flip-flop remains set, and when
READY L is generated, a CRC ERROR L signal is also generated.

SECTION 4 DETAILED LOGIC
10.11

DEVICE SELECT AND lOT DECODER

The lOT decoder (Figure 10-9) decodes TA8-E lOT instructions from the Memory Data Bus and generates signals to
control the T AS-E and TU60. Bits MD3-MD 11 are gated by I/O PAUSE when an 1/0 instruction is generated.
MD3-MDS generate signal SELECT H and enable bits MD9-MDll to be applied to the lOT decoder. The device
code 67X, where X is equal to 0-7, is selected by the jumpers on the output of NAND gates E7 (Table 10-1). The
lOT decoder is a DEC 7442 IC (see Section 7 for truth table and logic diagram). The DEC 7442 IC is a
BCD-to-decimal decoder that decodes MD9-MD11 and produces a low or one on the output line to indicate which
instruction has been executed by the program. As an example, MD9 low, MD1O, and MOll high (100) produce a
low on pin 4, which indicates a KLSA instruction was programmed.
10.12 CONTROL LOGIC
10.12.1

C Line Select Logic

The C line select logic (Figure 10·9) controls the direction of data flow between the AC and the Data Bus and
determines whether or not the AC is cleared. Table 10-6 gives the status of CO and Cl (high or low) for transferring
data between the AC and Data Bus, using the TAS-E instructions. As previously stated, when the KLSA instruction
is executed by the program, the C lines must be changed and this change must take place during the time that the
instruction is being executed. To accomplish this, flip-flop E14 (01 R) is cleared at TP3 time of the instruction cycle
(Figure 10-10), causing CO Land Cl L to go low and asserting NOT LAST TRANSFER L. NOT LAST TRANSFER
L stops processor timing to allow the Status A Register to settle and the C lines to switch before the complement of
the Status A Register is applied to the AC via the Data Bus. ENABLE H is negated (low) to prevent the contents of
the Status A Register from being applied to the Data Bus while the C lines are switching.

Table 10·6
C Line Select Levels for Transfers to the AC
Instruction

Transfer Operation

KLSA

low
low
low
low
low

high
low
high
low
low

AC-+DATA BUS then O-+AC
DATA BUS-+AC
WRITE: AC-+DATA BUS
READ: DATA BUS-+AC
DATA BUS-+AC

KGOB
KRSB

10-15

*MD06L---.------~

}---.---SELECT H

,,
L--4-----------o"
.. M007 L---<>---+---d-____

L--4----------o"

0-----_--""C1 L

,
0
IOT 6 L

"MD09 L

,,
L----1'----------c/

"MD1O L

"I/O PAUSE L

READ DATA
ENABLE L

,,
.. M008 L--_>---+---d'

b-----+-~"CO L

:MD03 L
"MD04 L
MD05 L

67X6(KGOA)
E27
lOT
DECODER
(7442)

67X5(KSAF)
67X4(KLSA)
67X3(KSBF)

LOAD STATUS A L

67X2(KSEN)
67X1(KSDR)
67XO(KCLR)

*MD11 L

TP3 H

*TP2 H ---------\

"OMNIBUS SIGNALS

8E-0670

Figure 10-9 Device Select and lOT Decoder Logic

+5V

D
CO l
E14
DlR
(7474)

Cll

lOT 4
C

0
ENABLE A H

TP3 H

E31

TP4 H

NOT lAST XFER l

lOT 4 H

BUS
STROBE l

+5 V ~'VV'v---'----l

E19A
ONE SHOT
(74123)
320ns

+ 5V --'INV-.----l

E19B
ONE SHOT
(74123)
lOOns

o
+3V

8E-0664

Figure 10-10 Data Transfer Control Logic

At the same time E14 (DIR) is cleared, the 741231C (see Appendix A, Volume 1 for logic diagram) is triggered (the
74123 IC is a dual one-shot multivibrator). E19A outputs a 320 ns pulse when triggered by the high to low
transition on the output of E3 NAND gate at TP3 time. The trailing edge of the pulse out of E 19A triggers E 19B
and generates a 100 ns pulse. The 100 ns pulse out of E19B asserts BUS STROBE L to restart processor timing. E14
changes state at TP4 time, and the C lines are switched to transfer the information on the Data Bus to the AC.
10.12.2 Time Pulse Logic
Time pulses, TP2, TP3, and TP4, are used throughout the module to enable gates and enable the execution of
instructions.
10.12.3 Initialize and Clear All Logic
INITIALIZE clears all TAS-E and TU60 logic when the power is first turned on, when the CLEAR key on the
programmer's console is depressed, or when the CAF instruction is executed. CLR ALL L is asserted when
INITIALIZE L is asserted, or when the KCLR instruction is executed to clear all logic on the TAS-E and TU60.
INIT L to the TU60 (Figure 10-9) is asserted longer than CLR ALL in the TAS-E to allow enough time for the signal
to be transferred to the TU60 and to clear the logic in the TU60. Flip-flop E20 is cleared by CLR ALL L to assert
INIT L at TP3 time and remains cleared until the next TP2 time. TP2 H sets flip-flop E20 and removes INIT L from
the TU60 during the next instruction cycle.

10-17

10.13 STATUS A REGISTER
The Status A Register (Figure 10-11) is loaded from the AC by a KLSA instruction, the AC is cleared, and the
complement of Status A is transferred back to the AC. Thus, one instruction is used to load and read the Status A
Register. The output of the Status A Register is used to enable interrupts, select a tape operation, select a tape drive,
and enable the TU60 transmitters and receivers.

DATA II L

INT ENA H
DATA \I L

DATA 10 L

DATA 09 L

NOT USED
E32
STATUS
REGISTER A
(8270

NOT USED

DATA 08 L

FR2 H
CLR LD CLK OS

FR 1 H

DATA 07 L

DATA 06 L

DATA 05 L

SELECT H

FRO H
E51
STATUS
REGISTERA
(8271)

DRIVE B H

SELECT ENABLE
CLR LD CLK OS t----------1r----~

DATA
05 L

DATA
04 L
ENABLE A H - - < _ - - - - - - - - - - '
8E-0674

Figure 10·11 Status A Register

10.14 FUNCTION REGISTER
The Function Register (Figure 10-12) decodes FRO-FR2 from the Status A Register to select one of the TU60
operations (Table 10-4). The Function Register is a DEC 7442 IC (see Section 7 for truth table and logic diagram)
that decodes FRO-FR2. The 7442 IC is a BCD-to-clecimal decoder that produces a low on one output line for each
combination of bits that are supplied as inputs. As an example, if FRO is low and FRl and FR2 are high (100), the
Back Space To File Gap line is asserted (low) and the TU60 is commanded to execute this operation. The output
signals applied to the TU60 are explained in Paragraph 10.10.

10-18

r------,:>---- NOT USED
j'>----NOT USED
SPACE FORWARD TO FILE GAP

E12
READ/WRITE GAP L

READ WRITE CRC CHARACTER

II
I

FUNCTION
BITS
FROM
STATUS A

FRO H

FR1 H

BACKSPACE TO BLOCK GAP
E4
FUNCTION
REGISTER
(7442)

WRITE ENA H

READ/WRITE CRC L
BACK BLOCK GAP L

ElO

WRITE GAP
BACKSPACE TO FILE GAP

BACK FILE GAP L

FR2 H
WRITE

E10 WRITE MODE L

REWIND

REWIND CMD L

READ

ElO

E10
E12

READ DATA ENA L

IOT 6 L (KGOA)
WRITE STATUS L

DRIVE EMPTY L
LOAD READ/
WRITE BUFFER L

TRANSFER RQST L

XFER (1) H

D
E13
XFER
(7474)

WRITE DATA ENA H

IOT6 (KGOA)

TP3 H
E12
BE -0675

Figure 10-12

Function Register

10.15 START LOGIC
Before any operation can be started by the TA8-E and TU60, START L must be asserted (Figure 10-13). To set the
START flip-flop, the TU60 must be in the READY state and there must be a cassette installed on the selected drive.
When these conditions are met and the KGOA instruction is executed by the program, the START flip-flop will set
at TP3 time and assert START L (low). START L is applied to the TU60 and the operation selected by the program
when the Status A Register was loaded is started. The TU60 ignores any START L signals that are generated after an
operation is started.
START is cleared by CLR ALL when it is asserted by INIT L from the processor or when the KCLR instruction is
executed by the program.
END L is applied to Status B to indicate to the program that the selected drive is ready for an operation and the
previous operation is complete. Note that READY L is negated if the TU60 is performing an operation.

DRIVE
EMPTY L
END L

READY L

REW L

E14
START

START L

CLEAR
ALL L
8E-0669

Figure 10·13 Start Logic

10.16 READ/WRITE BUFFER REGISTER
The Read/Write Buffer Register (Figure 10-14) is used during write operations to store an 8-bit byte until the drive is
ready to write it on the tape. During read operations, this register stores a word read from the tape until the
processor transfers the 8-bit byte to the AC. The Read/Write Buffer Register is an 8271 Ie (see Appendix A, Volume
1 for truth table, logic diagram, and pin locations) which is parallel loaded when LOAD R/W BUFFER L is asserted
(Figure 10-13).

10-20

DATA II L
RWOI H
RWOI L

RWOI L

DATA 10 L
RW02 H
RW02 L

RW02 L

E47
8271
READ/WRITE
BUFFER
REGISTER

DATA 09 L

RW03 H
RW03 L

RW03 L

DATA 08 L
RW04 H
RW04 L

RW04.L

LOAD R/W BUFFER L
+5V

DATA 07 L
RW05 H
RW05 L

RW05

DATA 06 L
RW06 H
RW06 L

RW06 L
E39
8271
READ/WRITE
BUFFER
REGISTER

DATA 05 L

RW07 H
RW07 L

RW07 L

DATA 04 L
RW08 H
RW08 L

RW08 L

IOT 6 L (KGOA)
READ L
WRITE DATA ENA H
BE-0676

Figure 10-14 Read/Write Buffer Register

10-21

LOAD R/W BUFFER L is asserted when one of the following conditions are met:
a.

During read operations, the XFER flag (Figure 10-15) must be set (1) and a read operation must be
selected by the program. XFER is set by TRANSFER ROST L each time a word is read from tape and
applied to the Read/Write lines (R/W 01-R/W 08). The selected drive must not be in a write status.

During write operations, if WRITE DATA ENA H (Figure 10-12) is asserted by the Function Register
and the KGOA instruction is executed by the program. The selected drive must be in a write status.

TRANSFER~~~

RQST L

__~

E13

XFER
(7474)

t----+-DATA (1) H

D
E13

DATA
FLAG

(7474)
Ot--r--~C

Ot----*-,

TRANSFER L

rOT 4 L (KGOA)
8E-0671

Figure 10-15 TA8-E Flags

10.16.1

Data Flag

The Data flag (Figure 10-15) is set each time a TRANSFER ROST is made by the TU60. When the Data flag sets,
the program is interrupted by an INT ROST if the interrupt system is turned on (bit 11 in Status A must be 1) or a
SKIP is generated if one of the SKIP lOTs are executed by the program. During read operations, the program must
execute the KGOA instruction and transfer data to the AC from the Read/Write Buffer Register. During write
operations, the KGOA instruction is executed and data is transferred from the AC and applied to the Read/Write
lines via the Read/Write Buffer Register. WRITE DATA ENA H enables data to be applied to the Read/Write lines
during write operations. During read operations, READ DATA ENA L (Figure 10-16) is asserted to transfer data
from the Read/Write lines to the OMNIBUS.

10.17 INTERRUPT LOGIC
An INT ROST (Figure 10-16) is made by the TA8-E if bit 11 in the Status A Register is set (1), and the following
conditions exist:
a.

One of the following Error flags is set.
1.
2.
3.
4.

b.
c.
d.
e.

TIME ERR
WRITE LOCK (If a write operation)
CRC/BLK ERR
DRIVE EMPTY

The tape is REWINDING.
The tape is at EDT/BOT.
The Data flag is set.
END L is asserted (low).
10-22

SKIP L

E2B

INT RQST L

EDTIBOT L
END FILE L

DRIVE EMPTY L
DATA FLAG(O) H

WRITE LOCK H
WRITE DATA ENA H

1--'
11
liNT
I BIT
FROM
ENA H
I STATUS A I

L __ -.J

8E-0672

Figure 10-16 Interrupt and Skip Logic

10.18 SKIP

SKIP L (Figure 10-16) is asserted and the program will skip the next instruction if one of the following conditions
exist:
a.

The program executes a KSDR instruction and the Data flag is set (1). The Data flag is set when the
program must execute a data transfer during read and write operations.

The program executes a KSEN instruction and the tape is at EaT/BOT or End of File (EOF).

The program executes a KSBF and the selected drive is not empty; tape drive is in the READY state and
not rewinding.

The program executes a KSAF instruction and any flag is set.

10.19 OUTPUT DATA MULTIPLEXER

The Output Data Multiplexer (Figure 10-17) is used to apply read data to the Data Bus during read operations or the
contents of Status B to the Data Bus when the KRSB instruction is executed by the program. The Output Data
Multiplexer consists of two 8235 ICs (see Appendix A, Volume 1 for truth table, logic diagram and pin locations)
that select one of two sets of inputs to be applied to the Data Bus. If the program executes a KRSB instruction, the
lOT 7 L signal is asserted and the contents of the Status B Register are applied to the Data Bus. During read
operations, READ DATA ENA L is asserted (low) and the data on the Read/Write lines is transferred to the Data
Bus.

10-23

END L
Jl-FF WRITE LOCK L

*RW 01 H
WRITE LOCK L

Jl-X REW L

*RW 02 H
REW L

Jl-J DRIVE EMPTY L

*RW 03 H
DRIVE EMPTY L

DATA 11 L
E42
(8235)

DATA 10 L
DATA 09 L

*RW 04 H

J2-Z EOF L

END FILE L

J2-BB EOT/BOT L

*RW 05 H
EOT /BOT L

J2-DD TIM ERR L

*RW 06 H
TIM ERR L

J2-TT CRC BLK ERR L

*RW 07 H
CRC BLK ERR L
*RW 08 H

IOT 7 L _ _ _ _ _ _ _ _

DATA 08 L
SO

DATA 07 L
E37
(8235)

DATA 06 L
DATA 05 L
DATA 04 L

~+_----------J

READ DATA ENA L - - - - - - - - - - + - - - - - - - - - - - - - '
*RW 01- RW 08 FROM THE READ/WRITE BUFFER REGISTER

8E-0673

Figure 10-17 Output Data Multiplexer

SECTION 5 MAINTENANCE
10.20 PREVENTIVE MAINTENANCE
Recommended preventive maintenance should be scheduled at regular intervals to maintain reliability and
performance in the TU60 Cassette Tape Transport System. Preventive maintenance schedules are found in the TU60
Cassette Tape Transport Maintenance Manual (DEC-00-TU60-DA).
The TA8-E Diagnostic (MAINDEC-08-DHTAA-A) and the TA8-E Data Reliability Test (MAINDEC-08-DHTAB-A)
are supplied to checkout and test the T A8-E. The diagnostic programs and reliability tests check all logic and the
ability to read or write data. TA8-E signals can be monitored with an oscilloscope while the diagnostics are running
to aid in the location of malfunctioning components. When a malfunction is suspected, the TA8-E diagnostics should
be used to checkout and troubleshoot the TA8-E. Refer to the TU60 Cassette Tape Transport Maintenance Manual
for test equipment, troubleshooting aids, and adjustments.
10.21 CORRECTIVE MAINTENANCE
The following programs are provided to aid in troubleshooting the TA8-E.
NOTE
A Tektronix 453A or equivalent oscilloscope with X10 scope
probe and an IC test clip are required for these tests_

10-24

10.21.1

lOT Decoder Check

To check the lOT decoder, perform the following steps:
1.

Deposit the following program into core memory, starting at location 0200.
Memory Location

Instruction

Operation

0200
0201
0202
0204

7604
3202
0000
5200

LAS
DCA switches in 202
Contents of switches
JMP-3 to beginning

Set the Switch Register (SR) to 6700.

Load address 0200, then press CLEAR and CaNT.

Set up the oscilloscope to monitor signals on channel A. Monitor SELECT H on pin 3 of E 1. SELECT H
should be present for 500 ns (Figure 10-18).

SYNC on channel A (SELECT H signal) and monitor pin 1 of E27 with channel B. Pin 1 is the output
line of the lOT decoder for the 6700 (KCLR) instruction (Figure 10-9).

Change SR to 6701 and monitor logic for the 6701 instruction.

Set the Switch Register to octal values for each of the lOT instructions (Table 10-3) and monitor the
logic associated with each instruction. Refer to the M8331 module prints (D-CS-M8331-0-1).

+3V------~----~

r--APPROXIMATELY 6/kS---I
6E- 0667

Figure 10-18 lOT Decoder Output Signal

10.21.2 Status A Register Check
To check the Status A Register, perform the following steps:

Deposit the following program into core memory, starting at location 0400.
Memory Location

Instruction

Operation

0400
0401
0402

7604
6704
5200

LAS
KLSA, Load Status A
JMP-2 to beginning

10-25

Set SR to 0377.

Monitor logic associated with E32 and E51 (Status A Register). Set SR4 through SRll to both Os and ls
to be certain both can be transferred. Monitor the gates associated with Status A Register
(D-CS-M8331-0).

10.21.3 Status B Check
To check Status B signals, perform the following steps:

Deposit the following program into core memory.
Memory Location

Instruction

Operation

0600
0601

6707
5200

KRSB, Read Status B
JMP-1 to beginning

With a jumper or clip lead, ground pin 4 of E38. AC bit 4 should read a 1.

With a jumper or clip lead, ground pin 7. AC bit 5 should read a 1.

Check all of the status bits by grounding the pins of the E38 and E42 ICs (D-CS-M8331-0).

10.21.4 Read/Write Buffer Check
To check the Read/Write Buffer, perform the following steps:

Deposit the following program into core memory.
Memory Location

Instruction

Operation

1000
1001
1002
1003
1004

7200
1300
6704
7604
6706

1005
1006
1007
1010

7200
1301
6704
6706

1011
1100
1101

5200
0020
0000

CLA
TAD AC, WRITE
KLSA, Load Status A
LAS, Get Switches
KGOA, Load Read/Write
Buffer from AC
CLA
TAD AC, Read
KLSA, Load Status A
Read Read/Write Buffer
Register
JMP-9, to beginning
Constant
Constant

Monitor pin 13 of E44 and toggle SR4. Pin 13 on E44 should follow SR4.

Repeat step 2 for R/W 07 through R/W 01 gates with SR5 through SR 11 (D-CS-M8331) for pins for
R/W 07 through R/W 01.

10-26

10.21.5 Command Decoder Check
To check the command decoder, perform the following steps:
1.

Deposit the program used to check the Status A Register beginning at location 400.

Monitor FRO-FR2 and toggle SR6-SR8. The level of FRO-FR2 should change when the bit in the SR
associated with it changes.

SECTION 6 SPARE PARTS
The spare parts for the TA8-E are listed in Table 10-7.

Table 10-7

t AS-E Spare Parts
DEC Part No.

Description

19-10436

DEC IC 74123

19-00046

DEC IC 7442

19-09973

DEC IC 97401

19-09972

DEC IC 6314

19-09971

DEC IC 6380

19-09935

DEC IC 8235

19-09929

DEC IC 7417

19-09705

DEC IC 8881

19-09686

DEC IC 7404

19-09615

DEC IC 8271

19-05579

DEC IC 7440

19-05577

DEC IC 7420

19-05576

DECIC7410

19-05575

DEC IC 7400

19-05547

DEC IC 7474

Quantity

SECTION 7 IC DESCRIPTIONS
This section contains a description of those ICs used on the TA8-E that are not used in the PDP-8/E. ICs not
included in this section are contained in Appendix A, Volume 1 of the PDP-8/E Maintenance Manual.
DEC74421C
The DEC 7442 IC is a BCD-to-decimal decoder (Figure 10-19) that consists of eight inverters and ten 4-input NAND
gates. The inverters are connected in pairs to make BCD data available for decoding by the NAND gates. Full
decoding of valid input signals ensures that all outputs remain off for invalid input conditions.
In the TA8-E, the 7442 IC has a 3-bit input with the fourth bit (pin D) used as an enabling signal that allows the IC
to have an output only when it is enabled. Thus, there will be no erroneous signals out of the decoder.

10-27

B
INPUT A

J'<o.

L[>~

OUTPUT 0

C
D
A
B

OUTPUT 1

C
D
A
B

INPUT B

C
[)
A

C
5

OUTPUT 2

B
OUTPUT 3

A
B
OUTPUT 4

C
D
A
B
IN PUT C

......

OUTPUT 5

5
A

4>
INPUT D

.--

OUTPUT 6

C
D
A
B
C
D

OUTPUT 7

A
B

c
D

OUTPUT 8

D
A
B
OUTPUT 9

~r---k
D

0
0
0
0
0
0
0
0

0
0
0
0

0
0

11-0734

0
1

0
0

INPUTS

OUTPUTS

0
0
0
0
0

0
0

0
1

0
0

0
1

0
,o

GND

OUTPUTS

Truth Table
11-0733

Figure 10-19 DEC 7442 IC

10-28

PART 8
DISKS

CHAPTER 11
RKS-E DISK DRIVE CONTROLLER

SECTION 1 INTRODUCTION
11.1

PURPOSE

The RK8·E (Figure 11-1) provides the interface between the PDP-8/E OMNIBUS and the RK05 Disk Drive. As a
part of this function the R K8-E

INSTRUCTIONS

STATUS
DATA

RKB-E CONTROLLER
M7104
M7105
M7106

DATA,CONTROLS, STATUS

CABLE 700-9026

P
8
/
E

BC11

M
N
I
B

BC11A

S
BCllA
TERMINATOR
CARD
(M930)
8E-0526

Figure 11-1

RK8·E Controller and RK05 Disk Drive
System Block Diagram

Decodes programmed lOT instructions.

Accepts and stores current address, command, and extended memory address words.

Selects the designated R K05 and starts the designated operation.

Jointly (with the selected RK05) locates the disk address (track, sector, and surface).

Generates interrupts and skips for status checking operations.

11-1

Generates break requests to initiate single cycle data breaks (data transfers to or from memory).

Buffers the input/output data and performs related conversions (serial to parallel and parallel to serial).

Performs housekeeping chores for single cycle data break data transfers (i.e., increments Current Address
Register and provides sequential memory addresses).

Counts bits and words in a transfer to determine when to end a data transfer.

Generates and checks CRC (parity) for each sector.

Provides flags to indicate current conditions and error status.

Provides logic to aid in the maintenance of the R K8-E and R K05.

11.2 PHYSICAL DESCRIPTION
The RK8-E consists of the following quad modules, which are inserted into the OMNIBUS and used to control up to
4 (maximum) RK05 Disk Drives.
•

M7104, RK8-E Data Buffer Register and Status Module

•

M7105, RK8-E Major Registers Module

•

M7106, RK8-E Control Module

The RK8-E modules are inserted into the OMNIBUS and connected together with H851 Top Connectors. The
RK8-E is connected to the RK05 Disk Drives by a 7009026 cable.
11.2.1

R K05 Disk Drive

The R K05 Disk Drive contains the drive electronics and mechanism for accepting and releasing the disk, positioning
the read/write heads, and reading and writing data from the R K8-E control. The drive contains a removable disk
cartridge, control logic, and a power supply. No power is supplied to the 'R K05 by the R K8-E, and the R K05
supplies no power to the R K8-E. Table 11-1 lists the R K05 Disk Drive specifications.
NOTE
The specifications in Table 11-1 apply to the R K05 when it is
used with the RKS-E and a 16-sector cartridge. The RK05 may
be used in other systems with other controllers and sector
formats.

11.3 RECORDING METHODS AND FORMATS
This section describes the recording methods and the format used to write data on and read data from the RK05
Disk Drives.

11-2

Table 11-1
RK05 Disk Drive Specifications
Specification

Characteristic
Cylinder, Track, and Sector
Cylinder Density

200 CPI

Cylinders/Drive

203

Tracks/Cylinder

Sectors/Track

Sectors/Cylinder

Bit Density and Storage
Bit Density

2200 BPI

Bits/Cylinder

120,000

Bits/Sector

3750

Bits/Drive

24 million

Data Word Storage
Words/Sector

4008 or 256 10

Words/Track
Words/Cylinder

10,0008 or 4096 10
20,000 or 8192 10

Words/Disk

1616K

Transfer Rate
Word Transfer

8.32 usec

Bit Transfer Rate

1440 kHz

Recording Method

11.3.1

Double Frequency

Double Frequency Recording Method

The R KS-E uses the double frequency recording method. During a write operation, the R KS-E control generates
timing pulses called Write Data Clock pulses (Figure 11-2). The time between the pulses is called a bit cell (space for
writing data). A pulse within the bit cell represents a data 1 and the absence of a pulse represents a data O. The clock
pulse and data (0 or 1) are sent to the drive as Write Data and Clock pulses. Each pulse is recorded on the disk as a
flux transition. A pulse representing a data 1 and the clock pulses cause a change in direction of current flow
through the write heads and thus a change in the magnetic flux on the surface of the disk. Zero data bits do not
cause a change in current flow through the write head; thus, there is no change in the magnetic flux on the surface of
the disk.
During a read operation, the drive electronics separates the bit cell flux transitions and the data flux transitions. The
bit cell flux transitions are sent to the R KS-E as Read Data Clock pulses and the data transitions are sent as Read
Data pulses (serial bits of data).

11-3

WRITE

WRITE DATA

I-- 690n5 --I

WRITE DATA CLOCK

WRITE DATA CLOCK
AND DATA

DISK FLUX
TRANSITION

READ
READ DATA CLOCK

n n n n n r0

READ DATA

n
1

BE -0527

Figure 11-2 Double Frequency Recording Method

11_3_2 Disk Addressing
The surfaces of the RK05 Disk Cartridge are divided into 203 tracks and 16 sectors (Figure 11-3). Each surface has
one read/write head.
A drive can be commanded to seek one of 203 cylinder addresses. The drive generates a signal and supplies it to the
R KS-E when it is on the correct cylinder address. When the drive completes a seek, it is advisable to check the
cylinder address to ensure the heads are positioned correctly.
The RKS-E can be commanded to read the cylinder address (HEADER) from the first cylinder it finds and check
this against the cylinder address it previously sent to the disk drive. If the two addresses agree, the controller starts a
data transfer; if they do not agree, an ERROR flag is set. The program must determine what to do about the
ERROR flag.
A drive performing a seek can be deselected and another drive selected and commanded to seek; thus, overlapped
seeks are possible.
11.3.3 Sector Format
The sector format (Figure 11-3) consists of a 140 JlS PREAMBLE of zero data bits (time pulses only), a SYNC bit
(data bit = 1). a 16-bit HEADER word containing the cylinder address, 256 12-bit data words, a 16-bit Cyclic
Redundancy Check (CRC) character, and a 25 JlS POSTAMBLE (erase delay zone).
11.3.3.1 HEADER Word - The HEADER is a 16-bit word containing 5 zero bits and a S-bit cylinder address
tollowed by 3 zero bits.

11-4

SECTOR FORMAT
140Jjs
PREAMBLE
(ALL O'S)

SYNC
DATA=1

HEADER
(16 BIT
WORD)

256
DATA WORDS
(12 BIT WORDS)

CRC
(16 BIT
WORD)

POSTAMBLE / ERASE
(25)Js) DELAY ZONE

203 TRACKS
\

001

~
\

201 f

~
~

DISK SURFACE
" SECTOR ADDRESS 08 TO 178 ON UPPER OR 0 SURFACE
SECTOR ADDRESS 208 TO 37B ON LOWER OR 1 SURFACE TOTAL OF 32 SECTORS (16 ON TOP AND 16 ON BOTTOM)
8E-0528

Figure 11-3 Disk Format
11.3.3.2 CRC Character - Data is recorded on the R K05 in blocks of 256 12-bit words (serial data); thus, each
block contains 3072 bits of data recorded in a single string, with no separations to indicate word boundaries or
record error checking bits.
A long string of data bits is susceptible to single bit errors caused by dropins, dropouts, or burst errors. Burst errors
are caused by unwanted physical motion of the read/write heads. The R KS-E generates a Cyclic Redundancy Check
(CRC) character to check for these errors. The CRC is a block check character that is calculated by the R K8-E
during a read Qr write operation. The CRC character calculated during a write operation is written immediately
following the data (Figure 11-3) and becomes part of the data string. The process used to calculate the block check
word is such that if no errors occur, the CRC word calculated while reading data is identical to that calculated during
a write operation.

To calculate a CRC word, the data block is treated as a number 3072 bits long which is divided by a polynominal
(X l6 + X lS + x2 + 1). The hardware required to do this is a shift register with Exclusive OR gating idivision being
shift and subtract).
A maintenance instruction allows the program to read the CRC character written on the disk or the CRC character
read from the disk.

11·5

11.3.3.3 Formatting A Cartridge - A disk cartridge is "formatted" when the cylinder address of a sector is written
in the HEADER word of each sector. A special bit in the Command Register allows the program to write HEADER
words in each sector (format). The program need only set the bit and write something in each sector. The RK8-E
control writes the cylinder address automatically in the HEADER area (Figure 11-3) of each sector. The formatting
program writes coded information in the data region of each sector and reads it back to verify that the disk is
formatted correctly.
During a normal read or write operation, the disk seeks a cylinder specified by the RKS-E and reads the HEADER
word of the first sector it finds after the seek is complete. This HEADER word is compared with the cylinder
address specified by the R K8-E to ensure the correct cylinder has been found. The control then waits until the
sector containing the address specified by the program passes under the read/write heads before reading or writing
data.
11.3.3.4 Write Protect - WRITE PROTECT is turned on at the RK05 Disk Drive or by a bit in the Command
Register when it is loaded by the program. WRITE PROTECT must be turned off by pressing a manual control (WT
PROT) on each disk drive. If the program attempts to write on a disk that is write protected, the write operation is
inhibited and an error condition is produced. WRITE PROTECT may be turned on manually at the RK05 by .
pressing the WT PROT switch.
11.4 MAJOR REGISTERS
The major registers of the RK8-E are in two broad categories: those that are loaded or read by user software and
those that are transparent to user software. The first category includes the Command Register, Current Address
Register, Disk Address Register and Status Register. The second category includes the 4-word Data Buffer Register,
the CRC Register, Major State Register, Modulo 12- and Modulo 16-bit counters, and the Modulo 128- or 256-Word
Count Register.
The major registers must be loaded from the AC by lOT instructions in the correct sequence before they perform
any control function. The individual flip-flops in the registers are set by a 1 (true) and cleared by a 0 (false) bit from
the AC. Refer to Section 3 for a list of lOT instructions and a detailed discussion of the contents of each major
register.
11.4.1 Command Register
The Command Register (Figure 11-4) is loaded from the AC by lOT 6746. This lOT also clears the AC and the
Status Register.
11.4.2 Current Address Register
The Current Address Register is a 12-bit register loaded from the AC with lOT 6744, which also clears the AC. This
register and 3 bits of the Command Register (Figure 11-4) are combined to make up a 15-bit Memory Address
Register. The ~ontents of the CA Register and the 3 bits in the Command Register are applied to the OMNIBUS to
select a memory location during a data transfer. The CA Register is incremented before each data transfer to select
the next sequential memory location. The EMA bits In the Command Register are not incremented, and these bits
must be changed by the program to select new memory fields. If the CA Register is i.ncremented past the last
memory location in a field, it will wrap around in the same field. The data is stored in location 000 and starts
incrementing through the field again.
11.4.3 Disk Address Register
The Disk Address Register is loaded from the AC by lOT 6743, which also clears the AC and enables the contents of
the Command Register to be applied to the control logic.

11-6

ENABLE
INTERRUPT
ON DONE
FLAG
FUNCTION
0
0
0
0
1
1

0
0
1
1
0
0

0
1
0
1
0
1
0

EMA2 EMAI
EMAO
EXTENNDED MEMORY
ADDRESS

TRANSFER
128 WORD
BLOCK

ENABLE
DONE
ON SEEK
DONE

READ DATA
READ ALL
SET WRITE PROTECT
SEEK ONLY
WRITE DATA
WRITE ALL
NOT USED
NOT USED

MOST
SIGNIFICANT
CYLINDER
ADDRESS
BIT
MEMORY FIELD

0
0
0
0

0
0
1
1
0
0

1
1

0
1
0
1
0
1
0
1

0
1
2

3
4

5
6

0
0

0
1
0

1
2

BE-OG10

Figure 11·4 Contents of Command Register

The Disk Address Register selects a sector to be used in a data transfer. To select an individual sector, the following
must be selected (Figure 11·5).

r;;--'

I
ICOMMAND
REGISTER

:'LJ ;\

L - -....l..--...L.._2l..--3.....l-.\4--L...\_5l..--6....l-\7--1.-\_8l..--9-1...;....'--1-0---1'1

L __ .J
""
.
1.
-

)

CYliNDER (TRACK) ------,~

SURFACE ~ SECTOR ~
8E-0609

Figure 11·5 Disk Address Register

1 of 203 cylinders

1 of 2 surfaces

1 of 16 sectors

The Disk Address Register and bit 11 in the Command Register (Figure 11·4) are combined to select a cylinder,
surface, and sector. The largest valid address is 14537 8 (cylinder address 202 10 ).

11·7

11.4.4 Status Register
The Status Register (Figure 11-6) contains all the information needed for the program to evaluate the operation of
the R KS-E and R K05.

CONTROL DONE.J
RDYS/R/W

NOT USED
SEEK FAIL

11\

L LDRIV~S~:~::::~~RESS

ERROR

DATA REQUEST LATE

CRC ERROR

WRITE LOCK OUT ERROR

FILE NOT READY

TIME OUT ERROR

BUSY ERROR
1 =TRUE
0= FALSE

eE-osoe

Figure 11-6 Contents of Status Register

11.4.5 Data Buffer Register
All data transfers between memory and a drive pass through the 4-word Data Buffer Register (DB1 through DB4).
This 4-word register increases the latency of the R K8-E control from 6.2 JiS with a single serial register and one data
buffer to 22.5 JiS with 4 Data Buffer Registers. Latency is defined as the maximum time the RKS-E control waits for
access to the computer memory before data is lost. The numbers given above are for a memory cycle time of 1.2 JiS.
During a read operation, Data Buffer 1 accepts the serial data from the drive and transfers a complete word to the
last unused buffer, which is eventually removed from Data Buffer 4 and transferred to computer memory. On a
write, data from computer memory enters Data Buffer 1 in parallel mode, transfers to the last unused buffer, and is
shifted out to the drive as a 12-bit serial word from Data Buffer 4.
During maintenance operations, the contents of the CRC Register, Command Register, and the Surface/Sector
Register (disk address) are shifted into Data Buffer 4 by the maintenance lOT for transfer to the AC or memory.
11.4.6 CRC Register
The CRC Register is a 16-bit register used to calculate the CRC character that is written onto the disk after the last
data word. During a read, it calculates the CRC of the read data and does a bit-by-bit comparison with the CRC
word read from the disk. It also contains the cylinder address loaded from the AC by the Load Address and GO
instructions. The CRC Register does a bit-by-bit comparison of the HEADER word to confirm that the selected
drive has found the correct cylinder address.
NOTE
The CRC Register and the Disk Address Register are physically
the same logic with multi purposes.

11.4.7 Major State Register
The Major State Register (Table 11-2 and Figure 11-7) is the control sequencer of the RKS-E; with its associated
gating, this register performs the major portion of the control functions of the RKS-E. The Major State Register is
incremented from one state to another, and its decoded outputs gate signals to or from the disk and perform
housekeeping tasks such as determining whether the control is in the HEADER region, data region or CRC region of
the disk format.
11-S

Table 11-2
Maior States
Operation
Seek Seek
Seek Check Check Seek Seek
Read Write Read Write

Major
State

Function

IDLE

Control is not busy until the GO

Command (DLAG) is issued and the
contents of the AC are loaded into the
CRC. The CRC Register contains the
Cylinder/Surface Address (Disk Address)
STROBE

Strobe the Cylinder Address from the
CRC Register to the Disk Drive and
wait for the Disk Drive ADDRESS
ACKNOWLEDGE signal.

DRIVE

Wait for DISK READY to SEEK, READ,

SEEKING

or WR ITE from the Disk Drive to
indicate the heads are positioned over
the Cylinder Address.

HEADER A

Wait for the first Sector Mark, then
start READ DELAY.

HEADER B

At the end of READ DELAY turn the
READ flip-flop on. Zeros are read
until the SYNC bit is read at the beginning of a block of data.

HEADER C

Read the 16-bit HEADER word and
compare it with the cylinder address
in the CRC Register.

SECTOR

If the HEADER word does not equal

SEEK

the cylinder address set CYLI N DE R
ADDRESS ERROR and go to IDLE
state. At each sector mark compare the
sector address with the Disk Sector
Address lines

If the addresses are equal

go to the next state. If this is a write
operation transfer data from the processor to the Data Buffer Register.

11-9

Table 11-2 (Cont)
Major States
Major
State

Operation
Seek Seek
peek Check Check Seek Seek
Read Write Read Write

Function

HEADER D

At the beginning of the sector start

( Read)

READ DELAY (85)1s). At the end of

READ DELAY set the READ flip-flop.
Note zeros are read until the SYNC bit
is read.
HEADER D

At the beginning of the sector start

(Write)

SYNC DELAY. Zeros are written

during SYNC DE LA Y time and after
SYNC DELAY times OUT (140)1s) a
one SYNC bit is written.
HEADER E
( Read)

Count and ignore the first 16 bits.

HEADER E
(Write)

Write the HEADER word contained in
the CRC Register.

DATA STATE
( Read)

Read 256 12-bit data words and a 16-

bit CRC character from the Disk and
compute a CRC. The 12 bit data words
are transferred to the Data Buffer
Register and the controller tries to keep
the Data Buffer Register empty by transferring data to the processor via the single
cycle data break.

DATA STATE
(Write)

Write 256 data words on the Disk Drive.

The Data words are transferred. from the
processor via the Single Cycle Data Break.

CRC STATE
( Read)

Read the CRC from the Disk Drive and

compare it with the CRC computed by
the controller.

CRC STATE
(Write)

Write the computed CRC on the disk
after 256 data words have been written.

11-10

Table 11-2 (Cont)
Major States
Major
State

Operation
Seek Seek
Seek Check Check Seek Seek
Read Write Read Write

Function

END STATE
( Read)

If the CRC character read from the Disk
Drive does not equal the computed C RC,
set the CRC ERROR flag and clear Read.
When the Data Buffer Registers are
transferred into processor memory, set
the DONE flag and go to the IDLE state.

END STATE
(Write)

Start ERASE DELAY and Write zeros.
At the end of ERASE DELAY (25).1s)
clear WRITE, set the DONE flag and go
to the IDLE state.

, - - - - - - - - SECTOR MARK
SYNC BIT

TP3
WAIT FOR
DISK ADDRESS
ACKNOWLEDGE

READ
DLY
85~5

READ
ZEROS

WAIT
READ
READ
FOR
COUNT
256 WORDS
CRC
SILO
16 BITS (12 BIT WORDS) WORD EMPTY

WAIT FOR
DISK READY TO
SK/RD/WRT
WAIT FOR
SECTOR MARK

READ READ
DLY ZEROS
85u5

'---S:-:CyC-:-NCo--- SECTOR MARK
j4-_BIT DLY~

SECTOR MARK [SYNC BIT
WAIT
READ
FOR
HEADER SECTOR
WORD
MARK

140~5

~--,W.:..:.R:.:.:IT-=E...

SYNC BIT

WRITE
WRITE
WRITE
HEADER
256 WORDS
CRC
WORD (12 BIT WORDS) WORD

ERASE
DLY
25~5

85~5

DRIVE
SEEKING

IF SEEK ONLY GO TO
IDLE AND SET THE
DONE FLAG

IF NOT A HEADER
CHECK GO TO SECTOR
SEEK STATE

8[-0529

Figure 11-7 Read and Write Flow Diagram

11.4.8 Bit Counters
The Modulo 12-bit counter determines PDP-8/E data word boundaries. The Modulo 16-bit counter determines where
the HEADER and CRG character are, so that the control knows when to check the HEADER and GRG characters.

11-11

11.4.9 128- or 256-Word Counter
This register counts the output of the 12-bit counter to determine when the correct number of data words (normally
256 words) have been transferred to or from the disk. When the half block bit is set in the Command Register, the
12Sth word stops the data transfer instead of the usual 256th word.
11.5 COMPANION DOCUMENTS
The following is a list of companion documents needed to operate and maintain the R KS-E.
a.

PDP-S/E, PDP-S/F, and PDP-S/M Small Computer Handbook - DEC 1973.

PDP-S/E Maintenance Manual, Volumes I and II.

Introduction to Programming - DEC 1973 Volumes I and II.

DEC Engineering Drawings, M71 04-0-1 , M7105-0-1, and M7106-0-1.

R K05 Disk Drive Maintenance Manual (DEC-OO-R K05-DA).

11.5.1 Software
The following programs and associated documents are used in the maintenance of the R KS-E.
a.

RKS-E Diskless Control Diagnostic, MAINDEC-OS-DHRKA-A-PB or D

RKS-E Drive Control Diagnostic, MAINDEC-OS-DHRKB-A-PB or D

RKS-E Disk Formatter, MAINDEC-OS-DHRKD-A-PB or D

RKS-E Data Reliability Test, MAINDEC-OS-DHRKC-A-PB or D
NOTE
The MAINDEC number is followed by PB for papertape and D
for Document, i.e., MAINDEC-08-DHRKA-A-PB for binary
tape and MAINDEC-08-DHRKA-A-D for the diagnostic
document. The latest revision of these documents and
programs should be used to run R K8-E diagnostics.

SECTION 2 SITE PREPARATION, INSTALLATION, AND ACCEPTANCE TEST
The R KS-E is installed on site by DEC Field Service personnel. The customer should not attempt to unpack, inspect,
install, checkout, or service the equipment.
11.6 SITE PREPARATION
Adequate site planning and preparation simplifies the installation process and results in a more efficient and more
reliable R KS-E installation. DEC Sales Engineers or Field Service Engineers are available for counseling and
consultation with the user regarding the installation.
Site planning should include a list of the actual components to be used in the installation. This list should include
such items as storage cabinets, Teletype supplies, work tables, etc.

11-12

Primary requirements for installation of the RK8-E are:
a_

A Teletype, Programmer's Console, and at least 4K of read/write memory must be available to run the
R K8-E diagnostics.

Adequate space,and power must be supplied for the RK05 Disk Drives (refer to Chapter 10 of the RK05
Disk Drive Maintenance Manual for power and space requirements).

NOTE
The RK8-E receives +5V, 3A of power from the OMNIBUS.

R K8-E diagnostics and documents must be available to checkout the R K8-E and R K05 (Paragraph 11.5).

Software to format R K05 disk cartridges must be available (Paragraph 11.5).

11.7 INSTALLATION
Perform the following steps to install the RK8-E:

Step

Procedure
Unpack and inspect RK05, using the RK05 Disk Drive Maintenance Manual, Volume 2,
Paragraph 2.1, RK05 Field Installation and Acceptance Procedure.

Using the inventory list shipped with the equipment, verify all items have been received.

Ensure that PDP-8/E power is turned off.

Ensure correct jumpers are installed to select the device code assigned to this R K8-E. The
M7104 is normally shipped with the 674X device code selected, but 675X through 677X
device codes may be used (Table 11-3).

Install jumpers to select priority assigned to this R K8-E (Table 11-4).

Connect the 7009026 cable to the Berg connector on the M7106 module.

Insert the RK8-E modules into the OMNIBUS (Figure 11-S)_ Refer to Table 11-5 in Volume
I of the PDP-8/E Maintenance Manual for module installation priority.

Install HS51 Top Connectors between the modules (Figure 11-S).

11.B ACCEPTANCE TEST
The following diagnostics must be run in the order shown and the specified number of passes to check the RKS-E.
(Refer to the diagnostic document for instructions to run the diagnostic).
a.

RKS-E Diskless Control Diagnostic, MAINDEC-OS-DHRKA-A-PB (2 passes)

RKB-E Drive Control Diagnostic, MAINDEC-08-DHRKB-A-PB (1 pass)

RK8-E Formatter, MAINDEC-OS-DHRKD-A-PB (1 pass)

RK8-E Data Reliability Test, MAINDEC-08-DHRKC-A-PB (1 pass)
11-13

Table 11-3
Device Select Jumper Installation
Octal Code

Install following Jumpers on M7104 Module

674X

W2
W4
W6
W2
W4
W3
W2

675X

676X

W6
W2

677X

W3
Table 11-4
RKS-E Priority Selection
Priority

I nstall Jumpers

W2
W3

Priority 0 (highest)

Priority 1

HB51
EDGE
CONNECTORS

11'
M7106
CABLE
D-AD-7009026-0-0
WITH M993

CABLE
D-AD-7009026-0-0
WITH M993

M7105

PDPS/E
OMNIBUS

PDPS/E
OMNIBUS
BE-0593

Figure 11-8 RK8-E Module Installation

11-14

11.9 RK8·E INTERFACE
One 7009026 cable is used to connect the RK8·E controller to the first RK05 Disk Drive (four maximum). Note
that the RKS-E is connected to only one drive and the input to and output from the RK05 are daisy-chained to the
other three disks (the connectors on all four disk drives are connected in parallel by BC11A cables). The 7009026
cable is connected from two Berg connectors on the M7106 module to slot A07, A08, B07, or B08 on RK05 Disk
Drive located closest to the RK8·E (Tables 11·5 and 11·6). The RK8·E modules on the OMNIBUS are tied together
by H851 Top Connectors. The signals of the pins of the top connectors are shown in Tables 11·7 through 11·10.
These tables give the origin of signals on the top connectors for troubleshooting and signal monitoring.
An M930 Terminator Card must be installed in the unused interface slot of the last RK05 Disk Drive.

Table 11·5
RK8·E-RK05 Interface Cable (P2)
Connector J2
on RK8·E
Pin No.
A

Signal

Description

GND

DSK CAP EX L

The address sent to the selected disk drive was greater than
312 8 • (tow=true)

DSK SEEK FAI L

Disk failed to seek the address specified

GND

DSK ACKNOWLEDGE L

GND

DSKSEC 2 L

GND

DSK DRIVE 3 L

GND

DSK RESTORE L

GND

DSK DRIVE 2 L

GND

DSK CYL ADD 4 L

GND

Disk has received and acknowledged the disk address

Disk sector address bit 1 (tow=l)

Select disk drive 3 (tow=true)

Recalibrate the selected disk drive (tow=true)

Select disk drive 2 (tow=true)

Disk cylinder address bit 2 (Iow= 1)

11·15

Table 11-5 (Cont)
RKS-E-RK05 Interface Cable (P2)
Connector J2
on RKS-E
Pin No.

Signal

DSK DRIVE 1 L

GND

DSK eYL ADD 1 L

GND

DSK DRIVE 0 L

GND

DSK eYL ADD 32 L

GND

DSK RDY S/R/W L

GND

DSK eYL ADD 128 L

GND

DSK WRT eLK
DATA L

GND

DSK eYL ADD 16 L

GND

DSK eYL ADD 64 L

GND

DSK eYL ADD 2 L

GND

DSK eYL ADD 8 L

GND

Description
Select disk drive 1 (low=true)

Disk cylinder address bit 0 (low=1)

Select disk drive 0 (low=true)

Disk cylinder address bit 5 (low=1)

Selected disk drive ready to read, write, or seek

Disk cylinder address bit 7 (low=1)

Disk write clock data (low=true)

Disk cylinder address bit 4 (low=1)

Disk cylinder address 6 (low=1)

Disk cylinder address bit 1 (low= 1)

Disk cylinder address bit 3 (low=1)

11-16

Table 11-6
RKS-E-RK05 Interface Cable (P1)
Connector J1
on RKS-E
Pin No.

Signal

Not used

GND

DSK DATA IN L

GND

DSK RD CLK L

GND

DSK WRT PROTECT L

GND

DSK READ L

GND

Not used

GND

DSK WRT STATUS L

GND

DSK SECTOR MK L

GND

DISK FI LE RDY L

GND

DSK HEAD SEL 1

Description

Serial Data from the disk drive

Clock pulses from the selected disk drive during a read
operation

Disk write protect (low=true). The selected disk drive does
not write if this signal is true

Disk read (low=true) causes the selected disk drive to read

Disk Write Status L (low=true, Disk OK)

Disk sector mark (low=true) from the selected disk drive

The selected disk drive is ready to read or write data
(low=true)

Disk head select bit; when this bit is a 1, the lower or 1
surface of the disk cartridge is selected

11-17

Table 11-6 (Cont)
RKS-E-RK05 Interface Cable (P1)
Connector J1
on RKS-E
Pin No.

Signal

GND

DSK INDEX MK L

GND

DSK WRT ERASE
GATE L

GND

DSK SEC 1 L

GND

DSKSEC4 L

GND

Not used

GND

DSK SEC 8 L

GND

Not used

GND

DSK STROBE L

GND

Not used

GND

Not used

Description

Disk index mark (low=true) from the selected disk drive

Disk write erase gate (low=true)

Disk sector address bit 0 (low=1) from the selected disk
drive

Disk address bit 2 (low=1) from the selected disk drive

Disk sector address bit 3 (low=1) from the selected disk
drive

Disk strobe enables the disk to receive disk address

11-18

Table 11-7
M7104 Top Connector Signal List
Signal

Pin No.

Origin

Description

12TH BIT OK H

HMl

M7106

Output of the divide by 12 counter each time 12 bits
are read or written

6RK3 OK H

HSl

M7104

6RK3 (DLAG) load disk address and go if RK8-E is
in the IDLE state

6RK3 OK L

HS2

M7104

Same as 6R K3 H except low is true

6RK4 L

JS2

M7104

6RK4 (DLCA) load Current Address Register

6RK6 H

HRl

M7104

6RK6 (DLDC) load Command Register

6RK7 H

JCl

M7104

6RK7 (DMAN) maintenance instruction

6RK7 OK H

HN2

M7104

6RK7(DMAN) OK asserted only at TP3 time

WRT BRK L

HHl

M7105

Write break request (use DBl for data transfer)

READ BRK L

HL2

M7105

Read break request (use DB4 for data transfer)

B DATA 10 H

JA2

M7104

Buffered data bus bit 10 (high=true) (1)

B DATA 10 L

JP2

M7104

Buffered data bus bit 10 (low=true) (1)

B DATA 11 H

JRl

M7104

Buffered data bus bit 11 (low=true) (1)

BDATA11L

JHl

M7104

Buffered data bus bit 11 (low=true) (1)

BRK DIR (0) H

HP2

M7105

Controls state of MD DIR L on the OMNIBUS

BTP30K H

HKl

M7104

Asserted at TP3 time if the RK8-E is in the IDLE
state for timing

CLR DRV CMD L

JC2

M7104

Clear commands to the selected disk drive (see DCLR
instruction and Table 11-11)

CLR ALL H

HDl

M7104

Clear all logic (see DCLR instruction and Table
11-11)

CLR ALL L

JU2

M7104

Same as CLR ALL H except low=true

DRV REVO H

JD2

RK05

Disk has read an index mark

DSK CAPACITY EX L

JKl

RK05

Disk capacity exceeded, a cylinder address greater
than 312s was sent to the disk drive

DSK FI LE RDY L

HEl

RK05

Selected disk drive is ready

11-19

Table 11-7 (Cont)
M7104 Top Connector Signal List
Signal

Pin No.

Origin

DSK WRT STATUS

JD2

RK05

Selected disk drive is in a write status

SET IDLE PL L

JJl

M7104

Set the IDLE state flip-flop

ENAB INT H

JBl

M7105

Enable the interrupt logic (see Table 3-2)

ENAB SEEK DONE H

JSl

M7105

Enable seek done if bit 3 in the Command Register is
set

END STATE (0) H

JJ2

M7106

The RKS-E is in the END state

ERROR CLR L

JDl

M7104

Clear the ERROR flip-flop

HI RDCLKH

JMl

M7105

Maintenance clock or clock from the disk during a
read

HI DATA IN H

JR2

M7105

Maintenance data or data from the disk during a read

IDLE (0) H

JNl

M7106

R KS-E is not in I DLE state when this signal is 0
(high)

IDLE (1) H

JL2

M7106

RKS-E is in IDLE state when this signal is 1 (high)

LAST WORD PL H

JN2

M7106

Output of the word counter each time 256 words are
read or written

LD CMD REG H

JPl

M7105

Load Command Register asserted by 6RK6 (DLDC at
TP3 time)

LO MAIN DATA H

HV2

M7105

Load main data

LO MAIN SHFT L

HPl

M7105

Shift main data

MAIN (0) H

JEl

M7105

Clear side of MAl N enable flip-flop. This signal is true
when the MAIN flip-flop is cleared (normal
operations)

MAIN (1) H

HA2

M7105

Set side of MAl N flip-flop. This signal is true when
the MAIN flip-flop is set to enable maintenance
operations

BDATAOl H

HT2

M7104

Buffered data bus bit 1

NOT EQUAL (0) H

JF2

M7105

The cylinder address sent to the disk and the cylinder
address read after seek is complete are not equal

Description

11-20

Table 11·7 (Cont)
M7104 Top Connector Signal List
Signal

Pin No.

Origin

RDY S/RIW L

HU1

RK05

Selected disk drive ready to seek, read, or write

BTP2 H

HC2

M7104

Buffered time pulse 2

SECTOR SEEK (0) H

JF1

M7106

RKS·E is in sector seek state if sector seek (O) is true
high

SEEK FAIL H

HU2

RK05

Selected disk drive failed to seek

MAIN PL H

HT1

M7105

See maintenance instruction and Table 11·14

DATA ENABLE (1) H

HN1

M7105

Enable gate to apply MA and EMA bits to the
OMNIBUS

DATA STATE (a) H

JM2

M7106

The RKS-E is not in data state when this signal is high

Description

(0)

B DATA STATE (1) H

HL1

M7106

The RKS·E is in the data state when this signal is high
(1 )

DB CONT 1 (OJ H

HV1

M7106

Data buffer 1 control

DB CONT 4 (1) H

HE2

M7104

Data buffer 4 control

DEVICE RK H

JA1

M7104

If device RK is high (true), the RKS·E is selected for
this operation

B TP3 H

JT1

M7104

Buffered time pulse 3

DRIVE STATUS BAD H

JH2

RK05

Selected disk drive not operational (Table 11-12)

WRITE (1) H

HM2

M7106

WRITE function is (1) high when a write operation is
selected

WRTCMD L

JE2

M7106

WRT command to the disk during a write operation

WT BUFF TO DATA L

HD2

M7104

Transfer DB4 to the data lines (used during
maintenance operations to transfer contents of DB4
to the AC)

RKDATA11H

HF1

M7104

Disk data bit 11

LD DISK ADDRESS H

JB2

M7106

Load Disk Address Register when asserted by 6R K3

SHFT WRT BUFF L

HR2

M7106

Shift write buffer (DB4)

AC7 (OJ H

HB1

M7104

Bit 7 from the AC

11-21

Table 11-7 (Cont)
M7104 Top Connector Signal List
Signal

Pin No.

Origin

RDY S/R/W SLO H

JLl

RK05

Selected disk drive ready to seek, read, or write

BRK RO H

HAl

M7105

Break request

B BRK RO H

HB2

M7104

Buffered break request

MAK (0) H

HJl

M7105

Data BRK ROST accepted (RKS-E has priority)

DATACLKOK H

HCl

M7106

Data clock OK

Description

11-22

Table 11·8
M7105 to M7104 Top Connector Signal List
Signal

Pin No.

Origin

Description

12TH BIT OK H

HM1

M7106

Output of divide by 12 counter each time 12 bits are
read or written

6RK30K H

HS1

M7104

6RK3 (DLAG) load disk address and go if RK8·E is
in the IDLE state

6RK3 OK L

HS2

M7104

Same as 6RK3 H except low=true

6RK4 L

JS2

M7104

6RK4 (DLCA) Load Current Address Register

6RK6 H

HR1

M7l04

6RK6 (DLDC) load command address

6RK7 H

JCl

M7l04

6RK7 (DMAN) maintenance

6RK7 OK H

HN2

M7l04

Same as 6RK7 except it is enabled at TP3 time

WRT BRK L

HHl

M7l05

Write break request (use DBl for data transfer)

READ BRK L

HL2

M7l05

Read break request (use DB4 for data transfer)

BDATA10H

JA2

M7104

Buffered data bus bit 10 (high=true)

B DATA 10 L

JP2

M7104

Buffered data bus bit 10 (Iow=true)

B DATA 11 H

JR1

M7104

Buffered data bus bit 11 (high=true)

B DATA 11 L

JH1

M7104

Buffered data bus bit 11 (low=true)

BRK DIR (0) H

HP2

M7105

Controls MD DIR L on the OMNIBUS

B TP3 OK H

HK1

M7104

Buffered time pulse 3

CLR DRIVE CMD L

JC2

M7104

Clear selected disk drive (DCLD)

CLR ALL H

HD1

M7104

Clear all logic (see DCLR instruction and Table
11-11)

CLR ALL L '

JU2

M7105

Same as clear all H except low=true

ENABLE DATA (1) H

HN1

M7105

Enable gates to apply MA and EMA bits to the
OMNIBUS

DATA STATE (0) H

JM2

M7106

The RK8·E is in the DATA state (data transfers are
enabled)

B DATA STATE (1) H

HL1

M7106

Buffered DATA state

11·23

Table 11-8 (Cont)
M7105 to M7104 Top Connector Signal List
Signal

Pin No.

Origin

DB CONT 1 (0) H

HVl

M7104

Data buffer 1 control

DB CONT 4 (1) H

HE2

M7104

Data buffer 4 control

DEVICE RK H

JAl

M7104

If device R K is high (true), the R K8·E is selected for
this operation

B TP3 H

JTl

M7104

Buffered time pulse 3

DRIVE STATUS BAD H

JH2

M7105

The selected disk drive is not ready (Table 11·12 bit
10)

WRITE (1) H

HM2

M7106

The write function is selected

WRTCMD L

JE2

M7106

Write command to selected disk drive

WT BUFF TO DATA L

HD2

M7104

Transfer contents of write buffer (DB4) to the Data
lines

RK DATA 11 H

HFl

M7104

Disk data bit 11 (serial data to disk)

LD DISK ADDRESS H

JB2

M7106

Load Disk Address Register when asserted by 6R K3

SHFT WRT BUFF L

HR2

M7106

Shift the Write Buffer out to the disk drive

AC7 (0) H

HBl

M7104

Bit 7 from the AC

ROY S/R/W H

JLl

M7105

Selected disk drive ready to seek, read, or write

BRK RO H

HAl

M7105

Break request

B BRK RO H

HB2

M7105

Buffered break request

MAK (0) H

HJl

M7105

Data BRK ROST has been accepted (RK8·E has
highest priority)

DATA CLK OK H

HCl

M7106

DATA clock OK

DRV REVO H

JK2

M7106

Disk index mark is applied to RK8·E during IDLE
state

DSK CAPACITY EX L

JKl

RK05

Disk capacity exceeded, address greater than 3128
sent to the disk drive

DSK FILE ROY L

HEl

RK05

Selected disk drive is ready (on·line)

DSK WRT STATUS L

JD2

RK05

Disk drive write status (low=true)

Description

11 ·24

Table 11-8 (Cont)
M7105 to M7104 Top Connector Signal List
Signal

Pin No.

Origin

SET IDLE PL L

JJ1

M7104

Set IDLE state flip-flop

ENAB INT H

JB1

M7105

Enable interrupt logic (Table 11-12)

ENAB SEEK DONE H

JS1

M7105

Enable seek done if bit 3 in Command Register is set

END STATE (0) H

JJ2

M7106

RK8-E in the END state when asserted

ERROR CLR L

JD1

M7104

Clear the ERROR flip-flop

HIRDCLKH

JM1

M7105

Main clock OR clock from the disk during a read

HI DATA IN H

JR2

M7105

Serial DATA from the disk drive during a read

IDLE (0) H

JN1

M7106

RK8-E is not in the IDLE state when this signal is
high

IDLE(l)H

JL2

M7106

RK8-E is in the IDLE state when this signal is 1
(high)

LAST WORD PL H

JN2

M7106

Output of word counter each time 256 words are
read or written

LD CMD REG H

JP1

M7106

Load Command Register (DLDC)

La MAIN DATA H

HV2

M7105

Maintenance data (Table 11-14)

La MAIN SHFT L

HP1

M7105

Maintenance shift pulse (Table 11-14)

MAIN (0) H

JEl

M7105

Maintenance command (DMAN instruction)

MAIN (1) H

HA2

M7105

Maintenance command (DMAN instruction)

BDATA01H

HT2

M7104

Buffered data bit 2

NOT EQUAL (0) H

JF2

M7105

The cylinder address sent to the disk and the cylinder
address read after seek is complete are not equal

RDY S/RIW L

HUl

RK05

Selected disk drive ready to seek, read, or write

B TP2 H

HC2

M7104

Buffered time pulse 2

SECTOR SEEK (0) H

JF1

M7106

R K8-E is in sector seek state if sector seek (0) is true
high

SEEK FAIL H

HU2

RK05

Selected disk drive failed to seek

MAIN PL H

HT1

M7105

See maintenance instruction and Table 11-14

Description

11-25

Table 11·9
M7105 to M7106 Top Connector Signal List
Signal

Pin No.

Origin

Description

12TH BIT OK H

FA1

M7106

Output of divide by 12 counter each time 12 bits are
read or written

6RK3 OK H

FA2

M7104

6RK3 (DLAG) load disk address and go if RK8·E is
in IDLE state

B DATA 7 H

ER2

M7104

Buffered data bit 7 (high=true) (1)

B DATA 10 H

EK1

M7104

Buffered data bit 10 (high=true) (1)

B DATA 11 H

EJ1

M7104

Buffered data bit 11 (high=true) (1)

CLR DRIVE CMD L

FB2

M7104

Clear commands to the selected drive

CLR ALL L

EH1

M7104

Clear all logic (see the DCLR instruction and Table
11·11)

DATA STATE (0) H

FP1

M7106

Data state (read or write data)

B TP3 H

FJ1

M7104

Buffered time pulse 3

DRV REVO H

FC2

M7106

Disk index mark is applied to the RK8·E during IDLE
state

DSK FI LE RDY L

FB1

RK05

Selected disk drive is operational

DSK WRT STATUS L

FD2

RK05

Selected disk drive is in a write status (low=true)

SET IDLE PL L

FK1

M7104

Set the IDLE state flip·flop

END STATE (0) H

FD1

M7106

END state (true=O)

ERROR CLR L

FE2

M7104

Clear the ERROR flip·flop

IDLE (0) H

FR2

M7106

The RK8·E is not in the IDLE state when this signal
is (0) high

IDLE (1) H

EC1

M7106

The RK8·E is in the IDLE state when this signal is (1)
high

LAST WORD PL H

FE1

M7106

LAST WOR D is asserted when 256 words are read or
written

MAIN (0) H

FP2

M7105

Clear side of MAl N flip·flop. This signal is true when
the RK8·E is not in the maintenance mode

RDY S/R/W H

ED1

M7105

Selected disk drive is ready to seek, read, or write

11·26

Table 11-9 (Cont)
M7105 to M7104 Top Connector Signal List
Signal

Pin No.

Origin

Description

DATA ENABLE (1) H

EU1

M7105

Enable gates to apply MA and EMA bits to the
OMNIBUS

SECTOR SEEK (0) H

FF2

M7106

The RKS-E is in the sector seek state if SECTOR
SEEK is true (high)

LAST BRK (1) H

FN2

M7105

last break (1=true) ends data transfer operations

WRITE (1) H

FF1

M7106

The write function is selected by the program

WRTCMD l

FV2

M7106

Write command to the R K05

BTP2 H

FH2

M7104

Buffered time pulse 2

B DATAS H

EM1

M7104

Buffered data bus bit S

BDATA9H

EL1

M7104

Buffered data bus bit 9

BRK ENABLE ClK H

FK2

M7106

Break enable clock pulse

BRK IN ClK H

FU2

M7106

Break in clock pulse

CLR CNTRS l

FS1

M7106

Clear counters asserted by CLR All, DATA CLR. or
HEADER E during STATE ENABLE

ClR SECTOR AD l

EF1

M7105

Clear Sector Address Register

CRC 16 (1) H

EN2

M7105

CRC Register bit 16

CRC DATA H

EA1

M7106

Serial CRC data

DATA IN (0) H

FR1

M7106

Serial data from the disk during a read

RD ClK (1) H

EB1

M7105

Read clock from the disk during a read

RD SHFT DB L

FS2

M7106

Shift Data Buffer during read operations

SECTOR ADDR 01 H

EP2

M7105

Sector address bit 0 high

SHFT SURF SEC H

FU1

M7105

Shift Surface Sector Register

ENAB DATA L

EV1

M7105

Enable data to the buffers

SHFT CRC L

FN1

M7106

Shift CRC out to the disk drive

FILE ROY H

EE1

RK05

Selected disk drive is READY

11-27

Table 11·9 (Cont)
M7105 to M7104 Top Connector Signal List
Signal

Pin No.

Origin

STROBE (1) H

EF2

M7106

Asserted when file is ready and GO bit is set (1)

FUNCTION 00 H

EU2

M7106

Function bit 00

)

Description

FUNCTION 01 H

EV2

M7106

Function bit 01

) Select disk drive
) operation, i.e., read

FUNCTION 02 H

ET2

M7106

Function bit 02

)

HALF BLOCK H

ES2

M7105

Transfer 128 words instead of 256

DATACLK OK H

FMl

M7106

Data clock OK

LO MAIN SHFT L

FL 1

M7106

Maintenance shift

DSK DRIVE 2 L

EPl

M7105

Select disk drive 2 when low (true)

DSK DRIVE 3 L

ENl

M7105

Select disk drive 3 (low=true)

DSK CYL AD 128 L

EE2

M7106

Disk cylinder address bit 7 (MSB)

DSK CYL AD 64 L

EB2

M7106

Disk cylinder address bit 6

DSK CYL AD 32 L

EJ2

M7106

Disk cylinder address bit 5

DSK CYL AD 16 L

EC2

M7106

Disk cylinder address bit 4

DSK CYL AD 8 L

ETl

M7106

Disk cylinder address bit 3

DSK CYL AD 4 L

EH2

M7106

Disk cylinder address bit 2

DSK CYL AD 2 L

EK2

M7106

Disk cylinder address bit 1

DSK CYL AD 1 L

ES1

M7106

Disk cylinder address bit 0 (LSB)

DSK CAPACITY EX L

FC1

RK05

Disk capacity exceeded, address sent to the disk
greater than 3128

HI MAIN SHIFT L

FT2

M7106

Maintenance shift pulse

BLAST BRK H

FL2

M7106

Buffered last break

LD DSK ADDRS H

EM2

M7106

Load Disk Address Register when asserted by 6RK3

RK DATA 11 H

FHl

M7105

Disk data bit 11

B TP3 OK H

FM2

M7104

Asserted during TP3 time of the I DLE state only for
timing and execution of instructions

)

11-28

Table 11·9 (Cont)
M7105 to M7104 Top Connector Signal List
Signal

Pin No.

Origin

SHFT WRT BUFF L

FJ2

M7104

Shift write buffer (DB4)

STATE ENABLE B H

FVl

M7106

Buffered STATE ENABLE

DSK RDY S/R/W L

EL2

RK05

Selected disk drive ready to seek, read, or write

DSK SEEK FAI L L

EA2

RK05

The seek operation on the selected disk drive failed

DSK DRIVE 0 L

ED2

M7105

Select disk drive 0 when low (true)

DSK DRIVE 1 L

ER1

M7105

Select disk drive 1 when low (true)

11-29

Description

Table 11-10
M7106 Top Connector Signal List
Signal

Pin No_

Origin

Description

12TH BIT OK H

FAl

M7106

Output of divide by 12 counter each time 12 bits are
read or written

6RK3 OK H

FA2

M7104

6RK3 (DLAG) load disk address and go

B DATA 7 H

ER2

M7104

Buffered data bus bit 7 (high=true)

B DATA 10 H

EKl

M7104

Buffered data bus bit 10 (high=true)

B DATA 11 H

EJl

M7104

Buffered data bus bit 11 (high=true)

CLR DRIVE CMD L

FB2

M7104

Clear commands to the selected disk drive clear all
logic (see the DCLR instruction and Table 11-11)

CLR ALL L

EHl

M7104

Clear all logic on the RKS-E

DATA STATE (0) H

FPl

M7106

Data state (read or write data)

B TP3 H

FJl

M7104

Buffered time pulse 3

DRV REVO H

FC2

M7106

Disk INDEX MARK is applied to the RKS-E during
the IDLE state

DSK FILE RDY L

FBl

RK05

Selected disk drive is operational

DSK WRT STATUS L

FD2

RK05

Selected disk drive is in a write status Oow=true)

SET IDLE PL L

FKl

M7104

Set the IDLE state flip-flop

END STATE (0) H

FDl

M7106

The RKS-E is in the END state

ERROR CLR L

FE2

M7104

Clear the ERROR flip-flops

IDLE (0) H

FR2

M7106

RKS-E is not in the IDLE state when this signal is
high

IDLE(l)H

ECl

M7106

RKS-E is in the IDLE state when this signal is high

LAST WORD PL H

FEl

M7106

Output of the word counter each time 256 words are
read and written

MAIN (0) H

FP2

M7105

Clear side of MAIN flip-flop. The RKS-E is not in the
maintenance mode when this signal is high

RDY S/R/W H

EDl

RK05

Selected disk drive ready to seek, read, or write

DATE ENABLE (1) H

EUl

M7105

Enables MA and EMA bits to be applied to the
OMNIBUS during a data break

11-30

Table 11-10 (Cont)
M7106 Top Connector Signal List
Signal

Pin No.

Origin

SECTOR SEEK (0) H

FF2

M7106

Sector seek state

LAST BRK (1)

FN2

M7105

Last break

WRITE (1) H

FF1

M7106

The Write function is selected

WRT CMD L

FV2

M7106

Write command

HI MAIN SHFT L

FT2

M7105

Maintenance shift (OMAN pulse)

BLAST BRK H

FL2

M7106

Buffered last break

LD DISK ADDRS H

EM2

M7106

Load disk address

RK DATA 11 H

FH1

M7104

Data bit 11 from the disk

B TP3 OK

FM2

M7104

Buffered time pulse 3 OK

SHFT WRT BUFF L

FJ2

M7104

Shift Write Buffer (DB4)

STATE ENAB B H

FV1

M7106

State enable

DSK ROY S/RIW L

EL2

RK05

Selected disk drive ready to seek, read, or write

DISK SEEK FAI L L

EA2

RK05

The selected disk did not complete a seek operation
(Table 11-12)

DSK DRIVE 0 L

ED2

M7105

Select disk drive 0 when low (true)

DSK DRIVE 1 L

ER1

M7105

Select disk drive 1 when low (true)

DSK DRIVE 2 L

EP1

M7105

Select disk drive 2 when low (true)

DSK DRIVE 3 L

EN1

M7105

Select disk drive 3 when low (true)

DSK CYL AD 128 L

EE2

M7106

Disk cylinder address bit 7

DSK CYL AD 64 L

EB2

M7106

Disk cylinder address bit 6

DSK CYL AD 32 L

EJ2

M7106

Disk cylinder address bit 5

DSK CYL AD 16 L

EC2

M7106

Disk cylinder address bit 4

DSKCYL AD 8 L

ET1

M7106

Disk cylinder address bit 3

DSKCYLAD4 L

EH2

M7106

Disk cylinder address bit 2

11-31

Description

Table 11-10 (Cont)
M7106 Top Connector Signal List
Signal

Pin No.

Origin

DSKCYlAD2 l

EK2

M7106

Disk cylinder address bit 1

DSK CYlAD 1 l

ES1

M7106

Disk cylinder address bit 0

DSK CAPACITY EX l

FC1

RK05

Disk capacity exceeded, cylinder address greater than
312 8

DATAClKOKH

FMl

M7106

Data clock OK during DATA state only

lO MAIN SHIFT l

Fll

M7105

Main shift (DMAN pulse)

BTP2 H

FH2

OMNIBUS

Buffered time pulse 2

B DATA 8 H

EMl

M7104

Buffered data bus bit 8

B DATA 9 H

EL1

M7104

Buffered data bus bit 9

BRK ENABLE ClK H

FK2

M7106

Break enable clock

BRK IN ClK H

FU2

M7106

BREAK IN clock

ClR CNTRS l

FSl

M7106

Clear counters asserted by ClR All, DATA ClR, or
HEADER E during STATE ENABLE

ClR SECTOR AD l

EFl

M7105

Clear Sector Address Register

CRC 16 (1) H

EN2

M7105

CRC Register bit 16

CRC DATA H

EAl

M7106

Serial CRC DATA

DATA IN (0) H

FRl

M7106

DATAl N from the disk

RD ClK (1) H

EBl

M7105

Read clock from the disk

RDSHFT DB l

FS2

M7106

Shift Read Data Buffer (Dll)

SECTOR ADDR 01 H

EP2

M7105

Sector address bit 0

SHFT SURF SEC H

FUl

M7105

Shift Surface Sector Register

ENAB DATA l

EVl

M7105

Enable data to the buffers

SHFTCRC l

FNl

M7106

Shift CRC Register

FILE RDY H

EEl

RK05

Selected disk drive is READY

Description

11-32

Table 11-10 (Cont)
M7106 Top Connector Signal List
Signal

Pin No.

Origin

STROBE (1) H

EF2

M7106

Asserted when file is ready and GO bit is set (1)

FUNCTION 00 H

EU2

M7106

Function bit 00

)

FUNCTION 01 H

EV2

M7106

Function bit 01

) Select disk drive
) operation, i.e., read

FUNCTION 02 H

ET2

M7106

Function bit 02

)
)

HALF BLOCK H

FS2

M7106

Transfer 128 words instead of 256

11-33

Description

SECTION 3 OPERATION AND PROGRAMMING
11.10 SINGLE CYCLE DATA BREAK DESCRIPTION
All data transfers between the RK8·E and memory are via the single cycle data break interface. The concepts of data
transfers and interrelationships of the data break interface and peripherals are explained in Chapter 10 of the Small
Computer Handbook 1973. A detailed description of the data break interface (KD8-E) is explained in Chapter 10,
Volume II of the PDP-B/E Maintenance Manual. The data break interface option operation is identical to the single
cycle data break control logic used in the RK8-E.
11.11

INSTRUCTIONS AND STATUS BITS

The following are used to program the RK8-E.
Skip on Disk DONE or ERROR flag (DSKP)
Octal Code:

6741

Operation:

Skip the next instruction if the TRANSFER DONE or ERROR flag is set.

Clear All (DCLR)
Octal Code:

6742

Operation:

Transfer bits 10 and 11 from the AC to the clear logic in the RK8-E (see Table 11-11) and clear
the AC.

Table 11-11
Clear Operations Using the DCLR Instruction
AC
Bit 10

AC
Bit 11

Operation
DCLS; clear tha AC and Status Register. This bit combination is normally used to clear
program interrupts.
DClC; clears the AC and all RK8-E control logic but does not clear the selected RK05
control logic. This bit combination is used only to simulate a power clear or if the
controller does not respond to normal commands. Note this instruction stops the
control even if it is rewriting a HEADER word; it should be used with care. The Status
Register contains all zeroes after the DClR instruction is executed with this bit
combination in the AC.

DClD; clears the AC and recalibrates the selected drive by forcing it to cylinder 000
(home position). This bit combination is used to recover from cylinder address errors
and select errors.
Accomplishes same operation as 0 O.

11-34

CAUTION
The following programming sequence should be used to
recalibrate the selected disk drive with a DCLR instruction.

DCLR with AC 0000

Clears Status Register and AC

STL

Set AC LINK bit to 1

RTL

Rotate AC and LINK left two. One in the LINK goes to AC bit 10 position

DCLR with AC 0010

The selected drive is recalibrated as explained in Table 11·11

DSKP

The program skips an instruction when the TRANSFER DONE flag is set
when the read/write heads are at the cylinder 000

JMP·1

DCLR with AC 0000

Clears Status Register and the AC

DSKP

Skip on TRANSFER DONE

JMp·1

Recalibrate procedure is finished. Read/write heads are at cylinder 000 (home
position) and the AC is cleared

Load Address and GO (DLAG)
Octal Code:

6743

Operation:

Transfer the contents of the AC to the Disk Address Register, clear the AC, and enable the
command in the Command Register to be executed. The Disk Address Register specifies one of 16
sectors, one of 2 surfaces, and one of 203 cylinders. The AC must be loaded with the disk address
before this instruction is executed. In a normal read or write operation, the following occurs:

The selected drive seeks the track specified by AC bits 0 through 6 and bit 11 in the Command Register.

When the selected drive signals it has completed a SEEK, the HEADER word is checked on the first
sector to pass under the read/write heads.

If the track specified checks with the HEADER word (read/write heads are on the right cylinder), the
control waits for the next sector pulse.

The control reads the sector address of each sector passing under the read/write heads and when the
correct sector is found a read or write operation is performed.

11-35

Load Current Address (DLCA)
Octal Code:

6744

Operation:

Transfer the contents of the AC to the Current Address Register and clear the AC. The contents of
the Current Address Register along with the EMA bits in the Command Register are applied to the
OMNI BUS MA and EMA lines to select a location in memory for a data transfer. Note that the AC
must be loaded with the address of the first memory location used in a data transfer.

Read Status Register (DRST)
Octal Code:

6745

Operation:

Clear the AC and transfer the contents of the Status Register to the AC (Table 11-12).

Table 11-12
Contents of Status Register
Bit

Indication
TRANSFER DONE is set (1).
a.

At the end of a data transfer

When an ERROR occurs while the controller is executing an operation

When the selected drive completes a seek only operation

When the selected drive completes a recalibrate operation if bit 4 in the Command Register is
set
NOTE
The TRANSFER DONE flag causes a program to interrupt if
bit 3 in the Command Register is set.

RDYS/R/W indicates the selected disk drive heads are in motion and the selected drive is ROY to SK,
RD, or WR.

Not used.

SEEK FAIL is set (1) to indicate the selected drive failed to seek a cylinder address specified by the
program. This bit is set by DSK SEEK FAI L L from the selected drive. The recalibrate operation
must be performed to clear bit 3. If the DLAG instruction is executed by the program and bit 3 is set
(1) the ERROR flag sets.

FILE NOT READY indicates the selected drive is not ready or inoperative. This bit is set (1) if DSK
FI LE DRY L from the selected drive is high. If the DLAG instruction is executed by the program, the
ERROR flag sets if bit 4 is set (1). To clear bit 4, some action must be taken by the operator, i.e.,
power up the selected disk drive.

11-36

Table 11-12 (Cont)
Contents of Status Register
Bit

Indication

CONTROL BUSY ERROR is set (1) if the program executes the DLAG, DLCA, or DLDC
instructions while the control is BUSY (IDLE is cleared). If a CONTROL BUSY ERROR occurs, the
current operation is completed and the TRANSFER DONE flag sets at the end of the operation. This
error occurs most often when programs are debugged, and requires rewriting of the program to
eliminate the error.
CAUTION
lOT DCLR with AC bit 11 should not be used to clear a
CONTROL BUSY ERROR. If the DCLR instruction is issued
by the program, the operation is aborted even if the program is
writing a HEADER word.

TIME OUT ERROR is set (1) if the control has been busy for more than 280 ms. If TIME OUT
ERROR sets, the TRANSFER DONE flag sets. TIME OUT ERROR indicates a hardware problem
and can be cleared by the DCLR instruction.

WRITE LOCK ERROR indicates the program tried to write on a write-protected disk drive. To write
on a disk drive that has been write protected, the operator must manually clear the write lock protect
by pressing the WT PROT switch on the drive which produced the error.

CRC ERROR is set (1) if the CRC character read from the disk does not agree with the CRC
character calculated by the RK8-E as data is read from the disk. CRC ERROR sets the TRANSFER
DONE flag immediately and the operation is stopped. If a CRC ERROR occurs, a new read operation
must be initiated to reread the data; if this is not successful, the data 'must be rewritten.

DATA REQUEST LATE is set (1) if the processor does not respond to a break request within 22.5
J,ls. The 4-word Data Buffer Register is filled within 22.5 J,ls, and if one of the registers is not freed

within this time period, a DATA REQUEST LATE ERROR occurs. DATA REQUEST LATE sets the
TRANSFER DONE FLAG and stops the operation. A new operation must be initiated to transfer the
same data. Note that if the Data Buffer Register is full during a read operation, the processor must
grant a BRK RQST within 6.5 J,ls after the register is filled; or if the Data Buffer Register is empty
during a write operation, the processor must grant a BRK RQST within 6.5 J,lS after the register is
emptied. Either one of these conditions causes a DATA REQUEST LATE error. If the register is
half-filled or half-empty, the latency would be 13 J,ls.

DRIVE STATUS ERROR is set (1) when the DLAG instruction is executed by the program if:
a.

The DRIVE NOT READY for one of the following reasons:
1.

Power is not turned on

The drive does not exist (incorrect address)

The selected drive does not have a cartridge installed

The door on the selected drive is not closed (interlock open)

11-37

Table 11-12 (Cont)
Contents of Status Register
Indication

Bit

Disk is not up to speed (disk rotation less than 1500 rpm)

Load switch on the selected disk drive is in the RUN position. The TRANSFER DONE
flag is not set as a result of DRIVE NOT READY

The WRITE CHECK ERROR is set to indicate the drive has one of the following error
conditions.
1.

Erase or write current without a WRITE GATE

The head position transducer lamp is inoperative. If WRITE CHECK ERROR is set, the
WT PROT switch on the selected drive must be depressed to remove the error. WRITE
CHECK ERROR does not set the TRANSFER DONE flag.

If disk capacity is exceeded (cylinder address greater than 3128 was sent to the selected
drive), the program must select a new disk address that is less than 312 8 • The
TRANSFER DONE flag is set if the disk capacity is exceeded.

If a SEEK FAI LURE occurs in the drive, this indicates a seek was not completed because
of some disk drive malfunction. If the control is busy at the time a SEEK FAI LURE
occurs, the TRANSFER DONE flag is set and the disk drive must be recalibrated using
the recalibrate lOT DCLR with AC = 10.

CYLINDER ADDRESS ERROR is set (1) if the HEADER word of a sector does not agree with the
cylinder address sent to the drive (either the HEADER word was read wrong or the read/write heads
were positioned to the wrong address).
The TRANSFER DONE flag is set and the HEADER word is retained in the CRC Register. The
selected drive should be recalibrated using the DCLR instruction (AC = 0010), and the disk drive
should be addressed again using the DLAG instruction. The cylinder address in the CRC Register is
transferred to the AC by the maintenance instruction for the program to compare the disk address
with the cylinder address requested by the program (refer to the 6747 maintenance lOT).

Load Command Register (DLDC)
Octal Code:

6746

Operation:

Transfer the contents of the AC to the Command Register and clear the AC and Status Register.
Note the AC must be loaded with information to be transferred to the Command Register (Table
11-13 and Figure 114) before this instruction is executed. Each of the functions selected by the
Command Register are discussed in detail in Paragraph 11.11.1.

11-38

Table 11-13
Command Functions
Bit

Function

0,1,2

Bits 0, 1, and 2 of the Command Register are decoded and used to select disk operations as
follows:
Bit 0

Bit 1

Bit 2

Read Data - Seek disk address, check the HEADER, and
read one sector.
Read All - Seek disk address, do not check the HEADER,
and read one sector.

Write protect the selected drive.

Seek disk address, and if bit 4 is 1, set the TRANSFE R
DONE flag when seek is completed.

Write Data - Seek disk address, check HEADER, and write
one sector.

Write all, seek disk address, do not check the HEADER,
and write one sector.

Not used
Not used

If bit 3 is a 1, enable interrupt on ERROR flag or TRANSFER DONE.

If bit 4 is 1, set TRANSFER DONE flag when seek is complete.

If bit 5 is a 1, the controller writes or reads 128 words in a sector instead of-256. The TRANSFER
DON E flag is set at the end of a sector and the last 128 words of the sector contai ns all zeroes.

6,7,8

Bits 6, 7, al")d 8 are used to address extended memory as follows:
Bit 6

Bit 7

BitS

(EMA2)

(EMA1)

(EMAO)

0
0
0
0

0
0

0
1
0
1
0
1
0
1

1
0
0

Field 0
Field 1
Field 2
Field 3
Field 4
Field 5
Field 6
Field 7

11-39

Table 11·13 (Cont)
Command Functions
Bit

Function
These bits are not incremented and the program must reload the Command Register to select a
new memory field when the Current Address Register overflows (reads all zeroes).

9,10

Bits 9 and 10 are used to select a disk drive as follows:
Bit 9

Bit 10

0
0

0
1
0

Drive 0
Drive 1
Drive 2
Drive 3

Bit 11 is the extended cylinder address bit (Figure 11·15). It is added to the 7·bit Cylinder Address
Register to allow the program to address cylinders 00 8 to 312 8 . Note an address greater than 3128
causes an ADDRESS ERROR.

Maintenance lOT (DMAN)
Octal Code:

6747

Operation:

Transfers the contents of the AC to the RK8·E maintenance control logic. The maintenance
operation performed is determined by contents of the AC (Table 11·14); therefore, the AC must
be loaded before this instruction is executed. Table 11·14 gives the purpose of each bit, and the
operations are discussed in detail in Paragraph 11.11.2.

11.11.1 Command Functions
When the Command Register is loaded by a DLDC instruction, the operation to be performed by the RK8·E is
determined by bits 0, 1, and 2 from the AC. The following paragraphs explain each of these functions. A flow
diagram illustrating all R K8·E operations is shown in Paragraph 11.15, Figure 11-15.
11.11.1.1 Read Data - A normal read operation (Table 11-13) is initiated when all zeroes (000) are transferred
from ACO-AC2 to the Command Register by a DLDC instruction. The RK8-E and RK05 must interact to SEEK
(find the correct cylinder), check the HEADER (find the correct surface), and read serial data from the disk drive.
The serial data from the disk drive is read into Data Buffer 1 and transferred to the last empty buffer as a 12·bit
parallel word. The parallel words are eventually moved into Data Buffer 4 and transferred to memory via the single
cycle data break.
The RK8·E tries to keep the Data Buffer Register empty, by initiating single cycle data breaks, so that a register will
be empty when each new word is received from the disk drive. If data is read from the disk drive while the Data
Buffer Register is full, the DATA REQUEST LATE flag is set and the sector must be read again.
A read operation continues until 256 words have been read from the disk drive and the TRANSFER DONE flag sets.
If the half block bit is set, 256 words are read, but only the first 128 words are data words. The second 128 words
are all zeroes and are not transferred to memory.

11·40

Table 11-14
Maintenance Functions
Bit

Function
Enables maintenance logic and disables lOT DLAG (GO).
Enable a shift to lower buffer (DB4) by setting the DB4 control flip-flop.

Check CRC Register

Check Command Register

Check Surface and Sector Register

Check Data Buffer

Check Data Break Request

Transfer contents of Data Buffer 4 to the AC

Not used

Maintenance data bit

Not used

11.11.1.2 Read AII- Read All is initiated when 001 is transferred from ACO-AC2 to the Command Register by
the DLDC instruction. Read All is identical to a normal read operation except the HEADERs are not checked. This
allows a disk cartridge that has been formatted to be checked by the program to verify the HEADERs have been
written on the cartridge correctly.
11.11.1.3 Write Data-Write Data (Table 11-13) is initiated when a 100 is transferred from ACO-AC2 to the
CommClnd Register by a DLDC instruction. The RK8-E and RK05 must interact to SEEK (find the correct cylinder),
check the HEADER (find the correct sector), and write data transferred from memory to Data Buffer 1 asa 12-bit
parallel word via the single cycle data break. The 12-bit word is transferred from Data Buffer 1 to the last empty
buffer. The 12-bit word is eventually transferred into Data Buffer 4 where it is shifted out to the disk drive as a
12-bit serial word to be written on the disk cartridge.
The R K8-E tries to keep the Data Buffer Register full during a write operation so that there will always be a word
available when the drive is ready to write. If the disk drive calls for data when the Data Buffer Register is empty, the
DATA REQUEST LATE flag is set and the sector must be rewritten.
The write operation continues until 256 words have been written on the cartridge and the TRANSFER DONE flag
sets. If the half block bit is set, 128 words of data from memory are written on the disk cartridge and 128 words of
all zeroes are written on the remainder of the sector.
11.11.1.4 Write AII- Write All (Table 11-13) is initiated when a 101 is transferred from ACO-AC2 to the
Command Register by the DLDC instruction. This function is identical to the write function except the HEADERS
are not checked by the RK8-E. Write All is used to format a new disk cartridge. To format a disk cartridge, a
HEADER word must be written at the beginning of each sector. The word to be written is determined by the
program (Paragraph 11.12.1).
11-41

11.11.1.5 Write Protect - A 010 transferred from ACO-AC2 to the Command Register by a DLDC instruction
turns on the WRITE PROTECT for the selected disk drive. If the program attempts to write on a disk drive that has
WRITE PROTECT set, a WRITE LOCK ERROR occurs and stops the write operation. The only way to enable
writing on a disk drive that has been write protected is to push OFF the WRT PROT OFF switch on the drive that
was write protected.
11.11.1.6 Seek Only - When a 011 is transferred from ACO-AC2 to the Command Register by a DLDC
instruction, the selected disk drive seeks the cylinder contained in the Cylinder Address Register but does not check
the H EADE R or start a read or write operation. Cylinder (2 tracks) seek electronics are self-contained in each disk
drive so once the seek operation has been started a new disk drive can be selected. Thus, more than one disk drive
can be doing a seek operation and the control can select another disk drive for a read or write operation. If seek only
is specified and the DLAG instruction is executed by the program (this instruction starts all disk operations), the
TRANSFER DONE flag is set after lOT DLAG is executed. TRANSFER DONE is set again when the seek is
complete if bit 4 in the Command Register is set (1).
11.11.1.7 Interrupt Enable - The program interrupt system is enabled if bit 3 in the Command Register is set.
When this bit is set (1), program interrupt is initiated if the TRANSFER DONE or ERROR flags are set.
11.11.1.8 TRANSFER DONE on SEEK COMPLETE - If bit 4 in the Command Register is set (1), the
TRANSFER DONE flags set when the selected drive has completed a seek operation.
NOTE
Programming precautions must be taken when using this bit
because it is possible to select another drive just as the drive
that was previously selected completes a seek. If this happens,
the unsophisticated program thinks there is a SEEK
COMPLETE on the newly selected drive (see Paragraph
11.12.5 for information on programming around this hazard).

11.11.1.9 Read or Write Half Block (128 Words) - If bit 5 in the Command Register is set, a half block (128
words) of data is specified for a data transfer instead of the usual 256 words contained in one sector. When writing,
the first 128 words of a sector come from memory and the second 128 words are all zeroes. The TRANSFER DONE
flag is set after a complete sector (256 words) is written. When reading, the first 128 words read from the disk
cartridge are transferred to memory. The TRANSFER DONE flag is set at the end of the sector when 256 words
have been read. The delay before setting the TRANSFER DONE flag during a read or write half block operation is
to allow the generation and checking of a CRC character at the end of the sector.
11.11.1.10 Extended Memory Addressing - Bits 6, 7, and 8 of the Command Register are used to address extended
memory (Table 11·13). The extended memory address bits (EMAO-EMA2) are not incremented; thus, the
Command Register must be reloaded to select a new memory field. If the Current Address Register overflows, the
data is wrapped around in the same field. During a write operation, if data has already been written in those
locations it will be written over; also the data read from memory during a write operation is duplicated (reread).
11.11.1.11 Unit Select - Bits 9 and 10 of the Command Register are decoded to select one of four disk drives
(Table 11-13). Signals to and from a disk drive are inhibited except when the drive is selected.
11.11.1.12 Extended Cylinder Address- Bit 11 of the Command Register is an extension of the 7-bit
Cylinder/Surface/Sector Address Register (Figure 11-4). The maximum number of usable cylinders is decimal 203,
designated as 00 10 to 202 10 or 00 8 to 312 8 • When the program specifies a cylinder address greater than 312 8 , the
CYLINDER ADDRESS ERROR flip-flop is set.

11-42

11.11.2 Maintenance Functions
The maintenance lOT 6747 (DMAN) ANDed with the contents of the AC allows program access to the major
registers in the R K8-E. The maintenance instruction transfers data to the major registers (i.e., Data Buffer Register)
or reads the contents of the registers into the AC or memory. Data can also be transferred to or from memory using
the maintenance lOT. A DClC instruction (clear control) must be used when changing from read to write or write
to read.
The major registers are described in Paragraph 11.4. Note that the CRC Register is a multipurpose register that
contains the cylinder address loaded from the AC and the cylinder address that is written or read as a HEADER
word. This register also calculates the CRC character. The CRC Register also contains the CRC character read from
the disk drive to be compared with the CRC that has been calculated. When the CRC Register is used as the Cylinder
Address Register, bits 1-3 and 12-16 are zeroes and bits 4-11 contains the cylinder address.
The contents of the CRC, Command, and Surface/Sector Register must be shifted into Data Buffer 4 before they
can be transferred to the AC or memory. These operations are explained in the following paragraphs.
11.11.2.1 Maintenance Mode - If the DMAN instruction is executed and ACOO is a 1, the controller is in the
maintenance mode, the maintenance functions are enabled, and the DlAG (GO) lOT is disabled. The maintenance
control bit is cleared by the clear control lOT (DClC).
NOTE
Maintenance functions cannot be microprogrammed.

11.11.2.2 Shift Enable - If AC bit 01 is set when lOT DMAN is executed by the program, the lower Data Buffer
(DB4) control flip-flop sets to enable a shift to the lower buffer.
11.11.2.3 Check CRC Register - When AC bit 02 is a 1 and the DMAN lOT is executed by the program, AC bit 10,
the CRC Register, and Data Buffer 4 are logically connected as a 29-bit shift register that is shifted one position with
each DMAN lOT. AC bit 10 shifts into the CRC and the CRC shifts into Data Buffer 4.
The program must count the bits shifted to determine when to read Data Buffer 4. AC bit 02 does not set a control
bit so a clear is not necessary.
11.11.2.4 Check Command Register - When AC bit 03 is set and the DMAN lOT is executed by the program, the
Command Register and Data Buffer 4 are logically connected as a 24-bit shift register that is shifted one position
with each DMAN lOT. The program must count the bits shifted to determine when to read Data Buffer 4. AC bit 03
does not set a control bit so a clear is not necessary.
11.11.2.5 Check Surface/Sector Register - When AC bit 04 is 1 and the DMAN lOT is executed by the program,
the surface bit, the Sector Register, and Data Buffer 4 are logically connected as a 17-bit shift register that is shifted
one position with each DMAN lOT. The surface bit shifts into the Sector Register and the Sector Register shifts into
Data Buffer 4.
The program must count the bits shifted to determine when to read the lower Data Buffer. AC bit 04 does not set a
control bit so a clear is not necessary.
11.11.2.6 Check Data Buffer - When AC bit 05 is a 1 and the DMAN lOT is executed by the program, AC bit 10
and Data Buffer 1 are connected logically as a 13-bit shift register that is shifted one position with each DMAN lOT.
In addition, the bit counter and word counter are incremented. The word counter is incremented by the overflow of
the 12-bit counter.

11-43

After 12 shifts, the 12-bit counter overflows setting a control bit indicating that the upper Data Buffer 1 is full. The
contents of Data Buffer 1 transfers to Data Buffer 4 which is read into memory. After 4 words if Data Buffer 4 is
not read, and another bit is shifted into Data Buffer 1, the DATA REQUEST lATE ERROR flag is set. If Data
Buffer 4 is read either into the AC or memory, information transfers into the buffer filling Data Buffer 4 and
emptying Data Buffer 1. When the word counter overflows after 256 transfers, the TRANSFER DONE flag sets.
AC bit 05 does not directly set a control bit but its results do. A DClC lOT should be issued before and after a
sequence using AC bit 05.
11.11.2.7 Check Data Break Request - When AC bit 06 is a 1, and lOT OMAN is executed by the program, a single
cycle data break request is initiated. The direction of transfer is controlled by the function bits in the Control
Register. If a read is specified, the contents of Data Buffer 4 is transferred into the memory location specified by the
Current Address Register and the Extended Memory Address Register. A write transfers data into Data Buffer 1. The
data transfers into the buffer and the Data Buffer fills after four data break requests unless it is emptied by a read
into the AC. It cannot be emptied by a read into memory if the DClC is executed before switching from read to
write or write to read. lOT DClC clears the Data Buffer control bits so the buffer appears to be empty. AC bit 06
does set a control bit, but it is automatically cleared after the data break is completed.
11.11.2.8 Check Lower Data Buffer - When AC bit 07 is a 1 and lOT OMAN is executed by the program, the
contents of Data Buffer 4 are read into the AC. AC bit 07 does not set a control bit so a clear is not necessary.
11.11.2.9 Maintenance Data - AC bit 10 is used in conjunction with other AC bits as data when the OMAN lOT is
executed by the program.
11.12 PROGRAMMING SEQUENCES
11.12.1

Format A New Disk Cartridge

The RK8·E control contains the logic required to format a disk cartridge. All the program must do is address every
sector on the disk and write on every sector using the Write All mode. The track address (cylinder and surface when
DlAG was issued) is automatically written on the particular sector HEADER word selected by the control. The data
written is not important except that the data should contain addressing information so a check can be made to
determine if the RK8-E and drive found the correct sector on the correct surface and cylinder.
To write a new disk, the Command Register function bits (bits 0,1,2) should contain octal 5 (Write All). To read a
newly formatted disk, the function bits should contain octal 1 (Read All). These function bits prevent the R K8-E
from reading HEADER words and reporting HEADER errors that exist on an unformatted disk.
Sequence of instructions to format a disk:
1.

Set up Current Address Register.

Set up Command Register 5000 for Write All, 1000 for Read All.

Set up first disk address and GO.

Wait for TRANSFER DONE flag, check for errors.

Set up current address again.

Set up second disk address and GO, etc.

11-44

11.12.2 Normal Read/Write
The programming sequence for a Write Data or Read Data mode is very similar to the sequence to format a disk. The
sequence is:
1.

Set up current address.

Set up Command Register 0000 for Read Data, 4000 for Write Data.

Set up required disk address and GO.

Wait for TRANSFER DONE flag and check for errors.

11.12.3 Bootstrap Loader
Many computers of the PDP-8 family include a clear with key start. On those machines, the clear of step 1 is not
required.

Clear Control.

Load the Command Register with AC = 0000. This also clears the Status Register.

Load disk address and GO.

JMP.

Most bootstrap loaders for the R K8-E are in sector 0, surface 0, and cylinder 0; thus, with the control cleared, a two
instruction bootstrap loader is all that is required.
11.12.4 Seek Only
The sequence for Seek Only (Command Register function bits equal 011) is different from Write All, Read All, Write
Data or Read Data. It is necessary to put two skip or interrupt sequences in the program.
The programming sequence is:

Set up Command Register, 3000 for Seek Only and desired unit number.

Load disk address and GO.

Wait for TRANSFER DONE flag. TRANSFER DONE is set during a Seek Only when DISK ADDRESS
ACKNOWLEDGE is received from the drive.

Clear Status Register DONE flag.

Drive is not seeking but if the TRANSFER DONE flag is to be set when the seek is complete, bit 4 of
the Command Register must be a 1, issue a load Command DLDC instruction with selected drive number
in AC 10-11 and AC bit 4=1.

Wait for TRANSFER DONE.

The alternative to steps 5 and 6 above is to check the condition of Status Register bit 1, wh ich is 0 when the seek is
complete.

11-45

11.12.5 Overlapped Seeks
Overlapped seeks make use of the seek only feature. The program starts multiple drives seeking and then periodically
selects a different drive to determine if it has completed seeking. A different drive may be selected after Paragraph
11.12.4 step 3, but in general, programs operating with other program interrupt devices could be confused as to
which drive actually completed a seek. For example, if bit 4 of the Command Register is a 1 (allowing seek complete
to set the TRANSFER DONE flag) and multiple drives are seeking, it is possible to select a different drive just as one
previously selected completes its seek. The TRANSFER DONE flag sets but the unsophisticated program incorrectly
thinks the newly selected drive has completed a seek.
A program has two methods of getting around this problem.
a.

Before selecting a new drive, the program changes the Command Register to make bit 4 a a without
changing the drive number. It then changes the drive number with bit 4 equal to 1. If the new drive has
completed a seek, there is no confusion as to which drive set the TRANSFER DONE flag.

Leave bit 4 of the Command Register set and check bit 1 of the Status Register to determine if the drive
selected or the drive previously selected set the TRANSFER DONE flag. Bit 1 of the Status Register is a
if the selected drive has completed the seek.

11.12.6 Recalibrate Selected Drive
The programming sequence for recalibrating a selected drive to cylinder 000 is similar to the sequence for Seek Only.
The sequence follows:
1.

Issue lOT 6742 with the AC equal to 0002.

Wait for TRANSFER DONE flag.

Clear status.

Drive is now seeking cylinder ODD. If the TRANSFER DONE flag is to be set when the seek is complete,
bit 4 of the Command Register must be set, i.e., issue DLDC instruction with AC 10-11 set to the
selected drive and AC bit 4=1.

Wait for TRANSFER DONE.

The alternative to steps 4 and 5 is to check bit 1 of the Status Register. Bit 1 is a when the recalibrate seek is
complete.
11.12.7 Data Transfers on Consecutive Sectors
Octal 1 or octal 4 (Read All or Write All) in the function portion of the Command Register allows a program to
format a new disk cartridge by disabling the checking of headers. This feature is also used to transfer data on
consecutive sectors. Assume a program is required to transfer 512 words of data on two consecutive sectors. The
program should use Read Data and Write Data (octal a and 4 in the function portion of the Command Register) for
the transfer of the first 256 words of data. When the first 256 words have been transferred and the TRANSFER
DONE flag is set, there is a minimum of 100 I1S for the program to set up the control for transfer to the next
consecutive sector. The function portion of the Command Register should be changed to octal 1 or octal 5 (Read All
or Write All), the Status Register cleared, and the next sector specified along with surface and cylinder when issuing
DLAG. The control does check the header of the next sector but transfers 256 words of data. It is not necessary to
change the Current Address Register, if a 512-word buffer is available in memory.
11.13 PROGRAMMING EXAMPLES
The following paragraphs provide examples to be used in programming the RKS-E Controller and the RK05 Disk
Drive.
11-46

11.13.1 Write All
The programming sequence that follows could be used to write information on a disk sector in the Write All mode.
Example
BGN, ClA Cll lAC
DClR
TAD CURENT
DlCA
TAD DRIVE
TADWRTAll
TAD FIELD
TAD EXBIT
DlDC
TAD TRACK
DlAG
DSKP
JMP .-1
DRST
CIA
TAD K4000
SZA ClA
ERROR,HlT
JMP DONE

/ enable clear control AC10=0 AC11=1
/ lOT 6742 clear control
/ desired current address ACO-11
/ lOT 6744 load current address
/ get drive number in AC9-11
/ get Write All function in AC
/ get field in AC6-8
/ get extended cylinder address bit in AC11
/ lOT 6746 load Command Register
/ get desired track in ACO-11
/ lOT 6743 load disk address and GO
/ lOT 6741 skip on DONE or ERROR flag
/ wait for flag
/ lOT 6745 read Status Register
/ change AC for testing
/ compare to expected value
/ skip if status OK
/ ERROR, disk status
/ to other seek, read, or write routines.

FIElD,OOOO
TRACK,OOOO
K4000,4000
CURENT,OOOO
WRTAll,5000

/ desired field in AC6-8
/ desired cylinder, surface, and sector
/ expected status
/ any desired current address
/ write all function ACO-2

11.13.2 Recalibrate
The programming sequence that follows could be used to "recalibrate" (return the read/write heads to cylinder 0) a
disk drive.
Example
BGN, ClA Cll lAC
DClR
TAD DRIVE
DlDC
ClA Cll CMl RTl
DClR
DSKP
JMP .-1 \
TAD K0200
TAD DRIVE
DlDC
DSKP
JMP .-1
DRST
CIA

/ enable clear control AC10=0 AC11=1
/ lOT 6742 clear control
/ get drive number in AC9-10
/ lOT 6746 load Command Register
/ enable recalibrate AC10=1 AC11=O
/ lOT 6742 recalibrate
/6741 lOT skip on DONE or ERROR flag
/ wait for flag
/ get enable set DONE bit in AC4
/ get drive number in AC9-1 0
/ lOT 6746 load Command Register
/ lOT 6741 skip on DONE or ERROR flag
/ wait for flag
/ lOT 6745 read Status Register
/ change AC for testing

11-47

TAD K4000
SZA ClA
ERROR, HlT
JMP DONE

I compare to expected value
I skip if status OK
I ERROR, disk status
I read routines, to other seek, write

DRIVE,OOOO
K0200,0200
K4000,4000

I desired drive in AC9-10
I enable set DONE AC4
I expected status only DONE flag.

11.13.3 Seek Only
The programming sequence that follows could be used for a Seek Only operation.
Example
BGN, ClA Cll lAC
DClR
TAD DRIVE
TAD SEEK
TAD EXBIT
DlDC
TAD TRACK
DlAG
DSKP
JMP .-1
TAD K0200
TAD DRIVE
DlDC
DSKP
JMP .-1
DRST
CIA
TAD K4000
SZA ClA
ERROR, HlT
JMP DONE

I enable clear control AC10=0 AC11 =1
I lOT 6742 clear control
I get drive number in AC9-10
I get seek function in ACO-2
I get extended cylinder address bit in AC11
I lOT 6746 load Command Register
I get desired track in ACO-11
I lOT 6743 load disk address and GO.
I lOT 6741 skip on DONE or ERROR flag
I wait for flag
I get enable set DONE on seek complete in AC4
I get drive number in AC09 and AC10
I lOT 6746 load Command Register
I lOT 6741 skip on DONE or ERROR flag
I wait for flag

K0200,0200
K4000,4000
DRIVE,OOOO
SEEK,3000
EXBIT,OOOO
TRACK, 0000

I enable set DONE bit (AC bit 4)
I known good or expected status
I desired drive in AC bits 9-10
I seek only function in AC bits 0-2
I extended cylinder bit in AC bit 11
I any desired cylinder, surface, and sector.

flOT 6745 read Status Register

I change AC for testing
I compare to expected value
I skip if OK
I ERROR, disk status
I seek complete, now to read or write routine
lor another seek routine

11·48

11.13.4 Overlap Seek
The programming sequence that follows could be used for an Overlap Seek operation with multiple drives
(Note: four (4) drives are assumed).
Example
BGN, ClA Cll lAC
DClR
DCA DRIVE
TAD M4
DCA CNTRl
OUT, TAD DRIVE
Cll RAl
AND K0006
DlDC
TAD DRIVE
Cll RAl
AND K0006
TAD SEEK
TAD EXBIT
DlDC
TAD TRACK
DlAG
DSKP
JMP .-1
ISZ DRIVE
JMP CNTRl
JMP OUT
JMPWAIT

I enable clear control AC10=0 AC11=1
I lOT 6742 clear control
I start with drive 0
I 4 drive counter constant
I set up the counter
I get drive number pointer
I put AC10-11 in AC9-10
I mask 9-10
I lOT 6746 load Command Register
I get drive number pointer
I put AC10-ll in AC9-10
I mask 9-10
I get seek function in ACO-2
I get extended cylinder address bit in ACll
I lOT 6746 load Command Register
I get desired track in ACO-l1
I lOT 6743 load disk address and GO.
I lOT 6741 skip on DONE or ERROR flag
I wait for flag
I update drive number pointer
I count drives
I send next drive out
I to drive wait routine to wait for drives

DRIVE,OOOO
SEEK,3000
EXBIT,OOOO
K0006,0006
M4,7774
CNTRl,O

I drive number pointer
I seek only function in ACO-2
I extended cylinder bit in AC11
I mask 9-10
I minus 4 constant
I counter

Routine to wait for drives doing an Overlap Seek.
WAIT, ClA Cll lAC
DClR
DCA DRIVE
TADM4
DCA CNTRl
IN, TAD DRIVE
Cll RAl
AND K0006
DlDC

I enable clear control AC10=0 AC11=1
I lOT 6742 clear control
I start with drive 0
14 drive counter constant
I setup drive counter
I get drive number pointer
I put AC10-11 in AC9-10
I mask 9-10
I lOT 6746 load Command Register

11-49

RDSTA,DRST
Cll RAl
SZAClA
JMP RDSTA
ISZ DRIVE
ISZ CNTRl
JMP IN
JMP DONE

I lOT 6745 read Status Register
I transfer AC01 to ACOO
I skip if drive not busy
I drive still busy AC bit 1
I drive completed seek
I update drive counter
I wait for next drive
I all drives complete. To other read, write, or
Iseek routines

DRIVE, 0000
K0006,0006
M4,7774
CNTRl,O

I drive number pointer
I mask
I drive counter constant
I counter

11.13.5 Write Data
The programming sequence that follows could be used to write information on a disk sector in the Write Data mode.
Example
BGN, ClA Cll lAC
DClR
TAD CURENT
DlCA
TAD DRIVE
TADWRTDAT
TAD FIELD
TAD EXBIT
DlDC
TAD TRACK
DlAG
D$KP
JMP .-1
DRST
CIA
TAD K4000
SZAClA
ERROR, HlT
JMP DONE

I enable clear control AC10=0 AC11=1
I lOT 6742 clear control

FIELD, 0000
TRACK, 0000
K4000,4000
CURENT,OOOO
WRTDAT,4000

I desired field in AC6-8
I desired cylinder, surface, and sector
I expected status
I any desired current address
I write data function ACO-2

I desired current address ACO-11
I lOT 6744 load Current Address
I get drive number in AC9-11
I get Write Data function in AC
I get field in AC6-8
I get extended cylinder address bit in AC11
I lOT 6746 load Command Register
I get desired track in ACO-11
I lOT 6743 load Disk Address and GO.
I lOT 6741 skip on DONE or ERROR flag
I wait for flag
I lOT 6745 read Status Register
I change AC for testing
I compare to expected value
I skip if status OK
I ERROR, disk status
I to other seek, read, or write routines

11-50

11.13.6 Read All
The programming sequence that follows could be used to read information from a disk sector in the Read All mode.
Example
BGN, ClA Cll lAC
DClR
TAD CURENT
DlCA
TAD DRIVE
TAD REDAll
TAD FIELD
TAD EXBIT
DlDC
TAD TRACK
DlAG
DSKP
JMP .-1
DRST
CIA
TAD K4000
SZA ClA
ERROR, HLT
JMP DONE

I enable clear control AC10=0 AC11 =1
I lOT 6742 clear control
I desired current address ACO-ll

FIElD,OOOO
TRACK,OOOO
K4000,4000
CURENT,OOOO
REDAll, 1000

I desired field in AC6-8
I desired cylinder, surface, and sector

/ lOT 6744 load current address
/ get drive number in AC9-10
/ get Read All function in AC
/ get field in AC6-8
/ get extended cylinder bit in AC11
/ lOT 6746 load Command Register
/ get desired track in ACO-11
I lOT 6743 load disk address and GO.
I lOT 6741 skip on DONE or ERROR flag
I wait for flag
I lOT 6745 read Status Register
I change AC for testing
/ compare to expected value
I skip if status OK
I ERROR, disk status
I to other seek, read, or write routines.

I expected status
I any desired current address
I Read All function ACO-2

11.13.7 Read Data
The following is an example of a programming sequence that could be used to read information from a disk sector in
the Read Data mode.
Example
BGN, CLA Cll lAC
DClR
TAD CURENT
DlCA
TAD DRIVE
TAD REDDAT
TAD FIELD
TAD EXBIT
DlDC
TAD TRACK
DlAG
DSKP
JMP .-1
DRST
CIA

I enable clear control AC10=0 AC1l=1
I lOT 6742 clear control
I desired current address ACO-11
/ lOT 6744 load current address
/ get drive number in AC9-11
I get Read Data function in AC
/ get field in AC6-8
/ get extended cylinder bit in AC11
/ lOT 6746 load Command Register
/ get desi red track in ACO-11
/ lOT 6743 load Command Register
I lOT 6741 skip on DONE or ERROR flag
I wait for flag
I lOT 6745 read Status Register
/ change AC for testing

11-51

TAD K4000
SZACLA
ERROR, HLT
JMP DONE

/ compare to expected value
/ skip if status OK
/ ERROR, disk status
/ to other seek, read, or write routines.

FIELD,OOOO
TRACK,OOOO
K4000,4000
CURENT,OOOO
REDDAT,OOOO

/ desired field in AC6-8
/ desired cylinder, surface, and sector
/ expected status
I any desired current address
/ read data function ACO-2

SECTION 4 THEORY OF OPERATION
This chapter contains a block diagram description (functional level) and a detailed description of the RK8-E logic.
Figure 11-9 shows the signal flow between the functional groups of logic.
11.14 BLOCK DIAGRAM DESCRIPTION
The R K8-E consists of 8 major groups of logic:
•

I/O Bus Interface

•

Command Register

•

Status Register

•

Data Break Control

•

Data Buffer Registers

•

CRC Register

•

Control Sequencer (Major States Register and Counters)

•

Maintenance Logic

11.14.1

I/O Bus Interface

The I/O bus interface (Figure 11-9) provides the following:
a.

A buffer for MDOO-MD11 from the OMNIBUS

lOT decoder

Timing pulses for the execution of instructions and maintenance operations.

MDOO-MD11 are decoded by the lOT decoder when instructions are executed by the program and generate signals
to load the R K8-E registers, execute skips and interrupts, and generate timing pulses for maintenance operations.
The outputs of the lOT decoder are used as control signals in other sections of t/le R K8-E. During the data break of
a write operation, the buffered memory data bits (MDOO-MD11) are applied to the Data Buffer Register for transfer
to the selected disk drive. This block of logic also contains bus drivers for signals to the OMNIBUS (i.e., BRK ROST,
INT ROST, SKIP, and INT I/O L) and provides a buffer for signals from the OMNIBUS (i.e., I/O PAUSE and the
time pulses).

11-52

• ;:.

DSKP(6741 )

ERROR
SKIP

TRANSFER DONE

DCLR (6742)

DSKP

DLAG(6743)

RK05 DISK
DRIVES

DLCA (6744)

(4 MAXIMUN)

INSTRUCTIDN
DECODER
1/0 PAUSE L

SKIP

DRST(6745)
DLDC (6746)
DMAN(6747)

MDOO-MDll

SERIAL DATA (WRITE)
READ DATAl DATA BUFFER
REGISTER

r--I

SERIAL DATA (READ)
IDLE
STROBE

PROCESSOR CONTROLS
BRK RQST

DATA BRK
CONTROL AND
PRIORITY
(LAST BREAK+128/256)

DRIVE SEEKING
READ
DELAY 251's

HEADER A
HEADER B
MAJOR STATES
REGISTER
(SEE TABLE 1-1)

DATAOO-DATA 11 (FROM AC)

DELAYS
(1)READ
(2)SYNC
(3)ERASE

HEADER C
SECTOR SEEK
HEADER D

SYNC
DELAY 1401's
ERASE
DELAY 251's

HEADER E

DATA STATE

M
N

CRC STATE

END STATE

B
U

CYLINDER
ADDRESS

-I

CRC REGISTER

CRC CHARACTER (SERIAL)
CYLINDER ADDRESS (0-7)

(FOR XFER TO AC)

EMA 00-EMA02
TRANSFER DONE
INT RQST
INTERRUPT

-I

DISK STATUS

INT ENABLE
ERROR FLAG

Ci
I

MAOO-MAll

COMMAND
REGISTER

WRITE CLOCK
STATUS
REGISTER

READ CLOCK

r CURRENT

ADDRESS
J REGISTER

MAINTENANCE INST.(DMAN)

COUNTERS BIT
(1)12th CARRY +12
(2)16th BIT+16
(3)LAST WORD+128/256

I
I

DISK
ADDRESS
REGISTER

Figure 11-9

I
I

SECTOR ADDRESS

R KS-E Block Diagram

MAINTENANCE
LOGIC

LAST WORD

DISABLE GO
~CHECK CRC
CHECK COMMAND REG
CHECK SURFACE SECTOR
CHECK DATA 8UFFER
CHECK 8RK RQST
CHECK LOWER DATA BUFFER
~

BE- 0530

11.14.2 Command Register
The Command Register (Table 11·13) enables all disk drive operations, i.e., read, write and seek, selects a disk drive
unit, selects a memory field for data transfers, enables interrupts, provides the most significant cylinder address bit,
and determines the number of words to be transferred (128 or 256). The Command Register (Figure 11·9) is loaded
from the AC by a DLDC instruction with DATA O-DATA 11. Note that the contents of the Command Register are
decoded and used after the program executes the DLAG instruction (load disk address and GO).
During maintenance operations, the contents of the Command Register are transferred to the AC using the DMAN
instruction (Table 11·14).

11.14.3 Status Register
The Status Register (Figure 11·9) contains the current status of the selected disk drive (Table 11·12). The program
determines the status of the RK8·E and disk drive by transferring the contents of the Status Register to the AC using
a DRST instruction. The Status Register receives its input from the RK05 Disk Drive and the data break control
logic. The DONE and ERROR flags are applied to the 1/0 bus interface to generate skips and interrupts if the skip or
interrupt logic is enabled. Note that bit 3 in the Command Register must be set (1) to enable an interrupt when the
DONE or ERROR flag sets.

11.14.4 Data Break Control Logic
The data break control logic (Figure 11·10) determines the break priority of the RK8·E, controls direction of data
transfer (to or from memory). and selects a location in memory for the data transfer.

BRK ROST

OSK HAS PRIORITY

OATAO-OATAI

BRK RQST

EMAO-EMA2
MAOO-MAII

OLAG
TP3
DATA BRK
TP4

0
M
N
I
B
U

+3V
OCLR

o
LAST
BRK

TP3

DATA BRK

LAST BRK L
OBI EMPTY

BRK ROST

TP2

BRK
ReST
TPI C

BRK IN
RO BRK

B BRK ReST

NEW BRK ReST

ALLOW BRK
OB2 EMPTY

INHIBIT CLEAR
DATA BRK

DB3 FULL

BE-0531

Figure 11-10 Data Break Control

11·54

The Current Address Register is loaded from the AC by a DLCA instruction with the initial address to be used in a
data transfer. The Current Address Register is incremented after each data break and applied to the MA lines
(MAOO-MA 11) to sequentially select memory locations for data transfers. Note that the memory field is selected by
bits in the Command Register (Table 11-13) and not incremented when the CA Register is incremented. The
direction of data transfer is determined by the decoded function bits in the Command Register, i.e., during a read
operation, data is transferred from the Data Buffer Register to memory via the data bus. Time pulses from the
OMNI BUS and control signals from the Data Buffer Register determine the timing of the single cycle data break.
The data break control also generates signals to stall the processor and stop the execution of instructions during a
data transfer.
The data break priority is returned to the OMNIBUS as DATA 0 (priority 0) or DATA 1 (priority 1) to indicate the
priority of the R K8-E. Data break control provides a DATA LATE signal to the Status Register if the processor does
not respond to a BRK RQST within 22.5 !-IS. The last break counter counts the words in a data transfer and sets the
LAST BRK flip-flop when 128 (half block) or 256 words have been transferred.
11.14.5 Data Buffer Register
The Data Buffer Register (Figure 11-11) provides four Data Buffer Registers (DB 1-DB4) for temporary storage of
data that is being transferred between memory and the disk drive. The four registers increase the data break latency
of the RK8-E control from 5.6 !-IS to 22.5 !-IS. Latency is defined as the maximum time the RK8-E can wait for a
BRK RQST to be accepted by the processor. During a write operation, parallel bits of data (MDOO-MD11) are
received from the OMNI BUS and applied to DB1. The parallel data is dropped into DB4 and shifted out of DB4 on
R K DATA 11 as serial data to the selected disk drive. During a read operation, serial data from the disk is shifted
into DB1 and dropped into DB4. The parallel bits out of DB4 are transferred to the data bus for transfer to memory
during a single cycle data break. The control logic associated with the Data Buffer Register controls the registers and
generates signals that are applied to the data break control logic. During maintenance operations, the contents of the
CRC Register, Command Register, and Surface/Sector Register can be shifted into DB4 and transferred to the AC or
memory by the DMAN instruction. The shifting of data in these registers is accornpiished by
;\,1AIN pulse, which
is generated by the DMAN instruction.
'11.14.6 CRC Register
The C RC Register (F igure 11-12) is a 16-bit multipurpose register with the following functions:
a.

The CRC Register receives a cylinder address from the AC when the DLAG (GOl instruction is executed
by the program and transfers the cylinder address to the selected disk drive.

Makes a bit-by-bit comparison of the cylinder address specified by the program and the cylinder address
from the disk drive to determine if disk has found the correct cylinder.

During a write operation, a 16-bit CRC character is computed, transferred to the disk, and written at the
end of the record.

During a read operation, a 16-bit CRC character is computed and compared with the CRC character
written at the end of the record. If the two characters are different, NOT EQUAL is asserted to set the
CRC ERROR flag. A CRC ERROR is produced if bits are lost or added during the read or write
operation.

The disk address is transferred from the AC as a 12-bit parallel word and bit 11 from the Command Register is added
to the 7 most significant bits of the CRC Register to form the 8-bit cylinder address (Figure 11-5) transferred to the
selected disk drive. Bits 12 through 16 are not used for the disk address. The disk address is transferred to the disk
drive on parallel lines during the STROBE major state.

11-55

1 (DB 1 FULL)

12th BIT
READ
LD RD BUFF

DB
CCONTI

*MDOO-MDll

0081 EMPTY
(FROM DISK)
READ DATA
DB DDNT2
1 (DB2 FULL)

DBl FULL
DB2 EMPTY

MAIN DATA
(AC BIT2)
(FROM DISK)
READ CLOCK

DBl

MAIN PULSE
(AC BIT2)
DB 2

DB2 FULL
DB3 EMPTY

o EMPTY

DB CONT 2 (LOAD)
DB2
DB CONT 3
1 (DB3 FULL)

DB3 FULL
DB4 EMPTY

o DB3 EMPTY

DB CONT3(LOAD)

DB3

MAIN PL
ACl

DB CONT 4
(DB4 FULL)
CMD REG BIT4 (AC4)
CRC 16
DATA STATE

CLR SYNC
TEST CLK

DB4

WRT CLK

o EMPTY

L-_-,......,-.......--'WRT DATA

12th BIT

TO MEMORY

(RK DATA 11 H)
TO DISK
DB CLK

DATA DO-DATA 11

WRT
1 CLR SYNC

1-DB2
1-DB3
1-DB4
0-DB4

SYNC

r-----, TEST

DATA BUFFER

CLOCK
ONE
SHOT
501'5

ONE
SHOT
1501's

WRT BUFF- DATA
B TP2

o
*OMNIBUS SIGNALS

DATA BUFFER CLOCK
8E-0532

Figure 11-11

Data Buffer Register

11-56

* DATA 0-6 _ _ _--,
CMD REG BIT II (EXT ADD BIT)

RD ClK
DATA STATE
CRC STATE
HEADER C
HEADER C
CRC STATE
DATA STATE

CYLINDER ADDRESS (07)

SHI FT CRC

TO DISK DRIVE

ClR DISK ADDR
CRC DATA
EXCLUSIVE
OR

WRT ClK

NOT
EQUAL

READ DATA
MAl N DATA

NOT EQUAL

~--~~-1D

EXCLUSIVE
OR

DATA STATE (0)
DATA STATE (I)
HEADER C
READ DATA

eRe STATE

DATA STATE

WRT DATA

CRe STATE
HEADER C
*OMNIBUS SIGNALS
8E-0533

Figure 11-12 eRe Register

When the RK8·E moves into the DATA state, the CRC Register is cleared and the computation of a CRC character is
started.
During write operations, the CRC character is transferred to the disk drive during the CRC state as a 16·bit serial
word. The serial bits are shifted out of the CRC Register to the disk drive and written at the end of the data.
During read operations, the CRC character is computed from the data read from the disk and compared with the
CRC character that was written at the end of the data. The CRC Register makes a bit·by·bit comparison of the two
CRC characters, and if they are different, NOT EQUAL is asserted to set the CRC ERROR flag.
The contents of the CRC Register are checked using the maintenance instruction. The bits in the CRC Register are
shifted into Data Buffer 4 and transferred to the AC (Table 11·14).
11.14.7 Control Sequencer
The control sequencer (Figures 11·13 and 11·14) comprises the Major States Register, word counter (128 or 256
words), and the bit counter. The word counter and bit counter keep track of the number of words transferred to or
from the disk drive. The bit counter counts 12 bits from the disk drive and increments the word counter each time a
word (12 bits) is read from the disk. After 256 words are read, the data transfer is stopped and the CRC character is
written on the disk during a write, or read from the disk during a read. If bit 5 in the Command Register is set (1),
the data transfer is stopped after 128 words are read or written, but the disk drive continues to write all zeroes
during a write operation or read all zeroes during a read operation until 256 words have been written or read. This
allows the R K8·E to process the CRC character, which is always written at the end of the data (Figure 11·7).
The Major States Register determines the format of the disk, i.e., PREAMBLE, HEADER, DATA, CRC, and
POSTAMBLE.
11.14.7.1 Major States - The Major States Register (Figures 11·13 and 11·14) controls each step the RK8·E
control progresses through to perform a seek, read, or write operation. Each major state causes specific operations to
be performed (Table 11·2 and Figure 11·7).
The Major States Register is a shift register that shifts a binary 1 starting at the I DLE state and ending with the END
states as shown in Figure 11·7 unless an error occurs (i.e., an ADDRS ERROR) or the function does not require all
major states (i.e., sector, seek, and recalibrate).
11.14.7.2 IDLE State - The RK8·E must be in the IDLE state (Figure 11·13) to allow initiation of a disk function
and returns to the IDLE state after an operation is completed. The IDLE state indicates that the control is not busy
and that it is capable of accepting lOT instructions from the processor (Figure 11·14). The IDLE flip·flop is cleared
when the program executes a DLAG instruction (load disk address and GO) or the CLR drive (DCLD) instruction.
The DCLD instruction initiates a special state called RESTORE, which is discussed in Paragraph 11.15.3.
The IDLE state flip·flop is set by any of the following conditions to return the control to the IDLE state to wait for
R K8·E instructions.
a.

At the end of ERASE DELAY during a write function.

During last break of a read operation (after Data Buffer Register is empty).

When the selected disk drive asserts ACKNOWLEDGE during a seek only operation.

When the ERROR flag is set (Table 11·12).

11·58

RESTORE

FILE READY D

RESTORE
RD CMD
END STATE
LAST BRK

CLR DRIVE C

SEEK ONLY

ACKNOWLEDGE

IDLE

D
IDLE

ACKNOWLEDGE

FILE READY

i
STROBE

CLR DRIVE

STROBE

LOAD DSK ADD

------IC

RDY TO SK/RD/WRT

GO
ACKNOWLEDGE

CK HEADER AND RD
HEADER A

CK HEADER AND WRT
RDY TO
SK/RD/WRT
ACKNOWLEDGE

HEADER B

HEADER
A

HEADER C
HEADER
C

HEADER
B
SECTOR MK

o
HEADER B

RD SYNC BIT

HEADER C

SECTOR SEEK

WRT CMD

WRT GATE

WRITE

HEADER C

16th HEADER BIT
DONT CHECK HEADER D

SECTOR SEEK

HEADER
D
0

SECTOR
SEEK
~D~SK~O~K~_ _ _,C
0
IDLE

DATA STATE

CRC
STATE

CRC STATE '(

DATA
STATE

WRT SYNC
SECTOR
EQUAL

DATA
STATE

16th HEADER BIT

HEADER E

SECTOR ADD
FROM DISK

HEADER E

HEADER

SECTOR C
MK

ADDRESS OF
DESIRED SECTOR

HEADER D

I-'H.:.::E::...A:.=D=-ER:..:......:D~O----I D

...-----ID

C
END STATE!

CRC STATE

16th BIT
OF CRC

IDLE

RD SYNC
rEND STATE

WRT C M D L

END
STATE

ERASE DLY

ONE
SHOT
25ps
C

12th BIT OF LAST DATA WORD

8E-053 4

Figure 11-13 Major States Register

11-59

RD CMD
HEADER D

RD GATE

SECTOR MK

ONE SHOT
85f's

READ DELAY

READ
DELAY

RD DLY

END STATE

SECTOR MK ~
WRT CMD

WRT SYNC

SYNC DLY

-L

ONE SHOT
140/,s

SYNC

WRITE SYNC DELAY
WRT CLK

HEADER D I j) HI'

MAIN
PULSE lAC 2)

LAST WORD

RD CLK

L--_ _ _ _.....Jr-1281h WORD

WRT CLK

COUNTER

WRITE CLOCK-DATA
WRT CLK
AND DATA

HEADER E
CRC STATE

RD DATA
D

READ

READ CLOCK -DATA

READ

RD CLK

Figure 11-14

Read/Write Delays and Counters

11-60

11.14.7.3 RESTORE State - The RESTORE state is a special state (Figure 11-13) used to clear SELECT ERRORS
and CYLINDER ADDRESS ERRORS. RESTORE is set by FILE READY and the CLR DRIVE command,
generated by the DCLD instruction. When the selected disk asserts ACKNOWLEDGE, the RESTORE flip-flop is
cleared and the Major States Register goes back to the IDLE state to wait for RK8-E instructions. Thus, the RK8-E
uses only one state for the clear operation and the control is released (made not busy) while the disk drive returns to
the home position.
11.14.7.4 STROBE State-The STROBE state (Figure 11-13) is used to transfer the cylinder address from the
CRC Register to the disk drive and wait for the selected drive to ACKNOWLEDGE the cylinder address. The
STROBE flip-flop is set by GO when the DLAG instruction is executed by the program if the selected disk drive is
ready (FILE READY asserted). STROBE is cleared when ACKNOWLEDGE is received from the selected drive and
the Major States Register moves to the HEADER A state or SECTOR SEEK state (Figure 11-7) when the selected
drive is ready to seek, read or write (F igure 11-14).
11.14.7.5 HEADER A State-The HEADER A state (Figure 11-13) is used to start a read delay (Figure 11-15)
and wait for a sector mark during read and write functions. When a sector mark is obtained from the disk drive, the
HEADER B state is entered and the HEADER A state is cleared by HEADER B.
11.14.7.6 HEADER B State - The HEADER B state (Figure 11-14) is used to turn READ on at the end of READ
DELAY (Figure 11-12) and read zeroes until a SYNC pulse is encountered. The SYNC pulse indicates the beginning
of the HEADER area of the disk format.
During a write operation, the write sync delay is triggered when a sector mark is received from the disk (Figure
11-141. After a 140 ps (write sync delay), a one bit (SYNC pulse) is written on the disk to indicate where the
HEADER area starts. When the SYNC pulse is read or written, tlJe RK8-E advances to the HEADER C state and
HEADER B is cleared.
11.14.7.7 HEADER C State - The HEADER C state (Figure 11-14) is used to read the 16-bit HEADER word and
compare it bit-by-bit with the disk address in the CRC Register. HEADER C is cleared when the divide-by-16
counter (Figure 11-15) asserts 16th bit to indicate the 16th bit of the HEADER word has been read from the disk
drive. When HEADER C clears, it sets SECTOR SEEK (Figure 11-14) and starts the SECTOR SEEK major state.
11.14.7.8 SECTOR SEEK State - When the control enters the SECTOR SEEK state, cylinder address ERROR is
set if the cylinder address does not equal the HEADER word read from the disk during the HEADER C state (Figure
11-121. During the SECTOR SEEK state, the sector address lines from the RK05 are compared with the
Surface/Sector Register.
11.14.7.9 HEADER D State - The HEADER D state is used to wait for the completion of READ DLY (85 ps)
during a read function or the completion of SYNC DL Y during a write operation. If this is a read function, the
controller reads all zeroes until a SYNC bit is read. When the sync bit is read, the control advances to the HEADER
E state. If this is a write function, the control writes zeroes and waits for SYNC DL Y, then writes the SYNC bit (a
data 1). When the SYNC bit is written, the RK8-E moves to the HEADER E state and clears the HEADER D
flip-flop.
11.14.7.10 HEADER E State-The HEADER E state is used to read, but ignores 16 bits of data during a read
operation. During a write operation, the 16-bit HEADER word in the CRC Register is written. When the 16-bit
HEADER word has been read or written, the Major States Register advances to the DATA state.

11-61

GET THE SELECTED

YES

DRIVE INTO A WRITE
PROTECT $T ATUG AT
TP3

YES

AT TP3 "LD DISK ADORS"
EXT CVl ADDRS~CRC4
ACO·6--CRC5·1 ~

INITIALIZE SELECTED

DRIVE AND SEEK

CYLINDER ADDRS ZERO
CLEAR STATUS REG

ANDAC

8E-0537

Figure 11-15 R K8-E Flow Diagram (sheet 1)

11-62

AS THE CONTROL ENTERS
A MAJOR STATE (MS)
THE PREVIOUS MS IS

ENABLE CYLINDER

- --"--

ADDRS (CRC 4- 11)
TO THE DISK ADDRESS

CLEARED

LINES. CLEAR IDLE
STATE

WAIT FOR "DISK ADDRESS
ACKNOWLEDGE"
CLR STROBE
(AND RESTORE)

YES

SET DONE FLAG

DRIVE SEEKING
MONITOR DISK
"ROY S/R/W"
LINE.
DRIVE IS POSITION
ING HEADS OVER

SK/RD OR
SK/WRT

WAIT FOR "SECTOR
MARK"
START READ DELAY

HEADER B STATE
AT THE END OF
READ DELAY SET
READ
READ ZEROS UNTIL
"SYNC BIT" IS READ
(FIRST ONE BIT OF

8E-0538

Figure 11-15 RKS-E Flow Diagram (sheet 2)

11-63

CLEAR THE COUNTERS
READ THE 16 BIT
HEADER WORD INTO
THE CRC REGISTER
AND COMPARE IT BIT
FOR BIT WITH THE
CYLINDER ADDRS IN
THE CRC REGISTER

IF WRITE TRANSFER

DATA FROM THE CP VIA
DATA BREAK REQUEST
TO THE DATA BUFFER

TRY TO KEEP THE
DATA BUFFER FULL

SET "CYL ADDRS
ERROR", DONE FLAG,
AND IDLE

8E-0539

Figure 11·15

R K8·E Flow Diagram (sheet 3)

11·64

HEADER D STATE
SET-UP FOR THE
HEADER WORD

SET WRITE

AT THE END OF READ
DELAY SET READ

WRITE ZEROS FOR
THE LENGTH OF
"SYNC DELAY"

READ ZEROS UNTIL THE
SYNC BIT IS READ

THEN WRITE THE
"SYNC BIT"

CRC REGISTER

BE-0540

Figure 11-15

R K8-E Flow Diagram (sheet4)

11-65

DATA STATE
CLEAR COUNTERS
AND THE CRC

SHI FT A 12 BIT WORD

SHI FT 12 BITS FROM

FROM DB4 TO THE DISK

THE DISK INTO DBI

AND CRe. GENERATOR

AND I NTO THE CRC

INCREMENT WORD

GENERATOR.

CNTR ON 12TH BIT

INCREMENT WORD
COUNTER ON 12TH BIT

IF DBI IS EMPTY
ISSUE A BRK RQST TO

WHEN A 12 BIT WORD IS

TRANSFER DATA TO
THE UPPER DATA

ASSEMBLED IN DB4.
ISSUE A BRK RQST TO

BUFFER FROM THE CPo

TRANSFER THE WORD

TRY TO KEEP ALL FOUR

TO THE CPo TRY TO
KEEP ALL 4 DATA

OATA BUFFERS FULL

BUFFERS EMPTY FOR
INCOMING DATA FROM
THE DISK
INCREMENT LAST BRK
COUNTER EACH TIME A
WORD IS TRANSFERRED
INCREMENT LAST BRK

TO DBI

COUNTER EACH TIME A
WORD IS TRANSFERRED
FROM DB4

OF THE SECTOR.
SHI FT ZEROS INTO THE
CRC GENERATOR.
YES
EACH 12TH BIT OF
ZEROS INCREMENT
THE WORD COUNTER.
INHIBIT DATA REQUEST
LATE
READ THE REMAINING
PORTION OF THE SECTOR
("ZEROS") INTO THE CRG
GENERATOR.

INHIBIT

DATA REQUEST LATE
12TH BIT INCRE MENTS
WORD COUNTER

Figure 11-15

RK8-E Flow Diagram (sheet 5)
11-66

8E-0541

READ

READ A 16 BIT CRC
CHECK WORD FROM
DISK INTO CRC
REGISTER. COMPARE
EACH BIT WITH THE
GENERATED CRC WORD

IF CRC FROM DISK
DID NOT EQUAL THE
GENERATED CRC
SET CRC ERROR

WAIT UNTIL THE DATA
IN THE DATA BUFFER IS
EMPTIED INTO THE CP
ON LAST BREAK

8E-0542

Figure 11-15

RK8-E Flow Diagram (sheet 6)

11-67

>--C--4>1 LOAD lAC) INTO THE CA

INITIALIZE CONTROL
CLEAR MAJOR

CLEAR STATUS
REGISTER AND AC

REGISTERS, SET
CONTROL TO IDLE.
AND CLEAR AC

LOAD lAC) INTO THE

COMMAND REGISTER
AND CLEAR AC

IF THE DONE OR
ERROR FLAG IS SET
ASSERT SKIP LINE

CLEAR THE AC AND
YES

LOAD THE CONTENTS
OF THE STATUS
REGISTER INTO THE AC

8E-0543

Figure 11-15

R K8-E Flow Diagram (sheet 7)

11-68

YES
AClltj 1

WHEN BRK RQST IS

ACCEPTED, TRANSFER
DATA FROM THE
MEMORY LOCATION
SPECIFIED BY THE
CURRENT ADDRESS

INTO OBl

WHEN THE BRK RQST
IS ACCEPTED, TRANSFER
DATA FROM DB4 INTO
THE MEMORY LOCATION
SPECIFIED BY THE
CURRENT ADDRESS

DATA BUFFER CONTROL
DATA BUFFER CONTROL
DROPS DATA INTO THE

DROPS DATA INTO

LOWEST EMPTY BUFFER

DATA IS AVAILABLE IN

LOWER DATA BUFFER IF
THE BUFFER ABOVE

8E-0544

Figure 11-15 RK8-E Flow Diagram (sheet 8)

11-69

DATA BUFFER CONTROL
DROPS DATA INTO

L....:.~;:,~:..:.A;,;,I~:..;TA.:OC.;,AA.:CN;..D_LO_A_D....JI----<~ ~~~:~SD:::I~~:~~R IF I-----.! A
FROM THE BUFFER

ABOVE

SHI FT AC BIT10 INTO

THE MSB OF DBl

NO
ON 12TH BIT DROP
THE UPPER BUFFER
INTO THE LOWEST
EMPTY BUFFER

SHIFT lSB OF THE
SECTOR-SURFACE REG

INTO THE MSB OF

THE lOWER DB
IF IT IS ENABLED

SHIFT LSB OF THE
COMMAND REG INTO
THE MSB OF THE

LOWER DB
IF IT IS ENABLED

SHI FT lSB OF THE CRe

>--'-''''--.... REG INTO THE MSB OF
THE LOWER DB
IF IT IS ENABLED

ENABLE LOWER DB
AS A SHIFT REG

Figure 11-15 RKS-E Flow Diagram (sheet 9)

11-70

11.14.7.11 DATA State - The DATA state is used to transfer 256 data words from PDP-8/E memory to the disk
drive during a write operation, or transfer 256 words of data from the disk drive to memory during a read operation.
The data break control logic tries to keep the Data Buffer full during a write operation and tries to keep the Data
Buffer empty during a read operation (the block diagram of the Data Buffer Register is discussed in Paragraph
11.14.5 and the block diagram of the Data Break control logic is discussed in Paragraph 11.14.4). The DATA state
ends when 256 words have been transferred and the word counter asserts lAST WORD. If the RK8-E has been
instructed to write 128 words, 128th word is asserted after 128 words (half block) have been transferred. The 128th
word ends data transfer operations and the disk reads or writes zeroes until the full block of data (256 words) has
been read or written. When lAST WORD is asserted, the RK8-E advances to the CRC state and clears the DATA
state flip-flop.
11.14.7.12 CRC State - The CRC state (Figure 11-13) is used to write the CRC character, computed by the CRC
Register (Figure 11-12) on the disk at the end of a sector during write operation. During read operations, the CRC
character computed by the CRC Register during the data transfer is compared with the CRC character read from the
disk. An Exclusive OR circuit on the CRC Register makes a bit-by-bit comparison of the CRC character read from
the disk and the CRC character shifted out of the CRC Register. If the two characters are not equal, the CRC
ERROR flag is set to indicate a CRC ERROR occurred during the data transfer. The program must check the Status
Register to determine if the CRC ERROR set the ERROR flag. The Major States Register advances to the END state
and clears the CRC state flip-flop when 16th BIT l is asserted.
11.14.7.13 END State - The END state is used by the read operation to allow the Data Buffer Register to be
emptied by the single cycle data break, set the CRC ERROR flag if the CRC characters were not equal, clear READ,
set the DONE flag, and return the RK8-E to the IDLE state (not busy). During a write operation, the controller
starts ERASE DlY (Figure 11-13) and after 25 IlS, WRITE is cleared, the DONE flag is set and the RK8-E is
returned to the IDLE state. Note that there is no CRC character comparison during a write operation and no CRC
ERROR should be detected.
11.14.8 Read/Write Delays, Clocks, and Counters
The read/write delays, clocks, and counters generate signals to assist the Major States Register in the control of disk
operations and help to develop the disk format.
11.14.8.1 Write Data Clock - The write data clock (Figure 11-14) is a 2.88 MHz oscillator that is used to generate
the WRT ClK pulses (Figure 11-2) during a write operation. The time between WRT ClK pulses (690 ns) is referred
to as a bit cell, which is used to write data. The WRT DATA ClK and a SYNC bit, CRC DATA bit, or a DATA bit
are written on the disk cartridge.
11.14.8.2 Write Sync Delay- Write sync delay (Figure 11-14) is a 140 IlS delay that is started when a SECTOR
MARK from the disk drive is detected during write operations. After 140 Ils, WRT SYNC is asserted and the SYNC
bit is written on the disk drive.
11.14.8.3 Read Delay - The read delay (Figure 11-14) is an 85 IlS delay that is started when the SECTOR MK
from the disk drive is detected, if the RK8-E is in the HEADER D state of a read operation. The 85 IlS delay allows
the control to wait for a SYNC bit before advancing to the HEADER Estate. RD DlY asserts the RD gate to allow
the RK05 to read.
11.14.8.4 Read Clock Data - The READ flip-flop (Figure 11-14) is set by RD DATA from the RK05 and cleared
by RD ClK to generate the READ signal. The READ signal is used to enable READ data pulses to be applied to the
Data Buffer Register. The READ data pulses are clocked into the Data Buffer Register by the RD ClK signal.

11-71

11.14.8.5 Counters - The RK8-E contains 4 counters (Figure 11-14) a divide-by-12-bit counter, a divide-by-16-bit
counter, a divide-by-128- or 256-word counter and a break counter. The divide-by-12 counter counts the bits of data
as they are read from the disk drive. Each time 12 bits (one word) are read, the word counter is incremented by 1.
After 256 words are read, LAST WORD L is asserted to end a data transfer. If the HALF BLOCK bit (bit 5) in the
Command Register is set, the 128th WORD signal is asserted after 128 words are read or written. This causes the
RK8-E to stop data transfers between memory and the disk drive, but the disk drive continues to read or write all
zeroes until LAST WORD L is asserted (256 words have been read or written). When LAST WORD is asserted, the
data transfer is complete. The 16-bit counter asserts 16th bit when 16 bits are read from the disk or written on the
disk. This is used when the PR EAMB LE and CRC are read or written to count 16 bits instead of 12.
The break counter is incremented during TP2 time of a break cycle to count the single cycle data breaks. LAST BR K
H is asserted after 128 or 256 words have been transferred to or from memory. There are 128 break cycles when the
HALF BLOCK bit (bit 5) in the Command Register is a 1. Note that LAST BRK does not stop a read or write
operation because 256 words must be read or written to end an operation. If HALF BLOCK is set (1), the last 128
words are all zeroes and not used.
11.14.9 Maintenance Logic
The maintenance logic (Figure 11-16) allows the program (software) to check the R KS-E operation. The program
can transfer the contents of the Data Buffer Register, CRC Register, Command Register, and Surface/Sector Register
to the AC or memory if the program executes the DMAN instruction. The operation performed when the DMAN
instruction is executed by the program is determined by the contents of the AC (Table 11-14 and Figure 11-15). The
maintenance logic allows the program to shift the contents of the CRC Register, Command Register, or
Surface/Sector Register into the Data Buffer Register for transfer to the AC by a DMAN instruction or to memory
by a data break. The shifting of registers is accomplished by the MAIN pulse, which is generated each time aDMAN
instruction is executed. The program must keep track of the number of shifts and determine when to transfer the
data to the AC or memory.
The maintenance logic checks all counters in the RK8-E control and allows data to be transferred from the AC to
the Data Buffer Register.
The maintenance logic provides timing pulses to the major registers, data break control, and control sequencer to
check these groups of logic. Note that the DMAN instruction disables the DLAG (GO) lOT and a clear operation
must be performed to allow the program to continue after maintenance operations are executed by the program.
11.15 DETAILED LOGIC DESCRIPTION
The logic in the RKS-E is divided into functional groups for discussion purposes. The block diagram, Figure 11-9,
and the flow diagram, Figure 11-15, should be used to understand the interaction of the logic, the signal flow within
the RKS-E, and the input or output signals.
11.15.1

I/O Bus Interface

The I/O bus interface consists of the MD receivers, lOT decoder, interrupt and skip logic, and timing and control
logic.
11.15.1.1 MD Receivers - The MD receivers allow data on the MD lines to be applied to the device select logic and
I/O decoder when an R KB-E I/O instruction is executed by the program. The MD receivers also allow data on the
MD lines to be applied to the Data Buffer Register during a write operation (MD -+ RD BUFF Land MD -+ RK L are
asserted).

11-72

MAINTENANCE ENABLE AND PULSE GENERATOR
MAIN II

A C:..=O--,H'-------1 0
cc
6RK71D MANI C

MAIN
MAIN PULSE

DATA BUFFER AND MAINTENANCE CONTROL LOGIC
MAIN PULSE

MAIN DATA(ACIO HI

DB4
CONTROL

AC2 H
DB CO NT 4

MAIN PULSE

AC4 H
MAIN PULSE

~M::CAI::-:N-=pCCULC-:SC::E----;--""MEMORY
AC6 H

, - " - - _ / (DATA O-DATA 111

AC 3 H
MAIN PULSE
6RK7(DMANI
AC7 H

AC
'--L-_/

(DATA 0- DATA II I

CONTROL DONE (MAINTENANCE)
SHIFT DB H

CONTROL DONE

N01E; The function of each A C bit is shown in table 3-4.
"OMNIBUS SIGNALS

CONTROL
DONE

8 E -0536

Figure 11-16 Maintenance Logic

11.15.1.2 lOT Decoder Logic - The lOT decoder (Figure 11-17) decodes MD bits (instructions) from the Memory
Data Bus and generates signals to control the operation of the RKS-E. Bits MD3-11 are gated by MD ""* RK L when
I/O PAUSE L is asserted by the processor. I/O PAUSE L is asserted anytime an lOT instruction is executed by the
program. MD3-S generates a signal DEVICE RK H and enables bits MD9-11 to be applied to the lOT decoder (an
S251 IC). The 8251 IC is a BCD to decimal decoder (see Volume I, Appendix A for truth table, logic diagram, and
pin locations) that produces a low on one output line to indicate which instruction has been executed by the
program. For example, MD9 low, MD10 and 11 high (100) produce a low on pin 9, which indicates a DLCA (6744)
instruction was executed by the program. The jumpers on MD6-S are used to select the device code for the RK8-E
when multiple systems are installed (see Table 11-3 for jumpers to select the device codes). I nternal I/O L is asserted
by the. DEVICE RK signal to prevent the processor from executing other lOT instructions while the RK8-E is
executing an lOT instruction.

11-73

PIO M7104 MODULE
MD 0 L
DATA ENAB (1) H
BRK DIR (0) H

MD-RD BUFF L

6RK5 L
6RK3 L _~.r--....
>--------~

MOl L

MD2 L

Cl L

LODB-AC L

6RK2 L-----<~6RK4 L
E44
6RK5 L
6RK6 L--OI-_ _

ENABLE RK DATA H

E29
B235

CO L
NOT USED
NOT USED

MD 3 L

MD 4 L

MD 5 L

......
......
..!.J
+>-

MD 6 L
INTERNAL I/O L

MD-RD BUFF H

MD 7 L

MOB L

MD 9 L

6RK3 OK L

MD 10 L

MD 11 L

6RK7 OK H

BE-Q588

Figure 11,17 MD Receivers and lOT Decoder

11.15.2 Control Logic
11.15.2.1 C Line Select Logic - The C line select logic (F igure 11-17) controls the direction of data flow between
the Data Bus and the AC and determines whether the AC is cleared or not. Table 11-15 shows the status of CO and
C1 to transfer data between the Data Bus and the AC using the RKS,E lOT instructions.

Table 11-15
CoLine Select Levels and Transfer Operations
Instruction

Transfer Operation

DCLR
DLAG
DLCA
DRST
DLDC
DMAN

Low
Low
Low
Low
Low
Low

High
High
High
Low
High
High

AC....:o,. Data Bus, Q....:o,. AC
AC....:o,. Data Bus, Q....:o,. AC
AC....:o,. Data Bus, Q....:o,. AC
Data Bus....:o,.AC
AC....:o,. Data Bus Q....:o,. AC
AC....:o,. Data Bus, Q....:o,. AC

11.15.2.2 Time Pulse 3 (TP3) Logic - TP3 (Figure 11-1S) is used throughout the RKS-E modules to enable gates
for the execution of instructions. SHORT TP3 is used in the detection of a BUSY ERROR (Paragraph 11.15.4).
11.15.2.3 IDLE - The IDLE state indicates that the control is not busy; the control must be in the IDLE state to
enable the execution of the 6RK2 (Figure 11-17), 6RK3, 6RK4, 6RK6. and 6RK7 (Figure 11-1S) instructions.
11.15.2.4 Clear Logic - The logic of the RKS-E and/or the RK05 Disk Drives is cleared as follows:
a.

By INITIALIZE during power up or if the CLEAR key is depressed on the PDP-S/E console.

The RKS-E logic is cleared by CLR ALL L if the 6RK2 (DCLR) instruction is executed by the program
and AC bits 10 and 11 equal 01 (Table 11·11).

By CLR ALL Land CLR DRV CMD L if the 6RK2 (DCLR) instruction is executed by the program and
AC bits 10 and 11 equal 10 (Table 11-11).

If a power failure is experienced and POWER OK H from the CPU goes low (Figure 11·18).
BTP3 H
B DATA 10 H
FROM AC

{

B TP3 L

B DATA 11 L
BTP3 OK H E44

CLR DRV CMD L

~------------------------~~~~

6RK2 H

E21

CLR ALL H
B DATA 11 H
B DATA 10L
BTP3 OK L

INITIALIZE H

Figure 11-1S INITIALIZE, CLEAR ALL and
Time Pulse 3 Logic
11-75

8E-0592

11.15.2.5 Interrupt Logic - INT RQST L (Figure 11-19) is asserted to interrupt the program if ENABLE INT His
asserted (bit 3 in the Command Register must be 1) and the ERROR or DONE flags are set.
11.15.2.6 Skip Logic - The SKIP line is grounded if the ERROR flag or the DONE flag is set and the DSKP
instruction is executed by the program (Figure 11-19).

ENABLE INT H - - - - i
INT RQST L
ERROR FLAG L - - - Q
DONE FLAG (0) H - - - O I
SKIP L
6RKt H (DSKP)-----i

SE-0590

Figure 11-19

Interrupt and Skip Logic

11.15.3 Command Register
The Command Register (Figure 11-20) is loaded from the AC by a 6RK6 (DLDC) instruction. The Command
Register (Table 11-13) is used to select a disk functiqn, enable interrupts, read or write 128 words instead of 256,
address extended memory, select a unit, and provide
a bit (EXT CYL ADDRS) for cylinder addressing. The
!
Command Register consists of three.8271 ICs (see Volume I, Appendix A for truth table, logic, and timing diagram)
that contain 12-flip-flops, which are set or cleared by bits from the AC. The inputs to the flip-flops are enabled by
DEVICE RK H, which asserts DATA ENAB L when the 6RK6 instruction is executed by the program to load the
Command Register. The outputs of the Command Register are applied to a function decoder, unit select decoder,
and the R K8-E control logic. Note that bit 11 is applied to the CRC Register to be used in cylinder addressing.
The contents of the Command Register can be shifted into Data Buffer 4 if the 6R K7 (OMAN) instruction is
executed by the program and AC bit 3 is set. The MAl N PL H signal shifts the contents of the Command Register
one bit position each time the OMAN instruction is executed by the program. The contents of the Command
Register becomes a 12-bit serial word that is applied to DB4 in the Data Buffer Register as EXT CYL ADDRS H
(Figure 11-25).
The Command Register is cleared anytime CLR ALL L is asserted (Paragraph 11.15.1.2).
11.15.3.1 Function Decoder - The function decoder (F igure 11-20) is an 74155 IC that decodes function bits
00-02 and determines what function is to be performed by the RK8-E and the selected RK05. The 74155 IC (see
Section 7 for the truth table, pin locator, and logic diagram) is a 3-line to 8-line decoder that generates a low on one
output line to select one of the R K8-E functions (Table 11-13). As an example, if FOO is high and F01 and F02 are
low, the function is to seek a cylinder, check the HEADER, and write data on the specified sector.

11.15.3.2 Unit Select Decoder - The unit select decoder (Figure 11-20) decodes the unit select bits (UNIT SEL 0
and UNIT SEL 1) from the Command Register to select one of the RK05 Disk Drives. The unit select decoder is a
74155 IC that decodes the two unit select bits and grounds one of the unit select lines. The 74155 IC (see Section 7
for truth table, pin locator, and logic) is used as 2-line to 4-line decoder that grounds one of the unit select lines and
selects one of the R K05 Disk Drives. As an example, if both unit select bits are high (11), pin 4 on the 74155 IC is
grounded and drive 3 is selected for an operation.

11-76

* DATA 0 L

1/0 -, CD CLR ALL L

... DATA 1 L

..d

* DATA 2 L

INTERFACE I
(M7104)--.I

,® 6RK6 H (DLDC)
® 6RK7 H (DMAN)

I
I

1 2 3
FUNCTION 00 H

E13
.-+-+---------~~CLEAR

BDATAOH

E13

(8~ill

BDATA 1 H

FUNCTION 01

FUNCTION 02 H
ENA~ INT H

~________~~-1~B~D~A~T~A~2~H~~
BDATA 3 H

... DATA 3 L

-,
, . - - - - - - - , SK/WRT L

SK/CHK/WRT L
E31
FUNCTION
DECODER
(74155)

SEEK L

E35

WRT LOCKOUT L
SK/RD L

WRT LOCKOUT H
6RK3 OK HI

*DATA5L
ENAB SEEK DONE H
HALF BLOCK H
*

DATA 6 L

E3
(8271)

BDATA 4 H
BDATA 6 H
BDATA 7 H

DEVICE RK H
E38

EMA 0 H
EMA 1 H

BDATA 5 H

* DATA 7L

D--+--- DATA ENAB L

r-- - - - - l
r
I
DATA 8 L

L-dE52

1* DATA 9 L
1... DATA 10 L

1* DATA 11 L

6RK7 H

U --~
E52

E52

6RK6 H

~__-+~C~LR~A~L~L~L~~CLEAR

BDATA8H
BDATA 9 H

BDATA 10 H

DRIVE 0 L
E10
UNIT
SELECT
DECODER
(74155)

E17
(8271)

UNIT SEL 1 H
EXT CYL ADDRS H

DRIVE 1 L
DRIVE 2 L
DRIVE 3 L

~------~Ir-----~r---------'

BDATA11H

L ______ J
...OMNIBUS SIGNALS FROM THE AC

EMA 2 H
UNIT SEL 0 H

6RK6 H
BTP3 OK H

~M~A~IN~PL~H~-4

BDATA 3 H

CO-,"" OM' >eo

___

J E41

8E-0597

Figure 11-20 Command Register

--1

... DATA 4 L

CLEAR

SK/CHK/RD L

DISK WRT
PROTECT L
TO RK05

11.15.4 Status Register
The Status Register (Figure 11-21) provides current status of the RK8-E and the selected BK05 Disk Drive to the
program. The contents of the Status Register are transferred to the AC for evaluation by the program if the 6RK5
(DRST) instruction is executed by the program (Figure 11-27). The flip-flops that make up the Status Register
supply inputs to the output data multiplexer (Figure 11-27) and are transferred to the AC via the Data Bus by the
6RK2 instruction. The flip-flops in the Status Register provide 1s (set) or Os (cleared) to indicate error conditions.
11.15.4.1 TRANSFER DONE - The TRANSFER DONE flag (ACO) is set (Figure 11-21) during maintenance
operations as follows:
a.

By the LAST WORD PL H signal at the end of a data transfer operation. LAST WORD PL H is asserted
after 256 words have been transferred. Note, if a half block or 128 words are transferred, the
TRANSFER DONE flag is not set until 256 words have been read or written.

By IDLE (1) H if the IDLE flip-flop is set by the detection of an error during an operation or at the
completion of an oPl'lration.

By IDLE (1) Hand RDY S/R/W if bit 4 (ENABLE SEEK DONE) is set.

11.15.4.2 HEADS IN MOTION - HEADS IN MOTION H (AC1) is asserted when the read/write heads on the
selected drive are in motion (Figure 11-21).
11.15.4.3 SEEK FAIL - SEEK FAIL (AC3) is set (1) when the DSK FAIL L signal from the RK05 is asserted
(Figure 11-21). DSK FAI L is asserted by the selected disk drive if it fails to seek the cylinder address specified by
program. A recalibrate operation must be executed by the program to clear this error condition.
11.15.4.4 DRIVE STATUS ERROR - The DRIVE STATUS ERR (AC6) is set when the selected disk drive is not
ready (i.e., not turned on~ by FILE READY Lfrom the RK05 (Figure 11-21). Some action must be taken by the
operator to clear this bit, i.e., power up the affected RK05.
11.15.4.5 CONTROL BUSY ERROR - CONTROL BUSY ERROR is set (1) if the program tries to do a DLAG,
DCLR with AC=10, DLDC, or DLCA instruction while the IDLE flip-flop is cleared (Figure 11-21). Note that the
control is busy unless the IDLE flip-flop in the Major States Register is set. This error occurs most often when new
programs are debugged, a rewrite of the program or routine that caused the error should eliminate the problem.
11.15.4.6 TIME OUT ERROR - TIME OUT ERROR is set (1) if the control has been busy for more than 280 ms
(Figure 11-21) or more than 7 revolutions of the disk cartridge. The DSK INDEX MK L signal is asserted once for
each revolution of the disk and applied as the clock input to the 74193 IC (see Section 7 for pin locations and logic
diagram). The 741~3 IC is a 3-bit binary counter that sets the TIME OUT ERR bit in the Status Register if the Major
States Register remains in some state other than IDLE for 280 ms. The binary counter is cleared each time the Major
States Register goes to the IDLE state and starts a new countdown each time the IDLE flip-flop is cleared.
11.15.4.7 WRITE LOCK ERROR -WRITE 'LOCK ERROR (AC7) is set if. the program tries to do a write
operation on a disk drive that has been write protected (Figure 11-21). If the selected disk drive has been write
protected, DSK WRT STATUS L from the write protected disk drive is high and the WRT LOCK ERR flip-flop sets
when the WRT CMD is issued by the program. The WRT LOCK ERR flip-flop in the RK8-E is cleared by LD DISK
ADDRS H if the affected disk drive is deselected. The WRT PROT switch of the affected disk drive must be
depressed to allow data to be written on any drive that has been write protected. Note that a disk drive is write
protected by programming the write protect function or by depressing WRT PROT switch on the RK05 (Table
11-13).

11-78

6RK2 H(DCLR)

»--.-- CLR STATUS L

BTP3 OK H --'---~,
CLR ALL H

6RK2 H( DCLR
B DATA 11 L

E45
I-'B:..:U:..:S,-Y~E,-,RccR,--_ _ _ _ _ _ _ _ _---\

SET BUSY ERR H
SET CRC ERR H
SHORT TP3 H
IDLE (0) H----c_ _

E50

SET TIME OUT ERR H

STATUS

SET STATUS ERR H

7~E9G6

j-'C"'R.o.:C"--'Eo.CR"R-'----_ _ _ _ _ _ _ _ _ _-/
TIME OUT ERR H (AC BIT 6)
DRIVE STATUS ERR H(AC BIT 10)
CYL ADDR ERR H(AC BITH)

NOT EQUAL (0) H

r----(FROM RK05)DISK INDEX MK L

END STATE (0) H-~_ _

+3V

FROM RK05
DSK WRT STATUS L

WRT LOCKL----\
ERR (1) H (AC BIT 7)

WRT CMD L

IDLE (1) H
+3V

E52
WRT
LOCK
ERR

E43
(74193)
BINARY
COUNTER
2BOms

LD DISK ADDRS H

WRT LOCK ERROR (0) H

CLR STATUS L
HI RD CLK H
DB ·CONT (1) H
FROM RK05 CAPACITY EX L

1 DATA RQST LATE(1)H (AC BIT 9)

DB CONT 4 (0) H
CLR DRIVE CMD L

E39
DATA
RQST
LATE

LD DISK ADDRS H
DATA CLK OK H

CLR STATUS L

r - --,

I NOT

DSK ROY
S/R/W H

SECTOR SEEK (0) H
NOT EQ (0) H E51

------,

o DATA RQST LATE (0) H

E43

I EQUAL
M7105
L __ J

I
I
I
H
I
I

HEADS IN MOTION H

SET CYL ADDRS ERR H

RDY S/R/W L
DONE FLAG (1) H
(AC BIT 1)

6RK2 L

E39
DONE

IDLE (1) H
ENABLE SEEK DONE H
ROY S/R/W H

IDLE (1) H

FROM RK05
E42
DSK SEEK FAIL L1:>SEEK FAIL H (AC BIT 3)

.J
Figure 11-21

FILE RDY H

o DONE FLAG(O)H

DRV STATUS BAD
lAC BIT 10)

I
I
L -------~
6E-0594

Status Register

11.15.4.8 CRC ERROR - The CRC ERROR (AC8) bit is set if the CRC character read from the disk drive does
not equal the CRC computed by the CRC Register during a read operation. The CRC character read from the disk
during the CRC state is compared bit-by-bit with the CRC character computed by the RK8-E (Figure 11-12). If the
CRC characters are not equal, NOT EQUAL (0) H is asserted low and when the Major States Register enters the
. END state the CRC ERROR bit is set.
11.15.4.9 DATA REQUEST lATE - DATA REQUEST LATE (AC9) is set if the processor does not respond to a
BRK RQST within 22.5 J.l.s. If the processor does not respond in time, the Data Buffer Register is emptied during a
write operation or filled during a read operation. This causes one or more data words to be lost. The DATA RQST
lATE flip-flop (Figure 11-21) is set by one of the following:
a.

HI RD ClK and DB CONT 1 (H) during a read operation. This condition indicates the Data Buffer
Register is full and there is no room for new data.

DATA ClK OK H and DB CONT 4 (0) H during a write operation. This condition indicates the Data
Buffer Register is empty and there is no data to be written on the disk cartridge.

11.15.4.10 DRIVE STATUS ERROR - DRIVE STATUS ERROR (AC10) is set if DRIVE STATUS BAD H is
asserted and the program initiates a load disk address (DlAG), attempts a clear drive command operation, or if the
disk capacity is exceeded (disk address greater than 312 8 ). The conditions that cause DRIVE STATUS BAD H to be
asserted are given in Table 11-12, bit 10.
11.15.4.11 CYLINDER ADDRESS ERROR - CYLINDER ADDRESS ERROR (AC11) i,s set if the HEADER
word of a sector does not agree with the cylinder address sent to the disk drive. The HEADER word is read from a
sector during the HEADER C major state and compared with the cylinder address in the CRC Register. If the
HEADER word and the cylinder address in the CRC Register (Figure 11-12) are NOT EQUAL, CYLINDER ADDRS
ERR is set and the TRANS FER DON E flag sets.
11.15.5 ERROR Flag
The ERROR flag is asserted by any of the following errors, which also set bits in the Status Register.
a.
b.
c.
d.
e.

BUSY ERR
CRC ERR
TIME OUT ERR
DRIVE STATUS ERR
CYl ADDRS ERR

If the ERROR flag is set and the DSKP instruction is executed by the program, the SKIP line is grounded. This
causes the program to skip an instruction (Figure 11-19). If the INTERRUPT ENABLE bit in the Command Register
(bits) is a 1 and the ERROR flag is set, the program will be interrupted by an INT RQST (Figure 11-19).
11.15.6 Sector Address Comparator
The sector address comparator (Figure 11-22) compares the address in the Surface Sector Register with the sector
address read from the selected disk drive during the HEADER C major state. The comparator is a 7485 IC (see
Section 7 for truth table, pin locator, and logic diagram) that asserts SECTOR EQ H when the two 4-bit inputs are
equal.

11·80

SECTOR SEEK (1) H

I
I

DSK SEC 8 L

DSK SEC 4 L

RK05
SECTOR
ADDRESS

DSK SEC 2 L

L - -

E47
COMPARATOR
(7485)

DSK SEC 1 L

'-I
SECTOR EQ H

HEADER D

L_.-J
r

SECTOR ADDRS 8 H
SU RFACE t-'S:..:E:..::C.:...TO::.:Rc:....:..:A::.:DD::..:R.:::S:....4.:.....:..;H~--I
SEC-TOR
SECTOR ADDRS 2 H
REGI STER I-=:..::.:...::.:.:.....:..:::=-~::..::.~--f
SECTOR ADDRS 1 H

8E-0589

Figure 11-22 Sector Address Comparator

11.15.7 Data Break Control Logic
The data break control logic (Figure 11-23 and 11-24) enables the RKS-E to assume control of the CPU Major
Register gating and directly address via the Current Address Register, memory locations associated with a data
transfer. The priority network compares the priority of the RKS-E with other peripherals making BRK RQST at the
same time. If the RKS-E has the highest priority, the controller asserts signals indicating the RKS-E has accepted the
request at INT STROBE time. When the RKS-E asserts BREAK, the single cycle data break is started, a data word is
transferred to or from the address indicated by the Current Address Register. If the transfer is from the RK05 to
memory, the data is applied to the Data Bus (DAT AO-DAT A 11) by the transfer control logic. Data transfers from
memory to the RK05 are taken from the MD lines (MDOO-MD11) and transferred to the RK05 via the Data Buffer
Register.
11.15.7.1 Current Address Register - The Current Address Register (Figure 11-23) and the EMA bits
(EMAO-EMA2) are used to select a location in memory to be used in a data transfer. The Current Address Register
is loaded with the address of the first memory location to be used in a data transfer when the 6RK4 (DLCA)
instruction is executed by the program. The RKS-E must be in the IDLE state (control not busy) when the CA
Register is loaded. DATA ENABLE (1) H (Figure 11-24) is asserted at TP4 time to increment the CA Register and
sequentially select locations in memory for data transfers. The contents of the CA Register are applied to the
OMNIBUS when MAK (1) H is asserted during a data break.
The CA Register consists of three DEC 74161 ICs (see Section 7 for timing diagram, logic diagram, and pin
locations). The DEC 74161 IC is a presetable binary counter with clock input for incrementing. Note that the clock
input and the control input (load) must be asserted to load the CA Register.
The EMA bits (EMAO-EMA2) from bits 6 through S of the Command Register are applied to the OMNIBUS when
DATA ENAB (1) H is asserted by the control logic (Figure 11-24) to select a memory field (0-7). The EMA bits are
not incremented and the Command Register must be changed by the program to change memory fields.

11·S1

CLR ALL L
B DATA 0 H
B DATA 1 H
B DATA 2 H

EMA 0 H

B DATA 3 H
COMMAND
REGISTER
(BITS 6.7
AND 8)

EMA 1 H

EB
CA
(0-3)
74161
LOAD

CLOCK
CLR ALL L

CARRY

I
I
I
I

EMA 2 H
B DATA 4 H
B DATA 5 H

DATA ENAB (1) H

B DATA 6 H
B DATA 7 H

E21
CA
(4-7)
74161

B TS4 H
CLOCK

DATA ENABLE (1) H

CLR ALL L
6RK4 L (DL A)
IDLE (0) H

B DATA 8 H
B DATA 9 H

B TP3 OK H

B DATA 10 H
B DATA 11 H
CLOCK

* Indicates Missing Logic(Ali bits of Memory Address Gated
through identical logic)

6RK4 L ( DLCA)

** OMNIBUS SIGNALS

MAK (1) H

BE-0591

Figure 11-23 Current Address Register

TS4 L

DATA OL

E42

~=i-w~~-,*-g
~~W5~ - ,,"W1
D~A1~
l
+3V

r -SRK-'"

I COUNTER

E43
BLAST BRK H

DATA ENAB (I) H D

MALC(I)H

04
BTP1 H

r-:=:':":":"':':"Hc

MALC

I LAST BRK(1)H
E45
LAST

I DATA ENAB(1)H

><>--------Ic BRK 0 lAST BRK(O)H

L ~7~0~..J
CLR ALL H

LD DISK ADDRS H

E 28 )o_.-::.ST:..:A::.:Rc..:T_C::.L::::R.:....::L_ _ _--'

MAIN Pl H
BDATA 6 H

+3V

BRK IN (I)

Hr--'''-I-+--~K!1I[ill!!.':~

+3V
BTPI H
MAD H D E45

MAK (1) H

MAK

MAIN (I) H

WRT BUFFER
-

E35
BRK
DIR

DATA L

1 MAK(1) H

o MAK(O)H

CLR ALL L

BRK ENAB CLK H
SET MAIN BRK H

cio
w

r;,/;;;71;; - - - I
I
L -

CLR ALL l

l
BRK ENAB ClK H
D E48
BRK
IN

DATA STATE (1) H
READ (1) H

- -- -

* BRK IN PROG L
DB CaNT 1(a) H
LAST BRK(O)H

~r_---------~B~R~K~R~Q~S~T~H-------------~D

B BRK RQST H D

I NBR(lI H

E38

E35

BRK

NBR 0 NBR(O)H

r - - - - - i c RQST 0

I
I

* CPMA DISABLE L

* OMNIBUS SIGNALS,SEE CHAPTER 9 OF THE SMALL
COMPUTER HANDBOOK-1972 FOR DESCRIPTION OF
THESE SIGNALS

WRT BRK L
DB CONT 2 (0) H

*INT STROBE H
B INT STROBE H

READ BRK L
IDBCONT3(1JH

L __

_-.l
Figure 11-24 Single Cycle Data Break
Control logic

8E-0598

11.15.7.2 Data Transfer Control Logic - The data transfer control logic (Figure 11-24) determines the direction
and type of data transfer. The BRK ENAB flip-flop is set immediately if a write operation is initiated or when the
Major States Register enters the DATA state during read operations. BRK ENAB (1) H supplies an input to E37 and
E46 to allow a BRK ROST if other conditions are met. BRK IN is set during read operations and cleared during
write operation to enable either E37 during read breaks or E46 during write breaks. During read operations, E37 is
enabled by DB CONT4 (1) Hand BRK IN (1) H to assert READ BRK L and initiate a BRK ROST at TP1 time. DB
CONT4 (1) H is asserted (high) when DB4 in the Data Buffer Register is full. A new BRK ROST is made each time
DB4 is filled until the data transfer is complete. BRK ROST is cleared during a read break when MAK (0) H is low if
DB3 in Data Buffer Register is empty. Note that DB CONT3 (1) H is low when DB3 is empty which enables E28 and
allows BRK ROST to clear at TP4 time if the MAK flip-flop is set. If DB3 is full, BRK ROST is not cleared and a
new break cycle is started to transfer new data. The data in DB3 is transferred to DB4 as soon as DB4 is empty; thus,
the data in DB3 is in DB4 when the next break cycle starts.
During write operations, E46 is enabled to assert WRT BRK L if BRK IN is cleared, BRK EN is set, LAST BRK (0)
H is asserted, and DB1 in the Data Buffer Register is empty. DB CONT1 (0) H is true to enable E46 and make a
BRK ROST at TP1 time when DB1 is empty. BRK ROST is cleared at TP4 time if MAK is set to negate MAK (0) H
(low) and DB2 is full. If DB2 is empty, DB CONT2 (0) H disables' E28 and the BRK ROST flip-flop is not cleared. If
DB2 is empty, the data in DB 1 is transferred immediately to DB2 and a new break cycle is started to fill DB 1 if the
RK8-E has the highest priority.
The data transfer control logic tries to keep the Data Buffer Register full during a write operation and empty during
a read operation via the single cycle data break.
11.15.7.3 Priority Logic - The RK8-E must have the highest priority to allow a break cycle when a BRK ROST is
made. DISK PRIORITY H (Figure 11-24) is asserted by a ground (W1 installed) on the input of E42 if the RKS-E is
assigned the highest priority (0).' DATA 0 L (highest priority) or DATA 1 L are asserted by the output of E3S when
the NBR flip-flop is set to prevent other peripherals from doing a break cycle when the RKS-E has priority. If
priority 1 is selected for the RKS-E, jumper W3 is installed. When a peripheral with priority 0 makes a BRK ROST,
E32 is enabled to supply a high to the input of E42. A high on E42 negates PRIORITY H and the HKS-E must wait
until DATA 0 L is negated by the peripheral with the highest priority.
Thus, when DISK PRIORITY H is asserted and a BRK ROST is made (NBR is set). a break cycle is started. NBR is
set at INT STROBE time if BRK ROST is set. When NBR sets, CPMA DISABLE Land BRK IN PROG L are asserted
on the OMNIBUS to start a break cycle. The OMNIBUS signals are explained in Chapter 10 of the Small Computer
Handbook - 1973.
11.15.7.4 CPU Control Logic - The CPU control signals are asserted by the RKS-E at TP4 time if DISK
PRIORITY H is asserted. DATA ENABLE is set at TP4 time to assert BRK CYCLE Land MSIR DISABLE L (see
Chapter 10 of the Small Computer Handbook - 1973 for description of signals). BRK DIR is set during read breaks
by BRK IN (1) H to assert MD DIR L. MD DIR L is asserted to allow data to be transferred from memory to the
RKS-E (write) and is negated to transfer data from the RKS-E to memorY.
The next TP1 pulse after DATA ENABLE is set causes the MAK flip-flop to set and assert MA, MS LOAD CONT L.
This inhibits loading of the MA, MS Registers by the processor and allows the contents of the CA Register applied to
the MA lines to select a location in memory for this data transfer.
MAK is set at the same time as DATA ENABLE. The clear side of MAK is used to clear BRK ROST at the end of a
BRK cycle if DB2 is full during write operations or DB3 is empty during read operations.
The LAST BRK flip-flop is set and BLAST BRK H from the break counter is asserted when the data transfer is
completed. The zero side of LAST BRK disables E46 and removes WRITE BRK L from the BRK ROST flip-flop to
stop write breaks. READ BRK L is negated when E37 is disabled by the loss of DB CONT4 (1) H to stop read
breaks.

11-84

The data break control logic is cleared when the load disk address (DLAG) instruction is executed by the program or
by CLR ALL L which is asserted when the DCLR instruction is executed.
11.15.8 Data Buffer Register and Control Logic
The Data Buffer Register (Figure 11-25) and its associated control logic (Figure 11-26) has the following functions:
a.

During read operations, serial data is shifted into DB 1 by the RD ClK pulses and transferred to DB4 via
DB2 and DB3 as 12-bit parallel words. The 12-bit words are then transferred to memory by the single
cycle data break. The single cycle data break control logic tries to keep the Data Buffer Register empty
so that there is space for temporary storage of data transferred from the disk.

During write operations, a 12-bit parallel word is transferred from memory to DB 1. The 12-bit word is
transferred to DB4 via DB2 and DB3. The 12-bit word is shifted out of DB4 by the WRT BUFF SHFT L
signal. The output of DB4 is supplied to the write control logic ~s 12 bits of serial data to be written on
the disk between clock pulses (Figure 11-2).

During maintenance operations, the contents of CRC Register, Command Register, or the Surface/Sector
Register are shifted into DB4 by the lO MAIN SHFT L pulse. The DMAN instruction is used to generate
the LO MAIN SHFT L signal (Table 11-14). The contents of DB4 are transferred to the AC via the Data
Bus by the DMAN instruction. Thus, the program can read and evaluate the contents of the Command
Register, CRC Register, and Surface/Sector Register during maintenance operations or error check
routines. The flow diagram in Figure 11-15 illustrates these maintenance operations, and Table 11-14
gives the AC bit requirements to accomplish the maintenance operations.

11.15.8.1 Data Buffer Register Control Logic - The Data Buffer Register control logic (F igure 11-26) provides
control signals to the Data Buffer Register (Figure 11-25). The DB control logic consists of a Control Register and a
DB clock with gating logic to aid in the control operations. The Control Register consists of four J-K master slave
flip-flops with clock inputs. The unique features of these flip-flops are: 1) a clock pulse will not cause any
transition in the flip-flop if neither the J or K inputs are enabled during the clock pulse and 2) if both the J and K
inputs are enabled during the clock pulse, the flip-flop will complement (change states). The J or K inputs are
enabled only when the input is of a state different from the present condition of the flip-flop, i.e., if DB 1 is in a 1
state only a 0 state input will cause the flip-flop to change state. When the flip-flops are in a 1 state, the Data Buffer
Register associated with that flip-flop is considered to be full, i.e., if DB1 control is in a 1 state, DB1 is full. When
the flip-flops are in the 0 state, the registers are considered to be empty.
The DB clock is made up of one 74123 IC (see Volume I, Appendix A for logic diagram and pin locations). This IC
is a dual one-shot multivibrator that outputs a pulse of a specified duration each time the input is enabled. The
duration of the output pulse is determined by an external capacitor and resistor, i.e., R7 and C38.
DB ClK H out of the first 74123 IC is a 50 ns pulse that is asserted when one of the inputs to E6 are enabled to
cause the input to make a high-to-Iow transition. One of the inputs to E6 is enabled when one of the Data Buffer
Control flip-flops is to be loaded. The pulse out of the first 74123 triggers the second 74123 IC and disables the
input to the first IC, also disabling the 0 ~ DB4 signal for 150 ns. This allows the completion of a data transfer
before a new DB ClK pulse is generated. Without this delay, the Control Register would attempt to load a register
before the output of a register has been transferred into another register (i.e., DB2 ~ DB3) or to the Data Bus (i.e.,
DB4 ~ Data Bus). Note that the clock pulse is initiated only when the correct conditions exist to load one of the
Data Buffer Registers and is disabled by the clear side of the second IC to allow time for a data transfer
(register-to-register or register-to-disk or processor).

11-85

r - -- I

DATA ENABLE (1) H
BRK DIR (0) H
E6

I H I RD CLK L

HI RD CLK H

WRT CMD L

E20

E18

E19'\ LD RD BUFF H

BTP 3 L

MD 0

B MD 0

t 1- -- -1111

HI DATA IN H

E3
P/O OBI

( 7495A)

[)-

E5
P/O OBI

p---

'-<l

(7495A)

SERIAL

I
+ 3V (1)

E4
P/O DB2
(74174)

El0
P/O DB3
(74174)

+3V(1l

B MD 11

--*-MfOf M 1

t11 i-

P-

--<

E32
P/O OBI
(7495A)

P-

P----

E25

+3V(1)

P/O DB2

MOil
E42 [

MD-RK L

L - - -

SERIAL

DB CONT
2 (1) H

I
I

[ MD-RK L

I
I
I
-.J

DB CONT

2(1) H

(74174)

DB CONT
3(1) H

E18

+3V(1l

DB CONT
3(1)H

P/O DB3

(74174)

.....
.....

1
LO MAIN DATA H
E31

LO MAIN SHIFT L
SHIFT WRT BUFF L

J E20

----

WRT BUFF
SHIFT L

E9
P/O DB4

(7495A)

P-

-<:

--- ---

E17
P/O DB4
(7495A)

DB CONT 4(0)H

P-

r--

--- -

. - - - . 1-DB4 H
·E24
P/O DB4
(7495A)

dB4H
(El1IDBCLKH

----.....

SERIAL DATA TO WRITE LOGIC ( M7106)
E16
RK DATAII H

* INDICATES PORTIONS OF IC NOT SHOWN

" "'''

"'}

OUTPUT TO

DATA MULTIP LEXER
1* RK DATA 0 L (See
Figure 4 -19)
RK DATA 0 H
E23
8E-0599A

Figure 11-25 Data Buffer Register (sheet 1)

PIC M7105

6RK7 OK H-------I
MAIN ENAB H - - - - - J
B DATA 5 H-~-----I

HI RD ClK H
HIGH MAIN SHIFT l
HIGH MAIN DATA l

MAl N DATA H - - - - I

HI DATA IN H

EXT CYL ADDRS H
B DATA 3 H
CRC 16 (1) H
B DATA 2 H
SECTOR ADDRS 1 H
B DATA 4 H

lO MAIN SHIFT L

MAIN (1) H

B DATA 0 H

6RK7 OK L

E39
C MAl N a MAIN (0) H

CLR ALL L
8E-0599B

Figure 11-25 Data Buffer Register (sheet 2)

11_15.8.2 Data Buffer Control 1 and Data Buffer 1 - Data Buffer control 1 is used to control Data Buffer Register
1 (Figures 11-25 and 11-26). DB CONT1 is set to a 1 state when DB1 is loaded and remains in a 1 state until the
data is transferred to DB2. DB1 is loaded (DB CONT1 goes to a 1 state) during write breaks by data from memory
when LD RD BUFFER H is asserted by BRK DIR (0) H and DATA ENABLE (1) H (Figure 11-25). During read
operations, DBl is loaded with serial data so the input to DB CONTl is not clocked in until 12 bits are read from
the disk cartridge. When 12 bits are read and shifted into DB1 by the read clock, 12th BIT OK H is asserted and DB
CONT1 goes to a 1 state (DB 1 is full).
Note that during maintenance operations MAIN DATA can be shifted into DB1 by the 6RK7 (OMAN) instruction if
bit 5 in the AC is a 1. This allows the program to check the Data Buffer Register and control logic.
Data Buffer Register 1 consists of three 7495A ICs (see Volume I, Appendix A for logic diagrams, pin locations, and
truth table) connected in series to form a 12·bit register. During read operations, this register is loaded with 12 bits
of serial data from the disk cartridge. The output of DB 1 is a 12-bit parallel word that is transferred to DB2. DB 1 is
also loaded with a 12-bit parallel word from memory (write operations) that is transferred to DB2 when DB2 is
empty.
11.15.8.3 Data Buffer Control 2 and Data Buffer Register 2 - DB CONT2 is set to a 1 state when DB CONT1 (1)
H (DBl full) and DB CONT2 (0) H (DB2 empty) are asserted. The output of NAND gate E13 (1 -+ DB2) triggers the
74123 IC and generates a 50 ns clock pulse, which clocks 1 -+ DB2 H into DB CONT2. Note that DB1 is not
transferred to DB2 unless 1 -+ DB2 is asserted to cause a clock pulse to be generated. This stops a transfer from DB 1
to DB2 unless DB2 is empty.
Data Buffer Register 2 consists of two 74174 ICs (see Volume I, Appendix A for logic diagram, truth table, and pin
locations) that are connected in series to form a 12-bit register. This register is parallel loaded with 12 bits from DB 1
when DB CONT2 is set to a 1 state. The parallel output of DB2 is transferred to DB3 when DB3 is empty.
11-87

12th BIT OK H

DB CONT 1 (1) H
E 12 1 (DBl FULL)

WRT CMD L
LD RD BUFFER H
(LOAD DB)
DB CONT 2(1)H

>-----iC

Cg~T1

DB CONT 1 (O)H
(7473)0 (OBI EMPTY)

DB CONT 4 (1) H
DB CONT 1 (0) H
D
WRT BUFF--DATA H
BTP2 H

n------IC

E52
7474

DB CONT 2(1) H

DB2H (LOAD DB2)
J

CLR SYN (0) H

DB CLK H

1 DB CONT2(I)H
(DB2 FULL)

0 DB CONT 2(0) H

r ___---ttK:...(7~4_7-3..J) (DB2 EMPTY)

+5V

+3V

E12
DB

,-----------------------------~~~~CCONT

CLR ALL L
+3V

0--DB4 H

DB CONT 2 (0) H
l--DB3
(LOAD DB3)

DB CONT 3 (1) H

DB CLK H

E14
DB

1 DB CONT 3(1) H

(DB 3 FULL)

C C~NT
K

DB CONT3(0) H

7476 0 (DB3 EMPTY)

+3V

l--DB2 H
R7
1),-,H'-Ql
T --,4cc(ce
-,De.:B"--,,C;:e.0,-,-NC.DB CLK H

l-DB4
J
(LOAD DB4)
E14
DB CLK H
DB

1 DB CONT 4(1) H
(DB4 FULL)
DBCONT4~) H
4
O'I-"-'~::":"::'-=-=:='-':":
0 - DB4 H K(7476) (DB4 EMPTY)

~~~~~~~~~----------------------------~~~~CCONT
DB4 ENAB H
l-DB4 H

(LEAR DB4)

0 - - DB4 H

I
I
I
I

6RK7(DMAN)

0
TP2 H

B TP2 H

- -- -

rp/-;MA~E::C;:O:-

E21

BTP3 OK H

E38
7474

MAIN (l)H

CLR ALL H
LO DB-AC H

AC 7 (l)H

DATA STATE (1) H
WRITE (1)H
12th BIT OK H

AC 7 (O)H

L ____________ _ -.J

Figure 11-26 Data Buffer Register Control Logic

8E-0500

11.15.8.4 Data Buffer Control 3 and Data Buffer Register 3 - Operation of Data Buffer Control 3 and Data Buffer
Register 3 is identical to DB2 CONT and DB2, except that DB3 H is qualified by DB3 (0) and DB2 (1). DB3 is
loaded from DB2 when DB2 is full and DB3 is empty. The output of DB3 is transferred to DB4 when DB4 is empty
(DB CONT4 in a 0 state) and DB3 is full (DB3 in a 1 state).
11.15.8.5 Data Buffer Control 4 and Data Buffer Register 4 - Data Buffer Control 4 (Figure 11-26) is used to
control Data Buffer Register 4 (Figure 11-25). DB4 is loaded with the contents of DB3 if DB CONT3 (1) H (DB3
full) and DB CONT4 (0) H (DB4 empty) are negated to assert 1 --* DB4 H. This causes DB ClK H to be asserted and
DB4 goes to the 1 state (full).
During write operations, the contents of Data Buffer Register 4 are shifted out to the disk via the write logic (Figure
11-28) on the RK DATA11 line as serial data. WRT BUFF SHFT l is generated by the WRT ClK pulses (Figure
11-28), and shifts the data once for each clock pulse. When 12 bits of data have been shifted out to the disk, E26 is
enabled and DB4 ENAB H is negated. This clears DB4 to the 0 state and DB4 can be loaded again from DB3.
During read operations, DB4 receives a 12-bit parallel word from DB3 for transfer to memory via the Data Bus.
When WRT BUFF --* DATA H is asserted to transfer the contents of DB4 to the Data Bus (DATAO-DATA 11), ClR
SYN (0) H is asserted to enable NAND gate E34. Signal 0 --* DB4 H is asserted if the TEST ClK H pulse out of the
74123 IC is negated and 0 --* DB4 returns DB CONT4 to the 0 state when the next DB ClK H pulse occurs. When
DB CONT4 goes back to the 0 state, it is ready for new data to be transferred from DB3_
Data Buffer Register 4 consists of 3 7495A ICs (see Volume I, Appendix A for truth table, logic diagram, and pin
locations) that are connected in series to form a 12-bit register. The register is loaded with 12 parallel bits from DB3
when DB4 is empty and DB3 is full. During write operations, the 12 bits are shifted out to the disk as serial data.
During read operations, a 12-bit parallel word is transferred to memory via the Data Bus.
During maintenance operations, the contents of the Command Register, the CRC Register, and the Surface/Sector
Register may be shifted into DB4 of the Data Buffer Register, for transfer to the AC. To accomplish this, the MAIN
flip-flop must be set by transferring a 1 from the AC in bit position 1 using the OMAN instruction. This enables the
maintenance logic (Figure 11-25) and allows bits from the AC to shift data into DB4. Signals MAIN Pl Hand B
DATA 01 H are used to set DB CONT4 (Figure 11-26) and keep it in the 1 state, which disables transfers from DB3
while maintenance operations are underway. An input to DB4 is supplied by NOR gate E9 and NAND gate E30 as
lO MAIN DATA H. When a OMAN instruction is executed by the program, the following events can occur:
a.

If bit 3 in the AC is a 1 when the OMAN instruction is executed, bit 11 from the Command Register
(EXT CYl ADDRS H) is applied to DB4. Each time the OMAN instruction is executed by the program,
if bit 3 in the AC is set, a bit is shifted out of the Command Register and into DB4. When the contents
of the Command Register are in DB4 (12 shifts), if the OMAN instruction is executed and bit 7 in the
AC is a 1, lO DB --* AC l is asserted to transfer the contents of DB4 to the AC via the Data Bus.

If bit 2 in the AC is a 1 and the OMAN instruction is executed, the contents of the CRC Register are
shifted into DB4. This operation is the same as that listed above for the Command Register. Note that
the program must keep track of the number of shifts required to shift all of the bits into DB4. The CRC
Register is transferred to the AC with the same instruction and AC bit used for the Command Register.

If bit 4 in the AC is a 1 and the OMAN instruction is executed, the contents of the Sector/Surface
Register are applied to DB4. This shift and transfer operation is the same as the other maintenance'
operations.

The MAIN flip-flop must be cleared using the DClR instruction after maintenance operations are completed.

11-89

11.15.9 Output Data Multiplexer
The output data multiplexer (Figure 11-27) selects either the contents of the Status Register or DB4 to be applied to
the Data Bus. The output data multiplexer consists of three 8235 ICs (see Volume I, Appendix A for truth table,
logic diagram and pin locations) that are controlled by the 6RK5 (DRST) instruction and enable RK DATA l. If lO
DB -+ AC is asserted during maintenance operations or WRT BUFF DATA l is asserted during read operations, RK
DATA 0 l through RK DATA 11 l from DB4 are applied to the Data Bus. If the 6RK5 (DRST) instruction is
executed by the program, the contents of the Status Register are applied to the Data Bus for transfer to the AC.

RK DATA 0 L
RK DATA 1 L
RK DATA 2 L
RK DATA 3 L
DONE FLAG (1) H
RDYS/R/W H
GND
SEEK FAIL H

E8
(8235)

DATA 0 L
DATA 1 L
DATA 2 L
DATA 3 L

RK DATA 4 L
RK DATA 5 L
RK DATA 6 L
RK DATA 7 L
DISK FILE ROY L
BUSY ERROR H
TIME OUT ERROR H
WRT LOCK ERROR H

E22
(8235)

DATA 4L
DATA 5 L
DATA 6 L
DATA 7 L

RK DATA 8 L
RK DATA 9 L
RK DATA 10 L
RK DATA 11 L
CRC ERROR H
DATA RQST LATE H
DRIVE STATUS ER H
CYL ADDR ER H

E49
(8235)

DATA 8 L
DATA 9 L
DATA 10 L
DATA 11 L

6RK5 (DRSTl

[";0 -;;7f~ -

DATA ENA8 (1) H
BRK DIR (1)H
B TS2 H

.LO D8-AC
WRT BUFF-DATA L

L __ __ J

ENABLE RK DATA L
8E- 0586

Figure 11-27 Output Data Multiplexer
11.15.10 Read/Write logic
The read/write (Figure 11-28) logic provides a clock for generation of clock and data pulses to be written on the disk
cartridge, the READ DlY logic, and logic to separate RD ClK pulses and READ DATA.
11.15.10.1 Write Clock - The write clock is a 2.88 MHz crystal-controlled oscilrator that generates the WRT ClK
pulses. When the WRITE flip-flop is set during SK/CHK/WRT or SK/WRT operations, the output of the write clock
is enabled to clock E41. The set side of the E41 flip-flop is tied to the data input so that E41 is set and cleared on
alternate clock pulses. This enables a NAND gate for WRT ClK pulses when E41 is set and a NAND gate for WRT
DATA pulses when E41 is cleared. Thus, WRT ClK pulses and WRT DATA pulses are applied as an output to the
RK05 from NOR gate E27. Note that the data pulses occur between clock pulses and a bit cell (Figure 11-2), and are
written on the disk cartridge in this manner. The CRC bits (CRC 16 (1) H) from the CRC Register (during CRC
state) and the SYNC bit (at end of write delay) are applied to E27 as data pulses to be written on the RK05 between
WRT ClK pulses.
During the DATA state, the WRT ClK pulses are used to generate WRT SHFT CRC H, which is used to compute the
CRC character (Paragraph 11.15.11).
11-90

DATA STATE (0) H

PIa M7106

SHFT WRT

BUFF l

B WRT ClK l

1'"

o,_~

-r-

~~5_7~
____

+5V
E36 WRT CMD l

SK/CHK/WRT l
, WRITE(1)H
SK/WRT l

D E48
WRITE
(7474) WRITE(O) H
HEADER D (1) H C
0
DATA
CLOCK
OK H
lO MAIN SHIFT l

HEADER E(O)H

B WRT ClK l
E40

CRC STATE (0) H

WRT SHFT CRC H

~-------------------------ct

READ(ll H

E37
READ
(7474)

RD ClK 2 l
READ(O) H

8E-0601

Figure 11-28

Read/Write Logic

11.15.10.2 Read Delay - The READ DL Y is a 74123 IC that delays the setting of the READ flip-flop, and the
read operation for 85 IlS. This allows the controller to wait for the SYNC bit before the Major States Register
advances to the HEADER E major state.
The 74123 is a one-shot multivibrator that is triggered when SECTOR MK H makes a low to high transition and
outputs of 85 IlS READ DL Y pulse. After 85 IlS, the READ flip-flop is set; after the SYNC bit is read, a read
operation is started. The set side of READ is applied to the RK05 as DSK READ L to cause the RK05 to read data.
The clear side of READ enables gates to allow RD CLK H and READ DATA IN L pulses to be applied to the RK8-E
Data Buffer Register and control logic.
11.15.11 CRC Register
The CRC Register (Figure 11-29) is used to store the disk address and compute a CRC character during read and
write operations. The CRC character is computed during write operations and written on the disk cartridge at the
end of the data. During read operations, a CRC character is computed and compared with the CRC character that
was written at the end of the data. If the two CRC characters are not equal, the CRC ERROR flag is set.
11.15.11.1 Disk Address - The CRC Register (Figure 11-29) is loaded with the 8-bit disk address when the DLDC
instruction is executed by the program to assert LD DISK ADDRS H. The two 7496 ICs receive 7 bits
(DATAO-DATA6) from the AC and one bit from Bit 11 (EXT CYL ADDRS H) of the Command Register. The disk
address bits are applied to the RK05 Disk Drive during the STROBE major state (Figure 11-31) to select a cylinder
(
and surface on the selected disk drive.
The CRC Register stores the disk address until the Major States Register enters the DATA state. At this time, the
CRC Register is cleared by DATA STATE (0) H, which is negated (low). The CRC Register is also cleared by the
6RK3 (DCLR) instruction if it is executed by the program.
.
Note that the Load Disk Address instruction loads the Surface/Sector Register (Figure 11-29) at the same time the
CRC Register is loaded.
During the HEADER C major state, the HEADER word is read from the selected drive as DATA IN H and applied to
Exclusive-OR gate E24 (Figure 11-29). RD ClK 1 l asserts SHFT CRC H and shifts the contents of the CRC
Register out to E24. Thus, the contents of the CRC Register (specified disk address) and the HEADER word read
from the disk are compared bit-by-bit. If any bits are different, NOT EQUAL is set by the output of the
Exclusive-OR (E24) and the CYLINDER ADDRESS ERROR flag is set (Figure 11-21).
The CRC Register contains the disk address specified by the program until the Major States Register moves to the
DATA state. If CYLINDER ADDRESS ERROR is set, the TRANSFER DONE flag sets and the drive that produced
the error must be recalibrated.
The disk address may be transferred to the AC for evaluation by the program using the DMAN instruction. When the
disk address is transferred, the contents of the CRC Register are shifted out on CRC 16 (1) H to DB4 of the Data
Buffer Register (Figure 11-25). Signal MAIN PL is asserted each time the DMAN instruction is executed by the
program to shift the CRC Register one position and transfer one bit of the CRC Register to DB4. Note that AC bit
02 must be a 1 to enable the MAIN PL and assert CRC MAIN SHFT l. The program must keep track of the number
of shifts and determine when to transfer DB4 to the AC.
Note that when the control is in any state except the DATA state, the Exclusive-OR gates for CRC 2 and CRC 15
have a ground on one input. The ground causes these gates to have an output that is the same as the input, which
allows the contents of the CRC Register to be shifted and compared with the CRC DATA H input.

11-92

B DATA 3 H

, . . . - - - - , CRC 13 (I) H

PIa M7105

CRC 8 (I) H

B DATA 2 H

CRC 7 (1) H
B DATA I H
6 RK3 OK L

EI4
SHIFT
REG I STER
(7496)

CRC6(I)H

B DATA6 H

CRC5(I)H

B DATA 5H

CRC 4 (I) H

B DATA 4 H

E4
SHIFT
REG I STER
(7496)

SERIAL IN

NOT
EQUAL

LD DISK ADDRS H

,----------rD---......., (1) H

E34
NOT
EQUAL

cO
w

CRC
14 (1 )H
CRCI5

CRC
13 (1) H

(1) H

E23
HEX D
( 74174)

CRC 14
(1) H
CRC 3

(1) H

CRC 2
(I) H

CRCI
(1l H

I
I

SECTOR
ADDRS 2 H
SECTOR
su~~tCE
ADDRS 4 H
SECTOR
SECTOR
H
REG I STER r-l---'-Ac..::D-=:D_R-"S_8:....:.c..

I
I

I MAIN P L H

I
I
DSK
I
~~t~ L I
I
I

1--,,-,,-=-'-'-'-1

_________ ...1

I
I

B DATA 9 H
B DATA 8 H

B DATA 7H

1
CLR
DISK
AD L

SECTOR
ADDRS I H

B DATA 11 H
BDATAIOH

+3V

(0) H

--------..,

rp/OM710S-----I
I

NOT
EQUAL

ENB

SET ClK CLR

CLR
SECTOR

b--_ _ _.JAD L

8E-0596

Figure 11-29 CRC and Surface Sector Register

The Exclusive-OR gates for eRe 2 and eRe 15 are used in the computation of the eRe character (Paragraph
11.15.11.2) .
11.15.11.2 eRC Character Computation - To generate a CRe word, the block of data is treated as a number 3072
bits long which is divided (modulo 2) by a polynominal X I6 + XIS + X2 + 1. This division being shift and subtract
(modulo 2) is accomplished by shifting the CRe Register and Exclusively ORing eRe 2, CRe 15, and eRe 16
(Figure 11-30) as follows:
a.

The eRC Register is cleared at the beginning of the DATA state.

The CRC Register is shifted one bit position each time a bit is read or written by WRT ClK l or RD
DlK 1 L.

The bit, which is read or written, is compared with CRC 16 (Exclusively ORed) and the result is
Exclusively ORed with CRC 2 and CRC 15.

Using this method, a CRe character is generated for each block of data (256 words) that is written on or read from
tape.

8E-0585

Figure 11-30 CRC Computation Block Diagram

DRIVEOL~

CRC4H---1~

~DISK DRIVE 0 L

DSK CYL ADDR 128 L

DRIVE1L~

CRC 5 H --\--.,-----....

~DISK DRIVE 1 L

DSK CYL ADDR 64 L

DRIVE2L~

CRC 6 H --\--.,-----....
DSK CYL ADDR 32 L

~ DISK DRIVE 2 L

DRIVE 3 L ~ __ .

CRC 7 H --+-1-........

~DISKDRIVE3L

DSK CYL ADDR 16 L
CRC 8 H --1---1
DSK CYL ADDR 8 L
CRC 9 H --1---1
DSK CYL ADDR 4 L
CRC 10 H

--f--r-.....
DISK CYL ADDR 2 L

CRC 11 H --+---11-........
STROBE H _ _....L...--\

DISK CYL ADDR 1 L

P/O M7105
8E-0587

Figure 11-31

Disk Address Output Buffers

11-94

11.15.11.3 CRC Character Check - The CRC character that is computed for each block of data during a write
operation is written on the disk cartridge after the data during the CRC state. This is accomplished by shifting the
contents of the CRC Register out to the disk drive via the read/write logic (Figure 11-28). During the CRC state, the
WRT ClK pulse is used to shift the contents of the CRC Register.
During read operations, a CRC is computed as explained above and when the control moves to the CRC major state,
the CRC character written on the disk is read. DATA IN H is enabled by CRC STATE H (Figure 11-29) and applied
to E24 Exclusive-OR gate. As the CRC character is read from the disk the CRC Register is shifted by RD ClK 1 H
and a bit-by-bit comparison is made of the two CRC characters.
If any of the bits are different the output of the Exclusive-OR (E24) sets the NOT EQUAL flip-flop. If NOT
EQUAL is set, the CRC ERROR flag sets during the END state (Figure 11-2~).
The CRC character can be checked by the program using the DMAN instruction the same way the disk address was
checked (Paragraph 11.15.11.1).
11.15.12 MajorStates
The operation of the Major States Register (Figure 11-32) and the determination of the disk format is discussed in
Paragraph 11.14.7. The detailed logic is shown so that the reader can see all the signals required to enter each major
state.
11.15.13 R K8-E Counters
The R K8-E counters (Figure 11-33) are used to count the bits and words in a data transfer and keep track of the
number of data break cycles.
11.15.13.1 12-Bit Counter - The 12-bit counter (Figure 11-33) consists of 74161 IC (see Section 7 for truth table,
timing diagram, and pin locations) used as a binary counter. The 12-bit counter is incremented by RD ClK 2 l
(read) or WRT ClK l each time a bit is read or written. When 12 bits have been read or written, 12TH CARRY H is
asserted to indicate a 12-bit word has been read or written. Signal 12TH CAR RY H increments the word counter
each time 12 bits are read or written until 256 or 128 words have been transferred. If HALF BLOCK H is asserted,
12th BIT OK H is negated after 128 words are read or written.
During maintenance operations, HI MAl N SHFT L is asserted if the program executes the DMAN instruction and AC
bits 2, 3, or 4 are 1. This allows the program to check the counters and control logic.
The counters are cleared by CLR ALL L or ClR CNTRS L. Signal DATA CLR L is asserted each time the Major
States Register advances to the DATA state by a pulse out of the 74123 IC. The 741231C (see Volume I, Appendix
A for truth table, logic diagram, and pin locations) is a one-shot multivibrator that outputs a pulse each time the
DATA state flip-flop sets. The counters are also cleared each time the Major States Register enters the HEADER E
major state or when STATE ENAB B H is asserted when the Major States Register enters the CRC or HEADER C
major state.
11.15.13.2 Word Counter - The word counter (Figure 11-33) consists of two 74161 ICs (see Section 7 for truth
table, timing diagram, and pin locations) that are used as divide by 128 or 256 counters. The word counter is
incremented by 12TH CARRY L each time 12 bits of data are read or written. LAST WORD H is asserted after 256
words have been read or written. Signal 128TH WORD H is asserted after 128 words are read or written, and if
HALF BLOCK H is asserted (bit 5 in the Command Register must be a 1), the data transfer stops after 128 words.
Note that the disk drive continues to read or write zeroes until 256 words are read or written, but this data is not
transferred to memory. The TRANSFER DONE flag is not set until lAST WORD H is asserted after 256 words are
read or written.

11-95

16th BIT H

P/O M7106
SK/CHK/RD l
SK/CHK/WR l

)("")--------~D

ROY S/R/W.-DSK ACKNOWLEDGE l

,---L
o

. - - - HEADER
I E32

DSK OK H

HEADER
1 B (1) H

1 A (1) H

E19
HEADER
A
HEADER

HEADER C (1) Hl E27

HEADER
1 C (1) H
E20
HEADER
READ SYNC
C
HEADER

SK/WRT l

SK/RD l

E22
HEADER
B
HEADER

I E16 ~---T---I~~) H'LC--...--O--, B (0) H

SET SECTOR SK H

+3V

BIT l

S>I
J

SECTOR
1 SEEK (1) H
E24
SECTOR
SEEK SECTOR

~~ C (0) H

IL.C_....-O..JSEEK (0) H

IL-______~I _______+_I--~~----------------------+_----------~D~S~K~O~K~H----------------~I

IDLE (1) H

HEADER B (1) H I E26
'-ClR STATE H

SEC'TOR
MK H

HEADER CHI E26
IDLE (1) H _

IDLE (1) H

I E29

SECTOR SEEK (1) H

H6~?F~l\

rc;;:;A;;':-O;- -,

I
I
IL _ _ _ Jr

HEADER 0 (1) H ) E29

SECTOR
EQ H O I I--f----''--<H 0
SECTOR

HEE{~ER

ClR STATES H.....--....".

01--

HEADER
E (1) H

E22
HEADER
HEADER
E
E (0) H
r---C
0

16th BIT l

E22
DATA
STATE
C

DATA
STATE (0) H

END
STATE

J......, C R C

DATA
STATE (1) H

...---'L..

1~ST~A~T~E~(~1)~H-H~__- I 0
E21
CRC
STATE CRC
~ C
0 STATE (0) H

lAST
WORD

16th

1 (1) H

E21
END
STATE

END
STATE

-j

HEADER E (1) H ) E29~

IDLE (0) H

ClR STATES H

SET HEADER E l
REA 0 SYNC BIT l J E32 )0----------------1

CRC STATE (1) HI E63

ClR STATE S
DATA STATE (1) H ) E23 ) o - - - - - - - - - - . . . . J

IL-___________________________________________
ClR STATES H ~
END STATE (1) H ) E23 )0------------------------------'

FROM RK05 DSK SECTOR MK l

IDLE (0) H E35

B7IDlE(1)H

DISK
SECTOR
MK H E17
E54)
""'---

SECTOR.

u
.
JL-)

MKl~

WRT CMD H

SYN Dli

SEy3N8C
BIT
DlY
(140,,5)
74123 f---------'

']'

READ
DATA IN l

+5V
,....-D
11---------11 E27
WRT ClK HI
E37
WRT
WRT SYNC
WRT SYN (0) H
~C
0

----

+3V

-=
RD ClK 2 l

:..:-=--=.:--=--=--tc
READ (1) H

DATA
11----'..:1N.:.-('-...:1C-): : . . j H &
E15
RD ClK;] E8
DATA
IN
7474
DATA IN (0) H

f
8E-0602

Figure 11-32 Major States Register (sheet 1)

WRTCMO L
END STATE (I) H
.LAST BRK (I) H

P/O M7106

ERROR CLR L
CLR ALL L

rM) -;:r;M - - - - - -,
I

~I~~~~

Il _________ ..JI
STROBE (1) H
SEEK L
RESTORE(I)L

SEEK ONLY H

E25

+5V

.-----1-------~E9

WRT CMO L
END STATE (1) H

......

WRT CMO L

IDLE (I) H

E43
ONE
SHOT
(74123)
ERASE
OLY
C (25/JS) 0

EIS
IDLE

o I--__---=I.=:O.=:L=.E-,(.:::.0,-).:..:...H

OSK FILE ROY L

+3V

RESTORE ( 1) H
DSK RESTORE L

OSK WRT STATUS L

EIS
RESTORE
CLR DRIVE
CMO H C

F...:.::::
LE=--:c
Rc:::
O-,-Y--,H'1 0
L.:.

LO DISK AOORS H

WRT LOCKOUT L

ROY S/R/W
MAIN (0) H

STROBE ( 1) H
DSK STROBE L TO RK05

E19

CLR DRIVE CMO L

6RK3 OK H

FROM RK05
OSK ACKNOWLEDGE L

CLR STATUS H

STROBE
GO H

r-~----------~C

o STROBE (0) H

CLR STATES H
CLR STROBE L
ACKNOWLEDGE H

E25
8E-0580

Figure 11-32 Major States Register (sheet 2)

~;M~D-'

128th
WORD H

I REG I S TER I-H-A-L-F--l
L~"':..:. -.J

121h BIT OK H

INH 12th BIT (ll H
D

12th CARRY L

BLOCKH

E15
INHIBIT
12th BIT
+3V
12th
CARRY L

~~~~~~C~~~O

1--4-++---1 EN

INH 12th
BIT (0) H

E3
BIN ARY
COUNTER
(74161l

E2
BINARY
COUNTER
(74161 )

E4
BINARY
COUNTER
(74161)

LA ST WORD PL H
Ell

CLR
ALL L
+5V
INC CNTRS L
C3t

+3V

E43
ONE .sHOT
(74123)

161h BIT H

El
BINARY
COUNTER
(74161l

DATA
ENABLE (1) H

~----------------iEN

BLAST
BRK H

HALF BLOCK H
E6
BINARY
COUNTER
(74161)

COMMAND
REGISTER
BIT 5

E5
BINARY
COUNTER
(74161l

CLRALLL~~~+-------------------------------~

BTP3 OK H
6RK3 OK L

SE-0595

Figure 11-33

RKS-E Counters

11.15.13.3 16-Bit Counter - The 16-bit counter consists of a 74161 Ie (see Section 7 for truth table, logic
diagram, and pin location) that is used as a binary counter. The 16-bit counter counts the bits in a HEADER word or
CRC character as they are read or written. The 16-bit counter is incremented by R D ClK 2 or the WRT ClK, which
asserts INC CNTRS H. After 16 bits are read or written, 16TH BIT H is asserted and applied to the control logic.

During maintenance operations, the 16-bit counter is incremented by HI MAIN SHFT l when the DMAN
instruction is executed by the program. This allows the program to check the 16-bit counter and associated logic.

11.15.13.4 Break Counter - The break counter (Figure 11-33) consists of two 74161 ICs (see Section 7 for truth
table, logic diagram, and pin locations) that are used as a binary counter. The word counter is incremented at TP2
time of a break cycle (DATA ENABLE is set) to count the number of single cycle data breaks. BLAST BRK H is
asserted after 256 words have been transferred to or from memory. If HALF BLOCK H is asserted (bit 5 in the
Command Register must be a 1), data transfers stop after 128 words have been transferred. Signal BLAST BRK H
sets the lAST BRK flip-flop (Figure 11-27) and stops data transfer operations.

SECTION 5 MAINTENANCE

11.16 PREVENTIVE MAINTENANCE
The recommended preventive maintenance should be scheduled on a regular basis to maintain the performance and
reliability of the RK8-E and the RK05 Disk Drive system. Preventive maintenance schedules are found in the RK05
Disk Drive Maintenance Manual (DEC-OO-R K05-DAl. R K8-E diagnostics (Paragraph 11.5.1) are provided to test and
troubleshoot the R K8-E controller. These diagnostics should be run at regular intervals to verify the operation of the
RK8-E.

11.17 CORRECTIVE MAINTENANCE
The following programs may be loaded into memory from the Switch Register and used to monitor RK8-E signals
during troubleshooting operations.

NOTE
The program to check the data buffers in Paragraph 11.17.1
should be run first.

11-99

11.17.1

Check Data Buffers

This program provides a scope loop to check the Data Buffers by shifting 12 bits of data (ls or Os) from AC10 into
DBl. When DBl is full, a parallel transfer is made from DBl to DB2, DB2 to DB3, DB3 to DB4. When DB4 is full, it
is read into the AC with the maintenance lOT and stored in memory.
l.

Clear disk control logic

Enable maintenance logic

Enable shift to data buffer 1

Set AC1 0 to equal data

Issue maintenance lOT 12 times

Read data buffer 4

Example:
Location

Contents

7600
7601
7602
7603
7604
7605
7606
7607
7610
7611
7612
7613
7614
7615
7616
7617
7620
7621

7301
6742
1230
3231
7330
6747
7012
7012
7012
1232
6747
2231
5212
7200
1233
6747
3234
7402

Operation

Mnemonic
CLA CLL lAC
DCLR
TAD -12
DCA COUNT
CML RAR
DMAN
RTR
RTR
RTR
TAD AC 10 DATA
DMAN
ISZ COUNT
JMP-2
CLA
TAD K20
DMAN
DCA BUF REG
JMPSTART
-12
COUNT
AC10 DATA
K20
BUF REG

/ ENABLE CLEAR CONTROL (AC10=0 AC11=1)
/ lOT 6742 CLEAR CONTROL
/ DESI RED SHI FT COUNT
/ SET UP COUNTER
/ ENABLE MAINTENANCE MODE (ACOO=1)
/ lOT 6747 MAINTENANCE lOT

/
/
/ ENABLE CHECK DATA BUFFER (AC05=1)
/ GET DATA TO BE SHIFTED INTO DBl
/ lOT 6747 MAINTENANCE lOT
/SHIFTED ONE WORD YET?
/ NO, SHIFT ANOTHER BIT.
/ YES, CLEAR AC
/ ENABLE DB4 TO AC TRANSFER (AC07=1)
/ lOT 6747 MAINTENANCE lOT
/ STORE DATA WORD
/ (DEPOSIT A HL T TO MAKE ONE PASS)
7630/7766
7631 /
7632 / 0000 0 R 0002
7633/0020
7634/

11·100

11.17.2 Checking the Command Register
The following program is used to check the Command Register. The data is obtained from the Switch Register and
loaded into the Command Register. It is then shifted into the lower Data Buffer, and read into memory using
maintenance lOT instructions.
'
1.

Clear disk control logic

load Command Register with data from the Switch Register

Enable maintenance logic

Enable shift to lower buffer

Set AC03 (check Command Register)

Issue maintenance lOT 12 times

Read DB4

Example:
Location

Contents

Mnemonic

7600
7601
7602
7603
7604
7605
7606
7607
7610
7611
7612
7613
7614
7615
7616
7617
7620
7621
7622

7301
6742
1230
3231
7404
6746
7330
6747
7010
6747
7012
6747
2231
5213
7200
1232
6747
3233
5200

ClA Cll lAC
DClR
TAD -12
DCA COUNT
OSR
DlDC
ClA Cll CMl RAR
DMAN
RAR
DMAN
RTR
DMAN
ISZCOUNT
JMP-2
ClA
TAD K20
DMAN
DCACMD REG
JMPSTART
-12
COUNT
K20
CMD REG

Operation
/ ENABLE CLEAR CONTROL (AC10=0 AC11=1)
/ lOT 6742 CLEAR CONTROL
/ DESIRED SHIFT COUNT
/ SET-UP COUNTER
/ OR THE SWITCH REGISTER
/ lOT 6746 lOAD COMMAND REGISTER
/ ENABLE MAINTENANCE MODE (ACOO=1)
/ lOT 6747 MAINTENANCE lOT
/ ENABLE SHIFT TO lOWER BUFFER DB4 (AC01=1)
/ lOT 6747 MAINTENANCE lOT
/ ENABLE CHECK COMMAND REGISTER
/ lOT 6747 MAINTENANCE lOT
/ SHIFTED ONE WORD YET?
/ NO, SHIFT ANOTHER BIT
/ YES, CLEAR AC
/ ENABLE DB4 TO AC TRANSFER AC07=1
/ lOT 6747 MAINTENANCE lOT
/STORE WORD
/ lOOP OR HALT (HAL T=1 PASS)
7630/7766
7631 /
7632/0020
7633/

11-101

11.17.3 Check Surface and Sector Register
This program is used to scope the Surface/Sector Register and Data Buffer 4. The data to be used is entered into the
Console Switch Register (switches 5-11) then loaded into the Surface/Sector Register. It is then shifted into the
lower Data Buffer (DB4 bits 5-11) where it is read into the AC and stored in memory.
1.

Clear disk control logic

En,able maintenance logic

Load Surface/Sector Register with data from switches

Enable shift to lower Data Buffer

Enable shift Surface/Sector Register (AC04=1)

Issue maintenance lOT 12 times

Read DB4

Example:
Location

Contents

Mnemonic

7000
7001
7002
7003
7004
7005
7006
7007
7010
7011
7012
7013

7301
6742
1230
3231
7330
6747
7604
6743
7332
6747
7012
7010

CLACLL lAC
DCLR
TAD -12
DCA COUNT
CLA,CLL,CML,RAR
DMAN
LAS
DLAG
CLA,CLL,CML,RTR
DMAN
RTR
RAR

7014
7015
7016
7017
7020
7021
7022
7023

6747
2231
5214
7200
1232
6747
3233
5200

DMAN
IS2 COUNT
JMP-2
CLA
TAD K20
DMAN
DCASS REG
JMP START
-12
COUNT
K20
SS REG

Operation
/ ENABLE CLEAR CONTROL (AC10=0 AC11=1)
/ lOT 6742 CLEAR CONTROL
/ DESIRED SHIFT COUNT
/ SET UP SH 1FT COUNTE R
/ ENABLE MAl NTENANCE MODE (ACOO=1)
/ lOT 6747 MAINTENANCE lOT
/ LOAD THE AC FROM THE SWITCH REGISTER
/ lOT 6743 LOAD DISK ADDRESS
/ ENABLE SHIFT TO LOWER BUFFER (AC01=1)
/ lOT 6747 MAINTENANCE lOT
/ ROTATE AC AND LINK RIGHT TWO PLACES
/ ENABLE CHECK SURFACE AND SECTOR REGISTER
/ (AC04=1)
/ lOT 6747 MAINTENANCE lOT
/ SHIFTED ONE WORD YET?
/ NO, SHIFT ANOTHER BIT
/ YES, CLEAR THE AC
/ ENABLE DB4 TO AC TRANSFER (AC07=1)
/ lOT 6747 MAINTENANCE lOT
/STORE WORD
/ LOOP OR HALT (HLT=1 PASS)
7030/7766
7031/
7032/0020
7033/

11-102

11.17.4 Check CRC Register
This program is used to scope the CRC Register logic. AC bit 10, CRC Register, and Data Buffer Register 4 are
logically connected in series. A data bit is shifted 28 times through this series register to allow the last 12 bits to be
read from DB4.
1.

Clear disk control logic

Enable maintenance mode

Enable shift to lower buffer (DB4)

Load maintenance data into AC10

Check CRC Register (AC02=1)

Issue maintenance lOT 28 times

Read DB4

Sh ift 12 more data bits in

Read DB4

10.

Jump back to step 8

Example:
Location

Contents

7000
7001
7002
7003
7004

7301
6742
1230
3231
7330

7005
7006
7007
7010
7011
7012
7013
7014
7015
7016
7017
7020
7021
7022
7023

6747
7010
6747
7010
1232
6747
2231
5212
7200
1233
3231
1234
6747
3235
5204

Operation

Mnemonic
CLA,CLL,IAC
DCLR
TAD -28
DCA COUNT
LOOP·CLA,CLL,
CML,RAR
DMAN
RAR
DMAN
RAR
TAD AC10 DATA
DMAN
ISZCOUNT
JMP-2
CLA
TAD -12
DCA COUNT
TAD K20
DMAN
DCA CRC
JMP LOOP
-28
COUNT
AC10 DATA
-12
K20
CRC

/ ENABLE CLEAR CONTROL (AC10=0 AC11=1)
/ lOT 6742 CLEAR CONTROL
/ DESIRED SHIFT COUNT
/ SET UP COUNT
/ ENABLE MAINTENANCE MODE (ACOO=1)
/ lOT 6747 MAINTENANCE lOT
/ENABLESHIFTTO LOWER DATA BUFFER (AC01=1)
/ lOT 6747 MAINTENANCE lOT
/ ENABLE CHECK CRC REGISTER
/ LOAD DATA BIT INTO AC10
/ lOT 6747 MAINTENANCE lOT
/ SHIFTED ONE 12 BIT WORD YET?
/ NO, SHIFT ANOTHER BIT
/ YES, CLEAR THE AC
/ DESIRED SHIFT COUNT
/ SET UP COUNT
/ ENABLE DB4 TO AC TRANSFER (AC07=1)
/ lOT 6747 MAINTENANCE lOT
/ STORE WORD
/ LOOP OR HALT (HAL T=1 PASS)
7030/7744
7031/
7032 / 0000 0 R 0002
7033/7766
7034/0020
7035/
11-103

11.17.5 Single Cycle Data Break Transfers (Read Operation)
This program transfers data from the RK05 to processor memory. It can be used to scope the data break control
logic, Data Buffers, Current Address Register, Command Register, and the logic involved in read operation.
1.

Clear control logic

Enable maintenance mode

load AC from the Switch Register

load Command Register

Enable shift to lower buffer

Set AC03 to 1 (check Command Register)

Issue maintenance lOT 12 times

Current address = 0000

Set AC06 to 1 (check data break request)

10.

Issue maintenance lOT

Example:
Location

Contents

Mnemonic

Operation

7600
7601
7602
7603
7604
7605
7606
7607
7610
7611
7612
7613
7614
7615
7616
7617
7620
7621
7622
7623
7624

7301
6742
1230
3231
7604
6746
7330
6747
7010
6747
7012
6747
2000

ClA,Cll,lAC
DClR
TAD-12
DCA COUNT
lAS
DlDC
ClA Cll CML RAR
OMAN
RAR
OMAN
RTR
OMAN
ISZ COUNT
JMP-2
ClA Cll CMl RTl
RTL
RTl
OMAN
NOP
NOP
JMP START

/ ENABLE CLEAR CONTROL (AC10=0 ACll=1)
/ lOT 6742 CLEAR CONTROL
/ lOAD DESIRED SHIFT COUNT
/ SET UP SHIFT COUNTER
/ TRANSFER SWITCH REGISTER CONTENTS TO THE AC
/ STORE DATA IN lOCATION 0000
/ ENABLE MAINTENANCE MODE (ACO=l)
/ lOT 6747 MAINTENTANCE lOT
/ ENABLE SHIFT TO lOWER DATA BUFFER (AC01=1)
/ lOT 6747 MAINTENANCE lOT
/ ENABLE SHIFTTO COMMAND REGISTER (AC03=1)
/ lOT 6747 MAINTENANCE lOT
/ SHIFT ONE WORD YET?
/ NO, SHIFT ONE MORE BIT
/ ENABLE MAINTENANCE MODE
/ ENABLE DB4 TO AC TRANSFER

7326
7006
7006
6747
7000
7000
7402

/
/ lOT 6747 MAINTENANCE lOT
/ NO OPERATION
/ NO OPERATION
/ (DEPOSIT A HALT TO MAKE ONE PASS)

11·104

11.17.6 Single Cycle Data Break Transfers (Write Operation)
This program transfers data from processor memory to the Data Buffer. It is used to scope the write operation
control logic, Current Address Register, Command Register, and the data break control logic.
1.

Clear control logic

Enable maintenance logic

Set Command Register to write function

Load the AC from the Switch Register

Store data in location 0000 of memory

Enable break request bit

Issue maintenance lOT

Read DB4

Example:
Location

Contents

Mnemonic

7600
7601
7602
7603
7604
7605
7606
7607
7610
7611
7612
7613
7614
7615
7616
7617
7620
7621
7622

7301
6742
7330
6746
7604
3000
7330
6747
7012
7012
7012
6747
7000
7000
7200
1225
67.47
3226
7402

CLA,CLL,IAC
DCLR
CLA,CLL,CML,RAR
DLDC
LAS
DCAO
CLA,CLL,CML,RAR
OMAN
RTR
RTR
RTR
OMAN
NOP
NOP
CLA
TAD K20
OMAN
DCA DATA
JUMP START

Operation
/ ENABLE CLEAR CONTROL (AC10=0 AC11=1)
/IOT 6742 CLEAR CONTROL
/ ENABLE MAINTENANCE MODE (ACO=l)
/IOT 6746 LOAD COMMAND REGISTER
/ LOAD AC FROM SWITCH REGISTER
/ LOAD AC INTO LOCATION 0000
/ ENABLE MAINTENANCE MODE (ACO=l)
/IOT 6747 MAINTENANCE lOT
/ ENABLE THE
/ MAINTENANCE DATA
/ BREAK REQUEST (AC06=1)
/IOT 6747 MAINTENANCE lOT
/ NO OPERATION
/ NO OPERATION
/ CLEAR AC
/ ENABLE DB4 TO AC TRANSFER (AC07=1)
/IOT 6747 MAINTENANCE lOT
/STORE DATA
/ (DEPOSIT A HALT TO MAKE ONE PASS)

11-105

11.17.7 Single Cycle Data Break Transfers (Write then Read)
This program transfers data in the Switch Register to DB1 of the RKS-E, then reads the data back into memory after
it has transferred into DB4. The transfers are effected by causing one break request while the Command Register has
a write command in it, then causing another break request with a read in the Command Register. Finally, check to
see if the word read equals the word written.
1.

Clear control logic

load Command Register with a write function

load memory location 0000 with data from the Switch Register

Enable maintenance logic

I nitiate one single cycle data break request

load Command Register with a read function

Initiate one single cycle data break request

Check data read with data from Switch Register

Example:
Operation

Location

Contents

Mnemonic

7600
7601
7602
7603
7604
7605
7606
7607
7610
7611
7612
7613
7614
7615
7616
7617
7620
7621

7301
6742
7330
6747
6746
7604
3000
7326
7006
7006
6747
7000
7000
7200
6746
7326
7006
7006

ClACll lAC
DClR
ClA Cll CMl RAR
DMAN
DlDC
lAS
DCA 0
ClA Cll CMl RTl
RTl
RTl
DMAN
NOP
NOP
ClA
DlDC
ClA Cll CMl RTl
RTl
RTl

7622
7623
7624
7625

6747
7000
7000
5200

DMAN
NOP
NOP
JMPSTART

/ ROTATE AC AND LINK LEFT TWO
/ ENABLE MAINTENANCE DATA BREAK
/ REQUEST (AC06=1)
/ lOT 6747 MAINTENANCE lOT
/ NO OPERATION
/ NO OPERATION
/ (HAL T=1 TIME) (NOP=CHECK DATA)

ClACll
TAD 0

/ CLEAR AC AND LINK
/ lOAD AC WITH WRITE DATA

/ ENABLE CLEAR DISK CONTROL lOGIC
/ lOT 6742 CLEAR CONTROL
/ ENABLE MAINTENANCE MODE ACOO=1
/ lOT 6747 MAINTENANCE lOT
/ lOT 6746 lOAD COMMAND REGISTER (WRITE)
/ lOAD AC FROM SWITCH REGISTER
/ STORE WRITE DATA
/ ENABLE THE
/ MAINTENANCE DATA
/ BREAK REQUEST AC06=1
/ lOT 6747 MAINTENANCE lOT
/ NO OPERATION
/ NO OPERATION
/ClEAR AC
/IOT 6746 lOAD COMMAND (READ)

CHECK DATA
7626
7627

7300
1000

11·106

Location

Contents

7630
7631
7632
7633
7634
7635
7636

7040
3003
1001
0003
7440
7402
5200

Operation

Mnemonic
CMA
DCA 0003
TAD 0001
AND 0003
SZA
HLT
JMPSTART

/ COMPLEMENT WRITE DATA
/ STORE DATA FROM AC IN MEMORY
/ LOAD AC WITH READ DATA
/ COMPARE READ AND WRITE DATA
/ SKIP ON ZERO AC (GOOD DATA)
/HALT
/ JUMP TO START

11-107

SECTION 6 SPARE PARTS
Table 11-16 lists recommended spare parts for the R K8-E. These parts can be obtained from any local DEC office,
or from DEC, Maynard.
Table 11-16
R K8-E Spare Parts
DEC Part No.

Description

Quantity

11-00114
19-05542
19-05575
19-05576
19-05579
19-05585
19-05587
19-09004
19-09055
19-09056
19-09057
19-09061
19-09062
19-09267
19-09485
19-09486
19-09594
19-09615
19-09667
19-09686
19-09704
19-09705
19-09931
19-09935
19-10011
19-10018
19-10091
19-10155
19-10224
19-10363
19-10406
19-10436
19-10645
19-10650
19-10652
19-10656
18-10694

Diode, D664
DEC IC, 7474
DEC IC, 7400
DEC IC, 7410
DEC IC, 7440
DEC IC, 7476
DEC IC, 7473
DEC IC, 7402
DEC IC, 7495
DEC IC, 74HOO
DEC IC, 74H10
DEC IC, 74H52
DEC IC, 74H53
DEC IC, 74H11
DEC IC, 380
DEC IC, 384
DEC IC, 8251 B
DEC IC, 8271
DEC IC, 74H74
DEC IC, 7404
DEC IC, 314
DEC IC, 8881
DEC IC, 74H04
DEC IC, 8235
DEC IC, 7486
DEC IC, 74193
DEC IC, 7437
DEC IC, 7408
DEC IC, 7485
DEC IC, 7496
DEC IC, 75451
DEC IC, 74123
DEC IC, 75452
DEC IC, 74161
DEC IC, 74174
DEC IC, 74155
DEC Crystal Oscillator

1
2
2

11-108

1
1
2

1
2

SECTION 7 IC DESCRIPTIONS
11.18 DEC741551C
The 74155 IC (Figure 11·34) is TTL circuit used as a 2-line to 4-line decoder (unit select decoded and as a 3-line to
8-line decoder (function decoder) in the RK8-E. This IC may also be used as a 1-line to 8- or 4-line multiplexer, but
it is not used this way in the RK8-E and will not be discussed here.
When the 74155 IC is used as a 2-line to 4-line decoder, as with the unit select decoder, the 1YO through 1Y3
outputs are selected by applying +3V to pin 1 and leaving pin 2 low. The inputs in this configuration are applied to
pins 3 and 13 and the outputs (low) are taken from pins 4,5,6, and 7.
In the 3-line to 8-line configuration, as in the function decoder, external connections are installed to tie pin 1 to pin
15 and pin 2 to pin 14 (Figure 11-34). This allows both the 2Y and 1Y outputs to be used and provides for three
inputs instead of two. In this configuration, the 74155 IC becomes a BCD to decimal decoder, which decodes three
binary bits (Paragraph 11.15.3.1).
11.19 DEC 741931C
The DEC 74193 (Figure 11-35) monolithic circuit is a synchronous, reversible (up/down), 4-bit binary counter
having a complexity of 55 equivalent gates. Synchronous operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincidentally with each other when so instructed by the steering logic.
This mode of operation eliminates the output counting spikes which are normally associated with asynchronous
(ripple-clock) counters. Figure 11-35 contains the logic diagram and pin locations.
The outputs of the four master/slave flip-flops are triggered by a low-to-high level transition of either count (clock)
input. The direction of counting is determined by which count input is pulsed while the other count input is high.
The counter is fully programmable, i.e., the outputs may be preset to any state by entering the desired data at the
data inputs while the load input is low. The output will change to agree with the data inputs, independently of the
count pulses. This feature allows the counters to be used as Modulo-N Dividers by simply modifying the count
length with the preset inputs.
A CLEAR input has been provided which forces all outputs to the low level when a high level is applied. The
CLEAR function is independent of the count and load inputs. An input buffer has been placed on the CLEAR,
COUNT, and LOAD inputs to lower the drive requirements to one normalized load. This is important when the
output of the driving circuitry is somewhat limited.
This counter was designed to be cascaded without the need for external circuitry. Both BORROW and CARRY
outputs are available to cascade both the up- and down-counting functions. The BORROW output produces a pulse
equal in width to the COUNT DOWN input when the counter underflows. Similarly, the CARRY output produces a
pulse equal in width to the COUNT UP input when an overflow condition exists. The counters can then be easily
cascaded by feeding the BORROW and CARRY outputs to the COUNT DOWN and COUNT UP inputs, respectively,
of the succeeding counter.
NOTE
Voltage values are with respect to network ground terminal.

11.20 DEC 7485 IC
The DEC 7485 IC performs magnitude comparison of straight binary and straight BCD codes. Three fully decoded
decisions about two 4-bit words (A and B) are made and are externally available at three outputs. The delay time for
a 4-bit comparison is 12 ns. Figure 11-36 shows the truth table, pin locator, and logic diagram.

11-109

OUTPUT

STROBEo-______~~

'YO

DATA
1C

SELECT
B

SELECT
A

DATA

STROBEo-______~~___~

OUTPUTS
______

r -_______

B B A A

4
DATA ST~gBE~~~~CJ ,'-'_Y_3____--... r-'Y'-',__--',-'-YO
CJ1

GND

OUTPUTS

Pin assignments for these circuits are the same for all packages.

BE-0605

Figure 11-34 DEC 74155 IC Illustration (sheet 1)

11-110

SN74155
2YO 2Y1

SN74155
2Y2 2Y3

rr~...I.I...-I.L.

--.-

1YO 1Y1

1Y2 lY3

2YO 2Y1

2Y2 2Y3

1YO 1Y1

1Y2 1Y3

..------.-...--w..........w.=iI IIr---""---""'---------'

I
I
I
I

I I
I I

I I
I I
2G
2G

ENABLE/DATA

~
ADDRESS SELECT

DUAL 2-L1NE-TO-4-L1NE DECODER CONNECTION

ENABLE/DATA

1G
G
STROBE
OR
DATA INPUT

~
ADDRESS SELECT

3-L1NE-TO-8-L1NE DECODER CONNECTION

8E-0606

Figure 11-34 DEC 74155 IC Illustration (sheet 2)

BORROW
OUTPUT

f
j'

...,

CARRY
OUTPUT

OUTPUT QA

OUTPUT QB

DATA
INPUT A

r-L-J
PRESET
QA

DOWN
COUNT
~

UP
COUNT

-Q A

"
l-

CLEAR

ll)

VI(

DATA
INPUT B

PRESET
QB

,.. T
OB

-9,

CLEAR

ll)
DATA
INPUT C

._rL./

A
PRESET
OUTPUT QC

QC
,.. T

QC ICLEAR

DATA
INPUT D

r-L-J
CLEAR

'--

t-fJ-

PRESET
QD

LOAD 0---0

6-?

-v

OUTPUT QD

,., T

0i:> ICLEAR

Y ?

8E-0227

Figure 11-35 74193 Ie Illustration (sheet 1)

11-112

CLEAR

LOAD
A

-.J

I
L--

r__
-

____

.-J
-.J..-----------.1L--

DATA

~--------~I

COUNT
UP
COUNT
DOWN
QA

=l
=,

QB
OUTPUTS

CARRY
BORROW

10 1
~

SEQUENCE
, LLUSTRATED

CLEAR

r--COUNT UP

----J

I
15

r - - COUNT DOWN

131

---I

NOTE:
A. Clear overrides load data, and count inputs.
B. When counting up, count-down input must be high; when counting down, count-up input must be high.
8E-0226

Figure 11-35 74193 Ie Illustration (sheet 2)

11-113

L-..-.-o"

D0-

~D-~

A2
82

D-

A<8

.:....
....

~
}-

,--1
TOP VIEW

I
J

}"\
~

A-8

'L
J

A1
81

DATA INPUTS

.j:>

A>8

D-

-, )-

D~fA ,A<8 A:8 A>B"A>B A:B A<B, GND
I NPUT
CASCADING
OUTPUTS
INPUTS

t--1

Pin assignments for these circuits are the same for all packages.

}tSD--

o-rFr

A-8

"-------t

A< 8

A >B

8E-0604

Figure 11-36 DEC 7485 IC Illustration

D-

The 7485 IC is used to compare the desired 4-bit sector address with a 4-bit sector address read from the disk
cartridge in the R K8-E. This application asserts the A-B output when the two 4-bit addresses are equal.
11.21

DEC 74161 IC

The DEC 74161 IC (Figure 11-37) is a presetable high-speed binary counter. Synchronous operation is provided by
having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so
instructed by the count enable inputs and internal gating. This mode of operation eliminates output counting spikes
normally associated with ripple clock counters. A buffered clock input triggers the four master-slave flip-flops on the
rising (positive-going) edge of the clock input. To preset of load the counter register, the clock input and the enable
must be asserted. The removal of enable allows the counter to be incremented by the clock input.
In the RK8-E, these ICs are cascaded to provide a 12-bit Current Address Register that is preset to an address in
memory and incremented during the single cycle data break to select sequential memory locations.

11-115

(9)

.-:L

L OAO

14
QA

CL EAR

CLOCK

(3)

oATA

13
QS

CLOCK
'----"'

~
~

(41

oATA

INPUTS

°c

'1'"
CLOCK

(51

oATA
(21

----:r-

CL OCK

(111

Pin (16)" VCC. Pin (8)" GNO
(71

CLOCK

--J...-.I

)

'----"'

..16)

oATA

ENAS LE

(15
RIPPLE

CARR Y

(TOP VIEW) t

CLEAR CLOCK ~ ENABLE GND
DATA INPUTS
positive logiC: See discription

8E-0607

Figure 11-37 DEC 74161 IC Illustration (sheet 1)

11-116

OUTPUTS

U
I

CLEAR

LOAD

,r----------------------

r----------------------

B _ _ _ _--'-_ _~, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

DATA INPUTS

1----------------------

C~
D

L _____________________ _

Ir----"----"T""j
-_
-_
-_
-_
-_
-_
-_
-_
-_
-L____________
_

CLOCK
CLOCK

II ~~--------~

ENABLE P

I
----,
____
----,..J'_ _
----,

-'-_~_....J

QB _ _ _ _

OUTPUTS

I ~~---------~----~

ENABLE T

1
II

'!--_"!-_....I

QC _ _ _ _ -"---'

----.,

QD _ _ _ _ -,'_-.....I

CARRY
14

1'2

1 '3

14
..- - - - COUNT

CLEAR PRESET

I
I
I
1

"I"

INHIBIT

The following sequence is illustrated
1. Clear outputs to zero
2. Preset to binary 12
3. Count to 13,14,15,0,1, and 2
4. Inhibit

SE-0603

Figure 11-37 DEC 74161 IC Illustration (sheet 2)

11-117

PART 9
DISPLAYS

CHAPTER 12
VT8-E HIGH SPEED VIDEO DISPLAY
TERMINAL AND CONTROL

SECTION 1 INTRODUCTION

The VTS-E, a video display option for the PDP-S/E, PDP-S/F, and PDP-S/M, consists of a video terminal and three
quad modules that plug into the OMNIBUS. The quad modules control the terminal operation and can interface the
VTS-E to either an LA30A-P DECwriter or an LS01-E Centronics Line Printer. Up to four VTS-E display options
can be used simultaneously with the same computer.
The display terminal comprises a CRT with its associated power supply, deflection circuits, video circuits, and a
keyboard with its control logic. The monitor is contained in a desk-top enclosure (Figure 12-1).
Data is transferred from the terminal keyboard to the computer AC Register by program interrupts. Data to be
displayed by the monitor is transferred from memory by single cycle data breaks to the VTS-E OMNI BUS control
modules. The control modules convert the parallel data to serial video information that is displayed on the viewing
screen. The monitor can display both alphanumeric characters and graphic symbols, either alone or in combination.

Figure 12-1

VTS-E Display Monitor

12-1

Neither the LA30A-P nor the LS01-E Line Printers is discussed here. Details concerning these two printers should be
obtained from the respective maintenance manuals. Publications and documents relevant to the VT8-E are:
a.

PDP-8/E, PDP-8/F, and PDP-81M Small Computer Handbook - DEC, 1973

PDP-8/E, PDP-8/F, and PDP-81M Maintenance Manual, Volume 1

VT8-E Diagnostic; MAINDEC-08-DHVTB-A (Graphic), MAINDEC-08-DHVTA-A (Alphanumeric)

DEC Engineering Drawings, E-CS-M8335-0-1, E-CS-M8336-0-1, and E-CS-M8337-0-1 (interface modules)

DEC Engineering Drawing, D-CS-5409917-0-1 (DEC keyboard #2)

DEC Engineering Drawings, D-CS-301 0326-1-0 (Motorola Raster Display)

12.1

SYSTEM OPERATING SPECIFICATIONS
Operating Temperature Range

12.1.1

Operating Humidity Range
(without condensation)

10% to 90% (Relative)

Power Requirements
(display monitor)

100-130 Vac, 50 or 60 Hz
±5% single phase at 2A
200-260 Vac, 50 or 60 Hz
±5% single phase at 1A

Power Consumption
(display monitor)

55W at 115V
65W at 230V

CRT Operating Specifications (Motorola Raster Display)
Screen Size

10-1/8 in. X 7-518 in ..

Phosphor

P4 (white)

Deflection Type

Magnetic

Deflection Method

Raster Scan

Input Impedance
(at VIDEO IN input)

75il ± 5%

Video Input Signal

0.9 to 2.2V with separate horizontal and vertical SYNC.

Video Pulse Rise and Fall Time

40 ns (10% to 90% point), measured at cathode With 1.0V
Pop input and 30V Pop output.

Video Output Amplitude

30V Pop (minimum), measured at cathode with 1.0V Pop input.

Resolution

Screen Center - 600 lines (minimum)
Screen Corners - 400 lines (minimum) (using shrinking raster
method)

12-2

Horizontal Sweep Frequency

15.6 kHz

Vertical Sweep Frequency

50 or 60 Hz (selectable)

Horizontal Retrace

11 /lS (maximum)

Vertical Retrace

21 horizontal lines @ 15.6 kHz

High Voltage

11 kV (minimum) @ 50 /lA beam current @ 24 Vdc power
supply adjustment

High Voltage Regulation

12 Mil (maximum), for a beam current change from 50 to
150 /lA @ 24 Vdc power supply adjustment.

CRT Refresh Rate

50 or 60 Hz

12.1.2 Visible Display Specifications
Screen Refresh Rate

60 or 50 frames/sec (determined
by local line frequency)

Refresh Method

Raster Scan

12.1.2.1 Alphanumeric Mode
Viewing Area

8-1/4 in. (horiz) X 6-1/4 in. (vert)
(32 characters/line)
8-1/4 in. X 4-1/4 in. (64 characters/line)

Character Lines

Character Size

0.185 in. width (32 h
/1')
c aracters Ine
O.220'·In. h'
elg t
0.090 in. width (64 h
/')
h
c aracters line
O. 150 'In. h'
elg t

Character Spacing
Horizontal

0.0740 in. (32 characters/line)
0.0370 in. (64 characters/line)

Vertical

0.0946 in. (32 characters/line)
0.0645 in. (64 characters/line)

Character Set

64-character ASCII set
(upper case)

Character Generation Method

5 X 7 dot matrix

12.1.2.2 Graphic Mode
Viewing Area

7 in. X 6-1/4 in. (if wired for 32
alphanumeric characters per line)
12-3

Viewing Area (Cont)

7 in. X 4-1/2 in. (if wired for 64
alphanumeric characters per line)

Display Lines

200

Flicker-Free Points per Line

189

SECTION 2 INSTALLATION AND ACCEPTANCE TEST
The VT8-E Video Display and Control are installed on site by DEC Field Service personnel. The customer should
not attempt to unpack, inspect, install, checkout, or service the equipment.

12.2 UNPACKING
The VT8-E Display Monitor is packed in a specially designed carton to avoid damage during shipment.
NOTE
Carefully examine the VT8-E for damage as it is unpacked.
Any damage should be reported immediately.
Unpack the VTS-E Display Monitor as follows:
Procedure

Step

Remove the Display Monitor from the shipping container.
2

Remove the polyethylene cover.

Remove any tape, etc., from the display monitor cabinet.

Remove the display monitor from the shipping skid.

Place the display monitor in the desired location.

Verify all items listed on the Inventory List shipped with the VTS-E have been received.

12.2.1 Primary Power
The Display Monitor uses a single ac power cable (permanently connected) to connect the site power source to the
display monitor. The monitor operates at 110-130 Vac, 50-60 Hz, single phase, or 200-260 Vac, 50-60 Hz, single
phase.
Each wire in the ac power cable is color-coded as shown in Table 12-1. The d~splay monitor is normally supplied
with a 15A connector. The selected ac service outlet must be capable of at least 2A, 110 Vac, 50 or 60 Hz, or 1 A,
200 Vac, 50 or 60 Hz.
Table 12-1
AC Power Cable
Line

Wire Color

Terminal Strip
Nomenclature

Frame Ground
Neutral/Line 2
Line 1

Green
White
Black

Frame Ground
Neutral or Line 2
Line 1

12-4

12.2.2 VT8·E Installation
Install the VT8-E as follows:
Procedure

Step
Ensure PDP-8/E power is off.
2.

Ensure the Display Monitor Power Select switch, located on the side of the Display
Monitor, is set correctly for the power source (115 Vac or 230 Vac).

Use a meter to measure the voltages on the wall receptacle and ensure that the hot,
neutral, and ground connections are the same as those on the Display Monitor power
connector (Table 12-1).

On the M8336 and M8337, ensure the 5 jumpers are installed to select only 64 or 32
characters per line. All jumpers must be installed for the same mode.

On the M8335 module ensure the correct device code jumpers are installed. Table 12-2
contains a list of the split lugs which should be connected in each of the 6 groups (A-F)
to select one of the 64 possible device codes. Split lug locations (by groups) are shown on
D-CS-M8335-0-1. Engineering Drawing cover sheet.

On the M8337 and M8335 modules, ensure the jumpers are installed correctly to select
the priority assigned to this VT8-E (Table 12·3). Only priorities 9 (highest), 10, and 11
(lowest) may be assigned to the VTS-E. Refer to MS337-0-1 and M8335-0-1 cover sheet
for jumper locations.

Connect J1 of the 7009042 Cable Assembly to J1 on the MS336 module.

Connect J2 of the 7009042 Cable Assembly to J1 on the MS335 module.

If a line printer is used, connect the printer cable assembly to J2 on the MS335 module.

Install the VT8-E modules on the OMNIBUS as shown in Figure 12-2. Refer to Figure 2-3
in Volume 1 for recommended module installation priorities. The VTS-E is not a memory
option. The VTS-E modules must be installed in this order;
MS336
MS337
MS335

Install HS51 Top Connectors as follows (Figure 12-2):

a.
b.

c.
12

Front
Middle
Rear

Between MS336H and M8337H
Between M8337E and MS335E
Between MS337 F and M8335F

Route the 7009042 Cable Assembly to the Display Monitor and connect J3 Winchester
Connector to the mating connector on the rear of the·console.

12-5

If a line printer is used, route the printer cable to the line printer and connect it.

NOTE
If more than one VT8-E is installed in one system (up to four may

be installed in one system), the second control goes on the
OMNIBUS directly behind the first, and the third behind the second,
etc. The two controls are interconnected by installing an H851 Top
Connector between M8335J of the first control and M8336J of the
second control. The controls must be assigned different device codes
(Tables 12-2 and 12-3).

Turn on PDP-8/E power and run the acceptance test in Paragraph 12.2.4.

Table 12-2
Device Code Select Jumper Installation
Device
Code

Group A

Group B

Group C

Group D

Group E

Group F

00
01
02
03
04
05
06
07
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36

2-3
2-1
2-3
2-1
2-3
2-1
2-3
2-1
2-3
2-1
2-3
2-1
2-3
2-1
2-3
2-1
2-3
2-1
2-3
2-1
2-3
2-1
2-3
2-1
2-3
2-1
2-3
2-1
2-3
2-1
2-3

2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1

2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-1
2-1
2-1
2-1
2-1
2-1
2-1

2-3
2-3
2-1
2-1
2-3
2-3
2-1
2-1
2-3
2-3
2-1
2-1
2-3
2-3
2-1
2-1
2-3
2-3
2-1
2-1
2-3
2-3
2-1
2-1
2-3
2-3
2-1
2-1
2-3
2-3
2-1

2-3
2-3
2-3
2-3
2-1
2-1
2-1
2-1
2-3
2-3
2-3
2-3
2-1
2-1
2-1
2-1
2-3
2-3
2-3
2-3
2-1
2-1
2-1
2-1
2-3
2-3
2-3
2-3
2-1
2-1
2-1

2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1

12-6

Table 12·2 (Cont)
Device Code Select Jumper Installation
Device
Code

Group A

Group B

Group C

Group D

Group E

Group F

37
40
41
42
43
44
45
46
47
50
51
52
53
54
55
56

2·1
2-3
2-1
2-3
2·1
2-3
2-1
2-3
2-1
2-3
2-1
2-3
2-1
2-3
2-1
2-3

2·1
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3

2·1
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-1
2-1
2-1
2-1
2-1
2-1
2-1

2·1
2-3
2-3
2-1
2-1
2-3
2-3
2-1
2-1
2-3
2-3
2-1
2-1
2-3
2-3
2-1

2·1
2-3
2-3
2-3
2-3
2-1
2-1
2-1
2·1
2-3
2-3
2-3
2-3
2-1
2-1
2-1

2-1
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3

57
60
61
62
63
64
65
66
67
70
71
72
73
74
75
76

2-1
2-3
2-1
2-3

2-3
2-1
2-1
2-1

2-1
2-3
2-3
2-3

2-1
2-3
2-1
2-3
2-1
2-3
2-1
2-3
2-1
2-3
2-1
2-3
2-1

2-1
2-1
2-1
2-1
2-1
2-1
2·1
2-1
2-1

2-3
2-3
2-3
2-3
2-3
2-1
2-1
2-1
2-1

2-'
2-1
2-1
2-1

2-'
2-1
2-1

2-1
2-3
2-3
2-1
2-1
2-3
2-3
2-1
2-1
2-3
2-3
2-1
2-1
2-3
2-3
2-1
2-1

2-1
2-3
2-3
2-3
2-3
2-1
2-1
2-1
2-1
2-3
2-3
2-3
2-3
2-1
2-1
2-1
2-1

2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3

2-'

Table 12·3
Priority Jumper Installation
Priority

M8337 Install
Jumper

M8335 Install
Jumpers

9 (highest)
10
11 (lowest)

W1
W2

P9 and P10
P9' and P10
P9' and Pl0'

12-7

MB336

MB337

MB335

MB336

TO
......1I!!I-iiIJ.~ 0 CONSOLE
PER A TORS

'----y------'

VTB-E No.2

Sf-061?

VT-BE No.1

Figure 12-2 VTS-E Module Installation

12.2.3 Acceptance Test
The VTS-E is checked for proper operation by running the two diagnostic programs. Both MAl NDECs referenced in
the introductory remarks and the A-SP-VTS-E engineering specification give detailed instructions for their
performance in the instructions shipped with the paper tapes. If problems arise, refer to the maintenance
instructions, both in this manual and in Volume 1.

SECTION 3 OPERATION AND PROGRAMMING
This section provides a functional description of the VTS-E logic, operation and programming information, a list of
lOT instructions, and some VTS-E programming examples.
12.3 FUNCTIONAL DESCRIPTION
The functional groups of logic in the VTS-E are described in the following paragraphs (Figure 12-3). Their purpose,
location (on what module). and function are provided to familiarize the reader with VTS-E operation. A detailed
description of VTS-E logic and timing is given in Chapter 4. Refer to Chapter 9 of the Small Computer
Handbook - DEC, 1973 for information about data transfers via lOT instructions and data breaks. A detailed block
diagram of the VTS-E showing data flow and the interrelationship of the functional groups is in the VTS-E Video
Display Control Engineering Drawings.
12.3.1

VTS-E Printer/Keyboard Control Module (M8335)

The functional groups of logic on the MS335 module are discussed in the following paragraphs.
12.3.1.1 MD Bus Gating - Data from the MD lines is applied to the MS335 module by I/O PAUSE if lOT
instructions are executed by the program or by MD EN during single cycle data breaks. Single cycle data break is the
method used to transfer data between memory and the display control (Paragraph 12.3.4.1).

12-S

<>
CO, Cl
DATA O-DATA 11

MD3-MDll

VT8-E PRINTER IKEY80ARD CONTROL (M833 5)
(1) KEY80ARD AND PRINTER lOT DECODERS (2)
(2) MD 8US GATING
(3) DATA 8US GATING
(4) KEYBOARD BUFFER
(5) KEYBOARD FLAG
(6)1/0 TRANSFER CONTROL
(7)lNTERRUPT AND SKIP LOGIC
(8) STARTING ADDRESS REGISTER AND COUNTER
(9) EXTENDED ADDRESS REGISTER AND COUNTER
(10) PRINTER BUFFER
(11) PRINTER FLAG
(12) HIGHER PRIORITY DETECTION

INT REQ
SKIP
MAO- MA11
J:MAO- EMA2

P
D
P
8
1
E

'---

0
M
N
I
B
U
S

VT8-E LINE BUFFER (M8337)
(1) LINE BUFFER A AND B
(2) ASCII DECODING ROM
(3) VIDEO CONTROL
(4) GRAPHIC VIDEO BUFFER
(5) CHARACTER BLANK DETECT
(6)EOS,BBF, AND EBF DETECT
(7) BLINK, CURSOR, BRIGHT, OR NORMAL DETECT
(8) DATA BREAK CONTROL
(9) BREA K COUNTERS
flOlMA AND EMA BUS GATING
11 DATA BUS GATI NG
(12) MAINTENANCE ENABLE

KEY80ARD
48 KEY
(ASC II CODE)

DATA (ASC II CODE)
BUF MEM DATA
XADR CNTR
ADR CNTR
DATA

CODE)

PRINTER
LA30A-P
OR
LS01E

CONTROL
VIDEO

BRK RQST, MA,MS LOAD CONT MS,IR DISABLED,MD DIR. CPMA DIS,BRK IN PROG
(PROCESSOR CONTROL SIGNALS)
CONTROL
CONTROL

MD9-MD11

FREQUENCY DIVIDER BOARD (M8336)
(1) DISPLAY IOT DECODER
(2.) CLOCK AND FREQUENCY DIVIDER
(3) 64 OR 32. CHARACTER SELECTION
(4) ALPHANUMERIC TIMING CONTROL
(5)GRAPHIC TIMING CONTROL
(6)CHARACTER COUNTER
(7)LlNE COUNTER
f81 ROW COUNTER
9 VIDEO CONTROL
(10)HORIZONTAL SYNC PULSE SHAPER
(lllVERTICAL SYNC PULSE SHAPER
(12.)VIDEO AND SYNC COMBINING CIRCUITS
(13)VIDEO ENABLE CONTROL
(14) REAL TIME CLOCK FLAG

J
COMPOSITE VIDEO
(SYNC AND VIDEO)

GRAPHIC
OR
ALPHANUMERIC
DISPLAY

SE-0679

Figure 12-3 VT8-E Block Diagram

12.3.1.2 lOT Decoders - The M8335 module contains two lOT decoders, one for the printer and one for the
keyboard. The decoders are assigned different device codes so that the printer lOT decoder is selected when printer
lOTs are programmed, and the keyboard lOT decoder is selected when keyboard lOTs are programmed. The
keyboard and printer may be assigned any two of the device codes listed in Table 12-2. The device codes assigned to
the keyboard and printer must be diff~rent from each other and different from the display device code. The lOT
decoders decode MD9-MD11 from the MD lines and generate control signals to control keyboard and printer
operations; i.e., data transfers. The keyboard and printer instructions are listed in Paragraph 12.3.4.
12.3.1.3 Data Bus Gating - The Data Bus gates are enabled and OAT AO-DAT A 11 are applied to the M8335 logic
when the following occur:
a.

If the program executes the PNPC or PNLP instructions to load the Printer Buffer.

If the program executes a DPLA instruction to load the Starting Address Register or a DPGO instruction
to load the Extended Starting Address Register.

During a single cycle data break, DATA 0 - DATA 8, 9, or 10 monitored by the VT8-E during data
breaks to determine if the VT8-E has the highest priority for a data break.
12-9

12.3.1.4 Keyboard Buffer - The Keyboard Buffer receives a 7-bit ASCII code from the keyboard when one of the
keys on the keyboard is pressed. The keyboard also generates a KEYBOARD STROBE which enables the 7-bit
ASCII code to be transferred to the buffer and sets the KYBD flag. When the KYBD flag is set, an INT ROST is
made if interrupts are enabled, or a SKIP if the DKSF instruction is executed by the program. An INT ROOT or
SKIP notifies the program that data in the Keyboard Buffer is available to be read into the AC. The program must
transfer the data in the buffer to the AC and clear the KYBD flag so that a new 7-bit ASCII character can be
transferred from the keyboard to the buffer.
12.3.1.5 I/O Transfer Control - The I/O transfer control logic determines the direction of data flow on the Data
Bus and whether the AC is cleared or not. CO and C1 (the C lines) are asserted by lOT instructions which transfer
data to or from the AC.
12.3.1.6 Interrupt and Skip Logic - The interrupt and skip logic allows the program to enable the interrupts and
generate an INT ROST when the KYBD and PRINT DONE flags are set or to check the flags using a SKIP
instruction, i.e., the DKSF instruction.
12.3.1.7 Interrupt Logic - The keyboard and printer interrupt logic is enabled if bit 11 in the AC is set (1) when
the DKIN instruction is executed by the program. If the interrupts are enabled, an INT ROOT is made when the
KYBD flag is set or the PRINT DONE flag is set. The KYBD flag is set when a keyboard key is pressed, and the
PRINT DONE is set when the printer has finished printing a character.
12.3.1.8 Starting Address Register and Counter (SAR) - The Starting Address Register (SAR) is a 12-bit register
that is loaded from the AC with the memory address of the first word to be transferred by the single cycle data
break facility. The contents of SAR are transferred to the address counter after the DPGO instruction is executed by
the program and the counter is incremented at the end of each data break to select the next sequential memory
address. The contents of the counter are applied to the Memory Address lines (MAO-MA 11) to address a location in
memory.
12.3.1.9 Extended Starting Address Register - The Extended Starting Address Register (XSAR) is loaded from bits
6, 7, and S of the AC by the DPGO instruction. The contents of XSAR are transferred to the XADR COUNTER and
used to select a field in memory for data transfers. The XADR COUNTER is incremented when the ADR
COUNTER overflows to select the next memory field. At this time the ADR COUNTER starts reading memory
locations in the newly selected memory field.
12.3.1.10 Printer Buffer - The Printer Buffer is a 7-bit register that is loaded from the AC by the PNLP
instruction. The data from the AC contains a 7-bit ASCII code for a character to be printed. The seven data bits are
transferred along with a PRINT STROBE pulse, and when the Print operation is completed, the PRI NT DONE flag is
set. If interrupts are enabled, an INT RQST is made at this time, or if the flag is checked by the PNSK instruction,
the SKIP line is grounded. The program may perform a routine to transfer another character to the printer at this
time.
12.3.1.11 PRINT DONE Flag - The PRINT DONE flag is set each time the printer completes a print operation to
inform the program that the printer is ready to accept a new character.
12.3.1.12 Higher Priority Detection - The higher priority detection logic mon itors the Data Bus to determ ine if
the VTS-E has the highest priority for a data break. If there are any peripherals connected to the OMNIBUS that
have a higher priority that the VTS-E, one of the lines on the Data Bus will be low to prevent the VTS-E from doing
a data break. As an example, if the peripheral assigned the highest priority wants to do a data break, DATA 0 is
asserted (low) and the VTS-E cannot do a data break until DATA 0 goes high at the completion of the other
peripheral's data break. When the VTS-E is ready to do a data break, DATA 9 or DATA 10 will be asserted low to
prevent peripherals with a lower priority from doing a data break before the VTS-E. As previously discussed, the
VTS-E may be assigned one of the three lowest priorities.

12-10

12.3.2 VTS-E Line Buffer Module (M8337)
The functional groups of logic located on the VTS-E Line Buffer Module are discussed in the following paragraphs.
12.3.2.1 Line Buffers A and B - Line Buffers A and B provide temporary storage of 32 or 64 words from memory
in the Alphanumeric mode or 32 words from memory in the Graphic mode. In the Alphanumeric mode the word
from memory (Figure 12-7) selects the visible field, display mode, and character to be displayed. In the Graphic
mode, the word from memory (16 words per line) consists of 1s (display a dot) and Os (do not display a dot) to
produce a line on the face of the CRT. The display mode (Alphanumeric or Graphic) is selected by bit 10 (0 ~
ALPHA and 1 ~ GRAPHIC) from the AC when the DPGO instruction is executed by the program.
Each alphanumeric character is displayed on the face of the CRT in a 5 (width) X 7 (height) dot matrix. To display
one row of characters (32 or 64 characters), the Display Monitor makes 10 horizontal sweeps across the face of the
CRT. The first two scans are used to load the Line Buffers from memory via the Single Cycle Data Break. The third
scan addresses a blank ROM location and the remaining seven scans display the alphanumeric data. The first of the
seven scans displays the first line of each character in the row of characters to be displayed, the second scan the
second line, etc., until seven scans are completed to display a row of characters (32 or 64). When the tenth scan is
completed, the program must set up for a new break and initiate a new break cycle to reload the Line Buffers if
additional rows of characters (20 maximum) are to be displayed. During the display operation the 7-bit ASCII code
(Figure 12-7) is decoded by the ASCII decoding ROMS to generate the video signals to be displayed and the four
control bits are decoded to determine the display mode and visible field. A display may be stopped after any number
of characters have been displayed, if the display is less than 20 rows, to save computer time. This is done by setting
CB1 and CB2 to 1s when the last character is displayed.
In the Graphic mode, data is displayed on the face of the CRT in a 189 (width) X 200 (height) dot matrix. Each line
(189 dots) requires 16 12-bit words. The last three bits of the sixteenth word are not used. Each bit of the data word
represents a dot or space on the face of the CRT. A logical 1 causes a dot and a logical 0 leaves a space. As an
example, 16 words of data containing all 1s displays a row of dots on the face of the CRT. In the Graphic mode,
3200 (200 X 16) words must be defined because there is no way to generate End-of-Screen (EOS). If the full screen
is not used, the remainder of the memory locations used should contain all Os.
12.3.2.2 ASCII Decoding ROMs - The ASCII decoding ROMs decode the 7-bit ASCII code from the Line Buffers
and generate a video signal for each line of each character to be displayed. After the start of a horizontal scan, data is
shifted out of the Line Buffers to address (the buffer is in a recirculating mode, thus an end-around shift) a ROM
character generator location and generate video for one line of the character. ROM character generator locations are
addressed seven times (once for each horizontal scan). The video signals generated each time it is addressed are
changed by the assertion of Signals inside the ROM to change the video pattern and produce the desired character
after seven scans. The video out of ROM (VI DE01-VI DE05) is applied to the Alphanumeric Video Buffer where it
is shifted out to the Video Control logic as five serial video pulses. These pulses will cause dots or spaces to appear
on the face of the CRT and after seven scans, an alphanumeric character is formed.
12.3.2.3 Graphic Video Buffer - In the Graphic mode, the contents of the Line Buffer are transferred one word at
a time to the Graphic Video Buffer. From the Graphic Video Buffer the 12-bit word is converted to serial video
pulses and applied to the Video Control logic. Dots are displayed for data 1s and spaces for data Os.
12.3.2.4 Character Display Mode Detection Logic - The Character Display mode is determined by CB3 and CB4
(Figure 12-7) of the data word from memory. As shown in Figure 12-7, the character may be displayed in the
Normal,_ Blink, Bold, or Cursor modes. The Mode Detection logic decodes CB3 and CB4 to assert the control signals
necessary to select the four modes.
12.3.2.5 Visible Field Detection Logic - The visible field is determined by CB1 and CB2 (Figure 12-7) of the data
word. As shown in Figure 12-7, the character may be displayed in the mode selected by CB1 and CB2 (NaP), a

12-11

blank field may be ended and the display enabled (EBl), a blank field may be started (BBF) or an End of Screen
(EOS) may be selected to end the display. EOS is particularly helpful because it allows smaller displays to be
displayed without using the entire core buffer. This saves core buffer space and reduces processor loading.
12.3.2.6 Single Cycle Data Break Control Logic - The single cycle data break control logic is used to force the
processor into the Direct Memory Access (DMA) state and transfer data between core memory and the VT8-E Line
Buffers via the Memory Data lines. Memory is addressed by the outputs of address and extended address counters,
which are applied to the Memory Address lines at the beginning of the break cycle.
12.3.2.7 Processor Control Signals - When the processor is forced into the DMA state, the VT8-E must generate
control signals to control the processor. The control signals required to accompl ish this are shown in Figure 12-3 and
explained in Chapter 9 of the Small Computer Handbook - DEC, 1973.
12.3.2.8 Break Counters - The break counters are used to count the words in a data transfer. The counters
overflow after 32 words are transferred in the 32 character mode or after 64 words are transferred in the 64
character mode to stop data transfers and release the processor.
12.3.2.9 MA and EMA Bus Gates - The MA and EMA bus gates apply the contents of the address counter and
extended address counter to the OMNIBUS MA lines during a data transfer. This allows the selection of a memory
field and memory location to be used in a data transfer.
12.3.2.10 Data Bus Gates - The Data Bus gates are enabled when the DPM D i nstructi on is executed by the
program to transfer data to the Data Bus. This allows VTS-E registers and buffers to be read into the AC for display
or evaluation by the program. To read the Display Buffers and Register with lOT instructions the Maintenance logic
must be enabled.
12.3.2.11 Maintenance Enable - The maintenance logic is enabled by the DPSM instruction. This allows the
program to read the VT8-E registers and buffers using the maintenance instructions. It also allows data breaks to be
taken by the VT8-E at a rate determined by the program.
12.3.2.12 Frequency Divider Board (M8336) - The functional groups of logic on the M8336 module are discussed
in the following paragraphs.
12.3.2.13 Display lOT Decoder - The display lOT decoder decodes the display instructions and generates the
necessary control signals to set up for data breaks, maintenance operations, and data transfers using lOT
instructions. The decoder is enabled when I/O PAUSE is asserted and the device code assigned to the display for this
VT8-E is decoded and decodes bits MD9-MD11 of the lOT instruction. At this time, the C lines are asserted to
control the direction of the data transfer, INTE RNAl I/O is asserted to prevent the processor from performing
other lOTs, and the instruction is executed by the VT8-E.
12.3.3 VT8·E Clock and Frequency Divider (M8336)
The VT8-E clock and frequency divider generates the necessary CRT sync pulse's and control signals required to
display data on the CRT. The timing chain consists of a 21.84 MHz crystal controlled oscillator and a chain of
divide-by counters with selected outputs used to generate sync and control signals. Jumpers are provided to allow
the selection of 64- or 32-character display control signals. These jumpers allow control signals of different
frequencies to be selected for the display of 32 or 64 characters per row. The counters in the timing chain and their
function are discussed in detail in Paragraph 12.4.2.2.
12.3.3.1 Real Time. Clock Flag - The Real Time Clock flag is set (1) at the start of each vertical retrace. If
interrupts are enabled, an interrupt request is made, or if a Skip instruction is being executed by the program, the
SKIP bus is grounded and the program will skip an instruction.

12-12

12.3.3.2 Video and Sync Combining Circuits - The Video and Sync Combining circuits combine the horizontal
and vertical sync with the video pulses from the ROM Character Generator to produce a composite video signal.
12.3.4 lOT Instructions
The following instructions are used to program the VTS-E.
12.3.4.1 Display Instructions - The display instructions assume device code 05 is used. There are 64 possible
device codes which can be used (Table 12-2) for the display. The device code for the display, keyboard, and printer
must be different (e.g., device code 03 for the keyboard, 04 for the printer, and 05 for the display). If more than
one VT8-E is installed in the same system, three new device codes must be selected for the second VTS-E. They
must also be different from each other and different from the device codes assigned to other PDP-S/E options
installed in the system.
Load Starting Address Register (DPLA)

Octal Code:

6050

Operation:

Transfer the contents of the AC to the Starting Address Register (SAR) and clear the AC. The AC
must contain the address of the first memory location to be used in a data transfer. The contents of
the SAR are transferred to the address counters and then incremented at the end of each single cycle
data break. This allows the sequential selection of locations in memory for data transfers.

Load Extended Starting Address (DPGO)

Octal Code:

6051

Operation:

Transfer the contents of AC10 and AC11 to the mode select logic, and AC6-ACS to the Extended
Starting Address Register (XSAR). AC10 and AC11 are used to select alphanumeric or graphic mode
and enable or disable the interrupt system as follows:
AC10

AC11

o
o

o
1

Alphanumeric Mode, Interrupt Disabled
Alphanumeric Mode, I nterrupt Enabled
Graphic Mode, Interrupt Disabled
Graphic Mode, Interrupt Enabled

AC6-AC8 must contain the memory field to be used in a data transfer. The XADR COUNTER is
incremented when the ADR COUNTER overflows at the end of each memory field to select the next
memory field. The ADR COUNTER selects the first location (0000) in the new memory field. Data
transfers may start immediately after this instruction is executed.
STOP the Display (DPSM)

Octal Code:

6052

Operation:

Stop the display and inhibit video and VT8-E initiated data breaks. This instruction also transfers
AC11 and AC6-ACS from the AC to the maintenance logic and the Extended Starting Address
Register. If AC11 is 1, the Extended Address Register is loaded with the contents of AC6-ACS. If
AC11 is 0, the contents of the Starting Address Register are transferred to the address counters and
the VT8-E is set up for a maintenance break. The AC must contain the memory field in AC6-ACS
and AC11 must be 1 or 0 to determine which operations are to be done before this instruction is
executed.

12-13

Maintenance Instruction (DPMB)

Octal Code:

6053

Operation:

Transfer the contents of the memory location specified by the Address Counter to the Data Buffer.
The Address Counter is incremented by 1 to select the next location in memory.

Maintenance Instruction (OPMO)

Octal Code:

6054

Operation:

Jam-transfer the contents of the Data Buffer to the AC. Note that the DPMB and DPMS may be used
to transfer data from memory to the Data Buffer and then to the AC where it is displayed. This could
aid in troubleshooting the VT8-E.

Maintenance Instruction (OPMS)

Octal Code:

6055

Operation:

Transfer the contents of the Extended Address Counter to AC6-AC8 and the state of the SENSE
switch into ACO (Figure 12-4). This allows the program to determine what memory field is selected
and determine the condition of the SENSE switch. Bit 0 is a logical 1 when the SENSE switch is on
and a logical 0 when the SENSE switch is off. This switch is located on the keyboard and the
programmer determines its use and meaning.

MSB

LSB
MSB

SENSE
SWITCH
I=ON
O=OFF

NOT
USED

LSB
CONTENTS
OF EXTENDED
ADDRESS REGISTER
(MEMORY FI ELD)

NOT-USED
8E- 0682

Figure 12-4 Extended Address and Sense Switch Data

Skip On Real Time Clock Flag (OPCL)

Octal Code:

6056

Operation:

Skip the next instruction if the Real Time Clock flag is set (1) and clear the flag. Real Time Clock flag
is set at the start of each vertical retrace.

Generate A BfHI Tone (OPBL)

Octal Code:

6057

Operation:

Generate a half-second audible tone for use as a bell. This tone can be heard by the operator and can
be used to alert the operator that he must respond; i.e., supply data to the program via the keyboard.

12.3.4.2 Keyboard Instructions - The keyboard instructions assume a device code of 03 has been selected for the
keyboard.
12-14

Clear Keyboard Flag (DKCF)

Octal Code:

6030

Operation:

Clear the Keyboard flag. The Keyboard flag is set when the Keyboard transmitter is ready to transfer
data, usually after one of the keyboard keys has been pressed.

Skip on Keyboard Flag (DKSF)

Octal Code:

6031

Operation:

Skip the next sequential instruction if Keyboard flag is set. Keyboard flag sets when one of the
keyboard keys has been pressed to supply data to the program.

Clear Keyboard Flag and AC (OKCC)

Octal Code:

6032

Operation:

Clear the Keyboard flag and the AC.

Logically OR Keyboard Buffer and the AC (DKOB)

Octal Code:

6034

Operation:

Logically OR the contents of the Keyboard Buffer with AC5-AC11, deposit the result in
AC5-AC11, and transfer a 1 to AC4. ACO-AC03 remain unchanged. When DKOB is combined with
the CLA instruction, the contents of the Keyboard Buffer are transferred to AC5-AC11.

Enable Keyboard Printer Interrupt (DKIN)

Octal Code:

6035

Operation:

Enable Keyboard Printer interrupt if AC11 = 1 or disable if AC11 = O. AC11 must be set to 1 or 0
before this instruction is executed by the program.

Read Keyboard Buffer (DKRB)

Octal Code:

6036

Operation:

Jam-transfer the contents of the Keyboard Buffer to AC5-AC11 (Figure 12-5). set AC4 to 1, clear
ACO-AC3, and clear the Keyboard flag. AC5-AC6 contains a 7-bit ASCII code which represents the
key pressed on the keyboard.

[

MOST SIGNIFICANT ASC II BIT

Figure 12-5 Keyboard Data Format

12-15

BE-osea

12.3.4.3 Printer Instructions - The following instructions assume a device code of 04 is used for the printer.
Set Printer Flag (PNSF)

Octa I Code:

6040

Operation:

Set the Printer flag

Skip on Print Done Flag (PNSK)

Octa I Code:

6041

Operation:

Skip the next sequential instruction if the Print DONE flag is set.

Clear Printer Flag (PNCF)

Octal Code:

6042

Operation:

Clear the Printer flag.
NOTE
Octal Code 6043 is not used.

Load Printer Buffer (PNLP)

Octal Code:

6044

Operation:

Load the Printer Buffer from AC5-AC11 (Figure 12·6) and Print. AC5-AC11 contains a 7-bit ASCII
code which determines the character to be printed.

DATA BITS

121

7 BIT ASC II CODE

I I I

1 L

MOST SIGNIFICANT ASCII BIT
IGNORED BY PRINTER

BE-0681

Figure 12-6 Printer Data Format

Skip on Keyboard or Printer Interrupt (PNSI)

Octal Code:

6045

Operation:

Skip if the interrupt is enabled and either the Keyboard or Print DONE flag is set.

Load Printer Buffer (PNPC)

Octal Code:

6046

12-16

Operation:

Load Printer Buffer from AC5-AC11 (Figure 12-6), Clear Print DON E flag, and Print. The 7-bit
ASCII code determines the character to be printed.

12.3.5 Display Data Format
The two types of data that can be displayed on the VT8-E CRT are alphanumeric and graphic data.
12.3.5.1 Alphanumeric Data Format - Alphanumeric data displayed on the CRT is determined by the 12-bit word
(Figure 12-7) transferred from memory during a Single Cycle Data Break. This word determines the visible field,
character display mode, and the character to be displayed as shown in Figure 12-6. The VT8-E can display 20 lines
of alphanumeric information; 64 normal sized characters or 32 enlarged characters can be displayed on each line.
NOTE
EOS allows termination of the display and LF code 012 allows
termination of the current row. Both termination methods
save core memory and computer time for display with less
than 20 lines.

MD BIT

0
NOT
USED

2
C81

C82

4
CB3

C84

CHARACTER
DISPLAY
MODE
CONTROL
BITS

7 81T ASCII CODE
(SEE TABLE 3-2)
7

VISIBLE
FIELD
CONTROL
BITS

MSB

I
LSB

~----~II~______~

CBI

~ CB2 VISIBLE FIELD CONTROL BITS
o

o
o

CB3

NOP

IF IN VISIBLE FIELD, DISPLAY
CHARACTER IN BITS 5-1\
ACCORDING TO CBI, CB2.

EBF

END BLANK FIELD. ENABLE
VIDEO STARTING WITH THIS
CHARACTER.

BBF

BEGIN BLANK FIELD. DISABLE
VIDEO FOR THIS CHARACTER
AND THOSE FOLLOWING.
BLANK FIELD CAN BE TERMINATED BY EBF CONTROL
CODE.

EOS

~ CB4 CHARACTER DISPLAY MODE CONTROL BITS
o

END OF SCREEN. THE PREVIOUS CHARACTER IS THE
LAST TO APPEAR ON THE
SCREEN. VIDEO AND DATA
BREAKS ARE INHIBITED UNTIL
THE NEXT VERTICAL RETRACE.
THIS ALLOWS ABREVIATED
DISPLAY BUFFERS WHEN IT IS
NOT DESIRED TO USE THE
ENTIRE SCREEN. THIS SAVES
CORE BUFFER SPACE AND REDUCES PROCESSOR LOADING.

NORMAL

DISPLAY THE CHARACTER IN BITS
5-1 AT NORMAL INTENSITY IF IN
VISIBLE ZONE.

BLINK

BLINK THIS CHARACTER AT A
1.9 Hz RATE (1.6Hz FOR 50Hz
SYSTEMS) IF IN VISIBLE ZONE.

BOLD

DISPLAY THIS CHARACTER AT INCREASED INTENSITY IF IN VISIBLE
ZONE.

CURSOR

DISPLAY THIS CHARACTER AS A
CURSOR IF IN A VISIBLE ZONE.
THE CHARACTER AND ITS DOT
MATRIX COMPLEMENT ARE DISPLAYED ALTERNATLY AT A 3.7Hz
RATE (3.1 Hz FOR 50Hz SYSTEMS).

BE -0683

Figure 12-7 Alphanumeric Display Data Format

12-17

12.3.5.2 Graphic Data Format - The VT8-E is capable of displaying graphic information on a 189 (width) X 200
(height) dot matrix. Each dot position corresponds to a bit of a data word in the core buffer. The first word of the
buffer defines the first 12 dots on the first row. Bit 0 is the first to be displayed and bit 11 the last. If a bit is set to
1, a dot is displayed and if it is set to 0, no dot is displayed_ Sixteen 12-bit words are required to display one line of
graphic data. The last 3 bits of the sixteenth word are not used. As an example, 16 words of all 1s (7777) from
memqry would cause a line of 189 dots to be displayed on the face of the CRT. In the Graphic mode there is no way
to terminate the buffer short of 3200 words (200 lines), thus the entire buffer must be defined even if a major
portion is blank.
12.3.6 Display Monitor and Keyboard Switches and Controls
12.3.6.1 Display Monitor Switches and Controls - Table 12-4 lists the switches and controls found on the display
monitor enclosure.

Table 12-4
Switches and Controls
Control/Switch

Location

Function

CONTRAST Control

Right-hand side

Used to adjust the picture for contrast.

BRIGHTNESS Control

Right-hand side

Used to adjust the CRT brightness
(i ntens ity).

VERTICAL Control

Right-hand side

Used to synchronize the raster in the
vertical direction.

HORIZONTAL Control

Right-hand side

Used to synchronize the raster in the
horizontal direction.

ON/OFF Switch

Keyboard upperright corner

1\\\ Applies primary power when in the

I \\ ON position.
\

115V/230V

Right-hand side
of CRT frame

Selects 115V or 230V as primary
power for the display.

AC Circuit Breaker
pushbutton

Rear panel

Res ets circuit breaker after
momentary fault (do not hold in).

SENSE switch

Keyboard lowerright corner

Use determined by the programmer
ON = logical 1
OFF = logical 0

12.3.6.2 Keyboard Controls - The basic function of the keyboard is to provide a convenient, on-line method of
transmitting ASCII-coded characters to the CPU for processing and, perhaps, display on the VT8-E CRT screen. The
keyboard transmits an ASCII code directly to the computer each time a key is pressed, and the computer, in turn,
may transmit the character code to the VT8-E control logic. The control logic determines if the received data is to
be displayed or used to control the displayed text format.

12-18

The keyboard can transmit either full ASCII or a 97-character subset. The selected code is determined by an internal
selector switch. With the switch set to position 1, the keyboard transmits the full ASCII character set listed in Table
12-5. With the internal switch set to position 2, the keyboard transmits the 97-character ASCII subset listed in Table
12-6.
The VTS-E Display Monitor does not display lower case alphabetical characters. However, it can receive both upper
and lower case characters, which are interpreted and displayed as upper case characters (Table 12-7).

Table 12-5
VTS-E Transmit Codes - Full ASCII Operation
7
Bit No.6
5
432 1

o
1

000 0

space

000

1
1

o
000

C+(8S)

C-+

z
k

ALT

o 0

\
CR

HOME

ERASE
LINE

ERASE
SCREEN

L,_______,,~------~;

CTRL
Shifted

12-19

Table 12-6
VTa~E Transmit Codes - Half ASCII Operation

(switch in position 2)

7
Bit No_ 6

0
0

0
1

0
0

1 (0)

4 3 2 1

0 0 0 0

space

0 0 0
0 0

0 0

0
0

0 0 0

C+(8S)

0 0

1 0 1

C-+

C,J.

0 0
0

L
CR

HOME

ERASE
LINE

ERASE
SCREEN

Shifted

12-20

Y
J

ALT

DEL
(rub out)

Table 12-7
VTS-E Receiving Codes

7
Bit No. 6
5
4 3 2 1

1
1

0 0 0 0

space

0 0 0 1

0 0 1 0

0 0 1 1

o 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

(

1 0 0 1

)

1 0 1 0

CR/LF

1 0 1 1

[

1 1 0 0

1 1 0 1

]

1 1 1 0

r'\

1 1 1 1

12-21

>
/

12.3.7 Programming Examples
The following VT8-E programming examples are programs that may be used to display alphanumeric or graphic data
on the CRT.

12.3.7.1 Graphic Display Program Example - This program displays data from the Switch Register in a 189 X 200
dot matrix. A dot is displayed for those bits on the Switch Register that are set to ls and a space is displayed for
those bits in the Switch Register that are set to O.

Memory
Location

Instruction

0200
0201
0202
0203
0204
0205
0206
0207
0210
0211
0212
0213
0214
0215

6007
1216
6050
1221
6051
1217
3010
1222
3220
7604
3410
2220
5211
5205

VTGRPH, CAF
TAD
DPLA
TAD
DPGO
VT,
TAD
DCA
TAD
DCA
LAS
DCA I
ISZ
JMP
JMP

0216
0217
0220
0221
0222

0400
0377
0000
0002
1600

BUF,
BUFM1,
COUNT,
K2,
M6200,

Mnemonic

Operation

BUF
K2
BUFMl
10
M6200
COUNT
10
COUNT
.-3
VT

/CLEAR AND INITIALIZE.
/LOAD THE STARTING ADDRESS
/OF THE DISPLAY BUFFER INTO THE VT8-E.
/CODE FOR GRAPHIC
/DISPLAY IN GRAPHIC MODE.
/SET AUTO INDEX FOR STORING
/THE DATA IN THE SR.
/LENGTH OF DISPLAY BUFFER
/SET COUNTER FOR FILLING BUFFER.
/READ DATA PATTERN FROM THE SR.
/STORE IN BUFFER
/BUFFER FILLED.
/NO, CONTINUE FILLING IT.
/RELOAD BUFFER AGAIN.
/STARTING ADDRESS OF BUFFER.
/STARTING ADDRESS OF BUFFER -1.
/COUNTER FOR FILLING BUFFER.
/GRAPHIC ENABLE WORD.
/COUNT FOR FILLING BUFFER.

400
400-1
0
2
-6200

12.3.7.2 Alphanumeric Display Program Example - This program echos the character typed on the console
keyboard on the VT8-E display. The Switch Register is ORed with the character to display the character in the
Normal, Blink, Bright, or Cursor mode. The display mode is selected from the Switch Register (Figure 12-7) as
follows:

0000
0200
0400
0600

Normal
Blink
Bright
Cursor

12-22

Memory
Location

Instruction

0200
0201
0202

6007
1233
3010

0203
0204
0205
0206
0207
0210

1233
3011
1235
3410
1240
3234

TAD
DCA
TAD
DCA I
TAD
DCA

BUFMl
11
EOS
10
M2400
COUNT

0211
0212
0213
0214
0215
0216
0217
0220
0221
0222
0223

1232
6050
6051
6031
5214
6036
0236
7421
1235
3410
7604

TAD
DPLA
DPGO
KSF
JMP
KRB
AND
MOL
TAD
DCA I
LAS

BUF

0224
0225
0226
0227
0230
0231

0237
7501
3411
2234
5214
5200

AND
MOA
DCA I
ISZ
JMP
JMP

K600

0232
0233
0234
0235

0400
0377
0000
3000

BUF,
BUFM1,
COUNT,
EOS,

400
400-1
0
3000

/STARTING ADDRESS OF BUFFER.
/STARTING ADDRESS OF BUFFER -1.
/FULL SCREEN COUNTER.
/END-OF-SCREEN CHARACTER.

0236
0237
0240

0177
0600
5400

Kl77,
K600,
M2400,

177
600
-2400

/7 BIT MASK.
/CONTROL BIT MASK.
/LENGTH OF BUFFER.

Mnemonic
VTALPH, CAF
TAD
DCA

INPUT,

Operation

BUFMl
10

.-1
Kl77
EOS
10

11
COUNT
INPUT
VTALPH

/CLEAR AND INITIALIZE.
/ADDRESS OF BUFFER -1.
/SET AUTO INDEX FOR POSITIONING
/THE END OF SCREEN CHARACTER.
/ADDRESS OF BUFFER -1.
/SET AUTO INDEX FOR STORING CHARACTERS.
/GET THE END·OF-SCREEN CHARACTER (3000).
/PUT END OF SCREEN IN DISPLAY BUFFER AREA.
/SET COUNTER SO PROGRAM IS RESTARTED
/AFTER A FULL SCREEN IS DISPLAYED.
/(64 CHARACTER MODE)
/LOAD THE STARTING ADDRESS
/OF THE DISPLAY BUFFER INTO THE VTS-E.
/GO DISPLAY.
/CHARACTER YET
/NO, WAIT.
tREAD THE CHARACTER ..
/KEEP ONLY 7 BITS.
/SAVE IN THE MO REGISTER.
/MOVE THE END-OF-SCREEN
/CHARACTER UP ONE IN THE BUFFER.
/READ DISPLAY MODE CONTROL BITS
/FROM THE SR.
/SAVE ONLY THE CONTROL BITS.
/"OR" THE CHARACTER WITH THEM.
/STORE CHARACTER WITH CONTROL BITS.
/FULL SCREEN (64 CHAR MODE)?
/NO, GET ANOTHER CHARACTER.
/YES, RESTART THE PROGRAM.

SECTION 4 DETAILED LOGIC DESCRIPTION
12.4 INTRODUCTION

A simple block diagram of the VT8-E Video Display and Control is shown in Figure 12-8. The interface supplies the
monitor with video and sync signals, and an audio ton~. The video is either alphanumeric character information or
graphic information, or a combination of the two that is made possible by switching the display mode at the screen
refresh rate.

12-23

INTERFACE MODULES
DATA BREAK XFER,
DISPLAYABLE DATA

PDPSI E,
8/F,8/M
OMNIBUS

DISPAY MONITOR

M8337

VIDEO,AUDIO,SYNC
---------M8336
96-128-CHARACTER ASCII
---------PROGRAMMED INTERRUPT
M8335
SET
XFERS

128-CHARACTER ASCll
SET

CRT DISPLAY CKTS

--...-------DEC STANDARD
KEYBOARD

LA30 (A)-P
OR
LS01- ED PRINTER
8E-0616

Figure 12-8 VT8-E Functional Block Diagram

The keyboard transfers data directly to the computer's AC Register by program interrupts or flags. Each character
code transmitted can either be displayed or used to control the displayed text format. Data transmitted to the
system printer is also transferred by program interrupts or flags. When the Interrupt System is disabled, flags are
checked by the SKIP instructions.
The logic description is divided into two parts: one part concentrates on the interface logic for both the
keyboard/printer and the display, while the second part concentrates on the keyboard and CRT circuits.

12.4.1

Keyboard/Printer Logic

A block diagram of the VT8-E Keyboard/Printer logic is shown in Figure 12-9. Pin assignments for OMNI BUS signals
and connector signals can be found on Engineering Drawing E-CS-M8335-0-1.

OMNIBUS
DATA 4-11 L

KYBD(O) L

-1---------------------.
lOT

CONTROL
SIGNALS

L -_ _-I---I-__ KEYBOARD
STROBE L
L-_ _ _--jl-...;.._ BIT 1-7 L

SKIP L4-~-----------4_---------
INT RQST L4-~-----------_+_-------rOT,
CONTROL
.SIGNALS

INTERNAL 110 L 4 - - + - - - - ,
CO L,Cl L4-~---.

DATA 0 ----r------,,....J
1/0 PAUSE L

lOT
INSTRUCTIONS

MD 3-11 L

~-----I--+ INITIALIZE L

PRINT(O) L

.------1--- BIT 1- 7
..-_ _....;.__ PRINTER
STROBE L

INITIALIZE - - ' - - - - - - \

lOT,
CONTROL
SIGNALS
DATA 5-11 L-~-------------------~

L -_ _ _--I-__ DEMAND

8E-0618

Figure 12-9 Printer/Keyboard Block Diagram
12-24

The VTS-E Keyboard/Printer logic has two distinct functions: transfer of data from the CPU AC Register to the
Printer Buffer Register and transfer of data from the Keyboard Register to the AC Register. The transfer of data to
the Printer Buffer is carried out by the Printer Receive logic. When the printer is able to receive data, it asserts the
DEMAND signal. This signal sets the PRNT FLG flip-flop in the Printer Receive logic. The resulting PRNT (0) L
signal causes the INT/SKIP logic to assert the OMNIBUS INT ROST L signal, if the VTS-E has been logically
connected to the interrupt system. Alternatively, PRNT (0) L can be tested by a program skip instruction in the
INT/SKIP logic. In either case, the computer ultimately proceeds to a program subroutine that begins the data
transfer. When this subroutine is executed, the information is transferred from the AC Register to the DATA 5-11
lines and clocked into a 7-bit register in the Printer Receive logic. The register outputs are available at J1 as the BIT
1-7 signals. The logic then generates a PRINTER STROBE L signal that clocks the BIT 1-7 data into the Printer
Buffer Register, clears the PRNT FLG flip-flop, and causes the printer to negate the DEMAND signal.
The transfer of data from the Keyboard Buffer Register to the AC Register is carried out by the Keyboard Transmit
logic. When a keyboard key is pressed, information is applied, via the BIT 1-7 lines, to a 7-bit register in the
Keyboard Transmit logic. When the keyboard generates a KEYBOARD STROBE L signal, the information is clocked
into the 7-bit register and the KYBD FLG flip-flop is set. The KYBD (0) L signal can be tested in the INT/SKIP logic
with a SKIP instruction, or the interrupt system can be used to cause the program to enter an appropriate
subroutine. When the subroutine is executed, the information is gated from the register in the Keyboard Transmit
logic to lines DATA 5-11 (the logic asserts the DATA 4 L signal separately so that the input character is compatible
with the modified-ASCII Teletype code), then to the AC Register. The AC is loaded and, simultaneously, the KYBD
FLG flip-flop is cleared.
12.4.1.1 lOT Decoder Logic - The lOT Decoder logic is shown in Figure 12-10, which includes the Video Display
Decoding logic for reference. The VTS-E Keyboard/Printer uses 12 lOT instructions, 6 for the keyboard and 6 for
the printer. (One of the listed printer lOTs, Skip on Printer or Keyboard Interrupt, apply to both functions and one
of the keyboard lOTs, Interrupt Enable/Disable.) More than one keyboard/printer can be interfaced to the PDP-S/E
at the same time. The VTS-E (or other control module) associated with each keyboard/printer must be assigned a
unique device selection code for both the keyboard and the printer. Therefore, the MS335 module is fabricated with
jumpers and solder terminals that allow the user to assign anyone of 64 possible device selection codes to both the
keyboard and the printer (care should be taken when assigning device selection codes to preclude multiple
assignments of the same code). Figure 12-10 illustrates the octal codes and mnemonics that pertain when the VTS-E
is manufactured. The octal codes and mnemonics for the instructions are listed in Paragraph 12.3.2. A complete list
of device codes and the jumpers required to select each device code is shown in Table 12-2.
12.4.1.2 Printer Receive Logic - The Printer Receive logic is shown in Figure 12-11. Significant signals are related
by the timing diagram in Figure 12-12_ Refer to both figures when reading the logic description.
The printer routine is initiated by DEMAND changing to the true state, indicating that the printer is ready for
another character. This sets the PRNT flag flip-flop. This flip-flop can also be set by the PNSF instruction at TP3
time. If the VTS-E is logically connected to the interrupt system, as this discussion assumes, the PRNT FLG (1) L
signal causes the INT/SKIP logic to assert the OMNIBUS INT ROST L signal. The program proceeds to an interrupt
servicing routine to determine the identity of the requesting device. The PNSI instruction in the routine causes the
program to jump to a VTS-E routine that determines whether the printer or keyboard requested the interrupt (other
options are open to the programmer, this is but one example). Ultimately, the VTS-E printer routine executes the
PNPC instruction.
During TS2 of the PNPC instruction, information is gated from the AC Register to the DATA lines and remains on
the DATA lines through TS3. When PNPC L is decoded in the lOT Decoder logic, it enables NOR gates E25C and
E25D (Figure 12-11). NOR gate E25-D asserts the DATA EN signal; both DATA EN A L and DATA EN BLare
derived from this signal. The difference between the DATA EN A L and DATA EN B L signals is significant only
when considering the Display logic; for the present one must know only that one of these two signals gates lines
DATA 9 and DATA 10 to the 7-bit register. The remaining DATA lines are gated to the register flip-flops as shown.

12-25

r-------------------------------,
I
I
Pia M8336 MODULE

...---

0)-- DPL A L
I )-- DPG o L
2)-- DPS ML
E46
BCD-TO- 3 )-- DPM B L
DECIMAL
7442
4 )-- DPM o L
5 )-L L
6:>- DPC
SELECT DISPLAY L -<~ MSB
7 :>-DPBL L

. '\

I
I

+-L.J
1_·

nL_______________________
'
-...-.J

MD"

MD'O L

MD9 L

MD3 L

MD4 L

MD5 L

MD6 L

MD7 L

MD8 L

LL.;

604X

-r:

LL.;

,)-- DKSK L
E'8
BCD-TODECIMAL
7442

::;:

-(:>o-<

2 )-- DKCC L
3:>4:>- DKOB L
5:>- DKIN L
6:>- DKRB L

MSB

DISP
J(YBD

WPRNT
0:>- PNSF L
,:>- PNSK L

D~P
/ -KYBD

P--

....

PRNT

::;:

D~P

1 1»
I

-{:>o-<

KYBD

PRNT

PNCF L
E26
2
BCD-TODECIMAL 3 :>7442
4 )-- PNLP L
5P- PNSI L

6~ PNPC L

MSB

I-(

II o PAUSE L

ERNAL

I/O L

0)-- DKCF L

1~ *~
l~

INT

~ ~

__ J

PRNT

I
I
I

r-r
-

PRNT

....

D-

~~~BD

LL.;

--rr

U---,.-

603X
605X-

~------

DKCC L

tLr

DKRB L
MD
--ENABLE
L

E17

-E17

DKOB L

E35

CO L

E35

C, L

NOTE:
Logic is P/O M8335 module, unless noted otherwise.
8E·0619

Figure 12-10 lOT Decoder Logic

12-26

PNSF L

DATA 11 L
DA
+3V

1
1

DATA 10 L
QB

DB
PRNT FLG
0
(1) L

BIT 1

I
I

PRNT
FLG
C

QC
DC
74174
HEX
F/F
QD
DD

DATA B L

I
I
I
I
IBIT2-51
SAME
I

E19

DATA 9 L

DATA 7 L
QE

DE
DATA 6L

DF
QF
CLOCK

BIT 6

DATA 5 L

...
N

-...I

DATA EN

>--+--+-BIT 7

PNLP L
PN PC L

E3B
7474
F/F

E25D >--+---+-----:1,.---4

+3V

_.J

+3V
PRINTER
STROBE L

1-------1 D
STROBE
STROBE

~-+-------------------------------------------------------------1D

L----------------------------------------------------------4C

NOTE:
Logic is P/O B335 Module unless noted

E3B

E39

TP3 L

Figure 12-11 Printer Receive Logic

8E- 0620

At TP3 time of the instruction, NAN D gate E-17 is enabled and the information on the DATA Iines is clocked into
the 7-bit register. Simultaneously, flip-flop STROBE 1 sets and thePRNT FLG flip-flop is cleared. The register data
is applied, via the BIT 1-7 lines, to the Printer Buffer Register. At the beginning of TS2 of the instruction following
PNPC, flip-flop STROBE 2 sets and asserts PRI NTE R STROBE L. This signal loads the Printer Buffer Register and
negates the DEMAND signal. Both STROBE 1 and STROBE 2 are cleared by the next TP3. When the print cycle
ends approximately 30 ms later, the DEMAND signal is again asserted and a new transfer can be started.

r+--------t-------------....,CYCLE _ _ _ __
I PRINT
",30MS
DEMAND

PRNT FLG (1) L

INT RQST L

PNSI L

SK I P L

PNPC L

I:
I'I

I'I
I
I
I
I

I
TS2 L

TP3

n~------~n~--------~n~---I

I
DATA 11-5 L

BIT

1-7

INSTRUCTION'

xxxx

RCVR STROBE L

"--___---II

NOTE
Tl. T2 and T3 ore distinct time periods.
The amount of time between periods is
a function of program-routine execution time.
8£-0621

Figure 12-12 Printer Receive Logic Timing

12-28

12.4.1.3 Keyboard Transmit Logic - The Keyboard Transmit logic is shown in Figure 12·13. Significant signals are
related by the timing diagram in Figure 12-14. Refer to both figures when reading the logic description.

TP3

DKCC L
DKRB L

D
iNiTiALiZE
E37
KYBD
FLG

KEYBOARD ----<It---.....~OI
STROBE H

KYBD FLG (1) L

DKOB L
DKRB L
BiT 1 L

BiT 2 L

DB b(}I8oB
F/F

DATA 11 L

E32

BiT 3 L

BiT 4 L

CLOCK

BiT 5 L

DATA 10 L

DATA 9 L

DATABL

DATA 7 L

E31
74175
QUAD
F/F
BiT 6 L

BiT 7 L

DATA 6 L

Do CLOCKOD

DATA 5 L

+3V

NOTE:
LOQic is PIO M8335 moduie

DATA 4 L
BE- 0622

Figure 12-13 Keyboard Transmit Logic

12-29

BIT

1-7

KEYBOARD STROBE

KYBD

l~
H~~________________________~__________________________________

FlG(l)l~~________________________+-________________~

INT RQST

l~~________________________+-________________~

PNSI l

SKIP l

DKRB l

DATA 11-4 l

COl,Cll

TP3 ____________________

----~r--l~------------------~r--l~---------8E-0623

Figure 12-14 Keyboard Transmit Logic Timing

The user initiates the keyboard sequence by pressing a key on the keyboard. The character information is placed on
the BIT 1-7 lines. After a period of time that allows the BIT lines to settle, the keyboard generates the
KEYBOARD STROBE H signal. The trailing edge of this signal clocks the information into the 7-bit register and sets
the KYBD FLG flip-flop. If the VT8-E is logically connected to the interrupt system, as assumed, the KYBD FLG
(1) L signal causes the INT/SKIP logic to assert the OMNIBUS INT ROST L signal. The program proceeds to an
interrupt servicing routine to determine the identity of the requesting device. The PNSI instruction in the routine
causes the program to jump to a VT8-E routine that determines if the printer or keyboard requested the interrupt.
Ultimately, the VT8-E keyboard routine executes the DKRB instruction.
When the DKRB instruction is decoded, the lOT Decoder logic generates the DKRB L signal and activates the
OMNIBUS CO and C1 lines. The DKRB L signal enables NOR gates E17C and E17D; the output signal from E17D
gates the information from the register outputs to DATA lines 5-11, and also causes NAND gate E27 to assert the
DATA 4 L signal. The DATA lines are gated to the AC Register and the information is clocked into the register at
TP3 time. Also at TP3, the KYBD FLG flip-flop is cleared, readying the logic for a new data transfer.
12.4.1.4 INT/SKIP Logic - The INT/SKIP logic is shown in Figure 12-15. The PANT FLG (1) L signal and the
KYBD FLG (1) L signal can cause program skips when tested by instructions PNSK and DKSK, respectively. The
signals can also be tested by the PNSI instruction, provided the ENA flip-flop, E37, has been set, logically
connecting the VT8-E to the interrupt system. When E37 is set, the PNSI L signal enables NAND gate E29, which, in
turn, enables NAND gate E34, if either the PRNT FLG (1) L signal or the KYBD FLG (1) L signal is asserted.
Simultaneously, NAND gate E13 asserts the INT ROST L signal.

12-30

r---<~ INITIALIZE

B DATA IlL
TP3 - - - - \

E37
PRIOT5L
ENA
(PNSI) L
F/F
C
Ot-+---Q

SKIP L
INITIALIZE H-----\

KY IOT I L _ _~':-;;-;;;"I
(DKSF)

KYBD
FLG (1) L
PR lOT I L-'--~-"""
(PNSK)L
PR NT . -,---..,.-_____
FLG (I) L

INT
D - - - - - - - - - - RQST
L

NOTE'
Logic is P/O M8335 module.
SE -0624

Figure 12-15 Keyboard/Print Interrupt and Skip Logic

The ENA flip-flop is set by the OMNI BUS I NIT signal for the PDP-S family computers. To clear the flip-flop,
remove the VTS-E from the interrupt system, load AC11 with logic 0 and then program the DKI N instruction. The
logic 0 in AC11 keeps the DATA 11 L signal negated. Thus, the 0 input of E37 remains high. At TP3 time, NAND
gate E22B provides a clock pulse for E37, clearing the flip-flop. E37 can be set at any time with the same instruction
merely by loading AC11 with logic 1.
12.4.2 Display Logic
Information displayed by the VTS-E is transferred by data breaks from the PDP-8/E memory. As with all data break
devices, the start of the data transfer is under program control. However, the VTS-E is a 1-cycle data break device;
consequently, it needs only a starting memory address to carry out the complete data transfer. The starting address,
i.e., the memory address of the first data word to be transferred to the VTS-E, is placed in the AC Register by a
program TAD instruction. Program lOT instructions gate this address onto the OMNIBUS DATA lines and cause it
to be loaded into a starting address register in the VTS-E (Figure 12-16). At the same time, the VTS-E Data Break
logic is readied for triggering.
When the CRT sweep is in a specified position, a synchronizing signal is generated by the VTS-E Timing logic. This
signal enables the Data Break logic to request a data break and check priority. If no higher priority device has
requested a break at this time, the Data Break logic asserts a number of OMNI BUS control signals, enabling direct
communication between the interface and memory for one PDP-S/E timing cycle. At the same time, other Data
Break logic signals gate the starting address onto the OMNIBUS MA lines. During the data break timing cycle, the
data word in the addressed memory location is transferred on the MD lines and loaded into the interface Line Buffer
Register. At TP4 time of the timing cycle, the Data Break logic increments the address in the Address Counter. The
data word in this new address is transferred during the next data break timing cycle, which might occur immediately
after the first (priority is checked during TS4 of each data break cycle; a higher priority device can interrupt the
VTS·E data breaks).
After each transfer, the address in the Address Counter is incremented, and the data word in the new address is
loaded into the Line Buffer Register. This register holds' 32 or 64 data words, depending on the mode (graphic or
alphanumeric) or the desired number of alphanumeric characters per line. The Data Break logic counts the number
of data breaks; when the specified number of data words has been loaded into the Line Buffer Register, the Data
Break logic ceases to request breaks.

12-31

ROM CHAR
GEN LOGIC

lOT

MAl NTENANCE
lOT LOGIC

DECODER
LOGIC

I NT/SKIP
LOGIC

MD 0-11 L(DATA)
BREAK CONTROL SIGNALS

E
REGISTER LOGIC

EMA 0-2 L
MAO-l1 L

STARTING ADDRESS
REGISTER LOGIC

DATA 0-11 L
(STARTING ADDRESS)

I
I

LOAD/ INCREMENT

MAC 1 (1)
MACO (1)

I MY PRIORITY L

DATA BREAK
CONTROL LOGIC

INT SiTROBE
CONT BRK
MAC 1 (0)
DATA BREAK
TP1
COUNTING LOGIC

DPGO L

MAINT L

STARTING ADDRESS
MODE CONTROL LOGIC

MD1,2 L ,(EOS) MD 5-11 L (LN FEED)

LALPHA/GRAPH
I
I

LOGIC

LINE BUFFER
REG CONT LOGIC
(GRAPHIC)

LOAD~SHIFT

LINE BUFFER
REG CONT LOGIC
( ALPHANUMERIC)

DPLA L

I PRIORITY

1""!'"',,- 1

BUFFER CONT
LOGIC

HALT BRK

I
I

DATA BREAK
HALT LOGIC

LBRK SHIFT
I

DATA 0-11 L (PRIORITY)
BE

Figure 12-16 Display Logic Block Diagram

- 06 25

If the VT8-E logic has been programmed to display 32 alphanumeric characters per line; for example, each data
word in the Line Buffer Register contains: the 7-bit ASCII code representation of an alphanumeric character (bits
5-11); data that controls how the character is displayed (bits 3 and 4); and data that controls the visible field (bits 1
and 2). Because the VT8-E displays only a 64-character set, bits 6-11 of the Line Buffer Register contain sufficient
data to display all alphanumeric characters. Characters are formed on the CRT screen when the CRT video circuits
selectively intensify points within a 5 X 7 dot matrix. The letter F is illustrated in Figure 12-17. Each horizontal
scan line corresponds to one row of the letter. As the sweep scans along a line, video signals selectively intensify
points as illustrated (5 video signals in row 1 of the letter F). If 32 alphanumeric characters per line are to be
displayed, for example, row 1 of each character is swept out by the same scan line. The next scan line sweeps out
row 2 of all 32 characters, and so on until the 7th scan line sweeps out row 7 of the characters, completing the
character line.

2
3
4

5
6
7

• • • • •
•
•
• • • •
•
•
•
8E-0626

Figure 12-17 Video Presentation for the Letter F

The video signals are generated, indirectly, by a ROM Character Generator. After the start of a horizontal scan line, a
6-bit ASCII character is shifted from the Line Buffer Register (at this time, the register is in the recirculating mode;
hence, an end-around shift is performed). The character addresses a ROM Character Generator location. This
location contains the video information for one row of the character. For example, assume that the letter F is the
first character to be displayed in a particular character line. The 6-bit ASCII representation of the letter F addresses
a particular ROM Character Generator location. The information in this location causes row 1 of the letter to be
painted during this scan line. The next character to be displayed is shifted from the Line Buffer Register and
addresses its unique ROM Character Generator location; the information in the location causes row 1 of this
character to be displayed just after character F. Row 1 of all 32 characters is displayed during this scan line.
After the start of the next horizontal scan line, the 6-bit ASCII representation of the letter F is again shifted from
the Line Buffer Register. Meanwhile, certain ROM control signals have been asserted so that the addressed location
differs from that of the first scan line. This location contains information that causes Row 2 of the letter F to be
painted during this scan line. Row 2 of all other characters is displayed during this scan line in similar fashion.
Consequently, the Line Buffer Register is shifted 32 times during each scan line; after 7 end-around shifts of the
register, a character line has been displayed.
Each character line comprises ten scan lines, rather than the seven just described. The three additional lines occur at
the beginning of the character line. During the first two scan lines, the Line Buffer Register is loaded from the
OMN IBUS M D lines; during the third scan line, a blank ROM location is addressed. Figure 12-18 represents two
character lines as they would appear on the CRT screen. Character line spacing (43% of character height) is provided
by the three blank scan lines.
If the VT8-E has been programmed for a graphic display, one line of graphic data is displayed during each horizontal
scan line. A line of graphic data is represented by 16 12-bit data words; each bit of a data word represents a dot or a

12-33

space on the CRT screen. The Line Buffer Register is loaded with two lines of graphic data by 32 data breaks. As the
sweep scans along a line, video signals selectively intensify points to paint the graphic symbol. Although 16 12-bit
data words contain 192 bits, only 189 points can be painted by each scan.

10 S CAN
LINES PER
CHARAC TER
L INE

\
J
I
I

LINE BUF FER {
IS LOADED FOR
NEXT ROW OF
CHARACT ERS

BE 0627

Figure 12-1S Two Alphanumeric Characters Displayed on the CRT
12.4.2.1 VT8-E Timing - The VTS-E Timing logic generates signals that sync tile Display logic and the CRT sweep
circuits. Figure 12-19 illustrates the CRT vertical and horizontal sweep signals and the VTS-E sync signals.
For 60 Hz operation, the VTS-E timing generates a V SYNC L signal every 16.7 ms. This sync signal causes a vertjcal
retrace, which is carried out in approximately 20 scan lines. A VZONE flip-flop in the timing controls the
displayable area in the vertical direction. When the flip-flop is set, the VZONE (1) signal enables a vertical display of
200 scan lines (the horizontal sweep rate is set at 15.6 kHz; a total of 60 scan lines is made non-displayable to
remove distortion-prone areas on the CRT screen).
The timing generates an HSYNC signal every 64.1 p.s. A HZONE flip.flop in the timing controls the displayable area
in the horizontal direction. When the flip-flop is set, the HZONE (1) signal enables graphic or alphanumeric video to
be painted in the distortion-free area of the screen (exceptions to this statement are pointed out in the detailed logic
discussion).
12-34

""'1~f-------------16.7m5 ------------.l~1
V SYNC L (f=60Hz)

U
I
I

I
I

I
VERT SWP~,________________________------------------~I'-

:
V ZONE (1)

L . . ._ - ' - -_ _

200 SCAN LINES
4O_~""'.~-----AT HORIZ. SWP
RATE -------.l~ 20
OF 15.6KHz
NON- DISPLAYED
NON -DISPLAYED
SCAN LINES
SCAN LINES

""'1~------------64.1 1"5 -------------+l~1
H SYNC

-Il
rL
I
----------------------------~i
I
I
I

I
I

HORIZ SWP (f=15.6KHz) ~

H ZONE (1)

I
I

---1

L ___

90Rlal~·--- 34 611"5 (GRAPHIC)

l!-__-'-l_ _

~I 9 aRia

NON-DISPLAYED
CHARACTERS

I-

NON-DISPLAYED
CHARACTERS

41.02JLs
(ALPHANUMERIC)

•

BE-062e

Figure 12-19 Sweep and Sync Signals

The VT8-E timing is such that either 50 or 100 alphanumeric characters could be displayed between HSYNC signals.
The HZONE (1) signal reduces the number of characters to either 32 or 64, respectively (an equal number of
characters is removed on both sides of the screen). Note that the HZONE (1) signal is of shorter duration for the
graphic display. This is explained as follows. Clock pulses of the same basic frequency are used to shift the
Alphanumeric Video Buffer Register and the Graphic Video Buffer Register. Seven shift signals are needed to display
the rows of the 5 X 7 alphanumeric character matrix (five signals intensify the scan, two signals provide spacing
between each character). Thus, 7 X 32, or 224 shift pulses are needed for an entire character line. An entire graphic
line needs only 192 shift pulses. Consequently, it seems that the HZONE (1) signal should be reduced by an amount
that allows 192 shift pulses to be generated (if the display area is not shortened, an improper display will result).
This would mean reducing the graphic displayable area by an amount equal to 32 shift pulses. However, this is not a
multiple of seven, which it must be to enable correct alphanumeric display. The closest number that is a multiple of
7 is 35. Thus, the horizontal zone for graphics allows only 189 shift pulses to be produced, cutting off the last 3 data
bits in each scan line (note that 28 could not be used because then too many graphic shift pulses would be
produced). The pulses are derived from a 5.46 MHz clock (t = 183.15 ns). Therefore, 189 shift pulses require an
HZONE (1) signal of only 34.61 jJ.s.
12.4.2.2 VT8-E Timing Logic - The VT8-E Timing logic generates the CRT sync pulses and the interface control
signals. All timing and control signals are derived from' a crystal-controlled transistor oscillator that produces pulses
at a frequency of 21.84 MHz. These pulses are applied to a Clock Pulse Generator, shown in Figure 12-20. The
generator divides the basic frequency by 2 and 4, producing well-shaped clock pulses of 10.92 MHz and 5.46 MHz.
Two test points are available which allow the oscillator clock to be inhibited and external clocks injected to drive the
timing chain.

12-35

1-1-----./1) 32
+5V

0 - - - CNT

+5V

CRYSTAL
CLOCK
F=21. 84MHz

}------j C

IN IT + REM V SYNC

Ol-I----;C

TRUTH TABLE
(Each Flip -Flop)

C
J

0
NOTES:
1. Logic is P/O M8336 Module
2. Connect jumper"64"for 64 Alphanumeric CharacterlLine
Connect jumper"32"for 32 Alphanumeric CharacterlLine
3.DEC 7473 J-K F/F Truth Table

o
o

.8E -0629

tn = BIT TIME BEFORE CLOCK PULSE.
tn+1 = BIT TIME AFTER CLOCK PULSE.

Figure 12-20 Clock Pulse Generator

The clock pulses selected are applied to a chain of DEC 74161 4-Bit Counters that counts down the pulse frequency
to 3.75 Hz (for 60 Hz operation). Selected outputs of the timing chain are gated to produce sync pulses and control
signals.
A logic block representation of the DEC 74161 4-Bit Counter Integrated Circuit (I C) is shown in Figure 12-21. This
IC, E17, is the first one in the timing chain. Because it is a 4-bitcounter, E17 can produce one pulse at its CARRY
output for each 16 pulses at its COUNT UP input. However, because the IC can be preset to any count, it can
produce a CAR RY output for any number of input pulses less than 16. The preset inputs are labeled A through 0 in
Figure 12-21 (A is the LSB). They are wired so that E17 is preset with a count of 1001 2 whenever a signal is applied
to the LOAD input and a clock pulse occurs. The CAR RY signal is generated when the count is in the 11112 state
and ENP and ENT are true. A Load signal is generated by the OR gate and E17 is preset to 1001 2 . Seven more
pulses at the clock input produce another CARRY signal and, again, the counter is preset. Thus, the counter divides
by seven. The counter can also be preset by a REMOTE V SYNC IN L signal, enabling the timing to be controlled by
some external device. The output of each bit, designated OA through 00 (OA is the LSB), is available for gating to
generate the sync and control signals.

+3V
REMOTE
VSYNC H

064

A
CLOCK
032

CARRY 1 - - - - - - /

E17+7
74193

+3V

8E-0630

Figure 12-21

4-Bit Counter

12-36

Figure 12-22 shows the entire chain of 74161 ICs. Each IC in the figure is represented in shorthand form: i.e., the
wiring of the PRESET inputs is not shown, the LOAD input circuits are not shown, and the destination of each
output is now shown (only those output bits that are used are indicated on the ICs). The binary designations above
each IC block represent the way the preset inputs are wired. For example, E16 is wired thus: PRESET input D is
tied to +3V; PRESET input C is grounded; PRESET inputs B and A are tied to +3V. Therefore, E16 is preset with a
count of 1011 2 and divides by 5.

F"10.92MHz .(100112
l64CH
CLK

T32CH

*(1 010 2

E17+7
CARRYi-....

32CH

-------<Il

CLK

*(1110)2

ABC

E16+5
CARRYi--------------------,

A B

E12+2
CLK
CARRY

F= S.46MHz

*(0100)2
E31 + 12
CARRY

F=S.46MHz

CLK

GND

A B

50
Hz

60
Hz

~
*(0110)2

.(0110)2

.( 111 0)2

E18+10
CLK
CARRY

E19"10
CLK
CARRY

CLK

ABC 0

ABC

E8+2
CARRY

50Hz
60Hz

E42 "16
V SYNC- CLK

REMOTE VERT SYNC IN
+50Hz RESET H
SOHz RESET

*COUNTER IS PRESET TO THIS BINARY VALUE

IC OUTPUT FREQUENCY
IC

NOTE:
LOQic is PIO

M8336

FREQ. OUTPUT
60Hz LINE

50Hz LINE

780KHz(32)
E17 1560KHz(64)

MDdule

E16 156KHz
E18 15.6K Hz

SAME
AS
60Hz

E19 1.56KHz
E8 780Hz
E9 60Hz

50Hz

E42 3.7SHz

3.12SHz
8E-0631

Figure 12-22 VT8·E Timing Chain

Each IC has a NOR gate at its LOAD input, exactly as shown in Figure 12-21; this gate ORs the CAR RY output
with REMOTE V SYNC and INIT IE17, E12, E16), or with REMOTE V SYNC and 50 Hz RESET IE18, E19, E8,
E9). The bit output destinations are shown, in part, only for ICs E19, E8, and E9.
The table in Figure 12-22 indicates the trequency of the CARRY output pulses of each IC. The output frequency
from E17 differs for 32 character/line and 64 character/line operation. The bit output signals from E17 determine
the alphanumeric character rate, the rate at which characters are painted on the CRT screen. Thus, the rate is twice
as fast for 64 character/line operation. E12 divides by two; therefore, the input of E16 is the same for both
character rates.
12-37

When a 50 Hz line is used, the timing is modified in the last three ICs. For 60 Hz operation, E9 is preset with a count
of 0011 2 and its CAR RY output provides the LOAD input for E9. E8 and E9, together, divide the output of E 19 by
26, producing a CARRY output pulse from E9 at a frequency of 60 Hz. This output is gated elsewhere in the logic
to generate the V SYNC L signal that causes a CRT vertical retrace. For 50 Hz operation, the 50 Hz jumpers are
connected, and E9 is preset with a count of 00102. Furthermore, the LOAD input of E9 is controlled by REMOTE
V SYNC IN or 50 Hz RESET H. When E9 attains a count of 001 2 and both E19-D and E8-A are high, E9 is preset
and a V SYNC pulse is generated. E8 and E9, together, divide the output of E19 by 31.2, producing pulses having a
frequency of 50 Hz. The table shows the output of E9 as 50 Hz (the output is not actually from E9, as for 60 Hz
operation, but it is convenient to think of it as so). As for 60 Hz operation, the output is gated to generate the V
SYNC L signal.

Note that the REMOTE V SYNC IN or 50 Hz RESET line is activated when E9 is preset; thus,lCs E18, E19, E8,
and E9 are preset at the moment of vertical retrace. This active step is not necessary during 60 Hz operation because
all ICs automatically overflow to the preset state.

Figure 12-23 shows the logic that generates the horizontal and vertical .sync signals, while Figure 12-24 shows the
HZONE and VZONE flip-flops and those signals that control the two flip-flops. The timing diagram in Figure 12-25
shows the line timing for both alphanumeric and graphic display. Two hundred of the HZONE (1) signals are
generated for each VZONE signal, as shown in Figure 12-19.

+5V

E16 CARRY-ClK
Ef8-A
EI8-D

+5V

------0

E46B
74123
500ns

------a
------a

>-.....-H SYNC

EI8-B

CLEAR

EI8-C -,,---~

+3V
+5V

ClK
REMOTE V SYNC,_ _ _ _ _---\
+50Hz RESET
60Hz
E9 CARRY --.o:-~;"'---:l_."
50Hz

E46A
74123
>1?4,us

V
SYNC
l

+5V

Ot-........q >-.......- v SYNC

CLEAR

+3V
NOTElOQic is P/O M8336 module.
BE-0632

Figure 12-23 Horizontal and Vertical Sync Circuits

12-38

EI6-B
EI6-A

H ZONE (I )

E 18-B ------..."--_~
EI6 ENABLE T
ClK

>--------IC

EI
H ZONE

,.-----fK

E28
DEC
8266

EIB-C

HI FOR GRAPHIC /SElECT A
lO FOR ALPHANUMERIC /
SELECT B
E9-B

E9-C
V ZONE(l)

E8-A
EI9-B
H ZONE

E 19 - C ....---i.---"

(1)

EI9-D

EI
V
ZONE

E9-0
8E-0633

Figure 12-24 Horizontal and Vertical Zone Flip-Flops

12.4.2.3 Starting Address Register Logic - The Starting Address Register logic is shown in Figure 12·26. The logic
includes two Starting Address Registers: one is a 12-bit register comprised of two DEC 74174 ICs (hex flip-flop);
the other uses three bits of a DEC 741751C (quad flip-flop). The Address Counter is comprised of four DEC 74193
ICs (4-bit up-counters) connected in series and is preset from the Buffer Registers.
The control signals that load and clock the Starting Address Registers and the Address Counter are generated by the
Starting Address Control logic, shown in Figure 12-27. When the program lOT instruction DPLA is issued, the 12-bit
starting address is placed on the DATA lines. The DPLA L signal causes both the DATA EN A L and DATA EN B L
signals to be asserted. The starting address is gated through the NAND gates to the DEC 74174 inputs and loaded
into the buffer at TP3 time by the LD ST ADD signal.
The extended field must also be identified by the EMA bits. The extended field address bits are placed on lines
DATA 6, 7, and 8 by the DPGO lOT instruction. Th~ DPGO L signal causes the DATA EN signals to be asserted,
gating the extended address to the DEC 74175 inputs. At TP3 time the XST ADD REG is loaded by the LD XST
ADD signal (DPGO).

12-39

E16 ClK UP
780 KHz
(32 CHAINE)

I IIIII III II II I II I I I I II I II I II I I I II II I II I I III I I I II I I I

EI6-A

E16 -8

EI6-C
E16 CARRY
156 KHz

u u u u u u u u
I

Ef8-A

U L
I
I
L

E18-8

EI8-C

EI8-D

EI8-CARRY
(LINE COUNT)
HSYNC
15.6 KHz
I
I

H ZONE (1)

I
I

GRAPHIC _+L _______ -:.I_ __
ALPHANUMERIC /
8E-0634

Figure 12-25 Alphanumeric and Graphic Line Timing

The DPGO l signal also clears the MAINT/GO flip-flop (Figure 12-27) at TP3 time, negating the MAINT l signal.
This negated signal enables a vertical sweep synchronizing signal, E46(O), to assert the lD ADD CNTR l signal. This
signal loads the starting address (including the extended address) into the 15-bit Address Counter.
At approximately the same time that the Address Counter is loaded, the Data Break Counting logic is readied for
triggering. When the sweep is in the specified position, the COUNTING signal is generated, enabling the Data Break
Control logic to request a data break. If the VT8-E has highest priority, the MACO and MAC1 flip-flops in the Data
Break Control logic are set. The MACO(1) and MAC1 (1) signals gate the 15-bit starting address from the Starting
Address Register outputs onto the MAO-11 and EMAO-2 lines. At TP1 of the data break timing cycle, the MAC2
flip-flop in the Data Break Control logic is set. The MAC1 (1) signal then enables the Starting Address Control logic
to assert the ClK ADD CNTR signal at TP4 time of the data break timing cycle. Thus, the address in the Starting
Address Register is counted up by one. The next data break timing cycle transfers the data word in the new address
to the VT8-E.
12.4.2.4 Data Break Counting logic - The Data Break Counting logic is shown in Figure 12-28. This logic
generates the COUNTING signal that enables the Data Break Control logic to request data breaks. When the
PRESET BRK signal is generated, flip-flop E43A is set, asserting the COUNTING signal. The COUNTING signal
enables the NBR flip-flop in the Data Break Control logic to be set at INT STROBE time. If the VT8-E has highest
priority, data breaks begin. Each TP1 signal of a data break timing cycle causes NAND gate E42 (Figure 12-28) to
assert the COUNT BRK signal. This signal is counted by the 4-bit up-counter, E53. When the correct number of data
breaks has been performed, flip-flop E43A is cleared via NOR gate E33 and data breaks cease.

12-40

..------,

CLK ADD CNTR
DATAII L

DATA 10 L

DATA EN B L
DATA 9 L

~1~~
'"

EI5
74174
HEX
DO FIF QD I---- DO

DATA 8 L
]

QD
LOAD CARRY

24./

DATA 7 L
]

QB
E16
74193
4-BIT
UP CNTR
r
QC
DC
QC

p'lO

YbP'::r=!
~P9

UP COUNT
DA
QA

QB f - - DB

DATA 6 L

r--

r-- -

DATA 2 L

DATA 1 L

DATA 0 L

]
]

MAR 10

MACO (1)

I E3

MA9 L

MA8 L

MA7 L

MAR 8

QC f - - f- DA

QD H-

MAR 7

]

OF r---r-

DD
QD
LOAD CARRY

LD ST ADD

MAR 3

MAR 2

MAR I

QA
E3
74175
' - - - DB QUAD
FIF Os

DC
Oc
DD

QD
CLOCK

LD X ST ADD

I
I

I B-

MA5 L

MA4 L

I
I

:v·I N:vI

MA3 L

MAR 0
MACI (1)

MA2 L

EMAR 2
E4
74193

EMAR I

DD
LOAD

G)-

MAl L

MAO L

I
I

UP COUNT
-

MA6 L

""--

QE H-

CLOCK

·II :8I

E8
74193

I
I

MAR 4

MAR 5

UP COUNT

MAIO L

I
I

E7
74174

MAIl L

MAR 9

EI2
74193

QB r---- r--- DD
QD
LOAD CARRY

23 /

•

MAR 6

QA r---- r--- DC

------DATA 3 L

CLOCK

DATA 4 L
]

MAR 11

UP COUNT
r- DA
QA

I
DATA 5 L

I P/O M8337

~
I

I
I

I
EMAR 0

EMA2 L

=E)-

EM AI L

EMAO L

L _ _ _ _.J

LD ADD CNTR L
NOTE'
Log-ic is PIO M8335 uniess noled.

8E-0635

Figure 12-26 Starting Address Register Logic

12-41

+5V
DPLA L 4...---0..---.........

t)--'---------- DATA EN B L

;>0-----------------.....- - - - - - - DATA EN A L
) - - - - - - - - - - - - - - + - - - - - - - LD ST ADD
TP3 --+---\

>--+-------- LD XST ADD
DPGO L -_-------<:1
INITIALIZE - - - - - \

+3V

E56
MAINTI
GO
C
0 1 - - - - - +.....- - - - - - - MAINT L

)------+----1D
DATA 10 L ---~_J

I 1 - - - - - + - - - - - - GRAPH/ALPHA( 1)
E55

GRAPH/
ALPHA
L------IC
01-------+------- GRAPH L

E46 (0)
(V SYNC TIME)---------------------------L~~

TP4

LD ADD CNTR L

...------------,
I PIO M8337
I
I
~

____

..!-I_ _ _ _ _ _ _ _ _ CLK ADD CNTR

IL _
-=
MAC2(1)~ I
_ _ _ _ _ _ _ _ _ _ -'

NOTE·
Logic is P/O M8336 module unless noted.
8E-0636

Figure 12-27 Starting Address Register Control Logic

12-42

G~~~~~----------------I

E9-C - 1 1 - - - - - - - 1
E19-0 - i 1 - - - - - - - - - - - 4 C l
E8-A--L---------~==-~~~

V ZONE (0) - - I I - - - - - - - - - - - - - = - - - - = - - - o t__
BO

fOI-~--+--I

E33
8266

I
I
I

MAINT L - - - - - - -.......-10

I
I
L

E43B
V SYNC L -.--q

>----.-t--lC

,.
GRAPH/ALPHA(IlH
(LO FOR ALPHANUMERIC SELECT B)

---------,---1
+ V

+3V
J

E48B
C
7473
K
0

TP1-~~

MAC 1(0)

E48A
C
7473
K
0

1 COUNTING

E43A

7474

---,

CLEAR
QO
E53+16
DEC 74193
COUNT UP

I
GRAPH L---4~t-~

NOTES;
I.Logic is P/O M8337 Module. unless noted.
2. W4 connected' 32 characterslline
W5 connected'64 characters/line

P/O

INITIALIZE
8E-0637

Figure 12-28 Data Break Control Logic

If the logic has been programmed for an alphanumeric display (assume 32 characters/line), 32 data words must be
loaded into the Line Buffer Register during two scan lines of the character row. During each of the eight remaining
scan lines, the Line Buffer Register is recirculated. Thus, new information is loaded once every ten scan lines and the
PRESET BRK signal must be generated only once every ten scan lines.
Note that. the logic within the dashed line in Figure 12-28 generates the PRESET BRK signal. The VSYNC L signal
prepares this logic for triggering by setting flip-flop E43B, thereby asserting the GO AFTER VSYNC signal (the
MAl NT L signal is negated by the Starting Address Control logic when a DPGO instruction is issued). VSYNC L also
clears the 4-bit up-counter and the two J-K flip-flops. When the VZONE flip-flop is set, NAND gate E7 is enabled.
EachE19 CARRY signal that occurs causes PRESET BRK to be generated. Because E19 CARRY occurs once every
ten scan lines, the Line Buffer Register is loaded once every ten scan lines, as required.
Figure 12-29 illustrates the timing of the counting network for an alphanumeric display of 32 characters/line. This
timing applies to a graphic display, as well, although the GRAPH L signal would be asserted for such a display. If the
logic has been programmed for a graphic display, the PRESET BRK signal must be generated differently. Sixteen
data words are needed to display one line of graphic data. Thus, the Line Buffer Register can hold two lines of
graphic data. Since a line of graphic data is displayed by one scan line, a PRESET BRK signal is required once every
two scan lines. The logic in Figure 12-30 is used to generate the Graphic mode PRESET BRK signal. It is similar to
the PRESET BRK logic in Figure 12-28. The VSYNC L signal is used in the same way and the data breaks are
counted by the counting logic in the same way. The LN CNT signal occurs at the end of each scan line, but the
E19-A signal is high for every other scan line. Consequently, the graphic PRESET BRK occurs once every two scan
lines.

12-43

VSYNCLU

PRESET BRK

--------~

COUNTING

IL._____. . .

E48B(0)

E48A(0)

~--------------------------

--.J----

QD _ _ _ _ _--',

(WHEN MAC (1)IS

1'----____

S~~~ _ _ _--uII..............
IIII...............
IlIlu..u..IIIIL..J,..L.l..IIIJ..I..L..L.IlII.u..u.IIIIJ.J..I...IIIII..LJ.J...III_ _ __

GRAPH L

E33A

~L-_ _ _ _ _ _ _ _ _ _ _~
BE -0638

Figure 12-29 Data Break Counting for 32 Characters/Line

E9-C - - - - - - - 1
E19-D -----------4L~
E8-A------------~

v ZONE(O)-------------===----<L~
fn=An

r 7c;"M-;3-;- - - - - - --,
p

I
I

MAINT L

PRESET
BRK

D
E43B

VSYNC L

>--- LINE CNT

L ________ ..JI
GRAPH/ALPHA (IlH
(HI FOR GRAPHIC. SELECT A)

NOTE:
Logic IS P/O M8336 Module unless noted

8E-0639

Figure 12-30 PRESET BRK Generation Graphic Mode

12.4.2.5 Data Break Control Logic - The Data Break Control logic is shown in Figure 12-31. When the
COUNTI NG signal is asserted by the Data Break Counting logic, NAND gate E52 is enabled. (MAl NT L is negated
by the DPGO instruction and HALT BRK L is asserted only for line-feed or end-of-screen.) The NBR flip-flop is set
at INT STROBE time, asserting the NBR (1) signal. This signal asserts OMNIBUS signals CPMA DISABLE Land
BRK IN PROG L and causes the VT8-E priority to be placed on the DATA lines during TS4. CPMA DISABLE L
causes the CPU CPMA Register to be disconnected from the OMNIBUS MA lines, while BRK IN PROG L ensures
that only data break devices place priority information on the DATA lines during TS4.

12-44

NBR(1)
rOT 3· MAINT L - - - - - - - < l i

D
COUNTING
HALT BRK L
MAINT L -____J

CPMA DISABLE L
E41A
NBR

BRK IN PROG L

INT STROBE - - - - - - - - { " " - - -

0
W1
W2
W3

0~---------~D~AT~A~9L
~0---------~D~AT~A~'~0~L
~0---------~D~AT~A~I'~L
MACO(1)

E38 . . . - -__-1

MS,IR DISABLE L

MY PRIORITY L -----------f~e_---__d

BREAK CYCLE L

MD DIR L
TP4----------_+-f~

1 MAC1(1)

E46A
MACI

M AC2 (1)

MACHO)

E41B
MAC2
TP1

~-----+_--------~---_+----~C

o I--_ _-'--M'--A-=-C2::..:(--,-,0)

fPi'OMa335 - -- - - --,

INITIALIZE

NOTE'
Logic is P/O M8337 Module unless noted
8E-0640

Figure 12-31

Data Break Control Logic

If the VTS- E has highest priority, MY PRIORITY L is asserted by the Priority logic (Figure 12-33). This signal is
NANDed with the O-output of the NBR flip-flop to produce a high logic level at the D-input of both the MACa and
MAC1 flip-flops; the flip-flops are set at TP4 time via NAND gate E2S. The MACO(1) signal asserts MS, I R DISABLE
L, BREAK CYCLE L, and MD 01 R L, and enables the MAC2 flip-flop to be set at TP1 time of the data break cycle,
thereby asserting MALC L. These OMNI BUS signals complete the CPU takeover process. MS, I R DISABLE L forces
the CPU to enter the Direct Memory Access (DMA) state and disables the CPU I R Register. The MALC L signal
prevents the CPMA Register from being clocked during the data break operation, while the BRK CYCLE L signal is
applied to the programmer's console and can be monitored on the display panel.
The MD DIR L signal is asserted so that the data word transferred during the data break timing cycle is rewritten in
the memory location during the write half of the memory timing cycle.
The MAC1 (0) signal is applied to NOR gate E42 to ensure that MACO and MAC1 can be cleared by TP4 whenever
NBR is cleared at INT STROBE time. The MAC1 and MAC2 outputs are used as gating signals elsewhere in the
Display logic.

12-45

LF CODE L
BMD 10
BMD 9

LF 1
E47A
C
7473
J

BMD 8
BMD 11
BMD 7
BM06
BMO 5

COUNTING
MAINT L

D
EOS CODE L

COUNTING
H

GRAPH L

E41
NBR

MOl L

C
J

MD2 L

ECF

C E47B
7473

MAC2(0)

HALT BRK L

TRUTH TABLE
J-K FLIP-FLOP
Tntl

Tn
J

0
0
1
1

0
1
0
1

Qn
0
, 1
On

FIN,
SHIFT
E51

C
V SYNC L

MAC2(1)

BRK
SHIFT H

Tn: bit time before clock
Tn<1 : bit time ofter clock
NOTE:
Logie is P/O M8337 Module

BE -0641

Figure 12-32 Data Break Halt, Line Feed/EOS Logic

12.4.2.6 Data Break Halt, Line Feed, and End-of-Screen Logic - The Data Break Halt, Line Feed, and
End-of-Screen logic is shown in Figure 12-32. This logic is used to clear the NBR flip-flop and stop Single Cycle Data
Breaks as follows:
a.

If the line feed ASCII code (012) is detected on the MD lines, E47A sets. This clears NBR if the counter
has not overflowed and the Maintenance mode is not enabled.

If the Character Counter overflows when 64 or 32 characters are transferred, counting is negated.

If the EOS code is detected (Figure 12-7) and EOS CODE l is asserted.

If V SYNC L is asserted at the end of the vertical scan.

If NBR is cleared by EOS CODE or LF CODE before the Character Counters have counted 64 or 32 characters, FIN
SHI FT (E51) sets. This allows the counters to continue counting until they overflow (read all Os) so that they will
contain a 0 count when the next data break is initiated. FIN SHIFT also allows BRK SHIFTS to be generated in
order to shift the line buffer data into the correct position. FIN SHI FT is clocked at each TP4 time and will clear at
. the first TP4 time after COUNTING is negated.
IOT3 • MAIN L is used to set NBR to cause one Single Cycle Data Break if the DPMB Maintenance instruction is
executed by the program.
12.4.2.7 Priority Logic - The Priority logiC is shown in Figure 12-33. Similar logic is contained on all interfaces
that connect to the OMNIBUS. Priority is checked during TS4 immediately following the INT STROBE signal that
sets the NBR flip-flop.
The VT8-E can have priority 10, 11, or 12. The device having the lowest priority (12) asserts the DATA 11 l signal
during TS4. Assume that priority 11 is assigned. This priority causes the VT8-E to assert the DATA 10 l signal
during TS4 L (jumper W2 in the Data Break Control logic is connected). JumpersPl0 and P9'must be connected in
the Priority logic. Because the DATA EN B L signal is asserted when NBR(l) is high, any data break device with a
higher priority can enable one of the NAND gates (the DATA EN A L signal is high throughout the priority check).
Thus, MY PRIORITY l is not asserted and VTS-E data breaks do not begin.
If the VTS-E is assigned priority 10, jumpers Pl0 and P9 are connected. Higher priority devices can assert any of
DATA lines 0 through S, thereby preventing the VTS-E from beginning data breaks. However, any device with a
lower priority, 11 or 12, must wait until the VT8-E relinquishes control of the CPU.
12.4.2.8 Line Buffer Register and Control Signal Logic - The Line Buffer Register logic is shown in Figure 12·34.
The register comprises four DEC 2518 ICs (hex 32-bit Shift Registers) and is loaded from the MD lines during each
data break cycle [MAC2 (0) is asserted lowl by control signals generated in the line Buffer Register Control logic
(Figures 12-35 and 12-36).
If 32 alphanumeric characters are to be displayed, Component Registers B1 and B2 are used as a 12 X 32-bit Shift
Register that is loaded with the 32 ASCII-coded characters. If 64 characters must be displayed, the Aland A2
Component Registers are also used as a 12 X 32-bit Shift Register. However, the two 12 X 32-bit registers are loaded
alternately, word by word from the MD lines. Consequently, they function together as a 12 X 64-bit Shift Register.
If graphic data is displayed, the A and B Registers operate as two independent 12 X 32·bit Shift Registers. While one
is displaying two scan lines of data, the other is refreshing for the next two scan lines.
When the LD B L signal, for example, is asserted, the 12 X 32-bit BRegister can be loaded from the MD lines. Data
gated to the LOAD inputs is shifted by the ClK B signal. When the lD B l signal is negated, the lOAD inputs are
disabled; the CLK B signal produces an end-around shift of the data. that has been loaded.

12·47

DATA 11 L -------<f----.".
DATA EN A L --.-----<t
DATA 10 L --t---=--~I~

D AT A 9 L --+-t---::-----<:I

DATA 8 L -t-----cr-

DATA 7 L - t - - - - - a

DATA 6 L -+-----<1

DATA 5 L - t - - - - - a

D A T A 4 L --t------<f-----.,
MY PRIORITY L

DATA 3 L - t - - - - - a

DATA 2 L --+-----a

DATA 1 L - t - - - - - a

DATA 0 L --+-----<1

Logic is PIO M8335 module
unless noted

NRB (1)
J:)-~---'L....;""'" DATA

EN B L

L _ _ _ _ _ _ _ _ -'

TO OBTAIN

CONNECT JUMPER

PRIORITY 12

Pg', PlO'

PRIORITY 11
PRIORITY 10
8E-0642

Figure 12-33 Priority Logic

Three DEC 74157 ICs (quad multiplexers) are included in the Line Buffer Register logic_ The READ SELECT signal
controls the multiplexers, causing either the A n inputs or the B n inputs to be gated to the f n outputs_ The outputs
are transferred to the Video Buffer logic, alphanumeric or graphic, and converted to serial video information.

Figure 12-37 shows a timing diagram that illustrates how the Line Buffer Register and the multiplexer are controlled
when 32 alphanumeric characters are to be displayed. The timing shown is relative; pulse durations, gate widths, etc"
mayor may not be actual.

12-48

r"Pio- ...,
1~8335
I
MDll L-+.-1-.q-..., 1

1 r--d~-~T---tI

t:..:.JL)-t-I--li-l

MD10 L I I

.--L--'1-L LI ----TIH LOAD
INPUTS
AI
MD8 L -ttl:-dL)-l-I_H -t1-j
HEX,32-BIT

MD9 L

MD7 L

STER
: ~-dLli------tl---rlt1 REGI2518

MD6L

SHIFT

;-,1

E16
'-- AO
~

, - - - - - - - - j 8074157

1
1
1

-82

r - B3

SELECT

LOAD
INPUTS

1
1

'------------j A 0

Bl
2518

1
1

L_~II
I. ~~~L-_~~.---------r-ll
--L

MD4 L

MD3 L

L -d

'------------i A I

.-------------------4 A2
, - - - - - - - - - - i A3 E15

'----~-+---------------4B1

.------------1B 2

.-+------------4 B3

F3
SELECT

!-~
MD2 L--j-~--}-____~~~~
-dJ
L-1-r~r-)-----~-+~~
--d J

MDO L -i-+-....:J-<l('"---..,~
MD
ENA8LE L

' - - + _ t - - - - - - - - - - - i B o 74157

r-----jB I

MDI

~aL~~pA~E:Ek

MD5

Al
A2

LOAD
INPUTS

A2
2518

AO
AI

A2
A3

E14 Fl
74157

BO
F2

r-=r-::

SELECT

LOAD
INPUTS

~+-r-r-r-----------------~

+5V
B2
2518

LDAL~~+-~-------------rr-~--~

NOTE:
Logic is PIO M8337 Module unless Noted

LDBL--~~-4------------__-+---~

eLK A ------<~l_---------------_t---------'
CLKB----~~---------------_4------~

S~i~~------------------------------------------------88E_E-~06"4~3

Figure 12-34 Line Buffer Register Logic

12-49

The period of time represented as tl is that period during which 32 data breaks are being performed (remember that
two scan lines are set aside for this purpose). During tl the line Buffer Register must be loaded from the MD lines.
The line Buffer Register Control logic (Figure 12-35) asserts the lD B l signal (the signal E19-D is low throughout
tl, keeping the VIS ZONE l signal high). Each data break cycle causes a data word to be gated to the B Register
lOAD inputs. The BRK SHIFT signal that occurs during TS3 l of the break cycle is gated through NAND gate
E37A, since the ALPHA ClK Al T is always cleared during a 32 character operation. This causes a ClK B signal to
be produced. When 32 data words have been loaded into the register, the COUNTI NG signal goes low and data
breaks cease (COUNTING goes low at TP1 of the break cycle, while BRK SHIFT is asserted during TS3 l).

VIS ZONE L

Fn= Bn

H ZONE (I)
V ZONE (I)
EI9-D
MAl NT/GO ( 1 ) - - - - - - - - 1 - . - /

Ao
BO
AI

B I E33
A2 8266
E32
B2

EI7 CLK

SHIFT LINE BUFFER

A3
ClK AL

MAINT
GO (I ) H -~"-----_'/

Fn= Bn

32
(2,3,OR4 DECODED BY E22
OCCUR BETWEEN EACH EI7
CARRY IN VIS ZONE)

BO
AI

VSYNCL---~~--~

B1 E28
A2 8266

D
NOTE:
1. Logic is PIO M8336 Module
2. Connect jumper '32' for 32 Char/Line
3. Connect jumper '64' for 64 CharI Line

r---~--~ B2

E38B

CLK B L

GRAPH/ALPHA (I) H _ _- - - - - '
INIT L ---!,4

~(LO FOR ALPHANUMERIC)
8E-0644

Figure 12-35 Line Buffer Register Control logic

Throughout each of the next eight scan lines, the Line Buffer Register must be shifted end-around. Period t2
represents the third scan line and the beginning of the fourth. The VIS ZONE l signal is asserted when HZONE(1)
goes high. The lD B l signal is negated, placing the register in the recirculating mode. During the time that VIS
ZONE l is low, the VTS-E timing generates 32 SHIFT LINE BUFFER signals. These signals enable NAND gate
E37A, thereby generating the ClK B signal. The register is shifted end-around by 32 ClK B signals. (Note that 31
ClK B signals are sufficient to shift all 32 characters through the multiplexer, but 32 are needed for the
recirculation.) Each time a character is placed on the register outputs, the multiplexer gates it to the ROM Character
logic (only the 6-bit ASCII code, bits 6-11, is gated to the ROM), There it is converted to serial video information
for display.

12-50

V SYNC L

Fn=An
GRAPHIC
PRESET

AO
FO

E32
GRAPH
LOAD
ALT AlB

PRESET BRK
LD A L

LD B L
F3

+3V

CLK A L

F=5.46MHz
Fn=An
AO
H ZONE (1)

V ZONE(1)

B, E2B
L--t---1A2 8266 F2
82

READ SELECT
(LO SELECTS A)
CLK B L

FoD--r--t----I-~

BRK S H I F T - . - - - - t - - - t - i A o

F1 D - - r - - '

L-.----IA,

.:>O----CIIB1 E36 F2
A2 8266
F3
GRAPH/ALPHA(tlH
( H I FOR GRAPHIC)
NOTE:
Logic is PIO M8336 Module

9
(PIN 9HI'Fn=An)
L-._---' (PIN 9 LO' Fn=Bn)

BE-0645

Figure 12-36 Line Buffer Register

The same operation is performed during each succeeding scan line. At the end of the tenth scan line, the character
line has been displayed. Another PRESET BRK signal is generated and 32 more characters are loaded into the Line
Buffer Register. Note that as these next 32 characters are shifted into the register, the 32 displayed by the
just-completed character line are shifted out. Because video is not enabled unless VIS ZONE l is low, there is no
danger of these earlier characters being displayed again.
Figure 12-38 shows a timing diagram that illustrates how the Line Buffer Register and the multiplexer are controlled
when 64 alphanumeric characters are loaded from the MD lines. Both the A and B Registers are used, providing 64
bits of storage space. As the timing diagram illustrates, the A and B Registers are loaded alternately so that each
contains 32 characters when 64 data breaks have been completed_ The registers are alternately recirculated during
each succeeding scan line (this timing is not shown, but is similar to that of Figure 12-37); when the characters have
been displayed, 64 new characters are shifted into the register.
Figure 12-36 shows the logic that controls the Line Buffer Register and the multiplexer during a graphic display.
Figure 12-39 shows a timing diagram that illustrates how the graphic data is transferred through the Line Buffer
Register logic. Read Select changes every Graphic PRESET which corresponds to every other scan line within the
visible zone_ When displaying Reg A, elK A l is generated once for every 12 graphic dot positions that are
displayed. This shifts a new word to the output of the Shift Register. The word is then loaded into the Video Buffer
after the 12 bits of the previous word have been displayed.
Both the A and B Registers are used when graphic data is displayed. One register is loaded from the MD lines with 32
data words; simultaneously, the information in the other register is displayed.

12-51

t1
PRESET BRK
COUNTING

~--------------~f'FC------------------------~0F'--------------------~-------

..--J

fE11-_______- I S ' F - - - - - - - - - -

F-----------------------~~Fr---------------------------F---------------------~f,~r------------------------F---------------------~~~c-------------------------

RECIRCULATE

~~...______......

RECIRCULATE B

F---------------------~,,~c------------------------CLK B

H ZONE (1)

-.Jlf1J1J1.fU1J
C.F---o
I

'--------.....

----------------~~~'------~
VIS ZONE L
I~------~
L . . - - - - - - - - I f,1'----1
BE-0646

Figure 12·37 Line Buffer Timing for 32 Character Line

V SY N C L 11---------------:l0',f-'------------....,

PR ESE T BRK

JL...-__________

-;f,FC_____________

c ------.L.-__~_
CO UN TIN G .--J~-------------;f ,f-

BRK SH I FT

---.llJUU1JUl...JUUUUl
II n

ALPHA CLK
ALT AlB (I) .J

n n I,c~n LJn LJr - -

LJ LJ

READ AlB (1) JUUl.Jl...,~
SELECT A

READ SELECT

LD A L. LD B L

------------------i,JF

c _ _ _ _ _ _ _ _ _ _ _ __

8E-Q647

Figure 12·38 Line Buffer Timing for 64 Character Line

12·52

PRESET BRK

n·

1=128.2,,"

I
r

2SCAN L1NES---1l

GRAPH LOAD ALT AlB (I)

LD A L

LOAD A

RECIRCULATE A

LD B L

RECIRCULATE B

LOAD B

BRK SHIFT

CLK A

111111111 32 P\\SES

111111

Iij

111111

11111

32 PULSES

16 455KHz
PULSES

16
,.---A--..

1111111111111111

III

1111

11111

IIj

11111

III

11111

1111111111111111

I'
Ii

1111

11111

((

1111111111111111

READ SELECT
AL/B H
H ZONE (I)

V ZONE (I)

CLK B

16 455KHz
PULSES

32 PULSES

1111111111111111

32
A

1111111111111111

1111111111111111
8E-0648

Figure 12-39 Line Buffer Timing

12.4.2.9 ROM Character Generator Logic - The ROM Character Generator logiC is shown in Figure 12-40.
Included in the figure is a representation of the alphanumeric Video Buffer Register. The major components of the
Character generator are three 23-XXA2 1024-bit read-only memories; each is organized to provide 256 4-bit word
locations. A functional logic diagram of 23-XXA2 is shown in Figure 12-41.

ASCII-coded characters are gated from the Line Buffer Register to each ROM on the six lines designated BIT 6-11.
The five most significant bits of the character, bits 6-10, are applied to a 1-of-32 decoder (Figure 12-41). The ROM
ROW CNT signals, generated in the VT8-E timing, are applied to 1-of-8 decoders. These three signals select one of
256 4-bit data words. The LSB of the ASCII character, bit 11, is used to gate the 4-bit word out of the ROM to the
Video Buffer Register, a DEC 7496 5-bit Shift Register. As Figure 12-40 shows, an odd ASCII character (bit 11 is
logic 1) causes the ODD ROM outputs to be selected, while an even character causes the EVEN ROM to be selected.
The XTRA ROM provides the necessary fifth bit of the data word and is selected for both even and odd characters.

Remember that ten horizontal scan lines are required to display one character line. During the first two scans, the
characters are shifted into the Line Buffer Register. During each of the next eight scans, the Line Buffer Register is
recirculated. Bits 6-11 of a character are the same during each scan. The ROM ROW CNT signals change during each
scan, cycling through the counts 0002 to 11 h, where ROM LS ROW CNT is the LSB. Consequently, eight
consecutive locations are selected for each ASCII character. The first location is blank, the next seven contain the
video information that is ultimately displayed.

12-53

ROM MS ROW CNT
ROM ROW CNT
ROM LS ROW CNT
BIT 11

+5V

I I

BIT 10
BIT 9
BIT 8
BIT 7
BIT 6

~ ~

5
6
7
13
9
14
4 2~~~A210
3 EVEN
ROM
11
2
1
15 E22
12
5
6
7

LD
CLK
ALPHA
ALPHA
VID B(FER VID rUFFER

I I I

5
13

14 DEC
10
423-015A2
3 ODD
11
2 ROM

1
E2
15

4
3
r--

I
I

5
13
14

~~VT
REG

I
I

E13
DEC
7496

SERIAL OUT

+5V
9

423-013A2 1O
3 XTRA
2 ROM
11
1
15 E26
12

E17
0

.......--

E17

E17
C

NOTE:
Logic is PIO

M8337 Module
SE-0649

Figure 12-40 ROM Character Generation Logic

Consider the ASCII code for the character H: 001 000 (10 8 ), Bits 6-10 (001 00) are, applied to the 1-of-32 decoder
during each scan. During Scan Line 3, the ROM ROW CNT signals are low (000 2 ), The data in the addressed location
is 0000, and no video is displayed. During Scan Line 4, the ROM ROW CNT signals are 001 2 • The data in this
location is 1000 and is displayed as video. Table 12-8 relates the eight scan lines, the ROM ROW CNT binary
representations, and the data in the addressed locations.
The fifth data bit for each scan is taken from the XTRA ROM. Note that only two outputs are available from this
ROM. If the character is even, the output at pin 11 is gated to the Video Buffer; if the character is odd, the output
at pin 12 is gated. This ROM is addressed exactly as is the EVEN ROM, as indicated in Table 12-9. The fifth data bit
for H is taken from pin 11 of the XTRA ROM. The result is shown below.
Scan Line

Data Bits Gated to
Video Buffer

3
4
5
6
7
8
9
10

00000
10001
10001
10001
11111
10001
10001
10001

NOTE: The pattern is generated for H.

12-54

BIT 6 - 1 5

BIT7- 1

1024- BIT MEMORY CELL
32 X 32
MEMORY MATRIX

1-0F-32
DECODER

BIT 8 - 2

BIT 9 - 3

BIT 1 0 - 4

ROM MS ROW CNT-7 _ _ _ _ _ _ _ _ _-f...l....l...l....l..J.,.JL.-.L..~
ROM ROW CNT - - 6 - - - - - - - - - - ;

.-_J

ROMLSROWCNT-5~---------t_ _

BIT

l1L

13
14

~"'--

Figure 12-41

ROM Functional Logic Diagram

Table 12-8
Character H, EVEN ROM Data Bits
Scan Line

Bits 6-10

ROM ROW CNT Binary
Representation

Data Word in
Addressed Location

00100
00100
00100
00100
00100
00100
00100
00100

000
001
010
011
100
101
110
111

0000
1000
1000
1000
1111
1000
1000
1000

5
6
7

8
9
10

12-55

8E-0650

Table 12·9
Character H, XTRA ROM Data Bits
Scan Line

Bits 6-10

ROM ROW CNT Binary
Representation

Data Word in
Addressed location

3
4
5
6
7

00100
00100
00100
00100
00100
00100
00100
00100

000
001
010
011
100
101
110
111

0000
0010
0010
0010
0010
0010
0010
0010

8
9
10

PIN 11

PIN 12

The pattern table for each ROM is included in Appendix A. To locate the pattern for an ASCII character, use the
following procedure:
Procedure

Step

If the character is even, divide the 6-bit binary representation by 2. The result gives the 6
most significant bits of the location.
2

Find this location in the Octal Location column of the EVEN ROM pattern table (Table
A-l) for 4 of the data bits; find the same location in the Octal Location column of the
XTRA ROM pattern table (Table A-3) for the fifth data bit.
For example: When the binary representation of character T, 010 100 (24 8 ), is divided
by 2, the result is 001 010 (12 8 ); octal locations 120-127 of the EVEN and XTRA
ROMs contain the video information for the character.

If the character is odd, take the even binary representation immediately preceding the
odd binary representation and divide by 2.

Find this location in the ODD and XTRA ROM pattern tables (Tables A-2 and A-3).
For example: To find the pattern for character G, 000 111 (07 8 ), divide 000 110 (06 8 )
by 2; the result, 000 011 (03 8 ), identifies locations 030-037 as yielding G.

12.4.2.10 Alphanumeric Video Buffer Control logic - Figure 12-42 shows the alphanumeric Video Buffer Control
logic. The logic generates the signals that allow the Video Buffer to convert the parallel ROM bits to serial
alphanumeric video bits. The logic is shown for 32 characters per line; if 64 characters per line are being displayed,
the input clock frequency is 10.92 MHz. Figure 12-43 shows a timing diagram for the 32 character per line
operation. Refer to both figures when reading the logic description.
The 5.46 MHz signal is gated by the logic to produce the LD ALPHA VIDEO BUFFER and ClK ALPHA VIDEO
BUFFER signals. The E17 up-collnter provides the necessary gating signals. The A, H, and C outputs of E17 are
applied to the DEC 7442 BCD-to-Decimal Decoder, E22. When E22 decodes deCimal 2, E26C is enabled and the
next clock produces a lD ALPHA VIDEO BUFFE R signal. When E22 decodes decimal 3 through 7, E26B is enabled

12-56

and 5 clock pulses are gated through to produce ClK ALPHA VIDEO BUFFER. A VID EN signal is also generated
when E22 decodes decimal 3 through 7. This signal is asserted through the E28 multiplexer when the VIS ZONE l
signal is low (note that the VIS ZONE l must be low for E22 to decode decimal 1 through 7).
Because E17 determines character rate, one lD ALPHA VIDEO BUFFER signal, one VID EN signal, and five ClK
ALPHA VID BUFFER signals are generated each time a character is shifted from the Line Buffer Register.
Remember that 32 SHIFT LINE BUFFER signals are used to recirculate the Line Buffer Register during each scan.
Each SHIFT LINE BUFFER signal generates a ClK B signal that shifts a different character to the ROM Character
Generator. The character generator produces five bits that represent the character. A lD ALPHA VIDEO BUFFER
signal then parallel loads these bits into the Video Buffer Register.
Five ClK ALPHA VIDEO BUFFER signals shift the data bits out of the buffer to the video logic. The VID EN
signal enables the video logic to generate signals for the display. Note that the lD ALPHA VID BUFFER signal,
designated A in Figure 12·43, loads the character that is shifted from the Line Buffer Register by the ClK B signal
designated A. While this character is being shifted from the Video Buffer, the new 5-bit character is being gated to
the buffer inputs. Note, also, that the character horizontal spacing is determined by the gating of the 5.46 MHz
signal. The character width is represented by five clock pulses (0.185 inches for 32 characters!1 ine); the horizontal
spacing is represented by the two clock pulses in each character period that are not gated (indicated by the
dotted-line ClK ALPHA VIDEO BUFFER pulses). Thus, the spacing is 40 percent of the character width, or 0.074
inches.
Figure 12-44 shows the timing of the alphanumeric Video Buffer Control logic for 64 characters per line. The logic is
the same as for 32 characters per line operation.

+3V

A
F=5.46 MHz
(32 CH/LiNE ) -.......---.:tCLK

CARRY
E17.;-7
74161

ABC

LOADp-------'

) - - - - - t - - - - - - - LD ALPHA VID BUFFER
L..---t----if--I LSB
CLK ALPHA VID BUFFER
E22
7442
BCD-DEC
DECODER 3

Fn"Bn

H ZONE ( 1 ) - - - - - r -.......
v ZONE ( 1 ) - - - - - 1 E14 lO---<l.---IMSB
E19-D
(F= 1.56KHz)

FO
VID EN

VIS ZONE L

NOTE:
'Logic is P/O M8336 Module
GRAPH/ALPHA (1)
(LO FOR ALPHANUMERIC)
8E-065t

Figure 12-42 Alphanumeric Video Buffer

12-57

151

I 10 I 11 I 12 I 13 I 14 I 15 I 9 I 10 I 11 I 12 I 13 I 14 I --I 1:5.8n5

5.46 MHz
1--183.15n5
E17 A

E17BU

E17 C

L
L

l . ._____--'

EI7D-------------------------------------------CHARACTER RATE 780KHz

SHIFT LINE BUFFER _ _ _ _...J1'==549.45n5

-===1. .____________---'
B

CLK B

READSELECT----------------------------------------(B-H)
IDOTI
DOT3 IDOT4 IDOT5 I CH SPACING I
.-.

CLK ALPHA VID BUFF

ALPHA VID ENAB 780KHz

I I
I I

1-'
I I
I I

lL.___J"I~~---

.-,
I I
I

915.75n5

---./~L.I

I-I
I I
I I

___--,

114~------1.28j15 ------.j~1

L
8E-0652

Figure 12-43 Character Timing for a 32 Character Line

12_4.2.11 Graphic Video Buffer and Control logic - The Graphic Video Buffer and Control logic is shown in
Figure 12·45. This logic converts the parallel data in the Line Buffer Register to the serial graphic video signals that
are applied to the Display Mode logic.

When a data word is shifted from the Line Buffer Register, it is applied to the Graphic Video Buffer on the lines
designated BIT 11-0. The Video Buffer Register comprises three DEC 7595 4-bit Shift Registers that can be parallel
loaded and serial shifted. The DEC 74161 counter, E31, counts down the 5.46 MHz clock pulses to produce an lD
GRAPH VID BUFFER signal at a frequency of 455 kHz. The derivation of this signal is shown in the timing diagram
in Figure 12·46. Graphic Video Buffer is loaded by ClK GRAPH VID BUFFER when lD GRAPH VID BUFFER is
true. This occurs every 12 clock pulses.

When the Video Buffer has been loaded, the lD GRAPH VID BUFFER signal goes low. The DEC 7495 Shift
Register cannot be shifted while this signal is high. The next eleven ClK GRAPH VID BUFFER signals shift data
out of the register (bit 0 is shifted out first). Note that bit 11 is not shifted from the register since only 11 shift
pulses are available. Twelve ClK GRAPH VID BUFFER signals are also used to chop graphic video into distinct
dots. This occurs at AND gate E28.

12-58

I 9 I 10 I 11 I 12 I 13 I 14 I 15 I 9 I 10 I 11 I 12 I 13 I 14 I 15 I

10.92 MHz ClK

E17 A

E17B~
E17 C

_ _ _ _ _ _.....

E17D-~--------------------------------

I-

u..-----------.u

641ns

1.56 MHz CHARACTER RATE U

E 12

IL_______________

---J

EI2-CARRY,780 KHZU

lD ALPHA VID BUFF

----~

~--------------~

I
U

~----------

-'F =-=1. .________. .

SHIFT liNE BUFF _ _ _ _ _

274 ns

ClK A

(7BO K H z ) - - - - - - - - - - - - - - - - - - - - - - - - - - - '
ClK B

READ SELECT (B-H,A-L)

ClK AlPH VID BUFF

ALPHA VID EN

1 . .___ 1
----1

1
8E-0653

Figure 12-44 Character Timing for a 64 Character Line

12.4.2.12 Visible Field Logic - When an alphanumeric character is to be displayed, the data word transferred to
the Line Buffer Register contains not only character information, but also information that controls the visible field
and the mode of display. The 12·bit data word is shown in Figure 12-47.
The ASCII-coded character is contained in bits 5-11. Because the VT8-E displays a 64 character set, only bits 6-11
are used to generate character video. Control bits 1 and 2 (referred to as CBl and CB2) are used to determine the
visible field by selectively blanking the video display. Control bits 3 and 4 (referred to as CB3 and CB4) determine
how the video is displayed.
Figure 12-48 shows the visible field bits logic, These' bits control the visible field as outlined in the table
accompanying the logic. When J-K flip-flop E44 is set, the BLANK L signal is asserted and the alphanumeric Video
Buffer output is inhibited (Figure 12-50 shows how the BLANK L signal inhibits video), Flip-flop E44 is controlled
in an intricate manner that can best be described by a timing diagram. This diagram is shown in Figure 12-49. The
timing begins with the start of a character line, represented by the PRESET BRK signal.
12-59

GRAPH VIS ZONE l
~....:F...;.n:....=.::.A::..n--, VI D EN

+3V E18~CARRY(LlNE COUNT)

AO
ABC
F=5.46 MHz ........- - - - - I C l K

V ZONE (1)

D
CARRY

H ZONE (1)

E31

BO
A1
B1 E28 F1
A2 8266
B2

ABC

A3
B3
GRAPHICI ALPHA (1) H) _ _---'
(HI FOR GRAPHIC)
ClK GRAPH VID BUFFER

r~~~---------------

I
I
I

BIT 11

-------,

r--=-!--.I--_ _--I_ _~

BIT 1 0 - - - - - 1
BIT 9 - - - - - I
BIT 8 - - - - - - /

I
I
I

BIT
BIT
BIT
BIT

I
I

I
I
I
I
I
L

7 ------12
6 -----I
5 -----I
4 ------15

BIT
BIT
BIT
BIT

3 ------12
1 61-----1-------'
2
3 E18 81----~
~__
1 - - - - - - 1 4 ~9591----~.
0 ------15
101----------/
NOTE'
GRAPH H
logic is PIO M8336 Module
unless noted

GO AFTER V SYNC

GRAPH
VIDEO

------------------------

I
I
I
..JI

NOTE:
logic is PIO M8336 Module unless noted.
8E-0654

Figure 12-45 Graphic Video Buffer Control Logic

Assume that a character in the previous character line had directed the beginning of a blank field; i.e .• CB1 of this
character was high. while CB2 was low. When this character was shifted from the Line Buffer Register. the next LD
ALPHA VID BUFFER signal to occur sets the J-K flip-flop E50B (Figure 12-47). Each succeeding character is either
a NOP direction or another BBF direction (both have the same result in the present situation). At the beginning of
the present character line. a PRESET BRK signal and a LINE CNT signal occur simultaneously. The leading edge of
the LINE CNT signal clears the E44 flip-flop. while the trailing edge of the PRESET BRK signal sets flip-flop E50A.
The next LINE CNT signal sets E44 again. because now E50A is set. All three flip-flops would remain in this state
throughout the entire character line and into and through each succeeding character line if no EBF direction were
received.
However. if an EBF direction is programmed into a data word. the blank field must be ended at the same point in
Scan Lines 3 through 10 (although nothing is displayed in Scan Line 3). Assume that character 16 of the present
character line directs an end to the blank field. The LD ALPHA VIDEO BUFFER signal corresponding to character
16 clears flip-flops E44 and E50B. For the rest of Scan Line 3. the BLANK L signal is negated. At the start of the
fourth scan line. flip-flop E44 has to be set again to blank the first 15 characters. The LI N E CNT signal sets the
flip-flop. thereby blanking the first 15 characters of Scan Line 4. Again. the sixteenth character says EBF and clears
flip-flop E44 (flip-flop B stays clear throughout). This procedure continues until the character line is completed. The
second LINE CNT signal of the next character line clears flip-flop E44. which then remains clear until another BBF
or an EOS is directed.
12-60

GRAPH VIS ZONE H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....1

5.46Mhz

ClK GRAPH VID BUFFER

141 51 6 171 819 110 1" 1'21'31'41'51415161718191'01" 1'21'31'41'5\
E31-A

E31-B

E31-C

E31- D

lL...-____

--'~

f=455Khz
n' - - - - - -

..J

lD GRAPH VID BUFFER _ _

LOAD

455Khz

SHI FT LINE BUFFER H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--.J

8£-0655

Figure 12-46 Graphic Word Timing

CB2

CB3

CBl

VISIBLE
FIELD
BITS

CB4

DISPLAY
MODE
BITS

I·

'-"T "'"

00"'----1
BE-0657

Figure 12-47 12-Bit Data Word Format

When the 7-bit ASCII code for line feed (012) is detected, NAND gate Ell is enabled, putting a high on the J input
of flip-flop E44. The LD ALPHA VID BUFFER signal corresponding to the character 012 sets E44, and the rest of
the character line is blanked. It would be contradictory to have the EBF control bits set for the line feed character.
The K input of E44 should not be a 1 when the LF (012) character is detected.
12.4.2.13 Display Mode Logic - The Display Mode logic is shown in Figure 12-50. These bits determine how the
alphanumeric video is displayed, as outlined in the table accompanying the logic.
When the character is to be displayed with normal intensity, the LD ALPHA VID BUFFER signal clears flip-flops
E27A and E27B. NAND gate E30B gates the serial output of the alphanumeric Video Buffer Register to NAND gate
E39. If the BLANK L signal is not asserted, the asserted ALPHA VID EN signal and the negated GRAPH L signal
gate the five data bits to the VIDEO line. If the character is to be displayed at increased intensity, E27A is set, while
E27B is cleared. NAN D gate E34C is enabled, in addition to E30B. Inverters E29A and E29B have open-collector
outputs. For increased intensity, both gates are inactive. Consequently, the VIDEO output is approximately 5V. For
normal intensity E29B is active and there is a voltage drop in the neighborhood of 3.5V across the 1 kD resistor.
Therefore the VIDEO output is approximately 3.5V.
12-61

LINE CNT
CB1
(BMD 1)
C E50B
7473
K

CB2
(BMD2)

PRESET
BRK

C E50A
7473

01-------1 K

V SYNC L
LD ALPHA
VID BUFFER
BMD 5
BMD 6
BMD 7
BMD 9

GO A~~~~ ~-+---I-O

BMD 8
BMD 10

BLANK L

-+-I C i4ji,

L--_ _ _ _ _ _

BMD 11

L-~----------------~K

E35

BMD
TRUTH TABLE
J - K FLI P - FLOPS
Tn.1

CB1

CB2

OPERATION

NOP

0
0

0
1

EBF

On
0
1
On

BBF

EOS

Tn= bit time before clock
Tn.l =bit time after clock

DESCRIPTION
DISPLAY CHARACTER IN BIT 6-11 IF IN
VISIBLE ZONE
END BLANK FIELD DISPLAY THIS
CHARACTER AND THOSE FOLLOWING
BEGIN BLANK FIELD,FROM AND INCLUDING THIS CHARACTER. VISABLE FIELD CAN
BE STARTED LATER IN BUFFER BY EBF
END OF SCREEN. VISIBLE FIELD IS
ENDED BEFORE DISPLAYING THIS CHARACTER UNTIL NEXT VERTICAL RETRACE

NOTE:
Logic is PIO M8337 Module

SE-0656

Figure 12-48 Display Control Logic

E50A(1}

----I

~I---------------I
I

E50B( I)

I
I
I

PRESET BRK

~~________________~___________________ ~~_________________
I

---~

LN CNT

E44 ( t )

l . . ___---'

U
t

CHARACTER
16 SAYS
EBF
8E-06S8

Figure 12-49 BBF and EBF Timing

12-62

OUTPUT {

7496
5-BIT S.R.

ROM

OUTPUT

E32
7474
3.75 Hz

330n
VIDEO
CB3
(BMD3)

D
E27A
7474

GRAPH L
CB4
(BMD4)

CB3

o
o

E27B
7474
C

CB4 OPERATION

o
o

NOTE:
Logic is PIO M8337 Module

NOP
BLINK
BRIGHT
CURSR

DESCRIPTION
DISPLAY CHARACTER AT NORMAL
INTENSITY
BLINK CHARACTER AT 1.875 Hz RATE
DISPLAY CHARACTER AT INCREASED
INTENSITY
DISPLAY CHARACTER AS CURSOR
BE-0660

Figure 12-50 Display Mode logic

A character is blinked at a 1.875 Hz rate when CB3 is logic 0 and CB4 is logic 1. The 3.75 Hz signal clocks flip-flop
E32. The O-output of the flip-flop alternately enables and disables NAND gate E30C, resulting in a VI DEO signal
that blinks at the desired rate. If CB3 and CB4 are both logic 1, NAND gate E30A is alternately enabled and disabled
by the 3.75 Hz signal. NAND gate E30B is enabled by the character bit, while NAND gate E34B is enabled by the
character's bit matrix complement. Thus, the character is displayed as a cursor.
12.4.2.14 Maintenance lOT Logic - The Maintenance lOT logic, shown in Figure 12-51, is enabled at TP3 time if
the program executes the DPSM instruction to set the MAl NT/GO flip-flop (E56l. Refer to Paragraph 12.3.4 for a
description of the lOT instructions enabled when the VT8-E is in the Maintenance mode. These instructions allow
the registers and buffers in the VT8-E to be read into the AC. Data may also be transferred from memory using the
DPMB instruction. DPMB sets the BRK ROST flip-flop on the M8337 module and the VT8-E executes one Single
Cycle Data Break to transfer data from the memory location determined by the Starting Address Register to the
Line Buffer.
12.4.2.15 Display Interrupt and Skip Logic - The Interrupt and Skip logic is shown in Figure 12-52. Interruptsare
enabled if bit 11 in the AC is 1 when the DPGO instruction is executed by the program. This sets INT ENA and the
VT8-E makes an INT RQST when the Real Time Clock (RTC) flag sets at the start of a vertical retrace and signifies
the end of the display frame.
The Skip Bus (SKIP L) is asserted at I/O PAUSE time of the DPCl instruction cycle to cause the program to skip
the next sequential instruction. The program may at this time switch modes (Alphanumeric/Graphic) without
disturbing the visible presentation.
12-63

INITIALIZE

+3V

MAINT/GO (1)

D
E56
MAINT/ MAl NT L
GO
C
0

DPSM L
TP3

IOT3·MAINT L
DPMB L
GRAPH/ALPHA (1)

D
E55
GRAPH/
ALPHA
C

LD ADDR CNTR L
GRAPH L

DATA 11 L

LD XST ADD

>O----*---*-------------------------------------DA~ENAL

P-----------------------DATA EN B L

P-----------------------COL
DPMS L --~----~
~-------------------------------Cl

L-4--Q

~-------------------------------------------------------X

L
BRKADDRDEN

oPMD L --------<lI > - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RD D BUFFER EN
NOTE:
Logic is P/O M8336 Modul.

Figure 12-51

BE-OGG1

Maintenance lOT logic

12.4.2.16 Bell logic - The Bell logic is shown in Figure 12-53. BEll EN, a 74123 IC, outputs a 476 ms pulse
when the DPBl instruction is executed by the program to enable the 1.56 kHz signal from E11-0 to be applied to
the bell. The volume of the tone is adjusted by potentiometer R25 on the M8336 module.
12.5 DISPLAY MONITOR CIRCUITS
12.5.1

Keyboard logic

The keyboard (Drawing D-CS-3010166-0-0) provides the VT8-E output to the computer. There are 128 ASCII
characters or codes that can be generated by the keyboard. A 2-way slide switch is mounted on the Keyboard logic
circuitry board to allow the keyboard to be set for upper/lower case ASCII (128 codes) or lower case ASCII (96
codes) operation. Each key has a variable capacitance that is actuated when the key is pressed, causing an excitation
voltage to be applied to one side of the capacitor, generating base drive for the transistor amplifier. A sequential
scanning technique is used, employing a MaS integrated circuit that consists of an 8-bit and an 11-bit ring counter
(to compose an 8 X 11 matrix), and circuitry to sample the conductance of each transistor amplifier (one per key).
As the two (8-bit and 11-bit) registers cycle, the 8-bit counter provides a collector voltage to as many as eleven of
the key output amplifiers. Up to eight of the transistor emitters are connected to each of the sensing circuits gated
by the 11-bit counter. The two sets of lines that form the 8 X 11 matrix are theoretically capable of sampling up to
88 keys.

12-64

+5V

DATA EN A - - - - - - - - - - ,

o
DATA 11 L

-f----------'

tNT RQST L

INT
ENA

DPGD L ~-----<f---,

}------1C

TP3

SKIP L
TP4

DPCL L

E9-LD
(V SYNC)

NOTE'
Logic is PIO M8336 module.
8£-0662

Figure 12-52 Display Interrupt and Skip Logic

+5V
+5V

TP3

'--------'--~.I

DPBL------------~

.;>C>---'VV____

74123
BELL
EN

-"N~-

AUD 10

(1.56KHz)
E11- 0 ----------------------------------'

NOTE
Logic is PIO M8336 module.
8E-0659

Figure 12-53 Bell Logic

12-65

The VT8-E uses the small 8-key keyboard as an extension ·of the main keyboard to generate cursor control codes to
position the cursor and to erase text. The keys used for cursor control or positioning are: cursor up (t l. cursor
down (.), cursor left (+), cursor right (.), and HOME. The erase-to-end-of-line (EOL) and erase-to-end-of-screen
(EOS) keys are used in conjunction with the LOCK key. The EOL and EOS codes will not be transmitted unless
they are used in conjunction with the LOCK key.
12.5.2 Motorola CRT Display
The following circuit descriptions refer to the detailed circuit schematic of the Motorola CRT Display Module shown
in Drawing D-CS-3010326-0-3.
12.5.2.1 Video Amplifier - The Video Amplifier has four stages incorporating devices 01, 02, 03, and 04. The
first stage, 01, functions as an emitter follower to provide a high impedance input with the 75n terminating resistor
removed. The high impedance operation permits use of bridging connections to drive a number of monitors from the
same signal source. The low output impedance of the first stage permits use of a low resistance contrast control
which furnishes flat video response over its entire range without the need for compensation. The collector output of
01 is used to drive the Sync Separator. C3 provides high frequency roll off to limit the collector output to the
band-width required to pass synchronization signals. 02 is a common emitter stage and is directly coupled to 04. 03
and 04 are connected in a cascade configuration. This common emitter/common base connection greatly reduces
the effect of Miller capacity compared with a conventional single transistor video output stage. C6 provides a ground
for video at the base of 03, the grounded base transistor of the video output cascade pair.
The video bias control (R10) is used to set the quiescent collector voltage of 03, C5, C7, C8, and R15 for high
frequency compensation. Restoration of dc voltage is accomplished by setting the video bias control so that sync
tips, which are negative-going at the collector of 03, just go into saturation. Variations in video drive result in
variations in the base current of 02 during sync time due to the low load reflected back when 03 is saturated. The
charge on C4 will t~us depend on the amplitude of output collector current during sync time. The result is a
clamping action which holds sync tips at the same level despite video signal variations. The Video Amplifier output is
direct coupled to the control grid of the CRT. R18 is used to isolate 03 from transients that may occur as a result of
CRT arcing.
12.5.2.2 Sync Separator - The Sync Separator uses a single stage, 05, to recover sync from the composite video
signal. A single-stage Sync Separator is adequate due to the high impedance of the following stages. The video input
to the Sync Separator is black positive. C11 is charged by the peak base current that flows when the positive peak of
the input takes 05 to saturation. This charge depends on the peak-to-peak input to 05.and thus makes the bias for
05 track the amplitude of the input signal. As a result, 05 amplifies only the positive peaks of the input signal. The
initial bias current through R24 sets the clipping level.
12.5.2.3 Phase Detector - The Phase Detector uses two diodes in a key clamp circuit. Two inputs are required to
generate the required output, one from the Sync Separator and one from the horizontal deflection system. The
required output must be of the correct polarity and amplitude to correct phase differences between the input sync
and the horizontal time base .. The horizontal collector pulse is integrated into a sawtooth by R45 and C15. During
sync time, both diodes in D7 conduct, shorting C15 to ground.
The sawtooth on C15 is thus clamped to ground at sync time. If the horizontal time base is in phase with the sync,
the sync pulse will occur when the sawtooth is passing through its ac axis and the net charge on C15 will be 0
(Figure 12-54). If the horizontal time base is lagging the sync, the sawtooth on C15 will be clamped to ground at a
point negative from the ac axis. This will result in a positive dc charge on C16 (Figure 12-54). This is the correct
polarity to cause the Horizontal Oscillator to speed up to correct the phase lag.
Likewise, if the horizontal time base is leading the sync, the sawtooth on C15 will be clamped at a point positive
from its ac axis, resulting in a negative charge on C15. This is the required polarity to slow the horizontal oscillator
(Figure 12-54). R33, C17, C16, and R32 comprise the Phase Detector Filter. The bandpass of this filter is chosen to
correct the Horizontal Oscillator phase without ringing or hunting.

12-66

REFERENCE
HORIZ.
SYNC

OSC ON FREQ
B 0 --l~~---'J~ NO CORRECTION
VOLTAGE DEVELOPED

__ OSC SLOW POS

o ---1'---~- CORRECTION VOLTAGE
D

o ---1k------I...,..- OSC FAST NEG

__ CORRECTION VOLTAGE
8E-0684

Figure 12-54 CRT Horizontal Oscillator Waveforms

12.5.2.4 Horizontal Oscillator - 06 is employed in a modified type of Hartley oscillator. The operating frequency
of this oscillator is sensitive to its base input voltage. This permits control by the output of the Phase Detector and
also by the setting of the horizontal hold control. The horizontal hold range is set by adjusting the core of L1.
12.5.2.5 Pulse Shaper and Horizontal Drive - 07 is used as a buffer stage between the Horizontal Oscillator and
the Horizontal Driver. It provides isolation for the Horizontal Oscillator as well as a low impedance driver for the
Horizontal Driver. R38 and C20 form a time constant which shapes the oscillator output to the required duty cycle
(approximately 50 percent), to drive the Horizontal Output circuitry. The Horizontal Driver stage, 08, operates as a
switch to drive the Horizontal Output transistor through T1. Because of the low impedance drive and fast switching
times furnished by 07, very little power is dissipated in 08. C21 and R42 provide damping to suppress ringing of the
primary to T1 when 08 goes into cutoff.
12.5.2.6 Horizontal Output - The secondary of T1 provides the required low drive impedance for 09. R44 and
C24 form a time constant for fast turn-off of the base of 09. 09 operates as a switch that, once each horizontal
period, connects the supply voltage across the parallel combination of the horizontal deflection yoke and the
primary of T2. The required sawtooth of the deflection current through the horizontal yoke is formed by the L-R
time constant of the yoke and output transformer primary. The Horizontal Retrace pulse charges C27 through D2 to
provide operating voltage for G2 of the CRT. Momentary transients at the collector of 09, should they occur, are
limited to the voltage on C27, since D2 will conduct if the collector voltage exceeds this value.
The damper diode, D1, conducts during the period between retrace and turn-on of 09. C28 is the retrace tuning
capacitor. C29 blocks dc from the deflection yoke. L3 is a magnetically-biased linearity coil that shapes deflection
current for optimum trace linearity. L4 is a series width control. C31 and R49, C42 and R68 are damping network
components for the linearity and width controls. C43D is charged through D5 developing the video supply voltage.
12.5.2.7 Vertical Oscillator Driver and Output - Sync from the collector of 05 is integrated by R26 and C35. 010
and 011 are connected as a regenerative switch. The series combination of C37 and C38 charges through R58 and
D3 until 010 turns on. This occurs when the emitter of 010 exceeds its base voltage and causes current to flow into
the base of 011, turning that device on. When 010 and 011 conduct, C37 and C38 are discharged to nearly O. 010
and 011 then shut off and the cycle repeats. The setting of the vertical hold control determines the repetition rate
of the charge and discharge of C37 and C38. The waveform generated is a positive-going ramp or sawtooth with a
fast retrace to O. D3 provides a small incremental voltage above ground to overcome the forward base-emitter drop
of the two following stages. 012 is an emitter follower used to transform the high impedance drive sawtooth to a
low impedance drive for 013.
T3 matches the collector of 013 to the vertical yoke. When 013 is cut off during Vertical Retrace, a high voltage
pulse is developed across the primary of T3. To limit this pulse to a safe value a varistor, R81, is connected across

12-67

the primary. R66 and C41 provide damping to shape the collector pulse so it may be used for retrace blanking. Since
the primary impedance of T3 decreases with current, the degree to which the primary shunts the reflected load
impedance varies with collector current. This would result in severe vertical non-linearity unless some compensation
is employed.
Resistors R60 and R59 couple the emitter voltage of 013 to the junction of C37 and C38. Since this path is
resistive, the waveform coupled back will be integrated into a parabola by C38. This results in a pre-distortion of the
drive sawtooth as shown in Figure 12-55. This is done to compensate for the non-linear charging of C37 and C38 and
the changing impedance of the primary of T3. An additional feedback path through R62 and C40 serves to optimize
the drive waveshape for best linearity.

I ~

PARABOLA

~ I FROM EMITTER

I OF Q24

I
I

EXISTING
VERTICAL SAWTOOTH
WITHOUT
I VERT PARABOLA ADDED

VV'I

~ VERTICAL SAWTOOTH ADDED
PARABOLA PULSE AND

TOGETHER, HENCE PRODUCING
THE REQUIRED VERT DRIVING SIGNAL
8E-0685

Figure 12-55 CRT Vertical Oscillator Waveforms
12.5.2.8 Retrace Blanking - Both Vertical and Horizontal Retrace blanking are provided by positive pulses applied
to the CRT cathode. The collector pulse from the Horizontal Output transistor is placed across R23 through R46.
The vertical collector voltage is differentiated by C30 to remove the sawtooth portion of the waveform. The
remaining pulse appears across R23. The mixed vertical and horizontal pulses on R23 are coupled to the CRT
cathode by Cl0.
12.5.2.9 Power Supply - The regulated power supply uses a series pass circuit. 016 is the series pass transistor,
014 is the driver, and 015 is the reference amplifier. The output voltage of the regulator appears at the emitter of
016 and is fed into a voltage divider consisting of R71, R74, and R73. The voltage appearing on the arm of
potentiometer R74 is used as an error input to 015. R74 is thus used as the output voltage adjustment.
Zener diode D13 establishes a reference voltage at the emitter of 015. R72 establishes the minimum bias current for
D13 to ensure proper Zener operation.
The voltage at the arm of R74 is compared with the reference voltage at D13 by 015. If the voltage at the base of
015 increases due to an increase in input voltage to the power supply for example, 015 conducts more current. This
decreases the current available to the base of 014, so 014 and 016 conduct less current, resulting in less voltage at
the emitter of 016. In this manner, input voltage changes are reduced by the overall gain of the regulator, which is
quite high. R79 reduces the power dissipation in 016 by carrying some of the supply current. This does not impair
regulation over the operating range of the power supply due to the large amount of gain available.

SECTION 5 MAINTENANCE
12.6 INTRODUCTION
VT8-E maintenance theory is directed to the module replacement level. The maintenance effort is divided into two
basic categories: preventive maintenance and corrective maintenance.

12-68

Preventive maintenance consists of routine periodic checks such as visual inspections, standard maintenance
procedures that involve cleaning and lubricating, and diagnostic tests that expose possible weakening conditions to
allow corrective action to be taken, eliminating the causative factor(s) of possible failures.
Corrective maintenance consists of isolating the fault or problem and making necessary adjustments and/or
replacements when a malfunction occurs. This involves the use of diagnostic routines prepared on paper tape and
designed to test the functional units of the system. The procedures and techniques of periodic checking aid in fault
isolation. Power requirements can be checked through the checkout procedures for power requirements contained in
Paragraph 12.2.2.
12.6.1

Equipment Required

Maintenance procedures for the VT8-E Video Display and Control require the standard equipment (or equivalent),
standard hand tools, and test probes listed in Table 12-10.

Table 12-10
Equipment Required
Equipment

Manufacturer

Designation

Multimeter
Oscilloscope
X10Probe
Recessed Tip
Diagnostic Self-Test
Routines

Triplett or Simpson
Tektronix
Tektronix
Tektronix

Model 630-NA or 620
Type 453
P6010
013-0090-00

12.6.2 Diagnostic Programming
The diagnostic routines, supplied as paper tapes, are used to test the various VT8-E functions and modules. A
complete description with instructions is provided with each tape.
12.6.3 Preventive Maintenance
Preventive maintenance consists of tasks performed periodically; its major purpose is to prevent failures caused by
minor damage or progressive deterioration due to aging. A preventive maintenance log book should be established
and necessary entries made according to a regular schedule. This data, compiled over an extended period of time, can
be very useful in anticipating possible component failures resulting in module replacement on a projected module or
component reliability basis.
Preventive maintenance tasks consist of mechanical and electrical checks. All maintenance schedules should be
established according to the environmental conditions at the particular installation site. Mechanical checks should be
performed as often as required to allow the fan and air filter to function efficiently. All other preventive
maintenance tasks should be performed on a regular schedule determined by reliability requirements. A
recommended schedule is every 600 operating hours or every four months, whichever occurs tirst.

12-69

12.6.3.1 Mechanical Checks - Use the following procedure to perform a mechanical check on the equipment.
Step

Procedure
Unplug the VTS-E main power and remove the cover.

Clean the exterior with a clean cloth moistened in a mild detergent. Only a very soft cloth
should be used to avoid scratching the protective screen used on the face of the CRT.

Clean the interior using a vacuum cleaner and ensure that the cabinet air exhaust vents are
thoroughly clean and unobstructed to promote adequate cooling. Should the vents
become obstructed, premature component failure may occur due to an increase in the
VTS-E internal temperature.

Inspect all wiring and cables for cuts, breaks, fraying, deterioration, kinks, strain, and
mechanical security. Tape, solder, or replace any defective wiring or cable covering.

Inspect the following for mechancial security: jacks, connectors, keyboard, etc. Tighten
or replace as required.

12.6.4 Troubleshooting
12.6.4.1 System Troubleshooting - Begin troubleshooting by repeating the operation in which the malfunction
was initially observed, using the same program or function. Thoroughly check the program for proper settings and
determine if the fault is definitely located in the VTS-E.
If the fault is isolated to the VTS-E, but cannot be immediately localized to a specific logic function, an effort
should be made to further isolate the fault to one of the VTS-E modules, e.g., keyboard, MS335 module, CRT
module, etc. Some helpful aids during functional analysis are the VTS-E engineering drawings, circuit schematics,
timing diagrams, and the applicable VTS-E diagnostic programs.
12.6.4.2 Module Troubleshooting - Once the fault has been isolated to a specific module, carefully remove the
suspected module. Inspect the receptacle for wear or damaged contacts. When the operability of the module is
verified, repair the faulty module or replace it with a module known to be operating properly and run the last
diagnostic program. If the system performs properly, return the system to an operating status and log an entry to
record all pertinent data concerning the fault or malfunction. When the individual defective part(s) within a module
is located and repaired or replaced, the module should be verified by a validation test.
12.6.4.3 VTS-E Assembly/Disassembly - The following procedures are provided for removal, replacement, and
installation of the various VT8-E modular components. Special and cautionary notes contained within the
procedures afford special attention and should be adhered to. Only procedures for the removal of the VT8-E
modular components are provided; for installation, the procedures should be performed in their reverse order.
12.6.4.3.1 VT8-E Module Boards - The MS335, MS336, or M8337 module boards should be inserted straight into
the OMNIBUS, never at an angle. When inserting a module board be certain it is fully seated in the OMNIBUS.
12.6.4.3.2 Cover Removal - The VT8-E cover is secured with four Phillips-head screws. Screw locations are
center-front, center-rear, and midway on the two sides. The screws are inserted up through the lower casting and
into four cover-retaining brackets. To remove the cover, remove the four retaining screws and lift the cover off.
NOTE
When the cover is removed, the 3-position interlock switch on
the left-hand side (viewing from the frond will go from the
fully depressed position (ON) to the middle position (OFF)
and must be pulled up to the third position (ON).

12-70

To install the cover, place the cover back on the lower casing, insert and tighten the four Phillips-head retaining
screws_ The interlock switch should be in the fully depressed (ON) position.
12.6.4.3_3 VTS-E Keyboards Removal - The VTS-E contains two keyboards, a large teletypewriter-type keyboard,
and a small B-key cursor control keyboard. The small keyboard is secured by four Phillips-head screws that are
inserted down through the four corners of the mounting board into the mounting bracket. The large keyboard is
secured by four Phillips-head screws that are inserted down through the keyboard mounting bracket. These four
screws should not be confused with the smaller and brighter Phillips-head screws that secure the keyboard to the
keyboard logic board. The smaller, brighter screws should not be removed.
Use the following procedure to remove the small keyboard:
Step

Procedure
Disconnect the ribbon cable from the small keyboard input connector.

Remove the four Phill ips-head retaining screws from the four corners of the small
keyboard mounting board.

Slide the keyboard to the left and lift it out.

Use the following procedure to remove the large keyboard:
Step

Procedure
Disconnect the 44-pin Berg connector from the keyboard output connector.

Remove the four, larger keyboard Phillips-head retaining screws from the keyboard
mounting bracket and remove the keyboard

12.6.4.3.4 CRT Removal - The CRT is secured to the VTS-E lower casting with four Phillips-head screws that are
inserted through the bottom of the VTS-E and into the bottom four corners of the CRT chassis. Use the following
procedure to remove the CRT:
CAUTION
Protective goggles and heavy gloves should be worn when
removing and/or carrying the CRT_ Never grasp the CRT by
the neck, nor chip or scratch any part of the tube.
Step

Procedure
Press the interlock switch down to ensure main power is off.

Viewing the VTB-E from the front, locate (15-pin and 12-pin) Mate-N-Lok connectors P1
and P2 on the lower right-hand side of the CRT chassis and disconnect both connectors.

Locate and remove the four Phillips-head retaining screws on the bottom of the VTB-E,
used to secure the CRT chassis to the lower casting.
NOTE
Upon removal, the CRT should be placed face-down on a soft clean
cloth or pad. Under no circumstances should the CRT be grasped by
the neck

Lift the CRT out of the lower casing.
12-71

APPENDIX A
ROM PATTERN TABLES

Table A·'
ROM Pattern Table
(EVEN ROM)
Decimal
Location

Octal
Location

Binary
Data

Decimal
Location

Octal
Location

Binary
Data

0
1
2
3

000
001
002
003

0000
0111
1000
1011

24
25
26
27

030
031
032
033

0000
1111
1000
1000

4
5
6
7

004
005
006
007

1010
1011
1000
0111

28
29
30
31

034
035
036
037

1111
1000
1000
1000

8
9
10
11

010
011
012
013

0000
1111
1000
1000

32
33
34
35

040
041
042
043

0000
1000
1000
1000

12
13
14
15

014
015
016
017

1111
1000
1000
1111

36
37
38
39

044
045
046
047

1111
1000
1000
1000

16
17
18
19

020
021
022
023

0000
1110
1001
1000

40
41
42
43

050
051
052
053

0000
0011
0001
0001

20
21
22
23

024
025
026
027

1000
1000
1001
1110

44
45
46
47

054
055
056
057

0001
1001
1001
0110

A·l

Table A-1 (Cont)
ROM Pattern Table
(EVEN ROM)
Decimal
Location

Octal
Location

Binary
Data

Decimal
Location

Octal
Location

Binary
Data

48
49
50
51

060
061
062
063

0000
1000
1000
1000

84
85
86
87

124
125
126
127

0010
0010
0010
0010

52
53
54
55

064
065
066
067

1000
1000
1000
1111

88
89
90
91

130
131
132
133

0000
1000
1000
1000

56
57
58
59

070
071
072
073

0000
1000
1000
1100

92
93
94
95

134
135
136
137

1000
1000
0101
0010

60
61
62
63

074
075
076
077

1010
1001
1000
1000

96
97
98
99

140
141
142
143

0000
1000
1000
0101

64
65
66
67

100
101
102
103

0000
1111
1000
1000

100
101
102
103

144
145
146
147

0010
0101
1000
1000

68
69
70
71

104
105
106
107

1111
1000
1000
1000

104
105
106
107

150
151
152
153

0000
1111
0000
0001

72
73
74
75

110
111
112
113

0000
1111
1000
1000

108
109
110
111

154
155
156
157

0010
0100
1000
1111

76
77
78
79

114
115
116
117

1111
1001
1000
1000

112
113
114
115

160
161
162
163

0000
0000
1000
0100

80
81
82
83

120
121
122
123

0000
1111
0010
0010

116
117
118
119

164
165
166
167

0010
0001
0000
0000

A-2

Table A-1 (Cont)
ROM Pattern Table
(EVEN ROM)
Decimal
Location

Octal
Location

Binary
Data

Decimal
Location

Octal
Location

Binary
Data

120
121
122
123

170
171
172
173

0000
0111
1000
0000

156
157
158
159

234
235
236
237

0100
1010
1001
0110

124
125
126
127

174
175
176
177

0000
0000
0000
0000

160
161
162
163

240
241
242
243

0000
0001
0010
0100

128
129
130
131

200
201
202
203

0000
0000
0000
0000

164
165
166
167

244
245
246
247

0100
0100
0010
0001

132
133
134
135

204
205
206
207

0000
0000
0000
0000

168
169
170
171

250
251
252
253

0000
0010
1010
0111

136
137
138
139

210
211
212
213

0000
0101
0101
0101

172
173
174
175

254
255
256
257

1101
0111
1010
0010

140
141
142
143

214
215
216
217

0000
0000
0000
0000

176
177
178
179

260
261
262
263

0000
0000
0000
0000

144
145
146
147

220
221
222
223

0000
0010
0111
1000

180
181
182
183

264
265
266
267

0000
0010
0010
0100

148
149
150
151

224
225
226
227

0111
0000
1111
0010

184
185
186
187

270
271
272
273

0000
0000
0000
0000

152
153
154
155

230
231
232
233

0000
0100
1010
1010

188
189
190
191

274
275
276
277

0000
0000
0000
0010

A-3

Table A-l (Cont)
ROM Pattern Table
(EVEN ROM)
Decimal
Location

Octal
Location

Binary
Data

Decimal
Location

Octal
Location

Binary
Data

192
193
194
195

300
301
302
303

0000
0111
1000
1001

224
225
226
227

340
341
342
343

0000
0111
1000
1000

196
197
198
199

304
305
306
307

1010
1100
1000
0111

228
229
230
231

344
345
346
347

0111
1000
1000
0111

200
201
202
203

310
311
312
313

0000
0111
1000
0000

232
233
234
235

350
351
352
353

0000
0000
0000
0010

204
205
206
207

314
315
316
317

0011
0100
1000
1111

236
237
238
239

354
355
356
357

0000
0010
0000
0000

208
209
210
211

320
321
322
323

0000
0001
0011
0101

240
241
242
243

360
361
362
363

0000
0001
0010
0100

212
213
214
215

324
325
326
327

1001
1111
0001
0001

244
245
246
247

364
365
366
367

1000
0100
0010
0001

216
217
218
219

330
331
332
333

0000
0011
0100
1000

248
249
250
251

370
371
372
373

0000
0100
0010
0001

220
221
222
223

334
335
336
337

1111
1000
1000
0111

252
253
254
255

374
375
376
377

0000
0001
0010
0100

A-4

Table A-2
ROM Pattern Table
(ODD ROM)
Decimal
Location

Octal
Location

Binary
Data

Decimal
Location

Octal
Location

Binary
Data

0
1
2
3

000
001
002
003

0000
0010
0101
1000

36
37
38
39

044
045
046
047

0010
0010
0010
0111

4
5
6
7

004
005
006
007

1000
1111
1000
1000

40
41
42
43

050
051
052
053

0000
1000
1001
1010

8
9
10
11

010
011
012
013

0000
0111
1000
1000

44
45
46
47

054
055
056
057

1100
1010
1001
1000

12
13
14
15

014
015
016
017

1000
1000
1000
0111

48
49
50
51

060
061
062
063

0000
1000
1101
1010

16
17
18
19

020
021
022
023

0000
1111
1000
1000

52
53
54
55

064
065
066
067

1010
1000
1000
1000

20
21
22
23

024
025
026
027

1111
1000
1000
1111

56
57
58
59

070
071
072
073

0000
0111
1000
1000

24
25
26
27

030
031
032
033

0000
0111
1000
1000

60
61
62
63

074
075
076
077

1000
1000
1000
0111

28
29
30
31

034
035
036
037

1000
1011
1000
0111

64
65
66
67

100
101
102
103

0000
0111
1000
1000

32
33
34
35

040
041
042
043

0000
0111
0010
0010

68
69
70
71

104
105
106
107

1000
1010
1001
0110

A-5

Table A-2 (Cont)
ROM Pattern Table
(ODD ROM)
Decimal
Location

Octal
Location

Binary
Data

Decimal
Location

Octal
Location

Binary
Data

72
73
74
75

110
111
112
113

0000
0111
1000
1000

108
109
110
111

154
155
156
157

1100
1100
1100
1111

76
78
79

114
115
116
117

0111
0000
1000
0111

112
113
114
115

160
161
162
163

0000
1111
0001
0001

80
81
82
83

120
121
122
123

0000
1000
1000
1000

116
117
118
119

164
165
166
167

0001
0001
0001
1111

84
85
86
87

124
125
126
127

1000
1000
1000
0111

120
121
122
123

170
171
172
173

0000
0000
0000
0000

88
89
90
91

130
131
132
133

0000
1000
1000
1000

124
125
126
127

174
175
176
177

0000
0000
0000
1111

92
93
94
95

134
135
136
137

1010
1010
1101
1000

128
129
130
131

200
201
202
203

0000
0010
0010
0010

96
97
98
99

140
141
142
143

0000
1000
1000
0101

132
133
134
135

204
205
206
207

0010
0010
0000
0010

100
101
102
103

144
145
146
147

0010
0010
0010
0010

136
137
138
139

210
211
212
213

0000
0101
0101
1111

104
l05
106
107

150
151
152
153

0000
1111
1100
1100

140
141
142
143

214
215
216
217

0101
1111
0101
0101

A-6

Table A·2 (Cont)
ROM Pattern Table
(ODD ROM)
Decimal
Location

Octal
Location

Binary
Data

Decimal
Location

Octal
Location

Binary
Data

144
145
146
147

220
221
222
223

0000
1100
1100
0001

180
181
182
183

264
265
266
267

1111
0000
0000
0000

148
149
150
151

224
225
226
227

0010
0100
1001
0001

184
185
186
187

270
271
272
273

0000
0000
0000
0001

152
153
154
155

230
231
232
233

0000
0010
0010
0010

188
189
190
191

274
275
276
277

0010
0100
1000
0000

156
157
158
159

234
235
236
237

0000
0000
0000
0000

192
193
194
195

300
301
302
303

0000
0010
0110
0010

160
161
162
163

240
241
242
243

0000
0100
0010
0001

196
197
198
199

304
305
306
307

0010
0010
0010
0111

164
165
166
167

244
245
246
247

0001
0001
0010
0100

200
201
202
203

310
311
312
313

0000
1111
0000
0001

168
169
170
171

250
251
252
253

0000
0000
0010
0010

204
205
206
207

314
315
316
317

0011
0000
1000
0111

172
173
174
175

254
255
256
257

1111
0010
0010
0000

208
209
210
211

320
321
322
323

0000
1111
1000
1111

176
177
178
179

260
261
262
263

0000
0000
0000
0000

212
213
214
215

324
325
326
327

0000
0000
1000
0111

A·7

Table A·2 (Cont)
ROM Pattern Table
(ODD ROM)
Decimal
Location

Octal
Location

Binary
Data

Decimal
Location

Octal
Location

Binary
Data

216
217
218
219

330
331
332
333

0000
1111
0000
0001

236
237
238
239

354
355
356
357

0000
0010
0010
0100

220
221
222
223

334
335
336
337

0010
0100
0100
0100

240
241
242
243

360
361
362
363

0000
0000
0000
1111

224
225
226
227

340
341
342
343

0000
0111
1000
1000

244
245
246
247

364
365
366
367

0000
1111
0000
0000

228
229
230
231

344
345
346
347

0111
0000
0001
1110

248
249
250
251

370
371
372
373

0000
0111
1000
0001

232
233
234
235

350
351
352
353

0000
0000
0000
0010

252
253
254
255

374
375
376
377

0010
0010
0000
0010

A·8

Table A-3
ROM Pattern Table
(XTRA ROM)
Decimal
Location

Octal
Location

Binary
Data

Decimal
Location

Octal
Location

Binary
Data

0
1
2
3

000
001
002
003

0000
0000
0010
0011

36
37
38
39

044
045
046
047

0010
0010
0010
0010

4
5
6
7

004
005
006
007

0011
0011
0001
0011

40
41
42
43

050
051
052
053

0000
0011
0000
0000

8
9
10
11

010
011
012
013

0000
0000
0011
0010

44
45
46
47

054
055
056
057

0000
0000
0000
0001

12
13
14
15

014
015
016
017

0000
0010
0011
0000

48
49
50
51

060
061
062
063

0000
0001
0001
0001

16
17
18
19

020
021
022
023

0000
0001
0000
0010

52
53
54
55

064
065
066
067

0001
0001
0001
0011

20
21
22
23

024
025
026
027

0010
0010
0000
0001

56
57
58
59

070
071
072
073

0000
0010
0011
0011

24
25
26
27

030
031
032
033

0000
0010
0001
0000

60
61
62
63

074
075
076
077

0011
0011
0011
0010

28
29
30
31

034
035
036
037

0000
0001
0001
0000

64
65
66
67

100
101
102
103

0000
0000
0011
0011

32
33
34
35

040
041
042
043

0000
0010
0010
0010

68
69
70
71

104
105
106
107

0001
0001
0000
0001

A·9

.•.

Table A-3 (Cont)
ROM Pattern Table
(XTRA ROM)
Decimal
Location

Octal
Location

Binary
Data

Decimal
Location

Octal
Location

Binary
Data

72
73
74
75

110
111
112
113

0000
0000
0011
0010

108
109
110
111

154
155
156
157

0000
0000
0000
0011

76
77
78
79

114
115
116
117

0000
0001
0011
0010

112
113
114
115

160
161
162
163

0000
0001
0001
0001

80
81
82
83

120
121
122
123

0000
0011
0001
0001

116
117
118
119

164
165
166
167

0001
0001
0011
0001

84
85
86
87

124
125
126
127

0001
0001
0001
0000

120
121
122
123

170
171
172
173

0000
0000
0010
0000

88
89
90
91

130
131
132
133

0000
0011
0011
0011

124
125
126
127

174
175
176
177

0000
0000
0000
0001

92
93
94
95

134
135
136
137

0011
0011
0001
0001

128
129
130
131

200
201
202
203

0000
0000
0000
0000

96
97
98
99

140
141
142
143

0000
0011
0011
0000

132
133
134
135

204
205
206
207

0000
0000
0000
0000

100
101
102
103

144
145
146
147

0000
0000
0010
0010

136
137
138
139

210
211
212
213

0000
0000
0000
0001

104
105
106
107

150
151
152
153

0000
0011
0010
0000

140
141
142
143

214
215
216
217

0000
0001
0000
0000

A-l0

Table A-3 (Cont)
ROM Pattern Table
(XTRA ROM)
Decimal
Location

Octal
Location

Binary
Data

Decimal
Location

Octal
Location

Binary
Data

180
181
182
183

264
265
266
267

0001
0000
0000
0000

144
145
146
147

220
221
222
223

0000
0000
0011
0000

184
185
186
187

270
271
272
273

0000
0000
0001
0000

148
149
150
151

224
225
226
227

0000
0010
0001
0001

188
1a9
190
191

274
275
276
277

0000
0000
0000
0000

152
153
154
155

230
231
232
233

0000
0000
0000
0000

192
193
194
195

300
301
302
303

0000
0000
0010
0010

156
157
158
159

234
235
236
237

0000
0010
0000
0010

196
197
198
199

304
305
306
307

0010
0010
0010
0000

160
161
162
163

240
241
242
243

0000
0000
0000
0000

200
201
202
203

310
311
312
313

0000
0001
0011
0010

164
165
166
167

244
245
246
247

0000
0000
0000
0000

204
205
206
207

314
315
316
317

0000
0001
0001
0010

168
169
170
171

250
251
252
253

0000
0000
0010
0000

208
209
210
211

320
321
322
323

0000
0001
0000
0000

172
173
174
175

254
255
256
257

0011
0000
0010
0000

212
213
214
215

324
325
326
327

0001
0011
0001
0000

176
177
178
179

260
261
262
2.63

0000
0000
0000
0000

A-11

Table A·3 (Cont)
ROM Pattern Table
(XTRA ROM)
Decimal
Location

Octal
Location

Binary
Data

Decimal
Location

Octal
Location

Binary
Data

216
218
219

330
331
332
333

0000
0011
0001
0000

236
237
238
239

354
355
356
357

0000
0000
0000
0000

220
221
222
223

334
335
336
337

0000
0010
0010
0000

240
241
242
243

360
361
362
363

0000
0000
0000
0001

224
225
226
227

340
341
342
343

0000
0000
0011
0011

244
245
246
247

364
365
366
367

0000
0001
0000
0000

228
229
230
231

344
345
346
347

0001
0011
0010
0000

248
249
250
251

370
371
372
373

0000
0000
0001
0000

232
233
234
235

350
351
352
353

0000
0000
0000
0000

252
253
254
255

374
375
376
377

0010
0000
0000
0000

2.17

A-12

PDP-8/E MAINTENANCE MANUAL
VOLUME III
DEC-8E-HMM3A-C-D

READER'S COMMENTS

Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of
our publications.
What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, well
written, etc.? Is it easy to use?

. What features are most useful? ________________________________

What faults do you find with the manual? _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Does this manual satisfy the need you think it was intended to satisfy? ________________
Does it satisfy your needs?

Why?

Would you please indicate any factual errors you have found.

Please describe your position.
Name ___________________

Organization _________________

Street _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Department

City _ _ _ _ _ _ _ _ _ __

State

Zip or Country _ _ _ _ _ __

-FoldHere -

- - - - - - Do Not Tear-Fold Here and Staple -

-- -- -

FIRST CLASS
PERMIT NO. 33
MAYNARD, MASS.
BUSINESS REPLY MAIL
NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES
Postage will be paid by:

Digital Equipment Corporation
Technical Documentation Department
146 Main Street
Maynard, Massachusetts 01754

DIGITAL EQUIPMENT CORPORATION

~ ~

WORLD-WII;>E SALES AND SERVICE

MAIN OFFICE AND PLANT
146 M a in S treet. Maynard, MasS8chusetts , U.S .A. 01754· Telephon e: from Metropo litan Boston ' 646-8600 · Elsewhere: (6 17)-897-5'"

TWX : 710-347-0212 Cable: DIGITAL MAYN Tele)(: 9·H457

UNITED STATES
NORTHEAST

MID-ATLANTIC -

REGIONAL OFFICE
.
275 Wyman Street. Wa ltham . Massachusetts 02154
Te lephone : (617}-890-0320/0330
TWX : 710-324-6919

KNOXV ILLE

WALTHAM

SOUTHEAST (conI.)

15 Lunda St reet, W altham , Massachusett s 02154

Telephone: (617)-891- 1030
T\NX , 710-324-6919
CAMBRIDGE/BOSTON
899 Mai n S tre el. Cambridge . Massachuset:s 02139
Telephone: (617)·49 1·6130
TWX. 710-320-1167
ROCHESTER
130 Alie ns C reek Road. Rochester. New York 146 18

Te lepho ne: (716).461-1700
CONNECTICUT

TWX- 710-253-3078

REGIONAL OFFICE

Te lephone: (312)-498-2500

TWX : 91 0-686-0655

WEST LOS ANGELES

MID -ATLANTIC -

US Ro ute 1, Princeto n. N ew Jersey 08540
Telephone, (609H52·2940
TWX, 5 10-685·2336

ANN ARBOR
2:'K1 Huron View Boulevard . Ann Ar bor , Michiga n 48 103

NEW YORK

Telepho ne , (313)-76 1-11 50

NEW JERSEY
1259 Rou te 46. Parsippany. New Jersey 07054
Te lephone (201)-335-3300
TWX 710 -987·8319

PRINCETON
U _S. Aou te 1
Princeton . New Jersey 08540
Tele phone; (609) 452-2940
TWX 510-685-2338

LONG ISLAND
1 Huntington Quadrangle
SUite lS07 Huntington Station, New York 11746
Telephone, (5 16) -694-4131. (212)-895·8095

ANAHEIM
BO I E. BaH Ro ad , A nahe im. Califo rn ia 92805
TWX; 910-591-1189
Telephone : (714}-776 -6932/873J

Plttsbur9 h , Pe nnsy lvania 15235
Te lep hone: (412)-243·9404
TWX , 710-797-3657

CHICAGO

95 Cedar Lane , Englewood, New Jersey 07631
Teleph one . (201) -87 1-4984. (2 12)-59 4-6955. (212)·736·0447
TWX. 710-99 1·9721

310 S o que l Way . Sunnyvale . Ca lifornia 94086
Teleph o ne : (408)-735-9200

PITTSBURGH
400 Penn Cen ter Boule vard

1850 Fr o ntage Roa d. Nort hbro ok . il linois 60062
Tel epho ne : (3 12)-498-2500
TWX: 91 0-686-0655

SOUTHEAST

3100 Rldg e lake D rive , Suite 108
Met airie , louPsl ana 700Cl2
Telephone 50-4·837-0257

WEST

CENTRAL
REGIONAL OFFICE:

1850 Frontage Roa d. Northbrook , IllinOIS 60062

240 Pomeroy Ave Meridt·n. Co nn 06450
Telephone (203) 237-8441/7466
TWX . 710·4610054

REGIONAL OFFICE '

CENTRAL (cont)
NEW ORLEANS

63 11 KIngston Pike , SuIte 21E
K noxville, Tennessee 37919
Te le phone : (6 15)-588-6571
TWX· 810-583-0123

TWX : 81 0-223-6053

INDIANAPOliS
21 Beachway D riv e - Su ite G
Indianapolis. Ind iana 46224
Telephone: {317)-243-834\
TWX 810-34 1-3436

MINNEAPOLIS
Sui te 111. 8030 Cedar Ave nue South,
Minne8 po lr s. Mi nnesota 55420
Te lephone . (6 12)·854·6562-3·4-5
TWX: 9 10-576-28 18

i510 C Oiner Avenue . Los Angeles, Californa 90025
Telephone : (213)-479-3791/4318
TWX: 910-342-6999

SAN DIEGO
3444 Hancoc k Stre et
San D iego, C ali f orni a 92110
Telephone : (7 14)-298-0591, 0593

TWX, 910-335-1230

SAN FRANCISCO

1400 Terra Bella
Mountain View, Ca lifo rnIa 94040
Te lephone: (415)-964-6200
TWX: 910-373-1266

PALO ALTO
560 San Antonio Rd. Palo Al to. Ca ltfornia 94306

Te lephone, (415)-969-6200

TWX: 910-373·1266

OAKLAND
7850 Edgewater Dri v e
Oakland. Ca lifornia 94621
Telephone (415)-635-5453/7830

TWX 910-366-7238

ALBUQUERQUE

CLEVELAND
Park Hil i Bldg 35104 Euclid Ave
Wil'OlJghby, Ohio 44094
T~ l ephone' (216)-946·8484
TWX 810- 427·2608

6))3 IndIan S chool Road, N.E.
Albuquerque, N ,M 87 110
Telephone : (505)·296-5411/5428

DENVER

ST. LOUIS

TWX : 910-989-06 14

Suite 110, 115 Progress Pky, Maryland Hel9hts,
MiSSOUri 63043
Telephone (314)·878-4310
TWX: 910·764·0831

23CS South Color ado B lvd Sui te #5
DenVEr, Colorado 80222
Telephone · (303)-757-3332/758- 1656/758-1659
TWX: 910-931-2650

Executive Budding
6811 Kenilworth Ave .. Riverdale. Mar,.l<1nd '084D
Telephone- (301}-779-16ooI752-8797
TWX ';'1 0 626 CJ662

DA YTON

SEATTLE

DURHAM/CHAPEL HILL

MILWAUKEE

PHILADELPHIA
Station Square Three. Paoli, Pennsylvanpa 19301
Telephone; (215)-647--4900/4410
Telex, 510-6688395

WASHINGTON

3101 K{>ttf!rll'1r~ Blvd. Dilylon, Ohio 45439
Tf>lephone ( ~13)-299-7377
TWX 810-459- 1676

1521 130th N_ E., Bellevue. Washlngto'l MOOS
Telephone: (206)-454-4058/455-5404
TW?,' 910-443-2306

SA LT LAKE CITY

2704 Chapel Hill Boulevard
D:Jfham. N"rlh C<lrolina27i07
Telephone' (919)-489-3347
TWX 510-927·0912

8531 W Capitol Drive, Milwaukee. Wisconsin 53222
Telephone' (414)463 9110
TWX: 910-262-1199

431 S(Juth :1rd East. Salt LAke City, Ut,.h e41l1
Telephone (801)-328·9838
Tv',X 910925-5534

ORLANDO

DALLAS

4358 East Broadway Road
Phoenix, Arizona 85040
Telephone: (602) 268-3486

PHOENIX

Suite 130. 700 1 Lake Ellenor Drive , Orlrmdo, Florida 32809 o~ "i North S \,'mmons Freeway
Dflllas, Texas 7S;:>47
Telephone: (Xl5)-851-4450
TWX 81M,50-D180
Telephone (214~ 638 4380

nvx 910-861 -4000

ATLANTA

2815 Clearview Place. Suite 100.
Atlanta. Georgia 30340
Telephone: (404)-4::-1-3734 13735':3736

HOUSTON
TWX

TWX; 910-950-4891

PORTLAND
SUite 168
5319 SW Canyon Court. Portland. Ore. 97221
Telephone: (503) 297-3761/3765

810-757-4223

l417 ~',t. m S're',1 Sllile A H( -I(>n
exas 77002
Tf!1 ph)ne (713)-5'4-2961
TWX 910-881 -16'>1

I r: .rope

Digita l EquIpment Aktiebolag

DigItal EquIpment Corporation ltd .

STOCKHOLM
Vretcovagen 2, S-171 54 Solna Sweden

AUCKLAND

INTERNATIONAL
EUROPEAN HEADQUARTERS
Digltill Equ ~m~ ,t CUrf) r, '
81 Route de t'AI'c
1211 Genf'va 26
Telephon
42 ~9 'iO

n m,

2 fl83

FRANCE
EquIpment Digital S _AR,L

SWEDEN

NEW ZEA LAND

Telephone: 98 13 90
Telex, 17050
CDbie Digital Stockholm

0''11\ , i Eqll r pm,~nt

327 Hue de C harenton, 75 Paris 12 BolE, Frar,ce
Telephone : 344-76·07
Telex, :;:'339

OSLO

10 rue Auguste Ravler, F-38 Grenoble France
Telephone: (76) 87 87 32
Telex 3? 882 F (Code 212)

GERMANY

DENMARK

D igital EqUipment GmbH

DigItal Equipment Corporation

MUNICH

a Muenchen 13, Wallenstelnplatz 2
Telephone: 0011-35031

Telex

150 ROSll.nlond Street, Carleton Place, Ontario
Telephone (613) -257-2615
TWX: 610-561-1651
16643

COPENHAGEN
Vesterbrogade 140. 1620 Copenhagen V

524-225

SWITZERLAND

COLOGNE

Digital Equrpment Cor poration SA
838-2269

FRANKFURT
6078 Neu-I!;p.nburg 2
Am ForSlhaus Gravenbruch 5-7
Telephone· 06102-5526
Telex 41 -76·82

HANNOVER
3 Hannover , Podblelsklstrasse 102
Telephone: 0511-69·7(}'95
Te lex : 922-952

GENEVA
r' pI< :le I Aim
1;"1
,·r
T Ie h

'6, Slo"tnrland
4? 79 ~
Tel, x nlJd

, ZURICH
hlE"f tr[lsse 21
CH16 Zunch, Swil7.('(I~nd
Telt' ohor 01 '60 3<; 66
T"le~ ')1.)59
~I

ITALY
Digital Equ ipment S.p_A.

AUSTRIA
Dig ital Equipment Corporation

D'g,l[ll Equipment of Can[lda. ltd

CANADIAN HEADQUARTERS

oJ 'IT " "
'e
V'la ldenmarthranesgate 84-B-86
Osl 1 Nn"
~"I~
,371'1
37 O? 30
Tt'le'

GRENOBLE

5 Koeln, Blsmar ckstrasse 7,
Telephone: 022 1-522181
Tel€"
Telegram: Flip Chip Koeln

CANADA

NORWAY

-PARIS

Ges m h H

VIENNA
Marlahllferstrasse 136, 1150 Vienna 15, AUBtria
Telephone: 85 51 86

Hilton Hous ,430 Queen Street, Box 2471 A.
Auckland, New Zealand
Telephl'ne: 75-533

MILAN
Cor~ 0

Gilnbaldi 49 , 20121 Milano, Italy
Telerh(lne 8n 748 694 394
Te lex 33615

SPAIN

OTTAWA
120 HolI, nd Street. Ottawa 3 , OntariO K1Y OX7
rpleptlOne (613) 7252193
TWX 610,S62·8907

TORONTO

MONTREAL
9675 Cole de Llesse Road
Dorval. QU<'bec. Canada 760
Telephone 514636-9393
TWX
553 1 - 103 Street
Edmonton, Alberta, Canll.da
Telephone' [4D:'lj.434-9333
TWX

ARGENTINA
BUENOS AIRES
CI'')f;in SA
V,rrey droj P,nn 4071, Buenos Aires
Tetllphone: <;2·3185
Telex 012·2284

MADRID

VENEZUELA

Alalo Ingenieros S.A., Enrigue Larreta 12, MadrId 16
Telephone: 215 ~"43 I Telex: 27249

C ARACAS

BARCELONA

READING

AtdlO Ingenleros S,A., Ganduxer 76, Barcelona 6
Telephone 221 44 66
Digital Equipment Corporation ltd,

The Even ing Post Budding , Tessa Road
Reading. Berks

BIRMINGHAM
29/31, B irmmgham Road, Suit n Coldf Id, W<lrv,lI'ks
Telephone (0044) ' I :'is'; 5~OI
Te ll"
i3i 060

MANCHESTER
13 Upp..r Pr.e clnct, Walkden. Manchester M28 SAZ
TelephorlP. 061 -790-8411
Tel"x' 66g666

LONDON
Bilton House, Uxbridge Road. Ealmg, London W.5.
Telephone: 01-579-2334
Telex : 2237 1

EDINBURGH
Shie l House, Crolgshtll. livingston,
West Lothian, Scotl and
Telephone: 32705 / Telex: 7271 13

NETHERLANDS
THE HAGUE
Di gital Equipment N.V
Sir Winston Chlirchi lilaan 370
Rijswijk/The Hague, N~the r lands
Te lephone : 070-995-160
Telex: 32533

BELGIUM
BRUSSELS
D i gita l Eq uipment NV,/S ,A.
108 Ru e D'Arl on
1040 Brussels, Belg ium
T e lephone : 02-139256
Tel ex: 25297

610-831-2248

VA NCOUVER
['"\ gltal Equlp:n"nt of Canada. ltd
"'10 West l?tl1 AvcnlJe
VancouvN 9, British Columbiil. Car>ada
Telephone' (604) -736-5616
TWX· 610·929-2006

Digital Equipment Co. Ltd
Arkwright Road. Reading, Berks
Telephone: 0734-583555
Telex 84327

610422·41 24

EDMONTON

UNITED KINGDOM
U .K , HEADQUARTERS

•

':'l.O L lkesh ,ra RO(ld East. Port Cre3,t. Ontario
Telephone' (416) -274-1241
TWX: 610- 492-4306

C oasrn S.A. (Sales only)
Apartado 50939
Salana Grande No 1 Caracas
,-eleph
72- )637
Cabl!! INSTRUVEN

CHILE
SANTIAGO

AUSTRALIA
Digital Equipment Australia Ply. Ud.

Cossin Chile Ltda, (sales only)
Cll.silla 145<l8, Correo IS, Santia90
Tf'leph"ne. 396713
Cal;le COACHIL

SYDNEY
PO Box 491, Crows Nest
N SW. Australia 3065
Telephone: 439-2066
Telex' AA20740
Cable, Dlgttal. Sydney

MELBOURNE
60 Park 8treet. South Melbourne. V ictoria . 3205
Telephone: 696--142
Telex : AA40616

PERTH
643 Murray Street
West Perth, Western Australia 6005
-I c lephone : 214-993
Telex, AA92140

BRISBANE
139 Merivale Street. South Brisbane
QueenSland. Austra lic. 410 1
Telephone 444-047
Telex : AA40616

I APAN
TOKYO
Rikei Trading Coo, Ltd (sales o nly)
KOHl\o·Kalkan Bldg
No, 18-14. Nishishimbashl H;home
Mlnato·Ku. Tokyo. Japan
Telephone 5915246
Te lex : 781-4208
Opgital Equipment Corporat Ion International
K wa Building No_ 17, Second Floor
/- 7 Nlshp-AmblJ 1-Chome
Mrnato-Ku, Tokyo. Japan
Telephone 404-5894'6
Telex: TK-6428

PHILIPPINES
Stan ford Computer Corpor ation
P,O, Box 1608
416 Dasmannas SI., Manila
Te lephone : 49-68-96
Telex, 742-0352

INDIA
ADELAIDE
6 Montr ose Avenue
Norwood . South Australia 5067
Telephone: 631-339
Telex : AA82825

H.S. Sonawa la M g DIrect or (Sales On l y)
H IND ITRON SERVI CES PU T LTD
69/ A N epean Sea Road
Bombay , Ind ia