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DEC-8E-HMM2A-D-D

January 1974

232 pages

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Document:	PDP-8e Maintenance Manual Volume 2 Internal Bus Options
Order Number:	DEC-8E-HMM2A-D-D
Revision:
Pages:	232
Original Filename:	http://bitsavers.org/pdf/dec/pdp8/pdp8e/DEC-8E-HMM2A-D-D_PDP-8e_Maintenance_Manual_Volume_2_Internal_Bus_Options_Jan74.pdf

OCR Text

internal bus options
maintenance manual
volume 2

•

~ .~
b- .

'----------~

MAINTENANCE MANUAL
VOLUME 2

For additional copies order No. DEC-8E-HMM2A-D-D from Direct Mail, Digital
Equipment Corporation, Maynard, Massachusetts 01754

Price:

$25.00

digital equipment corporation· maynard. massachusetts

1 st Edition, May 1972
2nd Printing (Rev), February 1973
3rd Printing (Rev), August 1973
4th Printing (Rev), January 1974

The material in this manual is for informational purposes and is subject to change without
notice.
Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTE R LAB

TABLE OF CONTENTS SUMMARY

Part 1-

Extended Arithmetic Option
KE8-E Extended Arithmetic Option
Chapter 1

Part 2-

Memory Equipment Options
C~p~r1

MR~F1KPROM

Chapter 2
Chapter 3
Chapter 4
Chapter 5

KM8-E Memory Extension and Timeshare
MR8-E Read Only Memory
MI8-E Hardware Bootstrap Loader
MP8-E Memory Parity

Part 3-

Real Time Clock Options
Chapter 1
Real Time Clock Options

Part 4-

Power Fail Option
KP8-E Power Fail and Auto-Restart
Chapter 1

Part 5-

I nterprocessor Options
Chapter 1
DB8-E Interprocessor Buffer

Part 6-

External Bus I nterface Control Options
KA8-E Positive I/O Bus Interface
Chapter 1
Chapter 2
KD8-E Data Break Interface

CONTENTS
Page
PART 1 EXTENDED ARITHMETIC ELEMENT OPTION
CHAPTER 1 KES-E EXTENDED ARITHMETIC ELEMENT
Section 1 Introduction

1.1

General Description

1.2
1.3

Software

1-1
1-1
1-1

Companion Documents
Section 2 Installation

1.4
1.5

Installation

1-3
1-3

Checkout

Section 3 System Description

1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
1.14
1.15
1.16
1.17
1.18

Step Counter Loading Operation (Figure 1-3)

Double-Precision Store (DST) (Figure 1-10)

1-4
1-7
1-7
1-7
1-9
1-9
1-10
1-10
1-11

Double-Precision Add (DAD) (Figure 1-11)

1-11

Subtract AC from MQ (SAM) (Figure 1-12)

1-13
1-13
1-14

Step Counter to Accumulator Loading Operation (Figure 1-4)
The Shift Left Operation
Right Shift Operations (Figure 1-5)
Normalize Instruction (Figure 1-6)
Double-Precision Skip if Zero (DPSZ) (Figure 1-7)
Double-Precision Complement (DCM) (Figure 1-8)
Double-Precision Increment (DPIC) (Figure 1-9)

Multiply Instruction (MUY) (Figure 1-13)
Divide Instruction (DVI) (Figure 1-15)
Section 4 Detailed Logic

1.19
1.19.1
1.19.2
1.19.3
1.20
1.20.1
1.21
1.21.1
1.21.2
1.21.3
1.22
1.22.1
1.22.2

EAE Instruction Decoding Logic
EI R Register
MODE Flip-Flop Logic
ROM Logic
EAE Timing Logic
EAE Timing Generator Timing Diagram
EAE Source Control Signals
Register Input Enable Signals
Data Line Enable Signals
Data Enable Signals
EAE Route Control Signals
Step Counter Loading and Control Logic
Step Counter Logic

iii

1-19
1-19
1-19
1-19
1-21
1-21
1-22
1-27
1-29
1-29
1-30
1-30
1-32

CONTENTS (Cont)
Page
1.22.3

Shift Right/Shift Left Control Logic

1.22.4

Shift OK Logic

1-34

1.22.5

EAE Carry In Logic

1-34

1.22.6

MQ Register Shift Left Logic

1-35

1.22.7

AC to MQ Transfer Signals

1-35

1.23

Destination Control Signals

1-35

1.24

EAE Start/Stop Logic

1-37

1.25

Extended EAE Logic

1-37

1.26

EAE Link Control Logic

1-37

1.27

EAE Skip Logic and GT Flag

1-39

Section 5 Maintenance
Section 6 Spare Parts
PART 2 MEMORY EQUIPMENT OPTIONS
CHAPTER 1 MRS-F 1K PROM
Section 1 Introduction
1.1

Physical Description

1-1

1.1.1

MRB-F Specifications

1-2

1.1.2

Documentation

1-2

Section 2 Installation and Acceptance Test
1.2

Installation Requirements

1.2.1

Installation

1-3
1-3

1.2.2

Acceptance Test

1-3

Section 3 MRS-F Description and Addressing
1.3

MRB-F Description

1-4

1.3.1

Address Decoder

1-4

1.3.2

Starting Address Decoder

1-4

1.3.3

Memory Control and Timing Logic

1-4

1.3.3.1

SW Start

1-4

1.3.3.2

Read or ReadlWrite

1-4

1.3.4

1K PROM

1-7

1.3.5

13th Bit PROM

1-9

1.3.6

ROM Address Flag

1-9

1.3.7

Read/Write Memory (RAM)

1-9

1.3.B

Data Multiplexer

1-9

1.4

Programming

1-12

1.4.1

PROM Erasing Procedure

1-13

CONTENTS (Cont)
Page
Section 4 Detailed Logic Description
1.5

Introduction

1-13

1.5.1

Address Decoder

1-13

1.5.2

Timing and Processor Control for SW Start of Memory

1-14

1.5.3

Field and Starting Address Select Logic

1-16

1.5.4

Memory Address Control Signal Generation

1-16

1.5.4.1

MCL LATCH PULSE L

1-17

1.5.4.2

STALL DLY

1-17

1.5.4.3

ROM ADDR

1-17

1.5.5

1K PROM Memory and Control Logic

1-17

1.5.6

256 Read/Write Memory and Control Logic

1-18

1.5.7

ROM and RAM Data Multiplexer

1-21

Section 5 Maintenance
Section 6 Spare Parts
Section 7 IC Descriptions
1.6

IC Descriptions

1-21

1.6.1

DEC 74157 IC Description

1-21

1.6.2

DEC 74200 IC Description

1-23

1.6.3

DEC 1702A IC Description

1-24

CHAPTER 2 KMS-E MEMORY EXTENSION AND TIME-SHARE
Section 1 Introduction
2.1

Memory Extension Description

2-1

2.2

Time-Share Description

2-2

2.3

Extended Memory and Time-Share Summary

2-3

2.4

Software

2-3

2.5

Companion Documents

2-4

Section 2 Installation
2.6

Installation

2-4

2.7

Checkout

2-4
Section 3 Principles of Operation

2.8

Introduction

2-5

2.9
2.9.1
2.9.2

System Description

2-5

Control Logic

2-7

Instruction Field Register and Controls

2-8

CONTENTS (Cont)

Page
2.9.3
2.9.4
2.9.5
2.9.6
2.10
2.10.1
2.10.2
2.10.3
2.10.4

Interrupt Buffer A
Data Field Register And Controls
Interrupt Buffer B
Extended Memory Addressing Output Control
Operating Functions
Status Operation
Interrupt Buffer Transfer to Memory and Restoration
Instruction Field Register Loading Operation
Time-Share Operation of the System

2-9
2-9
2-9
2-9
2-10
2-10
2-11
2-12
2-12

Section 4 Detailed Logic

2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
2.23

Instruction Field Registers
Instruction Field Output Multiplexer
Data Field Logic
Data Field Output Multiplexer
Data Field Output Gates
Interrupt Buffers Logic
Interrupt Inhibit Logic
Interrupt-Break Detect Logic
Register Clear Logic
Data I n Logic
User Flag Logic
Trap Detect Logic
Extended Memory Address Logic

2-15
2-15
2-15
2-15
2-15
2-19
2-19
2-19
2-19
2-19
2-19
2-23
2-23

Section 5 Maintenance
Section 6 Spare Parts
CHAPTER 3 MRS-E READ-ONLY MEMORY
Section 1 Introduction

3.1

3-1

Read-Only Memory Description
Section 2 Installation

3.2
3.3

3-1
3-2

Installation
Acceptance Test
Section 3 System Description

3.4
3.5

3-2
3-2

MR8-E Block Diagram
ROM Addressing

CONTENTS (Cont)
Page
Section 4 Detailed Logic
3.6

Address Decoder

3-4

3.7

Switch Select Logic

3-4

3.8

Line Driver Select Logic and Line Drivers

3-7

3.9

Sense Logic and Memory Register

3-7

3.10

Clear Logic

3-9

3.11

Line Select Diode Matrix

3-9

Section 5 Maintenance
Section 6 Spare Parts
CHAPTER 4 MIS-E HARDWARE BOOTSTRAP LOADER
Section 1 Introduction
4.1

General Description

4.2

Equipment Requirements

4-1

4.3

Companion Documents

4-2

4.4

Software

4-2

4-1

Section 2 Installation

4.5

Installation

4-2

4.6

Checkout

4-2
Section 3 Operating Procedures
Section 4 Principles of Operation

4.7

General Description

4-4

4.8

Major Portions of the MI8-E

4-5

4.8.1

Address and Data Information

4-6

4.8.2

Sequence of Operations

4-7

4.8.3

Bootstrap Timing (Figure 4-2)

4-7

4.9

Detailed Logic Description

4-7

4.9.1

Bootstrap Timing Logic (Figure 4-3)

4-7

4.9.2

Bootstrap Control Logic (Figure 4-6a and b)

4·11

4.9.3

Initial/Starting Address Jumper Network and Output Logic (Figure 4-7)

4·13

4.9.4

Extended Memory Field Output Logic (Figure 4-8)

4·13

12 x 32 Diode Matrix and Control Logic (Figure 4-9)

4·13

4.9.5

Section 5 Maintenance
4.10

Troubleshooting

4·13

4.10.1

MI8-E Bootstrap Diagnostic Program

4·16

vii

CONTENTS (Cont)
Page

4.10.2
4.11

Direct Memory Access Control Signal Verification
Bootstrap Hardware Troubleshooting Analysis

4-16
4-16

Section 6 Spare Parts

CHAPTER 5 MP8-E MEMORY PARITY
Section 1 Introduction

5.1

MP8-E Description

5-1
Section 2 Installation

5.2
5.3

Installation

5-1

Acceptance Test

5-2

Section 3 Principles of Operation
Section 4 Detailed Logic

5.4

Field Select Gating

5-2

5.5

Parity Generator

5-5

5.6

Error Flip-Flop and Gating

5-5

5.7

lOT Decoding and Skip, Interrupt Gating

5-7

5.8

Special lOT Control

5-8
Section 5 Maintenance
Section 6 Spare Parts

PART 3 REAL-TIME CLOCK OPTIONS
CHAPTER 1 REAL-TIME CLOCK OPTIONS
Section 1 Introduction
Section 2 Block Diagram
Section 3 Detailed Logic

1.1
1.2
1.3
1.4

1-2
1-2
1-2
1-3

Select Logic
Interrupt Flip-Flop Logic
Clock Flag Logic
Clock Logic

viii

CONTENTS (Cont)
Page

1.4.1
1.4.2

DKS-EA

1-3

DKS-EC

1-4
Section 4 Maintenance
Section 5 Spare Parts
PART 4 POWER-FAIL OPTION

CHAPTER 1 KP8-E POWER-FAIL AND AUTO-RESTART
Section 1 Introduction
Section 2 M848 Block Diagram
Section 3 M848 Detailed Logic
1.1

Select Logic

1.2

Power Monitor Logic

1-1
1-2

1.3

Auto-Restart Logic

1-5
Section 4 Maintenance
Section 5 Spare Parts

PART 5 INTERPROCESSOR OPTIONS
CHAPTER 1 DB8-E INTERPROCESSOR BUFFER
Section 1 Introduction
Section 2 Installation

1.1
1.2

Installation

1-1

Acceptance Test

1-2
Section 3 System Description
Section 4 Detailed Logic

1.3

Device Select Logic

1-4

1.4
1.5
1.6

Operation Select Logic

1-4
1-4
1-7

Interruptand Skip Logic
Input Data Gates and Output Buffers

CONTENTS (Cont)
Page
Section 5 Maintenance

1.7

1-7

Data Transfer Test
Section 6 Spare Parts
PART 6 EXTERNAL BUS INTERFACE CONTROL OPTIONS

CHAPTER 1 KAS-E POSITIVE I/O BUS INTERFACE
Section 1 Introduction
Section 2 Block Diagram
Section 3 Detailed Logic

1.1
1.2

BIOP Pulse Generator Logic

1-1

BMB Buffers/I nverters

1-3

1.3

lOP Timing Logic

1-3

1.4
1.5

Data Gating Logic

1-8

Skip Counter Logic

1-8
Section 4 Maintenance
Section 5 Spare Parts

CHAPTER 2 KDS-E DATA BREAK INTERFACE
Section 1 Introduction
Section 2 Block Diagram
Section 3 Detailed Logic

2.1
2.2

CP Register Control Logic

2-1

Cycle Select Logic

2-4

2.3

Priority Logic

2-7

2.4

B KMA Register Logic

2-8

2.5
2.6

Data Transfer Logic

2-10

we Overflow Logic and EMA Register Logic

2-13

Section 4 Maintenance
Section 5 Spare Parts

ILLUSTRATIONS
Figure No.

Title

Page

PART 1
1-1

EAE Interconnections

1-2

EAE System Block Diagram

1-5

1-3

Step Counter Loading, Flow Diagram

1-6

1-4

Step Counter to AC, Flow Diagram

1-7

1-5

SHIFT Operations, Flow Diagrams

1-8

1-6

NORMALIZE Operation, Flow Diagram

1-9

1-7

DPSZ Instruction, Flow Diagram

1-9

1-8

DCM Instruction, Flow Diagram

1-10

1-9

DPIC Instruction, Flow Diagram

1-10

DST Instruction, Flow Diagram

1-12

1-11

DAD Instruction, Flow Diagram

1-12

SAM Instruction, Flow Diagram

1-13

MUY Instruction/Operation, Flow Diagram

1-14

MUY Instruction Data Paths

1-15

DIVIDE Instruction, Flow Diagram

1-16

Major Registers

1-17

Divide Example - Divides 2218 by 148

1-18

1-20

1-19

EI R Register and Controls
MODE Flip-flop Logic

1-20

ROM Logic

1-22

1-21

ROM 1 Instructions

1-23

1-22

ROM 2 Instructions

1-24

1-23

EAE Timing Logic

1-25

1-24

EAE Timing Generator Timing Diagram

1-26

1-25

Source Control Data Path, Simplified Block Diagram

1-27

1-26

Processor Register Selection Logic

1-28

1-27

Data Line Enable Signals

1-29

1-28

EAE Data Control Logic for Processor Data Control Gates

1-30

1-29

EAE Route Control Signal Block Diagram

1-31

1-30

Step Counter Loading and Control Logic

1-32

1-31

EAE Step Counter

1-33

1-32

EAE Shift Right/Shift Left Control Logic

1-34

1-21

1-33

Shift OK Logic

1-35

1-34

EAE Carry In Logic

1-35

MQ Register Shift Left Logic

1-36

AC -+ MQ TRANSFER Signal

1-36

1-37

Destination Control Logic

1-36

1-38

EAE Start/Stop Logic

1-38

1-39

Extended EAE Logic

1-39

1-40

EAE Link Control

1-40

1-41

EAE Skip Logic

1-41

ILLUSTRATIONS (Cont)
Figure No.

Title

Page

PART 2

1-1

MR8-F Block Diagram

1-5

1-2

SW Start Timing

1-6

1-3

Read Timing

1-7

1-4

13th Bit Read/Write Timing (Slow Cycle)

1-8

1-5

PROM Block Diagram

1-6

PROM Addressing Scheme

1-8
1-9

1-7

Address Decoder Logic

1-14

1-8

MR8-F Timing and SW Operation Control Logic

1-15

1-9
1-10
1-11
1-12

Field and Starting Address Select Logic

1-17

Memory Address Control Signal Generator

1-18
1-19
1-20
1-22
1-24
1-25

1K PROM and Control Logic
ROM and RAM Data Multiplexer and Latch

1-13

RAM Memory (256 Word)

1-14

DEC 74157 IC Illustrations

1-15

DEC 74200 IC Illustrations (256-bit RAM)

1-16

DEC 1702A IC Illustrations

1-26

2-1

Memory Extension, Simplified Block Diagram

2-2

2-2
2-3

Typical Time-Share System

2-3

Memory Extension and Time-Share Control, System Block Diagram

2-6

2-4

Extended Memory Addressing, Flow Diagram

2-10

2-5

IF and OF Display Status During TSl

2-11

2-6

Interrupt Buffer Transfer to Memory and Restoration, Flow Diagram

2-12

2-7

I nterrupt Buffer Transfer to Memory and Restoration

2-13

2-8

Instruction Register Loading, Flow Diagram

2-14

2-9

I nstruction Field Registers and Gating Logic

2-16

2-10

Instruction Field Output Multiplexer

2-17

2-11

Data Field Logic

2-18

2-12

Data Field Output Multiplexer

2-18

2-13

Data Field Output Gates

2-19

2-14

Interrupt Buffers Logic

2-20

2-15

Interrupt Inhibit Logic

2-21

2-16

Interrupt Break Detect Logic

2-21

Data I n Logic

2-22

User Flag Logic

2-22

Time-Share Trap Logic

2-23

Extended Memory Address Logic

2-24

3-1

Read-Only Memory Block Diagram

3-3

3-2

H241 Braid Board

3-4

3-3

Address Decoder Logic

3-5

3-4

Switch Select Logic

3-6

2-17
2-18
2-19
2-20
2-21

xii

ILLUSTRATIONS (Cont)
Title

Figure No.

Page

3-5

line Driver Select Logic

3-6

line Drivers and Diodes

3-7

Sense Logic and Memory Register

3-10

3-S

Clear Logic

3-10

3-9

Read Timing Diagram

3-11

3-10

line Select Diode Matrix

3-12

4-1

MIS-E Block Diagram

4-6

4-2

Bootstrap Timing

4-S

4-3

Bootstrap Timing Logic

4-9

4-4

74123 Logic Diagram and Truth Table

4-10

4-5

CLEAR GO Signal Waveform Analysis

4-11

4-6

Bootstrap Control Logic

4-12

4-7

Initial/Starting Address Jumper Network

4-14

4-S

Extended Memory Field Output Logic

4-15

4-9

12 X 32 Diode Matrix

4-15

5-1

MPS-E Block Diagram

5-3

5-2

Field Select Gating

5-4

5-3

74180 S-Bit Parity IC

5-4

Parity Generator

5-6
5-6

5-5

ERROR Flip-Flop and Gating

5-7

5-6

lOT Decoding and Skip, Interrupt Gating

5-9

5-7

Special lOT Control

5-9

PART 3
1-1

Real-Time Clock (DKS-EA, DKS-ECL Block Diagram

1-2

Select Logic

1-3

INTERRUPT Flip-Flop Logic

1-4

Clock Flag Logic

1-5

Clock Logic DKS-EA

1-5
1-5

1-6

Clock Logic, DKS-EC

1-6

PART 4
1-1

MS4S Power-Fail and Auto-Restart Option, Block Diagram
Select Logic

1-2

1-2
1-3

Power Monitor Logic

1-4

1-4
1-5

Power Fail Timing

1-5

Auto-Restart Logic

1-7

1-6

Auto-Restart Timing

1-S

xiii

1-3

ILLUSTRATIONS (Cont)
Title

Figure No.

Page

PART 5
1-1

Interprocessor Buffer, Block Diagram

1-4

1-2

Device Select Logic

1-5

1-3

Operation Select Logic

1-5

1-4

Interrupt and Skip Logic

1-6

1-5

Input Data Gates and Output Data Gates and Drivers

1-8

PART 6
1-1

Positive I/O Bus Interface, Block Diagram

1-2

BIOP Pulse Generator Logic

1-3

BMB Buffers/Inverters

1-4

lOP Timing Logic

1-5

Waveforms, lOP Timing Logic

1-7

1-6

Data Gating Logic

1-9

1-7

Skip Logic

1-10

1-8

Timing, Skip Logic Application

1-11

2-1

Data Break Interface, Block Diagram

2-2

CP Register Control Logic

2-3

Cycle Select Logic

2-5

2-4

Timing, Register Control and Cycle Select Logic

2-6

2-5

Priority Logic

2-7

2-6

BKMA Register Logic

2-9

2-7

Data Transfer Logic

2-11

2-8

Word Count Overflow and EMA Register Logic

2-13

TABLES
Table No.

Title

Page

PART 1
1-1

Divide Instruction Table of Combinations

1-17

1-2

1-27

1-3

EAE Combinations of DATA T and DATA F

1-29

1-4

Recommended KE8-E Spare Parts

1-48

xiv

TABLES (Cont)
Table No.

Title

Page

PART 2
1-1

MR8-F Signals

1-2

MR8-F Spare Parts

1-23

2-1

KM8-E Extended Memory and Time-Share Option Instructions

2-7

1-10

2-2

Recommended KM8-E Spare Parts

2-25

3-1

Line and Switch Identification for ROM Addresses

3-8

3-2

Typical Error Typeout

3-13

3-3

Recommended MRS-E Spare Parts

3-13

4-1

MIS-E Bootstrap Loader Option Encoding Scheme

4-3

4-2

Recommended MI8-E (M847) Spare Parts

4-17

5-1

MP8-E lOT Summary

5-S

5-2

Recommended MP8-E Spare Parts

5-10

PART 3
1-1

Recommended DK8-EA/DKS-EC - (M882/MSS3) Spare Parts

1-6

PART4

1-1

Jumper Installation

1-4

1-2

Recommended KP8-E Spare Parts

1-9

PART 5

1-1

Connection from J 1 to J2

1-2

Simultaneous Receive and Transmit Operation by

1-3

Two PDP-8/E Computers Using Interprocessor Buffer

1-7

DB8-E Recommended Spare Parts

1-9

PART 6

1-1

KA8-E Cable Information

1-12

1-2

KA8-E Recommended Spare Parts

1-13

2-1

8271 IC Control Signals

2-5

2-2

Control Signals, Cycle, Type, and Direction of Transfer

2-12

2-3

KD8-E Cable Information

2-14

2-4

KD8-E Recommended Spare Parts

2-15

PREFACE

This manual, the second in a series of three, describes nonperipheral
options of the PDP-8/E, PDP-81M, and PDP-8/F.
The content of this manual includes installation procedures, theory
of operation, and maintenance procedures for the options described.
It is assumed that the reader is thoroughly familiar with Volume 1 of
this series, and with the applicable sections of the 1972 PDP-8IE
PDP-81M, and PDP-8IF Small Computer Handbook.

PART 1
EXTENDED ARITHMETIC ELEMENT OPTION

CHAPTER 1
KES-E EXTENDED ARITHMETIC ELEMENT

SECTION 1 INTRODUCTION
1.1 GENERAL DESCRIPTION
The KE8-E Extended Arithmetic Element option enables the PDP-8/E to perform arithmetic operations at high
speeds by incorporating EAE components with the existing central processor logic so that they operate asynchronously. All logic is contained on two quad-size modules, designated M8340 and M8341 , which plug directly into
the OMNIBUS. The two modules are interconnected by one H851 Connector. A second H851 Connector interconnects the M8341 to the major registers control module (Figure 1-1). This connector carries register gating and
controls from the EAE modules to the register controls module. A third H851 Connector interconnects the processor's M8330 Timing Generator Module with the EAE control, supplying clock and lOT functions to the EAE.
The basic OMNIBUS signals connect to each module.

1.2 SOFTWARE
The following programs are used in the maintenance of the KE8-E option.

KE8-E EAE Test Part 1 (MAINDEC-8E-DOLB) - This program tests all EAE instructions except
MUYand DVI.

KE8-E EAE Test Part 2 (MAl NDEC-BE-DOMB) - This program tests the MUY and DVI instructions.

KE8-E EAE Extended Memory Exerciser (MAINDEC-8E-DORA) - The KE8-E Extended Memory
Exerciser is a test of the KE8-E "8 Mode" instructions which, during the DEFER cycle, use the word
following the instruction to obtain the operand. The capability of each instruction to access every
memory field from every memory field through nonautoindex and auto-index is tested.

1.3 COMPANION DOCUMENTS
The following documents and publications are necessary in the operation, installation, and maintenance of this
option:
a.
b.
c.
d.

e.
f.
g.

PDP-8IE & PDP-BIM Small Computer Handbook - DEC, 1973
PDP-8IE Maintenance Manual - Volume 1
Introduction to Programming - DEC, 1972
DEC engineering drawings M8340-0-1 and M8341-0-1
KE8-E EAE Test Part 1, MAINDEC-8E-DOLB-D
KE8-E EAE Test Part 2, MAINDEC-8E-DOMB-D
KE8-E EAE Extended Memory Exerciser, MAINDEC-8E-DORA-D

1-1

MD, DATA BUS, TIMING, CONTROL, ECT.
OMNIBUS
~.~_ _•

FRONT OF COMPUTER
8£-0444

Figure 1-1

EAE Interconnections

SECTION 2 INSTALLATION
The KE8-E EAE option is installed on site by DEC field service personnel. The customer should not attempt to
unpack, inspect, install, checkout, or service the equipment.
1.4 INSTALLATION
Perform the following procedures to install the KE8-E options:
Step

Procedure
Remove the modules from the shipping containers.

Inspect the modules for any apparent damage.

Connect the modules as follows:

Insert the EAE modules between the Timing Generator and the CP Major Registers
and Register Control as follows:
M8330
M8340
M8341
M8310
M8300

Timing Generator
EAE Decoder and Step Counter
EAE Multiplexers and Timing Generator
CP Major Registers Control
CP Major Registers

The five modules must be installed in this order with no vacant slots between them
for the H851 Connectors to fit properly.

Install H851 Connectors (five total) to connect the five modules. All connectors
at the top of these modules will be utilized when all H851s are installed.
NOTE
The EAE is a complex instruction decoder that extends the basic PDP-8/E instruction set. It is intimately connected with the basic central processor
and relies heavily on an M8300 and M8310 in good
condition. Many potential problems can be avoided
by running Instruction Test I (MAINDEC-8E-DOAB)
and Instruction Test II (MAINDEC-8E-DOBB) before installing the EAE to verify the condition of the
CPU. These tests should be run again after EAE installation to verify that the EAE is not malfunctioning
and thereby modifying the basic instruction set.

1.5 CHECKOUT
Perform the following procedures to checkout the KE8-E option:
Procedure

Step

Verify that both EAE modules have been installed

Perform acceptance test procedures provided in Volume 1, Paragraph 2.3.

Load MAINDEC-8E-DOLB and perform EAE Test - Part I.

Load MAl NDEC-8E-DOMB and perform EAE Test - Part II.
(continued on next page)

1-3

Step

Procedure

Load MAINDEC-SE-DORA and perform EAE extended memory exerciser (even if
4K machine).

Make entry on user's log that the acceptance test for the KES-E was performed
satisfactorily.

SECTION 3 SYSTEM DESCRIPTION
The organization of the EAE system block diagram (Figure 1-2) follows the organization of the detailed logic
description. The detailed logic is organized by source, route and destination and contains logic diagrams representing each block illustrated in Figure 1-2.
Signals generated within the EAE control the operation of the MS300 Major Registers Module during EAE instructions. The processor timing extension logic causes the processor to halt at TP3 and at the same time starts the
EAE Timing Generator. This extends TS3 to enable data to be applied to the adders a number of times. The EAE
selects which register is to go into the adders by asserting a combination of signals shown in the EAE source controllogic block. What happens to the data when it is on route to its destination is accomplished by asserting a combination of signals in the EAE route control signals block. The destination of the data is either the AC Register or
the MQ Register.
The EAE was designed for hardware compatibility with old programs that were written for the PDP-S/1. The
MODE flip-flop is cleared, selecting Mode A, when the computer is turned on. Mode A is the PDP-S/I compatible
mode. Mode 8 is selected (via the mode-change instruction) only when using programs developed specifically for
this EAE.
To better understand how the EAE functions, 13 of the EAE instructions are described in terms of functional
flow to illustrate how the EAE completes each instruction.
NOTE
EAE operation is more integrated with the CPU than
most options. Before attempting to study EAE theory
of operation, the reader should thoroughly understand
CPU theory and review sections of Volume 1 as he is
reading this chapter.
1.6 STEP COUNTER LOADING OPERATION (Figure 1-3)
The Step Counter controls the number of shifts performed during the ASR, LSR, and SHL instructions. It also
controls the number of steps taken during MUL or DVI, and records the number of shifts required to normalize
a number.
The KES-E provides two methods of loading the Step Counter. The ACS instruction is used by the new, or Mode
8, instruction set; the SCL instruction is used by the old, or Mode A, instruction set. The SCL instruction is of
interest because this same method of step counter loading is used within the SHL, LSR, and ASR instructions in
both modes.
The ACS instruction takes place in a manner similar to an I/O transfer to a peripheral. The contents of the AC
are placed on the OAT A 8 US during TS3. CO is grounded so that the AC will be cleared. At the leading edge of
TP3 the five least-significant bits are loaded into the Step Counter.

1-4

EAE ON
TGI
TG2

fEAE
TIMING
EXTENSION
LOGIC

f'EA'EiNSTRUCTION- I DECODING LOGIC

I
I

RESTART

- - --..,

I
I

SOURCE - - - - - ,

I CONTROL LOGIC

r-P-R-O-C-ES-S-O-R"""L~ NOT LAST X FER

MODE B

~~~~~--+--ENO

1--+-- EN1

L-~~~~--~-EN2

I
I
I
I
I

r;:::-:;:-;-:-:;-l-J...__ A C -

BU S

L"::':":::':':~~r----t-- MQ -

BUS

r-;::::;:;--l---:--- D AT A T
I
EIR
I
L"::':"::':':":=_r-~- DATA F
I
ROM 1
I
AND
ROM 2
I
IEAE RoUTE CONTROL- - ,
IL ____________I---r---------t~ S I G NALS
II
I---+-_ LAST STEP
F E SET
F D SET
NEXT LOC H

t=t:

RIGHT

I---+-_ L EFT

L _ _ _ _.t--t-... SH I FT OK

LINK DATA
LINK
CONTROL
LOGIC

SHIFT
LOGIC

ADLK
LINK LOAD

1---:-- CARRY IN

ADLK DIS

SKIP
,--_LO_G_I_C_.....

SKI P

I - + - A C - M Q ENA

rEA'E 'DiSi-i'NATION-- - ,

I CONTROL SIGNALS

:L _________
I cgG~g I :
~

AC LOAD
MQ LOAD

8E- 0445

Figure 1-2 EAE System Block Diagram

The SCL instruction is somewhat more complicated. The Step Counter is to be loaded with the 1 's complement
of the next word in memory. As soon as the instruction is decoded, the SKIP line on the OMNIBUS is grounded.
As explained in Paragraph 3.38 of Volume 1, the SKIP line is tested during lOT and OPERATE instructions.
Grounding the SKIP line causes the next location (which, in this instance, contains the data for the Step Counter)
to be skipped as an instruction.
During TS4 of the F ETCH cycle, several control I ines into the M8300 Major Registers Module are asserted by the
KE8-E via the H851 Connectors. These signals (ENO and CARRY IN) cause the next location in memory to be
addressed and treated as an operand (F E SET). During TS2 of the EXECUTE cycle, the contents of the five
least-significant MD lines are inverted and applied to the inputs of the Step Counter. At TP2 the Step Counter
is loaded.

1-5

NEW
ONLY

OLD
ONLY

ACS

SCl

TSI
TS2
SETSCLD
AT TP2 l
DATA BUS
-+SC

CO l
TS3

1-+ SKIP

TS4

ENO
CARRY IN
(MA+ I-+MA)
1-+ E

1 -+ F

TS2

MD-+ SC

TS3

TS4

1-+ F

8E-0426

Figure 1-3 Step Counter Loading, Flow Diagram

1-6

1.7 STEP COUNTER TO ACCUMULATOR LOADING OPERATION (Figure 1-4)
The contents of the Step Counter are ORed with the contents of the AC and the result transferred to the AC.
The entire operation is so similar to an lOT input OR transfer that it will not be discussed further.

1.8 THE SHIFT LEFT OPERATION
SCA
NEW: 10
OLD: 1X

The shift left (SHL) instruction (Figure 1-5) isa 2-cycle instruction.
The first cycle fetches the instruction word; the second cycle fetches

TS1

a number that specifies the number of shifts that are to occur. The

TS2

entire operation is identical to the SCL instruction up to and includSCV DATA

ing TP2 of the EXECUTE cycle.
At the start of TP3 of the EXECUTE cycle, the EAE must shift the
contents of the AC, MO, and Link left by the number of places specified in the Step Counter. Normal machine timing stops at TP3 and

TS3

EAE timing begins; one shift operation occurs with each clock pulse
until the last shift has been performed.
Once the EAE is on, the following signals to the M8300 are asserted:
Signal

Function

LEFT L

Enables left shift gates at output of adders.

SHL+ LD EN L

Enables MO left shift path.

ADLK DIS L

Disconnects the normal Link-AC11 shift
path. Also disconnects the ACO-Link shift
path.

TS4

l~F

BE-0427

Figure 1-4 Step Counter to AC,
Flow Diagram

The following logic functions also occur:
Signal

Function

MOO ~ADLK L

Establishes shift path from MOO to AC11.

ACO ~ LINK DATA L

Establishes shift path from ACO to Link.

MO DATA is negated (high) so 0 is shifted into the M011. For each shift AC LOAD, MO LOAD and LINK LOAD
are developed and 1 is added to the step count. When the step count reaches 37, the EAE starts its shut-down
process.
If the instruction mode is A, the EAE merely performs its last shift with NOT LAST XFE R high. The processor
restarts, and the total number of shifts is one more than the number in the second core location. If the instruction mode is B, a special line within the EAE, SHIFT OK H, is negated. Negating SHIFT OK H negates the signals
required to cause AC shifts, and inhibits LI NK LOAD and MO LOAD. Thus, the processor starts without taking
the final shift; the number of places shifted is equal to the number in the second core location.

1.9 RIGHT SHIFT OPERATIONS (Figure 1-5)
Two right-shift instructions, ASR and LSR, are available in the EAE option. The only difference between the
two instructions is how the Link is handled. The Link is loaded at TP3 of the FETCH cycle via the OMNIBUS.
If the LSR instruction (logical right shift) is being processed, no data is placed on the LINK DATA line and thus
the Link is cleared. If the ASR instruction (arithmetic right shift) is being processed, ACO is placed on the LINK
DATA I ine and the Link is thus made equal to ACO.

1-7

ASR

LSR

ACO -+ LINK DATA.
ADLK DIS l.
LINK LOAD.
(ADO -+ LINK)

ADLK DIS L
LINK LOAD
(0-> LINK)

SHL

TSl
TS2

TS3

\ /
1 -+ SKIP

1 -+ SKIP

TS4

ENO
} (MA+l-+
CARRY IN
MA)
l-+E

l-+E

TS2

MD-+ SC

MD -+SC

START EAE TC AT TP3.

IF EAE ON;
LEFT L
SHL + LD EN L
ACO-+lINK DATA

IF EAE ON;
RIGHT L
MOll-- GT DATA
MO LOAD. GT LOAD
AC LOAD

ENO
)
CARRY IN

MO LOAD. LINK LOAD
AC LOAD
ADLK DIS L
E

ADLK DIS MUST
BE HIGH

MOO--ADLK L

TS3

(MA+l-+
MA)

~
RESTARTCPWHEN
SC =37

IF "NEW" AND SC = 37.
DISABLE SHI FT PATHS.
NO MO. LINK. OR GT
LOAD.

1 -+ F

TS4

BE-0425

Figure 1-5 SHI FT Operations, Flow Diagrams
As in the case of SH L, the computer enters the EXECUTE cycle to obtain step-count information. When the
EAE is turned on at TP3 of the EXECUTE CYCLE, the following signals are asserted:
Signal

Function

RIGHT L

Enables MO right shift, enables right shift gates at
adder outputs.

M011 -+ GT DATA

Enables path from M011 to the GT flag.

1-8

Like the SHL instruction, AC LOAD and MQ LOAD are generated for each shift and the step count is
incremented. GT LOAD is also generated for each shift, although the GT flag is held cleared if it is in Mode A.
Notice that the Link is not loaded, and that ADLK DIS L is high. These two conditions mean that the Link is
not modified during shifting, but that the output of the Link is coupled to the input of ACO. All other details
are similar to those given for the SH L instruction.
1.10 NORMALIZE INSTRUCTION (Figure 1-6)
Normalization is the process by which the 24-bit fixed-point word in the AC and MQ Registers is converted to
floating-point format and expressed as a fraction and the corresponding power of two.
The 1-cycle NORMALIZE instruction is completely implemented during TS3 of the FETCH state. Because the
final shift count is important to this operation, the Step Counter is initially cleared (zeroed). OMNIBUS signal
NOT LAST XFER L is asserted and, at TP3, processor timing comes to a halt and the EAE Timing Generator is
started. The Normalize operation only occurs if SHIFT OK H remains H, as determined by comparing ACO to
AC1. If the two are not equal, SHI FT OK H is grounded, thereby causing the EAE timing to halt and restart
the processor timing.
As long as ACO and AC1 are equal, AC, MQ, and Link will shift one place to the left as if they were one long register, as explained for the SHL instruction. Each time a shift occurs, 1 is added to the Step Counter. This continues until the EAE finds ACO not equal to AC1. Another condition for which the Normalization process is terminated is when AC2-MQ11 are all equal to 0 (the word cannot be normalized). The Normalization process also
terminates in Mode B if the 24-bit word in the AC and MQ equals 40000000 (only ACO is a 1); CO is grounded
during TS3 so that the AC is cleared.
1.11

DOUBLE-PRECISION SKIP IF ZERO (DPSZ) (Figure 1-7)

The 24-bit number in the AC and MQ is tested. If all bits are 0, the next instruction is skipped. If any bit is a 1,
the next instruction is executed.

NMI

DPSZ

TSl

TS2

TS3

TS2
O"'SC
START EAE TC
ATTP3
ADLK DIS L
ACO'" L DATA
SC+l-+SC
IF EAE ON, SHIFT
LEFT UNTIL ACO fAC1, OR AC1·MQ11
= O.

IF AC & MQ= 0,
l-+SKIP

TS3

WHEN NORMALIZED,
RESTARTCP.
IF "NEW" & AC,
MQ = 40000000,
CO L.

TS4

l-+F

TS4

BE-0428

l-+F

BE-0429

Figure 1-7 DPSZ Instruction, Flow Diagram

Figure 1-6 NORMALIZE Operation, Flow Diagram

1-9

1.12 DOUBLE.pRECISION COMPLEMENT (DCM) (Figure 1-8)
The objective of the DCM instruction is to form the 2's complement of the 24-bit word in the AC and MO. Since
the M8300 Major Registers Module is capable of only 12-bit arithmetic, the complete DCM operation requires
two passes through the adders. These passes are labeled Step 1 and Step 2 in Figure 1-8 and in the following
paragraphs. The entire operation takes place in the FETCH cycle.
The DCM instruction uses the SWP instruction built into the M8310. (One requirement of the DCM instruction
is that bit 5, controlling the MO -+ AC path, and bit 7, controlling the AC -+ MO path, both be ls.) Thus, as the
DCM instruction is decoded, the M8310 causes MO -+ BUS Land AC -+ MO ENA L (described in Volume 1, Paragraph 3.40). At the KE8-E, two other lines to the M8300 are being controlled. These lines are DATA F L, which
is asserted for both operations and CARRY IN L, which is unconditionally asserted for Step 1 and asserted if Link
is 1 for Step 2. The KES-E also disables normal Link gating and places CARRY OUT L from the adders onto the
LINK DATA L lineofthe OMNIBUS. The Link, AC, and MO are loaded at the conclusion of each step. (AC
LOAD and MO LOAD occurs at the end of Step 1 because of the SWP portion of the instruction.) The processor's
timing chain is stopped and the EAE's timing chain is run for one step to provide the extra time and load pulses
for Step 2.
One of the more severe tests of the DCM instruction is to perform this operation on a cleared AC and MO, since
such a task requires the carry to propagate through all 24 bits.
1.13 DOUBLE-PRECISION INCREMENT (DPIC) (Figure 1-9)
The DPIC instruction adds 1 to the 24-bit word in the AC and MO in the same manner as the DCM instruction.
The only difference is that DATA F L is not asserted, allowing the contents of the DATA BUS to be applied to
the adders without being complemented.

DCM

DPIC

TS1

TS2

TS3

T82
AC"'MQ, MO"AC
BECAUSE OF INSTR.
ADLKDISL
CARRY IN
CARRY OUT"'L1NK DATA.
DATAF
[MO LOAD. AC LOAD]
LINK LOAD.
START EAE TC. ONE CYCLE.
L"'CARRYIN
CARRY OUT'" LINK DATA
DATAF
ACLOAD.
MOLOAD
LINK LOAD.

AC"MQ,MO"AC
BECAUSE OF INSTR.
ADLK DIS L
CARRY IN
CARRY OUT" LINK DATA

COMMON TO
BOTH STEPS

STEP 1
T83

L"CARRYIN
CARRY OUT" LINK DATA

STEP 2

AC LOAD,
MOLOAD
LINK LOAD
TS4

TS4

[MO LOAD, AC LOAD]
LINK LOAD
START EAE TC, ONE
CYCLE ONLY

1 ... F

1"'F

BE-0430

BE-0421

Figure 1-9 DPIC Instruction, Flow Diagram

Figure 1-8 DCM Instruction, Flow Diagram

1-10

1.14 DOUBLE-PRECISION STORE (DST) (Figure 1-10)
The contents of MO and AC are stored at the double-precision location (two consecutive memory locations)_ The
AC, MO, and Link are not changed by this instruction_ When the EAE decodes the DST instruction (Figure 1-10),
the next location is accessed in a manner similar to the SCL instruction. Instead of grounding F E SET, however,
the DST instruction grounds F 0 SET, thereby causing the computer to enter the DEFER major state and treat
the next location as an address.
At the conclusion of the DEFER cycle, the computer enters the EXECUTE CYCLE. Simultaneously, a flip-flop
within the EAE sets. This flip-flop (EX1) grounds F E SET, causing the processor to perform two consecutive
EXECUTE cycles and forcing MA + 1 ~ MA at the end of the first EXECUTE cycle. EX1 is cleared at the end of
the first of these EXECUTE cycles, allowing normal processing to resume at the conclusion of the second
EXECUTE.
During each of the EXECUTE cycles, the following processor signals are asserted during TS2:
Function

Signal

MO~BUS }
DATAT
MD DIS

Gates MO Register to MB.
Removes the MD, which is normally applied to the
MB via the adders.

(AC ~ MO ENA L is also grounded, but has no effect since the MO is not loaded at TP2.)
During TS3, the usual gating is set up to swap the contents of the AC and MO. Hence, the sequence of events
during the EXECUTE cycle is:

Store the least-significant twelve bits, presently in the MO.

Swap the AC and MO.

Address the next memory location.

Store the most-significant twelve bits presently in the MO.

Swap the AC and MO to return the bits to their original locations.

1.15 DOUBLE-PRECISION ADD (DAD) (Figure 1-11)
The DAD instruction has many similarities to the DST and DCM instructions. Like the DST instruction, it uses a
second memory word as a deferred address. It also requires two EXECUTE cycles to obtain data from two consecutive memory locations. The DAD instruction handles its carry to and from the Link in a manner similar to'
the DCM instruction.
During TS3 of the FETCH cycle, ADLK DIS is grounded, enabling the OMNIBUS LI NK DATA and LINK LOAD
inputs. At TP3, LINK LOAD is generated. Since no data was placed on LINK DATA, the Link is cleared. Other
than clearing the Link, the DAD instruction process is identical to that of the DST instruction for the first two
machine cycles.
During each of the two EXECUTE cycles, a word is obtained from memory and applied to the adders via the MD
lines. During TS3, the output of the Link is applied to the carry input of the adders. The contents of the MQ
are gated to the other inputs to the adders. The carry output of the adders is applied to the LI NK OAT A input

1-11

DST

TS1

TS2

F
TS3

DAD

TS1
1 .... SKIP

TS4

ENO
}
CARRY IN

TS2

(MA+ 1 ....
MA)

ADLK DIS L
LINK LOAD
(0 .... L)

1 .... 0

1 .... EX1

IE1

TS3

MO .... BUS}
DATAT
MODIS

TS3

MO .... MB

(AC:MQ ENA

C- \

,------- I

1 .... SKIP

MO .... BUS
AC .... MOENA L
AC LOAD (SWAP AC,
MO,LOADMO)

END
} (MA+1 ....
CARRY IN . MA)

TS4

1 .... 0

o
TS4

END
CARRY IN
1 .... E

TS2

SAME AS E1

1 .... EX1

TS1
L"'CARRYIN
EN1 (MD)

SAME AS E1

MO"BUS
AC"'MOENAL
CARRY OUT ... LINK DATA
ACLOAD
MOLOAD
LINK LOAD
ADLKDlS L

TS3
ENO L
CARRY IN L
1 .... E

TS2

SAME AS E1

TS3

TS4

1 .... F

BE-0424

1 .... F

8E-0423

Figure 1-10 DST Instruction, Flow Diagram

Figure 1-11

1-12

DAD Instruction, Flow Diagram

of the Link; the path from the AC to MQ is enabled. At TP3 the AC, Link, and MQ are loaded. Hence, the
old AC is moved to the MQ, while the sum of the old MQ and the MD is loaded into the AC. The Link provides
and receives carry information.

1.16 SUBTRACT AC FROM MQ (SAM) (Figure 1-12)
The SAM instruction subtracts AC from MQ and places the result in
SAM

the AC, Link, and GT flag. The MQ is not modified. The entire operation takes place during the F ETCH cycle.

TSI

The MQ is gated to the adders by grounding source control lines ENO

TS2

and EN2 at the H851 Connectors. As listed in Table 3-4 of Volume 1,
ADLK DIS L

the MQ Register is gated to one of the sets of adder inputs. The AC

DATA F

is complemented and introduced to the other set of adder inputs via

CARRY IN

TS3

ENOL} MQ'"
EN2 L
ADDRESS
CARRY OUT'" LINK
DATA
lAC LOAD!

A "Greater Than" signal is generated and applied to the GT flag. The
carry from the address is applied to the Link inputs. The AC, Link,
and GT are loaded, completing the operation.

LINK LOAD
GT GATING ENA
GT LOAD

TS4

the DATA BUS by grounding AC --* BUS, DATA F, and CARRY IN.

The "Greater Than" signal is derived as follows:
a.

If the MQ and the old AC are of different signs, the MQ is
greater than the AC if the MQ is positive. The MQ is less
than the AC if the MQ is negative.

If the MQ and the old AC are of the same sign, the MQ is
greater than (or equal to) the old AC if the output of the
most-significant bit of the adder is positive. Otherwise, the
MQ is less than the AC.

l~F

8E-0422

Figure 1-12 SAM Instruction,
Flow Diagram

Logic at the input of the GT flag computes the "Greater Than" signal.
1.17 MULTIPLY INSTRUCTION (MUY) (Figure 1-13)
The MUY instruction combines the multiplicand (which was previously loaded into the MQ Register) with a multiplier (obtained from memory by the MUY instruction), using the rules of binary multiplication. The result is
left in the AC and MQ. The multiplication requires twelve (decimal) steps which are counted by the Step Counter.
At each step, MQ1l is examined. If it is a 1, the multiplier is added to the AC. Regardless of the state of MQ11,
the AC and MQ are shifted right in the same manner as is done for the LSR instruction, except that the GT flag
is not loaded. This same process is repeated for the new MQ11 until the twelve steps have been completed. At
this point, the AC and MQ contains the 24-bit product.
The MUY instruction requires one FETCH cycle to fetch the instruction, one DEFER cycle (Mode B only) to
obtain the multiplier address, and one EXECUTE cycle to obtain the multiplier and accomplish the multiply
operation.
The decoded instruction clears the Step Counter and places a 0 in the Link by asserting AD LK DIS Land LI NK
LOAD L. It then accesses the next location in memory (refer to SCL instruction). If the older, PDP-8!1 compatible, Mode A instruction set is in use, the next sequential address contains the multiplier. The EAE, therefore,
grounds F E SET L and goes directly to the EXECUTE cycle. If the EAE is in Mode B, F D SET L is grounded
and the processor enters the DEFE R state for the address of the multiplier. At the conclusion of the DE FE R
cycle, the processor automatically enters the EXECUTE state.

1-13

During the first part of the EXECUTE cycle, the multiplier is read
MUY

onto the MD lines, At TS3, NOT LAST XFER L is asserted on the
OMNIBUS; at TP3, processor timing halts, The EAE timing chain is

TSl

then started, The right-shift signals are asserted (refer to the LSR in-

TS2

struction for further details), Each time MQll is a 1, EN1 is grounded

O~SC

by the EAE, If EN 1 is ground, ENO is grounded by the MS31 0 Major

LINK LOAD (0 ~ L)
ADLK DIS L

Registers Control Module, Grounding EN1 and ENO causes the word,
on the MD lines to be added to the partial product, This process continues for the twelve steps necessary to complete the multiplication,

TS3

The last step is made with NOT LAST XFE R high, causing the processor to resume its timing,
The data paths for the MUY instruction are illustrated in Figure 1-14.
1 ~SKIP

This figure also illustrates the control signals that must be enabled to
make this instruction possible,

TS4

ENO
yMA+l~MA
CARRY IN MI
NEW: 1 ~D
OLD: 1 ~E

1.18 DIVIDE INSTRUCTION (DVI) (Figure 1-15)
D

There are two common methods of doing binary division:

AC~ BUS L

Restoring divide (the standard long-hand method): Try to
subtract, If the result is +, place a 1 in the quotient. If the
result is - , the subtraction does not take place; place a 0 in
the quotient, In either case, shift left,
Nonrestoring divide (the method used in PDP-S/E): Always
make the subtraction and always shift left, If the result is +,
place a 1 in the quotient; the next step will also be a subtract, If the result is -, place a 0 in the quotient; the next
step will be an add, This method requires a final correction
step if the final remainder is -.

START EAE TC AT TP3
IF EAE ON, RIGHT L
IFMQ11 =1;EN 1 L,
AC LOAD,
IVIQ LOAD.
REPEAT 12 TIMES.
RESTART CP WHEN
TS3

SC = 13.
ADLK DIS MUST BE
HIGH.

Figure '-15 illustrates the DVI I nstruction, This instruction requires
one FETCH, one DEFER (Mode B only), and one EXECUTE cycle,
The instruction clears the Step Counter at TP3 of the FETCH cycle,
The next memory location is accessed, as explained for the SCL in-

TS4

l~F

struction. If the instruction mode is B, the CPU must obtain the operand address by entering the DEFER major state, Otherwise, the

8E-0420

CPU goes directly into the EXECUTE state,
The first subtraction takes place at TP3 of the EXECUTE cycle, before the EAE is turned on. At the same time, the Link* is set. The

Figure 1-13 MUY Instruction/
Operation, Flow Diagram

EAE is turned on only if there is a carry from the most-significant bit of the adder. Otherwise, a condition known
as divide overflow exists, and the quotient cannot be contained in the 12 bits available. If the EAE is turned on,
the last divide step clears the Link. Thus, the Link is used as a program flag to indicate whether or not divide
overflow occurred.

"Link refers to Processor Link, DIV LNK refers to EAE Link.

'-14

MAJOR REGISTER BUS

RIGHT L

CARRY

CARRY OUT

DATA T L
DATA F H

ENO L
EN1 L

ADDER 11

MAJOR REGI STER BUS

RIGHT L
BE-0442

Figure 1-14 MUY Instruction Data Paths

The Major Registers are shown in Figure 1-16. This figure, an expansion of Figure 3-79 of Volume 1, shows the
signals that are important to the divide process. Notice that the MB300 has no provision for complementing the
MD. The only means of complementing is via the data control gates which are in the AC shift path. In order to
subtract, the KEB-E must cause AC plus MD -> AC. The AC now contains the complement of the result. Successive subtractions merely cause AC plus MD -+ AC, since the AC is already in complemented form. To change from
subtraction to addition, the KEB-E must cause AC plus MD -+ AC. Of course, successive adds are performed by
AC plus MD -+ AC. Complementing is accomplished by grounding DATA F, and must be performed each time
the quotient bit changes. The logic merely grounds DATA F if M010 =1= M011 after the first two divide steps
have established quotient bits in M010 and M01l. DATA F is grounded for the first two steps.
As explained above, AC may be in its true or complemented form as the divide operation progresses. The MO is
always in its true form, and is the source of unprocessed dividend bits that are shifted into AC11. If the word
being loaded into the AC is in complemented form, MOO must be complemented as it is shifted into AC11. The
logic merely examines M011. If it is a 1, MOO is complemented as it is shifted into AC11.
The fundamental rule governing the quotient bit is as follows:
If the sign of the dividend does not change, MO 11 -> MO 11.
If the sign of the dividend changes, M011 -> M011.
But the sign might have changed because the logic grounded DATA F, so the fundamental
must be expanded to:
If DATA F H and no sign change, or if OAT A F L and the sign changes,
M011 -> M011.

1-15

If DATA F H and the sign changes, or if DATA F L and no sign change,
MOll~MOl1.

Since DATA F L is caused by M010 =1= MOll, a little Boolean manipulation yields:
If M010 = 0 and no sign change, or if MO = 1 and the sign changes, 0 ~ MOll.
If M010 = 0 and the sign changes, or if M010 = 1 and no sign change, 1 ~ MOll.
The sign change is derived from DIV LNK (the AC sign bit after the shift) XORed with CARRY
OUT. All combinations of M01O, MOll, DIV LNK and CARRY OUT are shown in Table 1'1,
together with the resulting quotient bit.

DVI

TS2

o~sc

TS3

l-SKIP
END
}
CARRY IN

NEW;

'~D

OLD;

(MA+l .... MAJ

TS1
TS2

DiViSOR .... MD LINES
ADLK DIS L

}

SHl+ LO ENA L

ASSERTED FOR ENTIRE TIME STATE

AC .... SUSL

LINK DATA l
DATA F L

DVI- E· T53· EAE ON (FIRST STEP ~

ENll

DIVIDE OVERFLOW TEST)

O .... MODATA

LEFTl

SET LlN.K, MAKE
FIRST SUBTRACTION.

MOO .... ADLK

LINK LOAD

IF NO CARRY, ENTIRE

AC LOAD

OPERATION ABORTS

MQLOAO

BECAUSE OF DIVIDE

I F CARRY OUT L: STOP CP,
START EAE TIMING

OVERFLOW

TS3

IF SC '" 12,lEFT L
IF SC '" 0 OR IF MQ11 1: MalO,
DATA F L
MOO XOR MOll-+ ADLK l

ENl L

EAE ON - NORMAL DIVIDE

ADO -+ DIV lNK DATA
DIV LNK XOR CARAY OUT

STEPS (12 TOTAL)

XORM010--.-MQDATAL
AC LOAD
MOLOAD

DIV LNK LOAD
LEFT H
IFM010 oo 1,DATAFL
tFMQ11=O,EN1L

LINK DATA H
AC LOAD
LINK LOAD
RESTART CP

TS'

Figure '-15 DIVIDE Instruction, Flow Diagram

1-16

MAJOR REGISTER

BUS

AOO--------~----------~

LEFT L

CARRY OUT

CARRY

MAJOR

MQ LOAD
MQ DATA

LOAD

REGI STER BUS
8E-0443

Figure 1-16 Major Registers

Table 1-1
Divide Instruction Table of Combinations

MalO

M011

DIV LNK

CARRY OUT

DATA F

SIGN CHANGE

0
0
0

0
0

0
0
0
0
0
0
0

H
H
H
H

no
yes
yes
no
no
yes
yes
no
no
yes
yes
no
no
yes
yes
no

0
1

0
0

L
L
L
L
L
L
L
L

0
1

0
0

,
,,

H
H
H
H

0
0

1
L.XOR.-.J

i
"XOR

1-17

What goes into M011
(MO DATA)

0
1

0
0
1

0
0
0

0
0
1

Step
Corry

Link

0
0
0

Counter

Multiplier Quotient

Ace umul otor

000000 000 000
000 010 010 001
111111 ill 1 1 1 /
000000001 100
000000001011
000 000 010 111
000 100 100 010

00000

000000 001 100
111 111110100
111111101000

00001

Comments

Ae' -+ ADDERS (FI RST STEP)
MD-+ADDERS

'" '" '" ""I
'" '" "'"'"I

001001000100

MOO-+ACll

AC -+ ADDERS (MalO = Malt)

000 000 001 100
111111110 100

111111101000

010 010 001000

00010

'" '" '""'''

000000 001 100
111111110 100
111 111 101 000

""/
""I
'" '" '" ""I
'" '" '" ''''I
'" '" ""' 'I
""" ""'"I
'" '" """I
"'/
'" ""/

100 100010000

00 all

000 000 001 100
111111110 100
111111101001

001000100 000

00100

000000 001 100
111 111 110 101
111 111 101 010

010001 000 000

00101

000 000 001 100
111111110110
111 111 101 100

100 010 000 000

00 110

000 000 001 100
111 111 111 000
111 111 110 001

000 100 000 000

00 111

000000 001 100
111111111101
111111111010

001000000000

01000

000000001 100
000 000 000 11 a
000 000 001 100

010000 000 001

01001

000 000 001 100
111 111 111 111
111 111 111 111

100 000 000 011

01010

'" '" '"

n' '" '"

Ac -+ADDERS (M010;eM011)

AC ~ ADDERS (MalO = Mall)
MOO~ACll (Mall =1)

'" '" '"

000 000 001 100
000 000 001 011
000 000 010110

000000 000 110

01011
AC-+ADDERS (M010;eMOll)

'" '"

000 000 001 100
111111110101
111 111 110 101

'" '" '" '''I

000 000 001 100
000 000 000 00 1
000 000 000 00 1

000 000 001 100

01 100

000 000 00 1 100

01 101

SinceSC = 158 , MalO = 0, and Mall = 0;
MO plus AC -+ AC
(D ivide Correction).
NO SHIFT

Figure 1-17 Divide Example - Divides 221s by 148

1-18

Thirteen divide steps take place (the first step tests for divide overflow; the next twelve steps determine the
quotient). A final remainder correction step is made as the CPU is restarted and the Link is cleared. For the
correction step, the left-shift signals are all negated. If M010 = 1, the last regular divide step was a subtract. The
AC is in complemented form before the correction step; hence DATA F must be grounded to re-complement the
AC to its true form as a part of the correction process. If MOll =0, the divisor must be added to the remainder
(this is the correction step mentioned in the first part of this section).
Figure 1-17 shows an example of the division process.

SECTION 4 DETAILED LOGIC
1.19 EAE INSTRUCTION DECODING LOGIC
The EAE instruction decoding logic consists of the EAE Instruction Register (E I R), the MODE flip-flop, and
ROM 1 and ROM 2. The decoding logic recognizes EAE commands from the processor and interprets them in
terms of EAE instructions.
1.19_' EIR Register
The EIR Register (Figure l-lS) comprises 12 D-type flip-flops (IC 74H74). It is loaded at TP2 of the FETCH
major state with the 12 Memory Data bits (MDO-ll) and provides outputs of EI R N(l) or EI R N(O), where N
corresponds to the EIR bit designation. The most active EIR bits correspond to bits MD7-10 and playa dominant role in the EAE coding scheme. If the system is about to answer an interrupt and is not doing a data break,
all flip-flops are cleared at TP4. Otherwise, the flip-flops are cleared at TPl of FETCH.
1.19.2 MODE Flip-Flop Logic
The MODE flip-flop (Figure 1-19) comprises one J-K flip-flop (lC 74Hl06) which responds to SWAB and SWBA
instructions. Two modes of operation were designed into the EAE to accommodate the user having programs
that were written for a PDP-SII or to accommodate the new user. Mode A corresponds to the PDP-SII type software; Mode B corresponds to the new instructions that are provided. The EAE always starts in Mode A. The
MODE flip-flop allows the programmer to switch modes at his convenience. The flip-flop is clocked at the trailing edge of TP2 whenever the basic EAE instruction in a FETCH state is decoded.
1.19.3 ROM Logic
The ROM logic (Figure 1-20) consists of two ICs, each containing a 32 S-bit word capability and selected by the
combination of 5 inputs.
Figures 1-21 and 1-22 illustrate ROM operation. ROM 1 is enabled during either a FETCH or EXECUTE cycle,
when an EAE instruction has been decoded and the instruction is not a mode-swapping instruction. ROM 2 is
enabled during a FETCH cycle, when an EAE instruction has been decoded and the instruction is not a modeswapping instruction. Each EAE instruction can be easily traced to eight output ROM signals, each representing
a specific command to somewhere in the EAE logic. An indication of what each output is doing and where it is
going can be seen at the bottom of each matrix. For the purpose of ROM decoding a 0 can be considered active
and function as a 1 in normal logic terminology. For example, ROM 26 L causes an MA plus 1 to the MA. The
specific EAE instructions causing this ROM instruction can be seen on the matrix.

1-19

EIRO

EIRI

EIR2

EIR3

MDO

MDl

MD2

MD3

MD4

EIR9

EIRS

EIR7

TP2

EIR4

EIR5

MD5

CLOCK EIR

FETCH L

EIR10

+3V

'"
0

MOIl

MDW

MD7

MD6

TP1-------------4
FETCH L
INT IN PROG H---------,
TP4

O--EIR

MA,MS
LOAD CaNT L
SE - 0457

Figure 1-18 E I R Register and Controls

MODE B H

EIR4 (0) - - - - - - - 4
EIR5 (0) - - - - - - - 4

INIT H

EIRS (1) - - - - - - - L _
7447

EIR7 (0) - - - - - - - 4
EIRS ( O ) - - - - - - - r EIR9 (\) - - - - - - - 1
EIR10 (\) - - - - - - - 1
EIR4 (0)
EIR5 (0)

SWBA L

EIRS (0)
7431

EIR7 (1)
EIRS (1)
EIR9 (0)
EIRIO (0)

EAE

INST{:~:: :;;--------1
EIR3 (1) - - - - - - - - - - - 1

CLOCK MODE F/F

EIR11 ( 1 ) - - - - - - - 1

FETCH L

8E-0438

Figure 1-19 MODE Flip-Flop Logic

1.20 EAE TIMING LOGIC
The EAE timing logic is illustrated in Figure 1-23. The components consist of six D-type flip-flops, TG1 through
TG4, an E SYNC flip-flop, and an EAE ON flip-flop, plus a variety of control and input gates. Flip-flops TG 1
through TG4 are configured as a switch-tail ring counter. TG2( 1), TG3( 1) and TG4(0) are used to clock major
events in the EAE logic. For example, TG2(1) Land TG3(1) L are combined to form ETP (EAE Time Pulse),
which is the primary clock pulse to step the Step Counter and load registers.
The length of the switch-tail ring counter is controlled by ROM 12 L, which indicates whether an add (and
possibly a shift) or merely a shift operation is taking place. If adds are taking place, the EAE Timing Generator
must run at a slower rate to allow time for carries to propagate in the adders of the M8300 Major Registers Module.
If ROM 12 L is high, TG 1 is disabled and TG4 shifts (complemented) into TG2. Six clock pulses are required to
complete the timing generator cycle; hence, ETPs are 300 ns from leading edge to leading edge. If ROM 12 Lis
low, TG1 is in the Shift Register. The ETPs are then 400 ns from leading edge to leading edge.
1.20.1

EAE Timing Generator Timing Diagram

A timing diagram (Figure 1-24) relates the transition from processor timing to EAE timing. The signal NOT LAST
XF E R L, which is grounded when the processor is to stop, is not shown on the diagram (refer to Paragraph 1.25
for information on the EAE start/stop logic). NOT LAST XFER L is asserted at TP2D; at the leading edge of

1-21

TP3, processor timing halts. The EAE Timing Generator operation begins on the leading edge of TP3, which dc
sets the E SYNC flip·flop. EAE timing begins when flip·flop EAE ON is set; the timing chain is started on the
next 20·MHz clock input from the processor timing generator. The first ETP occurs when TG4 is set and TG2
is reset.
ETP occurs once every 300 ns or 400 ns (depending upon ROM 12 L) and continues as long as LAST STEP, or
SHIFT OK, or DCM + DPIC is not low. Anyone of these signals will cause a 0 to be clocked into the E SYNC
flip-flop, thus beginning a series of events that ends the EAE timing and restarts the processor timing.
Each time an ETP is generated by timing, the Step Counter is stepped one more time until the total number of
shifts have been completed.

E
FETCH
EIRO(O - " " " 1 - _
EIRI (0
EIR2 (1)
EIR3( I)
EI Rl1( 1) - - ' " " ' -

SWBA l
SWAB l
15

EA E INSTRUCT

ROM 11 l
Yl
ROM 12 l
Y2

EIRO (I)
MOOE B - r - L -__

NEW
INSTRUCT H

ROM 13 l
Y3

ROM 14 l
Y4

EIR8 (1)

EIR9 (I)

EIR10(1)

ROM 1
Y5

ROM 15 l
ROM 16 l

ADlK DIS l
ROM 17 l

Y7
Y8
FETCH l

SWAB l
SWBA l

--"'---

ROM 18 l

15
Yl

ROM 21 l
ROM 22 l

Y2
MODE (0)

EIR6 (1)

ROM 23 l
Y3
ROM 24 l
Y4

EIR8(1)

EIR9 (1)

EIRIO (I)

ROM 2

ROM 25 l
Y5
ROM 26 l
Y6
ROM 27 l
Y7

F D SET l
ROM 28 l

FE SET l
BE·044Q

Figure 1-20 ROM Logic

1.21

EAE SOURCE CONTROL SIGNALS

EAE demands on the processor are more extensive than most other options. Data can be selected from the AC,
MO, MD, MB, PC or from the CPMA Register. How the data is selected and its source are illustrated in Figure
1-25. The AC or the MO can be applied to one set of adder inputs via the DATA BUS. The MD, MO, PC, or
the CPMA Register can be applied to the second set of adder inputs.

1-22

FUNCTION

Y.3

V.4

OCTAL

III
82
83

F' NOP
F· (ACS + SCL
F· MUY
F' DVI

1
1
1
1

1
1

1
1
1
1

377
377
311
377.

B4
B5
116
117

F· NMI
F' SHL
F' ASR
F· LSR

1
1
1
1

1
1

1
1
1
1

1
1
1

1
0
0

1
1
1

143
377
171
311

lB
11
12
13

F' SCA
F' DAD
F' DST
NDP

1
1
1
1

377
371
377
377

15
16
17

F·DPSl
F· DPIC
F' DCM
F· SAM

1
1
1
1

0
0

1
1
1
1

377
231
231
331

211
21

E· NOP
E • SCL
E· MUY
E· DV I

1
1
1
1

1
1

1
1
1
0

1
1

Q
0

1
1
1
1

377
376
267
241

NOT USED
E· SHL
E . ASR
E • LSR

1
1

1
1
1

NOT USED
E· DAD
E ·DST
NOT USED

1
1

118

22
23

25
26
27

30
31
32
33
34
35

36
37

1
0

1
1
0

0
1

1
1

0
0

1.
1
1

1
1
1

1
1

0
1
1

1
1
1

U
0
0

142
366
366

1
1

X
331
377
X

X
0

NOT USED
NOT USED
NOT USED
NOT USED

X
X
X

;::
LL

:>:

...I

tt:
w

U)
~

c
c

C
C

""
z:

...I

...~
<.>

c
en
w
~
c
<.>

'"
...I

cD
~

w
~
c

c.»...

.:.J

;1'"

.... co

c>
tt:
wtt:
-'c

Q..<.>

'"'"

<.>

>
tt:
tt:
c

<.>

tt:
w

Q..

z:
'"
~

""z:
...I

:>:

...I

'"<.>Q..

tt:
w

C
C

w
~
c
u

...

....

...

....

!!:

...I

ROM 1 Instructions

1-23

'"Q..
~
~

C
C

'"
""z:
:::;
...I

<.>

'"
Figure 1-21

:Z
>
tt:
tt:~
cc

..,w
c

Q..
~

<.>
U)

c
co

...I
U)

<.>

...

....

FUNCT ION

OCTAL

NOP
ACS
NEW MUY
NEW DYI

1
0
1
1

1
1
1
1

1
1
0
0

1
1
1
1

1
1
0
0

t
1
I
1

377
177
331
331

NMI
SHL
ASR
LSR

1
1
1
1

0
1
1
1

1
1
1
1

1
0
0
0

1
1
1
1

1
0
0
0

337
372
J72
J72

SCA
DAD
DST
NOP

1
1
1
1

0
1
1
1

1
0
0
1

1
1
1
1

367
J71
371
377

DPSZ
DPIC
DCM
SAM

1
1

1
1
1
1

1
1
1

1
1
1
1

1
1

1
0
0
a

1
1
1
1

J57
277
277
277

Nap
SCL
OLD MUY
OLD DYI

1
1
1
1

1
1
a
0

1
1
1
1

1
a
a

377
J72
332
332

NMI
SHL
ASR
LSR

1
1
1
1

1
1
1

0
1
1
1

1
1
1
1

1
1
1

1
1
1
1

1
a
0
0

337
372
372
372

SCA
SCA·SCL
seA. OLD MUY
SCA.OLD DYI

1
1
1

1
1

a
0

1
0
a
0

1
1
1

0
0

0
0
a
0

1
1
1(

367
362
322
322

SCA· NMI
SCA • SHL
SCA· ASR
SCA· LSR

1
1
1
I

0
0
0
a

1
0
0
0

1
1
1

1
0
0

I
1

0
1
1
1

1
1
1

1
1

1
1
1
1

a
U

1
0

327
362
J62
362

D'"'

.'" .. ""

e.:>

D-

I-

1
.
..
.
. .. .. . . . . ..
V)

'-'

'"'-'c

l'.,.

UJ
l-

UJ
I-

'-'

'-'
c

til

a..

lUJ

IUJ

t:3

'-'
V)

::E

UJ
l-

UJ
I-

UJ
l-

UJ
I-

UJ
l-

UJ
I-

'-'
c

'-'

'-'
c

'-'

.,.

Figure 1-22

'"z
.,.

ROM 2 Instructions

1-24

EAE TG START H
TP3

DCM+DPIC L
LAST STEP L
SHIFT OK H

~----------------1D

EAE
ON

E
SYNC
}-_<.......> - - - - - - - - - - I C

EAE ON (t)

E SYNC (0)

EAE ON (0)

INITIALIZE
TP3

+3V

c.:n

ROM 12 L

+3V

EAE ON

+3V

EAE ON(1l
ROM 12 L

(1)

CLOCK

TG4(O)
8(-0447

Figure 1-23 EAE Timing Logic

LAST STEP L

RESTART L

TP3 H _ _--J

E SYNC (1) _ _- - '

EAE ON (1) _ _ _ _ _- - J

TGl (1) _ _ _ _ _ _ _.....

TG2 (1) _ _ _ _ _ _ _ _- - '

I
I
TG3 (1) _ _ _ _ _ _ _ _ _ _ _

TG4 (1) _______________

I
I

~.,..(I----....

'1
I

ETP _ _ _ _~---~-------~

I
I
I

PROCESSOR
TIMING
HAl.TS

EAE
TIMING
BEGINS

400ns
I

lsI. ETP

I
2nd ETP

LAST ETP
8E -0448

Figure 1-24 EAE Timing Generator Timing Diagram

ADDER
OUTPUT MUX

ADDERS

DATA T
ENO

DATA F

EN1
EN2
DATA BUS

AC-BUS
MQ-BUS

8E-0450

Figure 1-25 Source Control Data Path, Simplified Block Diagram

1.21.1

The processor register selection logic is illustrated in Figure 1-26. Signals ENO, EN 1, and EN2 determine what
data will pass through the Register Input Multiplexer. The data that is selected is illustrated by the decoding
scheme shown in Table 1-2.
Table 1-2
Register Select Decoding Scheme
ENO

EN1

EN2

low

. low

low

PC Register (not selected
by KE8-E)

low

high

MD Lines

low

high

low

MQ Register

low

high

CPMA Register

NOTE
When EN1 is grounded by EAE, gating within the
MB310 Major Registers Control automatically grounds
ENO. Thus, the EAE need only ground EN1 to select
MD to the adders.

1-27

r~;:; ~I~ ~'~-l
8235
E20
12

MD DISABLE
ENl
DCA·E.TS2

DST+DAD

II
I
I

I
L _______ ~J
3

EIR10 (1)
8235
E20

DAD+DST L

E
BTS3
+3V

MOll L
NORMAL DVI

DVI
BTS3

LAST DVI

ENl

LAST STEP L

MOll L 5

ROM 12 L
EAE ON (0)

MUY. EAE ON L

ROM 15 L

NOTE
NEXT LOC H

MS, IR DIS
ENO

TS4

I>"''--~- EN 2

+3V
EIR10 (1)
EIR9 (1)

SAM L
8235 Logic Summory:
If pin 7 is low, the A inputs
ore inverted and connected to
the outputs. If pin 9 is low,

ROM 22 L

the B inputs ore connected to
the outputs. Outputs are

TS3 L

open- collector.
8E-0453

Figure 1-26 Processor Register Selection Logic

1-28

1.21.2 Data Line Enable Signals
As illustrated in Figure 1·25, signals AC -* BUS and MO -* BUS are used to gate either the contents of the AC
Register or the MO Register to the DATA BUS. The generation of these two signals is shown in Figure 1-27.
Signal AC -* BUS occurs during all shift instructions, including MUY and DVI, as dictated by signal ROM 15 L
during TS3. Signal MO -* BUS is asserted by E and NEW INSTR. E and NEW INSTR also generate AC -* MO
ENA L. This arrangement automatically transfers the contents of the MO Register to the DATA BUS and the
contents of the AC Register to the MO. The DAD and DST instructions follow this procedure. There are other
times (DCM and DPIC) when MO -* BUS and AC -* MO L are asserted, but these situations are handled in the
M8310 by the MOA and MOL bits (refer to Volume 1).

MQ--BU5 L

NOTE

8T53

NEW INST H
E

T53:
ROM 15 L

I -~-----AC--8U5
----------=L>

8235

LogIc Summary:

If pin 7 is low, the A inputs
are inverted and connected to

the Qut.puts. I f pin 9 is low,
the B Inputs are connected to
the outputs. Outputs are

open - collector.
8E-0437

Figure '-27

Data Line Enable Signals

1.21.3 Data Enable Signals
Signals DATA T and DATA F allow data to move from the DAT A BUS to the adders. The type of data being
applied to the adders is illustrated in Table 1-3.
Table '-3
EAE Combinations of DATA T and DATA F
Signal

Type of Data Applied to Adders

DATAT

DATA F

low

Complement of contents of DATA BUS

low

high

Contents of DATA BUS

high

low*

Zero

"DATA F is grounded by a gate in the M8310 Register Control if DATA T is high.

1-29

The data usually placed on the OAT A BUS by the EAE option will be the contents of the AC Register or the
MO Register. Signals DATA T and DATA F can be asserted by either the Major Registers Control logic or the
EAE data control logic (Figure 1-28). Signal DATA T is brought low during TS2 when a DAD + DST instruction
is being executed during an EXECUTE cycle. However, DATA T is also brought low during TS3 of all EAE cycles,
as described in Paragraph 3.35.3 of Volume 1.
DATA F is pulled low by a SAM, DCM, or DPIC instruction during TS3. During a normal DVI, DATA F is low
if M010 and M011 are alike. During the last divide step (the correction step), LAST STEP L tests M010 for a 1.

8235

E20
EIR10(IlH

b-----<~ DATA T

DAD+DST L
E

liN 'Me31O Re:G~CONTROL
I
I IOT+ OPR
I

BTS3

I
I
I
I

L ________ --1
NOTE:
6

M011 L

b-----<~ DATA F

B235

E27
MOW L
7

NORMAL DVI

BTS3 --1--4>-1"-"'"
D~

b------------~

LAST STEP L
8235 Logic Summary:
I f pin 7 is low, the A inputs
ore inverted and connected to

ROM 22 L

the outputs. If pin 9 is low,

the B inputs ore connected to
the outputs. Outputs are

TS3 L

open- collector.

ON FOR SAM OR DCM
BE-0435

Figure 1-28 EAE Data Control Logic for Processor Data Control Gates

1.22 EAE ROUTE CONTROL SIGNALS
The EAE route control signals control shifting right, shifting left, carry in, and carry out. These elements are
represented in the simplified block diagram given in Figure 1-29.
1.22.1 Step Counter Loading and Control Logic
The Step Counter loading and control logic is illustrated in Figure 1-30. The logic controls loading, reading, and
incrementing the Step Counter.

1-30

MAJOR REGI STER BUS

LINK LOAD
LI NK DATA

AD LK DIS
AD LK

ADDER OUTPUT
MU LTI PLEXER

RIGHT
LEFT

------1L--CS:;:Hj"jI~FTT--1L_
CONTROL

SHIFT OK
L_O_Gr-1C_ _-,

r----------:__

LAST
STEP
CARRY OUT

~-'_-r_,-~~--------------:L__C_~_~_~_~_C_IN_~~ LINK
DATA BUS 4 - - - . . . . 1

EAE TIMING

MD
BUS
ADDER II
RIGHT L
SHL+ LD ENA
AC- MQ ENA L - - - - - - '
MAJOR REGISTER

BUS
BE - 0436

Figure 1-29 EAE Route Control Signal Block Diagram

TP2 0
SC LOAD L

ROM 18 L

CO L

TP3

>--- DATA -

TP3~ O--SC

SC H

ROM 21 L

ROM 23 L

TG3(1)~

ETP

SHIFT OK

ROM 15 L ... ~ SHIFTS

--v---

D-

+l--SC L

TG2 ( I ) - - < L J
T S 3 = D - SC-DATA H
ROM 25 L
BE-0432

Figure '-30 Step Counter Loading and Control Logic

Two sources of data (the AC and MD) can be loaded into the SC by two different instructions. If the last five bits
of the AC are to be loaded into the Step Counter, the ACS instruction generates ROM 21 L, which sets the DATA
XFER flip-flop at TP2. Because ACS is a Mode B instruction, MODE B H and DATA XFER (1) H generate CO L
and DATA XFE R (1) asserts SC LOAD L. Signal CO L is used to clear the AC Register at the same time the SC
is loaded. Signal DATA -+ SC H is used to gate the contents of the DATA BUS to the Step Counter. At TP3,
DATA XF E R is cleared and the SC is loaded.
If an SCL, SHL, ASR, or LSR instruction is decoded and the major state is EXECUTE, ROM 18 L is asserted. At
TP2D, SC LOAD L is asserted, which causes the complement of the last five MD bits to be loaded into the Step
Counter. Signal +1 -+ SC L is generated at EAE Timing Pulse (ETP) time by SH I FT OK H and ROM 15 L.
ROM 15 L is decoded when a shift operation is to take place.
When it is desired to load the AC Register with the contents of the Step Counter, instruction SCA asserts ROM 25 L.
During TS3 L, SC -+ DATA H is asserted, gating the contents of the Step Counter to the DATA BUS.
1.22.2 Step Counter Logic
The Step Counter logic is illustrated in Figure 1-31. IC 8266 transmits the complement of DATA 7 through 11
and the uncomplemented MD bits. When signal DATA -+ SC goes high, the DATA BUS bits (low for 1) are applied to the Step Counter (high for 1). Otherwise, bits MD7-11 (low for 1) will be complemented and applied to
the Step Counter (high for 1). The Step Counter loads the contents of the four input lines when SC LOAD L is
received and increments when it receives the signal +1 -+ SC L. The Step Counter is IC 74193. It is usually used
to count up to zero. When the count reaches 0, signal SC = 0 L is asserted.
Signal LAST STEP L is generated when SC = 13 8 during an MUL, when SC = 148 during a DVI, and when
SC = 37 for all operations.

1-32

SCO

MD7

SC2

4
74193

3
3

SC1

SC~O L

DATA
+3V
+5V

SC-DATA

DATA 7

12
9

DATA 8

SC1

DATA 9
SCO
SC2

1
2
13

LAST
STEP
L

12
DATA 10

SC1
SC3
SC4

3
5
4

DIV 12 L

13
DATA 11
1411

SC LOAD L
O---SC

DATA-SC H

8E-0439

Figure 1-31

EAE Step Counter

1.22.3 Shift Right/Shift Left Control Logic
The shift right/shift left control logic is illustrated in Figure 1-32. The 8235 I Cs are multiplexers that receive
select signals at pins 7 or 9 to select signals being received at pins 1,2,10, or 14. LEFT L is enabled during an
SHL, NORMALIZE, or DVI instruction. The shift-right (ASR or LSR) and multiply instructions cause RIGHT L
to be asserted.
1.22.4 Shift OK Logic
The shift OK logic (F igure 1-33) monitors the contents of the AC and MQ during the NM I instruction and checks
for LAST STEP L. When LAST STEP L becomes low during an SHL, LSR, or ASR instruction, SC =37. If the
MODE flip-flop is set, indicating the new or Mode B instruction set is in use, SH I FT OK H is grounded to prevent
the last shift from occurring. During an NMI instruction, SHIFT OK H is grounded when the number becomes
normalized, to prevent an extra shift from taking place as the processor is restarted.
1.22.5 EAE Carry In Logic
Signal CARRY IN L is developed by the EAE under the conditions shown in Figure 1-34. ROM output, ROM 22 L
is decoded when an SAM, DCM, or DPIC instruction is to be performed. If the EAE is off (SAM or Step 1 of
DPIC and DCM) CARRY IN L is generated. ROM 13 L controls the coupling of carries, and introduces a CARRY
IN L if the Link is set during Step 2 of DPIC and OeM and the two EXECUTE cycles of the DAD instruction.

LEFT L

ROM 14 L

ROM 15 L
EAE ON L

8235
E27

ROM 14 L ~...----.....
ROM 12 L - " " ' - _ . /

r--------------4

BTS3
LAST STEP L -,---~

NOTE:
12

DIV 10
DIV.LAST STEP 7

3 RIGHT L
8235
E31
EAE ON L
ROM 15 L

ROM 14 L

8235 Logic Summary:
If pin 7 is low, the A inputs
ore inverted and connected to

ROM 12 L

MUY·EAE ON L

the outputs. If pin 9 is law,
the B inputs ore connected to
the outputs. Outputs are
open - collector.
8E- 0434

Figure 1-32 EAE Shift Right/Shift Left Control Logic

1-34

ACI-'..-------....

(AC2-"=0)'MQ=0

AC4-11 =0

NEW H - - - - - ,

SHIFT OK H

LAST STEP L

NORMS+SHL+ASR+LSR

NORMS+SHL+ASR+LSR - - - - - - '
F

NEW H - I -.......
CO

* Low only for NMI instruction.
8E- 0433

Figure 1-33 Shift OK Logic

ROM 13 L
LINK
ROM 22 L
TS3 L

CARRY IN
EAE ON (0)

NEXT LOC H
MS,IRDIS

BE-0455

Figure 1-34 EAE Carry In Logic

1,22.6 MO Register Shift Left Logic
The MO Register shift left logic is illustrated in Figure 1-35. Decoded outputs ROM 14 L and ROM 15 L, with
EAE, select such signals as SH I FT OK H and CAR RY OUT L, etc. Signal MO DATA L provides quotient information to MOll during a divide. Otherwise, MO DATA L remains high, shifting zero into M01l for NMI and
SH L instructions. Signal SH L + LD EN L forces the MO Register to shift one place to the left. Also shown with
this logic is the DIV LINK and other gating required to generate the quotient bit.
1.22.7 AC to MO Transfer Signals
Figure 1-36 illustrates the conditions when the signal AC ~ MO ENA L can be asserted. This gating is used during
the DAD and DST instruction as a part of the AC ~ MO swapping process. AC ~ MO ENA L is also generated for
the DPIC and DCM instructions in the M8310, as described in Volume 1, Paragraph 3.40.
1.23 DESTINATION CONTROL SIGNALS
The signals that actually cause register loading are called destination control signals. In the case of the EAE, only
the AC LOAD Land MO LOAD L signals are developed in the EAE logic. Other loading signals, including MB
LOAD L, are asserted by the processor. Figure 1-37 illustrates how the AC, MO, and MB Register loading signals
are generated.

1-35

ROM 14 L
ROM 12 L

NOTE:

DIV
LINK

AC LOAD L

+3V

SHL + LD
EN L

SC=O L
MO

MO 10 L - ' - L _ - '

DATA L
ROM 14 L

ROM 12 L
8235 Logic Summary'

If pin 7 is low, the A inputs
ROM 15 L
EAE
ON (0)--'"

Ore inverted and connected to
the outputs. I f pin 9 is low,
the B inputs ore connected to
the outputs. Outputs are
open - collector.

(SHL+NORMS)"EAE ON
8E-044\

Figure 1-35 MO Register Shift Left Logic

DAD+DSTL~
E L~

AC--MOENAL
8E-0456

Figure 1-36 AC-"" MO TRANSFER Signal

8235

E27

NOTE

ROM 14 L
ROM 12 L

E L
DAD + DST L

TG2 (1)

SHIFT OK H

TG4(O)

r-----------,
8235 Logic Summary'

II BTP2 -yv--___ ~__ MB LOAD L II

If pin 7 is low, the A inputs
are inverted and connected to
the outputs. I f pin 9 is low,
the B inputs are connected to
the outputs. Outputs are
open-collector.

L _________ -1
PART OF PROCESSOR

8E- 0449

Figure 1-37 Destination Control Logic

1-36

1.24 EAE START/STOP LOGIC
The EAE start/stop logic, shown in Figure 1-38, transfers timing generation from the CPU to the EAE. Up to TP3
of certain EAE cycles the generation of all timing signals is under CPU control. At TP3, timing control can be
transferred to the EAE to allow high-speed multiple shifts and/or adds. At the conclusion of these special operations, timing is returned to the CPU.
The EAE grounds OMNIBUS signal NOT LAST XFER L before TP3 when the current instruction and major state
requires running the EAE timing chain. The N LX flip-flop is clocked 100 ns after the trailing edge of TP2, after
the ROMs and associated decoding have had ample time to settle. If the 0 input to N LX is high, one of the following instructions has been decoded; the major state is the one in which the EAE operation is to take place.
Instructions which start the EAE Timing Chain:
ASR, LSR, SHL, NMI, MUY, DVI, DPIC, DCM
The output of the NLX flip-flop is applied to one input of a two-input NAND gate (labeled A in Figure 1-38)
whose output grounds NOT LAST XFER L. At the same time, the other input of gate A is high, unless a Divide
Overflow situation is detected by gate B. If NOT LAST XFER L is low at the leading edge of TP3, CPU timing
is interrupted as described in Volume 1, Paragraph 3.21. EAE TG START H is ANDed with TP3 and the result
used to set the E SYNC flip-flop. At the trailing edge of TP3, the EAE ON flip-flop is clocked and sets. The EAE's
timing chain is now running.
The EAE continues to run until some condition within the EAE causes EAE STOP H to go high. At the leading
edge of the next ETP, E SYNC clears. At the trailing edge of the same ETP, EAE ON clears and stops the EAE.
Signal RESTART L has the same effect on the Timing Generator of the CPU (but not the Major Registers) as does
,

BUS STROBE L - it starts the CPU if NOT LAST XFER L is high. RESTART L is generated twice, once when
the EAE starts (it has no effect then), and once when the EAE stops. NOT LAST XFER L is high by the time
the second RESTART L signal is generated, because N LX is cleared by one of the EAE's timing generator flipflops (TG2) a short time after the trailing edge of TP3 and well before the leading edge of the first ETP.

1.25 EXTENDED EAE LOGIC
The extended EAE logic (Figure 1-39) consists of a D-type flip-flop called EX 1 and its associated logic. When set,
EX1 forces a second EXECUTE cycle and causes the processor to access the next sequential memory location.
Signal NEXT LOC H is used to generate CARRY IN L and to ground EXO, which causes MA + 1 to the MA
Register.
The logic gating for the EX1 data input is limited to either a DAD or DST instruction. DAD, DST, MUY, and
DVI are the only EAE instructions that enter a DEFER cycle. For both MUYand DVI instructions, EIR6(1) is
low and, therefore, prevents the EX1 flip-flop from being set.

1.26 EAE LINK CONTROL LOGIC
The EAE link control logic (Figure 1-40) contains all of the Link Control elements required to load the Link and
to disable the Link so that it is not affected by certain processor-EAE operations. For a better understanding of
Link operation within the processor, refer to Volume 1, Paragraph 3.39.

1-37

DCM+DPIC L----------------------------~._~
ROM 15 L ---------------------------<1

+3V

TP2

TP2 D

/-------1 D

D
DLY 1

DLY 2

NOT LAST TRANSFER L

NLX

OI--.......---iC

CLOCK

TP1------------------------------~--~

TG2(1)----------------------------~

+5V

)0----'

EAE TG START

OCM + DPIC L
ROM 15 L
DVI--~-

et,RRY OUT L
E SYNC (O)----.__~
L,~ST
DCM +DPIC
STEP

BTP3---*------------f-----,

....

L-============~--

S HI FT OK H

------------------------<1

EAE STOP H

D-[>--RESTART L

I----+---+----j D
EAE
ON
R

I N I TI A L I ZE ---------------------------1
ETP------------------------------------~~-----------'
SE-0454

Figure 1-38 EAE Start/Stop Logic

E L

F E SET

NEXT LOC H

INIT H
T P 4 - - ' -......

p-------'-----~

MA, MS, LC

MODE B H
EIR6 (1)

EIRO (1)
EIR1 (1)

EIR2
EI R3 (1)
( --0..____

DAD+DST

EAE INSTRUCT

EIR11(1l
8E- 0452

Figure 1-39 Extended EAE Logic

Signal LI NK DATAL provides information to be loaded into the Link by the LI NK LOAD L pulse. This information may be one of the following:
Enable

Result if Link Loaded

Used By

None

Zero

DVI (to clear overflow
indication) MUY, LSR,
DAD

ROM 11 L

Carry from adders

DAD, DPIC, DCM

ROM 13 L

AGO

ASR, NMI

DVI EAE ON (0)

One

DVI (to anticipate
overflow)

The LI NK LOAD L signal is generated at TP3 if ROM 17 is low (usually to preset the Link) and at ETP time during left shifts. During the execution of DVI, the Link is set at TP3 (for possible overflow indication) and cleared
if the DVI process reaches LAST STEP L (meaning a legal divide has occurred). During the right shift and MUY
instructions, the Link is not modified.
During left shifts, data is introduced from MOO to AC11 via a line called AD LK L. During SH Lor NM I instructions, MOO is gated directly to AD LK L. For DV I, MOO is sometimes inverted before being applied to AD LK L.
The gating logic, which depends on M011 and whether the first divide step has taken place (EAE ON), is also
shown in Figure 1-40.
The AD LK DIS L signal disables the normal Link gating described in Volume 1, Paragraph 3.39. AD LK DIS L
must be low any time the LINK LOAD L/L1NK DATA L inputs are used or whenever left shifts are performed
in order to avoid conflict with the normal link gating. This line is grounded by ROM 16 L.
1_27 EAE SKIP LOGIC AND GT FLAG
The EAE skip logic is illustrated in Figure 1-41. There are two methods of generating a SK I P L signal. Signal
NEXT LOC H, which is generated by the extended EAE logic, is inverted and applied to the SKIP L line. Signal
NEXT LOC H also generates CARRY IN L.
1-39

CARRY OUT L
ROM 11 L
ROM 13 L

1I N K
DATA L

ROM 12 L
ROM 14 L

AD LK
MOll L

ROM 15 L
EAE ON (0)
NOTE

TP3

ROM 17 L

LAST STEP L

EIR3 (1)
EIR2 (1) -..,...

LINK LOAD

LAST DVI L
~

8235 Logic Summary'
ADLK

DISL

If pin 7 is low, the A inputs
Ore inverted and connected to

ROM 16

the outputs. If pin 9 is low,
the 8 inputs are connected to

the oulputs. Outputs are
open-collector.

ROM 1
BE-0451

Figure 1-40 EAE Link Control

MOO
MO>AC
ROM 24 L

ACO
SGT L

+3V

T P3

-..-----+---l

NEXT
LOC H

y.--......-

SKIP L

NOTE·

MOO

ACO
RTF

EIR3( I)
EIR2(1 )

.-----"Nv- +5V

SAM L
ROM 22 L
TS3 L -.....

--'

8235
E31
8235 Logic Summary'

M011 L

If pin 7 is low, the A inputs
ore inverted and connected to
EAE ON (0)

the outputs. If pin 9 is low,
the 8 inputs ore connected to
the outputs. Outputs ore

ROM 15 L
(ASR +LSR) ·EAE ON L

Figure 1-41

open- collectol'.

EAE Skip Logic

The SKIP line is also grounded when a DPSZ instruction is being performed. This instruction tests the AC and
the MO for O. If both registers equal zero, the SKIP L signal will be asserted. SKIP L is used to set the SKIP
flip-flop in the processor's logic at TP3. For information on the processor's skip logic, refer to Volume 1, Paragraph 3.38.
The more complex part of the skip logic involves the Greater Than (GT) flag. When the GT flip-flop is set, instruction SGT forces the SK IP line to go low. The GT flag can be changed by one of three methods:
Source of Information

Method
RTF instruction

DATA 1

SAM instruction

Set if MO greater than or equal to AC;
cleared otherwise.

ASR or LSR

Previous M011

The GT flag is cleared if the EAE is in Mode A; hence, the flag is active only for Mode B instructions.

SECTION 5 MAINTENANCE
Since the EAE is physically connected to the Central Processor Timing Generator and OMNIBUS, a definite
possibility exists that some EAE malfunctions will not be caused by the EAE modules. For this reason, the following procedure is suggested.
Step

Procedure
Remove MS340 and MS341 from the OMNIBUS.

Perform processor-related diagnostics to ensure processor reliability.

Insert MS340 in OMNIBUS and connect it to the Timing Generator via the "J" top
connector.

Perform PDP-S/E Instruction Tests 1 and 2.

Insert MS341 in OMNIBUS and connect it to M8340 connector H.

Perform PDP-S/E Instruction Tests 1 and 2.

Connect MS341 to M8310 via "F" connector.

Perform PDP-S/E Instruction Tests 1 and 2.
NOTE
If problems are encountered during this procedure,
they can be isolated by troubleshooting the processor, and tracing the malfunction back to the last module or connector that was added to the system.
When this procedure fails to isoiate a malfunction,
perform EAE Instruction Tests 1 and 2, and the EAE
Extended Memory Test. One of these tests should
give some idea of the problem.
Once the problem is pinpointed, write and toggle in a
simple program using the malfunctioning instruction.

1-42

The following basic ideas can be built upon or modified to suit any special purpose:
1.

Mode Changing Instructions
0/

7431

SWAB

7447

SWBA
JMPO

5000
2.

SCL or ACS (dependent on mode)
Mode A
0/

7604

ModeB

3003

LAS
DCA.+2

7403

SCL

7403

ACS

XXXX

OPERAND

5001

JMP .-2

5000

JMPO

7431
7604

SWAB
LAS

SCA or SCA, C LA
Mode A
0/

7604

LAS

3003

DCA .+2

7403

SCL

XXXX

OPERAND

74410r
7641

SCA or SCA, CLA

7000 }

5 or 6 NO OPS WI LL HOLD THE AC

7~00

FOR OBSERVATION

5000

JMP 0
ModeB

7431

SWAB

7604
7403

LAS
ACS

7441 or
7641

SCA or SCA, CLA

7000 }
NO OPS TO HOLD AC FOR OBSERVATION

.j.

7000
5001
4.

JMP 1

SH L Shift Left
Mode A
0/

7604

LAS (Shift Count =one more than the last five bits of the location following SH L)

3006

DCA

1050

TADMO

7421

MOL
(continued on next page)

1-43

1051

TAD AC

7413

SHL

XXXX

SHIFT COUNT

7~00 }
'"

NO OPS WI LL HOLD AC AND MO FOR OBSERVATION

7000
7621

CAM

5000

JMP 0
ModeB

7604

LAS (Shift Count = last five bits of location following SHL)

3007

DCA

7431

SWAB

1050

TAD MO

7421

MOL

1051

TADAC

7413

SHL

XXXX

SHIFT COUNT

7~O } NO OPS WILL HOLD AC AND MO FOR OBSERVATION
7000

7621

CAM

5001

JMP1

NMI
0/

7431

SWAB (Start here if Mode B)

1050

TAD MO (Start here if Mode A)

7421

MOL

1051

TAD AC

7411

NMI

7~OO }

HOLDS AC AND MO FOR OBSERVATION

7000
5001
6.

ASR or LSR
0/

7604

LAS (Shift Count = One more than this number in location following ASR or LSR
if Mode A)

3007

DCA (Shift Count = Number in location following ASR or LSR if Mode B)

7431

SWAB (Start here if Mode B)
TAD MO (Start here if Mode A)

1050
7421

~v1QL

1051

TAD AC

7415 or
7417

ASR or LSR

XXXX

SHIFT COUNT
(continued on next page)

1-44

:000 }
NO OPS TO HOLD AC AND MO FOR OBSERVATION

7000
5000
7.

MUY
Mode A
0/

LAS (Multiplier)

7406
3006

DCA

1050

TAD MO

7421
1051

MOL
TAD AC

7405

MULTIPLY

XXXX

MULTIPLIER

7~00 } HOLD AC AND MO FOR OBSERVATION
7000
JMP

5000

ModeB
0/

7431

SWAB

7604

LAS (Multiplier)

3100

DCA 100

1050

TAD MO

7421

MOL

1051

TADAC

7405

MULTIPLY

100

ADDRESS OF MULTIPLIER

7~0 } HOLD AC AND MO FOR OBSERVATION
7000
JMP

5000

DVI
Mode A
0/

7604

LAS (Divisor)

3006

DCA

1050

TAD MO

7421

MOL

1051

TAD AC

7407

DVI

xxx x

DIVISOR

7~00 }

HOLD AC AND MO FOR OBSERVATION

7000
5000

JMP
(continued on next page)

1-45

ModeS
0/

7431
7604

LAS (Divisor)

3100

DCA 100

1050

TADMO

7421
1051

TADAC

7407

DIVIDE

100

ADDRESS OF DIVISOR

7~}

HOLD AC AND MO FOR OBSERVATION

MOL

7000
5001

JMP

SAM
0/

7431

SWAB

1050

TAD MO

7421

MOL

1051

TADAC

7457

SAM

7000 }
t

HOLD AC, MO AND STATUS FOR OBSERVATION

7000
5001
10.

JMP

DAD or DLD
0/

7431

SWAB

1050

TADMO

7421

MOL

1051

TADAC

7443 or
7763

DAD or DLD

XXXX

ADDRESS OF WORD

7~0 }

HOLD AC AND MO FOR OBSERVATION

7000
5001
11.

CONFIGURE AC AND MO

DST
0/

7431

SWAB

7445

DST

100

LOCATION OF WORD

7763

DLD

100

7~00 } HOLD AC AND MO FOR OBSERVATION
7000

(continued on next page)

5001
1-46

12.

DPIC
0/

13.

SWAB

7573

DPIC

5001

JMP

7431

SWAB

DCM
0/

14.

7431

1050

TADMO

7421

MOL

1051

TADAC

7575

DCM

1051

TAD Original AC

7440

SZA

7402

HLT

7521

SWP

1050

TAD Original MO

7440

SZA

7402

HLT

7621
5001

CAM
JMP

DPSZ
0/

7431

SWAB

7621

CAM

7451

DPSZ

7402

HLT

5001

JMP

The programs listed above, when used in conjunction with the flowchart, ROM encoding matrix, and print set,
provide simple, repetitive troubleshooting instructions.
Use the following check list as a guideline.

Instruction was properly loaded into the Op-decoder.

ROM address is correct.

ROM outputs are correct.

Step Counter decodes last step properly.

Control and loading signals listed on the flow chart are occurring at the correct time in relation to
time states and bit configurations.

SECTION 6 SPARE PARTS
Table 1-4 lists recommended spare parts for the KE8-E. These parts can be obtained from a local DEC office or
from DEC, Maynard, Massachusetts.

1-47

Table 1-4
Recommended KE8-E Spare Parts
DEC Part No.

Description

19-05585
19-05576
19-09955
19-10018
19-09934
19-09267
19-05635
19-05586
19-09486
19-09004
19-09667
19-09059
19-09973
19-09485
23-001A1
23-002A1
19-09930
19-09705
19-05515
19-07686
19-09062
19-10011 .
19-09935
13-00295
13-00365
13-00317
10-00067
10-01610

IC DEC 7476
IC DEC 7410
IC DEC 7412
IC DEC 74193
IC DEC 8266
IC DEC 74H11
IC DEC 74H20
IC DEC 74H40
IC DEC 384
IC DEC 7402
IC DEC 74H74
IC DEC 74H30
IC DEC 97401
IC DEC 380
IC Encoded ROM (Drives ROM 11-18)
IC Encoded ROM (Drives ROM 21-28)
IC DEC 7405
IC DEC 8881
IC DEC 7400
IC DEC 7404
IC DEC 74H53
IC DEC 7486
IC DEC 8235
Resistor 330n 1/4W, 5%
Resistor 1 K, 1/4W, 5%
Resistor 470n, 1/4W, 10%
Capacitor 6.8 /IF, 5V, 20% Solid Tantalum
Capacitor 0.01 /IF, 100V, 20% Ceramic Disk

1-48

Quantity

PART 2
MEMORY EQUIPMENT OPTIONS

CHAPTER 1
MRS-F 1K PROM

SECTION 1 INTRODUCTION
The MRS-F is a memory option for the PDP-S/E, PDP-S/F, and PDP-S/M computers. There are four versions of
the MRS-F. The MRS-FA is a 256 word (12-bit words) PROM. The MRS-FB is a 1K word (12-bit words) Reprogrammable Read-Only Memory (PROM) with 256 words of Random Access Read/Write Memory (RAM).
The MRS-FC is a 1 K word (12 bits) PROM only and the MRS-FD is a 512 word (12 bit) PROM only. These two
versions are identical to the MRS-FA except for the larger PROM capacity. The following descriptions of the
MRS-FA are the same for the MRS-FC and D.
The M RS-F has a switch (SW) start capability such that a program can be started using SW on the operator's or
programmer's console.
From a programming point of view, the MRS-F is addressed in the same manner as core memory (Paragraph 3.2.4
Volume 1). The MRS-FA is organized as 400 s words (256 10 words) of Reprogrammable Read-Only Memory.
The MRS-FA can be located starting at the beginning of any even numbered page in any field, such as OOOOs,
0400 s ,or 0600 s ' Note that the corresponding memory locations cannot be used by core memory while the
MRS-FA is installed in the OMNIBUS. When a memory location assigned to the MRS-FA is addressed, ROM
ADDR L is asserted to disable core memory.
The M RS-FB is organized as 2000 s words (1024 10 words) of PROM and 400 s (256 10 ) words of RAM. It is addressed the same way as the MRS-FA and core memory, although the PROM is a 13-bit memory. The 13th bit
of PROM may be set to logical 1 when M RS-FB is programmed to allow the program to address a word in the
Read/Write memory. When the 13th bit of PROM is a 1, the S least significant bits of the PROM output are the
address lines of the 256 RAM locations. During a Read access the S least significant bits are treated as an operand
to point to a Read/Write location in RAM. This allows the programmer to use instructions that require a Write
operation, Le., JMS, DCA, and ISZ. It does not mean that the MRS-FB is a 2400sword memory, it still has only
2000s words. Each time a R/W (RAM) Location is used, it takes one PROM Location to address it.
The MRS-FB does not pull ROM ADDR L, so it must be assigned addresses that are not assigned to core memory.
The M RS-FB operates from the OMN I BUS like any other PDP-S/E memory. The 256 words of Read/Write memory are spread throughout the 1 K of PROM memory where they are needed. All or none of the 256 words of
Read/Write memory may be used.

1.1 PHYSICAL DESCRIPTION
The MRS-F consists of the MS349 Quad Module which plugs into the OMNIBUS. The MS349 contains address
select diodes which can be arranged to select different addresses for the MRS-F. This allows the system fo be
expanded by the addition of other MS349 modules, up to a maximum of four MR8-FBs in a system. This maximum is due to the high +5V current (3.8A) of the MRS-FB.

1-1

There are. tabs on the MS349 module for the application of +5V from a battery power supply to the bipolar
read/write chips during an ac power loss. This prevents the loss of their contents during an ac power failure. If
the battery supply is not used, jumper the normal +5V to the read/write chips.
1.1.1 MR8-F Specifications
The following is a list of MRS-F specifications:
Characteristics

Specification

Power Requirements

MRS-FA +5V @ 1.64A -15V @ 100 mA
MRS-FB +5V@3.SA-15V @350mA
MRS-FC +5V @ 1.S4A -15V @300 mA
MRS-FD +5V @ 1.69A -15V @ 150 mA

Memory Cycle Time

2.4 ps fast cycle; 2.6 ps slow cycle

PROM Erasure Method

Ultraviolet Light (Note warning on Page 1-13).

PROM Programming Method

By external programmer

Memory Capacity
MRS-FA

256 words of ROM

MRS-FB

1K of PROM with 256 words of Read/Write Memory (RAM)

MRS-FC

1K word 2-bit PROM only

MRS-FD

512 word 12-bit PROM only

Temperature

0° to 55°C (standard computer environment)

Prerequ isites

The new MS347 Memory Timing Module is required as it pulls
the STALL line and interrupts the normal timing sequence.
STALL is pulled for about 1.2 ps to allow time to access PROM
. and time for data to settle on the MD lines.

Testing

The diagnostic is supplied to check the PROM after it has been
programmed.

1.1.2 Documentation
The following documents are necessary for the operation, installation, and maintenance of this option:

PDP-S/E and PDP-S/M Computer Handbook - DEC 1973

PDP-S/E/F/M Maintenance Manual - Volume 1

Introduction to Programming - 1972

DEC Engineering Drawing MS349-0-0

MRS-F PROM Diagnostic, MAINDEC-SE-DHMRC-D

MRS-F PROM Utility Programmer, MAINDEC-08-DHMRD

MRS-F Program Format Description, DEC-OS-OMRAA-A-D

1-2

SECTION 2 INSTALLATION AND ACCEPTANCE TEST
The M RS-F is installed on site by DEC Field Service personnel. The customer should not attempt to unpack,
inspect, install, or service the M RS-F.

1.2 INSTALLATION REQUIREMENTS
Primary requirements for installation of the MRS-F are:

A Teletype@ programmer's console and at least 4K of Read/Write Memory must be available to run
the MRS-F diagnostics.

MRS-F diagnostics and documents must be available to check the MRS-F.

The PDP-S/E timing board MS330 installed in the system must be REV E or later.

The paper tape used to program the PROM must be available to run the diagnostic.

1.2.1 Installation
Perform the following to install the M RS- F:
Step

Procedure
Ensure PDP-S/E power is off.

Ensure all of the hardware on the shipping list is included in the shipment.

Ensure proper diodes are installed in the MS349 module to select the starting address
for the 1 K PROM or 256-word ROM (drawing CS-MS349-0-0).

If this module is to use SW Start, ensure the jumpers are installed to select the starting
address (drawing CS-MS349-0-0). and that SW DIS jumper is in. If SW Start is not to
be used, then SW DIS jumper should be removed.

If this is a 256-word ROM (M RS-FA). ensure Y A 1 and Y A2 jumpers are installed.

Insert the MS349 module in the OMNIBUS (Table 2-3 of the PDP-8/E/F/M Maintenance
Manual, Volume 1) and install the top connectors (HS511). If an MS330 module is
installed, remove the M8330 module and install the MS349 module in its place.

Ensure the MS330, timing board installed on the OMNIBUS is REV C or higher.

1.2.2 Acceptance Test
Run MAINDEC-SE-DHMRC-PB to check the MRS-FA or MRS-FB. Instructions for running the diagnostic are
included in the document with the paper tape. The diagnostic checks the contents of PROM against the program
tape used to program the MRS-F, exerc:ises the Read/Write locations in RAM to ensure there is no interaction
between them, and ensures that the RAM reads and writes correctly.
NOTE
The MR8-FA or B PROM must be programmed at DEC before it is shipped or the customer must obtain a Programmer
(MR8-SL) to program the MR8-F. In either case, the tape usecl
to program PROM must be available to run the diagnostic.

@teletype is a registered trademark of Teletype Corporation.

1-3

SECTION 3 MRS-F DESCRIPTION AND ADDRESSING

1.3 MRS-F DESCRIPTION
Figure 1-1 is a block diagram of the MRS-F. The functional groups of logic shown in Figure 1-1 are discussed in
the following paragraphs.

1.3.1 Address Decoder
The Address Decoder contains address select diodes that can be arranged to assign a 2000s block of addresses to
the M RS-FB or 400s block of address to the MRS·FA. When the MA lines (MA OO-MA 03 are applied to the
select diodes in the correct order, MCl FIELD l is asserted to indicate that the MRS-F is selected by the progran
Also included is the Field Selection Decoder, which, by using three jumpers, selects the field where the PROM
program will run.

1.3.2 Starting Address Decoder
The Starting Address Decoder is used to start a program whose starting address is location OOOs or 200 8 of any
1 K memory in any memory field when SW on the console is pressed.

1.3.3 Memory Control and Timing logic
The Memory Control logic generates the necessary control signals to initialize the CPU and start a program at the
specified starting address during SW operation. It also produces the timing signals required for the memory
operation.

1.3.3.1 SW Start - When SW is pressed, the PROM initializes the CPU, loads a starting address, selects a memor'
field, and starts the program at the address and field specified by the Starting Address Decoder. Figure 1-2 is a
timing diagram for the SW start operation. The M RS-F signal used in this and other timing diagrams are explaine
in Section 4. The standard OMNI BUS signals are defined in Table 1-1. When SW is pressed, the PROM must:

Initialize the CPU.

load the starting address of the program, determined by jumpers (ST AD) on the board.

load Extended Address (Memory Field), determined by jumpers (EMA) on the board. The instructior
and Data Fields are connected together so both are enabled with one jumper.

Program is started.

The SW feature may be used only on one MRS-F and only if another option that uses SW Start is not installed
on the OMNIBUS, the SW function is selected by the installation of a jumper in the Memory Control logic of
the MS349 (DIS).

1.3.3.2 Read or Read/Write - During a Read operation the contents of the PROM memory location addressed
by the program are applied to the MD lines to be read into the processor. The timing diagram in Figure 1-3 assumes that the 13th bit is 0 and the contents of the addressed PROM location are applied to the MD lines.

1-4

ROM04 - ROM 11

ROM
ROM ADDRESS

r----..

MCl FIELD

RAM
ADDRESS ROM04-ROM 11
ENABLE
(RAM ADDRESS)
RAM WRT EN

**
0
M
N
I
B
U
S

ROM
ADDRESS
FLAG

TP3

WRITE
DECODER

r--

(WRITE)

256 WORD RANDOM
ACCESS MEMORY (RAM)
READ/WRITE

MCl FIELD

MD DIR l
MDOO - MDll

(READ)

.--

RAMOO-RAMII
DATA
MUlTIPlEXER

DATA 0, DATAl, DATA4, AND DATA6-DATA 11 (ADDRESS)
lATCH

* SW START SIGNALS
EMAOEMA2
MAOOMA02

FIELD
AND
ADDRESS
DECODER

LATCH
PULSE
MCl
FIELD

e-------

POWER OK H
RUN H

MEMORY CONTROlW
lOGIC
MCl ENABLE
(1) STAll DELAY

START ADDRESS

(2)lATCH DELAY
(3)SW START
lOGIC DELAYS
TO GENERATE
PROCESSOR
CONTROL
SIGNALS

MCl ENABLE
EMA

MEMORY
FIELD
AND
STARTING
ADDRESS
SELECT

...

-ROM

ROMOO-ROMll

'---

1K WORD REPROGRAMMABlE
READ ONLY MEMORY
(PROM)

f----

SW
INIT

DIS0

MA04- MAll

STAll

13BIT PROM

13BIT=1

4 TO 1
MULTIPLEX
SELECT

BMA02 - BMA03

* The SW slarl signals are PULSE LA, MEM START,
MS, DIS, lA EN, KEY CONT. These signals are
.. planed in TABLE 9-4 of Ihe SMALL COMPUTER
HANDBOOK -1972

** This signal isused only on MRS-FA
8E-0697

Figure 1-1 MRS-F Block Diagram

SW START

DL1~1

~Ij
PWR OK H

jNIT~l
GO

DLY 2

EN ST ADD

INDI LA EN
MS IR DIS

In
I

1'1

IJ
I

I~
I

III

DLY 3

DLY 4

PULSE LA H

II
Ii

EN EMA

n -LDMA

n - L D EMA

(

Lr
I
I

I j

MEM START

RUN

K CONT L

{ (

l j

8E-0692

Figure 1-2 SW Start Timing

1-6

READ

MEM ST/TP4

((

~IJ
TPl

TP2

f(
)J

TP3

((

n
~

RETURN

1.21"S
STALL

1. 351"S
MCL LATCH

H
Ii
MEM TO MD

ROM OATA

READ FROM RAM

ROM L

RAM DATA

U
8E-0695

Figure 1-3 Read Timing

When the 13th bit is a 1, the 8 least significant bits (04-11 of the PROM output) are used as an address rather
than an operand to point to a Read/Write location in the 256-word RAM. Figure 1-4 shows the timing required
for this operation. Whether a Read or Write operation will take place is determined by the operand in the RAM
location addressed by PROM or by an operand in PROM that writes in this location.

1.3.4 1K PROM
Figure 1-5 is a block diagram of the 1 K PROM. Only 400 s locations or 256 10 words are shown in the diagram.
A 256-word, 12-bit PROM (12 X 256 ROM matrix) is formed by one 256 10 word, 8-bit ROM and half of one
256 word, 8-bit ROM. Using six ROM chips in this way produces 1024 10 or 2000s12-bit words of PROM. This
is done by selecting one chip and either the upper or lower half of another chip for each read operation (Figure
1-6). As an example, if memory location 0000 is selected, E26 and the lower half of E50 are enabled.

1-7

R/W

13th BIT

MEMSTITP4U

TPI

TP2

----------\\r\----------------~r-l~-----------

TP3 _______________

~(~\------------------------------------------~r---l~------'1\

RETURN

STALL
1.35
MCL LATCH L

ROM DATA

',',

_ _ _

-----Ilj~

Ij~~

ROM L

_ _ _- - - - - - - -

'l,
MEM TO MD

RAM MD DIR

'll
MB TO MD

RAM WRT ENL

RAM DATA
8E-0694

Figure 1-4 13th Bit Read/write Timing (Slow Cycle)

..
MA 11 L

ifciM

* 3072

BMA02 BMA03
MA 04 L

13th
BIT
PROM
(l024Xll

INPUT
DRIVERS

BIT
PROM
MATRIX
(256XI2)

ADDRESS
DECODER

OUTPUT
BUFFERS

ROM OO-ROM 11

*THE 3072 BIT ROM MATRIX IS COMPRISED OF ONE BX256,0 ROM MATRIX AND HALF
OF ANOTHER BX 256,0 ROM MATRIX.1K OF PROM IS COMPOSED OF SIX ROM
MATRICES FOR 1024 ,0 12 BIT WORDS AND ONE ROM MATRIX FOR· THE 13th BIT.
BE-0693

Figure 1-5 PROM Block Diagram

1-8

12 BIT
MEMORY A6DRESS

1
ADDR

~ 400-777
E42

ADDR
0-377
E20

ADDR
400-717
E26

ADDR
1000-1377
E32

ADDR
1400-1771
E38

ADDR

~ 1400-1777
E50

-----

- - --~

ADDR
0-377

ADDR

~ 1000-1377

4 MOST
SIGNIFICANT
BITS
8 LEAST
SIGNIFICANT
BITS

8 LEAST
SIGNIFICANT
BITS

4 MOST
SIGNIFICANT
BITS

4M OST
SIGNIFICANT
BITS
4 MOST
SIGNIFICANT
BITS
8E-OG96

Figure 1-6 PROM Addressing Scheme

1.3.5 13th Bit PROM
The 13th bit PROM chip contains an additional bit for each of the 20008 locations in PROM. If this bit is set to
1, the contents of the PROM location addressed by the program are used to select a location in Read/Write
Memory. This allows the program to use instructions that require a Write operation which is not possible in
straight ROM memories. The 13th bit is not seen by the processor or program.
1.3.6 ROM Address Flag
The ROM Address flag is enabled by the installation of a jumper (YA 1) on the M8349 module for the M RS·FA.
This allows ROM ADDR L to be applied to the OMNIBUS when the 256-word ROM is addressed and disables
core memory. Signal ROM ADDR L is required because the MRS-FA uses 4008 locations which overlay core
memory.
1.3.7 Read/Write Memory (RAM)
The RAM is composed of twelve 256 X 1 bit chips. When the 13th bit of PROM is set, the 8 least significant bits
of PROM in that location are used to address the RAM. The contents of RAM are then applied to the MD lines
instead of PROM. The output of RAM is selected when ROM L is made true by the 13th bi~.
To write in a RAM location that is addressed by the eight least significant bits of PROM, RAM MD DI R H must
be asserted to generate a WRITE EN. If WRITE EN L is asserted, data on the MD lines is written into the RAM
location addressed by PROM, at TP3 time.
1.3.8 Data Multiplexer
The Data MUltiplexer selects either ROM DO-ROM 11 or RAM ~O-RAM 11 to be applied to the MD lines during
a Read operation. ROM L is asserted if the 13th bit is a 1 to select RAM 00- RAM 11. I f the 13th bit is 0,
ROM L is negated and ROM DO-ROM 11 is applied to the MD lines.

1·9

Table 1-1
MRS-F Signals

Signal

Description

DlY 1

D l Y 1 (Delay 1) is a one-shot multivibrator that outputs a 1.2 J.l.S
pulse when SW on the programmer's console is pressed and raised.
This signal sets the MCl GO flip-flop and pulls PWR OK low to start
the timing and generation of CPU signals required to load the starting address and memory field from the Starting Address Decoder.

DlY 2

Dl Y 2 (Delay 2) is a one-shot multivibrator that outputs a 100 ns
pulse on the trailing edge of IN IT H when MCl GO is set (1). This
pulse sets MCl lA, clears MCl KC, and triggers Dl Y 3 on the trailing edge. This enables the following signals to be applied to the
OMNIBUS.
MS IR DIS l
lA EN L
IND 1 l
KEY CaNT l
Then MC lEN ST AD DR H is asserted to apply the starting address
to the OMNIBUS.

DlY 3

Dl Y 3 (Delay 3) is a one-shot multivibrator that is triggered by the
trailing edge of Dl Y 2 to generate a 250 ns pulse. The O-side of Dl Y
3 is applied to Dl Y 4, which is triggered on the trailing edge of this
pulse. This is used to separate the setting of levels from the pulse that
loads these levels into the processor.

DlY4

Dl Y 4 (Delay 4) is a one-shot multivibrator that is triggered on the
trailing edge of Dl Y 3. This delay, along with Dl Y 3, is triggered
three times in the timing cycle. Twice Dl Y 4 produces PU lSE lA l
and the last time it produces MEM START L.

EN EMA H

EN EMA H (Enable EMA) is asserted at DlY 3 time when MCl GO (1),
MCl KC (1), and MCl lA (1) are asserted. This puts the field select
bits on the Data Bus, so that at the next PU lSE lA, it is strobed into
the processor.

EN ST ADDR H

EN ST ADDR H (Enable Starting Address) is asserted at DLY 2 time
when MCl GO (1), MCl KC (0), and MCl lA (1) are asserted. This
puts the starting address on the Data Bus, so that at the next PU lSE
lA, it is strobed into the processor.

INIT*

INIT (Initialize) is asserted if PWR OK H is asserted to clear all flags,
the AC, and the interrupt and break systems.

IND 1*

IND 1 is asserted low at the same time as lA EN l to ensure that only
the data lines are on the Data Bus when the starting address is transferred during SVJ operations.

KEY CaNT l*

KEY CaNT l is asserted by the M RS-F to generate STOP, enable
loading of the EMA, reset the RUN flip-flop, and disable the interrupt
system.

1-10

Table 1-1

(Cont)

MRS-F Signals
Signal

Description

MCl GO H

The MCl GO flip-flop is set by a Dl Y 1 pulse when SW on the console
is pressed and raised. This signal enables the gates required to apply
starting address, memory field, and CPU ~control signals to the OMN IBUS.

MCl lATCH P l

MCl lATCH P l is a 1.35 /1S pulse asserted by WRITE H and RETURN
H to clock ROM DO-ROM 11 or RAM ~O-RAM 11 out of the Data
Multiplexer and onto the MD lines during a Read operation.

MEM START l*

MEM START l is grounded prior to TP2 time to initiate a memory
cycle. Memory cycles are continued until STOP is set.

PULSE lA H*

PULSE lA H is asserted twice during an SW operation to transfer the
contents of the Data Bus to the CPMA Register. The Data Bus contains
the starting address one time and the EMA bits the other time.

PWR OK H

PWR OK H (Power OK) is negated (low) if the power supply output
drops below a predetermined level to initialize and stop the processor.
In the MR8-F PWR OK H is negated during an SW operation to initialize
the CPU.

RAM ~O-RAM 11

RAM ~O-RAM 11 is the 12-bit output of the Read/Write Memory
which is addressed by a location in PROM and applied to the MD lines
if the 13th bit at that location in PROM is set.

ROM DO-ROM 11

ROM DO-ROM 11 is the 12-bit output of PROM when a memory location in PROM is addressed by the program. I f the 13th bit is set to 1,
ROM 04-ROM 11 are used to address a location in RAM.

RAM MD DIR H

RAM MD DIR H is asserted by MO DIR l from the OMNIBUS to
generate RAM WRT EN. RAM WRT EN is applied to the RAM chips
to enable data on the MD lines to be written into RAM.

RAM WRT EN

RAM WRT EN l is asserted to enable the write input to all RAM chips
during a Write operation. This signal is controlled by RAM MD DIR l
whose state is determined by MD 01 R l from the OMN I BUS, and by
TP3*.

RETURN H*

RETURN H is asserted during a Read or Write operation. It is used in
the MR8-F during the read part of a cycle to trigger the MCl lATCH P L
and STALL one-shot multivibrators.

ROM ADDR l

ROM ADD R l is asserted to disable core memory when the 256 word
ROM in the MR8-FA is addressed.

ROj\;; l

ROM L is the output of the 13th bit multiplexer. It is used to select
which output (ROM DO-ROM 11 or RAM ~O-RAM 11) is to be put
on the MD lines. It also enables RAM for a Write operation.

STAll l

STALL L is asserted for 1.2/15 to allow time for access to PROM memory and for data to settle on the MD lines.

1-11

Table 1·1 (Cont)
MR8·F Signals
Signal
SW*

Description
SW is asserted (low) when SW on the console is pressed to start the
timing sequence to load the starting address. Note the SW DIS jumper
must be installed to use this feature with the MR8·F. SW must be
pressed, then raised, to start the SW start timing cycle.

"These signals are defined in detail in Chapter 9 of the Small Computer Handbook - DEC. 1972. The descriptions here apply only
to the MR8·F.

1.4 PROGRAMMING
The PROM chip is an ultraviolet (UV) erasable device. Seven PROMs are needed to accomplish the 1 K X 12 plus
1 K X 1 bit storage. The programming pulses needed are of high (35-48V) amplitude. To isolate these from the
TTL logic, all pins of the PROM chips are brought out to top fingers on the 1·side of the module. The TTL levels
associated with the normal PROM functions are brought to the corresponding fingers on the 2-side. In normal
operation, single-width top connectors join the 1-side to the 2-side of the module. To program the PROM, the
top connectors are removed and four cables are connected to the fingers instead. These cables make contact with
the 1-side only and are interlocked to prevent application of destructive voltages if the cables are plugged in incorrectly.
The PROM, when received from the factory or erased, contains all as. When programming the PROM, you insert
a 1 where it is needed. The a can be put in only by erasing the whole PROM; you cannot put a a into the PROM
using the programmer. The PROM is reprogrammable a minimum of 100 times.
A normal problem with read-only memories is that codes must be specially written to avoid instructions that require a Write operation (i.e., JMS, DCA, and ISZ) and the placing of variable locations in R/W memory. In this
PROM, that restriction is removed if the total number of alterable locations in a piece of core is 256 or less. This
is done by making the PROM a 13-bit memory. On a read access, if the 13th bit is a 1, the least significant 8 bits
stored in the ROM are treated as an address, rather than an operand, and point to a read/write location. The 1K
of P ROM are treated as an address, rather than an operand, and point to a read/write location. The 1 K of PROM
provides 256 of these locations.
By checking a program as it is written, it is possible to tag all operands that may be changed in the course of
execution and then to modify the program controlling the PROM programmer to set the 13th bit for this address
and place the next available RAM address in this location. Thus, whenever this location in PROM is accessed, the
actual data will be read from or written into the corresponding RAM location.
Programming Sequence
210/
211/
212/
213/
214/

TAD CONST
DCA TEM
ISZ CNTR
TAD TEM
JMS SUBR

1-12

Octal Codes for Program
210/
11/
12/
13/
14/

01254
03361
02255
01361
04300

254/
255/
361/

0010
10001
10002

/CONST ANT 10
/POINTS TO RAM LOCATION 1
/POINTS TO RAM LOCATION 2

300/

10003

/POINTS TO RAM LOCATION 3 FOR RETURN ADDRESS STORAGE

After PROM is programmed, it must be checked using the MRS-F diagnostic and the tape used to program the
PROM. PROM is read and compared with the program tape. The Read/Write locations specified by the 13th bit
are exercised to determine if they read and write correctly.
The rules for programming and generating paper tapes to program the M RS-F are given in the MR8-F Program
Format Description (DEC-OS-OMRAA-A-D).

1.4.1 PROM Erasing Procedure
The PROM chips may be erased by exposure to high intensity, short wave, ultraviolet light at a wave length of
2537 A. The recommended integrated dose (i.e., UV intensity X exposure time) is 6W sec/cm 2 • The ultraviolet
lamps should be used without short wave filters and the PROM should be placed about one inch away from the
lamp tube to be erased. This operation has the effect of writing all Os into the PROM. A UV Lamp (ModelS-52)
and UV Contrast Safety Goggles (Model UVC·303) can be purchased from ULTRA-VIOLET PRODUCTS, INC.
San Gabriel, California 9177S.
WARNING
Short wave ultraviolet light can cause "Sunburning" of the
eyes and skin. Eyes should be protected from exposure.

SECTION 4 DETAILED LOGIC DESCRIPTION
1.5 INTRODUCTION
The M RS-F logic is divided into functional groups for discussion purposes. The block diagram, Figure 1-1, should
be used to understand the interaction of the logic, the signal flow within the module, and the input or output
signals.
1.5.1 Address Decoder
Figure 1-7 shows the Address Decoder logic. The address assigned to the M RS-F is selected by cutting out one
of the diodes on each address bit. As an example, if the address assigned to the M RS-F requires EMA 2 L to be 1,
diode 03 is taken out, so that when EMA 2 L is a 1, E24 and E 17 do not ground the base of 01. When the correct combination of 1s and Os (the address of the MRS-F) are applied to the Address Decoder logic, the base of
01 is positive and E9 is enabled to assert MCL FI E LD Hand MCL FIELD L. This enables the memory address
bits (MA 04-MA 11) to be applied to the 1 K PROM chips and select a PROM memory location. This also enables the 13th bit decoder to determine if the 13th bit at that memory.location is a 1.

1-13

+5V

EMA

o l

06 1
05 0

EMA 1 l

09 1
0100

EMA 2 l

04 1
03 0

MA 00 l

011 1
012 0

MA 01 l

07 1
08 0
Mel B MA02 H

MA 02 l

02 1
01 0
Mel B MA03 H

MA 03 l

014 1

+5V

013 0

Mel FIElO l

8E-06878

Figure 1-7 Address Decoder Logic

1.5.2 Timing and Processor Control for SW Start of Memory
The logic used to initialize the processor, load the starting address and memory field, and start the program is
shown in Figure 1-8. The timing required for this operation is shown in Figure 1-2.
A SW operation timing chain is created in the MR8-F by four time-delay one-shot multivibrators designated DLY
1 through DL Y 4. The 74123 IC (Figure 1-8) consists of two one-shot multivibrators that output a pulse each
time the input is triggered. The duration of the output pulse is determined by an external resistor and capacitor.
(Refer to Appendix A of the PDP-B/E/F/M Maintenance Manual, Volume 1 for truth table, pin locator, and logic
diagram.)
If the SW DIS jumper is instaiied, the timing chain is started by SW H from the control panel when SW is pressed
and then returned to the up position. A positive-going transition on the SW line sets DL Y 1 for 1.2 J,lS. The RC
network and feedback on the input line removes switch contact bounce.

1-14

MCl
EN ST
ADDR H

+5V

MCl EN
EMA H

+5V

1
KEY
CO NT l

+5V
MCL

E29

I-f---lc

D I-.q~>r-........J......-'-,

SW DISABLE
IND t l

+5V
LA EN L

E47

E44

MS IR
DIS l

MEM
START L

PULSE
lA H

E57

L-.._ _ _ _ _ _ _ _ _ _ _ _ _ _ _......_

MCl RUN H
BE-06B8

Figure 1-8 MR8-F Timing and SW Operation Control Logic

PWR OK H is negated (pulled low) shortly after the Dl Y 1 pulse is generated if the RUN ON jumper is installed
to supply a ground to E48, or if the RUN OFF jumper is installed and RUN l is negated (high), With the RUN
OFF jumper installed as shown in Figure 1-8, SW operation takes place only when the processor is not running.
If the jumper is installed in the RUN ON position, the SW operation takes place anytime SW is pressed. When
PWR OK H goes low, the processor generates a 560 ms INIT H pulse to clear the processor and options.
After the 1.2 MS Dl Y 1 times out and the 0 side goes high, it clocks the MCl GO flip-flop. MCl GO sets and
MCl GO (1) H is true. This signal enables the signals to the Starting Address and Field Select logic, as well as
most of the signals used by the processor during an SW start sequence. The timing out of Dl Y 1 also removes
the NOT PWR OK signal, allowing PWR OK to go high (true).
When INIT times out and goes low, and with MCl GO set, DlY 2 is triggered to generate a 100 ns pulse. DlY 2
on the leading edge ensures that MCl KC is 0 and it sets MCl lA to 1. With MCl lA and MCl GO set, IND 1 l,
lA EN l, and MS I R DIS l are applied to the OMNIBUS. With MCl KC cleared, MCl EN ST ADDR H becomes
true and the starting address is put on the data lines.
When D l Y 2 times out (100 ns), its trailing edge triggers D l Y 3 which produces a 250 ns pulse. This delay allows
the signals generated by the previous delay to settle on the OMNIBUS.
On the trailing edge of Dl Y 3, Dl Y 4 is triggered and it produces a 100 ns pulse. The Dl Y 4 pulse, along with
MCl lA being set, enables NAND gate, E59 and produces PULSE lA H which loads the starting address into the
processor. This pulse is fed back to Dl Y 3, MCl lA, and MCl KC. On the trailing edge of DlY 4, Dl Y 3 is
triggered and MCl KC is set. Because MCl KC was a 0, MCl lA remains set.
Now that MCl KC is set, MCl EN ST ADDR is removed and MCl EN EMA H is enabled and the field address is
applied to the OMNIBUS. KEY CONT L is also applied to the OMNIBUS.
Once again DlY 3 times out and triggers Dl Y 4. This again produces the 100 ns PULSE lA H signal, retriggers
Dl Y 3, and clears MCl lA on its trailing edge. With MCl lA removed, all signals are disabled except MEM
START.
When Dl Y 4 is triggered again by the trailing edge of Dl Y 3, the only signal generated is MEM START L. MEM
START l is applied to the OMNIBUS to start the timing chain on the timing board of the processor and the RUN
flip-flop sets. When RUN sets, MCl GO clears to disable the SW start logic. The next TP2 pulse clears MCl KC.
At this time, the program starts at the address specified by the starting address and field select logic (Figure 1-2).
1.5.3 Field and Starting Address Select logic
The Field and Starting Address Select logic is shown in Figure 1-9. This logic determines the starting address and
field in which the program that is started with the SW key resides. The starting address and field are selected by
jumpers. Removing a jumper causes a 1 to be placed onto the Data Bus; otherwise, a 0 is placed on the Data Bus.
These bits (ls or Os) are applied to the Data Bus when either MCl EN ST ADDR H or EN EMAH in the Control
logic is true (F igure 1-8) . DATA 6-8 and DATA 9-11 on the Data Bus are transferred to the I F and DF of memory extension control when PULSE lA H is asserted (Figure 1-8). DATA 00 and DATA 01 determines the lK
block of memory in which the program resides, and DATA 4 determines the starting address (000 8 or 2008 ),
1.5.4 Memory Address Control Signal Generation
The logic shown in Figure 1-10 generates MCl lATCH PULSE l, STAll l, and ROM ADDR l to control PROM
and ROM memory access.

1-16

+5V

DATA 0 L

DATA 1 L

DATA 4 L
MCL EN ST ADDR H

E56

DATA 6 L

DATA 9 L

DATA 7 L

DATA 10 L

DATA 8 L

DATA 11 L
MCL EN EMA H

E61

BE-0687A

Figure 1-9 Field and Starting Address Select Logic

1.5.4.1 MCl lATCH PULSE l - The one-shot multivibrator E21A is triggered during Read operations by
WRITE H (WRITE H is low) and RETURN H to generate a 1.35 /lS pulse called MCL LATCH PULSE L. This signal clocks the PROM/RAM Data Multiplexer into the 12-bit latch. The latch enables the selected memory output
to the MD lines via the memory buffers which are enabled by MCL FI ElD H.
1.5.4.2 STAll Dl Y - STALL DLY (E21B) is triggered at the same time as E21A to generate a 1.2 /lS pulse
which is applied to the memory timing module. STALL L increases the memory cycle by 1.2 /lS to allow for access time of PROM and time for the data on the MD lines to settle before it is transferred to the processor.
1.5.4.3 ROM ADDR - ROM ADDR is set by STALL DLY to disable core memory if the 256 word MRS-FA is
to overlay the 4008 memory locations assigned to regular core memory. The jumper on the output of the E44
NAND gate is installed in the MRS-FA and removed from the MRS-FB. The MRS-FB does not occupy memory
locations assigned to a regular core memory.
1.5.5 1K PROM Memory and Control logic
Figure 1-11 shows 4008 words of PROM, the Control logic required to read PROM, and the chip for the 13th bit
addressing. Reading of the other PROM chips is accomplished the same way as the 4008 locations show (Engineering Drawing D-CS-MS349-0-0).

1-17

WRITE H

RETURN H

+5V
MCl lATCH
o I-'-P..:.U=.:lS:..=E--=l=--(1.15U5)

MCl FIELD H
STAll l
E21B

+5V

o
(1.0U5)

ROM
ADDR
E29

TP4

8E-0686

Figure 1-10 Memory Address Control Signal Generator

The Memory Address bits (MA 04-MA 11) are applied to the address inputs of the PROM 1702A chips (Appendix A) when MCl FIELD l is asserted by the Address Decoder (Figure 1-7). Mel FIELD L is asserted when this
PROM is addressed by the program. SMA 02 and SMA 03 are applied to NAND gates E 12 where they are decoded to enable the two addressed chips to be read. As an example, if SMA 02 and SMA 03 are both Os, E 12D
is enabled and E26 and the lower half of E50 are selected. This is done by supplying a low input to CS of these
2 chips. The CS input to the 13th bit chip is grounded so this chip is read every time. The output PROM is applied to the Data Multiplexer (Figure 1-12) except when bit 13 is a 1. When bit 13 of the memory location addressed by the program is a 1, ROM Hand ROM lout of E16 are asserted. Sit 13 is a 1 when the program must
address a location in Read/Write Memory. When ROM l is asserted the eight least significant bits of PROM (ROM
4-ROM 11) are applied to the RAM chips to select a location in RAM.
1.5.6 256 Read/Write Memory and Control logic
ROM OO-ROM 11 are applied to the 74200 RAM chips (Appendix A) when ROM l is asserted. ROM l is asserted
if bit 13 is a L Mel F!ELD L is always asserted when the PROivl is addressed. ROM 04-ROM 11 selects an address in RAM and RAM OO-RAM 11 are applied to the Data Multiplexer (Figure 1-12). The timing for this operation is shown in Figure 1-4.

1-18

+5V
MCl8MA02H

M-'

MCl 8MA03H

INDICATES
MISSING lOGIC
I

VCC

V8B

ROM 00 H

SEl

-J

E12Vo--

---------

NOTE

'!'
I

VGG

I
I

MA 10 l

r =B-

1702A

VGG

-----d E 3
-

I r--

~ROMIIH

~l
STROBE

E8./

VOD

'!'

~Q2

/I
r

E8 J

CS VGG

MCl BMA03 H

~
~

74151

=8]

E16

13TH BIT

-"I

E54'\ ROM 09H

~ROMIOH

E20
1702A

=8-J

.--

VBB

VCC

----,

ROM07H

~ROMOBH

VOO

MAll L
MCl FIELD L

~ROM06H

ADDRESS
0-377

MA06 l

MA09 l

r---

VBB

E3 '\

-..-/

]

~ROM05H

E26

~ E3./

MA08 l

+5V

INDICATES
MISSIN~ lOGIC

MA05 l

MA07 l

VDD

VCC

....co

ROM 04 H
JE49./

]

+5V

ADDRESS
0-377

~ .-----l El20

MA04 l

ROM 03 H

(74157)

1702A

MCl BMA03 l

ROM 02 H
E60

E50

.-----..

ROM 01 H

ADDRESS
400-777

.--

MCl BMA02 H

~
~

NOTE
These signals are used to select
other PROM chips.

-15V

Figure 1-11 1 K PROM and Control Logic

8E-0689

MCl lATCH P l

ROM H

.. - - .... YA2

ROM 00 H
ROM 01

ROM 02

J:
SEl

MOO l

ROM 03 H
RAM 00 H
RAM 01

EI4
E6
(74157)

~
E14

~ ClK

RAM 02 H

~ f--

RAM 03 H

STB

I
ROM 04

ROM 05

ROM 06

ROM 07

RAM 04

RAM 05

RAM 06

RAM 07

lATCH
E22
(74174)

).
SEL

ClR

EI8
(74157)

+5V

ROM 09 H

!;
SEl

ROM 10 H
ROM 11

E35
(74157)

lATCH
E39
(74174)

~
~
~
E31

~
E45

MD9 l

RAM 09 H

~
rB-- ~
E45

RAM 10 H
RAM 11

~M04l
E31

E31

ClR

RAM 08 H

E31

'---- ClK

M02 l

M03 l

STB

ROM 08 H

---

H
STB

MCl FIELD H
RAM MD DIR l

E45

BE - 0690

Figure 1-12 ROM and RAM Data Multiplexer and Latch

If the instruction specifies a Write operation for RAM, MD DIR l from the OMNIBUS is negated (high) and RAM
WRT EN l is asserted at TP3 time. RAM WRT EN l is applied to the WRT input of all twelve RAM chips and the
data on the MD lines (MD OO-MD 11) is written into the RAM location selected by ROM 04-ROM 11.
The tabs shown in Figure 1-13 are used to supply +5V from a battery so that RAM will not be changed if power
fails. The jumper shown takes the +5V from the OMNIBUS to supply the RAM chips. It can be changed to use
the battery voltage if this is desired by the user.
1.5.7 ROM and RAM Data Multiplexer
The ROM and RAM Data Multiplexer is shown in Figure 1-12. The multiplexer consists of three 74157 ICs that
select either ROM aD-ROM 11 or RAM OO-RAM 11 to be applied to the MD lines. If the 13th bit is a 1, ROM H
is true (high) and RAM OD-RAM 11 are selected as an output; otherwise ROM aD-ROM 11 are selected.
The output of the Data Multiplexer is applied to a latch Register (E22 and E39) where the selected output is
clocked onto the Line Driver Buffer by MCl lATCH P l (Figure 1-10). The Line Drive Buffers are enabled by
MCl FIELD H and RAM MD DIR L. MCl FIELD H is asserted anytime this PROM is selected and RAM MD
01 R l is high during Read operations.

SECTION 5 MAINTENANCE
The general procedures concerning preventive and corrective maintenance are given in Volume 1, Chapter 4.
When a malfunction in the MRS-FA or MRS-FB is suspected, the technician should use the diagnostic programs
listed in Paragraph 1.1.2 to determine the nature of the problem. Refer to option schematic drawing
E-CS-MS349-0-0 for IC locations and pin numbers. Test points are provided on the module to facilitate troubleshooting.
NOTE
If any 1702A PROM chips are changed during a troubleshooting or maintenance operation all of PROM must
be erased and reprogrammed.

SECTION 6 SPARE PARTS
The recommended spare parts for the MRS-F are listed in Table 1-2.

SECTION 7 IC DESCRIPTIONS
1.6 IC DESCRIPTIONS
1.6.1 DEC 74157 IC Description
The DEC 74157 IC is a Data Selector Multiplexer with buffered inputs and outputs (Figure 1-14). This IC has
four 2-bit inputs, one of which is selected as an output_ The output may be read via a strobe pulse, or in the case
of the MRS-F, the strobe pulse may be grounded. When strobe is grounded the selected input is applied immediately as an output. When SELECT is high, the B inputs (1B through 4B) are selected as outputs, and when
SELECT is low, the A inputs (1A-4A) are selected as outputs.

1-21

BATTERY

11i
TT

RAM 00 H

*,I

MCL FIELD L

I
I

ROM L

If 11

£2

>--

-f

ROM 04 H
ROM 05 H
ROM 06 H
ROM 07 H
ROM 08 H
ROM 09 H
ROM 10 H
ROM 11 H

- - *- --

I
I
I
I
I
I
I
I
I
I
I

fE23

- - - -- - - -- - - -- - -- -

I
I
I

I
I
I
I

MD 05 L

I\J

RAM 11 L

-f

E25

P-Ii

=::=::::-U I

WRT

TP3

.....--

MCL FIELD H...---.

--:]E51'

MD~
E34
El

E43

E46

- - - -- - --- - - -- - --I NDICATE MISSING LOGIC

I
I
I
I
I
I

- - - -- - - --

*0 OTTED LINES USED TO

TO ROM AND
RAM MULTIPLEXER
I
I

f--

I
I

E27

-f

RAM 06 H

!
MD 00 L

+ 5V

RAM 05 H

- - --- - - -- - - -El0

SUPPLY(+ ~V)

E13 "-

RAM WRT EN L

RAM MD DIR H
RAM MD DIR L

MD 11 L
8£- 0691

Figure 1-13 RAM Memory (256 Word)

Table 1-2
MR8-F Spare Parts
DEC Part
Number

Description

11-00114

Diode, 0664

11-00113

Diode, 0662

11-09990

Diode, I N757 A

15-03100

Transistor, 3009B

15-09649

Transistor, 2N3762

15-09338

Transistor, 6531 B

19-09004

IC, 7402

19-09931

IC,74H04

19-10436

IC,74123

19-05547

IC, 7474

19-10392

IC,5380

19-10390

IC, 7380

19-05575

IC, 7400

19-09705

IC,8881

19-09267

IC,74Hll

19-10652

IC,74174

19-10655

IC,74157

19-04057

IC,74Hl0

19-10393

IC, 7384

19-10155

IC, 7408

19-09936

IC,75151

19-09056
*23-041A4

IC,74HOO
IC, 1702A (ROM)

19-10818-2

IC, 74200 or 3106 (RAM)

Quantity
2

"Must be reprogrammed when new ROM chip is installed.

In the MR8-FA, three of the ICs are connected to select either ROM OO-ROM 11 or RAM OO-RAM 11 for application to the MD lines.
1.6.2 DEC 74200 IC Description
The 74200 IC is a 256-bit active-element memory comprising a monolithic transistor-transistor logic (TTL) array
organized as 256 words of one bit each (Figure 1-15). It is fully decoded and has three gated memory-enable inputs to simplify decoding required to achieve the desired system organization. The memory-enable circuitry is
implemented with minimal delay times to compensate for added system decoding which permits the total system
read and write time to closely approach the cycle time of the 74200 IC, typically 42 ns.
The tri-state output combines the convenience of an open-collector output with the speed of a totem pole output;
it can be bus-connected to other similar outputs, yet it retains the fast rise time characteristic of the TTL totem
pole output. To minimize the possibility that two outputs at opposite logic levels are applied simultaneously to a
common bus, the output-enable circuitry is designed such that the output disable times are shorter than the output
enable times.
1-23

(2)
1A
>--,(_4)'-0 1Y

(3)

(5)

>-_(_7_).() 2Y

(6)

28
SELECT~

(11)

>-_(:.:.9:.:.).() 3 Y

(10)

GND

INPUTS OUTPUT I NPUTS OUTPUT

positive logic
Low logic level at S selects A inputs.
High logic level at S selects B inputs.

(14)
4A

BE-0702

(12)
}----04Y

(13)

FUNCTIONAL TABLE
INPUTS
STROBE

SELECT

A B

OUTPUT
Y

H
L
L
L
L

X
L
L
H
H

X
L
H
X
X

L
L
H
L
H

SELECT
STROBE
8E-0701

X
X
X
L
H

Figure 1-14 DEC 74157 IC Illustrations

Write Cycle
The complement of the information at the data input is written into the selected location when all memoryenable inputs and the write-enable input are low. While the write-enable input is low, the output is in the high
impedance state. When a number of outputs are bus-connected, this high impedance output state will neither
load nor drive the bus line, but it will allow the bus line to be driven by another active output or a passive pull-up,
if desired.
Read Cycle
The stored information (complement of information applied at the data input during the write cycle) is available
at the output when the write-enable input is high and the three memory-enable inputs are low. When anyone of
the memory-enable inputs is high, the output will be in the high impedance state.
In the MRS-F, twelve of these 256 X 1 bit chips are used as a 256 word Read/Write Memory.
1.6.3 DEC 1702A IC Description
The DEC 1702A IC (Figure 1-16) is a 256 word, S-bit, electrically programmed ROM. The 1102A is packaged in
a 24 pin package with a transparent quartz lid. The transparent quartz lid allows the user to expose the chip to
ultraviolet light and erase the bit pattern (write all Os). The erase procedure may be repeated up to 100 times
without affecting the reliability of the ROM chip.

1-24

Initially all 2048 bits of the ROM are in the 0 state (output low). Information is introduced by writing 1s in the
proper bit locations. To program these chips, word addresses are selected by the decoding logic used in a Read
operation and the eight output terminals are used as data input terminals to write the desired data word. All
eight bits of one word are programmed simultaneously by setting the desired bit information patterns on the data
input terminals. Programming (pin 13) must be low to write 1s into the chip.
The 1702A is static and requires no clock pulses. To read a memory location, the hardware need only supply the
address inputs and assert the chip-select input. A chip is selected when the CS input is low.

Up
(3)

MEMORY {MEl
ENABLE ME2
INPUTS ME3

WRITE ENABLE WE
DATA INPUT

(12)
(13)

1"":""'\

rL-J"

L f-.I

r:"'\
L f..I

rLJ
.----.'\

1"":""'\

rL--/

L oJ

~
B~

1 OF 8
DECODER

rl-/

------r \.
rl-/

r:"'\
L f..I

LI-/

r:"'\
L f..I

OUTPUT

=L)-=

r:"'\

rLJ

If[~

L oJ

rL--J

.-----..

C"'\

>------1\.
>------1\.

~
~

r:"'\
L f..I

rL-/

A ~

C~:~~.~
I

ADDRESS
INPUTS
I
I

D~
E~
F ~

G~
H~

1 OF 32
DECODER

256 BIT MEMORY
MATRIX ORGANIZED
32 BY B

I
I

I
I
I

I
I
I
I

I
I
I

8[-0698

Figure 1-15 DEC 74200 IC Illustrations (256-bit RAM) (Sheet 1 of 2)

1-25

FUNCTION TABLE
INPUTS
FUNCTION

OUTPUT

MEMORY
ENABLEt

WRITE
ENABLE

Read

Stored Data

Inhibit

High Impedance

Write
(Stor. Complement of Data)

High Impedance

H = high level
L=lowlevel
X = irrelevant
t • memory enable
L • all ME inputs low
H • on. or more ME inputs high
~

MEl

ME2

ME3

~~~

ADDRESS
INPUTS

GNO

ADDRESS
INPUT

positive logic: Data out is complement of data which was
applied at data input. See description and
function table.
8E-0699

Figure 1-15 DEC 74200 IC Illustrations (256-bit RAM) (Sheet 2 of 2)

A2
Al

VOD

Vee

*DATA OUT 1

4(LSB)

*DATA OUT 2

*DATA OUT 3

*DATA OUT 4

*DATA OUT 5

A7
VGG

*DATA OUT 6

VBS

*DATA OUT 8

lHM.B)

PROGRAM

DATA
OUTI

ADDRESS INPUTS

AO-A 7

*DATA OUT 7

Vce

BLOCK DIAGRAM

PIN NAMES

PIN CONFIGURATION

CHIP SELECT INPUT

00UT ,- DOUT 8

DATA OUTPUTS

DATA
OUT 8

*THIS PIN IS THE DATA INPUT DURING PROGRAMMING

NOTE:
Logic 1 at input and output IS
a high and logic 0 is low
8 E- 0700

Figure 1-16 DEC 1702A Ie Illustrations

1-26

CHAPTER 2
KMS-E MEMORY EXTENSION AND TIME-SHARE

SECTION 1 INTRODUCTION
The KM8-E Memory Extension and Time-Share option generates a 3-bit address for the extended memory address
lines. This address allows the use of more than 4K of memory and, when required, is used as a prerequisite in a
time-sharing system.
All logic is contained on one M837 quad-size module that plugs directly into the OMN IBUS.
All signals enter and leave the module via the OMNIBUS.

2.1

MEMORY EXTENSION DESCRIPTION

Memory extension hardware is required when more than 4K of memory is to be addressed. Except for data
break devices, the KM8-E Memory Extension is the only means by which extended memory addresses can be applied to the three extended memory address lines called EMA 0-2. Memory is divided into 4K fields, starting
with field 0, for the basic 4K memory, up to field 7, when 32K of memory is employed. Each 4K of memory receives and decodes the EMA signals. This provides the addressing capability of up to 32,768 memory locations.
There are two types of fields: the Instruction Field, which acts as an extension to the PC and direct argument
addresses; and the Data Field, which augments the address of indirectly obtained arguments. When the programmer desires to use one field for instructions and a different field for data, he directs the corresponding field address to either the Instruction Field Register or the Data Field Register contained on the KM8-E. The field addresses are applied to the EMA lines by specific instructions and conditional logic. Safeguards are provided so
that during unplanned events, such as interrupts and data breaks, no field addresses are lost. Program instructions
allow any field address to be stored; this is particularly important to the programmer desiring to nest interrupts.
A simplified block diagram showing the basi~ transfer paths dealing with memory addressing and field addressing
is shown in Figure 2-1. The KM8-E is the only route by which fields above field 0 may be selected. The only exception is the data break device that has the capability of selecting its own memory field. The programmer has
two methods of selecting memory fields. One method is via the Console Switch Register; the second method is
via an lOT instruction. In either event, field information is loaded into the appropriate register in the extension
control. The extension control automatically responds to the appropriate instructions and major states by placing
the contents of the correct field register onto the EMA lines.

2-1

FROM
DATA
BREAK

TIASMA"
v

EMA

MEMORY
EXTENSION
,~

TIMIN
G

V--

DECODER

4K MEM

EMA BITS
a t 2

FI ELD

a
a
a
a

a
a

FIELD

FI ELD

FIE LD

FIE LD 3

a
a

FIELD 4

FI ELD 5

FIELD6

FIELD 7

DATA BUS

V'--MoLIN~
PROCESSOR

TIMING

-V

MEMORY
CONTROL

-V
BE- 0315

Figure 2-1

Memory Extension, Simplified Block Diagram

2.2 TIME-SHARE DESCRIPTION
The time-share portion of the KMS-E is used only when a time-sharing system is to be employed. The KMS-E
Module contains a jumper in the inhibit logic that prevents the operation of the time-share function. Unless this
jumper is to be removed from the module, the reader need not be concerned with the time-share description in
this chapter.
The KMS-E Memory Extension and Time-Share option provides the necessary additional hardware for a generalpurpose time-share system. This option, coupled with a time-sharing program, such as TSE, and 12K to 32K of
core, allows a maximum of 16 users to independently run programs. This creates the appearance that each user
has the computer to himself.
As a system, the user can be considered operating in one of three levels: a) not logged-in level, b) monitor level,
and c) user level. A typical system is illustrated in Figure 2-2. The user interface to the system is the KLS-E
Teleprinter Control. The monitor program performs a dominant role in controlling operation between the processor and the KMS-E option and between the users and the processor.
The monitor is a complex of subprograms to coordinate the operations of various programs and user consoles.
The monitor allocates the computer's time and services to various users; it grants a slice of processing (computing)
time to each job, and schedules jobs in sequential order to make the most use of the mass-storage device. The
monitor also handles user requests for hardware operations (reader, punch, etc.), swaps (moves) programs between memory and mass storage, and manages the user's private files. Thus, the primary time-sharing capability is
provided by the system monitor and the PDP-S/E Processor. However, certain additional hardware not provided
by the PDP-8/E Processor is needed to accommodate the special requirements of time-sharing and extended ad-

dressing capability.
For more information on the monitor and user programming, refer to Chapter 10 of Introduction to Programming.

2-2

------,

PC8-E
MASS
STORAGE

---

UP TO
32 K CORE

.....

~-,....-..

KM8-E

_.L_L_
MONITOR
PROGRAM

DEVICE CODE
(40,41)

PDP-8/E

DEV ICE CODE
(42,43)

USER 3
DEVICE CODE
(44,45)

I
I
I
II

I
TIME-SHARE USERS
I
L __ ~P'::"'O~~~S~ _ _ --1

KL8-E'S

OPERATOR
(03,04)
8E-0316

Figure 2-2 Typical Time-Share System

2.3 EXTENDED MEMORY AND TIME-SHARE SUMMARY

As a memory extension control, the KM8-E provides:

Hardware to allow the programmable selection of the extended memory field (fields 1 through 7),
allowing the extended addressing capability of the processor from a basic system of 4096 addresses
to an extended memory system of up to 32,768 addresses.

Hardware to prevent an interrupt or data break from interferring with the extended addressing scheme.

Hardware to save and restore a field return address.

As a time-share control, the KM8-E provides:

Hardware to distinguish between user and monitor modes.

Hardware to trap certain instructions, causing an interrupt and placing the time-share system in monitor mode.

Ability to establish user mode.

2.4 SOFTWARE

The following programs are used in time-sharing and memory extension operations:

System Programs
1.

TSE Time-Sharing Monitor (DEC-T8-MRFB) - TSE (Time-Sharing System for the PDP-8/E
Computer) is a general-purpose, stand-alone, time-sharing system. TSE offers each of a maximum
of 16 users a comprehensive library of programs for compiling, assembling, editing, loading, saving, calling, debugging, and running user programs on-line.

2-3

Diagnostic Programs
1.

Extended Memory Address Test (MAl NDEC-SE-Dl FA) - This program tests all of memory (up
to 32K) not occupied by the program to verify that each location can be uniquely addressed.

Extended Memory Checkerboard (MAINDEC·SE-D1BA) - This program is designed to provide
worst-case half-select noise conditions to determine the operational status of core memory. The
patterns generate worst-case noise conditions in all used fields of a PDP-S/E equipped with at
least SK of core memory.

Extended Memory Control and Time-Share Test (MAINDEC-SE-Dl HA) - This program tests
the Extended Memory Control and Time-Share option logic for proper operation. The program
exercises and tests the control lOT's, time-share instruction trapping, and the ability to address
all fields, program interrupt, and auto-index.

2.5 COMPANION DOCUMENTS
The following documents and publications are necessary for the operation, installation, and maintenance of this
option:

PDP-8IE & PDP-81M Small Computer Handbook - DEC, 1972

PDP-8IE Maintenance Manual - Volume 1

Introduction to Programming - DEC, 1972

DEC engineering drawing, Memory Extension and Time-Share Option, number E-CS-M737-0-1

Extended Memory Address Test, MAINDEC-SE-Dl FA-D

Extended Memory Control and Time-Share Test, MAINDEC-SE-Dl HA-D

SECTION 2 INSTALLATION
The KMS-E Memory Extension and Time-Share option is installed on·site by DEC Field Service personnel. The
customer should not attempt to unpack, inspect, install, checkout, or service the equipment.
2.6 INSTALLATION
Perform the following procedures to install the KMS-E option:
Procedure

Step

Remove the module from the shipping container.

Inspect the module for any apparent damage.

Connect the module to a convenient OMNIBUS slot.

2.7 CHECKOUT
Perform the following procedure to checkout the Kiv18-E option;
Procedure

Step

Verify that the extended memory modules have been installed.

Verify that the corresponding jumpers have been installed to reflect the appropriate memory fields.
(continued on next page)
2-4

Step

Procedure

Perform acceptance tests provided in Volume 1, Chapter 2, Paragraph 2.3.

Load MAINDEC-8E-D1 FA, Extended Memory Address Test. This program tests all of
memory (up to 32K) not occupied by the program to verify that each location can be
addressed uniquely.

Load MAl ND EC-8E-Dl BA, Extended Memory Checkerboard. This diagnostic program
provides worst-case half-select noise conditions and verifies the operational status of core
memory.

Load MAl ND EC-8E-D1 HA, Extended Memory Control and Time-Share Test. This program tests the Extended Memory Control and Time-Share option logic for proper operation. The program exercises and tests the control lOT's time-share instruction trapping;
and, if time sharing is implemented, the ability to address all fields, program interrupt,
and auto-index.

Make entry on user's log that the acceptance test for the KM8-E option was performed
satisfactorily.

SECTION 3 PRINCIPLES OF OPERATION
2.8 INTRODUCTION
The KM8-E system description is given in terms of its functional operation. From the functional point of view,
instructions that make either the memory extension or time-share portion do something must be considered, as
well as the philosophy of why the events happen as they do. The system description, therefore, is a composite
treatment of the hardware, represented in block diagram form, and of the flow of events, represented in flow
diagram form. The events that occur in the Memory Extension and Time-Share option are considered fully; the
events within the processor are considered only partially. Such areas as major register gating and how the processor functions are completely described in Volume 1.
2.9 SYSTEM DESCRIPTION
A block diagram representing all of the functional elements of the KM8-E Memory Extension and Time-Share
option is given in Figure 2-3. The logic can be considered divided into three groups: the Control (located on the
left portion of the illustration), the Instruction Field Registers (located in the center of the illustration), and the
Data Field Registers (located in the far right of the illustration). The only interface is the OMNIBUS. All signals
entering and leaving the system, therefore, are directed from and to the OMNIBUS. Data paths between the
KM8-E and the processor are via the DATA BUS. Data is directed to the console status indicators via the DATA
BUS during TSl to tell the operator which instruction and data fields have been addressed. When the data field
and/or the instruction field are to be stored in memory, the data path is from the DATA BUS to the AC Register.
A DCA instruction is then used to store information in memory. The data paths between the processor and the
KM8-E are via the DATA BUS and MD lines.
Special inhibiting features are designed into this option. For example, during a data break operation, when some
peripheral such as a disk is being operated, control lines such as CPMA DIS prevent the transmission of data to the
EMA lines. For the case of programmed interrupts, the logic provides the means of holding an interrupt back until a CI For RMF instruction has been completely processed.

2-5

OM N I BUS

DATA 5-8

USER

MODE L

,.,
D'

(MD 2+MO rill

RIB +

INO

{MD2+MD9+
MO 1O)L

(MO 2+M03iL

USER

INT

IMDOoMDI1L
TP2

INITIALIZE t

el NT. TP 3

MA,MS,

DATA J-NO

~~~g

NEGATE INT
TP30 (RTF +

BREAI(

IN PROG H

KEY CONT+
CIF+RMFJ

LD CONT - ' - - - -

LD ADDRt
TP 4oMA,
MS,LD

JMP+
JMS'TP3

eNT

DATA IN +
FoM03(JMP+JMS)+

Oo(JMP+JMSi
LOAD ADDRESS +
TP4.MA,MS,

INSTRUCTION
FIE LD

REGr STE R

STA'~

UF, IFQ, JF1, IF2

MAJOR
0
INPUT GAn~F

O[VI CE

SELECTOR

eu'
su'
KEYCONT+

DATA IN

_~ __ DATA IN

RTF~

INTERNAL

; 10
MD 6J,8

SUf, SFO, Sf 1, 5f2

OMNI BUS

Figure 2-3 Memory Extension and Time-Share Control, System Block Diagram

Another design feature is the time-share trap logic that signals the monitor when certain instructions are used
by the user.
2.9.1 Control Logic
The control logic (Figure 2-3) for the Memory Extension and Time-Share option contains elements similar to
most I/O devices. These are the device selector logic, operations decoders, and the C1, INT RQST, and SKIP signallines. Before operation begins, an lOT instruction addressed to this option is required. The INT ROST and
SK IP lines are directly controlled by the USE R I NT flip-flop that functions to detect a TRAP signal. This flipflop signals the monitor that a TRAP has been detected; the monitor then evaluates and takes appropriate action.
The USE R MOD E L control signal is used in the processor to prevent the processor from responding to H LT, OSR,
and lOT instructions. The INT INHIBIT flip-flop serves to ground the INT IN PROG line, thereby preventing an
interrupt from occurring when instruction field changes are being processed.
For the user not desiring to use the time-share portion of the option, a simple jumper on the module prevents the
User Flag (UF) flip-flop from being loaded. The instructions used with the Memory Extension and Time-Share
option are listed in Table 2-1. For a detailed explanation of each instruction, refer to the KMS-E Memory option
description in Chapter 7 of the PDP-8IE & PDP·8IM Small Computer Handbook.
Table 2-1
KMS-E Extended Memory and Time-Share Option Instructions
MEMORY EXTENSION OPERATIONS
Data Field and Instruction Field Operations
RMF
RIB

Restore Memory Field
Read Interrupt Buffer
Data Field Operations

CDF
RDF

Change to Data Field
Read Data Field
Instruction Field Operations

RIF
CIF

Read Instruction Field
Change to Instruction Field
FLAG OPERATIONS

GTF
RTF

Get the Flags
Restore the Flags
TIME-SHARE OPERATIONS

CINT
SINT
CUF
SUF

Clear User Interrupt
Skip on User Interrupt
Clear User Flag
Set User Flag

2-7

2.9.2 Instruction Field Register and Controls
The Instruction Field Register receives new instruction field information from anyone of three sources:
a) Memory Data Lines, b) DATA BUS, c) Interrupt Buffer. The main registers are the Instruction Buffer Register
and the Instruction Field Register. The three output lines of the Instruction Field Register are connected, via the
Extended Address Output Multiplexer, to the three EMA lines.
The control logic (Figure 2-3) associated with the Instruction Field Register governs data flow, providing the
necessary gating and the primary control signals to enable gating, loading, clocking, etc. This logic selects either
the Save Field, the DATA BUS, or the Memory Data lines as input and outputs this information to either the
Extended Address Output Multiplexer or the DATA B US. The flow of data is from the bottom to the top of the
illustration. When the contents of the Interrupt Buffer are transferred to the Instruction Field Register, an RMF
instruction gates the Save Field bits through the Instruction Field Multiplexer. When the contents of the Instruction Register were previously stored in some memory location, the CI F instruction gates bits M D 6-8 through the
Instruction Field Multiplexer.
The DATA BUS Receiver Gates receive data from the AC Register or the Console Switch Register. During TS3
of the FETCH state, the contents of the AC are applied to the DATA BUS, while the KM8-E Operations Decoder
is decoding the RTF instruction. The RTF instruction immediately gates bits 5-8 into the Instruction Buffer
Input OR Gates. This information may have been fetched from memory during the previous memory cycle or
input from the Console Switch Register.
The contents of either the MD lines or the Save Field are gated through the Instruction Field Multiplexer by instruction RMF or CIF. The Instruction Buffer Input OR Gates, in turn, apply either DATA 5-8, MD 6-8, or
the Save Field to the Instruction Buffer Register and apply the UF flip-flop, obtained from the Save Field, to the
User Buffer. The purpose of the Instruction Buffer is to prevent the logic from prematurely loading the Instruction Field Register.
If a C IF, RTF, or RM F instruction is issued, the actual change of field does not take place unti I the next JMP i nstruction has been comple~ed or until the EXECUTE cycle of a JMS instruction has been entered. The new instruction field is first loaded into the Instruction Buffer and then transferred from the Instruction Buffer to the
Instruction Register at TP4 so that memory is not disturbed.
Although data is available for input to the Instruction Buffer Register and the User Buffer, loading does not occur until the loading lines are asserted. To load the Instruction Buffer, signal line KEY CONTROL must be
grounded or one of the three loading instructions (RTF, CIF, RMF) must be asserted (grounded) and clocked in
by TP3. Manual loading of data at the Console Switch Register creates LOAD ADDRESS L for the Instruction
Buffer Clock input and KEY CONTRO L for the buffer loading. Bits IF 0-2, representing one of eight possible
instruction fields, are on the buffer output lines when the buffer is loaded. The instruction field input logic receives IF 0-2 and the UF flip-flop. Bits IF 0-2 are then ORed with DATA 5-8 unless the operator is manually
loading data into the Switch Register or an RTF instruction is executed. These conditions allow only DATA 5-8
to enter the Instruction Field Register. The UF flip-flop is inhibited if the TIME SHARE DIS signal is asserted.
Program loading of the Instruction Field Register is accomplished by a directly addressed JMP or JMS instruction
at the end of FETCH, or by a JMP or JMS at the end of FETCH, or by an RTF instruction. Manual loading is
accomplished by signal KEY CONTROL, which is developed when the operator loads data into the Console
Switch Register. The clocking for programmed loading occurs at TP4; for manual input, clocking occurs any time
LOAD ADD R ESS L is asserted.
Once the Instruction Field Register is loaded, the contents are ready to be loaded into either the Extended Address Output Multiplexer or the Interrupt Buffer.

2-8

2.9.3 Interrupt Buffer A
Interrupt Buffer A functions to save the contents of the instruction field when an interrupt occurs. Signal INT
IN PROG H loads the UF flip-flop and bits IF 0-2 at TP4. When the interrupt has been serviced and the memory
extension is again activated, the contents of the I nterrupt Buffer are input to the I nstruction Field Multiplexer by
an RMF instruCtion and the field change sequence of events will be repeated. Should the programmer wish to
nest interrupts, he can store the contents of the Interrupt Buffer using the GTF instruction (or RIB instruction).
The machine can be restored to its original condition using the RTF (or CIF and CDF) instruction.
2.9.4 Data Field Register And Controls
The Data Field Register and Controls function to receive a new data field from anyone of three sources:
a) Memory Data Lines; b) DATA BUS; c) Interrupt Buffer. The output lines of the Data Field Register are connected to the Extended Address Output Multiplexer and, when selected, address the data field by means of a
combination of three bits on the EMA lines.
The simplified blocks (Figure 2-3) concerned with the Data Field Register and Data Field Register operation
represent the flow of data, the necessary gating, and the primary control signals to enable gating, loading, clocking, etc. They function to select either the Save Field, DATA BUS, or memory data lines as an input and output
this information to the EMA lines or the DATA BUS.
The flow of data is from the bottom to the top of the illustration. When the contents of the Interrupt Buffer are
transferred to the Data Field Register, an RMF instruction gates the Save Field bits through the Data Field Control Multiplexer. When a CDF instruction is executed, bits MD 6-8 are gated through the Data Field Control
Multiplexer.
The DATA BUS Receiver Gates receive data from the AC Register or the Console Switch Register. During TS3
of the F ETCH state, the contents of the AC are applied to the DATA BUS while the KM8-E Flag Instruction
Decoder decodes the RTF instruction. The RTF gates bits 9 through 11 into the Data Field Register.
The contents of either the MD lines or the Interrupt Buffer (RM F instruction) are gated through the Data Field
Control Multiplexer. At TP3, the new data field is loaded into the Data Field Register. The manual loading operation is similar to manual loading of the Instruction Field Register.
2.9.5 Interrupt Buffer B
Interrupt Buffer B saves the contents of the data field whenever an interrupt occurs. Signal INT IN PROG H
loads data field bits DF 0-2 at TP4. When the interrupt has been serviced and the memory extension is to be
activated, the data field is restored to the Data Field Register by the RMF instruction.
2.9.6 Extended Memory Addressing Output Control
The three EMA 0-2 lines address anyone of 8 memory fields. When any combination of these lines is grounded,
the result is a selected memory field. The Extended Address Output Multiplexer with the DF EN flip-flop determines whether the EMA bits will be the data field or the instruction field (Figure 2-3). A simplified flow diagram
illustrating the conditions which determine the selection is shown in Figure 2-4.
Beginning at the top of the flow diagram, the logic tests for a JMP or JMS instruction. If the JMP or JMS instruction is activated, the instruction field is addressed. Otherwise, the logic tests the DEFER state. The DF EN flipflop is clocked by TP4 or LOAD ADD RESS if the field is applied at the console switches. If a data break is in
operation, the extended address will not be applied to the EMA lines at that time. As soon as the data break ends,

2-9

the Extended Address Output Multiplexer will be enabled to gate either the instruction field or data field bits
out to the EMA lines and thereby select a memory field.
The rule for data field usage is as follows: If the current instruction is an AND, TAD, ISZ, DCA or EAE instruction, and if the processor is currently in the DEFER state, the next EXECUTE cycle will use the data field. All
other machine cycles that are not data break cycles use the instruction field.
Notice that the DE FER state is tested at the end of the current processor cycle. The decision whether the processor is to go to the EXECUTE state or the FETCH state is clearly indicated in Figure 3-17 of Volume 1. The
same type of decisions that determine if the next state is to be EXECUTE or FETCH determine if the instruction
field or data field is to be addressed.

8E-0317

Figure 2-4

Extended Memory Addressing, Flow Diagram

2.10 OPERATING FUNCTIONS
The following paragraphs provide some examples of KM8-E operation. These descriptions reflect the flow of
events for illustiative purposes and do not reflect the method by which this option is to be programmed.
2.10.1 Status Operation
Occasionally the user wants to select the STATUS position on the Console Selector Switch. When he does this,
IND L will be generated at the start of TS1 and remain until TS2. Signal IND is used in the memory extension

2-10

and time-share logic to gate the contents of the I F and DF Registers through the output multiplexers and onto
the DATA BUS. Refer to the system block diagram given in Figure 2-3 and to Figure 2-5 for the bit arrangement
illustrating the status. Only bit 3 and bits 5 through 11 represent the status of the Memory Extension and TimeShare Control.
Bit 3 represents the interrupt status ofthe INT INH IBIT flip-flop. Signal INT INHIBIT is generated at TP3 whenever an RTF, KEY CONTROL, CIF, or RMF signal is asserted, and negated at TP3 whenever a JMP or JMS instruction occurs. This prevents any memory field from being lost during a program interrupt. Thus, whenever
bit 3 of the status indicator is illuminated, indicating a program interrupt inhibiting condition, the processor has
not started a JMP or JMS instruction since the last instruction field change instruction was performed. When the
IF and DF Registers are loaded and INT IN PROG H is asserted, the contents of the registers are loaded into the
Interrupt Buffers at TP4.
Bits 5 through 8 represent the contents of the instruction field and the flag in the IF Register; bits 9 through 11
represent the contents of the data field in the DF Register.
2.10.2 Interrupt Buffer Transfer to Memory and Restoration
A simplified explanation of how the Interrupt Buffers could be stored in memory and restored to the Instruction
Field and Data Field Registers is illustrated in Figures 2-6 and 2-7. An RIB or GTF instruction creates the necessary gating signals to allow the instruction field and data field to pass through the corresponding output multiplexers and be applied to the DATA BUS. The same instruction grounds the C1 line, which causes the contents
of the DATA BUS to be loaded into the AC Register. A DCA instruction transfers the contents ofthe AC Register to the corresponding addressed memory location. The next time the field is to be addressed, the TAD instruction returns the data to the AC Register and an RTF instruction allows the corresponding bits to be loaded into
the Instruction Buffer and Data Field Registers at TP3. The addition of PC, AC, and MQ handling allows nesting
of interrupts.

CONSOLE STATUS INDICATORS

DATA LINES

IND

IND
BE-0318

Figure 2-5 I F and DF Display Status During TS1

2-11

ACTION

RESULT

2.10.3 Instruction Field Register Loading Operation
The Instruction Field Register loading operation is illustrated in the Instruction Field Register loading flow diagram (Figure 2-8). The first four decision blocks represent
a go condition if anyone of the blocks contain a status of
yes. For example, KEY CONTROL is developed when the

SF-DATA BUS

operator depresses the EXTD ADDR LOAD key. The corresponding clock input is LOAD ADDRESS. If the load-

DATA BUS -

ing of the Instruction Field Register is under program control, the next three conditions are tested. An RTF instruc-

SAVE FIELD-MEMORY
LOCATION X

WAIT FOR TADX

tion allows the Instruction Field Register to be loaded at
TP4 of next JMP. Otherwise, the major states are tested.
If the processor is in the FETCH state and not performing
an RTF instruction, JMP or JMS is tested and finally MD3L
is tested. When MD3H is present (indicating direct addressing), the Instruction Field Register will be loaded at TP4.
Otherwise, a DEFER state with JMP or JMS is tested. Note
that the Instruction Field Register is not loaded during a
data break. The input is at TP4 to ensure that there is no

AC -DATA BUS
RECEIVER GATES

address mixup during the current memory cycle.
2.10.4 Time-Share Operation of the System
Because much of the logic is shared between the time-share
operation and the memory extension operation, it may not

DATA 5-8--IB
DATA 9-H - - OF
8E- 0319

be obvious what logic is specifically dedicated to the timeshare function.
The time-share portion operates in two modes as denoted

Figure 2-6

Interrupt Buffer Transfer

to Memory and Restoration, Flow Diagram

by the UF flip-flop (refer to the system block diagram presented in Figure 2-3). When the UF flip-flop is in the logic

1 state, the system is operating in the user mode and a user
program is running in the central processor. When the UF flip-flop is in the logic a state, the system is operating
in the executive mode and the time-sharing monitor is in control of the central processor.
The four instructions developed by the Time-Share Operations Decoder are used by the monitor in the executive
mode and are never executed by a user program. The trap logic is a monitoring device to assure the system that
the user is programming valid instructions. When TRAP is developed, INT RQST is grounded and SKIP is enabled. The monitor then takes over and examines the invalid instruction and determines what action must be
taken.
The UF flip-flop also plays an important role in monitoring for valid instructions. When the UF flip-flop is a 1,
USER MODE L is developed and the grounded line, which goes to the processor, inhibits STOP and !/O PAUSE.
The processor is operating in the executive mode during the time that memory extension or time-sharing instructions are being processed. The user mode begins when an SUF instruction has been completed. This sets the
USE R BUFFER flip-flop and inhibits the processor interrupt until the next JMP or JMS instruction. At the conclusion of either of these instructions, the UF flip-flop is transferred to the Instruction Field Register. At that
time, the UF signal is applied to the processor I/O control output gating where USE R MODE L is developed.

2-12

AC 5 -11 -

BUFFER a OF REG

MEM_ AC

* NOT GENERATED BY KMS-E
8E-0321

Figure 2-7

Interrupt Buffer Transfer to Memory and Restoration

The following is a summary concerning valid and trapped instructions:
FUNCTION NORMALLY:
AND
TAD
ISZ
DCA
JMP
JMS
most OPE RATES
TRAPPED INSTRUCTIONS:
HLT

Monhor Return. Machine must not stop because all users
would be shut down.

OSR, LAS

Requires special action. A user does not have his own Switch
Register.

lOT

Requires interpretation (usually a device code change) by the
monitor. For example, any user can use a KSF instruction
(octal 6031). If executed by the computer, this instruction
would test the flag of the console TTY (the operator). However, the monitor alters this instruction by changing the middle
6 bits to the device code of the user's TTY.

2-13

YES

LOAD INSTRUCTION
FIELD REGISTER
8E-0320

Figure 2-8 Instruction Register Loading, Flow Diagram

2-14

SECTION 4 DETAILED LOGIC
The following description represents an expansion of the Memory Extension and Time-Share Control system
block diagram given in Figure 2-3.
2.11

INSTRUCTION FIELD REGISTERS

The Instruction Field Registers and gating logic are illustrated in Figure 2-9. The major parts are the Input Multiplexer, Instruction Buffer, and Instruction Field Register.
If the instruction field is to be changed, instruction CIF causes MD bits 6-8 to pass through the Input Multiplexer.
If the instruction field is to be restored, instruction RMF causes the save field bits from Interrupt Buffer A to
pass through the Input Multiplexer. If the data is to come from the DATA BUS, the signal DATA IN gates in bits
DATA 5-8. Bit 5 holds the content of the UF flip-flop. The Instruction Buffer receives three bits. The same
signals that were used to gate the bits through the Input Multiplexer are used to load the Instruction Buffer at
TP3. The Instruction Field Register loads the inputs by DATA IN or during a JMP or JMS. The outputs are applied to the input gates of the Extended Address Output Multiplexer and Interrupt Buffer A.
2.12 INSTRUCTION FIELD OUTPUT MULTIPLEXER
The Instruction Field Output MUltiplexer is illustrated in Figure 2-10. It consists of an 8235 I C and various control gates. Data selection lines select either the instruction field or the save field which, in turn, is applied to the
DATA BUS. Signal IND L or instruction RIF selects the instruction field. Instruction GTF or RIB gates the contents of SUF and SFO through SF2 to the DATA BUS. Bit DATA 5 is used to indicate the status of the UF flipflop.
2.13 DATA FIELD LOGIC
The data field logic is illustrated in Figure 2-11. It consists of an 8266 IC Input Multiplexer and an 8271 IC Data
Field Register. Instruction CDF is used to select bits MD 6-8; instruction RMF selects save field bits SF3 through
SF5, which are to be restored from the Interrupt Buffer B. Signal DATA IN L gates in three DATA BUS bits,
DATA9-11.
The data field bits are loaded into the Data Field Register by DATA IN L or by CDF or RMF at LOAD ADDRESS
time or TP3.
2.14 DATA FIELD OUTPUT MULTIPLEXER
The Data Field Output Multiplexer is illustrated in Figure 2-12. Data Field bits DFO-2 and INT INHIBIT (1) H
are selected by I ND L. This places these bits onto the DATA BUS during TSl and into the Status Display on the
front panel. The contents of the Interrupt Buffer can be selected by the GTF or RIB instruction.
2.15 DATA FIELD OUTPUT GATES
The Data Field Output Gates are illustrated in Figure 2-13. The contents of data field bits D FO-2 are applied to
DATA 6-8 when the RDF instruction is used.

2-15

I";-;N-;;'- ~,~;;- -

[DATA IN+D(JMP+JMS)+F'MD3(JMP+JMS)] H - - - - - - ,
(LOAD ADD+TP4·MA. MS LOAD CNT) L
IB, IF, DF CLEAR L

CIF
RMF

--I

L~--'-"'--_'"

TIME SHARE DIS L - - - . r -.........
U F (1) H
J!)------*-d
DATA IN L-...-~_~

UF LOAO H

SUF-f-{>

(DATA IN+CIF+RMF) H - - - - - .
(LOAD ADDRESS + TP3) L
IB, IF, DF CLEAR L

MD6-~I---'-1-------~--L_~

' '+t>-+-----f---I

SF1~'-+-----+-~
I
MDa-~I-----1-------~

I NSTRUCT I ON
BUFFER

MD7-~I---'-1------~--L__ ~

SF2~

IFO
(8271)

(8271)

I
I

X~~-+-4--~--~

IB1.-...,.---..__~

INSTRUCTION
FIELD
REGISTER

IF1

IF2

L _______ --.J
DATA IN L
DATA 5

DATA 6 --""'~'-_'"

DATA

7--,~,-_."

DATA 8
BE-0418

Figure 2-9

Instruction Field Registers and Gating Logic

IND L
RI F L ----..,<--_
DATA 5

GTF L
RIB L

rs2;;-I

I
I
I

I
I

SUF

I FO -1--1---1-,/

JO----i- DATA 6

SFO

I
I
I
I

SFI

SF2

~--;-DATA

IF2 -1----1-./

,.,--~-

DATA 8

L ________ ..J

8E-0406

Figure 2-10

Instruction Field Output Multiplexer

2-17

r----------,

I 8266

CDF L

DATA IN L
CDF L
RMF L

I (LOAD ADDRESS+TP3) L - - - ,
IB,IF,DF CLEAR L
I
I

RMF L --1--_01

MD6 --+--~OI

L
DFO 7

SF3 --+-----401

MD7

--+------<01
8271
DATA FIELD
REGISTER

SF4 --7----<11

OF' 9

M 08 --1-----<11

DF2 '1
SF5 ----L---OI

L.. _ _ _ _ _ _ _ _ _ ....J
DATA IN L -

........--1

DATA 9 --+---\

DATA 10 --t---I

BE -0407

DATA 11 - - - · L _ /

Figure 2-11

Data Field Logic

rB235------ -,

IND L

INT INHIBIT (1) H -:---t--L-...J
+5V -~'v--~

I
I
I

~--DATA

)0--1- DATA 9

SUF 3

I
I

)0--1- DATA to

SUF 4

I
DATA 11
GTF L - - - -.....
RIB L - ___" )O-t--OI

8E-040a

Figure 2-12 Data Field Output Multiplexer

2-18

2.16 INTERRUPT BUFFERS LOGIC
DFO---i
DATA 6

Interrupt Buffers A and B are illustrated in Figure 2-14.
Buffer A is used to store the contents of the instruction field
DF'

in the event of an interrupt; Buffer B is used to store the con-

-+--i
DATA 7

tents of the data field in the event of an interrupt. Each time
an interrupt occurs, the buffers are loaded at TP4.

DF2 -+---1
DATA 8

2.17 INTERRUPT INHIBIT LOGIC
When the processor is honoring an interrupt,INT IN PROG H

RDF L

is asserted. This signal is asserted at +5V, and is driven posi-

8E-0409

tive by a load resistor- Thus, anytime INT IN PROG H is to
be negated, the signal line is simply grounded. Within the

Figure 2-13 Data Field Output Gates

memory extension logic there is a period of time in which
INT IN PROG H must not be asserted; for example, when the processor has issued a CIF instruction and has not
yet encountered a JMP or JMS. These logical conditions are represented in the logic diagram illustrated in Figure
2-15. Signal I NT IN H I B IT (1) H is carried to DATA 3 of the DATA B US to report to the Status Display that signalline INT IN PROG H has been negated, thereby inhibiting any interrupts if IND L is low.
2.18 INTERRUPT-BREAK DETECT LOGIC
The interrupt-break detect logic ensures that no critical operation, such as clearing of the IB, IF or DF registers
or loading the Save Field Register, is accomplished while a data break is taking place_ At the time an interrupt is
being honored, both of these operations must take place. The two signal lines representing these activities (INT
IN PROG Hand MA, MS, LD CONT) are tested. Refer to Figure 2-16 for the detailed logic.
2.19 REGISTER CLEAR LOGIC
The Instruction Buffer, the Instruction Field Register, and the Data Field Register will be cleared at TP4 (Figure
2-17) if there is an interrupt and no data break is occurring, or if the machine is powered up_
2.20 DATA IN LOGIC
The data in logic develops DATA IN L to load the memory extension registers or to allow bits 5-8 of the DATA
BUS to be gated into the instruction field logic and bits 9-11 of the DATA BUS to be gated into the data field
logic. Signal DATA IN L is asserted by the program when an RTF instruction is decoded, or under manual control during TS1. Refer to Figure 2-18 for the logic diagram.
2.21

USER FLAG LOGIC

The User Flag (UF) is used only when the time-sharing portion of this option is implemented. The UF logic
(Figure 2-19) is a D-type flip-flop that acts as a buffer in the same manner as the Instruction Buffer- Signal UF
LOAD H is generated by the instruction field loading logic when DATA 5 is a 1 or SUF is asserted and clocked
in by either an RMF or RTF instruction at TP3. The UF flip-flop can be set by instruction SUF and cleared by
the instruction SUF and cleared by the logical conditions shown in Figure 2-19.

2-19

TO INSTRUCTION FIELD
OUTPUT MULTIPLEXER
SUF

SFO

SF1

SF2

::~}

....--t--.....--t---+-- SFO

TO INSTRUCTION
FIELD INPUT
MULTIPLEXER

+--+--+-+-- SUF·
(INT IN PROG-MA, MS LOAD CNT) H

( LOAD ADD + TP4 • MA, MS LOAO CNT) L

+3V

USER

IBO

IB1

IB2

,FLAG
FROM INSTRUCTION
BUFFER

TO DATA FIELD
OUTPUT MULTIPLEXER
~

SF3

SF4

SF5

SF5j TO DATA
FIELD INPUT

.....- - j - - - SF4
....- - t - - - j - - - SF3

(INT IN F'ROG -MA, MS LOAD CNT) H
(LOAD AOD + TP4' MA, MS LOAD CNT) L

+3V

MULTIPLEXER

INTERRUPT
BUFFER B
(8271)

BDFOjTO EXT'D
BDF1 ADDRESS
OUTPUT
BDF2 MULTI PLEXER

....._-+_.. j TO DATA FIELD

OUTPUT GATES

DFO

DF1

DF2
BE-0410

Figure 2·14

Interrupt Buffers Logic

INT IN PROG. MA
MS LOAD CNT) H
TP4 H -_____./

TP3 H
CUF L--",_

RUN L
POWER OK H-_____~~-----------------------~::::::::~
TP3

H-_--...r--'"

DRJMP+JMSij L
[F'MD3(JMP+JMSl] L,-~_ _

INT IN PROGRESS H

DATA IN L
CIF L
RMF L -......._.-

tNT INHIBIT (I) H

BE-0411

Figure 2-15 Interrupt Inhibit Logic

INT IN PROGRESS H

INT IN PROG. MA. MS LOAD CNT
MA. MS LD CONT

Figure 2-16 Interrupt Break Detect Logic

TP4 H
(INT IN PROG·MA. MS LOAD CNT) H
RUN L
JO.--~---- lB. IF. OF CLEAR L

POWER OK H
8E-0413

Figure 2·17 Register Clear Logic

2-21

MDll
1/0 PAUSE L

-------0,--....

MD 4 e. 5 L - - - - - - - 0

(MD6-S) L-------oL-_~

MD10 L
MD9 L ------~L-_./

r-E~-;:-O~

TP 2 H

--,

----1----\
I

I
I

I
TSl L

DATA IN

(1)

~~I~-------Dr-~

IL _ _ _ _ _ -1

KEY CONTROL
8E-0414

F igu re 2-18

Data In Logic

TP3 H
SUF L

RUN L
POWER OK H

UF (1) H

TP3 H
CUF L

LOAD ADDRESS H - - - - - 1

TP3H-------r--~

UF LOAD H

RMF L
RTF L

8E-0415

Figure 2-19

User Flag Logic

2-22

2.22 TRAP DETECT LOGIC
The trap detect logic (Figure 2-20) is used when the time-sharing portion of this option is implemented. When
it is not implemented, the time-share disable circuit will contain jumpers that will hold the (0) side high and the
(1) side low. Signal USER MODE L will be high because UF (1) will be low. Signal TRAP is high if the MD lines
indicate an lOT (F.UM.6xxx) or special operate (F.UM.74xl, where bits 9 or 10 are ls).
2.23 EXTENDED MEMORY ADDRESS LOGIC
The extended memory address logic (Figure 2-21) includes the output gates within the 8235 IC and the DF EN
and EMA DISABLE flip-flops with corresponding control logic. The output gates, IC 8235, are a multiplexer of
which the data selected for output is determined by the EMA DISAB LE and DF EN flip-flops. The EMA
DISABLE flip-flop serves the same function as the MAC flip-flop in the M8310 CPU Control Module, and is used
to disable the output multiplexer at TP4 in the event of a data break.
The interrupt break logic signal clears the EMA D ISAB LE flip-flop at TP4 or when the machine is in the manual
mode. The DF EN flip-flop determines if the output data is the data field or the instruction field. If the processor is not doing a JMP or JMS instruction, but is in the DEFE R state, the data field will be addressed during the
next machine cycle. If the processor is doing a JMP or JMS or is not in the DEFER state, the instruction field
will be addressed.

rusER INT FiF --,
I
I
I
I
I

INITALIZE H

CINT L

TNT RQST L

!TR:;; ;;;T~ 7oG"7Z - - - - - I

SKIP L
SINT L
TRAP

I
I
I
I
I
I
I
I
I ____________ -.J
L

Figure 2-20 Time-Share Trap Logic

2-23

US R MODE L

UF (11----1

0416

(INT INPROG-MA,
MS LOAD CNTl H
TP4 H

r;2~
RUN L

+3V

LOAD
ADDRESS H

+3V

POWER OK L

POWER ON H

IFO
TP4

B DFO

----,

I
-=--1----+--1--1-..)

EMAO

---':'---<lI

IF1 --1---------+-t-L-~

CPMA DISABLE L

)Cr---L- EM AI

B D F 1 ---J----<~
MA, MS LOAD CNT H

I F2 ---I----------1--l_1\
B DF2 --+--a

)<>--1- EMA 2

L ______ --1

8E-0417

Figure 2-21

Extended Memory Address Logic

SECTION 5 MAINTENANCE
The general procedures concerning preventive and corrective maintenance are given in Volume 1, Chapter 4.
When corrective maintenance is required, the technician should use the maintenance programs given in Section 2
of this chapter to determine the nature of the problem. Refer to the option schematic, drawing number
E7CS-M737-0-1, for IC locations and pin numbers. Test points have been provided on the module to facilitate
troubleshooting.

SECTION 6 SPARE PARTS
Table 2-2 lists recommended spare parts for the KM8-E. These parts can be obtained from any local DEC office
or from DEC, Maynard, Massachusetts.
Table 2-2
Recommended KM8-E Spare Parts
DEC Part No.

Description

19-05575
19-09705
19-09615
19-09935
19-09934
19-09594
19-09667
19-05547
19-05577
19-05576
19-09686
19-09056
19-09486
19-09972
13-00365
10-01610
10-05306

IC DEC 7400
IC DEC 8881
IC DEC 8271
IC DEC 8235
IC DEC 8266
IC DEC 8251
IC DEC 74H74
Ie DEC 7474
Ie DEC 7420
Ie DEC 7410
Ie DEC 7404
IC DEC 74HOO
Ie DEC 384A
IC DEC 6314A
Resistor 1 K, 1/4W, 5%
Capacitor 0.01 MF DISK, 20%
Capacitor 6.8 ,uF, 35 V, 10%

2-25

Quantity

CHAPTER 3
MRS-E REA~-ONLY MEMORY

SECTION 1 INTRODUCTION

3.1 READ-ONLY MEMORY DESCRIPTION
The M RB-E is a 256-word Read-Only Memory (ROM) option used in the PDP-B/E. The M RB-E consists of an

MBBO Quad Module that is inserted into the OMNIBUS and an H241 Braid Board mounted on the MBBO Module.
The thickness of the module and braid board requires that two spaces be allotted for this option on the OMNIBUS,
although the MRB-E plugs into only one of these spaces. Each ROM option occupies two pages (400 8 locations)
of the 3210 pages (7777 8 locations) in each field. The M RB-E can be located starting at the beginning of any evennumbered pate in any field, such as 00008 , 04008 , or 44008 , Note that the corresponding core memory locations cannot be used by the software while the MRB-E is installed in the OMNIBUS. When a memory location assigned to the MRB-E is addressed, ROM ADD L will be asserted which, in turn, disables core memory.
From a programming point of view, and as viewed from the OMNIBUS, the M RB-E is addressed the same way as
core memory (Paragraph 3.24, Volume 1). Within the M RB-E these 400 8 words are organized as 200 8 lines, each
running through or around 24 ferrite cores (two 12-bit words). Each drive line is terminated by a diode on one
end and by a switch tied to a decoder on the other end. The memory locations are selected by MAOO to MA 11
and EMAOO to EMA02. The MRB-E is interfaced to the processor by the OMNIBUS.

SECTION 2 INSTALLATION
The MRB-E will be installed on site by DEC Field Service personnel. The customer should not attempt to unpack,
inspect, install, checkout, or service the MRB-E Module.

3.2 INSTALLATION
Perform the following steps to install the MRB-E Read-Only Memory:
Step

Procedure
Remove power from the PDP-B/E by turning Power Switch to OFF.

Ensure proper diodes are installed in the MBBO Module to select the starting address
of ROM (drawing CS-MBBO-O-1).

Insert the MRB-E (MBBO and H241) into the OMNIBUS (refer to Table 2-3, Volume 1)
for module installation priority.

3-1

3.3 ACCEPTANCE TEST
Perform the following steps to check the MRS-E Modules:
Step

Procedure
Load ROM Test Tape Low (MAINDEC-SE-D1JA-PB1) or ROM Test Tape High
(MAl NDEC-SE-D1JA-PB2). Refer to diagnostic write up for correct loading procedures.

Allow the diagnostic to run for 20 minutes with no errors.
NOTE
Refer to Section 5 for the procedure to change
ROM contents if errors are found.

SECTION 3 SYSTEM DESCRIPTION
3.4 MR8-E BLOCK DIAGRAM
The MRS-E consists of an MSSO Drive and Sense Module and an H241 Braid Board Assembly. The MSSO Module
contains the logic for addressing 256 words of memory located on the H241 Braid Board Assembly. The MRS-E
is addressed in the same way as PDP-S/E Core Memory (Paragraph 3.24, Volume 1). If the MRS-E is placed in
the same field with a 4K core memory, the two pages of core memory with the same addresses as ROM cannot be
accessed by the program. If the software tries to write in ROM, the new information will be lost and the contents
of ROM will not be changed. When the MRS-E detects an address to which it must respond it asserts ROM ADD L
(Figure 3-1) which disables core memory. The 4008 words of the MRS-E memory are organized as 2008 lines
with each line containing two words. The 200 8 lines run through or around 2410 ferrite cores and sense windings
(Figure 3-2). Each of the 200 8 lines is terminated by a diode at one end and in S groups of 16 10 lines tied to the
outputs of a BCD decoder at the other end.
3.5 ROM ADDRESSING
Addressing of the 4008 locations is accomplished as follows.

The three EMA lines and the four most-significant MA lines (MAOO-MA03) are decoded in Address
Selection AND gate within the MRS-E to determine whether the currently addressed location is within
the option. The Address Selection gate consists in part of 1410 diodes, seven of which must be removed
to define the combination of EMA and most-significant MA bits for which the MRS-E is active. If the
MRS-E is selected, a gate at the output of the Address Selection gate asserts (grounds) the ROM ADD L
line on the OMNIBUS, thereby disabling the core memory that would normally respond to that address.
In addition, a second output of the Address Selection gate (labeled FIELD L on the logic diagrams) enables decoding of the remaining MA lines.

MA04 through MA07 are decoded and select one of 20 s (16 10 ) drivers, each of which is conn~cted to
lOs (SIO) diodes.

MAOS through MAlO select one output of the line select decoder which is a BCD-to-decimal decoder.
One of lOs outputs from the BCD-to-decimal decoder is selected and forward biases the diode selected
by MA04 through MA07 so that current will flow through the selected line and induce a signal in the
sense winding if it passes through the core. Data is taken from the MRS-E using high-permability ferrite
U- and I-cores mated to form a closed magnetic path. The 200 8 lines run through or around the 2410
U-cores, the 24 I-cores are wound with a 50-turn sense winding. When current is driven through a selected line, which passes through the mated core, a 2.5V to 3.0V signal is magnetically induced in the
winding. The signal induced in the sense winding is fed to a DTL-type gate and clocked by a strobe
pUlse. If the selected line passes around (not through) the mated core, no signal is induced in the sense
winding.
3-2

MAoe, MA09, MAlO
FI ELD L

SWITCH
DIODE
SELECT
LOGIC

1
BRAID
BOARD

MA-OO TO MA-03

EMA-OO TO EMA-O'2
OMNIBUS
SIGNALS

'2 WORDS

MEMORY
ADDRESS
DECODER

ROM ADD L

STROBE

FIELD L

FI ELD L

FIELD H

MA04 - - MA07

LINE
DRIVER
SELECT

TP-4

MAll

WORD
SELECT

1
FIELD H
CLEAR L
MD DIR L

WORD
SELECT
LOGIC
AND
MEMORY
REGISTER

MD-OO TO MD-ll

8E-0350

Figure 3-1

Read-Only Memory Block Diagram

3-3

The selected line causes a 24-bit word to be read. MA 11 controls which half of the addressed word is
applied to the Memory Register. The output of the DTL gates is clocked into a 12-bit Memory Buffer
Register.

FIE LD H, NOT C LEA R Land M D D I R L enable the output of the Memory Register to the M D lines.

WORD a

~
~

0 1 2 3 4 5 6 7
0000000 0

WORD 1
8 9 10 1 I
000 0

10 9
0 0

8
0

7 6 5
000

4 3 2 1 0
000 0 0

8E-0349

Figure 3-2 H241 Braid Board

SECTION 4 DETAILED LOGIC
The logic in the MRS-E is broken into functional groups for discussion purposes. The block diagram in Figure 3-1
should be used to understand the interaction of the groups of logic.
3.6 ADDRESS DECODER
The Address Decoder (Figure 3-3) receives bits MAOO through MA03 and EMAOO through EMA02 for decoding.
The 14 diodes (7 of which are removed) select the high-order address of ROM. If the MA and EMA bits indicate
the selected address is within ROM FIE LD L, ROM ADD will be asserted, so that only ROM can be accessed by
the program. FIE LD L enables gates to allow MA04 through MA 11 to be decoded and used to select a line driver,
switch, and word 0 or 1.

3.7 SWITCH SELECT LOGIC
The switch select logic (Figure 3-4) decodes MAOS through MA 10 and selects one of the groups of diodes on the
H241 Biaid Board Assembiy using the proper switch line. FIE LD L is used to enable E26 AND gates and the output of the AND gates is applied to the 74145 IC. The 74145 IC is a BCD-to-decimal decoder that pulls one of the
output lines low when the 3-bit input is decoded. The output of E27 is applied to the 8 switches that enable the
selection of the proper diode and one of the 16 line drivers (F igu re 3-5).

3-4

TP4 H
TP4 L

ROM ADD L

+5V

-15V

MA03 L
0

FIELD L
MA02 L
0

4
-15V
5

MAOI L
0

7
MAOO L
0

8
9

EMAOO L
0

10
11

EMAOI L
0

13
EMA02 L
0

ASI
TP
8[-0351

Figure 3-3

Address Decoder Logic

3-5

09
*(16 DI:ODES)
: 0113
SWOO ___~--~~D~12~1-MAl 0 ---~::r--:-"""'"

1C)''-----4--JV\J''r--- + 5 V

A
MA09L---+-~---~

E27

MA08--~-<f--~
1O'~--~--JV\J"r----+5V

FIE L 0 L - 4 - - - - - - - -______--1 0

SW07

*Diode. located on H241 module.
8E-035~

Figure3-4 Switch Select Logic

MA07 L

0
C

MA06 L

B
A
MA05 L

SN7442N
E15

FIELD L

LINES
TI ED TO
DRIVERS
( SEE FIGURE

+5V
FI ELD L
STROBE H - - - - - - -.....

MAD4 L

3-6)

C
FIELD L

'----+-IB
'------t--tA
SN7442N
E19

+5V

8(- 0:548

Figure 3-5 Line Driver Select Logic

3-6

3.8 LINE DRIVER SELECT LOGIC AND LINE DRIVERS
The line driver select logic (Figure 3-5) decodes MA04 through MA07 and selects one of the 16 line drivers. Each
line driver has 8 diodes in its collector circuit, each of which is tied to one end of the 8 switch lines on the braid
board (Figure 3-6). There are 16 line drivers, with 8 diodes each, to select 128 lines (256 words) on the braid
board. The E12 AND gates are enabled by FIE LD L; MA05 through MA07 are applied to E15 and E 19. E15 and
E19 are BCD-to-decimal decoders that assert one output line for each input and cause the line driver to forward
bias 8 diodes. MA04 is used to select a control input at pin 0 on E15 or E19. When MA04 is 1 (low), E20 is disabled and input 0 of E19 has a low enabling input that allows E19 to pull one output low and select one of its
line drivers. When MA04 is 0 (high), E20 and E16 are enabled and input 0 of E15 has a low (enabling) input.
Note that each line driver has 8 diodes tied to 8 different switch lines in the diode matrix (Figure 3-6). When the
diode is selected by a line driver and the switch on the other end of a line is selected, current flows through that
line and induces a voltage in the sense windings of those cores that have a line passing through them. Table 3-1
lists the lines in the braid board and the two words associated with each line.
The diode tied to each line has the same numerical designation as the line, i.e., line 1 has 01 tied to one end.
3.9 SENSE LOGIC AND MEMORY REGISTER
The sense windings of the 24 ferrite cores are tied to DTL AND gates (Figure 3-7) on the M880 Module. As
stated previously, when current flows through the selected line a voltage is induced in the sense windings shown
as A 1 through A 11 for word 0, and B 1 through B11 for word 1. MA 11 applied to E26 allows one of the words
to be applied to the Memory Register when FIELD L and STROBE L are applied to E24. If MA11 is 0, word 0
(sense winding B) is applied to the Memory Register; if MA 11 is 1, word 1 (sense winding A) is applied to the
Memory Register.
The Memory Register is made up of 12 set-reset type flip-flops that hold the 12 bits of data until MD 01 R L, NOT
CLEAR L and FIELD H are received. The result enables the AND gates and applies the contents of the Buffer
Register to the MD lines.

,....---- - - -

------,

SN7442
E15 AND E19

........---------...".....
9

+5V

----------'---+-1

r--I

---, r - - - ---,

I
I D1
I
I
I
LI NE 1
LINE 8
IL _
_ _ _ _ _ _ .JI

I
I
I D121
I
I
I
LINE 121
LINE 128
IL. _
_ _ _ _ _ _ .JI

LINES AND DIODES INSIDE DOTTED LINE ARE ON THE

H241
8E- 0347

Figure 3-6

Line Drivers and Diodes

3-7

Table 3-1
Line and Switch Identification for ROM Addresses
Line

Sw.

Line

Sw.

Number

Addresses*

Term

Number

Addresses*

Term

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

000,001
002,003
004,005
006,007
010,011
012,013
014,015
016,017
020,021
022,023
024,025
026,027
030,031
032,033
034,035
036,037
040,041
042,043
044,045
046,047
050,051
052,053
054,055
056,057
060,061
062,063
064,065
066,067
070,071
072,073
074,075
076,077
100,101
102,103
104,105
106,107
110,111
112,113
114,115
116,117

0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

120,121
122,123
124,125
126,127
130,131
132,133
134,135
136,137
140,141
142,143
144,145
146,147
150,151
152,153
154,155
156,157
160,161
162,163
164,165
166,167
170,171
172,173
174,175
176,177
200,201
202,203
204,205
206,207
210,211
212,213
214,215
216,217
220,221
222,223
224,225
226,227
230,231
232,233
234,235
236,237

0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7

°
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7

°
1
2
3
4
5
6
7

"These addresses are within the MR8-E. To get the absolute address, add the starting address of the MR8-E to the MR8-E addresses, i.e.,
MR8-E starts at 4400, line 123 contains absolute addresses 4764 and 4765.4764 is word 0 and 4765 is word 1. The word will be selected
by Bit 11 applied to the MR8-E.

3-8

Table 3-1 (Cont)
Line and Switch Identification for ROM Addresses
Line

Sw.

Line

Sw.

Number

Addresses*

Term

Number

Addresses*

Term

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104

240,241
242,243
244,245
246,247
250,251
252,253
254,255
256,257
260,261
262,263
264,265
266,267
270,271
272,273
274,275
276,277
300,301
302,303
304,305
306,307
310,311
312,313
314,315
316,317

0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7

105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

320,321
322,323
324,325
326,327
330,331
332,333
334,335
336,337
340,341
342,343
344,345
346,347
350,351
352,353
354,355
356,357
360,361
362,363
364,365
366,367
370,371
372,373
374,375
376,377

0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7

°
1
2
3
4

5
6
7

'These addresses are within the MRS-E. To get the absolute address, add the starting address of the MRS-E to the M RS-E addresses, i.e.,
MRS-E starts at 4400, line 123 contains absolute addresses 4764 and 4765.4764 is word 0 and 4765 is word 1. The word will be selected
by 8 it 11 appl ied to the MRS-E.

3.10 CLEAR LOGIC
The clear logic (Figures 3-8 and 3-9) clears the Memory Register and enables gates to place data from the Memory
Register on the MD I ines of the OMNIBUS. The Memory Register is cleared when RETURN H goes high (100 ns
into the memory cycle) clearing the CLEAR flip-flop_
At STROBE TIME, the CLEAR flip-flop is set, enabling the Memory Register output gates (Figure 3-7) to transfer
the contents of the Memory Register to the MD lines, when MD DI R is asserted (MD DI R on the OMNIBUS is
low)_
3.11

LINE SELECT DIODE MATRIX

The line select diode matrix (Figure 3-10) selects one of the lines which pass through or around the ROM core
and allows current to flow through one line for each address_ One end of each line is tied to a switch; the other
end is tied to a diode. The diode is in the collector of a line driver (DRO to DR15) and the selected diode is

3-9

WORD 1

, - - - - - - - - - - - - - - - - - - - - ---..---------,
A12

L -_ _ _ _ _ _~-----------------

FIELD L

\-------+-------- - - - - - - - ------I

MA" L-~,,--_/

.-____+ __________W~JR~ !! __ -----1>------1--+
B12

'--------f-------- - - - - - - STROBE L-f------<:I---"

\-------+------- - - - - - - - ------I

\--~----t---

- - - - - - - ------j

MD II

MD 00

.**

EACH GATE ENABLES HALF OF THE SENSE GATES
DOTTED LINES INDICATE MISSING LOGIC IDENTICAL TO THAT SHOWN.

Figure 3-7

BE -0346

Sense Logic and Memory Register

+5V

TP
DAI
WRITE H - - - - 1
l>~>--<l

D CLEAR 1

CLEAR L

FIELD H -_.--1
CLEAR
E-21
} - - - - - j C PRESET 0

CLEAR H

RETURN H ---!---/

STROBE H
8E-0345

Figure 3-8

Clear Logic

3-10

BOOns

gOOns

1 1
RETURN

STROBE

**WRITE

CLEAR L

* Approximate times
**For reference on Iy
8E-0353

Figure 3-9

Read Timing Diagram

forward biased by the switch select logic to allow current flow through the line. Current flow through the line
causes a voltage to be induced in the sense windings of the cores through which the line passes. This voltage is
applied to the DTL logic (Figure 3-7) and gated to the Memory Register by MA11 and STROBE L.

SECTION 5 MAINTENANCE
The MR8-E diagnostic (MAINDEC-8E-D1JA-PB1 or MAINDEC-8E-D1JA-PB2) should be run when a ROM malfunction is suspected. Use the following procedure to change the contents of ROM or to correct errors.
Procedure

Step

Remove the H241 with cover and standoffs from M880.

With Side 2 of the H241 up, find the line that corresponds to the address of the word to
be changed. Each line contains two words, so the 128 lines contain 256 addresses (Table
3-1). Cut the line to be changed.

Solder the new wire to the lug as follows:
a . l f you are placing new words in these addresses, string the wire through all 24 cores
using all the tie down jumpers. The 24 cores correspond to the two 12-bit words of
the line (Figure 3-2). For a logical 1, string the wire inside the "U" core; for a 0,
string the wire outside the core. Terminate the wire on the proper switch (Table 3-1).
b.

If you are correcting an error in the MR8-E, the diagnostic program will provide all
the information needed. A typical typeout would be as shown in Table 3-2. For
this error, cut Line 5, replace it, and string wire through the cores as shown in the
insert portion of the typeout. The 24 bits shown correspond one-to-one with the
24 cores on the board, from left to right. The line should be terminated on SW4.
If an error occurs in the field, check the diode before replacing the line.

Check electrical continuity.

3-11

(ORO)

(DR1)

(DR2)

(DR3)

(DR4)

(DR5)

(DR6)

(DR7)

(DR8)

72
(DR9)

80
(DRlO)

88
(DR11)

(DR12)

(DR13)

(DR14)

(bR15)

(SWO)

(SWll

(SW2)

(SW3)

(SW4)

(SW5)

(SW6)

(SW7)
8E-0344

Figure 3-10

Line Select Diode Matrix

3-12

Table 3-2
Typical Error Typeout
ADDR

Good

Bad

Driver

Line

Diode

7010

3635

3637

Insert
011110011101

010101010100

Term
SW4

SECTION 6 SPARE PARTS
Table 3-3 lists recommended spare parts for the MR8-E. These parts can be obtained from any local DEC office
or from DEC, Maynard, Massachusetts.
Table 3-3
Recommended M RS-E Spare Parts
DEC Part No.

Description

Quantity

15-05321
15-03100
11-60114
19-10047
19-10046
19-09705
19-09688
19-09667
19-09486
19-09971
19-09267
19-09056
19-05576
19-05575

Transistor DEC 4258
Transistor DEC 3009B
Diode D664
IC DEC 74145
IC DEC 7442
IC DEC 8881
IC DEC 846
IC DEC 74H74
IC DEC 384
IC DEC 6380
IC DEC 74H11
IC DEC 7402
IC DEC 7410
IC DEC 7400

3-13

1
2

CHAPTER 4
MIS-E HARDWARE BOOTSTRAP LOADER

SECTION 1 INTRODUCTION
4.1

GENERAL DESCRIPTION

The MI8-E Bootstrap Loader option uses a 32-word Read-Only Memory (ROM) with diodes that can be arranged
to accommodate any program up to 32 words in length. The Bootstrap Loader option is available in the following
configurations:
Option Designation

RIM Program

MI8-E
MI8-EA,B
MI8-EC
MI8-ED
MI8-EE
MI8-EF
MI8-EG
MI8-EH
MI8-EJ

Unencoded
Paper Tape
TC08 DECtape
RK8-E
Typeset
Edu System (low)
Edu System (high)
TD8-E DECtape
RK05

Each configuration contains a uniquely encoded ROM in the form of a specific Read-In Mode (RIM) program.
Without this option, RIM would be toggled into memory by the operator at the programmer's console. The RIM
loader instructs the computer to receive and store, in core, data from any of the above peripherals in RIM-coded
format.
The MI8-E Bootstrap Loader is contained on one quad-size module, designated M847, that plugs directly into the
OMNIBUS. All signals enter and leave the module via the OMNIBUS.
4.2 EQUIPMENT REQUIREMENTS
The following basic equipment is necessary to operate and maintain the MI8-E Bootstrap Loader:

a.
b.

c.
d.

e.
f.

PDP-8/E Computer
ASR-33 Teletype or Equivalent
Low- or High-Speed Paper-Tape Reader
Low- or High-Speed Paper-Tape Punch
MI8-E Bootstrap Diagnostic
Bootstrap Loader Option

4-'

4.3 COMPANION DOCUMENTS
The following documents and publications are necessary for the operation, installation, and maintenance of this
option:

PDP-8IE & PDP-81M Small Computer Handbook - DEC, 1973

PDP-8IE Maintenance Manual - Volume 1

Introduction to Programming - DEC, 1972

DEC engineering drawing, Bootstrap Loader Option, number M847-0-1

MI8-E Bootstrap Loader Diagnostic Manual, MAINDEC-8E-D1IA-D-(D)

4.4 SOFTWARE
The MAINDEC-8E-D1IA-D diqgnostic is used to troubleshoot and verify the operation of the MI8-E Bootstrap
Loader option in all configurations shown in Paragraph 4.1.
The diagnostic is available in a low- and high-core version. The version used to test an MI8-E Module will depend
on the memory locations utilized by that particular module. The low-core version occupies and uses memory locations 0200-1777, the high-core version occupies and uses memory locations 4200-5777. Use the version that
does not conflict with the memory locations of the bootstrap block for the MI8-E Module under test.

SECTION 2 INSTALLATION
The MI8-E Bootstrap Loader option is installed on-site by DEC Field Service personnel. The customer should
not attempt to unpack, inspect, install, checkout, or service the equipment.
4.5

INSTALLATION

Perform the following procedures to install the MI8-E option:
Procedure

Step

Remove the module from the shipping container.

Inspect the module for any apparent damage.

Verify that the initial address, field address, and starting address jumpers are correct according to Table 4-1.

Verify that the diode matrix is properly cut.

Connect the module to a convenient OMNIBUS slot. The module should be located
reasonably close to the MM8-E Modules.

4.6 CHECKOUT
Perform the following procedures to checkout the M 18-E option:
Procedure

Step

Perform acceptance tests provided in Paragraph 2.3, Volume 1.

Load MAl NDEC-8E-D1IA-D. This verifies the correct operation of the MI8-E Bootstrap
Loader in all of its standard configurations.
(continued on next page)

4-2

Step

Procedure

If this verification was not performed satisfactorily, refer to Section 5 for troubleshooting
procedures.

Make proper entry on user's log that the acceptance test for the MI8·E option was performed satisfactori Iy.
Table 4-1
MIS-E Bootstrap Loader Option Encoding Scheme

Option
INITIAL
ADDRESS
Data

Starting
Address

MIS-EF
Edu Sys
Low

MIS-EG
Edu Sys
High

MIS-EH
TDS-E
Dectape

7737
6007
7604
7510
3343
6766
6771
5344
1376
5343
7600
6603
6622
5352
5752
7577
6014
6011
5357
6016
7106
7006
7510
5374
7006
6011
5367
6016
7420
3776
3376
5357
0220

7300
1312
4312
4312
6773
5303
6777
3726
2326
5303
5732
2000
1300
6774
6771
5315
6776
0331
1327
7640
5315
2321
5712
7354
7756
7747
0077
7400
7777

"
"
"
"
"
"
"
"
"
"
"
"

7737
6007
7604
7510
3343
6766
6771
5344
1376
5343
7600
6603
6622
5352
5752
7577
6032
6031
5357
6036
7106
7006
7510
5357
7006
6031
5367
6034
7420
3776
3376
5356
0220

0023

7770

7737

7300

MIS-EA
Paper Tape

7737
6014
0776
7326
1337
2376
5340
6011
5356
3361
1361
3371
1345
3357
1345
3367
6032
6031
5357
6036
7106
7006
7510
5374
7006
6031
5367
6034
7420
3776
3376
5356
0

7554
7600
6774
1374
6766
6771
5360
7240
1354
3773
1354
3772
1375
6766
5376
7754
7755
0600
0220
6771
5376
7777

"
"
"

7737

7554

Data

MIS-EC
TCOS
DECtape

MIS-E
Unencoded

MIS-ED
RKS

MIS-EE
Typeset

0023
6007
6751
6745
5025
7200
6733
5031
7777
7777

7756
7771
6014
6011
5360
7106
7106
6012
7420
5357
5756
4356
3373
4356
7777

"
"
"

"
"
"
"

"
"
"

"
"
"
"
"

"
"
"
"
"
"
"
"

"
"
"

4-3

"
"
"

SECTION 3 OPERATING PROCEDURES
The operating procedures for the Bootstrap Loader are as follows:
Procedure

Step

If the RUN lamp is on, depress the HLT key and observe that the RUN lamp is off.

Depress and raise the SW key.

Observe that the RUN lamp is again illuminated.

SECTION 4 PRINCIPLES OF OPERATION

4.7 GENERAL DESCRIPTION
The relation of the Bootstrap Loader and the CPU is similar to that of the operator's console and the CPU. Both
the loader and the panel must:

Initialize the CPU.

Load Address.

Load Extended Address.

Deposit instructions in sequential locations.

Load starting address of the program just deposited.

Start the program.

)

to define the first address in which
to deposit instructions

Because the operation of the Bootstrap Loader is closely tied in with the operation of the processor, the reader
should have a thorough understanding of the processor control signals. Detailed theory of the processor and
memory is given in Chapter 3, Volume 1; the control signal description is provided in Chapter 9 of the PDP-8IE

& PDP-81M Small Computer Handbook.
A summary description of the control signals necessary to accomplish the six operations listed above is given in
the following:
Operation

Assert

Affect on CPU

Initialize (Bootstrap)

Ground: POWER OK H (Pin
BV2)

Causes the CPU's MA Control flipflop to clear. Also causes the CPU's
timing generator to generate.

Initialize (Panel)

INITIALIZE H (Pin CR1)

INITIALIZE H, clearing the AC,
Link, all flags, and the Interrupt and
Break systems.

Load Initial Address

Ground: LA ENABLE L (pin
8M2)
Place initial address onto the
data lines of the OMNIBUS

Loads the address placed on the da·
ta lines into the CPMA register.

Pulse: PULSE LA H (Pin DR2)

(continued on next page)

4-4

Operation
Load Extended Address

Assert

Affect On CPU

Ground: KEY CONTROL L
(Pin DU2)
Place extended address bits onto Data 6-S and Data 9-11

Loads the addresses placed on bits
6-S and 9-11 of the DATA BUS
into the IF and DF of the Memory
Extension Control, Type KMS-E, if
one is in the machine.

Pulse: PULSE LA H (Pin DR2)
Deposit (used by panel)

Ground: KEY CONTROL L
(Pin DU2)
MS,IR DISABLE L (Pin CV1)
Place bits to be deposited onto
DATA BUS.

Causes one memory cycle to occur.
Word on DATA BUS is deposited,
and PC is incremented. Machine
stops at end of memory cycle.

Pulse (low): MEM START L
(Pin AJ2)
Deposit (used by bootstrap)

Same as Deposit above, except
KEY CONTROL L (Pin DU2)
goes high during TS3 of computer's cycl e.

Load Starting Address

Same operation as Load Initial Address except for the word plc<edc;1 the
DATA BUS.

Start Program

Pulse (low): MEM START L
(Pin AJ2)

Same as above, except that the machine continues to run.

Starts program.

To minimize the logic needed for the MIS-E, an extra Load Extended Address operation takes place just before
starting the program. Hence the complete sequence of operations is:

Initialize the CPU, Bootstrap, and all system devices.

Load Initial Address.

Load Extended Address.

Deposit 32 words into memory.

Load Starting Address of the bootstrap program just deposited.

Load Extended Address.

Start the bootstrap program.

4.8 MAJOR PORTIONS OF THE MIS-E
A block diagram of the major portions of the MIS-E is shown in Figure 4-1. When power is applied to the computer, critical control flip-flops within the MIS-E are initialized so that the MIS-E is inoperative and the computer
can run normally. If the switch labeled SW on the operator's console is moved to the "down" position and then
to the "up" position, the MIS-E will operate.
NOTE
SW should be left in the "up" position when the MIS-E
is not being used. If SW is left in the "down" position,
the MIS-E will operate if the machine is stopped and the
console's OFF/POWER/PANEL LOCK switch is moved
to the PANEL LOCK position.

4-5

12 DATA {
LINES
OF THE
OMNIBUS

!----

12-BIT BY 32-WORD
DIODE MATRIX

DATA
OUTPUT
GATES

I
32-BIT SHIFT REGISTER

I
f--

I----I-----

I--I-----

I--I--I-----

OMNIBUS
CONTROL
SIGNALS

TIMING S. CONTROL

I---

I----- ADDRESS
MU LTIADDRESS
I--- PLEXER
JUMPE RS
I----I----I-----

I, F,S

I--I--I--I--I-----

I--~

I-----

t
SE-0375

Figure 4-1

MIS-E Block Diagram

4.8.1 Address and Data Information
Address information is stored in three sets of jumpers denoted as follows:
Function

Designation
10-111

Initial address. 10 is the most-significant bit. The address encoded in the I jumpers
is the first of 32 successive locations into which instructions will be loaded by the
~Y1!8-E.

50-511

Starting address. SO is the most-significant bit. This address is the address at which
the MIS-E will start the program after the bootstrap program has been stored.

F2, F1, FO

Field bits. F2 is the most-significant bit. These bits are loaded into both the I F and
DF of the Memory Extension Control, Type KMS-E.

4-6

In all cases, the presence of address jumpers indicates a binary 0; the absence of a jumper indicates a binary 1.
Unencoded MIS·E boards are shipped with all jumpers in place.
Data to be deposited in memory is encoded by the presence (binary 0) or absence (binary 1) of diodes in a 12-bit
by 32-word matrix. The positions of words and bits within words are clearly indicated in etch on the board; the
presence or absence of diodes and jumpers for standard bootstraps is shown on the engineering drawings.
4.8.2 Sequence of Operations
When SW is operated while the computer is on but not running, the MIS-E's timing and control logic is activated.
The MIS-E first grounds POWER OK H to initialize the computer. Simultaneously, it clears the 32-bit shift register that drives the diode matrix. The timing and control logic then loads I and F addresses into the CPU and
Extension Control, respectively, by enabling the appropriate address multiplexer and then placing signals onto the
OMNIBUS. These signals have already been described in Paragraph 4.7. The MIS-E then shifts a 1 into the first
bit of the 32-bit long shift register, enables the matrix data output gates, and starts the processor's timing chain.
Thus, the contents of the first word in the matrix are placed on the DATA BUS. Control signal MS, I R D ISAB LE L,
applied to the OMNIBUS, causes this word to be written into memory. The KEY CONTROL L signal causes the
next sequential address to enter the CPMA, KEY CONTROL L is allowed to go high during TS3 of the processor's
cycle so that the processor continues to run. At the end of each memory cycle (TP4) the single 1 is shifted down
the shift register, and a 0 is shifted into the first bit of the register. This process continues until all 32 words have
been deposited.
When the 1 reaches the last bit of the shift register, control circuitry causes the processor to stop. The timing of
the MIS-E is restarted. After loading the "S" and "F" addresses into the CPU and Extension Control, the processor is again started and the MIS-E's job is done.
4.8.3 Bootstrap Timing (Figure 4-2)
A timing diagram illustrating the primary timing and control signals within the bootstrap, as well as the processor
timing, is shown in Figure 4-2. The development of each signal is shown in the detailed logic.
4.9 DETAILED LOGIC DESCRIPTION
The following paragraphs present portions of the MIS-E logic. All illustrations are interrelated and, therefore,
should be considered collectively. The sequential operation of each circuit is presented in the system description.
4.9.1

Bootstrap Timing Logic (Figure 4-3)

A timing chain is created in the timing logic by connecting, in series, four time-delay flip-flops designated D1
through D4. The 74123 IC has a retriggering characteristic that makes an automatic restart capability possible.
However, the restart loop is concerned only with D3 and D4 and is controlled by the logical conditions of one
flip-flop designated ACTIVE and a second flip-flop designated DATA.
Refer to Figure 4-4 for details about the 74123 IC. The restart operation makes use of the last line in the truth
table, which states that the one-shot will initiate a timing cycle if the A and B inputs are enabled and the Master
Reset input (C) is brought from low to high.
Again referring to Figure 4-3, the logic to the right of D1 is used to ground POWER OK H and serves to control
the GO flip-flop. GO will set when D1 times out only if RUN L is not asserted (the machine is stopped). RUN L
also prevents the bootstrap from grounding POWE R OK H, which would otherwise stop the processor timing.
Therefore, once the bootstrap is activated, GO remains set until processor timing begins. RUN L results and clears
the GO flip-flop.
4-7

"SW
01111

"POWER OK H
"INITIALIZE H

GO
02 (01

D3(1)

04 (11

~r-------------------------------------'~{r,-------------------------------------------

~/.r-~~~~~~1~1~~~~~~~~

--~b~------------------~--------------~~~r========================
--~{
~
f--

----\_-~:,\

-H
--H )

~ \_----------------~~L--------180

~ D4{1I ~ D4i1l

\-------------------------r---\

ACTIVE (11
ADD ENABLE
(DATA 0)
DATA ENBLE
(DATA 1)
FIELD (1)
"MS,IR DISABLE L
"PULSE LA H
"MEM START L

DATA (1)

=:t==r-----~f--l

FIEI.D 11 j

rl-----

MS,lR,DIS

_~-_1---~haoc;
~r_-----------~:;===========================~~~-PL-A-.~~~P~L-A-~_-_-4~----_
---r---t_--_4---r~-_4--_+r__-,MEMr-_ _ _ _ _ _ _ _~~i-------------------+~-------+----~~
I

*LA ENABLE L
"KEY CONTROL L

ST ADD

INIT ADD

'-------\i H-------------------,
~

LA EN

r l- - - - - - -

KEY CONT L

ADD

~-~,--+-~--------------1\--------------------r-----+-F~IE~L-D-__
-+D-AT-A-8U-S--~-------

FIELD-DATA BUS
SECOND (11
SHIFT CLOCK H

---r----t_----_4'---r!--i--~I--_4~~--------~2~N~~

SYSTEM CLEAR L
"TSl
"TS2

SHIFT

CLEAR

1300c;

"TP4

LAST (1)

__-r____

lOOns

TS3

\rrlLT~P~4----------__----~

t_------r--+I'----r--il----~'i----------------------~Ir LAST WORD

RESTART
.. STOP L

350"

r--------+~--+---r--------+---,TS2

300ns

"TS4

LAST WORD

! : --ij--+--l-----,
1 ' : - - - - 250".---------'\, \,r+-----,
--+---t------i---r

"TS3

--l

SYSTEM

CLOCK

32NO

f-I---- ~

LU LAST(I,

I FH-------------------::R::-E:::ST=A-=R::-iT r---- f---

--L.r

---r----t-------,Ir-,-+--~r--4----r---------------------~'~Il~S~T~O~P------------------t_t_--1---~---4i______-4STARTPROC

INITIALIZETOi~bTR
BUS

AlD~D?TR:OTLOcPR (eo p~6c
AOOR TIMG

t--__~32-~04R.~~~UMP ---------

~~~ESSOR TIMING

NOTE;

ST1~bWG
TO BUS

sLi'G IoLrPR h~

ADDRTD BUS ADDR

RTU',Mlp'RGOGRA'M
RE- 'J376

Signals marked *appear on the omnibus. All other signals are internal to the MI8-E.

Figure 4-2 Bootstrap Timing

+5V

10K

+5V

20K

10K
27pf

INITIALIZE H
CRI
(TO ACTIVE B MS, IR DIS)
02(0)

LOAD
PULSE H

o 10-------'
+3V

LAST WORD (1) H (cj) TP4

SET GO

+5V
22K

+5V
470n

150pf

CLEAR
GO L

OV2--~~~~~e-d

+5V

NOTE:
Letters in circles refer to woveforms shown in Figure 4-5

Figure 4-3

Bootstrap Timing Logic

BE -0377

+5V

C
EXTJR EXT

ri,

14(6)'

, 15(7)

Q
13(5)

Q
4(12)

3(11)

NOTE,
Pin numbers not in parentheses ore for delay 1 i
those within parentheses are for delay 2.
INPUTS

OUTPUTS

t
H

--u--u-

JL
JL

~ =TRANSITION FROM HIGH TO LOW

TRANSITION FROM LOW TO HIGH

JL LJ = OUTPUT WAVEFORMS(DURATION DETERMINED
BY THE RAND C ATTACHED TO THE ONE-SHOT)
8E-0378

Figure 4-4 74123 Logic Diagram and Truth Table
A positive-going transition on the SW line sets Dl for a period of 1.2 }1S. On the input line, the RC network and
feedback loop remove any switch contact bounce. On the output of Dl (1), the circuitry asserts POWE R OK L
(if RUN L is not asserted) and asserts CLEAR GO L when RUN L is asserted. Because CLEAR GO L is connected

to the clear side of GO, the net result is:

If the computer is running, ignore the output of Dl (0).

If the computer is stopped and Dl triggers, set GO.

The conditions upon which CLEAR GO L is generated are shown graphically in Figure 4-5.
Signal POWE R OK H goes low shortly after Dl (1) goes high. This causes the M8330 Timing Module to create a
560-ms INITIALIZE H pulse to clear the processor and options. In the meantime, Dl becomes reset because the
1.2-}1s delay times out. This causes Dl (0) to go high; this transition clocks GO. GO (0) L half-qualifies the input
to D2. At the end of the 560-ms INITIALIZE H pulse, the trailing edge sets D2 for a period of 180 ns. The D2
(0) negative-going output sets the ACTIVE flip-flop and the DEP flip-flop and the trailing edge of D2 (0) sets D3
for a period of 500 ns. At the trailing edge of D3 (1), the negative-going transition sets D4. A restart path beginning with D4 (1) H and gated by ACTI VE (1) H and DATA (1) L generates LOAD PU LSE H. Signal LOAD
PU LSE H (trai!ing edge) clocks the FiE LD flip-flop on the first pass and clocks the DATA flip-flop on the second
pass. The trailing edge of each LOAD PULSE H causes D3 to start another timing cycle. Once the DATA f!ipflop is clocked, DATA (1) H inhibits LOAD PULSE H and hence another restart operation until LAST is set (following the 32-word dump operation). The last D4 (1) H with DATA (1) H asserts MEM START L. MEM START L

4-10

---I 1.21' s I+D1 (1)

_----JI

L-I__

C (LO IF EITHER AorB HIGH)

D
(LO ONLY IF A and B HIGH)

IFSW-H a
RUN L IS HIGH

F
G

CLEAR GO L

+3V - - - - - - - +3V - - - ,

~------

+3V - - - - - ,
CLEAR GO L

I..
NOTE:
The letters A-I refer 10 Figure 3 .

r--

L..----II

IF PWR OK H - L a
RUN L (H)

·1

WIDTH
DETERMINED
EXTERNALLY
8E-0379

Figure 4-5 CLEAR GO Signal Waveform Analysis
asserts RUN L in the timing module and RUN L asserts CLEAR GO L, which then resets the GO flip-flop. The
timing chain remains inactive until LAST WORD H sets the LAST flip-flop and with TP4 creates RESTART.
4.9.2 Bootstrap Control logic (Figure 4-6a and b)
Four flip-flops are shown in Figure 4-6a. LAST, ACTIVE, and DEP are cleared by POWER OK H being low.
ACTIVE (1) low clears SECOND. ACTIVE (0) now high generates SYSTEM CLEAR L. SYSTEM CLEAR L
clears the FIELD flip-flop, the DATA flip-flop, and the 32-bit shift register.
When the timing chain reaches 02, 02 (0) sets flip-flops DEP and ACTIVE. ACTIVE (1) H now half-qualifies
STOP Land DEP (1) H generates MS, IR DISABLE L. FIELD (1) Land ACTIVE (0) Lgenerate NOT FIELD H.
This signal, combined with SECOND (0) H, asserts INITIAL ADD L. Signal ACTIVE (0) L, combined with
DATA (0) H, asserts lA ENABLE L.
When the timing chain reaches 04 and generates LOAD PULSE H, PULSE LA H is asserted. This loads the initial
address into the CPMA. When 04 times out (at the trailing edge of LOAD PULSE HI. FIELD is clocked. FIELD
(1) H half-qualifies the DATA flip-flop clock input and FIE LD (0) L qualifies FIELD TO DATA BUS.
With FIELD set, ACTIVE set and DATA reset, FIELD TO DATA BUS, KEY CONTROL L and LA ENABLE L
cause the memory field to be addressed. The trailing edge of LOAD PULSE H also asserts RESTART and the
timing chain is again activated.

4-11

D2(D)L

MS,IR DIS L

+3V
PWR OK H
INITIAL
ADD L
STARTI NG
ADD L

SYSTEM
CLEAR L

+3V
TP4

}-+___~----- LAST WORD
(D) @II TP4

02(0)

STOP L

START MEMORY H
04(0)

DATA (0) ~"-_"

~------------~~~6K H

TP4

8E-0380

FIELD __
DATA BUS

NOT
FIELD H

ACTIVE(O)

KEY
CONTROL L

TS3

LA
ENABLE L

ADDRESS ENABLE

, - - - - - - DATA EN
MEM
START
SYSTEM
CLEAR

SYSTEM
CLEAR

04(1 )

+3V

PULSE LA H
LOAD PULSE H

27n

470n

+5V~
27n
8E-0381

b.
Figure 4·6 Bootstrap Control Logic

4·12

The next LOAD PULSE H at the trailing edge clocks the DATA flip-flop and again asserts RESTART. DATA (1)
H now half-qualifies MEM START. When D4 is again set, D4 (1) asserts MEM START L. D4 (0) L, combined
with DATA (0) L generates START MEMORY H and SHIFT CLOCK H. SECOND is clocked by the trailing edge
of START MEMORY H in preparation for STARTING ADDRESS. Signal MEM START L starts the processor
timing and SHI FT CLOCK H activates the 32-bit shift register. The 32-word dump operation now begins. Signal
LAST WORD H is asserted when the 32nd word is reached. LAST is clocked at TP4 and LAST (1) qualifies
STOP L. LAST (0) at TP4 asserts SYSTEM CLEAR L and restarts the timing chain. SYSTEM CLEAR L again
clears flip-flops DATA and FIE LD.
With SECOND set, the next address must be the starting address. When the starting address is loaded into the
CPMA, the timing chain goes through two additional restarts for the field address and Memory Start. When
MEM START L is again qualified, START MEMORY H is asserted. The trailing edge of START MEMORY H
this time clocks the ACTIVE flip-flop and ACTIVE (0) asserts SYSTEM CLEAR L. This prevents a second 32word dump and removes all bootstrap signals from the OMNIBUS.
4.9.3 Initial/Starting Address Jumper Network and Output Logic (Figure 4-7)
The initial and starting addresses, determined by jumpers I for initial address and S for starting address, provide a
12-bit word for each type of address. Removing a jumper causes a 1 of the corresponding bit to be placed onto
the DATA BUS. Otherwise a 0 will be submitted. The 7235 IC multiplexer selects either the initial address or
the starting address, depending upon which control line is asserted low.
4.9.4 Extended Memory Field Output Logic (Figure 4-8)
The extended memory field output logic is jumper-selectable to provide either a 1 or a on each corresponding bit.
Signal FIELD ~ DATA BUS H, developed in the bootstrap control logic, is used to apply 1s and as to the DATA
BUS.
4.9.5 12 x 32 Diode Matrix and Control Logic (Figure 4-9)
A partial illustration of the 12 x 32 diode matrix and control logic is shown in Figure 4-9. The diode matrix is
arranged in 32 columns and 12 rows to accommodate 32 12-bit words. Each word is applied to the output logic
gates by 8-bit parallel-out serial shift registers with the first word being applied by SH I FT CLOCK H during TS1.
Four 74164 ICs, each providing 8 outputs, are used to sequentially bias the diodes corresponding to the selected
row. Each time SHIFT CLOCK H is received, the 74164 IC shifts to the next sequential output line. Carry to
the next IC is accomplished by the last IC output line, except for the output line labeled "31 ". When 31 has been
reached, LAST WORD H is generated and applied to the LAST flip-flop. Signal SYSTEM CLEAR L is generated
in the control logic to clear the shift registers.

SECTION 5 MAINTENANCE
The general procedures concerning preventive and corrective maintenance are given in Chapter 4, Volume 1.
When corrective maintenance is required, the technician should use the maintenance program given in Section 2
of this chapter to determine the nature of the problem.
4.10 TROUBLESHOOTING
The option schematic, drawing number E-CS-M847-0-1, must be referred to for IC locations and pin numbers.
Test points are provided on the module to facilitate troubleshooting.

4-13

START ADD L

r "";AT;- l

INIT ADD L

BUS

so
+5V
+3V
-15V

DATA 0
11
15

+5V
+3V
-15V

8235

6
+5V
+3V
-15V

+5V
+3V
-15V

DATA 2

DATA 1

DATA 3

DATA 4

DATA 5

6 9
5

8235

2
S6
+5V
+3V
-15V

11
15

+5V
+3V
-15V

DATA 7

DATA 8

DATA 9

8235

DATA 10

11
15

+5V
+3V
-15V

'13

10
+5V
+3V
-15V

DATA 6

S8
+5V
+3V
-15V

I
I

DATA 11

L_ - J
8E-0382

Figure 4-7 Initial/Starting Address Jumper Network

4-14

+ 5V <>---'VV\,--...----I
DATA 06

DATA 09

+ 5V o---'VI.'V--_--I-~
DATA 07

DATA 10

+ 5 V o---'VI.'V--_--t----f
DATA OB

DATA 11

FIELD -

DATA BUS H
eE-0383

Figure 4-8 Extended Memory Field Output Logic

TS1---rD

~ATn
BUS

DATA 00

DATA 01

I
I
I
I
I

DATA 02

•
•

I
I

•

••

•

••
•

DATA 09

DATA 10

+5V
DATA ENAB H

DATA 08

J ..O - - - - - - - - - - - - 3 2 WORDS - - - - - - - -

I
I

DATA 11

I
I
I

I
I

L..J
8E~0384

Figure 4-9 12 X 32 Diode Matrix

4-15

4.10.1

MIS-E Bootstrap Diagnostic Program

The operation of the MI8-E Bootstrap Loader should first be verified by the MI8-E Bootstrap Diagnostic Program,
MAINDEC-8E-D11A-D, with corresponding MAINDEC operating procedures.
4.10.2 Direct Memory Access Control Signal Verification
Because the bootstrap loader uses direct memory access control signals in a manner similar to the operator's console (front panel), addressing memory and depositing information must be accomplished in the same manner.
Proper operation of signals such as PULSE LA H, LA ENABLE L, KEY CONTROL L, MEM START L, and
STOP L can be verified by performing the following procedure at the programmer's console:
Step

Procedure
Load Address 7777.

Load Address 0000.

Load Extended Address 7.

Load Extended Address O.

Deposit bit 11, then 10 ... 0 individually.

MA should equal 0014.

Load Address 0000.

Exam. You should see bit 11, then 10 ... 0 until the MA = 0014.

Turn Rotary Switch to the state position.

Depress and hold LOAD ADDRESS. No major state should be lit (F,D,EI.

Put SW up. SW indicator should be off.

Put SW down. SW indicator should be on.

Deposit in location 0/7240

1n402.
14

Load and start location O.

Turn Rotary Switch to AC position. AC should = 7777.

Depress CLEAR. AC should =0000.

Load location O. Deposit 5000.

Load and start location O. Run light should be on.

Depress SINGLE STEP. Run light should be out.

If the above procedures were completed successfully, the problem is in the MI8-E Bootstrap Loader hardware.
If the procedures indicate a malfunction, the MI8-E should be removed and the procedure tried again; the problem is in. the programmer's console, the CPU or the Memory Extension Control.
4.11

BOOTSTRAP HARDWARE TROUBLESHOOTING ANALYSIS

A very convenient troubleshooting aid is the Programmer's Console Status Display. The mere presence or absence
of anyone of the addresses used in the Bootstrap Loader option can localize the problem by the process of

4-16

elimination. If the problem is that the option fails to continue after the initial address is loaded and the RUN
lamp does not come on, the probable cause is the FIELD flip-flop or associated circuitry. However, if the field
address is loaded but the RUN lamp does not come on, the probable cause is the ENAB LE flip-flop or associated
circuitry. It can be assumed that all of the logic leading up to the logic that controls MEM START functions
properly.
If the RUN lamp comes on but the 32-word dump operation does not begin, it can be assumed that the DATA
flip-flop functions and the problem is somewhere in the 12 x 32 diode matrix logic. No dump might indicate
that the first shift register is malfunctioning.
If the RUN lamp comes on and the dump operation takes place but then fails to stop, the problem is in the Shift
Register or LAST flip-flop. The problem also causes the most-significant MA lights to run at half intensity. Examination of memory shows that all locations have been cleared. The reason for the failure is that the single 1
which should shift down the 32-bit shift register has been lost, probably because of a malfunctioning 74164 IC.
A malfunction will also occur if a 74164 IC picks up a bit. In this situation, fewer than 32 words will be deposited.
Some of these words will be the OR of two or more of the words encoded in the diode matrix.
When an incorrect word is deposited, the faulty diode can be located by determining which word and bit fails.
This is easily accomplished by addressing the bootstrap initial address and depressing the EXAM key. When the
rotary switch is in the MD position, each of the 32-bit words can be examined.
If bootstrap timing operates properly, the SINGLE STEP and CONTINUE keys may be used to single-step the
bootstrap. This technique may be used to find out if data is being deposited correctly.

SECTION 6 SPARE PARTS
Table 4-2 lists the recommended spare parts for the M 18-E. These parts can be obtained from any local DEC
office or from DEC, Maynard, Massachusetts.
Table 4-2
Recommended MI8-E (M847) Spare Parts
DEC Part No.
19-10436
19-09004
19-05547
19-09935
19-10041
19-05575
19-09705
19-09686
19-09485
19-09486
15-03100
11-00114
13-01423
10-00006

Description
IC DEC 74123
IC DEC 7402
IC DEC 7474
IC DEC 8235
IC DEC 74164
IC DEC 7400
IC DEC 8881
IC DEC 7404
IC DEC 380
IC DEC 384
Transistor DEC 3009B
Diode D664
Resistor 6.8K, 1/4W, 5%
Cap., 0.01 /1F, 100V, 20%

4-17

Quantity

2
2

CHAPTER 5
MP8-E MEMORY PARITY

SECTION 1 INTRODUCTION

5.1 MP8-E DESCRIPTION
The MP8-E Memory Parity option adds the circuits required to generate, store, and check the parity of memory
words. The MP8-E consists of three quad boards, which are inserted into the OMNIBUS. An H220 Memory
Stack is used to store parity for all words in memory. A G227 Memory X-V Driver is used to provide word select
currents. A special G105 Sense· Inhibit Module, which also contains lOT decoding, is used.
This option expands the memory system from 12 to 13 bits per word. When a word is written into memory, its
parity is computed, and odd parity (odd number of binary ones in the 13-bit word) is generated and stored in the
13th, or parity, bit. When a word is retrieved from memory, the parity of the 13-bit word is checked. If even
parity is detected, a memory error has occurred.
Much of the MP8·E is identical to the MM8·E 4K Core Memory described in Chapter 3, Section 4, Volume 1. The
MP8·E is discussed in Chapter 7 of the PDP-8IE & PDP-81M Small Computer Handbook. The reader should have
a thorough understanding of this material before proceeding.

SECTION 2 INSTALLATION
The MP8-E will be installed on site by DEC Field Service personnel. The customer should not attempt to unpack,
inspect, install, test, or service the equipment.

5.2 INSTALLATION
Use the following procedure to install the MP8-E:
Procedure

Step
Ensure power is off.
2

Install the MP8-E on the position indicated in Table 2-3 of Volume 1.

Install the four H851 Edge Connectors between the three modules.

5-1

5.3 ACCEPTANCE TEST
To check the MP8-E, run the MP8-E diagnostic program, MAINDEC-8E-D1DA. The program should be run 15
minutes for each 4K MM8-E in the machine; e.g., if the machine has 16K of memory, run the diagnostic for 1
hour. Refer to the program writeup for instructions on how to run the program.

SECTION 3 PRINCIPLES OF OPERATION
Parity in the PDP-8/E is handled in a somewhat unconventional manner. The conventional method of handling
parity is to use a special 13-bit memory stack and sense-inhibit system in each of the memory fields. In the
PDP-8/E, however, the standard memory, Type MM8-E, is used for data and instruction storage, regardless of
whether the system contains the parity option. When parity is desired, an additional memory is added. This
special memory handles the parity bit for all possible memory fields. The advantage of this method of handling
parity is that no special memory stack is required.
Figure 5-1 is a block diagram of the MP8-E. The lower half of this figure is identical to the lower half of Figure
3-33 in Volume 1; only the portion above the broken line is different. Eight of the twelve memory bits are used,
corresponding to the eight possible fields. The FIE LD signal into the G227 X-V Driver is permanently enabled.
Hence, during each memory cycle all eight parity bits are read and rewritten into the parity core memory.
Field select gating decodes the extended address bits (EMA 0, 1, and 2) and MD DI R L. The three EMA lines
determine which of the eight parity bits are to be examined and possibly modified. All other bits are automatically rewritten from the local parity sense register. If MD DI R L is low, the selected bit is rewritten from the
Sense Register. If MD DI R L is high, however, the parity of the twelve MD lines is written into the parity memory.
The selected bit read from the parity core memory is combined with the bits on the twelve MD lines. If parity is
erroneous, the ERROR flip-flop is set. The ERROR flip-flop can be interrogated by a SKIP instruction, and can
cause an interrupt. lOTs permit clearing of the Error flag, enabling the disabling of parity interrupt, and intentional reading of even parity for diagnostic purposes.

SECTION 4 DETAILED LOGIC
The G227 X-V Driver and H220 Memory are discussed thoroughly in Volume 1. No attempt will be made in
this chapter to duplicate that discussion. In addition, certain portions of the G 105 are identical to corresponding
parts of the G 104 described in Volume 1. These portions are:
B.

c.
d.

e.
f.

Strobe Control Logic
Sense Amplifiers
Sense Flip-flops
Inhibit Drivers
Current Control Circuit
-6V Supply and Slice Control

(Vol. 1, Paragraph 3.27.8)
(Vol. 1, Paragraph 3.27.9)
(Vol. 1, Paragraph 3.27.10)
(Vol. 1, Paragraph 3.27.12)
(Vol. 1, Paragraph 3.27.13)
(Vol. 1, Paragraph 3.27.14)

These parts will not be described here in detail.
5.4 FIELD SELECT GATING
The field select gating (Figure 5-2) connects the output of a SENSE flip-flop to the input of the corresponding
Inhibit Driver. The output of gate A must be low in order to rewrite a 1 into the parity memory.

5-2

110

CONTROL

,-4 .

SPECIAL IOT

t-l

SIGNALs-~-.::~~~~~tl~~~~========:-[ID~E~c~ID~OD~TI~N~GJ=========~=~C~O~N~T~R~O~L~G~W~5~_-1S;;:iP~~:tiUF~
G105

MD LINES

SKIP L

SK1P > INTERRUPT

GAT I NG

PARITY
JERROR FLIP FLOP
GENERA;l~:f------------------------+!l
AND GATING

GiG5

INT RQST L

G105

EMA2

EMAI

FI ELD SELECT GATING

EMAO
MD OIR l

LTIMING

SIGNALS

GlG5

G105

READ/WRITE
CONTROL LOGIC
SENSE

AMPLIFIER

AND

MEMORY
DRIVERS

INHIBIT

SLICE CONTROL

G105

-6V SUPPLY

STROBE

-t-

SENSE AMP

Gl05

~rRETURN1-~E"T!f.U
R~N'-{--r~-+--:I CONTROL LO G l e e LEAR
~
~_ _ _ _~G~\O~sJ-~~~~i

CURRENT CONTROL
GIG5

FIELD

01\

tTl

G105

----------,~

G227, H220

_ _ _ _L_~--===~
XOD

N~
11111

I#- -~

OOOOs

B-~ng~~~

r--~E AS FOR

778

MM 8-E

(XX77)*

z'"
«w

<!>u

zt0;:
0'"

DIODE

X-AX IS
SELECTION

Y-AXIS
DIODE SELECTION

4096

12 BIT WORO
CORE

MATRiX

MEMORY

MATRIX

OS'

G619/H220~

7_700 8

~'-rT-rr;-r~G6~\~9/~~H~2~20~~

ADDRESS DECODING

ANOS~fTLCEHCET~ON

Joo

MJO\

c=:JMEMOR'f TIMING SIGNALS

GENERATED IN THE TIMING

STACK DISCHARGE

ADDRESS DECODING
AND SELECTION

SWIT{HES

G227

Y CURRENT,I

!---!---1.L~S~O~UrR__C~E~
·'--1
I
G227

G227

~+-I~--+--+--~~+---+--+--4-~

TO THE MA BITS

r------I

MAOS

---I'---_--+__+ __+--+---I PO~~I~C~N~~~F

x CURRENT L-+_ _
SOURCE...-_ _ ~

GENERATOR

*SELECTED LINES WITH RESPECT

--==:i

G2271-

MA02

(XXQO)*

(77YY)*

------+---~---+-----~---------SOURCE

MAQ3

MA04

MAGS RETURN

Figure 5-1

WRITE

INHIBIT POWER OK

MP8-E Block Diagram

MADS

MA07

MAce

MAlO

MAl'

TO INHIBIT DRIVER,
BIT 0

-+----

INHIBIT ENABLE H - - - -.....

WRITE PARITY L

TO SEVEN
OTHER
CIRCUITS

MEM OUT H - - - - - i
(H IF MD DIR L IS L)

+5V

--f---..--+-

READ PARITY L - .....

EMA 2

OUTPUT OF SENSE
FLlP- FLOP 0

EMA 1

(H = 1)

EMA 0

BE - 0400

Figure 5-2 Field Select Gating

5-4

The EMA bits are buffered from the OMNIBUS and applied to the input of an 8251 Binary-to-Octal Decoder.
One of the output lines of the 8251 is low for any combination of EMA bits. All outputs of the 8251 are inverted and appl ied to portions of the field select gating logic.
If the FIE LD 0 H line in Figure 5-2 is low (field 0 is not selected), gates A2 and C are disabled. The output of
gate B is high, enabling gate A 1. Thus, the output of SENSE flip-flop 0 is applied, via gate A, to the input of the
Inhibit Driver, writing the previously read bit back into memory.
If the FIE LD 0 H line is high, Field 0 has been selected. The output of SENSE flip-flop 0 is gated onto the
READ PARITY L bus via gate C. The source of information for the Inhibit Driver is now a function of MD DI R L.
If MD DI R L is low during the latter half of the memory cycle (as it is for all fetches and non-auto indexed defers),
gate B is enabled and the SENSE flip-flop provides the rewrite data. If MD D I R L is high, gate A 1 is disabled,
gate A2 is enabled, and WRITE PARITY L provides the data for the Inhibit Driver. A low on WRITE PARITY L
writes a 1 in the parity bit.
5.5 PARITY GENERATOR
The heart of the Parity Generator is the 74180 8-bit parity generator IC which is shown in Figure 5-3. Two of
these I Cs are cascaded to form the 12-bit gated parity generator shown in Figure 5-4. Line A is high if a 1 has
been read as the parity bit from memory. As will be discussed in Paragraph 5.6, the ODD PARITY H line is
sampled part way through the memory cycle, before MD D I R L can go high. During the latter half of the memory
cycle, if MD DI R L goes high, odd parity is sent to the selected Inhibit Driver via the WRITE PARITY L line.
(The state of WRITE PARITY L is ignored by the field select gating if MD DI R L is low.) EVEN PARITY
CONTROL H is normally low, as will be described in Paragraph 5.8.
5.6 ERROR FLIP-FLOP AND GATING
Before discussing this logic in detail, a review of MD D I R L and its ramifications in the machine cycle is necessary. MD D I R L is a signal that indicates the source of information on the MD lines. At the beginning of every
memory cycle MD DI R L is low, causing the contents of the currently active memory's Sense Register to be placed
on the MD lines. At TP2, MD DI R L mayor may not change. It will not change during an For non-auto indexed
D cycle. It will change on all other cycles unless grounded by an option other than the CPU (for example, during
a BREAK cycle with data direction from memory to peripheral). In any event, if MD DI R L remains low after
TP2, no modification of memory is possible and the PDP-8/E may well be performing a "fast" 1.2-/1s cycle. If
MD D I R L goes high after TP2, the PDP-8/E is definitely performing a "slow" 1.4-/1s cycle and is most likely
modifying memory.
In a fast cycle, the MD lines have just about changed state by the leading edge of TP2, and there is insufficient
time for the Parity Generator to settle. During such cycles, the parity decision must be deferred to the trailing
edge of TP2 in order to gain 100 ns more time for the Parity Generator to settle. Since MD D I R L cannot change,
there is no danger that the information on the MD lines will change.
In a slow cycle, the MD lines have set up 200 ns before TP2. The parity decision must be made at the leading
edge of TP2, since MD DI R L may well change and place new information (the contents of CPU's MB Register)
on the MD lines.
The ERROR flip-flop and its gating are shown in Figure 5-5. Assume that the ERROR flip-flop is cleared, and
that the odd parity is received from the parity generator logic. At the leading edge of TP2, the SLOW flip-flop is
clocked. At the trailing edge of TP2, the FAST flip-flop is clocked. Since no parity error has occurred, both
flip-flops remain cleared.

5-5

5 ~ EVEN
INPUTS

6 ~

ODD IN 4 _ _---.J
EVEN IN 3 - - - - - . I

Figure 5-3 74180 8-Bit Parity Ie

MEM OUT H
(LOW IF MD DIR L IS HIGH)

READ PARITY L
(FROM FIELD SELECT GATING)

000
IN

MOOD H

z: ODD

MD01 H

z: EVEN

M002 H
MD03 H
MD04 H
MD05 H

EVEN
IN

ODD
IN

MD06 H
MD07 H

Mooa H
MD09 H

z: ODD

ODD PARITY
( TO ERROR
FLIP-FLOP GATING)

z: EVEN

WRITE PARITY L
(TO FIELD SELECT
GATING)

M010 H
M011 H

EVEN PAR ITY CONTROL H
(FROM SPECiAL rOT CONTROL)
(NORMALLY LOW)
8E- 0402

Figure 5-4 Parity Generator

5-6

ODD

o
ERROR
lTO SKIP GATING)
TP3 L
INITIALIZE L
DOD PARITY H
l FROM PARITY
GENERATOR)

SLOW

MEM OUT L--"L-_ _

PARITY ERROR H

r ......- - - - lTO INTERRUPT GATING)

o
FAST

MEM OUT H

TP2 L -~-----+--lc R
CLR ERROR L
lFROM IOT-----~--'
DECODER)
8E-0403

Figure 5-5 E R RO R Flip-Flop and Gating

Now assume that the ODD PARITY H line becomes low during a fast cycle. MEM OUT L is low and MEM OUT H
is high, since these lines are controlled by MD DI R L. The ODD PARITY H line, therefore, is low at the trailing
edge of TP2, when the FAST flip-flop is clocked. Gate A is enabled, presenting a high signal to the D input of the
ERROR flip-flop, and simultaneously requesting an interrupt. The SLOW flip-flop may have been set at the leading edge of TP2, but gate B is disabled because MEM OUT L is low.
Last, assume that the ODD PARITY H line becomes low during a slow cycle. At the leading edge of TP2, the
SLOW flip-flop is clocked and set. MD DIR L goes high, the result of a flip-flop in the CPU's timing generator being clocked by TP2. Therefore, MEM OUT H goes low, disabling gate A; MEM OUT L goes high, enabling gate B.
The MD lines change, the Parity Generator starts to respond, and the FAST flip-flop is clocked at the trailing
edge of TP2. The state of the FAST flip-flop is ignored because gate A is now disabled.
Regardless ofthe type of cycle, the D input of the E R RO R flip-flop is high well before TP3, allowing an interrupt
request to be generated during the current memory cycle (if the interrupt system is enabled). At the trailing edge
of TP3, the ERROR flip-flop is clocked, setting the ERROR flip-flop. During all succeeding memory cycles, the
D inputs to both the FAST and SLOW flip-flops are high, maintaining the error condition. The three flip-flops
remain set until CLR ERROR L is generated in the lOT decoder logic (discussed in Paragraph 5.7). CLR ERROR

L clears FAST and SLOW at the leading edge of TP3. At the trailing edge of TP3, ER ROR (its D input is now low)
is clocked and thus cleared.

5.7 lOT DECODING AND SKIP, INTERRUPT GATING
A summary of the lOTs for the MP8-E is given in Table 5-1. The logic is shown in Figure 5-6. The device code
is decoded by a 314 gate in a manner similar to any OMNIBUS decoding scheme. As in any internal device, the

5-7

device must ground INTERNAL I/O L when it sees its device code to inhibit operation of the KA8-E. Decoding
of the lOT operation is done by an 8251 Binary-to-Octal Decoder.
The EPI Land DPI L signals are used to set and clear, respectively, the IRE (Interrupt Enable) flip-flop. The
CMP L and the SMP, CMP L signals are o Red together, gated with TP3, and 'the result used to clear both the FAST
and SLOW flip-flops in the ERROR flip-flop and gating logic. As was explained in Paragraph 5.6, the ERROR
flip-flop is then cleared at the trailing edge of TP3. The SMP L and the SMP, CMP L signal is ORed together and
the result ANDed with ERROR (1) to drive the SKIP L line of the OMNIBUS. The SKIP L line is also grounded
any time the SPO L line is grounded.
The one remaining output of the 8251, the CEP L line, is used to enable the special lOT control described in the
following paragraph.
NOTE
This lOT decoding scheme is somewhat special, and
should not be used as an example of general I/O decoding design.
Table 5-1
MPB·E lOT Summary
Octal

Mnemonic

6100

DPI

Disable MP8-E interrupts.

6101

SMP

Skip if no parity error.

6102

Description

Not used.

6103

EPI

Enable MP8-E interrupts.

6104

CMP

Clear parity error flag.

6105

SMP, CMP

Skip if no parity error, clear error flag.

6106

CEP

Check for even parity. Complement the
read parity but write odd parity in the
next EXECUTE cycle only. Used for
diagnostic purposes. Execution to a ROM
address results in no operation.

6107

SPO

Skip if MP8-E is in machine.

5.B SPECIAL lOT CONTROL
The CEP instruction gating requires additional comment. As shown in Figure 5-7, CEP ANDed with TP3 sets the
DAE flip-flop, causing one input of gate A to go low. The next time the computer's major state becomes
EXECUTE, OMNIBUS signal EL goes low. Gate A is fully enabled, generating EVEN PARITY CONTROL Hand
causing the output of gate B to go low. At the leading edge of TP2, the output of gate B goes high again; DAE
ciears; and EVEN PARITY CONTROL H is negated.
EVEN PARITY CONTROL H drives one input of the Parity Generator, causing the MP8-E to intentionally read
wrong parity to test the MP8-E logic. Since EVEN PARITY CONTROL H is negated at TP2 (before the memory
starts to rewrite), odd parity is written into the parity memory.

5-8

TO
INTERRUPT ENABLE
(IRE) FLIP-FLOP
,......-'---,

M003 H
M004 H --..._ _
M005 L
INTERNAL I/O L

MOOG H

M007 H - , - _ - "
MOOB H
I/O PAUSE L

OP1 L

M009 H
MOIO H
M011 H

SMP L

SKIP L

EPI L
CMP L

TO CLEAR

SMP. CMP L
CEP L

TO SPECIAL
lOT CONTROL

SPO L

Figure 5-6

SKIP L

lOT Decoding and Skip, Interrupt Gating

o
OAE

0----1C
TP2 L

INITIALIZE L

EVEN PARITY CONTROL H

CEP·TP3 L

(TO PARITY GENERATOR)
8E-0405

Figure 5-7 Special lOT Control

5-9

SECTION 5 MAINTENANCE
The MP8-E diagnostic program is a particularly good test of core memory stacks. If a stack operates properly in
the MP8-E, it is virtually certain to operate properly in any MM8-E, unless there is a problem with one of the four
bits that the MP8-E does not use. The MP8-E diagnostic should be run as a regular part of system maintenance.
Diagnostic messages and the program listing should serve to pinpoint any commonly encountered malfunctions.
The same procedures as described under memory troubleshooting in Paragraph 4.7, Volume 1 are applicable.
Note that the standard memory checkerboard programs are insufficient tests of the MP8-E, since a checkerboard
pattern of all 1s and all Os is used. The odd parity of all Os is 1. Li kewise, the odd parity of all 1s is 1. The strobe
adjustment procedure forthe MP8-E isthe same as for the MM8-E, with the exception of the checkerboard program used.

SECTION 6 SPARE PARTS
Table 5-2 lists recommended spare parts for the MP8-E. These spare parts can be obtained from any local DEC
office or from DEC, Maynard, Massachusetts.
Table 5-2
Recommended MP8-E Spare Parts
DEC Part No.

Description

12-10043
16-09651
16-09996
16-09478
16-10031-0

Rotary Switch
Transformer 8010
Transformer 6501
Transformer 1775
Delay Line, 100 ns

1
2

13-10032
13-02858
13-02956
13-04858
13-02953
13-03114
13-02871
13-04833
13-04856
13-04885
13-02941
13-03156
13-05128
13-05252

Resistor, 16.9 ohm, 6W, 1%
Resistor, 100 ohm, 1/8W, 1%
Resistor, 196 ohm, 118W, 1%
Resistor, 348 ohm, 1/8W, 1%
Resistor, 750 ohm, 1/8W, 1%
Resistor, lK ohm, 1/8W, 1%
Resistor, 1.21K ohm, 1/8W, 1%
Resistor, 1.96K ohm, 1/8W, 1%
Resistor, 4.64K ohm, 1/8W, 1%
Resistor, 9.09K ohm, 1/8W, 1%
Resistor, 14.7K ohm, 1/8W, 1%
Resistor, 34.8K ohm, 1/8W, 1%
Resistor, 56.2K ohm, 118W, 1%
Resistor, 68.1 K ohm, 118W, 1%

1
2

13-10071

Thermistor, lK, 1%

11-05275
11-00114
11-09991
19-10010

Diode D672
Diode D664
Zener Diode 114M6, BAZl
Diode Pack DEC 2501

Quantity

7
10

1
2

(continued on next page)

5-10

Table 5-2 (Cont)
Recommended MP8-E Spare Parts
DEC Part No_

Description

15-02155
15-01881
15-03100
15-10062
15-09649
15-10015
15-05312
15-03409-01

Transistor DEC 1008
Transistor DEC 2219
Transistor DEC 3009B
Transistor DEC 3734
Transistor DEC 3762
Transistor DEC 4008
Transistor DEC 4258
Transistor DEC 6534B

19-05575
19-05590
19-09004
19-09686
19-05580
19-05547
19-10724

IC DEC 7400
IC DEC 7401
IC DEC 7402
IC DEC 7404
IC DEC 7450
IC DEC 7474
IC DEC 74180

19-09056
19-09057
19-09267
19-05586
19-09967
19-09704
19-09485
19-09486
19-09594
19-09705

IC DEC 74HOO
IC DEC 74H10
IC DEC 74H11
IC DEC 74H40
IC DEC 74H74
IC DEC 314
IC DEC 380
IC DEC 384
IC DEC 8251
IC DEC 8881

5-11

Quantity
1

2
1
2
2

PART 3
REAL-TIME CLOCK OPTIONS

CHAPTER 1
REAL-TIME CLOCK OPTIONS

SECTION 1 INTRODUCTION
Three real-time clock options are available for use with the PDP-8/E. The DK8-EA and DK8-EC are similar; each
consists of a clock frequency source and control logic contained on a single quad module that plugs into the
OMNIBUS. These two clock options cause program interrupts of the PDP-S/E at predetermined intervals that
are not subject to program control. The options can be used by the programmer to sample processes or to count
events. The DKS-EP, a more sophisticated clock option, provides a large amount of program control. It provides
the means to measure and/or count intervals and events in different ways. This option is discussed in detail in the
LAB 8-E Maintenance Manual. Only the DKS-EA and DKS-EC are discussed here.

SECTION 2 BLOCK DIAGRAM
The difference between the DKS-EA and DKS-EC options is the way in which the clock frequency source operates. The DKS-EA derives a clock frequency of 100 Hz (for 50-Hz primary power) or 120 Hz (for 60-Hz primary
power) from a power supply ac voltage. The DK8-EC derives a clock frequency of 1 Hz, 50 Hz, 500 Hz, or 5 kHz
from a 20-MHz crystal-controlled oscillator. Because the options are similar in all other respects, the logic description pertains to both, except when the clock frequency logic is discussed. Reference designations on logic
symbols, E3, E12, for example, are for reference only. They mayor may not coincide with the reference designations on a specific schematic drawing.
Figure 1-1 is a block diagram of the DKS-EA/C. The control logic consists of the select logic, the I NTE R RUPT
flip-flop logic, and the clock flag logic. The clock frequency is provided by the cl6ck logic.
When an lOT instruction causes I/O PAUSE L to be asserted by the CPU Timing Generator, the option select
logic decodes bits MD-03 through MD-11. The INTERNAL I/O L signal is asserted to direct the positive I/O bus
interface to ignore the lOT instruction. The three instructions that pertain to the DKS-EA/C are 6131,6132,
and 6133. 6131 and 6132 are used in the INTERRUPT flip-flop logic where they set and clear, respectively, the
I NTE R R UPT flip-flop. If this flip-flop is set, the clock flag is logically connected to the interrupt system. Upon
receipt of an interrupt request, the computer begins to execute the interrupt servicing routine to determine the
identity of the requesting device. When the 6133 instruction in the servicing routine is decoded, the clock flag
logic asserts SKIP L. At the same time, the CLOCK FLAG flip-flop is cleared. The computer then proceeds to
the subroutine associated with the Real-Time Clock option. Both the INT RGST L and SKIP L signals are negated.
The next clock pulse asserts INT RGST L again and the procedure is repeated. Each succeeding clock pulse
causes an interrupt request until the 6132 instruction clears the INTER RUPT flip-flop.

1-1

INTERNAL 1/0 L

I
* 110 PAUSE L --+
* MD03-11

SELECT
6131
6132

SELECT
LOGIC

INTERRUPT
FIF LOGIC

r---

CLOCK FLAG
LOGIC

* INT RQST L
* SKIP L

CLOCK
LOGIC
6133

*OMNIBUS SIGNALS

8E-0159

Figure 1-1

Real-Time Clock (DK8-EA, DK8-EC), Block Diagram

SECTION 3 DETAILED LOGIC

1.1 SELECT LOGIC
The select logic is shown in Figure 1-2. The SELECT signal is asserted by NAND gate E5 when a 613X instruction
is decoded. The SELECT signal, in turn, asserts INTERNAL 110 L, which causes the positive 110 bus interface to
ignore the lOT instruction. The SE LECT signal is gated with bits MD-09 through MD-11 to provide instruction
6131,6132,or6133.

1.2 INTERRUPT FLlP·FLOP LOGIC
The INTERRUPT flip-flop logic is shown in Figure 1-3. The flip-flop, Ell B, is cleared by INITIALIZE; it can be
set by the first clock pulse following power turn-on. This flip-flop remains set until cleared by the 6133 instruction, as is discussed in Paragraph 1.3.
The first TP1 pulse to be generated after E11 A is set causes fl ip-flop E7 to be set; the 1-output of E7 provides
the desired high level at one input of NAND gate E9. The other input of the gate is from the l-output of the
INTERRUPT flip-flop. If the select logic decodes 6131, the INTERRUPT flip-flop is set at TP3 and E9 asserts
INT RQST L.
The 6132 instruction is used to disable the interrupt capability of the option. It, I ike the 6131 instruction, is
contained in the background program and, when decoded by the select logic, clears the INTERRUPT flip-flop at
TP3.
1.3 CLOCK FLAG LOGIC
The clock flag logic is shown in Figure 1-4. When 6133, which is usually located in the interrupt servicing routine,

is decoded by the select logic, NAND gate E9B in the clock flag logic asserts SKIP L (E7 is set at TP1 following
power turn-on). At TP3, the CLOCK FLAG flip-flop is cleared. Simultaneously, the CPU SKIP flip·flop, which
is conditioned by SKIP L, is set. This action causes the program counter to be incremented during TS4. Thus,
the instruction following 6133 is skipped and the next instruction that is performed is the first instruction of the
real-time-clock subroutine. At TP1 of this instruction, latch E7 in the clock flag logic is cleared, negating both

1·2

+3.5V--~

M003 L

INTERNAL 110 L

I-<..--------SELECT
M004 L

MOOG L
M005 L - t - - - - - - - - - - '
M007 L - t - - - - - - - - - - . . J
MOOB L - t - - - - - - - - - - - '

M009 L

MOll L

M010 L

1/0 PAUSE L

8E-O'SO

Figure 1-2 Select Logic

INT RQST L and SKIP L. The next interrupt request occurs when the CLOCK FLAG flip-flop is again set by a
clock pulse and the following TP1 pulse causes E7 to be set.
Naturally, the time required for the service loop must be less than the clock period. Furthermore, the clock is
free-running. Hence, the program must be able to handle two nearly simultaneous clock interrupts when the
CLOCK INTERRUPT flip-flop is enabled. Consider what happens if the clock is enabled just before it is ready
to generate a clock pulse. The enabling process generates an interrupt and the CPU may still be executing the first
clock subroutine when the option requests the second program interrupt. If this occurs, the interrupt servicing
routine is entered immediately after the first clock subroutine is exited, and the second execution of the subroutine occurs just after the first. Thus, an uncertainty of one count is always present because of the unknown clock
phase.
1.4 CLOCK LOGIC
-1.4.1

DK8-EA

The clock logic for the DKS-EA is shown in Figure '-5. The DKS-EA connects to the 2S-Vac output of the H724
or H724A Power Supply via the cable supplied with the option. The cable connects to the option with an S-pin
connector (2 pins are not used). Each ac input is wired, via the board etch, to an adjacent pin so that the 28 Vac
is not dead-ended (the KP8-E Power Fail and Auto Restart option also uses the 28-Vac output of the power supply;
if both options are in the system, one is connected directly to the power supply, while the second is connected to

J, of the first).

1-3

0132

TP3

SELECT

INT RQST L

TP1----\

NOTE:
See VoLt Appendix A for details af DEC7474IC
C1.0CK

+3.5V

BE-DI61

Figure 1-3 INTERRUPT Flip-Flop Logic

The circuit consists of a full-wave rectifier, a clamp, and a Schmitt trigger. The rectified ac voltage is clamped to
+5V by D 1 to prevent damage to the E 12 IC. E12 is wired as a Schmitt trigger and its output is a reasonably
well-shaped square wave with a pulse repetition frequency that is twice the frequency of the primary power
source.

1.4.2 DKS-EC
The clock logic for the DK8-EC is shown in Figure 1-6. The basic clock frequency, 20 MHz, is provided by a
crystal-controlled oscillator (see the option schematic). This frequency is divided by a factor of four by the two
J-K flip-flops, E 17 and E18 (when both the J and the K inputs are high, the 1 output is changed with each positive transition at the C input). The 5-MHz clock frequency is applied to a chain of DEC 7490 decade counters,
each counter except the last is wired to divide by ten; the last counter is wired to divide by five. The output of
counter E4, E8, E12, or E21 can be selected by connecting a jumper wire, as illustrated in Figure 1-6. (The option is manufactured with an etch connection from the output of E21 to the terminal that connects to the
CLOCK F LAG flip-flop; if a clock fieqUeilCY of other than i Hz is desired, cut the etch connection and wire a
jumper from the terminal to the desired flip-flop output.)

1-4

TP1

CLOCK

+3.5V

CE11AO
C
0
CLOCK
E7
DEC
FLAG
DEC
7475
D747"1 t - - - - i D
1

E11B(1)
INT RQST L

SKIP L
SELECT
6133

8E-0162

Figure 1-4 Clock Flag Logic

A
+5V

14 VAC

D1
TO H724
OR H724A

TO CLOCK
FLAG F/F
F=100Hz
OR 120Hz

14 VAC

SE-OI63

Figure 1-5 Clock Logic DKS-EA

1-5

1Hz

8E-0164

Figure 1-6 Clock Logic, DK8-EC

SECTION 4 MAINTENANCE
General instructions concerning preventive and corrective maintenance are given in Chapter 4, Volume 1. When
corrective maintenance is required, use the MAINDEC-8E-D8AA maintenance program to determine the nature
ofthe problem. The option schematics, E-CS-M883-0-1, E-CS-M882-0-1, E-CS-M860-0-1, and E-CS-M518-0-1,
must be referred to for IC locations and pin numbers. Test points are provided on the option to facilitate troubleshooting.

SECTION 5 SPARE PARTS
Table 1-1 lists the M882/M883 spare parts. Spare parts can be obtained from any local DEC office or from DEC,
Maynard, Massachusetts.
Table ,-,
Recommended DK8-EA/DK8-EC - (M882/M883) Spare Parts
Description

DEC Part No.
19-9705

DEC 8881

19-9704

DEC 314

19-9485

DEC 380

19-9051

DEC 7490

19-9050

DEC 7475

19-9004

DEC 7402

19-5589

DEC 7470

19-5576

DEC 7410

19-5575

DEC 7400

19-5547

DEC 7474

19-9486

DEC 384

Quantity

(continued on next page)
1-6

Table 1-1 (Cont)
Recommended DK8-EA/DK8-EC - (M882/M883) Spare Parts
DEC Part No.

Description

18-9880

Crystal (M883 only)

16-9651

Pulse Transformer (M883 only)

10-9678

Capacitor 0.047 J.lF, 16-15 + 20%

10-1610

Capacitor 0,01 J.lF, 1OOV, 20%

10-0016

Capacitor 100 pF, 100V, 5%

10-0014

Capacitor 68 pF, 100V, 5%

10-0011

Capacitor 47 pF, 1OOV, 5%

10-0006

Capacitor 10 pF, 1OOV, 5%

10-1765

Capacitor 0,005 J.lF,

1-7

Quantity

PART 4
POWER-FAIL OPTION

CHAPTER 1
KP8-E POWER-FAIL AND AUTO-RESTART

SECTION 1 INTRODUCTION
The KP8-E Power-Fail and Auto-Restart option monitors the computer's primary power source and initiates a
controlled shut-down sequence if a power failure occurs. This power-fail sequence protects the operating program
by storing the contents of the PC Register, AC Register, MO Register, and the Link in known memory locations.
When normal primary power is restored, the KP8-E automatically restarts the computer in location 0000, 0200,
1000, 2000, or 4000. The address is selected by installing a jumper.
The KP8-E Power-Fail and Auto-Restart option consists of the M848 quad module which is inserted into the
OMNIBUS and connected to the computer ac power supply by a 7007128 power cable. The PDP-8/E supplies
28 Vac and the PDP-8/F and PDP-81M supply 56 Vac. The 56 Vac input is reduced to 28 Vac by removing a
jumper (W2) on the M848 module.

SECTION 2 M848 BLOCK DIAGRAM
The KP8-E block diagram is shown in Figure 1-1. The power monitor logic checks the PDP-8/E power supply
28 Vac output or the PDP-8/F and PDP-81M 56 Vac power supply output which reflects the condition of the
primary power source. If line voltage drops below a predetermined minimum value, the UP signal is negated and
the PWR LOW flip-flop is set, asserting the OMNIBUS INT ROST L signal. Filter capacitors in the power supply
guarantee continued operation for 1 ms; this is sufficient time for the interrupt request to be recognized and the
program interrupt routine to be carried out (because of the time limitation, the KP8-E SPL instruction, Skip on
PWR LOW flag, 6102, should be the first status check made by the program interrupt routine).

SECTION 3 M848 DETAILED LOGIC
1.1 SELECT LOGIC
The select logic is shown in Figure 1-2. When the SPL instruction (6102) is decoded, the logic asserts the
INTERNAL 1/0 L signal that causes the Positive 1/0 Bus Interface to ignore the lOT instructions. The status of
the PWR LOW flip-flop is checked; if the flag is set, indicating a power failure has occurred, the SKIP L signal is
asserted. The program then skips the next sequential instruction and jumps to a subroutine that begins executing
the power-fail routine.

1-1

r - - - - - - - - - - - - - - - -..- INTERNAL IIO L

IIO PAUSE L

6102 (SPL)

MD03-11

SKIP L

D - - " I N T RQST L

r-.L..--~

DOWN

56VAC or 28VAC
(H724 OR H724A 28VAC)
(H740D 56VAC)

AUTO
RESTART
LOGIC

_____ INITIALIZE

t - - - - - - - IND I
t - - - - - - - KEY CONTROL L
t - - - - - - - LA ENABLE L
t - - - - - - - MS. IR DISABLE L
1 - - - - - - PULSE LA
1 - - - - - - MEM START L
_ _ _ DATA 0

-DATA 1
-DATA 2
-DATA 4

8E-0165

Figure 1-1 M848 Power-Fail and Auto-Restart Option, Block Diagram
1.2 POWER MONITOR LOGIC
The power monitor logic is shown in Figure 1-3. The logic directly monitors the ac output of the computer's
power supply, to which the option is connected by a cable. The cable connects to the option with an 8-pin connector (2 pins are not used). Each ac input at J 1 is wired via the board etch to an adjacent pin so that the ac is
not dead-ended (the DK8-E Real-Time Clock option (line frequency) also uses the ac output of the power supply;
if both options are in the system, one is connected directly to the power supply while the second is connected to
J 1 of the fi rst) .
NOTE
The W2 jumper must be removed when the KP8-E is installed in a PDP-8/F or PDP-81M.
The ac is full-wave rectified and applied to two comparator circuits. One of these circuits includes transistor pair

04/05 and initiates the auto-restart sequence. The second circuit includes transistor pair 02/03 and initiates
the power-fail sequence. There are two thresholds for power fail. An upper threshold, 103 Vac, which is used to
start the RESTART logic, and a lower threshold, 93 Vac, which sets the PWR LOW flip-flop. 04 and 05 detects
the 103 Vac threshold; 02 and 03 detect the 93 Vac threshold. The upper and lower thresholds have a tolerance
of ±1.0V. 02 provides a trigger for one-shot E7 when the amplitude of the line voltage, and hence, the amplitude
of the ac input of J 1, is above the desired minimum. The -10.3 Vdc reference voltage is generated by a precision
voltage regulator that is not shown (see the option schematic for this and for the resistor network).
The resistor network is equipped with jumpers that are installed to keep the power-fail line voltage thresholds at
their correct value, independent of nominal line voltage. Table 1-1 shows the jumpers that should be installed
for 115/230, 220, and 240 Vac inputs.
WARNING
The two threshold adjustments on the resistor network
should not be adjusted in the field. These potentiometers
are set at the factory to compensate for component
tolerances.

1-2

M03

M04 L

INTERNAL 110 L

M05 L - 1 - - - - - - ,
M06 L

M07 L

SKIP L

MOll

INT RQST L
MOS L

I/O
PAUSE
L

8E-0166

Figure 1-2 Select Logic

-15V

+5V

OIR

15ms
O~-+-----'

R28

R31

R24

R30

-10,3V (REF)

AUTO RESTART)
( LOG I C CLEARS
PWR LOW FF

INT
RQST
L
(CPO

UP (To AUTO RESTART LOGIC)

* COMPUTER
W2 MUST BE REMOVED WHEN INSTALLED IN PDP-B/M
TO REDUCE 56VAC TO 2BVDC
Figure 1-3 Power Monitor Logic
Table 1-1
Ju mper Installation
Line Voltage
(Nominal Value)
115/230
220
240

Add Jumpers Labeled
115/230 and 240
220
115/230

Remove Jumpers
Labeled
220
115/230
220 and 240

Figure 1-4 presents idealized waveforms to illustrate how E7 is controlled by the comparator circuit. If the line
voltage is above the selected minimum value, the positive transition at the coiiector of Q2 will be of sufficient
amplitude to trigger E7. Because the period of the collector waveform is less than the triggered delay time of E7,
the one-shot will remain active. If the line voltage falls below the minimum value for as little as one-half cycle, as
illustrated, E7 times out and an interrupt request is generated. Even though the power recovers almost instantaneously, the power-fail sequence is carried out.
The timing diagram shows the UP signal being asserted by the half-cycle immediately following the missing halfcycle. Thus, the auto-restart sequence begins 1.5 seconds later, as detailed in the following paragraphs.
1-4

56 or 28 VAC--+---~--~--~--~--~r---+-~+---~--~---+--~~

(1)

DOWN

--~------~---r---+--------~~

(1) --+---+----1----+----+----.,'----+--!

PW R

LOW

INT

RQST L
BE-OIGS

Figure 1-4 Power Fail Timing
1.3 AUTO-RESTART LOGIC
The computer must resume operation by executing the instruction that was stored in the starting location by the
power-fail routine. Consequently, the CPMA Register and the I F and OF Registers of the KMS-E option must be
loaded with the starting address before CPU timing is renewed. Furthermore, the CPU Major State Register must
be manipulated so that a FETCH cycle is entered when timing begins. The auto-restart logic meets these requirements by simulating some of the operations that normally occur when the programmer's console is being used.

1-5

Thus, to load the CPMA Register with the starting address, the auto-restart logic first asserts the LA ENABLE L
signal (at the same time, the MS, I R DISABLE L signal is asserted, this signal places the CPU in the DMA state,
ensuring that the first timing cycle begins in the FETCH state). The LA ENABLE L signal:

ensures that only "bus" information is placed on the DATA 0-11 lines; because nothing has access
to "bus" at this time, the DATA 0-11 lines carry the starting address jumper selected at the output
cf E3 (Figure 1-5) (Volume 1, Section 5, Paragraph 3.3.3, for clarification),

causes the address on the DATA 0-11 Iines to be gated through the CPU Major Register gating to
the MAJOR REGISTERS BUS.

After a delay to ensure that the control lines have settled, the logic asserts PULSE LA. This signal causes the CPU
to generate the CPMA LOAD L signal that loads the CPMA Register with the starting address. CPMA LOAD L
also sets the F flip-flop of the Major State Register; thus, a FETCH cycle will be entered when timing begins.
I NDl is asserted at the same time as LA E NAB LE to ensure only the starting address bits are on the bus if the
programmer's console is not installed (Volume 1, Paragraph 3.33.10).
When the CPMA Register has been loaded and the F flip-flop set, the auto-restart logic asserts the KEY CONTROL
L signal. After a delay that enables the control line to settle, PULSE LA is asserted again. However, because
KEY CONTROL L is true, CPMA LOAD L is not generated by this assertion of PULSE LA, nor is the Major State
Register clocked.
Rather, the Os on the DATA 6-11 lines are loaded into the I F and DF Registers of the KMS-E option (the autorestart logic allows for the KMS-E option even if the option is not contained in the system). After this assertion
ofthe PULSE LA signal, the MS, I R DISAB LE L, IND1, and LA ENABLE L signals are negated and a final delay
period is allowed. When this delay times out, MEM START L is asserted, initiating CPU timing, and the computer
fetches the instruction from location 0000, 0200, 1000, 2000 or 4000 of field O. The starting address is determined by the output of E3 (Figure 1-5) which pulls DATA 0, DATA 1, DATA 2, or DATA 4 low at the same
time PULSE LA is asserted.
The auto-restart logic is shown in Figure 1-5; the relative timing of the logic is shown in Figure 1-6. The
ENABLE/DISABLE switch, Sl, must be in the ENABLE position (up) if the automatic restart is to function
after a power interrupt has occurred. If S1 is in the DISABLE position, the PWR LOW flip-flop is cleared when
ac power comes up, but the program must be restarted manually.
The auto-restart sequence begins when the power monitor logic asserts the UP signal. The positive transition of
this signal triggers one-shot multivibrator E2. During the active 1.5 seconds of this one-shot, all system equipment (computer, peripherals, options) can complete operations initiated by the OMNIBUS INITIALIZE signal.
At the end of the 1.5 second delay, bistable latch E5 is triggered and the LA flip-flop is set. This latch sets the
KC (key control) flip-flop, clears the PWR LOW flip-flop, and triggers the E lone-shot (the O-output of E2 provides a required high signal at one input of E 1; as the timing diagram illustrates, this high precedes the E 1 trigger
signal by an appreciable amount of time). The l-output of the LA flip-flop asserts the LA ENABLE L, INDl and
MS, I R D ISAB LE L signals. The E lone-shot, when it times out after 250 ns, triggers one-shot E4, which is active
for 100 ns. During the 100 ns period, NAND gate E6 is, enabled and PU LSE LA is asserted. Thus, the CPMA
Register is loaded and the FETCH flip-flop is set. The El one-shot is retriggered, via NOR gate E6C, coincidently
with the leading edge of the PULSE LA signal; while the KC flip-flop is cleared 100 ns later to assert the KEY
CONTROL L signal. When E 1 times out the second time, PULSE LA is produced again. Thus, the I F and DF
Registers are loaded at this time. As before, E 1 is retriggered coincidently with the leading edge of PULSE LA.
At the end of PULSE LA, when E4 times out for the second time, the LA flip-flop is cleared, and LA ENABLE L
and MS, I R D ISAB LE L are negated.

1-6

(CU2)
INDI

(BM2)
LA ENABLE L

( AJZ)
MEM START L

(CVI)
MS, IR DISABLE L

DIR (0) H
DOWN H

(DU2)
KEY CONTROL

TPI (CD2)

DATA 0
DATA
DATA 2

+5V

DATA 4
NOTES'
, . See Appendix A for DEC 9601 and 7475 IC details.
2.51 shown in Enable Position.
3. Omnibus pin nurn~ers ore shown for Omnibus Sionais.

+5V

(DRZ)
PULSE LA

5,°
ENABLE/DISABLE
AUTO RESTART

+5V
L-----------------------------------------------------INITIALIZE

Figure 1-5 Auto-Restart Logic

UP/ON FF

155ec

(1.55eC

(AC LiNE >105VAC)

OLYF5~

CONT~

KEY

INO

(O-K.C. @)

TPI)~

1%M

ME,M START
________ __________________________________________-J
LA~

ENA.~~~~~

MS,IR OISA

~~~~~~__________________________________________-J

P L LSE LA _____________________--l

2~;On5

O.S _____--I

lOOns O.S. _____________________--l
8E-0170

Figure 1-6 Auto-Restart Timing

When E3 times out for the third time, it once again triggers E4. However, because the LA flip·flop is now clear,
no PULSE LA signal is produced. Instead, the l·output of E4 asserts MEM START L and CPU timing begins by
fetching the instruction in the starting location. At TP1 time of this FETCH cycle, the KC flip·flop is set by NOR
gate E6A and the KEY CONTROL L signal is negated.
The DI R (Direction) flip·flop ensures that a Restart Sequence is initiated only when ac voltage is rising, through
the Restart threshold toward normal line Voltage Condition.

SECTION 4 MAINTENANCE
General instructions concerning preventive and corrective maintenance are given in Volume 1, Chapter 4. When
corrective maintenance is required, the technician should use the maintenance program, MAINDEC-SE-DOKC-D
(D), to determine the nature of the problem. The option schematic, drawing E-CS-M848-0-1, must be referred
to for I C locations and pin numbers. Test points have been provided on the option to facilitate troubleshooting.
The threshold adjustment on the resistor network, which supplies the 10.3 Vdc reference, should not be adjusted
during troubleshooting and maintenance operations.

SECTION 5 SPARE PARTS
Table 1-2 lists recommended spare parts for the KP8-E. These parts can be obtained from any local DEC office
or from DEC, Maynard, Massachusetts.

Table 1-2
Recommended KP8-E Spare Parts
DEC Part Number
11-09991
11-00114
11-00275
15-04338
15-03409-01
19-05547
19-05575
19-05576
19-09004
19-09050
19-09373
19-09486
19-09705
19-09971
19-09972

Description
Diode, AZl-1/4M, 6.8V
Diode, D664
Diode, D672
Transistor, 65318
Transistor, DEC 65348
IC DEC 7474
IC DEC 7400
IC DEC 7410
IC DEC 7402
IC DEC 7475
IC DEC 9601
IC DEC 384
IC DEC 8881
iC DEC 6380
IC DEC 6314

1-9

Quantity

PART 5
INTERPROCESSOR OPTIONS

CHAPTER 1
DBS-E INTERPROCESSOR BUFFER

SECTION 1 INTRODUCTION
The DB8-E Interprocessor Buffer is designed to plug directly into the PDP-8/E OMNIBUS. This option allows
two PDP-8/E Computers to transfer data between themselves, one 12-bit word at a time, at a software-limited
rate of 50 kHz. The DB8-E can also be used to transfer data to user-designed logic on single-ended data lines.
The basic DB8-E option has one M8326 Module and one BC08-R cable (up to 100-ft long). The DB8-EB has one
M8326 Module, two BC08-R cables, and two 5409209 Module Adapters for connection to user-designed logic.
Device codes on the module are jumper-selected between 50 and 57, allowing a maximum of eight Interprocessor
Buffers to be used in one PDP-8/E.

SECTION 2 INSTALLATION
The DB8-E Interprocessor Buffer is installed on site by DEC Field Service personnel. The customer should not
attempt to unpack, inspect, install, checkout, or service the equipment.
1.1

INSTALLATION

To install the Interprocessor Buffer, remove power from PDP-8/E No.1 and insert the M8326 Module into the
OMN IBUS. Refer to Table 2-3, Volume 1, for information about recommended module priorities (the DBS-E
is a non-memory option). Remove power from PDP-8/E No.2 and insert the second M8326 Module into its
OMNIBUS. Connect one of the BC08-R cables between J1 of the first and J2 of the second DB8-E Module.
Connect the second BC08-R cable between J2 of the first DB8-E and J1 of the second DB8-E. This will connect
the output of PDP-8/E No.1 buffer to the input of PDP-8/E No.2 module and the output of PDP-8/E No.2 to
the input of PO P-8/E No.1. Table 1-1 shows the pin-to-pin connections of J 1 and J2.
Table 1-1
Connection from J1 to J2
J1 Pin No.
J1TT
J1 RR
J1D
Jl F
J1J

Adapter

J2 Pin No.

Module Pins

J2C
J2E
J2SS
J2PP
J2MM

A1
B1
V1
Ul
T1

1-1

Adapter
Module Pins
V2
U2
A2
B2
C2
(continued on next page)

Table 1-1 (Cont)
Connection from J 1 to J2
Adapter

J1 Pin No.

Module Pins
Sl
R1
T1
N1
M1

J1 L
Jl N
J1 R
J1T
J1V
J1X
J1Z
J1BB
J1DD

L1
K1
Jl
Hl

J2 Pin No.

Adapter
Module Pins

J2KK
J2HH
J2EE
J2CC
J2AA
J2Y
J2W
J2U
J2S

D2
E2
F2
H2
J2
K2
L2
M2
N2

NOTE: All pins not listed are tied to ground.

1.2 ACCEPTANCE TEST
The acceptance test should be performed when the DB8-E Modules are installed and periodically after installation
to check the operation of the DB8-E logic. A working MS326 Test Module is needed to perform this test. The
programs in Section 5 can be used for preliminary operational checks.
Perform the following steps to check the DBS-E Modules installed in the PDP-S/E OMNIBUS.
NOTE
The PDP-8/E under test will be referred to as PDP-8/E
No.1; the PDP-8/E with test module used to check the
DB8-E Module in PDP-8/E No.1 will be referred to as
PDP-8/E No.2.
Procedure

Step

Remove the DBS-E Module from PDP-8/E No.2 and install the test module in its place;
connect the cables from the DBS-E Module to the test module.
2

Load binary loader in PDP-S/E No.1 and No.2.

Load diagnostic MAl ND EC-8E-DOPA-PB in PDP-8/E No.1 and No.2.

Run Part 1 and Part 2 of the test for 5 minutes each. There should be no errors.

If there are no errors, remove the test module from PDP-S/E No.2 and reinstall the
DB8-E Module.

To check the DB8-E Module in PDP-8/E No.2, repeat Steps 1 through 5 with test
module in PDP-8/E No.1.

1-2

SECTION 3 SYSTEM DESCRIPTION
The Interprocessor Buffer (Figure 1-1) receives or transmits data under control of programmed instructions from
the CPU. Data can be put on the DATA BUS of the OMNIBUS to be transferred to the accumulator, or data can
be taken from the OAT A BUS and transferred to another PDP-8/E or user's equipment.
The following instructions are used to program interprocessor data transfers.
Skip on Receive Flag (DBRF)
Octal Code:
Operation:

65X1
Skip if the RECEIVE FLAG equals one.

Read Incoming Data (DBRD)
Octal Code:
Operation:

65X2
Read the incoming data into the AC, clear the RECEIVE FLAG, and set the remote
PDP-8/E's DONE FLAG flip-flop.

Skip on Transmit Flag (DBTF)
Octal Code:
Operation:

65X3
Skip if the DON E F LAG equals one.

Transmit Data (DBTD)
Octal Code:
Operation:

65X4
Transfer the contents of the AC Register to the transmit buffer. Transmit data
and set the remote PDP-8/E's DONE FLAG.

Enable Interrupt (DBEI)
Octal Code:
Operation:

65X5
Enable the interrupt request line.

Disable Interrupt (DBDI)
Octal Code:
Operation:

65X6
Disable the interrupt line.

Clear Done Flag (DBCD)
Octal Code:
Operation:

65X7
Clear the DONE FLAG.

To transfer data from PDP-8/E No.1 to PDP-8/E No.2, data is loaded into the AC of PDP-8/E No.1 and transferred to the output buffer of its DB8-E using the 65X4 lOT. In addition to loading the output buffer, lOT
65X4 also sets the RECEIVE FLAG flip-flop in PDP-8/E No.2. When the program in PDP-8/E No.2 has sensed its
RECEIVE FLAG flip-flop, data is gated into the AC of PDP·8/E No.2 using lOT 65X2. lOT 65X2 then sets the
DONE flip-flop of PDP·8/E No.1, indicating the transfer was completed, and clears the RECEIVE FLAG flip·
flop of PDP-8/E No.2. PDP-8/E No.1 then clears its DONE FLAG using lOT 6507.

SECTION 4 DETAILED LOGIC
The logic in the Interprocessor Buffer will be broken into functional groups for discussion purposes. Figure '-1
should be used to understand the relationship between each group of logic.

'·3

1.3 DEVICE SELECT LOGIC
The device select logic is shown in Figure 1-2. Bits MD03 through MOll are gated by I/O PAUSE when a 65XX
instruction is decoded. An I NT I/O Land SE LECT L will be asserted to allow the operation decoder to receive
its input and to cause the positive I/O bus interface to ignore the lOT instruction.
1.4 OPERATION SELECT LOGIC
SELECT L in Figure 1-3 will enable the gates for bits MOOg through MOll and allow inputs to the operation decoder which is a BCD-to-decimal decoder. (Refer to Appendix A, Volume 1, for details about the 8251 IC.) The
decoder will supply signals that represent instructions 65Xl through 65X7. When a 65X2 instruction is decoded,
the C line select logic will pull CO and Cl low to allow data to be transferred from the DATA B US to the AC.
1.5 INTERRUPT AND SKIP LOGIC
The interrupt and skip logic is used to interrupt the program when a data transfer is required. To allow an interrupt to occur, the INT ENA flip-flop must be set (Figure 1-4) by a 65X6 instruction. The l-output of the INT
ENA flip-flop will go to E17 and assert one side of the AND gates allowing them to generate INT RQST L. A
more detailed explanation of interrupt and skip logic can be found in Volume 1.
Table 1-2 shows the signal and data flow required to transfer information between two PDP-8/E Computers.

MD3-MD8

110 PAUSE

SELECT L
MD 9
MD10

MDl1

OPERATION
DECODER

DATA LINE

- - - - - - - t SELECT LOGIC

65X5
65X6
65X7

65Xl

INITIALIZE
65X2

CLEAR FLAG

REC IEVE
FLAG

SKIP
LOGIC

INITIALIZE
65X 3

INITIALIZE
65X7

INTERRUPT
LOGIC

DONE FLAG

INITIALIZE
65X 6
65X5

INTERRUPT
REQUESTL

INTERRUPT
ENABLE

8£-0273

Figure 1-1

Interprocessor Buffer, Block Diagram

1-4

~COL
Cl

M003 L------------------------------,
M004 L ------01

M005 L ----+----------------~
M006 L-_+----n

INT I/O L

M007 L -_+--0
-

MOOS L

SELECT L

-_+---01

110 PAUSE L

8E-0274

Figure 1-2

Device Select Logic

6 5 X 2 ----;.----1

C1 L

TP3H~TP-3
SELECT L

M D 0 9 L __-'-__.f'O

65 X 1
M 0 10 L -----l----ClI

8251
E13

65 X 2
65 X 3
65 X 4

M 0 11 L ----+---01

65 X 5
65 X 6
65 X 7
BE - 0272

Figure 1-3 Operation Select Logic

1-5

INITIALIZE H

P-~-INITIALIZE
_t~

.~~

65X6 -

0-------------,

65X3

65X5
TP3-------~~~~--------------~---------~

h---I--4- INT RQST L
65X2·
}-------o J 1T 1

tr-It----- SK I P L
65Xl

8E-027S

Figure 1-4

Interrupt and Skip Logic

1.6 INPUT DATA GATES AND OUTPUT BUFFERS
The input data gates (Figure 8·5) will be enabled by a 65X2 instruction and transfer data to the AC via the
DATA BUS.
Table 1·2
Simultaneous Receive and Transmit Operation by
Two PDP·8/E Computers Using Interprocessor Buffer

PDp·8/E No.1 Data Transmitter

PDp·8/E No.2 Data Receiver

Data is transferred from AC to the DATA B US and
applied to the data inputs of buffer flip-flops by
programmed instructions.
A 6504 instruction clocks the buffer flip-flops and
transmits information to PDP-8/E No.2 and simultaneously sends a signal from J 1 R R of PDP-8/E
No.1 to J2E of PDP-8/E No.2.

at J2E. INT RQST if ENA is set, and SKIP generated,

The trailing edge of the signal at J2C sets the
DON E F LAG to indicate PDP-8/E No.2 has
read data.

6502 instruction gates data to DATA BUS. TP3 and
6502 instruction enable signal to J 1TT to be transmitted to J2C of PDP-8/E No.1.

Signal is removed from J2C when 6502 signal is removed from gate in PDP-8/E No.2.

The RECEIVE Flag is cleared by trailing edge of 6502

Data is received and RECEIVE FLAG is set by signal
and subroutine to read data is started.

instruction.

The DON E F LAG is cleared by 6507 instruction.
PDP-8/E No.1 is ready to transmit or receive data.

PDP-8/E No.2 is ready to receive or transmit data.

The SELECT L signal applied to the output data gates will allow 1s to be transferred from the DATA BUS to the
data input side of flip-flops in the output buffer. When a 65X4 instruction is generated, the clock input of the
flip-flop will be pulsed and the data will be transferred to the input gates of PDP-8/E No.2. This instruction will
also cause J1 RR to go high and set the FLAG in PDP-8/E No.2. The data transferred from the Interprocessor
Buffer is +3V for true (1) signals and O.OV for false (0) signals.

SECTION 5 MAINTENANCE
Refer to Volume 1 for maintenance information about PDP-8/E Computers. The acceptance test given in Section
2 should be performed when an error is suspected in the DB8-E.
1.7 DATA TRANSFER TEST
Perform the following programs to transfer data from the switch register of PDP-8/E No.1 to the AC of PDP-8/E
No.2.

1-7

DATA 11 L

R20

J2S
8E-0276

Figure 1-5 Input Data Gates and Output Data Gates and Drivers

PDP-8/E No.2

PDP-8/E No.1
Address

Contents

Address

Contents

200
201
202
203
204
205

7604
6504
6503
5202
6507
5200

200
201
202
203

6501
5200
6502
5200

After the programs are loaded, load address 200 and start both PDP-8/Es. The AC lights of PDP-8/E No.2 will
display contents of SR on PDP-8/E No.1. It is recommended that the following be tried.

a.
b.

c.
d.

Aii 1s
AliOs
A single 1 in each bit position
A single 0 in each bit position.

1-8

SECTION 6 SPARE PARTS
Table 1-3 lists recommended spare parts for the DB8-E. These spare parts can be obtained from any local DEC
office or from DEC, Maynard, Massachusetts.
Table 1-3
DBS-E Recommended Spare Parts
DEC Part No.

Description

19-05547
19-05575
19-05579
19-09486
19-09594
19-09686
19-09973
19-09971
19-09972

IC DEC 7474
IC DEC 7400
IC DEC 7440
IC DEC 384
IC DEC 8251
IC DEC 7404
IC DEC 97401
IC DEC 6380
IC DEC 6314

1-9

Quantity

PART 6
EXTERNAL BUS INTERFACE CONTROL OPTIONS

CHAPTER 1
KAS-E POSITIVE 1/0 BUS INTERFACE

SECTION 1 INTRODUCTION
The KAS-E Positive I/O Bus Interface permits use of a PDP-S/I or PDP-S/l type peripheral with the PDP-S/E. If
the peripheral is a data break device, a KDS-E data break interface must also be in the system. The concept of
data transfers and the interrelationship of the KAS-E Positive I/O Bus Interface, the KDS-E Data Break Interface,
and the OMNIBUS are explained in Chapters 6 and 10 of the PDP-8IE & PDP-81M Small Computer Handbook.
A detailed discussion of CPU operation during a programmed I/O transfer is presented in Volume 1, Chapter 3,
Section 6. The reader should be thoroughly familiar with this referenced information to benefit from the detailed logic discussion presented in this chapter.

SECTION 2 BLOCK DIAGRAM
Figure 1-1 is afunctional block diagram of the Positive I/O Bus Interface. When an lOT instruction is placed on
the OMNIBUS MD lines, the I/O PAUSE l signal is asserted by the CPU timing generator. If INTERNAL I/O l
is not asserted by an internal peripheral, I/O PAUSE l causes the interface lOP timing to assert the NOT lAST
TRANSFER l signal. Thus, CPU timing is suspended at TP3 time. Simultaneously, lOP timing is initiated and
the lOP signal that is subsequently generated enables the BIOP pulse generator to produce one or more pulses.
These pulses are used by the peripheral in conjunction with BMB bits to decode lOT instructions.
The lOT instruction can clear and set flags and registers within the peripheral, or it can direct a data word transfer
or a SK IP operation. Data words are transferred between the data gating logic and the CPU via the DAT AO-11
lines; between the peripheral and data gating, the data path depends on the direction of transfer, as shown in the
block diagram. The OMNIBUS C lines are asserted within the data gating logic in combinations that depend on
the type and direction of transfer.
If a SKIP operation is directed by the lOT instruction, the peripheral asserts the external SKIP l signal when conditions warrant. lOP timing clocks the skip counter and either the DATAl 0 or DATA 11 line, or both, is activated.

SECTION 3 DETAILED LOGIC

1.1

BIOP PULSE GENERATOR LOGIC

Figure 1-2 shows the BIOP pulse generator logic, which converts bits MD9-11 to BIOP pulses 4,2, and 1, respectively. A logic 1 on any MD line conditions a corresponding NAND gate for enabling at TP2 time. When the
NAND gate is enabled, it dc-sets a flip-flop that, in turn, conditions another NAND gate. Simultaneously, the

1-1

EXTERNAL BUS

BMBOO-11

BlOP 1, 2,4

SKI P L

AC CLEAR L

ACOO -11

BAC 00-11

-,-

f
DATA
GATING
LOGIC

DATA 10

SK I P
COUNTER

DATA

lOP
BUFFERS/
INVERTERS

MD9-it

MDO-11

BIOP
PULSE
GENERATOR

lOP
TIMING

STOP L

f
TP2

I/O
PAUSE L

NOT
LAST
TRANSFER L

TP3

BUS
STROBE
L

C2L

DATAO-11

CIL

COL

OMNIBUS
8E-O!?t

Figure 1-1

Positive I/O Bus Interface, Block Diagram

flip-flop causes the STOP L signal to be negated. If an I/O transfer involving an external bus peripheral is in
progress, the STOP L signal enables TP3 to initiate the lOP timing operation. The lOP timing logic (Paragraph
1.3) responds by asserting a signal (lOP) that enables the flip-flop conditioned NAND gate. The resulting signal
is buffered and designated B IOP4, B IOP2, or B IOP1.
For example, if MD bit 9 is a logic 1, flip-flop 104 is dc-set at TP2 time (note that the 10 flip-flops are cleared at
each TP1 time). The a-output of the flip-flop causes STOP L to be asserted and, providing the 101 and 102 flipflops are cleared (MD bits 10 and 11 are logic 0)' the 1-output conditions NAND gate E24 for enabl ing by the
lOP signal. When the lOP timing asserts the lOP signal, E24 is enabled and the BIOP4 pulse is generated. The
width of the pulse can be varied by adjusting a potentiometer in the lOP timing logic, thereby asserting the lOP
signal for the desired amount of time (Paragraph 1.3). When the lOP signal is negated, E24 is disabled. Because
the output of E24 is connected to the clock input of 104, the flip-flop is cleared when E24 is disabled (note that
the D inputs of the 10 flip-flops are connected to ground; thus, a positive transition at a clock input clears the
flip-flop). The a-output of 104 negates the STOP L signal; this action causes the lOP timing logic to terminate
the I/O dialogue.
This example stipulated that bits MD10 and MD11 were logic O. Suppose, instead, that all three MD bits are
logic 1. All three 10 flip-flops are then set at TP2. The STOP L signal is asserted and the 1-output of 101 conditions E11C for enabling by the lOP signal. Observe that the a-output of 101 disables both NAND gate E8B and

NAND gate E24. Thus, the lOP signal enables E11 C first and the B IOP1 pulse is generated. When the lOP signal
is negated, E11 C is disabled and 101 is cleared. This action removes the disabling signal from EBB; however, E24
remains disabled because the a-output of 102 is one of its inputs. NAND gate EBB is now conditioned for enabling by the lOP signal. When this signal is again asserted by the lOP timing logic, BIOP2 is generated. When
BIOP2 ends, 102 is cleared, removing the disabling signal from E24. Now the BIOP4 pulse is generated, as detailed earlier.

1-2

, -____________________________ IOP

MD9

, -________-j-___

(FROM

rop TIMING)

TO
BIOP4
BUFFER

MDlO

TO
BIOP2
BUFFER
STOP L
(TO lOP TIMING)
MDI1

TP2~_J

r--L.~

r--,

TO
BIOPI
BUFFER

101
E6

0r-~------------------~

TPI-------------/
NOTE:
FLIP-FLOPS are

DEC 7474 (See Volume I, Appendix A far dejails)

Figure 1-2

BE-OH2

B lOP Pulse Generator Logic

Thus, the BIOP Pulse Generator logic operates in such a way that the BIOP pulses are not assigned specific time
slots. If only one of the MD bits is a logic 1, then the corresponding B lOP pulse, whether 4, 2, or 1, is generated
at the first assertion of the lOP signal. If more than one MD bit is logic 1, the least-significant bit is selected
first and its corresponding B lOP pulse is generated; the most-significant bit is selected last.

1.2 BMB BUFFERS/INVERTERS
The preceding paragraphs discussed the BIOP pulse generator. A peripheral uses these BIOP pulses in conjunction
with BMB bits to decode lOT instructions. The BMB bits are derived from the OMNIBUS MD bits, which are
buffered and inverted by the interface. Figure 1-3 shows the buffer/inverter and network.
BMB bits 03-08 are used in peripheral device selection logic. Both the true and the false states of these bits are
derived from the corresponding MD bit; this minimizes the device selection network in the external peripheral.
Although programmed transfer peripherals use the BMB bits only for device selection, data break peripherals receive output (from the CPU) data via the BMBOO-11 lines. Thus, all 12 BMB bits are derived, as shown in
Figure 1-3.
1.3

lOP TIMING LOGIC

Figure 1-4 shows the lOP timing logic, which determines the duration of BIOP pulses and the separation between
individual pulses, if more than one is programmed. Separation and duration can be varied individually by potentiometers that are indicated on the logic diagram and on the KA8-E etch as lOP SEP and lOP WIDTH. These

'-3

BMBOO

BMBOl

BMB02

BMB03

BMB04

BMB05

BMB06

BMB07

BMBOS

,......A-..

r--A--.

,...-'---.

r
+5V

+3V

GATING FOR
BITS 1 AND 2
SAME AS FOR

: BIT 0

l
I
I

+5V

I
:

I
I
I

:
:
I
I
I
L

MOO

GATING FOR BITS
AS FOR BIT 3

4-8

II II
I I

SAME

I I

M02

TO BIOP

...----j---.-- } PULSE
+--+- GEN

I I
II I

r-4-~-+~--+_~

L---1-T-r

-.J

MOl

GATING FOR BITS
9-11 SAME AS FOR
BIT 0

I I
I I

L -_ _ _ _ _ _ _ _ _ _~~------~

BMBll

BMB10

~l~lLl l~ I-

BMB09

MD3

M04

MD5

M06

MD?

M08

MD9

MOlO

MOll
8E-0173

Figure 1-3 BMB Buffers/Inverters

BUS
STROBE L

PWR OK H
BV2

rop

STOP L

IIO PAUSE L - - - - - - - - ,

~--+ 3 V -<>-----'

TP3

8E-0174

Figure 1-4

lOP Timing Logic

1-5

potentiometers determine the triggered delay time of associated one-shot multivibrators, shown as part of
DEC 74123 ICs. Briefly, the one-shots contained within a 74123 can be triggered by:

a positive transition at pin 2, if, prior to the transition, pin 1 is low and the clear (C) input is high (for
the "B" half of the IC, substitute pin 10 and pin 9 for pin 2 and pin 1, respectively),

a negative transition at pin 1, if, prior to the transition, pin 2 is high and C is high,

a positive transition at the C input, if, prior to the transition, pin 1 is low and pin 2 is high.

Figure 1-5 shows the lOP timing for a typical I/O transfer. The lOP signal is asserted three times during the time
that I/O PAUSE is active; thus, three BIOP pulses are generated by the BIOP pulse generator (the identity of the
BIOP pulses does not affect the waveform relationship). The waveforms representing SEP and WIDTH are shown
for the minimum allowable triggered delay time, viz., 200 ns for SEP and 600 ns for WIDTH. The potentiometer
values allow these delay times to be increased to five times the minimum value. Refer to both figures while
studying the following description.
If the I/O transfer involves an external bus peripheral (INTERNAL I/O L remains negated) and the BIOP pulse
generator negates the STOP L signal, and NAND gate E28 asserts the NOT LAST TRANSFER L signal; this signal
indicates to the CPU timing generator the impending interruption of normal timing. At TP3 time, lOP timing is
initiated, while CPU timing is suspended in TS3.
lOP timing begins when the SEP one-shot is triggered by the positive transition at its C input (TP3 going away)
SEP (Oi is used to trigger the 100 one-shot, which, in turn, triggers WI DTH. WIDTH (0) sets the lOP flip-flop;
the resulting lOP signal enables the BIOP pulse generator to begin the BIOP pulse. The STB (Strobe) one-shot,
triggered by the end of WIDTH (0), clears the lOP flip-flop; thus, the duration of the BIOP pulse is 100 ns longer
than the duration of WI DTH (0). A BUS STROBE L signal is generated by STB (1) at the end of each B lOP pulse
to execute the instruction represented by the BIOP pulse (BUS STROBE L causes the AC LOAD L signal to be
asserted in the CPU; see Volume 1, Chapter 3, Section 6 for details). When the first BIOP pulse has ended, the
sequence outlined begins again, this time with STB (0) triggering the SEP one-shot. When the last BIOP pulse
ends, the STOP L signal is asserted by the BIOP pulse generator. This signal ensures that the WIDTH one-shot is
not triggered by the next transition of 100 (0). Therefore, the lOP flip-flop remains clear through the remainder
of the lOP timing. When REST (0) (the Restart one-shot), which is triggered by the STOP L signa! transition,
goes positive after 320 ns, STB is triggered again, producing a final BUS STROBE L signal. This BUS STROBE
terminates I/O dialogue and reinstates CPU timing.
The 100 one-shot is necessary for proper triggering of WIDTH. It provides a negative transition at pin 9 of WIDTH
when SEP times out. If the negative transition were supplied by the a-output of SEP, WIDTH would trigger at the
same time as SEP. On the other hand, if the negative transition were supplied by the 1-output of SEP, WIDTH
would trigger at TP2 time, when the STOP L signal is negated. Consequently, the 100 one-shot is quite important
to the timing operation.
The 225 one-shot is also important to the timing logic. Note on Figure 1-5 that the STOP L signal is shown to
have a spike that is coincident with the trailing edge of the first BUS STROB E signa! (if three B lOP pulses were
generated, there would be two spikes shown). This spike is a representation of the tendency of the STOP L signal
to go low at the end of the lOP signal (NAND gate E8A in the BIOP pulse generator becomes momentarily indecisive at this point in the timing). The 225 one-shot brackets this spike in time and, thus, prevents the REST oneshot from triggering prematurely.

1-6

TP1 ~____________________________________________________________________________

IOP 1 F/F

~_-,--~I

F/F~
___L..----'I

lOP 2

IF~
___L..----'I

IO P 4 F

TP2

------~
TP3

~--------------------------------------------------------------------

n
=u=

-------~

SEP 0.5.
(4)

~------------------------------------------------------------

200ns

100us 0.5.
(E3)

0.5.

lOP F/F

WIDTH
(4)

225 ns 0.5.
(E2)

STB 0.5.
(E3)

U
U
Fl'-________-'n
U
u
U
U
=u=
U

600ns

lOOns

~
~

REST 0.5.
(E2)

BUS STROBE

NOT LAST--'
XFER

IL._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

1/0 PAUSE

LI
U-

~L_____________________________________________________J
NOTE:
IOT 6XX7 SHOWN TO GENERATE ALL 3 IOP'S NO GATE DELAYS SHOWN
8E-0175

Figure 1-5 Waveforms, lOP Timing Logic

1-7

1.4 DATA GATING LOGIC
The data gating logic is shown in Figure 1-6. During a programmed I/O transfer, data is transferred to or from the
CPU on the OMNIBUS DATAO-11 lines. Output data (from the CPU) is gated from the DATA lines through an
interface buffer/inverter network (illustrated in Figure 1-6 for bits 0 and 11) to the external bus BACOO-11
lines. If the output transfer is to be accompanied by a clearing of the CPU AC Register, the peripheral is directed
(by the B lOP pulse) to assert the OMNIBUS CO L signal. The peripheral does this indirectly by grounding the
external bus AC CLEAR line. The AC CLEAR L signal causes NAND gate E25D on the interface to assert the
CO L signal. If the AC Register does not have to be cleared, the C-lines remain negated high throughout the transfer.
On the other hand, an input transfer must always be accompanied by the assertion of at least one C-line. Note
that when a data word is transferred from the peripheral on the external bus ACOO--l1 lines, the interface DATA
IN L signal is asserted by NOR gate E29. If the data is placed on the AC lines during the BIOP pulse (as it must
be), NAND gate E25C asserts the C1 L signal. Simultaneously, the AC INPUTS ~ DATA BUS signal gates the
data onto the OMNIBUS DATAO-l1 lines. The result of these actions is an OR operation of the AC contents
and the data on the DATAO-11 lines. The peripheral can cause a jam input by grounding the AC CLEA R line,
thereby asserting the CO L signal. Thus, only the information on the OAT AO-11 lines is placed in the AC Register. Note that if data word DODOs is transferred from the peripheral, the DATA IN L signal is not asserted. To
transfer DODOs, the peripheral must ground the AC CLEA R line and, in effect, cause a jam input of zeros.
These are the four types of data transfers that can be made by the PDP-B/I type peripherals. Another form of
I/O transfer, other than a 12-bit data word, utilizes the interface skip logic to update the CPU PC Register. This
type of transfer is discussed in Paragraph 1.5.
1.5 SKIP COUNTER LOGIC
The peripheral, when directed by an lOT instruction, can cause a skip of 1,2, or 3 program instructions. It initiates a SKIP operation by grounding the external bus SKIP line. The interface skip logic, shown in Figure 1-7,
asserts the OMN IBUS DATA 10 and/or DATA 11 Iines, depending on the number of instruction skips required
(during a SK IP operation the peripheral does not place data on the ACOO-l1 lines). At the same time, the
OMNIBUS C lines are manipulated to provide a path for the DATA bits through the CPU major register gating
to the PC Register. The DATA bits are added to the contents of the PC Register, increasing the program count
in the register by 1, 2, or 3.
The timing diagram of a typical SKIP operation is shown in Figure 1-8. Refer to this diagram and to Figure 1-7
while studying the description that follows. The timing diagram shows that two B lOP pulses, 1 and 2, are generated during the lOT instruction. The imaginary peripheral that applies to this example decodes these two BIOP
pulses and responds by grounding the SKIP line. Keep in mind that this is an example, only, and that this imaginary peripheral does not necessarily exist. The combination of BIOP1 and BIOP2 can produce a variety of operations, depending on how a peripheral decodes the pulses.
Nevertheless, when TP3 starts lOP timing, this peripheral is directed to initiate a SKIP operation by asserting
SKIP L. The SKIP line controls the D-input of flip-flop E9, which is clocked when the STB one-shot is triggered.
Because STB is triggered at the end of each BIOP pulse, E9 can be clocked twice during tOP timing. !'Jete that
the 100 one-shot dc-sets E9. Thus, E9 is set at the fi rst triggeri ng of the 100 one-shot, or (as shown in Figure 1-8)
during a previous lOP timing cycle. Thereafter, 100 and STB are triggered alternately. Thus, E9 is alternately
cleared and set, as long as SK IP L is asserted. Each time E9 is cleared, SK IP 1, the first stage of the 2-5tage binary
counter, is clocked. In thi9-example, the binary counter is clocked twice, indicating that two instructions are to

1-8

*BACOO

*BAC!!

INT
COL

lOP
NOTE

RQST L

*AC

*INT

CLEAR
L

RQST L

* Denotes External Bus Signal
,8E- 0176

Figure1-6

Data Gating Logic

1-9

DATAll

DATA10

C2L

L -_ _ _ _ _ _ _-+-_*-_--<~_.---- T. P.

DB 1

T. P.
CAl

INITIAL! ZE

TP3

INTERNAL
I/O L

STOP L

I/O PAUSE L

SKIP L

r
I
I
I

1
E3A
100

E3B
STB

E2A
REST

I
I

I....:!e ~igUr~3 ~de~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _ _ _ _ _ -.J

8E - 0177

Figure 1-7 Skip Logic

TP3 f-

II
, I

BIOPI

I
I

I
!

;

BIOP2
I
I

SKI P

I
,:

STB (I)

II!
:1I

I
,
,

i I

, : !

i
I

w..i!
l-

E9 (0) I

(I)

SKIP 2 (I)

i
!

: I

Ii.

I
[

Ii'

L
t

,I
:

I
i

,
,

I I

;

CEN (0) I

;

DATA10

L :i

1-- .... --

(0) i

DATAl I

, :!

i
~H

'1-'-i--+.........

!, H-

,
REST

i j

I
i

: :
SKI P I

,........i+-+-.-1--11-4

100 (0) Ii

II'

",'hL';1

i
i

I
I

i
I

'1 1

, i I
,

I
I ! [

I
[

I
I

I
I
!

: I I

i II I ,1 I

1
IL
I I

I
I

,
i

I : ,

i
i

;

I
8E-0178

Figure 1-8 Timing, Skip Logic Application

to be skipped. SKIP 2 is set at the second triggering of STB. The C-line enable (CEN) flip-flop is dc-set by the
REST one-shot, enabling NAND gates E25 and E28B (note that CEN is clocked by STB at the same time that
it is dc-set by REST; the dc-input takes precedence in such a case). The assertion of C2 L, while C1 L and CO L
remain negated, provides a path for DATA10 through major register gating to the PC Register. C2 L and BUS
STROBE (generated when REST times out) assert PC LOAD Land DATA10 is added to the contents of the PC
Register, updating it by two. Note that the SKIP line must be negated before STB is triggered by the trailing edge
of REST (0). If not, the binary counter is erroneously clocked one more time.

1-11

SECTION 4 MAINTENANCE
There are no specific maintenance procedures for the KA8-E itself. Each DEC peripheral that connects to the
KA8-E has an associated MAl NDEC or exerciser program that enables the technician to maintain both the option
and the KA8-E interface. Because all of these peripherals use the one interface, a fault in the interface can be
isolated by running a number of MAINDEC programs. If ail programs result in errors, one can reasonably conclude that the KA8-E is at fault.
General information concerning corrective maintenance is included in Volume 1, Chapter 4. The technician will
find this material helpful. The interface schematic, E-CS-M8350, indicates important test points, IC locations,
and pin numbers and should be used whenever maintenance is being performed.
The KA8-E connects directly to a single peripheral via three cables that are supplied with the interface (refer to
the PDP-8IE & PDP-81M Small Computer Handbook, Chapter 10, for cabling rules and suggestions). Each cable
connects to the interface with a 40-pin Berg connector and to the peripheral with a DEC M953A cable connector.
From-To information for the cable is given in Table 1-1 (the cables are identical). (Refer to the PDP-8IE & PDP-81M

Small Computer Handbook for details concerning cable connections.)
Table 1-1
KAS-E Cable Information
From

From

(M953A Cable Conn.)

(Berg Conn.)

(M953A Cable Conn.)

(Berg Conn.)

Gnd
Gnd
Gnd
B1
Gnd
D2
Gnd
D1
Gnd
E2
Gnd
El
Gnd
H2
Gnd
H1
Gnd
K2
Gnd
J1

A
B
C
D
E
F
H
J
K
L
M
N
P
R
S
T
U
V
W

Gnd
M2
Gnd

L1
Gnd
P2
Gnd
M1
Gnd
S2
Gnd
P1
Gnd
T2
Gnd
S1
Gnd
V2
Gnd
Gnd

Z
AA
BB
CC
DD
EE

FF
HH
JJ
KK
LL
MM
NN
PP
RR
SS
TT
UU
VV

Pins A2, 82, U1, and V1 on M953A not used.
Pins A 1, C1, F1, K 1, N1, R1, T1, C2, F2, J2, L2. N2. R2, and LJ2 on M953A are ground pins.

'-12

SECTION 5 SPARE PARTS
Table 1-2 lists recommended spare parts for the KA8-E. These spare parts can be obtained from any local DEC
office or from DEC, Maynard, Massachusetts.
Table 1-2
KAS-E Recommended Spare Parts
DEC Part No.

Description

15-03100

Transistor, DEC 3009B

19-09705
19-10010
19-09971
19-09921
19-09928
19-09686
19-09373
19-09486
19-09004
19-05578
19-05577
19-05576
19-05575
19-05547

IC DEC 8881
IC DEC 2501
IC DEC 6380
IC DEC 7417
IC DEC 7416
IC DEC 7404
IC DEC 9601 (M835 only)
IC DEC 384
IC DEC 7402
IC DEC 7430
IC DEC 7420
IC DEC 7410
IC DEC 7400
IC DEC 7474

11-00114
11-00113

Diode D664
Diode D662

BC08J-l0

Cable, 10ft.
IC DEC 74123 (M8350 only)

1-13

Quantity

4
2

CHAPTER 2
KD8-E DATA BREAK INTERFACE

SECTION 1

INTRODUCTION

The KD8-E Data Break Interface is used by peripherals to transfer large blocks of data between the peripheral
and memory. This interface cannot provide all the necessary signals for such a data transfer. Consequently, the
positive I/O bus interface must also be used in the system. The concept of data transfers and the interrelationship
of the data break interface, the positive I/O bus interface, and the OMNIBUS are explained in Chapters 6 and 10
of the PDP-8IE & PDP-81M Small Computer Handbook, DEC 1972. A detailed discussion of CPU operation during a data break transfer is presented in Volume 1, Chapter 3, Section 6. The reader should be thoroughly familiar with this referenced information to benefit from the detailed logic discussion presented in Section 3.

SECTION 2

BLOCK DIAGRAM

Figure 2-1 is a functional block diagram of the KD8-E Data Break Interface. OMNI BUS signals are indicated by
asterisks (on the block diagram only). When an interface receives a B RK RQST L signal from its peripheral, the
request accept logic uses the next INT ST ROB E to assert signals that indicate acceptance of the request. These
signals are used by the CPU and the peripheral in preliminary operations and by the interface priority network.
The priority network compares the priority ranking of a peripheral with that of all other peripherals that make a
break request at the same time. The interface of the highest ranking peripheral generates a PR 10 R ITY signal that
allows its CP Control logic to assert CP control lines. This action enables the peripheral to assume control of the
CP Major Register gating and to directly address, via the BKMA Register logic, memory locations associated with
the data transfer. The direction of transfer and the type of transfer are controlled by the interface data transfer
logic. When the cycle select logic indicates that the true BREAK (BK) cycle is in progress, the data word is transferred to, or from, the address indicated by the BKMA Register logic. If the data transfer is from the peripheral,
the data word is placed on the DATA 0-11 lines of the OMNIBUS by the data transfer logic.

SECTION 3 DETAILED LOGIC
2.1 CP REGISTER CONTROL LOGIC
Figure 2-2 shows the CP Register control logic. The NRB flip-flop determines if the interface can assert the CP
Register control Iines in response to a break request from the peripheral. This determination is based on the state
of the NEW B RK OK L signal, which is asserted within the interface when conditions allow a data transfer (the
NEW BRK OK L signal is discussed fully in Paragraph 2.2). If NEW BRK OK L has been asserted by the interface and the BRK RQST L signal has been asserted by the peripheral, the NBR flip-flop is set by the INT STROBE

2-1

*BRK
*MD DATA
DATA 0-11 DIR L CONT L

*MA 0-11

BKMA REGISTER LOGIC
(ADDRESS SELECTION)

*MD 0-11

1--_ _ _ _

DATA 00-11

' - - - - - - - DATA ADDRESS 0-11
*MS,IR
DISABLE L

PRIORITY

*BRK IN *CPMA
PROG L DISABLE L

...

INT
STROBE

BRK
RQST L

ADDRESS
ACCEPTED L

*INDICATES OMNIBUS SIGNAL
BE-Ol79

Figure 2-1

Data Break Interface, Block Diagram

signal (Figure 2-2). The a-output of NBR then sets the ACTIVE flip-flop, which asserts the BRK IN PROG L
and CPMA DISABLE L signals. The CPMA DISABLE L signal conditions a flip-flop on the Major Register Control module (Volume 1, Figure 3-102) so that TP4 can clear the flip:flop; the resulting signal, MAC L, removes the
CPMA Register outputs from the MA lines. The BRK IN PROG L signal, which can be displayed on the programmer's console, ensures that only data break devices place priority information on the DATA lines during TS4.
When TS4 is entered, the 1-output of the ACTIVE flip-flop asserts the priority signal for this (our) interface. If
other peripherals have made break requests at INT STROBE time, each peripheral's interface asserts a priority
signal at TS4. The priority network (Paragraph 2.3) in each active interface examines these signals to determine
if it has the highest priority of all the devices currently attempting to use the data break system. If our peripheral
is not of sufficiently high priority, it must wait until the next TS4 signal; at that time the priority signals are
again compared. If our peripheral has highest priority, the D-inputs of the MAC1 and MAC2 flip-flops are taken
to a positive voltage; the flip-flops are then set at TP4. The 1-output of MAC1 not only asserts the MS, I R
DISAB LE L signal, which places the CP in the DMA state, but also conditions the MALC flip-flop so that it can
be set when the TP1 pulse occurs. The 1-output of MALC then asserts the MALC L signal, which ensures that
the CPMS Register and the CPMA Register will resume normal operation in the corr,~ct major state and at the correct memory address, respectively.

2-2

MALC L
TO BKMA LOGIC
NTALlZE----\

MS,IR
DISABLE L

' - - - - - - - - - - - - - - - ~~Po~ITY

TS4 L

TO
PRIORITY
BRKIN
PROG L

ADD ACCEPTED L
CPMA
DISABLE L

TP2

BE-OIBO

Figure 2-2 CP Register Control Logic

2-3

Note that ADD ACCEPTED L is asserted during TS1 of the first cycle following INT STROBE, regardless of the
outcome of the priority check. This signal clears the break request flip-flop in the peripheral, allowing the pei'iph-eral to make another request when it is ready. At TP1, the NB R flip-flop is cleared, also regardless of what Occurs
in the priority network. Thus, this flip-flop is active for only the short time necessary to indicate acceptance of
the break request. In contrast, the ACTIVE flip-flop is cleared only at TP2 of a true break cycle (defined and explained in Paragraph 2.2), which can be delayed for some time by priority considerations. Both NBR and
ACTIVE are used extensively as control signals in other functional sections of the interface.
2.2 CYCLE SELECT LOGIC
After our interface takes control of the CP, a data transfer can be made. The CP is in the DMA state and remains
in this state as long as MS, IR DISABLE L remains low. Each timing cycle (a "slow" cycle of 1.4 IlS) that occurs
during the DMA state is used by the interface/peripheral to accomplish tasks necessary for the data transfer. The
actual data word transfer takes place during the Break (BK) cycle of operation. For 1-cycle peripherals only the
BK cycle is necessary; however, 3-cycle devices require a Word Count (WC) cycle and a Current Address (CA)
cycle before the BK cycle. This section describes the method of selecting each of the three cycles of operation;
the details of what occurs during each cycle are presented in succeeding sections, except that certain BK cycle
operations are detailed here.
Figure 2-3 shows the cycle select logic. When one of the three flip-flops shown (WC, CA, and BK) is set at TP4,
the respective operation cycle is entered. If the peripheral is a 3-cycle device, the 3 CYCLE line is wired to ground
within the peripheral. Thus, pin 2 of the DEC 8271 IC is positive voltage (high). This high is gated to the D-input
of the WC flip-flop, providing the 8271 load (L) input is also high and the shift (S) input is low (see Volume 1,
Appendix A, for details about the 8271 IC). This provision is met each time the interface accepts a break request
from the peripheral (the 1-output of NB R goes high at INT STROBE time). The WC fl-ip-flop is set at TP4 - the
same TP4 at which MAC1 and MAC2 are set (because the D-input of both the CA and BK flip-flops is low, TP4
clears these flip-flops). Note that TP4 is NANDed with the output of a NOR gate (E18) that can be enabled by
the O-output of the ACTIVE flip-flop. This means that the WC flip-flop can be set even though access to the CP
has been claimed by another peripheral during T84 (the ACTIVE flip-flop is set prior to the priority check and
remains set until TP2 of the BK cycle). If this happens, the operations that normally occur during the WC cycle
are suspended for at least one cycle. One of these normal operations is the clocking of the 8271 flip-flops at TP4.
To suspend this clocking process, the 8271 is placed in the "hold" mode by the NBR and MALC flip-flops
(Table 2-1). The NBR flip-flop is cleared at TP1 of the suspended cycle, while the MALC flip-flop remains in
the clear state (MALC is set at TP1 of a normal cycle). The "hold" condition remains in effect until our peripheral has priority; at this time a normal WC cycle is entered.
At TP1 of the normal WC cycle NBR is cleared and MALC is set (NBR remains clear until a new break request is
accepted). As Table 2-1 shows, the 8271 IC is placed in the right-shift mode. In this mode, the three flip-flops
comprise a shift register that is right-shifted by clock pulses. Thus, TP4 of the WC cycle causes the high at the
1-output of WC to be shifted into the CA flip-flop (CA is set, while WC is cleared). The CA flip-flop, also, can be
set regardless of the results of the TS4 priority check (as before, the O-output of ACTIVE -enables TP4 to clock
the flip-flop). The normal CA-cycle operations are then suspended for at least one timing cycle. At TP1 of the
suspended cycle, MALC is cleared; the 8271 is placed in the "hold" mode, preventing TP4 of the suspended CA
cycle from clocking the flip-flops. When our peripheral has priority, the normal CA cycle is entered, MALC is
set at TP1 time, and the 8271 IC is again placed in the right-shift mode. The CA cycle operations are carried out
and, at TP4, the BK flip-flop is set, while the CA flip-flop is cleared.

2-4

BRK CYCLE L

.:>O---B BREAK L
MAC' (O)---<lI
NEW BRK OK L

roE-;;-S;; ,-

-.,

- - - - - - ----

I
I
I

I
I
I
I

I
I

I
IL ___ 2

s I

SHIFT/LOAD GATING

------------

_...J

3 CYCLE L

TP4

NBR(l)

MALC(O)

ACTIVE(O)

8E-0181

Figure-2-3 Cycle Select Logic

Table 2-1
8271 IC Control Signals
NBR F/F

MALC F/F

8271 IC Control State

Clear

Low

Hold

Set

Low

High

Parallel Load

Clear

Set

High

Low

Right Shift

The BK flip-flop, too, is set regardless of priority. If another peripheral has priority, the normal BK cycle operations are suspended and the 8271 I C is placed on the "hold" condition for at least one cycle. When our peripheral has priority, the normal BK cycle is entered at TP4. The O-output of BK is NANDed with the O-output of
MAC1 to assert NEW BRK OK L, BRK CYCLE L, and B BREAK L (Figure 2-3). Because MAC1 is cleared at
TP4 if another peripheral has priority, these signals are asserted only during a normal break cycle. NEW B RK OK
L tells the NB R flip-flop that data is about to be transferred and that a break request can be accepted at the next
INT STROBE time; BRK CYCLE L is applied to the programmer's console display to indicate the normal or
"true break" cycle; B BREAK L clocks the data into or out of the peripheral's buffer register, depending upon
the direction of transfer. At TP2 of the true BK cycle the ACTI VE flip-flop is cleared, negating the CP Register

2-5

contrallines. If the peripheral has not asserted the BRK RQST L signal before INT STROBE time of this cycle,
NB R and ACTIVE remain clear and the CP Register control lines remain negated. MAC1, MAC2, and BK are
cleared at TP4, while MALC is cleared at TP1 of the next timing cycle (because ACTiVE is clear when this TP4
occurs, the O-output of MALC is used to enable TP4 to clock the BK flip-flop). If a break request was made before I NT STROB E time, the WC flip-flop is set at the same time that the BK flip-flop is cleared; the break operation is repeated as many times as necessary.
Figure 2-4 is a timing diagram relating the signals discussed in this section and in the preceding section, CP Register Control Logic (the time scale does not reflect true processor timing; refer to Volume 1, Chapter 3, for timing
information) .

TPl
TP2

, I

h
1I h
h I

I I

TP4
INT STROBE

f-'.

BRK RQST L

TP3

h 1111 II hi

I
I

ACTIVE (1)

I
I

~J
I

.. CPMA DISABLE L
.. 8RK IN PROG L

MACl (1)
MAC2 (1)

I
I

.. MS,IR DISABLE L

I
"MALe (1)

MALe L

Ii! I!I

8271 "l"

.
I

i
I

I
I I

8271"S"

I ~f:L,_

~JltU
i

3- CYCLE L

we (ll

CA (ll
BK (1)

If-

i I

t-~ I
I

l--I-

I ,
I

LIII

I '

~f- f-f-

t4.

1
hf-

III,. :U

ADD ACCEPTED l

PRIORITY NO-GO
GO

' I hi

I
,

NBOK L
NBR (1)

h
I

, I

h'
h

III

i I

I hi
I
h

h
h

I Ih ,

I I

I
f-f-'
1-1-

B 8REAK L
.. BRK CYCLE L

.. AS CONTROLLED BY
"OUR" PERIPHERAL
NOTE:

3 - Cycle device der showing 1 word der with a priority break during CA cycle; we cycle is shown for sl!!cond word xfer.
8E-0182

Figure 2-4 Timing, Register Control and Cycle Select Logic

2-6

2.3 PRIORITY LOGIC
Figure 2-5 shows the priority logic. Each peripheral interface contains a nearly identical circuit; differences
exist only in the placement of jumper wires, which are designated AO-All and BO-Bl1 in Figure 2-5. The
priority of a peripheral is established on the interface by removing a particular A jumper (all A jumpers are wired
in place during production of the interface) and installing the corresponding B jumper. For example, to establish
a "0" priority for our peripheral, remove AO and install jumper BO. Note that this action disables all 12 NAND
gates (ICs E17, E34, and E49). Thus, the output from NOR gate E18 is low. When the interface accepts a break
request from the peripheral, the ACTIVE flip-flop is set at INT STROBE time. The O-output of ACTIVE enables
NAND gate E 10 to assert the PRIOR ITY signal; therefore, our interface/peripheral begins the data break operation. Because our peripheral has only to request a break for that request to be granted, our peripheral has been
assigned highest priority. No other interface can have its AO jumper removed, or its BO jumper connected.

PRIORITY

ACTIVE (0)

A4 Tt5
Ff-- -

+5V

TS4 L

Figure 2-5 Priority Logic

2-7

As many as 11 other peripherals can have a break request accepted by their respective interfaces at I NT STROBE
time. No matter what priority has been established for these peripherals, each of the 11 interfaces has an AO
jumper in place. Note that when our interface ACTIVE flip-flop is set, NAND gate E37 brings the DATA 0 line
low (our BO jumper is in place) during TS4. Because all interfaces monitor the DATA lines, NAND gate E17D
of each other interface is enabled. Thus, these interfaces cannot assert their PRIORITY signals as long as our
peripheral requests data breaks.
As another example, consider what happens if our peripheral ranks only third highest in the peripheral priority
structure. This priority is established on our interface by removing jumper A2 and connecting jumper B2. Because jumpers AO and A 1 are left in place, two other interfaces can keep our peripheral from beginning a data
break operation. If the second highest priority peripheral has a break request accepted at the same time our
peripheral's request is accepted, its interface brings the DATA 1 line low during TS4 time. NAND gate E17C on
our interface is enabled and the PRIORITY signal remains negated. Until this other peripheral has completed the
data break operation, our peripheral remains inactive. As has been implied, priority decreases from left to right,
i.e., the lower the priority of the peripheral, the higher the number of the A jumper removed and B jumper installed. Thus, to establ ish priority on the lowest ranking peripheral's interface, remove jumper A 11 and install
jumper B11.
2.4 BKMA REGISTER lOGIC
Figure 2-6 shows the BKMA Register logic.

This logic enables the peripheral to reference memory locations

associated with the data break transfer. A peripheral that has maae a break request must provide its interface
with a memory address via the DATA ADDRESS 0-11 lines (Figure 2-6). This address is gated through DEC
8266 (refer to Volume 1, Appendix A, for details of this IC) to the parallel-load inputs of the 8271 I Cs (the
gating for bits a through lOis identical; thus, the description and the illustration detail events for only bit a and
bit 11). When the interface accepts the peripheral's request at I NT ST ROB E time, the O-output of the NB R flipflop enables NO R gate E15, placing the 8271 ICs in the "load" condition (Table 2-'). At the same time, one
input of NAND gate E14 is sent high by the O-output of the ACTIVE flip-flop. At TP4, E14 is enabled and the
BKMA Register flip-flops are loaded with the address on the DATA ADDRESS lines. If the peripheral has priority, the MAC2 flip-flop is set, also at TP4; the l-output of the fl ip-flop enables NAND gate E 1, placing DATA
ADDRESS bit 0 on the MAO line. If the peripheral does not have priority, the address is retained in the BKMA
Register but not gated onto the MA lines until MAC2 is set at a later TP4 time. The NB R flip-flop is cleared at
TP1, regardless of the outcome of the priority check, and NO R gate E 15 places the 8271 ICs in "hold".
If the peripheral is a l-cycle device, the address placed on the MA lines at TP4 is that of the memory location to

or from which the data word is to be transferred. Note that NAND gate E26 is enabled in this situation (the BK
flip-flop of the cycle select logic is set, the WC flip-flop is clear). Thus, the full 12- or 15-bit address supplied by
the peripheral is placed on the MA lines. However, if the peripheral is a 3-cycle device, the WC cycle is entered
first after a break request is accepted. NAND gate E26, disabled during the WC cycle, in turn disables NAND
gate E40. Thus, DATA ADDRESS bit 11 is not gated onto the MAll line; rather, MAll is high, logic 0, during
the cycle. The address placed on the MA lines during the WC cycle is that of the memory location containing the
peripheral's WC Register; this address is hard-wired in the peripheral and is even (bit 11 is logic 0) so that the CA
Register can be easily referenced during the next timing cycle, as is explained in the following paragraph.
During the WC cycle, the count in the WC Register is transferred from memory to the CP, incremented, and returned to the register. At TP4, the WC flip-flop is cleared and the CA flip-flop is set. If the peripheral still has
priority, NAND gate E37 is enabled, pulling theMA11 line low. The MAO-10 lines carry the same address as
during the WC cycle. Thus, the peripheral's hard-wired address is incremented and the new address is that of
the memory location containing the peripheral's CA Register.

2-8

MAO - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

MAll

SIMILAR TO O-BIT
-- -- 1-10
- - - - - - -- ------------------ ---

r--

BKMA REGISTER
(E2.E22.E41)
DEC 8271ICS

I
MAC2(1)

CAO)

1-10 SIMILAR TO 0

I
I

WC(1)

I
I
L __ _

PARALLEL LOAD
S

NBR (0)

r-I

I
I
ACTIVE (0)
I

--------,
P/O E7
DEC 8266

I I
I I

I
I
I

I
I
I
L

r------I

P/O E44
DEC 8266

---,
I

I
I

I I
I I

I I
I I
I I

I
I

I I
I I
_______ ..-1 L _______

CA(li

I
I
I
...J

MACH1)

MDO---- - - - - - - - - - - - - - - - - - - - - ------MD11
DATA
__________________________________
DATA
ADDRESS 0
ADDRESS 11
8E-0184

Figure 2-6

BKMA Register Logic

2-9

MACl (0)

At the same time (TP4) that the CA Register address is placed on the MA lines, the CA flip-flop enables NAND
gate E18. This gate, in turn, enables NOR gate E 15, which places the BKMA Register in the "load" condition.
Also, NAND gate E18 removes the DATA ADDRESS lines from the parallel-load inputs of the BKMA Register,
substituting the MDO-11 lines. Note that these actions do not take place prior to the negative transition at the
BKMA Register flip-flop clock inputs. Thus, the BKMA Register retains the WC Register address until TP4 of
the CA cycle.
During the CA cycle, the address in the CA Register is transferred from memory to the CP, incremented, and returned to the register. The address, after incrementation (the current address), is that of the location to or from
which the data is to be transferred. Thus, this current address must be placed in the BKMA Register, and transreffed from there to the MA lines at the beginning of the BK cycle. The current address is sent via the MD lines
to the CP where it is incremented. At TP2, the result is returned to the MD lines and remains on these lines for the
latter portion of the CA cycle. Therefore, at TP4 of the CA cycle, the BKMA Register parallel-load inputs reflect
the current address. Because the BKMA Register is in the "load" condition, the current address is loaded into the
register. At approximately the same time, the BK flip-flop is set, while the CA flip-flop is cleared. Because E37
is disabled and E26 is enabled, the contents of BKMAO-11 are placed on the MAO-l1 lines.
Also at TP4, NAND gate E 18 is disabled. This action removes the MD lines from the parallel-load inputs, selects
the DATA ADDRESS lines, and places the BKMA Register in "hold". Note that the MALC flip-flop keeps NOR
gate E18 enabled throughout the BK cycle (ACTIVE is cleared at TP2), if the peripheral has priority. These two
gates ensure that the BKMA Register is ready to begin a new transfer, if the interface accepts a break request at
INT STROBE time of the BK cycle.
During the BK cycle, the data word is transferred to or from the location specified by the current address. The
logic that accomplishes this transfer through the interface is covered in the following section, which also details
the special operations of all three cycles.
2.5 DATA TRANSFER LOGIC
The data transfer logic (Figure 2-7) controls the direction and type of data transfer. Table 2-2 shows the relationship between the type and direction of transfer and the signal levels of the various control lines. The table
should be used with Figure 2-7 for a good understanding of the logic details.
If the transfer is to be from the memory to the peripheral, a 12-bit data word is transferred from the addressed location via the positive I/O bus interface. The Data Break Interface asserts the MD DI R L signal so that the data
word is rewritten in the memory location during the write half of the timing cycle. NAND gate E8B (Figure 2-7)
is used to ground the MD DIR line. The BK (1) and MAC1 (1) signals ensure that the true break cycle is in progress. The third input to E8B is high because NAND gate El0A is enabled. El0A is controlled by the DI (Data
In) and INC (INCrement) flip-flops, which are set and cleared respectively at TPl time of an output (from memory) transfer.
Note that the peripheral need not assert any control lines for an output transfer. However, if an input (to memory) transfer is to be carried out, the peripheral usually grounds the DATA IN line (exceptions are noted in the
discussion). The DI flip-flop is set at TP1 of the first cycle of the data break. if the peripheral is a 3-cycle device,
this first cycle is a \"/C cycle. Since the BK flip-flop is clear, NAND gate E 13 is disabled (note that the Di fiip-fiop

is significant in the operation of E 13 only during the B K cycle; thus, the decision to set or clear this flip-flop, by
asserting or negating the DATA IN L ~ignal, nned not be made during either the WC or CA cycles). One input of
NAND gate E8A is high. If this is a normal WC cycle (this interface's peripheral has priority), E8A is enabled during TS2 by NAND gate ElOB, pulling the DATA 11 line low. This signal bit of data is transferred to the CP and
added to the word count, which is brought to the CP from the WC Register, providing the BRK DATA CaNT L

2-10

signal is asserted by the interface. NAND gate E23 is used to assert this signal. Because this is a WC cycle, NAND
gate E15 is disabled, enabling E23 (MAC1 is set because the peripheral has priority). Therefore, the word count
is incremented. Because the MD D I R L signal is negated (both E8C and E8B are disabled during the WC cycle),
this new word count is placed in the WC during the write half of the memory cycle.

* DATA 0

.. DATA 11

DATA 00

DATA 11
.. MD DIR L

.. BRK DATA CONT L

BK(l)
MAC1 (1) ->+-f------4H-f----'
CA (1)

... TS2L

MAC1(0)

DATA IN L

-= TPl
.. OMNIBUS SIGNALS

Figure 2-7

Data Transfer Logic

8E-018S

During the CA cycle of the 3-cycle transfer, the current address is incremented in much the same way as the word
count. Again, DATA 11 is pulled low by E8A during TS2 if the peripheral has priority. E23 asserts the BRK
DATA CONT L signal, which enables DATA 11 and the current address to be added in the CPo If the MD DIR L
signal is negated, the new address is sent to the CA Register during the write half of the cycle. Note that the MD
DI R L signal is negated only if the NCAI (No Current Address Increment) flip-flop is clear. This flip-flop is

2-11

clocked at TP1 of a timing cycle and is normally clear. However, the peripheral can ground the CA INC INH line,
causing the NCAI flip-flop to be set at TP1. NAND gate E8C then asserts the MD DI R L signal during the CA
cycle. Thus, although the current address is incremented as usual, the original address (the one that was in the
CA Register at the beginning of the cycle) is returned to the CA Register during the memory write.

Table 2-2
Control Signals, Cycle, Type, and Direction of Transfer
Cycle

Direction
of Transfer

Out

Type

Word

Current

No Current

12-Bit

of Transfer

Count

Address

Increment

ADM

Data Word

Increment

High
Low
Low
High
High

Low
Low
Low
High
Low

High
Low
High
Low
High

High
Low
Low
Low
High

High
High
Low
High
High

Low
High
High
High
High

MD DIR L
BRK DATA CaNT L
DATA IN L
MB INC L
CA INC INH L

During the BK cycle of operation, whether of a 1- or 3-cycle operation, an input or output transfer can take place.
As described at the beginning of this section, there is only one type of output data transfer, i.e., the transfer of a
12-bit data word from the addressed location. However, there are three types of input transfers that can be carried out. One of these is similar to the transfer that takes place during the WC and CA cycles, and is designated
MB Increment. To accomplish this transfer, the peripheral grounds DATA IN and the MB INC lines. At TP1
the I NC flip-flop is set, while the DI flip-flop is set. NAND gates E 10A and E 15 are disabled by the INC flipflop. Thus, E23 asserts the B R K DATA CaNT L signal and, because E8C is disabled during the B K cycle, E8B
negates the MD D I R L signal. During TS2 the DATA 11 line is pulled low by E8A. This single bit is transferred
to the CP, where it is added to the data word that is brought from the addressed memory location. The incremented data is then sent back to the addressed location during memory write.
Another type of input transfer, similar to the MB Increment, is designated Add to Memory (ADM). The peripheral grounds the MB INC line only so that both the 01 flip-flop cleared and the INC flip-flop is set at TP1. During TS2 of the true break cycle, a 12-bit data word carried on the peripheral's DATA 00-11 lines is gated
through the interface to the OMN I BUS DATA lines. This data is added in the CP to the data brought from the
addressed memory location, and the result is rewritten in the memory location.
The third type of input transfer is that of a 12-bit data word to the addressed memory location. The peripheral
grounds neither line; thus, TP1 clears the 01 flip-flop and the INC flip-flop. NAND gate E 15 is enabled and
causes NA!\JD gate E23 to negate the BRK DATA CONT L signai. NAND gate El0A is disabled by the O-output
of 01 and, in turn, disables E8B. Because E8C is also disabled, the MO 01 R L signal is again high. During TS2; a
12-bit data word is placed on the OMN I BUS DATA lines and transferred to the addressed memory location.

2-12

2.6 WC OVERFLOW LOGIC AND EMA REGISTER LOGIC
Figure 2-8 shows the WC Overflow logic and the EMA Register logic. The WC OVERFLOW L signal is generated
by the interface during either a normal WC cycle or a true BK cycle if the OMNIBUS OVERF LOW L signal is as·
serted by the CPo aVE RF LOW L is asserted during a WC cycle to indicate that the last word of a block is about
to be transferred. WC OVERFLOW L is then used by the peripheral to terminate the data break operation. Our·
ing a BK cycle the aVE RF LOW L signal is asserted to indicate that an input transfer has resulted in assertion of
the CP CARRY OUT L signal. In this case, we OVERFLOW L is used in the peripheral as directed by the program.
+5V

CA(1)--{>

~E18 ~E26
~

----'''''------~WC
OVERFLOW L

MAC1 ( 1 ) - - - - - - '

OVERFLOW L
(BJ2)

WORD COUNT OVERFLOW
EMA 0

ACTIVE (0)--....._,

EMA 1

EMA 2

~------~y~----~

EXTENDED DATA ADDRESS
EMA REGISTER

BE-OI86

Figure 2-8 Word Count Overflow and EMA Register Logic

The EMA Register logic is used to specify the complete 15-bit memory address to or from which data is to be
transferred. EMAO is the MSB of the 15-bit address, whileMA11 is the LSB (see Chapters 9 and 10 of the
PDP-8IE & PDP-8IM Small Computer Handbook for definitions of OMNIBUS and External bus signals relating
to extended memory). If the computer contains only the basic 4K memory, EMA 0, EMA 1, and EMA 2 are
logic O. When memory is extended (up to 32K, if desired). these three most significant bits are used to indicate
which memory field is to take part in the data transfer. The peripheral specifies the memory field via the External
bus Extended Data Address 00-02 lines (Figure 2-8). This field address is loaded into the BEA (Break Extended
Address) register at TP4 of the first cycle of the break operation (Figure 2-4). If thsperipheral is a 3-cycle device,
the first cycle is the we cycle. However, note that BEA Register information is placed on the EMA lines only during a true BK cycle. Thus, for a 3-cycle device the we and CA Registers must be located in memory field 0, the
basic 4K. The location to or from which data is to be transferred can be contained in an extended memory field.

2-13

SECTION 4 MAINTENANCE
There are no specific maintenance procedures for the KDS-E itself. Each DEC peripheral has an associated
MAINDEC or exerciser program that enables the technician to maintain both the option and the KDS-E Interface.
General information concerning corrective maintenance is included in Volume, Chapter 4. The technician will
find this material helpful. The interface schematic, E-CS-MS360-0-1, indicates important test points, IC locations,
and pin numbers; it should be used when maintenance is being performed.
The KDS-E connects directly to a single peripheral via two cables that are supplied with the interface (refer to
PDP-8IE & PDP-81M Small Computer Handbook, Chapter 10, for cabling rules and suggestions). Each cable connects to the interface with a 40-pin Berg connector and to the peripheral with a DEC M953A cable connector.
From-To information for the cable is given in Table 2-3 (the cables are identical; refer to Chapter 10 of the
PDP-8IE & PDP-81M Small Computer Handbook for details concerning proper connection of the cables).
Table 2-3
K08-E Cable Information
From

From

(M953A Cable Conn.)

(Berg Conn.)

(M953A Cable Conn.)

(Berg Conn.)

Gnd
Gnd
Gnd
B1
Gnd
D2
Gnd
D1
Gnd
E2
Gnd
E1
Gnd
H2
Gnd
H1
Gnd
K2
Gnd
Jl

A
B
C
D
E
F
H

Gnd
M2
Gnd
L1
Gnd
P2
Gnd
M1
Gnd
S2
Gnd
P1
Gnd
T2
Gnd
S1
Gnd
V2
Gnd
Gnd

J
K
L
M
N
P
R
S
T
U
V
W
X

y
Z
AA
BB
CC
DD
EE
FF
HH

JJ
KK
LL
MM
NN
PP
RR
SS
TT
UU
VV

Pins A2, B2, U1 and V1 on M953A not used.
Pins A1, C1, F2, K1, N1, R1, T1, C2, F2, J2, L2, N2, R2, and U2 on M953Aareground pins.

SECTION 5 SPARE PARTS
Table 2-4 lists recommended spare parts for the KD8-E. These spare parts can be obtained from any local DEC
office or from DEC, Maynard, Massachusetts.

2-14

Table 2-4
KDS-E Recommended Spare Parts
DEC Part No.

Description

Quantity

10-01610

Capacitor 0.01 IlF, 100V, 20%

11-00113

Diode D662

19-05575
19-05579
19-09004
19-09057
19-09267
19-09971
19-09486
19-09615
19-09667
19-09686
19-09972
19-09973
19-09928
19-09934
19-09955
19-10010

IC DEC 7400
IC DEC 7440
IC DEC 7402
IC DEC 74H10
IC DEC 74H11
IC DEC 6380
IC DEC 384
IC DEC 8271
IC DEC 74H74
IC DEC 7404
IC DEC 6314
IC DEC 97401
IC DEC 7416
IC DEC 8266
ICDEC7412
IC DEC 2501

2-15

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CONNECTICUT
240 Pomeroy Ave MendE'n, Conn 06450
Te1ephOfle (203) 237·8441/7466
TWX 110·46J.()O~~

MID-ATLANTIC -

SOUTHEAST

REGIONAL OFfiCE:
US ROllI. I. Pr lncelon, New Jersey 08S40

Talephorwt: (609)-452-2940
TWX· 510-685-2338
NEW YORK
9S Cedar lane. Englewood New Jersey 07631

Telephone {201} 871-~. (212}59HI9S5, (212)·736-0447
TWX 710-991-9721
NEW JERSEY
1259 Route -46 Parsippany. New Jersey 07054

Telephone (201)-335-DX/

TWX 710-987-8319

PRINCETON
U.S. Aoute 1

Princeton. New Jersey 08540
Telephone (600) 452-2940
TWX 510-sas-2338
LONG ISLAND
1 Huntington Quadrangle
SUIte IS07 HuntinGton Station . New York 117-'16
Telephone {516)-694-4131, (212)-39S-8095
PHILADELPHIA
Station Square Three. Paoli. PennsylvanIa 19301
Telephone (215)-641-4900/4410
Telex 510·668·8395
WASHINGTON
EII8cullve BUilding
6811 Kenilworth Ave. Riverdale. Meryland 2p84O
Telephone, (:l>1}119-1600/152-8197
TWX' 710-826-9662
DURHAM/CHAPEL HILL
..
2704 Chapel HI1I Boule .... ard
Durham, North Cerolina 27707
Te lephone (919)-489-~7
TWX 510·927-0912
ORLANDO
Sulle I:J). 7001 Lake Ellenor Drive. Orlando. Florida 32809
Telephone, (305)-851-4450
TWX , 810-85().()180
ATLANTA
2815 C learvlew Place. Suite 100.
Atlanta , Georgia 30340
Talephone: (404}-4S1-373<!'3735I3736 TWX 811).757--4223

CENTRAL (conl)
NEW ORLEANS

631 1 Kingston Pike, Suite 21E
Knoxville. Tennessee 37919
Telephone - (6 15}~71
TWX ' 810-583-0123

3100 Al dgelake Ort .... e. SuIte 108
Metalfle, lOUISIana 7OOD2
Te lephcne S04-B37-()257

WEST

CENTRAL
REGIONAL OFFICE:

1850 Frontage Road. Norlhbrook. IIIlnola eoo62
Ta lephone : (312}-,.gs.2500
TWX: 910-fl86-065S
PITTSBURGH

«XI Penn Canler BouleYlrd
PIIIsburgh. Penn.yl ..... "'a 15235
Telephone : (412}243-9404
TWX 710-797-3657
CHICAGO

1850 Fronlage Aotld, Northbrook. l ilinoia 60062
Te lephone (312)-498-2500
TWX- 910-686-0655
ANN ARBOR

230 Huron VIew Boulevard. Ann Arbor, M ichigan 48103
Telephone (313)·761-1150
TWX: 810-223-8)53
INDIANAPOLIS

21 Beachway DrlYe - Suite G
Indillnapolil_ Indlenl 46224
Telephone. {317}2-43-83041
TWX 810-341-3436
MINNEAPOLIS
Suite 111 803J Cedar Ayenue South.

M<nneapoI18, Minnesota 550420
Telephone (612)-854-6562-3--4-5

TWX - 910-576-2818

C LEVELAND

Park Hitl Bldg 35104 Euclid Ave
WIlloughby. OhIo 44094
TE'lephone' (216)-946-8464
TWX. 810~27-2608
ST. LOUIS
Suite 110. 115 Proqress Pky . Marylend Helghta.
Missouri 63043
Telephone: (314)-878-4310
T'NX 910-764--0831
DAYTON

3101 Kelteflng Blvd. Dayton, OhIo 45439
Telephone (513}-299·7377
TWX. 810-459-1676
MILWAUKEE

8531 W Capitol Drl .... e, M ilwaukee, Wisconsin S3222
Telephone' (414)-463-9110
TWX: 910-262-1199
DALLAS

8855 Norlh Stemmons Freeway
Dallal. Tuas 75247
Telephone' (21 4)-638-4880
TWX' 910-861-4000
HOUSTON

3417 Milam Street, Sulle A. Houston. Tues nOO2
Telephone (713)-524-2961
TWX: 910-881-1651

REGIONAL OFFICE
310 Soquel Wwy . Sunnyval., C alifornia 9-«)86
Telephone : (408r735-9200
ANAHEIM
801 E. 8all Aoad . Anehelm, CalifornIa 92805
Telephone (71 4}n6-8932/8730
TWX: 910-591 - 1189
WEST LOS ANGELES
1510 Cotner A .... enue. Los Angelea, C.lIfoma 9OO2S
Telephone: (213}-4793791J4318
TWX; 910-342~
SAN DIEGO
3444 Hancock Street
Sen Diego, CalifornIa 92110
Te lephone ' (71 4}-298-05£,1 , 0S93
TWX g'O-3:)S.IZJl
SAN FRANCISCO
1400 TelTe Bell,
Mounlaln VIew, C.llfornla 940«1
Telaphone: (41S}-964-6200
TWX : 910-373-12Qi
PALO ALTO
S60 San Anh.>fIlo Rd Palo 14.110, California 943)6
Telephone (415)·969·6200
TWX 910-373-1266
OAKLAND
7850 Edgewater DrIVe
Oakland, California 94021
Telephone (.Il15)-635-54S3I7e:J>
TWX 910-366-7238
ALBUQUERQUE
6303 Indlen ~c hool Aoed. N E
Albuquerque. N M 871 10
Telephone (SOS}-296·S411/5A28
TWX: 910-989-0614
DENVER
23)5 South Colorado Blyd . Su lta #5
Denver. Colorado 8)222
Te lephone- (:1)3)-757-33321758- 16561758-1659
TWX, 910-93 1 -~
SEATTLE
1521 l:J)th NE" Be lleYue, Washln ton 98lOS
Telephone' (206)-454-4058/455-5404
TWX; gl0-443-2.))6
SALT LAKE CITY
431 South 3r"d E8St. Salt Lake City. Utah 84111
Telephorfe' (80I}328-qg)8
TWX, 910-925-S83.Il
PHOENIX
4358 East Broadway Aoad
PhoenIx. ArIzona 8S04O
Telephone. (602) 268-3488
TWX; 910-950-4691
PORTLAND
Suite 168
5319 S.W_ Canyon Cl)llrt. Portland. Ore 97221
Telephon. : (503) 297·3761/3765

INTERNATIONAL
EUROPEAN HEADQUARTERS

SWEDEN

Olgllel EqUIpment CorporatIon Internallonttl Europe
81 Route de rAlre
1211 Geneva 26, S .... ltzerland
Telephone 42 19 50
Tele~ 22 683

Olgllal Equipment Aklleboleg

Dlg llal EquIpment Corporation ltd.

STOCKHOLM
Vretenyagen 1.. S-171 ~ Solne Sweden

AUCKLAND

FRANCE
Equipment DIgital SAA_L

NEW ZEALAND

Telex 17050
Telephone : 98 1390
Cable Dig 1181 I Stockholm

CANADA

NORWAY

GRENOBLE
10 ~ Auguste Ravler F-"'113 Grenoble, france
Telephone: (76) g"1 87 32
Telell 32 882 F (Code 212)

Digltel Equipment
OSLO
F.rmlt Servl~e
Waldenmarthreneagata 84-B-86
Oslo I Nor .... "
Telex 166 43
Teleph o'" 3719 8!' 370230

GERMANY

DENMARK

Digital Equipment GmbH
MUNICH
8 Muenchen 13, Wal1enate.nplatl: 2
Telephone: 0811-35031
Telex: 524-226

DIgital Equipment Corporation

PARIS

327 Rue de Charenton, 75 Parla 12 "'., France
Telell.: 21139
Telephone 344-75-07

COLOGNE

COPENHAGEN
Veaterbrogade 140, 1620 Copenhagen V

SWITZERLAND

5 Ko.ln, Brsmarckstras8e 7,

Digital EqUipment Corporation SA

Telephone: 0221-522181 T.lex 8118-2269
Telegram Flip Chip Kee ln

GENEVA
11 Ro jle de • Alfe
1211 (,eneya 26, SWllzerland

FRANKFURT
6078 Neu-Itenburg 2
Am Forathaus Gravenbruch 5-7
Telephone 06102-5526
Telex: 41-7~
HANNOVER
3 Hanno.....r. Podblel.klatraase 102
Telephone : 051 1-89--70-95
Telex: 922-952

Hilton House, 43) Queen Street. BOil 2471 A,
Auckland. New Zealend
Telephona. 75-533

Tfllephone 4279 SO
Telell 22683
ZURICH
Sch"'uchzerSlr. ese 21
CH-8006 ZlIr, -~ SWllurland
Telepho'p 01 ' 50 35 66
Tel e .. 56059

ITALY

DIgItal EqUIpment of Caneda. Ltd
CANADIAN HEADQUARTERS

150 R( ·,.Imond Street Carleton Place. Onlarlo
Telephone {8 13}-2~7-26IS
TWX' 610·561·1651
OTTAWA

120 HolIl!lnd Street. Ottawa 3. Ontario KIY 0X7
Tel.-.phone (613)-nS-2193
TWX: 610-.562-8907
~~
;r.J) L.lk"!lhore Road Ea81. Port Credl l . Ontario

TORONTO

Telephone: (416}-'l74-1'l41

TWX 610-492-4306

MONTREAL

='157<; Cote de lIesse Road
Dorval, Quebec. Canada 760
Telephone 514-636-9393
TWX 610-422-4124
EDMfNTON

5531 - 103 Street
Edmonton . Albarta. Canada
TWX 610-831-2248
Telephone (403)-434·9333
VANCOUVER

0lgll81 Equipment of Caneda . Ltd
1210 Wesl 12th Ayenue
..
Vancouver 9. Bri llah Columbia, Canada
TWX,610-929-2006
Telephone (604}736-5616

Dlgllal EquIpment S pA

ARGENTINA

Digl1al Equipment CorporatIon Ges m,b H
VIENNA
Marlahilfentra8H 136. 1150 Vienna IS, AUltrla '
Telephone: 85 51 86

M/LAN

BUENOS AIRES

UNITED KINGDOM

MADRID

VENEZUELA

Dlgl1al Equipment Co, ltd •
U .K. HEADQUARTERS
Arkwright Aoad. Aeadlng. B.rka
Te lephone 0734-5B3555
Telex: 1M327
READING
The Ev.nlng Po.t Building, Te ... Ro.d
Reading. Berka.

Atalo Ingenieros S.A.. Enrlgue LarTeta 12, Madrid 16
Telephone: 21535 431 Telex: 2n49

CARACAS
Coasln SA (Salea only)
Aperlado S0939
Salane Grande No I. Caracel
TelephO"le 72-9637
Cable INSTRUVEN

AUSTRIA

BIRMINGHA M

29/31. Birmlflgham Road. Sutton Coldfleld. Warwlcka
Telephone. (0Q4.04) 21-355 5501
Te 11- 337060
MANCHESTER
13 Upper PrecInct. Walkden. Manchesler M28 SAl
Tetephon.: 061·790·8411
Telex 660066
LONDON
Bilton Houae. UxbrIdge Road, Ealtng. London W.5.
Telephone , 01·579-2334
Telex: 22371
EDINBURGH
Shiel House. Craigshlii. livingston,
Wesl Lothian, Scotland
Telephone: 32705 / Telex: n7113

NETHERLANDS
THE HAGU E

Dlgllal EquIpment NV
Sir Winston Churchillla&n 370
RI/swlJklThe Hague, Nelherlenda
Telephone, 070-995-160 Telex: 32S33

BELGIUM
BRUSSELS
DIgital Equipment N V./S A.
I~ Rue O' Arlon
1040 Bruaaela. Be lgium
Telephone: 02-139256 Talex: 25297

Corso Garibaldi 49. 20121 Milano. Italy
Teleph~ne 872 748 694:D4
Telell:' 33615

SPAIN

BARCELONA

Aleio Ingenleroa S.A .• Gandtiller 76, Barcelona 6
Telephone- 221 44 66
Digital EqUIpment Corporallon ltd

Coasln S.A
VIney del PI no 4071 Buenoa Airel
Telephone. 52-3185
Telex- 012-2284

CHILE
SANTIAGO

AUSTRALIA
DIgItal Equlpm'nt A ustralle Pty. Ltd .
SYDNEY

P.O Box 491. Crows Nest
N.S.W Australla:rJ6S
Telephone; 439-2566
Telex AA20740
Cable: Dlg ltsl. Sydney
MELBOURNE
60 P.rk Street, South Melbourne. Victor". 320S

T.lephone: 696-1 42

Telex: AA40616

PERTH

643 Murray Street
l(oIest Per1h . Weslern AUll tralla 6005
r~ephone 214-993
Telex : AA92I<tO
BRISBANE

139 Merl .... ale Slreet. South Brlabane
Queenslend. Auslrall. 4101
Telephone 444-047
Telex: M Ol6

Coaaln Chlte Ltda . (aelea only)
Caallla 14588. Correo IS. Santiago
Telephone 396713
Cable COACH IL

JAPAN
TOKYO

Rlkel Trad ing Co . Ltd (aa lea only)
Kozato-Kaikan Bldg
No 18-1 4. Nlahllhlmb.lhl I-chom.
Mlnato-Ku. Tokyo, Japan
.Telephone 591'5246
Ta lex, 761 -4208
DIgital Equipment Corporation International
Kowa Building No. 17, Second Floor
'/·7 Nrahl·Azebu I-Chome
Mlnalo-Ku. Tokyo. Japan
I
TelephOTle,404-5894'6
Telf!1C.: TK-6428

PHILIPPINES
Stanford Computer Corporation
p 0_ Box 1608
416 Dasmarines St" Manda
Talephone 49-68-96
Tel.x: 742~·

INDIA
ADELAIDE

6 Montrose A .... enue
Norwood. South Australia 5067
Telephone 631-339
Telex; AA82B25

H.S, Sonawale Mg Director (Sal.a Only)
HINDITAON SERVICES PUT LTD.
Road
Bombay, India

fBI A Nepean Su