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EK-8A002-MM-002

December 1976

602 pages

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Document:	PDP-8/A Miniprocessor Users Manual
Order Number:	EK-8A002-MM
Revision:	002
Pages:	602
Original Filename:	http://bitsavers.org/pdf/dec/pdp8/pdp8a/EK-8A002-MM-002_PDP-8A_Miniprocessor_Users_Manual_Dec76.pdf

OCR Text

E K-SA002-MM-002

PDP-8/A MINIPROCESSOR
USERS MANUAL

digital equipment corporation • maynard. massachusetts

1st Edition, November 1975
2nd Printing (Rev), December 1976

Copyright © 1976 by Digital Equipment Corporation
The material in this manual is for informaticmal
purpOSElS and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual..
Printed in U.S.A.

This document was set on DIGITAL'S DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
DECCOMM
DECsystnm-l0
DECSYSTEM-20

DECtape
DECUS
DIGITAL
MASSBUS

6/77-14

PDP
RSTS
TYPESET-S
TYPESET-11
UNIBUS

CONTENTS
Page

CHAPTER 1

INTRODUCTION AND DESCRIPTION

1.1
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.7
1.1.S
1.1.9
1.1.10
1.1.11
1.1.12
1.1.13
1.1.14
1.1.15
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5

SYSTEM DESCRIPTION
Central Processor Unit (CPU)
KCS-AA Programmer's Console
Limited Function Panel
Memory
.......... .
MMS-A Core Memory
MSS-A ReadIWrite Semiconductor Memory (RAM)
.......... .
M RS-A Read Memory (ROM)
MRS-FB Reprogrammable Read Only Memory (PROM)
GS016 Power Supply Regulator Module
GS01S Power Supply Regulator Module
Interfacing . . . . . . . . . . . .. "
Option Modules
........... .
DKCS-AA I/O Option Board (MS316) .
KMS-A Extended Option Board (MS317)
Peripheral Options ..
CONSOLE OPERATION
Limited Function Panel
Programmer's Console
Entering Data From the Programmer's Console
Examining Memory Locations
...... .
Entering Data in Memory

CHAPTER 2

INSTALLATION AND ACCEPTANCE TEST

2.1
2.1.1
2.1.2
2.1.3
2.2
2.3
2.3.1
2.3.2
2.4
2.4.1
2.4.2
2.4.3
2.4.3.1
2.4.3.2
2.4.3.3
2.4.3.4
2.4.3.5
2.4.3.6
2.4.3.7
2.4.3.S
2.4.3.9
2.4.3.10
2.4.3.11

SITE CONSIDERATIONS .. .
..... .
Power Source
I/O Cabling Requirements
Fire and Safety Precautions
UNPACKING INSTRUCTIONS
PACKING INSTRUCTIONS ..
BAS-C Chassis Assembly .
Other PDP-Sf A Chassis Assemblies
PDP-S/A BASIC SYSTEM COMPONENTS
Chassis Descriptions
Expansion Techniques . . . . . . .
PDP-SIA Module Descriptions
KKS-A Central Processor Unit (CPU)
MSS-A ReadIWrite Random Access Memory (RAM)
MR8-A Read Only Random Access Memory (ROM)
MMS-AA SK Core Memory
MMS-AB 16K Core Memory
DKCS-AA 1/0 Option Board
KMS-A Extended Option Board
Semiconductor Memory Power Supply
Core Memory Power Supply Regulator
Limited Function Panel
KCS-AA Programmer's Console

iii

1-4
l-S
1-S
l-S
l-S
l-S
l-S
1-9
1-9
1-9
1-9
1-9
1-10
1-10
1-10
1-10
1-10
1-10
1-10
1-10
1-11
1-11

2-1
2-2
2-2
2-2
2-2
2-3
2-3
2-3
2-7
2-S
2-14
2-14
2-14
2-16
2-16
2-21
2-21
2-24
2-2S
2-30
2-32
2-34
2-35

CONTENTS (Cont)
Page

2.5
2.5.1
2.5.2
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.8
2.8.1
2.9
2.9.1
2.9.2
2.9.3
2.9.4
2.10

INSTALLING THE PDP-8/A AND TURNING POWER ON FOR THE FI RST TIME
Environmental and Power Requirements . . . . . . . .
Turning on the Computer for the First Time . . . . . .
TESTING PDP-8/A WITHOUT PAPER TAPE DIAGNOSTICS
Programmer's Console . . . . . . . . . . . . . . . . .
Central Processor Test Houtines . . . . . . . . . . . .
Entering Test Routines from the Programmer's Console
Central Processor Test Houtines . . . . .
LOADING THE RIM AND BINARY LOADERS
Loading the RIM Loader .
Checking the RIM Loader . . . . . . .
Loading the Binary Loader . . . . . . .
Loading Binary Formatted Paper Tapes
TESTING THE PDP-8/A USING MAINDEC DIAGNOSTIC PROGRAMS
Central Processor Unit (CPU) Test
ADDITIONAL DIAGNOSTIC TESTS
Memory Test . . . . . . . . . . .
DKC8-AA Test . . . . . . . . . .
KM8-A Extended Option Board Test
Testing Extended Memories
BASIC PDP-8/A MAINTENA.NCE .

CHAPTER 3

INTERFACING TO THE OMNIBUS

3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.4
3.5
3.6
3.6.1
3.6.2
3.6.2.1
3.6.2.2
3.6.3
3.6.4
3.6.5
3.6.6
3.6.7
3.6.8
3.6.9
3.6.10
3.6.11
3.7
3.7.1

OMNIBUS PHYSICAL DESCRIPTION
BUS SPECIFICATIONS ." . . . .
METHODS OF DATA TRANSFER
Programmed 1/0 Transfer
Interrupt Facility
Data Break Transfer
The External Bus . .
MODULE CONFIGURATION ON THE OMNIBUS
OMNIBUS PIN ASSIGNMENT
MAJOR GROUPS OF SIGNALS . . . . . . . . . .
Memory Address - 15 Lines . . . . . . . . .
Memory Data and Memory Direction Control - 13 Lines
MD<0:11>L .
MD DIR L
Data Bus - 12 Lines . . . . .
1/0 Control Signals - 10 Lines
DMA Control Signals -·8 Lines
Timing Signals - 9 Lines . . .
CPU States - 6 Lines
Memory Timing Signals - 5 Lines
Miscellaneous Signals -- 18 Lines
Special Signals . . . . . . . . . .
Interconnections . . . . . . . . .
DETAILED DESCRIPTION OF THE 96 OMNIBUS SIGNALS
Memory Address - 15 Lines . . . . . . . . . . . . . . .

2-35
2-35
2-35
2-36
2-37
2-37
2-38
2-38
2-40
2-40
2-41
2-41
2-43
2-43
. 2-44
2-45
2-45
2-46
2-50
2-54
2-55

3-1
3-3
3-3
3-3
3-3
3-3
3-4
3-4
3-5
3-8
3-8
3-8
3-8
3-8
3-8
3-8
3-8
3-8
3-8
3-8
3-8
3-9
3-9
3-9
3-9

CONTENTS (Cont)
Page

3.7.1.1
3.7.1.2
3.7.2
3.7.2.1
3.7.2.2
3.7.3
3.7.4
3.7.4.1
3.7.4.2
3.7.4.3
3.7.4.4
3.7.4.5
3.7.4.6
3.7.4.7
3.7.4.8
3.7.5
3.7.5.1
3.7.5.2
3.7.5.3
3.7.5.4
3.7.5.5
3.7.5.6
3.7.5.7
3.7.5.8
3.7.6
3.7.7
3.7.7.1
3.7.7.2
3.7.8
3.7.8.1
3.7.8.2
3.7.8.3
3.7.8.4
3.7.9
3.7.9.1
3.7.9.2
3.7.9.3
3.7.9.4
3.7.9.5
3.7.9.6
3.7.9.7
3.7.9.8
3.7.9.9
3.7.9.10
3.7.9.11
3.7.9.12
3.7.9.13
3.7.9.14

EMA<0:2>L
MA<O:ll>L
Memory Data and D"irection Control - 13 Lines
MD<O:ll>L .
. ....
MD DIR L . . . . . . . .
Data Bus - 12 Lines . . . . .
I/O Control Signals - 10 Lines .
I/O PAUSE L - Pin COl .
INTERNAL I/O L - Pin CLl
SKIP L - Pin CSl
.....
INT RQST L - Pin CPl
C<0:2>L - Pins CEl (CO L); CHl (Cl L); CJl (C2 L)
BUS STROBE L - Pin CKl
NOT LAST XFER L - Pin CLl
INITIALIZE H - Pin CRl ..
DMA Control Signals - 8 Lines
BRK IN PROG L - Pin BE2 .
CPMA DISABLE L - Pin CUl
MS, IR DISABLE L - Pin CVl
MA, MS LOAD CONT L - Pin BH2
BREAK DATA CONT L - Pin BK2
OVERFLOW L - Pin BJ2
BK CYCLE L - Pin BL2
RUN L - Pin BU2
Timing Signals - 9 Lines
CPU STATE - 6 Lines
Major State Lines
IR<0:2>L . . .
Memory Timing Signals - 5 Lines
SOURCE H - Pin AL2, and RETURN H - Pin AR2
WRITE H - Pin AS2 .
INHIBIT H - Pin AP2 ..
STROBE H - Pin AM2
Miscellaneous Signals - 18 Lines
INDl L - Pin CU2, and IND2 L - Pin CV2
MEM START L - Pin AJ2
STOP L - Pin DS2 . . . . . . . . . . . . .
LINK L - Pin AV2
LINK LOAD L - Pin CS2, and LINK DATA L - Pin CR2
F SET L - Pin DP2
USER MODE L - Pin DM2
.............. .
INT IN PROG H - Pin BP2
LA ENABLE L - Pin BM2, and KEY CONTROL L - Pin DU2
PULSE LA H - Pin DR2 . . .
ROM ADDRESS L - Pin AU2
NTS STALL L - Pin BR2
SW - Pin DV2 . . . . . .
POWER OK H - Pin BV2

3-9
· 3-10
. . . 3-10
· . 3-10
· . 3-10
· . 3-11
· . 3-11
· . 3-11
· 3-12
· 3-12
· 3-12
· 3-12
· 3-12
· 3-12
· 3-13
· 3-13
· 3-14
· 3-14
· 3-14
· 3-14
· 3-14
· 3-14
· 3-14
· 3-14
· 3-15
· 3-15
· 3-15
· 3-15
· 3-16
· 3-16
· 3-16
· 3-16
· 3-16
· 3-16
· 3-16
· 3-16
· 3-17
· 3-17
· 3-17
· 3-17
· 3-17
· 3-18
· 3-18
· 3-19
· 3-19
· 3-19
· 3-20
· 3-20

CONTENTS (Cont)
Page
3.7.9.15
3.7.9.16
3.8
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
3.8.6
3.8.6.1
3.8.6.2
3.8.7
3.8.7.1
3.8.7.2
3.8.8
3.9
3.10
3.11
3.11.1
3.11.2
3.11.3
3.12
3.13
3.14
3.14.1
3.14.2
3.14.3
3.14.4
3.14.5
3.14.6
3.14.7
3.15
3.15.1
3.15.2
3.15.3
3.16
3.17
3.18
3.19
3.19.1
3.19.2
3.19.3
3.19.4
3.19.4.1
3.19.4.2
3.19.4.3
3.19.4.4
3.19.4.5

RES - Pin BS2
Special Signals
TIMING
Time Pulses and Time States
Memory Timing
..... .
Relationship Between CPU and Memory Timing
Basic 1/0 Timing ..
Expanded 1/0 Timing
Data Break Timing .
Data Exchange
Final Operations
CPU Major States
IR (FETCH Cycle) .
Interrupt Recognition
Timing Start and Stop .
ASYNCHRONOUS SIGNALS ..
SPECIAL SIGNALS . . . . . . .
ELECTRICAL CHARACTERISTICS AND INTERFACING
Logic Levels
Bus Loads
Driving the Omnibus . . . . . . . . . .
DRIVE AVAILABLE FOR PERIPHERALS
RECEIVERS AND LOAD RELIEF TECHNIQUES
INTERFACE EXAMPLES . . . . . . . .
Programmed 1/0 Interface Example
Flag Logic
Interrupt Request
Output Buffer
Input Buffer
1/0 Control
Input/Output Timing for Programmed I/O Interfaces
PROGRAM INTERRUPT TRANSFERS
Interrupt Timing . . . . . . .
Data Break Interface Ex,ample
Data Break Timing . . . . . .
THREE-CYCLE DATA BREAK ..
GENERAL CAUTIONS REGARDING INTERFACE DESIGN
TRANSMISSION LINE EFFECTS
EXTERNAL BUS . . . . . . . . .
Positive 1/0 Bus Interfacing
The Nature of the Extemal Bus
External Bus Signals
External Bus Signals
BAC 00-11
AC 00-11
BMB 00--11
BIOP 1,2, and 4
BTS1,BTS3

· 3-20
· 3-21
· 3-21
· 3-21
· 3-21
· 3-22
· 3-22
· 3-23
· 3-23
· 3-23
· 3-23
· 3-24
· 3-24
· 3-24
· 3-24
· 3-25
· 3-25
· 3-25
· 3-25
· 3-25
· 3-25
· 3-28
· 3-28
· 3-30
· 3-30
· 3-32
· 3-32
· 3-32
· 3-33
· 3-33
· 3-33
· 3-33
· 3-33
· 3-33
· 3-35
· 3-37
· 3-38
· 3-39
.. 3-39
· 3-39
· 3-39
· 3-40
· 3-40
· 3-40
· 3-40
· 3-41
· 3-41
· 3-41

CONTENTS (Cont)
Page

3.19.4.6
3.19.4.7
3.19.4.8
3.19.4.9
3.19.4.10
3.19.4.11
3.19.4.12
3.19.4.13
3.19.4.14
3.19.4.15
3.19.4.16
3.19.4.17
3.19.4.18
3.19.4.19
3.19.4.20
3.19.4.21

B RUN ..
AC CLEAR
SKIP . . .
B INITIALIZE 1
DATA 00-11
B BREAK
DATA OUT
DATA ADD 00-11
BRK RQST
ADD ACCEPTED
MBINCREMENT
CA INCREMENT INH
3 CYCLE . . . . . . .
WC OVE RF LOW .. .
EXT DATA ADD 0-2
B INITIALIZE 2 ..

· 3-41
· 3-41
· 3-41
· 3-41
· 3-41
· 3-42
· 3-42
· 3-42
· 3-42
· 3-42
· 3-42
· 3-42
· 3-42
· 3-42
· 3-43
· 3-43

CHAPTER 4

CENTRAL PROCESSOR UNIT

4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.3
4.3.1
4.3.2
4.3.2.1
4.3.2.2
4.3.2.3
4.3.2.4
4.3.2.5
4.3.2.6
4.3.2.7
4.3.2.8
4.3.2.9
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.5
4.5.1
4.5.2

CENTRAL PROCESSOR UNIT, GENERAL DESCRIPTION
TIMING GENERATOR
Power On/Run Logic
Timing Register Logic
CPU Timing Logic
Memory Timing Logic
I/O Transfer Stall Logic
Memory Stall Logic
FRONT PANEL OPERATIONS
Limited Function Panel
Programmer's Console
Clock Timing Logic
Register Logic
Multiplexer Logic
Register/Multiplexer Gating Logic Timing
ADDRS/DISP Readout Circuit Logic
Function Button Logic
DISP Button Logic . . .
THIS, HLT, BOOT Logic
Console Control Logic
INSTRUCTION DECODER
Instruction Register Logic
Major State Register Logic
DATA ENA/DATA CMP Logic
Address Update Logic
Major Register Load Signal Logic
AC Register Control Logic
MAJOR REGISTER GATING
Page Logic
Carry In Logic

vii

4-1
4-3
4-4
4-5
4-7
4-7
4-8
· 4-11
· 4-11
· 4-14
· 4-16
· 4-22
· 4-22
· 4-26
· 4-27
· 4-30
· 4-32
· 4-36
· 4-39
· 4-40
· 4-41

· 4-45
· 4-46
· 4-49
· 4-50
· 4-51
.4-53
.. 4-54
· 4-57
.. 4-59

CONTENTS (Cont)
Page

4.5.3
4.5.4
4.6
4.6.1
4.6.2
4.6.3
4.6.4

Skip Logic
Link Logic
I/O TRANSFER LOGIC
Programmed I/O Transfer Logic
Processor lOT Logic
Program Interrupt Logic
Data Break Transfers

CHAPTER 5

MEMORY OPTIONS

· 4-63
· 4-65
· 4-67
· 4-67
· 4-67
· 4-73
· 4-73

SECTION 1
MRS-A READ ONLY MEMORY (ROM)

5.1
5.1.1
5.1.2
5.2
5.2.1
5.2.2
5.2.3
5.3
5.3.1
5.3.2
5.3.2.1
5.3.2.2
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.6.1
5.4.6.2
5.4.6.3
5.4.6.4
5.4.7
5.4.7.1
5.4.7.2
5.4.7.3
. 5.4.7.4
5.4.7.5
5.5

MRS-A READ ONLY MEMOBY (ROM) DESCRIPTION
MRS-A Physical Description
M RS-A Specifications
FUNCTIONAL DESCRIPTION
Addressing . . . . . . .
Timing and Control
Input and Output Signal Definition
PROGRAMMING
..... .
Programming Operation
Programming Procedure . . . . .
Preparation of the Paper Tape
Blasting
.......... .
DETAILED LOGIC DESCRIPTION '"
Addressing Block Diagram Description
Field and Size Selection
Chip Select Decoder
The 13th Bit '"
Timing and Control
Timing Generation
Control Flip-Flops
Sequence of Control Operations
Initial Conditions
..... .
Single Stepping . . . . . . . .
Memory Data and Memory Register
Memory Chips . . . . . . . .
Address and Chip Enable Inputs
Memory Output Register
Data Transfer Lines
Physical Layout
MRS-A SWITCH LIST . . . .

5-3
5-3
5-3
5-3
5-5

5-5

5-S
5-S
5-S
5-S
5-9
5-9
5-9
5-9
5-10
5-12
5-12
5-14
5-16
5-16
5-16
5-16
5-16
5-17
5-1S

5-19
5-19
5-19
5-19
5-19

SECTION 2
RANDOM ACCESS MEMORY (RAM)

5.6
5.6.1
5.6.2

SEMICONDUCTOR RANDOM ACCESS MEMORY (RAM-MSS-A) DESCRIPTION
Physical Description
MSS-A Specifications

viii

5-21
5-21
5-23

CONTENTS (Cant)
Page

5.7
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.S
5.9
5.10
5.10.1
5.10.2
5.10.3
5.10.4
5.11
5.11.1
5.11.2
5.11.2.1
5.11.2.2
5.11.3
5.11.4
5.12

FUNCTIONAL DESCRIPTION
Address Select Logic
Timing and Control
Memory Chip Array
Memory Data
Operation
.....
INPUT AND OUTPUT SIGNALS
........ .
PROGRAMMING
DETAILED LOGIC DESCRIPTION
Address Selection Logic
Field Selection . . . .
Starting Address
Memory Size Selection
TIMING AND CONTROL LOGIC
MSS-A Timing Chain . . .
Operation of a RAM Cycle
Read Cycle . . . . .
Write Cycle . . . . .
Operation of a ROM-RAM Cycle
Memory Data and Memory Output Register
SWITCH DEFINITIONS . . . . . . . . . . .

5-23
5-23
· 5-24
5-24
· 5-25
5-25
5-25
5-26
5-26
5-27
5-27
· 5-2S
· 5-2S
5-29
• 5-29
· 5-30
5-30
· 5-33
· 5-33
5-37
· 5-37

5.13
5.13.1
5.13.2
5.13.3
5.13.4
5.13.5
5.13.6
5.13.7
5.13.S
5.13.9
5.13.10
5.13.11
5.13.12
5.14
5.14.1
5.15
5.15.1
5.15.2
5.15.3
5.15.4
5.15.5
5.15.6
5.15.7
5.15.S
5.15.9
5.16

SECTION 3
MRS·FB REPROGRAMMABLE READ ONLY MEMORY (PROM)
MRS-FB 1 K MEMORY
M RS-FB Specifications
M RS-FB Description .
Address Decoder . . .
Starting Address Decoder
Bootstrap Operation ..
Memory Control and Timing Logic
Rear or ReadlWrite
1K PROM
13th Bit PROM
ROM Address Flag
ReadlWrite Memory (RAM)
Data Multiplexer . . . .
MRS-FB PROGRAMMING
PROM Erasing Procedure
DETAILED LOGIC DESCRIPTION
Address Decoder . . . . . • .
Timing and Processor Control for SW Start of Memory
Field and Starting Address Select Logic
Memory Address Control Signal Generation
NTS STALL . . . . . . . . . . . . .
ROM ADDR . . . . . . . . . . . . . . . .
1K PROM Memory and Control Logic .. .
256 ReadlWrite Memory and Control Logic
ROM and RAM Data Multiplexer
MAl NTENANCE . . . . . . . . . .

· 5-41
· 5-42
5-42
· 5-42
· 5-44
5-44
5-44
· 5-44
5-44
· 5-44
5-45
5-45
· 5-4S
5-4S
5··51
5-51
5-51
5-51
5-54
5-55
5-55
5-55
5-55
· 5-57
5-57
5-59

CONTENTS (Cont)

Page
SECTION 4
CORE MEMORY SYSTEMS
5.17
5.18
5.19
5.19.1
5.19.2
5.19.3
5.19.4
5.19.5
5.19.6
5.19.7
5.19.8
5.19.9
5.19.10
5.19.11
5.19.12
5.19.13
5.19.14
5.19.15
5.19.16
5.19.17
5.19.18
5.19.19
5.19.20
5.19.21
5.19.22
5.19.23
5.19.24
5.19.25
5.19.26
5.19.27
5.19.28
5.19.29
5.19.30
5.19.31
5.19.32
5.19.33
5.19.34
5.19.35
5.20
5.20.1
5.20.2
5.20.3
5.20.4
5.20.5
5.20.6

MEMORY SYSTEM, GENERAL DESCRIPTION
MEMORY SYSTEM, FUNCTIONAL DESCRIPTION
MM8-AA 8K CORE MEMORY SYSTEM
Memory Core
Hysteresis Loop
X/Y Select Lines
Read Operations
Write Operations
Magnetic Core In Two-Dimension Array
Assembly Of 12-Stacked Core Mats
Core Selection System . . . . . . . . .
Organization Of X/Y Drivers And Current Source
X And Y Current Sources - General Description
Stack Charge Circuit ..
Power Fail Circuit
Core Selection Decoders
Address Decoding Scheme
Diode Selection Matrix ..
Operation Of Selection Switches
Operation Of The Core Selection Switches
Sense/Inhibit Function
Sense/Inhibit Line
ReadlWrite Operation
Inhibit Control Logic
Field Select Control LO!Jic
Sense Register Enable Logic
Sense Register Clear Timing
Strobe Control Logic
Strobe Setting Jumpers
Sense Amplifiers . . .
Sense Register
Inhibit Driver Load Gates
Inhibit Drivers
Current Source
POWER NOT OK
Test Points . . .
Circuit Variables
Core Memory Troubleshooting
MM8-AB 16K CORE MEMOHY SYSTEM
Assembly Of Twelve Core Mats
Address Decodi ng Scheme . . . . .
Operation Of The Core Selection Switches
ReadlWrite Operation
Field Select Control Lo'gic
Inhibit Control Logic

5-61
5-61
· 5-63
· 5-63
5-63
5-64
5-65
5-65
5-65
5-65
5-65
5-69
5-69
5-70
5-70
5-70
5-73
· 5-73
5-73
5-79
5-79
5-79
5-79
5-81
5-81
5-82
· 5-82
5-84
5-84
5-86
5-86
5-87
5-87
5-88
5-90
5-91
· 5-93
5-93
5-94
5-94
5-94
5-100
5-100
5-104
5-105

CONTENTS (Cont)

Page
5.20.7
5.20.8
5.20.9
5.20.10
5.20.11
5.20.12
5.20.13
5.20.14
5.20.15
5.20.16
CHAPTER 6

Sense Register Enable Logic
Sense Register Clear Timing
Strobe Control Logic . .
Strobe Setting Jumpers
Inhibit Driver Load Gates
Sense Amplifier
Inhibit Drivers
Current Source
POWER OK
Test Points ..

5-105
5-105
5-106
5-106
5-107
5-108
5-108
5-109
5-109
5-109

PDP-8/A OPTION MODULES
SECTION 1
DKC8-AA I/O OPTION MODULE (M8316)

6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.2
6.2.1
6.3

6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.4
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.5.1
6.5.5.2
6.5.6
6.5.7
6.5.8
6.6

6.7
6.8

6.8.1
6.8.2
6.8.3

DKC8-AA I/O OPTION MODULE BLOCK DIAGRAM DESCRIPTION
Serial Line Unit (SLU) . . . . . .
General Purpose 12-Bit Parallel I/O
Real Time Crystal Clock
Front Panel Control
SERIAL LINE UNIT . . . . .
SLU Specifications .. .
SLU FUNCTIONAL DESCRIPTION
Methods of Data Transfer
Transmit Operation
Receive Operation
SLU Timing Generator
Parity Generation
Number of Bits Per Character
SLU PROG RAMM I NG . . . . . .
SLU DETAILED LOGIC DESCRIPTION
Device Select Logic
.... .
SLU Operation Decoder . . . . . .
SLU Interrupt and Skip Logic
SLU Timing Generator and Baud Rate Select Logic
Universal Asynchronous ReceiverlTransmitter (UART)
UART Receive Operation
UART Transmit Operation
Level Converters
Reader Run Logic . . . . . . .
Request to Send and Terminal Ready
REAL TIME CLOCK
.......... .
REAL TIME CLOCK PROGRAMMING ..
REAL TIME CLOCK DETAILED LOGIC DESCRIPTION
Device Select and Operation Decoder Logic
Real Time Clock Frequency Dividers
Real Time Clock Interrupt and Skip Logic

6-3

6-4
6-4
6-4
6-4
6-4
6-4
6-5
6-6
6-6

6-7
6-7
6-8

6-9
6-9
6-9
6-10

6-10
6-11
6-12

6-14
6-14

6-17
6-18
6-18

6-21
· 6-21
· 6-21
· 6-21
· 6-21
6-22

6-23

CONTENTS (Cont)
Page
6.9
6.10
6.11
6.11.1
6.11.2
6.11.3
6.11.3.1
6.11.3.2
6.11.4
6.11.5
6.11.6

GENERAL PURPOSE PARALLEL I/O BLOCK DIAGRAM DESCRIPTION
GENERAL PURPOSE PARALLEL I/O PROGRAMMING
DETAILED LOGIC DESCRIPTION . . . . .
Device Select and Operations Decoder
Interrupt and Skip Logic . . . .
Receive and Transmit Operations
Transmit Operation
Receive Operation
Strobe . . . . . . . .'.
Parallel I/O Output Reg!ister
Parallel I/O Input Buffer and Data Gates

6·23
· 6·24
6·24
6·24
· 6-27
6·27
· 6·27
6·29
6·29
.. 6·29
6·30

SECTION 2
KM8·A EXTENDED OPTION MODULE (M8317)
6.12
6.12.1
6.12.2
6.12.3
6.12.4
6.13
6.14
6.14.1
6.14.2
6.14.3
6.14.4
6.14.5
6.15
6.16
6.16.1
6.16.2
6.17
6.17.1
6.17.2
6.17.3
6.17.4
6.17.5
6.17.6
6.17.7
6.17.8
6.17.9
6.18
6.18.1
6.18.2
6.18.3
6.19
6.19.1
6.19.2

KM8-A EXTENDED OPTION BOARD (M8317)
Memory Extension . . .
Timeshare Option
Power Fail/Auto Restart
Bootstrap Loader
MEMORY EXTENSION AND TIMESHARE DESCRIPTION
MEMORY EXTENSION BLOCK DIAGRAM DESCRIPTION
....... .
Control Logic
Instruction Field Register (I F) .
Data Field Register (DF) . . .
Instruction Buffer Register (lB)
Save Field Register (SFI
TIMESHARE CONTROL BLOCK DIAGRAM DESCRIPTION
MEMORY EXTENSION AND TIMESHARE PROGRAMMING
Memory Extension Pro~Jramming
........... .
Timeshare Programmin~J . . . . . . . . . . . . . . . . .
MEMORY EXTENSION AND TIMESHARE DETAILED LOGIC DESCRIPTION
Memory Extension/Timeshare Device Select . . . . .
Memory Extension and Timeshare Operation Decoder
Input Multiplexer
......... .
Instruction Field Register and Controls
Data Field Register and Controls . . .
Output Multiplexer
........ .
Timeshare User Buffer I~egister and Control Logic
Trap Detect Logic . . . . . . . . . . . . . . . , .
Interrupt Inhibit Logic . . . . . , . . . . . . . .
POWER FAIL/AUTO RESTJ\RT AND BOOTSTRAP LOADER
Power Fail!Auto Restart Block Diagram Description
Power Fail/Auto Restart Programming . . . . . . . . . .
Bootstrap Loader Block. Diagram Description . . . . . .
BOOTSTRAP ROM ORGANilZATION AND PROGRAMMING
ROM Organization . . . . . . . .
Auto-Restart/Bootstrap Sequence

xii

6-32
.. 6-33
6·33
6·33
6·33
· 6·33
· 6·33
· 6·33
6·35
6·35
6-35
6·35
6-35
6·35
6·36
6·38
6-38
6-38
6·39
6·41
6-41
6-46
6·46
6·46
6·51
6-51
6-51
6·51
6·53
· 6-54
6-54
6-55
6-55

CONTENTS (Cont)
Page
6.19.3
6.19.4
6.19.5
6.20
6.21
6.21.1
6.21.2
6.21.3
6.22
6.22.1
6.22.2
6.22.3
6.22.4
6.22.5
6.22.6
6.22.7
6.22.S

ROM Programming Examples
Bootstrap Example . . .
Obtaining Blank ROMs . . .
ROM PROGRAM LISTING
POWER FAIL/AUTO RESTART AND BOOTSTRAP OPERATION AND TIMING
Power Fail Operation
...... .
Auto-Restart Operation and Timing . . . . . . . . . . . • . . • . . . . .
Bootstrap Operation and Timing .. . . . . . . . . . . . . . . . . . . . .
POWER FAIL/AUTO-RESTART AND BOOTSTRAP OPERATION DETAILED
LOGIC DESCRIPTION
...................... .
Power Fail/Auto-Restart Device Select and Operation Decoder
. ....
Power Fail Interrupt and Skip Logic . . .
Bootstrap and Auto-Restart Timing Clock
Bootstrap Initialization Logic
..... .
Auto-Restart Initialization Logic . . . . .
Auto-Restart and Bootstrap Address Counters
ROM Memory Control and Multiplexers . . .
Bootstrap and Auto-Restart Operation Control Logic

CHAPTER 7

POWER SUPPLY

7.1
7.2
7.2.1
7.2.2
7.2.2.1
7.2.2.2
7.2.2.3
7.2.2.4
7.2.2.5
7.2.2.6
7.2.2.7
7.3
7.3.1
7.3.2
7.3.2.1
7.3.2.2
7.3.2.3
7.3.2.4
7.3.2.5
7.3.2.6
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5

GENERAL . . . . . . . . . . . . . . . . . . . . . . . . .
PDP-S/A SEMICONDUCTOR BASIC POWER ASSEMBLY
Power Board . . . . . .
Regulator Board (GS016)
........ .
........ .
+5 Vdc Regulator Circuit
+5 Vdc Regulator Circuit, Battery Operation
Battery Empty Circuit .
Battery Charging Circuit
±15 Vdc Circuit
POWER OK H Circuit
AC LOW L Circuit ..
SA400/600/S00 BASIC POWER ASSEMBLY
H9194 Connector Block Assembly
Regulator Board (GS01S)
+5 Vdc Regulator Circuit
-5 Vdc Regulator Circuit
+20 Vdc Regulator Circuit
±15 Vdc Circu it
POWER OK H Circuit
AC LOW L Circuit ..
SA420/620/S20 BASIC POWER ASSEMBLY
General . . . . . . . . . . . . . . . . •
Interlock and Triac Control Circuit
Line Level Transformer and Peak Detector
Thermistor/Thermostat and Emergency Shutdown
POWER OK H Circuit . . . . . . . . . . . . . .

xiii

6-56
6-56
6-56
6-57
· 6-57
· 6-57
· 6-6S
· 6-70
· 6-70
· 6-71
6-71
· 6-73
6-73
· 6-73
· 6-75
· 6-75
· 6-75

7-1
7-2
7-2
7-4
7-5
7-6
7-S
7-S
7-9
7-9
7-11
· 7-12
7-12
7-16
7-16
7-16
7-16
7-1S
7-1S
7-19
7-20
· 7-20
7-22
· 7-22
7-22
· 7-26

CONTENTS (Cant)
Page
CHAPTER 8

MAINTENANCE AND TROUBLESHOOTING

8.1
8.1.1
8.1.2
8.2
8.2.1
8.2.2
8:3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.4
8.4.1
8.4.1.1
8.4.2
8.4.2.1
8.4.2.2
8.5
8.5.1
8.5.2
8.6
8.6.1
8.6.2
8.6.3

MAINTENANCE AND TROUBLESHOOTING REQUIREMENTS
Diagnostic Programs . . . . . . . . . . . •
Equipment . . . . . . . . . . . . . . . . .
PREVENTIVE MAINTENANCE INSPECTIONS
Scheduled MaintenancEl
The Importance of a Preventive Maintenance Schedule
PDP-8/A TROUBLESHOOTIING .
..... .
Operator Errors
Troubleshooting Procedures
Validation Tests
Cable Problems . . . . . . .
Log Entry
........ .
Removal and Replacement of Modules
Removal and Replacement of Regulator Board
Removal and Replacement of LEOs on the Limited Function Panel
Removal and Replacement of LEOs on the Programmer's Console
POWER SUPPLY ADJUSTMENTS
G8016 Power Supply Adjustment
+5 V Adjustment (G8016} .
G8018 Power Supply Adjustment
+5 V Power Supply Adjustment
+20 V Power Supply Adjustment
POWER FAIL/AUTO-RESTART LEVEL ADJUSTMENT (G80l6 AND G8018)
G8018 Power Fail/Auto-Restart Adjustment
G8016 Power Fail/Aut()-Restart Adjustment
LINE VOLTAGE AND FREOUENCY COMBINATIONS
8A400/600/800
8A420/620/820
PDP-8/A Semiconductor

CHAPTER 9

SPARE PARTS

APPENDIX A

INSTRUCTION SUMMARY

APPENDIX B

OMNIBUS SIGNAL LOCATOR

APPENDIX C

MODULE ASSIGNMENT AND POWER REQUIREMENTS

APPENDIX D

PROGRAM LOADING PROCEDURES

0.1
0.2
0.3
0.4

TURNING THE SYSTEM ON ..
READ-IN MODE (RIM) LOADER
BINARY (BIN) LOADER
LOADING BINARY TAPES

APPENDIX E

ASCII CHARACTER CODES

8-1
8-1
8-3
8-3
8-3
8-3
8-3
8-3
8-4
8-4
8-4
8-5
8-5
8-5
8-5
8-6
8-6
8-6
8-6
8-6
8-6
8-6
8-6
8-9
8-9
8-9
8-9
.. 8-11
. 8-11

0-1
0-2
0-3
0-4

xiv

CONTENTS (Cant)

Page
APPENDIX F

DEVICE CODES

APPENDIX G

MEMORY CYCLE TIME SUMMARY

APPENDIX H

ENGINEERING DRAWINGS

ILLUSTRATIONS

Figure No.
1·1
1·2
1·3
1-4
1·5
1-6
2·1
2·2
2·3
2-4
2·5
2·6
2-7
2·8
2·9
2·10
2·11
2·12
2·13
2-14
2-15
2·16
2·17
2·18
2·19
2·20
2-21
2·22
2·23
2-24
2·25
2·26
3·1
3-2
3-3
3-4

Title
PDP-8/A Miniprocessor
.....
PDP-81 A System Block Diagram
PDP-8/A Limited Function Panel
PDP-81A Programmer's Console
Status Information . . . . . . . .
State Information
...... .
8A420, 8A620, 8A820 Packaging
PDP-8/A Computer Packaging (Inner)
PDP·8/A Computer Packaging (Outer)
Part of M8320 Module Showing R55 which is Removed for 8A Operation
PDP-8/A Semiconductor Chassis . . . . . . . . . . . . .
PDP-8/A Semiconductor Computer Chassis Dimensions
PDP-8/A Chassis (H9300) (Transformer Cover Removed)
PDP-8/A Chassis (8A420, 8A620, 8A820)
8A420/620/820 Chassis Dimensions
8A600/8A620 Expansion
....... .
KK8·A (M8315) CPU Module . . . . . .
MS8-A (M8311) ReadIWrite Random Access Memory
MR8-A (M8312) Read Only Memory (ROM)
MM8-AA Core Memory
...... .
MM8-AB Core Memory
......... .
DKC8-AA (M8316) I/O Option Board .. .
Etch Revision of DKC8·AA (M8316) I/O Option Board
KM8-A (M8317) Extended Option Board
.....
Semiconductor Memory Regulator Board (GS016)
8A MASTER/SLAVE Switch
G8018 Core Memory Regulator Board
Limited Function Panel
KC8-AA Programmer's Console
PDP·8/A Electrical Connections
Paper Tape Leader . . . .
L T33 Teletype Controls
PDP·8/A Omnibus (H9194)
PDP·S/A Hex and Quad Modules
SA Chassis (H9300)
..... .
Modules Connected With H851 Type Connector

Page
1-6
1-7
1-8
1-11
1-16
1-16
2-4
2-5
2-6
2-7
2-9
2-10
2-11
2-12
2-13
2-14
· 2-15
2-17
2-19
2-22
2-23
2-25
2·26
2-28
2-31
2-32
2-33
2-34
2·35
2-37
· 2·42
· 2-42
3-2
3·3
3-4
3-6

ILLUSTRATIONS (Cont)

Figure No.
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14

4-15
4-16
4-17
4-18
4-19
4-20

Title
Omnibus Signal Locator . ' . . .
Timing For One Memory Cyc:le
Time State and Time Pulse Change Timing
TP3 Timing During lOT Transfer
Memory Timing
Memory Timing
Write Timing .
Basic I/O Timing
CAF Instruction Timing
Timing to Stop CPU Using Not Last XFER L
Transfer Timing
....."..
External Loading of Link Timing
CPU Restart Timing
Data Break Timing . . . .
Data Exchange Timing ..
End of Data Break Timing
CPU Major States Timing
FETCH Cycle Timing
Interrupt Timing
Start Timing
Stop Timing
Typical I/O Decoder
Sample Programmed I/O Interface
Timing for Sample Programmed I/O
Sample One Cycle Data Break Interface
Data Break Control Timing Diagram ..
Three Cycle Data Break Simplified Block Diagram
Parallel Connection of Peripherals . . . . . . . .
External Bus Signals and Relalted Omnibus Signals
CPU Block Diagram
..... .
Timing Generator Block Diagram
Power ON/RUN Logic . . . . .
Timing Register Logic . . . . .
Timing Register Normal Timing
CPU Timing Logic
CPU Timing Signals
Memory Timing Logic
Memory Timing Signals
I/O Transfer Stall Logic
I/O Timing (NOT LAST XFER L Asserted)
Memory Stall Logic
........... .
Timing, NTS STALL L Asserted . . . . . .
Limited Function Panel Circuit Board Schematic, 8A Computers
Limited Function Panel Circuit Board Schematic, PDP-8/A Semiconductor Computer
Programmer's Console Block Diagram
Clock Timing Logic
Timing, Clock Timing Logic
Register Logic
Multi plexer Logic
.....

xvi

Page
· 3-7
· 3-21
3-21
3-22
3-22
· 3-22
3-22
3-23
3-23
3-23
3-23
3-23
3-24
· 3-24
3-24
3-24
3-24
3-24
3-25
3-25
3-25
3-30
· 3-31
3-35
3-36
3-37
· 3-38
3-40
· 3-41
4-2
4-3
4-4
4-6
4-7
4-8
4-9
4-9
4-10
· 4-10
.. 4-12
· 4-14
· 4-15
· 4-17
· 4-18
.4-20
· 4-23
· 4-24
.. 4-25
· 4-27

ILLUSTRATIONS (Cont)
Figure No.
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
4-32
4-33
4-34
4-35
4-36
4-37
4-38
4-39
4-40
4-41
4-42
4-43
4-44
4-45
4-46
4-47
4-48
4-49
4-50
4-51
4-52
4-53
4-54
4-55
4-56
4-57
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11

Title
MPX/Enable Signal Relationship .
Register/Multiplexer Gating Logic
Register/Multiplexer Gating Signal Timing
ADD RS/D ISP Readout Circuits . . . . .
OCTAL Designations - Resultant Displays
Function Button Logic .
o ISP Button Logic . . . . . . . . . .
THIS, HLT, BOOT Logic
..... .
Console Control Logic - STATE, MD
Console Control Logic - MA, DATA, SR ENAB LE
ROM A Logic
ROM B Logic
ROM C Logic
ROM 0 Logic
ROM E Logic
ROM F Logic
ROM H Logic
ROM J Logic
Instruction Registers Logic
Major State Registers Logic
Data ENA/Data CMP Logic
Address Update Logic
Major Register Load Signal Logic
AC Register Control Logic . . .
Block Diagram, Major Register and Gating (BITO)
Page Logic
Carry In Logic
Skip Logic
Link Logic
Major Register Gating (BITOO)' Prpgrammed I/O Transfer
Programmed I/O Transfer Logic
Processor lOT Logic . . . . . . . . . . . . . . .
Program Interrupt Logic . . . . . . . . . . . . .
Major Register Gating (BITO), Data Break Transfer
Data Break Transfer Control Signal Logic
AUTO-START Timing . . . . . . . . .
AUTO-START Timing, CPU Logic .. .
MR8-A ROM Memory Module (M8312)
ROM/RAM Configuration
ROM Block Diagram . . . . . . . . . .
ROM Timing Diagram . . . . . . . . .
Detailed Block Diagram of Address Select Logic
Field and Size Selection . . . . . .
...... .
Chip Select Decoding
13th Bit Mapping into 1K X 1 Array
13th Bit Mapping into 4K X 1 Array
Timing and Control Logic
ROM-RAM Selection Timing . . . .

xvii

Page

· 4-28
· 4-29
· 4-30
· 4-31
· 4-32
· 4-33
· 4-37
· 4-39
· 4-40
· 4-41
· 4-42
· 4-42
· 4-43
· 4-43
· 4-44
· 4-44
· 4-44
· 4-44
· 4-45
· 4-47
· 4-49
· 4-50
· 4-51
· 4-53
.4-55
· 4-59
· 4-62
· 4-64
.4-66
· 4-68
· 4-69
· 4-71
· 4-74
· 4-75
.4-77
· 4-78
· 4-79
5-4
5-4
5-6
5-7
5-10
5-11
5-13
5-13
5-14
5-15
5-17

IL.LUSTRATIONS (Cont)

Figure No.
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
5-36
5-37
5-38
5-39
5-40
5-41
5-42
5-43
5-44
5-45
5-46
5-47
5-48
5-49
5-50
5-51
5-52
5-53
5-54
5-55
5-56
5-57
5-58
5-59

Title
Single Step Operation
...... .
Arrangement of 1 K Memory .. .
ROM 4K Memory - Physical Layout of Module
RAM MS8-A Module M8311
MS8-A Block Diagram
Read Cycle Flow Chart
Write Cycle Flow Chart
Address Selection Logic
ROM (lC8223) Truth Table
Memory Timing Chain
Read Cycle Timing Diagram
TP4 Logic
Source Time Logic
Operations at TPl
Stall + 400 ns Logic
Write Cycle Timing Diagram
Write Cycle Logic
.....
ROM-RAM Initial Delay Logic
ROM-RAM Initial Delay Timijng Diagram
Detailed Timing of Initial Delay in ROM-RAM Cycle
Memory Array and Output Register
Simplified MR8-FB Block Diagram
M R8-FB Block Diagram
Bootstrap Operation Timing
Read Timing . . . . . . . .
13th Bit ReadtWrite Timing
PROM Block Diagram
PROM Addressing Scheme .
Address Decoder Logic . . .
ML8-F Timing and SW Operation Control Logic
Field and Starting Address Select Logic
Memory Address Control Signal Generator
....... .
PROM and Control Logic
ROM and RAM Data MultiplE!xer and Latch
RAM Memory (256 Word) . . . . . . . . .
Core Memory System Functional Block Diagram
Core Memory Timing Diagram . . . .
MM8-AA Core Memory Block Diagram
Magnetic Core . . . . . . . . . .
Magnetic Core Hysteresis Loop
Three Wire Memory Configuration
Core Stack Layout . . . . . . . .
8K + 12 Bit Stack and Sense Lines
Current Path For Write Current
Current Path For Read Currel1t
Decoding of X and Y Driver Current Sources Block Diagram
Stack Charge Circuit
Power Fail Circuitry . . . . . . . . . . . . . . . . . . . .

xviii

Page
· 5-17
5-18
5-18
5-22
5-24
· 5-26
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5-62
· 5-62
5-63
5-64
5-64
5-66
5-67
5-68
5-69
5-70
5-71
· 5-72
5-72

ILLUSTRATIONS (Cont)
Figure No.
5-60
5-61
5-62
5-63
5-64
5-65
5-66
5-67
5-68
5-69
5-70
5-71
5-72
5-73
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5-83
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5-87
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5-90
5-91
5-92
5-93
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14

Title
Decoding Relationships
.....
. ........ .
Organization of Planar Stack Diode Matrix for X Select Lines
Operation Of Selection Switches To Select Line XO
Detailed Operation Of Selection Switches
Inhibit Operation For Bit 0
Inhibit Control Logic
......... .
Field Select Control Logic . . . . . . . .
Memory Sense Register Enable Logic for Bit 0
Clear Time Control Logic
Strobe and Clear Timing
Strobe Control Logic
Strobe Adjustment . . .
Sense Amplifiers
Inhibit Drivers Load Gates
Inhibit Drivers Bit 0
Current Source . . . . . .
POWER NOT OK Circuit
Margining Test Fixture Connections
........ .
Test Point Signals
MM8-AB 16K Core Memory
MM8-AB 16K Core Memory Stack Layout
16K X 12 Stack and Sense Lines . . . . .
16K Core Memory Module Wiring Assembly
Decoding of X and Y Driver Current Sources Block Diagram
Decoding Relationships
Inhibit Operation For Bit 0
Field Selection Logic ..
Clear Time Control Logic
Strobe and Clear Timing
Strobe Control Logic . .
Inhibit Driver Load Gates
Inhibit Drivers for Bit 0
Current Source . . . . .
POWER NOT OK Circuit
DKC8-AA I/O Option Module Block Diagram
Serial Line Unit Block Diagram
Transmitter Block Diagram (UART)
UART Receiver Block Diagram
Timing Generator Block Diagram
SLU and Real Time Clock Device Select Logic
SLU Operation Decoder . . . . . . . . . . .
SLU Interrupt and Skip Logic . . . . . . . .
SLU Timing Generator and Baud Rate Select Logic
Format of I nput/Output Character
Receiver Timing Diagram
............ .
............... .
Transmitter Timing
EIA and 20 mA to TTL Converters and Reader Run Logic
TTL to EIA and 20 mA Converters
.......... .

xix

Page
5-73
5-78
5-78
5-80
5-81
5-82
5-82
5-83
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5-85
5-85
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5-111
6-3
6-6
6-7
6-8
6-8
6-10
6-11
6-12
6-13
6-15
6-17
6-18
6-19
6-20

IL.LUSTRATIONS (Cant)

Figure No.
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6·26
6-27
6-28
6-29
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6-41
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6-48
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6-50
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13

Title
Real Time Crystal Clock Block Diagram
........ .
Real Time Clock lOT Decoder and Interrupt and Skip Logic
Real Time Clock Frequency Dividers
..... .
General Purpose Parallel 1/0 Block Diagram . . . . .
Parallel 1/0 Device Select and Operation Decoder
General Purpose Parallel 1/0 Interrupt and Skip Logic
Parallel 1/0 Strobe Logic . . . . . . . .
Parallel 1/0 Output Register . . . . . .
Parallel 1/0 Input Buffer and Data Gates
KM8-A Block Diagram . . . . . . . . .
Memory Extension and Timeshare Block Diagram
Memory Extension and Timeshare Device Select Logic
Memory Extension/Time Share Operation Decoder
Input Multiplexer
......... .
I F Register and Control Logic
IF and DF Field Address Enable Logic
Data Field Register and Control Logic
Output Multiplexer
........ .
Time Share User Buffer Register and Control
Trap Detect Logic . . . . . . . . . . . . .
Interrupt Inhibit Logic . . . . . . . . . . .
Power Fail and Auto Restart Block Diagram
Bootstrap Loader Block Diagram
16 Bit Word ROM Format
Auto Restart Example
Bootstrap Example . . . . . . .
Auto Restart and Bootstrap Timing
Bootstrap Timing
........ .
Power Fail Auto Restart Device Select and Operation Decoder
Bootstrap and Auto Start Clock
Bootstrap and Auto Start Clock
CLK 1 and CLK2 Timing . . . .
Auto Restart Initialization Logic
Auto Restart and Bootstrap FlOM Address Counters
ROM Memory Control and MUX
........ .
Bootstrap and Auto Restart Operation Control Logic
Interconnections, PDP-8/A Semiconductor Basic Power Assembly
Power Board Circuits . . . . . .
G8016 Regulator Block Diagram
+5 Vdc Regulator Circuit
Regulator Board Edge Connector
+5 Vdc Regulator Circuit, Battery Operation
Battery Empty Circuit
Battery Charging Circuit
±15 Vdc Power Supply
POWE R OK L Circuit
AC LOW L Circuit
Voltage Monitor Waveforms
Battery Hold-up Time, Minimum Line Voltage vs % of Full-Rated Load

Page
6-20
6-22
6-22
6-23
6-27
6-28
6-29
6-30
6-31
6-32
6-34
6-39
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6-43
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7-4
7-5
7-6
7-7
7-8
7-9
. 7-10
7-10
7-11
7-12
7-13

ILLUSTRATIONS (Cont)
Figure No.
7-14
7-15
7-16
7-17
7-18
7-19
7-20
7-21
7-22
7-23
7-24
7-25
7-26
7-27
8-1
8-2
8-3
8-4
B-1

Title
Interconnections, 8A400/600/800 Basic Power Assembly
Connector Block Assembly Circuits
+5 Vdc Regulator Circuit
- 5 Vdc Regulator Circuit
+20 Vdc Regulator Circuit
±15 Vdc Circuit
POWE R OK H Circuit
AC LOW L Circuit
Timing, AC LOW L Circuit (60 Hz Operation)
Interconnections, 8A420/620/820 Basic Power Assembly
Interlock and Triac Control Circuit
Line Level Transformer/Peak Detector . . . . . .
Thermistor/Thermostat and Emergency Shutdown
POWER OK Circuit
....... .
G8016 Regulator Board Adjustments
G8018 Regulator Board Adjustments
H9194 Connector Block Assembly .
50 Hz and 60 Hz Connections on 10 Slot Machines
Omnibus Signal Locator

Page
7-14
7-15
7-16
7-17
7-17
7-18
7-18
7-19
7-20
7-21
7-23
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8-7
8-8
8-10
8-11
8-3

TABLES
Table No.
1-1
1-2
1-3
1-4
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
3-1
3-2

Title

Page

PDP-8/A Functional Characteristics
. . . . . . . .
....... .
PDP-8/A Computer Assemblies
PDP-8/A Limited Function Panel Controls and Indicators
PDP-8/A Programmer's Console Controls and Indicators
......... .
Summary of Installation Functions
PDP-8/A Computers, Dedicated Omnibus Slots
KK8-A (M8315) Central Processor Unit Switch Settings
MS8-A ReadIWrite Memory Switch Settings ..
MR8-A Read Only Memory Switch Settings
MM8-AA 8K Core Memory Jumper Installation
MM8-AB 16K Core Memory Jumper Installation
DKC8-AA I/O Option Board Switch Settings for C Etch Module
DKC8-AA Option Board Switch Settings for 0 Etch Module
Auto-Restart Select Switch Settings . . . . . . . . . . . .
Bootstrap Select Switch Settings (for ROMs Labeled 87 A2 and 88A2)
Bootstrap Select Switch Settings (for ROMs Labeled 158A2 and 159A2)
Bootstrap/Auto-Restart Switch Settings . . . . . . . . . . . . . . . . .
Bootstrap Switch Settings for ROMs (E82 and E87) Labeled 87A2 and 88A2
Bootstrap Switch Settings for ROMs (E82 and E87) Labeled 158A2 and 159A2
Basic PDP-8f A Troubleshooting
...... .
Slot Assignments for Modules on the Omnibus
Load Resistor and Drivers Summary . . . . .

1-3
1-5
1- 'J1
1-12
2-1
2-8
2-16
2-18
2-20
2-21
2-21
2-26
2-27
2-29
2-29
2-29
2-30
2-52
2-53
2-55
3-5
3-26

xxi

TABLES (Cont)

Table No.
3-3
3-4
3-5
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12

5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
6-1
6-2
6-3
6-4
6-5
6-6
6-7
7-1

Title
Omnibus Signal Drive Currents
lOTs For Sample Interface
Transfer Control Signals
Time State Stall Results
Primary Power Control .
Clock Timing Control Signals
Register Logic Bus Line Data
DEC7447 A Input/Output Signals
Function Button Control Signals
Display Control Signals
...;
ROM H Input/Output Signals
DATA ENA/DATA CMP Gating
PC, AC, MQ ClK Signal loading
ROM D Input/Output Signals
ROM C Input/Output Signals
ROM B Input/Output Signals
ROM E Input/Output Signals
ROM J Input/Output Signals
ROM A Input/Output Signals
M R8-A Specifications
MR8-A Signal Definitions
Switch Setting to Select Memory Field
MAO and MA 1 States for Memory Field Sizes
Switch Settings for States MAO and MA 1
Address Decoding
............. .
States of MA3 and MA2 to Select and Address Range
MS8-A Specifications
.......... .
MS8-A Signal Descriptions . . . . . . . . .
MS8-A ReadIWrite Memory Switch Settings
MR8-FB Signals
............. .
Core Selection Decoding Scheme "X" READ
Core Selection Y READ
Address Block Selection
Strobe Select Jumpers
V REF Jumpers
Voltage Test Points
Memory Data Errors Possible Causes
Core Selection Decoding Scheme "V" READ
Core Selection, V Read
......... .
Address Block Selection . . . . . . . . . .
COL and C1 l levels for Data Bus Transfers
D Etch SLU Baud Rate Select Chart
UART Signal Functions . . . . .
J4 Input Signal Pin Assignme~nts
J5 Output Signal Pin Assignments
ROM No.1 and ROM No.2 Listings (for ROMs Labeled 87 A2 and 88A2)
ROM No.1 and ROM No.2 Listings (for ROMs labeled 158A2 and 159A2)
PDP-8/A Family, Primary Power Assemblies . . . . . . . . . . . . . . . . . .

xxii

Page
3-29
· 3-32
3-34
· 4-16
· 4-19
· 4-24
· 4-26
· 4-32
· 4-34
· 4-38
.4-48
.4-50
· 4-52
· 4-58
· 4-60
· 4-61
4-70
4-72
4-76
5-5
5-6
5-11
5-12
5-12
5-13
5-14
5-23
5-25
5-39
5-46
5-74
5-80
5-82
5-84
5-90
• 5-92
5-93
5-101
5-103
5-104
6-11
6-13
6-16
6-25
6-26
6-58
6-63
7-1

TABLES (Cont)

Table No.
8-1
8-2
8-3
9-1
9-2

0-1
F-l

Title
Maintenance Equipment . . . . .
. ..... .
Preventive Maintenance (3 Months or 500 Hours)
PDP-8/A Line Sets, Fuses, and Transformer Assemblies
PDP-SI A Semiconductor Recommended Spare Parts
8A Recommended Spare Parts
RIM Loader Programs
Device Codes . . . . . . . . .

xxiii

Page
8-3
8-4
8-9
9-1
9-2

0-2
F-l

CHAPTER 1
INTRODUCTION AND DESCRIPTION

This manual provides the user with the necessary information to operate. interface to. maintain. and troubleshoot the
PDP-B/A Miniprocessor manufactured by Digital Equipment Corporation. Maynard. Massachusetts.
The PDP-B/A is the newest model of the PDP-B family consisting of the PDP-B/E. PDP-B/F. PDP-B/M and PDP-B/A. The
following illustrates how the PDP-B/A relates to its family members.
KIT-B/A
Modules

PDP-B/A
Small to Medium
Configu rations

PDP-B/M
Medium to Large
Configu rations

PDP-B/E
Large
Configurations

KIT-8/A is a module set version of the PDP-B/A configured to solve application problems that do not require a complete computer package with power. front panel. chassis. and cooling. Kits consist of processor, memory, option
boards, and mounting hardware including:
Central Processor Unit. Hex Module (MB315)
ReadlWrite Random Access Memory (RAM). Quad Module (MB311)
Read Only Memory (ROM). Quad Module (MB312)
Reprogrammable Read Only Memory (PROM). Quad Module (MB349)
DKC8-AA 1/0 Option Board with Serial 1/0, Parallel 1/0, Real-Time Crystal Clock, and Programmer's Panel Control.
Hex Module (M8316)
KMB-AA Extended Option Board with Memory Extension. Timeshare Control. Power FaiI/Auto-Restart. and Bootstrap
Loader, Hex Module (M8317)
M M8-AA(8K) and M M8-AB( 16K) Core Memory Modules

PDP-8/A - There are two basic types of computers in the PDP-B/A family. The first type is the PDP-B/A, which uses
semiconductor memories (MSB and MRB). The second type is represented by a series of computers. each of which uses
BK or 16K core memory (MMB); this series consists of the BA400. BA420. BA600. BA620. BABOO. and BAB20
computers. When a reference applies to both types of computers. the designation "PDP-B/A" is used. "PDP-B/A Semiconductor" refers to the semiconductor-memory computer. while "BA400." for example. refers to a specific core-memory machine and "BA" refers to the core-memory machines in general.

1-1

PDP-Sf A Semiconductor (Semiconductor ME.mory); designed to provide the security and data integrity of hard wired.
solid state logic and relay controllers. and in addition. provide the flexibility. power. and low cost of a computer. Space is
available to install 10 modules.
Semiconductor memory:
RAM 1 K. 2K. 4K (M8311)
ROM 1K. 2K. 4K (M8312)
PROM 1 K with 256 word RAM (M8349l

On Quad Modules

Battery backup:
System 1 to 7 minutes with provision for additional external batteries

SA (Core Memory); provides the lowest cost c:omputers in the 8K to 32K memory range for small computer systems
and mainframes. The PDP-8/A Central Processor Unit and two new core memories are used. Space is available for 12 or
20 modules.
Core memory:
8K (M M8-AA) and 16K (M M8-AS) Hex Modules (two slot spaces are reqUlired for each module).

Most of the options available for other members of the PDP-8 family are compatible with the PDP-8/A (see Paragraph
2.4 for a list of those that are not compatible). However. the DKC8-AA 1/0 Option module. the KM8-AA Extended Option
module. and several memory modules have beEm designed exclusively for the PDP-8/A.
Companion Documents include:
1.

Introduction to Programming - 1973

OSl8 Handbook

PDP-BIA Miniprocessor Handbook - 1975-1976

PDP-BIA Operators Handbook(DEC-8A-HOPHS-A-D)

PDP-BIA Engineering Drawings

PDP-8IE Maintenance Manual Volume II (OEC-8E-HMM2A-D-D) and III (DEC-8E-HMM3A-C-D).

All of these documents are available from Communications Services. Digital Equipment Corporation. Maynard. Massachusetts. 01754.
Table 1-1 lists the functional characteristics of the PDP-81A.

1-2

Table 1-1
PDP-8/A Functional Characteristics
Type

Single address, fixed word length, parallel transfer programmed data processor.

Word Length

12 bits.

Cycle Time

1.5 ps minimum (See memory speeds).

Memory Type

Cycle Time (ps)
Fetch Major State
All Other States

ROM Only
ROM/RAM (ROM Cycle)
ROM/RAM (RAM Cycle)
RAM Only
Core Memory

1.5
1.6

2.7

1.5
1.6
3.1

2.4

2.8

1.5

Memory Types

RAM
ROM
PROM
Core

Memory Expansion

Up to 32K.

Hardware Registers

5(AC, MQ, M B, PC, CPMA).

Auto Index

8 Auto Index registers per 4K memory field.

Addressing Capability

One instruction may address 256 locations directly or 4096 locations indirectly.

Instruction Set

6 memory reference instructions, 20 microprogrammable operate microinstructions,
and 8 input/output transfer instructions for the CPU and each of up to 60 I/O
devices.

Instruction Execution Time

Operate microinstruction
Directly addressed M R I
Indirectly addressed MRI

Input/Output Capability

Programmed data transfer, program interrupt system transfer, and 12 channels of
internal and/or external direct memory access (data break).

Auto Start Feature

The CPU contains an auto-start which can start the CPU at one of six switch selectable addresses upon application of power.

1 K, 2K, 4K
1 K, 2K, 4K
1K
8K,16K

*Cycle times reflect 1.5 J.lS memory.

1-3

1.5 ps*
3.0 ps*
4.5 ps*

Table 1-1 (Cont)
PDP-8!A Functional Characteristics
Options

Two new option boards which may be used separately or together.
1.

Front Panel Control
Serial Line Unit
Parallel I/O
Real Time Clock

Power Fail/Auto Restart
Memory Extension
Timeshare Control
Bootstrap Loader

Size (W X H X D)

19 X 10.5 X 10.5 in. (48 X 27 X 27 cm) - PDP-8/A Semiconductor, 8A400,
8A600,8A800.
19 X 10.44 X 23 in. (48 X 26.52 X 58.42 cm) - 8A420, 8A620, 8A820.

Weight

55 Ib (25 kg) - PDP-8/A Semiconductor. 8,01400. SA600. SASOO.
117 Ib (5:3 kg) - 8A420. SA620. SAS20.

Operating Environment

Ambient temperature
Relative humidity

Power Requirement

Approximately 150 W at 115 Vac, 50 or 60 Hz or 230 Vac, 50 or 60 Hz (voltage
and frequEmcy specified at time of order).

41° to 122° F (5° to 50° C)
10010 to 95% maximum, Wet bulb 90° F (32° C)

SYSTEM DESCRIPTION
1.1
The PDP-S/A is a general purpose miniprocessor. Its processor structure is single-address, fixed word length. parallel
transfer, using 12-bit. two's complement arithmetic. The cycle time of the processor is 1.5 J,lS. Standard features include
one level of indirect addressing and facilities for instruction skipping. program interrupts as a function of inputloutput
device conditions. and auto-restart features.
Five 12-bit registers are used to control computer operations, address memory, perform arithmetic or logical operations, and store data. An optional Programmer's Console provides switches and indicators that permit convenient
monitoring and modification of machine operation.
The flexible, high capacity inputloutput capabilities of the PDP-S/A allow it to operate a great variety of peripheral
devices. More than 60 inputloutput device options including high-speed paper-tape equipment. card readers, line
printers, disk and magnetic tape bulk storage devices, and a wide range of data acquisition, transmission, and display
peripherals are available from DIGITAL for the PDP-S/A.
Each PDP-S/A system is completely self-contained. A single source of 115 or 230 Vac power is required: internal power
supplies produce all the necessary operating voltages for the system. The basic PDP-S/A computer consists of a rackmountable chassis with a power supply and an Omnibus (backplane) into which Clre inserted the central processor. the
memory system. and the optional Programmer's Console and console terminal control. In the PDP-S/A, a bus .is defined
as a group of signal lines carrying related information. such as the 12 bits of an instruction or data word. The Omnibus
may be considered a wide bus containing several buses along with many other signal lines. Each PDP-SIA Omnibus has a
slot for the central processor unit. two slots reserved for the two option boards, plus several identical nondedicated
module slots. Each slot will accept a 144-pin quad or hex-sized module. (Some slots will accept a 1 SO-pin hex module.)
The Omnibus provides two-way signal paths between corresponding pins of the modules that are plugged into it.

1-4

A PDP-8/A computer pictured in Figure 1-1 shows both the Limited Function Panel (the panel on the bottom with three
switches and three indicators) and the Programmer's Console. The Programmer's Console can be located remotely from
the chassis; in such a case, or when the system does not include a console, a blank panel is attached.
PDP-8/A computers have three different mechanical assemblies that can be characterized by the number of available
Omnibus slots; that is, the PDP-8/A semiconductor computer assembly has a 10-slot Omnibus, while the 8A computer
assemblies have either a 12-slot or a 20-slot Omnibus. Table 1-2 relates the various PDP-81 A computers to some of the
basic system components. Note that the 8A400 can be considered the basic 8A computer, having a core memory, an 8A
CPU, and a 12-slot Omnibus. Thus, the 8A420 differs only in that it has a 20-slot Omnibus: the 8A600 differs in that it
has a PDP-8/E CPU; the 8A620 differs in that it has a PDP-8/E CPU and a 20-slot Omnibus: the 8A8DO differs in that it
has an FPP-8/A (not indicated in Table 1-2); and, the 8A820 differs in that it has an FPP-8/A and a 20-slot Omnibus.
Also, note that only 8A computers that use a PDP-8/E CPU can be expanded.

'-2

Table
PDP·8fA Computer Assembl ies
Computer

CPU

Memory*

Basic Power Assembly

PDP-8fA

KK8-A

Semiconductor

H763

H9192 (1 O-Slot)

8A400

KK8-A

Core

H9300

H9194 (12-Slot)

8A420

KK8-A

Core

BAS-C

H9195 (20-Slot)

SA 600

KKS-E

Core

H9300

H9194 (12-Slot)

Yes. As many as 20 slots
can be added.

SA620

KKS-E

Core

BAS-C

H9195 (20-Slot)

Yes. As many as 20 slots
can be added.

SASOO

KKS-A

Core

H9300

H9194 (12-Slot)

8A820

KKS-A

Core

BA8-C

H9195 (20-Slot)

Omnibus

Expandable

* A KMS-A (or KMS-E) Extended Memory Option module must be included in all the SA computers, since their basic memory capacity
is SK or 16K; the KMS is optional with the PDP-S!A Semiconductor computer, since the basic memory can be less than, greater than,
or equal to 4K.

Figure 1-2 represents, pictorially, the PDP-8/A Omnibus and the relationship of the fundamental system components
(i.e., CPU, memory, power supply, option, and peripheral interfaces). These components are described briefly in the
following paragraphs.

1-5

....

7288-5

Figure 1-1

PDP-8/A Miniprocessor

1-6

TELETYPE
OR
MODEM

PROGRAMMERS
CONSOLE
(KC8-AA)

KMB-E MEMORY
EXTENSION AND TIME

CUSTOMER
OPTION

SHARE
(M837)

KKB-E
CENTRAL PROCESSOR UNIT (M8300,
M831O), TIMING GENERATOR (M8330),
115VAC/230 VAC

BUS LOADS

(M831S1

OR
(1) SERIAL

KKB-A CENTRAL
PROCESSOR UNIT

POWER SUPPLY

'-I

POWER FAIL

PERIPHERAL
CONTROLLER
OR

(M8317)

LINE UNIT.

( 1)

MEMORY EXTENSION AND TIME
SHARE CONTROL.

INTERFACE

(2)

POWER FAIL AND AUTO
RESTART.

( SUPPLIED
BY CUSTOMER
OR DEC)

(3)

BOOTSTRAP LOADER

(2) REAL TIME CRYSTAL CLOCK.
(3) GENERAL PURPOSE PARALLEL I/O
(4) PROGRAMMERS FRONT PANEL
CONTROL.

(M83151

POWER

KM8-A EXTENDED OPTION BOARD

DKC8-AA I/O OPTION BOARD

(MB320)

CONTROL

DATA

TIMING

CONTROL

DATA

TIMING

CONTROL

DATA

TIMING

I CONTROL
ff
DATA

STATUS

*
*
*
*
~~--~~----~~--~----~~--~----~f-*~I-*~f-I--_*
:>
I f I
f
f
f
I
I

TIMING

DATA

CONTROL

TIMING

DATA

•

MS8-A RANDOM ACCESS
MEMORY (RAM)

MR8-A READ ONLY MEMORY
(ROM)

(M8311 I

(M83121

lK ,2K OR 4K

OMNIBUS

lK ,2K OR 4K

CONTROL

TIMING

DATA

•

CONTROL

TIMING

DATA

MR8-FBIK PROGRAMMABLE
READ ONLY MEMORY WITH
256 WORD RAM

MM-AA CORE MEMORY (8K)

(PROM)
(M8349)

MM8-AB CORE MEMORY !16K)
H219B AND G650

H219A AND G649

08-1107

Figure 1-2

PDP-8/A System Block Diagram

1.1.1 Central Processor Unit (CPU)
The KK8-A is contained on one hex module and has all the circuitry needed to manipulate data and generate control
signals; this circuitry includes the major registers and gating. the instruction decoder. the timing generator. and the autostart logic. The KK8-E is comprised of 4 hex modules. Two of these. M8300 and M831 O. constitute the CPU; another is
the Timing Generator (M8330). and the last is the Bus Loads (M8320).
1.1.2 KCS-AA Programmer's Console
The DKC8-AA 1/0 Option board contains the circuitry required to connect the PDP-8/A Programmer's Console to the
Omnibus. This console consists of an array of cCtntrols and indicators that facilitate c:omputer operation and maintenance.
Key pad switches provide convenient control of the system by allowing the operatOll' to start and stop program execution.
examine and modify the contents of memory. select various modes of operation. and load and execute short machine
language programs.
1.1.3 Limited Function Panel
The Limited Function Panel (Figure 1-3). which is often used without the Programmer's Console in dedicated applications. provides the necessary controls to apply power to the computer and start a program. A PANEL LOCK switch.
which is significant only when a Programmer's Console is present, allows the operator to disable most of the console
switches. This feature protects an operating program from being disturbed by accidental closure of a switch.

7118·5

Figure 1-3

PDP-8/A Limited Function Panel

1.1.4 Memory
The PDP-B/A memory can be configured from ROM. RAM. PROM. or core memory to meet the user's particular requirements. Memory sizes below 4K. (such as 1 K RAM. 1 K ROM. and 1 K PROM) are allowed. and the memory system can be expanded to 32K provided there! is adequate current available from the power supply. Each of the
various memory options available is discussed in the following paragraphs.
1.1.5 MMS-A Core Memory
The MMB-A is a 12-bit word, random access core memory system for the 8A computer. There are two versions available,
the M M8-AA (8192 12-bit words) and M M8-AI3 (16,384 12-bit words). Memory c:ycle time is 1.5 J..Ls. A one inch thick
hex module board contains the core stack. drive circuits. sense circuits. address decoders, etc. These circuits perform all
the operations required to transfer data into or out of core memory. The system plugs into one Omnibus slot but occupies
two spaces on the Omnibus because of the thickness of the module.
1.1.6 MS8-A Read/Write Semiconductor Memory (RAM)
The readlwrite semiconductor memory is a random access memory (RAM) mounted on a single quad board with a
capacity of 1 K. 2K. or 4K 12-bit words. Memory cycle time is 2.4 J..LS for instruction fetches and 2.B J..Ls for all other
states.

1-8

1.1.7 MR8-A Read Memory (ROM)
The MRB-A is a semiconductor read only memory mounted on a single quad board with a capacity of 1 K, 2K, or 4K
12-bit words. Memory cycle time with ROM memory only is 1.5 J.ls.
For those systems containing both ROM and RAM, a 13th bit in each memory location containing ROM and RAM
may be set to a logical 1 when the ROM is programmed to allow the program to address a word in readlwrite memory. When the 13th bit is on, the content of that memory location is interpreted as a memory address instead of an
operand and used to address the desired RAM memory location. This allows the programmer to use instructions that
require readlwrite operations (i.e., JMS, DCA, ISZ Instructions) when writing the ROM program.

1.1.8 MR8-FB Reprogrammable Read Only Memory (PROM)
The MRB-FB is an ultraviolet-erasable semiconductor memory mounted on a single quad board with a capacity of
1024 12-bit words of PROM and 256 words of readlwrite memory. PROM memory also has a 13th bit which can
be set to one, to address one of the 256 RAM locations. When the 13th bit is one, the eight least significant bits
read from a PROM location are used as an address to select one of the RAM locations. This allows the programmer
to use instructions that require readlwrite operations.
1.1.9 G8016 Power Supply Regulator Module
The GB016 Power Supply module provides + 5 Vdc and -15 Vdc and + 15 Vdc for the semiconductor versions of
the PDP-B/A Miniprocessor. The supply consists of a quad size board containing all the power generation and regulation circuitry necessary to provide these voltages. The power available is:

+5 Vdc
+15 Vdc
-15 Vdc

20A

0.75 A max
0.75 A max

}

sum

<1A

1.1.10 G8018 Power Supply Regulator Module
The G80 18 module supplies power for core memory systems for the BA. It differs from the semiconductor power supply
module in that more power is available:

-5 V
+5 V
+15 V

2A
25 A
2A

-15V
+20 V

2A
4 A

NOTE
The G8016 and G8018 Power Supply modules are not
interchangeable. The semiconductor supply (G8016) will
operate only with the PDP-8/A Semiconductor computer; the core memory supply (G8018) will operate only
with the 8A computers.
1.1.11
Interfacing
The PDP-8/A Omnibus is an internal inputloutput bus designed to eliminate random wiring and provide convenient
access to data and control signals. Interfacing is accomplished by inserting modules into non-dedicated slots.
The KA8-E positive 110 bus interface provides an extension to the bus system that facilitates interfacing PDP-B family positive bus equipment with the PDP-B/A. The positive 110 bus was designed for use with PDP-B/I and PDP-B/l
compatible peripherals, but it may be employed with almost any positive bus equipment.

1-9

PO P-81A systems provide three types of data transfer: program med data transfers. program interrupt transfers. and
direct memory access transfers. Programmed data transfer is the easiest to implement and is the most direct method
of handling data 110. Program interrupt transfers provide an extension of pro~Jrammed 110 capabilities by allowing
liD operations involving two or more devices to be performed concurrently. The' data break system uses direct memory access for applications involving extremely fast data transfer rates. All three 110 techniques are described in
Chapter 9 of the Miniprocessor Handbook. A detailed description of the Omnibus and its signals is contained in
Chapter 3 of this manual.

1.1.12 Option Modules
The PDP-8/A has two mUlti-option hex modules available. The M8316 module. which contains four separate PDP-8/A
options. and the M8317 module. which contains three options. Each of these modules and the options provided by them
are discussed in the following paragraphs and more fully described in Chapter 6.

1.1.13 DKCS-AA I/O Option Board (MS316)
The M8316 module contains a Serial Line Unit (SLU), a Real Time Crystal Clock. a General Purpose 12-Bit Parallel
liD. and the Programmer's Console control.
1.1.14 KMS-A Extended Option Board (MlS317)
The M8317 module contains the Memory E)(tension and Timeshare Control. Power Fail and Auto Restart. and the
Bootstrap Loader options.
1.1.15 Peripheral Options
Digital Equipment Corporation designs and manufactures many of the peripheral devices offered with the PDP-81 A.
All peripheral options purchased from Digital include the necessary cables. controllers. interfaces. etc. required for
system operation. Most options can be added to the system simply by inserting the modules into the Omnibus and
making cable connections between the modult3s and the peripherals.
1.2 CONSOLE OPERATION
There are two types of panels for the PDP-8/A - the Limited Function Panel and the Programmer's Console. The Limited
Function Panel is supplied with each PDP-8/A. The Programmer's Console is optional.
1.2.1
Limited Function Panel
The Limited Function Panel (Figure 1-3) has the necessary switches to apply power and to bootstrap the computer. and
indicators - POWER ON. RUN. and BATTERY CHARGING - to determine whether the computer is operating. Table 1-3
describes the function of the various switches and indicators on the Limited Function Panel.
1.2.2 Programmer's Console
The key pad switches and indicators on the PDP-8/A Programmer's Console (Figure 1-4 and Table 1-4) augment the
Limited Function Panel by allowing manual control of computer operation. and by presenting a convenient indication of
program conditions within the computer. PDP-8/A program execution can be started. stopped. monitored. or switched
among various modes of operation. The key pad switches also provide a means of selecting a memory location or major
register for examination and allow selective modification of readlwrite memory.
1.2.3 Entering Data From the Programmer's Console
Data is entered into registers from the programmer's console by first pressing the numbered key pad switches corresponding to the octal number to be entered, then the key pad switch correspondin~J to the register into which the data is
to be entered. For example. to load an octal number 7000 into the switch register. press 7. then press 0 three times. and
then press LSR. The data entered will be transferred to the switch register. To read the data that was entered in the
switch register. press SR and then DISP; the data is displayed in the 4 character octal readout.

1-10

Table 1-3
PDP-SfA Limited Function Panel
Controls and Indicators
Control or I nd icator

Function

ON/OFF

In the up position, this switch applies power to the computer and all controls and
indicators. Power is removed by moving the switch down.

PANEL LOCK

In the up position, this switch disables all key pad switches except Switch Register
(SR) and the read functions. The RUN and BATTERY CHARGING indicators are
not affected.

BOOT

When this switch is down, the Omnibus SW line is disabled (voltage level high). When
it is up, the SW line is asserted (low). This switch is used to start programmable read
only memory (PROM) and bootstrap loader programs. The key pad BOOT switch on
the Programmer's Console has the same function.

BATTERY CHARGING

This indicator is a LED. It lights when the battery backup supply is charging in the
PDP-8/A semiconductor computers; in the 8A420, 8A620, and 8A820 computers, it
lights when both G8018 regulators are operating properly. The indicator is present on
the 8A400, 8A600, and 8A800 computers, but is not used.

POWER

This indicator is a LED, lit when ac power is applied to the computer.

RUN

This indicator is a LED, lit when the RUN flip-flop is set.

THIS

BOOT

DISP

LSR

00000 1
1

o
o

RUN

0 STATE 0 MD

BUS

0 STATUS 0 SR
OAC

OMQ

STATE

LXA

CD CD CD CD 0 I'
CDCDCDCDO
00CDOO
THIS

BUS

STATUS

INIT

HLT/SS

RUN

08-1121

Figure 1-4

PDP-Sf A Programmer's Console

1.2.4 Examining Memory Locations
To determine the content of a location in memory, enter the memory field and press LXA. then enter the memory
address and press LA. Press MD and then DISP. Now press E THIS and the contents of this memory location will
be displayed in the 4-character octal readout. If you wish to examine two or more consecutive memory locations.
content of the next memory location will be displayed each time E N EXT is pressed.
1.2.5 Entering Data in Memory
To enter (deposit) data in a memory location. first enter the field into which data is to be deposited and press LXA.
then enter the address and press LA. Now enter the data and press D TH IS. If you wish to enter data into two or
more consecutive memory locations, press D NEXT after each entry is made.

1-11

Table 1-4
PDP-8/A Programmer's Console Controls and Indicators
Control or Indicator

Function

ADDRS

ADDRS is a 5 character octal readout that displays the content of
the 3-bit Extended Memory Address (EMA) register and the 12-bit
Memory Address (MA) register. The five characters (digits) show the
address of the memory location to be accessed next.

DISP

DISP is a 4 character octal readout that displays the content of the
register that has been selected for display. The Accumulator (AC),
Multiplier Quotient (MQ), Status Register, Switch Register (SR),
State, Memory Data (MD), or Data Bus (BUS) content may be read.
To select one of these for display, first press the appropriate key pad
switch (e.g., AC) and then press [) ISP. One of the LED indicators to
the left of the key pad will be lit, indicating which data is displayed
in the readout. 0 ISP also indicates the number button that is pressed;
i.e., if 3 (STATUS) is pushed, 3 appears in the right-most DISP position (if DISP is pushed after 3, the STATUS indicator Iights and the
o ISP readout ind icates the Status register contents). Thus, the operator can view the addresses being entered and the data being
deposited.

RUN

This indicator is a LED, lit when the RUN flip-flop is set.

Key Pad Switches
AC (O)

When key pad AC and then DISP are pressed, the content of the AC
at Time State 1 is displayed in the 4 character octal readout. The AC
indicator to the left of the key pad will also light.

MQ (1)

When key pad MQ and then 0 ISP are pressed, the content of the MQ
register is displayed in the 4 character octal readout. The MQ indicator to the left of the key pad will also light.

BUS (2)

When key pad BUS and then DISP are pressed, the content of the
DATA BUS (DATA 0-11) at Time State 1 is displayed in the 4 character octal readout. The BUS indicator to the left of the key pad will
also light.

STATUS (3)

When key pad STATUS and then DISP are pressed, the content of
the Status Register is displayed in the 4-bit octal readout (Figure
1-5). The STATUS ind icator to the left of the key pad wi II al so light.
The six most significant bits of the Status Register (bits 0-5) indicate either a set or cleared condition (logical one or logical zero).
Thus, the octal readout for these digits must be decoded to determine whether the bit is set or cleared.

First
Digit
Position

Illegal Characters
2,3,6, and 7

An octal 4 or 5 indicates that the link is set. An octal 1 or 5 indicates
that the Omnibus interrupt request line is asserted.

1-12

Table 1-4 (Cont)
PDP-8/A Programmer's Console Controls and Indicators
Control or Indicator
Key Pad Switches (Cont)
Second
Digit

Function

An octal 4,5,6, or 7 indicates that the INTERRUPT INHIBIT flipflop is set. The INTERRUPT INHIBIT flip-flop is located in the
memory extension and timeshare option.
An octal 2,3, 6, or 7 indicates that the interrupt system is enabled.
An octal 1,3, 5, or 7 indicates that the USER MODE line is
asserted. Signal USER MODE originates in the memory extension
and timeshare option on the Extended option board to disable execution of all OSR, LAS, HLT and lOT instructions when the computer is operating in Timeshare mode.

Third
Digit

Displays the content of the 3-bit instruction field register (I FO-2)
contained in the memory extension and timeshare option on the
extended option board.

Fourth
Digit

Displays the content of the 3-bit data field register (DFO-2) contained in the memory extension and timeshare option on the extended option board.

SR (4)

When key pad switch SR and then DISP are pressed, the content of
the SR (switch register) will be displayed in the 4 character octal
readout. The SR indicator to the left of the key pad will also light.

STATE (5)

When key pad switch STATE and then D ISP are pressed, the condition of the major states, 3 bits of the instruction register (I RO-2),
and 6 major Omnibus signals are displayed in the 4 character octal
readout (F igu re 1 -6). The ST AT E ind icator to the Ieft of the key
pad will also light. The octal readout must be decoded to determine
if the individual bits are in a set or cleared condition (a logical one or
a logical zero).

First
Digit
Position

Illegal Characters
3,5,6, and 7

A zero indicates that the processor is in the DMA state.
An octal 1 indicates that the processor is in the Execute major state.
An octal 2 indicates that the processor is in the Defer major state.
An octal 4 indicates that the processor is in the Fetch major state.

Second
Digit

Displays the content of the 3-bit Instruction Register (I RO-2).

1-13

Table 1-4 (Cont)
PDP-8/A Programmer's Console Controls and Indicators
Control or Indicator

Key Pad Switches (Cont)
Third
Digit

Function

An octal 4, 5, 6, or 7 indicates th,at the MD D IR line on the Omnibus
is asserted. Signal MD D I R is low and bit 6 is a logical one during
operations that read qata from memory. MD D I R is high and bit 6
is a logical 0 during operations that write data into memory.
An octal 2,3,6, or 7 indicates that BREAK DATA CONT line on the
Omnibus is asserted. BREAK DATA CONT is low and bit 7 is a
logical one during some direct memory access (DMA) operation.
An octal 1,3, 5, or 7 indicates that the SW line on the Omnibus is
asserted. This occurs only when BOOT on the Programmer's Console
or the Limited Function Panel is pressed.

Fourth
Digit

An octal 4, 5, 6, or 7 indicates ~hat the I/O PAUSE line on the
Omnibus is asserted. Signal I/O PAUSE L is generated during the
execution of an lOT instruction.
An octal 2,3,6, or 7 indicates that the BREAK IN PROG line on the
Omnibus is asserted (one or more devices are requesting a data
break). The highest priority device will begin a DMA operation at the
beginning of the next cycle.
An octal 1,3, 5, or 7 indicates that the BREAK CYCLE line on the
Omnibus is asserted (a DMA operation is taking place).

MD (6)

When MD and then DISP are pressed, the data on the 12-bit
MEMORY DATA bus (MDO-11) on the Omnibus are displayed in
the four character octal readout. The bus normally carries the content of the last memory location addressed by the 15-bit memory
address register.

Pressing LA (load address) loads the contents of the entry into the
Central Processor Memory Address (CPMA) register and enables the
FETCH major state for the next processor cycle.

LXA

Pressing LXA (Load Extended Address) loads the right-most digit of
the entry into the Data Field (DF) register and the next digit of the
entry into the instruction Field (I F) register.

INIT

Pressing INIT (Initialize) generates an INIT pulse that clears the AC,
the LINK, all I/O device flags and registers, and all interrupt system
flip-flops. This is equivalent to a programmed CAF instruction.

RUN

Pressing RUN generates a MEM START L signal, and sets the RUN
fl ip-flop. The program starts executing at the address that is in the
CPMA register.

1-14

Table 1-4 (Cont)
PDP-8/A Programmer's Console Controls and Indicators
Control or Indicator
Key Pad Switches (Cont)
LSR

Function

Pressing the LSR switch loads the entry into the Switch Register.
The Switch Register serves as a 12-bit temporary storage register for
data entries. The contents of the Switch Register can be read under
program control by the OSR and LAS instruction.

BOOT

Pressing BOOT twice causes the SW flip-flop to assert and then
negate the SW line on the Omnibus. The transition from assertion to
negation of the SW line causes a bootstrap operation to be performed. The signal from this BOOT switch is ORed with the signal
generated by BOOT on the Limited Function Panel so that either
switch can assert the SW signal on the Omnibus.

E THIS

Pressing E TH IS (Examine This) loads the contents of the memory
location addressed by the CPMA register into the Memory Buffer
(MB) register. The CPMA and PC are not incremented after this
operation. To observe the content of the MB, press MD, then DISP.

E NEXT

Pressing E NEXT (Examine Next) loads the content of the memory
location addressed by the CPMA into the Memory Buffer (MB) register and increments the CPMA and PC registers. This feature allows
the operator to step through a program and observe the operation
of one of the major registers, buses, etc., in the octal readout.

D THIS

Pressing D TH IS (Deposit This) loads the content of the entry into
the MB register and into memory at the address specified by the
CPMA register. The CPMA and PC are not incremented by this
operation.

D NEXT

Pressing D NEXT (Deposit Next) loads the content of the entry into
the MB register and into memory at the address specified by the
CPMA register. At the end of the operation, the PC and CPMA registers are incremented.

HLT/SS

Pressing HL T/SS (Halt/Single Step) while the machine is running will
cause it to stop. If the machine is stopped, pressing HL T/SS causes
the machine to execute one machine cycle.

1-15

FOURTH
DIGIT OF
OCTAL
DISPLAY

THIRD
DIGIT OF
OCTAL
DISPLAY

SECOND
DIGIT OF
OCTAL
DISPLAY

FIRST
DIGIT OF
OCTAL
DISPLAY

·EEJ
LINK

INT
ROST
NOT
USED

INTERRUPT
ENABLED

INTERRUPT
INHIBIT

IFO

USER
MODE

o!.

IF2
IF1

DFO

DF2
08-1148

Figure 1-5

FIRST
DIGIT OF
OCTAL
DISPLAY

DEFER

Status Information

SECOND
DIGIT OF
OCTAL
DISPLAY

IRO

THIRD
DIGIT OF
OCTAL
DISPLAY

IR2

BREAK DATA
CONT

FOURTH
DIGIT OF
OCTAL
DISPLAY

BREAK
CYCLE
08-1149

Fi~lure

1-6

State Information

1-16

CHAPTER 2
INSTALLATION AND ACCEPTANCE TEST

This chapter contains supplementary information and procedures for installing the PDP-81 A Computer System. Basic
installation and planning information. such as space requirements. environmental requirements. installation requirements. and system configuration data. are provided in Chapter 13 of the PDP-BIA Miniprocessor Handbook. Installation functions are summarized in Table 2-1.
All PDP-8/A computers and modules are tested thoroughly at DIGITAL's manufacturing facilities before they are shipped.
However. many switches and jumper wires can be arranged by the customer for specific purposes; furthermore. there is a
need both to verify the accuracy of system interconnections and site preparations. and to detect possible hidden damage
incurred during shipping. Consequently. a number of initial operating tests are also included in this chapter.

Table 2-1
Summary of Installation Functions
Identify space and power required for system configuration.
Survey proposed site
Prepare site in accordance with environmental space and power requirements.
Unpack equipment and check inventory checklist.
Install equipment.
Run acceptance test.
Enter results of acceptance test in log book.

2.1

SITE CONSIDERATIONS
Adequate site planning and preparation can simplify the installation process and result in an efficient. more reliable
PDP-8/A system installation. DEC Sales Engineers or Field Service Engineers are available for counseling and consultation with user personnel regarding the installation.

Site planning should include a list of the actual components to be used in the installation; this list should also include such items as storage cabinets. supplies. work tables. etc.
Primary planning considerations are:
1.

The availability and locations of adequate power

Protection against direct heat sources

Electrical noise radiation

2-1

Shock

The existence of fire protection devices.

If existing environmental conditions dictate, air conditioning andlor dehumidifying equipment (though not required for
the PDP-8/A) can become part of the site planning program.

2.1.1
Power Source
The power source should be free from conductive interference. In addition, all computer system supplies should be
connected to the same power source to avoid loading and source differentials that may affect computer operation.
2.1.2
I/O Cabling Requirements
The cabling for rack-mounted equipment can be routed into the chassis through an opening located in the rear of
the chassis. Subflooring is not necessary because casters elevate the cabinet high enough to provide sufficient cable
clearance. The cabling should be located where it cannot be damaged. This is especially important if the processor
and peripherals are not in close proximity.
2.1.3
Fire and Safety Precautions
The PDP-8/A Power Supply contains a thermal cut-out switch, circuit breaker, and fuses for protection against overheating and overloading. Both the cabinet and the power receptacle must be adequately grounded to ensure safe operation. A water pipe or steel beam provides an adequate ground. Refer to Chapter 13 of the PDP-BIA
Miniprocessor Handbook for grounding and power installation procedures.

WARNING
The frame of thEI computer must be grounded to protect personnel frclm dangerous electrical shock.
Grounding is achieved automatically when a 3··wire plug is used. However, a voltage reading from frame to ground
should be performed initially.
Electrical fires, although extremely unlikely, should always be extinguished by a Class 3 (C0 2 ) fire extinguisher.

2.2 UN·PACKING INSTRUCTIONS
All PDP-8/A computers are packaged in two containers, the inner container holding the computer, and a type of protective material. The steps in this section are sufficiently general to apply to any PDP-8/A. To unpack the PDP-8/A
computer, proceed as follows:
1.

Open the outer carton and remove the inner carton.

Open the inner carton.

Carefully remove the cardboard from the top and sides of the computer.

Carefully remove the computer from the box.

Inspect the computer for damage. If the computer is damaged, notify the carrier immediately.

Unpack any other boxes included in the shipment.

Check that all equipment. software, manuals, etc., are present as specified on the shipping list inside the
carton.

Save the cartons and packing material to use if the PDP-8/A is later repacked.

2-2

2.3 PACKING INSTRUCTIONS
Two kinds of packages are used for POP-8/A computers. The kind used and the applicable packing instructions depend
on the type of POP-8/A chassis assembly.
2.3.1
BAS-C Chassis Assembly
The 8A420, 8A620, and 8A820 computers use a BA8-C chassis assembly (20-slot Omnibus). Figure 2-1 illustrates the
packing procedure. First. the computer is placed in the inner container (9905417), the empty space is filled with plastic
protective material (AIR CAP, SO-120), and the container is sealed. The sealed inner container is surrounded with
protective foam material which is enclosed by the two telescope caps. Finally, the package is secured by two plastic
straps.
2.3.2

Other PDP-S/A Chassis Assemblies
CAUTION
The GS016 Regulator board assembly used on PO P-SI A
semiconductor computers contains a battery. This battery, while not of sufficient voltage to cause electrical
shock, represents a possible hazard if shorted. If repacking this type of computer, ensure that there is no loose
metal, such as solder, wire, or sheet metal parts inside
the cabinet.

The POP-8/A semiconductor computer and the 8A400, 8A600, and 8A800 computers use a chassis assembly that has a
10-slot or 12-slot Omnibus. To pack these computers proceed as follows:
1.

Place the computer in the smaller of the two shipping cartons with the back (side with power cord) of the
computer against the side of the carton.

Place the beveled die-cut sheet with foam protector (part number 9905675) in front of the computer (Figure
2-2). If the Limited Function Panel and a pop panel are on the computer, the beveled edge should be down
inside the carton. If the computer has a Programmer's Console, the beveled edge should be up so that the
cut-out in the cardboard fits the Programmer's Console.

Place the die-cut sheet with foam (part number 9905667) downward over the computer. The end with two
pieces of foam should be fitted around the fans and the other end should be positioned so that the cardboard
fits behind the cabinet mounting flange and the foam is against the side of the carton.

Close the flaps and seal the carton with tape.

Surround the sealed carton with protective foam material and enclose with telescope caps (Figure 2-3),

Strap in both directions using steel or plastic strapping.

2-3

FULL TELE

SCOPE CAP
(9905647)

IN CARTON
FILL VOIDS
SD-120
/ " WITH AIR CAP

PACKAGED

FOAM COR

RUGATED
ASS'Y

SIDE 'fg~~~641)

FULL

OPE CAP
TELES~9905647)

USE (2) PL

ASTIC STRAPS
DIRECTION

(1) I N EA~~NTAINER
TO HOLD
TOGETHER.

08-1789

Figure 2-1

8A420. 8A620. 8A820 Packaging

2-4

DIE-CUT SHEET
WITH FOAM SADDLE
(9905667)

DIE-CUT SHEETS
WITH FOAM BEZEL
PROTECTOR
(9905675)

REGULAR SLOTTED
CARTON (9905649)

08-1494

Figure 2-2

PDP-S/A Computer Packaging (Inner)

2-5

FULL TELESCOPE CAP
(9905662)

PACKAGED OPTION IN BOX
(9905649)

FOAM PAD
(9905663)
FOAM CORRUGATED
SIDE WALL ASS'Y
(9905661)

FULL TELESCOPE CAP
(9905662)

08-1790

Figure 2-3

PDP-8/A Computer Packaging (Outer)

2-6

2.4 PDP-8/A BASIC SYSTEM COMPONENTS
A PDP-81 A basic system comprises many components. The following three systems are the most common:
1.

A basic· PDP-8/A, a memory, and a Limited Function Panel.

A basic PDP-8/A, a memory, a Limited Function Panel. a KM8-A Extended Option board. a DKC8-AA 1/0
Option board, and a Programmer's Console (Paragraph 2.6 describes operating tests for this system).

A system as described in type 2 above, but accompanied by a Teletype@ and diagnostic *. programs (Paragraph 2.8 describes operating tests for this system).

As Table 1-2 indicated, a PDP-8/E CPU (KK8-E) can be used with the PDP-8/A system (8A600 and 8A620). In addition
to the CPU, most DIGITAL PDP-8/E options will operate with the PDP-8/A computers. The following will not:
1.
2.
3.
4.

KP8-E Power Fail/Auto-Restart option
DK8-EA Line Frequency Rear-Time Clock option
MM8-E 4K Core Memory
MM8-EJ 8K Core Memory

The KE8-E option (Extended Arithmetic Element) and the TD8-E DECtape Control will operate only with the 8A600 and
8A620 computers.
Modules can be inserted in almost any PDP-8/A Omnibus slot. There are, however, some restrictions and these are
summarized in Table 2-2. Notice that an M8320 module (Bus Loads) is inserted in slot 1 of the 8A600 and 8A620
computers. This module must be modified before it can be used in the 8A600 and 8A620 computers. If the modification
has been accomplished, R 55 (Figure 2-4) will have been removed; if R55 is present. carry out the procedure outlined in
DEC ECO M8320-00007.

08-1785

Figure 2-4 Part of M8320 Module Showing R55,
Which is Removed for 8A Operation

®Teletype is a registered trade mark of Teletype Corporation. Skokie. Illinois .
• A basic PDP-B/A is defined as a Central Processor Unit (CPU) and a chassis assembly (chassis. Omnibus. and power supply) .
• • Diagnostics are test programs written to find faults in the logic. The PDP-B/A programs are supplied on paper tape. Diagnostic programs are optional
and may be ordered from the Software Distribution Center. 146 Main Street. Maynard. Massachusetts 01754.

2-7

Table 2·2
PDP-8/A C()mputers, Dedicated Omnibus Slots

Omnibus Slot

SA600

SA600 & KES·E

SA620

SA620 & KES·E

1
2
3
4
5
6
7
S
9
10
11
12
13
14
15
16
17
1S
19
20

MS320
MS316
MS317

MS300
MS310
MS330

MS300
MS310
MS341
MS340
MS330

MS300
MS310
MS330

MS300
MS310
MS341
MS340
MS330

PDP·S/A Semiconductor,
SA400,SA420,SASOO,SAS20
MS315
MS316
MS317

Note 1: MS316 and MS317 are interchangeable in slots 2 and 3.
Note 2: Module numbers are related to options as follows:
M8315 - CPU (KKS-A)
MS316 - I/O Option Board (DKCS-AA)
M8317 - Extended Option Board (KMS-AA)
M8320 - Bus Loads
MS300 - CPU
M8310 MS330 - Timing Generator

.}
KKS-E

2.4.1 Chassis Descriptions
Three chassis types are available. The PDP-S/A Semiconductor computer chassis is illustrated in Figure 2-5 (the front
panels have been removed). Modules are insertl3d in the Omnibus from the front of the unit. Both quad- and hex-size
modules can be inserted; the fingers on connectors E and F of the hex size modules do not carry Omnibus signals (some
hex modules do not have connectors E and F). Figure 2-6 illustrates the dimensions of the same computer. as well as
indicating the ac line and fuse locations.

2-8

G8016
REGULATOR
ASSEMBLY

POWER
CONTROL
FUSE

MASTER-SLAVE
SWITCH

CABLE TO CONNECT
LIMITED FUNCTION
PANEL
7288-4

Figure 2-5

PDP-B/ A Semiconductor Chassis

2-9

SLOT 1

10.5 in
(26.7cm)

1
NOTE;
applied
It does not remove
ac power from the power transformer or fans.
4A( IIOV
OPERATION} OR 2A
(220V OPERATION)
SLOW BLOW FUSE

If you are servicing the power supply. you are
advised to:
1.
2.
3.

Turn PDP-B/A off.
Unplug the power cord.
Remove metal jewelry that could short
the battery. heat uP. and cause burns.

CAUTION
THE PDP-8/A MUST
BE PLUGGED INTO
UNSWITCHEO AC

08-1146

Figure 2-6

PDP-Sf A Semiconductor Computer
Chassis Dimensions

2-10

Figure 2-7 shows the chassis that is used with BA400. BA600. and BABOO computers. The dimensions are the same as
the PDP-B/ A Semiconductor chassis ; interior components are different. The GB01B regulator assembly has been removed to show the connector in which the assembly is inserted. The Omnibus connector blocks in the connector E position
are needed to accommodate the E connector of the core memory modules.
Figure 2 -B shows the chassis used with the BA420. BA620. and BAB20 computers . The example shown is an BA620.
containing the KKB-E CPU and Timing Generator. as well as the Bus Loads module. The H9195 Omnibus is mounted on
the Ce9ter Wall assembly (DEC Part Number 70- 12561) ; modules are inserted from the front of the unit. Two G801B
regulator assemblies are contained in'the rear of the chassis ; the regulator boards are inserted in PC board slots that are
mounted on the rear of the Center Wall assembly. Figure 2-9 is an outline drawing that gives the chassis dimensions and
illustrates the placement of the GB01B assembly.

CORE
MEMORY
SLOTS

REGULATOR
BOARD SLOT

CABLE TO CONNECT
LIMITED FUNCTION
PANEL

POWER
CONTROL
FUSE

73 6 7 -3

Figure 2-7
PDP-B/ A Chassis (H9300)
(Transformer Cover Removed)

2-11

7996-2

Figure 2-8 POP8/A Chassis
(8A240. 8A620. 8A820)

2-12

18.31 in. (46.50 em.)
(BElWE EN MOUNTING HOLE CENTER~

~~~'~

10.44 in.
26
ml
(

~
23"
In. (58.42

cm.)~

I®
Cl

08-1788

Figure 2-9

8A420/620/820 Chassis Dimensions

2-13

2.4.2 Expansion Techniques
Table 1-2 noted that the 8A600 and 8A620 computers could be expanded. Either a BA8-C or an H9300 can be added to
the basic chassis increasing the system capacity .accordingly. Figure 2-10 illustrates the basic chassis and the expansion
possibilities available for each type.

SA600

SA620

(KKS-E)

H9300

BAS-C

L_-,

BORB
08 -1786

Figure 2- 'I 0

8A600/8A620 Expansion

The basic chassis is connected to the expander chassis by BC08H cable assemblies. One cable connector is inserted into
either the top slot or the bottom slot of the basic chassis, depending on whether the expander chassis is located above or
below. The other connector is inserted into slot 1 or slot 20 of the expander chassis. If the 8A620 is being expanded with
an H9300 chassis assembly, the M8300, M83H), and M8330 modules must be removed from the basic chassis and
. placed in slots 10, 11, and 12, respectively, of the expander chassis. If the computer includes a KE8-E option, this too
must be removed from the basic chassis and inserted in the appropriate Omnibus slots of the expander. Refer to the
. PDP8 Configuration Guide for definitive guidelimts concerning expansion.
2.4.3 PDP-S/A Module Descriptions
The major units that constitute a PDP-8/A are described in the following paragraphs, along with the module switch
settings.
CAUTION
Switch settings may be accidentally changed unless
modules are removed and inserted carefully.
2.4.3.1
KKS-A Central Processor Unit (CPU) - The KK8-A, shown in Figure 2-11 is a multilayer hex module
(M8315) which resides in the top slot of the Omnibus. The KK8-A has an auto-start feature used to start the computer
automatically when power is turned on.
NOTE
If you are not using the CPU Auto-Start feature, turn
switch S1-7 ON and switches S1-1 through S1-6 and
S1-S OFF.
If you are using the CPU Auto-Start feature, set switches
in Table 2-3.

1IS shown

2-14

UNDERSIDE OF
BOARD

A
7246-1

Figure 2 - 11

KKS -A (MS315) CPU Module

Table 2-3
KKB-A (MB31 fi) Central Processor Unit Switch Settings
Switch

Function (When in the ON Position)

S1-1
S1-2
S1-3
S1-4
S1-5
S1-6
. S1-7
S1-S

Start in field 7 (OFF position specifies Field 0)
Start at address 4000
Start at address 2000
Start at address 1000
Start at address 0400
Start at address 0200
CPU Auto Start Disabled
OFF

Starting address 0000 may be selected by leaving switches 51-2 through 51-6 all OFF. Only one switch in the group 512 through 51-6 may be ON at any time. Failur43 to observe this precaution will result in a malfunction, even if the autostart feature is not used.

2.4.3.2

M58-A Read/Write Random AcctlsS Memory (RAM) - The M5S-A, shown in Figure 2-12, is a quad
module (M 8311), semiconductor, read/write Random Access Memory available in the following configurations:

Option

Memory Size

Module Number

MSS-AA
MSS-AB
MSS-AD

1K
2K
4K

MS311-YA
MS311-YB
MS311-YD

NOTE
If you are using a 4K RAM in Field 0, set switches 511, 2, 3, 4, 5, 6 and 10 ON and turn 51-7, 8, and 9
OFF.
5et switches as shown in Table 2-4 if other memory configurations are used.

2.4.3.3

MR8-A Read Only Random Access Memory (ROM) - The MRS-A, shown in Figure 2-13, is a quad module
(M8312). Read Only Random Access Memory . available in the following configurations:

Option

Memory Size

Module Number

MRS-AA
MRS-AB
MRS-AD

1K
2K
4K

MS312-YA
MS312-YB
MS312-YD

2-16

CONNECTOR TO MRB-A
IF 13TH BIT MS8-AlMR8-A
ROM/RAM CONFIGURATION

THESE CHIPS NOT
PRESENT ON M8311 -YA

Sl -l

Sl-10

THESE CHIPS NOT
PRESENT ON M8311 -YA
OR M8311 -YB
7015-B

Figure 2-12

MS8-A (M8311) ReadlWrite Random Access Memory

2 - 17

Table 2-4
MS8-A ReadlWrite Memory Switch Settings
Switch
S1-1, 2, and 3

Function/Position
Field Selection
S1-1
ON
OFF
ON
OFF
ON
OFF
ON
OFF

S1-4 and 5

S1-2
ON
ON
OFF
OFF
ON
ON
OFF
OFF

S1-3
ON
ON
ON
ON
OFF
OFF
OFF
OFF

S1-5
ON
OFF
ON
OFF

First Address in this RAM is

Field Selected
0
1

2
3
4
5

6
7

First Address
S1-4
ON
ON
OFF
OFF

S1-6

ON for 4K Memory M8311-YD

S1-7

OFF

S1-8

ON for 2K Memory M8311-YB

S1-9

ON for 1K Memory M8311-YA

S1-10

Test switch, normally ON

2-18

0000
2000
4000
6000

THESE THREE CONNECTORS ARE REMOVEO
TO PROGRAM THE ROM, BUT THEY MUST
BE IN PLACE FOR NORMAL OPERATION

CONNECTOR TO MS8-A
IF 13TH BIT MS8-A/MR8-A
ROM/RAM CONFIGURATION
IS USED

S1 -1

S4
S9-1

S9-8

7230-1

Figure 2-13

MR8-A (M8312) Read Only Memory (ROM)

2-19

The first address is always location 0000 of the selected memory field.

NOTE
If you are using a 4K RO M in Field 0 with no connections
to RAM, set swiitches as follows: 81-1 through 81-8; 861 through 86-8;; 87-1 through 87-8; 88-1 through 88-8;
89-1 through 89-8; 84-1, 2, 3, 6, 7, 8; and 86-3, 8; all
ON. 82-1 through 82-8; 84-4, 6; 86-1, 2; all 0 FF. If a
RAM is used with top connectors, change 84-7 to OFF.
Table 2-5 lists the switch settings for other memory configurations.

CAUTION
All switches must be OFF when the M8312 is being
programmed (j.e., while data is being loaded into
ROM).
Table 2-5
MRS-A Read Only Memory Switch Settings
Switch

Function/Position

51-1 to 51-8

52-1,8, and 5

Size Select 5witch 5ettings
52-1
ON
ON
OFF

S2·S
ON
ON
OFF

52-2 and 4

OFF

52-3, 6, and 7

Field 5elect 5witch Settings
Field

52-6
OFF
ON
OFF
ON
OFF
ON
OFF
ON

0
1
2
3
4
5
6
7

52·5
OFF
OFF
OFF

Memory Size

52-3
OFF
OFF
ON
ON
OFF
OFF
ON
ON

52-7
OFF
OFF
OFF
OFF
ON
ON
ON
ON

53-1 to 53-8

54-1,2,3,4,6, and 8
54-5
54-7

ON
OFF
OFF for ROM/RAM Combination; otherwise ON

55-1 to 55-8

56-1 and 56-2
56-3,4, 5, 6, 7, and 8

OFF
ON

57-1 to 57-8
58-1 to 58-8
59-1 to 59-8

ON
ON
ON

2-20

lK
2K
4K

2.4.3.4 MMS-AA SK Core Memory - The M MS-AA. shown in Figure 2-14. is a hex module (G649) with H219A
stack assembly that contains SK of core memory.

NOTE
If you are using core memory in fields 0 and 1, install
W1-3 and W1-2 and remove W2-4 and W3-4.
Install or remove jumpers as shown in Table 2-6 if other memory fields are in use.

Table 2-6
MMS·AA 8K Core Memory Jumper Installation
Fields Used

W1-3

W1-2

W2·4

W3-4

o and 1

IN
OUT
IN
OUT

IN
IN
OUT
OUT

OUT
IN
OUT
IN

OUT
OUT
IN
IN

2 and 3
4 and 5
6 and 7

2.4.3.6 MMS-AB 16K Core Memory - The M MS-AB. shown in Figure 2-15. is a hex module (G650) with H219E
stack assembly that contains 16K of core memory.

NOTE
If the M MS-AB is installed in fields 0 through 3, jumpers
W1-3 and W1-2 should be installed and W2-4 and W3-4
should be removed.
Install or remove jumpers as shown in Table 2·7 if other memory fields are used.

Table 2-7
MMS-AB 16K Core Memory Jumper Installation
Fields Used

W1·3

W1-2

W2·4

W3-4

o to 3

IN
OUT

IN
IN

OUT
IN

OUT
OUT

4 to 7

2-21

7388-1

Figure 2-14

M MS-AA Core Memory

2-22

7388-2

Figure 2-15

M M8-AB Core Memory

2-23

2.4.3.6 OKC8-AA I/O Option Board - There are two DKCS-AA hex modules (MS316) in existence; one is defined as
etch revision C (shown in Figure 2-16), the other as etch revision D (shown in Figure 2-17). The etch revision is identified
on side 2 of the PC board (side 1 is the compon'ant side). Lettering similar to the following appears near the lower right
corner (when viewing side 2).
Option Board 1
Side 2
MS316
5010900D
The letter D indicates the D etch revision. The information in this section is not totally applicable to each revision level;
differences that exist are indicated in the description.
The DKCS-AA combines four options:
1.

Serial Line Unit (SLU). 110 to 9600 (50 to 9600 for revision D) baud rate interface for Teletype. VT50. or
other compatible serial line unit.

Real-time Clock - Crystal controlled at 100 Hz.

General Purpose Parallel 1/0 - 12-bit 1/0 for user's device or another PDP-SIA.
NOTE
The General Purpose Parallel I/O on the 0 etch revision
of the M8316 module can be used as an interface for the
LA 180. Data to the LA 180 must be supplied in complemented form. The lOTs are different from the LA8
interface designed for the LA 180. A BC80-A cable, available from OIGITJl\L, must be used to connect the General
Purpose Parallel I/O (J 6) to the LA 180.

Console Logic - Logic to connect the KCS-AA Programmer's Console to the Omnibus.
NOTE
Revision C: For Teletype (A5R-33) operation without
real-time clock sClftware, set switches 51-4, 6, and 8 to
the ON position; :set switches 51-1, 2, 3, 6, and 7 to the
OFF position.
Revision 0: For Teletype (A5R-33) operation without
real-time clock software, set switches 51-1, 3, 4, 6, 8,
and 9 to the ON J)osition; set switches 51-2, 6, and 7 to
the OFF position (51-10 is a spare).

For other operation, set switches as shown in Tables 2-S and 2-9.

2-24

Jl PROGRAMMERS
CONSOLE

J2 PROGRAMMERS
CONSOLE (CONNECTS
TO BOTTOM CONNECTOR OF PROGRAMMERS
CONSOLE)

Sl -l

Sl-8

J5 PARALLEL {
I/O TRANSMIT

CJl

J4 PARALLEL{
I/O RECEIVE

J3 SERIAL {
LINE UNIT

Figure 2 - 16

DKC8-AA (M8316) 110 Option Board

7015-6

PARALLEL 1/0
TRANSMIT

J4
PARALLEL 1/0
RECEIVE

J3
SERIAL
LINE UNIT

J2 PROGRAMMER'S
CONSOLE (CONNECTS)
TO BOTTOM CONNECTOR OF
PROGRAMMER'S CONSOLE

REVISION LETTER
ON UNDERSIDE
OF BOARD (SIDE 2)

S1 ·1

SIDE 1

J1
PROGRAMMERS
CONSOLE

S1·10

Figure 2-17

D Etch Revision of DKC8-AA (M8316)
liD Option Board

Table 2·8
DKC8-AA I/O Option Board Switch Settings for C Etch Module
Switch
51 ·2,2 and 3

Function
Baud rate as shown below:
S1·1

S1 ·2

S1·3

Baud Rate

OFF
OFF
OFF
OFF
ON
ON
ON
ON

OFF
OFF
ON
ON
OFF
OFF
ON
ON

OFF
ON
OFF
ON
OFF
ON
OFF
ON

110
150
300
600
1200
2400
4800
9600

51·4

Clear Data Availabl e at Time 5tate 1 (normally ON)

51 -5

ON enables Real Time Clock

51 ·6

Test (normally ON, OFF for special testing)

51-7

ON for 1 stop bit, OFF for two stop bits

51·8

ON enables TTY filter in 20 mA CKT (u sed only for 100 baud)

2-26

8071 -1

Table 2-9
DKC8-AA Option Board Switch Settings for 0 Etch Module
Switch
S1-1, 2, 3, and 4

Function
Baud rate as shown below:
S1-4

S1-3

S1-2

S1-1

Baud Rate

ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
*OFF

ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
ON
ON
OFF
OFF
OFF
OFF

ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF

ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19.2K

S1-5

ON = Real Time Clock enabled
OF F = Real Time Clock disabled

S1-6

ON = Test Switch (always ON)

S1-7

ON = 1 Stop Bit in SLU character
OFF = 2 Stop Bits in SLU character

S1-8

ON = ASR/KSR 33 DR35 filter in (across SLU 20 rnA REC'V Leads
ON if Baud rate is 110 or below)
OF F = filter out

S1-9

ON = TS1 clears DATA AVAI L flip-flop in Parallel I/O Section
OFF = DATA AVAIL not cleared by TS1

*Serial Line will not run at this Baud rate. This setting is not to be used.

2-27

2.4.3.7
KMS-A Extended Option Board - The KM8-A. shown in Figure 2-18. is a hex module (M8317) combining
the following options:
1.

Power Fail/ Auto-Restart

Bootstrap Loaders - Provide commonly used I/ O loaders.

Memory Extension and Timeshare Control
NOTE
If you are using paper tape under control of the bootstrap
switches, no Auto-Restart, and timeshare enabled, set
the following switches ON: 51-1 through 51-4,51-8,
52-1, 52-5 through 52-7; set the following switches
OFF: 51-5 through 51-7, 52-2 through 52-4, and 52-8.

Other switch settings for the KM8-A are listed in Tables 2-10 through 2-13.
NOTE
There are two types of bootstrap ROM's used on the
KMS-A. ES2 and E87 have different labels on them for
the two different bootstrap ROM's. Modules that have
E82 and E87 (Figure 2-1S) labeled S7A2 and 88A2
should use Table 2-11 for switch settings. If ES2 and ES7
are labeled 158A2 and 159A2, use Table 2-12 for switch
settings.

•

11I1l1I1l HI

•

mil

rlJHlffJnHlJlJ
7299 -1

Figure 2-18

KM8-A (M8317) Extended Option Board

2 -28

Table 2·10
Auto·Restart Select Switch Settings
Restart Address

S2·2

S2·3

S2·4

0
200
2000
4200

OFF
OFF
ON
ON

OFF
ON
OFF
ON

OFF
OFF
OFF
OFF

Table 2·11
Bootstrap Select Switch Settings
(for ROMs Labeled 87A2 and 88A2)
Program

S2·5

S2·6

S2·7

S2·8

S1·1

S1·2

S1·3

Memory Address

*HI-LO RIM
*RK8-E
*TC08
*RF08/DF32D
*TA8-E

ON
ON
ON
OFF
OFF

ON
OFF
OFF
ON
ON

ON
ON
OFF
ON
ON

OFF
OFF
ON
ON
OFF

ON
ON
OFF
ON
ON

ON
OFF
ON
OFF
OFF

ON
ON
ON
OFF
OFF

7737
0024
7613
7750
4000

*May only be used with 4K of Read/Write Memory in field O.

Table 2·12
Bootstrap Select Switch Settings
(for ROMs Labeled 158A2 and 159A2)
Program

S2·5

S2·6

S2-7

S2-8

S1·1

S1·2

S1·3

Memory Ad dress

HI LO RIM
RK8-E
RX8-E
RF08/DF32D
TAS-E

ON
ON
ON
OFF
OFF

ON
OFF
OFF
ON
ON

ON
ON
OFF
OFF
OFF

OFF
OFF
ON
ON
OFF

ON
ON
OFF
OFF
OFF

ON
OFF
ON
ON
ON

'ON
ON
ON
OFF
OFF

7737
0024
0033
7750
4000

2-29

Table 2-13
Bootstrap/Auto-Restart Switch Settings
Start Switch
or Activating
Signal

S1-6

Switches
S1-7

S1-8

Bootstrap Enabled and Auto-Restart Disabled

BOOT Key

OFF

Bootstrap Enabled and Auto-Restart Enabled

BOOT Key
or AC OK*

Bootstrap Disabled and Auto-Restart Enabled

ACOK*

OFF

Bootstrap Enabled and Auto-Restart Disabled

ACOK*

OFF

Bootstrap Enabled and Auto-Restart Disabled

AC OK* or
BOOT Key

OFF

Feature

Bootstrap and Auto-Restart Disabled

S2-1
Timeshare Enabled

OFF

Timeshare Disabled

ON
S1-4

Bootstrap Activated in Run or Stopped State

OFF

Bootstrap Activated in Stopped State Only

Not Used

S1-5

*Starts if power voltage becomes adequate.

2.4.3.8 Semiconductor Memory Power Supply - The Semiconductor Memory Power Supply can supply 20 A at + 5
V. It will support only semiconductor memory (RAM and ROM). The GS016 regulator (Figure 2-1S) plugs into a dedicated backplane slot near the bottom of the chassis. The power supply has battery backup for power failures. The machine
will be totally supported for approximately 30-40 seconds after an ac line failure.
NOTE
All PDP-8/A Power Supply dc voltages are provided to
drive logic inside the basic chassis. DIGITAL is not
responsible for thel performance of the PDP-8IA if any dc
power is used outside the PDP-8/A chassis.

2-30

CAUTION
This area of the GB016 is normally covered with an
insulating shield. Removal of the shield exposes the
battery terminals. Should you accidentally short
these terminals with a ring or watchband, you
could receive a burn.

7016-11

Figure 2 - 19

Semiconductor Memory Regulator Board (G8016)

2 -31

NOTE
To enable control of the PDP-Sf A power from the ONOFF Switch. set the MASTER/SLAVE switch to the
MASTER (to the right) position. (The switch is identified
in Figure 2-6.)
In the 8A computers the MASTER/SLAVE swit.::h is mounted on the printed circuit board that includes the ON/OFF,
PANEL LOCK, and BOOT switches. This board is attached to the rear of the Limited Function Panel; remove the panel to
gain access to the MASTER/SLAVE switch. The switch is illustrated in Figure 2-20; if is shown in the MASTER position
(to the right when viewing the front of the switGh).

2.4.3.9

Core Memory Power Supply Regula'tor - The core memory power supply supplies the following voltages at
the currents specified:
+5 V @ 25 A
-5 V @ 2 A
+15V@2A
-15V@2A
+20 V @ 4 A

It will support core memory. The G8018 regulator (Figure 2-21) plugs into a dedicated backplane slot near the bottom of
the chassis. (The board slot is pictured in Figurel 2-7).

MASTE R/SLA VE
SWITCH

08-1787

Figure 2-20

8A MASTER/SLAVE Switch

2-32

+5V
CIRCUIT
BREAKER

ADJUSTMENT
TOOL MUST
ENTER HERE
FOR +5V
ADJUSTMENT

+5 V ADJUSTMENT

POWER OK LIGHT
(LIT WHEN ALL DC
VOLTAGES ARE
PRESENT)

- 5 V FUSE
(2.5 A)

Figure 2-21

POWER
FAIL
UP

POWER
FAIL

ADJUSTMENT
TOOL MUST
ENTER HERE
FOR +20 VOLT
ADJUSTMENT

+20 V FUSE
(4 A)

DOWN

G8018 Core Memory Regulator Board

2-33

+15 V FUSE - 15 V FUSE
(2.5 A)
(2.5 A)
7404-1

2.4.3 .10 Limited Function Panel (Figure 2-22) - The Limited Function Panel has three external switches and three
indicator lights (the MASTERISLAVE switch is mounted in the rear of the panel for SA computers) .

7288·3

Figure 2-22

Limited Function Panel

Lights
1.

POWER light indicates the PDP-S/ A is operating on ac power.

RUN light indicates the PDP-S/ A RUN flip-flop is set.

The BATTERY CHARGING light indicates either that the power supply battery is being charged (PDP-S/ A
semiconductor computer) or that both GS01S regulators are operating properly (SA420, SA620 , and SAS20
computers) . The light is present on the SA400. SA 600, and SASOO computers, but is not used.

2-34

Switches
1.

ON-OFF switch turns ac power on in the up position (this switch will not turn battery power on unless ac is
present). Turn power off before removing the power cord from the wall receptacle. Otherwise the PDP-8/A
will run on battery power for as long as the battery lasts.

On those systems having a Programmer's Console, the PANEL LOCK switch disables the following
switches: HLTISS, E NEXT, E THIS, 0 THIS, 0 NEXT. LA, LXA, INIT, BOOT, and RUN. The down position activates the Programmer's Console; the up position panel-locks the console.

The BOOT switch initiates the bootstrap function (if it is enabled) on the KM8-A Extended Option Board
(M8317). It is normally left in the down position. This BOOT switch is not affected by PANEL LOCK.

2.4.3.11

KC8-AA Programmer's Console (Figure 2-23) - The Programmer's Console has seven-segment LED displays of the Extended Memory Address (EMA). Memory Address (MAl. and the Status Register. The console can be
located up to 15 feet from the PDP-8/A. Two BC08R cables connect the console to the M8316 module (J 1 and J2).

o
o

RUN

0 STATE 0 MD

BUS

0 STATUS 0 SR
OAC

OMQ

THIS

BOOT

OISP

LSR

STATE

THIS

BUS STATUS

00000
00000
00000
MQ

LXA

INIT

HLT/SS

RUN

CD0~~~?j
08-1121

Figure 2-23

2.5

KC8-AA Programmer's Console

INSTALLING THE PDP-8/A AND TURNING POWER ON FOR THE FIRST TIME

2.5.1
Environmental and Power Requirements
Recommended operating conditions for the PDP-8/A are an ambient temperature of 5° to 50° C (41- 122 ° F) and
a noncondensing relative humidity of 10-95%. Voltage requirements are 90-132 Vac single phase (using approximately 3.2 A). or 180-264 Vac single phase (using approximately 1.6 A). Line frequency may be 49-51 Hz or
59-61 Hz, depending on the power transformer used in the power supply. Check the label at the rear of the computer to determine the correct voltage and frequency.
WARNING
Be sure that the ac outlet provides a non-current-carrying ground.
2.5.2 Turning on the Computer for the First Time
After unpacking the computer, allow at least 30 minutes for the machine to stabilize to ambient temperature before
applying power. This time should be increased to one hour or longer when the difference between storage or shipping temperature and the operating ambient temperature exceeds 30° F (17° C).

2-35

Install the equipment using the following procl~dure:
1.

Check switch settings on all modules. (See instructions in Paragraph 2.4.3).

Ensure that the regulator circuit breaker is ON. (The breaker is pictured in Figure 2-6.)

Turn OFF the ON/OFF switch on the Limited Function Panel (Figure 2-22).

Ensure that all ac power is received from the same branch circuit if the system has more than one power
cord.

Plug in the power cord. If a power control is used. plug the power cord into the receptacle marked UNSWITCH ED AC.
WARNING
Do not tOlJch the computer after plugging it
in until proper grounding has been checked.

Before touching the computer. chetck frame to ground voltage to ensure that less than 10 Vac is present.

Without touching any metal part of the PDP-8/A. turn the power ON/OFF switch ON.

Repeat step 6. In case of difficulty. have an electrician check the socket into which the computer has been
connected (electrical connections aire illustrated in Figure 2-24). If no difficulty is encountered, the computer
frame is properly grounded and there is no danger in touching it.

Power is now applied to the PDP-8lA. The fans should be running and the BATTERY CHARGING light should
light momentarily or stay on. (The light is not used in the H9300 chassis assembly.) If none of these occur.
check the MASTER/SLAVE switch (Paragraph 2.4.3.8). Turn the power OFF before checking the MASTER/SLAVE switch. This switch should be in the MASTER (to the right) position. Then turn the power ON. If
the condition still exists. refer to the basic maintenance section in Paragraph 2.10.

10.

Turn the PDP-8/A power switch OFF and the Teletype LlNE/OFF/ LOCAL switch to the OFF position.

11.

Connect the Teletype signal cable to the short cable (DEC Part No. BC05M -1 F, plugged into J 3 of the
M8316) in the PDP-8/A. The cable connectors are keyed for proper mating.

12.

Plug the Teletype into the same ae outlet as the PDP-8/A.

13.

Turn power ON/OFF switch on tho PDP-8/A to ON.

14.

Turn the Teletype LINE/OFF/LOCAL switch to LINE. Only the hum of the running motor of the Teletype
and the PDP-B/A fans should be heard.

2.6 TESTING PDP-8/A WITHOUT PAPEB TAPE DIAGNOSTICS
The procedures in this section are used to test the PDP-8/ A computer from the Programmer's Console. No paper
tape diagnostic programs are required for these tests.

2-36

~VAC ELECTRICAL

I
I

-- --

CONNECTION
THESE 1 - CONNECTIONS I

EARTH GROUND - NO lOAD
CURRENTFOR SAFETY PURPOSES

FRAME
GREEN WIRE OF
PDP- 81A POWER
CORD CONNECTS
TO THIS PIN

TO HIGH-QUALITY
GROUND. #4 AWG

I
---1-----------

8lACK

~~..,__------------~---L-~---'~ ~-=--=-_-_-_-_-_- ~ =-= ~ ~O~D

WAll
RECEPTACLES
(FEMALE)

L _________

RE::

l=- __________

~O/24;-VAC EL~IC~ - - -

I
I
I
I
I

S~~V~~~ I

ENTRANCE I

I
I

PRE~~E~ I

WHITE

I
I

--1

CONNECTION
THESE 1 - CONNECTIONS I
PREMADE
ONLY I

EARTH GROUND - NO lOAD
CURRENT FOR SAFETY PURPOSES

FRAME
GREEN WIRE 0'.
PDP- 81A POWER
CORD CONNECTS
TO THIS PIN

S~~V~~~ I

ENTRANCE I

L ___ _

TO HIGH-QUALITY
GROUND. #4 AWG

---~--------------

:
:

WHITE

L __ _
LOAD

L
---'

* A VOLTAGE BETWEEN THIS WIRE AND FRAME INDICATES THAT THE RECEPTACLE IS ON A LINE WHICH
IS A CONSIDERABLE DISTANCE FROM THE SERVICE ENTRANCE (THE WATT-HOUR METER AND FUSE BOX)
AND IS CARRYING SIGNIFICANT CURRENT. THIS VOLTAGE SHOULD NOT EXCEED 5% OF THE NOMINAL LINE
VOLTAGE.

Figure 2-24

PDP-S/A Electrical Connections

2.6.1
Programmer's Console
The Programmer's Console is shown in Figure 2-23 and is fully described in the PDP-BIA Miniprocessor Handbook and in
Paragraph 1.2. Its use in testing the PDP-S/A is described in detail in the paragraphs that follow.
2.6.2 Central Processor Test Routines
When no MAINDECs are available, small routines may be keyed into memory and run to check PDP-8/A operation.
These tests will not completely check out a PDP-8/A, but will find the most common failures. All routines start at
address 0200. If any failures occur. carefully examine each instruction of the routine. If the instructions are correct.
switch power off and check all of the module switch settings (all memory contents are lost when power is switched
off and the routines must be reloaded). If the routine is not entered properly, re-enter the routine and try to run
it again.
These routines are also useful when MAINDEC programs cannot be loaded because of a hardware problem.

2-37

2.6.3 Entering Test Routines from the Programmer's Console
The following procedure should be used to run Routine 1. the first POP-SI A test:
1.

Press. in order. MD. OISP - this will let you see what you deposit.

Press. in order. 0 0 0 0 LXA - sellect memory field 0

Press. in order. 0 2 0 0 LA - start loading instructions at address 200.

Press. in order. 7 0 0 1 0 NEXT - deposit an instruction.

Press. in order. 2 3 0 0 0 NEXT - deposit an instruction.

Press. in order. 5 2 0 1 0 NEXT - deposit an instruction.

Press. in order. 5 2 0 0 0 NEXT - deposit an instruction.

Press. in order. 0 2 0 0 LA - now get ready to start at location 200.

Press. in order. AC. OISP - Do this to see the accumulator (AC).

10.

Press. in order. INIT and RUN - start the program.

All other routines should be entered into memory using this procedure.
NOTE
If you make a mistake while you are entering a number, and you h,Bve not pressed 0 N EXT, LA etc., you
can correct the entry by re-entering the entire number.
The number appearing in the OISP indicator is the entry that the P~P-Sf A will use.

2.6.4

Central Processor Test Routines
The following routines should be used to check the CPU:

Routine 1
This program will increment the AC slowly so that the user can see that it is working. The internal numbering system of the POP-S/A does not use Sand 9.
0200
0201
0202
0203

7001
2300
5201
5200

Iincrement the AC by 1 - start here.
Iincrement a location and skip if it is zero.
IJump bac:k 1.
IStart pro~~ram over again.

Routine 2
This routine should print a pattern of all printable characters. Omit this routine if your POP-SI A is not equipped with
a Teletype, or similar terminal.
NOTE
Ensure that thl3 Teletype is set to LI N E for routines 2
and 3.

2-3S

The following line will print out while this routine is running. Characters mayor may not be printed after the letter Z.
depending on the column width of the terminal. These extra characters should be disregarded. Disregard the first line
printed.

#$%&'0 * + ,-.10123456789:; < = > ?@ABCDEFGHIJKLM NO PQRSTUVWXYZ (Random Characters)
0200
0201
0202
0203
0204

7001
6046
6041
5202
5200

Iincrement the AC by 1 - start here.
ITransmit.
I Am I done transmitting?
INo I am not done transmitting.
IYes I am done. Jump back and start over.

Routine 3
This routine will print what is typed on the terminal (echo characters). Type several lines of sentences. making sure
the terminal prints out what you type. Omit this step if your PDP-8/A is not equipped with a terminal.
0200
0201
0202
0203
0204
0205
0206

6031
5200
6036
6046
6041
5204
5200

IHas a key been pressed?
INo. go back and wait.
I A Key was hit. Read it.
ITransmit the character to the printer.
I Am I done printing?
INo. Go back one.
IYes I am done. Let's go back to wait for another key.

Routine 4
The following program checks some of the operate instructions. The program should halt at location 00216 (ADDRS
should read 00217) with the AC cleared. (AC=OOOO)
0200
0201
0203
0204
0205
0206
0207
0210
0211
0212
0213
0214
0215
0216

7240
7001
7640
7402
7120
7010
7510
7410
7402
7001
7002
1202
7420
7402
7402

IClear the AC, then complement the AC.
Iincrement the AC by 0202.
ISkip if AC = 0, then clear the AC.
IError halt. Computer should not halt here.
ISet the link to 1.
IRotate the AC right one. The AC should then equal 4000.
ISkip if the AC bit 0=0.
ISkip unconditionally.
IHalt. Computer should not halt here.
Iincrement the AC by one.
IByte swap. AC should equal 0140.
IAdd 7640 to 0140.
ISkip if link equals 1.
IHait on error.
IGood halt if AC = 0000.

Routine 5
The following routine tests the ISZ instruction. The program should halt at location 00207 (ADDRS should read
00210) with AC cleared (AC= 0000). To read the AC, press AC and then the DISP button.
0200
0201
0202
0203
0204
0205
0206
0207

7500
3300
7001
2300
5202
7440
7402
7402

IClear the AC and link.
IStore 0 in location 300.
Iindex the AC.
Iindex location 300.
IJump back and do again.
IDone check if AC = 0000.
IError (AC and location 300 should be zero).
IGood halt.
2-39

Routine 6
This routine tests the JMS instruction. This routine should halt with ADDRS
(AC= 0000). To read the AC, press AC and then the DISP button.
0200
0201
0202
0203
0204
0205
0206
0207
0210
0211
0212
0213
0214
0215

7300
3300
3204
4204
0000
1204
7041
1215
7440
7402
2300
5202
7402
0204

to 0021 5 with the AC cleared

IClear the AC and link.
IZero Pass counter.
IZero entry.
IJM S to subroutine.
IReturn address written here.

IGet return address.
IComplement and index the AC.
I Add to known good return address.
ISkip on 0 ~\C.
IError halt.
Iincrement Pass counter.
IDo again.
IGood halt.
IConstant.

Routine 7
This routine tests the Jump instructions. The program should halt at location 00214 (ADDRS should read 00215).
Run this test twice.
0200
0201
0201
0203
0204
0205
0206
0207
0210
0211
0212
0213
0214

5210
7402
5206
7402
52'12
7402
5204
7402
5202
7402
2300
5200
7402

IJump 210.
IError halt.
IJump 206.
IError halt.
IJump 212.
I Error ha It.
IJump 204.
IError halt.
IJump 202.
IError halt.
ILoop to do this program 4096 times.
IStart program over again.
IGood halt after 4096 passes.

2.7
LOADING THE RIM AND BINARY LO,~DERS
Programs in binary format may be used in machines with 4K or more of Read/Write Memory. The RIM loader must
be used to load the Binary Loader. The Binary loader is then used to load a program in binary format.
The RIM and Binary Loaders reside in the highest 1 K of a 4K memory. Machines with less than 4K of memory require the RIM loader to be loaded at addresses in the lowest 1 K of memory. Use of the Binary Loader on machines
with less than 4K of ReadIWrite memory is not recommended because of the length of the Binary Loader routine.
Each test procedure will tell you where to load the RI M loader.

2.7.1

Loading the RIM Loader
The RI M Loader is a 17 -instruction program needed to load the Binary Loader and other RIM formatted tapes. There are
two methods of loading the RIM loader: Manually loading each instruction through the Programmer's Console keys
(described in the next few paragraphs). and usin~J the bootstrap option, if there is 4K or more of Read/Write memory and
the KMS-A Extended Option Board (MS317) is in the computer. If you use the second method, turn to Paragraph 2.7.3.

2-40

Enter RIM Loader through the Programmer's Console keys as follows:
Press keys from left to right as ordered in the following steps (1 through 22).
1.
2.
3.

MD
0000
XXXX

DISP
LXA
LA

4.
5.
6.
7.
8.
9.
10.
1 1.
12.
13.
14.
15.
16.
17.
118.
19.
,20.
21.
22.

6032
6031
5357
6036
7106
7006
7510
5357
7006
6031
5367
6034
7420
3776
3376
5356
0000
0000
XXXX

D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
LA

/Enables memory data to the readout display
/Sets instruction and Data field to 0
/ADDRS should read the OXXXX value, see the
bottom of this table for the value of XXXx.
/DISP should read 6032
/DISP should read 6031
/DISP should read 5357
/DISP should read 6036
/DISP should read 7106
/DISP should read 7006
/DISP should read 7510
/DISP should read 5357
/DISP should read 7006
/DISP should read 6031
/DISP should read 5367
/DISP should read 6034
/DISP should read 7420
/DISP should read 3776
/DISP should read 3376
/DISP should read 5356
/DISP should read 0000
/DISP should read 0000
/ADDRS should be OXXXX*

• XXXX If you have a 4K RAM, enter 7756. If you have less than 4K of RAM, enter 0156 for loading all tests except version A of
the MS8-A test (Enter 1756 for this case only).

2.7.2
Checking the RIM loader
After completing the RI M loader procedure, the program may be checked by repeating the first three steps and pressing E N EXT. Each time E N EXT is pressed, the next four digits of the program should appear in the DISP lights.
When you are sure RIM loader is in memory correctly, proceed to the Binary Loader procedure, or load and run RIM
format MAINDECs (Paragraph 2.8) if you have less than 4K of read/write memory in your system.
2.7.3

loading the Binary loader
NOTE
Do not use the Binary loader procedure if the memory
size is less than 4K.

Place the tape labeled Binary Loader (DEC-08-LBAA-PM) in the Teletype reader, with the
START/STOP/FREE lever set to FREE. Position the tape so that the printed arrow on the tape points toward
you, and the single row of data holes at the beginning of the tape is over the read head (Figure 2-25).

Ensure that the LINE/OFF/LOCAL switch of the Teletype is set to LINE, and the papertape reader's
START/STOP/FREE lever is set to the START position (Figure 2-26).

If the KM8-AA Extended Option Board (M8317) is not available, the RIM loader must be loaded at this
time using the RIM loading procedure (Paragraph 2.7.1).

If the RIM loader was keyed in manually, press (in order) 7756, LA, INIT, and RUN. The RUN light
should be on. The Teletype reader should be reading tape.

2-41

If the KM8-AA Extended Option Board (M8317) was set up for Hi-Lo RIM . ensure that the BOOT switch
on the Limited Function Console is down ; then press the BOOT key on the Programmer's Console twice.
The RUN light should go on and the Teletype reader should read tape .

If the tape fails to read in or stops before the end of tape. reload the RIM loader using the RIM Loader
procedure (Paragraph 2 .7 .1).

After the tape is read to the trailing single row of data holes. press the H LTlSS key. The reader should
stop reading tape . The Binary Loader should now be in memory.

0 0 0 0 0 0 0 0 0 0 0 0 0 ,0 0 0 0

~ oTcOPO
0000000

00 00 0
0000
0000000000000000 000000000000000 0

00
0

000

0000000000000000000000000000 00000000000000000

~------------------------~yr--------------------------~/~

LEADER : SINGLE ROW OF DATA HOLES (HOLE " 8")

PROGRAM DATA
08-0 843

Figure 2-25

Paper Tape Leader

PAPER ROLL UNWINDS
COUNTER-CLOCKWISE

J
TAPE
UNWINDS
CLOCKWISE

PUNCH
MECHANISM
PUNCH
OFF/ON

PAPER TAPE
READER

LINE/OFF/LOCAL
2428

Figure 2-26

LT33 Teletype Controls

2-42

2.7.4

Loading Binary Formatted Paper Tapes
1.

Press (in order) 7777. LA. MD. DISP and E THIS. The DISP register should read 5301. If it does not.
check the RIM Loader and reload the Binary Loader.

If the cont~nt of address 07777 was 5301. press 7777. LA. and LSR.

Place the binary formatted paper tape in the reader. with the single row of data holes over the read
head.

Place the Teletype LINE/OFF/LOCAL switch to LINE.

Place the reader switch in the START position.

Press (in order) INIT. then RUN. The reader should start reading tape.

The Programmer's Console RUN light should go out when the first bit of trailer (row of single data holes
at the end of tape) is over the read head. The reader should automatically stop. Move the reader lever to
STOP or FREE.

Press (in order) AC. then DISP. The DISP register should read 0000. If the DISP register does not equal
0000. the tape must be reloaded.

Now the program is ready to run.

2.8 TESTING THE PDP-8/A USING MAIN DEC DIAGNOSTIC PROGRAMS
MAINDECs are test programs designed to test the KKS-A or KKS-E CPU. the DKCS-AA I/O Option Board. the KMS-A
Extended Option Board. and read/write memory. The minimum PDP-S/A system that can be tested with MAINDEC
programs consists of a box, an Omnibus, a power supply and the following options:
Option

Description

KKS-E
or
KKS-A

CPU

DKCS-AA
KCS-AA
LT33-D

I/O Option Board
Programmer's Console
ASR-33 Teletype

with at least 1 K of ReadlWrite memory starting in location 0000 of field O.
The PDP-S/A read/write memory can be any of the following:
Memory
MSS-AA
MSS-AB
MSS-AD
MMS-AA
MMS-AB

Size, Type
1 K Semiconductor
2K Semiconductor
4K Semiconductor
SK Core
16K Core

If your machine has a MRS Read-Only Memory, you should consult your local Field Service representative before
attempting to run MAINDECs.

2-43

2.8.1

Central Processor Unit (CPU) Test
The Central Processor Test is a good overall test of the PDP-Sf A. It is recommended that this test be the only one
run unless specific problems are encountered.
The CPU Test checks the CPU for proper oper.ation. The program first checks the HALT instruction (that's why the
program stops at step 7); then tests the remaining instructions.
Two variations of the CPU test exist. One of these variations applies if the PDP-Sf A has 4K or more of Read/Write
memory; the other. if it has less than 4K. In the steps below. the steps which are memory-size-dependent are enclosed in boxes. You should enter the information or perform the operation indicated for your memory configuration
(refer to sticker on the back of the PDP-S/A).
1.

Load RIM Loader (see Paragraph 2.7.1). starting with one of the following addresses:

>or=4K: 7756
<4K: 0156

>or=4K: Load Bin Loader (See Paragraph 2.7.3)
< 4K: Skip this step

Place" PDP-Sf A CPU Test" in paper-tape reader. Ensure that the header/trailer code (hole "S") is over
the read head. Tape number is:

>or=4K: MAINDEC-OS-DJKKA-PB
< 4K: MAINDEC-OS-DJKKA-PM 1.

Run the appropriate loader.

>or=4K: Press 0000 and LX-A.
Press 7777 and LSR.
Press 7777 and LA.
< 4K: Press 0156 and LA.

Press INIT.
Press RUN.
Tape will read into memory.

>or= K: Tape will stop automatically. Press AC. DISP. DISP indicators should equal 0000.
< 4K: Tape must be stopped when trailer is reached. Press H LTISS.

Set up location 0021 in the program as follows:
Press 0021 then LA.
Press 4000 then D THIS.

2-44

Start Program as follows:
Press 0000 then LSR.
Press 0200 then LA.
Press INIT.
Press RUN.

Program will stop (RUN Ight will go off) with ADDRS = 00222. Press STATUS and then DISP.
DISP indicators should equal 4000.
Press AC, then DISP.
DISP indicators should equal 7777.

Press RUN. Allow program to run for 10 minutes. If no errors are detected the program will not halt.

While program is still running, press any key on the Teletype.
Program should halt.

2.9 ADDITIONAL DIAGNOSTIC TESTS
These programs should be run to isolate specific problems. It is not recommended that they be run as a periodic confidence check.
2.9.1

Memory Test
The MSS-A MOS Memory Test checks all locations in memory field
for proper operation. It relocates itself in memory and tests all of memory not occupied by the program. This test assumes that the CPU is functioning correctly.

Load RIM Loader (see Paragraph 2.7.1). starting with address:

>or=4K: 7756
<4K: 0156*
• Use 1756 if the tape is the A revision (MAINDEC-08-DJMSA-A-PM). The revision letter is the single letter just before the final
PM.

Place tape labeled "1-4K MSS-A MOS Memory Test" (MAl N DEC-OS-DMSA-A-PM) in the paper-tape
reader.

Run RIM Loader using one of the following;

>or=4K: Press 0000, and LXA.
Press 7756, and LA.
<4K: Press 0156 *, and LA.
.• Use 1756 if tape is the A revision (MAINDEC-08-DJMSA-A-PM).

Press INIT, then RUN.
Tape will read into memory.
Tape must be stopped when trailer is reached (press H LTISS).

2-45

Set up location 0021:
Press 0021 and LA.
Press 4000 and 0 THIS.

Set up location 0023:
Press 0023 and LA.
Do one of the following:

If 4K: Press 7777. and [) THIS
If 2K: Press 3777. and [) THIS
If 1 K: Press 1777. and [) THIS.

Start program as follows:
Press 0000. then LSR.
Press 0200. then LA.
Press INIT. then RUN.

Allow program to run for 5 minutes. There should be no halts. At the end of 5 minutes. while program is
still running:
Press 0400. then LSR.
Program will halt.

2.9.2
DKC8-AA Test
The DKC8-AA I/O Option Test program tests for proper operation of the Serial I/O. Parallel I/O. and Real Time clock
contained on the M8316 module. In addition to the paper tape(s). the following equipment is needed:
W987 Quad Module Extender
Three Termi-point Jumpers (Available in a package of 100. type 915. Any length may be used. although 8 in.
is probably most useful).
BC08R cable (any stock length)
These items are supplied as a portion of the PDP-8/A maintenance kit. and may also be ordered separately using
the numbers just mentioned. This test requires placing the DKC8-AA on a module extender; hence a table to support the Programmer's Console or cables to extend the panel cables should be available.
1.

Turn PDP-8/A power OFF. Without altering the M8316 switch settings. remove the M8316 from the
PDP-8/A. Be sure to provide enough slack in the Teletype cable and the parallel I/O cables to allow easy
removal of the module. Plug the W987 Quad Extender into the slot previously occupied by the M8316.
and plug the M8316 into the extender. Remove the parallel I/O cables (if used) from J4 and J 5. marking
the cables so they can be properly reinstalled at the end of this test. Plug one end of the BC08R cable
into J4. Plug the other end of the BCOaR cable into J5. There should be one fold and no twists in the
cable. Do not remove the Teletype cable or the cables to the Programmer's Console. Turn PDP-8/A
power ON.

2-46

Using the same procedure as for steps 1, 2,' 3, and 4 of the CPU test. (Paragraph 2.S.1) load the tape into
memory.

CAUTION
Do not use the loading procedure for memory test.
The tape to be loaded is:

>or=4K: MAINDEC-OS-DJDKA-PB 1
<4K: MAINDEC-DJDKA-PM 1

Without turning power off. remove the Teletype cable from J3 and install three Termi-Point jumpers as
follows:
J3-E to J 3-H
J3-K to J3-KK
J3-S to J3-AA
Change S 1-5 on the MS316 from OFF to ON. Make no other switch changes at this time.

Set up location 0021 as follows:
Press 0021 then LA.
Deposit one of the following numbers by entering it via the numeric keys. then press D TH IS:

Enter
6000
6001
6003
6007
6017

Memory Size
1K
2K
4K
SK
16K

Start program as follows:
Press 0000. LSR then LXA.
Press 0200. INIT then RUN.

Allow program to run for 5 minutes. There should be no halts while program is still running:
Press 0400 then LSR.
Program will halt.
Then:
>or= 4K: Skip to Step 9
< 4K: Continue on to Step 7.

2-47

(Omit if >or= 4K) Return S 1-5 to off. Remove the Termi-point jumpers from J3 and re-install the Teletype cable. (Be sure it is installed so the printed A on the cable connector is at the saine end as the
printed A on J3.) Load:
MAINDEC-08-DJDKA-PM2
and then repeat steps 3. 4. and 5 of this test. Allow program to run for 5 minutes (no halts). Then:
Press 0400 then LSR.
Program will halt.

(Omit if >or= 4K). Return S 1-5 to off. Remove the Termi-point jumpers from J3 and re-install the Teletype cable as described in step 7.
Load:
MAINDEC-08-DJDKA-PM3
and then repeat steps 3. 4. and 5. Allow program to run for 5 minutes (no halts). Then:
Press 0400 then LSR.
Program will halt.

Do this step regardless of memory size.
For a C etch revision: Set S 1-3 and S 1-7 ON; leave S 1-5 ON.
For a D etch revision: Set S 1-1. 2. 4. 5. and 7 ON; set S 1-3 OFF.
Continue for either revision.
Remove the Termi-point jumpers from J3.
Now connect:
J3-F to J3-J
J3-E to J 3-M
Start program. as described in step 5. and allow program to run for 5 minutes (no halts). Then:
Press 0400 then LSR.
Program will halt.
Then do one of the following:

>or= 4K: Skip to step 11

< 4K: Do step 10

2-48

10.

Skip this step if > or = 4K.)
For a C etch revision: Set S 1-3, 5, and 7 OFF.
For a D etch revision: Set S1-1. 3, and 4 ON; set S1-2 and 7 OFF.
Continue for either revision.
Remove Termi-point jumpers from J3. Replace Teletype cable as described under step 7. Load
MAINDEC-OS-DJDKA-PM4
and repeat steps 3, 4, and 5. Allow program to run for 5 minutes. Then:
Press 0400 then LSR.
Program will halt.

11.

Do this step regardless of memory size.
For a C etch revision: Set S 1-3 and S 1-7 ON; set S 1-S OFF.
For a D etch revision: Set S1-1. 2, 4, and 7 ON; set S1-3 and S1-S OFF.
Continue for either revision.

Press 0000 then LS R.
Then do one of the following:

>or = 4K: Press 4000 then LA.
<4K: Press 1200 then LA.

Press INIT and then RUN.
The program should run for 30 seconds ± 0.5 seconds from the time the RUN button is pressed; then
halt.
Now:

>or = 4K: Press 4023 or LA.
<4K: Press 1223 then LA.

Press INIT and then RUN.
Program will halt.
Turn on S1-3 and S1-7.
Turn off S1-S.
Press 0001 and LSR.
Press RUN ..

WARNING
Do not press I N IT.
The program should run for 30 seconds ± 0.5 seconds, and then halt.

2-49

12.

Do this step regardless of memory size.
Turn PDP-8/A power OFF.
For a C etch revision: Set S 1-3. 5. and 7 OFF; set S 1-8 ON.
For a 0 etch revision: Set S1-1. 3.4.8. and 9 ON; set S1-2. 5. and 7 OFF.
Continue for either revision. Remove all Termi-point jumpers. Replace Teletype cable on J3. being sure the
pin letters on the cable and board c(mnector match. Remove the BC08R cable from J4 and J5. Re-install
parallel 1/0 cables (if used). Remove the W987 Quad Extender from the PDP-81A. and re-install the M316.
Be careful not to alter switch settinns accidently while inserting the M8316.

2.9.3

KM8-A Extended Option Board Test
NOTE
Make sure you have the correct diagnostic program.
MAIN DEC-08-DJ KMA-Ais for M8317 modules having ROMs E82 and E87 labeled 87A2 and 88A2; MAINDEC-08-DJ KMA-13is for ROMs labeled 158A2 and
159A2.

The KM8-A Extended Option Board Test program tests the circuitry contained on the M8317 module. As in the previous test. the module under test is placed on a W987 Quad Module Extender to allow the operator to alter switch
settings without turning off power to the PDP-81A. Again. it is advisable to have a table to support the Programmer's Console.
The following series of tests are designed for operation on a PDP-8/A with 4K or more of memory. since two of the
three options on this module require at least 4K of memory. Also available for this option are test programs which
will run in 1 K of memory. Consult your local DIGITAL sales office if more information on the 1 K programs is
needed.
1.

Turn OFF power to the PDP-8/A. and place the M8317 on the W987 Quad Extender. The M8317 must
be plugged into slot 2 or 3 of the Omnibus.

Write on paper the position of all switches on the M8317. and then place all these switches in the OFF
position. Unplug the controllers for any bootstrappable options (such as the PC8-E. TA8-E. RK8-E controllers and the KA8-E Positive 1/0 adapter). but leave the Teletype connected.

Turn on power: and load RIM at address 7756 using the keys. Do not attempt to use the bootstrap - it
was disabled at step 2. Load the Binary Loader (see Paragraphs 2.7.1 and 2.7.3).

Read in the tape (MAINDEC-08-DJI<MA-PB) using the Binary Loader. (See Paragraph 2.7.4).

Set up location 0021 as follows:
Press 0021 then LA.

2-50

Deposit one of the following numbers (depending on memory size) by entering it via the numeric keys
and then pressing D THIS.

Memory Size
4K
SK
12K
16K
32K

Enter
7003
7007
7013
7017
7037

Start program:
Press 0000, LXA. then LSR.
Press 0200, INIT, then RUN
6.

Allow program to run for 10 minutes. Then:
Press 0400 and LSR.
Program will halt.

Turn S2-1 on. Then:
Press 4255 then LA.
Press 0000, LSR. INIT, and then RUN.
Program will halt.

Set up for bootstrap test:
Press 4465, LA, INIT, then RUN.
Program will halt.

Test the paper tape bootstrap as follows:
Turn 0 N S2-5, S2-6, S2-7, S 1-1. S 1-2, S 1-3, S 1-6, S 1-7, and S 1-S. Make sure Teletype reader lever is in
either the STOP or FREE position.
Press:
BOOT
BOOT
HLT/SS
0000, then LSR
4401, LA. INIT, and then RUN
Program will halt with ADDRS = 04462 if paper tape bootstrap is correct.

2-51

NOTE
There is no point in checking a bootstrap unless your
PDP-SI A is equipped with the option, (e.g., unless your
PDP-S/A is equip'ped with an RKS-E, do not bother to
test the RKS-E bc,otstrap).
10.

Check any other bootstraps as follows:
Repeat step 8.
5et switches according to Table 2-14 or 2-15, depending on the bootstrap you are testing.
Leave 51-6,51-7, and 51-8 ON.
Press:
BOOT
BOOT
HLT/55

NOTE
There are two different types of ROMs for the MS317
module. Those mCldules that have ROMs labeled S7A2
and SSA2 should use Table 2-14 for bootstrap se!ect
switch settings (slBe Figure 2-1S for switch and ROM
locations). Those modules that have ROMs labeled
16SA2 and 169AZ should use Table 2-16 for switch
settings.
Enter the value of 5R from Tables 2-14 and 2-15, then press in order;
L5R. 4400, LA. INIT, then RUN
Program will halt with ADDR5 = 04462 if Bootstrap is correct.

Table 2-14
Bootstrap Switch Settings for ROMs (E82 and E87)
Labeled 87 A2 and 88A2
Bootstrap

S2-5

S2-6

S2-7

S2-8

S1-1

S1-2

S1-3

HI La RIM
RKS-E
TeOS
RFOS/DF32D
TAS-E

ON
ON
ON
OFF
OFF

ON
OFF
OFF
ON
ON

ON
ON
OFF
ON
ON

OFF
OFF
ON
ON
OFF

ON
ON
OFF
ON
ON

ON
OFF
ON
OFF
OFF

ON
ON
ON
OFF
OFF

0000
0004
0001
0002
0003

2-52

Table 2-15
Bootstrap Switch Settings for ROMs (E82 and E87)
Labeled 158A2 and 159A2
Bootstrap
HI LO RIM
RKS-E
RXS-E
RFOS/DF32D
TA8-E

11.

S2-5

S2-6

S2-7

S2-8

S1-1

S1-2

S1-3

ON
ON
ON
OFF
OFF

ON
OFF
OFF
ON
ON

ON
ON
OFF
OFF
OFF

OFF
OFF
ON
ON
OFF

ON
ON
OFF
OFF
OFF

ON
OFF
ON
ON
ON

ON
ON
ON
OFF
OFF

0000
0004
0003
0001
0002

Make sure the BATIERY CHARGING light on the Limited Function panel is off. If this light is on, leave
PDP-8/A power on but do not attempt the following test until the BATTERY CHARGING light is off.

NOTE
Unless you have experienced a recent
power failure while the PDP-8/ A was running or have unplugged the PDP-8/ A power
cord without first turning the ON/OFF
switch to OFF, it is very unlikely that the
BATTERY CHARGING light will be on by
the time you get to this test.
12.

Turn ON 51-1, 3, 6, 7, and 8: 52-3, 5, and 7. Turn OFF 51-2, 4, and 5: 52-1, 2, 4, 6 and 8.

13.

Enter the following:
Press 4600 then LA.
Press 0000, L5R. INIT, then RUN.
PDP-8/A will halt.

14.

Press 0002, L5R. INIT, and then RUN.

15.

Without operating the panel ONIOFF switch, unplug the power cord of the PDP-8/A from the wall receptacle. ADDR5 should display 04764, and the RUN lights on the Limited Function Panel and the Programmer's Console should be off.
Re-insert the power cord. The program should begin running again. Do not leave power cord unplugged
any longer than necessary, since the batteries will discharge.

16.

Repeat step 15 four times.

17.

Turn OFF power. Return the M8317 switches to the original positions, wrtten down at step 2. Remove
the W987 Quad Extender, and replace the M8317 in the PDP-8/A box. Be careful not to disturb the
switch settings on this module or any adjacent modules while so doing. Replace the Programmer's
Console.

2-53

2.9.4 Testing Extended Memories
A good test of extended memories. the CPU and the memory extension control may be made by running the 1 K to
32K Random Memory Reference Instruction E:<erciser Test. This test may also be used in systems with as little as
1 K of memory.
1.

Load RIM loader. as described in Paragraph 2.7.1 starting with one of the following addresses:
>or = 4K: 7756
<4K: 0156

Place MAINDEC-08-DJEXA-PM in paper-tape reader. enter same address as given for step 1. and press:
LA.
1000. then LXA.
INIT. then RUN.
Press H LTISS when trailer is over read station.

Set up location 0021 by pressing:
0021 and LA

Memory Size
1K
2K
4K
8K
12K
16K
32K

Enter
4000
4001
4003
4007
4013
4017
4037

Enter number corresponding to memory size from chart. then press D TH IS.
4.

Enter the following:
Press 0000 then LSR.
Press 0200. INIT. and then RUN.

Run two minutes for each 1 K of mE:lmory (4K: 8 minutes. 8K: 16 minutes. etc.).

2-54

2.10 BASIC PDP·8/A MAINTENANCE
Table 2·16 lists some basic PDp·8/A problem symptoms and their possible causes.

Table 2·16
Basic PDP·S/A Troubleshooting
Symptom

Possible Cause/Solution

No lights, fans not running

Fuse Blown. Power Switch is OFF. AC power not connected. MASTER/
SLAVE switch in wrong position.

Fans running, but no lights

Circuit breaker on the regulator assembly is OFF.

RUN light does not come on after
BOOT switch is activated

Check switches on KMS·A Extended Option Board (MS317). Switch
settings are in Tables 2·10 through 2·13.

BATTERY CHARGING light stays
on

The battery requires a minimum of 15 hours of charging after a complete
discharge. The light normally flashes on momentarily after power on if
battery has been fully charged.

RUN light comes on when power
switch is turned on

This function is switch selectable on KKS-A CPU Module (MS315) and
KMS·AA Extended Option Module (MS317).

RUN light stays on after AC power
is unplugged

Do not unplug AC power unless PDP-S/A power is shut off. The PDP-8/A
behaves as if there has been a power failure, and the battery supply takes
over.

Peripheral will not BOOT with
BOOT switch

BOOT switch on Limited Function Panel in wrong position, it should be
down. PANEL LOCK should be down. Check switches on the Extended
Option Board (M8317). Check baud rate switches on DKC8-AA 1/0 Option
Board (M8316). Switch settings are in Paragraph 2.4.3.6.

Machine remains powered even
with ON/OFF switch set to OFF

Fuse in power control relay circuit is blown. Set ON/OFF switch to OFF,
then unplug the power cord before attempting to change this fuse.

Light on the GS01S Regulator
board is out (SA computers).

Turn off power, remove regulator board, check +5 V circuit breaker
and -15 V, ±15 V, and +20 V fuses.

2-55

CHAPTER 3
INTERFACING TO THE OMNIBUS

This chapter provides the necessary interfacing information for users to understand operation of the Omnibus or to
build a special interface for the PDP-S/A. It deals primarily with hardware design considerations required to build an
interface for the Omnibus. Programming information is contained in two other PDP-S documents. Introduction to Programming and Programming Languages. A user who plans to write a program for hislher interface should be familiar
with these documents. However. DIGITAL has many device handlers and software packages the user may be able to
use as written. or modified. to operate devices with the PDP-S/A.
Signals are transferred from module to module on a device called the Omnibus. All PDP-S modules and options that are
compatible with the PDP-S/A plug into the Omnibus. The Omnibus is an etched board with rows of connectors soldered
to it. The pin assignment is the same on all connectors. The Omnibus is comprised of 96 signals and provides the means
to transfer these signals from module to module.
There are many advantages to the Omnibus approach. Because all connectors on the Omnibus carry the same signals. a module can be placed anywhere on the bus with the following exceptions:

3.1

The CPU must be plugged into either the top slot (slot 1) or the bottom 3 slots (refer to Table 2-2).

The PDP-S/A option boards must be plugged into slots 2 and 3 (either module in either slot). MOS memory cannot be plugged into slots 2 or 3.

All hex modules should be plugged into the top slots followed by quad modules in the lower slots.

OMNIBUS PHYSICAL DESCRIPTION

The Omnibus (Figure 3-1) consists of standard DEC HS63 connector blocks mounted on an etched circuit board and
wave soldered. The connectors are arranged to accept hex and quad type modules (Figure 3-2). The Omnibus has 10
slots if it is a semiconductor machine and 12 or 20 slots if it is a core memory machine. Core memory machines use an
extra connector (E) to supply +20 V and -5 V to the MMS-AA and MMS-AB core memory modules.
All pins on the Omnibus are parallel-wired (e.g., pin CM2 of slot 1 is wired to pin CM2 of slot 2) to form a parallel bus
comprised of 96 Omnibus signals. The parallel bus is used to connect the central processor. memory. peripherals. and
options. All modules must plug into the Omnibus.
The Omnibus is mounted on the PDP-S/A chassis (Figure 3-3 shows an SA chassis). Modules are inserted and removed
from the. front of the chassis. For connections to the outside world, connectors on the sides of the modules connect to a
shielded coaxial cable or flat ribbon cable. An opening in the chassis allows cables to be routed to the user's device.

3-1

CONNECTOR

CORE MEMORY
(USED ON
8A COMPUTERS)

SLOT 12

POWER
SUPPLY
REGULATOR
SLOT

7344-1

Figure 3-1

PDP-8/A Omnibus (H9194)

HEX MODULE

QUAD MODULE

08-12!18

Figure 3-2

3.2

PDP-8/A Hex and Quad Modules

BUS SPECIFICATIONS

Logic Levels
Logical 1
Logical 0

Maximum Voltage: +0.4 V
Minimum Voltage: -0.5 V
Maximum Voltage:
5.0 V
Minimum Voltage: +3.0 V

3.3 METHODS OF DATA TRANSFER
There are three methods of accomplishing input/output data transfers: Programmed I/O Transfers. Interrupt Transfers. and Data Break Transfers.
3.3.1
Programmed I/O Transfer
The simplest method of accomplishing an input/output transfer is to employ the Programmed I/O Transfer. This
method relies upon the processor to check the Status Flag and service the flag with a subroutine.
3.3.2 Interrupt Facility
A more efficient method of input/output transfers is to employ the Interrupt System. This method uses the Programmed I/O Transfer. but the device signals the processor when a transfer is requied by grounding an INTERRUPT
REQUEST line. The processor responds at the end of the current instruction by entering a service routine.
3.3.3 Data Break Transfer
A still more efficient method of transfer is to employ the Data Break System. Whenever the data break device decides that it is time to transfer. it generates MS. IR DIS to force the processor into a Direct Memory Access state
and CPMA DIS to disable the CPMA register. This leaves the data break device free to supply its own address and
to manipulate the Major Registers Control logic so that it can input and output data. The processor responds to a

3-3

CORE
MEMORY
SLOTS

REGULATOR
BOARD SLOT

POWER
CONTROL
FUSE

CABLE TO CONNECT
LIMITED FUNCTION
PANEL
7367-3

Figure 3 -3

SA Chassis (H9300)

break at the end of the current cycle . In general. data break requires more hardware than Programmed 1/ 0 . Addi tional logic is necessary to handle addressing , etc., and some Programmed 1/ 0 is necessary to initialize and check
the status of the device.
3.3.4 The External Bus
The External Bus , whi ch is mechanically and electrically organized the same as the 1/ 0 Bus on the PDP-S/ l or the
PDP- S/ I computers, plugs into the Omnibus by way of the Positive 1/ 0 Bus Interface and the Data Break Interface.
Each of these modules receives the same signal on the same pins as any other module plugged into the Omnibus.
The interfacing deta ils of the External Bus are given in Paragraph 3 . 1.9 and Volume II of the PDP-BIE Maintenance
Manual (DEC- SE-HMM2A- D- D).
The PDP-BIA Miniprocessor Handbook contains the information required to select the type of interfa ce requ ired for
the user's device and describes each of the transfer methods in detail.

3.4 MODULE CONFIGURATION ON THE OMNIBUS
The basic PDP-S/ A system is comprised of one Central Processor Unit and at least one memory module . Other modules
may be plugged into t he Omnibus to add additional memory, options, or device interfaces to the system. Table 3-1 lists
the PDP-S/ A -compatible modules along with their Omnibus slot assignments.
Hex and quad mod ules cannot be inter-m ixed on the Omnibus. All hex modules should be put together in the top
slots and all quad modules in the bottom slots.

3-4

For options that require additional modules to hold all the logic, two or more modules may be connected with H851 top
connectors (Figure 3-4).

Table 3-1
Slot Assignments for Modules on the Omnibus
Option

Optical Mark Card Reader Control
Card Reader Control
Interprocessor Buffer
I/O Option Module
Synchronous Modem Interface
Buffered Digital I/O
Positive I/O Interface
Programmer's Console
Data Break Interface
Redundancy Check Option
Central Processor Unit
Central Processor Unit
Timing Generator
Bus Loads
Asynchronous Data Interface

Extended Option Module
Line Printer Control
Line Printer Control
Core Memory (8K)
Core Memory (16K)
Read Only Memory (1 K)
Read Only Memory (2K)
Read Only Memory (4K)
Reprogrammable Read Only Memory
ReadlWrite Memory (1 K)
ReadlWrite Memory (2K)
ReadlWrite Memory
Reader Punch Control
RK05 Disk Control
TU60 Cassette Interface
TU10 DEC Magtape Control
Point Plot Display Control
Video Display and Terminal Control
DK8-EP Real Time Clock
AD8-A A/D Converter

Option
Designation

Type of
Module

CM8-F
CR8-F
DB8-EA
DKC8-AA
DP8-EA, EB
DR8-EA
KA8-E
KC8-AA, AB
KD8-E
KG8-EA
KK8-A

Quad
Quad
Quad
Hex
Quad
Quad
Quad
PNL.MT.
Quad
Quad
Hex
Quad
Quad
Quad
Quad
Quad
Hex
Quad
Quad
Hex
Hex
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad

KK8-E
KL8-JA
KL8-M
KM8-A
LE8-XX
LS8-F
MM8-AA
MM8-AB
MR8-AA
MR8-AB
MR8-AD
MR8-FB
MS8-AA
MS8-AB
MS8-AD
PC8-E, PR8-E
RK8-EA
TA8-AA
TM8-EA, -FA
VC8-E
VT8-E
DK8-EP
AD8-A

Number o.
Modules

2
1
1
0

1
2

1
2
2

3
1
4
2
3
2

Omnibus Slot
Assignment
4-last*
4-last
2-last
2-3
2-last
2-last
4-last
N.A.
4-last
4-last
1
Refer
to
Table 2-2
2-last
2-last
2-3
2-last
2-last
4-8
4-8
2-last
2-last
2-last
2-last
4-last
4-last
4-last
4-last
4-last
2-last
4-last
2-last
4-last
2-last
2-last

*' Last' applies except when considering both a non-expanded 8A600 or 8A620, and the added chassis of an expanded 8A600 or 8A620
(refer to Table 2-2).

3.5 OMNIBUS PIN ASSIGNMENT
Figure 3-5 relates the PDP-8/A modules (both quad and hex) and the Omnibus signals. The connectors are illustrated in
the lower part of the figure. The component side of the module is side 1. Individual pins are specified in this manner: B H 1
means connector B, pin H, side 1; DM2 means connector 0, pin M, side 2, and so on. Each connector pin has a
corresponding pin on the Omnibus that carries a specific PDP-8/A signal. The upper part of Figure 3-5 relates the signal
names to the Omnibuslmodule connector pins. The L (low) or H (high) after the signal name identifies the assertion level
for that signal. For example, MOO L is asserted (a logical one) when it is low (+0.4 to -0.5 V). Most signals on the
Omnibus are tied through a load resistor to + 5 Vdc. High level signals should be a minimum of + 2.6 Vdc and low level
signals should be +0.4 Vdc, as defined by TTL logic.

3-5

Figure 3-4

Modules Connected With HS51 Type Connector

The Omnibus is wired so that the signal appearing on a specific pin is the same for most slots on the Omnibus. For
example , pin CK 1 of every Omnibus slot carries signal BUS STROBE L. There are some exceptions and these are noted in
Figure 3-5 . In slot 1, which has the KKS-A CPU plugged into it. pins AA 1 and CA 1 are tied to + 5 Vdc instead of being
test points as indicated in Figure 3 -5. These pins supply the extra 5 Vdc current required for the MS31 5 module. Slots
2 and 3 also have pins with signals but they are different from the signals in the other slots.

BA 1 of slots 2 and 3 carries BA TIERY EM PTY L

BB 1 of slots 2 and 3 carries AC LOW L

DA 1 of slots 2 and 3 carries PAN EL LOCK L

3-6

CONNECTOR. SIDE

PIN
EI
A

This pin is connected to ground an the
bus but serves as a logic signal within
modules for testing.

Pins AA 1 and CA 1 in slat 1 supply
+5 V to the CPU module.

Pin BA 1 of slots 2 and 3 supplies
BA TTERY EMPTY to the aptian
modules.
Pin BBl of slats 2 and 3 supplies AC
LOW to the aptian modules.

DA 1 of slots 2 and 3 supplies PANEL
LOCK to the option modules.

F2~
CONNECTOR F
NOT CONNECTED
TO THE OMNI BUS

+15V

TP NOTE 2

+SV

TP NOTE 3

+SV

TP NOTE 2

+SV

NOT USED

-15V

-IS

TP NOTE 4

-15V

GND

GNO

GND

SP GND NOTE

NOT USED

MA8L

IR0 L

I/O

TPI H

MA4L

INT STROBE H

MA0 L

PAUSE L

-1SV

GND
EMA0L

+20V

MA9L

IRIL

C0L

TP2 H

MAS L

BRK IN PROG L

MA1L

GND

MEM REFRESH (+5V)

MAI0L

IR2 L

CIL

TP3 H

MA6 L

MA,MS LOAD CONT L

MA2L

EMA2 L

MEM REFRESH(+SV)

MAIIL

C2 L

TP4H

MA7L

OVERFLOW L

MA3 L

MEM START L

+20V

MD8L

BUS STROBE L

TSI L

MD4 L

BREAK DATA CONT L

MD0 L

MD DIR L

NOT USED

MD9L

INTERNAL 110 L

TS2 L

MDS L

BREAK CYCLE L

MDIL

SOURCE H

-5V

MDI0 L

USER MODE L

NOT LAST XFER L

TS3 L

MD6 L

LA ENABLE L

MD2 L

STROBE H

GND

+20V

MOil L

F SET L

INT ROST L

TS4 L

MD7 L

INT IN PROG H

MD3 L

INHIBIT H

NOT USED

DATA 8 L

PULSE LA H

INITIALIZE H

LINK DATA L

DATA 4 L

NTS STALL L

DATA 0 L

RETURN H

NOT USED

JUMPER 1

JUMPER

L--J

TP NOTE 5

~~~z~r~L~'monm~

+20V

No tes

DATA 9 L

STOP L

SKIP L

LINK LOAD L

DATA 5 L

RES H

DATA 1 L

WRITE H

i GND

GND

i NOT USED

DATA 10 L

KEY CONTROL L

CPMA DISABLE L

IND I L

DATA 6 L

RUN L

DATA 2 L

ROM ADDRESS L

NOT USED

DATA II L

MS,IR DISABLE L

IND2 L

DATA 7L

POWER OK H

DATA :3 L

LINK L

c::::J

c:J

r---'"

c:::::J

c:::J

<C--4(J);O<JZs:r;;<;<-I"'lrTJO O CDl>

<C--4(J)::O<JzS:r;;<;<-I"'lrTJOOrnl>

HEX MODULE
(COMPONENT SIDE)

< c --4 (J) ;0 <J Z s: r ;;<; <- I "'l rTJ 0 OCD l>

<C--4(J);o<JZs:r;;<;<-I"'lrTJOOCDl>

C~ONN~TOR E2~)
E

SI DE I

CONNEC TORE
SIDE 2

< C --4 (J) ;0 <J Z s: r ;;<; <- I "'l rTJ 0

OCD l>

C2~

A2/

QUAD MODU LES
HAVE 4 CONNECTORS

03·1011::1

3-7

3.6 MAjOR GROUPS OF SiGNALS
The 96 signals of the Omnibus can be divided into nine major classes.
Memory Address - 15 Lines
3.6.1
The 15 signals EMA<0:2>L and MA<0:11>L form a bus which defines the currently active memory address. The
source of MA <0: 11 > L is the CPU during instruction processing. and the currently active data break device during
Direct Memory Access (DMA) operations. The source of EMA<0:2>L is the memory extension control during instruction processing. and the currrently active data break device during DMA operations. Load resistors within the
CPU define EMA<0:2>L as zeros (highs) if there is no memory extension control in the system.
3.6.2

Memory Data and Memory Direction Control - 13 Lines

3.6.2.1
MD<O:11>L - The 12 signals MD<0:11>L form a bidirectional data path between memory and CPU.
In addition. these lines are monitored by Programmed 1/0 devices to determine device code and sub-device operation. and by data break devices to obtain output (memory-to-DMA device) words.

3.6.2.2

MD DIR L - The source -of information on MD<O: 11 >L is controlled by MD DIR L. If MD DIR L is

low. the data of the currently active memory is gated onto MD<O: 11 >L. If MD DIR L is high. the contents of the CPU's
memory buffer register are gated onto MD<0:11>L.
3.6.3 Data Bus - 12 Lines
The 12 signals DATA <0: 11 > L form a mUlti-purpose 12-bit bus used for data e~change between peripheral and
CPU. for data input from DMA devices. for front-panel monitoring of selected registers. and for the determination of
data break priority.
3.6.4 I/O Control Signals - 10 Lines
This group of signals controls the 1/0 dialogue between CPU and programmed peripherals. This group includes
INITIALIZE H. which is used for clearing peripheral flags.
3.6.5 DMA Control Signals - 8 Lines
This group of signals controls the operation of data break (DMA). Several of these signals are also activated for certain
front panel operations. Included in this group is RUN L. which is used for clearing data break requests when the computer
is halted.
3.6.6 Tim ing Signals - 9 Lines
Five time pulses serve as system clocks. Similarly. four time state levels serve as system enabling levels. All of these
signals originate within the main timing generator of the CPU.
3.6.7 CPU States - 6 Lines
The major state of the CPU appears on FL, DL, or EL (FETCH, DEFER, or EXECUTE); the operation code of the instruction
currently being processed appears on IR<0:2>L.
3.6.8 Memory Timing Signals - 5 Lines
Five signals originate in the main timing generator of the CPU and are bused to all memories. These signals
(SOURCE H. RETURN H. WRITE H. INHIBIT H. and STROBE H) control all memory operations.
3.6.9 Miscellaneous Signals - 18 Lines
These signals do not fit into any of the above categories. A large percentage of them are used by the Programmer's
Console. Two signals (ROM ADDRESS Land NTS STALL L) are driven by some types of memories under special
conditions. and are monitored by the CPU and other memories. The rest of these signals are truly miscellaneous. Included
in this group is a signal (POWER OK H) that reports the validity of the power supply voltages.

3-8

3.6.10 Special Signals
Slots 2 and 3 of the Omnibus carry some special signals which are used on the PDP-S/A option modules. They are: AC
LOW L, BATIERY EMPTY L (associated with the battery back-up power supply). and PANEL LOCK (disables operations
from the Programmer's Console when the PANEL LOCK switch is placed in the down position).
3.6.11
Interconnections
The interconnection of various system parts via the Omnibus is shown below:

CPU

MEM

EXT
b

MEM ADD
MEM OAT
DATA BUS

1/0 CTRL
DMA CTRL
TIMING
CPU ST
MEM TIM
MISC

MEM

DMA

110

PANEL

u t
n t h

•••
•••
X
•••X
•••X
•••X
•••
X
•••
X
•••
X
•••
X
•••X

•••
•••
X
•••
X
•••X
• ••X
•••
X
•••
X
•••
X
•••
•••X

•••
•••
X
•••X
•••
•••
•••
•••
•••
•••
X
•••X

•••
• ••
•••
X
•••X
•••X
•••
•••
X
•••
•••
•••

•••
• ••
X
•X ••
• ••X
• ••
• ••
X
•••
X
• ••
•••
• ••

• ••
•X ••
•X ••
• ••X
•X ••
•X ••
•X ••
•X ••
• ••
• ••X

*This is just the DMA portion of what is usually a complex peripheral. Such a peripheral usually uses the programmed
I/O signals as well.

3.7 DETAILED DESCRIPTION OF THE 96 OMNIBUS SIGNALS
This paragraph describes the logical operation of each of the Omnibus signal lines. The paragraphs are arranged similar to Paragraph 3.6 for easier correlation.
3.7.1
Memory Address - 15 Lines
These signals are changed starting at the leading edge of PULSE LOAD ADDRESS H or TP4 H and remain static
through the entire memory cycle.
3.7.1.1

EMA <O:2>L. - Must be settled 50 ns prior to leading edge of SOURCE H and RETURN H.

Signal

EMAO L
EMA1 L
EMA2 L

AD2
AE2
AH2

Most Significant Bit
Least Significant Bit

3-9

3.7.1.2

MA <O:11>L. - Must be settled 50 ns prior to leading edge of SOURCE H and RETURN H.
Signal

MAO L
MAl L
MA2 L
MA3 L

AOl
AEl
AHl
AJl

MA4 L
MA5 L
MA6 L
MA7 L

BOl
BEl
BHl
BJl

MA8 L
MAg L

001
DEl
OHl
OJl

MAlO L
MAll L
3.7.2

Most Significant Bit

Least Significant Bit

Memory Data and Direction Control - 13 Lines

3.7.2.1
MD<O:11 >L. - These lines form the data path to and from memory. If MO OIR L remains low for the entire
memory cycle, information from memory may be placed on the M 0 lines as late as 1 50 ns prior to TP2; otherwise, the
information must be present 250 ns before TP2. If MO OIR L is allowed to go high, the new M 0 information from the
CPU's Memory Buffer register must be on the Omnibus 150 ns prior to the leading edge of INHIBIT H, and must remain
static for the duration of INHIBIT H for proper memory operation. It is desirable that the MO lines remain static into Time
State 1 (TS 1) of the next machine cycle to facilitate displaying the contents of memory when single-stepping programs.
Signal

MOO L
MOl L
M02 L
M03 L

AKl
AL1
AMl
APl

M04 L
M05 L
M06 L
M07 L
M08 L
M09 L
MOlD L
MOll L

BKl
BL1
BMl
BPl
OKl
OLl
OMl
OP1.

Most Significant Bit

Least Significant Bit

3.7.2.2 MO DIR L - L=memory driving MO lines; H=CPU's MB register driving MO lines. MO OIR L is always
low from 100 ns after the leading edge of TP 1 H to the leading edge of TP2 H, when it may be allowed to go high.
The gating from M 0 01 R L to the drivers of the M 0 bus is static; hence care should be taken to guarantee that this
line does not "glitch". If M 0 01 R L remains low for the entire memory cycle, the information on the MO lines is
valid from the time it is placed on the Omnibus through the end of the memory cycle. No extra time need be allotted for computing and storing information in the CPU's MB register, and no time need be allotted for M B driver
turn-on and bus propagation after TP2.
Signal

MO OIR L

AK2

3-10

3.7.3

Data Bus - 12 Lines

DATA <0:11 >L. The data is a multi-purpose, '12-bit bus whose use is a function of the machine state. During TS1 of
every memory cycle, the data bus carries indicator information as defined by the IND lines, (Paragraph 3.7.9.1).
During TS2 of FETCH cycles, the data bus carries the contents of the AC. During TS2 of DMA cycles, the data bus carries
information to be placed in memory, or information to be added to the contents of memory. During TS3 of lOT instructions, the information on the data bus is a function of the liD control lines (Paragraph 3.7.4.5). During TS3 of OP2
instructions, the contents of the CPU's AC are plclced on the data bus if the CLA bit (bit 4 of the instruction word) is zero,
and the contents of the control panel's switch re~Jister are placed on the data bus if bit 9 of the instruction word is a one.
This implements the OSR and LAS instructions. During TS4 of all machine cycles, the data bus is reserved for determining data break (DMA) priority. See Paragraph 3.7.5 for more details.
A good general rule is for all logic to stay off the data bus unless there is a valid reason for placing data on that
bus. The data bus must be left free for use by the CPU.

3.7.4

Signal

DATAO L
DATA1 L
DATA2 L
DATA3 L

AR1
AS1
AU1
AV1

DATA4 L
DATA5 L
DATA6 L
DATA7 L

BR1
BS1
BU1
BV1

DATA8 L
DATA9 L
DATA10 L
DATA11 L

DR1
DS1
DU1
DV1

Most Significant Bit

Least Significant Bit

I/O Control Signals - 10 Lines

Basic I/O devices may perform data exchange between the AC of the CPU and the device's registers. The state of
the device is tested using skip instructions. ThBse devices need not make connection to C2 L, BUS STROBE Land
NOT LAST XFER l.
More complicated liD devices may use BUS STROBE L and NOT LAST XFER L to stall the CPU, perform multiple
transfers in a single lOT, andlor modify the PC (and/or the Link).
3.7.4.1
I/O PAUSE L - Pin CD1 - liD PAUSE L is low if F L MOO Land MD1 L are low and USER MODE L
and M 02 L are high. Also included is a gating term from the timing chain. It is the command to all Programmed I/O
peripherals to compare their device codes with the contents of M 0 <3: 8> l. If a peripheral finds equality with
MD<3:8>L it decodes MD<9: 11 >L to determine the sub-device operation to be performed. The peripheral has
100 ns in which to decode its subdevice operation and assert information onto the C lines and data bus. Similarly, it
must remove all information 100 ns after I/O PAUSE L is negated.

liD PAUSE L remains asserted during extended liD cycles until the CPU has been restarted. (Paragraph 3.7.4.7)
Although not mandatory, it is strongly urged that the peripheral logic design incorporate load-relief logic to minimize
loading on the DATA and MD buses when liD PAUSE L is negated. Loading rules require load relief if there is more than
one Programmed liD peripheral.

3-11

3.7.4.2 INTERNAL I/O L - Pin CL1 - INTERNAL 1/0 L alerts the KAS-E Positive 1/0 Bus Adapter that an I/O
device on the Omnibus has recognized the lOT being processed. If the KAS-E finds this line not asserted. it processes the lOT by stopping the CPU and entering an expanded I/O cycle.
All internal (Omnibus) I/O devices ground this line if they find equality between MD<3:S>L and thnir device code
when I/O PAUSE L is low.
3.7.4.3 SKIP L - Pin CS1 - SKIP L is sampled by the CPU at TP3 to determine if an I/O skip should occur. The skip
occurs if SKIP L is low. This line is sampled every TP3 (not just during lOT instructions) if the processor is not in the
DMA state.
3.7.4.4 INT ROST L - Pin CP1 - INT ROST L is sampled by the CPU at the leading edge of INT STROBE H if all
other interrupt conditions are met to determine if an interrupt request is pending. This line is asserted by a peripheral
device when a condition that causes an interrupt is encountered. Since the CPU contains a synchronizing flip-flop, this
line may be asserted at any time. In addition, if this line is grounded 100 ns or more before TP3, the SRO instruction
will skip.
3.7.4.5 C<O:2>L - Pins CE1 (CO L); CH1 (C1 L); CJ1 (C2 L) - C<O:2>L control the tyre of transfer during
an lOT as shown below:
C<O:2>L
012

Transfer

H x H

AC ~ DATA<0:11>L ~ AC (Peripheral may "or" information onto DATA<0:11>L)
AC~ DATA<0:11>L;O~ AC
DATA<0:11>L~ AC
DATA<0:11>L+PC~ PC
DATA<0:11>L~ PC

L HH
L L H

x H L
x L L

x z: doesn't matter. In general, peripherals use only SKIP L to modify the PC, and so do not make connection to C2 L. See
Paragraph 3.8.4 for the impact on timing.

3.7.4.6 BUS STROBE L - Pin CK1 - BUS STROBE L is a negative-going pulse which causes the AC or PC to
be loaded during an lOT. BUS STROBE L is also used in conjunction with NOT LAST XFER L during long I/O cycles
(Paragraph 3.7.4.7).
During an lOT, gating within the CPU generates a single BUS STROBE L pUI~cl at TP3 time if NOT LAST XFER L is
high (i.e., if the lOT is not an extended lOT). If an extended 1/0 cycle is in I rocess (i.e .. if NOT LAST XFER L is low
at TP3 H). the peripheral must generate all BUS STROBE L pulses. The AC or PC (depending on C2 L) is loaded at
the leading (falling) edge of BUS STROBE L.
3.7.4.7 NOT LAST XFER L - Pin CL 1 - Most peripheral controllers require only one transfer per lOT; hence the
single transfer at TP3 time is adequate. Such peripherals do not ground NOT LAST XFER L and do not drive BUS
STROBE L. Other, more complex peripherals (the KAS-E Positive I/O Interface. for example) require extended timing
and use NOT LAST XFER L to "stall" the CPU in an I/O cycle.
To stop the CPU in TS3 of an I/O cycle, ground NOT LAST XFER L prior to TP3 H of the lOT.
The CPU will remain in TS3, and will not generate INT STROBE H or BUS STROBE L. Timing is now controlled by the
peripheral.
The peripheral may make any number of transfers by controlling C<O:2> L. generating BUS STROBE L and keeping
NOT LAST XFER L at ground.

3-12

The .CPU is restarted by allowing NOT LAST XFER L to go high before the leading (falling) edge of BUS STROBE L.
In addition to making a final data transfer. the CPU restarts by generating INT STROBE H. entering TS4 and by negating 110 PAUSE L.
3.7.4.8

INITIALIZE H - Pin CR1 - INITIALIZE H is asserted (high) by:

Pressing the Programmer's Console INIT key.

Executing the CAF instruction (octal 6007).

Negating the POWER OK H.

INITIALIZE H statica~y clears the AC. Link. interrupt system. and peripheral flags. It also sets the interrupt enable
flip-flops of peripherals that must remain program-compatible with older versions that did not have an interrupt enable flip-flop. (Two important devices in this category are the TTY and paper-tape reader/pun(". interrupt enables.)
3.7.5 DMA Control Signals - 8 Lines
Data breaks (DMA) allow a peripheral to communicate directly with memory. bypassing the CPU. The only CPU register available to the DMA device is the M B; all other CPU registers must be preserved. Data breaks may occur between any CPU cycles. but a data break cannot be performed while the CPU is in the midst of an extended I/O
cycle because the currently active memory is then supplying information to the bus.
Data breaks take place in the following sequence:
1.

At INT STROBE H leading edge. the decision to request a data break is made at the peripheral by setting its
break request flip-flop.

A device starting a data break unconditionally asserts CPMA DISABLE L and BREAK IN PROG L until its
break request flip-flop is cleared.

Data break priority is determined on DATA <0: 11 > L when TS4 L is asserted. Each data break device is
assigned a unique line on DATA<O: 11 >L with DATAO L being the highest-priority line. Each requesting
device asserts its line on DATA <0: 11 > L and examines the state of all higher-priority lines to determine
if they are all high. For example. a device asserting DATA5 L examines DATA<O:4>L to make sure
these lines are all high. The device finding all higher-order lines high proceeds to step 4 below; all other
devices remain in step 3.

The device winning the priority test sets its MA Control flip-flops at the leading edge of TP4 H. (The
path from TP4 H to the Memory Address lines must have as little delay as possible; hence two flip-flops
are recommended to provide adequate drive without introducing the delay of a buffer (Paragraph
3.7.5.7). The MA Control flip-flops gate the break address onto the 15 Memory Address lines. and assert
MS. IR DISABLE L and (if this cyde is a data exchange cycle) BK CYCLE L.

At TP1 H. the active device asserts MA. MS LOAD CONT L.

For input to memory. the active device merely places its data on DATA<O: 11 >L during TS2. For output
from memory. the device asserts BREAK DATA CONT L during T52 L and loads its register with the
contents of MD<O: 11 >L at the leading edge of TP2 H. TP3 H. or TP4 H. For Add To Memory. the device places the data to be added on DATA<O: 11 >L during T52. and asserts BREAK DATA CONT L during T52. The modified information is loaded into the CPU's M B and overflow flip-flop at TP2 H. and may
be read by the device at TP3 H or TP4 H. (TP3 H is generally used. since OVERFLOW L is valid only at
this time.) The data prior to modification may be read at the leading edge of TP2 H.

3-13

At the completion of a data break. all lines are in the same order and at the same times in which they
were asserted.
Three-cycle data breaks are merely three one-cycle data breaks with a special control to handle Word
Count and Current Address cycles. BREAK CYCLE L is not asserted during these two cycles; it is asserted only for the final. data exchange cycle.
D MA latency is the longest machine cycle. plus the time of TS4.

3.7.5.1
BRK IN PROG L - Pin BE2 - This signal provides indicator information to the console. It is grounded at
INT STROBE H leading edge if a break is to take place. and asserts the console BRK IN PROG bit of the Major
State Register.
3.7.5.2 CPMA DISABLE L - Pin CU1 - CPMA DISABLE L is asserted (low) by break devices if data breaks are
to occur. It is sampled by the CPU and memory extension control at the leading edge of TP4 H. If CPMA DISABLE
L is low at that time. the memory extension control's field bits and the CPU's Memory Address bits are removed
from EMA<O:2>L and MA<O: 11 >L. If CPMA DISABLE Lis negated (high) at the leading edge of TP4 H. the
memory extension field bits and the CPU's Memory Address register are gated to EMA<O:2>L and MA<O: 11 >L
respectively.
3.7.5.3 MS, IR DISABLE L - Pin CV1 - When MS. IR DISABLE L is high. the Major State and IR flip-flops drive
the Major State and IR lines on the Omnibus (Paragraph 3.8.1). When MS. IR DISABLE L is asserted (Iowl. the Major State and I R lines are not driven by the CPU. Unless some external device asserts a Major State. the CPU is
then in the DMA state.
3.7.5.4 MA, MS LOAD CONT L - Pin BH2 - When MA. MS LOAD CaNT L is negated (high). the CPU and
memory extension control function normally. Asserting this line inhibits the loading of new information into the
CPU's Major State and Memory Address registers. and into certain control flip-flops of the memory extension control. This signal must Jlot change while TP4 H is high. It is normally changed at TP1 time.
3.7.5.5 BREAK DATA CONT L - Pin BK2 - This signal is ignored unless F L D L. and E L are all high. BREAK
DATA CaNT L should be stable as early in TS2 as possible. and defines the information loaded into the M B at TP2
H. If BREAK DATA CaNT L is high during TS2 of a DMA. DATA<O:ll>L is loaded into MB<O:11>. If BREAK
DATA CaNT L is low during TS2 of a DMA. MD<O: 11 >1 plus DATAO: 11 >L is loaded into MB<O: 11 >. Making
BREAK DATA CaNT L low and placing no information (zeros) on DATA<O: 11 >L causes a DMA that does, not modify memory.
3.7.5.6 OVERFLOW L - Pin BJ2 - This line is asserted (low) during TS3 if a carry occurs at TP2. Hence this line
is asserted if any of the following occur:
1.

Auto Index or JM S wrap-around

ISZ overflow

Data break overflow or carry

3.7.5.7 BK CYCLE L - Pin BL2 - Panel information from the data break device. Low indicates that a break data
transfer cycle is in process.
3.7.5.8 RUN L - Pin BU2 - This signal is really a CPU state since it indicates that the CPU's timing generator is
running (when low). It is included in this group of signals because its most important function is as a gating term
used to clear all break requests when negated (high).

3-14

3.7.6 Timing Signals - 9 Lines
Five pulses and four levels originate in the timing generator of the CPU and are used as system clocks and enabling
levels respectively. Time pulses are nominally 100 ns wide (INT STROBE H is more loosely defined. Refer to Paragraph 3.8.1). Time states change nominally 50 ns after the leading edge of the time pulse. When the CPU is
stopped. the machine is at the beginning of TS 1. Applying a single M EM START L causes the timing chain to start
and continue to run until:
1.

The STOP L line on the Omnibus is asserted at TP3. or

The CPU encounters a HLT instruction at TP3. or

POWER OK H is negated at TP3 and the current memory cycle is complete.

A time state precedes the time pulse of the same number; INT STROBE H is coincident with TP3 H except when in
an extended lOT operation; TS 1 L is automatically entered at the end of TS4.
Pin

Signal

3.7.7

TS1 L
TS2 L
TS3 L
TS4 L

CK2
CL2
CM2
CP2

TP1 H
TP2 H
TP3 H
TP4 H

CD2
CE2
CH2
CJ2

INT STROBE H

BD2

CPU STATE - 6 Lines

3.7.7.1
Major State Lines
The CPU Major State appears on these lines unless MS. IR DISABLE L is asserted (Paragraph 3.7.5.3). The Major
State as seen by the CPU's instruction decoder is taken from these lines. thus it is possible to build special options
which force instructions to the CPU. Normally. the Major State lines change at TP4.
Major State

DJ2
DK2
DL2

D l.
E L

3.7.7.2 IR<O:2>L - These reflect the state of the CPU's instruction register provided MS. IR DISABLE L is high.
A low on ~R<O:2>L represents a one in the corresponding bit of the Instruction Register. As in the case of the Major State lines. the IR lines are disconnected from the Instruction Register if MS. IR DISABLE L is low. The instruction seen by the CPU during D and E Major States is obtained from these lines. During instruction FETCH. the Direct
JUMP. lOT. and operate instructions are decoded directly from the MD lines. As with the Major State lines. it is possible to force instructions during defer or execute cycles. The I R is loaded at TP2 of an instruction FETCH (F L is
lowl. or at TP4 if an interrupt is being honored (lNT IN PROG H is high).
Signal

IRO L
IR1 L
IR2 L

DD2
DE2
DH2

3-15

3.7.8 Memory Timing Signals - 6 Lines
These signals are defined in terms of the 1.5 /-lS memory cycle. (See Paragaraph 3.8.2 for waveforms.)
SOURCE H - Pin AL2, and RETURN H - Pin AR2 - These signals become asserted (high) at the same
3.7.8.1
time and direct the memory to turn on its read/write currents. RETURN H becomes negated 50 ns later than
SOURCE H, thereby defining the voltage to which the memory stack is charged.
3.7.8.2 WRITE H - Pin AS2 - WRITE H controls the direction of current flow in the memory stack. It is high during write and low during read. If WRITE H is low, the positive-going transition of SOURCE H is usually used to clear
all Memory Buffer registers.
3.7.8.3 INHIBIT H - Pin AP2 - INHIBIT H is a gating level to the inhibit drivers of core memory. When high, it
causes the selected memory's inhibit drivers to turn on.
3.7.8.4 STROBE H - Pin AM2 - The leading edge of STROBE H provides a time reference from which the
strobe in each individual memory is derived. Each memory delays this edge by an optimum amount for that memory,
and then strobes its sense amplifiers. The selected memory must have its data on M D <0: 11 > L at or before strobe
leading edge plus 150 ns (this time does not include bus charging time).
3.7.9

Miscellaneous Signals - 18 Lines
IND1 L

IND2 L

H
H
L
L

H
L
H
L

Information on DATA<O:11>L
Status Word*
MCKO:11>
All zeros (highs)
AC<O:11>

*STATUS WORD (Figure 1-5)

I nfor rna tion

Bit

LINK

1
2
3
4
5
6-8
9-11

Not used
INT ROST L (low on DATA2 L if INT ROST L [Pin CP1] is low)
INT INH Flip-Flop**
INTERRUPT DELAY Flip-Flop (denotes interrupt on)
User Mode L **
IF<O:2>**
DF<O:2>**

**From memory extension control if present, otherwise these remain high (zeros).

3.7.9.1
INC1 L -' Pin CU2, and INC2 L - Pin CV2 - These signals control the information gated to
DATA <0: 11 > L during TS 1. Since DATA <0: 11 > L is defined as low for a 1, ones in register bits place lows on
DATA<O: 11 >L.
Gating circuitry in any logic driving IND1 Land IND2 L should ground IND1 L and allow IND2 L to go high if LA
ENABLE L is asserted (low) (Paragraph 3.7.9.9).
3.7.9.2 MEM START L - Pin AJ2 - Grounding MEM START L causes the timing chain of the CPU to start.
M EM START L may be a 100 ns negative-going pulse, or it may be a level that is low if TS 1 L is asserted and the
logical decision to start the machine has been made. MEM START L must not be asserted (low) beyond TP2 H.
since it may then interfere with possible H LT instructions.

3-16

A single MEM START L pulse causes the CPU to start and continue to run until halted by the program or by the
STOP L line (Paragraph 3.7.9.3).
3.7.9.3 STOP L - Pin DS2 - STOP L is sampled by the CPU at the leading edge of TP3 H of every machine
cycle. If STOP L is asserted (low). the CPU completes its current memory cycle and stops in TS 1 (just after TP4 H
goes to ground). At that point in its cycle, the CPU can display:
New Memory Address (on EMA<0:2>L and MA<O: 11 L)
New Major State (on F L D Land E L)
Memory Data of last-referenced location (on MO<O: 11 >L)
Status or AC or MQ (on OATA<0:11>L, depending on IN01 Land IN02 L)
Any other lines on the Omnibus for which display provision has been made
STOP L is asserted by HLT/SS on the Programmer s Console, and is also asserted when:
Single deposit (0 THIS) operation is in process
Examine operation is in processor
A H LT instruction (octal 7402) is executed.
POWER OK H is low KEY CONTROL L is low during examine or deposit condition (Paragraph 3.7.9.9).
3.7.9.4

LINK L - Pin AV2 - LINK L is low if the LINK bit of the CPU is a one. and high if the LINK is a zero.

3.7.9.5 LINK LOAD L - Pin CS2, and LINK DATA L - Pin CR2 - These two signals allow loading of the LINK
from the Omnibus. Loading occurs on the leading (falling) edge of LINK LOAD L. and the data loaded into the LINK
is a one if LINK DATA L is low. These two signals should be used only in extended I/O cycles while NOT LAST
XFER L is low.
3.7.9.6 F SET L - Pin DP2 - This line is asserted (low) if the Major State gating of the CPU indicates the next
Major State will be a FETCH. The conditions causing this line to be asserted are:
1.

A Major State of EXECUTE, no interrupt being honored (Paragraph 3.7.9.8).

A Major State of DEFER and an IR of 5 (JMP instruction).

A Major State of FETCH, a JMP instruction and MD3 L high (direct jump).

A Major State of FETCH and an lOT instruction.

A Major State of FETCH and an operate instruction.

DMA (F L, D Land E L a" high).

3.7.9.7 USER MODE L - Pin DM2 - This line is normally driven by the timeshare portion of the memory extension control and is tied high by a load resistor in the CPU if no memory extension control is in the system. USER
MODE L is changed only at TP4 time.

3-17

If USER MODE L is high, the CPU and control panel function normally. If USER MODE L is asserted (low). the following operations are inhibited:
1.

The HALT instruction (inhibited in the CPU)

The OSR and LAS instructions (inhibited in the panel logic)

1/0 PAUSE L remains high even though an lOT instruction is fetched from memory (inhibited in the
CPU).

Interruption of the program, upon detection of any of these conditions, is handled by the memory extension control.
3.7.9.8

I NT IN PROG H - Pin BP2 - INT IN PROG H is allowed to go high if:

The interrupt system has been turned on by an ION or RTF instruction and at least one subsequent instruction fetch has occurred.

An interrupt request has been recognized by the INT SYNC flip-flop of the CPU (which sets at the leading edge of INT STROBE H if INT RQST Land FSET L are both low).

There is no interrupt inhibiting condition. This condition is preserved in the INT INHIBIT flip-flop in the
memory extension control, and is generated if a CIF, CUF, SUF, RMF or RTF instruction has been processed and a JM P or JMS has not yet occurred to complete the field change.

INT IN PROG H is used by the CPU to load 0 into the CPU's MA. force the Major State to EXECUTE and IR to
JM S, and to turn off the interrupt system. INT IN PROG H is also used by the memory extension control to load the
save field, and to clear the IB, IF and DF. INT IN PROG H goes high at INT STROBE H time, and is not negated
again until the interrupt system is turned off (lNT IN PROG H, INT STROBE H and not DMA).
3.7.9.9 LA ENABLE L - Pin BM2, and KEY CONTROL L - Pin DU2 - These lines must not be asserted unless
the CPU is in the DMA state (MS, IR DISABLE L low and F L D L. and E L all high). If LA ENABLE L is low. any
logic driving IND1 Land IND2 L must assert IND1 L and turn off any drivers driving IND2 L.
The function of LA ENABLE L, KEY CONTROL L and BREAK DATA CO NT L are defined as follows:
Load Address Enable
L
L
L
L

H
H
H
H

Key Control
L
L

Break Data Control

Function

XLA 7
XLAO
Non-stop deposit
Load address
Panel examine
Panel deposit
Add to memory*
Break deposit*

H
H

H
L
H

L
L

H
H

L
L

*See Paragraph 3.7.5.5.

E THIS or E NEXT on the Programmer's Console asserts STOP L performs one memory cycle at the address in the
CPU's MA register, does a break add to memory, and increments the MA.
D THIS or D NEXT on the Programmer's Console asserts STOP L performs one memory cycle at the address in the
CPU's MA register, does a break deposit with the Entry Register of the console providing input data, and increments
the MA.

3-18

Load Address - There are two possible functions. If PU LSE LA H is asserted, the MA is loaded from
DATA<O: 11 >L. If MEM START L is asserted, the CPU starts, performing an examine at whatever location is in the
CPU's MA. At TP3 H, the contents of DATA<O: 11 >L are loaded into the PC and transferred to the CPU's MA at
TP4 H. The CPU is not stopped. (STOP L is not asserted.)
Non-stop Deposit - Same as panel deposit except STOP L is not asserted, so the CPU continues to run. Useful for
loading bootstrap programs into memory.
XLAO - There are two modes of operation. If PULSE LA H is asserted, the memory extension control is loaded with
whatever is on DATA<6: 11 >L. If MEM START l is asserted, the CPU starts and does an examine at whatever location is in the CPU's MA. The memory extension control is loaded at TP3 H, but 0 is on DATA<6: 11 >L so the memory extension control's IF, IB, and DF registers are cleared. STOP L is not asserted, so the CPU continues to run.
XLA7 - Like XLAO with MEM START L, except that the CPU places 7777 on DATA<O: 11 >L. loading 7 into the
I B, I F, and DF. The AC must be 0 for this function to work properly.
3.7.9.10 PULSE LA H - Pin DR2 - PULSE LA H causes the CPU's MA register to be loaded if KEY CONTROL L
is high; or the memory extension control's IB, IF, and DF registers to be loaded if KEY CONTROL L is low. PULSE
LA H is a nominal 100 ns positive-going pulse.
3.7.9.11
ROM ADDRESS L - Pin AU2 - ROM ADDRESS L is examined by core and other read/write memories.
If ROM ADDRESS L is high, the read/write memory functions normally. If ROM ADDRESS L is low, the read/write
memory is disabled. ROM ADDRESS L is asserted by small ROMs which overlay read/write memories, thus providing a small number of read-only locations in a large read/write memory. The gating for this signal must be fast.
There are only 25 ns from the time the address lines have been established to the time this signal must be asserted.
ROM ADDRESS L also modifies the JMS instruction by inhibiting the incrementing of the new PC contents. This action causes the JMS instruction to act like a JMP instruction (except for timing) if a JMS to ROM is attempted.
3.7.9.12 NTS STALL L - Pin BR2 - NTS STALL L (Next Time State Stall L) provides a means of stalling machine operation to accomodate memories slower than the one for which the timing chain was designed.
When NTS STALL L is high, the timing chain of the CPU functions normally. If NTS STALL L is asserted (low), the
timing chain functions normally to the middle of the next time pulse. The time state changes and the time pulse completes in the normal 100 ns, but the timing chain stalls at the beginning of the new time state. The stalling of the
time state continues until NTS STALL L goes high, restarting the timing chain. NTS STALL L has no effect on the
duration of the five memory timing signals. It merely stretches the time before read, the time between read and
write, and the time after write before new address. NTS STALL L must be low, 100 ns, before the leading edge of a
time pulse to guarantee stalling in the next time state. The timing generator will not stall in the next time state if
NTS STALL L is high for the 100 ns prior to the leading edge of the time pulse.
NTS STALL
Low at

And There is

Time State
Becomes Longer at

TP1 H

TS2

Longer time from end of read to TP2, allowing the CPU to accommodate memories with long read access time.

TP2 H

TS3

Longer time from when MB is loaded to the start of write.

TP3 H

TS4

Longer time from start of write to time address is changed: accommodating memories with long write times.

TP4 H

TS1

Longer time from address change to start of read.

Watch break latency when using NTS STALL.

3-19

3.7.9.13 SW - Pin DV2 - This line reflects the state of the bootstrap flip-flop controlled by the switch on the Programmer's Console ORed with the state of the bootstrap switch on the Limited Function Panel. The signal is low if
the switch is up on the Limited Function Panel.
On machines equipped with bootstrap options, the low-to-high transition of this line initiates bootstrap operation if
the CPU is halted. If there is no bootstrap option in the machine, this line is available for any use the user may devise.

3.7.9.14

POWER OK H - Pin BV2 - POWER OK H originates in the power supply and reports the state of the
dc voltages to the CPU, memory extension control and core memories. The dc supplies are in regulation if this signal
is high (Paragraph 3.9).

As the dc supplies fall toward ground, POWER OK H will be negated but may go somewhat positive again as the
+5 V supply nears ground. POWER OK H must remain at less than 0.4 V until all supply voltages are less than 30%
of their nominal value, otherwise, modification of core memory contents may occur.
POWER OK H being low asserts STOP L. POWER OK H going low is also applied to an integrator in the CPU. the
output of which generates INITIALIZE H and is used as a master clear for the timing chain. Similar integrators in
each of the core memories enable and disable the memory current supplies.
Negating POWER OK H does the following:
1.

STOP L is asserted immediately.

At the next TP3 H, RUN L is negated by the CPU.

At the following TS1, all break devices clear their break requests and the memory extension control initializes its EMA Enable flip-flop. The gating to accomplish this is usually the AND of POWER OK H
being low, TS 1 L being low, and RUN L being high.

After a delay (15-500 /-Ls) long enough to allow the longest possible memory cycle to complete, the timing chain is preset to the beginning of TS 1 with TP4 low. All memory timing Signals are made low. The
CPU's control flip-flop, which gates the CPU's MA onto the Memory Address lines, is placed in the "enabled" state. INITIALIZE H is generated, clearing the AC, LI N K and interrupt system.

After a similar delay, each core memory disables its current sources so that memory cannot be altered if
memory timing signals should become asserted as the dc voltages go away.

Upon application of power:
1.

The CPU, extension control and peripherals are all initialized.

Memory current sources are enabled 1 to 70 ms after POWER OK H is asserted. This enabling is accomplished by an integrating capacitor, so that "spikes" on POWER OK H are filtered out.

The internal clear signal and the Omnibus INITIALIZE H signal are negated 200 to 1000 ms after
POWER OK H is asserted.

All portions of the computer should be ready to run 0.1 sec after POWER OK H is asserted. M EM
START L will not be recognized until after INITIALIZE H is negated.

3.7.9.15

RES - Pin BS2 - RES is an unused line. Digital Equipment Corporation reserves the right to define this
line at a later date, and disclaims any responsibility to make this definition agree with any prior illicit use.

3-20

3.7.9.16 Special Signals - Special signals AC LOW L, BAnERY EMPTY L. and PANEL LOCK are carried only on
pins in slots 2 and 3 of the Omnibus.
3.7.9.16.1
AC LOW L - Pin B B 1 (Slots 2 and 3 Only) - AC LOW L is asserted when the ac. voltage falls below
95 Vac ±3% and is negated when ac voltage goes above 105 Vac ±3% (with corresponding values to 2201240
Vac operation). AC LOW L is controlled by a detector in the power supply which senses changes in the ac voltage
levels. On semiconductor machines. the system can continue to operate in the absence of ac power for up to 45 seconds fully loaded. In these machines AC LOW is the signal to switch to battery backup power. With core memory
machines, AC LOW causes an interrupt that allows the program time to transfer the contents of the active registers
to nonvolatile core memory.
3.7.9.16.2 BATTERY EMPTY L - Pin BA1 (Slots 2 and 3 Only) - BATTERY EMPTY L is asserted when a circuit in the power supply senses that the battery voltage has fallen below a certain value. This indicates that the battery has only 1.0 ms of run time remaining before the computer is halted by negation of POWER OK H (Paragraph
3.7.9.14).
3.7.9.16.3 PANEL LOCK L - Pin DA 1 (Slots 2 and 3) - PAN EL LOCK L is asserted when the PAN EL LOCK
switch is in the up position to disable all key pad switches except Switch Register (SR) and the read functions.
3.S TIMING
Many signals on the Omnibus are wire-ORed. For these signals, the high level is determined by a load resistor and
the low level is determined by one or more open-collector gates which ground the signal. Bus capacitance is moderately high; hence fall times in such situations are fast and rise times are slow (about 100 ns). This 100 ns is considered in the following timing diagrams by adding the 100 ns to the set-up times where necessary. This requires
C<0:2> L to be defined from 450 ns before the leading edge of B US STROBE L; 100 ns of this time is allotted to
charging C<0:2>L
3.S.1
Time Pulses and Time States
The time pulses (TP1 H. TP2 H, TP3 H, INT STROBE H, and TP4 H) plus their associated time states (TS 1 L TS2 L
TS3 Land TS4 L) serve as the timing reference from which all other timing is derived (Figure 3-6). Timing pulses
and time states are derived from a master crystal clock (20 M Hz) in the timing generator of the CPU. This clock has
a stability of 0.1 %; hence the time between positive edges of time pulses is accurate to 0.1 %. Time pulse widths are
90-110 ns; the uncertainty is caused by gate skew and threshold variation. Time states change nominally at 50 nf'
after the leading edge of the time pulses, but logic delays and loading introduce an uncertainty in this time.
Figure 3-7 details time pulse and time state change (this applies to TP 1 H. TP2 Hand TP4 H.l

rA-+- B-+-c-+-

0-1

rL- I l_ _ _ _ _ _ __

TP4H --.Jl
TPI H _ _

__________
_______
_ ___

TP2H _________~rI~

~rI~

TP3H
TSIL

TIMEPULSE~

TS2L

10 ns MIN _

TS4L

-90nsMAXIMUM"""
:I
I

A= 350n5
9=400n&
C=400ns

TI ME STATE

OLD

TOTAL TIME= 1500n5

Timing For One Memory Cycle

Figure 3-7

--------t-----

--l-I

0=350n&

Figure 3-6

:--90 to 110ns----.,

L--J

TS3L

:
I

UNCERTAIN

NEW

Time State and Time Pulse Change Timing

Figure 3-8 details TP3 H timing if NOT LAST XFER L is high and if 1/0 PAUSE L is high. (See Paragraph 3.8.5 for other
conditions.)
3.S.2 Memory Timing
Normal memory timing is based on 1.5 /-LS core memory, and is shown in Figure 3-9.

3-21

READ
SOURCEH~

RETURNH~

TP3H~

-:
1

t-- liOns MAXIMUM ---t
-I I- IOns MINIMUM I
-; - - - - ,- -

TIME STATE - TS3
INT

UNCERTAIN

--:

INH IBIT H

I TS4

-.; 350n5 i-: 50ns--' to-

:--350ns
r-- 50ns

-----r---L
--r-1-

---:;---+--

150 ns --,
to- 1
1 -.I
-90to150ns
STROBE H ~
_ - . . . L I_ _ _! -

:-- 0 to 50 nsec

WRITEH
::
~
Unless otherwise noted all times above
are + or - 10 nsec.

STROBEH~
~90 t0200ns~

Figure 3-8

WRITE

- 9 0 to 110 n s -

Figure 3-9

TP3 Timing During lOT Transfer

Memory Timing

3.8.3
Relationship Between CPU and Memory Timing
The timing relationship between the (read) CPU and memory is shown in Figures 3-10 (Read) and 3-11 (Write).
MO<O: 11 >L changes at TP2 H only if MO OIR L is allowed to go high. If MO OIR L remains low, MD<O: 11 >L is
settled on bus at STROBE H leading edge +250 ns.
The times given take into consideration the type of load on MO<0:11>L, EMA<0:2>L and MA<0:11>L and its
position, plus maximum bus capacitance.
TP4H~~_ _ _ _ _ _ __

Ioo--A-oot
ROM ADDRESS L.- -

USER MODE L OLD

I * LSETTLED (I NCLUDES BUS CHARGE TIME)
-tr--25ns MINIMUM

SOURCEH

r---j~

-oot

_ _ ___
EMA,MA, -

t--IOOns MINIMUM

-- -

TP2H

r-l~

MD<O:l1>L - - - - - - - -

I NH I BI T H

1---120 ns MAXIMUM

r---l--;-----I 0 I *
NEW

120n$ min

'II

MDDIRL

------j

20to150ns

MD < 0;11 >L ----------4--+--------------

New Memory Data on bus - - - - - 1 . 1

* Uncertain

--------.1

MD<O.l1> changes at TP2 H only if MD DIR L is
allowed to go high. If MD OIR L remains low MD <0.11 >
is settled or. the bus at STROBE H leading edge + 250ns

* Uncertain
A = 250 ns

Figure 3-10

r----1L.._________

I
I

OLD
Clear all memories at leading-----l
edge of SOURCE H

NEW Memory Data settled

___________

I-B'1

STROBE H _______--'il'-_________
---I

____________ _

ROMADDRESL~S=T~AB~L~E~F=R70M~P7RE~V~10~U-S-R~E-A-D------

EMA<0:2>L --;:-:-:--1 ~
MA<O:II>L
OLD 1* SETTLED(INCLUDES BUS CHARGE)

Figure 3-11

Memory Timing

Write Timing

3.8.4 Basic I/O Timing
The Basic liD timing in Figure 3-12 assumes the following:
1.

Single transfer during lOT

No modification of PC (no connection to C2)L

C<O: 1> L do not go to ground and then positive between the falling edge of liD PAUSE L and the rising edge of TP3 H.

The peripheral must place its data on DATA<O: 11 >L and assert any C lines at least 250 ns prior to TP3 H. SKIP L
must be asserted at least 100 ns before TP3 H if a skip is to occur. Peripheral registers are loaded at the leading
edge of TP3 H. Peripheral registers must be edge-triggered, since DATA<O: 11 >L may start to change before TP3
H goes low again.
The timing for the CAF instruction is shown in Figure 3-13.

3-22

3.8.5 Expanded I/O Timing
The restrictions of Paragraph 3.8.4 regarding single transfer and limited use of C<O:2>L do not apply.
The timing required to stop the CPU (this operation is not confined to lOTs) using NOT LAST XFER L is shown in
Figure 3-14.
TP3 H ~'--_ _ _ _ _ _ _ __
-001 I--- 20 ns min

IN ITIALI ZE H
STROBEH~

--.J
~300

to 900ns----l
(Never extends to next TP3 HI

____________________________

M 0 < 0: 11 >L :.-_-_ _
- _--.,-_ _
- _ _ _._-___
- _-_-__
- _-_-_-_-_-_ _
- _-_-__
- _-___
-_-_-_-_-

UNCERTAIN

lOT

I/O PAUSE L

Figure 3-13

C A F Instruction Timing

~----A------~IB~

TP2H ____________~r!~

___________________

TP3H _____________________~~ _______
TP3H _ _ _ _ _ _~rl~

-------- -------

DATA <0: 11 >L --+----ii-------II----+--------t--+-----Break
Depends on
IIAC
Indicator
Priority
C<O: 1> L
information
Dimension A = 450 to 550 nsec
Dimension B = 50 nsee minimum
100 nsee maximum
.... Uncertain

Figure 3-12

-toi

NOT LAST _ _ _ _ _-,
XFER L

____

I-- 100 ns min
--01 t-- 20 ns min

;-------

Figure 3-14 Timing to Stop CPU
Using Not Last XFER L

Basic 1/0 Timing

Figure 3-15 shows the timing required to make transfers to or from the AC. or to the PC.
Peripheral data registers should be edge-triggered and loaded at the leading edge of BUS STROBE L (since the contents of the Data Bus may change as a result of sending BUS STROBE L to the CPU).
External loading of LI N K must take place only in an expanded I/O cycle. and not at restart time. Figure 3-16 shows
the timing for this operation.
I

DATA<0;11>L

---- - - - - jI - - - I

C<0:1>L

-7-----------

I PERIPHERAL DATA*

I--- 300n5 min~

LINK DATA L - -

r--Defined
II
r--- 450 ns min -----.! '---20ns
I

LINK

C2L-----------LI--BUS STROBE L
(perl pheral - generated)
I
I

---------....;LJ-90-150 nS--4I

- - - - - - r - -.lbus information :
--t 150ns minimum _
20 ns minlmum _ _

LOADL-------~

90ns min --, 1 - 20 to 150 ns ---.J ::--LI NK L ______________.....:..____

OLD

'If required for input transfer. The 350 ns
includes 100 ns for charging tha bus.

Figure 3-15

Transfer Timing

Figure 3-16

NEW

External Loading of Link Timing

Figure 3-17 shows the timing to restart the CPU after the peripheral has completed its data transfers. Loading LI N K
is not allowed during this operation because of timing restrictions as the CPU leaves TS3.
3.8.6 Data Break Timing
The timing required to initiate a data break is shown in Figure 3-18. These signals are controlled by the device making the break request.
3.8.6.1
Data Exchange - The data exchange timing is shown in Figure 3-19. Data to be placed in memory or
used to modify memory must be in a register which has been loaded prior to TP1 H.
3.8.6.2

Final Operations - The timing required to end a data break transfer is shown in Figure 3-20.

3-23

INT STROBE H
NOT LAST XFER L - - ' r - - - - - - - - - -

............ 20 nsec
BRKINPROGL--~~-_-_-_-_-_-_-_I-!

--I 200n~I~~nlmum t-- (INCLUDES BUS
CHARGE TIME)

BUS STROBE Lit

~I_ _ _ _ _ _ _ __

pr~~~~t~~ -..:.....----:...___-__
I i;..,ll 50 nsec min.

INTSTROBEH~

.... ,50ns min---l
TP4H _ _ _ _ _ _ _ _~r_l~_ _ _ _ _ __

90 to 200 nsec ---I
I-Oto 50 ns - - - - i 1.--

r6T1

_____________

L.. _ _ _ _

CPMA DIS l

90 to 150 nsec - - t 1-20 to 100 ns - - - I !.--

I/O rtfU

- I I ' -____________

MA<O:">L -

- -

-,- -

- -

r - I- - - -

Old MA
: Break EMA and MA on bus
50 ns m a x --ej too-

DISA~tEI~ --------...,~I-_-_-_-__l':_-----

20 tol00ns----ool

Tlmeo,s~~~ --------+1---TS3

20 ns min -ej ' - :
lOOns min......,
TP1H ____________________

TS4

"This BUS STROBE L i. generated by the
controlling peripheral, and causes a data
transfer. The setup time requirements for
C(O:2)L and DATA(O:ll)L must be met.

Figure 3-17

t--

MA,MS LOAD CONT L
Must be low 20nsec
before next TP4 H
leading edge,

Figure 3-18

CPU Restart Timing

Data Break Timing

BRK IN PROG L _ _ _- - Jl _____ ...:

--! .... 20ns min
INT STROBE H -----~f'

____________
TP2 ________________
_____
TPl _ _ _ _~r-l~

TP4H

~!l~

DATA<0:11 >L - - -

250ns mln---f
- - - - - - 1- -

TPIH

-It-

,
1

~------

10---

CPMA DIS L - - - - '......
'I- - - - _J
-I 1-20n5 min -eI*,..
I
--t .....-20n8 min I
MStIR DISABLE L ____________- - ' _ _ J
I

Break device - - t
doto settled on bus

lOOns min*--f .....

OVERFLOW L

--In

TP3 H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

BREAK DATA CONT L must b'e settled on
bus at same time as Input data.

Figure 3-19

MA, M S LOA 0 CON T L - - - - - - - - - - - - - - - - -.....'
20 ns min -.l I.-

'Including bus charge time.

Figure 3-20

Data Exchange Timing

MA,MS LOAD CONT L
must be high 20nsec
prior to TP4 H

End of Data Break Timing

3.8.7 CPU Major States
The timing for the Major State of the CPU is shown in Figure 3-21.
3.8.7.1

IR (FETCH Cycle) - The timing for a FETCH cycle is shown in Figure 3-22.

TP2 H _ _ _~n~

TP4 H - - I " " L . --t
t-- 20 to 150 nsec
F L, D L, D L - - - - - - - - - - - - OLD
I NEW

-I
I-- 20 to 150 nsec
IR<0:2>L - - - - - - - - - - - - - - -

-r

F SET L ---~O~L-=D----i~-:-N~E7':'W:--:-(o-r not va I I d

F SET L

If FETCH)

Figure 3-21

3.8.7.2

______

NOT VALID

CPU Major States Timing

I-- 40 to 200nsec

--------i----

Figure 3-22

NEW

FETCH Cycle Timing

Interrupt Recognition - The timing associated with interrupt recognition is shown in Figure 3-23.

3.8.8 Timing Start and Stop
The timing for starting and stopping the CPU is shown in Figures 3-24 and 3-25.

3-24

START

MEMSTARTL~
-t
RUN L

INT STROBE H _--Fl'--_ _ _ _ _ _ _ __

--t 350 to 450 ns r--first TPI H _ _ _ _ _ _---'~

-I I- 50 n's minimum to be recognized
INT RQST L 11-_ _ _ _ _ _ _ _ _ __
INT IN PROG H ~ ___

t-- 90 to 400ns

--' I--- 20 to lOOns
--,

Ltf

--II- 20 to 150 nsec

Figure 3-24

t-- 40 to 200 ns
F SET L

Start Timing

----~II~_ __

40 to 200 ns---l
TP4H _ _ _ _ _ _ _~I1~

______

STOP
STOP L

20 to 150 nsec -_._----------Major states, IR
Prev i ous Stat e

--001 t-- 50 ns min
TP3H~
--I I-- 20 to 150 ns
RUN L
I
TP4H _ _ _ _ _ _ _ _ _ _~~

JMS and EXECUTE

'GoeJ low at JMS and EXECUTE and INT STROBE.

Figure 3-23

----,1-._________

Interrupt Timing

TSI L

~
CPU stopped - - e l

Figure 3-25

Stop Timing

3.9 ASYNCHRONOUS SIGNALS
The following signals are allowed to change asynchronously with respect to the CPU's timing chain:
POWER OK H (when negated also causes INITIALIZE H to change)
SW
IND1 L
IND2 L
INT RQST L
STOP L

3.10 SPECIAL SIGNALS
The following signals should be asserted only when the CPU is not running:
MEM START L (Paragraph 3.7.9.2)
PULSE LA H (90 ns min width positive pulse)

3.11

ELECTRICAL CHARACTERISTICS AND INTERFACING

3.11.1
Logic Levels
Low = -0.5 V to +0.4 V
High = +3.0 V to + 5.0 V.
3.11.2 Bus Loads
All bus load resistors are on the CPU module (instead of at the end of the bus) and the resistors are returned to + 5
Vdc. The Omnibus is restricted to 12 slots and may not be extended. Maximum bus capacitance is limited to 150 pF
of which 30 pF is caused by the 12 slot bus and connectors.
3.11.3 Driving the Omnibus
Table 3-2 is a list of Omnibus signals. their load type. if they must sink. drivers. and number of inputs. The load type
(1 through 6). and type of driver (OC. TRI. and UTI) are defined at the end of Table 3-2,

3-25

Table 3-2
Load Resistor and Drivers Summary
Signal

Load Type

BREAK CYCLE L
BREAK DATA CONT L
BRK IN PROG L
BUS STROBE L
CO L
C1 L
C2 L
CPMA DISABLE L
DL
DATA 0 L
DATA 1 L
DATA 2 L
DATA 3 L
DATA 4 L
DATA 5 L
DATA 6 L
DATA 7 L
DATA 8 L
DATA 9 L
DATA 10 L
DATA 11 L
EL
EMAO L
EMA1 L
EMA2 L
FL
FSET L
IND1 L
IND2 L
INHIBIT H
INITIALIZE H
INT IN PROG H
INT RQST L
INTSTROBE H
INTERNAL I/O L
I/O PAUSE L
IRO L
IR1 L
IR2 L
KEY CONTROL L
LA ENABLE L
LINK DATA L
LINK L
LINK LOAD L
MAO L
MA 1 L
MA2 L

1
1
1
6
1
1
1
1
1*
2
2
2
2
2
2
2
2
2
2
2
2
1*
2
2
2
1*
1
1
1
5
3
2
1
4
1
5
1*
1*
1*
1
1
1
1
6
2*
2*
2*

Driver Must Sink (mA)

Drivers

Number of
Inputs (TTL)

16
16

----

1-0C

1/2

----

1-0C

16
16
16
16
30
16
16
16
16
16
16
16
16
16
16
16
16
30
30
30
30
30
Do not drive TTL output
16
16
Do not drive TIL output
See Note 1
16
16
Do not drive TTL output
16
Do not drive TTL output
16
16
16
16
16
16
Do not drive
60
30
30
30

----

2
1/2
1/2
1/2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4

3-26

-------

---TRI
3-0C
2-0C
3-0C
2-0C
3-0C
2-0C
2-0C
2-0C
2-0C
2-0C
2-0C
2-0C
TRI

----------

-------

TRI
1-0C

----

1
1

---1-TTL
E.F.
2-0C

---TTL
1-0C
TTL
TRI
TRI
TRI
1-0C
1-0C
1-0C
1-0C
1-0C
TRI
TRI
TRI

---------1-UTI
4 1/2
1-UTI

------1
1/2
1/2
1/2
1 1/2
21/2
1

---1
1
1
1

T@ble 3-2 (Cont)
Load Resistor and Drivers Summary
Signal

Load Type

Driver Must Sink (mA)

Drivers

MA3 L
MA4 L
MA5 L
MA6 L
MA 7 L
MA8 L
MA9 L
MA 10 L
MA 11 L
MA, MS LOAD CONT L
MD 0 L
MD 1 L
MD 2 L
MD 3 L
MD4 L
MD 5 L
MD6 L
MD 7 L
MD 8 L
MD 9 L
MD 10 L
MDllL
MD DIR L
MEM START L
MS IR DISABLE L
NOT LAST XFER L
NTS STALL L
OVERFLOW l
POWER OK H
PULSE LA H
RES
RETURN H
ROM ADDRESS L
RUN L
SKIP L
SOURCE H
STOP L
STROBE H
SW
TP1 H
TP2 H
TP3 H
TP4 H
TS1 L

2*
2*
2*
2*
2*
2*
2*
2*
2*
1
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
2
2
1
1
2
1

30
30
30
30
30
30
30
30
30
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Do not drive
See Note 2
See Note 2
16
Do not drive TTL output
30
Do not drive TTL output
16
Do not drive TTL output
16
Do not drive TTL output

TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI

-3
1
5
2

-1
5
1
5
2
4
4
4
4
5

----

1
1
1
1
1
1
1
1
1
1
4
4
4
4
2 1/2
4
31/2
3112
31/2
21/2
31/2
3
1
2
1
3
1

1-0C

----

l-UTI
1

---TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
1-0C
1-0C
1-0C

----

------TTL

* Active pull-up when CPU tristate drivers are enabled.

3-27

-------

----

TTL

----

---TTL
3-0C
TTL

---Do not drive TTL output
Do not drive TTL output
Do not drive TTL output
Do not drive TTL output
Do not drive TTL output

Number of
Inputs (TTL)

TTL
TTL
TTL
TTL
TTL

---2

---------3
7

---1

Table 3-2 (Cont)
Load Resistor and Drivers Summary
Signal

TS2 L
TS3 L
TS4 L
USER MODE L
WRITE H

Load Type

5
5
5
1
5

Driver Must Sink (mA)

Drivers

Do not drive TTL output
Do not drive TTL output
Do not drive TTL output
16
Do not drive TTL output

TTL
TTL
TTL

---TTL

Number of
Inputs (TTL)

---3

21/2
2
1

NOTES
1.

INITIALIZE H and PULSE LA H. Driver must supply 30 rnA at +3 V, and source less than 1 rnA at ground.
An emitter follower is recommended. Typical circuit is shown in Figure 3-26.

POWER OK H. This line is driven high by circuitry within the power supply, but can be grounded by
options (such as the bootstrap loaders) which need to initialize the CPU and memory extension MA Control
flip-flops. The power supply driver must supply a minimum of 30 rnA at +3 V, and must not supply more
than 100 rnA when the output is shorted to ground. Peripheral drivers must sink 200 rnA at 0.4 V, and sink
less than 1 rnA leakage at +5 V.

The DEC 8881 (PIN 19-09705) will meet the 16 and 30 rnA requirement. Two 8881's in parallel will meet
the 60 rnA requirement.
'
LOAD 1: 470 n to +5 V, Clamp to +3 V.
LOAD 2: 390 n to +5 V, Clamp to +3 V.
LOAD 3: 2-470 n in series to -15 V, Clamp diode with anode ground.
LOAD 4: 390 n to +5 V, ferrite bead in series with pin to limit rise time.
LOAD 5: 390 n to +5 V, series ferrite bead , Clamp to +3 V on "finger" side of ferrite bead.
LOAD 6: 150 n to +5 V, Clamp to +3 V.
TRI = Tristate driver
UTI = Utilogic input (SIGNETICS 314 , 380, 384 or equivalent)
OC = Open collector

3.12 DRIVE AVAILABLE FOR PERIPHERALS
Table 3-3 lists the currents that are available for driving options. memories. etc. from the CPU and memory extension. Signals marked * are generally not used as output from CPU or memory extension.
3.13 RECEIVERS AND LOAD RELIEF TECHNIQUES
The use of Utilogic gates (Signetics SP314. SP380. etc) or other high impedance circuits as bus receivers is strongly
recommended. These gates have high threshold and low input drive. and thus present maximum noise immunity
while introducing minimum bus reflections. Since 10 mA is available only on CPU timing and memory timing signals,
buffering and load relief techniques must be used to decrease loading on the Omnibus.
A typical liD decoder is shown in Figure 3-26. Note the use of buffered liD PAUSE L. This signal keeps the M D receivers from loading the M D lines. since buffered liD PAUSE L supplies all needed base current to the three gates
on the M D lines unless liD PAUSE L is low. Similar techniques should be employed for signals from
DATA <0: 11 > L to peripherals.

3-28

Table 3-3
Omnibus Signal Drive Currents
Signal
BREAK CYCLE L
BREAK DATA CONT L
BRK IN PROG L
BUS STROBE L
C<O:2>L
CPMA DISABLE L
DL
DATA<O:ll>L
EL
EMA<0:2>L
FL
FSET L
INDl L
IND2 L
INHIBIT H
INITIALIZE H
INT IN PROG H
INT RQST L
INT STROBE H
INTERNAL I/O
I/O PAUSE L
IR<O:2>L
KEY CONTROL L
LA ENABLE L
LINK DATA L
LINK L
LINK LOAD L
MA<O:ll>L
MA, MS LOAD CONT L
MD<O:ll>L
MD DIR L
MEM START L
MS, IR DISABLE L
NOT LAST XFER L
NTS STALL L
OVERFLOW L
RES
RETURN H
ROM ADDRESS L
RUN L
SKIP L
SOURCE H
STOP L
STROBE H
TP<1:4>H
TS<1:4>L
USER MODE L
WRITE H

Source rnA @+3

Sink rnA@GND

3
3
3

5
5
5

*
*
*

3
3
3
5

*
*

10
10
2

'10

3
2

3
3
3

*
*
*
*

5
5

Depends on driver
10

3
5

3-29

10
10
10

10
10 Each
10 Each

380
MD3 L

MD4 L
380

314

MD5L

DEVICE 17

MD6L
MD7L
MD8 L

I/O PAUSE L

-----01
08-12!17

Figure 3-26

3.14

Typical liD Decoder

INTERFACE EXAMPLES

This section provides the user with interface examples and timing for Programmed liD, Interrupt, and Data Break
transfers. For a more complete description of these examples refer to Chapter 9 of the Miniprocessor Handbook.
The interface examples contain some special integrated circuits. These IC's, which are listed below, were chosen to
minimize loading on the Omnibus. Do not replace them with other devices having the same function unless you have
compared input loading and threshold figures (for input devices) or output driver and leakage (for the output device).

Input Devices
Device No.

Manufacturer Type

DEC Part No.

314
380
384

SIGNETICS SP314A
SIGNETICS SP380A
SIGNETICS SP384A

19-09704
19-09485
19-09486

Output Devices
Device No.

Manufacturer Type

DEC Part No.

8881
3.14.1

19-09705

Several 7438

Programmed I/O Interface Example

The Programmed I/O Interface (Figure 3-27) that illustrates the most commonly used transfer consists of:
1.

A device selection circuit

A device operations decoder

liD control logic and

Inputloutput buffers.

3-30

T--

110 CONTROL

I
I

TP3 H

INJI~~~~§

{

TO SET
FLAG

7474
FLAG

CLEAR FLAG
+3V

I
I

1+5-V-~~

--i

OPERATIONS DECODER
-

I
INT

RQST

I
I

I
SKIP L

+3V
OUTPUT
BUFFER

+---a

DM::c..
1_ _
L _:::.

BIT 11

DATA 10 L DUl -

+3V

I
I
I

DATA 9 L D51-

M011 0 _::.:.DP1-'--_-+_<1

DATA 8L DR1-

DATA 7 L BVl -

r--

I
I
I
I

--- - -

DEVICE SELECTOR

--- ---

SAME
CIRCUITRY
AS BITS

---

DATA 6 L BUl -

APl

MD3 L

AND
11

DATA 5L BS1-

M05 L

INPUT
BUFFER

DATA 4L BR1BPl

M01 L

BIT"

BKl

M04 L

DATA 2L AU1+3V
DATA 1L AS1-

I
I
I

MOB L

DATA I1i L AR1----~-a

AA2, BA2, CA2

+15 Vdc

DA2
AB2, BB2, CB2, DB2

I
I
I
I
~
08-1057

'DON'T WORRY ABOUT GROUND LOOPS,
MAKE LOTS OF GROUND CONNECTIONS

AC1, AC2, AF1, AF2,
AN1, AN2, ATl, AT2,
BC1, BC2, BF1, BF2,
Gcound'

+3V

I
I
-.--.L _________ _

CDl

+5 Vdc
-15 Vdc

L-'_
I

DKl

PAUSE L

OUTPUT BUFFER BIT 0

BMl

I/O

I
DEVICE
DATA"
IN

DATA 3L AV1-

M06 L

DEVICE

CONNECTOR I
DEVICE
DATA 11

+ 3V

DATA 11 L D V 1 - - - - _ - - q

MID

INPUT

I
I

:;~,ER

M09 L _.:.:DL:.:...'_ _+-47_0-Q

.-________________~I ____~

DEVICE INTERNAL
CLOCK PULSE

+3V

~-------~--~r-~

---,

INPUT I OUTPUT BUFFERS

BN1, BN2, BTl, BT2,
CC1, CC2, CF " CF2,
CN1, CN2, CTl, CT2,
DC1, DC2, DF " DF2,
ON " ON2, OT " OT2

Figure 3-27

Sample Programmed liD Interface

Device Selection Circuit - MD3-8 bits are used to carry the device select information. The example in Figure 3-27
shows the DEC380 and DEC314 being used as a simple device select and operations decoder. When octal 52 is received and signal I/O PAUSE L is asserted by the processor. gate 314 is qualified. The output is used to assert signals INTERNAL I/O L and MY DEVICE L. No operation can occur unless signal MY DEVICE L is asserted by the
device selection decoder.
Operations Decoder - M 09-11 bits determine the type of operation to be performed. Three DEC380's are shown
(Figure 3-27) receivinr these bits. The outputs of these gates are in turn presented to a binary-to-octal decoder type
8251 and the decoded results control the interface. The lOTs in Table 3-4 illustrate the various types of transfers
available.

Table 3·4

lOTs For Sample Interface
lOT

Function

6520
6521
6522
6523
6524
6525
6526
6527

Not used.
Transfer content of the AC to the output buffer.
Clear the AC.
Transfer the content of the AC to the output buffer and clear the AC.
Transfer the content of the input buffer to the AC (OR transfer).
Clear the flag.
Transfer the content of the input buffer to the AC (jam transfer)'
Skip if flag is set (1).

3.14.2
Flag Logic
The flag is represented as a 7474 D-type flip-flop. The C and 0 inputs are used by the peripheral device to set the
flag. If the flag is an input flag. it is set when data is loaded into the input holding register. If the flag is an output
flag. it is set when the data in the output holding register has been processed by the peripheral. (i.e .. when new data
may be loaded into the output register without disturbing the output devices operation). Two flags are required for
both input and output transfers.
3.14.3
Interrupt Request
The basic I/O interface may also be used to perform interrupt transfers by adding a gate to assert the interrupt
request line when a flag is set by an external signal (Figure 3-25). The processor responds to the INT ROST line by
completing the current instruction and then executing a JMS to location O. Simultaneously. the interrupt system is
turned off. The execution of the JMS instruction saves the current program count in location O. It is up to the program to identify the interrupting device by polling (testing) device flags sequentially. After the device has been serviced. the interrupt service routine returns to the main program with a JMP indirect instruction. It is a good idea to
have an interrupt gate in the logic even if the interrupt system is not going to be used. There is no penality for adding this gate because the CPU will not respond to the state of INT ROST unless the interrupt system is enabled or
an SRO instruction is fetched. Including this gate allows the user to recode the program for interrupt without changing the hardware.
3.14.4 Output Buffer
The output buffer receives processor data during lOT instructions and outputs data to a device under control of device timing. This buffer must be a D-type (edge-triggered) register. The command signal that loads the output buffer
also initiates action within the peripheral. The output flag should be cleared at or before the time this buffer is
loaded and should not be set again until the device has completely processed the data word.

3-32

3.14.5

Input Buffer

The input buffer receives device data at the device timing and applies the data to the data bus during an lOT instruction. The same signal that loads the input buffer is often used to set the input flag.
3.14.6

I/O Control

The I/O control includes INT ROST, which immediately responds when the flag is set; SKIP, which is asserted when
lOT 6527 is decoded and the flag is set; CO and C1, which may be asserted by the operations decoder during various conditions of data transfer; and input/output enabling logic, which responds to the operations decoder and controls the I/O buffers (Table 3-5).
3.14.7
Input/Output Timing for Programmed I/O Interfaces
A timing diagram corresponding to the programmed I/O interface example is illustrated in Figure 3-28. An explanation of the time periods from A to J is:
Period

Time

Function

A--D & E--J

350 ns

Time required to perform the transfer (PAUSE).

A--S & E--F

70ns

Time required to decode the device selection and assert INTERNAL I/O.

A--C & E--H

100 ns

Time required to decode the lOT and assert the necessary "c" lines or SKIP
and supply data if needed.

D&J

Note:

The time when the transfer takes place. Note that the data bus will change at
this time. This is the reason that edge triggering must be used.
The C lines control the direction of data transfer.

3.15 PROGRAM INTERRUPT TRANSFERS
The main difference between Programmed Interrupt transfers and Programmed I/O transfers is the software required.
Chapter 6, Introduction to Programming, contains a thorough discussion of software for the interrupt system.
The hardware required for Interrupt transfers is the same as already described under Programmed I/O tranfers, except the gate driving INT ROST L is required.
3.15.1
Interrupt Timing
Within each lOT, timing is the same as that already described for Programmed I/O transfers. Since several devices
may be simultaneously active using the interrupt system, the speed of response of the interrupt system is of interest.
The state of the interrupt system is sampled 350 ns before the end of every machine cycle. If a device requests an
interrupt, the CPU will start executing the J MS to location 0, a maximum of 3 machine cycles plus 450 ns after
receipt of the request. The JMS to location 0 takes one machine cycle, and the interrupt system is disabled in that
same machine cycle. From this point on, the response time of the interrupt system depends on the instruction sequence of the interrupt handler. A typical interrupt handler program requires about 40 machine cycles to completely
handle an interrupt. In critical cases, the user should count up the maximum number of machine cycles that can occur with the interrupt system disabled.
3.1 5.2
Data Break Interface Example
The basic break interface required to transfer data consists of a Break Memory Address register (BKMA) to address
memory independently of the processor; a Break Priority Network to assure the activation of the device with the
highest priority; Input/Output Buffers, and Break Control Logic. A sample data break interface is illustrated in Figure
3-29. The data break sequence of events is described in terms of the primary data break control signals and the processor timing given in Paragraph 3.7.5.

3-33

Table 3-5
Transfer Control Signals
Bus Set-up
Time with
Respect to
BUS
STROBE

Action
Required by
Peripheral at
Interface

Action by
Processor

Contents of
Data Bus
During Transfer

AC Register

280 ns

Load data bus
into buffer.

Transfers AC to
Data Bus. AC remains unchanged.

AC register only. User modification of this type of transfer may
bring undesirable results.

AC Register

280 ns

Ground CO.

Transfers AC to
Data Bus and
clears AC.

AC Register.

Type of
Transfer

Transfer
Control Lines
*CO
*C1

Information
Gated Onto the
Data Bus

Output AC
Data Bus.
ACunchanged.

Output AC
DATA Bus

AC Cleared

Load data bus
into buffer.

Input AC
Peripheral
Data

Peripheral Data
and content of
AC Register.

280 ns

Gate peripheral
data to data bus.
Ground C1.

Transfers content
of AC to the Data
Bus. The ORed
result loaded into
the AC.

AC ORed with Peripheral Data.

Input Jam.
Data Bus
AC.

Peripheral Data

280 ns

Gate peripheral
data to data bus.
Ground CO and
C1.

Transfer data bus
to AC Register.

Peripheral Data.

*CO is connected to pin CE 1. C 1 is connected to pin CH 1 on the Omnibus.

TSI
TSI

TPl

TS2 L

TP2.H

TP2 H

TS3 L

TP3 H

TS4 L
H

L-.r-t

...r-L

TP4

lOW IF CLA

I
I

NOT USED FOR OUTPUT OR SKIP
I

I
I
I

IN I AT RS

I I PRIORITIES

I
I

HANGING

12/3/5/7

INTERNAL
IIO L

I
I

I
A----l

DATA
BUS

I INDICATORS

MD
BUS

I
I
I

INTERNAL
I/O L

L W IF sKIP

SKIP L

I
I

SKIP L

lAC

B----'

CHANGING

IOT 652

NOT USED

I
I

F---.J

I
I
I

AC- OUTPUT BUFFER

6522

0_AC

6523

AC-OUTPUT BUFFER,O-AC

6525

0-FLAG

6527

SKIP IF FLAG IS SET

I
I
I

INPUT TRANSFER
IOT

6521

OUTPUT TRANSFER OR SKIP
ACTION

:4/6

I
E-.-l

I
I

rOT

I
I

PRIORITIES

I
I
I

I
I

I DATA-AC
I

I
I

OT 652
I

I
I
I

I
I

AC
I

MD
BUS

LOW IF CLA

Cl L

----..lL

I
I

C0 L

I
I

r-.

TS4 L

PAUSE L

C0 L

DATA
BUS

IIO

IIO PAUSE L
Cl

TPI H

TP4

L-

6524
6526

ACTION

INPUT BUFFER AC-AC (OR)
INPUT BUFFER -AC

~----

(JAM)

REFER TO APPENDIX D FOR OMNIBUS PIN NUMBERS FOR SIGNALS

Figure 3-28

3.15.3

Timing for Sample Programmed 1/0

Data Break Timing

The important timing consideration in data break (Figure 3-30). as in program interrupt. is whether sufficient time is
available from the time the flag (in this case. the break request) is set to the time the data is moved in or out of
memory. The PDP-8/A honors break requests between major states of an instruction. The break system is synchronized 350 ns before the end of every memory cycle. At the same time the processor tests for the possibility of interrupt. it tests for the possibility of break. The break system takes precedence over interrupts. Assuming no
extendedllO the processor requires no more than 1 memory cycle +400 ns to recognize a break request.
As a rule. the user should assign highest priority to the device that has data available for the shortest amount of
time. The user should assume that all devices request data breaks simultaneously and calculate the response time of
the break system as seen by each device to ensure that response time is less than the maximum allowable for thClt
device.

3-35

,I
I
I

1----1\-

EIU.OLA02.

EMA21.AN2 MAOLADI

r"A'~ 2i

I
I
I

A£

I
I

ADD 4

TP'H~

.. - - - _..

ADOIQ

_-_ ..,.-

"'5.'111

DIS L c. . ,

~e.CVCLEL.L2

ADO U-..J

II
I

Q')

_ _ _ _ _ _ _ _ _ ...1
BKIN
PROG L BE2

RE .... 'NOEII OF OMNIBUS PINS NEEMD FOR THIS INTERFACE

OAT. 51.. 1M
0..,1A 4L 8M

0.4.T.. 61. iitH
OOA 71. ItVl

OAT" '*- OS,
[)«fA 10L OUI

+SV"'AZ,8A2,CA2
+1SVDA2
-15'o'.I.82:,882,C82,082
eND

PINS e,F, Nt T {SIOf1 .2} OF CONNECTORS At B,C, 0
(MAKE LOTSOFORQUND CONNECTDCS-OON'T WOMY ol8OUT GAOUNDLOOPS)

Figure 3-29

Sample One Cycle Data Break Interface

T5 1 ~L_ _-11

TP1--------~r-I~---------------4I~--~r-IL--------------------~--~r-lL--------------_
T52 __________
I
I
~

TP2----------1r-lL--------ri--------~~L------+_------1r-lL----I
I

T53-------------------,

INT 5TB- TP3 ---------------~!I'---_'_I____________----'r_IL______--l-I_____________________

T54

L--_';-I--'

TP4---------------------------~Ir-l'-------------------------'~L41------------PRIORITY

l\\\\j I

----------------"~~I

BK REQUEST ~\\\\\\\\\\\\\\\\\\\\\\\\\\\~
BK IN PROG - - - - - - - - - - - - - - - - - - - - ,
CPMA DISABLE - - - - - - - - - - - - - - - - - ,

MY PRIORITY

I
I

i
I
I

MAC
MS IH DISABLE

___________________________----'1 CPMA DI5ABLED BK MA ENABLED

ilK CYCLE - - - - - - - - - - - - - - - - - - - ,

IR DISABLED

I
I

------------------~~JI-----------------------

BK D~A CONT---------------------------+:---,~LO~W'I~FAANDM~---------------4:---,------

+I---'-___

IN-----------------------------~:__~I~T~RA~N~SF~E~R~D~IR~EC~TI~ON~LA~T~CH~E~D________
I

OVFL

I SET IF ADM OVERtLOWED

I
I

Figure 3-30

3.16

I
BREAK CYCLE FOR THIS DEVICE

Data Break Control Timing Diagram

THREE-CYCLE DATA BREAK

It is possible to use memory locations as Word Count (WC) and Current Address (CA) registers by using a more complex DMA control. Figure 3-31 is a simplified diagram illustrating the interaction between the processor and a threecycle data break device. The initial set-up and exit phases include operations similar to those required for a singlecycle data break; however, the data transfer phase of a three-cycle break is divided into a WC cycle, a CA cycle, and
a data transfer cycle.
During initial set-up, the running program uses instructions to load the memory locations designated as the device
WC and CA registers, then executes lOT instructions that initialize the device and specify any necessary transfer parameters. Once the device control circuitry has been enabled, the processor is free to perform other tasks while the
peripheral accesses storage locations and executes the data break transfers.
Each three-cycle data break begins with a WC cycle during which the device gates the address of its WC register
onto the Omnibus. The address is fixed (hardwired). "and is usually an even number (bit 11 0) address. During the
word count cycle, the contents of the word count location is returned from memory and applied to one leg of the
processor's adder register. The device gates a 1 into the other adder inputs via the data bus, thereby incrementing
the word count. The resulting addition is tested for overflow while the incremented word count is restored to memory. If overflow occurs, the peripheral clears its enabling circuits and sets its device flag as soon as the current transfer has been completed. In any event. the device concludes each WC cycle by testing the data bus to determine
whether any higher priority device has entered a break request.
If there is no higher priority request on the data bus, the device immediately begins its CA cycle. The CA memory
address is usually one greater than the WC address. The CA memory location is incremented in the manner just described, and the incremented value is restored to memory and also transferred to the device break address register.
Break priority is tested again at the end of the CA cycle.

3-37

BREAK REQUEST
DISo.BLE CPU
OVERFLOW

PROCESSOR
LOGIC
L ~

r-------- 1-----,

I MEMORY

SUBROUTINE

I
I

WORD COUNT
REGISTER

I
I

L...-

f-- f-.-

ADDRESS TO
PERIPHERALS

I
I
I

PERIPHERAL
ADDRESS
DECODER

...

CURRENT
ADDRESS
REGISTER

DATA
ADDRESS

---

lOT'S

TR'!~NSFER

MA LINES

.... 1
DIRECTION

___ J

CONTROL
LOGIC

WORD COUNT
AND CURRENT

r
BIT 11 = 1 (CA REGISTER)
BIT 11 =0(WC REGISTER)

ADDRESS
. . 1 INPUT
GATES

... I

BREAK
ADDRESS
REGISTER
;

SELECTION
LOGIC

[:JJ

12-BIT CURRENT ADDRESS

....

.;ot

MB
REGISTER

12-BIT DATA

PROCESSOR

Figure 3-31

~Z
DATA
REGISTER

WIRED WORD
I COUNT ADDRESS

BIT 11 FROM
CONTROL LOGIC

DATA TO AND
FROM PERIPHERAL
3-CYCLE DATA BREAK DEVICE

Three Cycle Data Break Simplified Block Diagram

During the data transfer cycle. the peripheral generates a signal to specify the direction of the transfer. gates the contents of its break address register onto the Omnibus. and either accepts or transmits one word of data. If WC overflow did not occur during the WC cycle, the device relinquishes control of the processor and begins to prepare for
the next data transfer. When WC overflow does occur, the device flag is set and the running program executes lOT
instructions to perform any operations that may be required to terminate the block I/O process.
Chapter 5 of Introduction To Programming contains the necessary information to program a three cycle data break
device.

GENERAL CAUTIONS REGARDING INTERFACE DESIGN

3.17

Minimize capacitance on the Omnibus lines. The Omnibus will work properly only if the 100 ns allowed
for bus charge time is met. Limit wire lengths on interface modules to 6 inches per signal. In general.
this requirement means you should place bus receivers and drivers near the pins (which you will do anyway to minimize the crossovers if making a printed circuit board).

Good ground grids on interface boards are mandatory.

Observe normal TTL rules for + 5 volt bypassing. (Normal DIGITAL bypassing is 0.0 1 mfd per IC. plus a
6.8 mfd tantalum capacitor where power supply voltage enters board.)

Except when gating EMA <0: 2 > Land M D <0: 11 > L to bus (50 ns max). a peripheral has 100 ns to
react.

3-38

3.18 TRANSMISSION LINE EFFECTS
Rise-times on the Omnibus are generally long compared to propagation velocities. Hence most Omnibus signals
should be treated as capacitively-Ioaded lines.
Some signals driven by TTL drivers are a different matter entirely. These signals must be kept short (less than 1 foot)
and critical rise times controlled.
The signals which must be so treated are the nine CPU timing signals, the five memory timing signals, and 1/0
PAUSE L.
The characteristic impedance of the Omnibus itself (about 120 ohms) is a very small part of the overall picture. Of
far more importance is the value and position of the capacitive load presented by boards connected to the Omnibus.

3.19 EXTERNAL BUS
There are two additional basic techniques of receiving and sending data to the Omnibus:
1.

Using the KAS-E Positive 110 Bus Interface option.

Using the KAS-E Positive 110 Bus Interface and the KDS-E Data Break Interface.

3.19.1
Positive I/O Bus Interfacing
Previous discussions have brought out the fact that peripherals can be interfaced with either the Omnibus or the external bus. This means that a PDP-S/A user can utilize not only devices designed ex~lusively for the PDP-S/A, but
also devices originally designed for use with the PDP-S/I and PDP-S/l computers - and even devices of his own
manufacture.
This paragraph deals with the external bus, its applications, and the technique of interfacing peripherals to the bus.
Equipment that was designed for the PDP-S/I and PDP-S/l may be used by interfacing to the external bus; it can
also be used with the PDP-S/A, The user may want to transfer data between the PDP-S/A and a remote location.
The external bus, which is designed to drive long interconnecting lines, is ideally suited for this application.
This paragraph is intended to answer general question about the external bus and its relationship to the Omnibus.
For a detailed description and timing information about the KAS-E and KDS-E; refer to Volume II of the PDP-8IE
Maintenance Manual. You may obtain a copy of this manual from Digital Equipment Corporation, Communications
Services. 146 Main Street. Maynard Massachusetts, 01754.

3.19.2 The Nature of the External Bus
The external bus is a number of signal lines (SS. excluding grounds) that enable data transfers between the PDP-SIA
and peripherals. These lines carry data and control signa.ls between the peripheral and two interface boards - the
Positive 110 Bus Interface (KAS-E) and the Data Break Interface (KDS-E) that plug into the PDP-S/A Omnibus.
These two boards convert the Omnibus signals into PDP-S/I and PDP-S/l-type bus signals. For instance, PDP-S/I
peripherals need lOP pulses to perform instructions. The PDP-S/A does not generate internal lOP pulses. but it does
provide signals (M D bits 09. 10. and 11) that can be converted into lOP pulses by the Positive 110 Bus interface.
Other signals normally required by these peripherals are. in essence. available on the Omnibus. For example. BAC
(buffered accumulator) bits must be supplied for the PDP-S/I peripherals. The PDP-S/A data lines carry the necessary accumulator information. The Positive 1/0 Bus Interface merely buffers the DATA bits and. thus. provides the external bus BAC signals.
Although the external bus consists of signal lines from both the Positive 110 Bus Interface and the Data Break Interface. it is not always necessary to use both boards. When only Programmed 1/0 transfer peripherals are used. the
Positive 1/0 Bus Interface provides all the necessary signals. If data break peripherals are to be connected, both interfaces must be used. Because each data break peripheral requires its own data break interface board. the number of
signal lines comprising the bus may vary. There may be as many as 12 of these data break peripherals connected in
the system, each contributing 36 signal lines to the external bus. Figure 3-32 illustrates the bus and its use when
applied to a series of peripherals.

3-39

- -

-PDP-8/A
PROCESSOR
AND
CONTROL

OMNIBUS

- -

DATAO-il
MD 00-11
TSl
TS3
RUN
I/O PAUSE
INTERNAL I/O
TPI
TP3
INITIALIZE
CO
Cl
C2
INT RQST
BUS STROBE
NOT LAST TRANSFER:

~
~

POSITIVE
110 BUS
INTERFACE

EXTERNAL BUS
BACOo-'-'BIOP 1
BIOP2
BIOP4
BTS 3
BTS 1
B INITIALIZE 1

BMB 00-11
AC 00-11
SKIP
INT RQST
AC CLEAR
B RUN
DATA ADDRESS 00-11
BRK RQST
DATA OUT
MBINCREMENT
B BREAK
ADD ACCEPTED
B INITIALIZE 2

DATA 0-11
MAO-II
BREAK CYCLE
MA, MS LOAD CONTROL
CPMA DISABLE
MS, IR DISABLE
MD DIR
BRK DATA CONT
EMA 0-2
BRK IN PROG
OVERFLOW
MD 00-11
INITIALIZE
INT STROBE
TPI
TSI
TP2
TS2
TP4
TS4

- (12)+

(18) -'310
(12)-

- PERIPHERAL
(12)-

DEVICE

DATA
BREAK
INTERFACE

DATA 00-11
3 CYCLE
CA INC INHIBIT
EXT DATA ADD 0- 2
WC OVERFLOW

- - - - - -

(12)-

(3) -

- - - - - 08-1Z~9

Figure 3-32

Parallel Connection of Peripherals

3.19.3 External Bus Signals
Figure 3-33 shows not only the external bus signals. but also those Omnibus signals that are used by the two interfaces. Signal directions are shown for both buses. Some of the Omnibus signals - DATA 0-11. for instance - are
common to both interfaces, but for clarity this commonality has been disregarded. The external bus signals are
grouped according to the interface connector where they originate. Paragraph 3.19.4 lists the bus signals and the
connector and pin where each may be found). When similar signal lines are represented by one line of the drawing.
as BAC 00-11. the actual number of lines is indicated in parentheses. The external bus signals are discussed in detail in the following paragraph with emphasis on the relationship between these signals and the Omnibus signals.
3.19.4

External Bus Signals

3.19.4.1
BAC 00-11 - These signals represent the content of the PDP-81 A Accumulator register (AC). Information in the AC is transferred on the Omnibus data lines to the Positive 1/0 Bus Interface. The interface buffers the
signal and provides the BAC output. The BAC bits are strobed into registers in the peripheral when an lOT instruction is generated. 1 = +3 V.
3.19.4.2 AC 00-11 - The signals on these lines represent the contents of a register in the peripheral. This information is transferred to the Positive 1/0 Bus Interface where it is put on the data lines for transfer to the PDP-8/A AC.
1 = GND.

3-40

POSITIVE
110 BUS
INTERFACE

DATA BREAK
INTERFACE
NO.1

DATA BREAK
INTERFACE
NO.2

PDP-8/A

DATA
BREAK
DEVICE
\

DATA
BREAK
DEVICE

PROGRAMMED 1/0
TRANSFER DEVICES

EXTERNAL BUS

* DAISY-CHAINED WITHIN EACH DEVICE.
Figure 3-33

08-1260

External Bus Signals and Related Omnibus Signals

3.19.4.3 BMB 00-11 - The signals on these lines represent the contents of the Memory Sense registers. This information is transferred from memory on the Memory Data (M D) lines. The M D lines are monitored by the positive
I/O bus interface and the signals are converted to the BMB bits. These bits are used during lOT instructions;
BMB03-08 carry the device selection code, while BMB09-11 are converted to BIOP pulses. 1 = +3 V.
3.19.4.4 BIOP 1,2, and 4 - These pulses are generated in response to the voltage levels on MD09-11 (BIOP4-1,
respectively). These pulses generate lOT pulses within the peripheral. causing it to perform a certain operation. The
width of the BIOP pulses and the interval between pulses are variable and can be adjusted on the Positive liD Bus
Interface. Pulse = +3 V.
3.19.4.5 BTS1, BTS3 - These signals represent the TS1 and TS3 signals of the Omnibus. They synchronize operations in the peripheral with those in the computer and perform functions peculiar to the peripheral. They are primar
ily used in data break timing. Pulse = +3 V.
3.19.4.6

B RUN - If this signal is GND, the computer is executing instructions.

3.19.4.7 AC CLEAR - When this signal is asserted (brought to GND) along with the AC bits, the result is a jam
transfer of data to the AC. The signal may also be asserted by a separate lOP, clearing the AC.
3.19.4.8 SKI P - SKI P is asserted (grounded) by an lOT instruction. It causes the next sequential instruction to be
skipped. If the SKIP bus is asserted during more than one lOT of an I/O instruction, the program skips a corresponding number of instructions. No more than three skips can be made by a single instruction.
3.19.4.9 B INITIALIZE 1 - This 600 ns duration positive pulse is used to clear AC and link and to clear all flays
in peripherals. It is generated at power turn on, and by the Clear All Flags (CAF) lOT, 6007.
3.19.4.10 DATA 00-11 * - These lines transfer data from a data break peripheral to the data break interface. The
peripheral transfers the information when it receives the B BREAK signal from the interface, indicating the start of
the true break cycle. At TS2 of this break cycle, the data break interface transfers the data to the Omnibus DATA 0
11 lines, which carry the data to the PDP-8/A memory buffer. 1 = GND .

• Pertains to DATA Break interface only.

3-41

3.19.4.11
B BREAK * - This signal is generated in the data break interface and transferred to the peripheral, where
it enables a parallel loading of data. either into or out of the peripheral. The data break interface. in addition to generating B BREAK. asserts the Omnibus BREAK CYCLE line. notifying the computer that the break cycle has begun. 1
= GND.
3.19.4.12 DATA OUT* - This signal is produced by the peripheral and sampled by the data break interface. When
DATA OUT is asserted (grounded) during the break cycle. data is transferred from the computer's memory to the
peripheral.
3.19.4.13 DATA ADD 00-11 * - These lines transfer address information from the peripheral to the OMNIBUS MA
lines. If the peripheral is a 3-cycle break device. the address represents the memory location of the word count.
Since this location is always the same for a 3-cycle device. the DATA ADDRESS lines are hard-wired in the peripheral. This address must be even (ending in O. 2. 4. or 6) for word count. The data stored in this location represents the 2's complement of the number of data words to be transferred. The next sequential location is read from
memory as the Current Address register.
The data stored in this location represents the memory address of the data to be transferred. If the peripheral is a 1cycle break device. the address on the DATA ADDRESS lines is provided by a register in the peripheral and represents the memory address of the data to be transferred. The address on the DATA ADDRESS lines is sampled by
the TP4 pulse. The OMNIBUS CPMA DISABLE line is asserted by the data bFeak interface at TP4 to enable the
DATA ADDRESS information to be placed on the MA lines. 1 = GND.
3.19.4.14 BR K RQST* - This signal is asserted (brought to ground) by the peripheral when it is ready for a word
transfer. When BRK RQST is present at INT STROBE time. the data break operation is entered. The OMNIBUS INT
IN PROG line is asserted. and a load enable signal is provided for the data break interface break memory address
(BKMA) register.
3.19.4.15 ADD ACCEPTED* - This signal is generated by the data break interface when a BRK RQST signal has
initiated the data break operation. ADD ACCEPTED is used in the peripheral to clear the BRK RQST flip-flop. Pulse
= GND.
3.19.4.16 MB I NCR EM ENT* - When this signal is at ground level during the true break cycle. the contents of the
memory location are acted upon as outlined in the following table.

MB Increment

Data Out

Operation Performed

Low

Contents of the memory location
are incremented.

MB INC

Low

High

Data on the DATA 00-11 lines
is added to the contents of the
memory location.

Add to Memory (ADM)

Descriptive Term
Used for Operation

3.19.4.17 CA INCREMENT INH* - When this signal is asserted (grounded) during the CA cycle of a 3-cycle data
break. the CA is not incremented.
3.19.4.18 3 CYCLE * - This signal is transferred from the peripheral to the data break interface to notify the interface logic to set either the WC flip-flop (3-cyciB transfer) (ground input) or the B flip-flop (1-cycle transfer).
3.19.4.19 WC OVER FLOW* - The interface transfers this signal to the peripheral to notify it that the word count
location in memory has become zero and that the data transfer should end. The signal is also present when overflow
occurs during MB increment or ADM. Pulse = GND .
• Pertains to DATA Break interface only.

3-42

3.19.4.20 EXT DATA ADD 0-2 * - These three lines are used when a KM8-AA Memory Extension and Timeshare.
interface is included in the basic PDP-8/A. The peripheral uses the lines to indicate the particular memory field involved in the transfer.4
During a 3-cycle data break, WC and CA cycles always occur in field 0, while only the B cycle occurs in the field
specified by the extended data address. 1 = GN D.
3.19.4.21
BIN ITIALIZE 2 * - This positive signal clears all flags in the peripheral and is essentially the IN ITIA LlZE
signal of the Omnibus. It is used by the break device in lieu of B INITIALIZE 1 to reduce loading on the latter.
* Pertains to Data Break interface only.

3-43

CHAPTER 4
CENTRAL PROCESSOR UNIT

4.1 CENTRAL PROCESSOR UNIT, GENERAL DESCRIPTION
The detailed description of the central processor unit (CPU) relies on logic drawings extracted from the complete set of
drawings and schematics that appear in Appendix H. The extracted drawings are functional and often comprise logic from
more than one sheet of the complete set. Generally, the extracts do not include integrated circuit pin numbers; these can
be found in the print set. Appendix H also contains flow diagrams that relate to the significant CPU operations. Become
familiar with these flow diagrams; they not only describe the overall CPU operation concisely, but also help you understand difficult areas in the detailed logic descriptions.
The CPU manipulates data in response to a predetemined sequence of instructions. In the PDP-8/A both the data
and the instructions are stored in memory. An instruction is brought from memory to the processor where it is decoded to determine, first. what to do to the data, and second, what data is affected. When the data has been manipulated, the result is stored within the processor, transferred to a memory location. or transferred to some peripheral
equipment.
The CPU logic is contained on a hex-size printed circuit board that plugs into the Omnibus and is assigned the module designation M8315. Because the Omnibus accepts only four printed circuit board connectors. two of the connectors (E and F) extend off the Omnibus. The fingers on these connectors are test points that provide access to
certain significant signals in the Instruction Decoder and in the Timing Generator. These test points are shown in the
logic drawings (CS M8315-0-1) in Appendix H of this manual.
Figure 4-1 is a block diagram of the CPU. The Programmer's Console. although not physically part of the CPU. is
functionally inseparable. The operator can communicate with the major registers and cause data transfers to occur
by operating various console buttons. Data is transferred between the console and the processor on the DATA lines
in response to control signals generated within the console logic. The console is provided at the customer's option; a
Limited Function Panel (not illustrated in the block diagram) is provided with each PDP-8/A. This panel enables an
operator to turn power on. to lock out most of the Programmer's Console functions (if the console is part of the system). and to initiate memory and processor timing. provided certain options are plugged into the Omnibus.
The basic timing cycle of the PDP-8/A is 1.5 J.lS and is divided into four time states. The Timing Generator (TG). besides determining the basic timing cycle. provides the synchronizing signals that enable specific CPU operations to
occur during assigned time states. These synchronizing signals are applied to all CPU functional sections as well as
to memory and to opti'ons and peripherals.
To perform all the operations involved in retrieving, storing, and modifying information. the CPU utilizes the major
registers. Data is transferred between registers, between registers and memory (via the Omnibus M D lines). between
registers and peripherals (via the Omnibus DATA lines). and between registers and internal options. Transfers are accomplished by a major register gating network that selects the particular register to take part in the transfer and performs
some operation on the data being transferred. The selection and operation performed are determined by control signals
developed within the Instruction Decoder (10); the 10 also provides the control signals that determine the destination of
the transferred data.

4-1

['iNsTRucTiON De:COoERI

r;AJORREG7STERS- -

I AND GATING

I
I

I
ITIMT;;GGENERATOR" -

I
I

I
I
I

.., LINES

M8, CPYA

L---------~-_t-

H-=="----

LOAD

--T-----T----M'D
BI'

MEMORY
TIMING
SIGNALS

CONSOLE CONTROL
SIGNALS

__ ...I

"S~GCNO:LTs"0L
OMNIBUS

TI~I~::~~E

I ~~~;~~~f.tERS

~!~~~GFl~~NsTT~ciL

_ ":TL~

CONTROL

SlGr

r;; - - - 1. _ _
-

I
I

I
I
I

I
I

LINES _ _

DBAf~A_ :u~

.~ ___ ---'
:

Figure 4-1

_.1. - - - -

- --,

L ________________

I
MD

DATAi BUS

I
I
I

~OTRANSFER

TIMi:oULSE
TIME STATE SIGNALS

CPU Block Diagram

The signals that control the major registers and their gating are developed within the ID largely in response to three
variables:
1.

Basic instructions (as decoded by the Instruction Register logic)

Processor major states (as determined by the Major State Register logic)

Time states and time pulses.

These variables are combined in a number of Read-Only Memories (ROMs) to produce control signals that make the
major register gating network function.

4.2 TIMING GENERATOR
The various PDP-8/A operations take place in designated time periods of the operating cycle. These time periods are
delimited by signals produced in the Timing Generator. located on the CPU printed circuit card. Signals TS 1 through
TS4 divide the timing cycle into four nearly-equal states. while signals TP1 through TP4 identify the end of each
time state; these two groups of Signals form the foundation for all control signals used in the CPU and in memory.
Figure 4-2 is a block diagram of the Timing Generator. Central to the generator is the Timing Register logic that provides gating Signals for both the CPU Timing logic and the Memory Timing logic; Basic inputs to the Timing Register
logic are supplied by a crystal-co.ntrolled clock and by initializing logic that operates when power is applied to the
CPU and when the user initiates timing. Normal operation of the Timing Register logic can be modified by either the
Memory Stall logic or the 110 Transfer Stall logic. The former suspends timing to accommodate memory that has a
slower-than-normal cycle time; the latter suspends timing to facilitate multiple 1/0 transfers between the CPU and a
peripheral.

MEMORY
TIMING
LOGIC
CLOC K

CLEARL.

STROBE
SOURCE
RETURN
INHIBIT
WRITE

TO, T1
TIMING
REGISTER
LOGIC

GATING

GO (1)

MEM
START
L

MEMORY STALL

IIO STALL

MEMORY
STALL
LOGIC

IIO XFER

NTS
STALL L

CPU
TIMING
LOGIC

TS1-TS4,TP1-TP4
INT STROBE
BUS STROBE

STALL
LOGIC

NOT LAST
XFER L
08-1248

Figure 4-2

Timing Generator Block Diagram

4-3

4.2.1
Power On/Run Logic
The Power On/Run logic is shown in Figure 4-3. The CLEAR L signal and the GO(1) signal are generated in this'
logic and are used to begin the timing register operation. The RUN L signal is also produced and is used by the front
panel to indicate that timing cycles are being generated. Included in this logic is the auto-start circuit that enables a
user to have a program begin automatically at a pre-selected address.

TP4

H--~"""

QUAD FF
E5

GO(1)

QUEAf/~~(ll

Cf
3V

;>0---

RUN L

R 1(0) D - - + - - I

D------.----- ON L

R0(1)

TP3 H
TP4 H

+5V

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

08-1268

Figure 4-3

Power ON/RUN Logic

When the power is turned on, POWER OK H (a logic signal generated in the dc power supplies) remains low until
the dc voltages have attained a predetermined value. Throughout the time that POWER OK H is low. the CLEAR L
signal is asserted. Also, during this time, the de voltages, while not yet at the predetermined value, are of sufficient
magnitude to allow the logic to operate. Consequently, the ON L signal is generated, holding the RUN flip-flop in the
clear state. When POWER OK H is asserted, the ON DLY one-shot multivibrator is triggered (CLEAR L is negated
approximately 30 JiS later because of the delay circuit that includes NOR gate E36; this delay has greater significance when POWER OK H is negated for some reason, as will be shown later in this section). The ON L signal remains low 100 ms, long enough for all memory circuits to stabilize before operations are attempted.
When the ON L signal is negated, the RUN flip·-flop can be set if MEM START L is asserted. MEM START L can be
asserted automatically or manually, depending on the user's wish. For the moment assume that the auto-start feature is disabled and the user causes the MEM START L signal to go low by pushing the RUN button on the Programmer's Console. The RUN flip-flop is set, asserting the RUN L signal and enabling the next clock pulse to set the
GO flip-flop. The resulting high GO( 1) signal permits the Timing Register to begin its shifting operation.

4-4

The MEM START L signal can be asserted automatically soon after ON L is generated. The CLEAR L signal holds
both E42 flip-flops in the clear state when power is applied. If the OFF contact of switch S 1 is open. as shown in
Figure 4-3. the MEM START L line is grounded (the Timing Generator is always in time state one - TSL L is asserted - when not running). Thus. as soon as ON L is negated. the RUN flip-flop is set by the MEM START L signal.
The nature of the RUN flip-flop (DEC74S74) is such that when the clear and preset inputs are low at the same time.
both the 1 and 0 outputs are high. When one of the inputs goes high. the other input then prevails. Thus. when ON
L goes high. MEM START L sets the RUN flip-flop.
The auto-start feature is selected by the user with switch S 1. a two-position switch with individually movable contacts. If the OFF contact is open. the auto-start feature is enabled; when this contact is closed (in the ON position).
the resulting ground prevents automatic assertion of MEM START L. When auto-start is selected. the program begins automatically at the address specified by one of the top five contacts (Figure 4-3). Thus. if contact 4K is closed.
the program will begin at address 4000(8); if contact 400 is closed. the program starts at address 0400(8) (although all five contacts may be left open. causing the program to start at address 0000(8). only one of the contacts
may be closed at any time). If contact F7 is open. the address selected will be in instruction and data field 0; if F7
is closed. the address is in instruction and data field 7. When there is no memory extension control on the Omnibus.
field 0 is selected regardless of the setting of contact F7. Refer to Paragraph 4.6.4. which describes the sequence of
operation for the auto-start feature.
The Timing Generator can be halted by a program instruction. by various front. panel operations. or by negation of
the POWER OK H signal. All of these occurrences cause the STOP L signal to be asserted; the next TP3 H pulse
clears the RUN flip-flop. and TP4 H then enables a clock pulse to clear the GO flip-flop. The timing halts at the beginning of TS 1 L.
When POWER OK H goes low. because power is turned off or because a dc voltage drops below a desired level. a
delay circuit prevents the CLEAR L signal from immediately clearing the GO( 1) flip-flop. and. thereby halts timing prematurely (premature timing halt is undesirable because of the likelihood of altering the contents of core memory). Instead. the delay of approximately 30 IJ,S ensures that the RUN and GO flip-flops are cleared at TP3 time and TP4
time. respectively; thus. timing proceeds to its normal conclusion.

4.2.2 Timing Register Logic
The Timing Register logic is shown in Figure 4-4. The register comprises four DEC74S 194 integrated circuits - 4bit. bi-directional. shift registers. The four registers are shown in the configuration that applies during normal operation. i.e .. when neither of the stall networks is active.
The diagram in Figure 4-5 will help you visualize the process used to generate the timing signals. Conditions at time
to of this diagram can be characterized thusly: Power has been applied to the CPU; the 20 Mhz clock is producing
clock pulses; the dc voltages have attained a level sufficient to assert the POWER OK H signal; timing has not yet
been started by the user (M EM START L is high). Under these conditions the outputs of registers E9 and E 16 are
low. the outputs of E 11. except R2( 1). are low. and the outputs of E 12 may be low or high. depending on the state
of flip-flop E8 at power-on.
When the user causes M EM START L to be asserted. the GO flip-flop in the Power On/Run logic is set. asserting
the GO( 1) signal. Registers E9 and E 11 are placed in the right shift mode. Each clock pulse shifts a low into R3( 1)
of E 11. while shifting-down the high that began in R2( 1). When the high is shifted into E9-R1 (1). the STP (Set Time
Pulse) signal places register E 16 in the right shift mode. The next clock pulse causes E 16-R3( 1) (TO) to assume a
state opposite to that exhibited by E 16-R2( 1) (T1) before the clock pulse. Simultaneously. the CTS signal places E9
and E 11 in the parallel load mode. The new state of TO is then loaded into E 11. E 11 and E9 revert to the right shift
mode. and the shifting process is repeated. Each time the STP signal goes high. E 16 is placed in the right shift
mode and either TO or T1 changes state. Because the change of state is coincidental with the transition of register
stage E9- RO( 1). the signal from this stage is called CTS (Change Time State). although the change is actually effected by the STP signal. The TO and T1 signals. besides being essential in the Timing Generator. are used in the CPU
to generate many major register gating signals.

4-5

I/O STAll L

+3V

L51
+3V
INT STROBE l

+3V

-t5V

OS2

R3(1)

02 74S194
EI6
01

RHt)
ISO

R0(1}

Y>-"-r=D1
1

ClR ClK 050

74S194
Ell

R2(1)
Rt (1)
R0(1)

OS2

R3(1)

R2(O

ClR ClK OS0

r--

-n

T0l

'-----

~ TR;

r-<}-

03
02
01

74S194
E9

00
ClR

ClK

OS2

R3(1)

(>o-

R2(1)

...- 02 74S194 R2(1)

Rt(t)

STP

R0(t)

CTS

R3(1)

Et2

RHO
R0(1)

ClR ClK

OS0

CLEAR l
CLOCK
E8(0)l

74S194
OUTPUTS

INPUTS
ClR

S0 ClK OS0 OS2

PARAllEL IN
03 02

R3(1)

X
X

I
S

x R3(1)0 R2(t)0 Rt(1)0 R0(t)G

b
c
R3(t)n R2(1)n
I R3(1)n

R2(t)n

d
Rt (Un
Rt(t)n

lu
0

TS3 l

+3V
R0(1)

01 00

RI(t)

R2(1)

TSIL

IL
r-

X = Don't care
a ,b,c,d = level af steady - state inputs at 03,02,01,00.
R N (1) 0

= level of R N (1) before the indicated steady - state
conditions were established.

RN (I) n = level of RN (1) before the most recent upward
transition of the clock.
08-1250

Figure 4-4

Timing Register Logic

--, r- 50ns
CLOCK
E16-S1

PARALLEL LD

SERIALLJ
SHIFT :;r-

-JJ

E16-R3(11(T01 _ _ _ _ _ _ _ _

E16-R2( 1)(T1) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---'
E16- DS2
GO (1) _ _~

E9 t EI I -S1
El 1- R3(1)

SERIAL
PARALLELL-I..:::,S:..:.;HI.:-FT.:....-_ _
LD
-

-Jn'---------JnL..---------Jn'-------____nL.----______________--'rl'--_____
______________________________
~rI~

rl'--____-JrI'--_______~rl'_______

'--______-Jrl

El1-R2 (1)

---'n'--_____~n

Ell-Rl (1) _____

---'rl

EI1-R0 (1) _ _ _ _ _ _ _

E9-R3(1l _ _ _ _ _~n
E9-R2(I)(LDI _ _ _ _ _ _~rl

n
rl

--1n'-_____

E9- Rl (1) (STPI _ _ _ _ _ _ _
E9-R0(1l(CTSI

~rl

nL..-__
~

n
n

rL--

n
nL..-________

_________--1rlL.-______---'rl'--_____

~n'--

~rl

n
____

__J

rI'--_______

MEM START L
INT STROBE H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-Jr-l~

_____________

E12-S1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - E12-Rl(l)
E12- R0 (1l

Ea (01 L

L- ______ 11-____--1
i
L
- _ _ _ --'-_ _ _----J

_ _ _ ....J

08-'269

Figure 4-5

Timing Register Normal Timing

4.2.3 CPU Timing Logic
The CPU Timing logic is shown in Figure 4-6. The Timing Register signals TO and T1 are applied to a decoder,
DEC74S139, which generates the four time state signals (refer to the function table). Then each time state signal is
applied to a pulse synchronizer, D EC7 4120, the associated time pulse signal is produced (the pulse synchronizers for
TP2, TP3, and TP4 are not shown; they are similarto that of TP1).
The Timing Register signals LD and STP enable the clock to set and clear the TPC (Time Pulse Clock) flip-flop. The
resulting TPC H signal acts as clock for the pulse synchronizer, generating a time pulse signal of 100 ns width. Figure 4-7 is a diagram of the CPU timing signals.

4.2.4 Memory Timing Logic
The Memory Timing logic is shown in Figure 4-8, while a timing diagram is given in Figure 4-9. STROBE H,
SOURCE H, RETURN H, INHIBIT H, and WRITE H are used by memory to control the read and write portions of the
timing cycle. R ETU RN H and SOU RCE H, generated during both halves of the cycle, turn memory current on; the
conjunction of these two signals determines the width of the current pulse. R ETU RN H remains high 50 ns longer
than SOURCE H to ensure that the memory stack does not retain a capacitive charge. STROBE H, generated only
during the read half of the cycle, provides a time reference from which the outputs of the sense amplifiers are sampled. WRITE H and INHIBIT H are asserted only during the write half of the cycle; WRITE H enables the proper
read/write switches, while INHIBIT H turns on the inhibit drivers associated with memory control. Refer to Chapter 5
for details concerning memory operation.

4-7

T0 L

SI
T0

Bl 74S139
2-TO-4
DECODER
E20
A2

FA3
FB3

TSI L

FA2
FB2

TS2 L

FA0
FB0

TS3 L

TPI H

TPI L

74120
PULSE
SYNC
E22

R
C

TS4 L
QUAD FF
E5
------

TPC H

TPC

TPC L

------

STP

CLEAR
L

CLOCK

74S139
INPUT
TO
11
--_..._------

_...L_... - -

H- - H

NOTE:
TP2, TP3, a TP4 oenerated in the
some way as TP1.

74120

OUTPUT
TSl L TS2 L TS3 L TS4 L
L

H
H
H

---~

INPUT

--1-1- --1-1---- -H--

R
L

H
H

I Sl
IH

OUTPUT
INHIBITED
TPl L. TP1 H

oe-1270

Figure 4-6

CPU Timing Logic

4.2.5 I/O Transfer Stall Logic
Because of gating delays. some PDP-B/A-compatible peripherals need more time for an 1/0 transfer than is available
with normal processor timing; furthermore. some peripherals must make more than one 1/0 transfer during a single
lOT instruction. To satisfy these requirements. the 1/0 Transfer Stall logic. shown in Figure 4-10. interrupts normal
processor timing and stall the timing signals in TS3. The peripheral controller must assert the NOT LAST TRANSFER L signal to initiate the stalling operation. At the next occurrence of TP3 the processor timing is halted. The peripheral transfers the information, generating a BUS STROBE L signal with each word of data transmitted. This
continues until the controller negates the NOT LAST XFER L signal. signifying that the next BUS STROBE L signal
issued will be the last. This last BUS STROBE L signal restarts the processor timing. allowing TS3 to end and TS4
to begin.
The 1/0 Transfer Stall differs from the Memory Stall significantly: The former stalls timing only in TS3. the latter in
any time state; an 1/0 Transfer Stall occurs m~ar the end of the time state. while the Memory Stall occurs at the beginning; 1/0 Transfer Stall affects the memory timing signals in no way. while Memory Stall is primarily concerned
with these signals. Despite these differences. the stalling process is effected. essentially. in the same way. i.e .. the
CTS signal. which places shift registers E9 (Figure 4-10) and E 11 in parallel-load when high. is held active by the
signal at the corresponding register input (input DO of E9); therefore. the Timing Register cannot be shifted down
and timing signals are stalled.

4-8

1'50ns

CLOCK
T.
TI
LD
STP

TS I L

TS2 L

400n5

-I
I-

TS3 L

-I

400n5

I-

TS4 L
TPC H
TP1 H

350ns

-I

r-l

TP2 H

TP3 H

TP4 H

OB-1271

Figure 4-7

CPU Timing Signals

INHIBIT H

SOURCE H

RETURN H

S2J

OS2

~STROBEH

03
02

R1(1)

01
02J

TP1L~

74S194
E12

TP4 L
CLEARL~

R0'(1)

CLR CLK

OS2J
TP2 L

WRITE H
08-1272

Figure 4-8

Memory Timing Logic

4-9

-j
CLOCK

50n&

n.JlJl.JlJ1J1Jl..IU

TP I L
TP2 L

L..J

TP4 L
TI
EI2-R1(1l

i __
L

E12- R~ (I)

E8(0)L _ _ _

'--__~r
..J.-_ _ _

SOURCE H

L,__________--'

RETURN H

1..._________~

INHIBIT H
WRITE H
08 -1273

Figure 4-9
JlO PAUSE L

Memory Timing Signals

1/0 PAUSE H

S BUS STB

M00 L

BUS STROBE L
SI
R

MO 1 L
M 02 L _ _ _---l

74120
PULSE
SYNC
E19

SI
R

~gB~L~1

TPC L

Y 1 t - - - - - - - - f - J N T STROBE H
74120
PULSE
SYNC
E19

FH-Ly

Y0 D - - - - - - - - f - J N T STROBE L

TP1 L - - - -....

1/0 STALL L

QUAD FF
E5

110
STALL 0

S1
CLEAR L
T0

INT

NOT LAST

STROBE L

XFER L

R3(1)
R2(1l
E9

RI (1)

STP

R0(1)

CTS

CLOCK

Figure 4-10

ClK

08-1274

I/O Transfer Stall Logic
4-10

The logic in Figure 4-10 is effective not only when timing must be stalled, but also when an 110 transfer can be
made without the necessity of interrupting the timing cycle. When the instruction in the addressed memory location
is an lOT instruction, NAND gate E 18 asserts the 1/0 PAUSE L signal when the TP1 L signal comes true during the
Fetch cycle. If the lOT instruction does not require an extended timing cycle, the NOT LAST XFER L signal remains
high; thus, during TS3 both the S BUS STB and S INT STB signals are asserted. The TPC signals generated at TP3
time trigger the pulse synchronizers producing the BUS STROBE L signal and the INT STROBE signals. The active
BUS STROBE L signal causes the AC register or the PC register to be loaded, while the active INT STROBE L signal
enables the timing cycle to proceed into TS4.
If the timing cycle must be extended, the peripheral controller grounds the NOT LAST XFER L line before TP3, preventing the pulse synchronizers from being triggered by the TPC pulses. The controller must provide a BUS STROBE
L signal along with each data transfer. To stall the timing cycle, the NOT LAST XFER L signal must cause the CTS
signal to be suspended in its high state (Figure 4-11). NOT LAST XFER L does this by enabling the clock to set the
110 STALL flip-flop, which is then latched in the set state; 1/0 STALL L generates the required high DO input at shift
register E9, suspending CTS and, consequently, holding E9 in parallel load. Because E16 is halted in parallel load by
the same signal. 110 STALL L, the Timing Register stalls just before the normal end of TS3 L even though the TP3
pulse is completed.
The timing cycle remains stalled until NOT LAST XFER L is negated, at which time S INT STB is asserted (S BUS
STB is also asserted but has no significance at this time). The last BUS STROBE L generated triggers the INT
STROBE pulse synchronizer, producing both INT STROBE signals. The first clock pulse to occur after INT STROBE L
is asserted brings the ISO signal low, thereby placing E16 in the right shift mode and causing the D-input of the liD
STALL flip-flop to go low. The next clock pulse clears the 1/0 STALL flip-flop and places E16 in parallel load once
again. The third clock pulse brings the CTS signal low, and normal timing operation is resumed.

4.2.6 Memory Stall Logic
The Memory Stall logic is shown in Figure 4-12. This logic is designed to modify the normal operation of the Timing
Generator so that memories that have a cycle time slower than 1.5 IJ,S can be used with the PDP-8/A CPU. A slower
memory grounds the Omnibus NTS STALL L line to halt the Timing Generator during one or more processor time states
of a timing cycle. In order to stall the generator in a particular time state, the memory logic must assert the NTS STALL L
signal at least 100 ns before the time pulse that precedes the time state in which the stall is to occur. For example, to
suspend the timing in TS3, the memory must assert NTS STALL L at least 100 ns before TP2. The timing will halt at the
beginning of TS3, except for the TP2 signal. which is completed during its normal time; the timing remains in the stalled
condition until the NTS STALL L signal is negated.
Figure 4-13 is a timing diagram that illustrates the process just described, i.e .. the Timing Generator is stalled at the
beginning of TS3. This diagram shows NTS STALL L being asserted during TP1 and negated approximately 700 ns
later. Fifty nanoseconds after NTS STALL L is negated, the normal timing resumes and TS3 L is asserted for the
usual period of 400 ns. Note that the WRITE H signal is' stalled along with the processor timing signals. This is the
only memory timing signal whose duration is affected by the stalling process; all other memory signals are active for
the usual length of time regardless of the time state chosen for stalling. For example, if NTS STALL L is asserted
before TP1, the timing halts at the beginning of TS2; however, STROBE H, SOURCE H, RETURN H, and TP1 are
completed in the normal period of time.
Table 4-1 indicates the result achieved by stalling the timing generator at the start of each of the time states.
4.3 FRONT PANEL OPERATIONS
There are two types of control panels for the PDP-8/A. The Limited Function Panel is supplied with each computer;
it enables an operator to turn the computer on, and it provides several elementary indications of the PDP-8/A's operating condition. The Programmer's Console, KC8-AA. is an option that enables one to control computer operations
and to make step-by-step checks on significant conditions within the computer.

4-11

TPI H

T10

T25

T30

TP4 H

r-L

L-

--.J

--,

fS4 L

1 NT STROBE H

f"
.....

BUS STROBE L

I\,)

TPC H

T35

TP3 H

TS2 L

T20

TP2 H

TSI L

T15

r-l

EIS-RI II)
E1S- R0 (1)

L.J

STROBE H

r-l

.--.

L-J

r--L

n
L-J

rL
L.r

SOURCE H
RETURN H
INHI BIT H
WRITE H
08-1275

Figure 4-11

I/O Timing (NOT LAST XFER L Asserted) (Sheet 1 of 2)

T15

TIO

T20

T25

T30

T35

CLOCK
E16- 51
T0

--.J

J I____________~rl~____________~
El'-R3(1} ---Il~__________~rl~____________~
____
____________
______________________________________
E1'-R2 (1)
E9,EII-51

~rI~

~rl~

______~rl
E9-R0(1l ________
E9- R3 (1) __________~rl

El'-R' (1)

f>
......

____________
__________
E9-Rl (1) (STP) -,
__________
E9-R0 (I )(CTS) J I
~rl

E9-R2 (1)(LD)

~rl~

I/O PAUSE H

__________r_

_________

rl~

________

rl~

rl
____________rl
__________

~rl~

rI~

rl
rl

~rl

L__________rL-

_____

rl~

____

___________rL

---.J

NOT LAST XFER L
S BUS STB
S INT STB
TS3 L
I/O STALL L
08-1276

Figure 4-11

I/O Timing (NOT LAST XFER L Asserted) (Sheet 2 of 2)

STALL LATCH,

R3(1)
QUAD
E5

NTS STALL L

NTS
STALL

R2(1)

R1(O

STP

0.0'

R0(1)

CTS

1r-+------Q
0'

I/O
STALL L

CLK

CLEAR L
CLOCK _ _--4_ _ _ _ _ _ _ _ _ _ _--J

08 -1277

Figum 4-12

Memory Stall Logic

4.3.1
Limited Function Panel
Two Limited Function Panels are in use; one is used with the PDP-8/A Semiconductor computer. while the other is used
with the 8A computers. The switches. indicators. and circuit components of each panel are mounted on a circuit board
that is attached to the rear of the panel; the switches protrude through the panel and the indicators are visible through
panel openings. The circuitry associated with each panel is the same. but the location of circuit components differs. as is
shown by Figures 4-14 and 4-1 5. Connector J 1 of the 8A-type circuit board connects to the H 9194 Omnibus. while J 1
of the PDP-8/A semiconductor-type circuit board connects to the H9192 Omnibus via the Power Board Assembly. The
following description applies equally to each circuit board. except where noted otherwise.
The three LED indicators provide a basic indication of the computer's operating condition. In the PDP-81A Semiconductor
computer. the BATTERY CHARGING indicator lights when the battery charger circuit on the power supply regulator
board is operating; when charging current ceaSies to flow. the LED is extinguished. indicating that the battery is fully
charged. In the 8A420. 8A620. and 8A820 computers the BATTERY CHARGING indicator lights when both G80l8
regulators are operating correctly. The indicator is not used in the 8A400. 8A600. and 8A800 computers. The POWER
indicator monitors the secondary of the power transformer; when lighted. it indicates that ac power has been applied to
the computer. The RUN indicator lights when the Timing Generator is turned on and the Omnibus RUN L signal is
asserted. RUN L turns off transistor E1C allowing the LED to glow; when the Timing Generator is off. E1C conducts and
the LED remains dark.
The three switches on the front of the panel permit limited control of the computer. The PANEL LOCK switch is
shown in the active (up) position. the position that disables the console pushbuttons. except LSR and DISP. The
BOOT switch. shown in the inactive (down) position. is used to initiate bootstrap loading of programs. When the
switch is in the position shown. transistor E1A is off and the BOOT signal is high (BOOT becomes SW L on the 0 mnibus). To initiate a bootstrap operation. the operator must raise the BOOT switch and then return it to the down position. When the switch is raised. transistor E 10 is turned off. causing E1 A to turn on; this action brings the SW L
signal low. When the switch is returned to the down position. E1 A is turned off and the SW L signal goes high. The
low-to-high transition is used by the Bootstrap Loader option (M8317) to begin the bootstrap operation.
The computer's primary power can be controlled from two locations - the Limited Function Panel. where the
ON/OFF switch enables the operator to turn the power on or off. and a remote position. where the POWER
REQUEST signal can be switched to turn the power on or off. The MASTERI SLAVE switch determines the source
of primary power control. With the switch in the MASTER position the panel ON/OFF switch assumes control; with
the switch in the SLAVE position. the remote location assumes control (the power can be turned off by the panel
ON/OFF switch even though the SLAVE position has been selected).

4-14

CLOCK

E16 -S1

E9,El1-S1 -----,
TO
T1
El1-Rl (1)
E11-ROm
E9-R2 (1)(LO)
E9-R1 (l)(STP)
E9-RO (1) (CTS)

-..Jl

~
~

NTS STALL L

I
I·

STALL LATCH H

TS3 L

STROBE H

750n5

-I

SOURCE H
RETURN H

INHIBIT H
WRITE H
TPl H

II
II

TP2H

TP3H

TS1 L
TS2 L

TS4 L
08-1278

Figure 4-13

Timing. NTS STALL L Asserted

Table 4-1
Time State Stall Results
Time State Stalled

Result

TPl

TS2

The time from the end of read to TP2 is increased, accommodating memories with long
read-access time.

TP2

TS3

The time from the loading of the MB register
to the start of write is increased.

TP3

TS4

The time from the start of write to the change
of address is increased, accommodating
memories with a long write time.

TP4

TSl

The time from the change of address to the
start of read is increased.

NTS STALL L Asserted Before

The two switches are illustrated in Figures 4-14 and 4-15. along with part of the associated circuitry. The circuitry
and the signals are discussed in detail in Chapter 7. Power Supply; only the result of the switching operation is presented here. Table 4-2 shows what happens when the switches are in the indicated positions. The LINE LEVEL signal shown in the figures is a measure of the ac line voltage and is present as long as the ac line is connected to
the computer.
4.3.2 Programmer's Console
Figure 4-16 is a block diagram of the PDP-8/A Programmer's Console logic. Included in the block diagram is the
console control logic. part of the liD option board (DKC8-AA) that plugs into the Omnibus. The console logic is contained on two printed circuit boards that are mounted on the rear of the console. The two boards connect electrically
by short lengths of cable; the console connects to the liD option board by a cable that can be as long as 15 feet.
enabling the console to be located remotely from the PDP-8/A mainframe.
There are 20 pushbuttons. 8 LED (light-emitting diodes) indicators. and 9 7-segment LED displays visible on the front of
the console. See Chapter 1 for a description of the indicators and controls for both the Programmer's Console and the
Limited Function Panel.
The Programmer's Console pushbuttons can be grouped into number buttons and function buttons. Number buttons
are used to specify addresses and data. and to select the data from a specific source (for example. the AC register or
the DATA bus) for display in the DISP readout. When a number button is pushed. the number is displayed as the
right-most digit in the DISP readout. If a second number button is pushed. it appears as the right-most digit. while
the first is shifted left by one position. Any number of digits may be entered in the DISP readout. although only the
four displayed have meaning; collectively. the digits are referred to as the "entry."
Function buttons are used to start and stop CPU timing. to initialize selected CPU hardware. to load addresses and
data specified by the entry. and to display the data from the source selected by the entry.
When the operator pushes a function button. the logic generates the signals KFUNO L KFUN 1 Land KFUN2 L in a
combination that is peculiar to that button. The button is identified as "number" or "function" by the NUM H signal
or the FUN L signal. respectively (only one number or one function button can operate at the same time). Either of
these two signals causes the clock timing logic to assert three basic timing signals. KEY STB H. MCLOCK Land
KEY F L.

4-16

J1
04//

R3
470
POWER

+15V

BATTERY CHARGING

POWER

RUN

+5V

R7
1. 5K

R4
820
RUN

Rl
270
R2
270

BOOT
R8
1.5K R9
1.5K

PANEL LOCK

IPANEL LOCKI
SI
BOOT
0

ON/OFF

01
0672

02
0672

AC OFF L

R6
820

LI NE LEVEL

03
IN4004

OFF

POWER REQUEST

BATTERY

o SLAVE
OFF

SPECIAL GNO

13
16

+5V

9
10
11

08-1279

Figure 4-14

Limited Function Panel Circuit Board Schematic, 8A Computers

If a number button has been pushed, the signal combination representing that button is loaded into the number shift
register, gated through a data selector by the GATE ENT L signal. and loaded into the DISP flip-flops. The readout
control logic generates signals that multiplex the number data to the DISP readout circuits on the DISPLAY 0, 1,
and 2 lines, while at the same time asserting signals that direct the number data to the correct digit of the DISP
readout. When the operator pushes a second number button, the first number is shifted to bit position two of the
number shift register, while the second number is loaded into bit position one. Both numbers are gated to the readout circuits as just described and displayed in the correct digit position. A third and fourth number can be entered in
the same way. The DISP readout then shows the octal representation of whatever the entry is intended to specify,
the most significant bit of the data being contained in the left-most digit. This entry is displayed until the operator
pushes either another number button, changing the content of the number shift register, or a function button, disposing of the entry.

4-17

IIIPANEL
MiT ED
FUNCTION'
CIRCUIT BOARD I
I

~~~~~~~~---------,

I
1 - - - - - - - - - - - - - + 15V
1 - - - - - - - - - - - - BATTERY CHARGING

E1C

t-+--.--'W'Ir---- RUN L

F8fJ

N~J:

I---POWER--+5

ir--·,
+---~--+-BOOT ~ J
+5V

~~~3_d

PANEL LOCK

@~
LOCK

MASTER

LINE
LEVEL

AC OFF L

I ON/OF~

POWER
REQUEST

°SLAVE
BATTERY OFF

L... _ _ _ _ _

Figure 4-15

...J IL _________________ J
Limited Function Panel Circuit Board Schematic,
PDP-8/A Semiconductor Computer

The disposition of the entry depends upon what the entry represents; i.e., is it an address or is it data? If it is an address,
the operator can transfer it to the CPMA register by pushing the LA (load address) button. When this button is pushed,
the signals representing the LA function are loaded into the latch circuits and applied to a decoder. The decoder output
causes the gating logic to generate signals that gate the entry to the CPMA register via the Omnibus DATA lines. First.
the GATE ENT L signal selects the output of the number shift register for transfer to the console control logic on the BUS
0-11 lines. Then, the KCCN 1 SR ENABLE L signal is asserted by the interface gating logic, placing the entry on the
Omnibus DATA 0-11 lines. Transfer control signals asserted by the interface gating logic direct the information on the
DATA lines to the CPMA register and cause the register to be loaded.

4-18

Table 4-2
Primary Power Control

ON/OFF Switch

MASTER/SLAVE Switch

OFF

-Condition of transistor E1 B is irrelevant.
POWER REQUEST signal is grounded
(irrelevant in this situation).
Line voltage is applied to the power
transformer.
If POWER REQUEST is not grounded
at the remote location, E1 B is on; thus,
AC OFF L is low and ac line voltage
is not applied to the power transformer.
BATTERY OFF is grounded in the
power supply to prevent the battery
supply from operating.

AC OFF L is grounded, causing the ac
line voltage to be removed from the
power transformer.
BATTERY OFF is grounded to prevent the battery supply from operating.

MASTER

AC OFF L is grounded, causing the
ac line voltage to be removed from
the power transformer.
BATTERY OFF is grounded to
prevent the battery supply from
operating.

SLAVE

If POWER REQUEST is grounded,
E1B is off. AC OFF L and BATTERY
OFF are high. Line voltage is applied
to the power transformer.

If the entry is data, rather than an address, it can be deposited in a memory location that is addressed as just described.
The DTHIS or DNEXT button causes the gating logic to assert the GATE ENT L signal. placing the entry on the BUS 0-11
lines. Again, the KCCN 1 SR ENAB LE L signal passes the entry to the Omnibus DATA 0-11 lines where it is routed to the
M B register and placed on the M D 0-11 lines.
Rather than depositing the data in memory, the operator can load it into the switch register for future use by pressing the LSR button. At any later time, he or she can display the contents and, if necessary, make changes manually;
the operator can also program certain operations that use whatever data is stored in the register.
To display the contents of a register or of another available source, the operator pushes one of the buttons numbered from 0 to 6. The source of data represented by each of these numbers is indicated above the button. Thus,
when the operator wishes to view the contents of the AC register, for example. he or she first pushes the button
numbered "0". The signals representing number 0 are loaded into the number shift register and the number is disi\
played in the right-most digit of the DISP readout. Then, the operator pushes the DISP function button. The output
from the BCD-to-decimal decoder clocks the ENTO H, ENT1 H, and ENT2 H signals into flip-flops; the flip-flop outputs, DISPO H, DISP1 H, and DISP2 H, cause the AC indicator to light. At the same time. the interface gating logic
asserts Omnibus signals that gate the AC register contents onto the DATA 0-11 lines; the KCCN 1 DATA ENA L signal gates the DATA line signals through the selector to the BUS 0-11 lines. From the BUS 0-11 lines the AC contents are routed through the DISP flip-flops and the multiplexer to the DISP readout; they are displayed there until
another number or function button is pushed.

4-19

ENT 0,1,2 H
NUMBER
SHIFT
REGISTER

DATA
SELECTOR

CLOCK

GATE
SR L

NUM CLK H

- -,

--- ---- - - - - f;, -o MS40400

I
I
I
I
I

I
BUTTON PAD
NUMBER
BUTTONS
FUNCTION
BUTTONS

NUM H

1
-.-l

K FUN 0,1,2 L
FUN L

CLOCK
TIMING
LOGIC

f----

i
LD SR H

M CLOCK L

I
I

KEY F L

KEY STB H

- - -- - -

L --------

SWITCH
REGISTER

GATE
ENT L

FREERUNNING
CLOCK

FLiP-FLOPsl
CLOCK

-18US ENABLE
LOGIC

DSP LTH L
ADD LTH L
DISP

..J

r---- GATE ENT L

LSR
LA

J-I CIRCUITS
LATCH
~
ENABLE

BCD- TO
DECIMAL
DECODER

NOT E:
Un less noted, logic is PIO MS40421

LXA
INIT

GATING
LOGIC,
BUFFERS

RUN, HLT
PANEL a CPU
CONTROL SIGNALS

E THIS, E NEXT

o TH IS, 0 NEXT
ENABLE

ENABLE

1
08-1281

Figure 4-16

Programmer's Console Biock Diagram (Sheet 1 of 2)

r;/O~s"40400

- - - - - - - - - --,

BUSO-II

DISP
1 r--...:---*--.--.t FLIP - FLOP S

L' ~

l CLOCK

DSP LTH L

GATE SR L

I CONTROL
DISPLAY

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~------~-'

I LOGIC
'---------I
PANEL a. CPU CONTROL SIGNALS
4~------------------------------------------------------------------------------~L-----------------------~

INTERFACE
GAT I NG
LOGIC
A

EMA 0,1,2 L

_______

..J
08-1282

Figure 4-16

Programmer's Console Block Diagram (Sheet 2 of 2)

4.3.2.1
Clock Timing Logic - The clock logic is shown in Figure 4-17. The logic includes two priority encoders
(E1 and E6). two one-shot multivibrators (E18). two flip-flops (E23). and a 4-bit shift register (E24). The one-shot
multivibrators comprise a free-running clock-pulse generator that produces a 400 ns MCLOCK L pulse every 1 ms.
This MCLOCK L signal is used throughout the console logic and is fundamental to the operation of the clock timing
logic.
When the operator pushes 'a button on the front of the console. one of the priority encoders generates a binary representation at the AO. A 1. and A2 outputs. These outputs become the KFUNO L. KFUN 1 L. and KFUN2 L signals that
are important in the logic that follows (Table 4-3 lists the console pushbuttons and the corresponding binary representations.) The encoder also produces a signal at the GS output (FUN Lor NUM L); this indicates the identity (function or number) of the selected pushbutton and causes a low voltage level to be applied to the serial-input line
(DSO) of the 4-bit shift register (unless a button on the console is pushed. this shift register is constantly right-shifting a high voltage level that appears at the serial input; consequently. the register is always fully-loaded. except
when front panel operations are in progress). The 4th MCLOCK L pulse to appear after the button has been pushed
shifts a low into bit position 4 of the register (R3( 1)). thereby causing flip-flop E23A and. in turn. E23B to be set.
Thus. the KEY F L and KEY STB H signals are generated. KEY STB H being somewhat less than 400 ns wide due
to the delay in E24 and E23. Figure 4-18 shows the timing of the clock timing logic.
Note that 4 MCLOCK L pulses must be counted by the shift register after the pushbutton has been activated (i.e ..
when NUM L is asserted). This requirement ensures that switch contact-bounce will not affect circuit operation. For
the same reason. four pulses must be counted after the button has been released (if a new button is pushed before
this happens - a near physical impossibility - the KEY STB H signal will not be generated).
If two or more buttons are pushed simultaneously. the priority encoders ensure that only the button having highest
priority is represented at the encoder outputs. Highest priority is assigned to the 0 number button and to the DISP
function button; the remaining buttons are assigned priorities that correspond to their relative positions in Figure 417 (e.g .. button 7 has the lowest priority in the number group; the H LTISS button has lowest priority in the function
group).
The number buttons have priority over the function buttons. When a number button is pushed. the encoder EO output is high. This output is applied to the E 1 input of the function encoder and disables it. keeping all outputs high.

4.3.2.2 Register Logic - The Register logic is shown in Figure 4-19. (Figure 4-23 relates signals in this paragraph
and in paragraphs 4.3.2.3 and 4.3.2.4). The logic consists of 4-bit shift registers E 1. E2. and E3. quad flip-flops E5.
E6. and E7 (these flip-flops comprise the switch register). and data selectors E9. E10. and E11. When a console button is pushed. a binary-coded representation appears on the KFUN lines. If the button is one of the number group.
the NUM CLK H signal is generated. loading the signals into RO( 1) of each shift register (the E MODE L signal is
high at this time (Figure 4-23); hence. the shift registers are in the parallel load mode. ensuring that the as-yet
unused bit positions are loaded with ground-Ieivel signals). Because the button is from the number group. the GATE
ENT L signal is generated periodically and gates the signals through the data selectors to the BUS lines.
If the operator pushes a second number button. the NUM CLK H signal right-shifts the registers; consequently. the
signals representing the first number are shifted to R1 (1). while the signals representing the second number are
shifted into RO( 1) (note that the E MODE L signal is low at this time). Data representing four numbers can be entered in the registers and gated to the BUS lines. For example. consider what happens when the operator wishes to
deposit data word 6203(8) in memory. After selecting the memory address. he or she pushes the four octal numbers
consecutively. beginning with 6. When the operator has entered all four numbers. the data is represented on the
BUS lines as shown in Table 4-4. By pushing the DTHIS and DNEXT button. the data is routed through the logic
and deposited in the selected memory location. This action then negates the GATE ENT L signal. removing the data
from the BUS lines after it has been operated on. However. the data is retained in the shift register until the operator pushes another number button.

4-22

B PWR OK H -........- - - - - - - - - - - ,

A2
K FUN 0 L

EI8A(0)H
2

AI
K FUN I L
9318
EI

r-----MCLOCK L
AO
K FUN 2 L
MCLOCK H
EXT PUL L

6
GS
7
D3

NUM L
NUM H

i\J
W

LSR

LXA

INIT
RUN

D2
DI

EI
DISP

R3(t)
7495
E24

R2(ll
R1(O

ROO)
DO
RSHF CLKO DSO

AI
9318
E6
KEY STB H

E NEXT
GS D - - - - -.......-+-- FUN L

E THIS
0
D NEXT

7495

D THIS
HLT/SS

STH IS L

DSO

MODE

RSHF

CLKO

RO(1)

R1(1)

R2(1)

R3(1)

RT SHIFT

RO(1)n

R1(1)n

R2(1)n

t
t

PAR LOAD

S HLT L

BOOTY
n = STATE OF RN (1) BEFORE CLOCK PULSE
08-1283

Figure 4-17

Clock Timing Logic

Table 4-3
Clock Timing Control Signals
Pushbutton

O(AC)
l(MQ)
2(BUS)
3(STATUS)
4(SR)
5(STATE)
6(MD)
7

DISP
LSR
LA
LXA
INIT
RUN
ENEXT
ETHIS
DNEXT
DTHIS
HLT/SS
BOOT

DEC9318 Output

AO, Al, A2, GS
Al, A2, GS
AO, A2, GS
A2,GS
AO, Al, GS
Al,GS
AO,GS
GS
AO, Al, A2, GS
Al, A2, GS
AO, A2, GS
A2,GS
AO, Al, GS
Al, GS
AO,GS
AO,GS
GS
GS
Al, GS

KFUNOL

KFUN1L

X
X
X
X

X
X

Control Signal Generated
NUMH
FUNL
KFUN2L
X
X

X
X

X
X
X
X

X
X

X
X
X

STHISL

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X

E18A (0) H

E18B (0) H

MClOCKl

NUM H/FUN l

---1

E23A-ClEAR

~~----------------------------J

E23A -ClK

E23B-ClEAR

KEY Fl

KEYSTBH

~
l~

______________________________________

_____________________________________
08-1284

Figure 4-·18

Timing, Clock Timing Logic

4-24

SHLTL

The operator can load the switch register from the shift register at any time by pushing the LSR button. The data is
retained in the switch register unless a power down condition occurs, clearing the register, or until new data is loaded
from the shift register. Data is gated from the switch register to the BUS lines by the GATE SR L signal. This signal is
asserted whenever the operator has selected the switch register contents for display in the DISP readout. or when a
program instruction has directed that the switch register contents be placed on the Omnibus DATA lines (SR DATA Lis
asserted).
The operator displays the contents of some source by, first. pushing the appropriate button and, second, pushing the
DISP button. The binary-coded representation of the source is loaded into RO( 1) of the shift registers and. thus. appears on the ENTO, ENT 1. and ENT2 lines. These lines carry the binary-coded signals to the display control logic and
to the display indicators.

NUM ClK H

ClKl

ClKO
R3(1)

R2(O

,...--- 03

AO
~

E3
7495

t-- 01

Fl~B US 3

Ell
RW)

RO(1)

.".

K FUN 0 l

FO ~B US 0

F 2 - B US 6

A2
DO
RSHF

OSO

'--- 01

RHO) f--

DO
E7

RO(O) r - -

R3(0)

02
ClK

R2(0)
ClR

r------

ENTOH

F 3 - B US 9

, - - - - - A3
SI

.--

r - BUS 1
~

t--

El0

BUS 4
BUS 7

{:-

r - BUS 10

K FUN 1 l

r-I-- f-~

J
b

r-W

r--

ENT 1 H

t---

t-- t---

t---

]

.-~ BUS

..--

r - BUS 8
r - BUS 11

t-.".

K FUN2 l

.--t-- t---

~r--

r---

r------

E MODE l
ENT 2 H

r-~

]

GATE SR l GATE E N T l -

lO SR H
BPOK H
08-128~

Figure 4-19

4-25

BUS 5

Table 4-4
Register Logic Bus Line Data
Octal Number

Bus Line

Voltage Level

0
1

2
2

3
4
5

6
7

8
3

9
10
11

LO
LO
LO

HI
LO
LO
LO
LO
LO

HI
HI

4.3.2.3

Multiplexer Logic - The Multiplexer logic. shown in Figure 4-20. consists of hex flip-flops E 12 through
E 15 and multiplexers E 17 through E19. Data on the BUS lines is clocked into the flip-flops and gated by the multiplexers to the readout circuits via the DISPLAY lines or the ADDR lines. The data on the BUS lines is either the entry. which will be displayed in the DISP readout until disposed of. the contents of some source (the AC register. for
example). which will be displayed in the DISP readout. or the address of the currently-addressed memory location.
which will be displayed in the ADDRS readout.

Entry data is gated from the register logic onto the BUS lines by the GATE ENT L signal. When GATE ENT L is low.
the DSP LTH L pulse clocks the BUS lines data into hex flip-flops E 13 and E 15. The flip-flop outputs are applied 'to
multiplexer E19 and half of multiplexer E 18. The multiplexers are controlled by signals MPX A and MPX B. which
are generated by the readout control logic. The readout control logic also generates enabling signals that are applied
to the DISP and ADDRS readout circuits. Each of these enabling signals is applied to a 7 -segment LED display. The
enabling signals and the M PX signals are related in such a way that the correct data is displayed in each LED display. The block diagram in Figure 4-21 illustrates the method of gating the BUS lines data to the proper LED display. Figure 4-23 shows the timing of the signals involved in the procedure.
The table in Figure 4-21 relates the enable signals. the M PX signals. and the BUS lines. For example. the readout
control logic asserts enable signal
when both MPX A and MPX B are low. Signal
is applied to the anode connection of the right-most LED display (the one showing the LSD of the 4-bit octal DISP readout). The M PX signals
gate the multiplexer A inputs to the DISPLAY lines; thus. the data on the BUS 9. BUS 10. and BUS 11 lines is applied to the cathode connection of the LED displays. Only the right-most display indictates a number at this time.

The contents of a register. or some other source, are gated to the DISP readouts in the same way as is entry data. The
address of the currently-addressed memory, however, is clocked into hex flip-flops E12 and E14 (Figure 4-20) by the
ADR LTH L signal. This address is gated onto the BUS lines from the Omnibus DATA lines by the MA ENA L signa\.
which is asserted periodically provided that neither the LA. the LXA. nor the DEP button has been activated. The MPX
signals place the current address on the ADDR lines and the address is displayed in the ADDRS readouts.

4-26

DSP lTH l

BPOK H

1
BU so

STBI
DO

ROO)

BU S 3

RIO)

BU S6

R2(1)

BU S9

03
04

E15

R3(1)

R4(1)

R5(1)

ClK

ClR

STBO
FO -

DISPLAY 0 H

E19

F l - DISPLAY 1 H

r - Al

I
~

1 1
EI3

DISPLAY 2 H

ADDR 0 H

BUS 1

BUS 4
BUS 7 -

BUS 10 --<

-r--

E18

E14

L
~

1 1
'---

ADDR 1 H

ADDR 2 H

E17
BUS 2
EI2

BUS 5
BUS8
BUS 11

~
ADR lTH l

~
MPX A -

MPX B, - 08-1286

Figure 4-20

Multiplexer Logic

4.3.2.4 Register/Multiplexer Gating Logic Timing - The signals that control the Register logic and the Multiplexer logic are produced by the gating logic shown in Figure 4-22; the signals are related by the timing diagram in
Figure 4-23. The lower portion of Figure 4-23 shows timing signals that are generated in the ADDRS/DISP Readout
Circuit logic; these signals a re included to illustrate their relationship to the M PX signals.

4-27

The timing diagram shows what happens when the operator pushes a number button. the AC button in this ex- .
ample. and then the DISP button. The KFUN signals (not shown) are parallel loaded into the shift register by NUM
CLK H. after which the E MODE L signal goes low to place the register in the right shift mode. GATE ENT L gates
the entry to BUS lines 9. 10. and 11. and the DSP LTH L signal clocks the entry into the flip-flops. MPX A and
MPX B gate the entry to the DISPLAY lines and it is displayed in the right-most position of the DISP readout when
the 0 signal is low.
The MA ENA L signal is asserted periodically. When this signal is low. the address on the Omnibus MA lines is placed on
the console BUS lines. The ADR LTH L signal clocks the address into the flip-flops; the MPX signals gate the address to
the ADDR lines. and it is displayed in the ADDRS readout. Note that MA ENA L is negated whenever the LA. the LXA. or
the DEP button is pushed. Each of these buttons asserts the GATE ENT L signal for as long as the button is held down.
and entry data is placed on the B US lines for transfer to the Omnibus. Thus. address information must be kept off the
BUS lines during this period.
When the DISP button is pushed at t( 1) time. the E MODE L signal is negated by KEY STB H. and GATE ENT L
remains high. The entry is gated to the DISP key logic on the ENT lines and loaded into flip-flops there. This action
causes the AC indicator to light and asserts three signals - BUS EN L. IND1 L. and IND2 L - that transfer the contents of the AC register to the BUS lines. The DSP LTH L signal clocks the AC register data into the flip-flops. the
MPX signals place the data on the DISPLAY lines. and the data is displayed in the DISP readout. As before. the address on the MA lines is displayed in the ADDRS readout (the address remains unchanged throughout the timing
illustrated).

1
2

~
l-

I- I

I- I
I- I

I- I

I--

READOUT
r---CONTROL
LOG IC

I- I
I- I

IY1
I

Y J I
I- I

I- I

7-SEGMENT
SIG NALS

I-r-

BUS @- 00
BUS 3 - B0
BUS 6 - C0
BUS 9 - Ar;1

DISPLAY 1 H

F.0'
BUS2- 0.0'
BUS 5 - B.0' E18
BUS8- C.0'
BUSl1- A0

MPX B

DISPLAY 0 H

E19
BUS 1 - 01
BUS 4 - B1
BUS 7 - C1
BUS10- A1

MPX A

BCD-70-7
SEGMENT
DECODER

DISPLAY 2 H

Figure 4-21

MPX B
0
1
0
1

ENABLE
0
1
2
3

DISPLAY X H
A
C
B
0

BUS LINE DISPLAYED
9 10 11
6.7.8
3.4.5
0.1.2
08-1287

M PXlEnable Signal Relationship

4-28

D - - - - - N U M CLK H

LSR

(SEE FIGURE 4-27) .

t - - - - - LD SR H

~----GATE

SR L

SR-DATA L
PWR OK H

I - - t - - - t - - - - - - - - - - t " - - - - - - - - - - - - - - - - - - E MODE L

KEYSTBH

NUM H

x r - - - - GATE ENT L

M CLOCK L
D - - - - - A D R LTH L
BRUN L

D - - - - - DSP LTH L

+5V

BTSl L

CO
t3V

MA ENA L

7490

E25

SET 9

LXA*

R3(ll

R2 (1 l t - - - - - - - - MPX A
CLR

R1 (1 l 1 - - - - - - - - MPX B

* SEE FIGURE 4-26

M CLOCK H
08 -1288

Figure 4-22

tOI

--l r--400 nl

rLn.nnJlJ1.f

M CLOCK L

NUM H ~

AC(O)

~I_____ ~I~________~

KEY F L

KEYSTBH ____________~n~

______________________________ _____________________
~n~

E MODE L

NUM CLK H

GATEENTL~

DSPLTHL~-U

ADR LTH L

MAO (1) H

FUN L

01 SP

CURRENT ADDRESS DISPLAYED

AC DISPLAYED

Jw-LrU

MA ENA L

BUS EN L

IND' L

IND 2 L

MPX A

~ _ _ _ _ _ _ _ _ _ _---J

MPXB

~ _ _ _ _---'

---Ir--IL.._____________--'

E25 - R3 (1) _ _ _ _ _ _ _ _ _ _ _ _ _

IL..__

E22- Fa

D__....J

E22-Fl

E22- F2

1 . . .__. . .

E22-'F3

r--

E22-F4

~-.J

NOTE:
RUN L NOT ASSERTED.

Figure 4-23

08-1289

4.3.2.5 ADDRS/DISP Readout Circuit Logic - The logic shown in Figure 4-24 consists largely of 7-segment
LED displays. The DISP information is displayed on components E3, E4, E5, and E7; ADDRS information on components E9, E11, E12, E14; and extended memory information on component E15.
The relationship between the M PX signals and the display enable signals (0, 1, 2, 3, and 4) has been discussed and
is not repeated here (refer to Paragraphs 4.3.2.2 and 4.3.2.3). When an enable signal is generated, the corresponding transistor is turned on, supplying anode current to one or more of the LED displays. For example, if 0 goes low,
Q2 conducts, providing anode current for LED displays E3 and E9. Either E8 or E 13, each a decoder/driver, provides
high sink-current outputs that are applied to the LED cathodes. Thus, the octal information carried on the DISPLAY
lines or the ADDR lines is displayed by the correct component.

4-30

MPX A

MPX B

+5V
7490
E25
R3 (1)
R2 (1)
R1(O

8251
01 E22

...I

+5V

1
+5V

2
+5V

ROm r--CLK80 CLKO

MCLIK H

+5V

~Q' L«

,-,
l-'

olSP 3 E7

~
~

~
,-,
l-'

olSP 2

~
~

AooR 3

'-'
1_'

'--

,-,

E 14

I I

'--

+3V

+3V
gfedcba
7447A
E8
D C B A

DISPLAY 2 H

DISPLAY 1 H
DISPLAY 0 H

gfedcba
7447A
E16
D C B A

AooR 1 E11

I ,

'--

1_'

'--

I I

I_I

11
1

DISP 0.3

ADDR 2 E 12

,-,,-,

AooR 4 E 15

,-,,-,

olSP 1 E4

~ )Q2

ADDR 0
~

1-'

DEC 8251
9 fedc ba
7447A
E13
D C B A

BEMA2~~ ADDR2~~
BEMA 1 H

ADDR 1 H

BEMAOH-

AoDROH-

03
LO
LO
LO
LO
LO

02
LO
LO
LO
LO
HI

01
LO
LO
HI
HI
LO

00
LO
HI
LO
HI
LO

FO
LO
HI
HI
HI
HI

Fl
HI
LO
HI
HI
,HI

F2
HI
HI
LO
HI
HI

F3
HI
HI
HI
LO
HI

F4
HI
HI
HI
HI
LO

08-1290

Figure 4-24

ADDRS/DISP Readout Circuits

Table 4-5 relates the displayable octal digits to the input/output signal levels of the DEC7 447 A decoder/drivers.
while Figure 4-25 shows how the octal digits are derived in the 7-segment displays. When the digit 2 is to be displayed in one of the ADDRS LED displays. for example. output pins a. b. d. e. and g of E 13 go low. The LED segments with the corresponding designations are activated and the digit appears in .the readout.

Table 4-5
DEC7447A Input/Output Signals
Octal Number
C

0
1

2
3
4
5
6
7

LO
LO
LO
LO
HI
HI
HI
HI

Input Pins
B

LO
LO
HI
HI

LO
HI

LO
LO

HI
HI

Output Pins
e
d

LO
LO
LO
LO
LO

LO
LO

LO
LO
LO
LO
LO

g
HI
HI

HI
HI
HI

LO
LO

LO
LO
HI

LO
LO
LO

LO
LO
LO
LO
LO

LO
HI
HI
HI

7
08-1291

Figure 4-25

OCTAL Designations - Resultant Displays

4.3.2.6

Function Button Logic - Figure 4-26 shows the Function Button logic. The latch. E26. the BCD-to-decimal decoder. E29. and the gating logic. including hex buffers E28 and E31. are illustrated.

When a button is pushed. the binary code is clocked into the latch by the KEY F L signal. The latch output is decoded by E29 to produce an output signal that corresponds to the selected button (the 8251 function table in Figure
4-26 relates the decoder outputs to the function buttons). Note that the input at 03 of the decoder must be low.
This requirement can be met in one of two ways: First. if the CPU is not running and the PAN EL LOCK switch is in
the off position. any function button will enable! NAND gate E25B; second. if the CPU is running. the DISP button or
the LSR button will enable NAN D gate E25A. The second method ensures that the operator cannot inadvertently disrupt the CPU when it is in automatic operation (as will be seen. neither the DISP button nor the LSR button disrupts
operation).
The decoder output signal is applied to gating logic that generates the necessary control signals (the gating logic for
the DISP button is shown in a separate illustration. Figure 4-25). Table 4-6 lists the control signals generated by
each function button and gives a summary of the result achieved. Refer to Paragraph 4.6.4 for a discussion of the
CPU gating during console operations.

4-32

LD SR H
PULSE LA H

~---<~ (DR 2 )

+5V

KFUN 0 L
KFUN 1 L
K FUN 2 L
BRUN L

7475
RO(1)
DO
QUAD
FIF R1(t)
01 E26
R2(1)

R3(t)
03

R3(0)

PULSE LOAD
7 ADD L
DIS4
91NI L

INITIALIZE
(CR1)

8097
HEX
BUFFER

MEM START L
(AJ2)

-----KEY F L

13 KEY CNTL L

KEY CONTROL L
(DU2)

11 MS, IR DIS L

MS, IR DISABLE L
(CV1)

14
E31
12
DIS2

FUN L - - - - - - - - .

PAN LOCK L - - - - O

8251
BUTTON

OUTPUT

OISP

LSR

LXA

INIT

HLT,RUN

E NEXT/THIS

o NEXT/THIS

0lS2

INPUT

OUTPUT

HI
HI

3 BK DATA
CNTL L

E28

BREAK DATA
CONT L (BK 2)

DEP L

8097
HEX
BUFFER
7INI L

"XJ~------=-- I NO 1 L (CU2)

~)-_ _ _ _ _--1_LA

ENABLE L
(BM2)

7475

8097
0lS4

tn+1

GATE ENT L

INPUT OUTPUT

HI·Z

08-1292

HI·Z

Figure 4-26

Function Button Logic

Table 4-6
Function Button Control Signals
Function Button

Control Signal Generated

Signal Function

LSR

LD SR H

Load entry into Switch Register.

MS, IR DIS L

Asserts the Omnibus MS, IR DISABLE L signal, placing the
CPU in the DMA state and, thus, permits the console to
communicate directly with memory (refer to Paragraph
4.6.4, Data Break Transfers)'

GATE ENT L

Gates the entry from the number shift register to the console BUS lines.

LA ENAB L

Causes the Programmer's Console control to generate the
KCCN1 SR ENABLE L signal, thereby gating the entry
from the BUS lines to the Omnibus DATA lines.

IN1 L

Generates the IND1 L signal ensuring that only the entry is
placed on the DATA Bus. IND1 Land IND2 L determine
the type of information placed on the DATA bus during
TS1. The information can be any of the following:

LXA

IN01 L

IND2 L

DATA Bus Information

Status word (see Table 4-15 for the
Status word description)

MQ register contents

Logic 0 (HI)

AC register contents

PULSE LOAD ADD L

After the entry has been gated from the DATA bus to the
CPMA register, PULSE LA H causes the CPMA LOAD signal
to be generated, loading the entry into the register. Note
that buffer E31 generates PU LSE LOAD ADD L when KEY
STB H is asserted, which is quite some time after the entry
has been placed on the DATA bus (the top four outputs of
E31 are controlled by the enable input at DIS4, while the
bottom 2 outputs are controlled via DIS2).

MS, IR DIS L
GATE ENT L
LA ENAB L
IN1 L

See entry for LA.

KEY CNTL L

Causes the Omnibus KEY CONTROL L signal to be asserted. This signal and LA ENABLE L combine to gate the
entry from the DATA bus to the IF and DF registers of the
extended memory option.

4-34

Table 4-6 (Cant)
Function Button Control Signals
Function Button

Control Signal Generated

Signal Function

PULSE LOAD ADD L

Causes the extended memory control (M8317) to generate
a clock pulse that loads the entry into the I F and DF
register.

INIT

INI L

Asserts the Omnibus INITIALIZE L signal, causing the AC,
the Link, the interrupt system, and peripheral flags to be
cleared.

RUN

MEM ST L

Asserts the Omnibus MEM START L signal, causing the
CPU timing generator (TG) to start generating timing
signals.

ETHIS

MEM ST L

See'RUN'.

MS, IR DIS L

See 'LA'.

KEY CNTL L
BK DATA CNTL L

These two signals assert Omnibus signals KEY CONTROL L
and BREAK DATA CONT L, respectively; these Omnibus
signals, along with LA ENAB LE L, control CPU major register gating operations in the DMA state.
When BREAK DATA CONT L and KEY CONTROL L are
low and LA ENABLE L is high, the following sequence of
events occurs: During TSl the contents of the CPMA register are incremented and loaded into the PC register; during
TS2 the contents of the addressed memory location are
placed on the MD lines and loaded into the MB register;
during TS3 the Omnibus STOP L signal is generated causing
the TG RUN flip-flop to be cleared at TP3 time (the TG
halts in TS1, after TS4 operations have been completed see 'THIS L' for a description of TS4 operations).
The operator can cause the data contained in the MB register to be displayed in the DISPLAY readout by pushing the
MD button and then the DISP button. Alternatively, the
operator can push the console buttons in the following
order to examine a memory location: LA; MD; DISP;
ETHIS.

THIS L
(Generated by clock
timing logic)

Asserts the Omnibus MA, MS LOAD CONT L signal, preventing TP4 from loading the CPMA register. Thus, the addressed memory location remains unchanged and the
operator can modify the data by using the deposit function.

4-35

Table 4-6 (Cont)
Function Button Control Signals
Function Button

Control Signal Generated

ENEXT

DTHIS

DNEXT

Signal Function
This pushbutton generates the same signals as does ETHIS,
except for TH IS L. Hence, the CPMA register is loaded at
TP4 time and a new address is placed on the MA lines during
TS1 of the next timing cycle. The operator can use this
button to examine consecutive memory locations. The
following order is most advantageous: MA; MD; DISP;
ENEXT; ENEXT ... ; ENEXT.

MEM ST L

See 'RUN'.

MS, IR DIS L

See 'LA'.

GATE ENT L

Gates the entry from the number shift register to the console BUS lines.

DEP L

Asserts the console KCCN 1 SR ENAB LE L signal, which
gates the entry from the BUS lines to the Omnibus DATA
lines; the entry is placed on the CPU SUM lines and loaded
into the MB register at TP2 time. During the write half of
the timing cycle the entry is written into the addressed
memory location.

KEY CNTL L

When LA ENAB Land BK DATA CNTL L are high and
KEY CNTL L is low, the following sequence of events
occurs in the CPU major register gating: During TS1 the
contents of the CPMA register are incremented and loaded
into the PC register; during TS2 the DATA lines are gated
to the CPU SUM lines; during TS3 the STOP L signal is
generated, causing the RUN flip-flop to be cleared atTP3
time (the TG halts in TS1, after TS4 operations have been
completed - see 'THIS L' for a description of TS4 operations).

THIS L
(Generated by clock
timing logic)

Asserts MA, MS LOAD CONT L, preventing TP4 from
loading the CPMA register. Thus, the addressed memory
location remains unchanged.
This button generates the same signals as does DTHIS, except for THIS L. Thus, DNEXT can be used to deposit data
in consecutive memory locations.

4.3.2.7 OISP Button Logic - Figure 4-27 shows the logic associated with the DISP button. This button is used
when the operator wishes to display the contents of a register (AC. MQ. or SR). or the information carried by a bus
( DATA. M D). or STATE information. The pushbutton has two functions: It causes the appropriate console indicator to
light. signifying the source of the information being displayed; and it generates the control signals that gate the appropriate data to the display readout on the console.

4-36

STATE

STATUS

BUS

~ ~'~ ~'~ ~'C ~'C ~'C ~'~ ~
(

F1
F3
F2
74145
E17
02
01
03

FO
GATE SR L

74174
ENT 0 H

R5(1 )

ENT 1 H

Rl (1)

ENT 2 H

RO(I)

OISP 0 H

0lSP1 H

DISP 2 H

E36
CLK

MD L

b
EMODE

E30

.,..

~
MCLO CK L
BRU NL

MAO

0lS2

AOR LTH L

IND2 L

I
I
I

....

I N01 L

I
L... _ _ _ -'
74145

LO
HI

HI
HI

LO
HI

HI
HI

LO
HI

HI
HI

LO
HI

HI
HI

8251
DO

F4
LO

F5
HI

F6
HI

LO
HI

II X

I ~O

LO
HI

X = ~ON'T CARE

OSP LTH L

BT SI L

.....

NUM H

LXA

IN2L.

DIS4

E22

KEY S TB H

fP/oM'83'i61
5

DE~

BUS EN L

8097
E34
4

STATE L

BPOK H

,.. 03

,.. 12

OISP INH H E MODE L

8251
E29

L'4

f4p..-8251
E35

LO
HI

HI
HI

LO
HI

08 -1293

Figure 4-27

DISP Button Logic

Whenever a number button is pushed. the binary code for that button is entered in the number shift register; the
code is carried on the ENTO H. ENT1 H. and ENT2 H lines to the DEC74174 hex flip-flop (E36 in Figure 4-27).
When the operator pushes the DISP button. decoder E29 generates the DISP signal that enables KEY STB H to load
the binary code into E36. Hence. the code appears on the DISPO H. DISP1 H. and DISP2 H lines.
A DEC74145 decoder. E17. monitors the DISP lines and causes an appropriate indicator to light. The function table
in Figure 4-27 indicates the relationship between the DISP lines and the source indicators (note that the EMODE
flip-flop must be in the clear state for an indicator to be lighted; this flip-flop ensures that a lighted indicator is
turned off when the next number button is pushed).
A DEC8251 decoder. E35. and a hex buffer. E:i4. also monitor the DISP lines; these two components generate the
signals that cause the information to be gated to the DISPLAY readout. Table 4-7 relates the number buttons. the DISPO
H. DISP1 H. DISP2 H signals. and the control signals generated by E34 and E35. The top four entries (buttons 0 through
3) indicate that BUS EN L is asserted. along with some combination of IND1 Land IND2 L. BUS EN L causes information
on the Omnibus DATA lines to be gated to the console BUS lines (Paragraph 4.3.2.9). while the IND signals select the
type of information that is placed on the DATA lines by the CPU major register gating (refer to the LA entry in Table 4-6.
which relates IND signals and DATA bus information). The last three entries also indicate some combination of the IND
signals being generated; however. the signals fall into the "don't care" category in these situations. The MD l and STATE
L signals gate information from the MD bus and from selected Omnibus lines. respectively. onto the console BUS lines.
while the GATE SR L signal gates the console switch register contents to the BUS lines. The information on the BUS
lines is clocked into flip-flops in the multiplexer logic by the DSP LTH L signal (Figure 4-20) and displayed in the
DISPLAY readout.

Table 4-7
O.splay Control Signals
Button

DISPO H

OlSP1 H

DISP2 H

Control Signal (s)

O{AC)
HMQ)
2(BUS)
3(STATUS)
4(SR)
5(STATE)
6(MO)

LO
LO
LO
LO
HI
HI
HI

LO
LO
HI
HI
LO
LO
HI

LO
HI
LO
HI
LO
HI
LO

BUS EN L, INOl L, IN02L
BUS EN L, IN02L
BUS EN L, INOl L
BUS EN L
GATE SR L, INOl L, IN02L
STATE L, IN02L
MO L, IN01L

When a source has been selected for display. the source identity is loaded into the hex flip-flop E36. Hence. the
DISP lines reflect this identity until another source is selected for display. In some circumstances. the control signals
generated by E34 and E35 could impair operation. consequently. some means must be provided to prevent the signals from being generated in such circumstances. These means are provided by NAND gate E30. which. when inhibited. disables E34 and E35. The contents of a source are displayed during alternate periods of the MCLOCK L signal
(when the CPU is not running) or during TS1 of alternate timing cycles. The display information timeshares the BUS
lines with current address information that is displayed in the ADDR readout. This timesharing is accomplished by
the MAO flip-flop. which alternately enables and disables NOR gate E22; thus. E34 and E35 are disabled during the
time that the address information is being routed to the ADDR readout.
NOR gate E22 also inhibits E30 when the EMODE flip-flop is set. As noted earlier. a lighted indicator is turned off
by this flip-flop when a number button is pushed. More importantly. the control signals are negated so that the entry
can be viewed in the DISPLAY readout as it is being entered via the number buttons.

4-38

Another situation that requires E34 and E35 to be disabled arises when either the LA or the LXA pushbutton is activated.
In such a situation an address is placed on the BUS lines and gated to the Omnibus DATA lines; consequently. display
information must be kept off the DATA lines during the time that these functions are active. This is accomplished by NOR
gate E32. which inhibits NAND gate E30 when the LA or LXA signal is generated by decoder E29.
4.3.2.8 THIS, HLT, BOOT Logic - The logic shown in Figure 4-28 has several functions. Consider the HLT/SS
pushbutton. If the CPU is running when the operator pushes this button. the Omnibus STOP L signal is asserted and the
RUN flip-flop is cleared at TP3 time (Figure 4-3); the CPU stops in TS 1. If the CPU is stopped when the button is pushed.
not only is the STOP L signal asserted. but also the MEM ST L signal (Figure 4-28); hence. the CPU executes one timing
cycle before stopping in TS1. Note that the PANEL LOCK L signal must be negated for the DEC8097 hex buffer to
operate. Thus, the CPU cannot be halted when the PANEL LOCK switch on the Limited Function Panel is in the up
position. Furthermore. as Figure 4-26 shows. if the PANEL LOCK switch is on when the CPU is stopped. the processor
cannot be started.

rI p/O
--"
M8316 I
SHLT L

~~~-~~------_Q14

BPOK
...------H

KEY STB H
NUM H - - - - n

SING STE P L ---+i>o+STOP L (DS2 )

B F SW L---+4:>o+SW L(DV2)

I
I

FUN L
12
D1S4

I
I

~ 1".-.. J
L ___ J

MA,MS LOAD
1 1 n - - - THIS L~CONTL(BH2)
D1S2
.

8TS1 L
E THIS

S THIS L

8097

01S4,2 'INPUT

o THIS

PAN
E26
R3(O)

Figure 4-28

LOCK L

La
HI

I
,

La
-

I OUTPUT I
I
,

La
HI-Z

08-1294

THIS. H LT. BOOT Logic

Both the ETHIS and the DTHIS pushbuttons start a timing cycle. The single cycle that is executed differs from that
executed by the ENEXT/DNEXT functions in one way. i.e .. the memory address is not updated when the THIS functions are used. The THIS flip-flop. which is clocked at the end of TS1. is cleared when either of the THIS buttons is
pu_shed; thus. the MA.MS LOAD CONT L signal is asserted. preventing the CPMA LOAD signal from being generated at TP4 time of the timing cycle.
The dc set input of the THIS flip-flop is connected as shown to prevent improper operation should the ETHIS or
DTHIS button be pushed by mistake while the CPU is running. The dc set line is held low when the RUN L signal is
asserted. preventing the flip-flop from being cleared by the BTS1 L signal should STHIS L be inadvertently
generated.
The BOOT pushbutton enables the operator to load bootstrap programs. A low-to-high transition of the Omnibus SW L
signal causes the bootstrap option control (M8317) to initiate a bootstrap operation. provided the CPU is not running. To
bring about this transition of the SW L signal. the operator must push the BOOT button twice. The first push causes
NAND gate E21 to set the BOOTF flip-flop (the KEY STB H pulse is generated when BOOT is pushed. but neither NUM H
nor FU N L is asserted); the second push causes the flip-flop to be cleared. Thus. the SW L signal first goes low and then
goes high. initiating the bootstrap operation.

4-39

4.3.2.9 Console Control Logic - The Console Control logic is part of the 1/0 Option board (MS316) that plugs into the
POP-S/A Omnibus. Data is transferred between the Omnibus and the console logic via the Console Control logic. The
complete logic drawings for the console control lire included in Appendix H of this manual. Figures 4-29 and 4-30 show
portions of that logic to illustrate how data is handled by the control.

MD.3 L

MDt

BUS 4

BUS t

F.3

BUS 3

MD10 L

BUS 6

BUS 9

BUS 10

BUS 11

BRK IN PROG L

MD DIR L

IR0 L

BUS e

I/O PAUSE L

MD6 L

BUS 2

MD9 L

BUS 5

IR 2 L
F1

MD5 L
F2

EL
MD3 L

IR1 L

DL
MD2 L

MDe L

MD4 L

BUS 0'

MD7 L

F0'

BREAK
DATA CONT L

MDll L

BUS 7

BK CYCLE L

8234

STATE L
BBUF TSI H

-----_-4

o----+-- KCCNI STATE ENA L

KCCNI SR
ENABLE L

HI
HI

0 - -.........-

Fn
Bn
An
Bn
HI

KCCNI MD ENA L

MD L

Figure 4-29 Console Control Logic -

STATE. M 0

Figure 4-29 shows how STATE data and data carried by the MD lines are placed on the console BUS lines. The
DEC 8234 multiplexers are controlled by the two enable signals. KCCN 1 M DENA Land KCCN 1 STATE ENA L.
When the operator pushes the appropriate console button - M D or STATE - and then pushes the DI SP button. either MD L or STATE L is asserted by the DISP button logic. If the CPU is in TS1 and KCCN 1 SR ENABLE L is negated. the applicable data is gated onto the BUS lines.
Logic that performs a function similar to that of Figure 4-29 is shown at the top of Figure 4-30. Multiplexer E1
places either MA bus information or DATA bus information on the BUS lines. Only the multiplexer that accommodates bits 0 through 3 is shown; bits 4 through 11 are handled in like manner. Remember that MA bus data is
displayed during alternate periods of the MCLOCK L signal when the CPU is halted. or during TS1 of alternate timing cycles when the CPU is running. The information on the DATA bus can be displayed during those alternate periods when MA bus data is not displayed. If the operator wants to view the contents of the MQ register. for example.
he or she pushes number button 1 and then the OISP button. The BUS EN L signal is asserted. the MQ contents
are placed on the BUS lines and displayed in the DISPLAY readouts.
The foregoing operation. as well as those carried out by the logic in Figure 4-29. depends on the KCCN 1 SR ENABLE L signal being negated. The logic that generates KCCN1 SR ENABLE L is shown at the bottom of Figure 430. This signal gates Bus-lines information onto the DATA bus in three situations: When either the LA or the LXA
pushbutton is activated. generating LA ENAB L and causing the entry to be loaded into the CPMA register; when
either the DTHIS or the DNEXT pushbutton is activated. generating DEP L during TS2 and causing the entry to be
loaded into the MB register; or. when either an LAS (7604) or an OSR (7404) operate instruction is programmed.
generating SR DATA L during TS3 and causing the result of the specified operation to be loaded into the AC
register.

4-40

MA 0 L
DATA 0 L

BUS 0

BUS I

BUS 2

BUS 3

MAIL

8234
SO

LO
HI
LO
HI

LO
LO
HI
HI

Ii
Po
Ii

DATA 1 L

DATA 2 L

8234
El

MA 2 L

MA 3 L
DATA 3 L

KCCNI MA ENA L
KCCNI DATA
ENA L
KCCNI SR ENABLE L

BUS EN L

BUS 0

8235
SO

An Bn
LO
LO
Bn
HI
LO
HI- ~LO I---~~HI

DATA 0 L

DATA I L

DATA 2 L

DATA 3 L

BUS I

BUS 2

HT-

+5V--~~--~------~

KCCNI SR
ENABLE L

FL
INTERLOCK L
USER MODE L
MOO L - - - - < l I
MOl L - - - - - Q I
MD2L----QI
MD3L---0I
MD9L---0I
MOIl L
08- 1296

Figure 4-30

Console Control Logic-MA. DATA, SR ENABLE

4.4 INSTRUCTION DECODER
Logic within the 10, monitors the M 0 lines, decoding the information thereon and generating major register gating
control signals. The gating control signals are developed largely in response to basic instructions, CPU major states,
and time states and time pulses. In addition, Programmer's Console operations and 110 transfers can control major
register gating to some extent.
The ID logic (Figure 4-16) includes the Instruction Register, the Major State Register, the AC Register gating, and a
number of Read-Only Memories (ROMs). The ROMs playa most important part in the CPU operation. Major register
gating responds, basically, to program instructions or as a result of directions entered manually at the Programmer's
Console. Program instructions include memory reference instructions, operate instructions, and lOT instructions; each

4-41

of these types of instructions can be subdivided further. Furthermore. each instruction behaves differently depending
on the particular major state and time state. Consequently. major register gating control signals must be generated
under a variety of circumstances. A most convenient method of accommodating such an abundance of variables is to
devote a ROM to a significant set of circumstances. Thus. we have ROM D dedicated to operate microinstructions
during TS3. ROM J responding to Processor-lOT instructions during TS4. ROM F decoding skip and link instructions
during TS3. and so on.
The ROMs are illustrated in Figures 4-31 through 4-38 as they appear in the logic diagrams. All except ROM F (a
1024-bit ROM) are 256-bit ROM organized as 32 8-bit words selected by a 5-bit input code. Pins 10 through 14
are the input pins. pin 14 representing the most significant bit of the input code. Pins 1 through 7 and 9 are the output pins. while pin 15 is an enable input (a low voltage applied to this pin enables the ROM to function). For ROM F
the input pins are 1 through 7 and 15 (15 is most significant). the output pins are 9 through 12 (10 and 12 are not
used). and the enable pins are 13 and 14.

LA ENABLE L
KEY CONTROL L
BREAK DATA CONT L
T0
T1

SEL C L

SEL B L

SEL A L

13
ROM
A
E69
DMA

CARRY EN L
STOP L

PC EN L

MA EN L

MD EN L

PAGE EN L

AND EN L

ISZ SKI P TST L

7442
DCDR
E71

PC LD EN L
00

DATA CMP L

DATA ENA L
EL
DL
FL

DMA L

03
LO
LO
LO
LO
LO
LO

02
LO
LO
LO
HI
HI
HI

01
LO
HI
HI
LO
LO
HI

00
HI
LO
HI
LO
HI
LO

7442
F1
.F2
HI
LO
HI
LO
HI
HI
HI
HI
HI
HI
HI
HI

F3
HI
HI
LO
HI
HI
HI

F4
HI
HI
HI
LO
HI
HI

F5
HI
HI
HI
HI
LO
HI

F6
HI
HI
HI
HI
HI
LO
08 -1297

Figure 4-31

7
INT IN
PROG L

13 ROM B
E57

I F SET L

OL
FL

6
5

ROM A Logic

SEL C L
PC EN L

SEL B L
SEL A L
CARRY
EN L

12ADDRESS
UPDATE
11

MA ENL

02 7442 F4
DCDR
01 E71

MD EN L
PAGE EN L

AND EN L

lSZ SKP TST L

FL
TS4 L
NOTE:
For 7442 function table see ROM A .
08-1298

Fi~lure 4-32

ROM B Logic

4-42

SEL CL}
IRO L
IR1 L

SEE ROM A
SEL B L FOR 7442 DC DR

SEL A L
ROM
C
E70
INSTR

IR2 L
E L

F L
10

DATA CMP L
ENA L

E L
DL
MDO'MD2 L
74S139
A1

ENB1 B1
HI

LO
LO
LO
LO

FA2
HI

LO
LO

08-1299

Figure 4-33

ROM C Logic

MD3 L

MQ CLR EN L

7
MD4 L

MD5 L

MQ LD EN L

ROM 0

MQ -

BUS L

CARRY EN L

AC LD. EN L

E72
OPR

AC- BUS L
DATA CMP L

MOIl L

DATA ENA L

MD0'MD2 L
MD0 L

FA0

MD2 L
E58
74S139
MOl L

74S139
ENB1

ENBI

LO
LO
LO
LO

F L

T0
Tl

FAO
HI

LO
LO

08-1300

Figure 4-34

ROM 0 Logic

4-43

1:/0 PAUSE H
GTF H
C2 L

SELC L (SEE ROM A FOR 7442 DCDR)

13
ROM
E

E76
Cl L
CO L

1/0
DATA CMP L

08-1301

Figure 4-35

ROM E logic

ADLK L
ROM

F
E~3

SKIP/LINK

I SKIP L

TS3 L
08-1302

Figure 4-36

IRe'L
IR1 L
IR2 L
M03 L

14
13
12
11

ROM F logic

OPIL
OP2+0P3L
ROM
H

lOT XFER L

STATUS L

INT OFF L

E63
OPRIIOTI
MAJOR STATE
ENABLE

1:/0 L
M09 L
E SET L

M010 L

o SET L

MOl' L

13
12
11

ROM J
E38
PROCESSOR
lOT

1:NT ON L
SRQ H
SKON H
GTF H
RTF H
CAF H

DL
08-1303

Figure 4-37

08-1304

ROM H logic

Figure 4-38

4-44

ROM J logic

Note that most of the ROM input signals are taken from the MD lines. the Instruction Register (lR lines), and the
Major State Register. For the moment it is enough to be aware of the logic shown in Figures 4-31 through 4-38. In
Paragraph 4.5. tables are provided that enable one to determine easily the input/output relationship for each ROM
and to relate the ROM outputs to the major registers and gating. ROMs Hand J are used for other than major register gating purposes and are discussed in Paragraphs 4.4.2 and 4.6. respectively.

In addition to the logic already mentioned. the ID includes logic that supplements the ROMs for special purposes.
This logic is discussed in paragraphs following the Instruction Register and Major State Register descriptions.

4.4.1
Instruction Register Logic
The Instruction Register logic is shown in Figure 4-39. Operations in each CPU Major State are determined by the
type of instruction contained in the addressed memory location. This instruction is placed on the MD lines during
TS2 of a Fetch cycle. M D bits O. 1. and 2. which identify the basic instruction. are applied to the B inputs of the
DEC74157 multiplexer. During TS2. these input signals are gated to the multiplexer outputs and applied to the data
inputs of the quad flip-flop. Because the CPU is in the Fetch state. both enabling inputs of the quad flip-flop are low.
and at TP2 time the individual flip-flops are clocked. The flip-flop outputs. which represent the basic instruction (see
the I R Table). are distributed throughout the CPU logic on the I R lines.

.r--

OUAD FF BT10
E50
DATA
ENA

MOO L

INT IN
PROG H

FO
Fl

F L

Bl MUX 74157
A2

+3V

E51

IR,Z
FLAG

AC ZERO L
A3

MS,IR EN L

MD2 L

IRO L

IRI L

IR2 L

MOl L

10
OUT
CONT
CLR

TP4 H
TS4 L

74157
SO

LO
LO
HI

LO
HI

X
X

LO
HI

LO
HI
LO
HI

LO
HI

X
X

TP2 H

aT10
OUT
CONT
ENA
LO
LO
LO
LO
LO
HI

DATA

NO
OUT
LO
HI
NO CHANGE
HI·Z

IR TABLE
IR2
HI

INST

IRO
HI

IR1
HI

HI
HI

HI
LO

LO
HI

TAD
ISZ

HI
LO
LO
LO
LO

LO
HI
HI
LO
LO

LO
HI
LO
HI
LO

DCA
JMS
JMP
lOT

AND

OPR
08-1305

Figure 4-39

Instruction Registers Logic

4-45

During TS4, the signals on the A inputs of the multiplexer are gated to the flip-flop inputs. Providing an interrupt has
not been honored, the flip-flop is placed in a "no change" state; thus, the flip-flop outputs remain unchanged at TP4
time. However, if the INT IN PROG H signal had been asserted at TP3 time, the flip-flop's contents are changed at
TP4 time. The I R lines then represent the J MS instruction and, because the Major State register logic asserted the E
L signal at the same TP4 time, the CPU enters the Execute state and performs the JM S operations. An interrupt can
be honored during any major state timing cycle, as long as the cycle is the last one of the instruction; therefore, the
I R lines can be changed at TP4 of any state, as the logic demonstrates.
The M S, I R EN L signal can be negated at TP4 time by a data break peripheral or by the Programmer's Console. The
flip-flop outputs are removed from the IR lines and the CPU enters the DMA state.
When MS, IR EN L is asserted again, the IR lines assume the states that existed before the DMA interruption and
the interrupted instruction operations are resumed. If the MS, I R EN L signal is negated at the same time that the I R
flip-flops are clocked to the JMS state (as a result of INT IN PROG H being asserted). the CPU enters the DMA
state. On completion of the DMA operations, the CPU enters the Executive state and performs the JMS operation.
4.4.2 Major State Register Logic
The CPU operations are grouped functionally into the four major states - Fetch, Defer, Execute, and DMA. The first
three are entered actively when flip-flops in the Major State Register logic are set (only one major state flip-flop may
be active at any given time). The fourth state, DMA. results when none of the first three has been entered.
The logic is shown in Figure 4-40 and includes ROM H. Table 4-8 relates the input and output Signals of ROM H,
the basic instruction involved, and the present and next CPU Major State. For example, input code 22(8) occurs during the Fetch cycle of a DCA instruction, resulting in the E SET L signal being asserted by the ROM. Note that the
INPUT SIGNAL LOW column indicates the signals that must be low to achieve the desired input code (this convention is chosen because most of the Omnibus signals are active when low). Three stages of the 8T10 quad flip-flop
are used to generate the F L D L, and E L signals. The quad flip-flop is enabled by the MS, I R EN L signal; when
this signal is negated (MS, IR DISABLE L has been asserted by a peripheral or by the Programmer's Console) the
flip-flop outputs are removed from the output lines and the DMA L signal is asserted.
The flip-flops are clocked by the CPMA LOAD signal, which is generated during automatic operation at TP4 time
and during manual operation when the LA button is pushed. Some type of manual operation always precedes automatic operation; for example, to initiate automatic operation of a stored program, the operator must load the CPMA
register with the starting address of the program. He loads this address by pushing the console LA button, causing
the Programmer's Console logic to assert first the MS, IR DISABLE L signal and, second, the PULSE LA H signal.
MS, IR DISABLE L causes the DMA L signal to be asserted. This action results in ROM H being disabled; consequently, both the D SET L signal and the E SET L signal are negated, and IF SET L in the Major State register
logic is asserted. Because of gating differences in the Programmer's Console logic, MR. IR DISABLE L is asserted
much earlier than PULSE LA H. Thus, IF SET L is low when CPMA LOAD goes high, and the Fetch stage of the
quad flip-flop is set asserting the F L signal. If the operator now pushes the RUN button, the CPU begins automatic
operation in the Fetch state of the addressed instruction.
Since all instructions begin in the Fetch state, this state is entered from any state that completes an instruction.
Thus, Fetch can be entered from the Execute state of a 2- or 3-cycle instruction; Fetch can be entered from the Defer state of a 2-cycle instruction; Fetch can be entered from the Fetch state of a one-cycle instruction; finally, Fetch
can be entered from the DMA state. When tho Fetch state of a multi-cycle instruction has been completed, either a
Defer state or an Execute state follows, unless the operator pushes the H LTISS button or a data break device
causes suspension of program control. Either event can cause a halt or interruption when the Fetch state is completed; then the DMA state is entered. When operations in this state have been carried out control is returned to
the program, and the multi-cycle instruction can be completed.
ROM H provides the outputs that control the Major State Register flip-flops; Table 4-8 relates these outputs to the
input select codes. The table shows those circumstances in which either the D SET L signal or the E SET L signal is
asserted. When neither of these signals is low, I F SET L is asserted. For example, ROM H is disabled during the Execute state; consequently, IF SET L is asserted during all Execute cycles.

4·-46

F SET L
- F SET L
OUAD FF aT1 0
DATA ENA

E SET L

DMAL
INT IN
PROG L

o SET L

E62

AI,F,
D,E

IRO L

OPI L

IR1 L

OP2 +OP3 L

IR2 L

IOT XFER L

MD3 L

MS1

MSO

E SET L
10

OUT CONT

CLK

D SET L

CLR

MS ,IR DISABLE L
8T10

MS ,IR EN L
TP4

CPMA LOAD

MA,MS LOAD CONT L

nO
IN
LO
HI

DATA
ENA
LO
LO

OUT
CONT
LO
LO.
HI

nQ
OUT
LO
HI
HIGH Z

PULSE LA H
KEY CONT L
08-1306

Figure 4-40

Major State Registers Logic

Table 4-8
ROM H Input/Output Signals
(ROM is enabled for Fetch or Defer Major State)
Input
Code
0
2
4
6
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37

IRO L
X
X
X
X

Input Signal Low
IR1l IR2l MD3L
X
X
X

X
X

X
X
X

X
X

X
X
X

X
X
X
X

X
X

X
X
X

X
X

X
X
X
X

Present Major State/Next Major State

OP2 + OP3 L
OP1 L
lOT XFER L
lOT XFER L
D SET L

OPERATE
OPERATE
lOT
lOT
JMP
JMP
JMP
JMP
JMS
JMS
JMS
JMS
DCA
DCA
DCA
DCA
ISZ
IS2
ISZ
ISZ
TAD
TAD
TAD
TAD
AND
AND
AND
AND

Fetch/Fetch (I F SET L is low)
Fetch/Fetch (I F SET L is low)
Fetch/Fetch (I F SET L is low)
Fetch/Fetch (I F SET L is low)
Fetch/Defer
Defer/Fetch (IF SET L is low)
Fetch/Fetch (I F SET L is low)
Defer/Fetch (IF SET L is low)
Fetch/Defer
Defer /Execute
Fetch/Execute
Defer /Execute
Fetch/Defer
Defer /Execute
Fetch/Execute
Defer/Execute
Fetch/Defer
Defer/Execute
Fetch/Execute
Defer /Execute
Fetch/Defer
Defer /Execute
Fetch/Execute
Defer /Execute
Fetch/Execute
Defer /Execute
Fetch/Execute
Defer /Execute

X
X
X

Basic Instruction Programmed

X
X

X
X
X
X
X
X
X
X

ROM
Output Signal

X
X

X
X
X

X
X

D SET L
E SET L
E SET L
E SET L
DSET L
E SET L
ESET L
ESET L
D SET L
E SETL
ESET L
ESET L
DSET L
E SET L
E SET L
ESET L
D SETL
ESET L
ESET L
ESET L

Cc:msider the table entry for input code 21 (8), for example. This combination of input sigl1als is obtained when the
CPU is in the Defer state of an indirectly-addressed DCA instruction. DCA is normally a 2-cycle instruction, but indirect addressing means that the Defer state must be completed before the instruction is executed. Thus, the E SET
L signal is asserted during the Defer cycle, and the E L signal is generated at TP4 time.
Note that the INT IN PROG H signal asserts E SET L. INT IN PROG H is asserted when an interrupt request is honored by the interrupt logic of the timing generator module. At TP4 time the Execute state is entered; E SET L can be
asserted in this manner during either a Fetch, a Defer, or an Execute state, provided the particular state is the final
state of an instruction.
As shown earlier, Fetch can be entered from the DMA state. If MS, IR DISABLE L is asserted because manual operations are being performed, Fetch always follows DMA. However, if MS, IR DISABLE L has been asserted by a data
break peripheral. the Fetch state mayor may not follow the DMA state. A data break operation can begin at the end
of any Major State. Program control is halted for one timing cycle (control can be halted for three cycles. as well; for
convenience. a halt of one cycle is considered). When the Data transfer has been completed. program control is reestablished and the previously interrupted operation continues. An example of the interrupting process is given in the
following paragraph.
If operations are being carried out in the Fetch state of a 2-cycle DCA instruction, the E SET L signal is asserted. If
a peripheral initiates a data break during this Fetch state. MS, IR DISABLE L is asserted at TP4 time. At the same
time. CPMA LOAD is produced by TP4 and MA. MS LOAD CONT L, and Execute flip-flop is set; however. MS. IR
DISABLE L removes the flip-flop outputs from the output lines and the DMA state is entered. instead of the Execute
state. It could be assumed that the next TP4 pulse (of the DMA state) would set the Fetch flip-flop; however. at
TP1 of the DMA state the peripheral asserts MA. MS LOAD CONT L thereby preventing the TP4 pulse in question
from setting the flip-flop. Instead, this TP4 negates MS. IR DISABLE L. The Execute flip-flop is still set and. thus. E
L is asserted. Operations begin in the Execute state of the interrupted instruction. At TP1 of this state, MA. MS
LOAD CO NT L is negated. completing the return to uninterrupted operation.

4.4.3 DATA ENA/DATA CMP Logic
Figure 4-41 shows supplementary logic that generates the DATA ENA L and/or the DATA CM P L signals. These signals are used in major register gating to select the information on the DATA lines or the complement of that information for application to the adders; alternatively. a logic 0 may be gated to the adders. Table 4-9 relates the state of
the two signals to the type of data gated to the adders.

TO ROM A,C, D,E
"X)o....-L..---DATA ENA L

T52 L

DATA CMP L

F L

TO ROM A,C,D,E
08-1307

Figure 4-41

Data ENA/Data CMP Logic

As Figure 4-41 shows. ROMs A. C, D, and E can control the two signals. and do in all but one instance. i.e., during
TS2 of a Fetch cycle. In this instance the two signals cause the AC contents to be gated to the adder and placed on
the major register gating SUM lines (AC- > BUS L is asserted by the logic shown in Figure 4-44). If an SZA instruction has been issued. the AC contents will be tested by the Skip logic (Paragraph 4.5.3).

4-49

Table 4-9
DATA ENA/DATA CMP Gating
Signal

Data Transferred to Adder

DATA ENA L

DATA CMP L

HI
HI
LO
LO

HI
LO
LO
HI

HI (Logic 0)
HI (Logic 0)
Complement of information on DATA lines
Information on DATA lines

4.4.4 Address Update Logic
Figure 4-42 shows supplementary logic that generates PC LD EN L CARRY EN Land SEL B L. All three signals
are used to implement the MA + 1> PC operation that takes place during TS 1 of each Fetch cyle and during TS 1 of
selected DMA cycles.

PC LD EN L

CARRY EN L

LA E NA BLE L ----t-~~-t

SEL B L
(MA EN Ll

NOTE:
T0 LOW = TS1 or TS4
T1 LOW=TS1 or TS2
08-1308

Figure 4-42

Address Update Logic

During TS1 the SEL BLand CARRY EN L signals are asserted. assuming LA ENABLE L is high. SEL B L causes
decoder E71 (Figure 4-31) to assert the MA EN L signal. gating the CPMA address to one input of the adders
(DATA CMP L and DATA ENA L provide a logic 0 at the other adder input). CARRY EN L enables the Carry In logic
to add 1 to the address. If the CPU is in a Fetch cyle. PC LD EN L is asserted by NAND gate E55. enabling the PC.
AC. MQ CLK signal to load the PC register at TP1 time. However. if the CPU is in the DMA cycle. PC LD EN L is
asserted by ROM A (Figure 4-31); again. the PC register is loaded at TP1 time. This operation is carried out whenever the console E NEXT. D NEXT. E THIS. or D THIS button is pushed.
When the operator loads an address with either the LA pushbutton or the LXA pushbutton. the console logic asserts
the LA ENABLE L signal to prevent spurious incrementing of the address. LA ENABLE L can also be asserted during
the BOOT (or NON-STOP) DEPOSIT procedure. In this procedure PC LD EN L. CARRY EN L. and SEL BLare generated by ROM A. the PC register is incremented at TP 1 time. data is written into memory. and the CPU continues to
run (unlike the normal deposit function that halts after a single timing cycle).

4·50

4.4.5 Major Register Load Signal Logic
The logic that generates the major register load signals is shown in Figure 4-43. At the top is the logic that produces the clock signal for the PC, the AC, and the MQ registers. When a particular register's load enable signal (PC
LD EN L, for example) is asserted, the PC, AC, MQ CLK signal causes data to be loaded into that register. Table 410 lists the timing pulses and shows the conditions under which a particular pulse causes PC, AC. MQ CLK to load
a given register. Included is the reason each register is being loaded.

MD10 L
OPl L

PC,AC,
MQ CLK

BUS
STROBE
L _ _ _ _ _-J

TP4 H
MA ,MS LOAD CONT L -~__
CPMA LOAD
PULSE LA H
KEY CONT L

+3V

MD DIR L

TP2 H --.,.-~

L - - - - i - - - - - - - - - ( M B CLK)
TPl L
08-1309

Figure 4-43

Major Register Load Signal Logic

Logic that procudes the CPMA LOAD signal appears in the middle of Figure 4-43. The CPMA register is loaded at
each TP4 time. providing the MA. MS LOAD CONT L signal has not been asserted, and when the operator loads an
address with the Programmer's Console LA pushbutton.
When the LA button on the console is pushed. the console logic causes the entry to be gated to the CPMA register.
PULSE LA H is asserted and. since KEY CONT L is negated by the LA pushbutton. the CPMA LOAD signal loads
the address into the register.
Each TP4 pulse generates a CPMA LOAD signal when MA. MS LOAD CONT L is high. MA.MS LOAD CONT L can
be asserted by a data break peripheral to ensure that the CPU returns to the correct major state at the end of the
data break (Paragraph 4.6.2). Or, MA.MS LOAD CONT L can be asserted by the console E THIS or D THIS pushbutton. When either of these pushbuttons is activated, the address selected for examining or depositing is incremented
and loaded into the PC register at TP1 time; hence. MA.MS LOAD CONT L prevents the incremented address from
being loaded into the CPMA register at TP4 time.

4-51

Table 4-10
PC, AC, MQ ClK Signal loading
Timing Pulse
TP1

TP3

Necessary Condition

Fetch cycle

PC/Updated address stored in PC

DMA cycle

PC/Updated address stored in PC

DMA cycle

PC/An Auto-Start address provided by the Programmer's
Console is loaded from the DATA lines; it is transferred
into the CPMA at TP4 time

Defer cycle

PC/During a JMP I instruction, the address to which program control is to be transferred is loaded into the PC

Fetch cycle

PC/During a JMP instruction, the address to which program control is to be transferred is loaded into the PC
AC or MQ/Operate instructions can cause either or both
registers to be loaded

Execute cycle

PC/During a JMS instruction, the address to which program control is to be transferred is loaded into the PC
AC/During a DCA instruction, 0000 is loaded into the
AC, clearing it.
During a TAD instruction, the result of the addition of
the AC contents and the contents of the addressed
memory location is loaded into the AC
During an AND instruction, the result of the logicalANDing of the AC contents and the contents of the
addressed memory location is loaded into the AC

BUS STROBE L

lOT transfer in progress

AC or PC/Information placed on the DATA lines by a
peripheral is loaded into the AC or the PC

TP31/2

RTR or RTL microinstruction programmed

AC/The contents of the AC register are shifted left or
right by one place

RAR,RA~RTR,orRTL

AC/The contents of the AC register are shifted left or
right by one place; if RTR or RTL, this is the second
shift to occur during TS4

TP4

microinstruction programmed

4·52

The logic that generates the MD DIR L signal is shown at the bottom of Figure 4-43. Each TP1 pulse clears the DIR
flip-flop, asserting the MD DIR L signal during the read portion of the memory cycle; thus, data in the addressed
memory location is placed on the MD lines. At TP2 time the DIR flip-flop is kept in the clear state if the instruction
is in the Fetch state; hence, the data placed on the MD lines during the read half of the memory cycle is rewritten
in the same location during the write half of the cycle. If the instruction is in other than the Fetch cycle, the DIR flipflop is set at TP2 time and MD DIR L is negated. This action gates the contents of the MB register, which is loaded
at each TP2 time, onto the MD lines; consequently, the MB register becomes the source of the data that is written
into memory during the write operation.

4.4.6 AC Register Control logic
The logic in Figure 4-44 controls the AC register during many of its possible manipulations. Shown at the top of Figure 4-44 is logic that generates the AC->BUS L signal. ROM D and ROM E are the primary producers of AC->BUS
L. The logic shown is needed for isolated events. Note that the gating of the signals results in AC- > BUS L being
asserted during TS2 of a Fetch cycle, and during TS2 or TS3 of an Execute cycle.

ROM 0

M51

O-........-AC-BU5L

M010 L
D---BSW L

M08 L

OPl L

MD9 L

AC LD EN L

RR EN

LINK RR EN

LINK RL EN

RL EN

80
A0
A2
lOT XFER L

T53 L

74S158
MUX
Ese

OPl L
TS4 L
NOTE:
T21 HIGH =T52 or TS3
11 HIGH = T5 3 or T54
08-1310

Figure 4-44

AC Register Control Logic

In the first instance, a Fetch cycle, the AC register contents are placed on the DATA lines during TS2, gated to the
adders by the DATA CMP L and DATA ENA L signals (Figure 4-53), and placed on the SUM lines. The SUM lines
are tested by the Skip logic (Paragraph 4.5.3) in carrying out the SZA microinstruction. If the AC contents were
0000, the ZERO L signal is loaded into the Z-fla9 flip-flop at TP2 time and the next program instruction is skipped.

4-53

In the second instance. an Execute cycle. two uses are made of the AC- > BUS L signal. For one. the AC contents
are placed on the DATA lines during TS2 of the DCA instruction. gated to and loaded into the M B register at TP2
time. and written in the addressed memory location. For another. the AC contents are placed on the DATA lines during TS3 of the TAD instruction. gated to the adders. where the add operation is accomplished. and loaded into the
AC register at TP3 time.
Below the AC->BUS L logic is the byte-swap logic that generates the BSW L signal in response to the BSW microinstruction(7002). When the BSW instruction is issued. the AC contents are placed on the DATA lines during TS3.
gated to the adders. and put on the SUM lines. The BSW L signal. which is asserted at TP2 time. causes the information on the SUM 0 line to be gated to the input of AC bit 6. and the information on the SUM 6 line to be gated
to the input of AC bit O. Likewise. At bits 1 and 7. 2 and 8. 3 and 9. 4 and 10. and 5 and 11 are swapped. At TP3
time. the AC is loaded and the byte swap has been carried out.
At the bottom of Figure 4-44 is the logic that controls the loading and shifting of the AC register and the Link (the
LNK RR EN and LNK RL EN signals are used to control the Link and are explained in Paragraph 4.5.4; they are
shown here only for information). The AC register comprises DEC74S 194 bidirectional shift registers that can be parallel loaded and shifted either left or right. The signals RR EN and RL EN. generated by multiplexer E68 in Figure 444. determine the mode of operation for the register. as outlined below.

RR EN

RL EN

AC Register Mode

HI
HI

LO
LO

Parallel-load
Right-shift
Left-shift
Do-nothing

LO
LO

The AC register can be loaded from the SUM lines at TP3 times. at BUS STROBE L time. at TP3 1/2 time (Paragraph 4.4.5). i.e .. during TS3 and TS4. Most of the AC operations involve parallel loading in TS3. During. TS3 the
state of the AC LD EN L signal determines the state of the RR EN and RL EN signals. If AC LD EN L has been asserted by ROM C. D. or E. RR EN and RL EN place the AC register in the parallel load mode and the register is
loaded at TP3 time or at BUS STROBE L time.
During TS4 of a Group 1 operate microinstruction. the state of MD bits 8 and 9 determine the state of RR EN and
RL EN. respectively. This device permits the rotate instructions (RAR. RAL. RTR. and RTL) to shift the AC register
right or left. For example. the RAR (7010) instruction - rotate AC and Link right one - asserts the MD8 L signal.
while negating the MD9 L signal. As a result. R R EN is high and RL EN is low. producing a right shift of the AC
register at TP4 time (AC11 is shifted into the Link register). If RTR (7012) - rotate AC and Link right two - is programmed. the AC is clocked at TP3 112 time as well as at TP4 time (AC1 0 is shifted into the Link register).
4.5 MAJOR REGISTER GATING
The major registers of the PDP-8/A perform all the operations needed to implement program instructions. For example. the PC register keeps track of the program steps. the CPMA register selects the memory location provided by
the PC. and the AC register uses the data in the selected memory location to carry out arithmetic operations. Information of one type or another (data. addresses. etc.) must be exchanged by the major registers or transferred between a register and some source or destination. such as a peripheral or core memory. The major register gating
network. illustrated in block diagram form in Figure 4-45. enables this exchange and transfer of information. The
block diagram shows the gating for bit 0 of the 12-bit data word; all other bits are gated similarly and differences
that exist are noted in subsequent discussions.

4-54

CLR
LO
HI
HI
HI
HI
HI
HI
HI

HI
LO
LO
HI
HI
LO
-

HI
HI
HI
LO
LO
LO
-

SUM a

74S194
MODE
DS3
PAR LD
RT SHIFT
HI
RT SHIFT
LO
LT SHIFT
LT SHIFT
--

DSO
-

t
t
t
t
LO

HI
LO
-

CLK

Rn(1)
LO
On
HI
LO
AC1
AC1
NO
CHANGE

!
COUT l~ C4

1:4
ADDER
7483
B4

OUT
CONT
LO
LO
HI

DATA
ENA
LO

t
t
-

HI
-

DATA CM P l---<: SO
DATA ENA l---<: STB

so
LO
HI

ENl~DIS2.4

MD EN l - o DIS2.4
BUF
8097
El05

BUF
8097
El04

Fn
An
Bn
HI

,l
PC EN l - - ( OUT 10
CONT
DATA

--<: ENA

MAOl

PCO l

PC lD EN l

ADD IN 0

(

PC
8Tl0

PC C l K - ClK

BUS l

CONT
DATA
ENA

fb~~- ClK

~~R l ~ ~~1n 10
~ DATA

CPMA
8Tl a

AC-BUS l-<SI

-=-

TP2

ENA

ClK

HI
LO
HI

51
LO
LO
HI
HI

Fn
Bn
An
Bn
HI

50
LO
HI
LO
HI

8235
51
LO
LO
HI
HI

Fn
An Ern
An
Bn
HI

F2
MUX
8235
E87

MO-BUS l-<l SI
A2

I
T

INIT L - ( ClR
RR EN- SO

R3(1)

74~~94

Rl EN- SI

DSO I--ACI

LINK B I T - DS3
AC C l K - ClK

8234

.... SO

(ACO +AC61

MB
8Tl0

ANOENL

F2
MUX
8234
E86

MDOl

l
CPMA----,c: OUT 10

H>J

DATA 0 l

OUTPUT
INPUT
HI-Z
MA

74S158
STB
LO
LO
HI

Fa
MUX
74S158
E95

8097
DIS24
LO
HI

lOGIC

nO
olJT
nQ IN
NO CHANGE
HI-Z

CLK

P-- C IN l

8T10

§]

CARRY
A4 CO

LOGIC

CNT 4(1)

MO
74163

ClR P--- MO ClR EN l
lD

P-- MO lOAD EN l

ClK I - - MO ClK
DO

I
SUMO+SUM6

BSW l - o SO

F3
MUX

r STB7~~~;8
B3

I I

SUM 6

Figure 4-45

Block Diagram, Major Register and Gating (BITO)

08 -1311

Central to the major register gating is the DEC7483 full adder. When information is transferred from or to a major.
register, it passes through the adder, where it mayor may not be modified, and is placed on the SUM line. Each register, except the MQ, is loaded from the SUM line. The register that is to receive the data is determined by various
control signals; these are generated in response to the instruction identity, the CPU major state, the timing generator
time state, or to some combination of these factors.
For example, the program count in the PC register is transferred to the CPMA register at the end of one instruction
to indicate the memory location of the next instruction of the program. Hence, during TS4, the PC EN l signal gates
the PCO bit to the adder via the ADD IN 0 line. During the same time state, the DATA CMP l and DATA ENA l
signals disable the DEC7 4S 158 data selector (E95), causing a logic 0 to be applied to the other input of the adder
(pin A4). The result. PCO, is placed on the SUM 0 line and loaded into the CPMA register by the CMPA lOAD signal, which is generated by each TP4 pulse. Some circumstances require that a program instruction be skipped; this
can be done if the program count in the PC register is incremented by the adder before being placed on the SU M
line. The CPU Carry In logic generates the C IN l signal during TS4, causing the adder to increment the program
count. The result. PC+ 1 (the logic 1 is added directly to bit 11 of the PC)' is loaded into the CPMA register.
At times, information must be transferred between a major register and some source external to the CPU. A peripheral, for instance, can transfer data to the AC register during a programmed I/O dialogue. The peripheral places
the data on the DATA bus. During TS3 it is gated through the data selector to the adder and placed on the SUM
line. The byte-swap multiplexer (E115) gates the data to the AC register and the register is loaded by the PC, AC,
MQ, ClK signal at TP3 time. The data transfer can be made in the opposite direction, as well. In this case, the AC>BUS l signal places the AC contents on the DATA bus during TS3. The peripheral is responsible for clocking the
data from the DATA bus into a peripheral buffer register. The original data may be returned to the AC register and
reloaded at TP3 time; alternatively, the data selector can be disabled so that logic zeroes are placed on the SUM
lines and clocked into the AC.
The foregoing examples are presented merely to familiarize you with the block diagram in Figure 4-45. To become
familiar with the operation of the major registers and gating, one should become adept at following the gating of
PDP-8/A instructions through the logic represented in the block diagram.
Most of the major register enable signals and the various multiplexer control Signals were introduced in the 10 discussion, Paragraph 4.4. There, it was pointed out that a number of ROMs play an important part in decoding instructions and generating major register gating control signals. The logic for each ROM was illustrated and mention was
made of tables relating the RO M input and output signals. Two of these tables (4-11 and 4-12) appear in this paragraph. Other tables appear in the Skip logic, in the Major State Register logic, and in Paragraph 4.6, I/O Transfer
logic. Each table relates the input and output signals of a particular ROM and gives a brief resume of the result
achieved by each output condition. For example, Table 4-11 provides information about ROM 0, which generates
major register gating signals when operate microinstructions are programmed. The INPUT CODE column lists the
codes represented by the input signals in octal form. The INPUT SIGNAL lOW column indicates the signals that
must be low to achieve the desired input code '(this convention is chosen because most of the PDP-8/A Omnibus
signals are active when low). The ROM OUTPUT SIGNAL column shows the Signals that are generated for each input code (consider the inverter at output pin 2 as part of the ROM). while the INSTRUCTION OCTAL CODE column
indicates the group of operate instructions that relate to each input code. Finally, the RESULT column summarizes
the events that take place in the major register gating logic in response to the signals generated by the ROM.
Each of the 256-bit ROMs has a similar explanatory table asociated with it. At the top of each table is a notation as
to when the ROM is enabled. ROM 0 is enabled whe" pin 15, is low, i.e., during TS3 of an operate instruction.
Some of the ROM tables include a column headed DCOR OUTPUT SIGNAl. These ROMs generate three Signals SEl A l, SEl B l. and SEl C l - that are applied to a i BCD-to-decimal decoder, E71. The decoder then asserts the
signal indicated in the DCDR OUTPUT SIGNAL column.

4-56

To use the ROM tables with the block diagram in Figure 4-45 first consider what variables are represented by examining the instruction. Then find the ROM that is enabled for the set of variables exhibited. For instance, operate instructions are executed, for the most part. during TS3. ROM 0 is enabled during TS3, so refer to Table 4-11. For a
specific example, think about the CMA (7040) instruction - complement the AC. Table 4-11 shows four entires in
the INPUT CODE column that apply to the octal code 70XX. Two of them, 34 and 36, generate the CARRY EN L
signal. which is not needed to complement the AC: consequently, those entries can be ignored. Both of the remaining entires generate AC->BUS Land AC LD EN L. However, entry 35 generates DATA CM P L as well as DATA
ENA L a combination that results in the complement of the information on the DATA lines being gated to the SUM
lines. Thus, the events take place as follows: AC->BUS L gates the content of ACO to the DATA 0 line (Figure 445): multiplexer E95 gates the complement of the ACO bit to the adder, which places the information on the SUM 0
line: multiplexer E 115 passes the information on the SU MOline to the ACO-bit input. from where it is loaded at
TP3 time.
As another example, consider the basic AND instruction that directs a logical ANDing of the AC contents and the
contents of the addressed memory location. This is an interesting example, since the major register gating operates
intricately while executing the AND instruction. First of all, locate the ROM table that applies to basic instructions Table 4-12. The entry for input codes 34 and 35 apply in this example. Input code 34 produces the MD EN L signal
that gates the operand of the AND instruction through buffer E 105 and the adder to the M B register during TS2. At
TP2 time, the MB register is loaded and becomes the source of data for the MD lines (this ensures that the operand
is re-written during the write operation). During TS3, input code 35 produces the AND EN L signal. As can be seen
from the function tables in Figure 4-45, AND EN L causes multiplexer E86 to gate the complement of the data on
the M DO line to the DATAO line: at the same time, multiplexer E87 places the content of the ACO bit on the
DATAO line. If both MOO L and the ACO bit are logic 1 (MOO L is low and ACO is high). DATAO L is high, which is
not logic 1 but which is quickly converted to logic 1 by multiplexer E95. Thus, the SU MOline goes low, multiplexer
E115 places a high at the input of the ACO bit. and a logic 1 is loaded into the AC at TP3 time. If either MOO L or
ACO is logic 0, a logic 0 is loaded into ACO at TP3 time.
Most of the gating control signals are generated by the various ROMS. Those few that are not are produced by either the supplementary logic discussed in Paragraphs 4.4.3 through 4.4.6, or by the Carry In logic, the Skip logic,
and the Link logic. The last three groups of logic are discussed in detail in Paragraphs 4.5.2 through 4.5.4. Section
4.5.1 discusses Page logic, which modifies the block diagram of Figure 4-45 in certain circumstances.
4.5.1
Page Logic
The operand of a memory reference instruction (MRI) or the effective address of an indirectly-addressed JM P instruction can be stored in the current page or in page O. The logic shown in Figure 4-46, which is only partially illustrated in the block diagram of major register gating, satisfies either eventuality.
At TP4 of the Fetch cycle, the address of the M RI operand, for example, must be loaded into the CPMA register. If
the operand is on the same page as the MRI. only the relative address bits (5 through 11) of the CPMA register
need be changed: hence, MA bits 0-4 are loaded into CPMAO-4, respectively, to specify the current page, while M 0
bits 5-11 are loaded into CPMA5-11, respectively. to specify the relative address. However, if the operand is located
on page 0, both the relative address bits and the page bits must be changed: thus, zeroes are loaded into CPMAO-4,
while M 0 bits 5-11 are, again, loaded into CPMA5-11.
The MD4-bit is used to indicate current page or page O. When MD4 L is asserted, the M RI operand or the JM P I
effective address is on the current page. The PAG E EN L signal is asserted by ROM B for an M RI (Table 4-13) or by
ROM C for the JM P I instruction (Table 4-12). As Figure 4-46 shows, MA bits 0-4 are placed on ADD IN lines 5-11
(MD bit 5 is gated by an 8093 tri-state quad buffer). When the MD4-bit indicates page 0, zeroes are placed on the
ADD IN 0-4 lines, while the MD lines are again gated to ADD IN lines 5-11.
Note (Table 4-12) that the PC, rather than the CPMA, is loaded for the J M P I instruction. Also, this operation takes
place during TS3 rather than during TS4.

4-57

Table 4-11
ROM 0 I nput/Output Signals
(ROM Enabled for OPR"TSE)
Input
Code

M03L

M04L

0
1
2
3

X
X
X
X

4
6
7

X
X
X
X

10
11
12
13

X
X
X
X

14
15
16
17

X
X
X
X

ROM Output Signal
M07 L

M011 L

X
X

X
X
X
X

24
25
26
27

X
X
X
X

34
35
36
37

X
X
X
X

20
21
22
23

30
31
32
33

Inout Signal Low
M06L
M05L

X
X
X
X

X
X

X
X
X
X

X
X

Instruction
Octal Code

Result

DATA ENA L, AC LD EN L, MO -> BUS L, MO CLR EN L
DATA ENA L, AC LD EN L
DATA ENA L, AC LD EN L, MO -+ BUS L
DATA ENA L, AC LD EN L

nxx

MO -+ AC, Clear MO
DATA -> AC
MO-+ AC
DATA-+ AC

DATA CMP L, AC LD EN L, MO ClR EN L
DATA ENA L, AC LD EN L
DATA CMP L, AC LD EN L
DATA ENA L, AC LD EN L

76XX

Clear AC, Clear MQ
DATA -> AC
Clear AC
DATA -+ AC

DATA ENA L, AC LD EN L, MO"'" BUS L, MO LD EN L
DATA ENA L, AC ..... BUS L, AC LD EN L
DATA ENA L, AC -+ BUS L, AC LD EN L, MO ...... BUS L
DATA ENA L, AC -+ BUS L, AC LD EN L

75XX

Swap AC and MO
AC-+AC
Inclusive OR, AC and MO
AC -+ AC

DATA CMP L, AC LD EN L, MO LD EN L
DATA ENA L, AC ...... BUS L, AC LD EN L
DATA ENA L, AC -+ BUS L, AC LD EN L
DATA ENA L, AC ...... BUS L, AC LD EN L

74XX

AC .... MO, 0 -+ AC
AC -+ AC
AC-AC
AC -+ AC

DATA ENA L, DATA CMP L, AC LD EN L, CARRY EN L
DATA ENA L, DATA CMP L, AC LD EN L
DATA ENA L, AC LD EN L, CARRY EN L
DATA ENA L, AC LD EI\! L

73XX

DATA+l-+ AC
DATA-+ AC
DATA+' ...... AC
DATA-+ AC

DATA ENA L, DATA CMP L, AC LD EN L, CARRY EN L
DATA ENA L, DATA CMP L, AC LD EN L
DATA ENA L, AC LD EN L, CARRY EN L
DATA ENA L, AC LD EN L

72XX

DATA+1 -+ AC
DATA -+ AC
DATA+' ...... AC
DATA-+ AC

DATA ENA L, DATA CMP L, AC -+ BUS L, AC LD EN L, CARRY EN L
DATA ENA L, DATA CMP L, AC -+ BUS L, AC LD EN L
DATA ENA L, AC"'" BUS L, AC LD EN L, CARRY EN L
DATA ENA L, AC -+ BUS L, AC LD EN L

71XX

Complement and increment the AC
Complement the AC
Increment the AC
AC-+ AC

DATA ENA L, DATA CMP L, AC-+ BUS L, AC LD EN L, CARRY EN L
DATA ENA L, DATA CMP L, AC -+ BUS L, AC LD EN L
DATA ENA L, AC -+ BUS L, AC LD EN L, CARRY EN L
DATA ENA L, AC"'" BUS L, AC LD EN L

70XX

Complement and increment the AC
Complement the AC
Increment the AC
AC-+ AC

ADD
IN3

ADD
IN1
ADD
INO

ADD
IN2

ADO
IN6
ADD
IN5

ADO
IN4

ADO

INS

IN10

ADO

IN9

IN11

MD7 L

MD9 L

MD11 L

IN7

ADD

MD4 L
PAGE EN L

MA EN L

DIS 2 4

8097
ADD IN 0-4

ADD IN 6-11

MAOL -MA4 L

MD6 L -MOll L

HI-Z

MD EN L

08-1312

Figure 4-46

Page Logic

4.5.2 Carry In Logic
The Carry In logic is shown in Figure 4-47. The C IN L signal enables the processor to increment data_ This signal is
applied to the carry input of adder bit 11. There. it is added to two other inputs - the addend and the augend: any
carry from the addition is applied to adder bit 10. and so on, until a carry from adder bit 0 (C OUT L) is applied to
the link logic.
Data must be incremented for a variety of operations. This variety involves all the CPU Time States as well as the
CPU Major States. The digital multiplexer. DEC74151. has the versatility to cope with the many enabling signals
that are encountered. The 74151 data select inputs at SO. S 1. and S2 determine which of the 8 input lines is
routed to the output. The table in Figure 4-47 shows the inputs and outputs and lists the involved time states as
well.
Consider the major event that occurs during TS1 of a Fetch or DMA timing cycle. Le .. the address on the MA lines
is incremented and loaded into the PC register at TP1 time_ Because the address must be incremented. the Carry In
logic must assert the C IN L signal during TS 1. The 74151 table shows that during TS 1. the input at either DO or
D4 is gated to the output and causes the C IN L signal to go low. Thus. the address can be incremented during the
Fetch state as well as during a DMA cycle. when either the E NEXT or the D NEXT button on the Programmer's Console might be pushed.
The Defer and Execute states do not require an incrementing process during TS 1: however. since the adders are not
used at this time, it is unnecessary to prevent C IN L from being asserted_ Note that CARRY EN L is asserted during
TS1. provided the LA ENABLE L line has not been grounded by the Programmer's Console. When either the LA or
LXA pushbutton is activated. the address to be loaded is placed on the DATA lines and gated through the adders to
the CPMA register. Hence. the console also grounds the LA ENABLE L line so that C IN L does not increment the
selected address.

4-59

Table 4-12
ROM C Input/Output Signals

Input

Input Signal Low
IR1 L
IR2 L
FL+EL

Code

IRO L

12
13

X
X

14
15
16
17

X
X
X
X

X
X

DATA CMP L, PC LD EN L, SEL A L

DATA CMP L, CARRY EN L, SEL C L, SEL B L
DATA CMP L, PC LD EN L, SEL C L, SEL B L

DATA CMP L, CARRY EN L, SEL C L
DATA CMP L, PC LD EN L, CARRY EN L, SEL B L
DATA CMP L, CARRY EN L, SEL C L, SEL B L
DATA CMP L

20
21
22
23

X
X
X
X

24
25
26
27

X
X
X
X

34
35
36
37

X
X

X
X
X
X

30
31
32
33

Note:

ROM Output Signal

X
X

Tl Low = TS1 + TS2
T1 High = TS3 + TS4

4-60

DATA ENA L
DATA CMP L, AC LD EN L
DATA CMP L, CARRY EN L, SEL C L, SEL B L
DATA CMP L

DATA CMP L, CARRY EN L, SEL C L, SEL B L
DATA CMP L, SEL B L, SEL A L
DATA CMP L, CARRY EN L, SEL C L, SEL B L
DATA CMP L
DATA CMP L, SEL C L, SEL B L
DATA ENA L, AC LD EN L, SEL C L, SEL B L
DATA CMP L, CARRY EN L, SEL C L, SEL B L
DATA CMP L
DATA CMP L, SEL C L, SEL B L
DATA CMP L, DATA ENA L, AC LD EN L, SEL A L, SEL C L
DATA CMP L, CARRY EN L, SEL C L, SEL B L
DATACMP L

Basic
Instruction

DCDR
Output
PAGE EN L

JMP

JMS

MD EN L
MD EN L
PC EN L
MA EN L
MD EN L

DCA
MD EN L

i
I

Result

I
I

If MD4 L is logic 1 (operand is on current page). MAO-4 is loaded into PCO-4, MD5-11 is loaded into PC5-11. If MD4 L is logic 0 (operand i~
loaded into PCO-4, MD5-11 is loaded into PC5-11.
MD + 1 ~ MB; (contents of indirectly-addressed auto-index register are incremented and used as effective address)
MD -+ PC (PC is loaded with the address to which program control will be transferred)
PC -+ MB; PC + 1 -+ MB if Skip flip-flop is active (program count to which control will return after forced-JMS is completed, is stored in locatio
MA + 1 ~ PC (program control is transferred to the location of the first subroutine instruction)
MD + 1 -+ MB (contents of indirectly-addressed auto-index register are incremented and used as effective address)
No operation
AC ~ MB (AC register placed on data bus by AC register control logic, data bus gated to MB register)
0-+ AC
MD + 1 -+ MB (contents of indirectly-addressed auto-index register are incremented and used as effective address)
No operation

ISZ

MD EN L
ISZ SKP TST L
MD EN L

MD + 1 ~ MB (data in specified location is incremented to test for 77778 count)
1 -+ skip (if incremented data was 7777 8 , C OUT L is asserted, Overflow flip-flop is cleared at TP2, and Skip flip-flop goes active at TP3)
MD + 1 -+ MB (contents of indirectly-addressed auto-index register are incremented and used as effective address)
No operation

TAD

MD EN L
MD EN L
MD EN L

MD -+ MB
MD -+ ADDER, AC -+ ADDER (AC~ BUS L generated by AC register control logic); binary addition result to AC
MD + 1 -+ MB (contents of indirectly-addressed auto-index register are incremented and used as effective address)
No operation

AND

MD EN L
AND EN L
MD EN L

MD -+ MB
MD -+ DATA BUS, AC-+ DATA BUS; Logical-AND result to AC
MD + 1 -+ MB (contents of indirectly-addressed auto-index register are incremented and used as effective address)
No operation

Table 4-13
ROM B Input/Output Signals
(ROM Enabled During TS4)
Input Signal Low
IF SET L
MSO

Input
Code

GND

INT

Note:

ROM Output Signal

DCDR Output Signal

CARRY EN L, SEL C L

PC EN L

PC -+ CPMA; PC + 1 -+ CPMA if Skip flipflop is active

CARRY EN L, SEL C L

PCEN L

PC -+ CPMA (indirectly-addressed JMP inst).

CARRY EN L, SEL C L

PC EN L

PC -+ CPMA; PC + 1 -+ CPMA if Skip fl ipflop is active

SELA L

PAGE EN L

SEL C L, SEL B L

MD EN L

MD -+ CPMA (address of the operand of an
indirectly-addressed MRI instruction)

MS1
X

MSO Low = FL + DL
MS1 Low = F L + E L

*If MD4 L is logic 1 (operand is on current page), MAO-4 is loaded into CPMAO-4, MD5-11 is loaded into CPMA5-11.
If MD4L is logic 0 (operand is on page 0), logic 0 is loaded into CPMAO-4, MD5-11 is loaded into CPMA 5-11.

Result

74151
(TIME
S2

L
H

H
H

STATE)
(TS1)

STB
L

FO
DO

(TS4)

L
H
L
H

(TS2)

(TS3)

(TS1)

(TS4)

(TS2)

(TS3)

L
L
L

53
54
55
56
57

T0
CARRY EN L
LA ENABLE L
CPMA DISABLE L
ROM ADDRESS L

IRRJ L - - - - ,
SKIP FF -"---1
DATA ENA

STB

02
01

SUM 0
I

+3V

1
I

I
I
I

D----CllQ

SUM 7

QUAD FF
eTl0

E62

00
MUX

07 74151 Fid
06 E59

C IN L

A1,F,
SUM

D,E

OUT CO NT
EL

TRJ T1

NOTE:
T1 ANDTO LOW TOGETHER
DURING TSl

08 -1313

Figure 4-47

Carry In Logic

During TS2, no Fetch operations require data to be incremented. In the Defer state, however, an auto-index register
(memory locations 0010 through 0017) might have been referenced by the instruction being performed (refer to
Introduction to Programming, 1972, for a discussion of auto-indexing). In this case, the content of the register is incremented before being used as the instruction operand; thus, the information on the MD lines (the auto-index register contents) must be incremented during T52 before being loaded into the M 8 register at TP2 time. The 74151
table shows that during TS2 of all but the EXI~cute state, a high input at D6 causes the C IN L signal to go low. The
signal at D6, AI. is high when the data on SUM lines 0 through 8 indicates that an auto-index register has been referenced. The CARRY EN L signal is asserted by ROM C during this operation; refer to Table 4-12 for verification.
In the Execute state. two situations require that the C IN L signal be asserted during TS2. First. an ISZ instruction
can direct the CPU to increment the data in the specified location and then skip the next instruction if the result of
the incrementation is 0000. Second, the CPU interrupt system might have honored an interrupt request during an instruction wherein the SKIP FF signal had been asserted; consequently, rather than storing the program count in
memory location 0000, the CPU must store the incremented program count during TS2 of the forced JMS
instruction.
In both these situations, a high input at D2 of the multiplexer causes the C IN L signal to be asserted (CARRY EN L
is asserted by ROM C). For the ISZ instruction, the I RO L signal is high and, therefore, D2 is high. For the forced

JMS instruction IRO L is low and, because the SKIP FF signal is high, pin 2 is high.
TS3 operations in the Fetch state that require the C IN L signal to be asserted, involve the lAC operate microinstruction. If lAC has been programmed, the contents of the AC register are placed on the DATA lines during TS3
and gated to the adder. A 0 is gated to the ADD IN line of the adder, while the input at pin 12 of the multiplexer
causes the C IN L signal to go low (the CARRY EN l signal is asserted by ROM D). The result. AC+ 1, is placed on
the SUM lines and loaded into the AC at TP3 time. Similar operations take place when the lAC command is microprogrammed with other Group 1 microinstructions.

4-62

A JMS instruction requires that the address on the MA lines be incremented during TS3 of the Execute state. When
a JMS instruction is programmed. the operand of the instruction specifies the first memory location of the subroutine. In this location (Y. for example) must be stored the program count. to which the program will return upon
completion of the subroutine. The first instruction of the subroutine is contained in location Y+ 1 and. in order to
transfer control to location Y+,. the address on the MA lines (location Y) must be incremented during TS3. A high
input at 03 of the multiplexer asserts the C IN L signal (ROM C asserts the CARRY EN L signal). 03 is high providing both CPMA DISABLE L and ROM ADDRESS L are negated.
During TS4 of both the Fetch and the Execute cycles. the program count in the PC register is transferred to the CPMA
register. However. certain situations require a skip of one program instruction; hence. the program count in the PC
register must be incremented before being transferred to the CPMA. One of these situations arises when a Group 2
operate microinstruction. such as SKP. is programmed; another results from an lOT instruction causing a peripheral to
assert the Omnibus SKIP L signal; finally. an ISZ instruction might have been programmed. In each situation the SKIP
flip-flop is set at TP3 time. asserting the SKI P FF signal. This signal at 01 or 05 causes the 7415' multiplexer to assert
the C IN L signal during TS4 of both the Fetch and Execute cycles (the CARRY EN L signal is asserted by ROM B).

4.6.3 Skip Logic
The Skip logic. shown in Figure 4-48. samples the contents of the AC register andlor the Link. and the state of the
Omnibus SKIP line. If the sampled data meets specified conditions. the program count is incremented before being
transferred to the CPMA register at TP4 time; consequently. the next program instruction is skipped (Table 4-13).
The Skip operation is used primarily during the implementation of operate microinstructions. The majority of the
Group 2 operate microinstructions. and nearly half of the combined microinstructions involve the Skip operation.
ROM F decodes the Skip microinstructions and asserts the ISKIP L signal during TS3. The Skip flip-flop is cleared at
TP3 time. and the SKIP FF signal causes the Carry In logic to increment the program count. Two examples are offered to demonstrate how the logic responds to skip instructions.
Consider the Group 2 operate microinstruction SMA (7500) - skip on a minus AC. Remember that minus numbers
in the PDP-8/A are those between 4000(8) and 7777(8). i.e .. bit 0 is logic 1. Thus. during TS3 of the SMA instruction. ROM F will assert the ISKI P L signal if ACO is logic 1 (a high voltage level). When SMA is placed on the M 0
lines and the I R register decodes MD bits O. 1. and 2. the inputs to ROM F are as follows.

ROM F Input Pin

Voltage Level
Input Octal Code

ACO

LO
5

HI/LO

6/7

(If ACO is logic 1)
The ROM F pattern specification in Appendix J shows that ,the binary data contained in octal location 156(8) is
'1000. Thus. the ROM outputs are as follows.

ROM F Output Pin

Voltage Level
Output Signal Asserted

HI
ISKIP L

Location 157(8) causes both the ADLK L and the ISKIP L signals to be asserted. If the AC is positive. i.e .. ACO is
logic O. the ISKIP L signal remains high for any of the four possible inputs - 056(8). 057(8). 016(8). and 017(8) (inputs 016(8) and 017(8) result if input pi'; 2 is low. in which case the AC is zero).
The SZA (7440) microinstruction - skip on a zero AC - tests the AC for a zero condition. During TS2 the AC->BUS
L signal is asserted (Figure 4-44) and the contents of the AC register are placed on the SUM lines. If all AC bits are
zero (low voltage levels). the ZERO L signal is asserted and clocked into the flip-flop at TP2 time. The ROM input
code is 026(8) or 027(8). and ISKIP L is asserted by itself or together with ADLK L.

4-63

OP2 L

TP3H

SKIP FF

DMA L
FL

QUAD FF
8TIO

MD5 L

IR.Z

MD6 L

FLAG

MD7 L
MD8 L

LINK BIT

TS3 L

SUM11

TP2 H

OVERFLOW
SKI P L

TS3 L

08-1314

Figure 4-48

Skip Logic

The ISKIP L signal can be asserted two other ways: a peripheral can ground the Omnibus SKIP L line during an lOT
instruction. causing ISKIP L to be asserted during TS3: or. an ISZ instruction can cause the OVF (OVERFLOW) flip-flop to
be cleared. while also generating the ISZ SKP TEST L signal. thereby asserting ISKIP L.
An ISZ instruction directs the CPU to increment the data in the specified location and skip the next instruction if the
result of the incrementalism is 0000(8) (the operand of the instruction must be 7777(8) for such a result to occur).
The data is incremented during TS2 (Table 4-12; if the resLlt is 0000(8). the C OUT L signal is asserted by adder 0
and the OVF flip-flop is cleared at TP2 time. During TS3. ISZ SKP TEST L is generated by ROM C and the ISKIP L
signal is asserted. The Skip flip-flop is cleared at TP3 time and the following program instruction is skipped. Also during TS3, the OVERFLOW L signal is asserted. This signal is commonly used with a 3-cycle data break device: in
such an application. OVERFLOW L is used by the device control to indicate the last transfer of the data break operation (Paragraph 4.6.4).
Note that the Skip flip-flop is clocked at TP3 time of all but a DMA cycle. This restriction i necessary because of
the possibility of a data break device assuming control of the CPU immediately after a progra interrupt request has
been honored. Consider the following sequence of events: The Skip flip-flop is cleared at TP time of an SMA operate instruction, asserting the SKIP FF signal; an interrupt request is honored at the same ti e (the INT IN PROG H
signal is asserted at INT STROBE L time); a data break device takes control of the CPU by a serting the CPMA DISABLE L signal at the same TP3 time and the MS, IR DISABLE L signal at the following T 4 time. The first event
would normally cause the program count to be incremented and transferred to the CPMA register at TP4 of the
SMA instruction. However, when the INT IN PROG H signal is asserted, ROM B (Table 4-13) is prevented from generating the necessary gating signals. If the third event did not occur, INT IN PROG H would force the CPU into the
Execute cycle of the JMS instruction, during which cycle the incremented program count would be stored in location
0000(8) for retrieval at the conclusion of the program interrupt (Table 4-12). But. event three does occur and, thus,
control of the CPU is assumed by the data break device before the instruction register is forced to the JMS instruction. When the data break device relinquishes control of the CPU, the Execute cycle of the JMS instruction will be
entered and the PC+ 1 will be stored in location 0000(8). provided the Skip flip-flop is still clear and SKI P FF is
high. This provision is accomplished by prohibiting any TP3 that occurs during the data break operation from setting
the Skip flip-flop.
4.6.4 Link Logic
The Link is used with a TAD instruction and with Group 1 operate microinstructions that manipulate both the Link
and the AC register. A TAD instruction causes the contents of a specified memory location to be added to the contents of the AC register. The result of the addition can include a carry from adder O. Since such a carry is significant,
it is registered in the Link shift register. The shift register can then be manipulated so that the information can be
used in other AC operations. The Group 1 microinstructions can be used to clear and comple-ment the Link independently of the AC register, or to rotate the Link right or left along with the contents of the AC.
The Link logic is shown in Figure 4-49. The state of the link can be represented by the LINK BIT signal. which is
monitored by ROM F (Figure 4-48 shows all the input signals that are monitored by the ROM). When the Link is to
be complemented, because either a TAD instruction or a CML instruction is issued, ROM F controls the DEC74151
multiplexer with the ADLK L signal. The multiplexer provides Link inputs that are the complement of the Link's previous state. For example, assume that the Link contains a logic one. Thus, the LINK BIT signal is high. If the CML
instruction is issued, ROM F decodes its input signals and negates the ADLK L signal. The fO output of E48 goes
low; this level is parallel loaded into the Link shift register at TP3 time, complementing the previous state of the Link
(during TS3 of an operate instruction, ROM D in Table 4-11 asserts the AC LD EN L signal; the DEC 74S158 data
selector causes LNK RR EN and LNK RL EN to go high, placing the Link shift register in the parallel load mode).
When a TAD instruction is issued, the C OUT L signal mayor may not be asserted. If not, the to output of E48 assumes the same level as the previous state of the Link; i.e., if the Link was high before the TAD instruction, ADLK L
goes low when ROM F decodes its input signals, and the to output goes high. Hence, the Link retains its previous
state (during TS3 of the Execute cycle of a TAD instruction. ROM C asserts the AC LD EN L signal; thus, the Link
shift register is kept in the parallel load mode). However, if the TAD instruction had resulted in a carry out. both
ADLK Land C OUT L are asserted and the fO output goes low. complementing the Link.

4-65

AC Lo EN L
TS3 L

LNK RR EN

lOT
XFER L

M08 L

M09L

MUX
AO
74S158
B2 E68

S2
LO
HI
HI
HI
HI

LNK RL EN

S1
LO
HI
HI
LO

74151
SO

FO
LINK DATA L

LO
HI
LO
HI

LO
LO
HI
HI

A2
STB

OPI L
TS4 L

ACII
7

OS3

DO
LINK
DATA L
AC 0
~

fO
+3V

02
03 74151
E48
04

RTF H

R3(1l

R2(1l

RHI)

RO(I)

LINK L

LINK BIT

74S194
LINK

05
06
+3V

INIT L

ACO

C OUT L

LINK
LOAD L

LINK BIT
RTF H
TP3 H

TP3 H

(TPI L + TP4 Ll
(TP3}'2' [OP 1 L' MOIO L]l

CLR
LO
HI
HI
HI
HI
HI
HI
HI

SO
HI
HI
HI
LO
LO
LO

S1
HI
LO
LO
HI
HI
LO

DS3

748194
DSO

CLK

HI
LO
HI
LO
LO

R3(1)

RO(1)

LO
D3
HI
LO
R2(1)
R2(1)

LO
DO
R1(l)
R1(l)
HI

LO
NO CHANGE
NO CHANGE

08-1315

Figure 4-49

Link Logic

When the Link is to be cleared (Cll). ROM F negates the ADlK l signal no matter what the previous Link state.
The to output of E48 is low. and the Link is cleared at TP3 time of the instruction.
Two of the processor lOT instructions are involved with the Link bit (Paragraph 4.6.2. The GTF instruction can be
used to transfer the state of the Link to the 0 bit of the AC register. The RTF instruction enables the programmer to
return a previous Link state from the AC register to the Link register. When the RTF instruction is issued the LI N K
DATA l signal causes the to output of E48 to assume the state of the ACO bit. Then this state is loaded into the
Link register at TP3 time by the LI N K lOAD l signal (during T53 of an lOT instruction. the IN K R R EN and IN K Rl
EN signals are high. keeping the Link shift register in the parallel load mode).
During T53 of an operate instruction. ROM D asserts the AC lD EN l signal; the Link shift register is placed in the
parallel load mode by lNK RR EN and lNK Rl EN. If the instruction is a rotate instruction (RAR. RAl. RTR. RTl).
the state of the Link during T53 is loaded into the Link shift register at TP3 time; i.e .. the Link is not changed when
the shift register is clocked at TP3 time. During T54. either lNK RR EN or lNK Rl EN goes low. depending on the
direction of shift (i.e .. if the instruction directs a rotation to the right. lNK Rl EN goes low. while lNK RR EN goes
low for a rotation to the left); the Link shift register is placed in the right shift or left shift mode. If the instruction is
RTR or RTl. the link shift register is clocked at TP3 112 time. halfway through T54. At this time. the content of AC
bit 11 is loaded into R3( 1) of the Link (assume the instruction is RTR); at the same time. AC bit 10 is shifted into
AC 11. At TP4 time. the Link is clocked again and the content of AC bit 11 (originally in AC bit 10) is loaded into
R3(1) of the Link. Both R2( 1) and R1 (1) were loaded with logic 1 (positive voltage in the Link) at TP3 time; hence.
both RO( 1) and R3( 1) are high after the two clocking operations and the LI N K BIT signal exhibits the correct state.
The original content of the Link shift register has been rotated two places to the right. The single-rotate instructions
are effected similarly. but the Link shift register is clocked only at TP4 time. resulting in a shift of but one position.

4.6

I/O TRANSFER LOGIC

4.6.1
Programmed I/O Transfer Logic
Programmed liD transfers use lOT instructions to initiate data exchanges between a user device and either the AC
register or the PC register. Information is transferred to and from a device on the Omnibus DATA bus. Figure 4-50
illustrates the major register gating for a programmed liD transfer. while Figure 4-51 shows both the logic that generates
the gating control signals and a diagram that relates essential timing signals.
When an lOT instruction involving a data transfer is issued. the user device asserts the Omnibus C lines to generate
the necessary major register gating control signals. For example. if an lOT instruction directs a particular device to
transfer data to the PC register. the device asserts the C1 l signal and the C2 l signal and places the data on the
DATA bus. ROM E produces DATA ENA l and PC lD EN l. thereby gating the data to the PC register during T53.
At TP3 time. essentially. the PC. AC. MO ClK signal loads the data into the PC register.
Table 4-14 relates the input and output signals {or ROM E and outlines the results achieved by the possible combinations of the C line signals. Note that six possible types of data transfers exist. which are represented by input
codes 20(8) through 27(8). Input code 37 results when a GTF instruction is issued and the GTF H signal is asserted
by the Processor lOT logic (Paragraph 4.6.2). The timing diagram in Figure 4-51 shows how the PC. AC. MO ClK
signal is generated during a normal I/O transfer cycle. i.e .. when the lOT instruction does not require an extended
timing cycle. (Paragraph 4.2.5 has a detailed discussion of liD timing for both non-extended and extended timing
cycles.)

4.6.2 Processor lOT Logic
A number of internal lOT instructions are designated processor lOT instructions. They are represented as 600X(8)
and are concerned. in general. with program interrupts. The appropriate logic is shown in Figure 4-52.

4-67

SUM J;,

~~-~-+--~T-i-OO
HI

ADD IN 13

PC ,AC,
MQ ClK

08 -1316

Figure 4-EiO Major Register Gating (BITOO).
Programmed liD Transfer

When a processor lOT instruction is programmed, the INTERNAL liD L signal is asserted so that peripherals interfaced to the Omnibus via the KA8-E option (Positive liD Bus interface) will ignore the lOT instruction. The seven processor lOT signals are generated by ROM J. Table 4-15 lists the inputs and outputs for the ROM in detail. Note that
only inputs 20(8) through 27(8) are used for the processor lOTs. Inputs 10(8) through 17(8) are used when STATUS
information is to be placed on the DATA lines during TS 1.

Either a peripheral or the Programmer's Console can cause STATUS information to be placed on the DATA lines by
negating the IND1 Land IND2 L signals. When this is done the STATUS L signal is asserted by the DEC74S139
decoder during TS1, and ROM J generates the GTF H signal. The status of the INT ENA flip-flop is gated to the
DATA 4 line, the status of the INT ROST line is gated to the DATA 2 line, and the status of the Link Bit is gated to
the DATA 0 line. If the operator has used the Programmer's Console to negate the IND signals, the STATUS information is gated to the console and displayed during TS 1 (the programmer will have halted the CPU before attempting
to display the STATUS information).
The GTf H signal is also asserted when the GTF instruction is programmed. In this case, the 110 L signal is generated and the significant operation takes place during TS3 (when the STATUS L signal can be only high). Again, the
DATA 4, DATA 2, and DATA 0 lines reflect the status of the INT ENA flip-flop, the INT ROST L signal. and the Link
Bit respectively. This information, and that carried on the remaining DATA lines, is gated to the AC register and
loaded at TP3 time (Table 4-14, especially the entry for Input Code 37(8)).
The RTF instruction causes ROM J to assert RTF H and I NT ON H. RTF H restores a previous state of the Link,
while INT ON H turns on the interrupt system. Both the GTF and RTF instructions have minor significance within the
processor itself; their full potential is realized only when a KM8-AA Memory Extension option is included in the
system.

4-68

I/O PAUSE H

14
P " - - - SEL C L

GTF H
C2 L

C1 L
C0 L

13
12

ROM E
E76
I/O

P - = - - - AC

BUS L

I C ) - ' - - - AC LD EN L

10 '

DATA CMP L
D - ' - - - DATA ENA L

'-------'

1/0 PAUSE L

TS3 L
MD0 L - - - . Q

MOl L - - - C 1

BUS STROBE L
PC,AC,MQ CLK

~~~~E
E19
74120

MD2L-------...I

T0---nI

USER MODE L
F H

U.-------------------------.
~-------

I
I/O PAUSE H

~
I
I

TPI H

n
I

~------------------------~I------I

TP3 H

~I------------------------~J:l~-------

nL--________....Jn,_________--....Jfil
I

TPC

~------

TS3 L

NOT LAST XFER L
S BUS STB

BUS STROBE L

Ll.J
I
I

m~----

PC,AC,MQ CLK

Figure 4-51

Programmed 1/0 Transfer Logic

The CAF instruction causes the ROM to generate CAF H; thus. the CAF flip-flop is set at TP3 time. Transistor Q1 is
turned on. asserting the Omnibus INITIALIZE H signal as well as the CPU INIT L signal. The CAF flip-flop is cleared when
the TS1 L signal goes low. negating the initializing signals at the start of the next program instruction; the flip-flop is
cleared even if the operator has been single-stepping the CPU and ends with the CAF instruction (the timing generator
asserts the TS 1 L signal before halting). When power is turned on. ON L is held low for 100 ms after POWER 0 K H goes
high. The initializing signals are generated for this length of time to enable all system equipment to complete the
necessary initializing operations. When ON L goes high. TS 1 L clears the CAF flip-flop and the initializing signals are
negated.
The SKON H. SRQ H. INT ON' H. and INT OFF L signals are program interrupt-generated Signals. They are discussed
in detail in Paragraph 4.6.3.

4-69

Table 4-14
ROM E input/Output Signals
(ROM Enabled During TS3)
Input
Code

I/O PAUSE H

Input Signal Low
GTF
C2 L

ROM Output Signal
C1 L

CO L

DATA CMP L

6
7

DATACMP L

DATA CMP L
X

DATA CMP L
DATA CMP L

X
X

Result

DCDR
Output

DATA ENA L, PC LD EN L

Input data to PC register

DATA ENA L, PC LD EN L
X

Input data to PC register

DATA ENA L, PC LD EN L, SEL C L

PC EN L

Input data added to PC contents, result loaded into
PC

DATA ENA L, PC LD EN L, SEL C L

PC EN L

Input data added to PC contents, result loaded into
PC

DATA ENA L, AC LD EN L

Input data to AC register

DATA ENA L, AC LD EN L, AC-+ BUS L

AC to the data lines (output transfer), AC contents
returned to AC; input data can be OR'ed with AC

DATA CMP L, AC LD EN L, AC-+ BUS L

AC to the data lines (output transferl, zero to the
AC

DATA ENA L, AC LD EN L, AC-+ BUS L

AC to the data lines (output transfer), AC contents
returned to AC; input data can be OR'ed with AC

DATA ENA L, AC LD EN L

Link bit to ACO

I/O PAUSE H -_._--;

I/OL

MD3 L - - - - t
MD4 L - - - - r -......
MD5 L - - - - 4

I NTERNAL I/O L

k)----1~--a

MD6L-----i

TSI L

MD7 L - - - - I

+5V

MD8 L - - - - - i

TP3 H

STATUS L
IND1 L

IND2L

FB3

MD9 L

B2 ENB2

MD10 L

MDII L
TS1L

CAF H

2-4
DCDR
74S139
E58

2
ROM

RTF H
GTF H

TP3 H

LINK
LOAD L

ON L
INIT L

SKON H

SRQ H

I NT ON H

ACO

LINK
DATA L

INT OFF L
INT ENA

DATA 4 L

DATA 2 L

I F SET L
INT RQST L

H
H

DATA 0 L
LINK BIT

74S139
B2

FB3
H
H
H
H

ENB2 A2
H
-

ROMJ
INPUT
CODE
OUTPUT
GHH
10-17
(INDICATE)
CAF H
20
21
NOP
22
RTF H
INTDN H
GTF H
23
SRQH
24
INTOFF L
25
INTON L
26
27
SKON H
INT OFF L
08-1318

Figure 4-52

Processor lOT Logic

Table 4-15
ROM J Input/Output Signals
(ROM Enabled Permanently)
Input
Code

10
11
12
13
14
15
16
17

Input Signal Low
i/O L
M09L
M010 L

STATUS L

X
X
X
X
X
X
X
X

X
X
X
X

X
X

M011 L

X
X
X

X
X

Processor-lOT
Instruction

Result

....

Status word gated to data lines during TS1. Information
on data lines shown below.

GTF H
GTF H
GTF H
GTF H
GTF H
GTF H
GTF H
GTF H

6-8
~

20
21
22
23
24
25
26
27

X
X
X
X
X
X
X
X

X
X
X
X

*From memory extension control, if present.

X
X

Data Bit
0
2
4
5

CAF H
NOP
RTF H, INT ON H
GTF H
SRQH
INTOFF L
INTON H
SKON H, INT OFF L

9-11

Information
Link Status
Status of INT RQST L signal
Status of Interrupt Enable flip-flop
USER MODE L signal status*
IF<O:2>*
DF<O:2>*

4.6.3 Program Interrupt Logic
Program interrupt data transfers are more efficient than programmed 1/0 transfers. In the program interrupt transfer
mode. the program is interrupted only when an option demands attention by asserting the Omnibus INT RQST L signal.
The interrupt system monitors this I NT RQST L signal. If the system is turned on when this signal is asserted. the
processor executes a hardware-generated JMS to location O. Simultaneously. it turns off the interrupt system; thus.
further interrupts can occur only when the present one has been serviced. A program subroutine is entered to determine
the identity of the requesting option. When this identity has been established. a servicing subroutine allows the option to
take part in a programmed 1/0 dialogue with the processor.
The Interrupt logic is shown in Figure 4-53. The system can be turned on when the ION instruction asserts the INT
ON H signal. Each stage of the DEC8271 quad flip-flop must be in the clear condition; if so. the DEC74153 multiplexer gates a high to input 01 of the quad flip-flop and a low to input 02. The quad flip-flop is set at INT STROBE
L time. asserting the INT ENA signal. During the next Fetch cycle. the high at multiplexer input B 1 is gated to input
02 of the quad flip-flop; again. input 02 of the flip-flop is high. 03 of the flip-flop might be high. as well. provided.
first. that the I NT RQST L signal has been asserted by a peripheral and. second. that the Fetch cycle being performed is that of a 1-cycle instruction. i.e .. I F SET L is low. However. if we assume that the Fetch cycle is part of a
multi-cycle instruction. 03 is low; thus. at INT STROBE L time INT DLY and INT ENA. only. are asserted. During the
concluding cycle of the instruction. and if the INT RQST L signal is low. all inputs to the quad flip-flop. except DO.
are high. At INT STROBE L time INT ENA. INT DLY. and INT SYNC go high and the INT IN PROG H signal is
asserted.
Because INT IN PROG H is high during TS4. the Instruction register is forced to JMS at TP4. while the Major State
register is forced to the Execute state. During this Execute state cycle. the program count to which control will return after the program interrupt. is stored in memory location 0000. The INT STROBE L pulse that occurs during the
forced-J M S Execute cycle clocks the quad flip-flop. negating the I NT 0 LY and I NT ENA signals and. as a result. the
INT IN PROG H signal (note that it now makes no difference what happens to the INT SYNC signal). The CPU then
proceeds to the interrupt servicing routine. At the end of the routine. an lOT instruction turns on the interrupt system
again. Note that there is a delay of at least one complete timing cycle from the time that the INT ENA signal goes
high until the INT IN PROG H signal can again be asserted (if data break devices suspend the normal timing. there
can be a delay of many more than one cycle). This delay enables the CPU to obtain the return address from memory
location 0000. restoring control to the program before allowing a new interrupt to occur.
The 10F instruction turns off the interrupt system by asserting the INT OFF L signal. Because both INT DLY and INT
ENA are high and INT SYNC is low when the system is on (the system can be on without an interrupt request). the
multi-plexer gates the lows at its DO and 01 inputs to the quad flip-flop. The INT STROBE L signal then clocks the
flip-flops. negating INT ENA and INT DLY.
Two CPU lOT instructions test the status of the interrupt system. The SKON instruction asserts the I SKIP L signal if
the interrupt system is on. i.e .. if the INT ENA signal is high. If I SKIP L is low. the SKIP flip-flop is set at TP3 time.
Then. during TS4. the C IN L signal is asserted. the program count in the PC register is incremented. and the instruction following SKON is skipped. Because the INT OFF L signal is generated along with the SKON H signal (Figure 452), the interrupt system is turned off just after INT ENA is sampled. The SRQ instruction can also cause a program
instruction skip. but only if an interrupt request has been generated by a peripheral.

4.6.4 Data Break Transfers
Data transfers between a data break device and memory or between the Programmer's Console and memory occur
in the CPU DMA state. This state provides direct communication between the device and memory. allowing the device to assume control of major register gating by asserting a number of Omnibus signals when it is ready to make a
data transfer. Figure 4-54 illustrates the part of major register gating that is most involved with data breaks. while
Figure 4-55 shows the logic that generates the applicable gating signals.

4-73

IF SETL~.-.________________________________~
INT RQST L - d . . . . . - . / -

I SKIP L
SRQ H
SKON H

INT OFF L
DI

STBI

STBO

R3(1)

R2 (1)

INT SYNC

F L

FI
AI
BO

MUX
74153
E45

INT DLY

INT IN PROG H

QUAD FF
8271
E31

CO
FO

R1(1)

INT ENA

DO
DO
INT ON H

AO 51

CLR LD

CLK OS

INIT LINT STROBE
L
OMA L
GTF H

SO
L
H
L
'):1- r----:-:"
H
Sl
L
L
H

r-::- f----:...

74153
STBO,l
L
L
L
L
H

FO
AD
BO
CO
DO
L

F1
A1
B1
C1
01

SHF
L
L

LD
L
H

8271
OUTPUT AFTER CLOCK (INT STROBE L)
SAME AS BEFORE CLOCK
SIGNAL AT CORRESPONDING INPUT

Figure 4-53

08-1~19

Program Interrupt Logic

When the data break device is ready to begin a transfer, it asserts the MS,IR DISABLE Land CPMA DISABLE L signals; the former disables both the fR register and the Major State register (E62). forcing the CPU to the DMA state,
while the latter negates CPMA->BUS L at TP4 time, removing the CPMA register from the MA lines. With the
CPMA register disabled, the device can specify the memory location from or to which data will be transferred.
Three types of data break transfers are available to a peripheral. i.e., Input (Break Deposit). Output, and Add to Memory (ADM). Table 4-16 provides the input/output signal relationship for ROM A. The entries for input codes 30(8)
through 37(8) apply to the Break Deposit and ADM operations; the Output transfer is just a variation of ADM. For
example: If the device is to make an ADM transfer, it places the memory address on the MA lines after asserting
CPMA DISABLE Land MS,IR DISABLE L; at TP1 of the DMA cycle, the device asserts MA, MS LOAD CONT L so
that TP4 of the DMA cycle does not clock thel CPMA register (Paragraph 4.4.2); at the beginning of TS2, the device
asserts BREAK DATA CO NT L, causing the M D EN L signal to be produced by the decoder associated with ROM A
(Figure 4-31 shows the decoder) and, thUS, gating the data in the addressed location to the adder; also, early in TS2

4-74

the device places the information to be added on the DATA bus, from where it is gated to the adder by multiplexer
E95; the result is placed on the SUM lines and loaded into the MB at TP2; because MD DIR L goes high at TP2,
the MB contents are placed on the MD bus and stored in the addressed memory location during the write operation.
If an output transfer is to be performed, the device follows the same procedure as for the ADM, without placing information on the DATA lines; the data to be transferred to the device can be taken from the M D lines at TP2, TP3.
or TP4 time.
The ADM operation might result in a carry-out from adder 0 (C OUT L is asserted). If so, the OVF flip-flop. Figure 455, is cleared at TP2 time, and the OVERFLOW L signal is generated during TS3. The device can use this signal as
directed by the program; however, OVERFLOW L is commonly used with a 3-cycle data break device to indicate the
last transfer of the data break operation.
The Non-stop Deposit function, entries 10(8) through 13(8) in Table 4-16, is intended to be used. primarily, during
bootstrap operations. The function gives the same result as Panel Deposit. but because STOP L is not generated. the
CPU continues to run. When the BOOT button on the Programmer's Console is pushed (or when the BOOT switch
on the Limited Function Panel is pressed). the Bootstrap Loader option provides the starting address for the bootstrap operation and asserts MEM START L LA ENABLE L and BREAK DATA CONT L. The option places information
on the DATA bus during each TS2 until the bootstrap program is loaded entirely. at which time normal CPU operations are resumed.

SUM 0

COUT L

DATA CMP L - - - 0 1
DATA ENA L - - - 0 1 1

--------+----------+----------------.

DATA 0 L

MA EN L
MD EN L

MQ-BUS L

MD 0 L

--------1------------.

MA 0 L -------~

AC0

MD DIR L

CPMA-BUS L - - - 0
CPMA LOAD - - - - - - f

08- 1320

Figure 4-54

Major Register Gating (BITO).
Data Break Transfer

4-75

Table 4·16
ROM A Input/Output Signals
(ROM Enabled for OMA Statel

Input
Code

LA
ENABLE L

Input Signal low
KEY
BREAK DATA
CONTROL L
CONT L

TS1

DATA CMP L

TS4

DATA CMP L, SEL A L, SEL C L

AND EN L

EXTENDED

TS2

DATA CMP L, SEL C L, SEL B L

MD EN L

ADDRESS,

TS3

DATA CMP L, SEL A L, SEL C L

AND EN L

FIELD 7

TS1

DATA CMPL

LOAD

1S4

DATA CMP L

EXTENDED

X
X

LOAD

MD EN L

ADDRESS,

36
37

4-76

-_.. -

"~~""-"-"-""

• _. ____ •__

__....,.._"' _ _ ' " _ ••• _"

Result

When console 'LXA' button is pushed, address is placed on data bus (DATA 6-11), gated to IF and DF registers and loaded by PULSE LA H.

See text

When console 'LXA' button is pushed, address is placed on data bus (DATA 6-11), gated to IF and OF registers and loaded by PULSE LA H.

See text

TS2

DATA CMP L, SEL C L, SEL B L

TS3

DATA CMP L

TS1

DATA CMP L, PC LD EN L, CARRY EN L, SEL B L

MA EN L

TS4

DATA CMP L, SEL G L

PC EN L

TS2

DATA ENA L

TS3

DATA CMP L

No major register operation.

TS1

DATA ENA L

When console 'LA' button is pushed, address is placed on data bus, gated to CPMA, and loaded by CPMA LOAD signal.

TS4

DATA CMP L, SEL C L

kEN L

LOAD

TS2

DATA CMP L, SEL C L, SEL S L

MD EN L

ADDRESS

TS3

DATA ENA L, PC LD EN L

TS1

DATA CMP L, PC LDEN L

TS4

DATA CMP L, SEL C L

PCEN L

PANEL

PC contents loaded into CPMA at TN, providing MA, MS LOAD CONT L is high (signal is low if 'E THIS' button is pushed).

TS2

DATA eMP L, SEL C L, SEL B L

MD EN L

EXAMINE

Data in addressed location loaded into MB at TP2; operator used 'MD' and 'DISP' buttons to display MB contents.

TS3

DATA CMP L, STOP L

Timing generator 'RUN' flip·flop cleared at TP3, halting timing cycle after TS4 is completed.

TS1

DATA eMP L, PC LD EN L

MA+1 (See Figure 4·54) loaded into PC at TP1.

TS4

DATA CMP L, SEL C L

TS2

DATA ENA L

TS3

DATA CMP L. STOP L

TS1

DATA CMP L

TS4

DATA CMP L

TS2

DATA ENA L, SEL C L, SEL B L

FIELD 0
MA+1 ..... PC at TP1
NON·STOP

PC contents loaded into CPMA at TP4.

DEPOSIT

Information on data bus gated to MS, loaded at TP2, deposited in addressed memory location.

See text

MA+1 (See Figure 4·54) loaded into PC at TP1.

PC EN L

PANEL

PC contents loaded into CPMA at TP4, providing MA, MS LOAD CONT L is high (signal is low if '0 THIS' button is pushed).

DEPOSIT

Console entry data placed on data bus, gated to MS, loaded at TP2. deposited in addressed memory location.
Timing generator 'RUN' flip·flop cleared at TP3. halting timing cycle after TS4 is completed.
No major register operation.

ADD TO
MD EN L

MEMORY
BREAK

. -

OCDR
Output Signal

ROM Output Signal

CPU
Time
State

r---'--'

No major register operation.
Data in addressed location gated to adder, added to information placed on data bus by peripheral; result loaded into MB at TP2, returned
to memory.
No major register operation.

TS3

DATA eMP L

TS1

DATA CMP L

TS4

DATA eMP L

BREAK

No major register operation.

TS2

DATA ENA L

DEPOSIT

Peripheral places information on data bus; information gated to MB register, loaded at TP2, written into addressed memory location.

TS3

DATACMP L

No major register operation.

QUAD F/F
E42
STA,STB,MAC
R3(1)1---- CPMA -

CPMA DISABLE L
CLK

BUS L

CLR

EL
DMA L
M S, I R 01 SABLE L ---------+-------1

TP4--------~----,

LOAD

co~'\,ME --------1

) - - . . . - - - - - - - - - - - - - - - - - CPMA LOAD

PULSE LA H - - - - - - - ,
KEY CONTROL L - - - - -........- - ,
L A EN ABLE L

---------+-----------------___1

BRE~~~fT~------------------------------I
T0

----------------------------___1

T1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ;

ROM A
DMA

10------- SEL C L
10------- SE L B L
10------- SE L A L
10------- CARRY EN L
: > 0 - - - - STOP L

10------- PC LD EN L
~---

DATA CMP L

10------- DATA ENA L

TP2 H

OVERFLOW L

COUT L
08 -1321

Figure 4-55

Data Break Transfer Control Signal Logic

Communication between memory and the Programmer's Console is also effected during the DMA state. The Panel
Exam and Panel Deposit functions permit an operator to examine or deposit data in an addressed location (refer to
Paragraph 4.6.4 for details); the Major Register gating during all timing cycles of both functions is outlined in Table
4-16.
The Load Address and Load Extended Address functions can be initiated by the Programmer's Console LA and LXA
pushbuttons, respectively. The applicable TS1 operations are shown in the table. Each of these functions can be initiated by the auto-start feature that is available with the PDP-8/A CPU. This feature was introduced in Paragraph
4.2.1; the Major Register gating and the appropriate timing will be detailed in the following paragraphs.
Figure 4-56 shows the auto-start timing, while Figure 4-57 illustrates the associated logic. The discussion that follows assumes that contact 4K of switch S 1 is closed and contact F7 is open, i.e., the starting address is in memory
field O.

4-77

POWER OK H-----1

CLEAR L

ON L \

1--1::1100 M S = : r -

MEM START L \

L--_____________________

RUN L /

GO (1)

TSl (Ll

- - - - - - -J

LJ
LJ
___________Jn,__________

TP4H _________________________~n,~

R1(0)

R0 (¢) /

DATA 0 L /

CPMA-BUS L - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - KEY CONTROL L

LA ENABLE L

MS,IR DISABLE L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

ZERtO'S
INTO CPMA

4000,
INTO CPMA

CPMA LOAD _ _ _ _ _ _ _ _ _ _ _ _ _ _--''--_ _ _ _...... '--_ _ _ _
NOTE:
Signal relationship is only
approximate.

~IL__

4001,
INTO CPMA
08-1322

Figure 4-56

AUTO-START Timing

When the auto-start sequence begins, the memory field address is loaded into the IF and DF registers of the KM8AA Extended Memory option. This event occurs during the first timing cycle of the sequence, when the KEY CONTROL L and LA ENABLE L signals are asserted. The entries in Table 4-16 for input codes 4(8) through 7(8) apply to
this first timing cycle. During TS 1 no major register operations take place (the R ESU LT entry for TS 1 indicates what
happens when an extended address is loaded from the Programmer's Console). During TS2, the data in the addressed memory location - a location that is both random (the state of the CPMA at power-on is uncontrollable) and
immaterial - is gated through Major Register gating to the M B register, loaded at TP2, and returned to the memory
location (M D DI R L goes high at TP2). This operation is of no significance to the auto-start feature, but is necessary
so that the data in the memory location is retained. During both TS3 and TS4 the DATA lines are high (multiplexers
ES6 and E87 are disabled). and the IF and DF registers are loaded with logic O. Since the SUM lines are also high
during TS3 and TS4, the CPMA register is loaded with zeroes at TP4.

4-78

r - - -,
I 4K

I 1K
400
I 200
I OFF

I
+3V

DATA 0 L
DATA 1 L
DATA 2 L

DATA 3 L
DATA 4 L

I ~
I

BREAK DATA CONT L

-1

RHO
RHO)

KEY CONTROL L

QUAD
F/F
E42

TSIL
DO

RO(1)
RO(O)

R3(1l

CLR

CLK

MEM START L

LA ENABLE L

MS,I R DISABLE L
CPMA
DIS L

CPMA -

BUS L

CLEAR L
TP4
CPMA LOAD
MA, MS LOAD CONT L
08- 1323

Figure 4-57

AUTO-START Timing. CPU Logic

During the second timing cycle of the sequence. KEY CONTROL L is negated. while DATA 0 L is asserted; input
codes 14(8) through 17(8) of Table 4-16 are pertinent. In TS1. no operation takes place (the RESULT entry indicates what happens when an address is loaded from the Programmer's Console). During TS2. the data in location
0000(8) is gated to the MB. loaded. and returned to memory. In TS3 the information on the DATA lines. 4000(8). is
gated to the PC register and loaded at TP3 time. During TS4. the PC contents are gated through Major Register gating to the CPMA register and loaded at TP4 time. At this same TP4 time MS.IR DISABLE L is negated and the CPU
goes into the Fetch cycle. carrying out the instruction in location 4000(8).
If the auto-start address had been located in memory field 7. Major Register gating operations in TS3 and TS4
would have been as outlined in the entries for input codes 1(8) and 3(8) of Table 4-16. During both time states the
AN 0 EN L signal gates the contents of the AC register through multiplexer E87 to the DATA bus. If the AC contains
zeroes. as it must for this function to work properly. 7777(8) is placed on the DATA bus and the IF and OF registers
are loaded with 7(8). All other autostart operations are the same as for memory field O.

4-79

Table 5-1

MRS-A Specifications
Characteristic

Specification

Power Requirements for the 1024 Bit Chip
1K size memory
4K size memory
Memory Cycle Time
ROM (alone)
ROM-RAM (ROM cycle)
ROM-RAM (RAM cycle)
Programming Method
Memory Capacity
Temperature
Environment
Testing

Typical
+5 V ± 5% 2 A
+5 V± 5% 5 A

Worst Case
+5 V ± 5% 2.7 A
+5 V ± 5% 7.4 A

1.5 J.l.s
1.6 J.l.s
300 ns are added to the normal RAM cycle
By external means (MR8-SA Programmer)
1K, 2K or 4K
0
5to 50 C
Standard Computer Environment
The tape used in programming the ROM is utilized to run the
diagnostics.

The major logic blocks and signal flow for accomplishing these functions are shown in Figure 5-3. The tim~ng of the
signals during one memory cycle is shown in Figure 5-4. A list and definition of the signals used in the timing diagram are defined in Table 5-2.
A general description of the operation of the M RS-A based on the functional blocks. the connecting signal lines. and
the timing diagram follows.
Detailed descriptions of each of the logic blocks are presented in Paragraph 5.4.
5.2.1
Addressing
At TP4 the ROM memory register is cleared and a new address is placed on the Memory Address lines MA<O11 >.

The eight least significant address bits MA <4-11> are driven directly to the memory chip array of 16 columns by
three rows and are applied in parallel to each chip where they are decoded by the chip circuitry: one word out of
256 on each chip is selected.
The four most significant address lines. MA <0:3>. are decoded to select one of 16 chip columns. The addresses
can range from 0-400(8) (the first column) to 7377-7777(8) (the 16th column). i.e .. from 0 to 4096( 10).
The address select logic also determines whether the address is within the ROM's memory space in the larger 32K
computer memory. This is done by decoding the three extended Memory Address lines. EMA<0:2>. A signal FIELD
H is transmitted to the control logic when a valid address has been decoded.
5.2.2 Tim ing and Control
The basic timing is provided by the processor. which generates four time pulses (TP1-TP4). four time states (TS 1TS4). and two memory control signals (M 0 01 R Land RETU RN H). However. additional control and timing signals
are required by the M R8-A for the selection of one out of two modes of operation mentioned above. ROM or ROMRAM combination.

5-5

MA4- MAll

I
EMAO-EMA2

Jr---AD-D-R--~____~CH~I~P_S:~EL~E~C_T-+___C_S~O_-_C~S_15
________________~

MAO-MA3

]

SELECT
LOGIC

IBMAO-BMA3

FIELD H
IORO

II)

:l
IXl

i t--T_IM_IN_G_ _ _- . t
o

ROM SEL L
14-------1
NTS STALL L
MD DIR L

. - - & . -_ _.............

I
I

th
13

BIT

RAM AOD L
MEM CLR L

TIMING
AND
CONTROL

ROM STROBE H
RAM EN H
MD EN H'

1
MEM DATA
[
14~----------M-D-(0---11-)-----------I

M0
GATING

RMA (0-11)
[
{ ...----------t

G:~I~G

oD--8
oQ--{]

'I REGISTER
MEMORY
114--t----I
1

/~ Q--{]

~/ ,;;;;,p ARRAY 16>3

RAM

•

RAM ADD L
08-1196

Figure 5-3

ROM Block Diagram

Table 5-2
MFtS-A Signal Definitions

Signal Name

Description

RAM SEL L

An enabling signal for the RAM transmitted through the E Connector.

RMAO L - RMA11 L

Twelve RAM address lines leading to the RAM through the E Connector, and
equivalent to the MAO-MAll lines of the Omnibus.

ROM STROBE H

Clocks ROM memory register contents onto the MD or RMA lines.

MEM CLR L

Clears ROM memory register.

FIELD H

Asserted when the memory field and memory size have been selected. Used to
enable the timing and control logic.

CHIP SELECT

16 signal lines, one for each column of three chips in the 16 X 3 memory array,
are selected by the address decode logic.

MD EN H

A gating signal generated in the control logic. Directs the register data to the MD
lines (ROM cycle).

RMA EN H

A gating signal generated in the control logic. Directs the register data to the RMA
lines (ROM/RAM cycle).

SMA (0-3)

Four signals derived from the corresponding MA <0-3>. Used to generate the
13th bit (Figures 5-3 and 5-7).

5-6

tt MD DIR L

MEM CLR L

*TP 4 H

liMA L

l
L.J

=><

IIRETURNH

TS1

FIELD H

NTS STALL L

\STALL RESET

-------/

II TP 1 H

t:-=

ROM STROBE L

175

nS-:-1

RAM SEL L

100

200

300

400

500

600

* Omnibus Signals
NOTE:

700

800

900

NANO
SECONDS

If the 13th bit is set. RAM SEL L will be asserted and the
STALL L line will not be released at the end of STROBE L.
The NTS STALL line will be held by the MR8·A for
400-800 ns by which time the MSS·A will have asserted
NTS STALL and taken control of the cycle.
08 -1183

Figure 5-4

ROM Timing Diagram

The ROM chips have a fast enough access time (80 ns) to be compatible with the READ time and the total memory
cycle time provided by the processor. However. when operating with the RAM additional time is required. first because the RAM chips are slower. and second. because of the delays due to switching from one circuit to the other.
A longer memory cycle time must be generated. This involves disabling the normal processor timing and activating
another timing chain. The new timing chain is located on the RAM module. M8311. However. the circuitry for initially stopping the processor clock is part of the ROM module. This circuitry asserts NTS STALL and stalls the processor at the next time state. Besides the capability to initiate STALL the circuitry can also override STALL and
return to normal processor timing.

5-7

5.2.3 Input and Output Signal Definition
The M R8-A utilizes signals that originate in the central processor and in other modules of the PO P-8/A. I n addition.
the ROM generates signals for the operation of the RAM. The Omnibus signals are as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

MA 0-11 L
MD 0-11 L
EMA 0-2 L
TS1 L
MD DIR L
NTS STALL L
TP4 H
ROM ADDR L
POWER OK H
RETURN H

The Omnibus signals are completely defined in Chapter 3.
Signals generated by the M R8-A are defined in Table 5-2.

5.3 PROGRAMMING
The ROM chips are programmed electrically using the fusible link technique. Initially all bits of the ROM are in the 0
.state. Information is introduced by selectively programming 1s in the proper bit locations. In addition. the chips that
make up the 13th bit must be a 1 in each address location that is allocated for write operations in the ROM-RAM
configuration. That is. all locations that will be modified during the execution of a program must be flagged. In this
category are instructions requiring a write operation such as DCA. ISZ. and JMS. as well as locations used as autoindex registers. and those reserved for the programming of peripherals.
5.3.1
Programming Operation
In programming. the address selection is accomplished by means of the same decoding circuitry used in the read
mode. A high voltage is applied to the four output pins. the Vcc. and Chip Set 1 Sel 1 terminals. to physically alter a
fusible nichrome link. The voltage pulses are approximately 48 V. To isolate these from the board circuitry. the chip
contacts that are used during programming are brought out to three top connectors (F. H. and J) using the fingers
on one side of the board only.
The connections to the board logic are made to the corresponding fingers on the opposite side of the board. During
normal operation. single width connectors join the contacts on both sides of the board. However. during programming. the connectors are removed and three cables from the programmer (blaster) are attached to the module. These
cables have special connectors that make contact with the fingers on one side only - the chip terminal side. Additional protection to the circuitry is provided by a series of switches that are opened during programming (Paragraph
5.5.)

5.3.2 Programming Procedure
The programming of the ROM involves generating a paper tape containing the ROM pattern and then writing this
pattern into the ROM using a computer controlled blaster. The M R8-SA blaster is a special facility available at Digital for programming simultaneously all the chips on the board. Detailed description of both hardware and software
aspects of this facility are found in the PDP-BIA Miniprocessor Handbook. However. a brief summary of the procedures used is included here to complete the presentation.

5-8

6.3.2.1
Preparation of the Paper Tape - In the preparation of the paper tape, the locations requiring a write function are flagged. As an example, let one such instruction in the program (at location 200) be:
1.

200/DCA 250

Write accumulator contents into Loca.tion 250.

250/( 1) 1000

Location 250 in ROM is flagged. It contains RAM Address 1000.

2a.

250/DWRITE 1000

Assembler statement for tagging writable Location.

In a core program, line 1. would be all that is required. When using the ROM-RAM combination, both line 1. and 2.
are needed.
A patch has been developed for the PAL S assembler to transform core type programs into a format required by the
ROM-RAM combination.
The writable locations in ROM are tagged using the DWRITE statement. The RAM addresses are specified. The assembler then generates a paper tape in the format used by the MRS-SA ROM programmer, which will program the
appropriate 13th bits. The format for the MRS-SA tape is shown in the PDP-BIA Miniprocessor Handbook, Chapter
11. The 12-bit data word, in this case the address in the ReadlWrite memory, is punched as a normal data word,
but in the second line of the data word, hole 7 is punched to signify to the programmer that the 13th bit for this
address should be set.
5.3.2.2 Blasting - The paper tape is loaded into a PDP-S/A computer that operates the blaster. An SK memory is
required. The entire board is blasted at one time instead of individual chips.

6.4 DETAILED LOGIC DESCRIPTION
The block diagram in Figure 5-3 should be used to understand the relationship between the blocks of logic and the
signals that are generated by these blocks. Table 5-2 defines these signals. All Omnibus signals are defi led in ( '1apter 3.
6.4.1

Addressing Block Diagram Description
The addressing section of the M RS-A accesses 4096 separate memory locations in the standard ROM by means of 12
memory address lines (MA<O: 11 » and 3 Extended Memory Address lines (EMA <0:2».
In addition. one 4K field must be selected from among S using 3 EMA lines of the extended memory control circuit.
The 13th bit logic is closely linked with the address circuitry. The detailed block diagram of the address select logic.
Figure 5-5 shows these functions.
The eight least significant lines MA<4: 11 > are decoded by a circuit which is an integral part of the chip. One of
256 locations is thus selected.
Address lines MA < 0: 3> are used to generate 16 chip enable signals that are routed to the 16 X array of chips.
Each of the 16 lines activates three chips arranged vertically on the board. Since each chip has 4 bits per word, a
12-bit word is addressed. The total number of words accessed is 256 X 16 or 4096.
The M RS-A field select switch settings are compared with the EMA inputs to select the field. Field size is decoded by
means of a similar circuit. The output of this field circuit is an enabling signal FIELD H which allows the selection of this
field of memory.

5-9

CHAPTER 6
MEMORY OPTIONS

PDP-8/A Memory Options are as follows:
·M R8-A Read Only Memory (ROM) in 1 K, 2K, or 4K sizes.
MS8-A Random Access Read Write memory (RAM) available in 1 K, 2K, or 4K sizes.
MR8-FB Reprogrammable Read Only Memory (PROM) available in 1 K size with 256 words of readlwrite RAM
memory.
MM8-AA 8K Core Memory
M M8-AB 16K Core Memory
The PDP-8/A memory system can be configured from ROM, RAM, or PROM or combinations of these memories.
The memory system can be expanded up to 32K provided there is adequate current available from the power supply.
Each of the various memory options is discussed in the following sections.

5-1

MA4- MAIl

[>0

MA3

MAO

[

EMA 2
SIZE
SELECT

MAl

EMAO-EMA2

RAB 2K SEL
2L1NES(ASB)

2KCHIP
ENABLE

MAO- MA3

FIELD
SELECT

1K
OR
2K
CHIP
SELECT

4 LINES

CHIP
ARRAY
16X3

CHIP
SEL DECODE

13 BIT
CHIP
ENABLE

FIEl.D H

CSO- CS15

- BMAO-BMA3
08-1195

Figure 5-5

Detailed Block Diagram of Address 5elect Logic

5.4.2 Field and Size Selection
The MR8-A is a 1 K. 2K. or 4K memory that can be located at any 4K boundary at a 32K memory array. i.e .. it must start
at address zero of one of eight 4K memory fields. The field selection logic is shown in Figure 5-6.
Three switches (52-6. 52-3. and 52-7) and a comparator circuit consisting of three Exclusive-NOR gates with their
outputs tied together decode the Memory Extension address on lines EMA<0:2>.
The output signal FIELD H is true only if each one of the inputs from the switch settings matches that of the corresponding EMA line. e.g .. if EMAO is low. switch 52-7 must be closed. The output of the corresponding ExclusiveNOR gate is a high and all other switch setting inputs must similarly correspond to their respective EMA line.
A table of memory fields vs switch settings is shown in Table 5-3.
Each Field has an address range of 4K. Field 0, as an example, is composed of addresses 0-7777(8). A full complement of 1 K chips on the M R8-A will start at address 0 and end at the 4K boundary of the field.
A similar arrangement of NOR gate comparators and switches selects the proper size. The two most significant address
lines MAO and MA 1 are utilized for this purpose.
The states of these lines for the respective field sizes are shown in Table 5-4.
The switch settings that correspond to the states of MAO and MA 1 are shown in Table 5-5.
The memory size selection circuit and the field selection circuit constitute a combined five bit comparison network
shown in Figure 5-6 that generates FI ELD H. which. in turn is gated to produce the enabling signal ROM ADD L.

5-10

SIZE SELECT
MA1----a

MAO -

.........-+--0
S2-8

FIELD H
EM A 2 - - - + - 0

S2-6
EMA I - - - 1 - - " 0

MEM SIZE

S2-1

S2-8

S2-5

0--

S2-3
C= Closed (Switch is ON)
0= Open (Switch is OFF)
X = DONT CARE

EMAO---+--OI

S2-7

5V-+---~~--~

FIELD SELECT

Figure 5-6

08-1194

Field and Size Selection

Table 5-3
Switch Setting to Select Memory Field
Field
S2-6
0

2
3
4
5
6

Switch Settings
S2-3
S2-7

0
0
C
C

0
0

C
C

0= Open (Switch is OFF)
C = Closed (Switch is ON)

5-11

0
0
0
0
C
C
C
C

Table 5-4
MAO and MA1 States for Memory Field Sizes
ADDR Line
1K

0
0

MAO L
MAl L

MEM Size
2K

4K
X
X

Logic 0 is HI
X = Doesn't Matter
Table 5-5
Switch Settings for States MAO and MA 1
MEM Size
S2-1
lK
2K
4K

0
0

Switch
S2-8

S2-5

C
C

X
X

C = Closed (Switch is ON)

0= Open (Switch is OFF)
X = Doesn't Matter

5.4.3 Chip Select Decoder
The address decoding circuit provides for the utilization of a 1 K (256 X 4) chip. In the 1 K chip, the 8 least significant address bits (MA4 to MA 11) are routed directly to the chip.
The four most significant bits, MAO to MA3, are decoded to generate the 16 chip select signals CSO to CS 15 for
the 16 X 3 chip array.
The decoding network is shown in Figure 5-7. Address lines MAO to MA3 are routed via one side of the AND-OR
gates to two 4 to 8 decoders (lC7442) to generate 16 chip select lines. Each chip select line represents 256 words.
The address decoding scheme is shown in Table 5-6.

5.4.4 The 13th Bit
The same type memory chip is used in the 13th bit as in the other 12 bits of the memory array. However, the chips
are organized in a 256 X 4 matrix for a total of 1024 bits. To be useful as a 13th bit a transformation of the 256
X 4 into 1024 X 1 matrix is required. A 4 to 1 multiplexer, IC 74153, is used for this purpose as shown in Figure
5-8.
The MA2 and MA3 lines are used to strobe the MUltiplexer. The four combinations of the two lines and their corresponding address ranges are shown in Table 5-7.
The output of the multiplexer has an address range of 1 K.

5-12

CS 0

\LEAST
5V

+5V

7442
DO

SIGNIFICANT
BIT
__
BMA3

MA 3

RAB(2K)
01

MA 2
5V

BMA2

RAB(2K)

ONE OF
TWO
EIGHT TO
FOUR
DECODERS

MA 1
+5V

MA0-~~-----------r~

+ 5 V - -.......
EMA

CS 7

2--~"'"

BMA I

0---

+5V

S4-3
BMA a

()---

S4-'

08-1193

Figure 5-7

Chip Select Decoding

Table 5-6
Address Decoding
LSB

MSB

Address Lines
Bit Value

2048

1024

512

256

128

ADDRESS RANGE
0-3778

MA 4

256X4
ROM
CHIP

400-7778
1000 -13778

MUX
74153

1K X I
08 - 1777 8

1400 -17778

08 -1188

Figure 5-8

13th Bit Mapping into 1 K X 1 Array

5-13

Decoded on Chip

Decoded on one of two I Cs
(7442)

MA 11

10
2

Table 5·7
States of MA3 and MA2 to Select an Address Range
Address Range

MA3

o
o

0- 255 (0 - 377 8 )
256 - 511 (400 - 777 8 )
512 -767 (1000 -1377 8 )
768 -1023 (1400 -1777 8 )

To obtain a 4K address range (4K words one bit wide), four such Chip-MUX assemblies are used and the most significant bits MAO and MA 1 are used (Figure Ei-9).
The output of this configuration is 1 bit. the 13th bit. with an address range of 4K. which in turn is used as key control element of the ROM.

5.4.5

Timing and Control

The Timing and Control Logic of the MR8-A is shown in Figure 5-1 O.lt contains two timing one-shots and two control flip-flops.
One timing element asserts NTS STALL L and the other generates the ROM STROBE signal which clocks the control flip-flops and the memory register.
Switch S6-1 grounds the 13th bit. All inputs to the control flip-flops are 0 and therefore the output is a ROM output. This switch permits isolation of the ROM during trouble shooting.
S4-7 is closed and S4-8 is opened when there is no writable memory. and ROM operates in the read-only mode.
The switch settings are reversed. S4-8 closed and S4-7 open when the mode of operation is ROM-RAM. A complete list of switch settings is found in Paragraph 5.5.

MA0=j
MAl

MA0

ROM
256 X 4

MAl

74153
MUX

1K X t
0-17778

1K XI
200037778

13TH BIT
4K XI
0-7777

MA0j

ROM
256 X 4

74153
MUX

IK X 1
400057778

MAl

MA0j
MAl

ROM
256 X 4

74153
MUX

lK XI
100077778

08-~'87

Figure 5-9

13th Bit Mapping into 4K x 1 Array

5-14

E19

~------------------------------4-----------v~STALL

S4-8

STALL
ONE
SHOT

5V
5

~------------~--~c

RAM
SEL L

RMA EN
H

MD EN H

+3V

RETURN
TSI L
+3V

+3V
08 -1203

Figure 5-10

Timing and Control Logic

5.4.6 Timing Generation
The STALL one-shot has a delay of 600 ± 200 ns. It is triggered when the Omnibus signal RETURN H goes high
and is gated with FIELD H which is asserted when a valid selection is made by the memory field and size select circuits. STALL is asserted immediately and is maintained for the duration of the pulse 600 ± 200 ns unless overridden by a Reset generated in the STALL control flip-flop. The conditions for aborting STALL will be explained in a
subsequent paragraph that discusses the utilization of the timing pulses in the control scheme.
The STROBE one-shot is triggered at the same time as the STALL one-shot. i.e .. when RETURN H goes high. The
pulse duration is 175 ± 25 ns. The output is gated with FIELD H (for the same reason as is the STALL one-shot)
and inverted by the NAN D gate E-18. A positive pulse used to clock the two control flip-flops and the ROM memory
register appears at the end of the timed delay.
5.4.6.1
Control Flip-Flops - The two control flip-flops shown in Figure 5-10 are used to generate the control signals. The D input to both is the' 13th bit and they are both clocked by the STROBE one-shot. The output. after inversion. of the lower flip-flop when the data input is high (13th bit = 1). is RAM SEL L. ·RMA EN H is asserted
gating the data to the RAM address lines. Both signals are used in the ROM-RAM cycle.
When the data input is a low (13th bit = 0) the output after inversion is RAM SEL H (not a RAM cycle) and MD
EN H is asserted enabling the M D lines routing memory data to the processor. The output of the STALL Control flipflop resets the STALL one-shot. When the data input is a low (13th bit = 0) and ROM ADD L is asserted the stall
reset permits ROM to continue operation in a read only mode while ROM ADD L disables other Read-Write memories. RAM among others.
5.4.6.2 Sequence of Control Operations - The sequence of the control operations is shown in the two timing diagrams (Figure 5-4 and 5-11).
Refer to the timing diagram in Figure 5-11. NTS STALL L is asserted at RETURN time regardless of whether it is ROM or
ROM-RAM cycle (point 1). At STROBE time (point 2). a decision is made whether to continue or abort STALL. This
decision is made by the STALL control flip-flop in response to the 13th bit data input. if pin E24-5 is low resetting the
STALL one-shot (point 3). Simultaneously. MD EN H (Pin E24-8) is asserted (point 4). When it is a ROM-RAM cycle.
STALL is continued and RAM is selected.
5.4.6.3 Initial Conditions - It should be noted that initally the two control flip-flops are set in opposite states. The
STALL flip-flop is set (pin 5 high) during a RAM cycle. The other flip-flop i,s in the reset condition (pin 8 high) during a
ROM cycle. So both the ROM and RAM cycles are "armed." When the selection is made at ROM STROBE. one fires and
the other is disarmed. This is shown graphically in the timing diagram (Figure 5-11). This decision does not take place
instantaneously. Pulling and releasing NTS STALL requires a time delay of approximately 80 ns. The memory cycle then
is 1.6 J.LS instead of the normal 1.5 J.LS.
5.4.6.4 Single Stepping - In the single step mode of operation. M EM CLR L is enabled. Initially this clears the
memory register and all register flip-flop outputs to the gates go to zero. enabling the M D or the RMA lines.
If it is a ROM cycle RAM SEL H is high at the beginning of TP4 and E 15 asserts MEM CLR L (Figure 5-12); therefore. the
memory register will be cleared immediately.
The data on the MD lines comes from two sources. the ROM and RAM registers. The ROM register is cleared immediately to make sure that valid data is placed on the M D lines in case the current cycle is a ROM cycle. Should it
turn out to be a RAM cycle. the initial output on the lines will be as until the RAM data appears. Because of the
inherent delay in the RAM cycle no valid data will be lost.

5-16

:;'ALL

RAM SEL (H)
RAM SEL

MD EN H (ROM)
RMA EN H (RAM)

STALL CONTINUED BY RAM
E24 - 5

STALL [

RESET STALL (ROM)

F/F
....------- -

E24-6

ROM SEL
SELECT RAM

STALL OIS _ _ _ _ _...J

L.._ _ _ _ _ _ _ _ -

STALL L (RAM)
-

STALL RESET (ROM)

TS1 ~~_______________ . . . J

1;S

RETURN H

ROM
STROBE

OIS

150

350

NANOSECONDS
08-1184

Figure 5-11

ROM-RAM Selection Timing

RAM SEL H

MEM
CLR L
08-1189

Figure 5-12 Single Step Operation

5.4.7
Memory Data and Memory Register
The first 1 K block of the 4K ROM memory shown in Figure 5-13 is typical of all 4 1 K blocks.
It consists of:
1.

Twelve preprogrammed chips. arranged in a 4 X 3 array

Address and chip enable inputs.

A memory output register that accepts the data content of the memory chips. and

Transfer lines to the processor (MD lines) and RAM memory (RMA lines).

These are described in the following paragraphs. The physical layout of the chips on the board is shown in Figure 514.

5-17

//[J/=-~IT~(:I~

8 LINES
I
I

----.------,

CS3

/
/

MD SEL H

BIT4

BIT3

256

MA4 256

E25

E30

256

MAtt

RMA SEL H

BIT
CS3
2
BIT 1

BIT 0
E 34 .-+--=--:.-'-------1 D

ADDRESS RANGE:

0-255 (0-3778 )

CSO

CS2

CSt

C S3

MD 0

MEM
C~R

256~~~~~~~~~~;;;------~
512-7:-,o8~66;-~~~~;i

RMA 0
E37

BITS

0-3

BIT 8

BIT 7

E20

MAtI'

256

BIT tt

MA 4

/ I T = B I T S (4-7)

r---/

//
/

r-------/

BITS

4f/ F's

0-3

---------------'

768 -1O:3~:~~!-~~~~; i ------------.--------'

RMA 3

FROM
STROBE
FLIP/FLOP

------I

MD 3

MEM
CLR

Figure 5-13

08-1192

Arrangement of 1 K Memory

~ - - --@] BITS e-l1
4TH K

~ 1ST K ~

2ND K

3RIO K

BITS 4-7
BITS 0-3

CS14

CS12

CS10

cse

CS6

CS4

CS0
08-118G

Figure 5-14

ROM 4K Memory - Physical Layout of Module

6.4.7.1
Memory Chips - The semiconductor chips are the storage elements of the ROM memory. Basically they can
be programmed electrically after they are mounted on a module. Three of the four top connectors on the module F. H. and
J. provide access to circuit elements on the chips that can either be shorted or opened by the application of a high voltage
to selected connector pins. This introduces either'a logical one or zero into the selected memory cells. Two techinques are
available for programming the memory chips after they have been mounted on the module: - fusible link and avalanching. In general. a high voltage or current pulse alters the internal circuitry of the chip providing either a new current path
or opening an existing one.
The individual chips are mounted on sockets for easy replacement and reprogramming in the event of failure or error.

5-18

5.4.7.2 Address and Chip Enable Inputs - Eight address lines (MA<4: 11 » are decoded on the chip and select
one of 256 locations. The chip select lines select one of four chips in a 1 K block. Each chip is organized as 256
words by 4 bits. Three chips are required for a 12 bit word.
5.4.7.3 Memory Output Register - The memory output register consists of 12 flip-flops (7417 5's) one for each
bit in the memory chip. i.e .. four flip-flops per chip and 12 for each memory location. The output of the register is
routed to the M D or RMA lines by the STROBE pulse described above.
5.4.7.4 Data Transfer Lines - Routing the memory register contents is controlled by the gating signals M D SEL
Hand RMA SEL H which originate in the Control and Timing section. In the event M D SEL H is asserted the memory contents are placed on the MD lines. When RMA SEL H is asserted the memory data is routed out on the RMA
lines.
5.4.7.5 Physical Layout - The physical layout of the memory is shown in Figure 5-13. It consists of four 1 K
blocks described in the preceding paragraphs. Each 1 K block consist of 12 chips arranged in an 4 X 3 array. The
least significant address is on the right and the most significant on the left. The four least significant bits are on the
bottom.
5.5 MRS-A SWITCH LIST
The following is a list of the settings for the various switches on the M R8-A: They are listed in numerical order for
easy reference. Switches are open for normal operation unless noted.
S1

SW1 - SW8