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Document:	DZQ11 Asynchronous Multiplexer User's Guide
Order Number:	EK-DZQ11-UG
Revision:	002
Pages:	48
Original Filename:

OCR Text

EK-DZQ11-UG-002

DZQ11 Asynchronous

Multiplexer
User's Guide

)

EK-DZQ11-UG-002

DZQ11 Asynchronous i
-

Multiplexer

- User's Guide

Prepared by Educational Services
~

Digital Equipment Corporation

2.7

First Edition, August 1984

Second Edition, August 1987

The informationin this documentis subject to change without
notice. Digital Equipment Corporatlon assumes no responsxblhty
for any errors herein.

DEC

DECmate
.DECUS
DECwriter
DIBOL
MASSBUS

PDP

P/OS
Professional
Rainbow
RSTS
RSX

UNIBUS
VAX
VMS
vT
»
Work Processor

flolilolilta)

The following are trademarks of Digital Equipment Corporation.

[SE——

Printed in U.S.A.

CONTENTS

GENERAL DESCRIPTION

INTRODUCTTION ...ttt
e e e e e e e e e e e e e e e eeeean, 1-1
PHYSICAL DESCRIPTION ......ccoooviiiiiiieeeieeeeeeeee, et
———— 1-3

W N —

TESE COMMECIOTS ...ttt
eeee e
et e e eeeeaeeeeseens 1-6
SPECIFICATIONS ...t e ———— 1-8
Environmental...........oooooeioiieieeeeeeeeeeeeeeeeens e e —————— R 1-8
CElectrical....ooooeie
ee
et e e et —————————— 1-8

Performance .........oceeeeveeeeeveeeeeeenenne..e
e e e e et eaatt e et e et aeaeeaaas 1-8
INEETTACES ...
eeeeeeeeeeeesesneeens 1 -8
Maximum Configurations............cceocvuviiiieiiieiiiiieeeeeee e 1-9

Throughput ... eveennnnn 199
RECEIVETS ....ooiiiiiiiiieiieeieee
e,e, v et e 1-9
TranSmItters .......ovvviveieeriiiee
et eeennsettt
ettt et et eaananas 1-9

Baud-Rate Generator ....................... ett ———ieeeeeeeeeerrr———————————————————_ 1-9
Performance Summary............e er————————e ———— e
———— 1-10
INterrupts .oc.eeeveieieieeeee e, ST et ees 1-10
Receiver-Done Interrupt..........eeevvveveveenennne.. veisverreriarnunsresstressnasansnennssstsns v 1-10
CSIHO-ALArmM INTEITUPL....ovviiiiiecieieec
e e e, 1-10
Transmit Interrupt.........ccovvvvevennnnne... ereeseresteeteeneetatnnnstrarunnrrranaesseraresarrasrrens 1-10

CHAPTER 2

INSTALLATION

2.1

{

NGO\
Db LR

oL
LW Wi -

ek
ok ok
ket

DZQ11 Configurations ......... eee—— et
e e e e e e e e —— 1-4

Interface Cables..................... e e e
s e e 1-6

2.4

btk

ket ok

kot

et ok pad

[—

CHAPTER 1
L0 LY L0 L Lo L 0 Lo LY Lo LY Ly L W L M N N R —

Page

2.5

SCOPKE....cc et
e e e e et e e e e st e e e e e e eaaaes 2-1
UNPACKING AND INSPECTION ....................................................................... 2-1
INSTALLATION PROCEDURE..........cccooeveian. e eeeeereerar————. 2-5
Modem Control JUmpers...........ccocovvvviivvviiieeeeennnnnn. et ereeeeeeeerrt
eeererrr—————————. 2-5
Module Installation......... eeeeesereeriessiisioasesssssasess veemenreettereieesenrastrasneeresisasavsraasisane ver 29
Testing DZQ11s in PDP-11 Systems ............. virererieaonieien verereeisrenieenes e —— 2-13
Testingin MicroVAX Systems..........c.......... e ——— reiesieesrisresreesntesraes e 2-15
DEVICE ADDRESS ASSIGNMENTS......ooooeeoeoeeeeeoeeeeeeeeeeeeeeeeoeeo ceeverenennnn. 2-15
INTERRUPT VECTOR ADDRESS ASSIGNMENTS .....oooeiiiieeeeeennn R 2-18

CHAPTER 3

DEVICE REGISTERS

3.1

3.2.5

SCOPKE.....ccc et
e e e e e e e et e e e s eeeaeeeeeeeaeeeeees 3-1
DEVICE REGISTERS .......ooveeeiieeeeeeeeeeeeeeeeeeeeeeee, rrr——— S 3-1
Control and Status Register........... s e ———— 3-1
Receiver Buffer............ Heerrerttteeueaaeeaeeeeearrrenarraerereertrrnrieseessrans rreeeeeeeeeeerann——— ... 3-4
Line Parameter Register....... eeeeeeerereeeertreeeerttaeeeratreerrraearaaa,SO 3-5
Transmitter Control REeGISTET ..........eueeeueeiieieee
e AR 3-7
Modem Status Register........oooovvevviiiiiieieeeeeeeeeeeeeeeeeeennse r——————— 3-8

3.2.6

Transmit Data REZISTET ......oocuviiuiiieiiieiieieieeeeeeee ettt e e e e eeeeeeeeeee e 3-8

i
k]

2.3.3
2.3.4

2.3.2

23.1

2.3

‘V

2.2

3.2

3.2.1
3.2.2

3.2.3
3.2.4

111

"PROGRAMMING

4.1
4.2
4.2.1
4.2.2

et e e e eeee e ssb e e ettt e e e ebrae st e baa e e e e s tr e e e e e e b e e e e ba e e s et e 4-1
SCOPE. ...ttt
PROGRAMMING FEATURES........;......., ...............................eeeee——————————aaaaaenans 4-1
TOLETTUPES .vevveveeveeveeereeeeveseseseeneneeneenae. e eeesereerreisetieranrraaareesanassesnartnas 4-1
Emptying the Silo......cccoovveiiiiiiiiiiiiiiii i . 4-2

Transmitting @ Character ........cceceevieeieeerieeneeereeiesicenens eereeereeeeeeiesereenneeenns. 473
t 4-4
ettt n et
Data Set Control........ccccceeeeveniinneveeesveesett

4.2.3
4.2.4

FIGURES

Page

Title

1-1
1-2
3
-4
-5
-1
-2

M3106 Module .....cooueeeveiineiiiiniiinn. et eeeeeteeeeett—eeettareeraaeeraraaaerrnaaaaaanns reevniaennns 1-2
DZQ11 System Applications ..............ettt e ens 1-3
sre e se s 1-5
" Elements of the DZQT11 OPtiON ..ccueevieiiirieiieieeierieeee ittt
Test Connectors H325 and H329 ..ottt 1-6
Lo0pback CONNECHION .....ccouvieeiuiiriiriiiiiii ittt 1-7
Jumper Locations (DC367B Socket Mount)..........cceevveivieniininnienene tebeseeresnnresersens 2-6
- Jumper Locations (DC367B Surface Mount) ................ ettteeeeeeeeeeea———————taaaaaaranensL 2-7

4
-5
-1

'DZQ11 Installation (BC11U-25)....ccoovvveiiiiinnnnnnn.SUUUUUPRRS et e 2-10
DZQ11 Installation (70-19964-00).......cccccceviiiiiiiiiiiiiiiieniee e 2-13
ata e e e cerereeeeeeaen, 3-2
e eeeeee
Register Bit Assighment ........ccc..cooovnniinnin.n. et eeeeer—rreee

UJNNI}JNNP—*P—"—‘

Figure No..

Jumper Locations (DC7085 Surface MoUNt)........cccoeviiiiininininnieiniieeeesecene 2-8

TABLES

Title

Table No.

2-1

2-2
2-3
2-4
|
2-5
2-6
2-7
2-8
2-9
3-1
3-2
3-3
3-4

|
|

Page

TItems Supplied per Configuration........c.ccoeeveeverrerreorniniiiiinee e e en—— 2-4

e eet —————— 2-9
Jumper ConfigUration ..........cceeereereereeeereerininiiiiine e
eererrrr—————— RO 2-10
e
ceverciiiiiinnnnn.
Options..........cco
Response
Break Character
and
Revisions
Etch
50-16374-01
on
E28
Selection:
Address Switch
2711
cevrrreeeeeeneinnnnns
iinineeeen,
eeeereeiiiiimiiiiiiii
ReviSions..........cc
E17 on 50-16374-02 Etch
Vector Switch Selection: E13 on 50-16374-01 Etch Revisions and

El11 on 50-16374-02 Etch Revisions........... eeeeeetreneeeeeeeeieetettaeeerarr—aeeerranaaeaaearrnas 2-12

—————————aaeeeeeeeeeeterrea——————ae 2-16
et
Floating Address Assignments................. eeeeeeeeeeeete
v 2-17
.t
..
DZQLL
One
and
One DUVI1I1
.2-18
e
s
e
e
e
a
e
rrr
tt
et
TWO DZIQLIS
2718
eereeeeeeieen.
coveeiiiiiiiiiieieeeeeeeeeeeee
LiSt
A551gnments
Address
Vector
Q-bus
of
First Part
3-1
e
iienniierneee
........ooiviiiiiiiiereinii
ASSIZNMENTS
Address
DZQ11 Register
3-3
essses
esirarreassssssreeeessannnan
reeeeeiiiiirieeessirtrereeee
.....uuvviieeeeeiiiiieeeraei
ASSIZNIMENTS
CSR Bit
3-5
e,
t
ett
......c..ccccceevuennene.
Assignments
Bit
RBUF
3-5
e
t
ett
iie
.....eeeoveriiiiiiiiiiiiiiii
ASSIZNIMENLS
Bit
LPR

CHAPTER 4

“

’l

CHAPTER 1

GENERAL DESCRIPTION

1.1 INTRODUCTION

|
.,
N
B
|

}

The DZQI11 is a Q-bus option. Its outline is shownin Figure 1-1. The DZQII is an asynchronous
- multiplexer that interfaces between a Q-bus processor and four asynchronous serial data communication
lines. The DZQ11 communications interfaces are compatible with RS-232-C (V.28) and RS5-423-A
(V.10/X.26). Thereis enough modem control to permit dial-up (auto-answer) operation with full-duplex modems*, such as the Bell models 103, 113, 212, or equivalent. The device, howeveris not intended for
‘use on pubhc communication services in countrles where it may not meet the requlrements for attachment
approval. Remote full-duplex, working as a control (master) station over private lines, is also poss1ble for

point-to-point or multipoint operation. Figure 1-2 shows some possible apphcatlons for the DZQl11ina
Q-bus system.

All the DZQ11 parameters can be easily controlled by software. These parameters are:
Baud rate
Character length

- Number of stop bits for each line

Enabling of parity checking for each line (odd or even)
Enabling of transmitter and receiver interrupts.

Additional features include:‘

]
B
-

°
o
o
o
°

Limited modem control
Zero receiver baud rate
Break generation and detection
Silo buffering of received data
Line turnaround.

The DZQ11 is program-compatlble w1th the Q-bus DZV11.

NOTE

N
|

]

" For details of the M3106 module vanatlons, see
Figures 2-1, 2-2, and 2-3.

o
e 0 @

Documents describing the DZQ11 are:

| }

DZQ11 Asynchronous Multiplexer User’s Guide - EK-DZQ11-UG
DZQ11 Asynchronous Multiplexer Technical Manual - EK-DZQ11-TM
Field Maintenance Printset - MP-01795-01
DZQ11 Maintenance Card - EK-DZQ11-MC

* The DZQ11 modem confrol does not support half-duplex operation or the secondary transmit-and-receive operation available on
some modems (such as the Bell 202).

1-1

VECTOR

ADDRESS
SWITCH PACK

SWITCHPACK
/ DC7085

ADDRESS

E28

E11

E17

E13
omnaand

VECTOR

SWITCHPACK

DC367B

DC7085

NOTE:

FOR DETAILS OF THE'M3106
MODULE VARIATIONS,SEE FIG. 2-1, 2-2,

AND 2-3.
MKV87-1490

[S——1

Figure 1-1 M3106 Module

1-2

A
R
N

1.2 PHYSICAL DESCRIPTION
|
The DZQII is made up of two components connected by a ribbon cable. The components are:

L
2.

A single dual-height module, 21.6X13.2 cm (8.51X5.19 inches), called the M3106 module. All
input and output connections are available on a 40-way connector. This module 1ncludes all active
circuitry, including the line drivers and recelvers

Adistribution panel 6.7X8.5 cm (2.6X3.3 in) that contains four filtered D-type connectors, and a

40-way ribbon connector that connects to the M3106 module.

A G7272 Grant Continuity card may be needed.
Refer to Section 2.3.2 for an explanation.

LOCAL

- |

‘

REMOTE
TELEPHONE

I LINE

» K
=3

paTA |

1ser

Dpzott

[

’

[ oata |

7| seT

REMOTE

TERMINAL

LOCAL

1 set _—C:?—__SET i

_doara ]

DATA |

T, ELEPHONE

| LINE

| | pza11 <r‘:> ol
<+
2
.

Sengtserc

LSI-11
SYSTEM

| I

Figure 1-2

DZQI1 System Applications

1-3

LS|-1‘1k
I SYSTEM

1.2.1 DZQI11 Configurations
"The basic option supplied is the DZQ11-M and is made up of the following:
1.

2.
3.

" Logic Module

User’s Guide Maintenance Card

Turnaround test connector

M3106

EK-DZQ11-UG
EK-DZQ11-MC
H329

The bé_sic option (DZQ11-M) can be supplied with one of five cabinet kits for installation into different
il
SA

systems. These are:

CK-DZQ11-DA (21-inch cable), example of use — PDP-11/23S
CK-DZQ!11-DB (12-inch cable), example of use— Micro/PDP-11
'CK-DZQ11-DC (30-inch cable), example of use — PDP-11/23+
CK-DZQ11-DF (36-inch cable), example of use — PDP-11/83
CK-DZQ11-D3 unshielded option (BC11U-25 cable).

The first four cabinet kits are almost identical except for the length of the flat ribbon cables, and the
in the CK-DZQ11-DC. They are made up of the following:
addition of an adapter plate
BCO5L-xx cable (see NOTE)
H325 line-loopback connector

1.
2.

The distribution panel — 70-19964-00
Mounting bolts and washers for the distribution panel.

3.
4.

A system integrated DZQI11 option is a DZQ11-DP.

NOTE

The distribution panels provide noise filtering
~ and static discharge protection on the communi-

cations lines. The -DC version has an adapter

plate which allows the panel to be mounted in the
PDP-11/23+.

BC05 L-xx cables are supplied in different lengths

for each kit as previously specified.

The CK-DZQ11-D3 cabinet kit is a cable assembly made up of four cables, with D-type connectors at
one end, and the other end connected to a socket which fits in the module connector. This kit does not
provide noise filtering or static discharge protection on the communications lines.

40-WAY

CONNECTORS

. CABLE BCO5L

§o

DISTRIBUTION PANEL
(70-19964-00)

M3106 MODULE

CABLE ASSEMBLY
BC11U-25

o
AN

Tl
I

TEST CONNECTOR H325

TEST CONNECTOR H329
MKV87-1491

Figure 1-3

Elements of the DZQ11 Option

1-5

Interface Cables

1.2.2

The connections from the DZQll use 25pm male subminiature D-type connectors as specified for
_

RS-232-C.

Circuit AA (CCITT*101)

Protective Ground

Pin 1

Pin7
Circuit AB (CCITT 102)
Pin 2
Circuit BA (CCITT 103)
Pin 3
Circuit BB (CCITT 104)
Circuit CD (CCITT 108.2) Pin 20
Pin 22
Circuit CE (CCITT 125)
Pin8
Circuit CF (CCITT 109)

Signal Ground
Transmitted Data
Received Data
Data Terminal Ready
Ring Indicator
Carrier

NOTE

Signal ground and protective ground are connected
together, through the chassis, by jumper W1 on
the 70-19964-00 distribution panel.
vl 2.3

Test Connectors

Figure 1-4 shows the two accessory test connectors H329 and H325.

The H329 plugs into the module I/O connector and connects line O to _line l,':and' line 2 to line 3.
The H325 plugs into an EIA connector on the distribution panel, or BC11U-25 cable assembly, to
loopback data and modem signals over a single line. The loopback connections are shown in Figure 1-5.

H325

‘

~ H329

RD1851

Figure 1-4 Test Connectors H325 and H329

CCITT The International Consultative Committee for Telegraphy and Telephonyis an advnsory committee

created under the United Nations to recommend worldwide standards.

1-6

}

H329 STAGGERED TURNAROUND
TRANSMIT O

—» RECEIVE 1

DTR O

» RING 1

— CARRIER
1

RING0 €——

CARRIERO «—1—

RECEIVE0 «—

NOTE:

DTR1
—— TRANSMIT1

LINE 283 ARE STAGGERED
IN THE SAME WAY.

]

'H325 LOOPBACK CONNECTIONS

scE 22

scT 18

])

scr —/

SEC XMIT ———

| |

SECRCV

XMIT DATA ——»

RCV DATA

—2

REQ TO

SEND

————

CLR TO SEND

1
E

CARRIER

NEW SYNC

DATA SET RDY

n
|

DTR

RING

-2
-

—O W1 JUMPER MAY BE
REMOVED OR

—0O

INSERTED

I
B

|
<

]

Figure 1-5

Loopback Connection

RD1876

1.3

SPECIFICATIONS

[

Environmental, eleetrlcal and performance speC1fications for the DZQll are listed in the following
‘paragraphs.

1.3.1 Environmental |

Storage temperature

-40 degrees C to 66 degrees C

(-40 degrees F to 151 degrees F)

Operating temperature
|

Relative humidity

5 degrees C to 50 degrees C
(41 degrees F to 122 degrees F)

-1

SRR

Within the range of 10% to 95% non-condensing, at a maximum
wet-bulb temperature of 32 degrees C (90 degrees F) and a

Dlgltal Eqmpment Corporation normally defines the
operating. temperature range for a system as S

degrees C to 50 degrees C (41 degrees F to 122

]

minimum dew point of 2 degrees C (36 degrees F).

NOTE

|
-

degrees F). The 10 degrees C (50 degrees F) differ-

ence between the upper limits quoted allows for the

temperature gradient within the system box.

The maximum operating temperatures must be derated by 1.8 degrees C/1000 m (1 degree F/1000 ft) for
operation at hlgh altltude sites.

132 Electrical

Power consumption
|

1.100 A at + 5 V dc typical
0.236 A at + 12 V dc typical

Q-bus loading

| |

Q-bus dc loads — 1.0 dc loads

The following paragraphs describe the DZQll performance capablhtles and restrictions.

All revisions to the M3106 module are of equal
functionality and performance.

}

System Bus Interface

)

]
- |

]

The DZQ11 module interfaces directly to a Q22 or other Q-bus via connectors Av and B. The

]

Serial Interfaces

]

module meets the DIGITAL Q-bus specification.

1.3.3.1 Interfaces - The DZQ11 module 1nterfaces d1rect1y to the Q-bus. Th1s includes Q—bus variations

with 22-, 18- and 16-b1t addressing.

)

Q-bus ac loads — 1.5 ac loads )

1.3.3 Performance

}

The DZQ11 serlal 1nterfaoes comply with a subset of EIA/CCITT standards RS-232-C/V.24.

The electrical characteristics are compatible with EIA/CCITT standards RS-232-C/V.28 and

RS-423/V.10 (unbalanced interface).

1-8

/\ N

.J
.
v

1.3.3.2 Maximum Configurations — The DZQI1 multiplexer is assigned a device address in the
floating address space. The floating address space starts at 760010g and extends to 763776g. Maximum
configuration of DZQ11s is not limited by floating address space, but is limited by the rules controlling a
system configuration of average size.

As the DZQ11 needs one backplane AB slot—palr it is physrcally possrble to mount:
e
e
‘o

Two M3106 modulesin a PDP-1 1/23 S
Three M3106 modulesin a Micro/PDP-11
Four to five M3106 modules in a PDP-11/23+

These numbers are the absolute maximum, because of the limited number of 70-19964-00 distribution
panels that can be installed in the rear panel of the mounting box. These numbers may also be limited by
the available capacity of -the power supply, if other options are installed in the mounting box |

1.3.3.3

Throughput — Each DZQI1 is capable of a throughput of 10970 characters per second

(chars/s). This rate is computed as follows.

(Blts/ s X number of lines X dlrectlons) divided by bits/char
(9600 X 4 X 2)/7 equals 10 970 chars/s, at 5 bits/ char with one start and one stop bit and no parity.

The full device throughput can only be maintained when a character--service routine takes lOO
- microseconds or less.

The DZQ11

has a maximum non—standard datarate of 19 800 baud At this rate the throughputis 22 625 |

characters per second.

1.3.3.4 Receivers — The receivers perform serial-to-parallel conversion of 5-, 6-, 7-, or 8-level code
with one start bit and at least one stop bit. The character length, number of stop bits, parity generation, and

operating speed are programmable parameters for each line. Both the receiver and the transmitter of a
corresponding line share the same operating speed, and the receiver line can be enabled or disabled.

Each receiver is double buffered and has an acceptable input distortion of 43.75% on any bit. The sum of
the character distortion must also not exceed 43.75%. An exception to this is the stop bit. The stop bit can
tolerate an error of 50%, thatis, the receiver will accept a stop bit as short as one half ofa bit period. Break
detectionis provided on each receiver via a register bit. In addition, the configuration of switchpack E13- 9
and E13-10 can cause the processor to boot or halt when a breakis detected on line 3.
1.3.3.5 Transmitters — The transmitters provrde parallel-to-serial conversion of 5-, 6-, 7- or 8-level
~ code with or without parity. The parity sense, when selected, can be either odd or even. The stop code can
be either 1 or 2 units except when 5-level codeis selected. When 5-level codeis selected, the stop code can
be set to 1 or 1.5 units. The character length, number of stop units, parity generation and sense, and
operating speed are programmable parameters for each line. The operatmg speed for the transmitter is
common with the receiver. Breaks can be transmitted on any line. The maximum start—stop distortion for
the output of a transmitter is less than 2.5% for an 8-bit character.
1.3.3.6 Baud-Rate Generator — The baud-rate generators are completely programmable. Each line
- has an independent generator which can select 1 of 16 baud rates. Speed tolerance for all rates is better |
than 0.3%. The baud rates are shownin Section 1.3.3.7.

1-9

1.3.3.7

Performance Summary The {ollowmg list shows the programmable features offered for each

line.

Character length
Number of stop bits

5-, 6-, 7-, or 8-level code

-1 or 2 for 6-, 7-, or 8-level code. B
1 or 1.5 for 5-level code

Parity

Odd, even, or none

Baud rates

50, 75, 110, 134.5, 150, 300, 600, 1 200, 1 800, 2 000, 2 400, 3
600, 4 800, 7 200, and 9 600 (and non-standard 19 800)

Breaks

Can be generated and detected on each line
Line 3 has a hardware response to detected breaks which, when
enabled, may generate a HALT or BOOT. ThlS facility can be
selected by switches.

1.3.4

Interrupts

The following interrupts are available on the DZQll

1.3.4.1

Receiver-Done lnterrupt ~ The receiver-done interrupt occurs every time a character

appears at the output of the receiver buffer register and the sxlo alarmis disabled. The receiver-done

interrupt can be enabled or disabled from the bus.

1.3.4.2 Sllo-Alarm lnterrupt - The silo—alarm interrupt occurs after 16 entries have been made into

the receive buffer reglster by the scanner. This interrupt disables the receiver-done mterrupt andis armed
again when the receive buffer register has been read
1.3.4.3 Transmit lnterrupt — The transmit mterrupt occurs every time the scanner finds a bufferempty condltlon and the transmitter control register bitis set for that line. It can be enabled or disabled
from the bus.

1-10

~
CHAPTER 2
INSTALLATION

2.1 SCOPE

This chapter contains the procedures for the unpackmg, mstallatnon and initial checkout of the DZQl 1

asynchronous multiplexer. It contains information on the following:
Device and vector address selectlon
Recommended cables
Testing after installation
|
Floating address and vector assignment.

2.2

UNPACKING AND INSPECTION

The DZQ11 is packed following normal commercial packing practlces To unpack, first remove all
packing material and check the equipment against the shipping list. (Table 2-1 contains a list of supplied
items per configuration.) Report any damage or shortages to the shipper immediately and inform the local
DIGITAL office. Examine all parts and carefully examine the module for damage, loose components
and breaksin the etched paths.

CAUTION

The M3106is suppliedin a protectnve sleeve. Do
not remove the sleeve until you are about to install
the module. Protect the module from static during
installation.
WARNING

The"' procedures describedin this chapter involve the

removal of the system covers, and should be
performed only by trained personnel

ATTENTION
Les procédures décrites dans ce chapitre nécessitent
Penlévement des capots du systéme. Elles ne pourront
étre effectuées que par du personnel qualifié.

VORSICHT!
Bei der Ausfuhrung der in diesem Kapitel
beschriebenen
Anweisungen
mussen
die
Systemabdeckungen entfernt werden. Dies sollte nur
von geschultem Personal ausgefuhrt werden.

2-1

i ATENCION!

Los procedimientos descritos en este capitulo

incluyen el desmontaje de las cubiertas del sistema y
debe ser realizado solamente por personal entrenado.

ADVARSEL!
Ifolge de procedurer, som er beskreveti dette kapitel,
skal systemets beskyttelsesplader fj ernes; dette ber
kun udferes af personer der ved hvordan dette skal
goares.

WAARSCHUWING

Bij de procedures die in dit hoofdstuk worden

beschreven dienen bepaalde delen van de
systeemomhulling te worden verwijderd; dit mag
- uitsluitend worden gedaan door opgeleid personeel.

VAROITUS!

Tissd luvussa kuvatut toimenpiteet luttyvat
jirjestelmin suojakansien irrottamiseen. Ainoastaan
koulutettu henkilékunta saa suorittaa nimi
toimenpiteet.

it
&

AE TR, AEAN—DROALZTIZDONWT

BRXTHDET, (rEE,

L¥EMoils#E

kioffi;nofTév

2-2

ATNTN

0°0INN NIDAI NIJITD AT 2791 MWINNA MYIU9N
.IN0IN BTN T DU PN N 1WXIICY NIWNA
Y

ATTENZIONE
La procedura descritta in questo capitolo comporta la
rimozione delle coperture e deve essere eseguita solo
da personale specializzato.

ADVARSEL

I dette kapitlet beskrives bl. a. hvordan man fjerner
dekslene rundt systemet. Dette arbeidet ma bare

utferes av fagfolk.

- AVISO

Os procedimentos descritos neste capitulo respeitam
a forma como se retiram as protec¢des do sistema.
Dada a sua especificidade, recomendamos que seja
executado por pessoal especializado.

VARNING
1 detta kapitel beskrivs hur systemkaapan tas bort.

- Detta faar endast utfoeras av utbildad personal.

2-3

\ Descripti(m

‘

H329 test cm}necto.r
DZQ11 User’s Guide (EK-DZQ11-UG)

.
|

‘_

-1

4 4

)

)
]

o~
[
'1

o
-

N
)
]

1 1 .1
8 - 4

)

]

4 8 -

]
a

[Nt —

90-06021-01 washers

1 o

BCO5L-01 12-inch cable

H325 test cox_mectorn
90-06633-00 screws

]

‘BC11U-25 cable assembly
BCOSL-03 36-inch cable

~ Quantity
DA DB DC D3 DF
|

70-19964-00 distribution panel

BCOSL-2F 30-inch cable

CK-DZQ11-DA/DB/DC/D3/DF Cabinet kits
|
A
Description

.74-28684-01 adapfer plate
BCOSL-1K 21-inch cable

Quantity

‘

* M3106 module

{-'“\)

/‘ )

- o

DZQ11-M Base Option

Table 2-1 Items Supplied per Configuration

2-4

2.3 INSTALLATION PROCEDURE

The following paragraphs describe the installation of the DZQI11 option in a Q-bus system
All variations have the same functlonahty For the DC367B versions, the address and vector switchpacks

are E28 and E13 respectively, while those for the DC7085 version are E17 and E11.

Figures 2—1 and 2-2 refer to the module variations that use the DC367B gate array. Figure 2-1 refers to the

version that uses the socket-mounted DC367B, while Figure 2-2 refers to the version that uses the surfacemounted

DC367B.

Figure

2-3

array.

refers

the

M3 106

Varlatron

that

uses

the

DC7085

gate

All other- components discussed in this manual have the same component numbers for all three variations,

with the exception of jumpers W14-W17. These four jumpers are not available on the socket-mounted
DC367B variation (Figure 2-1), and must be installed on the other two versions.

2.3.1 Modem Control Jumpers -

There are eight jumpers on both module versions which are used for modem control. The jumpers labelled

- W1 to W4 link the Data Terminal Ready (DTR) circuit to the Request To Send (RTS) circuit. This allows
the DZQ11 to assert both DTR and RTS when using modems that need control of RTS. These jumpers
must be installed for running the cable and external diagnostic programs. The four jumpers W5 to W8 link
the Forced Busy (FB) circuits to the RTS circuits. When these jumpers are installed, asserting an RTS

circuit also places an ON or BUSY level on the corresponding FB circuit. Jumpers W5 to W8 are not
installedin the factory; therefore, they need to be added if this signalis required by the particular modem
used. Table 2-2 shows thejumper line assignments.

—1c
]fi#so-1 6374-01 A1

/SOCKET
68-PIN

DC3678 =i

" plcC

ADDRESS
SWITCHPACK —

E28
VECTOR

W
w
B

E13

AUD RATE

=~ —

ANGE-SELECT

SWITCHPACK

OTHER CONFIGURATIONS
NOT SUPPORTED
BY DIGITAL

MKV87-1492

Figure 2-1 Jumper Locations (DC367B Socket Mount)

2-6

1
wzb--

W#sm 6374-01 B1

— e
veto-2
W17
W1 SF_:I .

SURFACE MOUNT

DC367B | PLCC

ADDRESS

SWITCHPACK
E28
VECTOR

E13

13
12

B AUD RATE

11
18 RANGE-SELECT

NOT SUPPORTED
BY DIGITAL

—]

|
MKV87-1493

Figure 2-2 Jumper Locations (DC367B Surface Mount)

2-7

— 17

W15 W17 ?l |

]f #50-16374-02

W14

W16

—

|
J1

] |

W5 W6

J [

|
|

]

Coo3C0TII3CIIIaCIII

BAUD RATE

RANGE-SELECT

DC7085

VECTOR

SWITCHPACK | -

W13 __

£18

Wizez=

\
|

SWITCHPACK ~.

ov2

-l

W'IOE‘ L XTAL _:

ADDRESS

wot-—-

——-

E11
'

E17

.
OTHER CONFIGURATIONS
NOT SUPPORTED
BY DIGITAL

|
MKV87-1494

Figure 2-3 Jumper Locations (DC7085 Surface Mount)

[OuS—

t
-

Connection

DTR to RTS

W3S
W6
- W7
W38

RTS to FB
RTS to FB
RTS to FB
RTS to FB

W2
W3
W4

2.3.2

Jumper Configuration

Jumper

[

[SS—

L——-J

Table 2-2

DTR to RTS
DTR to RTS
DTR to RTS

Line
3
2
1
0

3
2
1
0

Module Installation

" To install the M3106 module, perform the followmg
NOTE

This checkout procedure should be performed by
~
trained maintenance personnel only.
| CAUTION

Switch off power before msertmg or removmg,
modules.

The M3106 is a fine-line-etch PCB. Handle it
carefully to avoid damaging the etch.

Take anti-static measures to protect the module.

The Q-bus Interrupt Acknowledge and the DMA Grant signals are dalsy-chamed through the

- AB slots of the Q-bus backplane. If a DZQ11 is followed by a quad-size option in an AB/AB
(Q/Q) backplane, it may cause an AB slot-pair to be left vacant. In order to maintain the

continuity of the dalsy—chamed sngnals a G7272 Grant Continuity card should be mstalledin
the vacant A slot.

Referto Section 2.4 for descriptions of the address assignments. Set the address switches so that
the module responds to its assigned address. When a switchis closed (ON), a binary 1 is
encoded. When a switchis open (OFF), a binary O is encoded. The switch numbered 1 is
connected to address bit 12, 2 is connected to address bit 11, and so on (Table 2-4).

The other 10-position switchpack performs the vector selectlon. SW1tch position 7 is not used.
Switch position 6 is connected to vector bit 3, 5 is connected to vector bit 4, and so on. When a
switchis closed (ON), binary 1 is encoded. When a switchis open(OFF) a bmary Oisencoded
(Table 2-5).

Position 8 of the vector selection switchis a test switch which can disconnect the DZQII

oscillator from all circuitry. Make sure that this sw1tch is in the ON position before
installation.

Positions 9 and 10 of the vector selection switchpack controls the DZQI 1 response to a Break
character received on Line 3. There are three valid optlons HALT, BOOT, and no response.

Table 2-3 lists the switch selections.

Table 2-3

Effect of Break Character on Line 3

SWitch

OFF
"ON

OFF
OFF

OFF

Break Character Response Options
|

Noeffect =
Causes Processor to halt
Causes Processor to boot

Illegal Condition

(normal operation)
(specific application)
(specific application)
:

Make sure that +5 volts is present between AA2 and ground and that +12 volts is present

between AD2 and ground. Measure at the nearest accessible point, if the backplane cannot be
|

accessed.

Remove power and insert the module in an AB slot of ‘the backplane.

Apply power and make sure that the +5 volts and +12 volts is present with the module
installed.

CAUTION
Insert and remove modules slowly and carefully to
prevent damage to the module components on the
card guides, and to avoid changing switch selections
in error.

“THIS SIDE UP"

M3106 MODULE

CABLE ASSEMBLY
BC11U-25

MKV87-1604

Figure 2-4

DZQ11 Installation (BC11U-25)

2-10

]

Tabie 2-4
~

Address Switch Selection: E28 on 50-16374-01 Etch Revisions and E17 on 50-16374-02
|

<— MSB

6[5
'

16 15]14 13,12[11 10 918 7
SWITCHES
1 1[1 1 e
|

SWITCH

4 3[2
Aro]o

LSB

1] 0
0| o0

]

Etch Revisions

nomeer | 11213456789

DEVICE

ApDRess
17760000

ON|

17760010

|ON|

17760030

17760040

17760020

ON | 17760050

i
.

[ON|

ON|

) |

| —]ON|ON
/“JoN P

17760060

[ON

{oN

—

__|on|on

Ton]
ON

ON|

17760500

17760700

oN|loN]ON|ON|ON]ON|ON

17763760

oN|lonlon|on|oONjON|ON]|ON]|

17763770

ON = SWITCH CLOSED TO RESPOND TO A LOGICAL 1 ON THE BUS

17760300

17760600

ON | ON

117760200
17760400

ON|

17760070
17760100

2-11

MKV87-1602

Vector Switch Selflection: El13 on 50-1_6374-01 Etch Revisions and E11 on 50-16374-02

Table 2-5

MSB

Etch Revisions

‘15]14 13 12]11 10 9I8 7 6l5 4 3|2 11
olo 0 ol\o 0 o}————swncues——»lvo ol
N

[

SWITCH

NnumBer | 112|314

|
|

|5 ]| 6|

FOR SETTING

OFE13-7TO 10
"

ADDRESS
300

ON
ON|ON

310
320
330

ON
ON | ON | ON
ON | ON | ON [ ON

350
360

OoN | ON | ON

REFER TO
SECTION 2.3.2

VECTOR

ON | ON

ON | ON
ON | ON
ON | ON

ION| ON|JON | ON| ON

‘

340

370

400
500

1 ON

0
o

LSB

ON | ON

600

ON | ON | ON

700

ON|{ON|/ON|ON|

ON|ON|ON | ON|

ON|

760

770

ON = SWITCH CLOSED TO PRODUCE A LOGICAL 1 ON THE BUS
MKV87-1603

2-12

70-19964-00

CHANNELS

DISTRIBUTION PANEL

0
.

40-WAY HEADER

40-WAY RIBBON CONNECTOR

CABLE BCO5L-XX

J
RED LINE

M3106
MODULE

RED LINE

TO “A”

A
Q-BUS BACKPLANE

MKV87-1£;95

* Figure 2-5 DZQI1 Installation (70-19964-00)

;

2.3.3 Testing DZQllsin PDP-11 Systems
The following diagnostics are available to test DZQI11s installed in PDP-11 systems. DZITA and
DVDZD are only used when a link between two processors is to be tested.

CVDZA
CVDZB
CVDZC
CXDZB

DZV11/DZQI11 Logic Test — Part 1
DZV11/DZQ11 Logic Test — Part 2
DZV11/DZQ11 Cable/Echo Test
DECX/11 Module

- DZITA

I_nterprocesSor Test Program (ITEP)

DVDZD

Overlay for ITEP

2-13

Test the option as follows.

Run diagnostics CVDZA- and CVDZB in internal mode, to verify operation. Refer to the listing
|

for more help. Run at least three passes without error.

Insert the H329 test connector in J1 with the letter side facing up. J1 is the cable connector at the
top of the M3106 module.

Run CVDZA and CVDZB in the staggered mode, to verify module operation. Refer to the
diagnostic listing for the correct procedure. Run at least three passes without error.

If the unshielded cab-kit (D3) version is used, replace the H329 test connector with the 40-way
connector end of the BC11U cable assembly. Follow the “This side up” instruction on the
assembly. Refer to Figure 2-4 for assembly and interconnection instructions.

If the cab-kit versions CK—DZQI 1-DA, -DB or -DF are used, feed the cable through the rear of
the cabinet and connect it to the distribution panel. Mount the distribution panel in the opening at
the rear of the cabinet.

The -DC version is provided with an adapter plate to fit the largé opening in a PDP-11/23+.

Mount the adapter plate on the distribution panel, with four of the eight screws provided. Mount
~

the distribution panel as described above.

Connect the H325 test connector on the first line and run diagnostic CVDZC. Select the cable-

test part of the diagnostic. Three passes are needed without error. Repeat this step for each line.

of Q-bus interference with other
‘Run the DECX/11 system exer,ciser’ to verify the absence
,

system devices.

The DZQ11 is now ready for connection to external equipment. If the connection is to a local
terminal through either of the two options (BC11U-25 or 70-19964-00), a null modem cable
assembly must be used. Use the BC22A, BC22D, or BCO3P null modem cables for connection
between the option and the terminal. The H312-A null modem unit may also be used in place of
the null modem cables.

Connections between the option and a modem should be made using a BC22E or BCO5D cable.
All of the cables referred to, with the exception of the BCI 1U-25 , must be ofdered'separately as

they are not components of a DZQ11 option.

If a tei'minal is available, run the diagnosti.c, CVDZC in echo-test mbde to verify the cable

~connections and the terminal equipment.

2-14

v(‘.=’x“

234 Testingin MicroVAX Systems |

The following dlagnostlc tests are avaxlable for testing DZQl Isin MlcroVAX systems.

EHXDZ

EHKMV

DZV1 l/DZQl 1 Test

Macroverify- MicroVAX System Test

‘Macroverify is a standalone diagnostic which contains a DZV11/DZQI1 test module.

Referto the apprOprlate dlagnostnc listing,orto Chapters 11 and 14 of the MlcroVAX Owner’s Guide, for

details of how to run EHXDZ and EHKMYV.

MicroVAX diagnostic testlng is described in your MicroVAX Dlagnostlc Maintenance (MDM)

package.
2.4

DEVICE ADDRESS ASSIGNMENTS

On UNIBUS and Q-bus systems, a range of addresses (xxx60010g to xxx63776g)in the top 4K wordsis
a531gned as floating address space (xxx means all top address bxts = 1).

The first part of the list of options (sufficxent to include the DZQ11) which can be assigned floating device
addresses is given in Table 2-6. ‘Rank’ gives the sequence of address assignment for both Q-bus and
- UNIBUS options.
If addresses are assigned according to defined rules, configuration programs can check which options are
installedin a system. Having a combined list allows us to use one set of configuratlon rules and one
configuration program for both Q-bus and UNIBUS systems.

2-15

Table 2-6 Floating Address Assignments

Rank

~ Device

DJ11

DH11

(decimal)

- Modulus
(octal)

4 words
'8 words

4 words

DQIl

~ Size

4 words

DU11,DUVII*

DUPI11

4 words

LK11A

4 words

DMC11/DMR11

4 words

DZ11, DZS11,

DZQ11*/DZV11*

- DzZ32

- 4 words

* Q-bus device
For example, the address assignment sequences could be:
UNIBUS

Q-bus

DJ11
DH11
DQI11

No Q-bus equivalent of DJ11
No Q-bus equivalent of DH11
No Q-bus equivalent of DQll

DU11

DUPI11
LKI11A
DMCl11
DZ11

|
o

DUV11

- No Q-bus equivalent of DUP11
No Q-bus equivalent of LK11A
No Q-bus equivalent of DMC11

DZQI11 and so on.

Devices of the same type are given sequentlal addresses, therefore all DUVl Isina system will have lower
addresses than DZQ11s or DZVl1ls.

For the purpose of address assignment, DZQ11sand DZV11s are considered as devices of the same type.
The column Size(decimal)in Table 2-6, shows how many words of address space are needed for each
device. The column Modulus(octal)is the modulus used for starting addresses. For example, devices with
an octal modulus of 10 must start at an address whichis a multiple of 10g. The same ruleis used to select a
gap address (see assignment rules) after an option, or for a nonexistent device.

2-16

.
i
|
'
1
!
i
1
i
.

The assxgnment rules are as follows

~_~

Addresses, startmg at xxx60010 are assigned according to the sequence of Table 2-6

5
:

Optlon and gap addresses are ass1gned accordmg to the octal modulus as follows.

[

Devices with an octal modulus of 10 are ass1gned an address on a 10g boundary (the three

Devmes with an octal modulus of 20 are assngned an address on a 20g boundary (the four

lowest-order address bits
= 0)

Address space equal to the device’s modulus must be allowed for each device which is

A one-word gap, assigned accordlng to rule 2, must be allowed after the last device of each type

Aone-word gap, ass1gned accordlng to rule 2, must be allowed for each unused rank on the list if

connected to the bus

This gap could be blgger when rule 2 is applied to the following rank

a device with a higher addressis used. ThlS gap could be blgger when rule 2 is applied to the
following rank

Two examples of address assngnment follow. Table 2-7 shows addresses for a system with one DUVl 1

and one DZQ11. Table 2- 8 shows addresses for a system with no DUV11 and two DZQ11s. Note that
where thereis no Q-bus device at a specific rank, the UNIBUS device parameters must be used to assign

the gap. Vector assignments (see Section 2.5) are also shownin these tables.

Table 2-7 is supported by a description of how to apply the assignment rules.
Table 2-7
Rank

Address

xxx60010

xxx60020

3
4

- xxx60030
xxx60040
|

xxx60050

xxx60060

xxx60070

xxx60100

xxx60110
xxx60120

One DUVI11 and One DZQI11
Designation

Vector

DJ11 gap

DHI11 gap
DQI11 gap
DUVI11
DUVI11 gap
DUPI11 gap

|
-

300

LK11A gap

DMCI11 gap
DZQ11
‘DZQI11 gap

|
|

310

The first floating addressis 760010 As aDJ11 has a modulus of 103, its gap can be assngned to 760010.
The next avallable location becomes 760012.

As a DH11 has a modulus of 203, it cannot be assigned to 760012. The next modulo 20 boundaryis
760020 so the DHI11 gapis ass1gned to this address. The next available locationis therefore 760022.
A DQI11 has a modulus of 108 It cannot be assigned to 760022 Its gap is therefore assigned to 760030.
The next available locationis 760032.

2-17

to 760032. Itis therefore assigned to 7'60040,. | As
The DUV11 has a modulus of 10g. It cannot be assignedaddress
v
is 760050.
the size of DUV11 is four words, the next available

are no more DUV11s. As 760050
There is no second DUV11, so a gap must be left to indicate that there
The next available address is 760052.
is on a 10g boundary. The DUV11 gap can be assigned to this.
|

And so »on.

Table 2-8 Two DZQlls

|
Rank |

Address

DeSignatioxi o

xxx60010

DJ11 gap

|
|

xxx60100
xxx60110

8
8

DHI11 gap
DQI1 gap
DUVI11 gap
DUPI11 gap
- LKI11A gap
DMCIl11 gap

xxx60020
xxx60030
xxx60040
xxx60050
xxx60060
xxx60070

2
3
4
5
6
7

xxx60120

Ist DZQ11
2nd DZQ11

DZQI11

gap

Vector

300
310

2.5 INTERRUPT.‘VECTOR ADDRESS ASSIGNMENTS |

Addresses between 300g and 774g are designated as the floating vector space. These addresses are
assigned in sequence as in Table 2-9.

‘Each device needs two 16-bit locations for each vector. For example, a device with one receive and one
transmit vector needs four words of vector space.

The vector assignment rules are as follows.

e DLV11-J
1. Each device occupies vector address space equal to ‘Size’ words. For example,'th
vector would be
occupies 16 words of vector space. If its vector was 300g the next available

340g.

There are no gaps, except those needed to align an octal modulus.

The vector addresses shown in Tables 2-7 and 2-8 are assigned according to these rules.
Table 2-9
Device

|
DLVI11-J
- DLVI11,DLV11-F
DRV11-B
- DRV11
DLV11-E
VSvil
KWVl1l1
|
DUV11
DZV11/DZQl11

First Part of Q-bus Vector Address Assignments List
‘Modulus

Size

- (octal)

(decimal)

16
4
4
4
4
8
4
4
4

2-18

10
10
10
10
10
10
10
10
10

—

CHAPTER 3
'DEVICE REGISTERS

3.1
SCOPE
~ This chapter descnbes the format and bit functxon of each register in the DZQI11.

3.2 DEVICE REGISTERS
The DZQ11 contains six addressable reglsters Flgure 3-1 shows the bit asmgnments of these reglsters
and Table 3-1 lists the registers and related DZQ11 addresses.

Table 3-1 DZQ1l Register Address Assignments |
Register Name

Control and Status Reg.
Receiver Buffer
Line Parameter Register

Transmitter Control Reg.
-

-~
~

Mnemonic
|

CSR
RBUF
LPR

TCR

Modem Status Register

MSR

Transmit Data Register

TDR

Address
|

Program
Capability

76 XXXO0

Read/Write

T6XXX4

Read/Write

T6XXX2
T6XXX2

Read Only
Write Only

T6XXX6

Read Only

T6 XXX6

Write Only

XXX = Selectedin agreement with the floatmg devrce address system

3.2.1

Control and Status Reglster

The control and status register (CSR) can be addressed with a byte or word address. All bitsin the CSR
are cleared by an occurrence of BINIT, or by setting device Master Clear (CSR<O4>) The formatis
shownin Figure 3-1 and the bit assignments are listedin Table 3-2.

3-1

, H/R| W/|/R NTAS 2| |Wi|s/ .

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< 4 % 410 | 3Isw | 31y [ANnOa | 2 y 3vs VS 311 | AQHL _

HgOa.IsHw

SV<,.3a|

¢S0-'vVW

3-2

Table 3-2

Bit

Title

<02:00>

Not used

<03>

Maintenance

(MAINT)

CSR Bit Assngnments |

| Functnon
This is a READ/WRITE bit. When set it loops the serial output

connections of the transmitter to the corresponding serial input

connections of the receiver at the UART (Used for loopback test

only.)

<04>

‘When written to a 1, this bit generates ‘initialize’ within the DZQ1 1.

Master Clear

A read-back of the CSR with this bit set indicates initialize in

(CLR)

progress within the device. This bit is self-clearing. All registers,

silos, and UARTS are cleared with the following exceptions:

Only bit 15 of the receiver buffer register (Data Valid) is

Thehighbyte of the transmitter control register is not cleared by

<05> |

<06>

cleared; the other bits (<14:00>) are not.

Master Clear.

The modem status register is not cleared by Master Clear.

Master Scan

This read/write bit must be set to permit the receiver and transmitter

(MSE)

- (CSR<15>) is inhibited from setting, and the recelved character

Receiver

This bit penmts the generatlon of an interrupt, when CSR<O7> or

'Enable

Interrupt

Enable

control sections to start scanning. When cleared, Transmitter Ready
buffers (silos) are cleared.

CSR<13> is set. This bitis read/write.

(RIE)

Receiver Done

(RDONE)

Yoo

<07>

This is a read-only bit that is set when a character élppears at the
output of the first-in/first-out (FIFO) buffer. For the DZQ11 to run

in the interrupt-per-character mode, CSR<06> must be set and
CSR<12> must be cleared. With CSR<06> and CSR<12>
cleared, character-flag mode is indicated. Receiver Done clears
when the receiver buffer register (RBUF) is read or when Master
Scan Enable (CSR<05>) is cleared. If the FIFO buffer contains an
additional character, the Receiver Done flag may stay clear for up

to 1 microsecond, while that character moves to the bottom of the
FIFO.

<09:08>

<11:10>

Transmitter

These read—only bits indicate the line number whose transmit buffer

TLINE A)

cleared. Bit <08> is the least-significant bit.

Line Number
(TLINE B and

Not used

needs servicing. These bits are valid only when Transmitter Ready
(CSR<15>) is set, and are cleared when Master Scan Enable is

Table 3-2 CSR Bit /Assignments (Cont)
- Bit

<12>

Title

Silo Alarm
Enable
(SAE)

<13>

Silo Alarm
(SA)
-

<l14>

‘Transmitter

Interrupt

Function

This is a read/write bit. When set, it enables the silo-alarm and
prevents RDONE (bit <07>) from causing interrupts. If the
receiver interrupt enable bit (bit <06>)is set, SAE enables the silo- alarm (bit <1 3>)to generate an mterrupt after 16 silo entries.

Thisis a read-only bit set by the hardware after 16 characters have
been entered into the FIFO buffer. Silo Alarm is held cleared when

Silo Alarm Enable (CSR<12>) is cleared. This bit is cleared by a
“read to the receiver buffer register and does not set until 16 additional
characters are entered into the buffer. If Receiver Interrupt Enable
(CSR<06>) is set, the occurrence of Silo Alarm generates a
receiver interrupt request. Flag mode operation of the Silo Alarm bit
is permitted with CSR<06> cleared.

This is a read/write bit which must be set for Transmitter Ready to

‘generate an interrupt.

Enable

(TIE)
<15>

Transmitter

Ready
(TRDY)

This read-only bit is set by the hardware when the transmitter
“scanner stops on a line whose transmit buffer may be loaded with
another character and whose related TCR bitis set. The transmitter
~ line number, specnfiedin CSR<09:08>, is only valid when Transmitter Ready is set. Transmitter Ready is cleared by any of the
following conditions:
1.

When Master Scan Enable is cleared.

When the related TCR bitis cleared for the line number
pointed to in CSR<09:08>

If additional transmit lines need service, Transmitter Ready appears

~ again within 1.4 microseconds of the completion of the ‘transmit data
register load’ instruction. When Transmitter Ready occurs with
Transmitter Interrupt Enable set, a transmitter interrupt request is

generated.

3. 2 2 Recelver Buffer
|
The receiver buffer (RBUF) is a 16-bit read-only register that contams the received character at the output
of the FIFO buffer. A read of the register causes the character entry to be removed from the buffer, and all
other entries to shift down to the lowest location that is not occupied. Only the Data Valid bit
(RBUF<15>)is cleared by BINIT or by setting device Master Clear (CSR<04>). Bits <14:00> are
not affected The bit assignments for the RBUF register are listedin Table 3-3.

3-4

Table 3-3 RBUF Bit Assignments |
Bit

- <07:00>

Title

Function |

Received

These bits» contain the received character, right justified. the least-

Character
(RBUF D<7:0>)

significant bit is bit <00>. For short characters, bits that are not
used are logic low. The parity bit is not shoWn.

<09:08>

Received
These bits contain the lme number on which the Received Character
Line Number
~
was received. Bit <08> is the least significant.
)
(RX LINE B and
RX LINE A)

<11:10>

Not used

<12>

Parity Error

(PAR ERR)

<13>

This bitis set if the sense of the parity of the received character does
not agree with the parity defined for that lme

" Framing Error

- This brtis set if the received character did not have a stop bit present

(FRAM ERR)

< 14>

B -

| <l15>

atthe correct time. This bitis usually interpreted as indicating that a
break has been received.

Overrun Error

This bit becomes set when a received characteris overwritten in the

(OVRN ERR)
|

UART buffer (by a following character), before it has been
transferred by the scanner to the FIFO.
|

Data Valid -

- (DATA VALID)
|

- This bit, when set, indicates that the datain bits <14:00> is valid.

This bit permits the use of a character-handling program which again

- and again takes characters from the FIFO buffer until there are no

more available. This is done by reading this register and checking bit
<15> until the program gets a word for which bit <15> is zero.

Saerasrnur

Table 3-4

LPR Bit Assignments

Bit

Title

<01:00>

.
)

<02>

Parameter Line

3.2.3 Lme Parameter Register
|
|
The line parameter register (LPR) controls the operatmg parameters related to each linein the DZQl 1.
The LPR must be addressed with a word address andis a write-only register. The line parameters for all
lines must be loaded again following an occurrence of elther BINIT ordevice Master Clear. Table 3-4 lists
bit assignments.
-

Number
(LINE B and
LINE A)

Not used

Function
These bits specxfy the lme number for Wthh the parameter information-

(bits <12:3>)is to apply Bit <00> is the least—mgmficant bit.

Must always be written as a zero when specifying the parameter line |
number. Writing this bit as a one extends the parameter line number
field into nonexistent lines. Parameters for lines 00 to 03are not

affected.

Table 3-4 LPR Bit Assignments (Cont)
Title

Bit
<04:03>

- Character
|
Length
(CHAR LGTH
- B and CHAR
LGTH A)

Function

These bits are set to receive and transmit characters of the length

(except parity) shown below.
Bit 03

Bit04

<06>

6-bit
7-bit

1
0
1

0
1
1

<05>

5-bit

8-bit

Stop Code

This bit sets the stop code length; 0 = 1 unit stop, 1 = 2 unit stop (or

Parity Enable

If this bit is set, characters transmitted on the line have an
appropriate parity bit added, and characters received on the line have

(STOP CODE)

(PAR ENAB)

<0T>

Odd Parity
(ODD PAR)

<11:08>

Speed code
(SPEED CODE
D to SPEED

1.5 unit stop if a 5-level code is used).

their parity checked.

If this bit is set, characters of odd parity are generated on the line and
incoming characters are expected to have odd parity. If this bit is not
set, but bit <06> is set, characters of even parity are generated on
the line, and incoming characters are expected to have even parity. If
bit <06> is not set, then the setting of this bit will not have any effect.
The state of these bits determines the operating speed for the
transmitter and receiver of the selected line.

0
1

110
134.5

0
1

150
300

0
1
0
1
0
1
0
1
0

600
1200

_~_ OO

Not supported.

- 3-6

Baud Rate

OO~ —,OO—~—=OO0O

[S—

i — — — —m—, O 00000
OO

[

CODE A)

1800
2000
2 400
3600
4 800
7 200
9 600

19 800*

Table 3-4

Bit

Title

<12>

Receiver

(RXENAB)

<15:13>~

Function

Enabled

LPR Bit Assignments (Cont)

ThlS bit must be set before the UART receiver loglc can assemble

characters from the serial input line. This bitis cleared following a

BINIT or device Master Clear.

Not used
NOTE

The M3106 module can be modified by jumpers
W9 to W13, so that code 1111 selects baud rates
other than 19 800. This modiflcationis not supperted
by DIGITAL.

3.24

Transmitter Control Register

The transmitter control register (TCR)is a byte- and word—addressable reglster The low byte of the TCR
contains the transmitter control bits, and must be set to start transmission on a line. Each TCR bit position

is related to a line number. For example, TCR<00>>is related to line 00, bit <01> to line 01, and so on.
Settinga TCR bit causes the transmitter scanner clock to stop if the UART for this line has a ‘transmit
‘buffer empty’ condition. An interrupt is then generated if Transmitter Interrupt Enableis set. The scanner
clock restarts when either the transmit data register (TDR)is loaded with a character or the TCR bitis
cleared for the line on which the clock has stopped. TCR bits must only be cleared when the scanner is not
runmng, (thatis, Transmitter Readyis set or Master Scan Enableis cleared).

The line enable bits are representedin TCR<O3 00>. These bltS are read/write and are cleared by BINIT
or device Master Clear Bits <07:04> are not used, and are read as zero.
The high byte of the TCR register contains the modem control signal that can be written, data terminal
ready (DTR). The bits are defined as follows:
|

Bit
<08>
<09>
<10>
<11>
<15:12>

Name

DTR Line 00
DTR Line 01
‘DTR Line 02
- DTR Line 03
Not used; read as zero

Assertion of a DTR bit creates an ON condition on the appropriate modem circuit for that line. DTR bits
are read/write and are cleared only by BINIT Jumpers have been prov1ded to allow the RTS Cll‘Cl.lltS tobe
asserted using DTR assertions.

3-7

Modem Status Reglster

3.2.5

The modem status register (MSR)is a 16-bit read-only register. A read to this register gives the status of |

the modem control signals that can be read, Ring and Carrier. The ON condition of amodem control signal
is interpreted as a logical one. Bits <07:04> and < 15:12> are not used and are read as a zero. The other
bits are defined as follows:

Bit

‘Name

Bit

Name

<00>
<01>
<02>
<03>
<07:04>

Ring Line 00
Ring Line 01
~ Ring Line 02
Ring Line 03
Not used; read as

<08>
<09>
<10>
<1l1>
<15:12> =

Carrier Line 00
Carrier Line 01
Carrier Line 02
Carrier Line 03
Not used; read as zero.

3.2.6

Zero

Transmit Data Reglster

‘The transmit data register (TDR) is a byte- and word-addressable, wrlte-only register. Characters for
transmission are loaded into the low byte. TDR<00> is the least-significant bit. Loading of a character
should occur only when Transmitter Ready (CSR<15>)is set. The character thatis loaded into this register
is routed to the line def1nedin CSR<09:08>. The h1gh byte of the TDRis def1ned as the break control
register.

Thereis a correspondmg break bit for each of the four multlplexer lines. TDR<08> represents the break bit
for line 00, TDR<09> for line 01, and so on. TDR<15:12> are not used. Setting a break bit forces the
output of that line to space. This register is cleared by BINIT or device Master Clear. The break control
register can be used regardless of the state of the Maintenance bit (CSR<03>)

3-8

CHAPTER 4
- PROGRAMMING

4.1

SCOPE

This chapter contains information for programming the DZQI11 efficiently. The following paragraphs
discuss the DZQ11 from the programming point of view and describe recommended programming methods.

4.2 PROGRAMMING FEATURES
The DZQ11 has some programming features that allow control of baud rate, character length, stop bits,
parity, and interrupts. This section discusses the application of these controls to get the wanted operating
parameters.

4.2.1 Interrupts
The Receiver Interrupt Enable (RIE) and Silo Alarm Enable (SAE) bltsin the CSR control the way that

the DZQll receiver interrupts the processor.

- IfRIE and SAE are both clear, the DZQl 1 never interrupts the processor. In this event, the program must
regularly check that the datais availablein the silo, and empty the silo when datais present. If the program
operates from a clock, it should check for charactersin the silo at least as often as the time it takes for the
silo to fill, allowing a safety element to cover processor-response delays and time to empty the silo. The
Receiver Done (RDONE) bit in the CSR is set when a characteris availablein the silo. The program can
regularly check this bit with a test byte or bit test instruction. When RDONEis set, the program should
empty the silo.
o
|

If RIE is set and SAE is clear, the DZQll interrupts the processor and forces it to the DZQ11 receiver
vector address, when RDONE is set. This indicates the presence of a character at the bottom of the silo. The
interrupt service routine can get the character by performing a move instruction from the RBUE If the
program then leaves the interrupt routine, the DZQ11 1nterrupts when another characteris available (which
may be 1mmed1ate1y if additional characters were placed in the silo while the interrupt was being serviced).
Another way is for the interrupt service routine to respond to the 1nterrupt by emptying the silo before it
leaves the routine.

IfRIE and SAE are both set, the DZQ11 interrupts the processor to the DZQ11 receiver vector when the
Silo Alarm (SA) bit in the CSR is set. The SA bit is set when 16 characters have been placed in the silo
after the last time the program has accessed the RBUF. Accessing the RBUF clears the SA bit and the
related counter. The program should follow the procedure described in Section 4.2.2 to empty the silo
completely in response to a Silo Alarm interrupt. This makes sure that any characters placed in the silo
while it is being emptied are processed by the program.

NOTE
If the program processes only 16 entries in
response to each Silo Alarm interrupt, characters
coming in while interrupts are being processed

build up without being counted by the Silo Alarm
circuit. The silo may in the end overflow without
|
‘the alarm being issued.

If the Silo Alarm interrupt is used, the program will not be interrupted when fewer than 16 characters are

received. In order to respond to short messages during periods of medium activity, the program should
regularly empty the silo. The scanning period depends on the wanted response time toreceived characters.
While the program is emptying the silo, it should make sure that DZQ11 receiver interrupts are inhibited.
" This should be done by raising the processor priority. The Silo Alarm interrupt feature can greatly
~ decrease the processor overhead that would be needed by the DZQ11 receiver. This is done by removing
the need to enter and exit an interrupt service routine each time a character is received.

The Transmitter Interrupt Enable (TIE) bit controls transmitter interrupts to the processor. If enabled, the
DZQ11 interrupts the processor at the DZQ11 transmitter interrupt vector when the Transmitter Ready
(TRDY) bit in the CSR is set. This indicates that the DZQI1 is ready to accept a character to be
transmitted.

Each DZQI1 1 needs two interrupt vectors, one for the transmitter section and one for the receiver section.

If simultaneous interrupt requests are generated from each section, the receiver section would have

priority in placing its vector on the Q-bus. A receiver interrupt to address X X0 is generated from having

‘either a Receiver Done (CSR<07>) or Silo Alarm (CSR<13>) occurrence. A transmitter interrupt to

address XX4 is generated by Transmiitter Ready (CSR<15>). An additional prerequisite for generating

interrupts is that the individual interrupt enable bits are set. The recommended method for clearing
interrupt enable bits is first to raise the processor status word to level 4; next, to clear these interrupt enable

bits; and then lower the processor status word to zero. Using this method prevents false interrupts from
|
being generated.

4-2

4.2.2 Emptying the Silo

- The program can empty the silo by performing consecutive move instructions from the RBUF to
~ temporary storage. Each move instruction copies the bottom character in the silo so that it is not lost, and
clears out the bottom of the silo, allowing the next character to move down for access by a following move
instruction. The program can determine when it has emptied the silo by testing the Data Valid bit in each
~word moved out of the RBUF. A zero value indicates that the silo has been emptied. The test can be
performed by branching on the condition code following each move instruction. The test or bit test instruction
must not access the RBUF because these instructions cause the next entry in the silo to move down without
saving the current bottom character. Also, following a move from the RBUF, the next character in the silo
may not become available for up to one microsecond. Therefore, on fast CPUs, the program must use
enough instructions or no-operation instructions to make sure that consecutive moves from the RBUF are
separated by not less than one microsecond. This prevents a false indication of an empty silo.

4.2.3

Transmlttmg a Character

The program controls the DZQ11 transmitter through four registers on the Q-bus: the control and status
- register (CSR), the line parameter reglster (LPR), the transmit control register (TCR), and the transmit
data register (TDR).

Following DZQ11 initialization, the program must use the LPR to specnfy the speed and character format
for each line to be used and must set the Master Scan Enable (MSE) bitin the CSR. The program should
set the TIE bitin the CSR if it wants the DZQI11 transmitter to interrupt the processor.

The TCRis used to enable and disable transmission on each line. One bit in this register is related to each
line. The program can set and clear bits by using move, move byte, bit set, bit set byte, bit clear, and bit
clear byte instructions. (If word instructions are used, the Line Enable bits and the DTR bits are accessed |

together.)

The DZQ11 transmitter is controlled by a priority selector whichis contlnuously looking for an enabled

line (Line Enable bit set), which has an empty transmitter buffer. When a lineis selected, it loads the number
of the line into the 2-bit transmit line number (TLINE) field of the CSR and sets the TRDY bit, interrupting
the processor if the TIE bitis set. The program can clear the TRDY bit by moving a character for the
“indicated line into the TBUF or by clearing the Line Enable bit. Clearlng the TRDY bit allows the scanner
to continue 1ts search for lines needmg service.

To start transmission on an idle line, the program should set the TCR bit for that line and wait for the

scanner to request service on the line, as indicated by the scanner loading the number of the line into
~ TLINE and setting TRDY. The program should then load the character to be transmitted into the TBUF
by using a move byte instruction. If the interrupts are to be used, a useful way of starting up a lineis to set
the TCR bitin the main program and let the normal transmitter interrupt routine load the character into the
NOTE

[

TBUF.

(

{

The priority selector may find a different line needing

- service before it finds the line being started up. This
occurs if other lines request service before the scanner can find the line being started. The program must
always check the TLINE field of the CSR when
responding to TRDY, to make sure that it loads characters for the correct line. Assuming the program
services lines as requested by the scanner, the scanner
in the end finds the line being started. If more than
one line needs service, the scanner requests service in
priority order as determined by line number. Line 3
has the highest priority and line 0 the lowest.

To continue transmission on a line, the pregram should load the next character to be transmitted into the
TBUF each time the scanner requests service for the line as indicated by TLINE and TRDY. Because the

transmitters are double buffered, a high-priority line may request two consecutive loads.

To terminate transmission on a line, the program loads the last character normally, and waits for the

scanner to request an additional character for the line. The program clears the Line Enable bit at this time
instead of loading the TBUF.

h"'—"’

The line stays in this condition as long as the bit stays set. The program should use a move byte mstructmn
to access the BRK bits.

If the program continues to load characters for a line after setting the BRK bit, transmitter operation
appears normal to the program regardless of the fact that no characters can be transmitted while the line is
in the continuous zero-sending state. The program may use this facility for sending correctly timed zero
signals by setting the BRK bit and using transmit ready interrupts as a timer. The program must also make
sure that the line returns to the one state at the end of the zero-sending penod before transmlttmg any
additional data characters.

The followmg procedure does this. When the scanner requests service the first time after the program has

loaded the last data character, because the lines are double buffered, the last data character has only
started transmission. The program should therefore load an all zero character, and wait for the next service
request while the last character is transmitted. When the scanner requests service the second time, the
~ program should set the BRK bit for the line, and the zero character is overwritten. At the end of the zerosending penod the program should load an all zero character to be transmitted. When the scanner
requests service, indicating this character has started transmlssmn the program should clear the BRK bit
and load the next data character
4.2, 4

Data Set Control

r
|

The program may sense the state of the Carrier and ng Indicator signals for each modem and may
control the state of the Data Terminal Ready signal to each modem. The program uses two registers to
access the DZQ11 modem control logic. There are no hardware interlocks between the modem control
logic and the receiver and transmitter logic Any wanted sequence should be done under program control.
The Data Terminal Ready (DTR) bitsin the TCR are read/write bits. Setting or clearing a b1tin this
register turns the appropriate DTR signal on or off. The program may access this register with wordor byte
instructions. (If word instructions are used, the DTR and Line Enable bits are accessed together.) The
DTR bits are cleared by the INIT signal on the Q-bus but are not cleared if the program clears the DZQ1 1
by setting the CLR bit of the CSR.

The Carrier (CD) and Ring (RI) bits in the MSR are read-only bits. The program can determine the

current state of the Carrier signal for a line by examining the approprlate bitin the high byte of the MSR. It
can determine the current state of the Ring signal for a line by examining the approprnate bitin the low byte
~ofthe MSR. The program can examine these registers at different times by using move byte or bit test byte
Instructions, or can examine them as a single 16-bit register by using move word or bit test word
instructions. The DZQ11 modem control logic does not interrupt the processor when a Carrier or Ring
signal changes state. The program should regularly sample these registers to determine the current status.
Sampling at a high rate is not necessary.
-

4-4

‘*-J

The normal rest condition of the transmitted data connection for any line is the one state. The Break |

(BRK) bits are used to apply a continuous zero signal to the line. One bitin the TDRis related to each line.

Digital Equipment Corporation - Bedford, MA 01730