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DEC-08-HZDC-D

May 1972

135 pages

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Document:	UDC8 Universal Digital Control Subsystem Maintenance Manual 197205
Order Number:	DEC-08-HZDC-D
Revision:
Pages:	135
Original Filename:	http://bitsavers.org/pdf/dec/pdp8/industrialProducts/DEC-08-HZDC-D_UDC8_Universal_Digital_Control_Subsystem_Maintenance_Manual_197205.pdf

OCR Text

DEC-08-HZDC-D

UDCS
universal dligital
control sul)system
maintenance manual

digital equipment corporation · maynard. massachusE~tts

1st Printing April 1971
2nd Printing (Rev) DHcember 1971
3rd Printing (Rev) May 1972

The material in this manual is for infonnational purposes and is subject to change without
notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL

PDP
FOCAL
COMPUTER LAB

CONTENTS

Page
CHAPTER 1 GENERAL INFORMATION
1.1

General

1.2

Purpose

1-1

1.3

Functional Description

1-1

1.4

Physical Description

1-5

1.4.1
1.4.2

System Organization

1-5

Logic and Screw Terminal Cabinet H964AA/AB

1.4.3

Logic and Screw Terminal Cabinets H964CA, CB, CC, CD

1-5
1-5

1.4.3.1

1-11

1.4.3.2

849A Power Control Panel
H740D Power Supply

1.4.4

UDC8-N or -P Master File

1-11

1.4.4.1

Master Control D DO 1

1-11

1.4.4.2

File Unit DD02

1-11

1.4.5

UDC8 Expander File

1-11

1.4.6

Functional Modules and Signal-Conditioning Modules

1-11

1.4.7

Screw Terminal Cable Assembly BC40C

1-13

1.5

Specifications

1-14

1.5.1

General

1-14

1.5.2

System Performance

1-15

1.6

Reference Documents

1-15

1-1

1-11

CHAPTER 2 PROGRAMMING
2.1

IOT Format and Instructions

2-1

2.2

Address Format and Generic Code

2-2

2.3
2.4

Interrupt Structure
Data Format

2-2
2-4

2.5

Application Programs

2-4

2.6

Sample Programs

2-4

CHAPTER 3 PRINCIPLES OF OPERATION

Block Diagram Analysis

3-1
3-1

3.3

Detailed Circuit Analysis

3-3

3.3.1

General

3-3

3.1
3.2

General

3.3.2

Device Selector and IOT Decoder

3-3

3.3.3

Addressing

3-3

3.3.4

Interrupt and Skip Logic

3-13

3.3.5

Data Gating

3-13

3.3.6

Determining Change-of-State (COS)

3-14

3.3.7

Initializing

3-14

iii

CONTENTS (Cont)
Page
CHAPTER 4 INSTALLATION
4-1

4.1

Site Preparation

4.1.1

Space Requirements

4-2

4.1.2

Environmental Conditions

4-2

4.1.2.1

Humidity and Temperature

4-2

4.1.2.2

4-2

4.1.2.3

Cleanliness
Static Electricity

4.2

Power Requirements

4-2

4.2.1

Logic Power

4-4

4-2

4.2.2

Primary Power Requirements

4-4

4.2.3

Primary Power Receptacles

4-5

4.3

Installation Checkout

4-5

4.3.1

Unpacking and Visual Inspection

4-5

4.3.2

1/0 Bus Connections

4-5

4.3.3

UDC Bus and Connections

4-6

4.3.4
4.3.5

Externa I Cab Ii ng

4-6

Electrical AC Power Cabling

4-6

4.3.7
4.3.8

DC Voltage Checks
UDC Functional Checkout

4-7
4-7

System Pre-Use Requirements

4-7

4.3.9

UDC Add On Expansion

4-7

4.4

UDC System Configuration

4-8

4.4.1

Bi-Level Interrupt Identification

4-8

4.4.1.1

Module Interrupt Selection

4-10

4.4.2

System Interrupt Response

4-10

4.4.3

Generic Codes

4-10

4.4.4

Status and Control

4-11

4.3.6

4.4.5

User Identification - Functional 1/0 Modules

4-11

4.4.6

Address Assignments

4-11

4.5

Functional 1/0 Module Setup

4-17

4.6
4.6.1

W730 Contact Sense Relay Input Module

4-19

W732 Contact Interrupt Relay Input Module

4-21

W740 Contact Sense Solid-State Input Module

4-25

W742 Contact Interrupt Solid-State Input Module

4-27

M684 Flip-Flop Driver Output Module

4-31

M686 Single-Shot Driver Output Module

4-33

M802 Latching Relay Output Module
M804 Flip-Flop Relay Output Module

4-35
4-37

M806 Single-Shot Relay Output Module

4-39

A633 D/A Converter Output Module

4-41

W734 1/0 Counter Module

4-45

Signal Conditioning

4-53
4-53

Field Power

CONTENTS (Cont)
Page
4.6.1.1

Common Power

4-53

4.6.1.2

Isolated Power

4.6.1.3

Driver Output
Input Module Signal Conditioning for Contact Sensing

4-53
4-53

4.6.2
4.6.3
4.6.4

Input Module Signal-Conditioning for Logic Level Sensing

4-53

Mercury-Wetted Relay Contact Signal Conditioning

4-53
4-57

4.6.4.1

Location of the Arc Suppression Network

4-57

4.6.4.2

Determination of RC

4-57

4.6.4.3

Load Consideration

4-57

4.6.5

Driver Output Signal Conditioning

4-61

4.6.6

DAC Module Signal Conditioning

4-61

4.6.7

Counter Module Signal Conditioning

4-61

4.6.8

Signal-Conditioning Module

4-64

W400 Isolated Power Signal-Conditioning Module

4-69

W402 Common Power Signal-Conditioning Module

4-71

W403 Solid-State Driver Signal-Conditioning Module

4-73

A233 Buffered Voltage Signal-Conditioning Module

4-75

A234 Buffered Voltage Signal-Conditioning Module

4-77

A235 Buffered Current Signal-Conditioning Module
A236 Buffered Current Signal-Conditioning Module

4-79
4-81

Field Wiring
Wire Specifications

4-83
4-83

Analog Output Wiring

4-83

4.7.1.3

Digital Input Wiring
Digital Output Wiring

4-83
4-84

4.7.1.4

Grounding

4-84

4.7.2

Installation

4-84

4.7.2.1

Top Entry

4-84

4.7.2.2

Bottom Entry

4-84

4.7.2.3

Cable Routing Lengths

4-84

4.7.2.4

Breakouts

4.7
4.7.1
4.7.1.1
4.7.1.2

4.7.2.5

Rear Terminal Assemblies

4-84
4-84

4.7.3

Screw-Terminal Markers

4-85

CHAPTER 5 MAINTENANCE
General
Preventive Maintenance

5-1

5.3
5.3.1
5.3.2
5.3.3

Corrective Maintenance
General
Test Equipment Required

5.3.4
5.3.5

Scanner Clock Adjustment
Bus Clock Signal Adjustments

!5-1
!5-1
!5-2
!5-2
!5-3
!5-4

5.1
5.2

!5-1

H740D Power Supply Adjustment

CONTENTS (Cont)
Page
CHAPTER 6 ENGINEERING DRAWINGS
6.1

6-1

General

ILLUSTRATIONS
Figure No.
1-1

Title

Page

UDC8 Overall Block Diagram

1-3

1-2

UDC8 Maximum Configuration Diagram

1-9

1-3

DD01 and DD02 Configuration Diagram

1-12

1-4

UDC8 Assembly Details

1-14

2-1

IOT Format

2-1

2-2

Address Format

2-3

Status and Control Word Format

2-3

2-4

General Application Program, Flow Chart

2-5

3-1

UDC8 Detailed Block Diagram

3-2

UDC8 Logic Diagram

3-5

3-3

IOT Decoder and Truth Table

3-9

3-4

Address Scanner Logic

3-11

3-5

COS Logic

3-15

4-1

Space Requirements for UDC8

4-3

4-2

UDC8 Logic Cabinet Power Distribution Block Diagram

4-5

4-3

Interrupt Class Example

4-8

4-4

Functional Module 1/0 Chart

4-11

4-5

Functional Module 1/0 Page

4-12

4-6

G729 Address Jumper Module

4-12

4-7

Channel Address Scheme

4-13

4-8

Slot and Screw-Terminal Numbering Scheme

4-15

4-9

Simplified Schematic Diagram (W730)

4-19

4-10

Simplified Schematic Diagram (W732)

4-21

4-11

Location of Jumpers (W732)

4-23

4-12

Simplified Schematic Diagram (W740)

4-25

4-13

Location of Bit Response Time Capacitors (W740)

4-26

4-14

Simplified Schematic Diagram (W742)

4-27

4-15

Location of Jumpers and Bit Response Time Capacitors (W742)

4-16

Simplified Schematic Diagram (M684)

4-29
4-31

4-17

Simplified Schematic Diagram (M686)

4-33

4-18

Location of Bit Timeout Potentiometers and Jumpers (M686)

4-34

4-19

Simplified Schematic Diagram (M802)

4-35

4-20

Location of Bit Relay Contact Jumpers (M802)

4-36

4-21

Simplified Schematic Diagram (M804)
Location of Bit Relay Contact Jumpers (M804)

4-37

4-22
4-23

Simplified Schematic Diagram (M806)

4-38
4-39

ILLUSTRATIONS (Cont)
Figure No.

Title

Page

4-24

Location of Bit Timeout Potentiometers and Jumpers and Relay
Contact Jumpers (M806)

4-40

4-25

Simplified Schematic Diagram (A633)

4-42

4-26

Location of Adjustments and Jumpers (A633)

4-43

4-27

Simplified Schematic Diagram (W734)

4-46

4-28

Location of Jumpers and Input Switch (W734)

4-51

4-29

Common Power for Load Switching, Wiring Diagram

4-54

4-30

Common Power for Contact Sensing, Wiring Diagram

4-54

4-31

Isolated Power for Load Switching, Wiring Diagram

4-55

4-32

Isolated Power for Contact Sensing, Wiring Diagram

4-55

4-33

Logic Level (TTL) Input, Wiring Diagram

4-56

4-34

Logic Level (RTL) Input, Wiring Diagram

4-56'

4-35

Logic Level (DTL) Input, Wiring Diagram

4-57

4-36

Contact Protection Network Nomograph

4-58

4-37

Arc Suppression Circuit Characteristics

4-59

4-38

Arc Suppression for Extreme Inductive Loads

4-60

4-39

Alternate Arc Suppression for Extreme Inductive Loads

4-60

4-40

Arc Suppression for Capacitive Loads

4-60

4-41

Common Power for Driver Output, Wiring Diagram

4-42

Common Power for Driver Output, Schematic Diagram

4-62
4-62

4-43

Isolated Power for Driver Output, Wiring Diagram

4-63

Isolated Power for Driver Output, Schematic Diagram

4-63

4-45

Logic Level Output, Wiring Diagram

4-64

4-46

DAC Wiring Diagram

4-65

4-47

Counter Input and Output (Common Power), Wiring Diagram

4-66

4-48

Counter Input and Output (Isolated Power), Wiring Diagram

4-67

4-49

Counter Input and Output (Logic Level), Wiring Diagram

4-68

4-50

Simplified Schematic Diagram (W400)

4-69

4-51

Location of Jumpers and Component-Mounting Studs (W400)

4-70

4-52

Simplified Schematic Diagram (W402)

4-71

4-53

Location of Jumpers and Component-Mounting Studs (W402)

4-72

4-54

Simplified Schematic Diagram (W403)

4-73

4-55

Location of Jumpers (W403)

4-74

4-56

Simplified Schematic Diagram (A233)

4-75

4-57

Simplified Schematic Diagram (A234)

4-77

4-58

Location of Adjustments and Fuses (A234)

4-78

4-59

Simplified Schematic Diagram (A235)

4-79

4-60

Location of Adjustments and Fuses (A235)

4-80

4-61

Simplified Schematic Diagram (A236)

4-81

4-62

Location of Adjustments and Fuses (A236)

4-82

5-1

H740D Power Supply Fuses and Adjustment Controls

5-4

5-2

Scanner Clock Waveform

5-4

4-44

vii

TABLES
Table No.

Title

Page

1-1

System Organization

1-6

1-2

DD01 Module Complement

1-13

1-3

DD02 Module Complement

1-13

2-1

UDC8 Instruction Set

2-1

2-2

UDC8 Generic Code

2-3

3-1

COS Definition Table

3-14

4-1

UDC8 Power Requirements

4-4

4-2

Hubbell Wall Receptacle Part Numbers

4-5

4-3

Scanner Counting Characteristics

4-9

4-4

Jumper Options (W732)

4-22

4-5

Jumper Options (W742)

4-28

4-6

Jumper Options (W734)

4-50

4-7

Voltage Scaling Options

4-53

5-1

H740D Voltage Tolerances

5-1

5-2

Recommended Module Spares

5-2

5-3

Recommended Component Spares

5-3

5-4

Test Equipment Required

5-4

6-1

UDC8 Engineering Drawings

6-1

viii

CHAPTER 1
GENERAL INFORMATION

1.1 GENERAL
The UDC8 Universal Digital Controller 1/0 Subsystem, manufactured by Digital Equipment Corporation, is a
peripheral device to be used with PDP-8 Computer Systems in industrial data acquisition and con11rol applications.
This device can be used with both the positive and the negative bus PDP-8 computers (refer to the PDP·B
Maintenance Manual for information on the computers and 1/0 bus structures).

1.2 PURPOSE
The UDC8 operates under computer program control as a highly flexible digital input/output device capable of
interrogating digital inputs and driving digital outputs connected to functional modules. Up to 256 digital sense
and control functional modules, each handling up to 12 individual digital points, can be directly a:ccessEKI by the
UDC8. 1/0 functions that can be handled by the existing complement of modules include driver output, relay
output, contact sense, contact interrupt, and D/A converters. This complement of functional modules provides
the means for controlling and monitoring most devices found in an industrial and process control :environment.
Selection and inclusion of appropriate functional input and output modules in the UDC8 tailors the subsystem
to a specific application.

1.3 FUNCTIONAL DESCRIPTION
The UDC8 consists of one master me, up to 63 file units (DD02) and up to 256 functional modulies (Figure 1-1).
The interface controller (DD01) of the master file coordinates all activities within the UDC8 in response to programmed IOT instructions, address, and data from the computer. Each 1/0 file unit is set up to respond to a
unique 2-digit octal address (6 binary bits), and each module slot in this unit responds to a unique 2-bit binary
address.
Thus, each module can be accessed directly, using an 8-bit address. Once accessed, data (DATAO) can be loaded
into the module for output control, or data (DATAI) can be read into the computer from a modu:le to be sensed.
In addition to the direct access feature, the UDC8 contains an interrupt structure, which may be enable!d or disabled under program control, and an automatic scan feature to determine the address of an interruptin~J module.
Only those functional modules that require fast program intervention are equipped with and connect to the interrupt structure. A third feature of the UDC8 is a hardware gating scheme for determining when an input contact
has changed state, and the direction of that change. Both the interrupt structure and the hardware gating scheme
significantly reduce computer processing overhead.

1-1

UDCS- Nor P
MASTER FILE

UDCS-X
EXPANDER FILE

(UP TO 16 WORDS)

(UP TO 24 WORDS)

DD01

110 BUS
AC
BAC
BMB

INTERFACE
CONTROLLER

INT REQ
SKIP

CONT

UOC BUS

GEN
AND

AODR

cos

PULSE

---

OATAO
DATAI

INT

ADDRESS SELECTOR
(SAME AS DD02)

l l

J I

DD02

MODULE

I/O
MODULE

SIG COND SIG COND SIG COND SIG COND
CARD
CARD
CARD
CARD

l l
T T

-------[6U~D~~·J-----

DD02

DD02
TO ADDITIONAL
FILES
(216 WORDS MAX)

INTERFACE

IIO

I I

DD02

~MODULE
IIO

I/O
MODULE

I/O
I/C
MODULE MODULE

I/O
MODULE

SIG COND SIG COND SIG COND SIG COND
CARD
CARD
CAF'.D
CARD

I/O
MODULE

I/O
IIO
I/O
IJO
MODULE MODULE MODULE MODULE

I/O
I/O
I/O
I/0
MODULE MODULE MODULE MODULE

I/O
MODULE

SIG CONoi SIG COND SIG COND SIG COND
CARD
CARD
CARD
CARD

SIG COND SIG COND SIG COND SIG COND
CARD
CARD
CARD
CARD

I/O
MODULE

I/O
I/O
MODULE MODULE

l l
T T

l
T

l
I

T T

I/O
I/0
MODULE MODULE

I/O
MODULE

CUSTOMER INTERFACE

Figure 1-1

UDC8 Overall Block Diagram

1-3

1.4 PHYSICAL DESCRIPTION
1.4.1 System Organization
The UDC8 System is completely modular for ease of system configuration and expansion (Table 1-1 ). For
applications requiring 16 digital words (192 digital points) or less, the system is available in a single-cabinet configuration. Systems requiring greater than 16 digital words but less than 64 digital words are housed in a dual-

cabinet configuration - one cabinet to mount the electronics, and one for the screw terminal connectors. Four
dual-cabinet configurations are required to implement a maximum system of 256 digital words (3072 digital
points).
The system's electronics cabinets are organized in files. _The first file in the system is a master file which contains
the computer interface, system timing and control, address/scan register, COS gating, and address decoding hardware for selection of up to four digital words. The master file can also contain three additional filre units, each
providing address decoding for up to four digital words. The hardware for each 4-word group is implemented by
adding up to four functional 1/0 signal-conditioning modules and the required screw terminal cable assemblies -one for each module. Fully implemented, the master file contains 16 digital words.
Expansion beyond 16 words is accomplished by the addition of expander files. Each expander file contains provision for a total of 24 words (288 digital points) in six file units.
Industrial packaging and modular design permit the UDC8 to be configured and modified according to application needs. The UDC8 is available with screw terminals which provide a conveninet means for connecting customer
field wiring to the UDC functional modules. The screw terminals can be housed in the logic cabin et or in a sepa1

rate cabinet located adjacent to the logic cabinet. The logic for a maximum UDC8 configuration of 256 words
(functional modules) is housed in four industrial-type cabinets. Figure 1-2 illustrates the maximum configuration,
including screw terminal cabinets, and locates the major units and functional modules of the UDCB. The major
units and modules are described in the following paragraphs.
1.4.2 Logic and Screw Terminal Cabinet H964AA/AB
The H964AA/AB Cabinet is a 19 in. industrial-type cabinet which contains the 849A Power Control, H740D
Power Supply, two top-mounted forced-air-cooling fans, air filters, and full front and rear doors. It will house
one UDC8 file and, with H964MA mounting hardware, the necessary screw terminals for connection of field
wiring. The UDC8 file is mounted at the top, the screw terminals just underneath, and the power elements at the
bottom. Cabinet cooling is accomplished by blowing air down from the top of the cabinet and us:ing the hole in
the bottom of the cabinet for exhaust. Bottom entry of field wiring is standard, although top, re~r entry is available as an option. See Figure 4-1 for cabinet dimensions.
1.4.3 Logic and Screw Terminal Cabinets H964CA, CB, CC, CD
The H964CA, CB, CC, and CD Cabinets consist of a pair of 19 in. industrial-type cabinets secured to each other.
The right-hand cabinet (as viewed from the wirewrap side) houses the UDC logic, while the left-hand cabinet contains the necessary screw terminals. The logic cabinet is capable of housing up to three UDC8 file1s. In addition
to the UDC8 files, the logic cabinet contains the 849A Power Control, one H740D Power Supply for eaich file
implemented, two top-mounted forced-air-cooling fans; air filters, and full front and rear doors. The screw terminal cabinet contains the necessary screw terminals for connection of field wiring. The screw terminals are
secured to the cabinet with H964MA mounting hardware. Bottom entry of field wiring is standard, although top,
rear entry is available as an option.

1-5

Table 1-1
System Organization
Item
System Cabinets

Model

Description
Single cabinet for UDC System up to 16 digital words
(192 digital points). Contains logic power supply,
cooling fans, and filters. Screw terminals that mount
in the same cabinet requires separate mechanical assembly (Model H964MA).

H964A

Mechanical assembly for mounting screw terminals in
single cabinets.

H964MA

Prerequisite

(bottom entry only of field
cables).
A-115V power supply
B-230V power supply

H964AA or H964AB

EXAMPLE: Model H964AA designates a single cabinet (bottom entry only of field cables,
with 115V power supply).

Master File

Dual cabinet for UDC8 System. One cabinet houses
system electronics and logic (contains logic power supplies, cooling fans, and filters). Second cabinet for
termination of input field wiring on screw terminals.

H964C

Basic UDC8 system file contains interface and control,
address/scan register, change-of-state (COS) gating, and
provision for installing four functional 1/0 modules
(48 digital points) and 1/0 cable. Master file may be
expanded to 16 digital words ( 192 digital points) by
adding three DD02 File Units and appropriate number
of functional 1/0 and signal-conditioning modules.

UDC8

A-top or bottom entry of field
cables. 115V power supply
8-bottom entry only of field
cables. 11 5V power supply
C-top or bottom entry of field
cables. 230V power supply
- - D-bottom entry only of field
cables. 230V power supply

~ N-negative bus interface

P-positive bus interface

H964A or H964C
PDP-8/1
H964A or H964C
PDP-8/L or PDP-8/E

(continued on next page)

Table 1-1 (Cont)
System Organization
Item
Expander File

Model

Description
Provides expansion capability. Expander file contains
mounting hardware, file 1/0 cable, and provision for
installing four digital words and up to five DD02 File
Units, each capable of containing four digital words.
{Fully implemented expander file contains 24 functional 1/0 modules - 24 digital words or 288 digital
points.)

Prerequisite

UDC8-X
A-second or third file in
electronics cabinets

UDC8 Master File
plus H964C Dual
Cabinet

B-first file in each additional
electronics cabinets

Second H964C Dual
Cabinet

[

File Unit:s

Provides address decoding, control logic, and DD02 capacity for mounting up to four functional 1/0 and signal-conditioning modules (four digital words or 48
digital points).

Functional 1/0
Modules

Contact Sense (relay)
Contact Interrupt (relay)
Contact Sense (Solid State)
Contact Interrupt (Solid State)
Single-shot Driver
Single-shot Relay
Flip-flop Driver
Flip-flop Relay
Latching Relay
DAC
1/0 Counter

W730
W732
W740
W742
M686
M806
M684
M804
M802
A633
W734

Master File,
Expander Files,
DD02 File Units

Signal-Conditioning
Modules

Common Power
Isolated Power
Solid State Driver
Buffer - OV to +10V
Buffer - +1 V to +5V
-BUffifr -- 4mAto 20 rnA
Buffer - 10 mA to 50 mA

W400
W402
W403
A233
A234
A235
A236

Functional 1/0
Module

Screw Terminal/
Cable Assembly

Provides screw terminal connection for one word.
Connects to signal-conditioning module.

BC40C-4

Signal-Conditioning
Module

UDC8 Master File,
Expander Files

SCREW TERMINAL
CABINET 4

LOGIC
CABINET 4
(48 WORDS)

, - 46 - 911-1416 1921 - 2426-29

SCREW TERMINAL
CABINET 3

0002 0002 0002 0002 0002 0002

EXPANDER FILE
SCREW
TERMINALS

LOGIC
CABINET 3
(72 WORDS)

- 4 6 - 911-1416-19 21 - 2426 29
0002 0002 0002 0002 0002 0002

EXPANDER FILE
SCREW
TERMINALS

0002 0002 0002 0002 0002 0002

EXPANDER FILE
SCREW
TERMINALS

SCREW TERMINAL
CABINET 2

0002 0002 0002 0002 0002 0002

-- --

H740D POWER SUPPLY

EXPANDER FILE
SCREW
TERMINALS

0002 0002 0002 0002 0002 0002

EXPANDER FILE
SCREW
TERMINALS

H740D POWER SUPPLY

======

0002 0002 0002

0002 0002 0002 0002 0002 0002

======

rSLOT No.

1 - 46- 911-1416-1921-2426-29FILE
0001-0

0002 0002 0002 0002 0002 0002

EXPANDER FILE
SCREW
TERMINALS

H740D POWER 849A POWER
SUPPLY
CONTROL

LOGIC
CABINET I
(64 WORDS)

MASTER FILE
SCREW
TERMINALS

EXPANDER FILE
SCREW
TERMINALS

SCREW TERMINAL
CABINET 1

0002 0002 0002 0002 0002 0002

H740D POWER SUPPLY

1 - 4 6- 911-1416-1921-2426-29

EXPANDER FILE
SCREW
TERMINALS

H740D POWER 849A POWER
SUPPLY
CONTROL

LOGIC
CABINET 2
(72 WORDS)

H740D POWER 849A POWER
SUPPLY
CONTROL

----=-=-====

H740D POWER SUPPLY

H740D POWER SUPPLY
H740D POWER 849A POWER
SUPPLY
CONTROL
08-0674

Figure 1-2 UDC8 Maximum Configuration Diagram

1-9

1.4.3.1

849A Power Control Panel - The power control panel located in the front of the logic calj>inet controls

the application·and removal of system primary power. The power control contains a LOCAL/REMOTE switch,
a power ON indicator, a primary power contactor, and a circuit breaker. When the LOCAL/REMOTE switch is
placed in REMOTE, application and removal of primary power can be controlled from the computer. F1or the
LOCAL position, primary power is controlled by using the front panel 30A circuit breaker.
1.4.3.2 H740D Power Supply - The H740D Power Supplies are located as shown in Figure 1-2. They produce
regulated +5V (20A) and -15V potentials for the file logic circuits and 1/0 modules. The +5V andipowe~r ground
outputs are made available at an output connector on the rear of the supply. These outputs are routed to each of
the files by separate wire runs. Ground and +5V are connected from file unit to file unit, using jull!lpers on the
rear of the G729 Modules. The -15V potential is used only for level conversions involved with a negative 1/0 bus
interface, and is therefore routed only to the master file. The supply contains a 15A fuse for +5V, and a 5A fuse
for -15V.
1.4.4 UOC8-N or -P Master File
The master file contains one DD01 Master Control, space for up to three DD02 File Units, power supply harness,

1/0 bus cables, and bus terminators.
1.4.4.1 Master Control 0001 -The DD01 Master Control (Figure 1-3) occupies three file unit slots in a UDC8
Master File, and offers four insertion slots for functional modules. Only one master control is required for full
utilization of the UDC8. Two types of master controls are available. One type is required to interface with the
PDP-8 family of computers having a positive 1/0 bus, and another for the PDP-8 family of computcirs having a
negative bus. The only difference in the two types of master controls is the module complement as listed in
Table 1-2.
1.4.4.2 File Unit 0002- The DD02 File Unit occupies one of six available locations in a file andicontains four
slots for: functional modules. Although 63 file units are required for full utilization of the UDC8, ~ny number of
file·units (up to 63) can be serviced by one master control. The module complement of the DD02 is listed in
Table 1-3. The DD02 is an expander assembly which contains 24 slots arranged in four vertical rov\fs of s:ix slots.
The upper two slots in each row constitute an extension of the UDC bus. The lower four slots in e~ch row constitute a unique address within the address field, into which any of the functional modules may be inserted. The
M851 Address Decoder and G729 Address Jumper Module occupy the second pair of slots in the bus section
(AB2) and serve the four 1/0 slots below.
1.4.5 UDC8 Expander File
The expander file is a housing which contains a DD02 File Unit and may contain up to five additional DD02 File
Units, a BC41 A Bus Extender, and one M935 Bus Connector per DD02.
1.4.6 Functional Modules and Signal-Conditioning Modules
There are several types of functional modules available for the UDC8. Some serve as input module$ for receiving
sensory or control data from customer devices; others perform output functions for controlling cusitome1r devices.
A detailed description, a simplified schematic, and a photograph of each module currently available are provided
in Chapter 4. The functional modules are plugged into slots provided by the master file, expander flles, and DD02
File Units (Figure 1-4). Each functional module requires a signal-conditioning module for normali~ing input voltages, fusing, arc suppression, and for connection to field wiring. These modules are also described in Chapter 4.
The 12 data bits and field power connections on the signal-conditioning module are brought to the screw-terminal
cabinet via a cable consisting of 18 twisted pairs.
1-11

M903

G772

M113

M112

M624

M623

11
M942

M851

14
M935

M935

***

G729

M169

M111

M115

M206

M112

M113

M602

M206

M112

M602

M510

M302

M206

M115

M113

M112

M206

M111

M302

M307

M304

M401

*Modules in these slots are as follows
Positive Bus 0001 (P)
B4
- M101
B6 and C6 - M103
C1 and 01 - M623
Negative Bus 0001 (N)
B4
- M100
B6 and C6 - M102
C1 and 01 - M633

M401

M851
G729
**

Four

Functional

Module

Slots

M935
***

**Module G729 plugs into rear of Module M851.
***Flat Mylar Cable BC41A-5 is used to interconnect files within a cabinet from slot AB4 of the
last 0002 of a file to slot AB 1 of the first 0002 of
the next file. A BC41A-10 Cable is required
when extending the UDC bus to the first 0002
in a new cabinet. Module M942 plugs into slot
AB4 of the last 0002.

Figure 1-3 0001 and 0002 Configuration Diagram

Table 1-2
0001 Module Complement
UDC8-N

UDC8-P

Negative Bus

Positive Bus

M100
M102
M111
M112
M113
M115
M169
M206
M302
M304
M307
M401
M510
M602
M633
M623
M624
M851
M903
M942
G729
G772

M101
M103
M111
M112
M113
M115
M169
M206
M302
M304
M307
M401
M510
M602
M633
M623
M624
M851
M903
M942
G729
G772

Name

Quantity

Bus Data Interface
Device Selector
Inverters
NOR Gates
NAND Gates
NAND Gates
Gating Module
General-Purpose Flip-Flops
Dual Delay Multivibrator
Pulse Shaper
Dual Integrating One-Shot
Variable Clock
1/0 Bus Receiver
Pulse Amp I ifier
Bus Driver
Bus Driver
Bus Driver
Address Decoder/Bus Receiver
Flat Mylar Connector
Terminator Module
Address Jumper Module
Power Connector

1
2
3
5
3
2
3
5
3
1
1
3
3
2
2
1
1
1
3
2
1
1

Location
B4
B6 and C6
D2, D3, and E6
A7, D8, E2, F2, and F3
A6, D7, and E3
D4 and D6
C2, C3, and C4
ca, C9, D9, E1 F1 and F4
C7,E7
F6
E8
E9, F7, and F8
B7, B8, and B9
E4 and F1
C1 and D1
A9
A8
AB12
AB 1, AB2, and AB3:
AB11 and AB14
AB 12 (Piggy-back on M851 )
A4
I

Table 1-3
0002 Module Complement
Type/Part No.
M935
M851
G729

Name
UDC Bus Extender
Address Decoder/Bus Receiver
Address Jumper Module

Quantity

Lo~ation

1
1
1

AB1 *
AB2
AB2 (Piggy-back on M851

*See Paragraph 4.3.2 for bus extension details.

1.4.7 Screw Terminal Cable Assembly BC40C
Field wiring is connected to screw terminal assemblies (BC40C-4) which make the necessary connections between
the signal-conditioning modules and the field-wiring terminations. Each BC40C Assembly makes connec1tions
available through 16 of the 18 twisted pairs for control wiring. The two remaining pairs provide parallele1d conductors for bringing in external excitation power when using common power signal conditioning. Only 12 control
pairs are used with UDC8 Functional Modules. Each circuit is completed through a twisted pair of 'No. 26 AWG
stranded color-coded wires connected to a pair of screw terminals. The terminals will accommodate No. 14 AWG
wire, and are arranged in two strips of 17 terminals, each supported in line by a common steel anglf support.

1-13

MASTER
CONTROL

0001

FUNCTIONAL I /0
MODULE

Figure 1-4 UDCB Assembly Details

1.5 SPECIFICATIONS
1.5.1 General
Operating temperature:

0° to 50°C

Humidity:

Up to 95% without condensation

Cooling and filtering:

Dust filters and blower fans in each logic cabinet with
bottom exhaust

Input cabling:

Top or bottom entry to supplied screw terminals.
Screw terminals will accommodate No. 14 AWG wires.
However, customer wiring should be limited to No. 18
AWG (max) 2-wire twisted pair per digital point for a
fully-wired cabinet (72 words).

Cabinet dimensions:

Single Cabinet

Height:
Bottom entry:
Top entry:
Width:
Depth:

72 in.
75 in.
21 in.
30 in.

1-14

Dual Cabinet

72 in.
75 in.
42 in.
30 in.

Power:

115/230V, 50 to 60 Hz, single-phase, 500 VA (max)
for logic. Possible additional 700W for 48V field excitation in 72 12-bit words of signal conditionin!~·

Heat dissipation:

1800 Btu/hr for logic power. Possible additional 2500
Btu/hr for 72 12-bit words of signal conditioning.

1.5.2 System Performance
Modes of operation:

a.
b.

c.
d.

Programmed digital output
Programmed analog output
Programmed digital input
Interrupt control led input
Interrupt controlled counting functi'On

Data Format:

(Paragraph 2.4)

Number of digital inputs and outputs:

256 12-bit words (3072 -digital points) maximuim

Type of input and output:

See functional modules described in Chapter 4

Input and output word (module) selection:

Directly addressable

Interrupt module identification:

4-bit module generic code and an 8-bit address

Interrupt scan:

Locates address and module type in a minimum of 5 µs
(20 µs worst case)

1/0 data rate:

1 x 10 5 12-bit words/sec

Computer interface:

Direct interface to positive or negative bus PDP-8
Computers

System clock rates:

Three clocks are available to each 1/0 word:
a. 0.63V rms at line frequency
b.
175 Hz - 1.75 kHz adjustable
c.
1.75 kHz - 17.5 kHz adjustable

For functional and signal-conditioning module specifications, see Chapter 4.
For controller module replacement schematics, see Volume 11.

1.6 REFERENCE DOCUMENTS
The following documents are essential in gaining an understanding of the PDP-8 Computer System:
Small Computer Reference Manual
PDP-8 Maintenance Manual
PDP-8 User Guide

The following diagnostic program is essential in establishing the performance of the UDCB subsystem:
UDC8 System Function Exerciser

UDC-8EX (MainDEC-08-DBYB-D)

1-15

CHAPTER 2
PROGRAMMING

2.1

IOT FORMAT AND INSTRUCTIONS

The UDCB responds to eleven unique IOT instructions employing device select codes 35 8 and 36 8 • These eleven
instructions, along with other computer instructions, are used to develop the program for controlling the operation of the UDCB. The IOT instruction format is illustrated by Figure 2-1; each instruction is listed and described
in Table 2-1.

OPERATION
CODE

DEVI CE SELECT CODE

OPERATION
SPECIFICATION
CODE
08 -0676

Figure 2-1

IOT Format

Table 2-1
UDC8 Instruction Set
Mnemonic

Instruction Code

Operation

(Octal)

UDSF

6361

Skip on UDC Flag and Clear Flag - If the UDC flag
is set this instruction will generate a skip pul1se, causing the computer to skip the next instruction and
clear the UDC flag.

UDEI

6364

Enable UDC Interrupt Flag

UDDI

6365

Disable UDC Interrupt Flag

UDLA

6363

Load Address - An 8-bit address (AC 04 thnough 11)
is loaded into the address/scanner register of! the
UDCB for accessing a specific module, after which
accumulator is cleared.

(continued on next page)

2-1

Table 2-1 (Cont)
UDC8 Instruction Set
Mnemonic

Instruction Code

Operation

(Octal)

UDRD

6366

Read Data - Clears the accumulator and reads data
from whichever module has its address stored in the
address/scanner register.

UDLD

6367

Load Data - Loads contents of accumulator into whichever module has its address stored in the UDC address/
scanner register, after which accumulator is cleared.

UDSS

6351

Skip On Scan Not Busy - This instruction will cause
the computer to skip the next instruction when the
scanner register has located the interrupting module
(used only after 6353).

UDSC

6353

Start Address Scan - Initiates address scan and clears
accumulator. Bit 10 enables scan for immediate interrupts; bit 11 enables scan for deferred interrupts.

UDRA

6356

Read Address and Generic Type - The accumulator
is cleared. The contents of the address scanner register and the module type code (generic) of the module
in that address are loaded into the accumulator as a
12-bit word.

UDLS

6357

Load Previous Status and Read Change of State (COS)
Gates - This instruction loads the contents of the
accumulator (previous status of the interrupting module) into the COS register of the UDC, clears the accumulator, and reads the exclusive OR function of the
COS gates into the accumulator.

UDRS

6355

Read UDC Status - Read UDC status (immediate AC
bit 10, or deferred AC bit 11 ) .

2.2 ADDRESS FORMAT AND GENERIC CODE
The address/scanner register in the UDC serves a dual purpose. It serves as a buffer register when the UDC is directly addressed by the computer, and as a scanner register upon command to find the address of an interrupting
module. The address format and the bit values of the address in the accumulator and the scanner/register are
illustrated in Figure 2-2. The generic codes, used only to identify which type of module generated an interrupt,
are listed and defined in Table 2-2. These codes may be used in directing the program to jump to unique servicing
routines.

2.3 INTERRUPT STRUCTURE
The interrupt structure of the UDC can be enabled or disabled under program control. If enabled and a module
issues an interrupt, the interrupt structure can be interrogated under program control to determine whether the
module requires immediate service or whether services can be deferred. When interrogated, the UDC issues a

2-2

status word. The status word format is illustrated in Figure 2-3. Subject to the result of the interrbgation, the
automatic scan may be started to search selectively for the address of the deferred or the immediatre interrupt
module. In multiple interrupts, the lowest channel address is always found.

GENERIC CODE
(FROM INTERRUPTING
MODULE ONLY)

BIT NQ.

"T.,
MODULE

SYSTEM UNIT
( 1 OF 64)

x
UDC ADDRESS
SCANNER
REGISTER

I
'--~~~~~---~~~~~~--'-~~~---'

LSB

MSB

08-0677

Figure 2-2 Address Format

Table 2-2
UDC8 Generic Codes
Type of Module

Generic Code

0000
0001
0010
0011
0100
0101
0110
0111

No interrupts present
Fault condition
Contact interrupt W733
Contact interrupt W743
1/0 counter W734
1/0 counter W734
1/0 counter W734
1/0 counter W734

NOT USED

BIT 10

BIT 11

0
0
1
1

STATUS
BITS
TYPE OF

INTERRUPT

NO INTERRUPT
DEFERRED INTERRUPT
IMMEDIATE INTERRUPT
DEFERRED AND IMMEDIATE INTERRUPT

1
0

08-0678

Figure 2-3 Status and Control Word Format

2-3

The search is selective because the processor issues a control word when the scan is started to enable one or both
types of interrupt modules for the search. The format of the control word is identical to the status word. After
locating and servicing an interrupt, it must be determined that no further interrupts await servicing. This may be
done either by reading UDC status (6355), or by issuing another start scan (6353) instruction. A return of generic
code 0000 indicates no further interrupts are set.

2.4 DATA FORMAT
The data transferred between the computer and the UDC modules is an unstructured 12-bit word. The 12 bits
may be unrelated, as in the case of driving or sensing individual digital points, or may represent a 12-bit number
for presetting or reading a counter or a 2-bit channel code and a 10-bit number for driving a digital-to-analog converter. Bit 0 on the module corresponds to bit 0 in the accumulator.

2.5 APPLICATION PROGRAMS
Application programs for the UDC8 will vary from one application to the next. However, to provide some insight
into the use of the UDC IOT instructions, a flow chart presenting some operational characteristics of the UDC
relative to the IOTs is presented in Figure 2-4.

2B SAMPLEPROGRAMS
Program No. 1
This sample routine reads the contents of the switch register, then outputs the information to the selected address.

BEGIN,

200
201

202
203

204
205
206

207
210
211

7300
121 1

6363
7604
6367
2210
5205
5200

0000
0000

CLA1CLL
TAD ADDF<ESS
UDLA
LAS
UDLD
ISZ DELAY
JMP

.-1

JMP BEGIN
DELAY1 0000
ADDRESS10000

/LOAD ADDRESS TD UDC
/OUTPUT DATA TO SELECTED
/ADDRESS THEN
/DELAY F'OR TI ME SPEC ff I ED
/DEPOSIT ADDRESS IN THIS LOCATION

Program No. 2
This sample program selects the address, then reads the data into the AC register from the input module.

BEGIN

200
201

202
203

204
205
206
207
210

7300
1207
6363
6366
2210

CLA1CLL
TAD ADDRESS
UDLA

5204

JMP

5200
0000
0000

JMP BEGIN
ADDRESS10000
OELAY10000

UDRD

ISZ
• -1

2-4

/LOAD ADDRESS
/THEN READ DATA IN
/AND DELAY FOR TIME
/SPEC IF IED
/DEPOSIT ADDRESS IN TH IS LOCATION

INTERRUPT

TEST OTHER
DEVICES ON
THE INTERRUPT
BUS

LOAD PREVIOUS
STATUS a READ
CHANGE OF
STATE GATES
IOT 6357

SET SOFTWARE
INTERRUPT FLAG
~-----t~AND RETURN TO

MAIN PROGRAM
TAKE APPROPRIATE!
ACTION BASED
ON WHICH BIT
CHANG.ED STATE

UPDATE PREVIOU$
STATUS OF
INTERRUPTING
MODULE WITH
STORED CURRENT
STATUS

ENABLE UDC
INTERRUPT
FLAG
IOT 6364

EXIT

TAKE APPROPRIATE
ACTION BASED ON
GENERIC TYPE O F 1 - - - - - - - - - - - INTERRUPTING
MODULE

READ AND STORE
CURRENT STATUS
OF INTERRUPTING
MODULE
IOT 6366

A
08-06,'9

Figure 2-4 General Application Program, Flow Chart

2-5

Program No. 3
This sample program is a routine to handle interrupts coming from Contact Interrupt (W732) Modules. First the
interrupt circuitry is enabled, then, when an interrupt occurs, the scanner is activated to find the address of the
interrupting module. When the address is found, it and the generic code are read, the COS is determined, and the
data are read in. After each HALT check the data, then press CONTINUE.

BEGIN

200
201
202
203

7300
6364
6361
5203
6355
6353

204
205
206
207

5206

210

6356

6351

21 1

1220

212
213

6357
7402

214

6366

215

7402

216
217
220

3220
5200

0000

CLA,CLL
UDEI
UDSF
JMP

/ENABLE THE INTERRUPT CIRCUIT
/AND SKIP ON INTERRUPT FLAG
/JUMP BACK AND SENSE FLAG AGAIN
/READ UDC STATUS AND
/START UOC SCANNER
/SKIP ON FLAG NOT BUSY
/JUMP BACK AND SENSE FLAG AGAIN
/READ THE ADDRESS AND GENERIC
/CODE

• -1

UDRS
UDSC
UDSS
JMP • -1
UDRA
TAD PREVIOUS STATUS
UDLS
HLT
UDRO
HLT
DCA PREVIOUS STATUS
JMP BEGIN
PREVIOUS STATUS, 0000

2-6

/LOAD PREVIOUS STATUS THEN READ
/COS AND HALT TO CHECK THE DATA·
/DEPRESS CONTINUE
/READ THE DATA IN AND
/HALT TO CHECK IT• DEPRESS
/CONT lNUE

CH~PTER 3

PRINCIPLES OF OPERATION

3.1 GENERAL
The UDC8 is capable of handling several digital control functions. These functions are to sense data, diispatch data,
respond to interrupts, and determine change-of-state. Each type of functional module is uniquely associated with
one or more of these functions. Therefore, depending on the types of modules used at an installation, :some or all
of the UDC functions may be employed. Descriptions of the functional modules are presented in: Chapter 4.
Block and simplified diagrams are included in this chapter and the detailed block schematics are imcluded in Volume 11 of this manual; see drawings D-BS-0001-0-01 through D-BS-0001-0-10.

3.2 BLOCK DIAGRAM ANALYSIS
A detailed block diagram of the UDC8, showing the interface controller, one address selector, and one -functional
module, is shown in Figure 3-1. The device selector and IOT decoder of the interface controller coordinates all
activities within the UDC8, in response to the IOT instructions from the memory buffer of the co;mputer. IOT
instructions are available for enabling, disabling, and interrogating the interrupt logic, for data and address gating,
and for starting the address scanner.
All module address and data transfers are executed by IOTs and are dispatched to or from the acc.umulator, via the
data and address gating circuits in the interface controller. To sense data at an input module, the computer must
issue an IOT to transfer the module address from the accumulator to the address register. This uniquely enables
the address logic on one functional module. Another IOT must then be issued by the computer

to transfer the

data from the input module, through the data and address gating circuits, to the accumulator. Toi send data to an
output module, the module must first be addressed as described above. A second IOT is then issu'ed to transfer
the data from the accumulator through the data and address gating circuits to the output module .. Those modules
that are equipped with the interrupt facility are all monitored by the interrupt logic in the interfate controller,
which in turn supplies the interrupt request to the computer. Each module contains jumpers whi¢h can be initially set up to issue an immediate or a deferred interrupt.
The computer, having determined that the UDC8 has generated an interrupt, will respond to the ihterrupt request
by issuing an IOT to read the UDC status. This IOT causes the UDC status word to be transferred to the accumulator. The contents of the status word will then cause the computer to defer service or to start the address search.
The address search is initiated by loading the desired control word into the accumulator and issuing an IOT to
start the address scanner. The control word is transferred to the UDC when the IOT is issued, to ~eterrnine which
of the modules are to be included in the search. When the scanner reaches the address of the intetrupting module,
the scanner is stopped. The module generic code and change-of-state signals, along with the address from the
scanner, are applied to the data and address gating circuits in the interface controller. The generid code, and address are transferred to the accumulator via the data and address gating circuits by issuing an IOT.

3-1

OD01
BMB

INTERFACE CONTROLLER
_..]

CLRAC

DEVICE SEL
AND
IOT DECODER

IOT
BAC

....

IOT

DATA
AND ADDR
GATING

....

INT REQ

.... SKIP

•

]

UDC
STATUS

..t

INTERRUPT
LOGIC

• •

ADDR

SKIP

r[
_J

IMM

BI NARY
TO OCTAL
DECODER

DEFER
INT
DATA
I/O

GEN

cos

ADDR

PULSES

STOP

I/O MODULE
6
IMM

olc

IMM

DEFER

[

INT

DEFER
EN

't'"

INT

]

ADDRESS REGISTER
AND SCANNER

ADDR

ADDRESS
SELECTOR

IMM

1
1

DATA GATING
LOGIC

. iJ

DATA

l INTERFACE

DEFER

STOP
LOGIC

RESET
INT
r---1 t-------'
s
INT
._____ R

.__

J SIG COND

1 CARD

CUSTOMER
INTERFACE

12
08- 0680

Figure 3-1

UDC8 Detailed Block Diagram

3-2

Depending on the type and application of the functional 1/0 module, the computer program conti'.nues iin one
of three directions by programming different IOTs.

Data could be read from an input module.

Data could be loaded into an output module.

The bit that changed state could be determined.

3.3 DETAILED CIRCUIT ANALYSIS
3.3.1

General

A logic diagram of the UDC8, showing the master file (DD01) and one functional module, is presented in Figure
3-2. Sheet 1 illustrates the device selector and IOT decoder, and the address and data gating circuits; Sheet 2
illustrates the interrupt logic and the address scanning circuits.
3.3.2 Device Selector and IOT Decoder
The device selector and IOT decoder of the UDC8 responds to device select codes 358 and 36 8 . Five IOT instructions are coded with device code 35 8 and six IOT instructions are coded with device code 36 8 , pr~vidin!~ a total
of eleven instructions for controlling and communicating with the UDC8. The IOT instructions ar~ listed and
described in Table 2-1 of Chapter 2. Figure 3-3 correlates the IOT instruction format, decode logic, mnemonics,
IOT code, and execution time. For basic IOT decoding information, refer to DEC's Small Compu~er Handbook.
3.3.3 Addressing
A detailed block diagram of the address and scanning circuits is shown in Figure 3-4. Shown are Olfle output module, two input modules, and one interrupt module connected to one address decoder.
An address decoder (M851) is associated with each group of four functional 1/0 module slots; theriefore, there is
an address decoder associated with the DD01 and each DD02 in the system.
All functional modules in a UDC8 can be addressed sequentially or at random, depending on the u$er program.
In either case, the Load Address IOT is issued to clear the UDC address/scanner register and load it: with the address from the computer accumulator. Once the address appears in the address/scanner register, o~e of the 64
address decoders (maximum configuration) recognizes the address. The binary-to-octal decoders oh the M851
Module decode bits 4 through 9 of the module address and cause one X and one Y output to be as~erted. If the
decoded X and Y bits correspond to the location of X and Y jumpers on the G729 Module, that filie unit is enabled. At the same time, one of the four outputs from the 2-bit decoder in the address decoder (WD 00,. 01, 02
or 03) becomes decoded as a function of bits 10 and 11 of the module address to enable one of the four modules
that are inserted in that file unit. When addressed, data can be loaded into an output module or read out of an
input module, using the Load Data or Read Data IOT instructions.
The interrupt feature of the UDC8 permits the use of modules that are equipped to issue an immeqiate or a deferred interrupt signal. While the basic input and output modules serve only as direct data interfac~s, the interrupt modules provide the interface for inputs which require fast response time. An interrupt corn~and from a
functional module will be acknowledged either immediately or at some later time, depending on th'.e typ1e of interrupt that is issued and the nature of the user program. In either case, the address of an interrup~ing module
must be found in order to service the module. This is accomplished by employing the address scanrer register in
the interface controller as three binary counters that are capable of examining all 256 module addrbsses and
stopping when the address of an interrupting module is located. The scanner is started under prog~arn control

3-3

CUSTOMER
INTERFACE

MODULE

.-~~~~~~~~~~~~~~~~~~~~~~I~NTERFACEo-~~~~~~~~--.

FUNCTIONAL I/O MODULE
(SEE NOTE 1)

UDC
BUS

ADDRESS SELECTOR

INTERFACE CONTROLLER

NOTE:

1. Individual modules ore limited to input or output functions, ~u.t not bot~

START

B START

R1F

B RIF

Module circuits shown on this diagram do not reflect a spec1f1c module.
collectively, the circuits shown, illustrate maximum interface and
m.odule capability ..

C RIF

DELAY
1.0 ,..sEc

SKIP ON SCAN NOT BUSY

6356 READ GEN AND ADDR

START INT SCAN

READ UDC STATUS

::.C>------fS~Y~S~T~JN~T'f-----------;=-SY=S~T~l=NT't-_(SEESHEET2)

READ GEN AND AODR
LOAD PREV STATUS ( IOT 1)
AND
READ COS GATES (IOT 4)

6351

IOT 1

6353
6355
6356

IOT
DECODE
LOGIC

6357
IOT 4

6357

12
INPUT BUS
SIG
COND
BOARD

12
12

DATA I

8 DATA I

POWER
P CL

C DATA I

IOT 2

COS CL

6357

READ COS GATES

o--- + 3V

COS OPN
12

GEN
00-03

8 POP

SMB
09 -11

AC 00-11

12
POP

UDC STATUS
00 AND 01

IOT 2

B GEN
00-03

C GEN
00-03
175H 7 -17.5KHz

CLK 00

CLOCK
00

8-BIT
ADDRESS
REGISTER
llND
h----------------------+-t-----,,__-t--1-----"--'=='--=o~~q SCllNNER

X, Y llND
WD00·03

6363 LOAD ADDR
SCO 04-11

SEL EN

(SEE SHEET 2)

SEL EN

SK IP ON UDC FL AND CLR FL

C CLK X, Y AND WD

LOAD ADDR

SAC 00-11
SAC 00-11

12
EN UDC INT FL

CLK 01
DIS UDC INT FL

6357 LOAD PREV STATE
12

DATA 0

6363 LOAD DATA 0

FFOO-FF11

SIG
12
COND >---+---l!NTERFllCE
BOARD
CKT
POWE'<

READ DATA I

C L COS

OUTPUT BUS

LOAD DATA 0
PWR CLR

LOAD

B LOAD

OPT
SELEC

B P CL

DELAY
1.5 ;..SEC

DELAY
1.0 ,.SEC

6361
6363
6364
6365

IOT
DECODE
LOGIC

6366
6367

IDT 4

IOOULE

uoc

TERFACEi----------

BUS

ADDRESS SELECTOR

START

B START

RIF

B RIF

PDP-8
I/0 BUS

INTERFACE CONTROLLER

NOTE:

AC 00-11

1. Ind1v1dual modules are limited to input or output functions, but not both.
Module circuits shown on this diagram do no1 reflect a specific module:
collectively, the circuits shown, illustrate maximum interface and
module copabi!itya

SKIP ON SCAN NOT BUSY
C RIF

DELAY
1.0 !'SEC

6356 READ GEN AND ADDR
START INT SCAN

READ UDC STATUS

~Y~ST~I~N~Tl-----------+S~Y=ST~IN~T+-~(SEESHEET 2 )

READ GEN AND ADDR
LOAD PREV STATUS (IOT 1)
AND
READ COS GATES (IOT 4)

)ATA I

P CL

8 DATA I

C DATA I

6351

IOT 1

6353
6355
6356

IOT
DECODE
LOGIC

6357
6357

IOT 4

IOT 2
35

B P CL

OPT
SELECT .._-+--+--+----I
35

COS CL
6357
READ COS GATES

POP

B POP

GEN
)0-03

IOT 2
36

C GEN
00-03

BMB 09-11

6356 READ GEN AND ADDR

175H,-17.5 KHz
CLOCK
00

C ADDR 00-07

8-BIT
ADDRESS
SCO 04-11
REGISTER D - - - + - - - 0

6363 LOAD ADDR

OP
SELECT
36

SEL EN

h----------------------+-+-----;'-----!-+---~C"--"'AD~D~R:....::.0~0-~0~7____.Qsc!~~ER

Y AND
D00-0

C CLK X, Y AND WO
(SEE SHEET 2)
12
SAC 00-11

SKIP ON UDC FL AND CLR FL
SEL EN
LOAD ADDR
BAC 00-11

DIS UDC INT FL
C L COS

FFOO-FF11

12
EN UDC INT FL

DATA 01
PREY
STATE
FF

LK 01

ATA 0

BMB 03
BMB 04
BMB 05
BMB 06
BMB 07
BMB 08

UDC STATUS
00 AND 01
12

B GEN
00-03

LK 00

CLR AC

12
12

SMB
09-11

AC 00-11

12
COS OPN

BMB 03
BMB 04
BMB 05
BMB 06
BMB 07
BMB 08

READ DATA I
LOAD DATA 0

6361
B IOP 1
6363
6364
6365

IOT
DECODE
LOGIC

B IOP 2

6366
6367

IOT 4
B IOP 4

PWR CLR
.OAD

B LOAD

DELAY
1.5 i4SEC

BAC 00- 11

DELAY
1.0 !'SEC

Figure 3-2

UDC8 Logic Diagram (Sheet 1 of 2)

3-5

CUSTOMER
INTERFACE

MODULE
:;:NT ER FACE

FUNCTIONAL I/O MODULE

UDC
BUS

ADDRESS SELECTOR

+
B

START

RIF

B RTF

INTERFACE CONTROLLER

6356 READ GEN AND ADDR

DELAY

1.0 JLSEC
B LOAD

LOAD

SYST
INT

B SYST

CLK 00

DELAY

1.5 JLSEC

1.0 JLSEC

+3V

6367 LOAD DATA AND CLR AC

INT
FLAG

INT

CLOCK

I/O BUS

IMM INT

B
IMM INT

UDC STATUS 01

DEF INT

B
DEF INT

UDC STATUS 00

SIG
COND
BOARD
POWER

IMM
EN

6365 DISABLE

PULSE
SHAPER

B
IMM EN

lMM EN

DEF EN

B
DEF EN

CLK 01

B CLK 01

CLK 60

B CLK 60

6353 START INT SCAN

6363 LOAD ADDR

AC PWR 60Hz
SAC 0 4 -l 1 (SEE SHEET 1)

X, Y AND
WO 00-03

BIN
TO
OCTAL
CONVERTER

GEN

B GEN

00-03

POP

B POP

SKIP ON SCAN NOT BUSY 6351

RESET BUSY FLAG

P CL

B P CL

STOP
X, Y WO

B STOP
X,Y WO

C CLOCK X, Y AND WO

DELAY

2.0 JLSEC

ADJUSTABLE
CLOCK
75-1750KHz

DELAY
1.5 JLSEC

UDC
BUS

t
B

PDP-8

I!O BUS

INTERFACE CONTROLLER

START

B RIF

DELAY
t.O µ.SEC

B LOAD

DELAY
1.5 l'SEC

6356 READ GEN AND ADDR

DELAY
1 .0 µ.SEC

+3V

6367 LOAD DATA AND CLR AC

INTERRUPT
REQUEST (1)

PROGRAM INT
INT
FLAG

B SYST
INT

B
CLK 00

6364 ENABLE

B
IMM INT

UDC STATUS 01

IMM

EN
6365 DISABLE

UDC STATUS 00

DEF INT

PULSE
SHAPER

SKIP

SKIP (1)

B
IMM EN
6353 START INT SCAN

B
DEF EN

63 63 LOAD ADDR
8 CLK 01

B CLK 60

AC PWR 60Hz
SAC 04-11 lSEE SHEET 1l

BIN
TO
OCTAL
CONVERTER
B GEN
00-03

SKIP ON SCAN NOT BUSY 6351

B POP
RESET BUSY FLAG
B P CL

C CLOCK X, Y AND WO

B STOP
X.Y WD

DELAY

2.0 µ.SEC

ADJUSTABLE
CLOCK
175-1750KHz

DELAY
1.5 µ.SEC

Figure 3-2

UDC8 Logic Diagram (Sheet 2 of 2)

3-7

by issuing the Start Interrupt Scan IOT activating the scanner clock. Before issuing this IOT, bit 10 (immediate)
and/or bit 11 (deferred) must be set in the accumulator. These bits determine the type of interrupt being
scanned by setting the immediate and/or deferred enable flip-flops. The output of these flip-flops is utilized to
enable the appropriate interrupt modules. Each counter (X,Y, and WD) is sequentially clocked until the associated
stop commands are issued by the stop logic on an interrupting module. Each interrupt module has its own stop
logic, which is enabled when the module has issued an interrupt. If more than one interrupt is present, the module
having the lowest address will be located. Therefore, those modules having highest priority should be assigned the
lowest module addresses.
First, the X register, with a maximum count of 7, localizes the interrupting module to eight file urnits having the
same X address. The counter stops when it reaches the lowest X address of an interrupting module. Then the Y
counter, which also has a maximum count of 7, further localizes the module to the one system file unit 1containing
the interrupting module. Finally, the word counter locates which of the four module slots in that file unit contains
the interrupting module. The maximum number of counts required to find an interrupting module in a maximum
system configuration is 17 (7 + 7 + 3). Each count requires approximately 1 µs.

BMB

IOT
(6XXX)

369

0
1

UDSS

UDSC

DEV I CE CODE

!OT
2 1

!OP
2 4

IOP

( IOP1 l
0

UDLA

UDE!

!OT EXECUTION TIME
EVENT!

IOT

0
UDSF

2
3

DEVICE CODE

359

EVENT 2
(IOP2)

EVENT 3
(IOP3)

UDRS

UDO!

UDRA

UDRD

UDLS

UDLD

!OT
CLR AC
IOT

CLR AC
!OT

UOOI

UDRS

LOAD PREV
STATE
LOAD DATA 0

CLR AC

!OT

CLR AC

READ COS

08-0682

Figure 3-3

IOT Decoder and Truth Table

3-9

INTERFACE CONTROLLER

BAC 11 _, f--------1

SEL
EN

LOAD
ADDR

ADDRESS SELECTOR
ADDR /SCAN ER
REGISTER

B ADDR 06

...

BAC 08 ---i f--1

BAC 07

__, ~

...

AND
GATES

B ADDR 03

BAC 05

__, ~

__, f--1

B ADDR 04

B ADDR 05

f---o6o--4

B ADDR 00

BAC 04 ---i r--1

START
INT SCAN

...

CLOCK
LOGIC

BUSY FLACKJ CLOCK}

MODULE 2 (INPUT)

J
J

t---o 0 0-

f--o 1 o----4
t---o 2 D--1
BINARY

B ADDR 01

o---1

f--o 3
TO
OCTAL f--o 4D--4
DECODER
t---o 5 D--1

t---o 7

MODULE 3 (INPUT)

......

t---o 0 0---,
t---o 1 D--4
t---o 2 D--4
BINARY
t---o 3 c:r-1
TO
OCTAL t---o 4 D--4
DECODER
t---o 5 D--4

WO 01
WDOO

AND
GATES

CLK y
BAC 06

]

WO 02

CLK WD
BAC 09 ---i f--------1

LOAD DATA

WO 03

B ADDR 07

.....

ADDRESS
DECODER

2-BIT
DECODER

WORD
REGISTER
BAC10 ---i f--------1

MODULE 4 (OUTPUT)

......

t---o 6 o---4
t---o 7 o----i

~~KX
~ -l
1

MODULE 1 (INTERRUPT)

]

..
--

IMM INT MODULES: CONNECT JUMPERS A AND B
DEF INT MODULES: CONNECT JUMPERS C AND D

SYST INT
,IMM INT

DEF INT
IMM
INT EN
DEF
INT EN

r--'j'

•c

)..

_,...

·"I

10
),

INT

......__

STOP LOGIC
00-STOPX

~p
]

]

····--·

j
J
08- 0683

Figure 3-4 Address Scanner Logic

3-11

After the address of an interrupting module is found by the scanner, the busy flag is reset to notify the computer
that the address and the module generic code can now be gated to the computer by issuing the Re~d Address and
Generic Type IOT.
3.3.4 Interrupt and Skip Logic
Interrupt requests and skip commands produced in the UDC8 are used by the computer to jump betwee!n main
programs and subroutines for finding and servicing the interrupt. The interrupt logic can be enabled and disabled
by issuing the Enable UDC Interrupt Flag and Disable UDC Interrupt Flag IOT instructions. The proper management of these instructions is the responsibility of the programmer. The interrupt logic may be disabled while the
UDC is being serviced; thus, a subsequent interrupt request does not interfere with the servicing subroutine. After
the UDC is serviced, the interrupt logic should again be enabled. All interrupt modules are connecited to the interrupt logic. In addition, each module will also send an immediate or a deferred interrupt command to lo1gic gating
circuits in the interface controller. A jumper wire must be installed in the module to have it issue one and only
one of the two signals. After an interrupt request is issued by the UDC, the computer, under program control,
jumps into a subroutine to search for the device issuing the request. If a UDC module issued an interrupt, a skip
command is sent to the computer when the Skip on UDC Flag and Clear Flag IOT instruction is is$ued, thus allowing the computer to jump into a servicing routine to determine what type of interrupt occurred. Thiis skip
command also clears the interrupt flag. If the Read UDC Status IOT reveals that an immediate interrupt occurred,
the computer will jump into another routine to service the interrupt. A deferred interrupt would allow the computer either to jump to a routine to service the interrupt, or to a routine designed to store the deferred interrupt
and continue the main program. The deferred interrupt can then be serviced when computer time is not critical.
Servicing a UDC interrupt request involves finding the address and generic type of the interrupting module, determining which data inputs have changed state in the direction specified by the jumpers on the module,. and
gating data out of or into the module. An immediate interrupt request is serviced by depositing a control word
into the accumulator and issuing the Start Interrupt Scan IOT instruction. The control word for servicing the
immediate interrupt request has bit position 10 set and bit position 11 reset to enable the stop loglc of only those
modules that are set up to issue an immediate interrupt. When the Start Interrupt Scan IOT instru:ction is issued,
the control word appearing in the accumulator will be gated into the UDC by the select enable signal, and will
cause the IMM EN and BUSY flip-flops to be set. Setting the IMM EN flip-flop enables the stop scan lo~1ic of all
the modules that could issue an immediate interrupt. The modules that are set up to issue a deferred interrupt are
enabled in the same way, except that a different control word (bit position 10 is reset and bit position 11 is set)
is deposited in the accumulator. The next IOT instruction in the servicing routine will be the Skip on Sc:an Not
Busy instruction, which enables logic in the UDC to generate a skip command when the busy flag is reset upon
termination of the address scan. The module address and generic code are gated out of the UDC to the accumulator by issuing the Read Address and Generic Type IOT instruction when the scan terminates. This IOT also resets the interrupt flip-flop on the addressed module. The generic code and address are used in the computer to
locate in memory the previous status of the interrupting word, which is used in determining the change-of-state information.
3.3.5 Data Gating
The data-gating logic is shown on Sheet 1 of Figure 3-2. Data is gated into or out of a functional moduli9 by depositing the module address into the accumulator and issuing the Load Address IOT instruction, and then reading
or loading the data by issuing the corresponding IOT instruction. To load data into an output module, the data
to be loaded must be deposited in the accumulator before issuing the IOT. The Read Data IOT instruction will
clear the accumulator before loading it with the input data. The Load Data IOT will clear the accumulator after
transferring the data to the functional module.

3-13

3.3.6 Determining Change-of-State (COS)
The hardware gating network for determining the direction of change (open or close) of inputs to contact
interrupt functional modules is illustrated on Figure 3-5. The gating network consists of two circuits used to determine the direction of an input change (1 to 0 defined as an opening and 0 to 1 defined as a closure) by comparing the previous status of the addressed module with its current status. Referring to Figure 3-5, gates A and D
are used to test for an input closure, and gates Band Care used to test for an input opening. The jumper installed
on the module determines whether a closure or an opening, or both, is of interest to the user. It does this by
means of enabling either one or both of the circuits. Issuing the Load Previous Status And Read COS Gates IOT
(6357) will transfer the previous status of the addressed module from the accumulator into the UDC controller,
clear the accumulator and load the accumulator with a 1 corresponding to each bit that has changed in the direction of interest. Only one IOT instruction, Load Previous Status And Read COS Gates, is required to execute
this function.
Jumpers A and B (Figure 3-5) in the interrupt modules must be connected as required by the user upon system
installation (refer to Chapter 4). A truth table illustrating the output of the change-of-state gates with various
combinations of previous status, current data, and jumpers is presented in Table 3-1.
3.3.7 Initializing
On power up, an initializing signal is generated on a dedicated bus line which is applied to the reset input of every
flip-flop on every 1/0 module. The signal is the result of ORing the output of an integrating-one-shot (M307) set
for 75 ms and B INITIALIZE from the PDP-8/1 or 8/L. The resulting signal starts approximately 5 ms after power
is turned on and lasts for approximately 250 ms.
Table 3-1
COS Definition Table
DATAl Changed
From Previous State
Unchanged

Opened
(1 to 0)

Closed
(0 to 1)

Unchanged

Pulse Open

Pulse Close

COS Out

State

(Jumper A)

(Jumper B)

(Exclusive OR)

0
0
0
0

0
0
0

0
1
1

0
0
0
0

1
1
1
1

0
0
0

0
1
1

1
0
1

1
1
1
1

0
0
0
0

0
0
1

0
1
0
1

0
1

1
1
1
1

0
0
1

0
1
0
1

0
0
0

DATAI

1
1
1

3-14

1
1

0
1

MODULE

ADDRESS SELECTOR
x
y

ADDRESS
DECODER

INTERFACE CONTROLLER
B ADDR 00-07

ADDRESS
SCANNER/REGISTER

P CL

P OP

CLOCK

START SCAN

DATA I

MODULE

ADDRESS SELECTOR
x

DATA I

ADDRESS
DECODER

WD1
WD2

P CL
B PCL

READ
COS GATES

POP

00-11

8 POP

bQSSTATE

MODULE

---+---

BAC

DATA I

00-11

0
8 DATA I 00-11

PREY
STATE
FF

DATA I
DATA I

(12)

CLOSED

12
08-0684

Figure 3-5 COS Logic

3-15

CHAPTER 4
INSTALLATION

This chapter contains necessary installation information for UDC Systems. The chapter covers the following
subjects:
•
•
•
•
•
•
•

Site Preparation
Power Requirements, AC, Fusing, Receptacles
Installation Checkout, DEC Field Service
UDC System Configuration, Addressing, 1/0 Module Placement
Functional 1/0 Module Setup
Signal Conditioning (including Arc Suppression)
Field Wiring

4.1 SITE PREPARATION
Adequate site planning and preparation can simplify the installation process and result in an efficient, reliable
UDC system installation. The customer's planning staff should prepare a list of the actual components to be used
in the installation. This list should include such items as tape-storage cabinets, work tables and desks, and any
other items pertinent to the customer's computer applications. In selecting the site for the installation, consideration should be given not only to the physical dimensions of the units comprising the system, but also to service
and operating space requirements and future expansion. The usefulness of a given area depends on many factors,
such as length-width ratio, location of columns, and position of doors, windows, and electrical outlets, so that a
truly usable area need be distinguished from that which only appears to be usable. Scale drawings of the possible
site locations should be prepared and consideration given to factors such as size of entrances into site area (they
should be large enough to allow entry of the largest unit of the system), proximity to large inductive machines,
circuit availability of adjacent working area (enough room should be allowed to accommodate the equipment, required personnel, storage facilities, and service area).
While operating, the system can produce anywhere from 5,000 to 50,000 Btu/hr {depending on the size) which
mu-st be drs-s-ipatec.L Wh-netn-dlviaual units of ffie system are -coC>lecfby filowers and ffiEf equlpmentis designed to
operate over a wide temperature range, it is recommended that air-conditioning be installed to ensure reliable
long-term operation. An air-conditioned area has the additional advantage of having a positive pressure with
respect to the outside area, which materially aids in maintaining a dust and dirt free environment. The atmosphere in the immediate vicinity of the equipment should be maintained as free from offensive dust and corrosive
air as possible.
An average illumination of about 40 foot-candles measured 30 inches above the floor should be available in the
area. Direct sunlight should be avoided since lower levels of illumination are needed to observe the various indicator lights on the control panels and operator consoles.

4-1

4.1.1 Space Requirements
Space requirements are determined by the specific system configuration to be installed, and, when applicable,
provision for future expansion. To determine the exact area required for a specific configuration, a machine-room
floor plan layout is helpful. When applicable, space is provided in the machine room for storage of tape reels,
printer forms, card files, system documentation, etc. The integration of the work area with the storage area depends on the work-flow requirement between areas.
In large installations where test equipment is maintained, DEC recommends that the test equipment storage area
be within or adjacent to the machine room. Figure 4-1 shows the space requirements for maximum and minimum
UDC8 configurations. This does not include the computer cabinet or other peripheral devices.

4; 1.Z-- Envtronmenta1 Conditions
An ideal computer room environment has an air distribution system which provides cool, well-filtered, humidified
air. The room air pressure should be kept higher than the pressure of adjacent areas to prevent dust infiltration.
4.1.2.1 Humidity and Temperature -The UDC is designed to operate in a temperature range of from 0°C to
50°C, at relative humidity to 95 percent with no condensation. However, typical system configurations using
input/output devices such as magnetic tape units, card readers, etc., require an operational temperature range between 18°C and 27.5°C up to 55 percent relative humidity. Nominal operating conditions for a typical system
are a temperature of 21°C with a noncondensation relative humidity of 45 percent.
4.1.2.2 Cleanliness - The following precautions are recommended by DEC to ensure optimum UDC system
operation:

Do not use steel wool for cleaning floors in the computer room.

To prevent air flow interference, do not place material on top of the cabinets.

Use a nonconductor type nozzle when vacuuming to minimize the possibility of an electrical accident.

Avoid spilling liquids (coffee, soda, etc.) on the equipment and operating controls (e.g., console switches,
Teletype® keys, and controls).

4.1.2.3 Static Electricity - Static electricity can be an annoyance to operating personnel and can (in extreme
cases) affect the operational characteristics of the UDC System and related peripheral equipments. If carpeting
is installed on the installation room floor, it should be of a type designed to minimize the effects of static electricity.
Flooring consisting of metal panels, or flooring with metal edges, should be adequately grounded.
4.2 POWER REQUIREMENTS
The following information pertains specifically to UDC8 subsystems. For detailed information regarding PDP-8
power requirements, including options, refer to the PDP-8/E & PDP-8/M Small Computer Handbook.
UDC Systems are sold in a variety of H964 cabinet configurations. Each cabinet contains a power control (849A)
and a power supply (H740D) for each file implemented. The H740D Power Supply is capable of supplying +5V
@ 20A.

The H738A Power Supply is optional and is available for implementing the A633 DACs.

®reletype is a registered trademark of Teletype Corporation.

4-2

RECOMMENDED
OVERHEAD
CLEARANCE

18 in.

APPROX 168 in.

ADDITIONAL 4in. FOR
TERMINATION CABINET

-- ' '

l-21 in.-1

-- '

...... .....

' \

SCREW
TERMINAL
CABINET

SIDE VIEW

\.
.......

.......

- -....
\

-- ' '
......

' ' ....... _ ' ..... ......

LOGIC
CABINET

......

66*in.

30in.

+
'132 '"·
7 .

- "' ' - -

\
\

SCREW
TERMINAL
CABINET
1

.......

...... .....

~
\

.......

' \

LOGIC
CABINET

.......

SCREW
TERMINAL
CABINET

- "" -- "'

' '

.......

' '\

LOGIC
CABINET

\
\

SCREW
TERMINAL
CABINET

.....

-- ....

.....

LOGIC
CABINET

......

'\ \

\
70.93 in.

-- ' --

.... .....

......

' .....

.......

PLAIN VIEW
08-0685

Figure 4-1

Space Requirements for UDC8

4.2.1

Logic Power

The internal control and logic power requirements for each logic cabinet are directly dependent on the number
and type of functional modules installed in that cabinet. One H740D Power Supply is provided for each file
implemented in a cabinet. As previously described, the H740D Power Supply has a maximum current capacity
of 20A. The power Requirements for the functional part of the UDC8 are shown in Table 4-1. The power consumption for the total number of modules implemented in the files should not exceed the capacity of the H740D
Power Supply.
Table 4-1
UDCS Power Requirements
Item

Consumption (Amps)

Master File
Expander File
DD02
W730
W732
W740
W742
M684
M686
M802
M804
M806
W734
W400
W402
W403

3.0
0.3
0.3
0.100
0.450
0.350
0.450
* 0.250
* 0.400
* 0.250
* 0.225
* 0.400
1.0
none
none
none

~~;;}

Power supplied by
one H738A per
four A633 Modules

A234
A235
A236

*This value assumes that 6 of the 12 circuits on the module are energized. The
power requirement is directly proportional to the number of circuits energized
at one time.

4.2.2 Primary Power Requirements
Each logic cabinet requires a 30/15A ( 115/230V) primary power source. Both local and remote control is provided. Local control provides the means for energizing each logic cabinet independently. Remote control is
chained from one cabinet to the other; therefore, the entire system can be energized by operating the power switch
on the computer console. Each cabinet contains all the control circuits and power supplies to establish the type of
control desired, and to convert the primary ac power to the de voltages required by the logic cabinet. Protection
for overvoltage and overcurrent is included in the power supplies. A simplified block diagram illustrating the distribution of the power within a cabinet is shown in Figure 4-2. For detailed information concerning distribution
and control of ac and de power, refer to engineering drawings provided in Volume 11 of this manual.

4-4

PRIMARY AC POWER
REMOTE CONTROL

849A
POWER
CONTROL

H740D
POWER
SUPPLY

+5V

FILE
N0.1

H740D
POWER
SUPPLY

+5V

FILE
N0.2

H740D
POWER
SUPPLY

+5V

FILE
N0.3

11-0973

Figure 4-2

UDC8 Logic Cabinet Power Distribution Block Diagram

4.2.3 Primary Power Receptacles
The installation site primary power line must terminate in Hubbell wall receptacles (or equivalent) to be~ compatible with the UDC8 System power line connector. The Hubbell wall receptacle part numbers are shown in
Table 4-2.
Table 4-2
Hubbell Wall Receptacle Part Numbers
Line Voltage
115 Vac, 60 Hz, 30A

Hubbell Receptacle Part Numbers
Receptacle 3330-G (3330 may be used)
Cap

230 Vac, 50 Hz, 20A

3331-G (3331 may be used)

Receptacle 7310-G (7310 may be used)
Cap

3321-G (3321 may be used)

4.3 INSTALLATION CHECKOUT
4.3. 1 Unpacking and Visual Inspection
After unpacking the equipment a visual inspection should be made to ensure against loose module~ and connections.
An inventory should be performed at this time to ensure all equipment and supporting documentation iis present.
(Refer to Accessory List.)
4.3.2 1/0 Bus Connections
Three BC08 Cables are required to connect the PDP-8 1/0 bus to the UDC8 from the computer or some other
peripheral device. These cables are to be inserted in slots A01, A02, and A03 of the DD01 Interface Controller
as follows:
BAC bus:
BMB bus:
AC bus:

slot A01
slot A02
slot A03

Slots 801, 802, and 803 may require M906 Termination Modules if the UDC8 is the last peripherial on the 1/0
bus. If not, they will contain another set of BC08 Cables to extend the 1/0 bus to the next perip~eral device.

4-5

4.3.3 UDC Bus and Connections
The UDC bus consists of 60 lines, 31 driven by open collector-drivers at the DD01 Master Control and 29 driven
by open collectors on 1/0 modules. Bus receivers on M510 Modules in the DD01 and on the M851 in each DD02
allow the full complement of functional modules to share the bus lines. Special double connector modules (M935),
a set of flat Mylar® cables, and a set of power cables are required to extend the UDC bus and power throughout
the UDC. The UDC bus is chained from one DD02 to another within a file with the M935 Bus Connectors. This
module connects the bus lines of slot AB 14 in the DD01 to AB01 of the first DD02 File Unit; slot AB04 is connected by an M935 to AB01 of the next DD02. One more DD02 may be thus connected in the first file. Further
extension of the UDC bus is accomplished by connecting from the AB04 of the last DD02 in the file to AB01 of
the first DD02 in the next file, using a 5-ft flat Mylar (BC41A-5) cable. A 10-ft flat Mylar (BC41A-'10) is used to
extend the bus between DD02s in different cabinets. Two terminating modules (M942) are also required to construct the UDC bus. These modules must be inserted in slot AB11 of the DD01 and in slot AB04 of the last DD02
on the bus. If no DD02 File Units are used, the second M942 Module is used in slot AB 14 of the DD01.

4.3.4 External Cabling
The BC40C Screw Terminal Assembly is the point at which customer control circuits connect to the UDC8 signalconditioning modules. Each circuit is completed through a twisted pair of No. 26 AWG stranded color-coded wire
connected to a pair of screw terminals. The terminals will accommodate No. 14 AWG wire, and are arranged in
two strips of 17 contacts, each supported in line by a common steel angle support. The steel supports are mounted,
one above the other, 36 in front and 36 at the rear of the dedicated cabinet. In the single file, single-cabinet con,
figuration, the screw terminals are mounted 12 front, 12 rear. The field wiring may enter only from the top or
bottom of the cabinet. Field wiring should be twisted pairs per control point. Maximum current per point is 2A,
limited by relay contact ratings; large wire is thus unnecessary. The twisted-pair field wiring is used to avoid stray
pickups and to minimize the radiation of switching transients by confining their fields largely to the space between the two wires of the twisted pair.
Horizontal bars are located at the top and bottom of the screw terminal cabinet, to be used for strain relief on
incoming cables. In addition, strain-relief members are located at both ends of the screw terminal brackets. The
input cables should be routed over these members to provide for strain relief as they branch out to individual screw
terminals. As the cables enter the screw terminal cabinet, they should be routed over the strain-relief bar and up/
down both sides of the cabinet.

4.3.5 Electrical AC Power Cabling
The 849A Power Controller supplies ac power to the UDC. The 849A Power Controller can operate in two modes,
remote and local. In the remote mode, an ac power cable is required between the central-processor controlled ac
power outlet and the 849A Control Socket. This provides ac power to control the circuit breaker when the central processor is turned on and off. In the local mode, the circuit breaker is controlled manually at the front of
the 849A.
The ac power for the UDC is normally 115 Vac, 60 Hz, single-phase, (220 ac, 50 Hz, single-phase) three wire.
Power for the UDC should be supplied from the same source as is the central processor.
Before connecting ac power to the UDC, measurements should be made at the Hubbell wall receptacle between
ac hot and ground, ac neutral and ground, and ac hot and ac neutral to ensure that proper power is available.

®Mylar is a registered trademark of E. I. DuPont de Nemours and Company.

4-6

After determining proper power is available, ensure that the 849A LOCAL/REMOTE switch is in LOCAL and
the circuit breaker is off. Plug the 849A ac Power Cable in and measure the voltage between the cabinet and ac
power ground; this measurement should be OV. Energize the 849A by switching the circuit breaker oni and again
make the measurement from cabinet to ground; again, OV should be read.
If the system has more than one UDC logic bay, each 849A Power Controller (one per logic bay) will have to be
connected and checked individually.
NOTE
If the checks of power outlined above show any discrepancies, these problems must be corrected before
proceeding. A SHOCK HAZARD may exist.
4.3.6 DC Voltage Checks
Two types of power supplies can be used in the UDC system. The H7400 Power Supply is used to supply file
logic power. One H7400 Power Supply is provided for each file implemented. The H738A Power Supply is used
in UDCs containing D to A options (A633) only.
Check the de output voltage of each H740D Power Supply by measuring the tabs on the right-hand most G729
(+tab on top, gnd tab on the bottom) in each UDC file. This measurement ensures that +5 Vdc is supplied to all
logic and 1/0 modules in the UDC.
Check the de voltages supplied by the H738A to the DAC option for +18, -18, and +5 volts at the screw terminals.
The screw terminals that are connected to DAC options are the only terminals that are prewired on the screw side.
4.3.7 UDC Functional Checkout
Using the UDC Acceptance Procedure (A-SP-UDC8-0-4) supplied with the documentation, the UDC Exerciser
Program (MAI NDEC-08-08YB-D), and the UDC Field Test Box, proceed to check the functional 1/0 modules.
The UDC Acceptance Procedure details specific steps and procedures used in checking the various functional 1/0
modules utilizing the test box and the exerciser program.
4.3.8 System Pre-Use Requirements
After the system has been connected and checked out as described in Paragraphs 4.3.1 through 4.3. 7, tlhere remain steps the customer must perform before putting the UDC into operation:

Signal conditioning (arc suppression) for output functional 1/0 modules. Refer to Paragraph 4.6.

Field cable connections to the UDC screw terminals.

Determination of any special addressing of functional 1/0 modules that require changing the G729
Address Selection Modules.

4.3.9 UDC Add On Expansion
The UDC can be expanded in four ways:

Addition of more functional 1/0 modules.

Addition of 0002 system units.
(continued on next page)

4-7

Addition of UDC8-X system files.

Addition of other UDC bays.

The latter presumes inclusion of the preceding items.
The additions, as they occur, require the following considerations.

The addition of 1/0 functional modules requires an available 1/0 slot, adequate power from the H740D
Power Supply, and mounting of the screw terminals. After the added modules are installed, functional
checkout is accomplished using items described in Paragraph 4.3.7 for those added modules.

The addition of other 0002 system units requires adequate mounting space in the BF01 file, power
cabling, and the UDC bus continuation with an M935 from the preceding 0002. Before adding 1/0
modules, a check of (a) above should be made.

The addition of other UDC8-X system files requires adequate space in the cabinet, power cabling, and
continuation of UDC bus via a BC41 A cable.

The addition of other UDC bays should be treated as described in Paragraphs 4.3.1 through 4.3. 7.

4.4 UDC SYSTEM CONFIGURATION
Configuration of UDC Systems is a user task and each system can be set up for optimum performance. In configuring a system, the user should consider his requirements in terms of functional areas. The UDC is basically
a digital multiplexer with the added availability of identifying user interrupts. Thus, functionally the UDC can
perform the following:

4.4.1

Bi-Level Interrupt Identification
1. Immediate
2.
Deferred

Status or State of Operation

Control

FURNACE

FUEL TANK

,___ _ _ _ _ FLOAT
FUEL LINE

ON/OFF

Bi-Level Interrupt Identification

The UDC control logic contains a hardware scanning feature to search for the address of any inter-

'---.,,..--1

IM INT

rupting module. Upon recognition of a UDC in-

CONTROL
OUTPUT

DEF INT

UDCB

terrupt by the skip chain program, the hardware
scanner may be started under program control to
POPS PROCESSOR

sequentially search the UDC addresscomplement
to find the interrupting module. Table 4-3 defines

08-0753

the priorities of all module addresses. The bi-level
UDC interrupt structure is useful in that the system

Figure 4-3 Interrupt Class Example

programmer can choose two classes of interrupts,
those requiring immediate program action and a deferred mode, where program action can be performed at a
later time.
The simple example of a temperature monitoring process illustrated in Figure 4-3 shows this concept more readily.

4-8

Table 4-3
Scanner Counting Characteristics
Address
Jumpers

0
0
0
0
0
0
0
0

0
1
2
3
4
5
6
7

1
1
1
1
1
1
1
1

0
1
2
3
4
5
6
7

2
2
2
2
2
2
2
2

0
1
2
3
4
5
6
7

3
3
3
3
3
3
3

0
1
2
3
4
5
6
7

4
4
4
4
4
4
4
4

0
1
2
3
4
5
6
7

5
5
5
5
5
5
5
5

0
1
2
3
4

6
6
6
6
6
6
6
6

0
1
2
3
4
5
6
7

7
7
7
7
7
7
7

1
0

1
4

3
2
5
8

33
36

3
6
9
12

34
37
40

65
68

4
7
10
13
16

35
38
41
44

66
69
72

97
100

Address Scanner Count (1 JJsec per count)
9
10
11
12
8
13

MODUL!E NUMBERS

11
14
17
20

39
42
45
48

67
70
73
76

98
101
104

15
18

21
24

19
22
25
28

23
26
29

27
30

-MODUL.E NUMBERS

43
46
49
52

71
74
77
80

99
102
105
108

47
50
53
56

51
54
57
60

55
58
61

59
62

63
MODULI:: NUMBERS

75
78
81
84

103
106
109
112

79
82
85
88

83
86
89
92

87
90
93

91
94

95
MODUL!E NUMBERS

107
110
113
116

111
114
117
120

115
118
121
124

119
122
125

123
126

127
------i

128

129
132

160

130
133
136

161
164

131
134
137
140

162
165
168

135
138
141
144

163
166
169
172

MODULE NUMBERS

139
142
145
148

167
170
173
176

143
146
149
152

192

193
196

224

194
197
200

225
228

4-9

195
198
201
204

226
229
232

147
150
153
156

151
154
157

155
158

___,

159

MODULE NUMIBERS

171
174
177
180

6
7

0
1
2
3
4
5
6

199
202
205
208

227
230
233
236

175
178
181
184

179
182
185
188

183
186
189

187
190

191
MODUL(: NUMBERS

203
206
209
212

231
234
237
240

207
210
213
216

211
214
217
220

215
218
221

219
222

223

MODULE NUMBERS

235
238
241
244

239
242
245
248

243
246
249

247
250

251

In this example, the furnace has a control unit that will provide ignition or shut down, a temperature sensing
element that will provide an interrupt at a preset temperature, and a fuel supply that contains a float switch to
indicate low fuel. If furnace temperature is too high or too low, the UDC should be interrupted immediately
and the furnace should be turned off or on depending on the interrupt received. However1 the float switch is only an indicator of low fuel supply; this interrupt can be recognized at a later time and thus is placed on the deferred line.
4.4.1.1

Module Interrupt Selection - Each interrupting UDC module can be placed in either immediate or de-

ferred mode. This is accomplished by the proper selection of jumpers on the module and will be covered in
Paragraph 4.5, Functional 1/0 Modules.
4.4.2 System Interrupt Response
The system interrupt response is defined as:
MODULE OPERATE TIME+ SCAN TIME+ PDP-8 INTERRUPT SERVICE TIME+ PROGRAM TIME.

Module Operate Time
W732 Relay Input Contact Interrupt - 2 ms
W742 Solid State Input Contact Interrupt - 2.5 ms (50 µs with high-speed option)
W734 1/0 Counter - Int on Overflow

Scan Time
Table 4-3 gives the search time for each UDC address.

PDP-8 Interrupt Service Time
This time depends entirely on the system configuration and the status of the system at the time of
the UDC interrupt. For a complete discussion of PDP-8 interrupt facilities, refer to the 1972 Small
Computer Handbook, Chapter 9, page 9-56.

Program Time
Program time can be computed from the service routine being used and information regarding processor cycle time which is available in the 1972 Small Computer Handbook.
It should be noted that although the operate time of the input modules is quite long, interrupts can be
waiting for service due to the receipt of two or more at the same time. Thus, the need for fast search
time and processor service time is evident.

4.4 . 3 Generic Codes
Each UDC interrupting module contains a 4-bit code that is present at the time the UDC module address is read.
This code allows the user to determine what type module has caused the interrupt. The codes for each module
are listed below:
Module

Generic Code

W732
W742

0010

W734

~~~~}

{

0101
0110
0111

4-10

Hardwired on Module
Hardwired on Module
(Selectable on Module
by jumper)

4.4.4 Status and Control
The remaining function of a UDC System is to obtain process status information and to provide control. These
function~ are provided by the remaining non-interrupting functional 1/0 modules. Placement of t~ese modules

is not critical and their location can be specified by convenience. However, it is advisable to segre~ate highvoltage switching elements such as mercury-wetted relay outputs from DIA converter outputs (A6i33) if at all
possible.
4.4.5 User Identification - Functional 1/0 Modules

cab_ File __

After the system is configured and functional 1/0 module placement is complete, the user is encouraged to utilize the 1/0 module cross reference provided. The cross-reference scheme includes a Functional Module 1/0 Chart (Figure 4-4) and a Func-

WORD
ADDR

G~~i ~

SCREW
TERMINAL

x Y 0-3

~UMPER5

c:;1~ 0

=1=-~[A=l====l==l==l===l==~=l==of=·;, ~~=•-t---==~==t===i
51

T1F

T2F

---+-- ----ll-----1

- I-

the back door of each UDC electronics cabinet and contains

T3F

T4F

1-----f----'I---+---+---+---+-----+--+----·•--··. +------+---

The 1/0 chart also includes a column entitled "Page No.", this

TSF

column is used to reference the module listed in the 1/0 chart

T6F

with detailed module descriptions contained on the Module 1/0

PAGE
NO.

l==C

tional Module 1/0 Page (Figure 4-5). The 1/0 chart is found on
space for information to identify each 1/0 module in the cabinet.

: MODULE
TYPE

t-·

t----+-----1-t--T----t---+- --+--- r---··
58
T7F
59

Page. Module 1/0 Pages are provided with each UDC system.

·--t-··

---- - - -

T8F
~===!===

t----+-----t-~--t--+--+-5-11--t-T9_F+-_J,~-+------t---512

TlOF

513

T11 F

514

T12F

4.4.6 Address Assignments

l---+----+---+----<f---1----1

After a system is installed, addresses may be reassigned to the

l===l====ll==l==ot="F==f.--~ccFC'= t=~··

516

functional modules. This is accomplished by changing two jump-

517

ers (one in the X field and another in the Y field) on the address
jumper modules (G729) of the address selectors (Figure 4-6).
These jumpers define the first two digits of the addresses of the

t------+---1

T2R

l---+---l----+----<f---1----+- ---- -·-

2
!---+----+---+--- t--

r- =.cc=c=j===

T1R

518

T3R

519

T4R

t-----

·I

---- --- t------ --

l===!===t==1==1==1==F= =t- -=~ =

-- ·--I

,,__ I- --~=-=I

four module slots in the file unit.

-·
523

+---

·-j

T7R
·--j

These two digits are straight octal, and the pair may be considered

524

T8R

to be the address of the file unit. The 8 x 8 matrix and accom-

526

panying diagram presented in Figure 4-7 illustrates this scheme.

527

T9R
----- t- .
T10R
:
T11R

528

The G729 modules are piggy-back modules that mount on the

529

T12R

---

- · - · - -t - - - - j

-----

-----1
L..___..l

M851 Address Decoder Modules of the file unit (DD02). By installing a jumper in the X field and a jumper in the Y field, the
four functional modules that are housed in that file unit will

Figure 4-4

Functional Mod~le 1/0 Chart

each respond to a unique address 0 through 3. To maintain configuration simplicity, it is recomm~nded that ad1

dresses be assigned to the modules continuously from right to left and from top to bottom (viewin~ cabinet from
rear), starting with channel no. 0.
If the channel numbers are reassigned to the modules, the corresponding screw-terminal strips must be relabeled
!

with the word number. See Figure 4-8 for details on the numbering scheme for slots and screw terhlinals.
In addition, the channel identification chart on the back door of the logic cabinet must be filled in ;and an information page filled out as addresses are assigned, modules are inserted, and customer devices are connected.

4-11

PAGE NO.
WOR6 ADDRESS

FILE

MODULE

Fl ELD

FIELD

CONTACT

UNIT

LOCATION

WIRING

PWR

INTERRUPT

INTERRUPT ENABLE

MODULE TYPE:

SIGNAL
CONDITION TYPE :
GENERIC CODE
WORD NO.
ARC SUPPRESSION
BITS
RES

CAP

TIMING

SIS

ACTIVE
CONTACTS
(FORMAORBJ

BIT FUNCTION REMARKS

1-----1-----+--------+-----+---·-----+---------1 - - - - - 1 - - - - + - - - - - + - - - - + - - - - - - - - t - - - -..·---..· - - - - - - - - - - - - - - - - - - - - - - - - - l
4

1-----1-----+------+-----+---------+-------------------------l

I----+-----+-----+----+---------+----------------------------___,
1-----1-----+-----+----+---------+------------------------<
10
t1

I----+-----+-----+----+------------··-------+--------.. - · - · - - - · - · - - - - - · - · - · - - - - - - - - - - - - - - - - - - - - !
12

1----+-----+-----+----+-----------t--------------------------------___,
13
14

l-----l'-------+----+----t----------+------------------------------1
t5
'-----'-----'-----~---~--------~-----~-------------------<

Figure 4-5

Functional Module 1/0 Page

JUMPERS

GRO

Figure 4-6

G729 Address Jumper Module

4-12

ADDR

Xs
27

Ya
25

MODULE

0
(SLOT 1)

00 - MODULE 0
01-MODULE 1
10 - MODULE 2
11 - MODULE 3

ADDRESS
SELECTOR
NO.O
(00)
P/O INTERFACE
CONTROLLER

(SLOT 2)

IOT
BMB------

(SLOT 3)
NO.I

PDP-8

ADDRESS
AND DATA

I/O

INTERFACE
CONTROLLER

( 01)

(SLOT 4)

DOOi

BUS

( 359 AND 369)
ADDRESS
AND DATA
AC------1

NO. 2
(02)

0
1

NO. 63
( 77) 8

2
3

x
4
5
6
7

000

004

010

014

020

024

030

034

003

007

013

017

023

027

033

037

040

044

050

054

060

064

070

074

043

047

053

057

063

067

073

077

100

104

110

114

120

124

130

134

103

107

140

144

113
150

117

123

127

133

154

160

164

170

137
174

143

147

153

157

163

167

173

177

200

204

210

214

220

224

230

234

203

207

213

217

223

227

233

237

240

244

250

254

260

264

270

274

243

247

253

257

263

267

273

277

300

304

310

314

320

324

330

334

303

307

313

317

323

327

333

337

340

344

350

354

360

364

370

374

343

347

353

357

363

367

373

377
08-0688

Figure 4-7 Channel Address Scheme

·r-r

DUAL CABINET CONFIGURATION

"~~~~~~ ~
SINGLE CABINET CONFIGURATION

MASTER FILE
EXPANDER FILE

A
B

EXPANDER FILE

0 - 0 0 ~MOUNTING
T

SLOT
FILE SLOT

F
R

PLANE

FRONT
REAR

0-{2] 0 STRIP NO.

0 0-0

TERMINAL STRIP

LOG IC AND SCREW
TERMINAL CABINET
LOGIC CABINET
12346-------29

1234 6--------29

SCREW TERMINAL CABINET
FRONT

REAR
A-S16-T1R

MASTER FILE OR
EXPANDER Fl LE

MASTER FILE

A-S17-T2R

A-S11-T9F
A-S12-T10F
A-S13-T11F
A-S14-T12F

FRONT

NOT USED
FOR MASTER ..(
FILE

REAR

A-S1-T1F

A-S16-T1R

A-S2-T2F

A-S17-T2R

A-S3-T3F

A-S18-T3R

A-S4-T4F

A-S19-T4R

A-S6-T5F

A-$21-TSR

A-S7-T6F

A-S22-T6R

A-S8-T7F

A-S23-T7R

A-S9-T8F

A-S24-T8R

A-S11-T9F

A-S26-T9R

A-S12-T10F

A-S27-T10R

A-S13-T11F

A-S28-T11R

A-S14-T12F

A-S29-T12R

EXPANDER

FILE

A-S29-T12R

B -S1-TIF

B-S16-T1R

B-S2-T2F

B -S17-T2R

B-S14-T12F

B -S29-T12R

EXPANDER

FILE

C-S1-T1F

C-S16 -TIR

C- S2-T2F

C-St7-T2R

C-S14-T12F

C-S29-T12R~

11-0974

MASTER FILE
l/O SLOTS

-s -s1

2
9

EXPANDER FILE I 10 SLOTS
09-0689

Figure 4-8 Slot and Screw-Terminal
Numbering Scheme

4-15

The UDC System final factory checkout will be made with address jumpers on G729 Modules installed in such
a manner that addresses are sequential, starting with 000, 001, 002 and 003 in the DD01 Control. Addresses
will progress down the bus in order. Addresses may be changed by moving jumpers on G729 Modules, but care
must be exercised to avoid duplicating X and Y pairs. The address, slot location, and screw-terminal! map should
be used for cross reference and record-keeping.
The matrix shown in Figure 4-7 enables the user to determine the four addresses that belong tC!> any X and Y
combination.
Example:

x = 4, y = 6
Matrix Box for
above X and Y

~
~

This box shows addresses 0230, 0231, 0232, 0233.
These are the absolute addresses for X4 and V6:
Address:

loOo I lo~o'

rohi rof1i

·~y

X=4

Y=6 WD=3

Address:

1 o~o

Q~ g

~·~Y
X=4

Y=6 WD=O

4.5 FUNCTIONAL 1/0 MODULE SETUP
The following data sheets provide information on all UDC8 functional 1/0 modules. The user is advised to read
the data sheets on each module type in his system carefully; he should pay particular attention to the jumper
configurations. The following 1/0 modules are discussed:

a.
b.

c.
d.

e.
f.
g.

i.
j.

Contact Sense (Relay)
Contact Interrupt (Relay)
Contact Sense (Solid State)
Contact Interrupt (Solid State)
Flip-Flop Driver
Single Shot Driver
Latching Relay Output
Flip-Flop Relay Output
Single-Shot Relay Output
DIA Converter Output
1/0 Counter

W730
W732
W740
W742
M684
M686
M802
M804
M806
A633
W734

4-17

W730

CONTACT SENSE RELAY INPUT MODULE

FUNCTIONAL SPECIFICATIONS
Power Requirements:

+5V @0.1A max

Input Response Time:

2 ms including Input Relay Bounce

Input Isolation:

10 9 n min, 250V

Input Voltage:

6V ± 5%@ 15 mA

Field to Logic Transfer:

OV at Input= Logic 0 DATAI

Signal Conditioning:

W400 or W402 required. Provisions for 24 Vdc or 48 Vdc
operation are available.

W730
X ADDR
FROM
SIG. COND.
CARD

Y ADDR
WO ADDR

+3V

TO
UDC
BUS

DATA I

(1 OF 12 BITS l
08-0695

Figure 4-9 Simplified Schematic Diagram (W730)

DESCRIPTION
The W730 Contact Sense Module (Figure 4-9) contains 12 bits of contact sense logic. When addressed by the
UDC, information concerning the state of the 12 relays is present at the DATAI gates. This data is the present
condition of the 12 relays, and can change at any time. It is not stored in any buffer, and is used for monitoring
purposes.

4-19

W732

CONTACT INTERRUPT RELAY INPUT MODULE

FUNCTIONAL SPECI Fl CATIONS:

Power Requirements:

+5V @ 0.45A max

Input Response Time:

1 ms max (Relay Bounce filtered)

Input Isolation:

109 .n min, 250V

Input Voltage:

6V ± 5%@ 15 mA

Field to Logic Transfer:

Interrupt on Input Transition, OV = Logic Oi DATAI

Signal Conditioning:

W400 or W402 required. Provisions for 24 Vdc or 48 Vdc
operation are available.

W732
DEF. INT.

J2
IMM INT
RIF

IMM. EN.
J5
JG

DEF.EN.

DATA I

0
PLS
R

s
+3V

FROM
SIG COND
CARD

PLS CL

GEN 02

X ADDR.
Y ADDR.
WD ADDR.
( 1OF12 BITS)

08-06~6

Figure 4-10 Simplified Schematic Diagram (W732)

4-21

TO
UDC
BUS

DESCRIPTION
The W732 Contact Interrupt Module (Figure 4-10) provides electrically isolated, differential inputs for 12
external customer contacts or voltages. Isolation of up to 250V is achieved by a miniature reed relay buffer
on each input point. This module provides reliable and trouble-free digital sensing in high noise environments.
Also, its differential input characteristics are particularly suited for those applications where the ground of the
customer's excitation voltage power supply may be different from (i.e., not directly strapped to) computer system ground. However, excitation voltages of 24V or 48V may be used by jumper selection on the signal-conditioning module that plugs into the W732 Module. The higher excitation voltages of 24V or 48V are recommended for contact wiping action to ensure reliability where field contacts are open, or subject to dust or oxide
buildup.
The input circuits of the W732 Module consist of 12 miniature Form Creed relay windings. The common contact of each relay is grounded. The NO (normally open) Form A contact is connected to the set input; the NC
(normally closed) Form B contact is connected to the reset input of an RS flip-flop. The consequence of current
flow in the relay winding because of a field contact closure will be to switch ground from the NC contact to the
NO contact of the input reed relay. This action causes the RS flip-flop to set. The bus driver inputs for each bit
are provided by address enabling and the RS flip-flop output. Changing the DATAI bus signal to a true level generates a logic 1 on the UDC DATAI lines when the module is addressed.
The change in state of the flip-flop is differentiated, the resulting pulse is open-collector 0 Red to the System
Interrupt Line.
MODULE JUMPER CONFIGURATION
The jumpers on the W732 Module must be configured by the user to meet his application needs. The jumpers
and their function are listed in Table 4-4 and are shown in Figure 4-11.
Table 4-4
Jumper Options (W732)
Function

Jumpers Required

IMM INT
DEF INT
PLS OP*
PLS CL*

J2, J5
J1,J6
J3
J4

*PLS OP and PLS CL are logic levels to be used in Software Routines as an
aid in determining change of state information.

CUSTOMER INPUTS
Filtering is required for customer contacts when contact bounce duration is greater than the W732 input response
time. Multiple interrupts will occur if contacts are not filtered.

4-22

PL.S OP J3

PL.S CL J4

IMM EN JS
DEF EN J6

IMM INT J2
DE:F INT J1

Figure 4-11

Location of Jumpers (W732)

4-23

W740

CONTACT SENSE SOLID-STATE INPUT MODULE

FUNCTION SPECIFICATIONS
Power Requirements:

+5V@ 0.25A max

Input Levels:

+4.6V to 7 .OV differential input= 1
13 mA to 22 mA
-1.0V to +1.4V differential input= 0
-2 mA to +2 mA

Input Overvoltage Protection:

±12V max sustained input

Failure Mode:

Fails on per point basis

Response Time:

Normal - 2.5 ms max. High speed - 50 µs max

Input Rate:

Normal - 200 Hz max. High speed - 10 kHz max

Common Mode Input Impedance:

10 10 n min

W740
X ADDR
Y ADDR

WO ADDR

TO
UDC BUS

DATA I
FROM
SIG COND
CARD
(10F12 BITS)
08 -0745

Figure 4-12 Simplified Schematic Diagram (W740)

DESCRIPTION
The W740 Contact Sense Module (Figure 4-12) provides high input isolation with solid-state reliability through
the use of a light emitting diode-photo transistor isolation element (OCI) and a Schmitt Trigger (ST). The W740
contains 12 bits of sense logic. When addressed by the UDC, information concerning the state of the 12 bits is
present at the data out gates. This data is the present condition of the 12 bits, and can change at any time. It is
not stored in any buffer, and is used for monitoring purposes. In addition to contact sensing, the W740 may be
directly interfaced to T 2 L, RTL, and DTL logic.

HIGH-SPEED OPTION
The W740 Module is capable of a fast response time as indicated in the module specifications. This is accomplished by clipping out the 0.33 µF capacitors shown in Figure 4-13.

4-25

BIT RESPONSE
TIME CAPACITORS
0.33µ.F

01
02

04
05
06
07
08

09
10

Figure 4-13

Location of Bit Response Time Capacitors (W740)

4-26

W742

CONTACT INTERRUPT SOLID-STATE INPUT MODULE

FUNCTIONAL SPECIFICATIONS
Power Requirements:

+5V@ 0.35A max

Input Levels:

+4.6V to 7 .OV differential input= 1
13 mA to 22 mA
-1.0V to +1.4V differential input= 0
-2 mA to +2 mA

Input Overvoltage Protection:

±12V max sustained input

Failure Mode:

Fails on per point basis

Response Ti me:

Normal - 2.5 ms max. High Speed - 50 µs max

Input Rate:

Normal - 200 Hz max. High Speed - 10 kHz max

Common Mode Input Impedance:

10 10 n max

W742

,~!:,____
~'

RIF

FROM
SIG COND
CARD

START

TO
UDC BUS

+3V

(10F12BITS}

08-0746

Figure 4-14 Simplified Schematic Diagram (W742)

4-27

DESCRIPTION
The W742 Contact Interrupt Module (Figure 4-14) provides high input isolation with solid-state reliability
through the use of a light emitting diode-photo transistor isolation element (OCI) and a Schmitt Trigger (ST).
The contact interrupt module is similar to the contact sense with the addition of interrupt logic. This logic is
activated whenever one of the input points changes state. Via its interrupt and interlocking scan logic, the UDC
controller can rapidly identify the interrupting module. The W742 Module can also be directly interfaced to T 2 L,
RTL and DTL logic.
MODULE JUMPER CONFIGURATION
The jumpers on the W742 Module must be configured by the user to meet his application needs. The jumpers
and their function are listed in Table 4-5 and shown in Figure 4-15.
Table 4-5
Jumper Options (W742)
Function

Jumpers Required

IMM INT
DEF INT
PLS OP*
PLS CL*

W5,W7
W6,W8

W9
W10

*PLS OP and PLS CL are logic levels to be used in software routines, as an
aid in determining change of state information.

HIGH-SPEED OPTION
The W742 Module is capable of a fast response time as indicated in the module specifications. This is accomplished by clipping out the 0.33 µF capacitors shown in Figure 4-15).

4-28

BIT RESPONSE
TIME CAPACITORS
0.33JA-F
00

01
02
03

IMM
EN
W5
DEF
EN
W6

04
05
06
01

PLS
OP
W9

PLS
CL
W10

IMM
INT
W7
DEF
INT

Figure 4-15

Location of Jumpers and Bit Response Time Capacitors (W742)

4-29

M684

FLIP-FLOP DRIVER OUTPUT MIODULE

FUNCTIONAL SPECIFICATIONS
Power Requirements:

+5V @0.5A max

Output Circuit:

Solid State - Open collector returned through diode and
resistor to +5V.

Output Drive Capability:

Resistive Load - 55 Vdc, 250 mA
Inductive Load - 55 Vdc, 250 mA
(Diode Suppression Supplied)
Incandescent Lamps: Lamps rated at 40 mA, to 48 Vdc
Lamps rated at 60 mA, to 28 Vdc
Lamps rated at 80 mA, to 18 Vdc
Lamps rated at 100 mA, to 12 Vdc
T 2 L level compatible (2-unit loads)

Response Time:

Rise Time - 10 µs (Resistive load without
Fall Time - 0.5 µs field wiring)

Logic to Field Transfer:

A logic 1 will provide current sinking ability

Signal Conditioning:

W403 only

M684
....-.__-J\AA~-+ 5V

,___D_AT_A~0~~~~~---1D

TO SIG.
COND. CARD

DRIVER

ADDR X

FROM
UDC
BUS

ADDR Y

ADDR WD
LOAD
START

(1 OF t2 BITS)

08- 0702

Figure 4-16 Simplified Schematic Diagram (M684)

4-31

DESCRIPTION
The M684 Flip-Flop Driver Output Module (Figure 4-16) provides 12 identical solid-state buffered outputs. It
can be used to drive solid-state logic (0 and +5V) or as a current driver for control of solenoid valves, relays,
lamps, displays, etc. Each flip-flop in the output register can be set by the Load Data IOT.
When used to drive logic circuits, a OV output will be generated by the flip-flop being set and a +5V output will
be generated by the flip-flop being cleared. This is accomplished by the load to +5V on the collector of the output circuit. The rise and fall time of this circuit measured at the screw terminals with no external field wiring is
10 µsand 0.5 µs, respectively.
A diode is in series with the +5V load to provide isolation from field voltages when used as a current driver.
Each driver circuit is protected from damage by inductive loads. Provided for all 12 circuits is a common ground
line, which must be connected to the common side of the field power source.

4-32

M686

SINGLE-SHOT DRIVER OUTPUT MODULE
FUNCTIONAL SPECIFICATIONS
Power Requirements:

+5V @ 0. 75A max

Output Circuit:

Solid State - Open collector returned througljl diode and
resistor to +5V.

Output Drive Capability:

Resistive Load - 55 Vdc, 250 mA
Inductive Load - 55 Vdc, 250 mA
(Diode suppression supplied)
Incandescent Lamps: Lamps rated at 40 m.a,, to 48 Vdc
Lamps rated at 60 mA!, to 28 Vdc
Lamps rated at 80 mA, to 18 Vdc
Lamps rated at 100 mA, to 12 Vdc
T 2 L Level Compatible (2-unit loads)

Response Time:

Rise Time - 10 µ,s (Resistive load without
Fal I Time - 0.5 µs field wiring)

Logic to Field Transfer:

A logic 1 will provide current sinking ability

Signal Conditioning:

W403 only

Timing Ranges:

0.5 ms to 80 ms - Short Range
80 ms to 2 sec - Long Range
(Adjustable on a per bit basis)

Recovery Time:

0.05 ms - Short Range
2 ms - Long Range

M686

1K
~----'VV'\,.---

,_____D_A_TA_0_ _ _ _ _---1 D

DRIVER

+ 5V

TO SIG.
COND. CARD

ADDR X
FROM
UDC
BUS

ADDR Y
ADDR WO
LOAD

'----------1

VARIABLE
DEL A Y
( 1OF12 BITS)
08-0698

Figure 4-17 Simplified Schematic Diagram (M686)

4-33

DESCRIPTION
The M686 Single-Shot Driver Output Module (Figure 4-17) provides 12 individually adjustable solid-state pulse
outputs. As noted for the M684, the M686 can be used to drive solid-state logic or as a current driver. The delay circuit is turned on using a Load Data IOT. The pulse duration for each output point is continuously adjustable from 0.5 ms to 80 ms. A connecting jumper allows this range to be increased between 80 ms and 2.0
seconds. The pulse duration will be set to 60 ms when delivered from the factory. The locations of the pulse
duration trimpots and jumpers are shown in Figure 4-18. The recovery time of the single-shots is 0.05 ms when
operating in the low range, and 2.0 ms when operating in the upper range. This recovery time determines the
maximum repetition rate per point.

MODULE JUMPER CONFIGURATION
Jumpers are required for range selection of the timeout. The long timeout range is selected when the jumper is
installed (Figure 4-18).
BIT TIMEOUT
POTS AND
JUMPERS

00
01

02
03
04
05
06

Figure 4-18

Location of Bit Timeout Potentiometers and Jumpers (M686)

4-34

M802

LATCHING RELAY OUTPUT MODULE

FUNCTIONAL SPECIFICATIONS
Power Requirements

+5V @ 0.5A max

Relay Type:

Mercury-Wetted Form C, Magnetic Latching
(NO or NC contacts available at screw termilnals)

Switching Specification:

250V, 2A (100 VA max)

Response Time:

3 ms max

Logic to Field Transfer:

Logic 1 closes NO contacts

Signal Conditioning:

W400 or W402, arc suppression is required Waragraph 4.6)

M802
DATA 0
ADDR X
FROM
UDC
BUS

TO SIG.
COND. CARD

ADDR Y
ADDR WO
LOAD
START

4.0ms
DELAY
( 1 OF 12 BITS )
ojl-0699

Figure 4-19 Simplified Schematic Diagram (M802)

DESCRIPTION
The M802 Latching Relay Output Module (Figure 4-19) provides "fail-safe" operation of 12 electHcally isolated,
normally open or normally closed mercury-wetted relay outputs. Magnetically latched relays rem'ain set in event
of power failure, ensuring continuity and integrity of field circuits.
The register on the module is loaded by the Load Data IOT. The Load Data I OT generates a 4-ms pulse which is
used to energize the relay coils in accordance with the input data. During this period, the latching relavs will
change state in approximately 3.0 ms (without bounce) and remain in that state until changed unt:Jer program
control.
4-35

MODULE JUMPER CONFIGURATION
The board is manufactured and tested with a jumper in place; the normally open (NO) contact, and common is
therefore the active pair (Form A). The normally closed (NC) contact may be used with the common as the active pair (Form B) by removing the existing jumper and inserting it in the adjacent set of split lugs. The jumper
change can be made on a per point basis (Figure 4-20).

RELAY CONTACT
JUMPER
PLACEMENT
00-NC
00-NO
01-NC
01-NO
02-NC
02-NO
03-NC
03-NO
04-NC
04-NO
05-NC
05-NO
06-NC
06-NO
07-NC
07-NO
08-NC
08-NO
09-NC
09-NO
10-NC
10-NO
11-NC
11-NO

Figure 4-20

Location of Bit Relay Contact Jumpers (M802)

4-36

M804

FLIP-FLOP RELAY OUTPUT MODULE

FUNCTIONAL SPECIFICATION
Power Requirements:

+5V @0.5A max

Relay Type:

Mercury-Wetted Form C
(NO or NC contacts available at screw terminalsJ1

Switching Specifications:

250V, 2A (100 VA max)

Response Time:

3 ms max

Logic to Field Transfer:

Logic 1 closes NO contacts

Signal Conditioning:

W400 or W402 - arc suppression is required (Paragraph 4.6)

M804
DATA 0

ADDR X
FROM
UDC
BUS

ADDR

TO
SIG. COND.
CARD

ADDR WO
LOAD

START
( 1 OF 12 BITS)
08-0700

Figure 4-21

Simplified Schematic Diagram (M804)

DESCRIPTION
The M804 Flip-flop Relay Output Module (Figure 4-21) provides 12 electrically isolated, normally open or normally closed mercury-wetted relay output contacts for buffered control of relays, contactors, displays,. lamps, etc.
The module is supplied with a jumper in place so that the NO and common contacts are the active pair (Form A).
The NC and common contacts can be used as the active pair (Form B) by removing the existing jumper and inserting it in the adjacent set of split lugs. This jumper change can be made on a per point basis.
The relays are driven by a flip-flop register which is loaded by a Load Data IOT. A logical 1 ene~gizes the relay
coil in approximately 3.0 ms (without bounce), which remains energized until reset by a logical 0 being loaded
or a power failure.

4-37

MODULE JUMPER CONFIGURATION
The board is manufactured and tested with a jumper in place; the normally open (NO) contact and common is,
therefore, the active pair. The normally closed (NC) contact can be used with the common as the active pair
(Form B) by removing the existing jumper and inserting it in the adjacent set of split lugs. This jumper change
can be made on a per point basis (Figure 4-22).

RELAY CONTACT
JUMPER PLACEMENT

~
BIT NO.

00
01

02
03

04
05
06

07
08

09
10

Figure 4-22

Location of Bit Relay Contact Jumpers (M804)

4-38

M806

SINGLE-SHOT RELAY OUTPUT MODULE
I

FUNCTIONAL SPECIFICATION
Power Requirements:

+5V@ 0.75A max

Relay Type:

Mercury-Wetted Form C
(NO or NC contacts available at screw terminals)

Switching Specification:

250V, 2A (100 VA max)

Response Time:

3 ms max

Logic to Field Transfer:

Logic 1 closes NO contacts

Timing Ranges:

0.5 ms to 80 ms - Short Range
80 ms to 2 sec - Long Range
(Adjustable on a per bit basis)

Recovery Time:

Recovery time is always less than response time- of relay

Signal Conditioning:

W400 or W402, arc suppression is required (Paragraph 4.6)

M806
DATA 0
ADDR X
ADDR
FROM
UDC
BUS

Y
TO
SIG. COND.
CARD

LOAD
START
NC

'---------1

VARIABLE
DEL A Y
(1OF12 BITS l
08-0701

Figure 4-23 Simplified Schematic Diagram (M806)

DESCRIPTION
The M806 Single-Shot Relay Output Module (Figure 4-23) provides 12 electrically isolated, momentary, normally
open or normally closed, mercury-wetted contact uutputs for initiating alarms, lamps, field rela~s, etc:. The module is supplied with a jumper in place so that the NO and common contacts are the active pair (Form A). The NC
and common contacts can be used as the active pair (Form B) by removing the existing jumper and inserting it in
the adjacent set of split lugs. The jumper change can be made on a per point basis.
The relays are driven by single-shots which are triggered by the Load Data IOT. A logical 1 energizes the relay
coil for the preset pulse duration, thereby operating the output relay contacts for that period oftime. The

4-39

duration of the contact closure for each output point is continuously adjustable from 0.5 ms to 80 ms.
Connecting a jumper in the variable delay circuit allows this range to be increased to between 80 ms and 2.0
seconds. The duration will be set to 60 ms when delivered from the factory. The location of the pulse duration
trimpots is shown in Figure 4-24.
MODULE JUMPER CONFIGURATION
Timeout Range - Jumpers are required for Range selection of timeout. The long timeout range is selected
when the jumper is installed (Figure 4-24).
Relay Contact - The board is manufactured and tested with a jumper in place; the normally open (NO) contact
and common is, therefore, the active pair. The normally closed (NC) contact can be used with the common as
the active pair (Form B) by removing the existing jumper and inserting it in the adjacent set of split lugs. This
jumper change can be made on a per point basis (Figure 4-24).
BIT RELAY CONTACT
JUMPER PLACMENT

BIT TIMEOUT POTS
AND JUMPERS

02-NC
02-NO

03-NO
03-NC

00-NC
00-NO
01-NO
01-NC
03

04-NC ~---'
04-N0----

05-NC
05-NO
07-NO

07-NC
06-NO
07

06-NC
08-NO
08-NC
09-NC
09-NO

10-NO
10-NC
09

11-NC
11-NO

Figure 4-24

Location of Bit Timeout Potentiometers and Jumpers
and Relay Contact Jumpers (M806)

4-40

A633

DI A CONVERTER OUTPUT MODULE
FUNCTIONAL SPECIFICATIONS
Resolution:

One part in 1024 of ful I scale

Digital Input (CHO):

0000 = 0 output
1000 = 1/2 full-scale output
1777 =full-scale output (-1 LSB)

Analog Output:

OV to -10V at 3 mA max

Gain Accuracy:

Adjustable to within± 0.05% of full scale at 25°C

Zero Offset:

Adjustable through zero

Settling Time:

35 µs max to within ± 0.05% of final value with 150 pF load.
50 µs with signal-conditioning module.

Linearity:

± 1/2 LSB

Power:

+5V ± 0.25V 450 mA max
+18V ± 0.01 V 147 mA max
-1 BV ± 0.01 V 30 mA max
Power is supplied from an external H738A supplv and applied through the screw terminals. One H738A supply will
supply the necessary power to four A633 DACs aind to its signal-conditioning modules.

Signal Conditioning:

Four output signal-conditioning modules are available for use
with the A633 DAC Modules.
A233
OV to +1 OV output at 15 mA r:nax*
A234
+1 V to +5V output at 15 mA max*
A235
4 mA to 20 mA into 750 n max*
A236
10 mA to 50 mA into 300 n max*

DESCRIPTION
The A633 DAC Module contains four 10-bit D/A converters, with input buffer registers, ladder networks, output voltage amplifier, and a reference supply (Figure 4-25).
There is also a power low circuit on the module, which grounds the input load signal in the event that computer
power is low or is lost. This feature is available for the user who cannot afford to lose analog output during a
power failure and has the converter connected to an auxiliary back-up supply.
The module operates like any digital output module in the UDC System. The 12-bit input data word is divided
into two major parts: the DAC data word (bits 02 through.11) and the channel select code (bits 0 and 1). The
2-bit channel select code determines which D/A channel will be selected.

*The outputs from the signal-conditioning modules are single-ended outputs. Therefore, the loads should be the type that can be groU1nded to the
analog ground, which, in turn, is connected to system ground in the UDC.

4-41

BitO

Bit 1

Channel

03
The complete 12-bit data word can be loaded on the D/A module at one time. Channel selection must be updated at each data word transfer. There are no status bits on the module; therefore, enough time must be allowed
between conversions for settling time purposes.

DATA FORMAT

'-...--A--~~~~~~-......,.--~~~~~~-

10 BIT DATA

CHANSEL

A633
DATA0<02:11 >

D
BUFF
REG
00

LAD
NET

OUT 00

LAD
NET

OUT 01

LAD
NET

OUT 02

D
BUFF
REG
01

D
BUFF
REG
02

FROM
UDC BUS

TO SIG
COND CARD
D
BUFF
REG
03

DATAO <OO>
DATO <01 >

OUT 03

LAD
NET

+1BV

DAC
ADDR
DECODER

REF
REGULATOR

-18V

+5V(UOC)

B LOAD

X ADDR _ _
Y ADDR
WO ADDR

MODULE
ADDR
DECODER

LOAD

POWER
LOW
CKT

+5V(DAC)

08-0747

Figure 4-25 Simplified Schematic Diagram (A633)

4-42

MODULE JUMPER CONFIGURATION
The only jumpers provided are those needed for use with a battery or back-up power supply. (Figure 4-26)
Function

Jumper

Battery or Backup Supply

W1
W2

Normal Operation

When the battery or back-up supply is used, the start signal is inhibited from clearing the DACs durin~1 power
restoration.

MODULE ADJUSTMENTS
All module adjustments are made at the factory. However, if there is a need for readjustment, the A-SP-BA633-0-2
DAC Checkout Procedure should be consulted.

REF

R149

EXT BATT
W'I

NORM

w:2

i~~~

PWR LOW

OAC{
0 3 BALANCE _ _ _ _.....,

ADJ R60

R156

Figure 4-26

Location of Adjustments and Jumpers (A633)

4-43

'W734
1/0 COUNTER MODULE

FUNCTIONAL SPEC I Fl CATIONS
Counter Type:

16-bit asynchronous binary up-counter buffered with anticoincidence circuitry. Read/Write

Power Requirements:

+5V@ 1A max

Counter Inputs:

Selectable by PC switch

PC Switch Position

Input
Contact Input (CONT)
109 r2 min, 250V, input isolation
6V ± 10% @ 18.5 mA input voltage
100 Hz max input frequency

Voltage Input (CV)
"O" = 0.7V max
"1" = +1.4 V to 3.5V
25 kHz max input frequency

CLOO UDC internal clock ( 175 Hz to
1.75 kHz adjustable)

CL01 UDC internal clock (1.75 kHz
to 17.5 kHz adjustable)

CLL line frequency clock

No input (Ground)

External Enable (EN):

Enabled = 0.7V max; not enabled= 1.4 to 35V

Counter Outputs:

Pulse (P)
Control (C)
Sign (S)

Output Drive Capability:

Resistive Load: 55 Vdc@ 250 mA
Inductive Load: 55 Vdc @ 250 mA
(Diode Suppression Supplied)
Incandescent Lamps: Lamps rated at 40 mA to 413 Vdc
Lamps rated at 60 mA to 213 Vdc
Lamps rated at 80 mA to 18 Vdc
Lamps rated at 100 mA to 12 Vdc
T 2 L Compatible (2 unit loads)

Pulse (P) Output Characteristics:

Frequency (At system counting frequency)
CLK 00: 175 Hz to 1.75 kHz, adjustable
CLK 01: 1. 75 kHz to 17 .5 kHz, adjustable
CLK L: Line frequency

4-45

FUNCTIONAL SPECI Fl CATIONS (Cont)
Width (Adjustable in four ranges)
RANGE 1: 20µsto 112µs
RANGE 2: 112 µs to 630 µs
RANGE 3: 630 µs to 3.5 ms
RANGE 4: 3.5 ms to 20 ms
Logic to Field Transfer:

All outputs are enabled when sinking current.

Address Restriction:

Due to the fact that the buffer update is inhibited while the
W734 Counter is addressed, the module should not be located
in address slot 000.

W734
CONT
CV
EN

EXT EN

PULSE
GEN

TO SIG COND
CARD

DATA 0

LOAD
B

F
E
R

WO
GENERIC
/L---D-AT_A_I_ _ _ _ __.__--1 ~ 1 ~---1

~~-----------.--~ ~

OVERFLOW

FROM UOC BUS
START
INTERRUPT

RESET
RIF

IMM EN_ _

----------------'
-------------~

WO
SCAN STOP

11·0976

Figure 4-27 Simplified Schematic Diagram (W734)

4-46

DESCRIPTION
The W734 Counter Module (Figure 4-27) is a 12-bit (optionally 16-bit) asynchronous binary up-counter. An
output buffer register is updated after each counter increment. When the module is addressed (under program
control) the buffer update is inhibited, preventing any data change. A full 12-bit data word can be parallel
loaded into the counter, allowing the counter to be preset under program control. To use the counter as a downcounter, the 2's complement of a number must be loaded.
One of five inputs, selectable by a PC mounted switch, can be selected for incrementing the counter. Two are
external event inputs and three are internal UDC clock inputs. The external inputs include a contact sensing input and a voltage input.
An enable/disable jumper is provided to select either an external enable or an internal self-enable to start the
counter after each preload. Upon overflow, the counter generates an interrupt and can continue or stop counting.
A jumper is provided to inhibit the counter on interrupt.
The counter provides three solid-state outputs: pulse, control, and sign. The pulse output is a pulse train whose
frequency is determined by the counter clocking frequency (counter input) and whose pulse width is established
by a jumper and a potentiometer. The control output goes true whenever the counter is enabled. The sign output is available when the counter is set up (by jumper) for 11 bit plus sign operation.
MODULE CONFIGURATION
Setting the counter up for a specific application is a user task. Therefore, the user should familiarize himself with
the various operating modes of the counter.

FUNCTIONAL MODES
ENABLE (External/Self)
Two methods are available for enabling the counter: external and self. In the external enable mode, a signal at
the EN screw terminals will enable the counter. If a count signal is present at the time the counter is enabled it
will not be counted. This mode is useful when external event synchronization is required to start the count. If
the counter is set up to operate in the self-enable mode, power up, system initialization or presetting the counter
will start the counter. Then, upon OVERFLOW, the counter is disabled or continues counting depending on
jumper setup. The counter starts counting from zero or from the count loaded.
OVERFLOW (Halt/Continue)
The module can be set up to halt or continue counting on OVERFLOW. In either case, an interrupt signal is
issued by the counter.
SIGN OUTPUT
The module can be set up to provide for a direction bit by selecting the SIGN option. With this option selected,
the module becomes a 11-bit counter with a sign bit, and overflow will occur when counter bit 10 (the 11th bit)
overflows. The SIGN ("S") output is available at the screw terminals as a solid state driver (open-collector) output.

COUNTING MODES
The module is able to count events or periods depending on which jumper is installed. Event and period counting
is shown in the following illustration.

4-47

5 EVENTS

+ 4--1

4 PERIODS
08-0739

The control output ("C") from the module behaves uniquely for each of the two counting modes.
EVENT Counting
In this counting mode, the control output becomes TRUE when the counter is enabled and NOT TRUE on
counter OVERFLOW as illustrated in the following timing diagram.

r-INPUT PULSE

____ _n__

TRAIN - - - -

ENABLE (EXT/SELF)

OVERFLOW

I~--------------------------------------~--------~
I

"c" CONTROL OUT

'~-------------------------------

08-0740

PERIOD Counting
In this counting mode the control output becomes TRUE at the first count and NOT TRUE on counter
OVERFLOW as illustrated in the following timing diagram.

OVERFLOW

____ _n__

INPUT PULSE TRAIN _ _ __.

I
I

ENABLE (EXT/SELF)

---i~-~----------------------------------+-:--------~--

"c" CONTROL OUT
08··0741

NOTE
OVERFLOW will occur when counter bit 10 or 11
(depending on SIGN option selection) overflows.

4-48

OPERATIONAL MODES
The counter must be set up to operate as an interrupting 1/0 module in a UDC System. Therefore~ the desired

GENERIC code and interrupt level (IMM or DEF) must be established and selected. In addition, tlhe desired
counter input (clock) and output pulse width must be selected to place the counter in operation.
INTERRUPT Levels
The desired interrupt level must be chosen by installing the proper jumper on the counter module. Like all UDC
interrupt modules, immediate and deferred interrupt level declarations are available for selection.
GENERIC Code
Since the counter can be used for a variety of functions, the following four GENERIC codes have been assigned
to the counter module.
GENERIC Code

0123
0100
0101
0110
0111

One of these codes can be selected by installing the proper jumper(s) on the counter module.
CLOCK Selection
The input clock or counter input is selected by setting PC switch S1 to the desired position. The switch positions
and the corresponding counter inputs are as follows:
Switch Position

Input

1
2
3

CONTACT
VOLTAGE

CLOO
CL01
CL LINE
GROUND

5
6

Position 6 should be selected if the counter is used as a data storage or transfer buffer without being clocked.
OUTPUT PULSE WIDTH
The width of the pulse output ("P") is continuously adjustable from 20 µs to 20 ms in four ranges. Thus to obtain the desired width, the proper range must be selected by installing the correct jumper and potentiometer R32
must be adjusted. The four ranges are:
RANGE 1:
RANGE 2:
RANGE 3:
RANGE 4:

20µsto 112µs
112 µs to 630 µs
630 µs to 3.5 ms
3.5 ms to 20 ms

MODULE JUMPER CONFIGURATIONS
Table 4-6 and Figure 4-28 identify the required jumper for each counter mode. Using the table, the user should
make sure that the proper jumpers for the desired modes of operation are installed on the module,

4-49

Tab!e 4-6
Jumper Options (W734)

Module Jumpers

W1
W4
or W3 or W6 W7 W8 W9 W10 W11
W2
W5

W12
W15
W22
W29
or W14 or W17
or W19 and
W13
W16
W18
W20

W30
and
W21

W23

W28
or
W24

W25

W27
or
W26

FUNCTIONAL MODES

EXTERNAL ENABLE

SELF ENABLE

HALT ON OVRFL

CONTINUE ON OVRFL

SIGN BIT
COUNT I NG MODES
EVENT COUNT
+:>.

cJ,
0

PERIOD COUNT
OPERATIONAL MODES

IMMINT_

DEF INT
GEN
CODES

PULSE
RANGE

x
x

0100
0101
0110
0111
RANGE1
RANGE 2
RANGE3
RANGE 4

12 BIT OPERATION
16 BIT OPERATION

x
x
x

x
x

x
x
x

PULSE WIDTH
RANGE W7-W10
PULSE
WIDTH---R32
GEN3
W11-W12

IM EN
W2
DEF EN
W3

GEN2
W14-W15 --..:,;,,.SIGN
W17

PERIOD
COUNT
W30

EVENT
COUNT
W29
CONTINUE
ON OVERFLOW
W19
PERIOD
COUNT
W21

HALT ON
:· OVERFLOW
W18
i.

EVENT
COUNT
W20

IM INT

EXTERNAL
ENABLE
W24

W5
DEF INT
W6

12 BITS
W25

SELF EN
W23

16 BITS
W26

$1 COUNTER
INPUT SWITCH

Figure 4-28

Location of Jumpers and Input Switch (W734)

4-51

4.6 SIGNAL CONDITIONING
The signal-conditioning modules serve as the interface between the field devices and the function$! 1/0 modules.
These modules plug into the end of the 1/0 module and accept the BC40C Cable Connector at the handle end.
Proper selection of signal-conditioning components and complete understanding and utilization of UDC signalconditioning options are essential for proper UDC System operation and implementation.
4.6.1

Field Power

In many cases, power from the field will be applied to functional 1/0 modules for contact sensing and load switching purposes. Two methods of distributing field power to UDC System can be used: common and isolated.
4.6.1.1

Common Power -The common power signal-conditioning module (W402) will distribute a single field

power source to all 16 bits on the functional 1/0 module as shown in Figures 4-29 and 4-30.
4.6.1.2 Isolated Power - The isolated power signal-conditioning module (W400) is used when the field power
source for each bit is isolated as shown in Figures 4-31 and 4-32.
4.6.1.3 Driver Output - The driver output signal-conditioning module (W403) provides ground continuity for
nonisolated solid-state driver outputs.
4.6.2 Input Module Signal Conditioning for Contact Sensing
The following input modules may be used for contact sensing purposes.

a.
b.

c.
d.

W730
W732
W740
W742

These functional modules require 6V@ 15 mA to drive each of their 12 input circuits. However, the rnmoval of
voltage scaling jumpers on the W400 and W402 signal-conditioning modules permits utilization of 24V or 48V
as a source power. Table 4-7 defines the jumpers to be cut to permit utilization of higher input voltages. Figures 4-51 and 4-53 identify the location of these jumpers.
Table 4-7
Voltage Scaling Options
Power Source

Jumper

6V
24V
48V

Cut None
Cut A
Cut A and B

4.6.3 Input Module Signal-Conditioning for Logic Level Sensing
The following solid-state input modules can be used for logic level sensing purposes.

a.
b.

W740
W742

TTL, RTL, or DTL logic circuits can be used to supply the logic levels (Figures 4-33 through 4-35). The W400
signal-conditioning module must be used to interface the field logic circuits with the solid-state input modules.

4-53

SCREW
TERM

M80X

W402

+
F

0----0

MERCURY
WETTED
NC RELAY 00

~
NC

0---0

•

HK1

FIELD
POWER

MERCURY
WETTED
NC RELAY 01

F1
HK2

11-0977

Figure 4-29 Common Power for Load Switching, Wiring Diagram

SCREW
TERM

W402

W730/W732 (RELAY) or
W 740/W742 (OCI)

---~

RELAY
or

SWITCH

0----0

I
___ .J

I
I

RELAY

F
G
0----{?)

SWITCH

I
I

____ _J

HK1

FIELD
POWER
HK2

OB-0748

Figure 4-30 Common Power for Contact Sensing, Wiring Diagram

4-54

SCREW
TERM

MSOX

W400

B
F

0-----0

MERCURY
WETTED
NC RELAY 00

FIELD
POWER
A

NC
B

0------0

FIELD
POWER

MERCURY
WETTED
NC RELAY 01

HK1

HK2

11-0979

Figure 4-31

SCREW
TERM

Isolated Power for Load Switching, Wiring Diagram

W730/W732 {RELAY) or
W740/W742 {OCI l

W400

- - - -,

RELAY

SWITCH

FIELD
POWER

0-----0

I
I

~EJ

---,

I
I

RELAY

SWITCH

0------0

~EJ

FIELD
POWER

I
I

_ _ _ _J

A
HK1

HK2

08-0749

Figure 4-32

Isolated Power for Contact Sensing, Wiring Diagram

4-55

SCREW
TERM

W400

W740 OR W742

+5V

270
F

0---0

+5V

270

HK1

HK2

06-0750

Figure 4-33

SCREW
TERM

Logic Level (TTL) Input, Wiring Diagram

W740

W400

OR W742

+5V

270
F

~
+

+5V

270

F
G
~
+

HK1

HK2

06-0751

Figure 4-34

Logic Level (RTL) Input, Wiring Diagram

4-56

SCREW
TERM
+5V
1.75K

W400

W740 OR W742
B

270
F

0-----0

+5'11

+5V

270

0-----0

HK1

HK2

08-0752

Figure 4-35

Logic Level (DTL) Input, Wiring Diagram

4.6.4 Mercury-Wetted Relay Contact Signal Conditioning
All M800 series functional modules contain 12 mercury-wetted relay outputs. These modules are used for load
switching purposes. The contact life expectancy, which can exceed 22 billion operations, depends largely on the
use of proper contact protection. Contact protection is required if the contacts are expected to handlle energy
levels in excess of 40 µ.J. This may be represented by the stored energy of a series inductance just prior to opening its circuit or that in a shunt capacitance immediately prior to closing the discharge circuit. In order to handle
this and larger energy levels, the following maximum voltage rates and current rises have been set.

When the contacts close a circuit, the rate of current increase should not exceed 25A/µs.

When the contacts open a circuit, the rate of change of voltage increase should not exceed fiV /µs.

The arc suppression circuit must bring the rate of current increase and the rate of voltage change increase to the
levels specified above. A series RC network across the relay contacts comprises the arc suppression nutwork.

4.6.4.1 Location of the Arc Suppressica Network - Space is provided on the W400 and W402 'Signal-conditioning modules for the RC arc suppression network. The resistor should be installed in field "F" and the capacitor
in field "G" (Figures 4-29 through 4-32 and Figures 4-50 and 4-53).

4.6.4.2 Determination of RC - The values of R and C for resistive loads can be determined by using the nomograph and formula presented in Figure 4-36. This nomograph can also be used for reactive loads. However,
further transient protection may be required, as discussed in the following paragraphs.

4.6.4.3 Load Consideration - The nature of the load must be carefully considered, especially if the contacts
are expected to switch the load current. The following types of loads are commonly used.

4-57

(/)

::c
0

I
I.LI
0

t:!

(/)

ii)
I.LI

NETWORK
12

20 I15 I-

MFD

10 ....
9 l-

R= 1omcx OHMS

e 1-

7 ......

6 II5 II4 I-

CX=l+§.Q
E
E•SOURC£VOLTAG£UilMEOIATELYPRIORTOCONTCLOSUR[

FOR E < 70, R MAY BE 3X INOICATEO VALUE

I-

70 < E < 100, R MAY BE ± 50'4

3 I-

100< E < 150, R MAY BE ± 10'1,
E > 150, R MAY BE ± 5 '!,
RMINIMUN

2 I-

.02

CMINIMUM

.03

'0.5 OHM
'.001 MFD .

.04 .05 .06 .07 .09 .I

1.5

.5 .6 .7 .8 .9 1.0

CURRENT - AMPERES

1.5

2.0

3.0

4.0 5.0

( IMMEDIATELY PRIOR TO CONTACT OPENING )

How to Use Nomograph
This nomograph affords a convenient means of determining the necessary
contact protection. To determine C, the value of load current is found on
the CUR RENT axis. Reading directly up to the sloping capacitance line, the
value of C is determined from the right hand CAPAC IT ANGE scale. To determine R, read directly up from the load current value to its intersection
with appropriate load voltage line. The value of R is then read from the left
hand RESISTANCE scale. For AC loads, peak values of current and voltage
must be used.

Figure 4-36 Contact Protection Network Nomograph
Reprinted by permission of C.P. Clare & Co., Chicago, Illinois

4-58

Resistive Loads
Proper arc suppression for resistive loads is relatively easy to accomplish. The RC values as detertninecl by the
use of the nomograph and formula will usually provide adequate protection. However, if long li~es am run to
the load, line inductance may become significant and transient protection may be required.
NOTE

Use peak values in calculating RC when ac power is used
for load switching.
DC Inductive Loads
A voltage transient is generated whenever the mecury-wetted relay contacts open and interrupt tllie current flow
in an inductor (Figure 4-37). The instant the contacts open, the inductor behaves like an energy :source with

LOAD

MERCURY
RELAY
CONTACTS

CONTACT
RATING

-----------

-----

TIME--+

To
(Al No Arc Suppression

MERCURY

RELAY
CONTACTS

rvYY'

l1 r I

LOAD

__ ____

CONTACT
RATING

l I

TIME__;_...

(Bl R-C Rote of Rise Protect ion

MERCURY

RELAY
CONTACTS

I :~J

CONTACT
RATING

Vic

-.i--

J_------0

-- -- - -

____

,_::::::

+
Vs

T.___..i..,___l

______________

,______......._

TIME--+
(Cl Rote of Rise ond Transient Protection
11-0984

Figure 4-37

Arc Suppression Circuit Characteristics

4-59

a high impedance load into which it can dissipate its energy. The high impedance load takes the form of the
opening contacts. The voltage across the high impedance load (the contacts) immediately rises to whatever value
is necessary for an arc-over to occur, thereby dissipating the energy stored in the inductor. The design objective
for this load is to provide control on the rate of current and voltage rise and suppress ordimit the voltage transient
so that it remains within contact ratings. Since the volt-second area under the transient curve remains constant,
the proper transient protection for a given application depends on how long the transient voltage can remain.
Effects and characteristics of arc suppression circuits are illustrated in Figure 4-37.
In Part A (Figure 4-37), having no arc suppression, damage will occur to the mercury-wetted relay contacts due
to the rate of rise of voltage and the voltage transients exceeding the contact rating specifications.
In Part B (Figure 4-37), the rate of rise is controlled but the transient still exceeds the contact rating specification.
Safe operation is achieved in Part C (Figure 4-37), when both
the rate of rise and the transient are controlled.
AC Inductive Loads

RELAY

TCONTACTS

Arc suppression for ac inductive loads is difficult to determine
by calculation due to the complex nature of the mathematics.
It is usually easier to use a bench test setup to identify transients and choose the appropriate RC values for the suppression circuit. One technique, which is useful for extreme loads
(above 100 Vac), is to place the main RC arc suppression circuit across the load as shown in Figure 4-38.
This alleviates the problem of ac leakage current through an
RC arc suppressor that is in parallel with the contacts. But,
this technique can result in a condition that exposes the contacts to voltage transients having a rate of rise in excess of
5V /µs due to the inductance of the field wiring. A secondary
arc suppressor, R2-C2, must then be installed in parallel with
the contacts. Since C2 need only be one-hundredth of the calculated value, ac leakage is reduced markedly.
An alternate method for protecting the contacts under extreme load conditions is to use a thyristor in parallel with the
traditional arc suppression circuit across the contacts, as shown
in Figure 4-39. All arc suppression components can then be
placed in the arc suppression fields ( F and G) of the signalconditioning modules (W400 and W402).
Capacitive Loads

}2 C:::r
I

AC Vs

NOTE:
RI and R2 should be calculated values.
Cl may be increased by 10 times calculated value
to further reduce transients.
C2 need only be 1/100 of calculated value.

11-0985

Figure 4-38 Arc Suppression
for Extreme Inductive Loads

LOAD

RELAY
CONTACTS

AC Vs

NOTES:
Rl and Cl provide rate of rise protection.
Dl Thyrister provides transient protection.

11-0986

Figure 4-39 Alternate Arc Suppression
for Extreme Inductive Loads

R2
LOAD
~~~~--~~..JVV'--~1---~~-o+

Since capacitors appear as short circuits when power is switched
into them and as high energy sources when power is switched
out of them into low impedances, current transients can produce problems. The design objective in protecting mecurywetted relay contacts is to limit the rate of current increase
when the contacts close and also to limit the absolute current
so as not to exceed contact specifications. The simplest way
to obtain this protection is illustrated in Figure 4-40.

4-60

NOTES=
R1 and Cl provide rate of rise protection.
R 2 provides current limiting.

Figure 4-40 Arc Suppression
for Capacitive Loads

11-0987

4.6.5 Driver Output Signal Conditioning
All M600 series functional modules contain 12 buffered open-collector driver output stages for driving loads.
The W403 Signal-Conditioning Module must be used as the interface between the field devices and the driver
output modules. Diode suppression for inductive loads is included on the driver output modules.; ther1efore, no
external suppression circuit is required. The signal-conditioning module is designed to accommodate both common and isolated field power applications. The only difference between common and isolated power configurations is in the way the loads are connected to the screw terminals. Figures 4-41 through 4-44 illu:strate the wiring
techniques. The maximum current that can be switched by a W403 Module at any one time is 4A.
The M600 series functional modules can also be used to drive T 2 L logic because the driver collectors are returned
to +5V through a diode and resistor. Again, only the W403 Signal-Conditioning Module can be used a:s the interface. The wiring technique for this application is illustrated in Figure 4-45.
NOTE
For driver output and logic level output configurations
described above, field power is not isolated from UDC
power as for load switching, contact sensing, and logic
level sensing configurations described previously.
4.6.6 ·DAC Module Signal Conditioning
The A633 DAC Module contains four D/A converters. Four different signal-conditioning modules are available
for interfacing the field devices with the DAC module. They are:
Module Type

Output Characteristics

A233
A234
A235
A236

0 to +10V@ 15 mA max
+1 V to +5V @ 15 mA max
4 mA to 20 mA, 750il max
10 mA to 50 mA, 300il max

The four outputs from the signal-conditioning module are single ended outputs (Figure 4-46). Therefore, the
loads should be of the type that can be grounded to the analog ground which, in turn, is connect:ed to system
ground in the UDC. Modules A234, A235, and A236 are factory adjusted, but can be adjusted in the field (refer
to the A-SP-BA633-0-2 DAC Checkout Procedure) .
NOTE
Loads, including screw-terminal wiring, having up to
0.1 µF will not cause instability but will affect settling
time.

4.6.7 Counter Module Signal Conditioning
The W734 1/0 Counter Module is a 12-bit (optionally 16 bits) asynchronous binary counter. The exteirnal inputs
and outputs include:

a.
b.

c.
d.

e.
f.

EN Input
CONT Input
~V Input
f_ Output
C Output
S Output

4-61

SCREW
TERM

MGXX

W403

~
+

HK1

FIELD

POWER

F1
HK2

GRD

11-0988

Figure 4-41

Common Power for Driver Output, Wiring Diagram

F2,4A

LOAD

[

LOAD

+
FIELD

POWER

F1, 4A
11- 0989

Figure 4-42

Common Power for Driver Output, Schematic Diagram

The W400 Signal-Conditioning Module must be used to interface the field devices (counter inputs and outputs)
with the counter. The counter outputs can be connected to accommodate common or isolated field power for
driving loads or can be connected to provide logic level outputs (Figures 4-47 through 4-49). No external protection is required for driving inductive loads since diode suppression is included in the counter output circuits.

4-62

SCREW
TERM

W403

M6XX

+
F

0--0

F 0------0G

HK1

F1
HK2
GRD

11-0990

Figure 4-43

Isolated Power for Driver Output, Wiring Diagram

LOAD

'·

LOAD

FIELD
POWER

FIELD
POWER
A

F1, 4A

11-0991

Figure 4-44

Isolated Power for Driver Output, Schematic Diagram

4-63

SCREW
TERM

W403

MGXX

+
F

~+5V
F

HK1
F1
HK2

GRD

11-0992

Figure 4-45

Logic Level Output, Wiring Diagram

4.6.8 Signal-Conditioning Modules
The following data sheets provide information on all UDCB signal-conditioning modules. The user is advised to
read the data sheets on each module in his system carefully and pay particular attention to the jumper configurations. The following signal-conditioning modules are discussed.

a.
b.

c.
d.

e.
f.
g.

Isolated Power
Common Power
Solid-State Driver
Buffered Voltage
Buffered Voltage
Buffered Current
Buffered Current

W400
W402
W403
A233
A234
A235
A236

4-64

A633

SCREW
TERMINALS

A23X

r---

,....

OUT 00

__.n.

~
OUT 01

}

LOAD

'\7

-S
~

-u

~
'\7

;;:.

OUT 02

~
~

_,t

-G
_;;:.
-..;;;,
TP

OUT 03

-G

-,;;;;,r

LOAD

1'
~

""'
5V

ov{

_.r.

'!!!
F1, 0.5A
-18V-

-0

J..

\"11

-v
_L'\..

':!
F2, 0.5A
+18V-

-<>

.~
'\7

+v
,....

18V RETURN-

......______.

F ROM
7384
OWER SUPPLY

*A235 A236 ONLY
11-0993

Figure 4-46 DAC Wiring Diagram

4-65

W734

W400
SCREW
TERMINALS

+5V

FIELD
POWER

c
+5V

CV
B

-:1:-

p
B

c
B

s
B

+
Fl ELD
POWER

, 1-0994

Figure 4-47

Counter Input and Output (Common Power), Wiring Diagram

4-66

W734

W400
+5V

SCREW
TERMINALS

+5V

+
CONT

FIELD
POWER

+5V

CV
8

-=1-

p
8

c
FIELD
POWER

c
8

c
FIELD
POWER

s
8

1-.i

, 1-0995

Figure 4-48 Counter Input and Output (Isolated Power), Wiring Diagram

4-67

W734

W400

+sv

SCREW
TERMINALS

+5V

EN
B

CONT

+ FIELD

POWER

c
+5V
CV
B

1-----NV1.----- +5V

NO CONN

+5V

i-----""""--l+---+5V

NO CONN

11-0996

Figure 4-49 Counter Input and Output (Logic Level), Wiring Diagram

4-68

'N400

ISOLATED POWER SIGNAL-CONDITIONING MODULE

The isolated power signal-conditioning module (Figures 4-50 and 4-51) is a double-ended module providing the
interface between 16 individual points on the functional 1/0 modules and customer contacts or field si1gnals.
Differential pair field wiring from the screw terminals is terminated on a 36-pin connector that connects to the
rear of the module.
CAUTION
This module may not be used with M684 Flip-Flop Relay Driver or M686 Single-Shot Relay Driver Modules.

SCREW
TERMINALS

W400

B
CUSTOMER
WIRING

ARC SUPRESSION
NET STUDS

VOLTAGE
SCALING
JUMPERS

F 0---0G

TO FUNCTIONAL
I /0 MODULE

( 1 OF12 BITS)
08-0692

Figure 4-50 Simplified Schematic Diagram (W400)
The isolated power feature is used where each field digital 1/0 point is supplied with power at the field location.
Each pair of control wires is isolated from every other point and from UDC ground.
When used with input modules (Contact Sense, Contact Interrupt), resistor/jumper selection on each circuit scales
the field-supplied excitation voltage of 6V, 24V, or 48 Vdc to 6 Vdc at 15 mA point for proper input circuit operation. The module will be delivered setup for 6V operation.
The mercury-wetted relay contacts of the output single-shot relay, flip-flop relay, and latching relay modules are
rated at 2A, 250V (the product not to exceed 100 VA) and require arc suppression. Provision far customermounting (split lug fields F and G) of the appropriate RC filter elements for arc suppression for each circuit is
provided on the W400 and W402.

4-69

BIT 00 VOLTAGE
SCALI NG JUMPERS
4A FUSES

BIT 00 C
JUMPER

BIT 00 ARC SUPPRESSION
NETWORK MOUNTING STUDS

Figure 4-51

Location of Jumpers and Component-Mounting Studs (W400)

W402

COMMON POWER SIGNAL-CONDITIONING iMODULE

The W402 Common Power Signal-Conditioning Module (Figures 4-52 and 4-53) is a double-ended module
providing the interface between 16 individual points on the functional 1/0 modules and customer contacts or
field signals. Differential pair field wiring from the screw terminals is terminated on a 36-pin connect!Dr that
connects to the rear of the module.
CAUTION
This module may not be used with M684 Flip-Flop Relay Driver or M686 Single-Shot Relay Driver Modules.

SCREW
TERMINALS

w 402

TO FUNCTIONAL
I/O MODULE

+ 1 - - - - + - t .... > - + - - - - <
FIELD
POWER

( 1 OF 12 BITS)
08-0693

Figure 4-52 Simplified Schematic Diagram (W402)
The common power signal-conditioning module has a power input pair that permits field-supplied excitation or
control power to be brought directly to the signal-conditioning module and distributed in parallel (common)
to each of the circuits on the functional 1/0 module. The input is fused for 4A. Therefore, when the combined
relay output current exceeds 4A on a module, Module W400 must be used for power distribution and conditioning.
When used with input modules (Contact Sense, Contact Interrupt) resistor/jumper selection on each circuit scales
the field-supplied excitation voltage of 6V, 24V, or 48 Vdc at 15 mA per point for proper input circuit operation.
The module will be delivered setup for 6V operation.
The mercury-wetted relay contacts of the output single-shot relay, flip-flop relay, and latching nelay modules are
rated at 2A, 250V (the product not to exceed 100 VA) and require arc suppression. Provision for customermounting (split lug fields F and G) of the appropriate RC filter elements for arc suppression for each circuit is
provided on the W400 and W402 Modules.
In applications where it is desired to demultiplex an output signal, the common power module can be used to
distribute this signal to the contacts of a relay output functional module. This eliminates the necessity of jumpering one side of all the output contacts together.
4-71

BIT 00
VOLTAGE
SCALING
JUMPERS
,...-->---..

4A FUSES

+
BIT 00
JUMPERS

Figure 4-53

BIT 00 ARC SUPRESSION
NETWORK MOUNTING STU OS

Location of Jumpers and Component-Mounting Studs (W402)

W403

SOLID-STATE DRIVER SIGNAL-CONDITIONING 1MODULE

This module is a double-ended module providing the interface between 16 individual points on the M684 FlipFlop Driver or the M686 Single-Shot Driver output modules and field circuits (Figures 4-54 and 4-55)1. Differential pair field wiring from the screw terminals is terminated on a 36-pin connector that connects to the rear of
the module. One wire of each pair connects one side of each field load to the open collector switch on the output module. If only logic levels are required, only this line is needed. The other wire of this pair connects the
opposite end of the load to a positive common power source. This power is customer-supplied and is brought
in to the W403 Module from the BC40C-4 Screw Terminal Assembly, along with the control point pairs. The
positive line is distributed to each of the control point pairs. A common return line for all field loads: is connected to UDC logic ground. Both positive and negative power loads are fused for 4A.

SCREW
TERMINALS

W403

TO FUNCTIONAL
I/O MODULE

GROUND
JUMPER

FIELD+
POWER1---+-1.n-+-~~~

4A
(1OF12 BITS)
08-0694

Figure 4-54 Simplified Schematic Diagram (W403)

4-73

BIT 00
JUMPERS
4A FUSES

GROUND JUMPER

+
BIT 00

JUMPERS

Figure 4-55

Location of Jumpers (W403)

A233
BUFFERED VOLTAGE SIGNAL-CONDITIONING :MODULE

FUNCTIONAL SPECIFICATIONS
Analog Output:

0 to +1 OV at 15 mA max (see below)

Gain Linearity:

-1 ± 0.05%

Zero Input Offset:

6 mV max

Settling Time:

35 µs max to within ± 0.05% of final value with 150 pF load.
50 µs with DAC A633

Power:

+18V ± 0.05V, 45 mA max plus load current
-18V ± 0.05V, 45 mA max

Power is supplied from an external H738A Power Supply and applied through the screw terminals (BC40C Cable
Assembly).

A233

;SCREW
TBRMINALS

,....__,

t--.

0
TP

0
INPUT
FROM
DAC

.J\.,,,-

.-v

A633

OUTPUT

r---

+
:--0-

t--

LOAD

: -0

RETURN

;

J.__.

( 1 OF 4 BUFF AMPS)
11-0997

Figure 4-56 Simplified Schematic Diagram (A233)

DESCRIPTION
The A233 Buffered Voltage Signal-Conditioning Module (Figure 4-56) contains four buffered volitage amplifier
circuits. This module is used as a signal-conditioning module for the A633 DAC Module. The aniiplifiers are
simple inverting type amplifiers with a gain of 1. A current buffer is used to provide up to 15 mA of output
current.

4-75

A twisted-pair cable is recommended to connect the output from the screw terminals to the load. This cable
should be of sufficient wire size to prevent excessive losses along the cable.
DA TA FORMAT (Channel 00)
Digital Input to A633

DAC Voltage from A633

0000
1000
1777

o.ooov

-5.000V
-9.990V

+5.000V
+9.990V

4-76

Voltage Output at Screw Terminals

A234
BUFFERED VOLT AGE SIGNAL-CONDITIONING iMODULE

FUNCTIONAL SPECIFICATIONS
Analog Output:

+1 V to +5V at 15 mA max (see below)

Gain Linearity: .

-0.4 ± 0.05%

Zero Input Offset:

Adjustable to give +1 V out

Settling Time:

35 µs max to within± 0.05% of final value With 1!50 pF load.
50 µs with DAC A633

Power:

+18V ± 0.05V 48 mA max plus load current
-18V ± 0.05V 48 mA max

Power is supplied from an external H738A Power Supply and applied through the screw terminals (BC40C Cable
Assembly).

A234

r----.
REF

COMMON

l--

SCREW
TERMINt!1LS

-"·

......--•

OFFSET

. l l--

:
~

INPUT
•v

FROM
DAC

A633

~
~

OUTPUT

RETURN

:!:.

""<7

LOAD

""'
~

i....--J

( 1 OF 4 BUFF AMPS)
11-0998

Figure 4-57 Simplified Schematic Diagram (A234)

DESCRIPTION
The A234 Buffered Voltage Signal-Conditioning Module (Figures 4-57 and 4-58) contains four buffered voltage
amplifier circuits. This module is used as a signal-conditioning module for the A633 DAC Modu]e. The amplifiers
are inverting type amplifiers with individual offset adjustments. A current buffer is used to provide up to 15 mA
output current.

4-77

A twisted-pair cable is recommended to connect the output from the screw terminals to the load. This cable
shou Id be of sufficient wire size to prevent excessive losses along the cable.
DATA FORMAT (Channel 00)
Digital Input to A633
0000
1000

DAC Voltage from A633

Voltage Output at Screw Terminals

o.ooov

+1.000V
+3.000V
+4.996V

-5.000V
-9.990V

1777

DAC 00

OFFSET
R14

DAC

OFFSET~-

R28

F2
0.5 AMP

0.5 AMP

DAC 02

OFFSET
R42

DAC

OFFSET
R56

Figure 4-58

Location of Adjustments and Fuses (A234)

4-78

A235
BUFFERED CURRENT SIGNAL-CONDITIONING MIODULE

FUNCTIONAL SPECIFICATIONS
Analog Output:

+4 mA to +20 MA into 750.Q max (see below)

Zero Input Offset:

Adjustable to give +4 mA out

Settling Time:

35 µs max to within 0.05% of final value with 150 pf= capacitor across the load. 50 µs with DAC A633

Linearity:

~99.95%

Power:

+18V ± 0.05V 126 mA max
-18V ± 0.05V 46 mA max

Power is supplied from an external H738A Power Supply and applied through the screw terminals (BC40C Cable
Assembly).

A235

SC~EW

TERM NALS

REF
TIP
COMMON

GAIN
FROM
DAC
A633

INPUT
OUTPUT

~I-

LOAD
RETURN

(10F 4 BUFF AMPS)
11-0999

Figure 4-59 Simplified Schematic Diagram (A235)

DESCRIPTION
The A235 Buffered Current Signal-Conditioning Module (Figures 4-59 and 4-60) contain four current source circuits. This module is used as a signal-conditioning module for the A633 DAC Module. The output current is directly proportional to the voltage from the A633 DAC, but is offset by +4 mA. The maximum load which will
not cause saturation is 750.Q.

4-79

DAC Voltage from A633

0000
1000
1777

-5.000V
-9.990V

Current Output at Screw Terminals

o.ooov

+ 4.000 mA
+12.000 mA
+19.984 mA

GAIN
R58
DAC
00

OFFSET
R59
BALANCE
R60
GAIN
R61

DAC
01

OFFSET
R62
BALANCE
R63

F1
-o.5AMP
F2
-0.5AMP
GAIN
R64
OAC
02

OFFSET
R65
BALANCE
R66
GAIN
R67---i

OAC
03

OFFSET----R68
BALANCE
R69

Figure 4-60

Location of Adjustments and Fuses (A235)

4-80

A236
BUFFERED CURRENT SIGNAL-CONDITIONING MOIDULE

FUNCTIONAL SPECIFICATIONS
Analog Output:

+10 mA to +50 mA into 300.n max (see below)

Zero Input Offset:

Adjustable to give +10 mA out

Settling Time:

35 µs max to within 0.05% of final value with 150 pF capacitor across the load. 50 µs with DAC A633

Linearity:

~99.95%

Power:

+18V ± 0.05V 246 mA
-18V ± 0.05V 46 mA

Power is supplied from an external H738A Power Supply and applied through the screw terminals (BC40C Cable
Assembly).

A236

SGREW
TERMINALS

REF
TP
COMMON

GAIN
INPUT
FROM
DAC
A633

OUTPUT

LOAD
RETURN

( 1 OF 4

BUFF AMPS)
11-1000

Figure 4-61

Simplified Schematic Diagram (A236)

DESCRIPTION
The A236 Buffered Current Signal-Conditioning Module (Figures 4-61 and 4-62) contains four current source
circuits. This module is used as a signal-conditioning module for the A633 DAC Module. The outiout current
is directly proportional to the voltage from the A633 DAC, but is offset by +10 mA. The maximum load which
will not cause saturation is 300.n.

4-81

DAC Voltage from A633

Current Output at Screw Terminals

o.ooov

+10.000 mA
+30.000 mA
+49.961 mA

0000
1000
1777

-5.000V
-9.990V

GAIN
R58

OAC

OFFSET

R59

BALANCE
R60

GAIN
R61

DAC
01

OFFSET
R62

BALANCE
R63

0 . 5 AMP

F2
0,5AMP

GAIN
R64

DAC
02

OFFSET
R65

BALANCE
R66

GAIN

R67

DAC

OFFSET
R68

GAIN

R69

Figure 4-62

Location of Adjustments and Fuses (A236)

4-82

4.7 FIELD WIRING
There are certain wiring procedures and practices that are recommended for the proper installation of all lead-in
wires connecting remote analog and digital devices with the computer. Deviations from this procedure: can introduce unpredictable system errors or inaccuracies because of variables that are unknown and/or ulhcontrollable.
All basic computer accuracies are thus given at the connection cabinet terminals and any inaccuracies c:aused by
lead-in wires must be considered separately.
The field input and output interface circuits have been inherently designed to cope with the majority of adverse
industrial plant environments. The design features include such things as:

Current rather than voltage sensitive digital inputs for greater immunity to induced voltages.

DC isolation between the UDC bus and the individual inputs and outputs.

Although these features allow the user more freedom in his lead-in cable installation, certain speaial precautions,
for the various types of inputs and outputs, are still necessary for optimum operation.
4.7 .1 Wire Specifications
All signal wiring should be individual twisted pairs containing about 6 to 12 twists per foot. Cables should be
composed of concentric twisted pairs with all lays and pairs twisted in the same direction for greater flexibility.
Recommended wire sizes, contingent upon compliance with specifications for maximum line impedance and
voltage drop, are:

a.
b.

No. 16 AWG (4.0 ohms per 100 ft) or equivalent.
No. 18 AWG (6.4 ohms per 1000 ft) or equivalent.
No. 20 AWG (10.1 ohms per 1000 ft) or equivalent.

Stranded wire should be used for flexibility. Tinned copper wire is recommended for oxidation resistance. The
insulation resistance between conductor and from either conductor should not be less than 500 megohms per
1000 ft (PVC).
The dielectric strength of the cable and conductor insulation should not be less than 600V. The lmulti-paired
cable should be jacketed in polyvinyl, polyethylene or Teflon at least 0.034-in. thick for mechan~cal prntection.
Teflon should be specified for areas where the ambient temperature is expected to be between 105°C (221°F).
and 200°c (424°F).
4.7 .1.1 Analog Output Wiring - Analog output signals are normally current or high-level voltag~ signals so that
most of the precautions necessary for low-level analog signals can be relaxed. Analog output sigrial wires should
be run as twisted pairs and may be run in multi-pair cable if their destinations are common.
4.7.1.2 Digital Input Wiring - Digital input signal wires can be run as twisted pairs and in multhpaired cables.
Digital input signals can also utilize 12 input signal wires and one common, as long as they are closely associated
or twisted together in the same cable. Digital input cables should not be run near ac power cabl~s. Digital input
wires can be mixed with digital output wires in the same cable tray. Digital input wires should nbt be mixed
with high-level digital output wires in the same cable.
Pulse type (counter) input wires and edge sensing interrupt type (alarm) input wires should be run as twisted
pairs in a multi-paired digital input cable.

4-83

4.7.1.3 Digital Output Wiring - Digital output signal wires should be run as twisted pairs in multi-paired cables
containing no analog wires.
Contact closure type (relay) output wires should be run separate from other input and output signal wires in
electrostatically shielded multi-twisted pair cables because of the noise producing characteristics of the devices
Oamps and relays) that are frequently powered from these outputs. Contact closure type signals are usually
made and broken quite suddenly, which can cause high voltage inductive spikes to appear on these lines and any
others in close proximity if the driven inductive devices do not have proper suppression.
It is strongly recommended that all ac devices and de inductive devices incorporate arc suppression circuits to
limit noise spikes to less than 2V above the signal level being switched.
Stepping motor driver output wires can be run as twisted pairs or as four wires and a common as long as they are
in close proximity or twisted together in the same cable.
4.7.1.4 Grounding - Ideally, all grounds should be separated into categories such as power grounds, logic
grounds, digital grounds, analog grounds and relay grounds, and each category of grounds should be run directly
to the ground electrode and tied to it at one point only. Practically this is not very feasible so that divisions can
be made only as to analog grounds and nonanalog grounds.
4. 7 .2 I nstal lat ion
Field wiring can be brought into the UDC system's cabinets either from the top or bottom. If the field wiring is
brought in through conduit, a space should be provided so that the conduit does not touch the IDACS cabinet.
4.7.2.1

Top Entry - A clamping plate is provided on the top entry version of the cabinet so the leads can be

securely clamped to the cabinets. Clamps are not provided by DEC. The plate must be drilled and the clamp
secured by a nut, bolt, and lock washer.
The H964MA allows the screw terminals to be set back to accommodate larger and larger bundles of leads. The
mounting screws are set on 2-in. centers. It is recommended that the screw terminals be set back 2 in. for each
complete file implemented.
4.7.2.2 Bottom Entry - No provision is made for clamping bottom entry cables. As in the top entry, the
H964MA must be set back 2 in. per file.
4.7.2.3 Cable Routing Lengths - The distance from 2 in. above the cabinet to the first bend is 12 inches. The
cable must run 15 in. toward the back of the cabinet to the second bend. It then runs vertically down 6 in. to
the bottom of the first screw-terminal assembly. Sixteen inches should be allowed to run and dress the longest
lead. The screw terminals are mounted on 1-3/8 in. centers, so incremental increases of 1-3/8 in. must be planned
for running additional leads.
4.7.2.4 Breakouts - A 2-in. stand-off is provided at each terminal'assembly of the mounting screws. These
posts provide a means for anchoring the cable and tying off the lead breakouts to the screw terminal assemblies.
4.7.2.5

Rear Terminal Assemblies - An additional 10 in. is added to the run following the first bend to get to

the back of the cabinet. Then, a 40-in. vertical run is made to the first breakout. Note where cables of large
diameter are formed, it is necessary to add several inches extra for the radius of each bend.

4-84

4.7.3 Screw-Terminal Markers
Each screw-terminal assembly has 17 pairs of screw terminals. Marker strips are supplied with each UDC System
to identify each screw-terminal pair. Up to three types of marker strips (in two pieces) can be suJ!>plied, one
type for each class of 1/0 modules being utilized. The classes are:

a.
b.

Digital 1/0
DAC
Counter

The digital 1/0 class contains the following modules: W730, W732, W740, W742, M684, M686, M802, M804, and
and M806. The marker strips to be used for these modules are shown below.

LEFT SIDE

~l- "+ l=
0

COMMON FIELO
POWER+

LcoMMON FIELD
POiWER-·

"+ 1-·°+ 1-"+I
RIGHT SIDE

018- 07'12

The+ and - terminal markings for each bit refer to the input polarity of the W730, W732, W740, and W742
Modules. For mercury-wetted relay contact output modules (M800 series), the marked polarity must also be observed if an arc suppression circuit is installed.
The marker strips for DAC Module A633 are shown below.

-18V

+5V

I§ -1 + -1
+ 5V

+18V

I+-· I+-v-1

LEFT SIDE

[CJ 1-

00
TP

-1-

01
TP

-1-

02
TP

~
LOAD

LOAD

~
LOAD

RIGHT SIDE
08-0743

4-85

The marker strips for Counter Module W734 are shown below:

RETURN

FOR

P, C AND S OUTPUTS

1
CONT

+
I
EXTERNAL COUNT
ENABLE INPUT

I-? I

CONTACT INPUT

VOLTAGE

IN PUT

LEFT SIDE

I? 1!1 ·I lfi I

I~· I

PULSE
OUTPUT

CONTROL
OUTPUT

SIGN
OUTPUT

W734
COUNTER

RIGHT SIDE
01-0744

4-86

CHIAP'TER 5
MAINTENANCE

5.1

GENERAL

The maintenance procedures presented in this chapter are limited to those required for maintaining and testing
the UDC8 equipment bays. Procedures for maintaining and testing the PDP-8 Computer System are contained
in the PDP-8 Maintenance Manual. The maintenance philosophy to be followed for the UDC8 should be preventive in nature; that is, an optimum amount of preventive procedures performed at a routine schedule will eliminate many costly equipment breakdowns and forecast impending failures long before they occur . Whim a failure
does occur, the modular design of the UDC8 minimizes repair and downtime. To locate a specific module or file
unit, refer to the channel/system unit identification chart on the rear of the logic cabinet.

5.2 PREVENTIVE MAINTENANCE
Since the UDC8 peripheral contains no special mechanical devices, only standard computer syst~m maintenance
procedures are required to ensure reliable operation of the equipment. Failures encountered in the UDC8 should
be recorded in the established system maintenance log for future reference. Regular entries in the maintenance
log of maintenance performed, troubles encountered, and corrective measures taken, can serve as a powerful tool
in maintaining system reliability. A mechanical inspection (diagnostic referenced in Paragraph 1J6) and voltage
checks should be performed at regular intervals to verify proper operation of the UDC8. Voltages and their required tolerances are listed in Table 5-1. Since each equipment bay has its own H7400 Power Supplies, the voltage checks should be performed for each bay. Cooling air filters at the top of the logic cabinet should be checked
and cleaned as necessary.

5.3 CORRECTIVE MAINTENANCE
5.3.1 General
The simplicity of the universal digital controller and the logic description provided in this manua[I, along with the
results of the diagnostic tests, normally permit the use of standard troubleshooting techniques for isolating a malfunction quickly and efficiently.
Table 5-1
H740D Voltage Tolerances
Voltage

Tolerance

+5V
+15V (not used)
-15V (UDC8-N only)

±0.250V (input to G729 under full load)
±1.0V

5-1

A special UDC Field Tester has been developed to aid the DEC Field Service Engineer in isolating and correcting
UDC problems. The tester is used in conjunction with the standard UDC diagnostic (UDC8-EX) and consists of
lamps and switches used to test UDC output and simulate field inputs. It also includes cables that bypass the
screw terminals and plug directly into the signal-conditioning modules.
CAUTION
In all cases, when troubleshooting the UDC, disconnect screw terminal wiring from signal-conditioning
modules, to eliminate hazardous field voltages.
For economical maintenance under most conditions, replace the inoperative module with a spare module, and
return the defective module to DEC for repair or replacement.
NOTE
Be sure that the jumpers in the replacement module
are set up to reflect those in the defective module.
Recommended spare modules are listed in Table 5-2, and recommended component spares are listed in Table 5-3.

5.3.2 Test Equipment Required
Maintenance activities for the UDC8 require standard test equipment and special materials as listed in Table 5-4,
and standard hand tools, test cables, and probes.

5.3.3 H740D Power Supply Adjustment
The +5V source should be adjusted for 5 ± 0.250V under full-load conditions. Use the jumper connections on
the rear of any G729 Module for access points. Figure 5-1 shows the location of the +5V control.
Table 5-2
Recommended Module Spares
Module Type

Modules

Quantity

A233
A234
A235
A236
A633
G729
M100
M101
M102
M103
Ml 11
M112
M113
M115
M169

0-10V DAC Output*
+1 to +5V DAC Output*
+4 mA to +20 mA DAC Output*
+10 mA to +50 mA DAC Output*
DAC*
X, Y Selector
Bus Data Interface**
Bus Data Interface**
Device Selector**
Device Selector**
Inverter
NOR Gate
Ten 2-lnput NANO Gates
Eight 3-lnput NANO Gates
Gating Module

*If more than ten of any one of these modules are utilized in the system, then one additional spare should be stocked.
**One or the other depending upon positive or negative bus.

(continued on next page)
5-2

Table 5-2 (Cont)
Recommended Module Spares
Modules
General-Purpose Flip-Flops
Dual-Delay Multivibrator
Dual Integrating-One-Shot
Variable Clock
1/0 Bus Receiver
Pulse Amplifier
Bus Driver
Bus Driver
12-Bit Flip-Flop Relay Driver*
12-Bit Single-Shot Relay Driver*
12-Bit Latching Relay*
12-Bit Flip-Flop Relay*
12-Bit Single-Shot Relay*
Bus Receiver-Address Decoder
Bus Connector
Bus Terminator
Isolated Power Cable Board*
Common Power Cable Board*
Relay Driver Power Cable Board
12-Bit Contact Sense (Relay)*
12-Bit Contact Interrupt (Relay)*
12-Bit Contact Sense (Solid State)*
12-Bit Contact Interrupt (Solid State)*
I /0 Counter*

Module Type

Quantify

M206
M302
M307
M401
M510
M602
M623
M624
M684
M686
M802
M804
M806
M851
M935
M942
W400
W402
W403
W730
W732
W740
W742
W734

*If more than ten of any one of these modules are•utilized in the system, then one additional spare should be;
stocked.

Table 5-3
Recommended Component Spares
Components

DEC No.

Ol!Jantity

Relay, Quad Form B (used on W730)
Relay, Quad Form C (used on W732)
Mercury-Wetted Latching Form C Relay (used on M802)
Mercury-Wetted Form C (used on M804, M806)
Pig-Tail Fuses, 4A 3AG
Optically Coupled Isolator
DEC 3568 Transistor (M684 and M686)

12-10116-0
12-10172-0
12-09672-1
12-09757-1
90-07219-2
19-10845
15-02937

2
2
2
2

5
2
2

5.3.4 Scanner Clock Adjustment
Scanner Clock in slot E09 (Module M401) should be adjusted to a period of 1.0 µs (1.0 MHz) by adjusting the
trimpot on the module while viewing the waveform at pins E09D2 or E09E2 (Figure 5-2).

5-3

Table 5-4
Test Equipment Required
Equipment

Manufacturer

Multimeter
Oscilloscope
Probe (2)
X10 Probe (2)
Module Extender*
Test Set
Service Kit*

Triplett or Simpson
Tektronix
Tektronix
Tektronix
DEC
DEC
DEC

Designation
Model 630-NA or 260
Type 543 or equivalent
P6010
P6008
Type W982
Optional
For single-shot timing adjustments

*Provided with each system.

_Fl
D

+5 AND+15V _ _
Fl (15AMP)

014-4----..:...._-+15V R35

-15V F2

(5A)~

+5V R50

0 • 4 - - - - - ' - - - - 1 5 V R26

1:-1005

Figure 5-1

H740D Power Supply Fuses and Adjustment Controls

~--1.0 µs

·I

____,JI- ------...
f4-5o ns-eoj
08-0691

Figure 5-2 Scanner Clock Waveform

5.3.5 Bus Clock Signal Adjustments
System clock (CLK 00) in slot F07 (Module M401) can be adjusted over the range of 175 Hz to 1.75 kHz by
adjusting its trimpot while viewing the waveform at pin F06H1. Clock CLK 01 in slot FOB (Module M401) can
be adjusted over the range of 1.75 kHz to 17.5 kHz while viewing the waveform at pin F06M1. For testing W734
type modules, these clocks must be set to 1.0 kHz and 16 kHz, respectively, for correct operation of the W734
Module. After the test these clocks should be reset to their original setting.

5-4

CH~P1rER 6

ENGINEERING DRAWrlNGS

6.1

GENERAL

This chapter lists DEC block schematics and cabling diagrams that are referenced in other chapter~ of this
maintenance manual (Table 6-1 ). These drawings are contained in the print set and Volume 11 of 'this manual,
and provide detailed information about the logic and wiring of the UDC8 peripheral.
Table 6-1
UDC8 Engineering Drawings
Title

Drawing Number
A-ML-IDAC-0
A-PL-IDAC-0-1
D-AR-IDAC-0-0
A-M L-UDC8-N
A-M L-UDC8-P
A-P L-U D C8-0-0
D-D l-UDC8-0-1

Industrial Data Acquisition and Control
Parts List
IDAC Arrangements
Digital Input/Output Sub-System (NEG)
Digital Input/Output Sub-System (POS)
Digital Input/Output Sub-System (Parts List)
Drawing Index List (UDC8)

A-ML-DD01-N
A-ML-DD01-P
A-PL-DD01-0-0
C-D l-DD01-0-01
D-AD-7006825-0-0
A-PL-7006825-0-0
D-MU-DD01-0-02
A-PL-DD01-0-02
D-BS-DD01-0-03
D-BS-DD01-0-04
D-BS-DD01-0-05
D-BS-DD01-0-06
D-BS-DD01-0-07
D-BS-D DO 1-0-08
D-IC-DD01-0-10
K-WL-DD01-0-09 (Complete)
A-M L-DD02-0
A-P L-DD02-0-0
C-D l-DD02-0-01
D-AD-7006838-0-0
A-P L-7006838-0-0

Control and Interface (NEG)
Control and Interface ( POS)
Control and Interface (Parts List)
Drawing Index (DD01)
Wired Assembly (DD01)
Wired Assembly (Parts List)
Module Utilization List
Module Utilization List (Parts List) (NEG ahd POS)
UDC Address Scanner and Register
Change of State (COS) Gates and Register
UDC Digital Input Multiplexer
Device Select and Input Interrupt Generatoir
UDC Bus Drivers and Receivers
Bus Receivers and Address Decoders (DD01)
1/0 Connectors
Wire List (DD01)
System Unit
System Unit (Parts List)
Drawing Index (DD02-0)
Wired Assembly ( DD02-0)
Wired Assembly (Parts List)
(continued on next page)

6-1

Table 6-1 (Cont)
UDC8 Engineering Drawings
Drawing Number

Title

D-MU-DD02-0-02
A-PL-DD02-0-02
D-BS-D D02-0-04
K-WL-DD02-0-03 (Complete)

Module Utilization List
Module Utilization List (Parts List)
Bus Receivers and Address Decoders
Wire List ( DD02-0)

E-CS-A233-0-1
D/E-CS-A234-0-1
D/E-CS-A235-0-1
D/E-CS-A236-0-1
D-CS-A633-0-1
B-CS-G729-0-1
B-CS-G772-0-1
ASP-H738-A-O
C-CS-M 100-0-1
B-CS-M101-0-1
D-CS-M 102-0-1
B-CS-M 103-0-1
B-CS-M 111-0-1
B-CS-M112-0-1
B-CS-M113-0-1
B-CS-M115-0-1
C-CS-M 169-0-1
B-CS-M206-0-1
B-CS-M302-0-1
C-CS-M304-0-1
B-CS-M307-0-1
B-CS-M401-0-1
C-CS-M510-0-1
B-CS-M602-0-1
C-CS-M623-0-1
C-CS-M624-0-1
C-CS-M633-0-1
D-CS-M684-0-1
D-CS-M686-0-1
D-CS-M802-0-1
D-CS-M804-0-1
D-CS-M806-0-1
C-CS-M851-0-1
B-CS-M903-0-1
C-CS-M942-0-1
D/E-CS-W400-0-1
D/E-CS-W402-0-1
D-CS-W403-0-1
C-CS-W730-0-1
D-CS-W732-0-1
D-CS-W7 40-0-1
D-CS-W7 42-0-1
D-CS-W734-0-1
B-CS-849A-0-1
D-CS-5409728-0-1

OV to +10V Output Buffer Amplifier
+1 V to +5V Output Buffer Amplifier
4 mA to 20 mA Current Output Buffer
10 mA to 50 mA Current Output Buffer
4-10 Bit D/A Converter
X-Y Jumper Card
Power Connector Module
DAC Option Power Supply
Bus Data Interface
Bus Data Interface
Device Selector
Device Selector
Inverter
NOR Gate
10 2-lnput NAND Gates
8 3-lnput NAND Gates
Gating Module
Six Flip-Flops
One Shot Delay
One Shot Delay
Integrating One Shot
Variable Clock
1/0 Bus Receiver
Pulse Generator
Bus Driver
Bus Driver
Bus Driver
12-Bit Flip-Flop Relay Driver M684
12-Bit Single-Shot Relay Driver
Latching Relay Output Driver
12-Bit Flip-Flop Relay Module M804
12-Bit Single-Shot Relay M806
Bus Receiver Addr Decoder
Connector, Flat Mylar
Bus Terminator
Isolated Power Cable Board W400
Common Power Cable Board W402
Relay Driver Power Cable Board W403
12-Bit Contact Sense (Relay) W730
12-Bit Contact Interrupt ( Relay).W732
12-Bit Contact Sense (Solid State) W740
12-Bit Contact Interrupt (Solid State) W742
Counter Module
Power Control
Regulator Board for H740D

6-2

UDC8 UNIVERSAL DIGITAL CONTROL
SUBSYSTEM MAINTENANCE MANUAL
DEC-08-HZDC-B

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