Digital PDFs

EK-VTX78-TM-002

January 1978

137 pages

Original

8.4MB

Document:	PDP-8 DECstation Technical Manual
Order Number:	EK-VTX78-TM
Revision:	002
Pages:	137
Original Filename:	http://bitsavers.org/pdf/dec/pdp8/cmos8/EK-VTX78-TM-002.pdf

OCR Text

DECstation technical manual

•
EK-VTX78-TM-002

digital equipment corporation • maynard, massachusetts

1st Edition, January 1978
· 2nd Printing (Rev), March I 9'7~

The information in this document is subject to change without notice and
should not be construed as a commitment by Digital Equipment Corporation.
Digital Equipment Corporation assumes no responsibility for any errors that
·may appear in this document.

This document was typeset on DIGITAL's DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment Corporation:
DEC
DECCOMM
D ECsystem-1 0
DECSYSTEM-20
DECtape
DEC US
DIGITAL

MASSBUS
PDP
RSTS
TYPESET-8
TYPESET-11
UNIBUS
DECstation

CONTENTS
Page
CHAPTER 1

INTRODUCTION

1.1
1.2

PURPOSE ........................................................................................................... 1-1
GENERAL .......................................................................................................... l-1

CHAPTER 2

THEORY OF OPERATION

2.1
2.2
2.2.1
2.2.1.1
2.2.1.2
2.2.1.3
2.2.1.4
2.2.1.5
2.2.1.6
2.2.1.7
2.2.1.8
2.2.2
2.2.2.1
2.2.2.2
2.2.2.3
2.2.2.4
2.2.3
2.2.3.1
2.2.3.2
2.2.3.3
2.2.3.4

OVERALL SYSTEM DESCRIPTION ............................................................... 2-1
DETAILED CIRCUIT ANALYSIS .................................................................... 2-6
Microprocessor ............................................................................................ 2-6
CPU ..................................................................................................... 2-6
Main Memory .................................................................................... 2-16
Panel Memory .................................................................................... 2-19
Real Time Clock ................................................................................. 2-19
Floppy Disk Drive Interface ............................................................... 2-24
MR78 Interface .................................................................................. 2-27
Serial Line Units ................................................................................. 2-28
Parallel 1/0 ........................................................................................2-37
Keyboard/Video Display ........................................................................... 2-37
Data Paths, Memory, and Decoder Circuits ........................................ 2-37
ROM, UART, and Timing Circuit.. .................................................... 2-55
Keyboard Circuits .............................................................................. 2-58
Microprogramming ............................................................................ 2-59
DC Power Supply ....................................................................................... 2-65
20 kHz Oscillator ................................................................................ 2-65
Pulse Width Modulator ...................................................................... 2-65
Inverter .............................................................................................. 2-65
Short Circuit Protection ...................................................................... 2-65

CHAPTER 3

MAINTENANCE

3.1
3.2
3.2.1
3.2.2
3.2.2.1
3.2.2.2
3.2.2.3
3.2.2.4

MAINTENANCE PHILOSOPHY ...................................................................... 3-1
TROUBLESHOOTING ................................................ .-..................................... 3-1
Troubleshooting Procedures ......................................................................... 3-1
MR78-BB ODT Package .............................................................................. 3-1
Starting the ODT ................................................................................ 3-18
Running the Reader ............................................................................ 3-18
ODTNotes ......................................................................................... 3-21
Overlaying ODT ................................................................................. 3-22

lll

CONTENTS (Coot)
Page
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
3.4
3.4.1
3.4.1.1
3.4.1.2
3.4.1.3
3.4.1.4
3.4.1.5

SUBASSEMBLY REMOV ALAND REPLACEMENT ............. , .................... 3-23
Base Assembly ............................................................................................ 3-23
Processor /Memory Module ................... ;.................................................... 3-23
1/0 Distribution Panel ....... ;....................................................................... 3-27
RUT and DP Modules ................................................................................ 3-27
Power Supply Assembly .....................-........................................ ;......_.......... 3-28
Monitor Board ........................................................................................... 3-32
Keyboard Assembly ............................................................... ;................... 3-32
CRT Assembly ............................................................................................ 3-34
ALIGNMENT AND ADJUSTMENT PROCEDURES ................................... 3-34
Video Display Adjustments ........................................................................ 3-34
Height ................................................................................................ 3-36
Width ................................................................................................. 3-36
Vertical Linearity ................................................................................ 3-36
Focus ................................................................................................. 3-36
Processor Board DC OK Adjustment ................................................. 3-37

APPENDIX A

SYSTEM CHARACTERISTICS

A.l
A.2

PHYSICAL ........................................................................................................ A-1
FUNCTIONAL ................................ ;.................................................................. A-1

APPENDIX B

MR78 PROGRAM LOADER

B.l
B.2

GENERAL ......................................................................................................... B-1
THEORY OF OPERATION .............................................................................. B-2

APPENDIX C

1/0 DISTRIBUTION PANEL PIN ASSIGNMENTS

APPENDIX D

PRSOl CABLE

APPENDIX E

APT AUTOMATIC TEST SYSTEM CONNECTIONS

APPENDIX F

FIELD REPLACEABLE UNITS (REPAIRS)

FIGURES
Figure No.

1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2~13

2-14
2-15
2-16
2-:17
2-!18
2-:19
2-20
2-21
2-22
2-23
2-~4
2-25
2-26
.2-27
2-28
2-29
2-30
2-~1

2-32

Title

Page

DECstation: Intelligent Terminal Configuration .................................................. 1-2
Typical Stand-Alone Computer Configuration ...................................................... 1-3
DECstation Block Diagram ................................................................................. 2-2
Keyboard/Video Display Block Diagram ............................................................. 2-3
7X7 Character Matrix .......................................................................................... 2-4
Display Cycle Flow Diagram ................................................................................ 2-5
DC Power Supply Block Diagram ........................................................................ 2-7
CPU Block Diagrarri ..................................................... ,...................................... 2-9
CPU Timing Diagram ........................................................................................ 2-15
Main Memory Block Diagram ............................................................................. 2-16
Read/Refresh Timing Diagram .......................................................................... 2-17
Read/Write Timing Diagram ..................................... ~ ....................................... 2-18
Panel Memory Logic Flow Diagram ................................................................... 2-21
Panel Memory Block Diagram ........................................................................... 2-23
Real Time Clock Block Diagram .................................... ;...........·........................ 2-23
Floppy Disk Drive System Interface Block Diagram ........................................... 2-25
Floppy Disk Drive System Interface Timing Diagram ......................................... 2-26
MR 78 Interface Block Diagram ...................................................... : .................... 2-27
SLU and Control Circuits Block Diagram .......................................................... 2-29
U ART Transmit Function Timing Diagram ....................................................... 2-33
U ART Transmit Circuits Block Diagram ........................................................... 2-35
UART Receiver Timing Diagram ....................................................................... 2-39
U ART Receiver Circuits Block Diagram ............................................................ 2-41
Parallel 1/0 Interface Block Diagram ................................................................. 2-45
RAM Address Mapping .·.......................................................................... :......... 2-49
Character Display Timing .................................................................................. 2-50
ROM Word Division .......................................................................................... 2-51
Cycle Timing Diagram ....................................................................................... 2-54
Display ROM Organization and Selection .......................................................... 2-56
Display Basic Timing Circuits ............................................................................. 2-57
Cathode Ray Tube ............................................................................................. 2-58
Scratchpad Memory ........................................................................................... 2-61
Microprogram Flow Diagram ............................................................................ 2-63
Keyboard Entry Flow Diagram .......................................................................... 2-64

FIGURES (CONT)
Figure No
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
B-1
B-2
C-1
D-1

Title

Page

Guide to Troubleshooting Procedures .................................................................. 3-2
Intensity Control and Fuse Locations ................................................................... 3-3
High Voltage Discharge Locations ....................................................................... 3-4
Anode Clip Locations .......................................................................................... 3-5
Function and Baud Rate Switches ........................................................................ 3-7
Jumper W7 Location ............................................................................................ 3-9
Short Raster Indication ...................................................................................... 3-11
Narrow Raster Indication ................................................................................... 3-11
Short Character Indication ................................................................................. 3-13
Thin Character Indication .................................................................................. 3-13
Uneven Character Indication .............................................................................. 3-13
Uneven Lines Indication ...................................................................................... 3-13
Illegal Characters Indication ............................................................................... 3-15
A23002B4- ROM Chip Location ....................................................................... 3-15 ·
Random Character Indication ............................................................................ 3-15
Distorted Character Indication ........................................................................... 3-17
Tilted Raster Indication ...................................................................................... 3-17
Enlarged and Fuzzy Characters Indication ......................................................... 3-17
Base Assembly Removal and Replacement ......................................................... 3-24
Processor /Memory Module Removal and Replacement ..................................... 3-25
Memory Board Removal and Replacement ........................................................ 3-26
Option Panel Removal and Replacement. ........................................................... 3-27
RUT and DP Module Removal and Replacement .............................................. 3-29
Power Supply and Monitor Board Cover Removal and Replacement.. ................ 3-30
Power Supply and Monitor Board Removal and Replacement. ........................... 3-31
Keyboard Assembly Removal and Replacement.. ................ ,.............................. 3-33
CRT Assembly Removal and Replacement.. ....................................................... 3-35
Alignment Control Adjustment Locations .......................................................... 3-36
DC OK Adjustment Location ............................................................................. 3-37
MR 78 Program Loader ....................................................................................... B-1
MR 78 Program Loader Block Diagram ............................................................... B-2
IjO Distribution Panel Cabling Diagram ............................................................. C-1
PRS01 Cable ....................................................................................................... D-1

TABLES
Table No.
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
3-1
3-2
3-3
3-4
3-5
3-6
B-1
C-1

Title

Page

Related Documentation ........................................................................................ 1-1
CPU Pin Assignments ........................................................................................ 2-11
Control Line Functions .; .................................................................................... 2-13
Real Time Clock Instructions ............................................................................. 2-23
Function Codes for LCD lOTs ........................................................................... 2-25
Baud Rate Selection (SLU 2 and SLU 3) ............................................................. 2-31
SLU Device Codes ............................................................................................. 2-31
SLU Signal Functions ........................................................................................ 2-42 '
Parallel 1/0 Interface Signal Functions ............................................................... z-.::'47
Command List ................................................................................................,. .. 2-51
Instruction Time States ....................................................................................... 2-55
Power On Troubleshooting Procedure .................................................................. 3-3
Start Up Troubleshooting Procedures ................................................................. 3-10
Program Loading Troubleshooting Procedures ................................................... 3-10
Operational Troubleshooting Procedures ........................................................... 3-11
Summary of ODT Commands ............................................................................ 3-19
ODT and Binary Loader ..................................................................................... 3-22
Program Selection Jumper Configurations ........................................................... B-3
1/0 Distribution Panel Pin Assignments .............................................................. C-2

vii

CHAPTER l
INTRODUCTION

1.1 PURPOSE
This manual will help you isolate and repair DECstation equipment malfunctions. It will also be
helpful when interfacing the DECstation with systems and devices other than those specifically designed for this system.
NOTE
Although references are made to optional devices
throughout this manual, appropriate manuals (Table
1-1) for these devices must be consulted for detailed
operating and troubleshooting information.

Table 1-1

Relattld Documentation

Document

Document No.

DECstation User's Guide (hardware)
DECstation User's Guide (software)
DECstation Technical Manual
VT78 MOS Memory Diagnostic
VT78 CPU Diagnostic
4K-32K PDP8A Processor Exerciser
RX8 /RXO 1 Diagnostic Programs
RX8/RX01 Data Reliability Exercise Program
LA 180 Printer Diagnostic
LQP-8 Printer Diagnostic

EK-VTX78-UG-001
DEC-S8-0878A-A-D
EK-VTX78-TM -001
MAINDEC-08-DKVTA-A -D
MAINDEC-08-DKVTB-A-D
MAINDEC-08-DJEXC-B-D
MAINDEC-08-DIRXA-D D
MAIND EC-08-DIRXB-ED
MAINDEC-08-DILAC-B-D
MAINDEC-08-DHLQA-B -D

1.2 GENERAL
The DECstation can be an intelligent terminal in a distributed data processing network or a stand~
alone computer. Figures 1-1 and 1-2 show typical intelligent terminal and stand-alone system configurations.

As an intelligent terminal, the minimum system configuration includes the VT78 terminal and an
external program loading device. Programs can also be loaded into the system from a host computer.
As a stand-alone computer, the DECstation has a mass storage device such as a floppy disk drive
system. Both configurations, intelligent terminal and stand-alone system, may have impact printers for
hard copy.

1-1

The VT78 terminal combines the functions of a conventional I/0 keyboard/video display with those
of a sophisticated minicomputer to form a complete computer system within a terminal. It has a full
typewriter-style keyboard, capable of generating both upper- and lower-case characters in ASCII code,
and a 19-key auxiliary keypad. The video display can show 24 lines of 80 characters. The system
utilizes direct cursor addressing.
The processor, located on the processor·module, controls all of the computer functions including those
of the random access MOS 16k word (32k byte) memory. The processor module also contains interface
circuits (see Chapter 2) which process· serial and parallel data. This permits the addition of peripheral
devices via connectors on the I/0 distribution panel (rear of terminal).

MA-0271

Figure 1-1

D ECstation: Intelligent Terminal Configuration

1-2

Ml-0 736

put er Con
Figure 1-2 Typical Stand-Alone Com

1-3

figuration

.•

CHAPTER 2
THEORY OF OPERATION

2.1 OVERALL SYSTEM DESCRIPTION
The VT78 terminal (Figure 2-1) has three major functional components: the microprocessor, the keyboard/video display, and the de power supply.
The processor is a 12-bit, fixed word length, parallel transfer computer using two's complement arithmetic. The processor contains a CPU, a 16k word main memory, a panel memory, an MR78 program
loading device interface circuit, a real time clock, and four peripheral I/0 interfaces.
The system operation is started by the application of prime power to the de power supply initiating the
power-up sequence. Upon completion of the power-up sequence, the diagnostics (resident-in-panel
memory) are performed to verify that the major system components are operating correctly. If there is
a malfunction within the system, the panel memory will issue a halt message and provide general status
information. Two indicators (DC OK and CPU OK), located at the rear of the terminal, also provide
status information.
The panel memory has 256 words of readjwrite Random Access Memory (RAM) for variable storage
and a 1k Read Only Memory (ROM). The ROM contains the resident diagnostics, an MR 78 pseudopapertape loader, and an RX78 bootstrap loader.
Program loading is initiated by momentarily pressing the START switch. This causes the panel memory to select the appropriate program loading device to load its program into main memory.
There are two program loading devices available with the DECstation. One is the MR78 and the other
is the floppy disk drive system. The MR78 has priority over the floppy disk drive system when 'the
START switch is pressed. Each device has its own interface. The MR 78 interface is uni-directional,
receiving 8-bit parallel data from the MR 78 in "papertape" format. The floppy disk drive system
interface is bi-directional (i.e., programs may be written or read) and permits system interface with two
RX78 floppy disk drive systems.
Main memory has 48 NMOS dynamic 4k RAM chips organized as 16k 12-bit words. It has three basic
cycles: read-refresh, read-wait, and read-write.
The DECstation has three Serial Line Units (SLUs). The SLU 2 interface permits the processor (using
EIA signaling levels) to communicate with any full duplex device. It provides error detection at transmission rates ranging from 50 baud to 19,200 baud. Baud rates, word parity, word length, and stop bit
selection are under program control. SLU 3 can communicate with any EIA full duplex device which
handles 8-bit data without parity and only one stop bit. Unlike SLU 2, this interface does not have
error checking but does provide the same baud rate selection under program control. SLU 1 is similar
to SLU 3 with the exception of the EIA signaling levels. It is hardwired directly to the keyboard/video
display IjO.

2-1

---,-I -

--:- -

KEYBOARD/VIDE O DISPLAY

DC
SUPPLY
AND
CONTROL

I
I
I

KEYBOARD

DISPLAY
MEMORY

DISPLAY

I
I
I

HI
I

-- -

_j_

DISPLAY
CONTROL

START
SWITCH

-- ~

MICROPROCESSOR

- - - - - - -1I
r---

PANEL
MEMORY

SLU 1

SLU 2

I
I

CLOCK
SLU 3

CPU

MAIN
MEMORY

PARALLEL
1/0
INTERFACE

DISK
INTERFACE

MR 78
INTERFACE

---- ---- --

1 - - - - 1----

EXTERNAL MR 78

-- --

I
~

I
I
I

_ _j

FLOPPY DISK SYSTEM
PRINTER &
MISC. DEVICES
08·1882A

Figure 2-1

DECstation Block Diagram

2-2

}

MISC
DEVICES

The parallel I/0 interface is a 12-bit bi-directional data port which responds to the instruction sets of
either the LA78 or the LQP78 printers. The parti~ular instruction set is determined by the printer used
and its associated cable.
The keyboard/video display (Figure 2-2) enables the user to communicate with the microprocessor
and control all of the system peripheral devices.
Characters to be displayed on the video screen are transferred to the display via SLU 1 and are stored
in a display RAM in ASCII format. There is a RAM location for each character which appears on the
screen of the video display; hence, the R~M consists of 1,920 7-bit words (24lines of80 characters).

CHARACTER
GENERATOR

VIDEO
SHIFT
REGISTER

TIMING
CHAIN AND
TIME STATE
GENERATOR

MONITOR
I BEAM)
DEFLECTION

CRT

KEYBOARD

UART

TO
MICROPROCESSOR
SLU 1

MEMORY
BUFFER

l
DATA OUT
RAM
ADDRESSES

ROM

l
I

I
X-REGISTER

Y·REGISTER

AC
REGISTER

FLAG

08-1868

Figure 2-2

Keyboard/Video Display Block Diagram

2-3

Characters fetched from the display RAM are applied to a character-generating ROM. The output of
this ROM, which is one horizontal line (7 bits) of the 7x7 character matrix (Figure 2-3), is loaded into a
video shift register. The video shift register is then shifted to provide an intensity signal to the video
display. As the current character is being shifted, the next character is fetched from RAM and applied
to the character generator. This process continues until all 80 characters for the line have been processed. When the end of the line is reached, the RAM X-address {horizontal addres~) is reset to zero.
These steps are repeated until all seven lines of the current set of characters have been placed on the
screen. The display control then advances to the next value of Y for the next line of characters.
Meanwhile, three blank lines (four for 50 Hz units) between the lines of characters (and the cursor) are
placed on the screen.
UPPER CASE

•

• •• ••••

:·····:

= DISPLAYED

•

DOT

•

LCURSOR
0

•

zz*

10
11

•

THIS SCAN IS ON 50 Hz UNITS ONLY;
60Hz UNITS USE 10 SCANS FOR CHAR ROW

LOWER CASE

•••••
• • • • • ••
• • • • • • ••

•
•
•••••
••
• •
••

• ••••••
••• •
•

•••••••

CP-2291

Figure 2-3

7X7 Character Matrix

An internal display processor (not to be confused with the main processor) handles the auxiliary
· functions of:
1.

Updating the X andY registers.

Scanning the keyboard.

Clearing the display.

Storing incoming characters.

Addressing the cursor.

Generating escape sequences.

The timing generator chain and time state generator provide vertical and horizontal deflection signals
for the CRT, as well as providing timing signals to the display processor and display Universal Asynchronous Receiver/Transmitter (UART). (See Figure 2-4.)

2-4

SHIFT VSR TO CRT
(DISP. THE CHAR.)

YES

YES
INCREMENT X REG.
(GET NEXT CHAR
FROM THE RAM)
SCAN A LINE
(CURSOR DISP.
LINE)

LINE SPACING;
PROGRAM CHECK UART,
PROCESSES CHAR.'S, ETC.

SCAN ANOTHER
LINE (DARK
SCREEN)

-::~
r:-1 *SCAN ANOTHER I

I LINE (DARK
CC~EN)

YES

O'sTO X REG
O's TO AC 0, 1, 2
INC. Y REG

RETURN TO TOP
OF SCREEN

o·s ... x REG.
O's..,.AC0,1,2
+1..,.YREG.

THIS LINE PAINTED
ON 50Hz UNITS ONLY.
CP-2306

Figure 2-4

Display Cycle Flow Diagram

2-5

Keyboard data entered by an operator is transferred to the processor under control of the keyboard/video display microprogram. During vertical retrace time, the microprogram checks the keyboard, searching for a typed key. This is performed 60 times each second (50 times each second on 50
Hz units). To do this the program tests the condition of every key in the keyboard. When it finds a
typed key, the ASCII code for the key character is loaded into the UART and transmitted to the VT78
main processor.
At the beginning of every keyboard routine, the program checks the status of the UART. If the UART
is still transmitting the previous entry, the program makes no further test of the keyboard. If the
UART is not transmitting, the. program tests the keyboard to determine if the previously processed
keys are still down. If they are, the program does not process them again. Instead, it exits the keyboard
~outine. When the previously processed keys have been released, the program resumes keyboard testmg.
The de power supply block diagram is shown in Figure 2-5.
Setting the POWER ON jOFF switch to ON causes prime power to be applied to a voltage doubler or
a full wave rectifier, depending on the source of the prime power. When the prime power source is 115
V, the voltage select switch is set to select the voltage doubler circuit. When the prime powersource is
230 V, the selector switch is set to select the full wave rectifier.
Regardless of the prime power source, the resultant voltage doubler or full wave rectifier output will
range from 230 Vdc to 360 Vdc. This is applied to the flyback inverter.
The flyback inverter converts the de input to 20k Hz which is stepped down by a transformer to
produce three output voltages. These voltages are rectified and filtered to become the sources of +5
Vde, -12 Vde, and + 12 Vde for the entire VT78 terminal. Regulators are provided at the -12 Vde and
+ 12 Vde outputs to ensure that these voltages remain within their regulation band of plus or minus
five percent.
The 5 Vdc output is sensed by the control circuit which adjusts the onjoff duty ratio of the inverter to
maintain this output within its five percent regulation band.
The control power circuit provides startup voltages for the control circuit before the inverter is running.
The de power supply output voltages are checked in the main processor module by a voltage comparator which indicates an error by turning off the DC OK indicator, if there are any voltages absent
or out of tolerance. This circuit will prevent any further operation of the DECstation until the malfunction is corrected.
2.2 DETAILED CIRCUIT ANALYSIS
2.2.1

Microprocessor

2.2.1.1 CPU- The entire CPU (Figure 2-6) is contained on a single 40-pin IC. Table 2-llists all of the
pin assignments and provides a brief functional description of each.
The accumulator is a 12-bit register with which arithmetic and logical operations are performed. Data
words may be fetched from memory to the accumulator or transferred from the accumulator for
storage in memory. Arithmetic and logical operations involve two operands, one is held in the accumulator and the other is fetched from memory. The result of the operation remains in the accumulator.
The accumulator may be cleared, complemented, tested, incremented, or rotated under program control. The accumulator also serves as an 1/0. All programmed data transfers pass through the accumulator.
2-6

r--PRIME
POWER
SOURCE
(115/230VAC
60HZ)

•

ON/OFF
SWITCH

1------

POWER
SELECTOR
SWITCH

FULL
WAVE
RECTIFIER

'---

1---

'---

VOLTAGE
DOUBLER

t--

+12 VDC
REGULATOR

I-- +12VDC

-12VDC
RECT.

I--

-12VDC
RI:GULATOR

r- -12VDC

I--FLYBACK
INVERTER

1---

CONTROL
POWER

+12VDC
RECT.

+5VDC
RECT.

+5VDC

CONTROL
CIRCUIT

08-1870

Figure 2-5

DC Power Supply Block Diagram

2-7

RESET, RUN/HL T
DMAREO,CPREQ
INTREQ

ALU&
TRANS
LOGIC

I
MUX

MAJOR
STATE
GEN

PLA

MEMORY & 011
DEVICE
CONTROL

OUTPUT
LATCH

I
PC

MAR

l
MQ

SKP, CO, C1, C2
LXMAR, DEVSEL,
SWSEL, MEMSEL
CPSEL

1
ALU

TEMP

LINK

CRYSTAL
~

TIMING&
STATE
CONTROL

XTA, XTB, XTC, DMAGNT,
INTGNT,IFETCH, DATAF, RUN
WAIT

08-1869

Figure 2-6

CPU Block Diagram

2-9

Table 2-1

CPU Pin Assignments
Function

Active Level

Symbol

Vee

RUN

Indicates the run state of the CPU and
may be used to power down the external circuitry. The ground going transition of this signal is used to detect the
HLT instruction.

DMAGNT

Direct memory access grant; DX lines
are three. state (always low).

DMAREQ

Not used (tied to Vee).

CPREQ

Control panel request, a dedicated interrupt which bypasses the normal device interrupt request structure.

RUN/HLT

Pulsing the RUN /HLT line causes the
CPU to alternately run and halt by
changing the state of the internal
RUNJHLT flip-flop.

RESET

Clears the AC and loads 7777 8 into
the PC. CPU is halted.

INTREQ

Peripheral device interrupt request.

XTA

External coded minor cycle timing,
signifies input transfers to· the processor.

LX MAR

The load external address register is
used to store memory and peripheral
address externally.

WAIT

Not used.

XTB

External coded minor cycle timing,
signifies output transfers from the
processor.

XTC

External coded minor cycle timing is
used with the select lines to specify
read or write operations.

OSC OUT

Supply voltage.

Crystal input to generate the internal
timing (also external clock input).

2-11

Table 2-1

CPU Pin Assignments (Coot)

Symbol

OSC IN

Refer to pin 14 (OSC OUT); also external clock ground.

DXO

DataX; multiplexed data in, data out.

DX1

Refer to pin 16.

DX2

Refer to pin 16.

DX3

Refer to pin 16.

DX4

Refer to pin 16.

DX5

Refer to pin 16.

DX6

Refer to pin 16.

DX7

Refer to pin 16

DX8

Refer to pin 16.

DX9

Refer to pin 16.

GND

Ground.

DXlO

Refer to pin 16.

DX11

Refer to pin 16.

LINK

Link flip-flop.

DEVSEL

Device select for I/0 transfers.

SWSEL

Switch register select for the OR THE
SWITCH REGISTER INSTRUC TION (OSR). OSR is a group 2 operate instruction which reads a 12-bit
external switch register and ORs it
with the contents of the AC.

Control line inputs from the peripheral device during an IJO transfer
(Table 2-2).

Refer to pin 32.

Not used (tied to Vee).

Active Level

Function

2-12

Table 2-1

CPU Pin Assignments (Coot)

Symbol

Active Level

Function

SKP

Skips the next sequential instruction if
active during an 1/0 instruction.

I FETCH

Instruction fetch cycle.

MEMSEL

Memory select for memory transfers.

CPSEL

The control panel memory select becomes active, instead of MEMSEL for
control panel routines. Signal may be
used to distinguish between. control
panel and main memories.

INTGNT

Peripheral device interrupt grant.

DATAF

Data field indicates the execute phase
of indirectly addressed AND, TAD,
ISZ, and DCA instructions so that the
data transfers are controlled by the
data field DF and not the instruction
field (IF), if extended memory control
hardware is used to extend the addressing space from 4k to 16k words.

Table 2-2
C~ntrol Lines

Control Line Functions

Operation

Description

DEV

The content of the AC is sent to the device.

DEY

AC;CLA

The content of the AC is sent to a device
and then the AC is cleared.

ACvDEV

Data is received from a device, ORed
with the data in the AC, and the result is
stored in the AC.

DEV

Data is received from a device and
· loaded into the AC.

*
*

PC+ DEV

Not used.

DEV

Not used.

i
I

* = Don't care.
2-13

The MQ register is a 12-bit temporary register which is program accessible. The contents of the accumulator may be transferred to the MQ register for temporary storage. The contents of the MQ register
can be ORed with the accumulator and the result stored in the accumulator. The contents of the
accumulator and the MQ register can also be exchanged.
The 12-bit memory address register contains the address of the memory location currently selected for
reading or writing. The memory address register can also be used as an internal register for microprogram control during data transfers between memory and peripherals.
The 12-bit program counter contains the address of the memory location from which the next instruction is fetched. During an instruction fetch, the contents of the program counter is transferred to the
memory address register, and the program counter is then incremented by one. When there is a jump
or JMS to another address in memory, the jump or JMS address is set into the program counter.
Branching normally takes place under program control. A Skip instruction increments the program
counter by one, causing the next instruction to be skipped.
The Skip instruction may be unconditional or conditional, depending on the state of the accumulator
andjor the link.
The Arithmetic and Logical Unit (ALU) performs both arithmetic and logical operations-two's complement binary addition, AND, OR, and complement. The ALU can perform a single position rotate
either to the left or to the right. A double rotate is implemented in two single-bit rotates. The ALU can
also shift by three positions to implement a byte swap in two steps. The accumulator is always one of
the inputs to the ALU. However, under internal microprogram control, the accumulator may be gated
off and all ones or all zeros gated in. The second input may be any one of the other registers under
internal microprogram control.
During an instruction fetch, the 3-bit Instruction Register (IR) contains the instructions to be executed
by the CPU. The IR specifies the initial step of the microprogram sequence for each instruction and is
also used as an internal register to store temporary data for microprogram control.
The DX (inputjoutput) multiplexer handles data, address, and instruction transfers between the CPU
and external devices such as memory and peripherals on a time-multiplexed basis.
During an instruction fetch, the instruction to be executed is received from memory via the DX multiplexer and loaded into the IR. The Programmed Logic Array (PLA) is then used for the correct
sequencing of the CPU for the appropriate instruction. After an instruction is completely sequenced,
the major state of the priority network decides whether the system is going to fetch the next instruction
in sequence or service one of the external request lines.
The PLA output latch latches the PLA output, thereby permitting the PLA to be pipelined; it fetches
the next control sequence while the CPU is executing the current sequence.
The CPU circuit timing sequence is shown in Figure 2-7.
The CPU generates all the timing and state signals used in the microprocessor.
The memory and device control unit provides external control signals to communicate with peripheral
devices (DEVESEL), switch register (SWSEL), memory select (MEMSEL), andjor control panel
memory (CPSEL). During 1/0 instructions this unit also modifies the PLA outputs, depending on the
states of the four device control lines. The ALU and register transfer logic provides the control signals
for the internal register transfers and ALU operation.

2-14

CRYSTAL
FREOUENCY·fc

STATES

I I
__j
1---Ts--l
T1

LXMAR

MEM/DEV /SW/CP
SELECT

(0-11) ~=="'--+--"'"''"'~~f-----1====="'"-"'"'"''"''"'~~="'---t-IU.I.~

WRITE DATA
ADDRESS

READ DATA

XTA

XTB

XTC
08-1867

Figure 2-7

CPU Timing Diagram

For memory reference instructions, a 12-bit address is sent on the DX lines. Load External Memory
Address Register (LXMAR) is used to clock an external register (MAR) to store the address information externally. The external address register then contains the device address and control information.
Various CPU request lines are priority sampled if the next cycle is an instruction fetch cycle. The
current state of the CPU is available externally.
For memory reference instruction, the MEMSEL line is active. For 1/0 instructionsthe DEVESEL
line is active. Control lines, therefore, distinguish the contents of the external register as memory or
device address.
External device sense lines (CO, C1, C2, and Skip) are sampled if the instruction being executed is an
1/0 instruction. Control panel MEMSEL, CPSEL, and SWSEL become active low for data transfers
between the CPU and control memory and the switch register, respectively.
The CPU instructions are 12-bit words stored in memory. The CPU makes no distinction between
instructions and data. It can manipulate instructions as stored variables or execute data as instructions
when it is programmed to do so. There are three general classes .of instructions: Memory Reference
Instructions (MRI), Operate Instructions (OPR), and Input/Output Transfer Instructions (lOTs).

2-15

2.2.1.2 Main Memory- Figure 2-8 is a simplified block diagram of main memory and its associated
control circuits. Figures 2-9 and 2-10 show the read/refresh and readjwrite memory cycle timing
sequences.
Data flow between the CPU and memory is controlled by signal XTC which is generated by the CPU.
When XTC is low, memory is in the read cycle. When XTC is high, memory is in th~ refresh, wait, or
write cycle.
During the read portion of XTC, the CPU selects a particular address in memory by placing the
contents of its internal memory address register on the DX lines. When a valid address is present on
the DX bus (lines DXOO through DX05) LXMAR goes high-loading the external 12-bit memory
address register and the 6-bit row latches within the memory chips. The row latches are loaded with the
high order bits (0 through 5). Approximately 270 ns later, the contents of the memory address register
(MAR 6 through 11) are loaded into the memory chip column address. When MEMSEL is pulsed
high, it clocks the read flip-flop, gating memory data to the DX bus to be read by the CPU.

DXOO-DX05MAR6-11-

MEMORY
ADDRESS
REGISTER

AO-A6

ROW

r--r ADDRESS
LATCHES

DECODER

....
r-

XTC

_,.

REFRESH
FLIP-FLOP

REFRESH
ADDRESS
COUNTER

L....o.

REFRESH
DELAY

L..to

COLUMN
ADDRESS
LATCHES

ROW
SELECT

DECODER

4096-BIT
STORAGE

1/0GATNG
CIRCUIT

~ROW SELECT

WRITE
PULSE
DECODER

DATA IN
LATCH
DATA
DATAIN__j

MEMSEL--•
....

READ
FLIP-FLOP

DATA OUT
LATCH

1-- TO
CPU

~--• TO
READ CYCLE
CPU
MA-0258

Figure 2-8

Main Memory Block Diagram

2-16

~~~-------------------------2.959~·--------------------------~

STATES

I--592NS--I
I I ""1_2__,.___..J

XTCL

XTBL
CLOCKS
LXMARL

REFRESH
CLEARS
ACCESS (1)

ROW SEL (0-3)
, - - DUE TO ACCESS
DELAY
COL SEL (A+B)

MEM SEL

-.I 269 ns

I
I
I
1

I
I

:
READ CYCLE

I
I
I
ADDRESS (0-6)

OX DATA

~~~~ESS I

-=:=~~~--

1
I

I
I
I

I
I

DX0-5 I
---t---1
I

MAR 6-11

DATA FROM
MEMORY

REFRESH ADDRESS

DX0-5

ADDRESS
DATA

I
I

---ONE ROWADDRESS USED TO REFRESH
ONE 64 BIT WORD

I
IL _______________ _

COL ADDRESS LOADED BY COL SEL AND
MAR 6-11 MULTIPLEXED TO AO-A5

!_ _______________ ____ ROW ADDRESS LOADED BY ROW SEL AND
MULTIPLEXED TO AO-A5

08-1878

Figure 2-9

Read/Refresh Timing Diagram

2-17

3.&5213

STATES

END WRITE

ACCESS 111

ROW SEL (0-31

oo•m-=a

DELAY

...,

COL SEL (A+BI

I
I
I

MEMSEL

269,.

READ CYCLE

WP (0-31

ADDRESS (0-61

DX..

x ' - - + - - - - - - - - - M - A _ R _ s . _ n_ _ _ _ _ _ _ _ _

MEMORY READ
DATA

IL ______ _

L_______ _

__.X

DXO.SIWRITEDATAI

)

MEMORY WRITE
DATA

COL ADDRESS LOADED
ROW ADDRESS LOADED
DS.1BBDA

Figure 2-10 Read/Write Timing Diagram

2-18

The refresh cycle is a method of preserving data within main memory, when a read or write function is
not being performed at that particular address. This cycle is initiated in the second portion of XTC
during every second IFETCH. When XTC goes positive, it clocks the refresh flip-flop. The refresh flipflop, in turn, causes row select to be asserted low after a refresh delay of 270 ns. The refresh address is
now loaded into the memory chip row latches to refresh the 64 bits of that row address.
Refresh cycles occur every second instruction fetch cycle, and all 64 memory chip addresses must be
refreshed in less than 2 ms. During the next refresh cycle the address is incremented and loaded to
refresh the data again. If the processor is stopped, the refresh cycle will occur every eight XTC cycles.
If the second portion of XTC is to be a write cycle, the refresh address will not be loaded. The address
used during the read cycle will become the write address. When XTC and MEM SEL are high, a write
pulse (WPO through WP3) will gate DX bus data into main memory, after a delay to ensure that valid
·
write data is present on the DX lines.

2.2.1.3 Panel Memory - The panel memory has 256 words of static read/write memory for variable
storage and a lk ROM. The ROM contains the handler which analyzes the panel requests, the floppy
disk drive system bootstrap, a pseudo papertape binary loader for use by the MR 78, and a resident
diagnostic.

Figure 2-11 is a flow diagram showing the operation of panel memory.
When the system is initially powered up or when the START switch is pressed, panel memory is
invoked and information from the CPU is stored in panel memory (Figure 2-12). Panel memory can
also be invoked by CP REQ, HALT, or a special lOT.
If the panel memory determines that the panel request has been originated by power turn on, the
resident diagnostics will be performed. If the panel request has been originated by the START switch,
pane~ memory will select either the MR 78 or the floppy disk drive system to input a new program. If
the p;anel memory causes a halt message to be displayed on the CRT, a probable problem exists within
the VT78 terminal.

A panel memory request is acknowledged if the CPU CPREQ line is active low. The panel request is
granted irrespective of the run or halt state of the CPU. The CPU is temporarily put in the run state for
the duration of the panel routine, and the CPU reverts back to its original state after executing the
panel program. CPREQ also bypasses the interrupt enable system. An internal flip-flop (CONTROL
FF) is set when CPREQ is acknowledged, preventing additional CPREQs from being granted.
As long as CNTRL FF is set, CPSEL is asserted low for memory reference instead of MEMSEL.
CPSEL is used to distinguish between main memory and panel memory.
2.2.1.4 Real Time Clock- The real time clock interrupts the processor at a 100Hz rate if the interrupt
enable flag is set. A Skip instruction causes the program to skip an instruction if the clock flag is set.

Figure 2-13 is a simplified block diagram of the real time clock.
The real time clock uses device code 13 8 • The real time clock instructions are listed in Table 2-3. MAR
bits 9 through 11 are decoded to determine what operation the real time clock will perform.
INTREQ L is asserted when the clock flag sets, if the clock interrupt enable flip-flop is set. The clock
interrupt enable flip-flop is set when DX11 (from the AC) equals a "1" and the 6135 instruction is
exec1;1ted by the program. SKIP L is asserted, causing the program to skip an instruction, if the clock
flag flip-flop sets when the 6137 instruction is executed by the program. The clock flag is then cleared
by the 6136 instruction.
2-19

~T~A~~s;-;s
PRO lOT

PROGRAM
REQUEST

START BUTTON

POWER-UP

DECODE
SEQUENCE

CHECK PANEL
RAM+

--~

NO
CR

MAIN MEMORY
RAM+

SAVE All
REGISTERS

+V~

H
A
l

PRINT "HLT"
PC, l,AC,MQ

PROGRAM 4 - - - - - - l
REQUEST

&WAIT
FOR
BOOTSTRAP

NULLSLU 2
JOB

YES
RX01 BOOTSTRAP
LOADER

KEYBOARD
TEST

WAIT FOR
START

PRINT
"LD ERR"
AC, l,AC,MQ

I NO

START
PROGRAM

_j
os-1 883A

Figure 2-11

Panel Memory Logic Flow Diagram
2-21

CPREQ
POWER
SWITCH

POWER
GOOD

CPU

PANEL
MEMORY

CPSEL

,.----

BOOTSTRAP
SWITCH

}

EXTERNAL
PROGRAM
DEVICE

MAIN
MEMORY

LATCH

08-1871

Panel Memory Block Diagram

Figure 2-12

SKIP L
MAR 3-11

DECODER

DIVIDER
(+B)

D7TICK

SKIP FLAG
FLIP-FLOP

1/0 CLOCK - - - - - , - - - - t - - - - - - - l

RESET-----4---4---------~-----~

DX11----~r----r-------------~

INT

INTREQ L

ENABLE FLAG
FLIP-FLOP
MA-0113

Figure 2-13

Real Time Clock Block Diagram

Table 2-3 Real Time Clock Instructions
Mnemonic Octal Code Function
CLIE

6135

Load the interrupt from the ACll:
ACll = l(setinterruptenable).
ACll = 0 (clear interrupt enable).

CLCL

6136.

Clear clock flag.

CLSK

6137

Skip on clock flag.

2-23

2.2.1.5 Floppy Disk Drive Interface- The floppy disk drive interface is used to effect data transfers
between the VT78 terminal and up to two dual floppy disk drive systems. Figure 2-14 is a block
diagram of the RX78 interface circuits.
The DEVSEL/CON logic decodes instruction bits (3 'through 11) to (1) select a floppy disk drive
system to transmit or receive data from the VT78 terminal and (2) control all of the functions to be
performed. Bit 7 selects the floppy disk drive unit. Drive 0 is selected when bit 7 equals 0. Drive 1 is
selected when bit 7 equals 1. Bits 9 through 11 select the function to be performed. The states of these
bits and the corresponding functions performed are listed in Table 2-4.
Bit 4 is the maintenance bit which can be used to check the RX78 interface during on-line and off-line
conditions. The on-line condition occurs when the cable connecting the VT78 terminal and the RX78
floppy disk drive system is connected. The off-line condition exists when this cable is disconnected.
While the maintenance bit is set (bit 4 equals one), data transfers between the microprocessor and the
floppy disk drive system are inhibited. When bit 4 equals zero, the RUN flip-flop may be set producing
RUN Lor RUN 1 L (depending on the floppy disk drive system selected). The RUN Lor RUN 1 L
signal initiates communication between the interface and the appropriate disk drive. The RUN flipflop is clocked in the command transfer mode when LCD is issued or in the data transfer mode to or
·
from the drive when XD R is issued.
The floppy disk drive interface provides two modes of data transfer-a 12-bit mode and an 8-bit mode
determined by the state of microprocessor accumulator register bit 5. When bit 5 equals 0, the 12-bit
mode is selected. This permits 64 words to be written in a diskette sector; thus two sectors are required
to store one page of information. When bit 5 equals 1, the 8-bit mode is selected-permittin g 128 8-bit
bytes to be written in each sector. This effectively increases the word storage capacity of the diskette by
33 percent.
Figure 2-15 shows the RX78 interface timing sequence.
When data is to be transferred to the floppy disk drive system from the microprocessor, the floppy disk
drive system will set the Transfer. Request (TR) flag requesting the first data word. The XDR command will load the data word from the microprocessor accumulator into the interface register.
The interface register consists of two 8-bit, edge-triggered universal shift registers used to temporarily
store data during transfers between the microprocessor and the floppy disk drive system. Data is
parallel loaded into the shift register when LOAD EN is asserted low.
The next XDR lOT will then cause LOAD EN to be asserted high. LOAD EN His ANDed with EN
A Hand EN B H to initiate the transfer of the data word (in serial form) from the interface register to
the sector buffer in the floppy disk drive system.
Upon receipt of the entire data word, the floppy disk drive system will issue another TR requesting the
next data word. The transfer process is then repeated until the sector buffer has been loaded (64 data
·
transfers for 12-bit mode or 128 transfers for 8-bit mode).
After the sector buffer is filled, the floppy disk drive system sets the Done flag indicating that the
function has been completed.
SKIP L will be asserted if any of the skip commands [Skip on Transfer Request {STR), Skip on Error
(SER), or Skip on Done (SON)] are decoded by the DEY SEL/CON circuit and the corresponding
flag has been asserted.

2-24

DXQ..11

DX0-3

MAR3-11 _ _,..

DEV
SEL/CON
DECODER

INHIBIT
GATES

INTERFACE
REGISTER

MODESEL

MODE
.___ _ _ _ _ _ _ _ _ _ _ _•

RX DATAL
DATA 1 L

RUNL
RUN
F/F
DONE----------~L_______

__j

RUN 1 L

TR---------------~~------~~--~--------~

STR - - - - - - - - - . . . , . . .

FLAG
F/Fs
SER
S D N - - - - - - - - - - - - - - - - - 1 L________

---------- -ef

Figure 2-14

STATUS
REGISTER

1-------- --•

_J----1L________j
08-1874

Floppy Disk Drive System Interface
Block Diagram

Function Codes for LCD lOTs

Table 2-4

SKIP L

Function

Bit Code

0·

Fill buffer.

Empty buffer.

Write Sector.

Read Sector

Not used.

Read Status.

Write Deleted Data Sector

Read Error Register.

2-25

LCDIOT

RUN

DONE

XFR REQ

OUT

RX DATA

SHIFT
DATA TO DISK

DATA FROM DISK

LOAD COMMAND- READ STATUS

: - - - - - - - - - - - REPEATS 64 TIMES - - - - - - - - - ! . . j
DONE GOES TRUE AFTER LAST TRANSFER

XDRIOT

RUN

XFR REQ

OUT ----~--~--------------------------------------~~-------------------------RXDATA

SHIFT

STR

WRITE DATA (12 BiT MODE'
MA-0459

Figure 2-15

Floppy Disk Drive System Interface
Timing Diagram

2-26

When data is to be transmitted from the floppy disk drive system to the microprocessor, XDR causes
LOAD EN; ENA, and ENB to be asserted high-shifting the first word into the interface register. The
TR flag is set with the first word in the interface register. This flag denotes that a request for a data
transfer from the floppy disk drive syst¥m to the microprocessor has been made. After the flag has
been tested and cleared, the word will be transferred to the microprocessor accumulator by the next
XDR command.
After transferring the next data word into the interface register, the TR flag is set again and the
transfer process is repeated until the entire contents of the floppy disk drive system's buffer register has
been transferred-emptying the buffer register. The DONE flag is then set indicating the end of the
transfer function.
2.2.1.6 MR78 Interface - The MR 78 program loader is an optional device which is used to load one
of several programs (stored in ROMs) into main memory. A complete functional description of this
device is provided in Appendix A.
The MR 78 interface consists of four buffer registers and associated gating circuits shown in Figure 2H).
When program loading is to be implemented, the panel memory handler checks for the existence of the
MR78 at the MR78 bootstrap port. If the MR78 device is not installed, the panel handler will check
fo'r the existence of a floppy disk drive system as program source. If the MR 78 device is installed,
Cl-IARACTER RDY Lis produced by the MR78 in response to the PI BD L initiation of the program
loading sequence. When the fetch new character instruction (6016) is issued, the current character (as it
appears at the bootstrap port) is ORed to the accumulator. The MR78 then starts to obtain a new
character, clearing the get character flag until the new character is available at the interface.

MR78 INTERFACE

P1 BDL
GET CHAR L

MR78

TRI-STATE
BUFFERS

""'
Sh I

HOLE 1 THRUS

DEVICE
CHARACTER ROY

RSF

DXO-DX11

MEMORY

SKIP L

READ ENABLE

RRBH

C1 L

RESET
MA-0114

Figure 2-16 MR78 Interface Block Diagram

2-27

Three lines at the interface are interrogated by the MR 78 program to define the number of programs
to be loaded before reading is terminated and the program is started.

NOTE
Although the MR78 bootstrap port was provided spe·
cifically for loading MR78 device programs, the port
may be used to input 8-bit character data in other
than binary format, providing Pl BD L is not present.
2.2.1.7 Serial Line Units- There are three Serial Line Units (SLUs) in the DECstation. Their function is to receive parallel data (characters) from the microprocessor accumulator and shift them out in
EIA to a serial device as serial data or to receive EIA data from a serial device, change it to parallel
data, and transfer it to the accumulator.
The SLUs consist of a Universal Asynchronous Receiver Transmitter (UART) driven by an oscillator
generator package. Figure 2-17 is a simplified block diagram of the SLUs and their associated control
circuits.
Timing for each of the SLUs is derived from a 5.066 MHz square wave clock and a network of
frequency dividers. The frequency of the clock applied to the UART is the baud rate multiplied by 16.
Baud rate selection is accomplished by an IOT instruction which loads 4 bits of the accumulator into
the frequency divider as shown in Table 2-5. Each SLU has its own baud rate generator, consequently
each baud rate can be programmed independently.
The decoded memory address register bits 3 through 8 select the SLU to effect the transfer of data
between the microprocessor accumulator and the external device. Two device codes are used-one for
transmitting data and the other for receiving data as listed in Table 2-6. Memory address register bits 9
through 11 determine the function to be performed by the selected SLU. The microprocessor is interrupted by an INT REQ L, if the interrupt enable flag is set and the transmit or receive flag sets. Skip is
asserted if the transmit or receive flag is set while flags are being checked by the program.
Since all of the SLUs are similar only one, SLU 2, will be described in detail.
When the U ART is in the transmit mode of operation, it changes 8-bit parallel data from the microprocessor accumulator to serial data for transmission to a serial device. Figure 2-18 shows the transmit
function timing sequence.
The number of bits per character, stop bits, parity, and error detection is selected by KMD1 lOT. Note
that SLU 2 is the only line having this capability. SLU 1 and 3 are fixed at 8 data bits, 1 stop bit, and
no parity. When the transmit operation begins, a strobe (TBRL) is generated by ROM D and ROME
at DEV SEL time. ROM D decodes the device selected and ROM E decodes the function desired.
Strobe TBRL loads the data from the microprocessor accumulator into the UART transmitter buffer
(Figure 2-19) and sets the UART internal transmit flag. The UART will now transfer the data from the
buffer to the transmit register and begin shifting data to the serial device.
The first bit transmitted is the start bit followed by bits 11 through 4 and the stop bit (assuming that
UART is transmitting in the 8-bit mode). Approximately three clock pulses after the transfer of data
from the transmit buffer register to the transmit register, the Transmit Register Empty (TRE) flag is set
and another character can be loaded into the transmit register.

2-28

A•

FLAG
TRC/RRC
TBRL--

DX4 -DX11

FLAG

SLU 1

1--

TRC/
RRC
TBRL

~>
SLU2

1--

FLAGTRC/RRC
TBRL-

.!J
SUJ3

1--

r---

l
TE SEL

MAR

3-8

ROM
D

1--

..
MAR
9·11

DEVICE
DECODER

BAUD
RATE
GEN

ROM

TRANS/
RECEIVE
DATA
BUFFER

·.}· SERIAL
DATA

INT
LOGIC

INTREQ

SKIP
LOGIC

SKIP

f---- TBRL

f--.- TRC/RRC
(BAUD RATE)

FLAGS

08-1875

Figure 2-17 SL U and Control Circuits
Block Diagram

2-29

Table 2-S Baud Rate Selection
(SLU 2 and SLU 3)
rontrol Bits

Baud Rate

Clock Div

FreqtoUA RT

6336

799.56 Hz

4224

1199.34Hz

110

2880

1759.03 Hz

134.5

2355

2151.17 Hz

(

150

2112

2398.67 Hz

(

300

1056

4797.35 Hz

(

600

528

9594.70Hz

(

1200

264

19.1894 kHz

1800

176

28.7841 kHz

2000

158

82.0633 kHz

2400

132

38.3788 kHz

3600

57.5682 kHz

4800

76.7576 kHz

7200

115.1364 kHz

()

9600

·33

153.5152 kHz

19200

316.6250 kHz

Table 2-6 SLU Device Codes
SLU

Receive

Transmit

2-31

+V
EIA
DATA

ov
-V

~START

BBITASCII(AI

STOP

~STAR'J'

BBITASCII(BI

-==+-+-..:f..--.--,;--,--.- h--.- t- f- -,- t,.- f,- -.- -.- il- ,-'--.. ~
_/

(3011

(3021

NOTE:

START BIT (11
}
BBITASCII
STOP BIT (1)

9600
BAUD
NO
PARITY

CLOCK+ 16

-1

----------------·1.042ms

------------to!

CLOCK
·,~

TBRL

2 TO 3 CLOCK !MAX RATE)

PULSE WIDTH APPROX. 250NS

TBRE

TRE

EIA
DATA

--------------------------~-----------------------------.·

I NOTE:
I

DATA
STROBE

}

-·---·-.---·-----

AFTER THIS POINT TR BUFFER IS EMPTY
AND CAN BE LOADED

I
I

.-------------

---·

TBR~

TRE

EIA
DATA

(LASTI STOP BIT

ITRANSMITI

08-1881

Figure 2-18

UART Transmit Function
Timing 'Diagram
2-33

A
B

CONTROL
LOGIC

PAR
GEN

A= NO STOP BITS
B = EVEN PAR SEL
C=NOPARITY
D = BITS/CHAR.

OUTPUT
CIRCUIT

r - SERIAL OUTPUT

LSB

09 -

DX11

06 07

05
DX04

XMIT
BUFFER
REGISTER

TRANSMIT
REGISTER

LOAD

MSB

(TBRL)

CLOCK

SHIFT

XMTR
TIMING
AND
CONTROL

TBE
UART TRANSMITT ER

TIME
GENERATOR

08-1876

Figure 2-19

UART Transmit Circuits
Block Diagram

2-35

The receive portion of the UART receives serial data from an external device and changes it to a
character to be transmitted, in parallel, to the microprocessor accumulator. This is performed during
the next KRB lOT (load receiver command). Figure 2-20 shows the receiver function timing sequence.
Transfer occurs when data, assembled in the receiver shift register (Figure 2-21), is transferred to the
holding register. At this time Data Received (DR) is asserted, the receive flag is set, and data is
transferred to the microprocessor accumulator. The receive flag is cleared when the content of the
holding register is transferred to the accumulator. This can only be done through the clear flag lOTs. If
not clleared, receipt of the next character will cause an overrun error.
Table 2-7 contains all of the SLU signals and includes a brief functional description of each.
2.2.1.8 Parallel 1/0- The parallel I/0 interface is used to connect the LA 78 or LQP78 printer to the
VT78 terminal. However, any parallel I/0 device (using 12-bit data and meeting the I/0 interface
specifications) can communicate with the VT78 terminal via the parallel 1/0 interface.
Figure 2-22 is a simplified block diagram of the parallel 1/0 interface.
The memory address register determines the device to be used in conjunction with the parallel 1/0
interface and the function to be performed. Device selection (LQP78 or LA 78) is accomplished by
decoding memory address bits 3 through 8 and the LA/LQP signal using the DVCD SEL register. The
function to be performed is determined by decoding memory address bits 9 through 11 using ROM A
and ROM B.
The PAPER ROY, CHARACTER ROY, CARRIAGE ROY, and PTR ROY signals show the status
of the printer. The use of these signals depends upon the device associated with the parallel I/0
interface. When the printer is ready to accept and print data, these signals will set corresponding flipflops which may be tested by an lOT causing a skip. The status register can be read by an lOT to
determine the status of the printer.
Parallel data is transferred using a bi-directional tri-state data bus. Normally IN /OUT is maintained
high and the parallel I/0 interface will only provide output data. When IN/OUT is asserted low, the
output register is disabled and the interface can receive data, if available. An input device must assert
the IN /OUT signal low for at least 50 ns prior to asserting new data on the lines and must keep it low
until 50 ns after the data has been removed.
NOTE
Parallel 1/0 signals can not be driven more than 25
ft (approximately 8 meters).
Table 2-8 is a list of the primary control signals used with the parallel 1/0 interface and includes a brief
functional description of each.
2.2.2

Keyboard/Video Display

2.2.2.1 Data Paths, Memory, and Decoder Circuits- The RAM and memory buffer, the character
generator, the video shift register, the instruction decoders, and the memory select and program test
registers are located on the data paths, memory, and decoder module. Each of these logic groups will
be discussed separately.

2-37

RECEIVE
FIGURE B

CLOCK

I
EIA
DATA

--~

+V
0 _ _ _.......,.,

<TART m

-V

I
I

m n

DRR

NOTE 1:
GENERATED BY DEVSEL
APPROX 250 NS WIDTH

-----'

•:

~-------------------------------------------- FIGURE
RECEIVEC

PE,FE

EIA
+V
DATA
0

I
BIT4

NOTE 2:
CONDITION DUE TO
STATUS OF PREVIOUS
CHARACTER

STOP BIT

START BIT

(BIT 11)

-V

RBRI-8, OE

NOTE2

I
ORR

NOTE 1

PE,FE

08-1873

Figure 2-20

UART Receiver Timing Diagram

2-39

DX11 - - - - - - - - - - - - - - - - - - - - - - - - DX4
DATA BITS TO AC

r,--------------~·-------------.
LSB

MSB
ROO

DATA
ENABL E
RRU

AND GATES

DATA HOLDING .REGISTER

SERIAL
DATA
INPUT

RECEIVER SHIFT REGISTER

A
.____

DATA !RECEIVED
PARITY ERROR

CONTROL LOGIC
CLOCK
INPUT

FRAMING ERRO R

EVEN
PARITY
SELECT

NO
PARITY

NB2

NB1
NUMBER OF
BITS/CHARACTER
08--1872

Figure 2-21

UART Receiver Circuits
Block Diagram

2-41

Table 2-7 SLU Signal Functions
Pin

Mnemonic

Description

Function

RRD

Receiver
Register
Disable

A high on Receiver Register Disable
forces the Receiver Holding Register
outputs to a high impedance state.

RBRlRBR8

Received
Data

The contents of the receiver buffer appear on these tri-state outputs. Words
less than eight characters are right justified to RBRl and the unused bits are
zero.

Parity
Error

A high level indicates received parity
does not match parity programmed by
control bits. If parity is inhibited, this
output is low (SLU 2 only).

Framing
Error

A high level indicates the first stop bit
was invalid (SLU 2 only).

Overrun
Error

A high level indicates data received
flag was not cleared before the last
character was transferred to the receiver buffer register (SLU 2 only).

SFD

Status
Disable

Never disabled (always ground).

RRC

Receiver
Clock

16 times the baud rate.

ORR

Data Received Reset

A low level clears the Data Received
DR output to a low level.

Data Received

A high level indicates a character has
been received and transferred to the
receiver buffer register.

RRI

Receiver
Register
Input

Serial data is clocked into the Receiver Register.

Master
Reset

A high level clears PE, FE, OE, and
DR to low levels and sets the transmitter output to a high level.

TBRE

Transmitter
Register
Empty

A high level indicates the buffer
has transferred its data to the transmit
register and is ready to receive new
data.

2-42

Table 2-7

SLU Signal Functions (Coot)

Mnemonic

Description

Function

TBRL

Transmitter
Buffer Load

A low level transfers data from TBRl
through TBR8 input into the buffer
register. A low to high transition
transfers the data to the transmit register. If the transmit register is busy,
transfer is delayed until the character
can be loaded.

TRE

Transmitter
Register
Empty

Not used.

TRO

Transmit
Output

Character data, start bit, and stop bits
are outputted serially.

26
3~

TBR1TBR8

Buffer Register Inputs

Input character data is loaded (in parallel) to the buffer register.

CRL

Control Bit
Load

A high level loads the control register
(SLU 2 only).

Parity Inhibit

A high level inhibits parity generation,
parity checking, and forces PE output
low.

SBS

Stop Bit
Select

A high level selects 1.5 stop bits for 56
characters and 2 stop bits for all others. A low selects 1.0 stop bits.

37,
38

CLS 2
CLS 1

Character
Length
Select

These inputs select the character
length (SLU 2 only).

EPE

Even Parity
Enable

When PI is low, a high level generates
and clocks even parity. A low level selects 1.0 stop bits (SLU 2 only).

TRC

Transmitter
Clock

Transmitter clock ( 16 times baud
rate).

2-43

CHECK L·

FROM
PERIPHERAL
1/0 DEVICE

PAPER ROY
CARRIAGE ROY
CHAR ROY
PTR ROY

---

PAPER
FLAG
F/F

CARR
FLAG
F/F

STATUS
REGISTER

CHAR
FLAG
F/F

n
u

r--1_

INT
ENABLE

SKIP L

0
PU

INT REO

,___/

PTR
FLAG
F/F

MAR 9-11
03

00 11

STATUS
GATES

ROMA
-CONTROLS

(CPU)

)

~
"'

INPUT
GATES

: - - - - LIFT RIBBON

f--+ CONTROLS
ROMB

DXOO·
DX11

LIFT
RIBBON
F/F

OUTPUT
REGISTER
MAR3-8 __.

DVCD
SEL

f---.

1/0
STROBE

STROBE
CONTROLS

f--

PAPER STROBE
CARRIAGE STROBE
CHARACTER STROBE
RESTORE

TO
PERIPHERAL
1/0 DEVICE

)_
08-1877

Figure 2-22 Parallel I/0 Interface
Block Diagram

2-45

Table 2-8 Parallel 1/0 Interface Signal Functions
Signal

Function

Character Strobe

This pulse causes the print wheel in the LQP78 to position the selected character in front of the print hammer. When motion stops, the hammer strikes.
In the LA 78 this pulse causes data to be loaded into the printer memory.
Upon completion of a line of data, the entire line will be printed. For any
user application the strobe is generated by the print character command
(6504) or the load printer buffer command (6664).

Carriage Strobe

This pulse is used by the LQP. The carriage strobe occurs when the LQMC
(6503) lOT is performed and causes the carriage to move in a selected direction and distance, using the value of the data received from the data bus.
Each data bit causes the carriage to move 120th of an inch. AC bit 0 determines the direction of motion-righ t (0) or left (1).

Paper Strobe

This pulse is used with the the LQP and occurs when the LQMP (6502) lOT
is performed. The signal causes the paper to move in the direction and distance specified by the data received. Each data bit causes the paper to move
1/48th of an inch per binary bit. Bit 0 determines the direction of motion-a
high causes the paper to advance and a low causes the paper to reverse.

Restore Strobe

This pulse is used with the LQP and occurs when the LQRE (6507) lOT is
performed. It causes the printer to abort all operations in progress, clear
error conditions, and move the carriage to the extreme left position.

LA/LQP

This signal determines which device code lOT will be performed. If the LA 78
printer device code (66) is required, the line should be grounded. The user
must select the device code. This is accomplished by using the correct cable
to connect the LA 78 or LQP78.

Data Lines

These signals receive and transmit binary coded information which represents various operations for each command. The data must be asserted true
for at least 200 ns prior to the strobe pulse.

Check Line

This input from the LQP indicates an error has occurred as a result of a
malfunction or an illegal command. All activity will stop and all inputs and
outputs will be disabled except the restore strobe. The restore IOT or a reycle of power is the only way to clear a check condition. This signal is not
used with the LA78 printer.

Character Ready

This input indicates that either printer is ready to begin a print cycle. This
signal is false while the printer is printing a character or loading a character
into memory.

Carriage Ready

This input indicates the LQP is ready to accept a carriage motion command.
The line is high (false) while the carriage is in motion. It is not used with the
LA 78 printer.

2-47

Table 2-8 Parallel 1/0 Interface Signal Functions (Coot)
Signal

Function

Paper Ready

This input indicates the LQP is selected properly and is supplied with power
and no internal malfunctions exist.

In/Out

This signal line is normally high. In this mode the interface will only provide
output data. If this line is asserted low, the output buffer is disabled and the
interface can receive any input data, if available. This line must be asserted
low for at least 50 ns prior to receipt of externally supplied data and maintained low until 50 ns after data has been removed.

Printer Select

This signal is only used by the LQP to enable the printer to respond to any
input commands. This line enables all printer input and output lines using a
grounded line from the interface.

The RAM consists of fourteen 2102 chips arranged to provide two 1024x7 read/write memories. To
the programmer, the memory appears as a 2048x7 bit memory, because the RAM addressing scheme
assigns all even addresses to one 1024 memory (page 1) and all odd addresses to the other memory
(page 2). 1,920 locations are used to store a screenful of characters (24 lines x 80 columns); the remaining 128 locations are used by the microprogram as a scratchpad memory; i.e., temporary storage of
keyboard characters, cursor address, etc.
The memory buffer contains the contents of the RAM location selected by the current contents of the
X and Y registers. Twice during each instruction time, the selected RAM output is strobed into the
memory buffer for transfer to the video circuits during display time, the UART for transmission to the
processor, or the X, Y, AC, orB registers because of a command test condition. Data written into the
RAM can be from the AC register, the B register, the ROM, or the UART. These inputs are multiplexed into the RAM by signals MUX A and MUX B. The TRUE/FALSE condition of MUX A and
MUX B is the result of decoded microprogram transfer commands.
Figure 2-23 illustrates how address mapping is accomplished. The memory is arranged in a 16x64
configuration with Y3, Y2, Y1, and YO selecting one of 16 rows and X5, X4, X3, X2, Xl, and XO
selecting one of 64 columns. Whenever the X register is greater than 64 or theY register is greater than
12, the two most significant Y address lines are forced high and the two most significant X address
lines are replaced by Y3 and Y2. This effectively divides the RAM into five sections: one 12x64 section
and four 4xl6 sections. Memory references for characters displayed in columns 0 through 63 will be
made to the 12x64 section; memory references for characters displayed in columns 64 through 79 will
be made to one of three 4xl6 sections. The contents of theY register will determine which one of the
three 4x 16 sections will be referenced.
The remaining 4xl6 section is used as a scratchpad memory by the microprogram. This section is
addressed whenever the Y register contains a number greater than 11. The address mapping circuits
replace the two most significant bits of the X register selection bits with Y3 and Y2. Since Y3 and Y2
will both contain Ones when a number greater than 11 is in theY register, they will select the highest
4xl6 memory section. X3, A2, X1, and XO will select one of the 16locations in this section.
The Video Shift Register (VSR) is a 7-bit shift register that holds one line ofthe seven-line character
currently being displayed on the CRT screen. During each video scan, the video shift register is loaded
from the character generator 80 times, once for each character position. After loading, the contents of
the VSR are shifted by B OSC A (the basic timing clock) through the video amplifier to the cathode of

2-48

the CRT where they modulate the electron beam. Zeros shifted out of the VSR will cause a +2 V signal
on the cathode and light on the screen. Ones will cause a +40 V signal on the cathode, cutting off the
CRT and producing a dark screen.
Figure 2-24 illustrates the data path of the character from the RAM to the CRT cathode and the
display timing. T2H, a timing pulse that occurs once every timing cycle, simultaneously loads the VSR
with one line of the character to be displayed and loads the memory buffer with the character that will
be displayed in the following screen location.
Every operation performed by the display is the result of an instruction stored in the 1024x8 bit ROM.
The 8-bit ROM word is decoded by the decoder logic to produce an instruction. This instruction will
cause some action to take place in the terminal. The bits of the ROM word are labeled A through H.

ACTUAL LAYOUT OF RAM CHIP
0 1 2 3-

-63

YO
y 1
y2

AAA8 8 8

-8

ccc

-c

Y 4

D D D

-D

Y 8

E E E

-E

Y11

F F F

-F

Y12
Y13
Y14
Y15

-A

79
79 64
64
E-----E
D-----D

79
64
A-----A
8-----8
C-----C

SCRATCH
PAD

F - - - - -F

PROGRAMMER/OPERATOR VIEW OF RAM LAYOUT
X• 0 Y•O
1
2
3
4

63164 -

-------------A
-------------8

AAA8 8 8-

c c c-

-79

A----A-0
8----8-1

- - - - - - - - - - - - c c - - - -c

-2

1-------t- 3
- - - - - - - ------D

D D D-

D----D

-4

-5

-6
-7

7
8

E E E-

- - - - - - - - - --EI-:E::-------:E::-1-8

-9

-10
-11

F F F- - - - - -

---- ----- F

F-- -- F

y. 12
13
14

SCRATCH
PAD

15
X•0-------15
CP-2293

Figure 2-23

RAM Address Mapping

2-49

+2• TURN ON
+40•CUT OFF

T2H

B OSC A

.~--------~

I I I I

I I I

~----------~

~---

I I I I I I I I I I I I
CP·2294

Figure 2-24

Character Display Timing

As Figure 2-25 shows, the ROM word is divided into three groups: A, BCD, and EFGH. If Bit A
equals 0, bits B, C, and D are decoded into one of eight instruction groups. Bits E, F, G, and H are
sampled to determine what action is to be taken. An action occurs if one or more of the bits are set to
I. For example, if bitE is a 1, a certain action will occur; if both bits E and Fare set to 1, two actions
will occur but not at the same time. If E, F, G, and Hare all set to 0, a different action takes place
depending on the state of B, C and D. Table 2-9 is a list of commands that are available when ROM bit
A is set to 0. If bit A of the ROM word is set to 1, a load RAM from ROM command will be decoded.
When operating in mode 1, the command is conditional. The seven least significant bits of the ROM
word (BCDEFGHA) are loaded to the RAM location specified by the contents of the X andY registers. When operating in mode 0, the load command is conditional. In operation, the command increments the AC register and then compares the ACto the selected RAM location. If AC is less than
RAM, the load command is not performed; i.e., the contents of the selected RAM location remains
unchanged. If AC is greater than RAM, BCDEFGH is loaded into the RAM and the DONE flip-flop
is set. All instructions listed in Table 2-10 are decoded at specific times in the instruction cycle. Six time
states (9TE, TF, TW, TO, TH, and T J) are produced during each instruction cycle (Figure 2-26). These
signals are gated with ROM bits EFGH to enable the desired action. Table 2-10 lists the timing states
and the instructions performed at each state in the instruction cycle.

2-50

The character generator consists of a 1024x8 bit ROM and associated address gating. The display code
for all characters displayed on the screen is stored in the ROM.
During display scans, characters fetched from the RAM are loaded into the memory buffer in ASCII
format. Because the address selection lines of the character generator are wired directly to the memory
buffer, the character generator never needs to be loaded. It is always selecting the ROM location
addressed by the ASCII code in the memory buffer. For example, if the memory buffer contains the
ASCII coded for "A," the character generator address lines will select the ROM location containing
the 7X7 display code for the letter "A." However, since the character display method used by the
display requires that only one line of the 7X7 character be displayed during a single horizontal scan,
three more address lines are provided to select one of the seven lines of the matrix: the three least
significant bits of the AC register. In operation, ASCII characters are loaded into the memory buffer;
the character generator uses this code as an address to select the ROM location containing the display
code for the desired character. AC bits 0, 1, and 2 are decoded to select one of the seven lines of the
character matrix for output to the video shift register.
Character generator outputs CDO through 6 are loaded into the Video Shift Register during the T2
time of every clock cycle. CD6 will be the first bit shifted out of the VSR; CDO will be the last.

A (OJ= INSTRUCTION
A (1 l= CONSTANT

COMMANDS

COMMANDS
CP-2295

Figure 2-25

ROM Word Division

Table 2-9

Command List

ABCD

Display Instruction

Mnemonic

0000

Set cursor flip flop.

SCFF

Clear the X and Y registers.

ZXZY

Decrement the X and Y registers.

DXDY

Load AC from memory.

M2A

2-51

Table 2-9
ABCD

0001

0010

0011

Command List (Coot)

Display Instruction

Mode 0: Printer scan flag set?

PSCJ

Mode 1: Jump if UART has received a character.

URJ

Mnemonic

Set video flip flop.

SVID

Complement bit X3 (8s-bit) of X register.

Increment AC register.

Load RAM from AC.

A 2M

Mode 0: Jump if ACO, 1, 2 = 78 .

TABJ

Mode 1: Jump if AC =RAM.

AEMJ

Load Y Register from Y buffer.

B2Y

Increment X; decrement Y.

IXDY

Increment AC register.

IAI

Load UART from RAM.

M2U

Mode 0: Jump if key click.

KCLJ

Mode 1: Jump if AC<RAM.

ALMJ

Complement bell flip-flop.

CBFF

Increment X register.

2-52

Table l-9
ABCD

0100

0101

Command List (Coot)

Display Instruction

Mnemonic

Increment Y register.

· Load RAM from B register.

B2M

Mode 0: Jump if 60 Hz line frequency.

FRQJ

Mode 1: Jump if AC = X register.

ADXJ

Clear cursor and video ff.

ZCAV

Clear AC register.

Decrement Y register.

Load X register from RAM.

M2X

Mode 0: Printer request flag set?

PRQJ

Mode 1: Jump if AC = RAM.

AEM2J

Load print shift register.

LPB

Enter mode 1.

Increment ROM bank.

IROM

Load RAM from UART.

U2M

Mode 0:

TRUJ

Mode 1:

2-53

Table 2-9

Command List (Cont)

ABCD

Display Instruction

Mnemonic

0110

Start printer.

EPR

Clear X register.

Decrement X register.

Load Y buffer from RAM.

M2B

Mode 0: Jump if UART is transmitting.

UTJ

Mode 1: Jump if video scan flag.

VSCJ

0111

Halt printer and clear Y register.

HPRIZY

Enter Mode 0.

Decrement AC register.

Spare.

Mode 0: Jump if not top of screen.

TOSJ

Mode 1: Jump if key not typed.

KEYJ

CP-2296

Figure 2-26

Cycle Timing Diagram

2-54

Table l-10 Instruction Time States
Time State

Decoded Instruction

ROM Enabling Signals

ZXZY, X8, IXDY, IX, ZA, Ml, 2Z, MO

A.E.

DXDY, lA, IAl, IY, DY, IROM, DX, DA

A.F

SCFF, SVID, B2Y, CBFF, ZCAV, LPB, EPR, HPR, ZY

A.E.F.G.H

CLEARWRITE FLIP FLOP

M2A,A2M,M2U,B2M,M2X,U2M,M2B

A.G

JUMP,NO-OP

A.H

l.l.l.l ROM, UART, and Timing Circuit- The ROM is a 1024x8 bit read-only memory that stores
the pisplay microprogram. It consists of eight 256x4 chips organized as illustrated in Figure 2-27 to
provide four pages of 256x8 bit memory. The outputs A through H reflect the contents of the location
addressed by the Program Counter (PC). The eight least significant bits of the PC will address one 8-bit
ROM word from page 1, 2, 3, or 4. Page selection is determined by the condition of PC bits 8 and 9.
The! PC is normally counted at the TH time of every instruction cycle to fetch a new command or
address from the next sequential ROM address.
Commands that affect the PC and the ROM are JUMP and IROM. A program jump is accomplished
by lbading a new address into the PC. The new address is always the contents of location JUMP + 1.
At tihe TH time of the JUMP command, the PC is counted and the ROM output word will contain the
newl address (JUMP + 1). If the jump conditions have been met, FLAG L will be TRUE and PC
cot.JNT will load the new address into the PC. Program skips are the result of not meeting JUMP
contlitions; there is no skip command. If JUMP conditions are not met, FLAG L will be false and the
PC iwill not receive the new address. Instead, PC COUNT will increment the PC a second time,
the next command from location JUMP +2.
fetching
I
!

··.·

The! JUMP command allows jumping within the selected page. To jump to a different page, the progratin must perform one or more IROM commands followed by a JUMP command. The IROM
co?lmand increments the page counter. When a JU. MP command is executed, the new page address is
lo~~rd into PC9 and PC8. At the same time, the contents of ROM location JUMP + 1 are loaded into
. PC through PCO to select one of the 256 locations in the new page.
1

;

Alliperations are synchronized by the basic timing clock and timing chain (Figure 2-28). The clock is
a c ystal-controlled oscillator operating at 13.824 MHz. Clock output B OSC A provides the basic
clo k frequency for the timing shift register and frequency dividers. It is also used to perform shift
ope ations in the video shift register. The output of the crystal clock becomes the input clock of an 8bit hift register. The outputs of the shift register are ANDed together to provide an input data signal
to t~e register. When all bits in the register are set to 1, the input data signal will be a "1." The result is
tha~ the register acts like a 9-bit ring counter with a "0" being shifted through all of the bit positions.
:

Thel output from this register when ANDed with the time state en!!ble signal produces the six time state
signjals required fer instruction decoding. The tim state enable signal is the output of the first stage of a
4-bit divide-by-10 counter that follows the shift register in the timing chain. The input clock to this
coupter is wired to the last stage (bit 7)of the shift register. This means that the time state enable flipflo~ is toggled once for each complete cycle of the shift register. It also means that it takes two
coniplete cycles of the shift register to produce the six time state signals.

14----------ROM OUTPUT-----------.(
A

P.C. 7-0
(ROM ADDRESS)

CARRY OUT

TW------1

TJ
CP-2297

Figure 2-27 Display ROM Organization and Selection

2-56

13.824 MHz

1 - - - - - - . . , . . - - - - - - - TE

r------------------------TF
8-81 T b--------------1----<lf-..........,
r------------------------TW
CNTR

+9
1 - - - - - - - - - TG

1-------TH

1-------TJ

,..--L---, TIME STATE ENABLE
4-BIT
CNTR r---------------------------~~
.;.10

4-BIT
CNTR
710

t----TSC L
(TOP OF SCREEN FLAG I

!-----+VERT H

CP-2298

Figure 2-28 Display Basic Timing Circuits

2-57

The input clock frequency applied to the 4-bit decade counter is 1.536 MHz which is the crystal clock
frequency divided by 9. Since this is a divide-by-10 counter, the frequency at the final stage is one tenth
of the input frequency or 153.6 kHz.
The clock is again divided by 10 in a second decade counter producing an output frequency of 15.36
kHz which is the horizontal display frequency. The output of the final stage of this counter is signal
HORIZ L which is at ground level during horizontal retrace time. The high-to-low transition of this
signal clocks the SYNC flip-flop producing H FLY H which inhibits automatic incrementing of the X
register and the loading of the VSR.
The clock is fed to three more counters to produce the clocks for the baud rates available in the
display. The last counter in the timing chain is used to develop the vertical display synchronization
signal, VERT H. This counter is jumper selected to divide by 10 or divide by 12 to produce a 60 Hz or
50 Hz VERT H signal.
Figure 2-29 is a diagram of the CRT used in the display. It consists of a heater, an electro-emitting
cathode, a control grid for biasing, a focus grid for shaping the beam, a screen grid for accelerating the
beam to the phosphor-coated face of the tube (screen), and an anode which provides the main accumulator.

VERT. DEFL.
COILS

HORIZ. DEFL.
COILS

FILAMENT
(HEATER)

ANODE(11KVOLTS)
SCREEN GRID
'-----FOCUS GRID
L - - - - CONTROL

GRID
CP-2300

Figure 2-29

Cathode Ray Tube

2.2.2.3 Keyboard Circuits- The keyboard is arranged so that the keys form an 8x10 matrix and every
key except the BREAK key has been assigned a unique identifying number representing its position in
the matrix. The AC register is used to detect keys that have been activated (typed). ACO, 1, and 2 are
decoded to enable one of the eight lines of the matrix; AC3, 4, 5, and 6 are decoded to enable one of the
ten columns. Any key can be checked by placing its identifying number in the AC register. If the key is
not down, FLAG L will be true.
The keyboard/video display program polls the keyboard during vertical retrace time by loading the
AC register with the highest key number and entering a program loop that continually subtracts one
from the AC register and tests the result until an active key is found or until the AC equals zero.
2-58

When a key is "down," the program leaves the test loop and stores the key number in Keyboard A or
Keyboard B of the scratchpad memory. On subsequent keyboard pollings, the program will fetch the
numbers stored in Keyboard A and Keyboard B and check the keyboard to see if one or both of these
keys are still "down." If both keys are down, the program leaves the loop and no keyboard entries are
made. When either of these keys are found to be "up," scratchpad locations Keyboard A and/or
Keyboard B are cleared and a new keyboard search is started. This test routine is always performed
before every keyboard test to prevent multiple entries of the same character.
After storing the identification number of the active key, the program looks up the ASCII code for that
key in a table in the ROM, then transfers the ASCII-coded character to the UART for transmission to
the processor.
The BREAK key cannot be tested by the program. The CONTROL key, if activated while a ROM
word is being loaded into the RAM, will force the two most significant bits of the ROM word to zero.
The ROM word is transferred to the RAM if AC is greater than RAM during a conditional load RAM
command. The BREAK key interrupts the UART serial data output line for as long as the key is held.
The break key functions independently of the program.
2.2.2.4 Microprogramming- The ROM resident microprogram controls all operations in the display.
This includes the three major operations performed by the display: (1) displaying characters andrefreshing the screen at a line frequency rate, (2) acting as an input device by transmitting key codes
entered by an operator to the SLU, (3) acting as an output device by processing or displaying codes
received. In addition, the microprogram directs the advanced features such as controlling data flow in
the hold screen mode and performing line relocation when scroll is pressed.
To perform these tasks, the microprogram needs control registers and flip-flops, counters, temporary.
stor~ge, etc. The scratchpad memory serves all these requirements. All status information is stored,
along with incoming characters, in the scratchpad silo. Figure 2-30 is a layout of the scratchpad
memory.
Figure 2-31 is a flow diagram of the microprogram operations. Top of-screen tests are performed at
line frequency rates; i.e., 60 times each second in 60Hz units (50 time~ each second in 50 Hz units). The
UART flag is checked after horizontal scans.
The keyboard is checked between displayed frames; i.e., during· vertical retrace time. If one or more
keys are pressed; the terminal transmits the code representing the depressed key to the processor.
Figure 2-32 is a simplified flow diagram of the keyboard entry subroutine. The AC register is set to
equal the highest numbered key on the keyboard, and then a KEY J command tests the flag to see if
the key is down. If the key is not down, the AC register is decremented and the flag is tested again. This
loop is repeated until a pressed key is found. Then an active key is located, the program looks up the
ASCII code for the pressed key in a table in the ROM, loads the ASCII character into the UART, and
transmits the character to the processor.
If none of the keys are down, the program will exit the routine when the AC register is equal to zero. A
jumper in the keyboard is wired to act like a pressed key whenever it is referenced. It is referenced when
the AC equals zero, meaning the keyboard was polled but no keys were down.

The identification number of the key is written into the scratchpad to prevent multiple transmissions of
the same character. Since the keyboard is polled 60 times a second, it is almost impossible not to detect
a pressed key more than once. As a first step then, the program reads the identification numbers stored
in Keyboard A and Keyboard B of the scratchpad and checks the keyboard to see if these keys are still
down. If they are, no transmission takes place during this scan. If one or both of the keys are up, the
program clears the scratchpad location associated with the key and polls the keyboard.
2-59

A LF command received from SLU 1 when the cursor is on the bottom line will cause the terminal to
scroll; that is, every line on the screen will move up one position leaving the bottom line blank-ready
to receive more characters. Information displayed on the top line is lost and will be replaced by
information previously displayed on the second line (line 1). To erase every RAM line and rewrite
these lines with the contents of the following RAM line would take too much time and be an unreasonable way to accomplish scrolling. Instead, any RAM line can be displayed as the top line of the screen.
This means that after one scroll, the top line would be RAM line 1 and the bottom line •vould be RAM
line 0. Successive scrolls would cause RAM line 2, 3, 4, etc. to be displayed as the top line and RAM
line 1, 2, 3, etc. to be displayed as the bottom line.
·
A scratchpad location is used to remember which RAM line is displayed on the top screen line. This
location, TOP LINE, contains a line number between 0 and 23 and is cleared to 0 to power-up time.
Memory location CUR Y contains the RAM line address of the cursor; location SCREEN LINE
contains the screen line address of the cursor.
The hold screen mode allows the operator to control the rate at which data from the processor enters
and leaves the screen. If left unchecked, high speed data from the processor would be displayed for a
very short time and then scrolled up and off the screen; the operator would not have enough time to
read the data. In hold screen mode, scrolling is commanded by the operator.
When the cursor is on the bottom line of the screen and a line feed comand (LF) is received from the
processor, the program stores the line feed command in the LINE FEED BUFFER of the scratchpad
and transmits the code for signal X OFF. The X OFF signal is used to request that data transmission
to the terminal be stopped. A few characters will be sent before the program receives and acts on the
request. The program stores these characters in the silo portion of the RAM.
To request more data, the operator presses SCROLL. The display program responds by scrolling the
screen and then processing the characters previously stored in the silo until the silo is empty. The
program then sends X ON to SUL 1, and data transmission is resumed until another LF is received.
When the terminal receives the code for ESC Z from the processor, it interprets this code as a request
for the terminal to identify itself. The terminal does this by transmitting ESC /K to· the processor. A
terminal with a printer option will transmit ESCjM. The code for these three characters cannot be sent
as one sequence; therefore, one character is sent after each frame displayed on the screen. The terminal
must remember what portion of the sequence has been sent. Location ID of the scratch pad is used to
store the status of the identification process. They are:
0

An ESC Z command is not pending.

135

An ESC Z has been received.

033

An ESC code has been sent to the processor.

057

A Slash(/) code has been sent to the processor.

101

A K or M code has been sent to the processor.

During the identification process, the keyboard is not polled. This is to prevent keyboard characters
from being mixed with the three-character escape sequence.
When the first character in the sequence has been sent, location IC is cleared to zero and keyboard
polling resumes.

2-60

HOST SILO

I
I

PRINTER SILO

SILO
INPUT
POINTER

XMIT
BUFFER

KEYBOARD
BUFFER
A

EQS
COUNT

SILO
COUNTER

TERMINAL
I.D.

XMIT
BUFFER

KEYBOARD
BUFFER

LF.
BUFFER

SILO
OUTPUT
POINTER

CURSOR
X

FRAME
COUNT

BELL
COUNT

CURSOR

TOP
LINE

VIDEO
LINE

PRINTER
CONTROLLER
FF

PRINTER
LINE
COUNT

VIDEO
SCAN
COUNT

PRINTER
SILO
INPUT
POINTER

EQS
LINE

PRINTER
SILO
COUNT

SCREEN
CURSOR
LINE

KEYBOARD
APPLICATION
MODE
FF

VIDEO
LINE
COUNT

PRINTER
SILO
OUTPUT
POINTER

I~
A
OUNTER

AUTO
PRINT
FF

PRINTER
X

SCROLL
COUNT

PRINTER

HOLD
SCREEN
FF

INCOMING
CHARACTER

GRAPHiCS
FF

11
08-1879A

Figure 2-30 Scratchpad Memory
2-61

RESET FLAGS
ERASE THE
SCREEN

TOP OF SCREEN
TESTS

CHECK THE KEYBOARD. TRANSMIT
A CHAR. SCROLL
THE SCREEN

YES

PROCESS THE
CHAR.

EMPTY UART
INTO SILO

DISPLAY A LINE
OF CHARACTERS

CP-2307

Figure 2-31

Microprogram Flow Diagram

2-63

STORE THE KEY
NUMBER IN
SCRATCH PAD
MEMORY

LOOK UP THE
ASCII CODE IN
THE ROM TABLES

NO
LOAD CHAR.
INTO UART
YES

CP·2308

Figure 2-32

Keyboard Entry Flow Diagram

2-64

The cursor appears as a flashing underscore on the screen on the ninth scan of one of the ten scan
character rows. Although the screen is refreshed 60 times a second, the cursor display is refreshed only
4 times a second to produce a blinking cursor. To achieve this low frequency refresh rate, scratchpad
location FRAME COUNT is preset to 160 and is incremented every time theY line containing the
cursor is to be painted on the screen. When FRAME COUNT overflows (every 15 frames), the CRT
beam is turned on, displaying the cursor, and FRAME COUNT is again preset to 160.
2.2.3

DC Power Supply

2.2.3.1 20kHz Oscillator- The 20kHz oscillator (clock) is a conventional NE555 oscillator. Timing
is determined by R18 and ClO for the time that the output is high and R19 and ClO for the time that
the output is low. The output is a 20 kHz rectangular wave. High time occurs for approximately 20 /lS.
This creates a window during which it is possible to turn off the control transistor, Q2. Q2 can never be
turned off when the clock is low.
With the output ofNE555 high, C10 is charged through R18. When the voltage across ClO reaches 2/3
Vee, th(: output of E1 drops and the discharge transistor turns on. ClO is discharged through R19 until
the voltage across C 10 drops to 1/2 Vcc. The output goes high and the discharge transistor turns off;
C 10 is again charged through R 18. C9 and C18 are decoupling capacitors.
2.2.3.2 Pulse Width Modulator -The trigger of E2 is connected through a 4.7k resistor, Rl7, to pin 3
of the clock. Whenever the clock is low, the output of the pulse width modulator is high and Q2.is on,
holding Ql (the main power switch) off. Also C11, the timing capacitor for the pulse width modulator,
is prevented from charging by forward-biased diode D19. When the clock goes high, Cll is charged
from the voltage controlled current source in the error amplifier. The control voltage of E2 is connected to the 5 V reference. Thus when the voltage across Cll reaches 5 V, the output of E2 drops, Q2
turns off, and Q1 turns on. When the clock drops to its low state, pin 3 of the pulse width modulator
goes high, turning Q2 on again and Ql off. At the same time, Cll is discharged and ready to begin the
next pulse. The pulse width is determined by the time the clock is high minus the time Cll charges. The
faster C 11 charges, the longer the pulse width.
2.2.3.3 Inverter- When Ql turns on, current flows through the primary of Tl. When Ql turns off,
the windings of Tl reverse polarity. The rectifiers in the secondaries become forward biased and
conduct, thus the energy stored while the primary was conducting is released to the filter capacitors
and loads the secondary windings. The control circuit senses the voltage at the 5 V output and adjusts
the on/ off duty ratio of Ql to maintain this output at 5 V. All other outputs remain relatively constant
also.
2.2.3.4 Short Circuit Protection - The short circuit protection circuit consists of E6, an LM339 comparator, and R29, the current sense resistor. Normally the output of the comparator is high. During an
over-current condition, the voltage drop across R29 increases enough to cause the voltage at pin 4 to
be greater than at pin 5. The comparator changes state; i.e., pin 2 drops low pulling the trigger of the
pulse width modulator to ground. The pulse width modulator output goes high to prevent the main
po~er switch from turning on. As soon as the current through R29 drops below approximately 10 A,
the! comparator output returns to a high state and normal operation resumes.

2-65

CHAPTER 3
MAINTENANCE

3.1 MAINTENANCE PHILOSOPHY
This chapter contains information necessary to isolate and repair DECstation malfunctions.
Figure 3-1 is an index to the troubleshooting procedures contained in Tables 3-1 through 3-4. Step-bystep turn on and operating instructions are followed by normal display illustrations. If these displays
are abs<:mt or incorrect, refer to the corresponding tables for troubleshooting information.
The use of the MR78 ODT is also described in Paragraph 3.2.2 to help isolate intermittent malfunctions or abnormal symptoms not provided in the troubleshooting tables.
3.2 TROUBLESHOOTING
3.2~ 1

Troubleshooting Procedures

Th~ possible equipment malfunctions listed in Tables 3-1 through 3-4 are categorized by abnormal

syil;lptoms. Corresponding causes are listed in order of probability. Corrective actions are, for the most
part, limited to the adjustments and/or substitution of major replaceable subassemblies for those
suspected to be defective.

3.2~2

MR78-BB ODT Package

Th~ MR 78-BB is a bootstrap ROM for the VT78, containing multifield ODT and a binary loader

suitable for use with the PRSOl papertape reader. It provides the Field Service Engineer with a tool to
modify diagnostics or customer software. It also allows the Field Service Engineer to generate short
prqgrams as an aid in isolating and correcting equipment malfunctions.

It is assumed that the operator is acquainted with the general operation of PDP-8 ODT programs. If

not, consult the Introduction to Programming book or the OS8 Handbook for additional ODT information.
NOTE
be able to function well
must
terminal
VT78
The
AB before it displays a
letters
the
display
to
enough
HLT message. If it does not, the ODT package can
not be run. It is possible to run ODT if there is a
HLT message after B and before C, D, or F, but a
HLT message after D indicates an extended memory
problem which might prevent ODT from running.

3-1

STEP 1
PROBLEM?

SET SYSTEM
POWER SWITCH
TOON

REFER TO TABLE 3-1
NO CURSOR
NO CURSOR ARCING NOISE
~B!<Q§f MISSING ENTIRELY
PORTION OF ABCDEF MISSING
FLICKERING DISPLAY

agc;<Q~E

NORMAL
DISPLAY

""""
.)

"'
STEP2

PROBLEM?

PRESS
START SWITCH

REFER TO TABLE 3-2
START MESSAGE NOT PRESENT

r
NORMAL
DISPLAY

START XX XX ACNQ XX

'
STEP3

PROBLEM?
LOAD
PROGRAM

TYPICAL
DISPLAY
(PERIOD I

REFER TO TABLE 3-3
PROGRAM CANNOT BE LOADED

STEP4
OPERATION

PROBLEM?
REFER TO TABLE 3-4
BAD DATA TRANSFER
DISPLAY PRESENT BUT INCORRECT
MA-0257

Figure 3-1

Guide to Troubleshooting Procedures

3-2

Table 3-1

Power On Troubleshooting Procedure

Symptom

Possible Cause

Corrective Action

No cursor.

Intensity control turned down.

Adjust intensity control (Figure 3-2).

No cursor, raster missing, DC
OK light off.

Blown fuse.

Replace fuse (Figure 3-2).

FUSE

~J\.~UJLtltLr 1

~r[[[[[[[[[[[[[[[[[

U,\1LLLLLL L

[[[[[[[[[[[[[[[[[
Mrrrrrrr[[[{[[[[[

~~LL~lLLLLL

""'

r[[[[[[[

'~U(HL[

rrrnr

( BRIGHTER

DARKER

INTENSITY
CONTROL
MA-0268

Figure 3-2 Intensity Control and Fuse Locations

3-3

Table 3-1

Power On Troubleshooting Procedure (Coot)

Symptom

Possible Cause

Corrective Action

No cursor, raster missing, DC
OK light off (Cont).

No prime power.

Restore source of prime
power.

WARNING
There are high voltages present in the power supply
and CRT. Make sure the terminal power line is unplugged and the CRT and capacitors are discharged
as shown in Figure 3-3 before handling the power
supply or CRT components. Make sure ground connection is made before discharging these points.

WARNING
MAKE SURE TERMINAL
IS UNPLUGGED BEFORE
SHORTING COMPONENTS TO
GROUND.

~f~
POWER SUPPLY

Figure 3-3

MONITOR BOARD

High Voltage Discharge Locations

3-4

MA-0267

Table 3-1

Power On Troubleshooting Procedure (Coot)

Symptom

Possible Cause

Corrective Action

No cursor, raster missing, DC
OK light on.

Anode cap disconnected.

Connect anode cap at power
supply (Paragraph 3.3.5).

Ano~e clip disconnected.

Connect anode clip at CRT
bell (Paragraph 3.3.5 and Figure 3-4) .

...

~----------1

.....

ANODE CLIP
(HIDDEN)

MA-0269

Figure 3-4 Anode Clip Locations

3-5

Table 3-1

Power On Troubleshooting Procedure (Cont)

Symptom

Possible Cause

Corrective Action

No cursor, raster missing, DC
OK light on (Cont).

Defective power supply assembly.

Replace power supply assembly (Paragraph 3.3.5).

Defective monitor board.

Replace monitor board (Paragraph 3.3.6).

WARNING
Use caution when handling the CRT to avoid shattering the tube. The CRT is an evacuated device which
can implode when broken.

No cursor, raster missing, DC
OK light on.

Defective CRT.

Replace CRT (Paragraph
3.3.8).

Defective RUT module.

Replace RUT module (Paragraph 3.3.4).

Defective DP module.

Replace DP module (Paragraph 3.3.4).

Defective keyboard.

Replace keyboard module
(Paragraph 3.3.4).

Defective character generator
module.

Replace character generator
module (Paragraph 3.3.4).

WARNING
There are high voltages present in the pov;er supply
and CRT. Mal>.e sure the terminal power line is unplugged and the CRT and capacitors are discharged
as shown in 'Figure 3~3 before handling 1he povter
supply or CRT components.

No cursor, raster present, arcing heard, DC OK light on.
Cursor present, no ABCDEF,
CPU OK light on.

_- - - - - - - - -

Defective power supply assembly.

Replace power supply assembly (Paragraph 3.3.5).

Anode cap loose.

Tighten cap (Figure 3-3).

Anode clip loose.

·Tighten clip (Figure 3-4).

Baud rate switch set
correctly.

In-

Set baud rate switch (bottom
of terminal) to 9600 baud
(Figure 3-5).

F nction switch set tn-

Set function switch (on bot-

rrectly.

·---------'--to_m_o_f_t_e_rm-in
_a-l)_t_o_f_u_n_d_u_p_le_x
position
(Figure 3-5).

3-6

lm
'

A- MATCH BELL
(BELL 103) LOCAL
B-110BAUD
C- MATCH (BELL 103)

D -600BAUD
E -1200BAUD
F -2400BAUD
G - 9600 BAUD

1- OFF LINE
2- FULL DUPLEX WITH
LOCAL COPY
3- FULL DUPLEX*
FUNCTION
SWITCH S1

*NORMAL SETTING

4-300BAUD
5-150BAUD
6-75BAUD
MA-0261

Figure 3-5

Function and Baud Rate Switches

3-7

Table 3·1

Power On Troubleshooting Procedure (Cont)

Symptom

Possible Cause

Corrective Action

Cursor present, no ABCDEF,
CPU OK light on (Cont).

Defective processor module.

Replace defective module
(Paragraph 3.J:l).

Cursor present, no ABCDEF.
CPU OK light off.

Defective processor module.

Replace' defective processor
module (Paragraph 3.3.2).

Cursor present, A only displayed.

Defective processor or memory module.

Replace module (Paragraph
3.3.2).

Cursor present, AB only displayed.

Defective processor module.

Replace defective processor
module (Paragraph 3.3.2).

Defective 1/0 distribution
panel.

Replace defective panel (Paragraph 3.3.3).

Defective processor module.

Replace defective module
(Paragraph 3.3.3).

Defective 1/0 distribution
panel.

Replace defective module
(Paragraph 3.3.3).

Cursor present, ABCD only
displayed.

Defective processor or memory module.

Replace defective module
(Paragraph 3.3.2).

Cursor present, ABCDE only
displayed.

Defective processor module.

Replace defective module
(Paragraph 3.3.2).

Cursor present, ABCDEF displayed but display flickers.

W7 jumper on RUT.

Remove W7 jumper (60 Hz
units) or insert jumper W7 (50
Hz units) (Figure 3-6).

Cursor present, ABC only displayed.

3-8'

--,

.,..., -, ...,
--,
..., --.

--.

----.

--,

...,

...,
...,
c:::::::l
....., S2®
-, -,
c:::::::l

...,

@'.::.:

-,
-,

RUT
MODULE

. . .,
.....,

S1 1

'-,
-,-, ...,...,

JUMPER W7

MA-0260

Figure 3-6 Jumper W7 Location

3-9

Table 3-2

Start Up Troubleshooting Procedures

Symptom

Possible Cause

Corrective Action

Start message not present.

Defective processor module.

Replace defective module
(Paragraph 3.3.2).

Loose or defective START
switch or cable.

Tighten or replace as required.

Defective I/0 distribution
panel.

Replace defective panel (Paragraph 3.3.3).

Table 3-3

Program Loading Troubleshooting Procedures

Symptom

Possible Cause

Corrective Action

Program can not be booted.

Defective RX78 program
loading device (if applicable).

See applicable maintenance
manual (RX78 floppy disk
drive system information).

Defective MR 78 program
loading device (if applicable).

Replace MR78.

Defective fuse (Fl) on distribution panel (MR 78 only).

Replace fuse.

Defective processor module.

Replace defective module
(Paragraph 3.3.2).

Defective memory module.

Replace defective module
(Paragraph 3.3.2).

Loose I/0 distribution panel
connector.

Tighten connector.

Defective I/0 panel.

Replace panel (Paragraph
3.3.3).

Defective 1/0 cable.

Replace 1/0 cable.

3-10

Table 3-4 Operational Troubleshooting Procedures
Symptom

Possible Cause

Corrective Action

Unable to adjust focus; display remains fuzzy.

Defective monitor board.

Replace monitor board (Paragraph 3.3.6).

Entire raster too short (Figure
3-7).

Vertical size/linearity out of
adjustment.

Adjust vertical size/linearity
control (Paragraph 3.4.1 or
3.4.3).

Unable to adjust raster or
character width.

Defective monitor board.

Replace monitor board (Paragraph 3.3.6).

Entire raster too narrow (Figure: 3-8).

Horizontal size out of adjustment.

Adjust horizontal size control
(Paragraph 3.4.1).

NOW IS THE TIME NOW IS THE TIME
NOW IS THE TIME NOW IS THE TIME
NOW IS THE TIME NOW IS THE TIME
NOW IS THE TIME NOW IS THE TIME
NOW IS THE TIME NOW IS THE TIME
NOW IS THE TIME

(SHORT RASTER)

(NORMAL DISPLAY)

MA-0254

Figure 3-7

Short Raster Indication

....,
NON IS THE TIME NON IS THE TIME
NON IS THE TIME NON IS THE TIME
NON IS THE TIME NOW IS THE TIME
NON IS THE TIME NON IS THE TIME
NON IS THE TIME NON IS THE TIME
NON IS THE TIME

NOW IS THE TIME NOW IS THE TIME
NOW IS THE TIME NOW IS THE TIME
NOW IS THE TIME NOW IS THE TIME
NOW IS THE TIME NOW IS THE TIME
NOW IS THE TIME NOW IS THE TIME
NOW IS THE T1ME

....J

(NORMAL DISPLAY)

(NARROW RASTER)
MA-0247

Figure 3-8 Narrow Raster Indicatioh
3-11

Table 3-4 Operational Troubleshooting Procedures (Coot)
Symptom

Possible Cause

Corrective Action

Unable to adjust intensity /brightness.

Defective monitor board.

Replace monitor board (Paragraph 3.3.6).

Defective power supply.

Replace power supply (Paragraph 3.3.5).

Defective CRT.

Replace CRT (Paragraph
3.4.1).

Vertical size out adjustment.

Adjust vertical size control
(Paragraph 3.4.1 ).

Vertical linearity out of adjustment.

Adjust vertical linearity control (Paragraph 3.4.3).

Defective monitor board.

Replace monitor board (Paragraph 3.3.6).

Horizontal size out of adjustment.

Adjust horizontal size control
(Paragraph 3.4.1).

Characters uneven (Figure 311 ).

Defective monitor board.

Replace monitor board (Paragraph 3.3.6).

Distance between lines uneven
(Figure 3-12).

Yoke out of adjustment.

Adjust controlling tabs on
yoke.

Lost data.

Baud rate switch set incorrectly.

Adjust baud rate to mode of
operation (Figure 3-5).

S2 not set correctly.

Set S2 in any position other
than fully clockwise position
(Figure 3-5).

Characters too short (Figure
3-9).

Characters too thin (Figure 310).

3-12

NOW IS THE TIME

HOW 18 THE TIME

(NORMAL SIZE)

(SHORT CHARACTERS)
MA-0248

Figure 3-9 Short Character Indication

NOW IS THE; TIME

NOW IS THE TIME

(NORMAL WIDTH)

(TOO THIN)
MA-0252

Figure 3-10 Thin Character Indication

NOW IS THE TIME

NOW 1S THE riME

(NORMAL DISPLAY)

(CHARACTERS UNEVEN)
MA-0255

Figure 3-11

Uneven Character Indication

NOW IS THE TIME NOW IS THE TIME
NOW IS THE TIME NOW IS THE TIME
. NOW IS THE TIME NOW IS THE TIME
NOW IS THE TIME NOW IS THR TIME
NOW IS THE TIME NOW IS THE TIME
NOW IS THE TIME NOW IS THE TIME
NOW IS THE TIME

NOW IS THE TIME NOW IS THE TIME
NOW IS THE TIME

(NORMAL DISPLAY)

(LINES UNEVEN)

NOW IS THE TIME NOW IS THE TIME
NOW IS THE TIME NOW IS THE TIME
NOW IS THE TIME NOW IS THE TIME

MA-0253

Figure 3-12

Uneven Lines Indication

3-13

Table 3-4 Operational Troubleshooting Procedures (Coot)
Symptom

Possible Cause

Corrective Action

Illegal characters generated
(Figure 3-13).

Defective character generator
board.

Replace character generator
board (Paragraph 3.3.4).

Defective RUT module.

Replace RUT module (Paragraph 3.3.4).

Baud rate switch set incorrectly.

Set baud rate switch to 9600
baud (Figure 3-5).

RUT /Character
ROM/PROM chips are incompatible.
Defective character generator
module.

Check that ROM chip is
A23002B4 series (Figure 3-14).

Defective DP module.

Replace DP module (Paragraph 3.3.4).

Defective RUT module.

Replace RUT module (Paragraph 3.3.4).

Wrong character displayed
when typed.

Defective keyboard.

Replace keyboard (Paragraph
3.3.7).

No key clicks; cursor present.

Defective RUT module.,

Replace defective module
(Paragraph 3.3.4).

No key click or cursor, raster
present.

Defective DP module.

Replace defective module
(Paragraph 3.3.4}.

Defective keyboard.

Replace keyboard (Paragraph
3.3.7) .

No key clicks; characters displayed.

Defective RUT module.

Replace defective module
(Paragraph 3.3.4).

No key clicks; characters generated wrong but legal.

Defective DP module.

Replace DP module (Paragraph 3.3.4).

Defective RUT module.

Replace defective module
(Paragraph 3.3.4).

Defective keyboard.

Replace keyboard (Paragraph
3.3.7).

Random characters generated
or screen fills with random
characters when first turned
on (Figure 3-15).

3-14

Replace character generator
module (Paragraph 3.3.4).

M23002B4 ROM

'.,. >V 1° fL.[ 1 II 1:

,___CHARACTER

MA-0250

GENERATOR

Figure 3-13 Illegal Characters Indication

D
I
MA-0270

Figure 3-14 A23002B4- ROM Chip Location

CURSOR

w
E

0
Ml

(NORMAL DISPLAY WHEN FIRST TURNED ON)

(RANDOM CHARACTERS)
MA-0246

Figure 3-15

Random Character Indication

3-15

Table 3-4 Operational Troubleshooting Procedures (Cont)
Symptom

Possible Cause

Corrective Action

No key clicks; characters legal
but distorted (Figure 3-16).

Defective .character generator
module.

Replace character generator
module (Para~r;;.;ph 3.3.4).

Entire raster tilted (Figure 3-

Incorrect yoke position.

Adjust yoke tilted on the neck
of the CRT clockwise or
counterclockwise. Make sure
the yoke is fully forward.
Tighten hold down screw.

Incorrect yoke position.

Push yoke forward to the
CRT bell as far as it will go.
Tighten hold down screw.

EIA device defective.

Replace I/0 distribution
panel.

Defecti.ve I/0 cable.

Replace cable.

Prebaud rate select switch not
set correctly.

Set baud rate select switch on
I/0 distribution panel to correct setting for device used.

Loose I/0 distribution panel
cable connector.

Tighten connector.

Defective cable.

Replace cable.

Defective processor module.

Replace processor module.

Defective LA 78 or LQP78.

Refer to the appropriate manual for troubleshooting information.

17).

Raster too large; all characters
enlarged and fuzzy (Figure 318).

Initial diagnostics good but
customer's program will not
run (SLU 2 or SLU 3 functions).

Initial diagnostics good but
LQP78 or LA78 does not operate properly.

3-16

NOW IS THE TIME

NOW \S THE TIME

(NORMAL CHARACTERS)

(DISTORTED CHARACTERS)
MA-0251

Figure 3-16 Distorted Character Indication

•

MA-0256

Figure 3-17 Tilted Raster Indication

NOW IS THE TIME
(NORMAL DISPLAY)

NOW IS THE TIME
(ENLARGED AND FUZZY CHARACTERS)
MA-0249

Figure 3-18 Enlarged and Fuzzy Characters Indication

3-17

3.2.2.1

Starting the ODT- To load and start ODT, perform the following steps:

Set the VT78 terminal power switch, located at the rear of the VT78 terminal, to the off
(down) position.

Attach the MR78-BB to the rear of the VT78. Make sure the connector is seated properly
before applying pressure. Tighten the holding screws.

Set the VT78 terminal power switch to the on (up) position.

Press the VT78 START pushbutton (even if the VT78 is printing a series ofHLT messages).
Make sure ODT is running by typing an address, followed by a slash (/). ODT should
display the contents of that location. Table 3-5 contains a summary of the ODT commands.

3.2.2.2

Running the Reader- To operate the reader perform the following:
CAUTION
Make sure that VT78 terminal power is turned off
when connecting the PRSOl cable to.prevent possible
damage to the terminal's SLU3 EIA receiver.

Attach the PRS01 reader to the auxiliary connector on the rear of the VT78 terminal (Appendix D).

Press the START switch on the VT78 terminal.

Place the papertape in the reader with the leader at the read station.

Type R or (N)R (N = number of binary tapes to be loaded)

Turn the reader on. The tape should run completely through the reader.

Turn the reader off. If the (N)R command was used, the binary loader will return to ODT.
The operator may then alter the program or start it at a specified address using the "G"
command.
NOTE
The PRSOJ is available with 300 and 2400 baud
rates. The constant in location 37777 sets the SLU 3
baud rate and is correct for 300 baud when the
START pushbutton is pressed on the VT78. If your
PRSOl has a 2400 baud rate, change this constant
from 5 to 12 (using ODT).

3-18

Table 3-5

Summary of ODT Commands

Command

Function

NNNNNj

Open location NNNNN.

Re-open latest opened location. ·

NNNN;

Deposit NNNN in currently opened location; close that location and
open the next location without typing its address.
Do not modify currently opened location; otherwise same as NNNN.

Return

Close currently opened location.

Linefeed

Close opened location; open next sequential
location.

NNNN+

Open (current location +NNNN) location.
NOTE
ODT will not automatically cross field boundaries;
instead, it will wrap in the same field.

+(plus)

Equivalent to l +.

NNNN-

Open (current location - NNNN) location.

-(minus)

Equivalent to 1-.

~· (circumflex)

Close current location. Take contents as a memory reference and open
the location referenced. If the circumflex indirect bit is set, the indirect
address calculation is also performed, and the opened location is in the
"F" field. If the instruction performs auto-indexing, the auto-index register is incremented before use.
NOTE
The op code portion of the instruction is not tested;
hence, all op codes (including lOT and OPR) are
treated as MRI instructions.

__ (underscore)

Close location, take its contents as a 12-bit address, and open that address in the "F" field.

NNNNNG

Start the program at address NNNNN. The AC and link are cleared,
the interrupt system is off, and the TTO flag is cleared. The data field is
made equal to the instruction field.

Equivalent to typing "2000."

3-19

Table 3-5 Summary of ODT Commands (Coot)
Command

Function

NNNNNB

Set up breakpoint linkage for a breakpoint at address NNNNN. Only
one breakpoint is allowed at any time. Locations 4, 5, and 6 of the
breakpoint field are used for the linkage. The old contents of these locations are lost. (See Paragraph 3.2.2.3 for restrictions on the placing of
breakpoints).

Completely remove breakpoint.

Open software accumulator.

Open software link.

NNNNC

Continue from breakpoint. Load the AC, L, INT ENABLE, data field,
and TTO flag with the values held in the software registers in ODT.
Resume program execution at the trapped instruction. Iterate past the
breakpoint NNNN-1 times. The next time the breakpoint is reached,
stop the user's program; type the contents of PC, L, AC, and MQ; and
wait for further commands.

Equivalent to lC.

Open search mask (initially 7777).

Linefeed following M

Open lower search limit (initially 0).

Linefeed following M
linefeed

Open upper search limit (initially 7777).

NNNNW

Search for NNNN. Searching starts with lower search address and ends
when upper search address has been processed. For each location in the
search range, the word from memory is ANDed with the search mask
and subtracted from NNNN. If the result is zero, the address and its
contents are printed.

Open "D" field. "D" is initially zero and holds the data field in effect at
the time of the last breakpoint. "Ds" only useage is to re-establish the
data field on "continue from breakpoint." The contents of"D" must be
an even multiple of 10 (octal); i.e., 0=20 means data field 2.

Open "F" field. Like "D," "F" is initially zero and is loaded with the
data field at breakpoint. "F" must also be an even multiple of 10 (octal). "F" is the field used in word search and in the MRI and indirect
address calculations. "F" is also the default field used when papertapes
with no field specifications are loaded. The content of "F" is ignored on
"continue."

CTRLO

Terminate output and return to keyboard input. Used for terminating
long word searches or aborting the reader routine.

3-20

Table 3-5

Summary of ODT Commands (Cont)

Command

Function

Open the register which saves the state of the interrupt enable. The
interrupt was off at breakpoint if this location contains 7777.

Linefeed following I

Open the register which saves the state of the local terminal's output
flag (the TTO flag). This register is 7777, if the TTO flag was set when
the I breakpoint was encountered.

Read one program into memory from PRS01. When the trailer is encountered, start the program running at the last address specified. The
loading defaults to the "F" field, as described in the previous paragraph. This feature allows the user to load a very large program that
might overlay ODT. The "R" feature does, however, require a final
field and origin statement to be on papertape.
Field N: This may be omitted if the last instruction was deposited in the
field of the starting address.
Starting address: This is used to define the 15-bit starting address. If
there is no checksum error, the program starts automatically.

Read N programs from the PRS01, return to ODT, and print the
checksum after each program (should be 0000). The program is loaded
into the "F" field until a field statement is encountered on the papertape. The papertape field statement then takes precedence. (See Paragraph 3.2.2.2 for details of loading programs). The programs to be
loaded must be on one contiguous tape, since there is no way to start
and stop the PRS01 software. The program will not start automatically; the "G" command must be used.

Rubout

Cancels the last command, including any digits. Types "?"

3.2.2.3 ODT Notes- Operating the START pushbutton modifies locations 00004 through 00006 of
memory (to turn off the interrupt system) and reads a fresh ·copy of the ODT /binary loader program
i~to locations 36400 through 37777. Watch for modification of 4 through 6 (20 through 23 in early
machines), if the START pushbutton is pressed after a program is loaded.
There are certain restrictions which must be observed when placing breakpoints:
1.

The breakpoint must be fetched as an instruction (e.g., it can not be an argument following a
JMS).

A breakpoint can not be placed at a CIF, RMF, RTF, or ION instruction.

A breakpoint can not be placed between CIF, RMF, or RTF and the next JMP or JMS
instruction.

A breakpoint can not be placed at the instruction following an ION instruction.
3-21

Setting a breakpoint changes locations 4, 5, and 6 of the breakpoint field. Many programs, including
OS8 USR routines, react badly when breakpoints are used in the same field. If you are experiencing
difficulty, a breakpoint without the continue feature may be simulated by placing CIF 30; ·JMP I
(6400) in the program. Although the continue feature is unusable, the contents of.all registers at the
time of breakpoint are available.
It should be noted that address 36400 is the start of the breakpoint trap routine. This address varies
from ODT to ODT and is valid for the MR78-BB version only.

This version of ODT handles the interrupt and. ITO flags, allowing the user to continue in an interrupt-driven program. The interrupt service routine in the user program must be able to handle interrupts from any field. This is a problem only in programs written for a 4k machine.
In some instances it may be desirable to use the MR 78-BB on a VT78 terminal equipped with an RX78
floppy disk drive system. The MR78-BB is wired so that it responds to the START pushbutton rather
than the internal RX78 bootstrap.
The following three-word instruction sequence can be typed into the VT78 when bootstrapping the
RX78 from ODT:
1.
2.
3.

6002 /Start here; make sure interrupt off.
6073 /PRQ; make panel request.
6200 /Starting address of the RX78 bootstrap in panel memory.

3.2.2.4 Overlaying ODT- The ODT and binary loader program is loaded into memory as described
in Table 3-6.
Papertapes can overlay the first parts of ODT and have the basic ODT functions of register examination; the register modification (i.e., nonbreakpoint starting), the breakpoint removal, and the paper-tape loader remain intact. The user must refrain from using overlapped features, however, because
the ODT dispatch table is not changed when features are lost.
Programs which overlay ODT should be loaded last. Any prior programs loaded should not modify
locations above 37000. The last program loaded (modifying 37000 through 37577) must be loaded
using "R," the automatic starting loader, since the loading of the program demolishes ODT. Under no
circumstances can papertapes be loadedinto lo.cations 37644 through 37777 since doing so will destroy
the binary loader.
Table 3-6 ODT and Binary Loader
Location

Function

36400-36577

Breakpoint, +, -, A, I, TTO flag.

36600-36777

Continue breakpoint start, L, D.

37000-37177

Word Search, , -,F.

37200-37577

ODT keyboard monitor, breakpoint
clear, nonbreakpoint start, and all
other ODT functions except "R."

37600-3777

R, NR, binary loader.
3-22

3.3 SUBASSEMBLY REMOVAL AND REPLACEMENT
3.3.1

Base Assembly (Figure 3-l9)

WARNING
There are high voltages present in the VT78 terminal. Make sure that the line cord is disconnected before attempting to remove or replace any of the
terminal subassemblies.
1.

Turn the VT78 terminal upside down.

Using a 1/4-in nut driver, turn the five base-assembly fasteners counterclockwise 90 degrees
and lift the base assembly free.

The base assembly cables are long enough to allow the base assembly to be placed behind
the unit for servicing. However, if the base assembly is to be separated completely from the
terminal, disconnect the two patch panel plugs and remove the ground lead shown in Figure
3-20.

4.
3.3.2

Reverse steps 1 through 3 to replace the base assembly.
Processor /Memory Module (Figure 3-20)

Remove the base assembly as described in Paragraph 3.3.1.

Remove the screw in the bottom of the base assembly, securing the processor/memory
module to the base.

Remove the two screws securing the processor /memory module mounting bracket to the
base assembly.

Lift the board with an upward and outward motion to disengage the processor/memory
module option panel connectors.

To separate the memory and processor boards, unscrew the five screws shown in Figure 321.

Reverse steps 1 through 4 to reassemble the processor /memory module and replace it in the
base assembly.
CAUTION
When inserting the processor /memory module in the
base assembly, make sure that the processor /memory module and option panel connectors are
aligned before applying pressure to avoid damaging
the pins.

3-23 .

0
COVER

Dr""'

REAR BASE
ASSEMBLY FASTENERS
(HIDDEN)

Figure 3-19

MA-0111

Base Assembly Removal and Replacement

3-24

MOUNTING
BRACKET
SCREWS

PATCH PANEL
CONNECTORS

'-'-'-

'-'-'-'-'-

L..L-1--l...L..
L-1-'-

' - L.. '-

t__
11::::!!:!::~~·..... I - -

L-1-L.-L-L..
.._ .... ..... .... L.. L.. ' - ' -

"""';;;:,.y,LI ~ ~- ~ ~ ~!:: ~ t~ ~ ~
LL..L..

1/0 DISTRIBUTION
------~-------Jrulll
PANELPLUG

l - '- '-

{REAR OF PROCESSOR MODULE)

PROCESSOR
MODULE

BASE
ASSEMBLY
MA-0112

Figure 3-20 Processor/Memory Module Removal
and Replacement .

3-25

CAPTIVE
SCREWS

MEMORY
MODULE

PROCESSOR
MODULE

"\-L----r-------1
®•0

c=:J

c::J

c=:J CCJ

c::J c :J

c=:J CD

c::J

c :J

c::::J [/..::::J

c:::=J

r::: J
@.

c=J
c:::=J c=J

c:n c=:J

c:::=J c::::=J

Ct..=J c=:J

c::=J c::=J

[jc=J r.::=J

c=:J c=:J

r==J

c::::J c::=J

r.::=J

c::::=J c::J

®•o
. MA-0108

Figure 3-21

Memory Board Removal and Replacement

3-26

3.3.3 1/0 Distribution Panel (Figure 3-22)
1.

Remove the base assembly as described in Paragraph 3.3.1.

Remove the processor/memory module as described in Paragraph 3.3.2~

If the terminal is equipped with an MR78 program loading device, loosen the two screws
securing the MR78 to the option panel and remove the unit.

Remove the two option panel plugs (if not already removed in Paragraph 3.3.1).

Remove all of the connector screws shown in Figure 3-22. (There are five option panel
connectors.)

Reverse steps 1 through 5 to replace the option panel assembly.
1/0 DISTRIBUTION
PANEL PLUGS

CAPTIVE
SCREWS

Figure 3-22

Option Panel Removal and Replacement

3.3.4 RUT and DP Modules
NOTE
The RUT and DP modules must be removed and replaced as a unit; they should not be separated until
they have been removed from the terminal.
1.

Remove the base assembly as described inParagraph 3.3.1.

Remove the two plastic cabie ties.

Remove the aluminum standoff.

Disconnect the monitor, keyboard, video interface, and power connectors.

3-27

MA-0104

Unscrew the nine small plastic wing nuts.

Lift the RUT and DP modules from the terminal.

To separate the RUT and DP modules, disconnect J1 and J2 by pulling the modules apart.

If the character generator is to be removed from the DP module, unplug the assembly. (The
character generator is secured to the DP module by its connectors.)

To replace the RUT and DP modules, reverse steps 1 through 8.
CAUTION
When replacing the RUT and DP modules, make
sure that connectors are aligned properly before applying pressure. Observe that color-coded wires on
both sides of the connectors match and, where indicated, pin 1 is located at the extreme left of the
connector as shown in Figure 3-23. If the character
generator has been removed, make sure the arrow on
the assembly points to the rear of the unit.
Power Supply Assembly

3.3.5

WARNING
There are high voltages present in the power supply.
Make sure that the terminal line cord is not plugged
into a source of power when servicing, removing, or
replacing power supply assemblies or components.
Using a screw driver or clip lead, discharge the filter
capacitors by shorting the capacitors to the assembly
chassis or any suitable ground. Make sure ground
connection is made first before discharging the capacitors.

Remove the base assembly as described in Paragraph 3.3.1.

Remove the RUT and DP modules as described in Paragraph 3.3.4.

Remove the three captive screws securing the rear cover and remove the cover (Figure 3-24).

Remove the ground leads (Figure 3-25}.

Disconnect and remove the cable connecting the monitor and power supply boards.

Loosen the captive screw until the latch is free enough to be rotated out of its socket.

Pull the assembly outward and slightly downward to disengage the catches in the bottom
rear of the assembly. Lift the assembly free of the chassis.

3-28

PIN 1

~ ......... 1
J1

CABLE
TIES

CHARACTER
GENERATOR

MONITOR
BOARD
CONNECTOR

RUT
.._
MODULE---..;.;....:.. L-

'-L-

STANDOFF

POWER
SUPPLY
CONNECTOR

L..

'-L-

'--

I..-

.__,__

L..

I--

.__

L--

J2
MA-0109

Figure 3-23

RUT and DP Module Removal and Replacement

3-29

GROUND
WIRES

~ \\

~~~~~L~LLULP

~r[[[[[[[[[[[[[[[[[

lU.\1U1LLl

[[[[[[[[[[[[[[[[[

""'

"rrrrrrr[[[[[[[[[

~~LL~LLLLLl

r[[[[[[[

rn_t[[L[[

~~5"-=~~~~

[[[[

POWER END MONITOR
BOARD COVER
COVER
SCREWS
MA-0106

Figure 3-24 Power Supply and Monitor Board Cover
Removal and Replacement

. 3-30

CAPTIVE
SCREW

POWER SUPPLY ·
CABLE

HIGH VOLTAGE
ANODE CAP

FASTENERS

POWER
SUPPLY

LATCH

CRT SOCKET

MA'0105

Figure 3-25

Power Supply and Monitor Board Removal and Replacement
3-31

3.3.6 Monitor Board
1.

Remove the base assembly as described in Paragraph 3.3.1.

Remove the RUT and DP modules as described in Paragraph 3.3.4.

Remove the power supply board as described in Paragraph 3.3.5.
WARNING
There are high voltages present in the power supply
and near the CRT. Make sure the terminal power
line is unplugged and the CRT and capacitors shown
in Figure 3-3 are discharged before handling the high
voltage anode clip and the CRT.

Remove the high voltage anode cap (Figure 3-25).

Press the tabs on the high voltage lead connector and withdraw the lead through the rear of
the assembly.

Remove the CRT socket.

Unscrew the clamp securing the yoke assembly and remove the yoke.

Remove the four screws securing the monitor board to the chassis and remove the board
from the terminal.

Reverse steps 1 through 8 to replace the power supply assembly.
CAUTION
When replacing the power supply cover, make sure
that the wiring is positioned so that it is not pinched
between the cover and the power supply assembly
·chassis.

3.3.7 Keyboard Assembly (Figure 3-26)
1. · Remove the base assembly as described~in Paragraph 3.3.1.

Remove the RUT and DP modules as described in Paragraph 3.3.4.

Remove the six screws securing the keyboard assembly to the terminal and remove the
assembly.

Reverse steps 1 through 3 to replace the keyboard.

3-32

CAPTIVE
SCREWS

CRT
SOCKET

YOKE CABLE
CONNECTOR

GROUND
SCREW
MA-0107

Figure 3-26

Keyboard Assembly Removal and Replacement

3-33

3.3.8

CRT Assembly (Figure 3-27)
WARNING
There are high voltages present in the power supply
and near the CRT. Make sure the terminal power
line is unplugged and the CRT and capacitors shown
in Figure 3-3 are discharged before handling the high
voltage anode clip and the CRT. Use care when handling the CRT. The CRT is an evacuated device and
could shatter if broken.

Remove the base assembly as described in Paragraph 3.3.1.

Remove the RUT and DP modules as described in Paragraph 3.3.4.

Remove the keyboard assembly as described in Paragraph 3.3.7.

Unclip the connectors from the yoke assembly.

Remove the ground lead.

Remove the four captive screws securing the CRT assembly to the terminal.

Remove the plastic spacers before removing the CRT. Make sure that these spacers are
replaced when reinserting the CRT assembly.

Slide the CRT out of the terminal.

Reverse steps 1 through 8 to replace the CRT assembly.
NOTE
Normally there are no adjustments required after the
initial manufacturing and alignment of the unit.
However, after replacing the CRT or deflection
yoke, the display must be realigned and adjusted as
directed in Paragraph 3.4.

3.4 ALIGNMENT AND ADJUSTMENT PROCEDURES
3.4.1

Video Display Adjustments
NOTE
Normally no terminal adjustments are required after
the initial manufacturing checkout and alignment of
the unit (except for the intensity control). However,
after replacing a CRT or deflection yoke, the display
must be realigned and adjusted. All adjustments are
located on the power supply /monitor boards. Set the
terminal to off-line operation and fill the screen with
characters before making any adjustments. Alignment and adjustment controls are shown in Figure 328.

3-34

. ,.

~------------1

CAPTIVE

SCREWS

,. ,.

KEYBOARD
ASSEMBLY
MA-0110

Figure 3-27 CRT Assembly Removal and Replacement

3-35

WIDTH

MONITOR
BOARD

HEIGHT

VERTICAL
LINEARITY
MA-Q259

Figure 3-28

Alignment Control Adjustment Locations

3.4.1.1 Height- Adjust the vertical-size potentiometer until the height of the display is 114 mm (4.5
in). This measurement is from the upper edge of the top character line to the lower edge of the bottom
character line (Figure 3-28).
3.4.1.2 Width- Using a nonconductive, hexagonal tipped alignment tool, adjust the iron slug in the
width coil until the width of the display measures 218 mm (8.6 in) (Figure 3~28).
3.4.1.3 Vertical Linearity- Adjust the vertical linearity potentiometer until the characters displayed
on the top line are the same size as the characters displayed on the bottom line (Figure 3-28).
3.4.1.4 Focus- Adjust the focus potentiometer until characters in all sections of the screen are sharp
and clear. Refer to Figure 3-28.

3-36

3.4.1.5 Processor Board DC OK Adjustment- To adjust the DC OK potentiometer, perform these
steps:
1.

Use a DVM measure Vee (approximately +5.0 V) across E138 pins 7 and 14 (Figure 3-29).

Subtract 4.74 V from the Vee measured in step 1:

Divide the difference by two.

Monitoring the voltage between pins 8 (+) and 9 (-) of E148, adjust the potentiometer
(Figure 3-29), until the DVM indicates the value calculated in step 3.

PIN 1

0
PIN 8

PIN 9 PIN 14

E148

DCOK
POTENTIOMETER

PROCESSOR BOARD
MA-0462

Figure 3-29

DC OK Adjustment Location

3-37

APPENDIX A
SYSTEM CHARACTERISTICS

A.l

PHYSICAL
Height
Width
Depth
Weight

A.2

14.4 in (36.6 em)
20.9 in (53.1 em)
27.2 in (69.1 em)
42 lb (19.1 kg)

FUNCTIONA L
Central Processor:
Word length
Cycle time
Memory

12 bits
2.96 (3.55) J.I.S
16,384 words NMOS R/W RAM; internal CMOS ROM for system control.

Video Terminal:
Screen format
Keyboard
Character set
Character matrix

24lines by 80 characters
Standard typewriter format with auxiliary numeric keypad
Full96 ASCII plus 32 special graphics.
7x7 dot matrix; direct cursor addressing.

Environmental:
Temperature
Relative humidity
Maximum wet bulb
Minimum dew point
Line voltage
Line frequency

10° C through 40° C (50° F through 104° F)
10% to90%
28° C (82° F)
2° C (36° F)
95 V through 127 V or 190 through 254 V
47 Hz through 63 Hz

A-I

APPENDI X B
MR78 PROGRAM LOADER

B.l GENERAL
The MR 78 program loader (Figure B-1) is an optional device which plugs into the MR78 connector on
the 1/0 distribution panel located at the rear of the VT78 terminal. Its function is to provide a convenient means of loading programs (in pseudo papertape format) into main memory via the MR 78 interface circuit described in Paragraph 2.2.1.6.
When the VT78 terminal START switch is pressed (assuming that the system has been powered-up
properly), panel memory (described in Paragraph 2.2.1.3) will check for the existence of the MR 78
device. If the device is present, its program will be loaded into main memory. If the device is not
present, panel memory will check the RX78 floppy disk drive system for an alternate source of programming information.

MA-0179

Figure B-1

MR 78 Program Loader

B-1

B.2 THEORY OF OPERATION (Figure B-2)
The presence of the MR 78 is acknowledged when the device is plugged into the VT78 terminal grounding PI BD L. This maintains CHARACTER RDY low. When the GET CHARACTER flag is set,
GET CHARACTER will also go low, clocking the 16-bit counter.
The 16-bit counter consists of four, 4-bit binary counters. The first 10 bits (ADDR 0 throughADDR
9) serve as the address for the words stored in the ROM chips. The following three bits are decoded by
a 3-to-8 line decoder to select the order in which the ROMs will be read. The switching network
minimizes power consumption by switching Vee to select the ROMs.
There are 16 ROM chips in the MR78. Each ROM is a 4096-bit read-only memory organized as 1024
words by 4 bits. The enable inputs are both maintained at ground. The outputs correspond to the data
programmed in the selected word which is, in turn, selected using the 10 address inputs.

- - - - - - - -,
I
I

ADDRESS

COUNTER

I
rBOA'R'02

r---

ENCODER

RESET

I
I

NETWORK

- - - - - -·~-1

GET
CHARACTER

I
SWITCHING

I
.

BIT4-11

ROMs

CHARACTER- +------,
ROY

P1 BD L - 1 - - - - - - 1

PROGRAM{~~
OPTOON'

PSEUDO PAPER
TAPE DATA

9
I
L-- ---- - - -

Figure B-2

MR 78 Program Loader Block Diagram

B-2

MA-0115

The ROMs are read in pairs providing 8-bit words. Each bit corresponds to a hole as in papertape
format; i.e., leader (200) followed by data/field origin statements, followed by 12-bit checksum, followed by trailer (200) statements. Field statements are identified by holes 8 and 7 (3XO, where X =
field); origin statements have hole 7 only (lYY, where YY is the first two octal digits of address
followed by a second character which contains the last two digits). Data statements have neither hole 7
nor 8.
Three jumpers are available which can be inserted to set corresponding interface lines to define the
number of programs to be loaded into main memory before reading is terminated and the program is
started. The jumper connections and the corresponding number of programs to be loaded are listed in
Table B-1.

Table B-1

Program Selection Jumper Configurations

Jumpers

Programs Loaded

OUT
OUT
OUT
OUT

OUT
OUT

IN
IN
IN
IN

OUT

IN
IN

OUT

OUT
OUT

IN
IN

OUT

B-3

2
3
4
5
6
7
8

APPENDIX C
I/0 DISTRIBUTION PANEL PIN ASSIGNMENTS

There are nine connectors interfacing the processor and memory modules with the keyboard/video
display and the outside world. These are located on the 1/0 distribution panel. Figure C1 shows the
cabling connnections. Refer to Table C-1 for individual 1/0 distribution panel connector pin assignments.

CPU

I/O POWER
DISTRIBUTION PANEL

r-----e4J3

I
I
I

2
SLU }

SERIAL
DATA

.......- - S L U 3

1/0 LOGIC

I
I

.......- - D C POWER

......,._ _ RX78 FLOPPY DISK
DRIVE SYSTEM

.......,._ _ PARALLEL 1/0

MA-0460

Figure C-1

1/0 Distribution Panel Cabling Diagram

C-1

Table C-1 1/0 Distribution Panel Pin Assignments
Connector

Mating
Connector

Signal

Electrical
Characteristics

Normally. open start switch.

60 rnA@ .4 V {when pressed).

11,12
2-4
2-5

Normally closed start switch.

60 rnA @ .4 V (when not
pressed.

2-13

SLU 1 transmitted data.

TTL output.

2-17

SLUl received.

1 TTL load.

J3
1

Ground.

Chassis ground.

Ground.

2-14

SLU2 transmitted data.

Mark = -3 V or more.

2-18

SLU2 received data.

Same as above.

Request to send.

Always> +3 V.

Ground.

Data terminal ready.

Always > +3 V.

Ground.
2

2-15

SLU3 transmitted data.

Mark = -3 V or more.
Space = + 3 V or more.

2-19

SLU3 received data.

Same as above.

Ground.

2-21

APT EN L

Normally left open-circuited.
Grounding this line causes bit
1 of the ACto set when a LAS
or OSR instruction is encountered in the program. (Bit 1 is
the "APT" bit and causes
early termination of the CPU
diagnostic followed by a jump
to the MR78 loader. Load is
4.7k + 1 TTL input.)

*These signals are loaded with 180 n to +5 V and 390 Q to ground in addition to the load specified. Tri-state
drivers sink 16 rnA @ 0.4 V, source 5.3 rnA @ 2.4 V.

C-2

Connector

Table C-1

1/0 Distribution Panel Pin Assignments (Cont)

Mating
Connector

Signal

Electrical
Characteristics

2-20

FE3

High if SLU3 receiver indicates a framing error. Framing errors are caused when a
"break" is sent to the processor by APT.

2-22

APTRST H

Driven by J5-18 when running
under APT. When driven
high, causes the PWR OK
comparator to simulate a DC
LOW condition. Hence the
processor behaves as though it
were just turned on.

1-19

Ground.

1-35

RUNL

* 1 TTL input.

1-40

ERROR L

* 1 TTL input.

1-34

INITIL

Tristate output.

1-37

XFR RQST L

* 1 TTL input/ open collector
output.

1-39

DONEK

* 1 TTL input.

1-45

DATAL

* 1 TTL input.

1-33

12 BIT 1 L

Tri-state output.

1':'41

SHIFT L

* 1 TTL input.

1-38

OUTL

Open collector driver plus*.

1-36

RUN 1 L

* 1 TTL input.

1-42

ERROR 1 L

* 1 TTL input.

1-43

INIT L

Tri-state output.

1-46

XFR RQST 1 L

*1 TTL input/open collector
out.

1-45

DONE1L

* 1 TTL input.

*These signals are loaded with 180 !1 to + 5 V and 390 !1 to ground in addition to the load specified. Tri-state
drivers sink 16 rnA@ 0.4 V, source5.3 rnA@ 2.4 V.

C-3

Connector

Table C-1

I/0 Distribution Panel Pin Assignments (Cont)

Mating
Connector

Signal

Electrical
Characteristics

1-47

DATA 1 L

*1 TTL input.

1-44

12 BIT L

Tri-state output.

1-40

SHIFT 1 L

* 1 TTL input.

1-35

OUT 1 L

Open collector driver plus*.

+12 v

No more than 150 rnA.

-12 v

No more than 150 rnA.

+5V

No more than 0.5 A.

Ground.

2-23

2-24

2-25

10
11

2-26

CHARACTER STROBE

****

RESTORE.

****

Ground.
2-27

14
15

****

Ground.

12
13

CARRIAGE STROBE
Ground.

8
9

****

Ground.

6
7

PAPER STROBE.

CHECK L

*****

Ground.
2-28

PAPER ROY L

*****

Ground.

2-29

CARRIAGE ROY L

*****

2-30

CHARACTER ROY L

*****

19
20

Ground.
2-31

PRINTER ROY L

*****

*All signals marked"*" are loaded with 180 0 to +5 V and 390 0 to ground in addition to the load specified.
Tri-state drivers sink 16 rnA@ 0.4 V, source 5.3 rnA@ 2.4 V.
****Tri-state driver sinks 32 rnA@ 0.4 V.
*****High threshold bus receiver plus 180 {}to +5 V and 390 0 to ground .

. C-4

Connector

Table C-l 1/0 Distribution Panel Pin Assignments (Coot)
Pin

Mating
Connector

Electrical
Characteristics

Signal
Ground.

21
22

2-32

LA/LQP (L/H)

Driver must sink 15 rnA.

2-33

LIFT RIBBON

Tri-state driver.

Ground.

2-35

2-36

2-37

******

DATA BIT 2
Ground.

31
32

******

DATA BIT 1
Ground.

29
30

******

Ground.

27
28

DATA BIT 0 (msb)

2-38

******

DATA BIT 3
Ground.

33
34

2-34

IN/OUT

Driver must sink 2 rnA.

2-39.

DATA BIT 4

******

Ground.

36
37

2-40

Ground.

38
39

2-41

2-42

******

DATA BIT 7
Ground.

42
43

******

DATA BIT 6
Ground.

40
41

******

DATA BIT 5

2-43

******

DATA BIT 8
Ground.

******With no connection made to the line "OUT": tri-state driver is defined under"*." With line "OUT"
grounded: one TTL input.

C-5

Connector

Table C-1

1/0 Distribution Panel Pin Assignments (Cont)

Mating
Connector

Signal

2-44

DATA BIT 9

46
47

******

Ground.
2-45

48
49

Ele~trical

Characteristics

DATA BIT 10

******

Ground.
2-46

DATA BIT 11

Ground.

1-3

+5V

4-7

Ground.

******

No more than 100 rnA.

1-32

1-31

1-30

"'"'

1-29

RESET

***

2-1

**with 15k pullup.

1-9

HOLE5

**with 15k pullup.

1-10

HOLE4

1-15

HOLE6

**with l5k pullup.

1-16

HOLE 1

***

1-17

HOLE3

1-18

HOLE2

**with 15k pullup.

1-21

CHAR READY L

1-23

HOLE7

1-24

GET CHAR L

1-26

P1 BD L

1-27

HOLE8

1-28

READ EN H

**TTL input.
***TTL output.
******With no connection made to the line "OUT": tri-state driver is defined under"*." With line "OUT"
grounded: one TTL input.

C-6

APPENDIX D
PRSOl CABLE

Detailed PRSOI cable fabrication information is shown in Figure D-1.

4
PARTS LIST
ITEM

.·

QIGITAL PART NUMBER

12~

12.09379

12.05886

12-05885

13-00295 (33011 )(owl
MA-()461

Figure D-1

PRSOI Cable

D-1

APPENDIX E
APT AUTOMATIC TEST SYSTEM CONNECTIONS

Three normally unused pins on the SLU3 connector are used to implement automatic testing of the
VT78 using the APT system (Refer to Table 1-1). These are:
Pin 11

Normally open, grounded by the APT system to indicate that the VT78 is under APT
control.

Pin 18

Connected to the framing error output of the UART handling SLU3.

Pin 25

Connected to pin 18 by the special APT connector causing the framing error signal,
produced when APT attempts to gain control of the system under test, to initiate a
RESET operation within the VT78. This reset condition is similar to that following
power-on but the presence of the APT EN bit in the status word (pin 11) causes the
built-in diagnostics to load the APT protocol from the special APT MR 78 rather than
proceed with the full system diagnostic test.

Using the APT interface signals on the SLU3 connector, the APT computer can gain control of the
VT78, regardless of the state of the machine, and initiate loading of diagnostics via SLU3.

E-1

APPENDIX F
FIELD REPLACEABLE UNITS (REPAIRS)

Unit

Part Number

Processor Module
Memory Module
1/0 Distribution Panel
Power Supply Assembly .
Monitor Board
DPModule
RUT Module
Character Generator
Keyboard Assembly
CRT Assembly
18 in. RX78-to-VT78 Cable
5 ft RX78-to-VT78 Cable
Two RX78s-to-VT78 Cable

54-12660
54-12691
54-12861
H7832
54-11444-01
54-11745
54-11743
54-11815
54-11170-4
70-10859
BC80D-1H
BC80D-5K
BC80E-

•

F-1

DECSTATION TECHNICAL MANUAL
EK-VTX78-TM-002

Reader's Comments

Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of our
publications.

What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, well
wr~~n,e~Jis~easytous~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~

What faults or errors have you found in the manual?--~~~~~~-~~~~~~~~~~-

Does this manual satisfy the need you think it was intended to satisfy? ~~~~~~~~~~~~Does it satisfy your needs?_~-~~--~~~~~~ Why? __________________________

Please send me the current copy of the Technical Documentation Catalog, which contains information on
the remainder of DIGITAL's technical documentation.

Name
Title
Company
Department

Street
City
State/Country
Zip

Additional copies of this document are available from:
Digital Equipment Corporation
444 Whitney Street
Northboro, Ma 01532
Attention: Communications Services (NR2/M15)
Customer Services Section
Order No. -~~~~~~-~-~~~-

.
-

-- -

-- -- -- -

FoldHere -

Do Not Tear- Fold Here and Staple

-· -- -- -- -- -- --

FIRST CLASS
PERMIT NO. 33
MAYNARD, MASS.
BUSINESS REPLY MAIL
NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES
Postage will be paid by:

Digital Equipment Corporation
Technical Documentation Department
Maynard, Massachusetts 01754