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ED-VT278-HR

June 1981

184 pages

Original

6.7MB

Document:	DECmate System Architecture Manual
Order Number:	ED-VT278-HR
Revision:
Pages:	184
Original Filename:	http://bitsavers.org/pdf/dec/pdp8/cmos8/DECmate/ED-VT278-HR-001_DECmate_System_Architecture_Manual_Jun81.pdf

OCR Text

EK-VT278-HR-001

DECmate
System
Architecture
Manual

digital equipment corporation • maynard, massachusetts

1st Edition, June 1981

Copyright 0 1981 by Digital Equipment Corporation
All Rights Reserved
The reproduction of this material, in part or
whole,
is
strictly
prohibited.
For
copy
information, contact the Educational Services
Department,
Digital
Equipment
Corporation,
Maynard, Massachusetts 01754.
The information in this document is subject to
c han g e
wit h 0 u t
not ice.
Dig ita 1
Equi pm e n t
Corporation assumes no responsibility for any
errors that may appear in this manual.
Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts.
DEC
DECUS
DIGITAL
Dig i tal Logo
PDP
UNIBUS
VAX

DECnet
DECsystem-10
DECSYSTEM-20
DECwriter
DIBOL
EduSystem
lAS
MASSBUS

OMNIBUS
OS/8
PDT
RSTS
RSX
VMS
VT

CONTENTS

CHAPTER 1

INTRODUCTION

1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4

DECmate General Description
•••••••••••••••••••
DECma te Opt ions •••••••••••••••••••••••••••••••••
DECmate Operating Systems ••••••••••••••••
WPS 8/278 Word Processing System
COS-3l0 Commercial Operating System
OS/278 Operating System
Specifications •••••••••••••••
VT278 Video Terminal •••••
RX02 Floppy Disk Drive
RL02 Cartridge Disk Drive •••••••••
DECmate System ••••••••••••••••••••••••••••••

CHAPTER 2

SYSTEM DESCRIPTION

2.1
2.2
2.2.1
2.2.1.1
2.2.1.2
2.2.1.3
2.2.1.4
2.2.1.5
2.2.1.6
2.2.1.7
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.3.3

General ••••••••••••••••••••••
DECmate System Overview
VT278 CPU Board
Microprocessor •••••••
• ••••
Control Panel Memory.....
• ••••
Main Memory..........
• ••••
CRT Control..........
• ••••
Real-Time Clock ••••••••••••••••••
RX278 Diskette Subsystem Control ••••••••
Printer Port •••••••••••••••••••••••••
Keyboard ••••••••••••••••••••••••••••••
Power Supply ••••••••••••••••••••••••••
Vi d eo Mo nit 0 r ••••••••••••••••••••••••••••
Option Overview ••••••••••••••••••••••••••••••
DP278 Communication Option
••••••••••••
RL278 Disk Subsystem Option ••••••••••••••
Extended Language Option •••••••••••••••••

CHAPTER 3

OPERATING PROCEDURES

3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4

General •••••••••••••••••••••••••••••••••••••••••
Controls and Indicators ••••••
• ••••••••••••
Keyboard Controls ••••••••
• ••••••••
Numeric Keypad •••••••••••••••••••••••••••
Keyboard LED Indicators ••••••••••••••••••
Rear Panel Controls and LED Indicators ••••••
iii

1-1
1-1

1-3
1-3
1-3
1-3
1-4
1-4
1-5
1-6
1-7

2-1
2-1
2-1
2-2
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-4
2-4
2-4
2-4
2-4

3-1
3-1
3-1
3-4
3-4
3-4

3.3
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.7.1

Self-Test
Power Tests
CPU OK Tests
General Tests •••••
SET-UP Mode Procedures
Change Screen Brightness
Repeat Self-Tests
LOCAL Mode ••••••
RX278 Bootstrap
RL278 Bootstrap
Print Screen •••••••••.•••••••••••••••
Terminal Mode Communciation ••••••••••
Initiating Terminal Mode I from SET-UP

3-4

.... .. ..... . 3-5

3-5
3-5
3-6
3-6
3-7
3-7
3-7
3-7
3-7
3-8

••••••••••••••••••••••••••••••••••

3-8

3.4.7.3
3.4.7.4
3.5
3.5.1
3.5.2

Initiating Terminal Mode II from SET-UP
Mode ••••••••••••••••••
Changing Parameters
Stopping Communication
Entering and Exiting SET-UP Mode
Entering SET-UP Mode
Exiting SET-UP Mode

3-9
3-11
3-11
3-11
3-11
3-12

CHAPTER 4

PROGRAMMING THE VT278

4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
4.1.10
4.1.11
4.1.12
4.2
4.2.1
4.2.2
4.2.3
4.3
4.3.1
4.3.2
4.4
4.5
4.5.1
4.5.1.1
4.5.1.2
4.5.1.3
4.5.1.4
4.5.1.5
4.5.1.6

Central Processor Unit
Accumulator ••••••••
Li nk •••••••••••••••
Multiplier Quotient Register
Program Counter •••••
Instruction Register
Stack Pointers •••••
Instruction Field •••••••••••••
Instruction Buffer
Data Field ••••••••
Instruction Save Field
Data Save Field
GT Flag
Multiplex Buses •••••
OX Bus •••••••••••••
C0 and C1 Bus
EMA2 Bus ••••••
Memory ••••••••••••
General Description
Memory Organization
Two's Complement Notation
Instr.uctions •••••••••••••
Memory Reference Instructions
AND
TAD
ISZ
DCA
JMS ••
JMP

Mode

3.4.7.2

· .. .....

.......

. . ..
... ·......... ....
..... ·.............
. . . . . . .. ....
.... .
iv

4-1
4-1
4-1
4-1
4-1
4-2
4-2
4-2
4-2
4-2
4-2
4-2
4-2
4-2
4-2
4-3
4-3
4-3
4-3
4-3
4-4
4-4
4-5
4-7
4-7
4-8
4-9
4-10
4-11

4.5.2
4.5.2.1
4.5.2.2
4.5.2.3
4.5.2.4
4.5.3
4.5.3.1
4.5.3.2
4.5.3.3
4.5.4
4.5.4.1
4.5.4.2
4.5.4.3
4.5.4.4
4.5.4.5
4.6
4.6.1
4.6.1.1
4.6.1.2
4.6.1.3
4.6.1.4

Operate Instructions ••••••••••••••••••••••••
Group 1 Operate Instructions ••••••••••••
Group 2 Operate Instructions ••••••••••••
OSR Instruction •••••••••••••••••••••••••
Group 3 Operate Instructions ••••••••••••
Input/Output Operations •••••••••••••••••••••
Programmed Data Transfer ••••••••••••••••
Programmed Interrupt Transfer •••••••••••
Direct Memory Access Transfer •••••••••••
Internal Operations •••••••••••••••••••••••••
Main Memory Control Instructions ••••••••
Memory Extension Control Instructions
Set TLS Buffer Size •••••••••••••••••••••
Load/Read Keyboard LED Pattern ••••••••••
Stack Instructions ••••••••••••••••••••••
Programming Considerations ••••••••••••••••••••••
Programming Modes •••••••••••••••••••••••••••
Normal Mode •••••••••••••••••••••••••••••
Vec to r Mode •••••••••••••••••••••••••••••
Vector Mode Priority Sequence •••••••••••
Vector Mode Caveats •••••••••••••••••••••

CHAPTER 5

PROGRAMMING STANDARD I/O DEVICES

5.1
5.2
5.2.1
5.2.2
5.2.2.1
5.2.2.2
5.2.3
5.2.3.1
5.2.3.2
5.2.3.3
5.2.3.4
5.2.3.5
5.2.3.6
5.2.3.7
5.2.3.8
5.2.3.9
5.2.3.10
5.2.3.11
5.2.3.12
5.2.3.13
5.2.3.14
5.2.3.15
5.2.3.16
5.2.3.17
5.2.3.18
5.2.3.19
5.2.3.20
5.2.3.21
5.2.3.22
5.2.3.23
5.2.3.24

Introduction ••••••••••••••••••••••••••••••••••••
Keyboard and Display Instructions •••••••••••••••
Terminal I/O Instructions •••••••••••••••••••
Terminal Emulation .•••••••••••••••••••••••••
Display Operation •••••••••••••••••••••••
Keyboard Operation ••••••••••••••••••••••
ESCape Sequences for Keyboard/Display •••••••
Cursor Position Report ••••••••••••••••••
Cursor Backward •••••••••••••••••••••••••
Cursor Down •••••••••••••••••••••••••••••
Cursor Forward ••••••••••••••••••••••••••
Cursor Position •••••••••••••••••••••••••
Cursor Up
Device Attributes •••••••••••••••••••••••
Erase in Display ••••••••••••••••••••••••
Erase in Line •••••••••••••••••••••••••••
Device Status Report ••••••••••••••••••••
Horizontal and Vertical Position ••••••••
Index . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . • . . .
Next Line •••••••••••••••••••••••••••••••
Reverse Index •••••••••••••••••••••••••••
Select Character Set ••••••••••••••••••••
Select Graphic Rendition ••••••••••••••••
Keypad Application Mode •••••••••••••••••
Keypad Numeric Mode •••••••••••••••••••••
Set Mode ••••••••••••••••••••••••••••••••
Reset Mode ••••••••••••••••••••••••••••••
Save Cursor •••••••••••••••••••••••••••••
Restore Cursor ••••••••••••••••••••••••••
Print Screen ••••••••••••••••••••••••••••
Load LEOs •••••••••••••••••••••••••••••••

. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

4-12
4-12
4-16
4-18
4-18
4-19
4-21
4-22
4-28
4-29
4-29
4-29
4-31
4-31
4-32
4-34
4-34
4-34
4-34
4-34
4-35

5-1
5-1
5-1
5-1
5-1
5-4
5-4
5-5
5-5
5-5
5-5
5-5
5-6
5-6
5-6
5-7
5-7
5-7
5-7
5-7
5-8
5-8
5-8
5-9

5-n
5-10
5-10
5-11
5-11
5-11
5-11

5.2.4
5.3
5.4
5.5
5.5.1
5.5.2
5.5.2.1
5.5.2.2
5.5.2.3
5.5.2.4
5.5.2.5
5.5.2.6
5.5.2.7
5.5.2.8
5.5.3
5.6
5.6.1

Keyboard/Display Programming Examples •••••••
Printer Instructions ••••••••••••••••••••••••••••
Real-Time Clock Instructions ••••••••••••••••••••
RX278 Diskette Subsystem ••••••••••••••••••••••••
RX278 Diskette Subsystem Instruction Set ••••
Load Command Function Codes •••••••••••••••••
Fill Buffer •••••••••••••••••••••••••••••
Empty Buffer ••••••••••••••••••••••••••••
Write Sector ••••••••.•••••••••••••••••••
Read Sector •••••••••••••••••••••••••••••
Change Density ••••••••••••••••••••••••••
Read Status •••••••••••••••••••••••••••••
Write Deleted Data Sector •••••••••••••••
Read Error Register Function ••••••••••••
Programming Examples ••••••••••••••••••••••••
Programming Considerations ••••••••••••••••••••••
Critical Interrupt Servicing ••••••••••••••••

CHAPTER 6

PROGRAMMING THE DP278

6.1
6.2
6.2.1
6.2.2
6.2.3
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.5
6.5.1
6.5.2
6.6
6.6.1
6.6.2
6.6.2.1
6.6.2.2
6.6.2.3
6.6.2.4

Introduction ••••••••••••••••••••••••••••••••••••
DP278 Interrupts ••••••••••••••••••••••••••••••••
Receiver Interrupts •••••••••••••••••••••••••
Transmitter Interrupts ••••••••••••••••••••••
Modem Change Interrupt ••••••••••••••••••••••
DP278-A Standard Communications Option ••••••••••
Asynchronous Operation ••••••••••••••••••••••
Synchronous Operation •••••••••••••••••••••••
Clocking ••••••••••••••••••••••••••••••••••••
Maintenance Mode Operation ••••••••••••••••••
Standard Communications Device Registers ••••
DP278-B Extended Communications Option ••••••••••
Synchronous Operation •••••••••••••••••••••••
Clocking ••••••••••••••••••••••••••••••••••••
Maintenance Mode Operation ••••••••••••••••••
Extended Synchronous Device Registers •••••••
DP278 lOT Instructions ••••••••••••••••••••••••••
Internal Register Instructions ••••••••••••••
Port Control, Port Status and Modem
Register Instructions •••••••••••••••••••••••
Down-Line Loading the VT278 •••••••••••••••••••••
Down-Line Loading Protocol ••••••••••••••••••
Down-Line Load Encoding Format ••••••••••••••
Leader/Trailer ••••••••••••••••••••••••••
Origin ••..•....•....•....•..•..........•
Field . . . . . . . . . . . . . . . . . . . . ~ ..•........•..
Data/Checksum

5-11
5-13
5-14
5-14
5-14
5-20
5-21
5-21
5-21
5-22
5-22
5-23
5-23
5-23
5-24
5-25
5-25

6-1
6-1
6-1
6-1
6-1
'6-1
6-2
6-2
6-2
6-2
6-2
6-13
6-13
6-14
6-14
6-14
6-23
6-23

. .... .. .. .... ... ....... ....

6-24
6-24
6-27
6-28
6-29
6-29
6-30
6-30

CHAPTER 7

PROGRAMMING THE RL278

7.1
7.2
7.3
7.3.1
7.3.2

Introduction ••••••••••••••••••••••••••••••••••••
RL278 Instruction Set •••••••••••••••••••••••••••
Addressable Registers •••••••••••••••••••••••••••
Command Register A ••••••••••••••••••••••••••
Command Register B ••••••••••••••••••••••••••

7-1
7-2
7-3
7-4
7-4

7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.8.1

Silo Buffer After Get Status ••••••••••••••••
Silo Data Buffer After a Read Header ••••••••
Word Count Register •••••••••••••••••••••••••
Break MA Register •••••••••••••••••••••••••••
Sector Address Register •••••••••••••••••••••
Error Register ••••••••••••••••••••••••••••••
Command Execution •••••••••••••••••••••••••••••••
Maintenance Command •••••••••••••••••••••••••
Reset Command •••••••••••••••••••••••••••••••
Get Status Command ••••••••••••••••••••••••••
Seek Command ••••••••••••••••••••••••••••••••
Read Header Command •••••••••••••••••••••••••
Write Data Command ••••••••••••••••••••••••••
Read Data Command •••••••••••••••••••••••••••
Read Data Without Header Check Command ••••••
Track Overrun •••••••••••••••••••••••••••

APPENDIX A

ASCII CHARACTER SETS

APPENDIX B

ENGLISH AND FOREIGN LANGUAGE KEYBOARDS

APPENDIX C

SPECIAL GRAPHICS

APPENDIX D

ALTERNATE CHARACTER ROM, STANDARD GRAPHICS

APPENDIX E

ALTERNATE CHARACTER ROM, SPECIAL GRAPHICS

APPENDIX F

DETAILED SPECIFICATIONS

APPENDIX G

PROGRAMMING CONSIDERATIONS

7-4
7-10
7-11
7-11
7-11
7-11
7-13
7-13
7-15
7-15
7-15
7-15
7-16
7-17
7-17
7-17

FIGURES
1-1
1-2
1-3
1-4
2-1
3-1
3-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
5-1
5-2
6-1
7-1
7-2

DECmate Major Components ••••••••••••••••••••••••
VT278 Dimensions ••••••••••••••••••••••••••••••••
RX02 Diskette Drive Dimensions ••••••••••••••••••
RL02 Cartridge Drive Dimensions •••••••••••••••••
DECmate Block Diagram •••••••••••••••••••••••••••
VT278 Keyboard ••••••••••••••••••••••••••••••••••
VT278 Read Panel with I/O Cover Removed •••••••••
VT278 Main Memory Organization ••••••••••••••••••
Memory Reference Instruction Format •••••••••••••
Basic Operate Instruction Format ••••••••••••••••
Group 1 Microinstruction Format •••••••••••••••••
Group 2 Microinstruction Format •••••••••••••••••
OSR Instruction Format ••••••••••••••••••••••••••
Group 3 Microinstruction Format •••••••••••••• ~ ••
lOT Instruction Format ••••••••••••••••••••••••••
RX278 Diskette Subsystem Instruction Format •••••
Error Status Register (RX2ES) •••••••••••••••••••
SCD Programming Flowchart •••••••••••••••••••••••
Basic Controller Operation Flowchart ••••••••••••
RL278 Instruction Set Format ••••••••••••••••••••

vii

1-2
1-5
1-6
1-7
2-2
3-2
3-3
4-4
4-5
4-12
4-12
4-16
4-19
4-19
4-21
5-15
5-16
6-4
7-1
7-2

7-3
7-4
7-5
7-6

Header Words Format •••••••••••••••••••••••••••••
Break MA Register •••••••••••••••••••••••••••••••
Sec tor Ad d res s Re g i s t e r •••••••••••••••••••••••••
Maintenance Command, Operational Sequence •••••••

7-10
7-11
7 - 11
7-14

TABLES
3-1
3-2
3-3
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
5-1
5-2
5-3
5-4
5-5
5-6
5-7
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15

3-6
General Self-Test Summary •••••••••••••••••••••••
3-9
Baud Rate Selection •••••••••••••••••••••••••••••
3-10
Communication Mode Selection
Group 1 Operate Instructions •••••••••••••••••••• 4-13
Microprogrammed Combinations of Group 1
Microinstructions ••••••••••••••••••••••••••••••• 4-14
Constants Generated by Microprogrammed
Group 1 Microinstructions ••••••••••••••••••••••• 4-15
Group 2 Operate Instructions •••••••.•••••••••••• 4-16
Microprogrammed Combinations of Group 2
Microinstructions ••••••••••••••••••••.•••••••••• 4-17
Group 3 Operate Instructions •••••••••••••••••••• 4-19
Main Memory Control Instructions •••••••••••••••• 4-23
Memory Extension Control Instructions ••••••••••• 4-29
Stack Instructions •••••••••••••••••••••••••••••• 4-32
Keyboard I/O Instructions •••••••••••••••••••••••
5-2
Display I/O Instructions ••••••••••••••••••••••••
5-3
Printer Instructions •••••••••••••••••••••••••••• 5-13
Real-Time Clock Instructions •••••••••••••••••••• 5-14
RX278 Diskette Subsystem Instruction Set •••••••• 5-16
Error Status Register (RX2ES) Bit Functions ••••• 5-19
Read Error Register Codes ••••••••••••••••••••••• 5-22
SCD Internal Register Addressing AC <1:3> ••••••• 6-3
SCD: ~Y~l, SYN2, or DLE Register Bit
De f 1 n 1 t 1 0 n s ••••••••••••••••••••••••••••••••••••• 6-5
SCD: Internal Status Register Bit Definitions •••
6-6
SCD: Mode Register 1 Bit Definitions •••••••••••• 6-7
SCD: Mode Register 2 Bit Definitions •••••••••••• 6-9
SCD: Command Register Bit Definitions ••••••••••• 6-11
ESD: Receiver Data/Status Register (RDSR)
Receiver Status Bit Definitions ••••••••••••••••• 6-14
ESD: Receiver Data/Status Register (RDSR)
Receiver Data Buffer Bit Definitions •••••••••••• 6-15
ESD: Transmitter Data/Status Register (TDSR)
Transmitter Buffer Bit Definitions •••••••••••••• 6-15
ESD: Transmitter Data/Status Register (TDSR)
Transmitter Status and Control Register Bit
Definitions ••••••••••••••••••••••••••••••••••••• 6-16
ESD: Parameter Control Synch/Address Register
(PS~A~).Synch/Secondary Address Register Bit
Deflnltlons ••••••••••••••••••••••••••••••••••••• 6-17
ESD: Parameter Control Synch/Address Register
(PCSAR) Mode Control Register Bit Definitions ••• 6-17
ESD: ~a~a Length Select Register (PCSCR) Bit
Deflnltlons •••••••••••••••••• ~ •••••••••••••••••• 6-19
DP278 Internal Register lOT Instructions •••••••• 6-20
DP278 Port Control, Port Status, and Modem
Register lOT Instructions ••••••••••••••••••••••• 6-21

. . . . . . . . . . . .. . . . . . . .

viii

6-16
6-17
7-1
7-2
7-3
7-4
7-5

Comparison of Binary and Down-Line Load
Formats ••••••••••••••••••••••••••••••••••••••••• 6-25
Binary and Down-Line Load Bit Definitions ••••••• 6-25
RL278 Instruction Set •••••••••••••••••••••••••••
7-3
Command Register A Bit Definitions ••••••••••••••
Command Register B Bit Definitions ••••••••••••••
Silo Buffer Bit Definitions •••••••••••••••••••••
Error Register Bit Definitions ••••••••••••••••••

PREFACE

This is a reference manual for assembly language programming of
the DECmate system. DECmate consists of the VT278 intelligent
video terminal, and a number of optional devices. It is assumed
that you already know programming and are familiar with the
assembler available on the OS/278 operating system.
This manual is organi zed in a usable order. It is not necessary
that you read the chapters sequentially. Each chapter and major
section is independent from the others. This allows reference to
specific information without frequent cross-referencing.
Chapter I provides general
hardware and software.

information about

the

DECmate

system

Chapter 2 is an overview of the major DECmate functional circuits
and options.
Chapter 3 describes the VT278 operating procedures which include
self-test, SET-UP, and terminal mode communication procedures.
Chapter 4 describes the fundamental VT278 instruction set.
Chapter 5 contains the programming information for each of the
VT278 standard devices. They include the keyboard/display, printer
port, real-time clock, and the RX278 floppy disk subsystem
interface.
Chapter 6 contains the programming
DP278 communications device.

information

for

the optional

Chapter 7 contains the programming
RL278 cartridge disk subsystem.

information

for

the optional

The appendices provide reference information such as ASCII and
graphics character sets, foreign language keyboards, detailed
system and option specifications, and programming considerations
for programmers who are converting from PDP-8 to VT278 systems.
You may also need to refer to the following documents:

•
•
•
•

DECmate Owner's Guide (AA-K330A-TA)
DECmate Technical Description (EK-VT278-TD)
DECmate Pocket Service Guide (EK-VT278-PS)
DECmate Maintenance Print Set (MP00900)

CHAPTER 1
INTRODUCTION

1.1
DECmate GENERAL DESCRIPTION
DECmate is a modular computer system, designed for use in office
env i ronments. DECmate consists 0 f a VT278 i ntell igent v ideo
terminal and a number of options, which include disk storage
subsystems and communications facilities.
All DECmate functions are controlled by a single board processor
mounted inside the terminal case. Figure 1-1 shows the major
components of DECmate. The components have the following features:

•

Central processor
instruction set

•

Main memory
memory

•

Control panel memory that supplies a second address space
outside the DECmate's normal 32K words of main memory

•

Integrated architecture that incorporates the keyboard
and video display as closely coupled peripherals

•
•
•
•
•
•

A standard serial printer port

that

executes

that contains

32K words

enhanced

PDP-8A

access

random

Up to four optional RX92 diskette drives
Optional ports supporting two serial communication lines
Up to four optional RL92 disk drives
Real-time clock
An automatic
power-up.

self-test procedure which

is executed at

1.2
DECmate OPTIONS
DECmate supports five user options. Each option can be ordered by
contacting your local DIGITAL Sales Office.
The DP278 communication option provides two programmable serial
communication ports in addition to the printer port.

1-1

CPU

IEXTENDED
I
LANGUAGE
'ROM
1
K
WORDS'
L __. __ ...J

UP TO 2 DUAL
RX02 DISKETIE
DRIVES
CRT

KEYBOARD
CONTROL

KEYBOARD
SERIAL PRINTER
REAL TIME
CLOCK

DP278
COMMUNICATIONS
IJPTION

t t
UPTO 4 RL02
DISK DRIVES

MA·7785

Figure 1-1 DECmate Major Components
The RL278 disk controller option connects up to four RL02 disk
drives to the basic DECmate system. This option allows access to
over 27 megabytes of additional mass storage.
The Extended Language ROM allows four foreign languages (in
addition to the standard United States and United Kingdom English)
to be displayed. Foreign language keyboards are available to
support each language:
French
French-Canadian
Dutch
German.
1-2

The serial printer option can be connected to the printer port on
the VT278.
The diskette drive option allows as many as four diskette drives
to be connected to the diskette interface on the VT278.
1.3
DECmate OPERATING SYSTEMS
The three operating systems available from DIGITAL for DECmate are
described in the following paragraphs.
1.3.1
WPS 8/278 Word Processing System
When used wi th wo rd process ing softwa re DECmate suppl i es a
hardware/software text processing system for office and business
use. WP5 8/278 allows the user to:

•

Prepare and edit reports which may require several drafts
before final printing.

•

Pr int form letters using a stored form document and a
list from which items, such as names and addresses, are
automatically selected.

•

Send documents via an asynchronous,
compatible communication line.

ser ial,

RS232-C

1.3.2

COS-31B Commercial Operating System
is an applications development tool for EDP users who want
to use data management functions for small to medium-size business
applications. It provides the user with:
COS-31~

•
•

An operation control monitor
An easy-to-Iearn, high level programming language
(DIBOL--Digital Equipment Corporation's Business Oriented
Language)

•

An interactive line-oriented text editor that is part of
the monitor

•

Program preparation, debugging, and production utilities.

1.3.3
OS/278 Operating System
OS/278 is a comprehensive executive for DECmate. It has extensive
appl ication software development tools and an efficient runtime
environment for producing application programs. OS/278 is
controlled through a concise command language (CCL)
that
simplifies program development and execution.
Programs stored on disks or diskettes are loaded, modified, or
executed by simple keyboard commands. OS/278 also allows program
chaining so that a complex program can be divided into a series of
smaller modules.

1-3

1.4

SPECIFICATIONS

This section contains a summary of specifications for DECmate
system components. Detailed specifications for each system device
are contained in Appendix F.

1.4.1

VT278 Video Terminal

Dimensions

See Figure 1-2

Weight
Monitor
Keyboard
Shipping weight
Display

13.6 kg (30 lbs)
2.0 kg (4.5 lbs)
18.6 kg (41 lbs)
12-inch CRT displays 7 X 9 dot
matrix characters with descenders

Format

24 lines X 80 characters
or
14 lines X 132 characters

Character set

96-character displayable ASCII
subset (upper- and lowercase,
numeric, and punctuation)

Cursor type

Blinking block character

Keyboard
General

83-key detachable unit with 1.9 m
(6 ft) coiled cord

Key layout

65-key arrangement similar to
standard typewriter keyboard with
18-key auxiliary keypad

Auxiliary keypad

18-key numeric pad with period,
minus, enter, and four
general purpose function keys
comma~

Visual indicators

Seven LEDs: two for on-line/off
line; one for data set ready (DSR)
(also user-programmable); four are
user programmable

Audible signals

Keyclick: simulates typewriter
bell; sounds upon receipt of BEL
code

I/O Interconnections
Floppy disk

37-pin female connector connects
one or two dual drives

1-4

36.Scm
(14% in.)

\...:J

\.J

1.-11.1cm
(4 3/8 in.)

24.5cm (9 5/8 in.)

---I

3O.5cm (12 in.)

2O.32cm (8 in.)

36.2cm (141/4 in.)
51.4cm (20% in.·)

I:'

41.3cm (16% in.)

I
':i'

45.7cm (18 in.)
·MEASUREMENT TAKEN WITH THE KEYBOARD PLACED FLUSH TO FRONT OF TERMINAL UNDER UNDERCUT.
MA·1991A

Figure 1-2 VT278 Dimensions
Printer

25-pin male connector

DP278 communications
controller (optional)

Two 25-pin male connectors

RL278 disk controller
(optional)

37-pin male connector

1.4.2

RX.2 Floppy Diskette Drive

Dimensions

See Figure 1-3

Weight

50 1bs (approx.)

1-5

Figure 1-3 RX~2 Diskette Drive Dimensions
Media

Each of two floppy disks supplies
one surface with 77 tracks.
Formatted capacity of 256,256
12-bit words per diskette.

Transfer rate

5~~K

Seek time

262 ms average

1.4.3

bits/sec

RLS2 Cartridge Disk Drive

Dimensions

See Figure 1-4

Weight

34 kg (75 1bs)

Media

Disk cartridge supplies two
surfaces with 512 tracks per
surface. Formatted capacity of
10.4 megabytes per cartridge.

Transfer rate

4.1 megabits/sec +1%

Seek time

55 ms average

1-6

Figure 1-4 RL92 Dimensions
DECmate System

1.4.4

Environment
Operating
Temperature
Relative humidity
Maximum wet bulb
Minimum dew point
Maximum altitude

150 to 320 C (59 0 to 99 0 F)
28 to 88 gercent
25 0 C (77 F)
2° C (36 0 F)
2.4 km (8888 ft)

Nonoperating
Temperature
Relative humidity
Maximum altitude

-35 0 to +68 0 C (-38 0 to +149 0 F)
5 to 98 percent
9.1 km (38,888 ft)

Line voltage

98--128 V rms single phase,
3 wire or
188--256 V rms single phase,
3 wire (switch-selectable)

Line frequency

47--63 Hz

Power

1-7

CHAPTER 2
SYSTEM DESCRIPTION

2.1
GENERAL
This chapter provides a brief functional description of the
DECmate system. More detailed information on DECmate and its
associated components is found in the DECmate Technical Description and the DECmate Maintenance Print Set.
2.2
DECmate SYSTEM OVERVIEW
Figure 2-1 is a block diagram of DECmate. The following discussion
describes each functional block of the diagram.
2.2.1
VT278 CPU Board
The CPU board controls all receiving, sending, and display
functions within the terminal. It receives data from the:
Keyboard
RX02 diskette drives
Printer (XON-XOFF data control characters)
Communication lines if the DP278 option is installed
RL02 disk drives if the RL278 disk subsystem option
installed.

The CPU board sends command information and data to the:
Keyboard
Video monitor
Serial printer
RX02 Diskette drives
Communication lines if the DP278 option is installed
RL02 disk drives if the RL278 option is installed.
The CPU board also has two LEDS:
1.

PWR OK lights to indicate
present and within tolerance

that

the

voltages

are

CPU OK blinks at a 1 Hz rate to indicate that the CPU is
functional.

The CPU board contains the following major circuits. The circuits
are described in the following paragraphs.

2-1

VIDEO
MONITOR
BOARD

VIDEO
DISPLAY
SCREEN

,---

CPUBOARDJ

I ~
I

SERIAL
PRINTER

I
I

RX02
DISKETTE
DRIVES

MAIN
MEMORY
32K

CPU OK
~ INDICATOR

I
I
KEYBOARD

REAL
TIME
CLOCK

COMMUNICATION
LINES

KEY
BOARD

RL02
DISK
DRIVES

L_C:R~_

_____ ..J
POWER
SUPPLY

AC
INPUT
MA·6713

Figure 2-1 DECmate Block Diagram
Microprocessor
Control panel memory
Main memory
CRT control
Real-time clock
RX278 diskette subsystem control
Printer port
2.2.1.1 Microprocessor -- The 6120 microprocessor is a high speed
CMOS processor that executes the VT278 instruction set. The
microprocessor has a dual purpose in the VT278:
1.

It executes
memory.

the

user

program

It uses a second memory address space called control
panel memory to control a video display and keyboard.
Special interrupts suspend the user program and transfer
control to code in control panel memory. This operation
is transparent to the user and the user program.
2-2

from

the

32K

word

main

2.2.1.2 Control Panel Memory -- Control panel memory is a second
32K word memory address space outside the VT278's normal 32K word
range. The added memory space allows rapid context switching. The
32K words of control panel memory address space is used for the
following functions:
Self-test
Terminal I/O emulation
Floppy and auxiliary bootstrap
Optional foreign language display
Video display buffer memory
CRT control registers.
2.2.1.3 Main Memory -- The basic VT278 includes 32K l2-bit words
of MOS random access memory.
2.2.1.4 CRT Control -- The display portion of the VT278 consists
of a portion of control panel memory, a dedicated CRT controller,
and a CRT. It displays either 24 rows of 89 characters or 14 rows
of 132 characters. Increased intensity, underscore, blink, or
reverse video in any combination can be assigned to each character
on an individual basis. These and other display functions are
controlled by ESCape sequences passed from the user program as
part of the normal terminal I/O. The ESCape sequences are listed
in Chapter 5.
2.2.1.5 Real-Time Clock
The real-time clock supplies the
programmer wi th an event clock. The clock is crystal controlled
with a frequency of 199 Hz and a basic accuracy of 9.91 percent.
The instruction set is given in Chapter 5.
2.2.1.6 RX278 Diskette Subsystem Control
A single 37-pin
connector at the rear of the VT278 connects one or two dual RX92
diskette drives. The instruction set for the diskette control is
discussed in Chapter 5.
2.2.1.7 Printer Port -- A 25-pin connector at the rear of the
VT278 connects to a variety of EIA serial printers. The baud rate
is set to 9699 when power is turned on. It may be changed to a
speed of 59 to 19299 baud under program control. The instruction
set is given in Chapter 5.
2.2.2
Keyboard
The keyboard connects to the VT278 CPU board via a 3-wire cable.
The cable supplies +12 Vdc and ground to power the keyboard logic.
The remaining wire is a bidirectional serial communication line.
It carries command information (requests for keyboard data, LED
information, and bell commands) from the VT278 CPU board to the
keyboard. It also carries a unique address from the keyboard to
the VT278 CPU board for each key pressed.
2.2.3
Power Supply
The power supply accepts either 120 or 229/240 Vac input. Voltage
input is selected with a slide switch on the VT278 rear panel. A
second swi tch indicates whether the input frequency is 50 or 69
Hz. The power supply generates +5 Vdc and +12 Vdc for use by the
VT278 terminal logic.
2-3

2.2.4
Video Monitor
The video moni tor accepts data from the CPU board and power from
the power supply. From these inputs it develops signals that
display data on the CRT screen. The video monitor also contains
all video adjustment controls.
2.3
OPTION OVERVIEW
The DP278 and RL278 are single board options which install
directly into the VT278 terminal enclosure. The extended language
option is a ROM (read only memory) which inserts into the CPU
board.
2.3.1
DP278 Communication Option
The
DP278
communication
option
provides
two
synchronous/asynchronous serial communication lines with full
modem control.
In asynchronous mode line speed is fully
programmable. In synchronous mode, line speed is determined by the
modem or the VT278 to a maximum of 9600 baud. The DP278 also
contains firmware to simulate a simple I/O terminal with full
modem control. Two versions of the DP278 are available:
1.

DP278-A provides two programmable
with full modem control;

communication

lines

DP278-B is similiar to DP278-A with additional circuitry
to support bit synchronous (BITSTUFF) operation.

Run-time characteristics for each port may be chosen as follows:

•
•
•
•
•
•
•

Character length: 5, 6, 7, or 8 bit
Number of stop bits: 1, 1.5, or 2
Parity: odd, even, or none
Operating mode: half duplex or full duplex
Clocking: synchronous or asynchronous
Protocol: byte-oriented or optional BITSTUFF
Line speed: 50, 75, 110, 134.5, 150, 300, 600, 1200,
1800, 2000, 2400, 3600, 4800, 7200, 9600, 19200 baud

The instruction set for the DP278 is given in Chapter 6.
2.3.2
RL278 Disk Subsystem Option
The RL278 disk controller controls up to four RL02 disk dr i ves.
The RL278 offers fully programmable DMA addressing. Up to 4096
words (programmable for 8 bits or 12-bits) may be transferred at
one time. The instruction set for the RL278 is given in Chapter 7.
2.3.3
Extended Language Option
This option is a ROM added to the basic CPU board. The ROM becomes
part of the 32K addressing range of control panel memory and
implements specific keyboard and display translation for up to
seven languages.

2-4

CHAPTER 3
OPERATING PROCEDURES

3.1
GENERAL
This chapter describes the VT278 operator controls and indicators
and a number of procedures for functions such as self-test,
SET-UP, and system initialization.
3.2
CONTROLS AND INDICATORS
This section describes the controls and indicators on the VT278
keyboard (Figure 3-1) and on the VT278 rear panel (Figure 3-2).
3.2.1

Keyboard Controls

SET-UP
This key is used to enter and exit SET-UP mode.
describes SET-UP mode and its options.

Paragraph

~
~

3.4

Cursor Control Keys
In local mode, each of these keys generates an ESCape code
sequence that moves the cursor in the direction shown. In SET-UP
mode, the f and t keys are used to . increase and decrease screen
brightness.

Backspace
This key transmits a backspace code

(~1~8)

Delete
This key transmits a delete code (177 8 ).

Return
This key transmits a carriage return (CR) code
3-1

(~158).

I
~

MA-6012

Figure 3-1

VT278 Keyboard

COMM 1
CONNECTOR

FLOPPY DISK
CONNECTOR

MAIN
FUSE
PRINTER
CONNECTOR

POWER
SWITCH

POWER O.K.
INDICATOR --;::~-411

MODEL AND
SERIAL NUMBER
LABEL

CPU O.K.
INDICATOR

POWER CORD
CONNECTOR

KEYBOARD
CONNECTOR
LINE
FREQUENCY
SELECTOR
SWITCH

COMMO
CONNECTOR

Figure 3-2

VT278 Rear Panel With I/O Cover Removed

Linefeed
This key transmits a linefeed (LF) code (012 8 ).

~
~ Shift

When pressed, this key enables the uppercase function of all keys.
If a key does not have an uppercase function the SHIFT key is
disregarded.

[§!J

Control
This key when pressed in combination with another key, generates a
control character code.

0T8b

This key transmits a tab code (IlIa).

rr:n

~ ESCape

This key transmits an ESCape code (033 S.).
3-3

3.2.2
Numeric Keypad
The numeric keypad enters numbers in calculator fashion. Each key
generates the same character as the corresponding numeric key on
the main keyboard. The ENTER key corresponds to the RETURN key.
These keys may also be used as special function keys when the
numeric keypad is set to application mode.

PFl--PF4
Programmed Function Keys
Each of these programmed function keys produces an ESCape
sequence that can have special meaning in a user program.

3.2.3

code

Keyboard LED Indicators

DSR and LI--L4
These five LEDs can each be turned on -and off under program
control by using the ESCape code sequences described in Chapter 5.
ON LINE
Th i sLED is controlled by VT278 firmware and is turned on after
the successful completion of the VT278 self-test. The LED is off
if any of the fatal self-tests fail or when the VT278 is in local
mode.
LOCAL
This LED is controlled by VT278 firmware and is only turned on
when the VT278 is in LOCAL mode. To enter LOCAL mode, you must
first be in SET-UP mode, as described in paragraph 3.4.

3.2.4

Rear Panel Controls and LED Indicators

POWER switch
Push this two-position switch UP to turn power on and DOWN to turn
power off.
PWR OK
This LED lights if the VT278 passes its power supply tests during
self-test. The LED does not light if the power supply is not
operating correctly.
CPU OK
This LED blinks once per second if the VT278 completes a very
basic set of tests. If an error in any of these tests occurs, the
LED may be ON or OFF. Either continuous condition indicates a
basic failure.
3.3
SELF-TEST
A self-test mode in the VT278 automatically tests the condition of
the VT278 when power is turned on. To turn power on, push the
POWER switch on the VT278 rear panel to the UP position (Figure
3-2) •

3-4

After the basic tests, there are two categories of self-test
errors: fatal, and nonfatal. Fatal errors indicate that the VT278
is inoperable because of an internal failure in, for example,
memory or the power supply. Fatal errors prevent operation of the
VT278.
Nonfatal errors indicate that the printer port, real-time clock,
or interrupt system are malfunctioning. The VT278 is still
operational even though a nonfatal error condition exists.
However, any user program that attempts to use the feature that
caused the nonfatal error may produce unpredicatable results.
You can determine the success or fa il ure of VT278 sel f-tests by
watching the CPU OK and PWR OK LEOs on the VT278 rear panel
(Figure 3-2), the keyboard LEOs in Figure 3-1, and the display.
3.3.1
Power Tests
When power is appl ied to the VT278 (POWER swi tch up), the power
supply first tests to see that all its output voltages are within
tolerance. If they are, the PWR OK LED on the rear panel lights.
If PWR OK does not light, the remaining tests will not be
performed.
3.3.2
CPU OK Tests
The following three tests are performed after the power test. If
anyone of the tests fails, CPU OK lights continuously, and the
remaining tests will not be performed.
Tl--control panel ROM memory checksum test
T2--control panel RAM memory read/write test
T3--keyboard response to scan initiation command
3.3.3
General Tests
The tests in this group are summarized in Table 3-1. The success
or failure of each test can be determined by watching the CPU OK
LED and keyboard LEOs. Table 3-1 shows the status of the LEOs in
the event of a test failure. Tests T·4 through T9 produce fatal
errors; tests T10 through T12 produce nonfatal errors.
If the VT278 passes all tests, CPU 01< bl inks, the word SET-UP
appears in blinking bold characters at the bottom of the display,
and only ON LINE on the keyboard lights.
If any of the
continuously.

basic

tests

Table

3-1

fails,

CPU

lights

If all fatal error tests pass, but one of the nonfatal errors
occurs, CPU OK blinks, the word SET-UP appears at the bottom of
the display, and the LEOs determine the failed test.
In Table 3-1, "X" means the LED is on, "0" means the LED is off.
Notice there are seven LEOs as shown in Figure 3-1.

3-5

Table 3-1
Test
No.

General Self-Test Summary

Description

CPU OK
LED

LEOs

Screen
Display

Fatal Error Tests

Display buffer memory

o XX XX XX

None

CRT controller

o XXXXX 0

None

Main memory read/write

o X X X X 0 X

None

Second main memory test

o X X XX 0 0

None

HLT instruction or

o XX X 0 XX

None

Panel request failure

o XX X0 X 0

None

Nonfatal Error Tests
Tl0

Printer port loopback

Blinks

o X X X 0 a X

SET-UP

TIl

Real-time clock

Blinks

o X X X 000

SET-UP

Tl2

Printer and real-time
clock

Blinks

o XX 0 XXX

SET-UP

Undefined interrupt

Blinks

o X X 0 X X 0

SET-UP

T13

X=LED on
O=LED off
3.4
SET-UP MODE PROCEDURES
When the self-tests described in Paragraph 3.3 are completed, the
VT278 is in SET-UP mode and the word SET-UP appears at the bottom
of the display screen. You can enter and exit SET-UP mode during
normal system operation, as described in Paragraph 3.5. The
following paragraphs describe the functions you can perform in
SET-UP mode.
3.4.1
Change Screen Brightness
You can change the display screen brightness as follows:
1.

To increase brightness press

T (cursor up).

To decrease brightness press

(cursor down).

Both keys auto-repeat and continue to step the brightness toward
maximum or minimum intensity if you hold the key down. There are a
total of 16 intensity levels (0 to maximum). When power is turned
on to the VT278, the intensity is set at mid-point.

3-6

3.4.2
Repeat Self-Tests
You can repeat the self-tests described
pressing the III key while in SET-UP mode.
SET-UP mode when the tests are completed.

in Paragraph 3.3
The VT278 returns

by
to

3.4.3
LOCAL Mode
LOCAL mode allows you to fully test the keyboard and display by
typing characters and ESCape code sequences on the keyboard and
verifying the results on the display screen. If you enter SET-UP
mode and LOCAL mode during normal system operation, (paragraph
3.5), the characters you type on the keyboard are sent directly to
the screen. They are not sent to any user program that might be
running in main memory.
To enter LOCAL mode while in SET-UP mode:

Press the 9 key.
The ON LINE LED turns off and the LOCAL LED turns on.

Press the SET-UP key.
The word SET-UP disappears from the display screen, the
cursor moves to the home position, and you can begin
typing on the keyboard.

To exit LOCAL mode and return to SET-UP mode:

Hold down the CTRL key, press the SET-UP key; then
release both keys.
The word SET-UP reappears at the bottom of the display
screen.

Press the 9 key.
The LOCAL LED turns off and the ON LINE LED turns on.

3.4.4
RX278 Bootstrap
If the VT278 system has an RX278 diskette subsystem, you can
bootstrap an operating system (e.g., COS-3ll2J) from floppy disk
dr ive I2J by pressing the 2 key while in SET-UP mode. The word
SET-UP disappears from the screen, the cursor moves to the home
position, and a message from the operating system appears on the
screen. At this point the VT278 is no longer in SET-UP mode but is
under control of the operating system.
3.4.5
RL278 Bootstrap
If the VT278 system has an RL278 disk subsystem, you can bootstrap
an operating system (e.g., COS-3ll2J) from hard disk dr ive I2J by
pressing the 6 key while in SET-UP mode. The word SET-UP
disappears from the screen, the cursor moves to the home position,
and a message from the operating system appears on the screen. At
this point the VT278 is no longer in SET-UP mode but is under
control of the operating system.
3.4.6
Print Screen
When the VT278 is in SET-UP mode, you can print the contents of
the display screen by pressing the 3 key. A pr inter must be
3-7

connected to the serial printer port. The printer port is
initially set to 9600 baud during self-test, but the baud rate can
be changed under program control (see Chapter 5).
3.4.7
Terminal Mode Communication
The VT278 has two terminal mode operations when equipped with the
DP278 communication option:

Terminal mode I requires a hardwired connection between
the DP278 and a host computer. In thi s mode, the VT278
operates similar to a VT100 video display terminal.
Connections must be made from communication port 0 and
involve the following signals.
Signal Name
Transmitted data
Received data
Signal ground
Protective ground*

Connector
Pin
2

3
7
1

EIA
RS232C
BA
BB
AB
AA

EIA
RS449
SD
RD
SG

CCITT
V24
103
104
102
101

DIN
66020
Dl
D2
E2
El

* Optional connection
2.

Terminal mode II is similar to mode I, but the connection
between the DP278 and the host computer must be made via
a modem. The modem must be connected to communication
port 0. Configuration information for matching the DP278
to a selected modem is incl uded in the DECmate Pocket
Service Guide.

Both modes permit a program to be down-line loaded from the host
computer to the VT278. Programming details for down-line loading
are provided in Chapter 6.
3.4.7.1 Initiating Terminal Mode I from SET-UP Mode -- The DP278
must be installed in the VT278 and hardwired to the host computer.
Pressing the 4 key causes the word SET-UP to disappear from the
screen and puts the VT278 into II simple terminal mode. II In thi s
mode any key pressed on the keyboard is transmitted via
communication port 0, and any c'haracter received as input from
port 0 appears on the screen.
When you press the 4 key, the following occurs:
1.

The DP278 enters Parameter SET-UP mode. A parameter
screen is displayed which allows you to change the baud
rate and/or the communication mode. The parameters may be
changed by typing a number from Table 3-2 for the baud
rate and a letter from Table· 3-3 for the communication
mode.

To exit Parameter SET-UP mode, press the RETURN key.

3-8

Table 3-2

Baud Rate Selection
Press
Key

Rate

110*
300
600
1200
2400
4800

3
4

5
6

* Communication baud rate defaults to 300
when alternate baud rate not specified.
3.

The DP278 responds by displaying the word CONNECTED in
the upperleft corner of the screen.

The VT278 will now function as a
the host computer.

terminal connected

3.4.7.2 Initiating Terminal Mode II from SET-UP Mode -- Pressing
the 5 key with the DP278 installed causes the word SET-UP to
disappear from the screen and allows the VT278 to perform similar
to terminal mode I. The main difference is that in terminal mode
II the DP278 provides the modem control signals required for
communicating through a modem.
When you press the 5 key, the following occurs:
1.

The DP278 enters Parameter SET-UP mode. A parameter
screen is displayed which allows you to change the baud
rate and/or the communication mode. You can change the
parameters by typing a numbe~ from Table 3-2 for the baud
rate and a letter from Table 3-3 for the communication
mode.

To exit Parameter SET-UP mode, press the RETURN key.

The DP278 responds by displaying the word CALL in the
upperleft corner of the screen. This reminds you to dial
the host computer and make the telephone connection via
the modem.

NOTE: You must press the RETURN key in response to the CALL
message. This causes the DP278 tQ-Fry-to-connect-to-[h-e-nost.
After you press RETURN, you have 30 seconds to complete the call.
4.

The DP278 attempts to complete the connection. When
does, the word CONNECTED appears below the word CALL.

The VT278 now functions
host computer.

the

as a

3-9

terminal connected

Table 3-3

Communication Mode Selection

Mode

Press
Key

No parity, 1 stop bit,
8 data bits, 80 display columns *

No parity, 1 stop bit,
8 data bits, 132 display columns

No parity, 2 stop bits,
8 data bits, 80 display columns

No parity, 2 stop bits,
8 data bits, 132 display columns

Odd parity, 1 stop bit,
7 data bits, 80 display columns

Odd parity, 1 stop bit,
7 data bits, 132 display columns

Odd parity, 2 stop bits,
7 data bits, 80 display columns

Odd parity, 2 stop bits,
7 data bits, 132 display columns

Even parity, 1 stop bit,
7 data bits, 80 display columns

Even parity, 1 stop bit,
7 data bits, 132 display columns

Even parity, 2 stop bits,
7 data bits, 80 display columns

Even parity, 2 stop bits,
7 data bits, 132 display columns

* Communications mode defaults to no parity,
1 stop bit, 8 data bits, 80 display
columns (letter A) when alternate mode not
specified.

3-10

3.4.7.3 Changing Parameters
You may want to return to
Parameter SET-UP mode to make changes after you are connected to
the host computer.
1.

Type CTRL-K, RETURN

Make the desired changes per Tables 3-2 and 3-3

Press RETURN.

The VT278 returns to the point it was at before you typed CTRL-K.
3.4.7.4
link:

Stopping Communication -- To disconnect the communication

Type CTRL-K

Press the D key.

The communication line
Parameter SET-UP mode.

disconnected

and

you

are

back

3.5
ENTERING AND EXITING SET-UP MODE
You can enter SET-UP mode from the keyboard when the VT278 system
is under control of a user program. Then, any of the SET-UP
procedures in Paragraph 3.4 can be performed. You can also enter
SET-UP mode directly from a user program by executing a PR2 memory
control instruction as described in Chapter 4.
3.5.1
Entering SET-UP Mode
To enter SET-UP mode from the keyboard:
1.

Hold down the CTRL
release both keys.

key,

press

The bottom row of the
bottom row is cleared.

The word SET-UP appears at the left of the bottom row in
bold, blinking characters.

Any of the SET-UP functions in Paragraph 3.4 can now be
performed.

display

3-11

the
is

SET-UP

saved,

and

key;
then

then
the

3.5.2
Exiting SET-UP Mode
To exit SET-UP mode:
1.

Press the SET-UP key.

The bottom line of the display that was saved and erased
is restored to the screen.

The VT278 returns control to the user prog ram
interrupted when SET-UP mode was entered.

that was

NOTE: Indiscriminate use of this feature may cause certain user
programs to lose data from a serial TTne since norffiaT Interrupts
are inhibited during SET-UP mode.

3-12

CHAPTER 4
PROGRAMMING THE VT278

4.1
CENTRAL PROCESSOR UNIT
The VT278 central processor unit (6120 CPU) is comprised of 12
special purpose registers, control logic, and an arithmetic
logical unit (ALU). The ALU performs both arithmetic and logical
operations such as AND, TAD, and logical OR. The following
paragraphs describe each special purpose register in the CPU.
4.1.1
Accumulator
The accumulator (AC) is a 12-bit register that performs arithmetic
and logical operations. Data words may be fetched from memory to
the AC or stored from the AC into memory. Arithmetic and logical
operations involve two operands, one held in the AC and the other
fetched from memory. The resu1 t of the operation is left in the
AC. The AC may be cleared, complemented, tested, incremented, or
rotated under program control. The AC also serves as the
input-output register for programmed I/O.
4.1.2
Link
The link (L) is a I-bit register that serves as a high-order
extension of the AC. It is used as a carry register for 2' s
complement ari thmetic. A carry out of the ALU complements the
link. The link may be set, cleared, or complemented under program
control. It may also be rotated left or right as part of the
AC.
4.1.3
Multiplier Quotient Register
The multiplier quotient (MQ)
is a program accessible l2-bit
temporary register. The contents of the AC may be transferred to
the MQ for temporary storage. The MQ can be ORed with the AC and
the result stored in the AC. The contents of the AC and the MQ may
also be exchanged.
4.1.4
Program Counter
The 12-bit program counter (PC) contains the address of the memory
location from which the next instruction is normally fetched.
Dur ing an instruction fetch, the PC is incremented by 1. When
there is a branch to another address in memory, the branch address
is set into the pc. Branching normally takes place under program
control. A skip (SKP, SMA, SZA, SNL) instruction further
increments the PC by 1, thus causing the next instruction to be
skipped. The skip instruction may be unconditional or conditional
on the state of the AC and/or link. During an input-output
operation, a device can also cause the next instruction to be
skipped.
4-1

4.1.5
Instruction Register
During an instruction fetch, the 12-bit instruction register
contains the instruction to be executed by the 6129.

(IR)

4.1.6
Stack Pointers
The stack pointers (SPI and SP2) are two 12-bit registers which
hold the address of the next stack storage location. PPCX or PACX
instructions cause post-decrement of the contents of stack pointer
SPX. RTNX or POPX cause a pre increment of the contents of the
stack pointer. Stack pointers are loaded from, and read into, the
AC. They may also be used as program-controlled temporary
registers.
4.1.7
Instruction Field
The 3-bit instruction field (IF) holds the memory field from which
all instructions, all indirect address pointers, and all directly
addressed operands are obtained. It may be read into the AC, and
loaded from the instruction buffer (IB). It is cleared by RESET.
4.1.8
Instruction Buffer
The 3-bit instruction buffer (IB) serves as a holding register for
instructions which change the IF. Instead of changing the IF
directly, field bits are loaded into the IB, and transferred to
the IF at the next JMP, JMS, RTNl, or RTN2. The IB may be loaded
from instruction bits, from the AC, or from the ISF. The IB is
cleared by RESET.
4.1.9
Data Field
The 3-bi t data field (OF) holds the memory field from which all
indirectly addressed operands are obtained. The OF may be loaded
from instruction bi ts, from the AC, or from the DSF. It may be
read into the AC. It is cleared by RESET.
4.1.19
Instruction Save Field
The 3-bit instruction save field (ISF) is loaded with the contents
of~the IF upon granting an interrupt. The ISF may be read into the
AC. It is cleared by RESET.
4.1.11
Data Save Field
The 3-bit data save field (DSF) is loaded with the contents of the
DF upon granting an interrupt. The OSF may be read into the AC. It
is cleared by RESET.
4.1.12
GT Flag
The GT flag is a I-bit register that can be loaded or read under
program control.
4.2
MULTIPLEX BUSES
There are three buses internal to the VT278 that carry data and/or
instructions. The buses and their functions are discussed in the
following paragraphs.
4.2.1
DX Bus
The l2-bit input/output multiplexer bus handles data, address and
instruction transfers between the 6129 and the main memory, panel
memory, and peripheral devices on a time-multiplexed basis.
4-2

4.2.2
C8 and Cl Bus
The C'" and Cl bus is a bidirectional time-multiplexed bus that
transmits the two MSBs of the extended memory address (instruction
or data field), and the status of the link (L) and GT flags. This
bus also receives I/O device transfer control commands.
4.2.3
EMA2 Bus
EMA2 is an output bus from the 6128 that transmits the LSB of the
extended memory address and the status of the interrupt enable
flip-flop (IEFF) on a time-multiplexed basis.
4.3
MEMORY
There are three general classes of instructions:
Memory reference instructions (MRI)
Operate instructions (OPR) and
Input/output instructions (lOT).
rOT instructions are further subdivided into
instructions and internal control instructions.

external

I/O

4.3.1
General Description
Instructions are l2-bit words stored in memory. The 6128 makes no
distinction between instructions and data. It can manipulate
instructions as stored variables or execute data as instructions
when programmed to do so.
Before proceeding further, we will discuss the memory organization
with which the 6120 interfaces.
4.3.2
Memory Organization
The 612'" has an addressing capacity of 32,768 l2-bit words. The
memory system is organi zed into 4896 word groups, called memory
fields, as shown in Figure 4-1. The first 4896 words of memory are
field 0. If a full 32K block of memory is installed, the uppermost
memory field is numbered 7. Two 32K word blocks of memory may be
connected to the 612"'. One of these blocks is main memory and the
other is panel memory. In any given memory field, every location
has a unique 4-digit octal (12-bit binary) address, 8888--7777
(0"'00--4095 decimal).
Each memory field is subdivided into 32 pages of 128 words each.
Memory pages are numbered sequentially from page 88, containing
octal addresses 8080--8177, to page 37 (octal), containing octal
addresses 7698--7777. The most significant 5 bits of a 12-bit
memory address denote the page number; the 7 low order bi ts
specify the address of the memory location within the given page.
During an instruction fetch cycle, the 6128 fetches the
instruction pointed to by the instruction field and the pc. The PC
is incremented by 1. The pc now contains the address of the 'next'
sequential instruction.

4-3

PAGE 37

LOC 177

PAGE 36

LOC 176

,FIELD 6

PAGE 35

LOC 175

FIELD 5

FIELD 7

FIELD 4
-~

FIELD 3
FIELD 2
FIELD 1
FIELD 0

32K MEMORY
(10S FIELDS)
00

------

PAGE 10

LOC 010

PAGE 7

LOC 007

PAGE 6

LOCOO6

PAGE 5

LOC005

PAGE 4

LOC004

PAGE 3

LOC 003

PAGE 2

LOC002

PAGE 1

LOC001

PAGE 0

}

LOCooO

1 MEMORY FIELD
(40SPAGES)
03

1 MEMORY PAGE
(200S LOCATIONS)
07

I I I I
\

1 MEMORY LOCATION
(12 BITS, USUALLY NUMBERED
AS SHOWN)

3 BITS = 1 OCTAL
DIGIT
MA·5982

Figure 4-1 VT278 Main Memory Organization

4.4

TWO'S COMPLEMENT NOTATION

Data is represented in two's complement integer notation. In this
system of notation, the negative of a number is formed by
complementing each bit in the data word and adding "I" to the
complemented number. The sign is indicated by the most significant
bit. In the l2-bit word used in the 6120, when bit 0 is a "0," it
denotes a posi ti ve number and when bi t 0 is a "1," it denotes a
negative number. The number range for this system is +3777 to
-4000 octal (+2047 to -2048 decimal).

4.5

INSTRUCTIONS

This section describes the VT278 instruction set, which includes:

•

Memory reference instructions (MRI)
stored in a memory location.

•

Operate instructions that allow manipulation
testing of data in the accumulator and link.

•

External I/O instructions that transfer information
between a peripheral device and main memory.

•

Internal control operation instructions which are similar
to external I/O instructions, but control internal
facilities such as stacks.

4-4

that operate on data
and/or

4.5.1
Memory Reference Instructions
Memory reference instructions (MRI) operate on the contents of a
memory location or use the contents of a memory location to
operate on the AC or the pc. Figure 4-2 shows the MRI format. Bits
0--2 of a memory reference instruction specify the operation code,
or opcode, and the 9 low-order bits specify the operand address.
Bits 5--11, the page address, identify the location of the operand
on a given page, but they do not identi fy the page i tsel f. The
page is specified by bit 4, called the page bit. If bit 4 is a
"0," the page address is interpreted as a location on page 0. If
bit 4 is a "1," the page address is interpreted to be on the
current page. The entire l2-bit address, consisting of the 7
low-order bi ts from the instruction and ei ther 0 or the current
page bi ts in the 5 high-order bi ts is known as the instruction
address, or IA. The instruction field provides the 3 high-order
bits of the complete IS-bit address (IA).
Other locations are addressed by using bit 3. When bit 3 is a "0,"
the operand is directly addressed, and IA is the location of the
operand. When bit 3 is a "I," the operand is indirectly addressed,
and the contents of IA specify the location of the operand. To
address a location that is not on page 0 or the current page, the
absolute address of the desired location is stored in one of the
256 directly-addressable locations as a pointer address. The
instruction addresses the operand indirectly through this pointer.
Upon execution, the MRI operates on the contents of the location
identified by the address contained in the pointer location. The
pointer is obtained from the current instruction field; the data
is in the current data field (OF).
It should be noted that locations 0010--0017 (octal) in page 0 of
any field are auto indexed. If these locations are addressed as
indirect pointers, the contents are incremented by 1 and restored
before they are used as the operand address. These locations may,
therefo re, be used for index ing appl ications. Our ing the memory
write operation, the OF appears on C0, C2, and EMA2. Indirect
reference to auto index reg isters from page 0 work as defined
whether the page bit is "1" or "0."

ADDRESS
MODE BIT
0= DIRECT
1 = INDI RECT.
PAGE BIT
O=PAGE 0
1 =CURRENT
PAGE

MA·5982A

Figure 4-2 Memory Reference Instruction Format

4-5

The memory reference instructions are as follows.
AND
TAD
ISZ
DCA
JMS
JMP

Logical AND to AC
Two's complement add
Increment and skip if zero
Deposit and clear the accumulator
Jump to subroutine
Jump

The
followi ng
instructions.

notat ion

desc r ibes

the

memo ry

reference

Symbol

Definition

Instruction address -- a 12-bit address
derived from the memory reference instruction
word and the PC. Bits 0--4 are 0 if bit 4 of
the instruction was 0. Bits 0--4 are equal to
bits 0--4 of the PC when the instruction was
fetched if bit 4 of the instruction was a 1.
Bits 5--11 are bits 5--11 of the instruction.

(IA)

"The contents of the memory location pointed
to by the instruction address."

Effective address -- equal to IA if
instruction bit 3=0; equal to (IA) if
instruction bit 3=1.

( ( IA) )

"The contents of the location pointed to by
(IA) ."

Opcode

Bits 0--2 of the instruction

"Is replaced by"

Bit 3 of the instruction

Denotes logical AND operation

Denotes logical OR operation

( IB)

Contents of the instruction buffer

4-6

4.5.1.1

AND

ADDRESS
MODE BIT

Purpose

Logical AND to AC

Execution time
(us)

Direct
2.76

Operation

Logical AND direct (1-.):
(AC)<-(AC)*(IA).

Indirect
3.95

Autoindex
5.13

Logical AND indirect autoindex (1=1, IA is
not 8818-8817):
(AC)<=(AC)*«IA».
Logical AND indirect autoindex (I=1, IA is
8818-8817):

(IA)<=(IA)+l
(AC)<-(AC)*«IA».
Operation code

Description

The contents of the effective address (EA)
is combined with the contents of the AC by
a bitwise AND operation. The result is left
in the AC, memory is unchanged, and the
original content of the AC is lost.

4.5.1.2

TAD

Purpose

2'8 complement add

Execution time
(us)

Direct
2.76

Operation

Binary add direct (1-.):
(AC)<-(AC)+(IA).

Indirect
3.95

4-7

Autolnde.
S.13

Binary add indirect (I=l, IA is not
0010-0(17):
(AC<= (AC) + ( (IA) ) •
Bina~y add ind~rect autoindex (I=l, IA is
0({J1({J-({J({J17):
(IA)<=(IA)+l
( AC) <= (AC) + ( (IA) ) •

Operation code

Description

The contents of the effective address (EA)
are added with the contents of the AC and
the result is stored in the AC. Memory is
unchanged and the original content of the
. AC is lost. If there is a high-order carry
from AC({J, ·the link is complemented.
If the AC is initially cleared, this
instruction acts as a load from memory.

4.5.1.3

ISZ
00

[ 0
\

: : I
1

OPCODE

I
I

PAGE BIT

ADDRESS
MODE BIT

MA·5994

Purpose

Increment and skip if zero

Execution time
(us)

Direct
3.55

4.74

4.34

5.52

Operation

Indirect

Autoindex
5.92 (no skip occurs)
6.71 (skip occurs)

Increment and skip if zero direct (I=0):
(IA)<=(IA)+l
If (IA)=({J then (PC)<=(PC)+l.
Increment and skip if zero indirect
(I=l, IA is not ({J01({J-0017):
( (IA) ) <= ( (IA) ) + 1
If «IA»=({J then (PC)<=(PC)+l.
Increment and skip if zero autoindex
(I=l, IA is ({J({J1({J-({J({J17):
(IA)<=(IA)+l
«IA» <= «IA) )+1
If «IA»=({Jthen (PC)<=(PC)+l.

4-8

Operation code

Description

The content of the effective address (EA)
is incremented by 1 and restored to memory.
If the content of the EA becomes 0, the PC
is incremented by 1 to skip the next
sequential instruction. If the content of
the EA does not become 0, the next
instruction is executed.

4.5.1.4

DCA

ADDRESS
MODE BIT

MA-5995

Purpose

Deposit and clear the accumulator.

Execution time
(us)

Direct
2.76

Operation

Deposit and clear the accumulator direct
(I =0) :
(IA)<=(AC)
(AC)<=0.

Indirect
3.95

Autoindex
5.13

Deposit and clear the accumulator indirect
(I=l, IA is not 0010-0017):
«IA»<=(AC)
(AC)<=0.
Deposit and clear the accumulator autoindex
(I=l, IA is 0010-0017):
(IA)<=(IA)+1
( (IA) ) <= (AC)
(AC)<=0.
Operation code

Description

The content of the AC is stored in the
effective address (EA) and the AC is set to
zero. fhe original content of the effective
address is lost.

4-9

4.5.1.5

JMS

ADDRESS
MODE BIT
MA-5988

Purpose

Jump to subroutine

Execution time
(us)

Direct
2.76

Operation

Jump to subroutine direct (1=0):
(IF)<=(IB)
(IA)<=(PC)
(PC)<=IA+l.

Indirect
3.95

Autoindex
5.13

Jump to subroutine indirect (1=1, 1A is not
0010-0017) :
(IF)<=(IB)
( (IA) ) <= (PC)
(PC)<=(IA)+l.
Jump to subroutine autoindex (1=1, 1A is
0010-0017) :
(1A)<=(IA)+l
(1F)<=(IB)
«1A»<=(PC)
(PC)<=(IA)+l.
Operation code

Description

The content of the PC is stored in the
EA. The PC is then loaded with 1 more than
the EA, so that the instruction that
follows the EA is the next instruction to
be executed. Therefore, the EA contains the
return address from the subroutine. The
content of the AC is not affected.

4-10

4.5.1.6

JMP

ADDRESS
MODE BIT
MA·5989

Purpose

Jump

Execution time
(us)

Direct
1.58

Operation

Jump direct (I=0):
(IF)<=(IB)
(PC)<=IA.

Indirect
2.76

Autoindex
3.95

Jump indirect (I=l, IA is not 0010-0017):
(IF)<=(IB)
(PC) <= (IA) •
Jump autoindex (I=l, IA is 0010-0017):
(IA)<=(IA)+l
(IF)<=(IB)
( PC) <= ( I A) •
Operation code

Description

The EA is loaded into the PC so that the
instruction stored at this address is the
next instruction to be executed. The
original content of the PC is lost. The
content of the AC is not affected.

4-11

4.5.2
Operate Instructions
Operate instructions have an opcode of 7 (Ill) and are divided
into 3 groups. Group 1 instructions have a 0 in bit 3. They
perform logical operations on the contents of the AC and link.
Group 2 instructions have a 1 in bit 3 and a 0 in bit 11. They
primarily test the contents of the AC and then conditionally
skip the next instruction. Group 3 instructions have a 1 in bit
3 and a 1 in bit 11. They perform logical operations on the contents of the AC and MQ. The basic operate instruction format is
shown in Figure 4-3.
In most cases, operate instructions from a group may be
microprogrammed with other operate instructions of the same group.
In these instances, the actual code for a microprogrammed
combination of two or more operate instructions is the bi t-wise
logical OR of the octal codes for the individual operate
instructions. When more than one operation is microprogrammed into
a single instruction, the operations are performed in a prescribed
sequence, with logical sequence number 1 performed first, number 2
performed second, number 3 performed third, and so on. Two
operations wi th the same log ical sequence number wi thin a given
group are performed simultaneously.
4.5.2.1 Group 1 Operate Instructions
Fig ure 4-4 shows the
instruction format of group 1 operate instructions. Anyone of
bi ts 4--11 may be set (loaded wi th a binary 1) to indicate a
specific group 1 operate instruction. If more than one of these
00

I I
1

I I

11
B

-A -B

MICROINSTRUCTION
GROUP 1
GROUP 2
GROUP 3

0
1
1

0
1
MA·5990

Figure 4-3 Basic Operate Instruction Format
00

,06

BSW IF 8,9,10=001 OR 111
R3l IF 8,9,10= 110

GROUP 1
LOGICAL SEQUENCE:
1 - ClA, Cll
2- CMA,CMl
3-IAC
4-RAR,RAl,RTR,RTl,BSW,R3l

MA-5991

Figure 4-4 Group 1 Microinstruction Format

4-12

bits is set, the instruction is a microprogrammed combination of
group 1 instructions, which will be executed according to the
log ical sequence shown in Figure 4-4. Bi ts 8, 9, and 10 are an
exception to this rule; these bits specify 1 of 8 possible types
of rotate instructions.
Table 4-1 lists commonly used group 1 instructions, their assigned
mnemonics, octal number, instruction format, logical sequence, and
the operation they perf.orm. All group 1 microinstructions require
2.37
microseconds,
but
RTR,
RTL,
and
BSW
require
3.16
microseconds.
Table
4-2
lists
microinstructions.

commonly

used

microprogrammed

group

It is often useful to generate a constant by microprogramming
group 1 microinstructions that manipulate the AC and the link. By
microprogramming a constant, you can save using a memory location.
Table 4-3 contains a number of instructions that produce some
commonly used constants.
Table 4-1

Group 1 Operate Instructions

Mnemonic

Octal

Sequence

Description

NOP

7000

No operation -- Causes a I-cycle delay
in program execution, without
affecting the state of the computer.
May be used for timing synchronization
or as a convenient means of deleting
another instruction from a program.

lAC

7001

Increment accumulator -- The content
of the accumulator is incremented by
1. A carry out of the accumulator
complements the link.

BSW

7002

Byte swap -- The content of the six
low-order bits of the AC is exchanged
with the content of the six high-order
bits. That is, bits AC<0:5> are
exchanged with bits AC<6:1l>. The
content of the link is not affected.

RAL

7004

Rotate accumulator left -- The content
of AC<l:ll> is shifted into AC<0:10>.
The content of AC0 is shifted into the
link, -and the content of the link is
shifted into ACll.

RTL

7006

Rotate two left -- Equivalent to two
consecutive RAL operations.

4-13

Table 4-1

Group 1 Operate Instructions (Cont)

Mnemonic

Octal

Sequence

Description

RAR

7010

Rotate accumulator right -- The
content of AC<0:10> is shifted into
AC<l:ll>. The content of the link is
shifted into AC0, and the content of
ACll is shifted into the link.

RTR

7012

Rotate two right -- Equivalent to two
consecutive RAR operations.

R3L

7014

Rotate three left -- Rotate the AC
(but not the link) three places to the
left. AC0 is rotated into AC9, ACI is
rotated into AC10.

CML

7020

Complement link -- The content of the
link is complemented.

CMA

7040

Complement accumulator -- The content
of each bit of the AC is complement.
This has the effect of replacing the
content of the AC with its lis
complement.

CIA

7041

2,3

Complement and increment accumulator
-- The content of the AC is replaced
with its 2's complement. This is a
microprogrammed combination of CMA and
lAC.

CLL

7100

Clear link -- The link is loaded with
a binary 0.

STL

7120

1,2

Set the link -- The link is loaded
with a binary 1. This is a
microprogrammed combination of CLL and
CML.

CLA

7200

Clear accumulator -- Each bit of the
AC is loaded with a binary 0.

GLK

7204

1,4

Get the link -- The AC is cleared and
the content of the link is shifted
into ACll while a 0 is shifted into
the link. This is a microprogrammed
combination of CLA and RAL.

STA

7240

1,2

Set the accumulator -- Each bit of the
AC is loaded with a binary 1. This is
a microprogrammed combination of CLA
and CMA. The AC will contain 7777.

4-14

Table 4-2

Microprogrammed Combinations of Group 1
Microinstructions

Mnemonic

Octal

Sequence

Description

CLL RAL

7104

1,4

Clear the link and rotate AC and
link left.

CLL RTL

7106

1,4

Clear the link and rotate AC and
link two left.

CLL RAR

7110

1,4

Clear the link and rotate AC and
link right.

CLL RTR

7112

1,4

Clear the link and rotate AC and
link two right.

CLA lAC

7201

1,3

Clear and increment the AC. The AC
will contain 0001.

CLA CLL

7300

Clear the AC and link.

Table 4-3

Constants Generated By Microprogrammed Group 1
MicrQinstructions

Octal

Constant
Decimal

0001
0002
0002
0003
0004
0006
0010
0100
2000
3777
4000
5777
6000
7775
7776
7777

1
2
2
3
4
6
8
64
1024
20,47
-2048
-1025
-1024
-3
-2
-1

Instruction
(Octal)

Microprogrammed
Combination

7301
7305
7326
7325
7307
7327
7315
7303
7332
7350
7330
7352
7333
7346
7344
7340

CLA CLL lAC
CLA CLL lAC RAL
CLA CLL CML RTL
CLA CLL CML lAC RAL
CLA CLL lAC RTL
CLA CLL CML lAC RTL
CLA CLL lAC R3L
CLA CLL lAC BSW
CLA CLL CML RTR
CLA CLL CMA RAR
CLA CLL CML RAR
CLA CLL CMA RTR
CLA CLL CML lAC RTR
CLA CLL CMA RTL
CLA CLL CMA RAL
CLA CLL CMA

4-15

4.5.2.2 Group 2 Operate Instructions
Figure 4-5 - shows the
instruction format of group 2 operate instructions. Bits 4--10 may
be set to indicate a specific group 2 instruction. If more than
one of bits 4--7, 9, or 10 is set, the instruction is a
microprogrammed combination of instructions. It will be executed
according to the logical sequence shown in Figure 4-5.
Skip instructions may be microprogrammed wi th CLA, OSR, or HLT
instructions. Skip instructions wi th a 0 in bi t 8, however, may
not be microprogrammed with skip instructions with a 1 in bit 8.
When two or more skip instructions are microprogrammed into a
single instruction, the resulting condition on which the decision
will be based is the logical OR of the individual conditions when
bit 8 is 0; or, when bit 8 is 1, the decision will be based on the
logical AND.
Table 4-4 describes each of the group 2 microinstructions. Table
4-5 lists the legal combinations of skip and CLA instructions.
Logical combinations of skip and OSR and HLT instructions are also
allowed.
All group 2 microinstructions
requires 3.16 microseconds.
00

require 2.76 microseconds,

but OSR

REVERSE SKIP SENSING OF BITS 5, 6,7
IF SET
LOGICAL SEQUENCE:
1-(BIT 8'=0)- SMA OR SZA OR SNL
(BIT 8'=1) - SPA AND SNA AND SZL
2-CLA
3-0SR, HLT
MA-5984

Figure 4-5 Group 2 Microinstruction Format
Table 4-4

Group 2 Operate Instructions

Mnemonic

Octal

Sequence

Description

HLT

7402

Halt -- Stops execution of the
program in main memory.

OSR

7404

Logical OR with status bits -- The
status bits (Paragraph 4.5.2.3) are
inclusively ORed with the AC. The
result is stored in the AC. The
content of the status bits is not
affected.

SKP

7410

Skip -- The content of the PC is
incremented by 1, to skip the next
sequential instruction.
4-16

Table 4-4

Group 2 Operate Instructions (Cont)

Mnemonic

Octal

Sequence

Description

SNL

7420

Skip on non-zero link -- The
content of the link is sampled. If
the link contains a 1, the content
of the PC is incremented to skip
the next sequential instruction. If
the link contains a 0, the next
instruction is executed.

SZA

7440

Skip on zero accumulator -- The
content of each bit of the AC is
sampled. If every bit contains a 0,
the content of the PC is
incremented to skip the next
sequential instruction. If any bit
contains a 1, the next instruction
is executed.

SNA

7450

Skip on non-zero accumulator -- The
content of each bit of the AC is
sampled. If any bit contains a 1,
the content of the PC is
incremented by 1 to skip the next
sequential instruction. If every
bit contains a 0, the next
instruction is executed.

SMA

7500

Skip on minus accumulator -- The
content of AC0 is sampled. If AC0
contains a 1, indicating that the
AC contains a negative, 2's
complement number, the'content of
the PC is incremented to skip the
next sequential instruction. If AC0
contains a 0, the next instruction
is executed.

SPA

7510

Skip on positive accumulator -- The
content of AC0 is sampled. If AC0
contains a 0, indicating that the
AC contains a positive 2's
complement number (or 0), the
content of the PC is incremented to
skip the next sequential
instruction. If AC0 contains a 1,
the next instruction is executed.

CLA

7600

Clear accumulator -- Each bit of
the AC is loaded with a binary 0.

4-17

Table 4-5

Microprogrammed Combinations of Group 2
Microinstructions

Mnemonic

Octal

Sequence

Description

SZA SNL

7460

Skip if AC=0 or L=1 or both.

SNA SZL

7470

Skip if

SMA SNL

7520

Skip if AC<0 or L=1 or both.

SPA SZL

7530

Skip if AC=>0 and L=0.

SMA SZA

7540

Skip if AC=<0.

SPA SNA

7550

Skip if AC>0.

SMA SZA SNL

7560

Skip if AC=<0 or L=1 or both.

SPA SNA SZL

7570

Skip if AC>0 and L=0.

SZA CLA

7640

1,2

Skip if AC=0, then clear AC.

SNA CLA

7650

1,2

Skip if

SMA CLA

7700

1,2

Skip if AC<0, then clear AC.

SPA CLA

7710

1,2

Skip if AC>=0, then clear AC.

AC~0

AC~0,

and L=0.

then clear AC.

4.5.2.3 OSR Instruction
The OSR instruction causes VT278
status bits to be ORed to AC<0:3> and AC<10:1l>. The instruction
format is shown in Figure 4-6.
If AC<0>=0, bits AC<I:3> define which foreign language keyboard is
attached. The keyboard language is set at system assembly time by
means of a four position DIP switch mounted on the VT278 processor
module. The exact interpretation of AC<I:3> is a function of the
keyboard translation ROM installed in the processor module. The
three bits allow selection of one of seven foreign language
keyboard formats. When AC<I:3>=000, standard US/UK is used but the
display language can be changed to a foreign language by executing
the select character set (SCS) ESCape sequence (Paragraph 5.2).
4.5.2.4 Group 3 Operate Instructions
Group 3 operate
instructions transfer data between the AC and multiplier quotient
(MQ) registers. These microinstructions are intended primarily for
use with external equipment, but they are also useful when the MQ
is employed as a temporary storage register.
Figure 4-7 shows the format of a group 3 microinstruction. The
operation code must be 7, to indicate an operate instruction,
while bits 3 and 11 must both contain a 1, to indicate a group 3
microinstruction. Anyone of bits 4, 5, or 7 may be set to
4-18

PRIMARY
POWER
SOURCE
FREQUENCY
HZ
HZ

KEYBOART
LANGUAGE
l=ENGLISH
O=FOREIGN
FOREIGN
LANGUAGE
KEYBOARD
TYPE

1=60
0=50

COMMUNICATIONS
OPTION
O=OPTION PRESENT
l=NO OPTION PRESENT
MA·5985

Figure 4-6 OSR Instruction Format

1 1 1 1 11 1 1 1CLA 1MQA 1 * 1MQL I * 1 * 1 * 1 1
LOGICAL SEQUENCE: 1 - CLA
2- MQA. MQL
3 - ALL OTHERS
* - CAUSES INSTRUCTION TO BE UNINTERRUPTIBLE IF 1
MA·5986

Figure 4-7 Group 3 Microinstruction Format
indicate a specific group 3 microinstruction. If more than one of
these bits is set,
the instruction is a microprogrammed
combination
of
group
3
microinstructions.
All
group
3
microinstructions require 2.37 microseconds.
Table 4-6 1 ists the group 3 microinstructions,
mnemonics, and the operations they perform.

thei r

assigned

4.5.3
Input/Output Operations
Input/output transfer (lOT) instructions have an opcode of 6. They
are used to start the operation of peripheral devices and to
transfer data between peripherals and the 6120. Three types of
data transfer may be used to receive or transmit information
between the 6120 and one or more peripheral I/O devices.
straightforward means
transfer
is
a
Programmed
data
communicating with relatively slow I/O devices, such as
console terminal.

of
the

Program interrupt transfers use the interrupt system to service
several peripheral devices simultaneously. On an intermittent
bas.is, they permit computational operations to be performed
concurrently wi th the data I/O operations. Both programmed data
transfers and program interrupt transfers use the AC as a buffer,
or storage area, for all data transfers. Since data may be
transferred only between the AC and the peripheral, only one
l2-bit word at a time may be transferred.

4-19

Table 4-6

Group 3 Operate Instructions

Mnemonic

Octal

Sequence

Description

NOP

7401

No operation -- This instruction
causes a delay in program execution,
without affectitig the state of the
computer.

CLA

7601

Clear accumulator -- Each bit of the
AC is loaded with a binary 0.

MQL

7421

Multiplier quotient load -- The
content of the AC is loaded into the
MQ. The AC is cleared, and the
original content of the MQ is lost.

MQA

7501

Mul tiplier quotient into ,accumulator
-- The content of the MQ is combined
with the content of the AC by a
bitwise logical OR operation, and
the result is lo~ded into the AC.
The original content of the AC is
lost, but the original content of
the MQis not affected. Note that
this instruction provides the
programmer with a direct inclusive
OR operation.

SWP

7521

Swap accumulator and multiplier
quotient -- The content of the AC
and the content of the MQ are
exchanged.

CAM

7621

Clear accumulator and multiplier
quotient -- Each bit of both the AC
and the MQ is loaded with a binary
0.

ACL

7701

Load AC with MQ -- The content of
the MQ is load into the AC. The
original content of the AC is lost.
The original content of the MQ is
not affected.

CLA SWP

7721

Clear accumulator, then swap -- The
AC is cleared, then the MQ is loaded
into the AC and 0000 is loaded into
the MQ.

4-20

Direct memory access (DMA) transfers variable-size blocks of data
between, high-speed peripherals and memory with a minimum of
program control by the 6120.
The lOT instruction format is shown in Figure 4-8. The first 3
bits, AC<0:2), are always set to 6 to specify an lOT instruction.
The next 6 bits, AC<3:8), contain the device selection code that
determines the specific I/O device for which the lOT instruction
is intended. Device selection codes 00 8 and 20 a through 278
specify internal operations, and may not be usea by external
devices. Internal operations are described in Paragraph 4.5.4. As
many as 55 I/O devices can be specified. The last 3 bits,
AC<9:11), contain the code that determines the specific operation
to be performed. The nature of this operation for any given lOT
instruction depends entirely upon the circuitry designed into the
I/O device interface.
4.5.3.1 Programmed Data Transfer -- Programmed data transfer is
the easiest and most common means of performing data I/O. Every
input/output transfer (lOT) instruction initiates one programmed
transfer which may transmit data or status information either to
or from a peripheral device. The amount of information that will
be transferred by a single lOT instruction depends upon the
particular operation that is coded into the instruction and the
complexi ty of the I/O device interface. In general, programmed
data transfers are limi ted to a maximum of 12 bi ts of data or 1
bit of status information per lOT instruction.
The computer operates much faster than most peripheral devices.
For this reason, I/O routines must check the status of a device
before executing an lOT instruction to be sure that the device is
not still performing a previous operation. Device status is
signalled through a system of I-bit registers called flags. Every
I/O device has a device flag which is set to 1 as soon as the
device finishes a current operation and is ready to begin a new
operation. If the flag is cleared (set to 0), the device is still
performing the operation specified by the last lOT instruction
received. Ready status is usually checked by means of a
skip-on-flag lOT instruction, such that the computer does not skip
out of a waiting loop until the I/O device is ready to begin a new
operation.

MA·5987

Figure 4-8 lOT Instruction Format

4-21

In general, for
instructions:

each

I/O

device

there

are

least

three

An instruction to transfer information and/or operate the
device.

An instruction to test the ready status of the device and
skip on the ready (or not ready) status of the device.

An instruction to clear or set the device flag.

4.5.3.2 Program Interrupt Transfer -- The program interrupt
system may be used to initiate programmed data transfers in such a
way that the time spent waiting for device status is greatly
reduced. It also provides a means of performing programmed data
transfers between the 6120 and peripheral devices while executing
another program. This is done by isolating the I/O handling
routines from the mainline program and using the interrupt system
to be sure that these routines are entered only when an I/O device
flag is set. This indicates that the device is actually ready to
perform the next data transfer.
The interrupt system allows external conditions to interrupt the
computer program (which must be in main memory). If no internal
higher priority requests are outstanding and the interrupt system
is enabled, the 6120 grants the device interrupt at the end of the
current instruction. After an interrupt has been granted, the
interrupt enable flip-flop in the 6120 is reset so that no more
interrupts are acknowledged until the interrupt system is
reenabled under program control.
A program interrupt is simply a conventional JMS instruction to
memory location 0000 in field 0 (octal code 4000) which is buil t
and executed by c i rcui ts in the processo r. Three cond i tions must
be satisfied before a program interrupt may occur:
1.

The interrupt system must be enabled,

The interrupt inhibit flip-flop must be cleared,

The interrupt request line must be asserted.

During the next machine cycle, the processor turns off the
interrupt system so that no further interrupts may occur until the
current interrupt has been serviced. It then executes the
hardware-generated JMS to memory location 0000. Th i s causes the
address of the instruction that was due to be executed when the
program interrupt occurred to be stored in location 0000 of memory
field 0. The PC is then loaded with 0001, so that the instruction
stored in location 0001 of field 0 is the next instruction to be
executed.

4-22

This instruction is usually a jump to the starting address of an
interrupt service routine, which generally performs all of the
following operations:
1.

Save the content of any registers (AC, MQ, link)
will be used by the interrupt service routine.

Determine which
interrupt.

Determine why the device caused an interrupt.

Correct the condition that resulted in the interrupt.

Restore the content of registers
interrupt service routine.

Turn the interrupt system on.

Resume mainline execution, usually by executing a JMP r 0
instruction (octal code 5400).

peripheral

device

caused

the

that were used

that

program

by the

A running program maintains control over the interrupt system by
executing the processor rOT instructions described in Table 4-7.
Table 4-7

Main Memory Control Instructions

Mnemonic

Octal

Execution
Time
(us)

SKON

6000

2.76

Skip if interrupt system on
The state of the interrupt
enable flip-flop is tested. If
this flip-flop is set,
indicating that the interrupt
system is enabled, the PC is
incremented to skip the next
sequential instruction and the
interrupt system is turned off
in the same manner as by an IOF
instruction.

ION

6001

2.37

Interrupt turn on -- The next
program instruction is
executed, then the interrupt
system is enabled. Delaying the
interrupt enable in this manner
gives the interrupt service
routine time to resume
background program execution
(by means of a JMP I 0
instruction) before another
program interrupt occurs.

Description

4-23

Table 4-7

Main Memory Control Instructions (Cont)

Mnemonic

Octal

Execution
Time
(us)

IOF

6002

2.37

Interrupt turn off -- The
interrupt system is disabled
inhibiting further program
,interrupts, including any
interrupt request that might
have occurred during execution
of the IOF instruction.

SRQ

6003

2.76

Skip on interrupt request -The state of the interrupt
request line is tested. If this
line is asserted, indicating
that one or more devices are
requesting a program interrupt,
the PC is incremented to skip
the next sequential
instruction.

GTF

6004

3.55

Get flags -- The following
machine states are read into
the indicated bits of the
accumulator:

Description

AC0
ACl
AC2
AC3
AC4
AC5
AC<6:8>
AC<9:11>
RTF

Link
GT flag
Interrupt request
line (1 if low; 0 if
high)
Power On flag
1

ISF<0:2>
DSF<0:2>

6005

3.16

Return flags -- This
instruction is the converse of
GTF. Link is loaded from AC0,
GT flag is loaded from AC1,
AC<6:8> are loaded into IB,
AC<9:11> are loaded into DF,
interrupt inhibit flip-flop is
set, and bit 4 is loaded into
the interrupt enable flip-flop.
The AC is then cleared.

6006

2.76

Skip if greater than -- If the
GT flag is set, the PC is
incremented to skip the next
sequential instruction.
4-24

Table 4-7

Main Memory Control Instructions (Cont)

Mnemonic

Octal

Execution
Time
(us)

CAF

6"-1"-17

2.76

Clear all flags -- Clear the
AC, link, and GT flag. Clear
the interrupt enable flip-flop
and all peripheral flags.

PR"-I

62"-16

32"-1
(8 "-I-col umn)
324
(132-col umn)

Panel request -- Used to access
locations in the display buffer
memory. The location to be
accessed is specified in row
and column format in the two
locations following the
instruction itself:

Description

CALL, PR"-I
ROW
COL

/The physical
/ROW number
/The physical
/COLUMN number

Execution of the instruction
causes immediate entry to panel
memory where the row and column
specified are used to access
the display buffer memory.
Return is made to CALL+3 with
the contents of that memory
location in the AC.
PRI

6216

Variable

Panel request -- Used to
transfer blocks of data
directly to the display buffer
memory. Achieves a much faster
screen update than normal
terminal I/O instructions. This
method should be used with
caution. Like large updates the
CPU remains in control panel
memory for long periods of
time. During this time, main
memory interrupts are not
serviced. Data to be put in the
display buffer memory follows
the instruction itself in the
following format:
UPDATE, PRI
ROW
COL
DATA
4-25

/This three word
/group repeated
/for as many

Table 4-7

Mnemonic

Main Memory Control Instructions (Cont)

Octal

Execution
Time
(us)

Description

7777

/screen locations
las required.
/Terminates
/update
/sequence.

Executing this instruction
causes immediate entry to panel
memory where the locations in
the display buffer memory
specified by row, column are
loaded with DATA. This
continues until the 7777
terminator is reached when
return is made to main memory
to the location following the
7777.
The screen may be filled by
this method at speeds
equivalent to a conventional
terminal running at over 100K
baud. The only limitation to
the amount of data that may be
passed at one time is that the
instruction cannot cross field
boundaries. Thus, the maximum
number of screen locations that
can be changed at one time is
approximately 1300. An update
of this length would take about
30 ms.
As the display buffer memory is
accessed directly by the PR1
instruction, certain sequences
of normal terminal output
executed just before the PR1
may not execute correctly. A
PRI should not be issued until
at least 40 ms after any clear
screen or line ESCape sequence
has been transmitted by a
normal TLS I/O sequence. To
simplify executing such
sequences the following method
of finding out when the Clear
function has completed may be
used:
4-26

Table 4-7

Mnemonic

Main Memory Control Instructions (Cont)

Octal

Execution
Time
(us)

Description
Send erase ESCape sequence.
Send device status report (DSR)
ESCape sequence and wait for
cursor position report (CPR)
ESCape sequence response.
When CPR is received, the Erase
function has been completed and
it is then possible to execute
the PRI screen update.

PR2

6226

Indeterminate

Panel request -- Simulates
entry into SET-UP mode and
pressing one of keys 0--9. Its
use is:
CALL, PR2
II Nil

17 or 8 bit
Irepresentation
lof 0--9

The effect is as though SET-UP
had been entered by pressing
CTRL and SET-UP and then one of
the keys 0--9. As in SET-UP
mode, only valid numbers have
any effect. An invalid N causes
a return to CALL+2.
PR3

6236

Not applicable

Panel request -- Used to access
certain control panel memory
routines from main memory. The
effect of issuing this
instruction is to transfer
program execution immediately
to that address in control
panel memory which is defined
in the memory location
following the PR3 instruction::
PR3
nnnn

4-27

Iprogram exeuction
Icontinues at address
Innnn in control panel
Imemory

Table 4-7

Mnemonic

Main Memory Control Instructions (Cont)

Octal

Execution
Time
(us)

Description
This instruction should only be
used with extreme caution. A
jump to an arbitrary address in
control panel memory could have
unpredictable results.
Certain routines in control
panel memory are written as
subroutines and may be accessed
via the PR3 instruction. The
routines are: Set TLS buffer
size (Paragraph 4.5.4.3) and
load/read keyboard LED pattern
(Paragraph 4.5.4.4).

WSR

6246

2.76

I/O write -- Clears the AC.

GCF

6256

3.55

Get current fields -- The
following bits are loaded into
the AC:
AC0
ACl
AC2
AC3
AC4
AC5
AC<6:8>

Link
GT flag
Interrupt request line
(1 if low; 0 if high)
Power on flag
Interrupt enable
flip-flop

Instruction field
(IF<0:2»
AC<9:ll> Data field (DF<0:2»

4.5.3.3 Di rect .Memory Access Transfer -- Di rect memory access,
sometimes called data break, is the preferred form of data
transfer to use wi th high-speed storage devices such as magnetic
disk. The DMA mechanism transfers data directly between memory and
peripheral devices. The 6120 is involved only in setting up the
transfer; the transfers take place with no 6120 intervention on a
"cycle stealing" basis. The DMA transfer rate is limited only by
the bandwidth of the memory and the data transfer characteristics
of the device.

The RL278 is the only DIGITAL device available for the VT278 that
includes a DMA interface. The RL278 is supplied wi th software
subroutines that perform all the necessary functions required for
DMA operation.
4-28

4.5.4
Internal Operations
Internal operations are those lOT instructions which have a device
selection code of 00 or 20 through 27 • For the VT278, internal
8
8
8
operations include:
Main memory control instructions,
Memory extension instructions, and
Stack operation instructions.
4.5.4.1 Main Memory Control Instructions -- Main memory control
instructions are described in Table 4-7. They are primarily used
to control the interrupt system and panel memory.
4.5.4.2 Memory Extension Control Instructions
The internal
memory extension control extends the addressing capabilities of
the VT278 from 4096 words up to 32,768 words. It does so by
appending three high-order bi ts to the memory address to define
the memory field. The instructions described in Table 4-8 access
extended memory fields by using the following registers to define
the bits of addressing.
1.

Instruction field (IF) - The IF is a 3-bi t reg ister that
serves as an extension of the pc. The contents of the IF
determine the field from which all instructions are taken
and the field from which operands are taken in directly
addressed AND, TAD, ISZ, or DCA instructions.

Data field (DF)
This 3-bi t reg ister determines the
memory field from which operands are taken in indirectly
addressed AND, TAD, ISZ, or DCA instructions and external
lOTs, OSR, and WSR functions.

Instruction buffer (IB) - The IB serves as a 3-bit input
buffer for the instruction field register. All field
number transfers into the instruction field register are
made through the lB.

Instruction save field (ISF) - When an interrupt occurs,
the contents of the IF are loaded into the ISF. The IB
can be restored by an RMF instruction before the exi t
from the interrupt subroutine.

Data save fi eld (DSF) - When an interrupt occurs, the
contents of the DF are loaded into the DSF. The DF can be
restored by an RMF instruction before the exi t from the
interrupt subroutine.

4-29

Table 4-S

Memory Extension Control Instructions

Mnemonic

Octal

Execution
Time
(us)

CDF

62Nl

2.37

Change to data field N -- Loads
the data field (DF) with the
program-selected field number
(N=0--7). All subsequent memory
requests for operands of
indirectly-addressed AND, TAD,
ISZ, or DCA instructions and
external lOTs, OSR, and WSR
functions are automatically
switched to that field.

CIF

62N2

2.37

Change to instruction field N -Loads the instruction buffer (I8)
with the program-selected field
number (N=0--7) and inhibits
processor interrupts until the
next JMP or JMS instruction. At
the end of either of these
instructions, the contents of the
instruction buffer register are
transferred into the instruction
field register (IF).

CDF CIF

62N3

2.37

Change to data field Nand
instruction field N -- Performs
the combination of CDF and CIF
operations.

RDF

6214

2.37

Read instruction field -- ORs the
contents of the data field (DF)
into AC<6:S>. All other bits of
the AC are unaffected.

RIF

6224

2.37

Read instruction field -- ORs the
contents of the instruction field
(IF) into AC<6:S>. All other bits
of the AC are unaffected.

RIB

6234

2.76

Read interrupt buffer -- ORs the
contents of the instruction save
field (ISF) and data save field
(DSF) -- which are loaded from
the IF and DF during a program
interrupt -- into AC<6:S> and
AC<9:ll> respectively. Thus,
AC<6:l1> contains the IF and DF
that were in use before the last
program interrupt.

Description

4-30

Table 4-8

Memory Extension Control Instructions (Cont)

Mnemonic

Octal

Execution
Time
(us)

RMF

6244

2.37

Description
Restore memory fields -- Restores
the contents of the ISF and DSF
(loaded from the IF and DF during
a program interrupt) into the IB
and DF, respectively. This
command is used upon exit from
the program interrupt subroutine
in another field. The RMF
instruction sets the inhibit
interrupt flip-flop. At the time
of the next JMP or JMS
instruction, the IB is loaded
into the IF and the interrupt
inhibit flip-flop is cleared.

4.5.4.3 Set TLS Buffer Size (PR3 Instruction) -- At power-on, the
size of the temporary buffer used to store characters transmitted
from the user program that will be placed in the display buffer at
the next End of Frame Panel Interrupt is set to 15 characters. The
number may be changed to 29 characters, which allows faster screen
updates.
PR3
5774

PR3
5775

Iset buffer size short (15)
Iprogram execution continues here
lafter the buffer size is changed
Iby the CP memory subroutine.
Iset buffer size long (29)
Iprogram execution continues here
lafter the buffer size is changed
Iby the CP memory subroutine.

4.5.4.4 Load/Read Keyboard LED Pattern (PR3 Instruction)
In
certain cases it is useful to be able to load (set) the pattern in
the rightmost five keyboard LEOs directly.
PR3
2376

/set the LED pattern
/program execution continues here
lafter the LED pattern is changed.

The LED pattern must already be in AC<7:ll> before executing the
PR3 instruction. The AC is unchanged by this instruction. It is
also possible to read the pattern in the rightmost five keyboard
LEOs.

4-31

PR3
2374

Iread the LED pattern
Iprogram execution continues here
lafter the LED pattern is read.

When program execution returns to main memory,
pattern is contained in AC<7:ll).

the

current

LED

4.5.4.5 Stack Instructions -- Certain rOT instructions are
internally decoded to perform stack operations using internal
stack pointers SPl and SP2. The stacks are located in field 0 of
main memory. Two separate stacks may be maintained -- one for the
PC, the second for the AC. An increment of the stack pointer is
defined as a pop off the stack. The stack operations defined are
Push PC+l (PPCl or PPC2) , Push AC (PACl or PAC2) , Pop to PC (RTNl
or RTN2) , Load AC from stack (POPl or POP2) Read Stack Pointer
(RSPl or RSP2) and Load Stack Pointer (LSPl or LSP2). These
instructions are detailed in Table 4-9. (SP) is the contents of
SPI for PPCI, PACI, RTN1, RSPl, or LSPl; otherwise, it is the
contents of SP2.
Th e s t a c k po in t e r moves down as item s are ad de d ( pus h ed ) t o t h e
stack and moves up as i terns are removed (popped). Therefore, it
always points to the top of the stack.
Table 4-9

Stack Instructions

Mnemonic

Octal

Execution
Time
(us)

Description

PPCl
PPC2

6205
6245

3.95
3.95

Push (PC+l) to stack 1
Push (PC+l) to stack 2
The contents of the PC+l are
loaded into the address pointed
to by the stack pointer. The
content of the stack pointer is
decremented to point to the new
top of the stack.
Ope rat ion:

PACl
PAC2

6215
6255

3.95
3.95

S P) ) <= (PC) + 1
(SP)<=(SP)-l.

Push AC to stack 1
Push AC to stack 2
The contents of the AC are loaded
into the address pointed to by
the stack pointer. The content of
the stack pointer is decremented
to point to the new top of the
stack. The AC is unchanged by
this instruction.
4-32

Table 4-9

Stack Instructions (Cont)

Mnemonic

Execution
Time
(us)

Octal

Description
Operation:

RTN1
RTN2

6225
6265

3.55
3.55

«SP» <= (AC)
(SP)<=(SP)-1.

Pop top of stack 1 to PC
Pop top of stack 2 to PC
The stack pointer is incremented
to point to the last address
pushed. The content of this
location is loaded into the PC.
Operation:

POP1
POP2

6235
6275

3.55
3.55

(SP) <= (SP) +1
(IF)<=(IB)
(IIFF)<=0
; Interrupt inhibit
; f 1 i p- flo pis
; cleared.
( PC) <= ( (S P) ) •

Pop top of stack 1 to AC
Pop top of stack 2 to AC
The stack pointer is incremented
to point to the last pushed
address. The content of this
location is loaded into the AC.
Operation:

RSP1
RSP2

6207
6227

2.37
2.37

(SP) <= (SP) +1
(AC) <= ( (SP) ) •

Read stack pointer 1 to AC
Read stack pointer 2 to AC
The contents of the stack pointer
is loaded into the AC.
Operation:

LSP1
LSP2

6217
6237

2.37
2.37

(AC)<=(SP).

Load stack pointer 1 from AC
Load stack pointer 2 from AC
The contents of the AC is loaded
into the stack pointer and the AC
is cleared.
Operation:

4-33

(SP)<=(AC)
(AC)<=0000.

4.6
PROGRAMMING CONSIDERATIONS
The following paragraphs describe the normal and. vector modes for
servicing interrupts.
4.6.1
Programming Modes
The VT278 I/O controller operates on device codes 03, 04, 32, 33,
and 13, and is capable of operating in a type of vectored
interrupt mode. Under certain circumstances it may be advantageous
to modify existing programs to increase system performance. The
interrupt system can, therefore, operate in either a normal mode
or a vectored interrupt mode. The lOT instruction CMOD (6130) is
used to change modes.
CMOD with AC0=1
set interrupt mode normal
CMOD with AC0=0 -- set interrupt mode vectored
The interrupt system is in normal mode when power is turned on.
4.6.1.1 Normal Mode
In this mode,
interrupts force a
subroutine call to location 0000. Any skip instruction that tests
a flag and finds it set clears the flag.
4.6.1.2 Vector Mode -- Vector mode can only be entered by issuing
the lOT CMOD with AC0=0. When operating with the interrupt system
enabled, vector mode may allow faster interrupt identification.
The normal interrupt skip chain is replaced by any sequence where
the first lOT issued following the interrupt is of the form 6ABC
(where C is anything other than 1 and AB is any unused device
code). The result of issuing this lOT is that the I/O device
causing the interrupt, or the highest priority device in the case
of more than one device interrupting, returns its device code to
AC<6:ll) and the flag of that device is cleared. Thus the
interrupt identification code could look something like:
IDENT,

6777
TAD (PTR
DCA TEM
TAD ITEM
PAC 1
RTNI

/Unused lOT to get vector
/Start of jump table
/Service routine start address
/Push AC to stack
/Go to service routine

4.6.1.3 Vector Mode Priority Sequence -- The interrupt priority
is set during self-test and is:
Priority
Highest

Lowest

I/O Device
Comm. line #1 receive
Comm. line #2 receive
Comm. line #1 send
Comm. line #2 send
Comm. option control/status
Keyboard
Screen
Printer port input
Printer port output

4-34

Device Code
30
34
31
35
36
03
04
32
33

The
priority
setup code
first
determines
whether
the
communications option is present or not. In the absence of the
option, the keyboard (93) has highest priority.
4.6.1.4 Vector Mode Caveats -- Since the interrupting device code
is returned by executing a nonfunctional VT278 lOT, existing
programs should be examined before using vector mode to be sure
that no lOTs can be issued that will cause the I/O controller to
respond when no response is expected. An example is an existing
program that runs on a system wi th Power Fai 1; the Skip on Power
Low lOT is 6192. If this lOT were issued on a VT278 running in
vector mode as the first lOT following an interrupt, the highest
device would load its device code into the AC and its flag would
be cleared.

4-35

CHAPTER 5
PROGRAMMING STANDARD I/O DEVICES

5.1
INTRODUCTION
This chapter contains programming information for
standard devices integrated into the VT278.
Device
Keyboard
Display
Printer port
Real-time clock
RX278 diskette subsystem interface

the

following

Device Code
03

04
32 and 33
13
75

In addition to the information for programmi~g these devices,
Paragraph 5.6 contains a number of programmlng considerations
regarding performance and interrupt servicing.
5.2
KEYBOARD AND DISPLAY INSTRUCTIONS
The keyboard and display on the VT278 can be controlled' wi th
conventional terminal I/O instructions (Paragraph 5.2.1), panel
request (PR) instructions (Paragraph 4.5.4), and ESCape sequences
(Paragraph 5.2.3). However, the keyboard/display is not a separate
device as on most small computers.
For the VT278,
the
keyboard/display device is emulated in control panel memory.
5.2.1
Terminal I/O Instructions
Tables 5-1 and 5-2 describe the terminal I/O instructions.
5.2.2
Terminal Emulation
Terminal emulation for the VT278 is accomplished by firmware
in CP memory. The following paragraphs describe emulation for both
display and keyboard operation.
5.2.2.1 Display Operation -- When a TLS instruction is executed
in main memory, a CP interrupt is generated. Since the CP
interrupt is serviced before the next main memory instruction can
be executed, the character code present in the AC prior to the TLS
instruction is still available in the AC and can be examined by a
service routine in CP memory.
Fi rst, the character code is examined to see whether it is a
normal character or if it has any special characteristics. If it
is a normal, displayable character, it is stored in a temporary
input buffer in a read/wr i te portion of CP memory.
Codes wi th
5-1

Table 5-1

Keyboard I/O Instructions

Mnemonic

Execution
Time
(us)

Description

3.55

Sets keyboard flag (TTl).

Octal

KCF
KSF

6"'31

3.55.

Skip on keyboard flag -- If
keyboard flag was set since this
lOT was last issued, the next
instruction is skipped. Keyboard
flag is set when a key is pressed.
If skip occurs, keyboard flag is
cleared.

KCC

6"'32

3.55

Clear AC.

KRS

6"'34

3.95

OR keyboard buffer to AC -Contents of keyboard buffer are
inclusively ORed with AC<5:l1> and
results are left in AC<5:11>.
Contents of AC<"':4> are unchanged.

KIE

6"'35

3.55

Keyboard interrupt enable -Enables/disables main memory
interrupt by keyboard flag
according to content of the ACll:
ACll='" -- clear interrupt enable;
ACll=l -- set interrupt enable.

KRB

6"'36

3.95

Load keyboard buffer to AC -Performs combined operations of
KCC and KRS. AC is cleared and
contents of keyboard buffer are
ORed into AC<5:11>.

5-2

Table 5-2

Display I/O Instructions

Mnemonic

Execution
Time
(us)

Description

3.55

Sets display flag (TTO).

3.55

Skip on display flag -- If display
flag was set since this lOT was
last issued, the next instruction
is skipped. If skip occurs,
display flag is cleared.

TCF

3.55

Clear AC.

TIE

3.55

Display interrupt enable -Enables/disables main memory
interrupts by display flag
according to content of ACll:
ACll=~ -- clear interrupt enable;
ACll=l -- set interrupt enable.

TLS

3.55

Load AC<4:ll> to screen -Transfers character in AC to
display memory buffer and sets
display flag. AC is unchanged.

Octal

SPF
TSF

6~4l

special characteristics (e.g., an ESCape character) may require
that several codes following the initial character be examined to
form a display function. These functions are also stored in the
temporary buffer and use the additional 4 bits of the l2-bit word
to mark them as functions and not as a-bit ASCII characters.
After the incoming character is processed, an lOT is issued in CP
memory that sets the TTO flag and operation is returned to the
main memory program. When the main memory program executes a TSF
instruction, it finds the TTO flag set, clears the flag, and skips
the next instruction to allow the program to proceed. If the main
memory program was running under interrupts, the return from CP
memory to main memory causes a main memory interrupt, and the
normal skip chain sequence finds the TTO flag set.
Characters and display functions stored in the CP temporary input
buffer are periodically transferred into the display buffer memory
and the information in the display buffer memory is used for
updating the display. This procedure occurs 5~ or 6~ times a
second for approximately 1 to 1.5 ms and is ini tiated by a CP
interrupt which has a higher priority than main memory interrupts.
The screen update is followed by a keyboard scan (Paragraph
5.2.2.2) and then control is returned to the main memory program.

5-3

5.2.2.2 Keyboard Operation -- The keyboard is scanned at the end
of the display buffer update. If the scanner finds a key down, the
scan causes an interrupt into control panel memory where, after
decoding, valid characters are passed to the user program by
loading them, one at a time, into the TTl buffer. At the same time
the TTl flag, which can be tested by the KSF instruction, is set.
Control then returns to the main memory program.
When the main memory program executes a KSF instruction, it finds
the TTl flag set, clears the flag, and skips the next instruction
to allow the program to proceed. If the main memory program was
running under interrupts, the return from CP memory to main memory
causes a main memory interrupt and the normal skip chain sequence
finds the TTl flag set. In either case, a KRB or KRS instruction
reads the character from the TTl buffer to the AC. A KCC 0 r KRS
instruction causes another CP interrupt to indicate to the
keyboard handling routine in CP memory that the TTl buffer is now
free to accept another character when or if one becomes available.
5.2.3
ESCape Sequences For Keyboard/Display
The information in this paragraph describes the ESCape sequences
for a VT278 equipped with a US/UK keyboard that does not contain
foreign language support. Additional information for foreign
language keyboards is included in Appendices A and B.
The VT278 has many control commands (ESCape sequences) that cause
the keyboard/display to take action other than to display a
character on the screen. In this way, a user program can transmit
ESCape sequences that can move the cursor, change modes, etc. The
ASCII codes for characters in all languages are shown in Appendix
A.
The following example shows the ASCII octal representation of
characters in an ESCape sequence that turns off all character
attributes, and then turns on underscore and blink attributes.
This sequence is called select graphic rendition (SGR).
Example
ESC

[

;

(SGR sequence)

033

133

060

073

064

073

065

155

(ASCII octal equivalent)

In the following ESCape sequence descriptions, the symbols Pv.' Ph'
P, PI' P n , and F
are parameters that represent numeric or
afphabetic values. fn addition, in those sequences that permit a
string of parameters, a semicolon (;) is required to separate the
parameters.

5-4

5.2.3.1

Cursor Position Report (CPR)

ESC [ Pv ; Ph R
P v = cursor vertical position (row)
Ph = cursor horizontal position (column)
CPR is transmi tted to the user program in response to a DSR
(device status report) sequence. CPR reports the active posi tion
of the cursor wi th val ues for parameters P
and Ph. A response
wi th no parameters or parameters of ";" Ys equivalent to the
cursor at home position.
5.2.3.2

Cursor Backward (CUB)

ESC [ P n D
CUB moves the cursor to the left. The distance moved is determined
by P • If P is " or 1, the cursor moves one position to the left.
n
n
If P is n, the cursor moves n positions to the left. An attempt
n
to move the cursor to the left of the left marg in leaves the
cursor at the left margin.
5.2.3.3

Cursor Down (CUD)

ESC [ P n B
CUD moves the cursor down without altering column position. The
number of rows moved is determined by P • If P
i s " or 1, the
cur so r moves d 0 wn 0 n e 1 1 n e • I f P n 1 s n, nt h e curnso r mo v e s n rows
down. An attempt to move the cursor below the bottom margin stops
the cursor at the bottom margin.
0

5.2.3.4

Cursor Forward (CUF)

ESC [ P n C
CUF moves the cursor to the right. The number of columns moved is
determined by P • If P i s " or 1, the cursor moves one position
to the right. Pf Pn i Q n, the ~ursor moves n posi tions to the
right. An attempt to move the cursor to the right of the right
margin stops the cursor at the right margin.
5.2.3.5

Cursor Position (CUP)

ESC [ P v ; Ph H
Pv = cursor vertical position (row)
Ph = cursor horizontal position (column)
CUP moves the cursor to the posi tion specified by P v and Ph. A
value of " or 1, or no value for P or Ph moves the cursor to the
first row or column, respectively. v

5-5

5.2.3.6

Cursor Up (CUU)

ESC [ P n A
CUU moves the cursor up without changing column position. The
number of rows moved is determined by P n • If P
i s " or 1, the
cursor moves up one row. If P n is n, the cursor nmoves up n rows.
An attempt to move the cursor above the top margin stops the
cursor at the top margin.
5.2.3.7

Device Attributes (DA)

ESC [ P n c
The user program sends DA with P equal to " or not present. DA is
a request for the control panel nmemory emulation code to transmit
the VT278 characteristics back to the user program in the
following ESCape sequence.
ESC [ ? 8 ; P s c

Ps
"
1
2
3

= configuration-dependent parameter)

Configuration
Basic VT278
32K memory
Basic VT278 plus communication option
32K memory plus communication option

If the VT278 contains the foreign language support option, the
ESCape sequence that responds to the DA request is extended as
follows.
ESC [ ? 8 ; Ps ; PI c
P s is already defined
keyboard language.
PI

this

paragraph

and

indicates

Keyboard Language
German
Dutch
French
French-Canadian

2
3
4

5.2.3.8

Erase in Display (ED)

ESC [ P n J
ED erases some or all characters on the screen according to P n •

Pn
"
1

Function
Erase from current cursor position to end of screen,
inclusive.
Erase from start of screen to current position,
inclusive.
Erase entire screen.

In all cases, the cursor position does not change.
5-6

the

5.2.3.9

Erase in Line (EL)

ESC [ P n K
EL erases some or all characters in the current line according to
Pn •
Pn

o
I

Function
Erase from current cursor position to end of line,
inclusive.
Erase from start of line to current cursor position,
inclusive.
Erase entire line.

In all cases the cursor position does not change.

5.2.3.10

Device Status Report (DSR)

ESC [ 6 r
DSR is a request from the user program for the emulation firmware
to report the current cursor position via a CPR sequence
(Paragraph 5.2.3.1).

5.2.3.11

Horizontal and Vertical position (HVP)

ESC [ P v ; Ph f

Pv = cursor vertical position (row)
Ph = cursor horizontal position (column)
HVP is identical to CUP. It moves the cursor to the posi tion
specified by P and Ph. A value of 0 or 1, or no value for P or
v
Ph moves the cursor to the first row or column, respectively. v

5.2.3.12

Index (IND)

ESC D
IND moves the cursor down one row without changing column
position. If the cursor is at the bottom margin, a scroll up is
performed.

5.2.3.13

Next Line (NEL)

ESC E
NEL moves the cursor to the first position on the next row. If the
cursor is at the bottom margin, a scroll up is performed.

5-7

5.2.3.14

Reverse Index (RI)

ESC M
RI moves the cursor up to the preced ing row without chang ing
horizontal position. If the cursor is at the top margin, a scroll
down is performed.
Select Character Set (SCS)

5.2.3.15

Define G0 set
Define Gl set
These sequences allow the user program to predefine two alternate
character sets as G0 and Gl. Once defined, the character sets can
be selected by transmitting SI (017 8 ) for G0 or SO (016 8 ) for Gl.
F
AX
B

Representation
United Kingdom Set
USASCII Set
Special Graphics
Alternate Character ROM
Alternate Character ROM, Special Graphics
French-Canadian
Dutch
German
French

1
2
3*
4*
K*
R*

* Only available on VT278 systems equipped with extended language
option.
5.2.3.16
ESC [ Pn

Select Graphic Rendition (SGR)
;~ ••• ;

Pn m

SGR establishes the attributes to be
characters sent to the screen according
for P n •
P

1
4
5
7

appended to subsequent
to the following values

Action
All attributes off
Display at increased intensity
Display underscored
Display blinking
Display negative (reverse) image

There are four display intensi ty levels at a given br ightness
setting: 0, 1, 2, and 3. (Where 0 is no display and 1, 2, and 3
are sequentially increasing levels of intensity.) Certain
combinations of attributes result in displays as follows.

5-8

Character/Underscore
Level

Background
Level

"13

4
5
1;4
1;5
4;5
1;4;5
7
1;7
4;7
5;7
1;4;7
1;5;7
4;5;7
1;4;5;7

"
"

2/1*
3
3/2*
2/1*
3/2*

13
13
13

"13

3
2
2/1*
3
3/2*
2/1*
3/2*

"
"""
13

* The display levels indicated alternate at the BLINK rate.
5.2.3.17

Keypad Application Mode (DECKPAM)

ESC =
DECKPAM allows the keys on
following ESCape sequences:
Key

aux il iary keypad

ESCape Sequence
ESC 0 P
ESC 0 q
ESC 0 r
ESC 0 s
ESC 0 t
ESC 0 u
ESC 0 v
ESC 0 w
ESC 0 x
ESC 0 Y

"1
2
3
4
5

7
8

In addition,
sequences:
Cursor
Key
Up
Down
Right
Left

the

Control

--)
(--

cursor

Key

,
ENTER
PF1
PF2
PF3
PF4

control

keys

ESCape Sequence
(Set Mode) *
ESC 0 A
ESC 0 B
ESC 0 C
ESC 0 D

* Paragraphs 5.2.3.19
reset mode (RM).

and

5.2.3.20

5-9

transmi t

the

ESCape Sequence
ESC 0 m
ESC 0 1
ESC 0 n
ESC 0 m
ESC 0 P
ESC 0 Q
ESC 0 R
ESC 0 S

transmit

the

following

ESCape

ESCape Sequence
(Reset Mode) *
ESC [ A
ESC [ B
ESC [ C
ESC [ D
describe

set -mode

(SM)

and

5.2.3.18

Keypad Numeric Mode (DECKPNM)

ESC >
In this mode, auxiliary keypad keys transmit codes that match the
characters on the keys.
Key
0
1
2
3
4
5

Character
0
1
2
3
4
5

7
8

Key

Character

,
ENTER
PF1
PF2
PF3
PF4

Return (015)
ESC 0 P
ESC 0 Q
ESC 0 R
ESC 0 S

Cursor control keys transmit cursor control codes.
Key
Up
Down
Right
Left

Sequence
ESC [ 1 A
ESC [ 1 B
ESC [ 1 C
ESC [ 1 D

i
V
--)
(--

5.2.3.19
ESC [ ? Ps

Set Mode (SM)
i •••• i

Ps h

SM sets one or more modes as specified by each parameter in the
parameter string. A mode is considered set until it is reset by a
reset mode (RM) sequence.
Function
Cursor key*.
Set 132-co1umn mode
Set Auto-repeat

Mnemonic
DECCKM
DECCOLM
DECARM

* See keypad application mode, DECKPAM, Paragraph 5.2.3.1
5.2.3.20

Reset Mode (RM)

ESC [ ? P s i •••• i P s 1
RM resets one or more modes as specified by each parameter in the
parameter string.
Function
Cursor key*
Reset to 80-column mode
Reset to nonrepeating keys

Mnemonic
DECCKM
DECCOLM
DECARM

* See keypad application mode, DECKPAM, Paragraph 5.2.3.17
5-10

5.2.3.21

Save Cursor (DECSC)

ESC 7
DECSC saves the
character set.
5.2.3.22

current cursor

position,

graphic

rendition,

and

Restore Cursor (DECRC)

ESC 8
DECRC restores the previously
rendition, and character set.
5.2.3.23

saved

cursor

position,

graphic

Print Screen (DECPRS)

ESC [ i
DECPRS transfers the screen contents to the serial printer port.
The VT278 remains in panel memory until this function is
completed.
5.2.3.24

Load LEDs (DECLL)

ESC [ P s q
DECLL allows the user program to control the programmable LEDs on
the keyboard.
Ps
0
1

2
3

4
5

Action
Turn OFF all five LEDs
Turn ON LED I
Turn ON LED 2
Turn ON LED 3
Turn ON LED 4
Turn ON LED DSR

5.2.4
Keyboard/Display Programming Examples
The program in example 1 continues to accept characters unti 1 a
dollar sign ($) is typed at the keyboard. It then stores 0000 in
the next memory location and halts.
The program in example 2 types the characters whose ASCII codes
were stored by the first program, and halts when a location with
contents equal to zero is reached. Both programs use locations
beginning at 2000 as a storage buffer for the ASCII characters.

5-11

Example 1
*200
START,
LISN,

DONE,
BUFF
BUFFPT,
MDOLAR,
$
Example 2
*300
START,

CHRTYP,

CRLF,

Program to Accept ASCII Characters
CLA CLL
TAD BUFF
DCA BUFFPT
KSF
JMP .-1
KRB
TLS
DCA I BUFFPT
TAD I BUFFPT
TAD MDOLAR
SNA
JMP DONE
ISZ BUFFPT
JMP LISN
CLA CLL
DCA I BUFFPT
HLT
2000

7534

Program to Print Out ASCII Characters
CLA CLL
TLS
TAD- BUFF
DCA BUFFPT
JMS CRLF
TAD I BUFFPT
SNA
HLT
JMS TYPE
ISZ BUFFPT
JMP CHRTYP

TAD K215
JMS TYPE
TAD K212
JMS TYPE
JMP I CRLF
TYPE,

BUFF,
BUFFPT,
K215,
K212,
$

/CLEAR ACCUMULATOR AND LINK
/SET UP BUFFER-SPACE
/AND INITIALIZE POINTER
/KEYBOARD STRUCK YET?
/NO: CHECK AGAIN
/YES: GET THE CHARACTER
/ACKNOWLEDGE IT ON PRINTER
/STORE THE CHARACTER
/CHECK FOR TERMINAL
/DOLLAR SIGN ($)
/IS CHARACTER A US"?
/YES: STORE ZERO OVER $
/NO: INCREMENT POINTER
/GET ANOTHER CHARACTER
/CLEAR ACCUMULATOR
/STORE ZERO IN LAST
/BUFFER LOCATION AND HALT
/BUFFER BEGINS AT
/CORE LOCATION 2000
/TWO'S COMPLEMENT OF 0244

TSF
JMP .-1
TLS
CLA CLL
JMP I TYPE
2000

215
212

/CLEAR ACCUMULATOR AND LINK
/RAISE PRINTER FLAG
/SET UP BUFFER SPACE AND
/INITIALIZE BUFFER POINTER
/RETURN CARRIAGE
/GET A CHARACTER
/IS IT ALL ZEROS?
/YES: HALT
/NO: TYPE THE CHARACTER
/INCREMENT BUFFER POINTER
/GET ANOTHER CHARACTER
/CRLF SUBROUTINE
/GET ASCII CARRIAGE RETURN
/PRINT IT
/GET ASCII LINE FEED
/PRINT IT
/AND.RETURN
/TYPE SUBROUTINE
/PRINTER READY YET?
/NO: CHECK AGAIN
/YES: TYPE CHARACTER
/CLEAR ACCUMULATOR
/AND RETURN
/BUFFER BEGINS AT
/CORE LOCATION 2000
/ASCII CARRIAGE RETURN
/ASCII LINE FEED
5-12

5.3
PRINTER INSTRUCTIONS
A 25-pin male connector at the rear of the VT278 allows you to use
anyone of a variety of serial printers (LQP02, LA34, etc.) that
are RS232-compatible. When- power is turned on to the VT278, the
baud rate for the printer is initially set at 9600 baud. You can
change the baud rate by using the TSB2 (lOT 6333) instruction.
This instruction is described in Table 5-3 wi th the remaining
printer instructions. Instructions with device code 33 are for
output of data from the AC to the printer. Instructions wi th
device code 32 are for inputting data from the printer to the AC.

Table 5-3

Printer Instructions

Mnemonic

Octal

Description

KCF2

6320

Set printer input flag.

KSF2

6321

Skip on printer input flag -- If printer
flag changed from false to true since this
lOT was last issued, the next instruction
is skipped. If skip occurs, printer input
flag is cleared.

KCC2

6322

NOP

KIE2

6325

Printer input interrupt enable -Enables/disables interrupts by printer
input flag according to content of AC11:
ACll=0 -- clear interrupt enable; ACll=l
-- set interrupt enable.

KRB2

6326

Transfer printer input data to AC<4:ll> -Contents of input buffer are transferred
to AC<4:11> and printer input flag is set.

SPF2

6330

Set printer input flag (TTI2).

TSF2

6331

Skip on printer output flag -- If printer
interface flag changed from false to true
since the lOT was last issued, the next
instruction is skipped. If skip occurs,
printer output flag is cleared. This flag
changes from false to true after printer
interface is read by a 6336 instruction
and interrupts if printer output
interrupts are enabled.

TCF2

6332

Clear AC.

TSB2

6333

Set baud rate
Printer port baud rate is
set according to contents of AC<8:11>:

5-13

Table 5-3

Printer Instructions (Cont)

Mnemonic

Octal

Description
Conts

Rate

1
2
3
4
5
6
7

Conts

Rate

18~~

11
12
13
14
15
16
17

2~~~
24~0

11~

134.5
15~

3~0
6~~
12~~

36~~
48~~
72~0
96~0
192~~

TIE2

6335

Printer output interrupt enable -Enables/disables interrupts by printer
input flag according to content of AC11:
AC11=~ -- clear interrupt enable; AC11=1
-- set interrupt enable.

TLS2

6336

Transfer AC<4:11> to printer -- Contents
of AC<4:11> are transferred to printer
buffer. Printer output flag is set when
print operation is completed.

5.4
REAL-TIME CLOCK INSTRUCTIONS
The real-time clock is crystal controlled and operates at 10~ Hz.
It has a basic accuracy of +0.~1 percent. Since the clock is
crystal controlled, cumulati ve- errors can be expected, but they
will not exceed +3 seconds in an 8 hour period.
The instructions
clock.

descr ibed

Table

5-4

control

the

real-time

5.5
RX278 DISKETTE SUBSYSTEM
The RX278 controller is an integral part of the VT278. Either one
or two pairs of floppy disk drives can be connected to the
controller. Dr ives can be RX~l (single densi ty) or RX~2 (double
density) and any combination of RX~l and RX~2 drives can be used.
However, some DEC standard software may require that the drives be
of the same type. RX~2 drives can be programmed for either single
or double density recording. RX~l drives will only operate in
single density mode.
5.5.1
RX278 Diskette Subsystem Instruction Set
The RX278 controller allows two modes of data transfer between the
VT278 and the floppy disk drives: 8-bit and 12-bit word lengths.
For the RX~l, in l2-bit mode, 64 words are written in a diskette
sector, requiring two sectors to store one page of information.
The diskette capacity in this .mode is 128,128 12-bit words (10~1
pages). In 8-bit transfer mode, 128 8-bit words are written in
each sector. Diskette capacity is 256,256 8-bit words, which is a
5-14

Table 5-4

Real-Time Clock Instructions

Mnemonic

Octal

Description

CLLE

6135

Set/clear clock interrupt -Enables/disables interrupts by clock:
AC11=~ -- clear interrupt enable; AC11=1
-- set interrupt enable.

CLCL

6136

Clear clock flag.

CLSK

6137

Skip on clock flag -- Senses clock flag
and increments PC if set, thereby skipping
next sequential instruction.

33 percent increase in diskette capacity over 12-bit mode. The
has double si ze sectors wi th a capaci ty of 256,256 12-bi t
words, or 512,512 8-bi t wo rds. Si nce 12-bi t mode does not fully
pack the sectors wi th data, the hardware puts in extra ~s. Data
transfer requests occur 23 us after the previous request was
serviced for 12-bi t mode (918 us for 8-bi t mode). There is no
maximum time between the transfer request from the floppy disk
drive system and servicing that request by the processor. This
allows the data transfer to and from the floppy disk drive system
to be interrupted without loss of data.
RX~2

The format for RX278 instructions is shown in Figure 5-1 and the
error register, RX2ES, is shown in Figure 5-2. The instruction set
is described in Table 5-5.
00

~O~~I~__N~~_T_US~~_D__~IO_E_N~I__~1_8_/12_1~~lu_~_~~I__~F~~N_cr_IO~iN__~__
"

TRANSFER
BYTE 1

04:11

TRANSFER
BYTE 2

00:03

8BIT
MODE

MA-1792A

Figure 5-1 RX278 Diskette Subsystem Instruction Format

5-15

RESERVED
MA-6022

Figure 5-2 Error Status Register (RX2ES)

Table 5-5

RX278 Diskette Subsystem Instruction Set

Mnemonic

Octal

Description

SEL

6750

Select RX~1/RX~2 drive
AC<ll>=l, select drive
AC<11>=0, select drive
A is selected by a CAF
power-on time.

LCD

6751

Load command register -- Must only be
issued when DONE is true. The contents of
AC are loaded into the interface register,
and under timing control from RX~1/RX~2,
sent serially to RX~1/RX02. The AC is
cleared following this lOT. AC bit 5
selects 8- or 12-bit mode of data
transfer. l2-bit mode is set following CAF
or power-on. AC bit 7 selects right or
left drive of selected drive pair (0=left,
l=right) •

pair
If
pair B. If
pair A. Drive pair
instruction or at

This lOT clears the DONE flag (DONE=false)
and executes the function specified in AC
bits 8, 9, and 1~. The eight functions
that can be performed are listed below,
and explained in Paragraph 5.5.2.
AC<8:lS>
000
001
01~

011
100
101
110
III

Function
Fill buffer
Empty buffer
Write sector
Read sector
Change density
Read status
Write sector (deleted data)
Read error register

5-16

Table 5-5

RX278 Diskette Subsystem Instruction Set (Cont)

Mnemonic

Octal

Description
For an RX~2 in a-bit mode, the Load
command is stored in two a-bit transfers.
The first a bits of the command word (bits
4--11 in Figure 5-1) are stored. Then
transfer request (TR) is asserted and an
XDR is performed to transfer the remaining
bits of data (bit 3, DEN, and bit 2,
Figure 5-1) right-justified. Extra bits in
the second a-bit transfer are filled with
zeros. Upon completing the transfer of the
second a-bit byte, DONE is asserted to end
the function.

XDR

6752

Transfer data'-- Data is transferred
between the AC and the interface register.
When the DONE flag is cleared (false) the
direction of transfer depends on the
current function. When the DONE flag is
set (true) transfer is always to the AC.
DONE=falsei transfer to AC.
l2-bit mode: the AC is cleared, then the
contents of the interface register are
transferred to the AC<0:ll>.
8-bit mode: the contents of the interface
register are inclusive ORed with the
contents of the AC<4:ll>. The result is
placed in AC<4:ll>. Bits AC<0:3> are
unchanged.
DONE=falsei transfer to interface
register.
12-bit mode: the contents of the AC<0:l1>
are transferred to the interface register.
The AC is unchanged.
a-bit mode: the contents of AC<4:11> are
transferred to the interface register. The
AC is unchanged.
DONE=truei transfer to AC.
(Same as DONE=falsei transfer to AC).

5-17

Table 5-5

RX278 Diskette Subsystem Instruction Set (Cont)

Mnemonic

Octal

Description

STR

6753

Skip on transfer request -- If the
transfer request (TR) flag from RX01/RX02
changed from false to true since this lOT
was last issued, the next instruction is
skipped. If skip occurs, the flag is
cleared. This lOT does not change AC.
The TR flag should be tested prior to
transferring data or address words with
the XDR instruction to be sure data or
address has been received or transferred,
or after an LCD instruction to be sure the
command is in the interface register. When
an XDR follows an LCD, the flag only has
to be tested once between the two
instructions.

SER

6754

Skip on error -- If the ERROR flag from
the RX01/RX02 changed from false to true
since this lOT was last issued, the next
instruction is skipped. If skip occurs,
the ERROR flag is cleared. This lOT does
not change the AC.
Floppy disk drive system error status
reg ister (RX2ES) (Figure 5-2) contains the
current error and status conditions of the
selected drive. This read-only register
can be accessed by the read status
function (101). RX2ES is also available in
the interface register upon completion of
any function. RX2ES is accessed by the XDR
instruction. E~ror bit meanings are listed
in Table 5-6.

SDN

6755

Skip on done -- If the DONE flag from the
RX0l/RX02 changed from false to true since
this lOT was last issued, the next
instruction is skipped. If skip occurs,
the DONE flag is cleared. This flag will
interrupt if interrupts are enabled.

5-18

Table 5-5

RX278 Diskette Subsystem Instruction set (Cont)

Mnemonic

Octal

Description

INTR

6756

Interrupt enable -- Enables/disables
interrupts by DONE flag according to the
contents of ACIl: ACIl=0
clear
interrupt enable; AClI=l -- set interrupt
enable.
DONE flag interrupts are disabled by CAF
instruction and following power-on.

RXINIT

6757

Initialize RXSl/RX02 -- The following are
cleared:
DONE flag
Transfer request flag
ERROR flag
Interrupt enable
Unit select set to A.
All drives connected are caused to
initialize.
At the end of the operation the DONE flag
is set. The AC is not changed by this rOT.

5-19

Table 5-6

Error Status Register (RX2ES) Bit Functions

Bit

Description

CRC error -- Cyclic redundancy check at end of data field
has indicated an error. Data must be considered invalid.
It is suggested that data transfer be retried up to 10
times, as most data errors are recoverable (soft).

Reserved.

Initialize done -- Indicates completion of initialize
routine. Can be asserted due to RX02 power failure, system
power failure, or programmable or bus initialize. Bit is
not available within RX2ES from a read status function.

RX02 -- Asserted if RX02 system being used.

DEN ERR -- Indicates that density of function does not
agree with drive density. Upon detection of this error
control terminates operation and asserts ERROR and DONE.

DRV DEN -- Indicates density of diskette in drive selected
(0=single, l=double).

Deleted data (DD) -- While reading data, a deleted data
mark was detected in the identification field. Data
following will be collected and transferred normally,
since deleted data mark has no further significance within
RX02. Any alteration of files or actual deletion of data
due to this mark must be done by user software. This bit
will be set if a successful or unsuccessful write deleted
data function is performed.

Drive ready -- Asserted if unit currently selected exists,
is properly supplied with power, has a diskette installed
properly, has its door closed, and has a diskette up to
speed.

5.5.2
Load Command Function Codes
RX0l/RX02 functions are ini tiated by means of the Load command
described in Table 5-5. The done flag should be tested and cleared
with the SDN instruction in order to verify that the RX0l/RX02 is
in the Done state pr ior to issuing the command instruction. Upon
receiving a command instruction while in the Done state, the
RX0l/RX02 enters the Not Done state while the command is decoded.
Each of the eight functions summarized below requires that a
strict protocol be followed for the successful transfer of data,
status, and address information. The protocol for each function is
described in the following paragraphs.
5-20

5.5.2.1 Fill Buffer (999) -- Fill buffer loads the floppy disk
drive system sector buffer from the processor with 64 words in
12-bit mode or 128 words in 8-bit mode for the RX01 and 128 words
in 12-bit mode or 256 words in 8-bit mode for the RX02. This
instruction only loads the sector buffer. To complete the transfer
to the diskette, the write sector function must then be performed.
The buffer may also be read back by means of the empty buffer
function to verify the data.
Upon decoding the fill buffer function, the floppy disk drive
system sets the transfer request (TR) flag signaling a request for
the first data word. The TR flag must be tested and cleared by the
processor with the skip on transfer request (STR) instruction
prior to each successive XDR lOT. The data word can then be
transferred to the interface register by means of the XDR lOT. The
floppy disk drive system then moves the data word from the
interface register to the sector buffer and sets the TR flag as a
request for the next data word. This sequence is repeated until
the sector buffer has been loaded. After the last word has been
loaded into the sector buffer, the content of the error status
register (RX2ES) moves to the interface register and the floppy
disk drive system sets the done flag to indicate the completion of
the function. The processor does not have to count the data
transfers. Any XDR command, after Done is set, loads the RX2ES
status word into the AC. The sector buffer must be completely
loaded before the interface sets the done flip-flop and recognizes
a new command. An interrupt would now occur if the interrupt
enable flip-flop were set.
5.5.2.2 Empty Buffer (901)
This function moves the contents of
the sector buffer to the processor. When the empty buffer function
is decoded, RX2ES bit 11 is cleared, and the TR flag is set with
the first data word in the interface register. This TR flag
requests a data transfer from the buffer to the processor. The
flag must be tested and cleared, then the word can be moved to the
AC by an XDR command. The direction of transfer for an XDR command
is controlled by the floppy disk drive system. The TR flag is set
again with the next word in the interface register. This sequence
is repeated until all words have been transferred, thus emptying
the sector buffer. The done flag is set after the RX2ES moves into
the interface register indicating the end of the function. An
interrupt would now occur if the interrupt enable flip-flop were
set.
NOTE: The empty buffer function does not destroy the contents of
the sector buffer.
5.5.2.3 Write Sector ("19)
This function transfers the
contents of the sector buffer to a specific track and sector on
the diskette. Upon decoding this function, the interface clears
bit 11 of the RX2ES and sets the TR flag, signifying a request for
the sector address. The TR flag must be tested and cleared before
the sector address can be loaded into the interface register by
the XDR command.

5-21

The TR flag is set again, signifying a request for the track
address. The TR flag must be tested and cleared; then the track
address may be loaded into the interface register by the XDR
command.
The floppy disk dr i ve system tests the suppl ied track add ress to
determine if it is wi thin allowable 1 imi ts. If not, the RX2ES
moves to the interface register, the error and done flags are set,
and the function is terminated.
If the track address is legal, the floppy disk drive moves the
head of the selected dr ive to the selected track, locates the
requested sector, transfers the contents of the sector buffer and
a CRC character to that sector, and sets the done flip-flop. An¥
errors encountered in the seek operation cause the function to
cease, the RX2ES to be loaded into the interface register, and the
error and done flags to be set. If no errors are encountered, the
RX2ES is loaded into the interface register and only the done flag
is set.
NOTE: The write sector function does not destroy the contents of
the sector buffer.
5.5.2.4 Read Sector (0ll) -- This function moves a sector of data
from a specified track and sector on the floppy disk to the sector
buffer. Upon decoding this function, the RX01/RX02 clears RX2ES
bits 5 and 11 (deleted data and CRC error, respectively) and sets
the TR flag signifying the request for the sector address. The
flag must be tested and cleared. The sector address is then loaded
into the interface register by the XDR command. The TR flag is set
again signi fying a request for the track address. The flag is
tested and cleared by the processor, and the track address is then
loaded into the interface register by an XDR command. The legality
of the track address is checked by the floppy disk drive system.
If illegal, the error and done flags are set when RX2ES moves to
the interface register, and the function is terminated. Otherwise,
the floppy disk drive system moves the head to the specified
track, locates the specified sector, transfers the data to the
sector buffer, and computes and checks CRC for data. If no errors
occur, the done flag is set with the RX2ES in the interface
register. If an error occurs anytime during execution of the
function, the function is terminated by setting the error and done
flags wi th RX2ES in the interface reg ister. Detection of a CRC
error resul ts in RX2ES bi t 11 being set. If a deleted data mark
was encountered at the beginning of the desired data field, RX2ES
bit 5 is set.
5.5.2.5 Change Density (100) -- This function operates as a NOP
for RX01 drives. For RX02 drives, the new density is selected
using AC bit 3: 0 = single density; 1 = double density.

5-22

5.5.2.6 Read Status (101) -- Upon decoding this function, the
floppy disk drive system moves the RX2ES to the interface register
and sets the done flag. The RX2ES can then be read by the XDR.
NOTE: The avera e time for this function is 250 ms. Excessive use
of this function results in substantially reduced throug put.
5.5.2.7 Write Deleted Data Sector (110)
This function is
identical to the wr i te data function except that a deleted data
mark is written prior to the data field rather than the normal
data mark. RX2ES bit 5 (deleted data) will be set in the interface
register upon completion of the function.
5.5.2.8 Read Error Register Function (Ill)
The read error
register function can be used to retrieve explicit error
information upon detection of the error flag. Upon receiving this
function, the floppy disk drive system moves an error code to the
interface register and sets the done flip-flop. The interface
register can then be read via an XDR command and the code
interrogated to determine which type of failure occurred.
Table 5-7 lists the read error register functions.

Table 5-7

Read Error Register Codes

Octal
Code

Error Code Meaning

0010
0020
0040
0050
0070
0110
0120
0130
0150
0160
0170
0200
0220
0240
0250

Drive 0 failed to see home on initialize.
Drive 1 failed to see home on initialize.
Tried to access track greater than 76.
Home found before desired track reached.
DeSired sector not found after looking at 52 headers (2
revolutions) •
More than 40 us and no SEP clock seen.
Preamble could not be found.
Preamble found but no ID mark found within allowable
time span.
Header track address of good header does not compare
with desired track.
Too many tries for an IDAM (identifies header).
Data AM not found in allotted time.
CRC error on reading sector from disk.
R/W electronics failed maintenance mode test.
Density error.
Wrong key word for set media density command.

5-23

5.5.3
Programming Examples (RX0l/RX02)
The following programming examples demonstrate a technique for
reading data from a sector into the floppy disk interface buffer
(example 1), and then transferring the data into main memory
(example 2).
Floppy Disk Programming Example 1
/READ SECTOR EXAMPLE
TAD (FUNCT
LCD
STR
JMP.-l
TAD (SECT
XDR
CLA
STR
JMP.-l
TAD (TRACK
XDR
CLA
SDN
JMP.-1
SER
JMP GOODRD
JMP ERRREC

/FUNCTION = 000 000 000 110
/(bits <8:10> = 011)
/SEND TO RX
/WAIT FOR REQUEST FOR SECTOR ADDRESS
/GET SECTOR ADDRESS
/AND TRANSFER TO RX
/XDR DOES NOT CLEAR AC
/NOW WAIT FOR REQUEST FOR TRACK ADDRESS
/GET TRACK ADDRESS
/SEND TO RX
/NOW WAIT FOR FUNCTION TO COMPLETE
/WERE THERE ERRORS?
/NO, GO ON
/YES, GO TO ERROR RECOVERY

GOODRD,

ERRREC,

5-24

Floppy Disk Programming Example 2
/EMPTY SECTOR BUFFER EXAMPLE

MORDAT,

DONTST,

TAD (BUFST-l
DCA AUTOl0
TAD (FUNCT
LCD
STR
JMP DONTST
XDR
DCA I AUTOl0
SDN
JMP MORDAT
SER
JMP GOOD
JMP ERRREC

/SET UP BUFFER POINTER
/LOAD INTO AUTO-INDEX REGISTER
/000 000 000 010 (Bits <8:10> = 001)
/SEND TO RX
/WAIT FOR DATA WORD
/IF NOT SET, TRY DONE FLAG
/WORD AVAILABLE
/BUFFER EMPTIED YET?
/NO, GO BACK AND WAIT FOR NEXT WORD
/BUFFER EMPTY, CHECK ERRORS
/NO ERRORS, GO ON
/ERRORS, GO TO RECOVERY ROUTINE

GOOD,
ERRREC,

5.6
PROGRAMMING CONSIDERATIONS
The proper procedure for servicing interrupts in time
applications is discussed in the following paragraph.

critical

5.6.1
Critical Interrupt Servicing
It is possible that the VT278 will periodically disable the main
memory interrupt system for periods of up to 1 millisecond during
the process of updating the displ ay buffer memory. In a time
critical application, the keyboard and display may be disabled to
allow the CPU to ded icate i tsel f to interrupt serv lClng. The
effect of disabling the keyboard and display is that the CRT
controller continues to refresh the screen with the last contents
of the display buffer memory and the keyboard no longer responds
to keystrokes (no keyclick). Any user programs that change the
status of the keyboard/display must be carefully debugged. Failure
to return to the correctly enabled state requires that the system
be powered down to reactivate the keyboard.
The recommended sequence to disable the keyboard and display is:
CLA
6125
6115
and to reenable:
CAF
CLA lAC
6125
6115
5-25

NOTE: When display/keyboard interrupts are disabled the following
loop hangs after some number of characters have been transmitted:
lAC
TLS
TSF
JMP .-1
JMP .-4

5-26

CHAPTER 6
PROGRAMMING THE DP278

6.1
INTRODUCTION
This chapter contains general programming information and register
bit assignments for the DP278 Communication Option. The DP278 is
available in two variations:
1.

DP278-A is the basic two-port option. Each port contains
a standard communications device (SCD) whose internal
registers can be programmed for asynchronous and
byte-synchronous operation.

DP278-B is similar to DP278-A, but each port contains an
additional extended synchronous device (ESD) that can be
programmed
to
permit
both
byte-synchronous
and
bit-synchronous (BITSTUFF) operation.

6.2
DP278 INTERRUPTS
The DP278 can generate three types of interrupts, all of which may
be vectored to determine the cause of interrupt.
1.
2.
3.

Receiver interrupts
Transmitter interrupts
Modem change interrupts

6.2.1
Receiver Interrupts
Each port can generate a receiver interrupt, if enabled, when
either a new character is assembled from the communications line
or when a parity, overrun, or CRC (ESD only) error, is detected.
6.2.2
Transmitter Interrupts
Each port may generate a transmitter interrupt, if enabled, when
either it is permissable to load a new character for transmission,
or when a transmitter underflow occurs (ESD only) •
6.2.3
Modem Change Interrupt
When ei ther port 'detects a change of state on any incoming modem
control line, if enabled, this interrupt flags the change of modem
state. The user program may, at any time, issue an lOT instruction
to examine the contents of either port's modem control register.
6.3
DP278-A STANDARD COMMUNICATIONS OPTION
The DP278-A standard communications option is a dual universal
asynchronous/synchronous data communications controller. You can

6-1

pro g ram i t t 0 t ran sm i t a n d r e c e i v e e i the r s y n c h ron 0 us 0 r
asynchronous data in full- or half-duplex operation. Transmitted
data is received from the VT278 DX bus and ser i al i zed for 1 ine
transmission. Received data is presented in an 8-bit parallel
format to the DX bus.

6.3.1
Asynchronous Operation (SCD)
Under asynchronous operation, the SCD can be programmed to:

•

Transmit/receive 5-, 6-, 7-, or a-bit characters

•

Insert 1,
length)

•
•

Compute and insert a parity bit, and

1.5,

2 stop bits

(dependent on character

Detect parity, framing, and overrun errors.

6.3.2
Synchronous Operation (SCD)
Under synchronous operation, the SCD can be programmed to:

•
•
•
•

Transmit/receive 5-, 6-, 7-, or a-bit characters

•

Allow for automatic SYN-SYN or DLE-SYN character fill.

Compute and insert a parity bit
Recognize and synchronize upon one or two SYN characters
Perform automatic SYN or SYN-DLE insertion and SYN or DLE
character stripping, and

6.3.3
Clocking (SCD)
For the SCD, use internal clocking for both asynchronous and
maintenance mode operation. Use external clocking for synchronous
operation.
6.3.4
Maintenance Mode Operation (SCD)
There are two types of maintenance checks:
1.

Local loopback -- causes the communications device to
internally connect its transmitter output to receiver
input and, therefore, check for parity, status, overrun,
and framing errors.

Remote loopback -- permits a remote modem to send data to
the communications device and have that data sent back
wi thout send ing it to the DX bus. The communications
device status register reports any send or receive
errors.

6.3.5
Standard Communications Device (SCD) Registers
Table 6-1 lists the SCD internal regist~rs that can be accessed
under program control.

6-2

Table 6-1

SCD Internal Register Addressing

Type

Receive holding register
Transmit holding register
SYNl, SYN2, or DLE
Internal status
Mode register 1
Mode register 2
Command

Read
Write
Write only
Read only
Read/write
Read/write
Read/write

AC<1:3>
Read
Write
000
001
011
010
100
100
110

101
101
III

Some registers are read only, some are write only, and some can be
either read from or written to. Each register is accessed by
setting accumulator bits AC<1:3> with the correct register
addressing information and then executing the appropriate rOT
instruction to read from, or write to, a particular port. The rOT
instructions are for device codes 30, 31, 34, and 35.
rn addi tion, the DP278-A has a modem reg ister, a port control
reg i ster, and a port status reg i ster for each port. Thi sallows
you to program modem controls and to read port and modem status.
These registers are accessed by rOT instructions for device code
36 and are described in Paragraph 6.5.2.
Pro g r a mm i n g the DP 2 7 8 r e qui res a n i nit i ali z a t ion pro c e s s t 0
configure the internal registers before data transmission. Figure
6-1 demonstrates a typical programming sequence for ini tiali zing
the seD. SCD register bit definitions are described in Tables 6-2
thro ugh 6-6.

6-3

INITIAL RESET

NOTE 1 ~------r-----~

YES

NOTE2~____~______~

NOTE2~

____~~____~

NOTES
1. MODE REGISTER 1 MUST BE WRITTEN
BEFORE 2 CAN BE WRITTEN. MODE
REGISTER 2 NEED NOT BE PROGRAMMED
IF EXTERNAL CLOCKS ARE USED.
2. SYN1 REGISTER MUST BE WRITTEN
BEFORE SYN2 CAN BE WRITTEN, AND
SYN2 BEFORE DLE CAN BE WRITTEN.

Figure 6-1

MA·6444

seD Programming Flowchart

6-4

Table 6-2

seD: SYNl, SYN2, or DLE Register Bit Definitions
00

AC
REGISTER
ADDRESSING
MA-7041

Bits

Definition
Not used

1--3

4--11

SYNl, SYN2, or OLE character (bits 7--eJ)

NOTE: SYNl, SYN2, and OLE are accessed via write operations with
conditions A1 =eJ, A~=l, and R/W=l. The first operation loads SYNli
the next loaas SYN2i the third loads OLE. If the required number
of accesses is exceeded, the internal sequencer cycles to point at
the first register. The pointer can be reset to the SYNI register
via a "read command register" operation or by an lOT 6367 (RESET
communications device).
lOT instruction 6367 resets all registers in the associated
devices in a port. Therefore, the registers must be reprogrammed.

6-5

Table 6-3

SCD: Internal Status Register Bit Definitions
01

DATA
CARRIER
DETECT
(ALWAYS
TRUE)
DATA SET
READY
(ALWAYS
TRUE)

Bits

OVERRUN

FE/SYN
DETECT

TXEMT/
DSCHG

PE/DLE
DETECT

TXRDY

RXRDY

MA-7042

Description
No t used

1--3

Data set ready -- always set to logical 1.

Data carrier detect -- always set to logical 1.

FE/SYN detect -- FE (framing error) detected during Asynch
mode operation. Set if character received was not followed
by a valid stop bit. SYN (SYN character) detected during
Synch mode operation.
Asynch: 0=normal; l=framing error.
Synch:
0=normal; l=SYN character detected.

Overrun -- set during Asynch mode if preceding character
was lost because receiver failed to keep up with incoming
character rate on this port.
0=normal
l=overrun error

PE/DLE detect -- set if character was received with a
parity sense opposite to that selected for this port. For
Synch operation, also may mean a OLE character was
received.
Asynch: 0=normal; l=parity error.
Synch:
0=normal; l=parity error or OLE character
received.

TxEMT/DSCHG -- set when transmit shift register is empty.
0=normal
l=transmit shift register empty

6-6

Table 6-3

SCD:

Internal Status Register Bit Definitions (Cont)

Bits

Description

RxRDY

0=receive holding register empty
l=receive holding register has data
11

TxRDY

0=transmit holding register busy
l=transmit holding register empty

6-7

Table 6-4

seD: Mode Register 1 Bit Definitions

ASYNCH{~T~P
LENGTH

NOT
USED

I
04

PARITY
TYPE

CH~~~;T~~~

SYNCH
{

MODE AND
BAUD RATE
FACTOR

PARITY
CONTROL

TRANSPARENCY
CONTROL (SYNCH) - _.....
MA-7043

Bits

Description
Unused

1--3

For synch operation, this bit represents the number of SYN
characters:
0=double SYN
1=sing1e SYN

For synch operation, this bit controls transparency:
0=normal
1=transparent

4--5

For asynch operation, these bits represent the stop code
length:
00=invalid
01=1 stop bit
10=1.5 stop bit (for 5-bit characters)
11=2 stop bits.

Parity type -- specifies whether port is to have even or
odd parity generated and checked. Has no effect unless bit
7 (parity control) is set.
0=odd
1=even

6-8

Table 6-4

SCD: Mode Register I Bit Definitions (Cont)

Bits

Description

Parity control -- specifies whether a parity bit is
generated on transmission and checked and stripped on
reception:
0=no parity bit
l=parity enabled.

8--9

Character length -- specifies the character length (not
counting start bit, stop bits, and parity bit if enabled)
for selected port.
00=5
01=6
10=7
11=8

10--11

bit chars.
bit chars.
bit chars.
bit chars.

Mode and baud rate factor -- selects mode (asynch or
synch) and baud rate factor (see note 2).
00=synchronous 1 X rate
01=asynchronous 1 X rate
10=asynchronous 16 X rate
II=asynchronous 64 X rate

NOTES:
1. Mode registers 1 and 2 are accessed via read operations with
~1=1, A~~0, and R/W=0, or write operations with A1 =1, A0 =0,
R/w=l. The first read (write) operation addr~sses mode register
1; a second operation addresses register 2. If the required
number of accesses are exceeded, the internal sequencer cycles
to point at the first register. The pointer can be reset to
register 1 by performing a "read command register" operation or
by an lOT 6367 (RESET communications device).
lOT instruction 6367 resets all registers in the associated
devices in a port. Therefore, the reglsters must be

reprogrammed~----------------------------------------

2 .• Asynchronous baud rate factor only applies if external clock is
selected for SCD mode register 2 (Table 6-4). However, one of
the asynchronous baud rate factors must be chosen. When
internal clock mode is selected from mode regISter-2,-the-clock
output from the SCD is 16X rate.

6-9

seD: Mode Register 2 Bit Definitions

Table 6-5

RECEIVER
CLOCK
SELECT
TRANSMITTER
CLOCK SE LECT
MA-7044

Bits

Description
Unused

1--3

1
1

0
'"

'" = Read mode register 2 (see note)
1 = Write mode register 2 (see note)

4--5

Unused

Transmitter clock
0=external
l=internal

Receiver clock
'" = external
1 = internal

8--11

Baud rate selection
specifies receiver and transmitter
speed of operation for selected port.
Bits
8
9
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1

10
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

11
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Baud
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
6-10

Table 6-5

SCD: Mode Register 2 Bit Definitions (Cont)

NOTE: Mode registers 1 and 2 are accessed via read operations with
AI =1, A0 =0, and R/W=0, or write operations with ~1-1, Aa-0, R/W=1.
Tfie first read (write) operation addresses mode reglster 1; a
second operation addresses register 2. If the required number of
accesses is exceeded, the internal sequencer cycles to point at
the first register. The pointer can be reset to register 1 by
performin a "read command re ister" 0 eration or by an lOT 6367
RESET communlcatlons devlce).
rOT instruction 6367 resets all re~is!~~s~~~he~ssociated
devices in a port. Therefore, the registers must be reprogrammed.

6-11

Table 6-6

SCD: Command Register Bit Definitions
00

REQUEST
TO
SEND
RESET
ERROR

DATA
TERMINAL
READY
RECEIVE
CONTROL

TRANSMIT
CONTROL

ASYNCH:FORCEBREAK
SYNCH: SEND OLE

Bits

Definition
Not used

1--3

4--5

Operating mode
00=normal operation
01=Asynch: automatic echo mode (echoplex); Synch: SYN
and/or OLE stripping mode.
10=local loopback
II=remote loopback

Request to send (RTS)--unused
0=force RTS output high
l=force RTS output low

Reset error
0=normal
l=reset error flag in status register (framing error,
overrun, PE/OLE detect)

Force break/send OLE
Asynch: force break
0=normal
l=force break.
Synch: send OLE
0=normal
l=send OLE.

6-12

Table 6-6

SCD: Command Register Bit Definitions (Cont)

Bits

Definition

Receive Control
0=disable
l=enable

NOTE: Whenever you enable the SCD Receive Control, you must also
perform a "dummy read." This operation clears the holding register
before any incoming characters are received, to ensure the device
will operate properly. You must perform the following steps:
1. Set AC<1:3> and AC9 to 1, and all other desired bits from Table
6-6, to write the Receive Control bit to the command register.
2. Execute an lOT 6316 (port 0) or lOT 6356 (port 1).
3. Set AC<1:3> to 0 to read the receive holdlng register (Table
6-1) •
4. Execute an lOT 6316 (port 0) or lOT 6356 (port 1).
10

Data Terminal Ready (DTR)--unused
0=force DTR output high
l=force DTR output low

Transmit Control
0=disable
l=enable

6.4
DP278-B EXTENDED COMMUNICATION OPTION
This version of the DP278 communication option adds the capability
of bit synchronous communication (BlTSTUFF) for such protocols as
X.25, HDLC, and SDLC. You can select, under program control,
whether a particular port operates as an SCD or ESD communication
device. Refer to Paragraph 6.3 for SCD programming information.
6.4.1
Synchronous Operation (ESD)
The DP278-B communication option can be programmed to:

•

Operate
in
a
bit-oriented
byte-control protocol (BCP);

•

Select character length (1 to 8 bits for BOP and 5 to 8
bi ts for BCP);

•

protocol

(BOP)

Provide SYNC or secondary address comparison for BCP/BOP;
Automatically detect and generate special
sequences, such as FLAG, ABORT, and GA;

6-13

BOP

control

•

Perform
BCP;

•

Perform CRC generation and checking.

SYNC

generation,

detection,

and

stripping

for

6.4.2
Clocking (ESD)
All clocking information for the ESD is derived from the incoming
modem lines. However, in maintenance mode, the SLUI clock is
substituted for the transmitter clock (TXCLK) input to each ESD.
6.4.3
Maintenance Mode Operation (ESD)
When maintenance mode is selected for the ESD, a local loopback
check similar to the SCD is enabled. Local loopback causes the
communication device to internally connect its transmitter output
to its receiver input.
6.4.4
Extended Synchronous Device (ESD) Registers
The following ESD internal registers can be accessed under program
control:
Register
Receiver data buffer
Receiver status
Transmitter data buffer
Transmitter status
Parameter control and control sync/address (PCSAR)
Data length select (PCSCR)

Type
Read only
Read only
Write only
Read/write
Read/write*
Read/write

* Two registers; each R/W.
Some registers are read only, some are write only, and some can be
either read from or written to. Each register is accessed by
setting accumulator bits AC<": 3> with the correct register
addressing information. Then the appropriate lOT instruction is
executed to read from, or write to, a particular port. lOT
instructions are for device codes 3", 31, 34, and 35.
In addition, the communication option has a modem register, a port
control register, and a port status register for each port. This
allows you to program modem control and to read port and modem
status. These registers are accessed by lOT instructions for
device code 36 and are described in Paragraph 6.5.2.
ESD register bit definitions are described in Tables 6-7 through
6-13.

6-14

Table 6-7

ESD: Receiver Data/Status Register (RDSR) Receiver
Status Bit Definitions

MA-7046

Bits

Definition

0--3

ERR CHK (error check) -- in BOP (bit oriented protocols),
this bit is set if CRC is selected and received in error.
Check this bit when bit REOM=I. In BCP (byte control
protocols) 1) This bit is set if parity is selected and
received in error. 2) If CRC is selected it is tested at
end of each byte. ERR CHR=1 if CRC is good; ERR CHR=0 if
CRC not good. Controller must determine last byte of
message.

5--7

ABC (assembled bit count) -- in BOP mode only, examine
when REOM=I. ABC="', message terminated on stated boundary.
ABC=XXX, message terminated by (FLAG,or GA) on unstated
boundary. Binary value of ABC=number of valid bits
available in receiver data buffer (ROB) right-justified.

ROR (receiver overrun) -- set to 1 when received data
transferred into ROB and previous data was not read,
indicating failure to service ROA (receiver data
available) within one character time. Cleared when
receiver status register is read, or when RXENA is
dropped.

RAB/GA (receiver abort or go ahead)
in BOP mode only,
if LM (loop mode)=~, this bit is set if an Abort character
is received. If LM=I, this bit is set if a Go Ahead
character is received. Bit is cleared when receiver status
register is read or when RXENA is dropped.

REOM (receiver end of message)
in BOP mode only, this
bit is set to 1 ·when the last byte of data is loaded into
the ROB (receiver data buffer) or when an Abort character
is received. Bit is cleared when receiver status register
is read or when RXENA is dropped.

RSOM (receiver start of message) -- in BOP mode only, this
bit is set to 1 when first non-flag (address byte) is
loaded into ROB (receiver data buffer). Bit is cleared
when second byte is loaded into ROB.
6-15

Table 6-8

ESD: Receiver Data/Status Register (RDSR), Receiver
Data Buffer Bit Definitions
00

I I .I I I"

07
A,
A,
A,
"/W
1" 0 +05 1"04 1"03 1RD21 RD.
. "
REGISTER
ADDRESSING

IROO I
,

RECEIVER
DATA (RDO-RD7)
MA-7047

Bits

Definition

0--3

4--11

Receiver data (bits RD<7:0»

6-16

Table 6-9

ESD: Transmitter Data/Status Register (TDSR)
Transmitter Buffer Bit Definitions

RAY

I I I I ITD71 I ITD41
REG I'STE R
ADDRESSING

TOe TO"

TOll

T02I TO. ITOO I

TRANSMITTERS
DATA (TOO-TD7l
MA.7048

Bits

Definition

9--3

4--11

Transmitter data (bits TD(7:S»

6-17

Table

6-l~

ESD: Transmitter Data/Status Register (TDSR)
Transmitter Status. and Control Register Bit
Definitions

Bits

Definition

0--3

TERR (transmitter error) -- read only bit. Underflow, set
high when TDB not loaded in time to maintain continuous
transmission. In BOP, automatically transmit: Abort if
IDLE=0; Flag if IDLE=l. In Bep, automatically transmit:
Sync if IDLE=~; Mark, cleared by TSOM if IDLE=l.

5--7

Not used

TXGA (transmit go ahead) -- R/W bit. In BOP mode only,
modifies character called for by TEOM. If set GA
character sent in place of Flag.

TXAB (transmitter abort) -- R/W bit. In BOP mode only,
TXAB=l: finish present character, then: transmit Abort if
IDLE=0; transmit Flag if IDLE=l.

TEOM (transmit end of message) -- R/W bit. Used to
terminate a message. In BOP mode: TEOM =1; send CRC, then
Flag; if TXENA=l and TEOM=l, continue to send Flag; if
TXENA=~ and TEOM=l, Mark line.
In BCP:
IDLE=0, TEOM=l: send eRC, then SYNCH
IDLE=l, TEOM=l: send CRC, then character from the
transmitter data buffer.
If eRC not selected, do not set TEOM.

TSOM (transmit start of message) -- R/W bit. If TXENA=l,
TSOM initiates start of message. In BOP mode: TSOM=l
generates Flag and continues to send Flags until TSOM=0,
then begin data. In BCP mode: IDLE=0, send SYNCH. IDLE=l
transmit out of TDB. In BOP mode there is also a special
space sequence of 16 zeros initiated by TSOM=land
TEOM=l. Special space sequence is followed by Flag. CRC
generation (if selected) begins when TSOM=~.

6-18

Table 6-11

ESD: Parameter Control Synch/Address Register (PCSAR)
SYNCH/Secondary Address Register Bit Definitions

SYNCH CHARACTER OR
SECONDARY STATION ADDRESS
MA-1050

Bit

Definition

0--3

4--11

Synch character/secondary status address -- in BCP
(byte control protocol) mode, bits 4--11 contain the
Synch character. Bit 11 is the least significant bit.
In BOP (bit oriented protocols) mode, and when
operating in secondary address mode, these bits
contain the desired secondary station address.

6-19

Table 6-12

ESD: Parameter Control Synch/Address Register (PCSAR)
or Mode Control Re9ister Bit Definitions
01

STRIP
SYNC/LOOP
MA·7051

Bits

Definition

0--3

APA (all parities address) -- if selected, modifies
secondary mode so that secondary address of 8 ones
activates the RDP (receive data path).

Protocol -- 0=BOP (bit oriented protocol) -- ADCCP,
X.2S, HDLC, SDLC. l=BCP (byte control protocol) -DDCMP, BISYNC.

Strip/Sync loop -- strip sync or loop mode. Effects
receiver only. In BOP mode allows recognition of a GA
(go ahead) character. In BCP mode, after second Sync,
strip Sync. When first data character detected, set
RXACT=I, stop stripping sync patterns.

SEC ADD (secondary address mode) -- in BOP mode only,
looks for address match prior to activating receiver.
When transmitting, the sec9ndary address must be
loaded into the TDB.

IDLE (Idle mode select) -- affects transmitter only.
In BOP mode, controls type of character sent when TSAB
(transmit abort) asserted or in event of data
underflow. In BCP mode, controls method of initial
Sync character transmission and underflow.

9--11

XYZ* (error control bi ts) -- Z Y X
0 0 0 X16 + X12 + XS + 1 CCITT
0 0 1 X16 + X12 + X5 + 1 CCITT
0 1 0 Not used
0 1 1 X16 + Xl2 + X2 + 1 CRC16

6-20

initialize to "I"
initialize to "0"

Table 6-12

ESD: Parameter Control Synch/Address Register (PCSAR)
or Mode Control Register Bit Definitions (Cont)

Bits

Definition
1 0 0 odd parity, CCP mode only
1 0 1 even parity, CCP mode only
1 1 0 Not used
I I I Inhibit all error detection

* Do not modify XYZ until both transmitter and receiver are idle.

6-21

Table 6-13

ESD: Data Length Select Register (PCSCRr Bit
Definitions
00

EXCON

TXDL1

TXDL3

TXDL2

EXADD

RXDL3

RXDL2
RXDL1
MA-70S2

Bits

Definition

0--3

4--6

TDXL (transmitter data length)
TXDL3

TXDL2

TXDLI

(Bit 4)

(Bit 5)

(Bit 6)

0
1
1
1
1
0
0
0

0
1
1
0
0
1
1
0

0
1
0
1
0
1
0
1

Length
(Bits/Character)
8
7
6

5
4*
3*
2*
1*

EXADD (extended address field)
in receiver only,
LSB of address byte tested for a "1." If no, continue
receiving address bytes, if yes, go into control
field.

EXCON (extended control field)
in receiver only, if
set, receives control field as two a-bit bytes.

6-22

Table 6-13

ESD: Data Length Select Register (PCSCR) Bit
Definitions ( Cont)

Bits

Definition

9--11

RXDL (receiver data 1eng th)
RXDL3

RXDL2

(Bit 9)

(Bit

RXDLI
1~)

(Bit 11)

1
1
1
1

1
1

1
0
1

0
0
0

1
1

0
0

Length
(Bits/Characters)
8
7
6
5
4
3
2
1

* Only use these character lengths in BOP mode operation.
6.5
DP278 lOT INSTRUCTIONS
This section describes the rOT instructions that control the
internal DP278 registers and the rOT instructions that provide
modem control and port status operations.
A 6XY4 instruction performs the following functions (where XY
may be 30, 31, 34, or 35, and not 36):
1.

For a read device, data is received from the device, ORed
with data in the AC, and the result is stored in the AC.

For a write device, the contents of the AC are sent to the
device.

A 6XY6 rOT instruction performs the following functions (where XY
may be 30, 31, 34, or 35, and not 36):
1.

For a read device, data is received from the device and
loaded in the AC.

For a write device, the contents of the AC are sent to the
device; then theAC is cleared.

6.5.1
Internal Register Instructions
The lOT instructions in Table 6-14 control the DP278 internal
reg isters. Before using instructions 6306, 6316, 6346, or 6356,
set the accumulator to the bit assignments in Tables 6-2 through
6-13.

6-23

Table 6-14

DP278 Internal Register lOT Instructions

Mnemonic

Octal
Code

Function

6300
6301
6302
6305
6306

Set port 0 receive flag
Skip on port 0 receive flag and clear it
Clear AC
Load port 0 receive interrupt enable
Read port o comm. device

6310
6311
6312
6315
6316

Set port 0 transmit flag
Skip on port 0 transmit flag and clear it
NOP
Load port o transmit interrupt enable
Write port 0 comm. device

6340
6341
6342
6345
6346

Set port 1 receive flag
Skip on port 1 receive flag and clear it
Clear AC
Load port 1 receive interrupt enable
Read port 1 comm. device

6350
6351
6352
6355
6356

Set port 1 transmit flag
Skip on port 1 transmit flag and clear it
Nap
Load port 1 transmit interrupt enable
Write port 1 comm. device

SPRF0
KPRF0
PRIE0
PRB0
SPTF.0
KPl'F0
PTIE0
PTB0
SPRF1
KPRF1
PRIE1
PRB1
SPTF1
KPTF1
PTIE1
PTB1

6.5.2
Port Control, Port Status, and Modem Register Instructions
The lOT instructions described Table 6-15 are for modem control
and port status operations.
6.6
DOWN-LINE LOADING THE VT278
When the VT278 is equipped with a DP278, programs can be down-line
loaded from a host computer to thOe VT278 by following the
operational procedures for terminal mode I or terminal mode II
operation described in Chapter 3. Programming considerations that
must be made regarding the protocol for transmission and the
format of information to be transmitted is discussed in the
following paragraphs.
NOTE: If the down-line load process has been successful, all
control of the VT278 is turned over to, and becomes the ~lT
responsibility of, the application program which has been loaded.
Digital Equipment Corporation takes no further responsibility for
the control of any modems or telephone equipment connected to the
VT278 at this point.

6-24

Table 6-15

DP278 Port Control, Port Status, and Modem Register
lOT Instructions

Mnemonic

Octal
Code

SMF
KMF
PCR0

6360
6361
6362

Function
Set modem change flag
Skip on modem change flag and clear it
Write Port 0 Control Register (does not
clear AC after transfer)
Before executing this lOT, set AC as
follows:
AC
<0:3>
4
5

6
7
8
9
10
11

Function
Unused
Port 0 terminal timing enable
Port 0 ESD transmitter enable
Port 0 ESD receiver enable
Port 0 request to send
Port 0 terminal ready
Port 0 signalling rate
Port 0 ESD maintenance select
Port 0 device select (0=SCD;
l=ESD)

If bit 11 changes the selected device,
this instruction must be followed by a
6367.
PSR

6363

Read Port X Status Register (where X=0 or
1). Clears AC before transfer. Before
executing this lOT, set AC0 for port 0
(AC0=0) or port 1 (AC0=1). Status bits in
AC, after 6363 instruction is executed
are:
AC
0
1
2
3
4

5
6
7

8
9

Function
Port select (0=port 0, l=port 1)
Unused (AC<l>=0)
Port X ESD transmitter active
(l=true)
Port X ESD receiver active
(l=true)
Port X ESD transmitter buffer
empty (l=true)
Port X SCD transmitter buffer
empty (0=true)
Port X ESD receiver data
available (l=true)
Port X SCD receiver data
available (0=true)
Port X ESD transmitter status
available (l=true)
Port X ESD receiver status
available (l=true)
6-25

Table 6-15

Mnemonic

DP278 Port Control, Port Status, and Modem Register
lOT Instructions (Cant)
Octal
Code

Function
10
11

PMR

6364

Read Port X Modem Register (clears AC
before transfer). Before executing this
lOT, set AC0 for port 0 (AC0=0) or port 1
(AC0=1). Modem register bits read into AC
after executing 6364 are:
AC
0
<1:3>
4
5
6
7
8
9
10
11

MCIE

6365

6366

Function
Port select (0=port 0, l=port 1)
Unused (AC<1:3>=0)
Port X request to send
Port X terminal ready
Port X signalling rate
Port X signal quality
Port X incoming call
Port X receiver ready
Port X data mode
Port X clear to send

Load Modem Control Interrupt Enable before
executing this lOT; set AC as follows:
AC
<0:10>
11

PCR1

Port X device select (0=SCD,
l=ESD)
Port X ESD present* (0=ESD
presen t)

Function
Ignored
Modem control interrupt enable
(l=enabled)

Write Port 1 Control Register (does not
clear AC after transfer).
Before executing this lOT, set AC as
follows:
AC
<0:3>
4

5
6

7
8
9

10
11

Function
Unused
Port 1 terminal timing enable
Port 1 ESD transmitter enable
Port 1 ESD receiver enable
Port 1 request to send
Port 1 terminal ready
Port 1 signalling rate
Port 1 ESD maintenance select
Port 1 device select (0=SCD,
l=ESD)

6-26

Table 6-15

Mnemonic

DP278 Port Control, Port Status, and Modem Register
lOT Instructions (Cont)
Octal
Code

Function
If bit 11 changes the selected device,
this instruction must be followed by a
6367.

RACD

6367+

Reset active communications device. Set
AC0 to selected port before executing this
lOT.
AC0=0 (port 0)
AC0=1 (port 1)
AC<l:ll> unused
Use this rOT whenever the active device in
that port is changed via a 6362 or 6366
instruction.

* If ESD chip is not present in a port, all associated ESD signals
are set to "I."

+ rOT instruction 6367 resets all internal registers in the
associated devices in a port. Therefore, the registers must be
reprogrammed.
6.6.1
Down-Line Loading Protocol
The protocol for down-line loading
steps:

consists

the

following

The host computer sends the sequence ESC L (033 8 114 8 ) to
the VT278. The VT278 could initiate this sequence by
transmi tting a character sequence to the host to cause
the host's transmission of the ESC L sequence.

The DP278 f i rmwa re recogni zes the ESC L sequence
starts execution of its down-line load routine.

The host computer sends characters to the DP278 using the
encoded format described in Paragraph 6.6.2. The encoding
may be done independent of transmission. That is, a host
computer utility may encode application programs, and
store them for future transmission.

The DP278 firmware receives and decodes the characters.

6-27

and

The DP278 sends an ESCape sequence to the host when the
load is completed:
ESC G (033 8 107 8 ) = successful load
ESC B (033 8 102 8 ) = unsuccessful load.

If the down-line load is successful, the VT278 begins
executing the loaded program from location 200 8 in field
0.

6.6.2
Down-Line Load Encoding Format
For the DP278 firmware to recognize the characters sent by the
host, the characters must be encoded by the host before
transmission. The down-line load format is similar to the binary
loader format generated by the PDP-8 assembler. Transmission must
include the following information codes in the order shown:
Leader
Or ig in
Data
Checksum
Trailer.
The principal difference between the binary and down-line load
formats is that character information is only included in the four
least significant bits of the down-line load 8-bit byte. In
add i t ion, bit s 1 and 2 mu s t a l wa ys be d iff ere n t • Th e r e s ul t i s
that transmitted characters are always in the range 40 8 to 137 8 ,
which excludes control codes.
Tables 6-16 and 6-17 summarize the differences between the two
formats and describe the bit definitions required to identify each
type of information transmitted. Notice that origin, data, and
checksum each require three consecutive bytes for down-line load
transmission, compared to only two for the binary loader.
Table 6-16

Comparison of Binary and Down-Line Load Formats
Binary Loader
Bit 01 234 567

Down-Line Load*
Bit 01 234 567

Header-trailer

10 000 000

X0 100 000

Field

11 FFF 000

X0 11F FF0

Or ig in

01 JKL MNP
00 RST UVW

Xl 01J KLM
Xl 00N PRS
Xl 00T UVW

Data/checksum

00 JKL MNP
00 RST UVW

Xl 00J KLM
Xl 00N PRS
Xl 00T UVW

Binary Type

* Bits 1 and 2 are always different from each other.

6-28

Table 6-17

Binary and Down-Line Load Bit Definitions

Information
Code Type

Binary Loader
Bits
and 1

Down-Line Load
Bits 2 and 3

Leader/trailer

Bit 0=1
1=0

Bit 2=1
3=0

Origin

0=0
1=1

2=0
3=1

Data

0=0
1=0

2=0
3=0

Field

0=1
1=1

2=1
3=1

6.6.2.1 Leader/Trailer -- When the firmware detects bit 2=1 and
bit 3=0, this byte is interpreted as the leader or trailer code.
The down-line load transmission must begin with a leader code and
end with a trailer code. When the DP278 firmware detects the
trailer code, it expects the previously constructed 12-bit word to
be the checksum.
For example:
Bits 01 234 567
00 100 000

(transmitted byte)

results in the firmware interpreting this byte as "either leader or
trailer.
6.6.2.2 Or Igin -- When the fi rmware recogni zes bi t 2=0 and bi t
3=1, bits 4--7 of this byte and bits 4--7 of the next two bytes
are interpreted as the origin. The firmware constructs these bits
into a 12-bit word and loads the succeeding data words into
consecutive addresses starting from the defined origin.
The DP278 firmware requires that all down-line loaded programs
must start execution at location 200 8 , field 0. However, portions
of the program may be located in other memory fields. Succeeding
field and origin information will instruct the firmware to load
the data that follows into newly specified fields starting from
the indicated address.
For example:
Bits 01
01
01
01

234
010
001
000

567
000
000
000

(3 consecutive transmitted bytes)

results in address octal 200 used as an origin address.
6-29

6.6.2.3 Field
The firmware is initialized to start the
down-l ine loaded program at field 0, address 200 8 • However, the
down-line loaded program may include additional fleld and origin
information, as discussed in Paragraph 6.6.2.2. When the firmware
recognizes bit 2=1 and bit 3=1, it interprets bits 4--6 as the new
field address. The current page address is unaffected.
For example:
Bits 01 234 567
00 110 110

(transmitted byte)

results in the current field address being set to field 3.
6.6.2.4 Data/Checksum -- When the firmware detects bit 2=0 and
bi t 3=0, bi ts 4--7 of this byte and bi ts 4--7 of the next two
bytes are interpreted as data. The firmware constructs a l2-bit
word and stores the word in the next memory location of the
current field. Bits 4--7 of the first byte are the most
signi ficant four bi ts, and bi ts 4--7 of the thi rd byte are the
least significant four bits.
For example:
Bits 01
01
01
01

234
001
001
001

567
III
110
110

(3 consecutive transmitted bytes)

results in 7756 8 being stored at the current field/page address.
If the next word constructed by the firmware is the trailer code,
this data word is interpreted as the checksum. The checksum is
computed by summing bits 4--7 in all transmitted bytes except for
leader/trailer and field bytes. The carry beyond 12 bits is
ignored.

6-30

CHAPTER 7
PROGRAMMING THE RL278

7.1
INTRODUCTION
This chapter describes the RL278 disk controller registers and
commands and the instruction set used to start the transfer of
data to and from an RL02 disk drive.

The flowchart in Figure 7-1 shows the basic sequence of events
that occur during execution of all controller commands. After the
necessary ·reg isters are loaded, the command is decoded and the
function control is started. Controller logic and error bits are
cleared. The command function to be performed is then executed.

INTERRUPT ENA (0)

INTERRUPT ENA (1)

MA.7054

Figure 7-1

Basic Controller Operation Flowchart

7-1

When the command function is completed, the done flag and the
interrupt enable are checked. If the interrupt is not enabled, a
skip function is generated by setting the done flag and the
command is terminated. If the interrupt is enabled, it causes the
CPU to jump (JMS) to location 0 into an interrupt service routine
request before command termination.
To issue a function command, the CPU places the address and data
onto the DX bus and the controller decodes the information and
channels it to the a'ppropriate register. After the desired
function command is written into command register B, it starts the
m~crosequencer
routine. The microsequencer control performs a
different routine for each of the controller command functions.
These routines manipulate the data formatting circuits to format
the data. Included in the data formatting function is an error
detection feature that uses cyclic redundancy checking (CRC).
Before reading or writing data, the drive heads must be positioned
properly on the disk. Th i s i s done by first executing a read
header command to determine where the heads are located and if the
upper or lower head has been selected. If positioned at the
desired track address, the read/write command can be executed
directly. Otherwise, a software calculation must be performed to
determine the cylinder distance the heads must move to the new
location. This cylinder-distance information is then transmitted
to the selected drive via a seek command.
7.2
RL278 INSTRUCTION SET
Input/output transfer (lOT) instructions are used to start disk
drive(s) operation and to transfer data. Figure 7-2 shows the lOT
instruction format. Bits 0--2 contain the opcode, which must be a
6 to specify an lOT instruction. Bits 3--8 contain the device
selection code and bits 8--11 contain the function code. The
instructions are loaded onto the DX bus and decoded by the RL278
controller. Transfers from the AC to the controller clear the AC
after the transfer is complete. Transfers to the AC from the
controller clear the AC first and then the transfer takes place.
The skip instructions in the RL278 instruction set perform the
skip and then clear the flag. This means that if a given flag is
true, it will be cleared upon completion of the skip lOT. Table
7-1 lists and defines the instruction set for the RL278.

I I.I I I
1

OP CODE

.I I

F~NCT+N CO~E

DEVICE SELECTION

MA-0869

Figure 7-2

RL278 Instruction Set Format

7-2

Table 7-1

RL278 Instruction Set

Octal Code

Mnemonic

Function

6600

RLDC

Clear controller, all registers, AC and
flags. (Do not use to terminate a disk
function. )

6601

RLSD

Skip on function done. Then clear if set
to a one.

6602

RLMA

Load break MA register from AC(0:11>

6603

RLCA

Load command register A from AC(0:11>

6604

RLCB

Load command register B from AC(0:11>,
execute command

6605

RLSA

Load sector address from AC(0:5>

6606

Spare (will clear the AC)

6607

RLWC

Load word count from AC(0:11>

6610

RRER

Read error register into AC(0:2, 10:11>

6611

RRWC

Read word count into AC(0:11>

6612

RRCA

Read command register A into AC(0:11>

6613

RRCB

Read command register B .into AC(0:11>

6614

RRSA

Read sector address into AC(0:5>

6615

RRSI

Read silo word (8-bit)

6616

into AC(4:11>

Spare (does not clear AC)

6617

RLSE

Skip on composite error, then clear if
set to a one.

7.3
ADDRESSABLE REGISTERS
The RL278 has six addressable registers that allow the CPU to
communicate with the controller using lOT commands in the form of
6XXX (Table 7-1). The instructions control and monitor the
controller and do not transfer data. These addressable registers
are explained in more detail as follows.
1.

Command register A
contains the desired cylinder
address (or difference for a seek) from which data is to
be transferred, for head selection, and for a read
command.

7-3

Command register B -- contains the function and format
control for the mode
(8- or l2-bit), drive select,
interrupt enable, extended memory bits, and the desired
function to be performed for a seek cylinder difference,
head selection, and difference commands.

Break memory address -contains
the
first
location to/from which data will be transferred.

memory

Sector address register -- contains the
of the first sector to be transferred.

address

Word count register
contains the number of data words
to be transferred to either memory or the disk.

Err 0 r reg is t e r - - con t a ins
different error conditions.

the

desired

in d i cat ion s

for

f i ve

7.3.1
Command Register A
Command register A is a 12-bit addressable register that contains
the cylinder address difference, head select, and direction for
seek functions (Table 7-2). Th i s reg iste r is also used dur ing
read/wri te operations (holds CYL ADD and HD SEL) when searching
for the correct disk address.
7.3.2
Command Register B
Command register B is a l2-bit addressable register that contains
the mode, dr i ve number, interrupt· enable, and the function code
(Table 7-3).
Silo Buffer After Get Status
7.3.3
When a get status command is executed, the disk dr i ve returns a
status word to the controller. The contents of the silo buffer is
divided into two words: word 1 and word 2 messages (Table 7-4).
The fault LED on the drive(s) will be asserted if any bit is set
in word 2.

7-4

Table 7-2

Command Register A Bit Definitions
00

DIRECTION
0= FORWARD
1 = REVERSE

SPARE

HEAD SELECT
0= UPPER
1 = LOWER
MA-0875A

Bit

Name

Function

AC0

Direction (DIR)

Indicates the direction in which
a seek is to take place. When
the bit is set, the heads move
toward the spindle (to a higher
cylinder address). When the bit
is cleared, the heads move away
from the spindle (to a lower
cylinder address). The actual
distance moved depends on the
cylinder address difference
(bi ts 3--11).

ACl

Head Select (HS)

Indicates which head (disk
surface) is to be selected:
set=lower (HD 1); clear=upper
(HD0) •
Spare

AC2
AC<3:11>

Cylinder address
difference DF<3:11>

Indicates number of cylinders
heads are to move on a seek and
a read/write operation. Range is
0000--0777
(0--511 10 ).
8

7-5

Table 7-3

Command Register B Bit Definitions
00

RESERVED

MODE
0= 12 BIT
1 = 8 BIT

FUNCTION
-BIT C

MAINTENANCE
DAR TO SILO

FUNCTION
BIT A

FUNCTION
BIT B
INTERRUPT
ENABLE
MA-0873

Bit

Name

AC0
ACI

Function
Reserved, normally cleared

Maintenance

Reads disk address register
(DAR) and loads into silo for
maintenance purposes. Bits 1 and
2 of command register B must be
set to 1 for function to work
correctly.
DAR is loaded by using rOT RLCA
to load command register A (for
cylinder address portion) and
RLCB to load the function along
with the loopback bit (1) and
the mode bit (2). When the
function done flag sets to a 1,
the silo should be read twice to
yield two 8-bit words which are
the DAR. The first word has the
following content. (AC<0:3> are
undefined for both words.)
AC04
AC05
AC06
AC07
AC08
AC09
AC10
AC11

Cylinder add.
Head select

(LSB)

o
Head select for seek
1 for reset, otherwise 0
Direction bit
1 for get status,
otherwise 0
Marker bit (always 1)

The second word has the following
content:
AC04
AC05
AC06
AC07
7-6

Cylinder
Cylinder
Cylinder
Cylinder

add.
add.
add.
add.

(MSB, RL02)
(MSB, RL0l)

Table 7-3

Command Register B Bit Definitions (Cont)

Bit

Name

Function
AC08
AC09
AC10
AC11

Cylinder
Cylinder
Cylinder
Cylinder

add.
add.
add.
add.

AC2

Mode

When set, indicates that data
field will be 256 8-bit words
per sector. When 0, data field
will be truncated to 170 12-bit
words per sector (12-bit mode).
T~e OS/8 operating system limits
it to 128. This bit must be set
when a get status or read header
command is to be executed.

AC3

Interrupt enable

When this bit is set, controller
is allowed to interrupt
processor at end of normal
command or error termination.

(I E)

AC<4:S>

Drive select

Determines which drive will
communicate with controller via
drive bus.

AC<6:8>

Extended memory
address (EMA)

Defines memory field location.
Allows 32,768 locations to be
addressed for processors having
more than 4K of ·memory.

AC<9:11>

Function code

Indicates command to be executed
by controller/disk subsystem.
Bits

"oo

1
1

0
0

1
1

7-7

o
o
o

Command
Maintenance
Reset
Get status
Seek
Read header
Write data
Read data
Read data w/o
header check

Table 7-4

Silo Buffer Bit Definitions
00

WORD1

0= RL01
1 = RL02

COVER
OPEN

HEAD
SELECT

BRUSH
HOME

HEADS
OUT

STATE B

STATE C

STATE A

Word No. 1
Bit

Function

Name

Undefined

AC(0:3>
AC4

Drive identification

0=RL01; 1=RL02

AC5

Head select (HS)

Indicates currently selected
head.

AC6

Cover open (CO)

Asserted when top cover is open
or dust cover not in place.

AC7

Heads out (HO)

Asserted when heads are over
disk. Cleared when heads
retract.

AC8

Brush home (BH)

Asserted when brushes retract.

AC(9:11>

State bits

Defines state of disk drive.
Bits
10
9
0
0
0
0
1
0
1
1
0

7-8

11
0
1

0
1
0

1
1

0
1

Definition
Load state
Spin-up
Load heads
Brush cycle
Seek-track
counting
Seek linear
mode
Unload heads
Spin-down

Table 7-4

Silo Buffer Bit Definitions (Cant)
00

·05

WORD2

WRITE
DATA
ERROR

WRITE
LOCK
STATUS

CURRENT
HEAD
ERROR

SPIN-UP
TIMEOUT
ERROR

SEEK
TIMEOUT
ERROR

VOL,UME
CHECK

WRITE
GATE
ERROR

DRIVE
SELECT
ERROR
MA-OB76A

Word No. 2
Bit

Function

Name

Undefined

AC<0:3>
AC4

Write data error
(WOE)

When asserted indicates that
write gate was on but no
transitions were detected on
write data line.

AC5

Current head error
(CHE)

Write current was detected in
heads when write gate was not
asserted.

AC6

Write lock (WL)

Write lock status of selected
drive.

AC7

Seek time out
error (SKTO)

Heads did not come on track
within approximately 3 seconds
during a seek operation or
ready to R/W was lost in
"lock-on" or position mode.

AC8

Spin error (SPE)

Spindle not obtaining
up-to-speed in 40 seconds or
spindle in overspeed (sector
pulses less than 593 us apart).

AC9

Write gate error

Drive sensed write gate
asserted during sector pulse
time, drive write locked, or
drive not ready, or drive has
another WDE error.

AC10

Volume check (VC)

Signals that new volume (media)
has been inserted into drive or
power has been cycled down then
up on drive.

ACll

Drive select error
(DSE)

One or more drives has same
number.

7-9

7.3.4
Silo Data Buffer After a Read Header
When a read header command is executed, six words are stored in
the silo. The first header word contains sector address, head
select, and cylinder address bit 0 (LSB) information (Figure 7-3).
The second word contains the remaining bits of the cylinder
address. Words 3 and 4 contain 0s and words 5 and 6 contain header
eRe information. All six words can be extracted by the program
using RRSl lOT.

WORD1

HEAD SELECT

WORD2

. ~~~

: UND+INED:

~~~ ,

CYLINDER ADDRESS

00
WORD 31

:UND+INED:

WORD

:UND+NED:

00
WORD 51

0
1

I I I I I I I

I I

: UND+INED:

0
1

MSB

1 LSB

I
,

HEADER CRC (7-0)

00
WORD6

01
:

UNDE~INED:

1 MSB 1

11
1 LSB 1
,

HEADER CRC (15-8)
MA-0877A

F'igure 7-3

Header Words Format

7-10

7.3.5
Word Count Register
When reading or writing data, ·the word count is loaded with the
2' s complement of the number of words to be transferred, and is
then incremented by 1 as each word is transferred. Reading or
writing terminates when the word count register overflows. The
register can be read back into AC<0:ll> with the RRWC instruction
(lOT 6611).
The 12-bi t word count reg ister allows up to 4096 data breaks
(DMAs) to take place at one time. This register is loaded with the
RLWC instruction (lOT 6607)
from AC<0:l1> which is the 2's
complement of the number of transfers specified.
7.3.6
Break MA Register
The break MA reg ister (Figure 7-4) contains the starting memory
address for word transfers between the controller and memory. BRK
MA is loaded by RLMA (lOT 6602) and cleared by an initialize or by
loading the register with zeros. The contents of BRK MA are
automatically incremented as each word is transferred between the
controller and memory.
7.3.7
Sector Address Register
The sector address register (Figure 7-5) is loaded by the RLSA
(lOT 6605) instruction and read by RRSA (lOT 6614). It contains
the sector address of the first sector to be transferred. Before
executing a read or write operation, the AC<0:5> bits are loaded
into the sector address register. The register can be read back
into AC<0:l1> with the RRSA instruction (lOT 6614).
7.3.8
Error Register
The error register (Table 7-5) is read by the RRER (lOT 6610)
instruction. The error register can be read at anytime for error
status.

I I

I. I

LSB

MSB

BREAK MEMORY ADDRESS
MA-3041

Break MA Register

Figure 7-4

I I

I. I

LSB

MSB

: NOT

~SED

SECTOR ADDRESS
MA-3042

Figure 7-5

Sector Address Reg ister

7-11

Table 7-5

Error Register Bit Definitions
00

DR ERR
MA·3043

Bit

Name

Function

AC0

Data CRC (DCRC) or
header CRC (HCRC)

If opr (01) is cleared and bit
00 is set, CRC error occurred
i n d a t a ( DC RC). r fOP r ( 01 ) i s
set and bit 00 is also set, CRC
error occurred in header
(HCRC) •

ACl

Operation incomplete
(OPI)

When set, indicates that
current command was not
completed within 200 ms.

AC2

Data late (DLT) or
header not found
(HNF)

When opr (bit 01) is clear and
bit 02 is set, indicates that
during a write operation silo
was empty. Therefore, a word
was not available for writing.
Also indicates that during a
read operation silo was full
and unable to store another
word from drive.
When opr (bit 01) is set and
bit 02 is also set, indicates
that a 200 ms timeout occurred
while controller was searching
for correct sector to read or
write (no header compare).
Bits
Error
DLT
OPI
HNF
DCRC
HCRC

AC10

Dr i v'e error (DE)

90
0
0

01
0
1
1

02
1

" " ""
"

1
1

This bit is tied directly to DE
interface line. When set,
indicates that selected drive
has flagged an error. Error can
be determined by executing a
get status command.

7-12

Table 7-5

Error Register Bit Definitions (Cont)

Bit

Name

Function
DE is cleared by issuing a
reset command to drive.

ACll

When set, indicates that
selected drive is ready to
receive a command. Bit is
cleared when seek operation is
initiated and set when seek
operation is completed.

Drive ready (DRDY)

7.4
COMMAND EXECUTION
There are eight controller commands embedded in command register B
(bits 9--11). Three of these commands are used for initialization
and test purposes; the remaining commands control head positioning
and the actual transfer of header information and read/write data
between the controller and the disk drive(s).
Bits
9

Command
Maintenance
Reset
Get status
Seek
Read header
Write data
Read data
Read data
(without header check)

0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

7.4.1
Maintenance Command
The maintenance command exercises the controller logic to be sure
that it is operating properly (Figure 7-6). This command tests
that the command registers, silo, and data paths can function
correctly without the disk drive connected.
'To execute the maintenance command, program the following steps:
1.

Set the AC<0: 11> to -4
(7774 8 ). Then execute the RLWC
10
instruction (lOT 6607) to load ~he word count register.

Set AC<0: 11> to the break address. Then execute an RLMA
instruction (lOT 6602) to load the break MA register.

Set AC<0:1l> according to Paragraph 7.3.2 to provide
maintenance mode (AC2=1) along with your choice of drive
select (AC<4:5»
and the EMA field
(AC<6:8». Set
AC<9: 11>=0 fo r the maintenance command. Then execute an
RLCB instruction (lOT 6604) to load command register B
from AC<0:11> and perform the maintenance command.
7-13

• SET UP FOR MAINT
CMD
• LD BREAK MA REG.
• LD WC REG TO -4
• LD CMD B REG
(SET FOR 8-BIT
MODE)

ERROR

YES

SET
BREAK RQST
FOR WRITING
AND READING

READ (VIA DMA) THE .
ONE 8 - BIT WORD
AND THE 2 (8 - BIT) .
CRC WORDS TO MEM.

CONTROLLER WILL
(VIA DMA)
WRITE 1(8-BIT)
WORD FROM
MEMORY
TO SILO PLUS 2(8-BIT)
CRC WORDS ADDED

MA-1429

Figure 7-6

Maintenance Command, Operational Sequence

When the maintenance command is decoded the following happens:
1.

One DMA takes place out of memory at the location
specified by the break MA. A write data function is then
executed out of the silo.

The written data is loaded back into the silo along with
two 8-bit words which are the eRe character.

3.
4.

DMAs take place causing the data (8-bit) word and the two

eRe words to be written into memory.

This sequence is repeated until word count overflow. At
this time a function done interrupt occurs. A eRe error
and· function done immedi ately raises an inter rupt if a
eRe error occurs.
7-14

7.4.2
Reset Command
Wh e n res e t i s ex e cut ed, all err 0 r bit s i n th e d r i ve are res e t •
This command does not c lear any reg i ste rs in the controller nor
does it cause the heads to move to track 0.
NOTE: The sector address and command register A must be cleared
before executlng thls command.
Get Status Command
7.4.3
By executing a get status command, it is possible to read the
status and errors of the disk drive. The command also causes any
er rors present to be cleared. When this command is decoded, the
drive sends the drive status word to the controller. When the
function done interrupt occurs the status words can then be read
from the silo into the accumulator by executing two RRsr rOTs.
NOTES: The sector address and command register A must be cleared
before executing this command.
The mode bit (command register bit 2) must be set when loading the
get status command into command register B.

7.4.4
Seek Command
A seek command involves two basic operations:
1.

Software calculating head selection, cylinder difference,
and positioning direction

Transmitting this information from the controller to the
drive to initiate a seek.

The seek function must be specified and a difference word must be
loaded into command register A to enable this function. A function
done interrupt occurs when the seek command and difference word
have been sent to the disk. If the difference word attempts to
move the head past the innermost track 255, RL0l or 511, RL02 or
the outermost track (0) limits, the head stops on the track limit.
NOTE: The sector address register must be cleared before executing
this command. This command must be issued before a read or wrlte
unless they are already properly positioned.
7.4.5
Read Header Command
The read header command reads the first header encountered on the
selected drive and stores the header information (two header words
and one header CRC word) in the silo. The header words can then be
extracted from the silo by reading the silo with two RRSI lOTs to
determine the present head posi tion. There are six words loaded
into the silo on a read header command:
Words 1 and 2=present position
Words 3 and 4=0s
Words 5 and 6=CRC information.

7-15

When this command is decoded the controller reads the first header
encountered on the disk. 'rhe function done interrupt sets,
indicating that the header words may now be read into the AC.
These words (address) can be used to determine current head
position or to calculate a different word to reposition the heads.
The header CRC is also loaded into the controller behind the
header words so that reads 5 and 6 of the silo yield these words
for diagnostic purposes.
7.4.6
Write Data Command
This is a DMA command that transfers parallel data from main
memory into the silo and shifts out the data in serial form to the
disk drive. Prior to executing the command, it is necessary to set
up the following registers:

Break MA reg ister
data is obtained

Sector address register
sector to be transferred

Word count register
number of data
written, entered in 2's complement form

Command register A
desired cylinder address and head
select from which data is to be transferred

Command register
function (write).

first

memory

location

desired

mode,

address

interrupt,

from

which

first

words

device,

EMA

DMA transfers are continuous until word count overflows. Serial
write data is continuous until the silo is emptied. At that point,
the command is terminated.
Multiple sector write on one track is executed if the word count
is greater than one sector. For a partial sector write, the
remaining sector area is zero-filled.
Mul tiple sector transfers in 12-bi t mode, either read or wr i te,
should not be attempted because of the odd length (8 bits)
remaining at the end of a given sector. In 8-bit mode, 16 multiple
sectors can be transferred.
When this command is decoded the controller begins reading
successive header words and comparing them to the sector address
register and command register A which contains the cylinder
address. When a match is found, the header CRC is checked and if
correc,t, that sector is written with the data starting at the
address designated by the break MA register. When writing a
partial sector the remainder of the sector is wr i tten wi th 0s.
When the word count overflows, an interrupt request from function
done indicates that the command is complete.

7-16

7.4.7
Read Data Command
This is a DMA command that transfers serial data from the disk
drive into the silo and shifts out the data in parallel form to
main memory. Before executing the command, it is necessary to set
up the following registers:
1.

Break MA register
is transferred

Sector address register
sector to be transferred

Word count register -- number of data words to be read,
entered in 2's complement form

Command register A -- desired cylinder address from which
data is to be transferred

Command register
function (read).

first memory location to which data
desired

B -- mode,

address

interrupt,

device,

first

EMA

DMA transfers are continuous until the word counter overflows.
Serial read data is continuous until the DMA is done. At that
point, the command is terminated.
When this command is decoded the controller begins reading
successive header words and comparing them with the sector address
register and command register A which contains the cylinder
address and head select information.
When a match is found, the header CRC is checked and if correct,
that sector is read. The data being read is placed into memory
beg inni ng at the address spec i f ied by the break MA reg iste r. A
function done interrupt, set at word count overflow time,
indicates that the transfer is complete.
If a data CRC error occurs, the CRC error flag and function done
flag are both set at the completion of the transfer.
7.4.8
Read Data Without Header Check Command
When this function is decoded the controller reads the data
portion of the sector following the next sector pulse. This data
is read into the silo and then into memory (on second sector
pulse) starting at the location specified by the break MA
register. The header is neither compared nor checked for CRC
errors. Data CRC is checked and the sector address (SA) is
incremented. If the word count has not overflowed, the next sector
i s rea d , ag a in wi tho u t c h e c kin g the head e r 0 r he ad e r CRC • Wh e n
word count does overflow, a function done interrupt occurs.
7.4.8.1 Track Overrun -- If word count overflow has not taken
place before the end of the track has been reached, the sector
address register is incremented to 50 8 , an illegal sector number,
causing an operation incomplete (OPI) time-out error. The sector
address register then can be read showing the illegal address.
7-17

APPENDIX A
ASCII CHARACTER SETS

The ASCII character sets in this appendix contain the display
codes that correspond to each of the six possible display
languages. The initial display language, when the VT278 is turned
on, is set at the factory. You can change the display language by
issuing an SCS ESCape sequence as described in Chapter 5. Unless
your VT278 system contains the foreign language support option,
only the US and UK display languages are available.
Some of the characters in the foreign language character sets are
actually graphic characters whose patterns are automatically
retrieved from the alternate character ROM (Appendix D)
for
display. The display codes for the alternate character ROM also
can be directly accessed if the alternate character ROM is
assigned as one of the two alternate character sets defined by an
SCS ESCape sequence.
ASCII octal codes 000 through 037 in each language do not produce
display characters. However, octal codes 001 through 037 can be
generated from the keyboard by pressing the appropr iate control
character.
For example, pressing and holding the CTRL key
followed by pressing the S key (is) generates octal 023 (DC3).

A-I

ASCII Code
Octal Decimal U.S.

Dutch French

Language
French
Canadian

000
001
002
003
004
005
006
007

0
1
2
3
4
5
6
7

tA
tB
tc
tD
tE
tF
tG

NULL
SOH
STX
ETX
EaT
ENO
ACK
BEL

010
011
012
013
014
015
016
017

8
9
10
11
12
13
14
15

tH
tl
tJ
tK
tL
tM
tN
to

BS
HT
LF
VT
FF
CR
SO
SI

020
021
022
023
024
025
026
027

16
17
18
19
20
21
22
23

tP
to
tR
ts
tT
tu
tv
tw

DLE
DC1
DC2
DC3
DC4
NAK
SVN
ETB

030
031
032
033
034
035
036
037

24
25
26
27
28
29
30
31

tx
ty
tz
t[
t\
t]
t ...
t/

tx
tv
tz
tij
t<

tx
tv
tz
te
tjl
t'

tx
tv
tz
te

tx
tv
tz
ta
to
til

tx
tv
tz
t[
t\
t]
t...
t/

CAN
EM
SUB
ESC
FS
GS
RS
US

t'"

German U.K.

Meaning

MA-9084

A-2

ASCII Code

Language
French
Canadian

German U.K.

space space space

space

"
#
$

"
£
$

"
#
$

"
£
$

%
&

%
&
,

%
&

%
&
,

%
&

(
)

Octal

Decimal U.S.

040
041
042
043
044
045
046
047

32
33
34
35
36
37
38
39

050
051
052
053
054
055
056
057

40
41
42
43
44
45
46
47

060
061
062
063
064
065
066
067
070
071
072
073
074
075
076
077

Dutch French

space

48
49
50
51
52
53
54
55

0
1
2
3
4
5
6
7

2
3
4
5
6
7

0
1
2
3
4
5
6
7

56
57
58
59
60
61
62
63

8
9

MA·9085

A-3

ASCII Code

Language

Octal

Decimal

U.S.

100
101
102
103
104
105
106
107

64
65
66
67
68
69
70
71

3/4

A
B

C
D

110
111
112
113
114
115
116
117

72
73
74
75
76
77
78
79

120
121
122
123
124
125
126
127

80
81
82
83
84
85
86
87

130
131
132
133
134
135
136
137

88
89
90
91
92
93
94
95

French
Canadian

German

U.K.

A
B

C
D

Dutch French

F
G

K
L
M
N

U
V

Z
[

Z
ij

y
Z

1/2
I

A
0

y
Z
[

]
1\

\
]
1\

MA-9086

A-4

ASCII Code

Language

Octal

Decimal

U.S.

Dutch French

140
141
142
143
144
145
146
147

96
97
98
99
100
101
102
103

150
151
152
153
154
155
156
157

104
105
106
107
108
109
110
111

160
161
162
163
164
165
166
167

112
113
114
115
116
117
118
119

170
171
172
173
174
175
176
177

120
121
122
123
124
125
126
127

a
b
c
d
e
f
9

French
Canadian

German

U.K.

.......

a
b
c
d
e
f
9

h
i
j
k
I

a
b
c
d
e
f
9

h
i
j
k
I
m
n

p
q
r

q
r

t
u

v
w

z..

""e

""
e
"u
...
e

{
I

}
~

DEL

1/4

"
DEL

u"-

e..
DEL

DEL

{

u
{3
DEL

DEL
MA-9087

A-5

APPENDIX B
ENGLISH AND FOREIGN LANGUAGE KEYBOARDS

The
VT278
keyboards
for
the
English,
Dutch,
French,
French-Canadian and German languages are shown in Figures 8-1
through B-S, respectively.

B-1

ttl
I
N

MA-6012

Figure 8-1

--.

English Keyboard

ttJ
I

MA-6013

Figure 8-2

Dutch Keyboard

tJj

I
~

MA-6015

Figure 8-3

...........

French Keyboard

tJj

I
(Jl

MA-6014

Figure B-4

French-Canadian Keyboard

tx1
I

0'\

MA-6011

Figure 8-5

German Keyboard

APPENDIX C
SPECIAL GRAPHICS

You can assign the special graphics character set as one of the
two alternate character sets by executing an SCS (select character
set) ESCape sequence as defined in Chapter 5. The special graphics
characters are shown in Figure C-l.

C-l

DISPLAY CODE (OCTAL)

137

.-.•...•..•... ...... .•. ••••••••• .••••••••• ..
.•••.....
..
•. .•... ...••••••••• .••....... ........ . ••••••••••
...
.........
...
.
.......
.
........
.•.•.....
• ••••••••• .•...•...
•••••••••
.•.
.•••.....
•••••••••
.•. .. .. .•..
........ . .•..
•••••••••
'., •••••••••
142

140

141

.. .•......
·
••••••••• .•
..
·
.. _ ....

.•....
.•....
'
.•.....
~

- ...

........ .

.•..... •........ .•

.•.....•
.•.....
....•.....
... .•.....
... .•.....
•

........ .• ........ .
•........ . •........ .
........ . .
·
.. .•...... ·
· .•.......
.
•
.. .•...... ·•
.. · .•.......
.. .•...... · .•...•... · .•.......
•

...
.•..... ...
..••.....
...
.
.•...•.•..... ......... ............
.. .••..... •.•......
........
.
....
•••••••••
146

150

147

.•...•.... .. .•..... .•.... .. - •......

.•.....
.
.
.•.....
.. .•......
..•...... · - •.......
••••••••• • ·· .•.......
•.......

152

151

.•.....

...•.....
.
· .•.......

...•......
. ..•......
. ..•......
. ..•......
..

.• ...•.....
... .•.....
... .•.....

••••••••• ... .•.....
156
160
157
155
••••••••••
.. .•...... .. .•......

...

........ .

·
. ..•......
. ..•......
. ..•......
· ..•......
.. .•...... . ..•......

.. .
.... .
. ..•......
. ..•......
. ..•......
"

162

161

......... . ••••••••••

.........

154

153

•

.. .•...... .. .•......
.. .•...... .. - •......
.
•• ••••••••
.. .•......
.. .•......
.. .•......
· - ... _.

145~

144

143

••••••••••

..•......

163

......... .
172

164
170
165
166
171
167
...•......
.. .•......
.. .•......
, ..•......
. ..•...... . .....•... •........ .
.. .•...... .. .•..... . .. .•......
.. .•...... .. .•...... .. .•......
.. .•...... . ...•..... · .•.......
.. .•...... .. .•...... . ..•......
.. .•...... . .•....... ... .•.....
.. .•...... ........ . . .....•...
.
•••••••• •••••••••
•••••••••
.. .•......
.. .•......
.. .•...... . ..•...... . .•....... . ...•.....
.. .•...... . ..•......
.. .•...... . ..•...... ... .•..... · .•.......
.. .•...... .. .•......
.. .•...... .. .•...... . .....•... ........ .
.. .•...... .. .•......
. ..•...... .. .•......
. ..•...... . ..•...... •••••••••• •••••••••
.. .•...... .. .•......
••

•

.........

•

...•....
..........
..........
..........
...
•....•....
.•.....
..............
.••...
173

174

...... .... ..... .•...
.......... .... .•....
· .•.... .. .•......
· .•....
· .•.... .•........
.•.... •.........

175

176

..
. .•.......
. .•.......
. .•.......

. ........ .
. ........ .
. ........ .
. ..•......
. ........ .
. ........ .
. ........ .
.......... .......... .•........ . ........ .
MA-6016

Figure C-l

Special Graphics

C-2

APPENDIX D
ALTERNATE CHARACTER ROM, STANDARD GRAPHICS

You can assign th i s character set as one of the two ava i lable
character sets by executing an SCS (select character set) ESCape
sequence as defined in Chapter 5. The standard graphics characters
in the alternate character ROM are shown in Figure D-1.

D-1

040

041

DISPLAY CODE (OCTAL)

....
. ...•.....
....
..... .

..••....
......... .. .•.

045
046--..J
..................................................•••••.........••....
.......... .......... •.... .•... ..
.. .•......
.•.... . ..•..•...
.. .•......
.•.... · .•...•... ••••••••• • •••••••••• . ..•......
.•...... ........ . . ..•......
· .•.•..... · .•.......
.•...... .. .•......
. ••••••••• • •••• •••••• .
. ..•......
· .•....... .. .•...
•••••••••
•••••••••
..
.•......• ..
.•...... ••••••••• ••••••••• • •••••••••
.•.... . ..•......
.•... ..•......
•••••••••
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.. .•......• ••••
.•.......
• ••••••••• . ••.......

.......... .•..

042

043

•

044

•

........ . ••••••••• ... .•... ......•......
.•...
..
...•....
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•..•....
...
..
.•.•....
.•.......
.•.
.•...
.•..••••••••• •••••••••
..
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.•.•....
•.
.•..•....
.•.
•.... .•...
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••••••••• •••••••••
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.
.....
....
.....
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.
.•...•...
•••••••••
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....
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...
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.......
.
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......... .....•••••....•. .•...
.....
...
.
•••••
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........
.
.........•.... .•.. ••........
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.•... •• •••••••• ...
....
•••••••• •••••••••
••••••••••

051

050

047

.•...
.•....... .
·
.•....
..
.... .•.... ..
.•.... ..

•

057

056

•

•••••

•

.•.....

060
.•........
.•....
.•..... .
·
·

066

........
.•.•.....
•••••••••
....
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•••••••••
....

. ..•......

. ..•......
. ..•...... . ..•......
. ..•......
.
. ..•......•
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•

•

061

062
064
... . •........
. 063
.
. ·
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.•....
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.•....... . . ..•......
·
_

•••••

·
.•.... .

.•.....

••

070

067

055

054

. ..•......
. ..•......
.•..... ·
. ..•......
.•...... ..
.. .•......
.•..... ·
.•..... .. .•......
·
..•...... .. .•......
..
..
·

.....

065

053

052

.....

•

....
.. ..•......
072

071

...•...... •.... ...•... ·
.....•... ·
.....•...
.. .•...... .....•...
.. .•...... •.... .•...
. •........ .. .•...... . ..•..•... ·

•.... .•...

..
..... .•...
· ....•....
•
..
.•......
· .•.......

.. .•......
.. .•......
. ..•......
. ..•......

...

073

. ...••....

. ..•......

.••......
•.... .•...
......
..•......
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..........
. ...••.... .••...... .
· .•••..... .•.. .•....
.....•...
.•...•.•.....
.•....
· ..•...... .. .•...... . ..•...... .•••••••••
•...•.... ........ . · ...•..... . .•.•.....
· .•...•... •... .•.... .•.. .•.... .•...•.... .•...•....
.•...•... .. ••..... •.... .•... •.... .•... ......•...
· .•...•... •... .•.... •••••••••• ......... . ......... .
•.... .•...
.
.•.... .
•

•

074

075

077

076

100

102

101

•

.....

· .•...•...
.•...
.....
..•...
•....
.•...
•....
.•...
••••••••••
••••••••.
.. . . . . . . ••
•........

.....•...

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MA-6018

Figure D-l

Alternate Character ROM, Standard Graphics
(Sheet 1 of 3)

D-2

.•.. .•.....•.....
••..•..............
.••.....
.•... •• •••••••• ••••••••• .••.•.... ..........
.••......
.••.......
.•... .•.... .•..
.........
.
...•.....
.•••.....
.•..
.•..
•...•....•..•...... .
•.... .•... •.... .•...
.•... .. .•.•.... .
...................
.
•....•...
.
.........
.........
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•••••••••• ..
•....•... .•..
.
.•... •....
•.... .•...
•• •••••••• ••••••••• •••••••••• ••••••••••
......
.••...... .•..•....
.••..... .•..
.••..... .••....... •...•....
...•..... •...•....
••••••••• ••••••••• •••••••• ...•... ......... ••••••••• •••••••••
.......... ....
••••••••• ......... .
103

.•.... ·

104

105

DISPLAY CODE (OCTAL)
111 -.-.J
110

107

106

.......... .......... ..
·
. .•.......
.•....
..........•....•...•.........
...... -"
........ .
. •........ . .
.•.... ........ .
.•...... .
•
....
.•....
....

.
.•....
.•.... .
•....
.
•.... .•...•
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•....
.•...

•

112
114
. .. 113
.•....
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•........ . •........ . •........ .
•......... •........ .
•.......
•........ .
. ..... •........ .

116
.. 115
. 120
. 117
· .•....... · ..•...... .
.
.
.. .•...... .. .•...... . ..•...... . ..•......
.. •...... .. .•...... . ..•...... . ..•......
. ..•...... . ..•...... .. .•...... . ..•......
. ..•...... . ..•...... . ..•...... . ..•......

•

••

•

','

•

.............. . ..•....
.....
.. .•....•...
.......
.•....

•

••••••••• ••••••••• ••••••••• •••••••••
•

•

••••••••• ••••••••• •••••••••
•

•

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.•..
.
........ . . .. ....
..... ..
...
.....
. .....
.
.
•••••••••
••••••••• ••••••••• ••••••••• ••••••••• ••••••••• .

125
127
121
126
123
..........
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. .. 124
.•...•....
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... 122
.. .•...... . ..•...... · .•..•....
..••..... . .....•...
.
•••••••••
•••••••••
•••••••••
•••••••••
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.•... •.... .•... •.... .•... •.... .•... .....•... .....•...
.•... •.... .•... •.... .•... •.....•... .... '.'," .....•...
.•...
•.... .•... •.... .•... •.... .•... .....•... .....•... .•...•...
•

•

........ .•

•

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.••......
... •.... •.......
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.
..•...•.... •...•....
.•.•......•...•.... ........ .
. . .•...
........ . ........ .
.. 130
. 131
. 132
· .•...........•.......•..•....
•.... .•... •.... .•... .•....
..
, ....•...•.....•...•.....•...
•.... .•... •.... .•... •.... .•...
•.... .•... •.... .•... .....•...
•.... .•... •.... .•... •.... .•...

••••••••• ••••••••• •••••••••
•

•

133

..........
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•

•••••••••

.••....

142
137
141
.•...•....
... 140
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134

135

·
. ..•.......•... ... . .
.
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.
.
.
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136

.•..

143

........ .
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144
. ..••.....
·

145

.•.... .
.
. ..••.....
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.•... ..... .•... ..... .•... ..... . .....•... . .....•...
· .•.•..... .....
.. .•...... ••••••••• • ••••••••• • ••••••••• ••••••••• • • •••••••••
.
.. .•...... •.... .•... •.... .•... •.... .•... .....•... .....•... .....•...
.. .•...... ••••••••• •
. ••••••••• • .
• •••••••••
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.•..

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•

....
. .
........ .

.........
•

..........

MA-6019

Figure D-l

Alternate Character ROM, Standard Graphics
(Sheet 2 of 3)

D-3

DISPLAY CODE (OCTAL)

..
... .. ...
.. . •• .. •••••••••... •• .. . ..
•••••••
.•.
...
..
..
.....
••...
•••••••• ••
••••••••• ••••••••••• •••••••••
...
.•.
...
••••••••••
••
..•. •••••• ••••••• •••••• ••••••
...
.......
••••
••••
•••
••••
... •••.. ... .•. .. .. •• ... ..••• •••..
.•.... ....•. •••..... •••...-.-.. •••••.......•.-.-•. ••••••••••... ••••••••••.......
.•. .......
.•. ......
•
....... •••••••• •••••••..- ••••••••
.......
147

146

. ••••••
.

...

. .
... . .

151

150

.. ••
•••••
.

••••. .

•••••••.

•

155

'157

156

••••

•

.•. .•. ... .•.
••••

165

••••••••

•••••••.

.•. ..
•• .. •••• ..

160

.
.

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•••••••

•

. 167
..

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.

•••••••
176

•••

.
.
.

•

.
.•
.

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-

•

••

•

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•

172

171

170

••••

•

.
.
.

.......•• ••••••• •••••••
-

•

177

•

••••••

Figure D-l

163

•

162

•

...
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......
.•.
..
..
..
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••••••
•• ...
..
..
..
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••• ••••
...
..
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..
......
••
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..
.•.
••••••• •••••••
..
• •••
... ...

.. .•. .•. •••... ... ...
......•. •••• .•.•••••.•... .••• ........ •••• .•..... •••••• .•.......
••
•• •••

175

••••

161

••••
••••

166
•••
• ••••
•••••••••.
•.
•

•

174

173

•

.. •••••••••.. ...... ••••

.
••••
. .. .
••••••
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.. . .
•

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•

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· •••. . . .

•

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164

154--..1

153

. '.

••••

•

152

.
MA-6020

Alternate Character ROM, Standard Graphics
(Sheet 3 of 3)

D-4

APPENDIX E
ALTERNATE CHARACTER ROM, SPECIAL GRAPHICS

Yo u can ass i g nth i s c h a r act e r set as 0 n e 0 f the two a va i lab 1 e
character sets by executing an SCS (select character set) ESCape
sequence as defined in Chapter 5. The special graphics characters
in ~he alternate character ROM-ar~ shown in Figtire E-l.

E-l

DISPLAY CODE (OCTAL)

137

••••••••••
•••••••••
•••••••••
•••••••••
•••••••••

•

•
•

J
..•...
.........
.
..................
.
......
.........
.
••••••
••••••••••
......
.........
.
•••••• ••••••••••
......
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•••••••••••••••••••
...... ............................
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•••••••••••••••••••
......
.
......
............................
.
................................................
.
..........
..........
..................
.
...... .......... .......... ......

140

....
....
....
. ....
....
..........

..........
.......... ..........
.......... ..........
.......... ..........

141

..........
..........
..........
....... ....
..........

142

..........
..........
..........
..........
..........

143

145

144

••••

••••
•
•

....

......... .
......... .

....
....

.
....

......... .

.
.

......................................................................
•••••• •••••••••• •••••••••• •••••••••• •••••••••• •••••••••
••••••
••••••••••
•••••••••• ••••••••••
••••••••••
•••••••••
••••••
••••••••••
••••••••••
••••••••••
••••••••••
•••••••••
......
..........
..........
..........
..........
..........
..........
..........
..........
......
..........
......
.........
•••••••••• ..........
•••••••••• ..........
••••••••••
•••••• ••••••••••
••••••
••••••••••
..........
......
..........
...•..
..•........
..........
..........
..........
......
..........
......
.........
.......... .......... .......... ...... .......... ...... ..•.......
147

146

150

151

153

152

154

••••••••••

••••

•

••••••••••

••••

•

••••••••••

••••

.•

.......... ....

....
••••
....
....

....

••••

....
....

....

155

156

.••...... ..............
.•... .. .•...... .......... . ........ .
. ............................ .
157

.......... ..........
.
.......... .......... ... .•.....

.........
.........

....
....

.......... ..........
·
......
·
......
.......... ..........
.......... ..........
.......... ..........

160

161

162

163

............................
..
............................
............................ .

. •...•....•..•................
. .........•..•.......••.••....
.
.
. .........•..•......•..•......
.......... .......... .

..........
..........
..........
..........
..........

..••.....
.........
.•.•.....
.•.......
.•••.....
.•••.....
............................
.
..••.....
............................
.
.........
.............................

164
..........
..........
........ ..
..........
..........
..........
..........
..........

165
..........
..........
..........
..........
..........
..........

166
..........
..........
..........
..........

167
170
171
172
..........
. .•••.........................
.......... .
.......... . ........ .
.
. ............................ .
.
.......... .......... . ........ .
.
.......... . ............................ .
.
.......... .......... .......... . ........ .
.
.......... .......... .
.
.......... .......... .
.......... .......... .......... .

.....................................................................
............................
.
..........
.........
.
...
.
•••••••••• ••••••••••
...
.
••••••••••
•••••••••• .........
••••••••••.
•.........
..........
••••••••••
•••••••••• ••••••••••
•••••••••• ..........
••••••••••
••••••••••. ..........
..........
.........
.......... .......... .......... .•.•.....
·

173
176
175
174
........................................

.......... .

..........
••••••••••

......
......

MA-6017

Figure E-l

Alternate Character ROM, Special Graphics

E-2

APPENDIX F
DETAILED SPECIFICATIONS

F.l

VT278 SPECIFICATIONS

Dimensions
Monitor
Height
Width
Depth

36.83 em (14.5 in.)
45.72 em (18 in.)
36 • 20 em ( 1 4 • 25 in.)

Keyboard
Height
Width
Depth
Minimum table depth

8 • 89 em ( 3 • 5 in.)
4 5 • 7 2 em ( 18 in.)
20 • 32 em ( 8 in.)
51.4 em (20.25 in.)

Weight
Monitor
Keyboard
Shipping weight

13.6 Kg (30 lbs)
2.0 kg (4.5 lbs)
18 • 6 Kg (41 1 b s)

Environmental
Operating
Temperature
Relative humidity
Maximum wet bulb
Minimum dew point
Al ti tude

10 0 to 40 0 C (50 0 to 104 0 F)
l0~ to 90~
28 C (82 F)
0
0
2
C (36
F)
2 • 4 km ( 8 000 f t)

Nonoperating
Temperature
Relative humidity
Al ti tude

_40 0 to 66 0 C (-40 0 to 151 0 F)
0% to 95%
9.1 km (30,000 ft)

Power
Line voltage

90--128 V rms single phase, 3 wire
180--256 V rms single phase,
3 wire (switch-selectable)

F-l

Line frequency

47--63 Hz

Current

2.2 A rms max @ 115 V rms
1.1 A rms max @ 230 V rms

Input power

250 VA apparent 150 W max

Current limiting

3 A normal blow fuse

Power cord

Detachable, 3-prong, 1.9 m (6 ft)

Di,splay

CRT

l2-inchdiagonal measure, P4
phosphor

Format
(selectable)

24 lines X 80 characters
or
14 lines X 132 characters

Character

Character size

80 column mode
3.35 mm X 2.0 mm
(0.132 inch X 0.078 inch)
132 column mode
3.35 mm X 1.3 mm
(0.132 inch X 0.051 inch)

Active display size

202 mm X 115 mm
(8 inch X 4.5 inch)

Character set

96-character ASCII subset standard
128 additional as option

Cursor type

Blinking solid block

X 9 dot matrix with descenders

Keyboard
General
K~yboard

83-key detachable unit with 1.9 m
(6 ft) coiled cord
layout

65-keys similar to standard
typewriter keyboard with l8-key
numeric keypad

Numeric keypad

l8-keys with period, comma, minus,
enter, and four general-purpose
function keys

Visual indicators

Seven LEDs: on line, local, and
data set ready, and four
user-programmable •

. F-2

Keyclick: sound simulates
typewriter. Bell sounds upon
receipt of BEL code

Audible signals

I/O Interconnect
Printer port

25-pin male connector (Figure F-l)

RX278 floppy disk
interface

37-pin female connector (Figure
F-2)

DP278 communications
option

Two 25-pin male connectors,
(Figure F-3)

RL278 hard disk
interface

37-pin male connector (Figure F-4)

•
•
•
•
•
•
•

•
•
•
•
•
•

MA-7190

Figure F-l

VT278 Printer Port Connector

F-3

MA-7191

Figure F-2
EIA
RS449

EIA
RS232C

CCITT
V24

RX278 Floppy Drive Interface Connector

DIN
66020

EIA
RS4499

EIA
RS232C

CCITT
V24

DIN
66020

MA-7192

Figure F-3

DP278 Communications Options Connector
(Port0/Port 1)

F-4

~
DRV ROY
DRV ROY

•
18

+
+

STAT IN

STAT ClK

RD DATA

SECT PlS

DRV CMD

SYS ClK
SYS ClK

•
•
27

•

DRV SE l 1 +

DRV SE l1 -

WRT GATE +

DC OK

WRT DATA +

•

8
7

WRT DATA-

DRV SE lO+

DRV SE lO-

Figure F-4

F.2

WRT GATE -

•
•

DRV CMD -

DRV ER R +

STAT ClK

DRV ER R-

STAT IN

MA·7193

RL278 Disk Cartridge
Interface Connector

RX02 DISKETTE DRIVE SPECIFICATIONS

System Reliability
Minimum number of
rev/track
Seek error rate
Soft data error rate
Hard data error rate

3 million/media (head-loaded)

1 in 10 seeks
1 in 10i2bits read or written
bits read or written
1 in 10

NOTE: The above error rates only apply to DEC approved media that
are properly cared for. Seek error and soft data errors are
usually attributable to random effects in the head7media

TnFerface;-such-as-erectrRal-noTse;-dlrt~-or-dust:-Both-are

t" err r

the err r

era e

call
"s 0 f
0 s i f
0
is
C0 v
b1
in 10 add TFforial
tries or less. "Hard" errors cannot be recovered. Seek error
retries should be preceded by a recalibrate.
Drive performance
Capacity
Per diskette

Per track
Per sector

Recording
FM (single
densi ty)
MFM (double
densi ty)
FM
MFM
FM
MFM

F-5

8-bit bytes
256,256

l2-bit words
128,128

512,512

256,256

3328
6656
128
256

1664
3328
64
128

Data transfer rate
Diskette to controller
buffer
Buffer to CPU interface

4 uS/data bit (FM); 2 us/data bit
(MFM)
1.2 us/bit

NOTE: RX278 interface can operate in 8- or 12-bit modes under
software control.
Track-to-track move
Head settle time
Rotational speed
Recording surfaces/disk
Tracks/disk
Sectors/track
Recording technique

6 ms/track maximum
25 ms maximum
360 rpm +2.5%; 166 ms/rev nominal

77 (0--76) or (0--114 8 )
26 (1--26) or (0--32 )
Double frequency (FM~ or
modified MFM
3200 bpi (FM) or modified (MFM)

Bit density maximum
on inner track
Track density
Average access

48 tracks/inch
262 ms, computed as follows:
Seek
Settle
Rotate
77 tks/3

X 6 ms + 25 ms + 166 ms/2 = 262 ms

ENVIRONMENTAL CHARACTERISTICS
Temperature
RX02, operating
RX02, nonoperating
Media, nonoperating

150 to 32 0 C (59 0 to 90 0 F) ambient;
max. temp. gradient =
0
11 C/hr (20 0 F/hr)
0
0
-35 to +60 C (-30 0 to +140 0 F)
0
-35 to +52 0 C (-30 0 ~o +125 0 F)

NOTE: Media temperature must be within operating temperature range
before use.
Heat dissipation
(RX02 system)
Relative humidity
RX02, operating

RX02, nonoperating
Media, nonoperating
Magnetic field

less than 225 btu/hr

25 0 C (77 0 F) maximum wet bulb
0
0
2 C (36 F) minimum dew point
20% to 80% relative humidity
5% to 98% relative humidity (no
condensa tion)
10% to 80% relative humidity
Media exposed to a magnetic field
strength of 50 oersteds or greater
may lose data.

F-6

Interface modules
Operating temperature
Relative humidity
Maximum wet bulb
Minimum dew point

50 to 50 0 C (41 0 to 122 0 F)
10% to 90%
36 0 C (90 0 F)
2 C (36
F)

Electrical
RX02 power consumption

5 A @ +5 Vdc, 25 W; 0.14 A @ -5 Vdc,
0.7 W; 1.3 A @ +24 Vdc, 31 W

AC power

4 A @ 115 Vac
2 A @ 230 Vac

F.3

RL92 DISK DRIVE SPECIFICATIONS

Physical and Environmental
Width
Depth
Height
Weight

Compatible with 48.26 cm (19 in)
RETMA rack
63.5 cm (25 in) behind bezel
26.52 cm (10.44 in)
34.02 kg (75 lb)

Mounting

Drive mounts on chassis slides

Power source

99--127 Vac (47--63 Hz)
180--254 Vac (47--63 Hz)
(manually-selectable)

Input power

160 W max @ 115 Vac, 60 Hz

Power factor

Greater than 0.85

Starting current

3.5 A rms max @ 90 Vac/47--63 Hz
5.9 A rms max @ 127 Vac/47--63 Hz
1.75 A rms max @ 180 Vac/47--63 Hz
2.5 A rms max @ 254 Vac/47--63 Hz

Heat dissipation

699 Btu/hr max

Power cord and connector

Molded line cord compatible with
drive operating voltage, and 861
power control for 129 Vac attaches
to drive. Power 'cord is 2.74 m (9
ft) long; ·plug is NEMA 5-15P.
239 Vac plug to attach to high
voltage drives is NEMA 6-15P

Safety

RL92 disk drive is UL listed and
CSA certified.

Interlocks

Used where potential exists for
damage to drive, media, operators,
or service personnel.

F-7

Temperature/Humidity
Operating
Temperature
Relative humidity
Maximum wet bulb
Minimum dew point
Nonoperating
Temperature
Relative humidity

-40 0 C (-40 0 F) to 66 0 C (151 0 F)
10% to 95% noncondensing

Al ti tude
Operating

2440 m (8,000 ft) max

Nonoperating

9.1 km (30,000 ft) max

Shock
Operating

Nonoperating

Vibration
Operating
Sinusoidal vibration

Nonoperating
Vertical axis excitation

Half sine shock pulse of gravity
peak and 10 +3 ms duration applied
once in either direction of 3
orthagonal axes (3 pulses total).
Half sine shock pulses of 40
gravity peak and 30 +10 ms duration
perpendicular to each of six
package surfaces.

(sweep rate 1 octave/min)
5--50 Hz, 0.002 in displacement
amplitude
50--500 Hz, 0.25 gravity peak
500--50 Hz, 0.25 gravity peak
50--5 Hz, 0.002 in displacement
ampli tude
1.40 gravity rms overall from
10--300 HZ Power spectral density
of 0.029 g 2 /Hz from 10 to 50 Hz,
with 8 dB/octave rol10ff from
50--300 Hz.

Longitudinal and lateral
axis excitation

0.68 gravity rms overall from
10--200 HZ 2 Power spectral density
of 0.007 g /Hz from 10--50 Hz, with
8 dB/octave rolloff from 50--200
Hz.

EMI

Meets DEC Standard 102, Section 7.

F-8

Dust

Attitude
Maximum pi tch
Maximum roll

The drive will operate in an
ambient atmosphere of less than 5
million particles 0.5 microns or
larger per cubic foot of air. The
drive is intended to run in a light
industry or cleaner environment.
+15 degrees
+15 degrees

Operational Specifications
General
Linear bit density
16 bit words per sector
Number of sectors
Track density
Number of tracks
Number of surfaces
Formatted capacity
Encoding method

5.2 (meg abytes)
MFM

Transfer rate (unbuffered
val ues)
Bit rate
Bit cell width
Words (16 bit)

4.1 megabits/second +1%
244 ns +1%
256 kilowords/second +1%

Latency
Rotational frequency
Average latency
Maximum latency

2400 rpm
12.5 ms +0.25 percent
25.0 ms +0.25 percent

Seek Time
Average
One track
Maximum
Head switching time

55 ms max (170 tracks)
15 ms max
100 ms max (512 tracks)
8 ms max

Start/Stop Time
Start
Stop

45 seconds
30 seconds

3725 bits/in at track 255 (decimal)
128
40 per surface
125/in
256 per surface
2

Disk Cartridge Specifications
Operating environment

Operating temperature of air
surrounding cartridge is within 40 0
to 48 0 C (40 0 to 120 0 F) range at
relative humidity of 8 to 80
percent. Wet bulB reading shall not
exceed 25 0 C (78 F). Before a
cartridge is used, it should be
kept in its cover for a minimum of

F-9

two hours in the same environment
as the disk drive in operation.
Above specified range does not
necessarily apply to disk drive.
0

Storage environment

Starage te~peratur8 is from -40 to
65 C (-40 to 150 F). Wet bulb
reading not exceeding 29 0 C (85 0
F). For wet Bulb temgeraturgs
between 0.56 and 29 C (33 and
85 0 F) disk cartridge shall be able
to withstand a relative humidity of
8--80%. Stray magnetic field
intensity shall not exceed 50
oersteds.

Dimensions (cartridge)

External diameter of top cover is
38.35 cm (15.1 in).
External diameter of protection
cover is 37.03 cm (14.58 in).
External height of cartridge
resting on bottom surface is 6.19
cm (2.44 in).

Maximum speed

Rotating parts of disk cartridge
can withstand effect of stress at
speed of 2500 rev/min.

Track geometry

512 discrete concentric tracks per
data surface.

Data track identification

Three-digit decimal number
(000--511) that numbers data tracks
consecutively starting at outermost
data track of each data surface.

Data surface
identification

Numbered 0 and 1 starting with
uppermost surface and corresponding
with head numbers.

Cylinder address

A cylinder is defined as the data
tracks on the data surface, one
track per surface, with a common
data track identification.

Data track address

A l6-bit word, where bits 0~-5
define a binary sector number, bit
6 defines surface, and bits 7--15
define a binary cylinder address.
This information is in word 1 of
each sector's header.

F-IO

APPENDIX G
PROGRAMMING CONSIDERATIONS

G.l
VT278 PROGRAMMING DIFFERENCES
The VT278 is upward compatible with earlier PDP-8 type computers.
The following paragraphs highlight the significant differences
between the VT278 and its predecessors.
G.l.l
Normal Interrupt Operation
The "Skip on Flag" lOT (6XYl) instructions in the VT278 clear a
flag when the flag is found to be set. lOT skip instructions on
earlier PDP-8 type computers did not clear the flag. Most programs
do not find this difference a problem. However, if a program
relies on the flag to still be set after the skip, the program
needs to be changed.
The following example shows code that fails on a VT278 but runs on
the earlier machines.
TSTl,

TST2,

6031
JMP OTHER
• • • •
• • • •

6031
HLT

/Test keyboard flag
/Not set, try something else
/Come here when skip occurs
/Now try flag again
/This time it didn't skip as the
/first 6031 cleared it.

G.l.2
Interrupt Enables
Previously, devices 03, 04 and 32, 33 had a single interrupt
enable for each device pair. The VT278 has a separate interrupt
enable for each device of the pair and separate instructions for
setting and clearing each.
Instruction

VT78

VT278

6035

Load interrupt enable
for both 03 and 04
from ACll.

Load interrupt enable for
03 only from ACll.

6045

Skip if either device
03 or 04 is causing
an interrupt.

Load interrupt enable for
04 only from ACll.

G-l

6325

Load interrupt enable
for both 32 and 33
from ACll.

Load interrupt enable for
32 only from ACll.

6335

Skip if either device
3~ or 33 is causing
an interrupt.

Load interrupt enable for
33 only from ACll.

Interrupt service routines that use the 6045(6335) skip need to be
altered. In general individual interrupt enables should cause no
problems except when programs attempt to disable interrupts from
device 04(33) by issuing lOT 6035.
G.l.3
lOT 6030 and 6329
These instructions previously clear the
VT278, the instructions set the flags.

TTI/TTI2

flags.

the

G.l.4
Stack Operations
VT278 stack instructions should not produce any incompatibility
problems unless the operating software arbitrarily enables a
(nonexistent) KT8A.
G.l.S
R3L Instruction
This new instruction rotates the AC three positions to the left,
leaving the link unchanged by directly moving ACB into ACll. This
was previously an illegal instruction. It should pose no problems
unless it was used to identify the type CPU on which a program was
running. It may now indicate the 'wrong' type CPU.
G.l.6
WSR and OSR Instructions
The WSR instruction was previously illegal. On the VT278, it can
be used to clear the AC. The OSR instruction is used on the VT278
to read status information. There is no swi tch reg ister on the
VT278.
G.l.7
The HLT Instruction
The HLT instruction or any group 2 microinstruction that includes
a HLT should never be executed in a user program. The effect is a
trap into control panel memory, entry into SET-UP mode, and the
display of a message of the form:
HLT XXXX YYYY ; AC,MQ,SPl,SP2 AAAA MMMM SSSS PPPP
Where:
XXXX = flag word at time HLT was executed
YYYY

= program counter +1 (instruction address following HLT)

AAAA = value in AC

G-2

MMMM = value in MQ

= value in SPI
PPPP = value in SP2
SSSS

The only recovery from this state is to reboot.

)
G-3

OECmate SYSTEM ARCHITECTURE MANUAL

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