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XX-57EEC-53
May 2000
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IM6402
Order Number:
XX-57EEC-53
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8
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http://bitsavers.org/pdf/dec/pdp8/cmos8/_dataSheets/IM6402.pdf
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IM6402/1M6403 Universal Asynchronous Receiver Transmitter (UART) FEATURES .GENERALDESCRIPTION • Low Power - Less Than 1 OmW Typ. at 2MHz • Operation Up to 4MHz Clock -'" IM6402A • Programmable Word Length. Stop Bits and Parity • Automatic Data Formatting and Status,Generation • Compatible with Industry Standard UART's IM6402 • On-Chip Oscillator with External Crystal IM6403 . The IM6402: and IM6403 are CMOS/LSI UART's for inte"rfacing computers or microprocessors to asynchronous serial data channels. The receiver converts ser'ial sta'rt, dilta, parity and stop bits to parallel data verifying proper code transmission, parity, and stop bits. The transmitter converts parallel data into 'seri.alform and automatically adds start, parity, and stop bits. The data word length can be 5, 6, 7 or 8 bits. Parity may be odd or even. Parity checking and generation can be inhibited. The stop bits' may be one or two (or one and <?ne-half when transmitting 5 bit code). Serial data format is shown in Figure 7. ThelM6402 and IM6403 can be. used in a wide range of applications including modems, printers, peripherals and remote data' acquisition systems. CMOS/LSI technology permi~l!'operating clock frequencies upt04.0MHz(250K Baud) an improvement of 10 to lover previous PMOS UART designs. Power requirements, by comparison, are reduced from 670mW, to 10mW. Status logic increases flexibility and . simplifies the user interface. • Operating Voltage ,IM6402_1/03_1: 4-7V IM6402A/03A: 4-11V IM6402/03:4-7V ThelM6402 differs from the IM6403 on pins2, 17, 19, 22, and .40 as shown in Figure 5. The IM6403 utilizes pin 2 as a crystal divide control imd pins 17 and 40 for an inexpensive crystal oscillator. TBREmpty and DReady are always active. All other input and output functions of the IM6402 and IM6403 are identical. PIN CONFIGURATION PACKAGE DIMENSIONS I' vcc'~I=" GND~ 3 :, , 39~EPE 38~CLSf RRD' 4 3' pelS> RBR8 5 RBR?·I 6 36 35 tJ sss PPI 32 TeA7 RRBBRR3, ,'0, RBRt PE FE 12 13 14 31 30 29 28 27 TBRS TBRS T8R4 TSR3 TBR2 OE SFD 15 16 26 TBAf 25 ~ TRO 4 17 24 OR~~ 18 [:::::::::::':::::::53 Si ~. 0.060(1.524), 0.160 MAX. '0.0'01.511 TABLE 1 I-'P-;;-IN+I",;Mc;:640'0''-t-:~'M",640~3w""'",XT",',,,l-t--,IM",640~3;;:w'-;::EX2T~e;;;lo",e.c.K--1 I' 1 17 40 Nie RRC TRC 1 DIVIDE CONTROlj DIVtD. E CONTROi.. XTAL EXTERNAL CLOCK INPUT XTAL GND = __---' '-""'--L...:.:c:'--'--_="-_'--_ _ J I-, -II-, 0.070 (1.7781 TYP. 0.018 (0.457) TYP. 0.020 (0.508) (~'~~l Q.Ot2 (0.305) TYP. TVP. 0.00' (0.0'51 '4.0641 -II.-, 0.160 (4.0641 '0.100 (2.540) ~ I- --I . 0 .... I1~X~1 MIN. 40 PIN PLASTIC DUAL·IN·LlNE PACKAGE (PLl TRE I 23 ::i'rBRL ---- ~:,~ : -\ 37161 :::: ~ : ~ ~:~8 RBR41 9 ,2.040 (51.8201 ;~ S~~RE [:::::D::::::5~~1 ·See Table 1 ORDERING INFORMATION ORDER CODE IM6402·1I1J3.1 IM6402A/03A PLASTIC PKG IM6402·1/03-1IPL IM6402/03-AIPL IM6402I03 IM6402/03-IPL CERAMIC PKG IM6402·1/1J3.110L IM6402/03·AIDL - MILITARY TEMP. IM6402·1/03-1MOL IM6402/03-AMOL MILITARY TtMP. IM6402·1/1J3.1 IM6402/03-AMOLI WITH 8838 MOl/8838 8838 'I '2.02~~~:3081 - 0.050 ~(103~2~1..f ~NO!!~~~~~~~I~NS AREMETRIC 0.165 (~~~Et~· t J( II ,!-, --It---, 0.050 11.270) 0.018 (0.4571 ±O.010 (0.254) to.D0210.0511 . I I --i t-; 0.125 0.100 (2.540) 13.175) ±O.010 (0254) MIN. I 0.000 1 0.008(0.'031 1--(15.2401---10.012(0.305) REf. 40 PIN CERAMIC DUAL-IN-liNE PACKAGE (OL) IM6402/1M6403 U~U!b IM6403 FUNCTIONAL PIN DEFINITION EPE GND elS1 RRD CL52 RBRS SBS RBA7 PI RBA6 CRL RBR5 T8R8 RBR4 TBR7 RBR3 T8R6 RSR2 T8R5 ", RBAl T8R4 (Continued) , PIN SYMBOL DESCRIPTION 14 FE' A high level on FRAMING ERROR indicates the first stop bit was invalid, FE will stay.active until the next valid character's stop bit is rect>ived. 15 OE A high level on OVERRUN ERROR indi. cates the data received flag was not cleared before the last character was transferred to the receiver buffer register. The Error is reset at the next character's ~ bit if ORR has been performed (i.e" ORR: active low), 16 SFD A high hivel on STATUS FLAGS DISABLE forces the outputs PE, FE, OE, DR:'rBRE* to a high impedance state, See Figure 4 and Figure 5. PE T8A2 FE OE T8Rl SFD TRO TRE TBAl DR MR RRI -DIFFERS BETWEEN IM6402 AND IM6403. FIGURE ,1. Pin Configuration IM6403 FUNCTIONAL PIN DEFINITION PIN SYMBOL DESCRIPTION *LM6402 only, 17 IM6402-RRC The RECEIVER REGISTER CLOCK is 16X IM6403-XTAL the receiver data rate. or EXT ClK IN 1B A low level on DATA RECEIVED RESET clears the data received output (DR), to a· low level. Positive Power Supply 2 IM6402·N/C No Connection IM6403-Control Divide Control High: 2,4 (16) Divider Low: 2,11' (204B) Divider 3 GND Ground 4 RRD A high level on RECEIVER REGISTER DISABLE forces the receiver holding register outputs RBR1-RBR8 toa high impedance state. 5 RBR8 The contents of the RECEIVER BUFFER REGISTER appear on these three-state outputs. Word formats less than B char. acters are right justified to RBR1. 6 RBR7 See Pin 5 ~ RBR8 7 RBR6 See Pin 5 ~ RBR8 8 RBR5 See Pin 5 - RBR8 9 RBR4 See Pin 5 - RBRB 10 RBR3 See Pin 5 - RBR8 11 ·RBR2 See Pi.n.5 - RBR8 12 RBRl See Pill 5 - RBR8 13 PE . A high level.on PARITY ERROR indicates 'that the received parity does not match :parity programmed by control bits. The output is active until parity matches on a succeeding character, When parity. is inhibited, this output is low. 19 DR A high level on DATA RECEIVED indicates' a character has been received and transferred to the receiver buffer register, 20 RRI Serial data on RECEIVER REGISTER INPUT is clocked into the . receiver register. 21 MR A high level on MASTER RESET (MR) clears PE, FE, OE, DR, TRE and setsTBRE, TRO high, less than 18 clocks after MR goes 10w,TRE returns high. MR does not clear the receiver buffer register, and is required after power-up, 22 TBRE A high level on TRANSMITIER BUFFER REGISTER EMPTY indicates the transmitter buffer register has transferred .its data to the transmitter register and is ready for new data, ' 23 A low level on TRANSMITIER BUFFER REGISTER LOAD transfers data from inputs TBR1-T8R8 into the transmitter buffer register, A low to high transition on T8RL requests data transfer to the transmitter register. If the transmitter register is busY,transfer is automatically delayed so that the two characters are transmitted end to end. See Figure 2. 24 TRE A high level on TRANSMITIER REGISTER EMPTY indicates completed transmission of a character including stop bits, 25 TRO Character data,' start data and stop bits appear serially at· the TRANSMITIER REGISTER OUTPUT, O~Olb IM6402/1M6403 IM6403 FUNCTIONAL PIN DEFINITION IM6403. FUNCTIONAL PIN DEFINITION (Continued) (Continued) PIN SYMBOL DESCRIPTION PIN SYMBOL DESCRIPTION 26 TBRI Character data is loaded into the TRANSMITTER BUFFER REGISTER via inputs TBR1-TBR8. For character formats less . than 8-bits,'the TBR8, 7, and 6 Inputs are ignored corresponding to the programmed word length. 35 PI" A high level on PARITY INHIBIT inhibits parity generation, parity checking and forces PE output low, 36 SBS" A high level on STOP BIT SELECT selects 1.5 stop bits for a 5 character format and 2 stop bits for other lengths. 37 CLS2" These inputs program the CHARACTER LENGTH SELECTED. (CLSI low CLS210w 5-bits) (CLSI high CLS210w6-bits)(CLSl low CLS2 high 7-bits) (CLSl high CLS2 high 8-bits) 38 CLS1" See Pin 37 - 39 EPE" When PI is low, a high level on EVEN PARITY ENABLE, generates and checks even parity. A low level selects odd parity. 40 IM6402-TRC IM6403-XTAL or GND The TRANSMITTER REGISTER CLOCK is 16X the transmit data rate. 27 TBR2 See Pin 26 - TBRI 28 TBR3 See Pin 26 - TBRI 29 TBR4 See Pin 26 - TBRI 30 TBR5 See Pin 26 - TBRI 31 TBR6 See Pin 26 - TBRI 32 TBR7 See ,Pin.26 - TBRI 33 TBR8 See Pin 26 - TBR1, 34 CRL A high level on CONTROL REGISTER LOAD loads the' control register. See Figure 3. CLS2 "See Table 2 (Control Word Functionl TABLE 2. Control Word Function CLS2 L L L L L L L L L L L L H H H H H H H H H H H H x = Don't Care CLS1 L L L L L L H H H H H H L L .L. L I: L H H H "H H H CONTROL WORD, EPE PI L L L L H L L' H H X X H' L L L. L L H H L H X H X L L L L H L L H X H H X 'L L L L H L H L H X H X SBS L H L H L H L H L H L H L H L H L H L H L H L H DATA BITS 5 5 5 5 5 5 6 6 6 6 6 6 7 7 7 7 7 7 8 8 8 8 8 8 PARITY BIT ODD ODD ' EVEN EVEN DISABLED DISABLED ODD ODD EVEN EVEN DISABLED DISABLED " ODD ODD EVEN EVEN DISABLED DISABLED ODD ODD EVEN EVEN DISABLED I DISABLED STOP BIT(SI 1 1.5 1 1.5 1 1.5 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 U~UIb IM6402/1M6403 IM6402A1IM6403A· ABSOLUTE MAXIMUM RATINGS Operating Temperature Industrial IM6402AII03AI ............ -40°C to +85°C Military IM6402AM/03AM .......... -55°C to +125°C Storage Temperature •.................. -65°C to 150°C Operating Voltage ,....................... 4.0V to 11.0V Supply Voltage ......... ; ....•........ ; ........ '+12.0V Voltage On Any Input or Output Pin .. -O.3V to Vee +O.3V NOTE: Stresses above those listed under ··Absolute Maximum Ratings·· may cause permanent device failure. These are stress ratings only and functional operation of the devices at these or any other. conditions above those indicated in the operation sections ofthis specification is not implied, Exposure to absolute maximum rating conditions for extended periods may cause device failures. D.C. CHARACTERISTICS TEST CONDITIONS: Vee = 4V to 11 V, TA = Industrial or Military . PARAMETER SYMBOL VIH I nput Voltage High 2 VIL Input Voltage .Low 3 IlL Input Leakagel l J 4 VOH Output Voltage High IOi-! = OmA . 5 VOL Output Voltage Low IOL =.OmA 6 IOL Output Leakage GND<:VOUT<:VCC 7 ICC Power Supply Current Standby VIN=GND orVcc 8 ICC Power Supply Current IM6402A Dynamic IC'" 4MHz 9 ICC Power Supply Current IM6403A Dynamic ICRYSTAL';3.58MHz 10 CIN Input Capacitancel l ] 11 Co Output Capacitance I 1 J Typ2 MIN CONDITIONS 1 MAX -1.0 GND<:VIN<:VCC ... UNITS V 70% VCC 20% VCC V 1.0 IJA GND+O.Ol V 1.0 IJA V VCC-O.Ol -1.0 5.0 500 IJA 9.0 mA . 13.0 mA 7.0 8.0 pF 8.0 10.0 pF MIN Typ2 MAX UNITS. D.C. 6:0 4.0 MHz '8.0 6.0 MHz . NOTE 1: Except IM6403 XTA L input pins (i.e. pins 17 and 40). NOTE 2: VCC= 5V. TA = 25°C. A.C. CHARACTERISTICS TEST CONDITIONS· Vee = 10V+5% , CL = 50pF , TA= Industrial or Military SYMBOL CONDITIONS PJ:IoRAMETER 1 IC . Clock Frequency IM6402A 2 ICRYSTAL Crystal Frequency IM6403A 3 tpw Pulse Widths CRL, DRR, TBRL 4 tMR Pulse Width MR 5 tDS Input Data Setup Time 6 tDH Input Data Hold Time 7 tEN Output Enable Time ns 100 40 See Timing Diagrams 400 200 ns (Figures 2,3,4) 40 0 ns 30 30 40 ns 70 ns TIMING DIAGRAMS CLS1, CLS2, SBS, PI, EPE SFOOR RRO 11"-'---'---'-""""\1 STATUSQR RBR1· RBRB FIGURE 2. Data Input Cycle FIGURE 3. Control Register Load Cycle VALID DATA F.IGURE 4. Status Flag Enable Time or Data Output Enable Time O~OIb IM6402/1M6403. I M6402..;1 II M6403-1 ABSOLUTE MAXIMUM RATINGS NOTE: Stresses above those 'Ii~ted under ·:'AbsoliJle.· Maximum R/ltin"s" may cause perman'!nt .device failure. These. are .~tress ratings only and functional operation' 0; the .devices at , 'these 'or any other conditions' 'above 'ihose indicated' in the operation' sections of th is specification is not implied. Exposure to absolute maximum rating conditions for extended periods ,may. cause device failures. Opi!ratingTemperature . . . ' " ' . ind4s~ria(I~6402-111.03~ 11- •.. .':... . . •.. -40~C to +85 0(: :' .. MilitarylliIl6402-.1 iV1I03"lM ........',.". -55°Cto,+125°C 'Storage Temperature ... i .•.· ...·.:·;·........ ·65°C to',!-1500C Operating Voltage ~;. ~',. ;,'.', ..•. :. ~ '.•. j';'; ;'.;'. 4.0V to 7.0V Supply Voltage"', .. : .. ;';.' .': ;'.': .. :'; ~'. '.;~ :.'. :' •.. :(", +8.0V Voltage On Any Input or OiJtputPiri ~':" ·6.3V to Vee +0.3V D.C. CHARACTERISTICS TEST CONDITIONS: Vee = 5.0 ± 10%, TA = Industrial or Military SYMBOL PARAMETER 'I" ,iin'IN CONDITIONS' 1 ,VIH 2 VIr.: 3 IlL Input Leakagelll GND,;;VIN';;VCC -1.0 4 VOH OutputVoltage High I.oH-·0.2mA 2.4 5 VOL Output Voltage Low .. IOL:= 2.0inA 6 IOL' O,:,tput Leakage ... ,'. Input Voltage High .. TVP2 MAI(, . VCC-2.0. . In!lul Voltage Lqw' " . " 0.8 " 1.0 ';, .V . , /lA V: -1.0 GND:-VOUT';;VCC UN.ITS V 0.45 V 1,.0 ./lA 7 I.CC··· . Power Supply Current St~ndby VIN=GND or VCC 1.~ 100 /lA 8 ICC . 'Power Supply Current IM6402 Dynamic. :fC -2MHz' ,. 1.9 mA fCRYSTAL=3.58MHz , ~.5 riJA .. 9 ICC .~ Power Supply Current IM6403 Dynamic 10 CIN: Iri,;<i,tCapacHanee( 1) 7.0 8.• 0 pF 11 Co Output Capac ita~ce[ 1 ) 8.0 , 10.0 , pF MIN Typ2 MAX D.C. 3.0 2.0 UNlrS MHz 4.0 3.58 MHz .. ., . .. NOTE~: Exc9Pt,.IMli403 XTAlt I~put p,ns (,.e. pons 11.and 40) . NOTE 2, VCC=5V,iAd25~C. A.C. CHARAcTERISTICS TEST CONDITIONS:Vc:c = 5.0V ± 10%, CL = 50pF, TA = Industrial or Military SYMBOL PARAMETER 2, CONDITIONS . Clock FrequencyIM6402" fC fCRYSTAL ! ,Crystal ~requency IM6,403 . Pulse Widtli.". CRI;.~' ORR; !BRL ""'" '3 tpw 4 tMR Pulse Width MR; . See Timing Diagrams 5 ,tDS I nput Data .Setup' Time (Figures 2.3,4) 6 tDH Input Data. I:! old A'im e ,,: 7 tEN Output Enable Time RRC 150_ .' '.400 .50',; 60 lis' .50 200' ns 20 ... .. ,40 ·80 " \ PIN 17 ~ ... TRC : PIN40 ns' ns· 160 ns' RECEIVER REGISTER 16XCLOCK I I RECEiVER REGISTER l6X 'Ci.OCI(i i ~ I "I' TRANSMITrERREGISTER / 16XCLOCK I TRANSMITTER REGISTER 16XCLOCK I N/C DR I PIN2 PIN I ,9 IM640:1 PIN 22 I of "" . PIN 16 SFD I ., \ , TBRE DIVIDE CONTRDL PIN 2 L = DIVIDE BY 2048 - - ' - " " " ' 1 1 - - - - - - - - - - - - - - - : - ' H = DIVIDE BY 16 I NIC PIN 19 O.R.,.."""."...+~-...,.,.......c3--'-} I BUFFERS ARE3-STATE \ WHEN SFD • HIGH \ . I , I I , TBRE _ _. P;.:I;.:N.::;22+_~_......c3-_ BUFFERS ARE" . IM6403 . ALWAYS M:..T..IVE " =-t-______ 16 SFD_;.:PI;.:N;.: I I '-" FIGURE 5, Functlonal,DIf,lerence Between IM6402 and IM6403UART (6403 ha. On-Chip 4111 Stage Divider) The IM6403 differs'fromthelMM02 on three Inputs (RRC. TRC. pin 2) as shown in .Figure 5. Two outPUtS (TBRE; DR) are not three-state as on the IM6402. but are always active. The on-chip divider and oscillator allow an inexpensive crystal to be used a~ a ti'inirig sowcetaih~Hh1ih additionillcircuitrys~ch " as.baud rate' 'generators. For example. a cOlorlV crystal at 3.579545MHz results in a baud rate of 109.2Hzfor an easy teletype i.nterface (Figure 11). A 9600 baud interface may be implemented using a 2.4576MHzcrystal with the divider setto divide by 16.' " . 'IM6402/1M6403 I M6402l1M6403 ABSOLUTE MAXIMUM RATINGS Operating Temperature IMS,402/03 . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Storage Temperature ................... -S5°C to 150°C Operating Voltage ...............•......... 4.0V to 7.0V Supply Voltage , ........................ ~ . . . . . . .. +8.0V Voltage On Any Input or Output Pin .. -O.3V to Vee +O.3V NOTE: Stresses above those listed' 'under "Absolute Maximum Ratings" may ,cause permanent device failure. These are stress ratings only and functional operation of the devices at these or any other conditions above those indicated in the operation se,ctions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may cause device failures. ' D.C. CHARACTERISTICS TEST CONDITIONS:, Vee = 5.0 ± 10%, TA = -40°C to +85°C SYMBOL PARAMETER CONDITIONS MIN 1 VIH I nput Voltage High 2 VIL Input Voltage Low 3 'IlL Input Leakagel11 ~ VOH 5 VOL 6 'IOL Output leakage GND<:VOUT<:VCC 7 ICC Power Supply Current Standby VIN=GND or VCC B ICC Power Supply Current IM6402 Dynamic IC = 500 KHz fCRYSTAL",2.46MHz TYP UNITS MAX V VCC'2.0 ; GND<:VIN<:VCC' -5.0· Output Voltage High IOH = -0.2mA 2.4 Output Voltage LoW IOl=I.6mA V 5.0 /-LA V· 0.45 V 5.0 /-LA -5.0 1.0 0.8 BOO /-LA 1.2 rnA 9 ICC Power Supply Current IM6403 Dynamic 3.7 rnA 10 CIN Input Capacitancel1] 7.0 B.O pF 11 Co Output Capaci)anceI1] B.O 10.0 pF MIN TYP MAX UNITS D.C. 3.0 1.0 MHz 4.0 2.46 MHz . NOTE 1:, Except IM6403 XTAl input pins Ii.e. pons 17 and 401. NOTE·2: VCC = 5V, TA = 25'C. A.C. CHARACTERISTICS , " TEST CONDITIONS' Vee= 5 OV + - 10%, Cl = 50pF TA = -40°C to +85°C SYMBOL PARAMETER CONDITIONS 1 IC Clock Frequency IM6402 2 ICRYSTAl Crystal Frequency I M6403 3 tpw Pulse Widths CRL, DRR, TBRl 4 tMR Pulse Width MR 5 tDS I nput Data Setup Time 6 tDH I nput Data Hold Time 7 tEN Output Enable Time . 225 50 ns See Timing Diagrams 600 200 ns (Figures 2,3,41 75 20 ns 90 40 ns BO ns 190 ------,I TBR1ILSB) TRE-+-----, r7.~~~~~~~ *,TBAE CLSl CLS2 CRL I I I ~ ~Mii1iULTIPLEXER~I CONTROL REGISTER TRO SSS EPE PI ~I RRI RRC MULTIPLEXER' RECEIVER REGISTER I I I I I I L , ___ _ I OE , * These out.put~ are three state (lM6402) or alway~ active (~~~3) FIGURE 6" IM6402/03 Functional Block Diagram IM6402/IM6403 BEGINNING OF FIRST STOP BIT~ 1--7 112 CLOcK CYCLES TRANSMITTER OPERATION The transmitter section accepts parallel data, formats it and transmits' it in ,serial form, (Figure, 7) on the TROutpu~ terminal. 5-8 DATA BITS 1.11120R2'STOPBITS STA,RT,BITi\ rl_ _ _-'--'-"-'-'-'I~,~---,--'I '~ ~}SB\\\\ \MSB\ \U~lL , PARITY I RR I' " . DATA, ,. ORR " ~~ I DR '-, " FE -IF ENABLED 1---:-112 CLOCK CYCLE, B A FIGURE 7. Serial Data Format Transmitter timing is shown'in FigureS'. ® Data is ioaded into" the transmitter buffer' register. from the inputs TBRr through TBRS by a logic low on the TBRload input. Valid data must be present at least tos prior to andt oH following the rising edge of TBRl. If words less than 8, bits are used, only the least significant bits are used. The character is right justified into the least significant bit, TBR1. ® The rising edge of i'ifFi[ " clears TBREmpty. 0 to 1 clock cycles late'rdata is transferred to the transmitter register and TREmpty is cleared and transmission starts. TBREmptyis reset to a logichigh. Output data is clocked by TRClock. The clock rate is 16 times the data' rate. © A second: pulse on TBRtoad loads data into the" transmitter buffer :register'.· Data trl!nsferto the transmitter register is delayed until transmission ohhe,current character is complete. @ Data is automatically transferred to th!! transmitter register and transmission of that character begins. " RBR1·8.0 E. PE C FIGUR,E g:Recelver Timing (Nollo Scale) STA,RT BIT DETECTION The receiver uses a l6X clock for timing (see Figure 10.) The start bit ® could have occurred as muc!:1 as one cloCk cycle before it was detected, as indicated by the shaded portion. The center of the start bit is defin~das Clock count 7V2. If the' receiver clock is a symmetrical square wave, the center ofthe start bit will be located within ±1 12 clock cycle, ±l 132 bit or ~ ±3.125%. The receiver begins sea'rching for the next start bit at the center of the first stop, bit. ," CLOCK RRIINPUT " ----r;J I. I. STAI:(T' COUNT7112 '-DEFINED CENTER OF START BIT 7.112 cLOCK CYCLES-----! 81I2CLOCKCYCLES~ FIGURE 10. Slart BII,Tlmlng TYPICAL APPLlC~TION A B 'c o \END OF LAST STOP BIT FIGURE B. Transmitter timing (Nollo Scale) , RECEIVER OPERATlqN' Data is received in serial form atthe RI input. When no'data is being received,Rlinput must remain high; The data is clocked through the RRClock., The clock rate is 16 times the data' rate. ~eceiver timing is shown in, Fi,gure 9. Microprocessor systems, which are inherently parallel in nature, often require a,n asynchronous serial interface; This function can be performEld easily with the IM6402I03 UART. Figure 11 shows how ttie IIvi6403 can be interfac~d to an IM6100 microcomputer system with ,ihe aid of an' IM6l01 Programmable Interface Element (PIE). The PIE interprets l(1putlOutput transfer (lOT) instructions from the proc,essor and generates read and write pulses to the UART. The SENSE lines on the PIE are also employed to ,allow t!:1e pro,cessar to . dete,ct UARTst!ltus. In particular, the processor'mustknow when, the Receive Buffer Register has accumulated a character (DR active);' and when the Transmit Buffer Register can 'accept imother character to be transmitted. .. in this example the characters to be'received or translT!itted wil,l be eight bits long (eLS 1 and 2: both HIG!:i) and transmitted the first stop bit data is transferred from the receiver register to with nopadty (PI:HIGH) and two stop bits (SBS:HIGH). Since the RBRegister)fthe word is less than S bits, the unused most' these' control bits will not be changed during operation, significant bits will be a logic 101lV' The output ci.hiinic~er isiigtit . Control Register :load (CRl) can be tie~ high.,Remember, since justified to the least ,significant bit RBR1. A.logichigh on t!:1E!IM6402l03 is a CMOS device, all unused inputs should be , OError indicates overruns. An oV8,+un occurs 'when DReady committed. ' , has not been cleared befo~e' the present, character. w~s The b~ud rate at 'which the transmi~er and receiver will transfered to the RBRegister. A logic high o~ PErrOi' indicate~ a operate'is determined by theextEltnal crystal and DIVIDE parityerro~.© 112 clock cycle later DReady is seqoa'"j~~ic , CONTROi'pinon the'IM6403. The internal divider can be setto high and FError is evaluated. A logic high onFError'indicates reduce the,crystalfn!quency by eithe~16 (PIN 2:HiGH) 204S an invalid stop bit 'was received. The receiver will not begin searching for the next start bit until a stop bitis received., .:' .,,: (PIN,2:l0W), times!· The frequency out of the internal divider ® A loiN level on DRReset clears the DReadylirie. @ During or O~OIb IM6402/1M6403 should be 16 times the desired baud rate. To generate 110 baud,this example will use a 3.579545MHz color TV crystal and DIVIDE CONTROL set low. The IM6402 may use different receive (RRC) and transmit (TRC) clock ratf3s, but requires an external clock generator. ' To assure consistent and correct operation, the IM6402/03 must be reset after power-up. The Master Reset (MR) pin is active high, and could be driven reliably from a Schmitt trigger inverter and R-C delay. In this example, the IM6100 is reset through still another inverter. The Schmitttrigger between the processor and R-C network is needed to assure that a slow rising capacitor voltage does not re-trigger RESET. A long reset pulse after power-up (-1 OOms) is required by the processor to assure that the on-board crystal oscilla'tor has sufficient time to start. The IM6402 supports fhe processor's bi-directional data bus quite easily by tying the'TBR and RBR buses together. A read command from the processor will' enable the REC'EIVER BUFFER REGISTER onto the bus by using the RECEIVER REGISTER DISABLE (RRD) pin. A write command fro~ the processor clocks data from the bus into the TRANSMITIER BUFFER REGISTER using TBRL. Figure 11 shows a NAND gate driving TBRL from the WRITE2 pin on the PIE. Thisgate is used to generate a rising edge to TBRL at the point where data is stab'le on the bus, and to hold TBRL high until the UART actually transfers the data to it's internal buffer. If TBRL were allowed to return low before TBRE went high, the intended output data would be overwritten, since the TBR is a transparent latch. Although not shown in this example, the error flags (PE, FE, OE) co,-!Id be read by the processor,using the other READ line from the PIE. Since an IM6403 is used, TBRE andDR are not affected by the STATUS FLAGS DISABLE pin. Thus, the three error flags can be tied to the dina bus'and gated by connecting SFD to READ2. If parity is not inhibited, a parity error will caus~ the PE pin to go high until the next valid character is received. A framing error is generated when an expected stop bit is not' received. FE will stay high after the error until the next complete character's stop bit is received. The overrun, error flag is set if a received character is transferred to the RECEIVER BUFFER REGISTER when the previouscha~acter has not been read. The OE pin will stay high until the next received stop bit after a ORR is performed. +5V OXo.OX l1 J::==========;:=============:::;--;::::=;::=t:=====:::3 DXo·OX l1 MR 3.579545MHz IM61001 MICROPROCESSOR c:J XTAL IM6101 PIE DIV INTGNT IM6403 UART 1------'------1 INTGNT LXMAR LXMAR OEVSEL DEVSEL XTC XTC Cl Cl 20rnA OR RS·232 SENSE 1 1----------------1 WRni2~------_r~ C2t-----------~C2 SENSE 2 ....- - - -....---------'1 SKP iiEAo2 SKP/INT LEVEL SHIFTERS REA01~----------~--~ iNT L............__.........4 , FIGURE 11. 110 Baud, Serial Interface ior IM6100 $yslem, ___ +5V
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