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May 2000
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IM6100
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XX-D77EE-17
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22
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http://bitsavers.org/pdf/dec/pdp8/cmos8/_dataSheets/IM6100.pdf
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IM6100 CMOS 12 Bit Microprocessor FEATURES GENERAL DESCRIPTION ®PDP is a registered trademark of Digital Electronics Corp. The IM6100 is a fixed word length,. single word instruction, parallel transfer microprocessor using 12-bit, two's complement arithmetic which recognizes the instruction set of Digital Equipment Corporation's PDP-S/e minicomputer. The internal circuitry is completely static and designed to operi'lte' at any speed between DC and the maximum operating frequency. Two pins are available to allow for an external crystal, thereby eliminating the need for clock generators and level translators. The crystal can be removed and the processor clocked by an external clock generator. The device design is optimized to minimize the number of external components required for interfacing with standard memory and peripheral devices. The IM6100 family includes IM6101 (Programmable Interfacing Element), IM6102 (Memory Extension/DMA Controller/Interval Timer), IM6103 (Parallel Input~Output Port), IM6512 (64 x 12 RAM), IM6312 (1k x 12 ROM), and IM6402/03 (UART), all featuring ultra low power-high noise immunity CMOS characteristics. The entire family is supported by the 6910 Intercept II Microcomputer Development System. PIN CONFIGURATION PACKAGE DIMENSIONS • Silicon Gate Complementary MOS • Fully Static - 0 to 5.7 MHz • Single Power Supply IM6100 Vcc = 5 volts IM6100A Vcc = 10 volts • Crystal Controlled On Chip Timing • PDP®-S/e, Instruction Set Compatible • Low Power Dissipation < 10mW @ 3.3 MHz @ 5 volts • TTL Compatible at 5 volts • Excellent Noise Immunity • Direct Me/llory Access (DMA) • Interrupt = = Vee = = 1 40 2 39 DMAGNT 3 38 CPSEL DMAREO : 4 37 : MEMSEL RUN := 5 36 RUN/HLT ~ 6 RESET 7 35 34 CPR EO INTREO XTA LXMAR ~8 9 33 32 E:= 10 31 11 12 30 29 WAiT XTB DATAF INTGNT = IFETCH =~ C2 ~C1 CO 8 SWSEL XTC 13 28 F 14 27 DX2 18 23 = ~~: :J DX3 19 22 DX6 .DX4 [ 20 21 :: ~ ,060 (1.524) .015 (0.381) I-- .110 (2.794) .090 (2.286) .060 (1.524) .045 (1.143) =p, "'''~'''I.DOB (0.2032) .[11-- I" .023 (.5842) .015 (.3810) .160 (4.064) .100 (2.540) . 'I .680 (17.272) .610 (15.494) DX" F= DX10 :l :J '--------_..... DX7 DX5 ORDERING INFORMATION IM6100A IM61 00 IM6100-1 IM61DO-11PL IM6100-AIPL IM61DO-IPL PLASTIC PKG. CERAMIC PKG. IM61DO-liDL IM61DO-AIDL MILITARY TEMP. IM61 DO-l MDL IM61DO-AMDL MILITARY TEMP. IM61 DO-l MDU IM61 DO-AM DU 8838 6838 WITH 8838 ORDER CODE _[I~..... DEVSEL LINK OSC OUT OS~~~ E= :~ '::~:~~:~,~;,:,~,::::~~:~ ,:~. rr=~ f:::::::;Q;:::::~ ,:~:. . \~::~i . ~!~ .l[~UUUUUUtltlutltltlunUUllU[ , --I l- -=1 r: --ir-' f .060 (1.524) .110 (2.794) ~ ~ .060 (1.524) .045(1.143) 1/ .023 ;.5842) .160 (4.084) .015(.3810) ~ i .015(0.381)-0-\1- I .008 (0.2032) • .680 (17.272) ~ O~OIL IM61 00 .sv GNO r-----r==~::l===r=====~~~~~~~~===iJ'~2t-~MULTIPLEXER ---t-,--I:g[~~J OXo - ox" -I LlNK:.... 1 1 1 I 1 1 os~sg~~--~-+-, XTA, XTB, XTC I~T~~~~~'A~~~""----'-=f-l-l IFETCH LXMAR OEVSEL SWSEL ii.lEMSE[ CPSEL WAIT---~--~ Figure 1: Functional Block Diagram FUNCTIONAL PIN DESCRIPTIONS PIN SYMBOL 1 2 Vec RUN 3 DMAGNT 4 DMAREO 5 CPREO 6 RlJN7i:iLT 7 RESET 8 9 INTREO XTA 10 LXMAR 11 WAIT .... 12 XTB 13 XTC 14 OSCOUT 15 OSCIN 16 DXo 17 OX, DESCRIPTION r Supply voltage. The signal indicates therunstate of the CPU and may be used to power down the external circuitry Direct Memory Access Grant-OX lines are three-state. Direct Memory Access Request-DMA is . granted at the end of the current instruction. Upon DMA grant, the CPU suspends program execution until the DMAREO line is released. Control Panel Request-a dedicated interrupt Which bypasses the normal device interrupt request structure. Pulsing the RunlHalt line causes the CPU to alternately run and halt by changing the state of the internal RUN/HL T flip flop. Clears the AC and loads 77778 into the PC. CPU is halted. Peripheral device interrupt request. External coded minor cycle timing-signifies input transfers to the IM6100. The Load External Memory Address Register is used to store memory and peripheral addresses externally. Indicates that peripherals or external memory is not ready to transfer data. The CPU state gets extended as long as WAIT is active. The CPU is in the lowest power state with clocks running. External coded l1)inorcycletiming-signifies output transfers from the IM6100. External coded minor cycle timing-used in conjunction with the Select Lines to specify . read or write operations. Crystal input to generate the internal timing (also external clock input). See Pin 14-0SC OUT (also external clock ground) DataX...,..multiplexed data in, data out and add ress lines. See Pin 16--0Xo. PIN SYMBOL DESCRIPTION 18 19 20 21 22 23 24 25 26 27 28 29 30 31 DX2 DX3 DX4 DX5 DXs OX? DX8 DXg GND DXlO DX11 LINK DEVSEL SWSEL 32 Co 33 34 35 C, 36 37 38 IFETCH MEMSEL CPSEL 39 40 INTGNT DATAF See Pin 16-DXo. See Pin 16-DXo. See Pin 16-DXo. See Pin 16-DXo. See Pin 16-DXo. See Pin 16-DXo. See Pin 16-DXo. See Pin 16-DXo. Ground . See Pin 16-DXo. See Pin 16-DXo. Indicates state of link flip flop. Device Select for I/O transfers. Switch Register Select for the OR THE SWITCH REGISTER INSTRUCTION (OSR). 'OSR is a Group 2 Operate Instruction which reads a 12 bit external switch register and OR's it with the contents of the AC. I" Control line inputs from the peripheral device during an 1/0 transfer (Table VII. See Pin 32-CQ. See Pin 32-CO. Skips the next sequential instruction if active during an 1/0 instruction. Instruction Fetch Cycle Memory Select .!o( memory transfers. The Control Panel Memory Select becomes active, instead of the MEMSEL, for control panel routines. Signal may be used to distinguish between control panel and main memories. Peripheral device Interrupt Grant. Data Field pin indicates the execute phase of indirectly addressed AND, TAD, ISZ and DCA instructions so that the data transfers are controlled by the Data Field, OF, and not the Instruction Field, IF, if Extended Memory Control hardware is used to extend the addressing space from 4K to 32K words. C2 SKP , O~OI1 IM6100 ARCHITECTURE ARITHMETIC AND LOGICAL UNIT (ALU) The IM6100 has 6 twe.lve bit registers, a programmable logic array, an arithmetic and logic unit and associated gating and timing circuitry. A block diagram of the IM6100 is shown in Figure 1. . The ALU performs both arithmetic and logical operations, -two's complement binary addition, AND, OR and complement. The ALU can perform a single position shift either to the left or to the right; a double rotate is implemented in two single bit shifts. The ALU can also shift by 3 pOSitions to implement a byte swap in two steps. The AC is always one of the inputs to the ALU, however, under internal microprogram control, AC may be gated off and all one's or all zero's gated in. The second input may be anyone of the other registers under internal microprogram control. ACCUMULATOR (AC) The ACis a 12-bit register in which ar.ithmetic and logical operations are performed. Data words 'may be transferred from memory to the AC or transferred from the AC into memory. Arithmetic and logical operations involve one or two operands, one held in the AC and the other fetched from the memory. The result of the operation is left in the AC which may be cleared, complemented, tested, incremented or rotated under program control. The AC also serves as an input-output register, as all programmed data transfers pass through the AC. TEMPORARY REGISTER (TEMP) The 12-bit TEMP register latches the result of an ALU operation, before it is sent to the destination register, to avoid race conditions. The TE'MP is also used as an internal register for microprogram control.' INSTRUCTION REGISTER (IR) LINK (L) The Link is a 1-bit flip-flop that serves as a high-order extension of the AC. It is used as a carry flip-flop for 2's complement arithmetic. A carry out of the accumulator complements the Link. Link can be cleared, set, complemented and tested under program control and rotated as part of the AC. MQ REGISTER (MQ) The MO is a 12-bit temporary register which is program accessible. The contents of AC maybe transferred to the MO for temporary storage, or MO can be OR'ed with the AC and the result stored in the AC The contents of the AC and the MO may also be exchanged. MEMORY ADDRESS REGISTER (MAR) While accessing memory, the 12-bit MAR register contains the address of the memory location that is currently selected for reading or writing. The MAR is also used as an internal register for microprogram control during data transfers to and from memory and peripherals. During an instruction fetch, the 12-bit IR is loaded with the instruction that is to be executed by the CPU. The IR specifies the initial step of the microprogram sequence for each instruction, and is also used as an internal register to store temporary data for microprogram control. MULTIPLEXER (DX) The 12-bit Input/Output Multiplexer handles data, address and instruction transfers into and out of the CPU, and to or hom the main memory and peripheral devices on a timemultiplexed basis. MAJOR STATE GENERATOR AND THE PROGRAMMED LOGIC ARRAY (PLA) During an instruction fetch the instruction to be executed is loaded into the IR. The PLA is then used for the correct sequencing of the CPU for the appropriate instruction. After an instruction is completely sequenced, the major state generator scans the internal priority network, which decides whether the machine is gOing to fetch the next instruction in sequence, or service one of the external request lines. PLA OUTPUT LATCH PROGRAM COUNTER (PC) The 12-bit PC contains the address of the memory location fromwhich the next instruction is fetched. During an instruction fetch, the PC is transferred to MAR and the PC is then incrernented by 1. When there is a branch to another address in memory, the branch address is set into the PC. Branching normally takes ,place under program control, however, during an input-output operation, a device may specify a branch address. A sktp (SKP) instruction[increments the PC by 1, thus causing the next instruction to be skipped. The SKP instruction may be unconditional, or conditional on the state of the AC orthe Link. During an input-output operation, a device can also cause the next sequential instruction to be skipped. Interrupts force the PC to 0000. Reset forces the PC to 77778. The PLA Output Latch permits the PLA to be pipelined; it fetches the next control sequence while the CPU is executing the current sequence. MEMORY AND DEVICE CONTROL, ALU AND REG TRANSFER LOGIC The. Memory and Device Control Unit provides external control signals to communicate with peripheral devices (DEVSEU, switch register (SWSEU, memory (MEMSEU andlor control panel memory (CPSEU. During 1/0 instructions this unit also modifies the PLA outputs depending on the states of the four device control lines (SKP, Co, C1, C21. The ALU and Register Transfer Logic provides the control signals for the internal register transfers and ALU operation. IM61 00 D~DIl. ARCHITECTURE (CONTINUED) T2 TIMING AND STATE CONTROL The IM6l00 internally generates all the timing .and state signals. A crystal is used to cont~ol the CPU operating frequency, which is divided by two by th~ CPU. Witha 4MHz crystal, the internal states will be of. 500nsec duration. The !Tlajortiming states are described in Figure 2 . ' . Tl .For memory reference instructions, a 12-bitaddress is . sent on the DX lines. The Load. External Memory Address Register, LXMAR, is used to clock an external register to store the address information externally, if required. When executing an InputOutput I/O instruction, the instruction .being executed is sent on the DX lines' to be stored externally. ,The external address' register then contains the. device"address and control informa'tion. The LXMAR pulse occurs onlyif a valid address is present on the DX lines. Various CPU request lines are priority sampled if the next cycle is an Instruction. Fetch cycle. Current state of the CPU is available externally. Memory/Peripheral data.is read for an input transe fer (READ). WAIT controls the transfer duration. If WAIT is active during input transfers, theCPU waits in' the T2 state. The. wait duration is an integral multiple of '. the crystal 'freq'uency - 250nsec for 4MHz. For memory reference instructions, the Memory Select, MEMSEL, line is active. For I/O instructions the Device Select, DEVSEL, line is active. Contr,ol lines, therefore, distinguish the contents of the external register as memory or device address.",' External device sense lines, Co, (;1, (;2, and SKp,~re sampled if. the instruction being executed is an I/O instruction.' , Control Panel Memory Select,CPSEL, and Switch Register Select, SWSEL, become active low for data " transfers between the IM6l0Q and Control Panel Memory and the Switch Register,respectively. T3,T4,T5 ALU operation and internal register transfers. T6 This state is entered for an output transfer (WRITEl. The address is defined during T1, WAIT controls the time for which the Write data must be maintained, WAIT WAIT OSCOUT STATES LXMAR MEM/CPlSWSEL ox XTA XTB XTC CPlINT DMAREQ ' RESET, RUN/HLT IFETCH OATAF ,RUN OMAlINT~:~ ,...----....,H-+---------------....--------+-.-.---...01~...j.-" 'Figure 2: IM6HlO AC TIming Diagram U~UIb IM61 00 MEMORY ORGANIZATION LO 1778 LOC 1768 LOC 1758 FIELD 7 FIELD 6 The IM6100 has a basic addressing capacity of 409612-bit words which may be extended by Extended Memory Control hardware to 32K. The memory system is organized in 4096 word blocks, called MEMORY FIELDS. The first 4096 words of memory are in Field 0; if a full32K of memory is installed, the uppermost Memory Field will be numbered 7. In anV given Memory Field every location has,a unique 4 digit octal (12 bit binary) address, 00008 to 77778 (000010 to 409510). Each Memory Field is subdivided into 32 PAGES of .128 words each. Memory Pages are numbered sequenTially from Page OOa, containing addressEls 0000-Oj778, to Page 378, containing addresses 76008-77778 . .The· first 5 bits of a 12-bit MEMORY ADDRESS denote the PAGE NUMBER and the low order 7 bits specify the PAGE ADDRESS of the memory location within the given Page. During an instruction fetch cycle, the IM6100 fetches the instruction pointed to by.the PC, the contents of the peare transferred to the MAR, and the PC is incremented by 1. .The PC now contains the address of the 'next' sequential instruction and the MAR contains the address of the 'current' instruction which must be fetched from memory. Bits 0-4 of the MAR identify the CURRENT PAGE, that is, the Page from which instructions are currently being fetched, and bits 5-11 of, the MAR identify the location within the Current Page. (PAGE ZERO (0), by definition, denotes the first 128 words of' memory, 00008-01778.) FIELD 5 FIELD 4 ,-. FIELD 3 FIELD 2 FIELD 1 FIELD 0 }- 32K MEMORY. (108 FIELDS) ~III~ 01778 FIELD 00008 (40, PAGES) > r'" }- > 01 8 LOC 0078 LOC 0068 LO 0058 LO 0048 LD!: 0038 LOC 0028 LOC 001, LOC 0008 1 MEMORY PAGE (2008 LOCATIONS) MEMORY ADDRESS 1.2-BIT OCTAL MEMORY ADDRESS 47168 7 89 1011 0 011 1 110 0 111 1 11 o 1 2 3 4 56 o 1 2 3 4 PAGE NUMBER 00 - 378 5 6 7 8 9 1011 PAGE ADDRESS 000 - 1778 01 PAGE NUMBER 10011. = 10011 = 238 PAGE ADDRESS 1001110 = 1001110 = 1168 Memory Organization INSTRUCTION SET The IM6100 instructions are 12-bit words stored in 'memory. The IM6100 makes no distinction between instructi.ons and data; it can manipulate instructions as stored variables or execute data as instructions when it is programmed to do so. There are three general classes of IM6100instructions. They are referred to as Memory Reference .Instruction (MRI), Operate Instruction' (OPR) and Input/Output Transfer Instruction (lOT,). The notations used in the following instruction tables are defined in Table I below: TABLE 1. Notation Definitions 1. ( ) denotes the contents of the register or location within parenthesis. (EA) is read as " ... the contents of the Effective Address." 2. (0) denotes the contents of the location pOinted to by the contents of the location within the double parenthesis. ((PA» is read as ". i. the contents of the location pointed tq by the contents of the Pointer Address." 3. - denotes " ... is replaced by ... " 4. - denotes the interchange operation. 5. 1\ denotes logical AND operation. 6. V denotes logical OR operation. 7. EA denotes the Effective Address for Direct Addressing. 8. PA denotes the Pointer Address for Indirect Addressing. PA can be any address on the CURRENT PAGE or PA can be any address (OOOOa) through (0177a) on PAGE ZERO other than the addresses (o010a) through (0017a) which are reserved forautoindexing .. 9. PAIX denotes the Pointer Address for autoindexing. It can be any address (0010a) through (0017a). 10. I represents bit. 3, the Indirect Addressing Bit, of the instruction: 11. EA, PA, or PAIX is specified by bit 4 through bit 11 of the memory reference instruction. 12. PC denotes the Program Counter. 13. SR denotes the Switch Register. 14. (AC)n denotes the nth bit of the AC contents. 15. DEV denotes a specific peripheral device and "dddddd" denotes the device address code. CMND is the command issued to the device during an I/O Operation and "eee" is its three bit code. IM61 00 INSTRUCTION SET (CONTINUED) MEMORY REFERENCE INSTRUCTION (MRI) The Memory Reference Instructions operate on the contents of a memory location or use the contents of a memory location to operate on the AC or the PC. The first 3, bits of a Memory Reference Instruction specify the operation code, or OPCODE, and the low order 9 bits, the OPERAND address, as shown in Figure' 3. " 10 11 ADDRESS • RELATI~~<;'~DR,ESS------.-J MEMORY PAGE o PAGE 0 1 CURRENT PAGE = = Figure 3: Memory Reference Instruction Format By this method; 256 locations may be directly addressed, 128 on PAGE 0 and 1280n the CURRENT PAGE. Other locations are addressed indirectly by setting bit 3. An INDIRECT ADDRESS Ipointer address) identifies the location that contains the desired address leffective address). To address a location that is not directly addressable,not in PAGE Oor in the CURRENT PAGE, the absolute address of the desired location is stored in one of the 256 directly addressable locationslpointer address). Upon execution, the MRI will operate on the contents of the location identified by the address contained in the pOinter location . It should be noted thai locations 00108-00178 in PAGEOare AUTOINDEXED. If these locations are addressed indirectly, the contents are incremented by 1 and restored before they are used as the operand address. These locations may, therefore, be used for indexing applications. Bits 5 through 11, the PAGE ADDRESS, identify the location of the OPERAND on agiven page, buttheydo not identify the page itself. The page is specified by· bit 4, called the CURRENT PAGE OR PAGE a BIT. If bit 4 is a 0, the page address is interpreted as a location on Page O. If bit 4 is a I, Table II lists the mnemonics for the six memory reference the page address specified is interpreted to be 011 the Current instructions, their OPCODEs, the operations they perform Page. and the number of, states r~quired for execution. For example, if bits 5 through 11 represent 1238 and bit 4 is a 0, the location referenced is the absolute address 01238. It should be noted that the data is represented in Two's However,if bit 4 is a 1 and the currentiristruction is in a Complement Intager notation. In this system, thenegative of memory location whose absolute address is 46108 the page a number is formed by complementing each bit in the data address 1238 designates the absolute address 47238, as word and adding "1" to the, complemented number. The sign shown below. ' is indicated by the most significant bit. In the 12-bit ,""ord 46108 = 100 110001 000 = PAGE 10011 = PAGE 238 used by the IM6100, when bit 0 is a "0", it denotes a positive Location 46108 is in PAGE 238. Location 1238 in PAGE 238, number and when bit 0 is a "1", it denotes a negative nU!T1ber. CURRENT PAGE, will be: dO 011 11010 OH= 100 111010011= 47238 The maximum Single precision number ranges for this L PAGE ADDRESS 1238 system are 37778 1+2047) and 40008 (-2048), PAGE NUMBER 238 Table II MNEMONIC OP CODE IA STATES OPERATION AND EA 0 10 LOGICAL AND DIRECT 08 I Operation: IACI-IACI "lEAl Description: Contents of the EA are logically AND"ed with the contents of the AC and the resu!t is stored in AC AND I PA 1 15 LOGICAL AND INDIRECT IPA i' 0010-001781 AND PAIX 1 16 0 10 Lg~!t~~~L}l!.'?eA~W5?6~(~GA~~j(~ = 0010-001781 BINARY ADD DIRECT TAD I PA 1 15 BINARY ADD INDIRECT IPA oF 0010-001781 TAD I PAIX 1 16 0 16 BINARY ADD AUTOINDEX IPAIX = 0010-001781 Operation IPAI-<PA! + 1. lAC) ----AC! + !I PAil INCREMENT AND SKIP IF ZERO DIRECT 1 21 INCREMENT AND SKIP IF ZERO INDIRECT IPA i' 0010-001781 1 22 0 11 INCREMENT AND SKIP IF ZERO AUTOINDEX IPAIX = 0010-001781 Ooeration (PAJ---iPAJ + l' IIPA)! ~IPA)) + I' if IIPAJI -0000 PC-PC+"l DEPOSIT AND CLEAR THE ACCUMULATOR DIRECT DCA I PA 1 16 DEPOSIT AND CLEAR THE ACCUMULATOR INDIRECT IPA i' 0010-00178) DCA I PAIX 1 17 DEPOSIT AND CLEAR THE ACCUMULATOR AUTOINDEX (PAIX = 0010-001781 0 11 JUMP TO SUBROUTINE DIRECT TAD EA 18 ISZ EA ISZ I PA 28 , ISZ I PAIX DCA EA JMS EA 38 48 Operation. IACJ-IACIA uPAIl Operation IACJ~ACI + lEAl . Description: Contents of the EA are ADO'ed with the contents 01 the AC and the result is stored in the AG. carry out complements the LINK. II AC is initially cleared. this instruction acts a$ LOAD from Memory. Operation IACI~ACI+IIPAII Operation: 'IEAI~EAI+l, jf IEAI::oOOOOa. PC-PC + 1 Description: Contents of the EA are .incremented by 1 and restored. If th~ result is zero. the next sequential instruction is skipped. Operation: «PAII-fIPAII+ 1. if IIPAII "" OOoos. PC--PC+ 1 Operation lEAl "-':ACI, (ACI-<)OOOa Description: The contents of the AC are stored in EA and the AC is clea~ed. Operation ({PA))~ACI. IAC)......aooaa Operation (PAI~PAJ+ 1, ((PA))--'(ACJ. IACI--oOOOs Operation: (EAI....-jPCI. IPCI--E.A+l DeSCription: The contents of the PC are. stored in the EA. The PC is incr€!mented by 1 immediately after every instruction fetch.· The contents of the EA now pornt to the next sequendallnstructlon following the JMS (return addressl. The next instruction is taken from EA+l . JMS I PA 1 16 JUMP TO SUBROUTINE INDIRECT iPA ¥ 0010-001781 JMS I PAIX 1 17 JUMP TO SUBROUTINE AUTOINDEX (PAIX = 0010-001781 0 10 JUMP DIRECT JMP IPA 1 15 JUMP INDIRECT IPA i' 0010-001781 JMP I PAIX 1 16 JUMP AUTOINDEX IPAIX = 0010-001781 JMP EA 58 Operation ([PA))-PC, (PCI--...<PAI+l Operation (PA)~PAI+l, IIPAIl---PC (PC)~PAI+l Operation (PCI-EA Description: The next instruction is taken from the EA. Operation (PCI'~PAI Operation (PAI+l, (PCI""';PAI e" n~nll IM6100 logical sequence' number 2 performed second, logical sequence number 3 performed third and so on. Two operations with the same.Jogicalsequenc;e number, within,a given group of microinstructions, are' performed simultaneously. ' INSTRUCTION SET '(CONTINUED) OPERATE INSTRUCTIONS The Operate Instructi~ns, which have anOPCOOE of 78 (111), consist of 3 groups of microinstructions. Group 1, which is identified by the presence of the 0 in bit 3, isused to ' perform logical operations on the contents of the accumula-' tor and link. Group 2, which is identified by the presence of a 11n bit 3 and aOin bit 11, is used primarily to testthecontents of the Accumulator and/or Link and then conditionally skip the next sequential instruction. Group 3 has a 1 in bit 3 and a 1 in bit 11 and performs logical operations on the contents of the AC and MO. The basic OPR instruction format is shown in Figure 4. 0 '9 8 6 5 10 : 'A MICROINSTRUCTION A GROUP 1 GROUP MICROINSTRUCTIONS Figure 5 sho~s the instructioi, format ora group 1 micro- , instruction. Anyone of bits 4 to 11 may be set, loaded with a binary 1, to indicate a specific group 1 microinstruction. If ,more than one of these bits is set, the instruction is a microprogrammed combination of group 1 microinstructions, which will be executed according to the logical sequence shown in Figure 5. . 11 B '2 I BSW IF BITS B&9AREO AND BIT 10 IS 1. lOGICAL SEQUENCES: 1-ClA, Cll'" ' 2-CMA,CMl' 3-IAC " ' , 4-RAR, RAl;,RTR. RTl, BSW B 0 T 0 GROUP 2 4 • GROUP 3 Figure 4: Bas,ic OPR Instruction Format Figure 5: Group 1 Microinstruction Format Operate microinstructions from any group may be micro~ programmed with other 'operate microinstructions of the same group providing the instruction codes do not conflict. The actual code for a mic'roprogrammed combination oftwo, or more, microinstructions is the bitwise logical OR of the octal codes for the individual microinstructions. When more than one, operation is microprogrammed into a, single', instruction, the operations are performed in a prescribed sequence, with logical sequence number 1 performed first, Table III lists commonly used group 1 microinstructions, their assigned mnemonics, octal code, logical sequence, the number of states, and the operation they perform. The .same format is followed in Table IV and V which lists group 2 and 3 microinstructi.ons, respectively. ' 'Table III: Group 1 Operate Microinstructions . OCTAL CODE, LOGICAL ,SEQUENCE NUMBER OF STATES 7000 1 10 lAC 7001 3 10 RAl 7004 4 7006 4 MNEMONIC NOP RTi.. .. , ' ", " " OPERATION NO OPERATION-This lnstru~hon causes a 10s1ate delay In programexeCUhon~'Wi~hout ~ffeCtinQ the stateo! the IM6100. it may be used for tlmlng.synchronlzatLon or as a convenient means of deleting an instructIOn from a program. INCREMENT ACCUMULATOR-The con'ten~ ollhe AC IS Incremented b;' one 1-1) and carry out' complements the L,ink IU. . , .. ROTATE. ACCUMULATOR LEFT -The contents of th~ AC and l are rotated one binary pOSition tothe left. AC (01 is shifted to Land l is shilled to AC 1111. . 15 " 'I i5 ROTATE TWO LEFT ~The contents of the AC and l are rotated two binary positions' to the lefl. ACt11 is shifted to land l is shifted 10 AC /101. 15 ROT ATE ACCUMULATOR R IGt;T-Theconlentof IheACand larerotated.~ne binary pOSition lathe right. AC (111 is shifted to l and'L IS Shifted to AC 101. ' .. :15 ROT ATE TWO RIG HT conlents of the AC and Lare rotaledlwo binary pOSitIOns to the right. AC 110~is 'shifted to land l is shifted to AC (II. 4 15 ~YTE SWAP~.Th~ righl.si~ lSI bllsol tho AC are exchanged or ~WAPPEDwiththe left six bits. ACIOlis sw~pped 7020 7040 : 2 2, 10 10, 7041 2,3 ,10 COMPLEMENT AND INCREMENT ACCUMUlATOR-TheC~"te"tOftMAci",ePI~ced,';"!th Cll CLL RAL Cll RTl Cll RAR Cll RTR STl 7100 7104 ,7106 7110 ' ,7112 7120 1 1,4 1,4 1,4 1,4 1,2 10 CLEAR L;INK-The U:nk ·!S i~adcd W~lh a binary O. 15 :,15 . 15" " 10 ,CLA GLT 7200 7201 '7204, 1 1,3 ,1,4", 10 10 15 CLA CLl STA 7300 7240 1 ,,1.0 10 7010 4 RTR 7012 4 BSW 7002 CMl CMA CIA RAR cui. lAC' ,1,2 , , -The With AC (61, AG til With AC \11, etc. l IS not affected. COMPlEME."NT· L..1Nk~Th(l contenl of the link is complemented. . ' COMPLEMENT ACCUMULATOR-The content of each bit of t!"le AC is C:ompl~mented having the ellect of replacil)g. the .content of the AC with its one's complement. '. .' its two's complement. Carry ~ut complements the LINK. i5 , . . , ClEARLli'lK-'-ROTATE ACCUMULATOR lEFT. CLEAR LINK-ROTATE TWO lEFT. CLEAR LINK-ROTATE ACCUMUlAlPR RIGHT. 'CLEAR LINK-ROTATE TWO RIGHT.' SET TrtE lJNK-The"LlNK is loaded with a bi'nary "corresponding with a microprogrammed c.ombinauor'.ot Cll and CML.· .. . CLEAR ACCUMU LATOR-Tho accumulator ;s loaded VI;th b;nary D's, CLEAR AC::C::UMUlATOR-INCREMENT ACCUMULATOR. GET THE LINK-The AC is cleared; tho content of l is shifted into AC tIll, aO is shifted into L. This is a micro- progra.m.med combination of .ClA and RAL. CL,EAR ACCUMl;J~TOR-CLEAR LINK. SeT .THE ACCUMULATOR-Each bit of the AC is set to 1 corresponding to a microprogrammed combination of CLA and. CMA:. ' . t IM6100 INSTRUCTION SET (CONTINUED) GROUP 2 MICROINSTRUCTIONS Figure 6 shows the instruction format of group 2micrOinstructions. Bits 4-10 may be set to indicate a specific group 2 microinstruction. If more than one of bits,4-7 or 9-.10 is set, the instruction is a microprogrammed combination .of group 2 microinstructions, which willbe executed according to the logical sequence shown in Figure 6. , Skip microinstructians may be micr9Progrimimed wi~h eLl( OSR, or HL T microinstructions. When ,two or more skip microinstructions are microprogrammed into a single instruction, the resulting condition,onwhich the decision will be based isthe logical OR of the individual conditions when bit 8 is 0, or, when bit 8 is 1, the decision will be based on the '. , logical AND. By combining skip. instructions properly, all possible relational conditi'onscan b\l tested (Le., =,;6, <,~, >, ~l. Skip microinstructions which have a 0 in bits 5, 6, 7, or 8 may not be microprOgra~m~d with skip microinstructions which have a 1 in those same bits. LOGICAL SEQUENCES: 1 (BIT B IS ZERO)-SMA OR SZA OR SNL (BIT B IS ONE) -SPA AND SNA AND SZL 2 ' -CLA 3 ,-OSR, HLT Figure 6: Group 2 Microinstruction Format Table W: Group 2 Operate Microinstructions , NUMBER OF OCTAL CODE LOGICAL. SEQUENCE NOP HLT 7400 7402 OSR 7404 SKP SNL 7410 7420 ,10 SZL 7430 10 MNEMONIC STATES OPERATION 1 3 10 NO OPERATION-,-see G,o"P 1 MICROINSTRUCTIONS ' HALT -:-Program ~to~s at ;h~ conclusion of the current machine cycle. If HL'r IS combined with ot'hers in OPR 2, the 3 15 10 other operations are completed before the end althe cycle. 10 OR WI'TH SWITCH 'REGISTER~Th,e,coriten'tof the SWitch Register If OR'ed with the conte'nt of the AC and the resul~ is stored in the AC. The OSR INSTRUCTION TIMING i~ sh,?wn in Figure 7. The IM6100 sequences the OSA instruction through 'a 2-cycle execute phase referred to as OPA 2A and OPR 28 SKIP-The content of,the PC is incremented'by.. 1, t.~,,~klp tli.e n'ext sequential instrucu'on SKIP ON NO'N-ZERO: LINK':'-The'~ontent O'f l is sa~Pled, the ~ext sequential instruction (s skipped if l ' contains a 1. II l contains a 0, the next instruction is executed ", !, • SKIP ON ZERO LlNK":""'The'content of l issampled, the next sequential instruction is skipped if lcontainsa 0, If the L contains a 1, the next instruction is executed I" SZA 7440 10. SKIP, ON ZERO ACCUry1ULA TOR--:-T.heconten~oftheAC is sampled: th.enext'seqUential instruction is ' skipped if the AC has al/,bits which are 0, If any bit In t~e AC IS a 1, the next ir:structlon'ls executed. SNA 7450 10 SKIP ON NON~ZERO ACCUMULATOR-'The cooteol 01 IheAC Is sampled; Ihe 0,,1 seq"oll" Instructfon IS skipped If the AC has any bits which are no~ 0, If every bit In the AC IS 0, the next instruction IS executed SZA SNL SNA SZL' SMA 7460 7470 7500 10 10 10 SKIP ON ZERO ACCUMULATOR, ORSKIP ON NON'ZERO LINK, OR BOTH' SKIP ON NON"ZEROACCUMULATOR AND SKIP ON ZERO LINK SPA 7510 10 SKIP ,ON N1INUS ACCUMULATOR--':"/f the cor:tent of AC (0) contains a 1, indicatin9 that the AC contains a negative two's complement number, the next sequentJallnstruction IS skipped. If AC (OJ contamsa 0, the next instruction is executed. SKIPON POSITIVE ACCUMULATOR-The cooteotsol AC 101 ,,,sampled, H:AC 101 coot,lo;.O, indica.tin~ that the AC con.tains a positive two'scomplement number, the next sequential instruction is skipped. If AClOJ contains a '1, the next.inslruction IS executed. I . . , SMA SNL SPA SZL SMA SZA 7520 7530 7540 SPASNA 7550 )0 SMA SZA SNL SPA SNA SZL CLA LAS 7560 10 , 7600 7604 1,3 10 15 SKIP ON MINUS ACCUMULATOR OR SKIP ON NON-ZERO LINK OR BOTH SKIP ON POSITIVE ACCUMULATOR AND SKIP ON ZERO LINK SKIP ON MINUS ACCUMULAT()R OR SKIP ON ZERO ACCUMULATOR OR BOTH SKIP ON POSITIV'E ACCUMULATOR AND SKIP ON NON-ZERO ACCUMULATOR SKIP ON MiNUS ACCUMULATOR OR SKIP ON ZERO ACCUMULATOR OR SKIP ON NON-ZERO LINK OR A L L . . ' . SKIP ON POSITIVE ACCUMULATOR AND SKIP ON NON-ZERO ACCUMULATOR AND SKIP ON ZERO LINK CLEAR ACCUMULATOR-The AC Is lo,ded with bloa,), O's, . LOAD ACCUMULATOR WITH SWITCH REGISTER-Thecool~nI01theACISIO'dedWith'lhe SZA CLA SNA CLA SMA CLA SPA CLA 7640 7650 7700 7710 1,2 1,2 1,2 12 10 10 10 10 SKIP ON ZERO ACCUMULATOR THEN CLEAR ACCUMULATOR SKIP ON NON-ZEROACCUMULATOR THEN CLEAR ACCUMULATOR SKIP ON MlfljUS ACCUMULATOR THEN CLEAR ACCUMULATOR SKIP ON POSITIVE ACCUMULATOR THEN CLEAR ACCUMULATOR 1 r 1 7570 10 ..... 10 ,10 10 2 'content cif the SA, bit for bit. This is equivalent to a microprogrammed ,combination orelA and OSA. IM6100 INSTRUCTION SET (CONTINUED) IFETCH' OPR 28 OPR 2A STATES I I I LXMAR I I I I I I '11 I I I I I : I I I I I I I I I I I ~ I I~ I I I I II '". '.. IL-J· I ". . I Dxl.M~~ 00 ® . ® ' II . I .. . ., . Figure .7: OSR ..instruction Timing. GROUP 3 PJlICROINSTRU,CTIONS Figure a shows the instruction foriTlat of group 3 microinstructions which requires bits 3 and.11 to cOntain a i. 1;3 its 4. 5 , or 7 .may ~eset to, indicate a specific group 3. microinstr,,!c,- . 4 2. 0 '1 :1 5 : CL<MOA tion. If more than one ·of the bits is ·set; the instruction is a ' microprogrammed combination of group·3 microinstruc" tions follow,ing the logical sequ~ncelisted in Figure 8, All unused bits are "don't care" . 6' . 7 I >~O< 8 .. ,. : : 10 '9 11 1 "DON'T CARE LOGICAL SE~UENCES: 1'-:CLA 2..,.MOA. MOL 3-ALL OTHERS Figure 8: Group 3 Microinstruction Format Table V: Group 3 Operate Microinstructions NUMBER OF STATES MNEMONIC OCTAl,.· CODE "I,.OGICAI,. . SEQUENCE NO,? .MOL 7401 7421 3 2 10 10 MOA 7501 2 10 .". dPERATION NO OPERATION-see Group 1 MiCrOjn~tructions MQ· REGISTER LOAD-The content of,the AG is loaded into th~.MQ. the AC is cleared and the original content of the MO is lost. ' '. . MO REGISTER iNTO ACCUMULATOR-Theconlenlo'lheMo;sOR'ecw;lhlheconlenlo'lheAC and the result is loaded into the AC. The original content of the AC is lost but the original content of the MQ is retained. This inSI~uction pro~ides the programme~ with. an incl~siv~ q~ operation. SWP 7521 3 10 CLA CAM 7601 7621 1 3 10 10 ACL 7701 :3 10 . CLASWP 7721 3 10 SWAP ACCUMULATOR AND MO REGISTER-ToeconlenlciilheACand MOare;nlerchanged , accomplishing a microprogrammed combination of MQA,and Mal.' ' CLEAR ACCUMULATOR CLEAR ACCUMULATOR AND MO REGISTER-TheccinlenloflheACandMOar~loadedw;lh binary O's. This is equivalent to a microprogrammed combination of CLA and MOL CLEAR ACCUMULATOR AND LOAD MO F.lEGISTER INTO.ACCUMULATOR- This is equivalent to a microprogrammed combination of CLA and MQA. CLEAR ACCUMULATOR AND SWAP ACCUMULATOR AND MO REGISTER- The content of the AC is cleared. The content of the MQ is loaded into the AC and the MQ is cleared. IM6100 referred to as IFETCH and consists offive (5) internal states. The IM61 DD sequences the 10i' instruction through 2-cycle execute phase. referred to as IOTA and IOTa. Bits 0-11 of the lOT instructions are available on DXO-ll at IOTA. LXMAR; these bits must be'latched, in an external address register. DEVSEL is active low to enable data transfers between the IM61DD and the peripheral devicelsl. The selected peripheral device communicates with the IM61DD through 4 control , lines '- Co, Cl, C2 and SKP. In the IM61DD the type of data transfer, during an lOT instruction, is specified by the 'peripheral devicels) by asserting ,the control lines as shown in Table VI. INSTRUCTION SET (CONTINUED) a INPUT/OUTPUT (lOT) INSTRUCTIONS ., The input/output transfer instructions, which have an OPCODE of Sa are used to control the operation of peripheral devices and to transfer data between peripherals and the IM6100. Three types of data transfer may be used to receive or transmit information between the IM610D and one or more peripheral 110 devices: PROGRAMMED DATA TRANSFER, which provides a'straightforward means of communicating with relatively slow 1/0 devices, such as Teletypes, cassettes, card readers and CRT displays, .INTERRUPT TRANSFERS which use the interrupt system to service several 'peripheral devices simultaneously, 'and DIRECT MEMORY ACCESS, DMA, which transfers variable-size blocks of data between high-speed peripherals and memory without IM61DD intervention. lOT INSTRUCTION FORMAT, The Input/Output Transfer Instruction format is represented in Figure 9. The instruction executes ,in ,17 states. The first three bits, D-2, are always setto 68 (110) to specify an lOT instruction. The low order nine bits are used for device selection and control. PDP-8/e compatible interfaces use bits,3-8 for device selection and bits 9-11 for control of the selected device. The IM61Dl PIE interface uses bits. 3-7 fpr device selection and bits 8-11 for control. In user designed systems,' the 512 possible lOT i,nstructions may be alloted' according to the user's needs. The nature of:this operation for any given. lOT instruction depen,ds entirely upon the circuitrY designed into the 1/0 device interface. , The',controlline SKP, when low during an lOT, causes the IM61DD to skip the,next sequenHal instruction, This feature is used to sense the status of various signals in the devic,e interface. The Co, Cl, and C2 lines are treated independently of the SKP line. ,In the case of a RELATIVE or ABSOLUTE JUMP" the skip operation is performed after the jump. The input signals to the IM61DD, DXD-l1, Co, Cl, C2, and SKP, are sampled at IOTA duririg DEVSEL. XTc arid the data from the IM61DD is available to the devicels) during that time. IOTa is used by the IM61DD to perform the operations requested during IOTA. Both IOTA and lOTs consist of six (6) internal , , states.' .: ' In summary, Programmed Data Transfer.perf()rms data 1/0, with a minimum of hardware support. The maximum rate at which programmed data transfers may take place .is I,imited by thelMqlDd instruction execution rate, however, the datil rate of the lTiost commonly used peripheral devices is much lciwerthan the maximum rate at" which programmed transfers can take place in the IM61DD. The major drawback associated with Programmed Data Transfer is the IM610D must hang. up in a wl;liting loop while the 1/0 device completes the last transfer and prepares for the next transfer. On the otherhand,this technique permits easy hardware implementation and simple, economical interface design. For this reason, almost all devices except mass storage units rely on programmed data transfer. PROGRAMMED DATA TRANSFER. Programmed Data Transfer is the easiest, Simplest, most convenient and most common means' of perf<;irmirig "data' 110. For microprocessor applications, it may also be the most cost effective approach. The data transfer begins when the IM61DD fetches an instruction from the memory and recognizes that the current instruction is an lOT IFigure 10). This is 4' 3 I : I' 5 6 8 iEV,CE +LECTIO~ AND 9 10, ", 11 ~~NTRO~ Figure 9: lOT Instruction Format I , In ,LXMARjJ1 , I I" I ~ "fJ DXIO-llb <D ' , UI . I ~ ® m® _ _:' !~ @ ® G) INSTRUCTIO", ADDRESS, " ® IN~TRUcTION I, I I i ' ·" "I I MEMsEr~ DWsEi:1 I I ,I ®DEVICE ADDRESS.AND CONTROL', '@DEVICE,DATA IN, ~,Cl,.c2, SKP., , ,., . . '. , Figure 10:, Input-Output Instruction Timing @ACOUT O~OI6 IM6100 INSTRUCTION SET (CONTINUED) Table VI: Programmed I/O Control Lines CONTROL LINES Co Cl C2 H H H L H H H H L L H L L L H L OPERATION DESCRIPTION DEV<:-AC The content of the AC is sent to the device. DEV <:-AC; CLA The content of the AC is sent to a device and then the AC is cleared. AC <:-AC V DEV Data is received from a device, OR'ed with the data in the AC and the result is stored in the AC. AC<:-DEV 'Data is received from a device and loaded into the AC. PC<:-PC + DEV Data from the device is added to the contents of the PC. This is referred to as a RELATIVE JUMP. PC~DEV Data is received from a device and loaded into the PC. This is referred to as an ABSOLUTE JUMP. 'Don't Care INTERRUPT TRANSFER PROGRAM INTERRUPT TRANSFERS DEVICE INTERRUPT GRANT TIMING The program interrupt system may be used to initiate programmed data transfers in such a way that the time spent waiting for device I/O is greatly reduced or eliminated altogether. This is accomplished by isolating the I/O handling routines from the mainlini3 program and using the interrupt system to ensure that these routines are entered only when an I/O device status is set, indicating that the device is actually ready to perform a data transfer. The current contents of the Program Counter, PC, are deposited in location 00008 of the memoryand the program fetches the instruction from location 00018. The return address is available in location 00008. This address must be saved in a software stack, before the interrupts are reenabled, if nested interrupts are permitted. The INTGNT signal, Figure 11, is activated by the IM61 OO'when a device interrupt is acknowledged; this signal is reset by executing any lOT instruction as shown in Figure 12. The INTGNT signal is necessary to implement an External. Vectored Priority Interrupt network. The IM6101 PIE contains the logic necessary to implement both vectored and non-vectored interrupts. The inter(upt system allows certain' external conditions to interrupt the computer progr.am by driving the INTREQ input Low. If no higher priority requests are outstanding and the interrupt system is enabled, the IM6100 grants the device interrupt at the end of the current instruction. After an interrupt has been granted, the Interrupt Enable Flip-Flop in the IM6100 is reset so that no more interrupts are acknowledged until the interrupt system is re-enabled under program control. The user program controls the interrupt mechanism of the IM6100 by executing the processor lOT instructions listed in Table VII. Several of these interrupt lOT instructions are also used if the memory is extended beyond 4K words t6 save and restore extended memory status during interrupt servicing. IOTA 23451 I INTREQI 1 INTGNT I ! '. 5 1 . 1 l··· 234 5 I f I I _ I I I 1 I I ~ i ~} INTERNALI INT EN FFI IFETCH! L________ -'~ r. MEMSEL~- - - - - - - - STATES I tm%#'/@'/4f#@'$MM0f)f7&MW0"$J4 I' 1 1.\ LXMARI 234 i~ I . ® CD ADDRESS 00008 o ADDRESS ® 00018 ® DON'T CARE READ ® INSTRUCTION FETCH FROM 00018 ® PC WRITTEN .IN LOC 00008 OF MEM Figure 11: Device Interrupt Grant Timing IFETCH • LX MAR MEMSEL -----,~--_--~lr---------4 II-' : 1 I(i) I ,....,.---.. ,®<) I 1 ~L..-_ _~In '1· ;0 I .1 1 I i CD INSTRUCTION ADDRESS ®6XXX FROM MEMORY @ADDRESS 6XXX 1 I I "" . ®1 I ~r+-I- - - - - I I INTGNT 1 o I I ! j DATA TRANSFER FROM PERIPHERAL DEVICES AS CONTROLLED BY Co, C" AND C, @DATA TRANSFER.TO PERIPHERAL DEVICES AS CONTROLLED BY Co, C" AND C, . Figure 12: Device Interrupt Grant Reset Timing O~OI!" IM61 00 INSTRUCTION SET (CONTINUED) Table VII: Processor lOT Instructions MNEMONIC . OCTAL CODE SKON 6000 ION 6001 IOF 6002 SRQ GTF 6003 6004 RTF 6005 SGT CAF 6006 6007 OPERATION SKIP IF INTERRUPT ON· .c.. If interrupt system is enabled, the next sequential instruction is skipped. The Interrupt system is disabled. INTERRUPT TURN ON - The internal interrupt acknowledge system is enabled: The interrupt system is enabled after the CPU executes the n.ext sequential instruction. The INTERRUPT ENABLE TIMING is shown in Figure 13. INTERRUPT TURN OFF - The interrupt system is disabled. Note that the interrupt system is automatically disabled when the CPU acknowledges an INTrequest. SKIPIF INT REQUEST - The next sequential instruction is skipped if thelNTrequest bus is low. GET FLAGS- The following machine states are read into the indicated bits of AC. bit 0 - Link bit 2 - INT request bus bit 4 - Interrupt Enable FF Other bits may be modified by external devices by controlling the C-lines, (ex. Extended memory controll. RETURN FLAGS - Link is restored from AC (OJ. Interrupt system is enabled after the next sequential instruction is executed. All AC bits are available externally to restore external states. (ex. Extended memory controll. Operation is determined by external devices, if any. CLEAR ALL FLAGS - AC and Link are cleared. Interruot svstem is disabled. IFETCH ION EXECUTE JON EXECUTE IFETCH EXECUTE IFETCH 3 STATES 1 <D . IW . =======+~-:-;::===+= LXMAR~===J'~D3!t======t:II· @~ I I . MEMSELI DEVSEL· INTERNAL! INTENFFI~ wi I LJ ______ ~ ____ ID INSTRUCTION ADDRESS 12> .INSTRUCTION FETCH I __________________ @) ® I ________________ ~I ~ i3) DEVICE ADDRESS (60018) ~ ____________ ~ (l) INSTRUCTION FETCH <!!l SAMPLEREOUEST LINES (5) DON'T CARE DEV WRITE <ID INSTRUCT/ON ADDRESS ® DONT CARE DEV READ, SAMPLE CO, C1, C2 & SKP Figure 13: Interrupt Enable FF ON (ION) CONTROL PANEL INTERRUPT TRANSFER state forthe duration of the panel routine. The IM61 00 reverts to its original processor state after the panel routine has been executed'. The CPRECl does not affect the interrupt enable system, and the processor lOT instruction, ION is redefined and IOF is ignored while the IM6100 is in the Control Panel Mode. Once· a CPREQ is granted, the IM6100 will not recognize any DMAREQ or INTREQ until CPREQ has been fully serviced, The IM6100 supports a memory space completely separate from main memory, called control panel memory: Therefore, th'e IM61 00 control panel and other supervisory functions are implemented in software, Thisimplementation need not use any part of the main memory or change the processor state. This is an important feature, since the final version of the system may not have a control panel and the system designer would like to use the entire capacity of the main memory for the specific system application, When a CPREQ is granted, the PC is stored in location OOOOs of the Panel 'Memory and the IM6100 resumes operation at location 7777s. The Panel Memory would be organized with RAM'si.nthe lower pages and PROM's in the higherpages. The control panel service routine would be stored in the higher pages in the nonvolatile PROM's, starting at 7777s. The control panel communicates with the IM6100 with the Control Panel Request, CPREQ, line, The CPREQ is functionally similar. to the INTREQ with some important differences: The CPREQ is granted even when the machine is in the HAL Tstate;the IM6100 is temporarily, put in the RUN EXECUTE CPINT IFETCH. . . STATES . CPREO ~__~~""~""~~~""~""~""~""~~""~""~""~~~ INTERNAL I i CNTRL FF I IFETCH I LXMAR I . .. ... I . .. . j® ~'.' CPmr--------r y .. . ' --r::;CD. . 3 PC WR.ITTEN IN LaC 00008 OF CP MEM 4 ADDRESS 77778 I I. }I ~. . ~- - - : ~ ~ I ADDRESS 00008 ....... 2 DON'T CARE READ' . . I . i .. ... I I I 1 I . ® INSTRUCTION FETCHED FROM ® IFCPU IS HALTED, THE RUN IS LaC 77778 OF CP MEM TRUE AT T1 OF CPINT Figure 14: Control Panel Interrupt G.rant Timing IM6100 O~OIb INSTRUCTION SET (CONTINUED) A Control Panel Flip-Flop, CNTRL FF, internal to the IM610Q, is set. when the CPREQ is granted. The CNTRL FF prevents further CPREQ's from being granted. . ~When the CNTRL FF is set, the Control Panel Memory Select, . . CPSEL, is active rather than the Memory Select, MEMSEL, for memory references. The CPSEL signal may therefore be used to distinguish the Control Panel Memory from the Main Memory. However, during the Execute phase of .indirectly addre.ssed AND, TAD, ISZ or DCA instructions, the MEMSEL is made active. The instructions are always fetched from the control panel memory, and the operand .address for indirectly address AND, TAD, ISZ or DCA refers first to the control panel memory for an effective address, which, in turn, refers to a location in the main memory. A main memory location may therefore', be examined and changed by indirectly addressed TAD and DCA instructions, Figure 15, respectively. Every location in the main memory is accessible to the control panel routine. . • Exiting from the control panel routine is achieved by executing the following sequence with· reference made to Figure 16. ION· JMP I OOOOa (Loc 00008 in CPMEM) The ION, 60018, instruction will reset the CP FF after executing the next sequential instruction, but will not affect the interrupt system since the CNTRL FF is still active. Location OOOOs of the CPMEM contains either the original return address, deposited by the IM6100 when the CP routine was entered, or a new starting address defined by the CP routine, for example, by activating the LOAD ADDRESS SWITCH.CPREQ's are normally generated by the manual actuation of the control switches. If the CPU registers must be displayed in real-time, the CPREQ's must be generated by a timer at fixed intervals. The designe~ may, also make use of the control panel features to implement Bootstrap loaders in the CP Memory so that the loader will be "transparent" to the main memory. Programs will be loaded by DCA I POINTER instruction, the pointer being developed in the CP RAM to point to the main memory location to be loaded. Approximately 64 P/ROM locations are sufficient to implement all the functions of the PDP®-8/e Control Panel. The IM6100 provides for a 12-bit switch register which can be read by the IM6100 under program control with the SWITCH REGISTER,OSR, instruction even without a control panel. An RTF, 60058, instruction also resets the internal CNTRL FF. Exiting from a panel routine can be achieved by activating the RESET line since RESET has a higher priority than CPREQ, see Figure 18. If the RUN/HL T line is pulsed while the IM6100 is in the panel mode, it will 'remember' the pulses(s) but defer any action until the IM6100 exits from the panel mode. DCA EXECUTE I ~ __________ (j) INSTRUCTION ADDRESS @ INSTRUCTION FROM CP MEMORY @ EFFECTIVE ADDRESS @ OPERAND ADDRESS ~ i--...:.;.:...---.-+--....:..:...----+....., I _______ DATAF ~ CPSEL MEMSEL ® OPERAND.ADDRESS ® DON'T CARE MAIN MEM READ <V AC WRITTEN INTO MAIN MEMORY FROM CP MEMORY . Figure 15: "DCA Indirect" In Control Panel. Routine ION EXECUTE ION EXECUTE STATES 1 IFETCH 1~1 INDIRECT IFETCH ~ JMP EXECUTE n I LXMAR r'----~ ~--~....,-Ir-----.....,.I~--~I@~----.,.,...---~I . CPSEL ~ I I DEVSEL I~~~:~~~ I L-J 4 ' . .' ~ CD INSTRUCTION ADDRESS ® INSTRUCTION FETCH FROM CP MEM . ® DEVICE ADDRESS (60018) • I .Lill.J Us I I I Lill..J I II I II ® @ ® INSTRUCTION ADDRESS o . INSTRUCTION FETCH FROM CP MEM .@ DON'T CARE DEVICE READ, SAMPLE CO, C1, C2 & SKP ® EFFECTIVE ADDRESS (00008) ® JMP ADDRESS FROM CP MEM LOC 00008 ®DON'T CARE .DEVICEWRITE @lIF CP~ WAS IN THE HALT STATE, THE RUN IS FALSE AT T1 . Figure 16: "ION; JMP I OOOOa" In Control Panel Routine IM61 00 D~DIl. 'DIRECT MEMORY ACCESS. (DMA) Direct Memory Access, sometimes called data break, is the ,preferred form, of ,data tr~nsfer for u,sewithhigh-speed ,storage devices such asmagnEitic, disk or tape units. The DMA mechanism trarisfers ,data directly be:!tweenmemory and peripheral devices, arid the IM61DD is involved only'in setting up the transfer; the transfers take place ori' a "cycle stealing" basis. The DMA transfer rate is limited only by the bandwidth of the memory arid the data transfer chanicteristics of the device. ' ' ' " The devicegerierates a DMA Request when it is ready to transfer' data. The IM61 DDgrants the DMAREO by. activating . .. " .. \ the DMAGNT signal at the end of the'current instruction as shown in Figure 17. The,IM6100 suspends any further instruction fetches until theDMAREO line is reieased.The DX lines are tri-stated, al) SELlines are high, and the external timing Signals XTA, XTB, and XTc are active and LXMAR remains low. The device which generated the DMAREO must provide the a'ddress and the nec'essary control Signals to the memory for data tnlnsfers. The DMAREOline 'can also be used as a level sensitive' "pause" line. DMA may also bei~plemented in, a transparent mode without stealing processor cycles by using the DX bus , during idle periods. The IM61 D2 ¥EDIC operates in, this manner. DMA EXECUTE IFETCH STATES II! I II I ~ ~I--~---------1\CD DMAGNT fr./'-------~------_;II ,I 1 - 1_ _ _ _- . , . - . , .. . . . ,I I IFETCH 1 I,I\ 'I I 1 I 1 <D DMAREQ REMOVED AFTER DMAGNT Figure 17: Direct Memory AccessIDMAi INTERNAL PRIORITY STRUCTURE After an instruction is completely sequenced, the major state generator scans the internal priority network as, shoVo(n ,in Figure 18. The state oOhe priority n'etwork ,decides the next sequence of the:! IM61DD. The request lines, RESET, CPREO,RUN/HL'r, DMAREO and INTREO, are samp'led in the last cycle,of. an instruction execution, at time n.' The worst case response time of the IM61DD to an external request is; 'therefore:thetimei required to execute the longest instruction preceded by any 6-state execution cycle. For the IM6100, this is an autoindexed ISZ, 22 states, preceded by any 6-state execution cycle instructioo.' , When)helM6100 is initially p~wered up, tne state oftlie' , timing generator is undefined. The generator isautomaticalIy initialized with a maximum of 34 clock pulses. The request, inputs, as the IM61DD is powered on, must span at least 58 ' clock pulses to be recognized, 34,' clocks for the counter to initialize and a maximum of. two IM61DD cycles (20 to 24 clocks) for the state generator to sample the request lines. A , positive transition on RUN/HALT should occur at least 10 clock pulses after RESET for it to be recognized. The, interrial priority is RESET, CPR EO, RUN/HLT, DMAREO, INTREO, and IFETCH. ' IFETCH If no external ,requests ~re pendirg,ihe ,IM61C)D fetches the riext instruction pOinted to by the contents of the PC. The IFETCH line is active during the cycle in which the instruc~ , tion is fetched. External devi~es can monitor DX, 0-2, during I FETCH-XTA to determine the functional classof the current ,instruction. For example, the external memory extension hardware must know when JMP or JMS instructions are fetched to implement the E~tended Memory Control. The IM6102 does this to implement' extended memory addressing. The Programmable Logic Array, PLA, in the IM6100 sequences the IM61DO to e:!xecute the fetched instruction. All INDIRECT and ,AUTOINDEX Memory Reference Instructions 'go through a common state sequence' to generate the Effective Address, EA, of the operand. The subsequent sequence,referred to as the EXECUTE phase, is controlled by the functional class of the instruction. The EXECUTE phase of AND, TAD, DCA, JMS, JMP and OPR Group 3 Microinstructions consists of only one cycle. ISZ' and lOT have a 2-cycle EXEC,UTE phase. OPR Group 1 and Group 2 Microinstructions have an optional second cycle, depending on the microcoding of the OPRinstructions. An IM6100cycie consists bf 5 states, Tl, T2,T3, T4 and Ts, with an optiorial sixth state, Ts; for Output Transfers (WRITH The state sequence for internal (processor) and external lOT instructions are identical. The Device Address arid Control bits are available inthe Exterral Address RegisterJor internal lOT instructions. External hardware, for example Extended Memory,Control, can control the, C-lines for data transfers to implement Get Flags (GTF), ReturnFlags (RTF), arid Clear All Flags (CAF) instructions. External Control of the, C-lines is necessary to implement theseJnternallOT instructions since the flag bits may be distributed both inside and outside the IM61DD. IM6100 'PRIORITY SCAN PRIORITY EXECUTE INOIRECT/AUTO INDEX INSTRUCTION EXECUTE - PHASE A INSTRUCTION EXECUTE - PHASE B <DoNlY FOR ROTATES ® ONLY FOR OSR . Figure 18: Major Processor States and Number of Clock Cycles:in Each State . IM6100 O~OIl RESET continues to provide the external timing Signals XTA, XTB and XTc, all SEL lines are high, anq.the PC is set to 77778. In most applications, the higher memory locations utilize P/ROM's or ROM's. Therefore, a power-up routine starting at the highest memory location can be used to initialize the system. It is also possible to force entry into control panel memory Of) power-up. The Reset initializes all internallM6100 flags and clears the AC and the LINK. The machine is halted. As long as the RESET line is low, the IM6100 remains in the reset state and the OX lines are three stated. The IM6100 EXECUTE RESET RESET RESET I HALT 1 STATES I I I I I I I RESET (L) I I I I I I I I I I ! I 1/ ! ! I REQUESTS SAMPLED AT T1 OF THE FINAL EXECUTE PHASE 2 EXECUTE MAY BE 5/6 STATES 3 PC IS SET TO 77773 4 CPU HALTS Figure 19: Reset Timing RUN/HALT ipentical to the CONTINUE switch of the PDP-8/e control panel and the RUN signal is low. The RUN signal can be used to power down external circuitry for a low power system. The RUN/HL T can also be used to make the IM6l 00 execute one instruction at a time as shown in Figure 21. The RUN/HL T combines the functional features of STOP, CONTINUE, and SINGLE INSTRUCTION as defined by the PDP-8/e Control Panel. RUN/HL T changes the state of the IM6100's RUN/HL T flipflop. Pulsing the line low causes the IM6100 to alternately run and halt. The RUN/HLT line is. normally high. The IM6100 recognizes the positive transition of the signal.. The RUN/HL T flip~flop can be put in the halt state under program control by executing the HL T, 74028, instruction. When the IM6100 is halted, RUN/HL T is functionally RUN/HLT--------------~ ~ LJ\\ \ \ I / RUN INTERNAL------------------------RUN FF t: HALT f / RUN Figure 20: Run/Halt Timing HALT HALT RUNIHLT INTERNAL RUN FF IFETCH -----++------ '---!-_ _ _ _ _ III--J.,;~.:.....~,...-+....... HALT EXECUTE A - -+__.;;..._--l --!.....lJ....,_ _ _ RUN~I--------~~~-l~---------t----------~------~--------~ DMAGNT~I ________ ~--~GD~2~--~t---------~----------_+~--------~--------~ -1__~------~~---------1L-------------1------------L----------.J IFETCHLi__________ RUNIHLT PULSE FOR "SINGLE STEP" CD GD DMAGNT ON FOR 1 CYCLE FOR HALT TO RUN TRANSITION ® TRIGGER RUNIHLT WITH IFETCH o RUN FF SAMPLED IN THE LAST EXECUTE CYCLE Figure 21: "Single Step" With Run/Hit O~OI6 IM6100 WAIT The IM6100 samples the WAIT line during input-output data transfers (Figure 22l. The WAIT line, if low, controls the transfer duration. If WAIT is active during input transfers (READ), the CPU waits in the T2 state. For an output transfer (WRITE), WAIT controls the time for which the write data is maintained on the OX lines by extending the T6 state. The wait duration is an integral multiple of the oscillator time period - 250nsecat 4MHz.: . The WAIT mechanism is an ideal way of providing for slower memory and peripheral devices in the system without significant degradation in system performance. For example, if one waits for all reads and writes for one delay unit (250nsec at 4MHz), the system throughput is reduced by less than 3%. osc OUT , Ts tL 1(min) :::: "2 - tXT(min) + twH :::: 250 - 100 + 30 :::: 180nsec tL1{max) < TS - tXT(max) - tws < 500 - 250 - 30 < 220nsec Note that the delay circuit can be as simple as an R-C network in conjunction with CMOS logic. Note.also that the WAIT can be made selective on main memory, device, control panel memory or switch register select line. 1-4------tL3------~ STATES MEM/DEVlCP/SWSEL XTA _ _ _......""! Figure 24: Write Transfer Wait Circuit XIS XTC WAIT::::::::JE~::::::::::::::JE~::: Figure 22: Wait Line Samplirg Timing ~----1L2 ----~ ~ XTA. -~D::"~Y..... 1-oo~t-------tL1-_-------i1>j Figure 24 shows a logic implementation to wait during . WRITE's only. The rising edge of MEMSEL (or CPSEL or DEVSEU during READ clocks in a zero on the WAIT line. XTB, after a delay, releases the WAIT line. Every WRITE pulse is preceded by a READ pulse, and if no write operat{on is performed in acycle, the T6 state is not entered and the WAIT line is not sampled. For x units of delay, the following conditions must be met: TS txT(min) + tL3(min) - tWH :::: x _ and 2 Figure 23: Memory And Input Transfer Wait Circuit The circuit shown in Figure 23 will make the IM6100 wait during main memory and device input (READ) transfers. MEMSEL or DEVSEL, being low, will assertWAIT low. When XTA becomes active high, the WAIT line is asserted high after a delay. The wait duration is controlled by the delay in the XTA-WAIT path (tll). The following conditions must be satisfied to obtain x units of delay during READ's: tSL(max) + tL2(max) + tws < T s Ts 2 In the circuit shown in Figure 25, the WAIT signal is normally asserted low. and it is released by XTA during READ's and XTB during WRITE's. Note that WAIT is active for all data transfers. Since XTA and XTBhave identical timing relative to the WAIT sample pOint;the constraints to be satisfied are as follows: tXT(min) + tL4(min) - tWH :::: x Ts and 2 tXT(min) + tL 1(min) - tWH :::: x ~ 2 tXT(max) + tL 1(max) + tws < (X + 1) lxT(max) + tL3(max)+ tws< (x + 1) tXT(max) +tL4(r;'aX)'+ tws < (x + 1) Ts 2 ~s 1 + - - - - - 1L4 -----+1 For example, for an IM6100 I device operating at 4MHz, 5.0V and 25° C, the constraints to be met to obtain 1 unit of delay (250nsec) are as follows: tL2(max) < Ts - tSL(max) - tws <500-300-30 < 170nsec Figure 25: Data Transfer Wait Circuit· O~DIL IM61 00 IM6100 ABSOLUTE MAXIMUM RATINGS Operating Temperature IndustriallM6100 ..................... -45°C to +85°C Storage Temperature ................ -65°C to +150°C Operating Voltage ...............•..... +4.0V to +11.0V Supply Voltage ................................ +12.0V Voltage On Any Input or Output Pin .... 1 ....•. , ............ -o.3V to Vee +O.3V NOTE: Stresses above those listed under '''Absolute Maximum Ratings" may cause permanent device. failure. These· are stress ratings only and functional operation of the devicesat these or any 'other conditions above those indicated· in the operation sections of this specification is not implied. Exposure to .absolute maximum rating conditions for extended periods may cause device failures. D.C. CHARACTERISTICS TEST CONDITIONS: Vee =' 5.0V ±10%, TA ~ -40°C to +85°C 1 2 3 4 5 6 7 8 9 10 PARAMETER Input VoltaQe HiQh Input Voltage Low Input Leakage Output Voltage High Output Voltage"Low .Output Leakage Power Supply Current-Standby Power Supply..:Current-Dynamic Input Capacitance Output Capacita~ce SYMBOL VIH Vil ill . VOH VOL 'IOl Ice Ice CIN. Co CONDITIONS MIN Vee-2.0 GND < VIN < Vee IOH =-D.2mA IOl = 2.0mA GND ::;. VOUT ::;. Vee 'VIN - GND or Vee fe = 2.5MHz -1.0 2.4 . TYP MAX O.B i.o 0.45 1.0 800 1.8 8.0 10.0 -1.0 7.0 8.0 UNITS V V uA V V ./I. A uA mA pF pF A.C. CHARACTERISTICS ISeeFigure 2 and 22) TEST CONDITIONS: Vee =' 5.0V ±10% , CL = 50pF, TA -40°C to +85°C, fe = 2.5MHz 1 2 3 4 5 8 6 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SYMBOL FREQ ts ILXMAR tAS tAH tENO IAl tEN twp twllO tos tOH toso tOHO tSl txT 1sT .' tRS IRH tRHP tws twH .. I, PARAMETER Operating Frequency Major State Time LX MAR Pulse Width Address Setup Time: DX-LXMAR 1+) Address Hold Time: LXMAR I+)-DX Data Output Enable Time: DEVSEL I+)-DX Access Time .from LXMAR Output Enable Time IMEM, CP,DEVSEU Pulse Width IMEMSEL, CPSEU Pulse Width IDEVSEU . Data Setup Time IDX- t MEMSEL/CPSEU Data Hold Time It MEMSEL/CPSEL-DX) Data Setup Time IDX-t DEVSEU Data Hold Time It DEVSEL-DX) Logic Delay to MEM/DEV/CP/SWSEL Logic Delay to LX MAR, XT A, XTB, XTC Logic Delay to DATAF, RUN, DMAGNT, INTGNT, LINK, IFETCH Set up Time for CPIINT/DMAREQ Hold Time forCP/lNT/DMAREQ, RESET, RUN"HALT RUN-HALT Pulse.Width Set up Time for Wait Hold Time for Wait MIN TYP MAX 2.5 800 335 120 175 575 650 . . 400 320 320 240 175 275 175 75 65 0 300 110 100 35 Note: For capacitance greater than 50pF, the AC.parameters will have a delay factor of 0.5ns/pF. 440 380 475 UNITS MHz ns· ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns IM61 00 IM6100-1 ABSOLUTE MAXIMUM RATINGS Operating Temperature IndustriallM6100-11 ......' ............ -40°C to +85°C Storage Temperature ................ -65°C to +150°C Operating Voltage .................. , .. +4.0V to +11.0V Supply Voltage .......................... ... . .. +12.0V Voltage On Any Input or ' Output Pin ....................... -D.3V to Vee +0.3V NOTE: Stresses above those listed under ,,"Absolute, Maximum Ratings" may cause permanent device, ,failure. These are str,ess ratings only and functional operat'ion of the devices at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating, conditions for extended periods may cause device failures. D.C. CHARACTERISTICS TEST CONDITIONS: Vee = 5.0V ±10%, TA = -40°C to +85°C SYMBOL 1 2 VIH VIL 3 IlL PARAMETER Input Voltage High Input Voltage Low Inp'ut Leakage 4 VOH Output Voltage High 5 VOL Output Voltage Low 6 10L Output Leakage 7 8 lee lee 9 10 CIN' Co CONDITIONS MIN TYP GND "'" VIN < Vee 10H '= '-O.2mA 10L = 2.0mA -1.0 GND "'" VOUT < Vee VIN = GND or Vee fe= 3.33MHz -1.0 , PowerSupply Current-Standby Power 13upply Current-Dynamic Input Capacitance 0.8 UNITS V V 1.0 jJ.A 2.4 V 7.0. ' Output Capacitance A.C. CHARACTERISTICS MAX Vee -2.0 8.0 0.45 V 1.0 jJ.A 800 2.0 jJ.A mA 8.0 10.0 pF pF IRef. Fig. 2 and 221 TEST CONDITIONS: Vee = 5.0V ± 10%, CL = 50pF, TA = -40°C to +85°C, Ie = 3.33MHz SYMBOL 1 PARAMETER FREO Operating Frequency MIN TYP MAX 3:33, UNITS MHz ns 600 260 2 ts Major State Time 3 4 tLXMAR LXMAR Pulse Width tAS 5 8 tAH tENO Address Setup Time: DX-LXMAR III .; Address Hold Time: LXMAR III-DX 6 tAL Access Time from LXMAR 7 tEN twp Output Enable Time IMEM, CP, DEVSELI Pulse Width (MEMSEL, CPSELI 235 Pulse Width IDEVSELI 235 ns 11 12 twPD tDS tDH Data Setup Time IDX-I MEMSEL/CPSELI Data Hold Time II MEMSEL/CPSEL-DXI 135 125 ns 13 tDSD Data Setup Time IDX-t DEVSELI 225 ns 14 tDHD 125 ns 15 tSL Data Hold Time It DEVSEL-DXI Logic Delay to MEM/DEV/CP/SWSEL 75 380 ns 16 tXT 65 270 17 18 tST tRS Logic Delay to LXMAR, XT A, XTB, XTC Logic Delay to DATAF, RUN, DMAGNT, .. INTGNT, LINK, IFETCH ns ' ns Set up Time for CP/INT/DMAREQ 19 tRH Hold Time for CP/INT/DMAREQ, RESET, RUN-HALT 20 21 tRHP RUN-HALT Pulse Width 200 80, tws Set up Timefor Wait 100 ns 22 twH Hold Time for Wait 20 ns 9 10 ns 85 ns 125 ns Data Output Enable Time: DEVSEL I<I-DX 470 520 ns ns 300 ns ns ns 340 0 Note: For capacitance greater than 50pF, the AC parameters will have a delay factor of 0.5ns/pF. ns ns ns O~OIL IM6100 IM6100A ABSOLUTE MAXIMUM RATINGS Operating Temperature, IndustriallM6l00AI ~ ... ; ........ '; '.... -40°C to +85°C Storage Temperature·',' .. : ........ 455°C to'+150"C Operating Voltage .. :., ..... : .......... '+4:0V W+ll.0V Supply Voitage ... ",:.; .... '........, ........,'..... +12.0V Voltage On Ariy Input or Output Pin ..... :. '........ : ....... -D.3V to Vee +O.3V NOTE: Stresses, above those listed under "Absolute Maximum Ratings" may cause permanent device failure. These are stress ratings only and functional operation 'olthe devices at these or any other conditions above those indicated in the operation sections of this specification. is, not implied. Exposure to absolute maximum, rating' conditions for extended periods may cause device 'failures. >.' D.C. CHARACTERISTICS TEST CONDITIONS: Vee = 10V ±5%, TA = -40°C to +85°C ',' 1 2 3 4 5 6 7 8 9, 10 SYMB6L VIH VII: ilL PARAMETER' Input Voltage High Inpui.Voltage Low '. Input Leakage Output Voltage High Output Voltage Low Output Leakage Power Supply Cu'rrent-Standby power Supply Current-Dynamic Input Capacitance Output Capacitance ' VOH VOL 10L Icc 'Icc CIN Co CONDITIONS MIN ' 70% Vee GND< VIN < Vee' 10H =' O.OinA 10L =O,OmA GND :5; Your < Vee V!f,j:'" GND or'Vee, fe=5,71MHz A.C.CHARACTERISTICS (Ref: 'Figures 2 and 22) TYP MAX V -1:0 Vee -{l.01 " V 1.0 p.A GND +0.01 1.0 900 4.0 8.0 10.0 ,':, " ~1.0 ", -" 20% Vee V " '7.0, 8,0 " UNITS V p.A ' uA inA pF pF ' . TEST CONDlTlbNS: Vee'= 10V ±5%, GL = 50pF, TA = -40°C to +85°C,fe =,5:71MHz . 1 2' 3 4 5 8 6 7 ,9 10 11 12 13 14. 15 16 17 18 19 20 21 22 SYMBOL FREQ Is tLXMAR lAs IAH tEND IAL tEN twp twpo tos tOH toso tOHO IsL tXT 1sT tRS tRH tRHP tws twH PARAMETER MIN Operating Frequency Major State Time 350 : LXMAR Pulse Width '150 ,'55 ' Address Setup Time: DX-LXMAR I~) , Address Hold lime: LXMAR II)-DX 60 Data Output Enable Time: DEVSEL II)-DX Access Time from LXMAR Output Enable Time IMEM, CP, DEVSEU ,140 Pulse Width IMEMSEL, CPSEU 140 Pulse Width IDEVSEU Data Setup Tirne (DX- t MEMSELlCPSEU 115 :", ' 60 Data Hold Time I t MEMSELlCPSEL-DX) 110 Data Setup Time IDX- t DEVS,EU ",' Data Hold Time It DEVSEL-DX) 60 ' , LOQic Delav t6 MEM/DEVlCP/SWSEL 35 .. Logic Delay to LXMAR, Xi'A, XTS, XTe 35 , Logic Delay to DATAF, RUN, DMAGNT, INTGNT, LINK, IFETCH , Set up Time for CP/INT/DMAREQ 0 " " Hold Time for CP/INTIDMJI,REQ, RESE;T, ~l,JN-HALT ,1.25 RUN-HALT Pulse Width 45 Set up Time for Wait 45 15 Hold Time for Wait TYP :', MAX 5.71 " ' . .. 250 2,95 185 " n'S " - ' " " " Note: For capacitance greater than 50pF, the AC parameters will have a' delay factor of 0.5ns/pF. " UNITS MHz ns ns ns ris ns ns ns " ' " 180 155 ' 190 ' ns ns, ns ns ns ns ns ns ri s ,ns,. I)S ns: ns IM6100 IMS100-1M (Military) ABSOLUTE MAXIMUM RATINGS Operating Temperature , Industrial IM6100-1M ...•........... -55°C to +125°C Storage Temperature ......... ; ...... -65°C to +150°C Operating Voltage ........... , ....... ',,' +4.0V to +11.0V Supply Voltage .............................. ," .. +12.0V Voltage On Any Input or Output Pin ..................... ,' .. -o.3\l to Vee +0.3V NOTE: Stresses above those listed under "Absolute MaximulT1 Ratings" may cause permanent device failure. These are stress ratings only and functional operation of the devicesat thes~ or,'any other conditions above those 'indicated in the OPElri3tion sections of this specification is not implied, Exposure to absolute maximum rating conditions for extended periods may cause device failures. D.C.' CHAR'ACTERISTICS ' TEST CONDITIONS:Yee =,5V± 10%, TA=-55°q to +125°C 1 2 3 4, 5, 6 7 8 9 10 SYMBOL VIH VIL ilL VOH VOL , 10L Icc Icc CIN Co PARAMETER Input Voltage High ' Input Voltage Low , Input LeakaQe " OutP\lt Voltage High Output Voltage Low Output Leakage Power Supply Current-Standby:, Power Supply Curre'nt-bynamic Input Capacitance Output Capacitance CONDITIONS MIN Vee -2,0 GND < VIN < Vee 'IOH:= -O,2mA 10L. =2.0mA GND < VOUT < Vee VIN = GND, or Vee fe = 2,5MHz TYP MAX UNITS' V V uA V V A pA mA pF ' pF . -1.0 2:4 ' 0.8 1,0 , 0.45 1.0 800 2,d -1,0 7.0 8,0 8.0 10.0 A.C. CHARACTERISTICS (ReI. Fig, 2 and 221 TEST CONDITIONS: Vee = 5.0V±10%; CL,= 50pF, TA= -55°Gto +125°C,fe = 2.5MHz " 1 2 3 " 4 5 8 6 7' 9 10 11 12 13 14 15 16 17 18 19 20 21 22 'SYMBOL FREQ ts tLXMAR tAs tAH tENo ., IAL tEN , , twp ,twpo tos tOH ,toso tOHO "tsl tXT " 1sT tRS tRH IRHP tws twH PARAMETER, Operating Frequency ' Major State'Time' , MIN TYP" 'MAX " 2,5 " 655 745 '470 " LXMAR Pulse Width " .. Address Setup Time: DX-LXMAR ('I Address Hold Time:: LXMAR W-DX Data Output Enable Time: DEVSEL ('I-OX Access Time from LXMAR Output EnableTimEr (MEM, CP, DEVSELI. Pulse Width (MEMSEL, CPSELI ' Pulse Width (DEVSELI '" Data Setup'Time (DX- t MEMSEL/CPSELI , ' Data Hold Time ( t MEMSELlCPSEL-DXI ., ,Data Setup Time (DX- t DEVSELI Data HoldTime( t DEVSEL-DXI' \ Logic Delay to MEM/DEV/CP/SWSEL Logic Delay to LXMAR; XTA, XTB; XTC ", Logic Delay to,DATAF, RUN, DMAGNT, INTGNT, LINK, IFETCH Set up Time for, CPIIl\iTIDMAREQ Hold Time for CP/INT/DMAREQ, RESET, RUN-HALT RUN-HALT Pulse Width Set up Time for Wait Hold Time for Wait ' .' UNITS MHz ns' ' ns ,ns .. ' 800 ,355 200 175 ns ns , ns' 'ns' 'ns ns . ns 330' :. ~30 250 170 350 170 75 ,65 " ' , .. ' 420 300 375 0 220 90 110 20 Note: For capacitance of greater than 50pF, the AC parameters all have delay factor of 0.5ns/pF. ns ns ns ns ns ns, ns ns ns ns ns O~OI!" IM6100 IM6100AM (Military) ABSOLUTE MAXIMUM RATINGS Operating Temperature Industrial IM61,o,oAM ............ : .. -55°C to+125°C Storage Temperature ..... , ........ ,. --65°C to +15,0° C Operating Voltage .,. ... : ... : ...... ,...... +4.0V,to +11.,oV Supply Voltage ..........•...•..•.. , ........... ,.+12.,oV Voltage On Any Input or Output Pin ..... : ................. -D.3V to Vee +,o.3V NOTE: Stresses above those listed under "Absolute Maximum 'Ratings"'may cause permanent device failure. These are stress ratings only and functional operation ofthedevicesat these or any other conditions above those indicated inthe operation sections of this specification is not implied. Exposure to absolute maximum rating -conditions for extended periods may cause device failures. D.C. CHARACTERISTICS TEST CONDITIONS: Vee = 1,oV ±5%, TA = -55°C to +125°C SYMBOL 1 VIH PARAMETER CONDITIONS Input Voltage Hi!:Jh 2 VIL Input Voltage Low 3 4 IlL VOH Input Leakag\; Output Voltage High 5 VOL 6 MIN . MAX -'1'.0 Vee -0.01 Output Voltage Low GND ::; VIN< Vee 10H =O.OmA 10L ='O.OmA 10L Output Leakage GND ::; VOUT ::; Vee -1.0 7 lee lee CIN Co Power Supply Current-StandbY Power Supply Current-Dynamic VIN ~ GND or Vee 8 9 10 TYP 70% Vee '20% Vee' V 1.0 JlA V GND +0.01 1.0 900 fe=.5.0MHz Input Capacitance Output Capacitance 4.0 8.0 10.0 ,7.0 .8.0 ' • UNITS V V JlA uA mA pF pF . A.C. CHARACTERISTICS IRef. Figures 2 and 221 TEST CONDITIONS: Vee = 1,oV ± 5%, CL =5,opF, TA = -55°C to +125°C, fc = 5.,oMHz SYMBOL FREO Operating Frequency MIN TYP MAX 5.0 UNITS MHz 2 ts Major State Time 400 ns 3 tLxMAR LXMAR Pulse Width 170 nS 4 tAS Address Setup Time: DX-LMAR I~I 70 tAH tENO . tAL · Address Hold Time: LXMAR I~)"DX ns ns' Data Output Enable Time: DEVSEL I*)-DX 290 ns Access Time from LXMAR 340 ns tEN twp _ twpo Output Enable Time IMEM, CP, DEVSEU· ·220 ns 5 8 6 7· '. PARAMETER 1 9 10 11 tos 12 tOH 13 toso 14 tOHO 15 tSL tXT 16 17 tST ' .. 70 . Pulse Width IMEMSEL, CPSEU 160 160 . Pulse Width IDEVSEU Data Setup Time IDX- t MEMSEL/CPSEU Data Hold Time It MEMSEL/CPSEL-DX) ns ns· ns 'ns 140 70 140 Data Setup Time IDX- t DEVSEU .Data Hold Time 1+ DEVSEL-DX) ns 70 ' 35 210 ns Logic Delay to LXMAR, XTA. XTB, XTC · Logic Delay to DATAF;RUN, DMAGNT; INTGNT, LlNK,IFETCH 35 '/ 170 ns ns Setup Time for CP/INT/DMAREO '" Hold Time for CP/INT/DMAREO, RESET, RUN-HALT 0 ns 140 ns ns · Logic Delay to MEM/DEV/CP/SWSEL 18 tRS 19 tRH 20 tRHP RUN-HALT Pulse Width 21 tws Set up Time for Wait·· 22 twH Hold Time for Wait " .... 210 50 .. '. ns 50 ns 20 ns Note: For capacitance of greater than 50pF; theAC parameters will have a delay factor of O.5ns/pF.
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