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XX-532CB-89
2000
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HM-61
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XX-532CB-89
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21
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http://bitsavers.org/pdf/dec/pdp8/cmos8/_dataSheets/HM-6100.pdf
OCR Text
HM-6100 mJHARRIS CMOS 12 BIT MICROPROCESSOR (CPU) Features • • Pinout LOWPOWER-TYP.<5.0pW SINGLE +5V POWER SUPPLY • FULL TEMPERATURE RANGE -55°C TO +125OC • • STATIC OPERATION SINGLE PHASE CLOCK, ON CHIP CRYSTAL OSC. • SOFTWARE COMPATIBLE WITH PDP-8/E • • 12-BIT DATA WORD OVER 90 SINGLE WORD INSTRUCTIONS • RELOCATABLE MEMORY ORGANIZATION • BASIC ADDRESSING TO 4K 12 BIT WORDS • PROVISION FOR DEDICATED CONTROL PANEL • 128 GENERAL PURPOSE REGISTERS • 8 AUTO INDEXING REGISTERS • FLEXIBLE PROGRAMMED 1/0 TRANSFERS • VECTORED INTERRUPT CAPABILITY Description The HM-6100 is a single address, fixed word length, parallel transfer microprocessor using 12-bit two's complement arithmetic. It is a general purpose processor which recognizes the instruction set of Digital Equipment Corporation's PDP-8/E Minicomputer. Standard features include indirect addressing and facilities for instruction skipping, program interrupts as a function of input/output device conditions, and auto-restart. Five 12-bit registers are used to control ':1icroprocessor operations, address memory, perform arithmetic or logical operations, and store data. The device design is optimized to minimize the number of external components required for interfacing with standard memory and peripheral devices. Functional Diagram Vee GND INTERRUPT CONTROL INSTRUCTION DECODER, TIMING AND CONTROL UNIT VCC RUN DMAGNT DMAREO CPREQ RUN/Rtf RESET INTREQ XTA LXMAR WAIT XTS XTC OSC OUT OSCIN DXO DX1 DX2 DX3 DX4 DATAF INTGNT CJ5SIT MEMSEL IFETCH SKP C2 C1 CO SWSIT DEVSEL LINK DX11 DX10 GND DX9 DX8 DX7 DX6 DX5 Specifications HM-6100 ABSOLUTE MAXIMUM RATINGS -O.3V to +8.0V (GND - 0.3V) to (vee +0.3V) -650 e to 1500 e Supply Voltage (Vee - GND) Input or Output Voltage Applied Storage Temperature Range Operating Temperature Range Industrial HM-61 00-9 Military HM-61 00-2 vee ~ 5.0 ± 10% Volts. T A ~ Industrial or Military ELECTRICAL CHARACTERISTICS SYMBOL D.C. PARAMETER MIN TYP MAX UNITS VIH Logical "1"' Input Voltage 70% vcc V VIHC Logical "1" Osc.1 nput Voltage VCC-.5 V VIL Logical "'0" Input Voltage 20% VCC V VILC Logical "'0"' Osc.lnputVoltage GND +.5 V +1.0 /lA IlL Input Leakage (1) -1.0 VOH Logical "'1"' Output Volt. (2) 2.4 VOL Logical "'0"' Output Volt. (2) TEST CONDITIONS OV~VIN~VCC V 10H = -0.2mA 0.45 V 10L= 2.0mA 10 Output Leakage +1.0 /lA OV~VO~VCC ICC1 Supply Current (Static) 400 I1A VIN = VCC, Freq. = 0 ICC2 Supply Current (Operating) 2.5 mA VCC=5.5V, Freq=2.0MHz CI Input Capacitance (3) 5 7 pF 10 pF 10 pF -1.0 CO Output Capacitance (3) CIO I nputlOutput Capacitance (3) 8 8 COSC Oscillator INIOUT CAP. (3) 30 Notes: (1) (2) (3) pF Except pin 14 and 15 Except pin 14 Guaranteed and sampled, but not 100% tested. TA = Military TA = 250 C TA = Indust. VCC=5.0V VCC= VCC= (1) 5.0 ±.10%V 5.0±.10%V MIN MIN SYMBOL PARAMETER MIN fMAX Max Operating Frequency Major State Time 500 600 800 TLX LXMAR Pulse Width 220 230 355 ns TAS Address Setup Time 80 85 200 ns TAH Address Hold Time 150 125 175 TAL Access Time from LXMAR 450 520 745 ns TEN Output Enable (Memory) 250 300 470 ns TEND Output Enable (1/0) 300 470 655 ns TWP Write Pulse Width 200 235 330 ns TDS Data Setup (Memory) 160 135 250 ns TDSD Data Setup (1/0) 185 225 350 ns TDH Data Hold Time 125 125 170 TST Status Signals Valid TRS Request Inputs Setup 0 0 0 ns TRH Request I nputs Hold 200 250 300 ns TWS Wait Setup Time 0 50 50 ns TWH Wait Hold Time 100 100 150 ns TRHS Run Halt Setup Time a 50 50 ns TRHP Run Halt Pulse Width 100 100 150 ns TS A.C. -400e to +850e -55 0 e to + 1250 e NOTE 1: MAX 4.0 MAX 3.33 250 300 MAX UNITS 2.5 MHz CL = 50pF ns See Timing Diagram ns ns 325 ns All devices guaranteed at worst case limits. Room temperature, 5V data provided for information - not guaranteed. TEST CONDITIONS Specifications HM-6100C-9 ABSOLUTE MAXIMUM RATINGS Supply Voltage Input or Output Voltage Applied Storage Temperature Range Operating Temperature Range Industrial H M-61 00e-9 ELECTRICAL CHARACTERISTICS D.C. -4ooe to +850e vee = 5.0 ± 5% Volts, T A = Industrial PARAMETER SYMBOL 8.0V Gnd -0.3V to vee +0.3V -65 0e to 1500e MIN VIH Logical" 1" I nput Voltage 70% VCC VIHC Logical "1" Osc.lnputVoltage VCC-.5 VIL Logical "0" Input Voltage VILC Logical "0" Osc.lnputVoltage TYP MAX ilL Input Laakage (1) -10 Logical "1" Output Volt. (2) 2.4 VOL Logical "0" Output Volt. 12) TEST CONDITIONS V V .8 GND +.5 VOH UNITS V V +10 J.1.A V OV~VIN~VCC 0.45 V IOL-1.6mA 10H = -D.2mA 10 Output Leakage +10 J.1.A OV~VO~VCC ICC1 Supply Current (Static) 600 VIN =VCC, Freq. = ICC2 Supply Current (Operating) 5.0 J.1.A mA -10 CI Input Capacitance (3) 5 7 pF CO Output Capacitance (3) 10 pF 10 pF CIO Input/Output Capacitance (3) 8 8 COSC Oscillator I N/OUT CAP. (3) 30 Notes: (1) (2) (3) pF Exceptpin14and16 Except pin 14 Guaranteed and samplad, but not 100% tested. TA = 250 C TA = Indust. VCC=5.0V(1) VCC = 5.0:!:5% SYMBOL A.C. PARAMETER MIN MAX MIN MAX UNIT TEST CONDITION 2.5 fMAX Max operating Freq. MHz CL = 50pF TS Major State Time 600 800 ns See Timing Diagram TLX LXMAR Pulse Width 270 335 ns ns 3.33 TAS Address Setup Time 100 120 TAH Address Hold Time 150 175 TAL Access Time from LXMAR 500 650 ns TEN Output Enable (Memory) 300 400 ns TEND Output Enable (I/O) 350 575 ns TWP Write Pulse Width 250 320 ns TDS Data Setup (Memory) 180 240 ns TDSD Data Setup (I/O) 200 275 ns TDH Data Hold Time 130 175 TST Status Signals Valid TRS Request Inputs Setup 0 0 TRH Request Inputs Hold 100 130 ns TWS Wait Setup Time 0 0 ns 300 ns ns 350 ns ns TWH Wait Hold Time 100 130 ns TRHS Run Halt Setup Time 0 70 ns TRHP Run Halt Pulse Width 100 130 ns Note 1: All devices guaranteed at worst case limits. Room temperature, 5V data provided for information - not guaranteed. a VCC=5.5V, Freq=2.0MHz Timing lind StlltB Control The HM-S100 generates all the timing and state signals internally. A crystal is used to control the CPU operating frequency. The CPU divides the crystal frequency by two. With a 4MHz crystal, the internal states will be of 500ns duration. The major timing states are described in Figure 1. T1 For memory reference instructions, a 12-bit address is sent on the DataX, DX, lines. The Load External Address Register, LXMAR, is used to clock an external register to store the address information externally, if required. When executing an Input-Output I/O instruction, the instruction being executed is sent on the DX lines to be stored externally. The external address register then contains the device address and control information. Various CPU request lines are priority sampled if the next cycle is an Instruction Fetch cycle. Current state of the CPU is available externally. Memory/Peripheral data is read for an input transfer (READ). WAii' controls the transfer duration. If T2 WAi'i' is active during input transfers, the CPU waits in the T2 state. The wait duration is an integral multiple of the crystal frequency - 250ns for 4MHz. For Memory reference instructions, the Memory Select, MEMSEL, lines are active. For I/O instruction the iJEilSEI, line is active. Control lines, therefore, distinguish the contents of the external register as memory or device address. External device sense lines CO, Cl, instruction. a, and SKP are sampled if the instruction being executed is an I/O swm, Control Panel Memory Select, CPSEL, and Switch Register Select, become active low for data transfers between the HM-Sl00 and Control Panel Memory and the Switch Register, respectively. T3,T4,T5 ALU operation and internal register transfers. This state is entered for an output transfer (WRITE). The address is defined during Tl. WAiT controls the time for which the WR ITE data must be maintained. TS The following illustrates the timing of the CPU when its operating frequency is low enough that propagation delays can be ignored. It effectively shows the timing of the CPU when it is single clocked. Ole OUT T..aTAUI LXMA" In'-+----;.I_-i-_:----+-'nL....:_--.:...._..:..-----.:..__I~___:_1_ 1 ~~I~ ~~~~~--~--~II~II rTll. . --:-__:--_-:-_-:--. . . XTA ":-_-:-. . . . XTI XTCj I I I I ~I DXlo-", 1 ADD --. 1 I !---:---~-~~-~,---,!----:--___:--_:_-~ I I I I 1 @"EAD~A I rr- ADD 1 M"EAD~~AW"'TEDATAW I. 1 1 1 1 I I I I I I I I I I I I I I I I I .~ c//////////IIW//$/////W////IWZ///hJVALlDW/////W&////A//////WI/ I v: FIGURE 1 - Static Timing The dynamic or high frequency timing illustrates the propagation delays at specified operating frequencies. (Refer to specifications) It defines the interface requirements for memory and I/O devices on the bus. OSCOUT STATES LXMAR XTA __~____~~~~ I 6\~________________________~--~----_ XTB~r----~~~4____~______________________--Jo/r~------ .: i '"'~--"'0~""/ ~*~_H \_7':.-=- =- =- =- =- =- =- =- =- =- =- =- =- =- =-~TWS.:.- :. ~rn-iI-:=TW~H-:"'1 ___ I -=:I-l~t--TS--T REQ- sTATus::)[______ RUNTHIT I I ~------~+I~~--------------------------~--~x:::: TRHP~~T~R~H=S----------------------------~-------- HI FIGURE 2 - Dynamic Timing Microprocessor Architecture The block diagram of the CPU architecture, shown on the front page, consists of the following major functional segments: • • • • CPU Registers Arithmetic and Logic Unit Ox-Bus Multiplexer Timing and Control Unit Each one is briefly described below. CPU REGISTERS The CPU consists of five, 12-bit registers, of which three are user programmable; 1) Accumulator (AC), 2) Program Counter (PC), and 3) Multiply Ouotient (MOl. The remaining two registers are the.lnstruction Register OR) and the Memory Address Register (MAR) which are used exclusively for internal operations. The CPU registers are defined as follows. ACCUMULATOR AND LINK (AC/L) All arithmetic and logical operations are performed in the AC. For any arithmetic operation, the AC data and memory data are combined in the ALU and the result is temporarily stored in the AC. Under software control, the AC can be cleared, set, complemented, incremented, tested or rotated. Using the Operate Microinstructions, a variety of register operate instructions can be' derived. The link is a one-bit exter:Jsion of the AC. It can be complemented with a carry ·out of the ALU or cleared, set, complemented, tested and rotated along with the rest of the AC. It also serves as the carry output for two's complement arithmetic. MULTIPLY OUOTIENT (MOl The MO register can be used as a temporary storage for the AC. The MO may be· 0 R'ed with the AC and the result stored in the AC or the contents of the AC and MO may be swapped. The MO is used in conjunction with the AC to perform multiplication, division, and double-precision operations. PROGRAM COUNTER (PC) The PC supports both memory and input-output device operations. For memory operations, the PC is controlled exclusively by internal logic and instructions fetched from memory. During an instruction fetch cycle the contents of the PC are transferred to the memory address register (MAR) while the current instruction is being decoded. The PC is then loaded with a new address or simply incremented for the next instruction depending upon the type of instruction. The next instruction obtained from memory is then loaded into the Instruction Register. For example, if the instruction is a JMP X, then the branch address X is loaded into the PC for program controlled branching. Branching can also be controlled by an external device during input-output operations. This feature allows I/O controlled vectored interrupts. MEMORY ADDRESS REGISTER (MAR) The MAR contains the address of the memory location that is currently selected for memory or I/O read-write operations. It is also used for microprogram control during data transfers to and from memory and peripherals. INSTRUCTION REGISTER UR) The instruction fetched from memory is held in the IR while being interpreted by the Instruction Decoder. The IR specifies the initial step of the microprogram sequence for each instruction and is also used to store temporary data for microprogram control. ARITHMETIC AND LOGIC UNIT (ALU) The A LU performs 12-bit arithmetic, logical and rotate operations. Its input is derived from the AC and anyone of the other CPU registers. The type of operations performed by the ALU include: ADD Logical AND Logical OR Test AC Left-right shifts and rotates Increment Complement Set/Clear OX-BUS MULTIPLEXER To keep the CPU pin count to a reasonable 40 and still maintain a 12-bit word structure, the address and data paths are multiplexed by the OX-Bus Multiplexer. It handles data, address and instruction transfers between the CPU and memory or peripheral devices on a time-multiplexed basis. TIMING AND CONTROL UNIT The Timing and Control Unit generates the state and cycle timing signals from a single-phase clock and maintains the proper sequences of events required for any processing task. It also decodes the instruction obtained from the I Rand combines the result with various timing signals and external control inputs to provide control and gating signals required by other functional units (both internal and external to the CPU). Memory Organization The HM-6100 has a basic addressing capacity of 4096 12-bit words. The addressing capacity may be extended to 32K words by Extended Memory Control hardware. Every location has a unique 4 digit octal (12 bit binary) address, 00008 to 77778 (000010 to 409510). The Memory is subdivided into 32 PAGES of 128 words each. Memory Pages are numbered sequentially from Page 008, containing addresses 0000-01778, to Page 378, containing addresses 7600877778. The first 5 bits of a 12-bit MEMORY ADDRESS denote the PAGE NUMBER and the low order 7 bits specify the PAGE ADDRESS of the memory location within the given Page. Loe 010. ~r 1 MEMORY FIELD (40, PAGES) LOC 007 LaC 006 LOC 005 LOC 004 LOC 003 LOC 002 LOCOOI LaC 000 1 MEMORY PAGE (200, LOCATIONS) FIGURE 3 - Memory Organization Memory and Processor Instructions The HM-6100 instructions are 12-bit words stored in memory. The HM-6100 makes no distinction between instruction and data; it can manipulate instructions as stored variables or execute data as instructions. There are three general classes of HM-6100 instructions. They are Memory Reference Instructions (MRI), Operate Instructions (OPR), and Input/Output Transfer Instructions (lOT). During an instruction fetch cycle, the HM-6100 fetches the instruction pointed to by the PC. The contents of the PC are transferred to the MAR. The PC is incremented by 1. The PC now contains the address of the "current" instruction which must be fetched from memory. Bits 0-4 of the MAR identify the CURRENT PAGE, that is, the Page from which instructions are currently being fetched and bits 5-11 of the MAR identify the location within the Current Page. (PAGE ZERO (0),00008-01778, by definition, denotes the first 128 words of memory and is called the Register Page.) Since the HM-6100 is a static design it can operate at any crystal frequency from 0 to 8MHz. State times required for execution are given for each instruction. Execution time can be calculated from the equation: T = N*(2*(1/F)) where N is the number of state times and F is the crystal or input clock frequency. MEMORY REFERENCE INSTRUCTIONS (MRI) The Memory Reference Instructions operate on the contents of a memory location or use the contents of a memory location to operate on the AC or the PC. The first 3 bits of a Memory Reference Instruction specify the operation code, or OPCODE, and the low order 9 bits, the OPERAND address, as shown in Figure 4. o 2 3 4 OP CODE 0 - 5 IA MP 5 6 8 9 10 11 PAGE RELATIVE ADDRESS 0 = Direct; Indirect Addressing Memory Page 0 = Register Page; IA: MP: 7 1 = Indirect 1 = Current Page FIGURE 4 - Memory Reference Instruction Format Bits 5 through 11, the PAGE ADDRESS, identify the location of the OPERAND on a given page, but they do not identify the page itself. The page is specified by bit 4, called the CURRENT PAGE OR REGISTER PAGE BIT. If bit 4 is a 0, the page address is interpreted as a location on the Register Page. If bit 4 is a 1, the page address specified is interpreted to be on the Current Page. By this Method, 256 locations may be directly addressed, 128 on the REGISTER PAGE and 128 on the CURRENT PAGE. Other locations are addressed by using bit 3. When bit 3 is a 0, the operand address is a DIRECT ADDRESS. An INDIRECT ADDRESS (pointer address) identifies the location that contains the desired address (effective address). To address a location that is not directly addressable, not in the REGISTER PAGE or in the CURRENT PAGE, the absolute address of the desired location is stored in one of the 256 directly addressable locations (pointer address). Upon execution, the MRI will operate on the contents of the location identified by the address contained in the pointer location. Note that locations 00108-00178 in the Register Page are AUTOINDEXED. When these locations are used for index registers their contents are incremented by 1 and restored before they are used as the operand address. These locations are therefore convenient for indexing applications. Combinations of mode and page bits yield four (4) addressing modes: • • • • Current Page, Direct Current Page, Indirect Register Page, Direct Register Page, Indirect A fifth addressing mode results from use of the AUTOINDEX registers: • Register Page, Autoindexed TABLE 1 NUMBER OF STATES MNEOP AUTOMONIC CODE DIRECT INDIRECT INDEXED OPERATION AND OX XX 10 15 16 LOGICAL AND: Causes a bit-by-bit boolean AND between the contents of the Accumulator and the contents of the effective address (XXX) specified by the instruction. The result is left in the AC and the data word in the referenced location is not altered. TAD 1XXX 10 15 16 TWO'S COMPLEMENT ADD: Performs a binary two's complement addition between the specified data word and the contents of the AC; the result is left in the AC. If a carry out occurs, the state of the Link is complemented. If the AC is initially cleared, this instruction acts as a LOAD from memory. ISZ 2XXX 16 21 22 INCREMENT AND SKIP IF ZERO: The contents of the effective address are incremented by 1 and restored. If the result is zero, the next sequential instruction is skipped. DCA 3XXX 11 16 17 DEPOSIT AND CLEAR THE ACCUMULATOR: The contents of the AC are stored in the effective address and the AC is cleared. JMS 4XXX 11 16 17 JUMP TO SUBROUTINE: The contents of the PC are stored in the effective address and the effective address + 1 is stored in the PC. The link, AC, and MO are unchanged. JMP 5XXX 10 15 16 JU MP: The effective address is loaded into the PC thus causing program execution to branch to a new location. lOT 6XXX 17 OPI 7XXX 10 15 INPUT/OUTPUT TRANSFER: Used to initiate the operation of peripheral devices and to transfer data between the peripherals and the CPU. OPERATE Instructions: Used to perform logical operations on the contents of the major registers. 2 - Cycle OPERATE 3 - Cycle OPERATE Operate Instructions The Operate Instructions, which have an OPCODE of 78(111), consist of 3 groups of microinstructions. Group 1 microinstructions, which are identified by the presence of a 0 in bit 3, are used to perform logical operations on the contents of the accumulator and link. Group 2 micro instructions, which are identified by the presence of a 1 in bit 3 and a 0 in bit 11, are used primarily to test the contents of the accumulator and then conditionally skip the next sequential instruction. Group 3 microinstructions have a 1 in bit 3 and a 1 in bit 11 and are used to perform logical operations on the contents of the AC and MO. The basic OPR instruction format is shown in Figure 5. Operate microinstructions from any group may be microprogrammed with other operate microinstructions of the same group. The actual code for a microprogrammed combination of two, or more, microinstructions is the bitwise logical OR of the octal codes for the individual microinstructions. When more than one operation is microprogrammed into a single instruction, the operations are performed in a prescribed sequence, with logical sequence number 1 microinstructions performed first, logical sequence number 2 microinstructions performed second, logical sequence number 3 microinstructions performed third, and so on. Two operations with the same logical sequence number, within a given group of microinstructions, are performed simultaneously. o 4 3 2 5 6 7 B 9 10 11 B A A B Group 1 0 0/1 Group 2 1 0 Group 3 1 1 MICROINSTRUCTION FIGURE 5 - Basic OPR Instruction Format GROUP 1 MICROINSTRUCTIONS Figure 6 shows the instruction format of a group 1 microinstruction. Anyone of bits 4 to 11 may be set, loaded with a binary 1, to indicate a specific group 1 microinstruction. If more than one of these bits is set, the instruction is a microprogrammed combination of group 1 microinstructions, which will be executed according to the logical sequence shown in Figure 6. o 2 o 5 4 3 I ClA 7 6 B 9 I I I I I I Cll logical Sequences: 1- ClA Cll 2 -CMA CMl 3-IAC 4 - RAR RAl RTR RTL BSW CMA CMl 10 11 0/1 lAC RAR RAl BITS BIT9 BIT 10 FUNCTION 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 BSW RAl RTl RAR RTR FIGURE 6 - Group 1 Microinstruction Format Table 2-1 lists commonly used group 1 microinstructions, their assigned mnemonics, octal number, instruction format, logical sequence, the operation they perform, and the number of states. The same format is followed in Table 3 and 4 which corresponds to group 2 and 3 microinstructions, respectively. There are several commonly used microprogrammed combinations of group 1 microinstructions. These are listed in Table 2-2. When writing programs it is necessary to load various constants into the AC for such purposes as initiallizing counters and to provide comparisons. Table 2-3 lists those constants which can be loaded directly via microprogrammed combinations of group 1 instructions. TABLE 2-1 NUMBER MNE- OCTAL LOGICAL OF MONIC CODE SEQUENCE STATES OPERATION NOP 7000 1 10 NO OPERATION - This instruction causes a 10 state delay in program execution, without affecting the state of the HM-6100. It may be used for timing synchronization or as a convenient means of deleting an instruction from a program. CLA 7200 1 10 CLEAR ACCUMULATOR - The accumulator is loaded with binary O's. FIGURE 2 -1 Continued NUMBER OF MNE- OCTAL LOGICAL MONIC CODE SEQUENCE STATES OPERATION CLL 7100 1 10 CLEAR LINK - The'link is loaded with a binary O. CMA 7040 2 10 COMPLEMENT ACCUMULATOR - The content of each bit of the AC is complemented. This has the effect of replacing the contents of the AC with its one's complement. CML 7020 2 10 COMPLEMENT LINK - The content of the link is complemented. lAC 7001 3 10 INCREMENT ACCUMULATOR - The content of the AC is incremented by one (1) and the carry out componments the Link (L). BSW 7002 4 15 BYTE SWAP - The right six (6) bits of the AC are exchanged or SWAPPED with the left six bits. AC(O) is swapped with AC(6), AC(l) with AC(7), etc. The link is not affected. RAL 7004 4 15 ROTATE ACCUMULATOR LEFT - The content of the AC and L are rotated one binary position to the left. AC(O) is shifted to Land L is shifted to AC(ll). The ROTATE instructions use what is commonly called a circular shift, meaning that any bit rotated off one end of the accumulator will reappear at the other end. RTL 7006 4 15 ROTATE TWO LEFT - The contents of the AC and L are rotated two binary positions to the left. AC(l) is shifted to Land l is shifted to AC(10). RAR 7010 4 15 ROTATE ACCUMULATOR RIGHT - The contents of the AC and l are rotated one binary position to the right. AC(ll) is shifted to land lis shifted to AC(O). RTR 7012 4 15 ROTATE TWO RIGHT - The contents of the AC and l are rotated two binary positions to the right. AC(10) is shifted to land l is shifted to AC(1). TABLE 2- 2 NUMBER LOGICAL OF SEQUENCE STATES MNEMONIC OCTAL CODE' ClA Cll 7300 1 10 CLEAR ACCUMULATOR - CLEAR LINK CIA 7041 2,3 10 COMPLEMENT AND INCREMENT ACCUMULATOR - The content' of the AC is replaced with its two's complement. The carry out complements the link. Thjs is a microprogrammed combination of CMA and lAC. STL 7120 1,2 10 SET THE LINK - The LINK is loaded with a binary 1 corresponding with a microprogrammed combination of Cll and CMl. STA 7240 1,2 10 SET THE ACCUMULATOR - Each bit of the AC is set to 1 corresponding to a microprogrammed combination of ClA and CMA. ClA lAC 7201 1,3 10 Sets the accumulator to a 1. OPERATION TABLE 2 - 2 Continued NUMBER LOGICAL OF SEQUENCE STATES MNEMONIC OCTAL CODE GLK 7204 1,4 16 GET LINK - The AC is cleared and the content of the link is shifted into AC(11) while a 0 is shifted into the link. This is a microprogrammed combination of CLA and RAL. CLL RAL 7104 1,4 16 CLEAR LINK - ROTATE ACCUMULATOR LEFT CLL RTL 7106 1,4 16 CLEAR LINK - ROTATE TWO LEFT CLL RAR 7110 1,4 15 CLEAR LINK - ROTATE ACCUMULATOR RIGHT CLL RTR 7112 1,4 15 CLEAR LINK- ROTATE TWO RIGHT OPERATION TABLE 2- 3 MNEMONIC OCTAL CODE LOGICAL SEQUENCE NUMBER OF STATES DECIMAL CONSTANT NLOOOO NLOO01 NLOO02 NLOO03 NLOO04 NLOO06 NL0100 NL2000 NL3777 NL4000 NL6777 NL6000 NL7776 NL7776 NL7777 7300 7301 7305 7325 7307 7327 7303 7332 7360 7330 7362 7333 7346 7344 7340 1 1,3 1,3,4 1,2,3,4 1,3,4 1,2,3,4 1,3,4 1,2,4 1,2,4 1,2,4 1,2,4 1,2,3,4 1,2,4 1,2,4 1,2 10 10 15 15 15 15 15 16 15 16 16 16 16 16 10 0 1 2 3 4 6 64 1024 2047 -0 -1026 -1024 -3 -2 -1 INSTRUCTIONS COMBINED CLA CLL CLA CLL lAC CLA CLL lAC RAL CLA CLL CML lAC RAL CLA CLL lAC RTL CLA CLL CML lAC RTL CLA lAC BSW CLA CLL CML RTR CLA CLL CMA RAR CLA CLL CML RAR CLA CLL CMA RTL CLA CLL CML lAC RTR CLA CLL CMA RTL CLA CLL CMA RAL CLA CLL CMA GROUP 2 MICROINSTRUCTIONS Figure 7 shows the instruction format of group 2 microinstructions, Bits 4 - 10 may be set to Indicate a specific group 2 microinstruction. If more than one of bits 4 - 7 or 9 - 10 is set, the instruction is a microprogrammed combination group 2 microinstructions, which will be executed according to the logical sequence shown in Figure 7. o 2 3 4 6 6 7 B I I I I I•I CLA SMA SZA Logical Sequences: 1 (BIT B = 0) -SMA or SZA or SNL (BIT B 1) -SPA or SNA or SZL 2 -CLA 3 -OSR, HLT = SNL 9 10 11 OSR HLT 0 * Reverse sensing BIT: Unconditional SKIP when BITS 6, 6, & 7 are O's FIGURE 7 - Group 2 Microinstruction Format Skip microinstructions may be microprogrammed with CLA, OSR, or H LT microinstructions. Skip microinstructions which have a 0 in bit B, however, may not be microprogrammed with skip microinstructions which have a 1 in bit B. When two or more skip microinstructions are microprogrammed into a single instruction, the resulting condition on which the decision will be based is the logical OR of the individual conditions when bit B is 0, or when bit B is 1, the decision will be based on the logical AND. TABLE 3-1 MNEMONIC OCTAL CODE NOP 7400 CLA 7600 HLT 7402 SKP NUMBER LOGICAL OF SEQUENCE STATES OPERATION 10 NO OPERATION - See Group 1 microinstructions. 2 10 CLEAR ACCUMULATOR - The accumulator is loaded with binary O's. 3 10 HA L T - Program stops at the conclusion of the current machine cycle. If H LT is combined with others in OPR 2, the other operations are completed before the end of the cycle. 7410 10 SKIP - The content of the PC is incremented by 1, to skip the next instruction. SNL 7420 10 SKIP ON NON-ZERO LINK - The content of L is sampled; the next sequential instruction is skipped if L contains a 1. If L contains a 0, the next instruction is executed. SZL 7430 10 SKIP ON ZERO LINK - The instruction is skipped if the link contains a O. SZA 7440 10 SKIP ON ZERO ACCUMULATOR - The content of the AC is sampled; the next sequential instruction is skipped if all AC bits are O. If any bit in the AC is a 1, the next instruction is executed. SNA 7450 10 SKIP ON NON-ZERO ACCUMULATOR - The next instruction is skipped if anyone bit of the AC contains a 1. If every bit in the AC is 0, the next instruction is executed. SMA 7500 10 SKIP ON MINUS ACCUMULATOR - If the content of AC(O) contains a negative two's complement number, the next sequential instruction is skipped. If AC(O) contains a 0, the next instruction is executed. SPA 7510 10 SKIP ON POSITIVE ACCUMULATOR - If the content of AC(O) contains a 0, indicating a positive two's complement number, the next sequential instruction is skipped. OSR 7404 3 15 OR WITH SWITCH REGISTER - The content of the Switch Regist·· ter is inclusively 0 Wed with the content of the AC and the resu It stored in the AC. The HM-6100 sequences the OSR instruction through a 2-cycle execute phase referred to as OPR 2A and OPR 2B. This instruction provides the simplest way to input data to the HM6100 from peripherals. LAS 7604 1,3 15 LOAD ACCUMULATOR WITH SWITCH REGISTER - The content of the AC is loaded with the content of the SR, bit for bit. This is equivalent to a microprogrammed combination of CLA and OSR. Table 3 - 2 lists every legal combination of skip microinstructions, along with the resulting condition upon which the decision to skip or execute the next sequential instruction is based. When these combinations include a ClA, the accumulator is cleared after the decision is made. This is a useful trick to save code when a new value will be TAD'ed into the AC. TABLE 3 - 2 MNEMONIC SZA SNl SNA SZl SMA SNl SPA SZl SMA SZA SPA SNA SMA SZA SPA SNA SNl SZl OCTAL CODE LOGICAL SEOUENCE NUMBER OF STATES OPERATION 7460 7470 7520 7530 7540 7550 7560 7570 1 1 1 1 1 1 1 1 10 10 10 10 10 10 10 10 Skip if AC = 0 or l = 1 or both. Skip if AC.;t'O and l = O. Skip if AC< 0 or l = 1 or both. Skip if AC?,O and l = O. Skip if AC ~O. Skip if AC >0. Skip if AC~O or l = 1 or both. Skip if AC >0 and l = O. When writing an actual program, it is useful to think in terms of the FORTRAN relational operators -.L T., .EO., etc.when trying to compare numbers. The following method along with Table 3 - 3 will provide this. ClA Cll TAD B CMl CMA lAC TADA Test ClA !Initialize AC and Link !Fetch 2nd number !Create "-B" (AC & l act like a 13 bit accumulator) !Fetch 1st number fUse instructions from Table 3 - 3 to provide test !The ClA is optional to provide a clear AC after test !Branch to FAil routine if test failed /Test passed, continue with program JMP FAil TABLE3-3 UNSIGNED COMPARE SKIP IF SIGNED COMPARE SNA SNl SNl SZA SZA SZl SZl SNA A. NE. B A. LT. B A. LEo B A. Ea. B A. GE. B A.GT. B SNA SMA SMA SZA SZA SPA SPA SAN GROUP 3 MICROINSTRUCTIONS Figure 8 shows the instruction format of group 3 microinstructions which requires bits 3 and 11 to contain a 1. Bits 4, 5 or 7 may be set to indicate a specific group 3 microinstruction. If more than one of the bits is set, the instruction is a microprogrammed combination of group 3 microinstructions following the logical sequence listed in Figure 8. 0 I 2 I I 3 4 5 I ClA IMOA logical Sequences: 1 - ClA 2 - MOA, MOL 3 - NOP 7 6 I I 8 9 Mall * *Don't care FIGURE 8 - Group 3 Microinstruction Format 10 11 TABLE 4 MNEMONIC OCTAL CODE LOGICAL SEQUENCE NUMBER OF STATES NOP 7401 3 10 NO OPERATION - See group 1 microinstructions. CLA 7600 1 10 CLEAR ACCUMULATOR MQA 7501 2 10 MQ REGISTER INTO ACCUMULATOR - The content of the MQ is logical OR'ed with the content of the AC and the result is loaded into the AC. The original content of the AC is lost but the original content of the MQ is retained. This instruction provides the programmer with an inclusive OR operation. MQl 7421 2 10 MQ REGISTER lOAD - The content of the AC is loaded into the MQ, the AC is cleared and the original content of the MQ is lost. This is similar to a DCA instruction. ACl 7701 1, 2 10 CLEAR ACCUMULATOR AND lOAD MQ REGISTER INTO ACCUMU lA TO R - This is equivalent to a microprogrammed combination of ClA and MQA. It is similar to the two instruction combination of ClA and TAD. CAM 7621 1,2 10 CLEAR ACCUMULATOR AND MQ REGISTER - The content of the AC and MQ are loaded with binary O's. This is equivalent to a microprogram combination of ClA and MQl. SWP 7521 2 10 SWAP ACCUMULATOR AND MQ REGISTER - The content of the AC and MQ are interchanged by accomplishing amicroprogrammed combination of MQA and MQl. ClASWP 7721 1,2 10 CLEAR ACCUMULATOR AND SWAP ACCUMULATOR AND MQ REGISTER - The content of the AC is cleared. The content of the MQ is loaded into the AC and the MQ is cleared. OPERATION Input Output Tflnsfer Instructions (lOT) The input/output transfer instructions, which have an OPCODE of 68 are used to initiate the operation of peripheral devices and to transfer data between peripherals and the HM-6100. Three types of data transfer may be used to receive or transmit information between the HM-6100 and one or more peripheral I/O devices. PROGRAMMED DATA TRANSFER provides a straightforward means of communicating with relatively slow I/O devices, such as Teletypes, cassettes, card readers and CRT displays. INTERRUPT TRANSFERS use the interrupt system to service several peripheral devices simultaneously, on an intermittent basis, permitting computational operations to be performed concurrently with the data I/O operations. Both Programmed Data Transfers and Program Interrupt Transfers use the accumulator as a buffer, or storage area, for all data transfers. Since data may be transferred only between the accumulator and the peripheral, only one 12 bit word at a time may be transferred. DIRECT MEMORY ACCESS, DMA, Transfers variable-size blocks of data between high-speed peripherals and the memory with minimum of program control required by the HM-6100. lOT INSTRUCTION FORMAT The Input/Output Transfer instruction format is represented in Figure 9. 0 2 3 4 5 6 7 a 9 10 11 10 11 USER DEFINABLE BITS 0 Basic lOT Instruction: 6XXX a 0 2 0 3 4 5 6 7 a 9 DEVICE SELECTION PDP-alE Format: 6NNX8 FIGURE 9 -lOT Instruction Format CONTROL The first three bits, 0 - 2, are always set to 68 (110) to specify an lOT instruction. The next 9 bits, 3 - 11, are user definable and can provide a minimal implementation when each bit controls one operation. When following PDP-8/E format, the next six bits, 3 - 8, contain the device selection code that determines the specific I/O device for which the lOT instruction is intended and, therefore, permit interface with up to 64 I/O devices. The last three bits, 9 - 11, contain the operation specification code that d'etermines the specific operation to be performed. The nature of this operation for any given lOT instruction depends entirely upon the circuitry designed into the I/O device interface. PROGRAMMED DATA TRANSFER Programmed Data Transfer is the easiest, simplest, most convenient and most common means of performing data I/O. For microprocessor applications, it may also be the most cost effective approach. The data transfer begins when the HM-6100 fetches an instruction from the memory and recognizes that the current instruction is an lOT @. This is referred to an IFETCH and consists of five (5) internal states. The HM-6100 sequences the lOT instruction through a 2-cycle execute phase referred to as IOTA and 10TB. Bits 0 - 11 of the lOT instruction are available on DXO - 11 at IOTA A LXMAR @. These bits must be latched in an external address register. DEVSEL is active low to enalbe data transfers between the HM-6100 and the peripheral device @)&@. Input-Output Instruction Timing..!!. shown i~ ure 10. The selected peripheral device communicates with the HM-6100 through 4 control lines - CO, Cl, C2 and SKP. In the HM-6100 the type of data transfer, during an lOT instruction, is specified by the peripheral device(s) by asserting the control lines as shown in Tables 5-1 and 5-2. The control line SKP, when low during an lOT, causes the HM-6100 to skip the next sequential instruction. This feature is used to sense the status of various signals in the device interface. The CO, Cl, and C21ines are treated independently of the SKP line. In the case of a RELATIVE or ABSOLUTE JUMP, the skip operation is performed after the jump. The input signals to the HM-6100, DXO - 11, CO, C1, C2 and SKP, are sampled during IOTA on the rising edge of time state 3 @. The data from the HM-6100 is available to the device during DEVSEL A XTC @. The 10TB cycle is internal to the HM-6100 to perform the operations requested during IOTA. Both IOTA and 10TB consists of six (6) internal states. I~.'------IFETCH-------'.~I'-'.---------IOTA------------.~I~.~---------IOTB--------~·~I OSCOUT T-STATES T1 T1 T1 I I I ox (0-111 ~-----<or=x:-w:?~3::x=m:::::J-----CJD"""------------( 1 I 1 IFETCHJr----------------------1-____________________________________________________ ~r__ LXMAR I ~~ ________________ , XTA ______ ~r--I~ ~r_1~ , _________________________________________________'r _______ ~r__I~ _________ ~r__l~ _____________ , " XTB~____________~r--lL---------~-----,--------------1r----- I ' r_------------L___________ I ________S_------------1_____________ _1r__ I , ~-----,t______r_--------~------------------------------------------------------~-XTCJr------------~ ~ I I L-J~--------------------------~-- __ I I __-I 1-__-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-__ . I I I , WAIT -_---L---.1\..--_-_-_-_-_-_-L---.J\--_-_-_-_-L-J\...-":___-_-_-_-_-_-_-_-_-_I S~.~-------------------- <D INSTRUCTION ADDRESS ® lOT INSTRUCTION ® DEVICE ADDRESS AND CONTROL FIGURE 10 - Input-output instruction timing @ DEVICE DATA IN ® AC DATA OUT TABLE5-1 AC DATA TRANSFERS CONTROL LINES SKP CO C1 C2 OPERATION DESCRIPTION H H H H DEV-AC The content of the AC is sent to the device. H L H H DEV-AC;CLA The content of the AC is sent to a device and then the AC is cleared. H H L H AC-ACVDEV; DEV-AC Data is received from a device OR'ed with the data in the AC and the result is stored in the AC. The new AC content is sent to the device. H L L H AC-DEV; DEV-AC Data is received from a device and loaded into the AC. The new AC content is sent to the device. L H H H DEV-AC; PC-PC+ 1 The content of the AC is sent to the device and the microprocessor skips the next sequential instruction. L L H H DEV-AC;CLA; PC -PC+ 1 The content of the AC is sent to a device, the AC is cleared, and the microprocessor skips the next sequential instruction. L H L H AC-ACV DEV; DEV-AC; PC-PC+ 1 Data is OR'ed into the AC, the new AC sent to the device, and the microprocessor skips the next sequential instruction. L L L H AC-DEV; DEV-AC PC-PC+ 1 Data is loaded into the AC, the new AC contents sent to the device, and the next sequential instruction skipped. TABLE 5- 2 PC VECTOR TRANSFERS CONTROL LINES SKP CO C1 C2 H H · · OPERATION DESCRIPTION H L PC -PC+DEV Data from the device is added to the contents of the PC. This is referred to as a RELATIVE JUMP. L L PC -DEV Data is received from a device and loaded into the PC. This is referred to as an ABSOLUTE JUMP. L · H L PC- PC+ DEV; PC- PC+ 1 The RELATIVE JUMP is performed and then the microprocessor skips the next sequential instruction. L · L L PC-DEV; PC-PC+ 1 The ABSOLUTE JUMP is executed and then the next sequential instruction is skipped . • Don't Care PROGRAM INTERRUPT TRANSFERS The program interrupt system may be used to initiate programmed data transfers in such a way that the time spent waiting for device status is greatly reduced or eliminated altogether. It also provides a means of performing concurrent programmed data transfers between the HM-6100 and the peripheral devices. This is accomplished by isolating the I/O handling routines from the mainline program and using the interrupt system to ensure that these routines are entered only when an I/O device status is set, indicating that the device is actually ready to perform the next data transfer, or that is requires some sort of intervention from the running program. TABLE 6 PROCESSOR lOT INSTRUCTIONS MNEMONIC OCTAL CODE SKON SOOO SKIP IF INTERRUPT ON - If Interrupt system is enabled, the next sequential instruction is skipped. The Interrupt system is disabled. ION SOOl INTERRUPT TURN ON - The internal interrupt acknowledge system is enabled. The interrupt system is enabled after the CPU executes the next sequential instruction. IOF S002 INTERRUPT TURN OFF - The interrupt system is disabled. Note that the interrupt system is automatically disabled when the CPU acknowledges an INT request. SRQ S003 SKIP IF INT REQUEST - The next sequential instruction is skipped if the INT request bus is low. GTF S004 GET FLAGS - The following machines states are read into the indicated bits of AC. bit 0 - Link bit 1 - Greater than flag" bit 4 - Interrupt Enable FF* bit 2 - I NT request bus bit 5 - User flag" bit S - 11 - Save Field Register* bit 3 - Interrupt Inhibit FF* OPERATION ~These bits are modified by external devices driving the DX bus and the ~-lines (CO = L, Cl = L). For example, bits 1 and S - 11 are part of the Extended Memory Control. RTF S005 RETURN FLAGS - Link is restored from AC (0). Interrupt system is enabled after the next sequential instruction is executed. All AC bits are available externally to restore external states. (ex. Extended memory control). (CO = H, Ci = H) SGT SOOS SKIP ON GREATER THAN FLAG - Operation is determined by external devices, if any. This flag is external and must control the skip line. CAF S007 CLEAR ALL FLAGS - AC and link are cleared. Interrupt system is disabled. The interrupt system allows certain external conditions to interrupt the computer program by driving the 'iN'i"REQ input to the HM-Sl00 low. If no higher priority requests are outstanding and the interrupt system is enabled, the HMS100 grants the device interrupt at the end of the current instruction. After an interrupt has been granted, the Interrupt Enable Flip-Flop in the HM-Sl00 is reset so that no more interrupts are acknowledged until the interrupt system is re-enabled under program control. The current content of the Program Counter, PC, is deposited in location OOOOs of the memory and the program fetches the instruction from location 0001S. The return address is available in location OOOOs. This address must be saved, possibly in a software stack, if nested interrupts are permitted. The INTGNT signal is activated by the HM-Sl00 when a device interrupt is acknowledged. This signal is reset by executing any lOT instruction. The INTGNT is also useful in implementing an External Vectored Priority Interrupt network. The user program controls the interrupt mechanism of the HM-Sl00 by executing the processor lOT instructions listed in Table S. Several of these interrupt lOT instructions are also used if the memory is extended beyond 4K words. DIRECT MEMORY ACCESS (DMA) Direct Memory Access, sometimes called data break, is the perferred form of data transfer for use with high-speed storage devices such as magnetic disk or tape units. The DMA mechanism transfers data directly between memory and peripheral devices. The HM-Sl00 is involved only is setting up the transfer; the transfers take place with no processor intervention on a "cycle stealing" basis. The DMA transfer rate is limited only by the bandwidth of the memory and the data transfer ·characteristics of the device. The device generates a DMA Request when it is ready to transfer data. The HM-Sl00 grants the DMAREQ by activating the DMAGNT signal at the end of the current instruction. The HM-Sl00 suspends any further instruction fetches until the DMAREQ line is released. The DX lines are tri-stated, all SEL lines are high, and the external timing signals XTA, XTB, and XTC are active. The device which generated the DMAREQ must provide the address and necessary control signals to the memory for data transfers. The DMAREQ line can also be used as a level sensitive "pause" line. Control Panel Interrupt Transfer The HM-6100 CPU provides a unique Control Panel (CP) feature through its CPREO input and CPSEL output lines. After aCknowledging the control panel request, the CPU generates the necessary timing to execute program code in CP memory while also providing the capability to transfer data between CP memory and the user memory using the AC as a buffer. This allows the user memory to be examined and/or modified by the CP software. The CPU will output the MEMSEL signal for all user memory references while the CPSEL signal is generated for CP memory references as shown in Figure 11. CPSEL OX-BUS CP REOUEST INPUT MEMSEL FIGURE 11 - Control Panel Block Diagram The designer can make use of the control panel features to implement various functions that will be "transparent" to the user's (main) memory. Some of the more common functions include: • • • • • • Binary Loader and Punch Register Examination and Modification Single Cycle Octal Debug with Breakpoints acta I Iisti ng Auto Bootstrap When a CPREO is granted the PC is stored in location 0000 of Panel Memory and the HM-6100 resumes operation at location 7777 of the Panel Memory. The CPR EO bypasses the interrupt enable system and the processor lOT instruction, ION and IOF, are ignored while the HM-6100 is in the Control Panel Mode. Once a CPREO is granted, the HM6100 will not recognize any DMAREO or INTREO until the CPREO has been fully serviced. During Control Panel program execution access to the user memory is gained through use of indirect TAD, AND, DCA and ISZ instructions. The CPU will transfer control from CPSEL to MEMSEL during the execute phase of these instructions. The instructions are always fetched from control panel memory. Exiting from the control panel routine is achieved by executing the following sequence: • ION • JMP 10000 /Exit via location 0000 in Panel Memory Location 0000 contains either the original return address deposited by the HM-6100 when the CP routine was entered, or it may be a new starting address defined by the CP routine. Internal Priority Structure After an instruction is completely sequenced, the major state generator scans the internal priority network as shown in in Figure 12. The state of the priority network decides the next sequence of the HM-6100. The CPU samples the RESET line, the request lines CPR EO, DMAREO, and INTREO, and the state of its internal RUN flip-flop during the last execute cycle of each instruction. The worst case response time of the HM-6100 to an external request is, therefore the time required to execute the longest instruction preceded by any 6-state execution cycle. For the HM-6100, this is an autoindexed ISZ, 22 states, preceded by any 6-state execution cycle instruction. The worst case response time is, therefore, 28 states, 14 IJs at 4M Hz clock frequency. When the HM-6100 is initially powered up, the state of the timing generator is undefined. The generator is automatically initialized with a maximum of 34 clock pulses. The request inputs, as the HM-61 00 is powered on, must span at least 58 clock pulses to be recognized, 34 clocks for the counter to initialize and a maximum of two HM-6100 cycles (20 to 24 clocks) for the state generator to sample the request lines. A positive transition of RUN/HLTshould occur at least 10 clock pulses after RESET to be recognized. The priority hierarchy is: • RESET - If the RESET line is asserted at the sample time, the processor immediately sets its program counter to 7777, clears the Accumulator and Link, and puts the processor in the HALT state. While halted, the processor continues to cycle and generate the timing signals XTA, XT8, and XTC. During reset the DX line is tristated and the SEL lines are high. • CPREQ - If the RESET line is not found to be asserted, but the CPREQ line is, the processor grants the control panel interrupt request at the end of the current cycle. • RUN/H LT - If neither of the foregoing lines are asserted, but the processor finds its internal RUN F F in the halt state, it enters the HALT cycle at the end of the last execute cycle. Pulsing the RUN/H LT line low causes the HM-6100 to alternately run and halt. The internal RUN FF changes state on the rising edge of the RUN/RLi' line. While halted the processor continues to generate the timing signals XTA, XTB, and XTC. • DMAREQ - DMA requests are granted at the end of the current cycle only if none of the above actions are pending. • 'iN'i'R'EQ - An interrupt request is granted at the end of the current cycle only if none of the higher priority lines preempts it. • IFETCH - If none of the above actions are indicated, the processor will fetch the next sequential instruction in the next cycle. PRIORITY SCAN PRIORITY EXECUTE INDIRECT/AUTO INDEX ONLY FOR ROTATES ONLY FOR OSR FIGURE 12 - Major processor states and number of clock cycles in each state. USB of Wait Input The HM-6100 samples the'iiVAi'T line during input-output data transfers. The WATi line, if active low, controls the transfer duration. If WAIT is active during input transfers (R EAD), the CPU waits in the T2 state. For an output transfer (WR ITE), WAIT controls the time for which the write data is maintained on the DX lines by extending the T6 state. When operating at the max frequency, the internal delay of the HM-6100 causes the falling edge select lines to be past the WAIT setup time for WR ITE. The rising edge of the select line for READ can be used to activate WAIT for a WR ITE. The wait duration is an integral multiple of the oscillator time period (Figure 13). ADVANCE STATE COUNTER NO NO ADVANCE DNECLDCK PULSE FIGURE 13 - WAIT sequencing steps. HM-6100 Oscillator Requirements USING AN EXTERNAL CRYSTAL An inexpensive crystal can be used th~reby eliminating the need for a clock generator. The crystal operates at parallel resonance. and thus is looks inductive in the circuit. An "AT" cut crystal should be used because it has a low temperature coefficient and can be used over a wide temperature range. The Feedback resistor and shunt capacitance are included internally. The crystal parameters needed are: • • • • • Frequency Mod of Resonance - Parallel (anti-resonant) Maximum Power level - 1 milliwatt Load Capacitance - 32pF Series Resistance (max) - 250n ---=-1 For precise frequency determination the effect of the stray circuit capacitance and internal 30pF capacitance must be taken into account. OSC OUT o r-- 141 XTAL I 15 OSC IN ;r; I I L ---~ FIGURE 14 - Oscillator input schematic USING AN EXTERNAL CLOCK GENERATOR When a system clock is needed, ego for a baud rate generator for UARTs, the HM-6100 can be externally clocked, thus eliminating the need for separate crystals. The external clock can be connected to the oscillator output pin while grounding oscillator input. This has the effect of over driving the small internal oscillator inverter causing an increase in supply current. Duty cycle - 50/50 Trise, Tfall- 20ns PIN DEFINITIONS PIN SYMBOL ACTIVE LEVEL I 2 VCC RUN H 3 DMAGNT H 4 DMAREQ L 5 CPREO L 6 RUN/HLT L 7 RESET L 8 9 INTREO XTA L H PIN SYMBOL ACTIVE LEVEL 21 22 23 24 25 26 27 28 29 30 31 DX5 DX6 DX7 DX8 DX9 GND DX10 DXll LINK DEVSEL SWSEL 32 CO H L L L DESCRIPTION Supply voltage. The signal indicates the run state of the CPU and may be used to power down the external circuitry Direct Memory Access Grant-DX lines are three-state. Direct Memory Access Request-DMA is granted at the end of the current instruction. Upon DMA grant, the CPU suspends program execution until the ~ line is released. Control Panel Request-a dedicated interrupt which bypasses the normal device interrupt request structure. Pulsing Ihe Run/Halt line causes the CPU to alternately run and halt by Chang~the state of the internal RUN/ flip flop. Clears the AC and loads 77778 into the PC. CPU is halted. Peripheral device interrupt request. External coded minor cycle timingsignifies input transfers to the HM-ill00. DESCRIPTION See Pin 16-DXO. See Pin 16-DXO. See Pin 16-DXO. See Pin 16-DXO. See Pin 16-DXO. Ground See Pin 16-DXO. See Pin 16-DXO. Link flip flop. Device Select for I/O transfers. Switch Register Select for the OR THE SWITCH REGISTER INSTRUCTION (OSR). OSR is a Group 2 Operate Instruction which reads a 12 bit external switch register and OR's it with the contents of the AC. Control line inputs from the peripheral device during an I/O transfer (Table 5). PIN SYMBOL ACTIVE LEVEL 10 LX MAR H II WAIT L 12 XTB H 13 XTC H 14 OSCOUT 15 OSCIN 16 DXO 17 18 19 20 DXl DX2 DX3 DX4 PIN SYMBOL ACTIVE LEVEL 33 34 35 C1 C2 SKI' L L L 36 37 38 IFETCH MEMSEL CPSEL H L L 39 40 INTGNT DATAF H H DESCRIPTION The Load External Address Register is used to store memory and peripheral address externally. Indicates that peripherals or external memory is not ready to transfer data. The CPU state gets extended as long as WAIT is active. The CPU is in the lowest power state with clocks running. External coded minor cycle timingsignifies output transfers from the HM~I00 . External coded minor cycle timingused in conjunction with the Select Lines to specify read or write operations. Crystal input to generate the internal timing (also external clock input). See Pin 14-DSC OUT (also external clock ground) DataX-multiplexed data in, data out and address lines. See Pin 16-DXO. See Pin 16-DXO. See Pin 16-DXO. See Pin 16-DXO. DESCRIPTION See Pin 32-CO. See Pin 32-CO. Skips the next sequential instruction if active during an I/O instruction. (Table 5) Instruction Fetch Cycle Memory Select for memory transfers. The Control Panel Memory Select becomes active, instead of the MEMSEL, for control panel routines. Signal may be used to distinguish between control panel and main memories. Peripheral device Interrupt Grant Data Field pin indicates the execute phase of indirectly addressed AND, TAD, ISZ and DCA instructions so that the data transfers are controlled by the Data Field, DF, and not the Instruction Field, IF, if Extended Memory Control hardware is used to extend the address· ing space from 4K to 32K words.
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