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XX-6EFA3-A8
May 2000
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HD-6121
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XX-6EFA3-A8
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8
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http://bitsavers.org/pdf/dec/pdp8/cmos8/_dataSheets/HD-6121.pdf
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mHARRIS HD-6121 CMOS I/O CONTROLLER Features • LOW POWER, TYP. < 2 mW • SINGLE SUPPLY - 5V • INDUSTRIAL AND MILITARY TEMPERATURE RANGES • 6120 COMPATIBLE INTERFACE • CONTROLS ANY COMBINATION OF FIVE INPUT OR OUTPUT PORTS WITH HANDSHAKING • ELIMINATES GATED READ AND WAITE SIGNALS THROUGH THE CONTROLLER • CONFORMS TO DEC' CONVENTIONS REGARDING DEVICE ADDRESSING AND COMMANDS • INDEPENDENT PROGRAMMING OF EACH DEVICE'S ADDRESS AND DATA DIRECTION • COMPLETE INTERRUPT AND SKIP LOGIC FOR EACH DEVICE INCLUDING PRIORITY INTERRUPT VECTORING • STROBE OUTPUTS ARE PROGRAMMABLE HIGH OR LOW TRUE • SENSE INPUTS ARE PROGRAMMABLE FOR LEVEL OR EDGE SENSITIVITY • ENABLE OUTPUTS FUNCTION AS USER PROGRAMMABLE CHIP SELECTS Pinout INTGNT ~ PRI STROBEl SENSEl ENABm S~~~~~~ ! ENABm STROBE3 SENSE3 ENAiii:E3 Description STROBE4 SENSE4 The HD·6121 Input/Output Controller (IOC) is a high performance, CMOS support circuit for the 6120 microprocessor. Fully programmable, this device offers independent control of any combination of five, 12 bit input or output ports. STROBE5 SENSE5 ENAiiLE4 ~ Used in conjunction with the 6120 microprocessor, the 6121 provides user programmable chip select decoding, priority vectored interrupt control, software readable status and 1/0 port handshaking signals. PRO SKI~ E vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 - HD·6121 40 ~Y££... 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 ~ WRi'i'E DXO DXl DX2 DX3 DX4 DX5 DX6 DX7 DX8 DX9 DX10 ~~ Me ~§ co The Priority In (PRI) and Priority Out (Pi"iO) control Signals permit up to eleven 6121s to be used without any additional hardware. Industrial control and other 1/0 intensive systems can profit greatly from the highly hardwarelsoftware efficient capability provided by the 6120/6121 chip set. * TRADEMARK of Digital Equipment Corp. Functional Diagram INTREQ co C1 SKIP OUTPUT BUFFER ....... .... PROGRAMMING AND INTERRUPT CONTROL -t READ WRITE INTGNT IOCLR LXDAR IOC CONTROL DX BUS DX BUS BUFFER PRI ... I/O PORT CONTROL LOGIC + .. .. VCC GND CAUTION: ElectroniC devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed. I ~~: * ENABLE STROBE SENSE ... PRO Specification HO-6121 ABSOLUTE MAXIMUM RATINGS Supply Voltage Operating Voltage Range Input/Output Voltage Applied Storage Temperature Range +8.0 VOLTS +4V to +7V VSS-0.3V to VCC+0.3V -65°C to +150°C Operating Temperature Range Industrial (-9, -9+) Military (-2, -8) Maximum Power Dissipation -40°C to +85°C -55°C to +125°C 1 Watt CAUTION: Stresses above those listed in the "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions aboVe those indicated in the operational sections of this specification is not implied. .. DC ELECTRICAL CHARACTERISTICS; VCC=5.0V+5%; TA = Industrial or Military TEST CONDITIONS MIN MAX UNITS SYMBOL PARAMETER VIH LOGICAL ONE INPUT VOLTAGE VIL LOGICAL ZERO INPUT VOLTAGE VOH LOGICAL ONE OUTPUT VOLTAGE VOL LOGICAL ZERO OUTPUT VOLTAGE VOL LOGICAL ZERO OUTPUT VOLTAGE ilL INPUT LEAKAGE CURRENT 10 1/0. OUTPUT LEAKAGE CURRENT ICC 70% VCC V 30% VCC VCC-0.5 V V 10H = -1.6mA Except for SKIP. INTREQ, CO and (;i which are open drain. 0.5 V 10L = 1.6mA Except for SKI P, INTREQ, eli and Cl 0.5 V -10 10 p.A OV,;;;VIN,;;;VCC -10 10 p.A OV,;;VO,;;;VCC NOTE 1 POWER SUPPLY CURRENT 100 p.A VIN=VCC or GND VCC ~ 5.25 V OUTPUTS OPEN CIN' INPUT CAPACITANCE 5 plF FREQ = 1 MHZ TA=25'C VIN=VCC or GND COUT' OUTPUT CAPACITANCE 15 pF FREQ = 1 MHZ TA=25'C VIN=VCC or GND 10L = 15mA SKiP, INTREQ, Co. Ci OUTPUTS * Guaranteed and sampled, but not 100% tested NOTE 1: APPLIES ONLY TO DXO THROUGH DXll, CO, C1, SKIP, AND iNi'REci WITH THE OUTPUT DRIVERS DISABLED OR OPEN DRAIN OUTPUTS OFF. A.C. ELECTRICAL CHARACTERISTICS; VCC=5.0V±5%; TA=lndustrial or Military; CL=50 pf, TEST CONDITIONS SYMBOL PARAMETER MIN MAX UNITS '-'~'~----'---- TAS ADDRESS SET UP TIME 30 ns TAH ADDRESS HOLD TIME 70 TRWE WRITE ENABLE DELAY 100 ns TRWD WRITE DISABLE DELAY 100 ns TWS WRITE SET UP TIME 50 ns TWH WRIT!: HOLD TIME 50 ns ns TPDE ENABLE OUTPUT DELAY 125 ns TPDD ENABLE OUTPUT DISABLE DELAY 200 ns TRE READ VECTOR ENABLE 100 ns TRD READ VECTOR DISABLE 100 ns TWPD WRITE PULSE DELAY 100 ns TLXH RESET DELAY, 10CLR TO LXDAR 100 ns NOTE: ALL MEASUREMENTS ARE TAKEN WITH INPUT RISE AND FALL TIMES" 20 NSEC Specifications NO·611t where tR=20 ns, VCC=5.0 volts, CL=50 pF on each of twelve outputs. i iii' (12 x 50 x 10-12) x (5.0v x 0.8)/(20 x 10-9 ) iiii120 mA This current spike may cause a large negative voltage spike on VCC, which could cause improper operation of the device. To filter out this noise, it is recommended that a 0.1 ,."F ceramic disk decoupling capacitor be placed between VCC and GNO at each device, with placement being as near to the device as possible. OECOUPLING CAPACITORS The transient current required to charge and discharge the 50 pf load capacitance specified in the 6121 data sheet is determined by i = CL (dv/dt) Assuming that all OX outputs change state at the same time and that dv/dt is constant; i =r CL (VCC x 80%) tA/tF MINOR CYCLES I~~ ox ______________________ ~ lOT CMD ~ ~I 000 DFO,DFI DATA I-- TWS 1TWHt- ~ ~ '\ \ ~r--- VECTOR DATA· I ~. I 4 16120 PULLS HIGH TRWD ~ I I I I I CI = H DURING WR!TE I ChL .. Vector Operation Only EXTERNAL lOT and VECTORED INTERRUPT OPERATION CAF INSTRUCTION POWER ON RESET RESET TIMING I ACTIVE LEVEL 1/0 PIN SYMBOL I I 1 2 iFJi'Gt;i'T' m 0 3,6,9, 12,15 STROBE 1-5 I 4,7,10, SENSE 13,16 1-5 0 0 5,8,11, ENABLE 14,17 1-5 18 PRO 0 19 SKiP 20 21,22 VSS 0 Co,ffi' Low 0 I I/O I I 23 24 25-36 37 38 INTREQ READ DXll-0 WRITE LXDAR Low Low High Low Low I 39 40 10CLR VCC Low Low Low DESCRIPTION Interrupt grant signal from the 6120. Input for priority string. Low implies no higher priority up the string. Device #1 Internally is the highest priority device. Output strobes set true by a transfer command. Cleared by a Set Flag command or by the corresponding sense Input going true. Programmable polarity. High or Low High or Low Low Status inputs from an external device. Can cause lOT skips or interrupts. Programmable edge or level sense and polarity. Bus transfer enable pulses for external devices. True during LXDAR. Low Output for priority string. Low implies enable for next device down the string. Device #5 internally is the lowest priority device and drives this output. True during LXDAR and WRITE to indicate to the 6120 that a skip is to occur on the current lOt. N-Channel open drain. Power supply ground. Control signals to the 6120 which specify the type of transfer required for an 1/0 instruction. See Table 1. N-Channel open drain. Interrupt request to the 6120. N-Channel open drain output. 6120 bus read pulse. 6120 data/address bus. (DXO=MSB, DXll = LSB) 6120 bus write pulse. 6120 I/O transfer enable signal. True during the execute phase of external lOT instruction. Also true during power on reset. Reset from the 6120 generated by power on reset or CAF instruction. Positive supply voltage. Low CONCEPT: The concept of the 10C is to provide basic control and enable signals for the devices which it controls but not be involved in the critical speed timing of the OX bus transfers to and from these devices. Each input or output port still has its own output latch or input driver interface which results in maximum flexibility with regard to I/O device characteristics. Because these latches and input drivers are not included in the 6121, this 40 pin device is able to provide complete handshaking for five I/O ports. Software programmable chip select decoding (ENABLE outputs) provides a means whereby I/O device addressing is readily changed with no change to the users PC board. This on-chip feature replaces the 2-5 IC's normally associated with chip select decoding. Another feature of the 6121 10C is an on-chip priority interrupt controlier. The interrupt logic includes software programmable vectors and complete interrupt request/grant handshaking for the 6120 microprocessor. This on-chip feature of the 6121 eliminates a separate interrupt controller IC. Up to eleven 6121 10Cs can be daisy chained without the need for any interfacing logic. This results in vectored interrupt control of up to 55 I/O ports. The Priority In (PRI) and Priority Out (PRO) control signals are used for this I/O expansion capability. Another major on-chip feature of the 612110C is the inclusion of I/O port handshaking signals. These signals provide the capability of polling the status of an Input port (SENSE inputs) and that of signaling an Output port that it has received data (STROBE outputs). These signals can be thought of as "Input Buffer Full" and "Output Buffer FUll" status lines. The characteristics of these signals are software programmable which greatly increases their flexibility. 6120 lOT INSTRUCTION SEQUENCING: The 6121 is designed to interface with the 6120 external lOT sequence. This sequence begins when the 6120 fetches an instruction from the memory and recognizes that the current instruction is an external lOT. An external lOT is any lOT (Bits 0-2=6) whose device code (Bits 3-8) is not 00 or 2X. EXTERNAL lOT COMMAND FORMAT o 2 o 3 4 5 6 7 8 1 ...1-'.----- ~EVICE A~DRESS:-----~MI 4 9 10 C~MMAN~ 11 Specification HO-6121 The 6120 sequences the lOT instruction through an execute phase. Bits 0-11 of the lOT instruction are available on DXO-11 as LXDAR falls near the start of the execute phase. The 6121 lac accepts the lOT command on the falling edge of LXDAR and latches this information into an internal command latch. WRITE or READ is active low to enable data transfers between the 6120 and the peripheral device(s). The 6121 communicates with the 6120 through 3 control lines .,. CO, C1 and SKIP.The type of data transfer during an lOT instruction is specified by the peripheral device by asserting the control lines as shown in Table 1. The control line SKIP, when low during an lOT, causes the 6120 to skip the next instruction. This feature is used to sense the status of various signals in the device interface. The CO andCi lines are treated independently of the SKIP line. The input command signals, Cli, C1 and SKIP, are sampled during LXDAR low' WRITE low. The data from the 6120 is available to the device(s) during LXDAR low· WRITE low. If Ci is low at LXDAR low' WRITE low, a read is also performed and data is read from the peripheral into the 6120 during LXDAR low' READ low. TABLE 1- PROGRAMMED 1/0 CONTROL LINES CONTROL LINES co C1 High High (Device)_(AC) The contents of the AC is sent to the device. Low High (Device)_(AC), Clear (AC) The contents of the AC is sent to the device, then the AC is cleared. High Low (AC)_(AC)V(Device) Data is received from a device,"OR'ed" with the data in the AC and the result stored in the AC. Low Low (AC)_(Device) Data is received from a device and loaded into the AC. DESCRIPTION OPERATION INTERNAL DEVICE CONTROLLER FLIP FLOP DEFINITIONS: There are five device controllers within the 6121 lac. Each controller has a set of control and status flip flops which are defined below: FLAG FLIP FLOP - Internal device control status flip flop which only has meaning if the IS programming bit is a 1. It is set by a SET FLAG lOT or by true going edge of sense input. It is cleared by the SKIP ON FLAG instruction only if it was sampled by that instruction as being set; by the interrupt vector operation; or by 10CLR. If the flag is set, interrupts can be generated if otherwise enabled. If the IS programming bit is 0, the flag flip flop is held in the cleared state. FLAG SAMPLE FLIP FLOP -Internal device control flip flop which samples the state of the flag flip flop at the falling edge of LXDAR. The set state of this flip flop causes the skip line to be pulled and the flag flip flop to be cleared during WRITE pulses of a skip lOT, STROBE FLIP FLOP-Internal device control flip flop which controls strobe outpuHne. It is set by a transfer lOT at the trailing edge of the LX AR pulse. It is cleared by iC5CCR, the true going edge of the sense input (if the IS programming bit set) or the SET FLAG lOT command. The STROBE output reflects the state of this flip ~op any time the strobe flip flop is cleared or at the end of LX AR if the strobe flip flop is set. INTERRUPT ENABLE FLIP FLOP -Internal device control flip flop which allows program enable of interrupts. This bit is set by 10CLR. This bit is loaded by DX11 during WRITE of LOAD INTERRUPT ENABLE lOT. If this flip flop and the flag flip flop are both set, then the INTREQ pin is pulled low. IIliTERRUPT SAMPLE FLIP FLOP -Internal device control flip flop which samples the state of the interrupt condition at the falling edge of INTGNT. The falling edge of INTGNT sets the interrupt sample flip flop if the flag flip flop and interrupt enable flip flop are set and the priority input is true. If the flag ~is clear or the priority input is false at the fall of fNTGNI. the state of the interrupt sample flip flop is not changed. The interrupt sample flip flop is cleared by the SKIP ON FLAG lOT, by the reset state of the interrupt enable flip flop or by 10CLR. If this flip flop is set, the device's priority output is false (high). PROGRAMMING: Immediately after power on reset, the five device controllers within the lac are set to a state such that the first lOT command received with PRI low will be interpreted as a programming command to set up various lac parameters. This is true only for power on reset and is not true for the reset generated by the 6120 CAF instruction. Power on reset from the 6120 is distinguished by LXDAR being low at the end of the 10CLR pulse. During the reset caused by the CAF instruction, LXDAR is high throughout the 10CLR pulse. Each of the five device controllers within the lac are programmed independently by separate lOT commands. If PRI is low, the first lOT programs the highest priority device (Device #1). The second lOT programs the second highest priority device (Device #2). This continues unt.!L.!!!!. the devices in the lac are program. med, at which time PRO is made low so that programming can commence on the next lac (if any) down the priority chain. The lac will not accept any operational lOT commands to any of the five devices until all five devices have been programmed. The programming lOT writes data from the 6120 accumulator. The lower 9 bits of the lOT instruction itself perform no programming function. The lOT instruction must be an external lOT, not device #00 or 2X. The programming format from the accumulator is shown below: PROGRAMMING COMMAND FORMAT o OP 3 2 IP 4 567 8 IS 9 10 11 EN c I/O additional constraint is that each device must have its own unique address. OP Output polarity 1= High true strobe output 0= Low true strobe output IP Input polarity 1 = High true sense polarity O=Low true sense polarity IS Input edge sensitivity 1 =Set flag flip flop and interrupt (if interrupts enabled) on true-going edge of sense input. Skip on flag flip flop set. 0= Skip on sense line input level true. (No interrupt on sense true.) DEVICE ADDRESS The 6 bit device address assigned to the device controller. EN Enable output control select. 1= Enable output is true (low) whenever the device is addressed. (Except for programming and vector operations.) O=Enable is true only when a transfer command (48 or Sa) is given. C C line control. O=Transfer commands do not cause C lines to be controlled. 1= Transfer commands cause C lines to be controlled. I/O Input or output port select. This programming bit has no meaning if the "C" programming bit is set to a "0". 1= T@.nsfer commands cause outputs to the device. (C1 is not pulled low.) 0= T@.nsfer commands cause inputs from the device. (C1 is pulled low.) After all five devices of the 10C are programmed, they are ready to respond to lOT commands with their programmed addresses. Because of this, no operational lOT commands can be used until all system 10C's have been programmed. An Note that unused devices must be turned off during programming simply by programming them with an internal lOT address (00 or 2X), and with the IS programming bit set to "0" to prevent interrupts. Also, sense inputs must be tied to ground. Internal 6120 lOT's do not generate LXDAR. The lOT controller is therefore made insensitive to all external lOT commands when programmed with an internal lOT address. Whenever a device controlle~ithin the 10C responds to its programming lOT, it pulls the CO line low so that the 6120 will perform an output operation from the AC followed by clearing the AC. IOC COMMANDS: Power on reset- This is indicated by the 10CLR input low and LXDAR low at the end of the 10CLR pulse. This operation sets up the 10C to be programmed as discussed above. Also, all five flag flip flops are cleared as are the flag sample and interrupt sample flip flops. The interrupt enable flip flops are all set. The strobe flip f10~S are cleared, the STROBE outputs are set low and the ENA LE outputs are set high. Note that if a controller is programmed for a low true STROBE output, then there will be a low to high transition on the strobe output when this device is programmed. Also, care must be taken to assure that the state of the flag, flag sample, interrupt sample, interrupt inhibit and strobe flip flops are not disturbed by the programming function. The 6120 Clear All Flags (CA~6nstructlon - This instruction is indicated to the 10C by I LR going low and LXDAR staying high during the 10CLR pulse. This operation performs exactly the same operation as power on reset on the device flag, flag sample, interrupt sample, interrupt enable and strobe flip flops. It does not set up the 10C for programming, nor does it disturb the state of any of the programming information stored within the 10C. EXTERNAL lOT COMMAND FORMAT 0 3 2 0 14 4 5 6 ~EVICE :ADDRES~ 7 9 8 11 ~OMMAN~ ~I Bit SET FLAG, CLEAR STROBE SKIP ON FLAG, CLEAR FLAG CLEAR ACCUMULATOR (If programmed for input) NOP DATA TRANSFER (CO not pulled low) LOAD INTERRUPT ENABLE (From DX11) DATA TRANSFER (CO pulled low) NOP 10 9 10 11 0 0 0 0 0 1 0 1 0 0 1 1 0 1 0 0 0 Each lOT is discussed below: SET FLAG, CLEAR STROBE -If the device is programmed for edge sensitive SENSE input, this lOT command causes the internal flag flip flop to be set and also clears the STROBE output to the programmed false state. If the device is programmed for level sensitive SENSE input, then the flag flip flop is not set by this instruction, but the STROBE output is cleared. SKIP ON FLAG, CLEAR FLAG - The skip on flag operation depends on whether the device is programmed for edge or level sensitivity. If programmed for level sensitivity and the SENSE input is logic true, then the SKIP line is pulled low during the lOT WRITE pulse; the clear flag operation has no meaning. II programmed for edge sensitivity, then the state of the flag flip flop is sampled to the flagWRflPle flip flop at the falling edge of LXDAR. During the lOT E pulse, the SKiP line will be pulled low if the flag sample flip flop is true. II the flag sample flip flop is set, then the flag flip flop will be cleared some time before or at the trailing edge of LXDAR. CLEAR ACCUMULATOR - This command only functions if the C line control programming bit (bit 10= 1) has been programmed for the device to control the C lines and the device has been programmed as an input device (bit 11 =0). When enabled by the above two programming conditions, this ~nd will cause CO to be pulled low during the lOT WRITE pulse. This will cause the 6120 accumulator to be cleared. DATA TRANSFER (4a or 6a) - Either transfer command will unconditionally set the STROBE output to its true state. II the "c" programming bit is set, the transfer commands will also cause the "C" lines to be controlled to specify the type of I/O transfer to be performed. II not, then the 10C device does not control the "C" lines. II the device "I/O" programming bit is 1, then Cl is not pulled low and an output transfer is specified by either 4a or 6a. II the I/O programming bit is 0, then an input transfer is specified by pullinJiLCi low during the WRITE pulse. Command 4a does not pull CO low. For an output, this corresponds to not clearing the AC after the output. For an input, this corresponds to "OR'ing" the input data with the AC. Command 6a always pulls CO low. For an output, this causes the AC to be cleared following the output. For an input, this corresponds to the input data being loaded into the AC. The STROBE output is cleared when the flag flip flop is set by the SENSE transition or by a SET FLAG command. LOAD INTERRUPT ENABLE - This command causes a write of 6120 AC bit 11 to the addressed device's interrupt enable flip flop. This write holds neither CO nor Ci low so that a write without a clear of the AC is performed. The device is incapable of generating interrupts if the interrupt enable flip flop is cleared. INTERRUPT LOGIC: A device controller within the 10C is capable of generating an interrupt by pulling the INTREQ line low if all of the following conditions are true: 1. The device is programmed for edge sensitive SENSE input, and 2. The device flag flip flop has been set, and 3. The device interrupt enable flip flop is set, and 4. The priority string input for that device is true. Normally, with no system interrupts outstanding, all device priolj!Y.inputs and outputs are low. At the highest priority 10C, the PRI input must be tied to Vss. Whenever the interrupt conditions are met at any device on the 10C, the INTREQ line is pulled low and the following sequence of events occurs: 1. The 6120 INTREQ being low causes INTGNT low. AIiIOC driving device controllers which have the interrupt condition met set their interrupt sample flip flops. Note that this is an edge triggered set and is not a "load". All device controllers which have their interrupt sample flip flops set will hold their respective priority outputs high. All device controllers with a high priority input hold their priority outputs high and also are inhibited from driving the INTREQ bus low. 2. When the first lOT is executed with INTGNT low, one of two events occurs, depending on the lOT command: a. II the command issued is a SKIP ON FLAG (la) command, then the normal operation of the lOT command occurs in the addressed device. A SKIP ON FLAG (1 a) instruction will clear the interrupt sample flip flop of the addressed device and will clear the flag flip flop if it is set. b. lithe command is not a SKIP ON FLAG (la) command, then the fact that INTGNT is low causes special action. During the WRITE pulse CO and Cl are both pulled low by the highest priority device with its interrupt sample flip flop set. No other device (not even the addressed device) will respond on this lOT. This lOT specifies a JAM read cycle. The 6120 then generates a READ pulse which causes the device address of the highest priority device with its interrupt sample flip flop set to put its device address on DX6-11 and all zeros on DXO-S. Also, the fla9..!!!.P..!!QE. of that device is cleared, causing it to remove the TJiITREQ drive. The interrupt sample flip flop is not cleared at this time so that the priority output of that device continues to be held false (high). c. Near the end of the interrupt service. routine of that particular device, the software should (with the 6120 interrupts disabled) execute a SKIP ON FLAG lOT to the device. This will clear the interrupt sample flip flop of the device, which in turn will setthe priority output olthat device true, enabling interrupts from devices lower in the chain. SOFTWARE NOTES: 1. When performing the interrupt vector operation from the 6120, the accumulator must be loaded with a "no interrupt" vector address (such as zero) before the vector lOT is issued. This vector is left in the accumulator if no internal vector is returned by a device controller. 2. Before a device's interrupts are turned off by resetting its interrupt enable flip flop with a 6XXS command the 6120's interrupts must be turned off. Failure to do so can result in an unidentifiable interrupt from the device. 3. When turning on a device's interrupt with a 6XXS command, an immediate interrupt will result if the device's flag is set and the 6120 interrupts are turned on. 4. Because the 10C programming sequence relies on an exact sequence of lOT instructions to be executed and 10CLR enables interrupts, the programming instructions must be executed with the 6120's interrupts off. 5. Use of the level sensitive "Skip on Flag, Clear Flag" operation (6xxl), requires that a redundant skip instruction followed by a NOP be used to guarantee that the "Flag Sample Flip Flop" is reset. TESTING NOTE: The PRO line cannot go true after any 10CLR true pulse (either in programming or in a CAF) until there is at least one READ pulse. In addition, no external lOT commands can be executed during an 10CLR true pulse. SUMMARY OF 6120, 6121 CONDITIONS: The following table provides a brief summary of all the 6120 and 6121 Operations. lOT COMMANDS BIT BIT BIT PROGRAMMING BITS 6120 6121 OPERATION OPERATION OUTPUTS 10 11 C 1/0 co Cl 0 1 0 1 1 HiZ HIZ Output (AC) NOP 1 0 0 1 1 HiZ HiZ Output (AC) Generate ENABLE. (Output to device.) Set STROBE output. 1 1 0 1 1 Low HIZ Output (AC) then (AC)+- 0 Generate EiiiABi:E. (Output to device.) Set STROBE output. 0 1 0 1 0 Low HIZ Output (AC) then (AC)+-O NOP except lor low CO output. Result is only to clear 6120AC. 1 0 0 I 0 HiZ Low (AC)+-Input V(AC) Generate ENABLE. (Input from device.) Set STROBE output. I 1 0 I 0 Low Low (AC)+-Input Generate ENABLE. (Input from device.) Set STROBE output. 9 I 0 I X X HIZ HIZ Output (AC) Loed Interrupt enable flip flop from OXII. 0 0 0 X X HiZ HiZ Output (AC) Set fleg flip flop if Its prog. b~ is set. Clear STROBE output. 0 0 I X X HiZ HiZ Output (AC) Pull SKIP low end cleer Flag F.F. if flag sample flip flop is a 1 during the write pulse. 1 I X X HiZ HIZ Output (AC) No operation. Vector Read X X Low Low (AC)+-Input Place interrupt vector on OX bus, clear Flag F.F. Programming lOT X X Low HIZ Output (AC) then (AC)+- 0 Load programming Information to device programming register from the OX bus during write. X BUFFERED BUS 6120/6121 INTERFACING EXAMPLE 51/0 PORTS 51/0 PORTS GND 1+----r--II--,.-.......L+-+--.j~----L_+__l-.J_..lDll!X!l;O·ll"- NOTE: This simplified example does not show the extended Memory Addressing and other features of the 6120. BUFFERED DXBUS
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