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XX-E4BD7-03
May 2000
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HD-6120
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XX-E4BD7-03
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19
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http://bitsavers.org/pdf/dec/pdp8/cmos8/_dataSheets/HD-6120.pdf
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HD-6120 mJHARRIS CMOS HIGH SPEED 12 BIT MICROPROCESSOR Pinout Features • LOW POWER, 50 MW OPERATING, 2 MW STATIC • SINGLE SUPPLY - SV • OPERATION FROM DC TO 5.1 MHZ • INDUSTRIAL AND MILITARY TEMPERATURE RANGES • DN-CHIP CRYSTAL OSCILLATOR CIRCUITRY • ON-CHIP EXTENDED MEMORY ADDRESSING-32K MAIN MEMORY, 32K CONTROL PANEL • OPTIMIZED MICRO-CODE MINIMIZES THE NUMBER OF CLOCK CYCLES REQUIRED FOR ALL INSTRUCTIONS • TWO ON-CHIP STACK POINTERS • SIMPLIFIED MEMORY AND I/O CONTROL SIGNALS FOR EASY HARDWARE INTERFACING • VECTORED INTERRUPT CAPABILITY • SOFTWARE IS PAGE RELOCATABLE Description The HD-6120 is a general purpose high speed, CMOS 12 bit microprocessor. It is designed to recognize the instruction set of Digital Equipment Corporation's PDP-6/E' minicomputer. Many architectural, functional and processing enhancements have been designed into the 6120 such that it can provide much higher system performance than its predecessor, the 6100. 00i' RUN 1 2 3 4 5 6 REffi" 7 ACK 8 9 10 11 12 13 14 OMAGNT OMAREQ SKiP RUN/HLT OSCIN OSCOUT IFETCH OXO OXI OX2 OX3 OX4 OX5 OX6 OX7 VSS HO·6120 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC READ WRi'i'E MEMSEL iOcLR CiffiAR ext;WI LXPAR EiAi'AF INTGNT iiiii'REa' CPREa STRTUP EMA2 Cl/01 CO/CO OXll OX10 OX9 OX8 The 6120 is targeted toward the experienced PDP-6' or 6100 user. Twelve bit accuracy, rapid interrupt response, battery backup and low power (sealed enclosure) capability all equate to a processor ideally suited to real time control applications such as data acquisition, industrial control and harsh environment military systems. • TRADEMARK DF DIGITAL EQUIPMENT CORP. Functional DIagrams cpu 12 CONTROL DX BUS XTAL INPUTS INTERRUPT CONTROL DMA 12 I/O CONTROL AND DEV CONTROL VCC GND CAUTION: Electronic device. are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed. DEV CONTROL Specifications HO-6120 ABSOLUTE MAXIMUM RATINGS Supply Voltage Operating Voltage Range Input/Output Voltage Applied Storage Temperature Range Operating Temperature Range Industrial (-9, -9+) Military (-2, -S) Maximum Power Dissipation +S.OVOLTS +4Vto +7V VSS-O.3V to VCC+O.3V -65°C to + 150°C -40°C to +S5°C -55°C to +125°C 1 Watt CAUTION: Stresses above those listed in the "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device. This Is a stress only rating and operation of the device at these or any other conditions above those Indicated in the operational sections of this specification Is not Implied. D.C. ELECTRICAL CHARACTERISTICSj VCC=S.OV±S%j TA = Industrial or Military SYMBOL PARAMETER MIN VIH LOGICAL ONE INPUT VOLTAGE 70%VCC VIL LOGICAL ZERO INPUT VOLTAGE VIH(CLK) LOGICAL ONE CLOCK VOLTAGE VIL(CLK) LOGICAL ZERO CLOCK VOLTAGE MAX UNITS TEST CONDITIONS V 30% VCC VCC-0.5 V V VSS+0.5 V 50% duly cycle Ir, If .. 20 ns 50% duly cycle Ir, If" 20 ns VTH+ SCHMITT TRIGGER POSITIVE THRESHOLD 50%VCC VCC-0.5 V REsET, 'DMAREQ, CPREQ VTH- SCHMITT TRIGGER NEGATIVE THRESHOLD 0.5 30% VCC V RESET, DMAREQ, CPREQ VOH LOGICAL ONE OUTPUT VOLTAGE VCC-0.5 V 10H = -1.6mA VOL LOGICAL ZERO OUTPUT VOLTAGE 0.5 V 10L = 1.6mA ilL INPUT LEAKAGE CURRENT -10 10 p.A OV.. VIN .. VCC 10 OUTPUT LEAKAGE CURRENT -10.0 10.0 p.A OV.. VO .. VCC ICC POWER SUPPLY STANDBY CURRENT 500 p.A VIN=VCC or GND VCC = 5.25 V RESET STATE OUTPUTS OPEN ICC· POWER SUPPLY OPERATING 10 ma VIN=VCC or GND VCC = 5.25 V F = 5.1 Mhz OUTPUTS OPEN 10SH HOLD CURRENT DURING DMAGNT -0.2 -0.6 -10.0 ma p.a Voul = VCC-l.0V Voul = OV LXMAR, LXPAR, READ. WRITE, OUT AND MEMSEL lOSS HOLD CURRENT DURING lOT SAMPLE TIMES -1.6 -10.0 ma Voul = OV CO, Cl , AND SKIP OUTPUTS lOSS HOLD CURRENT DURING lOT SAMPLE TIMES -50 -250 p.a Voul= OV INTREQ OUTPUT CIN* INPUT CAPACITANCE 5 pi FREQ = 1 MHZ TA=25'C VIN=VCC or GND COUP OUTPUT CAPACITANCE 15 pi FREQ = 1 MHZ TA=25'C VIN=VCC or GND * Guaranteed and .ampled, but not 100% tested Specifications HD·6120 A.C. ELECTRICAL CHARACTERISTICS; YCC=5.0Y±5%; TA=lndustrial or Military; CL=50 pf, FREQ=5.1 MHZ SYMBOL PARAMETER MIN MAX UNITS 5.1 Mhz F OPERATING FREQUENCY 0 T MINOR CYCLE PERIOD 392 ns TL LXMAR, LXPAR, LXDAR PULSE WIDTH 125 ns TAS ADDRESS SET UP TIME 60 ns TAH ADDRESS HOLD TIME 180 ns TREAD READ ACCESS TIME 720 ns TRS READ SET UP TIME 135 ns TRH READ HOLD TIME 20 ns TRP READ PULSE WIDTH 425 ns TRD READ PULSE DELAY 40 ns TWPD WRITE PULSE DELAY 200 ns TWS WRITE SET UP TIME (ALL NON lOT) 375 ns TWP WRITE PULSE WIDTH (ALL NON lOT) 425 ns TWH WRITE HOLD TIME (ALL NON Ion 200 ns TWSIO WRITE SET UP TIME (lOT) 200 ns TWIO WRITE PULSE WIDTH (lOT) 375 ns TWHIO WRITE HOLD TIME (lOT) 125 ns TDA READ ACK DELAY FOR NO WAIT 150 ns TXA WRITE ACK DELAY FOR NO WAIT 150 ns TEST CONDITIONS T = 21F F=5.1 Mhz MEMORY OPERATIONS F=5.1 Mhz NOTE: All measurements are taken with input rise and fall tim$s .s;;: 20 nsec. DECOUPLING CAPACITORS The transient current required to charge and discharge the 50 pF load capacitance specified in the 6120 data sheet is determined by i = CL (dv/dt) Assuming that ali DX outputs change state at the same time and that dvldt is constant; i '" CL (VCC x 80"10) tA/tF where tR=20 ns, VCC=5.0 volts, CL=50 pF on each of twelve outputs. i '" (12 x 50 x 10-12 ) x (5.0v x 0.8)/(20 x 10-9) '" 120mA This current spike may cause a large negative voltage spike on VCC, which could cause improper operation of the device. To filter out this noise, it is recommended that a 0.1 /JoF ceramic disk decoupling capacitor be placed between VCC and GND at each device, with placement being as near to the device as possible. It is recommendedlthat for systems with greater than 50 pF loading on the DX outputs that Harris HD-6432 CMOS Hex Bi-directional bus drivers be used to buffer the 6120 from the rest of the system. The HD-6432 bus driver has Iluaranteed performance specifications up to a 300 pF load. MINOR CYCLES ACK OuT 1IIIIIIIn d 11 I I t-TRD I LSSSSS I !--- IF~CH --~--~~~~~~~----~-------INSTRUCTION F~CH DATAF <XXI k C INDIRECT READ MEMORY READ OPERAilON MINOR CYCLES ACK I-- T -.f-. Note 1 -I jllllllllllllllll ISSSSS I I iiA'iiF §Oar INDIRECT ~ NOTE t: This cycle Is deleted on PACt, PAC2, PPCt, PPC2 and control panel Interrupt writes. MEMORY WRITE OPERATION "NOR CYCLES t-- T ---I M ~I~--------________________________~r- ~or.:J laTAS laTAH_I DXi;:A2C1 ,:=x iIms >------< ADORESS _-+1----, ~TREA}- TRP I IiEIiiEL - - - - - - . . ; I M I- 77 77 7 7 77 7 7 J ACK TRD--1 ~ DATA !-TRS-++TRH xxm ,INDIRECT I I ~TWP~ .--! I I H-TXA ! \ \ \ v 7 7 7 7 7 7 71 ____________________ I MEMORY READ·MODIFY·WRITE OPERATION CO,C1,EMA2 m DAFTWP~~ ~TR~ ~ I L-I_,..-III LT::-L I I I r-:1~:"'-_~C1!.:=:..cLc--:....1 I+- TRP . , I C1 =H SKiP iiEAo -.! _.., ffiIT _ _ _ _ _ _~----~-~I~-~c~1~-~H-._~--TXAM ACK 7 77711 777771 I TDA I- ~I K$V 7 11 111 I 1\ \ \ \ \ INTGNT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---I i5l\iiF ---'L.___ ..J NOTES: I-- ~ I~~--------~~ ~= C DATA \--TWS-l TWH Operation is shortened one Minor Cycle if READ is not executed. .. Read Data must be held until the risinq ~e of LXDAR for Read lOTs. EXTERNAL lOT OPERATION MINOA CYCLES I-- T --I LX~~1~AA, ~-~----------------------------------rc::- AEAD r 1"1 TAP-j --------...;1 TAO OuT 7777( I ;"1------------------- -l TAS t-TAD ~ ,-I-------------- ~ DX~DAT~ TDA ACK I_ '"I I 7777777777! CO, C1, EMA2 ~m~,-- DIffiW~~A- KSSSSSSSSSSSSSS ___________ E8& .......... ...;D;;.;.F_________________.... ________________________________ ~~~ OR SWITCH REGISTER (OSR) MINOA CYCLES I-- T --i ~~lc~,~--r------------------------rc::::--\4- TWP --.! WFffi"E' _______-11 I OUT 1;-------------_ . I I \\\\\\\\1 I r- -1 rTWS DX~ ACK CO, C1, EMA2 DATA TWH ~ zzzzzz;);x;i k\\\\\\\\\\ -'7_JoL-_________::.:DF____________-"!S&O&~..::..:::.. DATAF rn_~ ________________ WRITE TO SWITCH REGISTER .......:.....;.._ ~f"S"S3 Pin Assignments 1/0 Pin Symbol Active Level 0 1 OUT Low Description Bus timing control output which is low during all bus write or addressing operations. This signal Is used to enable outbound bus drivers. 6 2 DMAGNT High Direct memory access grant output- OX, CO, C1 , and EMA2 lines are high Impedance. I 3 i5MAFiEci Low Schmitt trigger Input. Direct memory access request-DMA Is granted althe end of the current bus operation. Upon DMA grant, the 6120 suspends program execution until the BMAREQ line Is pulled high. I 4 SKiP Low Input which causes the 6120 to skip the next Instruc1lon if low during an I/O Instruction. I 5 RUN/HLT 0 6 J!iUR Low This output Indicates the operating state olthe 6120. It Is low at all times eiccept during the reset and halt states. I 7 RESET Low Schmitt trigger Input. Clears the AC and the memory extension registers and loads 7777 (octal) Into the PC. RUNHLT Is set. The STRTUP line controls whether execution starts In control panel or main memory. RESET must be held low at least 42 clock cycles alter the clock starts running In order to Initialize the timing generator. LXDAR Is held low while RESET is low, and remains low until after the positive transition of J!im'i' and 10CLR. I 8 ACK High This Input Indicates that peripheral or external memory Is ready to transfer data. The 6120 read or write state gets extended as long as ACK Is low. During this time the 6120 Is in the lowest power state with clocks running. I 9 OSCIN 0 10 OSCOUT 0 11 IFETCH Low Instruction fetch cycle output. I/O 12-19, 21-24 20 DXODX11 VSS High Multiplexed bldirec1lonal data In, data out and address lines. (DXO=MSB, DX11-LSB.) Most negative supply voltage. I/O 25 CO/~ Pulsing the RUN/HLi" Input causes the 6120 to alternately run and ha~ changing the state of the Internal RUNHLT flip flop on the positive transition 01 the RUN! line. Input to crystal oscillator amplilier. (Also external clock input.) Output of crystal oscillator amplifier. Multiplexed extended memory addreas (EMA) active high output MSB and peripheral devlce'controiline active low Input from the peripheral device during an I/O transfer. Multiplexed EMA bit 1 and peripheral control line. See CO. I/O 26 C1/01 0 I 27 28 EMA2 STRTUP High Low order extended memory address output. This Input is tied to either VCC or VSS. II tied to VSS, the 6120 makes a panel request (caused by the PWRON lIag) as soon as ~goes to VCC. 7777 Is stored In location 0000 offield 0 01 panel memory. II STRTUP Is tied to VCC, PWRON does not cause a panel request. Instead, the CPU starts running In location 7777 of field 0 01 main memory. Location 0000 of main memory Is not altered. I 29 C'PREQ Low Schmitt trigger input. External control panel regues a dedicated Interrupt which bypasses the normal device Interrupt request structure. CPRE causes a control panel Interrupt request by setting the bootstrapllag with the negative going transition of CPREa. Therefore, this Input is transition rather than level sensitive. I 0 30 31 iNi'REQ iifflmi' Low Low Peripheral device Interrupt request input. Peripheral device Interrupt grant output. 0 32 i5Ai'AF' Low Output which Is low whenever the Data Field Is placed on the CO, C1 and EMA2 lines. 0 33 LX PAR Low Output which causes control panel memory address register to be loaded. Same as LXMAR, but for control panel memory operations. 0 34 LXMAR Low Output which causes main memory address register to be loaded. Address is strobed Into the main memory at the falling edge of LXMAR. 0 35 LXDAR Low 0 38 10CLR Low Output which causes device address register to be loaded. Same as LXMAR or LXPAR, except for lOT operations. Also used to distinguish between 10CLR Signals. See 10CLR below. Output which is low when RESET is low, or when CAF instruction Is given. US!!!.l2.!<!ear I/O lIags. II caused by RESET, LX(5)iil!f Is low during and alter the trailing edge ofIOCLR. 0 37 MEMSE[ Low 0 38 WRITE Low 0 39 READ Low 40 VCC e- Memory selec1. During memory operations, this output pulses to VSS at bus read and write times. Write pulse. This output is low during all bus data write operations; memory, I/O, and write to switch register. Read pulse. This output is low during all bus read operations; memory, I/O and switch register. It also serves the function of enabling Inbound bus drivers. Positive supply voltage. Major Registers ACCUMULATOR (AC) PROGRAM COUNTER (PC) The AC is a 12-bit register with which arithmetic and logical operations are performed. Data words may be fetched from memory to the AC or stored from the AC into memory. Arithmetic and logical operations involve two operands, one held in the AC and the other fetched from memory. The result of the operation is left in the AC. The AC may be cleared, complemented, tested, incremented or rotated under program control. The AC also serves as an input-output register. All programmed data transfers pass through the AC. The 12-bit PC contains the address of the memory location from which the next instruction is fetched. During an instruction fetch, the PC is transferred to Ol and the PC is then incremented by 1. When there is a branch to another address in memory, the branch address is set into the PC. Branching normally takes place under program control. A skip (SKP, SMA, SZA, SNl, etc.) instruction increments the PC by 1 (again), thus causing the next instruction to be skipped. The skip instruction may be unconditional or conditional on the state of the AC and/or LINK. During an input-output operation, a device can also cause the next instruction to be skipped. Link (L) l is a 1-bit flip flop that serves as a high-order extension of the AC. It is used as a carry flip flop for 2's complement arithmetic. A carry out of the AlU complements L. l can be cleared, set, complemented and tested under program control and rotated as a part of the AC. MO REGISTER (MO) The MQ is a 12:bit temporary register which is program accessible. The contents of AC may be transferred to the MQ for temporary storage. MQ can be OR'ed with the AC and the result stored in the AC. The contents of the AC and the MQ may also be exchanged. OUTPUT LATCH (Ol) While accessing memory or I/O, all data or addresses generated by the 6120 on the OX bus are held in the Ol for the time required on the bus. This frees the 6120 internal bus for other uses during these operations. The output latch can also be read to the 6120 internal bus so that it can function as a temporary holding register for internal operations. TEMPORARY REGISTER (TEMP) The 12-bit TEMP register latches the result of an ALU operation before it is sent to the destination register to avoid race conditions. The TEMP is also used as an internal register during instruction execution. INSTRUCTION REGISTER (IR) During an instruction fetch, the 12-bit IR contains the instruction that is to be executed by the 6120. STACK POINTERS (SP1 and SP2) The stack pointers are two twelve-bit registers which hold the address of the next stack storage location. PPCX or PACX instructions cause post-decrement of the contents of stack pointer SPX. RTNX or POPX cause a pre-increment of the contents of the stack pointer. Stack pointers are loaded from, and read into, the AC. They may also be used as programcontrolled temporary registers. Memory Extension Control Registers INSTRUCTION SAVE FIELD (ISF) INSTRUCTION FIELD (IF) The 3-bit Instruction Field holds the memory field from which all instructions, all indirect address pOinters and all directly addressed operands are obtained. It may be read into the AC, and loaded from the lB. It is cleared by RESET. INSTRUCTION BUFFER (IB) The 3-bit Instruction Buffer serves as a holding register for instructions which change the IF. Instead of changing the IF directly, field bits are loaded into the IB, and transferred to the IF althe next JMP, JMS, RTN1 or RTN2. The IB may be loaded from instruction bits, from the AC or from the ISF. The IB is cleared by RESET. The 3-bit ISF is loaded with the contents of the IF upon granting of an interrupt. The ISF may be read into the AC. It is cleared by RESET. DATA FIELD (OF) The 3-bit Data Field holds the memory field from which all indirectly addressed operands are obtained. The OF may be loaded from instruction bits, from the AC or from the DSF. It may be read into the AC. It is cleared by RESET. DATA SAVE FIELD (DSF) The 3-bit DSF is loaded with the contents of the OF upon granting of an interrupt. The DSF may be read into the AC. It is cleared by RESET. Basic Timing and State Control A 1S-bit address is sent on the CO, C1 ,EMA2 and OX lines for memory reference instructions. The lXMAR or lXPAR signals cause an external register to store the address information if required. When executing an input-output instruction, LXDAR causes an external register to be loaded with device address and control information. Memory data is read for an input transfer (READ). ACK controls the transfer duration. If ACK is low during input transfers, the 6120 waits with the READ line low. The high state of the ACK signal causes the 6120 to continue. Output transfers are similar to input transfers. The address is defined as given above. ACK controls the length of time for which the WRITE signal is low, similar to the READ line control. During an instruction fetch the instruction to be executed is retained internally and then executed. During the sequencing of the instruction the external request lines are sampled by the priority network. The state of this network decides whether the machine is going to fetch the next instruction in sequence or service one of the internal or external request lines. Internal Priority Structure GENERAL DESCRIPTION The external request lines and the internal request flags are sampled in ,an internal priorit~w~ internal riorlty is RESET, DMAREQ, RUN/HIT, CPREO, INTRE , and IFETCH. The state of the priority network determines the next operation. IFETCH If no external or internal requests are pending, the 6120 fetches the next instruction pOinted to by the contents of the PC. The iF"Ei'CR line is low during the cycle in which the instruction is fetched. RESET R'ESEi' initializes all internal flags and clears the AC, LINK and MO. All memory extension bits (IF, IB, DF,ISF and DSF) are Cleared. The interrupt enable and interrupt inhi.!2i!!!lp flops are cleared. RUNHLT is set to the run state. The RUN line is held high by RESET. The states of SP1 and SP2 are undefined at power up, and are unaffected by RESET. Upon application of power, the Internal timing generator is completely initialized within 42 clock pulses after power is within limits with RESET held low. The 6120 remains in the reset state as long as the RESET line is low. LXMAR, L:XPAR, READ. WRITE, iYiEMSEL. INTGNT and IFETCH are held high. IOCLR is held low. After RESET is changed from low to high, IOClR is made high. lXDAR Is held low for one minor cycle after IbelR Is high. DMAGNT and OUT are low. The first LXMAR or LXPAR occurs 5-1/2 minor cycles after IOCLR goes high. The PC is set to 7777 (octal) and execution commences in control panel or main memory, depending on whether the STRTUP input is low or high respectively. If execution commences in control panel memory, the FZ flag is set, the Panel Data flag is cleared, and 7777 is deposited in location 0000 of control panel memory before beginning instruction execution at location 7777. If execution commences in main memory, location 0000 of main memory is not modified. RUN/HLT The RUN/HlT line changes the state of the RUNHLT.llie.!!Qp. This flip flop l!lnitially placed in the run state by RESET. PulSing RUN/HlT low causes the 6120 to alternately run and halt. This Is true whetl!!r..executlng in main memory or control memory. The RUN/HLT line Is normally hl9.!1 The 6120 recognizes the positive transition of the RUN/HlT signal. The HLT instruction (7402 octal) does not cause the RUNHLT flip flop to be cleared, but causes entry into panel mode with the HlTFLG set. Memory Organization The 6120 has a basic addressing capacity of 4096 12-blt words. The addressing capacity is extended by the internal extended memory control hardware. The memory system is organized in 4096 word groups, called memory fields. The first 4096 words of memory are in field O. If a full 32K block of memory is Installed, the uppermost memory field will be numbered 7. Two 32K word blocks of memory may be connected to the 6120. One of these blocks is known as main memory and the other is known as panel memory. In any given memory field, every location has a unique 4 digit octal (12 bit binary) address, 0000 to 7777 (0000 to 4095 decimal). Each memory field Is subdivided Into 32 pages of 128 words each. Memory pages are numbered sequentially from page 00, containing octal addresses 0000-0177, to page 37 (octal), containing octal addresses 7600-7777. The most significant 5 bits of a 12-bit memory address denote the page number and the 7 low order bits specify the address of the memory location within the given page. During an instruction fetch cycle, the 6120 fetches the instruction pOinted to by the IF, PC, and address strobes LXMAR or LXPAR. The contents of the PC are transferred to the OL. The PC is incremented by 1. The PC now contains the address of the 'next' sequential instruction. The OL now contains the address of the 'current' instruction which must be fetched from memory. Bits 0-4 of the OL identify the current page, that is, the page from which Instructions are currently being fetched. Bits 5-11 of the OL identify the location within the current page. (Page zero, by definition, denotes the first 128 words of memory within a field, octal addresses 00000177.) Memory Reference Instructions (MRI) The memory reference instructions operate on the contents of a memory location or use the contents of a memory location to operate on the AC or the PC. Bits 0-2 of a memory reference Instruction specify the operation code, or opcode, and the 9 low-order bits specify the operand address. Bits 5-11, the page address, identify the location of the operand on a given page, butthey do not identify the page itself. The page is specified by bit 4, called the page bit. If bit 4 is a 0, the page address Is Interpreted as a location on page O. If bit 41s a 1, the page address Is Interpreted to be on the current page. The entire 12-bit address, consisting of the 7 low-order bits from the instruction and either 0 or the contents of the OL in the 5 high-order bits is known as the instruction address, or IA. The IF provides the 3 high-order bits of the complete 15-blt address, IA. Other locations are addressed by utilizing bit 3. When bit 31s a 0, the operand Is directly addressed, and IA is the location of the operand. When bit 3 is a 1, the operand Is indirectly addressed, and the contents of IA specify the location of the operand. To address a location that Is not on page 0 or the current page, the absolute address of the desired location Is stored In one of the 256 directly-addressable locations as a pointer address. The instruction addresses the operand indirectly through this pOinter. Upon execution, the MRI operates on the contents of the location Identified by the address contained In the pointer location. The pointer is obtained from the current Instruction Field; the data Is In the current Data Field. It should be noted that locations 0010-0017 (octal) in page 0 of any field are autoindexed. If these locations are addressed as indirect pOinters, the contents are incremented by 1 and restored before they are used as the operand address. These locations may, therefore, be used for indexing applications. During the memory write operation, the OF appears on CO, C2, and EMA2. Indirect reference to auto index registers from page 0 work as defined whether the page bit is "1" or "0". Data is represented in two's complement integer notation. In this system of notation, the negative of a number is formed by complementing each bit in the data word and adding "1" to the complemented number. The sign is Indicated by the mostsignificant bit. In the 12-bit word used in the 6120, when bit 0 Is a "0", It denotes a positive number and when bit 0 is a "1", it denotes a negative number. The number range for this system is +3777 to -4000 octal (+2047 to -2048 decimal). Microprogramming Group 1, 2 and 3 instructions are all microprogram mabie. This means that as many as five discrete instructions can be combined into one instruction which can execute in the same amount of time required for a single discrete instruction. Instructions listed under Groups 1, 2 and 3 represent the most commonly used microcoded instructions for these groups and are not a complete listing of all possible instructions. The general rule of thumb is that if an instruction can be rep- resented in machine code (using the "Microinstruction Format" templet), then it is a legal instruction. The logical sequence table which accompanies each "Microinstruction Format" templet shows the order in which the microcoded operations are performed. "Introduction to Programming" by Digital Equipment Corporation further explains the PDP-B" instruction set and the use of microprogramming. This handbook is also available from Harris Semiconductor. • Trademark of Digital Equipment Corporation HD-6120 OSCillator Requirements C2 = 20pf. is normally used. For Cl = 32pf. Cl and C2 would be approximately 47pf. The actual values are normally not critical unless an ultra precise frequency is desired. The HD-6120 has been designed to work with either a parallel resonant, fundamental mode crystal or an external frequency source. EXTERNAL CRYSTAL C1 When using an external crystal, two capacitors and a resistor are required to complete the oscillator circuit. Table 1 lists the required crystal characteristics and Figure 1 shows the correct circuit connections. OSCIN E' TABLE 1 Parameter Load Capacitance R••ri •• (Max.) c:::J 10 HD-6120 MO 10 OSCOUT C2 1\tpical Characteristic 2.4 - 5.1 Mhz Parallel resonant, AT cut, Fundamental mode Cl = 20pf or 32pf 200 n at 5.1 Mhz Frequency Type of Operation 9 FIGURE 1 EXTERNAL FREQUENCY SOURCE When using an external frequency source, the duty cycle should be 50/50 with rise and fall times less than 20ns. Input voltage levels should be VIH;oVCC-0.5V and Vll,.;;0.5V. The OSCIN pin of the HD-6120 is used in this case with the OSCOUT pin left open. The Harris B2CB4A CMOS Clock Generator is an excellent external frequency source which provides three outputs at different divide ratios (+1, +3, +6). The load capacitors Cl, C2 are chosen such that the total (including stray) capacitance seen by the crystal matches the specified load capacitance (Cl). ForCl = 20pf. avalueofCl = Memory Reference Instructions MICROINSTRUCTION FORMAT o 2 3 OP CODE (0-5) Indirect Addressing D = Direct 1 = Indirect -------1 Mn. monic Opcode Minor Cycles Dlr Ind Auto AND Oxxx 7 10 TAD 1xxx 7 10 ISZ 2xxx 9' 12' DCA 3xxx 7 10 JMS 4xxx 7 10 JMP 5xxx 4 7 • Add two Minor Cycles If a skip IS taken. 4 5 6 7 8 9 10 11 14----PAGE RELATIVE ADDRESS---~ Memory Page D = PageD 1 = Current Page Operation LOGICAL AND: Causes a bit-by-bit boolean AND between the contents of the Accumulator and thl! contents of the effective address (xxx) specified by the instruction. The result is lett in the AC and the data word In the referenced location Is not altered. 12 TWO'S COMPLEMENT ADD: Performs a binary two's complement addition between the specified data word and the contents of the AC; the result is lett In the AC. If a carry out occurs, the state of the Link Is complemented. If the AC is initially cleared, this instruction acts as a load from memory. 14' INCREMENT AND SKIP IF ZERO: The contents of the effective address is incremented by 1 and restored. If the result is zero, the next sequential instruction is skipped. 12 DEPOSIT AND CLEAR THE ACCUMULATOR: The contents of the AC are stored in the effective address and the AC is cleared. 12 JUMP TO SUBROUTINE: The contents of the PC is stored in the effective address and the effective address + 1 is stored in the PC. The Link, AC and MQ are unchanged. JUMP: The effective address is loaded into the PC thus causing program execution to branch to a new 9 location. 12 Group 1 Operate Instructions All group 1 instructions require 6 minor cycles, except those performing an ATA, ATl, or BSW instruction (8 minor cycles). MICROINSTRUCTION FORMAT o 2 3 4 5 6 7 8 9 10 11 0 ClA Cll CMA CMl A1 R2 A3 lAC S~ Rl 0 0 0 0 1 1 1 1 R2 0 0 1 1 0 0 1 1 R3 0 1 0 1 0 1 0 1 No Rotate SSW RAL RTL RAR RTR R3L Do Not Use Logical Sequence: l-CLA, CLL 2-CMA, CML 3-IAC 4-RAR, RAL, RTR, RTL, BSW, R3L Mnemonic Opcode Logical Sequence Operation NOP . 7000 1 No operation . lAC 7001 3 SSW RAl 7002 7004 4 4 Increment accumulator-the contents of the AC is incremented by 1. Carry out complements the LINK. Sy1e swap-ACO-S are exchanged with AC6-11 respectively. The LINK is not changed. RTl 7006 4 RAR 7010 4 Rotate accumulator left-the contents olthe AC and LINK are roteted one binary pos~ion to the left. ACO Is shifted to LINK and LINK is shifted to AC11. Rotate two lelt- equivalent to two RAL:s. Rotate accumulator right-the contents of the AC and LINK are rotated one binary position to the right. AC11 Is shifted into the LINK, and LINK is shilted to ACO. RTR 7012 4 Rotate two right - equivalent to two RAR's. R3l CMl 7014 7020 4 Rotate AC (but not LINK) left 3 places. ACO is rotated into AC9, AC1 into AC1 0, etc. Complement LINK -the contents of the LINK is complemented. CMA 7040 2 Complement accumulator -the contents 01 the AC is replaced by its l's complement. CIA 7041 2,3 Complement and Increment accumulator - the contents of the AC is replaced by its 2's complement. Cll 7100 1 Clear LINK-the LINK is made O. Cll RAl 7104 1,4 Clear LINK, rotate left. CllRTl ClLRAR 7106 7110 1,4 1,4 Clear LINK, rotate two left. CllRTR 7112 1,4 Clear LINK, rotate two right. 2 Clear LINK, rotate right. STl 7120 1,2 Set the LINK -load binary 1 Into LINK. ClA 7200 1 Clear accumulator -load AC with 0000. ClAIAC 7201 1,3 Clear and increment accumulator -load AC with 0001. GlK STA 7204 7240 1,4 1,2 Get LINK-place LINK In AC11; clear ACO-10 and LINK. ClACll 7300 1 Set accumulator- make AC=7m. Clear AC and LINK. Group 2 Operate Instructions All group 2 instructions require 7 minor cycles, except OSR and LAS (8 minor cycles). MICROINSTRUCTION FORMAT Logical Sequence: 1 - (BIT 8=0) - SMA or SZA or SNL - (BIT 8= 1) - SPA andSNA and SZL 2-CLA 3-0SR. HLT Mnemonic Opcode Operation Logical Sequence NOP 7400 1 No operation HLT 7402 3 Set the HLTFLG. Causes entry into panel mode instead of executing the next instruction provided IIFF is not set. If IIFF is set. panel mode Is entered after the JMP. JMS. RTN1 or RTN2 which clears IIFF. This Instruction in panel mode does not cause a re-entry Into panel mode, but does set HLTFLG. OSR 7404 3 OR with switch register-the contents of an external device are "OR"ed with the contents of the AC. and the result stored in the AC. The contents of the DF are available for device selecllon. SKP 7410 1 Skip-the content Of the PC is incremented by 1.to skip the next instruction. SNL 7420 1 Skip on non-zero LINK-skip If LINK one SZL 7430 1 Skip if LINK zero SZA 7440 1 Skip on zero accumulator-skip if AC=OOOO SNA 7450 1 Skip on non-zero accumulator SZASNL 7460 1 Skip if AC=OOOO or if LlNK= 1 SNASZL 7470 1 Skip If AC not 0000 and if LINK is zero SMA 7500 1 Skip on minus accumulator (ACO= 1) SPA 7510 1 Skip on positive accumulator (ACO=O) SMASNL 7520 1 Skip If AC Is minus or If LINK is 1 SPASZL 7530 1 Skip if AC is plus and if LINK is 0 SMASZA 7540 1 Skip if AC is minus or zero SPASNA 7550 1 Skip if AC is positive and non-zero SMASZA SNL 7560 1 Skip if AC is minus or if AC is =0000 or if LINK is 1 SPASNA SZL 7570 1 Skip if AC is positive. nonzero and if LINK is zero CLA 7600 2 Clear accumulator LAS 7604 2.3 Load accumulator from switch register SZACLA 7640 1.2 Skip If AC=OOOO. then clear AC SNACLA 7650 1.2 Skip on non-zero accumulator. then clear AC SMACLA 7700 1.2 Skip on minus AC. then clear AC SPACLA 7710 1.2 Skip on positive AC. then clear AC Group 3 Operate Instructions If bits 6, 8, 9 or 10 are set to a one, instruction execution is not altered but the instruction becomes uninterruptable by either..Q§!)el or normal interrupts. That is, the next instruction is guaranteed to be fetched barring a reset, DMAREO or RUN/HlT flip flop in the HlT state. Group 3 Operate Instructions All group 3 instructions require 6 minor cycles. MICROINSTRUCTION FORMAT o 2 3 4 5 ClA MOA 6 logical Sequence: l-ClA 2-MOA. MOL 3 - All OTHERS • - CAUSES INSTRUCTION TO IGNORE INTERRUPTS IF A "I'" 8 7 9 10 11 MOL BIT 4 0 0 0 0 1 1 1 1 5 0 0 1 1 0 0 1 1 7 0 1 0 1 0 1 0 1 NOP AC..... MO.O..... AC (MO + AC) ..... AC MO.....AC O..... AC O.....AC: O..... MO MO..... AC MO..... AC.O..... MO + denotes logical OR Mnemonic Opcode logical Sequence NOP MOL 7401 7421 3 2 MOA 7501 2 Operation No operation MO register load-the MO is loaded with the contents of the AC and the AC is cleared. The original contents of the MO is lost. MO "OR" with accumulator-the contents of the MO is "OR'"ed with the contents of the AC. and the result left in the AC. The MO is not modified. Swap contents of AC and MO - the contents of the AC and MO are exchanged SWP 7521 ClA 7601 CAM 7621 3 1 3 ACl 7701 3 load AC with contents of MO ClASWP 7721 3 Clear AC. then swap - the MO is loaded into the AC; 0000 is loaded into the MO Clear accumulator Clear AC and MO (actually a ClA MOL) Stack Operation Instructions The following lOT Instructions are internally decoded to perform stack operations using Internal stack pointers SP1 and SP2. These are internal lOT instructions; the iJ<i5AR' signal is not generated. If Instructions are being fetched from main memory, the stacks are located in field 0 of main memory. If instructions are being fetched from panel memory, the stacks are located in field 0 of panel memory, except for the Mnemonic Opcode case of a ReTurN from control panel memory via a RTN1 or RTN2 instruction. In this case, the main memory stack is accessed by the Instruction fetched from panel memory. Two separate stacks may be maintained - one for the PC, the second for the AC. An increment of the stack pointer is defined as a pop off the stack. Operation PUSH PC ON STACK. The contents of the PC are Incremented by one and the result Is loaded Into the memory location pointed to by the contents of SP1. SPI Is then decremented by 1. 6245 PUSH PC ON STACK. The same as PPCl except that SP2 Is used as the memory pointer. PPC2 PUSH AC ON STACK. The contents olthe AC Is loaded Into the memory location painted to by the contents of SPI. The PACI 6215 contents of SPI Is then decremented by 1. PAC2 PUSH AC ON STACK. The same as PACI except that SP2 is used as the memory pointer. 6255 RTNI RETURN. The contents of the stack pointer (SP1) Is Incremented by one. The oontents of the Instruction Buffer (IB) Is 6225 loaded Into the Instruction Field (IF) register. If a prior PEX Instruction was executed, the Control Panel Flip Flop (CTRLFF) is cleared. If the Interrupt Inhibit Flip Flop (IIFF) Is set, then the Force Zero (FZ) flag Is cleared. The contents of the memory location pointed to by SPI Is loaded Into the PC. Prior PEX Is cleared. RTN2 Same as RTN 1 except that SP2 is used as the stack pointer. 6265 POPI The contents of SPlis Incremented by 1. The contents of the memory location pointed to by SPI is then loaded Into the 6235 AC. POP2 6275 Same as POPI except that SP2 Is used as the stack pointer. RSPI The contents of SPI Is loaded Into the AC. 6207 RSP2 6227 The contents of SP21s loaded into the AC. LSPI 6217 The contents of the AC Is loaded into SPI. The AC Is cleared. LSP2 6237 The contents of the AC Is loaded Into SP2. The AC Is cleared. CAUTION: When swffchlng between main and control panel memory, the stack pointer. must be saved and restored, PPCl 6205 Internal Control Instructions Note that these Instructions apply If the 6120 Is executing Instructions from main memory or control panel. Mnemonic Opcode ION 6001 IOF 6002 RTF 6005 Operation Turn on Interrupt system. The Interrupt Enable Flip Flop Is set. Neither INTREQ or any control panel request will be granted until after execution of the next Instruction. (6 minor cycles.) Turn off Interrupt. The interrupt enable flip flop Is cleared Immediately. If'i'N'i'RECi Is low while this Instruction Is being processed, the interrupt will not be recognized. (6 minor cycles.) Load the following from the AC: ACblt To 0 1 4 6-8 9-11 SGT CAF 6006 6007 WSR 6246 GCF 6256 LINK GT IEFF IB OF The IIFF is set. The AC is cleared following the load operation. (8 minor cycles.) Skip if the GT flag Is set. (7 minor cycles.) The AC, LINK and GT flag are cleared. Interrupt enable flip flop is cleared. 10CLR is generated with LXOAR high, causing peripheral devices to clear their flags. (7 minor cycles.) Write to switch register. The contents of the AC are written to an external device using a special 1/0 transfer. The AC is then cleared. The contents of the OF are available for device selection. OATAF Is asserted. (7 minor cycles.) Get current fields. The following bits are loaded into the AC: ACblt Function 0 LINK 1 GT!.!!L2 1 if INTREQ is low oif iiii'i'REQ is high 3 PWRONflag 4 IEFF 5 0 6-8 IF 0-2 9-11 OF 0-2 (9 minor cycles.) Main Memory Contra/Instructions Note that these Instructions apply only if the 6120 is executing instructions from main memory. Mne- Opcode Operation monic SKON SRO 6000 6003 GTF 6004 Skip if Interrupt on, and turn off interrupt system. (7 minor cycles.) Skip ilthe device Interrupt line Is low. Note thalthis skip does not de~end on the state of the memory extension control's interrupt inhibit flip flop. The SRO merely tests the state of the IN REO pin. (7 minor cycles.) Get flags. The follOWing bits are loaded into the AC: ACblt Function 0 1 2 GT~ LINK llf Is low o If INTREO is high PWRONflag 1 0 ISF 0-2 DSF 0-2 3 4 5 6-8 9-11 PRO PRI PR2 PR3 6206 6216 6226 6236 (9 minor cycles.) These four opcodes have the same effect. The PNLTRP is set, causing the 6120 to enter panel mode instead of executing the next instruction, provided the Interrupt Inhibit flip flop Is not set. If the interrupt inhibit flip flop Is set, the panel mode will be entered following the JMP, JMS, RTNI or RTN2 which clears the interrupt Inhibit flip flop. These instructions are a NOP in panel mode. (6 minor cycles.) Panel Memory Contra/Instructions The 6120's control panel is implemented in software. The software implementation of the control panel need not use any part of the main memory or change the processor state. This is an important feature, Since the final version of the system may not have a control panel and the system designer would like to use the entire capacity of the main memory for the specific system application. Panel mode is entered because of the occurrence of any of four events. Each of these events sets a status flag, as well as causing the entry into panel mode. It should be noted that more than one event might happen simultaneously. Flag Set by Cleared by PWRON RESET low and STRTUPlow PRO (main memory) HLT instruction (or any OPR2 Instruction with bit 10 a 1) High-to-Iow' transition of CPREO PRSand PE)< PNLTRP HLTFLG BTSTRP Panel mode entry is functionally similar to the granting of an interrupt with some important differences. Entry into panel mode for any reason Is inhibited by the interrupt inhibit flip flop. Note that this means that a PRO or HLT instruction executed when the interrupt inhibit flip flop is set will not be recognized until after the Interrupt Inhibit flip flop is cleared on the next JMP, JMS, RTN1 or RTN2. Entry into panel mode is also inhibited immediately following the ION instruction but will be recognized after the instruction following the ION is executed. When a panel request is granted, the PC is stored in location 0000 of the control panel memory and the 6120 resumes operation at location 7777 (octal) of the panel memory. During PC write, 0 appears on CO, Cl and EMA2. The states olthe IB, IF, DF, ISF and DSF registers are not disturbed by entry into the control panel mode but execution is forced to commence in field zero. The panel memory would be organized with RAM in the lower pages and ROM or PROM in the higher pages of field zero. The control panel service routine would be stored in the nonvolatile ROMs, starting at 7777 (octal). PRSand PE)< PGO PRSif BTSTRP was set when status read A ConTRoL panel Flip Flop, CTRLFF, which Is internal to the 6120, is set when the CPR EO is granted. The CTRLFF prevents further CPREOs from being granted, bypasses the interrupt enable system and redefines several of the internal control instructions. As long as the CTRLFF is set, LXPAR Is used for all instruction, direct data and indirect pointer references. Also, while CTRLFF is set, the INTGNT line is held high but the interrupt grant flip flop is not cleared. lOTs executed while CTRLFF is set do not clear the interrupt grant flip flop. Indirectly addressed data references by control panel AND, TAD, ISZ or DCA instructions reference panel memory or main memory as controlled by a Panel Data Flag (PDF) internal to the 6120. If set, this flag causes indirect references from control panel memory to address control panel memory using LXPAR. If cleared, this flag causes Indirect references from control panel memory to address main memory using LXMAR. Control panel instruction fetch is specified by IF. Control panel indirect address fetch is specified by IF. Control panel current page or page zero data operations are specified by IF. Control panel indirect data operations are specified by DF. Main or control panel memory access is specified by the panel data flag. The PDF is cleared unconditionally whenever the panel mode is entered for any reason. It is also cleared by an instruction called CPD (Clear Panel Data). The PDF is set by an instruction called SPD (Set Panel Data). The state of the Panel Data flag is ignored when not operating in panel mode. Extended memory operations are implemented for panel mode instructions by a 1-bit flag in the EMA logic (the Force Zero- FZ-flag). This flag is always set when panel mode is entered and before the first panel mode memory operation (the store of the PC at control panel memory location 0000). As long as the FZ flag is set, zero appears on CO, C1 and EMA2 in place of the IF except for special CO, C1, EMA2 contents defined during write intervals, which remain undisturbed by FZ being set. The IF remains unchanged, however, and may be read by the RIF instruction. The data field is unaffected by the FZ flag and functions as defined above, using the panel data flag to determine whether operands are in main or control panel memory. In particular if FZ=O: Control panel instruction fetch is to control panel field O. Control panel indirect address fetch is to control panel field O. Control panel current page or page zero direct data operations are to control panel field O. Control panel indirect data operations are specified by DF. Main or control panel memory access is specified by the panel data flag. The FZ flag is cleared in panel mode simultaneously with the (IF)_ (IB) transfer following the first panel mode instruction which may change the IF. These instructions are CIF (62X2), CDF CIF (62X3), RTF (6005), and RMF (6244). The (IF)_(lB) transfer (and hence the FZ clear) takes place during the first JMP, JMS, RTN1, or RTN2 following the instruction. Once the FZ flag is cleared, the EMA logic operates in control panel memory as it does in main memory with the exception that the panel data flag controls whether indirect data operations are to control panel or main memory. In particular: Once the FZ flag is cleared in panel mode, it is not set until panel mode is entered again. The state of the FZ flag when not in panel mode is a "don't care". Exiting from the control panel routine is normally achieved by executing the following sequence: PEX JMP I 0000 /Iocation 0000 in control panel memory The second instruction in this sequence may be any JMP, JMS, RTN1 or RTN2 instruction. The use of JMS is not recommended, since the programmer has no means of preserving the FZ and panel data flags. The PEX instruction will cause the next JMP, JMS, RTN1 or RTN2 instruction to reset the CTRLFF. Location 0000 in the control panel memory contains either the original return address deposited by the 6120 when the control panel routine was entered or it may be a new starting address defined by the control panel routine. The IF and DF registers may also contain their original field designations or may have been altered by the control panel routine. If an exit is made from the control panel routine with the HLTFLG set, one instruction is executed in main memory before control panel mode is reentered due to the HLTFLG being set. Note that this allows a software-controlled single step operation of programs in main memory. Caution: Single step operation will not occur for any uninterruptable instructions or any instructions which set the IIFF. Exiting from a control panel routine can also be achieved by activating the RESET line, since reset has a higher priority than control panel request. If the RUN/HLT line is pulsed while the 6120 is in the panel mode, the 6120 will halt at the completion of the current instruction. Panel Mode Control Instructions Note that these instructions apply only if the 6120 is executing instructions from Control Panel Memory Mnemonic Opcode PRS 6000 Description Read panel status bits into ACO-4, 0 into remainder of AC. The bits are read as follows: ACbit Function 0 1 2 BTSTRP PNLTRP 1 if INTREQ is low o if INTREQ is high PWRON HLTFLG 0 3 4 5-11 Following the reading of the flags into the AC, the flags are cleared, with the exception of HLTFLG. BTSTRP is cleared only if a 1 was read into ACO. (8 minor cycles). PGO 6003 Reset the HLTFLG flip flop. (6 minor cycles). PEX 6004 Exitfrom panel mode into main memory at the end olthe next JMP, JMS, RTNI or RTN2 instruction. Clear PWRON and PNLTRP. (6 minor cycles). CPO 6266 Clear Panel Data Flag (PDF). Clears the panel data flag so that indirect data operands of panel mode instructions are obtained from main memory. The panel data flag is also cleared upon entry into panel memory. (5 minor cycles). SPD 6276 Set panel data flag. Sets the panel data flag so that indirect data operands of panel mode instructions are obtained from panel memory. (5 minor cycles). Memory Extension Instructions Most memory extension instructions require 6 minor cycles, except for RIB which requires 9 minor cycles. that there is no carry from the most-significant PC bit into the IF. The IF is also used for directly-addressed operands, and for indirect address pointers. The internal memory extension control extends the basic 4K addressing structure of the 6120 to 32K. It does so by appending three high-order bits to the memory address. These bits, which appear on CO, C1 and EMA2lines, apply to addresses within main memory or control panel memory. The changing of memory fields is accomplished via internal control instructions. The Data Field (DF) serves to extend the address of indirectly addressed operands, external lOTs, OSR and WSR functions. The Instruction Save Field and Data Save Field are used to retain the contents of the IF and the DF which existed prior to an interrupt. The Instruction Field (IF) serves as an extension to the PC, providing three high-order bits during instruction fetches. Note Mnemonic Opcode Operation CDF CIF 62Xl 62X2 CDFCIF RDF 62X3 6214 RIF 6224 RIB 6234 RMF 6244 Change Data Field to X. X is loaded Into OF. Change Instruction Field to X. Xis loaded into IB, and the IIFF is set. (The set state IIFF causes the priority network to Ignore interrupt requests). The contents of IB are loaded into the IF at the end of the next JMP, JMS, RTNI or RTN2 Instruction. At the same time the interrupt inhibit flip flop is cleared. A microprogrammed combination of CDF and CIF. Both fields are set to X. Load the contents olthe Data Field register Into bits 6-8 of the AC. DFO-2 goes to AC6-8 respectively. ACO-5 and 9-11 are unchanged. Load the contents olthe Instruction Field register into bits 6-8 olthe AC. IFD-2 goes to AC6-8 respectively. ACO-5 and 9-11 are unchanged. Load the contents of the ISF and DSF into bits 6-11 of the AC. ISFO-2 goes to AC6-S and DSFD-2 goes to AC9-11 respectively. ACD-5 are unchanged. Load the contents of ISF into IB, DSF into OF, and set the interrupt inhibit flip flop. This Instruction is used to restore the contents of the memory field registers to their values before an interrupt occurred. Input/Output Instructions Input/output transfer instructions, which have an opcode of 6, are used to initiate the operation of peripheral devices and to transfer data between peripherals and the 6120. Three types of data transfer may be used to receive or transmit information between the 6120 and one or more peripheral I/O devices. Programmed data transfer provides a straight-forward means of communicating with relatively slow I/O devices, such as teletypes, cassettes, card readers and CRT displays. Interrupt transfers use the interrupt system to service several peripheral devices simultaneously, on an intermittent basis, permitting computational operations to be performed concurrently with I/O operations. Both programmed data transfers and program interrupt transfers use the accumulator as a buffer, or storage area, for all data transfers. lOT INSTRUCTION FORMAT o 2 3 4 Bits 0-2 are always set to 6 (110) to specify an lOT instruction. The next six bits, 3-8, contain the device selection code that determines the specific I/O device for which the lOT instruction is intended. Device selection codes 00 and 2X specify internal operations, and may not be used by external devices. Up to 551/0 devices can be specified. The last three bits, 9-11, contain the operation specification code that determines the specific operation to be performed. The nature of this operation for any given lOT instruction depends entirely upon the circuitry designed into the I/O device interface (see the 6121 specification) . Programmed data transfer begins when the 6120 fetches an instruction from the memory and recognizes that the current instruction is an external lOT. The 6120 sequences the lOT instruction through an execute phase. Bits 0-11 of the lOT 5 6 7 8 -I 9 10 11 OPE~ATION ¢ODE instruction are placed on DXO-11; the data field is placed on CO, C1 and EMA2; and DATAF is asserted. LXDAR then falls, signalling the beginning of the lOT execute phase. These bits must be latched in an external register, since they are then removed to free the DX bus for I/O data exchanges. Following the fall of LXDAR, the 6120 generates a write Signal. During the WRITE, the 6120 reads the SKIP, CO and C1 lines. SKIP, CO, and C1 define the type of I/O operation. If C1 is pulled low during the write signal, then the 6120 adds one minor cycle and performs a read operation after the write. The control line SKIP, when low during the write portion of an lOT, causes the 6120 to skip the next instruction. This feature is used to sense the status of various signals in the device interface. The CO and C1 lines are treated independently of the SKIP line. Programmed 110 Control Lines External programmed data transfers require 10 minor cycles if there is a read, 9 if not. Control Lines CO C1 Operation Description High Low High Low (Device)<--(AC) (Device)<-(AC), CLA (AC)<-(AC) V( Device) (AC)<-(Device) The contents of the AC is sent to the device. The contents of the AC is sent to the device; then the AC is cleared. Data is received from a device, "OR"ed with the data in the AC, and the result is stored in the AC. Data is received from a device and loaded into the AC. High High Low Low Interrupt Transfer The program interrupt system may be used to initiate programmed data transfers in such a way that the time spent waiting for device status is greatly reduced. It also provides a means of performing programmed data transfers between the 6120 and peripheral devices while executing another program. This is accomplished by isolating the I/O handling routines from the mainline program and using the interrupt system to ensure that these routines are entered only when an I/O device is set, indicating that the device is actually ready to perform the next data transfer. The interrupt system allows external conditions to interrupt the computer program (which must be in main memory) by driving INTREQ low. If no internal higher priority requests are outstanding and the interrupt system is enabled, the 6120 grants the device interrupt at the end of the current instruction. After an interrupt has been granted, the interrupt enable flip flop in the 6120 is reset so that no more interrupts are acknowledged until the interrupt system is re-enabled under program control. The interrupt inhibit flip flop prevents interrupts (both device and control panel) from occurring when there is a possibility that the IF is not equal to the lB. More specifically, the interrupt inhibit flip flop is set whenever the IB is loaded (I.e., by the instructions CIF, COF CIF, RMF or RTF), and cleared whenever the IF is loaded from the IB (I.e., at the proper phase of JMP, JMS, RTN1 or RTN2 instructions). Device interrupts are recognized only if the interrupt s stem is enabled, the interrupt inhibit flip flop is cleared and INT E is low. Upon recognition of an interrupt, the 6120 stores the PC in location 0000 of field 0 and clears the interrupt enable flip flop. Zero appears on CO, C1 and EMA2 when the PC is stored. At the same time, INTGNT goes low. During the interrupt grant sequence, IF is loaded into ISF and OF is loaded into OSF. IF, IB and OF are then cleared. The next instruction is fetched from location 0001 of main memory field O. INTGNT remains low until the trailing edge of the first LXOAR generated by a main memory lOT following the recognition of the interrupt. The granting of an interrupt requires 4 minor cycles. If a control panel interrupt is granted while INTGNT is low, INTGNTwili be forced high as long as CTRLFF is set but will return to the low state when CTRLFF is cleared. Direct Memory Access Direct memory access, sometimes called data break, is the preferred form of data transfer to use with high-speed storage devices such as magnetic disk or tape units. The OMA mechanism transfers data directly between memory and peripheral devices. The 6120 is involved only in setting up the transfer; the transfers take place with no 6120 intervention on a "cycle stealing" basis. The DMA transfer rate is limited only by the bandwidth of the memory and the data transfer characteristics of the device. The external device generates a DMA request when it is ready to transfer data. The 6120 grants the DMAREQ by pulling the DMAGNT signal high at any point in any of the instructions, or between instructions, when the 6120 is not using the DX bus in performing a bus read, write or read-modify-write operation. The 6120 suspends its internal timing until the OMAREQ line is high. The DX lines, EMA2, CO and C1 lines are tristated. LXPAR, LXMAR, MEMSEL, OUT, ~ and WRITE are all held high by a device on each of thesE! lines which only has a very small pull-up drive. These lines can then be pulled down by an external device. In this way, these control lines are stable until the external device can gain control of them. IFETCH and LXDAR are both held high. RUN is held low. The states of OATAF and INTGNT are undisturbed. The external DMA device must not drive the bus until DMAGNT is high. The DMA device must: a. Drive all signals with three-state devices. b. Provide all address, data, LXPAR, LXMAR, and other control signals with the proper timing. c. Return all control lines to the high state before relinquishing the bus. d. Three-state all drivers at or before OMAREQ is pulled high by the device. After the DMAREQ line is pulled high, the 6120 negates DMAGNT and re-establishes proper timing before proceeding. Internal Flags Set Clear Conditions Conditions Name Load Conditions Comments IEFF ION inst. 1. RESET=low 2. 10F inst. 3. During INTGNT sequence 4. SKON inst. RTF inst. INTERRUPT ENABLE FLIP FLOP: Tested by the SKON instruction. GCF inst. loads state of IEFF into AC4. INTREQ is honored only if IEFF is set (1). IIFF 1. CIF inst. 2. CIF CDF 3. RMF 4. RTF 1. RESET=low 2. JMP, JMS, RTN inst. none INTERRUPT INHIBIT FLIP FLOP: Suppresses any INTREQ or Control Panel mode request. CTRLFF Upon entry into panel mode 1. RESET=low 2. Next JMP, JMSor RTN after PEX inst. none CONTROL PANEL FLIP FLOP: Indicates control panel operation. Interrupts are not honored when set. FZ Upon entry into panel mode none FORCE ZERO FLAG: Forces control panel instruction field access to field zero. Indirect data accesses are not affected. PDF SPD inst. First JMP, JMS or RTN inst. executed with IIFFset. 1. Panel mode entry 2. CPD inst. none PANEL DATA FLAG: When set causes indirect data operations executed in control panel to access CP memory. Otherwise they are to main memory. PDF is ignored when executing in main memory. RUNHLT RESET=low none On the low to high transition of the RUN/HLTline RUN HALT FLIP FLOP: When cleared the 6120 will halt after the first instruction in which this state is detected. The 6120 will respond to DMAREQ in this state. HLTFLG HLT inst. 1. RESET=low 2. PGO inst. none HALT FLAG: When set, Ranel mode will be entered unless the IIFF is set or RESET is low. IIFF can be cleared on the next JMP, JMS or RTN instruction at which point panel mode will be entered. PNLTRP PRO, PR1, PR2, PR3 inst. (main only) 1. RESET=low 2. PRS inst. 3. PEX inst. none PANEL TRAP FLAG: Same result as defined for HLTFLG. BTSTRP High to low transition ofCPREQ 1. RESET=low 2. PRS inst. none BOOTSTRAP FLAG: Same result as defined for HLTFLG. PWRON RESET and STRTUP=low 1. RESET and STRTUP=high 2. PRS inst. 3. PEX inst. none POWER-ON FLAG~es entry into panel mode when RESET is released and this flag is set. GT none RESET=low RTF inst. GREATER THAN FLAG: General purpose flag which has no arithmetic significance.
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