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2000
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HD-6101
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XX-DFEA0-DA
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8
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http://bitsavers.org/pdf/dec/pdp8/cmos8/_dataSheets/HD-6101.pdf
OCR Text
mHARRIS HD-6101 CMOS PARALLEL INTERFACE ELEMENT (PIE) Pinout Features • HM-6100 COMPATIBLE • LOW POWER STANDBY -500/-lW MAX • SINGLE SUPPLY 4-11 VOLTS • FULL TEMPERATURE RANGE -55 0 C TO +125 0 C • STATIC OPERATION • 4 PROGRAMMABLE OUTPUTS (FLAGS) • 4 PROGRAMMABLE SENSE INPUTS CONTROL FOR TWO 12 BIT INPUT PORTS • CONTROL FOR TWO 12 BIT OUTPUT PORTS • PRIORITY VECTORED INTERRUPTS • UP TO 31 PIE'S PER SYSTEM • 16 INSTRUCTIONS FOR PIE CONTROL Description The HD-6101 Parallel Interface Elements (PIE) are high speed, low power, silicon gate CMOS general purpose devices which provide addressing interrupt and control for a variety of peripheral functions, such as UARTs, FIFOs, Keyboards, etc. Data transfers between the HM-6100 CMOS Microprocessor and the HD-6101 are via Input-Output Transfer (lOT) instructions, control lines and DX bus. Vee POUT SKP/INT WRITE 2 READ 2 WRITE 1 ~ C2 INTGNT PRIN SENSE 4 SENSE 3 SENSE 2 SENSE 1 SEL 3 SEL 4 LXMAR SEL 5 SEL 6 XTC SEL 7 DXO DXl DX2 DX3 DX4 OX5 Cl FLAG 1 FLAG 2 FLAG 3 FLAG 4 DEVSEL GND OX11 DX10 DX9 oxe DX7 DX6 Data transfers between peripheral devices and the DX bus are controlled by the PIE via 2 read, 2 write, 4 sense and 4 flag functions. Internal PiE registers are programmed under software control for write polarities, sense levels or edges, flag values and interrupt enables. Another software controlled register stores the address for vectored interrupt operation. Functional Diagram LXMAR CONTROL AEGISTER A = XTC I/O B CONTROL REGISTER B ~ ~ .----+f_- ::::: ~) 4 SENSE INPUTS .----+f_- SENSE 3 SENSE 4 DX4I• • F E R I FLAG 1 } FLAG 2 .4 PROGRAMMABLE FLAG 3 OUTPUTS FLAG 4 SEI. 3 UP TO 31 PIE ADDRESSES VECTOR REGISTER INSTRUCTION REGISTER ::~: --+1---1 ~ 1----------' SEL6 SEL 7 E C T PRIN POUT In R"2 W1 W2 INTGNT Tl'lT/SKP C1 C2 +--\----------------' I PRIORITY SELECTION TOANO FROM OTHER PIE'S CONTROL FOR TWO 12~BIT INPUT PORTS } CONTROL FOR TWO 12-81T OUTPUT PORTS Specifications NO-6tOt ABSOLUTE MAXIMUM RATINGS -O.3V to +8.0V Supply Voltage (vee - GND) (GND - O.3V) to (Vee + O.3V) -65 0e to +1500e Input or Output Voltage Applied Storage Temperature Range Operating Temperature Range Industrial HD-6101-9 -400e to +85 0 e Military HD-6101-2 -550C to +1250C ELECTRICAL CHARACTERISTICS D.C. Vee = 5.0V 110%; TA = Industrial or Military SYMBOL PARAMETER MINIMUM VIH Logical "1" Input Voltage 70% VCC VIL Logical "0" Input Voltage ilL Input Leakage -1.0 VOH Logical "1" Output Voltage(l) 2.4 VOL Logical "0" Output Voltage 10 Output Leakage ICC Supply Current (Static) CI Input Capacitance(2) Co Output Capacitance (2) CIO Input/Output Capacitance(2) A.C. MIN MAX tDR Delay: DEVSEL to READ tDW Delay: DEVSEL to WRITE tDF Delay: DEVSEL to FLAG 200 tDC Delay: i5EiiSIT to C1 , C2 Delay: i5EiiSIT to SKP /iiiii' Delay: i5EiiSIT to D X 160 tDI tDA UNITS TEST CONDITIONS 20% VCC V +1.0 pA OV V 10H =-O.2mA <: VIN <;; VCC 0.45 V 10L = 2.0mA +1.0 pA OV <;; Vo 1.0 100 pA VIN = VCC, Freq. = 5 7 pF 8 10 pF 8 10 pF <: VCC a (1) Except pins 33, 34, 39 (2) Guaranteed and sampled, but not 100% tested. TA = 25 0 C VCC = 5.0V(1) PARAMETER MAXIMUM V -1.0 NOTE: SYMBOL TYPICAL TA= TA= INDUSTRIAL MILITARY VCC=5V±10% VCC = 5V±10% MIN MIN MAX UNITS TEST CONDITIONS 330 ns CL = 50pF 330 ns See Timing 375 415 ns Diagram 460 510 ns 210 460 510 ns 350 460 510 ns 200 100 MAX 220 300 140 300 150 tLX LX MAR Pulse Width 200 240 265 ns tAS Address Set-Up Time 60 80 90 ns tAH Address Hold Time 100 125 140 ns tDS Data Set-Up Time 50 80 80 ns tDH Data Hold Time 100 100 110 ns NOTE (1): All devices guaranteed at worst case limits. Room temperature, 5V data provided for information - not guaranteed. Specifications HO-6101C-9 ABSOLUTE MAXIMUM RATINGS Supply Voltage (VCC - GND) -O.3V to +8.0V (GND - O.3V) to (VCC +O.3V) Input or Output Voltage Applied -65 0C to +1500C Storage Temperature Range Operating Temperature Range -400C to +850 C Industrial HD-6101C-9 ELECTRICAL CHARACTERISTICS D.C. VCC = 5.0V 15%; TA = Industrial SYMBOL PARAMETER MINIMUM VIH Logical "1" Input Voltage 70% VCC VIL Logical "0" Input Voltage ilL Input Leakage -10 VOH Logical "1" Output Voltagel1) 2.4 VOL Logical "0" Output Voltage 10 Output Leakage ICC Supply Current IStatic) CI I nput Capacitance (2) Co Cio MAXIMUM UNITS TEST CONDITIONS V .B V +10 IlA OV ~ VIN ~ VCC V 10H =-0.2mA 0.45 V IOL=1.6mA +10 Il A OV~ VO" VCC 1.0 BOO 7 Il A pF VIN = VCC. Freq. = 0 5 Output Capacitance (2) B 10 pF Input/Output Capacitance(2) B 10 pF -10 NOTES: A.C. TYPICAL SYMBOL PARAMETER tDR Delay: DEVSEL to READ tDW Delay: tDF 5E\iSEI. to WRITE Delay: 5E\iSEI. to FLAG tDC Delay: DEVSEL to Cl, C2 (1) Except pins 33, 34, 39 (2) Guaranteed and sampled, but not 100% tested. TA = 250 C VCC =5.0V(1l TA= INDUSTRIAL VCC = 5V'±5% MIN MIN MAX UNITS 375 ns CL = 50pF 125 375 ns See Timing 230 475 ns Diagram 190 560 ns 250 560 ns 400 560 ns MAX 230 100 5E\iSEI. to SKP/iNT 240 tDI Delay: tDA Delay: nEVSEL to DX tLX LXMAR Pulse Width 230 300 ns tAS Address Set-Up Time BO 100 ns tAH Address Hold Time 120 150 ns tDS Data Set-Up Time 60 90 ns tDH Data Hold Time 120 150 ns TEST CONDITIONS NOTE (1): All devices guaranteed at worst case limits. Room temperature, 5V data provided for information - not guaranteed. Timing Diagram on the DX lines, or control outputs READ1 and Rl:AD2 are generated to gate peripheral data to the DX lines. A low going pulse on DEVSEL while XTC is low is used to generate WR ITE 1 and WR ITE 2 controls. These signals are used to latch accumulator data into peripheral devices. Timing for a typical transfer is shown below. During an instruction fetch the processor places the contents of the PC on the bus and obtains from memory an lOT instruction of the form 6XXX @. During IOTA of the execute phase the processor places that instruction back on the DX lines @ and pulses LXMAR transferring address and control information for the lOT transfer to all peripheral devices. A low going pulse on DEVSEL while XTC is high @) is used by the addressed PI E along with the decoded control information to generate CPU control signals Cl, C2, and SKP. Also at this time either the Control Register A or the Interrupt Vector Register are outputed <D ® All PIE timing is generated from HM-6100 signals LXMAR, DEVSEL, and XTC. No additional timing signals, clocks, or one shots are required. Propagation delays, pulse width, data setup and hold times are specified for direct interfacing with the HM-6100. I - - - - - - - - - - I O T INSTRUCTION-------------<--I -I.. IOTA----_.+I.. ·---IOTB---_ ...~1 ! - F E T C H - -..... STATE TIMES \ XTC oJ LXMAR .n. - -H "\ \ TLX I CPU MEMSEL DX(O-11) ~ TAS -I tTAH :Th X (2) X/ / / / 'OOY - Y/ 7 //X V///777/,/7 TDSFI -TDH DEVSEL - ~- -@J. io- TWP I:::::TDA DX(O-11) //////// READ C1,C2 PIE SKP/INT INTERRUPT DATA / - - /X ////////// X/ / / I-TOR ~.!~I - TDI X SKIP X - X INTERRUPT DATA I-TDF FLAG (1 OR 3) VIA CFLAG OR SFLAG - YY I-TOW WRITE - X T-TDF FLAG (1-4) VIAWCRA Sense FF are sampled when LXMAR is high by the PIE. eo, OX data, C'i, 1:2, and SKP are read by the HM-6100 on the rising edge of T3. ~ Pie Address and Instructions The HM-6100 communicates with the PIE and with peripherals through the PIE via lOT commands. During the IOTA cycle an instruction of the form 6XXX is loaded into all PIE instruction registers. The bits are interpreted as shown below. The 5 address bits (3-7) are compared with the pin programmable select inputs SEL3, SEL4, SEL5, SEL6, SEL7 to address 1 of 31 possible PIEs. Address zero is reserved for lOT's internal to the HM-6100. The four control bits are decoded by the PIE to select one of 16 instructions which are described below. PIE INSTRUCTION FORMAT o 2 o CONTROL MNEMONICS 0000 1000 READl READ2 3 4 5 6 7 8 ADDRESS 9 10 11 CONTROL ACTION The READ instructions generate a pulse on the appropriate read outputs. This signal is used by the peripheral device to gate onto the DX bus to be "OR'ed" with the HM-6100 accumulator data. The HM-6100 accumulator is cleared prior to reading peripheral data when CO is asserted low. 0001 1001 WRITEl WRITE2 The WR ITE instructions generate a pulse on the appropriate write output. This signal is used by peripherals to load the HM-6100 accumulator data on the DX lines into peripheral data registers. The HM-6100 AC is cleared after the write operation when the CO input is asserted low. 0010 0011 1010 1011 SKIPl SKIP2 SKIP3 SKIP4 The SKIP instructions test the state of the sense flip flops. 0100 RCRA The Read Control Register A instruction gates the contents of CRA onto the OX lines during time 0101 1101 1100 WCRA WCRB WVR The Write Control Register A, Write Control Register B and Write Vector Register instructions 0110 1110 SFLAGl SFLAG3 The SET FLAG instructions set the bits F L 1 and FL3 in control register A to a high level. PI E outputs FLAGl and FLAG3 follow the data stored in bits FL 1 and FL3 of CRA. 0111 1111 CFLAGl CFLAG3 The CLEAR F LAG instructions clear the bits FL 1 and FL3 in control register A to a low level. (6007)8 CAF HM-6100 internal lOT instruction CLEAR ALL FLAGS clears the interrupt requests by clearing the sense flip flops. If the input conditions have set the sense flip flop, the PIE will assert the SKP/INT output causing the HM-6100 to skip the next program instruction. The sense flip flop is then cleared. If the sense flip flop is not set, the PIE not assert the SKP/m output and the HM-6100 will execute the next instruction. 4 to be "OR" transferred to the HM-6100 AC. transfer HM-6100 AC data on the DX lines during time 5 of IOTA into the appropriate register. Programmable Outputs FLAGs (1-4) - The FLAGs are general purpose outputs that can be set and cleared under program control. G LAG 1 follows bit F L1 in Control Register A and etc. FLAGs can be changed by loading new data into CRA via the WCRA commands. In addition, FLAG1 and FLAG3 can be set and cleared directly by the commands SFLAG1, CF LAG 1, SF LAG3 and CF LAG3. Programmable Sense Inputs The sense inputs are used to set sense flip flops (SENSE FF) inside the PIE. For each sense input there are two FF's, one for skip and one for interrupt. Conditions for setting each SENSE FF, levels or edges and positive or negative polarities, are set by control bits SL and SP in CRB. The SENSE FF's are sampled when LXMAR is high. Interrupt requests are generated only when the sense flip flops are set by an edge and interrupts are enabled by writing to control reg A. Sense flip flops are reset on the following conditions. SENSE FLIP FLOPS SKIP FF CONDITION INTERRUPT FF Clears All CAF Instruction (60078) Clears All SKIP Instruction Clears Corresponding FF Clears Corresponding FF Vectored Interrupt Not Cleared Clears Highest Priority FF on Selected PI E After Interrupt Disabled (I E = "0") Not Cleared Disables Interrupt by Holding Corresponding F F in Reset State Vectoring Controls for Input and Output Ports READ (1-2) - struction, is specified by the PI E's assertion of the Cl and C2 control lines as shown below. The READ outputs are activated by the read instructions and are used by peripheral devices to get data onto the DX lines for transfer to the HM-6100. Read lines are active low. Interrupt and skip information are time multiplexed on the same line (SKP/INT). Since the HM-6100 samples skip and interrupt data at separate times there is no degradation in system performance. The PI E samples the sense flip flops and generates an interrupt request for enabled bits (lEl-4) when LXMAR is high. Interrupt requests are asserted by the PIE driving the INT/SKP line low. During IOTA of SKIP instructions the INT/SKP reflects the SENSE FF data when DEVSEL is low and XTC is high. If the SENSE flip flop is set, the INT/SKP line is driven low to cause the HM-6100 to skip the next instruction. A!! these outputs ~ open drain. WRITE (1-2) - The WRITE outputs are activated by the write instructions and are used by peripheral devices to load HM-6100 AC data from the DX lines into peripheral data registers. Output polarity is controlled by the WR ITE POLARITY bits of CRA. A logic one causes pulses to be positive while a logic zero causes pulses to be negative. I/O CONTROL LINES' - There are three I/O control lines from the PI E to the microprocessor - Cl, C2, and INT/SKP. The type of data transfer, during an lOT in- CONTROL LINES SKP CO" Cf E2 H H H H PIE_ AC H H L H AC_ ACVPIE OPERATION DESCRIPTION The contents of the AC is sent to the PIE. Data is received from the PI E, OR'ed with the data in the AC and the result stored in the AC. H H L L PC - Vector Address Vector address received from PI E and loaded into PC. This is referred to as an absolute jump. L H H H PC -PC+l Forces Microprocessor to skip next sequential instruction. NOTE: "The CO line must be connected to VCC using a pull-up resistor. Programmable Registers CONTROL REGISTER A (CRA) The CRA can be read and written by the HM-6100 via the RCRA and WCRA commands. IE (1-4) - A high level on INTERRUPT ENABLE enables interrupts for the SENSE inputs. The format and meaning of control bits are shown below. Otherwise these inputs provide conditional skip testing as defined by the SKIPl-4 instructions. FL (1-4) - Data on FLAG outputs corresponds to data in FL (1-4). Changing the FL bits under software control changes the corresponding FLAG outputs. o FL4 FL3 5 2 3 4 FL2 FLI WP2 WP (1-2) - A high level on WRITE POLARITY bits causes positive pulses at the WR ITE outputs. 7 6 WPI 8 9 10 11 IE4 IE3 IE2 lEI * = Don't Care CONTROL REGISTER B (CRB) The CRB can be written by the HM-6100 via the WCRB instruction. It has no read back capability. The format and meaning of control bits are shown. SL (1-4) - A high level on the SENSE LEVEL bits causes the SENSE inputs to be level sensitive. A low level in the SL bits causes the SENSE inputs to be edge sensitive. An interrupt request is generated only if a sense Iine is set o SL4 SL3 up to be edge sensitive and interrupts are enabled via the IE bits of CRA. SP (1-4) - A high level on the SENSE POLARITY bits causes the flip flop to be set by high level or positive going edge. A low level causes the flip flop to be set by a low level or negative going edge. 2 3 4 5 6 7 SL2 SLI SP4 SP3 SP2 SPI 8 9 10 11 * = Don't Care VECTOR REGISTER A hardware priority network uniquely selects a PI E to provide a vectored address. The first lOT command of any type, after the HM-6100 signal INTERRUPT GRANT goes high, resets the INTGNT line to a low level. The INTGNT signal is used to freeze the priority network and enable vector generation. The highest priority PI E has PIN tied to VCC. The lowest priority PIE is the last one on o 2 3 5 4 VECTOR the chain. Within the PIE, SENSE1 has the highest priority and SENSE 4 has the lowest. The vector address generated by the PIE consists of 10 bits from the vector register and two bits that indicate the sense input within the highest priority PI E that generated the interrupt. If PIN is tied to GND, then the PIE will respond as a non-vectored interrupt device. 6 7 REGISTER VPRI CONDITIONS 00 01 10 11 SENSE 1 SENSE 2 SENSE 3 SENSE 4 8 9 10 11 VPRI Pin Definitions PIN SYMBOL 1 2 VCC INTGNT ACTIVE LEVEL H 3 PRIN H 4 SENSE 4 PROG 5 6 7 SENSE 3 SENSE 2 SENSE 1 PROG PROG PROG PIN SYMBOL ACTIVE LEVEL 21 22 23 24 25 26 27 28 OX 6 OX 7 OX 8 OX9 OX 10 OX 11 GNO OEVSEL TRUE TRUE TRUE TRUE TRUE TRUE 29 FLAG 4 PROG 30 31 32 33 FLAG 3 FLAG 2 FLAG 1 C1 PROG PROG PROG DESCRIPTION PIN SYMBOL Positive voltage A high level on INTERRUPT GRANT inhibits recognition of new interrupt requests and allows the priority chain time to uniquely specify a PIE. A high level ON PRIORITY IN and an interrupt request wilt select a PI E for vectored interrupt. The SENSE input is controlled by the SL (sense level) and SP (sense polarity) bits of control register 8. A high SL level will cause the sense flip flop to be set by a level while a low SL level causes then sense flip flop to be set by an edge. A high SP level will cause the sense flip ftop to be set by a positive going edge or high level. A high If: (interrupt enable) level generates an interrupt request whenever the sense flip flop is set by an edge. See pin 4 .~ SENSE 4 See pin 4 - SENSE 4 See pin 4 - SENSE 4 DESCRIPTION ACTIVE LEVEL DESCRIPTION 8 SEL3 TRUE 9 SEL4 LXMAR TRUE 10 11 12 13 SEL 5 SEL6 XTC TRUE TRUE 14 SEL 7 TRUE See Pin 8 - SEL 3 15 OX 0 TRUE 16 17 18 19 20 OX 1 OX 2 OX 3 OX4 OX 5 TRUE TRUE TRUE TRUE TRUE Data transfers between the microprocessor and PIE take place via these input/output pins. See Pin 15 - OX 0 See Pin 15 - OX 0 See Pin 15 - OX 0 See Pin 15 - OX 0 See Pin 15 - OX 0 PIN SYMBOL ACTIVE LEVEL , H H Matching SELECT(3-7) inputs with PIE addressing on DX(3-7) during IOTA selects a PI E for programmed input output transfers. See Pin 8 -- SEL 3 A positive pulse on LOAD EXTERNAL ADDRESS REGISTER loads address and control data from OX (3-11) into the address register. See Pin 8 - SE L 3 See Pin 8 - SEL 3 The XTC input is a timing signal produced by the microprocessor. When XTC is high a low going pulse on OEVSEL initiates a "read" operation. When XTC is low, a low going pulse on"5'87SEl initiates a write operation. DESCRIPTION See Pin 15 - OX 0 SeePin15-0XO See Pin 15 - OX 0 SeePin15-0XO See Pin 15 - OX 0 See Pin 15 - OX 0 34 C2 L See Pin 33 - C1 35 READi PROG Outputs READl andA"E'AD2 are used to gate data from peripheral devices onto the OX bus for input to the HM-6100 Note the data does not pass through the PI E. The l5E'Vffi input is a timing signal produced by the microprocessor during lOT instructions. It is used by the PI E to generate timing for controlling PIE registers and "read" and "write" operations. The" FLAG outputs reftect the data stored in control register A. Flags (14) can be set or reset by changing data in CRA via a WRA {write control register A) command. FLAG1 and FLAG3 can be controlled directly by PIE commands SFLAG1, CFLAG1. SFLAG3 and CFLAG3. See Pin 29 - FLAG 4 See Pin 29 - FLAG 4 See Pin 29 - FLAG 4 The PI E decodes address, control and priority information and asserts outputs CT and during the IOTA cycle to control the type of data transfer. These outputs are open drain for bussing and require a pullup register toVec· C1 (L), a(LI - vectored interrupt CiIL!. C2IH) - READi. REA02o' R RA commands Ci (HI. a(H) . all other instructions 36 WRITE1 PROG Outputs WRITE1 and WRITE2 are used to gate data from the HM-6100 OX bus into peripheral devices. Data does not pass through the PI E. a 37 REA02 PROG See Pin 35.- REAi51 38 WRITE2 PROG See Pin 36 -- WRITEl 39 SKP/iiii'f L The PIE asserts this line low to generate interrupt requests and to signal the HM-6100 when sense flip flops are set during SKIP instructions. This output is open drain. 40 POUT H A high level on priority out indicates no higher priority PIE interrupt requests are outstanding. This output is tied to the PIN input of the next lower priority PiE in the chain.
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