Digital PDFs

XX-31907-BE

1966

353 pages

Original

17MB

Document:	F-77A pdp7maint 19
Order Number:	XX-31907-BE
Revision:
Pages:	353
Original Filename:	http://bitsavers.org/pdf/dec/pdp7/F-77A_pdp7maint_1966.pdf

OCR Text

F-77A

PDP-7 MAINTENANCE MANUAL

DIGITAL EQUIPMENT CORPORATION

•

MAYNARD, MASSACHUSETTS

ICOpy NO.

Th is manual contains proprietary information. It is provided to the
customers of Digital Equipment Corporation to help them properly
use and maintain DEC equipment. Reveal ing the contents to any
person or organ ization for any other purpose is proh ibited.

PDP-7 MAINTE NANCE MANUAL

CONTENTS

INTRODUCTION AND DESCRIPTION •.••••••••••••••••.•••.•.••.•.•••.•••

1-1

1 •1

Introduction

•••••••••••••.•••••••.••.•.•••...••...•.......•.•..•..•

1-1

1 .2
1 .3

Purpose ••••••••.••••••••••••.••••.••••.••••••••.••••••.•..•••.•••.•

1-1

Scope . . .......................................................... .

1-1

1 .4

Physical Description ••.••••.•••..••.•.••••.••••.•..•.....••...•.••••.

1-2

1 .4.1

•••••••••••••••••••••••••••••••••••••••••••••

1-2

1 .5

Overa II System Configuration ••.•••••••••••••••••••••••••.••••••••••••

1-2

1 .6

Options

1-4

Equ ipment Suppl ied

...........•.......

•••••••••••••••••••••••••••••••••••••••

1 .601

Standard Opt ion s ...................•...........................

1-4

1 .6.2

Special Options

1-7

1 .7

Reference Documents

1-7

1 .8

System Specifications •••••••••.••••••••••••••••••••••.•.•••..••••••••

1-9

1 .9

Referenc ing Conventions

1-13

OPERATION ••••••••••••••••••••••••••••••••••••••••.••••..••••.•••••••

2.1

Introduction

2.2
2.2.1
2.2.2

System Controls and Indicators •.••••••••••••••••.••.•••.•.••.•..••••••

•••••••••••••••••••••••••••••••••••••••••••••••••••••••

Operator Console Controls and Indicators
Ind i cator Pane I

••••••••••••••••••••••••••

••..••............•.•.•.....•................••.•

2-1
2-1
2-1
2-1

2-6

2.2.3

Perforated Tape Reader Controls

••••••••••••••••••••••••••••••••••

2-8

2.2.4
2.3
2.3.1

Teletype Controls •.••.••••.•••••••••••..••...•••..••.•.•...•.•••

2-9

Operating Procedures •••••••••••••••••••••••••••••••••••••••.••••••••

2-10

Manual Data Storage and Modification •••••••••••••••.•••••••••.•••

2-1C'

2.3.2

Loading Binary Data Using READ-IN Key •••••••••••••••••••••••••••

2-IL

2.3.3

Loading Data Under Program Control •••••••••••••••••••••••••••••••

2-13

2.3.4

Assembl ing Programs ••••••••••••.••.••••.••...••......•....••.•.•

2--13

2.3.5

Te I etype Code •..••••••.•..••••.••••.••..•••..••.....•........••

2-14

2.3.6

Local Teletype Operation •.•••••••••••••••••••.•••••••••••••••.••

2-18

2.4

Prog ramm i ng

••.••••••••••••.••••••••••••.•••••••...••......•..•..••

2-18

2.4.1

The Programm ing System

•••••••••••••••••.•..•.•..•.••..•.•.•••.•

2-18

2.4.2

Maintenance Programs ••••••••.•••••••.•••.•••••••••••...•..•••••

2-18

iii

PDP-7 MAINTENANCE MANUAL

CON TEN T S (continued)
Page

SYSTEM DESCRIPTION •••••.••••.•••.•••.•••••••.•.••...••...••...•••••••

3-1

Functional Description •••••••••••••••••••••••••••••••••••••••••••••••

3-1

3. 1 • 1

Instructions •••••••••.•••••••••••••••••••••••••••••••.•••••••••••

3-1

3.1 .2

Ma ior Contro I States •.••••••••••••••••••••••••••••••••••••••••.••

3-2

3. 1 .3

Timing •••••••••••••••••••••••••••••••••••••••••••••••••••••••••

3-4

Log ic Functions •••••••••••••••••••••••••••••••••••••••••••••••••••••

3-4

3.2.1

Flow Diagram Interpretation •.....•.•.••.•••..•..••.•.••••.••.•..•

3-4

3.2.2

Pre lim inary Operations •••••....•.••..•••.•.•.............•...•.••

3-6

3.2.3

Manual Operations •..•.••.•...•.•••.•.•••••.....•....•...•••..••

3-7

3.2.4

Programmed Operations •.•..•...••••......••.......•......•...•••

3-12

3.3

Processor ••••••••••••••••••••••••••.•••••••••••••...••.•...••.••••.•

3-32

3.3.1

Reg i ste rs •••••••.••••••••••••••••••••••••••••••••••••••••••••

••

3-32

3.3.2

Tim ing •••••••••••••••••••••••••••••••••••••••••••••••••••••••••

3-40

3.3.3

3-46

Core Memory •.•.••..••..••••..••..•.•........•............ ~ , ..•..••

3-56

3.1

3.2

3.4

•••••••

3-56

•••••••••••••••••••••••••••••••

••••••

3-57

Interface and Input/Output ..••••••••••••••••••••••••.••.••••.••••••••

3-65

3.5.1

Device Selector (KA-71 A-5) ••.••.••••.••••••••.•.••••.•.•••••••••

3-66

3.5.2

Information Co Ilector (KA-71 A-4) ••••••.••••.••.••••..•••.••..••••

3-66

3.5.3

Information Distributor •.•••.••••••••••••••••..••••••••••••••••• ~ ••

3-67

3.5.4

MB Bus Drivers

3-67

3.5.5

Control Signals

3-67

3.6

Input/Output •.•••••••

3.4.1

Memory Organ ization ••••.••••••.•••.•.•••••••••••

3.4.2

C ircu it Operations

3.5

•.•...•

••••

••••••

3-70

3.6.1

Teletype Model 33 Automatic Send/Receive Set •.••.•.......•.•...••

3-72

3.6.2

Perforated Tape Reader and Control Type 444B ••.•....•....•.....•.••

3.6.3

Tape Punch and Punch Control Type 75D •.........•..........••.•..•

OPTIO NS

••

•••••••••••

•••••••••••••••••••••••

••••..•••..••.•.••.......•....•...•...

••••••••••••••••••••••

3-79

4-1

4.1

Introduction

••.•••••••••.•••••••.•••••••••••••.•••.••••••••••••••••

4-1

4.2

Input/Output Options •...•••••.....•••••••••••.....•.•..•••..••.....

4-1

4.3

Processor Options ••••••••..

•••••••

4-2

Automatic Priority Interrupt Type 172B ••••.••.•.••.•....•••••••.•••

4-2

4.3.1

1_' • • • • • •

••

•••••

I_I

••••••• - ••••••

PDP-7 MAINTENANCE MANUAL

CON TEN T S (continued)
Page
4.3.2

Data Interrupt Mu Itiplexer Type 173 ••••••••••••.••••.•••••••••••••

4-12

4.3.3

Extended Arithmetic Element (EAE) Type 177 •••••••••••••••••••.••••

4-16

........................ , .............................. .

5-1

5.1

Introduction •.••••••••••••...•..••...•••••... e , • • • • • • • • • • • • • • • • • • • • •

5-1

5.2

Ma intenance Equ ipment Requ ired , •.••••.••••.•••••••.•.••.••••.•••...•

5-1

5.3

Module Handl ing

................................... , .............. .

5-3

5.4

Maintenance Controls and Indicators •..••••••••.•••.••.•.••..•••..•••• ,

5-3

5.5

Preventive Maintenance

MAINTE NANCE

5.5.1

................................. ., ...... .
Mechanical Checks .............................................

5.5.2

Power Supply Checks ••....••.•••.••••.•..•...............••..••.

5-6

5.5.3

Marg i no I Check 5 ••••••••••••••••••••••••••••••••

5-7

5.5.4

Memory Current Check

5.5.5

Sense Ampl ifier Check

5.6

•••••••••••••••

................... ,...................... .

5-5

5-10
5-13

Corrective Maintenance •••••••••••.••••• f ' • • • • • • • • • • • • • • • • • • • • • • • • • •

5-13

5.6.1

Maindec Diagnostic Programs •••••••••••••••.••••••••••••••••••••

5-14

5.6.2

System Troubleshooting •.••••••••••••••••••••••..••..•••.••••.•••

5-15

5.6.3

Circu it Troubleshooting •.••••••••••••••••••••••••••.••••••••.••••

5-18

5.6.4

Module Repair

5-21

•....••..•••.••...•..••••.•.•.....•.............•

6-1

ENGINEERING DRAWINGS

6.1

Introduction

6-1

6.2

Draw ing Numbers .............. ~ ................................... .

6-1

6.3

Circuit Symbols •••••••••••••••••••••.••••••••••.•.•..•..•••....••••

6-1

6.4

Logic Signal Symbols ••••••••••••••••••.••••..•••••.•.•.••.•.•••••.••

6-1

6.4.1

Log i c Level s •••••••••••••••..•..•••••••••••.••.•..••••••.••.•••

6-3

6.4.2

Standard Pu Ises •.•.••••••••••.•.••.••.••..••.•••••.••.•••••.••• "

6-4

6.4.3

FLIP C HIP Standard Pu lses ••••••••••••••••••••.••••••••••.•.••••••

6-4

6.4.4

Level Transitions ••.••••.••••••••••••••••••••.••....••••.•.••••••

6-5

6.5

Coordinate System

•.••.••••.••••.••.••..•••••.•• _ ..•....••..•••.••••

6-5

6.6

Module Identification ••••.•••••••••••••••••.••••.••..•.••••••.••••••

6-5

6.7

Example •••••.•••••.•.•....•....•...•.••••.•.••..•..... " ..••.••...

6-6

PDP-7 MAINTENANCE MANUAL

ILLUSTRATIONS

1-1

Programmed Data Processor-7 ••.••.••••.••.••••••.•••••••.••••••••••••••••

xii

1-2

PDP-7 Component Locations •.•.•••••••••••••••••••••••.••••...•.•••••••••

1-3

PDP-7 System Diagram •.•...............................................

1-4

Typical PDP-7 Installation •••••.••••••••••••••••••••••••••••••.••••••••••

1-5

2-1

Operator Console •••••••.•••..•••••••.•••..•••••••.••••••.••.•••.••..•••

2-2

Indica~or Panel

••••••••••••••••••••••••••••••••••••••

2-6

2-3

Perforated Tape Reade r •.••••••••••.••.••••••••••••.•••••••••..••.••••.••

2-8

2-4

Teletype Console ••.••••••••••••••••..•••...••••••••••••.•.•••••• , ••••••

2-9

3-1

Instruction VVord Format •••••••••••••••••••••••••••••••••••••••••••••.•••

3-3

3-2

Processor Detailed Block Diagram ••••••••••••.•••••••••••••.•••••••••••.••

3-33

3-3

Core Memory System Block Diagram •.••.•••••••••••••••.••••••••••••••••.•

3-57

3-4

Simple Core Memory Plane Showing Read/Write, Sense, and Inhibit Windings •••

3-58

3-5

Typical Core Selection Circuit and Drive Current Path •••••.•••...•••••••••••

3-61

3-6

Memory Control Timing •.•.•••.•••••••.•••••••••.••••.•••.......••••.••.•

3-62

3-7

Inh ibit Log ic for One Memory Ce II ••••.•••••••••.•••.•••••••••••••••••••••

3-63

3-8

Input/Output Information Flow •••••.•••••••••••••••••.•••••••••••••••••••

3-71

3-9

Block Diagram of Keyboard/Printer Control Type 649

•••••••••.•••••••.••••••

3-71

3-10

Tape Format and Reader Buffer Reg ister Bit Assignments ••••.••••••••••••••••••

3-76

3-11

Reader Buffer in Binary Mode ••••••••••••••••••••••••••••••••••.••••.•••••

3-78

3-12

Effect of Delayed Sampl ing •••••••.••••••••••••••••••••••••••••••••••••••

3-79

4-1

Automatic Priority Interrupt Type 172 Block Diagram ••••••••••••••••••••••.••

4-3

4-2

Data Interrupt Mu Itiplexer Type 173 Block Diagram ••••••••••••••••••••••••••

4-13

4-3

EAE Block Diagram •..•••.•••.•••..•••.•••.•.••••••....••..•.•••••.••.••

4-24

4-4

EAE Divide Flow Diagram •.•••••.••..••.••.•••••••••...•..•..•..••.••...•

4-40

5-1

Marginal-Check Panel

6-1

DEC Symbols

•••••..•••••••...

I-I

•••••••••••••••.•.••••.•.••.•.•...••.•••.•••• ~

•••

5-4

••••••••••••••••••••.•.••.•••••••••.•..•..•.•....••••.•.•

6-2

Standard Negative Pulse •••••••••••••••.•••••••••.•..•.••••...•••.••••.••

6-4

6-3

FLIP CHIP R-Series Pulse

•••••••••••••••••••••••••.•••..•••..••••.•••• _.•

6-4

Typical DEC Logic Block Diagram •••••••••••••••.•••••••••••••••••••••••••

6-6

PDP-7 MAINTENANCE MANUAL

TABLES
Table

Page

1-1

Hardware and Software Documentation •••••••••••••••••••••••••.•.. , •••••••

1-7

1-2

Ma in tenanc e Prog ram Library •• • • •• • ••••••••••••••••••.••••••••.•••••••••••

1-8

1-3

Physical Dimensions ....••.......•..•...............................••.•.

1-9

1-4

Summary of System Performance Characteristics ••••••••••••••••.••••••••••••

1-9

1-5

Summary of Peripheral Equipment Characteristics ••••••••••••••••••••••••••••

1-11

2-1

Operator Console Controls and Indicators ••••••••••••••••••••••••••••••••••

2-2

Indicator Panel Functions ••••••••••••••••••.••••••••••••••••••••••••••••••

2-7

2-3

Tape Reader Controls ••••••••••••••.••••••••••••••••••••••.••.•.•••••••••

2-9

2-4

Teletype Console Controls •••••••••••••••••••••••••••••••••••••••••.••.••

2-10

2-5

Readin Mode (RIM) Loader Program •••.•••••••••••••••• ~ .••.•••••••••..•.••

2-11

2-6

Teletype Code ••••••••••••••••••••.•••••••••••••••••..•••....•.•••..••.•

2-15

3-1

Memory Reference Instructions ••.•••••.•••••••••.• , ••.•••••••..•.••••.••••

1-14

3-2

OPR Instructions •.....•..•••............•.... ".........•................

3-26

3-3

Perforated Tape Reader Instructions ••.•••••••••••••• ~ •••.••••••••••••••••••

3-75

3-4

Tape l--unch Instructions ••••••••••••••••••••••••••••••••••••••••.•••••••••

3-81

4-1

I/O Options and Appl icable Documents

... ............................... .

4-1

4-2

EAE Bit Assignments and Operations •••••••••••••••••.••••••••••••••••••••••

4-17

4-3

EAE Instructions •••••••••••••••••••••••••••••

4-19

5-1

Maintenance Equipment •••••••••••••••••••••••••••••••••••••••••••••••••

5-2

Maintenance Controls and Indicators ••••••••••••••••••••••••• , ••.•••••••••

5-3

Power Supply Output Checks •••••••••••••••••••••••••••••••••••••••••••••

5-6

l5-4

Marginal Test Programs ••••••••••••••••••••••••••••••.•••••••••.•••••••••

5-11

ENGINEERING DRAWINGS
Power Suppl ies and Control
RS-B-728

Power Supply (+10 and -15) ••••••••••••••••••••••••••••••••••••••

6-7

RS-B-738

Power Supply (0-20 marg inal check supply) •••••.•••••••••.•••••••••

6-7

RS-B-778

Dual 15-Volt Power Supply

......................................

6-8

RS-B-779

Power Supply (one lOv and three 15v floating suppl ies) •.•••••••••••••

6-8

RS-C-739

Power Su pp Iy (Memory) ••.••••.•••.•••••••••••.••••.•••.•••••.•••

6-9

RS-B-W505

Low-Voltage Detector (for 739) •••••••••••••••••••••••••••••••••••

6-10

RS-B-G800

Control for 739 Power Supply •••••••••••••••••••••••••••••••••••••

6-10

RS-B-832

Two-Step Power Control ••••••••••••••••••••..•••••••••••••••••••

6-11

vii

PDP-7 MAINTENANCE MANUAL
ENG I NEE R IN G DR A WIN G S (continued)
Drawing
System Modules
RS-C-4706

Eight-Bit Teletype Receiver ••..••••••••••••••••••••••••.••••.•••.•

6-12

RS-C-4707

Eight-Bit Teletype Transmitter •••.•••••••••.•••••...••••••••..••.••

6-13

FLIP CHIP Modules

..............................................

RS-C-B210

PDP-7 Accumulator

RS-C-G001

DC Sense Ampl ifier

RS-B-G002

Master SI ice Control •••••.••••••••••••••••••••••••••••••••••••••

6-16

RS-B-G201

Inh ibit Driver •••••••...••••.••.•••••••••.•.•.••••••••..•••.••.•

6-16

RS-B-G202

Memory Selector ••...............••......•...............•...•.•

6-17

RS-D-G601

Memory Selector Matrix

..........................................

6-19

RS-D-G602

Memory Se lector Matrix •••••••••••••••••••••••••.••••••••••••••••

6-21

••••••••••• e

•••••••••••••••••••••••••••••••••

6-14
6-15

Central Processor Type KA77 A
ML-D-KA77 A-O-2

CP Module Map .••.••................•...................•....•.

6-23

BS-D-KA77 A-O-3

Spec ial Cyc les and Key Functions .................................. .

6-25

FD-D-KA77 A-O-4

Flow D i09 ram •••••••••• ••••••••••••••• "" •••••.••••••••••••••••.••

6-27

BS-D-KA77 A-O-5

Tim ing .•••••.•••••.•............••••.•••................••.....

6-29

BS- D- KA77 A-O-6

Run and Spec iel Modes .......•....•.......••.....................

6-31

BS-D-KA77 A-O-7

Major and Minor States ......................................... .

6-33

BS-D-KA77 A-O-8

MA, MB, and PC Control ....................................... .

6-35

BS-D-KA77 A-O-9

AC Control and Link •.........•.•...........•....................

6-37

BS-D-KA77 A-O-1 0

Memory Contro I .......•...............•.........................

6-39

BS- D- KA77 A-O-11

Extend Mode Control

6-41

BS-D-KA77 A-O-12

16K Memory Control

6-43

BS-D-KA77 A-O-13

32K Memory Control

6-45

BS-D-KA77 A-O-14

Interr~pt Control •............•.•.•.•...•......•.................

6-47

BS-D-KA77 A-O-15

MA and PC Reg i sters •.........•...•...•.............•.....•.....•

6-49

BS- D- KA77 A-O-1 6

MB Reg i sters ....•................•.........•.................•..

6-51

BS-D-KA77 A-O-17

AC-Register (Sheet 1)

6-53

BS-D-KA77 A-O-17

AC-Register (Sheet 2)

6-55

BS-D- KA77 A-O-1 8

MB and AC Bus Drivers •.............••...........................

6-57

BS-D-KA77 A-O-19

Central Processor Modifications for EAE

•••••••••••••••.•••..••••.••

6-59

CL-D-KA77 A-O-20

Centra I Processor Cab Ies au t/In (Sheet 1) ••••••••••••••••••••••••••

6-61

CL-D-KA77 A-O-20

Central Processor Cables Out/In (Sheet 2) ••••••.•••••••...•••••••.•

6-63

viii

PDP-7 MAINTENANCE MANUAL

ENG IN E E R IN G DR A vv IN G S (continued)
Page

Drawing
FLIP CHIP Modu les (continued)
WD-D-KA77 A-0-21

Bus Bar for Central Processor......................................

6-65

WL- B-KA77 A-O-22

Wiring List • ~ • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •

6-67

Basic PDP-7 Core Memory Log ic (Type 149)
BS-E-149-0-45

Inh ibit Drivers and Sense Ampl ifiers Core Memory 0 and 1

6-69

BS-E-149-0-46

"X" Axis Selection 4K Core Memory •••••••••••••••.•..••••••..••••

6-71

BS-E-149-0-47

"V" Axis Selection 4K Core Memory •.••••.•••••••....•.•.....•.•••

6-73

BS-E-149-0-48

"X" Axis Selection of Core Memory

6-75

BS-E-149-0-49

"V" Axis Selection of Core Memory •.••••••••.. _..••••••••.•••..••

6-77

ML-D-149-0-50

Standard Memory Modu Ie Map ••..••••••••.•.•..•••..•••••••.•••.•

6-79

WD- 0- 149-0-51

Resistor Panels

•••••••••••••••••••••••••••••••••••••••••••••••••

6-81

CL-D-149-0-52

Memory Stack Connector Configuration ••••••••••••••••••••••••.•••

6-83

Basic PDP-7 Input/Output Equ ipment
Perforated Tape Punch and Control Type 75D
BS-D-75D-0-2

6-85

Punch Control

Perforated Tape Reader and Control Type 444B
6-87

BS- D-444B-O-2

Reader Control

ML - D-444B-0-3

Reader 444B and Punch 75D Modu Ie Map

6-89

WD- D-444B-0-5

Reader 444B and Punch 75D Bus Schedule

6-91

•••••••••••••••••••••••••••••••••••.•••••••.•••••

Teletype Control Type 649
BS-D-649-0-2

6-93

Keyboard/Printer Control
PDP-7 Options

Extended Arithmetic Element Type 177
FD-D-177-0-2

EAE Flow Diagram (Sheet 1)

6-95

FD-D-177-0-2

EAE Flow Diagram (Sheet 2)

6-97

FO-O-177-0-3

EAE Modu I e Map •••••••••••••••••••••••••••••••••••••••••••••••

6-99

BS- D- 177 -0-4

EAE States •••••••••••••••••••••••••••••••••••••••.•••••••••••••

6-101

BS-D-177 -0-5

EAE Step Counter and Control

6-103

••••••••••••••••••••••••••.•••••••••
ix

PDP-7 MAINTENANCE MANUAL

ENG IN E E R IN G DR A WIN G S (continued)
Drawing
PDP-7 Options (continued)
BS- D- 177-0-6

EAE Reg i ster Contro I •••.••••.•••..••••••••••••.•••••••••••••••••

6-105

BS-D-177-0-7

Main Time Chain ••••.•..•••.••••••••.•••••••.••.•••••.•••••••.•

6-107

BS- D- 177-0-8

MQ Register •••••••••••••••••••••••••••••••••••••••••••••••••••

6-109

BS- D- 177 -0-9

AC Inverters •••••••••••••••••••••••••••••••••••••••••••••••••••

6-111

CL-D-177-0-10

EAE Cable Sche_du les ••••••••••••••••••••••••••••••••••••••••••••

6-113

WD-D-177-0-12

Pin and Block Layout EAE

6-115

Data Interrupt Mu Itiplexer Type 173
BS-D-173-0-2

Data Interrupt Mu Itiplexer Control

6-117

BS- D-173-0-3

Data Interrupt Multiplexer Data Input/Data Addresses

ML-D-173-0-5

Data Interrupt Mu Itiplexer Modu Ie Map o .

•• 0

•

•• 0

WD-D-173-0-8

6-119

••••••••

6-121

Bus Schedu Ie ••••••••••••••••••••••••••••••••••••••••••••••••• "

6-123

•

000

Automatic Priority Interrupt Type 172B
BS-D-172-0-2

Automatic Priority Interrupt Control

•••••••••••

6-125

BS-D-172-0-3

Automatic Priority Interrupt System (Sheet 1) •••••..•••...••.•••••••

6-127

BS- D- 172-0-3

Automatic Priority Interrupt System (Sheet 2) ••••

•••••••

6-129

ML-D-172-0-5

Module Map

••••••••••••••••••• "'., .••••••••••••••••••.•••••••.•

6-131

WD- D-1 72-0-6

Pin and Block Layout

00 • • 0

••

•

•••••••

•

000

o ••••

6-133

VO Dev ice Type KA71 A
BS-D-KA71 A-0-4

Information Collector ••

•

6-135

BS-D-KA71 A-0-7

Reader Contro I •••••••••••••••••••••••••••••••••••••••••••••••••

6-137

BS-D-KA71 A-0-1 0

Display Control ••••••••••••••••••••••••••••••••••••••••••••••••

6-139

BS-D-KA71 A-0-9

Teleprinter Control •••••••••••••••••••••••••••••••••••••••••••••

6-141

BS-D-KA71 A-0-3

CLK, FLG, SKP, and PWR CLR •••••••••••••••••••.•••••••.••••••

6-143

BS-D-KA71 A-0-8

Punch Control •••••••••••••••••••••••••••••••••••••••••••••••••

6-145

BS-D-KA71 A-0-6

Optional Device Selection

6-147

BS-D-KA71 A-0-5

Standard Device Selection

6-149

WL-B-KA71 A-0-13

Wiring List Type KA71 A •..••••••••••

•••••••••••••••••••••

6-151

ML-D-KA71 A-0-2

Modu Ie Location for I/O •....•.•.•.••••••••..•.•.•.•••....•.•.••

6-153

•••••• 0'

••

••••• 0

••

•••• 0

••••••••

0.'

••••••

PDP-7 MAINTENANCE MANUAL

ENG I NEE R I N G DR A WIN G S (continued)
Drawing
I/O Device Type KA71A (continued)
CD-D-KA71A-O-ll

I/O Package Cables (Sheet 1)

6-155

CD-D-KA71A-O-11

I/O Package Cables (Sheet 2)

6-157

CD-D-KA71A-O-ll

I/O Package Cables (Sheet 3)

6-159

WD-D-KA71A-O-12 I/O Package Bus Schedule ...................................

6-161

TL-A-KA71A-O-14

Terminator List (Sheet 1) .....................................

6-163

TL-A-KA71A-O-14

Terminator List (Sheet 2) .............•.......................

6-165

Wiring Diagrams
WD-D-7A-O-2

Console Panel-Wiring Diagram ............................... .

6-167

PW- D-7A-O-3

AC Power Wiring .......................................... .

6-169

PW-D-7A-O-4

DC Power Wiring

6-171

Figure 1-1

Programmed Data Processor-7

PDP-7 MAINTENANCE MANUAL

CHAPTER 1
INTRODUCTION AND DESCRIPTION

1.1

INTRODUCTION
The Programmed Data Processor (PDP-7), manufactured by Digital Equipment Corporation, is a

genera I purpose stored program computer using sol id state FLIP CHIP ™ logic modu les. The mach ine is a
single address type, with fixed la-bit word length, and uses 1s complement and 2s complement notation
to facilitate multiprecision arithmetic.
The manua I describes the basic computer organization and its optiona I equipment, and inc ludes
logic discussions in terms of the machine instruction repertoire. Manual operations and sample diagnostic
programming routines also are included for maintenance purposes. This manual is applicable to PDP-7
machines having serial numbers 100 and above.

1 .2

PURPOSE
This manual is compiled with a dual purpose--to provide initial instruction in the PDP-7 system,

and to provide maintenance information in a form for easy use and quick reference.
Information in this manual is graded for use by eng"ineers and technicians familiar with digital
logic techniques, digita I computer principles, and the concepts of computer programming. Programmed
maintenance routines greatly facilitates maintenance of this equipment.
One of several documuments related to the PDP-7 computer, this manut'll provides an understanding of system organization and capabHities. Each chapter is oriented to contain sufficient information for maintaining the equipment. The levels of discussion in any case assume the user to be familiar
with the technology of similar computers. For complete and comprehensive coverage of areas not found in
this manual, the operator should refer to the list of documents in paragrQph 1.7.

1 .3

SCOPE
In addition to information necessary for proper operation and maintenance, this manua I describes

in detail input/output and standard optional equipment used with the PDP-7 and core memory.
The presentation is both hardware and program oriented, and contains sufficient descriptions and
detailed logic drawings for understanding the logical operations of the system. At the same time, descriptions and treatment are program QJriented so that the software operations and impl ications, particu larly for

™FLIP CHIP is a trademark of Digital Equipment Corporation.

1-1

PDP-7 MAINTENANCE MANUAL

maintenance, are thoroughly understandable. Most important, the book is formatted and organized in such
a manner tha t any reference can be easi Iy located.

1 .4

PHYSICAL DESCRIPTION
The basic PDP-7 is completely se If-contained in a 3-bay DEC meta I cabinet, and requires no

special power sources, air conditioning, or floor bracing. A door (held closed by a magnetic latch) at
the front prov ides access to the wiring side of a II modu Ie mounting pane Is. A fan at the cabinet bottom
draws air through a dust filter to cool the modules. Air passes over the modules and exits through louvers
at the top.

1 .4.1

Equipment Supplied
Figure 1-2 shows the component locations of the basic PDP-7. The paper tape punch and

reader are mounted on the front panel. The Teletype unit may be mounted on a separate stand or may be
placed on the console table. For additiona I physica I data, see paragraph 1 .8, System Specifications.

1.5

OVERALL SYSTEM CONFIGURATION
The standard PDP-7 system includes the processor, memory, and the standard input/output equip-

ment shown in the processor block of figure 1-3. All other elements shown are optional equipment.
The processor performs the logical and arithmetic functions, controls the storage and retrieval
of information in core memory and controls flow of information to and from periphera I equipment. The
processor consists of control logic and the major registers of the system. The operawr console associated
with the processor permits manual manipulation of the contents of memory.
The core memory is a 4096-word or 8192-word random access ferrite core memory. The basic
memory is expandable to a maximum capacity of 32,768 words by using added memory modules cmd a Memory Extension Control Type 148. The memory has a cyc Ie time of 1 .75 j-lsec and provides a computation
rate of 285, 000 additions per sec. Indirect addressing and autoindexing features provid~ programming
flexibi lity.
The standard input/output (I/O) configuration contains the following peripheral equipment:
Teletype KSR Unit
Paper Tape Reader and Control
The Te letype keyboard inserts data into the computer, and the Te letype unit types out data on
page size roll paper, under either manual or program control.
The paper tape reader reads data from punched paper tape photoelectrically, controlled by the
computer stored program. The paper tape punch provides output on punched paper tape, controlled by the
stored program.
1-2

PDP-7 MAINTENANCE MANUAL

BAY I
5-1/4 INCH
MOUNTING PANEL

BAY 2

BAY 3

INDICATOR
PANEL

C
D
E

149
MEMORY

TAPE
PUNCH

MARGINAL CHECK
PANEL

F
H

BLANK

t---------

FANS

Ir-\.jl

CON OL

wi
I~
::::: ~~~f~ :::::
-- .. . ....
TAPE
READER

BLANK

I ~ ,h

KA77A
PROCESSOR

OOQ)

TABLE

J
K

A
B
C

KA71A

I/O PACKAGE

BLiNK
F

L
M

B28
POWER RECEPTACLE

FANS

J
FANS

i
FRONT

BAY :3

BAY 2

BAY I
-<-_u---c .. _ - -

TYPICAL
4 INCHES

738
POWER SUPPLY

-r
BLANK

BLANK
BLANK
728
POWER SUPPLY

SPACE
AVAILABLE
ON
REAR DOORS

REAR SPACE REQUIREMENTS
EQUIPMENT
TYPE

VERTICLE
SPACE REQ'D

728A POWER SUPPLY
734A,B,C POWER SUPPLY
743A POWER SUPPLY
772A POWER SUPPLY
778 A POWER SUPPLY
179A POWER SUPPLY
832 POWER CONTROL

8 INCHES
8 INCHES
12 INCHES
8 INCHES
12 INCHES
12 INCHES
8 INCHES

728
POWER SUPPLY

779
POWER SUPPLY

72B
POWER SUPPLY

UNAVAILABLE
(TABLE)
832C
POWER CONTROL
-15 DELAYED,
REAL TIME
TRANSFORMER

739
POWER SUPPLY
728
POWER SUPPLY

BLANK

REAR

Figure 1-2

PDP-7 Component Locations

1-3

739
RELAY PANEL

PDP-7 MAINTENANCE MANUAL

555

':570'

f:::::;RT

ir=
I
I

11:~~i

OECtope'
TRANSPORT

550
OECtape

•
•

CONTROL

•

'57A

•

MAG TAPE
CoN'rROi...

•

r------ -------I
I
I

CONSOLE

.TELE-'PRINTER

I
I

POP';"?

I
I

DATA INTERRUPT----.

.PRQ~e$S()a

COREMEM.
.~;1:75 pSEC

14K

REAL
TIME

CLOCK

L '
BASIC POP-7 J
----- -------- ------------··.·MEMORY'

EXTENSION
CONTROL

I
.·4K

Figure 1-3

PDP-7 System Diagram

The interface basically provides control links between the processor and input/output peripheral
equipment. In this instance, input and output data passes through the interface unit, which interleaves
high-speed data transfers and priority selection of input and output devices seeking communication with the
computer.

1.6

OPTIONS
The design of the PDP-7 offers flexibility for increasing the capacity and precision of the system

by selection of a wide variety of optional peripheral equipment. Location requirements depend on the
nature of the option and on availability of space (see User Handbook, F-75A, for typical installation and
layout configurations).

1.6.1

Standard Options
For practical purposes, options are classified as either standard or special in accordance with

projected requirements of the customer. A typical PDP-7 installation using many of the standard options

1-4

PDP-7 MAINTENANCE MANUAL

available is shown on figure 1-4. These options, described fully in chapter 4, are of three types: input
and output options, processor options (not shown), and memory expansion options. A wide variety of
input/output options are offered for use with the PDP-7, and these units are listed and device characteristics
described in table 1-5. The standard processor options are Extended Arithmetic Element Type 177 (EAE) ,
Automatic Priority Interrupt Type 172 (API), Data Interrupt Mu Itiplexer Type 173, Memory Increment
Type 197, and Boundary Register and Control Type KA70A.

CABLE ACCESS
(TYPICAL FOR 3 CABINETS)
SWINGING PLENUM
DOORS (3)

CASTER" SWIVAL RADIUS

3" - - - - - - - - - ' I : - - - - - - - . . a j
---61'4

SWINGING DOORS (10)

LOAD POINT

--.--++--+

+
11~

1"
17"4
I

:+~

50!!"
16

r-"....----_- ..,
+11
~

"I
+ ~+1

REMOVEABLE
END PANEL
FAN (TYPICAL FOR

/'loI11----++-- 3 CABINETS)

L~~ __.:::"'_...I

---,

L ____ ...I

27~"

SCREEN (TYPICAL
FOR 3 CABINETS)
-I---+-lf----

29"
4 32

~,~,

8 3"
4

TABLE

7 11

t - - - - - - -

68~"_-----.jjl
16

FLOOR PLAN

Figure 1-4

Typical PDP-7 Installation

The EAE option facilitates high-speed multiplication, division, shifting, normalizing, and
register monipulation. Installation of the EAE adds an la-bit multipl ier quotient register (MQ) to the

1-5

PDP-7 MAINTENANCE MANUAL

computer as well as a 6-bit step counter register (SC) , and the content of the MQ is continuously displayed
on the operator console. The Type 177 option and the basic computer cycle operate asynchronously, permitting performance of computations in the minimum possible time. Further, the EAE instructions are microcoded so that several operations can be performed by one instruction to simplify arithmetic programming.
Average multiplication time is 6.1 IJsec; average division time is 9 Ilsec.
The Automatic Priority Interrupt Type 172 increases the capacity of the PDP-7 to handle transfers of information to and from input/output devices by direc~ly identifying an interrupting device, without
flag search ing. Mu Iti leve I program interrupts are permissible where a device of higher priority supersedes
an interrupt a Iready in process. These functions increase the speed of the input/output system and simpl ify
the programming, thereby servicing efficiently more and faster devices. The Type 172 contains 16 automatic interrupt channels arranged in a priority sequence so that channel 0 has the highest priority and
channel 178 has the lowest priority. The priority chain guarantees that if two or more I/O devices request
an interrupt concurrently, the system grants the interrupt to the device with the highest priority. The other
interrupts wi II be serviced afterwards in priority order.
Using the Data Interrupt Multiplexer Type 173, the single PDP-7 data break interrupt channel
is expanded to handle information transfers with three high-speed I/O devices. This option provides multiplex control for simultaneous operation of three high-speed devices such as magnetic tapes or drums.
Maximum combined transfer rate is 570,000 18-bit w~rds/sec.
The Memory Increment Type 197 option allows an external condition or signal from an I/O device to increment the contents of any core memory location. The peripheral device initiates a break cycle
so that the contents of a core memory address specified by the device are read into the memory buffer
register, incremented by one, and written back into the same address in one computer cyc Ie.
The Boundary Register and Control Type KA70A option establishes core memory address boundar;es
that can be assigned to ::»pecific users when the system is used for real-time computing with simultaneous
multiuser program execution.
The standard core memory options are Memory Extension Control Type 148, Expansion Modules
Type 147 and 149B, and Memory Parity Type 176.
Memory Extension Control Type 148 is used when expanding memory capacity beyond 8K words.
This option provides the necessary extension of the program counter, memory address register, and mode
control.
Any memory size from 4096 to 32,768 words can be obtained by addition of Core Memory Modules Type 147 or 149B. Type 147 extends the capacity of the standard 4096 word memory to 8192 words.
Type 149B extends memory capacity by one field of 8192 words. Type 149B can be added only to memories
of 8K, 16K, or 24K capacity (not to 4K, 12K, etc., without also adding a Type 147 module).

1-6

PDP-7 MAINTENANCE MANUAL

Memory Parity Type 176 option assures reliability of all core memory data storage and retrieval
operations by generating, storing, and checking parity on every transfer. An odd parity bit is generated
and written in the same core location as the word being written. Upon reading, a word drawn from core
memory is checked for parity, and, if odd parity is detected, a program interrupt is initiated or the program is ha Ited.

1 .6.2

Special Options
Special options available with the PDP-7 system are not discussed in detail in this manual. In-

formation is provided on a customer-need basis and reference is suppl ied to the proper avai lable vendor
documents covering peripheral equipment supplied but not manufactured by Digital Equipment Corporation.
Most specia I options are input/output devices. Often the interface logic for each device varies
in accordance with the data transfer speed of the device and to its relative importance to the program.
S low-, medium-, and high-speed devices are connected as program controlled transfer channels, data
channels, and direct memory access channels. Medium- and high-speed devices are often connected as
automatic priority interrupt channels. Chapter 3 contains discussions of these interface control channels,
and chapter 4 contains a list of available special options they control.

1 .7

REFERENCE DOCUMENTS
Tables 1-1 and 1-2 list the standard documentation provided for the PDP-7system. Other

documents may be furnished as applicable to customer requirements.

TABLE 1-1

HARDWARE AND SOFTWARE DOCUMENTATION

Document
FLIP CHIP Module Catalog, C-105

Description
Function and specifications of FLIP CHIP modu les
and accessories

System Module Catalog, C-100

Function and specifications of system modules
and accessories

PDP-7 User Handbook, F-75A

Programming, instruction format, and computer
functions

PDP-7 Software Package

Perforated program tapes and descriptions for symbol ic assembly language, uti lity subroutines and
Maindec (maintenance) programs (see table 1-2)
1-7

PDP-7 MAINTENANCE MANUAL

TABLE 1-1

HARDWARE AND SOFTWARE DOCUMENTATION (continued)

Document

Description

Instruction manua Is and maindec programs

Individua I manua Is and programming materia I

for 110 dey ices

avai lable on a customer-need basis

Tech. Manual, KSR-33, vols 1 and 2

Operation and maintenance instructions

Bulletin 273B
IPB for Teletype unit

Parts, Model 33 Page Printer Set,
Bulletin 1184B
Tech. Manual, Hi-Speed Tape

Operation and maintenance instructions

Punch Set
Bu Iletin 215 B (BRPE)
Manua I Mode I 2500 Perforated

Operation and maintenance instructions

Tape Reader

TABLE 1-2

MAINTENANCE PROGRAM LIBRARY
Number

Name
Maindec 702 (Address Test)

Digita 1-7-55-M

Maindec 703 (Checkerboard)

Digital-7-56-M

Maindec 701 (Instruction)

Digital-7-54-M

Contest II (Instruction)

Digital-7-52-M

Teleprinter Test

Dig i ta 1-7-50-M

Maindec 710 (Reader)

Digital-7-57-M

Reader Punch Test

Dig i ta 1-7-53-M

C lock Interrupt

Digita 1-7-51-M
Options

Automatic Priority Interrupt Test

Digital-7-59-M

Extended Arithmetic Element Test

Digital-7-58-M

DECTOG

Digita 1-7-20-10

57A Error Specification

Digita 1-4-57-M

1-8

PDP-7 MAINTENANCE MANUAL

TABLE 1-2

MAINTENANCE PROGRAM LIBRARY (continued)

Name

Number
Options (continued)

340 Display Diagnostic

Digital-7-63-M

34 Display Test

Digita 1-7-60- N

370 Light Pen Test

Digital-4-3-I

Drum Diagnostic

Digital-7-62-M

630 Diagnostic

Dig i ta 1-7-64-M

1 .8

SYSTEM SPECIFICATIONS
The following tables, 1-3, 1-4, and 1-5, summarize the properties of the PDP-7 system and

some of the avai lable standard options.

TABLE 1-3

PHYSICAL DIMENSIONS

Unit

Ht. (in.)

Width (in.)

Depth (in.)

Wgt. (lbs)

Cabinet

69-1/8

61-3/4

33-9/32

1130

68-15/16

19-7/8

18-5/8

18-1/2

Table
Teletype

8-3/8

TABLE 1-4 SUMMARY OF SYSTEM PERFORMANCE CHARACTERISTICS
Capability

Function
Computer type

Parallel binary, single address, fixed l8-bit
word length

Machine code

1sand 2s complement notation

Memory

Coincident current ferrite core

Standard capacity

4096 or 81 92 words

Optiona I capacity

Expandable to 32,768 words

Cycle time

1 .75 jJsec

1-9

PDP-7 MAINTENANCE MANUAL

TABLE 1-4 SUMMARY OF SYSTEM PERFORMANCE CHARACTERISTICS {continued}
Capability

Function
Computation rate

285,000 additions/sec

Transfer rate
Data interrupt

570, 000 words/sec

Addressing

Sing Ie address with indirect addressing

Instructions

16 basic {13 memory reference, 3 augmented}.
Augmented instructions are microprogrammed to
provide more than 175 commands.

I/O capabi lity

Standard, 64 different devices individually
selected and addressed

Standard I/O lines
Device selector

expandable to any number

Information collector

seven 18-bit channels

Information distributor

six 18-bit channe Is

Signa Is
Levels
Pulses
Power requirement

Ov and -3v
Standard, single source, 115v, 60 cps, single
phase
Optiona I, 22Ov, 50 or 60 cps

Power dissipation

2200 watts

Heat dissipation

7150 Btu per hour

Ambient conditions
Operating temperature

50 to 122°F

Operating humidity

o to 90% relative humidity

Storage temperature

32 to 122°F

Storage humidity

less than 90%

1-10

PDP-7 MAINTENANCE MANUAL

TABLE 1-5

SUMMARY OF PERIPHERAL EQUIPMENT CHARACTERISTICS

Unit

Capability
Basic PDP-7 I/O Equipment

Type KSR-33 Teletype

10 char/sec ACSII standard 8-bit code

Type 2500 Paper Tape Reader

300 char/sec

Type BRPE Paper Tape Punch

63.3 char/sec
Standard I/O Options

Type CROl B Card Reader and Control

100 cards/min, 12 row, 80 col cards; alphanumeric or binary

Type 421 Card Reader and Control

200 cards/min, (800 Type 421 B); alphanumeric or binary

Type 40 Card Punch and Control

Controls card punch 1 row at a time at 40 msec
intervals (100 cards/min)

Type 647 Automatic Line Printer

Se lecHon, 64 characters; I ine length 120 char-

and Control

actersj print rate, 300, 600 or 1000 lines/min.

Loading, printing and format under program
control.
Type TU55 DECtape and Control

Fixed address, magnetic tape; read, write, and

Type 550

search speed, 80 ips; recording density, 375 bpi;
storage, 3 mi II ion bits; prerecorded timing and
mark tracks

Type 57A Automatic Magnetic Tape

Controls up to 8 IBM or IBM compatible tape trans-

Control

ports. Controls to read or write at densities of
200, 556 or 800 char/in.; speed, 75 or 112.5 ips.

Type 570 Magnetic Tape Transport

Reads and writes at 75 or 112.5 ips at program
selected densities of 200, 556, or 800 char/in.
IBM compatible.

Type 545 Magnetic Tape Transport

Speed, 45 ips; densities of 200, 556 or 800 bpi.
IBM compatible.

1-11

PDP-7 MAINTENANCE MANUAL

TABLE 1-5

SUMMARY OF PERIPHERAL EQUIPMENT CHARACTERISTICS (continued)
Unit

Capabi lity
Standard Vo Options (continued)

Type 50 Magnetic Tape Transport

Use with Type 57A to read/write IBM compatible
tapes; transfer rates of 15,000 or 41 , 700 char/sec;
tape speed, 75 ips at densities of 200 or 556
char/in.

Type 24 Seria I Drum System

Block transfers through data interrupt facility by
interlaced program and drum transfer operation.
Storage, 32,768; 65,536; or 131,072 words.

Type 350 Incremental Plotter Control

Controls 1 Digital Incremental Recorder, made by
California Computer Products, for high-speed
point plotting, continuous curves, etc.

Type 34A Oscilloscope Display

Displays data point-by-point on 5-inch scope.
Horizonta I axis to 10 binary bits; vertica I axis
to 10 binary bits.

Type 30D Precision CRT Display

Random positioning point plotting; 16-inch CRT;
raster, 9-3/8 in. square with 1024 points per
side. Plotting rate is 35 iJsec per point.

Type 340 Precision Incremental CRT
Display
Raster

9-3/8 in. square

Plotting rate

1 .5 iJsec per point in vector, increment, and character modes

Random point plotting rate
Types 33 and 342 Symbol Generators

35 iJsec
Type 33 used with Type 30D Display
Type 342 used with Type 340 Display

Type 370 Photomultiplier Light Pen

High-speed detection of display on Types 34A,
30D and 340 Displays. Computer samples detection to alter program.

1-12

PDP-7 MAINTENANCE MANUAL

TABLE 1-5

SUMMARY OF PERIPHERAL EQUIPMENT CHARACTERISTICS (continued)
Unit

Capability
Standard I/O Options (continued)

Type 138E Analog-to-Digital Converter

Successive approximation type; input range, 0 to
lOv; converted binary, selectable from 6 to 12
bits. Combinations of switching point accuracy
and number of bits are switch selectable.

Type 142 Ana log-to-Digita I Converter

High-speed converter; converts to a single 10-bit
binary number in 6 flsec. Conversion accuracy
is ± 0.15%, ± 1/2 LSB.

Type 139E Multiplexer and Control

Select up to 64 analog input channels for use
with Types 142 or 138E

Types ADA-1 Analog-Digital-Analog

For fast real-time conversion between digital and

Converter

ana log computers

Max sample rate D/A

200 kc

Max sample rate A/D and interface

100 kc

Word length

ten bits

Type 630 Data Communication System

Real-time interface with Teletype stations.
Avai lable for ha If-duplex and full-duplex operation with up to 64 stations.

Type 140 Relay Output Buffer

Inputs from computer accumulator to actuate
18 relays to provide either direct digital control
or signal generation for external equipment

Type 195 Inter-Processor Buffer

Provides interface with another computer for
bidirectional data communication asynchronously

1 .9

REFERENCING CONVENTIONS
The Digital Equipment Corporation engineering drawing conventions and instruction manual

referendng sh.ould be understood at this point. A study of the reference conventions in this paragraph
and chapter 6 wi II save considerable time and preselVe thought continuity when reading the text that follows. Any reference to figure numbers or table numbers indicates that the illustration or table is located
in the denoted chapter. For example, figure 3-1 is located in chapter 3, and is the first illustration in that
chapter.

1-13

PDP-7 MAINTENANCE MANUAL

All engineering drawings have a full drawing number. These drawings are included in chapter 6.
In text, references to engineering drawings are abbreviated in the following manner:
Full Drawing No.

D\KA~7~/O-2} .,

Drawing No. of Set
Processor Drawing Set No.

First text reference
All other text references

KA77A-2

-2

To locate a specific signal or function, the origin of the signal on a specific drawing is stated
in one of two conventions.
Example 1
liThe BGN pulse developed at PA(D23,4)1I where
PA - Module Type
D23 - Physical Location of Module
4
- Specific drawing number of previously mentioned set.
For complex block schematics the second convention is used.
Example 2
liThe CLR pulse generated at Module PA(2:C4)" where
PA - Modu Ie Type
2 - Specific drawing number of previously mentioned set
C4 - Roadmap coordinate location on drawing.

1-14

PDP-7 MAINTENANCE MANUAL

CHAPTER 2
OPERATION

2.1

INTRODUCTION
This chapter provides sufficient operating information for a technician acquainted with computer

systems similar in scope to the ?DP-7, and contains descriptions in tabular form of all system controls and
indicators, references for detai led information, and a discussion of maintenance programming considerations
for the operator. To become fu Ily cognizant of programming maintenance procedures for the PDP-7, the
operator must assimi late the information in th is chapter a long with the diagnostic routines in chapter 5,
assuming he has previously digested the programming and operating discussions found in the PDP-7 User
Handbook, F-75A.

2.2

SYSTEM CONTROLS AND INDICATORS
The following pages contain tables that list and define all system manual controls and indicator

lights. These are arranged on the following system elements (see figure 1-2): operator console, indicator
panel, Teletype console, and perforated tape reader unit. On all panels, an indicator light lIon ll denotes
a binary 1 in the associated register bit or the flip-flop control function.
The operator console and the indicator panel contain all major controls and indicarors for manual manipulation and for monitoring system operations. The operator console has major operating controls
such as STOP, START, CONTINUE, etc., and switches for selecting processor accumulator contents and
memory addresses for inserting data into the processor. During continuous operation this panel displays the
major processor register contents and various status conditions. The indicator panel displays memory conditions and both status and contents of functions and registers associated with the standard input/output
facility.

2.2.1

Operator Console Controls and Indicators
The operator console appears in figure 2-1, and table 2-1 lists the functions of the controls and

indicators.

2-1

PDP-7 MAINTENANCE MANUAL

LINK PIE RUN

MEMORY SUFFER

DUUI

CII,[ X X ][ II), I X )' X X 't 1.11
MUL TII'LIER QUOTIENT

ceo

X )[ X X 't I (J

EXAMfNl.

D[POSII

l XAMIIIIL
NI XI

O[POSI1'
NEXT

[:)(IENO

RLAO

Figure 2-1

PUNCH cEEO

SINGLE STEP

51111<>1.1:, IIIISI

OJ EIC

pown<

Operator Console

OPERATOR CONSOLE CONTROLS AND INDICATORS

Control or Indicator
START key

IlIIsr"uC rl')~~

AO()llfSS

IRAP

TABLE 2-1

!lRLAK

MEMORY ADOHI',!;S

ACCUMULATOR

CONIINUI:,

[)(""curt

Pf<Qe f<AM CO\JN IE R

ACCUMULATOR

c,', '1* X]( I X )[ X

IET'CH

c c c
cccrm

(.11)[1 X )[ I X )[ X X ]( X X ][ X XJ

Function
Starts the processor. The first instruction is taken from the
memory cell specified by the setting of the ADDRESS switches.
The START operation clears the accumulator (AC) and link (L),
and turns off the program interrupt faci I ity .

STOP key

Stops the processor at the completion of the memory cycle
in progress.

CONTINUE key

Causes the computer to resume operation from the point at
which it was stopped. Besides the normal off and momentary
on positions, this key has a latched-on position obTained by
raising the key instead of depressing.

EXAMINE key

Places the contents of the memory cell specified by the
ADDRESS switches into the AC and memory buffer (MB).
This operation is accomplished by automatically performing a
LAC instruction (see User Handbook) when the EXAMINE key
is pressed. At the completion of the operation, memory address register (MA), holds the contents of the ADDRESS switches
and the program counter (PC) contains the address of the next ce II.
2-2

PDP-7 MAINTENANCE MANUAL

TABLE 2-1

OPERATOR CONSOLE CONTROLS AND INDICATORS (continued)
Function

Control or Indicator
EXAMINE NEXT key

P laces the contents of the cell specified by the PC into the AC
and MB. The contents of the PC are incremented by 1, and
the MA contains the address of the register examined.

DEPOSIT key

Deposits the contents of the ACCUMU LA TOR switches into the
memory cell specified by the AD DRESS switches. This operation is accomplished by automatically performing tasks similar
to the combination of the CLA, OAS, and DAC instructions
(refer to Handbook) when the DEPOSIT key is pressed. The
contents of the ACCUMULATOR switches remain in the AC
and MB. The contents of the ADDRESS switches appear in the
MA. The PC contains the address of the next cell.

DEPOSIT NEXT key

Deposits the contents of the ADDRESS switches into the memory
cell specified by the PC. The contents of the PC are then incremented by 1. At the completion of the operation, the contents of ,the AC and MA are the same as for the DEPOS IT
operation.

READ-IN key

Punched paper tape is read in binary mode and stored in a core
memory block when this key is pressed and released. The ADDRESS switches supply the first address of the memory block.
After reading the tape, program control transfers to the processor
wh ich executes the last instruction word stored in the block.
To indicate that this last computer word on tape is the instruction
to be executed next, a hole must be punched in channel 7 of the
last I ine of the three binary I ines that constitute the last word.

SPEED switch and control

These two controls vary the repetition rate of manual operations
from approximately 40 tJsec to 8 sec. The switch (left) is a 5position coarse control; the control, (right) is a continuously
variable fine control. S lowest speed is obta ined with both
controls in the fully counterclockwise position.

2-3

PDP-7 MAINTENANCE MANUAL

TABLE 2-1

OPERATOR CONSOLE CONTROLS AND INDICATORS (continued)
Function

Control or Indicator
Console lock

This key-operated, 2-position lock switch prevents inadvertent
key operation from disturbing a program in progress. When the
key is turned counterclockwise, the console is unlocked and
a II controls operate norma Ily. When the key is turned clockwise, the console is locked; operation of any of the console
keys, the SPEED controls, or the POWER, SINGLE STEP,
SINGLE INST, or REPEAT switches does not affect the operation of the computer. The program, even with the keys disabled by the lock, can monitor the status of the ACCUMU LA TOR
switches.

TRAP switch and indicator

Permits the program to enter the trap mode.

EXTEND switch and indicator

In the raised position, this switch allows the extend mode to be
enabled by the EXAMINE and DEPOSIT keys. The indicator
Iights to denote enabling of the extend mode control.

PUNCH toggle switch
and FEED pushbutton

The toggle switch controls application of primary power to the
perforated tape punch. When the switch is down, punch power
is under program control; when up, punch power is on. The
pushbutton causes the perforated tape punch to punch tape
leader. Punch power rema ins on for an additiona I 5 sec as it
does under program control.

SINGLE STEP switch and
indicator

This switch causes the computer to stop at the completion of
each memory cycle. Repeated operation of the CONTINUE
key wh i1e th is switch is on steps the program one memory cyc Ie
at a time. The indicator Iights to denote operation in the
single-step mode.

SINGLE INST switch
and indicator

This switch causes the computer to stop at the completion of
each instruction. Repeated operation of CONTINUE key with
th is switch on steps the program one instruction at a time.

2-4

PDP-7 MAINTENANCE MANUAL

TABLE 2-1

OPERATOR CONSOLE CONTROLS AND INDICATORS (continued)
Function

Control or Indicator

When both switches are on, SINGLE STEP takes precedence
over SINGLE INST. The indicator lights to denote operation
in the single-instruction mode.
REPEAT switch and
indicator

This switch causes repetition of the operations initiated by pressing CONTINUE, EXAMINE NEXT, or DEPOSIT NEXT keys as
long as the key is held on. The S PEED controls govern the rate
of repetition. The indicator I ights to denote activation of the
REPEAT controls.

POWER switch and
indicator

This switch controls the application of primary power to the
computer and to a II its attached externa I devices. When power
is on, the indicator lights.

ACCUMULATOR switches

Used to establish the 18-bit word to be placed in core memory
by the DEPOSIT and DEPOSIT NEXT keys, or the word to be
placed in the AC by a program. These switches are also used
for program sense control.

ADDRESS switches

Used to establish the 15-bit core memory address loaded into
the PC by operation of the START, EXAMINE, or DEPOSIT
keys.

MULTIPLIER QUOTIENT
indicators*

Display the contents of the MQ.

ACCUMULATOR indicators

Display the contents of the AC.

MEMORY BUFFER indicators

Display the contents of the MB.

MEMORY ADDRESS
indicators

Display the contents of the MA.

*These indicators function only when the computer is equipped with a Type 177 Extended Arithmetic
Element option.
2-5

PDP-7 MAINTENANCE MANUAL

TABLE 2-1

OPERATOR CONSOLE CONTROLS AND INDICATOR (continued)

Control or Indicator

Function

PROGRAM COUNTER
indicators

Display the contents of the PC.

LINK indicator

Display the contents of the link.

PIE indicator

Lights when the program interrupt is enabled.

RUN indicator

Lights when the computer is executing instructions.

FETCH, DEFER, EXECUTE,
BREAK indicators

Light to display the major control state of the next memory
cycle.

Indi cator Pane I

2.2.2

The Indicator Panel is shown in figure 2-2 and indicators are I isted in table 2-2.

BREAK STARTED

flAG

( X X ][ X X ][ X 1.][ XX l[ XX ]C

CtIJ......
ACT

CHANNEL ON

(111[ X X)( X I,(XX 1(1 X ]C
o

READ

INH

WRITE

CC C CC
I

RUN

1516

BINARY

T T BUFFER

BINARY

!' r P SUFFER

FLAG

C C C till"'"

P T R BUFFER

FLAG

C C C [X X" X1)( 1111"'"
o

Figure 2-2

Indicator Panel

2-6

1314

PDP-7 MAINTENANCE MANUAL

TABLE 2-2

INDICATOR PANEL FUNCTIONS

Indicator
READ 1,2

Function
Designate the status of timing control flip-flops in the memory
control and indicate that the core memory is in a read cycle.

INH

Designates the status of the INH (inhibit) flip-flop in the
memory control and indicates the memory is in a write cycle.

WRITE 1,2

Designate the status of timing control flip-flops in the memory
control and indicate that the core memory is in a write cycle.

CHANNEL ON

Lighted indicators denote enabled priority interrupt channels
of the Type 172 Automatic Priority Interrupt.

BREAK STARTED

Lighted indicators denote program interrupt channels that are
active (requesting or using a break cycle).

RUN

Denotes the status of the RUN flip-flop in the Type 444B Perforated Tape Reader and Control, and indicates operation of
this device.

BINARY (bottom row)

Lights to designate that the perforated tape reader is in the
binary mode. If this lamp is not lit, the reader is in the alphanumeri c mode.

FLAG (bottom row)

Denotes the status of the perforated tape reader flag.

PTR BUFFER

Indicates the contents of the data buffer register of the perforated tape reader (last character or binary word read) .

ACT

Denotes the active or operating status of the Type 75D Perforated Tape Punch and Control.

BINARY (center row)

Lights to designate that the perforated tape punch is in the
binary mode.

FLAG (center row)

Denotes the status of the perforated tape punch flag.

2-7

PDP-7 MAINTENANCE MANUAL

TABLE 2-2

INDICATOR PANEL FUNCTIONS (continued)

Indicator
PTP BUFFER

Function
Indicates the contents of the data buffer register of the perforated tape punch {last character punched) .

FLAG (top row)

Denotes the status of the Type 649 Teleprinter and Control

I ine unit in (TTY) flag. (The in direction is referenced to the
computer, not to the Teletype equipment.)
TT BUFFER

Indicates the contents of the Teletype control line unit in (TTY)
data register (code of the last keyboard character struck) .

2.2.3

Perforated Tape Reader Controls
The tape reader appears in figure 2-3. Table 2-3 lists the tape reader controls and explains

their functions.

Figure 2-3

Perforated Tape Reader

2-8

PDP-7 MAINTENANCE MANUAL

TABLE 2-3

TAPE READER CONTROLS

Control

Function

POWER ON switch

Applies power to the power supply, capstan drive motor, and
fan motor.

READY/LOAD switch and
Tape width selector knob

In its clockwise position, the READY/LOAD switch deenergizes the brake and pinch roller to a Ilow tape insertion.
The knob may be moved in or out to handle different tape
levels.

2.2.4

Teletype Controls
The Teletype appears in figure 2-4. Table 2-4 lists the Teletype controls and explains their

functions.

(

Figure 2-4

Teletype Console

2-9

PDP-7 MAINTENANCE MANUAL

TABLE 2-4

TELETYPE CONSOLE CONTROLS
Function

Control
KEYBOARD

Provides a means of supplying input data, in the form of typed
characters, to the computer and/or the page printer, depending on the setting of the LINE/OFF/LOCAL switch.

LINE/OFF/LOCAL switch

Controls the application of primary power to the Teletype and
controls data connection between the Teletype and the central
processor. In the LINE position, the Teletype is energized
and connected as an I/O device of the computer. In the OFF
position, the Teletype is de-energized. In the LOCAL position, the Teletype is energized for off-line operations, and
the signal connections to the processor are broken. Both line
and local use of the Teletype requires that the computer be
energized through the POWER switch.

2.3

OPERATING PROCEDURES
Several methods are available for loading and unloading PDP-7 information. The method used

is dependent upon the form of the information, time limitations, and the peripheral equipment connected
to the computer. The following procedures are basic to any use of the PDP-7, and although they may be
used infrequently later on, they are valuable in preparing the initial programs and learning the function
of mach ine input and output transfers.

2.3.1

Manua I Data Storage and Modification
The use of the facilities on the operator console permits manual storage or modification of

programs and data. Chief use of the manua I data storage facil ities is to load the Readin Mode Loader
program and a II other programs in read- in mode format into the computer core memory.
The Readin Mode (RIM) Loader is a program used to automatically load programs into PDP-7
from perforated tape in RIM format. This program and the RIM tape format are described in the PDP-7
User Handbook F-75A and in Digital Program Library descriptions. The RIM program is listed in table 2-5
for rapid reference and can be used as an exerc ise in manua I data storage. To store data manua Ily in the
PDP-7 core memory:

2-10

PDP-7 MAINTENANCE MANUAL

a. Turn the lock switch counterclockwise and set the POWER switch to the up
position.
b. Set the ADDRESS switches to correspond with the address of the first word to be
stored. (In the case of the RIM loader program, this is 17762 ).
a
NOTE: Whenever an address in core memory is given in this section, it is
intended to apply to an aK memory. To translate this to the correct 4K memory address, subtract 1OOOOa.

c. Set the ACCUMULATOR switches to correspond with the binary contents of the
fi rst word. (In the case of the RIM Loader program, this is zero.)
d. Momentari Iy Iift the DEPOSIT/DEPOSIT NEXT key to deposit the word in
memory .
e.

Note the contents of the four storage registers (AC, MB, MA, and PC) as given

by their respective indicators after completion of the deposit operation. The AC and
MB must both contain the data word just deposited, the MA must contain the address
of the core memory cell in which the word was deposited, and the PC must contain
the address of the next consecutive core memory cell (MA+l).
f.

Store a" additional data words by momentari Iy depressing the DEPOSIT/DEPOSIT

NEXT key to the DEPOSIT NEXT position after each successive data word has been
set in the ACCUMU LA TOR switches. The contents of the PC wi II be incremented by 1
during each deposit next operation, thus setting up the address of the core memory
cell used for the next operation. The RIM Loader contains the following program:

TABLE 2-5
Address
(octa I)

Content
(octa I)

READIN MODE (RIM) LOADER PROGRAM
Tag

Mnemonic

Comments
--

17762/
17763/
17764/
17765/
17766/
17767/
17770/

0
700101
617763
700112
700144
637762
700144

GO,

0
RSF
JMP .-1
RRB
RSB
JMP I R
RSB

/READ ONE BINARY WORD
/WAIT FOR WORD TO COME IN
/READ BUFFER
/READ ANOTHER WORD
/EXIT SUBROUTINE
/ENTER HERE, START READER
/GOING
---".--..

-.---~.------

2-11

PDP-7 MAINTENANCE MANUAL

TABLE 2-5
Address
(octal)

Content
(octa I)

17771/
17772/
17773/
17774/
17775/
17776/

117762
057775
417775
117762
0
617771

READIN MODE (RIM) LOADER PROGRAM (continued)
Tag

Mnemonic

JMS R
DAC OUT
XCT OUT
JMS R
0
JMP G

OUT,

Comments

/GET NEXT BINARY WORD
/EXECUTE CONTROL WORD
/GET DATA WORD
/STORE DATA WORD
/CONTINUE

g. To recheck a loaded program, set the ADDRESS switches to the starting address
and momentarily set the EXAMINE/EXAMINE NEXT key to the EXAMINE position.
After the first cell has been checked, the remaining cells may be examined in sequence simply by repeatedly setting the switch to the EXAMINE NEXT posit:on
without adjusting the ADDRESS switches. By repeating steps b through d using the
address of the cell in question, it is possible to a Iter the contents of any cell .

2.3.2

Loading Binary Data Using READ-IN Key
Binary format tapes (inc luding the RIM Loader tape) can be loaded directly into the computer

without the need of a prestored program, as follows:
a . Turn the computer lock switch counterc lockwise and set the POWER switch to
the up position.
b. Set the tape reader POWER ON switch to ON.
c. Set the READY/LOAD switch to LOAD (c lockwise) and insert the binary tape.
The tape is placed in the right-hand loading bin of the reader, and, during reading,
travels to the left-hand bin. When the tape is properly positioned, there wi" be
three bit positions to the rear of the sprocket wheel and five bit positions to the front.
d. Set the tape reader READY/LOAD switch to READY.
e. Set up the starting address of the tape (found on the leader) on the ADDRESS
switches.
f.

Press and release the computer READ-IN key. The tape wi II be read automatica lIy.

2-12

PDP-7 MAINTENANCE MANUAL

2.3.3

Loading Data Under Program Control
Information (in other than binary format) can be stored or modified in the computer automatically

only by executing programs previously stored in memory. For example, having the RIM Loader stored in
the core memory allows the loading of RIM format tapes as follows:
a. Turn the computer lock switch counterclockwise and set the POWER switch to
the up position.
b. Set the tape reader POWER ON switch to ON.
c. Set the READY/LOAD switch to LOAD and insert the tape into the tape reader.
d. Using the ADDRESS switches, set the starting address of the RIM Loader program
(17770) .
e. Press and release the computer START key.

Press the START key. The tape is read automatica lIy. The program contained on

the tape may be initia Iized and started automatica lIy after being loaded. This occurs
because some tapes in RIM format are conc luded with address 0000 and a data word
equa I to one less than the starting address of the program just read. Therefore, after
the last tape character is read, the program starting address is taken by the program
counter as the address of the next instruction to be executed.

2.3.4

Assembling Programs
Programs prepared in binary format and written in symbolic language can be assembled into

binary, machine-language program tapes as described in appropriate Digital Program Library documents,
as follows:
a. Turn the 10ck switch counterclCl>ckwise and set trhe POWER switch to the on (up)
position.
b. Set the tape reader POWER ON switch to ON.
c. Store the RIM Loader program, either manually or by use of the READ-IN key,
as previously described.

2-13

PDP-7 MAINTENANCE MANUAL

d. Load the assembler program by means of the assembler tape. Since the assembler
tape is in RIM format, it can be loaded by the method described in paragraph 2.3.3.
When the tape has been run, the AC should contain aliOs. If it does not, a checksum error has been detected; showing improper storage of the program. When th is
occurs, the tape must be rerun unti I the AC does fina Ily conta ina II Os at the conc lusion of the loading process, indi cating proper storage of the program. Repeated
errors indicate defects in either the assembler tape or the PDP-7 system.
e. Set the tape reader READY/LOAD switch to the LOAD position, and insert the
symbol ic language tape to be converted into mach ine-Ianguage, binary format, into
the tape reader. Put switch back to READY position.
f.

Put the starting address of the assembler program (0020) into the ADDRESS switches

of the operator console. (Set ACCUMU LA TOR switch 10 up to indicate ASCII, or
down to indicate FIODEC.)
g. Press and release the CONTINUE key.
h. When assembly is complete, the assembler wi II stop with a Ills in the AC.

2.3.5

Te letype Code
The 8-bit code used by the Model 33 KSR Teletype unit is the American Standard Code for In-

formation Interchange (ASCII) modified. This code is read in the reverse of the normal octal form used
in the PDP . . . 7 since bits are numbered from right to left, from 1 through 8, with bit 1 having the most sign ificance. Therefore, perforated tape is read:

8
Least Significant
Octa I Bit

Most Significant
Octal Bit
2

Tape is loaded into the reader:

t
The Model 33 KSR set can generate all assigned codes except 340 through 374 and 376. Generally, codes 207,212,215,240 through 337, and 377 are sufficient for Teletype operation. The Model
33 KSR seT can detect all characters, but does not interpret as commands all of the codes that it can generate. The standard number of characters printed per Iine is 72. The sequence for proceed ing to the next

2-14

PDP-7 MAINTENANCE MANUAL

----

I ine is a carriage return followed by a I ine feed (as opposed to a I ine feed followed by a carriage return).
Key or key combinations required to produce octa I codes from 200 through 337, 375, and 377 are indicated
in table 2-6 with the associated ASCII character.

TABLE 2-6
Octal
Code

TELETYPE CODE

Character
Name

ASCII
Character

Teletype
Character

Key or Key
Combinations

200

Null/Idle

NULL

CTRL @

201

Start of Message

SaM

CTRL A

202

End of Address

EOA

CTRL B

203

End of Message

EOM

CTRL C

204

End of Transmission

EaT

CTRL D

205

Who Are You

WRU

CTRL E

206

Are You

CTRL F

207

Audible Signa I

BELL

CTRL G

210

Format Effector

CTRL H

211

Horizontal Tabulation

H TAB

CTRL

212

Line Feed

CTRL J

213

Vertical Tabulation

V TAB

CTRL K

214

Form Feed

CTRL L

215

Carriage Return

CTRL M

216

Shift Out

CTRL N

217

Sh ift In

CTRL a

220

Device Control Reversed for
Data Line Escape

DCO

CTRL P

221

Device Control On

DC1

CTRL Q

222

Device Control (TAPE)

DC2

CTRL R

223

Device Control Off

DC3

CTRL S

224

Device Control ~

DC4

CTRL T

225

Error

ERR

CTRL U

226

Synchronous Idle

SYNC

CTRL V

227

Logical End of Media

LEM

CTRL W

230

Separator, Information

CTRL X

231

Separator, Data Delimiters

CTRL Y

232

Separator, Words

CTRL Z

2-15

PDP-7 MAINTENANCE MANUAL

TABLE 2-6

TE LETYPE CODE (continued)

Octal
Code

Character
Name

233

Separator, Groups

SHIFT CTRL K

234

Separator, Records

SHIFT CTRL L

235

Separator, Fi les

SHIFT CTRL M

236

Separator, Misc.

SHIFT CTRL N

237

Separator, Misc.

SHIFT CTRL a

240

Space

241

Exclamation Point

242

Quotation Marks

SHIFT II

243

Number Sign

SHIFT #

244

Dollar Sign

SHIFT $

245

Percent Sign

SHIFT %

246

Ampersand

SHIFT &

247

Apostrophe

SHIFT I

250

Parenthesis, Beginning

SHIFT (

251

Parenthesis, Ending

SHIFT)

252

Asterisk

SHIFT *

253

Plus Sign

SHIFT +

254

Comma

255

Hyphen

256

Period

257

Virgule

260

Numeral 0

261

Numeral 1

262

Numeral 2

263

Numeral 3

264

Numeral 4

265

Numeral 5

266

Numeral 6

267

Numeral 7

270

Numeral 8

271

Numeral 9

ASCII
Character

Teletype
Character

Space

Key or Key
Combinations

Space Bar
SHIFT!

2-16

PDP-7 MAINTENANCE MANUAL

TABLE 2-6
Octal
Code

TELETYPE CODE (continued)

Character
Name

272

Colon

273

Semicolon

274

Less Than

275

ASCII
Character

Teletype
Character

Key or Key
Combinations

SHIFT <

Equals

<
=

276

Greater Than

SHIFT>

277

Interrogation Point

SHIFT?

300

SHIFT @

301

Letter A

302

Letter B

303

Letter C

304

Letter D

305

Letter E

306

Letter F

307

Letter G

310

Letter H

311

Letter I

312

Letter J

313

Letter K

314

Letter L

315

Letter M

316

Letter N

317

Letter 0

320

Letter P

321

Letter Q

322

Letter R

323

Letter S

324

Letter T

325

Letter U

326

Letter V

327

Letter W

330

Letter X

2-17

SHIFT =

PDP-7 MAINTENANCE MANUAL

TABLE 2-6
Octal
Code

TELETYPE CODE (continued)

Character
Name

ASCII
Character

Teletype
Character

Key or Key
Combinations

331

Letter Y

332

Letter Z

333

Bracket I Left

[

SHIFT K

334

Reverse Virgule

SHIFT L

335

Bracket I Right

336

Up Arrow (exponentation)

337

Left Arrow

]

SHIFT M

SHIFT +-

340 through 374 are not available
375

Unassigned Control

376

Not Avai lable

377

Delete/Idle/Rub Out

2.3.6

ALT MODE

DEL

RUB OUT

Local Teletype Operation
The Teletype can be used as an ordinary typewriter as follows:
a. Set the computer lock switch to the counterclockwise position.
b. Set the computer POWER switch to the up position.
c. Set the Teletype LINE/OFF/LOCAL switch to the LOCAL position.
d. Type out the desired information on the Teletype keyboard.

2.4

PROGRAMMING

2.4. 1

The Programming System
Programming instructions are to be found in chapter 3 and the PDP-7 User Handbook. Refer to

the User Manua I for detailed programming procedures.

2.4.2

Maintenance Programs
The basic maintenance routines for PDP-7 are:
Teleprinter 1/0 Test
C lock Interrupt Test
Reader and Punch Test

2-18

PDP-7 MAINTENANCE MANUAL

Maindec 710 (RPB Test)
Maindec 701 (Instruction Test)
Maindec 703 (Memory)
Maindec 702 (Address Test)
Contest II
(See Program Library List)
The first four are primari Iy input/output system tests; wh i Ie the Maindec routines are processor
and memory system checks. Refer to specific write ups in PDP-7 Program Library for detailed descriptions.
These routines are diagnostic programs designed to test specific functions within the computer
system. Maindec routines are available as perforated paper tapes in hardware readin mode (HRI) format.
Each diagnostic routine tape is accompanied by a description of the program, procedures for using the
program, and information on ana Iyzing the program resu Its to locate specific fai lures. Applications of
these routines are indicated at the appropriate points in chapter 5 as they apply to preventive or corrective
maintenance of the PDP-7 system. To execute these routines the user should be familiar with the machine
programming described in the User Handbook.

2-19

PDP-7 MAINTENANCE MANUAL

CHAPTER 3
SYSTEM DESCRIPTION

3.1

FUNCTIONAL DESCRIPTION
The major functional units of the PDP-7 are the central processor, the memory, and the VO

devices. The central processor performs arithmetic or logical operations upon data stored in memory and
controls the operation of the Vo devices. A series of instructions stored in memory, or the manipulation
of keys and switches on the operator consol e determ ines the nature and sequence of these operations.
During programmed operation, the processor retrieves from memory the instruction spec ified by the program, executes the instruction during one or more computer cycles, and then proceeds to retrieve and
execute the remain ing instructions specified by the program sequence. All arithmetic, logical, and control operations are performed as a function of three factors: the instruction retrieved from memory; the
major control state establ ished by the instruction; and the timing pulses produced by the processor.

Dur-

ing manual operation, the operator controls are used to stop and start programmed operation, to manually
select and examine specific memory locations, and to select special operating modes.

3.1. 1

Instructions
Instructions are of two types:

memory reference and augmented. All instructions contain an

operation code {specifying the nature of the instruction} in bits

through 3.

Memory reference instructions cause information to be stored in or retrieved from memory, and
contain a memory address as well as an operation code. All memory reference instructions require one
computer cycle in which the instruction is retrieved, and all except the jump instruction require a second
cycle in which to execute the instruction specified by the operation code. The jump does not cause
storage or retrieval of information, but transfers control of the processor from one block of consecutive
memory locations {containing instructions} to a different block of consecutive locations. The jump instruction is normally completed in one computer cycle.

If indirect addressing is employed, two cycles

are required for the jump and three cycles for other memory reference instructions.
Augmented instructions do not require reference to memory. Since no address is required, bits
4 through 17 are decoded to initiate various operations to extend or augment the operation code. Because no storage or retrieval operations are performed, most augmented instructions can be completed in
one computer cycle. Augmented instructions are divided into three classes:
a.

Instructions having an operation code of 648 are EAE instructions.

Instructions having an operation code of 708 are input/output transfer {lOT} commands,

and are used to control or test the status of I/O devices, or to effect an information transfer.

3-1

PDP-7 MAINTENANCE MANUAL

c. Instructions having an operation code of 748 are operate (aPR) commands, and are used for
basic processor data manipulation such as instruction skipping as a function of register condition, shifting, rotating, etc.
The formats of the various types of instruction words are illustrated in figure 3-1. Table 3-2
contains a I ist of the instructions performed by the PDP-7.

3.1.2

Major Control States
The computer operates in one of four major control states during each machine timing cycle.

One or more states are entered to execute an instruction. The states are fetch, execute, defer, and
break and are determined by the major state generator. Only one state exists at a time and all states,
except break, are determined by the programmed instruction being executed.

3.1 .2. 1

Fetch (F) - A new instruction is obtained when this state is entered. The contents of the memory

cell spec ified by the PC are placed in the MB, and the operation code (bits 0-3) of this instruction word is
placed in the I R. The contents of the PC are then incremented by 1. If a single-cycle instruction is
fetched, the operations specified are performed during the last part of the fetch cycle; then the next cycle
is a fetch state for the next instruction. If a 2-cycle instruction is fetched, the succeeding control state is
either defer or execute.

3.1.2.2

Defer (D) - When bit 4 of a memory reference instruction is a 1, the defer state is entered fol-

lowing the fetch state, to perform the indirect addressing. The memory location addressed by the instruction contains the address of the operand, and access to the operand is deferred to the next memory cycle
(execute) •

3. 1 .2.3

Execute (E) - This state is establ ished only when a memory reference instruction is being exe-

cuted. The contents of the memory cell addressed are brought into the MB, and the operation spec ified
by the contents of the IR is performed.

3.1.2.4

Break (B) - When this state is established, the sequence of instructions is broken for a data inter-

rupt or a program interrupt.

In both cases, the break occurs only at the completion of the current instruc-

tion. The data break interrupt allows for the transfer of information between core memory and an external
device. When this transfer has been completed, the program sequence is resumed from the point of the
break. The program interrupt causes the sequences to be altered. The contents of the PC and the contents
of the I ink are stored in core memory location 0000, and the program continues from location 0001 •

3-2

PDP-7 MAINTENANCE MANUAL

OPERATION
CODE

ADDRESS

13 1

'4 '5
1

r!6J!7J

'--..---'
INDIRECT
ADDRESSING
IF BIT IS A 1

Memory Reference Instruction Bit Assignments

OPERATION
CODE 70

CLEAR AC
AT EVENT
TIME 1 IF
BIT IS A 1

DEVICE
SELECTION

GENERATE
AN I/OP 2
PULSE AT EVENT
TIME 2 IF BIT
IS A 1

12 1'3 1

'4 '5 \16 \17
1

'--.,--J

SUB-DEVICE
SELECTION

GENERATE
AN IIOP 4
PULSE AT
EVENT TIME
4 IF BIT IS
AI

GENERATE
AN I/OP 1
PULSE AT
EVENT TIME
1 IF BIT IS
At

lOT Instruction Bit Assignments

IF BIT 8
IS A 1

ROTATE 1

OPERATION
CODE 74

~~~li~O~ ~

IF BIT 7
IS A 1

S~A

CLA
IF BIT
IS A 1

2 POSITIONS
IF A 1

SZL
SPA \ HLT I RTR • RTL \
IF BIT IF BIT IF BIT IF 81T IF BIT IF BIT
IS A 1 IS A 1 IS A 1 IS A 1 IS A 1 IS A 1

CML
IF BIT
IS A 1

t-.--V--"'----,~F~:::r--J.-"Ir-~--.

3i4 \ ~ I I
6

7 \ 8 \ 9 \ to

\11 ~1'3\141'~ 1 '6 \'7

C~S ~ R~lfTT
A 0 TO

IF BIT

~:~3~i

IS A 1

SKIP

~~N~II~~

9,10,11 IF
BIT81SAI
SNL
IF BIT
IS A 0
\

~~Ys
IF BIT

IF BIT

liS A '. IS A I, IS A 1

~
IF BIT
IS AI

IF BIT 7
ISAO
SZA
SMA
IF 81l IF BIT
IS A 0 IS A 0 J
t
IF BIT 8
IS A 0

Group 1 Operate Instruction Bit Assignments

OPERATION
CODE 74

ADDRESS SIZE
NUMBER

I 9J!0 111 \12 1 '3 1 '4 1 15 \

L--y---J

CONTAINS
AI TO
SPECIFY
GROUP 2

____________________________________

~y~

_____________________________---.-J

NUMBER LOADED INTO "rHE AC

Group 2 (LAW) Operate Instruction Bi t Assignments
Figure 3-1

Instruction Word Format
3-3

PDP-7 MAINTENANCE MANUAL

3.1.3

Timing
Seven times (designated Tl through T7) occur in sequence during each computer cycle. At

each time, two pulses are generated, one of which is 40 nsec and the other 70 nsec wide. These time
pulses cause gating circuits to perform sequential or synchronized logical or control operations. The
narrow pulses are used for operations where timing is critical, such as the simultaneous sampl ing and incrementing of a register; the wider pulses are used to initiate gating operating where timing is less critical. The intervals between successive pairs of timing pulses permit gates and registers to settle before
initiating a new operation.

During each computer cycle, memory reading occurs between times T2 and

T3; memory writing starts at time T4 and occupies the remaining portion of the cycle.

3.2

LOGIC FUNCTIONS
Both manual and programmed operation of the PDP-7 are required for the performance of any

complete task. Manual operation is normally limited to the following: storing a brief loader program;
modifying or examining data or addresses in a program already stored; or establishing the starting conditions for programmed operation.

In programmed operation, data and the sequence of instructions which

constitutes the program are loaded into the core memory; the starting address of the program is manually
establ ished; and the computer is manually started. The computer then successively executes the instructions spec ified by the program. For maintenance purposes and to fac iI itate debugging, there is provision
for advancing the program one cycle or one instruction at a time.

3.2. 1

Flow Diagram Interpretation
Two flow diagrams are provided: one, contained in engineering drawing 3, shows the events

that take place during each of the possible manual operations; the other, contained in engineering drawing 4, shows the events that take place during the execution of instructions . The two flow diagrams, sim ilar
in their arrangement, at the extreme left, show the timing pulses which initiate events at various times in
the cycle.

In the flow diagram of manual operations, these timing pulses are designated KEY MANUAL

and SPO through SP4.

In the flow diagram of programmed operations, the timing pulses are designated

Tl through T7. Times (in ,",sec or nsec), appearing in boxes that straddle the horizontal boundary line
separating two timing pulses, represent the time interval lapse between occurrence of those two pulses.
Events initiated by a specific timing pulse appear in rectangular boxes placed between boundary
lines associated with that pulse. It is important to note that all such events are initiated simultaneously
by the timing pulse if they form part of the event sequence. For example, in following the deposit (DP)
sequence on engineering drawing 3 at time SP2 the event ASl -- PC is followed in the sequence by DACIR and ACSl - AC. The vertical separation does not imply that the ASl ->- PC operation precedes the

3-4

PDP-7 MAINTENANCE MANUAL

other two; on the contrary, they are all initiated simultaneously. The vertical separation merely fac it itates the ill ustration of branches to other possible sequences.
Events in a sequence which is not specifically designated by a key name or instruction name
are assumed to be common to all sequences (e.g., 0 -.. MA at time SP1, engineering drawing 3).

Where

a common sequence branches into two or more sequences, depending on the operation in progress, the
operation associated with a given sequence is identified immediately below the branch. For example,
at time SP2 the event ASl -PC occurs in a sequence common to both examine (EX) and deposit (DP)
operations. The sequence then branches.

If an examine operation is in progress, pulse SP2 initiates the

event LAC -IR, but if a deposit operation is in progress, LAC -IR does not occur.

Instead, pulse SP2

initiates events DAC _ I Rand ACS1 -+ I R. Similarly, a common sequence may follow several separate
sequences. Thus, on engineering drawing 4, each of the separate sequences associated with the START,
CONTINUE, EXAMINE, and DEPOSIT operations is followed by the event 1 - TP1 which takes place at
time SP4.
Note that some of the events specified in the rectangles of the flow diagram are unconditional;
that is, they invariably occur at the specified time when the operation with which they are associated is
in progress. Thus, when the START key is pressed, the event AS1 -+ PC always takes place at time SP2.
Other events are conditional upon the state of control fI ip-f1ops or register bits. Conditional events are
represented in the rectangles by a statement of the required condition, which is separated from the conditional event by a colon. Thus, at time SP2 of a readin operation (engineering drawing 3), the statements
in the rectangle indicate that if the read paper tape (RPT) fl ip-flop is in the 0 state, the contents of the
address switch register are transferred to the PC (RPT (0): AS1 -+ PC). However, if the RPT flip-flop is
in the 1 stote, 1 is added to the contents of the PC and the operation code DAC (deposit content of accumulator in specified memory cell) is set into the instruction register (RPT (1): + 1 -+ PC DAC - IR).
On engineering drawing 4, the seven time pulses that occur during each computer cycle appear
at the left. The column immediately to the right contains the events associated with memory which occur
during every computer cycle, regardless of the major control state established. This column, designated
Events Common, also contains certain conditional events, whose occurrence is dependent on factors other
than the major state. The other events on th is drawing are grouped according to the major state established. Each major state (fetch, defer, execute, and break) lasts for one computer cycle, and all start
in the fetch state.
The exact mechanism by which the CP performs a function specified by an event shown on the
flow diagram is found by referring to the appropriate engineering logic diagram and the corresponding
circuit description. When tracing a transfer function, it is best to begin by examining the input and
control gating of the register to which the transfer is being made. Thus, to trace the function ASl -+ PC,
first examine the logic diagram of the PC, which shows that a set of input gates is triggered by a pulse

3-5

PDP-7 MAINTENANCE MANUAL

designated ASl -.. PC. To find out how this pulse is generated, examine the logic drawing of the PC control. When there is doubt as to where a pulse or level is generated, consult chapter 6. This chapter lists
all command pulses and control levels in alphanumerical order of their designations, together with the
number of the engineering logic diagram on which are shown the circuits which generate any given signal.

3.2.2

Prel iminary Operations
The circuit breaker mounted on the 2-step power control unit located at the rear of the cabinet

governs circuit protection and primary control of all power entering the computer. The lock switch and
POWER switch located on the console panel governs manual control of primary power. With the lock
switch in the unlocked position, turn ing on the POWER switch energizes a relay in the power control unit,
which in turn immediately energizes the computer logic power supply. A second relay in the power control unit imposes a delay of 5 sec before the memory power supply is energized. This delay ensures that
all ac transients in the computer have compl etely decayed before the memory is energized. Sim ilarly,
when the POWER switch is turned off, the memory power suppl ies are de-energized immediately and the
computer logic power is maintained for 5 sec longer.

In each case, the delay ensures that switching

transients cannot cause current surges thereby destroying information stored in the core memory.
During the 5-sec turn-on delay period, an integrating circuit enables a variable clock.

While

the clock is enabl ed, it em its standard negative pulses at a repetition rate of 200 kc. These PWR CL K
(power clock) pulses repeatedly clear the RUN and memory control fI ip-flops and trigger two NAND
gates, which the 0 condition of the RUN flip-flop enables. The output pulses from the gates trigger two
pulse ampl ifiers, which produce the PWR CLR NEG (power clear negative) and PWR CLR POS (power clear
positive) pulses. These PWR CLR pulses are suppl ied to the interface to establ ish initial conditions in
peripheral equipment. Thus, if switching transients set any fI ip-flops during the first 5 sec after power
turn-on, the PWR CL K or PWR CLR pulses immediately clear them. This establ ishes correct initial conditions and ensures that a stored program cannot be accidentally started or disturbed.
The lock switch, in its unlocked position, connects all the console keys and switches to the
-15v supply, thereby permitting them to generate the levels required to start the computer and to perform
manual operations. When a program has been started manually, the lock switch may be turned to its
locked position. This grounds all the console keys and switches to prevent manual interference with the
program. A second deck of the lock switch bypasses the POWER switch, so that power cannot be accidentally turned off while a program is running.

3-6

PDP-7 MAINTENANCE MANUAL

3.2.3

Manual Operations
Keys and switches on the operator console have three functions: they permit the storing of

information in core memory; they permit the contents of a specified core memory cell to be displayed fOi'
visual examination; and they permit the starting and stopping of execution of a program.
Operation of the START, CONTINUE, EXAMINE/EXAMINE NEXT, DEPOSIT/DEPOSIT
NEXT, or READ-IN keys generates the KEY MANUAL level transition to start the special pulse generator. The special pulse generator produces five tim ing pulses, designated SPO through SP4, which
initiate all functions performed as part of a manual operation. All five keys cause the RUN fl ip-flop to
be cleared at time SPO in order to stop any operations already in progress.

(Note that although it is not

logical to press the START key when a program is running, it could be accidentally pressed and must
therefore be made to stop current operations.) After the clearing of the RUN fl ip-flop, there is a 10fJsec pause to allow the completion of any EAE operations in progress. Thereafter, the sequence of operations depends upon which key was operated.

3.2.3.1

START Key -The START key initiates execution ofa program previously loaded into memory.

After starting the special pulse generator and clearing the RUN fl ip-flop, the key causes the following
events to take place:
a. At time SP1, the memory address register (MA) is cleared in preparation for entering the
starting address of the program from the ADDRESS switches. A complete clear is required,
because only binary 1s are transferred to the MA.
b. At time SP1, a BGN pulse is generated which cl ears the instruction register (I R), the read
paper tape (RPT) and other special mode fl ip-flops, and establ ishes initial conditions in the
registers of I/O devices. The multistate device of the major state generator is forced into the
fetch state in preparation for extracting the first programmed instruction from memory, and the
program counter (PC) is cl eared.
c. At time SP2 , binary 1s of the starting address preset on the ADDRESS switches are transferred into t he PC.
d. At time SP3, the RUN flip-flop is set to the 1 state, thereby conditioning a NAND gate
between the spec ial pulse generator and the main timing chain. Timing pulse SP4 triggers
this gate and causes the main timing chain to generate timing pulse T1. Thereafter, the CP
operates under control of timing pulses generated by the main timing chain and successively
executes programmed instructions until the RUN fl ip-flop is set to the 0 state.

3-7

PDP-7 MAINTENANCE MANUAL

3.2.3.2

CONTINUE Key - The CONTINUE key causes the CP to continue execution of a program after

a temporary halt. Pressing the key clears the RUN fl ip-flop during SPO and the MA during SP1. Since a
halt may take place at the end of any memory cycle, the CP must continue with the type of cycle that was
predetermined by the cycle in which the halt was requested. Thus, the only further action required by the
CONTINUE key is to set the RUN fl ip-flop to 1 at time SP3 and to cause timing pulse SP4 to initiate
operation of the main tim ing chain. The CP then continues execution of the program from the point at
wh ich it was hal ted.

3.2.3.3

STOP Key -The STOP key provides a means of halting a program at the conclusion of a memory

cycle. Pressing the key conditions a gate triggered at time T5 of the memory cycle. The output pulse
produced by the gate clears the RUN fl ip-flop, thereby preventing timing pulse TP7 from reentering the
timing chain to initiate a new cycle. The CP, therefore, halts at the conclusion of the memory cycle
during which the RUN flip-flop was cleared.

3.2.3.4

DEPOSIT/DEPOSIT NEXT Key -The DEPOSIT/DEPOSIT NEXT key, when momentarily set to

DEPOSIT, causes a binary number that has been preset on the ACCUMULATOR switches to be deposited
in the memory cell specified by the ADDRESS switches. When momentarily set to DEPOSIT NEXT, the
key causes a binary number preset on the ACCUMULATOR switches to be deposited in the memory cell
specified by the PC. Setting the key to DEPOSIT clears the RUN fl ip-flop at time SPO and the MA at
time SP1. A memory cycle to perform the operation is then initiated as follows:
a. At time SP1, a BGN pulse is generated to clear special mode and I/O device flip-flops;
the PC is cleared; and the major state generator is forced to the execute state. (Refer to the
key function flow diagram on engineering logic diagram 3.)
b. At time SP2, the binary 1s contained in the ADDRESS switches are transferred to the PC.
Then the binary 1s contained in the ACCUMULATOR switches are transferred to the accumulator register (AC), and the operation code for DAC (deposit AC) is set into the IR.
c. At time SP3, the contents of the PC are transferred into the MB. This step is necessary
because after time SP4, the processor enters an execute cycle in which the contents of the
MB are transferred to the MA at time Tl. The fact that the status of the I ink, trap flag, and
extend mode are also set into the MB is of no importance in a deposit operation, because the
MA does not sample those bits of the MB.
d. At time SP4, the contents of the PC are incremented by 1 to fac iI itate a further manual
operation at the next location after completing the deposit operation. Timing pulse 5P4 then

3-8

PDP-7 MAINTENANCE MANUAL

starts the main tim ing chain.

Note that the RUN fl ip-flop remains in the 0 state, and conse-

quently the CP halts at the end of the execute cycl e.
e. At time T1 of the execute cycle, since this is not a CAL (call subroutine) instruction, the
contents of the MB are transferred to the MA (CP flow diagram, engineering logic diagram 4).

f. At time T3 of the execute cycle the contents of the AC are transferred to the MBi and during
the remaining portion of the cycle this data is written into the specified memory cell. Since the
RUN fI ip-flop is not set, the CP halts after time T7 and the deposit operation is compl ete.
Setting the key to DEPOSIT NEXT causes the CP to perform an operation that is almost identical
to a deposit operation. The difference is that the PC is not cleared at SP1, nor are the contents of the
ADDRESS switches set into the PC at time SP2. The number preset on the ACCUMULATOR switches is
therefore deposited in the memory cell spec ified by the PC instead of by the ADDRESS switches.

Note

that the contents of the PC are incremented at time SP4. Therefore, after an initial deposit operation,
use of the DEPOSIT NEXT position causes deposits to be made at consecutive memory locations without
resetting the ADDRESS switches.

3.2.3.5

EXAMINE/EXAMINE NEXT Key -The EXAMINE/EXAMINE NEXT key, when momentarily set

to EXAMINE, causes the contents of the memory cell specified by the ADDRESS switches to be transferred
to the MB and AC. When the transfer is complete, the associated indicator lamps display the contents of
the MB, MA, and AC. The MB and AC contain the contents of the specified memory cell; the MA contains the address preset on the ADDRESS switches; and the PC contains the address of the next consecutive
memory cell. Thus, a number of consecutive memory cells may be examined without resetting the ADDRESS switches between each operation. When momentarily set to EXAMINE NEXT, the key causes the
contents of the memory cell specified by the PC to be transferred to the AC for visual examination.
Setting the key to EXAMINE clears the RUN fl ip-flop during time state SPO and the MA at
time SP1. A memory cycle to perform the operation is initiated as follows:
a. At time SP1, a BGN pulse is generated to clear special mode and I/O device fl ip-flops;
the PC is cleared; and the major state generator is forced to the execute state. (Refer to the
key function flow diagram on engineering logic diagram 3.)
b. At time SP2, the address specified by the ADDRESS switches is transferred to the PC, and
the operation code for LAC (load AC) is set into the IR.
c. At time SP3, the contents of the PC are transferred to the MB. {This step is necessary for
the reason stated under 3.2.3.4 c.

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PDP-7 MAINTENANCE MANUAL

d. During time state SP4, the contents of the PC are incremented by 1, and timing pulse SP4
starts the main timing chain.
e. At time T1 of the execute cycle, since the instruction is not CAL, the address contained in
the MB is transferred to the MA, and the AC is cleared.

f. At time T3, the contents of the addressed memory cell are read into the MB, and an XOR
{exclusive OR} operation is performed on the MB and AC. Since the AC was previously
cleared, this results in a direct transfer of the contents of the MB into the AC, where they are
available for visual examination. Since the RUN flip-flop is not set, the CP halts at time T7,
and the EXAMINE operation is complete.
Setting the key to EXAMINE NEXT causes the CP to perform an operation almost identical to
an EXAMINE operation. The difference is that the PC is not cleared at time SP1, nor are the contents
of the ADDRESS switches set into the PC at time SP2. The word loaded into the AC for exam ination is
therefore brought from the cell specified by the PC instead of by the ADDRESS switches.

Note that the

contents of the PC are incremented at time SP4 to permit examination of consecutive locations without
resetting the ADDRESS switches.

3.2.3.6

REPEAT Switch - Turning on the REPEAT switch causes the CP to repeat the operation specified

by one of the manual keys, at intervals determined by the settin9-of the SPEED controls on the console
panel, for as long as the key is held down. After completing a DEPOSIT or EXAMINE operation, use of
the REPEAT switch in conjunction with a DEPOSIT NEXT or EXAMINE NEXT operation permits deposition
in, or examination of, successive memory cells without specifying each address. Turning on the REPEAT
switch causes timing pulse SP4 to trigger a one-shot which produces a delay, the length of which is adjustable by means of the coarse and fine SPEED controls on the operator console. When the one-shot
reverts to its stable state, the level transition appearing at the output terminal is appl ied to the special
pulse generator and initiates time state SPO once more. The CP then repeats the operation assoc iated
with the manual key that is pressed.

3.2.3.7

READ-IN Key -The READ-IN key permits information punched in binary fprmat on paper tape

to be loaded into memory at successive memory locations, starting at the address specified by the ADDRESS switches. When in the binary mode, tape holes 1 through 6 of each line of tape contain onethird of an 18-bit word; hole 7 is not punched until the last I ine of the last character that is to be read,
and hole 8 is always punched to cause the I ine to be read. When the READ-IN key is pressed, the
processor selects the reader in binary mode, then waits for the reader to read three I ines of tape and
assemble these in the reader buffer in the form of an 18-bit word {and also waits until the READ-IN key
is released}. When the reader buffer is full, its contents are transferred to the AC and then deposited
3-10

PDP-7 MAINTENANCE MANUAL

in memory. The process of reading three lines of tape, assembling the information into an 18-bit word,
and depositing words at consecutive memory locations continues until the reader encounters a line of
tape in which hole 7 is punched. The reader then stops, and the processor executes the last 18-bit word
read and deposited (hole 7 being in the last line of this word).
Pressing the READ-IN key causes the RUN fI ip-flop to be cleared at time SPO and the MA to
be cleared at time SP1. The following takes place:
a. At time SP1, a BGN pulse clears the special mode flip-flops, including the RPT (read
paper tape) fI ip-flop to establ ish initial conditions. The, PC is cleared, and the major state
generator is forced to the execute state.
,b. At time SP2, the address specified by the ADDRESS switches is set into the PC, and the
operation code for DAC is set into the I R.
c. At time SP3, the RPT fI ip-flop is set to' 1 •
d. At time SP4, the AC is cleared and the contents of the PC are transferred to the MB. At
this time a command is generated that selects the reader in binary mode and causes it to read
three I ines of tape successively into the reader buffer. When the reader buffer is full, the
reader flag is set to 1 •
e. ,The processor now waits for three conditions to be met:
(1) The RPT flip-flop is in the 1 state (this condition was fulfilled at time SP3).
(2) The reader flag is set to 1 (indicating that the reader buffer is full).
(3) The READ-IN key is released.

If the processor is not forced to wait for this condition

to be fulfilled, the rapid action of the reader may cause several words to be deposited at
the starting address, with consequent loss or inval idation of information.
The levels representing assertion of these three conditions are combined in a gate; whichever
of the three conditions is fulfilled last causes a level transition to occur at the output of the
gate. This transition starts the main timing chain and initiates a computer cycle in the execute state.

f. The events in the execute cycle follow the pattern already described for a deposit operation. However, the CP does not stop at time T7 because tim ing pulse TP7, combined with the
1 state of the RPT fI ip-flop, causes the generation of timing pulse SPO of a second readin operation • However, the RUN fl ip-flop is cl eared at time SPO.
g. At time SPl of a second (or subsequent) readin operation, no BGN pulse is generated,
because the READ-IN key has been released. Further, since the RPT fl ip-flop remains set,

3-11

PDP-7 MAINTENANCE MANUAL

the PC is not cleared at time SPl and the contents of the ADDR~SS switches are not transferred
to the PC at time SP2.

Instead, the contents of the PC are incremented by 1 at tirpe SP2.

Thus, lB-bit words transferred from the reader buffer to the AC are deposited at consecutive
memory locations.
h. When the reader encounters a line of tape which has hole 7 punched, the assertion level
produced by hole 7 causes the RPT fI ip-flop to be cleared and the RUN fl ip-flop to be set at
time T5.
i. At time T7, since the computer is in the execute state and the RUN fl ip-flop is set, timing
pulse TP7 forces the major state generator to the fetch state and restarts the main timing chain.
At time Tl of the ensuing fetch cycle, the contents of the PC are transferred to the MA.
Therefore, since at that time the PC co'ntained the memory address of the last word read from
paper tape, the processor executes that word. The word may be any instruction, but sensible
choices for the programmer would be either a HL T (halt) instruction al !owin9 manual control
of the program before starting or a JMP (jump) instruction providing entry to the start of the
program.

3.2.3.B

SINGLE INSTRUCTION Switch -The SINGLE INSTRUCTION switch, in combination with an

F SET level (" instruction done" situation), generates a RUN STOP signal that resets the RUN fl ip-flop
and halts the CP at the end of the current memory cycle. However, the F SET ("instruotion done") level
is generated only during the cycle that completes the execution of an instruction and does not appear
during a fetch or defer cycle which must be followed by an execute cycle. Thus, when the SINGLE INSTRUCTION switch is turned on, the CP halts after completing each instruction; and the next instruction
must be initiated by pressing the CONTINUE key. When the SINGLE STEP and SINGLE INSTRUCTION
switches are both turned on, the SINGLE STEP switch takes precedence; and the CP halts after each
memory cycl e •

3.2.4

Programmed Operations
The normal mode of PDP-7 operation is the execution qf programmed instr\Jctions. A program

interrupt (produced by peripheral equipment to transfer control of the CP from the main program to a subroutine),can modify programmed operation. A data break or a clock break can also temporarily interrupt
the main program.

During a data break, lasting one memory cycle, a high-speed peripheral device,

which has a 15-bit address register as well as an 18-bit data register, can transfer information to or from
memory.

During a clock break, also lasting one memory cycle, a real-time clock may add 1 to the con-

tents of memory location 7. If an overflow occurs, a program break is initiated; otherwise the main
program is resumed.

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PDP-7 MAINTENANCE MANUAL

When a program is to be executed, the starting address of the program is preset on the ADDRESS
switches, and the START key is momentarily pressed. The CP fetches the first instruction from the specified address and executes it, at the same time adding 1 to the contents of the PC. Succeeding instructions
are obtained from numerically consecutive memory locations, unless a JMP or JMS instruction changes
the contents of the PC so that instructions are obtained from another block of numerically consecutive
locations in a different section of memory.
Programm ing is simpl ified and memory space is conserved if the programmer arranges the instructions for an operation performed many times during the course of the program in the form of a subroutine. A subroutine is a group of instructions contained in a numerically consecutive block of memory
locations that do not form part of the main program sequence. These subroutines may be entered from any
part of the main program by means of a JMS (jump to subroutine) instruction which stores in memory the
location of the next main program instruction {that is, the contents of the PC}. The next instruction to
be executed is the first instruction of the subroutine. Exit from the subroutine and return to the main
program sequence is obtained by means of a JMP I {jump indirect} instruction, which directs the CP to
the locat ion containing the next main program instruction and effects the execution of the instruction
found in that location.
The instructions performed by the PDP-7 are of two kinds: memory reference instructions and
augmented instructions. A memory reference instruction contains an operation code in bits 0 through 3,
and the location in memory of the word upon which the operation is to be performed in bits 5 through 17.
If bit 4 is a 1, it is an indication that the address contained in the instruction word is not that of the
operand itself, but is the location containing the address of the operand. This facil ity is known as indirect addressing.

Indirect addressing has many uses; for example, it may be used with a jump instruction

to permit reentry into the main program from a subroutine; it permits a memory location outside the current
8K field to be addressed when the extend mode is enabled; and it permits a programmer to gain access to
an operand whose absolute address is determined by the program itself but known to be contained in a
spec ific memory location.
An augmented instruction requires no reference to memory. An operation code in bits 0 through
3 identifies the instruction as an OPR/LAW, lOT, or EAE instruction. The contents of the remain ing bits
specify operations which timing pulses T5, T6, and T7 perform during a single computer cycle. More
than one such microinstruction may be combined into a single instruction provided that there is no logical
confl ict between the operations spec ified.
The following paragraphs first describe the memory reference instructions and then the augmented instructions. The load accumulator {LAC} and operate {OPR} instructions are described in detail, as
representative of the memory reference instructions and augmented instructions, respectively. Remarks
on the remain ing instructions are confined to important points not obvious from the flow diagram. All
of the explanations assume that direct addressing is employed (bit 3 contains a O). An explanation of the
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PDP-7 MAINTENANCE MANUAL

use of the autoindexing locations and of the use of a defer cycle to permit indirect addressing follows the
descriptions of the memory reference instructions. The descriptions of both memory reference and augmented instructions also assume that no I/O device has requested a break of any kind. The conditions
under which a break may be granted and the events during the ensuing break cycle are described after
the explanation of the augmented instructions.

3.2.4.1

Memory Reference Instructions

TABLE 3-1
Mnemonic
Symbol

MEMORY REFERENCE INSTRUCTIONS

Octal
Code

Machine
Cycles

Operation
Executed

CAL

Call subroutine. The address portion of this instruction is
ignored. The action is identical to JMS 20.

DAC Y

Deposit AC. The contents of the AC are deposited in the
memory cell at location Y.

JMS Y

Jump to subroutine. The contents of the PC and the contents
of the L are deposited in memory cell Y. The next instruction is taken from cell Y + 1 •

DZMY

Deposit zero in memory cell Y.

LAC Y

Load AC. The contents of Yare loaded into the AC.

XORY

Exclusive OR. The exclusive OR is performed between the
contents of Y and the contents of the AC, with the result
left in the AC.

ADDY

Add (ls complement). The contents of Yare added to the
contents of the AC in 1s complement arithmetic and the
result is I eft in the AC.

TADY

1s complement add. The contents of Yare added to the
contents of the AC in 2s complement arithmetic and the
result is left in the AC.

XCT Y

Execute. The instruction in memory cell Y is executed.

ISZ Y

Increment and skip if zero. The contents of Yare incremented by one in 2s complement arithmetic. If the result is
zero, the next instruct ion is sk i pped .

ANDY

AN D. The logical operation AN D is performed between th~
contents of Y and the contents of the AC with the result left
in the AC.

3-14

PDP-7 MAINTENANCE MANUAL

TABLE 3-1
Mnemonic
Symbol

MEMORY REFERENCE INSTRUCT IONS (continued)

Octal
Code

Machine
Cycles

SAD Y

JMPY

Operation
Executed
Skip if AC is different from Y. The contents of Yare
compared with the contents of the AC. If the numbers are
different, the next instruction is skipped.
Jump to Y. The next instruction to be executed is taken
from memory cell Y.

a. Load Accumulator (LAC)
The LAC instruction is a memory reference instruction which requires a fetch and
and execute cycle. During the fetch cycle, the address of the LAC instruction is transferred
from the PC to the MA, and the contents of the PC are incremented by 1. A read operation
transfers the contents of the memory cell addressed into the MB, and bits 0 through 3 are transferred directly into the IR as the operation code of the instruction to be executed. The contents of the MB are then rewritten into the memory cell from wh ich they were read. Finally,
the major state generator is set to the execute state. During the execute cycle, the operand
is extracted from memory and loaded into the accumulator. The following detailed description
of the sequence is read while referring to the flow diagram and to the specified engineering
logic diagrams.
At time T1 of any fetch cycle, the instruction register must be cleared. The F level
is NAND combined with the T1 pulse (05,7); and the gate output, after ampl ification and inversion, is applied to the direct clear inputs of the four IR flip-flops.

(In a similar manner,

the IR is cleared at time T1 of a break cycle and at time T2 of certain execute cycles. The
IR is not cleared during a defer cycle.) Also at time T1, the F negative level is NAND combined with the T1 pulse (C7, 8) to produce a PC1 -MA pulse. This pulse is appl ied to a set
of MA input gates, opening those already conditioned by a negative level from a PC fl ip-f1op
in the 1 state.
Note that the PC1 -MA pulse is appl ied only to bits 5 through 17 of the MA register. Bits 3 and 4 of this register are used only in conjunction with memories of 16K capacity
or more and must receive a separate transfer pulse (EPC1 -EMA) from the memory extension
control unit. The F level and T1 pulse are also NAND combined in the PC control logic
(E6, 8) to produce a +1 -PC pulse which increments the contents of the PC by 1. The
+1

PC pulse complements bit 17 of the PC register (F8, 15), and is also applied to a

gated pulse ampl ifier.

If this gate is already conditioned by a PC17 (1) level, a carry pulse
3-15

PDP-7 MAINTENANCE MANUAL

complements bit 16. A series of gated pulse amplifiers propagates the carry toward bit 5
and stops when it first encounters a bit in the 0 state. The fl ip-flops have a control I ed internal delay so timed that the MA input gates open and close before the incrementing pulse
causes any flip-flop to change state.

It is this internal delay which permits the PC register

to be sampled and incremented by simultaneous pulses without transferring the incremented,
rather than the original, contents to the MA.
At time T2 of every computer cycle, the MB is cleared and a read operation is
prepared. Time pulse T2 is appl ied to an isolating gate (D3, 8), and the output of th~ gat~
causes a pulse amplifier to produce the 0 -PC pulse. The TP2 pulse sets the READ flipflops of the memory control (27) to 1 and is NAN D combined with the MA4 (0) level to
produce the TP2 . SEL 0, 1 pulse (C8, 10). Note that the MA4 bit is always 0 unless more
than 8K of memory capacity is in use. The memory control decodes the MA5 bit to produce
either a SEL 0 or a SEL 1 level used to select one of the two 4K memory stacks in the standard 8K field. The SEL level is combined with the 1 output of the READ flip-flops to produce an appropriate SEL • READ LEVEL, which is applied to memory. Paragraph 3.4discusses
in detail the action of the memory. The effect of the SEL and SEL . READ I evels is to
enable the half-select X and Y read circuits in memory. The TP2 • SEL 0, 1 pulse applied
to a delay network in memory produces a strobe pulse which goes to the sense ampl ifiers of
the memory. This strobe pulse clears the READ 2 fl ip-flop and returns to the main timing
chain as the STB RTN pulse, which initiates the generation of T3 and clears the READ 1
fl ip-flop.
When the strobe pulse occurs, the memory sense ampl ifiers compare the signal
level in the sense winding of each core plane with a reference level.

In planes where

coincident read currents have caused a core in the 1 state to change to the 0 state, the
sense signal is greater than the reference level; and the associated sense amplifiers ~SA)
produce standard negative pulses. These SA pulses are appl ied to the MB input gates and
set the corresponding MB fl ip-flops.

An MB STB IN H negative I evel generated in the MB

control normally enables the SA - MB input gates. Thus, the contents of the addressed
memory cell are transferred to the MB unless the control logic specifically inhibits the gates.
During a fetch cycle, when the MB is loaded with an instruction word consisting of an operation code and the address of the operand, the four most significant bits (which contain
the operation code) are transferred directly into the IR, as well as into the MB. The negative pulses from sense ampl ifiers SAO through SA3 are appl ied to IR input gates conditioned
by the fetch level (D7, 7), and set the I R fl ip-flops accordingly.

3-16

PDP-7 MAINTENANCE MANUAL

After the strobe pulse has occurred, the contents of the various registers are
as follows:
ADDRESS switches

Z (address of the first instruction, which in this
exampl e is LAC Y)

Z+ 1

MBO through MB3 contain octal 20 (=LAC)
MB4{O) (= no indirect address)
MB6 through MB17 contain Y (address of operand)

I RO through I R3 contain octal 20 (=LAC)
In the instruction register, the states of I RO{O) and I R1 (1 ) are decoded to produce

an IA1 level and an IA3 level. The states of IR2(0) and IR3(0) are decoded to produce IBO
level. The IA3 level, which identifies the instruction as a memory reference instruction, is
NAN D combined with the ex isting fetch (F) and MB4(0) levels (E1, 7) to establ ish a SET
level. This ground level conditions the DCD gate (D3, 7) associated with a pulse amplifier
which sets an execute (E) state into the major state generator at time T7. At the same time
the ground level disables input L of module L21 to prevent any break request from being
granted until the execution of the instruction.
At time T4, timing pulse TP4 sets the INH fl ip-flop of the memory control logic,
thus enabl ing the inhibit supply of the memory. At time T5, both WRITE fl ip-flops are also
set and, in conjunction with the SEL 0 level, established coincident writing currents through
the cores of memory cell Z. All cores of the addressed cell are driven by full-select write
currents. However, those in planes which correspond to MB bits containing a 0 are inhibited
from changing state by a half-select inhibit current in the read direction. Thus, the contents of the MB are written back into the cell from which they are read.
At time T6, timing pulse TP6 resets the WRITE 1, WRITE 2, and INH fl ip-flops,
and the writing operation is now complete. At time T7, timing pulse TP7 INVTD is applied
to the DCD gates of the major state generator (24) and, in combination with the E SET level
establ ished during T3, sets the execute (E) state. The RUN fI ip-flop is still S&t, and the RUN
(1) level is NAND combined with timing pulse T7 (C8, 8) to produce a 0 -MA pulse which

clears all the fl ip-flops of the MA. The RUN (1) level is also combined with a SLOW CYC
(not slow cycle) level to condition a DCD gate at the entry to the main timing chain (F1, 5).
The TP7 pulse (delayed 150 nsec) is combined with a STOP CP TC (not stop central processor timing chain) level signifying that the extended arithmetic element does not require an

3-17

PDP-7 MAINTENANCE MANUAL

interruption. The resulting pulse triggers the DCD gate and energizes a pulse ampl ifier
(F2, 5). The output of this pulse ampl ifier causes the generation of timing pulse TP1,
thereby initiating the second (execute) computer cycle.
At time T1 of the execute cycle, the absence of an lAO signal at terminal S of
module F5 (C1, 8) results in the production of a CAL (not CAL instruction) level. This
level is NAND combined in the MA control (C7, 8) with the T1 timing pulse and another
negative level resulting from the absence of a defer (D) level. The output of the NAND
gate is applied to a pulse amplifier which produces an MB1 -- MA pulse. This pulse opens
all MA input gates already conditioned by a negative level from an MB fI ip-flop in the 1
state; thus the address of cell Y (containing the operand) is set into bits 5 through 17 of the
MA. The (E) level of the major state generator is NAND combined with the 1A1 level produced by the IR, and the output of the gate is inverted to produce an E • IA1 level (F2,9).
The E • !A1 level is NAND combined with the IBO level and inverted to produce an

E • LAC level. The E • LAC level enables a NAND gate which is opened by time pulse
T1 to trigger a pulse ampl ifier in the AC control logic (C6, 9). This pulse ampl ifier produces a 0 -- AC pulse which clears all the fl ip-flops of the accumulator.
During the execute cycle, the contents of memory cell Yare read into the MB
and then rewritten into memory in exactly the same manner as for cell Z (during the fetch
cycle). Therefore, the following paragraphs describe only those events pecul iar to the
execute cycle. After the strobe occurs, the contents of the various registers are as follows:
PC

Z+l

Contents of cell Y

Octal 20 (= LAC)

AIIO's

At time T3 of the execute cycle, the E • 1A1 level is combined with the T3 timing
pulse. The resulting pulse is applied to pulse amplifier PA2 of module J2 in the AC control
logic, and the output of the pulse ampl ifier is an XOR -+AC pulse. This pulse is appl ied to
a set of accumulator register input gates normally used to complement the accumulator in an
exclusive OR operation. However, since the accumulator is cleared at time T1 (of the execute cycle), no carry pulses can be generated; and the effect is a simple transfer of memory
buffer l's into the corresponding bits of the accumulator.
After the operand has been rewritten into memory cell Y (starting at time T4)
the MA is cleared, and the interrupt control is interrogated to determine the state to be set
into the major state generator for the next cycle. If any I/O device has initiated a break
3-18

PDP-7 MAINTENANCE MANUAL

request, the interrupt control logic (14) establishes a negative BK RQ (break request) level
which is applied to terminal K of module K20 in the major state generator. Then, provided
that neither aD SET nor an E SET level has previously been establ ished by the nature of the
instruction, a B,~ET ground level appears at terminal N of the module. This level, in combination with timing pulse TP7 INVTD, sets the major state generator to the break (B) state
for servicin'g the I/O device. If there is no break request, the BK RQ combines with
D SET and E SET levels to produce an F SET level; and, at time T7, a new fetch cycle is
initiated to extract the next instruction from memory address Z+ 1. Note that a break request is never granted until the current instruction has been executed. Thus, a break can
be granted only after completion of a 1-cycle instruction, after the execute cycle of a
multicycle instruction, or after a break cycle to continue a block transfer or other operation involving sever~1 break cycles.

b. Exclusive OR (XOR)
The exclusive OR logical operation is performed between the contents of the AC
and the contents of the MB and requires a fetch cycle and an execute cycle.

During a

fetch cycle, the operation code 24 is set into the IR; and the address of the operand is set
into bits 5 through 17 of the MB. At time T1 of the execute cycle, the address of the operand is transferred from the MB to the MA. At time T2, the MB is cleared; and a read
operation sets the operand into bits 0 through 17 of the MB. The E negative level of the
major state generator is NAND combined in the AC control with the IA1 negative level
produced by the IR decoder. The resulting E • IA1 negative level is combined in the AC
control with timing pulse T3 to produce a negative XOR -AC pulse. This pulse opens AC
input gates already conditioned by MB bits in the 1 state and complements the associated
AC bits. When 'the AC has previously been cleared (as in the LAC instruction), the
XOR -+ AC com~and :can be used for a simple transfer of binary 1s from MB to AC.

1s Complement Add (ADD)
The ADD instruction adds the contents of the MB to the contents of the AC in

1s complement arithmetic and requires a fetch cycle and an execute cycle.

During the

fetch cycle, the operation code 30 is set into the IR; and the address of the operand is set
into bits 5 through 17 of the MB. At time T1 of the execute cycle, the address of the operand is transferred from the MB to the MA. At time T2, the MB is cleared, and a read
operation sets the operand into bits 0 through 17 of the MB. At time T3, the E • IA 1 negative level causes an XOR operation to be performed in the manner already described. In
3-19

PDP-7 MAINTENANCE MANUAL

the AC control, the E negative level is further combined with the IB2 level produced by the
IR decoder to produce an E • ADD level. The E . ADD level, in combination with timing
pulse T4, produces a negative AC CRY (accumulator carry) pulse. This carry pulse opens
accumulator input gates in which the state of each AC bit is compared with the state of the
corresponding MB bit and carries are propagated where necessary. A carry pulse generated
by bit ACO causes the generation of a negative END CRY (end carry) pulse. The END CRY
pulse is appl ied to the complementing input of the AC17 fl ip-flop; if this is already in the
1 state, further carries are propagated toward bit ACO.

d. 2s Complement Add (TAD)
The TAD instruct ion adds the contents of the MB to the contents of the AC in 2s
complement arithmetic and requires a fetch cycle and an execute cycle. During the fetch
cycle, the operation code 34 is set into the IR; and the address of the operand is set into
bits 5 through 17 of the MB. At time T1 of the execute cycle, the address of the operand
is transferred from the MB to the MA. At time T2 the MB is cleared, and a read operation
sets the operand into bits 0 through 17 of the MB. At times T3 and T4, XOR anq carry
operations are performed as described for the ADD instruction. At time T5 an overflow from
bit ACO causes generation of a TAD CRY (2s complement carry) pulse which sets the link

fI ip-flop to 1. The effect of the I ink depends upon what instruction follows; fQr e~ample,
it may be sensed by an augmented instruction to cause a skip.

e. Execute (XCT)
The XCT instruction causes the CP to execute the instruction contained in the
memory cell addressed. The instruction requires a fetch cycle plus the cycles required to
perform the instruction contained in the cell. During the fetch cycle of an SeT instruction, the operation code is set into the IR; and the address of the instruction to be performed is set into bits 5 through 17 of the MB. At time T1 of the execute cycle, the
address of the instruction is transferred from the MB to the MA. At time T2, the IR is
cleared, and a fetch state is forced. Between times T2 and T3, the contents of the
addressed memory cell are read into the MBi and the four most significant bits (containing
the operation code) are set into the IR. The CP then executes the instruction contained
in the cell addressed by the XCT instruction. Note that even if the subject instruction is
a memory reference instruction, the effective address of the operand is available without

3-20

PDP-7 MAINTENANCE MANUAL

reference to the PC, so that the program sequence is unaltered. In other words, the CP seems
to be performing the subject instruction in place of the SCT instruction, then proceeds to the
instruction following the XCT instruction.

f. Index and Skip if Zero (ISZ)
The ISZ instruction increments the contents of the addressed cell by 1, using 2s
complement arithmetic.

If the incremented number is 0, the next instruction is skipped. The

ISZ instruction requires a fetch cycle and an execute cycle. During the fetch cycle, the
operation code 44 is set into the IR; and the address of the operand is set into bits 5 through
17 of the MB. At time T1 of the execute cycle, the address of the operand is transferred from
the MB to the MA. Between times T2 and T3, a read operation sets the operand into the MB.
The E level derived from the major state generator is combined in the MB control with the
IA2 and IB1 levels produced by the JR decoder. The resulting E • ISZ level conditions a gate
which is opened by timing pulse TP3 to produce a +1 -MB negative pulse. This pulse complements the least significant bit of the MB and is also appl ied to the MB gates which propagate
carry pulses.

If the MB overflows (which can only happen when the contents of the MB be-

come 0), bit MBO generates a carry pulse which is combined in the PC control with the
E • I SZ level. As a result, a negative pulse is generated which increments the contents of
the PC by 1. Starting at time T4, the incremented contents of the MB are written back into
the memory cell addressed by the ISZ instruction. Note that at time T1 of the fetch cycle
the address of the I SZ instruction is set into the MA; and the contents of the PC are incremented in the normal manner. If the incremented contents of the MB are not 0 and therefore
produce no overflow at time T3 of the execute cycle, the next instruction is fetched and executed. An overflow from the MB, however, causes the contents of the PC to be incremented
again, so that the instruction immediately following I SZ in the program is skipped.

g. Logical AND (AND)
The logical AND operation is performed by a transfer of Os from the MB to the AC.
Thus, at the end of the operation, all bits of the AC have been cleared except those bits containing a 1 both in the AC and in the ~perand before the operation started. The AN D instruction requires a fetch cycle and an execute cycle. During the fetch cycle, operation code 50
is set into the IR; and the address of the operand is set into bits 5 through 17 of the MB.
During the execute cycle, the address of the operand is transferred from the MB to the MA at
time T1. Between times T2 and T3, the operand is read into the MB. The E level derived
from the major state generator is combined in the AC control with the IA2 and IB2 levels from
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PDP-7 MAINTENANCE MANUAL

the IR decoder to produce an E • AND level. This level conditions a NAND gate, which at
time T5 is triggered to produce an MBO- AC pulse. The MBO -+ AC pulse clears all AC bits
corresponding to MB bits which are in the 0 state. AC bits which are already in the 0 state
remain Os, regardless of the state of the corresponding MB bit. AC bits which are in the 1
state remain 1s only if they correspond to MB bits in th~ 1 state.

h. Skip if AC is Different from Operand (SAD)
The SAD instruction sets the operand into the MB and performs an XOR operation
between the MB and the AC. No carry pulses are pllopagated, so that if the initial contents
of the AC are identical to that of the MB, the end contents of the AC will be 0, and the
next instruction will be performed.

If any bit of the AC differs from the corresponding bit in

the MB, the next instruction is skipped.
The SAD instruction requires a fetch cycle and an execute cycle. During the fetch
cycle, the operation code 54 is set into the IR and the address of the operand is set into bits
5 through 17 of the MB. The contents of the PC are incremented in the normal manner. At
time T1 of the execute cycle, the address of the operand is transferred from the MB into the
MA and a read operation sets the operand itself into the MB.
The E level derived from the major state generator is combined in the AC control
with the IA2 and IB3 levels from the IR decoder to produce an E • SAD level. The E • SAD
level conditions a gate which is opened at time T3 to produce a negative XOR pulse. The
XOR pulse causes MB bits in the 1 state to complement the corresponding bits of the AC.
No carry pulses are propagated, so that if the initial contents of the AC are identical to that
of the MB, the resultant contents of the AC are aliOs. A 17-input AND gate in the AC control samples the status of all the AC fI ip-flops at time T5 and generates an AC=O I evel only
if all fl ip-flops are in the 0 state. The AC=O level is combined in the PC control with the
E • SAD level to generate a +1- PC pulse which increments the contents of the PC by 1 •
Thus, if the initial contents of the AC are identical to that of the operand, the next instruction is skipped.

If anyone AC fl ip-flop is in the 1 state after the XOR operation (indicating

that the contents of the AC are different from that of the operand), the AC=O level is not
produced by the AC control gate, and the +1 - PC pulse is not generated. The CP, therefore, proceeds to the next instruction and executes it. The XOR operation is repeated at
time T6 to restore the original contents of the AC.

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PDP-7 MAINTENANCE MANUAL

i. Deposit AC in Memory (DAC)
The DAC instruction deposits the contents of the AC in memory at the address
specified in the instruction. The instruction requires a fetch cycle and an execute cycle.
During the fetch cycle, the operation code 04 is set into the IR, and the address where the
contents of the AC are to be deposited is set into bits 5 through 17 of the MB. At time T1 of
the execute cycle, the address for the deposit is transferred from the MB to the MA. The E
level derived from the major state generator is combined in the MB control with the lAO and
IB1 levels from the IR decoder to produce an E • DAC level. This causes an AC1- MB pulse
to be generated at time T3. The AC1 -+ MB pulse opens the gates connecting the output of the
AC to the input of the MB. A write operation (starting at time T4) deposits the new contents
of the MB into memory at the address specified by the DAC instruction.

Note that although

read currents are appl ied to the addressed cell, the combination of the E and lAO I evels in
the MB control produces an MB STB INH (MB strobe inhibit) level that inhibits the gates
between the sense amplifiers and the input of the MB. Therefore, the original contents of the
addressed cell are not transferred into the MB, and are lost.

Note also that when a pseudo-

DAC instruction is used for loading information from perforated tape, the RPT(l) level causes
the generation of a SEL -+ RRB pulse at time T2, which transfers the contents of the reader buffer into the AC. For further details, refer to the description of the READ-IN key in section
3.2.3. At the end of a readin operation, the combination of the RPT(1) level and a reader
hole 7 signal clears the RPT fl ip-flop and sets the RUN fI ip-flop at time T5. The fetch state
is then establ ished for the execution of the next instruction. However, if the readin operation is to continue, the RPT(1) level causes the MB to be cleared at time T7 and starts the
spec ial pulse generator.

j. Deposit Zero in Memory (DZM)
The DZM instruction clears the memory cell at the address specified in the instruction and requires a fetch and an execute cycle.

During the fetch cycle, the operation code

14 is set into the I R; and the address for the deposit is set into bits 5 through 17 of the MB.
At time T1 of the execute cycle, the address for the deposit is transferred from the MB to the
MA. At time T2, the MB is cleared, and a read operation is initiated in the normal manner.
The E level derived from the major state generator is combined in the MB control with the lAO
level from the IR decoder, thereby inhibiting the gates between the memory sense ampl ifiers
and the MB.

Information previously stored in the addressed cell is read, but does not reach

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PDP-7 MAINTENANCE MANUAL

the MB and is lost. A normal write operation takes place, starting at time T4; but since the
MB is cleared, 0 is written into the addressed cell. At the end of the execute cycle, the fetch
state is establ ished in preparation for execution of the next instructfon.

k. Jump to Subroutine (JMS)
The JMS instruction permits exit from the main program into a subroutine and requires
a fetch and an execute cycle. During the fetch cycle, the operation code 10 is set into the
IR; and an address (Y) is set into bits 5 through 17 of the MB. At time T1 of the execute cycle,
address Y is transferred from the MB into the MA. At time T2, the MB is cl eared and the input gates are inhibited; so that the normal read operation destroys the original contents of cell

Y. At time T3, the current program count and the status of the I ink are transferred to the MBi
the PC is then cleared. This information is written into cell Y and is available there when
reentry into the main program is desired. At time T4, the address Y is transferred from the MA
to the PC; and at time T5, the contents of the PC are incremented by 1. The end contents of
the PC are Y+ 1, the address from which the first instruction of the subroutine is fetched.

I. Call Subroutine (CAL)
The CAL instruction is equivalent to the instruction JMS 20.

During the fetch cycle,

the operat ion code 00 is set into the I R; and the I R decoder produces lAO and !BO levels. These
are combined in the MB control with a B (not a break state) level to produce a CAL level. At
time T1 of the execute cycle, the CAL level is combined in the MA control with the E level
derived from the major state generator and generates a 20- MA pulse. This pulse sets octal
20 into the MA by setting fl ip-flop MA 13 to the 1 state. The 20 --+ MA pulse also sets fl ipflop IR2, thereby setting operation code 10(JMS) into the IR. Thereafter, the CP proceeds to
execute the JMS instruction, depositing the I ink status and current program count at memory
location 20 and taking the first instruction of the subroutine from memory location 21, as described in the explanation of the JMS instruction.

m. Jump (JMP)
The JMP instruction transfers control of the CP to a sequence of consecutive memory
locations that begin at the address specified in the instruction. The JMP instruction requires
only one cycle (fetch), during which the operation code 60 is set into the IRi and the memory
location from which the next instruction is to be taken is set into bits 5 through 17 of the MB.
The IA3 and IBO levels derived from the I R decoder are combined in the major state logic to
produce a JMP level which conditions two gates in the PC control. At time T5, one of these
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PDP-7 MAINTENANCE MANUAL

gates is triggered to produce a 0- PC pulse which clears the PC. At time T6, the second
gate is triggered to produce an MB1- PC pulse which transfers the address spec ified by the
JMP instruction into the PC. The major state generator is then set to fetch, and, during the
following cycle, the next instruction is fetched from that address.
n.

Indirect Addressing and Autoindexing
When bit 4 of a memory reference instruction contains a 1, the CP interprets the

contents of bits 5 through 17 as the memory location where the address of the operand may be
found. At time T7 of the fetch cycle, the major state generator is set to defer instead of to
execute. At time T1 of the defer cycl e, the contents of the MB are transferred to the MA
(unless the instruction is CAL). The MB is then cleared, and a read operation sets the contents of the addressed cell into the MB, wh ich now holds the effective address of the operand.
If this address is one of the eight autoindexing locations 1° through 17 , decoding gates in
8
8
the MA generate a pulse which increments the contents of the MB by 1 at time T3. If the

instruction containing the indirect address was a JMP instruction, the PC is cleared at time
T5; the effective address of the next instruction is transferred from MB to PC at time T6; and
the major state generator is set to fetch at time T7. If the instruction was not a JMP, no
action occurs at times T4 through T6. The major state generator is set to execute at time T7.
At time T1 of the execute cycle, the effective address of the operand is transferred from MB
to PC. The machine then performs the operation spec ified by the instruction upon the operand
contained in the indirectly addressed cell.
The eight auto-index locations may contain either the effective address of an operand or an instruction, depending on the program requirements. When used as direct addresses,
they are identical to other memory locations. When used as indirect addresses, however, their
contents are incremented by 1 each time they are addressed. Thus, use of the autoindexing
locations facilitates the repetition of an arithmetic process on a series of numbers without performing separate arithmetic operations on the addresses concerned. The PDP-7 User Handbook
explains the uses of the autoindex locations from the programmer's viewpoint.

3.. 2.4.2

Augmented Instructions - The augmented instructions are of three groups: EAE instructions with

the OP code 64, which are discussed in chapter 4; lOT instructions with the OP code 70 which are discussed in the PDP-7 Interface and Installation Manual, F78A; and the OPR instructions with the OP code 74.
A II three augmented instruction groups can be microprogrammed to perform severa I non-confl icting operations in a single instruction. See table 3-2 for the OPR instructions.

3-25

PDP-7 MAINTENANCE MANUAL

TABLE 3-2

OPR INSTRUCT IONS

Mnemonic
Symbol

Octal
Code

OPR or
NOP

740000

CMA

740001

Complement accumulator.
plemented.

CML

740002

Complement I ink.

OAS

740004

Inclusive OR ACCUMULATOR switches.
The word set into the ACCUMULATOR switches is
OR combined with the contents of the ACi the result
remains in the AC.

RAL

74001 0

Rotate accumulator left. The contents of the AC and
L are rotated one position to the left.

RLR

740020

Rotate accumulator right. The contents of the AC and
L are rotated one position to the right.

HLT

740040

Halt. The program is stopped at the concl usion of the
cycle.

SMA

740100

Skip on minus accumulator. If the contents of the
AC are negative (2s complement), the next instruction is skipped.

SZA

740200

Skip on zero accumulator. If the contents of the AC
equal zero (2s complement), the next instruction is
skipped.

SNL

740400

Skip o~ non-zero I ink. If the '. rontains a 1, the
next instruction is sk ipped.

SKP

741000

Skip. The next instruction is unconditionally skipped.

SPA

741100

Sk ip on positive accumulator. If the contents of the
AC are zero (2s compl ement) or a positive number, the
next instruction is skipped.

SNA

741200

Skip on non-zero accumulator. If the contents of the
AC are not zero (2s complement), the next instruction
is sk ipped.

SZL

741400

Skip on zero I ink. If the L contains a 0" the next instruction is skipped.

RTL

742010

Event
Time

Operation
Executed
Operate group or no operation. Causes a 1-cycl e
program delay.

2,3

Each bit of the AC is com-

Rotate two I eft. The contents of the AC and the L are
rotated two pos it ions to the I eft.

------------------

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PDP-7 MAINTENANCE MANUAL

TABLE 3-2

OPR INSTRUCTIONS (continued)

Mnemonic
Symbol

Octal
Code

Event
Time

RTR

742020

2,3

Rotate two right. The contents of the AC and the L
are rotated two positions to the right.

CLL

744000

Clear link. The L is cleared.

STL

744002

2,3

Set link. TheLissetto1.

RCL

744010

2,3

Clear link, then rotate left. The L is cleared; then
the Land AC are rotated one position left.

RCR

744020

2,3

Clear link, then rotate right. The L is cleared; then
the Land AC are rotated one position right.

CLA

750000

Clear accumulator. Each bit of the AC is cleared.

CLC

750001

2,3

Clear and complement accumulator. Each bit of the
AC is set to contain a 1 .

LAS

750004

2,3

Load accumulator from switches. The word set into
the ACCUMULATOR switches is loaded into the AC.

GLK

750010

2,3

Get I ink. The contents of L are set into AC17.

LAW N

76XXXX

Operation
Executed

Load the AC with LAW N.

a. Operate (OPR)
The bit assignment of an OPR instruction is shown in figure 3-1.

It is seen that bit

5 is used in one instruction only, i.e., clear accumulator (CLA) for which the octal code is
750000. All other instructions of the OPR class have octal codes beginning with 74. The
functions performed at times T1 through T4 of an operate instruction are exactly the same for
those which occur in the fetch cycle of any other kind of instruction. The IA3 and IB3 levels
from the IR decoder are combined in the AC control with the MB4(0) level to produce the OPR
level. This level conditions two gates: one is triggered at time T5 to perform one set of operations and the other gate is triggered at time T7 to perform the second set of operations. The
first set of commands consists of the following:
(1) If bit 5 is a 1, the AC is cleared.
(2) If bit 6 is a 1, the link is cleared.

3-27

PDP-7 MAINTENANCE MANUAL

(3) If bits 7 and 13 are 1s, the AC is rotated one place right (and will be rotated
again during time T7).
(4) If bits 7 and 14 are 1s, the AC is rotated one place left (and will be rotated
again during time T7).
(5) If bit 12 is a 1, the RUN flip-flop is cleared and the program is halted at the
conclusion of the current memory cycle.
(6) If bit 8 is a 0, anyone of the following conditions increments the contents of the
PC to skip the next instruction: I ink is not 0 {bit 9 is a l)i AC is not 0 {bit lOis a
l)i AC is negative (bit 11 is a 1).
The second set consists of the following operations which take place in time T7:
(1) If bit 13 is a 1, the AC is rotated one place right.
(2) If bit 14 is a 1, the AC is rotated one pi ace I eft.
(3) If bit 15 is a 1, the contents of the accumulator switch register are inclusively
OR combined with the contents of the AC.
(4) If bit 16 is a 1, the I ink is complemented.
(5) If bit 17 is a 1, the AC is compl emented .
Note that because of the nature of the rotate operations, a rotate operation may not
be combined with any other operation of the same set. For example, a single instruction may
clear the I ink (first set) and rotate the AC one place {second set)i but a 2-place rotation (both
sets) precludes the instruction from performing any other operation.

b. Law (LAW)
The LAW instruction is a special case of an operate class instruction and has the
operation code 76. The I R decoder produces IA3 and IB3 levels which are combined in the
AC control with the MB4(1) level to produce an OP LAW level. This level conditions two AC
control gates: one is triggered at time T5 to clear the AC and the other at time T6 to perform
an XOR operation between MB and AC. This effectively places the entire instruction in the
AC. Thus, an address-sized number (15 bits), preceded by the operation code, can be loaded
into the AC without using an extra memory location. The various uses of the LAW instruction
are described from the programmer1s viewpoint in the PDP-7 User Handbook.

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PDP-7 MAINTENANCE MANUAL

c. Input/Output Transfer (lOT)
lOT instructions are au~mented instructions which can be microprogrammed to address
an I/O device and to generate up to three time pulses to initiate and control the operation of
the device. When an lOT instruction is executed, if bit 14 is a 1, the AC is cl eared at time
T5; if bit 17 is a 1, an IOP1 pulse is also generated at this time.

If bit 16 is a 1, an IOP2 pulse

is generated at time T7. If bit 15 is a 1, an IOP3 pulse is generated at time T1 of the following
cycle.

3.2.4.3

Break Cycle ~ A break cycle provides a temporary interruption of the main program during which

information may be transferred to or from a high-speed peripheral device or a subroutine may be initiated
to service a slow peripheral device. Reference to the flow diagram (4) shows that a break cycle may be
entered under the following conditions (which indicate an II instruction done" situation):

a. After the fetch cycle of an OPR, LAW, lOT, or directly addressed JMP instruction.
b. After the defer cycle of an indirectly addressed JMP instruction.
c. After the execute cycle of a directly or indirectly addressed memory reference instruction.
d. After a break cycle to continue a block transfer or other operation involving several break
cycles.

When a break request from peripheral equipment is granted, one of three possible sequences
takes place during the break cycle. If two or more break requests appear simultaneously, break sequences
are granted in the following descending order of priority: data break, clock break, and program break.

a•

Data Break
A data break may be granted to a high-speed I/O device containing registers which

can simultaneously supply or accept a 15-bit address word, an 18-bit data word, a break request
signal, and a direction-of-transfer signal. When a data break is granted, the IR is cleared;
and the address specified by the I/O device is set into the MA at time T1 of the break cycle.

If the I/O device spec ifies an outward transfer, the contents of the addressed memory cell are
read into the MB between times T2 and T3 and are available there for sampling by the input
register of the I/O device.

If an inward transfer is spec ified, the gates between the sense amp-

I ifiers and the MB are inhibited. As a result, any information contained in the cell is destroyed,
and the cell is cleared. At time T3 of the break cycle, the input gates linking the MB directly
to the output register of the I/O device are triggered, and the incoming data is set into the MB.
3-29

PDP-7 MAINTENANCE MANUAL

A normal write operation, starting at time T4, writes the data into the memory cell. Use of
the Type 173 Data Interrupt Multiplexer permits up to four high-speed VO devices to share
the data interrupt channel. (Refer to chapter 4 for further details.) After compl etion of the
high-speed transfer, a fetch state is establ ished for continuation of the program, unl ess a further
break request exists.

In this case, another break cycle follows.

b. Clock Break
A real-time clock, which can be enabled or disabled under program control by the
appropriate lOT instruction, is included in each PDP-7 system. When the clock is enabled,
each clock pulse initiates a break request. When the break is granted, the IR is cleared at
time T1 of the break cycle. The clock address 78 is set into the MA and the clock count request fl ip-flop is cleared. Between times T2 and T3 the contents of memory location 78 (the
clock count) are read into the MB and at time T3 the contents of the MB are incremented by 1 r
A normal write operation, starting at time T4, deposits the incremented clock count in memory
location 7 , If incrementing the MB does not cause an overflow, a fetch state is establ ished
8
at time T7 to continue the main program {unless there is a further break request}. If increm~nt
ing the clock count causes the MB to overflow, a carry pulse is generated by bit MBO. This
carry pulse sets the clock flag to 1, thereby initiating a program break. Possible programming
uses of the real-time clock are described in the PDP-7 User Handbook.
Note that when the automatic priority interrupt (API) option is included in the PDP7 system, the real-time clock is removed and the API is connected in its place. The real-time
clock may then use one of the API channels. For further details of the API, refer to chapter 4.

c • Program Break
Slow I/O devices, such as the Teletype or paper tape reader, require an interval of
several mill iseconds between the time one information transfer is performed and the time when
the device is ready for the next transfer. During this interval, the PDP-7 can perform mQny
hundreds of programmed instructions. When programmed instructions enable one or more such
devices, the program break fac il ity perm its the CP to continue execution of the main program
until such time as a device indicates, by setting its flag, that it is ready to send or receive
information. The setting of any device flag generates a program break request, and at the
first II instruction done" situation the CP enters a break cycle in which the address of the next
main program instruction, together with the status of the I ink, trap flag, and extend mode are
stored at location O. Control of the processor is then transferred to a subroutine starting in
location 1, which scans all the device flags to discover which device caused the interrupt.
3-30

PDP-7 MAINTENANCE MANUAL

Identification of the interrupting device may provide entry to a further subroutine for servicing
the device.· At the conclusion of the servicing subroutine, the main program may be reentered
by a jump indirect to location 0, which transfers program control to the address stored at location O.
A program break is granted when all of the following conditions are fulfilled:

(1) The program interrupt facility is previously enabled by a programmed ION
instruct ion.
(2) The setting of a device flag has generated a program break request.
(3) There is no data break in progress or waiting.
(4) There is no clock (or API) break in progress or waiting.
(5) There is no program break in progress.

At time T1 of the break cycle the IR is cleared, and at time T2 and MB is cleared.
The memory generates read currents which clear location 0, but the MB input gates
are inhibited so that any information previously contained in that location is destroyed. At
time T3 the I ink status is set into bit MBO, the extend mode status into bit MB1, and the trap
flag status bit into MB2. The contents of bits PC3 through PC17 are transferred to the corresponding bits of the MB and the PC is cleared. At time T4, the contents of the MA are transferred to the PCi note, however, that the MA is cleared at time T7 of the previous cycle and
is not reloaded, so its contents are still O. Also at time T4 a normal write operation is begun
which deposits the contents of the MB in memory at location O. At time T5, the contents of
the PC are incremented by 1, so that the next instruction is taken from location 1 in which a
subroutine starts. The program interrupt enable fl ip-flop is cleared to prevent any other program 'breaks until the interrupt is enabled by a programmed instruction at the conclusion of subroutine operations. Note, however, that data breaks and clock (or API) breaks may still be
granted.

If the program is operating in the trap mode and the program break is in itiated by the

trapping of an illegal instruction, the contents of the PC are again incremented by 1 at time
T5. Thus, control of the CP is transferred to a subroutine starting in memory location 2 in order
to identify the trapped instruction and take appropriate action.

If no data break or clock break

request is originated during the break cycle, a fetch state is establ ished at time T7 and the first
subroutine instruction is fetched during the ensuing fetch cycle.

If a data or clock break re-

quest exists, a further break cycle is granted before the subroutine is entered.

3-31

PDP-7 MAINTENANCE MANUAL

3.2.4.4

Trap Mode - When the PDP-7 forms part of a real-time or multiuser system, the trap mode

permits the use of sophisticated programming in the main program and guarantees this against interference
from other users operating in a different section of memory. When the main program is operating in real
time, it is particularly important to ensure that the processor cannot be halted, involved in lengthy operations, or thrown into a loop from which it cannot escape. The I/O trap provides the basic hardware necessary to provide protection against such disturbances.
When the trap mode is enabled by turn ing on the TRAP switch and by a programmed ITON (I/O
trap on) instruction, the following illegal instructions are trapped: all lOT instructions, all HLT {halt} instructions, and all XCT {execute} instructions. When an illegal instruction is detected, the trap flag is
set thereby preventing execution of the instruction.

Instead, a program break request is initiated. When

the break is granted, control of the CP is transferred to a subroutine starting at memory location 2, which
initiates procedures for identifying the trapped instruction and for taking appropriate action. The reason
for trapping lOT halt instructions is to prevent stopping the sequence at an undefined portion of the program. XCT instructions are trapped because if the subject instruction is also an XCT, a loop situation may
arise in which the CP never encounters an II instruction done II situation, so that all control is lost.

3.3

PROCESSOR
This section describes in detail the logic elements which perform the logic functions described

in 3.2. Descriptions of registers consider the effect of the various control signals applied; descriptions of
control elements consider the output signals and explain the conditions under which each of these is generated. Many types of FL IP CH IP modul es consist of a number of sim ilar components (e. g., Type W607 contains three identical pulse ampl ifiers).

Where necessary the individual components of a module are

identified by their input and output terminal letters (e.g., NOR gate NPR of module J5).

In addition,

references to the zone of the engineering drawing in which the component is located aid in identification
of a particular component.
All logic circuit elements of the processor appear on the block diagram of figure 3-2. These
elements consist of the major registers and their associated control elements, the timing generators for the
computer system, the manual controls, and the special program feature controls (data break control, program interrupt control, I/O skip, I/O trap, etc.).

3.3. 1

Registers

3.3.1.1

Accumulator - The AC is the major arithmetic register of the CP and is involved in most of the

mathematical, logical, and I/O transfer operations performed by the computer. This register consists of
18 Type B210 Accumulator FLIP CHIP modules at locations HJ2 through HJ19. The AC has a storage

3-32

PDP-7 MAINTENANCE MANUAL

ADDRESS

FROM INPUT/OUTPUT EQUIPMENT
USING DATA BREAK TRANSFERS

MA
CONTROL

t-A_DD_R_E_SS-l" ~~,;g~~

MEMORY
ADDRESS
REGISTER

FROM INPUT/OUTPUT EQUIPMENT
USING PROGRAMMED STATUS
CHECKS

TO DEVICE SELECTOR OF INTERFACE

FROM INPUT/OUTPUT EQUIPMENT
VIA THE INFORMATION COLLECTOR
OF THE INTERFACE

TO INPUT/OUTPUT EQUIPMENT VIA
THE INFORMATION DISTRIBUTOR OF
THE INTERFACE
MEMORY
BUFFER
REGISTER

~______- .____________________
D_AT_A__~•• ~g:~~~y

FOR INPUT/OUTPUT EQUIPMENT
USI NG DATA BREAK TRANSFERS
IB
MB
CONTROL

CLEAR AC
DIRECT CONNECTION AVAILABLE FOR ANY

1~~~~~Vr~18~~P~FE~JT~~F~g~

III MINOR STATES (INSTRUCTION STATES)

... MAJOR STATES (F,D,E,B)

OIl

ADDRESS ACCEPTED

DIRECT CONNECTION AVAILABl£ FOR

OIl DATA ACCEPTED

INPUT/OUJ:¥1 i~~~RNfN~~~~~

.. DATA READY

---------.
BREAK

1~~~~~e~T ....--_RE_QUE:..-:.;..S_T--J

TRANSFER DIRECTION

DATA BREAK

REQUEST~__________-IW

SYNC_

PROGRAM
INTERRUPT REQUEST

DIRECT CONNECTION AVAILABLE FOR
ANY INPUT/OUTPUT EQUIPMENT

POWER
CLEAR PULSE

SPECIAL PULSES
(SPO, 1,2,3,4)
TIMING PULSES
(TI THROUGH T7)
REQUEST
SLOW CYCLE

Figure 3-2

Processor Detailed Block Diagram
3-33

PDP-7 MAINTENANCE MANUAL

capacity of 18 bits. In programmed operation each flip-flop of the AC can be individually set or cleared
by means of gated signals from other registers or from external equipment. The fI ip-flops can also be set
(but not cleared) by means of the ACCUMULATOR switches on the operator console. The AC may also be
cleared collectively, or its contents incremented by 1, complemented, rotated, or shifted right or left.
An indicator on the operator console shows the status of each fl ip-flop in the register.
Each Type B210 module is a double-height module containing one buffered-output flip-flop, a
carry pulse amplifier, and all the required transistor gating elements. A positive pulse from a gating circuit sets or cleares the fl ip flop; the gates are conditioned by negative levels and are triggered by negative
pulses.
All bits of the accumulator are cleared collectively by a 0- AC pulse applied to input terminal
HV of a transistor gate connected to the direct clear input (HS) of the fl ip-flop.
Each bit of the AC may be individually set by a positive pulse from the information collector
applied to terminal HU, which is connected to the direct set terminal (HT) of the flip-flop. An unused
transistor gate permits a bit to be set by application of a negative pulse to terminal JL.
A pair of transistor gates to which the RAR pulse is appl ied, (at terminals HJ and HN), rotate
right operations. These gates set or clear the associated fI ip-flop according to the status of the adjacent
flip-flop of greater significance. The (1) level of this flip-flop is applied to terminal HH, and the (0)
level to terminal HM.
A similar pair of gates to which the RAL pulse is applied, (at terminals HL and HR), rotate left
operations. The (1) level (terminal HK) and the (0) level (terminal HP) of the adjacent flip-flop of less
significance condition these gates.
Each bit of the AC may be cleared by a 0 in the corresponding bit of the MB. The MB (0)
level is applied to terminal JH and clears the AC flip-flop when an MBO- AC pulse is applied to terminal

JF.
Each bit of the AC may be set by a 1 in the corresponding bit of the accumulator switch register. The (1) level from the corresponding ACCUMULATOR switch is applied to terminal JK, and the ACS1
pulse to terminal JJ.
Complementing is accompl ished by applying a positive pulse to both the direct set and direct
clear inputs of the fl ip-flop, through isolating diodes. Complementing is performed by anyone of the
following:
a. A negative C -+ AC pulse is applied to terminal JT; a transistor inverts the pulse.
b. A positive pulse from the XOR NAND gate; this gate is conditioned by an MB (1) level
applied to terminal JV, and is triggered by a negative XOR- AC pulse applied to terminal
JU. The output of the gate complements the AC flip-flop.

3-34

PDP-7 MAINTENANCE MANUAL

c. By a carry pulse from the adjacent AC bit of less significance. The negative carry pulse
is applied to terminal JP and is inverted by a transistor.

Carry pulses propagate to the adjacent bit of greater significance as they develop at the type
B210 Pulse Ampl ifiers. A carry from bit ACx to bit ACx-1 is generated under the following conditions:

a. When bit ACx contains a 1, and a carry pulse is received from bit ACx+1. The negative
ACx{l) level conditions terminal FD of a NAND gate; the incoming carry complements bit
ACx and triggers the NAND gate. The output of the gate triggers the carry pulse ampl ifier
which transmits a carry pulse to bit ACx-1.
b. During an ADD or TAD instruction, an XOR operation is first performed between the MB
and the AC. After the XOR operation, an AC CRY pulse is appl ied to all bits of the AC at
terminal FR of a NAND gate.

If the level inputs of this gate are conditioned by an MBx{l)

level appl ied to terminal FV and an ACx{O) level appl ied to terminal FE, the AC CRY pulse
causes the gate to trigger the carry pulse ampl ifier and a carry is transm itted to bit ACx-1 •
The resulting changes of state in fl ip-flops of greater significance may result in additional
carries being propagated as described in c. (above).

3.3. 1 .2 ' Link - The Link (L) is an extension of the AC and is used for data overflow. The I ink consists
of a single Type B210 Accumulator module. Storage capacity is a single bit. The link is capable of the
same functions as the AC and can be operated independently of, or in conjunction with, the AC.

indicator on the operator consol e shows the status of the I ink.
Anyone of the following conditions clears the I ink:

a. A BGN pulse at time SP1 of any key operation.
b. A microprogrammed rotate right command, if bit AC17 is O.
c. A microprogrammed rotate left command, if bit ACO is O.
d. A microprogrammed clear link command (bit MB6 is 1) at time T5 of the computer cycle.

Anyone of the following conditions sets the I ink:

a. An EAE SET L pulse originating in the extended arithmetic element.
b. A microprogrammed rotate right command, if bit AC17 is 1 •
3-35

PDP-7 MAINTENANCE MANUAL

c. A rotate left command, if bit ACO is 1 .
d. Timing pulse TP1 of the computer cycle, if the AC overflowed during the previous cycle.

The I ink is complemented:

a. By an ACO CRY {overflow} during a EAE multiply or divide operation.
b. By a TAD CRY pulse generated by an AC overflow during 2s complement addition; by a
microprogrammed complement link command in an operate instruction; or by a complement
I ink command originating in the EAE.

3.3.1.3

Program Counter - The PC determines the core memory address from which the next instruction

is fetched. This register consists of 15 Type B201 FI ip-Flops at locations F18 through F32 and 7 Type
B620 Carry Pulse Ampl ifiers at locations 1 H21 through 1H27. The PC has a storage capac ity of 15 bits.
In normal {nonextended} operations, only 13 of these are used. The 13 flip-flops containing the~e 13
least significant bits can be individually set either by gated signals in automatic operation or by the ADDRESS switches in manual operation. The PC can only be cleared collectively. The inclusion of complementing gates and carry pulse ampl ifiers permits the contents of the PC to be incremented by 1 injected into the least significant bit. An indicator on the operator console shows the status of each flip-flop.

3.3.1.4

Memory Address Register - The {MA} contains the address of the core memory cell currently

selected for reading or writing. This register consists of 15 Type B201 FI ip-Flops at locations C18 through
C32, and has a storage capacity of 15 bits. Each fl ip-flop of the MA can be individually set by gated
signals from other registers but can only be cleared collectively. An indicator on the operator console
shows the status of each fl ip-flop.

3.3.1.5

Memory Buffer Register - The {MB} serves as a data buffer between the processor and the

core memory. This register consists of 18 Type B201 FI ip-Flops at locations E2 through E19 and 9 Type
B620 Carry Pulse Ampl ifiers at even-numbered locations 102 through 1018, and has a storage capacity
of 18 bits. The register fI ip-flops can be individually set by gated si9nals but can only be cleared collectively. The circuits of the MB are similar to that of the MA with the addition of the pulse amplifiers
and complementing gates which allow the contents of the MB to be incremented by 1, injected into the
Ieast significant bit. An indicator on the operator console shows the status of each fl ip-f1op.

3-36

PDP-7 MAINTENANCE MANUAL

3.3.1.6

Major State Generator - Four NAND gates compose the multistate device whkh generates

the four major state levels: a Type Bl15 FLIP CHIP module at location K18 contains three, and another
similar module at location L17 contains the fourth. When disabled, each NAND gate produces a negative
level at its output terminal; when fully enabled by three negative levels, the gate produces a ground
output level. The gates are so interconnected that the output signal of each gate is appl ied to one input
term inal of each of the other three gates. Thus, if the fetch produces a ground output, this signal disables the other three gates, so that each produces a negative output. These three negative output signals
are returned to the input terminals of the fetch gate to maintain it in the fully enabled state. If a positive
pulse is now appl ied to the output of the execute gate, this pulse keeps the defer and break gates disabled,
but also disables the fetch gate. Terminals F and E of the execute gate remain enabled by the negative

I evels from the defer and break gates, but term inal D makes a transition from ground to -3v when the
fetch gate is disabled. The execute gate is now enabled by three negative input levels, so that its
ground output level is maintained after the setting pulse is ended. Two Type R602 FLIP CHIP modules in
locations L18 and K19 provide setting pulses for the multistate device. Each module contains two pulse
ampl ifiers, which produce a standard positive 100-nsec pulse. Each pulse ampl ifier is provided with two
DCD gates enabled by the combination of a ground level and a positive pulse. In principle, any state
can be entered from any other state; however, the major state gating makes certain necessary modifications to this principle.
During the execution of programmed instructions, the conditions establ ished during any given
cye! e determ ine the major state for the next cycl e. At time T7, those conditions are impl emented by
combining an F SET, D SET, E SET, or B SET level with timing pulse TP7 to produce a pulse that sets the
multistate device. However, when starting a program or performing a manual operation, other means may
establ ish a fetch or execute state under one of the following sets of conditions:

a. When the START key is depressed, the positive START level generated by the key circuits
is combined with timing pulse SP1 of the key cycle. The resulting pulse triggers pulse ampl ifier PAl in module L18 setting the multistate device to the fetch state.
b. A PIl - MA pulse, inverted in module L30, triggers pulse ampl ifier PA2 of module L19 and
establ ishes a fetc h state.
c. When a program is running in the trap mode, and an illegal XCT instruction is trapped, a
positive TRAP FLAG (O) level (produced only when the TRAP FLAG fl ip-flop is set) is combined
with the XCT CY (1) signal. This establishes a fetch state immediately, to avoid implementing
the illegal instruction.

3-37

PDP-7 MAINTENANCE MANUAL

During normal operation, an F SET level is combined in a DCD gate with timing pulse

TP7 INVTD B; and the resulting output of the gate triggers pulse ampl ifier PAl of module L18
to establ ish a fetch state.

The positive F SET level is generated by a NAND gate in module L2l and appears at output
terminal H of the gate. When negative D SET, E SET, and BK RQ levels enable all three inputs, the
ground F SET level appears at the output. An F SET NEG level is produced at terminals of module K22.
The D SET level indicates that the current instruction does not contain an indirect address which requires
a defer cycle to follow the fetch. The E SET level indicates that the current cycle is not a defer cycle
which requires an execute cycle to follow it. The BK RQ level indicates that no I/O device needs
servic ing.
An execute state is establ ished under the following conditions:

a. When any operation key other than the START key is depressed, a negative START level
derived from the key circuits enables a NAND gate in module L22 (B3, 24). When the BGN
pulse of the key cycle is added, the gate triggers pulse ampl ifier PA2 of module L18 and establ ishes the execute state.
b. During programmed operation, an E SET level conditions one input of a DeD gate; and
timing pulse TP7 INVTD causes the gate to trigger the associated pulse ampl ifier and establ ish
the execute state.
c. When a positive FORCE E SET pulse is generated during execution of certain EAE instructions.

One of three NAND gates located in modules L21, K20 and M19 generates the ground E SET
level which appears at terminal K20U if all of the following conditions are met: the current cycle is
operating in the fetch state; the operation code stored in the I R produces an IA3 level {indicating that
the instruction is not a single-cycle law, operate, or lOT instruction}; and bit MB4 is 0 {indicating that
the instruction contains the direct address of the operand}. The ground E SET level appears at terminal
J21 F if the current cycl e is operating in the defer state and the operation code produces an IA3 level.
The ground E SET I evel appears at term inal M 19R if the RPT fl ip-flop is set (during a readin operation).
A defer state is establ ished during the fetch cycle of any memory reference instruction or
JMP instruction which contains a 1 in bit 4. The negative F level and MB4{1} levels are combined in
NAND gate JKL of module L21, and the output of the gate is inverted in inverter PRS of module L20.
The output of this inverter and the output of NOR gate NPR of module L21 are both appl ied to inverter

3-38

PDP-7 MAINTENANCE MANUAL

TUV in module L20. Note that both the NAND gate and the NOR gate must give negative outputs to
produce the ground D SET level at terminal L20U. The NOR gate gives a negative output when the IA3
level from the IR decoder is at ground (this condition is not fulfilled when the IR contains 60 JMP, 64
EAE, 70 lOT, or 74 OPR/LAW), or when the IBO level is at ground (this condition is equivalent to an
IBO assertion and occurs when a JMP code is held in the IR).
A break state is established if a break request conditions NAND gate KLMN of module L21,
provided that neither a D SET nor an E SET level has already been established for the following cycle.
These conditions can be fulfilled at time T7 of the fetch cycle of an OPR, LAW, lOT or directly addressed
JMP instruction; during the defer cycle of an indirectly addressed JMP instruction; during the execute
cycle of any multicycle instruction; and during a break cycle.

3.3. 1 .7

Instruction Register - The I R fl ip-flops, together with the input gates and the output de-

coder appear at the right of engineering drawing 7. The output pulse of pulse ampl ifier RNPM in module
L16 clears simultaneously all four fl ip-flops. This pulse ampl ifier is triggered by anyone of the following
cond it ions:

a. A BGN pulse applied to inverter input terminal K15D (C5,7).
b. A timing pulse T1 applied to NAND gate NPR of module K16, when the gate is conditioned
by an F (fetch) level.
c. A timing pulse T1 appl ied to NAND gate JKL of module K16, when the gate is conditioned
by a B (break) level.
d. A timing pulse T2 appl ied to NAND gate DEF of module K16, when the gate is conditioned
by an E • XCT level. (The E • XCT level is generated by combining the IA2 and IBO levels
from the IR decoder with the E (execute) level in NAN D gate RSTU of module L17. The output of the gate is inverted and the E • XCT I evel appears at term inal K17U, provided that the
trap flag is not set.)

A 4-bit operation code may be set into the IR in one of the following ways:

a. When an F level conditions the four input gates in module K13, a binary 1 pulse from any
one of sense ampl ifier SAO through SA3 sets the corresponding IR fl ip-flop to 1 •

3-39

PDP-7 MAINTENANCE MANUAL

During execution of a CAL instruction, the 20-- MA pulse generated in the MA control is

applied to inverter input terminal LI5D. The inverted pulse sets flip-flop IR2 to 1, thereby
substituting a JMS (octal 10) operation code for the CAL (octal 00) code held in the IR.
c. During a deposit, deposit next, or read paper tape operation, a DP+DPN+READ-IN+RPT{l)
level conditions NAND gate STU in module L12. The gate is triggered by timing pulse SP(2)
of the key cycle and sets operation code 04 (DAC) into the IR by setting fI ip-flop IR3 to 1 •
d.

During an examine or examine-next operation, an EX+EXN level conditions NAND gate

LMN in module L12. This gate is triggered by timing pulse SP2 of the key cycle and sets operation code 20 (LAC) into the IR by setting fl ip-flop IR 1 to 1 .

The operation code is decoded by two sets of NAND gates and inverters. The gates of module
K14 and the inverters of module K15 decode the outputs of flip-flops IRO and IR1. Gating levels lAO
through 1A3 and 1A3 appear at terminals K15J, M, R, U, and T, respectively. The gates of module L14
and the inverters of modul e L15 decode the outputs of fl ip-flops IR2 and IR3. Gating levels IBO through
IB3 appear at inverter output terminals L15J, M, R, and U, respectively.

3.3.2

Timing
Each arithmetical and logical operation within the PDP-7 system is initiated by a command

pulse derived from the combination of 1 or more condition-indicating levels and 1 of 5 special purpose
tim ing pulses or 1 of 14 memory cycl e tim ing pulses. There is a considerabl e variation in the time required to perform the various machine operations because of the varying number of logic elements involved.
It is necessary, therefore, that these timing pulses be spaced at appropriate (but not equal) intervals. For
this reason, the PDP-7 does not contain a crystal clock or other generator of constant-frequency signals.
Instead, tim ing pulses are generated by two chains of pulse ampl ifiers, each ampl ifier being separated
from the next by a delay I ine or one-shot, which produces the desired interval between the two assoc iated timing pulses. Thus, a pulse or level transition appl ied to the first element is propagated down the
chain, generating as many standard-width timing pulses as there are delay/pulse ampl ifier pairs in the
chain.

If the output pulse from the last pair is returned, through a suitable delay, to the input of the

first pair, the pulse train becomes self-maintaining and ceases only when the circular path is broken at
some point.

3.3.2.1

Power Clear Pulse Generator (3)- During the power turn-on sequence, the power clear pulse

generator produces repeated PWR CL K (power clock) pulses at a repetition rate of approximately 200 kc.
These pulses clear the RUN fl ip-flop to establ ish correct initial conditions. The PWR CL K pulses are
3-40

PDP-7 MAINTENANCE MANUAL

combined with the RUN(O) level to produce positive and negative PWR CLR (power clear) pulses, which
are supplied to the reader control, punch control, and to the LUO (line unit out) buffer of the Teletype
control. The PWR CLR pulses are also suppl ied to the interface connectors, where they are available to
clear the registers of I/O devices in order to establ ish correct initial conditions.
In the power turn-on sequence, the power suppl ies wh ich provide + 1Ov and -15v for the CP
logic are energized through the fast-on, delay-off contact K3 of the Type 832 Power Control. The
memory power suppl ies are energized through the delay-on, fast-off contact K2 of the power control,
which provides a delay of 3 to 5 sec. At the beginn ing of this delay period, when the CP is first turned
on, the potential of terminals X and Y of the Type 1404 clock is near ground, thereby enabling the clock.
However, these terminals are connected through a resistor to the delayed -15v memory supply. When
memory power is turned on, the potential of terminals X and Y approaches -15v, thereby again disabl ing
the clock. The clock is enabled for a period of approximately 5 sec. The negative pulses appearing at
terminal E of the clock are inverted in module K22, (3), and the inverted pulses are appl ied to one of the
DCD gates of the RUN flip-flop to clear it. Two NAND gates in module E31 are conditioned by the
RUN (0) level (terminals E and K)i and, when triggered by the PWR CLK pulses at terminals D and J, these
gates each give an output pulse. The pulse appearing at terminal F triggers one pulse amplifier in module
E28, which produces the PWR CLR NEG pulse. The pulse appearing at terminal L of module F31 triggers
a second pulse ampl ifier in module D28, which produces the PWR CLR pas pulse.

3.3.2.2

Special Pulse Generator (5) - The special pulse generator provides the special pulses required

for timing events initiated by the manual keys and switches on the operator console. These pulses consist
of the BGN (begin) pulse, used for clearing registers prior to operation, and five timing pulses designated
SPO through SP4. The special pulse generator consists of a Schmitt trigger and a chain of five pulse amp-

I ifiers, each pair of pulse ampl ifiers being separated by a one-shot delay.
Initial excitation of the special pulse generator takes place when anyone of the manual keys,
except the STOP key, is operated.

Key operation generates two negative levels designated KEY MANU-

AL and CaNT (not continue), except in the case of the CONTINUE key, wh ich generates only the KEY
MANUAL level. The KEY MANUAL level causes the Schmitt trigger in module K31 (Type W501 FLIP
CHIP) to change state, thereby providing initial excitation of the special pulse timing chain. The positive-going level transition appearing at terminal F of the Schmitt trigger is applied to terminal H of
module L30, where it triggers a pulse ampl ifier through a DCD gate. The output of this pulse ampl ifier
is a 100-nsec pulse designated SPO, which clears the RUN fl ip-flop (6). The SPO pulse is also appl ied
to input terminal E of delay module L29. After 10 fJsec, a positive level transition appears at terminal
M of the delay module and triggers the pulse ampl ifier, which provides pulse SPI. Thereafter, pulses
SP2, SP3, and SP4 appear at 2-fJsec intervals. Pulses SP1 through SP4 are 70 nsec wide positive pulses,

3-41

PDP-7 MAINTENANCE MANUAL

which strobe registers or transfer information within the CP. When a key operation is completed during
special time states SPO through SP4, timing pulse SP4 is allowed to die out; and no further action occurs
until a new KEY MANUAL level is generated.

In key operations (other than read paper tape) which re-

quire one or more computer cycles for completion, timing pulse SP4 is NAND combined with the RPT{O)
level in module M14. The pulse output from the gate triggers a DCD gate in module M28, which provides initial excitation for the CP timing signal generator.

If the REPEAT switch ts turned on, the REPEAT

level is combined with the KEY MANUAL level to trigger the Type R401 Integrating One-Shot in module
K30. After an interval determined by the SPEED controls on the console, this one-shot reverts to its
stable state and triggers the pulse ampl ifier that generates pulse SPO, thereby causing the key operation
just completed to be repeated.
The BGN pulse is generated by combining the SPl pulse with the CONT level in module L25.
The positive pulse appearing at terminal F of this module is applied to terminal E of module M17, where
it triggers a pulse amp I ifier. The output of this pulse ampl ifier is a negative BGN pulse, appearing at
terminal H, which clears the special mode flip-flops (TRAP FLAG, I/O TRAP, RPT, XCT CY), the IR
fl ip-flops, and the program interrupt sync fl ip-flops.

3.3.2.3

Timing Signal Generator - Like the special pulse generator, the timing signal generator con-

sists essentially of a chain of pulse ampl ifiers separated by delay networks.

However, the gating which

controls exc itation (or regeneration) of the first pulse is somewhat more complex. Provision is made for
a slow cycle in which additional delays are inserted between timing pulses TP6 and TP7 of one cycle and
TPl of the following cycle.
After a key cycle, entry to the main computer timing cycle is obtained by NAND-combining
tim ing pulse SP4 with the RPT{O) level (the RPT fl ip-flop having been cleared by the BGN pulse in time
state SPl). The positive output pulse from the NAND gate (module M14) is applied to terminal N of
module M28. This module consists of a Type R60l Pulse Amplifier having six DCD gate inputs, of which
five are used for isolation or selection purposes. The output of the pulse ampl ifier is a standard 100-nsec
positive pulse which triggers the first ampl ifier/delay pair of the tim ing chain.
Each amplifier/delay pair of the timing chain consists of a Type B360 FLIP CHIP module containing a pulse amplifier and a delay line.

In the PDP-7 system, the module is so connected that the

pulse ampl ifier provides a standard 40-nsec negative pulse, which is available as a timing pulse of the
TPl through TP7 series. The output pulse is also applied to the delay I ine, which provides a delay adjustable between 20 and 250 nsec, with a resolution of 0.25 nsec. The delayed negative pulse is inverted
to provide a positive trigger pulse for the next pulse ampl ifier. The 70-nsec negative timing pulses in the
series T1 through T7 are obtained from Type W607 modules, each containing three pulse ampl ifiers. The
input trigger for each pulse ampl ifier is obtained by inverting the corresponding timing pulse of the TP
series.
3-42

PDP-7 MAINTENANCE MANUAL

During a normal computer cycle, the TP6 pulse (delayed by 240 nsec) is routed through a Type
B104 Inverter in module M21. This inverter gate is conditioned by a SLOW Cye level, and its positive
output pulse triggers the succeeding pulse ampl ifier to produce the TP7 pulse. The TP7 pulse returns to the
first pulse ampl ifier of the chain through a 150-nsec delay and a series of gates. The next cycle begins
immediately, if the following conditions are met: Inverter input term inal M21 K is conditioned by a negative STOP CP TC level (indicating that no EAE operation is in progress); and inverter input terminals
M21E and N15T are enabled by a negative SLOW CYC level and a negative RUN (1) level, respectively.
If these conditions are satisfied, both the level input (H) and the pulse input (J) of a DCD gate in module

M28 are enabled; and the delayed TP7 pulse triggers the associated pulse ampl ifier to initiate the generation of pulse TP1 of a new cycle.

If EAE operations are in progress, the inverter input at M21 K may be

disabled by a positive STOP CP TC level; and the processor is then temporarily halted. The processor is
restarted when a positive START CP TC pulse arrives at input terminal T of another DCD gate, which is
conditioned by a positive RUN (1) level.
During a slow cycle, the inverter in module M21 is disabled. The TP6 pulse then travels
through a second inverter of module M21 (input terminal P), which is conditioned by the SLOW eyC level.
The positive output pulse from the inverter is appl ied to the one-shot in module M20. This one-shot has a
DCD gate input, and the delay is adjustable over the range 400 nsec to 4 !-,sec. The normal reentry into
the timing chain is disabled by the positive SLOW CYC level, which appears at inverter input terminal
M21E.

Instead, pulse TP7 is inverted in module L28; and the pulse amplifier in module K19 produces a

TP7 INVTD (B) pulse, which triggers a Type R302 One-Shot in module M20. A positive SLOW CYC level
conditions the DCD input gate of this one-shot, and, at the conclusion of the delay period, the level
transition which appears at output terminal M20M initiates generation of pulse TP1 of a new cycle.
Every lOT instruction fetched from memory causes the minor state generator to produce negative IA3 and IB2 levels. These levels go to input terminals Rand P, respectively, of module L23 (C4,6)
where they are NAND combined with the I/O TRAP (0) level. Thus, provided that the I/O TRAP fJ ipflop has not been set, the gate gives an output which is inverted and appears as a negative lOT level at
terminal K23K (C4,6). Each I/O device that requires a slow cycle must generate a negative RQ SLOW
CYC level. This level is NAND combined with the lOT level in module L22 (D5, 6) to produce the positive SLOW CYC and negative SLOW Cye levels. The inverter in module K22 (D6, 6) in turn produces
the negative SLOW CYC and positive SLOW CYC levels. These four levels control the gates that determine the signal paths through the timing chain for normal and slow cycles. The total delay of the slow
cycle is factory adjusted to accommodate the slowest I/O device in use.
When the tape reader is loading information into memory, each tape character is read into the
reader buffer as the result of an operation in the READ-IN mode which uti! izes timing pulses SPO through
SP4 of one key cycle. However, the reader buffer assembles an 18-bit computer word by storing three
type characters successively in different sections of the buffer. The information transfer between reader
3-43

PDP-7 MAINTENANCE MANUAL

buffer and processor must be delayed until the reader buffer is full.
flip-flop is not set during the key cycle.

During readin, therefore, the RUN

Instead, a negative KEY MANUAL level (generated by releas-

ing the KEY MANUAL B key after initiating the operation) and a negative RPT{l) level condition the
NAND gate in module M14 (D2,22). When the reader starts to read the third tape character, the RD
FLAG fl ip-flop is set, indicating that the reader is ready to transfer information, and the negative RD
FLAG level conditions the third input of the gate. The last level to appear causes a positive-going level
transition at terminal M14H, thereby initiating a timing cycle during which the complete word is transferred from the reader buffer into the processor. When the transfer is compl ete, the reader flag is reset,
and the timing signal generator is halted until another word is ready for transfer.

3.3.2.4

Run Control (6) - The RUN flip-flop controls the continuous succession of normal computer

timing cycles. When the flip-flop is set to 1, and there is no slow cycle or stop timing request, timing
pulse TP7 of the current cycle (delayed by 150 nsec) is permitted to reenter the timing chain and generate
timing pulse TP1 of the next cycle. When the RUN flip-flop is reset to 0, it disables a gate in the reentry path and stops the computer, unless other conditions permit a new cycle to be initiated.

(Refer to

the description of the tim ing signal generator for details.) The program may halt the CP, but a manual
START or CONTINUE operation must then restart it.
The RUN fl ip-flop is an unbuffered flip-flop contained in a FLIP CHIP Type R201 module which
also contains two DCD gates for clear inputs and three for set inputs. The flip-flop is reset to 0 by the
following events:

a. When power is turned on after a shutdown, PWR CL K negative pulses are inverted in module
K22 and applied to a DCD clear input (terminal K26E) in order to establish initial conditions.
b. When any console key is depressed to initiate an operation, the SPO timing pulse is appl ied
to direct clear input terminal K26K, thereby causing any operation already in progress to be
halted at the end of the current memory cycl e.
c. A positive RUN STOP level is generated by the STOP, SINGLE STEP, or SINGLE INSTRUCTION key. This signal appears at terminal K26J of a DCD gate. Timing pulse T5 is
inverted in module L26, and the inverted pulse, applied to terminal K26H, triggers the gate
and clears the RUN flip-flop.
d. A positive HL T pulse arrives at terminal K26E to trigger a DCD gate and clear the RUN
fl ip-flop. The HL T command is generated by NAND combination of the I/O TRAP{O) level,
an MB12{l) level, and an lOP 1 pulse. The MB12{l) level is derived from the execution of

3-44

PDP-7 MAINTENANCE MANUAL

an OPR instruction contain ing a HL T micro-instruction. The RUN fl ip-flop is cl eared at time
T5. The CP halts after time T7 of the same cycle.

The RUN fI ip-flop is set under the following conditions:

Depressing the START or CONTINUE key generates a negative START+CONT level, which

is NAND combined in module L25 with the SP3 tim ing pulse. The positive pulse produced by
the gate is applied to terminal K26S, where it triggers a DCD gate and sets the RUN flip-flop.
b.

During a readin operation, a positive RPT(l) level conditions terminal K26V of a DCD set

gate. The pulse input of this gate (K26U) is triggered when a RDR HOLE 7 level is NAND
combined with timing pulse T5 of the cycle in which a hole 7 was detected. (A hole 7 indicates that the processor is to interpret and execute the last word read.)

3.3.2.5

I/O Pulse Generator (5) - Timing pulses for the control of I/O devices are generated in mod-

ules M30 and M31. Module M30 is a FL IP CH IP Type B115 containing three NAND gates; the output of
each gate triggers an associated pulse ampl ifier in module M31 to produce a standard negative 40-nsec
pulse. Any instruction of the lOT class generates a negative lOT level, which is appl ied to all three
NAN D gates. The subsequent generation of I/O pulses depends on the state of memory buffer bits
MB15, MB 16, and MB17.

If bit MB15 is 1, an lOP 4 pulse is generated at time T1 of the computer

cycle; if bit MB16 is 1, an lOP 2 pulse is generated at time T7; if bit MB17 is 1, an lOP 1 pulse is
generated at time T5. These pulses are routed to the device selector; there they are combined with
device selection levels to generate lOT command pulses that control the operation of the selected I/O
device or trigger control gates in the CP.

3.3.2.6

Manual Controls -:- The manual controls provide means of energizing and de-energizing the

computer, selecting modes of operation, manually inserting data into registers and core memory, and
visually examining the status of the most important registers. Wiring connections to the keys and switches on the operator console panel are shown on engineering drawing 3. The logic for gating signals
produced by the keys and switches is also shown on engineering drawing 3.

3.3.2.7

Interlock and POWER Switches - One deck of the key switch is connected in parallel with the

POWER switch and is closed when the switch is in the locked position. Thus, with the key switch in the
locked position, it is impossible to ruin a program because accidentally turning off the POWER switch
does not interrupt the primary power circuits. To shut down the computer, the key switch must be placed
in the unlocked position and the POWER switch in the off position. A second deck of the lock switch
3-45

PDP-7 MAINTENANCE MANUAL

suppl ies either ground or -15v to the key and mode switches. In the locked position, the key switch
grounds all key switches to disable them thereby preventing accidental interference with a program that
is running.

3.3.2.8

Key Circuits - When the computer is energized and the lock switch is in the unlocked position,

operating any of the keys or turning on the SINGLE STEP, SINGLE INSTRUCTION, or REPEAT switches
suppl ies -15v to a term inal on connector 2B29 or 2B32. The gating circuits shown on engineering drawing
3 combine key signals to generate various levels. These levels start the special pulse generator and condition control gates, as necessary, to cause the event sequences appearing in the flow diagram included
on the drawing.

3.3.2.9

Indicator Circuits - Indicators on the operator console are 28v incandescent lamps driven by

Type 4903 Light Bracket Assembl ies or Type 4904 Short Light Bracket Assemblies. These assembl ies contain a number of transistor switches, each connected between an indicator and ground. One side of each
indicator is connected to the -15v supply. A common ground potential is connected to the em itter of each
transistor through parallel-connected diodes, which provide the appropriate base-emitter bias. Each transistor switch is turned on by a negative signal I evel derived from a fl ip-flop and connected to the base
through a resistor. When a fl ip-flop is in the 0 state, it suppl ies a ground potential that cuts off the
transistor switch and extinguishes the associated indicator lamp. When a fl ip-flop is in the 1 state, it
suppl ies a negative potential to the transistor switch; and the indicator lamp lights. The potential appi ied to a I ighted indicator lamp is approximately 14v, which provides adequate visibil ity while ensuring
very long lamp life.

3.3.3

3.3.3.1

Accumulator Register Control (9) - The command pulses which clear the AC; propagate carries;

cause rotation; initiate the transfer of information from another register into the AC; and set, clear, or
complement the link are all generated in the logic circuits shown on engineering drawing 9. These logic
circuits also generate twelve conditioning levels and two timing pulses, which primarily control the conditions under which a command pulse is generated. Some of these levels and pulses, however, are also
transm itted to other register control s.
Pulse amplifier circuit RNPM in module K2 generates fhe 0- AC command pulse and clears
all the fl ip-flops of the AC simultaneously. Anyone of the following conditions clears the AC:

3-46

PDP-7 MAINTENANCE MANUAL

a. A BGN pulse, generated at time SP1 of any manual operation except STOP or CONTINUE,
is applied to terminal L2E. The inverted pulse appearing at terminal L2D triggers the pulse
ampl ifier.
b.

During a read paper tape operation, the RPT(l) level conditions AND gate UV of module

L2. Timing pulse SP4 of the key cycle triggers the gate,' and the inverted pulse appearing at
terminal L2D triggers the pulse ampl ifier.
c.

During the execution of a LAW instruction, a negative OP LAW level conditions AND gate

PR of module L2. Timing pulse T5 triggers the gate and causes clearance of the AC. The OP
LAW level is generated by combining a 1 on bit 4 of the instruction word with the IA3 and IB3
levels produced by the IR decoder.
d. An operate class instruction microprogrammed to clear the AC contains a 1 in bit 5 of the
instruction word. The buffered output of the MB5 flip-flop conditions AND gate KL of module
L2. Timing pulse OPR triggers the gate and causes clearance of the AC. The OPR timing pulse
is generated by NAND-combining the MB4(O) level with the IA3 and IB3 levels from the IR decoder in module L12. The output of the NAND gate is inverted to produce a negative OPR
level which conditions a further NAND gate (terminals JKL of module K8). This gate is triggered by timing pulse T4 and causes the pulse amplifier circuit EHF in module H8 to generate
the OP1 pulse.
e. An EAE CLA (EAE clear accumulator) level, generated in the EAE, conditions AND gate
ST of module L2. The gate is triggered by timing pulse T4 and causes clearance of the AC.

f. If the I/O trap is disabl ed, it is possibl e to microprogram any lOT instruction to cl ear the
AC during time T5 by inserting a 1 in bit 14 of the instruction. The IA3 and IB2 levels produced by the IR decoder are combined with the I/O TRAP(O) level in NAND gate NPRV of
module L23 (C4, 6). Two inverters in module K23 invert the output of the NAND gate. The
output of one of these inverters is an lOT level; the output of the other is combined with the
MB14(l) level in inverter PRS of module K23 (D4, 6). The output of this inverter is a negative lOT. CLA level, which conditions AND gate NM of module L2 in the AC control (A5, 9).
This gate is triggered by timing pulse T5 and causes clearance of the AC.
g.

During the execute cycle of an LAC instruction, the E level from the major state generator

is combined with the IA1 level from the IR decoder in module K9 to produce an E • IA1 level.

3-47

PDP-7 MAINTENANCE MANUAL

This level is further combined with the IBO level from the IR decoder in module K9 to generate an
E . LAC level, which conditions AND gate JH of module L2. This gate is triggered by timing pulse T1
of the execute cycle and causes clearance of the AC.
The XOR -+ AC command pulse causes the complementing of each bit of the AC that corresponds
to an MB bit in the 1 state.
the AC.

If the AC is cleared, the effect simply transfers the contents of 'the MB into

If the AC already contains a binary number and the propagation of carries does not follow the

XOR transfer, an exclusive OR operation is performed between the contents of the MB and the contents
of the AC; i. e., AC bits initially containing a 1 change to the 0 state if they correspond to MB bits containing a 1.

If the AC contains a binary number, and the XOR transfer is followed by the propagation of

carry pulses and then by an end-around carry of an overflow from bit ACO, the contents of the MB are
added to the contents of the AC in 1s complement arithmetic.

If the overflow from bit ACO is set into the

I ink instead of into bit AC17, the contents of the MB are added to the contents of the AC in 2s complement arithmetic. Anyone of the following conditions generates the XOR -+ AC pulse:

a. An XOR pulse originating in the EAE is appl ied to terminal L3E and initiates an XOR
command.
b.

During execution of any LAW instruction, a negative OP LAW level conditions AND gate

MN of module L3. The gate, triggered by tim'ing pulse T6, initiates the XOR command.
c.

During the execute cycle of a LAC, XOR, ADD, or TAD instruction, a negative E . IAl

level conditions AND gate HJ of module L3. The gate, triggered by timing pulse T3, initiates
an XOR command.
d.

During the execute cycle of a SAD instruction, a negative E . SAD level is generated by

combining the E level from the major state generator with the IA2 and IB3 levels from the IR
decoder in NAN D gate RSTU of module K12. The output of the gate, inverted, is the E . SAD
level and conditions AND gates PR and KL of module L3. Gate KL, triggered by timing pulse
T3, initiates an XOR command; a second XOR command is initiated when timing pulse T6
triggers gate PR in module L3.

Pulse amplifier circuit FDEC in module K5 generates the AC CRY (AC carry) command pulse.
During the execute cycle of either a TAD or an ADD instruction, the E . TAD or E . ADD ground level
is applied to NOR gate NPR of module L5 to generate the E . TAD + ADD negative level. This level

3-48

PDP-7 MAINTENANCE MANUAL

conditions NAND gate DEF of module L4. Timing pulse T4 triggers the gate, and the positive pulse
appearing at terminal L4F triggers the pulse amplifier which generates the AC CRY pulse. A positive
EAE CRY pulse originating in the EAE may also trigger the pulse amp I ifier.
Pulse ampl ifier circuit FDEC in module K3 generates the END CRY (end-around-carry) command
which causes an overflow from bit ACe to be added to bit AC17, with further carry pulses as necessary.
A negative E . ADD level conditions NAND gate TUV in module L4.

If bit ACe contains a 1 before the

carry operation, and changes to e as the result of carry pulses from less significant bits, an ACe CRY pulse
is generated. This pulse, after inversion, triggers the pulse ampl ifier STU in module K8, and the output
pulse from this amplifier triggers NAND gate~ TUV in module L4, thereby initiating generation of the END
CRY pulse. The END CRY pulse complements bit AC17, further carry pulses being generated as necessary.
Pulse amplifier circuit RNPM in module K3 generates the TAD CRY (2s complement addition
carry) command pulse which complements the link whenever one of the following conditions occurs:

a. An EAE CML (EAE complement I ink) command pulse originating in the EAE triggers the pulse
ampl ifier that generates the TAD CRY pulse.
b. An OPR instruction, microprogrammed to complement the link, contains a 1 in bit 16. The
MBB16(1) level conditions NAND gate TUV in module L5 (B5, 9), and an OP 2 pulse triggers
the gate. A TAD CRY pulse is then generated at time T7 of the computer cycle.
c.

During the execute cycle of a TAD instruction, a negative E . TAD level conditions NAND

gate NPR in module L4 (B6, 9).

If the AC overflows, this gate is triggered by the Ace CRY

(B) pulse and initiates generation of the TAD CRY pulse.
Pulse amplifier circuit RNPM in module H5 generates the C ~ AC command pulse. This pulse
complements each individual bit of the AC and occurs when an EAE CMA (EAE complement AC) command
pulse, originating in the EAE, triggers the pulse amplifier. The C ~ AC pulse also occurs at time T7 during the execution of an OPR instruction which is microprogrammed for a CMA operation by the insertion
of a 1 in bit 17. The MB17(l) level conditions NAND gate JKL in module L4 (B6, 9), and an OP 2 pulse
triggers the gate at time T7. The OP 2 pulse is generated by NAND-combining the negative OPR level
with timing pulse T7 in gate NPR of module L8 (C2, 9), and applying the resulting pulse to pulse ampl ifier
LNM in module K8.
The RAR and RAL command pulses are generated at terminals Nand D, respectively, of pulse
amplifier module K4.

A NAND gate, conditioned by an MBB13(1) level (for RAR) or an MBB14(l) level

(for RAL) triggers each of the two pulse ampl ifiers. An AC ROTATE pulse at time T5 strobes these gates
initiating generation of the RAR or RAL pulse.

If the instruction word contains a 1 in bit 7, the MBB7(l)

3-49

PDP-7 MAINTENANCE MANUAL

level conditions a NAND gate which is triggered by an OP1 pulse at time T7 and produces an additional
AC ROTATE pulse. Thus, one RAR or RAL pulse is generated at time T5 for a 1-place rotate operation;
if a 2-place rotate is microprogrammed, a second RAR or RAL pulse occurs at time T7. Rotate command
pulses originating in the EAE are appl ied to the input terminal of the RAR or RAL pulse ampl ifier (terminals K4R and K4F, respectively) and initiate generation of the RAR or RAL command pulses.
Pulse ampl ifier circuit RNPM in module K6 which appears at terminal K6N generates the
MBO - AC command pulse. This command pulse causes MB bits in the 0 state to set the corresponding bits
of the AC to the 0 state.

During the execute cycle of a logical AND instruction, the E level from the

major state generator is combined with the IA2 and IB2 levels from the IR decoder in NAND gate KLMN
of module K12 (C1, 9) and produces a negative E . AND level. The E • AND level conditions NAND
gate NPR in module J6 (C6, 26), which is triggered by timing pulse T5 and causes generation of the
MBO -+ AC pulse.
Pulse ampl ifier FDEC in module K6 which appears at terminal K6D generates the ACS1

-to

command pulse. This command pulse causes the contents of the ACCUMULATOR switches on the console
to be transferred into the AC. The ACS1 -+ AC pulse is generated at time SP2 of a DEPOSIT or DEPOSIT
NEXT key cycle. This command pulse may also be generated during the execution of an OPR instruction
containing a 1 in bit 15. The MBB15(l) level conditions NAND gate JKL in module J6, and an OP 2
pulse at time T7 triggers the gate causing generation of the ACS1 -+ AC pulse.
The ADD OV level is generated whenever the AC overflows during an ADD instruction. This
level conditions a I ink input gate which is strobed by timing pulse TP1 of the following cycle and sets the

I ink to 1 if there has been an overflow. The ADD OV level appears at the junction of term inals F7F,
F7L, F8J, and F8E. All four of the inverters connected to these term inals must produce a negative output
level to establ ish an ADD OV negative level. The possibil ity of an overflow is detected by applying the
ACO(O) status to NAND gate NPR in module F9 (B4, 9).

If this bit contains a 0 after data is XOR trans-

ferred to the AC, but before the carry pulses are generated, there is the possibil ity of an overflow.
Timing pulse T4 strobes the gate and, if bit ACO contains a 0, the POV fl ip-flop is set.

The buffered

IR3(0) level and the POV(l) level now fulfill two of the conditions for the production of an ADD OV
level. However, the states of bit MBO and bit ACO must now be sensed to determine whether an overflow
has in fact occurred. The two NAND gates in module D7 make the comparison.

If, after the carry, bit

MBO and bit ACO both contain a 1, there has been transfer of a 1 with no overflow. Terminal D7L, therefore, remains at ground potential and prevents generation of a negative ADD OV level. Similarly, if
bits MBO and ACO both contain a 0 after the carry, no transfer has taken place between these bits, and
term inal F7F remains at ground potential.

However, if bit MBO contains a 1 and bit ACO contains a 0

after the carry, an overflow occurs. Both NAND gates are disabled under these conditions, and a

3-50

PDP-7 MAINTENANCE MANUAL

negative output level from all four inverters generates the ADD OV level. The ADD OV level conditions
a I ink input gate which is strobed by the following timing pulse TP1 and sets the I ink. A few nsec later,
timing pulse T1 resets the POV flip-flop.
The OP SKP (operation skip) negative I evel is generated at term inal K10F and conditions a
gate in the PC control that increments the contents of the PC when an OPR instruction contains anyone
of six possible skip microinstructions. The OP SKP level is generated and the contents of the PC incremented at time T5 if anyone of the following sets of conditions is fulfilled:

a. Bit 8 is 0, bit 9 is 1, I ink is set.
b. Bit 8 is 0, bit10is1, contents of AC are zero.
c. Bit 8 is 0, bit 11 is1, bit ACO is 1 (sign negative).
d. Bit 8 is 1, bit 9 is 1, link is not set.
e. Bit 8 is 1, bit 9 is 1 , contents of AC are not zero.

f. Bit 8 is 1, bit 9 is 1, bit ACO is 0 (sign positive).

The NAND gates contained in modules L8, L9, and L10 (A1, B1, 9) generate the AC = 0 and
AC :/ 0 levels. These NAND gates sample the contents of each individual bit of the AC and give a ground
level at terminal L1OV if all bits are o.
Note that when more than one skip condition is specified in a single instruction, the combined
skip condition is the inclusive OR of the individual conditions when bit 8 contains a O.

3.3.3.2

Program Counter Register Control (8) - All of the command pulses which clear the PC, increment

its contents, or cause a transfer of information into the PC from other registers are generated in the control
logic circuits shown at the bottom right of engineering drawing 8. This logic element consists of six pulse
amplifiers which generate the command pulses, together with diode gates and inverters which determine the
conditions under which each pulse ampl ifier is triggered.
The pulse ampl ifier circuit at location F17 generates a 0 ~ PC command pulse which clears bits
5 through 17 of the PC. Bits 3 and 4 are used in conjunction with an extended memory and are cleared by
a pulse from the Type 148 Extend Mode Control option. Anyone of the following conditions clears bits
5 through 17 of the PC:

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PDP-7 MAINTENANCE MANUAL

a. At time SPl of a key cycle, after operation of the START, EXAMINE, or DEPOSIT key.
b. At time T5 of the fetch cycle of a JMP instruction, in preparation for the transfer of a new
address from the MB.
c. At time T3 of the execute cycle of a JMS instruction or at time T3 of a program break cycl e.
d. At time SP1 of a key cycle during a readin operation, provided that the RPT fl ip-flop is in
the 0 state.

The pulse ampl ifier c ircu it at location F16 generates an AS 1 -

PC command pulse which trans-

fers the contents of the ADDRESS switch register into the PC. Either of the following conditions generates
the command pulse:

a. At time SP2 of a key cycl e, after operation of the START, EXAMINE, or DEPOSIT key.
b. At time SP2 of a key cycle during a readin operation, provided that the RPT fl ip-flop is in
the 0 state.

The pulse ampl ifier circuit generates an MB1 -

PC command pulse which causes the contents

of bits 5 through 17 of the MB to be transferred into the PC. Bits 3 and 4 receive a similar command pulse
from the extend mode control. A JMP instruction generates the MB1 -

PC pulse at time T6 of the fetch

cycle; the information transferred is the address from which the next instruction is to be fetched.
The pulse amplifier F17 generates the MA1- PC command pulse at time T4 of the execute cycle
of a JMS instruction, or at time T4 of a program break cycle. The contents of the MA are the address at
which the current program count is to be deposited; this address is 0 for the program break.
The PC + 1 pulse increments the contents of the PC by 1 and is generated by two cascaded pulse
ampl ifiers at location L16 and location J26. The second pulse ampl ifier introduces a delay of 20 nsec
between the time at which the fl ip-flop outputs are sampled by the PC

-0-

MA pulse, and the time at which

the contents of the PC are incremented during a fetch cycle. The gating associated with these two pulse
amplifiers causes new instructions to generate the incrementing pulse during skip, jump, and special mode
operations. The incrementing pulse is generated in the following circumstances:

a. At time SP2 of a read paper tape operation.
b. At time SP4, following operation of the EXAMINE or DEPOSIT key.
c. At time T1 ofafetchcycle.
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PDP-7 MAINTENANCE MANUAL

d. At time T5 of the execute cycle of a SAD instruction if the contents of the AC are not O.
The E . SAD and AC 'I 0 levels which condition the NAND gate in module D14 are both
generated in the AC control.
e. At time T5 of the execute cycle of a JMS instruction, or at time T5 of a program break
cycle. The E • JMS component of the level which conditions terminal E of module D12 is
generated by the major state generator and IR decoder; the PROG • B component is generated
in the interrupt control.
f.

During the execute cycle of an ISZ instruction, at time T3, if a carry pulse is generated by

bit MBO of the MB, indicating that the contents of the MB are O.
g. At time T5 of an OPR instruction microprogrammed for one of the six possible skip operations, if the conditions for the skip are fulfilled. The OP SKP (operation skip) level and the
OP 1 pulse appl ied to term inals P and R of module F12 are both generated in the AC control.
h. At time T6 of a program break cycle after an illegal instruction is trapped, when the system
is operating in the trap mode. When the TRAP FLAG fl ip-flop is set, a one-shot delay generates the positive TRAP pulse that is appl ied directly to pulse ampl ifier input L16F.
i.

3.3.3.3

During an I/O device identification operation, when the flag of the selected device is set.

Memory Address Register Control (8) - The control circuits, shown at the top right of engineer-

ing drawing 8 generate all of the command pulses which cause a flow of information into the MA. This
control element consists of two Type B602 FLIP CHIP modules, each containing two 40-nsec pulse amplifiers; a Type B113 FLIP CHIP module containing four diode gates and associated inverters; and a Type
B115 FLIP CHIP module containing three diode gates and associated inverters.
The pulse ampl ifier circuit at location C15 generates standard negative pulses which clear the
entire MA under either of the following conditions:

a. At time SP1 of a key cycle after operation of any key except the STOP key.
b. At time T7 of each computer cycle, provided that the RUN fl ip-flop is in the 1 state. This
action prepares the MA for the insertion of a new address at time T1 of the following cycle.

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PDP-7 MAINTENANCE MANUAL

Pulse ampl ifier C17 generates a PC1 - MA pulse which transfers information from the PC to
the MA at time T1 of every fetch cycle. The address set into the MA by this action is that of the next
instruction to be executed.
Another pulse ampl ifier C17 generates a MB - MA pulse which transfers information from bits
5 through 17 of the MB into the corresponding bits of the MA. The transfer occurs at time T1 of a defer
or execute cycle, provided that the instruction below executed is not CAL (caU subroutine).

Either a

D ground level at terminal C14D or an E ground level at terminal C14E conditions terminal C14L with a
negative level. A negative CAL level derived from the MB control conditions terminal C14M. When
timing pulse T1 reaches terminal C14K, the positive pulse which appears at terminal N triggers the
MB1 -+ MA pulse ampl ifier.
A pulse ampl ifier C15 generates a 20

-4

MA pulse which sets octal 20 into the MA during the

defer or execute cycl e of a CAL instruction. A negative D or E level and a negative CAL level derived
from the MB control conditions NAND gate RSTU of module C14. When timing pulse T1 reaches terminal
R, the positive pulse appearing at terminal U triggers the 20 -+ MA pulse ampl ifier.

3.3.3.4

Memory Buffer Register Control (8) - The logic circuits, shown at the left of engineering

drawing 8, generate all the command pulses which clear the MB, increment its contents, and cause or
inhibit a transfer of information into the MB.

Four pulse ampl ifiers contained in two Type B602 FLIP

CHIP modules and one Type B620 Pulse Amplfier generate command pulses. A Type B684 Bus Driver provides negative or ground levels, which condition or inhibit the gates connecting the MB to the memory
sense ampl ifiers.

Diode gates and inverters combine various levels and timing pulses to select the condi-

tions under wh ich each command pulse is generated.
The 0 -+ MB command pulse generated by the pulse ampl ifier circuit RNPM at location F1
clears the entire MB register. The BGN pulse of a key cycle triggers this pulse ampl ifier at time T2 of
every computer cycle, and at time T7 of an execute cycle initiated by a readin operation.
The Type B684 Bus Driver at location C10 produces a negative MB STB INH (not MB strobe
inhibit) level continuously, thereby permitting the logic 1 pulses generated by core memory sense amp-

I ifiers to set the corresponding MB fI ip-flops during the read operation in every cycle. During certain
operations, however, the contents of a memory cell are not transferred into the MB. For these operations, a ground MB STB INH level inhibits the gates between the sense amplifiers and the MB. Anyone
of the following conditions causes generation of the MB STB IN H level:

During a program break cycle, the negative PROG • B level generated by the interrupt

control is appl ied to terminal T of diode gate module K21 and is inverted.

3-54

PDP-7 MAINTENANCE MANUAL

b. A high-speed Va device requesting a break cycle to deposit information in memory
generates a negative DATA-IN level, which conditions terminal K21 K. When the data
break is granted, the negative DATA· B level produced by the interrupt control conditions
K21 J and causes the NAND gate to produce a ground level at the input of the bus driver.
c. During the execute cycle of a JMS or DZM instruction, the E level from the major state
generator conditions terminal K21 E; and the lAO level produced by the I R decoder conditions
term inal K21 D. The NAN D gate then produces a ground I evel output which is appl ied to the
bus driver.

The MB + 1 command pulse increments the contents of the MB by 1 and is generated by two cascaded pulse ampl ifiers: FDEC of module E1 and EHD of module J26. Anyone of the following conditions
triggers these pulse ampl ifiers:

a. Time T3 of a defer cycle, when the contents of the MA are one of the auto-indexing locations 10 through 17. A" of these locations only are defined by a 0 in MA bits 5 through 13 and
a 1 bit 14. The MA5-13(O) and MA14(1) levels are combined in module F6 with the D level
from the major state generator and condition input terminal P of a NAND gate in module F2.
When timing pulse T3 is appl ied to terminal F2N, the gate is triggered, and its positive output
pulse causes the pulse ampJ ifiers to generate the + 1 -. MB pulse.
b. When a real-time clock is in use and is enabled by the program, the CLOCK· B level produced by the interrupt control when a clock break is granted conditions the NAND gate in
module F2. Timing pulse T3 triggers the gate and causes generation of the +1 -. MB pulse.
c. During the execute cycle of an ISZ instruction, the E level from the major state generator
and the 1A2 and IB1 levels produced by the IR decoder are NAND combined in module F5. The
output of the gate is inverted and conditions NAND gate in module F2. When timing pulse T3
is applied to terminal F2D, the gate is triggered and causes generation of the +1 - MB pulse.

Pulse ampl ifier circuit RNPM of module El generates the ACl -. MB command pulse which
causes the contents of the AC to be transferred into the MB. This command is generated only during the
execute cycle of a DAC instruction. The E level from the major state generator is NAND combined in
module F5 with the lAO and IB1 levels produced by the IB decoder. The output of the gate is inverted
and conditions NAND gate TUV in module F2. When timing pulse T3 is appl ied to terminal T, the gate
is triggered and causes generation of the AC1 ->- MB pulse.

3-55

PDP-7 MAINTENANCE MANUAL

The PC1-MBcommand pulse is generated by pulse amplifier circuit FDEC in module Fl and
causes the contents of the PC to be transferred into the MB. Anyone of the following conditions generates th i s command:

During a read paper tape operation, the RPT(1) level conditions NAND gate DEF in module

F9. Timing pulse SP4 triggers the gate, and the positive pulse which appears at terminal F
triggers the pulse ampl ifier.
b. During an exam ine or deposit operation, the EX + EXN + DP+ DPN level generated by the
key c ircu its conditions NAN D gate J KL in modu Ie F3. Tim ing pu Ise SP3 of the key cyc Ie
triggers the gate and cau~es generation of the PCl --.. MB pu Ise.
c.

During a program break cycle or the execute cycle of a JMS instruction, the

E • JMS+ PROG • B level conditions NAND gate DEF of module F3. Timing pulse T3 triggers
the gate and causes generation of the PCl -- MB pulse.

3.4

CORE MEMORY
Data and instruction storage and retrieval are performed in the PDP-7 by the core memory.

The standard PDP-7 is equipped with a DEC Type 149A Memory Module which can store 4096 18-bit
words and which requires a 12-bit address. The addition of a DEC Type 147 Core Memory Module expands
the memory capacity of the Type 149A Memory Module of the standard PDP-7 to 8192 words.

No auxiliary

equipment is required since the existing 15-bit memory address register (MA) provides the extra address bit required for selecting addresses in either 4K memory array. Memory capacity can be further expanded by
increments of 4096 or 8192 words to a maximum of 32,768 words.

Expansion beyond 8K requires the use

of a DEC Type 148 Memory Extension Control and the remaining two bits of the MA suppl ied within Type
148. All information enters and leaves core memory via an input/output register designated the memory
buffer register (MB). This manual describes the operation of the 8K memory; the basic principles and
methods of access to this memory are equally applicable to larger or smaller capacities. For information
on methods of accessing extended memories, refer to the maintenance manual for the Type 148 Memory
Extension Control.

3.4. 1

Memory Organization
Each 4K core memory module used in the PDP-7 is a simple, coincident-current, ferrite core

array assembled from core planes 64 cores wide by 64 cores deep.
and inhibit currents and gating circuits.

Each module is operated by read, write,

Figure 3-3 shows the interrelationship of the elements which

constitute the core memory system. The MA and MB are located in the central processor (CP). Timing
3-56

PDP-7 MAINTENANCE MANUAL

signals which control memory functions are derived from the CP timing signal generator in order to synchronize memory operations with CP operations. The memory cycles perform a read operation during
time states T2 and T3 and a write operation during time states T5 and T6. This permits random bidirectional access to any memory cell within one 1 .75-fJsec computer cycl e. Both reading and writing operations are performed during each cycle, since reading from a memory cell destroys the contents. Thus, if
the information is not to be lost, it must immediately be rewritten into the same cell from the MB. The
only exceptions to this rule occur during a data break in which the direction of transfer is into the computer core memory and during the execution of DAC, read/modify/write cycle of ISZ, ClK, auto index,
JMS, or DZN instructions.

FROM MEMORY
ADDRESS REGISTER
OF PROCESSOR

ADDRESS (MA 0 -11 )
SELECT ....

·
WRITE ·
READ

MEMORY
SELECTOR
SWITCHES
(G202)

---.

Sf£>

MEMORY
SELECTOR
MATRIXES
(G601 G602)

Y AXIS

FROM MEMORY
BUFFER REGISTER
OF PROCESSOR

DATA (MB 0-11)
,'rMA4.MA5

SELECT

IN~

FROM POWER CLEAR
AND TIMING PULSE
GENERATORS OF
PROCESSOR

TO MEMORY BUFFER
REGISTER AND
INSTRUCTION REGISTER
OF PROCESSOR

TIMING PULSES

--""

MEMORY

r---

--.
INHIBIT
DRIVERS
(G201)

CONTROL

FERRITE CORE
MEMORY ARRAY

READ/WRITE
SUPPLY CURRENTS

INHIBIT
SUPPLY CURRENT
STROBE

III DATA (SA 0-11)

SENSE
AMPLIFIERS
(GOOI)

i
MASTER
SLICE
CONTROL
(GOO2)

Figure 3-3

Core Memory System Block Diagram

3.4.2

Circuit Operations

3.4.2.1

Ferrite-Core Memory Array - The standard memory array consists of 18 planes, each having

4096 ferrite cores arranged in a 64 by 64 square. Each core can assume one of two stable magnetic
states corresponding to binary 1 and binary O. Four windings traverse each core. An X read/write
winding passes through all the cores in one horizontal row; a Y read/write winding passes through all the
3-57

PDP-7 MAINTENANCE MANUAL

cores in one vertical row; the sense and inhibit windings each pass through all the cores in the plane.
Figure 3-4 shows an exampl e of this winding for a 4 by 4 core plane.

In figure 3-4, passing a current

from right to left (write direction) of the diagram through the X2 winding produces a magnetic field
that tends to change all the cores in that row from the 0 to the 1 state. Passing a current from bottom to
top of the diagram through the Y3 winding produces a similar effect on the cores in that row. Neither
the X current nor the Y current is, by itself, strong enough to change the state of any core. However,
if both X2 and Y3 currents are turned on, the magnetic fields caused by the two currents are mutually

reinforcing in one core through which both windings pass. The combined strength of both fields causes
this, and only this, core (in each plane) to change state to the 1 condition.

In the PDP-7 system, an

array consists of 18 planes, with all the corresponding address windings connected in common so that
each plane can be considered equivalent to one bit of a storage cell. Thus, in the previous example,
the core located at coordinates X2Y3 on each plane will change to the 1 condition unl ess an inhibit
current prevents it from doing so.

Xl--f----I

X2--+---~~

X3 --+----r'

READ

INHIBIT

X4--4---~~

WRITE

+I
I
INHIBIT
WINDING

Figure 3-4

Simple Core Memory Plane Showing Read/Write,
Sense, and Inhibit Windings

3-58

PDP-7 MAINTENANCE MANUAL

If the storage cell consisting of X2Y3 cores is to contain Os as well as 1s, the cores in the
planes which correspond to 0 bits must be prevented from changing state when the writing currents are
turned on. This is accompl ished by passing a current through the inhibit windings of those planes. The
magnetic field due to the inhibit current has a direction and ampl itude which partially cancels the fields
due to the writing currents. Thus, even though both X and Y writing currents are present in all the X2Y3
cores, those cores in planes where an inhibit is also present remain in the 0 condition. After setting or
resetting cores, all of the read/write and inhibit currents are turned off without affecting the state of any
core.
To read the information stored in the X2Y3 cell, currents must be passed through all the X2 and
Y3 windings in the opposite direction, thereby tending to change all the X2Y3 cores to the 0 condition.
Cores X2Y2 of all planes which were inhibited during writing, and are thus already in the 0 state, induct
only a very small signal into the sense windings. However, X2Y3 read currents are turned on. The resulting flux change induces a relatively large signal into the associated sense windings. After ampl ification, these binary 1 signals complete the information transfer by setting the corresponding MB flip-flops.

3.4.2.2

Memory Selectors Type G202 and Memory Selector Matrixes Types G601 and G602 - The

memory selectors decode the information contained in the MA and perform memory cell selection; the
memory matrixes, controlled by the memory selectors, route read and write current pulses to the selected
memory cell.

In each memory array, address bits MA6 through MAll select read and write I ines in the

matrix of the Y axis; bits MA12 through MA18 select read and write lines in the matrix of the X axis.
Drawing E-149-0-9 shows the circuits for Y axis selection. Note that the four Memory Selector Type
G202 modules, known as drive selectors, shown at the left of the diagram, decode address bits MA6
through MA8. The four G202 modul es shown at the bottom of the diagram, known as ground sel ectors,
decode address bits MA9 through MAll. The selector modules provide pulses to open gates in the
Memory Selector Matrix Type G601 and G602 modules. A similar arrangement of memory selectors and
memory selector matrix modules provides selection of read/write I ines on the X axis, as shown in drawing E-149-0-98.

Drawing RS-B-G202 contains a schematic diagram of a memory selector. Drawings

RS-D-G601 and RS-D-G602 contain schematic diagrams of the matrixes.
The following discussion of the core selection process is based on the simplified schematic
diagram of figure 3-5. This diagram shows the logic switching circuits involved in the generation of
read and write currents for cell 46 on the Y axis. When cell Y46 is to be read, the address set into the
MA contains MA6(1), MA7(0), MA8(0), MAl 0(1), and MAll (0) which are appl ied as negative assertion
levels to the selector module. Negated ground levels corresponding to MA8(1) and MAll (1) are also
appl ied to the selector modules. The MA6(1) and MA7(0) negative levels enable transistor switches Q4
and Q5, respectively, of the drive selector module at location A10; similarly, the MA9(l) and MA10(l)

3-59

PDP-7 MAINTENANCE MANUAL

levels enabl e transistor switches Q4 and Q5 of the ground sel ector modul e at location A 13. The MA8{O)
and MAll (O) levels are both negative, thereby enabl ing transistor switch Q7 in both modules. A negated
ground level corresponding to MA8(1) and MAll (1) disables transistor switch Q2 in each module. These
levels are established as soon as the cell address is loaded into the MA during time state T1 of the computer cycle.
At time T2, tim ing pulse TP2 sets the READ 2 fl ip-flops (figure 3-6). The setting of the READ
fl ip-flop, in combination with the state of the field select bits, MA4 and MA5, causes a
SEL 1 . READ 1 level to be applied to the G202 Pulser Selector, which in turn applies a pulse to the
read pulser, thereby connecting read drive bus 4 to the positive supply. Simultaneously, the READ 2(1)
level enables transistor switch Q4 in both drive and ground selectors. The surge of current through the
transistors causes pulses to be generated which open pulse gates PG1 and PG4. A read half-select current then flows from the read/write memory current supply through the read pulser, pulse gate PG 1,
diode D1, the cores of cell Y46, diode D3, and pulse gate PG4 to the read/write common negative line.
This half-select read current is factory adjusted to approximately 330 ma. At time T3, the READ fl ipflops are both cleared in preparation for a write operation.
At time T4, timing pulse TP4 sets the WRITE 1 and WRITE 2 flip-flops, thereby enabling the
write pulser and transistor switch Q

a in the drive and ground selector modules. The resulting pulses

connect write drive bus 4 to the positive read/write current supply and opens pulse gates PG2 and PG3.
A write half-select current then flows from the supply, through pulse gate PG2, diode D4, the drive
lines of the cores of cell Y46 (in the opposite direction to the read pulse), diode D2, and pulse gate
PG3 to the read/write common negative line.

3.4.2.3

Inhibit Drivers Type G201 - The PDP-7 memory is wired for 19 Inhibit Driver modules Type

G201. Each of these modules energizes the inhibit winding of one memory plane. Note, however,
that the 19th plane is not used in the PDP-7 system unless the Type 176 Parity Checking option is in use,
in which case a 19th plane and an inhibit driver module are added and used for a parity bit. A schematic
diagram of an inhibit driver is shown in drawing RS-B-G201, and the connection of the inhibit drivers
in the memory system is shown in engineering logic diagram E-149-0-45. Figure 3· 7 shows the internal
logic circuits of an inhibit driver. A negative INH B level is applied to the module at terminals F and

J and is NAND combined with the negative 0 level of the associated MB bit in transistor switches Q2
and Q5. The combined signal output of transistor switch Q5 enables pulse gate 1, which provides the
principal on/off switching for the inhibit current. The INH B . MB{O) signal and the appropriate array
SEL signal are NAND combined in transistor gate Q2 or Q3.

If a negative SEL 0 level is present, tran-

sistor Q3 conducts and enables pulse gate 2, thereby routing the inhibit current into the inhibit winding
associated with bit X of memory array O.

If a negative SEL 1 level is applied to transistor gate Q4, pulse

gate 3 is enabled and routes the inhibit current into the corresponding bit inhibit winding of memory
3-60

CORES OF
CELL Y46

PG 1

-- -- -- -- --

READ DRIVE BUS 4

~--------------------------~----------~--------~-----

+ READ/WRITE

WRITE GROUND
BUS 6

SUPPLY

TO CELLS
Y40 THRU Y45

M,N

SEL 1- READ 1
H

SEL 1

G202
B02

""'-J

PG2
P,R

-- -- -- -- --

P63

PG4

+--____

L..-____________

-01 1
I
I
I
I
T
I
S
I
I
05
U
I
04
V
I
I
L __________________

WRITE 2

MAS (0)
MAS (1)

MA7 (0)

MA6 (I)

DRIVE SELECTOR

Figure 3-5

~~----~--------

0 8 - - Q3- -

--'

»
Z
-f

WRITE DRIVE BUS 4
~--------------------------~--------~----------~-----

SEL I -WRITE 1

-0

o-0

READ GROUND
BUS 6

DIODE -BALUN
NETWORK

06 -

READ
WRITE

-01- -

I
I
I
I

WRITE 2

MAll (0)
MAl' (1)

MAIO (I)
MA9 (1)

-03 1

SUPPLY

n
m

»
z

»
I

L _________________
GROUND SELECTOR

Typical Core Selection Circuit and Drive Current Path

PDP-7 MAINTENANCE MANUAL

200

400

600

1000

800

1200

1400

1600

1750

TPI TP2

TP3

(90t

I
1(160)

(480)

MA CHANGE

t~ DONE

(300)

MB-1
STROBEttRTN

TP5

TP4

t t
(120)

TP7

TP6
(210)

{240~

LAST FF CHANGE

~ BO'S CHANGE

TP601

INH

980

I
READ1
I ' ....._ _
__
I 80

t(150)

------J

WRITE 1

1020

510

I
1450

1490

I
READ 2

;'1
' - - - - - - - - - - '

480

WRITE 2

980

I
1480

I
I
I
I
I

NOTES:
1. ALL TIMES FROM MEMORY ADDRESS CHANGE
2. TRANSMISSION DELAYS CAUSE INHIBIT
CURRENT THROUGH CORE TO RISE BEFORE
AND DECAY AFTER WRITE CURRENTS

Figure 3-6

Memory Control Timing

array 1. The memory control logic ensures that SEL 0 and SEL 1 levels can never be appl ied simultaneousIy.

Inhibit current is appl ied to the inhibit winding of the cores through a balun which palances the

winding with respect to ground, thereby minimizing the effects of stray capacitance and permitting increased optional speeds in memory. Each Type G201 Inhibit Driver can sustain a current of 350 ma for

500 nseci however, in the PDP-7 system, the inhibit current is normally set at approximately 290 ma.

3.4.2.4

Sense Amplifiers Type G001 and Master Slice Control Type G002 - The PDP-7 memory contains

19 Sense Amplifier modules Type G001 and one Master Slice Control module Type G002.

Eighteen of

the sense amplifiers supply a standard negative pulse to the MB when an associated core changes from
the 1 state to the 0 state during a read operation. The 19th sense ampl ifier provides a parity bit when
the Type 176 Parity Checking option is in use. The master sl ice control suppl ies all the sense ampl ifiers
with closely controlled reference voltages for use in clamping and comparator stages.
3-62

Drawings

PDP-7 MAINTENANCE MANUAL

r r-CUR~NT~ --.,w- v

INHB

1
I
I

•

INHIBIT

POWER SUPPLY

ARRAY
SELECTION

K > - - - f - - - SEL 1
~--;-----~---SELO

H
.....- - - - - - 1 r - - M B X (0)

• CURRENT

t--+---...... I RETURN

INHIBIT
WINDING

ARRAY 0

Figure 3-7

INHIBIT
WINDING

ARRAY t

Inhibit Logic for One Memory Cell

RS-B-GOOl and RS-B-G002 contain schematic diagrams of the sense ampl ifier and the master sl ice control, respectively. The connection of these modules in the memory system is shown in drawing BS-E-1490-45.
Each sense ampl ifier contains a 2-stage dc preampl ifier, a rectifying sl icer, an output gate,
and a pulse ampl ifier. The first stage of the dc preampl ifier has two separate gated difference ampl ifiers,
wh ich share a common push-pull output stage. One input difference ampl ifier accepts a pulse input from
the sense winding of the associated plane in memory array 0, together with a SEL 0 ground level which
gates on the difference ampl ifier. The other input difference ampl ifier accepts a pulse from the corresponding plane in memory array 1 and a SEL 1 enabl ing level. The memory control logic provides the enobi ing levels wh ich ensure maximum stab iI ity. The sl icer suppresses nodes induced into the sense winding of a
memory plane by the read/write current pulses. Therefore, only the much larger signal produced by a
core changing state can produce an output from the sense ampl ifier.

3-63

PDP-7 MAINTENANCE MANUAL

In order to obtain an output pulse of the correct shape and duration, a strobe pulse is appl ied
to the output gate of the sense amplifier. The strobe pulse is obtained by combining timing pulse TP2 of
the computer timing chain with a field selection signal, applying the resulting pulse to a delay network,
and reshaping the delayed pulse in a pulse ampl ifier.
The strobe pulse is precisely timed with respect to the read current pulse, so that sensing occurs
at the instant when the signal induced into the sense winding reaches maximum peak ampl itude (figure
3-6).

If a core changes state, the slicer enables the output gate, and the strobe pulse causes the gate to

produce a 40-nsec output pulse. This pulse is reshaped in the p.ulse ampl ifier and appears at the output
terminal of the module as a standard negative pulse which sets an MB flip-flop.
The master sl ice control module contains three reference voltage diode networks, each with an
associated emitter follower output voltage control. The adjustment range of the first stage clamp potential
is from S.O to 6.Sv; that of the second stage clamp potential is from 11.S to 12.4v; and that of the slice
level is from S.O to 10.0v. The first and second stage clamp levels are factory preset at 6.Sv and 11.4v,
respectively, under a SO-ma load. The slice level is normally preset to 6.8v and may be adjusted so that
the sense ampl ifier gives symmetrical deviations when the sense ampl ifier + 1Ov supply is varied to the
upper and lower marginal levels.

3.4.2.S

Memory Gontrol - The memory control logic generates signals which perform memory array se-

lection and initiate the generation of read, write, and inhibit currents at the appropriate times in the
computer cycle. The logic diagram of the memory control is contained in drawing D-KA77AO-10, and
all references in the following discussion of the memory control are to this diagram unless otherwise
stated.
NAND gates in modules E21 and E22 decode address bits MAS(O) and MAS(1) producing SEL 0
SEL 1, SEL 2, and SEL 3 control signals. Each of these signals enables the sense ampl ifier gates associated
with a particular 4K memory array. When memory capacity is I imited to 8K, bit MA4 is always 0, and
bit MAS selects one of the arrays in the 8K field designated. At time T2 of the computer cycle, timing
pulse TP2 sets the READ 1 and READ 2 fl ip-flops. The READ 1 ground level output is combined with the
MAS(O) or MAS(1) level to produce a SEL • READ(l) B level which enables the read current pulser in the
address selection circuits. The negative READ 2(1) level is appl ied to the drive selectors and ground
selectors. At time T3, the STROBE 0, 1 pulse clears the READ 2 fI ip-flop first in order to disable the
read/write current pulsers; 30 nsec later, the STROBE RTN pulse clears the READ 1 fl ip-flop to disable
all the read gates in the drive and ground selectors. The setting of the WRITE fI ip-flops results in similar
actions, except that the WRITE 2 fI ip-flop opens the write gates in the memory selectors, thereby reversing
the direction of the current pulse through the memory cores.

3-64

PDP-7 MAINTENANCE MANUAL

The memory control logic includes bus drivers which provide adequate current to drive the
memory selectors and to gate the inhibit drivers. The NAND gates in module E29 combine address bit
MA4 with timing pulse TP2 for the generation of a separate strobe pulse for each of two 8K memory fields.
When memory capacity is limited to 8K, the TP2 • SEl 0, 1 pulse is used. The resulting strobe pulse is
appl ied to both 4K arrays of the 8K memory field.

3.4.2.6

Memory Current Sources - A Type 739 Power Supply is used in conjunction with the Core Mem-

ory Type 149B. The Type 739 unit contains two independent, floating power suppl ies. One supply provides read/write current, and the other provides inhibit current for a complete PDP-7 system, regardless
of the capacity of the memory. A Type 728 Power Supply provides +10v and -15v to energize the memory
logic. Both the 728 and 739 units are located at the rear of equipment bay 1, behind the memory. Circuit schematic diagrams for the 739 are shown in engineering drawings RS-C-739B, RS-B-W505, and RSG-800.

Engineering drawing RS-B-728 shows the circuit schematic for the Type 728 Power Supply.

3.5

INTERFACE AND INPUT/OUTPUT
All information transfers between the CP and I/O equipment (other than devices which use the

data break facil ity) take place under program control by way of the interface equipment and the accumulator register. Selection of an I/O device and generation of control pulses takes place in the interface
logic. Gating circuits to control information flow are located at the input of the receiving register.
The interface information transfer logic consists of four elements:

a. A device selector which decodes the lOT instruction to be executed, addresses the appropriate I/O device, and generates up to three lOT command pulses for control purposes.
b. An information coil ector which gates incoming information into the accumulator register.
c. An information distributor, consisting of bus drivers capable of driving an output system
through which information is transferred from the accumulator register to I/O devices.
d. The ClK, FlG, SKP and PWR ClR logic which controls the sequence of programmed operation.

The interface is packaged in bay 3; rows A through J. The drawing set number for the interface is KA-71 A-O (1 through 14). This drawing set also includes the control logic for the I/O equipment
suppl ied with the standard PDP-7.

3-65

PDP-7 MAINTENANCE MANUAL

3.5.1

Device Selector (KA-71 A-5)
The device selector (OS) logic generates lOT pulses to control the Va equipment and to de-

termine the data transfer sequence between the Va device and peripheral equipment. For standard
lOTs, when MB 6,7, and 8 are 0, the lOT Oxen level developed at the B117 NAND

Gate (D5:5)

enables the R151 Standard lOT Decoder. The R151 Decoder decodes MB bits 9 through 11 to enable one
of the eight standard device selectors. Each standard device selector consists of a B115 Gate, an R107
Gate, and an R603 Pulse Ampl ifier.

See table 4 of the PDP-7 Interface and Installation Manual F-78A

for device selector channel assignments. See drawing KA-71 A-6 for optional device selector coding.

3.5.2

Information Collector (KA-71A-4)
The IC consists of 18 R141 Multiple Diode Gate Modul es. The IC reads data or status informa-

tion into the AC from various devices. Seven IC channels or levels are available in the basic machines.
Each of these channels is wired to a signal cable connector corresponding to an upper half (bits 0-8) and
a lower half (bits 9-17) of the AC for optional equipment, or is wired directly to controls for the standard
PDP-7 VA equipment. On the basic machine, the paper-tape reader occupies one complete channel,
the Teletype occupies the lower half of a channel, and the status register occupies (nominally) one channel. If no card reader, card punch, or I ine printer is connected to the system, the lower half of the
status register channel may be used for other purposes. Thus, in the basic machine, the equivalent of
five free channels is available for additional IC inputs. Channel availabil ity of the IC is specified as
follows:

Use

Level

All 18 connections employed for RB of the tape reader.
2

First 9 connections employed for status signals of laRS
instruction (lOT 0314), and last 6 connections are
assigned to the step counter (SC) of the Type 177 EAE
option, when present.

3-5

All 18 connections open and assignable.

First 10 connections are open, and last 8 connections
are assigned to Teletype unit.

First 12 connections open and assignable.

3-66

PDP-7 MAINTENANCE MANUAL

Each level or channel of the IC consists of one 2-input negative AND gate for each of the 18
possible bits of an input word. The two inputs are usually supplied by a data signal and an lOT pulse which
is common to each bit of the input word. Outputs from the seven channels for each bit are N OR combined
to set the appropriate accumulator fl ip-flop. One bit for each of the seven channels is provided by a
Type R141 Diode Gate module; the entire IC is constructed of 18 of these modules.
When designing a PDP-7 system, it is necessary to consider the number of IC channels required
by peripheral equipment. If more than seven channels are required, the IC must be expanded to accommodate the additional information. Expansion requires a Type 175 Information Collector Expander consisting
of 18 Type R141 Diode Gate modules, 6 Type W640 Pulse Ampl ifier modules, and the appropriate mounting
panel and hardware. The Type 175 option connects into the standard IC through two signal cabl e connectors reserved for this purpose, and adds seven additional information channels.

3.5.3

Information Distributor
The information distributor of the basic PDP-7 system consists of 16 Type W02l Cable Connec-

tors to distribute the bus driver output signals. Negative logic 1 assertion levels from the AC appear as
ground logic 1 assertion levels on the distribution buses. The information distribution can be expanded
almost indefinitely by adding W02l Connectors, with additional bus drivers if the maximum load on the
standard drivers is I ikely to be exceeded.

3.5.4

MB Bus Drivers
The 1 levels of the MB fl ip-flops are available for distribution within the CP and to external

devices connected to the data channel. Nine Type B684 FLIP CHIP Bus Driver modules are used. Each
module contains two bus drivers, and each bus driver can supply up to 40 ma of load.
3.5.5

Control Signals

3.5.5.1

Power Clear Output Signals - The PWR CLR POS and PWR CLR NEG pulses generate in the

VO package during the first 5-sec interval following setting of the POWER switch to the on position.
These pulses initial ize and clear processor registers and control during the power turn-on period, and
are available to perform similar functions in external equipment. The PWR CLR POS signal is a 375-kc
100-nsec positive pulse generated in the Type R401 Clock module at location C15. The PWR CLR NEG
signal is a 400-nsec negative pulse produced in a pulse ampl ifier of the Type W640 module at location
C13 that is triggered by the PWR CLR POS pulses.

3.5.5.2

Begin Buffered Output Signal - The BGN (B) signal is supplied to external equipment through

a connection in the I/O package interface. This signal is a 400-nsec, -3v pulse generated by a W640
3-67

PDP-7 MAINTENANCE MANUAL

Pulse Ampl ifier at location C13 of the VO package during timing pulse SPl • CONTINUE NOT. In VO
equipment, the signal clears registers and resets control fI ip-flops to initial conditions when the START
key on the PDP-7 operator consol e is operated.

3.5.5.3

Run Output Signal - The 1 output of the RUN flip-flop is supplied to external equipment

through the interface circuits. This RUN(l) signal is a -3v when the computer is performing instructions
and is at ground potential when the program is halted. Magnetic tape and DECtape equipment use this
signal to stop transport motion when the PDP-7 halts, preventing the tape from running off the end of
the reel.

3.5.5.4

Slow Cycle Request Input Signal - The device selector supplies the SLOW CYCLE REQUEST

ground level signal to request that all lOT instructions which address a specific device be executed in
a computer slow cycle. This signal is added at the time a slow VO device is added to the computer
system. lOT instructions for the device are decoded in a Type W103 Device Selector module. The
ground level output at terminal BD when the device is selected requests the slow cycle by connection
to the input of a Type B171 Diode Gate module. This latter module is used as a ground level NOR gate
for all such request signals, and a negative output on terminal D of this module is appl ied to the processor tim ing c ircu its. The Type B171 modul e wh ich receives the SL OW CYCLE REQUEST signals from
various devices is located at E14 of the VO package.

3.5.5.5

Program Interrupt Request Input Signal - The flag of an external device can request a program

interrupt. When the device requires servicing, the condition of the flag, connected to the Type B124
Inverter module in location D27 of the I/O package, can request a program break. (The flag of the
external device should also be connected to the VO skip faci! ity so that the interrupt program can sense
the lOT 01 pulse to determine the device requesting the program break.) The PROGRAM INTERRUPT
signal level is the NOR of requests from up to nine devices that require programmed attention. The
program interrupt facil ity can be expanded to accommodate requests from nine additional devices by inserting another Type B124 module in location D28 of the VO package. When the program break is
entered, a subroutine is initiated to determine which device, of many, is to be serviced, and then to
perform the appropriate service operation (usually by supplying or receiving data under program control).

3.5.5.6

Data Break Request Input Signal - A high-speed I/O device may originate a data break re-

quest by plac ing a -3v DATA RQ I evel on the request I ine connecting the device to the computer. In
the interrupt control, the DATA RQ level is synchronized with delayed timing pulse T5 (T5-DLY) of the

3-68

PDP-7 MAINTENANCE MANUAL

current computer cycle, and sets the DATA SYNC flip-flop to 1. This causes a BK RQ level to be transmitted to the major state generator. Completion of the current instruction permits the major state generator to enter a break state, producing a (B) level. 1 nl5 (B) level combines with the DATA SYNC level
to produce a negative DATA· B level.
An external device connected to the data break fac iI ity of the computer suppl ies a DATA RQ
level, a 15-b it core memory address for the transfer, a signal indicating the direction of the transfer as
into or out of the computer core memory, and input or output connections to the MB for 18 data bits.
The DATA RQ level is sent to the computer at the time the data is ready for a transfer into the PDP-7 or
when the data register in the external device is ready to receive information from the PDP-7. This request level must be -3v for assertion, meaning a request for a data break, and drives a transistor base
requiring 2 ma of input current.

3.5.5.7

Transfer Direction Input Signal - The computer receives this signal, specifying the direction

of data transfer for a data break, from the requesting device. Transfer direction is referenced to the
computer core memory, not to the device. This signal is a -3v level when the transfer direction is in,
or is ground for an out transfer. A 3-input NAND diode gate for negative levels receives this signal at
terminal N18F. The gate also receives the internally generated DATA· B level and T3 pulse to cause
generation of the DATA ACC pulse which strobes the D1 lines into the MB.
3.5.5.8

Data Address Input Signal - During an ADDR ACC pulse of a break cycle, connections made at

the DA level input of a NOR gate in each module of the MA transfer the data address given by an VO
device to the MA.
3.5.5.9

Address Accepted Output Signal - At time T1 of the break cycle, the DATA· B level NAND

combines with timing pulse T1 to produce an ADDR ACC pulse (called DATA ADDR ->- MA pulse in early
systems). This pulse transfers the memory address in the address register of the VO device into the
processor MA. This pulse also acknowledges to the external device that its address has been accepted.

3.5.5.10 Data Information Input Signals - The 18 DJ lines establish the data to be transferred into the
MB from an external device during a data break in which the direction of transfer is into the PDP-7.
The DATA ACC pulse transfers the DI signal levels, presented to 2-input negative NAN D diode gates
at the binary 1 input 0; the MB, into the MB. This information in the MB is then written into core memory during a normal write operation. The DI signals are - 3v to designate a binary 1 or ground potential
to specify a binary 0, and should be available at the time the break request is made.

3-69

PDP-7 MAINTENANCE MANUAL

3.5.5.11

Data Accepted Output Signal - During time T3 of a data break cycle, when the external

device requests a transfer into the PDP-7, the DATA· B level causes a negative DATA ACe pulse
(called DATA INFO- MB in early systems) to be generated. This pulse strobes the data input gates of
the MB to transfer a data word from an external device into the MB. This pulse is also an output for
device synchron ization. Starting at time T5 the normal write operation writes information in the MB into
core memory.

3.5.5.12 Data Ready Output Signal - During T3 of a data break cycle in which the transfer direction is
out, the DATA· B level causes a negative DATA RDY (in early systems called MB INFO - OUT) pulse to
be generated. This pulse may strobe MBB information into the external device buffer; for this purpose the
signal may be delayed within the device to strobe the data into the buffer after an appropriate setup time.
Note that the transfer must occur prior to T2 of the next computer cycle.
3.5.5.13 Data Information Output Signals - Data break transfer from core memory to an VO device is
made through the MB, whose output is buffered for this purpose by 18 Type B684 Bus Drivers. Each bus
driver is capable of driving a 40-ma load. The MBB output terminals are in the VO package.

3.6

INPUT/OUTPUT
Peripheral equipment may either be asynchronous with no timed transfer rates or synchronous

with a timed transfer rate. Devices such as the CRT displays, teleprinter-keyboard, and the line printer
can be operated at any speed up to a maximum without loss of efficiency. These asynchronous devices
are continuously on and ready to accept data; they do not turn themselves off between transfers. Devices
such as magnetic tape, DECtape, the serial drum, and card equipment are timed-transfer devices and
must operate at or very near their maximum speeds to be efficient.
Some of the timed-transfer devices can operate independently of the central processor after
they have been set in operation by transferring a continuous block of data words through the PDP-7 data
interrupt fac i I ity. Once the program has suppl ied information about the location and size of the block of
data to be transferred, the device itself actually performs the transfer. The data interrupt fac iI ity logic
is described in Rrocessor Logic section of this chapter.
Separate parallel buffers are provided on each input/output device attached to the basic PDP-7.
The high-speed perforated Tape Reader Control Type 444B contains an l8-bit buffer and binary word assembler. The high-speed perforated Tape Punch Type 750, and the teleprinter and the keyboard of the
Teletype and Control Type 649 each contain separate 8-bit buffers. These devices are described in th is
chapter, and the buffers are located in bay 3 as part of the KA-7l A interface package.

3-70

PDP-7 MAINTENANCE MANUAL

DATA TRANSFERS VIA DATA BREAK

INFORMATION
COLLECTOR

••

18 BIT I. 75 I'-"C

4----

INFORMATION

DISTRIBUTOR

CONTROL PULSES
TO SELECTED

DEVICE:

••
•

* INClUDED WITH OPTION

Figure 3-8

Input/Output Information Flow

AC 10
THROUGH
TO 33 KSR
PRINTER

FROM
PROCESSOR
ACCUMULATOR

~ AC17

, - UNIT - CODE SERIAL INFORMATION
LINE UNIT OUT

(9-BIT TTO)

SHIFT

TTO
CONTROL

no
flOCK
CLOCK AND
FREQUENCY
DIVIDER

TlLETYII'I
IN1'lRfACI

TT~ K
ei,.o

r 1
1r

w
>

~
f?

f- )

Ht) FI-"
TTl fLAG

•

..-. }

TO
PROCESSOR
IIO SKIP
FACILITY

TTl
CONTROL

FROM 33 KSR
t<.EYBOARD

CONTROL"
LINE UNIT OUT

SERIAL
INFO

11 -

Figure 3-9

UNIT - CODE SERIAL INFORMATION

....

(6 -BIT TTl)

Block Diagram of Keyboard/Printer Control Type 649

3-71

IC 10
THROUGH
IC 17

TO
PROCESSOR
INFORMATION
COLLECTOR

PDP-7 MAINTENANCE MANUAL

Separate parallel buffers are also incorporated as part of DEC standard I/O peripheral equ ipment options. Information is transferred between the accumulator and a device buffer during the execution
time of a single-cycle lOT instruction. Because the maximum time the accumulator is associated with any
one external buffer is 1 .75 Ilsec, many standard I/O devices can operate simultaneously under control of
the PDP-7. Figure 3-8 shows the data path between device buffers and the AC through the information
collector or information distributor.

3.6.1

Teletype Model 33 Automatic Send/Receive Set
The Teletype unit suppl ied as standard equipment with a PDP-7 serves as a keyboard input and

page printer output, and as a perforated-tape reader input and a tape-punch output device. This unit is
a standard Model 33 Automatic Send/Receive Set (ASR) as described in Teletype Corporation bulletins
273B and 1184B. For operation with the PDP-7, th is un it is modified as follows:
a. The WRU (who are you) pawl is removed. Th is pawl is used only when several Teletypes
connect in a communication system so that a unit receiving a message sends a "who are you"
message to the transm itting un it wh ich automatically produces the "here is" identification code
and supplies it to the receiving station. In the computer system this pawl is removed to prevent
insertion of the "here is" code into data suppl ied to the computer from the Teletype un it.
b. Signal cables connect to a terminal block within the stand, a relay is added, and connections
are made to the tapereader advance magnet. These connections enable tape motion while the
control assembles a character, and disable the magnet when the keyboard flag is a 1, indicating
that the assembled character is ready for transfer to the computer.
This modification takes only a few minutes and does not permanently limit any normal use of
the 33 ASR.

3.6.1.1

Teleprinter Control KA71 A-0-9 - The control assembles or disassembles serial information for

the Teletype unit for parallel transfer to or from the accumulator of the processor, see figure 3-9. The
control also provides the flags which cause a program interrupt or an instruction skip based upon the availability of the Teletype unit, thus controlling the rate of information transfer flow between the Teletype and
the processor as a function of the program. Eng ineering drawing 11 shows the control and interface connections between the control and the Teletype unit.
In all programmed operations, the Teletype un it is considered two separate devices: a Teletype
input device (TTl) from the keyboard or the perforated-tape reader; and a Teletype output device (TTO) for
computer output information to be printed and/or punched on tape. Therefore, two device se lectors are
used, location D26 (5, A7 + B2). One of these is assigned the se lect code of 03 to in itiate operations
assoc iated with the keyboard/reader, and the other is assigned the sel ect code of 04 to perform operations
3-72

PDP-7 MAINTENANCE MANUAL

t'Jssociated with the teleprinter/punch. Corresponding lOT pulses from the two device selectors perform
parallel input and output functions. Pulses from the 10Pl pulse trigger the skip control element; pulses
from the IOP2 pulse clear the control flags and/or the accumulator; and pulses produced by the IOP4
pu Ise in itiate data transfers to or from the control.
Signals used by the Teletype unit are standard ll-unit-code serial current pulses consisting of
marks (bias current) and spaces (no current). Each ll-un it Te letype character consi sts of a l-un it start
space, eight l-unit character bits, and a 2-unit stop mark. The 8-bit flip-flop TTl shift register at locations C16, C17, B20, B21, and B18 rece ive the Teletype characters from the keyboard/reader. The
character code of a Teletype character loads into the TTl so that spaces correspond with binary 1sand
marks correspond to binary Os. Upon program command the complement of the contents of the TTl transfers
in parallel to the accumulator. Eight-bit computer characters from the accumulator load in parallel into
the 8-bit flip-flop shift register TTO at locations A16 through A21 for transmission to the Teletype unit.
The TTO c lock generates the start space, then sh ifts the eight character bits into a fl ip-flop wh ich controls
the printer selector magnets of the Teletype unit, and produces the stop mark. This transfer of information
from the TTO into the Teletype unit occurs in serial manner at the normal Teletype rate.
A ground IN ACTIVE signal flows from the control circuit of the Teletype incoming line unit
module when a Teletype character starts to enter the TTl. This signal clears the TT READER RUN flipflop, which in turn energizes a relay in the Teletype unit to release the tape feed latch. When released,
the latch mechanism stops tape motion only when a complete character has been sensed and before sensing
of the next character beg ins. The KE YBOARD FLAG fl ip-flop sets and causes a program interrupt when
an 8-bit computer character has been assembled in the TTl from a Teletype character. The program senses
the condition of this flag with a KSF microinstruction (skip if keyboard flag is a 1, lOT 0301) and issues a
KRB microinstruction which clears the AC and the keyboard flag; transfers the contents of the TTl into the
AC; and sets the READER RUN fI ip-flop to enable advance of the tape feed mechanism.
A TELEPRINTER FLG flip-flop sets when the last bit of the Teletype code has been set to the
teleprinter/punch, indicating that the TTO is ready to receive a new character from the AC. Th is flag
connects to both the program interrupt synchronization element and the skip control element. Upon detecting the set condition of the flag by the TSF microinstruction (skip if teleprinter flag is a 1, lOT 0401),
the program issues a TLS microinstruction wh ich clears the flag and loads a new computer character into
the TTO.
Operation of the Teletype incoming line unit TTl requires an input clock signal which is eight
times the baud frequency of the Teletype unit. Th is signal controls the strobing of Teletype information
into the TTl during the center of each baud (the most rei iable time for sensing) and controls the sh ifting
of information through the fI ip-flops of the TTL The Teletype transm itter requ ires an input c lock frequency
to be the same as the baud frequency of the Teletype un it. Th is signal controls the sh ifting of the TTO
and thus determ ines the tim ing of the ll-un it-code Teletype character it generates. The three Type R202
3-73

PDP-7 MAINTENANCE MANUAL

Dual FI ip-Flops at locations C18 through C20 produce the TTl CLOCK and TTO CLOCK signals. These
six flip-flops form a binary counter which provides frequency division of the output from the Type R405
Crystal Clock module at location C21. This frequency division method is used because electronic clocks
are not reliable at the low frequency required for Teletype operation. The 7.04-kc frequency of the clock
is 64 times the baud frequency of the Teletype unit. Division of the clock frequency by 8 (three binary)
fl ip-flops) yields the TTl CLOCK signal, which is eight times the baud frequency, and division by 64 (six
binary flip-flops) yeilds the TTO CLOCK signal, which corresponds with the baud frequency.

3.6.2

Perforated Tape Reader and Control Type 444B
A Digitronics Model 2500 Perforated Tape Reader and a DEC Type 444B Reader Control are

standard equipment supplied with every PDP-7 system. The tape reader is a timed-transfer device which
senses the holes punched in 5, 7, or 8-channe I paper or Mylar-base tape at a max imum rate of 300 I ines/
sec. When used in the PDP-7 system, the standard input medium is 8-channel tape. The reader control
contains an 18-bit output register loaded by the reader, together with all the logic elements necessary
for starting and stopping the reader under program control, and sensing the state of the output register.
The reader is normally mounted in the center of bay 2, immediately above the operator console. The
reader control is located in row C of the KA71 A interface package.
The mechanical and electrical operation of the reader is fully described in the manufacturer's
manual wh ich is suppl ied with the PDP-7 system and is identified in the I ist of Pertinent Documents in
chapter 1 of this manual. Therefore, the following paragraphs describe only the logical functions of the
reader and control, and the operation of the Type 444B Reader Control.

3.6.2.1

Logical Functions - The program controls entire operation of the reader. When the reader is

selected by the appropriate lOT instruction, the brake is released and the clutch engages the capstan to
move the tape past the photocells. The feedhold is sensed first, and generates a level transition which
causes sensing of the information channels. The sensing of information channels is delayed until the holes
have advanced far enough to ensure that punched holes transmit the maximum possible amount of light to
the photocells and that tape skew due to wornguidesdoesnotcause loss of information. For each hold
punched in a given I ine of tape, a corresponding bit of the RB (reader buffer) is set to 1. Information can
be read from the tape and assembled in the reader buffer in either of two modes: alphanumeric or binary.

3-74

PDP-7 MAINTENANCE MANUAL

a. Alphanumeric Mode
The alphanumeric mode, used for reading eight channels of information, is selected
by an RSA instruction of the lOT class. Each select instruction causes one I ine of tape to be
read and the information to be placed in bits 10-17 of the RB.
b. Binary Mode
The binary mode, used for reading 18-bit words, is selected by an RSB instruction
of the lOT class. One binary word occupies three I ines of tape. Each select instruction causes
three successive lines of tape to be read, each line containing six bits of binary information.
The first I ine, contain ing the most sign ificant bits, is read into bits 12-17 of the RB. The RB
performs as a 3-stage, 6-bit sh ift reg ister. When the first I ine of tape has been read, a sh ift
pulse causes the contents of RB12-17 to be shifted into RB6-11, and simultaneously reads the
second I ine of tape into RB12-17. A second sh ift pu Ise sh ifts the contents of the first Iine of
tape into bits RBO-5, the contents of the second I ine of tape into RB6-11, and reads the th ird
I ine of tape into RB12-17. The complete binary character is now assembled in bits RBO-17 and
the reader flag is set, ind icating that the reader buffer is fu II. When read ing in binary mode,
hole 7 is never punched; hole 8 is ignored, but a character is not read unless th is hole is
punched. The tape format for binary mode is shown in figure 3-10.
When a program is be ing stored by use of the READ- IN key, the processor forces the
reader into the binary mode and executes a pseudo DAC instruction each time the reader flag
is set. If a hole 7 is punched, the processor interprets th is as an instruction to stop the reader
and to execute the last 18-bit word read.

TABLE 3-3

PERFORATED TAPE READER INSTRUCTIONS

Mnemonic

Octal Code

Effect

RSA

700104

Select reader in alphanumeric mode. One 8-bit character is
read and placed in the reader buffer. The reader flag is cleared
before the character is read. When transmission is complete, the
flag is set.

RSB

700144

Select reader in binary mode. Three 6-bit characters are read
and assembled in the reader buffer. The flag is immediately
cleared and later set when character assembly is complete.

RSF

700101

Sk ip if reader flag is set.

RCF

700102

Clear reader flag; then inclusively OR reader buffer into AC.

RRB

700112

Clear reader flag. Clear AC and transfer contents of reader
buffer to AC.

3-75

PDP-7 MAINTENANCE MANUAL

CHANNEL

6
,.-A--.

CHANNEL
2
,..-J'--..

1 10 1 It 1 12 1 13 1 141151161 17

UNUSED

'---.r--J

'-v---'

'--v---J

'--..,---J

CHANNEL
7

CHANNEL

TAPE CHANNEL
8

DIRECTION OF
TAPE MOVEMENT

FEED

00000 0 000
00000 0 000
00000 0 000

L-y---J '---v--'
MOST
SIGNIFICANT
OCTAL BIT

'---y---I

SECOND
SIGNIFICANT
OCTAL BIT

LEAST
SIGNIFICANT
OCTAL BIT

Alphanumeric Mode

SECOND LINE READ

FIRST LINE READ

CHANNEL
6
~

CHANNEL

2
,--A----,

THIRD LINE READ
4

CHANNEL
6

CHANNEL

"CHANNEL

CHANNEL

,..--J.-,

r-"--o.

14 1 5

'--y-J

'-r--'

CHANNEL

1 10 1 It 112

CHANNEL

1 141151161171

'---y--I
CHANNEL

"---y-J
CHANNEL

'--y--J
CHANNEL

\--y--'

'--y--'

CHANNEL

~
CHANNEL

CHANNEL

TAPE CHANNEL
8

DIRECTION OF
TAPE MOVEMENT

FEED

00000 0 000
00000 0 000
00000 0 000
00000 0

} FIRST LINE READ}
} SECOND LINE READ
} THIRD LINE READ
FIRST LINE READ
} BY NEXT INSTRUCTION

Binary Mode

Figure 3-10 Tape Format and Reader Buffer Register Bit Assignments

3-76

BY ONE
INSTRUCTION

PDP-7 MAINTE NANCE MANUAL

3.6.2.2

Circu it Operations - The logic of the Type 444B Reader Control is shown on engineering draw-

ing BS-D-KA71-0-7. The reader control contains two major groups of logic elements: the reader buffer
(RB) and the control logic.
The reader buffer provides temporary storage for alphanumeric or binary characters read by the
tape reader. The RB contains two Type R203 FLIP CHIP Triple Flip-Flops, each flip-flop having a direct
clear and a DCD set input. These modules are used in bits RBO-RB5. For bits RB6-RB17, Type R202 FLIP
CHIP Double Flip-Flops are used, each flip-flop having a direct clear input and DCD set and clear inputs.
When reading in alphanumeric mode, bits RBl 0-RB17 are used. Tape characters are read directly into
these fl ip-flops, and the remain ing bits are not used. When reading in binary mode, the input gating
causes the reg ister to function as a 3-stage, 6-bit sh ift reg ister. Figure 3-11 shows a simpl ified diagram
of th is configuration. After the first I ine of tape has been read into bits RB12-RB 17, an RD SH 1FT 1 is
applied to all the DCD input gates of bits RB6-RB17.

Bit RB12 determines the condition of bit RB6, and

RB17 that of RB11, with a corresponding transfer in intermediate bits. Simultaneously, the second line
of tape is read into RB12-RB17. When the th ird I ine of tape is ready for reading, RD SHIFT 1 and RD
SHIFT 2 pu Ises are generated simu Itaneously and appl ied to the DCD input gates. The RD SHIFT 2 pu Ise
shifts the contents of bits RB6-RB11 into bits RBO-RB5. The RD SHIFT 1 pulse operates in the same manner
as before.
The (1) output of each RB fI ip (ground level) is inverted and appears on term inals of the W020
connector in location COl and of the W021 connector. Three Type R107 Inverters, each contain ing seven
inverters, are used for this purpose. The connector at location C1 routes the levels to indicators and also
provides connections to the IC.
At power turnon, PWR CLR negative pulses from the CP clear the RD BIN, RD RUN, and RD
FLAG flip-flops. A BGN pulse at time SP1 of a manual operation, or an lOT 0102 pulse from the device
se lector also initiates th is same clearing action, wh ich establ ishes in itial conditions.
An lOT 0104 command pulse starts the reader. Th is pu Ise appears whenever the reader is selected, and triggers a pu Ise ampl ifier produc ing a START pu Ise wh ich performs three functions:
a. It clears all the,reader buffer flip-flops, together with the RD FLAG, RD1 and RD2 flipflops.
b. It sets the RD RU N fI ip-flop to 1, thereby starting the tape reader.
c. If bit 12 of the MB contains a 1, the START pu Ise triggers a DCD gate that sets the RD
MODE fl ip-flop to 1. When th is fl ip-flop is in the 0 state, a ground BINARY level is produced
to select the alphanumeric mode. When the RD MODE fl ip-flop is set to 1, a negative BINARY

3-77

PDP-7 MAINTENANCE MANUAL

level appears to select the binary mode. Note that the RD MODE fl ip-flop may also
be set to 1 when a manual readin operation establ ishes an RPT (l)B level.
AC~

ACO

RD SHIFT 2

AC6

ACII

K:.17

AC12

-------ocoo---- - - -

r------DD<l1----I:::0<t---- -

RD SHIFT 10---+----00<1---00<1---- -

----I;)DoI::J--DD<J

READ IN o-----e--Dt-U~J

READ IN ~..........~t.&..I

LEVEL
HOLE 6

LEVEL
HOLE!

Figure 3-11

Reader Buffer in Binary Mode

Negative levels produced by 1 s in the first six bits of the tape are inverted and condition the
set DCD gates of fl ip-flops RB12-RB 17. Ground levels produced by as are directly appl ied to the reset
DCD gates. The levels produced by holes 7 and 8 condition an additional set of NAND gates wh ich do
not open unless strobed. The level transition produced by the feed holde causes Schmitt trigger W501 in
modu Ie D06 to change state. If the RD RUN fI ip-flop is set to 1, the output of the Schm itt trigger sets
the delay one-shot in modu Ie D05. The purpose of th is one-shot is to delay the instant at wh ich the reader
buffer samples the output of the photocells until the center I ine of the tape holes coinc ides with the center
of the feed hole. There are two reasons for th is. Using a correctly al igned tape, sampl ing at the leading
edge of the feed hole wou Id take place before the other holes were central ized over the photocells, so
that the output of the photocells would not yet have reached its maximum value. More important, if
worn tape guides have caused skew in the tape, sampling at the leading edge of the feed hole might cause
loss of information from holes 7 and 8, as shown in figure 3-12. Delaying the sampl ing instant ensures that
under tolerable conditions of skew all photocells produce some output, so that no information is lost.
When reading alphanumeric mode, the RD STRB output pulse from the one-shot triggers a DCD
gate conditioned by a ground BINARY level, and the output of the gate causes an RD SHIFT 3 signal to
appear. This pulse, inverted, strobes the hole 7 and hole 8 NAND gates. At the same time, the RD STRB

3-78

PDP-7 MAINTE NANCE MANUAL

pulse triggers two other DCD gates conditioned by a BINARY level. One of these gates causes generation
of an RD SHIFT 1 pulse; the other causes generation of a RD SHIFT 2 pulse. These RD SHIFT pulses strobe
all the DCD input gatesofthe RB flip-flops and read a line of tape into bits RB10-RB17. This strobe pulse,
inverted, sets the RD FLAG fl ip-flop. Since the NAND gates for holes 7 and 8 are not strobed, these
holes are not read.

However, hole 8 is always punched, and the negative level, inverted, permits gen-

eration of the RD SHIFT signals by condition ing DCD gates.

FEED
HOLE

-A--A--A- -A--A--f\--A--A--~2J

-v--v--V--s:.E~T:::::T:EV---V-~A~::~- ~
CENTER: MAXIMUM OUTPUT

g~~~~~N

SAMPLING AT LEADING
EDGE: REDUCED OUTPUT

:r-s;-=--=-~-=-=CX
-=-ff-=-8~
_u
__ u-~---- - ~f2=_~0~-U=: =:Q~-SKEWANGLEf

B. SKEWED TAPE

SAMPLING AT FEED HOLE
CENTER: ALL HOLES GIVE
SOME OUTPUT
SAMPLING AT FEED HOLE
LEADING EDGE: HOLE 8 LOST

Figure 3-12

Effect of De layed Sampl ing

The RD SHIFT 2 pulse which accompanies the reading of the first line of tape sets the RD 1
fl ip-flop. The output of th is fI ip-flop conditions the DCD set gate of the RD 2 dl ip-flop, and the fl ipflop is set when the RD SHIFT 2 pu Ise of the second I ine of tape appears. The RD 2(1) output conditions
the DCD set gate of the RD FLAG fI ip-flop, and when the th ird I ine of tape is read, the accompanying
RD SHIFT 2 pu Ise sets the RD FLAG fl ip-flop. The setting of the RD FLAG fI ip-flop indicates to the CP
that the reader buffer is fu II. The positive-going level transition produced by the RD FLAG fI ip-flop
clears both the RD MODE and the RD RUN fl ip-flops. Clearing the RD MODE fl ip-flop reestabl ishes the
alphanumeric mode; clearing the RD RUN fl ip-flop stops the reader.

3.6.3

Tape Punch and Punch Control Type 75D
The Teletype Tape Punch Set (BRPE) and "the DEC Type 75D Punch Control are supplied with

each PDP-7 as standard equ ipment. The tape punch is a timed-transfer device capable of punch ing 5-,
7-, or a-channel tape at a maximum rate of 63.3 char/sec. In the PDP-7 system the standard output
medium is 8-channel tape. The punch control contains an 8-bit data register, which is loaded from the
AC through the information distributor. It also contains all the logic elements necessary for starting and

3-79

PDP-7 MAINTENANCE MANUAL

stopping the tape punch and supplying it with the appl icable data. The tape punch is mounted in the
center bay, above the tape reader. The punch control is located in rows A and B of the KA71 A interface package.
The manufacturer1s manual suppl ied with the PDP-7, (see I ist of Pertinent Documents, chapter 1
of th is manual), fully describes the mechanical and electrical operation of the tape punch. Consequently,
the following paragraphs describe only the logical functions of the tape punch, and the operation of the
punch control.

3.6.3.1

Logical Functions - The program normally controls entire operation of the tape punch. How-

ever, the operator may punch leader tape (feed hole only punched) by pressing the PUNCH FEED button
on the console or he may force on the punch power by setting the console PUNCH switch. When the first
punch lOT instruction selects the tape punch, the punch is turned on and after a l-sec delay (during wh ich
the punch motor comes up to speed), punch ing beg ins. Subsequent punch instructions are executed immediately. The punch control functions as a buffer, a control unit, and a solenoid and motor driver for
the tape punch. When a tape punch operation is selected by an lOT instruction, a pu Ise establ ishes the
operating mode of the control (alphanumeric or binary) and causes the transfer of certain of the 1s stored
in AC to the buffer register of the punch control via the information distributor. If the mode is alphanumeric, the 1s are transferred from AC bits 10-17. If the mode is binary, the 1s are transferred from AC
bits 12-17. The flip-flops containing 1s then enable a series of gates which trigger solenoid drivers and
upon receipt of the punch command, a hole is punched in the tape in each channel where a corresponding
1 was present in the AC. When a I ine of tape has been punched, the buffer reg ister and PUN ACTIVE
fl ip-flops are cleared, and the PUN FLAG is set to indicate to the CP that the punch is ready for a further
punch ing instruction. After the last punch command, the motor remains energized for an additional 5 sec.
a.

Alphanumeric Mode
The alphanumeric mode, wh ich a PSA instruction of the lOT class selects, is used

for punch ing 8-channe I tape. Each se lect instruction causes one I ine of tape, consisting of
eight bits, to be punched. A hole is punched in each tape channel whose corresponding bit
in the AC is a 1, and a feed hole is always punched.
b. Binary Mode
The binary mode, selected by a PSB instruction of the lOT class, is used for punch ing
18-bit words. Holes are punched corresponding to bits 12-17 of the PB. Bit 11 (hole 7) is
never punched and bit 10 (hole 8) is always punched. Th is establ ishes the standard format for
binary information on tape. Since only six data bits are punched at a time, a complete 18-bit
word requ ires three I ines on the tape and consequently involves three separate PSB instructions.

3-80

PDP-7 MAINTE NANCE MANUAL

TABLE 3-4 TAPE PUNCH INSTRUCTIONS
Mnemonic

Octal Code

PSA

700204

Effect
Punch a line of tape in alphanumeric mode. The
punch flag is immediately cleared and then set
when punch ing is complete.

700244

PSB

Punch a Iine of tape in binary mode. The punch
flag is immediately cleared and then set when
punch ing is complete.

700201

PSF

Skip the following instruction if the punch flag
is set.

700202

PCF

Clear the punch flag.

The following instruction clears the accumulator and causes a line of tape to have only the
feed hole punched:
PSA+10

700214

Clear ACandpunch.

The following instruction as used on the PDP-4 is also available, but is generally replaced with
the more direct PSA.
700206

PLS

3.6.3.2

Same as PSA.

Circuit Operations - Punch Control Type 75D may be divided into the following major functional

circuit groups: control logic, punch buffer and solenoid drivers, and motor logic. Engineering drawing
KA-71A-0-3 shows all these elements.
a. Control Log ic
The operation of the punch is entirely under program control, and the control log ic
contains all the circuits which interpret a punch instruction and indicate to the CP when a
punch ing operation is complete. PWR CLR pu Ises generated in the CP at turnon are appl ied to
terminal L of the connector in module A09. These pulses, inverted, trigger a pulse amplifier
in module A09 clearing the punch buffer, which is also cleared if an lOT 0202 command pulse
and an MB15 (0) level cause a pulse to appear. In both cases the PUN MODE fI ip-flop is also
cleared.
The elements responding to program control are the PUN MODE flip-flop, which
determines whether alphanumeric or binary characters will be punched on the tape; the PUN
ACTIVE fI ip-flop, wh ich starts and stops the motor; and the PU N FLAG, wh ich is set to 0 at
the beg inn ing of a punch ing operation and is set to 1 when the punch ing of a character is complete •
. 3-81

PDP-7 MAINTENANCE MANUAL

An lOT 0202 command pu Ise clears the PUN MODE fl ip-flop. The fI ip-flop is set
by an lOT 0204 pu Ise, produced by an instruction to punch, if bit 12 of the instruction contains
a 1, spec ifying binary mode.

When set, the PUN MODE fl ip-flop forces a 0 into bit 11 of the

punch buffer (hole 7) and a 1 into bit 10 (hole 8). When the PUN MODE fl ip-flop is in the 0
state (for alphanumeric mode), the corresponding bits of the AC se ts bits 10 and 11 of the
punch buffer.
An lOT 0204 pulse, produced by an instruction to punch, clears the PUN FLAG
and PUN ACTIVE fl ip-flops. When a character has been punched, a PUN DONE level is produced clearing both these flip-flops and the buffer register. The PUN FLAG (1) level appears
at terminal T of the W021 connector in location B30, and is routed to the break control in the
CP. The PU N ACTIVE (1) level is uti I ized in the motor log ic •
b. Punch Buffer, Solenoid Drivers, and Synchron ization
The punch buffer (PB) is an 8-bit register providing temporary storage for information
suppl ied by the AC. The PB (1) levels condition the solenoid driver input gates. FI ip-flops
PBl 0-PB17 are cleared by PWR CLR pulse at power turnon, by an lOT 0202 command pulse,
and by the PUN DONE signal produced after the punch ing of each character. The DCD set
gate of each fl ip-flop is conditioned by the state of the corresponding bit of the AC and is
triggered by an lOT 0204 pulse. Thus, binary 1s are transferred from the AC into the PB.
2-input NAND gates control the solenoid drivers. The corresponding PB (1) level conditions
one input of each gate; the other input is enabled by a 5-msec signal generated in the synchronization c ircu its. During th is 5-msec period each fu Ily enabled gate causes the assoc iated
solenoid driver to energize the solenoid, and a hole is punched in the corresponding tape position. The solenoid driver for the feed hole punch receives only the synchronizing signal and
produces a feed hole for every operation.
c. Motor Log ic
The punch is turned on and off under program control, but the motor requ ires 1 sec
to attain full speed. To eliminate delay in the execution of successive punch instructions, it
is desirable to keep the motor running for 5 sec after a I ine of tape has been punched, so that
a further punch instruction can be executed immediately. The motor logic provides the requ ired
control signals for th is purpose. The Type R302 Delay One-Shot at location Bll delays the
execution of the first punch instruction for 1 sec to allow the motor to come up to speed, and
the Type R303 Integrating One-Shot at location R2B4 keeps the motor runn ing for 5 sec after
execution of the last punch instruction. These functions are accompl ished as follows:

3-82

PDP-7 MAINTENANCE MANUAL

(1) If a punch lOT instruction sets the PUN ACTIVE fl ip-flop, or if the the console
TAPE FEED pushbutton is pressed, a PUN RQ level is produced wh ich sets the integrating one-shot to its unstable state. The negative level produced at the (1) term inal of the integrating one-shot is inverted and causes a relay driver to energ ize
relay K1, thereby starting the motor.
(2) Punching cannot begin until a ground PUN READY level appears at NAND gate
output terminal B27N and conditions the DCD input gate of the 1-sec one-shot of
the synchronizing one-shot, the PUN READY level appearing only when two inputs
of NAND gate module A12 are conditioned by the negative levels. One input is
conditioned by the PUN RQ level. The other input is conditioned by the inverted (0)
level of the 3-sec delay one-shot at location AB1 o. When the integrating one-shot
is set and starts the motor, the positive-going level transition appearing at the (0)
term inal triggers the 1-sec delay one-shot into its unstable state. The output of the
delay one-shot, inverted, disables the NAND gate in module A12 thus preventing
the generation of a PU N READY level wh i1e the motor is gathering speed.
(3) After 1 sec, the motor having attained full speed, the delay one-shot reverts to
its stable state. A ground level is inverted wh ich causes a PUN READY level to
appear at the output of the gate.
(4) After a character has been punched, the PUN DONE level transition clears
the PUN ACTIVE flip-flop, producing a ground PUN RQ which removes the level
holding the integrating one-shot in its unstable state. The PUN READY level disappears immediately, preventing further punching. However, the integrating oneshot does not yet change state, and the motor continues to run. At the end of its
5-sec timing period, the integrating one-shot reverts to its stable state, causing
relay K1 to be de-energized and the motor to stop. Note that the 5-sec timing
period of the integrating one-shot does not beg in until clearance of the PUN ACTIVE
fl ip .. flop removes the PUN RQ signal holding the integrating one-shot in the unstable
state. If a further PUN RQ signal is generated before the end of the timing period,
tim ing action is immed iately halted. Thus, the integrating one-shot does not revert to
its stable state and stop the motor until Q full 5-sec period has elapsed since completion of the lost punch instruction.

3-83

PDP-7 MAINTENANCE MANUAL

CHAPTER 4
OPTIONS

4.1

INTRODUCTION
Th is chapter presents descriptions of standard options not described in other publ ications. The

standard options available with the PDP-7 are divisable into three groups: input/output, processor, and
memory.

4.2

INPUT/OUTPUT OPTIONS
Table 4-1 I ists the I/O options and the source for detailed descriptions. Chapter 3 describes

the channel arrangements for accommodating both medium- and high-speed options (program controlled
transfer channels, data channels, direct memory access channels, and automatic priority interrupt
channel s).

TABLE 4-1

I/O OPTIONS AND APPLICABLE DOCUMENTS

Option

Vendor

Document

Card Reader and Control
Type CR01 B

DEC

F-75A

Card Reader and Control
Type 421

DEC

H-421 A/451 A

Card Punch and Control Type 40

DEC

F-15(40)

Automatic Line Printer and Control
Type 647

DEC

F-75A

DECtape and Control TU55 and 550

DEC

H-TU55
H-550

Magnetic Tape Control Type 57 A

DEC

H-57A

Magnetic Tape Transport Type 570

DEC

H-570

Magnetic Tape Transport Type 545

DEC

F-75A

Magnetic Tape Transport Type 50

DEC

Magnetic Tape Equipment
Types 50/51/52

Serial Drum System Type 24

DEC

H-24

Incremental Plotter Control Type 350

DEC

PDP-8 Options Manual

Oscilloscope Display Type 34A

DEC

F-15 (34)

Precision CRT Display Type 300

DEC

F-15 (30E)

4-1

PDP-7 MAINTE NANCE MANUAL

TABLE 4-1

I/O OPTIONS AND APPLICABLE DOCUMENTS (continued)

Options

Vendor

Document

Precision Incremental CRT Display
Type 340

DEC

H-340

Photomu Itipl ier Light Pen Type 370

DEC

H-370

Analog-to-Digital Converter
Type 138E

DEC

H-138E

Multiplexer and Control Type 139E

DEC

H-139E

Analog-to-Digital Converter Type 142

DEC

H-142B

Data Control Type 174

DEC

F-75A

Data Communication System Type 630

DEC

Engineering Bulletin 630

Relay Output Buffer Type 140

DEC

see H-340

Interprocessor Buffer Type 195

DEC

F-75A

Symbol Generators Types 33 and 342

DEC

H-33 and H-342

4.3

PROCESSOR OPTIONS

4.3.1

Automatic Priority Interrupt Type 172B
The optional Automatic Priority Interrupt (API) Type 172B connects up to 16 I/O devices to

the program interrupt fac iI ity of the PDP-7 processor and allows each device to in itiate a program interrupt based on a prewired priority. The API provides direct identification of an interrupting device so
that the interrupt subroutine is not required to determine this by scanning device flags. The API also
executes multilevel interrupts in which a high-priority device may be granted an interrupt which supersedes an interrupt already in progress. These functions permit servicing more devices with greater speed
and efficiency. The API occupies two mounting panels, whose location depends to some extent upon
what other options are included in the PDP-7 system.

4.3. 1 . 1

Block Diagram Discussion - The API consists of a control element, a priority chain, and an

address selector. The real-time clock of the processor is assigned to channel 178 of the API.

Figure 4-1

shows the relationship of these elements to each other and to the processor. When a PDP-7 includes the
API option, it is connected in place of the real-time clock of the basic system and has a corresponding
priority {lower than data break interrupt requests, but higher than program interrupt requests}. An interrupt request from a device connected to the API is granted if the following conditions are met:

4-2

PDP-7 MAINTENANCE MANUAL

a. The API is in the enabled condition (by program control).
b. The requesting channel is in the enabled condition (by program control).
c. There is no data interrupt request present or data interrupt in progress.
d. There is no interrupt in progress on a higher priority channel.
e. There is no interrupt in progress on the requesting channel.

I ..
WI .....
IOP 1,2,4
I ....
T3

SYNC

CAC + PWR CLR ..

MB6(!)-MB1 1

PWR CLR
Pll _____ MA
PROCESSOR
AND
INTERFACE

t-,INT RQ

......

MA14IA
THROUGH
MA17IA

......

I
I
I
I

.....
......

PSE (1)
CONTROL

DBK

I
I

PIB1-+MA

-..

PRIORITY
CHAIN

(16)
~

...
r

CLR
CLK
FLG

CLK
FLG

f
ADDRESS
SELECTOR

)

REAL-TIME
CLOCK
(CH 17)

..£HAN RQ (16)
~

6.3V, GO'V

......

I
I
I
I
I
I

L __ - -

--- -

FLAGS
CLEAR
FLAGS"

I
I
I
I

1/0
DEVICES

-- J

DATA OUT

DATA IN

......
.......

lOT PULSES

Figure 4-1

....

Automatic Priority Interrupt Type 172B Block Diagram

Each channel in the API system is assigned a unique/ fixed/ core memory location (4°8-578). When an
interrupt is granted/ the next instruction is taken from the memory location assigned to the requesting
channel.
a. Control
The control element contains all the logic requ ired for enabl ing or disabl ing the
entire priority system or selected channels/ in response to lOT instructions. The control
element also generates the interrupt request (INT RQ) level signal/ which causes the processor
to grant an API interrupt (equivalent to a clock break in the basic system) at the first available opportunity.
b. Priority Chain
The priority chain contains a set of three fl ip-flops for each channel/ designated
bXX1, bXX2, and bXX3/ where XX represents the channel number. Each bXX1 flip-flop/
when set, enables the associated API channel. lOT instructions, in conjunction with the
contents of bits 2-17 of the accumu lator, sets and clears these fl ip-flops. At time T3/ a

4-3

PDP-7 MAINTENANCE MANUAL

SYNC pulse opens gates which a bXX1(l) level and a CH FLG (channel flag) level condition.
The output pulses from gates associated with enabled requesting channels set the associated
bXX2 fl ip-flops. The bXX2(l) output from the highest priority fl ip-flop generates a CHAN RQ
(channel request) level for the associated channel, and disables gates which prevent a CHAN
RQ level from being generated by channels of lower priority. Only one channel at a time can
generate a CHAN RQ level. The channel request level generated by the requesting channel
wh ich carries the highest priority is appl ied to the address se lector element, wh ich generates
the memory address assigned to that channel and an INT RQ (interrupt request) level. When
the processor grants an API break, it generates a PI1- MA pulse.

The PIl- MA pulse

sets the address wh ich the address selector generates into the MA of the processor, and transm its it to the API where it sets the bXX3 (hold break) fl ip-flop of the requesting channel. The
level transition that occurs when the bXX3 flip-flop is set to 1 clears the device flag. This
flip-flop remains set until the control element generates a DBK (debreak) pulse. It is cleared
by a CAC (clear all channels) instruction.
c. Address Se lector
The address selector consists of four NOR gates which set 1s or Os into bits 14-17 of
the MA to produce the memory address of the channel in which a CHAN RQ level is generated.
The channel address is transferred into the MA at time Tl of the API break cycle. The API
address selector also containscircuits that assure that MA121A is always a 1 and MA131A is
always a

when the API is granted an interrupt; hence the memory address range of 40 -57a.
a

d. Real Time Clock
The real-time clock consists of a Schmitt trigger, a pulse amplifier, and a clock
flag fl ip-flop. The Schm itt trigger input rece ives a 6.3 vac, 60 cps signal from a processor
power supply, and the trigger output is coupled to the pulse amplifier, which produces 100nsec pu Ises at the rate of 60 per sec. Each clock pu Ise sets the c lock flag fl ip-flop and, if its
channel is enabled, requests an API break. One channel (CH17a) if assigned to the real-time
clock and one is assigned for overflow from the core memory location containing the clock
count.

4.3.1.2

Logical Functions
a. Channel Allocation
The API provides 16 automatic interrupt channels arranged in a priority chain so that
channel OOa has the highest priority and channel 17a has the lowest priority. Each channel is
assigned a un ique, fixed memory location in the range 40a (C HOOa) through 57a (C H17 a). Each

4-4

PDP-7 MAINTENANCE MANUAL

I/O device is assigned a unique channel in order of device operating speed. The higher-speed
devices are assigned to the higher-priority channels. The priority chain guarantees that if two
or more devices request an interrupt concurrently, the first interrupt is granted to the device
with the highest priority. When th is device has been serviced, further interrupts are granted
to the other dev ices, in order of priority.
b. Mu Iti-Instruction Subroutine Mode
This mode is generally used to service an I/O device that requires control information from the PDP-7. Such devices are alarms, slow electromechanical devices, teleprinters,
punches, etc. Each device requires a servicing subroutine that includes instructions to manipulate data and give further instructions, such as continue, halt, etc., to the interrupting device. When an interrupt is granted, the contents of the channel memory location are transferred
to the MB and executed. If the instruction executed is JMS Y, the system operates in the
multi-instruction subroutine mode. The contents of the program counter and the condition of
the I ink are stored in location Y, and the device-servicing subroutine starts in Y + 1. (Note
that it is often useful to store the contents of the AC before servicing the device and to restore
the AC prior to exiting from the servicing routine.)
The interrupt flag is normally lowered by the 172, but can be lowered by an lOT
instruction if desired. Program control now rests with the servicing routine.
A return to the main program is accompl ished by an instruction sequence that restores
the AC and Iink, issues a debreak lOT, and gives a jump indirect to location Y (where the
contents of the PC prior to interrupt are stored). The debreaking lOT requires no channel designator, since the interrupt priority chain automatically releases the correct channel and returns
it to the receptive state. Th is lOT normally inh ibits all other interrupts for one memory cyc Ie
to ensure that the jump indirect Y is executed immediately.
The following program example illustrates the action that takes place during the multiinstruction subroutine mode. Assume an interrupt on channel 03.
Memory Location

Instruction

Operation

1000

ADD 2650

Instruction being executed when interrupt
request occurs.

0043

JMS 3000

Instruction executed as a result of interrupt
on channel 03. The JMS determines multiinstruction mode.
The Iink, condition of the extend mode, and
the PC are stored in location 3000.

3000
3001

First instruction of servicing routines stores AC.

DAC 3050

4-5

PDP-7 MAINTENANCE MANUAL

Memory Location

Instruction

Operation

3002
3003
3004
3005
3006

Instructions serv ic ing the interrupting in/out
device.

3007

LAC 3050

Restores AC for main program.

3010

DBR

Debreak ing lOT re leases channe I •

3011

JMP I 3000

Return to main program sequence.

1001

Next instruction executed from here un less
another priority interrupt is waiting.

c. Sing le- Instruction Subroutine Mode
In some instances, it is desirable for the PDP-7 to receive information from an external device but not to send control information to the device, such as in the counting of
real-time clock pulses to determine elapsed time. The single-instruction subroutine mode
simpl ifies programming a counter.
An interrupt request is subject to the same conditions as in the multi-instruction
mode, and the appropriate memory location is addressed as described previously. Then the
single-instruction subroutine mode is entered if the channel memory location does not contain
a JMS instruction. Normally the instruction is ISZ. In any case, since the signal instruction
constitutes the entire subroutine, the interrupt system automatically lowers the interrupt flag,
debreaks the interrupting channel, and returns the channel to the receptive condition.
If the ISZ instruction is used, the API acknowledges only the incrementing operation
and neg lects the sk ip TO avo id chang ing the contents of the program counter. If an overflow
results from the incrementing, a flag is set. This flag can be entered in another channel or
the interrupt system to cause a further program interrupt.
The following program coding illustrates operation in the single-instruction subroutine mode. Assume an interrupt on channel 06.
Memory Location

Instruction

Operation

1200

DAC 1600

Operation be ing executed when interrupt occurs.

0046

ISZ 3200

Instruction executed as a resu It of break on
channel 06. If overflow, flag is set, PC not
changed.

1201

LAC 1620

Next instruction in sequence of main program.

4-6

POP-7 MAINTE NANCE MANUAL

d. Automatic Priority Interrupt Instructions
The following instructions are added to the POP-7 with the installation of the Type
172 API option. Some instructions, for example CAC and ASC, can be microprogrammed.
Octal Code

Mnemonic

Operation

CAC

705501

Clear all channels: turn off all channels.

ASC

705502

Enable selected channel(s). AC bits 2 through
17 are used to select the channel (s).

DSC

705604

Disable selected channel (s). AC bits 2 through
17 are used to select the channel (s).

EPI

700004

Enable automatic priority interrupt system.
Same as real-time clock CLON.

DPI

700044

Disable automatic priority interrupt system.
Same as real-time clock CLOF.

ISC

705504

Initiate break on selected channel (for maintenance purposes). AC bits 2 through 17 are
used to select the channel.

DBR

705601

Debreak. Returns highest priority channe I to
receptive state. Used to ex it from mu Itiinstruction subroutine mode.

AC bits 0 to 1 are avai lable for expansion of the basic automatic priority interrupt
system to 4 groups of 16 channe Is.

4.3.1.3

Circuit Operations
a. Control
The control circuits generate seven conditioning levels and ten command pulses for
the operation of the API system. The logic circuits which produce these signals are shown on
engineering drawing 172B-2.
The PWR CLR + CAC positive pulse provides a means of collectively clearing all
fl ip-flops contained in the API, either automatically at power turn-on or under program
control. The PWR CLR + CAC positive pulse appears at pulse amplifier output terminal 1:.:51<',..
This pulse ampl ifier is triggered either by PWR CLR POS pulses appl ied to OCD gate E3E, F f
or by lOP 1 pulses generated in the processor and inverted by inverter LMN of module E7 (el,
172B-0-2). The inverted pulse is appl ied to DCD input E3H; and, if the level input of this
gate is conditioned by an 10 55 level, the pulse ampl ifier is triggered and generates the
PWR CLR + CAC pulse.

4-7

PDP-7 MAINTENANCE MANUAL

The 10 55 and 1056 levels are the basic enabl ing and disabl ing levels for the
entire API system. These levels are generated by decoding the content of bits 6 through 11 of
the MB in NAND gates at location F3 and F4. The 1055 assertion levels appear at terminals
F3E (negative) and F3D (ground). The 1056 levels appear at terminals F4E (negative) and
F4D (ground).
The PSE(l) (priority system enable) negative level conditions the NAND gates associated with channel 00. The PSE(l) ground level conditions a DCD gate, wh ich resets fl ipflop b003 in the priority chain when triggered by a COMMON DEBREAK pulse. The PSE(l)
levels are generated by the PS ENABLE fI ip-flop, wh ich is set by an EPI (enable priority interrupt)
instruction and reset by a DPI (disable priority interrupt) instruction. These lOT instructions
contain a 1 and a 0, respectively, in bit 12, which conditions NAND gates JKL and DEF in
module A12. The lOT 0004 command pulse, generated in the device selector, triggers whichever gate is conditioned and sets or resets the fI ip-flop. The PS ENABLE fl ip-flop must be set
by an EPI instruction before the API can initiate an interrupt from any channel.
The ASC 5502 command pu Ise appears at pu Ise ampl ifier output term inal E3U. An
IOP2 pulse generated in the CP triggers this pulse amplifier which inverter PRS of module E7
inverts. The inverted pu Ise is appl ied to DCD input E3P and triggers the pu Ise ampl ifier when
an 10 55 ground level conditions the gate. The ASC 5502 pu Ise sets all bXXl fl ip-flops of the
priority chain whose DCD set gates are conditioned by a 1 in the corresponding bit of the AC.
The DSC 5604 command pulse appears at pulse amplifier output terminal E5K. An
inverted lOP 4 pu Ise appl ied to DCD input 5E triggers th is pu Ise ampl ifier when the DCD gate
is conditioned by an 10 56 ground level. The DSC 5604 pulse resets all bXX1 fl ip-flops of the
priority chain whose DCD reset gates are conditioned by a 1 in the corresponding bit of the AC.
The ISC 5504 command pu Ise appears at pu Ise ampl ifier output term inal E4K. An
inverted lOP 4 pu Ise appl ied to DCD input term inal E4E triggers th is pu Ise ampl ifier when the
the gate is conditioned by an 1055 ground level. The ISC 5504 pulse sets the bXX2 flip-flop
of any channel selected by the insertion of a 1 in the corresponding bit of the AC. The setting
of the bXX2 fl ip-flop initiates a break request by the selected channel (or by the highest
priority channel if more than one has been selected). This command initiates a break request
on the selected channel or on the highest priority channel selected, independent of the channel
enable/disable conditions. The channel must be disabled if there is no device connected to it.

If a device is connected to the channel, the channel can be enabled, but the program must
consider the status of the external device. The ISC instruction allows diagnostic routines to
initiate a break on any channel, independent of external operations.

4-8

PDP-7 MAINTENANCE MANUAL

The negative INSURE DEBREAK level is generated by the INSURE DEBREAK flipflop and appears at terminal A15J when the flip-flop is set to 1. This level is applied to terminal J30P of the break control in the CP and forces a BK RQ condition for one cycle at the
end of an API break. This ensures that an indirectly addressed JMP instruction providing exit
from a break routine wi II be executed immediate Iy. Any instruction that generates a DBK (debreak) command sets the INSURE DEBREAK fI ip-flop wh ich is reset to 0 by timing pulse T3 of
the following cycle.
The DE BR (debreak) command pu Ise appears at pu Ise ampl ifier output terminal E5 (C3,
172-0-2). This pulse not only sets the INSURE DE BREAK flip-flop, but also triggers a pulse
ampl ifier to produce a COMMON DEBREAK command pulse in the priority chain. The DEBR
command pulse is generated by either of the following conditions:
(1) An lOP 1 pulse, inverted, is combined with an 1056 ground level in DCD gate
PR of modu Ie E5 to trigger the pu Ise ampl ifier.
(2) The INT RECOGNIZED fI ip-flop is set during time Tl of the API break cycle
by a PI1 -..

MA pulse generated in the break control of the CP. The INT

RECOGNIZED (1) negative level conditions one input of the NAND gate in module
E8. If two other inputs are conditioned by an F (fetch) level and a JMS level, at
time T5 of the fetch cycle the gate is triggered and causes the pulse ampl ifier to
generate the DBK pulse. If the following cycle is also to be a fetch, the F SET level
from the major state generator is combined with timing pulse T7 of the current cycle
to reset the INT RECOGNIZED flip-flop.
The OVERFLOW FLAG (1) level is generated during an API break in which the instruction in the assigned memory location of the requesting channel is ISZ. If the indexing
operation causes an overflow, an MBO CRY (B) pulse triggers gate NPR of module A12 and
sets the OVERFLOW FLAG fl ip-flop. The (1) output is appl ied to another channel of the
priority chain and initiates a break request. The OVERFLOW FLAG flip-flop is cleared when
the interrupt is granted.
A SYNC command pulse appears at pulse amplifier output terminal E9N. This pulse
amplifier is triggered by NAND gate RNPV of module E8 which is operated at time T3 of each
cyc Ie in wh ich the INT REC leve I and the 10 DEVICE 56 are both present. The presence of
these levels assures that no SYNC pulse will be issued when the API tries to debreak (DEBR)
and return to the main program sequence. The SYNC command pulse sets the bXX2 flip-flop
of all API channels wh ich have been enabled and are requesting an interrupt with a CH FLAG
level.

4-9

PDP-7 MAINTENANCE MANUAL

The PIBl

MA pulseappearsot pulse amplifier output terminal E9H. This pulse

ampl ifier is triggered when a PIl
granted. The PIl

MA pu Ise appears, ind icating that an interrupt has been

MA pulse is generated- in the processor break control circui ts at time

Tl of the break cycle and forces the major state generator to the fetch state. Th is pu Ise appears
at terminal IL 25H and is identical to the CLOCK 7 The PI Bl

MA pulse of the basic PDP-7 system.

MA pu Ise is appl ied to all channels of the priority chain, thereby setting fl ip-

flop bXX3 of the highest priority enabled. Setting of th is fl ip-flop turns on the channel and
clears the flag of the device to wh ich an interrupt has been granted.
b. Address Se lector
The address selector circuits generate negative levels which condition the input
gates of bits 14 through 17 of the MA, thereby setting the memory address assigned to the
requesting channel into the MA. The address selector circuits also generate the INT RQ level
which sets the API SYNC (CLK SYNC in the basic system) flip-flop of the break control (engineering drawing KA77-A-14). The CHAN RQ (channel request) levels of all channels in the
priority chain are applied to the four NOR gates in modules A16, A17, Ala, and A19. Only
the highest priority requesting channel generates a CHAN RQ level, so that only one address
at a time can be set up. In addition to the four MA addressing levels generated by the NOR
gates, an MA121 A level is generated with each address by disconnecting the ground jumper
on terminal P of module F27 in the MA (KA-77-15). This wiring modification, in conjunction
with the fact that MAl 31 A is never set to 1 by the PIB

MA pulse (KA77-15) produces the

desired range of memory locations (40 -57a).
a
The INT RQ (interrupt request) level appears at terminal A14M. Any address selected
by a selected channel causes one or more of the NOR gates to apply a ground output level to
the NOR gate in module A20. The INT RQ level is then generated from A20D, unless the PS
ENABLE fl ip-flop is in the 0 state. In that case, the negative PSE (0) level is inverted in
module A14 and grounds the INT RQ line.
c. Priority Chain
Each channel of the priority chain consists of three fl ip-flops, four NAND gates, an
inverter, and a pu Ise ampl ifier connected in a configuration that is identical in each channel.
The logic of the priority chain is shown on eng ineering drawing 172B-0-3 • Only channel 01
is described below, since all other channels operate in an identical manner.
Channel 01 is enabled when flip-flop bOll is set. The setting pulse is provided by
a DCD gate conditioned by a 1 in bit 3 of the AC and triggered by an ASC 5502 command pulse
from the control element. Sim i1arly, the channel is disabled when fl ip-flop bOll is reset by

4-10

PDP-7 MAINTE NANCE MANUAL

the combination of a 1 in bit 3 of the AC and a DSC 5604 command pu Ise from the control
element. When channel 01 is enabled under program control, the bOll (1) level conditions
one input of NAND gate KLMN in module E14(C2, 172B-0-3). Another input is conditioned
by a CH 1 FLG (channell flag) level generated in the associated I/O device. At time T3 of
the computer cycle, a SYNC pulse from the control element triggers the NAND gate; and the
output of the gate sets fl ip-flop b012. This fI ip-flop may also be set by the combination of a
1 in bit 3 of the AC and an ISC 5504 command pulse from the control element. Use of the
ISC instruction causes a break to be initiated on the selected channel without a prior enabl ing
instruction.
Three levels condition NAND gate KLMN in module Cl0. The input at terminal M
is a negative level indicating that channel 01 is enabled and that the associated device has
requested a break. The input at terminal L is a negative level indicating that no break is already in progress on th is channel. The input at term inal K is a negative level indicating that
no break is in progress on a channe I or higher priority, and that the API system as a whole is
enabled. If all these conditions are met, the gate becomes fu Ily enabled and generates a
CHAN 01 RQ (channel 01 request) ground level at terminal Cl ON. The CHAN 01 RQ level
is appl ied to the control element, where it generates the memory address assigned to channe I 01,
as well as an interrupt request level, which is applied to the break control of the CP. When
the interrupt is granted, the break control generates a command pu Ise wh ich sets the API address
levels into the MA, and causes the control element to generate a PIBl pulse. This pulse triggers
NAND gate DEFH in module Cl0, the priority level and a b012(1) level have already ccnditioned
the gate. The output of the gate sets the b013 fl ip-flop to 1. The positive-going level transition which appears at terminal Bl0S of this flip-flop triggers a pulse amplifier in module B9,
and produces a CLR FLG 1 pulse at terminal B9U. This pulse clears the I/O device Hag to indicate that an interrupt has been granted.
Note that any bXX2 fl ip-flop, wh ich is in the 1 state, produces a ground level at
terminal H, thereby disabling the associated NAND gate RSTU. The inverted output of a disabled RSTU gate disables inputs D, K, and R of the three NAND gates associated with the next
channel of lower priority. Th is prevents the lower priority channel from generating either a
CHAN RQ or a CLR FLG signal. When the flags of several devices are set concurrently, the
SYNC pu Ise sets the bXX2 fl ip-flop in each of these channels • However, the CHAN RQ levels
appear one by one, in order of channel priority ~
All fl ip-flops in all channels are cleared by a CAC + PWR CLR pu Ise generated in the
control element at power turn-on or when a CAC (c lear all channels) instruction is executed.

4-11

PDP-7 MAINTENANCE MANUAL

Wh i Ie an interrupt is in progress on channel 01, the b013 fl ip-flop remains set. At
the end of the interrupt, both fl ip-flops b013 and b012 are reset to O. A COMMON DE BREAK
pu Ise from the control element resets fl ip-flop b013 and the level transition of b013 resets fl ipflop b012. Note that the COMMON DEBREAK pulse triggers a DCD gate conditioned by a
ground level from the channel of next higher priority. Therefore, although the COMMON
DEBR pulse is applied to all channels, only the channel to which the interrupt was granted is
cleared.

4.3.2

Data Interrupt Multiplexer Type 173
Data Interrupt Multiplexer Type 173 consists of 60 FLIP CHIP modu les contained in two mounting

panels. When th is option is added to a standard PDP-7 system, the location of the mounting pane Is depends somewhat upon the number and type of other optional equ ipment in the system. When the 173 option
is designed into a specific PDP-7 system, convenience may require that the multiplexer be located in a
specific portion of the console. Module map 173-4 shows the locations of modules within the panels.
Data Interrupt Multiplexer Type 173 permits the direct transfer of information between the PDP-7 core
memory and one of four high-speed I/O dev ices wh ich can supply 15 address lines, lS data Iines, a request line, and a transfer direction line. The multiplexer services the devices in a preset priority order
and routes the address and data suppl ied by each device into the data interrupt channel of the standard
PDP-7 system. The data interrupt channel has priority over all other interrupt requests. When a data
break is granted by the central processor on completion of the current instruction, the transfer takes place
during one computer cycle, under the control of the I/O device. The maximum combined transfer rate
of four devices connected to the CP through the multiplexer is 570,000 lS-bit words per second.

4.3.2.1

Logical Functions - Figure 4-2 shows a block diagram of the logical elements of the data in-

terrupt multiplexer and their relationship to the central processor. When one or more of the devices
connected to the multiplexer generate a channel DATA RQ level (-3v), the multiplexer control transmits
to the CP a DATA RQ level which causes the DATA SYNC flip-flop in the interrupt control to be set at
time T5 DL Y (delayed) of the current cycle. At time T6 of the same cycle, the mu Itiplexer control selects
the device having the highest priority. When the central processor reaches an "instruction done" stiuation
and grants a break cycle, the following events take place:

4-12

PDP-7 MAINTENANCE MANUAL

CH 0 ADDRESS (15)

(15)

CH 2 ADDRESS (15)

CH 1 ADDRESS
ADDRESS
{
LINES FROM
SPECIFIC DEVICE

ADDRESS
MIXER

ADDRESS

(15)

..".-

CH:3 ADDRESS (15)

~
CH 0 DATA (18)

DATA
{
LINES FROM
SPECIFIC DEVICE

CH 1 DATA (18)

.....
.....
,...,.

CH 2 DATA (18)

..-

DATA
MIXER

DATA (18)

.-.
~

....

CH :3 DATA (18)

~ MPXB

PROCESSOR

(4)

CH 0 DATA RQ

...-

... T5

CH 0 DATA IN lOUT __

... T6

,..

".-

CONTROL
LINES OF
DEVICE CH 0

__ CH 0 AD DR ACCEPT

DATA IN lOUT (XFER DIRECTION)

.........

.. CH 0 DATA ACCEPT

DATA REQUEST

.. CH 0 DATA READY

MULTIPLEXER
CONTROL

"...

__ ADDRESS ACCEPTED

(5)

{
CONTROL
LINES OF
DEVICES CH 1-:3
(SAME AS CH 0)

(5)
(5)

Figure 4-2

".-

REQUEST SLOW CYCLE'(IF REQUIRED)..-

l
J

__ DATA ACCEPTED
__ DATA READY

Data Interrupt Mu Itiplexer Type 173 Block Diagram

a. At time T1 of the break cycle, the processor transfers the address suppl ied by the requesting
device into the MA, and the multiplexer returns a negative ADDR ACC (address accepted)
pulse to the requesting device.
b. At time T3, if an in transfer has been spec ified, the processor transfers the data suppl ied
by the device into the MB, and the multiplexer returns a DATA ACC (data accepted) pulse
to the requesting device.
c. At time T3, if an out transfer has been specified, the information that was stored in the
addressed memory cell is held in the MB, and the mu Itiplexer returns a DATA RDY (data ready)
pulse to the requesting device, indicating that the requested data is ready for sampling.
d. At time T5 of the multiplexer the priority chain is cleared and the processor interrogates
the DATA RQ line.
e. If the DATA RQ line is still a -3v, the processor grants another break cycle, and the
events described in a through d are repeated until all requesting devices have been serviced
in order of priority. If the DATA RQ line is at ground, indicating that there is no further data
request, the processor fetches and executes the next programmed instruction.

4-13

PDP-7 MAINTENANCE MANUAL

4.3.2.2

Circuit Operations - The following discussion of the detailed operation of Data Interrupt Mu Iti-

plexer Type 173 is based on engineering logic drawings 173-2 and 173-3. Reference is also made to the
break control of the central processor, shown on engineering logic diagram KA77-14.
a. Data Interrupt Mu Itiplexer Control
Each of the four I/O devices which may be connected to the multiplexer must supply
a - 3v CH X DATA RQ level when it is ready to receive or transmit data. The four request lines
are OR combined in modu Ie A3 of the mu Itiplexer (173-2:C5). A data request from any or all
of the four I/O devices results in the transmission of a negative DATA RQ level to the break
control of the central processor. This DATA RQ level is AND combined with timing pulse T5
DLYto set the DATA SYNC flip-flop (KAl7-14). In the break control, the DATA SYNC (1)
level is inverted in NOR gate N21 (Al, 14) to produce a negative BK RQ level which is appl ied
to the major state generator. When the processor reaches an II instruction done ll situation, the
major state generator establishes a break state. The B (break) and DATA SYNC (l) levels are
combined to produce a DATA·B level.
In the multiplexer, the CH X DATA RQ level conditions a gate which timing pulse
T6 of the current computer cyc Ie triggers to set the assoc iated MPX fl ip-flop. There are four
fl ip-flops, designated MPXO through MPX3. The inverted (1) level of each fl ip-flop holds all
flip-flops of lower priority in the 0 state by pull-over action. Thus, only one flip-flop at a
time can be set, and if two or more I/O devices have generated a DATA RQ level concurrently,
the MPX fl ip-flop wh ich is set at time T6 wi II be that assoc iated with the dev ice of highest
priority.
The MPX (1) level performs five functions, as follows:
(1) It cond itions the address mixer gates wh ich connect the address I ines of the
requesting device to the MA.
(2) It conditions the data mixer gates which connect the data lines of the requesting
dev ice to the MB.
(3) It is NAND combined in module A6 with the CH RQ IN level to produce a
DATA IN level for transmission to the break control of the processor.
(4) It is applied to one input of a two-input diode AND gate in a Type R141
modu Ie at location A5. The outputs of the seven gates in th is modu Ie are NOR
combined. As supplied, the second input of each gate is disabled by a ground connection; however, if any of the four I/O devices require a slow cycle, the associated
gate may be conditioned by the CH DATA RQ and MPXB negative levels to generate
a negative RQ SLOW CYC level for transmission to the processor timing circuits.
4-14

PDP-7 MAINTENANCE MANUAL

(5) It is applied to the input of a bus driver, whose output conditions three NAND
gates contained in a Type R111 module. The Type R111 modules for channels 0
through 3 are at locations C12 through C15, respectively. In each channel, an
ADDR ACC (address accepted) pulse from the processor triggers one NAND gate;
the output of the gate causes an associated Type W607 pulse amplifier to transmit a
CHX ADDR ACC (channel address accepted) pulse to the requesting device. A
DATA ACC (data accepted) pu Ise triggers these gates during an inward transfer,
causing the associated pulse amplifier to transmit a CHX DATA ACC pulse to the requesting device. A DATA RDY (data ready) pulse triggers the third gate during an
outward transfer causing the associated pulse amplifier to transmit a CHX DATA RDY
pulse to the requesting device. The three control pulses (ADDR ACC, DATA ACC,
and DATA RDY) are generated in the processor (as the DATA ADDR INFO

MB, and MB INFO -

MA, DATA

OUT pulses, respectively) and are transmitted

to the mu Itipl iexer control.
At time T5, timing pulse T5 (inverted) applied to the direct clear inputs of all four
MPX fl ip-flops resets them to O. If no other I/O device has generated at the CH DATA RQ
level in the meantime, the DATA RQ line is at ground and permits timing pulse T5 DLY to
c lear the DATA SYNC fl ip-f1op in the break control. At the conc lusion of the break cyc Ie,
the processor then fetches and executes the next programmed instruction. If, however, a further
CH DATA RQ level has been generated, the DATA SYNC flip-flop remains set and the processor
grants further data break cyc les unti I all requesting dev ices have been serv iced in order of
priority.
b. Address Mixer and Data Mixer
The address mixer consists of 15 Type R141 Diode Gate modules at locations B10
through B24, and 3 Type B105 Inverter modules each containing 5 inverters. Each Type 141
module contains seven 2-input diode AND gates whose outputs are NOR combined. Three of
these diode AND gates are unused. In the remaining four gates, one input is conditioned by
one of the MPXB levels; the other input is conditioned by an address I ine from the assoc iated
device. The ground level that appears at terminal D of the Type R141 module when one of its
gates is enabled is applied to an inverter of the Type B105 module. The resulting negative level
conditions the input gate of the corresponding bit of the MA.
The data mixer is sim i lar in operation to the address mixer, except the dev ice data
lines cond ition the input gates and there are 18 bits instead of 15. The Type 141 modu les are
located at positions A7 through A24, and the Type B105 modu les at positions B3, B4, C 1, and
C2. Each inverter in each mixer is equ ipped with a 15-ma clamped load; these loads are contained in Type W005 modules at locations C6 through C8.
4-15

PDP-7 MAINTENANCE MANUAL

4.3.3

Extended Arithmetic Element (EAE) Type 177
A standard option for the PDP-7, the extended arithmetic element (EAE) enables the processor

to perform arithmetic operations at faster speeds. With the EAE option installed, the processor can perform
parallel arithmetic operations. The programmer's instruction repertoire is also considerably expanded.
Certain EAE instructions being augmented are microprogrammed to perform several nonconfl icting logical
operations with one instruction. Other EAE commands are microcoded to perform specific arithmetic
operations such as multiply, divide, normal ize, and shift. The arithmetic commands allow the EAE to
operate asynchronously to the processor main timing chain permitting computations to be performed in the
minimum possible time.
The EAE logic consists of an 18-bit multipl ier-quotient register (MQ), a 6-bit step counter (SC),
two 1-bit sign registers (EAE sign and EAE AC sign), timing and control logic (EAE states, EAE register
control, and EAE main time chain) and data buffering logic (AC inverters). The four rows of EAE logic
are installed below the operator console in bay 2. The contents of the MQ register are displayed on the
MULTIPLIER QUOTIENT indicators located on the operators console below the ACCUMULATOR indicators.

4.3.3.1

Instructions - There are two classes of EAE instructions, setup and arithmetic. The setup instruc-

tion performs as an OPR instruction and is able to perform several nonconfl icting logical operations during
a normal computer fetch cycle. The EAE setup instruction consists of the op code 648 in bits

through 4

and the command code 08 in bits 9 through 11. Bits 5 through 8 and 12 through 17 are used for microprogrammed logical operations. The arithmetic class of EAE instructions performs as specific arithmetic
operations and operates in an argument fetch cycle. The EAE arithmetic instructions consist of op code
648 in bits

through 4, and the spec ific arithmetic command I isted below in bits 9 through 11 •

Multiply

Unassigned

Divide

Normalize

Long Sh ift Right

Long Sh i ft Le ft

Accumu lator Sh ift Left

Bits 5 through 8 are used for logical operations and bits 12 through 17 contain the number of
steps in the arithmetic command. For specific bit assignments refer to Table 4-2 EAE Bit Assignments and
Operations.
4-16

PDP-7 MAINTENANCE MANUAL

TABLE 4-2
Bit
Positions

Bits

0,1,2,3

11 01

EAE BIT ASSIGNMENTS AND OPERATIONS
Function

EAE operation code.

Place the AC sign in the I ink. Used for signed operations.

Clear the MQ.

Read the AC sign into the EAE AC sign register prior to carrying
out a stepped operation. Used for the signed operations multiply and divide.

6,7

Take the absolute value of the AC. Takes place after the AC
sign is read into the EAE AC sign.

Inclusive OR the AC with the MQ and read into MQ.
5 is a 1, this reads the AC into the MQ).

Clear the AC.

(If bit

9,10,11

000

Setup. Specifies no stepped EAE operation, and enables the
use of bits 15, 16, and 17. It is used as a prel im inary to multiplying, dividing, .and shifting signed numbers. Execution time
is one cycle.

9,10,11

001

Multiply. Causes the number in the MQ to be multipl ied by
the number in the memory location following this instruction.
If the EAE AC sign register is 1, the MQ will be complemented
prior to multiplication. The exclusive OR of the EAE AC sign
and the I ink will be placed in the EAE sign register (the sign
of product). The product is I eft in the AC and MQ, with
the lowest order bit in MQ bit 17. The program continues at
the location of this instruction plus two. At the completion
of this instruction the link is cleared and if the EAE sign was 1,
the AC and MQ are complemented. The step count of this
instruction should be 22 for a 36-bit multipl ication, but can be
varied to speed up the operation. The execution time is 4.2 to
8.7 ,",sec, depending on number of 1 bits in the MQ.

9,10,11

010

This is an unused operation code reserved for possible future
expansion.

9,10,11

011

Divide. Causes the 36-bit number in the AC and MQ to be
divided by the 18-bit number in MB following the instruction.
If the EAE AC sign is 1, the MQ is complemented prior to
starting the division. The magnitude of the AC is taken by
microprogramming the instruction. The exclusive OR of the
AC sign and the I ink are placed in the EAE sign. The part of
the dividend in the AC must be less than the divisor or overflow
occurs. In that case the I ink is set at the end of the divide;
4-17

PDP-7 MAINTENANCE MANUAL

TABLE 4-2
Bit
Positions

EAE BIT ASSIGNMENTS AND OPERATIONS (Continued)

Bits

Function

otherwise, the link is cleared. At the completion of this instruction, if the EAE sign was a 1, the MQ is complemented;
and if the EAE AC sign was 1, the AC is complemented. Thus,
the remainder has the same sign as the dividend. The step count
of this instruction is normally 23 (octal) but can be decreased
for certain operations. The execution time is 3.5 tJsec in the
case of divide overflow or from 9.0-12.6 tJsec otherwise.
9,10,11

101

Long right shift. Causes the AC and MQ to be shifted right
together as a 36-bit register the number of times specified in
the step count of the instruction. On each step the link fills
AC bit 0, AC bit 17 fills MQ bit 0, and MQ bit 17 is lost.
The link remains unchanged. The time is 0.1 n + 1.6 tJsec,
where n is the step count.

9,10,11

110

Long left shift. Causes the AC and MQ to be shifted left together the number of times specified in the step count of the
instruction. On each step, MQ bit 17 is filled by the link;
the link remains unchanged. MQ bit 0 fills AC bit 17 and
AC bit 0 is lost. The time is O. 1 n + 1 .6 tJsec, where n is
the sh ift count.

9,10,11

100

Normalize. Causes the AC and MQ to be shifted left together
until either the step count is exceeded or AC bit 0 AC bit 1 •
MQ bit 17 is filled by the link, but the link is not changed.
The step count of this instruction would normally be 44 (octa!).
When the step counter is read into the AC, it contains the number of shifts minus the initial shift count as a 2s complement 6bit number. The time is O. 1 n + 1 .6 tJsec, where n is the
number of steps in the shift counter or the number required to
effect normal ization, whichever is less.

9,10,11

111

Accumulator left shift. Causes the AC to be shifted left the
number of times specified in the shift count. AC bit 17 is filled
by the Iink, but the Iink is unchanged. The time is O. 1 n + 1 .6
tJsec, where n is the step count.

-I

12-17

Specify the step count except in the case of the setup command,
which does not change the step counter.

On the setup command only, causes the MQ to be complemented.

On the setup command only, causes the MQ to be incl usive
ORed with the AC and the result placed in AC. (If the AC
has been cleared, this will place the MQ into the AC).

4-18

PDP-7 MAINTENANCE MANUAL

TABLE 4-2
Bit
Positions

EAE BIT ASSIGNMENTS AND OPERATIONS (Continued)

Bits

Function
On' the setup command only, causes the AC to be incl usive ORed
with the SC and the results placed in AC bits 12-17. (If the AC
has been cleared, this will place the SC into the AC).

TABLE 4-3
Mnemoni«:
Symbol
EAE

LRS

Octal Code
640000

640500+n

EAE INSTRUCTIONS
Operatio'n

Cycle Time
(Approx i mate)

Basic EAE command. Acts as NOP instruction.
De Iays program 1 cyc Ie.

1 .5 IJsec

Long right shift. Shifts the contents of the AC
and MQ right the number of positions indicated
in OO+n where n = number of shifts.

1 .5 IJsec
+0.5 IJsec
per sh ift

IACI-'IMQI~
Lost
LRSS

660500+n

Long ri ght shift, signed. Shifts the contents of
the AC and MQ the number of positions indicated
in OO+n. The contents of ACO are initially dupl icated in the I ink. During shifting, the conTents
of the I ink fill ACO'

1 .5 IJsec
+0.5 IJsec
per shift

ACO--..LINK

rIIljl AC 1-.1 MQ I~st
ALSS

660700+n

Accumulator left shift, signed. Shifts the AC
I eft the number of positions indicated in OO+n.
The contents of AC O are initially dupl icated
in the I ink. During shifting, the contents of
the I ink fill AC17 and

1 .5 IJsec
+0.5 I-lsec
per shift

.lEJ~1 ITJ~
NORM

640444

Normal ize, unsigned. The contents of the AC
and MQ are shifted left until the contents of bit
ACO are not equal to bit AC, (AC O -I AC 1 ) or
until the contents of the AC and MQ are shifted
I eft 36 times (448 ),

-I

4-19

1 .5 IJsec
+0.5 IJsec
per shift

PDP-7 MAINTENANCE MANUAL

TABLE 4-3
Mnemonic
Symbol

Octal Code

LLS

660500+n

EAE INSTRUCTIONS (Continued)
Cycle Time
(Approx i mate)

Operation

Long left shift. Shift the contents
of the AC and MQ I eft the number of
positions indicated in +n.

1 .5 fJsec
+0.5 jJsec
per shift

rlAc 1....-1 MQ I

Lost

LLSS

660600+n

Long left shift, signed. Shifts the
contents of the AC and MQ I eft the
number of positions indicated in +n.
The contents of ACO are initially
dupl icated in the link. During
shifting, the contents of the I ink fill
MQ
and remain unchanged.
12
ACO-LINK

1 .5 jJsec
+0.5 jJsec
per shift

fIRJ---IMQ!LITJ,
Lost

ALS

640700+n

Accumulator left shift. Shifts the
contents of the AC I eft the number
of positions indicated in +n.

.[E]

1 .5 jJsec
+0.5 }Jsec
per shift

SHL

Lost
NORMS

660444

Normal ize, signed. This instruction
is used as part of the subrouti ne to
convert an integer into a fraction,
and an exponent for use in floating
point arithmetic. The contents of AC O
are dupl icated in the I ink. The contents of the AC and the MQ are shifted
left by this command until AC " AC or
1
O
until the contents of the AC and MQ
sh ift 36 times (448 ). The I ink fills MQ
17
and remains unchanged.
ACO=LINK

.[ACot AC,!
Lost

4-20

[_IMQIL[g~

1 .5 jJ sec
+0.5 jJsec
per sh ift

PDP-7 MAINTENANCE MANUAL

TABLE 4-3
Mnemonic
Symbol

Oc.tal Code

MUL

653122

EAE INSTRUCT IONS (Continued)
Cycle Time
(Approx i mate)

Operation

Multiply I unsigned. This instruction
multipl ies two 18-bit unsigned numbers
to form a 36-bit product. The multipI ier is loaded into the MQ by this
instruction.
O--MQ
AC¥MQ
The AC is cleared.
O~AC

The 2s complement of the number of bits
in the multiplier is transferred to the SC,

and the unsigned multipl icand is in location Y+ 1. This instruction stops the computer timing cycle during the fetch cycle
of Y+1 (multipl icand in the MB). MultipI ication begins with the CPTC stopped
with the major register as follows:

MB
[Mu'-:I-ti-p-::-Ii-c-an-d"""'11

SC
I No. of Steps I

On completion of multipl ication the major
registers are as follows:

AC
I'---P-ro-du-c--'tI

I Product I
SC
IClearedl

MULS

657122

This instruction multipl ies two 17-bit signed
numbers to form a 34-bit double signed product.
This instruction is microcoded to perform the
following:
1) Clear the MQ
O-+MQ
2) Get sign of multipl ier
ACO~EAE AC sign register
4-21

PDP-7 MAINTENANCE MANUAL

TABLE 4-3
Mnemonic
Symbol

EAE INSTRUCTIONS (Continued)

Octal Code

Cycle Time
(Approx i mate)

Operation

3) Transfer the multipl ier from AC to MQ.
AC

O-+AC
4) If sign is negative
(EAE AC sign = 1)
complement the MQ
(MQ -llMQ)

5) Place the number of steps
in SC

Multipl ication begins with the computer
timing chain stopped. The registers are
as follows:

1]]_____ 1Part ial Product 1~1i"""":'~M""""u--=I---:ti~p~1i-er-'I.
MB
IMultipl icand

640323

This instruction divides an l8-bit unsigned
number at location Y+l (divisor), into a
36-bit unsigned number (dividend) contained
in the AC and MQ. The number of steps (23 )
8
are transferred to the SC by this instruction.
Divisions begin with the major registers as
follows:

ISample

1..-\

SHL
AC
Dividend

1"-1 Dividend I.J
SC

IDivisor I I. .,N-:'"o-.
. -o-=-f~St-e-p--rsI
At divide end, the major registers are as follows:

IRemainder I

I Quotientl
SC
I Cleared

4-22

PDP-7 MAINTENANCE MANUAL

TABLE 4-3

EAE INSTRUCT IONS (Continued)

Mnemonic
Symbol

Octal Code

Operation

LACQ

641002

Places the contents of the MQ into
the AC.

Cycle Time
(Approx i mat e)

1 •. 6}Jsec

O·· .. AC
MQVAC

LACS

641001

Places the contents of the SC into
AC -AC •
12
17

1 • 6 }Jsec

Used as part of converting an integer
to a floating point number. Effectively, transfers the value of the
exponent to the AC.
O·~AC

SC V AC

CLQ

650000

-AC
17
12

1 .6 IJsec

Clears MQ

O--.MQ

ABS

644000

Dupl icates the contents AC in the
O
EAE AC sign register. If EAE AC
sign = 1 the AC is complemented.

1 .6 IJsec

GSM

664000

Get sign and magnitude, thus setting up
divisor or mu Itipl icand. Places AC sign
in the I ink and takes the absolute value
of AC.

1 .5 IJsec

4-23

PDP-7 MAINTENANCE MANUAL

4.3.3.2

EAE Major Units - The EAE major units are shown in figure 4-3. Refer to drawings BS-D-177-0-4

through 8.
TO EAE
SIGN REG.

STOP/START CPTC

TO EAE
AC SIGN REG.

RECYCLE

CMA, XOR,
C -til> AC,RAR,RAL
START
SETUP
MEMORY
BUFFER

MUL·DIV
EA[

OTHER

STATES

START
SHIFT

M.T.C.
AND
REGISTER
CONTROL

MQRR,MQRL,
O---MQ,I-MQ,
MQ

0""

<c
~r

::or

:Eo

MBI2-MBI7

Figure 4-3

STEP
COUNTER

TO ACI2 ...ACI7

EAE Block Diagram

a. EAE States (4)
The EAE states logic decodes the command portion of the EAE instruction to determine
the selected EAE state. It also contains the logic for stopping and starting the CPTC, and the
logic for operating the EAE asynchronous to the CPTC. The two EAE sign registers (EAE AC
sign and EAE sign) form part of this logic.
For setup instructions gate (D21, 4) decodes MB9(O), MB10(0), and MB11 (0) to generate a SETUP level at gate (D20, 4). For mu Itipl ication, gate (B24,4) decodes MB9(0),
MB10(0), and MB11 (1) at EAE T5 time to set the MUL fI ip-flop to 1 •
For division, gate (D24,4) decodes MB9(0) and MB10(1) at EAE T5 time to set the
DIV fI ip-flop to 1 •
For all sh ift operations gate (D17, 4) decodes the IA3(1), IB1 (1), and the MUL(O)
and DIV(O) levels to set the EAE·F flip-flop to 1. All shift operations start at T6 of the first
EAE fetch cycle when the START SHIFT pulse is generated at gate (D24,4).
b. Step Counter and Control (5)
The step counter (SC) is comprised of six Type B201 Flip-Flops conn(·~ted as a 2stage 6-bit octal counter. Bit registers SC15 through SC17 count the least significant octal
number, and SC12 through SC14 count the most significant octal number. The count loaded

4-24

PDP-7 MAINTENANCE MANUAL

the SC de term ines the number of steps to be performed during the EAE arithmetic operations.
The SC is loaded with the selected count during time EAE T3 of any arithmetic instruction by
the BM -.. SC pulse developed at PA (06,5). Because the SC is an "up" counter, the complement of the count contained in bits 12 through 17 of the arithmetic instruction is stored in the
SC. (MB12 through MB17 are complement connected to SC12 through SC17).
The counting sequence starts when the INPUT (LOW COUNT) signal develops the
LOW COUNT signal at PA (C19,5). The LOW COUNT signal originates at PA (B25,4) when
the START MUL·OIVor the START SHIFT pulse is developed. The SHIFT pulse developed at
PA (C19,5) initiates all further counts. The LOW COUNT pulse samples all input gates of
SC15 through SC17 which increases the count by 1. The LOW COUNT signal also samples the
status of SC15 through SC17 for ls at gate (B23,5). If SC15 through SC17 are ls, the HIGH
COUNT pulse developed at PA (014,5) increments SC12 through SC14 by one count. The SC
FULL fI ip-flop is set to 1 by two methods. At EA E T5 time, gate (026,5) is sampled. If SC 12
through SC17 are 1, the FULL fI ip-f1op is set. The other method is used with the CPTC stopped.
When SC12 through SC16 are 1, gate (B24,5) develops a FILL pulse which is delayed by delay
(030,5). The FILL pu Ise then sets the FULL fl ip-flop to 1. The SCOV fl ip-flop sets on the
sh ift pu Ise wh ich stops all EAE operations.
c. EAE Register Controls (6)
The EAE register control contains the logic for manipulating the AC, MQ and link
during EAE operations. The EAE register control also contains the adder/subtractor logic used
in the multiply and divide operations. The following is a list of the control signals and their
functions:
Signal

Function

CLR LINK

Clears the I ink at the start of the mu Itipi ication and division operation or during
m icroprogramm ing if ACO is 0

SET LINK

Sets the link to 1 during microprogramming

CMA

Complements AC

CLA

Clears AC

CML

Complements I ink

0- MQ

Clears MQ

MQ RR

Rotates MQ right

MQ RL

Rotates MQ left

AC1-.. MQ

Sets MQ bits to 1 which correspond to ACl
bits

4-25

PDP-7 MAINTENANCE MANUAL

Function

MQ1- AC

Sets AC bits to 1 wh ich correspond to MQ1
bits

XOR

Exclusive ORs the MB into the AC

CRY

Generates ACcarries

d. Main Tim ing Chain (7)
The EAE main timing chain controls the EAE timing when the CPTC is stopped. The
CPTC stops for all EAE multiply, divide, shift, and normalize operations. The EAE timing
then becomes a function of the sampl ing and sh ift rates of the AC and MQ as controlled by
the main tim ing chains.
During multipl ication, the first sample is initiated by the START and SCOV(O) levels
at gate B29. At T2 time gate D28 is sampled to determine if the first operation is in ADD or
a SHIFT by sampl ing MQ17.

Bit MQ16 is used for all further samples. At the end of mu Iti-

plication the sign of the product is tested at gate D26. If the EAE SIGN is a 1 (the product
is negative), the AC and the MQ are complemented by the CMA, 1 -+ MQ and 0 -+MQ signals
deve loped at gates D9, and C22.
For division, the first step is always subtract. The SUB fl ip-flop is set to 1 at EAE
T2.

For all other steps, the I ink is sampled.

e. Mu Itipl ier Quotient Reg ister (8)
The multipl ier quotient reg ister (MQ) is comprised of 18 Type B201 FI ip-Flop modu les
and additional B105 Gating Circuits. For multiplication, the MQ initially contains the multipl ier. At the conc lusion of the mu Itipl ication operation. the MQ contains the least sign ificant
part of the product with the most significant part in the AC. For division the MQ initially
contains the least significant part of the dividend. At the conclusion of the division operation
the MQ contains the quotient with the remainder in the AC.

For normal ize operations, once

the number normal izes, the least sign ificant part of the number forms in the MQ.

Information

transfers from and to the MQ by the following methods:
(1) For EAE setup commands, the contents of the AC transfer into the MQ by the AC 1 -+
MQ pulse gating the ACB levels into the MQ.
(2) As part of the division, normal ize, and shift-left operations the contents of the MQ
shift left by the MQRL (MQ rotate left) pulse gating the higher (positional) but lower (in
magnitude) MQ bit into the more significant (in magnitude) MQ bit register.

4-26

PDP-7 MAINTENANCE MANUAL

(3) As part of the multiplication and shift right operations, the MQ shifts right by the
MQRR (MQ rotate right) pulse gating the lower (positional) but higher (in magnitude) MQ
bits into the lesser significant (in magnitude) MQ bit register.
(4)

As part of the division operation, (MQ- MQ), the contents of the MQ are comple-

mented by coincidently applying the 0- MQ and the 1 - MQ pulse to the MQ. The
0- MQ pu Ise when used a lone clears the MQ, and the 1 -.. MQ pu Ise places a Ills in the
MQ.

4.3.3.3

Mu Itiply - The algorithm for mu Itipl ication using the PDP-7 EAE is to sample each bit of the

multiplier starting with the least significant bit and ending with the most significant bit. In the first
step, the least significant bit is sampled. If it contains 1, the multipl icand is added to the partial product. If it contains 0, no action occurs. The second and all succeeding steps occur with the bit located
in the next-to-Ieast sign ificant position wh ich is, after the first step, the present least significant bit.

If its contents are 1, the partial product is added to the mu Itipl icand; then the partial product and the
multiplier are shifted right with the contents of the least significant bit-being lost. If its contents are 0,
the partial product and the multiplier are shifted right. Multiplication is complete when all multiplier
bits are sampled.
In the EAE, the mu Itipl ier is stored in the MQ, the mu Itipl icand is stored in the MB, and the
partial product is developed in the AC and the MQ. For the first multipl ication step, the contents of
MQ17 are sampled. For all succeeding steps, the contents of MQ16 are sampled. The 2s complement
of the number of mu Itipl ication steps is stored in the SC. Multipl ication is complete when the SC overflows.
The EAE performs mu Itipl ication at high speeds. Th is is accompl ished by stopping the computer
tim ing chain wh ich allows the tim ing to be controlled by the sampl ing and sh ifting rates of the internal
logic. Further speed is gained by sampling MQ16 after the first step. This method effectively eliminates
one shift operation.
a. Sample Program
Th is sample program mu Itipl ies 58 by 28 as signed numbers. The two EAE instructions
in this listing are:
ST,

0200

200100

LAC CAND

/LOAD MULTIPLIER

0201

100500

JMS MPY

/LOCATE MULTIPLY SUBROUTINE

0202

200101

LAC PLIER

/LOAD MULTIPLIER

0203

740040

HLT

4-27

PDP-7 MAINTE NANCE MANUAL

MPY

CAND

0500

000202

0501

664000

GSM

/GET SIGN MULTIPLICAND

0502

040505

DAC·+3

/DEPOSIT MULTIPLICAND IN CAND

0503

400500

XCT I MPY

/LOAD MULTIPLIER

0504

657104

MULS

/SHIFT 4 TIMES AC -+ MO, 0 -+AC

0505

000003

MUL TIPLICAND

0506

440500

ISZ PC

0507

620500

JMP I 500

0100

000002

MUL TIPLICAND

0101

000005

MUL TIPLIER

/JUMP TO MAIN PROGRAM

Th is program uses 4-bit reg isters.
0010
0101
0010
0100

MUL TIPLICAND
MULTIPLIER
PARTIAL PRODUCT

PRODUCT

The setup instruction 664000 GSM is used in EAE signed mu Itiply operations to place
the sign of the multipl icand in the I ink with the AC

contain the absolute value of the mu hi-

pi icand. Th is operation is required before transferring AC-+ MB. During the execution of GSM,
a fetch cycle is initiated. The PC increments by 1; the MA contains the contents of PC before
incrementation. The MB contains the GSM instruction, and the AC contains the signed
mu I tipl icand •
(664000)8

MB ....~--

.-EAE--.
Instruction

---.
ACO

LINK

ACO

EAE

-+EAE

~SETUP-""

AC
SIGN

4-28

PDP-7 MAINTENANCE MANUAL

The EAE events during the fetch cycle are (see EAE flow diagram FD-177-0-2):
EAE Flow

EAE T1

NO EAE EVENTS

1'~ EAE· F (IR decoded)

O-STOP SHIFT, O-ADD, 0 -SUB
MB4(1} = ACO- LINK (places multiplicand sign into link)
MB6(1} = ACO-EAE AC SIGN
MB9, 10 , 11(O) = EAE SET UP

NO EAE EVENTS

EAE AC SIGN ¥ LINK- EAE SIGN

NO EAE EVENTS

EAE SETUP = CLR - EAE SIGN, EAE AC SIGN
CLR
SIGN, MUL, DIV, SCOV,
FULL, and NORM

At the cone lusion of th is instruction the AC contains the absolute value of the
multiplicand, and the link contains the multiplicand sign.
MULS 65 7104, AC -MQ, O-AC

AC AC

. - EAE CODE ~

~-+-+~

MQ EAE MQ AC
SIGN

SET MUL
F/F

EAE Flow (Fetch Cycle)
T1

NO EAE EVENTS

1 - EAE • F F/F

0 - STOP SHIFT F/F
O-ADD F/F
0- SUB F/F
OTHER = MB 12-17 .J. SC 12-17

AC1-MQ (multiplier) MQ
O-AC

4-29

Shift 4 times

PDP-7 MAINTE NANCE MANUAL

MB9(0)oMB10(0)-MB11(1)=1 MUL F/F
MUL=l =INHIBIT BREAK REQUEST
EAE AC SIGN ¥ LINK -EAE SIGN

NO EAE EVENTS

SET NORM F/F

The multipl ier is in the MQ, and the sign of the product is in the EAE sign register.
The next instruction fetched conta ins the mu Itipl icand, and an argument fetch cyc Ie is in itiated •
CP

EAE

FETCH '"
T1

O-IR, PC-1M

NO EAE EVENTS

+l-PC
T2

O-MB

O-EAEoF, MULoMQ17(1) = 1- STOP F/F

SAl -+'MB

START MUL ° DIV,

DZM - IR

DZM- IR

FORCE "B" SET

FORCE "EII SET

E ,....
AND
STOP
CPTC

At the conclusion of this instruction the MB contains the multiplicand and (2 ), the
8
accumu lator = 0, and the mu Itipl ier (58) is in the MQ ° The INPUT LOW COUNT increments
the SC by 1 wh ich starts the mu Itipl ication operation °
b ° Example - Mu Itiply 28 x 58
With the CPTC stopped, the tim ing is controlled by the EAE sh ifting and sampl ing
rates_ The initial condition of the registers are as follows: 4-bit AC and MQ registers are
used for the purpose of explanation _
MB
(Mu Itipl icand)
0010

Link
(Sign)
-0-

AC
(Product)
0000

MQ
(Multipl ier)
0101

All sh ifts are to the right, with the Iink
MQ

4-30

PDP-7 MAINTENANCE MANUAL

The SC is preset by MULS as follows:
111 all = - 4
The START MUL DIV pulse initiates the INPUT LOW COUNT which increments the
SC by 1 and samples MQ17 for a 1. Sampling occurs before shifting except for the initial
MQ17 sample. For all further operations, the CPTC is stopped and MQ16 is sampled.
MULS 58 x 28

(4-Bit Registers)

Product
(AC)

Multiplier
(MQ}

Mu Itipl icand
{MQ}

Link

0010

0000

0101

Add 0010
0010

0101
t

Sample
Setp 1

SHR a

0001

0010

0001

0010
t
Sample

Step 2

SHR a

0000

1001

0010

0000

0110

Add 0010
0010

1001
t
Sample

Step 3

SHR a

0001

0101

0010

0001

0100

SHR a

0000

1010

Step 4

Answer = 128
Remember to look back at MQ16 before sh ifting
MQ16(1) ADD then shift

4-31

PDP-7 MAINTENANCE MANUAL

STEP COUNTER
12

1
1
1
1
0

1
1
1
1
1
0

0
1
1
1
1
0

1
0
0
1
1
0

1
0
1
0
1
0

4
Input Low Count
1st Sh ift
2nd Sh ift
3rd Sh ift
4th Sh ift

Note: The timing chain starts when the operation has been completed.
c. Block Logic Discussion
This description is the detailed discussion of the functional operation of the EAE
logic elements during the execution of the MULS instruction 657104 , Refer to drawings
8
BS-D-177-0-4 through 7.
At Tl of the fetch cycle, the MULS instruction is fetched from memory and placed
in the MB.
At T2, the IR decodes bits 0-3 to produce the IA3 and 181 levels (OP code 64).
These levels coincide with the 0 states of the MUL and DIV flip-flops (C24,4) condition
NAND gate (D 17,4) to set the EAE· F fI ip-flop to a 1 •
At T3, the EAE T3 pulse developed at inverter (C31,7) clears the STOP SHIFT, ADD,
and SUB flip-flops (C26,7) to O. Also, the MB-+ SC developed at PA(Cll,5) transfers the
complements of MB bits 12-17 (111011) to the step counter, SC12-17, (C14-C18,5). The
0-+ MQ signal developed at PA(A23,6) clears the contents of the MQ to 0, and MB5 is a 1 •
At T4, the AC-+ MQ signal developed at PA(Cll, 6) transfers the contents of the
AC to the MQ. MB8 is a 1, and the CLA pulse developed at inverter (Dl0,6) clears the AC
to O.
At T5, the EAE T5 signal combined with the MB9(0), MB10(0), and MBll (1) levels
conditions NAND gate (B24,4) to set the MUL fl ip-flop (C24) to a 1. The MUL 1 level generates a MUL· DIV level at NOR gate (D23, 4). Th is level is appl ied to the central processor
interrupt control log ic to prevent a break request from interrupting the EAE operations. Also,
at T5, the EAE T5 level samples the status of the link and the EAE AC sign register for a 1
condition at NAND gates (D25, 4). If a 1 condition is sensed, the EAE sign register is set to a 1 .
At T6 no EAE events occur.
At T7, the T7 signal combines with the EAE. F leve I to set the NORM fl ip-flop
(C25,5) to a 1 •

4-32

PDP-7 MAINTE NANCE MANUAL

At the conclusion of the fetch cycle, the multiplier is in the MQ, the AC is cleared,
and the sign of the product is in the EAE sign register. As indicated in the sample program, the
program proceeds to the next instruction wh ich contains the mu Itipl icand, thus in itiating another
fetch cycle. At Tl, the normal fetch cyc Ie operations occur: The OP code 0

is decoded in the
8
IR, the contents of the PC are transferred to the MA, and the PC is incremented by 1 •
At T2, tf-" T2 signal c .ears the EAE fl ip-flop to 0 and also samples the status of MUL

and MQ17 for a 1. Since the MUL fI ip-flop was set to a 1 in the previous fetch cycle and
MQ17 is a 1, NAND gates (D27,7) condition the STOP SHIFT and ADD fl ip-flops (C26,7) to
the 1 state.
At T3, the T3 signal enables NAN D gate (D23,4) wh ich developes the START MUL·
DIV signal at PA (C23,4). The START· MUL signal triggers the delay (D 19,4) wh ich generates
three signals at PA (B25,4):
(1) The INPUT LOW COUNT which increments the step counter (SC)
(2) The STOP CPTC pulse which stops the computer timing chains, and
(3) The START pulse wh ich starts the multipl ication operation asynchronous
to the CP timing chain.
The START· MUL· DIV signal also generates the CLEAR LINK signal at PA(C3, 6).
The START pulse combined with the SCOV(O) level conditions NAND gate (B29,7) to sample
the states of the ADD and STOP SHIFT fl ip-flops at inverters (B29,7). Since both fl ip-flops
are a 1 (at T2), the RECYCLE signal is temporari Iy inh ibited and an ADD signal is generated.
d. Adder Operation During Multiply
The ADD pulse generated in inverter (B29,7) develops an XOR pulse at PA(A28,6).
The XOR performs MB '¥ AC ->- AC wh ich effectively half adds the MB with the AC. The ADD
pulse, delayed 100 jJsec at delay (A28,6), generates an AC CARRY pulse completing the
addition of the MB into the AC. The delayed ADD pulse also develops a RESET pulse at inverter (C31, 6) wh ich clears the ADD and STOP SHIFT fI ip-flops. When the AC CARRYS are
complete, the CP generates a CRY DET signal. Th is signal gates inverters (B28,6) wh ich generate a RECYCLE pulse. The associated logic at B27 and C25 appl ies only to the adder divide
routine. The RECYCLE pulse at PA(B30,7) generates a SHIFT pulse which shifts the AC and
MQ right one position by the MQRT signal and RAR signal developed at gates (C20,7).
In summary, the above adder sequence completes the in itial multipl ication step wh ich
originated at T2 when MQ17 was sampled. For all further operations MQ16 is sampled at gates
(C29,7). If MQ16 is a 0, neither the STOP SHIFT nor the ADD is set to a 1, and a shift operation occurs. If MQ16 is a 1, both fI ip-flops are set to a 1, and an ADD operation occurs followed by a sh ift •
4-33

PDP-7 MAINTE NANCE MANUAL

4.3.3.4

Divide - The algorithm for division is to subtract and shift left. Division begins with the divisor

in the MB, and the dividend in the MQ. The dividend is subtracted from the divisor. If the result is a
positive number, a 1 is placed in the quotient. If the result is a negative number, a 0 is placed in the
quotient. If the result of the first subtraction is a positive number, divide overflow occurs which stops
the divide operation. If the resu It of the subtraction is a positive number in any cycle but the first, the
dividend is rotated one place to the left with respect to the divisor and the operation continues with
another subtraction. A subtraction with a negative number resu Iting is followed by an addition. The
dividend is then rotated one position to the left and the subtraction is repeated to determine the next bit
of the quotient. At completion of the operation the quotient is in the MQ and the remainder in the AC.
For the EAE, the Iink is sampled.
a. Sample Program
The program I isting contains two EAE instructions, a setup instruction
0501-673000/LMQ
and the arithmetic instruction
0203-645306/DIVS
This program initially loads the dividend into the AC (LAC). The contents of the
AC are transferred to the MQ (LMQ) and the sign of the dividend is tested. If the sign is
negative, the link is set to 1. The divisor is fetched from memory and loaded into the AC
(JMS and LAC), then placed back in memory at the location DIVL. DIVL is the location of
the instruction to be performed immediately following the EAE arithmetic instruction DIVS.
Thus the divisor is in the MB during the execute cycle of the DIVS instruction.
Sample Division Routine
(1 28 "7 58 = 28 )
(1 )

MB
Divisor
58

(2)

ST,

DIV,

AC
REMAINDER

MQ
Dividend
12
8
MQ
QUOTIENT

0500

200100

LAC DIVIDEND

/LOAD DIVIDEND

0501

673000

LMQ

/TRANSFER TO MQ

0502

100200

JMS DIV

0503

200101

LAC DIVISOR

0200

000503

0201

420200

XCT I DIV

0202

040204

DAC IN DIVL

0203

645306

/LOAD DIVISOR
/STORE ADDRESS OF DIVISOR

DIVS,
4-34

PDP-7 MAINTENANCE MANUAL

DIVL,

0204

000005

DIVISOR

0205

440200

INCREMENT STORED PC

0206

620200

EXIT SUBROUTINE

0100

000012

DIVIDEND

0101

000005

DIVISOR

Divide Setup Instruction
MB

LMQ-673000-AC-+ MQ

---.--. -. --.

'--EAE~

ACO

CODE

ACl

LINC MQ

MQ AC

The contents of the AC are transferred to the MQ.
EAE Flow
Tl

NO EAE EVENTS

1-+ EAE • F F/F

0 STOP SHIFT, ADD, SUB F/Fs
MB4(1) = SIGN OF DIVIDEND TO LINK
MB5(l) = 0-+ MQ
MB9, 10, 11 = O-SETUP

MB7(1) = ACl s-+ MQ
MB8(1)

= 0-+ AC

At completion of this instruction, the sign of the dividend is in the link, the dividend is transferred to the MQ, and the AC is cleared.
MB
-"

.-EAE CODE--.

--.

ACO

EAE
SIGN

o
--.
AC

4-35

DIVS

PDP-7 MAINTENANCE MANUAL

EAE Flow
T1

NO EAE EVENTS

1- EAE-F

0- STOP SHIFT, 0 -ADD, 0 -SUB
MB6(1) ACO -EAE AC SIGN
(check sign of divisor)
SETUP = MB12-17 ---SC
(initial ize step counter)

O-AC

MB9(0)-MB10(1): 1- DIV, 1- DIV 1st.
MUL, DIV- = INHIBIT BREAK REQUEST
EAE AC SIGN ¥ LINK - EAE SIGN
(will answer be negative)

NO EAE EVENTS

NORM
The final results are:

AC equals 0; the divisor is in location following instruction

DIVS; the dividend is located in the MQi and the EAE AC sign holds the SIGN.
EAE Flow
T1
T2

0 -+- EAE • F, DIV(l) 1 - SU B, 1-+ STOP SHIFT

MUL V DIV: START MUL, DIV,
O-L, DZM-IR, FORCE E SET

Now in execute cycle,

timing chain stops at T7, MS

ind icates BVF

T7
Final Results
(1) Allregistershave been set up
Divisor
MB
001 01

Sample

-L-

Remainder
AC
00000

Dividend
MQ
01010

(2) If the I ink is a 0, subtract, then sh ift left_
(3) If the I ink is a 1, add, then sh ift left.
4-36

PDP-7 MAINTENANCE MANUAL

(4) Always sample the link before shifting.
(5) On the first divide the MB must be greater than the AC.
*Registers

rGJ~1 0

1.-1

SHL

STEP COUNTER

MQ Left
Only

1
1
1
1
1
1
1
0

1
1
1
1
1
1
0

0
0
0
1
1
1
1
0

0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0

-6
Input Low Count
1st Sh ift
2nd Sh ift
3rd Sh ift
4th Sh ift
5th Sh ift
6th Sh ift

Example 128 -:- 58 = 28

00101

0
CMLl

1st divide, sample I ink,
sample I ink before sh ift,
00101

Accumu lator

Link

Divisor

CMLO
CML 1
SHL 1

AC
CMA
Add
ACO CRY
CMA

Dividend

00000
1111 1
00101
00100
11011
10110

01010
01010

10110
00101

10101

nmT

10101
01011

01010
10101

Note: ACO CRY = CML
Step 1
00101
Add
Sample link
Sh ift left

10111

*Five-bit register for explanation only.

4-37

PDP-7 MAINTENANCE MANUAL

Div isor

Link

Accumu lator

Step 2
00101

10111
00101
11100
11000

01011

11000
00101

10111

l1TOf

10111
01111

Add
Sample link
Sh ift left
Step 3
00101
Add
Sample link
Sh ift left

11011

Step 4
00101
Sample I ink
Sh ift left

1
1
CMLO
0

Step 5
MB
00101

L
0

CML 1
1
CMLO
CML 1

Subtract

Sample link
Sh ift left
MQ only
FULL (1)
Last ADD

1
1
CMLO

Dividend

Add
ACO CRY

11011
00101
00000
00000

01011
10111

01111
01111
11110

00000

MQ
1111 0

CMA
Ado
ACO CRY
CMA

111 11
00101
00100
11011

11110

ACO CRY

11011
00101
00000

11101
11101

Function Complete Complement MQ
0
L

00000
REMAINDER

00010
QUOTIENT

Start central processor time chain and complete rest of program.

b. Logic Block Discussion
Th is description is the detai led discussion of the functional operation of the EAE
log ic elements during the execution of the DIVS instruction 645306.
At Tl of the fetch cycle, the DIVS instruction is fetched from memory and placed in
the MB.

4-38

PDP-7 MAINTENANCE MANUAL

At T2, MB bits 0 through 3 are decoded in the IR to produce the IA3 and IBl levels.
These levels, coincident with the 0 states of the DIV fl ip-flop (C24,4), condition NAND gate
(D17,4) to set EAE·F flip-flop to 1.
At T3, the EAE T3 timing pulse clears the STOP SHIFT, ADD, and SUB flip-flops
to O. Also at T3, if ACO is a 1 and MB6 is a 1, NAND gate output (D25,4) sets EAE AC SIGN
reg ister to 1. (The sign of the quotient is in the EAE sign reg ister .) The contents of MB12-17
are transferred to SC11-17 by the MB -SC signal generated at PA (D13,5).
At T4, when MB8=l, the CLA pulse developed at inverter (D16,6) clears the AC.
At T5, the EAE T5 pulse with the MB9(0) and MB10(0) levels conditions NAND
gate (D24,4) set the DIV fI ip-flop (C24,4) to 1. The 1 level of the DIV fI ip-flop (C24,4) sets
the DIV FIRST flip-flop (C14,7) to a 1. Also at T5, the EAE sign register (C24,4) is set to 1

if either the I ink or the EAE AC sign is a 1 •
At T7, the NORM flip-flop is set to 1. At the conclusion of the DIVS instruction,
the AC is cleared, the divisor is in the location following DIVS, the dividend is in the MQ,
and the EAE sign reg ister contains the sign of the quotient.
The next instruction is fetched from memory (DIVISOR) and a second fetch cycle is
in itiated •
At T2, the EAE·F F/F (C26,4) is reset to O.
At T3, a START MUL· DIV signal is generated.
c. Subtract (See figure 4-4)
The SUB signal developed at gate (B29,7) generates the ADD 1 pulse at PA (A28,6).
The ADD 1 pulse conditions inverters (D1 0,6) to produce the CMA and CML signals. These
signals respectively complement the AC and the I ink. The ADD 1 pulse also conditions the
COMP flip-flop to a 1 and delayed 100 !-,sec at delay (A26,6) generates the ADD 2 pulse.

4-39

PDP-7 MAINTENANCE MANUAL

RESET DIV F / F
TO 0

COMPLEMENT AC

YES
COMPLEMENT MQ

RESET LINK TO 0

INCREMENT
SC+l

SAMPLE 2 PULSE

Figure 4-4

EAE Divide Flow Diagram
4-40

PDP-7 MAINTENANCE MANUAL

ADD PULSE 1

COMPLEMENT

LINK

MB ¥

---+ AC

RESET: ADD
SUB F/F'.
STOP SHIFT

COMPLEMENT
AC

Figure 4-4

EAE Divide Flow Diagram (continued)
4-41

PDP-7 MAINTENANCE MANUAL

RESET ADD. SUB
STOP SHIFT F IF'S

OVERFLOW

Figure 4-4

EAE Divide Flow Diagram (continued)

The ADD 2 pulse generates the XOR signal at PA(A28,5) which logically performs
MB ¥ AC-+ AC. The pulse delayed 100 !-,sec by delay (A28,6 generates the CRY which propagates AC carries.

If ACO CARRY is a 1, the link is complemented again. ADD pulse 2 also

resets the ADD, SU B, and STOP SHIFT fI ip-flops. Once the carries are completed, the CP
generates a CRY DET pulse. The CARRY DET pulse develops the ADD3 signal at PA(A27,6).
Th is signal strobes the COMP fI ip-f1op output gates (B28, 6) to generate the CMA and CML
levels at inverters (D1 0, 6) wh ich recomplement the AC and I ink and generates the ADD 4
pu Ise.
The ADD 4 pulse senses the status of the I ink and DIV 1 ST fl ip-f1op (C14, 7) at
NAND gate (B26, 7). If the I ink is a 1 on the first div ision step, the SCOV fI ip-flop (C25, 5)
is set to 1 and the EAE divide operation stops. The CPTC starts again and the overflow condition is indicated. The ADD 4 pulse also triggers two delays (A27 and A25,6) to reset the
COMP flip-flop (C25,6) and to generate the RECYCLE pulse at gate (B28,6) if the SCOV
level is a O.

4-42

PDP-7 MAINTENANCE MANUAL

In summary, if the Iink is a 1 when sampled, the subtract routine is in itiated. The
AC and L are complemented, the MB is added to the AC. If add overflow occurs, the L is
complemented again. The AC and I ink are restored. On the first divide, the I ink is resampled.

If it is a 1, divide overflow occurs.

This indicates that if the divisor is greater than the divi-

dend, rescal ing is requ ired.
d. Shift Divide
Once the ADD or SUB operations are complete, the RECYCLE pulse starts the SHIFT
operation. The RECYCLE pu Ise develops the SHIFT signal at PA(B30,7).

The SHIFT signal

conditions gate (023,7) to shift the AC left with the RAL pulse developed at gate (C20,7), to
sh ift the I ink left with the LEFT ROTATE signal developed at gates (09,7), and the MQ left
with the MQ LFT signal developed at gate (C20,6). The SHIFT signal resets the DIV FIRST
fl ip-flop (C14,7) to 0, and increments the SC one count at gate. (018,5). The SHIFT signal is
also applied to delay (031,7 and B30,7). Del~y (031,7) relays the SHIFT pulse 35 psec to
develop the SAMPLE pulse at PA(D31,7). The SAMPLE pulse senses the status of the link at
gates (028 and 024,7) to set either the ADD or SUB flip-flops (C26,7). Delay (B30,7) delays
the SHIFT pulse 100 pseci then strobes gates (B29,7) to initiate the next ADD or SUB operations.
e. Divide Overflow
Divide overflow occurs when the SCOV flip-flop (C25,5) sets to 1. This indicates
that all division steps are complete. The OVFLO pu Ise conditions NAND gate (028,7) to
trigger the one-shot de lay (A30, 7).

De lay (A30,7) produces a 350-psec div ide end pu Ise at

PA(C23,7). The pu Ise strobes the following gates:
(1) Gate (D15,7) if EAE AC sign is a 1, the AC is complemented by the CMA pulse.
(2) Gates (A22,7) if EAE sign is a 0, the MQ is complemented by the 1- MQ and
0-- MQ pu Ises •
(3) Gate (B27,7), the DIV fI ip-flop is reset by the 0

DIV pu Ise •

(4) Gate (D 12,8) if the DIV FIRST fI ip-flop is 0, the I ink is reset by the 0

4.3.3.5

L pu Ise •

Norma Iize - Th is command is used as part of the conversion of an integer into a fraction and

an exponent for use in floating-point arithmetic. The algorithm for normal ize is to shift the AC and MQ
left unti I the contents of ACO do not equal the contents of ACl (ACO"l AC1). For positive numbers ACO
is (0) and ACl is (1). For negative numbers ACO is (1) and AC1 is (0). For signed normalized numbers
(NORMS) the sign of the number is dupl icated in the I ink. In other words, after normal ization L ::: ACO.
The link fills MQ17 and does not change.
4-43

PDP-7 MAINTE NANCE MANUAL

For normal ized numbers, the binary point of the fraction is assumed to be between ACO and
AC1, the mantissa of the fraction is from AC1 to MQ17, the sign in ACO, and the value of the exponent
in the step counter (SC).
SC12-17
Exponent in
excess 44 code
ACO

[lOST]

AC1-AC17

MQO-MQ17

+--1 SIGN 1MANTISSA I--~--I MANTISSA I" I
Binary Po int
The number in the SC at normal ization is actually the 2s complement of the exponent (- N)

plus the characteristic (S). The characteristic is a number equ ivalent to the total number of bit positions
in the AC + MQ (36

or 44 ). As part of the NORMS instruction (44 ) is loaded into the SC to establ ish
8
10
8
the exponent in excess 44 code. Th is means that the exponential range of the fraction (mantissa) is from
35
0
2 to 2
when normal ized. For example, if the integer + 3 is stored in bits MQ16 and MQ17 and we
wish to convert th is to a fraction and exponent, the following steps are requ ired:
ACO

AC17

MQO

MQ16 MQ17

ILOSTI~I-o-----o~I~~-I~o----o~1~1~lt~~
a. Load a number in the SC equal to the maximum number of shifts (S) (44 ).

b. Place the binary point between ACO and AC1 •
c. Sh ift left unti I MQ16 is sh ifted into ACO.
d. Count the number of sh ifts performed (N).
e. Subtract the characteristic (44 ) from the number of shifts performed to get the exponent

of the fraction.
The number to be normal ized is loaded into the AC or MQ and the NORMS instruction is
fetched from memory.
M B REGISTER

640444
8

--.

NORMALIZE

EAE INSTRUCTION
~

4--

4-44

0
0
0
1
0
._STEP COUNTER 448 (36 COUNTS)

PDP-7 MAINTENANCE MANUAL

EAE Flow (Fetch Cycle)
T1

NO EAE EVENTS

1- EAE·F

MB9(1), MB10(0), MB11 (0) == OTHER
OTHER == MB12-17

NO EAE EVENTS

MB8(0). NORMALIZED == 0 -+ FULL

MB9( 1) == START SHIFT

SET NORM
STOP CPTC

ACO

AC1

I----_MQ_----II~ I 61
a. Detai led Block Diagram Discussion
At T6, the START SHIFT signal developed at NAND gate (D24,4) (EAE.F and MB9
are 1) in itiates the normal ize operation. The START SH 1FT triggers 100-nsec de lay (D 19,4)
wh ich increments the SC(INPUT LOW COUNT), stops the computer tim ing chain (STOP CPTC),
and starts the sampling operation (START pulse at NAND gate B29,7).
At T7, the NORM flip-flop (C25,5) is set to 1 and the first normalizing sample occurs
at NAND gates (D 16,5). If the AC is already normal ized, gate (D15,5) sets the SCOV fI ipflop to 1 wh ich inh ibits the START pu Ise at gate (B29,7) from starting the sh ift operation.
All shifts are to the left for normalizing. The START pulse strobes gate (B29,7). If
the STOP SHIFT fl ip-flop is 0, a RECYCLE pu Ise is developed at gate (B29,7). The RECYCLE
pulse developes the SHIFT pulse at PA(B30,7), and the SHIFT pulse develops the RAL signal
at gate (D22, pins K and L), and the MQ LFT signal at gate (D22, pins P and N, 7). The AC
and MQ are shifted left one position. The SAMPLE pulse developed at delay (D21,7) senses
the status of NAND gates (D29,7). If either gate is a 1, the STOP SHIFT fl ip-flop sets to 1
inhibiting the RECYCLE pulse from initiating another shift except the shift operation already
in progress.

4-45

PDP-7 MAINTE NANCE MANUAL

CHAPTER 5
MAINTENANCE

5.1

INTRODUCTION
Basically, the PDP-7 maintenance system is directed to the module-replacement level. Thus,

downtime caused by malfunctions can be minimized and the system more readily kept on-line. The
maintenance effort is divided into preventive and corrective catagories, for descriptive convenience.
Preventive maintenance consists of routine periodic checks such as visual inspections, standard
maintenance procedures involving cleaning and lubricating, and occasional marginal-checking to expose
weakening conditions before they become malfunctions. Periodic maintenance also requires use of the
standard testing equipment Iisted in tabl e 5-1 •
When a malfuction occurs, corrective maintenance is instituted to isolate the problem and make
proper adjustments or replacements. Primarily this involves the use of diagnostic routines designed to test
the functional units of the system. Strictly speaking, categorizing these primary areas does not imply
complete independence. The prodedures and techniques of periodic checking can aid and are indeed
necessary in mal function tracing; and conversely, intermittent error conditions occurring during system
operations can be caused to occur continuously by applying marginal conditions. In this way, a proper
diagnostic can then be run to isolate and identify the problem.
Diagnostic routines are provided on perforated paper tape to be mounted and executed as
described in chapter 2, Operations, and documentation listed in table 1-3 of chapter 1, is provided for
each available routine.

5.2

MAINTENANCE EQUIPMENT REQUIRED
Maintenance activities for the PDP-7 system require availability of the standard test equipment

and special material listed in tabl e 5-1 , a Iso standard hand tools, c leaners, test cabl es and probes.

5-1

PDP-7 MAINTE NANCE MAN UAL

TABLE 5-1 MAINTENANCE EQUIPMENT
Equipment

Manufacturer

Designation

Multimeter

Triplett or Simpson

Model 630-NA or 260

Osci Iloscope

Tektronix

Type 547

Plug-in-Unit

Tektronix

Type CA

Clip-on Current Probe

Tektronix

Type P6016

Xl0 Probe

Tektronix

P6008

Recessed tip, 0.065 inch
for wire wrap terminals

Tektronix

206-052

Current Probe Ampl ifier

Tektronix

Type 131

Hand Unwrapping Tool

Gardner-Denver

500130

Hand-Operated Wire-Wrap
Tool with a 26263 bit for
24 AWG Wire and 18840 Sleeve

Gardner-Denver

14H1C

FLIP CHIP Module Extender*

DEC

Type W980

Paint Spray Can*

DEC

DEC Blue 5150-S65

Air Fi Iter*

Research Products Corp.

EZ Clean 2-inch Type MY

Fi Iter-Kote*

Research Products Corp.

By Name

Documents and Test Tapes
Teleprinter Input/Output Test*

DEC

Digital-7-50-M

Clock Interrupt Test Program*

DEC

Digital-7-51-M

CONTEST 11*

DEC

Digital-7-52-M

Reader and Punch Test *

DEC

Digital-7-53-M

Maindec 701 (Instruction Test)*

DEC

Digital-7-54-M

Maindec 703 (Checkerboard)*

DEC

Digital-7-55-M

Maindec 702 (Address Test)*

DEC

Digital-7-56-M

Maindec 710 (RPB Test)*

DEC

Digital-7-57-M

* One is suppl ied with the equipment

5-2

PDP-7 MAINTENANCE MANUAL

5.3

MODULE HANDLING
Turn off all power before extracting or inserting modules. Access to controls on the module

for use in adjustment, or access to points used in signal tracing can be gained by removing the module
(use a straight, even pull to prevent twisting of the printed-wiring board), connecting a Type W980
FLIP CHIP Module Extender into the vacated module connector in the mounting panel, and then reinserting the module into the extender.

5.4

MAINTENANCE CONTROLS AND INDICATORS
In addition to the controls and indicators on the operator console, the indicator panel, and

on the Teletype unit (described in chapter 2); maintenance operations use controls and indicators on the
marginal-check panel (mounted at the top of bay 3, at the front of the computer) and on the Type 832
Power Control. Table 5-2 describes the function of these controls and indicators, and figure 5-1 shows
the marginal-check panel.

TABLE 5-2 MAINTENANCE CONTROLS AND INDICATORS
Function

Control or Indicator

Marginal-Check Panel
Voltmeter

Indicates the output voltage of the marginal-check power
suppl y in either polarity.

Toggle switches
(four)

The bottom switch applies a -10 marginal-check voltage to
the Teletype control in the up position. The second switch
from the bottom applies -15 marginal-check voltage to the
Teletype control in the up position. The other two switches
are not used.

Selector switch

Controls the output of the marginal-check power suppl y. In
the +10MC position, the output is positive and is connected
to the orange +10MC connector. In the -15MC position, the
output is negative and is connected to the green -15MC connector. The center position is off and disconnects the output
from the marginal-check power supply.

5-3

PDP-7 MAINTENANCE MANUAL

TABLE 5-2 MAINTENANCE CONTROLS AND INDICATORS (Cont)
Control or Indicator

Function

Elapsed time meter

Indicates the total number of computer operating hours. This
unit of measure is instrumental for determining preventive
maintenance schedules by recording time between similar
malfunctions, etc.

Control knob

Controls the ourput of the marginal-check voltage to any
level between 0 and 20v.
Type 832 Power Control

Circuit breaker

Protects the computer circuits from overload due to failure
of the computer power circuits.

REMOTE/OFF /LOCAL
switch

Allows control of the computer primary power from the rear of
the machine during maintenance. In the REMOTE position,
the lock and POWER switches on the operator console control
application and removal of computer power. In the OFF
position the computer is de-energized, regardless of the
position of switches on the operator console. In the LOCAL
position the computer is energized regardless of the position
of operator console switches or door interlocks.

MEM. POWER switch

Controls the appl ication and removal of operating voltages
for the memory circuits.

•
•

+ lOMe

Figure 5-1

Marg inal-Check Panel

5-4

PDP-7 MAINTENANCE MANUAL

5.5

PREVENTIVE MAINTENANCE
Preventive maintenance consists of tasks performed periodically during operating time of the

equipment to ensure satisfactory working condition. Performance of these tasks forestalls failures caused
by progressive deterioration or minor damage, which if not corrected causes eventual down-time. Data
obtained during the performance of each task should be recorded in a log book. Analysis of this data
indicates the rate of circuit operation deterioration and provides information for determining when components should be replaced to prevent fai I ure of the system.
Preventive maintenance tasks consist of mechanical checks, i.e. , cleaning and visual inspections; marginal checks, which aggravate border-line circuit conditions or intermittent failures for
detection and/or correction; and checks of specific circuit elements such as the power supply, sense
ampl ifiers and master sl ice con.trol, and memory selectors. All preventive maintenance tasks should be
performed on a schedule establ ished by conditions at the installation site. The most important schedule
to maintain is that of the mechanical checks, which should be performed monthly or as often as required
to allow efficient functioning of the air filter, thus avoiding machine failures caused by overheating due
to dirty air filters. All other tasks should be performed on a regular schedule, at an interval determined
by the reliability requirements of the system. A typical recommended schedule is every 600 equipment
operating hours or every four months, whichever comes first.

5.5. 1

Mechanical Checks
a. Clean the exterior and the interior of the equipment cabinet using a vacuum cleaner or
clean cloths moistened in nonflammable solvent.
b. Clean the air fil,ters of the bottom of the cabinets. Remove each filter by removing the
fan and housing, held in place by two knurled and slotted captive screws, and wash in soapy
water and dry in an oven or by spraying with compressed gas. Spray each filter with FilterKote (Research Products Corporation, Madison, Wisconsin).
c. Lubricate door hinges and casters with a light machine oil, wiping off excess oil.
d. Repaint any scratched or corroded areas with DEC blue tweed paint number 5150-565.
e. Inspect all wiring and cables for cuts, breaks, fraying, wear, deterioration, kinks,strain.
and mechanical security. Tape, solder, or replace any defective wiring or cable covering.
f. Inspect the following for mechanical security: keys, switches, control knobs, lamp assemblies, jacks, connectors, transformers, fans, capacitors, elapsed time meter, etc.
Tighten or replace as required.

5-5

PDP-7 MAINTENANCE MANUAL

g. Inspect all module mounting panels to assure that each module is securely seated in its
connector.
h. Inspect power supply capacitors for leaks, bulges, or discoloration. Replace any capacitors giving these signs of malfunction.

5.5.2

Power Suppl y Checks
Perform the power supply output checks described in table 5-3. Use a multimeter to make the

output voltage measurements with the normal load connected, and the oscilloscope to measure the peakto-peak ripple content on all dc outputs of the supply. The +10 and -15v supplies are not adjustable
therefore, if any output voltage or ripple content is not within specifications, consider defective the
power supply giving these indications and initiate troubleshooting procedures. Refer to the engineering
drawing listed in the table.

TABLE 5-3 POWER SUPPLY OUTPUT CHECKS
Measurement
Terminals at
Power Supply
Output

Nominal
Output
(vdc)

Acceptable
Output
Range (v)

Maximum
Output
Current
(amp)

Maximum
Peak-to.., Peak
Output Ripple (v)

Type 728 Power Supply Drawing (RS-B-728)
Red (+) to
Yellow (-)

+10

+9.5 to 11 .5

7.5

0.7

Yellow (+) to
Blue (-)

-15

- 14 • 5 to 16 .5

8.5

0.4

Type 778 Power Supply Drawing (RS-B-778)
Red (+) to
Blue (-)

-15

- 14 • 5 to 16 .5

8.5

0.6

Type 779 Power Supply Drawing (RS-B-779)
Orange (+) to
Yellow (-)

+10

+9.6 to 11 .0

7.5

1 .0

Yellow (+) to
Blue (-)

-15

- 14 • 5 to 16 • 0

8.0

0.4

Red (+) to
Yellow (-)

+15

+14.5 to 16.0

7.5

1 •1

Yellow (+) to
Green (-)

+15

+ 14 • 5 to 16 • 0

7.5

1•1

5-6

PDP-7 MAINTENANCE MANUAL

Check the operation of the varible-output Type 738 Power Supply which produces the marginalcheck voltages. With all of the normal/marginal switches in the normal (down) position, make the
following measurements at the color-coded connector at the right side of any convenient module mounting
panel:
a. Connect a multimeter between the yellow (-) and black (+) terminals; set the +1 OMC/OFF /
-15MC switch to the -15MC position, and turn the control knob clockwise to assure that the
supply can produce at least -20v (as indicated on the multi meter) • Record the indication given
on both the marginal-check voltmeter on the panel and on the multimeter. These indications
should be equal, ± 1v. Connect the osci Iloscope to the yellow terminal, and measure the
peak-to-peak repple content to assure that it is no more than 1 .Ov. Turn the control knob
fully counterclockwise; set the +1 OMC/OFF /-15MC switch to the OFF position, and disconnect the multimeter and oscilloscope.
b. Connect the multimeter between the green (+) and black (-) terminals; set the +10MC/OFF/
-15MC switch to the +1 OMC position, and turn the control knob clockwise to assure that the
supply can produce at least +20v. Turn the control knob fully counterclockwise, set the
+10MC/OFF/-15MC switch to the OFF position, and disconnect the multimeter.
The Type 739 Power Supply output is not measured during this check, since it is monitored and
adjusted during the memory current check.

5.5.3

Marginal Checks
Marginal checking util izes the Maindec diagnostic programs to test the functional capabil ities

of the computer with the module-operating voltages biased above and below the nominal levels. Biasing
the operating voltages aggravates borderline circuit conditions within the modules to produce failures
detected by the program (see description of diagnostics, paragraph 5.6. 1). Upon error detection the
program usually provides a printout or visual indication which aids in locating the source of the fault,
and halts. Therefore, replacement of modules with marginal components is possible during scheduled
preventive maintenance.
The biased operating voltages at which circuits fail are recorded in the maintenance log. By
plotting the bias vol tages obtained during each scheduled preventive maintenance, progressive deterioration can be observed and expected fai lure dates can be predicted, thus providing a means of planned
replacement. These checks can also be used as a troubleshooting aid to locate marginal or intermittent
components, such as deteriorating transistors.
Raising the operating voltages above +10v increases the transistor cutoff bias that the previous
driving transistor must overcome, therefore low-gain transistors fail. Lowering the bias voltage below+10v
5-7

POP-7 MAINTENANCE MANUAL

reduces transistor base bias and noise rejection, thus providing a test to detect high-leakage transistors.
Lowering this voltage also simulates high-temperature conditions (to check for thermal run away). Raising
and lowering the -15v supply increases and decreases the primary collector supply voltage for all modules
and so affects output signal voltage.
Since the marginal voltages attainable vary for different circuit changes and/or system configurations, determine the expected marginal-check voltages for a specific system from the initial factory
test records and any subsequent test records in the maintenance log. A record of margins obtained at the
factory for a specific system is provided and serves as a base for all preventive and corrective maintenance
procedures.
Margins decrease with time and normal circuit operation deterioration, but this decrease does
not affect reliable operation of the machine until there is little or no margin at all. The normal slow
rate of margin decay can be used to predict the time at which the system should be examined to prevent
sudden failure; margins do provide a measure of circuit performance and can be used to certify correct or
defective operation.

CAUTION

00 not increase the -15v margin beyond -18v. Failure to
observe this precaution may cause serious damage to the logic
elements •

Marginal-check voltages are suppl ied to the various sections of the processor through connections made to the module connectors in each mounting panel. Each marginal-check voltage may be
adjusted throughout the range of 0 to 20v by means of the control knob and voltmeter located on the
marginal-check control panel. The selector switch on this panel selects either the +10 or the -15
marginal-check voltage. Power supply leads to the module connectors in the mounting panels are colorcoded as follows:
Orange

+ 1Ov marginal-check supply

Red

+lOv normal power supply

Black

Ground

Blue

-15v normal power supply

Green

-15v marginal-check supply

Marginal-check and normal supply voltages are distributed to each of two module rows in each mounting
panel through four SPOT switches on the marginal-check panel of each assembly.

There are two positions

for each SPOT switch: normal (down) and marginal-check (up). Therefore the modules in one row may
be marginally-checked, all other rows maintaining normal voltage. In each row the upper switch controls

5-8

PDP-7 MAINTENANCE MANUAL

the +1 Ov supply and the lower controls the -15v suppl y (with mounting panel viewed from the connector
side and switches on the left).
To perform the checks:
a. Assure that all normal/marginal-check switches on each module mounting panel are
in the normal (down) position (normal +1 Ov and -15v power suppl ies are being used).
b. Set the +10MC/OFF/-15MC selector switch on the marginal-check control panel to
the +1 OMC position.
c. Adjust the output of the marginal-check power supply so that the marginal-check
voltmeter indicates 1Ov.
d. Set the +10 normal/marginal switch for the first row to be checked to the marginalcheck (up) position.
e. Start computer operation in a diagnostic program or routine which fully uti I izes the
\

circuits in the row to be tested. If no program is suggested by the normal system application, select an appropriate Maindec program from table 5-4. To completely test the
PDP-7, all Maindec programs listed in table 5-4 should be performed at elevated and
reduced voltages for each supply terminal (+10, -15) and for each row indicated in the
table.

f. Decrease the marginal-check power supply output until normal system operation is
interrupted, and record the marginal-check voltage. At this point marginal transistors
can be located and replaced, if desired. Readjust the marginal-check power supply
output to the nominal +1 Ov level.
g. Restart computer operation. Increase the marginal-check supply output until normal
computer operation is interrupted, at which point record the marginal-check voltage.
Again it is possible to locate and replace transistors. Readjust the marginal-check power
supply to the nominal +lOv level.
h. Return the normal/marginal switch to the normal (down) position.
i. Repeat steps d through h for each of the other rows to be checked by biasing the + 1Ov
line.
j. Set the +10MC/OFF/-15MC selector switch on the marginal-check power supply to
the -15MC position and adjust the output until the marginal-check voltmeter indicates
15v.

5-9

PDP-7 MAINTENANCE MANUAL

k. Set the -15 normal/marginal switch to the marginal-check (up) position for the first
row to be checked; then repeat step e.

I. Repeat steps f and g, readjusting the marginal-check power supply to the nominal -15v
level at the end of each step. Return the normal/marginal switches to the normal (down)
position.
m. Repeat steps j through I for each other row to be tested by biasing the -15v line.
n. Set the +1 OMC/OFF /-15MC selector switch to the OFF position.

5.5.4

Memory Current Check
Measure the read/write and inhibit currents in the core memory. These currents should equal

the values specified on the memory array label (approximately 330 ma and 290 ma, respectively). This
label indicates the optimum memory setting determined at the factory. Allow the equipment to warm up
for approximately 1 hr before making measurements. Whenever possible this check should be performed
0

at an ambient temperature of 25 C. Compensate measured read/write and inhibit currents by subtracting
0

1 ma for every degree of ambient temperature above 25 C. (Add 1 ma for each degree below 25 C.)
The memory current check and sense ampl ifier check procedures must not be performed when the equip0

ment temperature is below 20 C.
Measure the read/write current using the oscilloscope and clip-on current probe at the read
side of a fully selected drive I ine of the X and Y axis G202 Memory Selector Switch. The READ terminals are either Land P, or M and N of a G202 module (refer to the G202 module schematic). Synchronize the oscilloscope with the negative transition of the READ signal found at location 1 B202H. Adjust
the read/write current to 330 ma or to the value specified on the memory array label by rotation of R16
in the GaOa read/write power supply control module.
In a similar manner, measure the inhibit current by connecting the clip-on current probe at
a proper terminal of the inhibit connector located at 1 B10. See drawing G201 for the appropriate inhibit terminal. Synchronize the oscilloscope on the negative transition of the INH(B) line found at
location 1 B10J. Adjust the inhibit current to 290 ma or to the value indicated on the memory array label ~
To obtain consistent measurements, position the current probe to indicate read current as a negative pulse,
and write and inhibit currents as positive pulses as displayed on the oscilloscope. Make all current
amplitude measurements jl'st before the knee in the curve of the trailing edge of a pulse.
read/write currents are me~sured from base I ine to peak amplitude, not from peak to peak.

5-10

Note that

TABLE 5-4

Diagnostic (MAINDEC) Test

Mounting
Panel
Row
Tested

MARGINAL TEST PROGRAMS

Clock
Interrupt
Test
Digital-7-51-M

Memory
Checkerboard
Test 703
Digital-7-55-M

CP
1C

+10

CP
1D

+10

Address
Test 702
Digital-7-56-M

Contest II

Reader and
Punch Test

Tel eprinter
Test

Digital-7-52-M

Digital-7-53-M

Digital-7-50-M

"o
"

+10, -15

.........

CP
1E

+10

~
Z

+10, -15

--I
(J')

CP
1F

»
z

+10, -15

()

CP
1H

*
**
+10, -15

+10, -15

CP
1J

+10, -15

CP
1K

+10, -15

CP
1L

+10, -15

CP
1N

*
**
+10, -15

+10, -15

CP
1P

**
*
+10, -15

+10, -15

* This check made with third (from the top) toggle switch on marginal-check panel in the ON (up) position.
**This check made with bottom toggle switch on marginal-check panel in the ON (up) position.

»
z
c
~

+10, -15

TABLE 5-4 MARGINAL TEST PROGRAMS (continued)
Mounting
Panel

Diagnostic (MAINDEC) Test
Memory
Checkerboard
Test 703
Digital-7-55-M

Digital-7-56-M

MEM
1A

+10

MEM
1B

+10

MEM
1H

+10

Row
Tested

Clock
Interrupt
Test
Digital-7-51-M

Address
Test 702

Contest II

Reader and
Punch Test

Digital-7-52-M Digital-7-53-M

Teleprinter
Test
Dig i ta 1-7-50-M

'"'C

'"'C
I

"'J

MEM
1J

+10

~
Z

+10

-I

DS
2A

**
*
+10, -15

+10, -15

()

DS
2B

**
*
+10, -15

+10, -15

DS
2C

**
*
+10, -15

+10, -15

Reader/Punch 3A

*
**
+10, -15

+10, -15

*
**
+10, -15

+10, -15

Reader/Punch 3B

Teletype Control

**
*
+10, -15

Teletype Control

* This check made with third (from the top) toggle switch on marginal-check panel in the ON (up) position.
** This check made with bottom toggle switch on marginal-check panel in the ON (up) position.

*
**
+10, -15

+10, -15

»
z
c
»
.--

PDP-7 MAINTENANCE MANUAL

5.5.5

Sense Ampl ifier Check
The GOOl Sense Amplifier (SA) modules are adjusted using marginal-checking techniques.

Perform the marginal checks using the Memory Checkerboard Program, Maindec 702. See table 5-4 for
marginal-power supply used, and set the SPDT switches accordingly. Check and adjust each SA circuit
so that approximately equal positive and negative margins can be obtained, using the +10v marginal power
supply.
Sense amplifiers are located at lH and lJ, 1-19. The master slice control is locoted at 1H20.

5.6

CORRECTIVE MAINTENANCE
Should a malfunction occur, the condition should be analyzed and corrected as indicated in

the following procedures.

No test equipment nor special tools are required for corrective maintenance

other than a broad bandwidth oscilloscope and a standard multimeter. However, a clip-on current probe
such as the Tektronix Type P6016 with a Type 131 Current Probe Amplifier is very helpful in monitoring
memory currents. The best corrective maintenance tool is a thorough understanding of the physical and
electrical characteristics of the equipment. Persons responsible for maintenance who are thoroughly
familiar with the system concept, the logic drawings, operation of specific module circuits, and the
location of mechanical and electrical components can readily interpret diagnostic routine printouts for
isolating malfunctions.
Diagnosis and remedial action for a fault condition usually proceed by the following steps:
a.

Preliminary investigation: gather all information to determine the physical and electrical

securi ty of the computer.
b. System troubleshooting: define the error by locating the fault to within a module through
use of diagnostic routines, control panel troubleshooting, signal tracing, or aggravation
techniques.
c. Replace defective module or modules to get the system on-I ine.
d. Log entry to record pertinent data.
Circuit troubleshooting to locate defective parts within a module and repairs to replace or
correct the cause of the circuit malfunction can proceed after the system is again operable. Reparied
modules should be subjected to validation tests to assure that the fault has been corrected.
Before commencing troubleshooting procedures record all unusual functions of the machine
prior to the fault and all observable symptoms. In addition, note the program in progress, condition of
operator console indicators, etc. This information should be referenced to the maintenance log to determine whether this type of fault has occurred before or if there is any cyclic history of this fault, and to
ascertain how the condition was previously corrected.
5-13

PDP-7 MAINTENANCE MANUAL

When the entire machine fails, perform a visual inspection to determine the physical and
electrical security of all power sources, cables, connectors, etc. Assure that the power supplies are
working properly and that there are no power short circuits by performing the Power Supply Checks as
described under Preventive Maintenance. Check the condition of the air filter in the bottom of the
cabinet. If this filter becomes clogged, the temperature within the cabinet might rise sufficiently to
cause marginal semiconductors to become defective.

5.6.1

Maindec Diagnostic Programs
Maindec routines are diagnostic programs designed to exercise or test specific functions within

the computer system, and are avai lable as perforated paper program tapes in read-in mode format. A
detailed description of the program contained on tape, procedures for using the program, and information
on analyzing the program printout accompanies each tape. These programs isolate the problem to a
major functional unit but not to the individual module level. However, examination of the printout,
observation of panel I ight conditions, and knowledge of the contents of the logic diagrams allow rnainteance personnel to establish the particular module at fault.
The following paragraphs briefly summarize the function of each basic maintenance routine for
testing the I/O functions of the PDP-7 system. Other test routines are available for optional equipment
(see complete PDP-7 Program Listing).
a. Teleprinter Input/Output Test - (Digital-7-50-M)
Tests the input and output functions of the teleprinter in four checks:
(1) Repeating single character output line.
(2) Repeating character sequence output line.
(3) Input of a I ine message, followed by output of same message.
(4) Input of a character, output of same character.
b. Clock Interrupt Test - (Digital-7-51-M)
Tests operation of clock, interrupt, reader, punch and teleprinter in the interrupt mode.
Checks operation of flags and I/O skip instructions.
c. CONTEST II - (Digital-7-52-M)
Tests instructions, memory, clock, program interrupt, and reader I punch and teleprinter.
d. Reader and Punch Test - (Digital-7-53-M)
Exercises and tests reader and punch. Reads or punches alphanumeric format tape; time
can be varied between read and punch commands.
5-14

PDP-7 MAINTENANCE MANUAL

The following Maindec programs test instructions, and the processor and memory operations.
a. MAINDEC 701 - Instruction Test - {Digital-7-54-M}
Instruction test consists of twelve programs that check all instructions {except lOTs}
processor registers and controls (including PC), checks indirect addressing and automatic
indexing. Refer to the covering document for location details, etc.
b. MAINDEC 703 - PDP-7 Checkerboard - {Digital-7-55-M}
Creates worst possible noise condi tions in memory. Then checks accuracy word by word.
Four starting addresses provide selection of different noise patterns.
c. MAINDEC 702 - Address Test - {Digital-7-56-M}
Tests Type 149A Memory Module for proper address selection; therefore, can aid in
checking memory address system including MA and MB registers, memory selection switches
and all associated controls.
d. MAINDEC 710 Read Binary Test (RPB) - {Digital-7-57-M}
Tests photo-electric reader during binary operation. Program detects picking up and
dropping of information and feed holes.
The Mai ndec diagnosti c programs are parti cularl y usefu I under margina I-checki ng condi tions.
Each coveri ng document contains full particulars for load ing the program, interpreti ng resu Its and operating the PDP-7 for diagnostic testing. Chapter 2 contains instructions for loading and starting Maindec
programs.

5.6.2

System Troubleshooting
Begin troubleshooting by performing the operation in which the malfunction was initially ob-

served, using the same program, and thoroughly check the program for proper control settings. Assure
that the PDP-7, and not the peripheral equipment, is actually at fault before continuing with corrective
maintenance procedures. Faul ts in equipment, check with transmits or receive information, or improper
connection of the system frequently gives indications very similar to those caused by computer malfunction. Faulty ground connections between peripheral equipment and the computer are a common source of
trouble. From that portion of the program being performed and the general condition of the indicators,
the logical section of the machine at fault can usually be determined.

If the fault has been isolated to the computer but cannot be immediately localized to a specific
logic function, it can usually be determined to be within either the core memory or the processor logic
circuits. Proceed to the Memory Troubleshooting or Logic Troubleshooting procedures. When the

5-15

PDP-7 MAINTENANCE MANUAL

location of a fault has been narrowed to a logic element, continue troubleshooting to locate the defective
module or component by means of signal tracing. If the fault is intermittent, a form of aggravation test
should be employed to locate the source of the fault.

5.6.2.1

Memory Troubleshooting - If the entire memory system fails, use the multimeter to check the

outputs of the 739 Power Supply. Measure the voltages at the terminal strip as indicated on engineering
drawing RS-B-739. Do not attempt to adjust this supply. If the supply is defective, troubleshoot it and
correct the cause of the troublei then adjust the output voltage by performing the Memory Current Check.
This discussion references the X and Y axis selection drawings, BS-E-149-0-46 and BS-E-1490-47 and the memory control drawing KA77 A-O-IO.

Looking at the X and Y axis drawings, note that a

core address is selected by a combination of two G202 switch selectors: one on the left side of the arraYi
the other on the bottom of the array. READ or WRITE transitions, buffered by the BD module at location
1 B30, trigger all G202 selectors which generate and distribute the actual read/write current or specific
cores. In each axis, selection of the two G202 switches is accomplished by the bit configuration in the
MA register. The actual read/write current pulses flow from the positive supply line, through a left
G202 selector, through a horizontal core matrix line, through the core and diodes, down a vertical core
matrix line to a bottom G202 selector, and into the negative return line.
A train of current spikes will be seen, and missing spikes will then represent malfunctioning
addresses. Read currents are at terminals E and Mi writer currents are at terminals K and P of each drive
selector.

Before loading a Maindec Address program to find specific address malfunction, trace the read/

write gating pulses from the BD module at 1 B30 and all the Hand J terminals of every G202 module. A
G202 Switch Selector module cannot select without the gating pulse. If the read/write currents are not
as specified on the memory array labels, adjust the Type G800 control module current accordingly.
Perform the Memory Address Test program (Maindec 702) to locate defective core memory
addresses. Complete the entire program and record all addresses which fail. Inspect the record of failure
addresses for common bits. Refer to engineering drawings BS-E-149-0-46 and BS-E-149-0-47, and check
the memory selectors that decode common bi ts of the fai I ing addresses. Also check the assoc iated resistor
board and memory matrix module.

If an address is dropping bits, use the operator console to deposit all binary 1s in that address.
Then examine that contents of the address to determine which bit position is not being set (contains a 0).
Check the sense ampl ifier, inhibit driver, and resistor board for the associated bit. Also check the memory
inhibit current as described in the Memory Current Check.

If an address is picking up bits, use the operator console to deposit all binary Os in that address,
and proceed as described in the previous paragraph.

5-16

PD P-7 MAl NTE NA NCE MA N UAL

To locate the cause of a specific address failure, use the oscilloscope and current probe to trace
read and write current while performing a repetitive program such as the Memory Address Test program or
the Memory Checkerboard Test program.
Perform the Memory Checkerboard Test program (Maindec 703) to troubleshoot all other memory
condi tions.

5.6.2.2

Logic Troubleshooting - If the instructions do not seem to be functioning properly, perform the

Instruction Test program (Maindec 701). This test halts to indicate instructions that fail. When an instruc ...
tion fails, as indicated by the operator console indicators when the program stops, or by the diagnostic
printout that follows the error halt, consult the descriptive manual for the Maindec 701 to obtain an
interpretation that wi II local ize the faul t.

If the computer interrupt system or the Teletype teleprinter do not seem to be functioning
properly, perform the Teleprinter Test Program, Digital-7-50-M. If the tape reader or punch operation is
questionable, perform the Reader and Punch Test (Digital-7-53-M) or the RPB Test (Maindec 710).
Refer to the Teletype and Digitronics documents (see table 1-2) for detailed maintenance information on the Model 33 KSR set, BRPE Tape Punch Set, and Model 2500 Perforated Tape Reader.

5.6.2.3

Signal Tracing - If the fault has been located within a functional logic element, program the

computer to repeat an operation which uses all functions of that element.

Use the osci Iloscope to trace

signal flow through the suspected logic element. Oscilloscope sweep can be synchronized by control
signals or clock pulses, which are available on individual module terminals at the wiring side (front) of
the equipment. Circuits transferring signals with external equipment are most likely to encounter difficulty. Trace output signals from the interface connector back to the origin, and trace input signals from
the connector to the final destination. The signal tracing method can be used to certify signal qualities
such as pulse amplitude, duration, rise time, and the correct timing sequence. Refer to the table on
engineering drawing KA-77A-0-5 to check or adjust the timing of circuits in the main timing chain or
special timing chain generators. If an intermittent malfunction occurs, signal tracing must be combined
with an appropriate form of aggravation test.

5.6.2.4

Aggravation Tests - Intermittent faults should be traced through aggravation techniques.

Inter-

mittent logic malfunctions are located by the performance of marginal-check procedures as described
under Preventive Maintenance.
Intermittent failures caused by poor wiring connections can often be revealed by vibrating
modules while running a repetitive test program. Often, tapping a wooden rod held against the handles
of a suspect panel of modules is a useful technique.

By repeatedly starting the test program and vibrating

5-17

PDP-7 MAINTE NANCE MANUAL

fewer and fewer modules, the malfunction can be localized to within one or two modules. After isolating
the malfunction in this manner, check the seating of the modules in the connector; check the module
connector for wear or misal ignment, and check the module wiring for cold solder joints or wiring kinks.

5.6.3

Circuit Troubleshooting
Basic functions and specifications for standard system modules used in the PDP-7 are presented

in the FLIP CHIP Module Catalog, C-105. Circuit schematics are provided in chapter 6 for modules not
described in the catalog. Schematic diagrams of all modules are provided in the set of formal engineering
drawings supplied with each system. The following design considerations may also be helpful in troubleshooting standard modules.
a. Forward-biased silicon diodes are used in the same manner as Zener diodes, usually to
provide a vol tage differential of O. 75v. For instance, a series string of four diodes produces
the -3 vdc clamp voltage used in most modules.
b. An incoming pulse which turns off the conducting transistor amplifier changes the state of
DEC flip-flops. Since these flip-flops use PNP transistors, the input pulse must be positive and
must be coupled to the base of the transistor. FI ip-flop modules that accept negative pulses to
change the state invert this pulse by means of a normal transistor inverter circuit.
c. Fixed-length delay lines such as the W300 are extremely rei iable and ver seldom malfunction. However malfunction occurs, these delay lines should not be replaced on the printedwiring board. In such cases return the entire module to DEC for repair.
d. The W607 and W640 modules both contain three independent pulse ampl ifiers, each with
its own input inverter. The time required to saturate the interstate coupling transformer determines output pulse duration.

No multivibrators or other RC timing circuits are used in the

pu Ise ampl i fiers.

5.6.3.1

In-Line Dynamic Tests - To troubleshoot a module while maintaining its connection within the

system:
a. De-energize the computer.
b. Remove the suspect module from the mounting panel.
c. Insert a W980 FLIP CHIP Module Extender into the mounting panel connector holding the
suspect module.

5-18

PDP-7 MAINTENANCE MANUAL

Insert the suspect module into the module extender, making accessible all components

and wiring points of the module.
e. Energize the computer and establ ish the program conditions desired for troubleshooting the
module. Trace voltages or signals through the module, using a dc voltmeter or an oscilloscope,
locati ng the source of the fau It.

5.6.3.2

In-Line Marginal Checks - The normal marginal-checking method can perform checks of

individual modules within the computer to test specific modules of questionable reliability, or to further
localize the cause of an intermittent failure which has been localized to within one module row. These
checks are performed with the aid of a modified W980 FLIP CHIP Module Extender. To modify an extender for these checks:
a. Disconnect module receptacle terminals A, B, and C from the male plug connection terminals. This can be accomplished by cutting the printed wiring for these lines near the plug end
and removing a segment of this wiring in each line.
b. Solder a 3-ft test lead to the printed wiring for terminals A, B, and C. Make this solder
joint close to the receptacle end of the extender, certainly on the receptacle side of the
w,iring break. Observe the normal precautions when making this connection to aSsure that
excessive heat does not delaminate the printed-wiring board and that neither solder nor flux
provides conduction between lines.
c. Attach a spade lug, such as an AMP 42025-1 Power Connector, to the end of each test
lead and label each lead to correspond to the A, B, or C terminal of the receptacle to which
it is connected.
To marginal check a module within the computer:
a. De-energize the computer.
b. Remove the module to be checked from the module mounting ponel; replace it with the
modified extender, and insert the module in the extender.
c(l). If the +lOv marginal checkis to be performed,connecttest lead Atothe+10v orange
connector terminal at end of the panel. Connect test lead B to the normal -15v blue connector terminal and test lead C to black ground connector.
c(2). When performing the -15v marginal check, conr~ct test lead A to the normal +10v red
connector, test lead B to the -15v green connector terminal, and test lead C to the black
ground terminal, keeping all SPDT switches in the down position.

5-19

PDP-7 MAINTENANCE MANUAL

d. Restore computer power, adjust the marginal-check power supply to provide the nominal
voltage output, and start operation of a routine which fully utilizes the module being checked.
The procedures and routines suggested in Preventive Maintenance for use in marginal checking
the computer can be used as a guide to-marginal-checking modules.
e. Increase or decrease the output of the marginal-check power supply until the routine stops,
indicating module failure, and record each bias voltage at which the module fails. Also record the condition of all operator console controls and indicators when a failure occurs. This
information indicates the module input conditions at the time of the failure and aids in tracing
the cause of the faul t to a particular component part.

f. Repeat steps d and e for each of the three bias vol tages. If margins of ±5v on the +10 vdc
supplies can be obtained, and the -15 vdc supply can be adjusted between -7v and -18v
without module failure, it is assumed a module is operating satisfactorily. If the module fails
before these margins are obtained, use normal signal tracing techniques within the module to
locate the source of the fault.

5.6.3.3

Static Bench Tests - Visually inspect the module on both the component and printed-wiring

sides to check for short circuits in the etched wiring and for damaged components. If this inspection fails
to reveal the cause of trouble or to confirm a fault condition observed, use the multimeter to measure
resistances.

CAUTION
Do not use the lowest or highest resistance ranges of the mul ti meter when
checking semiconductor devices. The X10 range is suggested. Failure to
heed this warning may result in damage to components.

Measure the emi tter-collector, coil ector-base, and emitter-base resistances of transistors in
both directions. A good transistor indicates an open circuit in both directions between collector and
emitter.

Normally 50 to 100 ohms exist between the emitter and the base or between the collector and

the base in the forward direction, and open-circuit conditions exist in the reverse direction. To determine forward and reverse directions, consider a transistor as two diodes connected back-to-back. In
this analogy PNP transistors are considered to have both cathodes connected together to form the base,
and both the emitter and collector assume the function of an anode.

In NPN transistors the base is

assumed to be a common-anode connections, and both the emitter and collector are assumed to be the
cathode.

5-20

PDP-7 MAINTENANCE MANUAL

Multimeter polarity must be checked before measuring resistances, since many meters (including
the Triplett 630) apply a positive vol tage to the common lead when in the resistance mode.

Note that

although incorrect resistance readings are a sure indication that a transistor is defective, correct readings
give no guarantee that the transistor is functioning properly. A more rei iable indication of diode or
transistor ma Ifunction is obtained by using one of the many inexpensive i n-circui t testers commercia Ily
available.
Damage or cold-solder connections can also be located using the multimeter. Set the multimeter to the lowest resistance range and connect it across the suspected connection. Poke at the wires
or components around the connection, or al ternately rap the module Iightly on a wooden surface, and
observe the multimeter for open-circuit indications. Often the response time of the multimeter is too
slow to detect the rapid transients produced by intermittent connections. Current interruptions of very
short duration, caused by an intermittent connection, can be detected by connecting a 1 .5v flashl ight
battery in series with a 1500-ohm resistor across the suspected connection. Observe the voltage across
the 1500-ohm resistor with an oscilloscope, while probing the connection.

5.6.3.4

Dynamic Bench Tests - In general, return to DEC for repair or replacement a module which

fails marginal in-line tests, or considered faulty for other reasons. Many modules require special equipment for dynamic testing, since the timing of pulse amplifiers and delay modules must be rigorQusly main"'"
tained within narrow limits. Dynamic tests, therefore, should be oriented only toward di~covery of
defective semiconductors. Dynamic tests may be carried out by means of a Type H901 Patchcord Mounting Panel connected to the computer power supply outputs by means of Type 914 Power Jumpers. Simulated ground-level signals may then be appl ied to the module under test, using Type 911 Patchcords, and
an oscilloscope connected to tp.rminals on the front of the Type H901 panel can monitor output terminals
of the module under test.

5.6.4

Module Repair
Repairs to FLIP CHIP modules should be limited to the replacement of semiconductors. In all

soldering and unsoldering operations in the repair and replacement of parts, avoid placing excessive
solder or flux on adjacent parts or service lines. When soldering semiconductor devices (transistors,
crystal diodes, and metallic rectifiers) which may be damaged by heat, the following special precautions
shou Id be taken:
1. Use a heat sink, such as a pair of pliers, to grip the lead between the device and the joint
being soldered.

5-21

PDP-7 MAINTE NANCE MANUAL

Use a 6v soldering iron with an isolation transformer.

Use the smallest soldering iron

adequate for the work.
3. Perform the soldering operation in the shortest possible time, to prevent damage to the
component and delamination of the module etched wiring.

5-22

PDP-7 MAINTE NANCE MANUAL

CHAPTER 6
ENGINEERING DRAWINGS

6.1

INTRODUCTION
This chapter contains reduced copies of DEC block schematics, circuit schematics, and other

engineering drawings necessary for understanding and maintaining this equipment. Only those drawings
which are essential and not available in the referenced pertinent documents are included.

Should any

discrepancy ex ist between the drawings in th is chapter and those suppl ied with the equ ipment, assume
the latter drawings to be correct. A complete listing of the drawings in this chapter is presented in the
table of contents.

6.2

DRAWING NUMBERS
DEC engineering drawing numbers contain five groups of information, separated by hyphens.

A drawing number such as BS-D-9999-1-5 consists of the following information reading from left to right:
a 2- or 3-letter code specifying the type of drawing (BS); a 1-letter code specifying the original size of
the drawing (D); the type number of the equ ipment (9999); the manufacturing series of the equ ipment (1);
and the drawing number within a particular series (5).

6.3

The drawing type codes are:

BS, block schematic or logic diagram

Ml, module list

Cl, cable list

RS, replacement schematic

FD, flow diagram

WD, wiring system

CIRCUIT SYMBOLS
The block schematics of DEC equ ipment are mu Itipurpose drawings that combine signal flow,

logical function, circuit type and physical location, wiring, and other pertinent information.

Individual

circuits are shown in block or semiblock form, using special symbols which define circuit operation. These
symbols are similar to those appearing in both the FLIP CHIP Modules Catalog and the System Modules
Catalog but are often simpl ified.

Figure 6-1 illustrates some of the symbols used in DEC eng ineering

drawings.

6.4

lOGIC SIGNAL SYMBOLS
DEC standard logic signal symbols are shown at the input of most c ircu its to spec ify the enabl ing

conditions required to produce a desired output. These symbols represent either standard DEC logic levels,
standard DEC pulses, standard FLIP CHIP pulses, or level transitions.

6-1

PDP-7 MAINTENANCE MANUAL

NON- STANDARD SIGNAL

-----t>

GROUND LEVEL PULSE

------------------------------NEGATIVE PUL SE

-----0

GROUND LEVEL

-------------

----------------------------~

•

--------

NEGATIVE LEVEL

------0(>

LEVEL TRANSITION USED AS A PULSE
OR TRIGGERING ON THE LEADING EDGE
OF A GROUND LEVEL

-----K>

TRIGGERING ON THE TRAILING EDGE
OF A PULSE

-15V LOAD RESISTOR CLAMPED AT - 3V

,~ ,--+
2

-/\

'-9

PNP

TRANSISTOR INVERTER
1. BASE

2. COLLECTOR
3. EMITTER

GROUND -LEVEL NAND, NEGATIVE -L EVEL
NOR DIODE GATE

-v

Figure 6-1

DEC Symbols

6-2

GROUND-LEVEL NOR, NEGATIVE -LEVEL
NAND DIODE GATE

PDP-7 MAINTENANCE MANUAL

1~
2

1. PULSE INPUT
2 CONDITIONING LEVEL INPUT
3. PULSE OUTPUT

2
CAPACITOR- DIODE
GATE

DIODE- CAPACITOR-DIODE
GATE

'--1

PULSE INVERTER

PULSE AMPLIFIER
I. PULSE INPUT, POLARITY INDICATED
BY INPUT SIGNAL
2,3. TRANSFORMER - COUPLED PULSE
OUTPUT. EITHER TERMINAL MAY
BE GROUNDED

8
FLIP-FLOP (MOST FLIP-FLOPS HAVE ONLY SOME
OF THE FOLLOWING):
I. DIRECT- CLEAR INPUT
2. GATED'CLEAR INPUT
3. DIRECT-SET INPUT
4. GATED-SET INPUT
5. COMPLEMENT INPUT
6. OUTPUT LEVEL, - 3 V IF 0,0 V IF I
7. OUTPUT LEVEL, 0 V IF 0, -3 V IF I
8. CARRY PULSE OUTPUT,UPON BEING CLEARED

o
5

------~--

_._----

'-4

!
DE

t=:
Figure 6-1

6.4.1

DELAY (ONE-SHOT MULTIVIBRATOR)
I. INPUT PULSE
2. OUTPUT LEVEl,-3V DURING DELAY
3,4 TRANSFORMER - COUPLED PULSE
OUTPUT. EITHER TERMINAL MAY
BE GROUNDED

DEC Symbols (continued)

Logic Levels
The standard DEC logic level is either at ground (0 to -0.3v) or at -3v (-2.5 to -3 ...5v).

Logic signals are given mnemonic names indicating the condition represented by assertion of the signal.
An open diamond (-<» indicates that the signal is a DEC logic level and that ground represents assertion; a solid diamond (--+) indicates that the signal is also a DEC logic level and that - 3v represents assertion. All log ic signals appl ied to the cond ition ing level inputs of capac itor-diode gates or
diode-capacitor-diode gates must be present for a specified length of time (depending on the module used)
before an input pulse triggers operation of the gate.

6-3

PDP-7 MAINTENANCE MANUAL

6.4.2

Standard Pu Ises
DEC standard pu Ises are 2.5v in ampl itude with reference to either ground or - 3v, depending

upon the type of module used. The width of standard pulses is either 40, 70, or 400 nsec as required for
specific circuit configurations. The standard 2.5v negative pulse (-2.3 to -3.5v) is indicated by a solid
triangle (--.. ) and is always referenced with respect to ground, as shown in figure 6-2.
OVERSHOOT

GND -

- 2 ~v

-- - - - -

-- - - -- --

PULSE

r- WIDTH--!

Figure 6-2

Standard Negative Pu Ise'

The standard positive pulse is the inverse of the negative pulse and is indicated by an open
triangle (----[». The positive pulse goes either from -3v to ground or goes from ground to +2.5v
(+ 2 • 3 to + 3 • Ov ) •

6.4.3

FLIP CHIP Standard Pulses
Two types of pulses, R series and B series, are utilized in FLIP CHIP circuit operation. The

pulse produced by R-series modules starts at -3v, goes to ground (-0.2v) for 100 nsec, then returns to
- 3v. Th is pu Ise appears in figure 6-3.

10 0/0

-0.2V - - -

~_ _ _ L - - -

--':"----- - -

- 3V

t--- 100NSEC~
I
-,
Figure 6-3

LC::400NSEC

FLIP CHIP R-Series Pulse

The B-series negative pu Ise is 2.5v in ampl itude and 40 nsec in duration and is sim i lar to the
one shown in figure 6-2. If th i s pu Ise is appl ied to the base of an inverter, the inverter output wi II be a
narrow pu Ise, sim ilar in shape to the R-series standard pu Ise. The B-series positive pu Ise, wh ich goes from
ground to + 2 .5v, is the inverse of the B-series negative pu Ise.
6-4

PDP-7 MAINTENANCE MANUAL

6.4.4

Level Transitions
Occasionally, the transition of a level is used at an input where a standard pu Ise is otherwi se

expected and a composite symbol (

.t» is drawn to indicate this fact. The triangle i$ drawn open

or sol id depending respectively on whether the positive (- 3v to ground) or the negative (grounc,l to - 3v)
transition triggers circuit action. The shading of the diamond either is the same as that of the triangle to
indicate triggering on the leading edge of a level, or is opposite that of the triang Ie to indicate triggering
on the trail ing edge.

An arrowhead (---...) pointing in the direction of signal flow indicates nonstandard

signals (power supply outputs, cal ibration reference levels, etc.).

6.5

COORDINATE SYSTEM
Each engineering logic drawing is divided into 32 zones (4 horizontal and 8 vertical) by marginal

map coordinates. Figure references in the text are usually followed by a letter and a digit specifying the
zone in wh ich the referenced c ircu it is located.

Physical reference to a draw ing area such as "lower left"

or lIupper center" may also be used.

6.6

MODULE IDENTIFICATION
Two designations appear in or near each c ircu it symbol or inside the dotted I ine surround ing

multiple circuit symbols shown on engineering drawings. The upper designation consists of four characters
spec ifying the module type. Th is designation identifies modu les in the Dig ital Systems Modu les CataloS1'
and the FLIP CHIP Modules Catalog describes the FLIP CHIP modules. This manual or other referenced
pertinent documents describes modu les not found in either catalog.
The lower designation is the modu Ie location code. The leftmost character of th is designotion
is a number indicating the cabinet in which the module is located. The next crharacter is a letter indicating the mounting panel in which the module is located. The last character consists of one or two numbers specifying the module location with in the mounting panel. As an example, the designation 1A22
indicates that this module is mounted in location 22 of mounting panel A in cabinet 1. Terminal J of this
modu Ie is designated at 1 A22J •
Module mounting panels which can accommodate more than one row of modules may be used in
the construction of certain equipment. For this equipment, a letter is assigned to each row of modules
within a mounting panel. When a particular device is contained within one cabinet, the number 1 may be
om itted from the reference designations appearing on the assoc iated draw ings for that dev ice.
Certain modules are indicated on engineering drawings by the normal 4-digit type number
followed by the suffix R or by a number and R. These modules contain removable jumpers which connect
certain output term ina Is to clamped load resi stors. The suffix Rind icates that all clamped load resi stors
on that particu lar modu Ie are in use; and since replacement modu les are sh ipped with all calmped load

6-5

PDP-7 MAINTE NANCE MANUAL

resistors connected, a new module can be substituted for the old without modifications. A suffix such as
2R ind icates that the two clamped load resi stors connected to output term inals designated by letters closest
to the beg inn ing of the alphabet are to remain connected, and all remain ing jumpers connecting clamped
load resistors to output term inals shou Id be removed. As an example, the designation 11 03-3R indicates
that the jumpers associated with output terminals H, L, and P of a Type 1103 Inverter Module are to remain connected, while the jumpers associated with output terminals T, W, and Z, are to be removed,
thereby modifying the standard Type 1103 into a Type 11 03-3R.

6.7

EXAMPLE
Figure 6-4 illustrates DEC symbols and nomenclature. The circuit shown is a Type 4303 Inte-

grating Single Shot used to control the enabl ing time of several gates. The modu Ie is locoted in the twelfth
position from the left (when viewed from the front or wiring side) of mounting panel B (the second row of
modules from the top) in cabinet 1. The symbol marked DELAY is a monostable multivibrator with two
complementary outputs, terminals U and W. The output at terminal U is connected to terminals 2D18F
and 1 B15M while the output at terminal W is connected to terminal 1 D02F.

TO lB1SM

SAFE

TO 1D02F

TO 2D1SF

~O3- u w

---

I 1B12

-- -

DELAY

I
I

VARIABLE

GO
lC12H
START
1BllJ
KI

10KO
TIME

Figure 6-4

T
OPEN
lB13H

Typical DEC Logic Block Diagram

6-6

I
-.l

SAMPLE
lC21Z

DMI

RED*
____. -__________~~__________- .________~~==D________~~+~V

CINCH JONES
~. KI o-------~,IIIx,
TERMINAL STRIP

CI
511,000
211V

MFO

RI
11111%
2IIW

311,~~ ""0

OV
YEL

INPUT
IIIIV AC
60N

MFD

1 1

55,000
211V MFO

C5
35
,000
25V MFO

311

'000
25V

MFD

roBl.lJE*

'''~~--~e-------~~------~------------~------------~----------~------~~~-I~
BLU
NOTE:
IN ORDER TO KEEP OUTPUT VOLTAGE WITHIN THE FOLLOWING LIMITS:
+ 10V: + 9.11 TO +IIV
-IIIV: - 14.11 TO -16 V
THE LOADI NG SHOULD BE WITH IN THE FOLLOWING LIMITS:
BOTH SIDES
+ 10 V 0 TO 7.0 AMPS
- III V 1.0
TO
8.0 AMPS
LOADED
ONE SIDE
+ 10 V 0 TO 7.11 AMPS
-III V 1.0
TO
8.11 AMPS
LOADED

* HEYMAN
MFG. CO.
TAB TERMINALS

~g~A~~OJ~EIIP,~Tf~T[ I~U~R~m _A~R=-~'_~~ED_B~_ THE FOLLOW I NG

Power Supply (+~Oand -15) RS-B-728

RED

FI
MOX IIAMP
SLO-BLO
RED

C2
511,000
25V
MFD

RI
50
211W

BLU

HEYMAN TAB CONNECTORS
CINCH JONES TERM. STRIP

BLU

Power Supply (0-20 margina I check supply) RS-B-738

6-7

DM9
r--------l

I
I

I
RED

RED

INPUT
lillY AC

60",

:515,000

MFD

MFD
211Y

25Y
PRIMARIES
TWISTED
RED 8 WHT

C2
:515,000

BRN

:515,000

IIiV

1-8 AMPS

MFD
211V

BLU
BLUE

T2
DEC
1016

BRN

RED·

* HEYMAN M'FG. CO. TAB-

BRN

TERMINAL IN PLASTIC BUSHINGS

c:::::J CINCH JONES TERMINAL STRIP

+
C4

3&,000
MFD
25Y

I _ _ _ _ _ _ _ _ JI
L

BlU !If

Dual 15-Volt Power Supply RS-B-778

ORANGE

+
10V

INPUT

YELLOW

IIIIV AC

.aN

IlIV

RED -WHT
TWISTED
RED

+
IlIV

+
I!lV

GREEN
UNLESS OTHERWISE INDICATED
HEYMAN MN CO TABTERMINAL IN PLASTIC BUSHING

[:=J CINCH .JONES TERMINAL

STRIP.

Power Supply (one lOv and three 15v floating supplies) RS-B-779

6-8

... - , ACME

i
I

FAN

II5VAC
GO'" ±IO%

14\

TI
T -1-57109
(DEC #1024)

1;2

i !g

OED

'--__+<
jI3>-+-I---,O",
JONES
STRIP

REO
I

~;~:~~CD

WITH

TRANSFORMER

BLU (80V)

04
...
po

~ ORN (75V)
~ YEL (70V)

's?

GRN- YEL(G5\1~3

~ BRN (GOV)

ORN

~ BRN-YEL(55\1

RI
350
2!!NI

~ RED-YEL(45V)

-0
0

C> 14

"'0
"'0

BRN- YEL( 55V)

C> II

GRN - YEUG5~

~ YEL{70vl

~
<l
3

~ ORN(75V)

"""l

C> a

~
;::0

..~

IBP IBU

I
I

-~~~~~~~~~~~~A~F~~~~W~HT~

"-J
W
--0

10 VIA) A '""O--_ _ _ _---I.-_ _I---+---'-R:..:E:..:D_ _ _ _ _ _ _ _ _.......:;.:A~Ar

()

BLU (aov)

~§

...

B
TE~~INA

BLU

'11

! VIO-~ JO. K. SIGNAL
1-"'-'~~.--t-+:::!GR~y:"O-GINHIBIT POSITIVE TEMP. COEFF.
INHIBIT POWER SUPPLY CONTROL G800
1,6~0 I
THERMISTOR, 33(M., ± 10% AT 25°/c
BN

-15V

B"'"

GNO

BLK
AC
Il8W
C '""O------I--+---I---+--=R::::E;;.O-----------.:::.L_ _ _ _ _ _ _ _ _ _ _ _ _-1""BM~I.:..:%INF-t:GGlY:-~y;,--o-7-1

{

~2552wO +_'"= CI
~

!I RED

+_""'C4

RI!O

"l;=-C7

_d\~e-=c

+ 4

R8
}

~";

L..---+4...-----'

~AO AH

I
I
~
I
I
:~IGGBRRR_Y~_~8~-~1~1
I

IBT IBP <>BU

AA
AB

READ/WRITE POWER

SUPPLY

G800

BLK!

1,62:)
j9
1/8\'1

,
L..--------+--+--I-~~_ _ _ _ _ _ _ _ _ _ _ _ _-1.:::B=--I%M-FT~#"09

LOW

VOLTAGE

DETECTOR

(CARBORUNDUM PT. NO. A0905P -B
OR EQUIVALENT)

55 -75V
0 - 2 AMPS

I BLU

r-~
.....
~..L-+!.IOI!...'%/lI..Q-'I--IO,-OR-~--+-~~-+-----+--+l""""''-O- 3 I

1% MF
UNLESS OTHERWISE INDICATED:
CAPACITORS ARE 9,0001100V; MFD
DIODES ARE IN 3212
TRANSISTORS ARE 2N 371G

~'~II20;;

BLK

~~~

~:";:."

i
II

GRN

~ BRN (GOV)

gg.

'-+---~----~~-------+I--Ol

WHT

j:, 2

~ BLU-YEL (SOV)

--0

+, J,,1 ,,06 ~t >~v"'"

~ REO-YEL (45V)

(J)
"""l

0-.

BLU-YEL(50V)

r---l
j

W505

L . -_ _ _ _ _ _ _ _ _ _ _ _~

JONES
STRIP

THERMISTOR,
10% AT 25°,t
R/W
POSITIVE330.1"1..,
TEMP. :!: COEFF.
(CARBORUNDUM PT. NO. A0905P -8
OR EQUIVALENT)

.-------------to-------4p------------o A + 10 V(A)
.--------~-----~-----~-------OC

04
IN 964 A

R2
7,500

GND

R6
3,000 07

Q2
TRIMPOT
BOURNS

DEC 2894- 3

5,000

• 0I
114M 6.8 AZ5

R3
68,000
10%

R4
6,800
10%

R5
1,000

L-------~~-~~-_4-----------------------0B-~V

UN LESS OTHERWISE INDICATED:
RESISTORS ARE 114W, 5%
DIODES ARE 0-664

Low-Voltage Detector (for 739) RS-B-W505

+
BN

TO POSITIVE
COEFF. THERMISTOR
330J\. AT 251°C

R30
BS
12,000
BP

BU
R24
1,500
BK
AA

+ 10V
R29
RI
33,000
10%

R2
3,000
10%

22 2W,10'Y.

AH
R31
750
2W

TO SERIES
REGULATOR
BASE

AD
R28
33,000
10%

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W; 5%
DIODES ARE 0662

AE
R21
820
B-15V
C GND

-3V
,
I.,; _ _ _ _ .J
'STRATE'
I

Control for 739 Power Supply RS-B-G800

6-10

#18 BlK

r-----------------------------------------------------~~~------------------------------------._--~GNO

}
Q~~_4~~~.-~~~ O~._----~------------------------------+_--------------~~--------------~.-~~~~+_O ~~~:~F
~~

#14WHT

NOTES:

6TERM
.JONES STRIP
'1141-6

Two-Step Power Control RS-B-832

6-11

I ______

BIT 4
RB9
Iff'- ___ 0

I _____

~BIT
8
RI52

]BIT S
RI24
1:.110 ___ 0

_____

I~~ ___ 0

~________~~'--+~~__~~~__-1H-__+.____~~~__-.4-__~____~B~I~T~4~__-.~~~____~~L-__~~-1.-____~B~IT~6~__~~_+._----~~----~--~~----~B~IT~----~--_1~A-o+IOV~)

o GND

-i5V

~
(Q

:J
""'l-

~
-I
(1)

RI46

R21

R64

(1)
""'I-

"'0

\'V

(1)

;;:0
(1)

C6
2200

0
(1)

<.
(1)
~

011

P
CLEAR FLAG

;;:0

Vl
I

()
I

RI36

""-J
0
0-

054

R29
1,500

C37
.0022 MFO

lJIILESS OTHERWISE INDICATED:
RESISTORS ARE 3,000 OHMs
RESISTORS ARE 1/4 W
RESISTORS ARE ~
CAPACITORS ARE MMFD
DIODES ARE 0-664

IrrsN~ill~:L~f~I~~ORP .1762

053
T
DATA

ENABLE
066

R 158

r-__~______~~__~__~____~~~__~__~____~~____~__~____~~____~__~____~OU~T~6~__~__~____~OU~T~7____-J__~____~OU~T_8~__~__~__~~~____~____~A+IOVIAI

045

D-662

D46
0-662
047

0-662

m
CO

::I
-to

~
-I
(I)
(I)
-to

-0

(I)

-I

a
:::J

-to
-to
(I)
""'I

;;:tJ

Vl
I

()
I

059

..j::...

"-.J
0
"-.J

RI47
V
OUTPUT

I2POO

W
OUTPUT

CLOCK
073

0-003
UNLESS OTHERWISE NDICATED:
RESISTORS ARE 3,000
1,000 I,~ a 3,000 OHM RESISTORS ARE 1/4Wi 5~
ALL OTHER RESISTORS ARE 1/4 W; 10~
DIODES .ARE 0-664
TRANSISTORS ARE 2N 1754
CAPACITORS ARE MMFO
II-IS TRANS~ELECTRON ICS COf!P#I762
REF BS 4707

ACTIY£

R
WAIT

T
CLOCK

AA+IOVIA,
AC,BC,BM
GNO

C31

.01

MFO

C32
.01
MFO

022
0-662

021
0-662
020
0-662
AD

019
0-662

RI9
1,500
5",

C30

.01
UFO
018
0-662
AV

RI8

~OO

-C

017
D-662

-C
I

016
0-662

""'"'-J

029

»0

0
C

.J::>..

C33

.01
MFO
R47
1,501:)
5",

AB-15V

-to
-S

;;:0

Vl
I

()
I
c::lI

I'V

AN
AS
BV

BR
BN

CIS

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 114Wl 10",
CAPACITORS ARE 56 MMFO
DIODES ARE 0-664
TRANSISTORS ARE DEC 2894-1

BA+IOV

Y
~f+IOV
47.f}JJ;
IFIXEOI .~

RI8

y
~~
MF

;;~~d.

lIFO

"21

1,210
MF
4~

'------4

~~010

R34
410

~,g~~2
~,g~62

~~ ~~?""
1i~_':~~'~b~r1:i~~ ~ r~,
.2

..... LEVEL

012

RI2
261
IIF

itll
AR 0--'

»
3

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I

~
~
CD

""I

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0
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RI9
82·5

»
R21

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01
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R3
~~1
IF

R6
10

R8
141

IIF

»- A ~F

IIF

147

IIF

R5
150

R22

~AK

R4
881

IIF

R33

~O
~

tI:0

R32
2,200

R25
150

II......

•

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~

541

~~62

R45

3,g~0

SPS2002
T2
T-20IO

2--:'

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~56

\ '"
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R37
r.::::: 013
;'R44

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2N3OO9

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2894-6

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08
DEC 2219

CLAMP

R28
141

.. 01.

(~H:>'

05
SDA-8
RI1

82.5

Vl
UI

AM()-<

06
SO&-'

.. F

()
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fli

~AN

R,
1,180
IF

R2
1,180
IF

RI5

R38
3,000 .,..CIO

R35~. DEC

~------------~-------------'---------------'----------r--------r------~----~-~-R~3~0;~:::::::~~~~0~·12~2~8g~'~~~-m~~~~~goo~~~~~

15
SPS

R40 ::
330 ~
I' :;
,CII

014
SPS
200~

Ji
"

TI
T-2010

~~021

~~~2

AF
RIO
1,000
STACk: !';...
SELECTION
82

~~g~~

(;1

.~~2
RII
DEC
5~
: IOOpOC 211M-m

C6 ~r:

.~IO

R47
470

---------+-----...

.....

.~2

R42

'....

410
...JL

AA
+lDV

UNLESS OTHERWISE INDICATED;
RESISTORS ARE 1/4W; IO~
CAPACITORS ARE ....FO
DIODES ARE 0-664
R68 R22 ARE DAYSTROII TRANSITRIM
IIF RESISTORS ARE VSWi "', 1DO,../"t WITH TI ctWUCTEl'IISTIC

AB
-15V

)
At, BP,BU
eND

R39

R41
410

1,500

5,.

cl2

.0022
.. FO

r--------------------------------------------~~--_.~------------------------------------------------------------QC GNO

....

,......--+--~~-----------

----------------+_----I__----__4t_~--_4IP----------------....--------__4t_----__-----------OV+ IOVIV)

D6
1N429

0-662

08
0-662
07
1>-662

04
0-682

L----e~----_6----6_--~------------------__4~----~~--~--~~--------------~~----------OB-ISV

UNLESS OTHERWISE INDICATED'
RESISTORS ARE 1/4",10"
RS, RIO a R 16 ARE TEL- LAB

Master Slice Control RS-B-G002

r-----------.-------------....

------------~------------------------------------__4t_------------------------_______OA+IOVIA)

R29
H

o-....-II~_6--+-I

JIO-....-II f--_64--r
INHIBIT

RETURN
L--------------------I~----------_r~~4-------_oR

' - - - - . - 0 U T. p.

RI2

680

RI4
680

RI6
470

RI8
470

R21
680

R23
880

L---~~------~~~~~~--~----~--~~----------------------~--~--~~--~--------_I~---4~--_oB-15V
L-_6----~----------------------------~----6_--------------------------------~--_4P--------------------4_--------~C GNO

UNLESS OTHERWISE INDICATED;
RESISTORS ARE 1/4W; 10'"
CAPACITORS ARE MMFO.

Inhibit Driver RS-B-G201

6-16

FIXED

r---------------------~._----------~--------------~----------~._----------------------------_oA+I~1
r---------------------T-----------_+----~--------_+------------+_----------------------------~~C

GND

Lse o

t+.....-.rv>w-....O T

r-:3"v--1

+-____________________

L-__

I STRATE:
I

~~--~------------------------~~--._--._~

I
I
.01

08
I
0-6621
I

MFO

D!I

0-862:
I
I
I
D4
I
D-t162 :

WRITE

'----flf-....--O..

WRITE'

I
ftl

ft2

470

"34

. .0

03
I
0-8821

2___

~--~--_4~------------_4~--~--------------~--_4--------------_4~--~------------~--~~----~~I~

Memory Selector RS-B-G202

6-17

3-C

T~~

1-17'

1-18

VIEW FROM
CDlPONENT SIlE

PLUG

PLUG
4

I-E~~------,--------,

1-50-+_---..........

PLUG 5

0-+----..,-..--------,
---+-.,

1- D
1- 4 O-~.....

.ImI.i

lETTERS OF PLUGS ARE ON PRINTED
CIRCUIT SlOE OF BOARD.
N~ ARE ON COMPONENT SlOE
OF BOARD.

WI!e!&
I-C

1-3

1- C o-+----~~------..,
1-3

O-+....---+-...

FIRST NUM8ER III REFERS TO PLUGS.
SECOND LETTER (CI OR NlIIIIBER (31
REFERS TO PINS.

1-8

0-+------....------.....,
......---+-..,

1-2 ~+-

I-A ~+_----p-------...,
I-I ~+

....---+-........

Memory Selector Matrix RS-D-G601

Memory Selector Matrix RS-O-G601
6-19

3-U

I-U

I-IT

1-18

I-HI 0-4---_--_
1-7'0-4-....-1--.

PLUG I

PLUG 2

I-Fo_+--+-----.
1-6o--I-_--I-~

PLUG

I-Eo-4---+---_
1-!5 0--1-_--1-...

PLUG

Iii

L£TTERS OF PLUGS ARE ON PAINTED
CIRCUIT SIDE OF BOARD.
PfJMBERS ARE ON COMPONENT SIDE
OF BOARD.

EXAMPLE

I-C

I-C:o--I---_---<

1-30--+-_--1--

1-3

FIRST NUMBER (II REFERS TO PUJ6S.
~ ~~S~Cl OR NUIltBER f3l

I~o_+--_----~

1-20-4-.....---1h
UNLESS OTHERWISE INDIC.crED:
RESISTORS ARE 2,200; I ...W; 10"DKlDES ARE 0-664
TRANSISTORS ARE DECIOO8
TRANSFORMERS ARE T-2060

I-A 0 - + - - + - - - - - ,

I-Io--+-_-+_.....

4-U

4-0

Memory Selector Matrix RS-D-G602

4-8

Memory Selector Matrix RS-D-G602
6-21

STANDARD MODULES
TYPE

QUANTITY

BI04

BI05

8113

8115
8117

OPTIONAL MODULES

OPTION

TYPE

QUANTITY

177

8104
8105

8123
8124

1
1
2

8123

8201

8204

8210

19
I
12
12

EXTD

8104
8105

8620

MEMORY

8113

8684

8115

ROOI

22
I

RI07

RI41

R203

R302

R401
R601

R602

8501
8360
8602

EAE

(SEE

8117

OPT/ON
INSTALLMENT
MODIFICATION
SHEETS)

8123

8155

8201
8602

6
3

8684

RI07

R202

R603

W607

RG50

W051
W501

W607

W640
W700

4
2

CP Module Map ML-D-KA77A-O-2

6-23

CP Module Map ML-D-KA77A-O-2

6-230

2~-

32K

16- 211K-

8- 16K

0 -

8K
BU FER ~
MA's TO ~T ME

P 51 5

P
A

~ BI15 8195 ~107 R21'2~202 B692 ~692 8602 ~6811 ~68~ ~68~ B68~~6~

868

~8~(/)2B W028 WQ!28 W!I)28 W028 ~Q!28 W(l2S!w021 ~"21 W~21.~021 W021 jwll21 ~~~~ e~g\ W921
1&

TO ~

MA"

20 21

22 23

"* * "* * *

2S 2& 27

MA 6-17

B BI17 BI13 ~115 8115 812 Wli9 81B~ 819~BIB5 B15~ BI55 RI07 RI07 RI97 RI0 B6811 B6B~ BI55 868~ B68~ B6B~ B6B~ B6BlI B6B~ 858~ B6811 068~ B6811 B6B~ B6e~ B6e~ B68~

o
+

o TA

SA
9
9
9
9
MEM
MB INFO CONT
+ ~ 17 17 IN
8
17
8
091
N .......---t--41B' s OU1-+--+O--tl'"
8
17
0,

•

• • o

SEL

RO I ~RT I

e~EL

__ M

CO TROL

W0~1 IIB21l W021

I
N

B
D

B
".

I
CRY

CRY

4
".
5
CRY

7
CRY

6
".

9
CRY

110

1121 W021 W021 11921 W021 1'1021 W021

W92i 8620 868~ B620 8684 8620 86811 B620 B6B4 B629

>--.. -.
MB
"

MB
I

MB
2

MB
3

M8
4

MB
5

MB
6

M8
7

MB
8

"..
MA
5

MA
6

MA
9

MA
19

MA
II

MA
16

MA
'17

B201 B201 8201 B291 B20

820

MA
12

MA
13

MA
III

MA
15

6BlI

86B

BilE BOO

BII

Bfl0

B20i B201 B2018201

Oil

&
II

CRY

13
CRY

10
".

15
CRY

RD 2 ....-4--1- MB BUS bPI I VE ~s
MB
8
10
6
~
INH

I NH
twRT
2

14
".
15

'If
MA
II

32K 16K
8K
EX P ME ORY

+
e +
17

W821

_ _ MA

17
CRY

o
16
".
17

B201 B291 B291 B291 B20

A ,

D 8

MB
9

MO
10

MB
II

MB
12

MB
13

MB
III

MB
15

MB
16

MB
17

.....-+--+----' MEMC Y

..-

B201 B20 I 8201 B201 8201 B20 I B29 I B21l1 B 195 B I 05 B 195 B36e

1---0' ERFL W

AC
I

___

AC
6

AC
8

AC
III

AC
II

CON ~OL- ~

C +11__

86028113 8113 ~11l5 ~115 BI17 B113 BI05 BI13 ~21'131e11l4 RI41 ~11l5

liNK

M 8

~ CO TROL

B20

321(

i6K

EXT!

MHORY

2':'

2!t

30_ 31

PC
19

PC
II

PC
1'2

PC:
13

PC
III

PC
15

AC
13

AC
16

T2
DLY

H
123

B2I'I1i B361l B36Il B 1011 B 1ge

AC
12

21'111

PC
8

201 ~21'11

2111 B291 B21l1 11291

AC
15

PC
7

BII iB602 .602

III

BII

*PC PC.,.. *PC PC
3

B20 I B21l B201 B29 I

C NT""Rq.-;--t--+--t---t A

B20

B6e~ B629 8684 8620 B68~ 8629 B684 8620 86811 B684 B684 86B1I 86B~ B6e~ B6e~ B6B~ B6BlI 868~ B68~ 8684 11921 W02lJ
--

E
B201 B2,"-

A 3 N

86e2 B2lJ I B201

B2GIB2G1 ~2G1 iB2G1 ~21'11

PC
16

2111 ~21'11 .211 1B2t1

.. .. '" ..
II 13
15
'" '"17

B!lI' B62 B62Q1

PC+l
RAP

CRY""

FLG

EAE

B21" B219 B219 B219 82111 ~21~ B219 B210 B210 8210 8210 B210 B210 0210 B210 B210 0210 B219 B210

...

MBB

14111

~(")

.d ~(I)

1'2(0

I( I 17( I

E
A

EAE

...~--+-+-

AC ~MUL TOR

MA ~R A " MI OR SATES

~ONT IoL

--I--............ RUN lAND

RAP .L-..a.ItoIL-.._-I---.... S P

IME f---4

R
V
E

oa.

--'-

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20 21

22 23124 ~ r26

AC UMUl TOR
CONT OL

-+-

5 . .--11--0......
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MAJO

AND MINO

RUN AND

STA ES

RAP +---t~
....
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IME

141

. "
E
i

M ~

[

I~I

113

113 8105 B113

117 B117 BI05 8115 B2011 BI13 BI05 B602 BI15 R6"2 R6"2 BI05 BI13 BI13 BI17 BII5 BI13 BI1l5 R302 8105 R3IJ2 BI05 BI(/)4 W021

CON-·

E
5 "'-4--+ AC UMUL TOR

__ T ME

SOU:
BUFF RS -+~"'_+--+--~--II----tTiME CHA·IIt----It--Ir--+--+---I--~CBu:

~ ~
EAE EAE

SOLE

~,C8lE

EAE

W029

o TRA~

*RE CON-'

I
N
D

"'0

(J)

l
E

W020 B602 B602 B602 B6112 B602 8105 W607 81130113 Bli!5 BI15 ~123 BI13 8105 BI13 BI05 BI15 R6113 0115 BI13 BI05 BI05 BI17 B20l1 R201 wallQl ~6l10 R602 RlIIl.1 W501 \1121

""'C

E
C

1411

B621'1 WIl21 WQl21 l1li21 W.,21 ~'21 wt21

()

~
17

B62e B62~ B621 8620 ~36fJ -_51 R3IJ2 ~"23 W.23

K 0

PC
17'

TP6
10

RPT
ECT

B 11tl5 B1211 R65B R65B R65" R650 R65B R650 R6Sltl R65" R651tl1U'01 ~105 BI15 1'16137 W697 1'1607 8105 BI13 R311J2 BI011 8360 B369 8360 B360 B360 B360 R601 B360 8115 W6l10 W021

f'.)

1:\

22 23

26 27

28 29 30.31

132
CONSOLE

"'-f--+-CAB ES T

I/O PKG,

",-I-+-+--t-I NT RRUP

CON ROl-+--+--+--+--I-...
-.......

R
E .

1'1021 1'1021 1'1021 W021 1'1021 1'11321 Wltl2J 1'1021 Vl021 1'1021 1'1921 W021
\t OPTIONAL MODULES

~ANU L_+-_+-.... CBLE
FUNC IONS

KEYS

B369 B 105 VI.640 B I 13 B I 15 B2911 BI 13 B I 13 B I 17 B 105 B I 13 W697

BI 15 8 I 1.3 R 107 W709 W700 11023

KEY
MANUAL
N32
KEY
START

KEY
CONt.

I
I

W!ZI21
RPT(t)'TP7

rBii3-- - - ---,
N28
I
START + CONT

-15V

-*"

~..T~RJ ...

A
I

FJH

...

Wf!2l~
N3

I
I

KEY
EX

CONT

IN27 KEY MANUAL

I
I
~1(~7-1
IN29
I

I
I

CONT

18115---'

fBIls-----"I
N27 START+EX+DP I

CONTINue!
I

r---?<Oi

KEY
DP

IM
I
1"\)1-- =1

I....-----:----~

~_ _ _ _ _--lM!!d V

--,

______ J

I CONTINUE
I

L ____ ~

SP 2

r"lH07- fsTof:i) -TBIOS- 1
KEY
STOP

L_~~

IN29
I L20
.....---f----ir--=-..........---l-........- - o READ-IN

B
lw50i----- - - - ,
I
I

I
STOP

I -=KEY MANUAL I

r----=-----.:I~O KEY MAN.UAL (B)

I
I

¢-AC
L,PCi-MB
SELECT ROO.
WAIT FOR
RDR FLAG.
RELEASE OF
R D-IN KEY
CYCLE)
( FIRST
ONLY

SP4

I
I
I

IK31

I 1 - - _..... READ-IN
~-----::'>RUN

I READ IN(B)

L _________

THE W5!2l1
SCHMITT TRIGGER ALLOWS
RELATIVELY SLOWLY CHANGING
MANUAL KEY LEVELS TO BE
SET UP BEFORE KEY MANUAL
!ill STARTS THE SPECIAL
PULSE TIMING CHAIN OR
ENABLES THE REPEAT CLOCK.

LEVELS FOR;

NOTE: ASSERTION I NOT ASSERTION

...

+I~V

GND

(DO NOT GND ANY OF THESE POINTS)

BGN: GENERATED BY PWR elK WHEN THE COMPUTER IS
TURNED ON OR OFF,
GENERATED AT SPl WHEN ANY MANUAL KEY IS OPERATED
EXCEPT CONTINUE; (CONTINUE DOES NOT GENERATE BGN.)
FUNCTION ClEI>.RS THE FOLLOWING REGISTERS
AND/OR FLIP-FLOPS:
EXD,EXD SYNC, DBK POV,MB,L,IR AC, TRAP FLAG
I/O TRAP, RPT, X.cT CY;PIE, DATA SYNC, Clf( SY.NC, PRbG SYNC ~
SETS THE EXCY TO A ONE (1).
FORCES THE EXECUTE CYCLE FOR ALL KEYS EXCEPT START
(AND CONTINUE).
.

NOTE!

ALL PINS DESIGNATED BY ASTERICKS
AND PIN D ON N3~t\ N31 SHOULD BE
COVERED WITH THE APPROPRIATELY
C-oLORED $LEEVING.

Special Cycles and Key Functions BS-D-KA77A-O-3

Special Cycles and Key Functions BS-O-KA77A-O-3

6-25

c·

._SEI

DEFER

FETCH

COMfv10N

/ADD Ov; i .... L!

i if --. pov

:OT- MB 15 (I): IIOP 4

PCI-.MA- EPCI ..... EMA

EXDW:
1 £j.EMA
J JMS+IR

1
PC+ I .... PC

IO~~RS
.. ..

I JMP

CAL

20. MA'1 MBI ---. MA

I~I
¢-+EMA

I 0 .... EXCY

IDLylc -.MB

•

• •

IIJMS-'lRI

•
..

,•

MBI--' MA

• •

•

EXCY W;MBI-+EMA

STROBE

j'E-3

JMPI

EAE

-I

lOT

1 OPR

TRAP

LAW

IIADOR 10 -17: MB+I ..... MB I

OP]

TRAP
FLAG
(I)

EXCY

•
•

I MAI.PC

]

lo ... AC I

I MBI4 (1 1:1

DATA
RQ SYNC
DLY ClK RQ
PROG RGSYNC

AC-'r~
--.AC

-.-MB

0-'AC

I ¢ ... PC I

J
I

~"'EPC

~MBI7 (Ill

IRPT(I)~
HOLE 7'
I ..... RUN
0-.RPT

I MBI"'PC I

M8 4 (0)

[B..UN (I ~_~~~

I
I

! ACVM8!
.... AC

I EXCY (~):: I
EMAI"'EPC
MB4(J)
MB4(01

MB4(jl

~$
1 1
:::

lPI~MAI$

1 ¥1~
VOP2

CRY

HlT

INHIBIT

•

.\18+1 IL,EPC,PCII
IN:
..... MB
--.MB DATAACC

• •

f0-'-PC I'DATA ROY
0-.EPC

IMB~'..ACI~
PC+I
.... PC

,
,

I
~ t

INST

1010

010

04
10
14

00
00

01
110
II

CAL
DAC
JMS
DZM

20
24

01
01
01
01
10
10
10

00
01
10
II
00
01
10
I I

LAC
XOR
ADD
TAD
XCT
ISZ
AND
SAD

I I
I I
I I
I I

JMP
EAE
01
lOT
10
I I 0PR/lAW

IEMAI-+EPCI

50
54

+
PC+I
..... PC

•
•

ITRAF BK: 1
PC +1
-"PC

BK RQ

~T
F

OCTAL

i
~

OP2: MBI3 (11: RAR
M814 (J): R.4L
MB i5 (I): ACSI .....AC
M816 (11:L:--.L
MB 17 (11; AC--.AC

OPI: OP SKI;::> ENYM38: ?':+I-~~C
MB5 (!): 0-.AC
MB6 (Jl; 0 .... L
M812 rll'7RAF'<01; ¢-.P-UN
M87 (11' M813 <I): RA'<
MB7 (ll·M8141ll: PAL

34
40

TRAP FLAG

AC~
...... AC

I3K1m

II
SP¢

I 0 ..... PIE I

~~!Si~BE

!0-'TRAP~ I

ACC

~~IAC0CRYl
-..AC
.... L

PC+ I
...... PC

RPTfll
IEMAI"'EPC
EXCY(0 ::1
RPT (0)
,
lMBI.EPC
EXCY (Il:: I
+
I EXCY(jl: 0 ... EMAI ¢ ... M8

I MAI ... PC

I MBI ... PC I

IrN(01
RJN(I

INST. DECODE

I~~~K

[10 P I

[STOP MEM WRITEI

¢ .....IR

MBQlCR

IMB0CRY:1
PC +1
.... PC

•

STROBE: ,SENSE AM?S TO T-iE ;/:8.
ALSO TO :q DL;Klr~G 1'"::";'('1 .

10T'MB 15 (j):!/OP4

IEMAI.EPcl

I rl

i0 ... xCTCY

EXD (j) : I _

I elK I PROG I DATA

, -, , , , • ,

AC-¥- MB --. AC

PC!
0 .... EPC

rTRAP
MB" ",.
(Il

¢.,.PC
¢--.EPC

IRUN STOp: Ql ...RUNI

R:JN r01:hLT

API

INHIBIT

IQl ....

TRAP (0)

I-+TRAP
FLAG

ISTART MEM WRIT§

IACI .... MBII L 1EPc' PC
_MB

(j)

rCT.TRAPiIl"
XCTCY til:
I . .TRAP
FLAG

I START INHIBIT I

STOP INHIBIT

I SAD

STROBE INHIBIT

II-.TRAPI
FLAG

AND

0-.IR

•

NOTES

fl-+XCTCyl

F-.MS

ISTOP MEM READI

IS~

1!~0TI

IA3

1'7

•

1SEL
RPT (1);1
RRB

SEE tEAE
FLOW DIAGRAM

lAI

I LAC 1 XOR -~D I TAD 1 xCT 1
I D~M
! DAC ! JMS~---

I~I •

~TART MEM READI

IA¢

CAL

IA2

y5 ...... I R

BREAK

EXECUTE

Flow Dia gam
r
KA77 A- 0- 4

60
64
70
74

I1lro

r
STROBE
INH

2 CYCLE
(IA31

~ MEMOR

Y
STROB E

crAWl

ICYCLE

nf3)

Flow Diagram KA77A-O-4

6-27

SP4

r- - -..,

i algs
I

rK'-----~SP fJ

L28

ra-r
D

ws'KB4_"

SP2

SPI

PA
W64f)
1(28 p
~

~~
~I

SP 3

T P 7--:--0..........'I.J

1,.hP1
APT I
I(EY
MANUAL (8)

(N~8DJ

-------~------BI~5

R401

K3¢

wH23

22 PIN AMPHENOL
ON CONSOLE

U V ewexey ez

SPEED 1
SPE EO 2 - - - - - '
SPE ED :3 - - - - '
SPEED 4 - - - - - - - '
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MA6(I)

MA~17J9)_

_
8'-84
1832

I
MAI3(1)

MA6~)

MAS 16(0) _ _ MASI6(re

u 80

MAI3(,0)

-v

-T

-5

MAI2(1)

18684
IB21

I
B

-p

I B29

MAI2{9i>

TB684

WB28
A23

SEL 2(8)

SEL3(B)

SEL¢(8)

SEL 1(8)

P-

eM
_M

---1B~4

W¢;21
A24
W021
A25

MABI3(1)
N

eH
eH

·E

A29

-,B684
N
828

16684IB27

-0
-0

W~21

M~I~~ _

MAS 12 (I)

W¢21
Al8

-v
-v

L _ _

I
1
1

E
J
H
I
I
_ _____________________ ..J

MA5(J)

MA5(¢)

MA4W

MA4(~)

SEL3--r~~r-~---_ _~r---_H~~
FtEAO f( IJ--=-~"""""'~SJ

SEL2-~~r--------~P~~-r------~--------_S~~

fRi~7u
I

L ___ _

- - -1

814

w0z/
A 21

'STROBE

lEO

2.3~CP(E20D)

u---

_ _ _ _ _ _ _- L -_ _ _ _,

NOTE:
I.

All

B684'S HAVE PINS C,M AND V TIED

TO GROUND.

7
16K Memory Control BS-O-KA77A-O-12

16K Memory Control BS-D-KA77A-O-12

6-43

5ELSMEAD1(1)B

5EL4MEA01(1)B

SELSI\WRITE1(1)B

SEL4I\WRfTE1(1)B

SEL7I\READ1(1)B

SEL6I\READf(1)B

SEL7I\WRITE1(1)B

SEL&I\WRfTE Ht}B

AIS

SEL 4(B)

SELS(B)

SEL6(B)

SEL7(8)

W02B
AI6
.r-1~------+-------+--------+-"""",

W02B

w028 r - 4 - - - - - - _ + _ _ ,
AI9

---"J-D

I
I
I

.8.. _____ _

•

RI~7

__ --L __

RIG7
I B!3

B!2

'i.. _____ _

, -

I
SEL 5~IH~AF~___________+-I_ _ _~U~T

~-<>SEL

E
-------

i
~,--oSEL41

I
P

MA5(1)

I_~<)C;:"]T

READ I CI)-:...:Hor;;:::lF_ _ _

-------

MA4 (I)

MA5<,£!)

WRITE I (I~M:..crAL1--_ _ _--=.:K:cr::::l

-=
J

SEL 4
II

t--=-4~Q S EL 6

I
I
I

I
I

B READ I (I)

1 814

SEL7,--~E~"~~~--~-----~----~H~~

I
D I
IWRITE I (I)

-TRI~7--

r - - - T 3 ----.l
I

I
I

I
I
I

K
_

II
------~

T2t\SEL 4,S

SEL 6--~Pa~~~----------~s~~

INPUT
T2t\SEL 2J>
(E28R)

L_________ ~ _________ -_

T 2t\SEL 6,7

INPUT
T21\SEL 11>,1
(E27R)

BI55
810

MA4 c1»

MA3 (~)

MA 3 (I)

NOTE:
ALL 8684'5 HAVE PINS e,M AND V

READ 2 (1)8

TIED TO GHO.

WRITE 2(1)B

INH(B)

:t ~~t~
---+----I~----+-=--<b
f~--------.f.....-------1. . . .:. . .6
::

AI8

..........

READ2(J)B

WRITE 2(1)8

INH(B)

8K£-2

7
32K Memory Control BS-D-KA77A-Q-13

32K Memory Control BS-D-KA77A-O-13

6-45

rBTls--Teiis--'

fBI i3 - "'""TBi ~ 5 - - ,

I N2,0

I N23

I
I

...H_+-'-"-<)I,...... ,

I NI8

I
K

IN 211

I
N ;
t---:-'----<.. CL 0 CK· B

M I

rI __ ~_ -Ji

, CLOCK SYNC (~)

IJ,

-- -

I
~ __ ~

L
1
'" BII71

':'

DATA

BGN

I
Vi
T
S I
U '" I
I
"I
____ ...l __ .-J

SYNC CI)

elK
SYNC (I)
PROS SYNC CI} --'--":"':"Clt

--1 ~~y ~~fF-n,~~ 1
PIE I

r:-- - -,

IBIG5,
BK RQ
Nr5
I~

I
I

1(11

H ~J-+,'---O BK Ra.
t - - - + - - -........-.L...-..-..:.:...u;:h,;---. . (K
K)

. -____~~H~
,
,
L ___ -1-___ -1

,......,\~~Ti·-

rS1I3- i N21

...V---:...i~.PR06.B

r---I----"""t'-------+-.....l.F." "22,

B--:-I~

, N23

, D

18"3- -liitss--'
I N 21

I
I

L _ _ -.-J

I
IN22
L _ _'::_ -1I

..-=-+--.

-IsiBg-

1L20'

PIE CI) B
(N (ll9V)

MUl,DIV

I PROG RQ

I NIB

N
M

OATA --4"'::"'IoIA}--l---l
RQ

I
L_ :=. J

filii" Tsigs - ,

I
I

INl7

INI5

I T

l(l<17P)'B

H I L
PROG INT RQ
,I
(N9H)
I
I
L-...

T5-DLY

DATA ROY

DATA ACC

'::

elK CNT RQ

ADO R ACC

INS OBK

rBiis-T---i

I PIE CI

- ' - _-_,
-l

L
TI

DATA· B

DATA-S

DATA· IS

CLoe K-B

MIS ~ CRY (B)

IDE I

I
I
1 BI~5
I N/5
I

~F__
I_.

PROG RQ

_ I I
- I L.PROG RQ
I
I

L _ _ - L __ --.J

eLK OVFLO

rsl13

":'

~~---~~

CLOCK7-MA

'::

I N24 L I
'l- I
I
A

DATA IN

~2.:0 ~--1

7
Interrupt Control BS-D-KA77A-O-14

Interrupt Control BS-D-KA77A-O-14
6-47

________~rF__________~~H~--------_+~J__----_____+~K~----~---+&---______--+M;.~_________+H~----------~----------_+~A----------_+~S----------~~T----------_+~U--________~
F -:82",,"1- - - - F-TB2~1- --- F -;a2~1 - -,--ya""iil- - -- , -re2~1--- ;-!Bztjl---- , ,-----IB2~1
CZ8
I C29
, C 3~
:cz~
leZI
,dz
,CZ7

lD3Z~~__________r£~
w¢2.¢

is 2~1- - - - - - - ICI8

I
I
,

,
,
f

A
I

I~
I

I
I
1

~--~ ,8

8
eLK 7--M A

~~MAWHEN API ISINSTAI!f9J.

r:-.----------,B 2~1

FI8

-T - - - - - - - - - - , - ; : - - - - - - - - - - , - - - - - - - - - - , - - - - - - - - - - - - , - - - - - - -

BZ¢I

FI9

. B2~1

F , B2~1

FZ¢

1 F-21

IB2~1
I FZZ

I
I

,
I

18201

, F23

I
I

I v

I 01

r iszi'- ---I

F26

MAt5IA

MAr7 IA

s
iBz~I-----

MAl,S IA

I
,,~REMOVE GNO*AOO 10K TO-15V FOR API.
I
~~~~~~~I~~~~~~~ ______________
Ml;14IA

F~B2¢'-F 32

F3~

-- - F -l,

,
I
I

NOTE:

MA 3,4 t PC ~~LB20t's SUPPUED WITH
MEMORY..EXTENSION CONTROL TYPE ~
MA5~ PC5 9201'5 SUPPLI ED WITH 6K
MEMORY OR LARGER •

... E·1

7
MA and PC Registers BS-D-KA77A-O-15

MA and PC Registers BS-D-KA77A-O-15

6-49

wrJJ2

;aJt--- __ h_mr u F - n-~:f'--------- .----1"::'------- F----I~rrn----- F----Tig,-m n -- •--n~wmn--- r----,iw--~~--~l~--u:.~~rn-n-- F----rB~rr-n--- F---~
1Bi~~A~________________~8~______~________~~________________~D~______~________~E~________________~F~--------~------~~----------------~J------------------~K~

I '¢J MBG !

9 _MB
ACI-MB
Ae ¢ (I)

AC I (I)

! AC4(1)

AC 3 (I)

AC 7 (I)

AC G (I)

AC 5 (I)

ACSC!)
I
I

PC'-MB
LIN K (I)

PC 3 (I)

DATA AC C
D1 ¢ (I)
SA ¢

on (I)

(I)

MB~

peS{I)

PC7 (I)

peS(I)

0140)

o I6 (I)

017 \I)

018(1)

5A4(1) --t-"'"tIt'I

SAG (I)

PC 5 (I)

~4-----~--------~~~~--~~--------+C~~~--~~--------~~~~----~---------+~~~t----+---------+~~

'-------- -T - ---1

1
1

I
I

:MBO
,'C RY

:B620

'?M

:B620

:B6~

4?M

1862~

4?M

, ID¢2
-:!:! __ -- - - - ---- _ -'-I 10¢4
:f
L_
-------- - ---- --------- -- - - __ -":..._______ - _ - - - - ____ . _____~
":- _________ ____ 1.IID~6
_ ___________________

-= __----- _______ J.: ____________________ :... _____________
'''*8

,86211

10U~
1 __________________
..JI

W¢2¢1,-________________________________________~------------------~------------------~--------------____~------------------~--------------------------------------~
18i

rS2~
I

,------- ------ --- F------fS2(ii- --- ----- F----- ~ B2~1---------- F -----'B2~1-- ------- F -----;8-Z~I--------- F - - - -Tezi.--------- F-----;S"lj"I- --- ----- - F- --- -TB-2~-'- - - ------

Ell

EI2

EI3

EI4

EI~

:
I

EI8

I EI7

ACII (I) -'-__L. . .J

Ael2 (I)

AC 13 (I) -.-..................

PCII (I)

PCIZ(()

PCI~-.--~=

or 9(1)

01 "(I) --'--=-u"

0112 (I)

01 13(1)--+--~

SA 9 (I)

SA II (I)--·l.'

c
DATA

: EIG

v u

AC 16 (I) -.----....~

PetS (I)

ACC
1

D116(1) -.--~-,-,

,
I
1

,
,,I
,

__ ~8~
L ________ .,- ____ _
I

,
,
---.L----- - - - - ____ - - - - ...1.- _________ - ___ _
r

U T

rAL._-f 1\:..:=-------\

- - - ' - - - --- -----,

I
I

:(DI¢S,T)
:

MB+I i

18620

,9620

: IDIQI

: 1012

MBI!3U)

IB62~l!-t

'IDI4

MBI2(1)

i86Z'lM
: 1016 ':'

'---- --- ---=-- - - ----- -- -- -- -"--- - -::. -- - -- --- - - - ----- --- -- - ------------1---- - --------- - --- -- -- - - ---- ------ _____ L _ _ _ _ _ _ _ _ -

Met5(1)

':'

MBI7(1)

:86Z~~

---- -

-- -------- -

--- -

-- -

12C'J:.r
I

1018 ':'
-:::::
__ J. - - - - - - - - - - - - -- - - - - - - - - - - - - - -- - - - - - - - - - - - --'
I

7
MB Registers BS-D-KA77A-O-16

MB Registers BS-D-KA77A-O-16
6-51

W~lZ¢ ,.--A------------------~B~------------------C~------------------.~O------------------~E------------------~F~----------------~H~----------------~~----------------~~K-.I

~B"2

-,-

: HJ 3

I
I

, HJ 5

HJ4

-HF- - 1B2'~
- - - - --- -

- - - - - - - - - - - - -·1- - - - - - - - Iq, - - - - - - - - - - - - HF -;-B2 ~ - - - - - - - HF- - Tj821~
HF
IB21~

HJ 2

,HJ8

I
I

I
1

1
1

_AC----~~AH·--~----~----~~Ar+--~----~--~~~~--_r----~----~.u~--~----~r_--~~~~_4----_4----~~~F_~~~~~~~~~~~~--~r_--~~~~--+_----+---~~~

LI NK(¢) -.----~-"
RAR
L1NKO)

ACSI~AC - - - - f - - t I

ACS ¢

(I) ----+--.t

ACS :3 (I)

ACS I (I)

ACS8 (I)

JP
...----'--(J II N)

M:.f;
CRY

At:.

C~Y

AC0 (~ --t-=-=.t

; AC 1 It/J)

:AC

2(t/Jf

:AC " "fJ)
'

1
,
I
I
I
1
I
I
L ________________________ ~ _______________ J _________________ ~ _________________

:AC 7 ~)

iAC 5.
I

I
I

L_______________ J __________________ L _____________ ------l------- _____________ ~ ______________________ J
I

•

7
AC-Register (Sheet 1) BS-D-KA77A-O-17

AC-Register (Sheet 1) BS-D-KA77A-O-17
6-53

---,------ ---T------ -- H.J- ,821~
Hoi

Hoi

18210

I HJI4

1 HJI3

rszl~r

I Hil5

I HJl6

I
,

--T-------- -----,

,HJI8

HJ(7

- - -- - iiJ-- TB2if" - - - - - HJ- - fBZli -- --- HJ- - -,-I 821~

1821~

IHJI~

I
I

I¢ _AC--~-!I'!

AC8 <¢

RAR
Ae 8{J)

8
RAL
ACI¢(I)
M~-AC

Meg r/J)

I
I ACSI-AC
ACSI2(1)

ACS 9 (I)

AC513(1)

C--AC

)lOA_AC

END
CRY

I
IMaIOlO

I
I

t-----i-I-----p:~'" f----"-----~~.

AC C RY

AC H/JI

: ACt4<qn

'-- __________________ -L ____________

I
I

147ft

I
I
LI _ ________________ .JI

I
I
I
I
I
I
- 1 - __ ~ __________ J. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ L _______________ .1 ____ ._________ -L _____________

1 _____________ _

-f-NOTE:

SEE O·7-~-4¢ FOR
CONNECTIONS

7
AC-Register (Sheet 2) BS-O-KA77A-0-17

AC-Register (Sheet 2) BS-D-KA77A-O-17

6-55

MBM 0 (!2l)

( D

( 0
C D

MSM 1(0)
E
E

MBM2(1j)
H

MBM 3 (0)
K

MB M4 (0)
M
M

MBM5 (Ill)

MBM6 (0)

S
S
S

~ BMII!! (QI)

MBM 7(0)
T

( D
( C
C 0

V )C04

T
T

V )CQl5

V )C06

E
E
E

H
H
H

MBM 12 (0)

MBMI3(~)

MBM 14 (0)

MBt-i 15(0)

M8MI6(0)

foil

S
S

MBB3«(IJ)

MBB2 (0)

MBS I (0)

t
1
1

'---

-H

-E

-0

P N

I<
L

'--

8684

(")

E 0

'---

? 9" so

E 0
~

I
I
!

8684

I
I

I
!

r. 9" BO

tMBBB(QI)

'--

BO
E

I
I

VJ w021

-r

-5

tMBB IIJ (If)

MBB9({6)

V ) C~7
V ) C{l8
V ) elll9

8684
011

'---

i684

Ol!

E D

I
I

I
I
I
I

MBBI3 (0)

J30
1146612(0)

MBBI4 (Ill)

MBBI::' (0)

MBBI6 (121)

MBB 17(0)
4

-- -- - --..,--- - -- - - - - - ---r-- - ------ - - - - ,
- - -B684
8684
86B4
I

-- - --- - --,--- - - -. - - -- - M8BII(0)
-- - , - -

E 0

-p

-M

MB87(0)
- - - - -- - ---,--- - -- - - -- - ---,--- - MBB4(0)
- -,- -- - MB86
------ - - - -r------- - MBB5(0)
8684
B684

M8M 17(0)W~21(3)

A
MBB~ (0)

'---

015

-P

I
I

017

E 0

I
I

'---

019

Lr-~~-f-_l_-f--~~'-f-_l_-f--~~~f--L-r--~-~-~f--l--r--~~~f·-l--r--~~-f-_l_-f--~-~-f-_l_-f--~-~-f-_l_-f--~-~r- _
SO

MB~(~)

MBI«(I)

MB4(~)

MB3{(Zl>

MB2tlll)

"'M

MB6(~)

Ma5(,)

MB7IQJ>

9- '?

M89(~)

MBBle)

?rn Cj\. BO

M8IQj(jlI)

MBIII¢1

?M ?y BD

M812(tb

M813''''

9M 9v 10

M814(P'

MBIS(,¢'

<;>

MBI7(~)

M816(,0>

B
W¢21
J~

~~--------~---------;~--------~~-------;~--------;r--------~~---------r~------~~

,,(I)
MBB I
MBB2
MBB3(1)
MBB4
MBB 5
MBB 60)
M887(1)
--------- ---T--------------T---------------T---------------T--8684
8684
8684
B684

MBB

r--

(I)

----T---- -------

CI)

(I)

eE
eH
eK
eT
ev w9J21
~~--------~~------~~--------~~------~~--------~~--------~--------~----------~ J32
MBBIIC!)

022

023

024

02~

MBBI2(1)

MBBI7(I)

- -,

B684
028

____ 1I ________________ I _________________ I ________________ I ___________ _

MB3(1)

MB 2(1)

M8 4 (I)

MB6~1)

M85(1)

MBB(J)

M87 U)

MB9(1)

~e-D---------------------e-H----------e-k----------e-M----------e-p----------e~s----------e~T~--------e~v W,,21
~~------~~--------~~------_;~--------.r~------_.~--------~~--------~--------_x~N4

r-I

AC80m

ACB 1 (I)

--R650-

---r--

I
I
I
I
I

,L __ o
I

__ ...L_

AC~CO

AC I (I)

-.--- -R650- --.,--

ACB 2 (I)

Ace 3(1)

--R65"j-

-"'

ACB4(1)

ACBS(I)

I
I
I

I
I

I
p
I
__--L._

o
AC.2U)

AC 3(1)

AC4(1)

ACSCI}

__ .1. __

MBI2(1)

MBI3 en

M814 (I)

ACB II (I)

I
I
I
P
I
__ ...1-_

I
I

I
I
I

AC G (I)

AC7 U)

__.1.- _

D
_____
ACSCIl

MB 17(1)

M816(1)

AC9(1)

ACB 13(1)

AC 1.0 (I)

AC II (I)

AC120)

AC 13(1)

I
__...1-_

A CBI4(J)

---r- --R650-

--"""1"-

MI0

__ .1.- _
ACI4 (I)

ACI S (I)

ACI6(1)

AC 17(1)

NOTE:

ACB9i1l
--.,-- .AC.8U)
.--R!V- ;-i-

M 81 S(I)

_________

ACB 7 (I)

MBII tI)

----~-----------MBI(I)

- - __ I _________________ LI ____

ALL B'84"'5 HAVE
PINS K.. L~U JUMPEREO
AS SHOWN IN D 3.

7
MB and AC Bus Drivers BS-D-KA77A-O-18

MB and AC Bus Drivers BS-D-KA77A-O-1B

6-57

(J28E)

411\
~-'V\r-.( J 28 D)

----,

INPUT (RAL)

r------------------,
:
8124
!

~~4-r-----------i

I 81,5
L, Mel!

: F II

~
I

EAE

EA£
SHIFT

AC 17 (Il

_~H4-~_----~--~~4~~~

.R~L.
t JZ9M)

INPUT (RAR)

BI~41

L31

8210 f'"

HJI9

EAE

RAR
(J291(,)

P
0

~~~

I K

RAL

I
L
________________

12~1\

------------------------------,

r
5

AC¢ W
I

LEFT ROTATE - - ' - _ 0 ' "'

I
I

( K32K)

R
EAE - F tB)----..-P-(I< 32V)

IL- _ _ _ _ _ _ _ _ _

p
I

MQ ~(I)

I L--____________________________________

I ______- ________ -L
I ____ _
____ _ ..L

VLEFT SHIFT
(K32E)

LINK lI)

~15V

8123

iL ____________________________________
H2~

____________ J

1211\

r------------------------BI24

---I

(FORCE E SET)

(LlSS)

Mf)2

4701\

8Z/\

r---------------------~~S----_r--~~~~CRY.OET
r-------------, T
R

JIIS:

-------

.1135

~I\

-= I
- -- ~

olC CRY
(1<_50)

JI2S

.1145

(F270)

------------------ --~~~-------------- ---------------------- ------------------ ---~
E

1(11

START MUL,OIV~I~D~~------------------~~~------------~----~~~----------------------~~~------__________~--~
(K32P)

___ ': ___ .1

~------------------------------------------------------------------------------

JI!S

82n.

JI6S

NOTE:
JI75
JI8S

ADD

Ik TO -ISV

OUTPUT OF

821ffs

ONE AND ZERO

BITS

LlNIC 1,2,17.

JI9S
:I'

NOTE:

•

-f SEE DWG.O-KA77A-O-9
-'I;

SEE OWG. O-KA 77-0-17

Central Processor Modification for EAE BS-D-KA77A-O-19

6-59

Wt521

SIGNAL

CABLE CONNECTORS
I
I
I

24- 32K MEM

24-32KMEM

16-24K MEM

AI6-BANK :3

AI7-BANK 3

AI8-BANK 2
BZ9

BZ9

SEL

e£

SEl 6 • WRITE

HZ3

T2" SEL

SEL 4·REAOHn B

IND

MB 2 INO

HZ3 ,
.' INHIBIT IND

MB 3 INO

3 INO

3IND

SEL S'WRITE,m B

MA 4 IND

PC 4 INO

MI 5 IHD

MA 5 INO

PC SIND

WRITE 2 INO

MB 6 INO

MA 6 INO

PC 6INO

Me 7 INO

MA 7 INO

7IND

MA e INO

PC 8 !NO

.1<

MB 9 DID

MA 9 IND

PC S INii

MBI~

MAl.., IND

PC I,INO

IWRITE I
I
I

.. WRITE 2(.) B

"WRITE 2mB

6 (8

SEL 4 (8)

SEL 7

Ma 4 IND

IND

r
I

SEL 7.WRITE
SEL

Me ~ INO
M8

INO

AI9·BANK 2:

STROlE 4,5

E SEL 4· WRITE !U) B

SEl 5. READ 1(1) B

lIND
2

E 32-CONSOLE

STRODE

READ

16~24K MEM I READ

T21\SEL 4,&

.H SEL 7° READ
el(

032-CONSOLE

Oltl -CONSOLE

UNLESS OTHERWISE SPECIAEO

READ 2 U)

(B}~;I

e
SEL 5

WIlITE 2 (I) It

(B)-l,;1
~

IN H 181

-2 \\'028

Me BIND

Me II

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INO
INO

. . 12 IHD
M8 13 IND

Me 14 INO

MA II IND

PC II INO

MA 12 IHO

PC 12 »to

Mol.., INO

PC 131NO

MA 14 IND

PC 14 INO

PC IS tNO

MB IS 1ND

MA 15 INO

MB 16 INO

MA 15 INO

PC 16INO

MAI7 INO

PC 17INO

MI 17 INO

'______________ :. ______________ Vj~?P_ !~QI~~J9~_ ~~!-~_ ~9!'.J_~~C_~~~? _________________________ _
8-16K MEM
A2f1-BANK I
B29

8-'&fCMEM
A"2I-BANK 1

.-81< MEM

A22-BANK'

A23-BANK fI

BZ9

H23

SEL 2- REA01(\)B

SEL ". READ

SEL 2.WRITE 1(1) B

'-81< MEM

"')8

SEL (j WRITE I(')B

STROBE 2.

SEL I

SEL 3- READ1(1) B

H23

MA8 91}.\

MAS 13 el)

MAS 90)

MAB 14

MAl 14 (I)

MAe 6 "

MAB • •
MAS ., (I)

READ 1(It B

SEL I

·2 WI1I28

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HZ'!»

CH~ P.KG

C2-JA) PKG
J29

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MA8 IS ~

MAS 5 U)

MA8 H •

MAS 15 CI)

MAS

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MA 6(1)

MAS n en

MAS 7 (J)

MAS 12 ..

MAB 16 (I)

MA 7(1)

MAl 8 .

_S 12 (.)

MAB 17 fI/J

Mol BC,.

Moll 13 "

MA8 17 (J)

IMS 8 W

l..!:::::::r----------00L...J

16-24fC IIEII

A3,2-BANK (I

A31-BANK I/J

~-eK MEM
A3"-BAHl< tiJ
HZ4

8-151( M[M
A29-BANK I
HZ6

MAl 7 ,.

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H25

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16-241( MEM
A2B-BANK Z
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WRITE 2 (J) B

1'-24K MEM
A26-BANK Z

8-16K MEM
A2S-BANK I

T21\ SEL ", I

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16-24K MEM
A24-BANK l
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C4-BANK Z
B<l6

8-1,fC MEM
C5-8ANK 1
8<16

16-24K MEM

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C6-SANK'
B_6

Mol 7~

MAS(I)

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CB-BANK 1

B"7

B~7

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C~-BANK •

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Mol 9 (I)

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III. USED ONLY FOR MEMORY SIMULATOR
.2. SEE 0-7A-"-13 FOR Wi1128 DETAILS •
• 3. SEE 0-7A-f/J-9 FOR WilZ8 DETAILS.

Central Processor Cables Out/In (Sheet 1) CL-D-KA77A-O-20

e (I)

Central Processor Cables Out/In (Sheet 1) CL-D-KA77A-O-20

6-61

W~21

SIGNAL

CABLE CONNECTORS
H 3 I-C OI'lSOLE

031 ~ r/OPKti-H31

CII

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SA 9 (I)
SA Ii! (I)

E31-r/O PKG-J 31

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DA 9 (I)

SA II (I)

ACS

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ACS

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ACS

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AC 2INO

ACS

3 (J)

AS 3 (I)

OA I~ (I)

ACS

4 (I)

AS 4 (I)

AC 4IND

ACS

5(1)

AS 5 (I)

AC 5 INO

ACS

6 (I)

AS 6 CI)

AC 6 INO

AC 7INO

SA 12 (I)

OA 3m

DA 12 (I)

4(1)

OA 13 (I)

ACS

7 (I)

AS 7 (I)

SA 14 (I)

sen
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OA 14 (I)

ACS

8 II)

AS 8 (I)

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ACS 12 (I)

AS 12 (I)

ACS 13 (I)

AS 13 (I)

ACS 14 (I)

AS 14 (I)

A(S 15(1)

A(S 17 (I)

STOP

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(F)

KEY OPN

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At 12 INO

SPEED 4

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AC 13 INO
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J29-EAE- CI0

PKG-J03

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K32- EAE-B03

L 32-CONSOLE
INPUT (C-A

<'1>

MBS 4

INPUT (TAD-CRY)

MBS

5 rg,

INPUT CAC- CRY)

MBB

EAE
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MBS ¢ (I)

MBB 9 II)

MBB 1 <I)

MBB 1(1 (J)

MBB 2 (I)

MBB II

(I)

START CPTC

MBB 3 <I)

MBB t2 (I)

lEFT ROTATE

M8B 4 ll)

MBB 13 (I)

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MBB 14 (J)

START MUL.DIV

MBB IS (I)

SHIFT

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MBB 7 (I)

MBB 16 <I)

MUL, DI V

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MBB 8 (I)

MBB 17 (I)

EAE- F un

MBB 10 «Il

MBB 6

SET

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N {6s-l",It> PKG-J 13

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N~6-l/0 PKG-J IP

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ACB 9~)

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ACB 10 ¢>

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ACB 13 rtJ>

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Ie 6 (I)

Ie IS (I)

Ie 7 (I)

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r/op I
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M 32-CONSOLE
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DATA RQ

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DATA IN

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DATA ACC

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SW SINGLE STEP

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DATA ROY

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MA 16 104

MB~ CRY(B)

DATA SLO RQ

SW REPEAT

MA 17 1,4

N ~I/O PKG-J{67

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PUN

PWR

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BGN

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T7
SP4
RPT (I)B

PUN

Central Processor Cables Out/In (Sheet 2) CL-D-KA77A-O-20

eK l

Central Processor Cables Out/In (Sheet 2) CL-D-KA77A-O-20

6-63

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6-65

REVISIONS

REV

LTR ECO NO

DATE

ENG

II-&-Y

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6-67

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STROBE

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6-69

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6-79

FRONT PANEL VIEW OF READ WRITE RESISTORS

FRO NT PA NE L V lEW

G691

IL
=========G~6~O~2:========IJ

G601
G602

X -AXIS

r-----~=_=_---__,

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G602

G602
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.-_ _ _ _-=-=-:-_ _ _ _...,

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G6020R G601
18 PLUG I

18 PLUG2

NOTE:
LETTERS

OF PLUGS ARE ON PRINTED
OF BOARD.

CIRCUIT SIDE

NUMBERS ARE ON COMPON ENT SIDE
OF BOA-RD.
18
PLUG
:3

PLUG

EXAMPL.E

I-C

:==3~~~:J:TO

1-3

FIRST NUMBER (I) REFERS TO PLUG

SECOND LETTER (C) OR NUMBER(3)
REFERS TO PINS.

NOTE:
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PLUGS

2. RES ISTORS ARE 125 OHMS.:!: 1%.

25 WATTS

NON-INOUCTIVE~

VIEW FROM COMPONENT SIDE t

Resistor Panels WD-D-149-0-51

INHIBIT
SUPPLYPOWER
TO INHIBIT POWER
SUPPLY

Resistor Panels WD-D-149-0-51
6-81

TOP

COt-JN

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CONNECTOR COIJFIGURATIO!J FOR. 'SEIJSE A\.ID If\lHI5IT WtIJOIt.JGS
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READ RETURtoJ E~D

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"' M EACH PAIR. OF SfNSf" WIU'DINCS WII..L 'Be: TW1STe'D.
EACH PAIR OF INHiBIT WIr..tDING.S WILL BE TWISTCI>.

lIf"* * LE'IJGTH OF CABLE'S FROM SOCKE:TS TO RE'A1e
HOUSI~G.

co~slsrs

MOU1JTi"'G PLATE'S IS 10 INCHE'S_
OF'"

HALVE'S BQLT~J:) rOGe:Tl-\e~
FOR EASY CiSAS$EM6LY

Memory Stack Connector Configuration CL-D-149-0-52

Memory Stack Connector Configuration CL-O-149-0-S2

6-83

Figures on pages 6-85 through 6-93 deleted (obsolete)

EAE
I
I
OPERATION
IF BITI=f
CODE

(64)

}::r~:,

.)
I

I
I

}

~----~------,I
I

BI T= I

:(IFEAE

ICOMMAND

1=00~

I ____ ..l.I ____ ....LI ____ ....LI ____ -'-I
L.
___ _ •

EAE

EVENT
TIME

t 1~ !

oj(

}

EVENT
TIME

3
EAE

INSTRUCTION BIT ASSIGNMENT

DELAY ADJUSTMENT
INITIAU SET ALL O£LAYS TO MAXIMUM EXCEPT:
!. D3~ (D-!??-{l!-S 03)
5~ NS INPUT (03~H) TO OUTPUT (D3¢L)
2. [)31 (0-177-0-5 C2)
ADJUST FOR MINIMUM
3. A27 (D-I77-(/j-6 05)
ADJUST FOR MINIMUM
FINAL:

ADJUST DELAYS AS SHOWN ON INOIVIDUAL PRINTS.
THE ORDER OF ~DJUSTMENT IS INDICATED THERE.

WIRING NOTE:
WHEN EAE IS INSTALLED, WIRE:
I. GROUNDS FROM LOWEST PIN IN EAE TO
DEVICE SELECTOR HIGHEST PINS
2. BGN:EAE (D2~L) TO DS(B3IV)
3. I-MQ EA.E (A23N) TO EAE (AI2T)

TI
T2

~EAE-F

STROBE EAE;

MUL'MQ17(l): 1-S'l'OP SH I '" , ,..,...00
DIV: l-SUB. .-I-stop SHIFT

l_EAE-f

"-STOP SHIFT J~""AOO • ~-SUB
MBlI( 1): AC0-L SET /CLR~ I NK

MB5(1): ~MQ
MB6 ( 1 ): AC0-EAE AC S I ~
MB6(1}' M87[0)' AC0!1 ):AC_AC
OTHER:

M812-17---d--+SC12-17

MB7(1) :
MB8(1) :

AC1-MQ
0-AC

(MQ"MQ
SETUP' MBI5[1): ~I_M~
~MQ
SETUP'MBI6( 1): MQ1_AC
SETUP' MB 17 (1): sel-AC
MB9(fI)· M81f1(0) • MBII [I): l_MUL
MB9(0) • Mill I!! 1 ): l_DIV,I-+DIV
FIRST
SC i2-i7~77: i_FULL __
MBa(S)' NORMAL I ZE ·ACI'lVAC1: 1-+FULl
MUl. 0.1 V: I NHI BIT BK RQ CN CP
EAE It SIGNVLlNK---EAE SIGN

MB9(1) :

START SH I FT

SETUP:

CLR

MULV DIV: START MUL, DIV,
9l-LINIiC

(M U LV DIV).EAE Ae

SIGH (I):

MQ-MQ
1_NORM

EAE Flow Diagram (Sheet 1) FD-D-177-0-2

6-95

DIVIDE

MULTIPLY

SHIFT

ADDER/SU BTRAC TOR

START/END

100 NS

~
100 NS

30 NS

20 NS

30 NS

20 NS

$ ~ ~
T

20 NS

30 NS

20 NS

20 N5

20 NS

~~ ~
nUL'
<fO(I)
~
70 NS

70 NS

OVE R FLO
60 NS

350 NS

STEP

COUNTER

SC 15-17=1 ~-----,

LOW COUNT
SC 15-17+1
... SC 15-17

HIGH COUNT
SC 12-14+ I
_SC 12-14

EAE Flow Diagram (Sheet 2) FD-D-177-0-2

6-97

()

E AE 1\"]') O· )LE /\1 AP

Iii

I I

I
:

A
I

! W ! W

rJ
B
B I eBB
B
B
B
B
B
B
8
B
r,
II."" I051¢51131113IC51,¢5113 502115 36,¢113 36,036,1'l3603,·,'

\~2.0'i¢211¢21113 1~51¢51113 I¢SI¢5

_ I1: ~ - r2-1-3

:E5

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I
~.

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i
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r
F

1'3

i
B

2 ()

2'3

:3 0

31R

BIB

I
11

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I-

I-i

¢21$121~21.0?li::";'1 ;"/112712/'1 ::11 2)1'1 <:'/1.2/1 ..:1/1 2012/'1 ?/I)'Y':I ":01

!
b

2¢1 201 2i2S12fl\1 104il7 61212 'I" 1¢51.¢41,¢436¢1(2i'5

r·+--+--+---+--+--I---+---ir--+--+-+--+---t----t--+--I----t-I--+---+---+--+--+---+--+·---I

I iii
I W Iw Iw I W W

I
w,w

1I r

117 36~ :6J 1t;b5

i6~P ,,:3 113 12912 2912 20'1,29' I 2'7 I 61z 114' 6,02 It5 60 7 29'4:204 2,0~ 19' 5 6¢. 1121461212 Ids 02fJ
I
II
~ I. ~~175~16~~1-7~I~A~~19~2~O~2~I~T22~-23~~~4~-2S~~=6~2~7~2~8~2~9~3~~~3~1~~~·~~

1'16'': I(Z S C/7 I I r 'i2SZllaiZI 1021 aiZI 0Z1 9121

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o wlw w!w wlw!wl't/
0211¢21 021 021

i
--1--

¢211¢211'7211~21 1~5 11215 '107 II~ II

-· T

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r:.

J."

1i ': 1':-

r - - - c - --1-_-- I

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I.

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26 ··.2..7 X8

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i

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r'm

b~
I

0..
""'-.Ie
""'-.II

(t)

-0

i
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N
I

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.,2

EAE Module Map FO-O-177-0-3

6-99

;a~5---l

START MUL
(83P)

DIV I 024
I
I
I
12¢J'\.
1

START SHIFT
I

T6 --.----'111

1
1

M B9 (I) --'----=..0...

li-

r------t--------/
1 BII5

IBIgJ5

1021
I

I
I

D2S2'

I
I

SETUP

E i
:

OTHER

I
1

EAE AC SIGN (I)
LINK (flI)

..,...._....s~

824

EAE

I
I

: M81¢CIJ
8115

1 __________
D24
I
j-

_____ l ______ -.l

82Il.

1- _ _ _ _ : _ _ _ _ _

LINK (I)

8117

AC SIGN (¢)

B
iSI/is- - ~
02¢

I
,

BGN

I
I

pas

-15V
I

t-'----,-. C LR

f-'-'--~EAE

I----~EAE

M
BGN ---'--"'-;:-'

r-----1
I BI~5

1018
I

I
I
I

r - - -- - - - - -j

I BH!'!5I
IL C31
____ ...JI

T3
EAE- F (I)

CLR POS
F

I R3¢2

EAE - F (I)

1 D 19
I

~--1~--t.)t--i>

IE
5H I FT -~I-=-DL2is;:L-.-.,....J

~ __ =- _

12¢fl

I
I
~-----.J

:
I

seo v (I)

:L-________________~------------------~~

: D9

-= I
DI V

<¢)

~+---. EAE- F (8)

1---''----:::> STO PCP T C
(B¢3D)

1- ______ - - J

L ___

START

(83 V)

1
I
L ____ ...J

EAE-F(I)

12¢fl

~BIXr5- -j

p
I
I

S
R

eo UNT

(C19 F)

r;-----j
I BI05
I
1 D2~
I

START
MUL, DIV

(B¢3H)

LOW

START

!-'U=---_-l> START CP TC

INPUTSETUP

IT:

IBI~4

~g9__ ~

NOTE:
I. DELAY ADJUSTMENT
DLY
8, DI9 UPPER
9, DI9 LOWER

BKE-l

D
PROBE I
CP K21J
CP K21J

PROBE 2
CP K21 K
CP K21 K

SYNC
PROBE I
PROBE I

CONDITION
LEVEL TO FALL lOONS AFTER PULSE WHILE SHIFTING
AS ABOVE WHILE MULTIPLYING

7
EAE States BS-D-177-0-4

EAE States 8S-D-177-0-4
6-101

4
NOTE:
I. DELAY ADJUSTMENT
PROBE I
DLY
10. D3(1j
EAE D3Q)H

PROBE 2
EAE C25J

SYNC
CONDITION
PROBE I. PULSE 50NS BEFORE LEVEL CHANGE BEGINS

-15

-15V

-15

-15 V

-ISV

-15
1.5K

BGN

I.5K

POS

,
I

B ~Biis- - i
I DI~

I
1
,

L __

HIGH:

,
I
I

K COUNTI

/--

r-- ---,
I

V U

LOW

MB-SC

,COUNT
IT,

MBll (I)

BI!lS4 :

Bl3 ,

L ____ J

SCI3 (I}--,--..... '

SC 14 (1)-1--'-41

I
,

IBII5

L_B_2~

COUNT) - -..........!..£lI

f-----.-+LOW COUNT

,- ----,

5CI5(1)
SCI6m

r----,------,

IL _=-____
_ 018 '--II

I BII5

I
I

SCI7(1)

__ J

SHIFT IDE
I
BI~5

LI
SCI6U

L_-=______ -=_

47fl-

r
I

COUNT

BIIS
I DZ6
I

I
lii"..L--T-J

,g:~3

I
I

SC I 7 (t)

I
I

EAE T 5 t f f i

: CII

MBI7 m

1
I

SET UP 1 S ;

-= I

:
I

~BIi 3 -:!Sv~ 5
I CI2 31'1

r--

MS .... S C

FULL~I en7 "Iv
I 824 A

LOW

I
..J

IDI3~L
PA
N
SCI-AC

EAE T3 1 U
OTHER

SCI4(1)

1 T /\
L ___ _

I
I
I

j--

______- .JI

SC 15 (I)
SC 16 (I)

I
I
·L _______ -.J

I
I
~

I
1
L ___ ~

ACBI (t)
BU·2

7
EAE Step Counter and Control BS-D-177-0-5

EAE Step Counter and Control BS-D-177-0-5
6-103

CMA

r------,

r------,
START

(C 10 D)

I BI15

MUL.DI V-4--=L~

I
I
I

: BI¢5

MBG (I)
MB7(¢)
ACB¢(I)

AC¢ ~)

IL ______
09
JI

ACB

¢m

1\: DI¢

~
I

'l...

_--,---=-L W~~ 7

r-B1 i3- -

HIT
F

: AIS

CLA
(C I¢ S)

EAE

-i

MB5(1)

L--T.----

l. I

82fl

I BI¢5
I A21

~-----.I

DET

____________________________

:!:- I

AD
R T _ _ _--"--F B 602

CML

(CIr.5E)

(C qip)

(CI,0H)

(0100)

XOR

CRY

47fl

RECYCLE

I
I

LFT

C 21

SEE NOTES

I C31
I MUL(I)
L-------~DIV (I)

r----

A24

EAE T5
STEP UP
MB 15 (I)

8105

U L>DI V·EAE AC SIGNCI>:- - - - - - - ~

A21

P.M

r-------,
1 8115
I

471\

I
I

I BI~5 -

A
N
_ _~R 860'2

(c 2¢V)

1828

R
~~-~RESET

ma;

1__

ADO
PULSE 3

ADD--I'>r--...!.:R't>

SUB

~MQ

E~C

(C I¢D)

B105
DI~

~-:------~--------------ADD PULSE 1

~
C21

(C2¢L)

~------+-----------------------~-------+-r--~CMA

(A29N)

I.. _ _ _ _ _ -l

,-.-------- ------------------------

ADD PULSE

L ______ J

L ____ _

CRY

I 015
:
L _____ .-l

I
I

E,C

BGN--+--~

:8113

II;

T7
J 'L,
MUL, 0 rv o ----L---'-4I/\
AC SIGN (I)

-=-

M88(j}~

'l...

I BI13

I A26

E A E 13 -+-.------=-.

t-BI9fs- -..,

r-----~

EAE F (I)

r:---------.,

---'"""--- I

K
L
J 'l...

LI NK
(C 10 T,)

IPAlI-'N.!..--.... SET

017

1/1.24

EAE T3

EAE T3
MB4 W

r-I

;eils---- l

~TI1-i- -~

v
T

12¢fl

ADD
PULSE 4
CLR~I----~-4----~

~Bli5- - ADD

PULSE 1

I
I BII5

- - - - - -r1

: DI';

02~

EAE T5

SET UP

IL ____
-= _

ADDER/SUBTRACTOR
NOTES:

I. DELAY
ADJUSTMENT
I. A29
2. A28

3.A25
4. A27

PROBE I

CP FI0T
CP FI0U
CP FI0T

EAE A27H

PROBE 2
CP FI0U
CP FI0R
CP EI0L
EAEC2SS

SYNC
CP HIID
CP HIID
CP HIID
PROBE I

CONDITION
lOONS BETWEEN LEADING EDGES
lOONS BETWEEN LEADING EDGES
lOONS BETWEEN LEADING EDGES
lOONS BETWEEN LEADING EDGES

MBIGO)

lt1UL,DIV
E AC SIGN (I)
E A E - F (I) --i--=-=-.!

L ______ ..J

SEE NOTES
PROBE I TO PROBE 2 WHILE
PROBE I TO PROBE 2 WHILE
PROBE I TO PROBE 2 WHILE
PROBE I TO PROBE 2 WHILE

DIVIDING
DIVIDING
DIVIDING
DIVID ING

on·a

7
EAE Register Control BS-D-177-0-6

EAE Register Control BS-O-177-0-6
6-105

I
-15V

I B I ¢4
1 B 29

829

-----------------

N :

1---~

-------------------

831

47Il

SCOV((O) --:-I-«:';~

~~--~

~-----I BI~5

I 8105
IL ______
B 31

R 1

K
0

r------,

r--------- --------------~--- ---------------~----,

r--------,
I BI!2l4
I

sue

ADD

R E -CY C LE

BI¢5

~~-~~~~-.J :... ___ D~ ~

l-=

t<
J

47Jl

IOVFLO

EAE
SIGNel)

EAE
SI6N(0)

: OIVW

INPUT

i-MQ

¢-MQ

- --- - - - - - - - - - - - - - - - - - - --- --I

rT-;r:----,/i-'KriJ

RESET

EAE

I
I

f------

181915 D

81~5
C31

I C 27

I
I

~~A~--~----~~------_+~~v_--~----------------~uu

~-L

E':.~1:BJt5--4:--:---4:------4:-T~~F~6:
i

--------------- --------i
T u
I

CMA

B6ei2 P,M I

Cf9

8105

'\...

L ______ ...J

DIV FI RST (f6)

-=
-=- C22
-=
L_______
l ____________
l ____ J
1

-=81¢5:
B27 I

47Jl

- - - - - -- - - -

- - - - - - - - - - - - - - - - - - iii

- - - - - - J

- - - -l

-- -------------,

1-+--------------

-15V-JVv---+-~)[]i,JF

L __

RAR
CIf6 K

I,0'K

.,5..-+-_. RAL
81,0'4

(t I¢M)

C2jJ

SHIFT

RECYCLE

MQ LFT

/VlQ RT

--,
L
SHIFT
.~~-SCOV(I)

~----- J_

~--'---M uL(I)
~'-t--

I
I
I
I
I

B\i5

+ ________ _
OIV(1

U V
T '\...

I
I BI!2l5
,L _______
C27
I
...J

: B 1¢5 -=

BI13

023

PROBE 2

CP EI~J

CP FI9JU

5 830

6 D31

SYNC

ID29'

lOONS 8ETWEEN PULSES PROBE I TO PROBE 2
WHILE MULTIPLYING
EAE B30N EAE CZ9E CPHIIO 35NS BETWEEN PULSES PROBE I TO PROBE 2

INPUT
SET LINK

ADD PULSE4 .... ---~

CLR

POS--~R~_.----~

I
I

Blf5

8115:

L ____ .!?~6-':' ____ ~ ~..J

CONDITION

CP HIIO

INPUT
OVERFLOW

LEFT
ROTATE

(B3K) ......- t - -.....
H

LEFT

I
1

ADJUSTMENT PROBE I

MB I 0' (0) _-+---....:;;...,o~

iBT~5- - ~

I. DELAY

RI
D I V (I) - t....:rfJ-;---t-....U\ I :

I
NOTES:

MB" (I) ---+----~

IL C27
_____ ...JI

- --I

8113- - - - -- - - -

E A£- F (f) --+---...:.:..:...~.

-T-----------~-------------L-----------~

-fSV

Is0Jl

L
K

: 023

IC 22
I

--,

I
I

-I-T

I
H
M UL (() -...;I---~..-:I\l

026
I
L ____
-l

I
I
LlNK(¢) R
____________ 1I _______________
FULL(¢
I

!8105

SIGN U)
EAE

SHIFT
(83E)
I

-= ...JI
L ____________

S HI F T---.---."--L>..J

oI V (I) +---.-------"-UVI2-s:.J

L. __ - -'-r - 7--: _

r WHILE MULTIPLYING
7 A30
EAE A~ EAE A~ PROBE I 350NS Of( MINIMUM WHILE DIVIDING
Ii A:3CUPPER,EAE A3¢P EAE MrJV PROBE I MINIMUM WHILE DOINS SIGNED MULTIPLY
LOWER
aF NEGATIVE NUMBERS

6
Main Time Chain B5-D-177-0-7

Main Time Chain B5-0-177-0-7
6-107

W¢2¢

A5C:~t~A'-------------~B'-------------~----~-_--==--_-~~--~-------.--==~r~~--·--~~-------J[~~.--------_------~H--------:=.-----J~------------~K

~ I 8201

-,---

AC B.¢

---

I
I

AC e2(1)

K L

AC I_M Q -+-......----.;;~I'I f--------~_tI
BI13
(I) ~-+-....=...~.

F B201
BI3

I
I
I

I
I

F B2~1
B II

I B I¢

f------------~~~~--------~~
8113
ACl! 5(1) J 1\

All

~-------8~.n

-ISV

1.5 K

1.5K

W¢2¢

M ______________~
~5L1~L______________~~
N______________~~
P ______________~
R _______________+~S--------_______+~T--------------_+U~----_4------~~V

182Tt - - -

};rs2~

I 814

---

I B21

~¢1
BtU

I
I

r 816

I
I

---

I BUi!

r I 8201

F B201

-- - Fl
I

c
MQRR
MQ 8 (r:)

MQ RL

MG I~ c¢
1~~~~--~~~r----------+~~------------+-~0------------+~~------------~~~-----------+~Ar~~~

AC~MO~--~~~r------~~~~-------~~

AC B 9(1)

8113

ACe 10(1

AJ5

-------

-~-

-- -

- -

- -- -- - - -- - - -

AC e 15(1)

IACBI6 (I)

I
-L-.
_

1\ B IL!

0
_

_ A22
__

-' _ _

D
MQ Register

B5-D-177-0-8

MQ Register BS-D-177-0-8
6-109

4
MBB 7(1)

~--- -T-~ i- B,~T--- -- -i-~
I

MBBI~(()

MBB9(1)

MBBln)

MB812(1)

--T-}

-=
-=
-=-=-=-,1
L _________________________________________

W021
BI

MBB4(J)

M8B3 CI)

iii
t
t:

W021
DI

MBB2(1)

MBSI6(1)

MBB 17(1)

N
L

p
I

-=-=-=
-=-=____________________________________
JI

MaBS (/)

iii

MBB6(t)

MBBsm

MBSl50)

I
E
: ,..-=.O,--;;;u---'

MBB I (/)

MBB I 4(1)

Bi¢5-

1
:

MBB¢ (I)

MBS 13(1)

----,t-} --- -r --- i-r----H -H-----} ----- H-----f -} --;

t t 1:::~:1:~l:~t~t~t~t~t~t~t

t t

7t.NOTE:
MBBS ARE SERIES
AT DRIVE END.

ACB¢(I)

;SI¢"5":" I

AC BI(I)

ACB2(1)

ACB4(1)

ACB3 CD

-~-----

,---I BI ¢5

AI¢

IAI3

I
-F

ACB 6(1)

ACB7W

ACBSU)

ACB9 til

ACB lo(r)

AC 811 W

ACBI2(1)

ACB 13 U)

ACBI7(1)

-t-----

---,

I
I

ACB5

TERMINATED

_____ _

A6 I D
__________________________________
______
________________
W02
E
K
M ________P
S
T
V
L-~

I
I

BItE-.

7
AC Inverters B5-0-177-0-9

AC Inverters B5-D-177-0-9
6-111

2
W021
EAE CABLE TO

SIGNAL

CABLE

4
CONNECTORS

Mel IN 01 CATOR
CABLE 2A ~5

:~:~~~:~

EAE CABLE TO IO

LENGTH

2~¢6-IL06

2A<P7 -IM0'6

M,]~2 IN D

ADD +B!

SUB

SHIFT-R

!e8!

ACB~ (~)

ACS¢,9(0)

MQ~3

IN 0

EAE F

ACB!i11

ACB I¢ cei)

MQ¢4

I NO

MUL

ACI:l~2(¢)

ACB II ('if)

MQ.¢5

INO

DIV

eE
eF

AC!:!¢3 (i)

ACBI2 (0)

"'Q~6

IN 0

EAE ;SIGN

ACE,04 (~)

ACBI3 (0)

(0)

ACB~5 (0)

ACBI4 (0)

,."

ACB 15 <¢)

I~Si.

(Q!)-rTI

ACe 16 (Q!}~T

ACfj~8(0)~

ACB 17 (0)-l.v

ACB.¢7

MQ,07

I
I

ACH16 (0)~SI

IN D

EAE AC

FULL

MQ(39

IN D -1.L

MQI0

INO

---t..MI

SCOV

MQII

INO+N!

MQ 12

INO

+PI
TRI

:~ ~ ~::-g
MQI7

INO

C P CONTROL
M8 BITS FROM CP

EAE

SINGLE
V STEP

EAE CABLES TO os

2B03_IN32

EAE CABLES

MB¢(I)~

MBB(oI (I)

MB~I(J)+EI

M BI0W

1>18s02 (I)

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WITH SERIES RESISTORS AS SPECIFIED

EAE Cable Schedules
CL-O-177-0-10

EAE ClISLE TO C P
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Reader Control BS-O-KA71A-O-7
6-137

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6-147

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Standard Device Selection BS-D-KA71 A-O-5

Standard Device Selection BS-D-KA71A-O-5

6-149

REVISI.ONS

REV

LTR ECO NO

DATE

ENS

A
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6-161

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6-163

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Terminator List (Sheet 2) TL-A-KA71A-O-14

6-165

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6-167

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6-169

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DC Power Wiring PW-D-7A-O-4

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6-171