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XX-4D495-A8

December 1964

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Document:	F-75P PDP7prelimUM
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F-75P

REFERENCE
MANUAL

DIGITAL EQUIPMENT CORPORATION

•

MAYNARD, MASSACHUSETTS

F-75P

Preliminary

PROGRAMMED

DATA

REFERENCE

PROCESSOR - 7

MANUAL

December 1964

DIGITAL EQUIPMENT CORPORATION· MAYNARD, MASSACHUSETTS

The information contained within this manual
is prel iminary and subject to change without
notice. Any comments concerning this manual
shou Id be addressed to:
Digital Equipment Corporation
Program Documentation Department
146 Main Street
Maynard, Massachusetts 01754

CONTENTS
Chapter

Page
PDP-7 SYSTEM DESCRIPTION ................................. .

1-1

Proc essor ................................................

1-1

Memory .................................................

1- 2

Central Processor Options ..................................

1-2

Input/Output Control. . . . . . . . . . . . . . . • . . . . • . . . . . . . . . . . . . . . . .

1-3

Input/Output Equipment •................................•.

1-3

Mass Storage .........................................

1-3

Displays.............................................

1-4

Analog-to-Digital .................•................•.

1-5

Card Equipment and Printer. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-5

Input/Output Systems ..............................••.

1-6

Programming System. . . . . . . . . . . . . . • . . . . . • . . . . . . . . . . . . . . . . . . . . . .

1-6

OPERA TI ON .......•..............•........................•.

2-1

Operator Console.........................................

2-1

Switches and Keys ........................................

2-2

Conso Ie Lock. . . . . . . . . • . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .

2-4

Console Lights. . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . • .

2-5

CENTRAL PROCESSOR ..............•..•....•.•...............

3-1

Arithmetic and Control Registers .....•....•.........•.•...•.

3-1

Control States .........•......•.•..•......................

3-2

Instructions ....•...............•...•......•.......•....•.

3-3

Memory Reference Instructions ................•.•....•..

3-4

Augmented Instructions .........................•......

3-8

Operate Class . . . . . . . . . . . . . . . . . . . • . • . . . . . . . . . . • . . . . . . .

3-8

Input/ Output Transfer (lOT) Instructions. . . . . . . • . . . . . . . . . .

3-11

Indirect Addressing .............•....•..•.......•.•.....•.

3-12

Auto-Indexing .......•...................................

3-12

Extended Ari thmet ic Element Type 177 ....•..........•.....•.

3- 15

iii

CONTENTS (continued)
Chapter

Page
EAE M i croprogramm i ng .. . . . . . . . . . . . . • . . . . . . . . . • . . . . . . .

3-16

EAE Bit Assignments and Operations . . . . . . . . . . . . . . . . . . . . .

3-17

Microprogramming High Speed Arithmetic ...............•

3-20

Instruction List. . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . .

3-21

Signed Multiply and Divide Closed Subroutines ..........•

3-23

INPUT/OUTPUT CONTROL AND INTERFACE ................... .

4-1

lOT Instruction.... . . . . . . . . . . . . . . . • • . . . . . . . . . . . . . . . . . . . . . .

4-2

Program Flags ... . . . . . . • . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . .

4-2

Device Selector (DS) . . . . . . . . . . . . . •. . . • . . . . . • . . . . . . . . . . . . . .

4-3

Slow Cycle. . . . . . . . . . . . . . • . . . . • . . . . • . . . . . . . . . . . . . . . . .

4-4

Information Collector (lC) ....................•.......•....

4-6

Information Distributor (lD) .........................•.•....

4-6

Input/ Output Status. . . . . . . . . . . . . . • . • . . . . . . . • . • . . . . . . . • . . . •

4-9

Input/Output Skip Facility (lOS) ................•......•...

4-9

Input/ Output Trap .. . . . . . . . . . . . . . . . . • . . . . . . • . • . . • . . • . • . . . .

4-10

Program Interrupt Contro I (PIC) .......•..•...•..•....•.•....

4-11

Automatic Priority Interrupt Type 172 . . • . . . . . . . . . . • . . . . . . . . . .

4-13

The Multi-Instruction Subroutine Mode ........•....•....

4-13

The Single Instruction Subroutine Mode. . . • . . • . . . . . . . . . . .

4-15

Priority Interrupt Instructions...........................

4-15

Real Time Clock. . . . . . . • . • . • . . . • . • . • . . • . . . . • . . . . . . . • . • . . . .

4-16

Data Interrupt Channel .....•..•....•....•......•.......•..

4-17

Data Interrupt Multiplexer Control Type 173 . . . . . • . • . • . . . . . . . .

4-18

Data Control Type 174 ................•...•..•..•..•...••.

4-20

MEMORY EXTENSION CONTROL TYPE 148 •.....•.•....••.•....

5-1

PR OGRAMM ING .....•......•.....................•..•..•.•..

6-1

CONTENTS (continued)
Chapter

BASIC I/O
EQUIPMENT

MASS STORAGE

DISPLAYS

ANALOG-TODIGITAL

Page
Assembler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-1

DDT (Digital Debugging Tape) ...........•..................

6-5

Editor . . . . . . . . . . . . . . . . . • . . . . . • . . . . . . . . . • . . . . . . . . . . . . . . . . .

6-7

Fortran ..................... . . . . . . . . . . . . . . • . . . . . . . . . . . . . .

6-9

Bus- Pak II ..........•..........•.......•..............•..

6- 10

INPUT/OUTPUT EQUIPMENT .............•.................•.•

7-1

Mechanical Configuration..................................

7-1

I/O Bu ffer i ng ................•.................•......•..

7- 1

Tel etype Mode I 33 KSR ..........•............•............

7-3

Key board •••......•.....•.........................•..

7-3

Tel e pr i nt e r . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .

7-4

Perforated Tape Reader Type 444 .......•.........•........•.

7-4

Paper Tape Reader Instructions .......•. •.••.•..... ...... ....

7-5

Perforated Tape Punc h Type 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-6

Tape Punch Instructions... . . . . • . . . . . . . . . . . . . • . . . . . . . . . . . . . .

7-7

DECtape .....••....•.•...••.•.••.........................

7-8

Automatic Magnetic Tape Control Type 57A ................. .

7-13

Magnetic Tape Transport Type 570 .........................•.

7-17

Magnetic Tape Transport Type 50 . . • . . . . . . . . . . . . . . • . • • . . . . . . .

7-17

Serial Drum Type 24 . . . . . . . • . • • . . . . . . • . . . • . . . . . . . • . . . . . . • . .

7-18

Prec ision CRT Display Type 30 .•............................

7-21

Precision Incremental Display Type 340 ..........•.........•.

7-22

High Speed Li ght Pen Type 370 •••.....•••........••.•.••.•.

7-24

Symbol Generator Type 33 .......•.•.............•.•.......

7-24

Multipurpose Analog-to-Digital Converter Type 138B .•........

7-25

Multiplexer Control Type 139 .............•...............•.

7-27

CONTENTS (continued)
~:hapter

Page
High Speed Analog-to-Digital Converter Type 142 ............ .

7-28

TELETYPE INTERFACE

Data Communication System Type 630 ....................... .

7-29

CARDS AND
LINE PRINTER

Card Reader and Contro I Type 421 A ...•................•.••..

7-32

Output Relay Buffer {18 Bits} Type 140 .........•.........••..

7-37

Card Punch Control Type 40 .•.....•..............•.........

7-37

Automatic Line Printer Type 647 . . . . . . . . . . . • . . . . . . . . . . . . . . • . .

7-38

Appendix
A1

TELEPR INTER CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

A 1-1

TELETYPE EIGHT-LEVEL CODE ...........•....•••....•....• ·•··

A2-1

CARD READER, HOLLERITH CODES ..........•••.......•....•...

A3-1

LINE PRINTER CODE ....................••..•..•.....•..•.••.•

A4-1

DIGITALIS SERVICE PRACTiCE ......•.•..••.•••.••.•..•..•.....

A5-1

RIM LOADER. . . . . • . . . • . . . . . . . . . . . . . . • • • • . . • . • . . • • . . . . . • • • . . •.

A6-1

I NSTRUCT ION SUMMARY .........•..••.••..••••••.•••••••...•

A7-1

POWERS OF TWO. . . . . . . • . • . . . . . • . • . • . . . • • . • . • • . . . • • . . • . • . . • ..

A8-1

ILLUSTRATIONS
figure
1-1

Expanded PDP-7 System ....•.......•.....••.••...•..•.•..•.••..

1-6

2-1

Operator Console •..•.•.•..•....•....•..•..•.•.•..•....•......

2-1

3-1

PDP-7 Central Processor and Memory .......•.••.••••..•.•...•....

3-1

3-2

Memory Reference Instruction Format .....•....•.•..••.•.••.•.•...

3-4

3-3

Operate Class Instruction-Bit Assignment ......•.••.•....••••••...

3-8

3-4

EAE Instruction Bit Assignment •..•..•..•••.••.•.••••.•...••.••.•

3-17

4-1

I/O Control Schematic .....•.•.•.•..... • .••••..•.•......••.•.••

4-1

4-2

Bit Ass i gnment for I nput- Output Transfer Instruction {iot} .....•.•....

4-2

ILLUSTRATIONS (continued)
Figure

Page

4-3

Device Selector Decoder ...............•.......................

4-5

4-4

I/O Pulse Cycle Diagram .•....................................

4-7

4-5

Input-Output Status Instruction-Bit Assignment ................... .

4-9

4-6

Data Interrupt Multiplexer Signal Diagram ....................•...

4-19

5-1

PIC Word Format •..........•......•........•..................

5-2

7-1

Cab inet Layout .............................................•.

7-2

Input/Output Flow ..................•.......•.........•.......

7-3

Alphanumeric Perforated Tape Format and Reader Buffer
Bit Assignment .......•.•.•..................................•.

7-5

7-4

Binary Perforated Tape Format and Reader Buffer Bit Assignment ..... .

7-6

7-5

DECtape Recording ..•........•....•..•........................

7-9

7-6

Drum Logic and Interface Connections ................•..........

7-20

7-7

Type 142 Simplified Block Diagram .........•....................

7-28

7-8

Card Reader Conso Ie •...........•...........•.................

7-34

7-9

Card Reader Contro I Pane I ..................•..................

7-34

vii

CHAPTER 1
PDP-7 SYSTEM

DESCRIPTION

PROGRAMMED DATA PROCESSOR-7 (PDP-7) is a general purpose, solid state, digital computer
designed for high speed data handling in the scientific laboratory, the computing center, or the
real time process control system. PDP-7 is a single address, fixed la-bit word length, binary
computer using lis complement arithmetic and 2 1s complement arithmetic to facilitate multiprecision arithmetic. A random access magnetic core memory with a complete cycle time of
1.75 microseconds is used to achieve a computation rate of 285,000 additions per second.
The PDP-7 is completely self-contained, requiring no special power sources, air conditioning,
or floor bracing. From a single source of 115-volt, 60-cycle, single-phase power, the PDP-7
produces circuit operating dc voltages of -15 volts (±1) and +10 volts (±1) which are varied
for mC'Jrginal checking. Total power consumption is 2000 watts. It is constructed with standard
DEC FLIP CHlp™ modules and power supplies. Solid-state components and built-in marginal
checking facilities insure reliable machine operation.
Input/ou'tput to the PDP-7 is fast parallel transfer and may be connected toa variety of peripheral equipment. In addition to the teleprinter, keyboard and high-speed perforated tape reader
and punch supplied with the basic computer, the PDP-7 optional peripheral equipment includes
magnetic tape equipment, card equipment and line printers, serial drums, cathode-ray tube
displays, a data communication system, and analog-to-digital converters. Special purpose
I/O equipment is easily connected using an interface of standard DEC modules.
The basic PDP-7 inc ludes the central processor and control console; 4096 word core memory;
input/output control with device selector (up to 64 I/O connections), information collector
(seven 18-bit channels), information distributor (six 18-bit channels), program interrupt, data
interrupt, I/O i'rap, I/O skip facility, I/O status check, and real' time clock. A high speed
paper tape reader (300 cps), high speed paper tape punch (63.3 cps), and KSR 33 teleprinter
(10 cps) are standard input/output equipment with the basic PDP-7.

PROCESSOR
The processor performs logical and arithmetic functions, provides access to and from memory
and controls the flow of data to and from the computer. It consists of the processor control,
the memory, memory control and six other active registers.
ACCUMULATOR (AC) is an 18-bit register which performs arithmetic and logical operations
on the data and acts as a transfer register through which data passes to and from the I/O
bu Her reg isters .

™ FL IP CH IP is a trademark of the Digital Equipment Corporation
1-1

LINK (L) is a l-bit register used to extend the arithmetic facility of the accumulator.
MEMORY ADDRESS REGISTER (MA) is a l3-bit register which holds the address of
the core memory cell currently being used.
MEMORY BUFFER REGISTER (MB) is on l8-bit register which acts as a buffer for all
information sent to or received from memory.
INSTRUCTION REGISTER (IR) is a 4-bit register which holds the operation code of
the program instruction currently being performed.
PROGRAM COUNTER (PC) is a 13-bit register which holds the address of the next
memory cell from which an instruction is to be taken.

MEMORY
The high speed random access memory is a 4096 word coincident-current core module with
a cycle time of 1 .75 microseconds. In one cycle the memory control retrieves an 18-bit
word stored in the memory cell specified by the memory address register, writes the word
by a parallel transfer into the memory buffer register, and rewrites the word into the same
memory cell.

CENTRAL PROCESSOR OPTIONS
CORE MEMORY MODULE TYPE 147
The Core Memory Module extends the memory capacity of the PDP-7 from 4096 words to
8192 words.
CORE MEMORY EXTENSION CONTROL TYPE 148
The Memory Extension Control allows the expansion of the PDP-7 memory from 8192 to
32,768 words in increments of either 4096 or 8192 words, using the Type 149 Memory
Modules. The Type 148 includes an Extended Program Counter, an Extended Memory
Address Regi ster, and an Extend Mode Control.
EXTENDED ARITHMETIC ELEMENT TYPE 177
The Extended Arithmetic Element is a standard option for the PDP-7 which facilitates
high-speed multiplication, division, shifting, and register manipulation. Installation of
the EAE adds an 18-bit register, the Multipl ier Quotient Register (MQ) to the computer
as well as a 6-bit step counter register. The contents of the MQ register are continuous- .
Iy displayed on the operator's console just below the accumulator indicators.
The Type 177 and the basic computer cycle operate asynchronously, permitting computations to be performed in the minimum possible time. Further, since the EAE instructions are microcoded, several operations can be performed by one instruction, thus
simplifying associated programming. Average multiplication time is 6.1 !-,sec, average
division time is 9 IJsec.

1-2

AUTOMATIC PRIORITY INTERRUPT TYPE 172
The Automatic Priority Interrupt increases the capacity of the PDP-7 to handle transfers
of information to and from input/output devices. The 172 identifies an interrupting
device directly, without the need for flag searching. Ml)ltilevel interrupts are permissible where a device of higher priority supersedes an interrupt already in process. These
functions increase the speed of the input/output system and simpl ify the programming.
More and faster devices can therefore be serviced efficiently.
The Type 172 contains 16 automatic interrupt channels arranged in a priority chain so
that channel 0 has the highest priority and channel 178 has the lowest priority. The
priority chain guarantees that if two or more in-out devices request an interrupt concurrently, the system grants the interrupt to the devicewith the highest priority. The
other interrupts wi II be serviced afterwards in priority order.
INPUT/OUTPUT CONTROL
The I/O control Iinks up to 64 input and output stations by Iines to the central processor,
calls the stations, and collects and distributes the input/output data. It also controls the
interleaving of data during a data interrupt, senses the status of I/O devices and skips
instructions based on this status, traps lOT (input-output-transfer) instructions initiating
a program break, and generates real time signal pulses for use by external peripheral
equi prnent.
No additional interface equipment is required to attach the standard PDP-7 Peripheral
Equipment. Word buffers are included within units of standard I/O optional equipment so
that the basic PDP-7 can simultaneously control data transfer between several I/O devices.
Spec ial-purpose I/O equipment is easi Iy connected to the PDP-7 by assembl ing an interface using the standard line of FLIP CHIP modules manufactured by DEC.
INPUT/OUTPUT EQUIPMENT

Mass Storage
DECtape DUAL TRANSPORT TYPE 555
A fixed address magnetic tape facility for high speed loading, readout, and on-line
program debugging. Read, write, and search speed is 80 inches a second. Density is
375 bits an inch. The two logica"y independent transports have a storage capacity of
3 million bits each. Features phase recording, rather than amplitude recording; redundant, nonadjacent data tracks; and a prerecorded timing and mark track.
DECtape CONTROL TYPE 550
Controls up to four Type 555 Dual DECtape T:ransports. Searches iil either direction for
specified block numbers, then reads or writes data. Units as sma" as a single word may
be addressed.

1-3

AUTOMATIC MAGNETIC TAPE CONTROL TYPE 57A
Controls up to eight tape transports automatically. Provides information transfer through
computer's data interrupt foc il ity, permitting interlaced program and tape operation.
Controls reading or writing of tape at various rates compatible with IBM, BCD, or binary
parity modes.
MAGNETIC TAPE TRANSPORT TYPE 570
Tape motion is controlled by pneumatic capstans and brakes, eliminating conventional
pinch rollers, clamps, and mechanical arms. Tape speed is either 75 or 112.5 inches
per second. Track density, program-selectable, is 200, 556, and 800 bits per inch.
Tape width is one-hal f inch, with six data tracks and one parity track. Format is IBM
compatible. Dual heads permit read-checking while writing.
MAGNETIC TAPE TRANSPORT TYPE 50
Reads and writes IBM-compatible magnetic tape at transfer rates of 15,000 or 41,700 cps
and 200 or 556 cpi .
BLCX K TRANSFER DRUM SYSTEM TYPE 24
Drum transfers operate through the computer's data interrupt facility permitting interlaced program and drum transfer operation. Storage capac ities of 32,768 words,
65,536 words, or 131,072 words are avai'lable.

Displays
v~ECIS'ON CRT DISPLAY TYPE 30

Plots data point by point on a 16-inch cathode ray tube in a raster 9-3/8 inches square
I,aving 1024 points on a side. Separately variable 10-bit X and Y coordinates. Includes
orogrom intensity control. Plotting rate is 35 microseconds per point.
PRECISION INCREMENTAL CRT DISPLAY TYPE 340
Plots points, I'ines, vectors, and characters on a raster identical to the 30. Plotting
rate is 1-1/2 microseconds per point in vector, increment, and character modes. Random
point plotting is 35 microseconds.
(JSClLLOSCOPE DISPLAY TYPE 34
Controls the plotting of data point by point on an X-Y plotting scope such as the
Tektronix Model RM 503. Raster size is 1024 x 1024 points.
YIGH SPEED LIGHT PEN TYPE 370

Uses fiber optic Iight pipe and photomultipl ier system for fast detection and modification
of information displayed on the precision CRT display.

1-4

Analog- To-Digital
ANALOG-TO-DIGITAL CONVERTER TYPE 138B
Transforms an analog voltage to a binary number, selectable from 6 to 11 bits. Conversion
time varies, depending on the number of bits and the accuracy required. Twenty-four
combinations 6f switching point accuracy and number of bits can be selected on the front
panel.
MULTIPLEXED ANALOG- TO-DIGITAL CONVERTER TYPE 138/139
The Type 139 Multiplexer Control permits up to 64 channels of analog information to be
applied singly to the input of the Type 138B Analog-to-Digital Converter. Channels can
be selected in sequence or by individual addresses.
HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER TYPE 142
Transforms an analog voltage to a single, 1 O-bit binary number in 6 microseconds. Conversion accuracy is ±0.15% ±1/2 least significant bit.
ANALOG-DIGITAL-ANALOG CONVERTER SYSTEM TYPE ADA-l
Performs fast, real-time conversion between digita I and analog computers. Maximum
sample rate for D/ A conversion is 200 kc; for A/D and interlaced conversions, 100 kc.
Digital word length is 10 bits. Actual conversion times are 5 microseconds for A/D and
2 microseconds for D/ A. Semiautomatic features enable the converter system to perform
many of the functions that a computer norma" y performs for other converter interfaces.
18-BIT OUTPUT RELAY BUFFER TYPE 140
18 spdt relays actuated by computer command for use to directly control or signal external
equipment.
INCREMENTAL PLOTTER AND CONTROL TYPE 350
Performs high resolution plotting on paper 12 or 31 inches wide at rates of 12,000 or
18,000 points per minute. Plotting increments are 0.005 and 0.01 inch.

Card Equipment and Printer
CARD READER AND CONTROL TYPE 421A, B
Reads standard 12-row, 80-column punched cards at a rate of 200 or 800 cards per minute
in either alphanumeric or binary modes.
CARD PUNCH CONTROL TYPE 40
Controls a card punch such as the IBM Model 523 Summary Punch.
holds one 80-bit row.

Punch Control Buffer

AUTOMATIC LINE PRINTER AND CONTROL TYPE 64
The automatic line printer prints lines of text 120 columns wide at a maximum rate of
300 I ines per minute. Printing is performed by solenoid-actuated hammers. A 64-character
set is provided.

1-5

Input/ Output Systems
DATA COMMUNICATION SYSTEM TYPE 630
Provides a real-time interface for up to 64 remote typewriter stations for on-I ine inputs
and outputs. Used in message switching, data collecting, and data processing in multiuser appl ications.
DATA INTERRUPT MULTIPLEXER TYPE 173
Provides multiplex control for simultaneous operation of three high-speed devices such
as the Type .57A Tape Control or the Type 24 Drum. Maximum combined transfer rate
is 570,000 l8-bit words per second.

ANALOG

340 CRT

+ t
DIGITAL

DISPLAY

--l

r
- __
I - - - -..-----1.

I
I

I
I
I
I

I
I

DATA INTERRUPT

POP-7
PROCESSOR

REAL
TIME
CLOCK

I
I
I

L ____ _

Figure 1-1

Expanded PDP-7 System

PROGRAMMING SYSTEM
The PDP-7 Programming System includes an advanced FORTRAN Compiler, a Symbolic Assembler, Editor, DDT Debugging System, Maintenance routines and a library of arithmetic, utility
and programming aids developed on the program-compatible PDP-4. Both the Editor and DDT
are designed to allow symbol ic debugging and computer-aided editing to replace the tedious
manual equivalent. New and updated programs are being developed continuously in the applied
programming department.

1-6

SYMBOLIC ASSEMBLER
The Symbolic Assembler lets the programmer code instructions in a symbolic language.
The assembler used on the PDP-7 allows mnemonic symbols to be used for instruction
codes and addresses. Constant and variable storage registers can be automatically
assigned. The assembler produces a binary object tape and lists a symbol table with
memory allocations and useful diagnostic messages.
DIGITAL DEBUGGING TAPE (DDT)
DDT speeds program debugging by communicating with the user in the address symbols of
the source language program. Program debugging time is further shortened when using
DDT because program execution and modification are controlled from the teleprinter
keyboard. For example, to branch to a new location in the program it is only necessary
to type the symbolic location name on the keyboard followed by the character, single
quote ('). The same symbol followed by the character, slash (;), causes the contents of
that location to be typed. By using DDT to insert break points in a program, the programmer can make corrections or insert patches and try them out immediately. Working corrections can be punched out on the spot in the form of loadable patch tapes, el im inating
the necessity of creating new symbolic tapes and reassembling each time an error is
found.
SYMBOLIC EDITOR
The Editor permits the editing of source language programs by adding or deleting lines
of text. All modification, reading, punching, etc., is controlled by symbols typed at
the keyboard. The editor reads parts or all of a symbolic tape into memory where it is
available for immediate examination, correction, and relisting.
FORTRAN COMPILER
The FORTRAN used with the PDP-7 is based on the field-proven FORTRAN 1/ used with
PDP-4 and is designed for programming flexibility and operating efficiency. An 8K
memory is now required for FORTRAN with the PDP-7 to provide a program and data
storage capacity commensurate with the power of the PDP-7 Processor. FORTRAN permits the PDP-7 user with Iittle knowledge of the computer's o'rganization and machine
language to write effective programs. Programs are written in a language of familiar
English words and mathematical symbols. Compilation of the original FORTRAN source
program is performed separately from the compi lation of associated subroutines. Thus,
when errors in FORTRAN coding are detected by the compiler diagnostic, only the
erroneous program need be recompi led.
BUS-PAK II
Designed for data processing operations, BUS-PAK is a program assembly system for use
by the data processing programmer. Programs written using BUS-PAK enable the PDP-7
to function as a business-oriented computer equipped with a logical instruction set very
simi lar to the instructions used by data processing computers. BUS-PAK operates in a
character mode, has a built-in high-speed I/O control, is capable of single and double
indexing, multilevel indirect addressing, a,nd makes available 15 accumulators.

1-7

CHAPTER 2
OPERATION

This chapter describes console operation of the PDP-7 through use of the console I ights, switches,
and keys. A second section describes how to load basic system tapes into the computer.

OPERATOR CONSOLE
The operator console contains all of the manual controls necessary to start and stop the PDP-7,
to observe the status of all active control processor registers, and to manually address, examine,
and change the 18-bit contents of any location {word} in core memory. The functions of the
console I ights, switches, and keys are described in the following tables.

MEMORY I'llJl'FER

U.NK f'IERUN

r!!TCH

DEFLR EnCU'I[U(,AK

IICII I CC
CII)

-•••
TRAP

START

STOP

CON'I'INlJE

UAMINE

DU~OSlr

EXAMItH
NEXT

DEPOSIT
NEXT

Figure 2-1

€Xl£NO

PUNCHJEEO

__ 1m rill DEl!

S1NGlE STEP

SINGlE,INS1

REPf,·Al

POWI'.~

!lEAO "" IN

Operator Console

2-1

~.';.~"
LJ.;;'
.

SWITCHES AND KEYS

Function
START

Starts the processor. The first instruction is taken from the
memory cell specified by the setting of the ADDRESS
switches. The START operation clears the AC and link,
and turns off the program interrupt.

STOP

Stops the processor at the completion of the memory cycle
in progress at the time of key operation.

CONTINUE

Causes the computer to resume operation from the point
at which it was stopped. Besides the normal "off" and
momentary "on" positions, this key has a latched "on"
position obtained by raising the key instead of depressing
it.

EXAMINE

Places the contents of the memory cell specified by the
ADDRESS switches into the AC and MB. At the completion
of the operation, the contents of the ADDRESS switches
appear in the MA, and the PC contains the address of the
next cell •

EXAMINE NEXT

Places the contents of the cell specified by the PC into
the AC and MB. The C(PC) are incremented by 1, and
the MA contains the address of the register examined.

DEPOSIT

Deposits the C(AC switches) into the memory cell specified
by the ADDRESS switches. The C(AC switches) remain in
the AC and MB. The contents of the ADDRESS switches
appear in the MA. The PC contains the address of the
next cell.

DEPOSIT NEXT

Deposits the C(AC switches) into the memory cell specified
by the PC. The C(PC) are then incremented by 1. At the
completion of the operation, the C(AC), C(MA) are the
same as for DEPOS IT

2-2

READ-IN'

Punched paper tape is read in .binary mode"into a core
memory bloctc. The first address of the memory block is
gIven by the C(ADDRESS switches}. Control then transfers
to the central processor wh i&;h interprets and executes the
last word in the block •.

Switches and
Function

Speed Controls
ADDRESS

A group of 15 switches used to establ ish the memory address
for the START, EXAM I NE, and DEPOSIT operations.

ACCUMULATOR

A group of 18 switches used to set up the word to be placed
in memory by the DEPOSI T and DEPOSIT NEXT operations,
or the word to be placed in the AC by a program. These
18 switches are used for program sense control.

EXTEND

Enables the Extend Mode of the optional Type 148 Memory
Extension Control to be used with all console keys and
switches perform ing memory reference functions.

TRAP

Perm its the Trap Mode to be engaged by the program.

PUNCH FEED .

Switch - controls perforated tap.e pu nc h power. When
down, punch power is under program control. When ~,
punch power is on.
Button - causes punch to punch tape leader. Punch power
remains on for additional 5 seconds as it does under program control.

SINGLE STEP

Causes the computer to stop at the completion of each
memory cycte. Repeated operation of CONTINUE while
this switch is on steps the program one memory cycle at a
time.

2-3

SINGLE INSTRUCTION

Couses the computer to stop ot the completion of each
instruction. Repeated operation of CONTIN UE while
this switch is on steps the program one instruction ot a time.
When both switches are on, SINGLE STEP takes precedence
over SINGLE INSTRUCTION.

REPEAT

Causes the operations initiated by pressing CONTINUE,
EXAMINE NEXT, or DEPOSIT NEXT to be repeated as
long as the key is held on. The rate of repetition is controlled by the SPEED knob setting.

SPEED

Two controls that vary the REPEAT interval from approximately 40 microseconds to 8 seconds. The left knob is a
5-position coarse control, the right knob a continuously
variable fine control. For both knobs, slowest speed is
obtained in extreme left position.

POWER

Controls the primary power to the computer and all external
dev ices attached to it.

CONSOLE LOCK
On the lower right-hand side of the console is a key-operated, 2-position lock. When
the key is turned counterclockwise, the console is unlocked and all controls operate
normally. When the key is turned clockwise, the console is locked; operation of any of
the console keys, the speed controls, or the POWER, SINGLE STEP, SINGLE INSTRUCTION
or REPEAT switches has no effect on the running of the computer.

2-4

CONSOLE LIGHTS

Indication

ACCUMULATOR

The contents of the AC

MU LTIP LIE R-Q UOT IEN T

The contents of the MQ

MEMORY BUFFER

The contents of the MB

INSTRUCTION

The contents of the IR

MEMORY ADDRESS

The contents of the MA

PROGRAM COUNTER

The contents of the PC

LINK

The contents of the Iink

PIE

Indicates when the Program Interrupt is Enabled

TRAP

Indicates when the Trap Mode is Enabled

EXTEND

Indicates when the Extend Mode is Enabled

RUN

The computer is executing instructions

FETCH, DEFER,
EXECUTE, BREAK

The major control state of the next memory cycle

SINGLE STEP, REPEAT,
SINGLE INST, POWER

Indicates the function is active

C (registers) are a binary display.

2-5

CHAPTER 3
CENTRAL PROCESSOR
ARITHMETIC AND CONTROL REGISTERS
Six active registers in the central processor are used to perform arithmetic operations,
control memory access and to transfer information to and from the computer. Figure 3 .. 1
shows the relation between the central processor registers and other elements of the
computer.

ACCUMULATOR
SWITCHES

r------------- ------

-- - -- ------------l

MEMORY
AND
MEMORY CONTROL

PROCESSOR CONTROL

L__________________

_______
ADDRESS
SWITCHES

Figure 3-1

KEYS

PDP-7 Central Processor and Memory

ACCUMU LA TOR (AC): Arithmetic operations are performed in this l8-bit register.
The AC may be cleared and complemented. Its contents may be rotated right or left
with the link. The contents of the Memory Buffer may be added to the contents of the
AC with the result left in the AC. The contents of both registers may be combined by
the logical operations AND and Exclusive OR, the result remaining in the AC. The
Inclusive OR may be formed between the AC and the accumu lator switches on the operator
console (see below), and the result left in the AC. Except in data interrupt transfers,
information is transferred between core memory and an external device through the
accumu lator.

3-1

If a l-cycle instruction is fetched, the operations specified are performed during the last
part of the fetch cycle. The next stote is fetch. If a two-cycle instruction is fetched, the
following control state is either defer or execute.
DEFER: When bit 4 of a memory reference instruction is a 1, the defer state is entered to
perform the indirect addressing. The memory locr.1ti()n addressed contains the address of the
operand, and access to the operand is deferred to the next memory eye Ie.
EXECUTE: This state is estobl ished only when a memory reference instruction is being
executed. The contents of the memory ce II addressed are brought into the MB, and the
operation specified by the contents of the IR is performed.
BREAK: When this state is established, the sequence of instructions is broken for a data
interrupt or a program interrupt. In both cases, the break occurs only at the completion of
the current instruction. The data interrupt allows information to be transferred between
memory and an externa I devi ce. When this transfer has been compl eted, the program
sequence is resumed from the poi nt of the break. T he program interrupt causes the
sequences to be altered. The contents of the PC and the contents of the Link are stored in
location 0000, and the program continues from location 0001. See Chapter 4, Program
Interrupt Control.

INSTRUCTIONS

Instructions are of two types: memory reference and augmented. Memory reference instructions require a memory address, whi Ie augmented instructions do not. For clarity, a set of
basic logic symbols is used throughout the instruction set.

Instruction Symbol Definitions
SYMBOL

DEFINITION

Designates any registerin core memory

Designates the jth bit of register Y

Yj-k

DesifJnates bits j through k of register Y

C(Y)

The contents of register Y

C(Y) = > C(Z)

The contents of Y replace the contents of Z
Designates an instruction, without reference to a register or
core Iocat ion

1-1

Instruction Symbol Definitions (continued)

SYMBOL

DEFINITION
41

The jth bit of an instruction. For example, 14 = 1 means
that bit 4 of an instruction code hos a value of 1.

I'I

In a memory reference instruction, this signifies indirect
addressing. It means that in the code for such on instruction 14 = 1 .
And

I nc I us i ve 0 r
Exclusive Or

em- signifies the complement

- - (overbar)

Complement. For example,
of the contents of register Y.

Memory Reference Instructions
The bit assignments of the memory reference instruction are shown in Figure 3-2. Bits 0-3
determine the operation to be performed. Bits 5-17 specify the memory address. Bit 4 is
used to specify indirect addressing.

[OJ 1 I 2 I 3 I 4D I 6I 7I 8 I 9 110 Iii!(2 [1m 4

4fJf'Operation Indirect
Code
Address
(Defer)

Figure 3-2

rn 1161171
I

Operand Address

Memory Reference Instruction Format

Memory reference instructions require a fetch cycle to interpret the operation and determine
,·he memory address, and an execute cycle to carry out the operation. Information is transfel red from the AC to core memory through the Memory Buffer. When an operand is to be
combined with the contents of the AC, it is brought from core storage into the MB; the
operation is then performed between the AC and the MB. When indirect addressing is
specified, an extra (defer) cycle is required to determine the effective address.

3-4

The imp instruction requires an address but not an operand and thus is not a true memory
reference instruction; although, it is convenient to I ist it with them. An execute cy~le is
not needed, and the instruction is completed in one cycle.

MEMORY REFERENCE INSTRUCTIONS
MNEMONIC
SYMBOL

OCTAL
CODE
(B its 0-3)

MACHINE
OPERATION

CYCLES

lac Y

Load AC. The C(Y) are loaded into the AC.
The previous C(AC) are lost; the C(Y) are
unchanged.
C(Y) = > C(AC)

doc Y

Deposit AC. The C(AC) are deposited in the
memory cell at location Y. The previous C(Y)
are lost; the C(AC) are unchanged.
C(AC) = > C(Y)

dzm Y

Deposit zero in memory. Zero is deposited in
memory cell Y. The original C(Y) are lost.
The AC is unaffected by this operation.
0= > C(Y)

add Y

Add (l's complement). The C(Y) are added to
the C(AC) in l's complement arithmetic. The
result is left in the 'AC and the original C(AC)
are lost. The C(Y) are unchanged. The link
is set to 1 on overflow.
C(Y) + C(AC) = > C(AC)

tad Y

Twos complement add. The C(Y) are added to
the C(AC) 'in 2's complement arithmetic. The
result is left in the AC and the original C(AC)
are lost. The C(Y) are unchanged. A carry
out of the 0 bit complements the link.
C(Y) + C(AC) = > C(AC)

xor Y

Exclusive OR. The logical operation Exclusive
OR is performed between the C(Y) and the
C{AC). The result is left in the AC and the

3-5

MEMORY REFERENCE INSTRUCTIONS (continued)
MNEMONIC
SYMBOL

OCTAL
CODE
(Bits 0-3)

MACHINE
CYCLES

xor Y (continued)

OPERATION

original C{AC) are lost. The C(Y) are unchanged. Corresponding bits are compared
independently.
C{YJ ¥ C{AC.) = > C{AC.).
I

Example
C(AC)j original C(Y)j
i

and Y

o
o

jms Y

1
1

AND. The logical operation AND is performed
between the C(Y) and the C(AC). The result
is left in the AC I and the original C(AC) are
lost. The C(Y) are unchanged. Corresponding
bits are compared independently.
C(Yj) " C(ACj) =>C(AC j)
Example
C(AC)j original C(Y)j C(AC)j final

1
1
60

o
o

imp Y

C(AC)j final

o
o
o

o
1

Jump to Y. The next instruction to be
executed is taken from memory cell Y.
Y = > C(PC)
2

Jump to subroutine. The'C(PC) and the C(L)
are deposited in memory cell Y. The next
instruction is taken from cell Y + 1 .
C(L) = C(Yo).
0 = > C(Yl-4)
C(PC) = > C(Y5-17).
Y + 1 = > C(PC)

3-6

MEMORY REFERENCE INSTRUCTIONS (continued)

MNEMONIC
SYMBOL

OCTAL
CODE
(Bits 0-3)

MACHINE
CYCLES

OPERATION

cal

Call subroutine. The address portion of this
instructiun is ignored. The action is identical
to jms 20. The instruction cal i is equivalent
to jms i 20.

xct Y

1 + time
of instruction being
executed

Execute. The instruction in memory cell Y is
executed. The computer acts as if the instruction located in Y were in the place of
the xct, so that the PC sequence is unaltered.

sad Y

Skip if AC is different from Y. The C(Y) are
compared with the C(AC). If the numbers are
the same, the computer proceeds to the next
instruction. If the numbers are different, the
next instruction is skipped. The C (AC) and
the C(Y) are unchanged.
If C(AC) I. C(Y) then C(PC) + 1 = > C(PC)

isz Y

Index and skip if zero. The C(Y) are incremented by one in 2 1s complement arithmetic.
If the result is zero, the next instruction is
skipped; if not, the computer proceeds to the
next instruction. The C(AC) are unaffected.
C(Y) + 1 =>C(Y)
If result = 0, C(PC) + 1 = > C(PC)

Execution Time (jJsec)
Instruction or program execution times can be computed in microseconds by multiplying the
number of machine cycles by 1.75, the microsecond cycle time of the PDP-7.

3-7

AUGMENTED INSTRUCTIONS

Augmented instructions do not require a memory reference. As a result, an execute cycle
is not needed, and the instructions in this class are completed in one cycle. Bits 4-17 of
an augmented instruction are used to spec ify the operations to be performed. Several
operations may be combined by microcoding in a single instruction, as explained below.
Operate Class
The group of augmented instructions with octal code 740000 is used to control bit
manipulation and sensing in the operating registers of the PDP-7. Instructions of the 74
octal code belong to the Operate Class. These instructions are designed so that several
of them may be combined in a single operate instruction. This is possible with operate
instructions whose functions are performed at different event times during the 1 .75 fJsec
instruction cycle. Figure 3-3 shows the Operate Class Instruction Bit Assignment.
A Table of Operate Instructions indicating event times follows. These event times are
numbered 1, 2, and 3 and occur in that order. An operation which takes place at event
time 2 is completed before event time 3 begins. Certain operations which take place at
the same event time may not be combined in the same instruction.

Opr-740000
Invert
Sense
Of Skip

l"leir 'IT
lf bit 8 = 1

If bit 7 = 1

Additional
Rotate

Figure 3-3

Operate Class Instruction - Bit Assignment

3-8

OPERATE INSTRUCTIONS
MNEMONIC
SYMBOL

OCTAL
CODE

opr

740000

cia

750000

Clear AC. The AC is cleared to O.
0= > C(AC)

cma

740001

Complement AC.
com pi emented .
C (AC) = > (AC)

cll

744000

Clear link.

EVENT
TIME

Operate. Indicates the operate class. When
used alone, performs no operation; the computer
proceeds to the next instruction after one
memory cyc Ie.

o = > C(L)

cml

740002

OPERATION

Each bit of the AC is

Link is set to o.

Complement link.

qI) = > C(L)
ral

740010

Rotate AC left. The C(AC) and the C(L) are
rotated Ieft one pi ace.
C(ACj) = > C(ACj-l)
C(ACO) = > C(L).
C(L) = > C(AC17)

rtl

742010

2, 3

Rotate two places left.
successive ralls.

rar

740020

Rotate AC right. The C(AC) and the C(L) are
rotated one place right.
C(ACj) = > C(ACj-l)
C(L) = > C(ACO)
C(AC 17) = > C(L)

3-9

Equivalent to two

OPERATE INSTRUCTIONS (continued)
MNEMONIC
SYMBOL

OCTAL
CODE

EVENT
TIME

rtr

742020

2, 3

Rotate two places right. Action taken is
equivalent to two successive rarls.

oas

740004

OR AC switches. The Inclusive OR of the
C(AC) and the C(AC switches) is placed in
the AC. If an AC switch is down, it is interpreted as a 0; if up, as a I.
C(AC switches) V C(AC) = > C(AC)

sma

740100

Skip if minus AC. If the AC is negative, the
next instruction is skipped.
If ACO = 1, then C(PC) + 1 = > C(PC)

spa

741100

Skip if plus AC. If the AC is positive, the
next instruction is skipped.
If ACO = 0, then C(PC) + 1 => C(PC)

sza

740200

Skip if zero AC. If C(AC) are 0, the next
instruct ion is sk i pped .
If C(AC) = 0, then C(PC) + 1 = > C(PC)

sna

741200

Skip if non-zero At.
If C(AC) -10, then C(PC) + 1 = > C(PC)

snl

740400

Skip if non-zero link. If C(L) is 1, the next
instruction is skipped.
If C(L) -10, then C(PC) + 1 = > C(PC)

szl

741400

Skip if zero link.
If C (L) = 0, the n C (PC) + 1 = > C (PC)

740040

immediately after the
completion
of the cyc Ie.

OPERATION

Halt. Stops the computer.

3-10

When skip o'perotlons ore combined tn a lingle instruction, the Inclusive OR of the
conditions to be met determines whether or not the skip takes place. For example, if both
S%O Qnd snl are speci¥led (operatton code 740600), the next instruction is skipped if either
the C(AC);= 0, the C(L) 1, or both. When th, sense of the skip is inverted (IS =1) in a
combined $kip, the skip takes place only if both of the conditions are met. For example,
bothsna and szl are specified (operation code 741600), the next instruction i$ not skipped
if either the C(AC) = 0, the C(L) :;: 1, or both. Thesk ip occurs only if both C(AC) .,. 0
andC(L) ;::: O.

The nature of the rotQte operation$ is such that no other operations may take place during
the same event time. The following restrIctions must therefore be observed:
rar ond ral may not be combined with 005, cml, or ema.
rtr c;md rtl may not be combined with ~Ia, ell, oas, cmo, or cml.

INPUT/OUTPUT TRANSFER (lOT) INSTRUCTION
Input/Output Transfer (jot) Instructions are used to controfexternol devices, sense their
status Clnd transfer information betw,en them and the central processor. The bit assignmentsof the iot claS$ (:Ire shown in Figure 4-2. Bits 0-3 carry the jot Instruction code
(70). Bits 6 ... 11 determine the external device selected; bits 4 ... 5 and 12-13~re used
to select Q mode of operation orsubdevice, and bits 15 ... 17initiate electdcal pulses
to the devicefQr direct control of the information transfer or devIce operation.
Descriptions of iot instructions are given a long with the flO equ ipment description, in
Chapter 7. The I/O Interface Electrieal Characteristics follow the device description.

The law Instruction
The law instruction ( code 760000) is a special case of the operate class instructions.
Bits 5-17 are not interpreted; instead, the instruction i·tself is placed in the AC. In th is
wayan address-si;ze number can be loaded into the AC without 'using an extra rnemory
location. The low instruction is used to:
load memory addresses for use in indirect addressing,
load character$ into the AC for USe with I/O equipment,
initialize word count for CI magnetic tape transfer,
preset the clock counter.

3-11

Only bits 5-17 of the law instruction are regarded by the above addresses, characters,
and counts.
Example:
low

1234

/the octal number 761234 is entered into
the AC

doc

/C(AC) ~ >C(location 15)

To initialize a memory location with a negative number, where the complete word
(bits 0-17) is to be regarded, it is necessary to take the l's complement of the number
and then subtract away the octal code 760000. For example, if the desired count is 755,
memory location Y is loaded with -755 as follows. The l's complement of 000755 is
777022, which can be represented as the sum of 760000 and 1022. Since 760000 is the
operation code for low, the resulting program sequence is used:
law

1022

dac

INDIRECT ADDRESSING

In a memory reference instruction, if bit 4 is a 1, indirect addressing occurs when the instru~tion is executed. Bits 5-17 of such on instruction are interpreted as the address of the
mel'llory location containing not the operand but the adqress of the operand. Thus, access to
the operand is deferred once to another location. The indirect instruction appears as'
Example:

add i 100

where,

C(100) = 001357

where i signifies indirect addressing. The processor interprets the contents of register 100
as the -;ddress of the instruction operand and in the next memory cycle adds C(1357) to the
AC. Access to an operand can be deferred in this manner only once during the execution
of an instruc;:tion.

AUTO-INDEXING
[och 8192 word memory field of a PDP-:-7 computer system contains 8 auto-indexlng memory
1/ q.( .Hons in memory locations shown in the table below. When one of these locations is
II' /,,1 as an indirect address, the location contents are automatically incremented by one,
(llId the result is taken as the effective address of the instruction. The indexing is done
with no added instruction time. Note that indexing of an auto-index location occurs only
on an indirect reference; for direct addressing, the auto-index locations are identical to
other memory locations.
3-12

Machine Size

Memory Fields

Relative Address

4K
8K
16K
24K

0
0
0,
0, 1, 2

10-17
10-17
10-17
10-17

32K

0, 1, 2, 3

10-17

Physical locations of
Auto-indexing locations

108- 178
108-178
108-178, 10010-100178
108-178, 10010-100178,
20010-200178
108-17 8 , 100108-100178,
20010-200178, 30010-300178

Example
Assume four memory locations initially have the following contents:
Location

Contents

10
40
100
101

100
50
40
41

The following four instructions to load the accumulator illustrate by comparison the use
of auto-indexing.
Places the number 40 into the AC

100
100
10
10

lac
lac
lac
lac

Places the number 50 into the AC
Places the number 100 into the AC
By auto-indexing, C (10) becomes 101 i
then the number 41 is placed into the AC

Auto-indexing is also used to operate on each member of a block of numbers without the
need for address arithmetic. The following three examples demonstrate how this is done:

N
Add a column of numbers

Y = ~ Xi
i = 1

Location

Contents

10/

FIRST -1
-N +- 1

COUNT

/Iocation of first word
/two1s complement of number of additions

cia
LOOP,

/clear AC

add

/add into partial sum

isz

COUNT

/test for completion

imp
CONTINUE

LOOP

/more in table
/sum in AC

3-13

go back

C i = Ai + Bi for i = 1, 2, ... N

Example 2

Note that three auto-indexing locations are used to simpl ify the addressing.
machine, eight locations are available for use as auto-indexing registers.

LOOP,

Location

Contents

10/
11/
12/

L(A) -1
L(B) -1
L(C) -1

/the location of the A array -1
/the location of the B array -1
/the location of the C array -1

lac
add

/get addend

/form sum

dac
isz

12
COUNT
LOOP

/store sum
/test for completion
/more in table, go back

imp
CONTINUE

/done, continue

C· = C· + K
I
I

Example 3

In the basic

i=l,2, ... N

Modify a I ist of numbers by adding a constant to each of them. Note that the auto-indexing
memory register contains an instruction rather than just an address. This is perfectly
acceptable since, when not in extend mode, only the address bits are used in generating
the effective address.

LOOP,

Location

Contents

10/
COUNT/
CONST/

dac

FIRST -1
-N +1

/deposit into first location in table -1
/two·s complement of number of words in table

/the constant

lac

/pick up initial value from table

add

CONST

/add the constant

xct

/replace in table

isz

COUNT

/test for completion

jmp

LOOP

/more on table, go back

CONTINUE

3-14

EXTEN OED ARITHMETIC ELEMENT TYPE 177

The Extended Arithmetic Element EAE Type 177 is a standard option for the PDP-7 to
facilitate high-speed multiplication, division, shifting and register manipulation. The
EAE contains an la-bit Mu Itipl ier Quotient Register (MQ), a 6-bit Step Counter Register,
two Sign Registers and the EAE logic. The two panels of EAE logic are normally installed
just below the Center Processor in bay one of the PDP-7 Computer. The contents of the
MQ register are continually displayed on the operator's console just below the accumulator
i nd i cators •
The Extended Arithmetic Element hardware operates asyncronously to the basic computer
cyc Ie, perm ittin.g computations to be performed in the min imum possible time. Further,
since the EAE instructions are microprogrammed, it is usually possible to simplify programm ing and shorten computation time by microcod ing exactly the arithmetic operation
desired.
The EAE instructions are broken up into two parts: The first part permits register manipulation as microprogrammed in the instruction wh i Ie data is be ing fetched; the second part
is the specified operation itself. Signed and unsigned multiplication would, for example,
differ in the microprogrammed first part where the $ ign monipu lotion is done. A table
showing the bit configuration for the EAE instructions is given in Figure 3-4.
The set-up phase of the instruction is broken up into four event times. M icroprogramm ing
for a II but the set-up commands uses on Iy the first three event times.. The bits corresponding to the 4th event time then specify the step count of commands such as multiply,
divide, and the shifts. The unassigned operation code should not be used as it is reserved
for future EAE expansion.
Instruction times for opera'tions performed by the EAE depend on the operation, the step
count i and the data itself. Each command has a basic operation time to wh ich is added
function times depending on the operation.
Time

Operation
Sh ift/Norma I ize

1.6 Jls plus O. lJls/step.

Multiply

2.4 JlS plus 0.1 J.1s/step plus 0.25 J.1S per
one-bit in the mu I tipl ier.

Divide

2.4 J.1S plus 0.35 J.1s/step plus 0.2 J.1S per
one-bit in the quotient.

5 ince the EAE expects to fine the mul tip Iier or the divisor in the location following the
multiply or divide instruction, a short subroutine is usually used to set-up the multiply or
divide in the general case. These subroutines in both open and closed form are shown
on the following pages. For multiplication or division by a constant, a subroutine is

3-15

not required and the maximum speed becomes the true multiplication or division time.
Single length numbers (lS-bits) are assumed to be of the form: . high-order bit is the sign
followed by 17 bits in l's complement notation. Doub:le, length numbers (36-bits) use two
registers, and are of the form: two high-order bits as signs', followed by 34 bits in l's
complement notation. Both sign bits must be the same •. Unsigned numbers may be either
18 or 36 bits in length.,

EAE Microprogramming
Arithmetic operations in the EAE assume that the numbers are unsigned 18 or 36-bit words.
To properly manipulate sign numbers, the EAE instructions are microprogrammed to take
comp lements and arrange the signs. In mu Itipl ication, the 18-bH number in the MQ
register is mu Itipl ied by the number in the memory location following the instruction.
The mu Itipl ier in the MQ register at the beginning of the operation can be either pos itive
or negative. If it is negative, its sign must also appear in the EAE ACsign register. If
this register is a one, the MQ register is complemented prior to the multiplication. Microprogramming makes it possible to set up the EAE AC sign register and to move the AC to
the MQ while the data is being fetched.
When the mu Itipl icand is taken from the memory location following the instruction I it must
be a positive number with the original sign in the Link. The exclusive OR of the Link
and the EAE sign register (the two registers containing the original signs of the numbers)
form the sign of the product. If the sign of the product is a one (negative) the AC' and
MQ are complemented at the end of the operation. For the signed multiplication, the
two most significant bits of the AC contain the sign of the product.
'
To produce a full 36-bit product or quotient, the step count of the multiply instruction
should be 18 and for the divide instruction 19. However, for calculation not requiring
36-bitaccuracy before rounding, the step count may be set lower to reduce the time
requ ired for the arithmetic operation. .
For unsigned operations the Link must be zero.
A list of microprogrammed EAE Register Manipulation instructions is given on the following
pages. Microprograms other than those common enough to warrant mnemonics are possible.
An example is an instruction to place the contents of the AC into the MQ. The operation
code for this instruction would be formed by using the EAE Setup op-code, code bit 5, to
clear the MQ at event time 1 and bit 7 to OR the AC into the MQ at event time 2. An
instruction of this type, however, is usually not necessary since the contents of the AC are
automatically transferred to the MQ prior to multiplication by the microprogrammed mul or
muls instruction.

3-16

,
I
,

EAE

110

,
,
I

,
,,
,

(64)

it bit:l I ,

I
I

I
,
I

~
I '
~------+----.,....---.,......-----; _ _ _ _
"- I
6.
EAE Command
,
'-lOU
000 setup

<:r

0
0

I
I

_ -

I.LJ

0 I I divide

I 00 no r m
IOllongrt
I 10 long I 'ft,

I
I
I
I

~
~II

if
bit&=IO ~

,
I
I

II - - - -..J ..
I

001 multiply
0 I0

I
,
,

lei

,
I
,

Code

I
I

Operation

,
,

1 /14

I
I

I I I ace um ' I ft.

I
Eve nt
,>time
I
I

, I
',I
'- _ - __ 1_ - - - ~,--_«~-+_-+-_ _ _ _+--_ . -._._~_.L.-'
I
I
I
,

I
I

I
I
I

___---.'"

<:r

I
I

Event

Shift Count
( it EAE Command:; 000)

)otlme

,-- - - - -,- - - - -1-

I,..

if bit = I

-',- -

-+,------......-0-....-.........----1-'

0 0

ICommand=OOO) 10

(If E A E

I O u
I
I
I
:E
(j)

---........ ~

Event
>time

L ____ L ___ ...,....1 _ _ _ _ i ____ ..1 _____ 1..._..1..---'_--11""

Figure 3-4

EAE Instruction Bit Assignment

EAE BIT ASSIGNMENTS AND OPERATIONS
(Refer to Figure 3-4)

BIT
POSITIONS'

BITS

0, I, 2, 3

1101

FUNCTION
EA E operation code.

Place the AC sign in the Link. Used for signed operations.

Clear the MQ.

3-17

EAE BIT ASSIGNMENTS AND ;OPERATIONS (continued)

BIT
POSITIONS

BITS

Read the AC sign into the EAE AC Sign Register prior to
carrying out a stepped operation. Used for the signed
operations multiply and divide.

6, 7

FUNCTION

Take the absolute value of the AC. Takes place after
the AC sign is read into th~ EA E AC sign.
Inclusive OR the AC with the MQ and read into MQ.
(If bit 5 is a I, this reads the AC into the MQ).
;

C lear the AC.

9,10,

000

Setup: Specifies 'no stepped EAE operation, and enables
the use of bits 15, 16,and 17. It is used as a pre lim inary
to multiplying" dividing, and shifting signed numbers.
Execution time' is one cyc Ie.

9, 10,

001

Mu Itiply: causes the number in the MQ to be mu Itipl ied
by the number in the memory location following th is
instruction. If the EAE AC Sign Register is I, the MQ
will be complemented prior to multiplication. The
exclusive OR of the EAE AC sign and the Link wi II be
placed in the EAE Sign Register (the sign of product and
quotient) .
The product is left in the AC 'and MQ, with the lowest
ord.er qit in MQ, bi,t 17. The program continues at the
. Ibc'ation o(th instruction plus two. At the completion
of th is instru ction the Li nk is cleared and if the EA E sign
wosl, the AC and'MQ ore corriplemented. The step
count of th isinstr':Jction shou Id be 22 (octa I) for a 36-bit
mu Itipl ication, but can be varied to speed up the operation. The execution time is 4.2 to 8.7 ~s, depending on
number of I bits in the MQ.

9, 10, II

010

9,10, II

, :,' Oil

(Th is is an u~~sed operation code reserved for .poss ible
future expansion).
.;,
: Divide: causes the_ 36-bit number in the AC and MQ to
be divided by the IS-bit number in the register following
the.instruction.: If the EAE AC sign is I, the f'(\Q is

3-18

EAE BIT ASSIGNMENTS AND OPERATIONS (continued)

BIT
POSITIONS

BITS

FUNCTION
complemented prior to starting the division. The magn itude of the AC is taken by m icroprogramm ing the
instruction. The exclusive OR of the AC sign and the
Link are placed in the EAE sign. The part of the dividend
in the AC must be less than the divisor or overflow occurs.
In that case the Link is set at the end of the d ivide;otherwise, the Link is cleared. At the completion of this
instruction, if the EAE sign was I, the MQ is complemented; and if the EAE AC sign was I, the AC is complemented. Thus the rema inder has the same sign as the
dividend. The step count of this instruction is normally
23 (octa I) but can be decreased for certa in operations.
The execution time is 3.5 IJS in the case of d iv ide overflow or from 9. a - 12.6 IJS otherwise.

9, 10, II

101

Long right sh ift: causes the AC and M Q to be sh ifted
right together as a 36-bit register the number of times
specified in the step count of the instruction. On each
step the Link fills AC bit-a, AC bit-17 fills MQ bit-a,
and MQ bit-17 is lost. The link remains unchanged.
The time is 0.1 n + 1.6 IJS, where n is the step count.

9, 10, II

110

Long left shift: causes the AC and MQ to be shifted left
together the number of times specified in the step count of
the instruction. On each step, MQ bit 17 is filled by .
the Link; the Link remains unchanged. MQ bit a fills
AC bit 17 and AC bit a is lost. The time is O. 1 n +
1 .6 IJsec, where n is the shift count.

9,10, II

100

Normalize: causes the AC and MQ to be shifted left
together unti I either the step count is exceeded or AC
bit a -I AC bit I. MQ bit 17 is filled by the Link, but
the Link is not changed. The step count of th is instruction would normally be 44 (octal). When the step
counter is read into the AC, it contains the number of
shifts minus the initial shift count as a 2 15 complement
6-bit number. The time is 0.1 n + 1.6 IJS, where n is
the number of steps in the shift counter or the number
required to effect normalization, whichever is less.

3-19

EAE BIT ASSIGNMENTS AND OPERATIONS {continued}
BIT
POSITIONS

BITS

9, 10, II

III

12-17

FUNCTION

Accumulator left sh ift: causes the AC to be sh if ted left
the number of times specified in the shift count. AC
bit 17 is fi lied by the Link, but the Link is unchanged.
The time is 0.1 n + 1.6 J.1s, where n is the step count.
Specify the step count except in the case of the setup
command, which does not change the step counter.

On the setup command on Iy, causes the MQ to be
complemented.

On the setup command only, causes the MQ to be
inclusive ORed with the AC and the result placed in AC.
(If the AC has been cleared, this will place the MQ
into the AC).

On the setup command only, causes the AC to be
inc Ius ive ORed with the SC and the resu Its placed in
AC bits 12-17. (If the AC has been cleared, this will
place the SC into the AC).

Microprogramming High Speed Arithmetic

The following example uses the microprogramming capabi Iities of the Extended Arithmetic
Element to maximize speed in arithmetic operations. Consider the case of normalizing a
12-bit word located in the AC (possibly converted from analog data) by multiplying it by a
5-bit constant. The speed increase is achieved by reducing the step count of the multiplication to the minimum necessary for this particular case. Note also that the multiply instruction wi II, through m icroprogramm ing, move the contents of the AC to the MQ prior to the
multiplication operation. It is assumed that the desired result, a 17-bit number, will appear
in the AC subsequent to the operation. It is also assumed that the Link is 0 prior to the
instructions and that the 12 data bits represent an unsigned (positive) number.
The multiply instruction is formed with the following bit configuration. Bits 0-3 are EAE
instruction operation code; bit 5 is set to clear the MQ prior to the multiply instructions;
bit 7 is set to place the AC into the MQ prior to the multiply; bit 8 is set to clear the AC
at the same time; bits 9 and 10 are 0; bit 11 indicates a multiply EAE instruction; bits 12
through 17 are used to set the step count of the instruction. The desired step count is 11
decimal (13 octal). The octal code for this special multiply operation is 653113. After

3-20

multiplying, it is necessary to long left shift the AC and MQ to restore the product to the
AC only. The step count must be 11 for this instruction; hence, the octal code is 640613.
When programmed, the above multiplication routine occupies three sequential memory
locations, the multiply instruction 653113, followed by the 5-bit constant, followed by long
shift instruction 640613. The total execution time of this open subroutine is (average) 5.0
microseconds for the multiply, followed by 2.7 microseconds for the shift requiring a total
of 7.7 microseconds to normalize the 12-bit analog data. The final result appears as a
17-bit number in the AC where it is then available for further operations.
/multiply wi,th step count of 11 (13 octal)

muls - 7

norm,

/storage of constant
IIss + 13

/signed left shift with step count of 11
(13 octal)

EAE INSTRUCTION LIST

OCTAL

OPERATION

eae

640000

Basic EAE command - No operation.

Irs

640500

Long right sh ift .

Irss

660500

Long right sh ift, signed (AC sign => Link).

lis

640600

Long left shift.

IIss

660600

Long left shift, signed (AC sign => L).

als

640700

Accumulator left shift.

alss

660700

Accumu lator left sh ift, signed (AC sign => L).

norm

640444

Normalize: max. shift is 44.

norms

660444

Normalize, signed (AC sign => L).

mul

653122

Multiply C(AC) x C(C(PC)) as IS-bit unsigned numbers,
leave resu It in AC V MQ. The Link must be O.

muls

657122

Multiply signed, C(AC) x C(C(PC)). The C(C(PC)) must
be positive and its original sign must be in the Link.
The signed result appears in AC V MQ right adjusted.

MNEMONIC

3.. 21

EAE INSTRUCTION LIST (continued)
MNEMONIC

OCTAL

OPERATION

div

640323

Divide C(AC and MQ) as a 36-bit unsigned number by
C(C(PC)). Leave quotient in MQ and remainder in AC.
The Link must be O.

divs

644323

Divide C(AC and MQ) as a lis complement signed
number by the C(C(PC)). The C(C(PC)) must be positive
and its original sign must be in Link. The signed quotient
is in the MQ and the remainder, having the same sign
as the dividend, will be in the AC.

idiv

653323

Integer divide. Divide C(AC) as an IS-bit unsigned
integer by C(C(PC)). The MQ is ignored. The quotient
will be in the MQ and the remainder in the AC. Link
must be O.

idivs

657323

Integer divide, signed. Same as idiv but C(AC) is
17-bit signed and the usual convention on C(C(PC)) and
Link apply.

frdiv

650323

Fraction divide. Divide the IS-bit fraotion in the AC
by the IS-bit fraction in the C(C(PC)). The Link must
be 0; the MQ is ignored. The quotient replaces the
MQ and the remainder replaces the AC.

frd ivs

654323

Fraction d iv ide, signed. Same as frd iv, but C(AC) is
17-bit signed and the usua I conventions of C(C(PC)) and
'Link apply.

lacq

641002

Replace the C(AC) with the C(MQ).

lacs

641001

Replace the C(AC) with the C(SC).

clq

650000

Clear MQ.

abs

644000

Place absolute value of AC in the AC.

gsm

664000

Get sign and magnitude, thus setting up divisor or multipi icand. Places AC sign in the Link and takes the
absolute value of AC.

osc

640001

Inc Ius ive OR the SC into the AC.

omq

640002

Inc Ius ive OR AC with MQ and place resu Its in AC.

cmq

640004

Complement the MQ.

3-22

Signed Multiply and Divide Closed Subroutines
/ signed divide subroutine

37-42 JJS

/ co II ing sequence
/

dividend in AC + MQ

jms divide

pickup other factor

divide,

entry to subroutine

doc tem
xct i divide
gsm
doc divl
lac tem
divs

divl,

/ location of divisor

isz divide
imp i divide

/ signed mu Itiply subroutine

25-31 JJS

/ co II ing sequence:

/
/
/
mpy,

one factor in AC
jms mpy
pickup other factor

/ lac xxx or lac i xxx

/ entry to su broutine

gsm

/ fix multiplicand magnitude

doc .+3
xct i mpy

/ get mu Itipl ier

muls

/ location of mu Itipl icand

isz mpy

/ index return

jmp i mpy

3-23

CHAPTER 4
INPUT/OUTPUT CONTROL AND

INTERFACE

Functions
Information is transferred between the PDP-7 and peripheral equipment by the input/output
control. This interface sets up the information path between computer and device, controls
the transfer, and monitors the state of availability of each device. It also includes facilities
for data, clock, and program interrupts. Figure 4-1 shows in schematic form the section of
the input/output control. The input/output control is itself controlled by the programmed input/
output transfer (iot) instructions. An iot instruction causes the input/output control to produce
pulses. These pulses select an I/O device and initiate a data transfer. The single iot instruction is microprogrammed to control all input/output devices.

PDP-7INPUT/OUTPUT CONTROL
(ALL STANDERD

EQIJIPIv'EfJT)

----. - 3V LOGIC LEvELS,

--2.5VSTANDfRD
:

PULSES.

OaTS INOIC~JE UNLIMITED NL.;MBER
OPTlON,l.LLf

AVA I LABLE

Figure 4-1

I/O Control Schematic

4-1

lOT INSTRUCTION
The input/output transfer (iot) instruction causes the input/output control to produce pulses
which select I/O devices and transfer information. All iot instructions are octal code 70
with a bit assignment as shown in Figure 4-2.
Mnemonic

Instruc tion Code

iot

700000

Operation
Code

Sub-Device
Selection

Operation
i nput/ou tpu t transfer

Device
Selection

Sub-Device
Selection

10 11 12 131 41 5161 71 81 9110 11q 121131141151161171

1~
J
=.J

If Bit Is a 1:
{

Figure 4-2

Clear AC at event time
Transfer an lOT pulse at event time 3
.
Transfer an lOT pulse at event time 2

Transfer an lOT pulse at event time 1

Bit Assignment for Input-Output Transfer Instruction (jot)

Bits 0-3 signify the iot instruction. Bits 4-13 specify the external device and its mode.
When bit 14 is a 1, the accumulator will be cleared prior to the data transfer. Bits 15-17
select the pulses sent to the device during event times 1, 2, and 3. For ease of recognition,
the iot pulses are coded according to bits 17,16, and 15as I/OP1, I/OP2, and I/OP4
respectively. I/OPl is used to check the status of a device. I/OP2 and I/OP4 are initiated
by the device selector to cause a transfer of information to and from the information collector
and the information distributor.

PROGRAM FLAGS
The status of each I/O device is indicated to central processor by flag bits. A program reads
the flag bits of a device and initiates appropriate action. In this way, input/output transfers
and program operation are easily coordinated. Flags are connected to the program interrupt
control, status bits, and the input/output skip facil ity.
A flag may indicate one of several things depending upon the location of its connection.
1.

Connected to the program interrupt, a flag indicates that:
a.

An output transfer has been completed and the device buffer is now available
for refi II ing.
4-2

An input buffer conto ins information for transfer into the computer.

A device operating asynchronously has information for input or requires
information for output.

Connected to the input/output skip facility, a flag may indicate:
a.

Skip the next instruction if the device buffer if full.

Skip the next instruction ifan output operation has been completed.

Connected to the status register, a flag may indicate the:
a.

Occurrence of an error

Direction of data transfer

Direction device is operating, forward, reverse

Mode of operation in a device

Subdevice connec ted to a centra I device

Busy or idle condition of a device.

DEVICE SELECTOR (DS)
The device selector selects an input/output device or subdevice according to the address code
of the device in memory buffer bits 4-13 of the iot instruction. It then generates an I/OP
pulse at event 1 if memory buffer bit 17 is a 1, event time 2 if memory buffer bit 16 is a 1,
and at event time 3 if memory buffer bit 15 is a 1. The I/O event times differ from those of
the microporgrammed operate group event times. A complete table of the I/OP pulses and
corresponding times is given below and in Figure 4-4.
Event
Time

Computer
Cycle Time

Instruc tion
Bit

I/OP
Number

I
2

17
16

1 (next cycle)

2
4

Upon receipt of an iot instruction, the device selector determines which device has been
selected, and then performs one or all of the following functions:

4-3

I/OP 1 is used to sense the state of the flag or flogs associated with a device.

I/OP 2 is used to clear the flag or flags associated with a device and to read
the contents of the device buffer into the Ie.

3. l/OP 4 is used to transfer data from the accumulator through the information
distributor into the buffer of an output device or to initiate operations within
a peripheral device (ex. a line of perforated tape is read into the tape buffer
or a card is,moved to a reading or punching station).

The specific function or functions an I/OP performs are selectable and depend on the device
and its timing requirements. A device may use any number of combinations of the three pulses.
Devices requiring more than three pulses may use multiple device codes. For extremely expanded mode selection, a device may sense the state of the accumulator bits loaded prior to
the iot instruction.

The 6-bit device selection numbers, memory buffer bits 6-11, are decoded by a diode
decoder module B171. (See Figure 4-3.) The 6-bit code, therefore, produces an assertion
level for the selected device. This level, in turn, controls I/O pulses through the device
selector gates. The device selector amplifiers transmit pulses to the selected device according to bits 15,16, and 17 of the iot instruction. These pulses can be of various types,
depending on the type of the pulse amplifier used. Two different pulse amplifiers are
avai lable and produce the following range of (ground reference) pulses:

2.5 volts, positive or negative pulses at 70-nanosecond intervals

2.5 volts, positive or negative pulses at 400-nanosecond intervals

The standard device selector contains selector modules for the standard devices and has provisions for up to 6 additional decoders, gates, and amplifiers. When additional peripheral
I/O devices are added to the PDP-7, a device code is easily establ ished in the device selector by clipping out the diode of the unasserted level in the B171 module. Figure 4-3 shows
the B171 with the clipping point marked with a (8).

Slow Cycle
For input/output equipment requiring a timing pulse chain slower 'l'h(.l:-~ the normal I/O pulse
cycle, a second timing chain may be requested by a signal from the device selector (see
Figure 4-4). The slow cycle permits equipment with slow logic to be easily interfaced to a
PDP-7 system.

4-4

-- -------

-T-....J
I

r/op
r/op 2
l/OP 4

r----- --------------8171

r------.,
I

M 8 6 (0)

MB6

(1)

J
I

r-------~
K

M 8 7 (0)

M 87 (1)

L
I

r- ------~
M

80 1-----..;.:_ _-QDo_;.;..;M~..;>t__<lO_--_,

a 8 (0)

I
I

M 88

(1)

IV1 b' 9

(0)

~--"":"---<JI 8 0 1------;.:_-:..-Ol>_..:..;N~ .:JII-~IO------'

~-------1

1\189 (1)

~--

- - - ---I

M 8 10 (0)

M 8 10 (1)

T
I

~ ------~

M 811 (0)

M811

I
I
L

I
_ _ _ _ _ _ .J

Figure 4-3

________________

Device Selector Decoder

4-5

The slow cyc Ie tim ing cha in is preset by DEC to give optima I operation for the slowest piece
of I/O equipment in the computer system. Only one slow cycle time can be requested by
the DS. The PDP-7 enters the slow cycle each time an iot instruction is given to transfer data
to or from a slow device.

INFORMATION COLLECTOR (IC)
The information collector is a seven-channel gated mixer which controls the transfer of 18-bit
words from externa I devices to the accumu lator. Pu Ises from the DS control the IC gates according to the device specified by the iot instruction. Because the accumulator must be cleared
before a word is transferred through the IC to the AC, the iot instructions are usually microcoded to clear the accumulator (bit 14 is a 1) at the same time the external device is activated.
In the standard PDP-7, seven channels of IC are used. The paper tape reader and I/O statvs
bits each occupy one 18-bit IC channel. The teleprinter occupies eight bits of a third channel. The remaining four and one-half channels are available for connection to any peripheral
and optional input equipment. Each PDP-7 input option connects directly into one channel
of the IC (ex. Extended Arithmetic Element Type 177, A-D Converter Type 138, DECtape
Control Unit Type 550).
For operation of more than seven input devices, the IC is easi Iy expandable in blocks of
seven channels to accommodate any number of channels.
The modules used in the IC are the seven-channel R141 gates. The R141 accepts standard
levels of 0 and -3 volts or standard 70-nanosecond or wider pulses. The input load is 0.5 rna
per grounded input.
Bits transferred to the AC correspond to the incoming polarities:

o volts

o tra nsm i tted to AC

-3 vol ts

1 transm i tted to AC

INFORMATION DISTRIBUTOR (ID)
The information distributor is an output bus system through which information is transferred from
the accumulator to external devices. Eighteen line drivers buffer and drive the accumulator
output through the external device connection cables. Other drivers and cable slots are used
to transfer memory buffer and device control bits. Six 18-bit ID channels are standard on the
PDP-7. The paper tape punch and teleprinter use two of the six channels. A third channel is
used for the expanded ID connection.
Other external devices are easily connected to the information distributor. Each device receives pulses from the device selector to gate in bits from the bus.
The I D can be expanded to any number of output channels.

4-6

NORMAL IIO PULSE CYCLE (TIMES IN j.lsec)

INPUT/OUTPUT PULSE CYCLES
NORMAL

If T2

n n 0
h

0.20

.0·

0.60

000
0.10 0.10

0.50

II I

T1 T2

n n nn
0.20

MB AVAILABLE

0.20

0.60

nnn
0.10

I I 'I

O.tO

0.50

D STD. DEC PULSE, 40 Ns

1/0 PULSE

CYCLE

II I[MB 14(1):0-Aq AC CLEAR FOR INPUT I
I

TIMING PULSE

STD, DEC PULSE. 70 Ns

1.75 psec

SLOW
TIMING PULSE

I I

AC READY FOR OUTPUT

STD. DEC PULSE. 40 Ns

1/0 PULSE

STD. DEC PULSE, 400 Ns

CYCLE

PRESET BY DEC

I I
I10P4

••

I10P1

I/OP2

I/OP =70 Nsec •

SLOW 1/0 PULSE CYCLE (TIMES IN .usee)
T6

T1 T2

If T2

MB AVAILABLE

I/OP4
I/OP=400 Nsec

Figure 4-4

I/O Pulse Cycle Diagram
4-7

The signal polarities presented to the output device by the 10 are:
-3 vol ts

AC bit contains a 0

o vol ts

AC bit conta ins a 1

INPUT/OUTPUT STATUS
The status of each I/O device, as indicated by its flags, may be read into assigned bits of
the AC. Figure 4-5 shows the standard assignment for the commonly used devices. An X indicates that the flag is connected to the program interrupt control. The presence of a flag is
reflected by a 1 in the corresponding AC bit.
The status of 18 flags may be read into the AC at one time using the following iot instructions.
iors

Input/output read status. The contents of
given flags replace the contents of the assigned AC bit.

700314

XIX

X I X

I)()(

101 1 I 2 I 31 4161 61 71 81 91101111121131141161161
Program Interrupt On
Tape Reader Flag
Tape Punch Flag
Keyboard Input Flag
~ype.Out

Flag

Display Flag

I .~

"I.

~~
> ASSIGNABLE

Clock Overflow Flag
Clock Enabled

...

Magnetic Tape Interrup t
x'· Program Interrupt Connected

Figure 4-5

Input-Output Status Instruction - Bit Assignment

INPUT/OUTPUT SKIP FACILITY (lOS)
The input/output skip facility enables the program to branch according to the status of an externa I device. The lOS has fourteen flag inputs and is expandable to any number, five of
which are used by the basic computer equipment. When an input/output skip instruction is executed, the DS sends iot pulses to the selected device input. If the flag connected to that
input is set to 0, the next instruction in the program sequence is executed. If the flag status
is 1, the next instruction is skipped. An I/O pu Ise for a skip must occur at event time 1.
The I/O skip facility is expandable through the addition of R141 modules, each of which contains seven additional skip inputs. A -3 volts indicates the presence of a flag.

4-9

Commonly used skip instructions are:
clsf

700001

Skip if clock has overflowed.

rsf

700101

Skip if paper tape reader buffer has a
character.

psf

700201

Skip if paper tape punch is ready.

ksf

700301

Skip if teleprinter keyboard buffer has a
character.

tsf

700401

Skip if teleprinter is ready to output.

dsf

700501

Skip on display flag (I ight pen).

cpsf

706401

Skip if card punch is ready.

Ipsf

706501

Skip if line printer is ready.

Issf

706601

Skip if I ine printer spacing flag is a 1 .

crsf

706701

Skip if card reader buffer has a character.
INPUT/OUTPUT TRAP

The PDP-7 I/O trap is designed to simplify programming of sophisticated input/output routines
and to provide the basic hardware necessary for a time-shared or multi-user system. The effect
of the trap is to insert a program break in place of the iot instruction. Two other conditions
are also trapped, an xct instruction whose subject instruction is also an xct and the hit portion
of an operate class i nstruc tion.
The trap provides the PDP-7 with the basic hardware necessary to use the PDP-7 in a timeshared mode. With the use of the extend and trap modes, multi-user installations with full
memory bank protection are possible. A program operating on one or more independent 8K
(or smaller) memory banks can be protected from accidental disturbance by a program operating
in other memory banks. All I/O operations can be mon itored to check for use of restricted 1/0
devices or restricted memory locations. In this way, the PDP-7 can be used for real-time process control and simultaneously be available to share time with other programs in other memory
banks without the threat of program interference.
The trap mode is enabled by the iton instruction (700062) with the console trap switch on. The
trap mode is disabled by any program break. The iton (700062) also turns on the program interrupt through a microcoding of the ion instruction (700042). Since the I/O trap may not be
disabled by a program without causing a program break, control over input/output rests entirely
wi th the I/O interrupt routines. Other uses of the program interrupt and extend mode are controlled by the trap, for the extend status may not be changed and the interrupt mode may not be
disabled by a program running in the trap mode.
4-10

The trap initiates a sequence of events depending on the trapped instruction.
iot

An iet instruction is trapped.

xct

An xct of an xct instruction is trapped.

hit

A microprogrammed hit of an operate class (740040) instruction is trapped.

A program break in place of the trapped instruction increments the program counter and
stores its contents in location 0, bits 3 to 17, stores the link in bit 0, stores the extend status
in bit 1, and stores the status of the trap mode in bit 2 (in this case 1). Control then
'transfers to location 2. The extend mode is enabled and the program interruptis turned off.
The next instructions are taken from the appropriate I/O routine.

PROGRAM INTERRUPT CONTROL (PIC)
The program interrupt control increases the efficiency of input/output operations by
freeing a program from the necessity of constantly monitoring program flags. When the PIC
is enabled and a peripheral device becomes available, the PIC automatically interrupts the
program sequence and causes a program break to occur. A subprogram beginn ing at the
break location may then sense the program flags to determine which of the devices caused
the interrupt. The device is then serviced and control returns to the main program. Fourteen
device flags connect to the basic PIC, and more flag connections can be easily added.
The PIC may be enabled or disabled by the program. When it is disabled, program
interrupts do not occur, although device flags may be set. Interrupts for these devices occur
when the PIC is re-enabled. When the computer is operating with interrupt-producing
devices, the PIC is normally enabled.
The following iot instructions control the PIC:
iof

700002

Interrupt off.

Disable the PIC

ion

700042

Interrupt on.

Enable the PIC

Each of the input/output devices has associated with it a program flag which is set whenever
the device has completed a transfer and is ready for another. When the interrupt is enabled
and the device is ready, the setting of the device flag (connected to the PIC) causes a
program interrupt. The main instruction sequence is halted, the program counter, link,
extend mode, and trap mode status are stored in location 0 and control transters to location
1. Thus, 9 jms 0 has effectively been executed. The interrupt is then disabled and the
extend mode is turned off. The word stored in location 0 has the following format:
o

3 4

4-11

Example
When the program interrupt is used to free the central processor between data transfers on a
slow I/O device, the PDP-7 can do arithmetic or other I/O transfers whi Ie the slow device is
in operation. The following sequence gives the lim iting usable rate at which the PDP-7 could
acknowledge repetitive program interrupts from the same device. Each data transfer is 18 bits.

/ conf'ents of PC and Link
SERVICE
TEMP

/save AC
/transfer data from device buffer
Ito AC

/store data in memory list

COUNT

.+2
END
TEMP

/reload AC
/turn on interrupt

/return to program

The routine takes 16 machine cycles, or 28.0 microseconds per loop. When operating with a
slow I/O device, the PDP-7 can perform other computations or other input/output operations
in between program interrupts.
If the paper tape reader (300 cps), paper tape punch (63 cps) and'teleprinter (10 cps) were all
operating at full speed simultaneously through the PIC, the per cent computer time taken for
I/O servicing is roughly

%1/0 time = device rates (cps) x service time (I-ls/interrupt) x 1O~
10
In this case,

0/0 I/O time = (300+63+10) x (28) x ,1 O~
10
or the time required to service the paper tape reader, punch, and teleprinter operating simultaneously in roughly less than 1.5% of the computer time.

4-12

The rQutlne beginning in location 1 is responsible for finding and servicing t~e device that
caused the Interrupt. When a program Interrupt occurs, the PIC is automatically disabled
since only single... level interrupting is provided. ThE;l interrupt routine can re-enoble the
interrupt mode at any time.
The status of the PIC is displayed on the operator console by the indicator marked PI EI
program interrupt enabled.
AUTOMATIC PRIORITY INTERRUPT TYPE 172
The (optional) Automatic Priority Interrupt Type 172 increases the capability of the PDP-7
to hand Ie transfers of information to and from input/output devices. The 172 identifies an
interrupting device directly without the need for flag search ing. Mu Iti-Ievel interrupts
are permissible where a device at higher priority supel'$edes an interrupt already in process.
These functions incr.,ase the speed of the input/output system and simplify the programmIng.
In th is way more and higher-speed devices can be serviced efficiently.
The Type 172 contains 16 automatic interrupt channels arranged in a priority choin so that
channel 0 has the highest priority and channel 178 has the lowest priority. Each channel is
assigned a unique, fixed, memory location in the range of 408 through 57B starting with
channel 0, When establishing priority, each I/O devjc:~ is assigned a unIque interrupt
channel. The priority chQin guarantees that if two or more I/O devices request on interrupt
concurrently, the system grants the interrupt to the device with the highest priority. The
other interrupt requests wi" be Serv iced afterward in priority order.
.
The automatic priority interrupt is assigned a priority just below that of the data interrupt,
a position held by the real time clock. The 172 replaces the real time clock. The priority
interrupt system may operate in either of tWQ modes, the multi .. instruction subroutine mode
or the single instruction subroutine mode. The mode is determined by the instruction in the
memory location assigned to the channel.
The Multi ... lnstruction Subroutine Mode .
This mode is generally used to service an I/O device that requires control informQtion from
the PDP .. 7. Such devices are alarms, slow electromechanical devices, teleprinters, punches,
etc. Each device requires a servicing subroutine that includes instructions to manipulate
data and give further instructions, such as continue, halt, etc., to the interrupting device.
An interrupt request from a device is granted if the following conditions are met:
The 172 is in the enabled condition (by program control).
There is no data interrupt request present.
The requesting channel is in the enabled condition (by program control)'
There is no interrupt in progress on a channel of higher priority.
There is no interrupt in progress on the requesting chQnnel.
When an interrupt is granted, the contents of the channel memory location are transferred
to the M B and executed. If the instruction executed is jms Y, the system operates in tf1e
multi.,instruc!ion subroutine mod~. The contents of the program counter and the condition

4-13

of the I ink are stored in location Y, and the device-servicing subroutine starts in Y + I.
(Note that it is often usefu I to store the contents of the AC before servicing the device and
to restore the K. prior to exiting from the servicing routine.)
The interrupt flag is normally lowered by the 172, but can be lowered by an iot instruction
if desired. Program control now rests with the servicing routine.
A return to the rna in program is accompl ished by a restore the AC and Iink, a debreak int
and a jump indirect to location Y, where the contents of the PC prior to interrupt are
stored. The debreaking iot requ ires no channel designator, since the interrupt priority
chain au tomati ca lIy rei eases the correct channe I and returns it to the re,ceptive state.
This iot norma Ily inh ibits a II other interrupts for one memory cycle to insure that the jump
indirect Y is executed immediately.
The following"program example illustrates the action that takes place during the multiinstruction subroutine mode . Assume an interrupt on channel 3 .
. Memory' 'Loco t ion·

Instruction

1000

add 2650

Instruction being executed when inferhJpt
request occurs.

0043

jms 3000

Instruction executed as resul t of interrupt
on channel 3. The jms"deterrnines multiinstruction mode.
.

Function

3000

3001

The link, condition of the extend mode,
and the PC are stored in location 3000.
dac 3050

First instruction of servicing routines
stores AC.

3002
3003
3004

Instructions servic ing the interrupting inout device.

3005
3006
3007

lac 3050

Restores AC for main program.

3010

dbr

Debreaking iot releases channel.

'3011

imp i 3000

Return to main. program seque'rice.

'1001' .

Next instruction executed from here unIess another priority inte~rupt is waiting.
4-14

The Single Instruction Subroutine Mode
In some instances, it is desirable for the PDP-7 to receive information from an external
device but not to send control information to the device. Such an applicatIon would be
the counting of real time clock pulses to determine elapsed time. The single instruction
sub routine mode simpl ifies programm ing a counter.
An interrupt request is subject to the same conditions as in the multi-instruction mode, and
the appropriate memory location is addressed as before. Then the single instruction subroutine mode is entered if the channel memory location does not contain a jms instruction.
Normally the instruction is isz. In any case, since the single-instruction constitutes the
entire subroutine, the interrupt system automatically lowers the interrupt flag, debreaks
the interrupting channel, and returns the channel to the receptive condition.
If the isz instruction is used, the 172 acknowledges only the indexing operation and neglects
the skip to avoid changing the contents of the program counter. If an overflow results from
the indexing a flag is set. Th is flag can be entered in another channel of the interrupt
system to cause a further program interrupt.
The following program coding illustrates operation in the single instruction subroutine
mode. Assume an interrupt on channel 6.
Memory Location

Instruction

1200

doc 1600

Operation being executed when interrupt
occurs.

0046

isz 3200

Instruction executed as a result of break
on Channel 6. If overflow, flag is'
set, PC not changed.

1201

lac 1620

Next instruction in sequence of main
program.

Operation

Priori ty Interrupt Instruc tions
The following instructions are added to the PDP-7 with the installation of the 172. Some
instructions, for example cac and asc, can be microprogrammed.
Octal Code

Mnemo"nic

cac

705501

Clear all channels. Turn off all channels.

asc

705502

Enable selected channel{s}. AC bits
2-17 are used to select the channel{s).

Operation

4-15

dsc

Disable selected channel{s),

705604

AC bits

2-17 are used to select the channel{s),
epi

'100004

Enable automatic priority interrupt system.
Same as rea I time clock cion. .

dpi

700044

Disable automatic priority interrupt system.
Same as real time clock clof.

isc

705504

Initiate break on selected channel (for
maintenance purposes). AC bits 2-17
are used to select the channel.

dbr

705601

Debreak. Returns highest priority channe I
to receptive state. Used to exit from multiinstruction subroutine mode.

AC bits 0 and I are available for expansion of the basic automatic priority interrupt system
to 4 groups of 16 channels.

REAL TIME CLOCK
The clock produces a pulse every 1/60 second (16.7 milliseconds), When the clock is
enabled, every clock pulse causes a clock interrupt. The clock interrupt is sim ilar to a
data interrupt in that the contents of an active register are not changed. This interrupt has
priority over a program interrupt but is of lower priority than a data interrupt. During
the interrupt the contents of memory location 7 are incremented by I. If the contents
of location 7 overflow, the clock flag is set to I. The clock flag is connected to the
program interrupt system and may cause a program interrupt.
Three iot instructions are associated with the clock:
clsf

700001

Skip the next instruction if the clock flag
is set to I.

clof

700004

Clear the clock flag and disable the clock.

cion

700044

Clear the clock flag and enable the clock.

Clock frequencies other than 60 cps can be (optionally) selected for use with the clock
interrupt. Depressing the START key on the operator console clears the clock flag and
disables the clock.
Since the clock registerisincorememorylocation7, its contents may be loaded or deposited

by a program. A standard technique for using the clock is to preset the contenh of location
7 with the complement of the desired count and then to enable the program interrupt and
the clock. An interrupt wi II occur at the end of the desired time. To cause an interrupt
at the end of I second ,the following routine can be used:

4-16

imp end-of-time

clock

lam* -60

/Ioad -60 into accumulator (same as
law 17720).

dac 7

/preset clock to -60.

cion

/turn on clock.

ion

/turn on interrupt.
/continue with I second worth of program.
DATA INTERRUPT CHANNEL

The data interrupt channe.!' allows a high-speed input/output device such as a magnetic
tape unit or drum, to operate independently once the information transfer has been initiated.
The data address (15 bits) is transmitted directly to the memory address register. The data
itself is read directly into the MB, bypassing the AC entirely. Since the data interrupt
has priority over all other interrupts, a request will be granted at the completion of the
current instruction. When a data interrupt occurs, the program is delayed for one cycle
wh iI e the transfer is made; the program then resumes. A transfer rate of 570, 000 IS-b it
words/second (1,710, 000 6-bit characters/second) is possible.
The external device must supply 15 address lines, IS data lines, a request line, and a
transfer in (out) line. A" Iines are -3 vo Its for assertion, ground for O. To accommodate
slow I/Odevices, the external device may request the computer to slow its cycle for the
duration of the transfer (see OS, Slow Cyc Ie).
The optional Type 173 Data Interrupt Multiplexer increases the data interrupt facility to
4 channels arranged in a priority chain. Thus, several high-speed devices such as a Type
57A Tape Control, a type 24 Drum, etc., may operate simultaneously at a maximum combined transfer rate of 570 KC words/second.
The optional Type 174 Data Control controls and buffers high speed transfer between the
computer and external devices which do not have the necessary control facilities. The
Type57A Tape Control and Type 24 Drum do not require this data control. Maximum
transfer rate is 570 KC words/second.

*Iam is a pseudo-instruction to the assembler which generates the equivalent machine instruction using a law instruction.
4-17

DATA INTERRUPT MULTIPLEXER CONTROL TYPE 173
The Data Interrupt Multiplexer Type 173 permits four high-speed input/output devices to operate into the standard PDP-7 data interrupt channel. The 173 operates at a combined transfer
rate of 570, 000 18-bit words per second and is designed for use with high-speed equipment such
us magnetic tape systems, drum systems, and mu Itiple high-speed ana log-to-digita I converters.
The 173 mu Itiplexer operates through the standard data interrupt fac iI ities of the PDP-7 computer'.
A signal to the data interrupt control causes the operating program to halt or pause for one cycle
while the information is either deposited. or removed from core memory. During this pause,
'fhere is no change in the status of the arithmetic registers. The operating program automatically
resumes after the mu Itiplexer access.
When an external device is addressed or addresses core memory through the Type 173 Multiplexer
and the data interrupt, the following events occur:
1.

The multiplexer switches to the device.

A - 3-volt level from the 173 control to the device indicates that the
centra I processor is ready for the data break.

The 1 .75-microsecond data break cycle begins.
Time 1 Computer samples the 15 address lines.
Time 2 Data is transferred in or out of core memory through the
173 multiplexer.
Time 3 Data is transferred in or out of core memory through the
173 multiplexer.

End of data break is indicated by -3-volt level on the multiplexer select
line.

Line connections to the multiplexer control must supply the da'ta, an address, the direction of
transfer, and the data request signa I:
Data

18 data lines, -3 volts asserts a 1 bit.

Address

15 address lines, -3 volts asserts a 1 bit.

Direction

One line, - 3 volts indicates data transfer into the multiplexer;

a volts indicates data transfer out of the multiplexer.
Data Request

One line, - 3 volts for data request.

4-18

(15)

Address Lines

Request for Transfer

(1)

Direction of Transfer

(1)

Data Bits -IN

- 3 volt level for assertion

•
•
•
•

(18)

- 3 volt level for assertion
-3 volt level for IN (from device to computer)
GND for OUT (from computer to device)
- 3 volt level for assertion

The following lines are sent from the data multiplexer control to the device:
MPXB Sel

1 per device

DATA" B

(1)

-- 3 volt level when the device is selected

•
•

- 3 volt level when a data request has been
granted and thei computer is lin a break
-3 volt pulse occurs at computer cycle time
one, address accept time. (70 NS pulse)

-3 volt pulse occurs at computer cycle time three,

data accept or transfer out time. (70 NS pulse)

DATA-OUT

.....
CENTRAL
PROCESSOR

{~
2

(I!I)
(I!I)
U!I)
(I!I)

r-IL-

r---o
ADDRESS LINES
FROM DEVI CE

DATA-S

DATA
ADDRESS
~ MULTI PLEXER
~

)

E~:S'NFO
FROM DEVICE

{

(8)
(18)
(18)
(8)

(I)

{

IN (OUT)

RQ
IN lOUT)

Figure 4-6

RQ
IN (OUT)

".'.'::

-::

DATA
MULTIPLEXER
SUFFERS

-:.

REQUEST FOR
TRANSFER AND
DIRECTION OF
TRANSFER FROM
4 DEVICES

DATA
INFO
~ MULTIPLEXER

DATA
MULTIPLEXER
CONTROL

.-.I

Data Interrupt Multiplexer Signal Diagram

4-19

(I)
DATA·S
(I)
MPXS SEL

(1)-DATA-OUT
(18) -

DATA CONTROL TYPE 174
The Data Control Type 174 controls and buffers the transfer of data blocks between the
PDP-7 and up to three external devices. Block transfers are made from consecutive memory
locations to one device at a time. The data control counts the number of data words transferred, buffers either incoming, or outgoing information until the transfer is complete and
signals the completion of a transfer. Maximum data transfer rate is 1.75 microseconds per
la-bit word, or 570,000 la-bit words per second.
Data is transferred between the two la-bit buffers of the data control and the PDP-7 through
the memory buffer register. The data control, includes four hardware registers: two data
buffer registers, one word count register, and one initial location register. The word
counter contains the complement of the number of words to be transferred in a block and is
indexed on each transfer. The location register contains the address of the next data word
to be transferred and' is indexed on each transfer.
The PDP-7 lOT instructions initiate a transfer of control information to the Type 174 Data
Control registers. The initial memory address specifications, direction of transfer and word
count are all sent from the accumulator through the information distributor to the 174
control. Once it is initiated, a transfer of block data is interleaved with the running
program and requires no additional instructions.
Completion of a block transfer can be indicated through the program interrupt channel or
through the automatic priority interrupt channel. The data control may be operated
directly through the data interrupt channel on the PDP-7 or indirectly through the Data
Interrupt. Multipl'exer Type 173. Up to four 174 Data controls can draw information through
the data interrupt multiplexer.

4-20

CHAPTER 5
MEMORY EXTENSION CONTROL TYPE 148

The Type 148 Memory Extension Control allows the expansion of the PDP-7 memory from
8,192 to 32,768 words in increments of either 4,096 or 8,192 words, using the Type 149
Memory Modules. The Type 148 includes an Extended Program Counter, an Extended
Memory Address Register, and an Ex'tend Mode Control. Locations outside the current
8,192 word field are accessed by indirect addressing while in the Extend Mode. In this
mode, bits 3-17 in the effective address of an indirectly addressed instruction contain the
M,emory Field Number (bits 3 and 4) and the Memory Address (bits 5-17). If not in the
Extend Mode, bits 3 and 4 of the effective address are ignored and the field number is
taken from the Extended Program Counter. Thus, when not in the Extend Mode, the
instruction and data must be in the same 8,192 word field. In the following example, the
program starts at location 66666 (Memory Field 3):
66666/

lac i 2345

62345/

54321

The effective address, 5432~ is interpreted as follows:

Octal

5
Bit

Binary
Extended
Memory
Address

2
17

345

11 0 111 0 01 0 110.1 01 0 0 11
2

I
I
I1
I

Field

Address

If not in the Extend Mode, bits 3 and 4 are ignored and the memory address is interpreted
as 14321 in the current memory field 3. The physical address is 74321.
The current memory field, from which instructions are executed, is stored in the Extended
Program Counter (EPC). The EPC is changed by jumping <imp i or jms i) while in the
Extend Mode. The Pr~gram Counter (PC) will not increment across memory field boundaries,
it counts from 00000 to 177778 and back to 00000 of the current memory field. A load
8
8
accumu lator instruction" or other memory reference instructions with indirect addressing

5-1

(lac i), can access data from any memory field, however, it does not change the EPC.
In the Extend Mode, cal goes to location 00020 of field O. When not in the Extend Mode,
it goes to location 20 in the current field. Program interrupts always reference field 0,
location O. Extend Mode is automatically cleared and the condition is stored in the bit
position one (I) of location O. The Extend Mode condition may be re-established at the
end of an interrupt routine by the instruction emir. The following diagram illustrates the
configuration of bits wh ich are stored in location 0 on a program interrupt.

3 4

7
PC
EXTEND

EPC

Figure 5-1

PIC Word Format

Each memory field which is added contains eight auto-index registers as does the basic
memory. The locations for auto-index registers with 32K of memory are:
00010

00017

20010

20017

40010

40017

60010

60017

Four instructions are added with the Type 148 Memory Extension Control:
sem

707701 Skip if in Extend Mode

eem

707702 Enter Extend Mode

lem

707704 Leave Extend Mode

emir

707742 Extend Mode Interrupt Restore

The following sequence will re-establ ish the condition of the Extend Mode upon completion of an interrupt servicing routine:
emir

/Extend Mode Interrupt Restore

ion

/turn program on

imp i 0

/return

5-2

The actual ef feet of the em ir instruction is to turn the Extend Mode on then off again if
the effective address of the imp i 0 instruction has bit 1 equal to 0, (Extend Mode was off
when the interrupt 'routine was entered). The em ir instruction can be given at any time
prior to leaving the interrupt routine and indirect addressing may be used without effect
on the Extend Mode. Onl y imp i will restore the Extend Mode Condition.
Ex isting programs lacking Extend Mode instructions can operate within any memory field
interrupt, If interrupt is used, the following routine
must be in field O.
pr~Y iding they do not use program

imp

SIM

SIM,

doc

/save AC

lac

/pick up return

and

MASK

/select field bits

doc

ADDR

/set up new location

lac

/pick up return

emir

/Extend Mode interrupt restore

doc i

ADDR

/store in new location

isz

ADDR

/set up jump

lac

/restore AC

imp i

ADDR

/return

ADDR,
MASK,

260000

AC,
Data interrupts must supply a IS-bit address. The cond ition of the Extend Mode is not
changed.

5-3

CHAPTER 6
PROGRAMMING

The purpose of th is chapter is to introduce the basic aids of programming and program preparation. The complete description of each program is given in its accompanying Program Library
Document. Questions regarding programs and programming techniques should be addressed to
the Manager of Applied Programming, Digital Equipment Corporation, Maynard, Mass.
Programming aids introduced:
Assembler
DDT (Digital Debugging Tape)
Editor
FORTRAN
BUS-PAK II

ASSEMBLER
The PDP-7 Assembler is a one-pass system which translates a symbol ic source program into a
form suitable for execution. The source program permits the user to express the operations he
wishes the computer to perform in a form more legible to the programmer than the binary code
in which the PDP-7 must receive its instructions. Instructions for the central processor and
input/output standard options are inc luded in the assembler.
By using this assembler, the programmer may employ mnemon ic codes for the instructions and
assign symbol ic addresses in the program. For example, if the programmer uses the characters
"lac," the assembler will transform this to the value 2000008 as stored in memory. The assembly process consists of substituting the value of each symbol for the symbol itself and punching
it out on the binary output tape.
During assembly, the assembler keeps a current address indicator which indicates the address
of the register into which the next instruction or data word will be stored. For each word
assembled, this address is increased by one. The initial address may be preset to allow assembly
at any location. Normal assembly starts at location 22.
The;l1assembler performs its action in one pass (i. e., the source language tape is processed only
once t produce the binary object language tape). Certain functions which cannot be handled
at a embly time must be handled by the loader when the program is loaded into memory.

/
Nsummary of the more important parts of the source language is I isted below.
list, refer to the PDP-7 Assembler Manual.

6-1

For a complete

Source Language
1.

Character Set
All of the lower-case characters of the alphabet are used along with numerals and certain
punctuation characters. These punctuation characters and their meaning to the assembler
are Iisted below.
Symbol

Meaning

space

add syllables

plus

add syllables

minus

subtract syllables

logical and

combine syllables

logical or

combine syllables

carriage ret.

term i nate words

tabulation

terminate words

comma

term i nate words

equals

define a parameter

slash

comment,. or address assignment

(

left paren.

in itiate constant

)

right paren.

terminate constant (optional)

period

current address indicator

+
&

Syllables
(a) Number - any sequence of digits delimited by punctuation characters.
ego

1
12

4374
(b) Symbols - any sequence of characters delimited by punctuation characters with
the initial character alphabetic (a-z).
ego

a
a121b
larrys

6-2

(d) Constant - a number or syllable consisting of one of the following forms:
(alpha)
(alpha ).
(a Ipha-t--l
Constants may consist of several syllables connected by syllabic operations as
long as no more than one syllable or symbol is undefined.

Express ions
The va lue of an expression is computed by combining the component parts in the
manner indicated by the connecting punctuation.

ego

a+3
lac a-5
szaVsnl
Note: The instructions "szl", "sna~1 and "spa" may be combined to form an expression;
the instructions "snl'~ "sza II and "sma" may also be combined . However, instructions from
one set may not be combined with instructions from the other, due to the use of bit 8.

Storage Words
Storage words are express ions del im ited by tabs or carriage returns. They occupy
one register in the program.

ego

lac a
imp .+5
lac (4)
add 520
lac (imp b-6

Symbol definitions
(a)

Parameter - may be assigned with the use of the equals sign (=).

ego

a = 6
exit = imp

(b)

Address assignment
The use of a / (slash) if immediately preceded by an expression sets the
current address equal to the value of that expression.

6-3

ego

300/

lac (56

begin -240+a/

lac (56

The expression must be defined at the time of assignment.
(c) Comma
If the expression to the left of a comma consists of a single, undefined symbol and
that symbol is not from the permanent symbol list, the assembler will set the value
of the symbol to the current address, thus defining that symbol.
ego

begin,

lac load

jmp begin

Variables
Any storage register which is reserved for data which may change during the program
is referred to as a variable. To indicate a variable, it is only necessary to include
the character $ anywhere within the first six characters of the variable name the first
time it is specified.

Pseudo Instructions
Pseudo instructions command the assembler to take certain action during processing of
the source language tape. They are transparent to the part of the assembler wh ich processes syllables for output and are disregarded after performing their control function.
The more important ones are described below.
(a)

Radix Control
The programmer can indicate the radix which the assembler should use when
interpreting digits.
Decimal - All numbers are interpreted as decimal numbers until the next
occurrence of the pseudo instruction 1I0ctal ll •
Octal - All numbers are interpreted as octal numbers until the next occurrence
of the pseudo instruction IIdecimal" .
When the assembler is initially read into core, the mode is octal.

(b)

Start
This pseudo instruction indicates the end of the symbolic source tape. It must be
followed by a carriage return. After the binary tape is read, the AC lights indicate
the last address used by the program. If Start is followed by a space and symbol ic
expression (inserted before the carriage return), the loader will jump to the address
equivalent of the symbol ic expression when the program has been read (load and
go).

6-4

(c)

Pause
Performs the same function as II start II except that the program halts on read in.
If Pause is accompanied by a symbol ic expression, the program may be started at
the address indicated by that expression by depressing CONTI NUE.

(d)

Variables
All variables which have appeared in the program up to this point but have not
had locations assigned to them will be stored sequentially starting at the address
indicated by the current address counter. Then processing of the program continues

Source Language Tapes
A source language tape can be produced off line using any 8-bit ASC II code equipment.
On-line source tapes can be prepared under program control with a greater flexibility for
error correction and modification using the Editor program.
For a complete description of the Assembler and its operation, refer to the PDP-7 Assembler
Manual, Digital 7-3-5.

DDT (DIGITAL DEBUGGING TAPE)
DDT is a debugging program for the PDP-7 computer. In both 4K and 8K computers, DDT
occupies the hi9hest 20008 registers of memory. Program modification and execution is from
the Teletype keyl;>oard and output is on the teleprinter or punched tape, as desired by the programmer. For example, to branch to a new location in the program it is only necessary to type
the symbolic location name on the keyboard followed by the character single quote('). The
same symbol followed by the character slash (/) causes the contents of that location to be typed.
Working corrections can be punched out on the spot in the form of loadable patch tapes, el iminating the necessity of creating new symbol ic tapes and reassembl ing each time an error is
found.
Breakpoints - One of the DDT's most useful features is the breakpoint. A simplified way of
thinking of a breakpoint is to think of hlt's being inserted in a program at critical points.
The breakpoint control characters ore as follows:
II

(double quote)

DDT inserts a breakpoint at the address specified before the I I . DDT will remove the instruction at the
break location and save it for future restoration. The
instruction at the break location is only executed
after the proceed is given. To proceed, execute (!).

6-5

{exclamation}

After a break occurs, this character causes DDT to
proceed with the user1s program. This proceed wi II
cause the instruction which was at the break location
to be executed and control to return to the user1s
program. It is possible to test a loop and break before
the last time around (ex. Nth time), by supplying a
number before the (~). The break wi II then occur
during the Nth cycle.

(single quote)

Go to the location specified before the I . This
character starts the program runn ing andwi II run until
it encounters the register which was specified as a
breakpoint.

As an example of breakpoint use, consider the program section

begin,

lac 0
add b
doc c

Suppose thi.s program is giving a wrong answer and you want to find where the error is in the
program. Break at "begin + 111; start the program running at "begin". Suppose a contains 15
and b contains 20:
You type:

BEGIN + 1"

You type:

BEGIN I

DDT types:

BEGIN + 1)

6-6

DDT types out the break location followed by a right paren, some spaces, and the current contents of the AC. At this point, the programmer is free to change registers or just examine them,
change the contents of the AC, or use any of DDT's other features.
For a complete description of DDT, refer to the DDT Program Description, Digital-7-4-S.

EDITOR
The Editor program reads sections of the symbolic source tape into memory where it is available
for exam ination and correction. Corrections are entered directly from the teleprinter keyboard.
The corrected text can then be punched out on a new tape. Text may also be entered and
punched for original tape preparation. Tape input and output may be either FlO-DEC or ASCII
codes, and the Editor will convert from one code to the other.
The information to be edited is stored in a text buffer, which occupies all of memory not taken
up by the Editor itself, and has a capacity for about 4,000 characters in a PDP-7 with 4096
words of memory, or about 16,000 characters in one with 8192 words.

Operating Modes
In order to distinguish between commands to itself and text to be entered into the buffer, the
Editor operates in one of two modes. In command mode, typed input is interpreted as directions
to the Editor to perform some operation. In text mode, all typed input is taken as text to be
inserted in or appended to the contents of the text buffer. To help the user keep track of the
mode, a visual indication is provided by the LINK light on the PDP-7 console. In command
mode, th is I ight is off; in text mode, it is on.
Listed below are five of the special functions which are part of the Editor.
Carriage Return (~ )

In both command and text modes, this is the signal for the
Editor to process the information just typed. In command
mode, the operation specified is to be performed. In text
mode, it means that the preceding line of text is to be placed
in the buffer.

Continuation ($ ~)

In text mode this fac i Iitates adding comments to successive
I ines or for end-of-I i ne correct ions. If a line of text is
terminated by this pair instead of a single carriage return,
the line will be entered as usual; then the line immediately
following it wi II be printed up to but not inc luding its
carriage return. Thus, the new I ine is I eft open for additions
for corrections.

Line Feed

(t )

This character has two meanings, depending on when it is
used. If it is struck after some information has been typed,
it causes that information to be deleted. Used thus in either
mode, it has the effect of erasing mistakes. When it has
6-7

processed the I ine feed, the Editor responds with a carriage
return. If, in command mode, line feed is the first character
typed on a line, the next line of text (line .+1) will be printed.
Rub Out (ro)

This key has three distinct functions. Typing ro in command
mode will cause the next line of text to be printed. The use
of ro for this purpose is preferred to that of I ine feed, since
it provides a neater printout.
Pressing ro in text mode will cause the last character of an
incomplete line of text to be deleted from the input buffer.
Continued striking of this key will cause successive characters.
to be deleted one by one, working from the end of the line
back to the beginning. In this way, a mistake can be corrected
without having to retype the whole line.
Example:

Instead of DAC PTEM, the following line was typed:
DAC CTE

To correct the line, ro is struck three times, erasing the last
three Ietters in success ion, E, T, and C. The correct text
is then typed, and the resulting Iine appears on the Teleprinter
as:
DAC CTEPTEM
It is stored in the text buffer, however, in correct form, as:
DAC PTEM
In text mode, the ro key has another function. Typed immediately after a carriage return, it signals the Editor to return
to command mode. If one deletes all the characters in an
incomplete Iine and then strikes ro one more time, the Editor
wi II also return to command mode. No keyboard response is
provided by the Editori but when it enters command mode,
the LI N K light, wh ich has been on whi Ie in text mode, goes
out.
Colon (:)

When this symbol is typed in command mode, the Editor wi II
print the decimal value of the argument that precedes it
followed by a carriage return. It is frequently used for determ in ing the number of Iines of text in the buffer.

6-8

Example:

or in determining the number of the current line:
32
For a complete description of the Editor and its operation, refer to the PDP-7 Editor Manual,
Digital 7-1-S.

FORTRAN
Based on the field proven FORTRAN used with the PDP-4, PDP-7 FORTRAN is written for
two different hardware configurations. One is for perforated tape systems and the other is
for a configuration which includes at least two logical tape units (either two magnetic
tape units or one dual magnetic DECtape unit). Both FORTRAN systems require an 8K
memory. Approximately 4000 (decimal) registers are available for stored program and data.
The principal subsections of the FORTRAN system are:
Compiler
Fortran Assemb Ier
Object Time System
Library
The compiler accepts input in the FORTRAN language and produces an output in an intermediate language acceptable to the assembler. The assembler accepts the compiler output
and produces a binary relocatable version of the program and a binary version of the linking
loader.
When the user is ready to execute a program, he loads the main program and any subprogram, followed by any built-in functions called from the library. Once the total program
is in memory, he loads the object time system and executes the program. The object time
system contains an interpreter for floating point arithmetic, an interpreter for format statements, routines such as fixed floating number conversions, and the I/O routines. The object
time system must be in memory when a FORTRAN program is executed.
FORTRAN has the following characteristics:
FIXED POINT CONSTANTS

1-6 decimal digits absolute value ~ 131,071 .

FLOATING POINT CONSTANTS
21 7 - 1 to min us 21 7 - 1 .

10 decimal digits precision.

Exponent range from plus

SUBSCRIPTS Any arithmetic expression representing an integer quantity: Variables in a
subscript may themselves be subscripted to any depth. N dimensional arrays are
perm itted.

6-9

STATEMENTS
Mixed expressions containing both fixed and floating point variables are
permitted. A maximum of 300 characters are allowed (statement numbers not counted).
STATEMENT NUMBERS

1 - 99999.

FUNCTIONS AND SUBROUTINES
Subroutines not contained in the FORTRAN library
may be compiled by the use of Function and Subroutine statements. Functions and
subroutines may have fixed or floating point values as defined by the programmer.
Users are required to insure consistent references.
INPUT AND OUTPUT DECtape (Digitalis Microtape system), magnetic tape, paper tape,
Teletype. Format may be specified by use of a FORMAT statement.
STATEMENTS AVAILABLE
Arithmetic statements, I/O statements with FORMAT, DO,
Dimension, Common, IF, GOTO, Assign, Continue, Call, Subroutine, Function,
Return.
TYPE DECLARATIONS
Variables may be declared as real, integer, and FORTRAN.
Variable names are 1-6 a Iphanumeric characters.
MIXED CODES

Symbolic instructions can be intermixed with FORTRAN statements.

VARIABLE PRECISION ARITHMETIC
Variable precision floating point arithmetic is used
with a choice of mantissa (25 or 36 bits) and exponent (8 or up to 99 bits).
ARRAYS

Arrays of up to 4 dimensions, either fixed or floating may be defined.

For a complete description of FORTRAN and its operation, refer to the PDP-7 FORTRAN
Manual, Digital 7-2-S.

BUS-PAK II
Bus~Pak II is a program assembly system designed for data processing operations.

By operating
on a character-by-character basis, its instructions are powerful, yet easy to learn and understand. Bus-Pak II offers programming features such as Editing, two modes of indexing and
complete input/output control. The Bus-Pak II programming system was developed so that
many of the manual record keeping and updating operations could easily be converted to
make use of a PDP-4 or PDP-7 computing system. Bus-Pak II users do not have to understand
the computer operation. Through the use of the pseudo-language, the PD P-7 is operated as
a business-oriented computer, performing all functions including the handl ing of peripheral
input/ourput equipment.

6-10

Modes of Operation
Bus-Pak II has two (2) modes of operation. A "Run ll mode which is used for normal
execution of the user's program and a "Single Instruction" mode for use in debugging
Bus-Pak II programs. The control of the mode of operation is by the AC switch zero on
the console. When AC switch zero is in the down position, Bus-Pak II operates in the
"Run" mode. When AC switch zero is in the up position, Bus-Pak II operates in the
"Single Instruction ll mode.
In the Single Instruction mode of operation, Bus-Pak II halts after the execution of each
Bus-Pak II instruction and indicates in the AC lights on the console the address of the next
Bus-Pak II instruction to be executed. When a II GOTO" instruction is executed, Bus-Pak II
wi II not stop unti I the instruction at the location indicated by the GOTO instruction is
executed.
Addressing
Both instructions and data essential for processing are contained in core storage. Each core
storage location is completely addressable. Bus-Pak II instructions are variable length
type instructions in that not all the instructions take up the same number of core storage
locations.
Data fields being processed are also of the variable length type. A data field length is
determined by the IINIt (number of characters) field in a specific instruction. All data is
processed from left to right, for as many characters specified by the instruction being
executed. Both instructions and data may be interm ixed as long as the data does not interfere with the normal flow of the program.

Input/Output Storage Assignments
No spec ific input/output areas have been assigned to any input/output device in the Bus-Pak II
system. The assignment of these areas has been left entirely up to the programmer. In th is way,
more efficient and less core consuming programs may be written. Care, though, must be taken
so that an area defined for a specific input/output device is large enough for the particular
device.

Editing
In the printing of reports, it is sometimes necessary to punctuate numeric data by dollar signs,
commas, and decimal points. This punctuation would take many instructions of testing and
shifting the data and inserting the correct punctuation characters. The editing feature provides
this punctuation of data automatically, based on a control word specified by the user. Floating dollar sign and asterisk protection is also available for check writing. Multiple sequential
data fields may be edited in one editing operation.

6-11

Indexing
Indexing is a means of address modification without disturbing the original data address in an
instruction. Bus-Pak II makes available two modes of indexing, single indexing and double
indexing. An effective address is calculated for every "TO," "FROM," and II BY II address
field specified by an instruction. In single indexing, the contents of the index register
specified by an address field are added to the data address, and this new effective address is
used in the execution of the instruction. In double indexing, the contents of the index register
specified by the double index register are also added tothe data address and this new address
used in the execution of the instruction.

Indirect Addressing
When indirect addressing is spec ified, the address is interpreted as the address of the register
which contains the address of the data to be processed. Multiple levels of indirect addressing are available, and each level of a IITO" or II FROM" address field may use single and/or
double indexing.

Double Precision Accumulators
All arithmetic operations on numeric data must be done by the use of one of the fifteen (15)
double precision accumulators available in Bus-Pak II. Each accumulator is capable of
containing a magnitude not exceeding ±3 4359738367 (±2 35 _1). An overflow
indicator is associated with each of the 15 available accumulators. The signs of the accumulators are computed algebraically depending on the signs of the data being calculated.
Arithmetic (add, subtract, multiply, divide) can be performed directly to memory. See
ADDMEM instruction example.
Program Counters
j

Fifteen (15) program counters are available forcontrollingmultiple execution of a particular
sequence of instructions.

Sense Switches
Fifteen (15) sense switches are avai lable through the use of the AC switches on the console
for manual control of program execution.

Program Switches
Fifteen (15) program switches are available for internal control of program execution.

6-12

Bus-Pak Example 1
MOVE CHARACTERS

op-code

mnemonic

variable operands

17411

FROM

The "N" consecutive characters starting address "FROM" are moved from left to right to the
II

Nil consecutive character positions starting address liTO. II

NOTE:

1. The original IIN" consecutive characters with the starting
address liTO" are replaced by the II Nil consecutive characters
with the starting address IIFROM. II The II N" consecutive
characters with the starting address IIFROM" are left undisturbed.

EXAMPLE:
MV

CORE STORAGE

before

B C

after

B C

CORE STORAGE

ADDRESSES

CONTENTS

473
F

-~'-----~--

The MOVE instruction is typical of the generalized data manipulating instructions contained
in Bus-Pak II.

6-13

Bus-Pak Example 2
ADD TO MEMORY

ADDMEM

op-code

mnemonic

variable operands

17523

ADDMEM

The contents of accumulator "AC" are algebraically added to the "N" consecutive
characters with the starting address liTO. II The results are placed into the II Nil consecutive
character positions with the starting address liTO. II
NOTE:

1. The contents of accumulator "AC" are left undisturbed.
2.

The sign over the units position of the liNn consecutive characters

with the starting address IITO" is taken into consideration.
3. The original "N" consecutive characters with the starting address
liTO" are lost.
4.

If the result of the addition produced a value whose magnitude

exceeded the capacity of the accumulator, the associated overflow
indicator will be set.

The result itself is worthless.

5. The sign of the result is placed over the units position of the "N"
consecutive characters with the starting address liTO. II
EXAMPLE:

ADDMEM
CONTENTS OF
-

CORE STORAGE

before
after

9
r--

CORE STORAGE

ADDRESSES

----_.

ONTENTS OF

before

+35

PECIFIED

after

+35

CCUMULATOR

6-14

CHAPTER 7
INPUT/OUTPUT EQUIPMENT

This chapter contains descriptions of standard DEC input/output equipment. Included with
each description are the iot instructions used with the device when it is connected to the PDP-7.
Peripheral equipment may either be asynchronous with no timed transfer rates or synchronous
with a timed transfer rate. Devices such as the CRT displays, printer-keyboard, and the
line printer may be operated at any speed up to a maximum without loss of efficiency. These
asynchronous devi ces are kept on and ready to accept data; they do not turn themselves off
between transfers. Devices such as magnetic tape, DECtape, the Serial Drum, and card
equipment are timed-transfer devices and must operate at or very near their maximum speeds
to be efficient.
Some of the timed-transfer devices can operate independently of the central processor once
they have been set in operation by transferring a continuous block of data words through the
PDP-7 Data Interrupt. Once the program has suppl ied information about the location and
size of the block of data to be transferred, the device itself takes over the work of actually
performing the transfer.

MECHANICAL CONFIGURATION
The basic PDP-7 is housed in two DEC standard (22-1/4 11 x 27-1/16" X 69-1/8") metal
cabinets. Equipment is mounted within the bays (FRONT) and on the rear doors (REAR) in
a layout shown in Fi gure 7 -1. Doors on the front of Bay 1 provide access to the memory,
central processor, and EAE wiring panels. The punch is housed in a pull-out drawer.
Short doors beneath the removable table provide access to the I/O Control wiring panel.
Power suppl ies for the central processor and memory (up to 32K) are mounted on the rear
door of Bay 1. Additional bays are easi Iy added to provide space for I/O options and
other equipment.
I/O BUFFERING
Separate parallel buffers are provided on each input/output device attached to the basic
PDP-7. The high-speed paper tape reader control contains an 18-bit buffer and binary word
assembler. The high-speed paper tape punch, the teleprinter, and the teleprinter keyboard
each contain separate 8-bit buffers.

7-1

BAY t

INDICATORS

FRONT

BAY 2

MARGINAL
CHECK

REAR

BAY i

738
MARGI NAL CHK
POWER SUPPLY

728
POWER
SUPPLY

4/BK
MEMORY
PUNCH

BLANK
READER

MEMORY
POWER
SUPPLY

CONSOLE

778

TABLE

POWER
SUPPLY

READER
PUNCH
LOGIC

BLANK

EAE
OPTION

CONVENIENCE
OUTLET

778
POWER
SUPPLY

1/0

CABLES

Figure 7-1

778
POWER
SUPPLY

BLANK

Cabinet Layout

Separate parallel buffers are also incorporated as part of DEC Standard I/O peripheral
equipment. Information is transferred between the accumulator and a device buffer during
the execution time of a single cycle iot instruction. Because the maximum time the
accumulator is tied to anyone external buffer is 1 .75 microseconds, many standard I/O
devices can operate simultaneously under control of the PDP-7.
Figure 7-2 shows the data path between device buffers and the AC through the Information
Collector or Information Distributor.

7-2

I<EYBOARD
BUFFER
READER
BUFFER

AID

••

AID
BUFFER

•

18 BITS

TELEPRINTER
BUFFER

I
'--------'

••
•

BUFFER

CENTRAL
PROCESSOR

MBa
MEMORY

DEC TAPE*'
.

1.75,us

PUNCH
BUFFER

DEC DPE.

DATA CHANNEL

•
••

* INCLUDED WITH OPTION

Figure 7-2

Input/Output Flow

TELETYPE MODEL 33 KSR
(Standard Equipment with the PDP-7)
The Teletype Model 33 KSR (keyboard-send-receive) can be used to type in or print out
information at a rate of up to ten characters per second. Signals transferred between the
33 KSR and the keyboard printer control logic are standard seria I, 11 un it code Teletype
signals. The signals consist of marks and spaces which correspond to idle and bias current
in the Teletype and zeros and ones in the control and computer. The start mark and subsequent eight character bits are one unit of time duration and are followed by a two unit
stop mark.
Each of the (64 type) characters and 32 control characters are represented by an 8-bit
standard ASCII code. The Teletype eight-level code is listed in the Appendix. The teleprinter input and output functions are logically separate, and the programmer may think
of the printer and keyboard as individual devices.
Keyboard
The keyboard control contains an 8-bit buffer (LUI) which assembles and holds the code for
the last character struck on the keyboard. The keyboard flag becomes a 1 to signify that a
character has been assembled and is ready for transfer to the accumulator. This flag is connected to the computer program interrupt and input/output skip facility and may be cleared
by command. Instructions for use in control I ing the keyboard are:

7-3

ksf

700301

Skip if the keyboard flag is set to 1. If
the flag is 0, the next instruction is
executed. If it is 1, the next instruction
is skipped. The flag is set only when a
character has been completely assembled
by the buffer.

krb

700312

Read the keyboard buffer. The contents
of buffer are placed in bits 13-17 of the
AC and the keyboard flag is cleared.

Teleprinter
The teleprinter control contains an 8-bit buffer (LUO) which receives a character to be
printed from AC bits 10 through 17. The LU 0 receives the 8-bit code from the AC in
parallel and transmits it to the teleprinter serially. When the last bit has been transmitted,
the teleprinter flag is set to 1. This flag is connected to the computer program interrupt
and input/output skip facil ity. It is cleared by programmed command. The instructions
for printing are:
tsf

700401

Skip if the teleprinter flag is set.

tis

700406

Load printer buffer and select. The
contents of AC _ are placed in the
10 17
buffer and printed. The flag is cleared
before transm iss ion takes place and is
set when the character has been printed.

PERFORATED TAPE READER TYPE 444
(Standard Equipment with the PDP-7)
The tape reader is a timed-transfer device wh ich senses the holes punched in 5, 7, or
8-~hannel paper (or Mylar-base) tape. The standard input medium is 8-channel tape.
The max imum read ing rate is 300 characters (I ines) per second. A power switch is
provided on the reader. This switch is usually left on, however, as the reader power
is removed when the computer is turned off.
Operation of the tape reader is controlled entirely by the program. When the reader is
selected, the brake is released and the clutch engages the drive capstan to move the tape
past the photocells which sense the holes punched in the tape. For each hole present in
a given line of tape, a corresponding bit of the reader buffer is set to 1 •
Information can be read from tape and assembled in the reader buffer in one of two modes:

7-4

ALPHANUMERIC MODE: Each select instruction causes one line of tape, consisting of eight
bits, to be read and placed in the buffer. Blank tape is ignored. The absence of a
feed hole causes the character punched in that Iine to be ignored. See Figure 7-3.
BINARY MODE: In the binary mode, select the instruction causes three lines of tape to be
read. The first six b its of each Iine are assembl ed in the buffer, thus three lines
form a single l8-bit word. The seventh bit is ignored. However, a character is
not read unless the eighth bit is punched. See Figure 7-4.

READER BU FFER

• 17

BUFFER BIT POSITION

DIRECTION OF TAPE

t 1 12

13 14

16 17

o 0

0
0
0

-Figure 7-3 Alphanumeric Perforated Tape Format
and Reader Buffer Bit Assignment

PAPER TAPE READER INSTRUCTIONS
rsa

700104

Select reader in alphanumeric mode. One
8-bit character is read and placed in the
reader buffer. The reader flag is cleared
before the character is read. When transmission is complete, the flag is set.

rsb

700144

Select reader in binary mode. Three 6-bit
characters are read and assembled in the
reader buffer. The flag is immediately
cleared and later set when character
assembly is completed.

7-5

rsf

700101

Skip if reader flag is set.

rcf

700102

C lear reader flag then inclusively OR reader
buffer into AC. C(RBj) V C(ACj) =>C(A CO.

rrb

700112

Clear reader flag. Clear AC and then
transfer contents of reader buffer to AC.
C(RB) = > C(AC).

READER BUFFER

•

LINE 3

LINE 2

LINE 1

LINE 1
LINE 2
LINE 3
LINE
DIRECTION OF TAPE

OX
Ox
OX
OX

000

o 0 0

BIT 5

BIT II

BIT 17

Figure 7-4 Binary Perforated Tape Format
and Reader Buffer Bit Assignment

PERFORATED TAPE PUNCH TYPE 75
(Standard Equipment with the PDP-7)
The Tape Punch is a timed-transfer device capable of punching 5, 7, or 8 channel tape
at a maximum rate of 63.3 characters per second. The standard input medium is 8 channel
tape.
Operation of the Tape Punch is controlled either by the program or by the computer operator.
The operator may punch blank tape (feed hole only punched) by depressing the punch feed
button on the console or he may force on the punch power by turning on the console punch
switch . Normally, the punch is left completely under program control. An instruction
to punch when the punch is turned off causes the punch to be turned on and the actual

7-6

punching takes place approximately one second later when the punch motor is up to speed.
Note that the central processor is never delayed by th is instruction nor any other lOT
instruction. Subsequent punching follows at normal punch speed. The motor remains on
for five seconds after the last punch command is given.
When the punch is selected, the contents of AC 1.0-17 are sent to the punch buffer and then
subsequently placed on tape. If a bit in the AC IS a I, the corresponding bit in the buffer
is set. Since the punch buffer is automatically cleared after punching a character, it is
impossible to OR into it. Information is hand led by the punch logic in one of two modes:
ALPHANUMERIC MODE: Each select instruction causes one line of tape, consisting of
eight bits, to be punched. A hole is punched in a tape channel if the corresponding punch buffer bit is a one. A feed hole is a Iways punched.
BINARY MODE: Each select instruction causes one line of tape, consisting of eight bits,
to be punched. Holes are punched corresponding to bits 12-17 of the punch
buffer. Bit" is never punched and bit 10 is a Iways punched. Th is forces the
standard format for binary information on tape.

TAPE PUNCH INSTRUCTIONS
psa

700204

Punch a line of tape in alphanumeric mode.
The punch flag is immediately cleared and
then set when punching is complete.

psb

700244

Punch a line of tape in binary mode. The
punch flag is immediately cleared and then
set when punching is complete.

psf

700201

Skip the following instruction if the punch
flag is set.

pcf

700202

Clear the punch flag.

The following instruction will cause a line of blank tape (except for feed hole) to be punched.
The accumulator is also cleared.
psa + 10

700214

Clear AC and punch.

The following instruction as used on the PDP-4 is also available, but is generally replaced
with the more direct psa.
pis

700206

Same as psa.

7-7

DECTAPE
DECtape (Digitalis microtape system) is a bidirectional magnetic tape system which uses a
ten-track recording head to read and write five duplexed channels. The DECtape system
incorporates the Type 555 DECtape Dual Transport and the Type 550 DECtape Control.

Dual DECtape Transport Type 555
The Type 555 Transport consists of two logically independent bidirectional tape drives
capable of handling 260 foot reels of 3/4 inch, 1.0 mil Mylar tape. The bits are recorded
at a density of 375 (±60) bits per track inch. Since the tape moves at a speed of 80 inches
per second, the effective information transfer rate is 90,000 bits per second, or one 18-bit
word every 200 microseconds. Traverse time for a reel of tape is approximately 40 seconds.
The 3-1/2 inch reels are loaded simply by pressing onto the hub, bringing the loose end of
the tape across the tape head, attaching it to the take up reel, and spinning a few times.
Individual controls on the transport enable the user to manipulate the tape i.n either
direction manually. The units can be "dialed" into a particular selection address.
There is no capstan or pinch-roller arrangement on the transport, and movement of the tape
is accompl ished by increasing the voltage (and thereby the torque) on one motor, whi Ie
decreasing it on the other. Braking is accomplished by a torque pulse applied to the trailing motor. Start and stop time average O. 15-0.2 seconds and turn around takes approximately 0.3 seconds.
Recording Technique
The DEC tape system uses the Manchester type polarity sensed (or phase modulated) recording technique. This differs from other standard types of tape recording where, for example,
a flux reversal might be placed on the tape every time a one is desired. In the polarity
sensed scheme a flux reversal of a particular direction indicates a zero while a flux reversal
in the opposite direction indicates a one. A timing track, recorded separately in quadrature
phase, is used to. strobe the data tracks. Thus, the polarity of the signal at strobe time indiCates the presence of a zero or one. Using the timing track on the tape as the strobe a Iso
negates the problems caused by variations in the speed of the tape. See Figure 7-5.
With this type of recording only the polarity, not the amplitude of the signal, need be
considered, thus removing some of the signal to noise problems and allowing the use of read
amplifiers with high uncontrolled gain. This recording also allows the changing of individual
bits on the tape without changing the adjacent bits.
Reliability is further increased by redundantly recording all five of the information tracks
on the tape. Figure 7-5 shows the placement of this track. This is accomplished by wiring
the two heads for each information track in series. On reading, the analog sum of the two
heads is used to detect the correct val ue of the bit. Therefore, a b it cannot be misread
until the noise on the tape is sufficient to change the polarity of the sum of the signals being
read. Noise which reduces the amplitude would have no effect.

7-8

TIMING TRACK 1
MARK TRACK 1
INFORMATION TRACK 1
INFORMATION TRACK 2
INFORMATION TRACK 3
INFORMATION TRACK lA

3/4

(Same as IT 1)

INFORMATION' TRACK 2A
(Sameas IT2)
DANl
KS

INFORMATION TRACK 3A

(Same as IT 3)

MARK TRACK lA
(SameasMTl)

T~~!~~ni~ACK lA

.-0I
j,
Track Allocation Showing Redundantly Paired Tracks
TIMING TRACK
MARK TRACK

INFOR_{1
MATION 2
TRACKS
3

r--- lines----l
6

Basic Six Line Tape Unit

MARK TRACK
DATA 1

REDUNDANT

DATA 2

SH~N

TRACKS

DATA 3

Control and Duta Word Assignments
Forward di,r~ctionof tilpe motion

- - - - - - - - - O N E BLOCK 26410 WORD LOCATIONS----------11

1
II

R~~~~~E!BlOCltJ~!~5E
-::

'DENTIFIES

II,

1------25610 DATA WORD LOCATIONS

RE~~~~EREVER:fE~~~.SE

PRE

CHEC~r~~~SE

R~~g~EIBlOCK RJ~l~5E

,-~, <Y '~ :" ' ; ' : ' ~;',:' ~;'<ii;;.¥;'f"~¥c~7;:~i~~~

~ J~ t t tt' t

:~:~D;~:BR~~E PROTECT'ON

D~' o,t, 0,,, D~' D~'l2L BLOCK NUMBER FOR

IN REV. CIR. A.ND SYMMETRY

LOADS MMIOB WITH -0, DURING

PROTE:~:E;::E D,~E;:~~:
Of MARK TRACK ERRORS

PROVIDES PROGRAMMEO ERROR DETECTION

WRITING, FOR REV CHECK SUM

AND END OF BLOCK DETECTION IF READING

PROVIDES SYMMETRICAL ERROR

IDENTifiES fiNAL OATA WORD, AND REQUESTS

DETECTION IN 80TH DIRECTIONS

CHECK SUM WITH AUTOMATIC CHECK SUM CONTROL
REQUESTS LOAOING OF CHECK SUM ANO INDICATES
BLOCK END, IF WRITING WITH PROGRAMMED CONTROL

FIRST DATA W O R O - - - - - - - - - - '

SECOND DATA WORO---------'

I.--J..._.L...-_ _ _ _ _ _ _ _ _

ADDITIONAL DATA WORDS

Cod.'unctionahat~.pplyonl)'inthedw.ellonindk:.'ed

SUCCESSIVE DATA WORDS _ _ _ _ _ _ _ _----'._...L....--I

NOTE: END MARKS, WHICH IDENTIFY THE PHYSICAL ENDS OF THE
TAPE, ARE THE ONLY MARKS NOT SHOWN.

DECtape Mark Track Format (Assumes 256

Figure 7-5

Data Words Per Block)

DECtape Recording

7-9

DECtape Control Type 550
The DECtape Control Type 550 operates up to four Type 555 Dual Tape Transports (8 drives)
transferring binary data between tape and computer. By using the automatic Mark track
decoding of the control and the program interrupt facility of the computer to signal the
occurrence of data words, errors, or block ends, computation in the main program can
continue during tape operations. Information can be transferred with programmed checking
by using the subroutines which are provided with the equipment. Format control tracks,
tailored to individual use by establishing any desired block lengths, can also be written
with the subroutines provided. The Control allows reading and writing of any number of
words at one mode command irrespective of the block length. Assembly of lines on the
tape into 18 bit computer words in either direction is performed automatically by the
Control. Status bits avai lable to the program specify the current condition of the Control
and error indications.

DECtape Programming
Three main groups of Programs are provided with the DECtape Systems: a basic set of subroutines for searching, reading and writing; a set of maintenance and diagnostic routines
(DECTOG); and a program for easy storage and retrieval of information via the computer
console (DECTRIEVE).
The basic PDP-7 subroutines for reading, writing, or searching allow the user to specify the
total number of words to be transferred irrespective of the block format on the tape. Searching can occur in either direction, and the search routine can be used independently to
position the tape or is used automatically by the read and write subroutines. Transfer of
data in this program, however, will occur only with the tape moving in the forward
direction. If the number of words specified is not a multiple of the aggregate block lengths,
the final block is filled with zeroes which are ignored upon reading. -The subroutines use
the program interrupt during searching but wi II pre-empt the computer during the actual
transfer of data. One auto-index register is used and must be defined by the main program,
and "DISMIS" must be defined as a jump to the routine which dismisses the interrupt. When
the transfer is completed, a programmed status register is set and a return is made to the
main program with the tape stopped. Errors are detected, coded numerically, saved in
status bits and indicated by a predesignated error return. The programmer can decode the
error and proceed in any manner desired. Approximately 4008 words of storage are used.
A sample sequence of instructions for transferring core locations 1000 through 1777 beginning
with block 100 on tape unit 1 would appear as follows:
jms
law
jmp
10000
law
law

jar MMRDS for Reading
jar LAC (100) Block Number

MMWRS
100
ERR

jError Return
jUnit Se lection
jar 1000, Core Starting Address
jar 1777, Core Final Address

1000
1777

7-10

DECTOG for the PDP-7 is a collection of short programs which allow the user to perform
various DECtape functions using the Accumulator Switches on the console. Programs
available include those which create the Mark track and block format, read or write designated portions of the tape, write specified patterns on designated blocks in either direction,
sum check designated blocks in either direction, Il roc k" the tape in various modes for
specified times or distances, and an exerciser which writes and sum checks designated areas
of the tape in both directions with changing patterns. Errors are completely analyzed and
typed out together with the number of the block causing the error and the status of the
DECtape system at the time of the error. Detailed descriptions of the various sub-programs
are available. For a more complete description of DECTOG refer to Digital 7-20-1/0.
DECTRIEVE for the PDP-7 allows the user to save or retrieve data using the Accumulator
Switches on the console. To store data the user specifies the unit, block number and
starting and ending core locations. The data wi II be saved together with appropriate
control information and sum checked. To retrieve the data only the unit and starting block
need be specified. The control information is used to insure the correct starting block, the
starting core location, and the amount of data to be read. Messages typed after reading or
writing indicate the operation, tape blocks used, and the total check sum for verification
purposes. All errors are fully analyzed as in DECTOG. Tapes are available for 4K or 8K
memories and for the first or second DECtape controls. For a more complete description of
DECTRIEVE refer to Digital 7-21-1/0.

DECtape INSTRUCTION LIST
MNEMONIC
SYMBOL

OCTAL
CODE

mmrd

707512

READ. Clears (0 or AC and transfers one word
from MMIOB to bits 0-17 of AC. **

mmwr

707504

WRITE. Transfers one word from bits 0-17 of AC
to MMIOB. **

mmse

707644

SELECT.' Connects the unit designated in bits
2-5 of AC to the DECtape Control. **

mmlc

707604

LOAD CONTROL. Sets the DECtape Control to
the proper mode and direction from bits 12-17 of
the AC, as follows: **

FUNCTION

**mmse and mmlc clear the Error Flag and error status bits (EOT, TIMING MTE, UNAB) and
mmse, mmlc, mmrd, and mmwr clear the Data and Block End Flags.
7-11

DECtape INSTRUCTION LIST (continued)
MNEMONIC
SYMBOL

OCTAL
CODE

FUNCTION

Bit 12 = Go (Go = Stop)
Bit 13 = Reverse
Bit 14 = In-motion Read
Bits 15-17 = Mode:
0= Move
1 = Search
2 =-Read
3 = Write
4 =Spare
5 = Read through block ends
6 = Write through block ends
7 = Write tim ing and'mark track
i. e. 42 = Read Forward
62 = Read Reverse
43 = Write Forward
41 = Search Forward
61 = Search Reverse
mmrs

707612

READ STATUS. Clears the 10 or AC and transfers
the DECtape status conditions into bits 0-8 of the
AC as follows:
Bit 0 = Data Flag
Bit 1 = Block End Flag
Bit 2 = Error Flag
Bit 3 = Erid of Tape
Bit 4 = Timing Error
Bit 5 = Reverse
Bit6=Go
Bit 7 = Mark Track Error
Bit 8 = Tape Unable

mmdf

707501

Skip on DECtape Data Flag. In Search Mode:
Block mark number should be unloaded via mmrd
instruction. In Read Mode: Data or Reverse
Check Sum should be unloaded via mmrd instruction. In Write Mode: Data should be loaded via
mmwr instruction.

7-12

DECtape INSTRUCT ION L1ST (continued)
MNEMONIC
SYMBOL

OCTAL
CODE

mmbf

707601

Skip on DECtape Block End Flag. In Read Mode:
Unload forward Check Sum via mmrd instruction.
In Write Mode: Load calculated forward Check
Sum via mmwr instruction.

mmef

707541

Skip on DECtape Error Flag. Timing Error, Mark
Track Error, End Tape, or Tape Unable Condition
has occurred. Use mmrs instruction to detect
specific error.

FUNCTION

AUTOMATIC MAGNETIC TAPE CONTROL TYPE 57A
The Automati c Magneti c Tape Control transfers information between the PDP-7 and up to
eight magnetic tape transports, using the data interrupt control and a data channel
supplied with the Type 57A. A number of different tape unit configurations may be
attached to the tape control, using one of three interfaces as follows:
Interface

Units Controlled

Densities Available

Type 520

DEC Type 50

200 bpi

Type 521

DEC Type 570

200 bpi, 556 bpi I 800 bpi

Type 522

IBM Model 72911, IV
IBM Model 7330
IBM Model 729V, VI

200 bpi, 556 bpi
200 bpi, 556 bpi
200 bpi, 556 bpi, 800 bpi

Tape format is standard and IBM-compatible, in odd or even parity modes.
The following functions controlled by various combinations of iot (in-out transfer) command
are all possible.
Write
Write End of Fi Ie
Write Blank Tape
Read
Read Compare
Space Forward
Space Backward
Rewind

7-13

Rewind/Unload
Gather Write
Scatter Read
Write Continuous
Read Continuous
Read Compare/Read
Read/Read Compare
Tape transport motion is governed by one of two control modes: Normal, in which tape
motion starts upon command and stops automatically at the end of the record; and Continuous,
in which tape motion starts on command and continues unti I stopped by the program when
synchronizing flags or status conditions appear.
The tape control contains the following registers:
DATA ACCUMULATOR (DA): 18-bits. Characters read from tape are assembled in the DA
and are taken, one 6-bit character at a time, from the DA to be written on'tape.
DATA BUFFER (DB): 18-bits. A secondary buffer between the DA and the MB in the
PDP-7. Under the data interrupt control, information is transferred between the MB and
the DB.
COMMAND REGISTER (CR): 3-bits. Contains the tape operation to be performed, as
specified by C(AC 9 _ 1 1).
UN IT REGISTER (UR): 3-bits. Contains the number (0-7) of the tape unit addressed for
the current operation, as spec i fi ed by C (AC 15-17) .
CURRENT ADDRESS REGISTER (CA): 13-bits. Contains the address of the memory cell
involved in the next data transfer. The initial contents of the CA are specified by bits
5-17 of the AC.
WORD COUNT REGISTER (WC): 13-bits. Contains the 2 1s complement of the number of
words involved in the transfer. The C(WC) are incremented by one after each word
transfer. The initial contents of the WC are specified by AC _ .
5 17
Tape operations, modes, and unit numbers are specified by the contents of bits 7-17 of the
AC. Tape control iot instructions transfer this information to the proper registers in the
control. A set of mnemonics has been defined to place any desired combination of
specifications in the AC by means of the law instruction. Data transfers are executed
through the Data Interrupt, thereby permitting simultaneous computation and data transfer.

7-14

The iot instructions used to perform these operations are briefly described below. For
detailed instructions on using the Type 57A Control, along with programming examples,
refer to Digitalis publication F-13(57A).
MNEMONIC
SYMBOL

OCTAL
CODE

mscr

707001

Skip if the tape control is ready. Th is
senses the tape control flag, which is set
when an operation has been completed and
the contro I is ready to perform another task.
Th is flag is connected to the program interrupt.

msur

707101

Skip if the tape unit is ready. Th is senses
the tape unit flag, wh ich is set when the
specified unit is ready for another operation.
Th is flag is connected to the PIC.

mccw

707401

Clear CA and WC.

mica

707405

Clear CA and WC, and transfer C(A C 5-17)
to the CA. Loads the CA.

mlwc

707402

Load WC. Transfers C(AC _ ) to the WC.
5 17

mrca

707414

Transfer the C(CA) to AC _ .
5 17

mdcc

707042

Disable TCR and clear CR. Clear WCO and
EOR flags (see below).

mctu

707006

Disable TCR, clear CR, and WCO and EOR
flags. Transmit unit, parity, and density
to tape control.

mtcs

707106

Transm it tape command and start. Th is
initiates the transfer.

mncm

707152

End continuous mode. Clears the AC; the
operation term inates at the end of the cu rrent
record.

mrrc

707204

Switch mode from read to read/ compare.
A IIows mode switch ing during the operation.

mrcr

707244

Switch from read/compare to read.

FUNCTION

7-15

The following commands deal with the two tape flags which determine when a transfer is complete. The WCO flag {word count overflow} is set when the WC becomes 0 after incrementing.
The end of record {EOR} flag is set when the EOR mark is sensed. Both flags are connected to
the PIC.

MNEMONIC
SYMBOL

OCTAL
CODE

msef

707301

Skip if EOR flag is set.

mdef

707302

Disable EOR flag. Th is disconnects it from
the program interrupt

mcef

707322

Clear EOR flag.

meef

707242

Enable EOR flag.
PIC.

Th is connects it to the

mief

707362

Initia Iize EOR flag.
the flag.

Clears and enables

mswf

707201

Skip if WCO flag is set.

mdvl

707202

Disable WCO flag.

mcwf

707222

Clear WCO flag.

mewf

707242

Enable WCO flag.

miwf

707262

Initialize WCO flag.

FUNCTION

There are \I status indicators associated with the Type 57A Tape Control.
The states
of all indicators may be observed by placing their contents into the AC. This is done
by an instruction sim ilar to iors, but applying only to the tape control. The instruction
is given below; the AC bit assignment is on the following page.
mtrs

707314

Read tape status

7-16

Indication is bit =1

AC bit

Data request late
Tape parity error

Read /compare error

End-of-file flag is set

Write lock ring is our

Tape is at load point

Tape is at end point

(Type 520) Tape is near end point
(Type 521 and 522) Last operation was writing

(Type 520) Tape is near load point
(Type 521) B Control in use with multiplexed transport
(T ype 522) Write echo check OK

Transport is rewinding

Missed a character

MAGNETIC TAPE TRANSPORT TYPE 570
The Type 570 Tape Transport may be connected to the PDP-7 using the Type 57A Tape
Control and the Type 521 Interface. It operates at speeds of 75 or 112.5 inches per second,
and densities of either 200, 556, or 800 characters (bits) per inch.
The Type 570 includes a multiplexing interface that permits time-shared use of the transport
by two tape controls connected to the same or different computers. This facilitates the pooling of tape units and allows two computers to exchange information via magnetic tape.
Programming is described in the section on the Type 57A Tape Control.

MAGNETIC TAPE TRANSPORT TYPE 50
The Type 50 tape unit may be connected to the Type 57A Control using the Type 520 interface. It operates at a speed of 75 inches per second and records information in low density
(200 characters per inch). Standard 7-channel, IBM-compatible tape format is used.

7-17

SERIAL DRUM TYPE 24
The serial drum system provides auxiliary data storage for the PDP-7 in any of three capacities:
32,768 words, 65,536 words, 131,072 words. Each word consists of 18 information bits and
a parity bit (generated by the drum system control; the parity bit is not transferred to core
memory).
Information is transferred between core memory and the drum in 256-word blocks. Each block
is stored on one sector of the drum. Two sectors are interleaved to one drum track; depending
on the drum size, there are 64, 128, or 256 tracks. From the programmer's point of view, the
track may be ignored; the logical storage unit is the sector. Transfers are effected through
the data interrupt control with the drum system providing the data channel.
Two iot instructions are required to initiate the transfer of a block of data. The first iot
specifies the memory location of the first word of the block and determines the direction of
the transfer; that is, drum to core or core to drum. The second iot instruction specifies the
drum sector address and initiates the transfer, which then proceeds under data interrupt control. The drum transfer flag is set to 1 when a block transfer is successfully completed. The
flag is connected to the program interrupt.
Four registers are used with the drum: (See Figure 7-6)
DRUM CORE lOCA"IION COUNTER (DCl) 16 bits. The DCl contains the core memory location of the next cell into or out of which a word is to be transferred. When
a word transfer is complete, the C(DCl) are incremented by 1 .
DRUM TRAC K ADDRESS REGISTER (DTR) 9 bits. The DTR contains the address of the
sector currently involved in a block transfer. At the completion of a successful transfnr, the C (DTR) are incremented by 1 .
DRUM F! NAl BUFFER (DFB) 18 bits. This is a secondary buffer between the memory
buffer an(J the drum serial buffer (see below). In writing, a word taken from the MB
is placed in the DFB to await transfer to the drum. In reading, the word assembled
in the seriol buffer is placed in the DFB. The next data interrupt takes it to the MB
and puts it in core.
DRUM SERIAL BUFFER (DSB) 18 bits. On reading, a word is read serially and assembled
in the DSB. On writing, a word in the DSB is written serially around the drum track.
In addition to the drum transfer flag, an error flag is used with the drum system. It may be
sensed by a skip instruction and should be checked at the completion of each block transfer.
The error flag indicates one of two conditions:
1. A parity error has been detected after reading from drum to core.
2. The data interrupt request signal from the drum was not answered within the wordtransfer period.

7-18

Because the DCl and DTR are automatically incremented {the DCl after each word transfer and
the DTR after each successful block transfer}, contiguous blocks of core may be written on
successive sectors of the drum, and conversely. The contents of one core load {4096 words}
may be transferred in either direction and would occupy eight successive tracks {16 successive
sectors} on the drum.
The iot instructions added with the drum system are:

MNEMONIC
SYMBOL

OCTAL
CODE

drlr

706006

load counter and read. Places the contents of
bits 2-17 of the AC in the DCl and prepares
the drum system for reading a block into core
memory.

drlw

706046

load counter and write. loads the DCl as above
and prepares the drum system for writing a block
from memory.

drss

706106

load sector and select. Places the contents of
AC9-17 in the DTR, clears both drum flags, and
initiates the block transfer {read or write, as
spec ified by the load counter instruction}.

drcs

706204

Continue select. Clears the flags and initiates
a transfer as spec i fi ed by the contents of the
DCl and DTR.

drsf

706101

Skip if drum transfer flag is set. This flag is
set when a block transfer is completed.

drsn

706201

Skip if drum error flag is not set.

drcf

706102

Clear both drum flags.

FUNCTION

For a complete description of drum timing, refer to the Digital publication, F-03{24A}.

7-19

Data to be written on the drum (18 bits)
MEMORY
BUFFER
REGISTER

Data read from the drum (t8 bits)

lOT Command
l--,-pu_ls_e_s_(_5_)_ _.... ~~e~~n;~giC

DRUM FINAL
BUFFER
(DFB)

Bit a
READ/WRITE I4~S_t_or_t_B_i_t- - - - I

DRUM SERIAL
BUFFER
(OSB)

PARITY
Parity Bit

Serial
Data

Transfer
Done Flog
Data Error or
Parity Error
Clock Pulse and Begin

Data Request
DATA
INTERRUPT
CONTROL

Data In
Data Request Answered

DRUM
DATA
CHANNEL
Clock Track

To DFB
and DCl

Track a
DRUM

Track Selection
(9)

TRACK
ADDRESS

X AND Y

SELECT

64,128, or 256
Heads

(DTR)
ACCUMULATOR

~~:;~~~r l~~~~ion Ini-D-R-U-M-C-O-R-E-'
Memory (16 bits)

1+ lost Address
of Data Transfer
(16 bits)

Track 255

lOCATION
COUNTER
(DCl)

~PDP- 7 ;-------7 <EE:~----------- Type 24 Serial Drum _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~>
Computer

Figure 7-6

Drum Logic and Interface Connections

7-20

PRECISION CRT DISPLAY TYPE 30
The Type 30 displays points on the face of a cathode ray tube. Each point is located by its
x- and y-coordinates in a square array whose origin is in the lower left corner of the tube
face. The array contains 1024 points on a side and measures 9-1/4" x 9-1/4".
The x- and y-coordinates have their own 10-bit buffers which are loaded from bits 8-17 of
the AC. In addition, there is a 3-bit brightness register (BR) which is loaded from bits
15-17 of the AC. The contents of this buffer specify the brightness of the point being
displayed on the scale below. The five brightest intensities are easi Iy visible in a normally
lighted room; th.e dimmest can be seen ina darkened room.
C(BR)

Intensity

3
2
1

brightest

average

7
6
5
4

dimmest

The x- and y-coordinate buffers (XB and YB) are loaded separately. Either may be loaded
without selecting the CRT. The usual procedure is to load one buffer, then load the second
buffer and select in one instruction. The Type 30 requires 50 microseconds to display a
point. No flag is associated with this operation.
The iot instructions for the Type 30 are as follows:
MNEMONIC
SYMBOL

OCTAL
CODE

FUNCTION

dxl

700506

Load the x-coordinate buffer from AC 8 - 17 .

C(AC 8 _17) = > C(XB)
dxs

700546

Load the x-coordinate buffer and select. The
point specified by the C(XB) and C(YB) is
displayed.

dyl

700606

Load the y-coordinate buffer.
C(AC 8 _ 17) = > C(YB)

dys

700646

Load the y-coordinate buffer and select. The
point specified by the C(XB) and C(YB) is
displayed.

7-21

MNEMONIC
SYMBOL

OCTAL
CODE

dxc

700502

C lear the x-coordinate buffer.

dye

700602

Clear the y-coordinate buffer.

dlb

700706

Load the brightness register from AC 15 - 17 .
Note: This instruction clears the display flag
connected to the light pen.

FUNCTION

PRECISION INCREMENTAL DISPLAY TYPE 340
The Type 340 Incremental Display is designed to permit rapid plotting of adjacent points,
as in vectors and geometric figures. Adjacent points are plotted at a rate of 1.5 jJS per
point. Point locations are specified on a 9-3/8 inch square raster by any of the 1024X
and 1024 Y coordinate addresses. The origin is at the lower left corner of the raster.
Plotting information is taken from sequential locations of core memory. Five word formats
are used to display data in one of four modes. The location of the first word of the data is
specified by the contents of bits 5-17 of the AC. The five word formats are as follows:
PARAMETER WORD Specifies the mode of display of the next word in sequence, the scale
and intensity of the display, and status of the light pen.
POINl MODE WORD Specifies an x- or y-coordinate, light pen status, and the mode of
the following word. Used for displaying random (non-sequential) points. Random points
are displayed at the slower rate of 35 jJS per point.
VECTOR MODE WORD Specifies the magnitude and direction of the x- and y-components
of a vector. An escape bit determines whether or not the following word wi II be a
parameter word.
VECTOR CONTINUE MODE WORD As in the vector mode, this format specifies magnitude
and direction of components, but the vector is continued unti I the edge of the grid is
encountered.
INCREMENT MODE WORD From a currently displayed point, this word specifies the
direction in which the next adjacent point is to be displayed. Four increments are
specified by a single word.
Detai led description of the Type 340 operation and the structure of the word formats are
given in Digital's publication "Precision Incremental CRT Display Type 340" F-13(340).
A Iist of the instructions added with the Type 340 follows:

7-22

MNEMONIC
SYMBOL

OCTAL
CODE

idla

700606

Load address and select. The contents of AC5-17
are placed in the display address counter (DAC)
and the display is started.

idse

700501

Skip on edge. If the edge of the grid is encountered (except in vector continue mode),
the display stops and an interrupt occurs if the
PIC is enabled. Skip on stop code. If a stop
code is encountered in a parameter word, the
stop flag is set. This flag is connected to the
program interrupt.

ids i

700601

Skip on stop interrupt. This flag is connected
to the program interrupt.

idsp

700701

Skip if light pen flag is set. When the pen
senses a displayed point, the pen flag is set.
This flag is connected to the program interrupt.

idrs

700504

Continue display. After a I ight pen interrupt,
this causes the display to resume at the point
indicated by the C(DAC).

idrd

700614

Restart display. After a stop code interrupt,
this causes the display to resume at the point
indicated by the C(DAC).

idra

700512

Read display address.
AC _ ·
5 17

idrc

700712

Read x and y coordinates. The C(XBO_S) are
placed in ACO-S, the C(YBO-S) are placed
in AC _ •
9 17

idcf

700704

Clear display control. All flags and interrupts
are c Ieared.

FUNCTION

Places the C(DAC) in

Display Options
Additional equipment is available for use with the Precision Incremental Display Type 340.

7-23

Type 341 Interface to the PDP-7 is a complete computer-display interface to the PDP-7 pro'viding automatic, high-speed address control, data communication, data feedback, program
interrupt, and skip capability. The interface provides sequential access to a single block of
data in the computer core memory.
Type 342 Character Generator plots standard ASCII code characters on a 35-dot matrix in
one of four sizes on the Type 340 Display. Average plotting time is 35 ,",sec per character.
Two 64-character sets are available.
Type 343 Slave Display is used for remote observation of data displayed on the Type 340 Display.
Type 347 Subroutine Option permits data display from arbitrarily located and non-consecutive
display tables within the PDP-7 memory.

HIGH SPEED LIGHT PEN TYPE 370
The high-speed Iight pen is a photosensitive device which senses displayed points on the face
of the CRT. The Type 370 uses a fiber optic light pipe and photomultiplier system, which
gives the pen a response time approximately five times faster than that of a photodiode. If the
pen is held in front of a point displayed on the face of the CRT, it transmits a signal which
sets the display flag to 1. The Type 370 is equipped with a mechanical shutter which prevents
the sensing of unwanted information whi Ie positioning the pen. Variable fields of view are
obtained by means of a series of interchangeable tips with fixed apertures. The iot instructions
for the I ight pen are:
dsf
dcf

700501
700502

Skip if the display flag is set.
C lear the display flag.

Operation and programming of the Type 32, a photodiode light pen, are the same as for the
Type 370.

SYMBOL GENERATOR TYPE 33
The symbol generator allows the programmer to plot text on the face of a Type 30 Display
without having to specify every point of each character. This capabil ity increases the speed
of text display by a factor of about ten and reduces flicker proportionally.
Each symbol is plotted on a matrix of 35 dots (5 dots wide and 7 dots high) in one of four character sizes. The information is supplied in the form of two 18-bit data words. Once the coordinates of the starting point of the matrix are given, two iot instructions suffice to plot the
whole symbol. When the plot is complete, the contents of the x-coordinate buffer are incremented automatically to provide a space between characters.
To plot a Iine of text, the coordinates of the starting point are given, using the two iot instructions, dxl and dyl. This point is the lower left dot of the matrix for the first symbol. Second,
the format must be spec ifi ed. Bits 15-17 of the AC spec ify the character size and whether automatic spac ing is to be employed. Fina lIy, the two plot instructions are given to display the
symbol.
7-24

Detailed descriptions of the Type 33 operation and word format are given in the publication
Digital Symbol Generator Type 33, F-13(33B}.

MULTIPURPOSE ANALOG- TO-DIGITAL
CONVERTER TYPE 138B
Twenty-four combinations of conversion accuracy and word length are possible with the
Type 138B. Rotary switches on the front panel allow the converter characteristics to be
changed to suit the application. One switch varies the word length from 6 to 11 bits. A
second switch varies the switching point error from ± 1 .6% to ± O. 05%. Conversion time
varies with the switch settings as shown in the table.
The left-hand parameter is the maximum switching point error. Overall conversion error
equals this error plus a quantization error of ± 1/2 LSB (least significant bit). At the top
of the table is the resolution in terms of the total number of binary bits. The table shows
the total time required to perform a conversion. (See p. 7-26)
The six circled values in the table are for general purpose applications. The 11 lower
settings are for use when accuracy, repeatability, and differential linearity are more
important than resolution (as in histograms). The seven upper settings may be used when
resolution is more important than accuracy, repeatability, and differential linearity (as
in averaging applications).

Input

Analog signal may vary between 0 and -10 volts. Input load
is ± 1 microampere and 125 picofarads. If a different voltage
range is desired, it is recommended that an ampl ifier be
used at the source, since this will also provide a low driving
impedance and reduce possibilities of noise pickup between
the source and the converter.

Output

A signed binary number of 6 to 11 bits, left justified, with
negative numbers represented in 2's complement notation.
A a volt input gives the digital number 10000 .
... A -5 volt input produces OOOO ..... A -10 volt input
produces 01111 ..... Ones are represented by DEC Standard
-3 volt Logic Levels; zeros, by ground levels. (Unsigned
output is available on special order.)

7-25

Instructions
The iot instructions for the converter are:
adsc

701304

Se lect and convert. The converter flag is cleared
and a conversion of an incoming voltage is
initiated on the channel specified by the multiplexer address register. When the conversion is
complete I the converter flag is set.

adrb

701312

Read converter buffer. Places the cont ents of the
buffer in the AC left adjusted. The remaining AC
bits are cleared. The converter flag is cleared.

adsf

701301

Sk ip if converter flag is set. Th is flag is connected
to the program interrupt.

A-to-D CONVERTER TYPE 138B
CONVERSION TIMES
{Microseconds}

Max. Switching
Point Error

0.80/0

(£)

0.2 %

0.1%
0.05 %

N umber of Bits
8
9

7-26

MUL TI PLEXER CON TR OL TYPE 139
The Type 139 is intended for use with the Type 138 A-to-D systems in applications where the
PDP-7 must process sampled analog data from multiple sources at high speeds. For each new
point selected, the multiplexer adds approximately 2.5 ""sec to the Type 138 A-to-D conversion time. For example the combined time to switch to a point and convert with 1 O-bit accuracy is 2.5 ""sec +27 ""sec = 29.5 ""sec. Switching point accuracy for this example is 99.90
percent with an additional quant-ization error of half the least significant bit.
The Type 139 Multiplexer Control can include from one to 16 Type 15780 Multiplexer
Modules (each module contains 4 independent transistorized floating switches), letting the
user select any multiple of four channels to a maximum of 64. In the Individual Address
mode, the Type 139 routes the data from any selected channel to the Type 138 converter
input. In the Sequential Address mode, the multiplexer advances its channel address by one
each time it receives an indexing command, returning to channel zero after scanning the
last channel. Sequenced operations can be short-cycled when the number of channels in
use is less than the maximum avai lable.
A 6-bit multiplexer address register (MAR) specifies a channel number from 0-778. A channel
address may be chosen in one of two ways. It can be specified by the contents of bits 12-17
of the AC or by indexing the contents of the MAR. The following iot instructions are used:
adsm

701103

Select MX channel. The contents of AC 12-17
are pi aced in the MAR.

adim

701201

Index channel address. The contents of the MAR
are incremented by L. Channel 0 follows
channel 778.

The channel address select instructions do not initiate a conversion. This can be done only
by an adsc instruction to the converter (see Type 138).

Multiplexer Specifications
Multiplexer Switching time
2.3 microseconds for source resistance (R) < 50 ohms 2.27 + 0.006 R (to be specified on
order) for source resistance> 50 ohms.
Multiplex
Six lines accept DEC standard levels of 0 and - 3 volts, with 0 volts for assertion.
Individual Address Control
Two pulses or level changes for clear and readin. The clear input accepts negative going
signals with a swing of 2.5 to 4 volts, a fall time less than 0.5 microseconds, and a width
greater than 60 nanoseconds. The readin terminal should receive a similar positive-going
signal 1 microsecond later. Address inputs should be brought to final value at least 1 microsecond before clear.
7-27

Sequential Address Control
One pulse or level change for indexing should be negative going as above. Multiplex
address inputs must be returned to -3 volts at least 2 microseconds before indexing.
Convert
One negative pulse, -2.5 volts amplitude and 0.2 to 0.4 microseconds duration. This
may occur 2.3 microseconds after a clear or index pulse (2.27 + 0.006R microseconds
for source impedance greater than 50 ohms) .

HIGH SPEED ANALOG-TO-DIGITAL CONVERTER TYPE 142
The Type 142 Analog-to-Digital Converter transforms an analog voltage to a signed, 10-digit
binary number with two's complement representation for negative numbers. Extremely high
rates of conversion are possible with this unit; five microseconds is needed for one conversion.
The sampl ing technique, a series of simultaneous comparisons, is responsible for the speed with
which conversions take place; other methods used in similar conversion applications require
20 ~sec or more for a 10-bit conversion. The new method simultaneously compares the amplitude of an analog signal with 16 digital values. Conversion accuracy is ±0.15% ±1/2 LSB
(least significant bit).

OUTPUT REGISTER
/'--',
D TO A rJ'//,,--------IVMAX)
I
\
.....
.... I

4 BITS
GRAY CODE

__ ....

DTO A L.I'//v-------.:VMIN
\

Figure 7-7

'- -~

I
I

Type 142 Simplified Block Diagram

7-28

In the simplified block diagram, the voltage scales for each step are produced by the equipment shown at left. Two D-A converters define maximum and minimum voltage levels; 14
precision resistors generate a voltage scale between them. These resistances, plus the D-A
converters, define 16 equal voltage levels. The 15 node points are applied to 15 comparators
and are compared to the analog input. Registers A, B, and C are loaded with a Gray-coded
word after each comparison during the conversion. The output register holds the 10-bit
binary word at the end of conversion.
The Type 142 A-D Converter uses DEC System Modules throughout and is housed in two
25-position DEC mounting panels.

Spec ifications
Indicators
Indicators for the system are included on a standard 5-1/4 inch rack-mounting panel.
The contents of the output register and Gray code registers are shown by the indicators.
Input
The analog signal can vary between 0 and -9 volts. The CONVERT pulse is the only
digital input required. It should be a negative-going signal with a swing of 2.5 to 4
volts, a fall time less than 0.5 ~sec, and a width greater than 60 nsec. The input
presents a pulse load of 3 units. Maximum current is 25 microamperes.
Output
10 binary bits in two's complement notation. When used with PDP-7, these transfer to
most significant bits of computer words. When used separately, signals are -3 volts for
a one, ground for a zero. Avai lable from 2 ~sec after end of conversion unti I 3 ~sec
after start of next conversion.

DATA COMMUNICATION SYSTEM TYPE 630
The 630 Data Communication System (DCS) is a real time interface between Teletype
stations and PDP-7. It is used for multiuser time sharing systems, message switching systems,
and data collection-processing systems. Its basic function is to receive and transmit
characters. When receiving, characters of different data rates and unit codes arrive from
the Teletype stations in serial form. The DCS converts the signals to Digital voltage levels;
the characters are converted from serial to parallel form and are forwarded to the computer.
When transmitting, characters in parallel form are presented to the Des by the computer.
The characters are converted to serial Teletype form of the correct data rate and unit code;
they are converted from Digital voltage levels to Teletype station signal levels, and they
are sent to the Teletype stations.
The modularity and plugability of the 630 DCS simplify the expansion of the system from one
station to 64 stations. Various combinations of data rates, unit codes, station types, and
station signal levels can be accommodated in one 630 DeS.

7-29

The 630 System consists of the 631 Data Line Interfaces, 632 Send/Receive Groups, and a
633 F lag. Scanner. It has a maximum capacity of 8 groups (8 stations per group) or 64
stations (128 pairs of wires for full duplex operation).
The Type 631 Data Line Interface converts Teletype station signal levels to Digital voltage
levels and converts Digital voltage levels to Teletype station signal levels. The extent of
moduJarity of the 631 is dependent upon the type of station signals to be converted. The
631 is pi ug connected to the 632.
The Type 632 Send/Receive Group converts parallel characters to serial Teletype characters
or converts serial Teletype characters to parallel characters. It mixes the received
characters of the eight Teletype stations onto a bus for presentation to the 633 and notifies
the 633 when service is required.
When a character has been received or transmitted, a flag (indicator) is activated. The
flag in turn notifies the 633 that service is required for that particular station. The manual
OFF-ON switch mounted on the handle of the receiver and transmitter modules may be
turned off to inhibit the flag from requesting service.
The Type 632 can accommodate a maximum of eight receiver modules and eight transmitter
modules. The quantity required is dependent upon the number of Teletype stations. (If
four half duplex stations are to be interfaced, only four receiver and four transmitter modules
are required.) The type of each module required is dependent upon the data rate, un it
code, and the number of data bits. Teletype stations requiring different data rates, unit
codes, and data bits can be intermixed in the Type 632. The receiver module disregards
hits (noise) less than one-half of a unit in length on an idle line. The 632 is completely
pluggable.
The Type 633 Flag Scanner decodes and interprets computer instructions, forwards received
characters to the computer upon request from the computer, sends characters to the transmitter modules when instructed by the computer, scans each 632 in search of activated
flags, notifies the computer when an activated flag has been found, and forwards the
station number requiring service to the computer upon request from the computer.
The Type 633 contains a precision crystal-controlled clock that generates highly accurate
timing pulses. The transmitter and receiver modules use the pulses to sample the serial
Teletype signals. An additional crystal clock can be added to accommodate multiple
Teletype speeds. A crystal clock is also used to generate timing pulses that control the
search logic of the scanner. The scanning mechanism of the 633 is modular. Each expansion permits eight additional stations (1 group) to be scanned.
A rotating priority scanner notifies the computer when an active flag has been found. The
computer program requests the station number and then handles the character. Programmed
priority of the stations is perm itted.

7-30

The flag scanner operates at the following speeds: the maximum total time required to examine
64 inactive stations, 32 microseconds; the maximum total time to search, notify the computer
and continue to search for 64 simultaneously active stations, 544 microseconds (exclusive of
computer interrupt and programming cycles); the minimum time required to find the next active
station upon being released by the computer, 6 microseconds; and the maximum time required
to find the next active station (station being serviced minus one) upon being released by the
computer, 92 microseconds.

Eight-Channel DCS
For smaller, lower-cost Data Communication Systems, programmed flag scanning can be used
in place of the hardware Type 633 Flag Scanner. Up to eight remote teletype stations can be
interfaced to the PDP-7 using the Type 634 Control.
The Type 634 Control:
1.
2.
3.
4.

decodes and interprets computer instructions.
forwards receive characters to the computer upon request from the computer.
sends characters to the transm itter modu Ies when instructed by the computer.
requests computer service when notified by the 632 that service is required.

The Type 634 contains a precision crystal-controlled clock which generates highly
accurate timing pulses. The transmitter and receiver modules use these pulses to
sample the serial Teletype signals. An additional crystal clock can be added to
accommodate intermixed Teletype speeds.
A computer program tests each flag to determine the station requesting service. A
system of eight (8) stations tends to be the practical limit for this method of station
service request detection. For more than 8 stations, a high-speed built-in flag
scanner is recommended.
When the system is used in-house, the function of the 631 may be inc luded in the
634. The 634 is a totally pluggable unit.
For a complete description of the DCS interface characteristics, operation, and instruction
sets, refer to the Digital publication F-03 (630A).

7-31

CARD READER AND CONTROL TYPE 421A
The card reader reads standard 12-row, 80-column punched cards at a maximum rate of 200
cards per minute. Cards are read by columns beginning with column 1. One select instruction starts the card moving past the read station. Once a card is in motion, all 80 columns
are read. The information obtained from each column is placed in a 12-bit card reader
buffer (CRB) from which it is transferred to the AC by the read buffer iot instruction.
The card reader buffer is a 12-bit register into which the information obtained from reading
a card col umn is placed. Cards may be read in one of two modes:
Alphanumeric: The holes (bits) in a column are interpreted as a Hollerith character code
(see Appendix). This is translated into a 6-bit card reader code for that character, which
is then placed in bits 6-11 of the CRB .• Bits 0-5 of the CRB are cleared.
Binary: The 12 bits of each column are accepted literally as a 12-digit binary number and
placed directly into the CRB. A punch is interpreted as a 1; no punch, as a O.

Card Reader Operat ion
Figure 7-8 is a photograph of the card reader console. The feed hopper is at the right, the
run-out stacker at the Ieft. Cards to be read are placed face down in the hopper, with the
tops of the cards (12 1 s edge) facing the operator. The plastic IIhat ll is placed on top of the
desk to insure that enough weight is provided to prevent jamming as the last few cards are
read.
The card reader console contains the buttons which control the operation of the device and
the lights which indicate its availability. From the standpoint of the program, the card
reader has two states, READY and NOT READY. In the READY condition, the card reader
accepts a select instruction and moves a card through the read station. The NOT READY
condition is caused by one of the following: power off, cover (of the console) not in place,
empty hopper, full stacker, malfunction (read check, feed check, val idity check), or endof-fi Ie condition.
In each of these cases, the NOT READY light on the console is lit. The NOT READY
condition exists unti I the 5T ART button is pressed, at which time the NOT READY I ight goes
out. If a malfunction exists, the reset button must be pressed first.

7-32

T he control buttons function as follows:
Button

Function

POWER ON
POWER OFF

These buttons control the primary power to the reader.
When the POWER ON button is pressed, it lights green;
the motors are started, and the drive rollers which move a
card through the reader are set in motion.

START

This button must be pressed to clear the not ready condition.
Only then does the card reader accept a select instruction.

STOP

If the reader is in operation when this button is pressed,
the reading of the currently selected card is completed,
the reader stops, and the NOT READY I ight goes on. The
START button must be pressed to make the reader available
again.

RESET

After a malfunction (see below) has occurred, the RESET
button must be pressed to turn off the 'c heck light and
clear the reader logic of the condition which caused the
error. It does not turn off the NOT READY light.

END OF FILE

When the operator wishes to signal the program that no
more cards are to be expected, he presses the EN D OF
FILE button when the hopper is empty. The button lights
white when this happens. If the hopper is not empty,
pressing this button has no effect. The end-of-file condition is removed and the light extinguished when cards are
placed in the hopper.

VALIDITY ON

If this button is pressed, validity errors (see below) that
occur when reading in the alphanumeric mode cause the
not ready condition to occur. The card reading is completed, and the reader stops. This button, which lights
ye II ow when pressed, has no effect when read ing in
binary mode.

The state of the reader is indicated by the console lights.
Indication

Light
NOT READY

When one of the conditions described above exists, this
white light is lit. As long as it is on, the reader is not
avai lable to the program. The NOT READY I ight is turned
off only by pressing the START button.

7-33

[NO
OF

NOT
HEADY

FILE

Figure 7-9

Card Reader Control Panel

Figure 7-8

Card Reader Console

7-34

Indication
READ CHECK
FEED CHECK
VALIDITY CHECK

Each of these red malfunction Iights is Iit whenever the
corresponding error condition exists. In each case, the
NOT READY Iight goes on at the same time, the current
card is passed out of the reader, and reading stops. To
make another attempt to read the card causing the error,
take it from the top of the stacker and place it on the
bottom of the deck in the hopper. Pressing RESET clears
the malfunction and turns off the corresponding light,
after which, pressing START clears the NOT READY light
and makes the reader avai lable.

Card Reader C heck Ind i cators
Read Check When a read check error occurs, it indicates that something is wrong in the
reading circuitry. If the condition is temporary, a second attempt to read the card should
be successful. More likely, however, a read check indicates a failure of some part of the
circuit, such as a bad read lamp or photocell. In this case, the reader probably requires
technical attention.
Feed Check This error occurs when a card fails to move properly through the feed ways
from the hopper into the stacker. If the card is bent, it may jam in the feed ways. If the
trai Iing edge has been damaged by frequent handl ing, the pickup knife on the bottom of the
hopper may not move the card to the drive rollers. When the card fai Is to appear at the
read station in the prescribed time, a feed check occurs. In any case, the card in error
should not be put back into the deck for a second read attempt, but a duplicate shou~d be
made and put in its place.
Validity Check When reading in alphanumeric mode, every column is checked to see if
the punches correspond to a valid Hollerith character. If they do not, a validity check
occurs and the CRB is cleared to O. If the VALIDITY ON button has been pressed, the NOT
READY light goes on and the reader stops. The card in error should be checked for improper
punches before a second attempt is made to read it.
The appendix gives a table of Hollerith character codes. Any punch combination which does
not appear in this table is invalid.

Programm i ng
There are four flags associated with the card reader. Each of the flags is associated with a
bit in the AC. When an iors instruction is executed, the status of the flags is read into these
bits.

7-35

Card Column This flag signals the presence of information in the CRB.
skip instruction and is connected to the program interrupt.

It is sensed by a

Card Done As soon as the trai Iing edge of the card has begun to pass the reading station,
this flag is set. It is cleared as soon as the next select instruction is given.
Not Ready Whenever the reader is not avai lable, this flag is set. It corresponds exactly
to the NOT READY light on the reader console and is set or cleared by the same operations.
End of File This flag corresponds to the END OF FILE light and button on the reader console. It is set when the EOF button is pressed and the hopper is empty; it is cleared when
more cards are placed in the hopper.

Instructions
MNEMONIC
SYMBOL

OCTAL
CODE

crsa

706704

Select and read a card in alphanumeric mode.
A card is started through the reader and 80
columns are read, interpreted, and translated
into 6-bit character codes. If the VALIDITY ON
button is lit, a validity check causes the reader
to stop.

crsb

706714

Select and read a card in binary mode. A card
is started through the reader and 80 columns are
read as 12-bit numbers. VALIDITY ON has no
effect since validity checking is not performed
during this mode.

crrb

706712

Read the card reader buffer. The C (CRB) are
placed in bits 6-17 of the AC. The card column
flag is cleared.

crsf

706701

Skip if the card column flag is set.

FUNCTION

Because a val idity error causes the CRB to be cleared, the program can easi Iy detect such
errors and take the appropriate action. For example, the number of the column or columns
in error can be typed on the printer to hel p the operator in checking the card.

7-36

Timing
When a card is selected, the card done flag is cleared. A minimum time of 83 microseconds
elapses before the first column is present in the CRB, at which time the card column flag is
set. The program then has 2.3 milliseconds to read the contents of the CRB into the AC. At
the end of that time, the information from the next column is present. A column is ready
every 2.3 milliseconds until the 80th column is encountered. The card done flag is set 600 to
1200 microseconds after the last column is read. If a select instruction is given within the
next 20 microseconds, the reader continues at its maximum reading rate.

OUTPUT RELAY BUFFER (18 BITS) TYPE 140
The Type 140 Relay Buffer consists of an l8-bit relay register and 18 HGS-1009 relays all
mounted within a standard 18 x 5-1/4" computer rack. Each relay is rated at 2 amperes for
500 volts and may be used to directly control external operations or transfer sensing signals
to and from external equipment.
The status of the 18 relays corresponds to the status of the 18 bits of the PDP-7 accumulator.
Two lOT instructions control the contents of the relay buffer. One lOT instruction reads the
contents of the accumu lator into the reader buffer; the other lOT clears the reader buffer.
The front panel of the 140 Re lay Buffer contains 18 indicator Iights to display the status of
each relay. The panel also contains 4 banana jack plugs for each relay output: a ground,
the 1 side of the relay, the 0 side of the relay, and a common point.

CARD PUNCH CONTROL TYPE 40
The card punch control is designed to allow the operation of a device such as the IBM
Model 523 Summary Punch. This type of punch requires one select instruction for each
card. Once the card is in motion, the 12 rows are punched at fixed intervals. If a select
instruction has not been given within a maximum time after the punching of the previous
card is completed, the punch shuts itself off.
The card punch control contains an 80-bit punch buffer (CPB) into which information is
placed for output. When a row has been punched and the CPB is ready to accept new
information, the card row flag is set. This flag is sensed by an iot skip instruction and is
connected to the PIC.

7-37

Instruct ions
The four iot instructions associated with the card punch are:
cpse

706442

Select the card punch. This starts a card moving
from the hopper to the punch station. Load the
card punch buffer. This transm its the contents of
the AC to the CPS. Five are required to fi II the
CPS (see below).

cpsf

706401

Skip if card flag is set. This flag is set when the
CPS is ready to accept a new row.

cpcf

706402

C lear the card row flag.

cplb

706406

Load the punch buffer, clear punch flag.

The 80-bit CPS is loaded from the 18-bit AC. Five cplb instructions are required to
assemble a complete row. The first four fill up the first 72 bits of the CPS (corresponding
to the first 72 columns of the card). The fifth cplb places the contents of bits 10-17 of the
AC in the last eight bits of the CPS and clears the card row flag.

AUTOMATIC LINE PRINTER TYPE 647
The Type 647 Line Printer prints Iines of text of up to 120 characters at a maximum rate of
300 I ines per minute. Printing is performed by solenoid-actuated hammers. The typeface
is engraved on the surface of the continuously rotating drum. A 64-character set is provided.

Interface
Information is transferred from computer to printer through the interface, which contains a
core buffer in which a line to be printed is assembled character by character. Each
character is represented by a 6-bit binary code. When a print cycle is initiated, the core
buffer is scanned each time a row on the drum comes up to the print station. As the
characters are printed, the corresponding core buffer positions are cleared so that at the
completion of the print cycle the buffer is clear and ready for the next line.

Printing
A print cycle is initiated by a command from the program. Depending on the distribution and
number of different characters in the line to be printed, a print cycle may take from about
48 to 180 milliseconds, not including vertical spacing of the paper.

7-38

Vertical Format Control
Vertical movement of the paper is under control of a punched format tape. Eight programselectable channels determine the amount of vertical spacing by sensing the punches in the
tape. Spacing is performed at the completion of a print cycle, at which time the contents
of bits 15-17 of the AC cause one of the eight channels to be selected. The paper and
tape then move until a hole in the tape is sensed. The table below shows the increments
punched on the standard format tape. The user may also create his own formats for which
a special punch is avai lable.
AC Bits
15-17

Tape
Channel

Spacing Increment,

2
3
4
5
6
7
8
1

Every line
Every 2nd line
Every 3rd line
Every 6th line
Every 11 th line (1/6 page)
Every 22nd line (1/3 page)
Every 33rd line (1/2 page)
Top of next form

1
2
3
4
5
6
7

Note that spacing is referenced from the top of the form. A space of one line requires 18 milliseconds. Longer skips vary in time; a full-page skip to the top of the next form takes about
610 milliseconds.

Operating Controls and Indicators
With the exception of the main power switch and certain test buttons, all of the operating
controls are located on two panels. The main panel is at the left on the front of the printer;
the auxiliary panel is at the rear on the same side of the machine.
ON, OFF: These buttons control primary power to the function ing parts of the printer.
The main power switch must be turned on for these buttons to function. The rest of the
controls operate only after ON has been pressed.
START: Places the printer on-line; it is then ready to receive information and print it.
STOP: Takes the printer off-line as soon as the buffer is clear. If there is information in
the buffer, the printer remains on line unti I after the next clear buffer instruction or the
completion of the next print cycle. When the printer goes off line, an alarm signal is sent
to the computer.
TEST PRINT: This button is for checking purposes; it is not used in normal operation.
TOP OF FORM: Moves the paper to the top of the next page.
when the printer is off line.

7-39

This button works only

TRACTOR INDEX: Used for aligning the forms with the format tape when new paper is
loaded. This button works only when the printer is off line.
PAPER LOW ALERT: This indicator lights red when the end of the paper is about to pass
through the drag devices below the printer yoke. An alarm signal is sent to the computer
at the same time.
NO PAPER: When the end of the paper has passed out of the forms tractors, this indicator
Iights red, and an alarm signal is sent to the computer.
YOKE OPEN: When the printer yoke is open, this indicator lights red. An interlock
prevents all but the TOP OF FORM and TRACTOR INDEX controls from operating.
ALARM STATUS: Whenever an alarm signal is generated, this indicator lights red.
In addition to the above ways, an alarm can be generated by a failure in any part of the
printer; such a failure automatically takes the printer off line.
Programm i ng
A line to be printed is assembled in the printer buffer character by character from left to right.
When the line is complete, a program command initiates the print cycle. When the cycle is
finished, the paper mayor may not be spaced vertically. Suppressing vertical movement makes
underscoring and overbarring possible. When spacing is performed, the printer buffer becomes
available 6 to 8 milliseconds before the paper comes to a stop. The program may begin assembling the next line during this time.
Three loading instructions allow the program to transfer one, two, or three characters at a
time from the AC to the printer buffer. If more than one character is transferred, the leftmost one is taken first.
The buffer loading instructions perform the Inclusive OR of the contents of the AC and the
current positions of the printer buffer. Thus, the buffer must be clear before a new I ine is
loaded. Clearing is done automatically during the print cycle, and an instruction is provided for initializing the interface and clearing the buffer before starting to print.
The capacity of the printer buffer is 120 characters. The program must keep track of the
number of characters transferred; if more than 120 are sent, the extra codes are ignored.
Two flags are associated with the Type 647. The buffer flag is set when the buffer is
cleared; this occurs at the end of the print cycle or as the result of a clear instruction.
The error flag is set when an alarm signal is sent and can be reset only when the alarm
condition is removed. Both flags are connected to,the p'rogram interrupt control.
The following instructions are added with the Type 647 Automatic Line Printer:

7-40

MNEMONIC
SYMBOL

OCTAL
CODE

Ipb-1

706504

Load printer buffer with 1 character. The
contents of AC12-17 are transferred to the
buffer. A minimum of 10l-lsec must elapse
before the next load instruction may be given.

Ipb-2

706524

Load printer buffer with 2 characters. The
two character codes represented by the middle
(bits 6-11) and right (bits 12-17) portions of
the AC are transferred in that order to the
buffer. A minimum of 20 I-lsec must elapse
before the next load instruction.

Ipb-3

706544

Load printer buffer with 3 characters. The
character codes in the left, middle, and right
portions of the AC are transferred to the
buffer in that order. A minimum of 30 I-lsec
must elapse before the next load instruction.

cpb

706502

C lear printer buffer. The contents of the
buffer are set to o. The buffer flag is set on
completion of this operation.

pri

706604

Print. The contents of the printer buffer are
printed, but the paper is not moved. The next
Iine of characters wi II be printed in the same
space. This makes underlining and overbarring
possible. The buffer flag is set when this
operation is complete.

pas

706624

Pr i nt and space. The contents of the buffer
are printed, and the paper is spaced vertically.
The spacing increment is specified by
C(AC 15 _ 17). The buffer flag is set 6 to 8
microseconds before the spacing is completed.

cbf

706602

C Iear buffer fl ag.

sbf

706501

Skip if buffer flag is set.

sef

706601

Skip if error flag is set.

706522

Spare.

OPERATION

The status of the buffer and error flags is read into ACbits 15 and 16, respectively, by
the iors instruction.
7-41

APPEN DIX 1
TELEPRINTER CODES

Baudot
(28 KSR)

FlO-DEC

ASCII
(33 KSR)

0-9
a-z
A-Z

0-9

A-Z
SA-$Z

A-Z
A-Z

(pe'riod)
!min!a!s signl
(center dot, per iod)
(center dot, comma}

)

(
)

(

(mu / tip/ y)

.......----,.....-.-

t
II

~II

[

$1
$:
$(

J
<
>

$)
$$"

""-

::::>

.,_ . __.V-1\
.........

l/crtical stroke}
(u nderhar)
(center dot)

)
I

(
)
+

*
II

5
<
>

..-

0/0

$#
$;
$!

"$
n.e.
II

~=.:'rbarl

Stop Code

)

n.e.

Form Feed

b~U

Tab

A 1-1

Tab

APPENDIX 2
TELETYPE EIGHT-LEVEL CODE
(ASC10
1 = HOLE PUNCHED = MARK
= NO HOLE PUNCHED = SPACE

MOST SIGNIFICANT BIT

'-- A
B
@

- CD

(LEAST SIGNIFICANT BIT

8 7 6 5 4 S 3 2 1
SPACE

a a a
a a 1
a 1 a
a 1 1
1 a a
1 a 1
1 1 a

BELL

a
a a
a 0
a a
a a
a a
a a
a a

FORMAT EFFECTOR

a a a
a a 1
a 1 a
a 1 1
1 a a
1 a 1
1 1 a

NULL/IDLE

START OF MESSAGE

END OF ADDRESS

END OF MESSAGE

-E

END OF TRANSMISSION

WHO ARE YOU

ARE YOU

(

)

HORIZONTAL TAB

-K

LINE FEED

-L

VERTICAL TAB

FORM FEED

CARRIAGE RETURN

-0

SHIFT IN

DCO

a 1
a 1
a 1
a 1
a 1
a 1
a 1
1 a

READER ON

1 0

TAPE (AUX ON)

-J

-M
N

f--f---

SHIFT OUT

R
S

-U
-V

-W
-

-Y
-Z
-

-I

I
-

RUB OUT

-.-

1 1 1

a a 0
0 a 1
a 1 a
a 1 1
1 a a
1 a 1

READER OFF

a
1 a

(AUX OFF)

1 0

ERROR

SYNCHRONOUS IDLE

1 0

LOGICAL END OF MEDIA

a a

-T

a 0 1
a 1 0
a 1 1
1 a a
1 a 1
1 1 a

'-v--J'--v---J

~".----A--~
..

a 0
..., 1 a 1
1 1 a

~ 1

SAME

A2-1

SAME
SAME

APPENDIX 3
CARD READER; HOLLERITH CODE

A
B
C
D
E
F
G
H
I
J

K
L
M
N
0

P
Q
R
S
T
U
V

W
X
Y
Z
0
1
2
3
4
5
6
7
8
9

=
,

$
(

61
62
63
64
65
66
67
70
71
41
42
43
44
45
46
47
50
51
22
23
24
2'5
26
27
30
31
12
01
02
03
04
05
06
07
10
11
60
40
21
13
33
53
73
14
34
54
74

blank 00

High order bits
10
01

blank

+ [&J

00
Low order
bits
0000
0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

= [#J

1100

[@J

$
(

[%J

[oJ

HOLLERITH CARD CODE
Zone
digit
no zone
no punch
1
2
3
4
5
6
7
8
9
8·3
8·4

blank
1
2
3
4
5
6

7
8
9

= [#J

[@]

A3-1

+ [&J

B
C
D
E

F
G
H
I

)

N
0

V
W
X

P
Q
R
$

[OJ

S
T

y
Z

[%J

APPENDIX 4
LINE

A
8
C
0
E
F
G

H
I
J

L
M
N
0
P
Q

R
S
T
U

V
W
X
Y
Z

1
2
3
4
5
6
7
8
9
0

=>
V

=
)
(

61
62
63
64
65
66
67
70
71
41
42
43
44
45
46
47
50
51
22
23
24
25
26
27
30
31
20
01
02
03
04
05
06
07
10
11
40
21
12
13
14
15
16
17
52
53
54
55
57
56

PRINTER CODE

Low order
bits

High order bits
01
10
11

0000

space

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010
1011

1100

1101

]

1110

1111

space 00
60
32
33
> 34
i 35
36
? 37
X 72
73
74
+ 75
77
76
I
~

A4-1

(

[

APPENDIX 5

DIGITAL'S

SERVICE

PRACTICE

Digital's reputation for reliability owes a great deal to rigid quality control and customer
field service. Before delivery all Digital products are thoroughly tested by trained checkout teams. Each module and every piece of accessory equipment is subjected to rigorous
tests, many of them conducted by specially designed, automatic check-out devices. Computers and special systems are checked electrically and logically by numerous programmed
routines.
During system checkout, customers are invited to visit the Maynard manufacturing faci lity
to inspect and become familiar with the equipment. Computer customers may also send
personnel to instruction courses in computer operation and maintenance at the Maynard
headquarte rs .
Digital's engineers are avai lable during installation and test for assistance or consultation.
Further technical assistance in the field is provided by home office design engineers or
branch office application engineers in New York, Washington, Pittsburgh, Chicago, Huntsville,
Los Angeles, San Francisco, Ottawa, Sydney (Australia), Reading (U.K.), and Munich.

A5-1

APPENDIX 6

RI M LOADER

To load the RIM loader, place the RIM loader tape in the reader, set the ADDRESS switches to
17763, and press the READ-IN switch.
The RIM loader contains the following program:
Location

Octal Code

17762/
17763/
17764/
17765/
17766/
17767/
17770/
17771/
17772/
17773/
17774/
17775/
17776/

0
700101
617763
700112
700144
637762
700144
117762
057775
417775
117762
0
617771

go,
g,

out,

Mnemonic

Remarks

0
rsf
imp .-1
rrb
rsb
imp i r
rsb
ims r
dac out
xct out
ims r
0
imp g

/read one binary word
/wait for word to come in
/read buffer
/read another word
/exit subroutine
/enter here, start reader going
/get next binary word
/execute control word
/get data word
/store data word
/continue

To load system tapes and other normal binary tapes, place the tape in the reader, set the
ADDRESS switches to 17770, and press START.

A6-1

APPENDIX 7
INSTRUCTION

SUMMARY

MEMORY REFERENCE INSTRUCTIONS
MACHINE
CYCLES*

OPERATION

MNEMONIC

OCTAL

cal Y

Call subroutine. Y is ignored
jms 20 if bit 4 = 0, jms i 20 if bit 4 = 1 .

dac Y

Deposit AC. C(AC) = >C(Y)

jms Y

Jump to subroutine. C(PC) = > C(Y 5 - 17),
C(L)=> C(Yo), Y + 1 = > C(PC)

dzm Y

Deposit zero in memory. 0 = > C (Y)

lac Y

Load AC. C(Y) = > C(AC)

xor Y

Exclusive OR. C(AC) V C(Y) = > C(AC)

add Y

Add (lis complement).
C(AC) + C(Y) = > C(AC)

tad Y

2 1 s complement add.

xct Y

Execute.

isz Y

Index and skip if O. C(Y) + 1 = > C(Y), if
C(Y) + 1 = 0, then C(PC) + 1 = > C(PC)

and Y

AND. C(AC) A C(Y) = > C(AC)

sad Y

Skip if AC and Y differ. If C(AC) -I C(Y),
then C (PC) + 1 = > C(PC)

jmp Y

Jump. Y = > C(PC)

law N

Load AC with law N. 1 = > C(ACo-4),
N = > C (AC5-17)

C(AC) + C(Y) = > C(AC)

-----------------------------------* 1 machine cycle
1.75 \Jsec.
=

A7-1

OPERATE INSTRUCTIONS

MNEMONIC

OCTAL

EVENT
TIME

OPERATION

opr

740000

Operate.

nop

740000

No operation.

cma

740001

Complement, C(AC) = > C(AC)

cml

740002

Complement link, e(I) = > C(L)

oas

740004

Inclusive OR AC switches.
C(ACS) V C(AC) = > C(AC)

las

750004

2,3

Load AC from switches.
C(ACS) = > C(AC)

ral

740010

Rotate AC + I ink left one place.
C (AC i) = > C (AC i-1), C (L) = > C (AC 17),
C(AC O) = > C(L)

rcl

744010

2,3

C lear Iink, then ral.

rtl

742010

2,3

Rotate AC Ieft twi ce. Same as two ral
instructions.

rar

740020

Rotate AC + I ink right one place.
C(AC j) = > C(AC j+ 1), C(L) = > C(ACO)'
C(AC17) = > C(L)

rcr

744020

2,3

Clear link, then rare

0= > C(L), then rare

rtr

742020

2,3

Rotate AC right twice.
instructions.

Same as two rar

hit

740040

Halt.

sza

740200

Skip on zero AC.
zero.

sna

741200

Skip on non-zero AC. Skip if C(AC) f.
positive zero.

spa

741100

Skip on positive AC. Skip if C(ACO) = O.

A7-2

0= > C(L), then ral.

o = > RUN.
Skip if C(AC) = positive

OPERATE INSTRUCTIONS (continued)

MNEMONIC

OCTAL

EVENT
TIME

OPERATION

sma

740100

Skip on negative AC.

szl

741400

Skip on zero link.

snl

740400

Skip on non-zero I ink.

skp

471000

Skip, unconditional. Always skip.

cll

744000

C lea r link.

0 = > C (L) .

stl

744002

2,3

Set the I ink.

1 = > L.

cia

750000

Clear AC.

clc

750001

2,3

C lear and complement AC.

glk

750020

2,3

Get link.

Skip if C(ACO) = 1 .

Skip if C(L) = O.
Skip if C(L) = 1 .

0 = > C(AC).
-0 = > C(AC).

0 = > C(AC), C(L) = > C(AC 17).

EAE INSTRUCTIONS

MNEMONIC

OPERATION

OCTAL

eae

640000

Basic EAE command - no operation.

Irs

640500

Long right shift.

Irss

660500

Long right shift, -signed.

lis

640600

Long I eft shift.

Iiss

660600

Long left shift, signed.

als

640700

Accumulator left shift.

alss

660700

Accumulator left shift, signed.

norm

640444

Normalize: max. shift is 44.

norms

660444

Normalize, signed.

A7-3

EAE INSTRUCTIONS (continued)
MNEMONIC

OCTAL

OPERATION

mul

653122

Multiply unsigned.

muls

657122

Multiply signed.

div

640323

Divide C(AC and MQ) as a 36-bit unsigned
number.

divs

644323

Divide C(AC and MQ) as a 34-bit lis complement
signed number.

idiv

653323

Integer divide unsigned.

idivs

657323

Integer divide, signed.

frdiv

650323

Fraction divide unsigned.

frdivs

654323

Fraction divide, si gned.

lacq

641002

Replace the C(AC) with the C(MQ).

lacs

641001

Replace the C(AC) with the C(SC).

clq

650000

ClearMQ.

abs

644000

Place absolute val ue of AC in the AC.

gsm

664000

Place AC sign in I ink and take absol ute va Iue
of AC.

osc

640001

Inclusive OR the SC into the AC.

omq

640002

Inclusive OR AC with MQ and place results in
AC.

cmq

640004

Com pi ement the MQ.

A7-4

PRIORITY INTERRUPT INSTRUCTIONS

MNEMONIC

OCTAL

OPERATION

cae

705501

Clear and reset all channels.

asc

705502

Enable selected channel(s}.

dsc

705604

Di sable selected channel (s).

epi

700004

Enable automatic priority interrupt system.

dpi

700044

Disable automatic priority interrupt system.

isc

705504

Initiate break on selected channel (for
maintenance purposes).

dbr

705601

Debreak .... Returns highest priority channel to
receptive state.

lOT INSTRUCTIONS

MNEMONIC

OPERATION

OCTAL
Program Interrupt

iof

700002

Turn off interrupt.

ion

700042

T urn on interrupt.

iton

700062

T urn on trap, also turns on program interrupt.

I/O Equipment
iors

700314

Read status of I/O equipment.

Clock
clsf

700001

Skip if clock flag is 1.

clof

700004

Turn off clock, clear clock flag.

A7-5

lOT INSTRUCTIONS (continued)
MNEMONIC

OCTAL

OPERATION

Clock (continued)
cion

700044

Turn on clock, clear clock flag.

Paper Tape Reader
rsa

700104

Select reader for al phanumeric, clear reader
flag.

rsb

700144

Select reader for binary, c Iear reader fl ag.

rsf

700101

Skip if reader flag is a 1.

rrb

700112

Read the reader buffer into AC, clear reader
flag.

rcf

700102

Clear reader flag then inclusively OR reader
buffer into AC.

Paper Tape Punch
psa

700204

Punch a line of tape in alphanumeric mode. The
punch flag is immediately cleared and then set
when punching is complete.

psb

700244

Punch a Iine of tape in binary mode. The punch
flag is immediately cleared and then set when
punching is complete.

psf

700201

Ski P the following instruction if the punch flag
is set.

pcf

700202

Clear the punch flag.

A7-6

lOT INSTRUCTION (continued)

------------------------------------------ --MNEMONIC

OCTAL

OPERATION

Keyboard Input from Teleprinter
ksf

700301

Ski p if keyboard fl ag is a 1 .

krb

700312

Read the keyboard buffer into the AC, clear
keyboard flag.

Tel epri nter
tsf

700401

Skip if teleprinter flag is a 1 .

tis

700406

Load teleprinter buffer and select, clear teleprinter flag.

tcf

700402

Clear the teleprinter flag.

DECtape 551
Transfers one word from mmiob to the AC.

mmrd

707512

Read.

mmwr

707504

Write. Transfers one word from the AC to mmiob.

mmse

707644

Select. Connects the un it desi gnated to the
DECtape control.

mmlc

707604

Load control. Sets the DECtape control to the
proper mode and direction.

mmrs

707612

Read status. Reads the DEC tape status conditions
into bits 0-8 of the AC.

mmdf

707501

Ski p on DECtape data flag.

mmbf

707601

Skip on DECtape block end flag.

mmef

707541

Ski p on DECtape error flag.

A7-7

lOT INSTRUCTION (continued)
MNEMONIC

OCTAL

OPERATION

Tape Control 57A
mscr

707001

Skip if the tape control ready (TCR) level is 1.

msur

707101

Skip if the tape transport is ready (TTR).

mccw

707401

Clear CA and WC.

mica

707405

Transfer AC bits 5-17 to CA and clear CA and WC.

mlwc

707402

Transfer AC bits 5-17 to we.

mrca

707414

Transfer CA bits 5-17 to AC bits 5-17.

mdcc

707042

Disable the TCR flag from the program interrupt
and clear command register.

mctu

707006

Disable the TCR flag from the program interrupt,
turn off the WCO flag and EOR flag, and select
the unit ,; the mode of parity, and the density
from the AC.

mtcs

707106

Place AC bits 9-12 in the tape control command
register and start tape motion.

mncm

707152

Terminate the continuous mode (the AC is cleared).

mrrc

707204

Switch mode from read to read compare.

mrcr

707244

Switch mode from read compare to read.

msef

707301

Skip if the EOR flag is a 1.

mdef

707302

Disable ERF.

mcef

707322

Clear ERF.

meef

707242

Enable ERF.

mief

707362

Initialize ERF, clear and enable.

mS'IIf

707201

A7-8

lOT INSTRUCTION (continued)
MNEMONIC

OCTAL

OPERATION

Tape Control 57A (continued)
mdwf

707202

Disable WCO flag.

mcwf

707222

Clear WCO flag.

mewf

707242

Enable WCO flag.

miwf

707262

Initialize WCO flag.

mtrs

707314

Read tape status bits into the AC.

Display 30D
dxl

700506

Load the x-coordinate buffer from AC _ .
S 17

dxs

700546

Load the x-coordinate buffer and select.

dyl

700606

Load the y-coordinate buffer.

dys

700646

Load the y-coordinate buffer and select.

dxc

700502

C lear the x-coordinate buffer.

dyc

700602

Clear the y-coordinate buffer.

dlb

700706

Load the brightness register from AC 15 - 17 .

Precision Incremental Display Type 340
idla

700606

Load address and se lect.

idse

700501

Skip on edge, skip on stop code.

idsi

700601

Skip on stop interrupt.

idsp

700701

Skip if I ight pen flag is set.

idrs

700504

Continue display following Iight pen interrupt.
A7-9

lOT INSTRUCTION {continued}
MNEMONIC

OCTAL

idrd

700614

Restart display following stop code interrupt.

idra

700512

Read display address.

idrc

700712

Read x and y coordinates.

idcf

700704

Clear display control.

OPERATION

Light Pen 370
dsf

700501

Skip if the display flag is set.

dcf

700502

C lear the display flag.

Card Reader 421 A
crsa

706704

Select card reader for alphanumeric.

crsb

706714

Select card reader for binary.

crrb

706712

Read card col umn buffer into AC.

crsf

706701

Skip if reader character flag is a 1.

Card Punc h 40
cpsf

706401

Skip if the card punch flag is a 1.

cpse

706444

Select a card, set card punch flag.

cplr

706406

Load row buffer, c Iear punc h fl ag .

cpcf

706442

Clear punch flag.

A7-10

lOT I NSTRUCTION (continued)
MNEMONIC

_.._----------..-..

OCTAL

OPERATION
'---_.'-'
'-'~-.'.-..' -....-"-"----~.. - ' - - - - - - - ,--- -----------

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A7-11

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APPENDIX 8
POWERS

n 2
o

2
4
8

1
2
3

16
32
64
128
256
512
1 024
2 048
4 096
8 192
16 384
32 768
65 536
131 072
262 144
524 288
1 048 576
2 097 152
4 194 304
8 388 608
16 777 216
33 554 432
67 108 864
134 217 728
268 435 456
536 870 912
1 073 741 824
2 147 483 648
4 294 967 296
8 589 934 592
17 179 869 184
34 359 738 368
68 719 476 736
137 438 953 472
274 877 906 944
549 755 813 888
I 099 511 627 776
2 199 023 255 552
4 398 046 511 104
8 796 093 022 208
17 592 186 044 416
35 184 372 088 832
70 368 744 177 664
140 737 488 355 328
281 474 976 710 656
562 949 953 421 312
1 125 899 906 842 624
2 251 799 813 685 248
4 503 599 627 370 496
9 007 199 254 740 992
18 014 398 509 481 984
36 028 797 018 963 968
72 057 594 037 927 936
144 115 188 075 855 872
288 230 376 151 711 744
576 460 752 303 423 488
1 152 921 504 606 846 976
2 305 843 009 213 693 952
4 611 686 018 427 387 904
9 223 372 036 854 775 808
18 446 744 073 709 551 616
36 893 488 147 419 103 232
73 786 976 294 838 206 464
147 573 952 589 676 412 928
295 147 905 179 352 825 856
590 295 810 358 705 651 712
1 180 591 620 717 411 303 424
2 361 183 241 434 822 606 848
4 722 366 482 869 645 213 696

4
5

6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72

OF TWO

-n

1.0
0.5
0.25
0.125
0.062 5
0.031 25
0.015 625
0.007 812 5
0.003 906 25
0.001 953 125
0.000 976 562 5
0.000 488 281 25
0.000 244 140 625
0.000 122 070 312 5
0.000 061 035 156 25
0.000 030 517 578 125
0.000 015 258 789 062 5
0.000 007 629 394 531 25
0.000 003 814 697 265 625
0.000 001 907 348 632 812 5
0.000 000 953 674 316 406 25
0.000 000 476 837 158 203 125
0.000 000 238 418 579 101 562 5
0.000 000 119 209 289 550 781 25
0.000 000 059 604 644 775 390 625
0.000 000 029 802 322 387 695 312 5
0.000 000 014 901 161 193 847 656 25
0.000 000 007 450 580 596 923 828 125
0.000 000 003 725 290 298 461 914 062 5
0.000 000 001 862 645 149 230 957 031 25
0.000 000 000 931 322 574 615 478 515 625
0.000 000 000 465 661 287 307 739 257 812 5
0.000 000 000 232 830 643 653 869 628 906 25
0.000 000 000 116 415 321 826 934 814 453 125
0.000 000 000 058 207 660 913 467 407 226 562 5
0.000 000 000 029 103 830 456 733 703 613 281 25
0.000 000 000 014 551 915 228 366 851 806 640 625
0.000 000 000 007 275 957 614 183 425 903 320 312 5
0.000 000 000 003 637 978 807 091 712 951 660 156 25
0.000 000 000 001 818 989 403 545 856 475 830 078 125
0.000 000 000 000 909 494 701 772 928 237 915 039 062 5
0.000 000 000 000 454 747 350 886 464 118 957 519 531 25
0.000 000 000 000 227 373 675 443 232 059 478 759 765 625
0.000 000 000 000 113 686 837 721 616 029 739 379 882 812 5
0.000 000 000 000 056 843 418 860 808 014 869 689 941 406 25
0.000 000 000 000 028 421 709 430 404 007 434 844 970 703 125
0.000 000 000 000 014 210 854 715 202 003 717 422 485 351 562 5
0.000 000 000 000 007 105 427 357 601 001 858 711 242 675 781 25
0.000 000 000 000 003 552 713 678 800 500 929 355 621 337 890 625
0.000 000 000 000 001 776 356 839 400 250 464 677 810 668 945 312 5
0.000 000 000 000 000 888 178 419 700 125 232 338 905 334 472 656 25
0.000 000 000 000 000 444 089 209 850 062 616 169 452 667 236 328 125
0.000 000 000 000 000 222 044 604 925 031 308 084 726 333 618 164 062 5
0.000 000 000 000 000 111 022 302 462 515 654 042 363 166 809 082 031 25
0.000 000 000 000 000 055 511 151 231 257 827 021 181 583 404 541 015 625
0.000 000 000 000 000 027 755 575 615 628 913 510 590 791 702 270 5u7 812 5
0.000 000 000 000 000 013 877 787 807 814 456 755 295 395 851 135 253 906 25
0.000 000 000 000 000 006 938 893 903 907 228 377 647 697 925 567 626 953 125
0.000 000 000 000 000 003 469 446 951 953 614 188 823 848 962 783 813 476 562 5
0.000 000 000 000 000 001 734 723 475 976 807 094 411 924 481 391 906 738 281 25
0.000 000 000 000 000 000 867 361 737 988 403 547 205 962 240 695 953 369 140 625
0.000 000 000 000 000 000 433 680 868 994 201 773 602 981 120 347 976 684 570 312 5
0.000 000 000 000 000 000 216 840 434 497 100 886 801 490 560 173 988 342 285 156 25
0.000 000 000 000 000 000 108 420 217 248 550 443 400 745 280 086 994 171 142 578 125
0.000 000 000 000 000 000 054 210 108 624 275 221 700 372 640 043 497 085 571 289 062 5
0.000 000 000 000 000 000 027 105 054 312 137 610 850 186 320 021 748 542 785 644 531 25
0.000 000 000 000 000 000 013 552 527 156 068 805 425 093 160 010 874 271 392 822 265 625
0.000 000 000 000 000 000 006 776 263 578 034 402 712 546 580 005 437 135 696 411 132 812 5
0.000 000 000 000 000 000 003 388 131 789 017 201 356 273 290 002 718 567 848 205 566 406 25
0.000 000 000 000 000 000 001 694 065 894 508 600 678 136 645 001 359 283 924 102 783 203 125
0.000 000 000 000 000 000 000 847 032 947 254 300 339 068 322 500 679 641 962 051 391 601 562 5
0.000 000 000 000 000 000 000 423 516 473 627 150 169 534 161 250 339 820 981 025 695 800 781 25
0.000 000 000 000 000 000 000 211 758 236 813 575 084 767 080 625 169 910 490 512 847 900 390 625

A8-1

DIGITAL SALES AND SERVICE
MAIN OFFICE AND PLANT
146 Main Street, Maynard, Massachusetts 01754
Telephone: From Metropolitan Boston: 646·8600
Elsewhere: AC617·897·8821
TWX: 710·347·0212 Cable: Digital Mayn. Telex: 092·027

DIGITAL SALES OFFICES
NORTHEAST OFFICE:
146 Main Street, Maynard, Massachusetts 01754
Telephone: AC617-646·8600 TWX: 710·347-0212
NEW YORK OFFICE:
1259 Route 46, Parsippany, New Jersey 07054
Telephone: AC201-335-0710 TWX: 510·235-8319
WASHINGTON OFFICE:
1430 K. Street, NW, Washington, D. C. 20005
Telephone: AC202-628-4262 TWX. 710·822-9435
SOUTHEAST OFFICE:
Suite 21, Holiday Office Center
3322 Memorial Parkway, S.W., Huntsville, Ala. 3580
Telephone AC205-881·7730
TWX: 205·533-1267
ORLANDO OFFICE:
1510 E. Colonial Drive, Orlando, Florida 32803
Telephone: AC305·422·4511
PITTSBURGH OFFICE:
300 Seco Road, Monroeville, Pennsylvania 15146
Telephone: AC412·351·0700
TWX: 412·372·4695
CHICAGO OFFICE:
910 North Busse Highway, Park Ridge, Illinois 60068
Telephone: AC312·825·6626 TWX: 312·823·3572

ANN ARBOR OFFICE:
3853 Research Park Drive, Ann Arbor, Mich. 48104
Telephone: AC313·761-1150 TWX: 810·223·6053
LOS ANGELES OFFICE:
8939 Sepulveda Boulevard, Los Angeles, Calif. 90045
TWX: 910·328-6121
Telephone: AC213-670·0690
SAN FRANCISCO OFFICE:
2450 Hanover, Palo Alto, California 94304
Telephone: AC415·326·5640 TWX: 910·373·1266
IN CANADA:
Digital Equipment of Canada, Ltd.,
150 Rosamund Street, Carleton Place, Ontario, Canada
Telephone: AC613·237·0772 TWX: 610·561·1650
IN EUROPE:
Digital Equipment GmbH, Theresienstrasse 29
Munich 2/West Germany
Telephone: 29 94 07, 29 25 66 Telex: 841·5·24226
Digital Equipment Corporation (UK) Ltd.
11 Castle Street
Reading, Berkshire, England
Telephone: Reading 57231 Telex: 851-84327
IN AUSTRALIA:
Digital Equipment Australia Pty. Ltd.,
89 Berry Street
North Sydney, New South Wales, Australia
Telephone: 92·0919 Telex: 790AA·20740
Cable: Digital, Sydney

DIGITAL SALES REPRESENTATIVES
IN THE SOUTHWEST:

DATRONICS INC.
7800 Westglen Drive, Houston, Texas 77042
Telephone: AC713·782·9851 TWX: 713-571-2154
7078 San Pedro Avenue, Suite 205,
San Antonio, Texas 78216
Telephone: AC512-824·6368 TWX: 512·571·0788
Post Office Box 782, Kenner, Louisiana 70062
Telephone: AC504·721-1410
Post Office Box 13384, Fort Worth, Texas 76118
Telephone: AC817-281·1284 TWX: 817·281-3120

IN THE NORTHWEST:
SHOWALTER·JUDD, INC.
1806 South Bush Place, Seattle, Washington 98144
Telephone: 206·324-7911 TWX: 206-998-0323
IN JAPAN:
RIKEI TRADING CO.,
12, 2·Chome, Shiba Tamura·cho, Minato·ku,
Tokyo, Japan
Telephone: 591-5246
Cable Rikeigood, Tokyo
IN SWEDEN:
TELARE AB
Industrigatan 4, Stockholm K, Sweden
Telephone: 54 33 24 Telex: 854-10178

5140

PRINTED IN U.S.A.

15-11/64