Digital PDFs

DIGITAL-7-55-M

May 1966

18 pages

Original

0.6MB

Document:	MAINDEC 702R ExtMemChkbd
Order Number:	DIGITAL-7-55-M
Revision:
Pages:	18
Original Filename:	http://bitsavers.org/pdf/dec/pdp7/DIGITAL-7-55-M_MAINDEC_702R_ExtMemChkbd_May66.pdf

OCR Text

1.0

IDE NTIFICA TIO N

1.1

Maindec 702 Revised

1.2

PDP-7 Extended Checkerboard

1.3

May 16, 1966

r=l

171

Ma i ndec 702 R
Page 1

ABSTRACT

The PDP-7 Extended Checkerboard verifies the performance of from 4096 to 32,768 words
of core memory and its associated logic. Memory is exercised in 4096 word increments with four test
patterns and their complement patterns. The program resides in the lower addresses of the first 4K of
memory and relocates to enable exercising of that region of memory.

REQUIREMENTS

3.1

Storage
The program, when initially loaded, occupies locations 0020 to 0474.

3.2

Subprograms {None}

3.3

Equipment
Standard PDP-7 with 4096 to 32,768 words of memory.

3.4

Misce"aneous {Not Applicable}

USAGE

4.1

Loading
The binary tape is punched in HRI mode.

Ac. J'~ Set the AC switches to 0000008 .

ftoPRJ,:sr- 5~ Set the Address switches to 000208 ,
If extended memory is to be tested set the EXTEND mode switch up; otherwise the switch
must be down ."t
Place the HRI mode binary tape in the reader.
Press READ-IN.
The binary tape is read in HRI mode. At the completion of program load, the test will determ ine memory size and initiate memory {see section 4.4 for Start-Up and/or Entry} .

NOTE: With the EXTEND mode switch down, the PDP-7 Extended Checkerboard may be loaded into any of the extended 8K areas and only that area wi II
be tested. At the time of load, with the EXTEND mode switch down, the
ADDRESS switches may be set to any of the following octal settings.

HRI LOAD ADDRESS
00020
20020
40020
60020

TEST
TEST
TEST
TEST

00000 to 17777
20000 to 37777
40000 to 57777
60000 to 77777

With the EXTEND mode switch up, the only address the program may be loaded at is 00020.

Me i ndec 702 R
Page 2

4.2

Calling Sequence (Not Applicable)

4.3

Switch Settings

4.3.1

ADDRESS SWITCHES

Loading Address 00020 (or see section 4.1 for loading into extended memory and not in
EXTEND mode) .

4.3.2

EXTEND Switch
Up

- to test extended memory with Checkerboard in the first 4K .

Down - for a II other cases.

4.3.3

AC Switches
Up

- Suppress writing the corresponding bit as a 1 in memory and do not test that bit for
fai lure.

Down - Include the corresponding bit in generating patterns and test it for failure.

4.4

Start-Up and/or Entry

When the Checkerboard program is read in I it is automatica Ily started at address 0020 by the
memory sizing routine. The first 4K of memory tested is addresses 10000 to 17777 (or 0400 to 7777 if on Iy
a 4K machine). The program then relocates to starting address 10020 (or 7420 if only a 4K machine) and
tests the lowest 4K of memory I addressing 00000 to 07777 (or 0000 to 7377 if only a 4K machine). The
Checkerboard wi II have one of three addresses for restart I depending on mach ine size and where the program was located at the time it was halted.
Set ADDRESS switches to 00020
7420
or 10020
AC switches - down - to test all bits
- up
- to suppress testing
Press START

NOTE: The above addresses are also relative to the 8K of extended memory
into which the program is loaded.

4.5

Errors in Usage
The following halts occur in succession for each error:
HALT 1

C{MA) = 00225, 07625 or 10225
C{AC) = contents of fai led register

Ma i ndec 702 R
Page 3
At least one bit in the memory cell just examined was not in its proper state. Each such bit
in error appears as the complement of the majority of bits. Suppressed bits appear as Os even though they
might be ls in the memory location.
For example, if the contents of the AC = 777767, one of two conclusions may be drawn:
Bit 14 was dropped on the first read/complement.
Bit 14 was picked up on the second read/complement.
Or, the contents of the AC = 000010 bit 14 cou Id have been picked up on the first read/complement or
dropped on the second.
Press CONTINUE:
HALT 2
C (MA) = 00227, 07627, or 10227
C(AC) = address of the register causing the previous HALT.
Press CONTINUE:
HALT 3
C(MA) = 00231, 07631, or 10231
C(AC) = control word used to generate the current memory pattern.
4.6

Recovery from Such Errors
HALT 1: Press CONTINUE for next HALT
HALT 2: Press CONTINUE for next HALT
HALT 3: Press CONTINUE to resume testing

RESTRICTIONS

The EXTEND mode switch must be down if 'the Checkerboard is to be loaded and run outside
the first 8K of memory.
Ma indec 703 Memory Address Test shou Id run successfu lIy before th is test is attempted on
an unknown machine.

DESCRIPTION

6.1

General

The PDP-7 Extended Checkerboard is designed to worst-case test core memory in 4K increments with the minimum possibi lity that the test itself be destroyed by a memory malfunction, and to test
memory from minimum to maximum configuration. HRI binary is supplied as an aid to loading the program
with a minimum functioning hardware requirement.
At the completion of program load, the memory sizing routine determines if the area the
program has been loaded into is 4K or 8K, and adjusts addressing constants if only 4K and Checkerboard
is started. If 8K, EXTEND mode is tested and if a 0, the Checkerboard is started. If EXTEND mode is
on, the program determines extended memory size and makes two JMP modifications to the basic Checkerboard so that the extended memory test wi II be moved out of the way and back again wh ile the first 4K of
memory is being tested.

Maindec 702 R
Page 4
Memory is exercised in 4096 word increments. Each 4K of memory is fully tested before the
test proceeds to the next 4K. A total of four patterns and their complement patterns are generated, exercised, and tested in each 4K before proceeding to the next 4K.
6. 1 . 1

Pattern Description

The Extended Checkerboard generates and exercises four basic patterns and their complement
patterns. These patterns would appear in a bit plane as follows:
Pattern 1:

o1 2 3
o
y

100

o1 1 0
o1 10

1 0 0 1

o1 2 3
o1 1 0

1
2
3

1 0 0 1
1 0 0 1
o1 10

Pattern 2:

o1 2 3

o
y

1
2
3

1 0 0 1
1 0 0 1
o1 1 0
o1 1 0

o
y

1
2
3

Pattern 3:

1
2

1 1 0 0
1 1 0 0
o0 1 1
o0 1 1

o 1 2 3
o
y

1
2
3

Pattern 4:

1
2
3

1 0 0

o0 1 1
o0 1 1
1 1 0 0

o0 1 1
o0 1 1
1 1 0 0
1 1 0 0

x
o12 3
o0 1 1

1
2
3

1 1 0 0
1 1 0 0
o0 1 1

o1 2 3
o

1 0 0 1
1 0 0 1

o1 2 3
o

010
o1 1 0

These patterns are generated by a common routine that produces them by using a different
18-bit control word for each pattern. Bit 0 to bit 15 of the control word generate 16 consecutive pattern
words. If a bit is a 0, a word of aliOs is written into the corresponding memory location; if a 1, a word
of a II ls is written. In bit 17 of the control word, a 1 indicates that the pattern complements on X addresses 100, 300, 500, and 700 (see patterns 1 and 2). In bit 17 of the control word, a 0 indicates that
the pattern complements on X addresses 000, 200, 400, and 600 (see patterns 3 and 4) .

Maindec 702 R
Page 5
The control words used to generate the patterns are as follows:

6.1.2

Pattern 1:

463145

Pattern 2:

631461

Pattern 3:

631460

Pattern 4:

463144

Test Description

Each of the four patterns and its complement pattern is exercised in the same manner. First,
the pattern is generated in the memory area being tested. Then, each memory location is individua lIy
read, complemented, read, and recomplemented to its origianl value so that the area being tested still
contains the entire pattern. The results of the second read are tested for all 1s or all Os. Then, the pattern is regenerated and each memory register is read; bit 17 is complemented, read, and recomplemented,
and the results of the second read are tested for all Os or all ls. The pattern is regenerated and bit 16 is
tested, then bit 15, and the process is repeated until bit 0 has been tested.
6.2

Applications

The Extended Checkerboard is designed for a minimum of manual intervention in completely
exercising all available memory. Most other applications require manual intervention and the changing
of the contents of specific memory locations.
Some of these applications can be accomplished as follows:
To Select a Single Pattern:
.To exercise memeory with only one of the four patterns it is necessary to change four memory locations so that they contain the same control word, i.e., all four memory locations should equal
463145 to exercise pattern 1 only.
Addresses

Current Contents

Pattern

0271
0272
0273
0274

463145
631461
631460
463144

One
Two
Three
Four

To Prevent Program from Relocating:
At times it may be desirable to exercise a single 4K memory module. In the case of a PDP-7
with only 4K of memory, one may want to only exercise addresses 0400 to 7777 or only addresses 0000 to
7377. Th is may be accompl ished by using one of the following two procedures.

NOTE: The first 4K of memory tested after program load is addresses 10000
to 17777, (or address 0400 to 7777 if only a 4K machine).

Maindec 702 R
Page 6
To lock the program into exercising only upper addresses:
Press STOP (immediately after loading).
Set ADDRESS switches to 0046, 20046, 40046, or 60046.
Set AC switches to 600020.
Press DEPOSIT (up).
Set AC switches to 000000.
Press START.
After testing the first area, the program relocates itself to starting address 10020 (or 7420 if
only 4K). This move can be detected by watching the PROGRAM COUNTER indicators. Bit 2 of the
PROGRAM COUNTER will light after the program has been relocated (or bits 3, 4, and 5 if only a 4K
machine) .
To lock the program into exercising address 00000 to 07777 (or to 7377 if the machine has
only 4K)
Load the Extended Checkerboard with all AC switches up.
Watch the PROGRAM COUNTER until the test has relocated itself.
Press STOP.
Set the ADDRESS switches to 10046, 30046, 50046, or 70046 (or if only a 4K mach ine to

07446) .
Set the AC switches to 610020 (or if only a 4K machine to 607420).
Press DEPOSIT (up).
Set AC switches to 000000.
Press START.
Since the Extended Checkerboard can be loaded into and run from extended memory by
loading with the EXTEND switch down, these procedures may be used to test any 4K of extended memory.

METHODS (Not Applicable)

FORMAT (Not Applicable)

EXECUTION TIME
Approximately 53 seconds for each 4096 words of memory .

Ma i ndec 702 R
Page 7
10.

PROGRAM

10. 1

Core Map (None)

10.2

Dimension List (None)

10.3

Macro, Parameter, and Variable Lists (None)

10.4

Program Listing

/ f..l f) P -

7 tIE MnRye HE. C K t, R BOA R 0 4 K 0 R 8 K A i\J 0 EXT E I\J 0 E 0 ME M0 R Y

dllCU''J

26~

I~L)L(JO,.J

l~H~"'>HU

20
32
247

CHt<:tiL..;
Ci\jTROL
celF IN 1
CUI..Dn~)

C ') MEMl)
I) M PEN LJ

~-l;HrKx
~-i\JULrH
~'

u llf~ K X

GE !\jPA I
GI:1PAI
Gr\jl Gnp
KCI\; T R
KCDUI\j "
KLFN1H
Kl~0

K100010

Kif>
t<.200
K37l

232

207
202
474
460
364
457
130
260
152
466
465
323
262
467
251

rJ:X ,'N tl

l) i\i

UP R cn·~
,..)AS\..)K
~ AT GE ;\j

PAr!. L)L:

')lTUP
STPrAIJ
':"vAUh)~

'--iIiLGTfi
:) V tvl S r I~
:) x. T I~ K x
IF.:SI
r S T E 1\11]

iS1LINK
,SlU~t-i
1

:-i X i ,\ ,J

',Ail \/ K '\
i" T i K \
I

?52

,.';"'R
lJ,.JC.( ,.JK'J

Mv L (J (H)

?53
322
324
470
464
263
242
243
267
442
471
472
473
427
24'5
271
45'5
100
103
46

NOEX

254

K400
K7400

1<.7777
LASTK~

l'1AnoP"
,'1 I N4

;'1LEN 1 H
!"I0V8AK
11 () V E K 1
'-1 iJ \l E K 2

f"iJVEK3
,"'1D\iEUP
MSKOUi
MS-i RP r
i1

v ,J MP S

11 It JMP 1
M\/JMP2

U~PSi

,\ I C1 r ~[
)\ ! h' nl ,J
CHKnlRIJ
C HK K L .)
IV, \I L () I i )
! '-)Tt.I\c)

65
375
265
270
244
261
236
2/7
276
255
256
240
462
104
60
246
;:>57
325
461
463
26 4
250
241
3/7

416

;"j I} ,J 1"1

IJ I. f)(1 ,-)
P1

20
32
46
60
65
100

M\lJ'1F2

103

I ~. S 1

104
130
152
202
207
232

l; E IV fJ A I

l;i\J1 ,OJ n,..J
C()i"t:tvI]
COl, Gll.,
c: lJ F I [\ j
t-'ATU'~

2:36

SV~,ST~

240

0PkSl'~

241

1'1AQr)R";

242
2 4:~

:~ 11\; 4

~A~'-i'"

244

Ylt..;!-:'J\' i

?4~

i ') I

~'"

l: t\i T ~ U
I 1 '-}

r;; ;::> F~

K 1 f.

0.200
.( 377
LH x
i

24h
241

2;;(1
2:;1
252
255

?S4

..; IJ A :.1 h' ..;

2tj'j

~ 'J 1_ (~ 1 H

?'5h

! :-; T II P,~

257

I.; l I ,J A i
,.J A', (;f "J
,\10.0

260

261
262

',"'ih'

2 6~~

IjfJf.(

264
26:'

u!~ F

r-ll " C i);J

26h

r"'1l. F iJ 1 Ii

267
270
271
27 f277

UP f< C Cl·~
i': S 1 ~ p

-.:; I h' T A·)

::-; E T UF-'
K400

5~;:>

K L E '\J 1 '1

32~

K74ft)((:

i ~\!l " l'\ "
A ~f K '\

324
325
364
375
377
416
427
442
455
457
460
461
462
4(,3
464

KC11 (il\' :

46~

S): I r'iJ
1H
i\J U X i I\i:)
!

~ ,\j D l.

;.. r Ii r '-., r
x. : ~-: I} L ,)
;"1 U Ii r_ll r>
1"1 () \/ R A f\
i"~ \I J ~1 P :.;

.. 'J i !,~ f<' \

i': (; f1 I K, "
I Y'i I \1 r. l(,
~ X. 1 ,'.I f\X

Ma indec 702 R
Page 8

KCNTR
K10000
K7777
MOVEKl
MOVEK2
MOVEK3
OMPENO

466
467
470
471
472
473
474

/POP-7 MEMORY CHECKERBOARD 4K OR 8K AND EXTENDED MEMORY
20/
CHKRBO,

CHKRLP,

LAC.
LAC STRTAO
DAC MADDRS
LAS
CMA
DAC MSKOUT
LAC MIN4
OAC PASSK
LAC PATLOC
OAC GETPAl
LAC I GETPAT
OAC CI\ITROL
JMS TEST
IS~ GETPAf
IS~ PASSK
JMP CHKRLP
O~M MSKOUr
n~M NOEX
LAC CHK~BO
[JAC GETPAr

/MOVE THE PROGRAM
XOR
DAC
MIJlOOP,
LAC
AND
SAD
JMP
LAC
XOR

TSTENL1,

IGET REGION StAt
ITO START TESTING

/-4

ITO COUNT PATTERNS

Iro GET PATTERNS
/GET NEXT CHECKER80ARO
/FOR GENERATING
ITEST CURRENT REGION
IOONE ALL 4 CHECKER80A~OS
INO, DO NEXT

IGET SA OF THIS PROGRAM
IFOR I NO I RECTS

TO rEST MEMORY Nor TESTED ON THE LAST PASS
UPRPRO
ICHANGE StAt TO NEXT TEST
SVADRS
IFOR INOIRECTS
I GETPAT
IGET NEXT INSTR
OPRCON
1740000
OPRCON
lIS IT AN OPERATIVE INSTR
TSTEND
IMAYBE
1 GETPAT
UPRPRO
/CHANGE ADDRESS OF REF.

OAC 1 SvADRS
IS~ SVAORS
ISt GETPAT
JMP MVLOOP
LAC I GETPAT
DAC I SVAORS
CMA
S~A

.)MP TSTEND-3

IADVANCE
IADDRESSES
ISTORE OPERATIVE GROUP
IDELIMITER
INO

Maindec 702 R
Page 9

NOLnCJ0,

lS~

GETF>Af

JSt SVAORS
LAC I GETPAf
DAC I SVADRS

IGEl NEXT CONSTANT

CMA
S~A
.jMP

CLA-OPR
NDLOOP

JS~ SVADRS
DAC I SVADf~S
~~ AD MAODRS
SKP

11 VJMP 1,

fvlV J 1"1 P·2 ,

ICf):-'jl\!lcr

r [S T,

,j MP
1 ISTLWR
LAC lJPRSTK
flAC 1 SVADRS

JMP

TSTUPR

SllBROl' fINES

12ND DELIMI fER

INO
IADVANCE FOR STORE S.A.
IMAKE SA=LWR START
ITHIS TEST TESTING LWR
IYES, NEXT PASS TEST UPR
IHAVE EXTENDED MEMOKY
IGO TEST LWR MEMORY OR JMP MOVEUP
IMAKE S.A.

= UPR START

IGO TEST UPPER MEMORY OR JMP MOV~AK
IMOVE EXTENDED CHECKER8D BACK

FORM TEST

P
,)MS GENPAr
CLA CMA- O')R
[lAC 8 [ TCOI\!
,JMS COMEML)
1_ AC Of\JE
OAC R J TCO:"
JMS Gr~NPAI
JMS COMEMd
LAC B I TCOI\J
eLL RAL-OtJK
f1AC B I TCOI'J
stA
.)MP .-6
LAC MIN4
xOR I GET~AT
SAD CI\iTROI_
.)MP I TES!"
f1AC C:'~TROL
,IMP T[ST+1
,j.t>1

IGENERATE PATTERN
ICOMPLIMENT WHOLE WORDS
ICOMPL I ME:\IT AND COMPAR~
ICOMPLIMENT SINGLE BITb
IGENERAfr
ICOMPLIMENT AND COMPARt
INEXT BIT
IDONE ALL
I f ES r NEXT BIT
IDONE COMPLIMENT
lyES

IPATTERN GENERAl ION VARIABLE LENGTH
lAND PA1TERN C0NTROLLED BY INITIAL
ICONTENTS OF cn~TROL
GENPA 1-,

JMP
LAC
OAC
RAR
LAC

.
CNTROL
SVMSTK
Kll2ll2l

SI\JL

CLA
[JAC LwR
TAD K212l0
OAC Ui-'R

IGEf MASTER PATTERN WORD

PATTE~N

Me i ndec 702 R
Page 10

LAC
DAC
LAC
DAC

GNLOOP,

MADDRS
SVADRS
MLENTH
SVLGTH

ISAVE STARTING ADDRESS
INUMBER OF WORDS

LAC K16
DAC NDEX
LAC SVMSTR
DAC PATGEN
LAC PATGEN
ClL RAL-OPR
DAC PATGEN
StL CLA-OPR

1-16 DECIMAL

CMA
AND MSKOUT
DAC I SvAORS
lSi! SVADRS
1St SVLGTH
SKP
,JMP I GE.NPAT
ISr NOEX
JMP GNLOOP

INO
IClR NOT SELECT

LAC SVAORS
AND K377
SAO l\oJR
JI"1P

• +4

SAO UPR
SKP
JMP

GNLOOP-4
LAC SVMSTR
CMA
OAC SVMSTR
JMP GNLOOP-4

IRESET FOR PATTERN
INEXT BIT TO LINK
ISAVE REST
ISHOULD NEXT WORD = 0

IGENERATE NEXT ADDRESS
100NE WHOLt PATTERN
IEXIT
IDONE 16 WORDS
INO
ICLR NEXT ADDRS TO LWR 8

IIF = (21
lOR = 21210
ICOMPLIMENT MASTER PAT

100 NExr 200

ICGMPARl MEMORY FOR FAILURE
COMEMU,

COLOOP,

JMP

LAC MADORS
[lAC SVAOR~
LAC MLENTH
OAC SVLGTH
LAC BITCON
XOR I SVADRS
GAC I SVADRS
LAC BlTCON
XOR 1 SVADRS
OAC I SVAORS

ISAVE STARTING ADDRESS
ISAVE LENGTH

AND MSKOUT
S2A

ICLR NOT SELECTED BITS
IIF -

CMA
AND MSKOUT
SNA
•.JMP COFINI

IMAKE +
IClR AGAIN
IRESULT SHOULD BE

(21

Ma indec 702 R
Page 11

eMA
AND MSKour
f1LT
LAC SIJADR"i

IOISPLAY FAiLED BIT 8S'

HLT

LAC CN1ROL
HL T
COF IN 1,

SvADRS
rSf SI/LGTH
JMP C()LOOP
J"1P I COMEMO

IOISPLAY PATTERN CON,WORD

IS~

IDO ALL

INa

MSTRPI

NUT C H A l\j GE 0 B Y M0 V I N G r HE PRO GRAM
IAf\IL) 'EMP SfORF Rt.:GlSTERS

ICC "J ~ fAN T S

I AM

liD GENERATE PATTERNS
I':>, A. TO TEST LlPR MEM

~)Vtv!')TK ,
'I f} H C; 1 ti ,

IrEMP STaR ClJRRENT RE:.GION

1'1 A [HJ R S •
j'1

I 1\14,

777774

r->A~SK.

;.15 k OU i •

i ~ T I \'Jli •

10000+CHK~8o

C I'! 1 ~? I)

~Wf.; Pr{l),

10000

~lf,

777760

t\ 2r' 0.
r\ 3 7 7,

?0(lI

\It) Fl(.

:~ 77

SVAIJRS,

'-; \/ L G r H ,

o
Cf1KR8D

lSILJP'~,

GE1PA1,
~ ATGF i'~,

(i1

"'100.

100

i_ ",I h •

UPR,

Ol\!t.
H l 'i C () 1\1 ,

,"1t.E I\lTH,

[)PRCON,
'-15 TRP 1 ,

srRTAD,

IDELIMITER

1-4

Iro COUNT PATTERNS
ITO NOT COMPARE BITS
ITO START TEST ON LowER
Iro STORE CURRENT PATTERN
IMASK TO MovE PROGRAM
Ira COUNT WORDS IN GENPAT
ITO FORM 200 OR 300
ITO MASK ADDRESSES
IFOR COUNTING
IFOR 1NO I RECTS
ITO COUNT MEM LENGTH
ITO START TES1 ON UPR
IFOR INDIRECTS
IUSED IN GENERATING
ITO FORM 100 AND 300
1= 0 OR 100
1= 200 OR 300

770000
740000
463145
631461
631460
463144

ILENGTH OF MEM TO

T~ST

IGENERATE
IGENERATE
IGENERATE
IGENERATE

LAM

IOELIMITER

PATTERN
PATTERN
PATTERN
PATTERN

2
3
4

Maindec 702 R
Page 12

ITEST MEMORY LF.:NGTH AND ADJUST
ITEST CONST A~ns IF ONLY 4K
SETUP,

CAF
DtM
CLA
DAC
SAD
"IMP
SlM
JMP
JMP
LAC

7777
CMA-OPR
17777
7777
• +4

14K

CHKRBlJ
TSXTND
K400

18K, SEE IF MEMORY IS
ICHANGE CONSTANTS

DAC STRfAD
DAC UPRST~

lIS HEM 4K OR 8K

ITO TEST 4K MACHINE

LAC KLENTH
DAC MLENTH
LAC
oAC
TAD
DAC
t<:400,
~LFi\JTH,

K7400,

K7412Jf2)
UPRPRO
TSTUPR
TSTlWR

"JMP CHKRBO
400
770400
7400

14K - 400
IMOvE

lEx rE:'JDED MEMORY CHECKERBOARD

IDEfERMINE
TSXTNO,

MEMm~Y

LENGTH

CLA
oAC 7777
DAC 17777
DAC KCOUNl
C~1 A
EEM
DAC I FOURKX
SAD 7777
..)MP NOXfND
1St KCOUNT
OAC I EGHTKX
SAD 17777
..JMP FNoLTH
IS~ KCOUNT
nAC 1 TWLVKX
SAO 7777
JMP FNoLTH
IS~ KCOUNT
DAC I SXTNKX
SAO 17777
JMP FNDLTH
CLA
IS~ KCOUNT

IINDICATE EXTENDED 4K
112K MACHINE (EXTRA 4K)
IINDICATE EXTENDED 8K

116K MACHINE (EXTRA 8K)
IINDICATE EXTENDED 12K
120K MACHINE (EXTRA 12K)

IINoICATE EXTENDED 16K

~XTENDEO

Ma i ndec 702 R

'Page 13

DtM
SAD
JMP
ISt
ntM
SAD
JMP
ISr.
FNDLTH,

CLA
TAD
CMA
DAC
LAC
DAC
LAC
nAC

I TWTYKX
I FOURKX

FNDLTH
KCOUNT
I LAsrKX
I EGHTKX
FNOLTH
KCOUNT

124K MACHINE (EXTRA 16K)

128K MACHINE (EXTRA 20K)
IINDICATE 32K OF CORE

CMA-OPR
KCOUNT

IMAKE 2'S COMPLIMENT
KCOUNT
IOF 4K EXTENDED MODULES
MVJMPS
MVJMPl
MVJMPS+l
MVJMP2
.)M P CHKR8D
I\JU:xlND,
LEM
ICLEAR EXTEND MODE
-.IMP CHKR80
INO EXTENDED MEMORY
XTOTST,
LAC KGOUNr
[JAG KeNf R
LAC K10000
DAC MADDRS
LAG MADDRS
TAD K7777
DAC MADORS
IGENERATE S.A. FOR
1St MADORS
INEXT 4K MODULE
I. AC MIN4
ITO TEST
nAG PASSK
LAC PATLOC
DAC GETPAr
LAS
CMA
(JAG MSKOU'
xri\lDLrJ,
LAC I GETPAT
DAC CNTROl
JMS TEST
ISr. GE.TPAT
l~r PASSK
JMP XTNOLP
1St KCN1R
100NE ALL EXTENOEU
JMP XTDTST+4
INO, DO NEXT 4K
JMP CHKRBD
IYES, TEST 10000 TO 17777
IMOVE THE EXTE~OED MEMORY CHECKERBOARD
IOUI OF THE wAY TU TEST BLOCK 0000 TO 7777
MOVEUP,

LAC MOVEK1
DAC 10
~G MOVEK2
oAG 11
LAC MOVEK3
GAC SVLGTH
LAC I 10
oAC I 11
1St SVLGTH

JMP .-3
JMP I TSTLWR

Ma i ndec 702 R
Page 14
IMOVE THE EXTENDED MEMORY CHECKERBOARD
IBACK TO FIRST 4K
MOVBAK,

LAC
DAC
LAC
DAC
LAC
DAC
LAC
DAC

MOVEK2+10000
10
MOVEK1+10000

IS~

JMP
JMP

SVLGTH+10000
• -3+10000
XTDTST

MVJMPS,

,-JMP
,jMP

MOVE UP
MOV8AK

F'UIJRK X
EGHTKX,
TWLVKX,
SXTNKX,
rWTYKX,

27777
37777
47777
57777
67777
77777

LASTK'(,
KCOUN1,

MOVEK3+10000
SVLGTH+10000
I 10
I 11

KCI\jTR,

(II

K10000.

10000

K7777,

7777

0VEK1,
MOVEK2,
MOVEK3,

xrOTST ... 1
XfOTST+7777

!)MPENO,

,H~P

,v1

::,TART

ITHIS ROUTINE IS
IEXECUTED OUT
IOF 2ND 4K OF
INOT EXTENDED
IMEMORY

-~'H)\IEK3+XTDTST

Sr.:: T uP

ITO GET TO FIRST 4K EXT£NUED
IDITTO 2ND 4K EXTENDED
13RD
14TH
15TH
16TH, OR 32K

Maindec 702 R
Page 15
Octal Dump

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Maindec 702 R
Page 16
00173
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00226
00227
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00231
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Ma i ndec 702 R
Page 17
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