Digital PDFs

XX-19AA1-16

1962

399 pages

Original

37MB

Document:	F-47 PDP4maintMan 19
Order Number:	XX-19AA1-16
Revision:
Pages:	399
Original Filename:	http://bitsavers.org/pdf/dec/pdp4/F-47_PDP4maintMan_1962.pdf

OCR Text

PROGRAMMED
DATA PROCESSOR-4
MAINTENANCE MANUAL

Technical Bulletin F-47

DIGITAL EQUIPMENT CORPORATION

•

MAYNARD, MASSACHUSETTS

ICOPY NO.

This manual contains proprietary information. It is provided tothe customers of Digital Equipment Corporation to help them properly use and
maintain DEC equipment. Reveal ing the contents to any person or
organization for any other purpose is prohibited.

TABLE OF CONTENTS

Paragraph

Page
list of Illustrations ..............................

xiii

List of Tables. . . . . . . . • • . . . . . • . . . . . . . • • . . . . . . • • . .

xvii

CHAPTER 1
INTRODUCTION

1-1

Purpose and Scope .•......•.....•...•.•..........

1·-2

Chapter Subjects .........

1-3

Fi gu res 0.................... 0. . . 0............ .

•••

•••••••••••••••••

1-1
1-1
1-2

CHAPTER 2
GENERAL DESCRIPTION

2-1

Purpose of System ....•

2-2

Standard Equipment ...•

2-3

Equipment Options .....•..

2-4

System Operating Specifications ............•.•..

2-3

2-5

Physical Characteristics ...••.•............•.••.

2-4

2-6

Power Requ i rements .•..

2-6

2-7

Equipment Listing .............

•••••••••••••••••••••••

•

•••••••••••••••••••

•••••

•••••••••••••

•••••••••••••••••••••••

••••••••••••••••

2-1
2-2
2-2

2-6

Bays

•••••••

2-6

Logic Panels and Power Equipment ..•.... 0.'

2-7

Modu Ie List ......

2-9

()

••

•

eel)

••••••••••••••••

CHAPTER 3
INSTALLATION

3-1

Genera I .•.

3-2

Installation of Standard Computer ............
a

••

•••••

Site Selection ..•

•

•••••••••••••••

•••••

iii

••••

••••••

•••

••••••••••••

3-1
3-1
3-1

Page

Paragraph

3-3

3-4

Unpacking and Handling •.••.•

Installation of Tape Reader .••.•.•...•••....

3-2

••••••••••••

Installation of Optional Equipment ..•....•••.•..

3~3

3-3

•

Reader and Punch ..••••••••..•..•.•.•••.••

3-3

Keyboard/Printer ••••••.•

3-5

••••••••••••••

•

3-5

Inspection and Adjustment ••..•••••.•..•..•••.••.
a

Visual Inspection •.•....•.•..

Meter Readings •••...•.....

Preoperationa I Checkout ...•...•

3-5

••••

3-6

•••••••••••

•••••••••

••••••••••

3-6

CHAPTER 4
SYSTEM FUNCTION

4-1

4-2 '"

Logical Organization ..••....•••..•.•

4-4

•••

Control Unit ....

Arithmetic Unit ..

Memory ...•.•..•......•.•.•.•.•.•.

Input-Output System .....•

Programming~.

000.4

••

••••••••••••••••••

••••

4-1

•••••

4-1

•

4-2

•••••

4-3

•

••

4-3

•••

4-4

•••••••••••••••••••••

a, Number System .....

4-3

0.0.

••••

Instruction Form'at .••...

,Computer States ...••..

d
e

•••

••

0.0

'• • • •

•••••

•••

4-4

•••

•••••••••

4-5

•••

• • • • • • • • •'

••

'D" • • • • •

4-7

Console Control

0000.8110lloooooooUO,,0000800

4-8

Instruction List

•• ooo.oo • • • • • • ct.o • • • • •

4-10

0000111000.000.0.00,&

4-20

Control, ,

01&0000

•••••••

00.0

••••

••

4-20

0000

4-21

••••••

4-22

•••••••••

4-23

••••••••••

4-24

••

4-25

Timing System ....•.•.

State Control

Program Control •..••••....••.•••.•

Logic Symbols~ ..

Transfer Logic ••..•••••••...••

Arithmetic Unit

•••••

•••

••••••••••••••••

0.0.000_00

••

••••••••••••••

00.8

••

000

•••

&0.0

••

•••••

••••

0".

Paragraph
a

Acc::umu lotor

b Lin k
c
4-5

4-6

C!)

e. II) .0

•••••

•

•••

••

•

••

Arithmetic Unit Control
,I

Memo~y

•

0 . 0 ,,0.

0.0

iii

coo coo

e. 0

Memory Ad.dress Register •..

Memory Buffer

'Memory Modu Ie

Input-Qutput Sy~tem

00.

•••

•••••

o· • • • • • • • • •

4-25
4-26

e o . co

•

...

••••••••

•

4-28

•••••

Re.ader Contro I . ~

Pu nc h Con tro' Type 75 .

•••.

•

•••••••••••••••

4-30

••••

4-31

••••

•

••••

•

4-7

F,low Charts

4-8

Computer Operations ............

4-9

••

•

••

o. •

••

4-28

••••••••••••

d ,Keyboard/Printer Control Ty,pe 65 ........ .
0

4-27

e ••••••••••

• • • '.

4-27

4-28

Real Time Option Type 25

•

4-26

o. ' .•••••••••••••••••••• ,

4-26

4-31

•

e' • • •

••••••••

4-32

•

4-35

•

•••••••

Special Pulse GperatiQns .. 0' • • • • • • • • • • • • •

4-35

Memory Cycle.

4-35

Major States

•••••••••••••

4-36

In-out Transfers ...

••••••••••••••••••

4-37

••••••••••••••••••••••

4-41

Use of Drawings

•

••••••••

•••

•

••

•••

•

••••••

CHAPTER 5
OPERATING PROCEDURES

5-1

General

5-1

5-2

Consqle Controls and Indicators ................ .

5-1

5-3

Reg i.s ters

State Indicators ..•

Operating Switches.

Operating Keys

•

•••••••••

••

000.00.0

••

Power COlJtro Is andlndi cators .
a

•••••••••••••

••••••

•••••••

••

•

•••••••••••

•

•••••••••••

••••••

Power Control Panel Type 813 0 0 . ' . , • • • • • • •

5-2

5-3

5-4
5-5
5-6
5-6

Paragraph

.E Marginal Check Controls ••
5-4

5-5

5-6

Operation of In-out Equipment

•

••

•

5-7

••••••

5-8

••••

••••••••

•

Photoelectric Tape Reader .•••.

••

•••

5-8

Pape r Tape Pu nc h

•

5-9

Teletype Keyboard/Printer .•••.

••••••••••

•

Computer Operation •.•.

•

••••••••••••••

•

•••••••

5-10
5-13

Manual Loading ..•....•.....••..•••••..•

5~13

Norma I Operation .•.

5-14

•••••••••••••••••••

5=14

Manual loader ..•.•.••...••••.••..••••.•

5-14

Norma I Mode ..••....•.•

•••••••••••••••

5-16

Manual Modes .••.•..........••.••••.••••

5-16

Repeat Mode.

5-17

OperatorRs Check I ists .....•..•••.•••...••••••

•

GOO

••••

CHAPTER '6
CONTROL

6-1

General

6-1

6-2

Genera I Contro I Functions ..•••.•.•. ~ .••.••..••

6-1

6-3

6-4

Console Control ..•..•.....••••.••••.•.•

6-1

Special Pulses .•.••••

•••••••

6·~3

Time Pu Ises •...

6-4

Run Control •..•.••..•..••.••••••••...•.

6-5

Ma i0 r 5ta tes

CO"

Fetch

Execute a •

Defe roo

Brea kG"

••••••••

0.0

••••••

•••••

•

f;)

I!J

•

6=6

eo •

(10

til

•

6=6

•

til

coo

•

()

••••

•

6-7

GOO.

til

•

••

•

••

•

t;1

•

6-7

'I)

•

6-7

Instruction Control (Minor States) ...•...••.•..•.

6-8

Instruction Register.

Instruction Decoder •••..••••..•••

•••••••••••••••••••

6-8
6· 9
u

••

•••

Page

Paragraph
,c

6-5

In-out lransfer Control

Prog ram Con tro I •.

•••

••••

Program Counter .•,

Program. Count Logic .•

•

c ,Program Transfer Logic

••

","

••

•

.'.

it •

••••

000

•••••••••••

0' • • • • • • • • •

••

••••••••

••••••••••••••••

OOOCl~_.OOO.O.4i'.OO"

••

6-10
6-11
6-11
6-11
6-12

CHAPTER 7
ARITHMETIC ,UN IT

7-1

Genera I' '".

7-2

Accumu lator

•

a e •

lit

•

~ • .'"

eo e

e e

Transfer Gates .

Rotate' Gates

Logi c Gates

Arithmeti c Gates

eo • •

e •."; •

e •• e •••

••

•

~ e •

•

eo.

•

III

••••" ••••••••••••••••••••

••••••••••

•

.~ " '"

•.

•••

•••••••••••

•

e • • • • eo • • • •

()

••

•••••••••••••••••

t!l

•

7-3

Link ..•.••.••••.•• o • • • ~' • • • • o • • • • • • • • • • • • • • • •

7-4

Addition Algorithm

7-5

.. ~' •••

••••

•••••••••••••••

7-1
7-1
7-2

7-3
7-4
7-5
7-7
7-8

Ones Complement Addition

7-8

Twos Complement Addition

7-8

Arithmetic Unit Control ........................ .

7-14

Accumu lator Decoder •••.••••••••.••••...

7-14

Operate Logic

7-15

Transfer Logi co ..••••••••.••••••.•..••..

7-16

Arithmetic Logic ..•.••••..•••.•• ~ ..•••..

7-16

Overflow Logic ..

7-19

oo • • @u • • • • • • • • • • • • • • • • •

CHAPTER 8
MEMORY

8-1

Genera I ••

8-2

Memory Address Logi c •...•..•••..•.

••

•••

•

...............

•••••••

••••••••••

Memory Address Register

Address Transfer Log i c .•..•.........•....

vii

••••••••••••••••

8-1
8-1
8-2
8-2

Paragraph
Memory Address Decoders .•.•..••....•...

8-3

Memory Data Transfers ....................... .

8-5

..:

8-3

8-4

Memory Buffer ........................

8-6

Data Transfer Logic .................•...

8-7

Index Logic ................•...........

8-8

Core Memory Logic ....•.....•.......•........

8-8

Memory Control •.•.•.............•.••.•

8-9

Core Bank .....•...•...................

8-10

X and Y Selection ...........•..••.••..•

8,- t 1

Memory Timing Functions .......•..•....•'

8-'13

Read and Write Drivers ................. .

8-15

Read Sensing

8-15

Write Inhibit Driving .............

••••••••

•••••••••••••••••

•••••

8-16

CHAPTER 9
INPUT-OUTPUT SYSTEM

9-1

General

9-2

Real Time Option Type 25 . "'"

9-3

...

•

It I"

•

•••

••••••

....

•

•••

9-1

9-1
9-1

Device Selection ............

Information Distribution ..............•..

9-2

Information Collection ........

9-2

Interrupt Logi c ..

In-out Skip Logic •..............•....•..

9-5

Reader Contra 10 ••••••••••••••••••••••••••••••

9-5

••••••••••

•••••••••

••••••••••••••••

•••••

9-3

Reader Buffer .•........................

9-5

Contra I Logic ...............•.•••...•..

9-6

9-4

Punch Control Type 75 ...............

9-5

Keyboard/Printer Control Type 65 .......•.•....

9-9

•••••••

9-8

Timing

'f.

9-11

Output Logic .•..........•....•.....•..

9-'12

••

••••••

viii

••

0."

••••

IIJ

•••

II.

Paragraph
c

Input Log,ic

III

1:1

9-15

•

•••

••

.....

CHAPTER 10
CIRCUIT DESCRIPTION
10-1

General

10-2

Inverters

10-3

10-4

10-1
0

•

•••••••••••••

••••••••

10-1
10-2

Inverter 1103R .........

Inverter 1104 ..•........................

10-3

Inverter 4 102R .

•••••••••••••

10-3

..d

Inverter 4105

••••••••••••••••

10-3

Inverter 4106 ...

•

••••••••

10-3

Inverter 4106R

•••••••••••••••

10-3

Diodes

••

•

••••

••

••••••••••••••••

•••.•••••

••••

••

•

•••••••

10-3

••••••••••••••

10-4

•

••

•

•••

••

o·

•

•••••••••••••••

••

Diode 4111

Diode 4112 ..

Diode 4112R

Diode4·113.0 ..

Diodes 4113R and 4113X 0... 0

Diode 4114

.§!

Diode 4114R . 00. 00.

Diode 4115R ....

00o

0.00.0

.•

•

•••

••

•

••••••

•••••••••••••••

0......... .

•••

•••••

•••••••••••••••••••

10-4
10-5
10-5
10-5
10-6

••••••••••••

10-6

0........ .

10-6

Bi nary-to-octa I Decoder 4105 ........... .

10-6

•

••••

•••••••••

Capacitor-Diode Gates .. 0

••••••••••••••••••

10-8
10-8

Negative Capacitor-Diode Gate 4127.•

Negative Capacitor-Diode Gate 4127R ... .

10-9

Positive Capacitor-Diode Gate 4128 ...... .

10-9

.sL

Negative Capacitor-Diode Gate 4129 .0 •.•

10-11

Negative Capacitor-Diode Gates 4129R
and 4129X

10-11

10-5

••

•

•••

Flip-flops
0
a Flip-flop 1213
0

••

£ Flip-flop 4203

•

oooooo.no

••

••••

•••

••••

0
o

•••

•

•••••

•••••••••••

••••••••

10-11
10-12
10-14

Page

10-7

10-8

10-9

Fi i p-flop 4204 .•....•••••..••••••.•......

10=17

FHp-flop 4204X .•

10~18

Flip-flop 4214 •...•.•.•.•.••.••...•.....

10-19

Four-bit Counte," 4215 1 • • • • • • • • • • • • • • • • • • •

10-19

.§!

F~ip-flop 4216 .•.••...•.•.........•...•..

10-21' ".

Flip-flop·4218 .•.., ••.....•.......••..•..•

10~23·

Am p I if i e rs • • • • • • • • • • . '. • • • • • • • • • • • • • • • • ~ • • • • • • •

10-24

.....................

Pulse Amplifier 1607..•..•...••••.......•.

10~24

Pu Ise Ampl ifi er 4604 •..........•.•••••...

10-26

Pulse Amplifier 4605

...•...••.......••..

10~28

Pu !se Ampl ifier 4606

...•..........•..••.

10~29

Pulse Amplifier 4606R ..•....••...••.....•

10-29

Bus Driver 1690 ..••...•......•.•••.

10-30

[

Solenoid Driver 4681 ....•..•••

Memory Elements.

••••

•••••••••

••••••••••••••••••.••.•••••••••

10-30
10-31

Sense Amplifier 1538 ..•..•.•.•••

Sense Ampl ifier 1540 ••..•••.•••.•....•.•.

10-33

Read/Write Switch 1972 .•....•••...••.•.•

10-35

Memory Driver 1973 .......•.•••..•. ;. •••.•

10-36

Resistor Board 1976 •...••..•.••••••••..•••

10-37

Resistor Board 1978 •...........•.••••..•.

10-37

Inhibit Driver 1982. • ..••••• • • · .• • • .... • •• •

10-38

De lay Ci rcu its

••••••••••••••

••••••••

10-31

•••

••

•

10-38

•••

••••••

De Iay 13 10••.•.•...•..

•

10-39

Delay 1311 •.•.•••.•••.••••.••.•••......

10,-40

Delay 4301 ..••...•..••.•••.

•••••••••••

10-41

Integrating One-Shot 4303 ..••.••..•..••..

10-43

••••

Pulse Circuits .••..••....•••.••...•••....

•••••

10-45

Clock 4401 .•.•...•••....•••..••.••••..•

10-46

Clock 4407 ..•••..••••.

1OL~48

Pu Ise Generator 4410 •...•.•.••

••••••••••••••••

••••••••••

10-49

" ~

Paragraph

10-10

Plug Adapters
1956 and 1956R
,

10-11

Power Suppl i es .

•••

10-50

•••••••••••••••

10-51

•

••

••••••

••

••••••

Power Supply 728

Variable Power Supply 734 ...

.£

Power Supply 735 ~

~ower Supply Control

Power Contro~ 813

•••

10-51

••••••••••••

10-52

••••

••

10-53

••

0000

10-54

•••••••••••••

00.0

10-56

11-1

'1701

000000

•••••

••

.0.0

•

CHAPTER 11
MAINTENANCE

11-1

Special Tools and Test Equipment.

11-2

Equipment Layout and Wiringo .

11-3

Logs

11-4

Adjustment and Calibration o .

11-5

11-6

•••••

••

••••••

•••

••••••

•

••

00.

•

••

Adjustable Timing Circuits

Power Supp! ies

.£

Sense Ampl Hi ers

Tape Reader Amplifiers

••

•

•••

11-2

••••

.11-3

••

11-7

••

11-7

•

••

11-8

•••

•

••

•••

••

•••

•

••••

••

11-10

000

••

•

•••

••••••••

11-12

••••••••

•

Recommended Spare Parts.

••••

•••••

11-14

ModuleSparesooooo.~.oo"'o, ... "o.", .. ",

11-14

In-out Device Spare Parts.

11-17

Circuit Component Spares

Mechanical Spares

Preventive Mauntenance

•••

•

••••

0' • • • • • • • • •

•••••••••••••

••••••••••

•

•••••

••••••

•••

••

Every Day (OperatorOs Maintenance) ......

Every Week

Every Month

Every Six Months "

11-24

••••••••

11-26

••••••••

•

•••••••••

••

••••••••••

•••

000

••••••••••••••••••

11-8

Maintenance', ,Programs .. "

••

11-23

••••••

11-22

•

11-21

Operator's MOHntenance

••

•

11-7

11-19

•••••••

•••••••••

11-27
11-27

11-29

Paragraph

11-9

11-10

11-11

PDP-4 library Program Guides ....

•••

11-30

Use of Marginal Check •.•.••...••....•••..

11-31

log En tr i es

eo.

•

Troubleshooting ....••......•

•••••

•

•••••••••••••••••••

•

eo • •

•

eo.

11-33
11-34

Initial Investigation ....•.•••...•.......•.•

11-35

Preliminary Check..•.•

11-36

Console Troubleshooting ...........•..

Logic Troubleshooting .....

Testing After Repair .........•.....

Maintenance Record Entries ...•.............

Modu Ie Repa i r

•

••••••

•••

•••••••••••••••

••••

11-37

•••••••••••••••

11-42

••

••••

••••••••••••••••••••••

•

11-48
11 ~49
11-49

••••••••••••

11-50

•••••••••••••••

11-51

Component Replacement ..............•....

11-53

Drafting Number System •.....•...•.•......•..•.•

11-53

Remova I and Replacement ...•

Modu Ie Troubleshooting ..

•

•••••••

11-54

•••••••••

11-55

Document Type ....•....•......••.

Size Letter••.

Pro j'ect Numbers .....•..•...•...•....•

•••

11-56

Serio I or Customer Number ...•.......•.....

11-56

Assembly Number.

11-56

Subassembly Number ............••••..•••.

11-57

Revision Letter and Change Number .....•.

•

11-57

Format Examples ........•. ~

•••

11-58

•••••

•

xii

••••••••••

••••••••••••••••

••••••••••

••

L 1ST OF ILLUSTRAT IONS

2-,1

PDP-4 System Configur9tion ............

2-2

PDP-4 with Reader, Punch and Keyboard/Printer"

2-3

PDP-4 Logic ,Panels ..

2-4

Plenum poors, Bad;: Vie~ of PDP-4 Bays ..

2-5

Interior of Bay 2 .. , , .... , ....................

2-6

PDP-4 Layout Diagram ...........

•

'j,o

•

•••

•••••••••••••••••

A-2

A-6
A-8

•

•••

••

•

••

A-1Ll·

3-1

PDP-4 Top View. " ....................... , ..... .

A-·]8

4-1

PDP-4 Logical Organization ...

4-,2

Computer Memory Cycle ........ , .......

4-3

PDP-4 Logic Symbols .. " .................. " ....•.

A-2B

4-4

Transfer Logic" ...

A-30

4-5

Teletype Cv'~e Timing ...

4-6

Flow Chart: Internal Processor Operations.

4-7

Flow Chart: Input-Output Operations .. 0 . 0 ' ••• , •• ~

A-'3D

5-1

Operator Contro I Pane I ' .

1\-42

5--2

Power Control Panel Type 813 ' ..

5-3

Variable Power Supply Type 734 and Marginal Check
Switch Panel .... , .............

/1.-46

5-4

Marginal Check Toggle Switches on Mounting Panel,

A··48

5-5

Paper Tape Reader (mounted on punch cabinet) . , . , . "

A-50

5-6

Paper Tape Punch ...............

5-7

Keyboard/Printer, .................. , ..........,

6-1

Keys, Switches, Time, Run 0 ' • • • • • , • • • • • • • • •

6-2

States, In-out Transfer Control. ....

6,-3

Program Contro I .. " .... " '. ~ ...........

7-1

Link, Operate, Accumu lator 0-3

7-2

Accumu lator 4-17 " ,

••••••

•••••••

••••

••

•

•• "

•

••

•

•••

••••

•

••

A-34

••

A-,24

A-32

••

••••

A,- ! 2.

••••

A-IO

•••••

•••

A-54

•

••.

A··60

•

• • • • .,

•

••••.•• "

A-68

••

A-.J2

•••••••••••••••••••

x iii

•••••

•

••••••

•••••

•

•••••

••••

••

••••••••••

••••••••••••••••••••

0.'

•

Figure
8-1

Memory Address, Memory Control .....•..........

A-/o

8-2

Memory Buffer, Index Logi c ......•...•..••.•.•..

A-80

8-3

Core Register X and Y Selection ..•..••.•• · •• • · · ·

A-84

8-4

Memory: Timing, Inhibit Driving, Read Sensing. • · ·

A-B8

9-1

Devi ce Se Iector ............•......•...••....•.

A-92

9.-2

Information Distributor .....•.........•......•..

A-96

9-3

Informat ion Co II ec tor•....•.•..........••.......

A-100

9-4

Data, Clock and Program Interrrupt Logic, .
In-out Skip Logic .............•............

A-104

9-5

Reader Contro I .....•.............•............

A-108

9-6

Punch Control Type 75 ................•.....•..

A-112

9-7

Keyboard/Printer Control Type 65 ..•.....••.••.•

A-116

9-8

Timing Diagram: Outgoing Line Unit .........•..•

A-120

9-9

Timing Diagram: Incoming Line Unit ............ .

A-124

Power Supply 728
Variable Power Supply 734 .........•.....

••••••

A-128

Power Contro I 813 .•....•........••.•••........•

A-130

Power Supply 735

Inverter 1103
Inverter 1104 ....

A-132

Flip-flop 1213 ........................•........

A-134

••••••

............

..........

Delay 1310
Delay 1311 ..........................

•••••••••••

A-136

Sense Amplifier 1540 ...............•••..•......

A-138

Sense Ampl ifier 1538

Pu Ise Ampl ifier 1607
Bus Driver 1690 ...................... ., .... ., ... .

A-140

Power Supply Control 1701
Plug Adapter 1956 .......•......................
Read/Write Switch

XIV

A-142

Figure
Memory Driver 1973
Resistor Board 1976
Resistur Board 1978

A-146

Inhibit Driver 1982

A-"f48

Inverter 4102
A-150

Inverter 4105
Inverter 4106
Diode 4111 ....... ~ ...... ~ ..........

•

••

•

••

A-154

A-152

Diode 4112
Diode 4113 . '.................... , .......
Diode 4114
Di od n 4 115 ........ '... ~ ......

•••

•

•••

• •'

A-'156

•

••

•

A-,158

•••

Nega1"ive Capaci1'cl'-Diode Gate 4127
Positive Capacitor-Diode Ga'te 4128

••

Negative Capaci1'cr-Diode Gate 4129
Binary-to-octal Decoder 4150 ... , ....

Flip-flop 4203
Flip-flop 4204 .... " ..•......• , .

•••••

u ••

•

A-,162

Flip-flop 4214

A-164

Four-bit Counter 4215
Flip-flop 4216
F lip-flop 4218 •.•......

•••••••••

•••••

•

A-'168

••••

•

,A.,-, 170

••••••

Delay 4301
Integrating One-Shot 4303 ...

•

••

Clock 4401
Clock 4407 ............................
Pu Ise Generator 4410
Pulse Amplifier 4604 . 0 ' • • • • • • • • • • •

•••••

Pulse Amplifier 4605
Pulse Amplifier 4606 ....•......... , 0"

•• , , , , • , ,

Solenoid Driver 4681 .................... " .. ,.
xv

A-174
A·,176

Figure

11-1

PDP-4 Detailed Logic Layout .................... .

A-178

11-2

Modu Ie Layout, Standard Computer •••••••••••••••

A-182

11-3

Modu Ie Layou t, 0 pt iona I Equ i pment •••

A-186

11-4

Control Panet ••

11-5

Console Circuits .••

11-6

Cab Ie D·ragram •••••.••••.

11-7

AC and DC Wiring Diagram •..

11-8

System Modu Ie List ..••.•.••....•.••••• '. '..•.•

11-9

Correct Orientation for Loading Paper Tape ••..•.•.

••

•

••••

••••••••••••••••••••••••••••

•••••••••••

xvi

••••••••

*:'.,. ,••••

• • • • • • • • • • • • • • • • • •'

••••••••

••

•••

••••

••

A-190
A-194
A-200
A-204
A-208
A-210

L1ST OF TABLES

Table

4-1

Timing Chart: In-out Transfer Instructions •••••••••

4-39

5-1

Tel etype Code

5-12

8-1

Memory Tim i ng •

11-1

Sample Format: PDP tog

11-2

Nominal Values, Memory Read/Write and
Inh ib it Cu rren tso

•

•••••••••••••••

•

••

•

••••

•

••

•

•••

••••••••••

•••

••

8-14

••••

11-5

•

.....

11-10

••••

•

••••••••

11-16

11-3

Recommended Modu Ie Spares .•

11-4

Recommended Additional Modu Ie Spares ..••••••.••

11-17

11-5

Recommended Tape Reader Spares •••.•••••

11-6

Recommended Circuit Component Spares ••

11-7

Mechanical Spare Parts

11-8

Sample Exercise Loop

11-9

Sa!Tlple Diagnostic Loop

11-10

DEC Document Number Format, ................... .

11-53

11-11

Document Categori es .•

11-54

••

•

11-18

............

11-20

..................

11-22

•

••

.....

•

xvii

•

•••

.....

••••

I t . '• •

••

•

•••

•

••

•

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•

••••••••

•••••

••••••••••••

11-45
11-45

CHAPTER 1

INTRODUCTION

1-1

PURPOSE AND SCOPE

The purpose of this instruction manual is to aid personnel in the installation, operation and
maintenance of the DEC programmed data processor, PDP-4.

The manual contains complete

descriptions of all portions of the standard PDP-4, and also describes several optional additions
to the PDP-4 input-output system.

: ,

1-2 CHAPTER SUBJ ECTS
A brief summary of system use and appl ication is present~d in Chapter 2, General Description.
Th is chapter a Iso contai ns a I isting of system specifications and physi cal characteristics.
Chapter 3, Installation, provides instructions for initial installation and set-up of the system.
Chapter 4, System Function, provides a full functional desc'ription of all system operations.
This chapter is written at a block diagram level, and explains what the system does, rather
than the way in which its functions are implemented in terms of hardware. Also included in
Chapter 4 is an explanation of the flow diagrams which show the actual operations performed
by the computer in the execution of the various program instructions and console functions.
Chapter 5, Operating Procedures, explains the use of all controls and indicators on the computer control panels. This chapter also outlines the basic procedures to be followed for normal
computer operation.
Four chapters contain a detailed description of system logical design.

The first of these is

Chapter 6, Control, which covers the computer timing system, the control of computer states,
and program control. Chapter 7, Arithmetic Unit, is a detailed description of the accumulator
and the associated logic required for logical and arithmetic computer operations. Chapter 8,
Memory, covers the operation of the computer core memory system. Chapter 9, Input-Output
System, explains the control of the standard photoelectric tape reader, furnished with the
basic PDP-4. This chapter also describes three optional additions to the input-output system:

1-1

the real time option, the control unit for the paper tape punch, and the control unit for the
keyboard/printer.
Chapter 10, Circuit Description, explains the function, specifications, and theory of operation of the circuit modules used in the PDP-4 system 0
Chapter 11, Maintenance, contains information useful for the adjustment, cal ibration, troubleshooti ng and repa i r of the computer.

1-3 FI GURES

Th is manual incl udes three general classes of figures: logic diagrams, ci rcuit schemati cs, and
miscellaneous figures such as photographs and block diagrams 0 The complete system logic is
shown in logic drawings for Chapters 6, 7, 8 and 90

The circuit schematics accompany

Chapter 10. The block diagrqms and photographs illustrate Chapters 2,3,4,5,9 and 110
Also included in Chapter 11 are various layout drawings, and cabling and wiring diagrams.
All figures are assembled in numerical order at the back of the manual

Figure references to

all illustrations except the circuit schematics are of the form II Figure 5-1" (i .eo, the first
figure referred to in Chapter 5). This circuit schematics are arranged in order by circuit type
designation.

1-2

CHAPTER 2

GENERAL DESCRIPTION

2-1

PURPOSE OF SYSTEM

The DEC Programmed Data Processor -4 is a compact solid-state stored program digital computer. The PDP-4 is designed explicitly to bring to special purpose systems the flexibility,
economy, and reliability of a p~oduction model general purpose machine. The basic function
of the PDP-4 is to collect information from, and distribute information to a wide variety of
peripheral devices accordin,g to a predetermined set of instructions. The computer may also
be used to odvantage for many test and training appl ications.
The PDP-4 is a single address, general purpose computer, operating on 18-bit binary numbers.
A random access magnetic core memory with a complete cycle time of eight microseconds
achieves a computation rate of 62,500 additions per second. The computer can, with single
instructions, perform both ls complement and 2s complement addition.
The PDP-4 includes all essential elements for optimum performance as a systems component.
The standard machine consists of:
An Internal Processorl,which performs all computational operations, controls the memory, and
handles information entering and leaving the machine;
An Operator Console, which contains all controls needed to observe and modify the status of
the internal processor;
A 1024 or 4096 Word Memory, which provides storage for information being collected or distributed and instructions for the interna I processor; and
A Paper Tape Reader,which permits information and instructions to be read from five-, sevenor eight-hole perforated tape into the internal processor at the rate of 300 characters per
second.
A broad assortment of optional input-output equipment may be controlled by the computer
through the installation of a real time control. The PDP-4 is easy to install, operate and
maintain, since it runs on ordinary 60 cycle, 117 volt current, features simplified controls,
and contains built-in marginal checking to facilitate preventive maintenance. The standard

2-1

computer is housed in two DEC equipment frames.
ditioning is required
2-2

No special wiring, subflooring or air con-

STANDARD EQUIPMENT

The equipment included ~n the standard PDP-4 is shown above the horizontal bar in Figure 2~ 1

The internal processor contains both the control unit and the arithmetic unit.
The PDP-4 is avo'iiable in two standard froms, depending upon the size of the core memory

The core memory in the PDP-4A has a storage capacity of 1024 18-bit words. The 'core memo~y
in the PDP-4B has a storage capacity of 4096 18-bit words.

Instructions are carried out by the

control circuits in muhiples of the eight-microsecond memory cycle time. For e~ample', addu:
"

"'/t."

deposit, and load are two-cycle instructions requiring 16 microseconds. The control unit contains all of the registers and control circuits necessary to execute the various instructions in

the program.f' and to handle the transfer of information between memory and the registers with ... :
in the internal processoL
The arithmetic unit inciudes an accumulator, a link register, and the control circuits necessary
to execute all arithmetic and,logical operations. The link provides a one-bit extension to the
accumulator.

It greatly simplifies the programming of double precision arithmetic, and allows'

the construction of products and quotients in mu Itipl ication and division by subroutine.
The standard PDP-4 ~ncludes .one input-output device, a photoelectric paper tape reader. The'
reader is governed directly by the internal processor through the reader control unit.
Mounted on one of the bays in the standard PDP-4 is an operator console. The contents of all
registers in the internal processor are displayed in the indicator I ights on the console. Thi~
panel also includes the keys and switches that control the mode of operation of the computer,
and the initiation of aU operations within the computer.

2-3

EQUIPMENT OPTjONS

Some of the options wh i ch may be added to the standard PD P-4 are shown below the horizonta I
bar inFigure 2-10 The memory capacity of the PDP-4B may be expanded to 8192 18-bit words
by adding the Type 17 Memory Option. This option includes a 4096 word core memory identical to that used in the PDP'~4BQ as well as several plug-in units which must be added to the
internal processor to control the second memory module.
2-2

An assortment of input-output equipment may be added to PDP-4 by installing the Type 25
Real Time Option. This option includes a device selector which decodes the microinstruction
portion of the in-out transfer instruction into in-out pu Ises. These pu Ises control the transfer
of information between the in-out device control units and the internal processor

The in-out

pulses also control the initiation of all operations within the device control units, and can
sense the status of in-out devices for program control purposes.

In addition to the device selec-

tor, the real time control also includes an information collector, an information distributor/l
an in-out skip facility, and an interrupt control.
The interrupt control allows program, c lock and data interruptions.

In a program interruption,

a signal from an external device can interrupt the main program, transferring control to an
approprfiate subroutine . Clock interruptions allow the computer to count pulses on a 60 cycle
clock so that the computer can be synchronized to durations in real time.

In a data interrup"'"

tion, the program pau~e.s for one memory cycle, while an external device gains direct access
to memory.
A wide variety of input-output options is available for use with PDP-4. Two of the most common
options are the following ~
Keyboard/Printer and Control type 650 The Type 65 is a Teletype Model 28 Keyboard and
Printer, with an input and prihting speed of ten characters per second.
Paper Tape Punch and Control Type 75. The Type 75 is a Teletype BRPE Punch, with an operating speed of 63.3 lines or characters per second.

It punches eight-hole tape.

However, the

punch may be modified to punch five-hole tape or seven-hole tape, if desired by the user
2-4

SYSTEM OPERATING SPECIFICATIONS

SYSTEM CHARACTERISTICS
Appl ication

Genera I purpose

Timing

Synchronous

Operation

Pa ra II e I process i ng

COMPUTER WORDS
Word length

18 bits

Number length

Sign: 1 bit; magnitude: 17 bits

2-3

Instruction length
Memory reference

Instruction code: 4 bits
Indirect addressing: 1 bit
Address: 13 bits

Augmented

Variable instruction code;
maximum length: 18 bits

Instruction type

Sing Ie address

ARITHMETIC UNIT
Interna I number system

Binary

Operation

Fixed point

Number range

_(1_2-17)~n~(1_2-17)

Addition time

16 microseconds, including both
instruction and operand access

STORAGE
Media

Magneti c cores

Cycle time

8 microseconds

Capacity

1024 words, or 4096 words
expandable to 8192 words

INPUT-OUTPUT SYSTEM
Photoelectric Tape Reader

300 characters/second
5-, 7- or 8-hole paper tape

Paper Tape Punch

63.3 characters/second
5-, 7- or 8-hole paper tape

Keyboard/Printer
2-5

10 characters/second

PHYS ICAl CHARACTER 1ST ICS

CONSTRUCT ION
Internal processor, memory, and control units for in-out devices are housed in standard DEC
bays (all steel construction). Control panel is aluminum.
MODULES
Standard DEC system plug-in units, series 1000 and series 4000.
2-4

POWER EQUIPMENT
Power supplies series 700; power controls series 800.
LOGIC
Solid-state. Transistors and crystal diodes utilizing static logic levels (0 vdc and -3 vdc).
DIMENSIONS
Standard PDP-4 (excluding "table)
Height 69 1/2 inches
Length 42 inches
Width 27 inches
Computer table
Height 27 inches
Width 80 inches,
Depth 23 inches
Reader
Height 8 1/2 inches
Width 19 1/2 inches
Depth 18 inches
Standard PDP-4 including table and reader
Weight 940 pounds
Reader and punch
Height 23 inches
Width 19 1/2 inches
Depth 18 inches
Weight 90 pounds
Keyboard/ printer
Height 153/4 inches (291/4 inches with top up)
Width 20 1/2 inches
Depth 23 1/2 inches
Weight 90 pounds
PDP-4 with table, reader, punch and keyboard/printer
Weight 1090 pounds

2-5

Memory expansion type 17
Requires extra bay I increasing length'to 62 inches .
Weight 250 pounds
2-6

POWER REQU IREMENTS

LINE VOLTAGE INPUT
105 to 125 volts, 60 cycle, single phase
CURRENT CONSUMPTION
Standard PDP-4B

8 amperes; 940 watts

Memory expansion type 17

1 .5 amperes

Reader

1 .0 ampere; 125 watts

Keyboard/printer type 65

1 .2 amperes; 60 watts

Punch type 75

1 .2 amperes; 75 watts

NOTE: With reader, punch and keyboard/printer in use, the computer requires less than 12 amperes. However I because the punch
draws a 9-ampere surge at turn-on, the computer should be connected to a 25-ampere line.

2-7

EQUIPMENT LISTING

The Standard PDP-4 and many of its options are housed in standard DEC bays. The front of
each bay can accommodate up to twelve horizontal 19-inch mounting panels.
hold up to 25 of the standard DEC plug-in logic modules.

Each panel can

Inside the double doors at the back

of each bay is an inner plenum door. The required power supplies and power control panels are
mounted on this door.
a BAYS - The PDP-4with reader, punch and keyboard/printer is shown in Figure 2-2. The
logic for the basic computer is contained in two DEC bays bolted together. As shown in
the figure, the operator console is at the front of the computer (mounted at the side of bay
1). The rear of the bays is at the left side of the console. The inner plenum doors which
hold the power equipment are inside the double doors shown in the figure.
In addition to the standard equipment, the real time option and the control units for the
punch and keyboard/printer can be mounted in bays 1 and 2. The type 17 memory option

2-6

and most in-out options must be housed in -separat,eunits.
~,

LOGIC PANELS AND POWER EQUIPMENT - The mounting panels and logic wiring of

PDP-4 are shown inFigure 2-3. Bay 1, containing the internal processor, the console and
the control units for reader fI punch and keyboard/printer, is at the left. Bay 2, containing
the memory logic and the real time option is at the right. Below the real time option is a
mounting panel for in'''';outplugstoconnect the computer to peripheral equipment. Space
for control units of optiona I deV'i'ces is avai lable below the in-out plugs.
Figure 2-4 shows the plenum doors on the backs of the bays.

In the center of bay 2 (He the

large resistors for the memory power supply. At the top of bay 2 are the main power cir,"

...

cuit breakers and the memory power switch.
728 power supplies.
plug-in modules

In the lower part of each bay are the type

Eac~of these supplies provides +10 and -15 volts dc required by the

Marginal check power supply controls are located at the top of bay 1. Behind these controls is a variable power supply type 734. The output of this unit can be varied from 0 to
20 vdc and can be applied to either the +10 or -15 volt lines in any logic panel for marginal checking the plug-in unit components.
Figure 2-5 shows the interior of bay 2. At the left are the backs of the logic panels; at
the right is the 'inside of the plenum door. 'The plug-in units in the four panels at the top
are logic circuits for core memory. The third memory panel also contains the core bank.
Below the memory are three pane"ls which contain the logic circuits for real time option.
In-out plugs are located helowthe real time option.
At the bottom of the plenum door is a type 728 power supply which provides power for the
logic in the bay

Above the 728 supply is the memory power supply type 735. At the top

of the door is the power control panel containing delays and isolating circuits for the
power sw itches.
A complete logic layout and-power equipment layout of the PDP-4 is shown inFigure 2-6.
The figure shows six type 728 power supplies -- four of which are required for the standard
computer. The bottom supply in each bay is for optional equipment.
The following table lists the mounting panel and power equipment requirements for the
standard PDP-4 and four options: Memory Expansion Type 17, Real Time Option Type 25,
2-7

Keyboard/Printer Type 65, and Punch Type 75.

(1) Standard PDP-4
Space requirement

2 bays

Logic panels
Interna I processor

6 mounting panels 1914 (l A to 1F)

Core memory.

4 mounting panels 1914 (2A to 2D)

Reader contro I

1 mounting panel 1914 (1 K)

Power equ i pment

4 power suppl ies 728
1 variable power supply 734
1 power supply 735
1 power control panel 813
1 marginal check switch panel

(2) Optional Equipment,
Memory expansion type 17
Space requirement

1 bay

Logic panels

4 mounting panels 1914

Power equ ipment

1 power supply 728; 1 power supply 735

Real time option type 25
Logic panels

1 mounting panel 1914 (2E)
2 mounting panels 1909 (2F, 2H)

Keyboard/printer control type 65
Logic panels

1 mounting panel (l M)

Power equipment

1 power supply 728*

Punch control type 75

;.' Ie

Logi c panels

1 mounting panel 1914 (1 L)

Power equipment

1 power supply 728*'i

If punch and keyboard/printer are both installed, only one extra power supply 728
is required

2-8

c MODULE'.lISlJ7..;Thef fgJ~1?Yiifl9.:,lj~.t:jRAlt~.tq~~~;~g!J"}t-~·~,plug-in:ry'lodules required by the

internal proc,eSspri.,: the "'11 K/Clnp·'f1.l<99~~"mern9rt~~:rreqq,~r. control, memory option type 17,
real time option type 25,.keyboqr~f):?dnter;con;t{9Itype 65, and punch control type 75.

(1) Internal Pro~~ssd'r"'- Numbers at the right are for the internal processor of PDP-4B.

N~gd~ive numbers in parenthesesin.cfrcote plug-in units that are removed for the PDP,

"~ ~~.

4A. Positive numbers in parentheses indicate 'plug-in units that'must be added to the
internal processor if the type 17 memory option is installed .
Type

Quantity

De~ay line 1310

2,(1)

Delay line 1311

(1)

Pulse amplifier 1607

(1)

Plug adapter 1956

Inverter 4105

Inverter 4106

D'iode 4111

Diode 4112

D:i'ode 4 113

Diode 4114

Diode 4115
Capacitor-diode 4127

Capacitor-diode 4129

Binary-to-octa I decoder 4150

FI ip-flop 4203

Dua I fl i p-flop 4204

21 (2) (-2)

Quadruple flip-flop 42~4

Quadruple flip-flop 42~18

Delay 4301
Integrating one-shot 4303
Clock 4401
Pu Ise generator 4410
Pulse amplifier 4604

(2) Cor~ 'Memory'~. Plvg:"inunlt ~equirements for the, type 17 memory expansions are
equqlto the'plug~in,unitreqw~ren'1entsfor the 4K memory I , plus the plug-in units that
must be added :~Q, th~, il'lte(na,l pro~~ssor{ se~ (1) page 2-9)
Quantity

Type

PD,P-4A
("1 K)

PDP-4B
(4K)

I~verte~ t1lb3"
~

, Inverter;l f04. ~ ,

• r ~.

Quadruple fl,ip·fl~p 1i13 ..
Sense amplifier ,1540

Pulse amplifier 1607
;:"

Power supply ~ontrOl ;l701'~
,(in power supply 135) :'1,

'Read/write switch 1972

Resistor 1978

Inhibit driver 1982

': ~ .,~

. : , .

j,-'

" Me~ory driver 197,3 '
Resistor 1976

'/ . ~

(3) Reader Contro I
Inverter 4105
Inverter 4106

Diode 4112
Capacitor-diode 4127

Quadruple flip-flop 4218

Pu Ise generator 4410
Pu Ise ampl ifier 4604
(4) Real Time Option Tlpe 25
Bus driver 1690

Inverter 4102
Inverter 4105
Diode 4114

, 2-10

Quantity

Type
Diode 4115
Capacitor-diode 4127
Capacitor-diode 4129~

Quadruple flip-flop 4218

Pu Ise generator 4410
Pulse amplifier 4604

Pulse amplifier 4605

(5) Keyboard/Printer Control Type 65
Inverter 4105
Inverter 4106
Diode 4114
Capacitor-diode 4127
Capacitor-diode 4128

Quadruple fl ip-flop 4214

Four-bit counter 4215

Quadruple flip-flop 4216

Clock 4407

Pulse amplifier 4604

Pu Ise ampl ifier 4605
(added to device selector)
Solenoid driver 4681
(6) Punch Control Type 75

Inverter 4105

Diode 4113

Quadruple flip-flop 4216

Delay 4301
Pu Ise generator 4410
Pu Ise ampl ifier 4604

* For interrupt logic, status and reader; add 1 for each additional device.

2-11

Type

Quonlity

Pulse amplifier 4605
{added to device selector}

Solenoid driver 4681

2':"12

CHAPTER 3

INSTALLATION

3 -1

GENERAL

Th is chapter provides the information needed to install the standard PDP-4 computer system
and the more common in-out device options. Installation and inspection procedures are described, together with general information on initial testing and use of the checkout programs.

3-2

INSTALLATION OF THE STANDARD COMPUTER

The standard PDP-4 consists of a two-bay central frame, a photoelectric paper tape reader,
and a separate table for the reader. The two most common items of optional in-out equipment
are a pap~r tape punch and a keyboard/printer. The central frame is shipped fully assembled.
The in-out equipment items are packed separately and must be installed before the system is
ready for use.

:!. SITE SELECTION - Before installing the PDP-4 system, a suitable location must be
selected. Space requirements for the system depend upon the quantity of optional equipment to be used
Figure 3-1

The floor area occupied by the central frame and the table is shown in

The central frame is 69-1/2" high. At least 3 feet clearance should be

allowed on all sides of the central frame for ease of access during maintenance.
Because the computer is mounted on casters, a level floor is required. The floor should be
capable of supporting 150 pounds per square foot.
The system is designed to operate efficiently over an ambient temperature from 50

to 104 •

The plug-in modules are cooled by blowing air out the front of the bays. Intake fans are
mounted in the floor of each bay. All necessary fans and blowers are installed at the
factory.

No additional cool ing equipment is required.

The user may elect to operate PDP-4 on either 110 or 220 vac. The internal power control
connections for one type of line voltage or the other are made at the factory before shipment. Although the computer, including punch and keyboard/printer draws less than 12

3-1

amperes (at 110 vac) while in operation, turn-on surges in the nn~out equipment (particularly the punch) may momentarily exceed this valueo A 25 ampere line is therefore recommended if the punch IS ~ncluded i~ the system

(Additional power must be prov~ded for

other optional peripheral equipmenL)
b UNPACK!NG AND HANDLING - The central frame is shipped on a skid, and may be
crated or not I depending on the mode of transportatnon
uncrated

A crate is furnished for air shipment

For truck sh ~pment it may be Ieft

'The crate contain~ng the central frame

is approximately 7.4 inches high, 3 feet wide and 4-1/2 feet long

The table and tape

reader are separately crated for all types of shipmento ~
(1) If the central frame is crated, carefully remove all crating and strapping! and
any packing material
padding

If the computer is sh ipped uncrated v remove any protective

(2) The plenum doors at the rear of the central frame bays have spring catches

reinforce these doors during shipment two bolts are used to hold each door shute Remove these bolts and store them in the plastic loops provided
(3) Remove any packing material, shipping blocks" etc
puter

from the inside of the com-

(4) The plug-in modules are taped into the logic panels to prevent damage in shipment

Remove the tape.

(5) Unpack the computer table and place it in front of the consol e (See Figure 2-2) •
(6) Below the table is a panel of power plugs for the in~out equipment. On the floor
of bay 1 is a power cabl e wi th a fema Ie pi ug

Run the cab! e th rough the hoi e in the

bay floor and plug it Into the single male socket in the power panel

The power

cabl es for the i n~out devi ces may be pi ugged into any of the four fema Ie sockets e
NOTE: If the user plans to reship the computer (or move it more
than a 'short distance) in the near future, special packing materials
should be saved for reuse The containers for the reader! punch and
keyboard/printer in particular, have been designed'especially to
accommodate the equipment, and are the safest means of packung it
for resh ipmenL
0

3-2

INSTALLATION OF TAPE READER - The single standard in-out device is a photoelec-'

tri c paper tape readero The reader is mounted in 'a cabinet, and the entire assembly !s
shipped in a single containero

If the computer also includes a tape punch, the two devices

are installed together (see paragraph 3-3~
the procedure Iisted below
(1)

For installation of the reader alone, follow

Uncrate the reader and place 1't on the computer table. Remove the cabinet top

by unscrewing the three Phillips screws on each side of the cabineL
to make sure that nothing has come loose during shipment
(2)

Inspect the reader

The reader power and data cables are coi led inside the reader cabinet

Run the

cables through the hole in the bottom of the cabinet, over the edge of the computer
table, and through the trough connected to the underside of the table

The data con-

nection from the reader to the computer is through a 22-pin Amphenol connector

Run

the data cable into bay 1 through the hole in the computer floor, and plug it into the
socket at the end of mounting panel 1K
sockets in the power plug panel
(3)

3-3

Replace the cabInet top

Plug the power cable into one of the female

INSTALLATION OF OPTIONAL EQUIPMENT

Two of the more common optiona I devi ces' used 'wi th the PDP-4 are a paper tape punch and a
keyboard/printer
stalled together
a

If the punch is included in the system, the punch and the reader are in-·

READER AND PU NCH - The tape reader is mounted in a cabinet, and the entire assem-

bly is shipped in a single container
containers

The punch and its cabinet are shipped in separate

Packed inside the punch cabinet are the power and data cables, the punch

cover, the tape catcher,,, and the chad box
(1)

Uncrate the punch cabinet and place iton the computer table. Open the door on

the right side of the cabinet, and remove the punch cover, the tape catcher and the
chad box

Coiled inside the cabinet are the power and data cables; these cables are

attached to the switches on the front of the cabinet.

3-3

(2) Uncrate the lape reader.

Place the reader cabinet on top of the punch cabinet,

so that the hole un the bottom of the reader cabinet is directly above the hole in the
top of the punch cabHnet

Remove the top of the reader cabunet by unscrewflng the

three Phullips screws on each side. Inspect the reader to make sure nothing has come
loose dudng shipment. Attach the reader cabinet to the punch cabinet by screwing
down the two captive bol ts at each si de of the reader

(3) The reader data and power cables are coiled inside the reader cabunet. Run these
cables through the hole in the floor of the reader cabinet' into the punch cabinet. Replace the top of the reader cabineL
(4) Careful Iy uncrate the punch and remove all packing materia!
wires ll screws ef'c.

Check for loose

Place several magazines or other such flat objects on the computer

table undew the open door of the punch cabineL Place the punch on the open door
(5) Attach the punch power and data cables to the punch

The power cable has a

Twist-lok connector; the data cable has an Amphenol type 57-30240 connector

(6) Run the data and power cables for both the reader and the punch through the hole

in the bottom of the punch cabinet, over the edge of the computer table ll and through
the trough aUached to the underside of the tabl e a The daf'a cabl es are connected to
the computer wHh 22~pin Amphenol connectors
through the hole in the computer floor

Run the data cables nnto bay 1

Plug the reader cable into the socket at the

left end of mounting panel 1K .. Plug the punch cable into the socket at the left end
of mounting panel 1L.
(7) Place the cover on the punch.
of the punch cabnnet

Note the two aluminum seating studs on the floor

The two mounting plates fit over these sluds

on the seating sf'uds and determine that it is securely in position
(8)

Place the punch

Place the tape catcher in position and secure it to the cabinet floor by screwing

down the two captive bol ts

Hang the chad box in position on the front of the punch,

and close the cab[net door.
(9)

Plug the reader and punch power cables into the female sockets in the power plug

pane!

3-4

KEYBOARD/PRI NTER - The keyboard/printer is ~hipped in a single container

The

power and data cables are already connected to the unitu and are coiled under the unit
inside the container.-"
(1) Uncrate the keyboard/printer-v and place it on the computer table

(2) Run the powe~' and data cables ove~ the edge of the table and ,through the trough
attached to the underside of the table
through a 22-pin Amphenol connector

The data cable is connected to the computer
Run the data cable into bay 1 through the

hole in the computer floor ll and plug it i.nto the socket at the left end of mounting
panel 1Mo
panel

Plug the power cable into one of the female sockets in the power plug

3-4' INSPECTION AND ADJUSTMENT
The PDP-4 system is thoroughly tested and checked before it leaves the factory"

Howeverr it

should be inspected and checked again after installation to 'make sure that no damage has
occurred during shipmenL
a

VISUAL INSPECTION - After the computer has been unpacked and the in-out equip-

ment is in place ll the system should be inspected visually

Check the following~

(1) Have all the shipping blocks; packing materials, tape¥ etc. been removed?

not 1 remove them,
(2) Are all plug-in units inserted firmly in position? Secure any that are looseo

(3) Are there any loose nuts or bo! ts?

If SOg tighten them"

(4) Are there any loose or broken wires?

(Refer to Chapter 11 for repair of wiring,,)

(5) Are the in-out device power and data cables plugged in?
(6) Make sure console POWER swHch is off (left)

(7) Plug in system power cable (the coned cable is on the floor of bay 2)
is e9uipped wHh a Mil ler Electric Type 034-2 connector

3-5

The cable

CAUTION
Unless the system has been modified for use with' 220 vac, the power
cable must be plugged into a 110 volt outleta
(8)' Are the three MAIN POWER circuit breakers on the type 81'3 power control panel
on?
b

If not I turn them on (up)

Make sure the MEM POWER switch is off (down)

METER READINGS - Before starting to run the test program, all machine voltages should

be checked with a meter

(1) With the computer connected to itsppwer source but with MEM POWER off,turn
on the POWER switch on the console,

The associated indic;:citor should lighL

(2) The type 728 power supplies each, have three output lines: ~10 vdc, ground, and
,

-15 vdc

T'he output voltages should be checked for each type 728 supply before

operating the computeru Measure these voltages at mounting panels lA, IF, and 2Ao
If the computer includes the optional real time control, also measure the voltages at
mounting panel 2Fo

All A pins in each mounting panel are bussed togethero Similar-

ly! the B pins, the C pins, and the D pins are also bussed togethero
at + 10 vdc; pin C is at -15 vdc; pin D is at ground
(3) Now turn on MEM POWER,
c

Pins A and Bare

This switch can now be left on permanently"

PREOPERATIONAL CHECKOUT - The PDP-4 program library includes a set of DEC

Maintenance Programs,

These programs are designed to check out different portions of the

computer to ensure that they are functioning correctly, Maintenance programs are a
powerful aid in diagnosing computer malfunctionso
The t~st programs usually run at installation include Instruction Test, Checkerboard,
Reader and Punch Test f and Teleprinter Input-Output TesL

All of these programs are

included in CONTEST, the consol idated maintenancetesL

Because all computer opera-

tions! including the running of test programs, depend on proper functioning of the instructions, the Instruction Testshould be run first,

Af.ter the computer has passed the Instruc-

tion Test, the memory Checkerboard should be run, followed by the Reader and Punch TesL
The Teleprinter Input-Output Test should be runlasL
More detailed instructions concerning use and applications of the PDP-4 maintenance
programs are furnished in the maintenance chapter of this manual, Chapter 11.

3-6

CHAPTER 4

SYSTEM FUNCTION

4-1

LOGICAL ORGANIZATION

The logical configuration of the PDP-4 is shown in Figure 4-1. The computer logic is divided
into four parts~ control unit, arithmetic unit, memory and input-output system. The contro!
unit and arithmetic unit together constitute the. internal processor.
a

CONTROL UNIT - The control unit of the computer governs the timing of all computer

operations, the information transfers between the internal processor and the memory or
input-output system ll and the operation of the various registers. The control unit includes
three internal registers, IR, PC and MA, and two console switch registers, AS and ACS

The instruction code of each instruction is decoded from the four-bit instruction register,
IR, to govern the execution of the instruction.

Each instruction word is retrieved from the

memory location specified by the contents of the 13-bit program counter, PC.

During the

execution of each instruction the program counter is advanced one position; consecutive
instructions are thus taken from consecutive memory locations.
Every memory access is made to the location specified by the contents of the 13-bit memory address register f MA. The MA register is loaded from the program counter for instruction retrieval; it is loaded from the address portion of the instruction word (in the memory
buffer) for either deferred address retrieval or memory reference. The operator can manua Ily provide addresses and data words for use by the computer through two switch registers

on the console control panel: the address switches, AS, and the accumulator switches,
ACS.
In addition to these registers the control unit also includes the operating switches u the
operating keys, and the control logic. The operating switches govern the mode of operation of the computer; the operating keys start and stop the specifi c computer operations

The control logic contains those control flip-flops and logic nets that govern computer
states, information transfers, and the operation of computer registers. The control logic

4-1

also contains the timing system of the computer

Most elements of the control unit are described in paragraph 4-3"

Howeverf those ele-

ments of contro I that are di recti y assoc iated with the ad thmeH c un i t or the memory are
described in conjunction with those units (paragraphs 4-4 and 4-5 respectively)"
b

ARHHMETIC UNIT - The arithmetic unit includes two l8-bit registers, AC and MB,

and a l-bit regist~r.f La
The memory buffer,MB, serves two distinct functions: d memory function, and an arith-'
meti c function

All transfers of information between memory and the other parts of the

computer are made through MB

The memory buffer is used in the arithmetic unit as a

passive register, that is, it serves only to hold the operand in arithmetic and logical instructions.

However:,. all indexing (i .e., incrementing by 1) is done directly in MB with-

out using AC

The accumulator, AC, is the major register in the arithmetic unite

It serves both as an

accumulator and as an in-out register.

The accumulator input logic includes transfer,

rotate, logical, and arithmetic gating.

The accumulator is used in the execution of all

two-term logical an'd arithmetic instructions.
tions always appears in the accumulator.

Furthermore, the result of all such instruc-

The AC input gating allows the computer to

perform the logi c functions AND, exclusive OR, and negation, as well as arithmeti c operation of addi tion

All other ari thmeti c operations must be programmed by using combina-

tions of negation and addition. The inclusive OR function must be programmed by combining negation and conjunction.
The bits of AC can be rotated in either direction

The ends of the register are connected

through the l-bit link, L, and the 19-bit combination is rotated

Besides functioning as

a computationa I register I AC a Iso serves as the in-out registeL All transfers of information between the computer and low-speed or programmed peripheral devices are made
through AC

The linkll L, extends the capability of the accumulatoL

This l-bit register connects the

ends of AC so tha't the 19-bit combination of Land AC can be rotated as a single register.
The programmer can use the link to construct products and quotients one bit at a time.

4-2

MEMORY - Two versions of the standard PDP-4 are available, depending upon the

type of memory modu leo The memory modu Ie of the PD P-4A provides storage for 1024
words; the memory module for the PDP-4B provides storage for 4096 words. Both modules
are magnetic-corey coincident-current memories which store 18-bit words. The memory
of PDP-4B can be expanded to 8192 words by adding the type 17 memory option. This
option includes a 4096 word memory module and the necessary controlling circuits for the
internal processoL
The lengths of the program counter and memory address register vary with the type of
memory included in the computer. These registers may be 10, 12 or 13 bits in length, depending upon whether a 1K, 4K or 8K memory is used. During each 8-microsecond memory cyclel1 access is made to the memory location specified by the contents of MA

The

addresses of the core registers in memory are always given in the octal number system so
that the addresses are the same as the configuration of bits (taken three at a time) displayed in the console indicators. Addresses may therefore vary from 0 to 1777, 7777 or
17777 depending on memory capacity.
The word read from memory is transferred into the memory buffer by a strobe

Since the

. read operation is destructive, the word contained in MB must be written back into the
core memory during the same cycle.

In preparation for the deposit of new information in

memory, the strobe is inhibited so the information read from the core register does not
reach MB

New information is then transferred into MB from the interna I processor, and

written into the addressed memory location by the write portion of the memory cycle.
d

INPUT-OUTPUT SYSTEM - The input-output system in the standard computer includes

one input device--a paper tape reader with its associated control unit. The control unit
is governed directly from the internal processor by in-out pulses generated from instructions
in the in-out transfer group. All transfers of data between the reader buffer and the computer are made through the accumulator.
A large number of optional in-out devices may be added to the computer. Two of the
more common optional devices are the paper tape punch for output, and the keyboard/printer for both input and output. Whenever any optional in-out equipment is added to
the computer.r the real time option must also be installed. Then all devices (including the

4-3

reader} are controlled from the internal processor through the real time option

This op-

tion includes a devi ce selector, an information distributor I' an information collector, an
in-out skip faci lity g and an interrupt control

The devi ce selector", DS, decodes the devi ce code portion of the in-out transfer instruction (bits 6 to 11) and switches the in-out pulses from the internal processor to the control
unit of the selected deviceo Transfers of data between the computer and the control unit
buffers are made through the accumu lator.

Input information is gathered from various

control units by the information collector, lei output information is distributed to the various control units by the information distributor, ID.

During in-out operations data trans-

fers between a device and its associated control unit are performed automaticallyo
The interrupt control allows various external signals to interrupt the program sequence

program break saves the current program address and transfers control to an appropriate subroutine

A clock break may be used to keep track of real time and thus correlate internal

operations to real time. A data break causes the program to pause for one memory cycle
while a high-speed automatic device makes direct access to memory

For example", with

the automatic tape control unit, control information goes through the accumulator, but
data is transferred directly between the memory buffer and the control unit through a direct
access channel
4-2

PROGRAMMING

This paragraph describes the programming characteristics and the instruction repertoire of
PDP-4n
a

NUMBER SYSTEM - PDP-4 is a fixed-point machine using binary arithmetic.

Nega-

tive numbers are represented as either the ones complements or the twos complements of the
positive numbers

Bit 0 is the sign bit, which is 0 for positive numbers

Bits 1 through 17

are magnitude bits", bit 17 being the least significanL The actual position of the binary
point may be assigned arbitrarily to best suit the problem at hando Two common conventions in the placement of the point are:
The binary point is placed to the right of the least significant biti
a II numbers then represent integers.

4-4

The binary point is placed to the right of the sign bit; all numbers
then represent fractions between -1 and +1

Subroutines can automatically perform both the conversion of decimal numbers into binary
for use in the computer, and also the output conversion of binary numbers into decimal

Operations for floating-point numbers are handled by interpretive programming or subroutines.
b

INSTRUCTION FORMAT - There are two classes of PDP-4 instructions: memory refer-

ence instructions and augmented instructions.
Memory reference instructions need access to memory for an operand, and therefore require two memory cycles for execution

Augmented instructions, on the other hand, have

no operand, and for this reason are performed in one memory cycle. The bits used to address the operand in the memory reference instructions are instead used, in the augmented
instructions, to augment the contro I capabi Ii ty of the instructions. Accordingl y, the augmented instructions are those instructions having augmented instruction codes
There are also two instructions which fall into neither of these classes

These instructions,

Jump and Load Accumulator with n, use their own address portions as operands and thus
are executed in a manner simi lar to the memory reference instructions

However, because

these two :instructions require no actual access to memory, they are executed in a single
cycle.
Memory reference instructions include arithmetic instructions, logical instructions, data
handl ing instructions, and program control instructions

The augmented instructions are

divided into two groups, the operate group and the in-out transfer groupo Each group is
actually a class of microinstructions produced by microprogramming the non-instruction
code portion of the instruction word

The instruction words for memory reference instructions require both an instruction code
and a memory address

The instruction code (bits 0 through 3) specifies the particular

instruction to be performed

The location in memory to which reference must be made is

specified by the memory address portion, Y (bits 5 through 17)

Bit 4 of the instruction is the indirect address bit. This bit is normally o.

4-5

If bi.t 4 is a 1,

the original address Y of the instruction is not used to locate the operand, jump location,
deposit location, etc of the instruction.
0

Instead, the address portion of the instruction

is used to locate a memory register that contains a new address

The new address is used

in place of the address portion of the original instruction" Th!s Indirect addressing technique frequently expedites the programming task

Furthermore ll address indexing may be combined with indirect addressing! avoiding the
need for separate indexing instructions. For this purpose! memory registers 10 through 17
are available as index registers

Whenever an instruction is indirectly addressed to one of

these memory index registers, the di rect address is indexed before being written back into
memory

The indexed direct address is then used for the required memory reference.

this way 11 a single indirectly addressed instruction of a program loop may refer to a successive memory location in each iteration of the loop

An instrucHon which uses an indirect address is called a "deferred" instruction because the
actual operation which the instruction performs is deferred unti I the new address is retrieved
from memory

Thus in a deferred instruction, Y is not the location of the operand, but

the location of the location of the operand. All memory reference instructions except law
can be indirectly addressed

Load AC with n must have a 1 in bit 4 because it used the

same primary four-bit code as the augmented instructions in the operate groupo
Augmented instruction words use the entire word for the instruction code

Thus the entire

class of augmented instructions uses only: two of the available sixteen primary codes to
perform a very large number of instructions

The instructions under each primary code are

referred to as an instruction group. For example, in the operate instructions, the group is
specified by the standard four-bit code in bits 0 to 3 plus a 0 in b!t 4,9 while the specific
instruction within the group is specified by the configuration of bits 5 to 170 The instructions in the operate group include skips, rotations of the accumu lator! and various other
logical operations"
The code for the in-out transfer group is bits 0 to 3 of the instruction word, whi Ie the
generation of in-out pulses and the clearing of the accumulator for in-out transfers are
controlled by bits 14 to 170

In the standard computer the in'-'out pulses are applied directly

to the reader control uniL

If the type 25 real time option is installed, each device is

selected according to the configuration of the device code (bits 6 to 11)

4-6

Bits 4, 5, 12

and 13 may be used to form subfunctions in the devi ce code or they may be used for other
contro I purposes
c

COMPUTER STATES - All instructions and interrupt operations are performed in mu Iti-

pies of the basic 8-microsecond memory cycle. The computer performs every memory cycle
in one and only one of four major states
break

These states are fetch, execute, defer and

The first three of these major computer states (fetch, execute, and defer) are pro-

gram states, i. e., whenever the computer is in one of these states, it is performing those
operations necessary for the execution of an instruction in the program

The fourth major

state of the computer,q the break state, is that state in which the computer performs all interrupt operations

Whenever the computer is in one of the three program states, fetch, execute, or defer,
it must also be in one of the minor computer states. This means that the computer must be
performing some specific instruction

These minor states correspond to individual memory

reference instructions I and to groups of augmented instructions.
During the fetch cycle of each instruction, the instruction word is retrieved from memory.
Augmented instructions are completed during this single memory cycle

Note, however,

that during the fetch cycle of an in-out transfer instruction, the internal processor merely
generates the appropriate in-out pu Ises. These pu Ises either are appl ied to the devi ce
control unit or else transfer information from the control unit into the internal processor.
Actual operations within the control unit and the transfer of information to the control
unit may occur much later.
If an instruction is deferred {indirectly addressed} the computer goes into a defer cycle at
the completion of the fetch cycle. During this defer cycle, the address portion of the instruction is used to retrieve a new address for the instruction operand.
In memory reference instructions, the fetch cycle (or the defer cycle, if the instruction is
indirectly addressed) is followed by an execute cycle. During the execute cycle, the
operand is retrieved from or depositied in memory, and the operations required by the instruction are completed

An instruction may be completed in any of the three program cycles, depending upon the
type of instruction

Augmented instructions are always completed in a fetch cycle. The

4 ....7

instruction Jump may be completed either in a fetch cycle or in a defer cycleo All memory reference instructions are completed in an execute cycle

After an instruction is com-

pleted", the program sequence may be interrupted by an external signal through the interrupt logic

When this occurs, the computer enters the break state

There are three types

of break cycles; these are for a dato break, a c lock break" or a program break

In a data break h' the main program pauses for one memory cycle while a high-speed device,
such as magnetic tape, gains direct access to memory"
the devace contro~ unit provides an address to MA"

At the beginning of the cycle,

If information is requested by the de-

vice" the word read from memory is m,ade- available to the control unit.

If information is

being transferred into the compute~r, the strobe is disabled, and new information is transferred into the memory buffer

In a clock break; the computer indexes the word contained ~n memory location 70

If this

index operation nncrements the word to zero (in twos complement arithmetic), the clock
flag is seta The program may therefore count external time signals by checking the clock
flag.,

In a program break, a signal from an external device can break the normal program

sequence and transfer control to a subroutine appropriate to the deviceo When a program
break occurs? the address in the program counter is deposited in memory location 0, and
program control is transferred to memory location 1
d

CONSOLE CONTROL - The states of all internal processor registers and control de-

vnces are shown in ~ndicator lights on the console. The console control panel also includes
the switches through which the operator exercises control over the computer. These switches
a Ilow the operator to start and stop computer operations, contro I the mode of operation,
and spec3fy words and addresses to be used by the computero The initiation of any operation from the console is timed by a chain of special pulses" spo through SP4. After completion of this speda! pulse chain, the regular memory cycle timing system of the computer begtns

The computer has four modes of operation: normal., single stepf single instruction, and repeaL

In the normal program-running mode, one memory cycle follows another without

interruption until the computer is halted by either the program or the operator. There are
two manual-operate modes: single step and single instruction

4-8

These are controlled by the

s~ngie step and single instruction switches

In a manual mode, operations are begun from

the console nn the normal manner but the computer halts at the end of the first memory
cyc~e (single step) or the end of the first complete instruction (single instruction)

During

any operaHon the computer must be in one and only one, of the above three modes (norj

malt' s!ngle step, or single instruction)

Furthermore f while in any of these three modes,

the computer may also be in a fourth mode -- the repeat mode

While the repeat switch

is on y the operation associated with any console key that is held on is repeated at a rate
det.ermined by the settnng of the speed switches

Console control of computer operations is exercised through seven operating keys

Six of

these console functions initiate computer operations; the seventh halts the computer.

all of these functions except Continue and StOPf the special pulse SPl produces the BEGIN pulseo

BEGIN clears various registers and flip-flops to prepare the computer for

, operat~on

The console functions are as fo I lows :

Start
The comput.er starts normal operation in the fetch state
the mem?ry ~ocation addressed by the address switches
of operatnon in the manua I modes

The first instruction is taken from
Start also initiates the first cycle

ContHnue
The computer resumes normal operation at the state indicated by the console lightso

In the

manua! modes" contnnue also initiates each cycle or instruction after the first.
Examine
The contents of the memory register addressed by the address switches are displayed in the
accumulator and memory buffer lights on the consoleD The address contained in the address
switches is transferred to the program counter and incremented by 1

Exam~ne Next

The contents of the memory register addressed by the program counter are displayed in the
accumulator and memory buffer lights on the consoleo The contents of the program counter
are incremented by 1

4-9

Deposet
The word contailned fin the accumulator switches is deposited in the memory location addressed by the address swHches. The address contained in the address switches is transferred to the program coun·ter and incremented by 1

DeposH Next
The word conta~ned un the accumulator switches is deposHed In fhe memory location addressed by the program counter

The contents of the program counter are incremented by

1"
Stop
'The computer ha~ ffs at the end of the current memory cycle

e INSTRUCTION UST,~ This list includes the title of the onstruction" the normal execuHon tnme O. eo£, wHhout Hndirect addressing), the mnemonic code u the octal representation
of the nnstructtlon code ll and a short description of the instruction
the contents of a regi'ster are indicated by C( )

In the following list,

Thus C(Y) means the contents of memory

location Yi C(AC) means the contents of the accumulator

A specific bit of a register is

nndncated by a subscrnpt number following the symbol for the regHster
sents bOt 17 of the memory buffer

Thus MB17 repre-

For memory reference nnstructions the octal instruction codes are gRven as two digits .. The
more sognHicant drrgOt represents the first three bits of the four-bit instruction code

The

second octal dog6t (with one exception) is either 0 or 4, dependHng upon whether the
fourth bH of the TInstructnon code is 0 or 1

Thus the two-dugH oc·ta! code is equal to the

Hrst f'wa dogHs of the oCfo! instruction word, assuming that bHs 4 and 5 of the word are
both 00

In memo~y Ireference instructions, bit 4 is the indirect address bit, and bit 5 is

the most sugnHncant bH of the 13-bit address

Therefore!1 the second digifof a six-digit in-

strucHon word whose nnstruction code ends in 0 may be Og

g 2 or 3 while the second digit

of an nnstructuon word whose code ends in 4 may be 4 g 5! 6 or 7 g depending upon the conHguraHon of bits 4 and 50
'The one exceptOon ·to th os convention is the nondeferabl e instruction law"

Th is instruction

requires a .~ ~n bH 4 because both law and the operate of augmented instructions use the

4-10

the same primary four-bit instruction code.: - Thus, law has a five-bit code' represented by
octal 76 (111 11) while the primary portion of the augmented codes for the operate group
is represented by octal 74 (111 10). The in~out transfer group is represented by octal
70 (111 0) but the second digit in the instruction word varies according to the configuration
of bits 4 and 5, which are part of the augmented code. For all augmente~ instructions
(comprising the two groups, opr and iot) the entire six-digit octal code is given.
Memory Reference Instructions:
Call Subroutine (16 fJsec) ......... '.... cal

Instructio'n Code 00

This instruction is equivalent to the instruction, jms 20. The address portion, Y, is ignored.
Call Subroutine may be used ps part of a master routine to call subroutine~. The address
20 may be interpreted as an indirect a;~dr~ss -- that is, cal indirect is equivalent to jms
20 indirect.
Deposit Accumulator (16 psec). . . . . . . . .. dac Y

Instruction Code 04

The C(AC) replace C(Y) in memory. The C(AC) are unchanged, the original C(Y) are lost.
JUrl'lP to Subroutine (16 fJsec) ...........

jms Y

Insturction Code 10

The C(PC) replace C(Y) in memory. When the transfer takes place, the program counter
holds the address of the instruction following the ims in normal sequence. The program
then executes the instruction in memory location Y + 1. The original C(Y) are lost.
Deposit Zero in Memory (16 fJsec). . . . . .. dzm Y

Instruction Code 14

The contents of memory location Yare replaced by zero (i. e ., memory location Y is
cleared). The original C(Y) are lost.
load Accumulator (16 fJsec) ............ lac Y

Ins~Tuction Code 20

The C(y) are placed in the accumulator. The C(Y) are unchanged; the original C(AC)
are lost.
Exclusive OR (16 fJsec) . . . . . . . . . . . . . . .. xor Y

Instruction Code 24

The bits of C(Y) operate on the corresponding bits of C(AC) to form the exclusive OR.
The result is left in the accumulator. The C(y) are unaffected.

4-11

Ones Complement Add (16 ~s~c). ~ ',',:_ ...•. add Y ;
The final C(AC) are the sum of the C(Y) and the .original C(AC); C(Y)' are 'unchanged . The
addition is performed in 1s complement arithmafi.c.

If the sum exc~eds the capacity .of the

, ,accumulator, the I ink is set.
"

In 15' c.omplement arithmetic, a negative number is rep~esented by th~ co~pl~~~nt of the
, :

•

•• ~ 1 ~ '- '

(

corresponding positive number. 'Thus a poshive number is chang~d to a'"neg~tive number
by changing the sign bit to 1, and changing all the Osto1s dod. cilLthe ls.to.'OSin. the
magnitude portion of the number. Since the complement of.~ slnglerbH, i.s:e;qui~9:1';.ent to
subtracting the bit from 1, complementing the binary integer n is equivalent ~o slJ~tracting
n

'n from 2

':"(2

, , : ",' i" : ":";,:,j :~"

- 1. Thus the number -n is represented in 1s complement a~ithm~ti c ~s
'

:,,,..

:,'

- n - 1). This convention results in'two representations for the number zero,: all Os

;, (+0), or a II 1s (-0). Minus zero resu I ts f~om adding -0 to -0, or adding -n fo +n.'
•

Twos Complement Add (16 ~sec). _ ... _ . .. tad Y

':,<

:'.
••

Instruction Code 34

The final C(AC) are the sum of the C(Y) and the .original C(AC); C(Y) are unchanged. The
addition is performed in 2s complement arithmetic.

If there is a carry out of bit O.of the

accumulator, the link is set. This feature is useful in multiple precision arithrri'e!tic.
In 2s complement arithmetic, a negative number is represented by adtJingl' to the ~.om
plement of the c.orresponding positive number. Thus the' riumber.;..n is represen'ted'in 2s
n
complement arithmetic as _(2 - n).
Execute (8 ~sec plus time of instructi.on
executed) ................... " . xct Y

Instruction Code 40

The instruction in memory l.ocati.on Y is executed. The program counter remains unchanged
(unless a jump or skip were executed).

Execute acts exactly as though theinstruct;~on be-

ing executed replaced the Execute instruction in the pr.ogram.

Execute may ge in~irectly

addressed, and the instructi.on being executed may also use indirect address'ing.

An xct

instruction may execute other xct commands.
Index and Skip if Zero (16 ~sec). . . . . . . .. isz Y

Instruction Code 44

, The C(Y) are replaced by the C(Y) + 1. the C(AC) are unaffected by this instruction.
The addition is performed in' 2s complement arithmeti c. 'If the sum is zer.o, the program

:','4-12

counter is advanced one extra position and the next instruction in sequence is skipped
Logical AND (16 .... sec). "

•••

•

and Y

••

Instruction Code 50

The bits of C(Y) operate on the corresponding bit,s of C(AC) to form the logical AND. The
resu It is left in the accumu lator. The C(Y) are unaffected.
Skip if Accumulator and Y Differ (16 JJsec).sad Y
The C(Y) are compared with the C(AC)

Instruction Code 54

If the two numbers are different, the program

counter is indexed one extra position and the next instruction in sequence is skipped. The
C(AC) and the C(Y) are unchanged.
Jump (8 JJsec) ............ " . . . . . . . . . . .. imp Y

Instruction Code 60

The address Y replaces C(PC) , The next instruction in the program is then taken from memory location Y. The original C(PC) are lost.
Load Accumulator with n (8 JJsec), ...

o •••

law n

Instruction Code 76

The instruction word replaces C(AC). The original C(AC) are lost. Since the instruction
code is all 1s, the binary word in AC is interpreted as a negative number (AC

= 1), and

consequently the magnitude of the address portion is equivalent to the magnitude of the
13
enti re word. As a resu It, the programmer may load a negati ve number -n (where n 2 )
into the accumulator by placing the negative representation of n in the address portion of
a faw instruction.
Augmented Instructions:
Operate Group (8 JJsec) ..

•••••••••• ,

••

opr

Instruction Code 74

The instructions in this group perform miscellaneous logical operations primarily up on the
registers in the arithmetic unit. The group also includes the conditional skip instructions.
All instructions in the group require 8 microseconds.
In these instructions the instruction code is 18 bits. The primary code (bits 0 to 4) specifies the operate group while the address portion specifies the operation to be performed or
the skip condition to be sensed, The various operations can be microprogrammed -- that
is, the addresses of the different instructions may be combined to form the union of the
functions.

For example, instruction 740403 causes the computer to skip the next instruc-

4-13

tion, if the Iink is 1 at the beginning of the operate, and complements both the accumu lator and the I ink.
Included in the operate group are the rotate and skip instructions

Rotate is a cycl i c shift.

A shift is an information transfer from bit to bit in a single registero Transfer of C(AC )
n

into AC

1 is a left shift: C(AC ) into AC 1 is a right shifto In a cyclic shift the two
nn
n+
ends of the accumulator are logically joined together through the link and information is
rotated through the 19-bit combination as though it were a ring

The skip instructions sense various elements in the arithmetic unit and cause the computer
to skip the next instruction in sequence if the addressed condition is satisfied

The intent

of any skip instruction is determined by the programming of bit 8 of the instruction word.
For example, the instruction 740200 is Skip on Zero Accumu lator, whi Ie 741200 is Skip
on Nonzero Accumu lator.
The logical operations specified by the operate instructions are performed by one or the
other of two operate pu Ises, OP1 and OP2. These pu Ises occur at different times during
the memory cycle.

Not only can the programmer combine several operate instructions to

perform operations on different elements but, because of the time interva I between the
two pulses, the programmer can also combine operate instructions in such a way as to
perform two operations on the same element at different times

In the following list, the

time of occurrence is given for the arithmetic unit operations. The skip instructions cause
a skip by incrementing the program counter at OP1 if, at that time, the skip condition is
satisfied. The instruction Halt clears flip-flop RUN at OP1, but before stopping, the
computer completes the cycle.
No Operation. . . . . . . . . . . . . . . . . . . . . . .• nop

Instruction Code 740000

The state of the computer is unaffected by this operation and the program counter continues
in sequence.
Clear Accumu lator. . . . . . . . . . . . . . . . . • .. cia

Instruction Code 750000

Clears AC at OP1 .
C Iear Link. . . . . .

•

••

c II

Clears L at OP1 .

4-14

Instruction Code 744000

Complement Accumu lator.

•••••••

•••.

cma

Instruction Code 740001

cml

Instruction Code 740002

ral

Instruction Code 740010

The C(AC) replace C(AC) at OP2.
Complement Link

•••

•

•••

••

•

••

The C(L) replace C(L) at OP2.
Rotate Accumulator and Link Left.

•

Rotates the contents of AC and L Ieft one place at OP2.
AC

L, L =

Rotate Accumulator and Link Righto

•••

rar

Instruction Code 740020

Rotates the contents of AC and L right one place at OP2.

Rotate Twi ce Lefto

••

•

<> •

••••

•

Instruction Code 742010

rtl

Rotates the contents of AC and L left two places. AC n =
AC =

••

•

••••••••

••

AC ' L =
O

Instruction Code 742020

rtr

Rotates the contents of AC and L right two places. AC
17

, L=

Rotate Twice Right.

AC n-2' AC 1 =

AC + , AC
=
16
n 2

Inclusive OR AC Switches with AC .... o. oas

Instruction Code 740004

The inclusive OR function of C(ACS) with C(AC) replace C(AC) at OP2.

If AC is cleared

at OP1 by combining cia with oas (750004), at the end of the instruction C(AC) = C(ACS) .
Ha Ito

•••••

•••

Stops the computer

•

is O.

••••••

••••

•

•••

•

hit

Instruction Code 740040

spa

Instruction Code 741100

Ski p on Plus Accumu lator
Skip if AC

Skip on Minus Accumu lator. . . • . . . . . . . .. sma
Skip if AC

is 1

Instruction Code 740100

sza

Instruction Code 740200

Skip on Nonzero Accumu lator ........... sna

Instruction Code 741200

Ski P on Zero Accumu lator ........

•

••

Skip if all accumulator bits are o.

Skip if any accumu lator bit is 1.
Skip on Zero Link. . . . . . . . . . . . . . . . . . . .• szl

Instruction Code 741400

Skip if L is O.
Skip on Nonzero Link .................. snl

Instruction Code 740400

Skip if L is 1 .
Skip ................................. skp

Instruction Code 741000

Skip the next instruction unconditionally.
In-out Transfer Group (8 Jlsec) .•.

••

••••

iot

Instruction Code 70

All in-out transfer instructions use instruction code 70 (111 0) in bits 0 to30f the instruction word. The programmer specifies the in-out devi ce and thesp~cifi c operations to be
performed by mi croprogramming the rest of the instruction w()rd.

In-out transfers are gov-

erned by a set of three in-out pulses, PI01, PI02 and PI04. The programmer controls the
generation of these pu Ises during the execution of an iot by pr~gramm ing 1, 2 or 4 respectively, as the final octal digit in the instruction word.
The first PIO pulse is generated after the iotinstruction is retrieved from memory in a fetch
cyc Ie.

The second pu Ise is generated 2.0 microseconds later. The th i rd pu Ise then fo Ilows

at the beginning of the next cycle 1.3 microseconds later. Since the pulses occur at different times, a single instruction may use more than one pulse; but only those pulses specified by the instruction are actually generated.
In addition to microprogramming specific operations within the iof instruction, the programmer must also specify the device by placing a device code in bits 6 to 11 of the in-

4-16

In th~ standard COniRpte~" tb~ P.IQ :pu Is~s are appl red'<J/ire:ctJy:tQ,fhe reader

struction word:

If the c:?:mpu;ter in~ludes t~,e txpe.25 real

control unit and no devic~ code is necessqryo
.

:','~

.~':~~":;"~'

~,},~,··.i/·~~.~'l

.~l··'<~

~.\

, time option, the device selector decodes the device code and switches, th,~ ;,pIO pvlses onto
the lines appropriate to the specified deviceo The pulses for each device are named according to the configuration of the j'r'ls'truction :code ~roducing them 0 Fbr-example,! the
three PIO pulses, for the ,readeX,'(ch1i¥i!;~;qRpe·QJt c,re IOJ010,,J'1 IOT0102cindiOT0104
: ;,.'

respectively.

. 1

r',"

Comple,tion of most in-out operations.'r~q\Ji~~s.o ,d~fi9iJeminimu,mtime~ This.:nilh,irhum time
•

:.~ _,i

".;

" '

'.",'

',,'

•

...

OJ'

•

is usually very long compared to the computermemory cy~l~ 0 The iot instructions:'~erve
'-,

':;';i' '4., ::",~--.

, f . ' -".,,;,

,,"

''''~..'

.~ •

•

m~~ely to rniti~te operation~ in 'th~'dev'f~~ c~rJtr~r ljnits -- the 90ntrol unit ,th,e,n carries
,.~_..

i..

:,.'.,""

:~>_':;.~i~~.·~.~:~tiJ ,':::)~~';"';':' ~,~

....

. ' ,

out operations automatically whi Ie the computer may continue executing other instructions.
When the entire operation is compret~d, the program must:'resynchronize the device and
the computer either by uti! izing the' interru'pf:fbgi c or by sensing the devi ce flag 0
In;,a,n,jot's, PI01-is used to sense'a'd~\ti'teflag, while PI02 usually clears the flago For
input devices, PI04 initiates operations i'ff'/Hf~}"aevice control unit 0 After the operation
is completed, the programmer, m~¥:cI~ar~Jh~,,~ccumulator by programming a 1 in bit 14 of
an iot instruction word, and can then transfer information from the devi ce buffer to the
.'

., f ' ,

.',

{

•

;',

}

.;:~.::

~·,··;!'·r~ .~

accumulator with PI020 For output devices, PI02 clears the device flag and the device
buffer. A PI04 pu1lse in' ,the"same rnsfttc'~1'oh',i~~y then transfer information to the devi ce
buffer and be~Jn <?peratjon of th e -, cC?lltroLYnrtt~:,';'
In addition to the device <i:odeil1 bitsp to ll/~ and the standar'd coding of bits 14 to 17 of
the instruction word, the. program.mer mayusebt,ts 4, 5 F 12 and 13 to produce subfunctions
~

•

,.:

;

"<.-, ':

.~. ':~";'

:;-

••

,-;;~

..... , :...

.....

in the device code or for other control purposes 0 For example,! in reader instructions the
,_'

,,'

{, ,',

_':" ,

,",'j r": "

,"C

•

state of bit 12 specifies whetherlhe 'tape ''is'''f6''be read in alphanumeric mode or in binary
mod.e. The folloyving list includes only thes,tCll1dard instru.cfrons for governing the real
time control, the reader, the punch, and the 1<~'ybo.ard/printeL The, programm~r may, of
..

",:

',.1.

::.~ ,"

l~: ~; ....

'r••••• ,:.

"1', '-:";'"

.',

':'

.~:,:.~'

•

course, generate other instructions for these devi~'es by varying the config,urqtion of bits
14 to' '17.' Each iot requires only either'microseddnds 6f intern'al

processo;ti'~~eihowever,

the time. given with each ins.tructionis the, f~Jl?,e.!fequired :for thedevice to cdtrlplete the
entire operation.

Interrupt Off (8 jJsec) ...•••

•

••

•

iof

Instruction Code 700002

Clear program enable flip-flop, preventing program breaks from interrupting the normal
program sequence.
Interrupt On (8 jJsec) .........•..

•

ion

•

Instruction Code 700042

Set program enable flip-flop, allowing the normal program sequence to be interrupted by
program breaks through the interrupt logic.
In-out Read Status (8 jJsec) ..

•

••

iors

Instruction Code 700314

This instruction sets specifi c bits of the accumu lator according to the status of the various
in-out devices. The meaning of the information transferred into AC is as follows:
AC Bit

If Set

Program interruptions are being allowed.
Tape reader buffer has been . loaded but not yet read by

em rrb.
2

Tape punch ready for output.

Keyboard key struck and not yet read by a krb.

Teleprinter ready for output.

Displayed point sensed by Iight pen.

Clock count is complete.

Clock interruptions are being allowed.

The rest of the AC bits are used for the status of other optional equipment.
Clock Ski p on Flag (8 jJsec) ......•.• " . .. csf

Instruction Code 700001

Skip of clock flag is on, indicating that a clock count has been completed.
Clock Off (8 jJsec) ••.•.•..••..••.

•••

cof

Instruction Code 700004

Clear clock enable flip-flop, preventing further clock interruptions of the normal sequence,
and clear clock flag.

4-18

Clock On (8 IJsec)o

•

~ ~

••

c, o.

Instruction Code 700044

con

Set clock enable flip-flop, allowing clock to interrupt the normal program sequence, and
clear clock flago
Reader Skip on Flag (8 /-Isec)Q

000

•

Instruction Code 700101

rsf

Skip if reader flag is on, indicating that reader buffer contains information not yet read by
an rrb

Reader Start in Alphanumeric (3.3 ms).
Clear reader buffer and reader flag.

000

rsa

Instruction Code 700104

Start reader operation in a Iphanumeri c mode

eight holes of a single I ine on the tape are read into the reader buffer
completed, reader flag goes on

All

When reading is

Reader Start in Binary (10 ms). . . . . . . . . ..

rsb

Instruction Code 700144

Clear reader buffer and reader flag. Start reader operation in binary mode,.: ~oles 1 to 6
in each of three lines on the tape are read and assembled into a full computer word in the
reader buffer. A line is recognized in binary mode only if hole 8 is punched, i ~e.A' lines
with no eighth hole are skipped. Hole 7 is ignored. The reader flag goes on when a full
word has been assembled,
Reader Read Buffer, (8 /-Isec).

•••

.••••

Instruction Code 700112

rrb

••

Transfer contents of reader buffer into accumulator and clear reader flag

Pu n c h Ski P 0 n F I g (8 /-I sec) ,

•

ps f

Instruction Code 700201

Skip if punch flag is on, indicating that the punch is ready for output.
Punch Load and Start (500 to 15.8 ms) .. o. pis
Clear punch flag and load punch buffer from AC

Instruction Code 700206
_
10 17

Punch one line of tape.

If AC

is 1, hole 1 is punched; if AC

is 1, hole 2 is punched; and soon to AC
which controls
16
10
the punching of hole 8. When punching is completed, . punch flag goes on Timerequired
0

to punch is 5 milliseconds; time between lines is 15.8 milliseconds.

If a punch instruction

follows immediately after punching is completed, 15.8 milliseconds are available for the
program.

4-19

pcf

Instruction Code 700202

Keyboard Skip on Flag (8 fJsec). . • • • • • • •• ksf

Instruction Code 700301

Punch Clear Flag (8 fJsec). . • . • • • • . . . . . .
Clear punch flag.

Skip if keyboard flag is on, indicating that keyboard buffer contains a character not yet
read: by a krb.
Keyboard Read Buffer (8 fJsec). . . . . . . . . .. krb

Instruction Code 700312

Clear keyboard flag and transfer a character from keyboard buffer to AC 13-17'
Teleprinter Skip on Flag (8 fJsec). . . . . • •. tsf

Instruction Code 700401

Skip if teleprinter flag is on, indicating that the teleprinter is ready for output.
Teleprinter Load and Start (100 ms). . . . . •. tis

Instruction Code 700406

Clear teleprinter flag and print character specified by AC 13-17'
Teleprinter Clear Flag (8 fJsec). • • • • • . • •.

tcf

Instruction Code 700402

Clear teleprinter flag.
4-3

CONTROL

This paragraph describes those elements of the control unit which are not discussed under arithmetic or memory. These control elements include the timing system, state control, program
control, and the transfer logic. The symbols used in the drawings to represent the logic elements are also described.
a

TIMING SYSTEM - The fundamental timing system of the computer is based upon a se-

quence of seven time pulses, T1 to T7. These time pulses occur at irregular intervals chosen so as to optimize memory operations. There is no repetitive standard clock pulse providing a fundamental time unit for the computer. The seven time pulses follow each other
in a chain covering one memory cycle of eight microseconds. Each time pulse is triggered
through a delay from the previous time pulse. The transition from one cycle to the next is
controlled by flip-flop RUN.

If RUN is 1 the final time pulse in one cycle triggers the

first time pulse for the beginning of the next cycle. When RUN is cleared, the computer

4-20

halts at the end of the current memory cycle because the final pulse in the cycle cannot
trigger the first pulse of the following cycle'o

The organization of a single memory cycle isshown in Figure 4-20 The seven irregularly
spaced time pulses are shown from left to right across the 7. 9-microsecond cycle 0 During
each such cycle a single memory access is executed 0 The specifi c actions performed at
each time pulse depend upon the particular operation in which the memory ;cycle occurs °
The functions that control the actual memory access during each cycle are also shown in
the figureo
tions

Each memory module contains four-flip-flops which control a. set of four func-

Three of these, the read, inhibit and write fU'nctions¥ are levels that control core

driving 0 These functions are shown by the horLz:ontal Iines in the figure ~ The fourth func~
Hon

the strobe ¥ is a pu Ise that sampl~s the output at the core memory sense amp! ifi ers 007

microsecond after the initiation of the read function
b

STATE CONTROL - Major states of the computer are controlled by a quaddstable de-

vice; minor states are controlled by the instruction registero The major states device! MS,
has four outputs -- F D, E and B; these outputs represent fetch ! defer, execute and break
j

At the end of each cyclel1 one of the four inputs <to MS is pu Ised ° This asserts' the corresponding output {and negates the other three outputs} so that the computer performs the next
cycle in the appropriate major state

When the computer is in one of the program states, fetch, defer or execute, it must also be
in one of the minor states -- that is, the computer must be performing' a specific instruction
During each fetch cycle, the memory strobe transfers an instruction word from memory into
the memory buffer 0 The instruction code (bits 0 to 3) is then transferred to the instruction
register IR 0 Although for programming purposes the instruction codes are given as twodigit octal numbers, for control purposes the contents of IR are decoded by.a binary-toquaternary decodero

In the two-digit octal code, the more significant digit represents the

binary number contained in 1RO_20 The second octal digit is 0 or 4, depending upon
whether bit 3 of the instruction word (IR ) is 0 or 1
3

For the instruction regIster 11 however, the four bits are decoded into a pair of levels giving a quaternary representation of the instruction code 0 The contents of bits 0 and 1 are
decoded into one of the IA levels, lAO to IA30 The contents of bits 2 and 3 are decoded
into one of the IB levels ff IBO to IB30 The execution of each specific instruction is con-

4-21

trolled by the pair of asserted levels from the instruction decoder. Furthermore, operations
common to entire groups of instructions may be controlled by a single IA or IB level. For
example, all instructions whose binary codes begin with 00 deposit information in memory;
thus, lAO disables the memory strobe.
If the computer is performing an augmented instruction, the appropriate pulses are produced
during the remainder of the fetch cycle. The operate pu Ises are generated at T5 and T7;
the programmed in-out pulses are generated at T5, T7 and T1 .
Anyone-cycle instruction that is not deferred is completed during the fetch cycle. The
computer then remains in the fetch state to retrieve another instruction word from memory.
If the instruction is deferable, a 1 in MB 4 causes T7 to put the major states device into the
defer state. The computer then retrieves a new operand address from memory.

In a two-

cycle instruction, the fetch state or defer state is followed by the execute state, during
which the required operand reference is made to memory. At the completion of an instruction (which may occur in the fetch, defer or execute state), if a break is requested
the computer enters the break state.

In this state the required type of cycle is performed,

depending upon whether the break is a data break, a clock break or a program break. At
the completion of all requested breaks, the computer returns to the fetch state.
c

PROGRAM CONTROL - At the beginning of each fetch cycle the contents of the pro-

gram counter are transferred into the memory address register. The current instruction in
the program is then retrieved from the memory location addressed by the contents of MA.
After the address transfer, the contents of the program counter are incremented by 1. Th is
causes the next instruction to be taken from the succeeding memory location, during the
following fetch cycle.
During a skip instruction, if the skip condition is satisfied, the program counter is advanced
one extra position. This causes the program to skip the next instruction in normal sequence.
The opr skip instructions can sense the states of arithmetic unit elements; the iot skip instructions can sense flags associated with the in-out devices

Program control is transferred to a new location by loading a new address into the program
counter. The counter is loaded from the memory buffer on imp; it is loaded from the address switches for console operations; and it is loaded from the memory address register for

4-22

.' 1

. ,!

:!. .•.

; 1

';,<H"

d LOGIC SYMBOLS - The symbols used on the logic drawings are shown in Figure 4-3,
Note, that i n .~he:rectpngl e whi ch, .represents' a fl ip-flop, the a-out term inat;E'~nd the l-out
termin<?1 Fare sh<?wn twtc~"OveTthe "0" the two terminals are shown withi'fhe'polarities
they ~ave wh~n t~e fHp-Hop is itith~ a.state; over the "1'1 the two term,inals tYre shown
with the polarities they havewheh tbe flip-flop is in the 1 state. TherefO're;'lf'he '"0" and
"1" in the rectangle represent both ,the ,output terminals and the contents ort~I!1' flip-flop.
•

~,'.

',.,

.:.

:.~~.

~..

'?- ~

;..\

" ~

.. ~'.r.

'1 ~

•

... t

In the norma I convention the II a" is at the left of the rectangle and the O-outfermina I is
","... -'..

~ '."

,";~ :""'1'

represented by the left diamond in both pairs.

The two gatableinputs ?re s~own at t,h..e bottom of the rectangle with t~~~p;-il1.terminal at
: , the left~U~g~tabiedirect pulse inputs are always shown at the sid~s o.f aflip-:flop.
,

•

• •

"the example in ;hefigure a direct cle~r input is shown at the left..

,"~.'

-~'.

., Some fHp-flops, also have complement inputs. Such inputs are shown or 'the 9P'f.to.m center
,:; ,r:Qf:tre rect~ngl~< A carry;out of a flip-flop is shown at the left side. ; A d'ifecfcarry into
, q flip"'i£!op is shown at the right,

position
_

, _.

while a goted carry in is shown irftfil'eiJsLJa1"C'omplement

~ \

.. ~

': t ~ ~

'Instead of represenHng a binary dig'it, a flip-flop sometimes represents a pair of mutually ex"

•

.~.~

'1 ... ·',...-.

" clusive logi'e fu~ctions .In such a 'case the outputs are often labeled with the' ~ames of the
~.

functions rather than with usual "0" and "l II. For example, the states of the read mode the
Jlip-fl9P in reader control are read binary (RD BIN) and read alphahumeric(RD~ALPHA).
.

. .

,,". ,"

~; .

The prihcipal advantoge of havihg fourl6gical outputs to represent two o~tput terminals at
,
'
">1,' ~
two assertion 'levels' is that there: iis never any need to invert a signal' namewhi~h appears
as an input to a logic net,

Even though the computer uses inverter logic, all log'ica! con-

ditions appear"hlthe drawi'ngs' with correct truth values. When a flip-fl~p output is used
as the input to a logic net, the signal name indicates the correct state o(th~ fl ip-flop that
enables the neL
To'determine the'phySi'cal' source of the signal (i.e., the output terminal to ~hi!ch the sigf,

~'~~~,

nal line!'is' corinected) one must consider; both 'the signal name and the ass~rtion I~vel. For
1
example, the signal A at therieg~tive6sser'tion level a~tually originat~~'a·ti~h·~ l~~ut
terminal of'flip-flop A; the sign~liA!J:'6t)thegrou'nd assertion level actually ori~inat·es at

the O-out terminal of flip-flop A. The signal designation A

can thus refer to the output

signal generated at either terminal of flip-flop A, when that flip-flop is in the 1 state.

! TRANSFER LOGIC - AI! information transfers must take place between two informationstoring devi ces.

In most cases the transfer is made from one fl ip-flop register to another.

A bH of information contained in a specifi c fl i p-flop of the source register is transferred to
a corresponding fl ip-flop in the receiving register.
In memory access, information is transferred between the memory buffer flip-flops and the
ferrite cores within the memory core-bank registers.

In rotate operations information is

transferred from one fl ip-flop to another in the same register.
The operation of a 1 transfer is shown in Figure 4-4A.

In the example shown, the 1s in

M CLEAR, clears every flip-flop in M and then the transfer pulse, K l->M, sets each bit
M

in the corresponding bit K is 1. After both pulses have occurred C(M} = C(K}. Note
n

that if a 1 transfer is executed without a prior clear the final contents of M equal the OR
function of the previous contents of M and the contents of K. That is, after the pulse
K l->M, a bit M

is 1 if M was already 1 or if K is 1.
n

A 0 transfer is shown in Figure 4-4B. The pulse KO -> M clears M if K is O. This type of
n
n
transfer produces the AND function of C(K} and the original C(M} because a bit M is 1
n

after the transfer onl y if M was originall y 1 and K is 1 •
n

If a 0 transfer and a 1 transfer are executed simul taneousl y, the resul t is a jam transfer.
No clear pulse is requmred in this case because M is set if K is 1, and M is cleared if
n
n
n
K is O. The jam transfer is used in PDP-4 to sh ift information from one bit to another of
the same register; for example, in the rotation of the accumulator. In a left rotation, information is transferred from M to M

1i in a right rotation, information is transferred

from M to M l'
n
n+

A typical example of the 1 gnput gating to a fl ip-flop in a register is shown in Figure 4-4C.
I'nformation may be transferred into the receiving register from any of several source regis ....
ters whenever the appropriate transfer pulse is appl ied to the corresponding capacitor-diode
gate. If the output of the source is al ready in pulse form (e.g., the output of the sense
ampl ifiers in memory) I information may be transferred into the receiving register without a

4-24

gating level. The transfer is effected by the line labeled "direct ll in the figure. A separate pulse is required for each flip-flop in the receiving register unless the pulse is clearing or complementing the entire register. A direct input pulse may be shown in the logic
drawings as it is in Figure 4-4C, or alternat"ively, it may be shown at e'ither side above the
capad tor-diode gates.
In the logic drawings, the name of each transfer pulse is preceded by a symbol that indicates the drawing on which the signal is generated.

For example, the pulse-that transfers

information from MB to PC is generated on the PC drawing, so the p'ulse is labeled
PCMB1
4-4

PC.

ARITHMETIC UNIT

The arithmetic unit includes two full-word, l8-bit registers, a l-bit link register, and associated control circuits. The two fu II-word registers' are the accumu lator and the memory buffer .
. The memory buffer is a passive register in arithmetic unit operations -- that is, MB holds the
'operand in all two-term arithmetic and logical op~rations. The memory buffer is active only in
indexing operations which are performed independently of the accumulator.
The accumulator is active in all arithmetic unit gperations.

In either 1s complement or 2s com-

plement addition, the contents of MB and A~ are aqded together; the result appears in AC
a

ACCUMULATOR - The accumulator,isthe major register in the arithmetic unit. Trans-

fers to AC may be made from the memory buffer, the reader buffer, and the console accumulator switches.

If the computer includes the real time control, the reader buffer connec-

tions are replaced by connections from the information collector.

In this case, information

from the reader buffer and a II other input devi ces is transferred into the accumu lator through
the information co II ector. All transfers into the accvmu lator are 1 transfers requ i ring a prior
cleaL
The accumulator and the link may be rotated either right or left.

In rotate operations, AC

and L together form a 19-bit circular register with AC

linked to AC
through L. The link
17
O
may therefore be considered to be to the left of AC and to the right of AC170

The arithmetic unit can perform three logic functions. These are: logical negation, AND
(conjunction), and exclusive OR. The program may produce the inclusive OR between the

4-25

contents of MB and AC by using the negation and con junction.

In a 11 cases, the resu It ap-

pears in AC. The exclusive OR function and the AND function can be performed only with
the contents of MBi the inclusive OR function may be produced from any source register except MB, by programming a 1 transfer from the register into AC without first clearing AC.
The addition operation in 1s complement or 2s complement arithmetic is carried out in two
stages. First, a partial sum is produced by the logical exclusive OR between MB and ACi
second, a carry function changes the exclusive OR result into the true arithmeti c sum. The
number in AC at the end of the operation is the sum of the previous contents of AC plus the
contents of MB.
plementing it.

In ls complement arithmetic, the negative of a number is formed by comIn 2s complement arithmetic, the negative of a number is formed by com-

plementing the number and then adding 1 .
bLINK - The link, L, is a one-bit register that extends the capabilities of the accumulator.

It may be cleared or complemented, or rotated as part of the accumulator.

It is used

as an overflow flip-flop for 1s complement arithmetic, and as a carry link for 2s complement
arithmetic. The state of the link can be sensed by skip instructions so that the programming
of multiple precision arithmetic is somewhat simplified. Since L can be sensed it is available as a general program flag.

Products and quotients may be constructed, one bit at a

time, by uti! izing the Iink in appropriate subroutines.
c

ARITHMETIC UNIT CONTROL - The control circuits for the arithmetic unit include the

operate logic, the overflow logic, and the transfer and arithmetic pulse logic for the accumulator and the link. The operate logic includes the operate skip,logic, the generation
of the pulses that clear or complement AC or l, and the generation of the pulses that rotate AC and L to the left or right. Use of L as an overflow fl ip-flop is controlled by the
overflow logic. The transfer logic controls the transfer of information into ACi the arithmetic logic generates the pulses that perform addition
4-5

MEMORY

During every eight-microsecond memory cycle, the memory address register addresses a single
core register in the computer memory. The memory cycle is divided into two portions, a read
portion and a write portion. During the read portion of the cycle, a single la-bit computer
word is read from the addressed core register into the memory buffer. During the write portion

4-26

of the cycle, the word contained in the memory buffer is written back into the addressed core
register. For both the read and write portions of the memory cycle, the addressed cere register is specified by the contents of the memory address register
a

MEMORY ADDRESS REGISTER - a 10-, 12- or 13-bit address is transferred into MA at

the beginning of every memory cycleo This address controls memory access throughout the
entire cycle. All operations occurring in the memory during the cycle affect only the
single core register addressed by the contents of MA

At the end of each memory cycle,

MA is cleared in preparation for use during the n~>.<t cycle

Included with the memory address register in -the internal processor are four binary~to-octal
decoders. For 12- or 13-bit address decoding, each of these four memory address decoders
decodes a three-bit section of MAo For a 13-bit address, the extra bit (MA ) selects the

memory module while the outputs of the decoder~ are applied to both memory modules.
lO-bit address decoding, each pair of ?ecoder~ de~odes five bits.

In each pair, one de-

coder decodes the less significant three bits binary-to-octal; the other decodes the more
signifi cant two bits binary-to-quaternary. For all addressing the decoder outputs are applied to memory instead of the binary information in MA

.!?

MEMORY BUFFER - At the beginning of every memory cycle the memory buffer is

cleared. During the read portion of the cycle a word is read out of the memory and transferred into MB by the strobe

If new information is to be deposited in memory during the

cycle then the strobe is disabled so the read merely clears the addressed core register.

New

information can then be transferred into MB. During the write portion of the cycle the contents of MB (whether new or old) are written into the addressed memory location

In index-

ing operations the word read from memory is indexed in MB before being written back into
the core register from whence it came.
At the same time that a word is being written into memory the word is also available to the
rest of the computer from MB. During logical or arithmetic instructions, the operand in MB
is used by the accumulatorinputgating. During an iot instruction bits 14 through 17 control
the in-out operations from MB and bits 6 through 11 are decoded by the device selector

If MB contains an operate instruction word, bits 5 through 17 control the execution of the
instruction directly from MB

However, if MB contains a memory reference instruction
4-27

word, the address portion of that word is transferred to MA at the beginning of the next
memory cyc Ie.
c

MEMORY MODULE - The memory module contains a 4096 word core bank or a 1024

word core bank.

It also includes associated logic circuits for addressing memory locations,

for reading information out of memory and for writing information into memory.

In the

4096 word core bank the core regis,ters are arranged in a 64-by-64 matrix; in the 1024 word
core bank the registers are arranged in a 32-by-32 matrix.
The outputs of the memory address decoders are appl i ed to the memory: modu Ie. At the
module, these outputs select a single core register for use during the current memory cycle.
The memory control pulses from the control unit are applied to a four-bit shift register in
the memory modu Ie. The memory timing functions (see Figure 4-2) are' ge~~r~ted 'from the
outputs of this shift register. The read function makes information from the addressed core
register available to the 18 sense amplifiers. This information is sampled by the strobe,
which transfers it to the memory buffer.
"'i.'

Prior to the write function, the inhibit function applies inhibit current to all bits of the
core register that correspond to Os in MB. The write function then writes a 1 into each of
the remaining (uninhibited) core bi.ts.. Information is thus written into 'th~ addressed core
register by a 1 transfer. The write function writes ls into all bits of the core register except those bits whi ch are kept in the 0 state by an inhibit current.
4-6

INPUT-OUTPUT SYSTEM

The input-output system in the standard computer includes one input devi ce only -- a paper
tape reader. Other in-out devices may readily be added to the system by installing the type
25 real time control.
~

REAL TIME OPTION TYPE 25 - The real time option includes five se~tions. These are:

devi ce selector, information distributor, information collector, interrupt lo~i c, and in-out
skip facility. All in-out operations in PDP-4 are initiated by the programmed in-out pulses
PI01, PI02, and PI04. These three pulses are applied to the d~vice selector. A specific
set of three pulse. lines is selected according to the device code of the in-out inst'ruction
word. The three in-out pulses become iot pulses on the selected ou·tput pulse lines. The
4-28

device selector thus behaves as a 3-pole s~lector switch whose position is determined by
bits 6 through 11 of the in-out instruction

Each set of three iot pulse lines controls a parHbJlar in-out deviceo For control purposes,
the interrupt logic is treated as a device~, 'In'some' cases a complex device such as magnetic
tape requires a larger number of control pulses. Such a device is therefore treated as several devices having several device codes,o
The information distributor includes a setofbus drivers through which the 18 bits of the accumulator are made available to taperpin panels for connection to in-out devices. The
information collector is essentially an l8-channel pulse amplifiero

Information from any

devi ce buffer is transferred through the cbllector to the accumu lator whenever. the appropriate iot pu Ise is appl ied to the Ie input gating.
The interrupt logic allows the computer to perform breaks fn the normal sequence of program instructions to accommodate the needs of high~speed in-out devices, reOI time synchronization, and so forth. Three types of break'are available -- data break, clock
break, and program break

The computer does not perform breaks routinely; the break

must be requested by specific external conditions. Data breaks may be requested only by
high-speed in-out devices such as magnetic tape equipmenL The real time clock break is
requested at the 60-cycle power line frequency {every 16.6 milliseconds}. A program
break may be requested by any in-out devi cei however, high-speed in-out devices use the
program break only for control purposes.
Whenever any kind of break is requested, the computer goes into the break state after completing the current instruction

Then a,ll break requests are granted before the computer

returns to the fetch state to begin the next instruction

If severa I breaks are requested

simultaneously, the data request has first priority, followed by the clock request and,
finally, by any program requests.
For a high-speed data transfer, the device must request a data break and provide a memory
address

For data output" the computer retrieves the addressed word from memory and

makes it available to the device. For data input, the computer clears the addressed location and transfers the word provided ,by t~e device into the memory buffero
The programmer can turn the real time clock on and off by adjusting the stQte of the clock

4-29

enable flip-flop. As long as the clock is enabled., aclock request is made automatically
every 1/60 second.

Each time the request is granted, the computer indexes the number

contained in memory location 7.

If the number becomes 0 as a result of the indexing op-

eration, the clock flag is set. The flag then requests a program break to indicate that the
clock count is complete.
The programmer may also turn the program interrupt system on and off by adjusting the state
of the program enable flip-flop. A program interruption may be requested by any in-out
device. The inputs to the program interrupt system are the flags of the in-out devices
(11 input lines are available in the standard type 25)

When a program request is granted,

the computer deposits C(L) and C(PC) in memory location 0 and then executes the instruction contained in location 1. When entering a program break, the computer automatically
disables the program interrupt system.

Nested program breaks can occur on Iy if the pro-

gram enables the interrupt system within the routine that begins in location 1.

Note that

the programmer should clear all device flags before initially enabling the program interrupt system; otherwise, a device flag that is still 1 after some previous in-out operation immediately makes a spurious program request.
The type 25 real time option also provides an in-out skip facility. The flags of all in-out
devices (up to a maximum of 16) may be sensed by in-out skip instructions.

If the addressed

flag is on, the program counter is forthwith directly incremented by 1.
b

READER CONTROL - The control unit for the tape reader includes an l8-bit buffer

register RB. This buffer is loaded as information is read from the tape. When the type 25
rea I time option is used, transfers to the accumu lator from the buffer are made through the
information collector. When the reader is used alone, the buffer is connected directly to
the accumulator input gates. The reader may operate in two modes: alphanumeric and
binary.

If the reader is operating in alphanumeric mode, a single line of eight holes on

the tape is read. The eight data bits from this line are loaded into RB

- .
10 17

If the reader is operating in binary mode, only holes 1 through 6 are read, but the reader
reads three lines from the tape. The six data bits from the first line are loaded into
RB

- . As each of the two subsequent lines is read, the data in RB is shifted left six
12 17
places and the six data bits from the new Iine are also read into RB 12-17. In binary mode,

4-30

a line of tape isreadonlyifh6Ie8,is'punched~;\'J£.hole 8 is not punched, the reader skips
the line. Therefore, to construct a 'fu I Lworcf in biinary; the reader reads the first three

I ines in which hole 8 is punched. '
Each line is moved past the reader photodiodes by engaging the reader clutch. When a
signal is picked up from the feed hole, the ou-tpuf,.oT.fhe photodiodes is strobed and data is
read into the reader bufferu
character (I ine) is read

In alphanum:eric :mode:, the reader flag goes ?n after a single

However, in bh1aryrttode a two-bit counter couri::ts the characters

read from the tape and the reader flag goes on Q'nlyafter three characters have been read
Two in-out pulses, iot2and iot4, contro"there~der logic.

Pulse iot2 clears the reader

Pufse' i~t4 starts the reader; clears the flag,

flag and causes a 1 transfer from RB into AC:

the buffer, and the I ine counter; and adjusts the ,state of the read mode fl ip-flop according
, to the state of bit 12 of the ioL The reader logic.ithen loads tre buffer from information on
the tape, in binary or alphanumeric mode depending upon the state of the read mode flipflop.
When RB is loaded, the reader flag goes on and the program may transfer C(RB) into AC
with an iot2 pulse. The accumulator may be'cleare'd before the transfer by programming a
in bit 14 of the iot.
c

PUNCH CONTROL TYPE 75 - The pu~chsontro,1 unit contains aneight-bit buffer PB.

The punch , logic is controlled by two in-ou,t. pulses,'. ' .iot2,- and iot4.
The first of these pulses
.
~

.~<

clears the punch buffer and turns off the punch flag .~he second (iot4) transfers the eight
least significant bits of the accumulator into tbe,buffer, and starts the punch

Both in-out

pulses are generated by the single instruction, plso
After receiving pulse iot4, the punch control unit waits for a synchronizing signal from the
punch motor.

During the 5-mil \.isecondinterv~:d after receiving this synchronizing signal,

the control unit punches one I ine on the tape.

It does this by energizing appropriate sole-

noids corresponding to the contents of the punch buffer. At the same time, the control
unit advances the tape to the next position. ~he'1 punching is completed, the punch flag
goes on.
d

KEYBOARD/PRINT ER CONTROL TYPE 65:'- Ti~e keyboard/printer is actually two inde-

4-31

pendent in-out devices. The keyboard section and the printer section are separately controlled and separately addressed. The two control systems, line unit outgoing (LUO) for
the printer and line unit incoming (LU I) for the keyboard, function independently except
for a common timing system.
The signal provided by the keyboard and required by the printer is the standard five-element
start/stop teletype code. An element in the code may be either a mark (current flow) or a
space (absence of current). The character to be printed or the printer operation to be performed is determined by the configuration of marks and spaces that make up the five elements of the code. Figure 4-5 shows the timing relationships of the start impulse, the stop
impulse, and the five code-element impulses in the standard teletype code.
When a key is struck at the keyboard, a five-bit keyboard buffer (LU 1 - ) is loaded, one
1 5
bit at a time, with the five elements of the incoming teletype signal. As soon as the keyboard buffer is fu Ily loaded, the LU I flag goes on.

In-out pu Ise iot2 clears the flag and

causes a 1 transfer of the contents of the keyboard buffer into the accumulator. As usual,
the programmer may clear AC prior to the transfer by programming a 1 in bit 14 of the iot.
The printer control logic also includes a five-bit buffer (LUO

). In-out pulse iot4 trans1-5
fers the least significant five bits of the accumulator into the printer buffer and initiates
one cycle in the printer control logic. During the printer cycle, the printer logic generates the five-element teletype code from the information in the buffer. At the end of the
printer cycle, the buffer is clear and the LUO flag goes on.
flag, as is required before each printer cycle.

In-out pulse iot2 clears the

Both printer pulses (iot2 and iot4) are gen-

erated by the single instruction, tis.
4-7

FLOW CHARTS

Paragraph 4-8 describes the specific operations that can be executed by the computer

Each

computer operation is a chronological sequence of events. Each individual event isachange
in the state of the computer.
The flow charts show the operations as sequences of events. The rna jor states flow charts
(Figure 4-6) show the sequences that make up the various computer cycles. Each sequence begins at the top of a flow chart. Time is represented by horizontal bars on a nonlinear scale.
Each horizontal bar represents the occurrence of a time pulse. The time pulses are written in
4-32

t41hede.f:tc: hQ;~~:hcQ.llJmri O:c T~h~'Jru;e tilJ1il~LSG~ !.;~ds I~!b il}ll J:!'h:e,}l:~a¥fjg~·J?,£;·l~bff ~~g:~,I?;u."trJ/ memery
p

.. .j~

,r 4'ic

Vc:Je (Fj,gur;e. 4t12h,
i

JJ.~;:l
" f.H\f\ 1 ( .
··i',
'.

, ) .: .:;; i! i

:.3('1 ;'; i

,,::', 1,/1

;~c)E'~f~h}:V~~'t;i'b6l('phfl1Jbn"~~: :'fI6vJ~hClF!tre:~~ek~nlls jb!:~~~ueli'b~;8re\iehts" for' b ~speclfi Co' dperatien .
Arrews 'ihdi crit~\heidrr;~:~tfen ofltbw~ 'I!A~~l (va~'ibul f1~rryi1~{~ [i;es :the 'n~:e'bf:f't'6wlhPb~,dken by
·...,a:,rect8n;~Jei in';whi~h)s:,written ;th~~:p~s:;!fittfP~rqh,~~~UI;9.F~Y~~§ ,qr:,t~:~\ . J~pr~~~pensVqg\·Jime
:;;~pUhe ~;cA,U ~e,v.e,qhithgt:~.ane . ''f'/..r~,tt~n\i¥,·i thjJl>RsSjPBJEf·lh~ri·t;9!.n~tq'i~qJ\;<jJ IqOfJ:c;:tl ;~jA9~N:f~)q\o/ line

.occur at the same instant in time., "Fo.r·pwrp9;S'esiQLclarity~ certain simultaneeus events
may be shewn in separate rectangles,
Nete that in many cases the state .of a fl ip-flep (.or register) is sensed by the same time
pulse that changes the state .of the flip-fl.op being sensed. This is possible·because .of the
delay inherent in the flip-flep .or its input gating; i.e., the change in state.of the flipflep .outputs lags behind the pulse applied t.o the input gating.

Therefere the present state

.of a fl ip-fl.op can be sensed at the same time that t~e fl ip-fl.op is cleared, and the .outputs
.of a register can be used at the same time that new infermati.on is transferred inte the register.
If a specific event in a given line .of How depends .only upon time; then that event is written alone in the rectangle.

Hewever, if .other cenditiens which mayor may net be ful-

filled als.o gevern the specific event, then these .other cenditiens are alse written in the
rectangle.

The conditiens are written t.o the left.of a c.olen; the specific event caused by

the cenditions is written te the right .of the c.olen.;
In s.ome cases several sequences .of events may begin with the same partial sequence.

this case the entire greup .of sequences is represented by a single flow line shewing the
c.omm.on events.

A branch point whi6h distributes the H.ow into several separate sequences

indicates the peint atwhichtheseveraLsequencesdiverge.

Fer example, in a fetch cycle

all instructiens are retrieved fr.om memery by the same set .of events.

Hewever, after the

instructi.on cede is transferred t.o the instructien register, the sequence diverges depending
upen whether the instructi.on requires .one cycle.or tw.o cycles.

Each diverging line then

has further branch peints depending upen other c.onditi.ons.
Mevement al.ong any specific branch must depend upon the fulfillment of seme specific
c.onditien. The appr.opriate cenditi.ons are written .on the irdividual branch lines.

4-33

In all

two-cycle instructions the state of MB 4 is checked

If MB4 is 1, the major states device,

MS, is put into the defer state; if MB4 is 0, MS goes into the execute state

With the time

pulse at which this event occurs, the line of flow branches into two possible seql:lences.
One branch is followed if MB4 is 1i the other branch is followed if MB 4 is O.
In some CQses separate branches may .join, indicating that the events following the intersection point are the same for both sequences. Whenever a branch point or an intersection
point occurs, arrows are drawn on all incoming lines

A single path from top to bottom of any flow chart represents a single computer cycle. The
path is entered at the top of the chart, according to the conditions listed. At the bottom
of the chart eaen path II termJngt§9 by .g r§ference to the cycle that follows the completed
~'~UlnQflt

In tA@ mejer .§tet@§ ·flew Gh9ft§ @nJy th9se~vents that are pecu I iar to an individua I sequence
8fe §R9WA 'in th~ fjn~ 9fffsw t~rPlJ9h the chart. The events that are common to all cycles
9F@ Ii~t@e fA 9 eq'~mn at the left of the charts. These common events include the events

that me~e yp the standard memory cycle. Also common to all cycles are those events that
synchronize the interrupt logic to the main timing system.
The major. states flow charts show at I of the operations executed within computer memory
cycles. Other internal processor operations are shown at the right of Figure 4-6. A flow
chart of the chain of special pulses (SPO to SP4) is shown in the upper right of the figure.
Below the flow chart are the logical equations which define various other pulses and control levels.

In the lower right is a table of instruction decoding.

The PDP-4 input-output operations are shown in a different form

The events produced by

the in-out pulses are listed in Table 4-1. This table provides the link between the fetch
cyc Ie in-out transfer flow Iine and theflow chart of the individual in-out operations
(Figure 4-7). The sequences of events making up the in-out operations do not depend
upon any sequence of time pulses.

Instead, they depend upon signals from the in-out de-

vices or delays included within the control unit.logic.

Delays between the various events

in each sequence are shown by breaks in the line of flow; the length of the delay is written in the break.

4-34

4-8

COMPUTER OPERATIONS

The operations performed by the computer are those that make up the special pulse cunsole
functions, the memory cycle, the instruction and break sequE~nces in the major states, and the
transfer of information between the computer and in-out (~evi ces.
a

SPECIAL PULSE OPERATIONS - The operations governed by special pulses are shown

in the upper right of Figure 4-6, When power is first applied to the computer logic, the
initial state of the various computer flip-flops is indeterminate. As a result it is possible
for the initial states of flip-';:lcps at power turn-on to cause information losses by generating unwanted information transfers. A power clear pulse is used to prevent such informaHon losses. Whenever the main power switch is operated, the power clear pulse clears
the control flip-flops in the memory and in the in-out equipment control units.
All other special pulses result from using the operating keys on the console. The events
produced by these pu Ises are shown in the flow chart in the upper right of Figure 4-6,
Whenever any operating key is turned on, a logic level is asserted in the internal processor.

For all console operations except Stop, the OR function (KEY MANUAL) generates

a manual pulse which in turn triggers the chain of special pulses spa to SP4. This chain
of special pulses times the execution of the appropriate operation.

In all special pulse

chain operations except Continue, SPl also generates the initial clear pulse BEGIN " This
pulse prepares the computer for operations by clearing various registers and control flipflops throughout the system.
At the end of the chain, SP4 begins the memory cycle by triggering T1.

If the computer

is operating in the repeat mode, spa triggers a variable delay whose duration is determined
by the setting of the console speed switches

If the operating key is sti lion at the end of

the delay, the special pulse chain is again initiated by triggering spa.
b

MEMORY CYCLE - Most of the events required for the basic memory cycle are common

to all cycles and are shown in a column at the left of Figure 4-6. The memory cycle begins at T 1, with the clearing of the memory buffer and the transfer of an address to the
memory address register, The latter event is not shown as common to all cycles

Instead,

address transfer is shown in each individual cycle flow chart because the source of the address varies, depending upon the major state of the computer.

4-35

At T2 the read level is enabled by setting flip-flop R, Just prior to T3, flip-flop RS ~s
set. This produces the strobe which transfers a word hom fhe addressed memory location
to the memory buffero At T4, the read level is disabled by clearing 'flip-flop R, At the
same time, flip-flop W is seta
If the computer is operating in single step mode or the stop key is on g T5 clears fUp-flop
RUN. This flip-flop is also cleared if the computer is operating in single nnstruction mode
and is performing the final cycle of an instruction provided that no break has been syn-'
chronized in a previous cycle.
timing system.

Pulse T5 synchronizes the interrupt logic to the computer

If a break has already been synchronized,,, the break cycle is included in

the current instruction

If the break is synchronized in the final cycle of an instruction f

the computer halts before performing the break cyde,
Time pulse T5 also begins the assertion of the inhibit level by setting flip-flop L

Immedi-

ately following T5, RS is cleared. The 0 state of RS in conjunction with the 1 state of W
enables the write level

At T7, both inhibit and write levels are disabled by clearing flip-flops I and W"

If the

computer is going to continue in normal operation, MA is cleared in preparation for the
next memory cycle"

If flip-flop RUN is 0, the computer haitSo The halt takes precedence

over any other flow Iine shown leaving T7 in the flow charts"
c

MAJOR STATES - Events that occur in the cycles for each of the four major states are

shown in the main portion of Figure 4-6. Fetch cycle events {at the left} occur in two
distinct groups

The standard program control and instruction retrieva! operations are in

the first half of the cycle" Operations required for individual instructions are executed in
the second half of the cycle

If a previously executed instruction was an iot 8 the last in~out pu Ise is generated at the
same time that the norma! fetch cycle events occum The normal events indude the clearing of IR, the transfer of an address from the program counf'er to the memory address register, and the incrementing of the program counter

After the instruction is retrieved from

memory, the instruction code is transferred from the memory buffer to the instruction register. This transfer does not require a transfer pulseD

Instead ff the setting of flip-flops in

MB causes the immediate transfer of information on into IR

4-36

This type of IItransition ll trans-

fer is indicated by the letter "T" in the flow charts.
After the instruction code is transferred to IR, the flow branches into two main sequences.
The flow line for theone-cycle instructions goes ,to the left; the flow line for the twocycle instructions goes to the right. The specific events required for the execution of the
one-cycle instructions are shown at the left of the figure .In addition to the time pulses,
several control levels are involved
in the execution of ,these instructions. These control
.
levels are defined by the equations shown at the right of Figure 4-6. The flow Iine for
the in-out transfer i~structions shows the generation of the in-out pulses according to the
configuration of bits 15 to 17 <:,f the ,iot instruction word. The actua I operations produced
by these pulses, and the decoding of the device code, are given in Table 4-1 .
From the final time pulse the flow lines continue to a defer cycle or an execute cycle in
the case of the two-cye lei nstructions and the deferred Jump. For the nondeferabl e onecycle instructions, the flow line returns to another fetch cycle unless the normal program
sequence is being interrupted.
To the right of the fetch cycle is the flow chart of the defer cycle. During defer, the address of the instruction is used to retrieve another address from memory. For a Jump, this
address is used as the operand and the computer returns to the fetch state. For a twocycle instruction, this address is used to retrieve the true operand, and the computer enters
the execute state.
For all two-cycle instructions, the required memory reference is made in the execute cycle.
For most of these instructions, the strobe transfers the operand from memOI"y to MB just prior
to T3. However, if the instruction is depositing information in memory, the assertion of
lAO disables the strobe and new information is transferred into MB at T3. At the end of
the cycle, the computer returns to the fetch state unless a break is requested.
The break cycle is shown in the flow chart at the right. The Iine of flow diverges into
three branches, depending upon whether a data break, a clock break, or a program break
has been requested. At the end of the cycle the computer returns to the fetch state unless another break is requested.
d

IN-OUT TRANSFERS - When the instruction code for the in-out transfer group appears

in IR, bits 15 to 17 are decoded into the three in-out pulses. The operations executed by

4-37 ::

these in-out pu Ises are shown in Table 4-1 .
Table 4-1 inc \'udes all of the iot instructions for the type 25 real time option, the reader,
the punch and the Model 28 keyboard/printer.' The pulses governi'ng in-out informat'ion
transfers usuallyserve"only to initiate ope'rations in ci specific device control unit by clearing various control fl i p-flops. After operations are initiated, the computer continues with
other instructions whi Ie the device control unit proceeds independently with its own operations.
The input-output operations of the control units are shown in 'a separate in-out flow chart
(Figure 4-7). All in-out operations except keyboard input are initiated by the in-out
pulses. The keyboard input sequence is initiated by striking a key. There is no sequence
of timing pu Ises ,for the input-output operations; each individual event in an in-out sequence either is triggered by a delay from some previous event or else is triggered by a
signal received from thein-out device.

4-38 .

igJ~= Jnstr..uction code 70

Instruction Dec()ding
iot MB: 4

T5:

AC CLEAR

iot MB:

Tl :

PI04

iot MB:
iot

5
6

MS: 7

T7:

PIOl

T5:

Device Selection
00

Interrupt Logic:

PIOl

CLOCK FLAG: PC+ 1

PI02

1
12

: 1 -~ PROG ENABtE

MB~2: a -~ PROq ENABLE

a -~ CLOCK FLAG

PI04

MB
MB

1
. "
: 1 -~.CL~?CK ENABLE
12

a
12

: a -~ CLOCK ENABLE

Reader Logic:

PIOl

RD FLAG: PC+ 1

PI02

C(RB) V C(AC) => C(AC)

0-;;:' RD FLAG

O-:>RD RUN"
PI04

0-;:::' RD FLAG

RB CLEAR

0-':> RD
.
. 1, 2 . . :~;, . ;.;. :.'
1 -;:::. RD RUN

v' .

TIMING CHART: t~-OUT TRANSFER INSTRUCTIONS

TABLE 4-1

(Continued)

Reader Logic (cont'd):

MB: : RD BIN -~RD MODE
2

MB~2: RD ALPHA -:>RD MODE
(see Figure 4-7)

Device Selection (cont'd)
Punch Log i c :

Pial

PUN FLAG: PC+1

PI02

PUN CLEAR
assert PUN IDLE
(negates PUN 'FLAG)

PI04

assert PUN ACTIVE
(negates PUN FLAG and PUN IDLE)
C(AC

_ ) V C(PB) ~ -C(PB)
10 17

(see Figure 4-7)

Keyboard (LUI):

Pial

LUI FLAG: PC+1

PI02

negate LUI FLAG
C(LUI) V C(AC) => C(AC)

10 Status:
PI04

03
C(STATUS WORD) V- C(AC;} :(> C(AC)

TABLE 4-1

TIMING CHART: IN-OUT TRANSFER INSTRUCTIONS
(Continued)

Tel eprinter (LUO):

PIOl

LUO FLAG: PC+ 1

PI02

0 -;::> LUO FLAG

PI03

C(AC)

=> C(LUO)

START

..~' .~

(See Figure 4-7)

4'-9 USE OF DRAWINGS
The 'complete system logic is shown in logic drowi'ngs qlustrating Chapters 6, 7, 8 and 90
Reference to these drawings is essential in understanding the detailed operation of the system"
Because these drawings are the most frequently used s6ur~e of troubleshooting inform.ation, it
"

is irrlportant to be familiar with the symbols and conventions which they employ.
The standard DEC logic symbols used on the logic drawings are explained in the DEC Digital
Logic Handbook. Additional symbols used in PDP-4 drawings are shown in Figure 4-30

Each

circuit included in the logic drawings is identified by type as well as by its physical location
in the computer.
Ci rcuit type is al ways shown as a four-digi t number.

Th is number is the same type number used

to identify the circuit in the DEC catalog.
Examples:
. 5 inverters (500-kc seri es)

4105 .

5 inverters (5-mc sed es)

1105 . .

1607 . .

. "_ 3 pulse ampl ifi ers (5-mc seri es)

All circuits other than logic nets are shown as blocks on the logic drawings.

Besides the four-

digit type number, these blocks usually include a two-letter mnemonic abbreviation of the
circuit function.

4-41

Examples:

DE •

· delay

PA •

• pulse ampl ifier

PG.

· pulse generator

SD .

• solenoid driver

BD •

• bus driver

The circuit location code is lettered directly below the circuit type number. Circuit location
code is shown as a single letter preceded by one digit and followed by one or two digits.
Example:

A
the 10th plug-in unit from the left end
- ' - - - - - - - of mounting panel A
' - - - - - - - - - in bay 1 •
Terminal designations are formed by adding the pin letter to the plug-in unit location code
described above.
Example:
lAl0M - - - - - - pin M of the connector in position lAl0
Each logic drawing is laid out with rectangular map coordinates. The horizontal coordinates
are 1 to 8 (from left to right) and the vertical coordinates are A to D (from top to bottom).
Because a single drawing may contain a number of networks, coordinates are usually included
in figure references to specific networks within a logic drawing.

For example, a reference to

the circuit "in Figure 6-3B4" would mean that the circuit is located at coordinates B4 of logic
diagram 6-3 (the third diagram referred to in Chapter 6 of this manual).
Schematic diagrams for all computer circuits are bound into the back of the manual. These
schematics are arranged in numerical order by circuit type designation. All circuits illustrated
are described in Chapter 10.

4-42

CHAPTER 5

OPERATING PROCEDURES

5 -1

GENERAL

The purpose of this chapter is to provide the operator with the information needed to operate
the PDP-4 computer system. Descriptions of all controls and indicators are included, together
with the instructions covering the operation of the standard in-out equipment.

In addition,

this chapter provides general instructions for manual loading and for operating the computer
under normal conditions. These general instructions supplement the special instructions included in each program write-up.
5-2 CONSOLE CONTROLS AND INDICATORS
All of the controls and indicators of the PDP-4, except those associated with the in-out equipment, are located on the console operator control panel. This panel is divided into two sections: a panel face, which contains all the indicators and some of the operating switches; and
a panel shelf at the bottom, which contains the operating keys and the rest of the operating
switches.
When any console indicator is lit, the associated flip-flop is in the 1 state, or the associated
function is true. Most toggle switches on the operator control panel are pushed up for on (or
1) and down for off (or 0). The operating switches are either toggle switches or rotary switches.
The toggle switches are pushed to the right for on and to the left for off

The operating keys

on the panel shelf are two- or three-position momentary-contact switches with a center off
position. All of the keys produce operations when pressed down; only three of them produce
operations when Iif ted up.
The operator panel is shown in Figure 5-1 . Functionally, various switches and indicators on
the panel may be divided into the following four groups:

(1) Registers (described in ~ below). Six sets of register indicators and two switch registers. These are located in the left two-thirds of the panel face, except for the l-bit link
register, which is located at right center.

5-1

(2) State indicators

(.!: below). Four indicators located in the upper right of the panel

face. Also included is the indicator for the run flip-flop.
(3) Operating switches (~ below)

Four toggle switches with associated indicators, locat-

ed on the lower right of the panel face, and two rotary switches! located at the right of
the panel shel f

(4) Operating keys

(:!. below). Five momentary-contact switches, located at the left of

the panel shelf. The three two-position switches on the left are single logical keys -that is, each produces a single logical operation.

The two three-position switches on the

right are dual logical keys -- each switch may produce either of two operations; depending upon whether it is lifted up or pushed down

a REGISTERSRegister i ndi cators:
PROGRAM COUNTER (PC)
This l3-bit register contains the address of the next instruction in the program.
INSTRUCTION (IR)
Four-bit register which contains the instruction code of the instruction being performed or
just performed.
MEMORY ADDRESS (MA)
This 13-bit register contains the address of the previous memory access

When the com-

puter has stopped, these lights display the last address usedo This is because the normal
end-of-cycle clearing of MA is inhibited immediately prior to the halto
MEMORY BUFFER (MB)
All transfers into or out of core memory take place through th is l8-bit register. The MB
register also holds the operand for all computational instructions. Furthermore, indexing
is done directly in MB. When the computer has halted g MEMORY BUFFER indicates the
word contained in the memory location addressed by MEMORY ADDRESS.
ACCUMULA TOR (AC)
This l8-bit register is the major arithmetic and operating register in the computer and is
involved in most computer operations.

In computational instructions; the operand from

5-2

MB operates on the contents of AC. The resu Its of computations always appear in AC.
During in-out operations, AC is use~ as
a. b~ff~r for transferring
data between the computer
...
'.

' "

and an in-out device control unit.

,").

.' ~.:

1 ; '. ~ ; .

LINK (L)
This one-bit register is an extension of the accumulator for the construction of products
and quotients.

LINK also serves as an overflow flip-flop for 1s complement arithmetic, a

carry link for 2s complement arithmetic, and may be used by the programmer as a general
program flag.
Switch registers:
ADDRESS (AS)
A 13-bit toggle switch register through which the operator provides the memory address for
the console functions Start, Examine,and Deposit.
ACCUMULATOR (ACS)
Lifting DEPOSIT transfers the contents of this 18-bit toggle switch register into the memory
location addressed by the ADDRESS switches., Pre~sing DEPOS IT NEXT transfers the contents of ACS into the memory location addressed by PROGRAM COUNTER.

During the

instruction, Inclusive OR of AC Swi.tches with AC (oas), the C(AC) are replaced by the
inclusive OR function of the C(ACS) with C(AC).
b

STATE INDICATORS -

RUN (RUN)
Lit while the computer is running in normal mode.' Whenever the run flip-flop is cleared,
the computer stops at the end of the current memory cycle.
FETCH (F)
When lit, indicates that the next cycle to be performed will be utilized to retrieve an instruction word from the memory location addressed by PC.
DEFER (D)
When lit, indicates that the next cycle to be pe'rformed will be utilized to retrieve a
deferred address from the memory locatio,n addressed by the least significant 13 bits of MB.
<'

;;.

5-3

'",

EXECUTE (E)
When lit, indicates that the next cycle to be performed will be utilized to retrieve an
operand from, or deposit an operand in, the memory location addressed by the least significant 13 bits of MB.
BREAK (B)
V~hen lit,

indicates that the next cycle to be performed will be utilized to execute a data

break, a clock break or a program break.
c OPERATING SWITCHESPOWER
Pushing this toggle switch to the right turns on computer power and lights the associated
indicator. After turning POWER on, the operator must wait 5 seconds to allow the memory power suppl y to turn on before starting computer operations

When power is swi tched

off, memory power turn-off is immediate but computer power remains on for another 5
seconds

This switch normally applies power to the entire system unless a piece of in-out equipment
is turned off individually.
SINGLE STEP
If th is switch is pushed to the right the computer enters the singl e step mode, I ighting the
associated indicator. In this mode, the computer executes a single memory cycle when
START is operated. Subsequent cycles in this mode are executed, one at a time, each
time CONTI NUE is operated.
SINGLE INST.

If this switch is pushed to the right the computer enters the single instruction mode, lighting the associated indicator.

In this mode, the computer executes a single instruction

when START is operated. Subsequent instructions in this mode are executed one at a time
each time CONTI NUE is operated.

Note that if both SI NGLE STEP and SI NGLE I NST.

are on, the single step mode has preference.
REPEAT
Pushing this switch to the right lights the associated indicatori and causes operations

5-4

initiated by an operating key'tobe rep~(it~'8';di;l;o'~'~:ds:"the key is held' on. The'operations
are repeated at a rate determined by the setting of the SPEED switches

:~ '" , ..; '-',.. ' ,.-,

SPEED

These switches allow the operator to varyth'e':reipeCft"'fn~t~:rval from 40 microseconds to 8
seconds in five overlapping ranges.

The s~it~c{h~s~ii1'clude ~ five-position rotary switch and

a potentiometer knob.
d OPERATING KEYS - All of the following keys except STOP and CONTINUEproduce
the BEGIN pulse at SPl

BEGIN clears var10us r~.9;is!ers and flip~flops to preporie the
:

t ..:

>-,

" ' . / ".,.

•..•

\ computer for operation.

START
Pressing this key causes the computer to beg,io:.normal operation in the fetch state.

The

first instruction executed is taken from the location addressed by the ADDRESS switches.
STOP
'\ ('. "f'io

",,:~.

•

Pressing this key clears the run flip-flop, cau~rMg!'Hlwe computer to halt at the end of the
current memory cye! e .
CONTINUE
Pressing this key causes the compute'r' to resJme'riotrri~( operati~n, starting at the point
:indicated by the console lights. For use ih tR~' f~p~dt mode, this key ha's a catch in the
1

up posit-i'on. Li fti ng the key causes the sa~e bpM~dti'bn

•

ds; :pr~ssi'ng it, but the key rema i ns

on unti I pushed off by the operator.
EXAMINE (EX)
. • . . . •)

:. ;::'1:':.

When th is key is I if ted, the contents of the (rremory I'ocation addressed by the ADDRESS
switches are displayed in both the ACCUMULATbR ·c'nd·'MEMORY BUFFER lights

At the

completion of Examine, the MA lights display the,:,a"ddress:'of the memory location examined,
and the PC lights display the address of the: nex't'iconsecutive location
.'

EXAMINE NEXT (EXN)

When this key is pressed, the contents orthe':~Eirl\(iryqci'~~t,on add~essed by PROGRAM
"

•

'1 :'1...

:'.

>.:

t..

.1:

COUNTER are displayed in both the AC anCl:M'B'I'i~f1fs'~ ~ At the completion of Examine
Next" the MA Iights display the address of' ,the' m:eh1drYlocath);' examined, and the PC

lights display the address of the nex't consecutive location.
DEPOSIT (DP)
Lifting this key deposits the contents of the ACCUMULATOR switches into the memory
location addressed by the ADDRESS switches. At the completion of Deposit, the word
deposited is displayed in the AC and MB lights. The MA lights display the address of the
memory location holding the information and the PC lights display the address of the next
consecutive location.
DEPOSIT NEXT (DPN)
Pressing this key deposits the contents of the ACCUMULATOR switches into the memory
location addressed by PROGRAM COUNTER. At the completion of Deposit Next, the
word deposited is displayed in the AC and MB lights. The MA Iights display the address of
the memory location holding- the information, and the PC lights contain the address of the
next consecutive location.

5-3 POWER CONTROLS AND INDICATORS
Alternating line voltage is distributed to the various computer power supplies through the type
813 power control panel located on the top of the bay 2 plenum door. A separate panel is
provided for control of marginal check voltage. This panel (located at the top of the bay 1
plenum door) includes switches for applying marginal check voltage to specific portions of the
computer.' In addition, individual mQrginal check toggle switches are located on the front of
each logic panel.
~

POWER CONTROL PANEL TYPE 813 - Computer power is controlled by the POWER

switch on the operator control panel (paragraph 5-2~).

Turning this switch on activates

the power control panel type 813 at the top of the bay 2 plenum door.
The 'type 813 power control panel (Figure 5-2) contains an elapsed-time meter, three
MAl N POWER circuit breakers, and a MEM POWER toggle switch. An extra pair of circuit breakers is incl uded for special appl ications. The elapsed-time meter counts the number of hours main computer power is on. The circuit breakers and toggle switch are normally left on at all times. The thr~e MAIN POWER circuit breakers provide overload
protection to the computer power supplies. Line voltage for the entire computer goes
through these three circuit breakers.

5-6

The 813 control delays memory power turn-on

Th BS delay turns on memory power 5 sec-

onds after mai'l power is turned qn, to ensure that turn-on transients 'in the "computer do
not affect the mem.ory

<c,

The MEM POWER ~witch on ,the type 813 panel perrnits turning off

this delayed line-voltage input to the memory power supply" Memory po;\:V~r ~an thus be
turned off separate/ y from the rest of the computer for maintenance or troubleshooting
purposes.

If the system inel udes more than one memory module, the MEM POWE~. switch

controls the' delayed I ine vol tage to all the memory power suppl ies

For computer turn-off another set of delays is incl uded in the power input to the computer.
While memory power turn-off is immediate, the turn-off delay keeps ma~n. computer power
;6n for 5 seconds after the console POWER switch is turned ofL
~'MARGINAL CHECK CONTROLS - The variable power supply type 734 furnishes, mar-

ginal check voltages to the tomputero

It is located at the top of the bay 1 plenum doore

This power supply provides voltages which can vary from 0 to -20 or +20 vdc, depending
on the setting of the associated polarity switch

Output val ues between 0 and 20 volts

are controlled by a variac and monitored on the MARGINAL CHECK voltage meter (Figure
,5-3)?Line voltage for the type 734 power supply is supplied directly from the power control panel with no intervening switch.

Therefore, the marginal check power supply is on

whenever the rest of the computer is on.
The plug~in :unit' pi'ns to which marginal check voltage is applied are selected by three
toggle switches (at the left of each logic panel on the front of the bays, Figure 5-4) and
an associated three-position polarity switch (on the marginal check switch panel, Fig~re
5-3)

To make, positive marginal check voltage available to the computer, the polarity

switch is set to +10MC" Marginal voltage can then be applied to the A lines of any panel
by pushing up the top toggle switch on that pane, and to the B lines by pushing up the
center toggle switch,

For marginal check of the -15vdc lines, the polarity switch is set

to -15 Me and the bottom toggle switch of each panel being tested IS pushed.upu

Note

that" all! ines not being marginal checked receive their normal vol tages automaticall y.
Although no marginal voltage can be applied to the computer if all three toggle switches
on every panel are off (down), it is also possible to disconnect all marginal voltage inputs
by turning, the polarity switch to the OFF positionv This appl ies normal vol tages throughout the computer regardless of the settings of the toggle switches
5-7

There are five toggle switches to the right of the three-position polarity switch on the marginal check switch panel (Figure 5-3)

For all these swHches, the up position is on; down

is off. Only the first three switches on the left are used; the two on the right are spares.
The SENSE AMP switch appl ies marginal vol tages to the memory module sense ampl ifiers
These sense amplifiers take up only a portion of panel 2Do

For ease in troubleshooting,

the sense amp I ifiers are isolated from the rest of the panel and are checked independently
by the SENSE AMP switch. The rest of the plug-in units in panel 2D are marginal checked
in the usual way by the switches on the mounting panel.
Marginal checking of the sensing circuits in the photoelectric tape reader is done with the
FEED HOLE and INFO HOLES switches. To facilitate troubleshooting, separate switches
are provided for feed-hole and information-hole sensing circuits. When one of these
switches is pushed up, marginal voltage is applied to the +10 vdc lines in the corresponding circuit if the setting of the polarity switch is +10MCo

5-4 OPERATION OF IN-OUT EQUIPMENT
The three in-out devices most commonly used with the PDP-4 are a photoelectric paper tape
reader, a paper tape punch! and a Teletype keyboard/pdntero Manufacturer's manuals for
these devices are provided with the PDP-4 computer. In addition". some special instructions
and precautions are included below regarding the use of these devices as part of the PDP-4
system
~

PHOTOELECTRIC PAPER TAPE READER - The tape reader (Figure 5-5) is used by the

computer as an input device

The reader is described in the manual for the Digitronics

Perforated Tape Reader! Model 25000
(1) Reader Controls - Operator control over the reader is exercised through two
switches

The reader motor is turned on by pushing up the toggle switch located to

the left of the read head cover

In front of the cover is the ready/load switch

Turn-

ing this switch to the right (load) releases the brake so that the operator may load or
unload tape

Turning the switch to the left (ready) energizes the brake so that the

reader may be controlled from the computer. The operator must also adjust the ready/
load switch for the width of the tape loaded into the reader. For Bye-hole tape, the

switch must be pushed in all the way; for eight-hole tape; the switch r!1u'st ,be pulled
.

'~.I;...:

•

out as far as it will goo
(2) Loading - Before loading or unloading the reader, the ready/load switch must be

turned to the righL This releases the brake and prevents damage to the tape. When
loading the reader, the tape must be oriented so that it unfolds from the top of the fanfold stack and with the edge nearer the feed holes, away from the operator. The unfolded stack is placed in the right":hand tape bin

(3) Operation - Once the tape is properly loaded, energize the brake .b y:.turr}ing',the

ready/load switch to the lefto A reader iot can then control the reader~y genera'ting
appropriate signals in the reader logic. The reader run signal closes the pinch rollers,
causing the tape to move past the sensing photocells.
CAUTION
'Before running a program incl uding any reader iot's, the reader
must be turned on and the brake must be energized. Fai Iure to turn
on th~ reader wi II cause the comp~ter to hang up at the point where
the reader flag is sensed. When th is occurs, the program must be
run again from the beginning. Failure to energize the brake will
, aUowthe tape to sl ide when a I ine is read, turning further information into gibberish.
J'

(4) Unloading - After the reader has finished reading a tape, turn the ready/load

;,rs,WitchtO' the right

The tape may then be removed from the left tape bin.

(5) Coding - When reading tape in binary mode, the reader reads only the sixJeast

significant bits of each character that has the eighth hole punched, and assembl'es
three such characters into an 18-bit computer word

When reading tape in alphanu-

meric mode, the reader reads all eight bits in each character

The information read>

from the tape may be in any code. The code used by the: keyboard/printer is I isted"in'
TabJe 5";'1

b PAPER TAPE PUNCH - The tape punch, used by the computer as an output device', is
mounted inside a cabinet below the reader. The punch mechanism faces the door on the '
right of the ~abinet (Figure 5-6). The fan-fold tape is fed to the punch from a contaiher.
~., \

After punch ing, the tape is fed into the tape catcher

A slot on the front of the cabinet

(below the tape reader, see Figure 5-5) allows access to this tape catcher without opening
the cabinet door.

Punch operation is as follows

(1) Punch Controls - Operator control over the punch is exercised through two switches on the front of the punch cabinet. The punch motor is turned on by push ing the
toggle switch up. Located above the toggle switch is a red button

Holding this

button down feeds tape through the punch with only the feed hole punched.
(2) Loading - Turn off the punch motor, then load the tape into the punch as shown
in Figure 5-6. After the tape has been proper! y positioned through the device, turn
the punch on, and hold down the tape feed button long enough to feed approximatel y
18" of leader. Make sure the tape is feeding and fol ding proper! y in the tape catcher.
CAUTION
Before running a program including any punch iot's, the punch must
be turned on Failure to do this will cause the computer to hang up
at the point where the punch flag is sensed. When this occurs, the
program must be run again from the beginning
0

(3) Unloading - To remove a length of punched tape from the tape catcher, first hold
down the tape feed button long enough to provide an adequate leader at the end of
the tape (and also at the beginning of the next length of tape) .
Reach into the tape catcher slot and remove the fan-fold tape. Tear off the tape at a
point within the leader area (that portion of the tape with only feed holes punched).
After removal from the catcher, the stack of folded tape should be turned over so that
the beginning of the tape is on top, and then ~beled

Make sure enough leader is left in the tape catcher to make at least three folds, with
the first fold towards the catcher opening.
perly inside the bin.

This ensures that the tape will stack pro-

If necessary, hold down the tape feed button to provide addi-

tional leader e
c TELETYPE K EYBOARD/PRI NTER - The keyboard/printer is two devices: the keyboard
for input, and the printer for output.

In most cases the operator communicates with the

5-10

computer through the keyboard/printer, especial Iy when debugging a program

The keyboard/printer motor is controlled by a toggle switch mounted on the cabinet at the
right of the keyboard

Pushing ~h~ ~witch to the right turns on the motor

Complete in-

structions for install ing paper and ribbon in the '\printer are given in Teletype Specification

57595.
Figure ?-7 shows the ke~board.

The code for the Teletype chorac.ters iSl isteq'in Tabl e

5':"1~' Ope~ating any of the regular keys on the keyboard prints the corresponding character and sends the corresponding code into the .~omputer

Operating the: figure' shift key

"'(FI GS) causes the keys to print figures and symbols.o The letter shift key (LTRS~ returns the
, machine to alphabetic printing

Operating the unmarked key in the lower right of the

; keyboard sends the code 00 into the computer

The computer or keyboard can lock the

, keyboard by sending the code 00 twice if) succ~ssion

" The special keys located across the top of the keyboard do not send signals into the computer.

The keyboard lock key (KBD LOCK) locks all of the regular keys on the lower part

of the keyboard.

The keyboard may be unlocked by pressing KBD UNLK

Holdi·ng down the repeat key (REPT) causes any regul,lar key that is hit to repeat continuously until REPT is released.

5-11

Character

TABLE 5-1

TELETYPE-.CODE

Octal Code

Character

Octal Code

Bell

16
22 :.

B
C

Space

Carriage Return

Line Feed

Figure Shift

Letter Shift

5-12

Holding the local line feed key (LOC LF) causescontinlJous paper feedout. This feedout
is about three times as fast as the standard line feed key repeated.
CAUTION
Before running a program that includes any printer iotis, the printer
must be turned on. The logic for the outgoing Iine unit generates
its own completion pulses. Failure to turn on the printer will cause
the computer to execute the entire program without actually printing anything.

5-5

COMPUTER OPERATION

The computer may operate in anyone of the following three modes: normal mode, or either of
the two manual modes, single step or single instruction. Furthermore" the computer may simultaneously be in the repeat mode.

In this mode the computer repeats any operation initiated by

an operating key as long as the key is held down.
In addition to the three operating modes, the computer performs four independent console operations: Examine, Examine Next, Deposit, and Deposit Next. These operations are initiated
by the corresponding operating keys, and may be performed in the repeat mode. The operator
must uti Iize these operations for manua I loadi ng .
a

MANUAL LOADING - In order to begin operations with an empty memory, the operator

must load initial information into the computer manually. Manual loading utilizes the ACCUMULATOR and ADDRESS switches, and the DEPOSIT and DEPOSIT NEXT keys.

Infor-

mation so deposited may be examined by using the EXAMINE and EXAMINE NEXT keys.
Although the operator may load any desired instructions or data into the computer, a simple, 11-instruction manual loader is listed in paragraph 5-6~o This loader reads perforated
tape in a special format and is usually utilized to read in a larger block format loader. The
larger loader then may be used to read in full programs and data

The manual loader reads the tape in binary mode. The first set of three lines and every oddnumbered set of three lines on the tape are control words. The second and all even-numbered
sets of three Iines on the tape are data words.

If a control word is a dac instruction, the

loader deposits the following data word in the location addressed by the control word.

5-13

Following the final data word is an extra control word.

If this instruction is jmp, the com-

puter enters normal operation at the location specified by the jmp address. The instruction
may also be hlL The final control word must be followed by a dummy last word if the programmer wishes the tape to stop after termination of the manual loader.
The operator shou Id put the manual loader in the top of the memory

In this position, the

routine is less Iikely to be destroyed during normal operation.
b

NORMAL OPERATION - The START key initiates normal mode operation.

It is also

used, in conjunction with the manual mode toggle switches, to initiate operations in a
manual mode. When START is pressed the computer starts in the fetch state; thefirst instruction access is made to the location specified by the ADDRESS switches.
When the computer is operating in normal mode, it can be halted by pressing STOP. Always press STOP before operating any other key.
If the computer has been halted while in normal mode, it can be restarted by pressing
CONTINUE. This causes the program to continue where it left off.

Note, however, that

whenever a halt is followed by any operation that changes the state of the computer (such
as Examine or Deposit), the computer must be started as at the beginning of normal mode
operation

The address of the next instruction must be set into the ADDRESS switches be-

fore START is operated.

5-6

OPERATOR1S CHECKLISTS

The following checklists are provided for the operator's convenience. Checklists are included
for loading the manual loader, and for operating the computer in normal mode, in either
manual mode, and in repeat mode. Special instructions for running a particular program may
be found in the write-up of that program.
a

MANUAL LOADER - To place the manual loader in the top of the memory, follow the

steps below in the order given:

5-14

(1)

Turn off all ADDRESS and ACCUMULATOR switcheSo Make sure the mode switches

SINGLE STEP, SINGLE INST. and REPEAT are all off.
(2)

Set address 7762 into the AD DRESS switches. Lift DEPOS IT .

(3)

Load the octal code 700101 into the ACCUMULATOR switches, and press DEPOS-

IT NEXT. Continue this process for all of the instructions in the manual loader. For
each instruction, set the octal code into the ACCUMULATOR switches and press DEPOS IT NEXT. The manual loader routine is as follows:

Location

Octal Code

Mnemonic

7762/r,

7763/

700101

rsf

/ reader wait loop

7764/

607763

i mp.-1

/ wait for word

7765/

700112

rrb

/ read buffer

7766/

700144

rsb

/ read another word

7767/

627762

imp i r

/ exit subroutine

7770/

700144

rsb

/ enter here, start reader

Remarks
/ stored address

in binary
7771/g,

107762

ims r

/ get control word

7772/

047775

dac out

/ deposit control word

7773/

407775

xct out

/ execute final control
word

7774/

107762

7775/out,

7776/

607771

(4)

ims r

/ get data word
/ stored control word

imp g

/ continue

Examine the memory locations containing the manual loader to make sure that

the routine was inserted properly. Set address 7762 into the ADDRESS switches and
lift EXAMINEo The contents of the addressed memory location are displayed in the
MB and AC lights. Each successive memory location may then be examined by pressing EXAMINE NEXT.

5-15

.!: NORMAL MODE ,~ To operate the computer in normal mode" follow the steps below in
order given

This checklist assumes that the computer already contains a program whIch

may be the manual loader (~ above)

n) Turn off aU ADDRESS and ACCUMULATOR switches

Make sure the mode swHches

SINGLE STEP ff S~NGLE INST. and REPEAT are all ofL
(2) Check program write~up for in-out equipment needed for the current program run.
Where needed!, load the equipment with the required tapes" etc,
(3) Turn on all ~n~-~~.,::~~quipment to be used during program rune

Failure to do this

wi II cause the computer t'O hang up or run without actual I y performing the requnred
informaHon transfers

The entire program must f,hen be repeated from the begunning,

(4) S'et address of Hrst instruction into the ADDRESS switches.
(5)

Press START,

(6) Check program write-,up for any special instructions to be followed during the
program run>
(7) To hal t the computer l press STOP
TI NUE

To conf'inue wah the program" press CON-

However f If the state of the computer has been changed after the hal t (such

as by an examnne or deposit operation), proceed as for starting l1 from step 40
c MANUAL MODES ~ T6 operate the computer in either of the manual modes; follow the
steps below in the order given.

This list assumes that the computer is already loaded with

an appropriate program,
(1) Turn off all ADDRESS and ACCUMULA TOR switches

Make sure the mode switches

are all off.
(2) Turn on the appropriate manual mode switch, S~ NGLE STEP or SI NGLE I NST"
Note that if both switches are on simultaneously; single step mode takes preference.

5-16

(3) Check program write-up for in-out equipment needed for the current program run.
Where needed? load the equipment with the required tapes, etc.
(4) Turn on all in-out equipment to be used during program run
will cause the computer to hang up.

Fai Iure to do th is

The entire program must then be repeated from

the beginning.
(5) Set address of first instruction into the ADDRESS switches

(6). Press STARTo The computer will perform a single memory cycle if SINGLE STEP
is on, or a single instruction if SI NGLE I NST

is on

(7) For each subsequent cycle or instruction, press CONTINUE.

The computer will

stop after every cycle or instruction.
(8) To leave the manual mode, turn off the manual mode switch that is on. To complete the program in normal mode, press CONTI NUE

However, if the state of the

computer has been changed after leaving the manual mode/1 proceed as for normal
mode starting (~above, step 4).
d RE,PE,AT MODE - If an examine or deposit operation is being repeated, no stored program is necessary.

If repeating in normal mode or in a manual mode, it is assumed that the

computer is already loaded with an appropriate program. When repeating in single step or
single instruction, the computer will halt after each memory cycle or each instruction,
respectively.

If repeating in normal mode, halting of the computer must be handled by the

program.

(1) Turn off all ADDRESS and ACCUMULATOR switches

Make sure the mode switches

are all off.
(2) Set the SPEED switches to the desired repeat interval

(3) If repeating in a manual mode, turn on the appropriate manual mode switch,
SI NGLE STEP or SI NGLE I NST.

5-17

(4) If repeating program operations (i .e., in normal manual mode) prepare the in-out
equipment as stated in

.!: and.:. above.

(5) Set address for fi rst memory access into the ADDRESS switches.
(6) To repeat Examine, turn on REPEAT and then lift and hold EXAMINE.
To repeat Deposit, set the desired word into the ACCUMULATOR switches, turn on
REPEAT, and then lift and hold DEPOSIT.
To repeat Examine Next, lift and release EXAMINE.

Then turn on REPEAT, and hold

down EXAMINE NEXT.
To repeat Deposit Next, set the desired word into the ACCUMULATOR switches, and
lift and release DEPOSIT.

Then turn on REPEAT and hold down DEPOSIT NEXT.

clear the entire memory, set the SPEED switches to the shortest repeat interval, turn
off all ACCUMULATOR switches, turn on REPEAT and hold down DEPOSIT NEXT.
This procedure wi II clear the 4K memory in less than 1/5 second.
, To repeat Start, turn on REPEAT; then press and hold START.
To repeat Continue, press and release START; then turn on REPEAT and lift CONTINUE. The up position of the CONTI NUE key has a catch, so the operator need not
hoi d the key on

(7) To leave the repeat mode, turn off REPEAT.

5-18

CHAPTER 6

CONTROL

6-1

GENERAL

The control unit of the PDP-4 computer incl udes all the logic used to govern the following
functions: timing of operations within the computeru transfer of information within the central
processor, execution of the program and of individual instructions within the program, operation of the various registers, and storage and retrieval of information from memoryo The present chapter describes those portions of the control logic that provide overall control of computer
operations, including console control, timing, control of computer states, in-out transfer control, and program control

Certain portions of the control unit are discussed in other chapters

The arithmetic unit control

circuits, which govern all computational operations and accumulator transfers l are included in
the discussion of the arithmetic unit (Chapter 7)

The memory address register and the pulse

logic that controls the core memory and the address and data transfers are incl uded in the system (Chapter 8)

The control elements described in the present chapter are shown in three logic drawings u Figures 6-1 I 6-2, and 6-3. For information on the use and organization of these drawings, refer
to paragraph 4-,90

6-2

GENERAL CONTROL FUNCTIONS

Genera! control functions of PDP-4 are shown in Figure 6-1 0 These functions control the
operating mode of the computer and the initiation, timing u and hal ting of computer operation
a

CONSOLE CONTROL - The operator may control the computer through the keys and

switches located on the console

The keys start and stop computer operations! while the

swif'ches allow the operator to turn the computer on and off and to control the mode of
computer operation

The power~c1ear logic associated with the power switch is shown in the lower right of

6-1

Figure 6=,1. Re!ays D1 and D2 are located in the type 813 power control panel

When the

power switch ns turned on ll terminal F of plug-in unit 1B16 is temporarily grounded
pin F os at ground, pulses are produced by the power clock

Wh8!e

The first power clock clears

the run fIDp·~fiop so that the application of power to the computer cannot cause It to go
into nor'ma! operatnon
power~c!ear pulses.

While pin F is at ground and RUN is 0, the power clock generates

These pulses clear various control fl ip-flops in the memory and the

in-out equipment in order to prevent accidental information transfers.
When power ns turned off g pin F is again grounded temporarily, producing the power clock
and the power~c!ear pulses as at power turn-on

The clearing of RUN causes the computer

in stop at the end of a memory cycle, so that no information is lost from memory even if

power ~s turned off accidentally while the computer is running, such as, for example p by
pun !ng the pi ug out of the wall.
The nnputs to the 10gHc from all the keys and several of the switches are shown in the lower
left of F!gure 6= 1

The computer uses levels derived directly from most of the keys and

swHches u but the Dnput !ogic also generates a number of functions from combinations of the
switches ~n order to govern events that are required by two or more operations

There are seven logkal keys dedved from five momentary-contact switch levers

Thl.s is

because two of fhe switches may produce one or the other of a pair of operations, dependHrng on whether the lever is lifted up or pushed down. Of the seven key functions, SIX
iniHate operations within the computer, wh8le the seventh halts the computer. Five OR
functions are generated from the initiating keys to control operations common to two or
more keys

For example, a word is retrieved from memory on both of the operations Exa-

mine and Examine Next, while a word is deposited in memory on both of the operations
Deposit and Deposit NexL KEY MANUAL is the OR function of all the six initiaHng
keys.

This functnon trnggers both the special pulse chain and the main timing chain.

other OR functions generated by the input logic are as follows.
EXEXN
DPDPN
EXEXN + DPDPN
START + EX + DP

6-2

The

The stop key is ORed with the level from the single step switch to produce RUN STOP.
Whenever the RUN STOP level is asserted, the computer is stopped at the end of the current memory cycle by clearing the run flip-flop
order to end normal operation

The stop switch asserts RUN STOP in

The key function is asserted onl y when the momentary-

contact stop lever is pressed. However, RUN STOP is asserted continuously when the single step toggle switch is on, so that the computer stops' at the end of every memory cycle
that is initiated by a key.,

The single instruction switch also generates RUN STaPf but

only during the final cycle of any instruction

This is effected by the function F SET which

indicates that the next cycle the computer is to perform is a fetch cycle and~ therefore,
that the current cycle must betFi'e final cycle of the instruction being performed.

In single

instruction mode, a break cycle may be performed as part of either the preceding instruc- .
tion or the following instruction, depending upon the time of break request synchronization.
The output of the repeat switch is inverted and used with the speed control (B6).

The speed

control incl udes both a five-position switch and a pot wh ich allow the operator to vary the
repeat interval from 40 microseconds to 8 seconds
b

SPECIAL PULSES - The initiation of any operation from the consol e is control Ied by a

chain of special pulses, SPO through SP4
Figure 6-1, B5 to B8.

The logic governing this pulse chain is shown in

If any initiating key (ie any key other than stop) is turned on, the

assertion of KEY MANUAL triggers pulse generator 1 B09 which in turn produces SPO. This
special pulse clears RUN and triggers the ten-microsecond delay in 1 B13.
This delay allows the computer to complete the current memory cycle~ in case an initiating
key should be operated while the computer is running

After the computer has stopped~ the

positive pulse output of the delay, SPIP, triggers the remainder of the special pulse chain,
SP1 through SP4. These are a" negative pulses! one microsecond aparL

Note, however,

that the pulse amplifiers in the chain produce both the pulses and the delays between them
Each pulse ampl ifier is set to produce a one-microsecond output pulse. The fall ing edge
of the output is the special pulse; the rising edge, one microsecond later~ triggers the next
pul se ampl Hi er in the cha in.
The chain of special pulses, SPO through SP4, initiates computer states before the regular
memory-cycle timing chain begins at SP40

In Examine, Examine Next~ Deposit, and

6-3

Deposit Next the computer executes onJy one memory cycle following the specnal pulse
chain; in Start and Continue the computer enters the normal operating mode

In addition to' producing individual functions for the specific console operations", SPl also
triggers the BEGIN pulse on all initiating operations except Continue (A2)
initial clear which prepares the computer for operation

BEGIN is an

Since Continue initnates opera=

Hons according to the present state of the computer! no initial clear is requDred 0
~n repeat mode/1 the operation produced by any initiating key is repeated over and over

again as long as the key is held on 0 If the repeat switch is on:,· t~,e terminatDon of the ten~
microsecond level from delay 1 B13 triggers the integrati"'ng 6n~~shot, I NT

This delay re~

mains in the 1 state for an interval determined by the settingo,ri'the console speed switches
At the end of the delay interval I NT returns to the 0 state', triggerin~ SPQ, provided one of
the initiating keys is on (KEY MANUAL). Thus the operation initiated by a particular key
is repeated over and over at a rate determined by the operator

TiME PULSES - The main timing system of the computer is a chain of time pulses l Tl

through T7

These time pulses occur at irregular intervals throughout the 709 - microsecond

memory cycleo The time pulses are generated from the chain of time gate flip-flops/1 TG

(Figure 6-1, A3 to A7). An extra time gate TGPC 1 enables the execute7
cycle incrementing of the program counter during the isz instruction.
through TG

When operations are initiated from the console the special pulses control the various functions that must precede the first memory cycleo These functions include the clearing of
the time gates by SPl Po Once the initial operations are complete, the memory cycle is
started by SP4. This final special pulse sets TG /1 generating'Tl The first time pulse"
1
delayed by 1 .0 microsecond in delay line 1A09 (B2) and the various gates; clears TG and
1
sets TG . The setting of TG generates T2. In this way fl a single 1 bit is rotated through
2
2
the chain of time gates, successivel ygenerating each pulse in the chaon 0
0

The seven time pulses and the times at which they occur in the memory cycle are listed
above the t!me gates in Figure 6-1
the memory cycle; Figure 4-20

These time pulses are also shown in the diagram of

Each pulse in the chain triggers' the TIME ROTATE pulse

through one or both of the delays shown in Bl and B20 TIME ROTATE produces the next
time pulse by clearing the single time gate that is in the 1 state and setting the next time

6-4

gate 0 The intervals between the time pulses are all either 100 microsecond or 103 microseconds, depending on whether onl y one or both of the delay I ines are used. Time pulses

1, 2, 5 and 6 are delayed 1 00 microsecond; time pulses 3, 4 and 7 are delayed 1 .3 microseconds

back into TG ,
7
1
the entire cycle requiring 7.9±0.1 microseconds. However, T7 produces TIME ROTATE
The memory cycle is repeated over and over, by rotating the 1 from TG

only if RUN is 1

The computer is halted by clearing the run flip-flop (.:!. below). This

prevents repetition of the memory cycle.

Note, however, that the timing chain can be

broken only at T7. Therefore, no matter when RUN is cleared, the computer halts only at
the end of a full cycle.
As well as the seven time gates that control the time pulse chain, an additional time gate
is provided to control the incrementing of the program counter 0 The same TIME ROTATE
that produces T3 also sets TGPC.

The TIME ROTATE that produces T5 also clears TGPC.

The only way in which the memory buffer can be cleared between T3 and T5 of the execute
cycle of isz, is by being incremented to zero. Thus if MBa is cleared while the condition
1
E·ISZ TGPC is asserted, the program counter is incremented (paragraph 6-5~ s
0

RUN CONTROL - The computer operates in the normal mode with one memory cycle

following another while the run flip-flop is 10 Each time the memory cycle ends, T7 triggers T1 of the next cycle, causing the computer to continue

Whenever RUN is cleared,

the current cycle is completed and the timing chain ends at T7.
Initially RUN is cleared by the power clock, to prevent the computer from going into
normal operation when power is turned on. The flip-flop is also cleared by SPO so that the
computer always halts before beginning any operation initiated from the console.
The operations Start and Continue put the computer into normal operation by setting RUN
at SP30

Because none of the examine or deposit operations use the normal mode, RUN

remains clear for the single memory cycle of these four operations 0
When the computer is operating, RUN may be cleared by the operate instruction Halt
(OP1 0MB: 2) or by T5 if RUN STOP is asserted. RUN STOP governs the hal ting of the
computer in the single step and single instruction modes, but it is also asserted whenever
the stop key is operated.
6-5

6-3

MAJOR STATES

Every memory cycle that the computer performs must be perform'ed in one and onl y one of four
major states. These states are fetch, execute/l defer and break

The state that the computer

is in during any given memory cycle depends on the state of the four-state device shown in the
upper left of F!gure 6-20 This major states device, MS/l has four inputs and four outputs. When'=
ever a positive-going pulse appears at any input, the corresponding output is asserted and the
other three outputs are negated.
The state of MS is stabilized by the four type 4115R diode gates in 1 Cal.
is an OR gate· for ground levels, and an AND gate for negative levels

Each of these gates

A positive-gonng pulse

on a single input asserts the corresponding output and negates the other three outputs by satis'~
fying the OR-gate condition at the diode gates to the other three sections of the device

Sat~

isfying the OR gates in these other three sections generates three negative levels which satisfy
the AND-gate condition in that section of the device whose output is asserted

Satisfying

this AND gate continues to assert the corresponding output even after the input pulse has dis-'
appeared.
For example g if the computer is next to perform a fetch cycle, one of the input gates in B2
must be satisfied!! producing a positive-going pulse at 1 D03P

This cuts off transistor 1C02F /l

asserting the output level F, and satisfying the diode OR gates in the other three sections of
the device at inputs 1Cal U, P and F .. The ground outputs of these diode gates cut off transis~
tors lC01V/l Rand K, producing negative levels which disable outputs E, D and B, and satisfy
the AND~gate conditions at the fourth diode gate, 1Cal W, X and Yo The negative output of
this fourth diode gate turns on transistor 1Cal Z, holding 1C02F at ground, and continuing to
assert ,F

The conditions that cause the computer to enter each of the major states are described in .:!.
through ~ belowo The computer normally changes state at the end of the memory cycle, ie
at T70
a

FETCH - When MS asserts the output FI the computer is in the fetch state and the cur-

rent memory cycle is utilized to retrieve an instruction word from memoryo The conditions
that cause the computer to perform a fetch cycle are shown in Figure 6-2, B1 and C1

In the console operation Start l normal operation of the computer begins with the fetch

6-6

cycle. In normal operation, the computer enters the fetch state at the completion of every
instruction (ie, if no difer cycle or execute cycle is called for) provided there is no break
requesto The computer also returns to the fetch state, from Tl of the execute cycle of the
instruction Execute

In this fetch cycle, the computer interprets the operand of Execute

as an instruction to be executed
b

EXECUTE - When MS asserts the output E, the computer is in the execute state g and

the current memory cycl e is uti Iized for the memory reference of a two-cycle instruction.
The conditions that cause the computer to perform an execute cycle are shown in Figure
6-2, C2 and C30
The computer enters the execute state on any of the examine or deposit console operations.
This is because the memory cycles performed in these two types of operations are performed
as the execute cycle of the instructions Load Accumulator and Deposit Accumulatorp respective/ y

In normal program operation, the computer enters the execute state at the

completion of the fetch cycle of any two-cycle instruction that is not indirectly addressed
(lA3 MB~).
0

If a two-cycle instruction is indirectl y addressed, then the computer automat-

ically enters the execute state after the defer cycle is completed.
c

DEFER - When MS asserts the output D, the computer is in the defer state, and the

current memory cycle is utilized to retrieve a deferred address from memory.

The condi-

tions that cause the computer to enter the defer state are shown in Figure 6-2C3o The computer enters the defer state following the fetch cycle of a deferrable instruction if the indirect address bit MB4 is 1. The deferrable instructions include all of the two-cycle instructions (lA3) and the one-cycle instruction Jump (which is included in the condition by
ORing IBO with IA3).
d

BREAK - When MS asserts the level B the computer is in the break state and the current

memory cye! e is uti! ized to perform a data break, a clock break, or a program break

The

conditions that cause the computer to perform a break cycle are shown in Figure 6-2C4o
The computer enters the break state if a break request is received from the interrupt logic
and the current memory cycle is the final cycle of the instruction being performed (ie, the
computer is not entering either the defer state or the execute state)

6-7

6-4

INSTRUCTION CONTROL (MINOR STATES), .

When the computer is in any of the three majorstates fetch, execute, or defer" it must also be
in one of the minor states; that is, the computer must be performing some specific instrucHon.
The minor state of the computer is determined by decoding the contents of the instruction reg~
ister. Th is register contai ns the four-bit code of the i nstructi on currentl y bei ng executed.
In addition to the levels provided by the instruction aecoder, the augmented instructions are
further decoded into sets of pulses which perform the indicated microinstructions. The in-out
transfer pulses are' described here (~ below); the operate pulses, 'however, are described with
the operate logic {paragraph 7-5~.
a

INSTRUCTION REGISTER - When the computer is in one of the major program states"

the minor state is defined by the contents of the instruction register. The computer IS put
into a specific minor state by loading the instruction code into the instruction register dur'ing the fetch cycle. The computer then remains in the same minor state unti I the next fetch
cycle; unless a break cycle occurs first.
The instruction register and associated control circuits are shown in Figure 6-2, C5 to C7

The instruction register is cleared initially by BEGIN. It is then cleared at T1 of every
fetch cycle and break cycle. In the latter case, the register is left clear throughout the
cycle. The instruction register is also cleared at T1 of the execute cycle of the instruction
Execute; since the computer is returned to the fetch state at the same time that IR is cleared,
the instruction code portion of the operand retrieved .during the memory reference of xct IS
loaded into the instruction register by the fetch cycle.
The four-bit instruction part of any word that is retrieved from memory during a fetch cycle
(ie an instruction word) is loaded into the instruction register. The transfer of information
from MB to IR is not performed on a time pulse. Instead, both registers, IR and MB, are
cleared at the beginning of the fetch cycle. Then, if any bit of MB is set during the fetch
cycle, the drop in the 1 output of the MB bit sets the corresponding bit of IR.

In this way

the instruction code that is loaded into MB by the memory strobe is then loaded immediately
into IR without waiting for a time pulse.
In addition to loading an instruction code during every fetch cycle, codes are also loaded
into IR for certain console operations and for the instruction Call Subroutine.. In an

6-8

examnne operation; IRl is set, producing the instruction code for Load Accumulator (20)

in a deposDt operation, 1R3 is set, producing the instruction code for Deposit Accumu~ator
(04)

immediately following the fetch cycle of calf IR2 is set by 20---> MA" producing the in~
struction code for jms. Thus at the same time that address 20 is loaded unto MA" the minor
state swHches from cal to jms and the computer completes the instruction as ims 20
b

~NSTRUCTION DECODER - The outputs of the IR flip-flops are applied to the diode

decoder shown in the upper ri gh t of Figure 6-2

Th is decoder produces two sets of four

levels each. The four levels, lAO through IA3, correspond to the four numbers that may be
contanned in the two more significant bits of IR (lR ' IR ) The four levels IBO through
O
1
iB3 correspond to the four numbers that may be contained in the two less signincant bats of
0

~R OR211 ~R3)

The unstruction decoder does not produce command levels that correspond to ondividua!
gnstructoons

Instead, each of the eight levels lAO through IA3 and IBO through iB3 corre-

sponds to a group of four instruction codes

For example" lAO is asserted when lRO and ~Rl

contaon 00. Level lAO thus represents those instructions with octal codes 00, 04, 10 and
14 {corresponding to four-bit codes 000 0,000 1,0010 and 0011 respectively)

The more

signifHcant digit in the octal code corresponds to the octal number contaoned in IR _
The
O 2
less significant digit in the octal code is either 0 or 4, depending upon whether the least
0

significant bit of the four-bit instruction code is a or 1 •
Accordungly! the octal codes for the instructions do not correspond to the potput levels
from the instruction decoder.

The numbers as the ends of the level designations correspond

to the four~bit codes expressed in a quaternary number system

In the control CDrcuHs

that execute the various operations within an Anstruction, the single onstructoon must be
indacated by ANDing one of the IA levels with one of the iB levelso In other words g the
final decoding onto individual instructions is done in the control circuits., rather than at
the onstruction decoder.
However 11 the i evel outputs from the decoder are in many cases used to control operaHons
common to a group of instructions. For example ll in all one-cycle instructions IRa and IRl
are both 1

As a resul t, the computer may enter the execute state onl y on the condition

6-9

IA3. Information is deposited in memory during the execute cycle of any instruction fin
which both IRO and IR1 are 0; consequently the memory strobe is disabled by the assertion
of the level lAO.
Both lAO and IA3 are needed by the computer logic in polarities opposite to those un which
they are produced by the instruction decoder. The inversion of these two levels is shown
in 07. Buffering of the 0 output of IR3 is also shown

This level is buffered for use !n

arithmetic unit control.
c

~ N-OUT TRANSFER CONTROL -

All transfer of information between the computer and

in-out devices as controlled by microprogramming within the iot instruction. This control us
exercised through the in-out pulses and the clear-accumulator level (Figure 6-2, 02 to
04). When the instruction code for an in-out transfer is loaded into IR, decoder levels
IA3 and IB2 are asserted. This enables the diode gates in the lot logic

The programmer determines which in-out pulses (PIO) are generated by adjusting the con=
figuration of bits 15 through 17 of the iot instruction word. If bit 17 is a 1, the Hrst in~out
pulse is generated by T5. Similarly, bits 16 and 15 generate PI02 and PI04 at T7 and 1'1,
respecHvelyo The clear-AC level PIOC1 is generated by a 1 in bit 14. This level is
appl ied directl y to accumulator control (paragraph 7-55,). In preparation for the transfer
of onformation into the accumulator, PIOC1 causes T5 to clear AC.

If the real time option type 25 is incl uded in the computer, the device selector (paragraph
9-20 decodes bits 6 through 11 of the iot instruction word to determine the in-out device
that is addressed. The device selector actually selects the device by switching PIO pulses
1, 2 and 4 into lot pulse lines 1, 2 and 4 for the specified device.
In the standard computer, no decoding of bits 6 through 11 is required because the single
lot instructoon contro!s only the reader. In thus case, the PIO pulses are applied directly
to the reader control unit. Furthermore, PI02 is appl jed directl y to the input gaHng of
the accumulator (paragraph 7-2~. Since the standard machine contaons no information
collector" the outputs of the reader buffer are apploed directl y to the accumulator input
gates.

6-10

6-5

PROGRAM CONTROL

The program control elements comprise the program counter and the associated count !oguc and
transfer logic.

Each instruction in the program is retrieved from the memory location addressed

by the contents of the program counter. The program counter is stepped one position during
each fetch cycle. This causes instructions to be taken from consecutive memory locations.
The programmer controls the program sequence by means of the skip instructions and the jump
instructions. The skip instructions cause the computer to skip one instruction in the normal
sequence if a specified condition is satisfied. The skip is implemented by advancing the pro'~
gram counter one extra position. The jump instructions can transfer program control to any
chosen location. This transfer is accomplished by loading a new address into the program
counter.
a

PROGRAM COUNTER - The program counter is shown in the upper hal f of Figure 6-30

This counter is composed of type 4204 dual fl ip-flops that are connected in the carry con~
figuration.
FI ip-flops in the counter are numbered to correspond to bits in the address portion of the
instruction word. The configuration of the counteras shown is that required for use with an
8K memory.

In this case, PC

is not used, while PC holds the required 13-bit address.
4
5 17
For use with a 4K memory, plug-in unit 1 D15 (bits 4 and 5) is removed, and PC then
6 17
specifies a 12-bitaddress. For use with a 1K memory, plug-in units 1B15 and 1B16 (bits 4
through 7) are removed and the remainder of the register holds the required 1O-bit address.
Normal counting and skipping in the program counter are produced by the pulse PC + 1 •
This counting pulse increments the program counter because the program counter fl ip-flops
are connected in a carry configuration. This means that whenever a carry pulse changes
PC from 1 to 0, PC generates a carry pulse that complements PC l'
n
n
nPrior to the transfer of any information into the program counter through the gated set in=
puts, PC must be cleared through the direct clear inputs. Addresses may be transferred
into the program counter from bi ts 5 th rough 17 of the memory buffer, the memory address
register, and the address switches.
b

PROGRAM COUNT LOGIC - The program counting pulse PC + 1 is generated by the

6-11

logic shown on the lower right of Figure 6-30 This pulse increments the counter both for
ordinary counting and for skipping. To count memory locations in the program" in a pro~
gram break" in certain console operations, and in the subroutine-calling jump" the program counter is incremented by PC + 1 0 The standard program counting occurs at Tl of
every fetch cycle. in any examine or deposit operation PC + 1 is pulsed by SP4. Thus
after performing one Examine or Deposit operation, the operator may examine the contents
of the next memory location or deposit information into the next memory location without
operating the address switches 0
in a program break or a subroutine-call ing jump, program control is always transferred to
the location that follows the deposit location of the address of the interrupted program.
For th is reason" the program counter is incremented at T5 in the execute cycle of Jump to
Subroutine or Call Subroutine, or in a program break cycle.
All other advances of the program counter cause the computer to skip an instruction. In an
operate group skip instruction, if the addressed condition is satisfied, PC is incremented by
OPl (paragraph 7-5~.

During indexing operations PC is incremented if the index number

becomes zero during the instruction. Th is condition is indicated to the program count logic
by a change in MBa from 1 to a while TGPC is 1 during the execute cycle of isz

The time gate is asserted from T3 to T5. The only way in which MBa can change from 1 to
a between these two time pulses (while E·ISZ is asserted) is by incrementing the memory
buffer to zero. The other two-cycle skip instruction, sad, causes a skip if the contents of
the accumulator differ from the contents of the addressed memory location 0 After the first
exclusive OR is executed in sad, PC +1 is pulsed by T5 if the accumulator does not contain
zero.
The gate that controls on-out skips depends upon whether or not the real time option is
installed. In the standard computer a skip is produced by Pial if the reader flag ~s on.
But if the computer incl udes the type 25 option, PC is incremented by the pulse from the
in-out skip logic (paragraph 9-2.=)
c

PROGRAM TRANSFER LOGIC - All transfers of program control are effected by clear-

ing the program counter and transferring a new address into it

Following the transfer"

PC counts successive memory locations in the usual manner. The program counter transfer

6-12

logic utilizes the following four pulses (lower left f Figure 6-3):
PC CLEAR
The program counter is cI eared immediatel y prior to the transfer of an address into it, Any
of the conditions that produce an address transfer (see below) clears the counter at the time
pulse or special pulse immediatel y preceding the transfer

PCMB1-:>PC
An address is transferred from the memory buffer to the program counter at T6 of Jump.
PCMA1-:>PC
An address is transferred from the memory address register to the program counter at T4 in
the execute cycle of jms or cal, or in a program break cycle. This causes a routine to
begin at the memory location that follows the deposit location of the address of the interrupted program.
PCAS1-:>PC
An address from the consol e address swi tches is provided to the program counter at SP2 of
the operations Start, Examine, and Deposit.

6-13

CHAPTER 7

ARITHMETIC UNIT

7-1

GENERAL

The standard PDP-4 arithmetic unit includes two full-word (l8-bit) registers and a link. The

I ink is a one-bit register that extends the capabil ity of the accumulator. The two full-word
registers are the accumulator /l AC, and the memory buffer, MB
and logical operations, the memory buffer is a passive register

In two-operand arithmetic
AI though MB makes one of the

operands available to the accumulator input gating and the arithmetic unit control logic/l MB
itself is not affected by the operation

All operations performed on the operands during two-

operand instructions are actual! y executed In the accumulator

However i in SIngle-operand

instructions y both arithmetic registers are active; logical negation IS performed in AC/l and
indexing is performed in MB.
This chapter describes the accumulator, the link/l and associated control circuits. The memory
buffer is described in detail as part of the memory system (paragraph 8-3) 0 The control elements
associated with the arithmetic unit and described in this chapter are the overflow logic, the
operate logic, and the logic nets that generate ,the various control pulses for the accumulator
and the I ink

The arithmetic unit is shown in two logic drawings, Figures 7-1 and 7-20 For information on
the use and organization of these drawings/l see paragraph 4-90

7-2

ACCUMULATOR

The accumulator is composed of 18 type 4203 fl ip-flops (Figures 7-1 and 7-2)

Each of these

18 fl ip-flops has a gated complement input as well as the usual 0 and 1 gated inputs

In the

figures/l three inverters and ten capacitor diode gates are shown associated with each accumulator flip~flop

These inverters and gates are all contained within the flip-flop module

well as the usual buffered 0 and 1 outputS/l each accumulator flip-flop also has both a carry
output and an indicator output. The carry output is an unbuffered 0 outputo The fall of this
output is used as a pulse for the bit-to-bit "ripple" carry in addition operations (~ below)

7-1

Except for ripple carry connections and single-bit pulse connections from the information collector, every accumulator control pulse is applied to the input gates of all bits in the registero
The ripple carry output for each bit is applied only to the next more significant bit of the
register

Level gates for transfers from the memory buffer, the reader buffer, and the console

accumulator switches are applied to each accumulator bit from the corresponding bH of the
source register

If the machine includes a type 25 real time option, the reader buffer connections are replaced
by single-bit pulse inputs from the information collector.

Each bit of the accumulator also

receives outputs from the stages on either side as level gates for rotate operations.

The accu-

mulator and I ink are rotated together as one 19-bit register; thus, for rotate operations! both
ACOand AC

receive level gates from the link.

The outputs of the accumulator fl ip-flops are used for arithmetic and transfer operations as we! I
as for rotate operations. The a outputs of the AC bits are appl ied to the AC arithmetic input
gating, while the 1 outputs are applied to the transfer input gating of MB. If the real time
option is installed, the 1 outputs of AC are also available to the output equipment through the
information distributor.
Four types of accumulator input gating are described in the present paragraph. These are: 1)
transfer gating, 2) rotate gating, 3) logic gating, and 4) arithmetic gating.
a

TRANSFER GATES - Transfers to the accumulator may be made from the memory buffer f

the reader buffer u and the console accumulator switches

If the computer inc! udes the

real time option! the reader buffer connections are replaced by connections from the information collector

In this case, information from the reader buffer and all other input

devices is transferred into the accumulator through the information collector. Since all
transfers into the accumulator are 1 transfers, a prior clear is required

The AC CLEAR

pulse cI ears the enti re register by pul Sl ng the a input of every fl ip-fl op (Figure 7-1 B6) .
The 1 transfer of the contents of MB into AC uti! izes the pulse AC XOR MB. Th is pulse
complements a bit of AC if the corresponding bit of MB is 1 (B6). This operation produces
the exclusive OR function of the contents of MB and AC (c below). However u in the
instructions lac and law, AC is automatically cleared before AC XOR MB is pulsed. Accordingly" the exclusive OR pulse sets any bit of AC which corresponds to a 1 in MB,

7-2

thereby effectivel y produc ing a 1 transfer~'
The 1 transfer of the contents of the console accumulator switches into AC as produced
through the bottom row of input gates by the pulse ACS1-~ AC (Figure 7= 1C6). In either
of the console deposit operations, this transfer pulse !s automat!cally preceded by a clear,
as required . However, as part of an operate instruction . . ACSl-7AC actual! y produces the
incl uSlve OR of the contents of ACS and AC unless the programmer mncroprograms the
operate instruction to incl ude a prior clear..
In the standard machine, the 1 transfer of the contents of the reader buffer onto AC 8S pro~'
duced by the in-out pulse P102 (C6). However u Of the computer ~ncl udes the real time
option, the reader buffer connections are removed and all transfers from input equipment
to AC are made through the information col! ector

All gating is performed in the coli ector

so that the transfer of information from IC to AC is made by slngle~bit pulse inputs through
col umn 6 of the taper pin block that is shown below the accumulator input gating.
pulse from a bit of IC sets the corresponding bit of AC

Each

Note that the standard transfer

from RB as well as all transfers through the real time option are 1 transfers requiri ng a prior
clear. This clear is not automatic and must be provided by the programmer through microprogramming the. in-out transfer instruction
~

ROTATE GATES - Two rotate pulses are appl ied to the accumulator input gating. These

are AC RI GHT ROTATE,and AC LEFT ROTATE (Figure 7-1 C6)

Each of these pulses pro-

duces a cycl ic one-place sh ift of the contents of the accumulator: one to the right, the
other to the left. In rotate operations, -the accumulator is a 19--bit circular register with
through the link (paragraph 7~3) As a result[1 for rotate purposes,
17
the link may be considered to be to the! eft.of AC and to the right of AC
O
17

linked to AC

Both rotate pulses are appl ied to both the 0 and 1 input gates of all fl ip-flops in the accumulator. On a right rotation, the gating levels to a specific bOt of AC are provided by
the next more significant bit. In a left rotaHon u the gating levels to a specific bit of AC
are provided by the next less significant bit

The rotate pulses produce a bit~to-bit jam

transfers in AC. For example, on a right rotation, AC

cI eared If AC

is set if AC

is 1 fI while AC

is 00

The pulse AC RIGHT ROTATE transfers the contents of AC

into AC

'uO

n+a

The right rotate

into the Iink, and the contents of t.he !ink
17
The pul se AC LEFT ROTATE transfers the contents of AC n into AC n'"'" 1 The

operation also transfers the contents of AC
; nto AC

left rotate operation also transfers the contents of AC
the I ink into AC
c

into the I ink, and the contents of

LOGIC GATES - The computer can perform three logic functions; these are logical

negation, AND (conjunction), and exclusive OR.
OR of two words by using negation and conjunction

The program may produce the inclUSive
0

However, the augmented instructions

that transfer information into AC from the accumulator switches or input devices do not
include an automatic prior clear. Failure to microprogram the required clear causes these
instructions to produce the incl usive OR of the contents of AC and the source register.
These instructions, however, can transfer information into AC only from external sources.,
not from memory.
The accumulator complement pulse AC CMA produces the logical negation of the word in
the accumulator. Pulse AC CMA changes the state of each bit in the accumulator by
pulsing the complement input. In 1s complement arithmetic, logical negation is equivalent
to the arithmetic negative. If the contents of the accumulator are interpreted as a number,
the compl ement pul se produces the 1s compl ement negati ve of that number

The other two logic pulses produce the logic function of two words; one in the accumulator, the other in the memory buffer. The resul t appears in the accumulator. The excl usive
OR function of the contents of MB and the contents of AC is produced by the pulse AC XOR
MB (Figure 7-1 B6). The exclusive OR function is produced by complementing a bit of AC
if the corresponding bit of MB contains 1. The state of an AC bit after AC XOR MB depends
upon the initial state of that bit and the state of the corresponding bit of MB as follows:
MB

AC (original)

AC (final)

o
o

o
o
As can be seen from the table above, the complementing of a bit of AC (if the correspondi ng bi t of MB is 1) produces the excl usive OR function.

7-4

if all bits 1n the accumulator are original! y O.f the fi nal contents of AC are the same as the
contents of MB; thus, if AC is cleared prior to the exclusive OR operation.f AC XOR MB
effects a 1 transfer of the contents of MB into AC (see.:!, above)

AC XOR MB is also the

Hrst of a panr of pulses which produce addition in the accumulator ° AddHRon is produced

by partial addition followed by a carry funcHon
exclusive OR funcHon

(5! below)

The parHal addRHon is equIvalent to the

The AND function of the contents of MB and the contents of AC is produced by the 0 transfer AC MBO-7AC ° This pulse clears those bits of the accumulator which correspond to
bets of MB containing O. An AC bit contains 1 after AC MBO=-->AC only H it contained 1
before the pulse occurred and corresponds to a bH ~n MB which also contanns loin this
way t-he 0 tTansfer produces the bit-by~bH logical AND funcf'ion of MB and AC
d

AR~THMETIC GATES - The accumulator !ncl udes two arithmetic gates °

enables the bit,-to-bH ripple carry chain

One of these

This gate is used both on 1s complement and 2s

complement addition operations, and is appl ied to all bits in the accumulator

The other

arithmetic gate is used only in 1s complement addition, and is applied only to AC

The addition operation is carried out in two stages ° The first is a partial addition; the
second is a carry function

The partial addition IS performed by the AC XOR MB pulse

whIch produces the exclusive OR function of the contents of MB and the contents of AC
(:, above)

After the partial sum (ie the resul t of the partial addHion) has been formed the

full register carry pulse, AC CARRY, changes the excl usive OR into the hue arHhmeti c
sum ° At the end of the operation, the number represented in the accumulator is the precontents of the accumulator pi us the contents of the memory buffer °

VIOUS

The partial sum is equal to the true aTithmetic sum for any bit wh,:ch does not receive a
carry

H a sum of two binary numbers is considered on a bit~by~bH basls y the exclusive

OR function of the two numbers is actually the correct sum in a g/iven bH if there HS no
carry ~nto that bit ° For example, the sum of two Os is 00 The sum of 1 and 0 is 1 ° The
partial sum g ie the exclusive OR funfction y of two 1s is 0 (this last example, however, does
require that there be a carry into the next' more signHicant ba) °
A given bH of the partial sum is valid as a bit' of lrhe true arithmetic sum provided that no
cartry !nto the bit is present. But if there is a carry into the bit

/,l

then that bH of the

partial sum is the opposite of the correct bit of the arithmetic sum. After the partial sum
is produced, the full-register carry function changes the states of all those bits of the
partial sum which are incorrect as bits of a true arithmetic sum

The full-register carry pulse, AC CARRY, produces the correct carry function both by
complementing certain bits in the accumulator and by initiating the ripple carry at those
bits that it complements. The full register carry complements (ie carries into) a bit of the
partial sum if the next less significant bits of the summands were both 1

The computer cannot sense the previous state of a fl ip-flop, so instead it senses the corre=
sponding configuration of the partial sum

This produces the same resul t because AC XOR

MB, which produces the partial addition, changes the state of AC only if MB is 1 if
n
n
after the partial addition there is 0 in AC and 1 in MB , then both bits must originally
0

have been 1. The carry therefore compl ements AC

1 if MB

is 1 and AC

is 0 after the

excl usive OR is formed.

If AC CARRY changes an accumulator bit from 1 to 0, the carry output of that bit (an un~
buffered 0 output) becomes asserted negative. The carry output of each AC bit is appl ied
to a gate at the complement input of the next more significant bit. The drop in the carry
output acts as a pulse at the capacitor-diode input gate. The gating level for these complement input gates is AC CARRY ENABLE

This gating level is applied to the ripple

carry complement input gates in all AC bits.
In addition operations, the AC CARRY pulse is generated while AC CARRY ENABLE is
asserted

Thus the partial addition of two 1s in the given bit of the accumulator produces

a carry pulse into the next more significant bit. The carry pulse ripples up the register
unHI a 0 bit is complemented

The complement pulse from either type of carry function

(AC CARRY or the carry pulse produced by a bit changing state) complements a bit whether
it is 0 or 1, but a 0 inhibits the ripple carry from propagating to the next bit.
Addition in the accumulator is performed in the following manner: The MB XOR AC pulse
produces in the accumulator a partial sum of the contents of MB and AC. The carry pulse
then initIates the carry chain at each place in the partial sum where the next less signif~
icant bH is a 0 resul ting from the partial addition of two 1s.

Each section of the carry

chain propagates as far as is necessary to produce the correct sum of the contents of MB

7-6

and the odginal contents of AC

The second arithmetic gate is the AC ADD ENABLE gate 0 This gate ITs applied only to
It is asserted only in 1s complement addition when AC IS 00 ~n the last stage of
17
O
the accumulator g AC , the gating level for AC CARRY is asserted whenever AC ADD
17
ENABLE is asserted and MBO is loin 1s complement arithmetic? the addltRon of t'wo neg-

ative numbers requires that 1 be added to the least signHicant bH of fhe accumulator.

is 0 and MBO is 1 after the excl usive OR pulse g then these bits must both have been
O
1 original! y. In other words, the numbers in AC and MB were both negative before the

addition. In this case AC CARRY complements AC

, adding 1 to the least s!gnHicant

bi t as requi red 0
The ripple carry appl ied to AC

is the AC END CARRY 0 In 1s complement' addHion oper17
ations g th is pulse is generated by the rippl e carry output of AC
If the state of AC
O
O
changes from 1 to 0 as the result of either the full-regIster carry or the ripple carry during
0

, adding 1 to the least
17
significant bit of the accumulator 0 That this arithmetic logic does In fact produce the

a 1s complement addition! AC END CARRY complements AC

correct sum of two binary numbers is proved in paragraph 7-4 below

The link, Lv is a type 4203 flip-flop module containing a basic flip~flop and t'en capacitordiode input gates.

It is used to extend the capabilities of the accumulator.

complemented g or rotated as part of the accumulator

~t may be cleared,

The I ink serves as an overflow fI 'p,-flop

for ls complement arithmetic, and as a carry link for 2s complement adthmetic 0 Since the state
of the link may be sensed by skip instructions g the programmMng of multiple precision arithmetic
is greatly sumplHied

The IDnk is cleared by BEGI N whenever any operation os initiated from the console

Program

control over the IBnk undividually is exercised through two operate Hnsh>uct~ons: Clear link and
Complement link.

These are represented in the link logic by the condHHons OPl oMB! and

1
OP2 oMB 16g respectivelyo Since the programmer can control the state of Lg and can also sense
its state through operate skip i~structions! the link is available as a general program flag

The program may also control the I ink as part of the accumulator through the two operate rotate

7-7

instructions. The AC rotate pulses are gated into the 0 and 1 link inputs by levels from AC
and AC

. On AC rotations to the right, the rotate pulse is gated by the state of AC

17
L is set or cleared in a right rotation if AC

is 1 or 0, respectively

17
left rotate pulse adjusts the state of L according to the state of AC .
O

O
Thus,

17
On the other hand u the

Three arithmetic gates affect the link. First, in 1s complement addition, if the accumulator
overflows v the AC ONE COMP OV level is asserted. With this level asserted, T1 complements
L if it is O. The effect is to set L at T1 of the cycle following a 1s complement addition when
the accumulator has overflowed.
The second arithmetic gate appl ied to L is the AC CARRY ENABLE level. This leve!, asserted
in both 1s complement and 2s complement addition, gates the link carry pulse, L CARRY; into
1 input of the link. This carry pulse is generated only in 2s complement addition when the state
changes from 1 to O. In other words, the Iink is set if, as a resul t of a 2s complement
O
addition, the sign of the accumulator changes from negative to positive
of AC

The third arithmetic gating level gates AC CARRY into the link 1 inpuL This level, L TAD
ENABLE, is asserted only during 2s complement addition when AC

is 0, and MBO is 1 The
O
assertion of this level at the time of AC CARRY implies that, before the exclusive OR pulse;
0

both AC and MBO were loin other words, in 2s complement arithmetic, if the signs of both
O
MB and AC are negative prior to the addition, the full register carry sets the Iink ..
The three arithmetic gates for the link together have the following result: (1) L is set by a 1s
complement addition overflow; (2) L is set if a 2s complement addition changes the sign of the
accumulator from negative to positive; (3) L is set by the 2s complement addition of two negative numbers.

7-4

ADDITION ALGORITHM

Both 1s complement and 2s complement addition are possible in the PDP-4. The two algorithms
corresponding to these operations are described in ~ and.!: below.

ONES COMPLEMENT ADDITION - Assume that originally the accumulator contains

Ai and that the memory buffer contains B

Assume further that PS is the partial sum pro-

duced in AC by the AC XOR MB pulse, and that S is the arithmetic sum of A and B° For

7-8

convennence u first consoder!' the slimp!e case where A and B are both posiHve binary fractnons whose sum os less than ~ (He ~herre fis no overfl.ow)

After the AC XOR MB pu!se,9 a bnr of the pm"Ha! sum PS
and on~y H/l therens no carry ynto S

3S equal. to a bH of the sum S Hv
n

Shoulld there be a carry Ento S ! then fhe parHa!

equa~s the complement' of Sn
Because both srgns are plus and there is no su'gn
n
change" there os no carry onto PS~ 7 Therefore PS
= S17
17

sum bUt PS

To understand theoperatoon of the two cany funcHons (fun regnster cany /l and dppl e
canyL dhdde PS ~nto sectDons§ starHng at the rnghL

The firrst section starts wHh PS

wnlich satisfies *~he conditions PS

17
The

= O! Ak = Bk = 1
k
second sectoon starts with PSk~,'~ and extends to the ne>d bit that satisfnes the same condi-

and ends at the FUrst bH PS

Hons as PS

Proceed ~n thi:s way '~hrough the entire partial sum

Since there can be no carry Into HII the least sNgnHicant bit of the parHa! sum must be
correcL If thlis bH h 1; or H H !s 0 resul fDngfrom the part~al addition of two Os#, then
there HS no carry out generated

Because no carry exisf'S; the next bH of the partial sum

must also be con'ecL Proceed wnth each more slgnHicant blif' of the parHal sum unHI a
Us' reached whuch u's 0 resuh~ng from *'he partBal addition of two 15 Bit PS is also
k
k
correct'; thereforre.7 a! I bilts of the parHa! sum in the FUrst section are correcL
bH PS

Because the partna'! sum r:n PSi<, generates a carry /l PSk~ 1 !S not correct
section!s carrned'nnto PS

A lfrrom the first

kE,l by thefun~reglst'e~ carr)" pulse AC CARRYo If PS k _ 1 I's 1

(resu~'t!ngOfrom the parHa~ addit~on of 0 and 1

L then there must be a carry into PSk~'2.

Th os carry IS provuded by the ripple canry ~h ich complements PS .,2 when PS _ changes
k
k 1
from] to 0.' ~n thus wayu thedpple caury propagates up ihe reg~ster untDi a 0 bat is encountered

if thus 0 HS the ~'eslJh of the pm'tHal additnon of two OS,9 then no further carry

os generated

An fu~,ther bUs are correct' up t'o the next' 0 that resuu ts from the part~al addi-

Hon of two] s; that ~Sl' dp *'0 the end of the section

~f the 0 that termITrJotr'es the riipp~e carry resul ts from the partial adduf'ion of two ls R then

there must be a cony ont'o HTe nex.f' bilL However p the partial addHnon of two 1s is the
condH!on that ends ~he sectlion

The fu! !='regist'er carry pulse then beg~ns a new dpple

carry H!1 the next secHono The carry operat'ion complement'S all incorrect bits of the
parHa~ sum

At, the comp~eHon of the carry operatfion the resul t S Us the correct sum of

A and B.
The preceding exampl e shows that the addition al gorithm works for the simple special case
of two positive numbers. Before proving the algorithm for the remaining cases {including
negative operands) four further necessary facts should be understood:

1) The sign bits are included in the partial addition -- that is, the partial sum of two
m0n us s i g ns (1 s) is a p Ius s i g n (0).
2) Both carry functions are appl ied to the accumulator sign bit (AC ). The sign bit is

treated precisely as though it were a next more significant bit of AC.

3) The full register carry complements AC

if two negative numbers are added
17
4) If the sign changes from minus to plus in the carry operation, the ripple carry propagates into AC

. This is an end-around carry.

Assume that the binary point is to the left of the most significant bit -- that is, all compu~
ter numbers are 17-bit fixed-point fractions. The computer representation of the positive
number x is therefore

+. [x J
where the brackets enclose the number contained in AC _ • The sign of th is number is
l 17
contained in AC •

In 1s complement arithmetic the negative of a number is produced by subtracting the number
from a number that is all h. This is done by changing the sign and subtracting the magni17
tude from (1 - 2- ). The computer representation of the number -x is therefore
-.[1_x_2- 17 J
Let x and y be positive 17-bit fractions. Four different cases of addition are possible:
Case one:

x+y

Case two:

(-x) + (-y)

Case three:

x + (-y) ; y ~ x

Case four:

x + (-y) ; y > x

Case one ff the addition of x and y, is discussed above in the basic description of the addi'~
tion algorithm. Addition proceeds as follows:

+. [x J
+0 [y ]

+.[x+yJ

7-10

If (x + y) ~ 1, the overflow changes the sign during the carry operation. Consequentl y, if
the addition of two positive numbers resul ts in a negative answer, it is apparent that the
sum has exceeded the capacity of the accumulator . When such an overflow occurs, the
contents of AC represent the number
-.[x+y-1]

In case two, the addition of (-x) and (-y), the partial addition and all carries except the
sign-bit carry operations would produce the following result:
-17
-.[1-x-2
]
17
_.[1_y_2- ]

+.[1 +1_x_y_2- 17 _2- 17 ]
The partial addition of two 1s in the sign bit causes the full register carry to complement
-17
AC , adding 2
to the contents of the accumulator If (x + y) < 1, the carry overflows
17
into the sign bit. The complete result is:
17
- . [1 - (x + y) - 2- ]
0

which is the computer representation of -(x + y) .
If (x + y) ~ 1, there is no carry into the sign bit. In case two (two negative operands), the
absence of a carry into the sign bit indicates that the result of the addition overflows, ie,
that the sum exceeds the capacity of the accumulator. Consequently, if the addition of
two negative numbers resul ts in a posi tive answer, it is evident that the sum has exceeded
the capacity of the accumulator. The accumulator then contains the number:

+. [1 - (x + y - 1) _ 2- 17 ]
The sign is pi us, and the magnitude is the compl ementof (x + y - 1) .
In case three, the addition of x and (-y), where y is less than x, the partial addition and
all carries except the sign-bit carry operations would produce the following result:

+. [x]
_.[1_y_2- 17 ]
-.[1 +x_y_2- 17 ]
Because y ~ x, it follows that (1 + x - y) ~ 1. Therefore the carry overflows into the sign
change (- to +) causes an end-around carry. The complete result is:
+.[x-y]
Since, in case three addition, the signs of the operands are different, the sum can never
7-11

exceed the capad ty of the accumulator
same reason

This is also true of case four adduHon v for t'ne

~n case fou~! the addition of x and (-yL, where y is greatercthc;m x, the parHa! addition

and all cordes except the sign-bit carry operations would produce the fo!!ow~ng resu~ t~

+ [x]'
0

_0[1_y_2- 17 ]
-17' ,
-0[1 +x-y-2
]
Because y > x!! it follows that (l + x - y) < 1

As a conseqljence, there is no overflow or

end-around carry and the above resul t is the computer representation of the negative num=
be r x - y, 0e - (y ~ x)
b

TWOS COMPLEMENT ADDITION - As in the discussipn of 1s complement arHhmetoc

above., assume that originally the accumulator contains A, and that the memory buffe~' con-~
tanns B

Assume further§ that PS is the partial sum produced in AC by theAC XOR MB

pulse., and that S us the arithmetic sum of A and B.
The function of the full-register carry, AC CARRY, and the ripp;1 ecarry us exactly the
same as described above for 1s complement addition. In other words, the algorHhm de'~'
scribed above for the addition of two positive numbers in 1s complement arHhmetk ~s
identical to the algorHhm in 2s complement arithmetic for the addition'oftwo posHive
numbers~

In 2s complement arithmetic, however, addi'tion involving negative operands

differs

Before proving the algorithm, for the cases including negative operands three fur-

ther characteristics of 2s complement addition should be understood:

'J) The sign bits are included in the partial addition -- that is, the partial sum of two
minus signs Os) os a plus sign (0).
2) Both carry funcHons are applied to the accumulator sign bit (AC )

treated precisely as though it were a next more significant bit of AC
3) Neither carry function affects AC
applied to AC

The sign bH ~s

. The fuli register carry, AC CARRY!! us not

; and there is no end-around carry from AC

into AC

Assume that the binary point is to the left of the most significant bit -- that is!! all compu~
tel" numbers are 17-bit fixed-point fractions.

in 1s compl ement ad thmeti c, the negative

of a number is produced by subtracting the number from a number that is ai I 1s"

7-12

~ n 2s

complement arithmetic, however .. the negdtlveof a number is produced by subtracting the
number from a number that is all Os
magnitude from 1

Th ~s IS done by changing the sign and subtracting the

The computer representaHon of the number - x is therefore ~

-o[l-x]
The four possible cases of addition of two posHive 17-bit fractions are:
Case one:

x+y

Case two:

(-x) + (-y)

Case three:

x + (-y); y~x

Case four:

x + (-y); y>x

Case one, the addition of x and y, is discussed in the basIc descriptfion of the addition
algorithm for 1s complement arithmetic (~above)
sent the number + [x + y].
0

operation

The contents of AC after addition repre~

If (x + y) ~ 1, the overflow changes the sign during the carry

Consequently, if the addition of two positive numbers results in a negative

answer, it is apparent that the sum has exceeded the capacity of the accumulator. When
such an overflow occurs, the contents of AC represent the number
-o[x+y-l]
In case two, the addition of (-x) and (-y)" the partial addition, and ali carries except the
sign bit carry operations would produce the following result:

[1 - x ]

[1- y]

[1 + 1 - x - y ]

-~---

If (x + y) < 1, the carry overflows into the sign bit. The complete result IS:
-. [l-x-y]
wh ich is the computer representation of -(x + y),
If (x + y) ~ 1, there is no carry into the sign biL In case two (two negative operands),
the absence of the carry into the sign bit indicates that the resul t of the addition overflows, ie, that the sum exceeds the capacHy of the accumulator. Consequently, if the
addition of two negative numbers resul ts in a positive answer, H is evi dent that the sum
has exceeded the capacity of the accumulator

The accumulator then contains the number

+ [l - (x + y - 1) ]
0

. 7-13

In case three, the addition of x and (- y), where y is less than x, the partial addition and
all carries except the sign bit carry operations would produce the following result:

+. [x J
-.[l-yJ
-.[l+x-yJ
Since y .::: x, it follows that (1 + x - y) ~ 1. Therefore the carry overflows into the sign;
and the complete resul t is
+.[x-yJ
Because, in case three addition, the signs of the operands are different, the sum can never
exceed the capacity of the accumulator. This is also true of case four addition, for the
same reason.
In case four, the addition of x and (- y), where y is greater than x, the partial addition
and all carries except the sign bit carry operations would produce the following result:

+. [x J
-.[l-y]
-o[l+x-y]
Because y > x, it follows that (1 + x - y) < 1

As a consequence, there is no overflow

and the above result is the computer 2s complement representation of the number x - y,
ie - (y - x) .

7-5

ARITHMETIC UNIT CONTROL

Arithmetic unit control includes all the logic nets that generate the control pulses for the accumulator and the I ink. Also incl uded is the overflow logi c for 1s complement addition! the
carry I ink logic for 2s complement addition, and a diode decoder net that allows the computer
to sense the accumulator for zero contents.
a

ACCUMULATOR DECODER - The diode decoder which senses whether or not the accu-

mulator contains zero is shown in Figure 7-1 A2. The 0 outputs of all 18 accumulator bits
are brought to the inputs of this diode decoder

If all the bits of the accumulator contain

0, this decoder generates the level AC =0 at both ground and negative assertion levels.
The accumulator is sensed both for zero contents and for nonzero contents by the OP SK IP
Iogi c (~ below). The output of the decoder, asserted at ground level, prov! des the
7-14

negatively asserted AC f: 0 level required by :the:():PSKIP, logic.

Note that the decoder

does not assert the AC = 0 level when the accumulator:b~tsare all 1s (representing -0 in 1s
complement arithmetic). In 1s complement arithmetic, the decoder asserts an "AC = +0"
level onlyo
b

OPERATE LOGIC - The levels and pulses developed during an operaf'e instruction (opr,

code 74) are generated by the operate logic. This paragraph describes the generation of
the two special time pulses which time all the events in operate instructions" as we! I as
the logic that generates the OP SKIP level

Three accumulator pulses (the two rotate

pulses and the complement pulse) are also described here since these pulses are produced
only by operate instruction

The two instructions opr and law both correspond to the same four-bit instruction code in
IR (1111 = iA3·IB3). The execution of law is governed by the level OP LAW (Figure
7-1 D1) which corresponds to the opr/law configuration of IR and the condition that MB4
is 1 (code 76)

The execution of the opr instructions is governed by the operate time pulses

OP1 and OP2 (D3). These pulses are generated by T5 and T7, respectively, when IR is in
the opr/law configuration and MB4 is 0 (code 74). All operations within the operate group
instructions are executed by OPl and/or OP2 .
In an operate skip instruction, bits a to 11 of the augmented instruction code determine the
condition for the skip. The skip logic is shown in Figure 7-1, B2 and C2" Bits 9 to 11
address the individual skip condition or skip conditions. The 1 states of bits 9,10 and 11,
respectivel y, address the 1 state of the link, zero contents in the accumulator, and negative contents in the accumulator (ie, the 1 state of AC ). Whenever the addressed conO
dition is satisfied, the level OP SKIP COND is asserted.
In an operate skip instruction, OP1 increments the program counter (paragraph 6-5~ if the
level OP SKIP is asserted. This level is equivalent to OP SKIP COND if MBa is 0, but if
MBa is 1, the truth value of OP SKIP is opposite to that of OP SKIP COND

Thus, when

a 0 is programmed in bit a of the instruction word, the skip occurs if the addressed condition is satisfied; on the other hand, a 1 programmed in bit a causes the skip if the addressed
condition is not satisfied. If no condition is addressed, MB~ produces an absol ute no-skip,
while MB! produces an absolute skipo

The following three register control pulses are generated only by operate instructions:
AC RIGHT ROTATE.' AC LEFT ROTATE
A pulse on either of these lines (B5, C5) rotates the contents of the accumulator and the
link one place in the direction indicatedo The directional pulses are produced by the
AC ROTATE pulse according to the configuration of bits 13 and 14 of the instruction word"
A right rotation is specified by MB~ 3; a left rotation is specified by MB~ 4"

Each rotate

instruction may produce a one-place or two-place rotation; depending upon the state of
bit 7 of the instruction word. AC ROTATE is automatically produced by OP2 (B1); however, it is also produced by OP1 if MB7 is 1

Thus, the programmer determunes the direc-

tion of rotation by adjusting bits 13 and 14, and determines the number of rotations by
ad j us t i ng bit 7 .
AC CMA
The accumulator is complemented only by the operate instruction, Complement Accumulator. The cma instruction is represented by the condi tion OP2· MB~ 7 (A5) "
c

TRANSFER LOGIC - The logic that generates the four accumulator transfer pulses IS

shown in Figure 7-1

These four pulses include the AC clear pulse and three pulses that

transfer information into AC from other registers.
AC CLEAR
The net that governs the clearing of the accumulator is shown in Figure 7-1 D2. At the
initiation of operations from the console, BEGI N clears AC.

This is done primarily to

prepare AC for use in the deposit operations. The accumulator is also cleared automaticall y
by any instruction that loads information into AC from MB. This occurs at T1 In the execute
cycle of lac, and at T5 in the single cycle of law.

The programmer controls the clearing

of AC through the operate instruction Clear Accumulator (OP1 'MB~) and through programming a 1 in bit 14 of any in-out transfer instruction (T5 "PIOCl).
AC XOR MB
This pulse produces the exclusive OR of MB and AC as a logic function, as partial addition,
and as a comparison ~unction 0 It also produces the 1 transfer of information from MB to AC

if AC is cleared first.

The logic governing AC XOR MB is shown in Figure 7-1, D3 to D50

The exclusive OR function is produced at T4 in the execute cycle of any instruction

7-16

whose instruction code begins with 2 or 3 (lAl).

This includes both addition instructions

and the instructions Exclusive OR and Load Accumulator. AC XOR MB also produces a 1
transfer at T6 in the single cycle of law
comparison function

In the instruction sad, AC XOR MB produces a

The first excl usive OR at T4 clears AC if the contents of MB and AC

are identical", At T5, the program count' logic (paragraph 6-5~ increments the program
counter if the accumulator does not contain zero -- that is, if the original contents of MB
and AC were different. At T6, a second excl usive OR pulse restores the original contents
of AC.,
AC MBO~AC
This pulse (C4) is generated at T5 in the execute cycle of the instruction and.

The pulse

clears each AC bit which corresponds to an MB bit containing 0, generating the bit-by-bit
logical AND function between the contents MV and the .::>riginal contents of AC"
ACS1-~AC

The 1 transfer of a word to AC from the console accumulator switches (D4) occurs in two
situations: in the operate instruction oas (OP2 MB: ) and in either of the console deposit
5
operations (SP2 ,KEY DPDPN). Although the accumulator is cleared automatically prior to
o

the transfer in console operations, the clear is not automatic in the case of the operate
instruction.

Thus, when the program loads information into AC from the switches, the

program must clear AC prior to the transfer.
d

ARITHMETIC LOGIC - Arithmetic operations utilize three levels and fIve pulses

Two of the pulses; AC CMA and AC XOR MB, are described in ~ and.:.. above,

This para-

graph describes the three levels and the remaining three pulses. The generating logic
elements are shown in Figure 7-1

These levels and pulses, plus AC XOR MB, perform the addition algorithms
nals are grouped in three pairs.

The SlX sig-

The first pair, a level and a pulse, performs the pdncipal

carry function for both 1sand 2s complement addition. The other two pairsy a pair of
levels and a pair of pulses, govern the carry effects derived from the sign bits

The Hrst

pair is associated with the full register carry; the second pair, with the ripple carryo In
each paIr of signals f one is for 1s complement and the other is for 2s complement. Since
the addition Instruction codes differ onl y in bit 3, the two types of addition are differentiated in the logic by the state of 1R3

7-,17

AC CARRY ENABLE, AC CARRY
The AC CARRY ENABLE level is asserted while TG
of the addition instructions (B4)

is 0 during the execute cycle of eHher
3
The level is therefore asserted throughout the execute

cycle of add or tad except between pulses T3 and T4. At T4, when AC XOR MB produces
in the accumulator the partial sum of the contents of MB and AC, the carry enable level IS
Because of the delay in the inverters, AC CARRY ENABLE ~s asserted

not yet asserted.
shortly after T4.

The full register carry pulse, AC CARRY, is produced at T5 while the carry enable leve! is
asserted.

The two-stage addition operation (in either 1s or 2s complement) is always pro-

duced in the following manner : First, the excl usive OR function produces the partial sum
at T4; then AC CARRY ENABLE is asserted; and finally AC CARRY is pulsed at I5

AC ADD ENABLE, L TAD ENABLE
These two levels differentiate the effect of the full register carry for 1sand 2s complement
addition.

The logic developing these levels is shown in C3 and C40

CARRYon AC

The effect of AC

depends upon the configuration of bit n+ 1 of both AC and MB" At the

the condition AC~ is replaced by AC ADD ENABLE This level is
17
equivalent to AC~ during 1s complement addition (lRB~)
Thus AC CARRY can affect
input gating to AC

only during 1s complement addition.

In either type of addition, a given bit AC is complemented by AC CARRY when the conn
O
1
dition AC 1 ·MB 1 is true. In 2s complement addition (IRB31) the equivalent condition
n+
n+
0
1
for the sign bits (ie AC .MB ) produces the level L TAD ENABLE. This level gates AC
O
O
CARRY into fhe 1 input of L. Consequentl y, when two negative numbers are added in 2s
complement arithmetic, the full register carry sets the I ink.
L CARRY, AC EN D CARRY
These two pulses determine the effect of the ripple carry from AC

(A4)

In 1s complement

addition, an end-around carry is required if the sign bit changes from 1 to 00

The AC

carry out, ACCP ' is therefore gated to produce AC END CARRY when 1RB3 is 00

in 2s

complement arithmetic, however, no end-around carry is desired. So, instead" ACCP
is gated by IRB~ to produce L CARRY"

Both the I ink carry and the end-around carry are

further gated by AC CARRY ENABLE, so that they have no effect except in addi tion operations.

In 1s complement addition, the ripple carry from AC

7-18

complements AC

; in 2s

complement addition, the carry has no effect on AC
e

but, instead, sets the Bnk.

OVERFLOW LOGIC - Overflow logic is provided for use only in 1s complement addi-

tion. The logic elements that check for overflow in the accumulator are shown in Figure
7-1, B3 and A4. The overflow logic inc! udes two inverters cross connected as fl ip-flop
AC POSS OV, and a diode-transistor logic net. The setting of the flip-flop indkates
that overflow may occur in an addition. The output level of the logic net J' when asserted,
indicates that an overflow actually has occurred.
If two numbers of opposite signs are added together, the magnitude of the resu! t must be
less than the magnitude of the larger number. As a result, no overflow can occur when the
signs of the operands differ. The overflow possible fl ip-flop is set by the accumulator full
register carry if AC

is 0 after the partial addition. In other words, the overflow possible

flip-flop is set in any addition operation (1s or 2s complement) if, before the addHion" the
signs of MB and AC are the same.
When two numbers of I ike sign are added together, the resul t shoul d also have the same
sign. To ensure that th is is the case, the states of the sign bi ts are again checked after
the addition is performed. This check is performed in the logic net

If an overflow is

possible during 1s complement addition and if, after the addition, the sign bits of MB and
AC are different, then the AC ONE COMP OV level is asserted" This level causes T1 to
set the link at the beginning of the following cycle. The link thus acts as an overflow
flip-flop for 1s complement addition.

The overflow possible flip-flop is cleared by BEGIN

and subsequentl y by Tl a t the begi nn i ng of every cyc Ie. As a resul t, the same ti me pul se
that sets the link in the case of an overflow also clears AC POSS OV disabling the 1s
,I

compl ement overflow gate.

7-19

CHAPTER 8 .

MEIv\ORY

8-1

GENERAL

The core memory system of PDP-4 consists of a memory address register and decoders, a memory buffer, and a memory module" A choice of two types of memory module are available~
a 1K memory module y providing storage for 1024 eighteen~bit words; or a 4K memory module,
providing storage for 4096 eighteen-bit words.

Both modules are composed of a coincident-

current core bank and associated read/write logic, sense amplifiers, and timing circuits.
Memory capacity may be further expanded by adding a second 4K memory module to the
computer, providing a total storage of 8192 eighteen-bit words.
.

In all memory systems, re-

gardless of capacity! provision is included for direct external access to memory through the
data interrupt logic.
The lK memory module uses a 10-bit address, while the 4K memory module requires a 12-bit
address.

If a second 4K memory module is added to the system both modules share the same

memory addressing element and memory buffer.

The memory address register includes an ex-

tra flip-flop which selects the module, while the location within the selected module is specified by the usual 12-bit address.
chapter.

Both types of memory module are described in the present

The two modules are similar in operation.

They differ only in the number of cores

in each core plane, and in the logic that selects the address windings.
The memory system is shown in five logic drawi ngs, Fi gures 8-1 through 8-5.
apply to the 4K and 8K memories,

Fi gures 8-1

Figures 8-1, -2, -4, and -5 apply to the 1K memory.

For information on the use and organization of these drawings! see paragraph 4-9.

8-2

MEMORY ADDRESS LOGIC

The memory addressing element of the computer is composed of the memory address register,
four binary-to-octal memory address decoders, and the input logic associated with the address decoders, and the input logic associated with the address register.

.....' 1

MEMORY ADDRESS REGISTER - The memory address register is shown in Figure

8-1. The flip-flops in the register are labeled MA4 to MA

. Flip-flop MA is
17
4
not usedD The designations of the remaining flip-flops correspond to the memory ad-

dress portion of the instruction word.

Each memory access is made to the location

specified by the contents of the MA register.
The configuration of the register shown in Figure 8-1 is for use with an 8K memory.

The 12-b it address conta i ned in MA6- 17 spec ifi es one of th e 4096 (2 12) locations
within a single memory module, while MA5 selects the module. For use with the 4K
memory, plug-in unit 1C15 is removed and MA _
then contains a standard 12-bit
6 17
address. For use with the 1K memory, plug-in units 1C15 and 1C16 are removed.
Then the contents of MA _
provide the la-bit address necessary to specify one of
8 17
10
the 1024 (2 ) locations within the lKmemory module. The la-bit address or the 12bit address is decoded by the memory address decoders to select a particular pair of X
and Y windings within the core bank.

Each core register within a memory module

corresponds to a single pair of X and Y windings.
All transfers into the memory address register are 1 transfers requiring a pd,)r clear.
The MA register may be cleared by pulsing the direct clear inputs to the Type 4204
fl ip-flops

Addresses may be transferred into MA from either the program counter or the

memory buffer.

In the instruction cal, the address 20 is loaded into MA by directly

setting MA

(B6). For use in data interruptions, address lines from a high-speed in13
out control unit may be connected to the bottom row of capacitor-diode input gates
through column 4 of the taper pin block shown below the register. An address from
the address I ines is loaded into MA by the pulse DBA l~ MA, which is equivalent to
the ADDRESS +MA pulse from the interrupt logic (paragraph 9-2i).
the pulse 7-+- MA (applied to MA

In a clock break,

through column 6 of the tape pin block) loads
15 17

address 7 into the register.
b

ADDRESS TRANSFER LOGIC - In normal operation, an address is transferred into

MA at the beginning of every memory cycle, and MA is then cleared at the end of the
cycle in preparation for the next cycle. The logic that governs the transfer of addresses within the internal processor is shown at the- lower left of Figure 8-1. Prior to
the first memory cycle when an operation is initiated from the console, MA is cleared

8-2

by SP1.·· It is then cleared at the end of every memorY' cycle, while the computer continues in normal operqtion (RU N=;= 1). Tb~ com.~u~er ~hal ts act the end of any memory
cycle in which RUN is cleared.

The clear~ng ofRt~,N inhibits the clearing of MA at
.

I '

the end of the cycle .. Then, after th!3 cOrlJputer has hatted, the memory ,address in.'

.... '

' , '

",'

dicafors on the console display the address towhi~h access was made during the finql
cycle of operQtion.
An acJdress is transferr.ed into MA at T1, ofrever,y m~m~ry cycle.

In a fetch cycle, the

address is provided
by the program counter for instru~tion retrieval.
' . . i . _'
~'."

~, t . . '

, , '

.~ ~

In execute and
,

def~.r cycles, the address is provided by the mel!lory,b~ffe~}~r retrieval of the operand
o~ Q defer~ed ad,dre~s ..

In the ,instruction Call Subroutine the transfer pulse MB1~MA

10Qds,addr~ss 20 into MA by g~ner~~ting the pul~e~O+MA.
'~'.:

-;'

. ,t .'"

•

(,'

The MB inputs to the MA

- -

•

gating do not affect the transfer because MB is cleared at the end of the preceeding
•

•

! " .

•

'~~>,

~~ (:~

.~>\

cycle. The internal processor dO,es not <?ontrol.th~ tr,ansfer of an address, to MA at the
•

••

....

'.,

beginning of a break cycle.

In a data break or clockbreak, the transfer is provided by

the i~terrupt logic (~above).

In a program hr~ak ti'ccess is always made to address 0,

so'no actual Qddress transfer' is necessary. Since MA'is previously cleared, the absence

of an address transfer is equivdlent to the transfer or~dd~ess' O.
c . MEMORY ADDRESS DECODERS ~. Memory addresses in-MA are decoded to select
a single core register fromJ~e 'total number of regi-$ters available in the computer mem'. ory. With an8K memory ,MA5 is d~coded d'irectly by memory control to select a single
memory moduJeJor use during the 'cycle (paragraph 8-40. For either a 4K or an 8K
contains a 12-bit address, spe~ ify~ngasingle location in one memmemory ,MA _
6 17
ory, module. Wah ,a 1K memory, MAS;'" 17 c()n,ta.i:nsa 1Q-bit address spec ifying a single
location in the 1 K memory module.
That part of the address in MA which speciHes asingle location in one memory module
is decoded to select X and Y windings corresponding to the addressed memory location.
The ~;ecoding is' accompl ished in two sta-ges: first, the 1O~bit or 12-bit address in MA
is decoded by four type 4150 binary-to-octal decoders, MADA through MADD (figure
8-1). Second stage decoding is accompl isheH by applying the decoder outputs (including four asserted outputs) to the read/write switches in the memory module.
connections

The

between MA and the decoders, and the meaning of the decoder output

8-3

depend upon whether a location is being addressed in a 4K modul,e or a lK module.
(1)

Twelve-bit Address Decoding - In the4K memory modu.le!1 the core registers

are arranged in a 64-by-64 matrix (64<~ 64 = 4096). A s'ingle core register is
selected by selecting one outof 64 X windings and one out'of 64 Y windings.
The selected register is located at the intersection of the"seleo'ted'X and Y windings
(paragraph 8-4~).
To select one X winding and one Y winding~ the 12~bnQ,ddress in MA is divided
into two 6-bit portions. The six-digit binary number in MA'6~11 is decoded into
a two-digit octal number by MADA and MADS. Simi larly, the six-digit binary
number il,,\;t~:\12~17 is' ,.:lec6~"ecJin'to'ajwo..cJigit octal number byMADC and MADD.
Each of the four decoders receives outputs from three bits of MA ci~d' asserts one of
eight output levels. The octal output level asserted by '0 given decoder corresponds
to the binary contents of the three associated MA bits.

The four decoders have a total of 32 outputs. Of these' 32 out'puts, four outputs
(one from each decoder) are asserted. The asserted outputs, fromlv\ApA and MADS
address a single Y winding from the 64 Y windings' in the core'ban"k,o Similarly, the
asserted outputs from MADC and MADD address a single X winding from the 64 )(
windings in the core bank. Selection of the, appropriate X and Y windings, addressed from the memory address decoders, is performed by the read/write switches
in the memor>' module (paragraph 8-4~).

In.an 8K memory system, the outputs of

the memory address decoders are appl ied to both memory 1ll9du les.
(2) Ten-bit Address Decoding - In the 1K memory modu,le;! the core 'registers are
Cl

rranged in a 32-by-32 matrix (32 x 32 = 1024). A single core register is selected

by selecting one out of 32 X windings and one out of 32 Y windings. 'The selected
register is located at the intersection of the selected X and Y windings (paragraph

8-Llb ) .
To select one X winding and one Y winding, the ten-bit address in MA is divided
into two 5-bit portions. The five-digit binary number in MA8~ 12 is decoded into
a two-digit octal number by MADA and MADS. Si.mi,larly, the five-digit binary
in MA 13 - 17 is decoded into a two-digit octol nUmber by MADC and MADD.

q'--Ii

Decoders Band D each receive outputs from three bits of MA (MA
MA

_ and
10 12
The octal output levels asserted

_ ) and assert one of eight output levels
15 17
by a given decoder respond to the binary contents of the three associated MA bits,
0

The other two decoders, A and C, receive outputs from only two bits of MA

a_9

and MA

respectiv."ely) and thus used as binary-to-quarternary decoders.
12 13
This is done by grounc1ing inputs E and F of these two decoders so that only output

0, 1, 2 or 3 can be asserted.

In this manner, the contents of two MA bits are de-

coded into octal, but 3 is the largest octal digit that can result. The entire tenbit address is therefore decoded into a pair of two-digit octal numbers. Each number
can range from 00 to 37.
The four decoders therefore have a tota I of 24 outputs. Of these 24 outputs, four
outputs (one from each decoder) are asserted.
The asserted outputs from MADA and MADB address a single Y winding from the 32
Y windings in the core bank. Simi larly, the asserted outputs from MADe and
MADD address a single X winding from the 32 X windings in the core bank. Selection of the appropriate X and Y windings addressed from the memory address decoders is performed by the read/write switches in the memory module (paragraph
8-4~)

8-3

MEMORY DATA TRANSFERS

The l8-bit memory buffer is the only register that functions in all four sections of the computer
logic: control, arithmetic, in-out and memory. Although instruction codes are decoded from
the instruction register, all other instruction or control information is uti Iized di rectly from MB.
In memory reference instructions, only the indirect address bit provides control information, but
in the augmented instructions, all bits provide control information.
In most cases, single bits of MB gate specific operations; but in the addressing of in-out devices, MB _
is decoded to provide octal information (paragraph 9-2~). The MB register also
6 11
functions as an element of the arithmetic unit in arithmetic and logical instructions. In most
such instructions, MB holds the operand and the MB outputs provide the necessary levels to the
arithmetic and logical gating of the accumulator.

8-5

However, all indexing operations are

performed directly in MB.
In data interruptions, MB serves as an in-out register II bypassing AC. The outputs of MB are
available directly to the data-out Iines, and information can be transferred directly into MB
thrqugh the data-in lines, As an element of the memory system, MB serves as the buffer between
the memory module and the rest of the computer. All transfers of information between the inte'rna I processor and core memory must be made through the memory buffer
a

MEMORY BUFFER - The l8-bit memory buffer is shown in Figure 8-20 This register

is composed of type 4204 dual flip-flops that are connected in the carry configuration.
This type of connection a Ilows indexing operations to be performed directly in MB
rather than requiring transfers to AC.
During every memory cycle, a full-length computer word is read from or written into
memory through the memory buffer. At the beginning of every cycle, MB is cleared
by pu!sing the direct clear inputs to all the flip-flops in the registero

In most in-

structionsr a word is read from the addressed memory location, and that same word is
written back into memory whi Ie it is being used for the execution of the instruction.
Information read from the cores by tJ-e memory strobe (paragraph 8-4!:) is transferred
from the sense amp\ ifiers into the memory buffer through the Cannon connector shown
below the register
by "the strobe.

The gating for this transfer is done directly in the sense ampl ifiers

Information is loaded into MB as single-bit pulse inputs, each of whi ch

sets a corresponding bit of the register,
During the second half of the memory cycle, the word contained in MB is written back
,into the same memory core register from which it came (paragraph

8-4i )

At the same

time that the word in MB is being written back into the addressed core register, it is
also used in MB by the rest of the computer.

During a fetch cycle, the instruction

code is transferred from MB to IR. Following both fetch cycles and defer cycles, the
,address portion of the word is transferred from MB either to MA or PC.

In execute

cycles, the word in MB is available to the transfer, logical and arithmetic gating of
the accumu latoL The word in MB can thus be used for a II instruction operations

.<,~oweverf during indexing operations, the number in MB is indexed by the MB +1

pulse before being written back into memory., Therefore, the number written into

8-6

memory during the cycle is 1 greater than the number read out at the beginning of the
cycle.
In those instructions for which new information is deposited in memory, the strobe is
disabled so that the memory register is cleared, but no information is transferred into
MB from the core bank.

If information is transferred into MB from some other part of

the computer I the new information is then written into the vacated core register in
place of the old

If no new information is made avai lable from MB then nothing is

written back into the core register, and it is left clear.
Information may be transferred into MB from either the accumulator or the program
counter. Both transfers are 1 transfers requiring a prior clear, but MB is cleared at
the beginning of every memory cycle. Whenever the address of an interrupted program is deposited in memory from the program counter, the state of the link is also
preserved by transferring the contents of L into MBa

In data breaks, information

may be transferred into MB from the data-in Iines (through column 4 of the taper pin
block shown below the register)

The information transfer is made on the pu Ise DB 11

~MB, which is equivalent to the INFO .... MB pulse from the data interrupt logic

(paragraph 9-2i).
If the data break access is being made for the retrieval of the information from memory,
both the a and 1 outputs of the MB flip-flops are available to the data-out lines through
the connectors shown above the register
b

DATA TRANSFER LOGIC - The logic that governs the transfer of information to

MB from other registers in the internal processor is shown in the lower left of Figure
8-2. At the initiation of operations from the console, MB is cleared by BEG IN.
The register is then cleared at the beginning of every memory cycle by T1.

However,

in Call Subroutine, MB is cleared at the end of the fetch cycle so that the state of
MB cannot affect the transfer 2a-.MA at the beginning of the next cycle (paragraph

A word is transferred from AC to MB at T3 in the execute cycle of the instruction
Deposit Accumu lotor. Whenever the program sequence is interrupted and an eventua I
return to the interrupted program is desired, the current program address is stored in

8-7

memory. The address is transferred from PC to MB at T3 in a program break cycle, and
in the execute cycle of Jump to Subroutine or Call Subroutine.
The transfer of an address from PC to MB is also made at SP3 in any examine or deposit
operation

However! this transfer is not made for the deposit of information in memory

In al! examine and deposit console operations, the one memory cycle that is performed
is performed as an execute eye Ie. Thus the transfer of PC to MB at S P3 is made mere Iy
to utilize the subsequent normal transfer of MB to MA at T1 of every execute cycle
(paragraph 8-2~).
c

INDEX LOGIC - Three types of indexing operations are provided in PDP-4o

The programmer may use the instruction Index and Skip on Zero to count program
loops.

The programmer maya Iso index addresses in order to perform an i nstructioil or

set of instructions on a whole sequence of operands.

Address indexing is combined

with indirect addressing. Automatic indexing is performed in clock breaks to keep
track of real time.
The logic that governs the incrementing of the memory buffer is shown in the lower
left of Figure 8-2. For counting program loops, the line MB+1 is pulsed by T4 in the
execute cycle of an isz instruction (D 1). The network shown in D3 provides address
indexing in defer cycles. During any defer cycle, if the indirect address is between
10 and 17, T4 pulses MB+1. With this procedure, each time a deferred address is
retrieved from a memory index register {locations 10 to 17L. the deferred address is
incremented before it is written back into memory. The next time the address is retrieved, it addresses the next consecutive memory location.

In each clockbreak, the

number contained in memory location 7 is indexed (paragraph 9-2~.

When this

number is indexed to zero, the clockflag is set.
8-4

CORE MEMORY LOGIC

The two PDP-4 memory modules, 4K and lK, are shown in Figures 8-3,8-4 and 8-5. Both
modules, are composed of a coincident current core bank, and associated timing, driving and
sensing logic. The core bank of the 4K modu Ie has a capacity of 4096 eighteen-bit words;
the core bank of the lK module has a capacity of 1024 eighteen-bit words.

8-8

Since both. modules contain the same number of core planes (that is, the core registers in both
modules are 18 bits in length) the timing, write inhibit driving, and read sensing logic for both
modules is identical (Figure 8-4).

However, the two modules contain a different number of

core registers and hence require different numbers of read/write switches to select the X and Y
windings. The X and Y selection for the 4K memory module is shown in Figure 8-3; the X and
Y selection for the 1K memory module is shown in Figure 8-5.
The description of the core memory logic given in this paragraph is for the 4K memory. Wherever the 1K memory differs from the 4K memory, the differences are expl i c i tl y mentioned in the
text. The memory modu Ie furnished with the standard computer is located at the top of bay 2.
If a second 4K memory is added to the system, it is mounted in an extra bay.

Internal processor

control over the memory module is described in ~ below. The memory modu Ie logic is described
in!: through..!: below.
~

MEMORY CONTROL- The internal processor controls the operation of the memory

module through the control signals shown in Figure 8-1 D6. Three of the signals are
pulses that control the timing of operations within the core memory. The fourth signal
is a level which disables the memory strobe if the information being read from the
addressed core register is not wanted by the computer.
The memory clear pulse (which clears the memory control flip-flops in preparation for
each memory cycle) is produced initially by the power clear, and subseq uently by the
final time pulse of every memory cycle. By shifting control information through the
four control flip-flops in the memory module, the memory control pulses and the memory inhibit pulse together time the memory cycle operations. The memory control
pulses are all applied to the same line, since fliplooflops R, RS, Wand I are included
in a single shift register plug-in unit with all pulses applied to the same input pin.
Because fl ip-flop I. is set out of sequence in the memory timing shift register, the inhibit pulse is generated separately from the memory control pulses.
There are four memory control pu Ises. The first three control pu Ises are produced at
T2, at 0.7 microsecond after T2, and at T4. The memory' inhibit pulse is then produced at T5 and the final (fourth) memory control pulse follows the inhibit pulse by
0.2 microsecond.

8-9

The memory read operation destroys the contents of the addressed memory register.
Whi Ie the read is taking place, information from the core register is transferred to the
memory buffer by tl-e strobe.

In any cycles during which new information is being

deposited in memory, the strobe is disabled. The addressed core register is then cleared, but no information is loaded into MB. The memory strobe is also disCilbled during
the execute cycle of any instruction that deposits information in memoryC lAO). In
a program break, the strobe is disabled so that the current program address may be
deposited in memory. The strobe is also disabled during a data break, if the break is
being util ized for data input.
If the memory system is expanded to two 4K memory modules, the plug-in units shown
in the lower right of Figure 8-1 are added to the internal processor. These units
duplicate the memory control and memory inhibit pulses. With two memory modules,
the memory strobe disable and memory clear signals are applied to both modules.
However, the memory contro"1 and memory inhibit pulses are applied only to the module
selected by MA . If MA5 is 0, pulses from 1A25 are applied to the first memory
5
module, but if MA5 is 1, pulses from 1A19 are applied to the second memory module.
If the computer contains only one memory module, the MA~ input in D6 is still connected to the 1 output of the MA5 plug-in unit.

However, the 1 output terminal of

that plug-i n un it is ti ed to ground.
b

CORE BANK - The memory core bank is composed of 18 core planes.

In the 4K

memory module, each plane contains 4096 ferrite cores (64 rows x 64 columns); while
in the 1K memory module, each plane contains 1024 ferrite cores ( 32 rows x 32
columns).

Every memory core is threaded by four windings; X and Y selection windings,

an inhibit winding, and a sense winding. The following description applies directly to
the core bank for the 4K memory modu Ie.

(Whenever the number of elements differs

for the 1K memory, the appropriate number is written in parentheses following the
number that appl i es to the 4K memory.)
The 64 (32) X and 64 (32) Y windings each thread a row or column of 64 (32) cores in
each of the 18 core planes. A single X or Y winding continues from one core plane
to the next, threading the same row or column in everyone of the 18 planes. A
single X winding and a single Y winding intersect at a single memory location

8 -10

containing an l8-bit core register.

During each memory cycle information is read from

or written into the single addressed core register

This addressed register is selected from

among the 4096 (1024) registers in the core bank by selecting the single X winding and the
single Y winding that intersect at the corresponding memory location.
There are 18 inhibit windings and 18 sense windings; one inhibit winding and one sense
winding for· each core plane.

~th the inhibit windings and the sense windings thread

all 4096 (1024) cores in the plane with which they are used.

Individual cores within the

addressed register are selected by the sense windings during reading, and by the inhibit
windings during writing

NOTE ~ The core bank actually includes an extra core plane which
is completely wired in There are therefore 19 planes, and 19 inhibit and sense windings. The extra 19th plane is not ordinarily used,
but is provided in case it is wanted for some special application.
The following discussion refers only to the 18 core planes that are
ordinarily used,
0

X AND Y SE LEeTION - Each of the 4096 locations in the 4K Inemory core bank is

specified oy a particular l?-Git acicJrt:ss ill the mCiilory address register.

The memory

module selection logic selects one of the 64 X windings and one of the 64 Y windings,
corresponding to the contents of MA.

For the lK memory module, each of the 1024

locations in the core bank is specified by a particular 10-bit address in MA.

The

memory module selection logic then selects one of the 32 X windings and one of the 32

Y windings according to the contents of MA. In either case, the two selected windings
intersect at the same relative location on each of the 18 core planes; the 18 cores located at these intersection points make up the addressed memory register.
The X and Y selection logic for the 4K memory is shown in Figure 8-3.
selection logic for the 1K memory is shown in Figure 8-5.
ings is similar.,

The X and Y

The layout of the two draw-

They differ only in the number of logic elements shown.

The X selection

logic is shown in the upper half of both Figures; the Y logic in the lower half.

The out-

puts of the memory address decoders are appl ied to the switching logic through the inverters shown below the switches

The outputs of the switches are applied to the core

bank through the memory stack sockets shown <?bove the switches.

The following de-

scription appl ies directly to the X and Y selection for the 4K memory.

8-11

(Whenever the

number of elements differs for the 1 K memory, the appropriate number is written in parentheses following the number that appl ies to the 4K memory 0)
The 32 (24) outputs from the memory address decoders (paragraph 8-2~ are appl ied to
the inverters shown in Band D in the figure (Figure 8-3 for the 4K memory I' Figure 8- 5
for the lK memory).

From the inverters, the 16 (12) X-selection levels are applied

to the Type 1972 read/write switches shown at the top of the figure. S im ilarly, the
16 (12) Y-selection levels are applied to the read/write switches shown at the bottom of
the figure.~ Only four of these 32 (24) selection levels are asserted during any given
memory cycle; two Y levels from MADA and MADB and two X levels from MADe and
MADD.
The two asserted Y levels enable one of 64 (32) Y read/write switches, and thereby permit the associated Y winding to be pulsed by the output of the read or write bus. Similarly, the two asserted X levels enable one of the 64 (32) X read/write switches, and
thereby permit the associated X winding to be pulsed by the output of the read or write
bus.

In this way, the two sets of read/write switches select one X winding and one Y

winding, and thereby select the addressed core register for reading or writing.
A Type 1972 plug-in unit includes four read/write switches. A detailed circuit description of the read/write switches is included in paragraph lO-7~: There are 64 (32)
switches in each of the two sets; both sets are identical in function. Each switch is
controlled by an AND-gate input. Each AND gate receives one of the eight (four)
more-significant-digit selection levels and one of the eight IE~ss-significant-digit selection levels. Only the AND gates that receive two asserted selection levels are enabled.
During any memory accessl' these AND gates correspond to the single X and Y windings
designated by the contents of MA

When both inputs to a read/write switch AND gate are at ground, the switch closes,
completing the current path between one end of the assoc iated winding and the read bus.
Since the other end of the winding is permanently connected to the write bus, the read/
write switch permits application of the bi-polar core-drive pulses to the two selected
windings.

(One polarity corresponds to a read pulse; the other polarity corresponds

to a write pulse)

8-12

The Type 1976 resistor cards located between the read/write switches and the core bank
provide the necessary loading to produce a core-drive current of appropriate magnitude.
Nominal value of the half-read and half-write currents is 190 mao A single half-current
is not sufficient to change the state of a core. However, the intersection of two half
currents at the cores of the addressed register is sufficient to switch these cores (see..!
and.§l below).
d

MEMORY TIMING FUNCTIONS - The timing for the memory cycle read and write

operations is controlled by the shift register containing flip-flops R, RS, Wand I
(Figure 8-4, Bland B2). This sh ift register is in turn controlled by pu Ises from memory
control ~ above). During a memory cycle, timing control information is shifted through
the shift register by the memory control pulses. The entire register is cleared at the
end of each cyc Ie by the memory clear pu Ise (T7). Th is prepares the register for the
next cye Ie.
The control data shifted through the register is self-contained.

No external gating

levels are applied to the register. The register starts the memory cycle in a cleared
state. Because the outputs of the second stage (RS) are appl ied to the opposite input
gates of the first stage (R), the first shift pulse following the memory clear automatically sets R. At the second shift, R1 sets RS, asserting the condition RS1. This causes
O
the third shift to set Wand clear R. The condition R in turn clears RS at the fourth
pulse. Thus a 0 is shifted through the first three stages of the register two pulses behind the 1.
The final stage of the shift register (I) is set early by the inhibit pulse (T5). This
grounds the 0 output of flip-flop l. Although the fourth shift clears RS, this pulse does
not affect I.
The four timing functions, read, write, inhibit, and strobe, cause the read and write
operations to be performed. The read, write, inhibit functions are levels; the strobe
function is a pulse. State changes in the ferrite cores of the memory core bank occur
much more slowly than changes of state in the computer logic elements. The coredriving pulses are therefore of relatively long duration (approximately two microseconds)

The duration of these pu Ises is much longer than the duration of computer

logic pulseso The core driving pulses are in fact produced from computer logic levels.
The memory timing functions are generated from the shift register outputs (A 1 to A3,

C2). The logical conditions for these functions are as follows:
Read:

R= 1

Strobe:

l~RS

Inhibit:

I= 1

Write:

(RS = 0) . (W = 1)

The strobe is produced by the fa II in the 1 output of RS, when RS is set (C2).

However,

if the memory strobe disable level is asserted, the strobe is not produced. This prevents
information read from the core register from being transferred into MB

Thus the read

operation merely clears the core register so that new information can be read into it
during the same cycle.
Operation of the memory timing network is summarized in Table 8-1 below

This table

shows the states of the four shift fl ip-flops after each time pulse. The shaded columns
at the right of the table show the duration of the timing functions.

Note, however,

that these functions are shown relative to the irregularly spaced time pulses. Therefore,
the length of each shaded column is not necessarily proportional to the actual duration
of the assoc iated pu 15e. The true duration of these functions is shown in the diagram
of the memory cycle (Figure 4-2).
TABLE 8-1
MEMORY TIMING
Time

Timing Flip-flops
R RS W
I

Timing Functions
Read Strobe Inhibit Write

- - ---

In itial State

0---

0-" -

T2 + 0,7 IJS,

0-- - -

Tk;j ~ill:ll~_llf
.,)
.~."I..

1- -

T5 + 0.2 jJS.

T 7 (Clear)

-lD
-

'- -

- -

8 -14

.- -

.-~

READ AND WRITE DRIVERS - The Type 1973 current drivers in the memory module

provide the read and write currents applied to the core bank windings (Figure 8-4D4) .
These two currents are identical in magnitude, but of opposite polarityo A detailed
description of the Type 1973 current driver is included in paragraph 10-7~:
When the read driver is enabled by the -3 vdc read level, a core drive read current is
applied to the selected X and Y windings

This read current flows through the following

path~ terminal V of the read driver (-13 vdc), the read bus, the two closed read/write

switches (these two switches provide parallel paths, one for X and one for Y), the selected X winding and Y winding corresponding to the two closed read/write switches,
the write bus, and terminal V of the write driver (-3 vdc).
Conversely I when the write driver is enabled by the -3 vdc write level, current is applied to the same X and Y windings, but in the opposite direction

Terminal Vof the

write driver is then at -13 vdc, and terminal V of the read driver is then at -13 vdc. The
current path is exactly the same for both the read pu Ise and the write pu Ise. However,
during the read pulse, the voltage atthe read bus is 10 volts more negative than that at
the write bus"while during the write pulse, the write bus is more negative. The Type 735
memory power supply furnishes the -3 vdc and -13 vdc used by the Type 1973 drivers.
Circuit description of this power supply is treated in paragraph 10-11~: A separate power
supply is required for each memory module because of possible temperature-induced
variations in the core characteristi cs
f

READ SENS ING - When a memory core is magnetized in the 1 direction, it is said to

contain a 10 When magnetized in the opposite direction,it is said to contain a O. During
the read operation, a full-read current (ie, two half-read currents, one on the selected X
winding, and one on the selected Y winding) is applied to magneti-ze the memory cores in
the addressed memory register The fu II read current tends to magnetize the memory cores
0

in the 0 direction, and hence has no effecton those cores of the addressed register which
were initially in the 0 state.
However" when the full-read current is applied to a core containing a 1, the core
magnetization changes polarity, and the core is switched from the 1 state to the 0 state.
This change of state induces an output voltage on the sense winding that threads the core.
{The same sense winding threads all 4096 (1024) cores in the plane containing the
8-15

affected core)

The two ends of this sense winding are connected to the two input ter-

minals of a Type 1538 or Type 1540 sense amplifier. Circuit descriptions of these sense
amp! Hners are provided in paragraphs 10-7~ and ~ respectivelyo
There are 18 sense amplifiers used in the memory, one for each of the 18 core planes
(Figure 8-4", C2 to C7). The sense amplifiers are differentia! amplifiers which reject
common-mode sngnals but amplify difference signalsc This tends to prevent noise voltages on the sense windings (from half-selected cores, etc.) from being erroneously
sensed as va!fld 1 output signals. The a.ctual output signal from a 1 state core which
has been swiltched to the 0 state by a full-read applies a difference signal of approximateijy 60 millivolts to the sense amplifier inputsc
The sense ampBfi ers sample the core outputs by means of a 70-nanosecond strobe pu Ise.
Thjs strobe ns regulated to occur approximately 007 microsecond after the beginning of
the read level
noise ratHo

At this time the sense winding is likely to produce the best signal-to-

~f the addressed core in a given core plane contains a

causes it to apply a difference signal output to the sense winding

1, the read pulse

The strobe samples this output signal" and co,uses the sense amplifier to generate a
standard ~og~c pulse output (provided that the core output exceeds the required l-s;gnal
threshold at the time of the strobe)

This logic pulse output sets the corresponding

f! !p-flop of the memory buffer register

The transfer of information from the memory to the memory buffer is a 1 transfer. The
memory buffer is cleared prior to the read-out from the addressed core register. At
read'-out! the sense ampl ifiers corresponding to the l-state cores of the addressed register set the corresponding bits of MB
~

WRITE INHiBIT DRIVING - The read operation is destructive; read-out leaves all

cores of the addressed register in the Ostateo During writing, a full-write current (jet
two haif-wunte currents, one on the selected X winding, and one on the selected Y
winding) ~s applied to all 18 cores in the addressed memory registero The full-write
current tends to magnetize the memory cores in the 1 direction.

Cores that receive

on!ya fu!i-write current are switched from the 0 state to the 1 state of magnetization
To write a word from MB into the addressed core register/! it is necessary to prevent

8 -16

(or inhibit) this change of state for just those cores of the addressed register that correspond to 0 bits in MB. This is done by applying an inhibit current of opposite
polarity (the equivalent of a half-read current) to only those cores which are to remain
in the 0 state.

Net current to these cores is then equivalent to only one half-write

current. Because this current is not sufficient to drive the cores beyond the "knee"
of the hysteresis loop, they do not change state, but remain in the 0 state.
The inhibit currents which prevent the writing of 1s into the 0 bits of the addressed
register are applied to the core planes through the 18 inhibit windings, each of which
threads all cores in a single core plane.

Each inhibit winding therefore threads one of

the 18 bits in the addressed register. The Type 1982 inhibit drivers (Figure 8-4, A4 to
A7) determine which of the 18 inhibit windings are to be pulsed.

Circuit description

of the 1982 inhibit drivers is treated in paragraph 10-7!l.
The inhibit driversare switching circuits which are enabled by two ANDed inputs.
The inhibit level @ above} is ANDed with the 0 signals from the bits of MB, enabling
those inhibit drivers corresponding to MB bits that contain O. This allows inhibit current to flow through the associated inhibit windings.

Inhibit current flows from the

inhibit common line (always at -3 vdc) through the enabled inhibit drivers to the inhibit reference line (always at -13 vdc).
While the inhibit level is asserted, current paths are completed from the common line
through the enabled drivers and the associated inhibit windings to the reference line.
The resulting inhibit currents cause the appropriate bits of the addressed core register
to remain in the 0 state.

8-17

CHAPTER 9

INPUT-OUTPUT SYSTEM

9-1

GENERAL

The input-output system of the standard PDP-4 computer contains a single input device, a
photoelectric paper tape reader

The reader control unit is controlled directl y by the in-out

pul ses from the i nterna I processor.
Other in-out devices may readil y be added to the system by install ing a type 25 real time
option. When th is option is install ed, the control units for the reader and all other in-out
devkes are governed through the device selector

This selector decodes the device code por-

tion of the iot instruction word (bits 6 through 11) and translates the in-out pulses into iot
pulses for the specified device

The present chapter includes detailed descriptions of the real time control and the control units
for three in-out devices. These devices are the standard photoelectric tape reader and two
options ll the paper tape punch and the keyboard/printer. The equipment described in this
chapter is shown in seven logic drawings, Figures 9-1 through 9-7. For information on the use
and organizatoon of these drawings, see paragraph 4-9.

9-2

REAL TIME OPTION, TYPE 25

The real time option governs the control units of the reader and all optional in-out devices.
The device sel ector decodes the device code section of an iot instruction word, and changes
the in-out pulses Hnto iot pulses for the appropriate control unit (incl uding the interrupt control).

Information is made available to output devices through the information distributor,

while information is brought into the computer from input devices through the information
collectoro The type 25 option also includes the interrupt logic and the in-out skip logico
a

DEV!CE SELECTION - The device selector is shown in Figure 9-1

The inputs to the

selector (at the left) are the in-out pulses (Pial, 2 and 4) and the outputs of bUts 6 to 11
of memory buffer

9-1

In an in-out transfer instruction, the individual in-out device is addressed by bHs 6 to 11
of the iot instruction word. The device code is decoded by the type 4605 pulse amp!Hier
modules. The logical configuration of this module is shown in the lower right of the fflgure.
The diode decoder inputs in the module are prewired to respond to a particular configum-

Hon of MB _ , ie to a particular device code When the diode inputs to a g!ven 4605
6 11
plug-in unit are enabled, any in-out pulses generated by the instruction word are switched
0

onto the iot lines for the correspondi ng devi ceo
For example, the first type 4605 unit at the left (2F06) is wired for the code 00 to control
the interrupt logic.

In this way, whenever an instruction of the form 7400XX appears in

the program, the in-out pulses generated in the internal processor are applied to the !nter~
rupt logic as iot pulses. The in-out pulses are provided by in-out transfer control according to the configuration of bits f5 to 17 of the instru ction word (paragraph 6-4~)

The number of type 4605 pulse amplifiers included in the device selector depends upon the
number of in-out devices driven by the computer. More options may be readily controi!ed
from the computer merely by adding more type 4605 units to the selector
b

i NFORMA TlON DISTRIBUTION - Information is distributed to the various output de-'

vi ces through the distributor shown in Figure 9-2. The 1 outputs of the accumulator f! ~p-'
flops are buffered by type 1690 bus drivers and made available to the output devices
_ are made available to the punch buff~
10 17
are made avai labl e to the tel eprinter buffer (LUO) at the

through taper pin panels. The contents of AC
er and the contents of AC

_
13 17
taper pin positions shown in the figure. Connections for other options are also shown,

while tie points for further equipment may be made as desired.
Both outputs of MB12 are also made available to in-out devices through the information
distributor

Besides the device code in bits 6 to 11, bit 12 of an iot instruction word may

also be used for control purposes. For example, in controlling the reader, bUt 12 speciHes
whether the tape is to be read in alphanumeric mode or in binary mode.
The information distribution capacity of the real time option may be increased as desired
merel y by adding more distributors in series with the one shown.
c

I NFORMATION COLLECTION - Information from input devices is transferred into the

9-2

accumulator through the information collector, IC (Figure 9-3),

This collector includes

18 pulse ampl ifiers and associated input gating. The output of each pulse ampl Hier is
applied to the set input gate of the corresponding bit of the accumulator (paragraph 7-2~)"
The 18 bits of the reader buffer are connected to the first row of gates in the collector.
The five bits of the incoming I ine unit are connected to gates 13 to 17 in the second row.
Information from these two buffers is loaded into AC through the collector on iot' 2 of the
corresponding iot instruction. Row 3 of the collector is used for the instruction In-out
Read Status, with the flags for the various devices connected to the IC gates as shown.
Tape unit status information is loaded into AC through the left half of row 2.
The ma~netic tape control and the card reader are also connected to the IC gates as
shown; additional input devices may be connected as desired.

The information collection

capacity of the real time option can be increased merely by adding more information
collectors in series with the one shown.
d

INTERRUPT LOGIC - The logic that governs interruptions in the normal program sequence

is shown in Figure 9-4. The three types of interruptions, data, clock and program, are
synchronized by the flip-flops shown across the top of the figure.

The flip-flops are cleared

initiall y by BEGI N and synchronization occurs at T5 in the memory cycle, Whenever any
of the synchronizing flip-flops is set, the break request level is asserted (B5).

This causes

the computer to enter the break state at the end of the current instruction (paragraph 6-3.~ .
The data interrupt logic is shown at the left in Figure 9-4.

The control unit of the high-

speed device that utilizes the data interrupt logic must provide two levels, one which re-"
quests a data break and one which specifies the direction of information flow
data request is made, T5 sets the synchronizing flip-flop.
data break level when it enters the break state.

When a

Then the computer asserts the

The data break level causes the program

to pause for one memory cycle while the high-speed device makes direct access to memory
At Tl, an address is transferred into the memory address register (paragraph 8-2~)

The

ADDRESS ~MA transfer pulse also signals the device that access to memory has been
granted.

If the break is for data output, the word read from memory by the strobe is avai 1-

able to the device from the memory buffer.

However, if the level DATA IN is asserted,

the break is used to deposit information in memory.

9-3

DATA IN disables the memory strobe

(paragraph 8-4~ and transfers information from the device into MB at T3 (paragraph 8-3~) .
The programmer controls the clock interrupt logic (left center, Figure 904) by programming
P,,04 for the interrupt logic (device code 00). Pulse IOT0004 clears the clock flag and
adjusts the state of the clock enable flip-flop according to bit 12 of the iot instruction
word. The 60-cycle clock is produced through a pulse generator from a filament transformer mounted on the 813 power control panel. While the clock is enabled, each clock
pulse sets the clock count request fl ip-flop. Whenever th is fl ip-flop is set, T5 sets the
synchronizing fl ip-flop, causing the computer to enter the break state. This break cycle
i's a clock break, provided no data break is being requested simultaneously.
A clock interruption merely causes the program to pause for one memory cycle while the
number contained in memory location 7 is indexed. If this number becomes zero as a result
of the indexing operation, the clock flag is set, indicating that the clock count has been
completed"

In the clock break cycle, T1 produces the pulse 7-?>MA (D4). This pulse

loads address 7 directly into MA (paragraph 8-2~ and clears the clock count request flipflop, After the contents of location 7 are retrieved from memory, the index logic increments the word in MB by 1 (paragraph 8-3.:). If the carry initiated by MB+ 1 rippl es
through the entire register, MBO changes state from 1 to 0, setting the clock flag.

This is

conditioned by the 0 state of the clock count request flip-flop to prevent the initial clearing of MB at the beginning of the break cycle from setting the clock flag.
The program interrupt logic is shown in the upper right of Figure 9-4. Program control
over program interruptions is exercised through PI02 of the interrupt iot"

Pulse IOT0002

adjusts the state of the program enable flip-flop according to bit 12 of the iot instruction
word.

EI even devi ce flags may be connected to the program request logic (A7). Any of

these device flags may make a program request provided program breaks are allowed, and
provided the computer is not currently in a break cycle. When a program request is made,
T5 sets the synchronizing flip-flop (A4) causing the computer to enter the break state at

the end of the current instruction (B5) " If no data break or clock break is being requested
simultaneously, the break cycle is utilized for a program break.

Th is type of interruption actuall y ends the current program sequence by transferri ng program
conhol to a subroutine. The computer saves information necessary for a subsequent return

9-4

to the interrupted program by depositing the contents of the program counter and the Iink
in memory location 00 The program then executes the routine that starts with the instruction in memory location 1

Operations necessary for the program break cycle are conditioned by the level PROG B
0

(see paragraphs 8-~, 8-3.!: and 6-S~u

This level also prevents further program Inter-'

ruptions of the break routine by causing TS to clear the program enable fl ip-flop
e

I N-OUT SKIP LOGIC - The programmer may check the status of any device by condi-

tioning a skip on the appropriate device flag

To address the device flag l1 the program

uses Pial in the in-out transfer instruction for the particular device (lower right,? Figure
9-4). The device flag is addressed through the device selector (~ above)

For example,

if the punch flag is on, Pial in a punch lot (lOT0201) generates 10 SKIP

This pulse

increments the program counter one extra step (paragraph 6-S.!:), causing the computer to
skip the next instruction in normal sequence

9-3

READER CONTROL

The control unit for the photoelectric paper tape reader is shown in Figure 9-S., The l8-bit
reader buffer is at the top of the figure. The control logic and control fl ip-flops are at the
lower left; and at the lower right is a block diagram of the reader control unit.
a

READER BUFFER - The 18-bit reader buffer, RB, is composed of 18 type 4218 flip-flops

Each fl ip-flop has a direct clear input and gated 0 and 1 inputs

The input gating to the

flip-flops is provided by capacitor-diode gates contained within the flip~flop plug-,in uniL
When information is read, the presence of a hole in the tape is indicated by a -3 vdc leve!
Consequently, the ground level utilized by the input gates indicates the absence of a hole

To compensate for this polarity, the input signals are applied directly to the clear input
gatesl1 and through inverters to the set Bnput gates, of the reader buffer bits

The reader can read the tape in either of two modes, binary or alphanumeric. H the computer is readong in alphanumeric mode, only a single line on the tape IS read g and the
entire I ine is loaded into reader buffer bits 10 through 17

If the reader IS operating in

binary mode g holes 7 and 8 on the tape are ignored, but three I ines are read from the tape
In binary mode g data from holes 6 through 1 is loaded into RB

9-S

_
12 17

The contents of

_
are then shifted into RB _ , and the data from holes 6 through 1 of the second
12 17
6 11
line on the tape are loaded into RB _ . The contents of the buffer are then again shifted
12 17
left six places, and the third line from the tape is read into RB _ "
12 17
RB

The read shift pulse, RD SHIFT, is applied to both the set and clear gates of all bits in the
buffer

This single pulse accomplishes both the shifting and the loading operations.

RBO to RB
the right.

From

, the RD SHIFT pulse to each bit is gated by levels from the bit six places to
The read shift transfers the contents of any six bits of RB into the next more

significant six bitsc

However, the gating levels for the input gates of RB bits 12 through

17 are the input signals from holes 6 through 1 on the tape.
with information from holes 6 through 1 of the tape.

Thus RD SHIFT loads RB

_
12 17
In binary mode, an entire l8-bit

computer word is assembled in the buffer by three read shifts.
When reading in binary mode, each read shift transfers the contents of RB16 and RB17 Into
RB

· However, in alphanumeric mode, RD SHIFT instead loads RB
and RBll with in11
10
formation from hoi es 8 and 7 on the tape.
b

CONTROL LOGIC - The logic nets and control flip-flops of the reader control unit

are shown at the lower left of Figure 9-5"

The five reader control flip-flops are the 2-bit

read counter, RDl and RD ; the run flip-flop, RD RUN; the reader flag, RD FLAG; and the
2
read mode fl ip-flop, RD MODE.
When the run flip-flop is set, the reader clutch is engaged through the network shown in
B4, moving the tape.

When RD RUN is cleared, the clutch is disengaged and the brake is

engaged, stoppi ng the tape.
from the tape

The read mode fl ip-flop controls the acceptance of information

If RD MODE is in the RD ALPHA state, the control unit accepts the first

line encountered on the tape and information from all eight holes is loaded into the reader
buffer.,

If RD MODE is in the RD BIN state, the reader accepts information only from lines

in which hole 8 is punched.

In this case, information from holes 1 through 6 is loaded into

the buffer wh i I e hoi es 7 and 8 are ignored.

The read counter controls the execution of a

reader instruction by counting the number of I ines read from the tape.
The in-out pulse that initiates operations in the reader control unit is PI04 in t'he standard
mach,ne, or IOT0104 if the type 25 real time option is used.

The difference is only one

of nomenclature; the two pulses have exactly the same effect.

Similarly, the in-out pulse

9-6

PI02.# which clears the reader flag, is relabeled IOT0102 if the type 25 option is used.
Pulse PI04 sets the reader run flip-flop but clears the read counter, the reader flag, and
the enti re reader buffer.

If MB12 is 0, PI04 puts RD ALPHA into RD MODE, wh i Ie if

MB12 is 1, PI04 instead puts RD BI N into RD MODE.
The run flip-flop engages the clutch in the reader, starting the tape

When the feed hole

on the tape is encountered, pulse generator 1 K14 (B4) produces the RD STROBE pulse.

RD RUN is 1, the read strobe produces the read shift (C2), provided either the tape is being
read in alphanumeric mode or hole 8 on the tape is punched. When reading in binary mode,
the reader runs until three lines, in which hole 8 is punched, have been read from the tape
into the buffer, regardless of how many characters are encountered.
In a binary mode instruction MB12 is 1, so PI04 asserts RD BIN.

This enables the O-input

shift gates to bits RB
put gates of RB

and RB11 -- that is, it applies the 0 outputs of RB , 17to the 0 in16
10
,ll(D3, 85). The first read shift loads the information contained in holes

10
6 through 1 into RB bits 12 through 17, and sets RD . The second read sh 1ft transfers the
1
information contained in RB _ into RB _ , simul taneousl y loads the information con12 17
6 11
tained in holes 6 through 1 on the tape into RB _ , and sets RD2 (without clearing RD ).
1
12 17
The third read shift transfers the information contained in RB _
into RBO_ll' simultane6 17
ously loads the information contained in holes 6 through 1 on the tape into RB _ , and
12 17
sets the reader flag.
The negatively asserted 1 output of the flag is applied through a capacitor-diode gate (C3)
to clear the run flip-flop.

This disengages the clutch and applies the reader brake, stop-

ping the tape. Since RD RUN is now 0, no further strobe or shift pulses are generated.
Three I ines of tape have been read, the buffer contains a full l8-bit computer word, and
the reader flag is on, indicating that RB contains new information. When the information
is retrieved by PI02, the flag is cleared.
In an alphanumeric mode instruction MB12 is 0, so PI04 asserts RD ALPHA. This disables
the O-input shift gates to RB

and RB11 (D3, B5) preventing RD SHIFT from shifting Os
10
into these bits. At the same time, RD ALPHA enables the transfer into RB
and RBll
10
from hoi es 8 and 7 .
The first (and only) read shift loads information from holes 8 through 1 into RB

9-7

_ and
10 17

also sets the reader flag . The 1 output of the flag falls to its 'negative assertion level,
clearing the run fl ip-flop.

This disengages the cl utch and appl ies the reader brake, stop-

ping the tape. Since RD RUN is now 0" no further strobe or shift pulses are generated.
One alphanumeric character has been loaded into RB

_ and the reader flag is on, indi10 17
cating that RB contains unretrieved information. When the information is retrieved by
P102, the flag is cleared.

9-4

PUNCH CONTROL, TYPE 75

The punch control unit is shown in Figure 9-6. The control unit includes an eight-bit punch
buffer, PB, drivers to power the solenoids in the punch, and two control circuits" The control
circuits comprise the three-state punch status device (D2, D3), and the punch synchronizing
and timing logic (B2, B3). At the upp~r left is a block diagram of the punch control unit.
real time option supplies two iot pulses' to the punch control unit.

The

These are IOT0202, which

clea'rs the punch buffer and turns on the punch flag; and IOT0204, which loads the eight-bit
buffer from AC

_
(through ID) and initiates the punch cyclec
10 17

The three inverters shown at the lower left of the figure are connected as a three-state device,
the punch status marker.

Til is device has three inputs and three outputs,

Pulsing anyone of

the inputs asserts the corresponding output, and negates the remaining two outputs,
states of the marker are punch active, punch idle, and punch flag.

The three

The punch start pulse

(lOT0204) is inverted to momentarily assert the punch active level. This level, asserted at
ground, turns off both the center and left tran'sistors. The negative output of the center and
left transistors maintains conduction through the right transistor, so that the punch active level
remains asserted
In a similar manner, the punch clear pulse (IOT0202) turns on the center transistor and turns
off the two end transistors, asserting the punch idle level and negating the punch active level.
The punch done pulse turns on the left hand transistor, asserting the punch flagi' and negating
both the punch idle and the punch active levels.
As long as the punch motor is running, a synchronizing pulse is generated every 15.8 mill isecondsc

To punch a line on the tape, the solenoids must be energized at this synchronizing

pulse, in order to avoid punching the tape while it is advancing to the next line. These
SYNC PUN pulses are generated once ~ad~ revolution of the punch shaft, regardless of

9-8

whether a I ine is currentl y being punched on the tape.
The punch start pulse OOT0203) asserts the punch active I ine, and at the same time transfers
the contents of AC 0-17 into the buffer

The first subsequent synchronizing pulse is appl ied

through a pulse generator to a type 4301 delay. Since asserting punch active disables punch
idle and punch flag, thus delay immediately asserts a five-millisecond level. This level gates
the 1 outputs of the PB flip-flops through inverters into the solenoid drivers, energizing the
feed-hole solenoid and those data-hole solenoids which correspond to PB bits containing 1 •
The feed-hole solenoid is also energized continuously whenever the tape feed button on the
punch cab;net is held down.

This allows the operator to punch blank tape for leaders.

At the end of the five-mill isecond delay, the level output of the delay is disabled and a terminating pulse is developed at pin Eo Thos is the punch done pulse, which puts the punch
status marker into the punch idle state. The concurrent disabl ing of the punch active I ine prevents subsequent synchronizing pulses from triggering another punch cycle. At this point, a
single line has been punched on the tape from the data contained in bits 10 through 17 of the
accumulator, and PUNCH IDLE is asserted, indicating that the punch cycle has been completed.
Aft'er completion of the punch cycle¥ the first subsequent punch clear pulse (lOT0202) clears
PB and switches the punch status marker from the punch idle state to the punch flag state. The
transfer of information into the buffer ~s a 1 transfer, which means that PB must be cleared
prior to the punch start pulse> The flag, when asserted, indicates that the punch control unit
is ready for the initiation of another punch cycle.

9-5

K EYBOARO/PRI NTER CO NTROL" TYPE 65

The two control units for the Teletype Model 28 Keyboard/Printer are shown in Figure 9-7. The
outgoDng line unit shown at the top of the figure develops the teletype signal that controls the
printer

Incoming teletype signal from the keyboard is decoded by the incoming line unit

shown of' the bottom of the figure.
the left.

Timing signals are provided by the clock circuits shown at

Except for the clock, which is common to both, the two control units function inde-

pendentl Yo
Signals both to and from the keyboard/printer are in the standard five-element teletype code.
An element on the code may be either a mark or a space. A mark is denoted by current flow

9-9

in the teletype line; a space is denoted by the absence of current flow

The character to be

printed or the printer operation to be performed is determined by the configuration of marks
and spaces which make up the five elements of the code

The keyboard/printer also requires (and provides) two additional impulses: the start impulse
and the stop impulse
impulses

The start impulse is al ways a space; it precedes the five code-el ement

The stop impulse is always a mark; it follows the fifth code-element impulse

Nor-

mally the start and stop impulses are used to synchronize teletype sending and receiving equupment ~

Neither the start nor the stop impulse conveys information; but both these impulses must

nevertheless be provided to the printer by the outgoing line uniL The incoming line unit must
also accept both the start and stop impulses as part of the signal from the keyboard

The keyboard/printer operates at a speed of ten characters per second. The printing rate determines the duration of each impulse in the composite teletype signal. The start impulse and
each of the five code el ement impulses are of equa I duration: 1303 mi II iseconds

The duration

of the stop impulse has no upper Iimi t, but must not be Iess than 18 mi II iseconds.
All printer operations are controlled by the printer selector magnets shown in A8" As long as
current is maintained through the printer selector magnets, the printer is idle" This situation
corresponds to a teletype stop impulse of indefinite duration.

The start impulse at the beginning

of a character-code si gnal interrupts the current flow, rei easing the pri nter sel ector magnets"
This action initiates one printer cycle.

During the remainder of the cycle, the printer selector

magnets act as an electromechanical decoder for the five code-element impulses representing
the character to be printed. After the fifth code-element impulse, the stop impulse again
causes current flow through the printer selector magnets
past the completion of a printer cycle, the printer stops

If this current flow is maintained

The printer then remains idle until

the next start impulse. The printer selector magnets, therefore, act as both start/stop control
and as signal decoders for the printer e
The duration of the stop signal may be considered as the duration of the mark (current flow)
between the last code-element impulse of the present teletype-character signal, and the start
impulse of the next teletype-character signal

In continuous printing, the stop impulses pro-

vided by the outgoing line unit are 20 milliseconds long

This 20 -millisecond duration ensures

that the printer completes a print cycle before subsequent signals are provided to ito

9-10

In the incoming line unit, the start impulse provided from the keyboard initiates the process of
loading the keyboard buffer. The stop impulse provided by the keyboard inhibits further operation of the incoming Iine unit. The duration of the keyboard stop impulse is determined by the
rate at which the operator depresses the keys. In the model 28, the keys cannot be struck at
a rate faster than 10 characters per second.
a

TIMING - Timing signals for both the outgoing and the incoming line units are supplied

by the clock shown at the left of Figure 9-7. A 9 .6-kilocycle clock drives the complement
input of the first flip-flop in a divide-by-16 flip-flop chain. As each flip-flop in this
chain changes state from 1 to 0, it complements the following fqp-flop in the chain. Both
the 1 and the 0 outputs of the fourth flip-flop in the chain, LUFD , supply a 600-cycle
3
square wave. This output, the LUI CLOCK, provides timing for the incoming line unit.
The LUI CLOCK also drives an additional divide-by-4 flip-flop chain.

The output of the

last flip-flop in this chain, LUFD ' is a lS0-cycle square wave. This output is the LUO
S
CLOCK, which provides timing for the outgoing line unit.
At ten characters per second, the composite teletype signal representing one character or
printer operation has a duration of 100 milliseconds. This 100-millisecond interval is
divided into the 20-mi II isecond stop impulse and six additional 13. 3-mi II isecond impulses,
the start impulse and the five code-element impulses. The LUO CLOCK is asserted twice
during the start impulse and twice during each of the five subsequent code-element impulses. This timing relationship is used by the outgoing line unit to generate teletype
signals for the printer.
The reader, on the other hand, is an asynchronous device. The incoming I ine unit cannot
know when an operator is about to strike a key.

If a lSO-cycl e cI ock were used to time

the incoming line unit, a situation could easily arise in which the logic were trying to
sample the level of the incoming teletype signals just as that level were changing.

order to avoid this situation, a 600-cycle clock is provided.
A 600-cycle square wave is asserted eight times during each 13.3-millisecond codeelement impulse. The incoming I ine unit samples the level of the incoming teletype signal
at the beginning of the fifth LUI CLOCK cycle subsequent to the start impulse generated
by the keyboard. Thus, the operator can strike a key at any time; the incoming I ine unit

9-11

nevertheless always samples the incoming teletype signal at some instant between eight· and
ten mIll !seconds after the start of an impulse
b

OUTPUT LOGIC - The outgoing line unit consists of a six-bit shift register, LUO,

three control flip,-flopsy a timing counter, and two timing counter decoders

The iot pulse that initiates a printing operation IS 1 T0404 ., This pulse effects a 1 transfer
of AC bits 17 through 13 into the first five bits of the six-bit $hift register (LUO _ ) At
l 5
some time subsequent to th is pulse, the timing counter and associated ci !"cults produce a
0

start pulse. This start is followed by six consecutive shift pulses. The first shift pulse comes
13.3 milliseconds after the start pulse. The interval betweenshifts is also 13.3 milliseconds. The sIxth shiftcoinddeswith the end pulse, which is also produced by the counter and timing circuits. The first start pulse subsequent to IOT0404 s'ets the sixth bit of the
sh ift register.
Th is sixth sh ift-register bit, LU0 , is the fl ip-flop that produces the waveform of the
6
composIte tel etype signal. The 0 output of LU0 is gated into a sol enoid driver provi ded
6
no key IS currentl y depressed at the keyboard" The pri nter prints the character corresponding to a key struck at its keyboard, so that while the keyboard is being used as an input
device, the printer is not free to print output characters. In order to avoid conflicting
signals to the printer selector magnets, the 0 output of LU0 is gated to the solenoid
6
driver by a level wh ich is asserted onl y when the keyboard is free.
When the 0 output of LU0 is asserted, the solenoid driver causes current flow in the line,
6
energizing the printer selector magnets. When LU0 is clear, current flows in the line;
6
when LU0 is set, no current flows in the line The first start pulse subsequent to
6
1 T0404 sets LU0 , interrupting current flow in the line. This interruption of current is
6
the beginning of the start impulse.
0

After the 13.3-millisecond duration of the start impulse, the first of the six shift pulses is
produced by the timing circuits"

Each pulse shifts the entire;contents of the shift register

one place to the right. This is a normal shift in LUO _ ; however, the shift from LU0
5
l 5
to LU0 IS a complement shift, ie if LU0 is 1 before the shift, then 0 is shifted into
6
5
LU0
The first sh ift!l occurring 13 3 mtl l,iseconds after LUO START, changes the state
6
of LU0 1'0 represent the first of the five ~eletype code-element impulses designating the
6
0

9-,12

character to be printed.

The second shift pulse, 13.3 milliseconds later, again changes

the state of LU0

to represent the second teletype code-element impulse. The third,
6
fourth and fifth shift pulses, provided at 13.3-millisecond intervals, change the state of
LUO 6 to produce the third, fourth and fifth teletype code-element impulses.
Suppose, for example, that AC 13-17 contain the five-bit code representing the letter F,
10110. Pulse IOT0404 transfers the five AC bits into LU0 _
The first subsequent start
5 1
pulse produced by the timing circuits sets LU0 , producing the teletype start impulse.
0

The first shift, 13.3 milliseconds later, clears LU0 , producing current flow (a mark) in

the teletype line. This is the first code-element impulse in the character F.

The next

four shifts respectively set, clear, clear, and set LU0 . This action produces the remain6
ing four code-element impulses of the character F: space, mark, mark, space, in that
order. The result of the output operations up to this point has been to develop the teletype
start impulse and the five code-element impulses representing the character F, by succes':"
sively shifting the five code bits contained in LUO _ to the right into LU0 . Since the

l 5

contents of LUO _ have been shifted out, these bits are now clear.

l 5

The sixth shift provided by the timing circuits coincides with the LUO END pulse. Since
LU0

line.

is now clear, this sixth shift pulse sets LU0 , initiating current flow in the teletype

This new current flow denotes the beginning of the teletype stop impulse. Simulta-

neously, LUO END sets LUO FLAG. The flag, when on, indicates that the outgoing line
unit is ready for the initiation of another printer cycle.

This flag may be cleared by

I T0402 .
The timing and control circuits for the outgoing line unit {include the two flip-flops LUO
ON and LUO I BT (A7), the four-bit LUO counter, and two associated counter decoders.
When IOT0404 transfers information into the first five bits of the shift register, it also sets
LUO ON. In changing state from 0 to 1, LUO ON clears LUO FLAG,

The asserted 1

output of LUO ON gates the first subsequent LUO START pulse to set LUO IBT and LU0 .

The sh ift pulses to all six bHs of the sh ift register are gated by the 1 output of LUO I BT .
The end pulse, concurrent with the sixth shift, not only sets LUO FLAG but also clears
both LUO ON AND LUO IBT

Flip-flop LUO ON is therefore set from IOT0404untii

LUO END.
However, LUO I BT is 1 onl y during the generation of the teletype start impulse and the

9-13

five teletype code-element impulses" Both these flip-flops are cleared by LUO END, at
the beginning of the teletype stop impulse"
The 150~cycle LUO CLOCK is applied both to a gated complement input to LUO counter
bit CT3; and to the capacitor-diode gate at the set input of LUO counter bit CT20 Th!s
counter thus counts 15 LUO CLOCK pulses, by gating the first pulse to set CT2 and gating
the remaining 14 pulses to complement CT3. Since the first LUO CLOCK sets CT2", the
counter al ready contains the number 2 after only the first pulse.

The second and all sub-

sequent LUO CLOCK pulses complement CT3. The counter then functions as an ord~nary
binary counter. Since after the first clock the counter contains 2, it is cleared by the 15th
clock. This count-to-15 process is repeated over and over again.

LUOSTART is produced

by the first LUO CLOCK subsequent to the interval during which the counter contains 3.
The LUO START pulses are therefore produced at intervals of 100 milliseconds {correspondi ng to 10 characters per second} .

The least significant bit of the counter, CT3 11 changes state from 1 to 0 seven times during
this 100-millisecond interval" The first clearing of CT3 occurs when the counter is chang-'
ing from 3 to 4.

Each subsequent time CT3 clears, it produces a LUO SHIFT pulseo The

first of the six sh ifts therefore occurs about 13" 3 mi II iseconds after the start pulse

Sub-

sequent shifts follow at intervals of 13.3 milliseconds.
When the counter clears (ie, has counted 15 pulses), the change in state from 1 to 0 in the
most significant bit of the counter, CTO, produces LUO END. This pulse signals the begh'lning of the stop impulse. After 20 milliseconds, a new LUO START pulse is generated. It
is followed by a new group of six shifts and a new LUO END pulse {concurrent with the
sixth shift}. Again, 20 milliseconds later i another LUO START pulse is generated. Th!s
process is performed over and over again

If an information transfer at IOT0404 occurs during the 20-millisecond interval between
LUO END and LUO START, then the new character is printed immediately after the last
at the maximum printing rate.

If no new transfer occurs between the end and start pulses,

then a full 100-'millisecond printer cycle must elapse before the printing of another
character.
A timing chart (Figure 9-8) shows the operation of the counter, the four control flip-flops,

9-14

and the shift register.

This timing chart alsoshowsa:ll the pulses generated by the out-

going I ine unit.
c

I NPUT LOGIC - The teletype I ine input from the keyboard is shown in Figure 9-7D4.

A 10K resistor bleeds the -15 vdc supply to the teletype keyboard generator contacts.
These contacts are closed when the keyboard is idle. Since the contacts are closed, current flows in the line, representing a teletype stop impluse of indefinite duration

When

a key is struck the keyboard generator contacts generate a teletype signal that corresponds
to the depressed key. This teletype signal includes both the start and the stop impulses.
When the operator strikes a key, the keyboard generator contacts fi rst open for 13" 3
milliseconds, representing the start impulse. Following this, the keyboard generator contacts produce the five code-el ement impulses representi ng the appropriate character or
printer operations. Finally, after the fifth code-element impulse, the keyboard element
contacts close once more, representing the stop impulse. The duration of this final stop
impulse has no upper limit, but must not be less than 18 milliseconds"

Duration of the stop

impulse is determined by the frequency with which the operator strikes keys at the keyboard,
The stop impulse provided from the ke'yboard cannot be shorter than approximatel y 18
milliseconds because the keyboard is- inferlocked to prevent the operator from typing at a
speed faster than 10 characters per second. The operator may, however, type at any rate
slower than 10 characters per second.
The incoming line unit includes a six-bit shift register, a three-bit timing counter, two
control flip-flops, and associated gating circuits. The first bit of the six-bit shift register,
LUiS' is connected to sample the level of the incoming teletype I ine at a shift pulse. If
at the time of Q shift, current is flowing in the line (mark), LUI

is cleared. On the other
5
hand, if current is not flowing in the I ine (space), then the shift sets LUI .
5
The first subsequent shift transfers the state of LUI
LUI

into LUI , and simultaneously loads
4
5
with the next mark (or space) impulse. The effect produced by subsequent shifts IS

5
the same, ie each shifts the contents of the register to the right one place and simultane-

ously loads LUI

according to the present level of the teletype signal

The timing system for the incoming line unit provides six;shifts. These shifts are provided
between eight and ten milliseconds after , the start
of each
incoming
teletype impulse y
:!
..
,
"
i~

9-15

'.~.~;'j'

,:~.:~

including the start impulse. Since the start impulse is always a space (no cur'rent flow)
the fUrst of the shift pulses always sets LUI " The five subsequent shift pulses shift the 1
5
originally contained in LUI five places to the right. The result, after all sixshHts have
5
occurred, is that the 1 originally loaded into LUI by the start impulse is nowconta!ned
5
in the sixth bit of the register, LUI DONE. This flip-flop indicates that the shift register
loading process is complete.
After the sixth sh ift .. the contents of LU1 _ are the compl ement of the five-bit code rep5 1
resenting the character corresponding to the key that was struck The sixth bit of the regu

ister

LUI DONE, contains 1. Bits 5 through 1 contain the complement of the teletype

code because bit 5 is cleared when sampl ing a mark impulse and set when sampl ing a space
impul se. To compensate for the compl ement representation, the 0 outputs of LUi _ are
5 1
provided as l-transfer I ines to the information collector.
The timing circuits for the incoming I ine unit are the three-bit counter LUI CTR, the two
control fl ip-flops LAST and NO CHAR and the pulse gates shown at the left of the shIft
j

The 600-cycle LUI CLOCK is supplied to the gated complement Input of the

least' significant counter bit, CTR2. This complement gate is shown in the figure as a
circle, and is different from the usual pulse gate. When the negative level input to this
gate is asserted, input pulses behave as though they were appl ied to a direct clear input

In other words, if the gating level is asserted y input pulses applied to this complement gale
may complement CTR2 from 1 to 0, but cannot complement CTR2 from 0 to 1.

If the gating

level is negated, then incoming complement pulses may complement CTR2 In either direction
Whenever the teletype keyboard generator contacts are closed, the generator idle level f
LUI IDLE, is asserted (04).

LUI IDLE is a negatively asserted level and is equ!valent to

the negation of the positively asserted level LUI RUN.

If the incoming teletype signa! is

idle, ie the keyboard generator contacts have been closed for some time, then the timing
counter (CTR) and flip-flop LAST are clear,

Flip-flop i~O CHAR is set, however&, Mndi-

cating that no signal is presentl y being received from the keyboard.
When a key is struck, the start impulse (a space) interrupts the flow of current in the line.
The interruption of current asserts the LUI RUN level at ground. Since fl ip-flop NO CHAR
is 1 and LU~ RUN IS now asserted, the capacitor-diode gate for LUI CLOtK' pulses is
enabled (C4)

The first subsequent LUI CLOCK is gated through a pulse ampfHier to clear

9-16

NO CHAR and all, six bits of ,the ~h ift r~gi,ster:

In·, ql~ori'ng, NO CHAR disabl es the neg-

ative inhibit level at the complement input gate of .CTR2.
Since the first clock is used to clear NO CHAR,' the counter actually begins counting with
the second clock.

The counter contains 1 after the second clock, and therefore must con-

tain 4 after the fifth clock," Consequently, it is the fifth LUI CLOCK which sets the most
significant bit of the counter, CTRO

The fall in the negatively asserted 1 output of

CTRO is interpreted as a pulse by the capacitor-diode gate shown in D4.

If fl ip-flop LAST

is not yet set, th is pulse is gat'ed to produce the first of the six sh ifts for the sh ift register.
Since CTRO is set by the fifth 600-cycle LUI CLOCK pulse, the interval between the beginning of the incoming start impulse and the shift is between 8 and 10 milliseconds.
Subsequent shifts are produced each time CTRO is set.

Every eighth LUI CLOCK sets

CTRO, producing a 13,,3-millisecond interval between shifts. When the sixth shift loads
1 into LUI DONE, the change in state from 0 to 1 sets LA.ST. After 6.6 mill iseconds,
CTRO clears. The clearing of CTRO clears LAST, which in turn sets NO CHAR.

The 1 out-

put of NO CHAR again asserts the inhibit level at the clock input to the counter. At this
point, the five teletype character code-elements produced by the keyboard generator are
represented by the contents of the first five bits of the shift register, LU1 _
Flip-flops
1 5
LUI DONE and NO CHAR are set; the timing counter and flip-flop LAST are cleal,
u

The device flag is produced by ANDing the 1 outputs of DONE and NO CHAR.

Since

both these flip-flops are setJ' LUI FLAG is asserted, indicating that the keyboard buffer
contains an unretrieved character.

Pulse IOT0302 clears LUI DONE, turning off the

FLAG, and at the same time transferring the contents of LU'1_5 into AC

,
13 17

Figure 9-9 is a timing chart showing the operation of the shift register, the two most significant bits of the timing counter! and flip-flops LAST, NO CHAR, and DONE.

Figure

9-9 also shows all pulses generated by the incoming I ine unit"
A new loading cycle begins whenever the operator again strikes a key. At the instant the
key is struck, the incoming start impulse gates in the first LUI CLOCK to clear NO CHAR
and initiate a new loading cycle,

Initiation of a new loading cycle proceeds regardless of

whether or not the five bi ts representi ng the previous character have been trans Ferred to
the accumulator.

If the operator types at the maximum keyboard speed of 10 characters

9-17

per second, the interval during which transfer to AC is possible may be as short as 15
milliseconds. All PDP-4 programs involving keyboard input must therefore sense the LUI
flag at intervals which are sufficiently short to ensure data transfer to AC within 15 millijseconds from the time the flag goes on .

9-18

CHAPTER 10

C, R CUI TOE SC RIP T ION

10-1

GENERAL

This chapter describes the function and operation of th~ circuits used in the standord PDP-4
computer and in the following three options: the real time option, the punch and the keyboard/
printer. All circuits except power suppl ies and the type 813 power control ore pi ug-in modules;
ie, all components are mounted on DEC standard etched circuit boards.
Schematic diagrams are included for all circuits, except that (lny modvle which includes a final
"Rtl in its type number shares the same schematic with the unit having the same type number
with the "R." Inverters 4106 and 4106R are an example of such a pair. The additional connections of the R type are indicated by dotted lines in the common schematic. The schematic
diagrams ore grouped at the rear of the manual, in order by type number.

No figure reference

is, made in individual unit descriptions, but references to the applicable schematics are implied.
10-2

INVERTERS

The inverter modules used in PDP!"'4 are made up of combinations of three basic circuits: a -3 vdc
supply, a diode-clomped load resistor, and a basic inverter. The clamped loads and the -3 vdc
supplies are all identical. In inverter 1103R, diode Dl and resistor R13 make up Q typical clamped load, while diodes 07, 08, D9, and 010, and resistor R19, form CJ typicQI -3 vdc supply.
There are two types of basic DEC inverter, differing in speed of operation. These are the highspeed (5 me) inverter and the low-speed (500 kc) inverter. Module 1103R contains a typical
high-speed inverter composed of transistor 01, resistors Rl andR2, and capacitor Cl. Modul e
4105 contqins a typical low-speed inverter, composed of 01, Rl, R2 and Cl. The two inverter
types differ only in transistQrtype, and in the value of the bose input by-pass capacitor (Cl).
These two differences affect only the switching speed of the circuit. The delay time of the highspeed 1000 series is 20 nonosec;onds, wh ile that of the low-speed: 4000 series is 0.3 microseconds.
Both types of inverter 'are used as Ievel gates or pulse gates, and both qre driven by DEC standard levels and negative pulses.

10-1

The inverter transistors are operated in two modes: saturati~r~, ?,n? cyt-off. When an inverter
transistor is in the saturated state, collector-emitter impe9a,~ce, is y~X)! low. Conversely, at
cut-off l collector-emitter impedance is very high.

If the emitter is at ground, and the collector

is connected to a -3 vdc clamped load, the collector Qulp"Lft level (or pulse) is an inversion of
the base input level (or pulse).

For example, if the base input level is ground, the transistor

is cut-off. The output is then -3 vdc, determined by the clamping voltage. Hqwever" ,if the
base input 'level is -3 vdc, the transistor saturates. The ground level at the emitter is then
also present at the output.
Base input loading is determined by the 3K base resistor. With ,-3 vdc present at the base input
and the emitter at ground, a saturating current of 1 rna flows through the transistor.

The bqse

input by-pass capacitor provides overdriving current to speed transistor switching. When the
base input is at ground, the '68K resistor to + 10 vdc suppl ies I to achieve good dc cut-off of
co
,',
'
the transistor. This 681< resistor also acts as a voltage divider with the 3K inplJt resistor to shift
the base positive, thereby preventing accidental transistor turn-on by noise pulse,s.
The diode in the clamped load limits the negative voltage at the inverter outputs., It does this
by providing a low impedance path from the -3 vdc supply when the output voltage at the collector of the inverter transistor is more negative than -3 vdc.

The clamping diode thus supp\ ies

whatever current is needed to maintai.n a 12-volt rise, (from -:-15 vdc) across the 1.5K load'resistor. This current is a maximum of 8 rna under no-load conditions, and decreases to zero as
the current drawn from the ~xternal' load increases to 8 rna.

The value of the clamped-load

resistor thus determines the maximum external load current at which the inverter can maintain
a regulated -3 vdc output

The -3 vdc supply is established by the four 0.75 vdc 'forward voltage drops across four seriesconnected lN645 silicon diodes. Current flows from ground through the' four diodes and then
through the parallel combination of the supply.load and the 560-ohm resistor. This resistor accepts enough current to mgintain a -3 vdc diode voltage even under minimum-load conditions.
a

'INVERTER 1103R - This 5 mc module contains six basic inverters, six clamped loads,

and a -3 vdc'supply. 'All logic terminals (base input, emitter, and collector) are accesible at the output pins of the module. The clamped loads are internally connected to the
output terminals of the basic inverters. The 1103R circuit is accurately represented by the

10-2

1103 schematic provided that the dotted lir)es between the clamped loads and the output
terminals are understood to be wiring connections.
b

INVERTER 1104 - This 5 mc module contains four basic inverters., four damped loads,

and a -3 vdc supply. Both the logic terminals and the clamped-load terminals are accessible at the output pins -of the module. Bias return for transistors Q1 and Q2 is to +10 vdc
(A)

For transistors Q3 and Q4, bias return is to +10 vdc (B). This division permits sub-

modular marginal testing and thus facilitates troubleshooting.
c

INVERTER 4102R - This 500 kc module contains nine basic inverters, nine clamped

loads, and a -3vdc supply.

Each inverter has its emitter internally connected to ground,

and each inverter collector is internally connected to a clamped load. The base and collector logic connections of each inverter are brought to the external connector.
d

INVERTER 4105 - This 500 kc module contains five basic inverters, three clamped loads,

and a -3 vdc supply. All logic and clamped-load terminals are accessible at the output
pins of the module. Bias return for transistors Q1 and Q2 is to +10 vdc (A). The bias return for Q3, Q4andQ5is to +10 vdc (B).
e

INVERTER 4106 - Except that no internal connections are made between transistor

collectors and associated clamped loads, this module is the 500 kc equivalent of inverter
1103 R (~ above)
f

10-3

INVERTER 4106R - This module is the 500 kc equivalent of inverter 1103R (~above).

DIODES

The diode modules in PDP-4 contain one or more diode logic gates. Diode modules 4112, 4112R,
4114and 4114R contain negative OR gates (OR gates for negative levels). Diode modules 4111,
4113, 4113R and 4115R contain positive OR gates (AND gates for negative levels). Each gate
is interna II y connected to an inverter base input

A clamped load is provided for each inverter.

A single -3 vdc supply (described in paragraph 10-2) is included in each diode module. With
the exception of diode 4111, inputs can be driven either by DEC standard levels or by 0.4-microsecond negative pulses. Only levels may be applied to the inputs of diode 4111 .

10-3

OIODE 4111 - This module contains two identical six-diode positive OR gates (com-'

posed of diodes 01-06 and 07-012, respectively). The following description of a six-diode
positive OR gate (an ANO gate for negative levels) refers to the circuit contpining diodes
01 to 06 (inputs K. to R), but applies equally to the circuit containing diodes D7 to 012.
Gate current is returned to -15 vdc through resistor R1. Any diode that is connected to a
ground input is forward-biased

Consequently, the gate output is at ground l less the smal i

forward voltage drop across the diode. Voltage divider 013, 014 and R3 shifts the gate
output sufficiently positive to ensure that Q 1 is cut off. Therefore, if any input is at
ground, the output (pin J) is at-3 vdc (assuming the inverter collector is connected to a
clamped load, such as R5-0 17) .
When a! I inputs are at -3 vdc, the gate output disconnects from the gate inputo The neg'ative gate output voltage is determined by current flowing from the base of Q 1 through 0 '13
and D14. This current saturates Q 1, grounding the output at the coliectorofQ 1. Capac»tor C3 furrHshes overdriving current to the base of Q 1, speeding transistor switching

Switching delay averages 004 microseconds.
Bias resistors R3 and R4 are connected to separate +10 vdc (A and B) lines to permit' independent marginal testing of the two diode gates contained in the module.
b

OIOOE 4112 - This module consists of six identical two-diode negative OR gates. Six

clamped loads are also included in the 4112 module but are not used. The six pairs of gat'~·
ing diodes are 01-02, 03-04, 07-08, D9-010, 013-014 and 015-016. The foHowing
description of a two-,diode negative OR gate refers to the circuit containing diodes 03-04,
but applies equally to the other diode circuits.
The gate is driven by +10 vdc (A and B) applied through resistors R3! R4 and R8. This volt,,~~
age forward-biases the diodes

The voltage drop across the diodes is low. As a result f the

voltage at the base-input resistor R3 approaches the lowest voltage present at either of the
gate inputs (E or F) •
If one or both of the inputs is a negative logic level (-3 vdc) I a negative level is applied
foo the base input of the inverter transistor Q 1. This turns Q lon, causing the collector
output of Q 1 to rise to ground

10-4

The inverter transistor is cut off onl y in the event that none of the inputs are negative (ie,
only if both inputs are ground levels). A ground level is then appl ied to the base input
of the inverter .. Switching delay is no more than 0.3 microseconds.
Resistors R4 and R8 are connected to the A and B +10 vdc lines, respectively. This prevents
excessive sensitivity of transistor operation to the marginal test ~
c

DIODE 4112R - This module is identical to diode 4112 (~above) except that each of

the six clamped loads is jumpered to the collector output of the corresponding gate trans istor
d

DIODE 4113 - This module consists of six identical two-input positive OR gates.. Six

clamped loads are also included in the 4113 module but are not used .
The two-diode positive OR gate functions in a similar manner to the six-diode positive OR
gates described in ~ above (module 4111) ~ If a ground level is applied to either of the two
input terminals, then the inverter transistor is turned off

The inverter transistor is turned

on only when negative logic levels {-3 vdc} are applied to both input terminals.
The six positive OR gates contained in the 4113 module have a switching delay of approximatel y 0.16 microseconds. A speed-up capacitor in the base circuit of each gate {shunting
the two series-connected sil icon diodes} accelerates the turn-off of the transistor when one
or more of the gate inputs is raised to a ground level. The bqse resistors of three of the six
gates are connected to the A supply; the base resistors of the remai,ning three gates are connected to the B supply. This permits submodular marginal checking of the 4113 circuiL
e

DIODES 4113R and 4113X - The 4113R module is identical to the 4113 (d above) ex-

cept that each of the six clamped loads is jumpered to the collector output of the corresponding gate transistor.
The 4113X modul e is also identical to the 4113 except for internal connections between the
collector outputs and the clamped loads~ In the 4113X, outputs H, T and Ware ORed by
connecting these three outputs to a single clamped load. Similarly, outputs P and Z are
ORed by common connection to a second clamped load.. Output L is connected to a third
clamped load, as in the 4113R. The remaining three clamped loads are not used ..

10-5

D~ODE 4114 - Th~s module contains two iden'tical four-input negative OR gates and

two identical three-inpurnega'tive'OR gate~'o F'ou'r cl~~ped loads are a'lsoinclud~d in the
4114 module but are not usedo The three~diode and'fbu~-diode'negati~e 'OR g~t~~ funcHon
; Hrl ,a:si~Harman!1er ,to the :two~diode, negativeQR'gates ,described in'~ above (module 41'12)
~f -3 vol ts is appl ied ,to,qny one of the inputs ,of a,gate u : the inv·ertertroinsisfbr associated

with that gate is turned on

The inverter transistor is turned off only ,w.henal ~ of the inputs

are af ground 0 '
,

Maximum switching delay of each cnrcuit is 003 microsecondso The gate puller re~istors
(Rl and R3, for example) are returned to separate +10 vdc lines! making gate operation
less, .crHical Y'{.H~ ~espect tq, mar;ginal, vQriations. jn .the +10 vdc I ines'~

DIODE 4114R - This module is identical to diode 4114 (f above) except ,that ~~~h of
'

' l " ' -

•..•

' .

'the four clampetd loads is internally connected.to the coll~ctor of the correspoqd.~9.9:,Qate
•

•

hansistor.
.

;

i ....

DIODE 4i15R - This module contains two ide'ntical four-input positive OR gates.,?nd

two identical three-input positive OR go'teso The moaule also contains four ciamped'ioads

'which are internally' cormected to the collector 'of an:: associated gate' transistor~ Except
for the 'rwrriberof !np~tsf 'the operation of both the four~di'~de' and three-diode gates is
sim nar to the 'operation of the two-diode gate describe~ in ~ above (module 41'13) 0 if a
ground level is applied to cmy one of the inputs of a gate, the inverter transistor associated
,

wHh'that gate is tLJrned off. The output is then at the clci~pingvoltage (-3 vdc).

The in-

vert,7r tra,ns;stor is turnedo!1" grounding the,ouJputl on!ywhen all of the' inputs are at

--3 vdc

MaXimum switching delay of each circuit is 0016 microseconds. The bias r'esistors (R2 and
RS) of,transistors Ql and Q3are, conJ1ect~d to +10 v:dc.(A)i,the bias resistors (R5and Rll)
of,Q2and Q4 are connected to + 10 vdc (B)o This permits submodular testing of the' gate
circuits.

~INARY-TO--OCTAL DECODER 4150 -

Both Qutputsof each of three fl ip-flops are

appl ied to the input terminals of the binary-to-octal decoder

')0'-6

The decoder has eight out-

put terminals numbered 0 through 70 For any given combination of states of the three fl ipflops which furnish the decoder inp~ts, one specific output of the decoder is a -3 vdc level
and the remaining seven decoder outputs are ground levels

The binary-to-octal decoder module is composed of eight identical parf's

Each of these

ports is a three-diode negative OR gate (which is logically equivalent to a positive AND
gate)

Except for the number of gate diodes u each of these gates is identica I to one of the

negative OR gates included in diode module 4112

(.!: above)

The eight decoder output terminals shown in the 4150 schematic represent, from left to right,
the octal numbers 0 through 70 The output signals generated by the decoder always include
a single -3 vdc level at one of these eight terminalso The remaining seven outputs are then
at ground

The -3 vdc level is generated at a specific output terminal -- that terminal

which represents the octal equivalent of the binary number in the three input fl ip-flops.
The eight diode gates are each connected to a different set of input I ines {refer to the
lower portion of the 4150 schematic}. These connections are arranged so that' each of the
eight gates responds to one of the eight possible combinations of Os and 1s that can be genera ted by th ree fl i p-fl ops .
As in the case of diode module 4112

(.!: above), a given gate transistor is cut off, thereby

producing a -3 vdc output, only when ground levels are applied to all of its gate input
diodes

Because of the gate input configuration, only one of the eight gates receives

ground levels at all three input diodes. The remaining seven gates must each have at least
one negative input level (-3 vdc). Consequently, the seven associated transistors remain
saturated, thereby producing ground output levels at all but one of the decoder outputs

Each of the eight sets of three-diode gate inputs is connected to one output terminal (either
the 0 terminal or the 1 terminal) of each of the three input flip-flops. When a flip-flop
is in the 1 state, its 0 and 1 outputs are at ground and -3 vdc u respectively

For the 0

state of the flip-flop, the polarity of the outputs is reversed. The decoder logic senses the

1 state of an input fl ip-flop as a ground I evel taken from the 0 output of the fl ip-flop
Conversely, a ground level from the 1 output asserts the 0 state of the flip-flop

The output terminals of the flip-flop representing the least significant of the three binary
digits being decoded are connected to inputs L (lout) and K (0 out). The flip-flop outputs

10-7

for the '1ext more signHicantdigit are similarly connected to J and Hi while~t~ose for the
mos'~' s!gnRHcant di'git are applied to F andE

BecQuse the 1 state of a fUp~,flop ijs as£er'ted

by a ground level f~'om its 0 output I the input connections for each gate' are: the complement of the three~d~gH binary number being decoded

For example u t~e ;gate,which de""

codes octal 7 (= bHna~y 111) is connected to the 0 outputs of all three::£! ip:fI~ps

These

three terminals are aH at ground when the three fl ip-flops contain the binary
,n_umber 1'! '}
.:;.

With all three diodes at ground g the gate transistor is cut off and the 7 o\..!tput
!'ermRnal of
..
-,'

the binary-to-octal decoder drops to -3 vdc

CAPACrrOR~D~ODE

10-4

.~.' ,

GATES

The capacitor--diode modu!es contain pulse gates. Standard 0.4 microsecond nego,tive DEC
I

pulses or negative-gof:l1g level changes ddve the pulse inputs of these gates.
.

•

f~:'-

~:~:'\: .. ~ L ~

Logi~ levels are
", 'I:. . ';, -" :\j',

appHed to the gaHng lnputs. The polarity of the logic level applied to a specHnc pulse gate
determines whe'ther or notr' 'that' gate will generate an output pulse when an input pulse is applied
,to fit.
'the 4'128 capacHor-d!'ode module contains pulse gates which have an inverter input stage" and

an output gating stage

This module is used for reading information into unbuffered fl ip-flops

(type 4214)0

The, pulse gates in the 4127 and 4129 capacitor-diode modules are constructed

differently

These two modules have an input gating stage and an output inverter stage

The

4127 and 4129 modules are u'sed for sampling the outputs of unbuffered flip-flops or any other
log,ic levelo The flip-flop output is used as a gating level

The contents of the flip';...flop can

then be sampled by applying a standard DEC pulse to the pulse input of the capacitor-diode
gate

NEGAT~VE CAPACjTOR-DIODE

!cal pulse gates

GATE 4127 - The 4127 module contains six ident-

Each gate has an inverter at the gate output. The following descdpt~on

refers to the gate containing transistor Qlb' but applies equally to the other five gates of
the module.
Type 4'127 pulse gates are used to sample any logic levelo The level is'applied to input
F of '~he gate u and a standard 004 microsecond negative DEC pulse is applied ,to inputE.
~f the gating level

is negaHve (-3 vdc) the gate is enabled. The n~gaHve input pulse then

10-8

generates a positive-going output pulse at terminal H. If the gating level is at ground,
the gate is inhibited and no output pulse is generated.

A logical delay is built into the circuit to prevent logical race problems. Delay is necessary to avoid splitting pulses when an unbuffered flip-flop is sampled at the saille time it

is pulsed. Because of the built-in delay, the gating level must be present one microsecond
before the arrival of the input pulse.
The pulse gate is composed of capacitor C1, diode D1 and resistor R2. Through R5, the
output of the gate is referenced to a dc I evel of -3.75 vdc. Th is vol tage source is provided by an additional series-connected diode, D25, which is added to the -3 vdc supply
in the module

Diode D2 and resistor R1 are incl uded to prevent the pulse gate input from

being driven more negative than -3 vdco Should the input be driven too negative, D1
might be forward-biased, causing spurious turn-on of transistor 01 (without the arrival of
a pulse at input E).
When the gate is enabled by the application of a -3 vdc level to input F, capacitor Cl
charges to -3 vdc through R1 and R2. Diode D1 is still reverse-biased, because its anode
is at -3.75 vdc. But, when a negative pulse is applied to pulse input E, and is differentiated by C1, diode D1 is forward-biased. The resul ting negative pulse at the junction of
D1 and R5 is coupled through C2 to the base of 01. This turns on the transistor, causing
output terminal H to rise to ground potential

At the trailing edge of the input pulse, D1 is cut ofL Some rise in voltage is coupled
through C2 before D1 cuts off. However, the base of Q1 is clamped to ground through D3,
so no excessive back-bias is appl ied to the base of Q1 •
The clamped loads in the 4127 module (D4 and R4, D8 and R9, etc.) are not used.

connections are made from the output pins of the module to these loads.
b

NEGATIVE CAPACITOR-DIODE GATE 4127R - The 4127R module differs from the

4127 in only one respect. In the 4127R each of the six clamped loads is internally connected to the collector output of the corresponding inverter.
c

POSITIVE CAPACITOR-DIODE GATE 4128 - This module contains two identical units.

Each of these units is composed of a single inverter and four capicator-diode pulse gates ..

10-9

The follow'ing descdpHon refers to the 'pulse ,gctewhhpulse'inpUt"termlnta!',P;and output
'~'e~m!na! ELI but applies equaHy to the,other-seven1,gates of the moduleo

Terminol F:h

the go'te level Input of this pulse gate 0 T~.e terminal ,P input pulsei,s s~are,c;f wHh three
,

/" r ·

" " . . '

'~.'

•

'," _, f

,. •

'The 'c~rcuH !s trig'gered ,by applying a standard n'egative DEC pulse to Hn'put:P~ ',Thns ~nput"
pulse h !nverted by trans/:stor Q 1

The resul ting posi.tive-going pwls'e ,at':the,coHector of

Q'1 IS appl ied to,lhe gate t.hrough C4o' ' If the g,atei~ ~I}ab!edv t~e 9}ffer~ntJote.d rRsJng
~.,

:.~.

,,;._

,"!,

"'i.:~:..

.... ,,~. "'::'lf~

,". ;.e~,ge of ,the p.uls,e !s app!Je~, to the output of the circui~oThe negati.Yi~ .~pi;k~~,pr~ated by
'j"

•

'.1

. . . 1.,"

differenHation of ,the:trailfing edge of ,~he pulsf? never appears at..the 0l!tput <?f,the circuit
,

j.",

. .

,'.

1 I

l,.

..',

. •

. " ' '.

but Hs ins'tead discharged through R80
"

,.'1

'} ::

: ,

,':' ~'t..

}I:.

' ••

The logic levelappl ied to gating. input F .determines whether or ,not the pulse 'gate .. wil!
. pass the posBive spike generated by, ,the,Jead~ngedge of, th~ input pul,se 0' A':r}~egoHve
gaHng leve! (-3 vdey pr'even'ts the generation of an output puJse by providing de hackbl'as to dnode D20 A ground, gating level permits the generation of an ~utput ,p';Jls~o
, : When a -3 vdc!.level flS. app! ied to gate terminal..F u the junction of C4'ond D2·dr,QPs from
groundtQ -,3 vdc 0 Thede!oy requir~d for this,change in voltage is determined;:by the tnme
constant of R8 Gmd C40

The gate is inhibited ,when the on6de of D2 is a't~3'vdc.; With the

gate nnhibited y no posiHve puheof less' than three volts can cause thejunetiorCof C4 and
D2 to rise above ground to forward 7 biasD2o The,refore, no pulse can be appHed .to the
load at output E (wh~ch js normallY,at ground potential).,
J

••

; . ,

'When a ground level is applied to gate, term.inal' F:J the :junction of C4 ond D2r'isesfrom
-,3 vde to grou!1d 0 The delay required for .this, chooge in vottage is dete'rmined by the Hme
constan~' of R8 and C40

The p~l~e gate, is enabl,ed when the anode of D2 is at ground 0

Any pos!tive pulse is the~ .sufficient to forward-bias D2,~; consequently any positive pulse
is passed through D2 to *.he load 0
The 4')28 module i~ used ,~o' read hlf~rmation :into a type 4214 uribLiffered'flip-flopo For
.

thIS use the pulse outpu~' oflhe gate is connected'to eifher the' Oot tliel i~put of the flipflopo

The posiHve output pulses from the puls~ gate 'then set or clear' the flip-flopo

The

delay built into the capacitor-diode circuits is useful for prevenHng logical race problems
, ' ,

(refer to ~,abov~)o

;

Because of the del~y built into the circuit u the ground gate enabling

10-10

level must be present at least 1.5 microseconds before a shift or jam transfer, and at leos1'
4.5 microseconds before a standard read-in operation.
d

NEGATIVE CAPACITOR-DIODE GATE 4129 - This module contains two identical

units. Each of these units is composed of four pulse gates ORed into an inverter output
stage.

These gates are identical to the gates used in the 4127 module (~above). A DEC

0.4-microsecond negative pulse, applied to a pulse input, is enabled by a -3 volt level
input and is inhibited by a ground level input. A 68K resistor returns each gate level inp'
to +10 vdc.

This prevents any unused gates from affecting the rest of the circuiL

The

4129 module also includes a negative de supply identical to the supply in module 41270
(This supply provides both -3 vdc and -3.75 vdc outputs.)
The pulse gates of the 4129 module may be used to sample the outputs of unbuffered flipflops.

The flip-flop output is applied to the level input of the gate, and a standard 0.4

microsecond negative DEC pulse is applied to the pulse input.

Because of the logical del

built into the circuit, the gating level must be present one microsecond before the arriVQj
of the input pu Ise.
e

NEGATIVE CAPACITOR-DIODE GATES 4129R and 4129X - The 4129R module diffe~,

from the 4129 in only one respect.

In the 4129X each of the clamped loads is internally

connected to the collector output of the corresponding inverter.
The 4129 module is also similar to the 4129X except for one variation. The collectors
of both inverters in the 4129X are internally connected to one of the clamped loads in-·
eluded in the module. The other clamped load is left unconnected and is not used

10-5

FLIP-FLOPS

There are seven different flip-flop modules used in the PDP-4.
flip-flop, the 4204 module contains two flip-flops.

The 4203 module contains art"

The remaining five PDP-4 flip-flop modu'

(1213,4214,4215,4216 and 4218) each contain four flip-flops.

All flip-flops change state

when an on transistor is turned off by a positive pulse appl ied to its base. The collectors of
the nonconducting transistors are clamped to -3 vdc
for clamping voltage.

10-11

Each module includes a -3 vdc supply

FLIP-FLOP 1213 - This module contains fourfidehticat:flip ... flops (1 through'4L, eight

capacitor-diode gates l one inverter I and d -3 vdc supplyo

The four fl ip-flops are designed

to operate as a unito With sl ight changes in external pin connections, the module can
operate as a four-stage shift register or as a four-bit buffer register.

Both types of ope,ration

are described belowo A negative pulse applied to terminal E is inverted by transistor Q1,.
and brought out to terminal Fo This positive-going pulse may be used to drive the shiftone and shift-zero pulse inputs (S and V) to all four flip-flopso

The eight capacitor-diode

gates are used to set and c lear each fl ip-flop 0 Note that only fl ip-flop # 1 has an externa,l
connection for a a input (P)

The other three fl ip-flops in ,the module have internally con-

nected a inputs, but no a terminal is brought out to the module connectofo A clear input
(M) is used to clear all four flip-flops simultaneously 0 Each Hip-flop has individual 1 ane;!.
~. {

a outputs

> ,;

Silicon diodes D17 through D2a make up the -3 vdc supplyo

ReSistor R28 to -15 Xdc, in

series with the diodes, furnishes sufficient current to keep the diodes forward-biased," thus.:
providing a constant -3 vdc source

When the module is used as a buffer register .. terminal F (pulse out) is externally connected
to S (shift one)o A 7a nanosecond negative pulse appHed to E initiates a parallel ls transfer into the four fl ip-flops of the module 0 Just those flip-flops are set to which ground
levels are appl ied at the time of the pu~se

The 7a-nanosecond negative pulse is inverted by Q 1 and then appl ied to F and S as a positive pulse referenced to -3 vdco This positive pulse is applied from S to the 1 input gates
of all four flip-flops.

Gating capacitors ell! C13 u C15 and C17 differentiate the pulse

and reference it to the level present at the one-in terminals of the four flip-flops (pins N,
R, T and U).

This level may be either -3 vdc or ground.

Since the cathode vol tages of diodes D2, D6 u D 1a and D 14 are close to ground! the,' pulse
can pass these diodes only when the corresponding one-in terminals are at ground

For".

example" suppose that fl ip-flop # 1 is in the a state (Q2 o'n,and Q'3 off) 0 Then .. if the onenn terminal of the fl ip-flop (N) is at ground, a. pulse through S can pass D2, cutting off
conduction through Q20
state

The cut-off of Q2 turns, on Q3/1 switching the fl ip-flop to thE! .1

In contrast" if the one-in terminal of the flip-flop ~s at -3 vdc when Sispulsed"

no change in state can occur

While the module is used as a buffer register, no individudl 0 transfers occur. A70-nanosecond pulse appl ied to M clears the entire register.
berore the parallel is transfer described above.

This clear operation is carried out

The fl ip-flop side of C3 is returned to

-0.75 vdc to provide noise immunity for the clear input.
When the module is used as a shift register, F is externally connected to both 5 and V.

The

o outputs of fl ip-flops # 1, #2 and #3 are each externally connected to the 1 inputs of the
next more significant stage' (J to R, 1 to T, and X to U).

These external connect'ions'

parall,el the existing internal connections from the 1 outputs of flip-flops #l,#2and#3 to'
the individual 0 inputs of flip-flops #2, #3 and #4 respectively. Although only flip-flop
#1 has an external 0 input, all four flip-flops have identical clear capacitor-diode gates.
These gates are puls'ed through the shift-zero line.
As a shift register, fl ip-flop module 1213 operates in the following manner. Assume a II
four flip-flops are initially in the 0 state. The first 70-nanosecond negative pulse arrivin,S
at' E is inverted by Q 1 and appears as a positive pulse on both the shift-one and shift-zero
lines.' This pulses the 0 and 1 inputs to all four flip-flops.

If ground is present at the one-

in terminal of flip-flop #1 (N) and -3 vdc is present at the zero-in terminal (P), flip-flop

# lis set to the 1 stat~. Th'is causes the 0 output of that fl ip-flop to rise to ground (J).

Be~ause J is connected to R, the l' input of fl ip-flop #2, th~ second shift pulse se;s fl ipflop #2.

The effect of the s~cond pulse o~ fl ip-flop # 1 is independent of the change in state

of fl ip-flop #2 and depends only on the levels appl ied to the input gates of fl ip-flop # 1 .
The third shift pulse sets fl ip-flop #3 to the state of fl ip-flop #2.
cleared flip-flop #1, its 1 output is at ground.
pulse to clear flip-flop #2.

If the preceding pulse

This ground output causes the third shift

The 1s and Os injected at flip-flop #1 thus propagate through

the entire shift register on successive shift pulses. Each stage assumes the state of the next
less significant stage. The delay of the capacitor-diode input gates in accepting level
changes prevents any ambiguity in the fl ip-flop outputs at pulse time.

This delay is small

compared to the pulse rate.
It is possible to set or clear any of the four fl ip-flops individually without pulsing the shift
lines.

For instance, to clear fl ip-fl~p #4 independently, the collector of an inverter is

connected to the 1 output of the fl ip-flop. When fl ip-flop # 4 is in tIle 1 state, QS is off
and Q9 is on.

The fl ip-flop remains in the 1 state becguse the col iector load of QS draws
10-13

sufficient current through R26 to keep Q9 saturated

The level shift produced :~y R23 from

the collector of Q9 to th~ base of Q8 reverse-biases Q8, holding it cut ofL
If the em itter of the, inverter is at ground and the inverter is driven to saturation; its collector (together with pin Y}'will rise to ground. This causes Q9 'to be cut off'.
tQ~ voltage of Q9 falls to the clamp voltage 19.pd turns on Q8.
"Iq,t~e, 0 s!ate.

The collec-

The flip-flop is then stable

The flip-flop can be set in the same way by grounding its

o output. A

;chqnge ?f ~tate produced in,this manner does not aff~ct the other flip-fl.9ps in,the·module!
and can occur independf1l1t,ly of the shift pulse,s. The emitters of inverters use9, fO,r this
.p~rpose must be ,.directly connected to ground •
,j"

, ' "

~'" ';'FLlP~F'LO'P 4'20j ~ Thi's ~o;d~le'co~sists ~(a' singil~'b~ffered flip-flop', 3' pCI:se inverters, 13 negative and 2 positive capacitor';'diod~" gates,' a' two-diod~ negati~~:' AND~gate,
and a negative dc supply.
Each 'negative capacitor-diode gate is similar to those contained in module 4127 (paragraph

'10-4~). 'Each'positi°ve capacitor-diode gate is similar to those in module 4128 (pa~~g~aph
':10-49. The negative supply generates -3 vdc 'in the same manner as do the suppl ies ~on

;tdi~e(fil1 the i~verter modules. However , an ~dditio'nal series diode, D36, is added to the
. supply, generating -3.75 vol ts

Terminals are located at the front and back of the modu Ie

Those' located at the back have an asterisk added to the letter denoting the term inal (A* I
for example).
Type 4203 flip-flops make up the PDP-4 accumulator. Flip-flop pulse inputs include set

I(K*', S and X), clear (E* and F*) shift (J* and H*) and complement (K, A*, S-a\' and C*).
Except for inputs A*, F* and S, all pulse inputs are gated by an associated level input.
These levels are asserted a't -3 vol ts

Accordingly, the register may be loaded 'in parall el u

have its contents shifted left or right, or be complemented, with a minimum of external
c ircu i try'.
A carry output (H) permits connection of the register bits so that the register may be used as
a counter. The 0 and 1 outputs are at F and R, respectively. A -3 volt level at F and
ground at R indicates the 0 state, while the opposite polarity, ground at F 'and "':3 volts at

R, indicates the 1 state.' Terminal L provides a 1 output fo'r a consol~ panel indicator.

10-1.4

Capacitor-diode gates provide all input gating. The logical delay built into this type of
gate permits the input levels to be sensed at the' same,time that the flip-flops which generate these levels are chan,ging state .. With the exception of the carry input (K), standard
OEC 0.4 microsecond pulses drive all inputs. The carry input is driven by a level drop
from ground to -3 volts (generated when the next less significant accumulator bit goes from
the 1 to the 0 state).
The flip-flop is set by a negative pulse at K* or~, provided that level input W or T, respectively" is ~t -3 vdc. A negative pulse a"t S,al~ays sets the flip-flop, since the level
return of the capacitor-diode input gate is inter,nally connected to -3 vdc through R45.
The following description of the setting of the flip"';Hop by a pulsea.tK* also describes the
operation of the fl ip-flop in response to signals at all three set inputs.
Prior to the appl ication of a pulse at K* I the cathode of diode 030 is at the vol tage appl ied
to·W(ground or -3 'Ide). Regardless of the cathode voltage, 030 is back-biased, since
its anode is connected to -3.75 vdc through R37. Capac itor C 19 blocks the -3.75 vdc
from the base of 1-ran,sistor Q6; this transistor is held off by a positive voltage at its base,
from voltag~ divider ~38-031.
Assume that the Hip-flop is in the 0 state; then Q4 is cut off and Q5 is on. The 0 output
buffer, Q2, is held off by the ground althe collector of Q5, so the 0 output at F is -3 vdc.
The 1 output buffer, Q7, is held on by the -3 vdc at the collector of Q4, so the 1 output,
R, is at ground.
A 2.5-volt negative set pulse applied to K* is coupled to the cathode of 030 by C 18.

the quiescent level at the cathode of 030 is ground (a ground input level at W) the diode
is not forward-biased by the set pulse. The pulse is then inhibited at this point.

How-

ever, if the quiescent level is -3 vdc, D30 is forward-biased, passing the pulse to the base
of Q6 through C19. Transistor Q6inverts the 'Pulse, momentarily grounding the collector
of Q40 Voltage divider R33...;R34 shifts the base"of Q5 positive, turning Q5 off. The collector of Q5 is then clamped at -3 vdc by 021 and R22. The -3 vdc is coupled to the base
of Q4 by R23 and C14, tvrning Q4 on. The turn-on of Q,4 holds its collector at ground
after the termination of the set pulse. The fl ip-flop is then in the 1 state.
The turn-on of transistorQ4 holds the 1 output buffer (Q7) off, so that the 1 output at R

10-15

~s at -3 vdc u and the light-driver output at L is energiz~d through R440

The turn-off9f Q5

turns on ,the 0 output buffer b' Q2; consequently the:O o!Jtput IF ll- is at ground e
The f! ip-f!op ~s cleared by a 2 .5-vol t negative purse: applied to E*or F*ih a- manner sfimnar to that described above 0 The clear 'pulse switches the'fI ip::"flop

to the 0 state' by momen-

tari!y grounding the-co"le~tor of Q2. A pulse at E* is' ga'ted by the I:eve'! applied to M.
The ~npu-ta't f* I! I ike the set input at S i is always enabled.

at enther J* Or H*' ~ A pulse

The fl ip-flop may be 'either se·t or cleared by a negat"nve pulse

at J* is d~rected to the set or clear side of the fl ip-flop by a -3 vdc asse.rtionlevel at termnnal U or Pll respectivelyoSimiiarlYlla pulse a't H*is gdtedby the:levels at Vand N.
These asserHon le~els are derived from the adjacent bits of the accumLdator ,~o as: to jam
t-ransfer the state of the adiacentbit into the flip-flop (a shHtbperation)'. 'Except that the
set and clear gates of the fl ip-flop are pulsed simu! taneously Q the operation·, of these inputs
js s~mHar to the operation of a set input descrived above, since only one of the pair of

;gates is enabl ed at any time.
Termr:nals A*'v B*'u C*'and K are the complement inputs to the flip-flop. AnegaHve pulse
at C~"I! or a fall ing level at K complements the fl Bp-flop provided that J or D* f respectnvelYi
~s ~t -3 vdc.

iiJ order for a pulse at B* to complement the fl ip-f1opl! both, level.,inputs Z

and Y mus"t be at -3 vdco A pulse at A* always complements the flip-floPll since the associated capacHor-diode gate level return isinterna! Iy connected to -3 vdc through R6. The
following description of fl ~p-flop complementing by means of a pulse ~t B* also describes
the operation of the flip-flop in response to a signal at any of its four inputs.
Prilor to the app!.i~ation ofa pulse to B*fJ the cathode of.04 is at the highes,t voltage of
eUither input Yand Zo

(These two inputs are ANOed for negative levels by diodes 01 and

02u duode 03 limits the maximum negatRve gate o,utput to -3 vdco) Whether this voltage

is ground or -3 vdc ll D4 is back-biased because its anode is returned .to -3.75 vdc through
R80 Capacitor C5 nsolates the -3.75 vdc from the base of Q1

This transistor is held off

by a positive voltage on its basel! determined by voltage divider R10-Ol0o

The collector of Q1 is clamped to -3 vdc by 012 and R9.'Capacitors C13 and C15 isolate
th~s voltage from the anodes of 022 and D28 u

respectively

The voltage at the-anodes is

determ ined by the vol tages on the coil ectors of fl ip-flop transHstors Q4 and Q5 I' through

10-1.6

R29 and R26, respectlvely • ',Neither D;22"'nor.D28 is>forward-biased (their cathodes are
approximately at grolJl1d)', 'andfhe 'f~ ip ... flop r~mains'; stable in either state.
The leading edge of a negati~'e p~lse input a't' B* 'is differentiated to a ne;gative pulse at the
cathode of D40

This negative pulse is superimposed on the quiescent level.

If-the quies-

cent level is -3 vdc (both Z' and Y at -3 vdc)" D4passes the negative pulse to the base of
Q1 through C50

Trans.istor Ql i'nverts the; pulse; the inverted pulse is then applied to capac-

itor-diode gates C:13-D22-R29an'd C 15-D28-R26.
The pulse is ?irected by the gates to the base of the on transistor

For example" if the

fl ip-flop is in the 0 state, Q4 is off and Q5 is ~n'. The level af the anode of D28 is ground,
sO,D28 is forward-biased by ~he pulse and passes the pulse to the base of 'Q5 . The level at
the anode 9f D22 is -:-3 vd,c, and the pulse does n6thave sufficient ampl'itude to forward, bias D22

<:=o,nsequently , the pulse is blocked 'from the base of Q4. When the pulse turns

: the on transistor off, the £"1 ip-flop changes state.
c

FLIP-FLOP 4204 - This module contains two buffered flip-flops, two pulse inverters,

eight negative and Jour positive capacitor-diode gates, and a series-string sil icon diode
negative de;: supply

The negative capacitor-diode gates are similar to those of module

4127, while the positive capacitor-diode gates eire similar to those of module 4128 (par.j

agraphs 10-~ a~d.s, respectively).

Four 'series-connected diodes (D18 to D21)igenerate

-3 vdc as in the supply contained in the inverter modules (paragraph 10-2)0

In the type

4204, a fifth diode (D 17) is added to the series-string, generating -3 75 vdc 0 The supply
Q

is also tapped between diodes D20 and D21" to provide -0075 vdc

Except for th~ number

and arrangement ~f input and output terminals, e'ach of the two fl ip-flops contained in the
module is similar~to the flip-Hop in module 4203(~ above}.
Type 4204 fl ip-flops m(Jke up various registers6f the PDP-4.
L, M and N9reshared by both fl ip-flops
into flip-flop A by:levels at inputs J

Gated set poise in'puts at

Common set pulses at these inputs are gated

Hand F respectively.

into fl ip-flop B by levels at inputs W, X and Y respectively

The same set pulses are gated
0

Inputs K and U provide sep-

arate direct set i~putstoflip~flops.A and S, respectively. All set inputs accept DEC standard 205-volt, Oo4-microsecond negat"ive puls~s. Assertion levels for the gating,level inputs are -3 vdc

" ; 10-17

The counting Rnputs (S for fl ip-flop A and the corresponding unlettered terminal/l shown
in the center of the schematic, for fl ip-flop B) are used only in module 4204X

<i below).

Flip-flop A has its 1 and 0 outputs at P and E, respectively; flip-flop B has its 1 and 0
outputs at Z and R

Both flip-f!ops share a common clear input at terminal To

Unlike the clear input of flip-

flop 4203 (in which an additional pulse inverter accepts a negative pulse) input T of the
type 4204 requires a DEC 0.4-microsecond positive pulse. This pulse is ac coupled by
capacitor C3 to the bases of A and B fl ip-flop transistors Q2 and Q7, respectively. For
example, when a positive pulse is appl ied to T, capacitor C3 references the pulse to the
level at the anodes of D6 and D14. This level is -0.75 vdc, determined by the connecti.on
through R34 to the negative supply

The small negative voltage prevents noise pulses from

passing through D6 and D14, which would cause spurious clearing of the flip-flops.

How-

ever§ a standard DEC positive pulse at T generates a sufficiently positive voltage to forward bAas D6 and D 14.~ and pass to the bases of Q2 and Q7.

These transistors cut off g and

the two flip-flops assume the 0 state.
d

FLIP-FLOP 4204X - This module is identical to flip-flop 4204 (~above}J' except that

the collector output of transistor Q8 {corresponding to the 1 output of fl ip-flop A~ is internally connected to the counting (complementing) input of flip-flop Bo The schematic of
fl ip-flop 4204 also represents modules 4204X if the dotted I ine in the center of the schematic is assumed to be a wiring connection

Flip-flops of the 4204X module make up the bits of PDP-4 registers that are also coun'terso
in addition to the inputs described in ~ above, flip-flop A has a counting input (S). The
carry output of f! ip-flop A and the count input of fl ip-flop B are connected inside the
module

Terminal V is the carry output of fl ip-flop Bu available for connection to the

next more significant type 4204X module.

The count pulse input to S may be a 004 micro-

second positive pulse.\' as it is when flip-flop A is the least significant bit of a counter.
Terminal S also accepts the rising level from carry output V of the next less sngnificant
counter bit when th~s bit changes from 1 to O. The clear pulse at T must be 1.0-microsecond wide so that the pulse does not end before the carries die out.

10-18

FLIP-FLOP 4214 - This module contains four 'i'clentlcal Hip-flops (#1 through #4) and .

a ·-3 vdc supplyo Each flip-flop ha·s 0 and 1 inputs and outputs. Moreover u each pair of
flip-flops shares a common clear input: P for flip-flops #1- and #2, and R for flip-flops #3
and #40 A standard DEC Oo4-mIcrosecond positive, pulse, applied to P or R/clears both.
asso~iated flip-flop~o

Beca~se".aU fourflip-f.IQPsare, J~e.n.tic:al"

the following descrIption

of fJ ip-flop # 1 also appl ies to the other three ,fl ip~flops.:
When fI ip-flop # 1 contains Ou··transistor Q 1 is' on'and transistor Q2 is off. The fl ip-flop'
,i,si's'fable in this state because the negative collector voltage'of Q2 is coupled to the base
of QJ by R2 0 n~e Cl,Jrrent flow, thr.ough R2 is enough to ~!1ep Q 1 saturated

The collElctor

of Q 1 is thereforeqt gr.:ound;thus the vol tage;divider '. R5and R6, biases Q2 off 0
roset'the flip-flop to the 1 state! the pulse output of'~ positive capacitor-diodegat~' r~
applied to H {one in} 0 Th is pu Ise turns off transistor Q1. The resu I ting negafive vol t~ge'!

crt the collector of Q 1 drives' Q2 into' saturation

The coll'ector of Q2 rises to ground po~

tential'·£! keeping Ql cutoff. Silicon diodes [13 and D4havea forward-bias threshora of
more' than 005 volts u and thus block smaller noise-pulse inputs from the transistor·bas:~s.·
The fl ip-flop is cleared ina simHarway by a positive pulse at E (zero in) 0 The clear pulse
.turns Q2 off£!, returning Ql to saturation

The bases of the two transistors in each fl ip-flop are returned to separate + 10 vdc Iines to
atlow: more precise trouble local ization through marg:inal testing.

f
bi.tso

FOUR-~IT COUNTER 4215 -

This modul.e contains four fl'ip-flops for use. as counter.

Th~ four flip-flopsuA, B, C and D,are logically independent.

The flip-flops may

. therefore be connected in any logical configuration 0 When the fl ip-flops are connected
as a counter", the significance of each flip-flop as a counter bit is determined only by the
ext~rnal connectionso

The module also contains 12 positive. capacitor-diode gates (C14-

R30-D 1 and C l-R7-D5 are two examples) and a negative dc supply. The supply, consisting of diodes D21 to D24 and resistor R29 f is similar to the - 3 vdc supply contained in
module 1 r03R (paragraph 10-208 except that -0075 vdc is tapped from the junction of
D21 and D220
Flip-flops B£!. C and D have complement inputs at terminals R, K and E, respectively:.
FI ip-flop A has separate set and clear inputs, but may be complemented by applying a

10-19

signal to both ,inputs simultqneously. Flip-flop C has an inhibit level input at M. When
the inhibit is enabled, fl ip-flop C cannot be complemented from 0 to 1, although it may
still be complemented from 1 to, O.
Positive pulses (either a standard 0.4 DEC pulse or the positive-going output of a pulse
inverter) or a positive 3-volt step (such as the 1 output of a less significant counter bit
when that fl ip-flop goes from 1 to 0) drive the complement and c lear inputs. A -3 vdc
level at M enables the inhibit to fl ip-flop C. Carry propagate time per bit is 50 nanoseconds. Tbe following description of flip-flop A a Iso describes the other three fl ip-flops.
A ,positive pulse applied to' W {set one} or V {set zero} reaches the base of the associated
fl ip-flop transistor only if the transistor is on. The positive pulse changes the state of the
fl ip-:-flop by turning the on transistor off. When fl ip-flop A is 1, a positive pulse at input
,V passes through capacitor-diode gate C15-R31-D4 to the base of Q2! turning Q2 ofL, ,
The fl ip-flop switches to the 0 state.

Positive pulses at V now have no further effect, since

capacitor-diode gate C15-R31-D4 is disabled when flip-flop A is O. However! gate C14R30-Dl is enabled when flip-flop A contains 0, so that a positive pulse at W passes to the
base Ql i turning Q1 off, and switching flip-flop A to the 1 state.
If W is jumpered to VIJ the resulting combined input is a complement input. When this' input is pulsed

gates C14-R30-D1 and C15-R31-D4 steer the pulse to the base of the on

transistor, turning it off! so that the flip-flop switches state.

Gate Cl-R7-D5, associated

with terminal X, is permanently enabled because R7 is returned to -0.75 vdc. Thus a positive pulse at X clears flip-flop A directly. Resistor R7 is returned to -0.75 vdc rather than
to ground in order to prevent spurious noise from affecting the fl ip-flop. Since signal voltages are greater than -0.75 vdc, they pass through D5, but small noise signals are blocked.
The gate time constant (R7 xCI) is longer than that of the other two capacitor-diode input
gates because a 1 .O-microsecond pulse is used to clear the counter. This allows carried
to die out before the pulse ends.
Terminal R (add FFB) is the complement input to flip-flop B. A positive pulse at R is applied
simultaneously to two capacitor-diode gates. These gates! C16-R32-D6and C17-R33-D9,
steer the pulse to the base of the on transistor! turning it ofL When flip-flop B is 1, gate
C17-R33-D9 is enabled! and a positive pulse at R clears FFB. Conversely, when FFB is 0,-(.;
gate C 16-R32-D6 is enabled, and a positive pulse at R sets it. The complement input to

10- '20

fl ip-flop 0, term ina I E (add FFD), 'operates'sim il(H~ly
..
.' c ' : , " ,
"..'1
0

\
Terminal K (add FFC) is the complement input to flip-flop C'o

Pulses at K are gated by

two capacitor-diode gates,' like the two i~put gates offlip~flop B, described above. One
.

. ....: . . . '

'..

,.'

,:.

..1

....

'..

of the two input gates offlip-flop C is returned to th~ collector of Q6. This gate, C19R35-D14, is enabled'~hen;FFCIs'lo;lf FFC f~'l~ a posi'ii'~~'pulse at K is gated to the base
of Q6, turning it off, and clearing th~ fl.ip-flopo

Th~' oth~;,c'~pacitor-diode gate, C18R34-D 11, is returned to the outp~t of 'a ;ne'gati~ebl(g~t~," of which the collector of Q5 is

one input, rather than directly to the coltector"of Q5.

.',

This OR gate! compo~ed of 025, 026, and puller'resi'stor R38, functions similarly to the
.

. .

.,..'

: •. '

gates described in paragraph 10-3~ (diode 4112)

'j
0

.,..

The anode c:>f 011 is at the more nega-

tive level of either the collector v~lt~ge~fQ5 o~ the inhibit level at terminal Mo When
the input at M'is ground&, flip-fl~~'.C fun~tion~ a~:~the others in the module, and is com"

plemented by each positive input pulse at K.' However, if the inputatM is -3 volts, the
pulse at K cannot ,'rea~h the b~~e of 05, even fhough'the collector of Q's i'~ ground (the
fl ip-flop is in the 0 state). On the other hand, the p~th to the base of Q6 isnot affected
by the input at Mu so thefl ip~flop may be complemenfed from 1 to 0 regardless of the inhibit level.

'"
t,

FLIP-FLOP 4216 - This module contai~s 4 flip-flops,' 2 pulse inverters, 12 positive'

capacitor-diode gates, and a sedes-strin~' sil icon di6'de negative dc supply. The fou~ fl'ipflops have internal output to input connectio~s betwe~n consecutive fl ip-flops so that the
,,':
.~...
~
four fl ip-flops constitute a fou'r-bit shift register package Four capacitor-diode gated in,.

}'"

puts are provided for parallel read-in of 1s.

FI ip-flops Au Bu C and 0 include transistors Q9-Q 10, 97-Q8, Q5-Q6, and Q3-Q4,
respectively. Except for the number and ,arrangement of inputs, these fl ip-flops are simi lar
to those of module 4215. Transistors ql ,,andQ2a,re the, two pulse inverters. All 12
capacitor-diode gates are used at the inputs of the fl ip-flops; each gate (C2-R6-03, for
example) is similar to the positive ~apa~itor-diode gates of module 4128 (paragraph 10-4~).
.

~iodes 028 to 031 and resistor R44 make up the negative supply.

This supply is similar to

those contained in the inverter mo~ules (see paragraph 10-2).
For shift operation, the shift pulse input is!throug~. ter.mi,nal R to the base of Q1.

10-2; l'

Complementary input levels at J and F gate the inverted pulse at the, collector of Q 1 to :
the set or clear side of flJp-flop D. For parallel read-in of hv the read-in pulse is appl ied
to PI to the base of Q2. The input levels at H,M, T and Y,gate the inverted pulse at the
collector of Q2 to the set sides of fl ip-flops D, C, B and A, respectively. A pulse a'tX
clears all four flip-flops simultaneously.

Pulse inputs are DEC standard 0.4 microsecond

pulses, negative for inputs Rand P, and positive for clear input X. , Level input~ are ground
for assertion.

Input-o,utput de,lay for each fl ip-flop is 50 nanoseconds.

Assume that all fl ip-flops are clear prior to a shift operation. A negative pulse aJ R is
inverted by Ql I appearing as a positive pulse at the collector of Ql. The positive pulse"
is ac coupled to the anodes of diodes D4 and D 11 by capacitors C4 and C 10 respectively.
,

The voltage at the anode of D4 is the sum of the positive pulse and the level at terminal

J v while the voltage at the anode of D 11 is the sum of the positive pulse and the leve! at

F.!f F is ground v and J is -3 vdc (read in 0), only D11 is forward-biased v passing th~
pulse to the base of Q41 tending to cut Q4 off .. However, Q4 is already cut offv thus
fl ip-flop D remains in the 0 state .
The pul'se from the collector of Q1 ~s also applied to the 1 and 0 inputs of flip-flops CU'

B and AU' through capacitors C8, C15, C13, C20, C18 and C23. However, the pulses are
gated only to the clear side of all fl ip-flops, because each 0 input gate return is to the

1 output of the flip-flop to the left. Since all flip-flops are initially clear, the 1 outputs
are at gr?und, enabl ing the 0 input gates. The 1 input gates of fl ip-flops C, B and A are
disabled by the -3 volt assertion levels at the 0 outputs of fl ip-flops D, C and B. For
example, C15 couples the pulse to the anode of D17. Diode D17 is forward-biased because the leve I return of gate C 15-R21-D 17 is to the grounded coli ector of Q30 The same
pulse is coupled through C8 to the anode of D9, but D9 is reverse-biased by the -3 volt
level asserted by the 0 output of fl ip-flop D. Therefore the shift pulse tends to clear fl ipflop C, rather than to set it; so that flip-flop C remains clear after the shift pulse.
Ifg at the shift pulse l J isat ground and F is at -3 vdc (read-in 1), diode D4 passes the
pulse to base of Q3. Transistor Q3 is cut off, and fl ip-flop D goes to the 1 state

The

level at the anode of D9 goes to ground after a delay approximating the time constant
C8 x R12. Therefore the next shift pulse passes through D9 to the base of Q5, setting flipflop C.

In a similar manner subsequent pulses shift the 1 through the register.

10-22

Parallel read-in to the four fl ip-flops is accompl iished by a negative pulse applied to terminal Po The pulse at P:'is' tnverted at the collector of Q2.

This positive plJlse from Q2 is

gated to the bases bfthe odd 'numbered transist'ors of fI ip-flopsD through A by capacitordiode gates. 'In this case g the enabl ing levels that' sel'e'c't the flip-flops to be set are present at inputs HfI Mg Ti and Y. For example g a posfttive pulse from the collector of Q2 is
ac coupled to the anode of D3 by ,cqpa.citor, C2,~ The pulse forward-biases D3 a~d passes
on to the base of Q3 only,if input H haS"beenat grol)nd for several time constants.

If the

pulse reac~es th~base of. Q3,. this transistor is cut. off and flip-flop D is seta
A positiy;e piJlse at terminctl-'X clears the register ldy'tuhiJngoff all the even numbered
transistors of flip-flops D'through 'Ao Afour:"'output' positive capacitor-diode circuit (C6R36-Dl0-D16...;D22-D26) couples the pulse to the transflst.'Or bases. The gate return connection to -0~75 volts:prevents noise pulses from affect,ng the flip--flopso

FLlP"'FLO'P4218'- This module contains four flRp-flopsg a pulse inverter O' eight posi-

tive capacitor-diode gates O' and a negative dc supply. Depending on external connections O'
type 4218 Hip-flbPs ma'ybe used as bits of 'shift registers or buffer registers with a jamtransfer para I! el read-in 0. Flip-flops # 18 # 2g#3 and # 4incl ude transistors Q2-Q3, Q4-Q5 tf
Q6-Q7 b' and Q8-,Q9 u respectivelyo

Transistor Q 1 !S the pulse inverter.

All inputs are through posHive capacitor":"diodegatesi each of these gates is simi lar to the
gates described in paragraph 10-4~ (module 4128) 0 The negative dc supply I consisting of
diodes D 17 to D20 9 and resistor R28 is similar to the -3 vdc supply described in paragraph
10-2 {inverters}. Howeve.r,thesupply in module 4218 has a -Ou75 volt tap at the junction
of diodes D17 and D18i ,and a ,-2025 volt tap at the i.~.mction of diodes D19 and D20.
The read-in pulse inpufat terminal Pisa DEC standard 0.4-microsecond negative pulseo
Levels at terminals Eu'Hg' S and V gate the pu!se '~O the set side u and levels at F b' Kg U
and X gate the pulse to the clear side of flip-flops #1 through #4 g respectively .. Gating
levels are asserted at ground 0 All four fI ip-f!ops are cleared simul taneously by a DEC
,.0

standard 004 m!cro~econd posftive pulse at Ro
50 nanoseconds

input-'output delay for each flip-flop is

The four flip-flops become a,shift register if the 0 output (l) and 1 output (J) of flip-flop

# 1 are connected as gating levels to the 1 ;npu1' (H) and 0 Input (KL· respectivelyO' of

flip-flop #2; and similar connections are made between flip-flops 112 and fl3v and '3 and
#4. The resulting four-bit shift register is comparable to module 4216 ~ above) except
that it lacks gated parallel 1 inputs

A positive pulse at R clears the register v and a

negative pulse at P reads into flip-flop #]

Subsequent pulses shift the 1 through flip-flops

#2 f1 #3 and #4.
When the four fl ip-flops are used as a buffer register with jam-transfer parallel read-inu
the external connections are made differently from the above

In this case§ both 15 and

Os are transferred (the register need not be previously cleared) into the flip-flops of module
4218 in a simultaneous parallel transfer from corresponding bits of another register.; The 1
and 0 gating level inputs of flip-flop #2, for example, are connected to the 0 and 1 ou'tputs u
respectively, of an associated bit in another register

When this associated bit is 1b' the

negative assertion level at its 1 output disables the 0 input gate of fl ip-flop #2; and the
level at the 0 output of the associated bit, asserted at groundfl enables the 'I input gate
of flip-flop #2. Conversely, when the associated bit is 0, the 1 input gate of flip-flop #2
is disqbled and the 0 input gate is enabled . Similar connections are made to the 1 and 0
',,'

input gate term inals of the other three 4218 fl ip-flops

A negative pulse at Pcauses each

fl ip-flop to assume the state of the corresponding bit in the associated register.
The response of ,the flip-flops of the type 4218 module to the read-in pulse is similar to
the response of the fl ip-flops of the type 4216 module (R above).

10-6

AMPLIFIERS

This section describes seven modules which serve to provide power ampl ification for PDP-4
logic pulses and levels.

Pulse amplifiers 1607, 4604, 4605, 4606 and 4606R power ampl~fy

and standardize DEC logic pulses.

Bus driver 1690 inverts and amplifies logic levels. Sole-"

noid driver 4681 is basically a switch which enables a small amount of input power at logic
level voltages to control larger amounts of power at higher voltages for use in external circuits.
a

PULSE AMPLIFIER 1607 - This module contains three inverters and a -3 vdc supply.

The three pulse ampl ifiers include transistors Q2-Q3, Q5-Q6 and Q8-Q9. The inputs
to the three ampl Hiers are pins H, Land Pg while the outputs are E-Fg J-Ku and M~N!
respectively. The three inverters are Q 1! Q4 and Q7. Diodes D 16 through D '19 make up
the -3 vdc supply.
10-24

A pulse amplifiergenerates:ah, ou'tpuJ puJ;se"wh~hev.,er it,s input 'is grounded • The inpu;t ";
may be grounded by conne,cting :it tothe'icQ1U'eat.or::of one or more pulse gates (such as the
Ql circuit). The Jnputto ,;t.he::co'mbinedlcircuit'is~ithen: the base input of the pulse gate~
Normally the signal applied to'theJnpu:f is a.DEC' 70~ncmo!$econd negative pulse

J:iow-

ever, the input requirement is satisfied by any 2 to 5 volt negative pulse having a fall
"

. ~' . ;'

' -:

.' ,

.~.: l \: _

" ._

.~ . <~

time less than 50 nanos~conds, and a width of at, least 50 nanoseconds at -2 volts. When
the input is pulsed by. a' sig~~I' ~~~;ing: t~e~e, spec:i'fications, the out~ut generates a D.EC"
standard

70,-nanos~~ond'puisei ,d~layed by~"25:"na·~oseco~ds. This puise is c~pabie of driv-

~;t;.

. <',

,. ~.

'.'

;' :': :p"'J

, , '

,ing 16 units of pulse load, or 20 units, if the' loads are near by.
•

;

•

; \ : ' \ ;0.

" .

~ ~~ _,'

- -. '

, Because all three pulse <ln1pjifiers qr.e i)~~~ti~a.,I,' the following description of the;ornplifier
"

•

: including, transistors Q2, Qnd~~Q3.appl ies ;j9~ally:,t~.fheother two ampl ifi'~rs in 'th~ modyle

Assume that' the emitte?of":Q'l j'sigrou:nded (Z) 'and thcIt the collector ofQ 1 (X) is connected
:,

to t'he'emitferofQ2: (H).

In the quiescerhstat~,,·trdns-rstors Ql, Q2 andQ3,are c,uioff.
:

;

. ~;' \ . ~:

The collector of Q 1 and:the erni ttetof 02: 'are'co'nhe-c:ted to" the junction of'resis~~r R3, and
silicon diode Dl, and are therefore at approxiniQt~~ly'-4 vdc. Resistor R3- ahd di<;>de D1,
together with R4 and D2,. ~orlll a.volt~ge djvid~r,be~e~:m-15 vdc and -3 vdc (with ~thEf
diodes forward-biqsed)

The base qfQ2 isc<?nnette9 t9)he voltage"divid~t' af',the j~nction

of D1 and D21 and h,h~ld at apprqxirry'!tely' ~,303 vdco
Another vol tage divi'der is formed by the seris~ 'combination' of R11 and R16 •• Th is v<;>ltage
divider holds the collectors of Q2 q~d:,Q3q,t . ap.pr.oxi~atel,y -8 vdc. Diode D4 is for~ard
biased, so that the. collector, voltages of Q2:,.?nq 93
. 9r:eseparated by only 0;3 volts. 'The
' . , ' , ' '.

base and emitter of Q3 are;at,gro.und~There is nO,vo,ttage acr,oss outputs E and F.
When an input pulse appears-at the base'ofQl ('a<}; th'is transistor saturates and gfouh~S the
emitter of Q20 Thiscau,ses,Q2,to saturate; ,resisto~ R~ limits the base current. The collector
of Q2 drops from -8vdc, to ~ro~n~

:lb is c;lrop ,~mrp~,q iate,ly appears across the primary of T1 •

Initially this voltage:remai~sJairly"constal')t~ec~u;seoLthe low-resistance voltage divider
~_

R11, and R16

" ,

i ' ~.:

.....,'

" .

Wh~r th,e 1transfo~)mer . staf,t~(~r~~!!p:9rn?:r.,~" s~rp~nt than originaIJyJIC?w~9

through R6, D4 disconrec,t~ thr' G.C?,I~~ftP~;~,i;~<;Yltr.J~Rf1.. RJt-~J po The vol'!ag~ ,c;l,.cr9s~T1
begins to decrease., c:qpacjt~)r C,2JlJ~~fS, the ,~ircuJJJo,giye the correc~ output puls~ )'Vidtho
.

'_.,. '

' .,.J. I ; .

_.'.

!,..

; .' ; ~ .

t.,

....

. , . "

Whenthetran,sfon:ner~oltage, ~Cls;drc?p,p~d t(?-'I+~I~c>. }b~:ot;Jtpv,t pulse end~ ••. Resistor, ,R5 and
' . . .

•

I " ,

'\...',

••.

diode D3 clamp the overshoot in the primary 'of T1

.•

The Q3 circuit {including R8, T2, 05, R7 and (4) amplifies the pulse from the secondary
of T1 (see ~ below). The output pulse may be made negative by groun~ing termJnal F of
the secondary of T2; or positive, by grounding Eo A terminating resistor in the range of
82 to 220 ohms is used aLthe ends of cable distribution lines to prevent signal reflections.
b

PULSE AMPLIFIER 4604 - This module contains three identical pulse amplifiers. The

first pulse amplifier includes transistors Q1 through Q3, and has its inputs at terminals E
and F. Outputs are at J a'nd H

The second pulse ampl ifier is composed of Q4, 05 and

Q6; inputs are M and N; and outputs are Sand T. The third pulse amplifier includes Q7
through Q9, with inputs at Y and Z; and outputs at V and X. An additional pair of control
, terminals is associated with each of the three pulse amplifiers .. For the first pulse amplifier,
these control connections are K and l. Shorting K to l with an external jumper con"nects
qn interna,1 c:;apac itor in the circuit of the first pulseampl ifier. When connected;~his
, additional capacitance legthens the duration of the output pulse to 1 micorsecond. ,The
corresponding control conne~tionsff'rthesecot'\~ and third pulse amplifiers are terrp,inal
epair~ P and R; and U and W,

respectively.

'Negative going signals with an'amplitude of 2.5 to 4 volts, a fall time of less than 005
, microseconds; and a width greater than 60 nanoseconds drive inputs E, Nand Z.. Positivegoing signals with an amplitude of 2.5 to 4 volts, a rise time of less than 0.5 microseconds,
and a width greater than 60 nanoseconds drive inputs F, M and Y.
'When properly driven, each 'amplifier produces a OEC standard 0.4-microsecond puls'e
across its outputs.

If the external 'jumpers are added to the circuits; the outputs produce

1-microsecond pulses.

Because all three: amp/ ifiers are identical, the following description

of the qmplifier including Q 1, Q2 and Q3 appl ies to each ampl ifier

The pulse amplifier consists of a monostable mul tivibrator (Q 1 and Q2), and an output
pulse ampl ifier (Q3). Capacitor-diode C4-06 couples a negative input at E to the base of
Q2. Capacitor-diode C3-03 couples a positive input to the primary of transformer T1.
This transformer inverts the 'positive input, and 05 couples the resulting negative pulse to
the baseofQ2. An appropriate pulse at either input thus provides a negative pulse at the
base of Q2. This negative pulse triggers the multivibrator. The multivibrator generates
a negative output pulse g which is amplified by the circuit of Q3. The output is a negative

10-26

pulse at terminal J if H is grounded, or a ppsitive,pulse at H if J is grounded.
In the quiescent
state,Q,l
i.s on,
and
Q2 and
,Q3 are
off • Base current for Q 1 flows through
,
'. "
- '.
•
" .
"
i.-'~""

R1, holding Q 1 in ~Qtu~ation. Volt~ge divider R7-R9 shiftstfte sl ightly negative Q 1 collector voltage positive
qt the
base of Q2, keeping Q2 at cut-off.
Diode 01 clamps the col!
. ,
".
,
~.

lector ofQ2 to -3 vdc. Voltage divider R8~Rl0";;R13 biases the base of Q3 positive, hold•

VI"

~_~ , '<t

~ J'

; ' .

ing Q3 off. , The ~ollec.:tor of Q3 is somewhat more negative than -7 volts, as determined
,

;

~}.

•

by voltage divIder Rl)-R14., No ~urrent flows i"n the 'primary of'T2, a'nd there i$ 'no output across the secondary.
'. When a negative pul~e is applied to input E, C4 differentiates the leading edge of this
>input signal, generating. a r']egative pulse .~t the cathode of 06. This pulse forward biases
D.6,and pa~ses to the ?ase of Q2. Transistor Q2 ,tur~s on, and its collector voltage jumps
from -3 volts to ground. Th.is positive step is coupled by ,capacitor C2 (or Cl in parallel
with C2, if pins K and L a~e jumpered), to the b~se of Ql. Transistor Q1 cuts off and its
..

collector voltage dro~s t~

-3 volts. Current flows from the base of Q2'through R7, holding

Q2 on even though the input pulse has ended. The multivibrator remainsln this state until
the' coup'ling capacitan~e (C2, or Cl'and C2) from the collector of Q2,to,.the:base of Q1
discharges.

Th'fs dis~harge time' is proportional to the capacitance. Hence~:t~,e multi-

vibratorst~ys in itste'mporary state 0.4'm'icrosecond if only C2 is in the circuit, or 1 micro'second 'if both Cl a~d C2~'re in the circuit. After the appropriate time, Ql turns on, cutting Q2 off. the multivibrator is back in its qui.e'scent state.
The negative pulse generated at the Q 1 collector turns on Q3. The Q3 collector rises to
ground level, placing approximately 7 volts across the primary of T2. Resistors Rll, R14
and capacitor C6 s'tabili'ze the vottage at terminal 1 ofT2 so that the primary voltage does
not diminish appreciably during the pulse. The-output vol tage at the secondary is propor. tional to the primary .vol.togeo, ,The pulse terminates when the multivibrator returns to its
'quiescent state,~utting,off Q3.• , Diode D8 and resistor R12 damp the overshoot in the
primary of T2. DiodeDZ clips the overshoot at -15 volts, so that excessive' voltage is not
applied to~,the coHector,of Q;3.,
A positive pulse a"t terminal.. F tdggers t~e,sal11~,chain of events to produce an output pulse
across J andH.

However, th~ pulse is invertedhy Tlbefore being applied to the base of

Q2. ~ Diode 02 ane). resis;tor R5 damp ~h~, transformerduring recovery. Diode 05 blocks the

1'0-27

positive recovery p'ulse from the base ofQ~.-

~ULSE AMPliFIER 4605 - This module c8nt~fns'three identical' pulse -amplifiers, a

negative diode AND gate, ~nd an inverter •. The first

of the three pulse amplifiers includes

transistors Q 1 a~d Q3". Tr!=lnsistor Q2 is the inverter. :The second pulse ampl ifier includes
.

Q4 and .Q5; the third, Q6 and Q7" Diodes D 1 through '06 make up' the negative AND
gate

Except that a p~ir of' i~put pins is provided for each gating diode (M and N are

al ternative inputs t~ D6, for exampl~) the diode g'ate and inverter combination is simi lar to

one of the type 4111 circuits (paragraph 10-3~.

Tlf.lrminals F~ J andL'are the'inputs to the three pulse amplifiers; the respective ou'tputs are

E, H an~ K•. When~ver
'

02 i~'~atur~ted (gro~ndingthe em'itters of Ql, Q4and Q6), a

DEC standard" 0.4 negative pulse applied"to an amplifier input generates a·similar pulse at
the ampl ifier' ~utput. '. Negative DEC levels at all six diode gate inputs are required to
. \

saturate Q2. Because all three pulse amplifiers are alike, the following description of the
amplifier containing Qf and Q3 applies to the other two.

In. thequie,scent state the voltage ~t the base of ,Q1 is more positiv~ than the emitter vol. tage qAs a, resul t, Q 1 i,scut off.

No current,flows through the primary of transformer Tl,

and there is no volt~ge across secondary. ~he secondary of T1 grounds the base of Q3 1
holding Q3 off.

No current flows in the pri~ary and there is no output a pin E. Vol tage

divider RS-Rl1 holds the GPllec.tor voltages of Q1 and Q3 at approximately -7.5 volts. The
Q3 collector is directly connected to the voltage divider while the Q1 collector is clamped to the divider by R7 and D9.
Assume that negative levels are present. at the anodes of D 1 through D6, saturating Q2.
The Q2 collector is then at ground"enabling all three pulse amplifiers.
When a negative 'pulse, m~eting the input requirementsf is applied to F, Q1 saturates.
This grounds terrriin~1 2 of' ·Tl. Theother end'of the primary, at terminal 11 remains at
-705 volts since the voltage sourc'e is of fairly low impedance. The voltage induced in the
secondary of T1 is proportional to the voltage appearing across the primary.
'Increasing current flows in the primary of Tl. However, the voltage across the primary
remains nearly constant until the transformer starts drawing more current than originally
flowed through R7.' 'At this time, D9 disconnects the collector of Q1 from the voltage
10-28

divider

Capacitor C'3 tunes the primary winding of T1 to give the proper pu'lse width

When the voltage across,the transformer drops to zero, the output pulse endso Resistor R5
damps the overshoot

In a similar manner, the circuit of Q3 further amplifies and shapes the pulse. This circuit
consists of Q3, an emitter degenerating resistor R12, output transformer T2, damping components R9 and D10, and bypass capacitor C4. The output pulse is negative at terminal E.
d

PULSE AMPtlFIER 4606 - This module contains three identical pulse amplifiers. Each

of the three contains a,basic multivibrator and pulse amplifier output circuit ident'ical to
that of the type 4604 (~above). However, the input circuits of the type 4606 differ in the
following three respects:
(1) Transistor inverters are used for positive input pulses, replacing the input pulse
transformers of the 46040
(2) A capacitor-diode gate, similar to those of the type 4127, provides an additional
negative pulse input to each ampl ifier in the type 4606.

(3) The input and output terminals are as follows:
TERMINALS
INPUTS

PAl

Direct Positive Pulse:

Direct Negative Pulse:

Gated Negative Pulse:

Negative Gating Level:

Positive Pulse Out:

Negative Pulse Out:

OUTPUTS (same as for type 4604)

PULSE AMPLIFIER 4606R - The 4606R pulse amplifiers are identical to those of the

4606 module except that inputs F, N and Vare internally connected to clamped loads. As
a result, these inputs are gateable and are driven by positive-going pulses from collectors
of inverter pulse gates.

'BUSDRIV.E~ 1690 - Thi.s module contain,s f,~ur;,i~vert;i;n.g level (101plifiers, and~; ~8. 75

·vdc·supply •.. ·Each·,ampHneT:~~·~..fdt!s"~9t~::~~ls at low Jmp~dance, for use;in
heavily loaded logic lines. The output rise and fall times of level changes are ext~nded
to 1 .,0 micros,econd. This slow-switching characteristic makes the 1690 ampl ifiers usefu I
:~.:;.

,lj'-:

j'.

, : ' .•.•

~,.,.

~t~:...:,;.,,;;·?·::l;',.~!!.~ ... (

.~ ..-' "'. t~

·f~ . • ;.. :•. , ;

--l:~1·.,

.~~.

,;i:

.. ~.

,.(~.

.':,.~"

;- .~~:t,~··,tJ.;··'i'\.; .. " .•~',:'

t':

;.,'A)'·····:~!~r·.~'.

::"

;(~}'.~,.....

t~.~~'.~;.·)·., ...·i.

, ' .

•

...

~ ,,",W

•

" " .

i.:lq9rc.Je~els~(O}:md;.":,3..vQIt.s),9,,r..e,9Ppl~~d at }nputs,~,Mf U and So
"'~_"

(.',~.

in circuits when; rapid changes of level cou Id produce unwanted ringing
~

.'"

outputs at L, N, T and R are the inversion of the input levels

.,-

The cQrrespon,d~~g,
_

, , ' " ,

Each input represents

,L." dpprh'ximdtely one-half unit:'OfS'.o.megdcycle base load. '" The'maximumovlput capability

:{':'~~f;~Ff{r:rlifier:r~,il5'lHlitsof base:lodcJ::. Each 6mplifier;:is :1dentical. Thei·amp.lifier with
; ..

When a -3 volt level is applied to input K, transistor Q1 turns on and it"s c~lrec)to/r'i;~~s
~t~"~rq~r9~. ,This y()'ta9,~ ri~~ cuts, <;:>ff D1 ~ and allows ~4 and ~5 to bring th~ base~ of Q2
" . "

•.

. .

'. •

. '

~'"

. '

,'....

r , : " . ;,

.: _

•

and Q3 toward +1 Q vdc. The positive-going rise ends at ground when D 1 again c,?nducts.
Transistors Q2 and Q3 are complementary emitter followers
~':. ':-.~

.';.~'J ~I:":"-~'.

.~_

'..

>;',

,;;.

..... ~

~' . -.>

One of these two transistors
:_--;;-

" ' .

'.-:

always conducts (Q2 when the output current flow's 'to the lodd, Q3 when the curtent flows
from the load)

Output L

at the ~~itte~s df Q2' dnd' Q3 ols6'"'rises ·togrolJnd. ':~"';lt:

When ground level is applied to in:put K', 'the 'circuit 5wit6hesstate'. Transistor Q1 cuts off,
and the Q 1 collector voltage foJ Is toward -15 vdc.
',; ",'

at -3.75 vdc

However I D 1 and 03 clamp the voltage

': .. J;

The -3075 volt, level is applied to tiie bases of Q2 and Q3. OutputfQllows
t.,

'F:,

. . ,',

the base voltage applied to Q2 and Q3. C;:~nsequently, the output at L fa'ils to approximately -305 volts.
Cqpacitor C2 delays the changes in output levels. Whep ;the input r,ises from -3 vdc to
• • ":. \¥ ~ •

".~'

ground, C2 must charge through R3 and D 1. Converse~y I V{h~n the input drops from ground
to -3 vdc, C2 must discharge through R4 and R5. Diode D1 prevents the low collector
resistance of Q 1 at saturation from shunting the; dis~ih6rge 'of (30

Diode D2 compensates

for the level shift introduced by D 1.
~'

SOLENOID DRIVER 4681 - This module contains three identical driver circuits. Each
circu h~opercites' '.,(ils.d"switch, .,capable' of swit2h'ing a '50Q-rri'i lliampere currenf,ih'a 70-vo It
\

(maximum)' :c.ircui-l o ; Switch control' inputs are standard IDEC logi c levels . Each sole~oid
driver cdn cQnt~ol ~n .i.l}dl,lGt..iy~)qad i ~uch as punch soleQQid.~ or/ypewriter relays.: ' ;
The three switch inputs are terminals K, :M and Ro The corresponding outputs are L,N

and Po Terminal E is connected to the external load return voltage source 0

Because all

three solenoId drivers are "identical," the following descripti'on of circuit 1 applies to the
other two drivers

When the solenoid driver is in the quiescent condition u the input at K is -3 vdc

Since the

emitter of Q 1 is at ground potential u Q 1 is saturated, and its collector is at ground

The

em itter of Q2 is at -2025 vol ts (the forward vol tage drop across diodes D 1 through D3)

The base of Q2u at ground u is positive with respect to its emitter, so that Q2 is cut ofL
Under these condit-ions; the load circuit is openo Diode D4 connects the Q2 collector to
the external negaHve supply, protecting Q2 from highly negative transient voltoges resulting from switching inductive loadso
output is at' the load return vol tage

No current flows in the externalcircuitl' and the
0

When input K is grounded u Q1 cuts ofL The collector voltage of Q1 drops toward -15
volts O' turning on Q20 "This completes the load circuit, allowing current to flowo

10-7

MEMORY ELEMENTS

This paragraph describes seven memory plug-in units: sense amplifier 1538, sense amplifier 15400'
read/write swntch 1972!/ memory driver 1973 u resistor board 1976, resistor board 1978, and
inhibit driver 19820 Sense ampl ifiers 1538 and 1540 perform simi lar functions.
other, but not both, is used in a PDP-4 memory module

One or the

The sense ampl ifier determines when memory cores change state (refer to paragraph 8-4£).
Read/write switch 1972, memory driver 1973 u and resistor board 1976 are used in series with the
X and Y core windings to form the read-write current path (paragraph 8-4~:)

Inhibit driver

1982 and resistor board 1978 are used in series with the inhibit windings to form the inhibit
current path (paragraph 8-4,~)
a

SENSE AMPLIFIER 1538 - This module contains a difference preamplifier, a rectify-

ing slicef u and a gated pulse amplifiero A balanced input, generated when a memory core
changes state

is appl ied to the input of the preampl Hier

Here the input is ampl ified

enough to reach the slicing voltage. The preamplifier also discriminates against commonmode noise signalso Differential signal gain of the preamplifier is 20, while the commonmode gain is 00

10-31

The pulse ampl ifier gate is enQ,bled when the prean;tpl}fie~; outputreqches, a predetermined
slice level. A strobe pulse; is\applied to the pulse input,ofthe amplifier during the specific
time interval when the memory cores are read and may change state

An output pulse

from the sense ampl Rfierindicatesthat. duri~g the strobe time a core changed state! and
thereby produced a slice level which enabfed the pulse amplifier gate

The strobe permits sampling the memory'sense :wi~ding~atthe particular instant of the read
operation when the signal-to-noise ratio is besta This accurate timing increases the certainty that every time 'a memory ,core being read actually switches from the 1 state to the

o state, this change of state wJII indeed be sensed; Clrd conversely, that spurious noise
signals will not be wrongly interpreted as a change in core state

The two ends of the memory sense winding are connected to sense ampl Hier inputs Hand
FoThe output pulses induced on the sense winding when the memory cores change state are
applied across these two inputso A 70~nanosecond sta,ndard DEC negative pulse is applied
to strobe input RoThe polarity of the sense ampl ifier output depends upon the output
terminal wiringo When L is grounded! a positive output pulse appears at Pi conversely,when
P is grounded! a negati ve outpu't pulse appears at Lo The preampl ifier outputs {T and V)u
the sl icer test point (5) and ,the gating level output (M) are used only for troubleshooting

Balance potentiometer.Rl,adjusts the virtualgrounq of the sense winding for minimum re•

. . .

•

"..

covery time from the noise genera,ted by the inhibit currento Potentiometer R8 is the zero
set of the direct-coupl;ed compound-connected amplifier Q2-Q3-Q4, while potentiometer
R5 varies the threshold leve(at which the pul,se a~pli'fier is ~~abled. This threshold level
can be varied from 0 to 50 mi Hivoits '(referred to the preampl ifier inputs). Procedures for
making these adjustments are discussed in paragraph 11-4~o
Before the memory cores are read, no input is applied to the sense amplifier from the
memory sense windingo The two bases of Q2 are held atground by potentiometer Rl and
resistors R2-R3o Assum'ing' that potentiometerR8 is 'set so that the differentia I preampl ifier
is in balanceuthe collector'current through both sides of Q2 depends on the settingof

pofe~tiometer R50 This currentI!' in turn! determines the vottages on the bases of sUcer
transistors Q5 andQ6'o

In normal operation,'· R5 i'sset so that these base vol tages are more

positive than the base voltage of slicer transistor Q7 {sri icon diodes D 11 through D 14 hold
the base of Q7 at approximately +7 vdc}o Consequently! the emitter voltage of Q5! Q6
,10"'32

and Q7 which follows the voltage at the base of Q7, biases Q5 and Q6 ofL
Since Q7 is conducting, the voltage at the base of QS is clamped by Dl0 at 0.3 vdc. As
a result, Q8 is cut off, and voltage divider R22-R23 holds the emitter of Q9 at -3 vdc.
The output pulse amplifier is thus inhibited, since a negative pulse at terminal R cannot·
tri gger the ampl ifer by saturating Q90
When a memory core changes state, a vol tage is induced on the sense winding.

Input

voltages of opposite polarity are applied from inputs Hand F to the bases of Q2. For out
of phase signals, R31 provides the principal Q2,emitter impedance, while the common mode
emitter resistance consists primarily of the relatively high collector resistance of Ql. Consequently, the differential signal is ampl ified substantially more than a common mode input.
Transistors Q3 and Q4, in compound connection with the two channels of Q 1 raise the Q2
input impedance whi Ie maintaining stage vol tage gain

The applied differential signal is amplified and inverted by the preamplifier, and drives
the base of either Q5 or Q6 negative

When th is base becomes more negative than the base

of Q7, the latter cuts off. Transistor Q8 saturates, grounding the emitter of Q9. The output pulse amplifier is now enabled. Thus, if R is pulsed during the time the input exceeds
the sl ice vol tage, a pulse is generated across output terminals P and L. The operation of
the pulse amplifier is similar to that of the type 1607 pulse amplifier described in paragraph
10-6a.
Switch 51 allows marginal check voltage on the+ lOA line to be applied individually to
each 1538 sense ampl ifier.
b

SENSE AMPLIFIER 1540 - This module is used in place of the 1538 sense amplifier in

.some PDP-4 computers.

It is functionally similar to the 1538 (~above), containing a

differential preamplifier, slicer and outp:.Jt pulse amplifier.

The pre~rnplifier differential

gain is 20, while the common mode gain is 0.5.
The sense winding inputs are Hand Fi R is the strobe input. The outputs, at P and L, generate either a positive or negative standard DEC 70-nanosecond pulse. When L is grounded,
a positive output pulse appears at Pi conversely, when P is grounded, the output pulse is
negative at L. The preamplifier outputs (S and U), and the gating level output (M) are
used only for troubleshootingo
10-33

Balance potentiometer R2 adiust's the' virtual ground of the sense winding for minimum recovery time from the n?ise generated, by the inhibit currento Slice potentiomete.,r R12 varies
the predetermined threshold !evel,at whnch the pulse amplifier is enabled
leveJ can be varned fro,m o,'to 50 mn! I!volts (referred to the input)
these two adiustments are gnven in paragraph 11-4~

Thisthreshold

Procedvres for making

Before the memory cores an~ read g no nnput is appl ied to the sense ampl ifier from the memorysense winding 0 T,herefore the bases of transistors Q 1 and Q2 are grounded by R19 R2
a.nd R30 The collectors ,Qf Q1. and Q2 are at -5 voltso Capacitors C3 and C4 isolate this
voltage from the bases ofQ3 and Q4. The quiescent voltage at the bases of Q3 and Q4
is d~termin.ed by the setting oJ slice potentiometer R120

Generally R12 is set so this voltage

.is sl ightly posiHve 0 Trans!storsQ3 and Q4 are cut off 0
Transistor Q5! which shares 'a common emitter connection with Q3 and Q4 is saturated
. since its base is at grou~d ~ Since Q5 is saturated, the Q5 collector and therefore the Q6
base are sl ightly posituve g holding Q6 off

Vol tage divider R18-R 19 keeps the emitter of

Q7 sufficiently negative to prevent the generation of an output pulse

When a memory core changes state, a voltage is induced in the sense windingo '.' Input volo

'tages of opposite polarity are applied from inputs Hand F to the bases of Q1 andQ20 For
out-oF-phase signals ll Cl g C2 and R28 bypass emitter resistors R5 and R70 As a. result, the
Q 1-Q2 preampl ifier stage produces a vol tage gain for such difference input signals.

But

for in:-phase input signals u the emitter resis,tance of the preamplifier stage is less than unityo
The common-mode noise reiection feature of the sense amplifier circuit is due to the low
common mode gain of the preampl iHer stage 0
At the arrival of the sense-'winding input signal, an ampl Hied negative voltage swing is
capacitor coupled to the base of either Q3 or Q4 (depending upon the direction of the
core 6S change of state).
When the base of Q3 becomes more negative than the emitter, Q3 conducts
of Q4 becomes more negative than the emitter, Q4 conducts.

If the base

In either case.v the voltage

at the emitter of Q5 follows the base voltage of' the conducting transistor (Q3 or Q4) 0 This
turns off Q50 Turn-bff of Q5 causes a drop in the base voltage of Q6, saturating Q6, and
thereby grounding the eml'tter of Q70 The emit,ter ground at Q7 enables the pulse amplifier

input gating.

Pulseampl,ifieroperationis sim'ilar to that of the 1607 pulse amplifier

(paragraph 10-60.
The pulse amplifier remains enabl'ed until the preamplifier output returns to its normal
quiescent level. During the time the gate is enabled, a pulse applied to strobe input R
generates an output pulse across terminals P and L. Although the pulse amplifier is enabled
when the memory core changes state in either direction (during write operations as well as
1

read operations) the strobe occurs only during read operations. Consequently, the sense
amplifier generates an output pulse only during read operations.
c

READ/WRITE SWITCH 1972 - This module contains four identical switch circuits with

outputs numbered 1 through 4. Each circuit is a switch with an AND-gate input, which
controls the ~ppl ication of drive current to a memory core winding. The followin'g description refers to read/write switch #1 (with gate inputs E and It), but applies also to the other
three switches in the module.
When -3 vdc is present at either gate input; the circuit acts as an open switch, preventing
the flow of core drive current. However I when both the E and F gate inputs are grounded,
the switch is enabled g permitting core drive current to flow through the associated memory
core winding. The core drive current then flows between bus terminal V and output #1 0N).
If one or both of the gate inputs is at -3 vdc, the D 1-02 AND gate causes grounded-emitter
transistor Q 1 to saturate. The comparatively small size of resistor Rl provides fast turn-on.
For fast turn-off; germanium diode D4 limits the excursion of Q1 into saturation.
When Q 1 is conducting, its collector is at about -1 vdc ~ This voltage is direct-coupled to
the base of Q21 holding Q2 off. This opens the forward-bias current path between -35 vdc
and transistors Q3 and Q4. These two transistors can then be held off by back-bias diodes
D5 and 06 respectively. With Q3 and Q4 cut off, the switch is open; and the drive current path betWeen V and W is interrupted.
The switch is enabled by grounding both the E and F gate inputs. This Cduses the D 1-D2
AND gate to cut off Q1

At the cut-off of Q1, its collector drops to a voltage more

negative, than the higher voltage at either V or W. During selection both of these pins
are returned td-3 volts.

10-35

Transistors Q2; Q3 andQ4 .turn o'n ;',.j The c.irciJi t· .betwe.en·)t Q.nd\ Wi c.lo.$e~Si ·pe~m.H'tiq9 ,<:;1\:' .
read or write current to flowo During the read portion of a memory cyc;!e" V'. is ¢tt;·.;"!~:13:~d.c
an~ W is returnedJhrou.9~. the!l,'lert;'l:9rx core ,win9ins.tc? -~ '(~..? ~ .~ore driv;e; curr.~nt lt~.en
•

I'"

~.':

•

. . .t

•

....:

;.;', ..

.a ...

I;,

~.: • •

' ••

",. \ :..

.,.

',l .... !~.

.t.'

f,IQwsprimarily through Q4o ..puring }~e write .portion of~he memory cycleb' the polarity is
.f

•.'1:

- i. • . . .../- •..:

•

:..

'~.

..-.~'

I.:

, ' . .~;r,.

. ,revers.edi V is at ,-3 vdc and W is,,returned to -J 3 lvdc through the core winding
L_
"

:," 't-l.·~'

;;".;;

.~.

- -:' "

~} ~

:'_:':..~:.

- '~".:,

.'~

t;;·

"'\"

drive curr~nt flows primarilY,thrqu,gh Q3 during this portion o~ th~ cycle
-

t. ,"!

','

'..'

I •

r:,

'".,'

;j,

'· .. ~.!<,. • . I

(

The cor~

0
:',

~.... '

,,:

l'~..

~. MEMORY DR;IVER 1973~' E~'~hPb P~4~~m'e~~'ry includ~~'tWo identical;type r973~\
.,

:.:-r·(,~-··""'·~;'

;':

~'¥-

....

, .... ~......

":..

--i.'

.·1t:1.,··.. ,~;,";

memory driver moduleso The'se-drlve'rs serve~'ds both source's'and sinks for the memo'ry' core-

~~i;YT.~r~r~entso Th.e ~~I~,-,,~r~~~curr,e~!-.P9th}.u~,.~.Jrom,o~~ . 1~~3 'r0du.le·{~~Tjr~9~9r.~~er) :,

,~hr~~~~,t;he enabl~~, ]

91 2 re,?d/w~it~ ,~~it~h~s J~ above) (lnd tr~ir assoc,.i<:J ted ,J?7{>, rT¥sJ~tP&

, ,.~o~Je~"clr~uits ~ ~T.:I~~) .~n~:·.7Qr~)'y.i~dJpgsl, to t~e se.co~d ) (73 mO~}JI~.~{th,e.Y"r~~~~, ~fJX~O.~
.·):In·'the: q'uiescent st¢lt~u' the irtput~of e.ither driver is a groundleve'l and theoutputds ;~·avdc

When a -3 vdc leve I is appl ied to the inpu t of a driver (ie, ;to the readddver du'fing'fne:'
!.,;;~{~Cl~.fqrtion of the cycle or, ~~/he.Vlfrit~.drh:e~ during the. wri!= p~rtion of the c~c~I~)~:'iJ~~

. putput falls
to ,
-13
vdco A ''';.;10-volt
potential
then.'1':".
exists between
the enabled
driver ond
;
., "
"
",....
';""
.'"
, ' : - ' : . ' ,.' '...,::,)~'

~), .. L';~fC;.:

t~~ q~,.iesc~nt driver

This pot~~t.iC?l: c9~~~~ .:.~ c~re-dr.~ve current to flp~ .~brough ,t~,e ,sp~,;tlfic

...
X ox:Y memory wir:lding selected
by theread/write
switcheso
The logic level inpu.t
is
t..,\ "','
.:'.-t'. . .
:.> .. ' "/ :\',/
"',
i"" . .
M'

•

• •

!~.

.....

:I~

appl ied to input J of the memory driver
,i';ip'ut'

'/0'

:.; .... \,. ,:':-:'. . ' .';

.j.

~'~".

,~,!.,

'.f:'~

The -3 vdc or -13 vdc ou tput is taken from out,t., "
~,.,;. · . " ; i ( ;
~,':\

• L
"\

~, ;.,~

:',

l',,: f'~

In the quiescent st~tE~/,agroYrl~.lev~Lis."appl,ied to input.)
•

','

emitter transistor Q1

,;,"

~ If,

,:.

.' ,,~, ':

: t

" , 'r'

, :

.. 0 '_.

Thi.s inpu~ cuts, off gr9~ndedJ

",.;

The resulting drop in the collector voltage of Q1 permits current

'through'R3 to turn on' Q2oTh~"t~11:~e'miuer cu~rk'~t' in t0rn; s~tur~tes parall~\1 transi;fors

•

~>!,1

,.:

~urrent throug~ .R3 also.,saturates,Q3Q' th~reby: grounding both the base of Q4 an,d the anode
,

.', ~

i·

of diode D30 The ground at the base of Q4 turns off Q.4.
D i.ode D3 s,-!ppl ies. cut':"'9ff
current
:. ..
.
.
>

to parallel transistors Q6 and Q8, turning these transistors off alsoo
With parallel transistors Q5 gr~ Q7 conducting,andparallel transistqrs Q6 and Q8 cut off,
,'"

"iI'

•

' , . : , :

,;'''''';;.

output
terminal
V is coupl~d
to th~
.,:",3
vdc sour.c~at;
R (and
isolated frQm . the -13" vdc sc;>urce
:;
.
,.',
. ,
:
..
.
" , ;! .
}..
.'
~

at W)

The memory driver output in the quiescent state is therefore -3 vdc ..

10-36

! :_ 'I "

Trar{sistor 01 ~hen:\sd:hjratesg

~n the active st'ote g a ,·,3 vdclevel is' a,pplled to tnplJt J~

groundnngthe base of Q2 and the anodes of D1 and D20 The ground at the ibQse 'Of:Q2turns off Q2 • . Duc)des D~ and D2 'supply cut~off curr~nt to para lIel transiStors 'Q5~a'nd Q7 i

saturaHon" The Q4 em\ith~r 'current in turnsaturatesQ6 ahd Q8 ..
~:('.,

,',

:~i.

:'.~

.',

,~.

'~'_'.

,_:

With parallel trans~stors Q6 and Q8 conducting g and parallel transistors Q5 and Q7cut off!
output V os coupled to the -13 vdc source of' W (and isolated from the -3 vdc s~~r~~;~t R)
'!>:'1'he" mem'ory drrve'r output' fnth~dctive state is therefore ~ 13 vdc ..

. ',~~f "

~:"Y'RES~STOR BOARD, 1976'r.Thus moduie contains elght,50-ohm" 3-wa,tt resistor~,?Y'{J/th

'1/2

tolerance .. A capac.Rtor,and resBstorare addedjn parallel with eacr'qf ff:he_§p-""':.~hm

resistors ..
Each:of the eight par91!el combinations shown on the schemaf'ic is conneqted asa,term,ina•.

, tion;load; to a single X or Y .. winding of the- m.emory cor~bank

... '1...-/

,The other en.d Of})1~ip,arallel

combination Is connected to one of the 197.2,read/wr,ite switch outputs o The relativ,~Ly
high impedance of this load (compared to the impedance of the core winding) helps to ensure
"

a c()l1sf'ant core drive current regardless of the~agnetization states ~f the cores thr~aded by
\"

~"!

a si,ngle winding.,

f "'RESISTOR BOARD '1978 -ihf~:rnbdule;'con'tains eight 50-ohm, 3c:owatt resi'stors V;ith
1/20/0 tolerance

For use in the PDP-4 memory, onl y six of these eight resistors are used

. (resistorsMT and,NS,:are,not 'used)

The six resistgJs that are,;u'sed have a, cppacitor and

resistor added .in pqraHel,with ,eac;hof theorigina I 50-ohm, resistors.

Th is capacitor and

resistor are connected in series; they are shown by dotted lines on the ,scher:natic

The capac-

Itor is 4700 pf wHh3% "tolerance . The series resistor is.,47 ohms with 1% toleranc;:e

;

Each 'of these parallel combinations is connected to -3'vdc (at terminal P) by 220-ohm 1%
resistor

A 39 I-'f capacitor fI C9 If provides an ac shunt to ground

~s connected as a

Each of these circuits

t'ermanation load to a single inhibit winding of the memory core banko

The other end of the pc;1rqUel Gombination is connected to the Gorresponding Inhibit driver.

INHIBIT DRIVER 1982 - Each PDP-4 memorycontains 18 identical inhibit drivers.

Each

of these inhibit drivers is a switch with an AND-gate input, which controls the application
of current to the inhibit winding of a single memory core plane

Four inhibit drivers are

included in each 1982 plug-in moduleo The following description refers to inhibit driver #1
(with gate inputs E and F), but applies equally to the other three drivers in the module.
The inhibit driver is similar to the type 1972 read/write switch (.!:. above) except that it controls a unidirectional inhibit current only, rather than read and write currents of opposite
polarity.
When -3 vdc is present at either gate input, the circuit acts as an open switch, preventing
the flow of inhibit currenL However; when both the E and F gate inputs are grounded, the
switch is enabled, permitting core driver current to flow through the associated memory
inhibit winding

The inhibit current then flows between the terminal V inhibit supply and

output #1 (W).

If one or both of the gate inputs is aot -3 vdc g the D3-D4 AND gate causes grounded-emitter
transistor Q2 to saturate. The comparatively small size of resistor R2 provides fast turn-on.
For fast turn-off, germanium diode D7 limits the excursion of Q2 into saturation.
When Q2 is conducting, its collector is at about -1 vdc. This voltage is direct-coupled to
the base of Q4, holding Q4 off. This opens the forward-bias current path between the base
of Q6 and -35 vdc u cutting off Q6. Diode D10 furnishes reverse bias current to Q6. With
Q6 cut off, the current path between V and W is interrupted, and the inhibit driver furnishes
no inhibit current.
The inhibit driver is enabled by grounding both the E and F gate inputs. This causes the
D3-D4 AND gate to cut off Q2. The collector of Q2 is then driven more negative by R6.
Furthermore, R6 supplies turn-on current to Q4, and the emitter current of Q4 saturates Q6.
With Q6 saturated u the current path between V and W is completed, so that the driver can
furnish inhibit current to the inhibit windingo

10-8

DELAY CIRCUITS

The four modules described in this section provide adjustable delays for standard DEC negative
pulses. Two of these four units (the 1310 and 1311) are high speed 5 mc circuits. These two

10-38

unlit's are used to delay 70~'nanosecond pulses
are !ow speed 500 kc cnrcuUts

The other two delay units (the 4301 and 4303)

These units are used to delay Oo4-microsecond pulses

The 1310 and 13~ 'ij unHs generate comparativel y short delays by means of delay lines

The

430~ and 4303 deiays generate longer delay times by means of monostable mulHvibrators

DELAY 1310 = This module contains a delay line which provides up to 1 mucrosecond

de~ay in 50-'nanosecond stepsl7 and an Inverter driven by the delay line outpuL

The inverter

output can drive an external pulse amplifier (such as the type 1607, paragraph 10-6~) 0
The inverter t'ermnnais are brought to the external connector of the module, so they are
avalliable for !og~car gat,'ung

To tdgger the de!ayt' a st,'andard DEC 70-nanosecond negative pulse is applied to termonal

X 0 After a predet'ermnned delay, dependent on the external connections made among
t'ermiinais J t'hrough W t' the inverter output at E is temporarily grounded, ind~caHng the end

of the delay ~ntervall 0
The ~nverter adds 20 nanoseconds to the delay of the line 0 The line delays described below
do not include this 20'~nanosecond inverter delayo
Two jumpers are usually used to determine the delay; one for coarse adjustment, the other
for Hneo The coarse range of the delay is selected by one of the following iumper connec-

}umpered Terminals

U to N

V t'o P

,,0

0 0
0

Delay Range
.0

00000 0

0 0 0 0 0 0 0 000 0 00' 0 0
0

0 - 0

mi c roseconds

0 0 0 0 0 0 002 - 004 microseconds
0

V to R

004 - 006 microseconds

W *'0 S

006 -,008 microseconds

W ~'o T

008 - 1.0microseconds

WHh\ln a coarse de!ay range, there are available five graduated delays separated by

iincrement'S of' 0005 mncroseconds 0 The fine delay wHhin a given coarse range is selected
by one of the foUow:ing jumper connections

10-39

Jumper Term~na!s

H to N

u 0

•

Delay = Lqw End of Range Plus:
0

o. p 0

No th un9

H to M 0000000000000000000000000000000 0005 m~croseconds

H to L 0000000000.0000000000000000000000010 microseconds
H to K o. 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0
0

H to J 0 0 0'0 00 0 00

o·

0 0 0 00 00
g.

0 0 0 015 microseconds
0

0 0 00 0 0 2 00 mi c rosec on ds

For example~ To produce a delay of exactly 0095 microseconds, jumper Wand T, and H
. ,....

and K ·(008 + 0015.= 0095)

. -When the circuit iSHn the qunescent st'ate.'l resistor R1 furnishes the cut-off current which
holds transistor Q1 off 0 Termonatong res8stors R2 and R3 prevent signal reflections from the
ends of the delay line 0 By attenuatnng the short,-delay output signals, R4 and R5 compensate
for the attenuation of long-delay signals traversing a greater length of line 0 Diode Dl isolates the input from reflections caused by a mlismatch at the output tap 0
b

DELAY 1311 -, Thus module cont'aHns two identr:cal delay lineso The following descrip-

tion refers to the delay contannftng transBstor Ql, but applies equally to the other delay on
the module

The 1311 delay operates on a similar manner to delay 1310 (s: above) except that the delay
!ntervalsavaHiable are I imited to the lowest range of the 1310 delay 0 A delay of 200 nanoseconds (not including the addiHonal 20-'nanosecond delay introduced by the inverter) is
available on 50-nanosecond steps.
To trigger the delay, a standard DEC 70-nanosecond negative pulse is applied to terminal E.
After a predetermHned delay dependent upon the external connection made between F and H,
J, K or L, the inverter oUJtpu'~' at N ~s temporarily grounded, thus indicating the end of the
delay interval

The delays produced by each connection are as follows:
{connections Dn parentheses refer to the second unit}
Jumpered _TermB~~~

.Delay

F to L (5 to W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • 0 0 0 0 0 0 0 50 nanoseconds
0

F to K (S to V)

100 nanoseconds

F to J (5 to U)

150 nanoseconds

F to H (5 to T)

••

0 00 0 00 0
0

•

0 00 00 00

200 nanoseconds

DELAY 4301 - This module contains an input pulse gate, a monostable mvltivibrator,

an output level ampl ifier, and an output pulse ampl ifier. The pulse gate transistor is Ql;
Q2 and Q3 are the multivibrator transistors; Q4 is the level amplifier transistor; and QS is
the pulse ampl !fier transistor.

Diodes D10 through D13 provide a -3 vdc suppl y

Whenever input Vis enabled by a ground level at Z, and triggered by a DEC Oo4-microsecond negative pulse i another Oo4-microsecond pulse is generated at pulse output E or F
after a predetermined adjustable delay

If E is grounded, a positive pulse is generated at

However" if F is grounded, a negative pulse is generated at E.

In addition to its pulse output, the 4301 delay circuit ~Iso has a level output cit J

This

output, which is normally at ground, falls to -3 vdc during the de,layo An alternate method
of triggering the delay is to ground input X through the collector of an external pulse gate
sn'milar to Ql

'Using only internal components, the delay may be varied from 2 oS microseconds to 200 mill iseconds in S ranges. With U jumpered to T, potentiometer R7 varies the delay within each
range. Range selection is determined by jumpering H to one of the terminals L, N, Mu P
or Ril thereby connecting capacitor C4, CS, C6, C7 or C8 into the multivibrotor circuit,.
The delay range with onl y C4 in the circuit is 2.S microseconds to 25 microseconds

Connecting each higher valued capacitor in turn raises the delay range by approximately
a fa c to r 0 flO .
C~rcuit recovery time is 20% of the maximum delay in each range.

The conhection between

Hand L is wired internally. If external control of the delay is desired, a potentiometer
may be connected between pins Sand T. Higher ranges may be added to the delay by
connecting an additional capacitor between pins L ond K

Current from the base of Q2 flows through R6 and the parallel combination R7-R8. This
current holds Q2ono With the collector of Q2 close to ground, voltage divider R4-R9 holds
Q30fL The collector of Q3 is then held at about -6 vdc by voltage divider R13-R14o
There is no vol tage across the primary of transformer T2, and no vol tage appears across
the secondary

Current through R13 and R14 saturates Q4. Consequently level output J is at ground. The
base of Q5 is grounded through the secondary of T20 Th is ground holds Q5 off. The output

10-41

pulse amplifier remains In its quiescent state

There, is no pulse output across E and F

The 4301 delay is triggered in the following manner. A-2 oS-volt, Oo4-microsecond pulse
is appl ied through Y to the base of Q1 0 If the emitter ofQl is gtdunded at Z, enabling the
input gate, the transflstor saturat'es t7 grounding its collector 0
Terminal 2' of the T1 pdmary then becomes posHive with respect to terminal 1, and an increasing current flows through the primary

(Capacitor C2 bypasses the primary to prevent

input noise from spuriously tdggedng the cBtcuuL) The increasing current in the primary
produces a negative voltage at secondary terminal 40
voltage to the base of Q3; thereby turnRng Q3 on

Diode Dl couples this negative

The collector of Q3 then applies a ground through diode D7 to the junction of R13 and R140
This cuts off Q40 Output J t'hen drops to -3 vdc, indicating the beginning of the delay intervalo
The ground at the collector of Q3 ils applied through diodes D5 and D6, resistor Rl0, and
the H to K 'capacHance to the base of Q20 Thus ground immediately cuts off Q2, causing
its collector vol tage to drop 0 Resist'or R4 then draws base current from Q3, holding Q3
on even after the end of the pulse from termina I 4 of transformer T1 0
The monostable muitHvibrator made up of Q2 and Q3 remains in this state (Q2 off and Q3
on) for the time interval requnred to charge the capacitance in the Q2 base clrcuiL The
RC time constant whnch determunes thus interval depends upon the capacitors in use, and
the resistance of R6 Hn series wHh the paraHel combination of R8 and potentiometer R70
When the time delay capacitors have charged to a sufficiently negative voltage, Q2 turns
on

The resul Hng rise in the coH ector vol tage of Q2 is coupled through R4 and C3 to the

base of Q30 This cuts off Q30 The current in the primary of T2 then falls to it's quiescent
level

The resulting negat'ive pulse'in the T2 secondary is applied to the base of Q5, turn-

ing Q5 on

The pulse ampl iHer composed of Q5 and transformer T3 then generates a standard Oo4-microsecond DEC pulse across outputs E and F

Operation of the pulse ampl Hier circuit is explain~

ed in the descdption of module 4605 (paragraph 10-6~ 0
Since g when Q3 I'urns off" the voltage af' 'fhe base of Q4 is determined by voltage divider

10-42

R13-R14, transistor Q4 then turns on.. OutputJ therefore returns to ground,indicating
the end of the delay
d

INTEGRATING ONE-SHOT 4303 - This module contains two monostable multivibrators,

two difference ampl ifiers (sl icers), three inverters, apos.itivecapacitor-diode gate and a
negative de supply

These components form a single circuiL The type 4303 has flip-flop

type logic level outputs

When the circuit is in the 1,.state, the 1 output is asserted at

-3 vdc, a nd the 0 0 utput f>r6x{~%"';i&6p'i!~~el .1 n 'th~ 0 sta te, the 0 ou tput is asserted at
~3 vdc, and the 1 output provides a ground level.

When an input (there are three) is pulsed g

the circuit assumes the 1 state, having previously been in the 0 state.. The circuit returns
. to the 0 state after a selected delay, which begins with the termination of the input ~ignal 0
The two mul tivibrators incl ude transistors Q2-Q3 and Ql0-Qll respectivel y

Transistors

05-Q6 form one sl icer, Q7-Q8 make up the otheL The three inverter transistors are Ql,
Q4 and Q90 Capacitor Cl, resistor R1, and diode D1 compose the positive capacitor-diode
.

gate

Th'e negative dc supply contains diodes D9 through D16 and resistor R28. Vol toge

I~v~fs of -0.75 vdc g -1.5 vdc, -3 vdc, -4.5 vdc,., -5.25 vdc, and -6 vdc are tapped from
the supply at the cathodes of D16, D15, D13, Dll, Dl0 and D9 respectively.
Three inputs are provided at terminals K, Sand R. The signal input at K may be either a
DEC standard 0.4-microsecond negative pulse or a negative level.. The input at S is a
DEC standard Oo4-microsecond positive pulse or positive-going level change; this pulse is
gated through to the base of Q2 by a ground level at T.. Input R requires a positive pulse
such as the output of a positive capacitor-diode gate similar to Cl-R1-D1

The 1 and 0

outputs are Wand U, respectively.
The delay is variable from 3.4 microseconds to 0.9 seconds in five overlapping ranges.
Connection of one of 'five internal! y contained capacitors into the circuit determines the
delay range

Capacitor C7 is connected internally to give the shortest delay range

Con-

necting capacitor C6, C8, C9 or' Cl0 (E, F, H or J, respectively) to ground (D) increases
the range by successive factors of approximatel y 10.. Potentiometer Rl0 determines the delay
within each range if Y is jumpered to X

Alternatively, the delay may be determined by

, an external potentiometer connected between Z and X

10-43

In the quiescent state, Ql, Q3, Q4, Q5, Q8, Q9 and Ql0 are off. Transistors Q2, Q6,
Q7 and Ql1 are on. Voltage divider R2-R3shiffs the ground level at input K positive,
biasing Ql off. Multivibrator Q2-Q3 is in its stable state with Q2 held on by base current
flowing through:R5, and Q3 held off by ,voltage divider R8-R9. With the collector of Q2
at ground, voltage divider R~ l-R12 biases Q4 off.
In slicer Q5-Q6, transistor Q5 is off and Q6 h condy.cting .. Diode D6 clamps the collector
of Q6 at -0.75 vol ts, hoi ding Q6 out of saturation. ,The. common, emitter connection of

NP'N ·transist~rs Q5 andQ6 follows the vol tage (-1 .5 vol ts) at the base of Q6. Consequent.'Iy Q5 is cut off.
. .' ,

The other slicer transistors,Q7a~d_ Qa, are on and off r respectively. The series combination of potentiometer Rio, ~an'd resisto'rs' R13 and R14 draws sufficient current from the base
orQ7 to's'aturate that transis~tor, even if the potention\et~r is set at its maximum resistance.
The saturation ofQ7hoids the common emitter connection ofQ7 and Q8 at -~ .25 volts,
the collector voltage'of Q7. The more.positive voltage (-4.5 volts) at the base of Q8
holds' Q8 at cut-off. WithQ8 cut. off j, Q9, is ba~k-biased thr~ugh R19 so .C?9 is cut off,
also. Since Q9 is cut off, the voltage diviper composed of R23 cmd the parallel combination
of R21 and R24hol'ds" Ql0 off. Consequently" multivibrator Q10-Qll is i!1 its stable state,
with Ql0 off and Qll o,n.
The circuit is triggered from the ,quiesc~nt sto'te when anappropriate input at K, R or S
drives the base of Q2 positive. Multiv.iqratorQ2-q3.flips to the temporary stat,e with
Q2 off and Q30n. Diode.D4 cl'amp$ the,collec,to~ voltage of Q2 at -3 volts. Rl1 and
C5 couple this-3 volt ,tevel to,the base of Q4, s9turating Q4. The saturation of Q4
grounds its coli ector.
The grounded collector of Q2 drives the bases of Q5 and Q7 positive. The signal divides
at the two bases j'n order to perform twoJunctions. " The s,ignal at the base of Q7 goes to
output multivibrator Q10-Qll, driving this multivibrator to its temporary state. The base
of Q5 forms part of'the feedba'ck loop that returr,ls the signal to input multivibrator Q2-Q3,
returning this multivibrator to its quiescent, or,stable, state.
,

As the base of Q7 goes positive, Q7 turns off and Q8 turns on. ;The common emitter connection of the two transistors rises to the base' vol tage of Q8. Transistor Q8 turns on but

10-44

'does not saturate because the rising cell ecter veltage ef Q8 is clamped at -5025 vel t's by
the turn-en ef Q90 'Transister Q9 dees saturate, and its cellecter vel tage dreps to' -5025
ve!t'so Resister R20 couples this veltage to' the base ef Ql0, turning Ql0 eno Multivibrat'er
Q10-Ql1 flips to the t'emperary state, with Ql0 en and Qll efL The eutputis now in the
'j

stateii' with W at -3 volts? and U at greund 0

in the feedback leep to input multivibrater Q2-Q3, R14 drives C7 (and any ether capacitor
that may be in paraHe'l with it) tewardgreund 0 This is the charge mede 0 When this veltage
reaches -1 05 veltsli' Q5 begins to cenduct, raising the cemmen emitter veltage ef Q5 and
Q60 CensequentlY!1 Q6 is cut efL the cellecter veltage ef Q6 gees pesitive, ferward,~
b~'as!ng D5 and cutting eff Q30 ' Transistor Q2 turns en,

previded that it is net held eff by

a centinuing negative level at 'K 0
The tUrn-en ef Q2 greundsthe base ef Q4, cutting Q4 eff, and beginning the discharge
, mede 0 Befere .the cellecter ef Q6 can return to' its quiescent state, C7 (and any additienal
capaciter which is in parallel with C7) must discharge, threugh resister R13 and petenf'lemeter R10, to' a veltage mere negative than -1 05 velts 0 At this peint Q6 turns en and D5
becemes back~biased,f discennecting R16 and R17 frem the base circuit ef Q3oHowever,
the greunded cell ecter ef Q2 centinues to' hO'I d Q3 eff

When the base veltage ef Q7 becemes mere negative than -405 velts, Q7 turns en and Q8
turns efLThe ,-6 velts frem the negative supply back-biases 09 threugh R19, turning
QgefL The dse in veltage at the cellecter ef 09 cuts eff Ql0, returning the eutput
mul tivibrater to' it's stable state 0 The eutputs at Wand U return to' the 0 state (W at greund
and U at ,=,3 veltsL indicating the end ef the delayo
if the Rnput to' Q1 is held at -3 vdc, capaciter C7 charges up to' greund and stays there 0
Thus the eutput remains in the l' state

The eutput returns to' the 0 state after a fixed in-

terva! fellewing the remeval ef the negative 01 input
~ntervals than the delay peried,f

When input pulses arrive af' sherter

the eutput similarly remains in the 1 state, returning to'

the 0 state after a fixed interval fellewing the last pulse 0

10~9

PULSE C~RCU~TS

Three medules£, cleek 4401, crystal cleek 4407 and pulse generater 4410 are described in this

10~45

section 0 All three modules produce standard DEC 0 .4-microsecond pulses, either positive
or negative 0
The type 4401 and 4407 clocks produce a continuous train of pulses at predetermined frequencies, and serve as timing devices in the PDP-4 equipment.

Pulse generator 4410 utilizes a

Schmitt trigger to generate an output pulse when ever its input is triggered 0 The input may be
triggered even by slow, and perhaps irregularl y changing vol tages.

Th is feature makes the

4410 pulsegeneratoruseful in converting sine waves and mechanical switch closures to pulses.
a

CLOCK 4401 - This module consists of an astable multivibrator, a pulse amplifier-

shaper, and an output pulse ampl ifier.

The mul tivibrator incl udes transistors Q1 and Q2;

the pulse shaper transistor is Q3 and the output pulse ampl ifier transistor is Q4.

The type

4401 clock generates standard DEC 0.4 microsecond pulses across output terminals E and F
at any frequency from 5 cycles--to 500 kc per second

The interval from 5 cycles to 500 kc

'is divided into 5 overlapping ranges; within each range the output frequency is continuously
adjustable 0 The output pulse train may be inhibited by applying -3 vdc to V through a diode
whose anode is connected to V.
Potentiometer R4 adjusts the frequency with in each range.

The range is determined by the

amount of capacitance between pins T and V. An external jumper connects one of five
capacitors contained in the module into the circuit for this purpose.

The frequency range

for each of these connections is as follows:
Connection

Frequency Range

T to Moo 0 0 0 0 0 0 000 000 000 0 0 000 00 .. 00 •. 5 cycles to 50 cycles
0

T to R •

•••

0 . 0 . 0 .••• 0 0 0 . 0 0 0 . 0 0 0 . 0 0 0 0 50 c yc I es to 500 c yc I es
0

T to P .000 ... 00.0 .• 0000. 0
0

T to N ...
T to U o.

•

0 0 0 •. 0 0 . 0
0 ..

••

•

0.0 .... 00500 cycles to 5000 cycles
•

0
0

00 0
0

5 kc to 50 kc
50 kc to 500 kc

Diodes Dl through D6 determine the operating vol tages of the mul tivibrator. These are
silicon diodes with a voltage drop of approximately 0.75 volts each. Because they maintain this voltage drop across a wide range of current flow, multivibrator operation is stable
and comparatively independent of the -15 vdc supply.

Diodes D1 through D6 hold the base

of Ql at -2025 vdc and fix the Q1 and Q2 collector supply at -3.75 vdc.

10-46

Multivibrator feedback is obta:ined~byconriec'ting-P::fo,otie'o.f M~ R, P, Nor U, and jump-'
ering X and Y. An alternative arrangement, which extends the multivibrator frequency
range, is to connect an external capacitor between V and T.

External fine control may be

provided by connecting an external potentiometer between Y and Z.
Because the fine control, potentiometex R4 varies the operating; point of Q1 over a wide range!
a dual collector load is provided fO.r Q1 ", For low operating current resistor R3 is the principal load, and the Q1 gain is sufficient to maintain oscillation. For high operating current,
the principal load is through R2, and Q1 is not driven into saturation.
Mul tivibrator transistors Q1 and Q2 a I ternate on and off at ,a rate that is a function of the
RC time constant of the range-determining capacitor (one of C3 through C7) and the series

combinatio~ of resistor R1 and potentiometer R4. An output pulse is generated during each
cycle of the mul tivibrator when Q2 turns off.
Assume that at a given moment Q1 is turning off and Q2 is turning on. The emitter vol tage
of Q2 follows the negative-going voltage at the collector of Q1. Capacitor C3 (if T is
jumpered to M) couples the negative transient to the emitter of Q1"

The feedback from the

Ql collector to its emitter rapidly triggers the multivibrator to the astable state with' Q1
off and Q2 on. The secondary of T1 generates a positive pulse at the base of Q3. However, th is pulse- only drives Q3 further into cutoff, and the output pul se ampl ifi er is not
affected.
The multivibrator remains stable in this state while C3' charges through R1 and R4.

The Q1

emitter vol tage rises exponential! y towards ground. When the emitter vol tage becomes more
-

positive than the -2.25 vol ts at the base, the transistor begins to turn on. The Q1 collector-emitter feedback triggers the multivibrator to the other state (Q1 on and Q2 off). The
multivibrator remains ,in that state while C3 charges through R5.

Note that if terminal V

is held at -3 vdc, Q1 cannot turn on. ,The mul tivibrator remains stable with Q1 off and
Q2 onunti I the -3 volts is removed.
At the turn-off of Q2, the collapse of current in the primary of transformer T1 causes a
negative pulse to be generated at terminal 3 of the T1 secondary. This negative pulse
saturates Q3, grounding terminal 2 of the T2 primary. The output pulse amplifier, composed of Q4, T2 and T3 generates a standard DEC 0~4-microsecond pulse across E and F

10-47 '

:. Operation of the, pulse amplifier is explained .in th,~ qtlsc;ri,ption,Qf module 4603 (paragraph

10-6.=) .
'1 ~ ( .

CRYSTAL CLOCK4407
- This module
contains a crystal oscillator, an osc:illator out":,', i
f'·...· .r:
. , .'
',.~

j',

~., l '. ..

. :..'

" .

put amplifier, a Schmitt trigger circuit, and an output pulse amplifier. The crystal oscill"

; :",

r",

':"

',. "

',',

ator includes tra'n'slstors'Qr, Q2 and' Q3'; transistor Q4'isthe 6scilla'tor a'mpli'fier. The
Transisto'r Q7 is' pa'rt of th~outpu't pu-rs~ dmprifier 0

Schmitt ci rcuitinchJdesQ5 'ahd Q6.
fI"'" ,'.,

• \.

•

The 4407 moduleg~n~rates DEC standard 0 o4-microsecond pulses, either positive or nega~'
I

•

t. ; I ~ .

:~ \' .J

'.'

. ~. .

•.

~ !

,.'

tive, at a frequency determined by the series resonance of the oscillator crystal.
i'cl6ck'4407 has ci cry~t~1 with a series reson~:nce of 9.6

In PDP-4,

kc. ",

i,:.Termr~~I'r~is t~,~ ,n~g;~tiye ~<?u,tput, ,~nd F,is the,gositive, oytpuL, ,If Fis ijumpere~. ~o ground,

E produces a 9.6 kc train of negative p~lse~:. CQnver~:ely, if E is grounded, F 'pro~uces
a 9.6 kc train of positive pulses

,.~. ~.,.

,.; Positive
feedback from the '\collector
to the
emitter
of Q1:. . sustains oscillatio~s).o
the crystal
'.'
. ' '..,- .
.
1 ..
'. ~.
; . ~ ;"
, ~. :,
oscillator.. The feedbac~ path gqes,from the coll~ctor of Q1 through crystal CR-1, the two
,

". "

".j

:,;.

'; '.' ~

'f'

, .

~ ~',

.!'"

, ~~itt~r followers 02 ~md Q~,~ to the emitter ~f Q1, ~, The asci Ilator output i;s, t~keJl from the
coil ector of Q30

The ci'rcuit oscillates (unity ..ga'in around: the feedback loop)qt that frequency such ,that the
highest proportion of signal voltage is fed back to the emitter of Q1. Crystal CR ... 1 has
minimum
resistance
at .....seri~s resonqnce. Thus the positive feedback i's maximum at the series.
.. '
l~

resonant.frequency
of CR-1
,

' .

,Gain ar()und ,the. feedback ; loop is. less than unityfor other
.
.,'

. .

Osc::illa,tiory i,s th.er~fore systained on.lY at the series-resonant frequency of
~,'

..}.

CR-1, ie 9.6 kilocycles.
'j

0,;

frequencies.

- : : " " ..

;

j ,

....

'-'1",;.-,

The parallel res6nanY:drcuit ,Cl:C4':'"ll~is 'tuned in the vicinity of 9.6 kc. ' The increased
impedance of this :tuhed:circuit at resonance .comperlsate~for the loss of Q1 collector load
impedance at the series resonance of crystal CR;...l ~

This compensation near resonance helps

to stabilize, the gain of Q1 J ; ~n~ assIsts in tuninQ ,the oscillator to th~ desired frequency.
Zener diodes. 01 and,[)2makethe'"operating volta~,es,of the oscillator circuit independent
,

" o~ supply va ria tic:ms .,

',"

The osciHatoroutput<to the base ofQ4· is amplified at the Q4collector and applied to the

10-48

ba'se of Q5. The Schmitt circuit, Q5 and 06, converts the 9.6 kc sine wave into a 9.6 kc
square wave. The output pulse amplifier, Q7, then converts the square wave into a 9.6 kc
train of DEC standard 0 .4-microsecond pulses.
The Schmitt circuit and output pulse amplifier are similar to the circuit contained in module
4410 (,:. below). Each time the sinusoidal output from the Q4 collector drives the QS base
more negative than -2 vol ts, Q5 turns on and Q6 turns off. The turn off of Q6 generates
a pulse at outputs E-F. Since Q6 turns off and on once for each cycle of the oscillator,
the pulses are produced at the oscillator frequency.
c

PULSE GENERATOR 4410 - This module contains a Schmitt trigger circuit, an output

pulse amplifier, and an RC filter.

The Schmitt circuit includes transistors Q1 and Q2; the

pulse amplifier transistor is Q3; resist~rs Rl and R2 and capacitor C1 make up the filter.
Module 4410 generates a standard DEC 0.4-microsecond pulse whenever its input voltage
drops from a value more positive than -1 volt to a value more negative than -2.0 volts. If
no internal filtering is required, the input is applied to terminal S. However, if the internal
filter of the type 4410 is needed (for example, when the circuit is used in conjunction with
a mechanical switch), Sand U are jumpered and the input is applied to Z. The negative
trigger input to Z can then be derived by mechanically switching K to Z. The combination
of capacitor filtering and the hysteresis of the Schmitt circuit prevents all but the noisiest
contacts from generating more than one pulse per switch closure.
The output terminals of the 4410 are E and F. The output pulse may be either positive or
negative. Terminal E generates a negative pulse when F is connected to ground; F generates a positive pulse when E is grounded.
Assume that initially the input (at S or Z) is ground, Q1 is off and Q2 is on. The emitters
of Schmitt trigger transistors Q1 and Q2 are:held about 1.8 volts negative by the Q2 emitter follower action. The Q2 base voltage is determined by voltage divider RS-R7-R10 and
and R11. Diode 03 isolates the emitters of Ql and Q2 from the -1 .0 vol t level at the
junction of R14 and R1S. Diode 01 and resistor R4 couple the ground input level to the
base of Q1. Since this base is back-biased, Q1 is cut off.
The collector of Q2 is at -4 volts .• The current through the primary of transformer T1 is held
steady at about 10 ma, and no vol tage appears across the secondary. The base of Q3 is

he! d at ground:b>,y~the SeObndo rY'of; Tlp <;l:rn,g' Qa)s~/c.utqffp;: J~,:·,·QP;~OJ~~ct9r.·,)sqJ opproximately "'7-o5~voH:Sfand'there,js':no':outpyt\q'CrQ$sHltl~Hld; Eo !o(: tu;_{it.o ,:~,.<T . ~~.,i "

"JCV

To tdgger the circuit" a negative voltag~'isl:6P~ffe~(;td.11f~:e·l~p~\t:.~~'Sdh~1t?~f?gger h,dhSIS,

torCH begins to (conrdv-ct o.s·s'Oclm~QS' lh: l:xIs~ ;beCQmJ~~tmef~t;legqfJ,'te.! tD9·n .Hf:~~itte~:.o '''~'Th is

occursnwhen' the·lnpubfal t$j beJbW!~-aloout ~2.;o05t4>ltS'c( ~Wh~~~Q:l;. stqrts t9( cOQduct~~;~!.col ~

"Re'~i~t'~r ~t a~d ~~"pb'cfto~ "C~f'c6dpie the~'rfs{gg 2Ibn'~c:t;r vbl f6geO'f' Ql,:td' the"haskbf Q2,
I

Turn'-'off 6f'Q2t.~a;ker:1H~ ib:brilmdl1 t'mi~Her':tohhecti6'rf6f :Ql!'iand

thereby cutting off Q20

; ,92Jl1or~ pos;iHY:7!,~~;e~~9!!~%,;~h7 tXf~,T.~,?-j o..f j

;9,\ o~; ~f~ pO,~i:tiv~J/:~~~~'~ 3~~\ tP~?lf~~,hmitt

td~g.~r ch:cL!~t a~s~~r~c~ a .fa.~f'.,<?n~PQ~.~f ~Jo,!~J., jnd7pendent.qJ .the fall time.,qf the input' signal

,. . .,.,r.

,.,', • .·L",l

't'

.' .....'/;'"

,1/

;.,~L

•

.'/;;J

i:·.-· ,-.;;'

........

<;j:~;T:: .•:':'iUL:

,'c

;WHhfhe turn~()ff 6f Q2~,.,t.he<clrrren·hthroughi the'; pr.Imaf} ''''of tron~forrn.er .

.rJ 'coUo~~,Jqin-

·A~C,"?g.q nega,F'(~;p,u,!~~e. at~ter~,~,~~r;!'~1~i?-r t~~. 'bl':E1\~.o,n.~~t~l ~i' ~is, ~el9.ati.~e.;~~!se r~~{,~.,~fl Hied
~

by pulse ampl Hiet Q3. and appears across outPlJts E and Fo" The pulse ampl iHer .shapes the
'-:",.

",<

'.'1

, )

~t~,;.

.•

.:\J

~~..

(',',

i'"

·f:.;L~~

•

'.- ' . ':':?~'><";

·'"F',::.

·1.;

•.. '::

.,' . ,output pulse to 205 vol t's .in amp! i.tuo~ and 0.04 microsecon9 in duration

~,:.:

~..

.,},':

,,::

; ":~~"j.

~-·tr..l"~··

;"""'!.;1'!,'

l'~-~'

.,,··,·.~.~/~'··

,<J

r·:_~·."f! ;?,(1(~:;:

The polarHy of the

~~.:·:-: .. ~;~:;~·tr,'! (n~~

,.'

pulse depends 9n whe'ther E is 9~ounged (for a positi,ye pulse) ~r F, i~ grounde,d{for a nega~
.~

;

".!

,Hve pul,se}

•..

•

{

•

:l).;~~

;

;-'~t:J'

;1" j !:

\':'

:~n~:":"".···;

~~;" . .- :) ·';~.·:-.~A .. ·~!".

',)iJ~':~

I:' ,,'

~)~'l ~\

.. "~'

i;'; ~'.~" 'j-:;~tlr1'

" ' / ' , ; :..::' iC'; ..

, When th~, QJ·base :il:Jput'ugoin\!~',isesJowarcds grpund",tne.Ql, e~!tter (oJlO\Al~- this y~l~qge un-

.' HI. th~' base!fts at appr.o?<Hncrtely··-,l yoh ~i·At·this;point,; D3 again .start~ to ,cRnd,:,<:=.t:,g ',clamping the emitter voltage"ci'/ Furthetirise;pf th~t'i.nput W~I,t:qge.cuts:qff: Q1o,) As ~h~ J~)ii8Qllector :go~s ,~egat~.v~!; lP~i~,,'i~;1 ~a:g~.' •. dr?p.t~ c~up~e~ .th~~~~,h. R7 ~.n? .~2 to. the ,~:s~ ?~" ~~.J;. turn'~
ing, Q2 back qn,,? 9~d 1:he,reby returning the tr:i.gger circuit to the initial stateo
•.•..

;

'.:'

•

~";'

' ...

::;-:.

e 'l..' £;(.,:.~ ..

,:\·i::'.~:'

,::~: ~.,.~";,,~ '.~

:w:", .,'~

t:..:"

Th~s re-

-'.j

establishes current through the primary of Tl f! and indu~~~ a p~sitiye pulse at terminal 3 of
'''U:~J'"~~

the T1 secondary

-..

.,...

"~''',''

This posHRve pulse, however I onl y drives Q3 further into cutoff and the

fi ~r i~ unaft~tted'~:;'Dfode:'D2and' cresi'stcsli R9: prev'ent ri ~girlg :, n'Tro

output pul se amp! D

; .

"<.

t," -

: It.

~~\,

:~"~

...

~',,'

<:."

','i- r,'

;':!',

f.'.

,; !f

':'::)(,

rheset~9 plug.a9~.pt~L~. <:lr.e.pl~g'='Hn unJts thathove aJO~pinplug at the module back panel
,

'.',...."

'':'.' , ,.

; :".'

~" . . .

;;.,.l~. . . ;r~.'

. . _;

C. . . ' •. ' ;

•

,:.

> ':- ,"'/',j,':i'r'.

{only nnne pins are usedL, In addViC?fl ..tofhe standard 227'Pin pluglo,cated_at th~ front panel
,.

.. '

:,~

,',.-11

,'1\.

. ~,.,~.

.".' - ~,}

'~.~ . .

,.',:""'~

':;;" i.-o

;i(.;

. <:.1:,~:, . . . 1

~nternal widng connec~'S each pon of the back panel plug to a pin of the front panel plug

. Bot-h' 'types of ~dapters cire ;0s~d\o;b~i'~~' th~'}gar phJg to:~rr~ctlohs ~rthe:420j:rFrp'-fiopr!to the
,.

'.'

,10-50

i,"

front of the mounting panel.
I

The PD P-4 includ~s only three adapters. A single 1956 adapter couples the rear plug of the
Iink fl ip-flop (type 4203) to the front of the mounting panel. Two 1956R adapters couple the
accumulator rear plugs (also 4203 flip-flops) to the front.

One 1956R adapter is located at

each end of the accumulator, and parallel bus connections are made between the rear plugs
of the adapters and the register fl ip-flops.
The 1956R adapter differs from the 1956 adapter in that eight of the nine internal jumpers be"tween the back and front panel plugs are grounded through resistors. These resistors serve as
terminating resistances for pulsed lines. All the resistors are 100 ohms, except the two that
connect lines C*-L and E*-R to ground. These two resistors are 47 ohms. The connection
between D* and N carries levels, not pulses, so it requires no terminating resistor.

10-11

POWER SU PPLIES AND CONTROLS

The PDP-4 power suppl ies convert standard 110 vac to dc power at the appropriate voltages for
the computer circuits. The supplies include type 728, 734 and 735.

Power supply control

type 1701 and the type 735 supply are functionally a single supply unit.

Power control 813

controls the appl ication of power to the computer.
a

POWER SUPPLY 728 - This unit suppl ies the +10 vdc and -15 vdc power required by

most of the PDP-4 modules

Two type 728 suppl ies, with their -15 vdc outputs connected

in series, fur!:lish -30 vdc for the 4681 solenoid drivers.
The outputs of the 728 supply are +10 vdc (0 to 7.5 amperes), or -15 vdc (1 to 8.5 amperes)

When both outputs are used concurrently, the current lim itations are more strin-

genL All three of the following limitations then apply:
(1) +10 vdc limited to between 0 and 7.0 amps
(2) --15 vdc limited to between 1 and 8.0 amps

(3) Both outputs limited by the relationship:
51(+10) + 61(_15).:5 53
The +10 volt output is regulated between-+S'.5 vd::: and +11 vdc; the -15 volt output is regulated between -14.5 vdc and -16 vdc. Assuming line voltage variation from 105 to

")0-51

125 vac, this regulation holds from minimum to maximum load" Output ripple is less than
350 mill i vo Its

The line vo Itage is stepped down to 10-0-10 vac and' 15-0-15 vac by transformer T 1

Diodes D2 and D3are connected to the 10 volt secondary taps as a positive full-wave
rectifieL Capacito~s C2'and.o4 filter out the Oc component of the output. Resistor Rl,
in parallel with the 10 volt load, 'keeps the output within regulation tolerances even
though the external load is decreased to the no-load condition.
Diodes D 1 and D4 are connected to the -15 volt secondary taps of T1, as a negative fullwave rectifier. "Capacitors Cl i ,C3, C5and C6 filter out the ac componenL
Spe.cial properties of transformerr~ make possible the simple design of the power supply.
T1 is a saturated-core transformer which provides inherent overload protection
with shorted Qutputs g 'only a limited output current can be drawn.

Even

This self-Inmiting

secondary current eliminates the need for series impedance elements at the,filter inputs.'
The dc output impedance of the supply is thus kept low, rendering regulating devices
unnecessary.

The recHfier diodes are oriented so that the de output of the bridge at the junction of D2
and D4 is positive with respectt'othe junction of D'l and D3.

Paralle! capacitor Cl filters

the output. Voltage regulation is improved for small load currents byparallel resistor Rl.
A slow-blow 5-ampere fuse at the positive output protects the supply against overload.
The dc output vol tage is indicated on a 0-30 vdc meter across the output

POWER SUPPLY 735 - This supply provides power to the PDP-4 memory logic

input voltage requirement is a nominal 110 vac

The

Outputs are ...:3 vdc (terminal B), -13 to

-16-1/2 vdc (C and [)~, and -35 vdc (E). A +10 vdc level is generated for use by the
internal shunt regulator circuits, and for use by power control 1701. Terminals C and B
are the inhibit voltage supply output; D and B are the read/write voltage supply outputs

Since the read/write and inhibit voltages must be well-regulated, compound connection
shunt regulator circuits are used across these outputs. The bases of shunt regulator transistors 01 and 03 are brought to terminals F and N (for connection to power control 170'0
rather than to their respective' output vol tage points. Besides regulating the output vol tages/l
the connection to the 1701 control serves two other functions.

The 1701 c·ircuitry varies the

output vol tage in accordance with the temperature of the core stack. Furthermore! the
1701 control permits adjusting the output vol tage to the individua I requirements of a
specific core stack.
The inhibit and read/write supplies are very much alike. They differ, however, in that the
inhibit supply output current varies over a wider range. Whereas the read/write supply
output current varies only from 0 to 0.4 amperes, the inhibit supply output must vary from

o to 3.0 amperes 0 Consequently, both the inhibit supply series dropping resistance (Rl,=R2)
and also the emitter resistor R4 of the principal shunting transistor Q4, are smaller than the
corresponding resistors in the read/write supply.
Transformer Tl steps down the 110 vac input to 10-0-10 vac, and to 35-0-35 vac

Diodes

D2 and D3 are connected as a positive full-wave rectifier to the 10 volt secondary taps 0
CapacHor C5 filters the dc output of the rectifier, which is then applied to the emitter
circuits of 01 and 03, and to terminal A of power control 1701. Diodes D1 and D4 are
connected to the 35 vac secondary terminals as a negative full-wave rectifier. Capacitor
C3 filters the rectified -35 vdc output at E.
This -35 vdc also provides the negative input to both the inhibit and read/write supplies 0
The positive input to these two supplies is -3 vdc from terminal B. This voltage is gen'erated by the forward voltage drop across four series-connected diodes D5, D6, D7 and D80
The anode of D5 is connected to the grounded center tap of T1. Because the inh ibit and
read/write supplies are similar, the following description of the read/write supply also
adequately describes the inhibit supply.

'10-53

The base of s~\:Jnl~·regu,lator.h'ans:~s.tQ~ Qt Is.bi9.se~(f~o.~JerminoLF ofJhe 1701 control.
~
'.:t. ~; (. r r ~ ~ "-" ",'.
' .
.
.

. •

" .

' , ' 1':

\:.; \

The operat80n of the 17.:01 !contr~J_ h' fu!J y.id:~crip,~>s:i}:~.£ be:.lo~
..o".. However u tO~,~nderstand
..
'

the regulating acHo;n oJ trons~.stors QJ and Q2 it€qn be.a~sul11ed
for the time being thatthebase of
'..
.

:,'"

Q1 is biased: through a: cpn!le~tllon,to th~ term1nal, p outP';Jt of the supply. Although thUs
.

•

: •

~...

r . ,_

• '~:.

connectlQnh il{l.'tfactmade through. rh.eJ 701 control c;:ircuitry!,
the bias feedback
funcHons
':
.
.: , ~

.~.

,,' .

"~'

in much the same way as if the feedback connection from output D were unstead made
l

..' 'i ~

: ,'. ~ : I -. ',;-'

.-~.)

;'.

throug~: a ,battery 11 referen~e d.iodeu 0.1" resistance
-"

If the output vol,tag.e~,f~_~.~,~1 e}the,r becquse <?~.9njflcJ~qs~ -ir the ,supply !:09d ll 91" ,~e,cause of
. a rise i'fl the r;e.gul,qtClf: inp~t;··ve;lt~Qe.1l then.th~ba~~ yolt9~e,of:.q1 als?rnseso Con~uction
~'.

through Ql decreaseSIl and the.,pl ..:e.r,Jlltt~r voltage rises Y'{ith .thebase voltage. Consequent.'

~:-

~J"'<"

:~:~~

i y.9 conduction thr'bugb. ,Q2 als:o qecr~ose~, "'" T~e 9.e~reas~, up conduction thro!Jgh the two
.

".'

".;. ~

'~,'

~,:: ~r71'~

":.:. .

transistors (chiefly Q2Lt:etlq~ tq.res,tore the ,origi~;a! ~o!ta:ge\;~t Do S~miladYII a f9~;tJn the
output voltage ~s counteracted by nncreased conductHon un the shunt' reg.u!ator. . _~?pacitor
C6provldes ~ I~w o;utp~t )mped,~n:e for transient loads.
During normal ci;rcuH:op~rqt'fiqnv,Z.ener dnode..p8 doe.s not c:onduct. This diode \~_used
..

:. 'if

¥ 1 .' .. ~

" " , .~ j

solely a.s,a prote.ct~ve,qev'·sy·o I('the ,eventth~t c9nduc:~Jon through 01 or 02 ,is seriously
impaired by a 1l)S:J,I.fupqtnpnv ,try.e c,ircuH .. o.utput vq!,tage}l"ould y ~n the absence of DB/! tend
.

I ' ' ' ' :

;..

to fall towards -35 yde.,!:. To a:v;o~d;~u.ch a lar;ge t:legativ~ 9utput voltagel1 ard th~ r~sulHng
•

.".

:..

"j<."

possibHl Hy of damagang other computer ,me':l0ry ~Lementsl1 Z~~er ~iode D8 is us:d ~9 clamp
the terminal Doutput to a maxi.mum negat.·ive value of -17 vdc with respect to termnnal B.
"

. :.

. t

f!' • .-

,~...

POWER S{JPPLY:'CONTROL 1701 - Thos !unit 'controls power supply 735. The }701

module contcsUns;two"id~nticcif; c'lrcuHs Q:' ,Oneofthese~two-circuits control-s the 735 inhibit
supplyu and the other controls the735 read/write supply; Since both the inhibHand read/
write suppl~es functOO~~tn the same way!! the foll:owirigdescription· of. the read/write control circuH On the lower half of the schematic), applies equally to the inhibH control
circuit (top half of sc~emaH~}..o
Term[na I E of the 170"1 control is connected't·o the -3 vdc common of the 735 power suppl y.
Terminal H is connected to'the nominal ...;,13 vdc output' of the read/write supply. Terminal A receives +'10 vdc' (fr6m,the 735 supply).

Terminals V and, Ware contTol terminals.

When V is' jumpered"tdi,W 11 the 'temperature' coefficient of the 'regulation in the 735 supply

.' lO~54

is -005% per CO 0 When this connec'tionis leffopen, the temperature coeffi~ient is -0.8%
per CO

The control output i~ otF,.

As an adjunct to th'e 735 read/write supply, the control circuit performs thn9~functionso
First, the terminal F output biases the base of shunt regulator transistor Q1 in the 735
suppl y

Th is bias determines the read/wri te oU~p'u'f:' vol tage. The bias, and,the resul ting

read/write output, 'can be ~diu~sted by a poten~ti'~~etel<
,

Second, a thermistor{placed in theenvi~onment of the memorycore:stack},makes t'he bias
.

. '

,.~,

temperature-depenQenL Because the thermal coeffici~n~ of thi's thermistor is'hegative

(":404% per Co), ,the rea:d/write o'utput' ~ortage 'is'6'~~9at'i,ve f~nction of tem'perat~r~ 0
, " ,

';"

",",

',,'

".,-,

.'~~"

•

' . '.,'

,',

:'j'

As the temperature of the core stack increases, th,e 'n3qd/write yol,tQ'ge'ontJ"c'uWent cle,....

. crease

',,'

,. , J .

','

This tempera.t~re'A;ompen~ation ~orr~cts f~r'the fact' 'that the highJr; th'~'bore temp-

erature, the smaller the ~ore wtriding "cJrre~t' th~.t is needed to swHcha"'rrlemo';y~c'ore
,",
... ,

r: ' ' .;

The third function of 'tlje cbntrol circuit is to compen,sate ·forchanges in'the read/write
,

~ .

,,'

•

t.;'

, ,

.•..

, .

voltage that are caused by variations in the,load and in the supply'
inpl1t voPtage.'
The
.'
.
.
.

. ~'

control circuit serves to fur.ther compound the shunt regulator conta~ined in the 735 read/
write supply

Transistors Q4 and Q5 make up a difference amplifier., The change in voltag~·.afthe coiIector of Q5 is proportional to the vol tage difference between the bases o'f Q4 an~ ,q5

Bias control levels from the potentiomet~rente~,th~differerice a'mpHfier6t th~ ba~7 of Q4.
Bias control Ievelsdetermined

by changes in the resistance of the thermistor are appl ied to

the base of Q5. The feedback, or regulation signal, also enters the difference 'afnpl ifier
at the Q5 base

The series combination of control potentiometer R13 and resistor R12 is in.parallel with
l

•

a 6.2 vol t Zener reference dio:de.' Th is doubl e~anode Zener diode provi des the ba~i c
vol tage reference used by the circuit.. The referen,ce diode has extremel y good temper1 "

' ; .

ature stability. Voltage across it remains nearly constant for normal variations in ambient
temperature, and for wide variaJi9ns j;h'curh~nt.o
Countercl,ockwiserotation of the pote~tipmeter va~iesthe base vol tage of transistor g4

'fro~ -902 vql ts to approximafe'ly ..;6.5 volts.: Rotating the potentiometer counterclockwise decreases the read/write·'output voltage; clockwise rotation increases the output,.

10~.55

vol tage. The potentiomet.er.c.ont(~l~,,theo.ut.Ryt VOL~.Q'9J~,iI1Ahe fqllowing ,manner. Assume
that the potentiometer is rotated counterclockwise.: JheQ4 pas,e vpltage)hen becomes
more positive, decreasing .co~duction throu~h Q4., Conducti(:m through Q5 then increases,
raising t~e ~se v~ltage of~"~P'~ transistor' ,Q6:~
.

Thi~ in~'r~~ses condu'ctionthrough Q6, and

~:;.

thus lowers the hias output at F. The more negative output at F causes increased conduc~

.-.

tion in the 735 read/write shunt r~gulator transi~tors, thereby decreasing ,the read/write
. .

output vol tage. Clockwise rotation of the potentiometer increases the suppl y output in
exactly":the opposite manner •
To und~rstand the lVfay inwhich the con~,~ol circuit compensates for temperature changes,
assume that while the 04 base voltage remains constant, the temperature increases. The
,

\',

increasing temperature produces a decrease in the value of the thermistor (connected bee

;.~.

• _:'

".:.'

,,..

;

•

;

tween J and K). ,As the resistance of the thermistor decreases, the Q5 base voltage also
'"

' . ;

-.-

•

decreases, increasing conduction through Q5. The bias output at F decreases, thus reducing 'the supply' output vo'!tage. Decrease'~ i~: dmbienf' tem'perature produce o~ increased
\

output vol tagein exactly the opposite mariner.

;' "

Connected across the supply output is a vol tage divider, comprising the thermistor and
resistors R16, R17, R18 and R19. The supply output voltage is fed back to the base of Q5
through this ~oltage dividEh;thereby regulating the output'ov~~varDations in load and input vol tage

.'rn ci s~n~e',th"erefore, Q5 provides the fitststclge of' a'compound shunt reg-

ula'tor. The final stage'of'this,'compo'und regulat~r is 02 On the 735 supply};
If, for exampl.e, the supply voltage becomes more negative, then the base of Q5 also goes
~

. ,

.',

;':-.

',-

-.,

If,'.

_'.

negative, increasing conduction through Q5. This causes the Q6 base vol toge to rise, and
increases conduction through Q6. The output F bias vol tage then drops, increasing conduction thr~;ugh the'shunt regula't6r' tra~sistors in the 735' supply. This causes the output
voltage of th~ 735 supply to ris~'to'its 6rig'in'al torrett value. Positive deviations in output voltage are c'orrech3din ~iactly 'thJ oppos'ite;manner.
e

POWER CONTROL 813 - This unit is the, main power control for the PDP~4 equipment

The 813
unJt appl ies men:tory
system.
p<?wer s~paratel
y from. the power t'o the rest of the com.
. .
."
'.",
.. ,'"
~..

puter. Del9yed ~e,lay switching in th~ control .!urn~ .on ,memorypower 5 seconds after the
,

.:.

' ; "

,.,

\, .... _

turn~on of c.omputerpo~er" and ,turr:,~ off m~morx power 5 seconds before turning off
.'

. ... -.'

'.1'-.""::

:~.':':"

-10-56

.~. i

I."

~ ""':~'"

,:';':-':

• -01'

.... ,

~'. .

',~~'"

computer power. Consequentl y, turn~on and hirn-off transients in'fhe computer eq~jp
ment. cannot dist'ur~ rn~rnory,c;ore states
•

" ,

the 813 unitaJs6providestyiid"control,signals: a timed ground ,level, arid a603 vac timing
s.ngnal., The gr6undleve1 i,s established, for 5' seconds at terminal 7, beginn:ing when com"pulerpower is turned on, and 'beginning again when memory 'power is ttJrnedofL This
ground' leveloenables 'the' power 'clock (paragraph 6;0.200 The 6.3 vac signaL, iprovided
whenever memory power is on, furnishes 60 cycle timing,to the real time c1ock,{paragraph
9-2d)

,Jh.~813~:powercontrormaibe used with either 110 va,c or220,vac.

If the'B13 is used with

110 vac, the two H input terminals are jumpered, and the 110vacj.s applied'across Hand
No For a 220vac inpu,t, N is the ground connection, while the H terminals are the two
.

. ... ~; ~

.,"

- ,

'hot connections to the 220-vol t line
o ·

,'~.' •

~ ~

,':

0,
•

•

, :The rnemprypow,er output is at terminals A-B. All other ac power for the computer ~s
furnished acrO$S C-D and D-F

The 6.3 vac output is at terminals 3 and 4. Ternionals

5 and 6 are not used" "
:'Four reloY~l Pl, .02'"

K3 and K4; establish the switching sequence withi,n .'the'S13control.

The, D1, ,contacts c.loseiQstantcineousJy,· bl,.lt open after a 5:"'second delay: The D2 contacts
, c1qse only'affer q 5-seconddelay, but open ins.tdntaneously. Both K3a,nd K4 are instantaneous on-off relays.
Normallyac line voltage is present at inputs Hand N. The power control is turned on by
closing the power switch on the console 0 Relay Dl is then energized. Contacts 2-3 of
Dl close immediately, energizing K30 All three sets of K3 contacts close at once, apply=
ing 110 vac across outputs C-D and D-,F 0 All the computer equipment fed by these outputs
is then energized

F~ve seconds after the D1

contacts closet' D2 contacts 2-4 close

Unless the memory power

switch is open, relay K4 then energizes closing both sets of K4 contacts. This supplies
j

110 vac to memory power output A-B 0 Fi lament transformer T1 steps down the 110 vac at
A-B to provide 6.3 vac at output terminals 3 and 4.
During the Hve seconds while D1 contacts 6-7 are closed and before D2 contacts 6-7 have
opened, terminal 7 is grounded

At the end of the five seconds, contacts 6-7 of D2 open,

10-57

disconnecting the ground level at pin 7 •
When the consol e power switch on the consol e is turned off, relays Dl and D2 are deenergized. Contacts 2-4 of D2 open cmmediatel y, de-energizing K4. This relay immediately disconnects power output to A and B, thus turning off memory power, and the 6.3
vac output at terminals 3 and 4. Five seconds later, D1 contacts 2-3 open, de-energizing
K3. All three K3 contacts open immediately, interrupting power to outputs C-D and D-F
and thus turning off the computer.
During the five-second turn-off delay, contacts 6-7 of D1 and 6-7 of D2 are both closed,
grounding terminal 7. At the end of the five seconds, contacts 6-7 of D1 open disconnecti ng the ground at pi n 7 .
The memory power switch permits the operator to turn off memory power while the rest of
the computer power is still on. Circuit breakers CB1, CB2 and CB3 provide overload
protection. With a 110 vac input, CB2 I imits the combined load at a II three power outputs
to 50 amperes.
With a 220 vac input, CBl limits the combined load at A-B and C-D to 25 amperes, while
CB3 I imits the load at D-F to 25 amperes. Meter M is an elapsed time meter which provides an indication of the total time in hours that computer power is on. Both input and
output power line filters are used; these are shown on the print as boxes Fl through F8.

10-58

MAl NTENANCE

. "'\

The foHowingspeci91 too,ls and ,test equiprryent are recommended for the efficien't maintena~ce
of the PDf-4 c~~pu"ter ~.
Multimeter: '

Simpson Model 260A,

'. Triplett 'Model 630NA, or equivalent
Submihioture' ~
,

Mueller type '30 or equivalent

all igator CI ips
Osci Iloscope

Tektronix 540 series with type CA plug-in
yertical ampl ifier, or equivalent

Long-lead probes

Tektronix P-6002 or equivalent

Current probe

. Tektronix P-6016 or equivalent

Paper tape gauge

Friden type T-18118, or equivalent

Plug-in puller:_

DEC type 1960*_

PI ug-in,extender

DEC type 1954*

Pigta i I pi ug-i n

Modi fi ed :PEC type ,1954

extender
6 ~ac iron -with isolation transformer

Sol dering iron

* Digital Equipment CC)_ rpora,tion furnishes one oLe.och
of these units without
"

charge with each ,PP,P:~4 computer.
{.

,'.

(

)

Included in the above list is the pigtail plug-in extender-, This maintenance aid can be readily fabricated from a standard DEC type 1954 unit extender'- Disconnect the small wire leads
to h~rmrnafs A~ B,'and C:oftheunit "extende"r';'and ~older eight.;..fo,ot leads to the three terminals. Solder al igatbrcHps to the free:>endsof the 'three 'eight~f6ot leads. Terminals A and B
can then be' connected tbthe TO~v6hmarginal" check';'pbwer supply •. , TerminalC can be connected to tl1e-1S:";vdl t ma~gih6'1 check' supply'. --ThTs pe'rmi fs -co'nvenien-tmargina I testing of
,

:..

:'.,;

""01:

individual circurt card

Either the .A or the B pOrH6t1;.~:rAhe car<:!can be separately checked,

thereby permitting submodu!ar testing

11-2 EQUIPMENT LAYOUT AND WIR!NG
Figure 11-1 shows the detailed physical layout for all of theJ09iccompris~d.bY"',th~:~t~f\dard ,.,
,.

;

-",'",

0/1

,.'

PDP-4, the real time option, and the control units for the reader, punch ond keyboard/printeL
-.'

. .

}:·.:·'.'~."~1:·)r·~

~t;,~;.·.

Figure 11-1 shows the position of logic circuits onl Yi locations of power control panels an'd'

Each mounting panel in Fi9ure1121i~'d'ivid'edc; int~

power suppl ies are shown in Figure 11-7.
sect;ons according to logical function.

Unlabeled areas bounded by solid lines.indicqte,:~ec.,··'·i"
.,
,,'

tions of the m~unting panel in which no modules are installed, Areas that are labeled by logic
funct;on and separated by dashed! ines represent circuits all of which appear qn ..th~,s9-rr~ logic
~

print (block schematic),

. ~

" , , ' it

Figure references are included as two-port hyphenat~d t1;l)plbers at
"

the lower left of each logic section bounded by solid lines,
Two module layout drawings, Figures 11-2 and 11 .. 3, show the module types normally installed
in every mounting panel location,

Figure 11-2 is the module layout for the standardfDP-4

system, including the memory and the reader control logic.

Figure 11 .. 3 is the module layout

for t!'e optional equipment: the real time ~ption, the magnetic tape control,' the control':, units
for the punch and keyboard/printer, and the adapters for the I ine printer and card reader'.
Figure 11-3 also shows the posif'ions of modules that are added to the PDP-4 internal· processor
when the type 17 memory option is installed.
The console wiring and circuits are shown in Figures 11-4 and 11 ... 5,

Figure 11-4 isa schema."

He of the wiring for the console keys and speed controls.

Figure 11-5 shows all indicators,

address and accumula-torswitches, and ope~ating switches.

In Figure 11-5, the re'or view

shows the console terminal strips, giving t~o-digit numbers (60, 61, etc .), each prefixed by
the console panel deslgnation OG
the cable destina'tions

In cable diagrams, these OG60"series numbers indicate

at the console.

Figure 11-6 is the cable diagram for the entire PDP-4 system, including th~real time option,
magnetic. tape control t an~ control logic for the paper tape re,ader and punch, the ;keyboard/
pl int~r, cord reader, cClrd punch

CRT display, and h igh.':,speed I'ineprinter

All movnti ng

panels in the centralfram~ (both bays) are shown with ,r~ferences to ,prin~s shp~ing ~~~.wiring,
,

cabl ing and logic contained in each panel ~, The in-out devices are shown as smaller blocks at

11-2

the left in Figure 11-6. The source and destination of all cables are shown, with references'
to cable I ists that show the connections and logical functions of each cable. The diagram:6lid
shows the type of connector used to terminate each cable.
The AC and DC wiring diagram, Figure 11-7, shows the power wiring configuration for a PDP4 that includes the type 25 real time option and the reader, punch, and Model 28 Keyboard/
Printer. The -15 vdc line from the type 728 power supply located in '1 E rear is wired in series
with the -15 vdc line from the type 728 located in1D rear; this provides the -30vdc"required
by the solenoid drivers for the punch and keyboard/printer.

In a PDP-4 using onl y the reader,

the 728 supply in 1E rear is not used. The type 728 supply in 2E rear supplies the +10 and -15
vdc for the type 25 real time option and the memory system (panels 2A to 2H). When additional in-out device control units are installed (in panels 2K to 2M), an additional type 728 power
supply is required. This additional supply is installed in location 2ER, and supplies power for
panels 2E to 2M. When the supply in 2ER is installed, the type 728 supply in location 2DR is
reconnected to suppl y only the memory system, panels 2A to 2D. The power suppl ies for the
type 17 memory expansion are located in bay 3, and are not shown in Figure 11-7.

11-3

LOGS

Properly kept and adequately detailed logs are absolutely necessary to good maintenance. If
a malfunction should occur, the first step in troubleshooting is to obtain all the available in":
formation about the faul t. The machine log is a vital part of the information pertinent to a:

troubleshooting problem. The standard PDP log format used by DEC, and available from DECto PDP-4 users, is shown in table 11-1. During normal computer operation, the most important
items to be logged are:

(1)

The times at which computer power is turned on and off;

(2)

The e.lapsed time meter reading when power is turned off;

(3)

The name of the' person or department using the computer during normal computi,ng

time;

1 ;

(4)

The times at which the user began and finished his use of the computer;

(5)

The name or type of program run, or the category of mach ine use (e.g., pr~gram
,

development, debugging, etc.).
The reverse side of the PDP log is reserved for entries in the maintenance record.
11-3

The main-

tenance record must Inc' ude every observation about mach i ne performance not al ready entered
as a comment on the front side'of the log; and it must include complete descriptions of everything done to the machine, apart from normal operation, for whatever reason.

In particular,

the maintenance record must at least include the following:
,(1)

Complete descript"ions of machine performance under marginal check, giving the

name of the program run, the panels to which margin voltages are applied, the power
lines supplied with margin voltages (e.g"
levels at which failure is observed,

+lOA, +lOB, or -15C), and the margin

Entries describing marginal check performance

shoul d be made regardl ess of the reason for perform ing the check.
(2)

The exact times of beginning and end of computer down-time.

(3)

Complete and detailed reasons for computer down-time"

This entry should include

a description of the mal function that causes down-time, if any.
(4)

In the case of malfunction, a detailed description of the steps taken to trouble-

s.hoot the mal function"
(5)

All steps taken to remedy a faul t (e.g., replacements, repairs, etc.)

Maintenance record entries must not necessari Iy be restri cted to the categories given above.
It is extremely important to log any machine behavior pattern or symptom, even if it does not
seem immediately pertinent to a machine malfunction

For example, if the operator notices

excessive vibration in the punch -- even if such vibration is not accompanied by malfunction-this observation should be noted in the maintenance record

If the operation log (front side)

indica,tes that a particular circuit breaker must be reset frequently over a short period, this
should be entered in the maintenance record"

Entries of this nature may seem insignificant or

'frivolous at the time they are noted, but if these symptoms later aid in troubleshooting a related
malfunction, the entries do not appear silly in the least.
A properly kept maintenance record reveals at a glance the previous history of failures throughout the entire system. Maintenance record entries often show patterns of consistency among
failures that seem totally unrelated,.

In troubleshooting, completely new lines of attack are

often suggested by such patterns of consistency.

To take best advantage of previous mal function

experience, the maintenance record must be kept up to date accurately and faithfully.
In any case of doubt as to whether an observation is important enough to put in the maintenance

l1-A

PDP

LOG

F=========t'=====-=-f---~------

--- -~-===P=====F==~==iF====C= = = = = = = 1

DATE

TI M EON

POWER

TIMEOFF

1==========!c=C==-- =-~'~F=-'=~-c=-~==±='=====I====~===dF==========:J
TIME TIME
ELAPSED TIME
USER
ON
OFF
COMMENTS
METER READING
t=======,==c= =_=~~=-==c_====~===============I=~A~T,,--_~P OW E R 0 F F
t-----------+---+------I---------------------------t---------I
~----------I----------f___---- ----1--- ------ ---

- - - - - - - - - - - - - - - - - - - - - + - - - -_ _ _ _'----_---.:.....1

~----------------------------

-------------------------~-------___{-----~---.J

~----------------- --------

- ------- ---- - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - --~----I

t - - - - - - - - - - - - -------- --------

--------------------:-----------+------------!

r - - - - - - - - - + - - + - - - - t - - - - - - - - - - - - - - - - - - - - - - - - I - ------------=------- - - - - - - , - - - - - - - - -

t - - - - - - - - - - + - - - + - - - + - - - - - - - - - - - - - - - - - - - -1----, --------=------------"--,,---,, - - -

t------------+-----+--+----------- ---=-=---------

t - - - - - - - - - - - + - - - + - - - - + - - - - - - - - - - - - - - - - - - - - - - - - -- -

-. --

-----,---

---

---,----

r - - - - - - - - - + - · - + - - - - t - - - - - - - - - - - - - - - - - - - - --1-------------- ,,---r---------+---+----t--------------------------------- - - - - ---"--

---------------_._-------------------------------------!
a------------I----- ----1-------------------- -+--------- ----

TABLE 11-1

SAMPLE OPERATION LOG FORMAT
11-5

MAINTENANCE RECORD

11-6

~ecord, enter it.

The maint~nance record is the on! y source of informaHon on. the histpryof

machine performance

Information from the manntenance record almost always saves tim.~

troubleshooting malfunctions later., but H the ~nformaHon ~s not entered/! the record is usel~ss.
~

Always enter everyth ing in the mannf'ena!1Ce ~'ecorrd; th ~s way [I everyth ing Bmportant is sure ,to
..... '.,,
be there
0

. J
.'

"-'

11-4 'ADJUSTMENT AND CAUBRAr~ON
~!I ,,~EC systems .are. designed for maXImum ;rel'uablllHy under a wide range of operating coq~i

tions

Very little adjustment or ca!Bb[iat~ol1 flS rrequfired c The followang procedures may be car-

ried out as corr¢c,tive mai.ntenance Yif necessary; but they should not be performed as routin:e
pertodic chec.ks.'
, Y

£.: AI?AU$TA~LE TIMING .<;:iRCU~TS .~ There are three types of adjustable timing circults
,~s~d ip., t~~ PJ>P-4:

the types 43q~ and 4303 adjustable delays, and the type 4401 C!9,9k.

til other;d~lay modu'~s used in PDP~·4 contaun distributed-constant delay lines

peJ9iYs of

this type cannot be adjusted c
The type 4303 integrating single shot module flS used Rn the Hming logic of the PDP-~'l

. '. ; ; : ! ) ~'.. .)

, ." ~~l-. . ~ .. ~

;

•

~.~

.' .

tance val u~s
~ '..

':."

•

~.'

. .

,'_t·

'::.

I" ~ ,

The shortest delay range,is ~~ter-

-v'

','>'.'

•

The four successively longer delay ranges.are

selected by cpnnecting pin D to pons Eu F,; HIl and J g respectivelyo
.

~:"I ,r ~ i

"'I

Pin D is the_capacHor sei ectHon termunal

0
-"';

.!.

••

•

mined,by making no connection to pHn Do

':"

f\;JormaU y the delay range ~s determuned by' selecting one of five c~p~c.i.-

,(Figure 6-1).
~

- .

• "

.--

.'~~

Fine adjustment,of the
,

, ••

delay is made at the screwdriver f'dmpot beh~nd the access hole in the type 4303 module
<

' . . '

frame ~

•

!'-J,

•

;

Delays longer than 009 seconds may be obtained by connecting an external capac-

,-, it~r between pins band M

~f desired!l an external potentiometer may be us'ed instead of

the trimpoti'in this case the externa~ pot'entnometer IS connected between pins X a'nd z~
Figure 6-1 shbwsthe t'ype 4303'used ~n the PDp·=4 timung logic

-,.-J

The delay adjustmen'ts

described above are made by the speed controls at the console.
The type 4401 module is the power dock shown un Fugure 6-1 D6"
at DEC to a frequency 'of about 25 kEiocydes

This module is adjusted

The output frequency of the type 4401 ;
,

clock may be adjusted at the tdmpot behrrnd the access hole in the aluminum frame o'f the
module

The type 4401 should not need adiustment unless H is replaced ~

Two type 4301 single-shot delay modules are used in the PDP-4,

One provides the 10-

microsecond delay between SPO and SPl P in the tim~ng !ogic (Figure 6-1),

The other pro-

vides a 5-millisecond delay in the punch logic (Figure 9-6)
The duration of the delay in the type 4301 module is adjusted by observing the durationofthe
level output at pin J

Connect an oscilloscope with a calibrated sweep to pin J

Trigger

the sweep internal Iy I and set the sweep time per cenHmeter adjustment so that the entire
duration of the level output is displayed.

The duration of the negative going level at pin

J is adjusted to the required delay by means of the screwdriver trimpot adjustment. An
access hole is provided for the screwdriver in the aluminum frame of the type 4301 module.

£. POWER SUPPLIES - The PDP-4 contains two types of variable power supply. These are
the type 734 marginal check power supply and the type 735 memory power supp"y.

The

type 734 power supply provides the marg:na! check voltage, variable from 0 to 20 vdc,
The output polarity of the supply is determined by the setting of the polarity switch on the
marginal check switch panel.

The voltage adjustment is at the knob at the front panel of

the typ~ 734 supply at the top rear of bay 2. This marginal check supply adjustment is
used routi nel yin ma rg i na I check procedures.
The type 735 memory power supply adjustments are made at the type 1701 plug-in module
(part of the supply).
ments

The type 1701 module has two access holes for screwdriver adjust-

The adj ustment through the center hoi e is the read/wri te current adj ustment.

adiustment through the bottom hole is the inhibit current adjustment.

The

For the 8K memory I

there are two complete type 735 power supplies, each with its associated type 1701 plugin control (paragraph 10-11~ and~).

These 735 supplies are each adjusted independently.

Type 735 memory supply adjustments are always made for current output
735 supply for voltage output.

Never adjust the

These current adjustments should not be altered unless there

has been trouble with the regulation of the supply; both the inhibit current and the read/
write current adjustments are set accurately during manufacuture.
is seldom required

Subsequent adjustment

If memory malfunction has been isolated to insufficient or excessive read/write current or
inhibit current, the type 735 supply may be adjusted by the following steps.

11-8

(1) Set the ACCUMULATOR and ADDRESS ,switchs to zero
the SPEED controls to the fastest repetition rate

Turn REPEAT on co Set

Have someone hold the DEPOSIT

key up. (If you are alone and cannot prop up the DEPOSI T key, deposit the instruction "jump to 0000 11 (600000) in location 0000. Press the START key.)
(2) , Attach an o,sciUoscope current probe to the wire originating at pin W of the 'typ'e ,
1972 read/write switch i~ location 2A 1 • ,Set the sweep to 1 microsecond per.c~nti-·""'-"
meter andtdgger the sweep on Tl (available at one of the insulated stand09fs ifj'P9n'ei "
1A). The oscdlloscope then displays theread current waveform, followed-immediately
by the write ~urrent waveform which is of opposite polarity.
(3) ~djust the current probe to give a calibrated deflection of conveflienfamplitudeo
Check both the read and write current waveforms for the current val ues given in Table
11-2 below. Do not yet al ter the adjustr'!len'ts at the type 735 memory power ~uppl;y.
(4) ,Turn on AS

" (If you are alone and cannot prop up the DEPOSIT key, halt the

, c~mputerandde'posit the instruction IIjump to 000'1 11 (60 0001) in 10cation,OOO, ~

, Again press the START key.
(5) Attach the current probe to the' wire or~ginatio.g at pin X of the type 1972 r~ad/

~rite 'switch in location 2A 1. A,gain check the read and write current wdve'fo,rm~
'''~

~gainstfhe values':giyen ill Tabl~ 11-2" below.
, ,,1,

(6) If both the read curr~nt and write current w(Jv,~forms as observed at pin Wand pin
X of the type 1972 read/wri te swi tch are both too great or too sma II by rough Iy the
same ampl itude, then the type 735 memory power supply needs adjustment. Adjust
the screwdriver trimpot through the center hole of the type 1701 plug-in so that both
the read and the write current waveforms have the value shown in Table 11-2 belowo
This adjustment c:ontrols both the rea~ and the write current waveform. The read current may be adjusted two or three milliamps high if necessary to obtain the proper
value for write;currenf(oi"lviceversa),. : . , '
, ~ "':,J.

(7) Return AS

r: ~

to zero

"')' ,

;,'"

With the current pro,~el:oqs;,er\(e the inhibit current wave-

17
form at pins W, X, Y, and Z of the type 1982 inhibit driver located in 2Cl0. The

peak inhibit current amplitude should corre$pond to the value shown in Table 11-2.
The type 735 memory power supply should be readjusted only if the inhibit current at
all four pins is too great or too sma! I by the same amount.

(8)

If the inhibit current adjustment is required, adjust the screwdriver trimpot through

the bottom access hole in the type 1701 power supply control plug-in.

The inhibit

current amplitude should be checked after adjustment at all inhibit driver output pins.

(9)

If you are alone and are using jump instructions to pulse the memory, check the

inhibit current at pins Wand X (location 2C5) by depositing the instruction jms 0000
(10 0000) in location 0001.

Since MBa and MB1 are both

a in this instruction, the

inhibit current levels may be checked at pins 2C5W and 2C5X.

TABLE 11-2

NOMINAL VALUES, * MEMORY READ/WRITE, AND INHIBIT CURRENTS

Core-stack Manufactur€r

Read/write Current

Inhibit Current

RCA

180 ma.

165 ma.

Ampex

180 ma.

165 ma.

General Ceramics

180 ma.

165 ma.

Ferroxcube

200 ma.

180 ma.

* Optimum current val ues are I isted on a label at the rear of the core-stack.
These values are determined at DEC for best performance under margins.

~ SENSE AMPLI FI ERS - Each PDP-4 memory system contai ns 18 sense ampl i fi ers.

There

are two types: the type 1538, and the type 15400 All 18 sense ampl ifiers in a memory
system are of one of the two types; they are never mixed.

The procedures for adjusting the

two types are identical; however, the locations of the adjustments differ.
On the type 1538:

the BALANCE adjustment is made through the lower access hole;
the SLICE adjustment is made through the upper access hole;
the MARGI NAL CH ECK toggle switch at the bottom of each

11-10

On the type 1538:

...

r'l1odLiI e fro me'i t used;to'a

pp Iy 'rna rg in. vo /toge ..

the BALANCE adjustment is made through the, upper acc:ess hole;
the SLICE adjustment is made through the lower access. hole;
..."......,...-

marginal check voltage is applied to all 18 modules by the SENSE
AMP switch on the marginal check'swrtchpone,"
The sen,se ampl ifi er adj ustments are made as foil ows:

(1) Using an oscilloscope with a differential preamplifier, 'observe'pins -T and V of the
1538; Sand U of the 1540 ~ Set the preamplifier of the oscilloscope todis,plqy the
differential waveform between the two pins ( on Tektronix type CA preamp, set to'
Uadd algebraic'~>and invert one but not both inputs).
(2) Run the memory Checkerboard program

Do not use the worst pattern P9rtionof

the Checkerboard program, since this pattern generates severe drift in the scope display.
(3) Set the duration of the scope hoace so that one entire memory cycle is displayed:
1microsecond/centime.ter pSync at T1

(4) Adjust the BALANCE to minimize the noise injected at T5 and T7. These timing
pulses correspond to the turn-on and turn-off times of the inhibit current. As the correct adjustment, is approached, the sense preamplifier output broadens and incrEtases
in amplitude" Often the strobe pulse, 0.7 fJS after T2, may be seen as a pip near the
center of the sense preamplifier waveform.
(5) Remove the oscilloscope probes~ and using one probe, observe pin M. 'Th'is pin
provides a -3 vdc logic level from the slicer section of the sense amplifier .

. (6) Stop the computer and restart at the location corresponding to the memory Checkerboard worst pattern

(7) At the marginal check switch panel just below the type 734 marginal check power
supply, turn on the first switch at the lefL This switch applies margt:nal check supply

11-"1

voltage to th~:.,tlO:~ li:n:e"f()r. t~,~.~~n.se .amp,lifiers ,Marginal check voltage is applied
to individual type 1538 modules using the toggle switch on the type 1538 module frame

fhityp'e,,,;54d.'ha~· no su~hswitch; ma~gin~voltage is applied to al'l 18 type 1540 '~od.

:'i'ul'~s ':byt~;~s~;i':tch'~t th~ marginal check s~itch panel.
(8) Have som~one stand,hy the type' 734 marginal check supply to vary the voltage and
call out meter readings .

The lower the voltage of the supply, the greater is the like-

Iihood that spurious bi ts are gen'erated; the higher the vol tage of the suppl y,' the great-~
jer j~ th~.P~~1 ih~9d of losing bits ~
•

. t'

"",r

. ~

.-,

•

Adlustthe SLlCE~ 'Control so that bits are ,lost and " p icked up" at margi'nal che~k vol t~dgeisymmetd~c dbout!the nominal +10 vdc level.

As the marginal check voltage ,is

decreased, the duration of the logic level at pin M is seen to increase\until eventually
a spurious thinner noise burst appears within, representing the spurious 1 level, se... ed
":'-1 ~

'1 .~ ~ .~', ~ [' :_ !'"~,~ c~.~~ t .

from a core containing
"

o.
..,.'.

As the marginal check voltage is increased, the -3 volt logic level at pin M n()rrows,
and eventually either falls or becomes so narrow as to exclude the strobe pulse. When
,tbi~happ~ns', ·,·the sense ampl ifier pulse output is absent regardless of th"e state of the

sensed core; the bit is lost. The SLICE must be adjusted so that the vol tages (as pro,vide~,by the mar~!n~1 check supply) at which bits are lost and picked up, ,are sym"m

'metric about the nominal +10 volts~
'd TAPE READER AMPLIFIERS - All nine reader amplifiers are mounted on one 'printed cir. ;"cuit.board 'located on the reader chassis,

They are shown in Figure 2-2- 6f the DigHroni cs

Perforated Tape Reader Model 2500 manua I dated June 1962"
Befof 7 making,.adiu:~tr~ents on the reader amplifiers, the reader itself should be checked
for proper m,echoni<??1 operation.

The read~r ampl ifier a~iustments affect the timi~g and

duration of the reader amplifier output levels.

However, the intensity and duration of

":. -<:th~'light, impuJse sensed by the reader photodiodes also affect these same output levels,
Therefore, before adjusting the reader amplifiers, the following four steps should be performed,
.;;;:;~' (1)' CheckitlJ~he"laterat' registration ;of the punched holes in fhetape with respect to the

11-)2

tape edge" Use the Friden tape gauge type T..;, 18118'0 insert the gauge pi ns into the
tape feed holes and check that the.tapeliesi"n the gauge with the edge nearer the
feed holes snug against the raised shoulder of the gauge"

(2) Remove the upper read head cover ~ Thread the tape through the tape guides on
both sides of the read head, but pass the tape over the capstan on the left,:and over
(not through) the brake assembly on the righto Position the tape lengthwise so-that
the feed hole of the tape is over the feed hole photodiode in the read head." Set the
tape guide knob to READY. Check for lateral r'egistration at the feed hores. i The tape
feed hole should not be out of registration laterally by more than 10% of its diamet~r.
(3) With reader power on, check that the excit~r lamp has not become yen ow. If th~
light is 'not white and bright, replac~ the 'lamp.' Check that the light beam falls directi y on the row of photodiodes (the tape need not be loaded). The I ight beam adjustment procedure is described in paragraph 5.,5.3' of the Digitronics Model 2500
manual ..
(4) Replace the read head cover. '
.

If the mechanical operation 'o'f the reader is satisfactory, the tape reader ampl ifiers may

be adjusted as described below.
Adjustments

to the tape reader ampl ifiers are made at the nine screwdriver trimpots mount-

ed on the amplifier card (LAC).
The amplifier outPyt levels should be ?bserved with an oscilloscope having a dual-trace
preamplifier. A closed loop of tape having al~ernate lines punched with 15 and Os sho~ld.
be used. The qdiustme,nt procedure is as follo~~. ,

;.'

(1) Sync the"'os'~illosCcipe sweep to the ~'eg~tive-going leading edge of the waveform'
.

•

' .

:' " , "

j'~.

::..\

at pin S of the pulse generator in location 1 K14. This signal is the output 'of the tape'
reader feed hole amplifiero Set the sweep to 10 ms/cm so that the signal from three
lines on the tape is displayed.
(2) Run the closed tape loop of 1s and Os continuously.

1'1-13 '

This may be accomplished' by

,~~,-

putti ng the i nstruc tions rsa (70 0104), rsf (70 0101), j mp (60 000 1), and jmp 0000 (60
0000) in memory locations 0000, 0001, 0002, and 0003, respectively.

Start the ma-

chine at 0000
(3) With one oscilloscope channel, observe the waveform at pin lK14S (in parallel
. with the sync probe).
hole levels

Three negative-going levels are displayed.

These 'are the feed-

(4) Adjust the feed-hole amplifier on the reader chassis to provide negative,-going
output levels of duration between 1 3 and 1 .4 ms"
u

(5) Set the oscilloscope preamplifier to switch channels on alternate sweeps. With the
second scope channel, observe the data channel ampl ifier outputs (one at a time) at
pins F, K, N, S, V, and Y of location lK09, and at pins U and X at location lK12.
The display should show the two 1 .3+ ms

feed-hole levels and one data-channel neg-

ative-going level of longer duration, corresponding to the line of holes on the tape.
(6) Adj us t the data-channel ampl i fi ers for a Iogi c Ievel duration of 2; 3 to ,2.4 ms,
(7) Check that the trailing edge of the negative data-channel level is at least 0.3
ms. later than the trailing edge of the feed-hole level.

This completes the adjustment

procedure,

11-5 RECOMMENDED SPARE PARTS
The most economical quantity of spare parts to be maintained depends on the requirements of
the individual userc

Spare module stocks for the PDP-4 used one shift per day need not be as

large as spare stocks for the PDP-4 used two or three shifts per day,

Similarly, in applications

that permit only minimal down-time, the stock of spares must be greater than the stock required
when more down-time can be tolerated < Paragraphs::,!:" and.:. below discuss recommended
spare allowances for modules, circuit components, and in-out equipment, respectively,

Para-

graph ~ gives recommended mechanical spare allowances.
:: MODULE SPARES - For single shift applications, one spare module of each type usually
constitutes a sufficient stock of spares. A spare module of each type permits testing b 1'
11-14

substitution during off hours ... ,Wh~.n.q,,9~f.e9t.iy~n,oduJe is removed and replaced by the
corresponding spare, the defective module can be repaired to create a new spare

Defec-

tive transistors, diodes, and other easily detected faulty components can be rapidly removed and replaced

In single shift operations, two modules of the same type very rarely

fail during the time required to repair one.
Table 11-3 gives the DEC module types used in the PDP-4, including the 4K and 8K memories; the reader, punch, and typewriter control logic; and the type 25 real time option~
The system module list, Figure 11-8, gives the total module count for a PDP-4 system ..
For PDP-4 applications in which down-time must be minimized, and for installations used
for more than one shift per day, additional stocks of the more complex modules are deSHrable

(,I

The more complex modules may require considerable time for diagnosis and repair

of faul ts" To minimize down-time, insurance (in the form of additional spares) should be
provided against the possibility of two failures within the time required for repair. Additional spares are also desirable for module types used in large quantities

Table 11-4 gives recommended additional spare allowances by module type for PDP-4 ap-'
plications requiring minimal down-time or multiple shift operation

The spares listed in

Table 11-4 are recommende~ in addition to the minimum stock of Table 11-3e All PDP-4
installations should stock the Table 11-3 listing, but high-usage or high-priority installations should stock the Table 11-4 allowance as well as the Table 11-3 allowance

For example, the spares allowance of module type 4204 are as follows: in a single-shift
installation where moderate down-time can be accepted, onl y the singl e 4204 spare listed
in Table 11-3 need be stocked

In a multiple-shift installation or in an installation where

only minimal down-time can be tolerated, two type 4204 spares are recommended
additional spare is Iisted in Table 11-4.)

11-15

(The

TABLE 11-3

RECOMMENPEOMQOULE SPARES
4114/4114R

4216

4115R

4218

1213

1973
2
1976
2
1978

4301

1310

1982

4127/4127R
3
4128
4129/4129R

4401

1103
1104

4303

1311

41 02R

1540

4105

4150

4407

1607

6
4106/4106R

4203

4410

4111

4204

1701

4112R

4214

1972

4113/4113R

4215

4604
5
4605
4681 3 ,4

1690

NOTES:
1 - required onl y in the Type 25 Real Time Option.
2 - resistor boards: spares are desirable but not necessary.
3 - required only in the Teleprinter control logic. In emergencies,
a type 4401 clock adjusted to 9.6 kilocycles may be used in place
of th e type 4407 .
4 - required only in the high-speed tape punch control logic.
5 - required in the Type 25, the reader control, and the punch control logic.
6 - In emergencies, the types 1103/1103R may replace the types
4106/4106R.

11-16

'.:

TABLE 11-4

~'~ ~~

RECOMMENDED 'ADDITIONAL MODULE SPARES

(For minimal down-time or multiple shift use)

Standa rd PDP-4

(i nc Iudes 4K memory and reader control)
4203

4204

4604

1540

1972

1982

1103,

1540,

2-1972

4129R,

4604

Optional Equipment
The 8K Memory:
Type 25 Real Time:

Tape Punch:

(no additional spares necessary)

Model 28 Teleprinter

(no additional spares necessary)

I N-OUT DEVICE SPARE PARTS - Recommended spare parts allowances for the Digitron-

ics photoelectric paper tape reader, the Teletype BRPE 11 paper tape punch, and the Teletype Model 28 keyboard/printer are presented below.
Table1l-5 gives the recommended spare parts allowance for the Digitronics Type 2500
readero Installations at which down-time must be minimized should also have a complete
Type 2500 reader available for immediate replacement.

11-17

TABLE 11-5