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XX-4E683-23

1974

26 pages

Original

1.6MB

Document:	PDP-15/76 UniChannel 15
Order Number:	XX-4E683-23
Revision:
Pages:	26
Original Filename:	http://bitsavers.org/pdf/dec/pdp15/XVM/Unichannel15_Overview_1974.pdf

OCR Text

"'l"

I ,.~
f

® 1974

Digital Equipment Corporation

'The material in this manual is subject to change
without notice.

The following are trademarks of
Digital Equipment Corporation
Maynard, Massachusetts 01754
DEC
DIGITAL
PDP
UNICHANNEL

TABLE OF CONTENTS

PAGE NO.

SECTION
INTRODUCTION

UNICHANNEL IS HARDWARE ARCHITECTURE

UNICHANNEL IS SOFTWARE ARCHITECTURE

MEMORY LAYOUT

.. . . . . . . .. . . .. . . .. . . . . .. . . . . . . . . . . . . . . .
~

PIREX TASKS

INTERRUPT LINK

MXIS-B MEMORY MULTIPLEXERS

.............................. 17

PDP-II/OS CONTROL REGISTERS

SYSTEM CONFIGURATION

SYSTEM RESTRICTIONS

..................................... 21

PDP-IS UNICHANNEL OPTIONS

INTRODUCTION

This guide describes in more detail, the UNICHANNEL 15 operation and
features presented in the RK15 Disk Cartridge System Option Bulletin.
The first section ..••• presents a look at the UC15 system architecture.
The second section ...•. describes the PlREX montior system; how to
use it and other software aids.
The final section •....• provides, for those interested in creating
their own programs, a complete hardware specification including lOT
and register .descriptions.
Supplementing this guide are two manuals:

Unichannel 15 System Maintenance Manual: •. DEC-l5-HUCMA-A-D
UC15 Software Manual: ....•.•.••.•.•......• DEC-15-XUCMA-A-D
The maintenance manual describes the details of the MXl5-B and the
DRl5-C logic and gives maintenance details.
The software manual describes the details of the PIREX Monitor.

UNICHANNEL - 15 HARDWARE ARCHITECTURE

The term UNICHANNEL was created because it emphasizes the union of
Digital's UNIBUS with the big computer concept of the programmable
I/O channel. UNICHANNEL 15 unites low cost, mass produced peripherals with big computer software and performance on the PDP-IS.
UNICHANNEL 15 (UCIS) is a peripheral processor for the PDP-IS utilizing the PDP-II/OS minicomputer. It provides the PDP-IS with a
second general purpose processor and a second high speed I/O bus;
the UNIBUS. This UNIBUS is an IS-bit pathway permitting transfer
of either IS-bit words, l6-bit PDP-II words, or two S-bit bytes.
The UCIS allows flexible low cost configuration and expansion
of PDP-IS systems.
The UCIS minimizes the peripheral processing load on the PDP-IS
allowing maximum computational throughput in a low-priced,
medium scale system •

. . . UN
.. IB.U.S
. .......

UC15

~~__P_D_P___I_S__~. .P.D.P.-.I.S. .I./.O. .B.U.S_

FIGURE 1:

Simplified UCIS Diagram

UNICHANNEL 15 OPERATION
There are three major components of the UCIS:
1.

A PDP-II/OS computer with "local" PDP-II memory.

An MXlS-B memory multiplexer which allows both the PDP-IS
processor and the PDP-II processor to share common memory.
The shared memory is ordinary IS-bit PDP-IS core memory_

An "interrupt link" to provide a real-time means of interprocessor communications.

PDP-IS MEMORY
(up to I28K
words)

MXIS-B
MEMORY
MULTIPLEXER

PDP-IS
COMPUTER

UNIBUS

PDP-II
MEMORY

PDP-IS I/O BUS

PDP-II
CPU

Figure 2:

INTERRUPT
LINK

Diagram of UCIS Hardware Interrelationships

SUMMARY - UNICHANNEL IS HARDWARE ARCHITECTURE

This particular architecture was chosen because of its many advantages •••••••
PDP-IS Memory is addressable by the UNIBUS. Hence, DMA transfers
from and to such secondary storage devices as disks are direct.
The interrupt link provides inter-processor signaling on a microsecond basis. This is ideal for efficient real-time service -a necessity for flexible I/O control.
All PDP-IS systems may be upgraded by adding the UCIS.
remains useable.

All memory

Cost is minimized by allowing the PDP-II to share the PDP-IS console
and paper tape loader system.
Maximum use of the PDP-IS memory is maintained through synchronization overlap with memory use by the MXIS-B. This "pre set up" technique increases the number of memory cycles per second when both
PDP-IS and PDP-II/OS are accessing the common PDP-IS memory.
The UNIBUS provided by the UCIS is electrically compatible with any
device meeting UNIBUS interfacing specifications with the following
restraints:
1.

UNIBUS lengths must be kept short.

No provision is made for UNIBUS parity.

Data in the common PDP-IS memory may be treated as either 18 or 16
bit words or as (2) 8-bit bytes.
True simultaneous parallel processing is possible in the local and
common memories.
The DMA rate is high and the worst case and average latencies are
low for maximum I/O performance.
Finally, the system is highly modular allowing flexibility in configuration and excellent software utilization and control. The
system permits variations in both local and common memory size. It
allows almost any combination of PDP-IS and UNIBUS peripherals.

UNICHANNEL - 15 SOFTWARE ARCHITECTURE

The hardware architecture is complimented by sophisticated system
software. PDP-IS software systems running with a UNICHANNEL
system relies on PIREX, a compact multitasking peripheral executive.
In addition to PIREX, Digital supplies UNIBUS device drivers,
UNICHANNEL compalible handlers, and supporting utility functions.
The software system used by UCIS consists of two parts:
1.

One component is a mutli-programming peripheral processor
executive called PIREX and is executed by the PDP-II.

The other component is an operating system in a PDP-IS.
(e.g. DOS-IS or BOSS-IS).

PIREX
PIREX is a multi-programming executive designed to accept any number of requests from a PDP-IS or PDP-II and process them on a priority basis while processing other tasks concurrently. PIREX services all Input/Output requests from the 15 in parallel on a controlled priority basis. Requests to busy routines (called tasks)
are automatically queued (entered into a waiting list) and processed
whenever the task in reference is free.
In a background environment, PIREX is also capable of supporting any number of priority
driven software tasks initiated by the 15 or the 11 itself.
Figure 3 shows the communications flow in a UNICHANNEL system.
The possible links which may exist in the system are as follows:
1.

Handler to driver to allow the PDP-IS to use a UNICHANNEL
device.

Handler to non-driver task to allow the PDP-II to intercept
output and manipulate it or store it for spooling.

Program to non-driver task to allow cooperative processing
on the two CPU's as occurs in the use of the MAC-II assembler.

-...

BUFFERS IN
SHARED MEMORY

---

INTERRUPT LINK-TASK CONTROL
BLOCK STRUCTURE

I ~----------- ---~ I
I DEVICE

-- --- ------ --DEVICE
I
HANDLER I PDP-IS

.
I

~.
0

SOFTWARE
TASK
I
I

I-_

~--::.:--.

~-----

DEVICE
I DRIVER

-----

DEVICE
HANDLER

I
------ ----~ i
I
I
I
----I
II ,..----

DEVICE
I
HANDLER ,I

SOFTWARE
TASK

I DRIVER

~ __ ~

~-X

SOFTWARE
TASK

I SOFTWARE
. TASK

-----

~== -=...-:- - - - - r:==~
R

Figure 3

I
: DEVICE

DRIVER

DIAGRAM OF UNICHANNEL SOFTWARE SYSTEM

MEMORY LAYOUT

Figure 4 details the memory map which exists on UNICHANNEL System.
Note that both the 11 and 15 parts of the system can operate concurrently, all memory contention is resolved by the MXls-B. Note
also, that if the 11 system operates with area "A" complete simultinaiety is possible because no memory contention can occur.

l28K
PDP- 15 ADDRESSES

UNIB US ADDRESSES
Unav ailable

12 4K

116 or 112K

Ava 1'lable to
DMA breaks

Available to PDP-IS
and PDP-IS I/O BUS

20 0 r 16K

28K
"Sha red" memory
aval'lable to
both CPU's

Shared
Memory

8 or 12K

'\ 0

Loca 1 11
Memo ry

Unav ailable

0
~

"Local" PDP-II Memory = A
"Shared" Memory = B
PDP-II CPU Address Space = A + B
UNIBUS DMA Address Space = A + B + C
PDP-IS Address Space = B + C + D
Figure

UNICHANNEL SYSTEM MEMORY MAP

PIREX TASKS

The PIREX software system consists of several routines to support
multi-programming among tasks. These routines perform such functions as: context switching, node manipulation and scheduling.
The tasks which execute in this environment are device drivers,
directives to PIREX, or merely software routines which execute in
a background mode.
Device drivers are tasks which typically perform rudimentary device
functions (e.g.: read, write, search, process interrupts, etc.),
Directives are tasks which perform some specific operation for a
task under PIREX. The connecting and disconnecting tasks to/from
PIREX are performed by the CONNECT and DISCONNECT directives. The
third type of tasks are software routines which execute in a background mode of operation. The MACRO-II assembler and Spooler are
both run as background tasks.
To support multiprogramming among tasks, each task is required to
have a format as shown in the figure below:

Task Stack Area----------

Control Register--------Busy/Idle Switch---------

Task Program Code--------

Figure

TASK FORMAT

The execution of a Task by PlREX is accomplished by first scanning the
Active Task List (ATL). The ATL is a priority-ordered linked list of all
active Tasks in the current system currently capable of running. An
Active Task is one which:

Is currently executing.

Has a new request pending in its deque (double ended queue) .

Has been interrupted by a higher priority task.

When a runnable task is found, the stack area and general purpose
registers belonging to the task are restored and program control transferred to it. Program execution begins at the first location of the
task program code (See Figure 2.1) or at the point where the task was
previously interrupted by a higher priority task. When a task is interrupted by other tasks, its general purpose registers and stack are
saved. The ATL is rescanned when a new request is issued to a task or
when a previous request is complete.
When the PlREX Software System is running, it is normally executing the
NUL task (a PDP-II WAIT Instruction); The NUL task is run whenever there
are no requests pending, a task suspends itself in a wait state,
or while all other tasks are waiting for I/O previously initiated.
When the PDP-IS issues a request to the PDP-II to be carried out by
PlREX, it does so by interrupting the 11 at Level 7 (the highest
PDP-II Interrupt Level) and simultaneously passing it an address
of a Task Control Block (TCB) through the interrupt Link.
An 11 task can issue requests via the IREQ MACRO.
The contents of the TCB comfletely describe the request (task addressed, function, optional interrupt return address and level,
status words, etc ..•• ) The TCB will usually reside in the PDP-IS
memory and must be directly addressable by the 11.
(i.e. It resides
in shared memory) •
Error conditions are passed back to the 15 in the Task Control Block (TeB) along with status information necessary for
complete control and monitoring of a particular request.
Usually the request is to a device on the 11 but other types
are allowed.
Task Control Blocks are used for communication with PlREX and
tasks running under it. The general format of a TCB consists of
three words followed by optional words necessary for task con~un
ication. Optional words, generally are used to pass buffer addresses, commands and device status as may be appropriate.
TeB:

(API TRAP ADDRESS *400(8)} + API LEVEL
(FUNCTION CODE *400(8)} + TASK CODE NUMBER

REV:

REQUEST EVENT VARIABLE
(Optional Words)
Figure

STANDARD TCB FORMAT
10.

The "TRAP ADDRESS" is a PDP-IS API trap vector and has a value
between ~ and 377(8). Location ~ here corresponds to location
¢ in the PDP-IS. The API Level is the priority level at which
the interrupt will occur in the PDP-IS and has a value between
~ and 3.
A ~ signifies API II Level II ~ , a 1 for level 1 etc •••
The API trap address and level are used by tasks in the PDP-II
when informing the 15 that the requested operation is complete
(e.g ••• a disk block transferred or line printed).
The Task code number is a positive number between ~ and 128
that tells PIREX which task is being referenced, (Tasks are
addressed by a numeric value rather than by name).
The Function Code determining whether hardware interrupts are
to be used at the completion of the request. If the code has a
value of ~, an interrupt is generated at completion of the request;
If a 1, an interrupt is not made.
The Request Event Variable, commonly called REV or just EV, is
initially cleared by PIREX (set to zero) and then set to a value "n"
(by the associated task) at the completion of the request. The
values of "n" are:
~

= request pending or not yet completed.

= request successfully completed.

-2

(mod 2·16-1) non-existent task referenced.

-3

(mod 2·16-1) illegal API level given (illegal
values are changed to level 3 and processed).

-4

(mod 2·16-1) illegal directive code given.

-777

= (mod 2·16-1) request node was not available from
the Pool, i.e. the POOL was empty, and the referenced
task was currently busy or the task did not have an
ATL node in the Active Task List.

NOTE -- the Task Control Block specification clearly defines a
modular cOITIDunications structure with minimum impact on PDP-IS
software.

11.

ADDING DRIVERS TO PlREX
A powerful feature allows the PDP-IS to bring in a PDP-II driver,
(into either its own memory or the II's
local memory) connect
it to PIREX via a connect directive (a disconnect directive) is
also provided) and then issue I/O requests through PlREX to the
driver. The user can now take full advantage of the existing and
future PDP-II peripherals along with an elaborate queuing structure built into PlREX allowing complete parallel processing.
MACRO 11 ASSEMBLER (MACll) AVAILABLE)
A MACRO 11 Assembler is provided. This assembler is a Macro subset of the existing PDP-II Macro assembler and is slightly modified to run under the control of DOS-IS and PlREX.
To accomplish this, the MACRO assembler (MACll) is loaded by the
15 as a core image into bank 1 of the 15. MAC 11 is then connected
up as a low priority driver to PlREX and requested to begin the assembly. The 11 then carries out the actual assembly while the 15
handles all of the opening and closing of files, reading and writing of test and object information until the assembly is complete.
To the user at the console teletype, MAC 11 appears to be just a
DOS-IS system program which is loaded in and run by the 15.
NOTE: That any customer developed software should of course, take
into account PIREX context switch, the bandwidth of the UNIBUS 18
and latency consideration of the associated system.
SUMMARY
As one can easily see, the UC15 software system is a powerful tool
to the user who requires the utmost in flexibility and utility.
UC15 also provides an expansion capability beyond any system currently available.

12.

INTERRUPT LINK

The following section describes the registers and control of the
interrupt link. This link is used to pass Task Control Block
Pointers (and through them the information in Task Control Blocks)
between the PDP-IS and PDP-II systems. The hardware which comprises this link consists of a DRIS-C special purpose interface
to the PDP-IS, I/O BUS, and 2 DRII-C general purpose UNIBUS interfaces. The DRIS-C is controlled by PDP-IS lOT's while the DRll's
are accessed as registers on the UNIBUS.
Register Descriptions (PDP-II)
(CSR) 767770

Bit 6 - when bit 6 is a 1, it will enable an interrupt on BRS to TV 300, if the API DONE flag is set
in bit 7 of 767770.
Bit 7 - API DONE - set to 1 whenever none of the 4
API channels has a request pending.
NOTE: Neither of these bits is expected to be
used in normal systems programming.

(ODB) 767772

Low byte - contains the API address for an API level
Loading a new value in the byte causes
the appropriate API flag to be set in the DRlS-C and
and API break in the PDP-IS will occur, is the API
is enabled and no higher activity is occuring. It
also will cause a PI interrupt if API is not installed.

~reak.

High byte - contains the API address for an API
level 1 break. S~e conditions as low byte.
(lOB) 767774

Bit ~ - contains bit "2" of the Task Control Block
Pointer (TCBP) . See note under bit 1.
Bit 1 - contains bit "1" of the TCBP.
NOTE: That reading 767774 does not effect the
new TCBP flag in bit 7 of 767760-.-Bit 6 - API 2 DONE flag - when a 1 indicates that
there is no API level 2 request pending before the
PDP-IS. When a 1 also indicates the 767762 low
byte may be loaded with a new API level 2 address
to cause a new API interrupt level 2 and set the
API 2 flag in the ORIS-C.
Bit 7 - API ~ DONE flag - when a 1 indicates that
there is no API level ~ request pending before the
PDP-IS. When a 1 also indicates that 767772 low byte
may be loaded with a new API level ~ and set the API
~ flag in the ORIS-C.
13.

Bit 8 - Local Memory Size bit ~ - the least significant bit of a two bit field which specifies the
number of, 4K word memory banks that are connected
to the UNIBUS.
Bit 9 - Local Memory Size Bit 1 - the most significant bit of a two bit field which specifies that
number of 4K memory banks are connected to the
UNIBUS.
LMSI

LMSO

0
0
1
1

0
1
0
1

o Local Memory
4K Local Memory
8K Local Memory
12K Local Memory

Bit 14 - API 3 DONE flag - when a 1 indicates that
there is no API level 3 request pending before the
PDP-IS. When a 1 also indicates that 767762 high
byte may be located with a new API level 1 address
to cause a new API interrupt at level 3 and set the
API 3 flag in the DRIS-C.
Bit IS - API 1 DONE flag - when a 1 indicates that
there is no API level request pending before the
PDP-IS. When a 1 also indicates that 767772 high
byte may be loaded with a new API level 1 address
to cause a new API interrupt at levelland set the
API in the DRIS-C.
(CSR) 767760

Bit 6 - ENABLE TCBP (Task Control Block Pointer)
INTERRUPT - When a 1 allows and interrupt on BR
level 7 to TV 310 upon receipt of a new TCBP from
the PDP-IS.
Bit 7 - NEW TCBP flag - is set to 1 whenever the
PDP-IS issues lOT 706006 thus placing a new TCBP
in 767764 and bits 0 and 1 of 767774.
It is cleared
by the PDP-II doing a DATI to location 767764.

(ODB) 767762

Low byte - contains the API address for an API level
2 break. Same conditions as 767772 low byte.
High byte - contains the API Address for an API level
3 break. Same conditions as 767772.

14.

(lOB) 767764

TCBP (Task Control Block Pointer) - bits 3-17.
This contains the lowest IS bits of the address sent
by the PDP-IS. Note: that the address is "word"
aligned. Note also that doing a DATI to this register lowers the New TCBP flag (767760 bit 7)
and also sets the DONE flag cleared by lOT 706002
in the PDP-IS.

PDP-IS lOT's
706001

SIOA - Skip I/O Accepted. Tests whether the TCBP
DONE flag is-set-indicating the PDP-II has read
the TCBP and skips the next location if the DONE
flag is a 1.

706002

CIaO - Clear !/O ~one.

706006

LIaR - Load I/O Register and clear TCBP DONE flag.
Places the contents of the PDP-IS "AC" into an 18bit buffer register. The output of the buffer
register is seen by the PDP-II as TCBP at location
767764 and bits 0 and 1 767764. The lOT also
causes the TCBP DONE flag to be cleared and in the
PDP-II causes bit 7 to be set in location 767760,
which in turn causes the PDP-II to do an interrupt
at BR 7 to TV location 310.

706112

RDRS - Read Status Register - Clears the AC and
loads the contents of the DRlS-C status register
into the AC.
(This effectively moves the DRlS-C
enable interrupt bit into bit 17 of the AC).

706122

LDRS - Load Status Register. Loads the contents of
the AC into the DRIS-C status register.
(Places
value of AB bit 17 in the DRIS-C "enable interrupts"
bit).

706104

CAPIO - Clear APIa flag in DRIS-C.

706124

CAPII - Clear APll flag in DRIS-C.

706144

CAPI2 - Clear AP12 flag in ORIS-C.

706164

CAPI3 - Clear AP13 flag in DRIS-C.

706101

SAPIa - Tests the APIO flag in the DRIS-C and skips
the next in~truction if the flag is 1.

IS.

Clear the TCBP DONE flag.

706121

SAPll - Tests the APll flag in the DRIS-C and skips
the next instruction if the flag is 1.

706141

SAPI2 - Tests the AP12 flag in the DRIS-C and skips
the next instruction if the flag is 1.

706161

SAPl3 - Tests the API 13 flag in the DRIS-C and
skips the next instruction if the flag is 1.

PDP-IS STATUS REGISTER (ORIS-C)
Bit 17

Enable PI/API interrupts. When a 1 enables interrupts from the PDP-II processor. Note this bit is
set to a 1 by initialize and the CAF instruction.
It can only be cleared by using the LDRS (lOT 706122)
instruction.

bit #

t&\\\\\\\\\\\\\\\\\\\'\\'\\~\~
enable PI/API

Figure

16.

Figure: 8

PDP-II/OS CONTROL REGISTERS

Bit #

DRII-C #0
TV

Bit #14

r...a..~~_ _ _ _............a..~~~_ _ _ _ _ _ _ _ _ _ _ _ _~1 767772

= 300

API 0 Address

APIOI Address

BR = 5

Bit#IS 14

9 8 7

1 0

I I ~\\\\\\\~ I I I ~\\\\\\1l1121 767774
Bit#

~\\~\\\\\~

DRII-C #1
TV

= 310

BR = 7

Bit#

16olI~

......_ _ _ _ _

I K~\\\\\\\\\~ 767760

--.&Jt,~.a....,)~,---

API 3 address

--,1 767762

_ _ _ _

API 2 address

Bit# 15

0
3
-.
.
.
767764
PDP 15 bit number
1.
~~\1

TASK CONTROL BLOCK POINTER (TCBP)
(upper 2 bits in 767774)
17.

MXIS-B

MEMORY MULTIPLEXERS

When the PDP-IS memory is accessed by the PDP-II/OS or any NPR
UNIBUS device, the addresses are relocated by the MXIS-B multiplexer.
The MXlS-B multiplexer not only relocates the UNIBUS addresses
but emulates byte operations in PDP-IS memory. Hence normal
PDP-II programs, with byte read and byte write operations may
be executed from PDP-IS memory. Also such byte oriented NPR
devices as Mag Tape may make transfers directly to PDP-IS
memory.
Note: That the PDP-II
processor can access the PDP-IS memory
which is between the end of local memory and the 28K of address
space available to its address scheme.
A.

Output - PDP-IS Memory Bus

Will connect to MM15, MX15-A, and ME15 memories.
B.

Inputs

PDP-II: Modified UNIBUS with PA and PB used as 016 and 017 respectively.
It meets all other UNIBUS specs. Defined as
UNIBUS/18, input would have a lower address bound that could be
fixed to any 4K multiple address O-120K. This would be specified as jumpers. Note that only 8K and 12K of local memory
will be supported by diagnostics and systems programs. Hence,
the maximum commonly addressable memory (11 processor) will be
20K or 16K. An upper limit would be provided as l24K.
The addresses presented from the PDP-II are relocated t9 prevent
location 0 being the same physical address on each machine.
The PDP-II will be able to be relocated by 4K increments to 124K.
Local PDP-II memory is restri~ted to 4 increments.
Note that any "write" operation to a common memory location by
8 bit or 16 bit UNIBUS devices causes PDP-IS data bits 0 and 1
of the location to be forced O.
PDP-15: Standard 15 Memory Bus Interface - no upper and lower
bounds. No relocation. Emphasis is on minimum delay through
multiplexer for this port.

18.

If both processors request at the same time, PDP-IS will get use
of the memory. When requests are not simultaneous, a first come,
first served mode operates. Practically, all this means is that
the 15 and 11 will alternate access to common memory except under
the special conditions described above. NOTE: No local memory
is provided on the PDP-IS.
Bus Loading:

MXlS-B •••••.•••• 2 PDP-IS memory bus load
Drives 4 PDP-IS memory bus loads
DRIS-C/DRII-C .•• 1 Unibus Load
1 PDP-IS I/O bus load

Power: (Steady State)
UNDCHANNEL 15 (no peripherals) .• 5 at 11SV
2.SA at 230V
Voltage:
Frequency:

115 Vac : 10% or 230 Vac + 10%
+
50 - 2 Hz or 60 + 2 Hz

o
Environmental: Temperature •.•.•.•••.... lO to SOOC
Relative Humidity ..••..• 20% to 95%
UCIS Cabinet Dimensions:

Unibus Compatability:

Memory Cycle:

Depth: •.•. 30in (0.76m)
Width: •..• 21 in. (0.S3m)
Height: .•. 72 in. (1.83m)
Weight: .•. lSO Ibs. (70 kg)-not including peripherals.

Can be used with any PDP-II family processor that does not use parity. On
those systems with parity, the parity
must be disabled.

MXlS-B normally adds 200 ns to both the PDP-IS
and the PDP-II cycle times.

DMA Facility to Common Memory:
Maximum transfer rate •...• 41SK words/sec
Worst-case latency .•••••.• 6 ps (no DCH transfers
in PDP-IS)
12 ~s (DCH transfers
in PDP-IS)
Average latency ..•..••..•. 2.S ps
DMA Facility to PDP-II/OS Local Memory:
Maximum Transfer rate .•.•• l million words/sec
Worst-case latency ••...... 7.2Fs
Average latency ••.••.•..•. 2.5 ps
19.

SYSTEM CONFIGURATION
The UC1S cabinet will replace the curent disk cabinet immediately
to the left of the PDP-IS processor.
The increased spacing will require longer I/O or memory bus
cables in some installations.

DRlS-C
Interrupt Link
MXlS-B
Memory Multiplexer
RKOS
1.2 million word
Cartridge Drive

Reserved for
2nd RKOS

• [
• [

----.

]

ett ~ 1 : ~ !O~

•

PDP-II/OS with
8-l2K of local memory
2 small peripheral --------~••
slots slots
and 3 system
unit

1~~~~~~~~~1m~~-'''''''.,r-''''~
~

Reserved for
BAll peripheral-----------~..
~
expander box

Figure 9

20.

SYSTEM RESTRICTIONS
RKOS (RKll) Disk Pack Capability
The 18 bit RKll disk pack will not be able to be read by RKII-C
or RKII-D system (16-bit only systems).
This means that data bases and PDP-II files created on 18-bit
RKll systems may not be taken directly to an PDP-II only system. The transfer medium for such a transfer would have to be
Mag Tape.
This situation was chosen to make RKII-C and RKII-D packs compatible
(i.e .••.• all PDP-II only systems).
Memory Limits
UNIBUS NPR devices can access a maximum of 124K. The amount of
shared memory available to UNIBUS NPR devices is 124K less the
amount of local memory. In a "normal" configuration the PDP-II/OS
would have 8K of memory, in which case the available PDP-IS memory would be limited to l16K. This limit is due to the fact that
UNIBUS/18 peripherals must have access to all memory. The maximum memory of the 11 without some relocation option would be 28K.

Note: That the PDP-II with 8K of local memory can only address
the lowest 20K of common memory to access Task Control Blocks
set up by the PDP-IS.
I/O Latency
Multiport memories always have increased worst case latency
over a single port-non-competitive situation. This system
is no exception. The PDP-II
normally gives an "NPR break"
a worst case latency to BSSY of 7.0 usec. On this system, we
must add to that time, the time it requires the PDP-IS to do
three I/O memory cycles (5.0 usec.). The worst case latency
is, hence, 12.0 usec.
CAF/RESET Limitations
The following timing considerations are of interest to programmers:
A RESET instruction may cause the PDP-IS to incorrectly read
the API address. The Console RESET and CAF instruction may
violate UNIBUS specifications. Hence, random "initialize"
pulses may cause system malfunctions. The following guidelines must always be followed;
21.

CAF must not be executed while there is a Task Control Block
Pointer (TCBP) waiting to be read by the PDP-lIn

RESET must not be executed while there are API requests
pending for the PDP-IS.

RESET must not be executed if there is any NPR activity on
the UNIBUS. All active NPR devices must be shut down in
a power fail sequence prior to executing RESET.

22.

PDP-IS UNICHANNEL OPTIONS

UClS-HE

Peripheral Processor: 11/05 or 11/10-NC
or - SA, 2 DRll-C, DR15-C, MX15-B, DDll-B,
KYII-JH, H950, 115V.

8K Local Memory

UClS-HF

Per~pheral

Processor: 11/05 or 11/10-ND
or - SB, 2 DRII-C, DR15-C, MX15-B, DDII-B,
KYll~JH, H950, 230V.

8K Local Memory

UC15-HK

Peripheral Processor: 11/05 or 11/10 - NC
or - SA, 2 DRII-C, DR15-C, MX15-B, DDII-B,
KYll-JH, H950, MMII-K, 115V.

12K Local Memory

UC15-HL

Peripheral Processor: 11/05 or 11/10-ND
or - SA , 2 DRII-C, DR15-C, MX15-B, DD1I-B,
KYII-JH, H950, MMII-K, 230V.

12K Local Memory

RK15-HE

RK05-AA, RKII-E, UC15-HE, 115V, 60Hz

RK15-HF

RK05-BB, RKII-E, UC15-HF, 230V, SOHz.

RK15-HH

RK05-AB, RKll-E, UC15-HF, 230V, 60Hz.

RK15-HJ

RKOS-BA, RKII-E, UClS-HE, 11SV, 50Hz.

RKlS-HK

RK05-AA, RKII-E, UC15-HK, 11SV, 60Hz.

RK15-HL

RK05-BB, RKII-E, UC15-HL, 230V, 50Hz.

RK15-HM

RK05-AB, RKII-E, UC15-HL, 230V, 60Hz.

RK15-HN

RK05-BA, RKII-E, UC15-HK, 115V, 50Hz.

15/76-DE

KP15, ME15-EA, LA30-CA, PC15, KE15, KW15,
TC15, TUS6, RK15-HE, 115V, 60Hz.

lS/76-DF

KPlS, MElS-EB, LA30-CD, PC15-A, KE15, KWlS,
TC15, TU56, RK15-HF, 230V, 50Hz.

15/76-DK

KP15, ME15-EA, LA30-CA, PC15, KE15, KW15,
TC15, TU56, RK15-HK, 115V, 60Hz.

15/76-DL

KP15, ME15-EB, LA30-CD, PC15-A, KE15, KW15,
TC15, TU56, RK15-HL, 230V, 50Hz.

lS/76-ME

KPlS, ME15-EA, LA30-CA, PClS, KElS, KWlS,
TC59-D, TUIO, RK15-HE, 115V, 60Hz.
23.

lS/76-MF

KPlS, MEIS-EB, LA30-CD, PClS-A, KElS, KWlS, TCS9-D,
TUIO, RKIS-HF, 230V, 50Hz.

lS/76-MK

KPlS, MEIS-EA, LA30-CA, PClS, KElS, KWlS, TCS9-D,
TUIO, RKIS-HK, 11SV, 60Hz.

lS/76-ML

KPlS, MEIS-EB, LA30-CD, PClS-A, KElS, KWlS, TCS9-D,
TUIO, RKIS-HL, 230V, 50Hz.

NOTE:

For further information and extra copies of this
manual please contact the PDP-IS Marketing Department at the following address:
PDP-IS Marketing Department
Digital Equipment Corporation
200 Forest Street
Marlboro, Massachusetts
01752

24.