Digital PDFs

XX-3EB8D-D6

November 1975

102 pages

Original

6.8MB

Document:	MP-00013 XM15 EngrDrws
Order Number:	XX-3EB8D-D6
Revision:
Pages:	102
Original Filename:	http://bitsavers.org/pdf/dec/pdp15/XVM/MP-00013_XM15_EngrDrws_Nov75.pdf

OCR Text

(

XM15
Engineering Drawings
Digital Equipment Corporation

The material herein is ~formation purposes only
and is subject to chan"hout notice Digital
Equipment Corporation~assumes no responsibility for
any errors which may appear herein.

These drawings and specifications herein are the
property of Digital Equipment Corporation and shall
not be reproduced or copied or used in whole or in
part as the basis for the manufacture or sale of items
without written permission.
Copyright ° 1975, Digital Equipment Corporation

''THE MATE"'AL tlEREIN IS FOR INFORMATION PURPOSES ONLY
AND IS SUBJECT TO CHANGE WITHOUT NOTICE, DIGITAL EOUIPMENT
CO"I'OAATION ASSUMES NO RESPONSIBILITY FOR ANY ERRORS
WHICH MAY AI'I'EAR HEREIN,"

FIELD .\fll
~t'AINTENAa.c~ ft~IIr.\.1T ~~-n
1\.1 .Le; r-1f\UU'\.I
y
~U;;;

"THIS OAA'.'II!NG AND SPECIFICATIONS, HEREIN, ARE THE I'AOl'ERTV 01' DIOITAL IQUI'MINT CORPORArlON
AND SHALl- NOT BE REPRODUCED OR COPIED OR USED IN WHOLE OR IN 'ART AI THI IAIII I'OR THI MANU.
FACTURE OR SALE OF ITEMS WITHOUT WRITTEN PERMISSION. COl'YAIQHT ()
DIGITAL IQUIN,NT
CORPORAT'ON,"

1915 .

TABLE OF CONTENTS
B-TC-XMI5-.0-9
B-DD-XMI5-.0
D-UA-XMIS-.0-.0
A-PL-XMI5-.0-.0
D-UA-M7172-.0-.0
D-CS-M7172-.0-BCCI
D-CS-M7I72-.0-BCC2
D-CS-M7I72-.0-BCDI
D-CS-M7172-.0-BCD2
D-CS-M7172-.0-BCA
D-CS-M7I72-.0-BCT
D-UA-M7I73-.0-.0
D-CS-M7173-.0-PRS
D-CS-M7I73-.0-PMPS
D-CS-M7I73-.0-PML
D-CS-r.17173-.0-MPA
D-CS-M7173-.0-MPDI
D-CS-M7I73-.0-MPD2
D-CS-M7I73-¢-MPD3
D-CS-M7I73-¢-MPT,
D-UA-M7174-.0-fi1
D-CS-M7I74-¢-IPCl
D-CS-M7174-.0-IPC2
D-CS-M7I74-.0-IPPC
D-CS-M7I74-.0-IPCM
D-CS-M7174-¢-IPEP
D-CS-M7174-~-IPAM

D-CS-M7174-¢-IPPD
D-UA-M717S-¢-.0
D-CS-M717S-¢-MMAR
D-CS-M7I7S-¢-MMBR
D-CS-M7I75-.0-MMC1
D-CS-M7I75-¢-MMC2
D-CS-M7I7S-¢-MMC3
D-CS-M717S-¢-MMll
D-CS-M717S-¢-MM1.0
D-CS-M7175-¢-MMSM
A-PL-XMI5-¢-8
D-UA-M7176-¢-¢
D-CS-M7I76-¢-APIC

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XMI5 PRINT SET
TABLE OF CONTENTS
MEMORY PROCESSOR (XMIS)
MEMORY PROCESSOR (XMI5)
MEMORY PROCESSOR (XMI5)
15 MEM-UNIBUS INTERFACE
CONTROL 1
CONTROL 2
DATA ,0-8
DATA 9-17
ADDRESS REGISTER
TERMINATORS
MEMORY PORT
PORT REQ SYNC
PORT MSYNC & SSYNC
PORT MISC CONTROL
MEMORY PORT ADDRESS
MEM PORT DATA
MEN PORT DATA
MEM PORT DATA
MEMORY PORT TERMINATOR
IPF
REQUEST & START
CONTROL 2
PROGRAM COUNTERS
READ & WRITE COMPARITOR
EP ADDRESS WINDOW
ADDRESS MUX
FILE DA'I'A
MEM MGR
ADDRESS RECV & DECODE
BOUNDRY & RELOCATE REGISTERS
MODE CONTROL
TRAP , CO~ROL
INST DECODE
I AND I/O BUS DRIVERS
rOB RECV AND DECODE
SHARE REGISTER & ADDRESS MUX
XM15 SHIPPING LIST
API
API CONTROL

UNIT VARIATIONS
COVERED BY THIS
PRINT SET

XMIS-BA
XMIS-BB
XMlS-UJ
XMIS-UK
xr.llS-UL
XMIS-UM

ci
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Digital Equipment
Corporation

PRINT SET ORDER NO.
MP¢¢¢13

USED ON OPTION/MODEL

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PROJ. ENG.

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D-IA-7011502-0-0
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API REQ'S
PRIORITY LEVELS ¢-3
PRIORITY LEVELS 4-7
TEST REQUESTS
I/O BUS RECV
BUFFERED API CONTROL
CLK AND I/O MUX
I/O ADDRESS
I BUS DRIVERS
BUS XCVR
BUS XCVR
LOW VOLT DET
LOW VOLT DET
XM1S lOB & API DRIVERS
XM15 BUS1&2 AND EXT PROCESSOR CONN
MOL & lOB CONNECTORS
lOB & IBUS CONNECTORS
API CABLE TERM & CONN
WIRED ASSY (XM1S)
LOGIC POWER HARNESS
XM15 MEMORY PROCESSOR
XM15 CUSTOMER ACCEP~ANCE

K· WL . XM I 5 - 0 - W L

XM 15 NAME LIST

SIZE iCOoe

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SHEET2 OF

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-THIS DMWING NtD SPECIFICATIONS, HEAEItI, ARE THE PROPERTY Of' DIGITAL EQUIPt'.ttIT COItPO~IOM AND SHALL
lOT BE REPRODUCED OR COPIED OR USED IN WHOLE
IN PART AS THE BASIS f'OR THE tWruf'I.CTUn£ OR SALE OF
ITEHS WITHOUT DITTEN PERHISSION. COPYRIGHT C 1975
,DIGlTl.L tQUIPI«NT CO~POAATlO:.·

DD~lE<Cl0~V
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THIS IS PRINT SET I I· 1 [~

UNIT
NOTE:

VARIATIONS

FOR FIELD MAINTENANCE PRINT SET SEE:

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VAR
XM1S-BA
XMIS-BB
XMIS-UJ
XM1S-UK
XM15-UL
XM1S-UM
XM1S-UN

MEMORY
MEMORY
MEMORY
MEMORY
MEMORY

XMIS-UP
XMI5-WJ
XMI5-WK
XMI5-WL

MEMORY PPOCESSOR (XM 15)
MEMORY PROCESSOR ,'XMI5~
MEMORY PROCESSOR XMI5)
MEMORY PROCESSOR l XMI5
MEMORY PRQCESSOR XMI5
MEMORY PROCESSOR XMIS)
MEMORY PROCESSOR XMI~l
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MEMORY PROCESSOR XMI~

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PROCESSOR (XMI5)
PROCESSOR (XMJS)
PROCESSOR l X MIS)
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MEMORY PROCESSOR(XMIS)
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ASSY 19 INCH
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861-E POWER CO~~ROL ASSY (24~V)
UNIT ASSY BAll-K (125V)
UNIT ASSY BAI1-K (240v)
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2
3
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45
46
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49
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51
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1204826
1209175

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111
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17
18
19
20
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1
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MEMORY EXPANSION 32K
MEMORY EXPANSION 32K

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MEMORY PROCESSOR (XMI5)

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D-UJI.-M7176-0-~

32
33
34
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36
37
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D-CS-M966-YA-1
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IPF
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BUS DRIVER
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CP TERMINATOR CARD
BUS XCVR
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39
40
41
42
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28
29
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MAVNARD. MASSACHUSETTS

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9/26/75
DATE
ENG ~ L-H.-P....... ___
DATE
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PHL TRUSS lID #10-32 X 1
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59
60
61
62
63
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57 1211825
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58 C-IA-7008288-8F-~
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Fred Doll
6/21/76
Fred Doll
6/21/76

ITEM DWG NO./ PART NO.
68

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C-UA-MF15-WE
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MEMORY EXPANSION (32K)
MEMORY EXPANSION (64K)
MEMORY EXPANSION (64K)

3 3
30 30 30 30 3
2
2
2
2 2
2
2 2
1
1 I 1 I
1 1 1
41 41 41 41 41 41 41 41
35 35 35 35 35 35 35 35
8
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TITLE
MEMORY PROCESSLR (XMI5)

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PARTS LIST
Fred Doll

P~TF.

i£ NG

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foRu.;

IDATE

6/21/76

Doll

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C-PL-7006501-10-0
E-UA-S61-0-0

II 1

BASIC CABINET ASSY 19 INCH
86~-0 POWER CmnROL ASSY (125V)

1 i

;--_+I--~~--+--+--+--4

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6

D-UA-BC08A-7-0

C-UA-MF15-UO-O

MEMORY EXPANSION 32K

D-AD-7011524-0-0

WIRED ASSY (XMI5)

~UAL

CABLE

C-IA-700B2B8-3F-O

CABLE ASSY (3-1/2 FEET)

0-IA-7407349-1-0

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NUT J<EPS
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ITEM

DWG NO- / PART NO.

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1 I

1 1

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11 1

4
1

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1 I
NUMBER

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9006653
0-IA-7C11827-0-0
1211825

WASHER FLAT ,375 0.0. X .156 I.D.
CONTROL PANEL ASSY
SLIDE, CHASSIS, TILT 3 POSITION

6
1
1

6
1

58
59

C-IA-700B288-BF-0
0-UA-BC08A-8-0

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60
61

A-DC-7407314-0-0
A-OC-7406574-0-0

FAN HOUSING DECAL
DECAL

FEE~1

BCOBA CABLE (8 FEET)

1
1

- 1 - 1 - 1
1

9107370-22

WIRE U4 AWG RED

A/I ~/I lA/F IA/F

9007930
C-UA-MFlS-WA

SOLDERLESS CONN HO
MEMORY EXPANSION ( 32K)

65
66

C-UA-MF15-WB
C-UA-MF15-WC

MEMORY EXPANSION (32K'
MEMORY EXPANSION (32K)

1
1

TITLE

1
1

IASSV NO.
D-VA-XM15-0-0
ME~10RY

PROCESSOR (XM15)

ISH E ET

fJrlpLl
1
015T

IR~V

NUMBER
XM15-0-0

fCC NO

DEC 16-(J~5)-IOJI-Ng70

DIGITAL EQUIPMENT CORPORATION

QUANTITY / VARIATION

MAYN PA'RTsS1CIST E T T S
SECTION

CHECKED
DATE
PROD
DATE

ISSUED SECT.

!iI 3:Il:1

DESCRIPTION

LI"I

MADE BV
DATE
ENG
DATE

til

1
LI"I

... ... '" ...X
LI"I

ITEM

Frea uoJ.J.
6/21/76
Fred Doll
6/21/76

C-UA-MF15-WD

9107646

2 2 2 2
A/ tAli A/I All

9107679
910767)-6

TUBING ZIPPER I" BLK
POWER CORD #14 AWG

All lAll tAn An

C-CA-MFlS-WE
C-UA-MF15-WF

O-UA-M7172-0-0

15 MEM-UNIBUS INTERFACE

D-UA-M7173-0-0

MEMORY PORT

1
1

SECTION
ISSUED SECT.
DESCRIPTION

i !i1 :sg:1

I
LI"I

LI"I

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...z: ....

MEMORY EXPANSION
( 32K)
MEMORY EXPANSION (64K)
MEMORY EXPANSION (64K)

1
1

D-UA-M7174-0-0

IPF

D-UA-M7175-0-0

MEM MGR

31
32

D-tJA-M7176-0-0
D-CS-M966-YA-l

API
POP15 MEMORY BUS TERMINATOR

33
34

D-CS-M622-0-1
0-CS-M621-0-1

BUS DRIVER
DATA BUS DRIVER

L
4

D-CS-M910-0-1

CP TERMINATOR CARD

36
37

D-tJA-M5921-0-0

BUS XCVR

D-CS-M930-0-1

Bes TERMINATOR

38
39

0-UA-G8270-0-0
9007651

30 30 3'] 30

9006565

LOW VOLT DET
1-i.I\SHER EXT TOOTH #10
NUT, KEPS, HEX #10-32

9008887

STRAP

9007786

NUT

BRAID WITH TERHINALS

CHECK~D

DATE
PROD
DATE

DWG NO. / PART NO,

COVER PANEL 5-1/4
TUBING, EXTRUDED 5/B" BLK

41 41 141 in

TINNER'1AN UO-32

43
44

9006074-3
SCR PHL TRU3f" HI) #10··32 X 5/8
9006074-2
SCP, PHL FLAT HD t10-32 X S/8
TITLE
IASSY NO.
MEMORY PROCESSOR {XM1~j
D-UA-XI-H 5-0-0
ISHEET

SOLOERLESS #6

XI- 15-0-0

63
64

QUANTITY /VARIATION

55
56
57

4 4
12 12 '12 '.2
4 4 4 4
1

~~~ ~~ORM

JU~lPER,

1204826
1209175

I 015T I

PARTS LIST

MAYNARD. MASSACHUSETTS

6/21/76
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6/21/76

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DIGITAL EQUIPMENT CORPORATION
Fred Doll

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VT48

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LOGIC POWER
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DIGJTAL EQUIPMENT CORPORATION

ENGINEERING SPECIFICATION

MAYNARD. MASSACHUSETTS

nnE

ENGINEERING SPECIFICATION

-TiTlE

XM15 MEMORY PROCESSOR

REV

DESCRIPTION

XM15 MEMORY PROCESSOR

DATE 10-30-75
1.0

T;,e primary function of the XM15 is to receive and process
all requests made to memory.
In addition, the XMIS provides
mounting space and power for the Automatic Priority Interrupt
(API) module.

REVISIONS
CHG NO
XM15-

ECO CHANGE

pjOoI

DATE

ORIG

APPD BY

GENERAL DESCRIPTION

CONTINUATION SHEET

DATE

F. DOLL

The XMlS contains power, I/O bus interface, memory bus
interface, and various control functions for the operation
of the M7l76 Automatic Priority Interrupt logic, the M7l7S
Memory Management logic, the M7l74 Instruction Pre fetch
logic, and the M7l73 Memory Port. The various XMlS functions
are discussed in the following paragraphs.
1.1

Individual Module Description
M7l76 Automatic Priority Interrupt (API)
The M7176 API provides eight levels of priority interrupts
for the XVM System. Of these eight levels, the upper four
are assigned to I/O devices and are initiated by flags
(interrupt requests) from the devices. The lower four levels
are programming levels and are initiated by software requests.
High data rate or critical devices are assigned to high
priority levels and can interrupt slower device service
routines.
M7l76 holds the lower device interrupt request
until it can be serviced. The source of the interrupt is
also directly identified, eliminating the need for flag
search routines.

TABLE OF CONTENTS
1.0
1.1
1.2

General Description
Individual Module Description
System Interconnections

2.0
2.1
2.2
2.3

System Specification
Physical Specification
Environmental Specification
Unibus Specification

3.0
3.1
3.2

Programming Specifications
lOTs
Register Functions

4.0
4.1
4.2

Cable Configurations
Input Cables
Output Cables

5.0
5.1
5.2
5.3

Maintenance
Equipment Required
Preventative Maintenance
Adjustments

APPD

DEC

...-rI'"
.-1: I

/,~

A self-starting, high resolution (18 bits) task accounting
clock is also contained on M7l76. The accounting cluck
provides essential data that allows accurate appropriation
of machine cost among multi-users of the XVM System. A
single lOT reads and clears the contents of the task accounting clock register.
M7l75 Memory Management
The M7l7S provides the XVM System core memory with protect
features to trap HALT, lOT, OAS and chained Execute inst-rllcti0ns and the addressing of a non-existent memory bank.
A boundary register and two relocation registers, and
associated control logic, are used to establish the limits
of the user's program and relocate the program upward in
memory from the real machine location.

NUMBER
XM15-0- 5

. /

16·13921 101.,..911

DEC FORM NO
ORA 10'

ORA 107

ENGINEERING SPECIFICATION
TiTlE

NUMBER
XMIS-0_5

CONnNUATION SHEET

ENGINEERING SPECIFICATION
TiTlE

XM15 MEMORY PROCESSOR

selection of indirect addressing with 15, 16, or 17 bits:
relocation disabling:

CONTINUATION SHEET

multi-processor configurations, memory interleaving and
distribution, and improved IPF performance.
M7l72 Bus Interface
The M7l72 Bus Interface receives, drives, and de-skews the
processor memory bus. M7l72 converts processor address and
control information to signals compdtible to the XM15 and its
memory bus and communicates with the memory port and IPF.
Temporary storage for the current memory read data is also
provided.

In addition, there are software controlled modes which allow:

SHEET _2_ OF ~

XM15 MEMORY PROCESSOR

The boundary register functions in two modes: prutect and
relocate.
In the protect mode the boundary reg1ster sets
the lower memory limit for the user's program.
In the
relocate mode the boundary register establishes the upper
memory limit for the program, while the lower limit is
established by the first relocation register.
The second
relocation register, called the share register, provides
for memory segmentation in a multi-user environment.

DEC 16-1l81)-1022-Nl10

Internal Memory
The XHlS contains either 32K of MFlS core memory or 24K of
HE15 core memory within the same BAlIK mounting box.

user lOT enabling:

write protection of the shared segment, and

specifying the shared segment length.

1.2

SYSTEM INTERCONNECTIONS
XM15 Bus

M7l74 Instruction Pre fetch (IPF)

The XM15 Bus is the bus between the memory port in the XM15
and the internal and external memory.
If the optional second
port is included in the XH15 there will be two independent
XM15 buses.

The M7l74 IPF provides the XVM System with improved
instruction fetch times by pre fetching presumed instructions
from memory.
IPF does this by monitoring requests to memory
and synchronizing itself to the current instruction address.
The IPF then attemps to pre fetch up to four locations ahead
of the processor. Simultaneously, the IPF continues to
monitor memory references and, whenever possible, provides
the requested instructions directly from its internal
register file.
Provisions to pause during operand and/
or defer cycles to minimize memory conflicts are also provided
by the IPF. Whenever the IPF fails to supply the requested
instruction, or if it senses that the current instruction will
cause the program to break sequence, the I~F will abort the
current contents of its register file.
The IPF may be enabled
and disabled under program control or manually by means of a
switch on the M7l72 Bus Interface module.

The XM15 Bus connects all memory to the XM15.
In addition,
the XMl5 Bus may be connected to the external processor
input of another Y.VM System to form a multiprocessor system
with two or more XVMs. Except for the absence of bus
arbitration signals, the XM15 Bus is compatible with the
Unibus.
CPU and IPU-to-Memory Bus (MDLs)
The central processor and I/O processor each asynchronously
access memory over the same MDL bus. The priority structure
concerning which processor's request is sent to the XMlS is
de~~rmined by the processor memory port switch.
The I/O
processor is given first priority. The MOL bus consists of
18 bi-directional lines over which address and then data
information is transmitted to and from the XM15. Various
control signals are on this bus as well as provisions for
interfacing the optional floating point processor (FPlS).

M7l73 Memory Port
The M7l73 Memory Port arbitrates requests for memory access
directly from the XVM, IPF, and the external processor input.
M7l73 drives, receives, and de-skews the XM15 memory bus. On
the external processor input, M7l73 has upper and lower limit
address selection, negative address relocation (XV200
Unichannel systems), and "address float" which allows positive
address relocatior.. The IPF and XVM inputs do not provide
boundary or re!ocation selection.
In addition, M7173 performs
four way memorj interleaving functions.
XM15 may house an
optional second memory port to allow greater flexibility in

IPU-to-I/O Devices (I/O Bus)
The I/O processor communicates with all devices over a common
I/O Bus which contains bi-directional data lines, address line
enable, reque~t, and grant lines for API and data channel, and
others such as program interrupt and skip request.

--------------------------------~~~~~--~~~=---~~~
I~~
I SI1E ICODEI
NUMBER
I RAEV
______________________________~M~~s~p__~I~x~M~I~S_-~0-~5~----~~~~
~~~ rg,RII NO

DEC 16-1lI1)-I022-N370

SHEET _3__ OF 1_0__

DEC FOAM NO
DRA 108

DEC 16

UIII- 1022-N370

SHEET _4_ OF ~

ENGINEERING SPECIFICATION

ENGINEERING SPECIFICAnON

CONnNUAnON SHEET

XM15 MEMORY PROCESSOR

TITLE

nnE

XM15 MBIIORY PROCESSOR

Console-to-CPU (I Bus)

3.0

Progr. . .ing Specifications

The indicator bus contains bi-directional lines to transait
information to the lights on the console and switch infor.ation from the console to the central processor. Several
control lines are also located on the cable. The ME15/MF15
memory do~s not use the IBus.

3.1

lOTs
701701
701702
701704
701741
701742
7017 ....
700032
700024
701724
701762
701764
703302
707742
701104
7033 ....
705501
705512
705521
705')22

API to Central Processor Bus
Because the XM15 contains several internal options which deal
with the operation of the central processor, a special cable
(API cable) is required so that the option may utilize these
internal central processor signals.
2.0
2.1

SYSTEM SPECIFICATION
Physical Specification
The XM15 consists of a' (13) thirteen slot hex' backplane,
an M7l72, M7l73, M7l74, M7l75 and M7l76 module. In
addition, there are several single height modules and
interface cables. The backplane is mounted in a BAlIK
expander box. 32K of MF15 or 24K of ME15 memory may also
reside in the BAlIK. The XM15 is located below the console
of the XVlOO or in a standalone cabinet for add-ons.

2.2

2.3

3.2

IIPSIt
IIPCV
IIPLD
IIPSIII:
IIPEO
JllPCNE
RDIIII
LDIIII
IIPLR
RDCLIt

IPOPF
CAP'
RES

DBIt

DBR
SPI
RPL

EBI
OBI

COImNUAnON SHEET

Skip on .e.ory protect violation flag.
Clear .e.ory protection flag.
Load boundary register.
Skip on non-existent .e.ory flag.
Enter User Mode.
Clear non-existent ...cry flag.
Load . . register into AC.
Load . . register.
Load relocation register.
Load CLIt into AC.
TUrn the IPF off.
Clear all flags.
Restore User Mode.
Debreak API Level.
Debreak and Restore.
Skip on PLa inactive.
Load PLs into AC.
Enable breaks.
Disable breaks.

Environmental Specification

A ten bit register which when used in protect mode, sets the
lower aeaory limit in increments of (400 a ) for the users
prograa. When in relocate mode the bounaary register
establishes the upper memory limit for the user program.

50 0 C input air

Operating Temperature:

10 0

Humidity:

5 - 90% relative (noncondensing

Input Voltage:

90-132 Vac, 115 Vac nominal
180-264 Vac, 230 Vac nominal

Relocation Register

Frequency:

47-63 HZ, 3 phase cabinet
power

A ten bit register which is added to the CPU address bits 0-9,
when in user mode, creating the actual memory address. This
register is not used in protect .ade.

XM15 Power Required:
(does not include
memory)

5 V t 5% including ripple
25A max.

Clock Register

Contains the count of a free running oscillator which has a
10 usec resolution. The clock is disabled when API level
0-3 are being processed and is cleared after being read into
the AC. OVerf~ow is not prp.vente~ and will occur every
2.62 seconds.

Unibus Specification
Standard Unibus rules must be followed concerning its
length and loading when connecting to the external processor
input (EPI). The EPI represents one bus load when the one
port (M7l73) configuration is used and two bus loads when
the XM15 is dual ported.

NUIIBER
DEC FORM NO DEC 16-(3811-1022-N370
DR.ll0B

---- ----------- ..- .....-.- .. -- ..... ......_. .."' ,.
.....

__:,._,__ ~_~~= . _.~~_=--.

ENGINEERING SPECIFICATION
TITlE

SHEET _5_ OF ~

___

DEC FORM NO DEC 1.,:aall-10Z~170
.::D.::RA:...:..:10:.:.:..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ .~.~ ~

ENGINEERING SPECIFICATION

CONTINUATION SHEET

TITLE

XtU5 MEMORY PROCESSOR

REV

XMlS-0-5
SHEET _6_

OF ~

CONTINUATION SHEET

XM15 MEMORY PROCESSOR

IPOFF Register

R DIS - Relocate Disable (Bit 0)

A one bit register which is loaded with AC bit 17. When set
the IPF is disabled until the bit is cleared by either the
lOT lPOFF and AC bit 17 on a 0 or a CAF being issued.

When set, inhibits relocation and all protect violations
(except NEXM) while in User Mode. This allows the use of
G Mode without the protection or relocation features. When
bit 0 is clear, normal relocation and protection occur except
as determined by Share Mode and lOT Enable.

Non-Existent Memory Flag
Set when non-existent memory is referenced while in user mode.
Cleared by CAF, MPCNE or DBR.
Memory Protect Flag
Set if a privileged instruction is detected, an address
boundary violation occurs, a non-existent memory reference
occurs or a privileged write modification is attempted while
in user mode.

GM - G Mode (Bits 1, 2)
The G Mode is entered whenever the system is in User Mode and
the GO, Gl bits (MM bits 1 , 2) are set to binary 1, 2, or 3.
The MM signals the CPU to pass 18 bits of any defer address
and causes PC bits 0-2 to be stored during a JMS instruction
rather than L, BM and UM. While in G Mode, Gl, Gl select
the address width through M7l7S.
GO, Gl = 00 = 01 = 02 = 03 -

Privileged instructions are the following =
(liLT, OAS, lOT, XCT of XCT, CAL).

normal mode, not G Mode
G Mode with 16 bit defers
G Mode with 18 bit defers
G Mode with 17 bit defers

User Mode
A one bit register which is set by the lOT MPEU and is cleared
if the memory protect flag is set or an interrupt occurs. The
bit can be restored by issuing a DBR lOT followed by an
indirect memory reference. When User Mode is true, the
memory management features which are selected, are turned on.

GO, Gl bits also determine the virtual position of the
Shar~d Address Space (SAS).
IP - lOT Permit (Bit 3)
Bit 3 of the MM, which when set, allows execution of lOTs
while in User Mode.

Memory Management (MM) Register
WP - Write Protect (Bit 4)
The MM register contains mode control bits, the Share Address
Register (SR), and the Segment Length Register (SLR). The
MM register is reau to the AC by lOT 700032 and is loaded
from the AC by lOT 700024. MM register bit assignment are
shown in the following figure and are described in the
following listing.
101l2131415T 6 7
SLR

SH - Share (Bit 5)
Bit 5 of the MM enables Share Mode when set.

1 84

Bit 4 of the MM, which when set, write protects the External
Shared Address Space (ESAS). A protect violation and trap
occurs if an ESAS write is attempted.

SHARED ADDRESS

SLR -

Segment.Lengt~

These bits determine the size of the external shared
segments. Always equals ISAS + ESAS.

M7l75 Memory Management (MM) Register Format

1-DEC FORM NO DEC
DR'" 108

SI1E ICODE I
I
1& ·,3811-1020"""370

NUIIBER

NUMBER

I XM15-0~S-

SHEET _7_ OF ~

XMlS-O-S
DEC FORM NO DEC 16-'3.1)-1022 .... 370
OR.ll0.

SHEET _8_ OF .-!!!-

E-N-:G=-:'-:IN~E:":E:-:n~IN~G-S~P~~-C-I-fl-C-A-i-IO-~-~--[-::-;::]----C-O-NT-'N-UA-T-'O-N-SH-E-El~>.......

CONTINUATION SHEET

ENGINEERING SPECIFICATION
TITLE XM15 MEMORY PROCESSOR

TITLE

2.0
Bits 6, 7 I : 0

= 1000 a (S12 l0 ) Locations

XMlS MEMORY PROCESSOR
OUTPUT CABLES
From

Function

= 1 = 2000 a ( 1024 10) Locations
.. 2 = 10000a (4K) Locations
.. 3 = 20000 a ( aK) Locations
Shared Address Register - SA (Bits a - 17)

Device

Loc

Device

EXT
PROCESSOR

XMIS

A/BlO

TO NEXT DEVICE

MEM BUS 1
MEM BUS 2

XMlS
XMIS

C/DlO
C/OI3

MEMOhY
MEMORY

XMl5

AB03/04

BAlS

Cable

Loc

BClIA,
A/BOI
A/BOI

BCllA
BCllA

I/O BUS

Tho Shared Address Register (bits a - 17 of the MM) contains
the relocation factor for the share address.
It points to
the position of ESAS - 2S6 in core.
SA bits a-17 are added
to the CPU address bits S-9.

XVM SYSTEM

PDPIS SYSTEM XMl5
BA,DWI5
ORIS
UC & RP or
RF

XM1S Cable Configurations

ABOl/02 BC09B-4
ABOI/02 BC09B-IO
BC09B-12
BC09B-lS
BC09B-2S

BAIS
OR,RP,RFIS
AB03/04 TCl5
TCl5

AB03/04

1.0

INPUT CABLES

1.1

No FP15

NOTES:

Function

If the external processor bus does not continue from the XMl5
it will be terminated in XMl5 slot A/BIO with a M930 module.
BUS DC LO will be grounded if no EXT PROC.

MOL
MOL
API CONTROL
I BUS
I/O BUS
1.2

- Loc --To

From
Device

Loc

Device

Cable

AOS
BOa
EOS
DOS
ABOl/02
A/B 13

J02
XMIS
KPlS-C
.T03
XMIS
KPlS-C
H03
XMIS
KPlS-C
H02
XMlS
KP1S-C
MN02/03
XMlS
KP1S-C
EXTERNAL PROCESSOR XMlS

BCOaA-7
BC08A-7
BC08A-7
7006437-8
BC09B-7
BCllA

With FP15
Frdm'

Function

-To

Loc

Cable

Device

Loc

Device

MOL
MOL
API CONTROL
I BUS
I/ 0 BUS

KPlS-C
KPlS-C
KPlS-C
KPIS-C
KP15-C

J02
J03
H03
H02
MN02/03

FPlS
FPlS
FPlS
XM15
XMIS

H29
H30
H3l
DOS
ABOl/02

BC08A-5
BC08A-5
BC08A-S
7006437-8
BC09B-7

MOL
MOL
API CONTROL

J29
FPlS
J30
FPlS
FPlS
J3l
EXTERNAL PROCESSOR

XMl5
XMl5
XM15
XMlS

A08
B08
E05
A/BI3

BC08A-7
BC08A-7
BC08A-7
BCIlA

-- ---

The memory bus is terminated at the last memory by an M930 in
slot A/B09.

Memory on the processor rear door should be positioned last on
the XMIS bus eliminating the necessity of exiting the rear door
with the XM15 bus for ease of cabling and minimizing bus length.
XMlS

bus #2 follows the same rules as bus #1 when present.

S.O

MAINTENANCE

S.l

Equipment
The following equipment is helpful in troubleshooting problems
in the XM15.
Tektronix 4S3 oscilloscope or equivalent
Extender boards

5.2

The XMlS has no mechanical parts requiring regular service.
Therefore, only standard processor maintenance procedures are
necessary to insure reliable operation.

5.3

Refer to Chapter 7 of the Maintenance Manual for adjustments.

IA I

NUMBER

sllE

XM15-0- 5
DEC FOR .. NO
ORA 108

DEC 16-(381)-1022~370

SHEET __9_ OF

DEC FORrA NO
ORA 108

DEC 16'-(381)-1022-N370

CODE I

NUMBER

XMI5-0-5

sH E ET ---1..Q. 0 F --1.Q...

MAYNARD. MASSACHUSETTS

TITLE

ENGINEERING SPECIFICATION
TITLE

DATE

ENGINEERING SPECIFICATION

DIGITAL EQUIPMENT CORPORATION

CONTINUATION SHEET

XMls Customer Acceptance Procedure

11-6-75

XMls Customer Acceptance Procedure
REVISIONS

REV

DESCRIPTION

IcHG NO

ORIG

DATE

APPD BY

DATE

The following steps will be followed to accept and insure that
all necessary paper work, diagnostics, etc., are included with
the XMls.
HARDWARE AND SOFTWARE
Reference prints A-PL-XMls-O-8 for necessary hardware and
software.
PROCEDURE

ENGJ //!
/rI<7,L..·~
. ,'~"1.2.-1019-N911

IAPPD - ;

I
"

NUMBER

XMls-O-6

Visually inspect for loose bolts, power plugs, modules,
pinched cables or bent pins.

Check that all fans'are working properly.

Check that all console functions work correctly.

Load and run all diagnostics. Appendix I shows diagnostics
and run times. The IPF (M7174) should be "ON".

Load and run system exerciser.

If operating system supplied: one pass of the O. S.
acceptance test.

When all diagnostics have been run, acceptance of the
XMls system is complete.

S11E ICOsDpEI

REV

NUMBER
I XM15-0-6

DEC FORM NO DEC 16-(llll-l02~l70
ORA 101

SHEET _2__ OF __
3_

ENGINEERING SPECIFICATION
TITLE

REV

CONTINUATION SHEET

XMls Customer Acceptance Procedure
APPENDIX I
All diagnostics ~lst run error free.

Program

Run Time

Extended Memory Address Test

Passes/Bank

Extended Memory Checkerboard

Passes/Bank

Instruction Test Pt. 1

10 Min.

Instruction Test Pt. lA

10 Min.

Instruction Test Pt. 2

10 Min.

I/O Test (API)

15 Min.

Memory Protect Test

2 Passes

Memory Relocate Test

2 Passes

XM15 Memory Management Test

1 Pass

NUIIBER

XM15-0-6

REV

SHEET _3_ OF __
3_

Thl. dr.wln• • nd apeciflc.tlo" •. M.,..in. Ir, t'" prop .
• rty of Ol,ltat EQulpm.nt Corporat1o" Ind ~III not be
reproduced or copied or uMd H' ",,1'\01, or ,n part IS
ttle ball' 'or the mlnuflmre or ~I~. of ~".,. without
writtwn perrl'iliionCOPYRIGHT ~. !S?r:;

JiG I TAL

EQU! Pt,,1ENT

~ORP.

(

FIRST USED ON OPTION MODEL

QTY.

DESCRIPTION

XMI5

PARTS LIST

PART NO.

iTEM
{ NO.

(

WIRE LIST
XMI5
NEXT HIGHER ASSEMBLY

B-DD-XMI5 - (/J
SCALE
SHEET
DEC FORM NO

nRR 10Q

I !
OF

SIZE CODE

NUMBER

REv,

C
~< WL XM 15 - (/) - VlL
DIST. I
I I I I I I I I I
J