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Document:	DV11 Communications Multiplexer User's Manual
Order Number:	EK-DV11-OP
Revision:	001
Pages:	104
Original Filename:

OCR Text

DV11 communications
multiplexer

user's manual

dlilgliltiall

,
|

EK-DV11-OP-001

DV11 communications

multiplexer
user’'s manual

digital equipment corporation « maynard, massachusetts

1st Edition, December 1976

The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any errors which may appear in this

manual.

Printein
d U.S.A.,

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

DECtape

DECCOMM

DECUS

RSTS

DIGITAL

TYPESET.8

DECsystem-10
DECSYSTEM-20

MASSBUS

PDP

TYPESET-11

UNIBUS

‘ \\

.CONTENTS
Page

CHAPTER 1

INTRODUCTION AND GENERAL DESCRIPTION

1.1

PURPOSE ANDSCOPE
. . .. .. ... ... e
e e e e SO
DV11 COMMUNICATIONS MULTIPLEXER e
e
e e
e e e e

1.2

DV 11 Overview Block Diagram . . . .. e e e e e e
e
Establishing the Data Link
. . . .. ... .. .. J
DV11 Operation . ... .......... e
e e

1.2.1

12.1.1
1.2.1.2

1.3

General Specifications

1.3.1

. . . . .. ...

e e 1A
12
e
e e e e e e e
12

... ..... R
|

CHAPTER 2

INSTALLATION

2.1

SITE PREPARATION AND PLANNING

. ... ... ... e e

B
)

e e e - 2-1

e e e e e

Minimum Through Maximum Configurations . . . . . . e

2.1.1

Compatibility Considerations and Precautions

2.1.2

2-1

. . . . . . ... ... .. T 2-1

Interface Specifications and Signals . . . . ... ... ee e e - 2-2
Interrupt Priorities and Address Asmgnments e 2-2
. . . . .. .. .. e, e e 2-2
~ Interrupt Priorities

2.1.3
2.14
2.14.1

Interrupt VectorAddress A351gnment .........e e e e e e e e e 2-2
. S e e 22
. . . ...
Address Assignments
e 2-2
e
e
e e e
Environment . . . . . . e

2.142
2.143
2.15

it -

UNPACKING ANDINSPECTION . . . . . . .. ..

INSTALLATION OF BASIC ASSEMBLIES

2.3

Unibus Cable Interconnections

2.3.1
2.4.1

B |
1-1

- Reference Documents . . . . ...
.. .. ... O1.3
PHYSICAL DESCRIPTION . . ...
.. ... e e e e e e e
e e .13

122

2.4

. . . . . v it

e e

Unibus and Interrupt Vector Address Assxgnments e

e e

2-5

Synchronous Parameter Selection

2.4.3

Resistance Checks . . . . ... ... e e e e e e e 2-16
Installation of Add-OnDVI1 . ... ......... St 2-16

2.5 |

SYSTEM CHECKOUT .

CHAPT ER 3

PROGRAMMING

3.1

PROGRAMMABLE FACILITIES AND FUNCTIONS et e e e e

3.1.1

3.1.2
3.1.2.1

3.122
3.1.2.3
3.1.2.4
3.1.3
3.1.3.1

3.1.3.2
3.1.3.3
3.1.34

3.1.3.5

3.1.4

3.1.4.1

3.14.2

e e e

2-5

242

244

. . . . . . .. PR e

2-4

e e 25

. . . . .. ... e e

- MODULE INSTALLATION AND CUSTOMIZING

e e 2-13

. . .. S

Programmable Registers

2-17

e e

3-1

. . . . . . . P L34

Control Table . . .. ....... .
~
ControlTable Format . . . . ..........c.ouuueiuuen...... 34

~ Receive Control Byte
. . ......... i
e e M
e e e e e 34
Transmlt Control Byte . ... ........... i e e e e e e e e e e 3-5
|
Control Byte Symmetry . . . ... ... e e e e e e e e e e 3-5
| vOperatlons With Directly-Addressable Registers . . . . ... ... ... e e 3-5
Modem Setup and Control
. . . ... ... S
ST .35
Accessing Secondary Registers
. . . ... ... ... e
e e e e e e e e e - 3-6
Data Transfer Enabling . . ...
. e ee e e e
e e
e
e e e e e e e 3-6
Interrupt Enabling and Response
. . . .. ... ...
. ... o 3-6
Extended Memory Addressing . . . . . e e e e e
e e e e e e
e e . 36
ProtocolProcessmg e
e e
e
e e
e e
e e e e e e e e e e e
e
e 3-6
BCC Polynomial Selections
. . . .. ... ....... e
i
e e e e
e e e 3-6
Processing
Block Terminations
. . . .. ..................... 36

CONTENTS (Cont)
Page
3.1.4.3

Control
Byte Inhibit

3.1.4.4

Sync Character Selection

3.1.4.5

3.1.4.6
3.1.4.7
3.1.5

. . . . .. . . . ..

- Sync/Mark
State Select
Line Activity Snapshot

. .. ....... e e e

. . . . .. ... e

e e e b e e

e e

3-7

3.1.5.2

Table Sizeand Location

e e e e e e

3-7

. . . . .

1
3-8

e e b

e e
.

. . . ... ... ... ... .., .. ... .......

3.2

DIRECTLY-ADDRESSABLE REGISTERS

3.2.1

System Control Register (SCR)

3.2.2

Line Control Register (LCR)

... .. .. e e

e e e e e e e e

. ... ... ... .. e

e e e

. . . . ... ... .. .. .. ...

3.2.3

Receiver Interrupt Character Register (RIC)

324

NPR Status Register (NSR) . . ... ... P e

3.2.5

Reserved Register

Special Functions Register (SFR)

3.2.7

‘Secondary Register Selection Register (SRS)

3.2.8

Secondary Register Access Register (SAR)

3-7

3-8

e e e

3-8

v ev.....

. ... ... [

3.2.6

1
3-7

. . ... .. ...
.e e

Provision for Alternate Data Transmission Tables

3.2.9

e e e e e

e e

. . . ... ... .. e

3.1.5.1

3.3

e .. 37

. ........ R

Stripping Received Syncs

Data Transfer Operations

e 3-15

. . . .. .. ...........S 3-20

Modem Control Registers

e e e e e e e

e e e

ey e

e e e e 3-20

. . ..
. . . e e ey

e e ... 320

. .. .. ... ... ........... . 324

. . . . . .. . ... ... ..,...... e e

INDIRECTLY ADDRESSABLE (SECONDARY) REGISTERS .

. . .

... 324

.. b e v e e e e . 329

3.3.1

Transmitter Principal Current Address (0000)

3.3.2

Transmitter Principal Byte Count (0001)

3.3.3

‘Transmitter Alternate Current Address (0010) . . . ... ..., .., ,.......33
Transmitter Alternate Byte Count (0011)
. .. .. ... ..., .,,......... 3-32
Receiver Current Address (0100) . . ... ........ e
e e e 3-32

3.34

3.3.5

. .. .. e

3.3.6

Receiver Byte Count (0101)

3.3.7

Transmitter Accumulated Block Check Character (0110)

3.3.8

Receiver Accumulated Block Check Character (0111)

. ... ....
.

3.3.9

Transmitter Control Table Base Address (1000)

3.3.10

Receiver Control Table Base Address (1001)

3.3.11

Line Protocol Parameters (1010)

3.3.12

Line State (1011)

3.3.13

Transmitter Mode Bits (1100)

3.3.14

Receiver Mode Bits (1101)
Line Progress (1110)

e e e e

e e e e e e e e

e e 3-29

3-32

. . . . . ee e e e e

e e e e e e

e e

. . . . . ... ... ... . .

. . . .. e

CONTROLBYTEFORMAT

3.5

DV11INITIALIZATION

e e

P ¥

. . .. .. ..., ....... 3-32
e e e 3-33

e e

. .. ...
.. e e e e e e e

e 3-33

e e

e e 3-33

. . .

e e e

P X

. .. ... 3-33
e e

e e 3-33

. .. ... .. .. ... O
P X |

Receiver Control Byte Holding (1111)

3.4

. . .. .. .. e e e

e e e e e e e e

e e e e e e e

. ... .............. e

3.5.1

Line Modem Set-Up

3.5.2

DV11 Data Transfer Setup

. . ... ... e

DATA TRANSFER IMPLEMENTATION

3.6.1

Originating and AnsweringCalls

3.6.2

Resynchronization During Reception

Termination of Transmission and Receptlon

. . . .. e

Reception Control

e e e .. 333

e e e

e e e e e

e e 3-39

e e 341

e e

e .. 341

..., .. 341
e 3-42

. . . . .. ... ... ... .......... . 342

BISYNC Implementation
TransmissionControl

e e e

. ... ... .. e e e e e e e e e e e e

3.6.3
3.64.1

e e e e e e

. .. ... .. ...,

3.6.4

36.42

e e e e e e e e e e e e e e e e e e e e e 341

. ... ... .. e

3.6

3.6.5

. . . . .. .. ... ... ..... N

3.3.15
3.3.16

. . . . ..., . ... ..., .., . ..... 3-29

e e e e e e

e e e e

e e e

e e e e e ee e e e e e e e

e e 3-42

e e e 343

. . .. ... ....... e e e e e e e e e e e e

e e 343

. . . ............ e .. .343

DDCMP Implementation

. . . . . . . . .. . .

3.6.5.1

Transmission Control

3.6.5.2

ReceptionControl

. . . . . . . . . .. .

0 it

e 3-47

. . . ... ... ... .... b

e e e

i 3-47
e

e e e

e e 348

CONTENTS (Cont)
Page

APPENDIX A

PDP-11 MEMORY ORGANIZATION AND ADDRESSING CONVENTIONS

APPENDIX B

PROTOCOLS FOR BINARY SYNCHRONOUS COMMUNICATIONS

APPENDIX C

GLOSSARY OF TERMS AND ABBREVIATIONS

ILLUSTRATIONS

Figure No.
1-1

12
21
22
2.3

2.4
2-5

Pa ge

e
.... e
DV11 Overview Block Diagram . . . . . . .. ... ...
e e e
e
e
e
e
e
g
e
e
i
e
e
e
e
e
..
.
.
.
DV11 Communications Multiplexer
e
e
..
...
...
.
.
.
.
.
DV11 Interconnection Diagram

Module Utilization Diagram

e P

. . . . . .. .. .. e

e Address Selection Switches . .. ... . . ........
— Device
DV11 M7836 Modul
Vector Address Selection
Interrupt
—
DV11 M7837 Module

Switches for DV11 Data Handling Section . . . . . . . . . .« .o

ol
Byte Address
Contr

3-5
3-6
3-7

3-8

2-1

2-2
2-3
24

2-5
3-1

3-2
3-3

2.7

2-8

. . . ... ... .. .. ... 2-18

e|
e
. . . . . . . o o i it

3-4

e
Control Byte FOIMAats . . .« « o v v oot i ettt e e
e e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
...
.
.
.
DV11 Primary Registers .

3-5

. . . .. ..o
. .. .o oot
oo v
. . ... .
. . oo oo v i v v i

3-44

DVI1 Secondary Registers . . . . o« v v v v v vt o i i e e 3-30
. .
BISYNC Transmission Flow Diagram
.
.
.
.
BISYNC Reception Flow Diagram
.
.
.
DDCMP Transmission Flow Diagram
.
.
.
DDCMP Reception Flow Diagram .

.
.
.
.

Table No.
1-1

2-6

3-1

2-4

. . . ... ... .. ............. 2-14

Location of Sync Switches on M7839Module

Distribution Panel and Test Connector Jumper Configuration

3-3

1-2
1-5

. . . . . . .. ... ... . ....

3-2

DV11 M7807 Module — Device Address Selection Jumpers
and Interrupt Vector Address Selection Jumpers for DV11
Modem Control Unit

2-6

iTitle | |

Reference DOCUMENES

. . .« v v v v v e e e e e e e e

e e e

e e

e e e

EIA Electrical Specifications . . . . . . .. .. ... e
e
e e e e e e e e e e e e
e e
Device Address Switches . . . . . . o ¢ o i i

Vector Address Switches for Data Handling Section . . . . . . ... ... ... ... e
Vector Address Jumpers for Modem Control Unit . . . . . ... ... ..o cvv
oo
Synchronous Parameter Selection Switches . . . . . .. .. ... ...
... ...
..
...
..
...
..
Functions of DV11 Programmable Registers . . . . . .
System Control Register Bit Assignments
Line Control Register Bit Assignments

Cards)
nous
Line
(For Synchro

. . . . . ... . ... ..o

. . . . . . ..« .o v v

i v i oo e

e e e e

3-46

3-48
3-49

TABLES (Cont)

Table No.
34

Title

Page

Line Control Register Bit Assignments

(For Asynchronous Line Cards)

. .. ... ... L .

Receive Function Interrupt Conditions

36
3.7

38
39
3.10

(For Synchronous Line Cards)

. ... ... e

....

(For Asynchronous LineCards)

)

. .. ... .........

Transmit Function Interrupt Conditions
Control Status Register Bit Assignments
Line Status Register Bit Assignments

. . .. ..., ...
. . . ... ...
..

cccccccccccccccc

[

[]

)

[)

[}

[

[}

. . . ... ..., ..

Line Protocol Parameters Secondary Register Bit Assignments
Line State Secondary Register Bit Assignments

3.12

............

Receive Function Interrupt Conditions -

Line Progress Secondary Register Bit Assignments

. . . ..
.

. . . . . .

313

Control Byte Bit Assignments

3-14

~Transparent Data Transmission Control
. . . . ... ... ..
Non-Transparent Data Transmission Control . . . .. .. ..

3-15

. .. ...
.. e

;

CHAPTER 1

INTRODUCTION AND GENERAL DESCRIPTION

1.1

8 or 16 serial data lines can be rrrultiplexed directly to

PURPOSE AND SCOPE

This manual is intended to provide operational pro-

'PDP-11 core memory for bidirectional data transfer.

gramming information for the DVl Commu‘nications Multiplexer. The manual consists of three
chapters plus appendices:

The DV11 is intended for use with a PDP-11 program
~that provides the rules or protocol which govern the

data transfers and the generation and interpretation

of data link control and character codes.

Chapter | provides an introduction and overall

functional

and

physical

descrlptrons

of the

Protocols require processing to (1) monitor trans-

DVII;

mitted and received characters in order to identify
and respond to control characters, (2) maintain a

Chapter 2 contains site preparation, interfacing,

"~ record of control and data transmission and recep-

and installation information;

tion sequences, and (3) compute the error checking
code (block check calculation) on each character

Chapter 3 includes all information necessary for
operation

of the

DVI1Il via

transmitted or received. The DVI1 performs these

the PDP 11

program;

functions, thus relieving the processor of this over-

head. A Core Memory Control Table, set up by the
PDP-11 program, is used by the DV11 to direct the

Appendices contain reference data, commu-

processing of received and transmitted characters.

nications introductory data, and an extensive

"The control table is comprised of control bytes,

‘glossary of terms and abbreviations.

which form a one-to-one correspondence wrth each

chakacter transmitted or received.

The reader unfamiliar with communication line protocols should readAppendrx B before attemptmg
Chapters 1 and 3.

1.2.1 DVI11 Overview Block Diagram
Figure 1-1 is a DV11 overview block diagram, show-

are generally defined at

ing the principal functional units, and data and con-

their first appearance. However, should the reader
encounter a word that is not fully understood, refer

trol lines for the DV11. The DV1! consists of two
primary functional subsystems, as indicatéd on the

to the glossary provided in Appendrx C

block diagram: a Modem Control Unit, and a Data

Terms unique to the DVII

before

proceeding.

Handling Section. The Modem Control Unit mon-

1.2 DVI1 COMMUNICATIONS

directed by the PDP-11 program. The Data Handling

itors and controls operations of the line modems as

Section sequences and synchronizes transfer of data

MULTIPLEXER

The DVII is a communications multiplexer for the

PDP-11 family of computers. By means of the DV11,

between the modems and the PDP-11 Unibus (effec-

tively, core memory).

A MODEM CONTROL

INTERRUPT
~

MODEM

SET-UP

comRTOL

" NPR

NPR

MASTER
SCANNER

LINE SELECT
—{ <4>

NPR

|
@-——.-—q

;EOMOTE

MODEMS
|

g RECE
IRIVERS —
TRANSMITTERS

SYNC B FLAGS

CONTROL

= |
S le

MODEMS

STEP

[75]
|

DATA LINES

UNI

DATA HANDLING

MICRO

RECEIVED
CHARACTER

PROCESSOR

B’—‘—7
= |TM RRNAD%M
|
Ra
ACCESS
”‘."‘.

SILO

MEMORY

RECEIVER

INTERRUPT
‘CHARACTER
REGISTER

)

/'\'8 |
NS

\/’
|

11-2896

‘Figure 1-1

1.2.1.1

DVII Overview Block Diagram

Establishing the Data Link - Data transferis

Handling Section to enable the data transfer between

enabled whenever
I.

the selected local modem and core memory.

An operator manually initiates a call to a

The serial/parallel interface is accomplished in the

remote modem, or the PDP-11 program

receivers and transmitters. The receivers assemble

dials the remote number via the DNI1!

characters received from the serial data lines and set a

Automatic Calling Unit; when the data

flag each time a character is assembled. The trans-

link is established by the remote modem

mitters disassemble parallel characters
for transmis-

- answering

the call,

the DVIl

Modem

sion on the serial data lines and set a flag each time

Control U nit signals the PDP-11 program

another character can be accepted for transmission.

via an mtcrrupt

The Master Scanner cyclically enables the receivers
2.

In response
to a
-

RING signal from a

and

remote modem, the DVI] Modem Con-

transmitters

route their flags to the

Milcroproccssor

trol Unit interrupts the PDP-11 program,
to

initiate an exchange of signals that

The Mlcroprocessor T controlled by a Read- Only

establishes the data link.

1.2.1.2

Memory (ROM), which handles character transfers
and steps the Master Scanner. Once started by the

DVI11 Operation - With the data link estab-

PDP-11

lished, the PDP-11 program sets up the DVI11 Data

program,

continuously.

1-2

the

Microprocessor

runs

The Received Character (RC) Silo is a first-in, firstout storage buffer with a capacity of 128 characters.
When a character is received by the DV11 and the
RC Silo is empty (usual condition), the character
‘propagates to the bottom of the RC Silo. The Microprocessor then inspects the character code to compute the core memory address of the control byte for
that character. A Non-Processor Request (NPR)

instruction is issued by the Microprocessor to fetch
the control byte, which is then interpreted.

In most cases, the control byte will specify.character
storage, and the character will be transferred from
the bottom of the RC Silo to core memory via an
NPR transfer. Should the control byte identify the
character as an interrupt character, the character will be propagated into the Receiver Interrupt Character
(RIC) register for further attention, and the PDP-11
program will be signalled via an interrupt. The RICregister is used to display interrupt characters to the
PDP-11 program, along with the line number and
any error flags.

Processing instructions for the character in the RIC

register are sent to the Microprocessor by the PDP-11 program. The RC Silo continues to accumulate
received characters while waiting for the PDP-11 program to complete its response to the interrupt; however, inspection and storage of any additional
characters from the RC Silo to PDP-11 core memory
by the Microprocessor is inhibited. (The Microprocessor continues to perform data transmission
tasks.)

NPR Control is used by the Microprocessor to access

core memory, to store received characters, fetch characters for transmission, and fetch control bytes to
direct character processing. Table addresses in core

memory are stored in the Random ‘Access Memory

(RAM) for character storage and retrieval, and byte
counts for controlling the quantity of data transferred. The RAM also contains registers for controlling protocol functions for each data line.

Character transmission is similar to the reception

process just described. When the Master Scanner
finds a transmitter flag, the Microprocessor uses

NPR Control to fetch the next character for that line

from core memory, it then uses the character code to

compute the address of the corresponding control
byte, and does an NPR to fetch the control byte. The
Microprocessor responds as directed by the control
byte and then loads the character into the transmitter
for transmission.

'1.2'.2 ‘Reference Documents

of pertinent documents, i.e.,
a list
Table 1-1 contains
documents covering concepts and systems peculiar to
the DV11, plus documents covering equipment with
which the DVIl interfaces.

1.3

PHYSICAL DESCRIPTION

The DV11 Communications Multiplexer is housed in
a 9-slot, double system unit and includes a separate

rack-mounted distribution panel for each group of

1-2 shows a DV11
eight modems in a system. Figure
system for supporting eight lines or modems. Other
configurations are discussed in Chapter 2.
1.3.1

General Specifications

‘Environment

Tcmpcrature:‘ 10° to 50° C

Humidity: 0 to 90% non-condensing

- Power Requlrements

A DVI1 system with l6 synchronous lines:
175A@ +5V

10A@-15V
OSA@+15V

A DVl1l systcm with 16 asynchronous lmes
205A@ +5V

1l0A@-I5V

A@ +15V -

8 asynchroA DVI11 with 8 synchronous and
|
nous lines:
A
@ +5V
190

1.0A@-15V
@ +15V
0.55A

Character Length
5, 6,7, or 8 bits
Internal Baud Rates Provided
Synchronous (via switch settings):
1200, 2400, 4800, 9600
Asynchronous (via PDP-11 program):
50, 75, 110, 134.5, 150, 300, 600, 1200,
1800, 2000, 2400, 3600, 4800, 7200, 9600,
38,400

Operating Modes

Full- or Half-Duplex

Table 1-1
Reference Documents

Title

Description

GENERAL

PDP-11 Peripherals Handbook

Discussion of overall system addressmg modes and basic instruction set from a programmmg pointof view. Some interface and
|

installation data.

PDP-11 Instruction List .
7

Pocket-size list of instructions. List group names functions, codes,

‘and bit assignments. Includes ASCII codes and the bootstrap
~ loader.

Logic Handbook

Presents functions and specifications of the M-Series logic modules

and accessories used in PDP-11 interfacing. Includes other types of |
logic produced by DEC but not used with the PDP-11.

Introduction to Minicomputer Networks

Binary Synchronous Communications
|

Principles of -computer-based:date communications technology.

Introduction to IBM’s Binary‘SynchronousCommunications

A Message-Oriented Protocol for
Interprocessor Communication

Protocol (BISYNC or BSC).

Introduction to DEC’s Digital Data Communication Message

Protocol (DDCMP).

Data Set 201
A and 201 B Interface

Description of interface leads in synchronous modems.

Specifications

Data Set 201C Interface Specification

Data Set 208A Interface Specification
=~~~

SOFTWARE

Paper-Tape Software PrOgramming |
|

‘

Interface Specification

Data Set 208B Interface Specification

Handbook

Interface Specification

Detailed drscussron of the PDP-11 software system used to load,
dump, edit, assemble, and debug PDP-11 programs. Also included

is adiscussion of input/output programming and the floating-pomt
and math package.

Figufe 1-2

DVI1 Communications Multiplexer

‘Parity Generation and Detection
Odd, Even, or None

Modems Accommodated

Synchronous modems (Bell System 201, 208,

209, or equivalent)

'Asynchronous modems (Bell System 202 series,

Sync Character Facility

Synchronization of a line can be selected to be
on the basis of the receipt of either one sync
character or two consecutive, identical sync

characters. For each 4-line group, two sync

‘codes may be manually preset in switches. The
PDP-11 program may select either of those two
sync codes for use on a selected line.

103 series or equivalent)

Bus Loading

Two PDP-11 Unibus Loads

Protocols Implemented

The DV11 specifically implements (but is not
limited to) Digital’s DDCMP and IBM’s BISYNC protocols.

Maximum Throughput

38,400 characters/second

NOTE

Since the DV11 requires 21 A of +5 V power, only
three DV11s can be placed on a typical 21-in. expander
box. Expander boxes usually contain three H744 regu-

lators, each of which has a capacity of 25 A. A device

cannot be powered partially from one regulator and
partially from another regulator; the number of DV11s
must equal the number of regulators. Therefore, three
DV11s is the maximum for one expander box.

CHAPTER 2

INSTALLATION

This chapter provides information for interfacing,

2.1.2

————
.-

in Section 2.1, Site Preparation and Planning. Instal-

asynchronous modems 202 series, 103 series or equiv-

lation, customizing, and checkout procedures are discussed in Sections 2.2 through 2.7.

alent when asynchronous line cards are used. The
DVI11 provides internaal clock rates of 1200, 2400,
4800, and 9600 baud at 0.005% accuracy for synchronous operation; modems operating at other rates
must supply their own clock signals. Itis recommended that modem-supplied clockmg be used where

2.1 SlTEPREPARATlQN AND PLANNING
2.1.1

Compatibility Considerations and Precautions

The DVI| with synchronous line cards is directly
compatible with Bell synchronous modems 201, 208,
209, or equivalent. It is also compatible with Bell

installing, and testing the DV1l1 Communications
Multiplexer. Interfacing considerations are discussed

Minimum Through Maximum Configurations

The DV11 provides multiplexing capability to PDP11 core memory for up to 16 modems. The DVI11 is

available.

housedin a nine-slot, double system unit and includ-

es one rack-mounted distribution panel for cach

group of eight modems in a system. Five of the nine
slots are occupied by functions required in any system configuration. The rcmammg four slots are occupied by four hex-printed circuit boards (M 7839 or
M7833), designated as the line cards. Each line cardis
capable of supporting data transfers to and from four
modems. The M7839 line card supports synchronous
data transfers while the M7833 supports asynchronous data transfers (these line cards contain the
receivers and transmltters)

The DVII is compatible with all members of the
PDP-1! family of computers. PDP-11 standard software address allocations provide for the implementation of as many as four DV1ls in a PDP-11 system.
DV11 throughput rate, however, forms a more severe
limitation on the number of DV!ils in a system as
will now bc dcmonstrated

A single DVI11 multiplexing 16 modems at 9600
baud, each in full duplex mode, is capable of transferring 38,400 8-bit characters per second (1200 characters per line X 16 lines X 2 directions). Although this
is well within the capabilities of the DV1Il, on the
average, the PDP-11 is provided with only 26 us to

The 5-module unit common to all DVIl con-

figurations is designated the DV11- AA. Two of the
M 7839 module, plus one distribution panel and associated cables, form an eight line synchronous umt

designated the DV11-BA. An eight line asynchronous
d replacing the
unit, the DV11-BB, is generateby
M7839 modules in the DVII-BA unit with two
M7833 modules. Similarly, a mixture of one of each
line card forms a synchronous/asynchronous unit

handle each character. Although most characters are
handled by NPR transfers, program and protocol
efficiencies still need to be relatively high to maintain
this rate; this would be for a single DVIIl. Some
76,800 NPR ¢/s would be required, or about 10 per-

designated the DV11-BC. The minimum DVII system configuration consists of one DV11-AA unit plus
one line card option, DV11-BA, DV11-BB or DVI1lBC:; a maximum configuration consists of one DV11-

cent of Unibus capacity. With all lines operated in

DDCMP mode (control byte fetch inhibited), 38,400
NPR c¢/s would be required, or about 5 percent of
Unibus capacity.

AA unit plus two line card options.

2-1

DVils should be connected ahead of all Massbus

devices on the Unibus and behind unbuffered NPR

devices

such as RKOSs. DVI1ls have placement
requirements similar to those for DQIlls. If both
DQIls and DV 1s are used, place the units with the

A; DN11; DM11-BB; DRI11-A; DR11-C;

highest baud rate first. If all DV11s have 16 lines at a
9600 baud rate, a maximum of 1 DV11 can be connected with the following exceptions:

‘a.

Reader;

DX11;

DLI1I-C, -D, -E;

PA611

Punch;

DTII;

DJ11;

DHII;

Section/DV11 Modem Conrol Unit.

TwoDVIlscan be used on a PDP-1 1/40,

Ifany type device is not used in a system,
vector assignments move down to fill the
vacancies.

Two DVllscan be used on a PDP—l 1/70
with no Unibus disks.

For lower speed lines, the maximum number can be

increased proportionally. (Example: a PDP-11/40
with 2400 baud rate lines can use four DV1ls.) A

based

NPR

access.

another DV11 would be after the existing
DVI11, but addition of a DC11 would
cause all other vector addresscs to move

Interrupt

performance depends on the operating system, protocol, and buffer lengths.

upward. )

2.1.3 Interface Specifications and Signals
The DVI11 presents two unit loads to the PDP-11
Unibus and also provides modem control and data

Each device interrupt vector requires four address

locations (two words). A further constraint is that all

vector addresses must end in 0 or 4. The vector

leads compatible with EIA RS-232-C and CCITTV24 specifications. EIA RS-232-C electrical specifications are listed in Table 2-1.

Reassignment of other type

devices already in the system may be
required. (For example, the vector for

maximum of four DV11s can be placed on any sys-

are

If additional devices are to be added to the
~ system, they must be assigned con- tiguously after the original devices of the
same type.

tem because of address space limitations; the limita-

2.1.4

PA611

GT40; LPS1I; VT20; DQI11; KWI11-W:
DUIIl; DUPII;, DVIl Data Handling

PDP-11/45, or PDP-11/50 with no disks.

tions

The devices are assigned in order by type:
DCI11; KL11/DL11-A, -B; DP11; DM11-

address is specified as a three-digit, binary-coded

octal number using Unibus data bits 0-8. Because the

vector must end in
0 or 4, bits 1 and 0 are not speci-

fied (they are always 0) and bit 2 determines the least
significant octal digit of the vector address (0 or 4).

Interrupt Priorities and Address Assignments

2.1.4.1

Interrupt Priorities - The DVI11 uses three
interrupt vector addresses. Interrupt priorities for the

2.1.4.3

Data Handling Section are selectable by means of a
priority plug on the M7837 module. The priority plug

775040, 775100, 775140, etc. lfany DMi11 -AAsarein
use, the DVI11 will follow them. -

is preset to select BRS priority; it may be changed to

select

BR6 priority, but the diagnostic programs

expect BRS.

The Modem

Control

manently wnred to BR4 pnonty

2.1.4.2

2.1.5 Envirorment
'
The DV11 will operate in temperature environment

Unit is per-

from 10° to 50° C with a relative humidity up to 90%,
non-condensing. Power requirements are as follows:

Interrupt Vector Address Assignment
- .Com-

munications devices are assigned floating mterrupt
vector addresses as follows

Address Assignments - The DV 11 is assigned

an address of 775000. Additional DV11s would be at

Voitage

Current
(Amperes)

The vector space starts at location 300 and
proceeds upward to 776.

-15

+15

2-2

0.5

(

EIA Electrical Specifications

Driver output logic levéls with 3K to

ISV>

>S5V

SV>>-15V

- TKload

~ Driver output voltage with open cir-

IV, <25V

cuit

Driver output impedance with power

20 > 300 ohms

off
Output short circuit current

/1,/ <0.5A

Driver slew rate

T < 30‘V;..ts.

Receiver input impedance

TKQ> R, > 3KQ

‘Receiver input voltage

Receiver output with open circuit

15 V compatible with driver
Mark

input

Receiver output with +3 V input

Space

Receiver output with -3 V input

Mark

" 7777
AN
A LAY
%,

NSNSTSSNSSY

LOGIC “0” = SPACE — CONTROL ON
Noise margin
Transition region
Noise margin

S TITTTITIT

LOGIC “1”= MARK = CONTROL OFF

2.2

UNPACKING AND INSPECTION

2.3 INSTALLATION OF BASIC ASSEMBLIES
Drawing D-UA-DV11-0-0 shows the physical

After unpacking, check that the following parts are

present for the basic DV11-AA unit:

~arrangement of the wired backplane, distribution

panel(s) and cables in a typical installation. Figure 2I is the DV11 interconnection schematic. Install the
9-slot, double system unit in the expander box or
processor box as space and power are available. With
power off, test the resistances between all pins of the
power harness Mate-N-Lok connector. Only pins of

| D-AD-7010834-0-0 Logic Assembly
I M7807 Bus Control and Mux Board
1 M7808 Modem Control Scan and Mux Board
I M7836 ALU and Transfer Bus Board

I M7837 Unibus Data and NPR Control Board

the same wire color should be connected. Secure the

| M7838 ROM, RAM, and Branch Board

ground wire to one of the mounting screws. Plug in
the Mate-N-Lok connector of the power harness.
Apply power and check for proper voltages on the
|
logic pins (not the cable) as follows:

I M920 Unibus Connector

Also check that the following parts are present for
each line card option ordered:

Voltage

+5+£0.25V

~-15+£0.75V
+15+£0.75V

2 H8612 Line Card Test Connectors
1 H317C Distribution Panel

CiUl

4 BCO8R-15 Cables

This will ensure that the cable and the Mate-N-Lok
connector were correctly installed. Turn power off,
(Note that the DVI1 is not yet connected to the
Unibus, nor are any modules installed.)

I H325 Test Connector

DVI11-BA: 2 M7839 Sync Mux Line Card

DVI11-BB: 2 M7833 Async Mux Line Card

Install the distribution panel(s) as indicated in Figure

2-1. Refer to Figure 2-7 for the proper jumper con-

DVII-BC: | M7839 Sync Mux Line Card 1
M7833 Async Mux Line Card

figuration of the distribution panel. To install an addon DV11, see Paragraph 2.4.4.

OUTPUT CABLES
ARE BCOS0D-23
f

I 8 CuTPUT CABLESI :
ETey

DISTRIBUTION

PANEL

(FIRST 8 LINES)

J € ’o

]/\1

NIK]

Ji¢

\./

men SLOT $

4 BCOBR
CABLES

]
PDP11 PROCESSOR BOX

OR BA11 EXPANDER
BOX THAT CONTROL

'THE DV11

CONTROL

LOGIC WIRED

ASSY

. D-AD-T010834

4 BCOBR

H317C

DISTRIBUTION PANEL
(SECOND 6 LINES)

CABLES

J9
N

{

Jig

]
\wy

LINE CARD SLOT 7

M7BO7_Ji

LEE;.%B'_Q}ET
M7807

AC POWER CORD
TOLINEGR PDP-11

NOTE:

‘

ClA2
CIB2

Instail ail BCOBR cables with smooth
side toward you and ribbed side toward
circuit boord.
1-2930

Figure 2-1

DVI11 Interconnection Diagram

L5l

2.3.1 Unibus Cable Interconnections

- DVII,

The DV11 is shipped with one M920 Unibus Con-,

nector (placedin slot 9 as shown in the module utilization

program,

electrically

Figure 2-2),

connecting

the

provided on the DVI11 as follows:

which provides for

unit

the

Two Unibus addresses (also called device

addresses) and two interrupt vector addresses are

PDP-11

Unibus. For processor box installation where the unit

is to be electrically placed in mid-bus (i.e., somewhere

DV.‘I_l'Data Handling Section address,

DV11 MCU address,

between the first and last devices on the PDP-11
Unibus),

the M920 from the next higher device

DVIIl

(closer to the processor) on the bus is plugged into

Data Handling Section interrupt

vector address,

slot 1 of the DVII, and the M920 in slot 9 of the

DVI11 is plugged mto slot 1 of the next lower device

DVI1 MCU interrupt vector address.

on the bus.
Because the DVI11 has ten registers directly addressFor an end-of-bus mstallanon of the DV11, proceed

able by the PDP-11 program, it must be assigned a

as follows

Unibus address that is a multiple of 32 (octal 40). All
DVlils

Remove the M930 Unibus Terminator

addresses.

system

should

have

consecutive

from the last slot of the current end-of-bus
~device.

The Unibus addresses for the DV11 Data Section are

controlled by a rocker DIP switch package, located
on module M7836, and by jumper straps on module

Remove the M920 from slot 9 of the
DVII1 and place in slot | of the DVI1.

M7807 for the DVI1 MCU. (Locations of all address

selection switches and jumpers are shown in Figures
3.

lnstall the M930 (removed in step l) in

2-3 through 2-5.) The position of these switches deter-

slot 9 of the DV11.

mines bits 03-12 of the Unibus address. If a rocker

switch is set to ON or a jumper on the M7807 board
Unibus interconnections are made via BC11-A cables

1s in, an address bit of zero in the corresponding bit

where the DVII is installed in expander box or is

position serves to address the DVI11 Data Handling

physically
the first or last unit in any box. Cable

Section. DEC standard software requires that the

requirements in these cases are as described in Figure

DVI1 address be set as specified in Paragraph 2.1.4.

2-2.

Switch settings for device address selection are shown
in Table 2-2.

2.4

MODULE

CUSTOMIZING

Figure 2-2

INSTALLA TION

AND

The interrupt vector address for the Data Handling
Section is controlled by a DIP switch package on the

is the module utilization diagram. Set the

address assignment and parameter selection switches

as described in Paragraphs 2.4.1 and 2.4.2 before

M7837

installing modules.

08-03. The switches should be set to select vector

module, which selects vector address bits

addresses between 300 and 776. Switch settings for

2.4.1

Unibus

and

lnterrupt

Vector

interrupt vector address selection for the Data Han-

Address

Assignments

dling Section are shown in Table 2-3. Vector address

The Unibus and interrupt vector addresses for the
DVI1 must be set manually before operating the

jumpers on the M7807 module (Table 2-4).

selection for the Modem Control Unit is done by

2-5

M920

M7836

M7837

M7838

‘

_g;g%g’

ALU

UNIBUS

ROM

MUX

CABLE

UNIBUS

CONNECTOR

QfS%?’

§;3%§

MUX

MU X

AND

NOTE 3 | TRANSFER
BUS

DATA

RAM

NPR
NTROL

BRANCH
-

AND

CARD
|

LINES
0-3

M320
CABLE

LINE

AND

9
7

LINE

CARD
|

LINES
4-7

UNIBUS

LINE

CONNECTOR

LINES

NOTE 2

CARD
g-11

NOTE 1
8
-

M7807

M7808

BUS

CONTROL
AND
-

MODEM

CONTROL
SCAN

MUX

AND

X
MU

NOTES:

VIEW FROM WIRING SIDE

1. If end of bus repiace M9220 with M930.

2.1f last unit in basic box replace M920 with BC11A cable
end when expanding to pheripheral box.

3.1f first unit in expander
box replaca M920 with BCI1A cable end.
t1-2932

Figure 2-2

Module Utilization Diagram

2-6

7 7

7414-10

ON=0
OFF =1

A04
UNUSED

74143

Figure 2-3 DV11 M7836 Module — Device Address Selection Switches

}

2-7

UNUSED

Figure 2-4 DV11 M7837 Module — Interrupt Vector Address Selection Switches
for DV11 Data Handling Section

DEVICE ADDRESS

(AO3 —- A12)

‘

w18

W12

W17

w13

Jumper

Bit

A12

A09

w12

A04

w13

A05

W15

A03

W10

W14

A08

A1l11

W16

A06

w17

AO07

<
W16

Jumper In=0

.
w10

w11

INTERRUPT VECTOR

ADDRESS

Jumper
w1

Bit
=

DO8

D02

pos

W15

DO6

W5
W6

(D02 — DO08)

-i

D07
-

W7,

D05

D04

Jumper In = 1

w14

7414-11

Figure 2-5 DV11 M7807 Module — Device Address Selection Jumpers
“and Interrupt Vector Address Selection Jumpers

for DV11 Modem Control Unit

2-10

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3
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Table 2-3

Vector Address Switches for Data Handlmg Section
(Vector Addresses are Modulo 10)

M7837Switeh |
~Address Bit

| 4

D08 | D07 | D06 | DO5

| D04 |

| Vetor

Address

DO3 |

x |x

| 300

X
X

320
330

Xx |

X
X

| x
X

X
| X

x
X

| X

400
410

420
430

440

X
|

X | X

510
530

520

460

500

X | X

450

470

360
370

| X

350

340

x |

310

540

560

550

570

etc. to

770

Notes: 1. X means switch ON
Set only the switches shown.

Vector Address Bit D02 is controlled by DVI 1 logic dependent on
whether a Receiver Interrupt (Bit D02= 0 = Vector A)ora

Transmitter Interrupt (Bit D02 = 1 = Vector B) is being requested.

2-11

A Table2-4

Vector Address Jumpers for Modem Control Unit

(MCU Vector Addresses are Modulo 4)

W2 | Vector

M7807 Jumper | WI*| WS | W4 | we | W7 | w3 |
| D08 | DO7

| DO6

| DO5S

| DO4 | D03 | D02

| x

X |

| Address

x | 300

304
X

310

314

320

330

324
334

340

344

350
354

360

364

374

| X

| x

X| X

x|
x|

x
x

X
X

450

454

| x

x|
x
X | X
X
X

2-12

400

404

410

414

420
424

430
|

|
X

X
X

370

| X
X

x | 440
|
444

1
x
.
X | x
X

434

460
464

470
474
| s00
504

- AddressBit

Table 2-4 (Cont)

Vector AddressJumpersfor Modem Control Umt
(MCU Vector Addressesare Modulo 4)

Address Bit

D08

| D07 | D06 | DOS - D04

| X

| x

| D03|

DO2 | Address

510

x|
I

514
x

520

524
X

530

534

544
|

ssa

X |x

I x

se4

s70

| x

560

|
=

o Notesf

574
etc_._ito

X méansjumper OuUT
Cut only the jJumpers shown

3*Jumper W1 is in for the PDP 1 1/20 w1th the KHll and for the PDP 1 1/40
| PDP 11/45, and newer PDP-11s.

2.4.2 Synchronous Parameter Selection
Rocker DIP switches are located on each M7839
module for selectlonof the: followmg synchronous
data channel parameters e

Sync character codes”

Switch settings for each synchronous parameter are
listedin Table 2-5. Swntch locatnons are shownin Flgure 2-6.

1. Internal baud rate (1200 2400, 4800,
~.9600)

:_--Full/half duplex

NOTE

Parity (odd/even/none)

Whenever possible, the parameters shouid be con-

Characterlength (5 6, 7 or 8 bits)

duplex

Sync requirement (whether one sync char-

figuration can only bedone after dlagnostlcs have been

acter or two consecutive, identical sync
characters ‘are required to achieve line

run. DV11 diagnostics don’t support half-duplex or

synchronization).

figured per customer requirements at this time. If halfor

parity

parity operation.

operatlon is required,

this con-

SWITCH PACK 4.

SWITCH PACK 3

Sync Character A~

‘Sync Character
B

SWITCH PACK 2

SWITCH PACK 1

Baud rate and

Parity, Character

Duplex Select

length, and number
of syncs

74145

Figure 2-6 Location of Sync Switches on M7839 Module

2-14

)

“Table 2-5
Synchronous Parameter Selection Switches

ASwitch
|
Pack

Function

Parameter

Name

Internal Baud

1200 Baud |

Select B

Ratc -

2400 Baud

Select A
Select B

52
S2

4
3

ON
ON

OFF

4800 Baud

Select B

OFF

9600 Baud

Select A
Select B

S2
S2

4
3

ON
OFF

Select A

OFF

Full Duplex*

HD3

| S2

HD?2

HDI

"ON

HDO

Half Duplex

HD3

OFF

HD?

OFF

HDI

OFF

HDO

OFF

No Parity*

OFF

EPE

OFF

ON.

EPE

OFF

Full/Half

Duplex

|
Parity

|
Odd Parity
|

Even Parity

Select A

Number

Setting

Character

8 Bits/Char

WLSI

Length
(Excluding

|
7 Bits/Char

WLS2
WLSI

SI
S|

4
3

OFF
ON

Parity)

WLS?

OFF

6 Bits/Char

WLSI

OFF

5 Bits/Char

WLS2
WLS|

SI
S1

4
3

ON
ON

- WLS2

1 SYNC 00

OFF

| SYNC 01
1 SYNC 02

SI
Sl

6
7

OFF
OFF

1 SYNC 03

OFF

SYNC

1 SYNC REQ.

Requirement

*Must be selected to run diagnostics DZDVA to DZDVE.

7-15

OFF

Table 2-5 (Cont)
Synchmnous Parameter Selection Switches

)
Function

Switch

Parameter

Sync Req. (cont)

Pack

Number

1 SYNC 00

1 SYNC 0!

1 SYNC 02

- ON

| SYNC 03

Desired Code

Sync A

]

(As required

v
8

OFF=Logical one)

(As required

cal one)

2 SYNC REQ.

Sync Character

Codels

Name

Desired Code

Sync B

Setting

OFF=Logi-

Line synchronization can be selected by the receipt of

2.4.4

either one sync character or two consecutive, identi-

Proceed as follows to install an add-on DVI11:

Installation
of Add-On DV11

cal sync characters. For each 4-line group, two sync
codes (Sync A or Sync B) may be manually preset in
the Sync Character Code switches. The PDP-11 pro-

Install the wired backplane assembly in

the mounting box.

gram may select either of these two sync codes for use

on a selected line.
2.

Measure the resistance between pins of

Internal baud rate 1s determined by the ON/OFF

the power harness (see first paragraph of

states of the Select A and Select B switches. This is

Section 2.3).

applicable only when the modem does not supply
clocking.

Plugin the Méte-N-Lok connector of the

power harness.
2.4.3

Resistance Checks

Measure the resistance between the following pins on

the backplane with the white plug of the 7010835

Apply power and measure voltages at the
logic pins (Paragrah 2.3).

cable hanging free (not plugged in), and with all modules plugged in:
+5 V to GND must be 0.5

5.
or greater

-15 V to GND must be 50 Q or greater

Turn power off.

Set all addréss,”parameter switches (Paragraphs 2.4.1

+15 V to GND must be 10 Q or greater

and 2.4.2) and distribution

panel jumpers (Figure 2-7).

If the resistance is less than the lower limit indicated,
check for
a short. If the resistance exceeds five times

Hhst_all modules (Figure 2-2).

Unplug the power harness.

Do resistance checks (Paragraph 2.4.3).

10.

Apply power.

the low limit, it may indicate an open circuit. Make

each measurement twice, once for each polarity of the

meter. The lowest reading must not be less than the
low limit listed. If the above resistances are correct,

connect the white plug in accordance with D-UA-DVI11-0-0.

2-16

2.5

SYSTEM CHECKOUT

Turn on the power. Toggle in the Bootstrap and load
the

Absolute

Loader

(if not already

done).

The

addresses and contents of the Bootstrap Loader are
listed below.

Address

Memory size

-—-744

determines the

Contents

016 701
.

first 3 digits:

———746

000 026

---Equals:

---750

012 702

017 for4K

——=752

- 000 352

037 for 8K

——-754

005 211

057 for 12K

—--756

105 711

077 for 16K

——=760

100 376

117 for 20K

—--762

116 162

137 for 24K~

-—-764

000 002

157for28K

---766

——-400

——=770

005 267

=772

177 756

[

000 765

=776

177560

(TTY Reader)
or

177550
- (High speed

reader)

Place Absolute Loader (MAINDEC-11-LZPA-PO)
in the reader, load and start at address ——-744. Place
the diagnostic tape in the reader, load and start att

~ address ---500. Load and run the DV11 diagnostics
as specified in Chapter 5 to verify system operation.

If half-duplex or parity operation is desired, configure the M7839s accordingly (Table 2-5).

2-17

DISTRIBUTION PANEL

EIA CONNECTOR

()

——
o

s ‘p__,.TO pegepyiogare
s

H325

P.GND

"TEST CONNECTOR

— EIA XMIT DATA 8@

——— EIA RCV DATA B9

DATA SET
RDY 9@

| me

P
a————

J1=3

@02

CTS B9

—

Ji—-4

_J
-

J1-5
S

GND

CARRIER @9

J1-8

-ftn

———]

wWa1A

(202 SEC TX 2@)
-

OO —

WZ2A

(202
SEC RCV 22)

NEW
SYNC

J1-15

W@6S
O

DCE

Ji-11
J1-12

-—h

wg3s

RTS

J1-24 -

SCT @@

N=17

-0—0—— DCE SCR 2@ -

Ji-20

Ji-22

¥
| nEW

OTR 08

SYNC

) nAn

J1-6

Ji-14
W@g4s
-O—O0—— DTE SCTE 29
W2 SF

RTS 29

¥% NORMALLY

REMOVED

NOTES:
1. Jumper configuration is typical for remaining lines.
For actual jumper locations, refer to drawing D-CS-5411153.

2. For asynchronous use, remove jumpers denoted by the letter “S”.

For synchronous

use,remove jumpers denoted by the letters "A" or "F"
19-4404

Figure 2-7 Distribution Panel a‘nd Test Connector Jumper Configuration

2-18

CHAPTER 3
PROGRAMMING

determine and respond to requirements for auxiliary

This chapter contains all information required for

protocol processing (i.e., block check calculations,

controlling operation of the DVI1 Communications
Multiplexer

means

of the

PDP-11

data block termrndtrons control character handling)

program.

(Chapter | should be read prior to this chapter.) The
reader should also be familiar with synchronous
protocols as discussedin Appendix B. Chapter contents

The PDP-11 program directs DVl | activities through
the programmable registers of the DV11, along witt
a control tdble set up in core memory for reference b+

~are arranged as follows:

_the DVII

Programmable Facilities and Functions:
The programmable registers, core memo-

DV11 are discussed (Section 3.1).

3.1.1 Programmable Reglsters
The DVII programmable registers consist of the

2. Complete, detailed descriptions of pro-

addressable via the Unibus, plus *‘secondary” regis-

ry table references, and functions of the

“primary” system registers, which are directly

ters, which may be accessed by the PDP-11 program
after first loading a primary register. (The primary
register selects the secondary register to be accessed.)
The directly-addressable registers provide for modem
setup and control, data transfer enabling, interrupt

grammable registers and control bytes
'(Sectrons 3. 2 3.3, 3.4).

Procedures for DVI1 initialization (Sectron 3.9).

enabling and reporting, extended memory addres:

Methods for controllingdata. transfers

ing, and access to secondary registers. The secondar.
registers provide for protocol processmg and dat..

and implementing protocols (Section 3.6).

Section 3.1 describes DVI1 functions in sufficient

Ten directly-addressable registers are provided

detail to enable the reader to omit a detailed study of

“There are 16 secondary registers provided for each ¢

the comprehensive reference data in Sections 3.2, 3.3,

the 16 multiplexed data channels, for a total of 250
secondary registers. The secondary registers make up

and 3.4, and to proceed directly to the procedural
data in Sections 3.5 and 3.6.

3.1

transfer control.

a separate Random Access Memory (RAM) within

PROGRAMMABLE FACILITIES AND

the DVI11. Secondary registers store functions that
may vary from line to line, and that require the exten-

FUNCTIONS

The DVIl
is a core memory-to- synchronous/asynchronous data line multiplexer with special
features to facilitate processing of a wide variety of

sive storage capacity of the RAM.

communication protocols. Under the overall direc-

Paragraphs 3.2 and 3.3, following a discussion of the

Functions of programmable registers are described in

tion of the PDP-11 program, the DVI11 sets up the

control table. Functions, functional categories, and

memory, monitors and reports error conditions, and

in Table 3-1, which is provided for reference during

data line modems, stores and retrieves data from core

table references for programmable registers are listed

examines each transmitted or received character to

study of Paragraphs 3.1.3 and 3.1.4.

3-1

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3-3

3.1.2

The mode field occupies bits 8, 9, and 10 and is
appended to the basic control table address to form

Control Table

The control table contains the control bytes fetched
from core memory by the DV 1 each.time a character

the actual address of the control byte. Thus, in the

is received or is to be transmitted. The control bytes

exampie above, the control bytes for character code

101 would be in location 4101 (mode 0), location

are used by the DVI1I to control processing of the
transmitted or received character.

4501 (mode 1), location 5101 (mode 2), etc. The con-

trol byte address formation sequence is graphically
depicted in Figure 3-1. Control byte formats are

3.1.2.1 Control Table Format - The addresses in
core memory for each line of the receiver and transmitter control tables are set in secondary registers by
the PDP-11 program. The DV11 adds the character
code to the base address to form the basic core memory address of the control byte for that character. For
example, if the base address of the receiver control
table for a given line is 4000 and the character 101
code is received (ASCII letter A), 4101 would be
effective core memory address of the associated con-

shown in Figure 3-2.

Receive Control Byte - Whenever a charac-

3.1.2.2

ter is input to the DV11 from the data link receiver,
the associated control byte is obtained from core
memory by a Non-Processor Request (NPR) to specify the next mode and to dictate character dis-

position. The following character dispositions are

trol byte.

provided:

With this scheme, 256 locations (2;) are sufficient to
provide control bytes for every possible 8-bit charac-

ter code. In the usual protocol, however, certain
codes are susceptible to more than one mode ofinterpretation, depending upon the sequence in which

or non-transparent. Thus, 3-bit mode specification

they are received and whether the data is transparent

fields are provided in secondary registers for each line
in the transmitter and receiver functions. Sequencing
between modes may be effected by the control byte,

Generate (or
interrupt.
|

not

Accumulate (or do not accumulate) the
character in the Block Check Character
(BCQC).

operate.

Expect the BCC (tréat the next character
as a BCQC).

ADDRESS

BITS

Table Base Address

Resultant

Address of

Control Byte

Co[eTeTo[eTo
[ [olole elee[o L[ T
| rOT‘l I‘ol o] oEo]ol«J

Character Code

pMode No.

8inary -

|
EXTENDED
ADDRESS
[N\

BED

Shiffed)

ST L
Figure 3-1

Store (or discard) the character.
~

which specifies the mode in which the DVI1 is to

Parameter

generate)

Control Byte Address

L P

]

INCLUDE
CHAR. IN BCC

SEND BCC

l SEND DLE

NEXT MODE

TRANSMIT CONTROL BYTE

RECEIVE CONTROL BYTE

X
\

—

—/

NEXT MOD

DISCARD /STORE

INTERRUPT

EXPECT
BCC

PROGRAM

INCLUDE CHAR
11-2682

- Figure 3-2

Control Byte Formats

The interrupt disposition provides for signalling the
program in the event oferror conditions, or data link
control characters requiring special handling. The
character that caused the interr :nt is loaded into the
RIC register. The program responds by sending a

special control byte to the DVI1, which would then

override the previous dispositions set for received
characters. The discard disposition provides for
inhibiting storage of data link control and other
unwanted characters. The do-not-accumulate disBCC
position provides for the exclusion of non-data,
anticipation signals characters from the error-checking process. BCC anticipation signals the DVII to
initiate data block termination procedure.

3.1.2.3

transmission command causes the DVI1 to retrieve

the DLE character from secondary register storage

and *“‘stuffs” the DLE in front of the character to be

3.1.2.4

Control Byte Symmetry - The receive and

so that a single
transmit control bytes are configured
transmit and
both
for
provide
will
table
control
“receive functions for a given line if the following functional limitations are observed:

The protocol must progress from mode to
mode in a symmetrical fashion for both

the same characters must be included in
the BCC for both tran_smit and receive.

ter is input to the DVI1 from PDP-11 core memory,

For protocols that do not meet these requirements,
separate control tables may be used.

tions are provided:

Accumulate (or do not accumulate) the
character in the BCC.

2. ) Send the BCC after t»he character_.'
3.

Sendv the DLE before the character.

transmit and receive;

Transmit Control Byte - Whenever a charac-

the associated control byte is obtained from core
memory by a NPR to specify the next mode and any
other processing instructions. The following instruc-

transmitted.

3.1.3

With

Operations

Registers

Directly-Addressable
|

The directly-addressable registers provide for modem
setup and control data transfer enabling, interrupt
enabling and reporting, extended-memory addressing
~and access to secondary registers (see Table 3-1).

3.1.3.1

Modem Set‘up and Control - Modem

enabling, monitoring, and control are provided by
the Control Status Register (CSR) and the Line Status Register (LSR) of the Modem Control Unit. Stepby-step procedures for accomplishing these functions
are contained in Paragraphs 3.5 and 3.6.

As in the case of the receive control byte, the do-not-

accumulate disposition provides for the exclusion of

non-data characters from the error-checking process.
The BCC transmission command signals the DV11 to
initiate data block termination procedure. The DLE

3.5

3.1.3.2

Accessing Secondary Registers - The Sec-

the character in the RIC register and resume withdrawing characters from the RC Silo.

ondary Register Selection Register (SRS) provides

for PDP-11 program access to the secondary registers
in the DV11 RAM. To address a secondary register,

3.1.3.5

the PDP-11 program sets the 8-bit RAM address,

is to access a core memory tables at extended memory

consisting ofthe 4-bit line number, plus the 4-bit reg-

locations, the basic 16-bit table address is set in the

ister selection code, in SRS 00-03 and SRS 08-11,

appropriate secondary register. The extended address

respectively.

Extended Memory Addressing - If the DV11

Loading or reading the SRS is then

bits are the set in SCR 04, 05. The DV11 appends the

accomplished by loading or reading the Secondary

extended address bits to the 16-bit table address and

stores the resultant 18-bit in the SRS (the RAM is 18

SRS must be saved by interrupt service routines.

bits wide).

Data Transfer Enabling - The System Con-

LCR bits 04, 05 display the extended memory address

trol Register (SCR) provides for clearing the Data

- bits for the secondary register selected by the SRS,

3.1.3.3

Handling Section (SCR 11) and starting the Micro-

for reading by the PDP-11 program.

processor (SCR 00) to enable the Data Handling Section. Individual receivers are then enabled by setting

3.1.4

the line number in bits 00-03 of the SRS, then setting

Processing

Receiver Enable in Line Control Register (LCR bit

accomplished almost exclusively with secondary reg-

13), coincident with the Control Strobe (LCR 15).

isters, as indicated in Table 3-1.

Protocol Processing

and

control

of protocol

functions is

Individual transmitters are enabled by setting Trans-

‘mitter Go (bit 02) in the Line State Sccondary

3.1.4.1

bits 03, 04 of the Line Protocol Parameters Second-

BCC Polynomial Selections - The code set in

ary Register selects the type of block check poly-

nomial to be applied to the transmitted and received
3.1.3.4

Interrupt

Enabling

and

Response -

Data

data for error-checking purposes. Longitudinal redu-

-Handling Section interrupts may occur as a result of

ndancy

receive function interrupt conditions or transmit func-

(CRC-16), and CRC/CCITT checks are prov1dcd

tion interrupt conditions. Receive function interrupts

for.

checks

(LRC),

cyclic

redundancy

checks

~occur as a result of error conditions, encounter of
data block boundaries, or upon fetching a control

3.1.4.2

byte for a received control character that specifies an

changes and BCC anticipations or transmission may

Processing

Block

Terminations

Mode

interrupt. Receive function interrupt information is

be effected at the end of a data block if the PDP-11

stored in the RIC register.

program sets a marked byte count into a byte count

secondary register. The mode change and/or BCC
- Transmit function interrupts occur as a result of error

conditions or data block boundaries being encoun-

command is then set by the PDP-11 program into the
~

appropriate secondary register before
or during the

tered. Transmit functions interrupt information is

data block receive or transmit interval. When the

stored in a first-in, first-out buffer; the output of this

byte count reaches zero, the “mark” is detected by

buffer forms the NPR Status Register (NSR). The

the

buffer (or “‘silo’) i1s monitored ot detect overflow.

and/or BCC command.

DVII,

which

responds to thc mode change

Receive function interrupts, transmit function inter-

Byte counts are set in 2’s complement form in bits

rupts,

when

00-14 of byte count secondary registers; the registers

set SCR 07, 15, 10,

are incremented with each byte transferred to count

and

NSR

silo overflow

enabled by SCR 06,

respectively.

13,

12,

interrupts,

them up to zero. Thus, a byte count may be marked

by setting bit 15 to zero at byte count set time. When
The PDP-11 program should set SCR 08 in response

the marked byte count reaches zero (00-14=0), bit 15

to a receiver interrupt, enabling the DVI11 to process

1S set to one, enabling the DV11 to detect the mark.

3-6

3.1.4.3

Control Byte Inhibit - For protocols such as

DDCMP,

which do

not

require arbitrary

mode

changes within a data block, provision has been made
to inhibit the control byte fetch cycle. All characters

BISYNC transparency operation, idling of a sync
causes a4 bad BCC and hence a NAK from the remote
terminal. Thus, the Transmitter Underrun bit
indicates whether the NAK is the result of line errors

are included in BCC, and all are stored. The PDP-11
program sets the inhibit bit in the Line Protocol

or idling syncs.

Parameters secondary register (bit 05 for receive, bit

3.1.5

06 for transmit). The inhibit is effective only when the

To establish a data transfer operation between core
‘memory and a selected data line for either transmis-

DV11 is in mode 0. If DDCMP is implemented with
control tables, but the Control Byte Inhibit feature is
desired, the control table must provide space for
mode 0, despite the fact that the hardware does not

Data Transfer Operations

sion or reception, the PDP-11 program must commu-

nicate the following basic information to the DV11:

actually reference that part of the table.

Theidentification of the selected data line.

3.1.4.4

The quantity of data to be transferred,

Sync Character Selection - Two sync charac-

ters (A and
B) may be manually set for each four-line

and

group (00-03, 04-07, 08-11, 12-15). Selection
of the

sync character for a line is then accomplished by set-

the address of the table of locations in
memory (the “data table”) for data read

ting the Sync A/B Selection bit (LCR 10) coincident

with

the

Control

Strobe

initialized to sync A (zero).
3.1.4.5

(LCR

15). The

bit

Sync/Mark State Select - The selected sync

character is also used as the transmitted Fill character. In lieu ofsyncs, the data line can be set to idle the
MARK state upon both byte counts reaching zero by

setting Line Protocol Parameters bit 00 to 1. Idling of

syncs takes place for a definite number of character

times. Idling of the

MARK

or write.

The PDP-11 program specifies the selected data line
number
‘in bits 00-03 of the SRS. The quantity of
data to be transferred is specified by loading a byte
count into the appropriate DV11 secondary register.

Similarly, the program loads the base address
of the

core memory table into the DV11 secondary register

provided.

state occurs for an

indeterminate period (i.e., synchronization is lost).

‘Using the data table address to access the corre-

3.1.4.6

sponding location in core memory, the DVI11 starts
the data transfer. As each byte is transferred, the
DVII increments both the byte count and the data

Stripping Received Syncs - Setting Line Pro-

tocol Parameters bit 01 to | causes sync characters

arriving after the achievement of synchronization,
but before the first non-sync character, to be stripped

from the incoming data stream (i.e., not stored in the
RC Silo). Sync characters with which the recerver

achieves sync are stripped in any case.

3.1.4.7

Line Activity Snapshot - The PDP-11 pro-

gram can monitor conditions
on a selected line by
examining bits 00-07 of the Line State Register,
which provide a snapshot of line activity. Of particu-

lar interest in Line State 03 (Transmitter Underrun).

This is set to one by the DVI1 whenever data is not

available in time for the synchronous transmitter,
and indicates that one or more idling syncs have been

sent. In byte count-oriented protocols or in IBM’s

table address (termed the “‘current address’’). When

the byte count reaches zero, the DV11

initiates data

block termination procedure
and halts data reception
for the corresponding line. (Data transmission is handled somewhat differently, as will now be described).
3.1.5.1

Provision for Alternate Data Transmission

Tables - By means of the data sequencing method
just described, data can be transferred between core
memory and the selected data line at the maximum

DVI11 throughput rate. However, if more than one
data table is to be transmitted, the program would

have only the transmission time of the last byte ofthe
previous table in which to establish a current address
and byte count for the next message, unless a double-

The DVI11 provides such a double-register system in

Start the DVI1 Microprocessor

the form of two registers for storage of transmitter
‘current addresses and two registers for storage of
transmitter byte counts. The registers are called prin-

Enable DVII data interrupts and detect
interrupt requests

cipal current address, alternate current address, prin-

Restart DVI11

cipal byte count, and alternate byte count. Thus,
while the DVI11

is transferring data from the table

defined by the principal current address and byte
count, the PDP-11 program may establish and load

the alternate current address and byte count. When
the principle byte count reaches zero, the DV11

Data Handling Section

after receiver interrupt and
Set the extended address bits to the DV11

for core memory addressing by the DV11.

con-

The SCR also provides PDP-11 program control of

tinues the data transfer operation, without interruption, by switching to the alternate registers and

Microprocessor ROM functions and provides simu-

notifies the PDP-11 program, which may then load

lated

the primary registers. This seesaw activity continues

purposes.

transmission mterrupts

for

maintenance

until both byte counts are zero, at which time trans-

Format of the SCR is displayed in Figure 3-3. Bit

- mission stops.

assignments are described in detail in Table 3-2.
3.1.5.2

Table Size and Location -~ Any memory location, including those with extended address, may be
used and data tables may cross extended address
boundaries. Messages to be transmitted or received

3.2.2

PDP-11 program in order to:

may comprise data tables of up to 16,384 bytes.

3.2

Line Control Register (LCR)

The Line Control Register is intended for use by the

Enable reception on a selected line

DIRECTLY-ADDRESSABLE REGISTERS

Read the extended address bits used for

core memory addressing by DV11 second-

The DV11 contains 10 registers which may be directly

ary registers, and

addressed by the PDP-11 program. Formats, designations, addresses and mnemonic codes for these reg-

isters are displayed in Figure 3-3. The System Control
Register (SCR) and the Line Control Register (LCR)

are used by the PDP-11 program principally to set up

data transfers. The Control Status Register (CSR)
and the Line Status Register (LSR) are used to set up

the line modems. Other directly-addressable registers
are provided to enable interrupt interpretation and
handling, access to DV 11 secondary registers, and for
maintenance functions.
|
The

bit

description

the PDP-11 program. If a bit may be physically read
by the program but the datum read is not valid, it is

listed as “‘write”” with the *“‘only” omitted; the converse case is similarly treated.

implements

the

principal

DVll

The following LCR bit descriptions apply only to
those lines associated with
a synchronous line card.

The enabling of reception is controlled by separate
storage for each line. This is accomplished by using

PDP-11 program. The Sync Character Selection bit
(LCR 10) and Maintenance bits LCR 09, 11, 12, and

14 are set in separate storages for each four-line
group (00-03, 04-07, 08-11, and 12-15, as selected by

SRS 02-03) by LCR 15 strobe. Consequently, LCR

bits 09-14 are not valid for a line selected at a random

point in time and so are designated as write bits.
Since LCR 15 strobes 09-14, programs must update

The System Control Register is a byte-addressable
register for use by the PDP-11 program in order to:
I.

also

in SRS 00-03 at the time that LCR is set to | by the

only, write only, or may be both read and written by

System Control Register (SCR)

LCR

mamtenance functlons

LCR 15 as a strobe pulse generator to load LCR 13
(Receiver Enable) into control storage for the line set

tables contain a

read/write column to indicate whether bits are read

3.2.1

The

‘Select the sync character(s) for each linc

all of the bits 09-14 when it is desired to update any
one of these bits. The LCR format for synchronous

Initialize the Data Handling Section of

line cards is displayed in Figure 3-3. Bit assignments

the DV11 Master Clear

are described in detail in Table 3-3.

3-8

NPR STATUS INT

INTERRUPT

MASTER

RECVR. INT

SERVICE

WRITE ENABLE

INTERRUPT

ADDRESS

BITS

07.

‘

CONTROL
STROBE

STEP

ROM BRANCH

u PROC

DISABLE

11-2684

]

ARE. READ- ONLY
)
'

11-2685

ENABLE

SYNC A/

|MAINTENANCE

SYNC B

CLOCK

DATA

MODE"

TRANSMITTER
DISABLE
T

TRUE

BITS

WINDOW
'

BRANCH

'ADDRESS

MAINT BIT

EXTENDED
-

X \R RER i
B

- l

I b

RECEIVER

11-2686

LINE CONTROL REGISTER
(LCR) 775004 (FOR SYNCHRONOUS
LINE CARDS).

MAINTENANCE ~ MAINTENANCE -

INTERRUPTING CHARACTER

(ALL BITS

EXTENDED

RECBVERINTERRUPT‘CHARACTER REGBTER(RI(H 775002
T

|ROM SINGLE

SOURCE

e—— INTERRUPT CODE ——te——— LINE NUMBER

]

ROM DATA

ENABLE

COMPLETE
15
-~ RECVR

BIT

CLEAR
.

REC INT

INT

ENABLE

OVFLOW INT | NPR OVFLOW|

NPR

]

)

- SYSTEM CONTROL REGISTER (SCR) 775000
12
1. 10 09 08
07
06
05 04

|
13

LINE CONTROL REGISTER (LCR) 775004 (FOR ASYNCHRONOUS
LINE CARDS)
15

wol

ow | w | ow

ASYNCHRONOUS

"STROBE

LINE CARD
REGISTERS

x | R

*‘;;_‘*J
7 REGISTER

——

[ -

CONTROL

SELECTION
CODE

x | R

R |

N —

ADDRESS

TRUE

EXTENDED

BRANCH

BITS
11-4407

|
15

‘SECONDARY REGISTER SELECTION REGISTER (SRS) 775006

—

~——

UNUSED

~—

——

UNUSED

‘LINE SELECT

.
14

]

SECONDARY REGISTER ACCESS
15

11-2687

]

DATA TO/FROM SECONDARY REGISTER SELECTED BY SRS REGISTER

11-2688

Figure 3-3 DVI11 Primary Registers (Sheet 1 of 3")

3.9

SPECIAL FUNCT!ONS REGISTER (SFR) »775012

1 10

ROM DATA REGISTER CONTENTS |
-2689

NPR STATUS
15

——
o

g’:'T-'RQ
IN

—

UNUSED

00-1

—

—_—

INTERRUPT CODE

UNUSED

VIS

—

LINE NUMBER

11-2690

RESERVED REGISTER (RIR) 775016
.15

1-2691

CONTROL STATUS REGISTER (CSR) 775020 (FOR SYNCHRONOUS LINE CARDS)
15

/’f,

.08

LINE NUMBER
RING

LEAR TO

CLEAR

TRANSITION | SEND TRARS
CARRIER

SCAN

DATA SET

TRANSITION . READY TRANS

| MAINTENANCE

DONE

~ MODE

CLEAR

STEP

MUX

SCAN

ENABLE
INTERRUPT

ENABLE

11-2692

CONTROL STATUS REGISTER (CSR) 775020 (FOR
1S

|. /

;

RING
TRANSITION

CLEAR

| SEND TRANS

CARRIER

CLEAR

TRANSITION

»’

041

|
LINE

MAINTENANCE

SCAN

SECONDARY
RECEIVE

ASYNCHRONOUS LINE CARDS)

O7?

DONE

MODE

CLEAR
MU X

'SCAN

NUMBER

ENABLE

STEP

INTERRUPT

BUSY

ENABLE

11-4408

Figure 3-3 DV11 Primary Registers (Sheet 2 of 3)

3-10

LINE STATUS REGISTER (LSR) 775022 (FOR SYNCHRONOUS LINE CARDS)
15

R |

)

UNUSED

'“l

RING

CLEAR TO

NEW

SEND

SYNC

CARRIER ON

DATASET
READY

TERMINAL

READY

REQ TO

LINE

SEND

ENABLE

MODEM STATUS

——

MODEM CONTROL
i1-2693

LINE STATUS REGISTER (LSR) 775022 (FOR ASYNCHRONOUS LINE CARDS)
15

071

=
T
S

INUSED

UNU

RING

CLEAR
TO

SEND

CARRIER

MODEM

STATUS

SECONDARY

RECEIVE

REQ TO

SECONDARY

TRANSMIT

LINE

SEND

ENABLE

TERMINAL

READY

MODE
M

LEGEND
R=READ ONLY

CONTROL

wW=WRITE ONLY
W1= WRITE ONES ONLY

X: UNUSED

= FOR MAINTENANCE ONLY

Figure 3-3 DV11 Primary Registers (Sheet 3 of 3)

311

11-4409
:

Table 3-2

System Control Register Bit Assignments
Bit(s)

Designation

Function

Microprocessor GO

When set to one, enables the Microprocessor to

Read/Write
Read or Write

operate the DV11 Data Handling Section. Must
be set to one to enable DV11 to perform any

functions other than modem control. Cleared
by Initialize.

01-03

(Maintenance)

04-05

- Extended Address

The contents of these bits as set by the PDP-11

Write

program form bits 16 and 17, respectively,
of

any current address or control table base address
loaded by the PDP-11 program into a secondary

~ register for the line selected
by SRS 00—03.
These bits must be set before loading the
- Secondary register. These bits are read/write,

but when read reflect only the values of SCR
'04—05,and not the values of address bits 16 and
17 for the selected line. (Refer to the discussion

-+ .of Line Control Register bits 04—05.) Thus, an
interrupt service routine saving the contents of

these bits will store bits 04—05 exactly as set by

the PDP-11 program. Cleared by Initialize.
06

When set to one by the PDP-11 program, enables

Receiver Interrupt

Read or Write

the Microprocessor to interrupt the PDP-11 program by setting a one in SCR 07. Cleared by
-

Initjalize.

Receiver Interrupt

Set to one by the DV11 to request a PDP-11 pro-

(Vector A)

gram interrupt occurring during data reception.

Read or R/W

The reception conditions that cause the DV11 to
request an interrupt are listed in Table 3-3. The

PDP-11 program should respond to the interrupt

by reading the Receiver Interrupt Character Register to identify the condition and may then load

the Receiver Control Byte secondary register with
a new control byte. The PDP-11 program should

then set SCR 08.- SCR 07 does not cause an inter-

rupt unless SCR 06 has been set to one by the
PDP-11 program. Cleared
by Initialize. This bit
is read only except when SCR 09 is set, in which

case it is read/write.
08

Receiver Interrupt

Set to one by the PDP-11 program when it has com-

Service Complete

pleted an interrupt service routine and desires

Microprocessor servicing of the character in the
Receiver Interrupt Character register. Setting of

this bit clears SCR 07. Cleared by Initialize.

3-12

Read or Write

~ Table 3-2 (Cont)

| SyStem Control Register Bit Assignments
Bit(s)

Designation

Function

Read/Write

NPR Status OVerflow

Set to one by the MicroproCessor whenever the

Read or Write

(Vector B)

NPR Status Register/silo is full. Failure occurs

(Maintenance)

whenever the 851

program does not promptly

read the NPR Status Register contents following
a SCR 15 interrupt, and 64 NPR status entries
have occurred. SCR 10 does not cause an inter-

rupt unless SCR 12 has been set to one by the
PDP-11 program. Cleared by Initialize.

Master Clear

When set to one, clears the following bits in the

DVI11:

Read or Write

SCR bits 0-3,6.7,9,10.11,12,13,15
RIC bits 0--15

LCR bits 7- 14
NSR bit

~ The Received Character Silo is also cleared. This
bit is self-clearing.

NPR Staths Overflow B

When set to one, enables the setting of SCR 10 to

Read or Write

- generate an interrupt request. Cleared by Initilize.

NPR Status lntgrrupt, :

When set to one, enables the setting of SCR 15to

Read or Write

Enable

- generate an interrupt request. Cleared by Initialize.

NPR Statusv_lnterfupt_"‘

- Set to one WheneVer the Microprocessor loads data

Interrupt Enable

(Vector B)

into the NPR Status Register to report an interrupt

- condition occurring during data transmission. Set

to zero whenever the PDP-11 program reads the

NPR Status Register. This bit is read only except
when Bits 07 and
15 Write Enable (SCR 09) are

set to one, in which case it is read/write. SCR 15

does not cause an interrupt unless SCR 13 has
been set to one by the PDP-11 program. Cleared
| by Initialize.

3-13

Read or R/W

Table 3-3

Line Control Register
Bit Assignments

Bit(s)

| OO——Oll
02-03

(For Synchronous Line Cards)

Desiéfiation .[

(Maintenance)
|

04-05 |

Extended Address
|

‘Read

Function

Unused

|
o

- ~ For the secondary register selected by SRS

- 00-03 and 08—11, these bits display the con-

Read/Write

Read only

tents of bits 16 and 17, respectively. This en~ ables the program to read the extended address
bits of the current address and control table base
‘address secondary registers.

07-09

(Maintenance)

Sync Select

Unused

—

For the line selected by SRS 00—03, this bit sets

Wtite

Sync A character or Sync B character, depending

- on whether this bit is set to zero or one, respec-

’ti'Vely‘,‘.at LCR 15 set time. Cleared by Initialize.
Sync character encoding is discussed
in Chapter 2.

11,12
13

~ (Maintenance)
Receiver Enable
|

'
=

When set to one at LCR 15 set time, causes the

receiver for the line set in SRS 00-03 to search
for the synchronization character(s) in the input
bit stream. When the synchronization character(s)

is found, the Microprocessor sets the Receiver

‘Active bit in the Line State secondary register.
LCR 13 must be set to one to enable reception on
a line following Initialize. This bit is not used for
resynchronization during reception.

To resynchronize dUri_n_g reception, the Receiver
Resynchronize bit in the Line State secondary

. register is set toone.
To shut down reception in a line, the line number

is set in SRS 00—03 and LCR 13 is set to zero at
LCR 15 set time. The Receiver Resynchronization bit in the Line State secondary register is

then set.
Cleared by Initialize.

(Maintenance)

3-14

Write

‘Table 3-3 (Cont)
Line Control Register Bit Assignments

(For Synchronous Line Cards)
~

Bit(s)
15

Designation
-

Function

Control Strobe

When set to one, strobes LCR 13 into control

Read/Write
Write

storage for the line set in SRS 00—03 and strobes

LCR 09, 10, 11, 12, 14 into control storage for
the 4-line group sct in SRS 0203, then clears

itself. May be set at the same time as the LCR

. bits that it strobes into storage for the selected

line or line group.

The format of the RIC is shown in Figure 3-3. VS“pe'cif—

The following LCR bit descriptions apply only to
those lines associated with an asynchronous line card.

~ic bit assignments for the RIC are as follows:

For asynchrdnous line cards, ea“ch"line"has four 4-bit
Bits 00-07: This field contains the inter-

registers associated with it, each of which may be
loaded by addressing the LCR with appropriate register selection bits set in LCR 09 and 10, in addition

to the line selection bits set in SRS 00-03. The four

registers associated with each line are called the

“Primary,” **Format,” “Baud Rate,” and ‘‘Mainte-

the highest order bitin the charactcr

nance’ registers and are selected by LCR 10-09 codes

of 00, 0I, 10, and 11 respectively. While the bit

'Bits 08-11: This ficld' contains the line num“ber on which the interrupting character was
received. Bit eight is the least significant bit.

assignments are described
in detail in Table 3-4, it canbe noted here that LCR 15 (Line Control Strobe)
functions the same for asynchronous line cards
as it"
does for synchronous line cards and that the cautions

expressed above with regard to LCR bits 09-14 are
similarly valid for the asynchronous case. The LCR
format for asynchronous line cards is displayed in
Figure 3-3. Bit assngnments are descnbcdin detail iin

Table 3-4.

3.2.3

rupting character, right-justified. Bit 00 is the

least significant bit. On parity-equipped synchronous characters of less than eight bits, the
parity bit will appear immediately to the left of

~
|

Bits 12-15: This field contains the code specifying the reason for the interrupt. Refer to
Tables 3-5 and 3-6 for code meanings.

324 NPR Status Register (NSR)

The NPR Status Register is a 64-level “read-once”

Receiver Interrupt Character Register (RIC)

silo; that is, a read ofthis silo ‘“‘empties” it of its old-

The Receiver Interrupt Character Register is a read- " est entry (destructive read), and any new data “falls”
only register which stores the character that caused
~into the silo output if new data is waiting when a read
the PDP-11 program interrupt,
the line number on

which the character was received, and the code speci-

is completed. The NSR is read-only register which
identifies (1) interrupt-causing conditions that occur

fying the reason for the interrupt. This register is

during character transmission and (2) the line num-

cleared by Initialize.

ber on whnch the mtcrrupt occurrcd

3-15

Table 3-4
Line Control Register Bit Assignments
(For Asynchronous Line Cards)

Bit(s)
00,
01

(Maintenance)

—

02,03

04, 05

Read/Write

Function

Designation

Unused

Extended Address B

For the secondary register selected by SRS 00-03

Read only

and 0811, these bits display the contents of bits

Read

16 and 17, respectively. This enables the program
to read the extended address bits of the current
address and control table base address secondary
registers.

06, 07, 08
09,10

Unused

——

For the line number selected by SRS 00—03, the

Code

code bits determine which Asynchronous Line

Write

Card register is written into at LCR 15 set time.

There are four registers associated with each line
and they are called ‘“Primary,” “Format,” ‘“Baud
Rate,” and “Maintenance” registers. Descriptions

| ~ of the register bits are found in LCR 1114,
Cleared by Initialize.
11-14

Asynchronous

This is the path provided for access to the line card

Line Card

registers. Loading of a register occurs at LCR 15

Registe rs

‘Write

set time and is dependent on the line number

selected by SRS 00—03, and the register selection

code set in LCR 09—10. Each line has four 4-bit
registers associated with it, designated as:

“Primary,” “Format,” “Baud Rate,” and
“Maintenance.” These registers are cleared by
Initialize. Bit assignment description of the
registers follows LCR 15 functional description.

When set to a one, strobes LCR 1 l",- 12,13, 14 into

Control Strobe

Write

control storage for the register selection code set

~in

LCR 09-10 and the line specified by SRS
00—03, then clears itself. May beset at the same
time as the LCR bits that it strobes into storage

for the selected register.

//,.\\

PanhaN

Table 34 (Cont)

‘Line Control Register
Bit Assignments
(For Asynchronous Line Cards)

Bit(s)

Designation

Function

‘Read/Write

Asynchronous Line Card Primary Register

09,10

Primary Register

“For the line number selected by SRS 00-03,the

Selection Code 00
|

Half Duplex/
Full Duplex

[

This bit, when set, conditions the line to operate in
half duplex mode. If this bit is cleared, the line is

Write

code of 00 specifies writing into the Primary

Write
-

‘conditioned to operate in full duplex mode. When

operating in half duplex mode, the selected receiver

is blinded during transmission of a character.

“Even Parity '

This bit, when set. gencrates‘characters with even

parity on the line and expects received characters

‘Write

to have even parity. If this bit
is cleared, characters
of odd parity are generated
on the line and received

characters are expected to have odd parity. The
|

state of this bit is immaterial if the Parity Enable

- bit (Format register bit 14)
is not set. This bit
must be conditioned prior to loading the Format

Receiver Enable
|
-

This bit must be set before the receiver logic can
assemble characters from the serial input line. When

Write
o

this bit is set, Receiver Active (Line State Bit 00)

is subsequently set. To shut down reception on a
line, the program should first clear Receiver Enable

and the set Receiver Resynchronize (Line State

Bit 01). The program must wait one character
‘|

Break

‘

interval after shutdown before restarting a line.

This bit, when set, forces a space on that line’s

output causing a break condition. The break con-

’

Write.

~dition may be timed by sending characters during

the break interval, since these characters never

reach the EIA line.

Control Strobe
|

When set to a one, strobes the Primary Register

bits 11, 12, 13, 14 into storage for the line speci-

. fied in SRS 0003, then clears itself. May be set

at the same time as the bits that it strobes into
storage.

3-17

Write

Table 3-4 (Cont)
Line Control Register Bit Assignments

(For Asynchronous Line Cards)

Bit(s)

Pesignation

- Function |

Read/Write

Asynchronous Line Card Format Register

09,10

For the line number selected by SRS 0003, the

Format Register
Selection Code 10

code of 10 specifies writing into the Format
register at LCR 15 set time. LCR 09 = 1, LCR
10=0.

11, 12

Character Length
|

These bits are set to transmit and receive characters
1

- Two Stop Bits

Write

of the length (excluding parity) as shown below.
—_—0
O N

Selected Character Length

5 bits

0
1
0

|
-

6 bits
7 bits

8 bits

This bit, when set, conditions the line transmitting

Write

with 5, 6, 7, or 8 bit code to transmit characters

having two stop bits. One stop bit is sent when this
bit is cleared.

Parity Enable

If this bit is set, characters transmitted on the line

Write

have an appropriate parity bit affixed, and characters received on the line have parity checked. Parity

- sense is determined by the state of Primary Register
bit 12,

Control Strobe

‘

When set to
a one, strobes the Format register bits

Write

11,12, 13, 14 into storage for the line specified in

SRS 0003, then clears itself. May be set
at the
same time as the bits that it strobes into storage.

Asynchronous Line Card Baud.Rate Register
09, 10

11-14

Baud Rate

" For the line number selected by SRS 00—03, the

code of 01 specifies writing into the Baud Rate

Selection

Code 01

10=1.

Speed Code

The state of these bits determine the operating

speed for the transmitter and receiver of the
selected line.

3-18

Write

Table 3-4 (Cont)

Line Control Register Bit Assignments
(For Asynchronous Line Cards)

Bit(s)

Designation

“

“Function

Read/Write

Asynchronous
Line Card Baud Rate Register (Cont)

11-14 (Cont)
o

14
0
0
0
0

13
0
0
0
0
1

150

1
1

0
1

1
0

300
600

-0

1200

2400

3600

-0

4800

1
I
Control Strobe
R

Baud Rate
50
5
110
1345

11
0
1
0
1

0
S0

12
0
0
1
]

1800

2000

7200

11
B

0
1

9600
38,400*

|~ When set to a one, strobes the Baud Rate register
o

Write

bits 11, 12, 13, 14 into storage for the line specified

in SRS 0003, then clears itself. May be set at the
same time as the bits that it strobes into storage.

*Special Interface Leads For High Speed Op‘e'ratio'n .

DV1li Buw" A response that originates from an asynchronous receiving line to mdlcate that the character servrcmg rate for that line
is not being sustained. Toinsure received data integrity, external hardware must interpret and implement this response in such a

fashion to provide a restraining feature on the remote transmitter. The “ON"’ condition of DV11 Busyisindicated by a negative voltage-

in the 3 to 15 volt range. The “OFF" condition of DV11 Busy is indicated by a positive voltagein the 3:to 15 volt range. DV11 Busy

is in the off state followmg a Unibus lmtrahze DVll Master Clear, or Receiver Enable cleared (LCR anary Regrster bit 13). The ON
duration of this lead is dependcnt on the servicing rate of the DV11 Character ProcessorTherefore, DV11 Busy may be of any minimal
period. DV11 Busy is asserted a maximum of 10/16th of a bit time followmg receptlon of the frrst stop blt l'or an operatmg speed of
38,400 baud, the DV11 Busy featurc must be used.

Data Set Busy The capabrhty of an asynchronous transmitting line to have contmual transmrssron remotely started and stopped |
Thisis the complementary featurc of DV11 Busy. Data Set Busy must be implemented with external supporting hardware and must
be used with an operating spced of 38,400 baud. Line card modification is required for implementing Data Set Busy at a baud rate

other than 38,400 baud. The “ON" condition of Data Set Busy is interpreted by a negative voltage in the 3 to 15 volt range. The

“OFF” condition of Data Set Busy is interpreted by a positive voltage in the 3 to 15 volt range. Data Set Busy, when on, is defined as

a remote stop request. To inhibit continual character transmission, Data Set Busy must be received prior to 15/16th of the last stop

bit interval. Data Set Busy is invalid when the line is being operated in either internal maintenance mode
or at an operating speed less
than 38,400 baud, assuming no linc card modification was performed.

3-19

Table34(Cont)
Line Control Register Bit Assignments

(For Asynchronous Line Cards)
~ Bit(s)

Designation

Function

Read/Write

Asynchronous Line Card Maintenance Register

09, 10

Maintenance

For the line number specified by SRS 00—03, the

code of 11 specifies writing into the Maintenance

Selection

Code 11

Maintenance

This bit, when set, lobps the transmitter’s serial output

Internal Mode

lead to the receiver’s serial input lead. While operating

Write

Write
A

in maintenance mode, the EIA transmit data leads,

EIA received data leads, and the remote Data Set busy
features are disabled. Normal operating mode is

assumed when this bit is cleared.
12—14

Unused

Control Strobe

—

When set to a one, strobes the Maintenance register

Write

bit 11 into storage for the line specified in SRS
00-03, then clears itself. May be set at the same
_time_ as the 'bi_t t_hat it strobes into storage.

Interrupt-causing

conditions

and

associated

3.2.6

line

Special Functions Register (SFR)

The Special Functions Register is used for mainte-

numbers are stacked in the 64 entry first-in, first-out

silo buffer and dropped into the NSR output as each

nance only.

prior entry is read by the PDP-11 program. Each time

a new entry is dropped into NSR output, NSR 15 is

3.2.7

set to indicate the presence of valid data and SCR 15

The Secondary Register Selection Register provides
for PDP-11 program access to the secondary registers
in the DVI1 RAM. To address a secondary register,
the PDP-11 program sets the 8-bit RAM address,
consisting of the 4-bit line number, plus the 4-bit reg-

is set to request an interrupt. Each time
an NSR entry

is read by the PDP-11 program, NSR 15and SCR 15

are reset to zero. NSR

15 is also set to zero by

Initialize. (The other NSR bits are not reset
to zero

Secondary Register Selection Register (SRS)

ister selection code, in SRS 00-03 and SRS 08-11,

by initialize.)

‘respectively. Loading or reading the SRS is then

accomplished by loading or reading the SAR. Inter-

"The NSR‘ format is shown in Figure 3-3. Transmission interrupt codes are described in Table 3-7.

rupt service routines must save the contents of the
- SRS.

The 4-bit line selection code in SRS 00-03 provides
for selection of the 16 data lines. The 4-bit register

3.2.5

Reserved Register

selection code in SRS 08-11 provides for selection of
the 16 secondary registers supplied for each data line.

Reserved for future system requirements.

3-20

Table3ds

Receive Function Interrupt Conditions
~ (For Synchronous Line Cards)
Code Set in RIC 1215

Meaning

Special Character Received:

- Bit 00 of the control byte for the characterin RIC 00—07 is set to one (generate mterrupt) mdrcatrng that the received characteris a special character.

Panty Error

The characterin RIC 00—07 has a panty sense opposite to that selected for

this line (the line specified in RIC08—11) by the parity sense sw1tches on the
M7839 module (Figure 2-6).

| Overrun:

‘

The received character(s) preceding the character set in RIC 00—07 have been
- lost because of overflow of the Received Character Silo.

Parity Error and Overrun:

As described above for error codes OOOl and 0010.

Byte Count Warnrng

The character set in RIC OO 07 has been stored in core memory No more
|

]

characters may be stored for this line as the byte count is now zero.

Block Check Complete

The block check character(s) for the data block received on this line have
arnved and have been included in the Accumulated BCC. The Accumulated
BCCis now in the Receive Accumulated Block Check Character secondary
register; the OR of the high and low bytes of the accumulated BCC issetin
|

RIC 00 07.

Undefined

-0

‘Byte Count Zero:

The receive byte count for this lme was zero prior to recerpt of the character
~set in RIC 00--07. Thus. the character was not stored as no assigned storage
was available.

0o |

* 'Undefined

Undefined

Processmg Error 00:
A non-existent memory time-out occurred when the DV11 attempted to store
- the character set in RIC 00— 07

1
|

0 \,

vProcessrng Error 01:

A non-existent memory time-out occurred when the DVl 1 attempted to fetch
| the control byte correspondrng to the character set in RIC OO 07.

3-21

Table 3-5 (Cont)
Receive Function Interrupt Conditions

(For Synchronous Line Cards)

Code Set in RIC 1215
14

Meaning

Processing Error 10:

The DV11 received a signal on the memory parity error line from the PDP-11
~when the DV11 attempted to store the character set in RIC 00—-07. This condition indicates a defect in the memory parity logic, as the PDP-11 generates
parity error signals only on core memory read operations.

Processing Error 11:

A memory parity error occurred when the DV11 attempted to obtain the con-

trol byte corresponding to the character in RIC 00-07.

Table 3-6

Receive Function Interrupt Conditions
(For Asynchronous Line Cards)

Code Set in RIC 1215
12
13
14 |
15
0

Meaning
-

Special Character Received:

)

(generate interrupt), indicating that the received character is a special character.

Bit 00 of the control byte for the character in RIC 00—07 is seto a one

| Parity Error:

The character in RIC 00—07 has a parity sense opposite to that selected for this
line (the line specified in RIC 08—11) by the programmable Format registers of
the Asynchronous Line Card.

Overrun Error:

The received character(s) preceding the character set in RIC 00—07 have been

~ lost because of overflow of the Received Character Silo.

Framing Error:
The character set in RIC 00—07 lacked a stop bit present at the proper time.
This code is usually interpreted as indicating the reception of a break.
Byte Count Warning:

~ The character set in RIC 00—07 has been stored in core memory. No more characters may be stored for this line as the byte count is now zero,

]

~ Block Check Complete:

The block character(s) for the data block received on this line have arrived and
have been included in the Accumulated BCC. The Accumulated BCC is now in
~ the Receive Accumulated Block Check Character secondary register; the OR of

~ the high and low bytes of the accumulated BCC is set in RIC 00-07.
p—

3-22

Table 3-6 (Cont)

Receive Function Interrupt Conditions
|

(For Asynchronous Line Cards)

Code Set in RIC 1215
15

- Undefined

Undefined

Meaning

Byte Count Zero:

" The receive byte count for thrs lme was zero prior to receipt of the character set
in RIC 00--07. Thus, the character was not stored as no assigned storage was

available.
1

Undefined

‘Undefined

-0

Processing Error 00:

Undefined

A non-existent memory time-out occurred when the DV] ] attempted to store

the character set in RIC 00--07.

-0

Processing Error O1:

| |
|

A non-existent memory time-out occurred when the DVll attemptedto fetch

1| 1

the control byte correspondrng to the character set in RIC 00-07.

| Processrng Error 10:

A DVII received signal on the memory parity error line from the PDP-11 when
~ the DV1 I attempted to store the character set in RIC 00-—07. This condition
indicates a defect in the memory parity logrc as the PDP l ] generates parity
error signals only on core memory read operatrons

1
|

" 'Processmg Error 1

~ A memory parity occurred when the DVl 1 attempted to obtam the control
| ,byte correspondmg to the characterin RIC 00-07.

NOTE

A prrorrty encoding scheme is used by an asynchronous line to present a multrple error code condltron Any
error flag combination that contains an overrun error is presented as an Overrun Error (code 0010)in the

'RlCR register. A framing error and parity error combination is presented as a Frammg Error (code 0011)in
the RICR register. A multiple error condition that displays a Parity Error (code 0001) does not exist. This
priority scheme is used only by the Asynchronous Line Card. Exrstmg error code brts that are generated on

a synchronous line are not affected by this scheme.

3-23

Table 3-7

TM,

(

Transmit Function Interrupt Conditions
Code Set in NSR 08—11

Meaning

Transmitter principal current address specified a non-existent memory loca-

|
0

tion (NXM).

Transmitter principal byte count is equal to zero.

Transmitter alternate current address specified a non-existent memory loca-

o tion (NXM)

]

Transmitter alte‘rnate byte count is equal to zero.

An attempted control byte fetch by the DV11 produced a non-existent mem-

ory condition or a memory parity error. (The specific error is set in the Line
~State secondary register.)

SRS 00-03 are also used to select line control storagc |

number 1n the CSR, then sets the Line Enable bitin

for loading from the Line Control Register.

the LSR.

CAUTION

Do not change the contents of SRS without checking
that LCR 15 is cleared, indicating that any outstanding

" Formats for the CSR and LSR are displayéd in Fig-

ure 3-3. Bit assignments are described in detail in
Tables 3-8 and 3-9, respectively. Some bit assignments have dual definitions to reflect the type of

LCR load to the line cards has been completed.

3.2.8 Secondary Register Access Reglster (SAR)
The Secondary Register Access Register provides the‘

modem that is being controlled (i.e., synchronous vs
asynchronous). Tables 3-8 and 3-9 define each bit
- assignment as it applies to both modem types.

PDP-11 program with direct access to the secondary
register selected by the SRS register. Loading or reading the SAR is equivalent to loading or reading the
secondary regrster addressed by SRS 00—03 and
08-11.

The interrupt mode is set for all enabled lines by setting CSR 05 and 06 each to one. CSR 05 (Scan
Enable) causes the MCU to scan the enabled modems

cyclically to detect a change or transition in one of
the modem status bits. When a transition is detected,

Modem Control Registers
|
PDP-11 program control of the line modems is

scanningis stopped, the condition causing the transi-

3.2.9

accomplished through the Control Status Register
in the

ister (LSR)

(CSR) and the Line Status Reg

Modem Control Unit (MCU) of the DV11. The CSR

controls data line or modem selection and operating
mode (interrupt or non-interrupt) of the MCU, and
enables the detection of changesin modem status by
the PDP-11 program. The LSR routes control bits

tion is set in the CSR 12-15 field, the line number for
the srgnalhng modemis availablein CSR 00-03, CSR
107 (Done bit)is set to one, and the PDP-11 program

~is interrupted.
Ld

The non-interrupt mode is feasible if only one modem
is to be monitored for activity at one time. The line
number for the modem is set in the CSR and modem

provided by the PDP-11 program to the modems and

status bits LSR 04-07 are continuously sampled by

transfers modem status bits to the Unibus for the
modem(s) selected via the CSR. To enable any one of
the 16 lines, the PDP-11 program sets the selected line

the PDP-11 program. When one of these status bits
becomes set

one,

respond by setting a 03.

3-24

the

PDP-11

program

may

Table 3-8

Control Status Register Bit Assignments
Bit(s)
00-03

LINE (Line Numb_ern)

Réad/Write

Function B

Designation

Read or Write

Binary address of one of 16 modems:

Bt 3

2 1

LineNo.

]

Cleared to 0000 by Initialize or Clr Scan (bit 11 of
CSR). Sixteen microseconds +lO% settling time is
required.

- This portion of the CSR is a presettable binary

counter; thus, it may be loaded directly by the
PDP-11 program to address a selected data line, or

advanced by SCAN EN (CSR bit 5) or STEP (CSR

bit 8) to address sequential data lmes
BUSY

Set to 1 whenever modems are being cyclically

scanned or a Clr Scan (CSR bit 11) is being

Read only

- executed.
05

SCAN EN

Causes cyclical scanning of status lines from all

(Scan Enable)

enabled modems when set to 1 if Done (CSR bit

Re:ad or Write

7) is set to 0. Scanning stops and Done is set to
I when a status transition is detected. A 1.2
microsecond period is required for scanning to
come to a halt when the PDP-11 program changes

this bit from 1 to 0; therefore, Busy (CSR bit 4)
must be tested for its zero state before changing

the line number (CSR bits 0—3) to ensure that
all detected transitions are serviced. Cleared by
Initialize and Clr Scan (CSR bit 11).
06

INTER EN

(Interrupt Enable)

Enables Do“ne signal from CSR bit 7 to cause a
PDP-11 interrupt on priority four when set to 1.

Cleared by Initialize and Clr Scan (CSR bit 11).

3-25

Read or Write

Table 3-8 (Cont)

Control Status Register Bit Assignments

Bit(s)

Designation

DONE

Read/Write

Function

Set to one whenever a transition occurs on a
status line (RING, CO, CS, DSR) from an

Read or Write

enabled modem during the modem scanning

process, as initiated by Scan En (CSR bit 5).
When Done is set to one, the scan stops and the

status transition(s) are set in CSR bits 12—15.
The line number of the modem with the new

status is in CSR bits 0—3, and the current states
of that modem’s status lines are reflected in LSR
bits 4—7. Cleared by Initialize and Clr Scan (CSR

bit 11).

STEP

When set to 1, causes the line number in CSR bits

0-3 to be incremented by 1. If a status transition
~ is detected for the new line, Done (CSR bit 7) is
set to 1. Done does not inhibit Step. This bit is

‘used principally for maintenance and requires
1.2 microseconds +10% to execute. This bit is
write ones only.

(Maintenance)
CLEAR MUX

Clears bits 4—7 of the LSR (RS, Term Rdy, NS,

Write ones

Line En) for all lines when set to 1. This bit is

write ones only.
11

CLR SCAN

" Clears bits 0-3, 5.6, 7.9, and 12—15 of the CSR
when set'to 1, and clears MCU “Scan Memory”’ in

18.8 microseconds £ 10%.

(The MCU detects modem status transitions by
storing the conditions of the several modems’

status lines in Scan Memory, then continuously
comparing the updated status conditions with

the previous status conditions during the modem
scanning process. Thus, if Scan En (CSR bit 5)
is set to 1 following a Clear Scan and the interrupt

‘mode is set, an interrupt will occur for all modems
which have ON status lines (DSR, CS, CO, RING),

as these will appear as OFF to ON transitions to
the MCU.)

3-26

Write ones

Table 3-8 (Cont)
Control Status Register Bit Assignments

Bit(s)

Function

| Read /Write |

Set to 1 whenever an ON to OFF or OFF to ON
transition occurs
on the DSR status line from the

Read only

Designation

"DSR
(Data Set Ready

transition)

selected modem. Not valid if the PDP-11 program

(Synchronous

- has changed the line number
in CSR bits 0—3 and

modem definition)

- the scan has not been cycled for one or more lines

by Scan En (CSR bit 5) or Step (CSR bit 8) Cleared
by lmtnahze or Clr Scan

SEC RX

Set toal whenever an ON to OFF or OFF to ON

" (Secondary Receive
transition)

‘transition occurs on the SEC RX status line from
|

(Asynchronous

(

modem defin‘itio’n)‘ "‘
o

Read only

the selected modem. Not valid if the PDP-11 pro- gram has changed the line number
in CSR bits 0—3

and the scan has not been cycled for one or more

lines by Scan En (CSR bit 5) or Step (CSR b1t 8).

Cleared by lmtxahze or Clr Scan |
13

CcS

Set to 1 whenever an ON to OFF or OFF to ON

Read only

(Clear to Send

transition occurs on the CS status line from the

transition)
|

“selected modem. Not valid if the PDP-11 program
has changed the line number in CSR bits 0—3 and

the scan has not been cycled for one or more lines

by Scan En (CSR bit 5) or Step (CSR bit 8).
Cleared by Initialize or Clr Scan.

co
(Carrier On
transition)
-

~Set to 1 whenever
an ON to OFF or OFF to ON
transition occurs on the CO status line from the

~ Read only
o

selected modem. Not valid if the PDP-11 program
~has changed the line number in CSR bits 0—3 and

the scan has not been cycled for one or more lines

by Scan En (CSR bit 5) or Step (CSR bit 8).

{

Cleared by lnmallze or Clr Scan.
15

RING

Set to 1 whenever an OFF to ON transition occurs

Read only

(Ring Signal)

on the RING status line from the selected modem.

PRI

‘Not valid if the PDP-11 program has changed the
line number in CSR bits 0—3 and the scan has not
been cycled for one or more lines by Scan
En
(CSR bit 5) or Step (CSR bit 8). Cleared by
Initialize or Clr Scan.

3-27

Table 3-9

Line Status Register Bit Assignments

Bit

Designation

Function

LINE EN
(Line Modem Enable)

When set to 1 for the line selected by bits 0—3 of the CSR,

causes status conditions DSR, CS, CO, and RING from

Read /Write

- Read or Write

the corresponding modem to appear in bits 4—7 of the
LSR and causes status transitions from the same modem
to set the Done bit (CSR bit 7) to 1 during the scanning
process. To set the Line En bit for a line, the line number

is set in the CSR, then the Line En bit is set in the LSR.
Cleared by Initialize and Clear Mux (CSR bit 10).

TERM RDY
(Terminal Ready)

~ When set to 1 for the line selected by bits 0—3 of the CSR,
maintains line seizure (“off-hook” condition) for the corre-

- Read or Write

sponding madem. To set the TERM RDY bit for a line, the
line number must be in the CSR, then the TERM RDY bit

“is set in the LSR. Cleared
by Initialize and Clear Mux.

When set to 1 for the line selected by bits 0—3 of the CSR,

(Request to Send)

Read or Write

conditions the corresponding modem to transmit data. To
set the RS bit for a line, the line number must be in the
CSR, then the RS bit is set in the LSR. Cleared by Initialize
and Clear Mux.

When set to | for the line selected by bits 0—3 of the CSR,

(New Sync)

Read or Write

signals the corresponding modem to resynchronize on the

(Synchronous

carrier. To set the NS bit for a line, the line number must

- modem definition)

be in the CSR, then the NS bit is set in the LSR. Cleared
by Initialize and Clear Mux.

03
|

SEC TX

When set to a | for the line selected by bits 0—3 of the CSR,

(Secondary Transmit)

signals the corresponding modem to transmit on the reverse

(Asynchronous
|
modem definition)

channels. To set the SEC TX bit for a line, the line number
must be in the CSR, then the SEC TX bit is set in the LSR.

Read or Write

Cleared by Initialize and Clear Mux.

DSR

(Data Set Ready)
Synchronous
modem definition)

SEC RX
(Secondary Receive)

~ Set to 1 whenever the DSR line from the modem selected
by bits 0—3 of the CSR is ON, provided that the Line En

Read Ognly
|

bit for that modem has been set. Indicates the modem
has seized the line,

- Set to 1 whenever the SEC RX line from the modem

Read only

selected by bits 0—3 of the CSR is ON, provided that

(Asynchronous

the Line En bit for that modem has been set. Indicates

modem definition)

a remote modem is signaling the local modem on the
reverse channels.

Set to 1 whenever the CS line from the modem selected

(Clear to Send)

by bits 0—3 of the CSR is ON, provided that the Line
En bit for the modem has been set. Indicates the modem
is ready to transmit data. Occurs in response to an RS
(LSR bit 2).

3-28

Read only

Table 3-9 (Cont)
~Line Status Register Bit Assignments

Bit
06

Designation
CO
~ (Carrier On)
(detected) o

Function

Read/Write

Set to| whenever
the CO line from the modem selected
by bits 0—3 of the CSR is ON, provided that the Line En

Reud only

~ bit for that modem is present and that the releived signal
is present for demodulation.

RING

Set to | whenever the RING line from the modem selectéd

Reud only

by bits 0--3 of the CSR is ON, provided that the Line En
-

bit for that modem has been set. Indicatesa remote modem

“is signalling the local modem.

3.3

INDIRECTLY ADDRESSABLE (SE(‘OND-

Transmission continues, using the Transmitter Alter-

ARY) REGISTERS

nate Current Address for this line (secondary register

The secondary registers make up the RAM of the

0001). provided that the Transmitter GO bit in the

DV1l and may be accessed by the PDP-11 program
via the SRS and the SAR, as described in Section 3.2.

one.

Line State secondary register for this line
is still set to

The PDP-11 program must clear (or properly set up)

all secondary registers before setting SCR 00 (Micro-

3.3.2

Transmitter Principal Byte Count (0001)

The Transmitter Principal Byte Count secondary reg-

processor GO). Because the RAM is volatile, secondary register contents must be re-established in the
event of power failure.

ister contains a

15-bit word that

plement

number

of the

is the 2's com-

of bytes

(characters)

remaining to be transmitted on the associated line.

Sixteen secondary registers, summarized in Table 3-1,

The 16th bit (bit 15) 1s used by the PDP-11 program

are provided for each of the 16 data lines, making a

to enable change of mode and/or BCC transmission,

total of 256 secondary registers. Secondary register

based on reaching 4 zero byte count during transmis-

formats are shown in Figure 3-4.

ston. When bit 15 1s set to zero by the PDP-11 pro-

gram,
NOTE

The Secondary

Registers are

13-15

of ‘the Line Progress secondary

mode when the principal byte count reaches zero;

NOT cleared by

Initialize.

3.3.1

bits

also, the BCC will be transmitted if Line Progress bit

10 is set to one. When bit 15 is set to one by the PDPIl program, bits 00-02 of the Transmitter Mode Bits

Transmitter Principal Current Address (0000)

secondary register continue to control the line transmission mode. A byte count with bit 15 set to zero (at

The Transmitter Principal Current Address secondary register contains the 18-bit core memory address

of the next character to be transmitted on the associ-

the time the byte count is loaded by the PDP-11 pro-

ated

gram) is referred to as a “*‘marked” byte count.

line.

The extended

address bits are initially

loaded from SCR 04-05 to provide the 18-bit address
capability. This register is incremented by one with
each character transmitted on the associated line by

This register 1s incremented by one with each character transmitted on the associated line
by the DVI11 if

the DVI1 if the principal message table is being used
(Line State secondary register bit 07 set to zero).

the principal message table is being used (Line State
07 set to zero). When this register reaches zero, trans-

When the transmitter Principaf Byte Count (second-

mission continues (using the Transmitter Alternate

ary register 0001) for the same line reaches zero, an

interrupt code is set in the NPR Status register.

Byte Count for this line) if the Transmitter GO bitin

the Line State secondary register is still set to one.

TRANSMITTER PRINCIPAL BYTE COUNT (0001)
18

12 NORMAL BYTE COUNT

©*MARKED BYTE COUNT

TRANSMITTER ALTERNATE CURRENT ADDRESS (0010)
15

TRANSMITTER ALTERNATE BYTE COUNT (0011)
15

1= NORMAL BYTE COUNT

Z=MARKED BYTE COUNT

RECEIVER CURRENT ADDRESS (0100)

RECEIVER BYTE COUNT (0101)

1= NORMAL BYTE COUNT

@ MARKED BYTE COUNT

TRANSMITTER ACCUMULATED BLOCK CHECK CHARACTER (0110)

RECEIVER ACCUMULATED

BLOCK CHECK CHARACTER (0111)

LEGEND

R=READ ONLY
W:=WRITE ONLY
X= UNUSED

| % NOT FOR ACCESS BY PDP-11 PROGRAM.

Figurc 3-4

11-2881

DVI11 Secondary Registers (Sheet 1 of 2)

3-30

TRANSMITTER PRINCIPAL CURRENT ADDRESS (0000)

TRANSMITTER

CONTRO:

TABLE

BASE ADDRESS (1000)

RECEIVER CONTROL TABLE

LINE

BASE ADDRESS (1001)

‘

PROTOCOL PARAMETERS (1010)

X
:

DLE CHARACTER

OCMP

—

TRANSMIT

BLOCK
BLOCK

TYPE

LEADING

DDCMP

SYNES oLe

RECE IVE

MARK
ON BOTH

BC:
O

LINE

15.

STATE

(1011)

1312

| x

NEXT RCV. MODE .
" ON MARKED

.08

EXPECT
BCC ON

BYTE COUNT: @

MARKED RECEIVE

|
o

UNDERRUN

RECEIVER

RESYNCHRONIZE

—

" 00

J e

- UNUSED

RECEIVER MODE BITS (1101)

UNUSED

MODE

LINE PROGRESS (1110)
14

X -

NEXT TRANSMIT MODE

"MARKED TRANSMIT
8.C:0

ON MARKED
BYTE COUNT: @

”

SEND BCC ON

EXPECT
'

BCC2 NEXT
.
Rgfxgc-

RECEIVER CONTROL BYTE HOLDING (1111)

1. 2 W . X

expecTep
15

MODE

RECEIVER
ACTIVE

TRANSMITTER

w | R

" TRANSMITTER MODE 8ITS (1100)
|

MEMORY

PARITY ERROR

|TRANSMITTER [TRANSMITTER |
|NON-EXISTENT|
GO .

USE ALTERNATE .

TABLES

R | R | R

SYNC STRIP
ON
°

‘

"BC:@ -

03
x

DLE SENDING

SEND

BCCI
NEXT

PROGRESS
.

SEND BCC2

DCC!NE NEXT

UNUSED

[ .8 1. 8. % %

EXPECT

BCCY

RECEIVER CONTROL BYTE

‘

» F'ig,urc 3-4 D_VI I Sécondary 'Reg.i'ste:rs (Sheet 2 of 2)

3-31

3.3.3 Transmitter Alternate Current Address (0010)
The Transmitter Alternate Current Address register
has exactly the same function as the Transmitter
Principal Current Address register described in Paragraph 3.3.1. This register is incremented by one with
each character transmitted by the DV11 on the assois being used
ciated line if the alternate message table
(Line State secondary register bit 07 set to one).
When the Transmitter Alternate Byte Count (secondary register 0011) for the associated line reaches zero,
an interrupt code is set in the NPR Status register.

Transmission continues using the Transmitter Princi-

pal Current Address for this line (secondary register
0001), provided that the Transmitter GO bit in the
Line State secondary register for the same line is still
set to one.

3.3.4 Transmitter Alternate Byte Count (0011)
The Transmitter Alternate Byte Count secondary
register contains a 15-bit word that is the 2’s complement of the number of bytes (characters) remaining to be transmitted on the associated line. The 16th
bit (bit 15) is used by the PDP-11 program to enable
change of mode and/or BCC transmission, based on
reaching a zero byte count during transmission.
When bit 15 is set to zero by the PDP-11 program,

bits 13-15 of the Line Progress secondary register for
this line will control the transmission mode when the
alternate byte count reaches zero; also, the BCC will
be transmitted if Line Progress bit 10 is set to one.
When bit 15 is set to one by the PDP-11 program, bits

00-02 of the Transmitter Mode Bits secondary register continue to control the line transmission mode. A
byte count with bit |5 set to zero (at the time that the
byte count is loaded by the PDP-11 program) is
referred to as a “‘marked’ byte count,

3.3.6 Receiver Byte Count (0101)
The Receiver Byte Count secondary register contains
a 15-bit word that is the 2’s complement of the number of bytes (characters) remaining to be received on
the associated line. The 16th bit (bit 15) is used by the
PDP-11 program to enable change of mode and/or
BCC anticipation, based on reaching a zero byte
count during reception. When bit 15 is set to zero by
the PDP-11 program, bits 13-15 of the Line State secondary register for this line will control the reception
mode when the byte count reaches zero; also, the
BCC will be expected if Line State bit 10 is set to one.
When bit 15 is set to one by the PDP-11 program, bits
00-02 of the Receiver Mode Bits secondary register
continue to control the line reception mode. A byte

count with bit 15 set to zero (at the time the byte

count is loaded by the PDP-11 program) is referred to
as a “‘marked” byte count. When this register reaches
zero, an interrupt code is set in the RIC register and
the DVII stops transferring received characters to
. memory.
core

3.3.7

Transmitter Accumulated Block Check

Character (0110)

The Transmitter Accumulated Block Check secondary register contains the continuously-computed
BCC (specified by the Line Protocol Parameters secondary register) to enable destination stations to
check integrity of transmission on the associated line.
Characters to be included in the block check calculation are specified by bit 03 of the Transmitter Control Bytes for each character. The contents of this
register are transmitted as two sequential bytes, low-

order eight bits first (except when LRC-8 is the
selected block check type, in which case a single byte
is transmitted). The DVI11 automatically clears this
register to zero after transmitting its contents.
|

This register is incremented by one with each charac-

ter transmitted on the associated line by the DV11 if
the alternate message table is being used (Line State
secondary register bit 07 set to one). When this register reaches zero, transmission continues using the
Transmitter Principal Byte Count for this line if the
Transmitter GO bit in the Line State secondary regis-

NOTE

The DV11 computes CRC-16 and CRC-CCITT on a
byte-at-a-time basis (parallel), thus the character

length must be eight bits. LRC-8 may be selected for
characters of S, 6, 7, or 8 bits.

Receiver Accumuiated Block Check Character

3.3.8

The Receiver Current Address register contains the
18-bit core memory address for storage of the next
character to be received on the associated line. The
extended address bits are initially loaded from SCR
04-05 to provide the 18-bit address capability. This
register is incremented by one with each character

|
(0111)
The Receiver Accumulated Block Check secondary
register contains the continuously-computed BCC
(specified by the Line Protocol Parameters secondary
register) for checking integrity of data received on the
associated line. Characters to be included in the block
check calculation are specified by bit 03 of the
Receiver Control Byte for that character. The PDP|1 program should clear this register if the accumulated block check at the end of the message 1s non-

received on the associated line by the DVI11.

7€ro.

ter 1s still set to one.

3.3.5

Receiver Current Address (0100)

3-32

3.3.9

Transmitter Control Table Base Address (1000)

determines the receiver control table to be used for

controlling reception on the associated line.

The Transmitter Control Table Base Address secondary register contains the 18-bit address of the transmitter control

table

for

the

associated line.

The

3.3.15

Line Progress (1110)

extended address bits are initially loaded from SCR

The Line Progress secondary register contdms bits set

04-05 to provide the 18-bit address capability. The
contents of this register are used by the Micro-

“and referenced by the Microprocessor to control and

- processor in the computation of the control byte

the selected protocol (these bits are not intended for

monitor activities on the associated linein executing

addresses for transmitted characters.

3.3.10

access by the PDP-11

program). This register also

- stores mode change and BCC transmission control

Receiver Control Table Base Address (1001)

bit's; as set by the PDP-11 program, for use by the

The Receiver Control Table Base Address secondary

~Microprocessor when

Count reaches zero, as discussed in Section 3.1. Line

18-bit address of the receiver

control table for the associated line. The extended

Progress

address bits are initially loaded from SCR 04-05 to

detail in Table 3-12.

marked Transmitter Byte

provide the 18-bit address capability. The contents of
this register are used by the Microprocessor in the

3.3.16

computation of the control byte addresses for the

The Receiver Control Byte Holding secondary regis-

received Lhdrdcters

Receiver Control Byte Holding (1111)

ter provides storage for the Receiver Control Byte in
bits 00-07. The PDP-11 program may set a control

3.3.11
The

Line Protocol Parameters (1010)

Line Protocol

Parameters secondary

byte into this register while responding to a DV11

receiver special character interrupt.

contains the transmitter Data Link Escape (DLE)

character when required by the associated line pro-

response. 1s

tocol,

plus

control

bits

to implement

program

signals

the

complete

DVII

(SCR

When the PDP-

that

08=1),

its
the

interrupt
Micro--

protocol

processor uses the control byte in this register to con-

requirements and handling of sync characters. The

~trol the disposition of the interrupting character in

PDP-11 program writes the data in this register for

the RIC register.

reference by the microprogram. Bit assxgnments are
describedin detail in Table 3- lO

3.3.12

Line State (1011)

The Microprocessor may also use this register to
|

write control

only, if an error condition or data block boundary

|1 program and the Microprocessor to control and

condition caused the interrupt; the existing mode

monitor line activities in executing the selected pro-

specified in the control byte is not altered. The PDP-

"\ .

tocol. This register is-also used by the PDP-11 pro-

bytes ‘that specify character discard

The Line State secondary register is used by the PDP-

gram to store

I'l program should not write this register except dur-

mode change and BCC anticipation

~ing inttiahzation or interrupt response cycles. Receiv-

bits

for reference by the Microprocesso
when
r a =
marked Receiver Byte Count reaches zero, as dis-

‘cussedin Section 3.1, Bit assignments are descnbedIn
‘detail in Table 3 lI

er Control Byte format is shown in Figure 3-4.

If the PDP-11 programmer so desires, the generation
of receiver interrupts may be limited to only those

3.3.13

Transmitter Mode Bits (1100)

cases where the PDP-11 program wishes notification

The Transmitter Mode Bits secondary register con-

that a particular character has arrived, rather than

tain the 3-bit mode selection field (in bits 00-02)

have the PDP-11 program change the character proc-

which determines the transmitter control table to be

essing directions specified in the control byte. In these

used for controlling transmission on the associated

circumstances, the PDP-11 program may direct that

line.

character processing resume (set SCR 08=1) without

3.3.14

Receiver Mode Bits (IIOI)

changing
the control byte stored in the Receiver Con-

trol Byte Handling register. This is possible because

The Receiver Mode Bits secondary register contams
the 3-bit mode selection field (in bits 00-02) which

~ the control byte is stored with its bit 00 (generate
interrupt) cleared.

3-33

Table 3-10

Line Protocol Parameters Secondary Register Bit Assignments
Bit(s)
00

Function

Read/Write

When set to one, causes the associated data line to go

Read or Write

Designation

Idle Mark

to the MARK state at the conclusion of transmission

~ of the character currently being loaded into the
transmitter if both principal and alternate byte

counts are zero. When cleared, sync characters will

be idled on a synchronous data line or a MARK
STATE will be asserted on an asynchronous line.
01

When set to one, causes sync characters arriving on

Strip Leading Syncs

Read or Write

the associated data line after the achievement of
‘synchronization, but before the first non-sync
character, to be stripped from the incoming data
stream (i.e., not stored in the RC Silo). The sync
character(s) with which the receiver achieves

sync are stripped in any case.
Unused

03-04

Set by the PDP-11 program to specify the type of

Block Check Type

Read or Write

block check calculation to be done for transmissions
and receptions on this line:

DDCMP Receive

BCType

LRC-8 (XOR)

]

CRC-16
(X'® + X!'5 + X* +1)

Unused-16

CRC-CCITT(X'¢ + X'2 + X®> +1)

When sct to one, inhibits the Microprocessor from
~

Read or Write

fetching control bytes during character reception on
the associated line if reception mode is 0. Useful for
increasing throughput and reducing core storage

requirements when using DDCMP protocol.
06

DDCMP Transmit

When set to one, inhibits the Microprocessor from

Read or Write

fetching control bytes during character transmission
on the associated line if transmission mode is 0.
Useful for increasing throughput and reducing core

storage requirements when using DDCMP protocol.
Unused

08-15

DLE Character

Contains the Data Link Escape (DLE) character for
the associated line. When a character is to be trans-

mitted and the control byte for that character (as
fetched by the DV11) has bit 01 set to one, the DLE

- character is fetched from this register by the Microprocessor and transmitted just prior to the character
being processed.

3-34

Read or Write

Table 3-11

Line State Sévcio'ndary Register Bit Assignments
Bit(s)

F unctiofi

Designation
Receiver Active

| Read/Wfi"tel

Réad

Set to one by the Microprocessor when the enabled =

receiver for the associated line has detected the

Vsynchronizatio’n‘Characte»r(s) for that line. (Receiver

enabling, done via the Line Control Register, is
discussed i Paragraph 3.2.2.)
0l

Recciver
‘Resynchronize

Set to one by the PDP-11 program to effect

resynchronization during reception or'to turn off -~

Write |

- |

reception on the associated line, as described in

“Section 3.5. The Microprocessor searches for the
- synchronization character(s) for the associated line
=.
S

if the receiver for the line has been enabled (receiver
enabling is discussed in Paragraph 3.2.2). When the

synchronization character(s) is found, the Micro-

processor sets the Receiver Active bit (Line State 00)
“to one. If any characters for the associated line are
stored in the RC Silo when this bit is set, they are

discarded (see Line Progress 07 description).
02

'Transmi‘tte_r“‘Go

Set to one by the"PDP-l] program to command the

Read or Write

DVI11 to transmit data on the associated line. Set
to zero by the Microprocessor whenever

1. transmitter principal and alternate byte counts
are both equal to zero, or

2. transmitter NXM (Line State 04) sets to one, or

3. transmitter MPE (Line State 05) sets to one.
“This bit may be set to zero by the PDP-11 program
~ to abort transmission.

Transmitter

‘Set to one by the Microprocessor when a character has

Read or Write

Underrun

been loaded into the transmitter for the associated

Zero

line and the transmitter has returned a Data Not

Available signal.. Should be set
to zero by the PDP-11
program after it has been read. Indicates that one or

‘more idling sync characters have been sent by the
transmitter.

|
CAUTION

In byte count oriented protocols or trans-

~ parency operation in IBM’s BISYNC, idling
of a sync causes a bad BCC and hence a NAK

from the remote terminal. Thus, the Trans-

mitter Underrun bit indicates whether the
NAK is the result of line errors or idling syncs.

- 3-35

Table 3-11 (Cont)

Line State Secondary Register Bit Assignments

Bit(s)

Function

Designation

Transmitter NonExistent Memory (NXM)

Set to one by the Microprocessor whenevera non~ existent memory condition is encountered during

Read/Write
Read or Write
Zero

transmission (NPR Status Register interrupt codes

0000, 0010, 1000). The PDP-11 program should
read the NPR Status Register, then clear this bit.

This bit clears Transmitter Go (Line State 02) when
set to one.

Transmitter Memory

Set to one by the Microprocessor whenever a memory

Read or Write

Parity Error

parity error is encountered during transmission (NPR

Zero

Status Register interrupt code 1000). The PDP-11
program should read the NPR Status Register, then

clear this bit. This bit clears Transmitter Go (Line

State 02) when set to one.
06

Sync Strip On

Set to one by the Microprocessor in response to Strip

Read only

Leading Syncs command bit (Line Protocol Parameters

01) from PDP-11 program to the associated line. Causes
the Microprocessor to strip from the incoming data
stream all sync characters arriving after the achievement
of synchronization, but before the first non-sync character. Set to zero by the Microprocessor on arrival of the

first non-sync character.
07

Use Alternate Tables

When set to zero by the PDP-11 program or the Micro-

Read or Write

processor, causes the Microprocessor to extract data

for transmission on the associated line from the princi- .
pal tables. When set to one by the PDP-11 program or
the Microprocessor, causes the Microprocessor to
extract the transmit data from the alternate tables. Set

to zero by the Microprocessor when the alternate byte
count is equal to zero. Set to one by the Microprocessor

when the principal byte count is equal to zero.

08-09

‘Unused
Expect BCC

When a marked receiver byte count reaches zero, this
bit is examined by the Microprocessor. If this bit has
been set to one by the PDP-11 program, the Microprocessor interprets the next received character (in

the case of LRC-8 block check types) or the next two
received characters (in the case of CRC-16 and

CRC-CCITT block check types) as block check
character(s), and passes them through the BCC
~calculation logic. The Microprocessor then places the

OR of the high and low bytes of the accumulated BCC
into the RIC register with the line number and interrupt

code 0101. A control byte with bit 04 set to one
(character discard) is written into the Control Byte
secondary register to inhibit storage of the block check

character(s), and SCR 07 is set to one to interrupt the
program.

3-36

Read or Write

Table 3-11 (Cont)

Line State Secondary Register Bit Assignments
Bit(s)

Function

- Read/Write

Next ReceivéModé on

When a marked receiver byte count reaches zero, the

Read or Write

Marked Byte Count =0

Microprocessor transfers these bits to bits 00—02 of

Designation
Unused

11-12

13-15

the Receiver Mode Bits secondary register to set the

mode for the next character(s) to be received.

Table 3-12
Register Bit Assignments
Secondary
Progress
Line
Bit(s)
00

Send BCC!1 Next

Read/Write

Function

Designation

(Not intended for access by the PDP-11 program.)

Read

Set to one by the Microprocessor whenever:

I. A marked transmitter byte count has reached
zero and bit 10 of this register is set to one.

)/\\\

2. A transmit control byte with bit 03 set to one
has been fetched by the Microprocessor (useful

‘when an ITB, ETB, or ETX has been
encountercd in BISYNC protocol).

Cleared by the Microprocessor if LRC or the first
BCC has been loaded for transmission by the
Microprocessor.
0l

Send BCC2 Next

(Not intended for access by the PDP-11 program'».)

Read

- Set to one by the Microprocessor when LRC or
the first BCC has been loaded for transmission,
~ but reset to zero again if LRC-8 is selected as the
Block Check Type for the associated line in Line
Protocol 03-04.

Set to zero by the Microprocessor when the second
BCC byte (BCC2) has been loaded for transmission
by the Microprocessor.
DLE Sending In

Progress

(Not intended for access by the PDP-11 program.)

Set to one by the Microprocessor when it loads a
Data Link Escape character for transmission on the

associated line in response to a control byte command

bit (01). Cleared by the Microprocessor when the DLE
has been sent.

03-04

Unused

3-37

Read

Table 3-12 (Cont)
Line Progress Secondary Register Bit Assignments

Bit(s)

Designation

Function

Expect BCCI

(Not intended for access by the PDP-11 program.)

Read/Write
Read

Set to one by the Microprocessor whenever (1) Line
State bit 11 (Expect BCC) has been set to one by
~the PDP-11 program and a marked byte count has
reached zero, or (2) a receive control byte has been

fetched with bit 03 (Expect BCC) set to one. The

next received character is then interpreted as the
first block check character (BCC1) and a BCC calculation is performed. If LRC-8 is the selected block
check type, the Microprocessor

1. places the OR of the high and low bytes of the
accumulated BCC into the RIC register with

the line number and interrupt code 0101.
2. writes a control byte with bit 04 (character

discard) set to one, into the Control Byte
secondary register to inhibit storage of the

BCC, and

3. sets SCR 07 to one to interrupt the PDP-11
program.

If either CRC-16 or CRC-CCITT is the selected block
check type (both BCC1 and BCC?2 required), the

Microprocessor sets Line Progress 06 (Expect BCC2)
and does not perform steps I, 2, and 3 until after
BCC2 is received.

Expect BCC2 Next

(Not intended for access by the PDP-11 program.) Set to one by the Microprocessor whenever Line

Progress 05 (Expect BCC1)
-

is set from one to zero

during a character reception cycle and either CRC-16
or CRC-CCITT is the selected block check type. The
next received character is then interpreted as the

second BCC (BCC2), a BCC calculation is performed,

and the Microprocessor proceeds as described in
steps 1, 2, and 3 for Line Progress bit 05.

3-38

Read

Table 3| 2 (Cont)

Line Progress Secondary Register Bit Assignments

Bit( s)
)

Read/Write

| Designation

'Function

Resynch,rbnization

(Not intended for access by the PDP-11 program.)

Read

Set to one by the Microprocessor whenever a

Flag Expected

resynchronization cycle starts for the associated
line receiver as commanded by Line State O1.

~ Cleared by the Microprocessor when all characters

stored in the RC Silo for the associated line have
been removed. This bit inhibits transfer of RC Silo
- characters designated for the associated line to the
Unibus until the Resynchronization Flag character

reaches the bottom (output) of the RC Silo. -

Unused

08-09
o

When a marked transmitter byte count reaches zero,

Send BCC

- Read or Write

this bit is examined by the Microprocessor. If this

bit has been set to one by the PDP-11 program, the
Microprocessor sets Line Progress 00 (Send BCCI

~
~

- Next) to one for the associated line. The Micro-

processor then transmits the first block character
(BCC1) after the character which caused this byte
“count to go to zero. If either CRC-16 or CRC-CCITT

is the selected protocol, the Microprocessor transmits

the second block check character (BCC2) after

13-15

transmission of BCCl.

Next TranSmit Mo"dé ,'

When a marked transmitter byte count reaches zero,
“the Microprocessor transfers these bits to bit 00-02
of the Transmitter Mode Bits secondary register to

on Marked Byte
Count=0

Read or Write

~ set the mode for the next character(s) to be trans-

mitted.

3.4 CONTROL BYTE FORMAT

Control byte bit assignments (Table 3-13), are based
on the structure of the DV11 interpretation logic, and
are arranged so that the same control bytes can be
used for both transmission and reception, provided

The sa}me_charact’er’s‘_’are included in the
BCC for both transmit or receive.

If the protocol being executed does not have the
above characteristics, separate control tables for
transmit and receive may be established by setting
different values in Receive Control Table Base
Address and Transmit Control Table Base Address
secondary registers. Control byte formats for trans-

that:

The protocol progresses from mode to
mode in a symmetrical fashion for both

mission and reception are shown in Figure 3-2.

transmit and receive, and

3-39

“Table 3-13

.Control Byte Bit Assignments
Bit(s)
00

‘Transmitter Control Byte

Receiver Control Byte

Unused (to effect symmetry)
.

Interrupt PDP-11 Program:

When set to one, causes the DV11 to request a
PDP-11 program interrupt. The DV11 sets the
received character being processed in the

Receiver Interrupt Character Register and

“awaits a reset of SCR 08 by the PDP-11 program.

Send Data Link Escape Next:

Unused (to effect symmetry)

When set to one, causes the DV11 to fetch the
Data Link Escape (DLE) character from
secondary register 1010 for the selected line
and transmit it before transmitting the character being processed.

Send BCC:
When set to one, causes DV11 to transmit the

Expect BCC:
When set to one, causes DV11 to set up for

~ following transmission of the character being

character as the block check character.

block check character(s) for the selected line

processed.

receiving and processing the next received

Include Character in BCC:

When set to one, causes the character being

processed to be included in the block check
character being accumulated for the selected

line. When set to zero, inhibits inclusion.

Unused (to effect symmetry)

Discard/Store Character:

)

When set to zero, causes the character being
processed to be stored at the receiver current

~address in core memory for the selected line.
When set to one, inhibits character storage.

0507

Next Mode:

Specifies the mode for the next character to
be transmitted on the selected line. Bit 05 is

Specifies the mode for the next character to
be received on the selected line. Bit 05 is the

the least significant bit. -

least significant bit.

3-40

3.5

DVIIINITIALIZATION

LCR 10 and 13 are implemented for synchronous reception on a line. When oper-

DVI11 initialization consists of setting up the DV11

ating on an asynchronous line, character

line modems and the DV11 Data Transfer Section.

3.5.1

format and baud rate must be set up at

this time.

Line Modem Set-Up

Initialization for the line modems consists of setting

Followmgis an illustrative procedurc to setup a line
for lransmnssxon

the line number for the modem to be enabled in CSR
00-03. CSR 06 (Interrupt Enable) may also be set to
one at this time to select the interrupt mode. The Line

Enable bit (LSR 00) is then set to one to complete the

Set

the transmitter

control

table

core

initialization process for the selected line. The process
is repeated for each line that is to be enabled.

~memory addresses and byte counts in the

CSR and LSR are cleared at bus initialization time.

counts to zero if marked byte counts are

Setting CSR 10 and 11 (Clear Mux and Clear Scan)

required by the protocol.

appropriate principal and alternate sec-

ondary registers, setting bit 15 of the byte

each to one is equivalent to bus initialization, except

that the Terminal Ready bits (LSR 01) for each line

Set the required protocol control bits and

are also cleared by Clear Mux. If a Clear Scan is

the DLE character in the Line Protocol

issued, the PDP-11 program must wait for the MCU

Parameters secondary register.

Busy Indicator (CSR 04) to return to zero before

sending additional command bits.

Initialize transmitter mode to non-zero in
~ Transmitter Mode Bits secondary register

3.5.2

(1100) if required by the protocol; set oth-

DVII Data Transfer Setup

The primary registers should be cleared by a Master

er bits in this regxstcr as required by the

Clear (SCR 11), then the secondary registers for all

protocol.

lines must be cleared. Then set Microprocessor GO
(SCR 00). The Microprocessor will now loop in an

Set bit 07 of Line State secondary register

idle mode. The first word to SCR may also contain

to one if transmlssmn IS to start from the

the extended address bits (SCR 04-05) and interrupt

altcrnatc tdbles

endbles (SCR 06, 12, 13), as required.

5. 'lf' the data link is established on the

Following is an illustrative procedure to setup a line

- selected line, set bit 02 of Line State sec-

for data reception:

ondary register to one to start the trans-

mitter for the Ime
.

Set the receiver control table core memory

address and the byte count in the appro-

If the line is asynchronous, the character

priate secondary registers.

format and baud rate in the Line Control

Set the required protocol control bits in

State bit 02

Initialize receiver mode to non-zero in

the Line Protocol Parameters secondary
register.
|
|

3.6 DATA TRANSFER IMPLEMENTATION

With the DV 1 initialized as discussed in Section 3.5,

Mode Bits secondary register

calls to or from remote modems may be originated or

(1101) if required by the receiver protocol

answered and DVI| data transfers started by the
PDP-11 program. The data transfer process or pro-

Receiver

"implementation logic.

tocol is controlled by the contents ofthe control bytes
When the data link is established on the

and by the service routines for the DV11 interrupts.

selected line (Paragraph 3.5.1), set LRC

This section contains descriptions of call origination

13 and 15 to one to cause the line to sync

and answering procedures; resynchronization during

up and start receiving characters. Set LRC

reception; termination of transmission and reception,

10 to one at the same time if sync charac-

and suggested programming methods for implementing BISYNC and DDCMP protocols.

ter(s) B is to be selected.

3-4]

Originating and Answering Calls

PDP-11

program waits on Data Set
Ready (DSR) transition (CSR 12) and the

The Control Status Register (CSR) and the Line Stat-

us Register (LSR) are provided to enable the PDP-11
program

originate

and

answer calls

Carrier On (CO) transition (CSR 14) from
the enabled modem.

to/from

remote modems. Initially, the local modem is enabled

and the operating mode (interrupt or non-interrupt)

is set, as described in Paragraph 3.5.1. An interchange then takes place between the PDP-11 program and the MCU to originate a call, as follows:

PDP-11

program sends Data Terminal

Ready (LSR 01) to cause enabled modem
to hold the line once the call is established.

tion and initiates data transfers.
3.6.2

Resynchronization During Reception
If line synchronization initially fails or is lost, the
PDP-11 program can command resynchronization

during reception by setting bit 01 of Line State secondary register to one. The DV11 then

PDP-11 program dials remote number via
DNI1

Automatic

Dialing Unit,

or an

set
to one), during which any receiver

characters for this line already buffered in

remote modem. When the call has been

via the Call Request line and Data Termi-

the DVI11 are discarded

00), and

operator switches to “Data Mode’ and

Data Terminal Ready holds the call.
PDP-Il

program

waits

Data

modem (CSR 12). If the MCU is oper-

ating in the non-interrupt mode with only
one line enabled (as reflected by the contents of CSR 00-03) LSR 04 may be readily used to monitor the DSR line.

searches

|
for

the

|
synchronization

character.

Set

Ready (DSR) transition from the enabled

clears the Resync Command bit (Line
State 01) and Receiver Active : Line State

nal Ready. In the manual dialing case, the

defines a *‘Resync Flag Expected interval”
(Line Progress secondary register bit 07

operator manually initiates a call to the

established, the DN11 will hold the line

When CO is detected, the PI')P-.l 1 pro-

gram starts the DV11 Data Handling Sec-

When the synchronization character is found, the
DVI11 sets the Receiver Active bit to one to enable
receipt and storage of subsequent characters on the
resynchronized line. The program should not request

resynchronization again until at least one character
has been received since the previous resynchronization request.

When DSR is detected, the PDP-11 program sends a Request to Send (LSR 02) to

set the data mode for transmission.

PDP-11

(CO) and Clear to Send (CS) transitions

Termination of Transmission and Reception

The DVI1I terminates transmission on a line when-

program waits on Carrier On

(CSR 14 and
modem.

3.6.3

13) from the enabled

ever both principal and alternate byte counts have
reached zero, ora non-existent memory or memory
parity error condition is encountered. The DV11

sets
Transmitter GO (Line State secondary register bit 02)
to zero to terminate transmission. The PDP-11 pro-

When CO and CS are detected, the PDP-

gram may set Transmitter GO to zero to abort
transmission.

Il program starts the DV11 Data Han-

dling Section and initiates data transfer.

The PDP-11 program shuts down reception on a line
by clearing Receiver Enable (LCR 13) and setting

Line State secondary register bit 01 (Receiver Res-

Answering a call consists of the PDP-11 program

ynchronize) to one. The DV11 then

detecting the Ring transition from the enabled mod| I.

em (CSR 15), then

clears the

Resync Command bit (Line
State 01) and the Receiver Active bit (Line

State 00), and

PDP-11 program sends Data Tcrminal

Ready (LSR 0l1) to cause enabled modem

to answer the call.

discards any receiver characters already
accumulated for the line.

342

3.6.1

3.6.4

BISYNC Implementation

be loaded with the base addresses and byte counts for

'BISYNC implementation software is considered in

data buffers one and two, respectively. On each zero

three functional groups: control tables, interrupt

byte count interrupt, the next buffer address would

service routines, and the protocol module.

- be loaded into the appropriate registers.

The control tables contain the control bytes, which

-~ For non-transparent data, the DVI11 is initialized to

control sequencing between modes and accumulation

Mode 3 for transmisston of any header data (see Fig-

of the BCC. During transmission, the control bytes

ure D-3) or the ENQ control character. ITB, ETB,

also control DLE stuffing and BCC transmission.

ETX characters
are included in the BCC and fol-

Additionally, during

reception, the control bytes

lowed by the BCC in Mode 3. The DVI1 is switched

enable discard of unwanted characters and reception

to Mode 4, the text transmission mode, on occur-

of this BCC.

)

rence of the STX or ITB delimiters. Occurrence of a

The interrupt service routines respond to zero byte

zero byte count causes
a return to Mode 3 to send the

next data block.

~count and error interrupts, and, during reception,

respond to special character interrupts.

Table 3-15 shows the transmission sequence and the

The protocol module initializes the DV 11, establishes

control byte dircctives for a block of non-transparent

data that is separated into two intermediate blocks.

direction of transfer, sets up and manages the data
buffers, and handles error and special character flags

set by interrupt service routines. Handling of error

flags may take the form oftry-again routines, or
operator notification. Handling
of special characters

may require such operations as a switch from receive
to transmit, or termination and disconnect (i.e., EOT
received).
|
3.6.4.1

Transmission Control -

3.6.4.2

Reception Control - Figure 3-6 is a state flow

chart for the BISYNC reception control process.
Four states or modes are required: Modes 0 and 2 are
used to handle non-transparent data, Modes 3 and 4

are used to handle transparent data.

Mode 0 (Waiting
for Message)

Figure 3-5 shows

The DVI11 is initialized to Mode 0, and the address

state flowcharts for the BISYNC transmission con-

and byte count registers in the DV11 are set to receive

trol process. There are five states or modes: three for

one byte. Response to the initial control character is

‘transparent

as follows:

data

transmission,

and

two for non-

‘

transparent data transmission.

ENQ
- the character is stored to record the
For transparent data, the DV11 mode is initialized to

request, an interrupt is generated to turn the

Mode 0, causing the DV11 to stuff a DLE in front of

‘buffer contents over to the protocol module for

any ACK, RVI, or WACK control characters sent by

printout or other handling, and a new buffer is

the PDP-11. The DV11 also stuffs a DLE in front of

requested to store the expected data. The data is
input in Mode 0 (no mode change).

the first STX sent by the PDP-11 and switches to

Mode

|, the transparent data transmission mode.

The DV11

stays in Mode | until a marked byte count

DLE - discard the character and go to Mode |

reaches zero (see Section 3.3), and is then switched to

(transition to transparent reception).

Mode 2, the end-of-transparent block mode.

STX
or SOH - store the character and go to

In Mode 2, transmission of the ITB sequence (ITB

Mode 2 (non-transparent
data reception).

DLE STX) causes a return to Mode 1 for transmis-

sion of the remainder of the data block. Transmission

EOT
- store the character, generate an interrupt

of an ETB or ETX character causes a return to Mode

to turn buffer contents over to protocol module

0 to enable transmission of the next data block.

for termination of reception; stay in Mode 0.

Table 3-14 shows the transmission sequence and the

NACK - store the negative acknowledgement

control byte directives for a block of transparent data

character, generate interrupt to turn buffer con-

that is separated into two intermediate blocks. The

tents over to protocol module for resumption of

DVI11 principal and alternate registers would initially

transmission; stay in Mode 0.

3-43

NON-

TRANSPARENT

TYPE OF

TRANSPARENT

DATA REQUIRED

INITIAL

INITIAL NON-

TRANSPARENT

TRANSMISSION

—

;::ZISPARENT
TRANSMISSION

NON-

TRANSPARENT
1

TEXT TRANS.

MISSION

2
END OF TRANSPARENT BLOCK

11-2949

Figure 3-5

BISYNC Transmission Flow Diagram

3-44

Table 3-14
Transparent Data Transmission Control

Data Buffer

Stuff

- Send BCC After |

A DLE?

This Character?

No.

Contents

STX

YES

CHAR. |

—

YES

CHAR. N**

(2)*

—

YES

3
|

Current

INCL. CHAR. IN BCC?

ITB

YES

DLE

—

- YES

STX

—

YES

CHAR. |

YES

CHAR. N**

(2)*

YES

ETX/ETB

YES

,.‘,.»_‘

- Control Byte Directives

Mode

*On Byte Count Zero l'ntérrupt ~ Not Control Byte Dircctive
**If Char.is a DLE. Stuff a DLE

Table 315

Non-Transparent Data Transmission Control

Data Buffer

~
Mode
Current

Control Byte Diréctives
|

Send BCC After

No.

Contents

]

STX

—

CHAR. |

YES

CHAR. N

(3)*

YES

ITB

YES

CHAR. |

—

YES

CHAR. N

(3)*

YES

ETX/ETB

—

YES

This Character?

*On Byte Count Zcero Interrupt ~ Not Control Byte Directive

3-45

INCL. CHAR. IN BCC?

0
WAITING FOR
MESSAGE

NO
1

TRANSITIONTO

STX

TRANSPARENT
RECEPTION

YES

TRANSPARENT
TRANSPARENT

DATA

DATA RECEPTION

RECEPTION

YES

TRANSPARENT

ETB*/ETX"*

CONTROL
CHARACTER
RECEPTION

- STX/SYN/DLE/.
iTe*

*RECEIVED THE BCC
YES
ETB*/ETX*

11-2950

Figure 3-6

BISYNC Reception Flow Diagram

3-46

Mode 1 (Transition to Transparent Reception)

generated, the buffer contents are turned over to the

In this mode, the system initializes for the reception

protocol module, and address and byte counts are set

of transparent text. Mode 1 is entered only from

to receive the 2-byte BCC.

‘Mode 0 following reception of a DLE. An STX is
expected; if one is received, it'is discarded (an inter-

Mode 4

rupt is generated to set the Transparent Data flag),

follows:

responds

other control

characters

and Mode 3 1s set.
DLE - store the character, mcludein the BCC,

positive

acknowledgement chdracter (ACK,

return to Mode

WACK RVI)is received, an mterrupt 1s generdted to

turn the buffer contents over to the protocol module

STX - discard, include in BCC, return to Mode

for resumption of transmission, and the DVII is

returned to Mode 0. Receipt of the ENQ repeat
request causes an interrupt to set an Errorflag and
“turn buffer contents over to the protocol modulc

ENQ - interrupt, store the character, set Error

flag. return to Mode 0.

All other received characters are stored, an interrupt

SYN - discard, return to Mode 3.

is generated, dnd the DVI1 is returned to Mode 0.
All Other Char.acters - store, include in BCC,

Mode 2 (Non-Transparent Data Receptlon)

return to mode
3.

The system receives non-transparent text (mcludmg

Modev's'_ (Transpérent ‘lntermediate ' Déta Reception)

header, if sent)in this mode. All characters are stored

and included in the BCC, except as follows:

ITB - store the character, mcludein BCC and

DLE - discard, include in BCC, go to mode4¥

All Oiher Characters - lnterfupt, store, return

’

p/—\\\

receive BCC next. Interrupt, turn buffer con-

tents over to protocol module

ETB or ETX -~ store the character, include in

buffer to the protocol module with errors. Go

BCC and receive BCC next. Set End-of-Block

to mode 0.

flag and turn buffer over to protocol module.
Go to Mode 0.

- 3.6.5

DDCMP Implementation

The method suggested for DDCMP implementation

ENQ - discard the character and set error flag.

uses a single control table for both send and receive.

Interrupt and turn buffer over to protocol mod-

Buffers are configured so that the only interrupts

ule. Return to Mode 0.

required are those resulting from zero byte counts.

SYN - discard.

Reference Figure B-4 for DDCMP data message
format.

Mode 3 (Transparent Data Reception)

3.6.5.1

Transparent text is received in this mode. All charac-

chart for the DDCMP transmission process. Initially,

ters except DLE are sorted and included in the BCC.

the DV 1 principal transmit registers are set with the

A DLE, if received, is discarded, and Mode 4 (Trans-

base address and byte count of the data buffer con-

parent Control Character Reception) is set.

Mode 4 (Transparent Control Character Reception)

Transmlssmn Control - Flgure 3-7 1s a flow

taining the header, with bit 15 of the byte count set to
zero, to cause BCC transmission at zero byte count

time (reference Paragraph 3.1.4.2).

Control characters received in the transparent data

stream are processed in this mode. The usual control
characters would be the block delimiters, ITB, ETB,

or ETX; these are included in the BCC, which is

received immediately after them. The ITB is stored

and requires a change to Mode 5 to strip syncs and
then to get the rest of the data block. ETB or ETX is
stored and return to Mode 0 is made. An interrupt is

If 4 numbered (data) message or bootstrap message is
being sent, set the alternate transmit registers with the
base address and byte count of the first data buffer
containing the actual data. When setting up to transmit the last data buffer, set bit 15 of the byte count to
zero to cause BCC transmnssnon at zero byte count
. llme

3-47

3.6.5.2 Reception Control - Figure 3-8 is a flow
chart for the DDCMP reception process. Initially,

the DVI11I receive reglsters are set to receive the six

bytes of theincoming DDCMP header and bit 15 of
the byte count register is cleared to dlrect reception of
the BCC.

1. SET PRINCIPAL

AMIT REGS
WITH HEADER

The first character in the first buffer is now examined

BUFFER AD-

to determine message type. If it is a numbered data

DRESS & B.C.

message (SOH character) or a bootstrap message

SETBITTO

(DLE character), the character count in buffer words

SEND BCC
WHEN B.C.=0

two and three is used to build a receive buffer of
appropnate size. If it is an unnumbered control mes-

" DATAOR

sage (ENQ character) no addmonal “buffering is
required.

BOOTSTRAP

When the DVI1 mterrupts to sxgnal BCC reception

MESSAGE

complete, set the DV11 receive registers to input the

YES

data to the receive buffer that has just been built, if
~any. On the next interrupt, return control to the call-

GET NEXT
BUFFER

LAST

\\_

BUFFER

T NO

ing program.

SEND
BUFFER

The BCC is checked at the points indicated
in Figure
3-8. The BCC Received interrupt occurs as a result of

SEND BUFFER

SETBITTO

ing zero. The BCC characters are included in the
BCC. The accumulated BCC, if correct, should be

SEND BCC |

zZero.

WHEN B.C. =0

C RETURN

>|
11.2951

Fig.u_re 3-7 DDCMP Transmi.ssion Flow D-ivagram

3-48

,’/

“

a control byte directive or a marked byte count reach-

y
s

.
-

SET TO RECEIVE

FIRST3BYTES

f@— -—

-—

DV11 INTERRUPT

SET TO RECEIVE

SECOND 3BYTES

BOOTSTRAP (DLE)

OR DATA (SOH)

" IYPE OF

CONTROL (ENQ)

MESSAGE

DV11
INTERRUPT

GET CHARACTER

CHECK BCC

COUNT AND
BUILD R ECEIVE

BUFFER

[

—— —

DVI11INTERRUPT

CHEC K

RETURN

HEADER BCC

SETDV11 TO
RECE IVE

MESSAGE

RETURN
]

11-2952

Figure 3-8

DDCMP Reception Flow Diagrarh

£+

3-49

\-\
1

APPFNDIX A

PDP 11 MEMORY ORGANIZATION
AND ADDRESSING CONVENTIONS

The highest 8K address locations (760000-777777)

- The PDP-11 memory is organized into 16-bit words

consisting of two 8-bit bytes. Each byte is addressable

are reserved for internal general registers and per-

and has its own address location: low bytes are even-

ipheral devices. There 1s no physical memory for

numbered, high bytes are odd-numbered.
Words are

“these addresses; only the numbers are reserved. As a

addressed at even-numbered locations only and the

“result, programmable memory locations cannot be

high (odd) byte of a word is automatically included to

assigned in this area; therefore, the user has 248K

provide a 16-bit word. Consecutive words are there-

‘bytes or 124K words to program.

fore found in even-numbered addresses. A byte oper-

ation addresses an odd or even location to selcct an 8bit byte.
A PDP Il processor w1thout the Memory Manage-

The Unibus address word contains 18 bits 1dent1fiedv.

~mcnt Unit provides 16 address bits that specify 2'¢

as A(17:00). These 18 bits provide the capability of

or65,536 (64K) locations (Figure A-2). The max-

addressing 256K memory locations, each of whichis

imum memory size i1s 65,536 (64K) bytes or 32,768

an 8-bit byte. This also represents 128K 16-bit words.

(32K) words. Logic in the processor forces address

In this discussion, the multiplier K equals 1024 so

~ bits A(17:16) to s if bits A(15:13) are all Is, when the

that 256K represents 262,144 locations and 238K rep-

~ processor is master, to allow generation of addresses

resents 131,072 locations.

This

~in the reserved area with only 16-bit control.

maximum memory

size can be used only by a PDP-11 processor with a
Memory Management Unit that utilizes all- 18
address bits. Without this unit, the processor pro-

Bits 13, 14, and 15 become all Is first at octal 160000

vides 16 address bits which limits the maximum mem-

ory size
to 64K (65,536) bytes or 32K (32,768) words.

which is decimal 57,344 (56K). This
iis the bcgmnmg

of the last 8K bytes of the 64K byte memory. The

Figure A-1 shows the organization for the maximum

processor converts

memory size of 256K bytes. In the binary system, 18

760000-777777, which relocates these last 8K bytes

bits can specify 218 or 262,144 (256K) locations. The

(4K words) to the highest locations accessible by the

octal numbering system

1s used to designate the

locations

160000-177777

bus. These are the locations that are reserved for

address. This provides convenience in converting the

internal

address to the binary systcm that the processor uses,

addresses; therefore, the user has 57,344 (56K) bytes
or 28,672 (28K) words to program.

as shown below.

|16 | 15 [ 14 | 13

o|lo
N

|12 | 11
| v

|10
|

|09
|

|08 | 07
’

1|11
AL

—

|06

gcnerdl

|05

|04 | 03|02 | 01|

]o]o|o]ojo|
A

pcnph_cral device

00 |ADDRESS
BIT

|siNaRY
J

OCTAL
11-3176

A-1

08|07

e— 16 BIT DATA WORD

HIGH BYTE

LOW BYTE

000001

000000

000003

000002

USER ADDRESS SPACE

¥
o

AVAILABLE USING 18

ADDRESS BITS ON
POP-11 PROCESSOR

WITH MEMORY
MANAGEMENT

OPTION,

INCLUDES 248K (253,952)

BYTES OR 124K (126,976)
WORDS.
757777

757776

760001

760000

HIGHEST 8K (8192)

BYTES

*7 77777
:

4K (4096)

WORDS RESERVED FOR

DEVICE REGISTER

ADDRESSES.

777776

LAST ADDRESS IS BYTE

NUMBER 262,14310

* MAXIMUM SIZE WITH 18 ADDRESS BITS IS 256K(262,144) BYTES OR 128K (131,072) WORDS.
11-1690

Figure A-1 Memory Organization for Maximum |
Size Using 18 Address Bits

Memory Size |

Memory capacities of S6K bytes (28K words) or
under do not have the problem of interference with

the

reserved

area,

because

designations

less

K-Words

Highest Location
(Octal)

K-Bytes

than

160000 do not have a binary | in bit A13. No address-

017777

es are converted and there is no possibility of physical

037777

memory locations

interferring

with

the

reserved

spdce.

PDP-11 core memories are availuble in 4K, 8K, or

24
32

16K increments. The highest location of various size

core memories are shown.

A-2

057777
077777

117777

137777

- 56

157777

08|07

00|

+— 16 BIT DATA WORD —|
HIGH BYTE

LOW BYTE

000001

000003

000000

000002

USER ADDRESS SPACE
AVAILABLE

s_/J

USING 16

ADDRESS BITS ON

—’__

__\J

PDP-11

PROCESSOR

f MANAGEMENT OPTION.
WITHOUT MEMORY

INCLUDES 56K (57,344)

BYTES OR 28K (28,672)
WORDS.

137777

157776

160001

160000

ADDRESSES 160000-

/__\\J

f—\

_____//'J

177777 ARE CONVERTED

TO 760000 -777777 BY

THE PROCESSOR. THUS,

THE
f HIGHESBECOME
T 8K (8192)
BYTES
THEY

OR 4K(4096) WORDS

* 17777 I

177776

LAST ADDRESS IS BYTE NUMBER 65 53510
MAXIMUM SIZE WITH 16 ADDRESS BITS
IS

RESERVED FOR DEVICE
REGISTER ADDRESSES.

64K (65, 536) BYTES OR 32K(32,768) WORDS.
1-1689

Figure A-2

Memory Organization for Maximum
Size Using 16 Address Bits

A-3

APPENDIX B
PROTOCOLS FOR BINARY

SYNCHRONOUS COMMUNIC ATIONS

‘A protocol is a set of rules which govern the sequenc-

data terminal is capable of transmitting a fixed num-

ing, identification, and synchronization of data inter-

ber of bits per second in each direction; the control

‘\\'\

changed

between

data

terminals.

This

bits reduce the effective rate of information transfer.

appendix

describes the features of two popular protocols to

The ratio of the information bits to the total bits

enable the user to select and plan for the implementa-

determines the one-way line utilization efficiency.
The more control, header and error-checking characters needed by a protocol,
the less efficient the line.

tion of the protocol best suited to his needs. This
appendix also provides the necessary background

~ data for understanding the data exchange requirements which the DVll was specifically chIgned to

B.l.3 Acknowledgement Handling

accommodate.

‘Acknowledgement handling can affect line utilization
in two ways. First, if the acknowledgement is a sepa-

B.1

DATA CHANNEL UTILIZATION

The DV11

rate message, then both the acknowledgement and

interchanges serial, synchronous, bytes or

the gaps between the acknowledgement and the data

characters with remote terminals via data channels or

blocks are part of Control Overhead. Second, more

lines. The maximum efficiency with which a channel

overhead occurs if each message requires a separate

may be utilized is determined by the structure of the
~ protocol being used. Four factors inherent
i1n any
protocol affect data channel utilization efficiency:

acknowledgement. Acknowledgements within blocks
containing

acters

reduce the first overhead

for

normal

conditions;

only errors

are

indicated by separate blocks. If the protocol defines a

direction utilization

'Bll

information

because 1t usually takes fewer or no additional char-

control overhead

way

acknowledgement handling

response,

number of data termmals or stations per lme

reduced.

acknowledge

multiple

blocks

with

one

the number of overhead bits 1s further

Direction Utlllzatlon

A data channel between two terminals may physncally

B.1.4

permit one-way or two-way transmission, called simplex or duplex operation, respectively. The two-way

When the activity from one station on a lineis below

transmission may alternate in direction of transmis-

putting additional stations on the line. This is similar

sion, called half-duplex, or may provide simultaneous

to telephone party lines and is called **multipointTM or

two-way transmission, called full-duplex. Most physical facilities are full-duplex, however, the protocol
being used may not take advantage of the physical

“multidrop.”” When only two stations are involved, it

Stations Per Line

full utilization, the extra capacity can be utilized by

Is called *‘*point-to-point.”” Most protocols support

both point-to-point and multipoint arrangements.

facility. It may be a hali-duplex protocol (alternate

For multipoint operation,
one station in the network

data transmissions), although the physical facility is

Is designated as the Control Station. The remaining

full-duplex. To make the most efficient
use of a full-

stations are designated as Tributary Stations. The

duplex facility, a full-duplex protocol is required.

Control Station initiates data transfers by *‘polling”
and *‘selectionTM of Tributary Stations. Polling is an

B.1.2

invitation to send data, transmitted from a Control

Control Overhead

Data transferred between terminals is compnsed of

Station to a Tributary Station. Selection is a request

information, control and error-checking bits. All but

to receive data, to be sent from the Control Station to

the information bits are Control Overhead bits. A

“the Tributary Station.

B-1

B.2

in that some printing characters are replaced by non-

DATA AND CONTROL CODES

The purpose of a data channel is to transfer data,
unaltered, from a transmitter station (master) to a
receiver station (slave). The data to be transferred is
embedded in control codes, which serve to identify
the type of data being transferred, and to provide for
synchronization and error detection. (Thus, the chan-

printing control characters and the parity is specified
to be odd. This code is readily adaptable to computer-to-computer communications.
Of the other existing codes, the most widely used are

the Extended Binary Coded Decimal Interchange

nel is considered to consist of the physical facility

Code (EBCDICQC), the 5-bit Baudot code, found in old

plus control codes. For this reason, the control codes

teleprinter equipment, the Four of Eight Code, the

may be referred to as Data Channel or Data Link
control codes.) Since both stations are operated in
accordance with the same protocol, the receiver station is able to differentiate between the several types
of control codes and data codes sent by the transmitter, and can therefore act accordingly.

IBM punched-card Hollerith code, the Binary Coded
Decimal (BCD) code, and the 6-bit Transcode.
EBCDIC is an eight-level code similar to ASCII,

except that while ASCII uses its eighth level for parity

bits, EBCDIC uses. it for information bits, thereby
extending the range of characters to 256.

B.2.2

Preceding the

Character-Encoded ‘Data.

Synchromzatmn Codes
data

and control

|
character

1S a
sequence of one or more synchromzmg (SYN or
SYNC) characters, which have a protocol-defined bit

machine-language computer programs. In order to

pattern. The synchronization characters. are used by
the receiver to synchronize, or get in phase with, the
characters in the continuous stream of bits, to determine where each character begins and ends. (This is
the character-framing process described in Appendix

do this, all data, including the normally restricted

C. )

B.2.1.1

Transparent Data - It is often necessary to

transmit

binary data,

floating-point

numbers,

packed-decimal data, unique specialized codes, or

Data-Link Control characters, are treated only as

specific bit patterns. Protocols differ in the methods

B. 2 3 Error-Detectmg Codes

used to permit the use of all possible bit patterns as
data while still controlling the data channel. Tech-

The protocols to be described use error-detecting
codes provided
for by the DV11: LRC, CRC-16, and

niques for achieving transparency are discussed sepa-

CRC-CCITT.

rately for each protocol described herein.

B.2.1.2

Character Codes - Several character encod-

LRC is a Longitudinal Redundancy Check on the

ing schemes are available. The codes differ primarily

total data bits by message block (see Figure B-1). An
LRC character is accumulated in both the sending

in the number of bits used to represent characters and

and receiving terminals during the transmission of a

the bit patterns which correspond to the characters.

block. This accumulation is called the Block Check

Characters are divided into graphic characters, repre-

Character (BCC). The transmitted BCC is compared
with the accumulated BCC at the receiving station for

senting a symbol, and control characters, which are
used to control a terminal or computer function.

an equal condition. An equal comparison indicates a
good transmission of the previous block.

Although many codes are in use, the trend is toward

the

universal

7-bit-plus-parity

ASCII

(American

Standard Code for Information Interchange) code.
ASCII

was

introduced

the U.S.A. Standards

Institute and has been accepted as the U.S. Federal

Standard. Techniques for transmitting transparent or
-binary data also exist within the structure
of the

Cyclic Redundancy Checking (CRC) is a more powerful method of block checking than LRC. A CRC is
a division performed by both the transmitting and
receiving stations, using the nurmeric binary value of

the message as a dividend, which is divided by a constant. In performing the division, borrows are

ASCII code. Special characters are set aside for Data

ignored. The quotient is discarded and the remainder

Channel control.

serves as the check character, which 1s then trans-

A variation of the ASCII code is the 8-bit Data Inter-

the transmitted remainder with its own computed
remainder, and finds no error if they are equal.

change Code. Primarily, this code differs from ASCII

mitted as the BCC. The receiving station compares

In the protocols to be descnbcd all data are classed
into two types or categories: Transparent Data, or

B.2.1 Types of Data

Bit Position

lf 6

543210

Character1

111001

Character 2

0011

Character 3

0000O0T1

Polling and addressing on multipoint lines are handled by a separate control message and not by using
the header field. The text portion ofthe field is variable in length and may contain transparent data. If it

is defined as transparent, it is delimited by DLE

00O

(Data Line Escape) STX and DLE ET (End of Text),
or DLE ETB (End of Text Block). The block1S termi-

nated by the BCC.

Character4 | O 1 1 10000
LRC-8BCC

| Figure B-1

0001

BSC protocbl employs a rigorous set of rules for
establishing, maintaining, and terminating a communications sequence. A typical exchange between a
“data terminal and the DVI1/PDP-11 on a point-to-

Longitudinal Redundancy Checking

point private line is illustrated in Figure B-2.

B.3.2
An infinite number of constants may be used to per-

form the CRC division.
The DV11 makes available

two CRC computations: CRC-16 (which uses a poly-

Error Checking and Recovery

To detect and correct transmission errors, BSC uses
either VRC/LRC
or CRC. depending upon the character code. If the code is ASCII, a VRC check is per-

nomial of the form x'® + x!S"+ x2 + 1), and CRC-

formed on each character and an LRC on the whole

CCITT (which uses a polynomial of the form x'¢ +

message. The LRC becomes one 8-bit BCC. If the

x'2 4+ x% + 1). Each generates a 16-bit BCC.

code is EBCDIC, CRC-16 (x'®* + x!5 + x2 + 1) is
used, resulting
in a 16-bit BCC.

B.3

BSC PROTOCOL (BISYNC)

One of the most widely used protocolsis IBM’s Bma-

If the BCC transmitted does not agree with the BCC

ry Synehronous Communications (BSC). BSC, also

computed by the receiver, or if there is a VRC error, a

known as BISYNC, has been in use since 1968 for

LRC is the modulo 2 sum (exclusive-OR) of the bits

NAK sequence (shown in Figure B-3) is sent back to
the data source. BSC calls for the retransmission of
the block when an error occurs. BSC will typically
retry three times before concluding that the line is in
an unrecoverable state. BSC checks for sequence

in each bit position of all characters in a message

errors by alternating positive acknowledgments to

transmission between IBM computers and remote
terminals of the batch and video display types.

block to produce a BCC. The figure shows the BCC

successive blocks. ACKO and ACK are the respon-

computation for four 8-bit characters using LRC.

ses to the even-numbered and odd-numbered blocks

Each character contains seven data bits and an odd-

in the message, respectively. These are sent in sepa-

parity bit.

rate control messages.

B.3.1 Controlling Data Transfers
The format of a BSC message is shown in Figure B-2.
BSC uses control characters to delimit the fields. The

B.3.3

Character Coding

BSC supports ASCII, EBCDIC, or 6-bit Transcode

(Start of Header) and ends with STX (Start of Text).

lists and describes certain bit patterns in
each set that have been set aside for the required BSC
control characters. Some BSC control codes are mul-

The contents of the header are defined
by the user.

ti-character sequences.

header is optional; if it is used, it begins with SOH

SYN

SOH | HEADER

STX

Table D-1

TEXT

ETX

BCC
1

11-2898

Figure B-2

BSC Data Message Format

DV11/PDP-11

TERMINAL
Terminal sends a message whose text

is a single control character: ENQ.
This means *‘I have some data to send
to you.”

@ DV11/PDP-11 receives ENQ.
PDP-11 acknowledges terminal by responding

OI0

Terminal Sends Block of Data.

Terminal Receives “Go Ahead.”
\

DVll

l/PD

P—l

rece

ives

bloc

of da
ta

and

checks for data errors. If no error, jump
to 8.

If an error has occurred, PDP-11 sends a
control character (NAK or Negative

- Terminal receives NAK and /

ACKnowledgment) which means ‘‘Please
retransmit last message.”

retransmits last message.

Return to state 6.

PDP-11 responds with an acknowledgment

message (ACK) which says “I received that
OK — send me the next message.”

Terminal sends next block of data or,

if transmission is complete, sends a
control character (EOT — for END-

OF-TRANSMISSION) which says

“l am finished.”

\fl

DV11/PDP-11 receives EOT message and

goes into its closing sequence.

Figure B-3 Typical Data Exchange Using BSC (BISYNC)

Table B-1

BSC Data Channel Control Codes

one DLEi1s disregarded; the otheris treated as data.

Meaning

SYN

‘tion. When a bit pattern equivalent to DLE appears

“within the transparent data, two DLEs are used to
permit transmission of DLE as data. When received,

Control

Code Mnemonic

~control character to be recognized as a control func-

~This technique 1s called *character stuffing.”

Synchronous Idle

B.3.5

Data Channel Utilization

BSC transmission is half-duplex. The line must be

SOH

Start of Heading -

STX o

Start of Text ,- )

’aeknowledgment sequence and once for the data

End of lnterrnediate'Trzrrrs-

and acknowledgments are handled by separate con-

| I‘TB |

turned around twice between each block (once for the
block). All fields are delimited by control characters,

~mission Block
ETB

End of Text

EOT

End of Transmission

acknowledgment

sequence

‘ment sequence. A mrmmum of two character times is

" required for each synchronization.

BSC ‘supports

B.3.6

Synchronization

‘BSC synchronizes on each block or control sequence

Enquir'y.

- ACKO/ACK1

Alternating Affirmative =

‘WACK

| both pomt-to-point and multrpomt hnes |

| ENQ
~

sequences.

required for each block and for each acknowledg-

End of Transmission Block

ETX

trol

by preceding the formatted block with the synchro-

‘nizing (SYN) characters. Two synchronizing characters are required, but more (usually five) are sent.

'SYN is defined as a unique bit pattern in each of the

Acknowledgments

three information exchange codes available with

Wai't.-Before-Transmit Positive
Acknowledgments -

NAK

| Ncgativc Acknowledgment

DLE |

- Data-Link _Escapc

RVI

| Rcveyrse-lntcr‘rupt

BSC. In addition, some BSC apphcatrons require that
all Is PAD chardelers follow messages

B.4

DDCMP PROTOCOL

DDCMP (Digital Data Communications Message

Protocol) was developed to provide full-duplex mes-

sage transfer over stdnddrd existing hardware

B.d.1

TTD |

Témporary Text Delay

DLE EOT

Disconnect Sequence for a

Switched Line

Controlling Data Transfers

- The DDCMP message formatis shown in Frgure B4. A single control character is used in a DDCMP

message, and is the first character in the message.
Three control characters are provrdedin DDCMP to

differentiate between the three possible types of
messages

SOH - data message follows
‘B.3.4

Data Transparency

In BSC, the transparent mode is defined by starting

the text field with DLE STX. Once in transparency,
the only control character of significance is DLE.

Any Data Link control characters transmitted during
the transparent mode must be preceded by

a DLE

ENQ - control message follows

DLE - bootstrap message follows.

Note that the use of a fixed-length header and message size declaration obviates the BSC requirement

for extensive message and header delimiter codes.

syn | | sy
|

S—

con

DATA )

CRC-2

_(ANY NUMBER OF 8-8IT | 1g BiTS

CHARACTERS UP TO 214)

11-2897

Figure B-4 DDCMP Data Message Format
16,383 bytes long. To validate the header and count
field, it is followed by a 16-bit CRC-16 field; all header characters are included in the CRC calculation.
Once validated, the count is used to receive the data
and to locate the second CRC-16, which is calculated
on the data field. Thus, character stuffing is avoided.

Figure B-5 shows a simple example
of data exchange
between the DVI11/PDP-11 and a data terminal.
More efficient procedures can be derived after a
study of DDCMP.

B.4.2

Error Checking and Recovery

B.4.5 Data Channel Utilization
DDCMP uses either full- or half-duplex circuits at
optimum efficiency. In the full-duplex mode,
DDCMP operates as two dependent one-way chan-

DDCMP uses CRC-16 for detecting transmission
errors. When an error occurs, DDCMP sends a separate NAK message. DDCMP does not require an

acknowledgment message for all data messages. The

nels, each containing its own data stream. The only

number in the response field of a normal header or in
either the special NAK or ACK message, specifies
the sequence number of the last good message

dependency are the acknowledgments which must be
sent in the data stream in the opposite direction.

received. For example, if messages 4, 5, and 6 have
been received since the last time an acknowledgment

Separate ACK messages are unnecessary, reducing

the control overhead. Acknowledgments are simply
placed in the response field of the next message for
‘the opposite direction. If several messages are

was sent and message 6 is bad the NAK message

specrfies number 5 which says message 4 and 5 are

good and 6 is bad.” When DDCMP operates in full-

received correctly before the terminal is able to send a
message, all of them can be acknowledged by one

duplex mode, the line does not have to be turned

around; the NAK is simply added to the sequence of

response. Only when a transmission error occurs or

‘messages for the transmitter.

when traffic in the opposite direction is light (no data
When

a sequence error occurs in

message to send) is it necessary to send a special
NAK or ACK message, respectively.

DDCMP, the

receiving station does not respond to the message.
The transmitting station detects, fromthe response
field of the messages it receives (or via tlmeout) that

In summary, DDCMP data channel utrhzatlon fea-

the receiving station is still looking for a certain mes-

tures include:

sage and sends it again. For example, if the next mes-

sage the receiver expects to receive is 5, but 6 is

The ability to run on full- or half duplex
data channel facilities.

received, the receiver will not change the response

field of its data messages, which contains a 4. This

Low control character overhead.

No ‘‘character stuffing.”

SOH, ENQ and DLE. The remainder of the message,

No separate ACKs when trafficis heavy;
this saves on- extra SYN characters and

including the header, is transparent.

inter-message gaps.

says: ‘I accept all messages up through message 4

and I'm still looking for message 5.
B.4.3

Character Codmg

DDCMP uses ASCII control characters for SYN,

B.4.4

Data Transparency

DDCMP defines transparency by use of
a count field

Multlple acknowledgments (up to 2595)
with one ACK.

in the header. The header 1s of fixed length. The

count in the header determines the length of the

The ability to support point-to-point and
multipoint lines.

transparent information field, which can be zero to

B-6

TERMINAL

DVI1/PDP-11

Sends a STRT (START) message which

means:

“‘l want to begin sending data

to you and the sequence number of my

first message will be 1.7

\.‘ @ Receives STRT message.

| ) |

Sends a STACK (Start Acknowledge)
message which means:

“OK with me:

here is the first sequence number (5) |

will use in sending data messages to you.”

Receives STACK.
Sends Data Messages with a response field
set to 4 and the sequence field set to 1,

which means:

*I am looking for your

message 1.”" Other messages may be sent
at this time (i.c., messages 2, 3, ctc.)
without waiting for a response. \..

@ Receives Data Message 1 and checks it for
sequence and CRC errors. If there isa
sequence error, go to 12. If there is no

error, go to 9.

A CRC error was detected. Computer B
sends a NAK message with the response
~

field set to 0, which means:

‘‘All messages

up to 0 (Modulo 256) have been accepted

and message | is in error.”
Computer A receives NAK, retransmits

Message | and any other messages sent
since (i.e.. 2, 3, etc.) if already sent.

| \ @ Sends ACK response of 1 either in a separate
ACK message or in the response field of a

Ol6

data message.
Receives ACK and releases Message |

Continues sending messages.

\ @ Discard message and wait for proper

Times out because of lack of response /

Message 2.

for Message 2. Sends a reply for

Message 2.

\
|
@» Send NACK response of | in the
response field.

Retransmits Message 2 and
following messages.

Figure B-5 DDCMP Sample Handshaking Procedure
B-7

B.4.6 Synchronization
DDCMP achieves synchronization through the use
of two ASCII SYN characters preceding the SOH,
ENQ, or DLE. It is not necessary to synchronize
between messages as long as no gap exists. Gaps are
filled with SYN characters. Two sync characters are

" required, but more are usually transmitted. If synchronization between messages is deliberately lost by

sending PAD (all 1s) characters, the intermessage
interval must be at least 14 character times in length.

B.4.7 Bootstrapping
DDCMP has a bootstrap message as part of the pro-

‘tocol. It begins with the ASCII contro! character
DLE. The information field contains the system
reload programs and is totally transparent.

APPENDIX C

GLOSSARY OF TERMS AND ABBREVIATIONS

ACK - Acknowledgment

Binary Synchronous Communications (BSC) - A uni-

ACK 0, ACK I (Affirmative Acknowledgment) - These

ters and control sequences, for synchronized

form discipline, using a defined set of control charac-

replies (DLE sequence in Binary Synchronous Communications) indicate that the previous transmission
block is accepted by the receiver and that it is ready

transmission of binary coded data between stations in
a

data

commumcatlons systcm

(Also

BISYNC.)

called

to accept the next block of the transmission. Use of
ACK 0 and ACK 1 alternately provides sequential
checking control for a series of replies. ACK 0 is also

BIS YNC - Binary Synchronous Communications.

an affirmative (ready to receive) reply to a statlon,

selection (multipoint), or to an initialization sequence
(line bid)in point-to-point operation.

Block Check Character (BCC) - The result ofa trans~

mission verification algorithm accumulated over a

transmission block, and normally appended at the

“end; e.g., CRC, LRC.
ASCII - American Standard Code for Information

“Interchange. This is the code established as an American standard by the American Standards
Associdation.

Byte - A binary element string operated upon as a
unit and usually shorter than a computer word, e.g.,
six-bit, eight-bit, or nine-bit bytes.

Automatic Calling Unit (ACU) - A dialing device

Carrier - A continuous frequency capable of being

(Bell

modulated or impressed with a signal.

801

or equivalent) that

permits a business

machine to dial calls automatlcally over the communications network.

CCITT - Comite Consultatif Internationale Telegraphique et Telephonique. An international con-

Baseband- In the process of modulation, the base-

sultative

bandis the frequency band occupied by the aggregate
of the transmitted signals when first used to modulate

communications usage standards.

4 cdrrier.

Baud - A unit of signaling speed. One baud corre-

committee that

sets

international

Channel - (a.) A path for electrical transmission
between two or more points. Also called a circuit,

facility, line, link, or path. (b.) The physical facility or

sponds to a rate of one signal element per second.

path plus control codes, within ‘which the actual data

Thus, with a duration of the shortest signal element

to be transferred is embedded.

of 20 ms, the modulation
rate is 50 baud.

Character - The actual
or coded representation of a
digit, letter, or special symbol.

Baudot Code - A code for the transmission of data in
which five bits represent one character. It is named

for Emile Baudot, a pioneer in printing telegraphy.

The name is usually applied to the code used in many

CO - Carrier On.

- Communication Contro/ Chafacter - In ASCII, a

functional character intended to control or facilitate

teleprinter systems and which was first used by Mur-

transmission over data networks. There are ten con-

ray, 4 contemporary of Baudot.

trol characters specified in ASCII which form the

BCC - Block Check Charactcr (q.v.)

procedures. (See also: Control Character.)

basis for character-oriented communications control

Data Link - An assembly of terminal installations
and the interconnecting circuits operating according
to a particular method that permits information to be
exchanged between terminal installations. Note: The
method of operation is defined by particular transmission codes, transmission mode, direction, and

Concentrator - A communications device that pro-

vides a communications capability between many

low-speed, usually asynchronous channels, and one
or more high-speed, usually synchronous channels.
Usually different speeds, codes, and protocols can be
accommodated on the low-speed side. The low-speed
channels usually operate in contention, requiring buffering. The concentrator may have the capability to

control.

Data Set - A device that converts the signals of a
business machine to signals that are suitable for
transmission over communication lines and vice versa. It may also perform other related functions.

be polled by a computer, and may in turn poll
terminals,

Conditioning - The addition of equipment to leased
voice-grade lines to provide specified minimum values of line characteristics required for data transmission, e.g., equalization and echo suppression.

(Same as ‘““‘modem.”).

- Digital Data. Communications Message
DDCMP
Protocol. A uniform discipline for the transmission

of data between stations in a point-to-point or multipoint data communications system. The method of
physncal data transfer used may be parallel, serial

Contention - A condition on a communications channel when two or more stations try to transmit at the
same time.

synchronous, or serial aysnchronous.

Control Character - (1.) A character whose occur-

rence in a particular context initiates, modifies, or
stops a control function. (2.) In the ASCII code, any
of the first 32 characters. (See also: Commumcattons |
Control Character. )

Demoa’ulatzon - The process of retrieving an ongmal
signal from a modulated carrier wave. This technique
is used in data sets to make communication signals
compatnble with business machine signals.

Dial-Up- The use of a dlal or push--button telephone

Control Procedure - The means used to control the
orderly communication of information between stations on a data link. Syn: Line Discipline. (See also:

to initiate a station-to-station telephone call.

Protocol.)

Dibit - A pair of binary digits. Used to encode the
four carrier phase shifts required for blnary modu-

CRC - Cyclic Redundancy Check (q.v.)

lation by modem:s.

Dired 'Memo'ry Access (DMA) - A facility that per-

Cross Talk - Unwanted insertion of signal from an

without passing through the processor’s general registers; either performed independently of the processor or on a cycle-stealing basis. (Same as NPR.)

CS - Clear to Send.
Cyclic Redundancy Check (CRC) - An error detection

DLE (Data Link Escape) - (a.) A control character
used in BISYNC to provide supplementary line-control signals (control character sequences or DLE

scheme in which the check character is generated by
taking the remainder after dividing all the serialized
bits in a block of data by a predetermmed binary
number.

sequences). These are two-character sequences where

Dataphone - A trademark of the

es according to the function desired and the code
used. (b.) A control character used in DDCMP to

the first character is DLE. The second character vari-

A T.&T. Company

signal a bootstrap message.

to identify the data sets (modems) manufactured and
supplied by the Bell System for use in the transmis-

the transmission cf data over the regular telephone "

- In communications, pertaining to a simultaDuplex
neous two-way, independent transmission in both
directions, sometimes referred to as full-duplex.

network (DATAPHONE Servnce)

(Contrast with half-duplex.)

sion of data over the regular telephone network. It is

also a service mark of the Bell System that identifies

C-2

adjacent communication channel.

mits 1/O transfers directly into or out of memory

ldle Loop - See Executive Routine.

EBCDIC - Extended Binary Coded-Decimal Inter-

change Code. An 8-bit character code used primarily
in IBM equipment. The code provides for 256 differ-

ITB (Intermediate Text In Binary Synchronous Com-

ent bit patterns.

munications, Block) - A control character used to ter-

Echo - A portion of the transmitted signal returned

block check character is sent immediately following

minate an

intermediate block

of characters. The

from the distant point to the source with sufficient

ITB. but no line turnaround occurs. The response fol-

magnitude and delay so as to cause interference.

lowing ETB or ETX also applies to all of the ITB

checks |mmcdmtely preceding the block terminated
ENQ (Enquiry) — (a.) Used in BISYNC as a request -

for

response

obtain

identification

and/or

by ETB or ETX.

indication of station status. ENQ is transmitted as

l. - Low.

part of an imtialization sequence (line bid) in pointto-point operation, and as the final character
of a

Line - See Channel.

selection or polling sequence in multipoint operation.
(b.) Used in DDCMP to signal a control message.

Link - See Channel.

EOT (End of Transmission) - Indicates the end of a

Longitudinal Redundancy Check (LRC) - A system of

transmission, which may include one or more mes-

error control based on the transmission of a Block

sages, and resets all stations on the line to control

- Check Character (BCC) based on preset rules. The

mode (unless it erroneously occurs within a transmis-

check formation ruleis appliedin the same manner to

stion block). EOT is also transmitted as a negative

cach character.

response to a polling sequence.

L.RC - Longitudinal Redundancy Check.
ETB - End of Transmission Block.

Mark - Presence of a signal. In telegraphy, mark repETX (End of Text) - Indicates the end of a message.

resents

If multiple transmission blocks are contained in a

Equivalent to a binary one condition.

message 1n

the

closed

condition

current

flowing.

BSC systems, ETX terminates the last

block of the message. (ETB is used to terminate pre-

Modem - Contraction of modulator-demodulator. A

ceding blocks.) The block check character is sent

device that modulates and demodulates signals trans-

immediately following ETX. ETX requires a reply

mitted over communication facilities. (Same as data

indicating the receiving station’s status.

set.)

Executive Routine - A program that monitors system

Modulation - The process by which some character-

activity and transfers control to subordinate pro-

istic of a high-frequency carrier signal is varied in

grams for handling. When handling is complete, con-

accordance with another lower frequency *“‘informa-

trol 1s returned to the executive. When the system is

tion signal. This technique is used in data sets to

Inactive, the executive spins in an idle mode.

make business-machine signals compatible
with com-

munication facilities.

Facility - See Channel.
Multiplexing- The division of a transmission fac:hty
Full-Duplex - See Duplex.

into two or more channels.

H - High (positive).

Multipoint Circuit - A circuit interconnecting several

stations.
Half-Duplex - Pertaining to an alternate, one-way-ata-time

duplex.)

independent

transmnsnon

‘

(Contrast

with

NAK ( Negative Acknowledgment) - Indicates that the

- previous transmission block was in error and the

receiver is ready to accept a retransmission of the
erroneous block. NAK is also the ‘‘not ready” reply
Header — The control information prefixed in a mes-

sage text, e.g., source or destination code, priority, or

initialization

message type. Syn: Heading, Leader.

operation.

C-3

a station

selection

(multipoint)

to an

sequence (line bid) in point-to-point

Non-Processor Request (NPR)- High priority data
transfers to the PDP-11 Processor. These are direct

- RS - Request tb Send.

memory access type transfers, and are honored by the
processor between bus cycles of an instruction execu-

" SDLC
- Synchronous Data Link Control. A protocol

tion. NPR data transfers can be made between any

point, multipoint, or loop arrangement, using syn-

two peripheral devices without the supervision of the
processor. Normally, NPR transfers are between a

chronous data transmission techniques.

mass storage device, such as a disk and core memory.

Seizure Line - Terminating a transmission line in a

An NPR device has very fast access to the bus and

an instruction is in progress. (See DMA.).

DC path, causing a relay element in the telephone
switching network to trigger and complete the circuit
between the calling station and the called station.
Voice or data is then inductively coupled between the
transmission line and the terminal. Equivalent to tak-

Non-Transparent Mode - Transmission of characters

phone instrument or data set.

for the transfer of data between stations in a point-to-

can transfer at high data rates once it has control.

The processor state is not affected by the transfer;
therefore, the processor can relinquish control while

defined

character

format,

e.g.,

ing the handset **off the hookTM ofa conventional tele-

ASCII

EBCDIC, in which all defined control characters and

| Selective Calling - The ability of a transmitting sta-

control

tion to specify which of several stations on the same
line is to receive4 message.

character

sequences

are

recognized

and

treated as such.

Serial Transmission - A method of information transfer in which the bits composing a character are sent
sequentially. (Contrast with parallel transmission.)

NS - New Sync.

Parallel Transmisson - Method of information transfer in which all bits of a character are sent simultaneously. Contrast with serial transmission.

Signal - In communication theory, an intentional disturbance in a communication system. (Contrast with

Path - See Channel.

noise.)

Silo - A first-in, first-out hardware buffer, such as the

Polling- A centrally controlled method of calling a
number

points

permlt

them

RC Silo and the NSR
in the DV, which use the

transmit

3341 Propagable Register 1.C., described in Appen-

information.

dix B.

Priority or Precedence - Controlled transmission of
messdages in order of their desngnated Importance;

Simplex Mode - Operation of a channel in one direc-

e.g., urgent or routine.

tion only with no capability of reversing.

Private Line or Private Wire - A channel or circuit

Smg/e Address Mewage - A message to be delivered

furnished to a subscriber for his exclusive use (non

to one destination only

~dial-up).

Start of Heading (SOH
) - (a.) In Bmdry Synchronous
Communications (BISYNC), precedes a block of
heading characters. (b.) In DDCMP, signals a data

Protocol - A set of rules which govern the sequencing,

1dentification,

and

synchronization

data

exchanged between data terminals.

messdage.

RC - Received Character.

Station - One of the input or output points on a com-

munications system.
Reverse Interrupt (RVI) -

Binary Synchronous

Communications, a control character sequence (DLE

Stuffa DLE - Send a Data Link Escape character

sequence) sent by a receiving station instead of ACK
1

just prior to the character to be transmitted.

or ACKO to request premature termination of the
transmission In progress.

- STX - Start of Text.

C-4

Svnchronous Idle (SYN) - Character used as a time

entry to and exit from the transparent mode is

fill in the absence of any data or control character to

“indicated by a sequence beginning with a special Data

maintain synchronization. The sequence of two con-

Link Escape (DLE) character.

tinuous SYNs 1s used to establish synchronization

TTD - Temporary Text Delay (q.v.).

(character phase) following each line turnaround.

Svstem Unit - Three 8-slot connector blocks mounted

Unibus - The single, asynchronous, high-speed bus

end-to-end and capable of accommodating up to four

structure shared by the PDP-11 processor, its memo-

~hex modules (printed circuit boards). When two sys-

rv, and all of its peripherals.

tem units are connected to form a double system unit,

Unibus Load - The electrical connection of two 8881

up to nine hex modules may be accommodated.

outputs and one 8640 input to a Unibus signal lead.

Teletypewriter Exchange Service (TWX) - An automatic teleprinter exchange switching service provided

Unit Load - All inputs impose a load on the outputs

by Western Union.

driving them. A TTL unit load requires 1.6 mA at
ground and +40 uA at +3 V. The load imposed upon

an output by an input can be defined as a number
of

Telex - An automatic teleprinter exchange switching

unit loads.

service provided by Western Union.

Temporary Text Delay (TTD) - In Binary Synchro-

Vector - Two words, containing the value of the pro-

nous Communications, a control character sequence

gram counter and processor status word, respective-

(STX...ENQ) sent by a transmitting station
to either

ly, that direct the processor to a new routine.

indicate a delav in transmission or to initiate an abort

ol the transmission in progress.

Vector Address — The address of the location containing the vector words.

Term - Terminal.
Vertical Redundancy Check (VRC) - A check or par-

Terminal - (a.) A point at which information can

ity bit added to each character in a message such that

~enter or leave a communication network. (b.) An1/0
device designed to receive or send source data in an
environment associated with the job to be performed.

the number of bits in each character, including the

parity bit, 1s odd (odd parity) or even (even parity).

Volatile - A storage device whose contents may be

Capable of transmitting entries to and obtaining output from the system of which it is a part.

altered by a power shut-off. The DV11 RAM is a volatile device.

Text - That part of the message which contains the
substantive information to be conveyed. Sometimes

- VR(C - Vertical Redundancy Check.

called **bodyTM of the message.
WACK - Wait-Before-Transmit Positive Acknowl-

Mode - Transmission of binary data

edgments. In Binary Synchronous Communications,

with the recognition of most control characters sup-

this DLE sequence is sent by a receiving station to

pressed. In

indicate that it is temporarily not ready to receive.

Transparent

Binary Synchronous Communications,

C-5

DV11 COMMUNICATIONS MULTIPLEXER

USER'S MANUAL
EK-DV11-OP-001

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