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EK-DV11-MM-002

November 1976

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Document:	DV11 Communications Multiplexer Maintenance Manual
Order Number:	EK-DV11-MM
Revision:	002
Pages:	244
Original Filename:

OCR Text

DV11 communications

multiplexer
maintenance manual

dlilgliltiall

'EK-DV11-MM-002

DV11 commumcatmns N
multlplexer

mamtenance manual

digital equipmen’t corporation - maynard, massachusetts

1st Edition, August 1975

2nd Edition (Rev), November 1976

Copyright © 1975, 1976 by Digital Equipment Corporatibn
The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes no respon-

sibility for any errors which may appear in this
|

manual.

Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

PDP

DECtape

DEC

DECUS
DECCOMM
DECsystem-10 ~ DIGITAL
MASSBUS
DECSYSTEM-20
|

RSTS
TYPESET-8
TYPESET-11
UNIBUS

CONTENTS
|

. CHAPTER 1

Page

INTRODUCTION AND GENERAL DESCRIPTION

PURPOSEANDSCOPE

. .. ........... [P

1-1

DV11 COMMUNICATIONS MULTIPLEXER ... ...
.. ... e 1-1
DV11 Overview Block Diagram
. . . . .. ... .. ... ...... Lo 11
D

et jed

Establishing the Data L1nk

DVI11 Operation

Reference Documents
[N

PHYSICAL DESCRIPTION

General Specifications

................... Lo

12
. . . . .. .. ... ... ... .. ... ... 12
. . . . . . .. e
e e e e e e e e e e e e
1-3
. .. ... ....... [
e
e e
1-3

. . . .. ... ... ...... ..., . ...,

CHAPTER 2

INSTALLATION

2.1

SITE PREPARATION AND PLANNING

. . ... .. e

e e e A|

2.1.1

Minimum Through Maximum Configurations

2.1.2

. . . ..

- Compatibility Considerations and Precautlons

... ... ... -

2-1

e e

e e e e eL

2-1

. . . . . . . .. ...
.. . ....

2-2

2.1.3
- 2.14
2.14.1
-

2.1.4.2

- 2.143

2.1.5

Interface Specifications and Signals

Interrupt Priorities and Address As31gnments

Interrupt Priorities

e e e e e e

. . . . . . ... ...

- Interrupt Vector Address Ass1gnment

Address Assignments
Environment

e ee

. . . ... ... ... ...

2-2

2-2
2-2

... L.

2-2

oo oo

2-4

. . . . . .. ...

2-2

2.2

UNPACKING AND INSPECTION

2.3

INSTALLATION OF BASIC ASSEMBLIES

2.3.1

. . . . . . . . . ... .. ... 24

Unibus Cable Interconnections

. o v

. . . @

. . . . . . . . . . . o

MODULE INSTALLATION AND CUSTOMIZING

. -

2-5

e e e e e e e e ee e

255

2.4.1

Unibus and Interrupt Vector Address A531gnments

2.4.2

Synchronous Parameter Selection

2.4.3

Resistance Checks

244

Installation of Add-OnDV11

. ..

........... - 2-5
... ... e, 2-13

. . . . ... .. ... ..... e e e e

. ... ... ... e

2.5

SYSTEM CHECKOUT

'CHAPTER 3

PROGRAMMING

3.1

PROGRAMMABLE FACILITIES AND F UNCTIONS

3.1.1
3.1.2
3.1.2.1

3.1.2.2

3.1.2.3
3.1.2.4
3.1.3

3.1.3.1
3.1.3.2

3.1.3.3
3.1.34
3.1.35

3.1.4

3.14.1

3.1.4.2

e e 2-16

e e e e e e 2-16

. . . . . . . . . .

Programmable Registers

2-17
o

e e e e e e e e

. . . . ... .. ... .. e

3-1

e e e L.

341

. .. ...
. e eControl Table Format
. . .. .. ... ... ...........

Control Table

3-4

Receive Control Byte

. . . . . . . . . . . . ..

Transmit Control Byte

3-4

. ... .. e e e e e e e

3-5

Control Byte Symmetry . . . . . e
e,
Operations With Directly-Addressable Registers . . . . . . P
Mod
Setup and
em
Control

Accessing Secondary Registers

3-5

. . ... ... ............

. . . ... ... ... ......

3-6

Data Transfer Enabling
. . ... ... ... ...........
3-6
Interrupt Enabling and Response . . . . ... ... ....... - 3-6
Extended Memory Addressmg ................... 3-6
Protocol Processing
. . . . . . . . . . ... ... - 3-6

BCC Polynomial Selections

. . . . . . .. ... .. .. .. ...

Processing Block Terminations

. . .

. . . . . .

. . . . . . ..

3-6
3-6

CONTENTS (Cont)
Page

3.14.3
3.14.4

3.1.4.5
3.1.4.6
3.1.4.7
3.1.5

3.1.5.1
3.1.5.2

3.2

3.2.1

3.2.2
3.2.3

3-7
3
3-7

Data Transfer Operations
. . . ...
. . .. e e e e e e e
e e e e
Provision for Alternate Data Transmission Tables . . . . ...
.
Table Size and Location . . . . . . . . . . . . .o

3-7
3-7
3-8

Stripping Received Syncs . . . . . . . . R U
Line Activity Snapshot
. . . . . . .. .. .. .... .

DIRECTLY-ADDRESSABLE REGISTERS

3-7
3-7

. . . . ... ... e ... 3-8

System Control Register (SCR)
. . . . . .. .. e e e e e e 3-8
Line Control Register (LCR)
. . . . . .. ... .. ... e e
e .. 3-8
Receiver Interrupt Character Register (RIC)
. . . . . . ..
. .. ... 315
NPR Status Register (NSR)
. . . . . .. e e e e e e e e e e e 3-15

3.2.5

Reserved Register

3.2.6

Special Functions Register (SFR) ............... e
. 3-20
Secondary Register Selection Register (SRS)
. . o v, 3-20
Secondary Register Access Register (SAR) . . . . . . .. ... .... 3-24

3.2.7

3.2.8

3.2.9
3.3

3.3.1
3.3.2
3.3.3

3.34

. . . . . e e e

e e

e 3-20

Modem Control Registers . . . . . e e 3-24
INDIRECTLY ADDRESSABLE (SECONDARY) REGISTERS . . . ...
. 3-29
Transmitter Principal Current Address (0000) . . ...
.. .. ... 329
Transmitter Principal Byte Count (0001) . . . .. .. .. ...
.. .. 329

Transmitter Alternate Current Address (0010)

Transmitter Alternate Byte Count (0011)

. . . . . ..

.. ... 3-32

. . . . . ... ... ... .. 3-32

3.3.8

Receiver Current Address (0100) . . . . . .. .. e e e e e e e e 3-32
Receiver Byte Count (0101) . . . .. ... ... e
e e 3-32
Transmitter Accumulated Block Check Character (0110) . . . . .. L. 3-32
Receiver Accumulated Block Check Character (O111)
. . . . . . . .. 3-32

3.39

Transmitter Control Table Base Address (1000)

3.3.10

Receiver Control Table Base Address (1001)

3.3.5
-

Control Byte Inhibit . . . . . . . . . . . . ..o oL
- Sync Character Selection
. . . . . ..e
e e e e e e e e
Sync/Mark State Select
. . . . . . .. ...

3.3.6
3.3.7

. . . . ... ...
... 3-33
. . . . . . .. .. .. .. 333

3.3.11

Line Protocol Parameters (1010)

3.3.12

Line State (1011)
. . . . . . . .o
e e e e e e 3-33
Transmitter Mode Bits (1100) . . . . . . . . . . . . ...
..., . 3-33
Receiver Mode Bits (1101)
. . . . . . . . . . ..
. oo 3-33

3.3.13
3.3.14
3.3.15
3.3.16
3.4
3.5

3.5.1
3.5.2

3.6

3.6.1
3.6.2

3.6.3

3.6.4

Line Progress (1110)

. . . . . . .. J

3-33

. . . .. ...
. e 3-33 .

Receiver Control Byte Holdlng(llll)
. S K
CONTROL BYTE FORMAT
. . . .. . o it et it e e e 3-39
DV11 INITIALIZATION
. . . . o o
e e e e e e e e e e e e e ... 341
Line Modem Setup
. . . . . . . . .. ... ... .. e
e e e e e 341
DV11 Data Transfer Setup
e
e e e e e e
e e e e e e 341
DATA TRANSFER IMPLEMENTATION e e e e e e e e e e e e e
e 3-41
Originating
and Answering Calls . . . . . ... ... ..........342
Resynchronization During Reception . . . . . ..
. .. e e e e e 3-42
Termination of Transmission and Recept1on
......... I 3-42
BISYNC Implementation
. . . . .. ... ... ... ... ... ... 343

CONTENTS (Cont)
Page

3.6.4.1

Transmission Control

3.6.4.2

Reception Control

3.6.5

3.6.5.2

Reception Control

CHAPTER 4

PRINCIPLES OF OPERATION

4.1

SYSTEM BLOCK DIAGRAM

. . . ... ... T

4-1

e e e e e e e e
. . . . ... ... ....... e
e e e e .
Line Selection and Character Transfer . . . .. ... ... .. ..

4-4

. ..
. .. e

. . . . .. ... ... ... e

Random Access Memory (RAM)
NPR Operations

Programmable Registers

4.3

DV11 MICROPROGRAM

4.4

DATA RECEPTION

4.4.3.4

4.43.5

- 44.3.6
4.4.4

4.4.5
4.4.6
4.4.6.1

4-4

. . . .. ... ... .. I
. . . .. .. ... ... e,

4-7

. .

... ... ....... e e

. ... .. ..... e
e
e
Responding to the Synchronization Character(s)

4.5.2
4.5.2.1

4.5.2.2

4-7

e e e, 4-11

Processing Block Check Characters

. . . . . ..

... ... .. 4-14

Handling DDCMP Receive Mode

. . . ... ... ... e e 4-14
Computing the Control Byte Address
e
e e e e e e e, 4-14
Control Byteto ALU

. . . ... ... e .. 4-14

Interpretmg the Receive Control Byte

Storing the Character
in Core Memory

. . . . . . ... ... ... .. . 4-14

Terminating the Data ReceptionProcess
Processing for Normal Byte Counts
Handling Receiver Interrupt Characters

4.5.1

e e e

e
e e 4-11
. . . . . . .. .. ... .. ... ... .. 4-12
Fetching the Control Byte . . . . . . . e e e e e e
e e e
e e 4-12
Initial Tests
. . . ...
.. .. e e e e
e e e
e
4-12
Handling Exceptional Condltlons
..... R 4-12

Handling Resynchronization Request

4.5.1.1

4-6

Character Inputto RCSilo

4.4.8
4.5

4-4
44

4-6

4.4.6.2
4.4.7
4.49

4-4

. ..

. . . . ...

Unibus Interface

. . . . . . . . . . v

... ... .........

Modem Enabling and Control

Modem Selection and Scanning

- 4.4.3.3

LINE MODEM SELECTION AND CONTROL

4.2.2

4.4.3.1

... .... e

. . . . . . .e

4.2.3

4.4.3.2

. ..

e e ...
. . .. .. .. .. O

4.1.4

4.4.3

e e e e e e e

Computations

4.1.5

4.4.2

e e

441

Microprocessor

44.1

e e e

4.1.2

4.2

e e

e ...

Modem Control Unit (MCU)

42.1

I VK”.\\\,

4.1.1

4.1.3

3-43
e e 3-43

. . . .. ... ... .. ... ... ..... 3-47
. . . . . . . . .. . .. ... ... .... 3-47
. . . . . .e
e e e e e e e e e 3-48

Transmission Control

4.1.2.2

DDCMP Implementation

3.6.5.1

4.1.2.1

. . . . . e

. . . . . ...
. e e e e e e e e

. . . . . ... .. ... .... 4-15
. . . .. .. ... .. ... . 415
. . . . . ... .. ... ... 4-15
. . . ... . .. ... . ... 4-15

Processing for Marked Byte Counts

Handling Receive Errors

DATA TRANSMISSION

. . . . . . . . . ... ... .. 4-15
. . . . .. ... ... e

. . . . . .. ...
... e

. . . . .. . e

Fetching
the Transmit Character

e e . . 415

e e . ... 4-15

e e e e e e e e e . 4-16

. . .

. ... . . ...
.. .. .. 4-16

Handling DDCMP Transmit Mode

. . . . . . ... .. ... ... 4-19

Fetching the Control Byte

. . . .. .. ... e
e e e e e e e e e e 4-19
Computing the Control Byte Address
A
w8
Control Byteto ALU
. . . .. ... ... ... ... .. .... 4-20

CONTENTS (Cont)
Page

4.5.3
4.5.4

4.5.5

4.5.5.1
-

4.5.5.2
4.5.6

4.5.6.1
4.6
4.6.1
4.6.2

4.6.3

4.6.4
4.7

4.7.1
4.7.2
4.7.3

4.7.4
4.7.5

4.7.6
4.7.7
4.7.8

4.7.9
4.7.10
4.8
4.8.1

4.8.1.1

4.8.1.2
4.8.1.3
4814
4815
48.1.6

48.1.7

4.8.1.8
4.8.1.9

4.8.2
4.8.2.1

4.8.2.2

4.8.2.3

4.82.4
4.8.2.5
4.8.2.6
4.8.2.7
4.8.2.8

4829

Interpreting the Transmit Control Byte

. . . . . .. ... ... .. .. 420

. . . . . . . . .« o o v i v v vt oo e e 4-20
Character Transmission
e e e e e i e e e e e 4-20
... ... .. e
Termlnatmg DataBlocks
... . 420
Control Byte Termination . . . ... ... ... ... e
... 4-21
...
...
.
...
.
.
.
.
Termination
Marked Byte Count
‘Handling Transmit Interrupts . . . . . . . . . ... ... 4-21

Processing Frrors

. . . . . .. ... .. R P 4-22

e e e e 4-22
e
. ... ... ..... e e e e
UNIBUS INTERFACE
e e e e e e e 4-23
e
e
Interface Operations . . . . . e e e
e e e e e e e e e e e 4-23
DV11 Selection . .. ... .. ..... e
e e e e e e e e e 423
‘Non-Processor Requests (NPRs) ........ e
e e e e e e e e e e e e e e 4-24
Data Interrupts . . . . . . .. .. e
MICROPROCESSOR INSTRUCTIONS e e e e e e e e e e e e e 4-24
. . . . . .. O 4-24
Unibus/Transfer Bus Interlock
DV11 Timing . .. ... ... e e e b e e e e e e e e e 4-26
4-27
e
A (BRA) . . o v i v e e e e e e e e e
Branch
e e e e e .. 427
. ....... e
BranchB(BRB) . . . ..
Arithmetic and Logic Unit (ALU) Operatlon e e e e e e e e e e e 4-28
RAM Operation (RAM) . ... ........ e e e e e e i e e 4-29
e ... . 430
.e
. .. . . ...
Data Transfer (XFR)
e e e e e e 4-30
Non-Processor Request (NPR) Operatlon e e e e
.431
Set/Clear (S/C) Operation . . . . . . . . v o v v
4-31
.
e
e
e
e
e
e
e
Operatlon
(BCC)
Character
Check
Block

- LOGIC DIAGRAM DESCRIPTIONS

. .. .. ... ... .. e

e e e e e 4-33

e e

e e 4-33

e e e e 4-33
ALU and Transfer Bus Drawing e e e e e e e
e e e e e e e e e e e e e 4-33
M7836 (D1-1) . ... .. .. e
M7836(D1-2) .. ... e . . 4-33
... 433
e
e e e
e
M7836 (D1-3) .. .. ..... e
e 4-33
M7836 (D1-4) .. . . .

M7836 (D1-53)

. o v v

e e e

e e e e e e

M7836 (D1-6)
M7836 (D1-7)
M7836 (D1-8)
M7836 (D19)

.. ... e e e e e e e e e e e e e 4-33
. ...
... ... .... e e e e e e e e e.. ... 433
e e e e .. 433
e
. . . . . i
e e 437
e e ee
ee e
.. ... .. e

M7837(D2-1)

.. ... e
. ... ...

Unibus Data and NPR Control Drawmg

e e e e e e e e
e

e e

e e 4-37

e e e ... 437

M7837(D2-2) ... ... ... "
M7837 (D2-3)

M7837(D24)

M7837 (D2-5)

SC ¥

. e e
.. ...

e e e e 4-37

e e e e e .. 437

.. .. .... e e e

e e e e e e e e 4-37

... .. e e e e e e

M7837 (D2-6) . . . .
M7837 (D2-7) . . . .
M7837 (D2-8) . ...
M7837 (D2-9) '+« o v

. . S ... . 438
... ... e e ee e e e e 4-38
e e e e e e e e e 4-38
..... . e
e 4-38
e e e e e

CONTENTS (Cont)
Page

4.8.3

ROM, RAM, and Branch Drawing

4.8.3.1

4.8.3.2

4.8.3.3

4.8.3.4

4.8.3.5

4.8.3.6

4.8.3.7

4.8.3.8

M7838 (D3-2)

. . . .

M7838(D3-3)

... ... B 4-39

- M7838(D34)

......... e

e e e

M7838(D3-5)

. . ..

MT838(D3-6)

.. .

48.3.11

4.8.4

e e e e e e e e e

e e

..... e

M7838 (D3-10)

... .. e

M7838 (D3-11)

. . . . .

e e e

4844

M7839 (D4-4)

. . . . .

e e e e

........... 4-40

e e e

M7839 (D4-8)

48.5

e e e 4-40

e e 4-41

e e e e 4-41

M7839 D4-6) .. ... ..... e e e e i
|

e 4-40
e el 4-40

440

e e e

M7839 (D4-7) . .. .. e e e e e e e

4.8.4.8

M7839 (D4-5) .. ...
. ee e e

4.8.4.77

e 4-41

e e

e e 4-41

e e e e e

e e

e 4-42

e e e e e e e e e ee

e eie wwa e eiwie e 4-42

Asynchronous Receivers and Transmltters S
-

4.8.5.2

4.8.5.3

4.8.5.4

4.8.5.5

4.8.5.6

48.5.7

4.8.5.8

|
»

4.8.5.10

M7833 (D4-1 — D4- 10)

e e 4-42

48.6.1

M7833(D4-2)

. .

M7833(D4-3)

. ... ... ... VL e 4-43

... ... ... e

M7833 (D44)

. . . . .

M7833 (D4-5)

... .. e

4.8.64
|

4.8.6.6

4.8.6.7

4.8.6.8
-

4-42

4-44
e

e e 4-44

M7833(D4-6)

. . ...

. ... .. P

... e e 4-44

.. ...e

e e e

R 4-47

e e, 4-47

e e e

e e

... ... e

e e e e 4-48

s e 4-49

e e

e e 4-49

M7807(MD2)

.. ...... e e e T R 4-49

M7807 (D3)

. . . o

M7807 (D4) . . .

4.8.6.5

4-42

M7833 (D4-7)

‘M7807(D1) ...

B k)

. ... .... S

DVll Modem Control Unit Drawmg

4.8.6.2
4.8.6.3

... .. e e e e e e e e e e

M7833(D4-1)

M7833 (D4-9, D4- 10)

4.8.6

4-42

Universal Asynchronous Recewer/Transmflter (UART)

- M7833(D4-8)

4.8.5.11

4.8.6.10

e e 4-40

. . . . . 4-40
. . . .

4.8.6.9

M7839 (D4-1)

... ..

e e 4-39

e
e
e e 4-40

M7839 (D4-3)

4.8.5.9

e
e

e e e

M7839 (D4-2)

4851

e ee e

4.8.4.2

4.8.4.5

e 4-39

e e e e e

4.8.4.3

4.8.4.6

e e

... .. ... .. "............. 4-39

Synchronous Receivers and Transmltters Drawmg

4.8.4.1

e e 4-39

e e e e e e e e 4-39

M7838(D3-9) . ... .....

4.8.3.10

)/—\\\\

e e e e

M7838 (D3-8) . ... .......

4.8.3.9

. . .. ... .. ... 4-38

.. ... ... e e e

M7838 (D3-7)

. . . . . . ..

M7838(D3-1)

M7807 (D5)

. . . o

e
e

e e

4-49

e 4-49
e e

4-49

M7807(D6)

.. ... e

e e

M7808 (D7)

. . . v o o e

M7808 (D8)

... ... T 4-49

M7808 (D9)

. . .o i

e e

e e e e e e 4-49
4-49

e 4-50

M7808 (D10) . ... .. ... ...... ............ 4-50

Vii

CONTENTS (Cont)
Page

M7808 (D11)

48.6.11

o oo oo e e

4-50

4.8.6.12

CHAPTER 5
5.1

5.1.1
5.1.1.1

5.1.2
5.1.3

52
5.2.1

MAINTENANCE
PROGRAMMABLE REGISTER MAINTENANCE FUNCTIONS

. . .. .. .

541

Microprocessor Diagnostic Functions
. . . . . . . . . . . . . . . ...
~ Special Functions Register (SFR) . . . .. ... ... ... ...

5-1
5-2

Data Transfer Diagnostic Functions

5-2

5.2.1.1

5.2.1.2
5.2.1.3

. . . ... ... ... .. e

DZDVB Diagnostic
DZDVC Diagnostic

. . . . . .. . e 5-6
. . . . v v v vt e e e co.. 56

DZDVD Diagnostic

5.2.1.5

- DZDVF Diagnostic

5.2.3

e e e e

e e

5-5

. . . . ... .

. . . . .. .... e

e e e

DV11 Modem Control Unit Dlagnostlcs .................

Modem Control Unit On-Line Tests

e ..

. . . . . . . L P ...

. . . . . o o oo v v v e e

5.3

TOGGLE-IN PROGRAM

APPENDIX A

PDP-11 MEMORY ORGANIZATION AND ADDRESSING CONVENTIONS

APPENDIX B

INTEGRATED CIRCUIT DESCRIPTIONS

B.1

INTRODUCTION

e e e e

s e e d e e e e e
e e-~

B-1

PR1472B SYNCHRONOUS RECEIVER (P/SAR)

. ... ... ... ... .

B-2

. . . .. .. ... e e

B-3

B.2.1
B.3

B.3.1
B.4

DZDVA Diagnostic

52.1.4

5.2.2

. . . . . . . . . . . . .. .. ...

Modem Control Unit (MCU) Diagnostic Funct1ons
........... 5-5
DIAGNOSTIC PROGRAMS . . . . . . .
e e e e e e e e d e e - 55
DV11 Data Handling Section Diagnostics . . . . . . . .. .. .. ... 55

. . .. .

Synchronous Mode Operation

PT1482B SYNCHRONOUS TRANSMITTER (P/ SAT)
Synchronous Mode Operation

. . . . . . . . v v v v v v v v

- UART FUNCTIONAL DESCRIPTION
.

............
.. ..

. . . . . v v v v e e it e e e

B.S

1488 QUAD LINE DRIVER

. . . . . . . o

B.6

1489L QUAD LINE RECEIVER

18-11660 CRYSTAL OSCILLATOR SPECIFICATIONS

B-22

e e e

B-23

e e e e e .

B-24

... ...... .

B-25

B.8

3106 256-BIT RANDOM ACCESS MEMORY (RAM)

3341 4-BIT X 64-WORD PROPAGABLE REGISTER (FIFO)

B.10

4007 DUAL-BINARY TO ONE OF FOUR-LINE DECODER

.. ..

B-27

........

B-28

e e e e e e e e e e e e e e

B-29

B.11

4015 QUAD TYPE D FLIP-FLOP

B.12

5603 PROGRAMMABLE READ-ONLY MEMORY (ROM)

B.13

7442 4-LINE TO 10-LINE DECODERS

B.14

7450 DUAL 2-INPUT AND-OR-INVERT

B.15

7489 64-BIT READ/WRITE MEMORY

. . . .. e

B-16

s e

. . . ... .. ... .... e

B-9
B-10

. . . .e

...

. ... .....

e e e e .. .....

...
. .. e e e e e e e e e e
..

B-33
B-34

e e e .. .....

B35

74121 MONOSTABLE MULTIVIBRATOR . . . . . .. .. .. ... ...

B-36

7492 FREQUENCY DIVIDER

. . . . ... ... ... e

B.17

7493 4-BIT BINARY COUNTER

B.18

viii

. . ...
.. ... e

v v

B3l

'B-32

e e e e e e

B.16

. . . . . . . . . . .

B-30

CONTENTS (Cont)

B.19

B.20
- B.21

74123 MONOSTABLE MULTIVIBRATOR

. .. ... ..e

74150 DATA SELECTOR/MULTIPLEXER

. . . ... .. .. ......

74151 DATA SELECTOR/MULTIPLEXER

B.22

74153 DUAL 4-TO-1 DATA SELECTOR

B.23

. . . . . ... .. ... .....

B.25

74154 4-TO-26 DECODER-DEMULTIPLEXER
74155 3-LINE TO 8-LINE DECODER
74157 2-TO-1 MULTIPLEXER . ... .. e
e e

B.26

74161 4-BIT BINARY COUNTER

B.24

e e e

e e e e e e e

B.27

74174 HEX D-TYPE FLIP-FLOP

. . . . . . .. .. ... ... ......

B.28

74175 QUAD D-TYPE FLIP-FLOP

. . .. .. ... ... . ........

B.29

74181 ARITHMETIC LOGIC UNIT (ALU)

B.30

74193 SYNCHRONOUS 4-BIT UP/DOWN COUNTER

B.31

74197 50 MHz BINARY COUNTER/LATCH

. . .. . ... ... .. ....
. .. ...
.. e e

. .. ... .. ... ..... |

B.32

8242 4-BIT DIGITAL COMPARATOR

B.33

. . . o o o o o

8266 2-INPUT 4-BIT DIGITALMUX

. ... ... ... ... .......

B.34

8271 4-BIT SHIFT REGISTER

. . . . . . . . ... ... ... ......

B.35

APPENDIX C

C.1

'~ SYNCHRONOUS SERIAL DATA HANDLING
BINARY DATA TRANSFER METHODS

. ... ... ...e e e e

e ..

C.1.1

Parallel
vs Serial . . . . . . .. e

C.1.2

Asynchronous vs Synchronous
Synchronizing at the Receiver . . . . . . . . . . . . . . ... .. ...

C.1.3

e e e e

s e

APPENDIX D

PROTOCOLS FOR BINARY SYNCHRONOUS COMMUNICATIONS

D.1

DATA CHANNEL UTILIZATION

D.1.1

Direction Utilization

D.1.2

Control Overhead

D.1.3

Acknowledgement Handling

D.1.4

Stations Per Line

D.2

e e

. . . . ... ... .............

DATA AND CONTROL CODES

D.2.1

TypesofData

. . ... .. ............

D.2.1.1

Transparent Data

D.2.1.2

Character Codes

. . . ... ... e e

D.2.2

Synchronization Codes

D.2.3

Error-Detecting Codes .

D.3

|
. .

. .

BSC PROTOCOL (BISYNC)

D.3.1

. e e

ee e

'
e

e e

e e e

Controlling Data Transfers

D.3.2

Error Checking and Recovery

D.3.3

Character Coding

D.3.4

. . . .

.. e

Data Transparency

D.3.5

Data Channel Utilization

D.3.6

Synchronization
. . ... ... ... ....

e e.

'CONTENTS (Cont)
Page

DDCMP PROTOCOL

D.4

. . . . . e S'

D.4.1

Controlling Data Transfers

D.4.2

Error Checkingand Recovery

D.4.3

Character Coding

D.4.4

Data Transparency

D.4.5

Data Channel Utilization

D.4.6

Synchronization

DA4.7T

Bootstrapping

APPENDIX E

. . . ...
.. .. e e e e e e e

. . . . . . . . . .. .. ...
. ... .

. . .. ... ... e e e e e .e e e e e e e

. ..
. ..e .e e

D-5
D6

D-6

e e e e e e

D-6

. . . .. .. ... ... .....e e

D-6

. . . . . . . . . . .«
. . ...

D-5

e e

... .. e e e e e e e e e e e

e e e e »
e e e e e

D-8

GLOSSARY OF TERMS AND ABBREVIATIONS

ILLUSTRATIONS
Title

Figure No.

1-1

DV11 Overview Block Diagram

1-2

DV11 Communications Multiplexer

Page

. . . . . . . . . . . .. ....

- DV11 Interconnection Diagram

e e e |

1-5

. . . . . . . ... ... .. ...... .

2-4

. . . . . . .. e

e e e e e

Module Utilization Diagram . . . . .. « v v v v v v e P
DV11 M7836 Module — Device Address Selection Switches
. . . . . .o

2-2
2-3

DV11 M7837 Module — Interrupt Vector Address Selection Switches

2-4

for DV11 Data Handling Section

. . . . . . . . . . v v v v v v v

Vector Address Selection Jumpers for DV11 Modem Control Unit

. . . . .

2-6
2-7

DV11 M7807 Module — Device Address Selection Jumpers and Interrupt

Location of Sync Switches on M7839 Module

- Control
Byte Acdress

Control Byte Formats

... ... L.

. . . . .. .. e . e

DV11 Primary Registers

. . . . .

. . . . . ...
.. ..
. . . . . .. ee e e e e e e e e e e e

e e e e

DV11 Secondary Registers . . . . ... ... .. e e e
e e e e e
BISYNC Transmission Flow Diagram
. . ... ... .. e
e
e e
'BISYNC Reception Flow Diagram
. . . . .. e
e e e
e e e e e e e e

DDCMP Transmission Flow Diagram
. . . . . .. ... ... ... ....
DDCMP Reception Flow Diagram . . . . . . J SR
DV11 System Block Diagram

MCU Block Diagram

. . . . .e e e e e e e

e e e
e .

. . . . . ... ...... e e e e

e e ..

Modem Scan Timing Block Diagram

. . . . . ... ... ..e e e e

Microprogram Executive Flow Diagram
Data Reception Flow Diagrtam

Data Transmission
Flow Diagram
Unibus Interface Block Diagram

e e

e e e e e

. . . . .. ... ... ... ....... - 4-10
. . . ..

. .. ... .. .. ....... .

422

e s e e

425

. . . . . . . . . . . ...
.. ... .. -

4-26

Block Diagram of Baud Rate Generator Selection Circuitry for Lines 00—03

. 4-45

Microprocessor Instructions

. . . . . . .. e e s e et

Microinstruction Timing Diagram

4-10

. . . ...
. .. e

. . . . . . .. e . e

ILLUSTRATIONS (Cont)
Figure No.

Title

Page

4-11

Typical UART Clock Selection for Line 03

5-1

Maintenance Mode 01 (Internal Mode) Block Diagram

5-2

Maintenance Mode 11 (Internal Mode for Systems Testing)
Block Diagram (Synchronous)

. . . . . . .. e e

e e e 4-46

. . . . . .. . .. ..

. . . . . . . . o v v v v v v v

e ..

5-3

Maintenance Mode 10 (External Mode) Block Dlagram (Synchronous)

Typical Internal Maintenance Mode Path (Asynchronous)

. . .. ...
. ..

5-5

Typical External Maintenance Mode Path (Asynchronous)

. . . . .. .. ..

5-6

Test Configuration (DV11 Modem Control Unit with H861) Block Diagram

5-7

Test Configuration (DV11 Modem Control Unit, D1str1but10n Panel
and Test Connector) Block Diagram

5-8

. . ..

.. ...

...

.. ....... .

Distribution Panel and Test Connector Jumper Conflguratlon

Test Configuration (ON LINE Modem Loop-Back) Block Diagram

A-l

‘Memory Organization for Maximum Size Using 18 AddressBits

. . . . . . .

“A-2

Memory Organization for Maximum Size Using 16 Address Bits =

. . . . . . .

B-1

PR1472B Programmable Synchronous Recelver (P/SAR)

B-2

. . . . . .

e e e e e e e

B-7

P/SAR
Pin Connections . . . . . . v v 0 v v v e i
e e e e e e e e
Synchronous Timing Example (P/SAR) . .. .' e e e e e e e e e PT1482B Programmable Synchronous Transmltter (P/ SAT)
.........
P/SAT Pin Connections
. .. ..
. .. T
ARe
e e e e
Synchronous Timing Example (P/SAT)
I PV A
Format of Typical Input/Output Serial Character . . . ...
... ... ..

B-8

UART Transmitter, Block Diagram and Simplified Timing Diagram

- UART Receiver, Block Diagram and S1mp11fled T1m1ng D1agram

B-10

UART Signal/Pin Designations

B-11

Block Diagram Dual Baud Rate Generator

B-12

COMS5016 Pin Assignments

B-3

B-4
B-5

B-6

. . . ...
.. .. e

. . . . . . . . ..

e e

... .. ..

. . . . .. .. ... ...... e e e e

C-1

Parallel Data Transfer

Asynchronous Character Format

. . .. . ...

C-3

Synchronous Character Format

. . ... .. ... .. i

Serial
Bit Stream

. . .. ........ T

... ... ... ......

e e

. . . . .T
S

D-1

Longitudinal Redundancy Checking . . . . e
e e
P

D-2

BSC Data Message Format

D-3

Typical Data Exchange Using BSC (BISYNC)

DDCMP Data Message Format

D-5

'DDCMP Sample Handshaking Procedure

. . . . . . . . . . . . v i v i

Pe e e

. . . ..
. . .. N
R
. . . . . . .. .. e e e e e e

‘TABLES
Table No.

Title
Reference Documents

. . . . . .

EIA Electrical Specifications

2-2

Device Address Switches

...... |

e e e e e e

C-2

-1

e e e e e

. . . .. ... e

e e e e e e e I

. . . . .. . .. e
e
e
e e e e .

. . . . .. e e e e e
e e .

TABLES (Cont)

Table No.

Page

Title

2-3

Vector Address Switches for Data Handlrng Section (Vector

Vector Address Jumpers for Modem Control Umt (MCU Vector |

Addresses
are Modulo 10)
Addresses are Modulo4)

. . . .. . . ... .. ... ... e
. .. .. e

e e e e e e e e e

2-5

Synchronous Parameter Selection Switches

3-1

Functions of DV11 Programmable Registers

System Control Register Bit Assighments

e e ..

. . . . . . .. i

e e e

. . . . . .e e e e

e e

. . . . . . . . ... . . .. ...

3-3

Line Control Register Bit Assignments (For Synchronous Lrne Cards)

3-4

Line Control Register Bit Assignments (For Asynchronous Line Cards)

3-5

Receive Function Interrupt Conditions (For Synchronous Line Cards)

3-6

Receive Function Interrupt Conditions (For Asynchronous Line Cards)

3-7

Transmit Function Interrupt Conditions

. . . . . . . . . .. e
e e

3-8

Control Status Register Bit Assignments

. . . . .e e e

Line Status Register Bit Assignments

3-10

Line Protocol Parameters Secondary Register Bit Assignments

3-11

Line State Secondary Register Bit Assignments

Line Progress Secondary Register Bit Assrgnments

3-13

Control Byte Bit Assignments

. . . . . e

3-14

Transparent Data Transmission Control

3-15

Non-Transparent Data Transmission Control

. . . . . .

. . . .. . ... ... ..

3-12

~ Idle Loop Microprogram Listing

e e

. . . . . . . ... .. .. e

e e e

e e e e e

e e e e e e e '

. . . . . e
. . . . . . . ... ... ..

. . . ... . ... ... ... e

Exceptional Character Reception Conditions

e e e

. . . . . . . .. ... ...

Receive Function Interrupt Conditions (For Synchronous Line Cards)

- Receive Function Interrupt Conditions (For Asynchronous Line Cards)
Transmit Function Interrupt Conditions

. . .. . ... .. e e e .

ALUOperations

. . . . . . . . ... .. ... '. e

Set/Clear Codes

. . . . . . . . . . . .

e
e e e e

....e

DV11 Functional Unit-to-Drawing Cross-Reference (Alphabetrcal)
Synchronous Parameter Selection Switches

Coe

. . . . . ... ... e

Static Tests of DV11 Functional Units (DZDVA)

. ... .. e e .

Synchronous Receivers and Transmitters Unit Diagnostic (DZDVB)

. . . ... ... ...

Static Tests of DV11 Functional Units (DZDVF)

. .. .. ... e

System Control Register Maintenance Bits

. . . . . . . . .. e

5-12
5-15

Line Control Register Maintenance Bits (For Synchronous Line Cards)

.. 5-16

Line Control Register Maintenance Bits (For Asynchronous Line Cards)

. 5-18

Control Status Register Maintenance Bits

. . . . . . . ... . ... ...

" Integrated Circuit Modules Used in DV11
-

. . .

Free-Running Microprocessor Diagnostic (DZDVC)

P/SAR Signal Mnemonics

P/SAR Signals

. . . . . . . .t t

. . . . . . . . .

Sync Mode Control Definition

P/SAT Signal Mnemonics
P/SAT Signals

. . . ..

... .. ... ....

e e

e e.

e.
. . . ... .. ... ... e

e e e e .

. . .. ... ... S

. . . . ... ... ......... e e e

SYNC Mode Control Definition

. . . . .e

Xii

.
e e e e e

e e e e ee

v e e e e e

5-18

TABLES (Cont)
‘Table No.

Title

B-8

UART Signal Functions

Dual Baud Rate Generator Address/Frequency Assignments

B-10

Dual Baud Rate Generator Pin Functions

BSC Data Channel Control Codes

. . . . ... ... .. P P

Page

B-20

. . . . . . . .

B-59

. . . . .. ... ... ......

B-60

. . . . . . . . . . . . . . .

.. ... ..

D-5

CHAPTER 1

INTRODUCTION AND GENERAL DESCRIPTION

1.1 PURPOSE AND SCOPE

1.2

This manual is intended to provide maintenance and

MULTIPLEXER

operational programming information for the DV11

The DV11 is a communications multlplexer for the

Communications Multiplexer. The manual cons1sts

PDP-11 family of computers. By means of the DV11,

DVl

COMMUNICATIONS

8 or 16 serial data lines can be multiplexed directly
to

of five chapters plus appendlces

Chapter 1 provides an introduction and overall

PDP-11 core memory for bidirectional data transfer.
The DV11 is intended for use with a PDP-11 program

functional

that provides the rules or protocol which govern the

and

physical

descriptions of the

data transfers and the generation and interpretation

DVI11;

of data link control and character codes.

Chapter 2 contains site preparation, interfacing,
and installation information;

Protocols require processing to (1) monitor trans-

Chapter 3 includes all information necessary for
operation of the DV1l

mitted and received characters in order to 1dent1fy_

via the PDP-11

and respond to control characters, (2) maintain a
“record
of control and data transmission and recep-

program,

Chapter 4 contains a detailed description of
DV11 principles of operation;

tion sequences, and (3) compute the error checking
code (block check calculation) on each character
transmitted or received. The DV11 performs these
functions, thus relieving the processor of this over-

Chapt'er 5 provides information for servicing

head. A Core Memory Control Table, set up by the

the DVI11, including a guide to the diagnostic

PDP-11 program, is used by the DV11 to direct the
processing of received and transmitted characters.
The control table is comprised of control bytes,

software;

Appendices contain reference data, integrated

~circuit

descriptions,

which form a one-to-one correspondence with each

communications

character transmitted or received.

introductory data, and an extensive glossary of
terms and abbreviations.
Chapters 1, 3, and 4 are organized so that reading

1.2.1

them in sequence, will provide a complete picture of

Figure 1-1 is a DV11 overview block diagram, show-

system operation on an optimum study gradient. The

ing the principal functional units, and data and con-

DV11 Overvnew Block Diagram

reader unfamiliar with communication line protocols

trol lines for the DV11. The DVI11 consists of two

should read Appendix D before attempting Chapters

primary functional subsystems, as indicated on the

block diagram: a Modem Control Unit, and a Data

4.
1, 3,and

Handling Section.

Terms» unique
to the DV11 are generally defined at
their first appearance. However, should the reader
encounter a word he does not fully understand, he is
cautioned to reference the glossary provided in the
appendix before proceeding.

The Modem Control Unit mon-

itors and controls operations of the line modems as

directed by the PDP-11 program. The Data Handling

Section sequences and synchronizes transfer of data

~ between the modems and the PDP-11 Unibus (effec-

tively, core memory).

I-1

A MODEM CONTROL
INTERRUPT

MODEM

SET-OP

CONTROL
UNIT
'

MODEMS
1

'DATA HANDLING

DATA LINES

-—‘—— TO
REMOTE
MODEMS

| (16) L 1mE
S
LINE SELECT
MASTER

SCANNER _®'—" RECE;I‘I’)ERS
TRANSMITTERS
(g

STEP

NPR

SYNC & FLAGS

CONTROL [

il"—’ RANDOM
ACCESS "‘"
(19)
MEMORY |

@ &iT9

)

% 12%

RECEIVED

MICRO-

‘

CHARACTER

PROCESSOR

siILo

B <

—

_( )
—8
RECEIVER

lbpecss 10874 K oLt = 156
8 orDS

INTERRUPT

CHARACTER

-8)

()

A
4

\/’

| .

II—28§6

Figure 1-1

1.2.1.1

DVI11 Overview Block Diagram

Handling Section to enable the data transfer between

Estabhshmg the Data Link
- Data transferis

enabled whenever
1.

the selected local modem and core memory.

The serial/parallel interface is accomplished in the

An operator manually initiates a call to a

The receivers assemble

remote modem, or the PDP-11 program

receivers and transmitters.

dials the remote number via the DNI11

characters received from the serial data lines and sgt-a—

Automatic Calling Unit; when the data

Alag each time a character is assembled. The trans-

link is established by the remote modem

mitters disassemble parallel characters for transmis-

answering the call,

Modem

sion on the serial data lines and set a flag each time

- Control Unit signals the PDP-11 program

another character can be accepted for transmission.

the DV1l

via an_interrupt.

The Master Scanner cyclically enables the receivers

In response to a RING signal from a

and

remote modem, the DV11 Modem Con-

transmitters

route

their

flags to

the

Microprocessor.

trol Unit interrupts the PDP-11 program,

The Microprocessor is controlled by a Read-Only

to initiate an exchange of 51gnals that

establishes the data 11nk

Memory (ROM), which handles character transfers

and steps the Master Scanner. Once started by the

1.2.1.2 DVI11 Operation ~ With the data link estab-

PDP-11 program,

lished, the PDP-11 program sets up the DV11 Data

continuously.

1-2

the

Mlcroprocessor‘runs

The Received Character (RC) Silo is a first-in, first-

1.2.2

out storage buffer with a capacity of 128 characters.

Table 1-1 contains a list of pertinent documents, i.e.,

Reference Documents

‘

When a character is received by the DV11 and the

documents covering concepts
and systems peculiar to

RC Silo is empty (usual condition), the character

the DV11, plus documents covering equipment with

propagates to the bottom of the RC Silo. The Micro-

which the DV11 interfaces.

processor then inspects the character code to compute the core memory address of the control byte for
A Non-Processor Request (NPR)

1.3 PHYSICAL DESCRIPTION
The DV11 Communications Multiplexer is housed in

instruction is issued by the Microprocessor to fetch

~a 9-slot, double system unit and includes a separate

that character.

the control byte, which is then interpreted.

rack-mounted distribution panel for each group of
eight modems in a system. Figure 1-2 shows a DV11

In most cases, the control byte will specify character

system for supporting eight lines or modems. Other

~storage, and the character will be transferred from

configurations are discussed in Chapter 2.

the bottom of the RC Silo to core memory via an
NPR transfer. Should the control byte identify the

1.3.1

General Specifications

character as an interrupt character, the character will
be propagated into the Receiver Interrupt Character

Environment

(RIC) register for further attention, and the PDP-11

Temperature: 10° to 50° C

program will be signalled via an interrupt. The RICr-

Humidity: 0 to 90% non-condensing

egister is used to display interrupt characters to the
PDP-11 program, along with the line number and

any error flags.

Processing instructions for the character in the RIC
register are sent to the Microprocessor by the PDP-11
program. The RC Silo continues to accumulate
received characters while waiting for the PDP-11 program to complete its response to the interrupt; however,

inspection

and

storage

any

Power Requirements

A DVII system with 16 synchronous lines:

175A@ +5V
10A@-15V
0.5A@ +15V

A DV11 system with 16 asynchronous‘ lines:

additional

characters from the RC Silo to PDP-11 core memory

205A@ +5V

by the Microprocessor is inhibited. (The Micro-

10A@-15V

processor continues to perform data transmission

0.6

tasks.)

NPR Control is used by the Microprocessor to access

A@ +15V

A DV11 with 8 synchronous and 8 asynchronous lines:

core memory, to store received characters, fetch char-

acters for transmission, and fetch control bytes to

190A @ +5V

direct character processing. Table addresses in core

10A@-15V

memory are stored in the Random Access Memory
(RAM) for character storage and retrieval, and byte

counts for controlling the quantity of data transferred. The RAM also contains registers for controlling protocol functions for each data line.

0.55A @ +15V

)

Character Length

5.6,7,
or 8 bits

;,(.E”m@w

.
N

ifi?.fifi%fig
°°

b@'TL#

fikflbp:

?flbbl

Internal Baud Rates Provided

Character transmission is similar to the reception

Synchronous (via switch settings):

process just described. When the Master Scanner

1200, 2400, 4800, 9600

finds a transmitter flag, the Microprocessor uses
NPR Control to fetch the next character for that line

from core memory, it then uses the character code to -

compute the address of the corresponding control

‘byte, and does an NPR to fetch the control byte. The

Microprocessor responds as directed by the control
byte and then loads the character into the transmitter
for transmission.

Asynchronous (via PDP-11 program).
- 50, 75, 110, 134.5, 150, 300, 600, 1200,

1800, 2000, 2400, 3600, 4800, 7200, 9600,
|
|

38,400

Opérating Modes

Full- or Half-Duplex

Table 1-1
Reference Documents

' Title

Number

Description

90P262 (112-00973-290B)

Discussion of overall system, addressing modes,

GENERAL

PDP-11 Peripherals
Handbook

and basic instruction set from a programming

point of view. Some interface and installation
data.
PDP-11 Instruction

- 19P741

Pocket-size list of instructions. List group names,

List

functions, codes, and bit assignments. Includes

ASCII codes and the bootstrap loader.

Logic Handbook

Presents functions and specifications of the M-

C-105

Series logic modules and accessories used in PDP-11

interfacing. Includes other types of logic produced

by DEC but not used with the PDP-11.
Introduction to Mini-

- 6802-11274-4582

computer Networks

ES-09-45

Binary Synchronous

IBM SRL GN27-3058

Principles of computer-based data communications

technology.

Introduction to IBM’s Binary Syfichronous Com-

Communications

munications Protocol (BISYNC or BSC).

A Message-Oriented

Introduction to DEC’s Digital Data Communication

DEC, 1973 (Wecker)

Message Protocol (DDCMP).

Protocol for Inter-

processor Communi-

cation

Data Set 201A and

Description of interface leads in synchronous

PUB 41201 *

modems.

201B Intgrface

Specifications
Data Set 201C

PUB 41210%

Interface Specification

PUB 41209*

Interface Specification

PUB 41211*%

Interface Specification

DEC-11-GGPA-D

Detailed discussion of the PDP-11 software system

Interface

Specification

Data Set 208A
Interface

Specification
Data Set 208B

Interface
Specification
SOFTWARE

Paper-Tape Software

Programming

used to load, dump, edit, assemble, and debug

~ PDP-11 programs. Also included is a discussion of
input/output programming and the floating-point

Handbook

and math package.

*May be obtained from AT&T Co., Supervisor, Information Distribution Center, 195 Broadway, Room 208, N.Y.C.,N.Y. 10007
($1.50 each).

-4

(

741413

Figure 1-2

Parity Generation and Detection

Odd, Even, or None

DVI11 Communications Multiplexer

F 54m €

Sync Character Facility

5wiT¢ Hw,,r- kLo

asunt

22 g

on the basis of the receipt of either one sync

Modems Accommodated

character or two consecutive, identical sync

Synchronous modems (Bell System 201, 208,
209, or equivalent)

characters. For each 4-line group, two sync
codes may be manually preset in switches. The

Asynchronous modems (Bell System 202 series,

sync codes for use on a selected line.

PDP-11 program may select either of those two

103 series or equivalent)
A

Synchronization of a line can be selected to be

Bus Loading'
Two PDP-11 Unibus Loads

‘Sincethe:DN¥alsrequites:
Pl

er, only
AT

three DV11s can be placed on a typlcal 21-in. expander

Protocols Implemented

box. Expander boxes usually contain three H744 Tegu-

- The DV11 specifically implements (but is not

lators, each of Wthh has a capacnty of 25 A At

limited to) Digital’s DDCMP and IBM’s BISYNC protocols.

'zTherefore,three

Maximum Throyghput

DVllsis the maximum for one expander box.

- 38,400 characters/second
Ixlb x A60°

1-5

D& enooTe

ce DoPLEr
me€ | Fo
Sa
No Pamto
e
CARD

S Te €S

Kg_e?wké' |

'A
22E ~— S1~C
Py
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Bex - 54mc B

CHAPTER 2

"IN STALLATION

This chapter provides information for interfacing,
installing, and testing the DV11 Communications

2.1.2
Compatibility Considerations and Precautions
The DV11 with synchronous line cards is directly
compatible with Bell synchronous modems 201, 208,

lation, customlzlng, and checkout procedures are dis-

asynchronous modems 202 series, 103 series or equiv-

Multiplexer. Interfacing considerations are discussed
in Section 2.1, Site Preparation and Planning. Instalcussedin Sections 2.2 through 2.7.

2.1
2.1.1

209, or equivalent. It is also compatible with Bell

alent when asynchronous
line cards are used. The
DVI11 provides internaal clock rates of 1200, 2400,
4800, and 9600 baud at 0.005% accuracy for synchro-

SITE PREPARATION AND PLANNING

nous operation; modems operating at other rates

Minimum Through Maximum Configurations

must supply their own clock signals. It is recommend-

The DV11

provides multiplexing caapability to PDP11 core memory for up to 16 modems. The DV11 is

ed that modem-supplied clocklng be used where
available.

housed in a nine-slot, double system unit and includes

one rack-mounted distribution panel for each
group of eight modemsin a system. Five of the nine

The DV11 is compatible with all members of the

slots are occupied by functions requiredin any sys-

PDP-11 family of computers. PDP-11 standard software address allocations provide for the implementa-

tem configuration. The remaining four slots are occupied by four hex-printed circuit board
(M 7839
s or
M7833), designated as the line cards. Each line card is

tion of as many as four DVI11s in a PDP-11 system.
DV11 throughput rate, however, forms a more severe
limitation on the number of DVI1ls in a system, as

capable of supporting data transfers to and from four

modems. The M7839 line card supports synchronous
data transfers while the M7833 supports asynchro-

will now be demonstrated.

nous data transfers (these line cards contain the
receivers and transmitters).

The

5-module

unit

common

all

DV1l

A single DV11 multiplexing 16 modems at 9600
baud, each in full duplex mode, is capable of transfer-

con-

figurations is designated the DV11-AA. Two of the
M7839 module, plus one distribution panel and asso-

ring 38,400 8-bit characters per second (1200 characters per line X 16 lines X 2 directions). Although this

ciated cables, form an eight line synchronous unit
designated the DV11-BA. An eight line asynchronous

is well within the capabilities of the DV11, on the
average, the PDP-11 is provided with only 26 us to

unit, the DVI11-BB, is generated by replacing the
M7839 modules in the DV11-BA unit with two
M7833 modules. Similarly, a mixture of one of each

handle each character. Although most characters are
handled by NPR transfers, program and protocol
efficiencies still need to be relatively high to maintain

line card forms a synchronous/asynchronous unit
designated the DV11-BC. The minimum DVI1 sys-

this rate; this would be for a single DV11. Some
76,800 NPR c/s would be required, or about 10 per-

tem configuration consists of one DV11-AA unit plus
one line card option, DV11-BA, DV11-BB or DV11-

cent of Unibus capacity. With all lines operatedin
DDCMP mode (control byte fetch inhibited), 38,400

BC; a maximum configuration consists of one DV11- AA unit plus two line card options.

NPR c¢/s would be requ1red or about 5 percent of

Unibus capacity.

2-1

v’DVlls should be connected ahead of all Massbus

devices on the Unibus and behind unbuffered NPR
devices such as RKO05s. DVI1ls have placement
requirements similar to those for DQIl1s. If both
DQlIs and DVlls are used place the umts w1th the

The devices are assigned in order by type:
DC11; KL11/DL11-A, -B; DP11; DM11A: DN11; DM11-BB; DR11-A; DR11-C;
PA611 Reader; PA611 Punch; DT11;
DX11; DL11-C, -D, -E; DJ11; DH11;
GT40; LPS11; VT20; DQI11; KWI11-W;
DU11; DUPI1; DVI1l Data Handling

Section ADV11-Moedem-Contol-Unit.

TwoDVlIscan be used on a PDP-11/40,

Two DVllscan be used on a PDP—11/70

PDP-11/45, or PDP-ll/SO with no disks.

vacancies.

with no Unibus d1sks

with 2400 baud rate lines can use four DVI1l1s.) A
maximum of four DV11s can be placed on any sys-

tem because of address space limitations; the limita-

tions are based on NPR access. Interrupt
performance depends on the operatmg system pro-

upward.)

tocol, and buffer lengths.

2.1.3 Interface Specifications and Signals |

Each device interrupt vector requires four address
locations (two words). A further constraint is that all
vector addresses must end in 0 or 4. The vector
address is specified as a three-digit, binary-coded
octal number using Unibus data bits 0-8. Because the
vector must end in 0 or 4, bits 1" and 0 are not specified (they are always 0) and bit 2 determines the least
s1gn1f1cant octal digit of the Vector address (O or 4).

The DVI11 presents two unit loads to the PDP-11
Unibus and also provides modem control and data
leads compatible with EIA RS-232-C and CCITTV24 specrf1cat1ons EIA RS-232-C electrical spec1f1cations are listedin Table 2-1.

2.1.4 Interrupt Priorities and Address Assignments
Interrupt Priorities - The DV11

uses three |

interrupt vector addresses. Interrupt priorities for the
Data Handling Section are selectable by means of a
priority plug on the M7837 module. The priority plug
is preset to select BRS priority; it may be changed to

select BR6 priority, but the diagnostic programs
expect BR5. The Modem Control Unit is permanently wired to BR4 priority.

2. 1 4 3 | Address Ass1gnments The DVll1s ass1gned

| ij%A‘fs*fiarein
2.1.5

Environment

‘The DV11 will operate in temperature env1ronment
- from 10° to 50° C with a relative humidity up to 90%,

non-condensing. Power requirements are as follows:

2. 1‘ 4.2 Interrupt Vector Address Assignment Com-

munications devices are assigned floatmg interrupt

Current |

Voltage

(Amperes)

vector addresses as follows

If additional devices are to be added to the

system, they must be assigned con-

tiguously after the original devices of the
same type. Reassignment of other type
devices already in the system may be
required. (For example, the vector for
another DV11 would be after the existing
DVI11, but addition of a DC11 would
cause all other vector addresses to move

For lower speed lines, the maximum number can be
increased proportionally. (Example: a PDP-11/40

2.1.4.1

If any type device is not used in a system,
vector assignments move down to fill the

+5
-15

The vector space starts at location 300 and

+15

proceeds upward to 776.

2-2

21
1
0.5

EIA Electrical Specifications

Driver output logic levels with 3K to

15V>,>5V

7K load

SV>

Driver output voltage with open cir-

IV <25V

>-15V

cuit

Driver output impedance with poWer

20 > 300'ohms

off

‘Output short circuit current

1,/ <0.5 A

Driver slew rate

- Receiver input impedance

TKQ> R, > 3KQ

Receiver input voltage

Receiver output with open c1rcu1t

<30 Vus

15 V compatible with driver
- Mark

mput

Space |

Receiver output with +3 V input

Receiver output with -3 V input

T
NN

SANNNVNNNN

Mark

LOGIC “0”= SPACE — CONTROL ON
Noise margin
‘Transition region
Noise margin

L LTI

LOGIC “1”=MARK
= CONTROL OFF

2.2

UNPACKING AND INSPECTION

2.3 INSTALLATION OF BASIC ASSEMBLIES
Drawing D-UA-DV11-0-0 shows the physical

After unpacking, check that the following parts are

arrangement of the wired backplane, distribution

‘present for the basic DV11-AA unit:

- panel(s) and cablesin a typical installation. Figure 2-

MEU

1 is the DVI11 interconnection schematic. Install the

1 D-AD-7010834-0-0 Logic Assembly

9-slot, double system unit in the expander box or
processor box as space and power are available. Withpower off, test the resistances between all pins of the
power harness Mate-N-Lok connector. Only pins of
the same wire color should be connected. Secure the
~ground wire to one of the mounting screws. Plug in

{1 M7807 Bus Control and Mux Board
1 M7808 Modem Control Scan and Mux Board

fi‘« /)&95; | {1 M 7837 Unibus Data and NPR Control Board
|

"1 M7836 ALU and Transfer Bus Board

1 M7838 ROM, RAM, and Branch Board
1 M920 Umbus Connector

the Mate-N-Lok connector of the power harness.
Apply power and check for proper voltages on the
logic pins (not the cable) as follows:

Also check that the following parts are present for
eachline card option orderéd:

Voltage

+5+ 025V

ClA2

-15+£0.75V

C1B2

- ClU1

+15+£0.75V

2 H8612 Line Card Test Connectors

1 H317C Distribution Panel

This will ensure that the cable and the Mate-N-Lok

4 BCO8R-15 Cables

connector were correctly installed. Turn power off.
~ (Note that-the: DV11 is'not yet connected to the
Unibus, nor-are any modules installed.)

1 H325 Test Connector |

DVI11-BA: 2 M7839 Sync Mux Line Card

DV11-BB: 2 M7833 Async Mux Line Car‘d'

Install the distribution panel(s) as indicated in Figure

2-1. Refer to Figure 5-8 for the proper jumper con-

figuration of the distribution panel. To install an addon DV11, see Paragraph 2.4.4.

DVI11-BC: 1 M7839 Sync Mux Line Card; 1
M7833 Async Mux Line Card

OUTPUT

CABLES

ARE BCOS5D-25
[

T 8 OUTPUT CABLEST
H317C

DISTRIBUTION

PANEL

J10

[f\\

J12

\_J

J11

(FIRST 8 LINES)

LINE CARD SLOT 5

M7808 Ji

LINE CARD SLOT 6

m7808

BCOSR

CABLES

PDP11 PROCESSOR BOX
OR

BA11 EXPANDER

BOX THAT CONTROL

THE DV.11

CONTROL

LOGIC WIRED

ASSY

D-AD-7010834

4 BCOBR

H317C

DISTRIBUTION

PANEL

(SECOND 8 LINES)

J10

J11

J12

CABLES

LINE CARD SLOT 7

]

LINE CARD SLOT

[

\\//

M7807

J J

AC POWER CORD
TO LINEOR PDP-11

NOTE:
Install all

BCO8BR cables with smooth

side toward you and ribbed side toward
circuit board.
11-2930

Figure 2-1

DV11 Interconnection Diagram
2-4

2.3.1

Unibus Cable Interconnections

‘DVI11.

The DVI1 is shipped with one M920 Unibus Connector (placed in slot
9 as shown in the module utili-

zation program, Figure 2-2), which provides for
~ electrically

connecting

the

unit

the

PDP-11

Two Unibus addresses (also called device

addresses) and two interrupt vector addresses are
prov1ded on theDVll as follows
|
|
1.

DVII Data Handling Section address,

is to be electrically placed in mid-bus (i.e., somewhere

DVII MCU address,

Unibus), the M920 from the next higher device

‘Unibus. For processor box installation where the unit

between the first and last devices on the PDP-11

(closer to the processor) on the bus is plugged into
slot 1 of the DVI1, and the M920 in slot 9 of the
DVI11 is plugged into slot 1 of the next lower device

on the bus.

.For an end-of-bus installation of the DV11, proceed
as follows:

Remove the M930 Unibus Terminator

device.
2.

Remove the M920 from slot 9 of the
DVI11 and place in slot 1 of the DV11.

Install the M930 (removédlin step 1) in

slot 9 of the DV11.

Unibus interconnections are fnade via BC11-A cables

where the DV11 is installed in expander box or is
- physically the first or last unit in any box. Cable
~ requirements in these cases are as described in Figure

2-2.

MODULE

CUSTOMIZING

DVl 1 MCU interrupt vector address. o

Because the DV11 has ten registers directly addressable by the PDP-11 program, it must be assigned a

INSTALLA TION

AND

as described in Paragraphs 2.4.1 and 2.4.2 before
installing modules

Unibus

and lnterrupt

DVlils in a

addresses.

system

should

have

consecut1ve

| _TheUnibus addresses for the DV11 Data Section are
controlled by a rocker DIP switch package, located

on module M7836, and byjumper straps on module
M7807 for the DV11 MCU. (Locations of all address

selection switches andjumpers are shownin Figures
2-3 through 2-5.) The position of these switches determines bits 03-12 of the Unibus address. If a rocker
switch is set to ON or a jumper on the M7807 board
is in, an address bit of zero in the corresponding bit

position serves to address the DV11 Data Handling
Section. DEC standard software requires that the

DVI11 address be set as specified in Paragraph 2.1.4.
Switch settmgs for device address selection are shown_

Figure 2-2 is the module utilization diagram. Set the
address assignment and parameter selection switches

2. 4 1

Data Handling Section interrupt

Unibus address that is a multiple of 32 (octal 40). All

from the last slot of the current end-of-bus

2.4

DVI1

vector address,

Vector

Address

- Assignments

The Unibus and interrupt vector addresses for the

DVI1 must be set manually before operating the

~in' Table 2-2.

The interrupt vector address for the Data Handling

Section is controlled by a DIP switch package on the
M7837 module, which selects vector address bits
08-03. The switches should be set to select vector

addresses between 300 and 776. Switch settings for
interrupt vector address selection for the Data Han- dling Section are shownin Table 2-3. Vector address
selection for the Modem Control Unit is done by
jumpers on the M7807 module (Table 2-4).

Y7
4

A s vasl
;

ymwif
| E?YAjgzéqfi
:
.

A B
.

6 ¢

53
TALx1F

=113 5q

ALU
AND
TRANSFER
BUS

UNIBUS
DATA
AND
NPR

CONTROL

DEY

wie T

47D

40D

ROM
RAM
AND

51|
M7839/

BRANCH

MUX
LINE
CARD

LINES
0-3

—

gl
., M7833

CABLE
UNIBUS
CONNECTOR
NOTE 3

B O =1 x7829
(

QU
T

M7839/

M783 9/

M7 839/

M7833

M920
CABLE

MU X
LINE
CARD

UNIBUS
CONNECTOR
NOTE 1

LINES

Lines | NOTE 2

M7833

LINES
4-7

M7833

8-11

12-15

BUS

MODEM

AND
MUX

MUX

CONTROL

CONTROL
|

SCAN
AND

VIEW FROM WIRING SIDE

NOTES:
1. If end of bus replace M920 with M930.

2.If last unit in basic box replace M920 with BC11A cable

end when expanding to pheripheral box.
3.If first unit in expander box replace M920 with BC11A cable end.
11-2932

Figure 2-2 Module Utilization Diagram
- 2-6

7414-10

A12

A11

A10

A09
A08
ON=0
AO7

OFF =1

A06

A05

A04
UNUSED

7414-3

Figure 2-3

DVII1 M7836 Module - Device Address Selection Switches

2-7

RN R

iSRR

eTy O Ay

7414 7

D08

D 07

UNUSED
D 04

D 03

ON
OFF

7414- 1

Figure 2-4

DVI11 M7837 Module - Interrupt Vector Address Selection Switches

for DV11 Data Handling Section

2-8

DEVICE ADDRESS

(A0O3 — A12)

W18

w12

W17

w13

W16

Jumper

Bit

A12

A09

W10

A08 -

w11

A10 —

w12

A04

w13

A05 -

W14

A11

w15

A03 -

W16

A06 -

W17

A07 -

Jumper in=0

W10

W11

INTERRUPT VECTOR

ADDRESS

(D02 — DO8)
Jumper

Bit

D08

D02

D03

D06 -

D07 .

Wé6

D05

D04

W15

W14

o oty

-«

Jumper In =1

7414-11

Figure 2-5

DVI11 M7807 Module - Device Address Selection Jumpers
and Interrupt Vector Address Selection Jumpers

for DV11 Modem Control Unit

-a[npour 9¢g/J U0 papiaoid SI YoIMS € 31q ON “AJuo L08LIN 03 sofidde uorosfes ¢ My

2-10

Table 2-3

Vector Address Switches for Data Handling Section
(Vector Addresses are Modulo 10)

M7837 Switch |
Address Bit

5 | 6 | Vector

DOS

| DO7

| D06 | DO5S | D04 |

DO3 | Address

300
310

320

330

340
350

1360

370

X |

400
410

420

430
X

440

450

\'\

460
470

]

X
X

X
|

500

510

520

530
540

550
X

560
570
etc. to

770

VNotes:

_1.
2.

" X means switch ON
Set only the switches shown.

Vector Address Bit D02is controlled by DV11 logic dependent on

whether a Receiver Interrupt (Bit D02= 0 = Vector A) or a

Transmitter Interrupt (Bit D02 = 1 = Vector B) is being requested.

2-11

Table 2-4

Vector Address Jumpers for Modem Control Unit
(MCU Vector Addresses are Modulo 4)
M7807 Jumper

Address Bit

| Wi1*

| W5

| W4

D0OS

| DO7

| D06 | DO5

| We

| W7

| w3

| w2

Vector

| DO4 | D03 | D02 | Address

- X

300
304

310
314

320
324

330
334

X
|

340

344
X

350
354

360
364

370

374

| X

| x

400
404

410

414
X

420
424

430
|

434

440
444

450
454

460

464

470
474

2-12

500

504

Table 2-4 (Cont)
Vector Address Jumpers for Modem Control Unit

fta

(MCU Vector Addresse
are
s Modulo 4)

M7807 Jumper | WI¥ | WS

| wa

Address Bit

| DO6

DOS

| DO7

We
| DOS

| w3 | w2

| X

Vector

| DO4 | D03 | D02 | Address
X

510

514

520

524
X

530

534

544

550
554

540

1560
564

570
574
etc.
to

774
Notes:

X means jumper OUT

Cut only thejjumpers shown.

3.
-

*Jumper Wiisin for the PDP-11 /20 w1th the KHll and for the PDP- 11/40
PDP-11/45, and newer PDP- lls

2.4.2

Synchronous Parameter Selection
Rocker DIP switches are located on each M7839
module for selection of the followmg synchronous

data channel parameters
1.

Internal baud

Sync character codes

Switch settings for each synchronous parameter are

listedin Table 2-5. Switch locatlons are shownin Figure 2-6.

rate

(1200

2400,

4800,

- 9600)

Full/half duplex
Parity (odd/even/none)

Whenever possible, the“parameters should be con-

Character length (5, 6, 7, or 8 bits)

duplex

figured per customer requirements at this time. If half-

or parlty

operatlon

requlred

thli?:‘t.

Sync requirement (whether one sync char-

acter or two consecutive, identical sync

irl;gn DV11 dlagnostlcs don’t support half-duplex or

parity operatlon SyNc A' = 226, 590 C ‘B g6

characters are required to achieve line
synchronization).

2-13

b CQ

22<

SWITCH PACK 4

SWITCH PACK 3

Sync Character A

Sync Character B

2 w,%;x;:.-.;'

oM zPRITY
oN = 2PD trary

2
SWITCH PACK
’
Baud rate and
Duplex Select

oN [ove g
FOX HDx
Py
o0 ’ SR=

28
Jotd

SWITCH PACK 1
Parity, Character
_
__length, and number
kIAE
No

of syncs

OF F= Sy

—

& T D 8gat.

Figure 2-6 Location of Sync Switches on M7839 Module
2-14

)

Table 2-5
- Synchronous Parameter Selection Switches

Switch
Function

Parameter

Name

Pack

Number

Select B

Select A

Select B

SelectA

OFF

Select B

OFF

Select A

9600 Baud

Select B
Select A

S2
S2

3
4

OFF
OFF

Full Duplex*

HD3

_ geT o P~

HD2

HD]

HDO

HD3

OFF

HD?2

'OFF

HD1

OFF

HDO

OFF

Even Parity

ON |

" OFF

7 Bits/Char

WLS1
WLS?2

S1
S1
S1

4
3
4

OFF
ON
OFF

6 Bits/Char

WLSI1

OFF

WLS2

5 Bits/Char

WLSI

WLS2

)

OFF

Internal Baud

Rate

1200 Baud

|
2400 Baud

4800 Baud

* Full/Half
Duplex

ifpg pEID
|

Half Duplex

Parity

No Parity*

- 0dd Parity

Character

Length
(Excluding
Parity)

SYNC

Requirement

8 Bits/Char

1 SYNC REQ.

1 SYNC 00/

o oM

1 SYNC 01

1 SYNC 03

g e

lpane

*Must be selected to run diagnostics DZDVA to DZDVE.

1 SYNC 02

DEFAacLT

2-15

S YWDCATLA16

stue G T OGL

Setting

OFF

OFF
OFF

Table 2-5 (Cont)
Synchronous Parameter Selection Switches
,

Switch

Function

Sync Req. (cont) |

Parameter

2 SYNC REQ.

Pack

Number

1 SYNC 00

"ON

(As required

OFF=Logi-

cal one)

(As required

OFF=Logi-

cal one)

1 SYNC 01

1 SYNC 02
|

Sync Character

1 SYNC 03

Desired Code

Name

Sync A

Codes

|
Desired Code

Sync B

Setting

Line synchronization can be selected by the receipt of

2.4.4

either one sync character or two consecutive, identi-

Proceed as follows to install an add-on DV11:

Installation of Add-On DV11

cal sync characters. For each 4-line group, two sync
codes (Sync A or Sync B) may be manually preset in

the Sync Character Code switches. The PDP-11 program may select either of these two sync codes for use

on a selected line.

Install the wired b.ackpla'ne assembly in

the mounting box.

Internal baud rate is determined by the ON/OFF
states of the Select A and Select B switches. This is

Measure the resistance between pins of
the power harness (see first paragraph of

Section 2.3).

applicable only when the modem does not supply

clocking.

Plugin the Mate- N-Lok connector of the

power harness.
2.4.3

Resistance Checks

Measure the resistance between the following pins on

the backplane with the white plug of the 7010835

logic pins (Paragrah 2.3).

cable hanging free (not plugged in), and with all modules plugged in:

+5 V to GND must be 0.5 Q or greater

Apply power and measure voltages at the

- 6.

=15V to GND must be 50 Q or greater

Turn power off.

Set all address, parameter switches (Paragraphs 2.4.1 and 2.4.2) and distribution

+15 V to GND must be 10 Q or greater

panel jumpers (Figure 5-8).

If the resistance is less than the lower limit indicated,

Install modules (Figure 2-2).

Unplug the power harness.

low limit listed. If the above resistances are correct,

Do resistance checks (Paragraph 2.4.3). | |

DV11-0-0.

10.

Apply power.

check for a short. If the resistance exceeds five times
the low limit, it may indicate an open circuit. Make

each measurement ¢wice, once for each polarity of the
meter. The lowest reading must not be less than the

connect the white plug in accordance with D-UA- |

2-16

2.5

SYSTEM CHECKOUT
|
Turn on the power. Toggle in the Bootstrap and load

the Absolute Loader (if not already done). The
addresses and contents of the Bootstrap Loader are
listed below.

Memory size

Address

Contents

744

016 701

——-T746

000 026

determines the

——Equals:

——-750

012 702

017 for4K

-—==752

000 352

037 for 8K

——754

005 211

- 057 for 12K

-—756

105711

077 for 16K

——-760

100 376

117 for 20K

——-762

116 162

137 for 24K~

-—-764

000 002

157 for 28K

———766

———400

---770

005 267

772

177756

——-T774

000 765

first 3 digits:

——-776

177 560

(TTY Reader)

or
177 550

(High speed
reader)
Place Absolute Loader (MAINDEC-11-LZPA-PO)

in the reader, load and start at address ——744. Place
the diagnostic tape in the reader, load and start att
address ——-500. Load and run the DV11 diagnostics
as specified in Chapter 5 to verify system operation.

If half-duplex or parity operation is desired, configure the M7839s accordingly (Table 2-5).

2-17

CHAPTER 3
PROGRAMMING

This chapter contains
all information required for

- determine and respond to requirements for auxiliary

controlling operation of the DV11 Communications

Multiplexer

means

of the

PDP-11

protocol processing (i.e., block check calculations,

data block terminations, control character handling).

program.

(Chapter 1 should be read prior to this chapter.) The
reader should also be familiar with synchronouspro-

The PDP-11 program directs DV11 activities through

tocols as discussedin Appendix D. Chapter contents

the programmable registers of the DV11, along with
a control table set up in core memory for reference by

are arranged as follows:

the DV11.
1.

Programmable Facilities and Functions:

The programmable registers, core memory table references, and functions of the

3.1.1

DV11 are discussed (Section 3.1).

The DV11 programmable registers cons1st of the
“primary”’

Complete, detailed descriptions of ‘pro-

which

are

directly

after first loading a primary register. (The primary

~ register selects the secondary register to be accessed.)
The directly-addressable registers provide for modem

Procedures for DV11 1n1t1ahzat10n (Section 3.5).

registers,

ters, which may be accessed by the PDP-11 program

(Sectlons 3.2, 3 3, 3.4).

system

addressable via the Unibus, plus “secondary” regis-

grammable registers and control bytes

Programmable Registers

setup and control, data transfer enabling, interrupt

enabling and reporting, extended memory address-

Methods for controlling data transfers

ing, and access
to secondary registers. The secondary

and implementing protocols (Section 3.6).

registers provide for protocol processmg and data
transfer control.

Section 3.1 describes DV11 functions in sufficient
detail to enable the reader to omit a detailed study of

Ten

the comprehensive reference datain Sections 3.2, 3.3,

There are 16 secondary registers provided for each of

and 3.4, and to proceed directly to the procedural |

the 16 multiplexed data channels, for a total of 256
-

AND

FUNCTIONS
The

DVI11

registers

are

provided.

secondary registers. The secondary registers make up

datain Sections 3.5 and 3.6.
3.1 PROGRAMMABLE FACILITIES

directly-addressable

a separate Random Access Memory (RAM) within
the DV11. Secondary registers store functions. that
may vary from line to line, and that require the exten-

core

memory to- synchro-

sive storage capacity of the RAM.

nous,/asynchronous data line multiplexer with special

features to facilitate processing of a wide variety of

Functions of programmable registers are described in

communication protocols. Under the overall direc-

Paragraphs 3.2 and 3.3, following a discussion of the

tion of the PDP-11 program, the DV11 sets up the
data line modems, stores and retrieves data from core

table references for programmable registers are listed

memory, monitors
and reports error conditions, and

in Table 3-1, which is provided for reference during

examines each transmitted or received character to

study of Paragraphs 3.1.3 and 3.1.4.

control table. Functions, functional categories, and

3-1

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3-2

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3-3

3.1.2

The mode field occupies bits 8, 9, and 10 and is
appended to the basic control table address to form
the actual address of the control byte. Thus, in the
example above, the control bytes for character code
101 would be in location 4101 (mode 0), location
4501 (mode 1), location 5101 (mode 2), etc. The control byte address formation sequence is graphically
depicted in Flgure 3-1. Control byte formats are

Control Table

The control table contains the control bytes fetched
from core memory by the DV11 each time a character
is received or is to be transmitted. The control bytes
are used by the DVI11 to control processing of the
transmitted or received character.
3.1.2.1 Control Table Format — The addresses in
core memory for each line of the receiver
and trans-

shown in Flgure 3-2.

mitter control tables are set in secondary registers by
the PDP-11 program. The DV11 adds the character
code to the base address to form the basic core memory address of the control byte for that character. For
example, if the base address of the receiver control

- 3.1.2.2 Receive Control Byte - Whenever a charac-

ter is input to the DV11 from the data link receiver,
the associated control byte is obtained from core

table for a given line is 4000 and the character 101

code is received (ASCII letter A), 4101 would be
effective core memory address of the associated con-

memory by a Non-Processor Request (NPR) to specify the next mode and to dictate character disposition. The following character dispositions are

trol byte.

provided:

With this scheme, 256 locations (2s) are sufficient to

provide control bytes for every possible 8-bit character code. In the usual protocol, however, certain
codes are susceptible to more than one mode of interpretation, depending upon the sequence in which
they are received and whether the datais transparent
or non-transparent. Thus, 3-bit mode specification
fields are providedin secondary registers for each line
in the transmitter and receiver functions. Sequencing
between modes may be effected by the control byte,
which specifies the mode in which the DV11 is to
operate

Generate (or do nct gener'ate) an

Store (or discard) the character.

Accumulate (cr do not acCumulate)tthe

interrupt.

character in the Block Check Character
(BCC).

Expect the BCC (treat the next character
as a BCO).

Binary

Parameter

EXTENDED
ADDRESS
B ITS

.ADDRESS

Table Base Address

L__H STeTe o

Resultant

Address of
Control Byte

Shifted)

O‘[-OTO I 0o

-l

Figure 3-1

06. 05

[o]efofofefe]e |°-l °]

Character Code

Mode No.

Control Byte Address

INCLUDE
CHAR. IN BCC

SEND BCC

—

SEND DLE

NEXT MODE
TM

" x | - TRANSMIT CONTROL BYTE

X
07

X
\

NEXT MODE
—

)

X=NOT USED

DISCARD/STORE|

RECEIVE

~ EXPECT

CONTROL BYTE

|
INTERRUPT
PROGRAM

INCLUDE CHAR
IN BCC
I1-2682

Figure 3-2

Control Byte Formats

The interrupt disposition provides for signalling the
program in the event of error conditions, or data link
control characters requiring special handling. The
character that caused the interrupt is loaded into the
RIC register. The program responds by sending a

special control byte to the DV11, which would then

override the previous dispositions set for received
characters. The discard disposition provides for
inhibiting storage of data link control and other
unwanted characters. The do-not-accumulate disposition provides for the exclusion of non-data; BCC
anticipation signals characters from the error-checking process. BCC anticipation signals the DV11 to
initiate data block termmatron procedure.
3.1. 2 3 Transmit Control Byte Whenever a charac“ter is input to the DV11 from PDP-11 core memory,
the associated control byte is obtained from core
memory by a NPR to specify the next mode and any
other processing instructions. The followmg 1nstructions are provided:

Accumulate (or do not accumulate) the
character in the BCC.

Send the BCC after the character.

Send the DLE before the character.

As in the case of the receive control byte, the do-notaccumulate disposition provides for the exclusion of
non-data characters from the error-checking process.
- The BCC transmission command signals the DV11 to
initiate data block termination procedure. The DLE

transmission command causes the DV11 to retrieve
the DLE character from secondary register storage
and “stuffs” the DLEin front of the character to be
transmitted.

3.1.2.4

Control Byte Symmetry - The receive and

transmit control bytes are configured so that a single
control table will provide for both transmit and
receive functions for a given line if the following functlonal llmltatlons are observed

The protocol must progress from mode to

mode in a symmetrical fashion for both
transmit and receive;

the same characters must be included in
the BCC for both transmit and receive.

For protocols that do not meet these requlrements
separate control tables may be used
|
|

3.1.3 Operatlons With Dlrectly-Addressable
o
Registers
The directly-addressable registers provide for modem
‘setup and control data transfer enabling, interrupt
enabling and reporting, extended-memory addressing
and access to secondary registers (see Table 3-1).

3.1.3.1 Modem Setup and Control - Modem
enabling, monitoring, and control are provided by
the Control Status Register (CSR) and the Line Status Register (LSR) of the Modem Control Unit. Stepby-step procedures for accomplishing these functions
are contained in Paragraphs 3.5 and 3.6.

the character in the RIC register and resume with-

“drawing characters from the RC Silo.

for PDP-11 program access to the secondary registers
in the DV11 RAM. To address a secondary register,

3.1.3.5

the PDP-11 program sets the 8-bit RAM address,

is to access a core memory tables at extended memory

consisting of the 4-bit line number, plus the 4-bit register selection code, in SRS 00-03 and SRS 08-11,

Extended Memory Addressing — If the DV11

locations, the basic 16-bit table address is set in the
appropriate secondary register. The extended address

respectively. Loading or reading the SRS is then

bits are the set in SCR 04, 05. The DV11 appends the

accomplished by loading or reading the Secondary

- extended address bits to the 16-bit table address and

stores the resultant 18-bit in the SRS (the RAM is 18

SRS must be saved by interrupt service routines.

‘bits wide).

LCR bits 04, 05 display the extended memory address

3.1.3.3 Data Transfer Enabling - The System Control Register (SCR) provides for clearing the Data

bits for the secondary register selected by the SRS,

Handling Section (SCR 11) and starting the Micro-

for reading by the PDP-11 program.

processor (SCR 00) to enable the Data Handling Sec-

3.1.4

tion. Individual receivers are then enabled by setting

the line number in bits 00-03 of the SRS, then setting

Protocol Processing

~ Processing and

control

of protocol

functions

Receiver Enable in Line Control Register (LCR bit

accomplished almost exclusively with secondary reg-

13), coincident with the Control Strobe (LCR 15).

1sters as indicatedin Table 3-1.

Individual transmitters are enabled by setting Transmitter

3. 14 1 BCC Polynomlal Selectlons The code set in

(bit 02) in the Line State Secondary

| Reglster

bits 03, 04 of the Line Protocol ParametersSecond-

ary Register selects the type of block check poly-

3.1.3.4

nomial to be applied to the transmitted and received

Interrupt Enabling and Response - Data

Handling Section interrupts may occur

data for error-checking purposes. Longitudinal redu-

as a result of

ndancy

checks (LRC), cyclic

redundancy checks

receive function interrupt conditions or transmit func-

(CRC-16), and CRC/CCITT checks are prov1ded*

tion interrupt conditions. Receive function interrupts.

for.

occur as a result of error conditions, encounter
of

3142 Processing Bl,o_c”k Terminations - Mode

data block boundaries, or upon fetching a control

byte for a received control character that specifies an

changes and BCC anticipations or transmission may

interrupt. Receive function interrupt information is

be effected at the end of a data block if the PDP-11

stored in the RIC register.

program sets a marked byte count into a byte count

secondary register. The mode change and/or BCC
Transmit function interrupts occur as a result of error

command is then set by the PDP-11 program into the

~conditions or data block boundaries being encoun-

appropriate secondary register before
or during the

tered. Transmit functions interrupt information is

data block receive or transmit interval. When the

stored in a first-in, first-out buffer; the output of this

byte count reaches zero, the “mark” is detected by

buffer forms the NPR Status Register (NSR). The

the DVI1I,

buffer (or “silo”) is monitored ot detect overflow.

and/or BCC command.

which

responds

to the mode change

Receive function interrupts, transmit function inter-

Byte counts are set in 2’s complement form in bits

rupts,

00-14 of byte count secondary registers; the registers

and

NSR

silo

overflow interrupts,

enabled by SCR 06, 13,

when

12, set SCR 07, 15, 10,

are incremented with each byte transferred to count

respectively.

them up to zero. Thus, a byte count may be marked

The PDP—AII program should set SCR 08 in responSe

the marked byte count reaches zero (00-14=0), bit 15

by setting bit 15 to zero at byte count set time. When

‘to a receiver interrupt, enabling the DV11 to process

is set to one, enabling the DV11 to detect the mark.

3-6

Accessing Secondary Registers — The Sec-

ondary Register Selection Register (SRS) provides

3.1.3.2

3.1.4.3

Control Byte Inhibit - For protocols such as

DDCMP,

which

not require

arbitrary

BISYNC transparency operation, idling of a sync
causes a bad BCC and hence a NAK from the remote
terminal. Thus, the Transmitter Underrun bit

mode

changes within a data block, provision has been made
to inhibit the control byte fetch cycle. All characters

1ndlcates whether the NAKis the result of line errors

are included in BCC, and all are stored. The PDP-11

or 1d11ng syncs.

program sets the inhibit bit in the Line Protocol
Parameters secondary register-(bit 05 for receive, bit
06 for transmit). The inhibit is effective only when the

3.1.5

Data Transfer Operations

To establish a data transfer operation between core

DV11 is in mode 0. If DDCMP is implemented with

memory and a selected data line for either transmis-

control tables, but the Control Byte Inhibit feature is

sion or reception, the PDP-11 program must commu-

desired, the control table must provide space for

nicate the following basic information to the DV11:

mode 0, despite the fact that the hardware does not
actually reference that part of the table.

The identification of the selected data line.

3.1. 4 4

The quantity of data to be transferred,

Sync Character Selection- Two sync charac-

ters (A and B) may be manually set for each four-line

and

group (00-03, 04-07, 08-11, 12-15). Selection of the
sync character for a line is then accomplished by set-

ting the Sync A /B Selection bit (LCR 10) coincident

the address of the table of locations in
memory (the “data table”) for data read

with

or write.

the

Control Strobe (LCR

15).

The bit ‘is

1n1t1allzed to sync A (zero).
3.1.4.5

The PDP-11 program specifies the selected data line
Sync/Mark State Select — The selected sync

number in bits 00-03 of the SRS. The quantity of

characteris also used as the transmitted Fill charac-

data to be transferred is specified by loading a byte

ter. In lieu of syncs, the data line can be set to idle the

count into the appropriate DV11 secondary register.

MARK state upon both byte counts reaching zero by
setting Line Protocol Parameters bit 00 to 1. Idling of

- Similarly, the program loads the base address of the
core memory table into the DV11 secondary register

syncs takes place for a definite number of character
times. Idling of the MARK state occurs for an

provided.

indeterminate period (i.e., synchronization is lost).

Using the data table address to access the corre-

3.1.4.6 Stripping Received Syncs - Setting Line Protocol Parameters bit 01 to 1 causes sync characters

the data transfer. As each byte is transferred, the
DV11 increments both the byte count and the data -

sponding location in core memory, the DV11 starts

arriving after the achievement of synchronization,

table address (termed the “current address”). When

but before the first non-sync character, to be stripped

the byte count reaches zero, the DV11 initiates data

from the incoming data stream (1 €., not storedin the

block termination procedure and halts data reception

RC Silo). Sync characters with Wthh the receiver

for the corresponding line. (Data transmission is han-

achieves sync are strippedin any case.

dled somewhat differently, as will now be described).

3.1.5.1
3.1.4.7 Line Activity Snapshot - The PDP-11 pro-

Provision for Alternate Data Transmission

Tables — By means of the data sequencing method

gram can monitor conditions on a selected line by

just described, data can be transferred between core

examining bits 00-07 of the Line State Register,

memory and the selected data line at the maximum

‘which provide a snapshot of line activity. Of particu-

DV11 throughput rate. However, if more than one

lar interest in Line State 03 (Transmitter Underrun).

data tableis to be transmitted, the program would

Thisis set to one by the DV11 whenever datais not

have only the transmission time
of the last byte of the

available in time for the synchronous .transmitter,

previous table in which to establish a current address

and indicates that one or more idling syncs have been

and byte count for the next message, unless a double-

sent. In byte count-oriented protocols
or in IBM’s

reglster system was prov1ded

3-7

The DV11 provides such a double-register system in

the form of two registers for storage of transmitter

Start the DV11 Microprocessor

current addresses and two registers for storage of
transmitter byte counts. The registers are called prin-

Enable DV11 data interrupts and detect
interrupt requests

cipal current address, alternate current address, prin-

cipal byte count, and alternate byte count. Thus,
while the DV11 is transferring data from the table

Restart DVII Data Handling Section
after receiver interrupt and

defined by the principal current address and byte

count, the PDP-11 program may establish and load

the alternate current address and byte count. When
the principle byte count reaches zero, the DV11 continues the data transfer operation, without inter-

vSet the extended address bits to the DV11
for core memory addressing by the DV11.

The SCR also provides PDP-11 program control of
Microprocessor ROM functions and provides simulated transmission interrupts for maintenance

ruption, by switching to the alternate registers and

notifies the PDP-11 program, which may then load
the primary registers. This seesaw activity continues
until both byte counts are zero, at which time trans-

purposes.

Fonrmat of the SCR is displayed in Figure 3-3. Bit

mission stops.

assignments are described in detail in Table 3-2.

3.1.5.2 Table Size and Locatioh — Any memory loca-

tion, including those with extended address, may be.

3.2. 2

used and data tables may cross extended address

The Line Control Registeris intended for use by the

boundaries. Messages to be transmitted or received

PDP-11 program in order to:

Line Control Reglster (LCR)

“may comprise data tables
of up to 16,384 bytes.
1.

3.2

Enable reception on a selected line

2 - Read th‘e extended address bits used for

DIRECTLY-ADDRESSABLE REGISTERS

The DV11 contains 10 registers which may be directly

core memory addressing by DV11 second-

addressed by the PDP-11 program. Formats, desig-

ary registers, and

nations, addresses and mnemonic codes for these reg-

isters are displayedin Figure 3-3. The System Control
Register (SCR) and the Line Control Register (LCR)

Select the sync character(s) for each line.

are used by the PDP-11 program principally to set up

The LCR also implements the principal DVI1I

data transfers. The Control Status Register (CSR)

maintenance functions, as discussed in Chapter 3.

and the Line Status Register (LSR) are used to set up

the line modems. Other directly-addressable registers

The following LCR bit descriptions apply only to

are provided to enable interrupt interpretation and

those lines associated with a synchronous line card.

handling, access to DV11 secondary registers, and for
maintenance functions.

The enabhng of receptlon is controlled by separate

storage for each line. Thisis accomplished by using
The register bit description tables contain

LCR 15 as a strobe pulse generator to load LCR 13

read/write column to indicate whether bits are read

only, write only, or may be both read and written by

(Receiver Enable) into control storage for the line set

~ in SRS 00-03 at the time that LCR is set to 1 by the

the PDP-11 program. If a bit may be physically read

'PDP-11 program. The Sync Character Selection bit

by the program but the datum readis not valid, it is

listed as “write” with the “only’’ omitted; the con-

(LCR 10) and Maintenance bits LCR 09, 11, 12, and
14 are set in separate storages for each four-line

Verse case is s1m11ar1y treated. Bits intended exclusive-

group (00-03, 04-07, 08-11, and 12-15, as selected by

ly for maintenance use are describedin Chapter 5.

SRS 02-03) by LCR 15 strobe. Consequently, LCR
bits 09-14 are not valid for a line selected at a random
~ point in time and so are designated as write bits.
- Since LCR 15 strobes 09-14, programs must update
all
of the bits 09-14 when it is desired to update any
~ one of these bits. The LCR format for synchronous

3.2.1

System Control Register (SCR)

The System Control Register is a byte-addressable
register for use by the PDP-11 program in order to:

Initialize the Data Handling Section of
the DV11 Master Clear

line cards is displayed in Figure 3-3. Bit assignments

3-8

are described in detail in Table 3-3.

NPR STATUS INT.

OVFLOW INT.

T X s\Wo

< 13
NPR INTERRUPT

INT.
o\

MASTER

ENABLE

| NPR OVFLOW|

EN.

QM:

CLEAR

REC.INT

WRITE ENABLE

INTERRUPT

ADDRESS

STEP»

ROM BRANCH

u PROC

DISABLE

ITS

05
]

|ROM SINGLE

SOURCE

EXTENDED

ROM DATA

RECVR.

ENABLE

11-2684
|

02
N

INTERRUPTING CHARACTER

READ ONLY)

( ALL BITS ARE

E Y\
2L

11-2685

LINE CONTROL REGISTER (LCR) 775004 (FOR SYNCHRONOUS LINE CARDS)

CONTROL
STROBE

‘I1

/,//

RECEIVER

SYNC A/

ENABLE

DATA

/
//

\
_J

EXTENDED

BRANCH TRUE

ADDRESS

MAINT.BIT

DISABLE

CLOCK

TRANSMITTER

MODE

|MAINTENANCE

SYNC B

MAINTENANCE ~ MAINTENANCE
N

'RECEIVER INTERRUPT CHARACTER REGISTER (RIC) 775002

BITS

WINDOW

11-2686

\\~,~"‘“'—““\\Va—\h_,/’/
@klf 4o inE BASILE

LINE CONTROL REGISTER (LCR) 7?5004 (FOR ASYNCHRONOUS LINE CARDS)

410

| S

LINE CARD

STROBE

REGISTERS( 2

,\(;/ SELECTION

ADDRESS

RERIAED roR wriT
e .I»fl-"fi q-i%

BRANCH

TRUE

BITS

CODE

X ////

EXTENDED

o4&

-—

ASYNCHRONOUS

CONTROL

x |x | x | R

w | w | w | w | owo|ow

4‘/\\\

T’

RECVR. INT

SERVICE
COMPLETE

BIT 15¢7

«—— INTERRUPT CODE ——»je——— LINE NUMBER

SYSTEM CONTROL REGISTER'(SCR) 77 5000

1-4407

SECONDARY REGISTER SELECTION REGISTER (SRS) 775006
15

“

—_

J\_

‘,;f

LINE SELECT

UNUSED

11-2687

|
15

I
|

SECONDARY REGISTER ACCESS REGISTER (SAR) 775010
14

I
l

DATA TO/FROM SECONDARY REGISTER SELECTED BY SRS REGISTER

|
11-2688

Figure 3-3

DV11 Primary Registers (Sheet 1 of 3)

3-9

SPECIAL FUNCTIONS REGISTER (SFR) 775012
15

ROM DATA REGISTER CONTENTS

.
I1-2689

NPR STATUS REGISTER (NSR) 775014
11

“

pTa—

VALID
IN

—~

~ INTERRUPT CODE

P b’é"rs.,w

UNusED

00-11

UNUSED

LINE NUMBER
|

11-2690

RESERVED REGISTER (RIR) 775016
15

———

—

11-2691

CONTROL STATUS REGISTER (CSR) 775020 (FOR SYNCHRONOUS LINE CARDS)
15

RING

CLEAR TO

CLEAR

SEND TRANS

—

CARRIER

DONE

MODE

DATA SET

TRANSITION

CLEAR

READY TRANS

STEP

MUX

SCAN

ENABLE

INTERRUPT

BUSY

ENABLE

5235’5j14.oq 15 TRUE= DomE

11—-2692

CONTROL STATUS REGISTER (CSR) 775020 (FOR
15

RING

CLEAR

\‘%}

|MAINTENANCE

SCAN

SECONDARY

CLEAR

RECEIVE
TRANSITION

MU X

[

CARRIER

©O08

ASYNCHRONOUS LINE CARDS)
06

©O5

CLEAR

TRANSITION | SEND TRANS

DONE

MODE

SCAN

INTERRUPT

041

LINE

NUMBER
o

BUSY

ENABLE

'7 i;]

Figure 3-3

ENABLE

STEP
|

"
N

~ LINE NUMBER

MAINTENANCE

SCAN

TRANSITION

DVI11 Primary Registers (Sheet 2 of 3)

3-10

1-4408

LINE STATUS REGISTER (LSR) 775022 (FOR SYNCHRONOUS LINE CARDS)
15

09 08

UNUSED
'

RING

CLEAR TO

NEW

SEND

SYNC

‘

CARRIER ON
—

DATA SET

READY

TERMINAL
READY

REQ TO
SEND

J\..

MODEM STATUS

LINE

ENABLE
J

MODEM CONTROL
11-2693

LINE STATUS REGISTER (LSR) 775022 (FOR ASYNCHRONOUS LINE CARDS)
15

UNUSED
|

CLEAR TO

RING

04
|

"SEND

CARRIER

RECEIVE

LINE

SEND

TRANSMIT

ENABLE

TERMINAL

READY

MODE
M

CONTROL
|

W=WRITE ONLY
W1= WRITE ONES ONLY
X=UNUSED

% = FOR MAINTENANCE ONLY

Figure 3-3 DV11 Primary Registers (Sheet 3 of 3)

311

REQ TO

SECONDARY
“

|
|

MODEM

SECONDARY

STATUS

LEGEND

'R=READ ONLY

11-4409

Table 3-2

System Control Register Bit Assignments
Bit(s)

Designation

Function

Microprocessor GO

- When seto one, enables the Microprocessor to

Read/Write

Read or Write'

operate the DV11 Data Handling Section. Must

be set to one to enable DV11 to perform any
functions other than modem control. Cleared
by Initialize.
01-03

(Maintenance)

See Chapter 5.

04-05

Extended VAd‘dress

The contents of these bits as set by the PDP-11
program form bits 16 and 17, respectively, of

Write

any current address or control table base address
loaded by the PDP-11 program into a secondary
register for the line selected by SRS 00—03.
These bits must be set before loading the

Secondary register. These bits are read/write,
but when read reflect only the values of SCR

04—05,and not the values of address bits 16 and
17 for the selected line. (Refer to the discussion

of Line Control Register bits 04—05.) Thus, an

interrupt service routine saving the contents of
these bits will store bits 04—05 exactly as set by

the PDP-11 program. Cleared by Initialize.
06

Receiver Interrupt

When set to one by the PDP-11 program, enables

Read or Write

“ the Microprocessor to interrupt the PDP-11 program by setting a one in SCR 07. Cleared by

Initialize.
07

Receiver Interrupt

Set to one by the DV11 to request a PDP-11 pro-

(Vector A)

gram interrupt occurring during data reception.

Read or R/W

The reception conditions that cause the DV11 to

request an interrupt are listed in Table 3-3. The
PDP-11 program should respond to the interrupt

by reading the Receiver Interrupt Character Reg-

ister to identify the condition and may then load
the Receiver Control Byte secondary register with

a new control byte. The PDP-11 program should
then set SCR 08. SCR 07 does not cause an interrupt unless SCR 06 has been set to one by the
PDP-11 program. Cleared by Initialize. This bit

is read only except when SCR 09 is set, in which

case it is read/write.
08

Receiver Interrupt

Set to one by the PDP-11 program when it has com-

Service Complete

pleted an interrupt service routine and desires
Microprocessor servicing of the character in the

Receiver Interrupt Character register. Setting of
this bit clears SCR 07. Cleared by Initialize.

3-12

Read or Write

Table 3-2 (Cont)
System Control Register Bit Assignments

“Bit(s)

Designation

Function

Read/Write

Read or Write

(Maintenance)

See Chapter 5.

NPR Status Overflow

Set to one by the Microprocéssor whenever the

(Vector B)

NPR Status Register/silo is full. Failure occurs

whenever the PDP-11 program does not promptly

read the NPR Status Register contents following
a SCR 15 interrupt, and 64 NPR status entries

have occurred. SCR 10 does not cause an interrupt unless SCR 12 has been set to one by the
PDP-11 program. Cleared by Initialize.

Master Clear

When set to one, clears the following bits
in the

DV11:

Read or Write

SCR bits 0-3,6,7,9,10,11,12,13,15
RIC bits 0—15

LCR bits 7—-14
NSR bit 15
-

The Received Character Silo is also cleared. This

bit is self-clearing.

When set to one, enables the .se‘tting of SCR 10 to

Interrupt Enable

generate an interrupt request. Cleared by Initilize.

o NPR'Status Interrupt
-

NPR Status Overflow

Enable

When set to one, enables the setting of SCAR 15 to

generate an interrupt request. Cleared by Initialize.

—

Unused.

- Read or Write
|

|
—

NPR Status Interrupt

~ Set to one whenever the Microprocessor loads data

(Vector B)

~into the NPR Status Register to report an interrupt
condition occurring during data transmission. Set

to zero whenever the PDP-11 program reads the
~

Read or Write

NPR Status Register. This bit is read only except
when Bits 07 and 15 Write Enable (SCR 09) are

set to one, in which case it is read/write. SCR 15

does not cause an interrupt unless SCR 13 has
been set to one by the PDP-11 program. Cleared
by Initialize.

3-13

Read or R/'W

Table 3-3

(

Line Control Register Bit Assignments

.‘

(For Synchronous Line Cards)
Designation

00—-01

(Maintenance)

See Chapter 5.

Unused |

02—03
04—05

'Read/Write

Function

Extended Address

For the secondary register selected by SRS

Read

00—03 and 08—11, these bits display the con-

Read only

tents of bits 16 and 17, respectively. This en-

~ ables the program to read the extended address

bits of the cu_rrént address and control table base
address secondary registers.

Unused

07—-09

~ (Maintenance)

Sync Select

See Chépter 5.
For the line selected by SRS 0003, this bit sets

Write

Sync A character or Sync B character, depending
on whether this bit is set to zero or one, respec-

tively, at LCR 15 set time. Cleared by Initialize.

Sync character encoding is discussed in Chapter 2.
11,12

(Maintenance)

Seé Chapter 5.

Recyeiv'e.r Enable

‘When set to one at LCR 15 set timé, causes the
receiver for the line set in SRS 00—03 to search

for the synchronization character(s) in the input

bit stream. When the synchronization character(s)
is found, the Microprocessor sets the Receiver

‘Active bit in the Line State secondary register.
'LCR 13 must be set to one
to enable reception on
‘a line following Initialize. This bit is not used for

resynchronization during reception.
To resynchronize during reception, the Receiver
Resynchronize bit in the Line State secondary
register is set to one.

To shut down reception in a line, the line number
is set in SRS 00—03 and LCR 13 is set to zero at
LCR 15 set time. The Receiver Resynchronization bit in the Line State secondary register is

then set.
Cleared by Initialize.
14

(Maintenance)

See Chapter 5.

3-14

Write

Table 3-3 (Cont)

Line Control Register Bit Assignments
(For Synchronous Line Cards)

Designation

- Bit(s)

C'ontrol Strobe

Function

| Read/Write

When set to one, strobes LCR 13 into control

storage for the line set in SRS 00—03 and strobes

Write

LCR 09,10, 11, 12, 14 into control storage for

the 4-line group set in SRS 02—03, then clears

itself. May be set at the same time as the LCR
bits that it strobes into storage for the selected

line or line group.

The f(\)llowing LCR bit descriptions apply only to

The format of the RIC is shown in Figure 3-3. Specif-

those lines associated with an asynchronous line card.

ic bit assignments for the RIC are as follows:

For asynchronous line cards, each line ha_s four 4-bit

Bits 00-07:

registers associated with it, each of which may be

loaded by addressing the LCR with appropriate reg-

ister selection bits set in LCR 09 and 10, in addition
to the line selection bits set in SRS 00-03. The four

least significant bit. On parity-equipped syn-

chronous characters of less than eight bits, the

registers associated with each line are called the

“Primary,” “Format,” “Baud Rate,”” and “Maintenance’’ registers and are selected by LCR 10-09 codes

of 00, 01,

parity bit will appear immediately to the left of

- the highest order bit in the character.

10, and 11 respectively. While the bit

Bits 08-11:

assignments are described in detail in Table 3-4, it can

This field contains the line num-

ber on which the interrupting character was
received. Bit eight is the least significant bit.

be noted here that LCR 15 (Line Control Strobe)

functions the same for asynchronous line cards as it

Bits 12-15: This field contains the code speci-

does for synchronous line cards and that the cautions
expressed above with regard to LCR bits 09-14 are

fying the reason for the interrupt. Refer to

similarly valid for the asynchronous case. The LCR

Tables 3-5 and 3-6 for

format. for asynchronous line cards is displayed in

Figure 3-3. Bit assignments are described in detail in
Table 3-4.
S

This field contains the inter-

rupting character, right-justified. Bit 00 is the

3.2.4

code meanings.

NPR Status Register (NSR)

The NPR Status Register is a 64-level “read-once”

3.2.3

Receiver Interrupt Character Register (RIC)

silo; that is, a read of this silo “empties’ it of its old-

The Receiver Interrupt Character Register is a read-

est entry (destructive read), and any new data ‘“falls”

only register which stores the character that caused

into the silo output if new data is waiting when a read

the PDP-11 program interrupt, the line number on

i1s completed. The NSR is read-only register which

which the character was received, and the code speci-

identifies (1) interrupt-causing conditions that occur

fying the reason for the interrupt. This register is

during character transmission
and (2) the line num-

cleared by Initialize.

ber on which the interrupt occurred.

3-15

Table 3-4

Line Control Register Bit Assignments
(For Asynchronous Line Cards)

Bit(s)

Function

Read /Write

Extended Address

For the secondary register selected by SRS 00—03

Read only

Read

and 08—11, these bits display the contents of bits
16 and 17, respectively. This enables the program

Designation

00, 01

(Maintenance)

See Chapter 5.
Unused

02, 03

04,05

to read the extended address bits of the current

address and control table base address secondary
reglsters

Unused

06, 07, 08

09,10

For the line number selected by SRS 00—-03, the

Code

code bits determine which Asynchronous Line

Write

Card register is written into at LCR 15 set time.

There are four registers associated with each line

and they are called “Primary,” “Format,” “Baud

- Rate,” and “Maintenance” registers. Descriptions

of the register bits are foundin LCR 11-14.

Cleared by Inltlahze
Asynchronous

11-14

Line Card
~

Registers

This is the path provided for access to the line card
registers. Loading of a register occurs at LCR 15

Write

set time and is dependent on the line number

selected by SRS 00—-03, and the register selection

code set in LCR 09—10. Each line has four 4-bit
registers associated with it, designated as:

“Primary,” “Format,” “Baud Rate,” and
“Maintenance.” These registers are cleared by
Initialize. Bit assignment description of the
registers follows LCR 15 functional description.

Control Strobe

When set to a one, strobes LCR 11,12, 13, 14 into

‘Write

control storage for the register selection code set

~in LCR 09—10 and the line specified by SRS

00—03, then clears itself. May be set at the same
time as the LCR bits that it strobes mto storage
for the selected register.

3-16

Table 3-4 (Cont)
Line Control Register Bit Assignments

(For Asynchronous Line Cards)

| Bit’v(‘s) |

Designation

Read/Write

Function

Asynchronous Line Card Primary Register |
09,10

For the line number selected by SRS 00—03, the

Primary Register

Selection Code 00

- Write

code of 00 specifies writing into the Primary
register at LCR 15 set time.

Half Duplex/ s &7

This bit, when set, conditions the line to operate in

Full Duplex

“half duplex mode. If this bit is cleared,
the line is

Write

conditioned to operate in full duplex mode. When
operating in half duplex mode, the selected receiver

is blinded during transmission of a character.
12

Even Parity

This bit, when set, generates characters with even

Write

parity on the line and expects received characters

to have even parity. If this bit is cleared, characters

of odd parity are generated on the line and received
characters are expected to have odd parity. The
state of this bit is immaterial if the Parity Enable

bit (Format register bit 14) is not set. This bit

must be conditioned prior to loading the Format
Register.
13

Receiver Enable

This bit must be set before the receiver logic can

Write

assemble characters from the serial input line. When

this bit is set, Receiver Active (Line State Bit 00)

is subsequently set. To shut down reception on a
line, the program should first clear Receiver Enable

and the set Receiver Resynchronize (Line State

Bit 01). The program must wait one character
-interval after shutdown before restarting a line.
14

Break

This bit, when set, forces a space on that line’s
output causing a break condition. The break con-

Write

dition may be timed by sending characters during

the break interval, since these characters never
reach the EIA line.

When set to a one, strobes the Primary Register

Control Strobe

bits 11, 12, 13, 14 into storage for the line specified in SRS 0003, then clears itself. May be set
at the same time as the bits that it strobes into
-

storage.

3-17

Write

Table 3-4 (Cont)
Line Control Register Bit Assignments

(For Asynchronous Line Cards)

Bit(s)

Designation

Function

Read/Wtite

~ Asynchronous Line Card Format Register

09,10

| |

Format Register

For the line number selected by SRS 00—03, the

Selection Code 10

code of 10 specifies writing into the Format

Write

11,12

Character Lerigth

These bits are set to transmit and receive chafacters

~of the length (excluding parity) as shown below.

Two Stop Bits

7 bits

8 bits

Write

Selected Character Length

5 bits
,

6 bits

This bit, when set, conditions the line transmitting

Write

with 5, 6, 7, or 8 bit code to transmit characters

having two stop bits. One stop bit is sent when this
bit is cleared.

Parity Enable

If this bit is set, characters transmitted on the line

Write

~ have an appropriate parity bit affixed, and charac-

ters received on the line have parity checked. Parity
sense is determined by the state of Primary Register
bit 12.

Control Strobe

When set to a one, strobes the Format register bits

Write

11,12, 13, 14 into storage for the line specified in
SRS 0003, then clears itself. May be set at the
same time as the bits that it strobes into storage.

Asynchronous Line Card Baud Rate Register

09, 10
|

Baud Rate

For the line number selected by SRS 00—03, the

code of 01 specifies writing into the Baud Rate

Selection
Code 01

11-14

Speed Code

Write

10=1.

The state of these bits determine the operating

speed for the transmitter and receiver
of the
selected line.

3-18

Write

Table 3-4 (Cont)
Line Control Register Bit Assignments

(For Asynchronous Line Cards)

- Bit(s)

Designation

Function

Read /Write

Asynchronous Line Card Baud Rate Register (Cont)

11—-14 (Cont)

Control Strobe

‘Baud Rate
50

110

134.5

-0

150

300

600

1200

-0

2000

-0

2400

3600

4800

7200

9600

38,400%*

1800

When set to a one, strobes the Baud Rate register

Write

bits 11, 12, 13, 14 into storage for the line specified

in SRS 00—03, then clears itself. May be set at the
same time as the bits that it strobes into storage.

*Special Interface Leads For High Speed Operation
DV11 Busy
— A response that originates from an asynchronous receiving line to 1nd1cate that the character servicing rate for that hne
is not being sustained. Toinsure received data integrity, external hardware must interpret and 1mplement this response in such a
fashion to provide a restraining feature on the remote transmitter. The “ON> condition of DV11 Busy is indicated by a negative voltage

in the 3 to 15 volt range. The “OFF” condition of DV11 Busy is indicated by a positive voltage in the 3 to 15 volt range. DV11 Busy
‘is in the off state following a Unibus Initialize, DV11 Master Clear, or Receiver Enable cleared (LCR Primary Register bit 13). The ON

duration of this lead is dependent on the servicing rate of the DV11 Character Processor. Therefore,

DV11 Busy may be of any minimal

period. DV11 Busyis asserted a maximum of 10/16th of a bit time following receptlon of the first stop bit, For an operating speed of
38,400 baud, the DV11 Busy feature must be used.

Data Set Busy — The capability of an asynchronous transmitting
line to have continual transmission remotely started and stopped.

This is the complementary feature of DV11 Busy. Data Set Busy must be implemented with external supporting hardware
and must

be used with an operating speed of 38,400 baud. Line card modification is required for implementing Data Set Busy at a baud rate
other than 38,400 baud. The “ON”’ condition of Data Set Busy is interpreted by a negative voltage in the 3 to 15 volt range. The

“OFF” condition of Data Set Busy is interpreted by a positive voltage in the 3 to 15 volt range. Data Set Busy, when on, is defined as
a remote stop request. To inhibit continual character transmission, Data Set Busy must be received prior to 15/16th of the last stop

bit interval. Data Set Busy is invalid when the line is being operated in either internal maintenance mode or at an operating speed less
than 38,400 baud, assuming no line card modification was performed.

,-/

Table 3-4 (Cont)
Line Control Register Bit Assignments

(For Asynchronous Line Cards)

~ Bit(s)

‘Designation

Function

Read/Write

Asynchronous Line Card Maintenance Register

09, 10

Maintenance

For the line number specified by SRS 00—03, the

code of 11 specifies writing into the Maintenance

Selection

Write

Code 11

Maintenance
Internal Mode

This bit, when set, loops the transmitter’s serial output
lead to the receiver’s serial input lead. While operating

in maintenance mode, the EIA transmit data leads, |
EIA received data leads, and the remote Data Set busy
features are disabled. Normal operating mode is

Write
|

assumed when this bit is cleared.

12—14

—
Control Strobe

Unused

—

When set to a one, strobes the Maintenance register

Write

bit 11 into storage for the line specified in SRS
00—03, then clears itself. May be set at the same
time as the bit that it strobes into storage.

conditions and associated line
numbers are stacked in the 64 entry first-in, first-out
silo buffer and dropped into the NSR output as each
prior entry is read by the PDP-11 program Each time

3.2.6

a new entry is dropped into NSR output, NSR 15 is

3.2.7 Secondary Reglster Selection Register (SRS)
The Secondary Register Selection Register provides
for PDP-11 program access
to the secondary registers
in the DV11 RAM. To address
a secondary register,
the PDP-11 program sets the 8-bit RAM address,

Interrupt-causing

set to indicate the presence of valid data and SCR 15
is set to request an interrupt. Each time an NSR entry
is read by the PDP-11 program, NSR 15and SCR 15

are reset to zero. NSR 15 is also set to zero by
Initialize. (The other NSR bits are not reset to zero

by initialize. )

The NSR format is shown in Figure 3-3. Transmis-

consisting of the 4-bit line number, plus the 4-bit reg~ ister selection code, in SRS 00-03 and SRS 08-11,

respectively. Loading or reading the SRS is then
~accomplished by loading or reading the SAR. Inter-

rupt service I‘OlltlIlCS must save the contents of the'

‘sion interrupt codes are described inTable 3-7.

3.2.5

Special Functions Register (SFR)

The Special Functions Register is used for maintenance only (refer to Chapter 5 for descrlptlon)

SRS.

The 4-bit line selection code in SRS 00-03 provides
for selection of the 16 data lines. The 4-bit register
selection code in SRS 08-11 provides for selection of
the 16 secondary registers supplied for each data line.

Reserved Register

Reserved for future system requirements.

3-20

Table 3-5

Receive Function Interrupt Conditions
(For Synchronous Line Cards)

Code Set in RIC 12-15
15

Meaning
Special Character Received:

Bit 00 of the control byte for the characterin RIC 00—07is set to one (generate interrupt), indicating that the received characteris a special character.

Parity Error | |
The characterin RIC OO 07 has a parlty sense opposite to that selected for

this line (the line specifiedin RIC 08—11) by the parity sense switches on the

M7839 module (Figure 2-6).

0
|

OVerfun:

The received character(s) preceding the character set in RIC 00—07 have been
lost because of overflow of the Received Character Silo.

Parity Error and Overrun:
As described above for error codes 0001 and 0010.

Byte Count Warning:

The character set in RIC 00—07 has been stored in core memory. No more

///

characters may be stored for this line as the byte count is now zero.
0

Block Check Complete:

The block check character(s) for the data block received on this hne have
arrived and have been includedin the Accumulated BCC. The Accumulated |
BCC is now in the Receive Accumulated Block Check Character secondary
register; the OR of the hlgh and low bytes of the accumulated BCCis set in
RIC 00-07.

Undefined

Byte Count Zero:

The receive byte count for this line was zero prior to receipt of the character
set in RIC 00—07. Thus, the character was not stored as no assigned storage
was available.

Undefined

Processing Error 00:

A non-existent memory time-out occurred when the DV11 attempted to store
the character set in RIC 00-—-07.

| 1

Processing Error Ol

A non-existent memory time-out occurred when the DV 11 attempted to fetch
- the control byte corresponding to the character set in RIC 00—-07.

3-21

Table 3-5 (Cont)
Receive Function Interrupt Conditions

(For Synchronous Line Cards)

Code Set in RIC 12—15

Meaning
Processing Error 10:

The DV11 received a signal on the memory parity error line from the PDP-11

when the DV11 attempted to store the character set in RIC 00—07. This condition indicates a defectin the memory parity logic, as the PDP-11 generates
parity error signals only on core memory read operations.
1

Processing Error 11:

A memory parity error occurred when the DV11 attempted to obtam the con- trol byte corresponding to the characterin RIC 00— 07

Table 3-6

Receive Function Interrupt Conditions
(For Asynchronous Line Cards)

in RIC 12—15
Code Set
15

h Meaning
- Special Character Received:

Bit 00 of the control byte for the character in RIC 00—07 is set to a one
(generate interrupt), indicating that the received character is a special character.
Parity Error:

The characterin RIC 00—07 has a parlty sense oppos1te to that selected for this
line (the line specifiedin RIC 08—11) by the programmable Format registers of

‘the Asynchronous Line Card.
Overrun Error:

The received character(s) preceding the character set in RIC 00—07 have been
lost because of overflow of the Received Character Silo.
Framing Error:

The character set in RIC 00—07 lacked a stop bit present at the proper time.
This codeis usually interpreted as indicating the reception of a break.
Byte Count Warning:

The character set in RIC 00— 07 has been storedin core memory. No more characters may be stored for this line as the byte count is now zero.
Block Check Complete:

The block character(s) for the data block received on this line have arrived and

have been includedin the Accumulated BCC. The Accumulated BCC is now in

the Receive Accumulated Block Check Character secondary register; the OR of

the high and low bytes of the accumulated BCC is set in RIC 00—07.

3-22

Table 3-6 (Cont)
Receive Function Interrupt Conditions

(For Asynchronous Line Cards)

Code Set in RIC 12—15
15

Undefined

Byte Count Zero:

Meaning

—

The receive byte count for this line was zero prior to receipt of the character set

in RIC 00—07. Thus, the character was not stored as no assigned storage was

‘available.
1

Undefined

~ Processing Error 00:

A non-existent memory time-out occurred when the DV11 attempted to store
the character set in RIC 00—-07.

-0

Processing Error 01

A non-existent memory time-out occurred when the DV11 attempted to fetch
the control byte corresponding to the character set in RIC 00—07.

1
|

0
|

Processing Error 10:
|

A DVI11 received signal on the memory parity error line from the PDP-11 when

the DV11 attempted to store the character set in RIC 00—07. This condition
indicates a defect in the memory parity logic, as the PDP-11 generates parity

error signals only on core memory read operations.
1

1
~

Processing Error 11:
A memory parity occurred when the DV11 attempted to obtain the control
byte corresponding to the character in RIC 00—07.

NOTE

A priority encoding scheme is used by an asynchronous line to presenta multiple error code condition. Any
error flag combination that contains an overrun error is presented as an Overrun Error (code 0010) in the
RICR register.
A framing error and parity error combination is presented as a Framing Error (code 0011) in

the RICR register. A multiple error condition that displays a Parity Error (code 0001) does not exist. This
priority scheme is used only by the Asynchronous Line Card. Existing error code bits that are generated on

a synchronousline are not affected by this scheme.

3-23

- Table 3-7

Transmit Function Interrupt Conditions

" Code Set in NSR 08—11
11

Meaning

Transmitter prmmpal current address spe01fied a non-existent memory loca-

tion (NXM).

Transmitter principal byte count is equal to zero.
Transmltter alternate current address specified a non-emstent memory loca-

‘tion (NXM)
0

Transmitter alternate byte count is equal to zero.

An attempted control byte fetch by the DV11 produced a non-existent _‘memory condition or a memory parity error. (The specific error is set in the Line
State secondary register.)

SRS 00-03 are also used to select line control storage

numberin the CSR, then sets the Line Enable bitin

for loading from the Line Control Register.

the LSR.

Formats
for the CSR and LSR are displayed in Fig-

CAUTION

Do not change the contents
of SRS without checking
~ that LCR 15 is cleared, indicating that any outstanding

LCR load to the line cards has been completed.

ure 3-3. Bit assignments are described in detail in

Tables 3-8 and 3-9, respectively. Some bit assignments have dual definitions to reflect the type of
modem that is being controlled (i.e., synchronous vs

3.2.8

Secondary Register Access Register (SAR)

The Secondary Register Access Register provides the

- asynchronous). Tables 3-8 and 3-9 define each bit

assignment as it applies to both modem types.

PDP-11 program with direct access to the secondary
register selected by the SRS register. Loading or read-

The interrupt mode is set for all enabled lines by set-

ing the SAR is equivalent to loading or reading the

ting CSR 05 and 06 each to one. CSR 05 (Scan
Enable) causes the MCU to scan the enabled modems
cyclically to detect a change or transition in one of

secondary reglster addressed by SRS 00-03 and
08-11.

3.2.9

the modem status bits. When a transition is detected,

Modem Control Registers

PDP-11

scanning is stopped, the condition causing the transi-

tion is set in the CSR 12-15 field, the line number for

program control of the line modems is

accomplished through the Control Status Register

the signalling modem
is available in CSR 00-03, CSR

(CSR) and the Line Status Register (LSR) in the

07 (Done bit)is set to one, and the PDP-11program

“Modem Control Unit (MCU) of the DV11. The CSR
controls data line or modem selection and operating

is interrupted.

The non-’interrupt mode is feasible if only one modem

mode (interrupt or non-interrupt) of the MCU, and

enables the detection of changes in modem status by

is to be monitored for activity at one time. The line

number for the modem
is set in the CSR and modem

the PDP-11 program. The LSR routes control bits
provided by the PDP-11 program to the modems and

status bits LSR 04-07 are continuously sampled by

transfers modem status bits to the Unibus for the

the PDP-11 program. When one of these status bits

modem(s) selected via the CSR. To enable any one of

becomes

set to one, the PDP-11
respond by setting a 03.

the 16 lines, the PDP-11 program sets the selected line

3-24

program

may

Table 3-8

Control Status Register Bit Assignments
Bit(s)

Designation

00—03

LINE (Line Number)

Function
Binary address of one of 16 modems:

LineNo.

o0 1

Read/Write
Read or Write

Cleared to 0000 by Initialize or Clr Scan (bit 11 of
CSR). Sixteen rmcroseconds +10% settling time is
. ,requlred
- This portion of the CSR is a presettable binary
counter; thus, it may be loaded directly by the

- PDP-11 program to address a selected data line, or

advanced by SCAN EN (CSR bit 5) or STEP (CSR

bit 8) to address sequent1a1 data lines.
04

BUSY

Set to 1 whengver modems are being cyclically

Read only

scanned or a Clr Scan (CSR bit 11)is being
executed.

SCAN EN

Causes cyclical scanning of status lines from all

~ (Scan Enable)

enabled modems when set to 1 if Done (CSR bit

Read or Write

7)is set to 0. Scanning stops and Doneis set to
1 when a status transition is detected. A 1.2

microsecond period is required for scanning to
come to a halt when the PDP-11 program changes

this bit from 1 to 0; therefore, Busy (CSR bit 4)
must be tested for its zero state before changing

the line number (CSR bits 0—3) to ensure that
all detected transitions are serviced. Cleared by

Initialize and Clr Scan (CSR bit 11).
06

INTER EN
(Interrupt Enable)

Enables Done signal from CSR bit 7 to cause a
PDP-11 interrupt on priority four when set to 1.

Cleared by Initialize and Clr Scan (CSR bit 11).

3-25

Read or Write

Table 3-8 (Cont)

Control Status Register Bit Assignments

Bit(s)
07

Designation

Function

Set to one whenever a transition occurs on a

-DONE

Read/Write
Read or Write

status line (RING, CO, CS, DSR) from an
enabled modem during the modem scanning
process, as initiated by Scan En (CSR bit 5).
When Done is set to one, the scan stops and the

status transition(s) are set in CSR bits 12—15.
The line number of the modem with the new

status is in CSR bits 0—3, and the current states
of that modem’s status lines are reflected in LSR
bits 4—7. Cleared by Initialize and Clr Scan (CSR

bit 11).
08

- STEP

When set to 1, causes the line number in CSR bits
0—3 to be incremented by 1. If a status transition

is detected for the new line, Done (CSR bit 7) is

set to 1. Done does not inhibit Step. This bit is

used principally for maintenance and requires
1.2 microseconds £10% to execute. This bit is
~ write ones only.

(Maintenance)

CLEAR MUX

See Chapter 5.

Clears bits 4—7 of the LSR (RS, Term Rdy, NS,

Write ones

Line En) for all lines when set to 1. This bit is
write ones only.

CLR SCAN

Clears bits 03, 5, 6, 7,9, and 1215 of the CSR
when set to 1, and clears MCU “‘Scan Memory’’ in

| 18.8 microseconds
£ 10%.

- (The MCU detects modem status transitions by
storing the conditions of the several modems’

status lines in Scan Memory, then continuously
comparing the updated status conditions with

the previous status conditions during the modem
scanning process. Thus, if Scan En (CSR bit 5)
is set to 1 following a Clear Scan and the interrupt

mode is set,
an interrupt will occur for all modems
which have ON status lines (DSR, CS, CO, RING),
as these will appear as OFF to ON transitions to

the MCU.)

3-26

Write ones

Table 3-8 (Cont)
Control Status Register Bit Assignments

Bit(s)

Designation

Function

- DSR

Read/Write

Set to 1 whenever an ON to OFF or OFF to ON

Read only

(Data Set Ready

transition occurs on the DSR status line from the

transition)

selected modem. Not valid if the PDP-11 program

(Synchronous
modem definition)

has changed the line number in CSR bits 0—3 and
“the scan has not been cycled for one or more lines

by Scan En (CSR bit 5) or Step (CSR bit 8). Cleared
by Initialize or Clr Scan.

SEC RX

Set to a 1 whenever an ON to OFF or OFF to ON

(Secondary Receive

transition occurs on the SEC RX status line from

transition)

the selected modem. Not valid if the PDP-11 pro-

| (Asynchronous

gram has changed the line number in CSR bits 0—3

~modem definition)

and the scan has not been cycled for one or more

Read only

lines by Scan En (CSR bit 5) or Step (CSR bit 8).
Cleared by Initialize or Clr Scan.

Set to 1 whenever an ON to OFF or OFF to ON

(Clear to Send

transition occurs on the CS status line from the

transition)

selected modem. Not valid if the PDP-11 program

Read only

has changed the line number in CSR bits 0—3 and
the scan has not been cycled for one or more lines

by Scan En (CSR bit 5) or Step (CSR bit 8)
- Cleared by Initialize or Clr Scan.

Set to 1 whenever an ON to OFF or OFF to ON

(Carrier On

transition occurs on the CO status line from the

transition)

selected modem. Not valid if the PDP-11 program

has changed the line number in CSR bits 0—3 and

‘Read only

the scan has not been cycled for one or more lines

by Scan En (CSR bit 5) or Step (CSR bit 8).

- Cleared by Initialize or Clr Scan.
15

RING

(Ring Signal)

Set to 1 whenever an OFF to ON transition occurs

on the RING status line from the selected modem.
- Not valid if the PDP-11 program has changed the
line number in CSR bits 0—3 and the scan has not

been cycled for one or more lines by Scan En
(CSR bit 5) or Step (CSR bit 8). Cleared by
Initialize or Clr Scan.

3-27

Read only

N
//

Table 3-9

Line Status Register Bit Assignments
Bit

Designation

Function

Read/Write

LINE EN

When set to 1 for the line selected by bits 0—3 of the CSR,

Read or Write

(Line Modem Enable)

- causes status conditions DSR, CS, CO, and RING from

the corresponding modem to appear in bits 4—7 of the
LSR and causes status transitions from the same modem

to set the Done bit (CSR bit 7) to 1 during the scanning process. To set the Line En bit for a line, the line number

is set in the CSR, then the Line En bit is set in the LSR.
Cleared by Initialize and Clear Mux (CSR bit 10).

TERMRDY

When set to 1 for the line selected by bits 0—3 of the CSR,

(Terminal Ready)

maintains line seizure (“‘off-hook” condition) for the corre-

Read or Write
-

sponding modem. To set the TERM RDY bit for a line, the

line number must be in the CSR, then the TERM RDY bit

Q
o

- is set in the LSR. Cleared by Initialize
and Clear Mux.

When set to 1 for the line selected by bits 0—3 of the CSR,

(Request to Send)
|
|

conditions the corresponding modem to transmit data. To
set the RS bit for a line, the line number must be in the

" Read or Write

CSR, then the RS bitis set in the LSR. Cleared by Initialize

and Clear Mux,

(New Sync)
(Synchronous
modem definition)
|

03
-

SEC TX
(Secondary Transmit)
(Asynchronous
|
-

modem definition)

|
04

When set to 1 for the line selected by bits 0—3 of the CSR,

Read or Write

signals the corresponding modem to resynchronize on the
carrier. To set the NS bit for a line, the line number must

|
|

bein the CSR, then the NS bit is set in the LSR. Cleared
by Initialize and Clear Mux.

When set to a 1 for the line selected by bits 0—3 of the CSR, |
~ signals the corresponding modem to transmit on the reverse
‘channels. To set the SEC TX bit for a line, the line number

Read or Write
|

must be in the CSR, then the SEC TX bit is set in the LSR.

Cleared by Initialize and Clear Mux.

DSR

Set to 1 whenever the DSR line from the modem selected

(Data Set Ready)

by bits 0—3 of the CSRis ON, provided that the Line En

Synchronous

bit for that modem has been set. Indicates the modem

modem defm1t1on)

has seized the line.

SEC RX

Set
o 1 whenever the SEC RX line from the modem

(Secondary Receive)

selected by bits 0—3 of the CSR is ON, provided that

(Asynchronous

the Line En bit for that modem has been set. Indicates

modem definition)

Read only

a remote modem is signaling the local modem on the
reverse channels,

Set to 1 whenever the CS line from the modem selected

(Clear to Send)

by bits 0—3 of the CSR is ON, provided that the Line
En bit for the modem has been set. Indicates the modem
is ready to transmit data. Occursin response to an RS

(LSR bit 2)

3-28

Read only

(

Table 39 (Cont)

Line Status Register Bit Assignments

Bit

Designation

Function

Read/Write

Set to 1 whenever the CO line from the modem selected

(Carrier On)

by bits 0—3 of the CSR is ON, provided that the Line En

(detected)

bit for that modem is present and that the received signal

Read only

is present for demodulation.
07

RING

Set to 1 whenever the RING line from the modem selected

- Read only

by bits 0—3 of the CSR is ON, provided that the Line En
bit for that modem has been set. Indicates a remote modem

is signalling the local modem.

INDIRECTLY ADDRESSABLE (SECOND-

Transmission continues, using the Transmitter Alter-

nate Current Address for this line (secondary register

ARY) REGISTERS

- The secondary reglsters make up the RAM of the

0001), provided that the Transmitter GO bit in the

DV11 and may be accessed by the PDP-11 program

Line State secondary register for this line is still set to

via the SRS and the SAR, as described in Section 3.2.

one.

The PDP-11 program must clear (or properly set up)
all secondary registers before setting SCR 00 (Micro-

processor GO). Because
theRAM is volatile, second- ary register contents must be re-establlshed in the
event of power failure.

3.3.2

Transmitter Principal Byte Count (0001)

The Transmitter Principal Byte Count secondary reg-

ister contains a 15-bit word that is the 2’s complement of the

number of bytes (characters)

remaining to be transmitted on the associated line.

Sixteen secondary registers, summarized in Table 3-1,

The 16th bit (bit 15) is used by the PDP-11 program

are provided for each of the 16 data lines, making a

to enable change of mode and/or BCC transmission,

total of 256 secondary registers. Secondary register

based on reaching a zero byte count during transmis-

formats are shown in Figure 3-4.

sion. When bit 15 is set to zero by the PDP-11 pro-

/m\\‘

gram, bits

13-15 of the Line Progress secondary

NOTE

The Secondary Registers are NOT cleared by

mode when the principal byte count reaches zero;

Imtlallze

also, the BCC will be transmitted if Line Progress bit
10 is set to one. When bit 15 is set to one by the PDP- -

- 3.3.1

Transmitter Principal Current Address (0000)

11 program, bits 00-02 of the Transmitter Mode Bits

The Transmitter Principal Current Address second-

secondary register continue to control the line trans-

-ary register contains the 18-bit core memory address

mission mode. A byte count with bit 15 set to zero (at

of the next character to be transmitted on the associ-

the time the byte count is loaded by the PDP-11 pro-

ated line. The extended address bits are initially

gram) is referred to as a “marked” byte count.

loaded from SCR 04-05 to provide the 18-bit address
capability. This register is incremented by one with

each character transmitted on the associated line by

This register is incremented by one with each charac-

the DV11

ter transmitted on the associated line by the DV11 if

if the principal message table is being used

- (Line State secondary register bit 07 set to zero).

When the transmitteriPrinCipal Byte Count (secondary register 0001) for the same line reaches zero, an
interrupt code is set in the NPR Status register.

the principal message table is being used (Line State
07 set to zero). When this register reaches zero, transmission continues (using the Transmitter Alternate
Byte Count for this line) if the Transmitter GO bit in
- the Line State secondary register is still set to one.

- TRANSMITTER PRINCIPAL BYTE COUNT (00O1)
15

1= NORMAL BYTE COUNT
@=MARKED BYTE COUNT

TRANSMITTER ALTERNATE CURRENT ADDRESS (0010)
00

TRANSMITTER ALTERNATE BYTE COUNT (0011)
00

1= NORMAL BYTE COUNT
@=MARKED BYTE COUNT

RECEIVER CURRENT ADDRESS (0100)

RECEIVER BYTE COUNT (0101)
15

- 00

1= NORMAL BYTE COUNT

2= MARKED BYTE COUNT

TRANSMITTER ACCUMULATED BLOCK CHECK CHARACTER (0110)
15

RECEIVER ACCUMULATED BLOCK CHECK CHARACTER (0111)
15

‘

LEGEND

R=READ ONLY

W=WRITE ONLY
X= UNUSED

% N,Ol FOR ACCESS BY PDP‘—nm_:PR%GRAM.

11-2881

| Figure 3-4 DV11 Secondary Registers (Sheet 1 of 2)

3-30

TRANSMITTER

CONTROL TABLE BASE ADDRESS (1000)

RECEIVER CONTROL TABLE BASE ADDRESS (1001)

LINE PROTOCOL PARAMETERS (1010)
15 -

X
A

;

DLE CHARACTER

DDCMP:

__._.J

2;285

TRANSMIT

STRIP

TYPE

" DDCMP

RECE IVE

LEADING

SYNCS €

MARK
ON BOTH

‘

B.C:
Q@

| LINE STATE (1011)
15

—

NEXT RCV. MODE

EXPECT
.
BCC ON
MARKED RECEIVE

ON MARKED
BYTE COUNT=9Q

SYNC STRIP

B.C.=g

USE ALTERNATE
TABLES

|TRANSMITTER [TRANSMITTER |

NON-EXISTENT|
MEMORY
|

GO
v

TRANSMITTER

UNDERRUN

RECEIVER

ACTIVE
'

RECEIVER

MEMORY

RESYNCHRONIZE

PARITY ERROR

TRANSMITTER MODE BITS (1100)
15

;wr

—

UNUSED

RECEIVER MODE BITS (1101)

MODE

UNUSED

MODE

LINE PROGRESS (1110)
15

1
NEXT TRANSMIT MODE

'ON MARKED
=~
BYTE COUNT =@
|

RECEIVER

07
7

SEND BCC

EXPECT

Rgfxgc

EXPECT

ExPECTED

00
7

SA2
DLE

BCC2 NEXT

/ ./ ./
S

"MARKED TRANSMIT
B.C.z0
,

06
7/

SENDING

PROGRESS

SEND

NEX

BCC2

NEXT"

CCC! NEXT

CONTROL BYTE HOLDING (1111)

UNUSED

RECEIVER CONTROL BYTE

.11-2882

| .Figure 3-4 DVI1l Secondar_y Régisters' (Sheet 2 of 2)

3-31

When the Transmitter Alternate Byte Count (secondary register 0011) for the associated line reaches zero,
an interrupt code is set in the NPR Status register.
Transmission continues using the Transmitter Principal Current Address for this line (secondary register

0001), provided that the Transmitter GO bit in the
Line State secondary register for the same line is still
set to one.

3.3.4

Transmitter Alternate Byte Count (0011)

The Transmitter Alternate Byte Count secondary
register contains a 15-bit word that is the 2’s complement of the number of bytes (characters) remaining to be transmitted on the associated line. The 16th
bit (bit 15) is used by the PDP-11 program to enable
change of mode and/or BCC transmission, based on
reaching a zero byte count during transmission.
When bit 15 is set to zero by the PDP-11 program,

bits 13-15 of the Line Progress secondary register for
- this line will control the transmission mode when the
alternate byte count reaches zero; also, the BCC will
be transmitted if Line Progress bit 10 is set to one.
When bit 15 is set to one
by the PDP-11 program, bits
00-02 of the Transmitter Mode Bits secondary register continue to control the line transmission mode. A
byte count with bit 15 set to zero (at the time that the
byte count is loaded by the PDP-11 program) is
referred to as a ““marked” byte count.

3.3.6

Receiver Byte Count (0101)

The Receiver Byte Count secondary register contains
a 15-bit word that is the 2’s complement of the num-

ber of bytes (characters) remaining to be received on

the associated line. The 16th bit (bit 15) is used by the

PDP-11 program to enable change of mode and/or
BCC anticipation, based on reaching a zero byte

count during reception. When bit 15 is set to zero by
the PDP-11 program, bits 13-15 of the Line State secondary register for this line will control the reception
mode when the byte count reaches zero; also, the
BCC will be expected if Line State bit 10 is set to one.
When bit 15 is set to one by the PDP-11 program, bits

00-02 of the Receiver Mode Bits secondary register
continue to control the line reception mode. A byte
count with bit 15 set to zero (at the time the byte
count is loaded by the PDP-11 program) is referred to
as a “marked” byte count. When this register reaches
zero, an interrupt code is set in the RIC register and
the DVI11 stops transferring received characters to

core memory.
3.3.7

Transmitter Accumulated Block Check

Character (0110)

The Transmitter Accumulated Block Check secondary register contains the continuously-computed
BCC (specified by the Line Protocol Parameters sec-

ondary register) to enable destination stations to

check integrity of transmission on the associated line.
Characters to be included in the block check calcu-

lation are specified by bit 03 of the Transmitter Con-

trol Bytes for each character. The contents of this
register are transmitted as two sequential bytes, low-

order eight bits first (except when LRC-8 is the
selected block check type, in which case a single byte
is transmitted). The DV11 automatically clears this
register to zero after transmitting its contents.

This register is incremented by one with each charac-

NOTE
The DV11 computes CRC-16 and CRC-CCITT on a

ter transmitted on the associated line by the DV11 if
the alternate message table is being used (Line State

length must be eight bits. LRC-8 may be selected for

secondary register bit 07 set to one). When this register reaches zero, transmission continues using the
Transmitter Principal Byte Count for this line if the

Transmitter GO bit in the Line State secondary register is still set to one.

3.3.5

Receiver Current Address (0100)
The Receiver Current Address register contains the

18-bit core memory address for storage of the next
character to be received on the associated line. The
extended address bits are initially loaded from SCR
04-05 to provide the 18-bit address capability. This
register is incremented by one with each character
received on the associated line by the DV11.

byte-at-a-time basis (parallel), thus the character
characters of 5, 6, 7, or 8 bits.

3.3.8

Receiver Accumulated Block Check Character

- (0111)

The Receiver Accumulated Block Check secondary
register contains the continuously-computed BCC
(specified by the Line Protocol Parameters secondary
register) for checking integrity of data received on the

associated line. Characters to be included in the block
check calculation are specified by bit 03 of the
Receiver Control Byte for that character. The PDP11 program should clear this register if the accumu-

lated block check at the end of the message is nonZero.
»

3-32

3.3.3 Transmitter Alternate Current Address (0010)
The Transmitter Alternate Current Address register
has exactly the same function as the Transmitter
Principal Current Address register described in Para~graph 3.3.1. This register is incremented by one with
each character transmitted by the DV11 on the associated line if the alternate message table is being used
(Line State secondary register bit 07 set to one).

3.3.9

Transmitter Control Table Base Address (1000)

determines the receiver control table to be used for
controlling reception on the associated line.

The Transmitter Control Table Base Address secondary register contains the 18-bit address of the trans-

mitter control table for the associated line. The

3.3.15

extended address bits are initially loaded from SCR

04-05 to provide the 18-bit address capability. The

and referenced by the Microprocessor to control and
monitor activities on the associated line in executing

contents of this register are used by the Micro~processor in the computation of the control byte

the selected protocol (these bits are not intended for

addresses for transmitted characters.

3.3.10

Line Progress (1110)

The Line Progress secondary register contains bits set

access by the PDP-11 program). This register also
stores mode change and BCC transmission control

Receiver Control Table Base Address (1001)

bits, as set by the PDP-11 program, for use by the

The Receiver Control Table Base Address secondary

Microprocessor when a marked Transmitter Byte
Count reaches zero, as discussed in Section 3.1. Line

register contains the 18-bit address of the receiver
control table for the associated line. The extended
address bits are initially loaded from SCR 04-05 to

Progress register bit assignments are described in

detail in Table 3-12.

- .,

provide the 18-bit address capability. The contents of
this register are used by the Microprocessor in the

3.3.16

computation of the control byte addresses for the
recetved characters.

The Receiver Control Byte Holding secondary regis-

3.3.11

Receiver Control Byte Holding (1111)

ter provides storage for the Receiver Control Byte in
bits 00-07. The PDP-11 program may set a control

Line Protocol Parameters (1010)

byte into this register while responding to a DV11

The Line Protocol Parameters secondary register
contains the transmitter Data Link Escape (DLE)

receiver special character interrupt. When the PDP-

character when required by the associated line pro-

response

tocol, plus

processor uses the control byte in this register to con-

control

bits to

implement

protocol

requirements and handling of sync characters. The
PDP-11 program writes the data in this register for

program

signals

the

complete

DVI11

(SCR

that its

08=1),

the

interrupt

Micro-

- trol the disposition of the interrupting character in
the RIC register.

reference by the microprogram. Bit assignments are
described in detail in Table 3-10.

33.12 Line State (1011)
The Line State secondary register is used by the PDP11 program and the Microprocessor to control and

specified in the control byte is not altered. The PDP-

tocol. This register is also used by the PDP-11 pro-

11 program should not write this register except during initialization or interrupt response cycles. Receiv-

gram to store mode change and BCC anticipation

bits for reference by the Microprocessor when a
-

only, if an error condition or data block boundary
condition caused the interrupt; the existing mode

monitor line activities in executing the selected pro-

The Microprocessor may also use this register to
write control bytes that specify character discard

er Control Byte format is shown in Figure 3-4.

marked Receiver Byte Count reaches zero, as dis-

cussed
in Section 3.1. Bit assignments are described in
detail in Table 3-11.

If the PDP-11 programmer so desires, the generation
of receiver interrupts may be limited to only those

'33.13 Transmitter Mode Bits (1100)

cases where the PDP-11 program wishes notification

~ The Transmitter Mode Bits secondary register con-

that a particular character has arrived, rather than

tain the 3-bit mode selection field (in bits 00-02)

have the PDP-11 program change the character processing directions specified in the control byte. In these

- which determines the transmitter control table to be
used for controlling transmission on the associated

circumstances, the PDP-11 program may direct that

line.

3.3.14

Receiver Mode Bits (1101)

character processing resume (set SCR 08=1) without
changing the control byte stored in the Receiver Con-

trol Byte Handling register. This is possible because
the control byte is stored with its bit 00 (generate

The Receiver Mode Bits secondary register contains

the 3-bit mode selection field (in bits 00-02) which

interrupt) cleared.

3-33

Table 3-10
Line Protocol Parameters Secondary Register Bit Assignments

Bit(s)
00

Function |

Designation

Read/Write
Read or Write

Idle Mark

of the character currently being loaded into the
transmitter if both prrnc1pal and alternate byte

STATE erl beasserte&d»-on an asynchronous line.
01

Strip Leading Syncs

When set to one, causes sync characters arriving on

Read or Write

- the associated data line after the achievement of
~ synchronization, but before the first non-sync
character, to be stripped from the incoming data
stream (i.e., not stored in the RC Silo). The sync
character(s) with which the receiver achieves
sync are stripped in any case.
Unused

02
03-04

Block Check Type

~Set by the PDP-11 program to specify the type of
block check calculation to be done for transmissions

Read or Write

DDCMP Receive

LRC-8 (XOR)

BCType

CRC-16 (X*® + X!'3 +X2 + 1)

Unused-16

—_

03
_0
= O

and receptions on this line:

CRC-CCITT (X! ¢ +X!2 + X5 + 1

When set to one, inhibits the Microprocessor from
fetching control bytes during character reception on
the associated line if reception mode is 0. Useful for

Read or Write

increasing throughput and reducing core storage
requirements when using DDCMP protocol.
06

DDCMP Transmit

When set to one, inhibits the Microprocessor from

- Read or Write

fetching control bytes during character transmission

on the associated line if transmission mode is O.

Useful for increasing throughput and reducing core
storage requirements when using DDCMP protocol.

08-15

Unused
DLE Character

Contains the Data Link Escape (DLE) character for
the associated line. When a character is to be trans-

mitted and the control byte for that character (as

fetched by the DV11) has bit 01 set to one, the DLE
character is fetched from this register by the Microprocessor and transmitted just prior to the character
being processed.

3-34

Read or Write

Table 3-11

Line State Secondary Register Bit Assignments

Bit(S)

Designation

Receiver Active

Function

Set to one by the Microprocessor when the enabled

receiver for the associated line has detected the

R_ead/Writé
Read

synchronization character(s) for that line. (Receiver
- enabling, done via the Line Control Register, is

discussed in Paragraph 3.2.2.)
01

Receiver

Set to one by the PDP-11 program to effect

Resynchronize

resynchronization during reception or to turn off

Write

reception on the associated line, as described in
Section 3.5. The Microprocessor searches for the

synchronization character(s) for the associated line

if the receiver for the line has been enabled (receiver
enabling is discussed in Paragraph 3.2.2). When the

synchronization character(s) is found, the Microprocessor sets the Receiver Active bit (Line State 00)

to one. If any characters for the associated line are
stored in the RC Silo when this bit is set, they are
discarded (see Line Progress 07 description).

Transmitter Go

Set to one by the PDP-11 program to command the

Read or Write

DV11 to transmit data on the associated line. Set
to zero by the Microprocessor whenever

1. transmitter principal and alternate byte counts
are both equal to zero, or

2. transmitter NXM (Line State 04) sets to one, or

3. transmitter MPE (Line State 05) sets to one.
This bit may be set to zero by the PDP-11 program
to abort transmission.

Transmitter
Underrun
fi? ¥

Set to one by the Microprocessor when a character has

Read or Write

been loaded into the transmitter for the associated

Zero

line and the transmitter has returned a Data Not

¢&o

Available signal. Should be set to zero by the PDP-11

program after it has been read. Indicates that one or
more idling sync characters have been sent by the
transmitter.

CAUTION
In byte count oriented protocols or trans-

parency operation in IBM’s BISYNC, idling
of a sync causes a bad BCC and hence a NAK
from the remote terminal. Thus, the Transmitter Underrun bit indicates whether the
NAK is the result of line errors or idling syncs.

3-35

Table 3-11 (Cont)
Line State Secondary Register Bit Assignments
Bit(s)
04

Read/Write

Function

‘Designation

Transmitter Non-

Set to one by the Microprocessor whenever a non-

Read or Write

Existent Memory (NXM)

existent memory condition is encountered during

Zero

transmission (NPR Status Register interrupt codes
0000, 0010, 1000). The PDP-11 program should

read the NPR Status Register, then clear this bit.

This bit clears Transmitter Go (Line State 02) when
.

set to one.

Transmitter Memory

Parity Error

~Set to one by the Microprocessor whenever a memory

Read or Write

~ parity error is encountered during transmission (NPR
Status Register interrupt code 1000). The PDP-11

Zero

program should read the NPR Status Register, then

clear this bit. This bit clears Transmitter Go (Line

“State 02) when set to one.
06

Sync Strip On

Read only

Set to one by the Microprocessor in response to Strip

Leading Syncs command bit (Line Protocol Parameters
01) from PDP-11 program to the associated line. Causes
- the Microprocessor to strip from the incoming data
stream all sync characters arriving after the achievement
of synchronization, but before the first non-sync charac-

ter. Set to zero by the Microprocessor on arrival of the
first non-sync character.

- 07

Use Alternate Tables

Read or Write

When set tow#gg@by the PDP-11 program or the Micro-

processor, causes the Microprocessor to extract data
for transmission on the associated line from thespinei
walstableszWhen set to one by the PDP-11 program or
the Microprocessor, causes the Microprocessor to

extract the transmit data from the alternate tables. Set

to zero by the Microprocessor when the alternate byte
count is equal to zero. Set to one by the Microprocessor
when the principal byte count is equal to zero.

Unuséd

08-09

Expect BCC

When a marked receiver byte count reaches zero, this
bit is examined by the Microprocessor. If this bit has
“been set to one by the PDP-11 program, the Microprocessor interprets the next received character (in

the case of LRC-8 block check types) or the next two
received characters (in the case of CRC-16 and

CRC-CCITT block check types) as block check

character(s), and passes them through the BCC

calculation logic. The Microprocessor then places the
OR of the high and low bytes of the accumulated BCC
into the RIC register with the line number and interrupt
code 0101. A control byte with bit 04 set to one
(character discard) is written into the Control Byte

secondary register to inhibit storage of the block check
character(s), and SCR 07 is set to one to interrupt the
program.

3-36

Read or Write

Table 3-11 (Cont)

Line State Secondary Register Bit Assignments
Bit(s)

,Designat'ion

Function

Read/Write

Next Receive Mode on

When a marked receiver byte count reaches zero, the

Read or Write

Marked Byte Count =0

Microprocessor transfers these bits to bits 00—02 of

11-12

13-15

Unused

the Receiver Mode Bits secondary register to set the

mode for the next character(s)
to be received.

Table 3-12

Line Progress Secondary Register Bit Assignments

Bit(s)
00

Designation

Serid BCC1 Next

Read/Write

Function

Nttt eiidedefomaccesssbyzthe”RBRsprogram.)

Read

Set to one by the Microprocessor whenever:

1. A marked transmitter byte count has reached
-

zero and bit 10 of this register is set to one.

2. A transmit control byte with bit 03 set to one
has been fetched by the Microprocessor (useful
when an ITB, ETB, or ETX has been

encountered in BISYNC protocol).

Cleared by the Microprocessor if LRC or the first
BCC has been loaded for transmission by the
MicrOprocessor.

Send BCC2 Next

(NotirsteRdet :?orava"@’@e‘ssabr*fi?’“?‘_;?"‘efPlPFlaptogram:)

Read

Set to one by the Microprocessor when LRC or

the first BCC has been loaded for transmission,
but reset to zero again if LRC-8

is selected as the

Block Check Type for the associated llnein Line
Protocol 03—04.

Set to zero by the MicfoPrOcessor when the second
BCC byte (BCC2) has been loaded for transmission
by the Microprocessor..
02

DLE Sending In

(Not

Progress

Set to one by the Microprocessor when it loads a

intended foraccess bythe PDP11 program.)

- Data Link Escape character for transmission on the
associated line in response to a control byte command
bit (01). Cleared by the Microprocessor when the DLE
“has been sent.

03-04

Unused

3-37

Read

Table 3-12 (Cont)

Line Progress" Secondary Register Bit Assignménts
Bit(s)
05

Expect BCCI

Read/Write

Function

Designation

MNeisintendedibomaecessbysthesRBP-1-1-program.)

Read

Set to one by the Microprocessor whenever (1) Line
State bit 11 (Expect BCC) has been set to one by
the PDP-11 program and a marked byte count has

reached zero, or (2) a receive control byte has been
fetched with bit 03 (Expect BCC) set to one. The
next received character is then interpreted as the

first block check character (BCC1) and a BCC calculation is performed. If LRC-8 is the selected block
check type, the Microprocessor

1. places the OR of the high and low bytes of the
-

accumulated BCC into the RIC register with

the line number and interrupt code 0101.
2. writes a control byte with bit 04 (character

discard) set to one, into the Control Byte
secondary register to inhibit storage of the
BCC, and

3. sets SCR 07 to one to interrupt the PDP-11
program.

If either CRC-16 or CRC-CCITT is the selected block
check type (both BCC1 and BCC2 required), the

Microprocessor sets Line Progress 06 (Expect BCC2)
and does not perform steps 1, 2, and 3 untfl after
BCC2is received.

Expect BCC2 Next

(Notintendedffo.r
eSS Ve

Set to one by the throprocessor whenever Line

Progress 05 (Expect BCC1)is set from one to zero

during a character reception cycle and either CRC-16

or CRC-CCITT is the selected block check type. The
next received character is then interpreted as the

second BCC (BCC2), a BCC calculation is performed,
and the Microprocessor proceeds as described in

steps 1, 2, and 3 for Line Progress bit 05.

3-38

Read

Table 3-12 (Cont)

Line Progress Secondary Register Bit Assignments

Bit(s)
07

Designation

Function

Resynchronization

(NetsntendetdforuicvossbysthesPDRpiogia.)

Flag Expected

Set to one
by the Microprocessor whenever a

Read/Write

Read |

- resynchronization cycle starts for the associated
line receiver as commanded by Line State O1.

Cleared by the Microprocessor when all characters
stored in the RC Silo for the associated line have
been removed. This bit inhibits transfer of RC Silo

characters designated for the associated line to the
Unibus until the Resynchronization Flag character

reaches the bottom (output) of the RC Silo.

08—09
10

Unused

Send BCC

When a marked transmitter byte count reaches zero,

Read or Write

this bit is examined by the Microprocessor. If this

bit has been set to one by the PDP-11 program, the
- Microprocessor sets Line Progress 00 (Send BCC1
Next) to one for the associated line. The Micro-

processor then transmits the first block character

(BCC1) after the character which caused this byte
count to go to zero. If either CRC-16 or CRC-CCITT

is the selected protocol, the Microprocessor transmits
the second block check character (BCC2) after
transmission of BCCI.
11-12

13—15 |

Unused

Next Transmit Mode
on Marked Byte

Count =0

When a marked transmitter byte count reaches zero,

Read or Write

- the Microprocessor transfers these bits to bit 00—02

of the Transmitter Mode Bits secondary register to
set the mode for the next character(s) to be trans-

mitted.

3.4

CONTROL BYTE FORMAT

Control byte bit assignments (Table 3-13), are based

The same characters are included in the

BCC for both transmit or receive.

on the structure of the DV 11 interpretation logic, and

are arranged so that the same control bytes can be

If the protocol being executed does not have the

used for both transmission and reception, provided

above characteristics,

that:

transmit and receive may be established by setting

|
1.

The protocol progresses from mode to

mode in a symmetrical fashion for both

transmit and receive, and

separate control tables

for

different values in Receive Control Table Base
Address and Transmit Control Table Base Address
secondary registers. Control byte formats for transmission and reception are shown in Figure 3-2.

Table 3-13

Control Byte Bit Assignments

Function
Bit(s)

Transmitter Control Byte

Receiver Control Byte

Interrupt PDP-11 Program:

Unused (to effect symmetry)

When set to one, causes the DV11 to request a

PDP-11 program interrupt. The DV11 sets the

received character being processed in the

Receiver Interrupt Character Register and

awaits a reset of SCR 08 by the PDP-11 program.

Send Data Lmk Escape Next

When set to one, causes the DV11 to fetch the
Data Link Escape (DLE) character from

Unused (to effect symmetry)

secondary register 1010 for the selected line
and transmit it before transmitting the character being processed.

Send BCC:

When set to one, causes DV11

Expect BCC:

to transmlt the

block check character(s) for the selected line

following transmission of the character being
processed.
|
|

receiving and processing the next received
character as the block check character.

Include Character in BCC:
When set to one, causes the character being

|
Include Character in BCC:
When set to one, causes the character being

“character being accumulated for the selected

character being accumulated for the selected

processed to be included in the block check

line. When set to zero, inhibits inclusion.

When set to one, causes DV11 to set up for

processed to be included in the block check

line. When set to zero, inhibits inclusion.

Discard/Store Character:

Unused (to effect symmetry)

When set to zero, causes the character being
processed to be stored at the receiver current

address in core memory for the selected line.
When set to one, inhibits character storage.

05-07

Next Mode:

be transmitted on the selected line. Bit 0S5 is

Specifies the mode for the next character to
be received on the selected line. Bit 05 is the

the least significant bit.

least significant bit.

Specifies the mode for the next character to

3-40

3.5

DVI11 INITIALIZATION

LCR 10 and 13 are implemented
for synchronous reception on a line. When oper-

DVI11 initialization consists of setting up the DV11

line modems and the DV11 Data Transfer Section.
3.5.1

~ ating on an asynchronous line, character

format and baud rate must be set up at

Line Modem Set-Up

Initialization for the line modems consists of setting
the line number for the modem to be enabledin CSR
00-03. CSR 06 (Interrupt Enable) may also be set to

this time.
Followingis an 111ustrat1ve procedure to setup a line

for transmission:

one at this time
to select the interrupt mode. The Line

Enable bit (LSR 00) is then set to one to complete the
injtialization process for the selected line. The process

1s repeated for each line that is to be enabled.

appropriate principal and alternate secondary registers, setting bit 15 of the byte

CSR and LSR are cleared at bus initialization time.

counts to zero if marked byte counts are

Setting CSR 10 and 11 (Clear Mux and Clear Scan)

required
by the protocol.

each to one is equivalent to bus initialization, except

that the Terminal Ready bits (LSR 01) for each line
are also cleared by Clear Mux. If a Clear Scan

issued, the PDP-11 program must wait for the MCU

Parameters secondary register.

(CSR 04) to return to zero before
sending additional command bits.

DVI11 Data Transfer Setup

protocol.

lines must be cleared. Then set Microprocessor GO
(SCR 00). The Microprocessor will now loop in an

Set bit 07 of Line State secondary register

idle mode. The first word to SCR may also contain

to one if transmission is to start from the

the extended address bits (SCR 04-05) and 1nterrupt

alternate tables.

enables (SCR 06, 12, 13), as required.

| Following is an illustrative procedure to setup a line
for data reception:

Initialize transmitter mode
to non-zero in
Transmitter Mode Bits secondary register

er bits in this register as required by the

Clear (SCR 11), then the secondary registers for all

If the data link is established on the
selected line, set bit 02 of Line State sec-

- ondary register to one to start the transmitter for the line.

Set the receiver control table core memory |
address and the byte count in the appro-

If the line is asynchronous, the character
format and baud rate in the Line Control

priate secondary registers.

Set the required protocol control bits in

State bit 02.

the Line Protocol Parameters secondary
register.
3.

(1100) if required by the protocol; set oth-

The primary registers should be cleared by a Master |

Set the required protocol control bits and
the DLE character in the Line Protocol

Busy Indicator

3.5.2

Set the transmitter control table core
memory addresses and byte counts in the

3.6

Initialize receiver mode to non-zero in
Receiver Mode Bits secondary register

DATA TRANSFER IMPLEMENTATION

With the DV11 initialized as discussed in Section 3.5,

calls to or from remote modems may be originated or

(1101) if required by the receiver protocol

answered and DV11

data transfers started by the
PDP-11 program. The data transfer process or pro-

implementation logic.

tocol is controlled by the contents of the control bytes

When the data link is established on the

and by the service routines for the DV11 interrupts.

selected line (Paragraph 3.5.1), set LRC
13 and 15 to one to cause the line to sync

This section contains descriptions of call origination

up and start receiving characters. Set LRC

reception; termination of transmission and reception;

and answering procedures; resynchronization during

10 to one at the same time if sync character(s) B is to be selected.
|

and suggested programming methods for implementing BISYNC and DDCMP protocols.

3-41

3.6.1

Originating and Answering Calls

PDP-11 program waits on Data Set
Ready (DSR) transition (CSR 12) and the
Carrier On (CO) transition (CSR 14) from

The Control Status Register (CSR) and the Line Status Register (LSR) are provided to enable the PDP-11
program to originate and answer calls to/from

the enabled modem.

remote modems. Initially, the local modem is enabled

and the operating mode (interrupt or non-interrupt)
is set, as described in Paragraph 3.5.1. An inter-

gram starts the DV11 Data Handling Section and initiates data transfers.

~ change then takes place between the PDP-11 program and the MCU to originate a call, as follows:

PDP-11 program sends Data Terminal

PDP-11 program dials remote number via
DN11 Automatic Dialing Unit, or an

When CO is detected, the PDP-11 pro-

3.6.2

Resynchronization During Reception

If line synchronization initially fails or is lost, the
PDP-11 program can command resynchronization
during reception by setting bit 01 of Line State secondary register to one. The DV11 then

Ready (LSR 01) to cause enabled modem
to hold the line once the call is established.

defines a “Resync Flag Expected interval”
(Line Progress secondary register bit 07
set to one), during which any receiver
~characters for this line already buffered in
- the DVI11 are discarded
»

clears the Resync Command bit (Line
State 01) and Receiver Active (Line State

operator manually initiates a call to the

remote modem. When the call has been

established, the DN11 will hold the line
via the Call Request line and Data Terminal Ready. In the manual dialing case, the
operator switches to “Data Mode” and

00), and

Data Terminal Ready holds the call.

searches for the synchronization
character.

PDP-11

program waits on Data Set

Ready (DSR) transition from the enabled

DVI11 sets the Receiver Active bit to one to enable

receipt and storage of subsequent characters on the

resynchronized line. The program should not request
resynchronization again until at least one character
has been received since the previous resynchronization request.

When DSR is detected, the PDP-11 pro-

3.6.3

gram sends a Request to Send (LSR 02) to
set the data mode for transmission.

Termination of Transmission and Reception

The DV11 terminates transmission on a line whenever both principal and alternate byte counts have
reached zero, or a non-existent memory or memory
parity error condition is encountered. The DV11 sets
Transmitter GO (Line State secondary register bit 02)
to zero to terminate transmission. The PDP-11 program may set Transmitter GO to zero to abort
transmission.
|

PDP-I_l program waits on Carrier On

(CO) and Clear to Send (CS) transitions
(CSR 14 and 13) from the enabled

When the synchronization character is found, the

“modem (CSR 12). If the MCU is operating in the non-interrupt mode with only
one line enabled (as reflected by the contents of CSR 00-03) LSR 04 may be readily used to monitor the DSR line.

modem.

WhenCO and CS are detected, the PDP-

11 program starts the DV11 Data Handling Section and initiates data transfer.

The PDP-11 program shuts down reccption on a line
by clearing Receiver Enable (LCR 13) and setting
Line State secondary register bit 01 (Receiver Resynchronize) to one. The DV11 then

Answering a call consists of the PDP-11 program

detecting the Ring transition from the enabled mod-

em (CSR 15), then

clears the ‘Resync Command bit (Line

State 01) and the Receiver Active bit (Line
State 00), and

PDP-11 program sends Data Terminal

Ready (LSR 01) to cause enabled modem
to answer the call.

3-42

discards any receiver characters already
accumulated for the line.

3.6.4

BISYNC Implementation
BISYNC implementation software is considered in

three functional groups:

be loaded with the base addresses and byte counts for

data buffers one and two, respectively. On each zero

control tables, interrupt
service routines, and the protocol module.

byte count interrupt, the next buffer address would
be loaded into the appropriate registers.

The control tables contain the control bytes, which control sequencing between modes and accumulation

For non-transparent data, the DV11 is initialized to
Mode 3 for transmission of any header data (see Fig-

of the BCC. During transmission, the control bytes
also control DLE stuffing and BCC transmission.
Add1t1onally, during reception, the control bytes

enable discard of unwanted characters and reception

of this BCC.

‘The interrupt service routines respond to zero byte

ure D-3) or the ENQ control character. ITB, ETB,

ETX characters are included in the BCC and followed by the BCC in Mode 3. The DV11 is switched
to Mode 4, the text transmission mode, on occur-

rence of the STX or ITB delimiters. Occurrence of a
zero byte count causes a return to Mode 3 to send the
next data block.

count and error interrupts, and, during reception,

respond to special character interrupts.

Table 3-15 shows the transmission sequence and the

The protocol module initializes the DV 11, establishes

direction of transfer, sets up and manages the data
buffers, and handles error and special character flags
set by interrupt service routines. Handling of error

flags may take the form of try-again routines, or

operator notification. Handling of special characters

may require such operations as a switch from receive
to transmit, or termination and disconnect (i.e., EOT

control byte directives for a block of non-transparent
data that is separated into two intermediate blocks.
3.6.4.2

Reception Control - Figure 3-6 is a state flow

chart for the BISYNC reception control process.
Four states or modes are required: Modes 0 and 2 are
used to handle non-transparent data, Modes 3 and 4

are used to handle transparent data.

received).

| 3.6.4.1

Transmission Control - Figure 3-5 shows

state flowcharts for the BISYNC transmission con-

trol process. There are five states or modes: three for
transparent data transmission,

and two for non-

transparent data transmission.

For transparent data, the DV11 mode is initialized to

Mode 0, causing the DV11 to stuff a DLE in front of
any ACK, RVI, or WACK control characters sent by
the PDP-11. The DV11 also stuffs a DLE in front of
the first STX sent by the PDP-11 and switches to

Mode 1, the transparent data transmission mode.
stays in Mode 1 until a marked byte count

The DV11

reaches zero (see Section 3.3), and is then switched to

for Message)

The DV11 is initialized to Mode 0, and the address
and byte count registers in the DV
11 are set to receive
one byte. Response to the initial control character18

as follows:

"ENQ - the character is stored to record the

request, an interrupt is generated to turn the

buffer contents over to the protocol module for
printout or other handling, and a new buffer is
requested to store the expected data. The data is

input in Mode 0 (no mode change).

DLE - discard the character and go to Mode 1
(transition to transparent reception).

Mode 2, the end-of-transparent block mode.

STX or SOH - store the character and go to

In Mode 2, transmission of the ITB sequence (ITB
DLE STX) causes a return to Mode 1 for transmis-

Mode 2 (non-transparent data reception).

sion of the remainder of the data block. Transmission
of an ETB or ETX character causes a return to Mode

EOT
- store the character, generate an interrupt

to turn buffer contents over to protocol module

O to enable transmission of the next data block.

for termination of reception; stay in Mode O.

Table 3-14 shows the transmission sequence and the

NACK - store the negative acknowledgement

control byte directives for a block of transparent data

character, generate interrupt to turn buffer con-

that is separated into two intermediate blocks. The
DV11

Mode
0 (Waiting

‘tents over to protocol module for resumption of

principal and alternate registers would initially

transmission; stay in Mode 0.

3-43

NONTRANSPARENT

TYPE OF

TRANSPARENT

DATA REQUIRED

I
0

INITIAL

INITIAL NON-

TRANSPARENT

- TRANSMISSION

TRANSMISSION

NON-

TRANSPARENT

'TRANSPARENT

DATA

TEXT TRANS-

TRANSMISSION

MISSION

END OF TRANSPARENT BLOCK

YES

ETB/ETX

11-2949

Figure 3-5

BISYNC Transmission Flow Diagram

3-44

Table 3-14
Transparent Data Transmission Control

Data Buffer

Control Byte Directives

Mode

Send BCC After
This Character?

INCL. CHAR. IN BCC?

Contents

STX

YES

—

—~

CHAR. 1

—

YES

CHAR. N**

(2)*

—

- YES

A DLE?

‘No.

-2

Current

Stuff

ITB

—

YES

DLE

—

YES

STX

—

YES

CHAR. 1

—

YES

CHAR. N**

(2)*

YES

ETX/ETB

YES

*On Byte Count Zero Interrupt — Not Control Byte Directive
**If Char. is a DLE, Stuff a DLE

Table 3-15
Non-Transparent Data Transmission 'Control Data Buffer

Control Byte Directives

Mode

Contents

STX

—

CHAR. 1

—

YES

CHAR. N

(3)*

—

YES

ITB

YES

'YES

CHAR.1

—

YES

CHAR. N

(3)*

—

YES

ETX/ETB

—

YES

Current

Send BCC After

No.

This Character?

*On Byte Count Zero Interrupt — Not Control Byte Directive

3-45

INCL. CHAR. IN BCC?

WAITING FOR
MESSAGE

‘

TRANSITION TO

STX

TRANSPARENT
RECEPTION

YES

TRANSPARENT

DATA

TRANSPARENT

‘

RECEPTION

DATA RECEPTION

YES

YES
~

TRANSPARENT

ETB*/ETX*

CONTROL
CHARACTER
RECEPTION

STX/SYN/DLE/

ITB*

*RECEIVED THE BCC
YES

ETB*/ETX*

11-2950 -

Figure 3-6

BISYNC Reception Flow Diagram

3-46

Mede 1 (Transition to Transparent Reception)

generated, the buffer contents are turned over to the

In this mode, the system initializes for the reception

protocol module, and address and byte counts are set

of transparent text. Mode 1 is entered only from
Mode 0 following reception of a DLE. An STX is

to receive the 2-byte BCC.

expected; if one is received, it is discarded (an inter-

Mode 4 responds to other control characters as

rupt is generated to set the Transparent Data flag),

follows:

and Mode 3 is set.

DLE - store the character 1ncludein the BCC,
If a positive

return to Mode 2.

acknowledgement character (ACK,

WACK, RVI) is received, an interrupt is generated to
turn the buffer contents over to the protocol module
for resumption of transmission,
and the DVII1 is
returned to Mode 0. Receipt of the ENQ repeat
request causes an interrupt to set an Error flag and
~ turn buffer contents over to the protocol module.

STX - discard, include in BCC, return to Mode
3.

ENQ - interrupt, store the character, set Error
flag, return to Mode 0.

SYN - discard, return to Mode 3.

~ All other received characters are stored, an interrupt

is generated and the DVll is returned to Mode 0.

All Other Characters - ’store-,‘ include in BCC,
return to mode 3.

Mede 2 (Non-Transparent Data Reception)

The system receives non-transparent text (including

Mode 5 (TranSparent Intermediate Data Reception)

header, if sent) in this mode. All characters are stored
and included in the BCC, except as follows:

SYN - discard

| _' ITB - store the character, include in BCC and

‘

DLE - discard, include in BCC, 20 to mode
4. |

receive BCC next. Interrupt, turn buffer con- tents over to protocol module.

All Other Characters - Interrupt, ‘store »re‘t'urnv

ETB or ETX - store the character, include in
BCC and receive BCC next. Set End-of-Block
flag and turn buffer over to protocol module.

buffer to the protocol module with errors. Go

to mode 0.

Go to Mode
0.

3.6.5

DDCMP Implementation

The method suggested for DDCMP implementation

ENQ - discard the character and set error flag.

uses a single control table for both send and receive.

Interrupt and turn buffer over to protocol mod-

Buffers are configured so that the only interrupts

ule. Return to Mode 0.

required are those resulting from zero byte counts.

SYN - discard.

format.

Moede 3 (Transparent Data Reception)
Transparent text is receivedin this mode. All characters except DLE are sorted and includedin the BCC.

Reference Figure D-4 for DDCMP data message

3.6.5.1

Transmission Control - Figure 3-7 is a flow

chart for the DDCMP transmission process. Initially,
the DV11 principal transmit registers are set with the

A DLE, if received, is discarded, and Mode 4 (Trans-

base address and byte count of the data buffer con-

parent Control Character Reception) is set.

taining the header, with bit 15 of the byte count set to

Mede 4 (Transparent Control Character Reception)

time (reference Paragraph 3.1.4.2).

‘zero, to cause BCC transmission at zero byte count

Control characters received in the transparent data
stream are processed in this mode. The usual control
characters would be the block delimiters, ITB, ETB,
- or ETX; these are included in the BCC, which is
received immediately after them. The ITB is stored

~and requires a change to Mode 5 to strip syncs and
then to get the rest of the data block. ETB or ETX is
stored and return to Mode 0 is made. An interrupt is

Ifa numbered (data) message or bootstrap message is

being sent, set the alternate transmit registers with the
base address and byte count of the first data buffer
containing the actual data. When setting up to transmit the last data buffer, set bit 15 of the byte count to
zero to cause BCC transmission at zero byte count
time.

3-47

3.6.5.2

Reception Control - Figure 3-8 is a flow

chart for the DDCMP reception process. Initially,
the DV11 receive registers
are set to receive the Six
bytes of the incoming DDCMP header and bit 15 of
the byte count register is cleared to dlrect reception of
1.

SET PRINCIPAL

XMIT REGS

the BCC.

The first characterin the first bufferis now examined
to determine message type. Ifitis a numbered data
message (SOH character) or a bootstrap message
(DLE character), the character count in buffer words
two and three is used to build a receive buffer of
approprlate size. If it is an unnumbered control message (ENQ character) no add1t10na1 bufferlng is

WITH HEADER
BUFFER AD-

DRESS & B.C.

2, SETBITTO
SEND BCC

WHEN B.C.=0

required.

DATA OR

BOOTSTRAP

When the DVl mterrupts to signal BCC receptlon

MESSAGE

complete, set the DV11 receive registers to input the
data to the receive buffer that has just been built, if
any. On the next mterrupt return control to the call-

YES
GET NEXT

BUFFER

“LAST .

BUFFER

ing program.

SEND
BUFFER

The BCC is checked at the points indicated in Figure
3-8. The BCC Received interrupt occurs as a result of
a control byte directive or a marked byte count reaching zero. The BCC characters are included in the
BCC. The accumulated BCC, if correct, should be

. SEND BUFFER

2. SETBITTO
SEND BCC

ZE€ro,

WHEN B.C.=0

C neumn )
.11-2951

Figure 3-7 DDCMP Transmission Flow Diagram

3-48

SET TO RECEIVE
FIRST 3BYTES

DV11 INTERRUPT

¢— — —

SET TO RECEIVE

SECOND 3 BYTES

BOOTSTRAP (DLE)

OR DATA (SOH)

TYPE OF

CONTROL (ENQ)

MESSAGE
h — —

GET CHARACTER

DV11

INTERRUPT

CHECK BCC

COUNT AND
BUILD RECEIVE
BUFFER

¢— — — DV11 INTERRUPT

(

1. CHECK

RETURN )

HEADER BCC

2. SETDV11 TO
RECEIVE

MESSAGE

C RETURN )
11-2952

Figure 3-8 DDCMP Reception Flow Diagram

3-49

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4.2.1

Timing of the scanning process for each line is con-

Modem Enabling and Control

trolled by the Ring Counter, a 4-bit shift register connected in a self-clocking configuration. The Ring
Counter starts when CSR 05 (Scan Enable) is set to
one by the PDP-11 program. The process for each
line, shown in the timing diagram in Figure 4-3, is as

Line or modem enabling is accomplished as follows:
1.

The line number is set in the Line Counter
(CSR 00-03) by the PDP-11 program:

The PDP-11 program then sets the Line
Enable bit (LSR 00).

follows:

The Line Enable fans out to 16 flip-flops, one for
each line. The Line Counter output (drawing D9) is
decoded to generate a clock signal, which strobes the
Line Enable bit into the selected flip-flop. LSR 01-03
modem control bits (TERM RDY, RS, NS) may be

4.%.2

. The line counter is incremented to (1)

address the location in Scan Memory corresponding to the next sequential modem
and (2)

select the

sequential

modem.

set for each line similarly.

Modem Selection and Scanning

The contents of the addressed location are
loaded into the Hold Register.

Once the Line Enable flip-flop for a modem has been
set, the modem may be selected by setting the corresponding line number into the Line Counter. The
PDP-11 program selects modems in order to send
control signals (NS, RS, TERM RDY) or to sample
status bits (DSR, CS, CO, RING) or status bit transitions. The control signal NS and status bit DSR are
replaced by SEC TX and SEC RX respectively when
the line number corresponds to an asynchronous line.
The Line Counter may be loaded directly from the
Unibus or stepped via MCU controls to enable

The contents of the status lines from the
selected modem are then loaded into the
addressed location in Scan Memory.

The new contents of the addressed location are compared with the previous contents (as stored in the Hold Register) by
the Transition Detector. If a change is
detected and the Line Enable bit for the

selected modem has been set in LSR 00,

scanning of the status lines from the modems in end-

the Done flip-flop (CSR 07) is set, serving
to halt the Ring Counter and if CSR 06 is
set, to interrupt the PDP-11 program.
(Operation of the Transition Detector is

around fashion. During the scanning process, modem
status transitions are detected by storing the conditions of the several modems’ status lines in Scan
Memory, a 4 X 16 random access store, then continuously comparing the updated status conditions with
the previous status conditions as modem scanning

Done must be reset to enable resumption of the

proceeds.

scanning process.

shown in Figure 4-3.)

EXCLUSIVE OR GATES.

CLOCK(P|N6)|1||||||||||||||||
DONE+ SCAN EN (PIN 3) _]

R& (PINS) LINE INCR H)

.
3

{

RAM

CONTENTSW

INCREMENT LINE

8571 RING

CTR

CTR,(M7808

BOARD E48

MODULE )

TRANSITION
DETECTEDH

WRITE NEW STATUS BITS

FOR THIS LINE TO SCAN MEMORY

R1 (PIN7) (LD HOLD H)

—

|
TRANSITION DETECTOR LOGIC:
An exciusive OR condition produces an
assertion at one of the input pins to ESS,
causing an assertion at E59 pin 11.

SET HOLD REG. WITH
PREVIOUS STATUS BITS
FOR THIS LINE

R3 (PIN 1)INTR TEST H)

RAM OUTPUT DATA

HOLD REG.DATA == == == o —— otv o o oo o

s em e

e o

e e f e

TRANS DET H
ONE LINE /MODEM

PROCESSING INTERVAL

Figure 4-3

TRANSITION

DETECTED

11-2899

Modem Scan Timing Block Diagram

4.2.3

Unibus Interface

PDP-11

interrupt

control,

selection,

has

completed

its

signaled DV11 to proceed
5.

ing paths and directions for LSR and CSR bits
between the MCU and the Unibus have been

Receive flag set

indicated in Figure 4-2.

Received character waiting in Received

~ Character Silo.
If one of the four data reception conditions (con-

DV11 MICROPROGRAM

nectors

Figure 4-4 shows the Idle or “Executive” Loop of the

6) is present,

the microprogram

branches to the appropriate entry point of the Data

DVI11 microprogram. Numbered connectors have
been included to link Figure 4-4 with the flowcharts

Reception routine (Figure 4-5) to handle the condition; similarly, if one of the two data transmission

for data reception and data transmission in Figure 4-

conditions (connectors 2, 3) are present, the micro-

5 and 4-6, respectively. When the Idle Loop is entered

program branches to the appropriate entry point of

at DV11 start time, or re-entered from elsewhere in

the Data Transmission routine (Figure 4-6).

the microprogram,

the Master Scanner is
incremented to select the next data line and the
microprogram checks for the following conditions in

DV11 instructions are described in detail in Section

4.7 and shown in summary form in Figure 4-8. Note

from Figure 4-8 that the op code is in bits 12-14 and

sequence:

Resynchronization requested

Transmit Go flag set

program

response to a receiver interrupt and has

selection of register transfer direction are accomplished in the MCU Unibus Interface. The exact gat-

4.3

PDP-11

and

that the destination address for branch instructions is
contained in bits 0-7, plus bit 15.

Table 4-1 is a binary microprogram listing for the

Idle Loop. Note that the loop occupies the first 10

Transmit flag set

locations of the ROM.

Table 4-1

Idle Loop Microprogram Listing

Location

Contents
15— | —8

| —4

Instruction

Comments

| —-0

0000

| 0101 | 0000 | 0100 | 0010

0001

0011

OOOO

0101 | 0100

~ XFR

Move master scan to RAM Address register

0010

10010 | OOOO

0000 | 1011

RAM

Fetch Line State contents

| 0010 | 1110

BRB

Branch on RESYNC Bit

1010

BRB

Branch on Transmitter Go Flag

1110 | 0100

- BRA

Branch on Transmit Flag

0011

0100

0111

| 0001

0111 | 0010 | 0011

S/C

Increment Scanner

0101

0000

0110

0000 | 0101 | 0010 | 1001

BRA » ‘

Branch on Interrupt Response

01.1 1

0000 { 0100 | 0000 | 1010

BRA

Branch on Receive Flag

1000 |

0000 | 0011 | 0100 { 0011

BRA

Branch on Reéeived_ Character in RC Silo

1001

0000 { 0001 | 0000 | 0000

BRA

Loop back to 0000

0010

4-7

RE-ENTER

START

NOTE

THIS FLOWCHART IS AN EXAMPLE ONLY.
THE ACTUAL ROM PROGRAM MAY TEST

THE SAME POINTS IN A DIFFERENT ORDER.

INCREMENT
MASTER

SCANNER

RESYNC

DATA RECEPTION
ROUTINE (FIG. 4-5)

RESYNC

REQUESTED

LINE

(LINE
STATE 01)

ENABLE

TRANSMITTER

DATA TRANSMISSION
ROUTINE (FIG. 4-6)

FETCH CONTROL

TRANSMITTER

BYTE & SEND

FLAG

NEXT CHAR.

HANDLE

INTERRUPT

RECEIVER

PROCEED

"INTERRUPT

(SCR 08 = 1)

:
RECEIVER

CHARACTER

YES

STORE CHAR.

RECEIVED
CHARACTER

DATA RECEPTION

ROUTINE (FIG. 4-5)

IN RC SILO

FLAG

YES

FETCH CONTROL
BYTEAND

WAITING IN

STORE CHAR.

. RCSILO

IN CORE

NOTE:

This flowchart is an example only.
The actual ROM program may test
the same points in a different order.
11-2880

Figure 4-4

Microprogram Executive Flow Diagram

4-8

PDP-11 PROGRAM

GET CONTROL

INTERRUPT

BYTE AND

RESPONSE IS

STORE

COMPLETE

CHARACTER
NPR

STATUS SILO

CLEAR

SCR 10

YES | CLEAR RESYNC

RESYNC FLAG

EXPECTED

DISCARD

FLAG

CHARACTER

EXPECTED BIT

PARITY

CHAR.TO

ERROR OR

RIC

ves

[ CLEAR EXPECT
BCC2 BIT

INCLUDE CHAR.

1. CLEAR EXPECT

YES

BCC1 BIT
2. SET EXPECT

CC2BIT

3. INCLUDE CHAR,
BCC

ACCUMULATED

BCC BYTES TO _4

BIT

EXPECT BCC2

YES

1. FORM DISCARD

LOGICAL OR OF

CLEAR

COUNT

“ONLY"” CONTROL

BYTE, STORE IN

—

2.SCR 07=1

CHARACTER
TORIC

C.B.

{IN ALU) SAYS

YES

TORI

CLEAR

1. CHARACTER

REQUEST

2.CONTROL BYTE

INTERRUPT

FROM C.8.

BCC

SET

YES

c.B.
SAYS EXPECT

EXPECT
BCC1

CLEAR ALU

RESULT
REGISTER

CHAR.TO RIC

SAYS INCLUDE

INTERRUPT

CHAR. IN

THIS A MARKED
B.C.

CODE TO RIC

WRITE NEXT
RECVR MODE TO

CHAR. TO RIC

C.B.

RECVR. C.B.

SAYS DISCARD

REG. IN RAM

CHARACTER

INTERRUPT

CODE TO RIC

BCC
EXPECTED

DO NPR TO

STORE

CONTROL

CHARACTER

BYTE IN RAM

J
RCSILO TO RIC
INTERRUPT

GET

CODE TO RIC

CONTROL BYTE

SET SILO OUT

FROM RAM

BC.+1

-B.C.

C.A+1—~C.A.

UPDATE

vES

FROM DATO
INTERRUPT

CODE TO RIC
SET SILO OUT

)

RESYNC

CHAR. TO RIC

B.C. =0

GETNEWB.C.

RECEIVER

MODE BITS

STORE CHARACTER

IN RCSILO

RECEIVER

1. CLEAR RESYNC

ACTIVE

REQUEST
2.CLEAR RCVR

ACTIVE FLAG

1.SET RESYNC
FLAG EXPECTED
2. SET RESYNC

{THIS IS

PULSE

SYNC)
SET RECEIVER
ACTIVE
SET SYNC

YES

LEADING
SYNCS TO BE
STRIPPED

STRIP ON

SET

:(E:%E\I/‘E/ER

STRIP ON

1. CLEAR FLAGS

2. STORE CHARACTER IN RC

SILO

FLAGS

ALPHABETICAL CONNECTOR
IS INTRA-PAGE. NUMERICAL

CONNECTORS CORRESPOND
TO FIGURE 4-4.

11-2926

Figure 4-5

Data Reception Flow Diagram

4-9

FETCH CONTROL BYTE AND

ENABLE TRANSMITTER

SEND NEXT CHARACTER

CLEAR TMARK

YES

BIT FOR THIS

SEND

LRC
PROTOCOL

BCCY

INHIBIT
cc2

LINE

SET UP TO
YES

SEND BCC2

"SEND

NEXT CYCLE

accz

YES

1-~SCR 10 JL
_[

TRANSMITTER

SET

TMARK BIT

( 5

IDLE
MARK

YES
ALTERNATE

TABLES

YES

SET UP FOR

SET INTERRUPT
ENTRY IN NSR

PRINCIPAL
TABLES

ALT. BC = 0
)

NEXT CYCLE

SET UP FOR

YES

PRINCIPAL

SET

ALTERNATE

.BC=0

GET

ENTRY

TABLES

NEXT CYCLE

NSR

PRINCIPAL

GET

PRINCIPAL

ALTERNATE

CURRENT

CLEAR BC MARK

PROGRESS 00-15

ADDRESS

GET LINE

SET NEXT MODE

FETCH NEXT

CHARACTER

SET UP TO

TO DATI

N ace

ACCUMULATE

COMMAND

CHAR. IN

SEND BCC1
NEXT CYCLE

BCC
SET ERROR FLAG
CLR XMTR GO

YES

DNA
FLAG

SET

TRANSMITTER
UNDERRUN
FLAG

TRANSMITTER
Go

I
SEND CHARACTER
COMPUTE

CONTROL

BYTE
ADDRESS

PRINCIPAL/
ALTERNATE

sump
ALTERNATE
BC AND CA

NXM/MPE

C.B. TOALU

BUMP

‘

PRINCIPAL

ALTERNATE

8C=

BC AND CA

C.B.SAYS
SEND DLE

PRINCIPAL
B

NEW MODE
TO RAM

SETUP TO
SEND BCC1

NEXT CYCLE

YES

C.B.'SAYS
SEND BCC

1. SET DLE BEING

SENT BIT

2. SEND DLE

NOTE:

NUMERICAL CONNECTORS CORRESPOND
TO FIG. 4- 4.

ALPHABETICAL CONNECTORS

ARE INTRA-PAGE

11-2925

Figure 4-6

Data Transmission Flow Diagram

The first instruction is a Set/Clear (op code 101),
which

advances

the

Master

Scanner

The fifth instruction is also a Branch Instruction B.

5-stage

Instructions six through ten are Branch Instruction A

counter shown on D3-4) to the next sequential line -

types (op code 000) and operate similarly to Branch

number (line no.

Instruction B. The tenth instruction is an uncon-

1 at start time). The code that

directs the Set/Clear pulse to increment the Master

ditional branch, effected by tying the associated test

Scanner is 01000010, set in bits 0-7. The incrementing

point to a logical one.

pulse is generated at Data Strobe L time (D3-3).
4.4 DATA RECEPTION

The second instruction is a Data Transfer (op code

The data receptlon sequence for a data line is as

011), which gates the updated line number from the
Master Scanner to RAM Address Register. The 0101

follows:

source code in bits 4-7 selects the Master Scanner as

The

source by gatmg the Master Scan bits to the Transfer
Bus.
,

synchronization

character(s)

detected and the line active condition is
set.

| Thé 0100 destiriation code in bits 0-3 is decoded in

D3-6 to generate a RAM Address Register 0-3 Clock
L pulse at 02 time, which is used to load the 4-bit
RAM Address register in D3-8 with the line number

Each character received is input to the RC
Silo.

The control byte for the character
is fetched from core memory and interpreted

from the Transfer Bus.

to command character disposition; then

The third instruction is a RAM operation (op code
010), which reads the contents of the Line State sec-

If the character is not an interrupt charac-

ondary register for the selected line to the RAM Out-

ter or a BCC, it is stored at the current

put Data register. Bits 0-3 of the RAM address come

address in core memory, or

from the line number, as described in the previous

paragraph. Bits 4-7 of the RAM address come from

Ifitis an interrupt or block check charac-

bits 0-3 of the instruction. The Instruction Decoder

ter, it receives special handling.

Enable L signal from the Unibus/Transfer Bus Interlock is negated during the microinstruction cycle,

The flowchart for the Data Reception routine is

enabling the ROM data bits 0-3 and the stored line

shown in Figure 4-5. The connector numbers shown

number bits to be gated to the appropriate RAM

correspond to the Idle Loop connector numbers Fig-

Address selection lines (D3-8).

ure 4-4.

The 010 op code is decoded by E83 on D3-2 to pro-

The data reception sequence will now be described in

duce a RAM Operation L signal, which is ANDed on

detail.

D3-6 with the zero state of the read/write bit (bit 08
of the instruction) to generate a RAM Output Data

4.4.1

Clock L pulse. This pulse clocks the contents of the

Character(s)

Responding

the

Synchronization

accessed RAM location into the RAM Output Data

Depending on the setting of the Sync Requirement

switch for the line (Table 2-5), either one or two sync
characters

will

required

achieve

synchro-

nization. If synchronization is selected
to occur on

The fourth instruction is a Branch Instruction B (op
code 111), which tests bit 01 of the Line State con-

one sync character, the synchronous receiver returns

tents in the RAM Output Data Register. The test

nals when the sync character is detected in the serial

point selection code contained in bits 8-11 of the

input bit stream. If synchronization is selected to

Receiver Flag L (D1-5) and Match Detect (D3-2) sig-

instruction selects RAM output bit 01 in D3-2 (E52).

occur

two

successive syncs,

the synchronous

If bit 01 is true, a Branch Point True H pulse is gener-

receiver does not return Receiver Flag L until the

ated at 02 time, causing the ROM Address register
(D3-1) to be loaded with the branch address contain-

character immediately following the first sync character is received. If that character is also a sync, Match

ed in bits 0-7 and 15 of the instruction.

Detect is also asserted.

4-11

For

synchronization

Data Reception routine (Figure 4-5), to fetch the con-

occurs when Receiver Enable (Line Control Primary

asynchronous

receiver,

trol byte from core memory for the character. When

the control byte has been fetched, it is stored in the

13) is asserted.

Receiver Flag L and

Match Detect signals are simulated by the receiver

Receiver Control Byte Holding secondary register for

logic prior to presentation of the first character to the

reference by the PDP-11 program in the event of an

RC Silo.

interrupt. If the interrupt occurred as a result of the
Interrupt bit being set in the fetched control byte, this

Receiver Flag L generates Receiver Flag Waiting if

bit is cleared from the stored control byte to prevent

the RC Silo is not full, causing the microprogram to

an extraneous interrupt from occurring when the

enter the Data Reception routine at entry point five.

microprogram re-enters the Data Reception routine

Provided that the receiver is not already active, the

at point four following completion of the PDP-11

microprogram will branch on Match Detect true to

program’s response to the control byte interrupt.

set Line State bit zero to one (receiver active condi-

tion). If Match Detect is false (possible only when

If an interrupt request is set (SCR 07=1) as a result of

two sync characters are required), a Resync pulse is

an error or data block termination condition, a con-

sent to the receiver, causing the Microprocessor to

trol byte with only the Discard bit set to one is set in

resume searching for the synchronization charac-

the Receiver Control Byte Holding secondary regis-

ter(s). The Sync Strip On bit (Line State 06) is set at

ter. This eliminates the possibility of the micro-

this time if the PDP-11 program has commanded

program processing control byte commands for a

sync character stripping (Line Protocol Parameters

non-existent character.

bit 01).

4.4.3.1
4.4.2

Character Input to RC Silo

Initial Tests — Upon entry to point four of

the Data Reception routine, a copy of the character

With each subsequent Receiver Flag L signal, the

in the RC Silo is transferred to the A register and

microprogram finds the line active and sends a Set

passed through the ALU to the ALU Result register

Received Data Enable signal to the receiver (D1-5).

for testing. (A copy of the character remains at the

The receiver then places the character on the parallel

output of the RC Silo, for use in error routines. The

load lines to the RC Silo. The microprogram strobes

copy remains until a “Set Silo Out” pulse occurs.)

the character into the silo with a Set/Clear instruc-

The line number is transferred from ALU 08-11 to

tion that generates a Set Silo In L pulse, then negates

the RAM Address Register (address bits 00-03) for

the Received Data Enable line. Storage of leading

accessing the line’s set of secondary registers.

(extraneous) sync characters is inhibited if Line State
06 (Sync Strip On) has been set. Sync Strip On is

Provided that DDCMP Receive mode (Paragraph

cleared when the first non-sync character arrives.

4.4.3.4) has not been specified and that no exceptional conditions are true, the microprogram com-

The format of the received character, with its line

putes the core memory address of the control byte

number and Error flags within the RC Silo is as

corresponding to the received character, and an NPR

follows:

is executed to transfer the control byte to the Receiv-

er Control Byte secondary register.
‘Bit(s)

Content

00-07

Received Character

4.4.3.2

08-11

Line Number

the six exceptional conditions listed
in Table 4-2 is

12 Parity Error

Handling Exceptional Conditions - If one of

present, the microprogram handles the condition and

13 Receiver Overrun

branches to the Idle Loop. The control byte is not

14 Unused

fetched.

15 Resync Flag (see Paragraph 4.4.8)
4.4.3

Fetching the Control Byte

The Resynchronization flag conditions listed in Table
4-2 are discussed in Paragraph 4.4.8. Processing
of

With a character
in the RC Silo, the microprogram

block check characters is discussed in the following

branches from the Idle Loop to entry point six of the

paragraph.

4-12

Table 4-2
Exceptional Character Reception Conditions

Point(s) Tested to Detect Condition

Condition
Parity Error

Bits 12, 13 of ALU Result, while

or Receiver

‘received character (with its line

Overrun

number and any error flags) is
stored there.

Resync Flag

Line Progress 07=1 (Resync Flag

‘Expected but

Expected) and ALU Result 15=0

" not Found -

(no resync flag). Received character in ALU result during testing.

Resync Flag

Line Progress 07=1 (Resync Flag

Expected and

Expected) and ALU Result 15=1

(resync flag). Received character -

Found

in ALU result during testing.

~ Received

Microprogram Response

Transfer RC Silo to RIC Register

(2)

F orm “Discard Only” Co‘ntrol- Byte

Set Receiver Interrupt Flag (SCR 07=1)

(4)

Branch to Idle Loop

(1)

Discard Character

Branch to Idle Loop

(1)

Discard Character

(2)

Clear Line Progress 07 (Resync Flag

Branch to Idle Loop

Expected)

Line Progress 06=1

(See Text)

Line Progress\ 05=1

V(See Text)

Character is

BCC2
Received

Character is
BCC1

Character

(1)

RAM Output bits 0—14=0

Received

(2)

while Byte
Count=0

4-13

RC Silo Out to RIC Register
Set RIC 15=1 to indicate to PDP-11
program that BC=0

Form “Discard Only”» Control Byte

Set Receiver Interrupt (SCR 07=1)

(3)

Branch to Idle Loop

4.4.3.3

Processing Block Check Characters - The

Address register and an NPR instruction is executed,

received character is interpreted as the first block

causing the PDP-11 to read the contents of the

check character (BCC1) if Line Progress 05 (Expect

addressed location to the DATI register. In accessing

BCC1) has been set to one by the microprogram in

~a core memory location, two types of errors are pos-

response to a control byte command bit or a marked

sible:

byte count reaching zero with Line State 10 set to one

parity error (MPE). The Microprocessor handles

(Expect BCC). The microprogram clears the Expect

these errors as described in Paragraph 4.4.9.

non-existent memory (NXM), and memory

BCCI1 bit and includes the BCC1 character in the
BCC, as in Paragraph 4.4.4. If the selected block

If the control byte fetch resulted in no error condi-

check type (Line Protocol Parameters 03-04) calls for

tions, the control byte is transferred from the DATI

two BCCs, the Expect BCC2 bit is set to one, and

- return is made to the Idle Loop.

ter (bits 00-07). The contents of this register are then
retrieved again from the RAM and transferred via

When the complete BCC (one or two characters,vas

the B register to the ALU Result register. The new

required) has been received and accumulated within

receiver mode bits are transferred from the ALU

the Receiver BCC secondary register, the high and

Result register to the Receiver Mode Bits secondary

low bytes of the Receiver BCC secondary register are

ORed together in the ALU and transferred to RIC

00-02 in the process.

00-07. RIC bits 12 and 14 are set to spemfy the appropriate interrupt function.

4.4.4

Interpreting the Receive Control Byte

The Receiver Control Byte secondary register is now

The microprogram tests and responds to the receive

fetched and the Character Discard bit (04) is set to

control byte command bits in the following sequence:

one to inhibit storage of further characters (bits
00-03 are cleared). SCR 07 is then set to cause a

PDP-11 program interrupt.

Generate an interrupt (control byte bit

00=1): A copy of the character at the output of the RC Silo is transferred to the

4_.4.3.4

state

Handling DDCMP Receive Mode - The set

RIC register and the Receiver Interrupt

of Line Protocol Parameters 05 (DDCMP

flag (SCR 07)is set.

Receive) and receiver mode bits of 000 causes' the

DV11 to delete the control byte fetch operation for

Expect the BCC (control byte bit 02=1):

all received characters. The ALU Result register is

Line Progress register 05 (Expect BCC1) is

cleared to inhibit possible character discard and the

set.

main routine is re-entered at the point where the BCC

is accumulated, as shown in the flowchart. This logic

discussion continues
and is further discussed in Para-

Include the character in the BCC (control
byte bit 03=1): the RC Silo is propagated

graph 4.4.4.

to the A Register, the accumulated BCC

4.4.3.5

from secondary register 0111 is gated to B
Computing the Control Byte Address - The

microprogram

forms

the

effective

control

byte

the Line Protocol secondary register are

address by appending the receiver mode bits to the

read to the RAM Output Data register.

character code in the ALU

Result register. The

The BCC Network resultant, selected by

receiver mode bits, stored in bits 0-2 of the Receiver

the BCC control bits is loaded into the

Mode Bits secondary register, are translated during

BCC Result register and written back into

transfer to bits 8-10 of the B Register before being

the Receiver Accumulated BCC second-

added to the character code. The results are then

ary register (0111).

added to the Receiver Control Table Base Address.
The effective address is gated to the ALU Result

Discard the character (control byte bit
04=1): The RC Silo contents are propa-

gated down one character (Set Silo Out L
4.4.3.6

ister

Control Byte to ALU - The ALU Result reg-

contents

pulse). Silo operation is discussed in Sec-

are then transferred to the NPR

tion 4.8.

4-14

4.4.5

Storing the Character in Core Memory

At entry point four, the receiver interrupt character

In the event that the control byte specifies neither an

plus control bits are transferred from the RC Silo to

interrupt nor a character discard, the current address

the ALU Result register via the A register. ALU bits

is read from the RAM secondary register 0100 to the

08-11

NPR Address register. The RC Silo output is trans-

RAM Address register to select the set of secondary

(line identification) are transferred to the

ferred to the DATO Register and an NPR is executed

registers for the line. SCR 08 is cleared and the micro-

to store the character.

program fetches the control byte from the RAM and

proceeds exactly as described earlier for standard
4.4.6

Terminating the Data Reception Process

character processing (Paragraph 4.4.4).

The receiver byte count and receiver current address
are retrieved in turn from the RAM, incremented by

4.4.8

one in the ALU, and rewritten to the RAM.

A resynchronization request by the PDP-11 program

Handling Resynchronization Request

(Line State Ol set to one) causes a branch from the
4.4.6.1

Processing for Normal Byte Counts — If the

Idle Loop to entry point one of the Data Reception

updated receiver byte count is equal to zero, the

routine. The Resynchronization Request and the

DATO register contents (i.e., the last received charac-

Receiver Active flags (Line State 01 and 00, respec-

ter) are transferred to the RIC Register to enable

tively) are cleared on entry and the Resynchroniza-

inspection by the PDP-11 program. RIC 14 is set to

tion Flag Expected bit (Line Progress 07) is set. The

notify the program that byte count has reached zero.

microprogram then sends a Resync Pulse L to the

The Microprocessor then creates a “‘discard only”

synchronous receiver to enable a sync character

control byte and sets the Receiver Interrupt flag

search.

(SCR 07).
The asynchronous receiver interprets Resync Pulse L
4.4.6.2

Processing for Marked Byte Counts - If bit

as a line shutdown sequence.

15 of the receiver byte count is equal to one when bits
00-14 equal zero, it must have initially been set to

A word with bit 15 (Resync Flag) set to one is now

zero by the PDP-11 program (marked byte count).

generated and strobed into the top (input) of the RC

This is so because of the 2’s complement byte count

Silo.

incrementing operation.

(output) of the silo, the silo will have been purged of

In this case,

the micro-

When the Resync flag word reaches the bottom

program moves the Line State secondary register

all characters that may have been stored in the silo

upper byte (bits 08-15) to the ALU Result bits 00-07.

for the resynchronized line at the time the resynchro-

The Next Mode bits in ALU Result 05-07 are trans-

nization command was issued.

ferred to bits 00-02 of the Receiver Mode Bits sec-

ondary reglster

On each subsequent entry to point four of the Data

If ALU 03 (Expect BCC) has been set to one by the

ync Flag Expected bit set and branches to test ALU

Reception routine, the microprogram finds the ResPDP-11 program, the microprogram sets Line Prog-

Result 15 to see if the Resync flag word has reached

ress 05 (Expect BCC1), and returns to the Idle Loop.

the RC Silo output. If ALU Result 15 equals zero,

No interrupt is required until the accumulated BCC

the character is discarded. If ALU Result 15 equals

has been ORed into the RIC register. The micro-

program then creates a ‘“‘discard only” control byte

one, the microprogram clears the Resync Flag
Expected bit before discarding the character and

and sets the Receiver Interrupt flag (SCR 07).

branching to the Idle Loop.

4.4.7

4.4.9

Handling Receiver Interrupt Characters

The set state of the Interrupt Request flag (SCR 07)

Handling Receive Errors

An attempt to fetch the receive control byte may

inhibits the Received Character Waiting H signal

result in one of two types of errors. The first type is a

(D1-5), preventing the microprogram from entering

non-existent memory (NXM) time-out, in which the

the Data Reception routine at entry point six (Figure

DV11 waits a fixed interval of time (20 us) for the

4-5). Thus, silo storage accumulates characters until

PDP-11 to respond to a core memory access attempt

the PDP-11 program sets SCR 08. When the PDP-11

before setting an error condition. The second typeis a

program sets SCR 08, a clear SCR 07 L signal is gen-

Memory Parity Error (MPE), returned by the PDP-

erated to clear SCR 07, enabling a branch to entry

11 when a parity error occurs during a control byte
fetch attempt. An NXM may also occur as a result of
an attempt to store a character.

point four, where the receiver character that caused
the interrupt is handled.

4-15

If either Error flag becomes set, the Microprocessor
transfers the character from the RC Silo output to the

Count and Current Address secondary

RIC register, then sets the appropriate error bits in

registers are incremented.

RIC 12-15. The Microprocessor then branches to
create a “discard only” control byte and set the

The character transmission sequence is
described in detail in this section. This is

Receiver Interrupt flag (SCR 07). Receive function
interrupt codes are described in Tables 4-3 and 4-4.
4.5

The character is transmitted and the Byte

followed by discussions of data block terminations (Paragraph 4.5.5), and error

DATA TRANSMISSION

handling procedures (Paragraph 4.5.6).

Transmissions on a data line fall into four categories

in terms of data storage and sequencing:

A flow chart for the data transmission
process is shown in Figure 4-6. Connector

Character transmissions,

consisting of

numbers shown correspond to the con-

control and data characters stored in core

nector numbers in Figure 4-4.

memory, which make up message header

and information content.
2.

—
4.5.1

Data Link Escape (DLE) character trans-

missions, a special case of character trans-

Receiver and Transmitter units send a Tran Flag

mission, since the DLE is stored in a

Waiting signal to the Test Point Decoder (D3-2,

RAM secondary register rather than in
core

memory,

and

transmitted

Fetching the Transmit Character

When a transmitter is ready for a character, the

ES53). Tran Flag Waiting causes the microprogram to

branch to the Data Transmission routine (connector

receipt
of a control byte command bit.

one in Figures 4-4 and 4-6).
3.

BCC transmissions; the BCC is accumu-

lated in

a RAM secondary register and
The routine checks on entry whether a BCC transmis-

transmitted on receipt of a control byte
command bit. The BCC may consist of a

sion has been commanded. The check is accom-

single character (BCC1) or two characters

plished by gating the Line Progress secondary register

(BCC1,

to the ALU Result register via the A register and
branching on ALU bits 01 or 02 to the appropriate

BCC2),

depending upon

the

selected block check type.

BCC transmission instructions. (The tests are made
in the ALU Result register to facilitate any block ter-

Mark and Sync transmissions; these are
outputs of the synchronous transmitters

mination procedures that may be required. BCC

to the corresponding data lines, sent in the

transmission and block termination procedures are

absence of data.

describedin Paragraph 4.5.5.)

Mark transmission is sent by the asyn-

chronous transmitters to the correspond-

If BCC transmission has not been commanded, availability of the NPR Status register /Silo (NSR) is test-

ing data lines in the absence of data.

ed, since the NSR will be needed to report interrupt

The basic character transmission sequence for a data

conditions that may occur during character transmis-

line is as follows:

sion. If NSR is not full, the Line State secondary reg-

ister is fetched from the RAM and the Transmitter
GO bit (Line State 02) is inspected. If Transmitter
GO is zero, the microprogram sets the TMARK bit

When the transmitter is ready for a character, the character is fetched from core

memory.

for the selected transmitter, if commanded by the set
state of Line Pragress Parameters bit 00 (Idle Mark),

The control byte for the character is then

and returns to the Idle Loop. If Transmitter GO is set
to one, Line State 07 is tested to determine whether

fetched from core memory to sequence
DLE and BCC transmissions and control
BCC accumulation; and

the next transmit character is to be fetched from a
principal or an alternate core memory table.

4-16

‘Table 4-3
Receive Function Interrupt Conditions
(For Synchronous
Line Cards)

Code Set in RIC 12—-15
15

Meaning
Special Character Received:

Bit 00 of the control byte for the character in RIC 00—07 is set to one (generate

interrupt), indicating that the received character is a special character.

Parity Error:

The character in RIC 00—07 has a parity sense opposite to that selected for this

line (the line specified in RIC 08—11) by the parity sense switches on the

M7839 module (Figure 2-6).
0

Overrun:

The received character(s) preceding the character set in RIC 00—07 have been
lost because of overflow of the Received Character Silo.

Parity Error and Overrun:
As described above for error codes 0001 and 0010.

Byte Count Warning:

The character set in RIC 00—07 has been stored in core memory. No more char-

acters may be stored for this line as the byte count is now zero.
0

Block Check Complete:

The block check character(s) for the data block received on this line have

arrived and have been included in the Accumulated BCC. The Accumulated BCC
is now in the Receive Accumulated Block Check Character secondary register;

the OR of the high and low bytes of the accumulated BCC is set in RIC 00—-07.
0

Undefined.

Byte Count Zero:

The receive byte count for this line was zero prior to receipt of the character set
in RIC 00—07. Thus, the character was not stored as no assigned storage was
available.

Undefined

Procéssing Error 00:
A non-existent memory time-out occurred when the DV11 attempted to store

the character set in RIC 00—-07.
1

Processing Error 01:

A non-existent memory time-out occurred when the DV11 attempted to fetch
the control byte corresponding to the character set in RIC 00—07.

Processing Error 10:
The DV11 received a signal on the mamory parity error line from the PDP-11
when the DV11 attempted to store the character set in RIC 00—07. This condi-

tion indicates a defect in the memory parity logic, as the PDP-11 generates
parity error signals only on core memory read operations.
1

Processing Error 11:
A memory parity error occurred when the DV11 attempted to obtain the control byte corresponding to the character in RIC 00—07.

4-17

Table 4-4
Receive Function Interrupt Conditions

(For Asynchronous Line Cards)
Code Set in RIC 1215
15

Meaning

» Special Character Received:

Bit 00 of the control byte for the character in RIC 00—07 is set to a one
(generate interrupt), indicating that the received character is a special character.
0

Parity Error:

The characterin RIC 00—07 has a parlty sense opposite to that selected for this
line (the line specified in RIC 08—11) by the programmable Format registers of
the Asynchronous Lme Card.
0

Overrun Error:

The received character(s) precedmg the character set in RIC 00—07 have been
lost because of overflow of the Received Character Silo.
0

F rammg Error:

The character set in RIC 00—07 lacked a stop bit present at the proper time.

This codeis usually interpreted as indicating the reception of a break.

Byte Count Warning:
The character set in RIC 00—07 has been storedin core memory No more

characters may be stored for this line as the byte count is now zero.

Block Check Complete:
The block character(s) for the data block received on this line have arrived and
have been included in the Accumulated BCC. The Accumulated BCC is now in

the Receive Accumulated Block Check Character secondary register; the OR of
the high and low bytes of the accumulated BCC is set in RIC 00—-07.

Undefined

Byte Count Zero:

The receive byte count for this line was zero prior to receipt of the character

set in RIC 00—07. Thus, the character was not stored as no assigned storage was
~

available.

Undefined

-Processing Error 00:
A non-existent memory time-out occurred when the DV11 attempted to store

the character set in RIC 00—-07.
1

Processing Error O1:

- A non-existent memory time-out occurred when the DV11 attempted to fetch
the control byte corresponding to the character set in RIC 00—07.

4-18

Table 4-4 (Cont)
Receive Function Interrupt Conditions
(For Asynchronous Line Cards)
Code Set in RIC 1215

Meaning

Processing Error 10:

A DV11 received signal on the memory parity error line from the PDP-11 when
the DV11 attempted to store the character set in RIC 00—07. This condition
indicates a defect in the memory parity logic, as the PDP-11 generates parlty
error signals only on core memory read operations.

Processing Error 11:

A memory parity occurred when the DV11 attempted to obtain the control byte
corresponding to the characterin RIC 00-07.

NOTE: A priority encoding scheme is used by an asynchronous line to present a multiple error code condition. Any

error flag combination that contains an overrun error is presented as an Overrun Error (code 0010) in the
RICR register. A framing error and parity error combination is presented as a Framing Error (code 0011) in

chart. This logic discussion continues and is discussed
further in Paragraph 4.5.3.

In either case, the appropriatev(principal or alternate)
byte count is fetched from the RAM and examined. If
the byte in bits 00-14 is equal to zero, the microprogram branches to select the other transmission
data table for the next character fetch, or to terminate
data transmission if the other byte count is also equal
to zero. The zero byte count condition is also tested
for and handled after the character is transmitted and
the byte count incremented, as described in Para-

4.5.2

Fetching the Control Byte
If the transmit character fetch resulted in no error

conditions, the microprogram computes the core
memory address of the corresponding control byte.
The microprogram then fetches the control byte and
transfers it to the ALU Result register, where it can
be manipulated and interpreted.

graph 4.5.4. The purpose of testing the byte count on
entry is to prevent character transmission in the event

that the Transmitter GO bit has been set to one and
no byte count has been set by the PDP-11 program.

4.5.2.1 Computing the Control Byte Address - The
microprogram computes the control byte address by

If the byte count is non-zero, the appropriate (principal or alternate) current address is transferred from
the RAM to the NPR Address register and an NPR
instruction is executed, causing the PDP-11 to read
the contents of the addressed location to the DATI
register. (NPR operations are descrrbed in Section

code, then adding in the transmitter control table
base address. Initially, the character is transferred
from the DATI register to A register bits 00-07 to
position it for computation. The character is also
temporarily transferred to the DATO register (via the
A and ALU Result registers) for later transmission
and possible accumulation in the BCC after the con-

4.6.)

4.5.1.1

appending the transmitter mode bits to the character

)

trol byte has been interpreted. The transmitter mode
bits, stored in bits 00-02 of the Transmitter Mode
Bits secondary register, are translated during transfer

Handling DDCMP Transmit Mode - The set

to B register bits 08-10 before being appended to the

state of Line Protocol Parameters 06 (DDCMP

character code. The interim result is transferred from

Transmit), plus transmitter mode bits set to 000,

the ALU Result register to the B register, and the
control table base address is transferred from the

causes the DV11 to delete the control byte fetch oper-

ation for all transmitted characters. Thus, exit is
made from the main routine just prior to the control

RAM to the A register. A and B are again summed to

byte fetch. The routine is re-entered at the point
where the BCC is accumulated, as shown in the flow

form the resultant control byte address in the ALU
Result register.

4-19

4.5.2.2

Con*rol Byte to ALU - The control byte
address is now transferred to the NPR Address regis-

ter for transmission causes a marking condition to be

ter and an NPR instruction is executed, causing the
PDP-11 to read the contents of the addressed loca-

in Chapter 3.) If DNA is asserted, the microprogram

tion to the DATI register.

branches to fetch the Line State secondary register

If the control byte fetch resulted in no error condi-

(The PDP-11 program may sample the Transmitter

asynchronous transmitter, although lack of a charac-

sent. (Refer to cautionary note regarding idling syncs

and set the Transmitter Underrun bit (Line State 03).

tions, the control byte is transferred from the DATI

Underrun bit to determine whether an idling sync has

been sent after the last character was loaded into the

00-07. The transmitter mode bits are transferred

transmitter.)

from the ALU Result register to the Transmitter

program transfers the character from its temporary

Mode Bits secondary register, and are translated

After

checking

DNA,

the

micro-

storage in the DATO register to the Transmit Char-

from positions 05-07 to 00-02 in the process.

acter register at 02 time. A 300-ns Transmitter Strobe

4.5.3

mitters unit and the transmit character is loaded into

H pulse (D3-4) is routed to the Receiver and TransInterpreting the Transmit Control Byte

The microprogram tests and responds to the transmit

the transmitter for the selected line.

control byte command bits in the following sequence:

The microprogram now tests the transmitter data

Send DLE (control byte bit 01=1): the

table selection bit (Line State bit 07), retrieves the

DLE character is fetched from the Line

indicated (principal or alternate) transmitter byte

Protocol

count

Parameters secondary register

and loaded into the Transmit Character

and

transmitter

current address

from

the

RAM, increments each one in the ALU and rewrites

them to the RAM. If the updated count is equal to

acter being processed.

zero, the microprogram branches to select the other

Send BCC Next (control byte bit 02=1):

~or to terminate data transmission if the other byte

the Send BCC1 Next bit (Line Progress bit

count is also equal to zero.

transmission data table for the next character fetch,
2.~

00) is set to one to initiate transmission of

the BCC in the next character transmission cycle.

4.5.5

Terminating Data Blocks

The DVI1I1 provides the PDP-11 program with two
3.

Include the character in the BCC (control

means of terminating data blocks:

byte bit 03=1): the character is transferred

from the DATO register to the A register,
the accumulated BCC is gated from sec-

The PDP-11 program may supply a con-

trol byte with bit 02 (Send BCC) set to one

ondary register 0110 to B register, and the

block

check

computation

control

(control byte termination).

;

‘

from the Line Protocol secondary register

The

PDP-11

program

may

provide

marked transmitter byte count, signalled

ter. The BCC Network resultant selected
by the BCC Control bits is loaded into the

by bit 15 of the Byte Count register being

BCC Result register and written back into

zero (marked byte count termination).

equal to one after bits 00-14 have reached

the Transmitter Accumulated BCC sec-

|
4.5.5.1

4.5.4

Character Transmission

Test Point Selector (D3-2). If the Microprocessor

does not send the character to the synchronous transmitter before the center of the last bit of the character

in the control byte causes the microprogram to set Line Progress bit 00 (Send BCC1) to
one. On the next entry into the data transmission routine, the set state of Line Progress 00 causes the
microprogram to fetch the Transmitter BCC from the

being transmitted, the DNA signal is generated by
the synchronous transmitter, and an idling sync char-

acter is sent.

Control Byte Termination - The Send BCC

command

When response to the control byte is complete, the
microprogram samples the Data Not Available
(DNA) level from the synchronous transmitter to the

[SY

are read to the RAM Output Data regis-

ondary register (0110).

bits

A DNA signal is not generated by an

RAM and transfer bits 00-07 (BCC1) to the Transmit
Character register for transmission. The Line Protocol secondary register is then incremented by one to

set up for sending the second 8-bit BCC (BCC2), if
required.

4-20

Line Protocol bits 03-04 are then tested. If they are

4.5.6

both equal to zero, the BCC is an LRC and BCC2 is

Transmitter interrupts are caused by core memory

not required; the microprogram clears Line Protocol
bit 01 and returns. For all other codes, BCC?2 is
required, and is sent on the next entry into the Data

Handling Transmit Interrupts

processing errors and zero byte counts. Transmitter
interrupt codes and associated line numbers are set in

the NPR Status Register (NSR), an 8-bit silo 64 char-

Transmission routine. At the next entry into the data
transmission routine after sending BCC2, the micro-

acters deep (D2-9). The interrupt code is gated to
Unibus bits 08-11 and the transmitter line number is

before returning, if both principal and alternate byte

gated to Unibus bits 00-03. Whenever an entry is
available at the silo output, the NPR Status bit is set,

‘program clears Transmitter GO (Line State 02)

and is gated to Unibus bit 15 when the PDP-11 pro-

counts are equal to zero.

gram reads the NSR.

4.5.5.2

Marked Byte Count Termination - This form

of termination provides for mode changes as well as
BCC transmission at zero byte count time without

The line number in the NSR is obtained directly from

requiring a control byte fetch. The microprogram

the Master Scanner. The interrupt code is obtained

moves the contents of Line Progress 08-15 to ALU

from an intermediate 4-bit store that holds the selec-

Result 00-07 via the B Register. ALU 05-07 are then

tion code (bits 04-07 of the RAM address) for the last

transferred to Transmitter Mode Bits secondary register 00-02 to update the transmit mode.

In the case of a byte count interrupt or processing

secondary register accessed by the Microprocessor.
error during character fetch, this turns out to be the

The microprogram next inspects the set Send BCC1

code for the associated register. (If, for example, the

Next command bit, now in ALU 02. If ALU 02 is set

transmitter principal byte count reaches zero, code

to one, the microprogram fetches the Line Progress

0001, the selection code for the Transmitter Principal

secondary register and sets bit 00 to one, causing

- Byte Count secondary register, is set in NSR 08-11.)

BCC transmission the next time that the micro-

Transmitter interrupt codes are listed and described

program services the transmitter flag for this line.

in Table 4-5.

Table 4-5
Transmit Function Interrupt Conditions

Code Set in NSR 08—11

Meaning

Transmitter principal current address specified a non-existent memory

location (NXM).
0

Transmitter principal byte count is equal to zero.
Transmitter alternate current address specified a non-existent memory

location (NXM).
0

Transmitter alternate byte count is equal to zero.

An attempted control byte fetch by the DV11 produced a non-existent
memory condition or a memory parity error. (The specific error is set in
the Line State secondary register.)

4-21

4.6 UNIBUS INTERFACE

4.5.6.1 Processing Errors — A transmit character or
control byte fetch attempt may result in one of two
types of core memory processing errors. The first
type is a Non-Existent Memory (NXM) time-out, in
which the DV11 waits a fixed interval of time (20 us)
for the PDP-11 to respond
.to a core memory access
attempt before setting an error condition. The second
type is a Memory Parity Error (M PE), returned by
the PDP-11 when a parity error occurs during a control byte fetch attempt. A single error code (1000) is
provided for both types of control byte fetch processing errors. The PDP-11 program must examine Line
State bits 04 and 05 to determine whether an NXM or
MPE, respectively, has occurred. Parity error
indications occur only on PDP-11s equipped with

Figure 4-7 shows the functional units of the Unibus
Interface logic for the DV11 Data Handling Section.

(Unibus Interface logic for the Modem Control Unit
is discussed in Section 4.2.)

Selection of the DV11 Data Handling Section by the
Processor is accomplished by the Address Decoder in
conjunction with the Unibus/Transfer Bus Interlock.
The Address Decoder interprets the 14-bit DV1l
Data Handling Section address in Unibus address
and the Unibus/Transfer Bus Interbits A04-A17,
lock acknowledges selection by returning Slave Sync
(if the Microprocessor is not accessing DVI11 programmable registers via the Transfer Bus).

parity memory.

A\
”

SSYN (SLAVE SYNC)

ADDRESS

(o)

(1) ADDRESS
DECODER
|

TRANSFER BUS
INTERLOCK

D1-8

D3-7

c1,co

INSTRUCTION DECODER ENABLE

BITS 1-3

BITS 2-3

" UNIBUS/

ADDRESS SELECTED

LOAD SELECTED REGISTER/BYTE

DECODER

D2-5

D oA

SECTION

PROGRAMMABLE

REGISTERS

READ

‘:BI,
e REGISTER +
'
o

_SELECTOF; J
D

(DATA TO PROGRAMMABLE REGISTERS)

6 X16

READ
REGISTER

@ | DATA FORBUS

”

t;.

UNIBUS
DATA

.__®

MIXER

ER g _fe—(8)
8

(1e)
T\

NP%AEETA
REGISTER

D1-9

NPR

(NPR ADDR @@ (BYTE SELECT)

ADDRESS

NPG, SSYN

CONTROL

(8)—
A\

> g TRANSFER
BUS

ffe\

ADDRESS
TO BUS

\8)

MEMORY PARITY ERROR (MPE)
Y
DATA

STROBE

D1-8

NPR, SACK,BBSY,MSYN

(CHARACTERS, CONTROL BYTES)

”

D2-6,D1-9

NPR DATA TO BUS

(CORE MEMORY ADDR)

(CHARACTERS)

NP%“.L?TA

)

1o TEST
POINT

NON-EXISTENT MEMORY (NXM)_ [ oe| ecToR

D2-7

NPR OPERATION

FROM INSTRUCTION
DECODER IN

CONTROL
VECTOR ADDRESS

INTERRUPT

A REQUEST / B REQUEST

CONTROL

‘

MICROPROCESSOR
FROM SCR REG.

D2-8

11-2884

Figure 4-7 Unibus Interface Block Diagram
4-22

The Register Decoder interprets the direction selec-

The register selection bits are also routed to the Read

tion bits (CO, C1) and the 4-bit register and byte selec-

tion code A00-A03, to enable register read and write

plexes the programmable registers onto the Data For

by the PDP-11 program. The Unibus data lines D0O-

Bus lines. If a read operation is specified Bus C1 bit

D15 fan out to the six programmable registers into

reset to zero (H), a Read Register H signal is gener-

which data may be written (SCR, LCR, SRS, SAR,

ated (D2-5) and gates the selected register to the

SFR, Reserved). All eight programmable registers

Unibus (D2-6).

may be read. The register selected for reading is gated
‘via the Read Register Selector onto 16 data lines.

4.6.3

Non-Processor Requests (NPRs)

The DV11 issues NPRs to store or retrieve data from
NPR Control responds to NPR operation requests

PDP-11 core memory. The core memory address is

from the Microprocessor by initiating a handshaking

placed in the NPR Address Register and an NPR

procedure to access core memory via the Unibus,

operation is executed to either load the DATI register

then gating the contents of the NPR Address Register

with the contents of the accessed location or load the

to the Unibus address lines. The NPR data is trans-

core location with the contents of the DATO register.

ferred via the DATI and DATO registers for core
memory read and write operations, respectively. Bit

The NPR Operation L signal from the Instruction

00 of the NPR Address Register gates the selected

Decoder sets Request Bus flip-flop at 02 time (D2-7).
When SACK (Selection Acknowledge) and BBSY
(Bus Busy) are both clear, Bus NPR L is asserted to
request Unibus access. When the processor responds

byte to the Unibus via the Unibus Data Mixer.

4.6.1

Interface Operations

Three types

of interface operations between the

DV11 and the PDP-11 Unibus are provided for:

Selection of a DV11 programmable register

for

read/write

the

PDP-11

(NPR) by the DV11 to access core memo-

Generation

PDP-11

program

interrupt.

Ope\ration type (2) is performed only
by the Data
Handling Section of the DV1l. Unibus interface
operations will now be described in detail.
4.6.2

ing the propagation of the grant to units further

down the bus. SACK is set, 50 ns later, serving to (1)
acknowledge selection.

Generation of a non-processor request
ry for a read/write operation,

clear. This inhibits assertion of Bus NPG Out, block-

clear the Bus NPR and (2) assert Bus SACK L to

program,

with Bus NPG In (Non-Processor Grant), Grant will

go to zero, since Request Bus is set and BBSY is

DVI11 Selection

The Processor responds to the SACK by removing
Bus NPG In. When the device asserting BBSY
releases the bus, BBSY is set to one (after a 30-ns
delay to ensure that BBSY does not cut off its own set
pulse). BBSY now generates the Address To Bus signal, which enables the NPR Address Register to the
Unibus Address lines (D1-8).

BBSY also starts the MSYN (Master Sync) Wait 200-

ns timeout. At the end of this interval MSYN is set
and Master Sync is asserted on the Unibus. A 20-us

When the Processor becomes Unibus bus master and

one-shot is fired and sets NXM if core memory does

places the DV11 Data Handling Section Address on

not return slave sync during this interval.

the bus address lines, Address Selected H (D1-8)
becomes true, and causes a slave sync to be returned

(BUS SSYN L signal on D3-7). Simultaneously,
Instruction Decoder Enable L becomes true and

enables decoding of the programmable register selec-

If the C1 bit has been set in the NPR Address Regis-

ter to define a core memory write operation, NPR
Data to Bus L (D2-7) is asserted, gating the DATO

tion bits in D2-5. (The logical conditions enabling

slave sync are described in detail in Paragraph 4.7.1)
If a write operation is specified Bus C1 bit set to one
(L), a load signal is generated and routed to the
selected register to load the Unibus data bits into the

the data and returns slave sync, causing the CLR flip-

byte (high /low) selected by bit 00 of the bus address.

release the Unibus.

flop to set. The CLR signal resets MSYN, which
starts a 100-ns end cycle delay. Request Bus is cleared

at the end of the delay, causing BBSY to clear and

4-23

If the C1 bit has been cleared in the NPR Address

4.7

The DV11 microprocessor has a repertoire of eight

return of slave sync from core memory will start the

microinstructions, as shown in summary form in Fig-

200-ns Data Wait delay. When the delay expires, a

ure 4-8. Note that op codes are set in bits 12-14.

MICROPROCESSOR INSTRUCTIONS

40-ns Data Strobe H pulse is generated to gate the

Functional operation and logical execution sequence

Unibus data to DATI register. The trailing edge of
Data Strobe sets CLR to terminate the cycle and

of each microinstruction is discussed in detail following descriptions of the Interlock System and Timing

release the Unibus.

Controls, which sequence Microprocessor operations

4.6.4 Data Interrupts

instruction mnemonics shown in this section are

Interrupt request bits set in the SCR cause assertions

those

of the A Request H and B Request H lines to Inter-

assembler.

and synchronize them with Unibus operations. The
implemented

for

the

Microprocessor

rupt Control (D2-8). The A Request/B Request condition determines the state of Vector Bit 02 (set to one

4.7.1

for B Request; otherwise, reset to zero). The Vector

The microprogram and the PDP-11 program both

Unibus/Transfer Bus Interlock

to Bus L signal is enabled whenever Interrupt Con-

have access to the RAM and to several other DV11

trol becomes bus master.

functions, such as the SCR and the NPR registers.

Interlock controls have been provided in the DV11

The cross-coupled 7402 NOR gates form a transition-

prevent interference between the two programs when

sensitive flip-flop. If an A Request H or B Request H

both attempt to access a common function.

is asserted at E6 pin 11 or pin 12, an interrupt request

is generated and is stored by the cross-coupled NOR
gates. Should a second assertion on the A Request/B

Control of access to shared functions is governed by

Request lines occur while the first is being serviced,

the states of the Unibus GO and Microcode GO flip-

the transition would be masked by the assertion at

flops (D3-7). When the device acting as Unibus bus

the other NOR gate input (E6-11 or E6-12). How-

master places the address of the DV11 (775000) on

ever,

Request or B

the Unibus address lines, the Address Selected H lev-

Request) is dropped, the 74121 one-shot fires, serving

el (D1-8) is asserted. This is ANDed in D3-7 with

when

the first

assertion

to (1) temporarily disable both request lines, and (2)

MSYN H when it becomes available from the

provide a transition at the end of the one-shot inter-

Unibus, and with A17H, to condition the Unibus GO

val which generates an interrupt request for the sec-

flip-flop for setting. The next transition to zero of the

ond assertion on the

Phase flip-flop (which is continuously toggled by the

A Request/B Request lines.

20-M Hz master-clock) is thus enabled to set Unibus

GO. If no microinstruction is in progress, the DV11

If the SACK and the BBSY flip-flops are reset, the
interrupt request causes BRS L (bus request on inter-

returns slave sync (Bus SSYN L signal on D3-7) to

rupt priority level 5) to be asserted to the Unibus via

acknowledge receipt of bus control, following com-

the priority jumper plug. When level 5 has priority,

pletion of any internal initialization which may have

the processor asserts BG5S IN (bus grant on interrupt

been initiated by a Master Clear (SCR 11=1). The

priority level 5), which clears Grant, blocking propa-

Instruction Decoder Enable L signal is also asserted

gation of the Grant to units of the same priority level

to enable Unibus access to DV11 functions.

further down the bus. Bus SACK L is then asserted

by the DV11, inhibiting the processor from issuing
further Grants during this interrupt cycle.

The set state of Unibus GO holds Microcode GO

When the device asserting BBSY releases the bus,

ited, as positive transitions from the set output of the

cleared. Thus, microprogram operations are inhib-

NOBBSYNOSSYN H is asserted, serving to (1) clear

Phase flip-flop do not set Microcode GO. When the

SACK and (2) set BBSY, thus asserting Vector to Bus

device addressing the DV11 relinquishes bus control,

L, which gates the vector to the Unibus and generates

Address Selected H turns off, causing the next transi-

Bus Intr L (D2-6). The processor responds to Bus

tion to zero of the Phase flip-flop to clear Unibus Go.

Intr L by reading the vector address and asserting

This removes the inhibit to the D input of Microcode

BUS SSYN L. This clears BBSY, via E50 pin 4,

GO, and the next transition to one of the Phase flip-

releasing the bus.

flop sets Microcode GO.

4-24

BRANCH A (BRA)

_J\_

TEST

POINT

BRANCH

ADDRESS

BRANCH B (BRB)
15

e~
TEST

POINT

BRANCH

ADDRESS

ALU OPERATION (ALU)
15

UNUSED

ALU OPERATION

RAM OPERATION (RAM)
15

—~—

J\_

UNUSED

~—

WRITE OP. SOURCE

RAM LOCATION

DATA TRANSFER (XFR)
15

Cc1

X
“

UNUSED

SOURCE

DESTINATION

NPR OPERATION (NPR)
15

—

UNUSED

SET/CLEAR

OPERATION

(S/C)

J\_

~—

UNUSED

BCC

J’

FUNCTION

OPERATION (BCC)

UNUSED
X= UNUSED

P= HIGH-ORDER BIT OF BRANCH ADDRESS
,

11-4008

Figufe 4-8

Microprocessor Instructions

4-25

and 03 are similarly generated as the timing pulse,

The state transition of Microcode GO sets the Microinstruction In Progress flip-flop, which places a static
inhibit on the gates which generate the Slave Sync
and Instruction Decoder Enable L signals. Thus, if
the DV11 is selected during a microinstruction cycle,
Unibus GO sets, but Slave Sync is not returned until
the microinstruction execution cycle is complete.

strobed by the 20-MHz clock, shifts down the timing
flip-flops in the 745175 (E90).

Microinstruction In Progress is reset at T250 time for
a 50-ns interval to enable either:

1.
4.7.2

DVI11 Timing

Figure

4-9 is a timing diagram of the microinstruction execution cycle. Two master clocks (D35) provide system timing control. The 5.068 MHz
clock is counted down by four binary counters to
provide the several bit-rate timing pulse trains
required by the synchronous receivers and transmitters. The 20 MHz clock provides the basic 50-ns

the return of Slave Sync if the DV11 has
been selected.

At time 01, the ROM Address Register is
incremented to address the next sequential ROM
location. Instructions loaded into the ROM Data
Register at the preceding 03 time are interpreted at 02
time, and in the case of branch instructions, the
ROM Address register is loaded with the 9-bit ROM
address set in the branch instruction if the point tested is true. Data transfer sources are also enabled at 02
time. At Data Strobe L time, Set/Clear operations
are executed. Resultants are also strobed into the
BCC and ALU Result registers and data transfer destinations at Data Strobe L time. At 03 time, the contents of the ROM location specified by the ROM
Address register are strobed into the ROM Data reg-

intervals required for microinstruction timing.
Microinstruction timing pulses are generated by the
logic shown in D3-7.

When the Unibus GO flip-flop resets, the Microcode

GO flip-flop sets on the next transition to one of the
Phase flip-flop, causing Microinstruction in Progress

to set. The Microcode GO state transition sets T50,

which in turn resets Microcode GO. The set state of
Microinstruction In Progress inhibits further setting
of Microcode GO during the microinstruction cycle.
The result is the generation by Microcode GO of a
50-ns timing pulse (01) at the start of each microinstruction cycle. Timing pulses 02, Data Strobe L,

—»]

the setting of Microcode GO, thus
initiating the next microinstruction cycle,

ister for execution as the next microinstruction.

le—50ns

INSTRUCTION=-IN
PROGRESS FF

—_—————

LET UNIBUS IN

MIROCODE GO
FF (01 TIME)

INCREMENT ROM
ADDRESS

02 TIME

—

I
L

DATA STROBE L

I
——

SET BRANCH
ADDRESS

03 TIME

1
W—-—I

‘

DATA OUT
TO ROM
DATA REG
11-2888

Figure 4-9

Microinstruction Timing Diagram

4-26

' 4.7.3

;

Branch A (BRA)

TEST POINT

BRANCH

ADDRESS
1H=-3175

Logic

Function

If the point selected by bits 08-11 is true, the ROM

Bits 08-11 of the Branch A instruction set in the

address set in bits 00-07 and 15 is transferred to the

ROM Data Register (D3-2) are decoded to select one
of the test points input to the 74150 selector/multiplexers. The decoded Branch A op code
enables the logical state of the test point to the 74150
output to generate a Branch Point True level
if the

ROM Address register, causing the microprogram to

execute the instruction stored at that address as its
next instruction.

f/'“\

test point is asserted. The Branch Point True level is
recorded at T50 time by flip-flop E88 and enables
loading of the ROM Address register (D3-1) with the
branch address from the ROM Data register at 02
“time. At 03 time, the contents of the branch location
are loaded into the ROM Data Register.

4.7.4

Branch B (BRB)

TEST

T
W

POINT

BRANCH ADDRESS
I1-3168

Function

Logic

If the line selected by bits 08-11 is true, the ROM

Same as Branch A microinstruction.

address set in bits 00-07 and 15 is transferred to the
ROM Address register, causing the microprogram to
execute the instruction stored at that address as its

Pey

next instruction.

4-27

4.7.5

Arithmetic and Logic Unit (ALU) Operation

—_—

UNUSED

—

ALU OPERATION

‘

11-3169

Function

Logic

Bits 00-05 select one of the ALU resultants. The

The ALU operation bits (ROM Data register 00-05)

selected resultant is strobed into the ALU Result

are statically presented
to the ALU (D1-1, D1-2) to

select the specified resultant. The ALU Operation L

.
|

enabling level from the Instruction Decoder loads the

selected resultant into the ALU Result register at 02
time. ALU resultants selected by ALU codes are listed in Table 4-6.

Table 4-6

ALU Operations
ALU Operation Code in ROM 00—-05
05

O‘

o |

ALU Resultant

A Plus B

Minus 1 (2’s Complement)

OR of A or B

Zero

AND of A Complement and B

APlus 1

4-28

4.7.6 RAM Operation (RAM)

R/W

UNUSED

J\.

WRITE OP. SOURCE

RAM LOCATION
11-3170

Function

Logic

If bit 08 is set to one, a RAM write operation is per-

For a RAM write operation, the RAM Operation L

formed. The source register or field specified by bits

level from the Instruction Decoder is ANDed (E86

04-07 of the instruction
are gated to the Transfer

pin 6) with the set state of ROM Data register bit 08

Bus. The gated bits are transposed as required in the

to generate an 80-ns RAM Write Enable L pulse (D3-

gating process. The address of the RAM location for

6). Delay line DL2 and NOR gate E91 are used to

the write operation is partly defined by the contents

stretch the 50-ns pulse (T50) to 80 ns in length. If the

of bits 00-03 of the instruction, which form bits

Instruction Decoder Enable L signal from the Inter-

04-07 of the RAM address. Bits 00-03 of the RAM

lock is negated (D3-8), the 8-bit address is placed on

Address (the line number) are supplied by the con-

the RAM Address lines and the data on the lines

tents of the RAM Address register. The combined 8-

from the Transfer Bus is strobed into the addressed

bit address is placed on the RAM Address lines and

RAM location by the RAM Write Enable L pulse.

the data on the lines from the Transfer Bus is strobed
into the enabled RAM location.

For a RAM read operation, the RAM Operation L
level from the Instruction Decoder is ANDed (E86

If bit 08 is zero, a RAM read operation is performed.

pin 6) with the reset state of ROM Data register bit

The address of the RAM location for a read oper-

08 to generate a 50-ns RAM Output Data Clock

ation is partly defined by the contents of bits 00-03 of

pulse at 02 time (D3-6). If the Instruction Decoder

the instruction, which form bits 04-07 of the RAM
Address. Bits 00-03 of the RAM Address (the line
number) are supplied by the contents of the RAM

the 8-bit address is present on the RAM address lines,

Address

(D3-11) by the RAM Output Data Clock pulse. For

The combined

Enable L signal from the Interlock is negated (D3-8),
and is strobed into the RAM Output Data register

8-bit address is

placed on the RAM address lines and the contents of

additional logic detail, refer to Paragraph 4.8.3.6.

the addressed location are read to the RAM Output
Data register. Bits 04-07 of the instruction are not

sampled for a RAM read operation.

4-29

Data Transfer (XFR)

4.7.7

UNUSED

DESTINATION

SOURCE

1-3171

Function

The register or field selected by bits 04-07 is gated to

the Transfer Bus with bits transposed as required.
The data on the Transfer Bus lines is then loaded into

the destination register selected by bits 00-02 of the
instruction. If the destination is the NPR Address
register, bit 09 specifies DATI when reset to zero or

DATO when set to one. Bit 09 is not otherwise sampled to execute the instruction.

| Logic

ROM Data register bits 04-07 are statically present
at the Transfer Bus selector/multiplexers (D1-3, D14) to multiplex the selected source registers onto the
Transfer Bus. Destination selection is accomplished
by the Destination Decoder, a BCD-to-decimal decoder on D3-6. ROM bits 00-02 are applied to the BCD
inputs and the destination register loading pulse is
generated at 02 time, enabled by the Data Transfer L

level from the Instruction Decoder.

4.7.8 Non-Processor Request (NPR) Operation
15

x | 1

UNUSED
1n-3172

Function

Logic

The NPR Operation L signal from the Instruction

A NPR is executed to store or retrieve a byte to or
from the PDP-11 core memory location specified by
the contents of the NPR Address register.

Decoder sets Request Bus flip-flop at 02 time (D2-7)
to set the NPR. NPR operation is discussed in Section 4.6.

4-30

4.7.9

Set/Clear (S/C) Operation

—

FUNCTION

UNUSED

1H-3173

Function

Logic

The Set/Clear function specified by bits 00-07 is per-

The S/C function decoders are shown in D3-3. The
output pulse is generated at Data Strobe L time, as
indicated.
|

formed; it is most frequently used to set/clear
selected bits in the RAM Output Data register, or to

—

advance the Master Scanner. Set/Clear codes are listed in Table 4-7.

4.7.10 Block Check Character (BCC) Operation
00

UNUSED
11-3174

Function

The BCC resultant specified by bits 03 and 04 of the

RAM Output Data register is loaded into the BCC

Result register.

Logic

The contents of the A and B registers are logically
combined in the BCC Network (D1-6, D1-7). RAM
output bits 03 and 04 condition the selection gates to
obtain one of four possible resultants, as described in
Table 3-10. The BCC Calculation L signal from the
Instruction Decoder loads the selected resultant into
the BCC Result register at Data Strobe L time.

4-31

Table 4-7

Set/Clear Codes
-

0
0

-0

Bits

Function

-0

Set SCR 07

Set RICR 12

Set RICR 13

Clear SCR 08

Set RICR 15
Set RICR 14

Set SCR 10

Clear NXM

-0

Set Silo Out

Set Silo In

Clear RDE

-0

Set ALU 02

Set RDE

Clear ALU 02

Clear ALU 01

Clear ALU High Byte

Clear RAM 03

Set RAM 03

Clear RAM 02

Set RAM 02

Clear RAM 01

Set RAM 01

Clear RAM 00

Set RAM 00

(Unused)

(Unused)
Advance Master Scan

Resync Pulse

Clear TMARK

Set TMARK

Clear Tran Data 08

-0

Set Tran Data 08

Clear RAM 07

Set RAM 07

Clear RAM 06

Set RAM 06

Clear RAM 05

Set RAM 05

Clear RAM 04

Set RAM 04

4-32

4.8

LOGIC DIAGRAM DESCRIPTIONS

4.8.1.4

This section contains descriptions of DV11 logic as it

M7836 (D1-4) — Shows Transfer Bus bits

08-17 and part of the Set/Clear Signal Generator.

appears on the system logic diagrams. Table 4-8 provides

cross-reference between DVI11

functional

4.8.1.5

M7836 (D1-5)- Shows the RC Silo, a 16-bit

units’ system logic drawings, and the drawing-by-

silo, 128 characters deep, composed of eight 3341

~drawing descriptions of DV11 logic provided within

propagable register modules. Silo input consists of

each subparagraph of this section. Units spelled with

the receiver character, the line number from the Mas-

all capitals in Table 4-8 appear on system and sub-

ter Scanner, plus any parity error, receiver overrun,

system block diagrams within this chapter. The func-

or Resync flags. An entry is set in the RC Silo input

tional registers SAR and SFR have been omitted

(“top” of the RC Silo) by a 180-ns Set Silo in L pulse,

from the table as these are formed by RAM data lines

triggered by a Set/Clear command signal. The entry

and ROM Data register lines, respectively.

propagates down toward the RC Silo output (‘““bottom”). The silo output data may be non-destructively

4.8.1

ALU and Transfer Bus Drawing

transferred to destination storages via the Transfer

Logic for the ALU, Transfer Bus, BCC Unit, RC

Bus. If, however, a Set Silo Out pulse is generated by

Silo, and portions of the Unibus Interface is contain-

a Set/Clear signal, the entry at the RC Silo output is

ed in drawing M7836, D1-1 through D1-9.

shifted out of the RC Silo and is replaced at the RC

Silo output by the next sequential entry (if any).
4.8.1.1

M?7836 (D1-1) - Shows the entire B register

(B0O0-B17), Arithmetic and Logic Unit (ALU) bits

The drawing shows the gates that generate Receiver

00-07, and bits 00-07 of the ALU Result register.

Flag Waiting by ANDing the Silo-Not-Full condi-

The B register is loaded from the Transfer Bus by the

tion with Receiver Flag L from the selected receiver.

B Register Clock pulse, and is issued at 02 time is a

The Receiver Flag Waiting signal causes the Micro-

result of a Data Transfer Microprocessor instruction.

processor to issue a Set/Clear command that sets the

The A and B register contents are input to the ALU

Received Data Enable flip-flop, as shown. This is

where they are combined to form resultants.

used by the Receivers and Transmitters unit to gate

the next received character to the RC Silo input lines.
The ALU is made up of 74181 ALU chips, inter-

connected for carry bit propagation. ROM data bits

The flip-flop that sets the Resync Flag in bit 15 of the

00-05 are continuously decoded by the ALU. During

RC Silo is at E5-9. This flip-flop is set by a Set/Clear

execution

command and cleared with the next advance of the

of an

ALU Operation Microprocessor

instruction, these data bits define the ALU operation,

Master Scanner. It is used to generate the Resync flag

and the A/B resultant is strobed into ALU Result

character described in Paragraph 4.4.8.

Strobe L time.

4.8.1.6

M7836 (D1-6) - Shows the part of the BCC

Unit that generates the block check polynomials.
4.8.1.2

M?7836 (D1-2) - Shows the Entire A register

(A00-A17), ALU bits 08-17, and bits 0817 of the
~

ALU Result register. The A register is loaded from

4.8.1.7

the transfer bus by the B Register Clock pulse, issued

Unit that selects one of the block check polynomials,

at 02 time as a result of a Data Transfer Micro-

and shows the BCC Result register (BCC 00-BCC

processor instruction. ALU operation is described in

15).

M7836 (D1-7) - Shows the part of the BCC

Paragraph 4.8.1.1.

ALU bits 08-17 are strobed into ALU Result bits

4.8.1.8

M7836 (D1-8) - Shows the NPR Address

08-17 at Data Strobe L time.

4.8.1.3

00-07. The Transfer Bus consists of 74150 and 74151

the Transfer Bus at 02 time as a result of a Data
Transfer Microprocessor instruction. The contents of

selector/multiplexers. ROM data bits 04-07 select

the NPR Address register are gated to the Unibus

Decoder. The NPR Address register is loaded from
M7836 (D1-3) - Shows Transfer Bus bits

the register to be gated to the Transfer bus on when-

address lines via the 8838 transceivers by the Address

ever a Data Transfer or RAM Operation Microprocessor instruction causes assertion of the Transfer

to Bus signal from NPR control. Note that Bus Cl1
and Bus CO are loaded from ROM data 09 and 08

Source Enable L level.

(see Paragraph 4.7.7).

4-33

Table 4-8

DV11 Functional Unit-to-Drawing Cross-Reference
(Alphabetical)

DV11 Section

DV11 Functional Unit

Drawing(s)

4.8.18

~ Address Decoder

M7836 (D1-8)

ALU Result Register
A Register
Arithmetic and Logic Unit (ALU)
~ Asynchronous Registers
Baud Rate Generation

M7836 (D1-1,D1-2)
M7836 (D1-2)
M7836 (D1-1,D1-2)
M7833 (D4-2)
M7833 (D4-4)

4.8.1.1,4.8.1.2
4.8.1.2
48.1.1
48.54
4.8.5.6

M7836 (D1-6,D1-7)

- 4.8.1.6,4.8.1.7

M7836 (D1-7)
M7833 (D4-3)

4.8.1.7
4.8.5.5

M7839 (D4-2)
M7836 (D1-9)
M7837 (D2-6)

4.84.2
4.8.1.9
4.8.2.6

M7836 (D1-8)

Address Transceivers

B Register

M7836 (D1-1)

Block Check Calculation (BCC) Unit

BCC Result Register
Card Selection
Control Signal Decoder
DATI Register
DATO Register
Destination Decoder
Flag Detectors

Data
Handling
Section

Paragraph(s)

48.1.8

48.1.1

M7836 (D1-9)

4.8.19

M7838 (D3-6)
M7839 (D4-2)

4.8.3.6
484.2

M7833 (D4-3)

4.8.5.5

Interrupt Control
Interrupt Vector Output Gates

M7837 (D2-8)
M7837 (D2-6)

- 4.8.2.8
48.2.6

Line Control Register (LCR)

M7837 (D2-3)
M7838 (D3-2,D3-10)
M7839 (D4-4)
M7833 (D4-2)
M7838 (D3-5)
M7838 (D3-4)
M7838 (D3-1)
M7836 (D1-8)
M7837 (D2-7)
M7837 (D2-9)
M7839 (D4-8)

4.8.3.2
- 4823,483
4.8.4.4
48.5.4
4.8.3.5
4.8.3.4
48.3.1
4.8.1.8
4.8.2.7
4.8.2.9
- 48.4.8

Maintenance Register
|
Master Timing Generator
Master Scanner
|
Microprocessor Instruction Decoder
NPR Address Register
NPR Control
NPR Status Register/Silo (NSR)
Parity Error and Overrun Detectors

RAM Address Register

M7838 (D3-)

4.8.3.8

RAM Address Source Selectors
RAM Input Data Source Selectors
RAM Output Data Register
RAM Write Interlock

M7838 (D3-8)
M7838 (D3-8)

4.8.3.8
4.8.3.8

M7838 (D3-11)
M7838 (D3-6)

4.8.3.11
4.8.3.6

Random Access Memory (RAM)

M7838 (D3-9, D3-10)

Read Register Selector

M7837 (D2-1)

Received Character (RC) Silo

M7836 (D1-5)

4.8.39,4.8.3.10
4.8.2.1

4.8.1.5

Receiver Bit Window

M7839 (D4-2)

4.8.4.2

Receiver Interrupt Character Register (RIC)

M7837 (D2-9)

48.2.9

M7839 (D4-6, D4-7)

4.8.4.6

M7833 (D4-6)

4.8.5.8

Receiver Register Files

M7833 (D4-5)

4857

Receiver Selector

M7839 (D4-8)

4848

M7837 (D2-5)

4.8.2.5

Reserved Register

M7837 (D2-3)

4.8.2.3

Receiver Flags

4-34

Table 4-8 (Cont)

DV11 Functional Unit-to-Drawing Cross-Reference
(Alphabetical)

DV11 Section

DV11 Functional Unit

Drawing(s)

Paragraph(s)

Read-Only Memory (ROM)

M7838 (D3-1)

4.8.3.1

ROM Address Register

M7838 (D3-1)

4.8.3.1

ROM Data Register

M7838 (D3-2)

Secondary Register Selection Register (SRS)

M7838 (D3-8)

4.8.3.8

Set/Clear Signal Generator

M7838 (D3-3), M7837

4.8.3.3

(D2-3),
M7836 (D14)

48.1.4

SFR Input Gates

M7838 (D3-1)

4.8.3.1

Sync A/B Selector

M7839 (D4-1)

4.84.1

Synchronization Controls
o

M7839 (D4-6, D4-7)
M7833 (D4-5)

4.8.4.6
4.8.5.7

Synchronous Receivers
Synchronous Transmitters

M7839 (D4-6, D4-7)
M7839 (D44, D4-5)

4.8.4.6,4.8.4.7
48.4.4,4.8.4.5

4.8.3.2

System Control Register (SCR)

M7837 (D2-4)

4.8.2.4

Test Point Selector

M7838 (D3-2)

4.8.3.2

Timing Control

M7838 (D3-7)

4.8.3.7

Data

Timing Gates

M7839 (D4-3)

484.3

Handling

TMARK Register

M7839 (D4-8)

4.8.4.8

Section

Transfer Bus

M7836 (D1-3,D1-4)

48.1.3,48.1.4

(Cont)

Transmit Character Register

M7838 (D34)

4.8.34

Transmitter Flags

M7833 (D4-8)

4.8.5.10

Transmitter Selector

M7839 (D4-2)

4.84.2

TTL/EIA Data Converters

M7839 (D4-4, D4-5)
M7833 (D4-6, D4-7,

4.8.4.4
4.8.5.8

D4-8)

4.8.5.10

Unibus Data Mixer

M7837 (D2-6)

4.8.2.6

Unibus/Transfer Bus Interlock

M7838 (D3-7)

4.8.3.7

- Universal Asynchronous Receiver/Transmitter

M7833 (D4-9, D4-10)

4.8.5.11

4-35

Table 4-8 (Cont)

| DV11 Functional Unit-to-Drawing Cross-Reference
(Alphabetical)
DV11 Section

DV11 Functional Unit

Drawing(s)

Address Decoder

M7807 (D1)

Bits 0—3 Transceiver

Modem

Control
Unit

Paragraph(s)

4.8.6.1

4.8.6.7

Bits 4, 5, 6, 7 Register Selector

M7808 (D7)

4.8.6.7

Bits 5, 6, 7, 9 Transceiver

M7808 (D7)

4.8.6.7

Control Status Register (CSR)

M7808 (D7)

4.8.6.7,4.8.6.8

Hold Register

M7808 (D7, D8)

4.8.6.8

Interrupt Control
Line Status Register (LSR)
|

M7808 (D8)
M7807 (D3, D4, D5)

4.8.6.2
48.63,4.8.64,

M7808 (D9,D10,D11)

4.8.6.5,4.8.6.9,

M7808 (D7)

4.8.6.7
4.8.6.7

4.8.6.10,4.8.6.11

LSR/CSR Bits 0—3 Selector
Ring Counter

M7808 (D7)

Scan Memory

M7808 (D8)

TTL/EIA Converters

4.8.6.8

M7807 (D6)

4.8.6.6

M7808 (D12)

4.8.6.12

4-36

4.8.1.9

M7836 (D1-9) - Shows the DATI register, a
NPR data register which gates bytes as selected by

inverted to form read-only bit LCR 07 (Maintenance

Bit Window). The Maintenance Clock bit (LCR 08),
when set, permits the 74161 counter to count up to 16

NPR Address bit 00 from the Unibus to the Transfer

Bus. The register is clocked by the Data Strobe H

pulses of the 2.30.4-kHz clock, which (1) generates a

signal from NPR control (D2-7).

34-us Maintenance Clock Pulse during 8 of the 16
pulse intervals for maintenance mode 01 receivers
and transmitters, and (2) generates a carry which

An 8-bit extension (bits 08-15) of the DATO register

is also shown. Although NPR operations require
only DATO 00-07, the full 16-bit configuration is
used by the Microprocessor for temporary storage.

returns a pulse to clear LCR 08.
LCR 15, when set, enables a 320-ns one-shot to generate the Control Strobe, which loads LCR 09-14
into control storage for the line set in SRS 00-03. The

4.8.2

Unibus Data and NPR Control Drawing
Logic for the Unibus Data and NPR Control is con-

firing of the enabled one-shot occurs on the first
negative transition of a 9600 baud clock signal fol-

tained in drawing M7837, D2-1 through D2-9.

lowing the first positive clock transition.

4.8.2.1

M7837 (D2-1) - Shows bits 00-08 of the
Read Register Selector, which consists of 74151 selec-

tor/multiplexers.

Bits

AO01-A03

the

The 74155 Decoder interprets eight of the Set/Clear
commands specified by the Set/Clear Micro-

Unibus

- processor instruction. The Set/Clear Signal Gener-

address are gated to the Read Register Selector to
select one of the eight programmable DV11 Data
Handling Section registers to be gated onto the

ator is described in Paragraph 4.8.3.3. This drawing is
also the source of all data taken from the Unibus.

Unibus data lines. The eight programmable registers

4.8.2.4

M7837 (D2-4) - Shows System Control register bits 00-15. All flip-flops shown are cleared by

are as follows:

Initialize; some are also cleared by other sources. The
ROM Single Step bit, SCR 01 (E66 pin 5), is cleared

SCR - System Control' Register

microinstruction cycle 01 time (D3-6), which
occurs just after SRC 01 is set (a maintenance fea-

RIC - Receive Interrupt Character Register

ture). Setting of SCR 08 (Receiver Interrupt Service

- LCR - Line Control Register

Complete) causes SCR 07 (Receiver Interrupt) to
clear (E15 pin 6).

SRS — Secondary Register Selection Register

The 74121 one-shot (E24) enables loading of SCR 15
by the Load SCR High Byte signal whenever SCR 09

SAR - Secondary Register Access Register (i.e.,

the output data lines from the RAM)

(Bit 15 Write Enable) is set (refer to Table 5-6). Logic

SFR
- Special Functions Reglster (i.e., the out-

i1s provided to enable combinations of the several
interrupt bits (as SCR 07, Receiver Interrupt) to gen-

put data lines from the ROM)

erate interrupt requests (A Request/B Request).
Assertion of Temporary Disable L from Interrupt
Control (D2-8) disables A Request and B Request

NSR - NPR Status Register/Silo

(see Paragraph 4.6.4).

RIR - Reserved Register

4.8.2.5

M?7837 (D2-5) - Shows the Register Decoder, which interprets the Direction Selection bits (CO,

4.8.2.2

M7837 (D2-2) - Shows bits 10-15 of the
Read Register Selector. Read Register Selector func-

Cl1) and the 4-bit register and byte selection code in

Unibus address bits AO0O-A03 to enable the PDP-11

tion is described in Paragraph 4.8.2.1.

program to read and write the programmable regis-

ters. If the PDP-11 program has selected a programmable

4.8.2.3

M7837 (D2-3) - Shows bits 07-15 of the
Line Control Register (LCR), eight outputs of the

Set/Clear Signal Generator, and the Reserved Register bits (RIR 00-07). The Bit Window L signal from

the Synchronous Receivers and Transmitters unit is

for

reading

and

the

Instruction

Decoder Enable L level from the Unibus/Transfer
Bus Interlock is asserted, the Register Decoder sends
Read Register H-and Data-To-Bus H signals to the
Unibus Data Mixer (D2-6) to gate the selected regis‘ter data to the Unibus.

4-37

‘\_\

tion may be written by the PDP-11 program:

LCR - Line Control Registér
input data lines to the RAM)

SFR - Special Functions Register (i.e., ROM
|

RIR - Reserved Register
SRS - Secondary Register Selection Register
(byte-addressable)

~SCR

System Control

Assertion of the Vector to Bus L level from Interrupt

Control causes the switch-selected vector address bits
to be gated to the Unibus.

4.8.2.7 M7837 (D2-7) - Shows the NPR Controls;
this logic is described in Section 4.6.

‘SAR - Secondary Register Access Register (i.e.,

Data Register)

DV11 does an NPR transfer (NPR Data to Bus L
asserted), NPR ADDR 00 H selects two of the four
74157 ICs, thus gating the eight DATO bits into the
appropriate byte position (high byte or low byte).

addressable)

The Register Decoder also interprets the NSR selec-

tion code and generates a Read NPR Status H signalwhich serves to read the NSR Status to the Unibus
and to propagate the contents of the NSR Silo
“down” by one position (see Paragraph 4.8.2.9).

4.8.2.6 M7837 (D2-6) — Shows the DATO register
(E34, E40), the Unibus Data Mixer (E27, 33, 34, 41),
and the Interrupt Vector output gates. The Unibus
Data Mixer (the 74157 2-to-1 multiplexers) selects the
an NPR transfer)
DATO lines (DV11 is performing
is reading
program
or the Data for Bus lines (PDP-11
to
Selector
Register
Read
the
a DV11 register) from
the
whether
on
depending
gates,
the Unibus input
NPR Data to Bus L or Read Register H signal,
respectively, is asserted. In either case, the Data to
Bus H signal will be asserted and the Unibus Data

4.8.2.8 M7837 (D2-8) - ShOws the Interrupt Con-

trols; this logic is described in Section 4.6.

M7837 (D2-9) - Shows the Receiver Interrupt Character register (RIC) and the NPR Status
Register/Silo (NSR). The NSR is an 8-bit silo 64
characters deep, composed of two 3341 propagable
register modules, plus a single flip-flop for storing

4.8.2.9

NSR 15, the NPR Status bit.

The line number in NSR 00-03 is obtained directly
from the Master Scanner. The interrupt code in NSR
08-11 is obtained from an intermediate 4-bit store
(74175 module) that holds the selection code for the
last secondary register accessed by the Micro-

processor (hence, the use of RAM Output Data
Clock). The Data Transfer microinstruction gates an
entry into the NSR silo by generating an NPR Status
Register Reporting Clock pulse at 02 time. If the
NSR silo is not already full, a 180-ns one-shot is
fired, gating the entry (line number and interrupt
code) into the NSR silo. The entry propagates down
toward the NSR silo output (“bottom” of the NSR
silo). When an entry reaches the NSR silo output, the
NSR 15 flip-flop lead is conditional so that NSR 15
sets on occurrence of a Read NPR Status H signal.
When the PDP-11 program reads the entry at the silo
output, a Read NPR Status H signal is generated,
serving to (1) set NSR 15 if an entry exists at the Silo

output, and (2) gate NSR 15 to the Unibus. At the
conclusion of the NPR Status H signal, a 110-ns
pulse is generated to clear the entry that was just read
from the Silo, thus propagating down any subsequent

Mixer output lines will be gated to the Unibus.

entries. (NSR 15 is cleared.)

Note that the DATO is an 8-bit register and that each
output bit is connected to a high byte position and a
low byte position (i.e., DATO register bit 00 (E34,
pin 15) is connected to both the Unibus Data Mixer
for Bus Data 00 and for Bus Data 08. When the

4.8.3

ROM, RAM, and Branch Drawing

Logic for the ROM, RAM, Microprocessor branching and associated controls and storage is contained
|
in drawing M7838, D3-1 through D3-11.

4-38

If the PDP-11 program has selected a programmable
register for writing and the Instruction Decoder
Enable L level from the Unibus/Transfer Bus Interlock is asserted, the Register Decoder generates an
enabling level to load the selected register. For the
byte-addressable registers (SCR and SRS), A0O is
interpreted to select the specified byte. Six of the programmable registers in the DV11 Data Handling Sec-

4.8.3.1

M7838 (D3-1) - Shows the ROM, the ROM
Address register, and the Special Functions Register

4.8.3.3

(SFR) input gates. The ROM consists of eight 5603

appear in M7836 (D1-4), and M7837 (D2-3). ROM

M7838 (D3-3) - Shows three-fifths of the

Set/Clear Signal Generator (the remaining portions

ROM modules, each of which contains 256 4-bit

Data bits 00-07 define the 74155 to be used for the

characters.

set/clear operation, which is enabled at Data Strobe

Each

group of four

5603

modules

(arranged horizontally on the diagram) comprises a
single 256 X

L time.

16 ROM; thus the aggregate DV11

ROM consists of two 256 X 16 ROM:s.

4.8.3.4

M7838 (D3-4) - Shows the Transmit Char-

acter register and the Master Scanner. The Transmit

The ROMs are addressed in an interleaved manner

Character register is loaded from the Transfer Bus by

by a

(ROM

the Transmitted Data Bus Clock L signal, generated

Address register) consisting of three 74193 modules.

by a Microprocessor Data Transfer instruction. A

The counter is stepped by 01 pulses from Timing
Control to access ascending locations in the ROMs,

load the register contents into the selected transmitter

alternating between ROMs to access contiguous locations within each ROM. If a point tested by a Branch

Transmitter strobe is routed to the logic on the

9-bit,

end-around

binary

counter

300-ns Transmitter Strobe H pulse is generated to
on the line selected by the Master Scanner. The

Microprocessor instruction is true, the counter is
loaded in parallel at 02 time from ROM Output Data
register bits 00-07 plus 15.

M7839/M7833 “line cards.”

The Master Scanner is a 5-bit, end-around binary

counter implemented with two 74193 modules. The

If SCR 03 (ROM Data Soufce) is set to one, ROM

Master Scanner is incremented each time the micro-

outputs are disconnected (caused to float), and the

program enters the Idle Loop to service either the

data lines from the Unibus (Buf Data 00-15) are
gated to substitute for the ROM output data lines.

transmitter or the receiver for a line. Thus, the loworder bit is used to specify the transmit or receive
function for the line, and the four high-order bits

4.8.3.2

M7838 (D3-2) - Shows the Microprocessor

reflect the line number.

Instruction Decoder, Test Point Selector, and ROM
Output Data register. The Instruction Decoder inter-

4.8.3.5

prets bits 12-14 of the ROM Output Data register

generators. Microprocessor timing is provided by the

and generates signals to enable execution of Micro-

20 MHz signal. Internal baud rates are generated by

processor instructions.

M7838 (D3-5) - Shows the master timing

counting down the 5.0688 MHz signal with the 7492
frequency divider and the 7493 and 74161 4-bit bina-

The Test Point Selector consists of two 74150 selec-

ry counters. The 74161 is connected to a divide-by-11

tor/multiplexers. If a Branch A or Branch B instruc-

to produce a 460,800 Hz signal. The 7493 divider

tion is interpreted, the corresponding 74150 module
will decode the test point selection bits (ROM Data

signal (called 230.4 kb) for use by the LRC 08

(E106) divides that by two to produce the 230,400 Hz

08-11) and assert a Branch A L or Branch B L signal,

Maintenance Clock Pulse circuit (Paragraph 4.8.2.3).

respectively, if the test point is true. These are ORed

The 230,364 Hz signal is divided by 4, producing a

together and stored as a Branch Point True H level at
T50 time. Branch A L and Branch B L form bits 00

where it is divided by 3, 6, and 12, to obtain 19,200

and 01, respectively, of the Line Control register (for

- Hz, 9600 Hz, and 4800 Hz, respectively. The 4800 Hz

57,600 Hz signal; this is input to the 7492 (E105)

maintenance).

signal is divided further by the 7493 (E100). The baud

rates shown provide a “times one” clock to the synchronous “line cards.”
The ROM Data register is loaded at 03 time if the

Microprocessor

is operating (SCR 00=1). The
Microprocessor executes the instruction in the ROM

4.8.3.6

Data register at the next 02 time. When running a

Output Data Clock, and the RAM write interlock.

M7838 (D3-6) - Shows the Data Transfer

microinstruction

maintenance program, SCR 03 (ROM Data Source)

Destination

Decoder,

the

RAM

The destination decoder is a 7442 4-to-10 line decoder

is set to one, and the Unibus data lines are gated to

which decodes the destination bits of the Data Trans-

the ROM Data register, which is then loaded by the

fer microinstruction and generates a strobe to load

Load SFR L signal from the Register Decoder. The

the specified register at 02 time. The RAM Output

maintenance program then sets ROM Single Step
(SCR 01) to one, causing the Microprocessor to exe-

Data Clock is generated at 02 time
as a result of a

RAM Operation Microprocessor instruction with bit

cute the instruction in the ROM Data register.

08 cleared.

4-39

The RAM write interlock prevents the Micro proc-

essor from writing into

a RAM location until the

Output Data Clock L pulse from the RAM
Read/Write Control. When RAM outputs bits 00-14

Microprocessor reads the latest data written into that

equal zero, a signal is generated to enable detection of

location by the PDP-11 program. Microprocessor

zero byte counts. RAM output bits 00-07 may each

RAM operations are described in Section 4.7.

set or cleared by the Microprocessor,

using

Set/Clear Microprocessor instructions.
RAM write activity by the PDP-11 program is stored

in a 256-bit 3106 “footprint” store. Each time the

4.8.4

Unibus writes data into one of the 256 RAM regis-

Drawing

ters, a bit is stored in the footprint store at the loca-

Logic for the Synchronous Receiver and Transmitter
unit is contained in drawing M7839, D4-1 through

tion corresponding to the addressed RAM location.

When the Microprocessor attempts to write into the

Synchronous

Receivers

and

Transmitters

location of the footprint store. (When the micro-

D4-8. The drawing shows the logic for lines 00-03,
contained on a single line card, and is typical of the
remaining three line cards, which implement lines
04-07, 08-11, and 12-15, respectively, of a full 16-line
synchronous DVI11 system. Selection signal names
reflect the 4-lines-per-card organization: the two
high-order bits of the Master Scanner and the SRS
register are considered to select individual four-line
cards; the low-order bits select one of four lines on

program attempts to invite a RAM location and finds

the card.

same

location

without

having

read

the

Unibus-

updated data stored there, the output of the footprint
store inhibits the RAM Write Enable pulse and sets
the Write Inhibit flip-flop for sampling by the Test

Point Selector. After the Microprocessor performs a
read at the same location, Write Inhibit is cleared and
the inhibit bit is removed from the corresponding

Write Inhibit set, it branches back to read the con-

tents of that RAM location again and updates the

4.8.4.1

new copy.)

Do not access a specific RAM location more than

Code selection switches and the Sync A/B Selector.
The zero or one state of LCR 10 selects the Sync A in
Sync B switch settings, respectively, as the sync character. The sync character is loaded into the Fill Character holding registers of the four synchronous
transmitters on the line card and the Match Character holding registers of the synchronous receivers by

once every 17 Unibus instructions.

the LCR 15 Control Strobe.

Do not spin on secondary flags.

4.8.4.2

NOTE
Footprint circuit operation results in the following pro~~ gramming restrictions:

4.8.3.7
Bus

M7838 (D3-7) - Shows the Unibus/Transfer

Interlock and Timing Control. This logic is

M7839 (D4-1) - Shows the Sync Character

M7839 (D4-2) - Shows the Flag Detectors,
Receiver Bit Window, Transmit Data Leads, and

Control Signal Decoder. The Flag Detectors route
four flag lines. from the receiver and transmitter

selected by Master Scan bits T/R and 00-03 to the

described in Section 4.7.

Microprocessor:
4.8.3.8

M?7838 (D3-8) - Shows the Secondary Regis-

ter Selection register (SRS), the RAM Address Regis-

Data Not Available (transmitter idling)

Tran Flag Waiting (transmitter ready for

ter (RAR), the RAM input data source selectors and
the RAM address source selectors.

another character)
4.8.3.9

M7838 (D3-9)

Shows

storage for bits

00-08 of the DV11 RAM. Each 256-bit 3106 RAM

Match Detect (receiver has detected a
sync character)

module stores a single bit (e.g., bit 00) for all 16 registers for all 16 lines.

4.8.3.10 M7838 (D3-10) — Shows storage for bits

Receiver Flag (receiver has completed
assembly of a character).

09-17 of the DV11 RAM. Note that RAM output
bits 16 and 17 from LCR bits 04 and 05, respectively.
4.8.3.11

M7838 (D3-11) - Shows the RAM Output

Data register. The register is loaded by the RAM

The Receiver Bit Window routes the data input on
the line selected via the SRS leads to LCR 07 if internal maintenance mode 01 has been selected via LCR
11, 12.

4-40

The Control Signal Decoder loads the Resync flip-

The internal Baud Rate Clock drives the SCTE leads

flop and the TMARK flip-flop for the selected line or

in all operating modes except internal maintenance

receipt of the respective commands from the Micro-

mode O1. In mode 01, SCTE leads are driven by LCR

processor. The Control Signal Decoder also routes

08. In maintenance mode 10 (external), the internal

300-ns Buf RDE and THRL pulses to the selected

clock is turned around with a H325 test connector.

line’s receiver or transmitter, respectively. The Buf
RDE

the

In half-duplex operation is manually selected for a

Receiver flag. The THRL pulse loads the synchro-

(Received

Data

Enable)

signal

resets

line, the Clear to Send lead from the line’s transmitter

nous transmitter’s holding register with the data from

(SAT pin 17) inhibits the RX clock. The inhibits are

the Transmit Character register (this is the Trans-

labeled TMARK 00-03 on the drawing, but are

mitter Selector in Figure 4-1). Buffer gates are pro-

actually connected to the Clear to Send leads of the

vided for the transmit data leads to the synchronous

transmitters.

The drawing also shows the distribution of the LCR

4.8.4.4

15 Control Strobe to the synchronous receiver and

transmitters for lines 00 and 01, the Maintenance reg-

M7839 (D4-4) - Shows the synchronous

transmitter for the line selected by SRS 00-03. The

ister, and the TTL/EIA Data Converters for bits

- Strobe 00-03 pulses are used to load LCR 13 (Receiv-

00-01.

er Enable) into the Search Sync flip-flop for the

cussed in Appendix C.

Synchronous transmitter operation is dis-

selected receiver. These strobe pulses also load the

selected transmitter Fill Character holding register,

and the selected receiver Match Character holding

Maintenance register stores LCR 09, 11, 12, 14 for

receipt of the

LCR

Control

Strobe,

the

each 4-line group of transmitters and receivers on the
line card. Bit assignments are as follows:

4.8.4.3

M7839 (D4-3) - Shows the Timing Gates,

which select one of three clock sources for the syn-

LCR 09: Transmitter Disable

chronous receivers and transmitters:

LCR 11, 12: Maintenance Mode

LCR 14: Maintenance Data

the EIA input lines,

LCR 08, the Maintenance Clock pulse

4.8.4.5

generator, or

transmitters and the TTL/EIA Data Converters for

M7839 (D4-5) - Shows the synchronous

lines 02-03. Synchronous transmitter operation is
3.

the

manually-selected,

internal

discussed in Appendix C.

DVI11

clock (1200, 2400, 4800, 9600 baud rates
available).
4.8.4.6

The TX Clock 00-03 lines and the RX Clock 00-03

M7839 (D4-6) - Shows the synchronous

receivers and the Synchronization Controls for lines

lines convey the selected clock signals to the trans-

00-01. Synchronous receiver operation is discussed in

mitters

Appendix C.

and receivers,

respectively.

If an internal

maintenance mode is selected (Mode flip-flop 00=1),

The Synchronization Controls consist of a Receiver

the EIA inputs are inhibited at pins E15-11, E15-8,
E15-3, and E15-6 for the TX lines and at E4-6, E4-3,

Flag flip-flop, a Search Sync flip-flop and two Resync

E4-11,

flip-flops for each line. When the receiver detects a

and

E4-8

for the RX lines. The selected

Maintenance Clock source (LCR 08 in maintenance

sync character, MDET (Match Detect) is asserted. If

mode 01, or the internal Baud Rate Clock in mainte-

the 1 Sync selection switch has not been set (OFF

nance mode 11) is then gated to the RX and TX lines.

position), the Receiver flag sets. The receiver is now

Note that maintenance mode 01 occurs when mode

framing characters, and the next character asserts

00 flip-flop is set to one and mode 01 flip-flop is reset

DR (Data Ready). If the 1 Sync selection switch has

to zero. Thus, the mode 00 flip-flop is the low order

been set (ON position), the Receiver flag sets in

bit of the maintenance mode and the mode 01 flip-

response to Data Ready being asserted rather than in

flop is the high order bit of the maintenance mode.

response to Match Detect being asserted.

4-41

The PDP-11 program sets LCR 13 (Receiver Enable)

contain 5, 6, 7, or 8 data bits, one or two stop bits,

coincident with an LCR 15 control strobe to set the

and either odd/even parity or no parity. The baud

Search Sync flip-flop for the selected line. This pro-

rate, bits per character, parity mode and number of

duces an assertion at pin 28 (SS) of the receiver. The

stop bits are programmable via the system registers

receiver synchronizes internally on the positive edge

and the PDP-11 program. Consult Appendix B for

of the RX Clock, then shiftsin a new bit on the nega-

complete information on this unit.

t1ve edge

4.8.5.2

M7833 (D4-1 - D4-10) — The drawing shows

To resynchronize during reception, the SS lead must
be asserted during a positive transition of the RX

the logic for lines 00-03 contained on a single board,

Clock. The Microprocessor sends a Resync pulse

contain

and is typical of the remaining three boards which
lines 04-07, 08-11, and 12 through 15,

which direct-sets the Resync 1 flip-flop, serving to (1)

respectively, as a full 16 line asynchronous system.

produce the required negation at the receiver’s SS

Again, as with the synchronous system, selection sig-

lead, (2) clear the receiver’s status flags (OE and PE),

nal names reflect the four lines per card organization:

and (3) reset the Data Ready lead (pin 26). The next

the two high order bits of the Master Scanner and the

positive transition of the RX Clock sets the Resync 2

SRS register are considered to select individual four-

flip-flop (either Resync 1 set or Resync 2 set causes a

line cards; the low order bits select one of four lines

negation at SS). Resync 1 resets on the first negative

on the card

edge of the RX Clock following the Resync pulse;
Resync 2 is toggled by positive edges of the RX

4.8.5.3

Clock.

the chart for clock generation.

At the negative transition of the RX Clock, the

4.8.5.4

receiver goes out of synchronization and negates

registers, strobes,

Match Detect. Resync 2 is reset by the next positive

selected line cardis decoded by SRS (most srgmficant

edge of the RX Clock, causing an assertion at the SS

bltS) according to the following (E68):

M7833 (D4-1) - Shows the regulators and

M7833 (D4-2) - Shows the card selection,
and initialization circuitry. The

lead. Thus, the next positive transition of the RX

Clock causes internal receiver synchronization, and

SRS 03

SRS 02

on the negative transition immediately following, the

Selected Line Card
00-03

first bit is shifted in and the receiver starts looking for

04-07

a match character.

- 08-11

12-15

4.8.4.7

M7839 (D4-7) - Shows the synchronous

receivers and the Synchronization Controls for lines

The selectionf of one of four registers for each of the

02-03. Synchronous receiver operation is discussed in

lines is accomplished by LCR 09 and LCR 10 (E52).

Appendix

The

Synchronization

Controls

described in Paragraph 4.8.4.6.

are

Format
4.8.4.8

M7839 (D4-8) - Shows the Receiver Selec-

tor, the Parity Error, and Overrun Detector, and the
TMARK register. When asserted, the

Baud Rate

Maintenance

|
|

LCR 10

LCR 09

TM ARK bits

set the selected lines to the MARK state.

The control strobe circuitry is indicated at the bottom
left of D4-2. The selected line card gates the strobe

4.8.5

Asynchronous Receivers and Transmitters

pulse to the selected lines register (Primary, Format,

etc.) as directed by bits LCR 09 and LCR 10. Control
4.8.5.1

Universal

Asynchronous

Receiv-

er/Transmitter (UART)- The UART is a full duplex

device with transmit and recieve sections. UART is
an LSI subsystem which accepts binary characters

from either a terminal device or a computer and

strobe, a 300 ns pulse originating on D2-3,
is widened
to 400 ns by one shot E59, to accommodate format
register requirements (UART strobes). Since there
are 16 registers per line card (4 registers per line X 4
lines per card), a 4-line-to-16 line decoder (E52) is

transmits /receives this character with control and

used to direct the Control Strobe pulse to the selected

error detecting bits. Input or output characters may

4-42

The four 4-bit primary registers (E24, E13, E8, and

During the transmit service routine, the

E14) are comprised of quad double rail output latch-

microprocessor presents a character to the

es (74175). Each primary register, consisting of one

line card for transmission plus an associ-

74175 unit, is four bits wide and stores the bits

ated transmitter strobe pulse to load that

defined by LCR 11 through LCR 14.

character into the selected transmit register file. Tran File Load L, generated at

The four maintenance reglsters each one b1t wide,

E68-6, is the register file pulse. Register

consist of E35 and E34 (7474) on D4-2. These units

file is then decoded to Tran File clock.

are loaded when LCR 11 is “1.”

(See ALC D4-8 for discussion of these

signals.)

The Format register is physically located in the

UART, while the Baud Rate register is located in the

Receiver Flag L (UART) - Active low at

Dual Baud Rate Generator (COM 5016). Both regis-

E82-1 when the selected receiver has a

ters are of 4-bit capacity. Initialization of the DV11

‘Receive Flag or Match Flag present (at

E37) and the Master Scan T/R signal is

clears only the Primary and Maintenance registers.

positioned to the receiver section.
4.8.5.5

M7833 (D4-3) - Shows the Card Selection

and Flags logic. This circuitry comprises functions

Match Detect L (UART) - Active low at

required
by the line card for communication with the

E82-4; this signal is used by the micro-

rest of the DVI11 multiplexer. Line card selection is

processor to update status of the selected

performed by the decoding of the Master Scan 02 and

line.

03 bits as follows:

During assertion of the Receiver Enable line (Primary register bit 13), the Match flip-flop, E36-9, is

Master Scan

Selected Line Card

00-03

04-07

08-11

-0

12-15

turned on. The turn-on of the Match flip-flop (7474)

then simulates a receiver flag and asserts Match

Detect L. Both of these signals must be present for

the microprocessor to be synchronized with the line

via the Receiver Active bit in the Line State secondary register.

The microprocessor provides Master Scan C and
Master

Scan

D signals

corresponding

After the microprocessor has set its receiver active

com-

bit, it then sets and clears the Received Data Enable

plementary logic levels of Master Scan 02 and 03,

flip-flop (E97 on D1-5). The Receive Data Enable

respectively. The C and D lines are applied to E68.

flip-flop output is then routed to one of two locations
to clear the logic that caused a receiver flag. Upon
system initialization (startup), the Match flip-flop

Also supplied by the microprocessor are two low
order bits, Master Scan 01 and 02 for per line selec-

tion. The latter signals are applied to E73, and, via

(E36) is cleared and subsequent Receive Data Enable

the inverters to the scan section multiplexers E60,

signals clear the appropriate Receive Flag indicator

E37, E31, and E83. The Master Scan T/R signal gen-

for the receiver register file. The actual logic for this

erated at E73-4 permits individual selection of either

function is on D4-5 and essentially switches the rising

the receive or transmit side of a line.

edge of Receive Data Enable with the output of the
selected match multiplexer (E31) on D4-3, and E30
and E20 on D4-5.

The ,»micr(‘)processor requires three flags from the

Settmg the Match flip-flop (E36) causes the output of
a 75 ns single-shot (E63) to be decoded as CLR
MATCH L (E31) to the selected line. Absence of the
Match flip-flop set condition generates the CLR
RCV FLAG L (E31) which is routed to the Receive
Flag for the lines (E44, E26 on D4-6). See descriptions of these functions in D4-5 and D4-6.

ALC logic. Two of these flags are generated by the
UARTs and include:
1.

Tran Flag Waiting L (UART) - Active

‘low (at E82-10) when the selected transmitter has an empty register file and Master Scan T/R is in the T state.

4-43

4.8.5.6

M7833 (D4-4) - Shows crystal and clock

A priority scheme, mechanized in E71, E75, and E64,

generation circuitry. The transmit and receive sec-

is utilized to convert the three types of errors into a 2-

tions of a UART share a common clock. The clock

bit error field for the microprocessor. Write addresses

pulse may have two origins:

associated with the 10-bit words are specified by a

9318 priority encoder, E48 (see D4-6). The 9318 gen1.

COM 5016 Dual Baud Rate Generator

erates Receive File Address leads 00 and O1. In con-

2.4576 Crystal Oscillator

junction with D-type flip-flop E36-6 and single slots
E38-4,

and

E38-12,

the 9318

also generates

the

The COM 5016 Dual Baud Rate generator is the

Receive File Load L signal which causes data to be

clock source for all frequencies from 50 to 9600 baud.

written into the Receive register files.

Each of the COM 5016s may generate two clock frequencies (for receive and transmit) which depend on

Coincidence of the CARD FLAG SELECT 00-03 L

the bit content of LCR 11-14 and a corresponding

and DATA ENABLE 00-03 H signals causes reading

BRG STROBE. The output frequency is thus pro-

of the Receive register file. Presence of these lines

grammable by the PDP-11 program. See Figure 4-10.

indicates that the Master Scanner has selected this

LCR 11-14 H frequency select bits are presented to

module to read the receive character and its associ-

the COM 5016 (ES1 and E57) together with the input

ated error field into the microprocessor Received

from

Character Silo. Data Enable 00-03 H gates the signal

a 5.0688

MHz

oscillator

(E27).

After

the

through the 8881 driver circuitry.

selected frequency has been specified, the clock pulses
are distributed to the ALC via tri-state gates (E56 and
ES0).

The Match/Active logic consists of E2, E29, E23,

The 38.4K baud clock rate uses a 2.4576 MHz

logic are used to enable reception. The RCVR ENBL

E10, E25, and E15. These four common sections of

oscillator (Y1) and frequency divider E92. Selection

signal, when cleared, holds both the Match and

of 38.4K baud is indicated when BUF LCR 11-14

Active flip-flops cleared. The positive-going transi-

contains address 17. See Figure 4-11. Address 17 is

tion of RCVR ENBL triggers a single-shot (74123)

decoded by E39 and conditions the SPEED flip-flops

E2 or E10 while the trailing edge of the smgle-shot

E45 and E55. Then the appropriate flip- flopis set by

sets the Match flip-flop.

BRG STROBE.

The setting of the Match flip-flop and receiver flag
simulation has been described in D4-3. Setting the

The SIGNAL SPEED 17 H signal disables the con-

trol line of the selected 8093 by gating its output into

Match flip-flop causes the associated line Active flip-

the high impedance state. Simultaneously, it enables
the control line of the selected 8094 by gating its output into the low impedance state. The 38.4K baud

flop to set. The output of the Active flip-flop is utilized on the direct clear of the receive flag indicator on

clock

indicating a receive flag to the DV11 microprocessor.

appears

D4-6 (E44, E26) to enable/disable the line from

at the selected line output (D4-4

CLOCK 00-03 H).

A resync pulse (RESYNC PULSE 00-03 L) at E30,
E20, clears both the Active and Match flip-flops thus

4.8.5.7

M7833 (D4-5) - Shows the receive files,

shutting down the appropriate line.

receive data, and match logic. The Receiver register
files E54, E95, E94, are used to buffer store the
received data characters from the UARTS prior to

4.8.5.8

read-in by the microprocessor. The receive register
file 1s a 12-bit register which presents eight data bits

viced by this logic. The receiver flags for the four lines

and a 2-bit error field to the microprocessor. The

clocked to the 1 state when the receiver servicing logic

M7833 (D4-6) - Shows the Receiver Flag

Service logic. The UART receiver sections are serare the 7474 flip-flops E44 and E26. These units are

UART actually feeds three error lines to the receive

reads a character from the UART. Upon reading of

the register file by the microprocessor, the corre-

sponding flag is cleared. CLR RCV FLAG L is genFraming Error

erated at E31 (D4-3) andis ORedin E32 with the set

Parity Error

side output of the Active flip-flop (E29, E23, E25, or

Overrun Error

E15) to provide the clearing logic for the flag.

4-44

BRG

GENERATED

STROBE

D4-2 WHEN

THE BAUD RATE REGISTER
AND THE SRS.LINE NUMBER
ARE SELECTED, ONLY

IS SELECTED.

STT

lcm

DESIRED HALF OF COM. 5016

O3 H

ADDRS

BRG CLOCK

LINE 03

fi’>__ EXT __ _ __ _E5Y
D

COM
5016

CLK
:> ?ADDRS
J

BRG CLOCK

LINE 02

STR

BRG

STROBE 02
H
E27

5.0 688 MHZ

DIP
e
BRG
STROTE

O1H

STT

4 BIT BUFFERED BCD WORD
FROM

LCR

CLK

ADDRS

LINE

e
COM
5016

iILDERS

SELECT DESIRED SPEED

FR |

BRG CLOCK

-INE 00

STR

BUF LCR 14

BUF
BUF

LCR
LOR

13
12

H
H

BUF

LCR

BRG

STROBE OOH
TO SPEED CODE 17 SELECTION

11-4410

Figure 4-10

Block Diagram of Baud Rate Generator

Selection Circuitry for Lines 00-03

"The error encoding function is performed by E64.
Status of OR and PE, the error field for the three
inputs is shown in the following table:
Priority Encoding Table

OR
L
L
L
L
H
H
H
H

UART Errors
FE | PE

74157 (pin 1)

L
H
L
H
L
H
L
H

SO=L=A
L
SO=H=B
H
L
L
L
L

L
L
H
H
L
L
H
H

*Low = Logical one

4-45

*MASTER
PE
OR
H

H No Error

H
L

L
L

L
H

L
L
L

H
H
H

CRKT.

0SC

—

614.4KH

(8AUD)

BAUD

[

—

H—G

E39

2]|E50 &

(FROM THE COM 5016)
TO

BUF LCR11 H—

— v

SELECTED

SPEED TO

UART RECEIVER &
TRANSMITTER CLOCK INPUTS
6

7474

3 .

CLOCK 03 H

J{l

E45

eresTROBE

CP2 D4-4

2|D

8093

REMAINING

7474's

BUF LCR 14 H——

BUF LCR 13

£28

GENERATION

SELECTION

BUF LCR 12 H—
- 7420

@—'
U3
!

BRG CLOCK LINE O3|

SPEED CODE 17

38.4K

TO
o
REMAINING
r 8094'S

(38.4K) |

2 4576 Mz | E22
7493

e e

l
|
l

SPEED
_D4-4
1703

5
o_

ols

03 H

|
14

RESET

(CLEARS ALL 7474's USED IN)

(SPEED 17 SELECTION UART)
(CLOCK WOULD THEN BE DERIVED)
(FROM THE BRG CLOCK.)
11-4411

Figure 4-11

Typical UART Clock Selection for Line 03

The latter signal is generated at E41-4 via E41-12.

- Timing for the receiver essentially is centered around
two serially connected single-shots (E4) which cause

Presence
of a UART DA flag causes one or more of

the outputs of quad D-type flip-flops (E49) to be

the flip-flops (E49) to be set, Active LOW outputs

-sampled. The flip-flops are controlled by E43 which

from E49 are then furnished to the Priority Encoder.

switches Data Available (DA 00-03 L) and RCV

Group Select L, at E48-14, is generated when the

FLAG 00-03 H. The data available lines originate in

‘encoder has an active input and is fed back to the
Sample Clock input, E42-10, to prevent retriggering

“the UART.

of the Sample Clock input until the current cycle has
A typical timing sequence is now described. Control

been completed.

logic is shown on the bottom half of D4-6. The
RESET L line from D4-2 results from the INIT D1

The active LOW Group Select line sets the Receive

signal (E7-12 on D4-2). When RESET L goes HIGH,

Data Enable (RDE) flip-flop, E36-6, which in turn

the clear input of E49 goes HIGH. The expiration of

output retriggers Sample Clock if UART Data Avail-

activates the Received Data Enable lead, RDE
L, of
the selected UART. RDE L triggers a 560 ns RDE
DLY single-shot (E38-4). The RDE L line permits
enabling of the eight receive data output signals from
the UART. Output of RDE Delay at E38-4 triggers
the LOAD FILE single-shot whose output in turn
clocks the UART character into the Receiver register

able flag is not present.

file for the indicated address (D4-5).

RESET L is delayed by 30 ns
in DL 1 and then causes
a rising transition on the Sample Clock single-shot
E4-13. E4-13 produces a 100 ns clock pulse routed to
E49-9 to sample the flip-flop outputs. Expiration of

sample clock triggers Sample Delay (E4-5) whose

4-46

The Receiver file load single-shot then triggers a 600

(EOC) is a UART generated signal that is LOW dur-

ing the time a character is transmitted. UART EOC

RESET DA single-shot E41-12. The negative

going edge of E41-12 is routed to the following

is then inverted and switched with the HIGH side of

locations:

the HALF DUPLEX flip-flop (D4-2) to generate a

HIGH level (markmg) condition to the UART serial-

Direct clears the RDE flip-flop at BE36-1,

in lead

which disables Receive Data Enable,
2.

Decodes the Reset DA pulse via E61-2;

4.8.5.10

and,

may be separated into the following areas:

Sets a Receiver Flag and triggers the Wait

Delay single-shot E41-4. Output from the
latter unit clears the flip-flops (E49) and
furnishes a logic LOW to the delay line

circuitry as discussed above. Clearing of

the 74175 flip-flops removes the active
inputs of the encoder causing the Receive

single-shot

Remote Stop Logic

per line character that the microprocessor presents to

causes

‘the line card. The write address leads of the file are

SAMPLE DELAY to retrigger again to

Flag Indicators
Timing Circuitry

ter files (74170), E78 and E77, are utilized to store the

to go HIGH. Subsequent timeout of the
DELAY

Transmit Register Files

Transmit Register Files — Two 4-bit by 4-word regis

file address lines and Group Select signal
WAIT

M?7833 (D4-8) —Shows the Transmit Flag

Servicing logic. Transmitter flag servicing functions

determined by the two low order Master Scan lines,

service the next Data Available flag.

BUF MSCAN 00-01, and are written into the regis-

The DV11 BUSY circuitry (E16) is activated if a

ter file by TRAN FILE LOAD L.

Receive Flag is asserted when Data Available (DA) is

Read address lines are routed into the register file

true. DVI11 BUSY then assumes the mark state (-V)

from the 9318 priority encoder, E87. Operation of

- until the microprocessor services the current Receiver

these lines is analogous to that discussed in the receiver. Data lines DB1-D8 are sent to the UART.

Flag. DV11 BUSY, which must be implemented with

-external hardware, essentially prevents the remote
transmitter from sending the next character until the

Transmitter Flags — The Transmit flag indicators E74

present UART received character has been process-

and E84 are initially cleared by RESET L (D4-2).

}4.8.5.9 M7833 (D4-7) - Shows the EIA IN and

ns TRAN FLAG CLK signal (see D4-3) is produced

Upon DVI11 microprocessor servicing of a flag, a 300

that sets the clock to the one state. Setting of the flipflop occurs on the trailing edge of the flag clock and

OUT, and MAINT LOGIC. The normal path for

EIA received data is through the 8093 buffer (E18).

prevents the flag indicator from being displayed to

Each of the EIA input drives also goes through an

the microprocessor.

8094 buffer which comprises a per-line maintenance
loop. The MAINT H signal determines which
of the
buffers (E17, E18) goes to a high impedance state.
Each serial input lead is held to the mark state when

flag indicator thus presenting a TRAN FLAG to the

receiver enable is cleared. When a receiver enable is

Microprocessor.

cleared (E24, E13, E8, or El14), a HIGH 1nput level

occurs on the 7432 (E3).

Transmitter Timing - Three single-shots in series plus

a 30 ns delay line comprise the timing circuitry for the

The BREAK feature is mechanized by ANDing the

transmitter. The trailing edge of RESET L releases

UART serial output line with 0 output of the Break

the clear input of the flip-flops (E88-1). E88 functions

flip-flop (D4-2) at E9. When the Break flip-flop is set,
therefore, a LOW logic level is applied to EIA Input

in the same manner as in the receiver service timing.

When one of the flip-flops is set, it indicates that a

Driver El11. EIA XMIT DATA 00-03 thus spaces

UART has an empty transmitter buffer and that the

(+V).

microprocessor has placed a character in the register
file for that line. The rising edge of the delayed

In half-duplex mode, the receiver must be inoperative
when

The transmitter timing logic

senses the flag and loads the character from the file
into the UART. THRL L, the character loading signal, is generated in E89 and its occurrence clears the

transmission

indicated.

RESET L triggers E63-5 at E63-10. The output pulses

End-of-character

at E63-5 clocks E88-9 to sample any line request for

4-47

transmission. If no lines are requesting (all four flip-

Pull-up resistors R35, R36, R37, and R38 are includ-

flops of the 74175 cleared), the remaining single-shots

ed in the speed 17 line to permit Data Set Busy to be

trigger on the trailing edge
of the previous single-shot

- operated independently of the selected baud rate.
Data Set Busy is true (active LOW) when a marking

output and the E87 Priority Encoder does not gener-

condition is present on the line.

ate an active Group Select output at E§7-14. Timeout

the

third

single-shot

(E70-12)

retriggers

the

sequencing network of the single-shots via E42-11 to

4.8.5.11

sample the selecting line again. As before, a request-

for the four lines. The UARTSs are the fundamental

ing line is indicated by the 9318 Priority Encoder and

part of the line card operation. Each UART converts

the Group Select output going LOW and by the bina-

serial data from an EIA receiver (NON-MAINTENANCE MODE) to parallel data for the Receive

ry weighted address code of the highest order input.

The address code and Group Select enables the
appropriate address leads and read enable inputs of
the register file. Character strobe occurs when E89
decodes Group Select and the output at E70-4 is true
generating the THRL 00-03 L condition. As just

described, THRL L also direct clears the flag to signal the microprocessor that the register file is now
empty. E70-12,-a nominal 125 ns single-shot, provid-

es the minimum hold time for the character and

M7833 (D4-9, D4-10)- Shows the UARTSs

“register file and parallel data from the line card’s
“Transmit register file to an EIA driver. Both the
receiver and transmitter are doubled buffered, and
each operates from a common internal format control register. The Format register, when written, will
produce a UART strobe signal that loads the common operating parameters for the line. These parameters and strobe are fed into the UART at the bottom
of each block.
|

Transmit Operation - When the UART is idle, the

retriggers the sequencing network.

transmitter is marking and is indicated by a high level
on the serial output lead. To transmit, a parallel char-

acter is placed on the data bus lines (DB1-DB8) and

Remote Stop -The asynchronous line card contains a
feature that permits an externally applied signal to

is loaded into the appropriate UART by the THRL
lead. The UART’s internal control logic then makes

stop subsequent characters from being presented
to

a parallel to serial conversion of the character and

the line after the stop code of the current character is

adds start and stop bits. The start bit is placed on the

transmitted. E88 is fed from four 4-input positive

line first and is followed by the least significant data

NORs (E65, E79) which check for the following

bit (DB1 pin 26). If parity has been selected, the parity bit follows the most significant data bit and precedes the stop bit(s). The transmitter clock is applied

el
ol e

conditions:
Transmitter Flag Cleared

to pin 40 and is 16 times the desired bit length.

End of Character (EOC)

Receive Operation — Reception begins when the serial

UART Transmitter Buffer Empty

input lead (pin 20) transitions from a mark-to-space.

‘No External Stop

The EOC line is a UART-generated character which

This transition indicates a start bit condition and is
sampled again at the center of the bit. If the serial

is LOW when a full character, including stop bits, is

input is high at this time, the receiver returns to the

transmitted. EOC remains LOW until the start of

idle state, otherwise the data entry state is entered. In

transmission of the next character.

the data entry state, the receiver stores the serial input

TBMT (Transmitter buffer empty) is another UART-

ity has been selected and the received parity bit differs

generated line that goes LOW when the UART hold-

from the selected parity sense, the parity error bit (pin

lead according to the Control register format. If par-

ing register may be loaded with another character.

13) goes high. The receiver also samples the first stop

bit for a marking condition or ‘“‘valid” stop bit. If the

The final condition for activating E65, E79 is gated

stop bit is low, then the framing error bit (pin 14) is

by an external Data Set Busy condition (E6). To acti-

set. The framing error bit, parity error bit, and

vate this line,

received character (pins 5-12) are transferred to the

the following

conditions must be

satisfied:

Receiver Holding register one cycle after the stop bit

has been sampled. This transfer sets the Data Avail1.

Speed 17 (38.4K baud) selected; and

able flag (pin 19). If the previous character in the
holding register has not been serviced by the Receiver

Selected Line not operating in internal

Flag Servicing logic on D4-6, then the Overrun Error

maintenance loop back mode.

flag is set when Data Available is updated.

4-48

4.8.6

4.8.6.5

DV11 Modem Control Unit Drawing

ed in drawings M7807 and M7808. (These drawings

00-03 for lines 08-15 are gated from the 74175 flip-

-are numbered D1 through D12.) Note that the circuit

flops (described in the above two paragraphs) by the

schematic pin designations are for a module in loca-

74151 selector /multiplexers, so that the program can
read the status of these flip-flops.

tion A-B-C-D, whereas the DV11 uses these modules
in location C-D-E-F.

4.8.6.1

4.8.6.6

M7807 (D1) - Shows the Address Decode

4.8.6.7

on Unibus lines A00-A17, with the direction selection bits CO and CI1, plus an MSYN signal to command selection. The Address Decoder responds with

transceivers (E41 and E44) are used to transfer bits in
either direction. The In High level from the Address

tion and LSR/CSR selection bits are routed to the

Decoder conditions the transceivers as transmitters,

Unibus interface gates and transceivers to enable

enabling them to gate data to the Unibus.

read or write of the selected register by the processor.

The LSR/CSR Bits 00-03 Selector (E36) interprets

M7807 (D2) - Shows the Interrupt Control

the register selection bit from the Address Decoder
(bit 01 of the MCU address) to gate bits 00-03 of the
selected register to the Unibus via the 8838 transceiver at E41. The Bits 4, 5, 6, 7 Register Selector
(E53) similarly interprets the register selection bit to

logic. A cross-coupled NOR gate flip-flop (7402) is
used to inhibit a second interrupt until the first one
has been serviced. If the Done flip-flop sets while the
Interrupt Enable bit (CSR 06) is set, a transition
occurs at E57 pin

M7808 (D7) - Shows the Unibus interface

gates for transferring CSR bits 00-11 and LSR bits
00-07 between the Unibus and the MCU. Two 8838

SSYN to acknowledge selection. The direction selec-

4.8.6.2

M?7807 (D6) — Shows the TTL-to-EIA logic

level converters for lines 08-15.

Logic. The processor places the DV11 MCU address

10 which causes an interrupt

(1) gate bits 05, 06, 07 of the selected register to the
Unibus via the 8838 transceiver at E44, and (2) gate
bit 04 (a read-only bit) directly to the Unibus.

request to be asserted to the Unibus (Bus B BR L).
When the MCU has priority, the PDP-11 returns Bus
B BG IN H, which clears GRANT, blocking propa-

gation of the grant to units of the same priority level

LSR bits 00-03 comprise the 74197 Line Counter,

further down the bus. Bus SACK L is also asserted to

stepped by the 8271 Ring Counter as described in
Section 4.2. Ring Counter Stages 00-04 are ORed
together to produce a static assertion at E54 pin 4
(LSR 04, the MCU Busy bit) whenever the Ring

acknowledge selection.

When the device asserting Bus Busy releases the bus,

the vector is gated to the Unibus and Bus Intr L is

Counter is cycling.

generated. The Processor responds to Bus Intr L by
AT

M7807 (DS)- Shows LSR bits 00-03 storage

for line 15 in 74175 quad flip-flop module. LSR bits

Logic for the DV11 Modem Control Unit is contain-

reading the vector address and asserting slave sync.

4.8.6.8

This clears the 7402 latch, which in turn clears BBSY,

Hold register, and Transition Detector. The Scan

M7808 (D8) - Shows the Scan Memory,

Memory is a 7489 4 X 16 RAM, whose data output

releasing the bus.

lines are gated to the 4015 Hold register by the lead-

4.8.6.3

ing edge of a clock pulse from the 8271 Ring Counter

M7807 (D3)- Shows LSR bits 00-03 storage

for lines 08-11 in 74175 flip-flops. The flip-flops for

(D7) at bit time 01 (Ld Hold H). The RAM address

the selected line are loaded by a clock pulse from the
7442 BCD-to-decimal decoder, which interprets the
output of the Line Counter in D7. A 74151 selector
multiplexer gates the RING signal line (CSR 15)
from the selected modem within the second group of

being accessed is determined by the contents of the

eight modems (lines 08-15).

able at the RAM output at the trailing edge of the Ld

74197 Line Counter (D7). The updated modem status

bits (DSR, CS, CO, RING) are written into the
accessed RAM location while the Ld Hold H line is

at a logical one level. The updated bits become availHold H pulse.

4.8.6.4 M7807 (D4)- Shows LSR bits 00-03 storage
for lines 12-14 in 74175 flip-flops. The 74151 selec-

The Transition Detector consists of three exclusive

tor/multiplexers are used to gate the DSR (shown as

OR gates which continually compare the RAM out-

SEC RX) CS and CO signals (CSR 12-14) from the

put data with the contents of the Hold register and a

selected modems within the second group of eight
modems (lines 08-15).
|

tions (only) of RING. If one of the updated RAM

7408 /7404 combination that detects positive transi-

4-49

bits should differ from the corresponding Hold regis-

4.8.6.10

ter bit, an assertion would occur at E59 pin 11 (Tran-

age for lines 04-06 in 74175 flip-flops. Three 74151

sition Det H). As shown in D7, this assertion would

selector /multiplexers are used to gate the Data Set

set the Done flip-flop at Ring Counter bit time 04.

M7808 (D10) - Shows LSR bits 00-03 stor-

Ready, Clear to Send, and Carrier On signal lines
from the selected modems within the first group of
eight modems (lines 00-07).

4.8.6.9

M7808 (D9) - Shows LSR bits 00-03 [Line

En, Term Rdy, Request to Send, New Sync (rede-

4.8.6.11

fined SEC TX)] storage for lines 00-03 in 74175 flip-

age for line 07 in 74175 quad flip-flop module. LSR

flops. The flip-flops for the selected line are loaded by

“bits 00-03 for lines 00-07 are gated from the modems

M7808 (D11) - Shows LSR bits 00-03 stor-

a clock pulse from the 7442 BCD-to-decimal decoder,

by the 74151 selector/multiplexers. LSR bit 00 is

~which interprets the output of the Line Counter in

gated from the Line Enable flip-flops.

D7. A 74151 selector/multiplexer gates the RING

signal line from the selected modem within the first

4.8.6.12

group of eight modems (lines 00-07).

ic level converters for lines 00-07.

4-50

M7808 (D12) - Shows the TTL-to-EIA log-

CHAPTER 4

PRINCIPLES OF OPERATION

System Logic Diagrams: operation of the

logic circuits appearing on each system

er should be familiar with the contents of Chapter 1

logic drawing is described, to correlate the

and Chapter 3 before reading this chapter. DVI11

drawings with the functional description

principles of operation are discussed in the following

in Chapters 3 and 4 (Section 4.8).

sequence:

4.1 SYSTEM BLOCK DIAGRAM

System Block Diagram: operation of the

Figure 4-1 is a detailed block diagram of the DV11

DV11 functional units are discussed with

‘Multiplexer. Control lines are shown as light solid

reference to a detailed system block dia-

lines, data transfer paths are shown as heavy solid

gram (Section 4.1).

Line Modem Selection and Control: oper-

ation
-

lines; with the nominal number of bit lines within
each path indicated by encircled numbers. Logical

of the

Modem

Control

functional unit diagrams appear on the system draw-

ing, indicated by the number in the lower right of

Unit

(MCU), to handle selection and control of

each block. Ancillary and other functional units,

line modems is discussed with reference to

which would not serve to clarify principles of DV11

the MCU block diagram (Section 4.2).

operation, have not been included in Figure 4-1.

DVI11 Microprogram: control of the charprocessor is shown with flow charts and

Inter-register transfers in the DV11 Data Handling
Section are switched through the DV11 Transfer Bus,

references to system logic diagrams. A
section of the binary microprogram is dis-

lines have been used in some cases to indicate essen-

played and its operation examined (Sec-

tial data paths between registers. The Modem Con-

acter

transfer

process

the Micro-

as indicated by the diagram; however, heavy dotted

tions 4.3, 4.4, 4.5).

trol Unit, Microprocessor, Synchronous Receivers

and Transmitters,

Unibus Interface: the logical exchanges of
data

and

PDP-11

control

signals

between

UARTs,

and Random Access

Memory (RAM) functional subsystems have each

the

Unibus and the DVI1I is

been enclosed
by dashed lines to assist in the transition from Figure 1-1, the DV11 Overview.

described in detail (Section 4.6).

DVI1 Instructions: detailed descriptions

4.1.1

of the instructions that make up the

Line modem selection and control is accomplished

Microprocessor instruction repertoire are

Modem Control Unit (MCU)

via the Control Status Register (CSR) and the Line

Status Register (LSR) as described in Section 3.2.

provided. Timing of the instruction execution process and the DV11/PDP-11

Three control lines are routed to each of the 16 line

Unibus Interlock

modems and four status lines from each modem are

control

are

also

described (Section 4.7).

monitored by the MCU, as indicated in Figure 4-1.

4-1

et A

DV 11 Multiplexer principles of operation. The read-

e et

This chapter contains a détai}ed description of the

..,u,__

- SYRCHRONOUSHRECEIVER S56r RRSNSNHTHRERS

SAT's

TRANSMITTER

SYNCHRONOUS
TRANSMITTERS

SELECTION

paze.pe>

FLAG

DETECTORS

[

[®

D4-2

\ |

"MODEMTCONTROL UNKF #2 ors
4x16

)

~7e) CONTROL

LINE STATUS
|

}
|

BCC RESULT | | ALU RESULT

—

RDR BITS

RAM

+—*

ADDRESS
ReeG

D3-8

SECONDARY
”

(Sheet 1 of 2)

DATA

RANDOM

ACCESS

D2-7

4-2

I o

<%>

I
I

D3-2

TEST POINT

INSTRUCTION

D3-2

D3-1

BRANCH -

<%8

sy g

ENABLE

HIZLO BYTE SELECT

RAM OUTPUT

D3-8

D3-1f

DATA REG

D29

- LONTROL

REQ |

<§>

DATI

-~ NPR DATA

TES DI

[

DATO

&0 parf

NPR DATA

SCR

1SYSTEM CONTROL

1§>

UNIBUS

o
i

§y

;

&, i | STATUS REG

D1-8

NPR's

MEMORY

ADDRESS REG |

SELECTOR
REG

NPR CONTROL

(—{I,h—-—_

DVI11 System Block Diagram

RDR

ROM DATA REG.|

|sTaRT

Synchronous

Figure 4-1

D3-1

! @

|
|

TIMING
D3-7

CONTROL

STEP

PDP-1{

D3- 1

—I

l
|

ALU
ARITHMETIC &
LOGIC UNIT
D1-1, D1-2

READ-ONLY

CONTROL

‘

REG

]

I»

ADDRESS '4::>". MEMORY
.
|
16x512

RECEIVER

<§>

ROM |

BCC
BLOCK CHECK
CHAR
D1-6,D1-7

INTERRUPT

;

CHAR.l

5ms Ja am At

STATUS REG

l
|

CHARACTER

CONTROL [

O-I-—.—l

03-4

STEP

[

D1-3,D1-4

(18)

REGISTERD1-2(

RECEIVED

SCANNER

M
D4-8

LINE
(\SELECT [ MASTER

SELECTOR

RECEIVERS

SOR (16)

| QGD Q@ |

D4-6,D4-7

FLAGS TO

—» TEST PT.

1
i

SAR's
'MODEMS

TRANSMIT

CHARACTER REG
D3-4

I
TO LINE

[+
2

42 1’I

|l
l

DV11 TRANSFER BUS

.
11-2678

DV11 TRANSFER

—|

(8)

UNIVERSAL ASYNCHRONOUS RECEIVERS &

| TRANSMITTERS'

TRANSMITTER
SELECTION

D4-8

I
|

l .

ASYNCHRONOUS|

D4-9,D4-10
-

_______ @

v
I.

| I

TEST

PT.

RECEWVER
fe+
SELECTION
loa-5.04-6

| .,

LINE

STEP

[

|» |

<9>3

BCC

ALU

BLOCK
CHECK
CHAR

ARITHMETIC
LOGIC UNIT&

D1-6,D1-7

D1-1, DI-2

TM
|

REG

——

D3- 1

16)

SILO

D1-5
L

D1-7

D3-1

CONTROL
057

ROM DATA 032
REG.

D1-1,D1-2

‘

| I

;

}

(16)

" TEST POINT

INSTRUCTION

o_
|

)

q| bk N
|-

CONTROL

*——.—l

| I ||| |

CONTROL

STATUS REG

LINE STATUS

. |
»

+—

2
ADDRESS

DECODE

|
CONTROL

D3-8

SRS

SECONDARY

16)|

ROR | BITS

REG

""’pa-s

ENABLE

—l
(16)

|
DATA

RANDON

D3-9,D3-10

RAM
OUTPUT
DATA
REG

ME MORY
18

x256

p3-11]

NPR CONTROL

D2-7-

|
~

ADDRESS REG |

STATUS REG

D2-9

D1-8

4
|
HI/LO BYTE SELECT
‘

NPR's

'CONTROL

INTERRUPT

D2-8

SIGNALS

[

Omn
DATI
8

DATO

NPR DATA

_
@D

SYSTEMREGCONTROL
REQ
54
INT.

SCR

16)

PDP-11 UNIBUS

11-4413

b.
Figure 4-1

Asynchronous

DVI11 System Block Diagram
(Sheet 2 of 2)

4.3
et

4x16 )

IRAM

D3-1 |

D3-2

SELECTOR

BRANCH

|
.
[sTart

_STATUS

-I I

‘

l MODEM CONTROL UNIT

:
|

|
ALY RESULT

D2-9
|

- ! (18)

INTERRUPT

|
BCC
RESULT

STEP

‘

M6EM50F;Y

TIMING

CHARI
RECEIVER

INTI

| ||

(

TM ADDRESS
RoMm _@_.
|
ROM
READ-ONLY

ECEI
CHARACTER

'V |
|
|

D1-2

@ I

D3-4

_I |
|

2\SELECT
| SCANNER
MASTER
—

-4

||
|

SELECTOR

|
l

TO LINE

FLAG
| giT%CTORS

FLAGS TO

I
MODEMS <

» |

D4-9,D4-10

(O—

D1-3,D1-

CHARACTER REG
D3-4

UART'S
ASYNCHRONOUS

TRANSMIT

TRANSMITTERS|

—

MICRO

PROCESSOR 5y

BUS

4.1.2

Microprocessor

Operation of the DV11 is controlled by the contents

memory). The RC Silo is 16 bits wide to accommodate control bits and line number bits as well as

(microprogram) of two 256 X 16 read-only-memories

the 8-bit character. Handling of receiver interrupt

(ROMs) in the Microprocessor. The contents of the

characters

ROM are addressed by the ROM Address Register

(RIC) register is described in Section 1.1.

via

the

Receiver

Interrupt

Character

(RAR) and read out to the ROM Data Register

each ROM. Timing Control is started when the PDP-

4.1.3 Random Access Memory (RAM)
RAM locations may be addressed by either the PDP11 program via the Secondary Register Selection
(SRS) register, or by the microprogram via the RAM
Address register. The SRS provides the full 8-bit
address needed to specify a RAM location. The
RAM Address register provides only the four loworder bits, obtained from the current data line num-

11 program sets System Control Register bit SCR 00-

ber in the Master Scanner. The four high-order bits

(RDR) for decoding. The instruction operation code

in bits 12-14 is decoded to produce control signals to
enable instruction execution.

The RAR is stepped by Timing Control to address
ascending

locations in

the ROMs, alternating

between ROMs to access contiguous locations within

01. Timing Control generates timing pulses (01, 02,

are placed directly on the RAM address lines from

03 and Data Strobe L) to sequence execution of each

the RDR whenever a RAM location must ‘be

instruction within the 300-ns ROM read cycle. If the

op code specifies a conditional branch and the speci-

accessed for a data read or write operation. An interlock inhibits simultaneous access to the RAM by the

fied test point is true, the RAR

“microprogram and the PDP-11.

is set to the branch

address at 02 time.

' 4.1.4

NPR Operations

In addition to branch operations, Microprocessor

NPR Control responds to a microprogram NPR

instructions are provided to perform computations,
read and write data between RAM locations and sys-

instruction by initiating an exchange of control signals with the Unibus and core memory to enable

tems registers, initiate NPRs, set or clear selected

microprogram access to core memory to fetch or

control bits and effect inter-register data transfers.

The gating logic is structured to transpose bit fields as

store a byte at the address specified in the NPR
Address register. Interrupt Control effects a similar

required during inter-register transfers.

exchange and gates the vector address to the Unibus.

4.1.2.1

4.1.5

Computations - ‘The Block Check Com-

Programmable Registers

putation (BCC) unit and the Arithmetic Logic Unit

Functions of all programmable registers exhibited in

(ALU) are logical networks for computing block

Figure 4-1

check characters, effective addresses, logical com-

Maintenance functions of programmable registers

binations, etc. The microprogram loads the values to

are described in Chapter 5.

have

been

described

Section

3.2.

‘be logically-combined
into the A and B registers and

the several resultants become statically available on

4.2

~the BCC and ALU output lines. Selection Codes are

CONTROL

applied
to one of the networks by the microprogram

Figure 4-2 is a detailed functional block diagram of
the Modem Control Unit (MCU), using the same

to specify one of the resultants, which is then strobed
into the corresponding Result register.

4.1.2.2 Line Selection and Character Transfer ~“Each time the Microprocessor completes the process-

ing steps for a data line, it steps the Master Scanner

to the next sequential line, causing it to select the
receiver or transmitter for that line to sample the corresponding Ready flag and any synchronizationcharacter-detected and error conditions. Processing

LINE

MODEM

SELECTION

AND
|

conventions as in Figure 4-1 to show data and control
~lines and system drawing references. In addition,

selection lines are shown as entering vertically into
functional blocks, while data transfer lines are
indicated as horizontal flows. Dashed lines are used to
~enclose the Unibus Interface gates and the functional
units that hold the bits of the LSR and the CSR. Register bit names and numbers have been included in
the figure. Note that not all bits of the CSR are stored

for a data line consists essentially of one step for

in flip-flops, i.e., the CLR MUX and CLR SCAN

character transmission (transferring the next charac-

“signals from the Unibus are not actually stored in the
MCU. Similarly, in the LSR, status bits 4-7 are not

ter from core memory to a transmitter), or two steps

Received Character (RC) Silo from a receiver, or

stored in the MCU, but are routed to the Unibus
from the enabled and selected modem. Register bit

transferring a character out of the RC Silo to core

functions are described in Section 3.2.

for character reception (loading a character into the

) /—\\\
/

" CHAPTER 5

MAINTENANCE

This chapter contains descriptions of DV11 program-

5.1.1

mable register maintenance functions and PDP-11

The DV11

Microprocessor Diagnostic Functions

diagnostic programs for exercising, testing, and
maintaining
full operation of the DV11 Multiplexer.

the PDP-11 program to:

The programmable register maintenance functions

includes diagnostic functions which enable

set bits to interrupt itself: SCR 15, the

- NPR Status Interrupt bit and SCR 09, Bit

are discussed
in sufficient detail to enable the user to
exercise DV11 logic circuits via simple or complex

15 Write Enable, in conjunction with SCR

PDP-11 programs of his own design. Operation
of

13, NPR Interrupt Enable (Vector B); or

each PDP-11 diagnostic program provided by Digital

SCR

is then described. To effectively use the information

junction with SCR 06, Receiver Interrupt
-

on the programmable register maintenance functions,

07, Receiver

Interrupt,

Enable (Vector A).

con|

the user should have read Chapters 1, 3, and 4.
2.

provide

for

sequential examination

ROM contents using SCR 02, the ROM
5.1

Branch

PROGRAMMABLE REGISTER

Disable

bit,

disable

branching.

MAINTENANCE FUNCTIONS

Programmable register bits intended only for maintenance operations are shown as shaded bits in Figure
3-3. Tables 5-6, 5-7, 5-8, and 5-9, describe, in detail,

ROM

cause an unconditional ROM branch to

examine ROM locations at random (by

setting X000 0001 XXXX XXXX into the

the maintenance bits of the System Control Register

(SCR), Line Control Register (LCR), and Control

ROM Data register, where the Xs are the

Status Register (CSR). In addition to the mainte-

branch address bits (Branch A instruction

nance-only bits, SCR 00 (Microprocessor GO), LCR
15 (Control Strobe) and CSR 08 (Step) have been
included in the maintenance bit reference tables as

~with Sure True test bit set).
4.

read or write the ROM Data Register

being principally intended for maintenance use. The

(Special Functions register) in con-

maintenance-only

junction with SCR 03, the ROM Data

Special

Functions

Source Select bit, and step the Micro-

described in this section.

processor one instruction at a time (SCR

Maintenance functions proVided by the DV11 pro-

01, the ROM single step bit).

grammable registers fall into three categories:

1.
2.

Microprocessor Diagnostic Functions
Data Transfer Diagnostic Modes
|

Modem

- Functions

Control

indirectly examine test point conditions
by means of the Branch True bits (LCR 00
and 01). This permits a test of the ability
of the Microprocessor Set/Clear instruc-

Unit Diagnostic

tion to change the states of test points.

5-1

S.1.1.1

Special Functions Register (SFR) - The Spe-

The 01 mode closes a TTL data path from the output

cial Functions register is used for maintenance only,

of the transmitter to the input of the receiver. The

to enable read or write
of the ROM Data register in

Maintenance Clock pulse bit (LCR 08), driven by the

the DV11 Microprocessor by the PDP-11 program.

PDP-11

program, clocks the data bits out of the
transmitter and into the receiver. The Maintenance

When SCR 03 is set to zero, the SFR contains the
current contents of the most recently addressed ROM

location, enabling inspection by the PDP-11

Bit Window (LCR 07) may be used by the PDP-11

pro-

program to monitor the data bits entering the receiv-

gram. When SCR 03 is set to one, data written into

er. If the Transmitter Disable bit (LCR 09) has been
set, the data entering the receiver is determined by the

the SFR by the PDP-11 program is written into the
ROM Data register, where the Multiprocessor may

state
of the Maintenance Data bit (LCR 14) at LCR

act upon it as if it were actual ROM data.

15 set time. Use of the Maintenance Data bit permits
the diagnostic to check ability of the synchronous
receiver to recognize the sync character, present Data

The SFR is used in conjunction with Microprocessor

GO (SCR 00), ROM Single Step (SCR 01), and
ROM Branch Disable (SCR 02), to enable PDP-11
maintenance

programs

create

Avallable flags, etc.

Microprocessor

instructions and to confirm the ability of the Micro-

In mode 11 (Figure 5-2), a TTL data path is closed

processor to execute them.

5.1.2

from transmitter output to receiver input, just as in

Data Transfer Diagnostic Functions

mode 01. However, clocking must be derived from

Three data transfer diagnostic modes for synchronous line card testing are provided. These modes are

one of the internal DV 11 switch-selectable clock rates

selected by bits 11 and 12 of the Line Control register

monitored at the receiver input. This mode is espe-

shown in Table 5-1. Data may not be injected or

in conjunction with the LCR 15 strobe bit. The diagnostic

modes

enable closed-loop

cially useful for system software performance testing.

data paths and

enable the injection and monitoring of data within

the data transfer paths.

[ MODE 11 DATA PATH

Mode 00 is the normal (non-maintenance) operating
mode. In mode 01 (Figure 5-1), the PDP-11 program

can clock selected data bits or bytes into a closedPDP-11

OUTPUT

INPUT

loop path from PDP-11 to transmitter to receiver to

1200,2400
)
)
1)

DN AL OVIERNAL | 4800,9600 | syncHRONOUS | | SYNCHRONOUS

for the enabled receiver (LCR 13 set to one).

SELECTION

The following EIA level converters are disabled, so

BAUD CLOCK

RECEIVERS

TRANSMITTERS

SWITCHES

that the majority of the logic can be dlagnosed with-

11-2886

out disconnecting the modem cable
Receiver Clock

Figure 5-2

Transmitter Clock

Receiver Data

Block Diagram (Synchronous)

Transmitter Data
LCR 27

LCR 28

MAINT. BIT

MAINT.

WINDOW

CLOCK

[cLock
DATA

Maintenance Mode 11

(Internal Mode for Systems Testing)

[ MODE 21 DATA PATH

For mode AIO.(Figure 5-3) to function, all lines con,

INPUT

nected to the modem must be disconnected at the

OUTPUT

SYNCHRONOUS [

| SYNCHRONOUS

RECEIVERS

TRANSMITTERS

modem interface and replaced with the H325 con-

nector. The H325 connector turns around specified
signals after level conversion and returns them to the

11-2885

- DVI11 as simulated inputs. This is called the external

maintenance mode, since the EIA level converters are
Figure 5-1

Maintenance Mode 01

(Internal Mode) Block Diagram

also tested. Clocking is derived from the internal
DV11 clocks, as in mode 11.

Table 5-1
Synchronous Parameter Selection Switches
Function

Parameter

Name

Switch

Number

Setting

Pack
Internal Baud

1200 Baud

Select B

Select A

2400 Baud

Select B

Select A

OFF -

Select B

OFF

Select A

Select B

OFF

Select A

OFF

Rate
|

4800 Baud

9600 Baud

Full/Half

Full Duplex*

Duplex

Half Duplex

Parity

No Parity*
Odd Parity
|

Even Parity

Character Length

8 Bits/Char

(Excluding Parity)

7 Bits/Char

6 Bits/Char
5 Bits/Char
SYNC

1 SYNC REQ.

HD3

HD2

HD1

HDO

HD3

‘5

OFF

HD2

OFF

HD1

- OFF

HDO

OFF

EPE

OFF

EPE

OFF

WLS1

OFF

WLS2

OFF

WLS1

WLS2

OFF

WLS1

OFF

WLS?2

WLS1

WLS2

ON
OFF

1 SYNC 00

Requirement

1 SYNC 01

OFF

1 SYNC 02

OFF

1 SYNC 03

OFF

2 SYNC REQ.

Sync Character

Desired Code

1 SYNC 00

1 SYNC 01

1 SYNC 02

1 SYNC 03

Sync A

Codes
Desired Code

Sync B

*Required for diagnostics DZDVA to DZDVE.

5-3

ON
-

ON
(As required
—

OFF

one)

(As required
—

= Logical

OFF = Logical

one)

MODE 12 DATA PATH
{H315 CONNECTOR)

- (MODEM (S)

DISCONNECTED)

EIA LEVEL CONVERTERS

[

4800,9600 SYNCHRONOUS
ERS
RECEIV
=

BAUD CLOCK

SYNCHRONOUS
TRANSMITTERS

11-2887

Figure 5-3

verters are tested.

Maintenance Mode 10 (External Mode)
Block Diagram (Synchronous)

$ TO EIA LEVEL CONVERSION

TTL SERIAL OUT

UART

7432

8094

TTL

SERIAL

UART
RECEIVER

TRANSMITTER

MARK =1= HIGH
SPACE=0= L OW

MARK=1=HIGH
SPACE=0:=LOW

MAINT H

PORTION OF MAINTENANCE LOGIC
11-4402

Figure 5-4

Typical Internal Maintenance Mode Path (Asynchronous)

PATH

DATA

(H325 CONNECTOR)
|

—

i i TTL SERIAL OUT

EIA LEVEL CONVERSION
TTL SERIAL IN

MARK =1=HIGH

SPACE=0=LOW
UART

MAINT L

7432

UART

RECEIVER

TRANSMITTER
8093

172 DUPLEX

PORTION OF HALF DUPLEX AND MAINTENANCE LOGIC

BAUD RATE

SELECT
ES
SWITCHION

{}OUTPUT

UlNPUT

INTERNAL| 1200,2400.

14-4403

Figure 5-5

Typical External Maintenance Mode Path (Asynchronous)

5-4

DV11

Two data transfer diagnostic modes for asynchronous line card testing are provided. These modes are
selected by bits 9, 10, and 11 of the Line Control register in conjunction with the LCR 15 STROBE bit. In
Internal Maintenance mode (Figure 5-4), a TTL data
path is closed from the transmitters output to the
~ receiver input. This mode is especially useful for system software performance testing. For the external
maintenance mode to function, all lines connected to
the modem must be disconnected at the modem interface and replaced with the H325 connector (Figure 5- 5). In external maintenance mode, the EIA level con-

5.1.3

Modem Control Unit (MCU)

Diagnostic Functions

The MCU diagnostic functions provide for smgle-

NOTE

The configuration section of DZD VE must be run if the
DV11 has any asynchronous line cards.

stepping the MCU scan controls and testing the

integrity of the modem status lines. Whenever CSR
08 is set to one, the modem or line number is
incremented by one. If a status transition is detected

Hardware equipment required for the Data Handling

Section diagnostics is as follows:

for the new modem, Done (CSR 07) is set to one.
Done does not inhibit further stepping.

PDP-11 with 8K core

‘Whenever CSR 09 is set to one, all status lines from

- DVII-AA System Unit

all enabled modems become logical ones. This feature
enables testing of the

MCU scan control logic and the

status lines to the PDP-11.
5.2

DVI1-BA, DVII-BB or DVII-BC
Unit

DIAGNOSTIC PROGRAMS

2-4

Separate groups of diagnostic programs, test equipment, and procedures are provided for testing the
DV11 Modem Control Unit and the DV11 Data

H8612

’

Test

Connectors

per line

card)

MAINDEC-11-DZDVA

Handling Section, respectively. Each of the two diag-

Diagnostic

- Program

nostic groups will be discussed separately.
1

3.2.1

MAINDEC-11-DZDVB

DV11 Data Handling Section Diagnostics

Five Data Handling Section diagnostic programs are
provided: DZDVA, DZDVB, DZDVC, DZDVD,

MAINDEC-11-DZDVC

and DZDVF. Because of the complexity of the Data

Program

Handling Section, tables are provided herein to correlate the functional units tested with the individual

MAINDEC-11-DZDVD

tests within each diagnostic program.

Diagnostic

Program

Diagnostic

Program

A sixth diagnostic, DZDVE, tests the Modem Con-

trol section and provides a method of inputting infor-

MAINDEC-11-DZDVF Diagnostic
Program

mation concerning the settings of the Synchronous
Parameter Selection switches (reference Table 2-5)
for the particular DV11 being tested. For DV11s not

yet configured to a customer’s particular requirements, the diagnostics will automatically assume the

following parameters without the need of running the
configuration section of DZDVE (starting address
210):

- Module Extender, W904 (Hex-Height)

Modem Tes‘t‘~\C564fin'ector,~H325A

Multimeter (Triplett

1
I.

Full Duplex*

Parity Off*

Simpson),

Model 630-NA or 260

Oscilloscope (Tektronix), Type 454 or
) equivalent

X10

Probes

(Tektronix),

P6061

equivalent

Character Length of Eight Bits

Two Syncs Required

programmable registers, the Microprocessor instruc-

Synchronous Character Codes: Sync A =

tions, and NPR operations. The Special Functions
register is used to create the Microprocessor instruc-

5.2.1.1

226, Sync B = 062.%

DZDVA Diagnostic - Tests operation of the

tions; the ROM is not exercised.

*Required for diagnostics DZDVA to DZDVE

5-5

Table 5-2 shows the functional units tested by each
test or test group of the DZDVA diagnostic, and
includes system logic drawing references. Functional
unit names correspond to those used in the drawing
descriptions in Section 4.8. Tests performed are as
follows (tests are numbered octally):
Tests 1 and 2:

The register selection section of

the Unibus Interface is tested (Address Decoder, Register Decoder, Read Register Selector).
This section is exercised by all DZDVA tests.

Tests 3 - 53:

Read/write functions of the pro-

grammable registers are tested.

Tests 53 -57:
ondary

5.2.1.3 DZDVC Diagnostic - Performs free-running
tests of ROM and RAM operations. ROM contents
are verified against a core image. Table 5-4 shows the
functional units tested by each test or test group of
the DZDVC diagnostic, and includes system logic
drawing references. EH86¥F2-test: conneetorsissrequired
enneaehENETR33 and M7839.

Read/write functions of the sec-

registers

the

RAM

are tested;

spurious interactions between secondary regis-

ters are also tested for.
Tests 60 and 61:

Initialization functions are

5.2.1.4 DZDVD Diagnostic - Performs NPR character and control byte fetch and interpret operations
to test the Microprocessor, the RAM, and the NPR
data input interface (NPR Controls, NPR Address
register, DATI register). This diagnostic also tests the
protocol processing functions of RAM secondary
registers. A table of logical units tested by the various
tests in the DZDVD diagnostic is not provided
because the DZDVD diagnostic tests the microprogram, not the wired logic. H8612 Test Connector
is required on each M7833 and M7839. Test 1:

The transmit control byte and trans--

mitter “‘next mode’ are tested.

tested.
Tests 62 — 110:

The Microprocessor instruc-

tions are tested by means of the Special Func-

tions register. The Master Scanner, BCC, and

ALU units are tested in conjunction with the

Tests 2 and 3:

Transmitter Mark/Sync

functions.

Tests 4 - 6. Tests store/discard, BCC |

inclusion/exclusion, and next mode functions

Microprocessor instructions.

of receive control byte.

Interrupt Control functions

Tests 11 — 120:

Test 7:

are tested.

Tests DLE transmission function of

receive control byte.

Tests

121 and 122:

The NPR Status register is
Test 10:

tested.

Tests control byte fetch inhibit for

- both transmit and receive.
Tests 123 - 127:

The NPR Microprocessor

instructions is tested, causing tests to be made

Test 11:

of the NPR interface section (NPR Controls,

ing function.

NPR

Address

DATO,

and

DATI

registers).

Test 12:

DZDVB Diagnostic - Tests data transfer,

flag setting, and synchronization functions of the

Synchronous Receivers and Transmitters Unit. Table
5-3 shows the functional units tested by each test or

Tests Microprocessor restart after

special character interrupt.
Test 13:

- 5.2.1.2

Tests leading sync-character-stripp-

Tests operation of marked byte count

function for transmit and receive.
Test

14:

Tests

transmit

and

receive mode

functions.

test group of the DZDVB diagnostic, and includes

Test 15:

system logic drawing references.

receive control bytes.

Tests all functions of transmit and

x| %

11-4064

&®

x| x

x
x
x

®
®
x

®
x| %

x| x

x|X®

Static Tests of DV11 Functional Units (DZDVA)

X | X[ X%

x| x| x|x

x| %

x| x

X | x

x| x

X | x| x

x| x

x| X

x| %

x| x

x|[x]|x]|x|x

X | x| %

X | x| x

X [x|x|x|x|x]|x]|x

x| x
&

)

29
*

XAUX| XX

X
X | %

G X

¥ |
x| x| x| x

x| x| x

X[ XIXIxX|X|[xX|X{x]|x|x]|x]|x]|x

x
¥ |%

X | x| X

XIX ||

X< |%|[x|x]|x]|x

XXX [X[X|x[x]|x|[x]|x|x]|x]|x]|x]|x]|x

x| x [ xx|x|x|x|x|x|x|x|x]|x|x|x]|x]|x]|x

x| X

x| x

x|
x

x| x

X[ x| x|x|x

XXX

x| x|x|x|[x|x|x|x|x

% |x

XXX |x|x|x|x]|x

@ X[ x> [x|x[x[x|x|x|x|x|x|x|x]|x|x|x]|x|x]|x

X |%

XX |x|[x|x|x|x|x

X x| x|x|x|x

x |x

XX [x|x|x|x|x]|x

3 |

x| x| x| x

x| x| x|x|x]|x]|x

G-

I5]5

AMEIRE:

I IR A A B Bt

§IRIIR|T|V|9|B3)58|8/8/23|8|BIRIS|N|R|X|.|e|r|E|E
S| 8

New Function Tested

Comprehensive Test

)

x| x| x

|REFERENCE

Table 5-2

Table 5-3

Synchronous Receivers and Transmitters
Unit Diagnostic (DZDVB)

DRAWING

)ozes%?

REFERENCE
TEST NUMBER

X | X

3.7

1 x|

X
X| X

X |X | X
X | x|

11,12

X | x|

X |X

1,2

X |X | X | X

16, 17

X | X | x|

| X

X |X

20
21
22

X
X
X

X | x|

X | X | X|X
X | x|

X | X

X | x|

X | X | x|

X | X

x|x

11-4056

Table 5-4

Free-Running Microprocessor Diagnostic (DZDVC)

DRAWING\

' O ogg NN

9,\ ;2% NN

REFERENCE

TEST NUMBER

2.3

X |X

X |x

X |x |X

X |X

6,11

X |X

|x|x

X |x

X |X
X |X

X |X | X

X |X

13,14

X |X |X

X |X

X |X |X

X |X

15-22

11-4057

(X)Comprehensive Test

5-8

5.2.1.5

DZDVF Diagnostic - Attempts to test all
programmable logic associated with the asynchro-

H861 Test Connector (16 lines)

nous line card. Any synchronous line cards installed
in the DV11 will be skipped and untested. Table 5-5

H325 Modem Test Connector (1 shipped

per 8-line group) (DZDVE supports the

shows the functional units tested by each test of the

use of any number of H325s that may be

DZDVF diagnostic, and includes system logic draw-

available)

ing references. H8612 Test Connector is required on

each M7833. In addition to all tests, there is a special-

test (Test 41) to be used to create a specific condition
according to the user’s preference. In order to use
Test 41, load address 200 and start with SW1=1 (Test

BCO8R Cables

MAINDEC-11-DZDVE

No.) type 41 and enter the asynchronous line card
parameters for each of the two lines tied together at

The hardware is assembled per Figures 5-6 and 5-7

the H317C Distribution Panel by a BCO3P cable. All

DZDVE 1s operated per MAINDEC procedures.
Five or more passes in each configuration is consid-

DVI11 primary registers and secondary registers for

the two selected lines will be printed out and the execution phase will be repeated.
5.2.2

ered a valid test.
- 5.2.3

DVI11 Modem Control Unit Diagnostics

The

Both On-Line (ITEP) and Off-Line (DZDVE) diag-

nostics are provided for the DV11 MCU. The On-

NOTE

other PDP-11 test stations and is not restricted to any
- two given lines of the DV11.

dling features.

Procedures for each On-Line Test are as follows:

Three test configurations are provided: two Off-Line,

ON LINE - Procedure

and one On-Line:

OFF-LINE

TM .
.

:’/

modem contrQl with H861 test con-

Assemble hardware per Figure 5-9.

nector termination

2. Connect a modem to any line.

modem control and data-handling

with

an H325 Modem Test Con-

ON-LINE
modem

loop-back-around
5.

100 percent testing. Hardware requirements are as

5.3

follows:

DVI11-AA System Unit

DVI11-BB,

procedures.

Use

the

Five or more passes are considered a valid
test.

ment configurations (Figures 5-6 and 5-7) to achieve

PDP-11 with 8K core

MAINDEC

external loopback mode.

Line Tests — The Off-Line Tests require two equip-

Operate MAINDEC-11-DZDVO (ITEP)
‘per

configurations.

DVI11-BA,

Establish a connection with the remote
system or test station.

nector (Figures 5-7 and 5-8)

Two

con-

The On-Line ITEP diagnostic may also be used to call

addition, the Off-Line DZDVE diagnostic uses an
H325 Test Connector to test the MCU and data han-

equipment

the remote.

an HB861 test connector to test the entire MCU. In

the

must be connected to the DV11, the other modem, at

link to another PDP-11. The Off-Line diagnostic uses

require

equivalent, and must be of similar type. One modem

features may also be checked by connecting a direct

Tests

configuration may be Bell 103, 201, 202, 208, 209, or

of a modem or direct link to another PDP-11. The

Modem Control Unit On-Line Tests

On-Line

figuration shown in Figure 5-9. Modems used in the

Line diagnostic tests the MCU features with the aid

Diagnostic

Program

TOGGLE-IN PROGRAM

This test exercises a synchronous line in system test

mode (11) using Sync A = 2268 bits per character,

and no parity. Two sync characters are required for
synchronization.

DVI11-BC

The transmitter transmits three
characters: 226, 226, 227. The receiver goes active
after receipt of the two syncs and stores the 227 in

8-line

group

core.

5-9

When toggling in this program, the operator should
deposit the address of the DV11 System Control register in location 1000 and deposit the line number
under test in address 1002. After loading the test, set
1004 in

the console switches,

depress LOAD

ADDRESS, and depress START.

1000

—

1002

1004

1000

1010

12737

1012

340

1014

177776

1016

13700

1020

1000

1024

MRESET:
RAMCLR:

REGCLR:

REGSEL:

Line No.

12706

1006

1022

DVSCR

10001

MOV #1000,SP

MOV#340,PS

- Make RO = DVSCR
Make R1 = DVSRS

62701

1026

1030

10102

1032

5202

1034

10203

1036

5203

1040

12710

1042

4000

1044

12704

1046

1050

12705

1052

1054

10411

1056

110512

Make R2 = DVSRSH

Make R3 = DVSRA
Issue Master Reset

Set up to clear 17 lines
Set up to clear 17 registers per line

Select Line Number
Select register

1060

5013

Zero this register

1062

5305

Decrement register counter

1064

100374

1066

5304

1070

100367

1072

5037

1074

2226

1076

13711

1100

1002

1102

5037

1104

1236

1106

12713

1110

1232

1112

112712

1114

1116

12713

1120

177775

1122

112712

1124

1126

12713

1130

1236

BR to REGSEL #0
Decrement Line No. Counter

"BRto REGCLR #0
Clear RX & TX Control Byte Table Address

Load Line No. in DVSRS
Clear Rcv Buffer
Load TX Primary CA

Select TX Primary BC

Load -3 Byte ’Count
Select RX Current Address

Load RX Current Address

5-10

1132

112712

1134

1136

12713

1140

177777

1142

112712

1144

1146

12713
L

Select RX Byte Count

Load -1 RX Byte Count

Select Line State Register

Load Transmit GO

1150

TEST:

CWAIT:

TXPCA:
RCVBUF:

1152

112712

1154

1156

12713

1160

2000

1162

112712

1164

1166

12713

1170

2000

1172

12760

1174

134000

1176

1200

5760

1202

1204

100775

1206

5210

1210

105710

1212

100376

1214

22737

1216

227

1220

1236

1222

1401

1224

1226

137

1230

1040

1232

113226

1234

227

1236

Select TX Control Table Base Address
Load TX Control Table Base Address

Select RX Cent‘rol Table Base Address
Load RX Control Table Base Address

Load LCR with Systems Mode, Receiver Enable, Strobe

Test for LCR15=0; When true fall through

Set Microprocessor Go

Test for Receiver Interrupt in DVSCR

Compare expected 227 vs stored character

Branch to jmp if compare was equal
Halt if comparison not equal
Jump to MRESET

Sync, sync
Data Character
Received Character

S-11

XXX X% |[x]|X

Table 5-5
|
Static Tests of DV11 Functional Units (DZDVF)

X|
X

X
x|
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x|
x|
X
X [ X
x|
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x|
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X

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X | %%

[ X|x]|x]|x|x

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(38|85

X
x|

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3¢ 5 5] 5|3

X |X

x|
%

REFERENCE

DRAWING

i
)

XXX X x| XX

[%x]|

)

|x|x

8|S

[17]

5-12

NEW SYNC

DATA SET READY

J H861
FOR ONE
LINE

TERM RDY
cS

co
RS

RING

“

N
|
B
U
S
]

LINES O-3

ovin

MODEM

LINES 4-7

CONTROL |_LINES 8-11
UNIT | | |NES 12-15

H861

(16 LINES)

11-2936

Figure 5-6 Test Configuration
(DV11 Modem Control Unit with H861) Block Diagram

SCT

SCR
SEC XMIT

SEC

RCV

NETIE

SCE

Y
g VY

H325

XMIT DATA

RCV DATA

RS
CS

co
NEW

SYNC

DATA SET RDY

DTR
RI

CUT TO TESTX
NEW

SYNC

LINES 0-3

DV14

LINES 4-7

CONTROL | LINES 8-11
UNIT

LINES 12-15

DISTRIBUTION
PANELS

——L{] [0] MODEM TEST CONNECTOR (H325)

¥NORMALLY CUT FOR USE WITH DVii
(SYNCHRONOUS MODE ONLY)

(

)

11-2937

Figure 5-7 Test Configuration

(DV11 Modem Control Unit, Distribution Panel and Test Connector) Block Diagram -

5-13

DISTRIBUTION PANEL

EIA CONNECTOR

(fir\

H325

;—r——-RGND

TEST CONNECTOR

3——-— EIA XMIT DATA 22
;———— EIA RCV

DATA SET
RDY 29

;——— RTS

DATA 292

J1-2

—1—— CTS 00
6

Wa3Ss

sy — |

J1-4

_‘

J1-5

———
S GND
8
—1 —

CARRIER 22

J1-8

G—_—

—1—— (202 SEC TX 2@)

Wa1A

WJ2A

—e

(202

NEW

SYNC

J1-11 ——l

J1-12

o
—f—

SEC RCV».@Q)

W@6SsS

J1-—-15

15
o—1—— DCE SCT Q9O
16
—— WO7S
17

Ji1—17

*~—

—O—O0——— DCE SCR 29

J1-24

J1-20

SE—

J1-—22

.——.——

NEW®

2l TR 22

SYNC

IIA“

22
——— RI
23

J1—6
-

Q9O

J1-14

W@4Ss

25
—

—O——O0— DTE SCTE 9209

)

—O—O—— RTS 29
WA5F -

% NORMALLY

REMOVED

SNOTES:

11-4404

Figure 5-8 Distribution Panel and Test Connector Jumper Configuration

5-14

1
:
LINE O-3

§]
N
|
B

DV11
- MODEM
CONTROL

UNIT

LINE 4 -7

LINE

8-11

DISTRIBUTION
PANELS

LINE 12-15

REMOTE
PDP-11 SYSTEM

MODEM

OR TEST
STATION

|
|

===

—

Fommm

m e

77777

| S
|
L o s oS Sy J

11-2934

Figure 5-9 Test Configuration (ON LINE Modem Loop-Back) Block Diagram

Table 5-6
System Control Register Maintenance Bits

Bit(s)
00

Designation

Microprocessor Go

Function

When set to one, enables the Microprocessor to

Read/Write
Read or Write

‘operate the DV11 Data Handling Section. Must
be set to one to enable DV11 to perform any

functions other than modem control. Cleared by
Initialize.

ROM Single Step

When set to one, causes the DV11 microprogram to

Read or Write

execute one Read Only Memory cycle and stop.
When the ROM cycle begins, this bit is automatically

cleared. Cleared by Initialize.
02

ROM Branch Disable

When set to one, inhibits execution of branch instruc-

Read or Write

tions by the Microprocessor. Cleared by Initialize.

ROM Data Source

When set to one, enables loading of the Special

Select

Functions Register (SFR) by the PDP-11 program.

Read or Write

The contents of the SFR are then automatically

strobed into the ROM Data Register, a Microprocessor
register. Cleared by Initialize.

Bits 07 and 15

When set to one, places the DV11 in System

Write Enable

Maintenance mode, enabling the DV11 program
to write bits 07 and 15 of this register (SCR 15).

Cleared by Initialize. The System Control Register
must be word addressed when and while these bits
are set.

5-15

Read or Write

Table 5-7
Line Control Register Maintenance Bits
(For Synchronous Line Cards)

Bit(s)
00-01

Designation

Microprocessor Branch

Read/Write

Function

Whenever a branch instruction is encountered by the

True L

Microprocessor and the point tested by the Micro-

(Bit 00 - Branch A)

processor is true, the branch is enabled and one of

(Bit 01 - Branch B)

these bits will clear. Bit 00 = 0 if a Branch A instruc-

‘Read

tion causes a branch, and bit 01 = 0 if a Branch B

instruction causes a branch. (Microinstructions are
described in Section 4.7.)
07

Maintenance Bit

This bit displays the input bit stream to the receiver

Window

for the line selected by SRS 00—03. If LCR 09

Read only

(Transmitter Disable) is set to zero for the selected

line, the output of the selected line’s transmitter
will be the input data.

If LCR 09 was set to one and maintenance mode 01
was set in LCR 11, 12 for the selected line at bit 15

set time, the Maintenance Data bit (LCR 14) will be
the input data.
08

Maintenancé Clock

Simulates the transmitter and receiver clocks for every

Pulse

line for which maintenance mode 01 was set in LCR

Write

11,12 at LCR 15 set time. When set to one, causes
maintenance mode 01 receivers to input one bit each
and causes the corresponding transmitters to output

one bit each LCR 08 then clears itself. BIS and BIC
instructions should not be used to set this bit.
09

Transmitter Disable

When set to one, disables the transmitter for the 4-line

Write

group selected by SRS 02—-03 at LCR 15 set time.

This permits entry of Maintenance Data from LCR 14
to the receivers for the selected lines without inter-

ference from the lines’ transmitters.

11,12

Maintenance Mode

For the 4-line group selected by SRS 0203, these bits

Select

set normal operation or one of the three maintenance
modes at LCR 15 set time, as follows:
Mode

Normal Operation

Internal Maintenance Mode

External Maintenance Mode

Internal Maintenance Mode

for System Testing

LCR 11, 12 are cleared by Initialize. Maintenance modes
are described in Section 5.1.

Write

Table 5-7 (Cont)
Line Control Register Maintenance Bits

(For Synchronous Line Cards)

Bit(s)

| Designation
Maintenance Data

Function

When set to one at LCR 15 set time, simulates

| Read/Write
Write

data at the input to the receivers for the 4-line

group set in SRS 02-03, provided that maintenance mode 01 has been set for those lines (see
LCR 11, 12 description).

If LCR 14 is being used to simulate receiver data,
LCR 09 (Transmitter Disable) should be set to one
for the selected lines at LCR 15 set time to inhibit

additional input from the transmitters.

LCR 14 should be cleared when not in use for

simulating input data. Cleared by Initialize.
15

Control Strobe

When set to one, strobes LCR 13 into control
storage for the line set in SRS 00—03 and sets
LCR 09, 10,11, 12, 14 into control storage for
the 4-line group set in SRS 02—03, then clears
itself. May be set at the same time as the LCR

bits that it strobes into storage for the selected
line or line group.

Write

Table 5-8
Line Control Register Maintenance Bits

(For Asynchronous Line Cards)
Bit(s)

Designation

00-01

Microprocessor

Whenever a branch instruction is encountered by

Branch True L

the Microprocessor and the point tested by the

Function

Read /Write
Read

Microprocessor is true, the branch is enabled and
(Bit 00—Branch A)
(Bit 01—Branch B)

one of these bits will clear. Bit 00 = 0 if a Branch A
instruction causes a branch, and bit 01 = 0 if a Branch

B instruction causes a branch. (Microinstructions are
‘described in Paragraph 4.7.)

09-10

Maintenance Register

For the line number selected by SRS 00—-03, the

Selection Code 11

code of 11 specifies writing into the Maintenance

Write

Maintenance Internal

This bit, when set, loops the transmitter’s serial

Mode |

output lead to the receiver’s serial input lead. While

Write

operating in Maintenance mode, the EIA transmit

data leads, EIA received data leads, and the remote
Data Set Busy features are disabled. Normal operating
mode is assumed when this bit is cleared. Cleared by

Initialize,
15

Control Strobe

When set to a one, strobes the Maintenance register

Write

bit 11 into storage for the line specified in SRS
00—03, then clears itself. May be set at the same

time as the bit that it strobes into storage.

Table 5-9

Bit(s)
08

Designation

STEP

Function

When set to 1, causes the line number in CSR 00—03

\',

Control Status Register Maintenance Bits

Read/erte
Write ones

to be incremented by 1. If a status transition is
detected for the new line, Done (CSR 07) is set to 1.
Done does not inhibit Step. This bit is used principally

for maintenance and requires 1.2 microseconds * 10%
to execute. This bit is write ones only.

MAINT MODE

When set to 1, causes all status lines from all enabled

(Maintenance Mode)

modems to be logical ones. Used for maintanence.

Cleared by Initialize and Clr Scan (CSR 11).

5-18

Read or Write

APPENDIX A
PDP 11 MEMORY ORGANIZATION

AND ADDRESSING CONVENTIONS

The PDP-11 memory is organized into 16-bit words
consisting of two 8-bit bytes. Each byte is addressable

The highest 8K address locations (760000-777777)
are reserved for internal general registers and peripheral devices. There is no physical memory for
these addresses; only the numbers are reserved. As a

and has its own address location: low bytes are evennumbered, high bytes are odd-numbered. Words are
addressed at even-numbered locations only and the

result, programmable memory locations cannot be
assigned in this area; therefore, the user has 248K
bytes or 124K words to program.

high (odd) byte of a word is automatically included to
provide a 16-bit word. Consecutive words are therefore found in even-numbered addresses. A byte oper-

ation addresses an odd or even location to select an 8- |

bit byte.

A PDP-11 processor without the Memory Manage-

The Unibus address word contains 18 bits identified

ment Unit provides 16 address bits that specify 216
0r65,536 (64K) locations (Figure A-2). The maximum memory size is 65,536 (64K) bytes or 32,768

as A(17:00). These 18 bits provide the capability of

addressing 256K memory locations, each of which is
an 8-bit byte. This also represents 128K 16-bit words.

(32K) words. Logic in the processor forces address

In this discussion, the multiplier K equals 1024 so
that 256K represents 262,144 locations and 238K represents

bits A(17:16) to 1s if bits A(15:13) are all 1s, when the

processor 1s master, to allow generation of addresses
in the reserved area with only 16-bit control.

131,072 locations. This maximum memory

size can be used only by a PDP-11 processor with a

Memory Management Unit that utilizes all 18
address bits. Without this unit, the processor provides 16 address bits which limits the maximum mem-

ory size to 64K (65,536) bytes or 32K (32,768) words.

Bits 13, 14, and 15 become all 1s first at octal 160000
which is decimal 57,344 (56K). This is the beginning

Figure A-1 shows the organization for the maximum

processor

memory size of 256K bytes. In the binary system, 18

760000-777777, which relocates these last 8K bytes

of the last 8K bytes of the 64K byte memory. The

bits can specify 218 or 262,144 (256K) locations. The

converts

locations

160000-177777

numbering system is used to designate the
address. This provides convenience in converting the

(4K words) to the highest locations accessible by the
bus. These are the locations that are reserved for
internal general register and peripheral device

as shown below.

addresses; therefore, the user has 57,344 (56K) bytes
or 28,672 (28K) words to program.

octal

address to the binary system that the processor uses,

| 15

| 14

| 13

e
1

110

|09

|08

[ 07

|06

|05

|04

A
1

A
7

—

A
6

| 03|02

|01]|

S?QRESS\‘

|BINARY

A
0

J
1

OCTAL
~11-3176

08|07

16 BIT DATA WORD —#

000001

LOW BYTE

_HIGH BYTE

000000

000003

000002

USER ADDRESS SPACE
AVAILABLE USING 18
ADDRESS BITS ON
WITH MEMORY

,__4‘

}

PDP-11 PROCESSOR

)

L_/

MANAGEMENT OPTION.

INCLUDES 248K (253,952)

BYTES OR 124K (126,976)
WORDS.

757777

760001

.___%’

757776

,‘

760000

)
HIGHEST 8K (8192)

—

o k BYTES OR 4K (4096)

DEVICE REGISTER

WORDS RESERVED FOR

ADDRESSES.

777777

\7777786

4
ADDRESS IS BYTE NUMBER 262,143,,
4LAST
* MAXIMUM SIZE WITH 18 ADDRESS BITS IS 256K(262,144) BYTES OR 128K (131,072) WORDS.
o

I-1690

Figure A-1 Memory Organization for Maximum
Size Using 18 Address Bits

Memory capacities of 56K bytes (28K words) or
under do not have the problem of interference with

Memory Size
K-Words

160000 do not have a binary 1 in bit A13. No addresses are converted and there is no possibility of physical
memory locations interferring with the reserved
space.

4
-8
12
16

the reserved area, because designations less than

PDP-11 core memories are available in 4K, 8K, or

16K increments. The highest location of various size

core memories are shown.

24
28

K-Bytes
8
16
24
32

Highest Location
(Octal)
|

017777
0377717
057777
077771

117777

137777
157777

08|07

«— {6 BIT DATA WORD —#|
HIGH BYTE

LOW BYTE

000001

000000

000003

000002

USER ADDRESS SPACE

AVAILABLE USING 16
ADDRESS BITS ON
]

-—

PDP-11

PROCESSOR

) WITHOUT MEMORY

)

MANAGEMENT OPTION.
INCLUDES 56K (57,344)
BYTES OR 28K (28,672)
WORDS.

187777

157776

160001

160000

fi
ADDRESSE$ 160000177777 ARE CONVERTED

——
~

TO 760000 -777777

—~

THE PROCESSOR. THUS,

) THEY BECOME THE

HIGHEST 8K (8192) BYTES
OR 4K(4096) WORDS

RESERVED FOR DEVICE
%

177777 |

177776

LLAST ADDRESS IS BYTE NUMBER 65,535,

MAXIMUM SIZE WITH 16 ADDRESS BITS IS 64K (65,536) BYTES OR 32K(32,768) WORDS.
IH-1689

Figure A-2

Memory Organization for Maximum
Size Using 16 Address Bits

A-3

APPENDIX B
INTEGRATED CIRCUIT DESCRIPTIONS

B.1

INTRODUCTION

descriptions are intended as maintenance aids for trou-

The MSI and LSI Integrated Circuits (ICs) shownin

bleshooting to the IC level. ICs are sequenced alphanu-

the engineering drawings for the DV11 Synchronous

merically within this appendix; they are listed in Table

Multiplexer are covered in this appendix. These

B-1 for summary reference.

Table B-1
Integrated Circuit Modules Used in DV11

I.C. No.

Description

1472

Synchronous Receiver (P/SAR)

1482

Synchronous Transmitter (P/SAT)

UART

Universal Asynchronous Receiver Transmitter

COMS5016

Dual Baud Rate Generator

1488

Quad Line Driver

1489L

Quad Line Receiver

18-11660

Clock (Crystal)

3106

3341

RAM (256 X 1)

4007 \/
4015

5603

7442 V'
7450

7489 v/
7492 /

4-Bit X 64-Word Propagable Reglster

Dual-Binary to one of Four-Line Decoder

Quad Type D Flip-Flop

ROM (256 X 4)

4-Line to 10-Line Decoders
Dual 2-Input AND-OR-Inverter

64-Bit R /W Memory
Frequency Divider

7493

4-Bit Binary Counter

74121

Monostable Multivibrator

74123

Monostable Multivibrator

74150

Data Selector /Multiplexer

74151 V4

Data Selector /Multiplexer

74153

Dual 4-to-1 Data Selector

74154

4-t0-26 Decoder /Demultiplexer

74155

74157 V',

3-to-8 Decoder

2-to-1 Multiplexer

74161 ¥
74174 j

4-Bit Binary Counter
Hex D-Type Flip-Flop

74181

Arithmetic Logic Unit (ALU)

74175 ¥

74193 v/
74197
8242

Quad D-Type Flip-Flop

Synchronous 4-Bit Up/Down Counter
50 MHz Binary Counter/Latch

4-Bit Digital Comparator

2-Input 4-Bit Digital Mux

4-Bit Shift Register

B-1

This appendix also provides a functional description of

from the device terminals, consists of a Control regis-

the UART. It includes a table of UART signal func-

ter and a Match-Character Holding register. Con-

tions and simplified block diagrams and timing dia-

tiguous synchronous serial characters are compared

grams of the UART receiver and transmitter.

in a programmable Match-Character Holding register, character synchronized and assembled.

B.2

The Receiver Holding register, a buffer storage regis-

PR1472B SYNCHRONOUS RECEIVER

The P/SAR is a programmable receiver that 1nter-

ter with an associated Data Received flag, provides
an entire serial ‘“character time” for servicing

(P/SAR)

faces variable-length, serial data to a parallel data

(unloading) the receiver. The Match-Character Hold-

channel. The receiver converts a serial data stream

ing register, in conjunction with the comparator,

into parallel characters with a format compatible
with all standard synchronous, asynchronous, or

compares the serial data stream, provides an output
when the input bit pattern matches the contents of

isochronous data communications media. Only syn-

the Match-Character Holding register and causes

chronous operation is implemented on the DV1I;

character synchronization. A Master Reset is

therefore,

provided.

only

synchronous

operation

will be

discussed.

P/SAR signal mnemonics are listed in Table B-2 and

Figure B-1 is a block diagram of the P/SAR. The

described in detail in Table B-3. Pin connections are

P/SAR

shown in Figure B-2.

control

memory,

crL | 33

programmable

- SFR

2009 GEUOT

internal

——— SYNCHRONOUS
INPUT FOR

FE’SS

[ I

MODE ONLY

EPE

Vss

]
20] voo

TIMING & CONTROL

WwLS,

CONTROL

RECEIVER

w
8]

RR8

COMPARATOR

RECEIVER

RF'!9

RR7

HOLDING

RR‘S

—C

DENOTES SIGNAL PIN
UNDER CONTROL BY CHIP

DISABLE (CD PIN 6)*

MATCH CHARACTER HOLDING REGISTER

PUUYSodboobbe
RR

MHRL

MHR

11-2938

Figure B-1

PR1472B Programmable Synchronous Receiver (P/SAR)

Vss

Input/Output Name

Input/Output Symbol

Power Supply

Vss. Vop, VGG

Receiver Mode Select

RMS,, RMS,, RMS,

Match-Character

MHR; —~MHR

RMS _ [12

MHR _ [13

MHR, []
4

wLs
|,
[5

Holding Register

Word Length Select

1 @ \\s—// 40

WLS,; —WLS,

RRQL__ 7

RR, []8

RR_[]9

Chip Disable*

RR _[]10

-3

Receiver Holding

RR, —RR,

RR, []11

112

RR []13

114

RR []15

Parity Inhibit

Even Parity Enable
Status Flag Reset

SFR

Data Received .Reset

DRR

Data Received

Overrun Error

Framing Error*

Sync Search

Parity Error

Match Detect

MDET

Receiver Register Clock

Control Register Load

CRL

Match-Character

MHRL

MHR3|:17

| 24

MHR [ 18

[]19

Vop

[20

RMS

MHR
|
RMS
,
MHR
RI

MHR
CRL
MR

RRC

MDET
PE

FE/SS
OE
DR

DRR

SFR
WLS

MHR >

EPE

| Figure B-2 P/SAR Pin Connections

B.2.1

Synchronous Mode Operation

Synchronous data appears as a continuous bit stream

of contiguous characters at the input to the receiver

with no start or stop bits. Character synchronization
(the “‘framing” of this continuous bit stream into
characters of a predetermined fixed length), must be
accomplished by a comparison of this bit stream and
a synchronization sequence. The P/SAR is designed

to accommodate internal or external character synchronization by program control. Internal character

Holding Register
Load Receiver Input

MHR
4

11-2933

RRC

Master Reset |

[]16

goooOoooouguodguduyguududuu

Table B-2

P/SAR Signal Mnemonics

synchronization is used by the DVI11.

*Not used in DV11 synchronous operation

- B-3

Table B-3

P/SAR Signals
Pin Number
1

37,39, 2

I/O Name
Vgg POWER SUPPLY

Symbol

Vss

Function
+5 Volt Supply

RECEIVER MODE

RMS,;, RMS,,

A low-level input voltage, Vyp, applied to CD (pin 6)

SELECT

RMS,

enables RMS; , RMS,, and RMS; inputs. The Receiver
Mode Select Inputs, in conjunction with the Control
Register Load Strobe selects the Receiver operating

mode. RMS; , RMS, and RMS; are left high (connected
internally to Vyp via a pull-up resistor) to select the

synch-internal operating mode.
18,22

MATCH-CHARACTER

MHR, MHR,,

A low-level input voltage, Vi , applied to CD (pin 6)

17,36,3

HOLDING REGISTER

MHR, MHR,,

enables the inputs to the Match-Character Holding

38,4,40

DATA

MHR, MHR,,

MHR, MHRg

characters are input into the Match-Character Holding
Register with the MHRL Strobe (pin 34). If a character of less than 8 bits has been selected (by WLS; and

WLS,), only the least significant bits are accepted.
These inputs are switch selectable to the appropriate
input voltage.
5,23

WORD LENGTH

WLS, ,WLS,

SELECT

A low-level input voltage, Vyy, applied to CD (pin 6)

enables the inputs of the Control Register and Load
Strobe, CRL. Parallel 8-bit characters are input into
the Control Register with the CRL Strobe (pin 33),

WLS, and WLS, select the transmitted character length

from five (5) to eight (8) bits defined by the Truth
Table below:

WLS,

\4is

SELECTED WORD LENGTH

5 BITS
6 BITS

7 BITS
Viu

Vin

8 BITS

WLS; and WLS, are switch selectable to the appropriate
input voltage.

CHIP DISABLE

This line controls the disable associated with busable inputs and Tri-State outputs. A high-level input voltage,
Vig» applied to this line disables inputs and removes

drive from push-pull output buffers causing them to

float. Drivers of disables outputs are not required to sink
or source current. The I/O Lines controlled by Chip Disable are defined below. In the DV11, the Chip Disable
line has been hard-wired to a low-level input voltage.
INPUT LINES

TRI-STATE

OUTPUT LINES
CRL

DRR

EPE

SFR

MHRL

WLS,-WLS,

RMS; -RMS;

MHR,-MHRg

RR,-RRj
|

Table B-3 (Cont)

P/SAR Signals

I/O Name

Pin Number
7-15

RECEIVER HOLDING-

Symbol

RR,—RR,

Function
A low-level input voltage, Vi, applied to CD (pin 6)

enables the Receiver Holding Register outputs,

OUTPUT

RR; —RRy. The parallel data character, including parity
(RRy), appears on these lines. Program control selection

of a word length less than eight (8) bits will cause the
most significant bits of the character to be forced to a
low-level output voltage, V¢

. The character will be

right justified. RR; (pin 15) is the least significant bit

of the character.
16

Vi POWER SUPPLY

PARITY INHIBIT

-12 Volts Supply.

A low-level input voltage, V11> applied to CD (pin 6)
enables the EPE and PI inputs.

EVEN PARITY ENABLE

EPE

The Even Parity Enable Input and the Parity Inhibit
Input to the Control Register, in conjunction with the

Control Register Load Strobe, select even, odd or no
parity to be verified by the receiver. A high-level input

voltage, Vyyy, applied to EPE selects even parity if a
low-level input voltage, Vjp, selects odd parity if a low-

level input voltage is applied to Parity Inhibit. PI and
EPE are switch selectable to the appropriate input
voltage.

EPE

SELECTED PARITY

ODD

Vil

EVEN

NONE

X — either Vyp or Vig- When programmed, the appropriate parity is verified following the last data bit of a
character.

(

STATUS FLAG RESET

SFR

A low-level input voltage, Vyp, applied to CD (pin 6)
enables the SFR input. A low-level input voltage, Vi1

applied to this line resets the PE and OE Status Flags.
25

DATA RECEIVED

DRR

RESET

A low-level input voltage, Vyy, applied to CD (pin 6)
enables the DRR input. A low-level input voltage, 7

applied to this line resets the DR Flag
26

DATA RECEIVED
FLAG

A high-level output voltage, Vg indicates that an entire character has been received and transferred to the

Receiver Holding Register. When operating in the
synchronous mode, the first SYN character, when loca-

ted and transferred to the Receiver Holding Register,
will not cause DR to go to a high-level output voltage,
Vg but will cause MDET to go to a high-level output
voltage. Character transfer to the Receiver Holding

Table B-3 (Cont)
P/SAR Signals

I/O Name

Pin Number

OVERRUN ERROR

Symbol
OE

Function

A low-level input voltage, Vyp, applied to CD (pin 6)
enables the OE output. A high-level output voltage, Vo,
indicates that the previously received character was not

FLAG

read (DR line not reset) and was, therefore, lost before
the present character was transferred to the Receiver

Holding Register. This transfer occurs in the center of

the last bit of a received synchronous character, at which
time this flag is updated.
|
FRAMING ERROR/

FE/SS

SYN SEARCH

- FE/SS is a two-way (I/O) bus. When programmed for the
SYNCHRONOUS MODE, this line is an input and is not
under control of CD. This line should be driven by a
tri-state or an open collector device.
If programmed for INTERNAL CHARACTER
SYNCHRONIZATION (DV11

case), a transition from

a low-level input voltage, Vyj,toa high-level input
voltage, Vypy, initiates the automatic internal “SYN”
CHARACTER search operation.

Prior to initiation of this operation, the Receiver Holding
Register is “transparent” so that its contents are identical to that of the RECEIVER REGISTER. Upon

receipt of a SYN character, (previously loaded into the
Match-Character Holding Register during initialization),
the Receiver Holding Register becomes non-transparent,

the MATCH DETECT output (MDET) goes to a high-

level output voltage, Vg, but, the Data Received (DR)
FLAG does not assume a high-level output voltage,

Vog: The P/SAR is now in character synchronization.
Subsequent SYN or data character will be transferred to
the RECEIVER HOLDING REGISTER as they are

assembled (at the center of the last bit) and the DR FLAG
will be raised. A transition from a high-level input voltage,
VIH’ to a low-level input voltage, VIL’ causes the
P/SAR to lose character synchronization and forces the

Receiver Holding Register to become “‘transparent.”
29

PARITY ERROR

A low-level input voltage, Vyy, applied to CD (pin 6)
enables the PE output. Parity, if programmed, is verified upon receipt of the center of the parity bit which
is the last bit of a synchronous character. If a parity

FLAG

error exists, the associated PE register is set to a highlevel output voltage, V.
30

MATCH DETECT
FLAG

MDET

A high-level output voltage, V5, indicates that the contents of the Receiver Register are identical to the con-

tents of the Match-Character Holding Register. This flag
is set to a high-level output voltage, Vyp, at the center
of the last bit of a synchronous character.

/——!ru.\.

Table B-3 (Cont)
P/SAR Signals

Pin Number
31

I/O Name

Symbol

RECEIVER REGISTER

RRC

Function

'This fifty (50) percent duty cycle clock provides the
basic receiver timing. The negative transition from a high-

CLOCK

level input voltage, Vyyy, to a low-level input voltage, Vpp,

shifts data into the RECEIVER REGISTER at a bit rate

‘determined by RMS;, RMS, and RMS;. Synchronous
operation requires that this negative transition occur at

the center of each data bit.

MASTER RESET

A high-level input voltage, Vyyy, applied to this line resets

timing and control logic to an idle state, sets the contents of the Receiver Holding Register to a high-level

output voltage, Vypy, resets the contents of the MatchCharacter Holding Register, the MDET, DR, PE, FE,
and OE outputs to a low-level output voltage, Vyy
, but
does not effect the contents of the control register.
33

CONTROL REGISTER

CRL

A low-level input voltage, Vyy, applied to CD (pin 6)
enables the CRL input. A low-level input voltage,

LOAD STROBE

Vi1 applied to this line enables inputs to DC “D Type”
Latches of the Control Register and loads it with

Control Bits (EPE, PI, RMS; , RMS,, RMS;, WLS,,
WLS,). This line is hard-wired to a low-level input
voltage, VIL'

MATCH CHARACTER

MHRL

A low-level input voltage, Vyy, applied to CD (pin 6)

HOLDING REGISTER

enables the MHRL input. A low-level input voltage, Vi,

LOAD STROBE

applied to this line enables input to DC “D Type”
Latches of the Match-Character Holding Register and
loads it with the Match-Character Register data,

MHR, —~MHR5. A high-level input voltage, Vig applied
to this line disables the Match-Character Holding Regis-

ter. This line may be strobed or hard-wired to a low-level
input voltage, Vyj.

RECEIVER INPUT

The serial input data stream received on this line enters
the Receiver Register determined by the character length
and parity programmed.

An example of synchronous timing is shown in Fig-

The Control register is loaded by hard-wiring CRL to

~ure B-3. Device operation is programmed subsequent

a low-level input voltage, which defines the internal

to being forced into its idle state. The P/SAR will

synchronous mode of operation and ‘‘times one”

enter a defined idle state when the Master Reset

clock rate selection, character length and selected

(MR) line is strobed to a high-level input voltage. In

parity if required. Table B-4 illustrates all program-

this state, all timing and control logic are reset, the

mable synchronous formats.

contents of the Receiver Holding register is set to a
high-level output voltage and all output flags are

Character synchronization

reset to a low-level output voltage. The MR also

requires receiver recognition of specific bit pattern(s),

causes the contents of the Match-Character Holding

which define the relative position of synchronous

from the data stream

characters in the data stream and subsequent charac-

ter assembly.

TCO

MR ]

TR,TR

) 4

THRL —

CTS

THRE

TRO

(112]3]a[s]e]|7[s|[P|F|iI|[L]L]

[c|H]|a[R[1]2]3[4a]|5]6]7[8]|P]|1]2]|3|4a]|5]|6]|7]8]|P]

—

—1

BAR

DD/EOC

[

*CLOCK SHOWN IS BIT RATE CLOCK (1X).

NOTE: o).V,

MS=ViL
MS=VIH
wLs=VIH
wLs=VIH
11-2901

Figure B-3

Synchronous Timing Example (P/SAR)

Table B-4

Programmed for internal character synchronization,

Sync Mode Control Definition

with a high-level input voltage on the Sync Search
line, the Receiver Holding register is transparent and

Control Word

Character Format

RWW
MLL

its contents are identical to the Receiver register. The

data stream, gated into the Receiver Input (RI) by the

SSSPP

negative tr.ansition of the Rece.iver reg.ister Cloc.k
Data

Parity Bit

3211E

Bits

Checked

i 8 g 8 (1) |

10100

0dd

r.egloster to 1ts non-traqsparent state and initializes

10101
1011 X
11000

6
6
7

Even
None
0dd

11101
1 111X
X_Sets to SYNC Mode

3
3

7
7
3

Even
Nore
0dd

Even
Nore

Mqtch Dete-ct (MDET), returns the Rece1ve1: I-.Ic')ld.lng

timing and control loglc, but does not set the Data
Received flag to a high-level output voltage. The
character. followmg the mgtch will be tran.sferred to

the Receiver Holc'hng register at the receipt of the
center of its last bit and the Data Recglved flag is set
toa h1gh-l§vel output voltage. Depending on line dis01'p¥1ne, this last .chara.cter may also be a synchronizing char.acter, in which case, MDET will continue
to be a high-level output voltage when the Data
Received flag is set. Therefore, sequence verification

(When RMS; =1, the receiver operates in the
internal character SYNC mode, as required by

the DV11.)

Match-Character Holding register.

A match, indicated by a high-level output Voltage.on

Nore

11001
1 101X
11100

compared with the preprogrammed character in the

g‘(};

1 001 X

—

(RRCO), Shlf'FS through the Receiver register a}nd is

can be performed by the system. Selection of a word
length of less than eight bits causes the most signifi-

cant bits of the character to be forced to a low level
output voltage.

nization to be lost and initiates transparency of the
Receiver Holding register.

chronous character. For word lengths less than eight
bits, the parity bit appears immediately to the left of

B.3

the last bit in the character. If a parity error exists, the

(P/SAT)

associated PE register is set to a high-level output

The P/SAT is a programmable transmitter that inter-

PT1482B SYNCHRONOUS TRANSMITTER

faces variable-length, parallel-input data to a serial

voltage.

channel. The transmitter converts parallel characters
Transfer of a character to the Receiver Holding regis-

into a serial data stream with a format compatible

ter sets the associated Data Received Register flag

with

(DR) to a high-level output voltage. If the Data

isochronous data communications media. Only syn-

all

standard

synchronous,

aysnchronous

Received Register flag has already been set to a high-

chronous operation is implemented on the DV11;

level output voltage and has not been cleared by

therefore,

external logic, the transfer of a character to the

discussed.

only

synchronous

operation

will

Receiver Holding register causes the previous character to be lost (written over) and is alerted by Overrun

Figure B-4 is a block diagram of the P/SAT. The

Error flag, which is a high-level output voltage. In

P/SAT

normal operation, the Data Received flag is reset by

from the device terminals, consists of a Control regis-

internal

control

memory,

programmable

DRR when the Receiver Holding register is serviced

ter and a Fill (Idle) Character Holding register. Con-

(unloaded). The status flags, PE and OE, are also

tiguous,

provided with an external reset SFR. A low-level

synchronous mode, with the automatic insertion of a

input voltage on Sync Search during the negative

programmable

transition of the RRC causes character synchro-

absence of parallel input data.

serial characters are transmitted, in the
Fill

(Idle)

Character

during

the

SoaeLe004 Sa00a0ed
FHRL

THUL

TRANSMITTER HOLDING REGISTER

EPE

TRANSMITTER REGISTER

INEVAY,
MULTIPLEXER

._.

TRO

Vss

| |

us, E>_*
WLS,

HOLDING REGISTER

b b Lo

[

- FILL CHARACTER

THRE .__J
CRL

—

If programmed, parity is verified upon receipt of the

center of the parity bit which is the last bit of a syn-

TIMING 8

VDD

CONTROL

é¥$$%£
CLK

CTS

DAR

VGG

TCO

22|

DENOTES

SIGNAL PIN

CONTROL BY

UNDER

CHIP DISABLE

(CD PIN22) SEE ELECTRICAL
CHARACTERISTICS.
1i-2939

Figure B-4

PT1482B Programmable Synchronous Transmitter (P/SAT)

Table B-5

The Transmitter Holding register, a buffer storage

P/SAT Signal Mnemonics

for servicing (loading) the Transmitter (Shift) regis-

ter. Under internal logic control, the (P/SAT) multi-

plexer loads

data from the Transmitter Holding

into the Transmitter Register. A Master Reset is
provided.
P/SAT signal mnemonics are listed in Table B-5 and
are described in detail in Table B-6. Pin connections
are shown in Figure B-5.
B.3.1

Synchronous Mode Operation

Synchronous transmission requires that characters
(programmably variable from 5 to 8 data bits plus
parity) are contiguous with no start or stop bits. Since
the requirement that characters are contiguous does

not imply that the system servicing the transmitter

always has ample time to load the Transmitter Holdmitted when data has not been loaded into the
Holding

This

character

defined as the Fill or Idle Character and a separate
register has been provided to load this character upon

Power Supply

VSS’ VDD’ VGG

Even Parity Enable

EPE

Parity Inhi_bit

Control Register Load

CRL

Clock

CLK

Clock Rate Select

CS; —CS,

Mode Select

MS; —MS,

Data Not Avaflable Reset

DAR

Data Not Available

Data Delimit/End of

DD/EOC

Transmitter Holding

[]3

38 |7 TRg

CRL

[]4

37 1 FRg

cLk

36 [1 TRy

cs,

35 |7 FRo

csp

39 [J wLs,

[0 TRg

Ms, []8

33 [] FRg

MSp

32 [1 TRg

DAR []10

31 [] FRg

TCO [

30 [ TRa

DA []12

29 [1 FRy

[]13

28 [1 TRy

THRE []14

27 [0 FRy

TRO

[]15

26 1 TR,

Veg

251 FR,

cTs

24 [ TR,

MR []18

23 |] FR,

THRL

[]19

FHRL

CTS

Master Reset

Transmitter Holding

THRL

Fill-Character Holding

FHRL

Chip Disable*

Fill-Charact.er Holding

FR; —FRg

22 1 co

Clear-To-Send

1 Vpp

Transmitter Holding
11-2902

Figure B-5

TRO

Output

40 [ wLS;,

EPE

THRE

~ Register Empty
Transmitter Register

Vss 1

| TCO

Character

initialization. The Fill Character Holding register is

loaded by strobing the Fill Character Holding Register Load (FHRL) line to a low-level input voltage.

Input/Output Symbol

Transmitter Clock Out

ing register, it is necessary that a character be transTransmitter

Input/Output Name

TR; —TRg

Word Length Select

P/SAT Pin Connections

WLS, —WLS,

*Not used in DV11 synchronous operation.

B-10

Table B-6
- P/SAT Signals
Pin Number

Function

Symbol

I/0 Name

Vgg POWER SUPPLY

Vss

EVEN PARITY ENABLE

EPE

PARITY INHIBIT

+5 Volt Supply
A low-level input voltage, Vyy, applied to CD (pin 22)

enables the EPE and Pl inputs.

The Even Parity Enable Input and the Parity Inhibit
Input to the Control Register, in conjunction with the
Control Register Load Strobe, select even, odd or no

parity to be generated by the Transmitter. A high-level
input voltage, Vg, applied to EPE selects even parity

and a low-level input voltage, Vyy, selects odd parity if
a low-level input voltage is applied to Parity Inhibit. PI
and EPE are switch selectable to the appropriate input
Pl

EPE

VIL
VIL

VIL
VIH

VIH

voltage.

SELECTED PARITY

ODD
EVEN
NONE

X —either Vyp or Viy. When programmed, the appropriate parity is generated following, and is contiguous with,
|

the last data bit of a character.

CONTROL REGISTER
LOAD STROBE

CRL

to CD (pin 22)
A low-level input voltage, Vi, applied
enables the CRL input. A low-level input voltage, Vi,
applied to this line enables DC Latches of the Control

a low-level input voltage Vyy.
TRANSMITTER
REGISTER CLOCK

TRC

This is a fifty (50) percent duty cycle clock. The positive
going edge of this Clock shifts data out of the Transmitter
- Register at a Times One rate bit as determined by the
Control Bits CS; and CS,, and provides the basic time
reference for all device functions.

6—7

CLOCK RATE SELECT

CS; —CS,

A low-level input voltage, Vi, applied to CD enables the
CS, and CS, inputs. These two lines select the internal
clock rate divider ratio to produce the transmitter bit

rate defined by the Truth Table below:
CSy

CSq

VIL

VIH
VIiH

VIL
VIH

ViL

VIH

SELECTED CLOCK
INPUT RATE

1 X BIT RATE

16 X BIT RATE

32 X BIT RATE
64 X BIT RATE

These lines are hard-wired to a low-level input voltage.
MODE SELECT

MS,; —MS,

A low-level input voltage, Vyy, applied to CD (pin 22)

enables the MS; and MS, inputs. These lines select the
transmitter operating mode.

Table B-6 (Cont)

P/SAT Signals
Pin

I/O Name

Number

DATA NOT AVAILABLE

Symbol
DAR

RESET

Function

A low-level input voltage, Viy, applied to CD (pin 22)
enables the DAR input. A low-level input voltage, VIL’

applied to this line resets the Data Not Available Flag.
11

TRANSMITTER

TCO

CLOCK OUTPUT

This output is a clock at the transmitted bit rate. The
negative going edge of this clock corresponds to the cen-

ter of each transmitted data bit. The positive going edge
corresponds to the start of each data bit transition. All

waveforms in this specification are referenced to TCO.
12

DATA NOT AVAILABLE

FLAG

A low-level input voltage, Vi, applied to CD (pin 22)
enables the DA input. A high-level output voltage,

VOH’ on this line indicates that a Fill-Character has been
transmitted, since a character was not loaded into the

Transmitter Holding Register by the center of the last

bit of a Synchronous Character.
13

DATA DELIMIT/

DD/EOC

END OF CHARACTER

A low-level output voltage during synchronous transmission indicates that the last bit of a character is being
transmitted.

TRANSMITTER

THRE

HOLDING REGISTER

A low-level input voltage applied to CD (pin 22) enables

the THRE input. A high-level output voltage, Vops on

EMPTY

this line indicates the Transmitter Holding Register is

empty and has transferred its contents to the Transmitter
Register and may be loaded with a new character. This
line goes to alow-level output voltage, Vo1, when THRL
goes to a low-level input voltage, Vi

TRANSMITTER

TRO

The contents of the Transmitter Holding Register are

serially shifted out as an NRZ waveform on this line provided that a character was loaded into the Transmitter

Holding Register prior to DA Flag (in Synchronous

Mode). If a character was not loaded prior to a DA
Flag, the contents of the Fill-Character Register are transmitted as the next character.

VG POWER SUPPLY

CLEAR-TO-SEND

~12 Volts Supply

CTS

The Clear-To-Send Control initiates or disables transmission as a function of the state of this line. A high-level
input voltage, V1yy initiates serial data transmission pro-

vided a character has been loaded into the Transmitter

Holding Register. A low-level input voltage, Vy1
., applied
to this line during transmission allows completion of that
character only, after which the output will continue to

mark until a high-level input voltage is applied.

Table B-6 (Cont)
P/SAT Signals
Pin Number

I/O Name

MASTER RESET

Symbol

Function

The rising edge of a high-level input voltage, Vi applied
to this line resets timing and control logic to an idle state,

sets THRE, the contents of the Fill-Character Holding
Register, and TRO to a high-level output voltage, Vou19

TRANSMITTER
HOLDING REGISTER

THRL

A low-level input voltage, Vyy, applied to CD (pin 22)
enables the THRL input. A low-level input voltage, Vi

LOAD STROBE

applied to this line enables DC Latches of the Transmitter Holding Register and loads it with the Trans- mitter Holding Register data and forces THRE to a low-

level output voltage, Vo1
.- A high-level input voltage,
Vi applied to this line disables the Transmitter Holding

FILL-CHARACTER

FHRL

A low-level input voltage, Vyp, applied
to CD (pin 22)

| HOLDING REGISTER

enables the

FHRL input. A low-level input voltage, Vi

applied to this line enables DC Latches of the Fill-

Character Holding Register and loads it with the FillCharacter Register data, FR; —FRg. A high-level input
voltage, Vg, applied to this line disables the Control

level input voltage, Vyp.
21

Vppp POWER SUPPLY

CHIP DISABLE

Ground.

. CD

This line controls the disconnect associated with busable
inputs and Tri-State outputs. A high-level input voltage,

Vim applied to this line removes drive from push-pull
outputs causing them to float. Drivers of disabled inputs
are required to sink or source current. The I/O lines con-

trolled by Chip Disable are defined below. In the DV11,
the Chip Disable line has been hard-wired to a low-level
input voltage.

INPUT LINES

TRI-STATE

OUTPUT LINES
CRL

THRL

EPE

FHRL

THRE

FR; —FRyg

CS; —-CS,

TR; —TR,

MS; —MS,

WLS, —WLS,

DAR

B-13

Table B-6 (Cont)
P/SAT Signals

Pin Number

I/O Name

Function

- Symbol
FR, —FR,

A low-level input voltage, Vyy, applied to CD (pin 22)

23,25

FILL-CHARACTER

27,29

HOLDING REGISTER

enables the inputs of the Fill-Character Holding Register

31,33

DATA INPUTS

and associated Load Strobe, FHRL. Parallel 8-bit characters are input into the Fill-Character Holding Register

35,37

with the

FHRL Strobe (pin 20). If a character of less

then 8 bits has been selected (by WLS; and WLS,) only
the least significant bits are accepted. These inputs are

switch selectable to the appropriate input voltage.
During Synchronous transmission, the Fill-Character is

transmitted if a character was not loaded into the
Transmitter Holding Register prior to a DA Flag;i.e.,
the Transmitter Holding Register did not contain a

character at the center of the last bit being transmitted
from the Transmitter Register. A high-level input voltage,

Vg Will cause a high-level output voltage, Vyyy, to be

transmitted, Least Significant Bit (FR;) to Most Signifi-

cant Bit (FR,
) order.
24, 26

TRANSMITTER

28,30

HOLDING REGISTER

enables the inputs to the Transmitter Holding Register

32,34

DATA INPUTS

and associated Load Strobe, THRL. If a character of less

TR, ~TR,

A low-level input voltage, Vyy, applied to CD (pin 22)

than 8 bits has been selected (by WLS; and WLS,), only

36,38

the least significant bits are accepted. A high-level output
voltage, Vg, will cause a high-level output voltage to be

transmitted, Least Significant Bit (TR;) to Most Signifi-

cant Bit (TR
) order.
3940

WORD LENGTH

WLS; ~WLS, | Alow-level input voltage, Vyy ,applied to CD (pin 22)
enables the inputs of the Control Register and Load
Strobe, CRL. Parallel 8-bit characters are input into the

Control Register with the CRL Strobe (pin 4), WLS;
and WLS, select the transmitted character length from
five (5) to eight (8) bits defined by the Truth Table
|
below:
WLS,

WLS,

5 BITS

6 BITS

A
Vig

SELECTED WORD LENGTH

7 BITS
Vi

8 BITS

WLS, and WLS, are switch selectable to the appropriate
input voltage.

B-14

(

The P/SAT will enter a defined idle state when the

Table B-7

MR is strobed to a high-level input voltage. In this

SYNC Mode Control Definition

state, all timing and control logic are reset, the Trans-

mitter Register Output continues to mark, the Trans-

Control Word

Character Format

mitter Holding Register flag is set to a high-level

output voltage, the Data Delimit/End of Character

(DD/EOC) flag is set to a low-level output voltage,

MMLL

and the contents of the Fill Character Holding regis-

SSSSPP

Data

Parity

ter are forced to a high-level voltage.

21211E

Bits

Bit

An example of synchronous timing is shown in Fig-

000O00O0

Odd

ure B-6. The Control register is loaded by hard-wir-

00001

Even

ing CRL to a low-level input voltage which defines

10001

None
Odd

Added

synchronous mode of operation, character length,

00100

selected parity if required, and the Times One clock

100101

Even

rate selection. Table B-7 illustrates all the program-

None

mable synchronous character formats.

01000

Odd

01001

Even

001

The character transferred into the Transmitter regis-

10101

ter (from the Transmitter Holding register
or the Fill

Character Holding register) is determined at the center of the last bit of the character being transmitted.

None

01100

0dd

101101

Even

None

0111X

Sets to SYNC Mode

ss.

MR _[]__
MHRL

RRC

SN Tc[F[A[R[SVIN] Te[RIARR[SVIN] Te[A[AlR[1 2 [ [4[s [e]7 [P]
(.

CHARACTERTM1
MDET

——

cHARACTER*2

——

J\o

cHARACTER*3

——

]

DRR

cHARACTER*4
]

]

RR,RR

[SIYIN] [clu]alr[s|Y|n] [c[n][a[r[s|Y[N] [c]n[a[r]1]2]3][4]5]6]7]P]

) CHARACTER® cHARACTER®z

SFR

CHARACTERTMS CHARACTER®a

]

CLOCK SHOWN IS BIT RATE CLOCK (1X)
11-2900

Figure B-6

Synchronous Timing Example (P/SAT)

B-15

If, at this time, no character has been loaded into the
Transmitter Holding register, the Fill Character is
loaded into the Transmitter register at the end of the
bit being transmitted and a Data Not Available
(DNA) flag is set to a high-level output voltage. This
Fill Character will be repeatedly transmitted until a
character is loaded into the Transmitter Holding register, at which time, the DNA flag is reset, the Fill
Character will be completed and the newly-loaded
synchronous character will follow contiguously.

The Data Delimit/End of Character flag has been
provided to indicate the transmission of serial data
on the Transmitter register output.

The Data Delimiter/End of Character flag is defined
as a low-level output voltage during transmission of
the last bit of a synchronous character and when the
P/SAT is in the idle state.
B.4

UART FUNCTIONAL DESCRIPTION

The UART is a MOS/LSI device packaged in a 40-

pin DIP. It is a complete subsystem that transmits
and receives asynchronous data in duplex or half

A high-level output voltage, on the THRE flag

duplex operation. The receiver and transmitter can

indicates that the Transmitter Holding register is

operate simultaneously. The transmitter accepts par-

empty and may be loaded with a character. Data on

the inputs of the Transmitter Holding register is loaded when the Transmitter Holding Register Load
(THRL) line is strobed to a low-level input voltage,

allel binary characters and converts them to a serial
asynchronous output.

The receiver accepts serial asynchronous binary char-

forcing the THRE flag to a low-level output voltage.

acters and converts them to a parallel output. The

This data must be stable prior to THRL going to a

high-level input voltage, since this register is a set of
DC latches which are enabled by THRL.

receiver and transmitter clocks are separate and must

be 16 times the desired baud rate. The allowable
clock rate is DC to 160 kHz.

Control bits are provided to select: character length
of 5, 6, 7, or 8 bits, (excluding parity) mode, odd or

If the Clear-to-Send (CTS) line is at a low-level input
voltage, or if the Transmitter register is in the process
of transmitting a character, the character in the
Transmitter Holding register will not be transferred
down to the Transmitter register and the THRE flag
will remain at a low-level output voltage. Raising the

even parity, and one or two stop bits for 6, 7, or 8-bit

characters. For 5-bit characters, 1 or 1-1/2 stat bits

are used. The format of a typical input/output serial
word is shown in Figure B-7.

Both the receiver and transmitter have double char-

CTS line to a high-level input voltage, or completion
of transmission of a character from the Transmitter

acter buffering so that at least one complete character

register, causes the automatic transfer of the character in the Transmitter Holding register to the Transmitter register which forces the THRE flag
to be set
to high-level output voltage. The selected parity is
added to the data during the transfer to the Trans-

is always available. A register is also provided to

mitter register and serial transmission is initiated as

transmitter data buffer (holding) register can be

an NRZ waveform. A low-level input voltage applied

loaded with a character when the TBMT (Trans-

to CTS during transmission allows completion of
that character only, after which the device enters the
idle state and the output will continue to mark until a

mitter Buffer Empty) line goes high. Loading is

high-level input voltage is applied.

MARK (1)

SPACE(O)

store control information.

A block diagram and simplified timing diagram for

the UART transmitter are shown in Figure B-8. The

accomplished by generating a short negative pulse on
the DS (Data Strobe) line. The positive-going trailing

edge of the DS pulse performs the load operation.

FIRST CHARACTER

‘l NEXT

‘l CHARACTER

START DATA1 DATA2 DATA3 DATA4 DATAS5 DATA6 DATA7 DATA8 PARITY STOP1 STOP2 START DATA1
r -

1 LSB !

| MSB 1|

|
f
— - TS
ST
TIm STT
I
I
|

LJ__J__I__L_J__I__l_J__I_ -1

- ="

11-2205

Figure B-7

Format of Typical Input/Output Serial Character

B-16

PARALLEL

DATA INPUT

(bB1—DB8)

DATA STROBE (DS)

TRANSMITTER BUFFER

EMPTY

START

SERIAL OUTPUT (50)
|

]

(TBMT)

ASYNCHRONOUS

END OF

sTop START

DATA

| LA

DATA

TRANSMITTER

TIMING

l
‘

]‘I

CHARA(CETOECR)

STOP

J—'__

DIAGRAM

NO.STOP BITS—Ls]
EVEN PAR. SEL.—2s CONTROL
35

NO PARITY—»

BITS/CHAR. =128,

HOLDING

CONTROL

STROBE

PAR

TM Gen ["]
OUTPUT
LOGIC

(BDO7 ——»
BDO6 —»

BDO5 —»

BITS ) BDO3——
28

BDO2 ——m

XMTR

BDO1 —2'5.
\‘-.
,,.

STROBE

END OF

=?HAF§ACTER

XMTR

HOLDING

SHIFT

| BDOO
DATA

DECODER

EOC

DATA <| BDO4 —*

SERIAL

—® QUTPUT

LOAD

SHIFT
i

5> TRANSMITTER
» BUFFER

TBMT
F/F

EMPTY

GENERATOR

11-2207

Figure B-8

UART Transmitter, Block Diagram and Simplified Timing Diagram

in this state until transmission of a new character

UART transmitter Shift Register when this register

begins.

becomes empty. The desired start, stop and parity
bits are added to the data and transmission begins.

One sixteenth of a bit time before a complete charac-

A block diagram and simplified timing diagram for

ter (included stop bits) has been transmitted, the

the UART receiver are shown in Figure B-9. Serial

EOC (End of Character) line goes high and remains

asynchronous data is sent to the SI (Serial Input) line.

START

SERIAL INCPHUOTN(()SUIS)
RECEIVED

DATA

AVAILABLE

(DA)

START
'/

STOP

DATA

STOP

| Ll

PARALLEL F;g{&_ I:‘,ODUB'.I')

RESET DATA
AVAILABLE(RDA)

RECEIVER

TIMING

DIAGRAM
11-2209

REC DATA
AVAILABLE

REC
DATA

ENABLE

FRAMING
ERROR

DATA BITS
BDO?

REC
PARITY
ERROR

OVERRUN

STATUS
WORD
ENB

AND GATES
BDOO

rIrtrrLT
——»

AND GATES

RESET

DATA—
2ol R

AVAIABLE

DATA

OVERRUN

PARITY

FRAME
C

HOLDING REGISTER

I S

SERIAL
DATA
INPUT

cLock

LQCK

54
RECEIVER SHIFT REGISTER

fi ~

CONTROL LOGIC

ng |
EVEN
PARITY
SELECT

Tss
NO
PARITY

T37

DATA AVAILABLE
PARITY

ARITY

ERROR

FRAMING

ERROR

Tsa

NB2
NB1
NUMBER OF
BITS/CHARACTER
11-2208

Figure B-9

UART Receiver, Block Diagram and Simplified Timing Diagram

B-18

The character is automatically transferred to the

The UART searches for a high to low (mark to space)

fers the state of the framing error and parity error to

transition on the SI line. If this transition is detected,

the Status Holding register. When the DV11 accepts

the receiver looks for the center of the start bit as the

the receiver output, it drives the RDA (Reset Data

first sampling point. If this point is low (space), the

Available) line low which clears the DA line. If this

signal is assumed to be a valid start bit and sampling
continues at the center of the subsequent data and

line is not reset before a new character is transferred

stop bits. The character is assembled bit by bit in the
receiver Shift Register
in accordance with the control

line goes high and is held there until the next charac-

to the receiver Holding register, the OR (Overrun)

ter is loaded into the receiver Holding register.

signals that determine the number of data bits and
selected and does not check, the PER (Receiver Par-

Figure B-10 is a pin/signal designation diagram for
the UART. The function of each signal is given in

ity Error) line goes high. If the first stop bit is low, the

Table B-8. In the Function column, the references to

stop bits and the type of parity, if selected. If parity is

FER (Framing Error) line goes high. After the stop

high and low signals are with respect to the pins on

bit is sampled, the receiver transfers in parallel the

the UART. This information is used during servicing

contents of the receiver Shift Register into the receiv-

of the device. Programmers should refer to the DV11

er data buffer (holding) register. The receiver then

sets the DA (Received Data Available) line and trans-

cerning the function of these signals.

119
DA ——— RECEIVE DATA AVAILABLE
15
OR — OVERRUN

RESET DATA AVAILABLE 20 RDA
SATUS WORD ENABLE ——>q SWE
RECEIVED DATA ENABLE 29 RDE
~

RECEIVER CLOCK

——

14
FER -——— FRAMING
PER

RCP

ERROR

H3
& RECEIVE PARITY ERROR

20
SERIAL INPUT »— S|

DATA BIT INPUTS

33|
(—»— DB8
32
—»— DB7
31
———
DB6
30
——
DB5
29
DB4
28

RD8 ——»)

RD7 6—»

RD6 &
18
RDS |——»

RD4 Té———"

-»—{ DB3

27
—»——26
| —+>——

RD3 ———»

ROz
RDt

DB2
DBI

23
DATA STROBE »—C
4

TRANSMITTER CLOCK —»———

;
RECEIVED DATA BITS
¢

}|——»

SO —2—2'—> SERIAL OUTPUT

TBMT |—— TRANSMITTER BUFFER EMPTY

24
EOC ——» END OF CHARACTER

TCP

XR CS NB2NB1 NP PE2 SB

EXTERNAL RESET —»————l
CONTROL STROBE

NO.OF BITS PER CHAR{
NO PARITY

PARITY SELECT

TWO STOP BITS

—

|37

|39 |36
NOTE:

Pini=+5V
Pin2=-12V
Pin 3= GROUND

F
.

11-2214

Figure B-10

UART Signal/Pin Designations

Table B-8

UART Signal Functions

Pin No.

Mnemonic

- Name

Func_tioh

512

RD1-RD8

Received Data

Eight data out lines that can be wire ORed. RD8 (pin 5) is
the MSB and RD1 (pin 12) is the LSB. When 5, 6, or 7 bit

character is selected, the most significant unused bits are
low. Character is right justified into the least significant

bits.

- PER |

Receive Parity

Goes high' if the»-'received character parity does not agree

Error

with the selected parity.

FER

Framing Error

Goes high if the received character has no valid Stop bit.

Overrun

Goes high if the previously received character is not read
(DA

line

not

reset)

before

the

present

character

transferred to the receiver Holding Register.

SWE

Status Word Enable

RCP

Receiver Clock
|

RDA

Reset Data

When low, places the status word bits (PE, OR, TBMT, FE,

and DA) on the output lines.

Input for an external clock whose frequency must be 16
times the desired receiver Baud rate.

When low, resets the received DA (Data Available) line.

Available
19

Received Data

Goes high when an entire character has been received and

Available

transferred to the receiver Holding Register.

Input for serial asynchronous data.

Serial Input

External Reset

After power is turned on, this line should be pulsed high

which resets all registers, sets serial output line high, sets

end of character line high, and sets transmitter buffer
empty line high.

TBMT
|

Transmitter

Goes high when the transmitter Data Holding Register may

Buffer Empty

be loaded with another character.

Data Strobe

Pulsed low to load the data bits into the transmitter Data

Holding Register during the positive-going trailing edge of

‘the pulse.
24

EOC

End of Character

Goes high each time a full character, including stop bits, is
transmitted. It remains high until transmission of the next

character starts. This is defined as the mark (high) to space

(low) transition of the start bit. This line remains high when
no data is being transmitted. When full speed transmission
occurs, this lead goes high for 1/16 bit time at the end of

each character.

B-20

Table B-8 (Cont)
UART Signal Functions

Pin No.

| Mnemonic

Name

Serial Output

Function

Output for transmitted character in serial asynchronous

format. A mark is high and a space is low. Remains high

when no data is being transmitted.
26-33

DB1-DBS8

Data Input

Eight parallel Data In lines. DB8 (pin 33) is the MSB and

DB1 (pin 26) is the LSB. If 5, 6, or 7 bit characters are
selected, the least significant bits are used.

Control Strobe

When high, places the control bits (POE, NP, SB, NB1 and

- NB2) into the control bits Holding Register.

No Parity

When high, eliminates the parity bit from the transmitted
and received character and drives the received parity error

(PER) line low. As a result, the receiver does not check
parity on reception and during transmission the stop bits

immediately follow the last data bit.
36

2SB

Two Stop Bits

Selects the number of stop bits that immediately follow the
parity bit. A low inserts 1 stop bit and a high inserts 2 stop

bits.

37,38

NB2, NB1

~ Number of Bits

Select 5, 6, 7, or 8 data bits per character as follows.

per Character

(Excluding Parity)

POE

Even Parity Select

Bits/

NB2

NB1

Char

(37)

(38)

Selects the type of parity to be added during transmission
and checked during reception. A low selects odd parity and
a high selects even parity.

TCP

Transmitter Clock

Input for an external clock whose frequency must be 16
times the desire transmitter Baud rate.

B-21

B.5 1488 QUAD LINE DRIVER

12 0—

2 O—

a B EEEENER

(TOP VIEW)

13 O—
.

4 O—

50—

E R EEEEEE

1C-0037

v+v .

9 O—

V- -

O 1

10 O—

v+ 14
0—

IC-0020

382K

$6.2K

INPUT 4 O—i¢—¢
INPUT 50—j¢—9

370

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300

AMA—O0
6 OUTPUT

y ¥
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GND 7°"__L

$3.6K
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310K

|
V-

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> 7K

270

NOTE:

1/4 of circuit shown.
1C-0067

B-22

B.6

1489L QUAD LINE RECEIVER

40—

(TOP VIEW)
B

‘

>_0 6

O-—J

)

O 14

V+ <

.1......
1C-0037

oo
IC-0021

-0 14 v¥

S 9K

RESPONSE

CONTROL

$5K

———03 OUTPUT

g2k

[

‘
~

INPUT 1 O—AMA
aK

y¥

$10K
P

O 7

GROUND

NOTE:

1/4 of circuit shown.
1C-0068

B-23

B.7

18-11660 CRYSTAL OSCILLATOR

SPECIFICATIONS
Size

14-Pin, Dual In-Line Package
Output Waveform

Square to Drive TTL
Frequency Range

5.0 MHz to 26.0 MHz

Calibration @ 25° C
+50 PPM
Fan Out

5 TTI

Rise Time (0.5 V to 2.5 V)
15 ns max.

Fall Time (2.5 V t0o 0.5 V)
15 ns max.

0 Level

Less Than 0.5V
1 Level

Greater Than 2.5V
Typical Input

+5 Vdc + 0.5V @ 28 mA
Temperature Range
0° -70° C
Symmetry @ 1.5V

35 - 65%
Frequency vs Temperature

+50 PPM

B-24

B.8

3106 256-BIT RANDOM ACCESS MEMORY

output is in the high-impedance state. When a num-

(RAM)

ber of outputs are bus-connected,
this high-imped-

The 3106 is a high-speed, fully-decoded, status bipo-

ance output state will neither load nor drive the bus

lar 256-bit open collector RAM in a 256 X 1 con-

line, but it will allow the bus line to be driven by

figuration. The 3106 is provided with a tri-state

another active output or a passive pull-up if desired.

output which allows up to 80 devices to be connected
to a common bus line.

Read Cycle - The stored information (complement of
information applied at the data input during the write

Write Cycle - The complement of the information at

cycle) is available at the output when the enable

the data input is written into the selected location

inputs are low. When any one of the memory enable

when

inputs is high, the output will be in the high-imped-

all memory-enable inputs

and write-enable

input are low. While the write-enable input is low, the

ance state.

FUNCTION TABLE
Inputs

Function

Memory

Outputs

Write

Enable+ | Enable

Write

High Impedance

Read

Stored Data

Inhibit

High Impedance

(Store Complement of Data)

H = High Level, L = Low Level
X = Irrelevant, ¥ = For Memory Enable

L = All ME Inputs Low
H = One or More ME Inputs High

B-25

MEMORY | ME!
ENABLEC
INPUTS

ME2

ME 3

(5)

WRITE (12)

FROOOE T

ENABLE —c>
WE

paTA (13)

INPUT '

[

(1)

B (2)

10F8
DECODER

O-

ADDRESSJ

(7)

o
O-

E()

(10)

1 OF 320

o
.,
o,
.

o,
DECODER [oO~

O-

0~
o

ADDRESS
INPUTS

Vee

DATA WRITE

H(14)

o
.

bui&dufljxl)fl t)nJ)uJ)nnAJnsAn L A A LA AL

—

(15)

INPUTS

(6) outPUT

256 -BIT MEMORY
MATRIX ORGANIZED
32-BY-8

ADDRESS
INPUTS

H INPUT ENABLE 6

schematics of inputs and outputs
EQUIVALENT OF EACH

INPUT

OUTPUT

-—

3
O NOM
58

Vee

Vee
6k
INPUT
il

2]]13(laflsfle]]7]]s

_B)

ADDRESS
I NPUTS

positive logic:

ME1T

ME2

ME3

OUT-

PUT

NOM
—

OUTPUT

GND

ADDRESS
INPUT

Data out is complement of
data which was applied at

data input. See description
and function table.
IC-0133

B-26

B.9

3341 4-BIT X 64-WORD PROPAGABLE

When data has been transferred to the bottom of the

memory, OUTPUT READY goes high indicating the

The 3341 is a 64-word X 4-bit memory that operates

presence

in a first in /first out (FI/FO) mode. Inputs and out-

READY and SHIFT OUT are high, data is shifted

puts

are

completely

independent

(no

common

of valid

data.

When

both

OUTPUT

out of the silo. This causes OUTPUT READY to go

clocks). When both INPUT READY and SHIFT IN

low.

‘are high, the four bits on D0-D3 are loaded into the

READY and SHIFT OUT are low. At this time, the

first

stay until INPUT

bits in the adjacent upstream cell are transferred into

READY and SHIFT IN go low. This causes the bits

the last cell causing OUTPUT READY to go high

bit

position

where they

to propagate to the second bit position (if empty)

again.

where they are propagated to the bottom of the silo

Data

is maintained until

If the

silo

has

been

READY will stay low.

both OUTPUT

emptied,

OUTPUT

by internal control signals.

LOGIC

——>4

__.5

INPUT

64 WORD x 4 BIT

JFiE0

MAIN REGISTER

Do —GD STAGE
D3

BLOCK DIAGRAM

STAGE i1

5 o our

INPUT READY <

[

Vgg=PIN 16

VDD=P|N

MASTER

RESET

Vgg=PIN 1

READY

ouT

3 —{sHiFT N

Ve []1

’

INPUT READY [| 2

ORF ROy — 14

SHIFT IN[] 3

0o []4

3341
4 — Do

CONFIGURATION

(TOP. VIEW)

LOGIC SYMBOL

Qo — 13

S5 — Dy

QrH—12

6 — Do

Qo p— 11

7 —Ds3

Qz — 10

16 [] Vss
15[

] SHIFT ouT

14 ] OUTPUT READY

13[] Qg

12 ] Q4

Do[]e

11[] Q2

D3 []7

10[7] Q3

VDD/

9] MR

MASTER RESET

Ts
Vgg =PIN 16 +5V

VpD= PIN 8 GND
1C-0163

B-27

B.10

4007 DUAL-BINARY TO ONE OF

FOUR-LINE DECODER

LOW-LEVEL GATE
OVcc .

S
-

o O

1C-0064

HIGH-LEVEL

34K

Stk

GATE

100

TGO O

1C-0063

D—-o 4 (12) QO

ENABLE

X (10)
6¢

V (9)7¢
= PIN
Vee

b
fi

3 (13) Q¢

2 (14) Q2

Do—u (15) Q3

D—
1/2 of device shown

GND:=PIN 8

1C-0062

B-28

B.11

4015 QUAD TYPE D FLIP-FLOP
LOW

LEVEL GATE

OVCC
<l

34K

34K
—0

L(_‘
SET 3

CLK

——

o—4

o
Q

R3 (1)

22K

Y¥

+ Diodes only on

+inpuis connected
to external

CLR 3
SET2

points

i
j,

R2 (1)

HIGH

LEVEL

GATE

OVec

24K
SET 1

$1.2K

100

(1)

fi*

e H

o———¢

SETO

/ $:
Q

5003
T

RO (1)

¥ Diode only on

input connected

to external point

1C-0060

13
3 CLOCK

3
9 CLR

BIED

R3 (1)
=

Vec=PIN

COMMON TO ALL FOUR

[}

Jrof

1C-0061

1/4 OF DEVICE SHOWN

AND RESET

{+4]

HgBpBptipgBpOpiigBD

ISET 3
4

CLOCK

15|

FLIP-FLOPS

GND=PIN 8
IC-0059

B-29

B.12

5603 PROGRAMMABLE READ-ONLY

MEMORY (ROM)

The IM5603 is a 1024-bit, bipolar programmable
ROM, organized into 256 words of 4 bits each. The

IM5603 is pin-compatible with the SN74187N mas-

Vee A:o:::c;:on:mg:m; 0s

ked read-only, and when properly programmed, may

F;I I';;l F;l m 11—2] m m r-l

be used interchangeably with the masked ROM
wherever the slightly slower access time of the PROM
is acceptable. The IM5603 has open collector out-

puts. To read the memory, both chip enable inputs

)

are held low. The outputs then correspond to the data

programmed in the selected word. When either or

both of the
chip enable inputs are high, all outputs
.

L_IL_I l__l
L__”_I
l_”_l
l_l
A
A
A
A
A,
GND

BLOCK

are floating.

DIAGRAM

a0 o—
5

al o—
6

0z 7g

ABDL?!BFEE?RS

1024 BIT

Jeggosei

(32 x 32)
MEMORY CELLS

a3 o—
4

a4 o—

55—
a6

ADDRESS

S BUFFER

|—

108

DECODER

a715

cs1<;-3—

CE 2 o—
14

}—|
||

DEcobER

10F8

DEcCoDER }—
]

CHIP

ENABLE

10r8

10Fs

DECODER

OUTPUT

BUFFER

VCC =16

GND =8

112

IC-0132

B-30

B.13

7442 4-LINE TO 10-LINE DECODERS

INPUTS

OUTPUTS

Vee

16|

[15]

[14]

[13]

[|12]

l_\ —

—

O 1 2 3 4 5 6 7 8 9
HDaBmBpid
0

GND

OUTPUTS

|
IC-0055

(1)

INPUT

(15)

OUTPUT O

5
A

)

INPUT B

OUTPUT
1

B
(14)

(2)

(3)

C
D

OUTPUT 2

+—2B
T

(4)

OUTPUT 3

A
Bl

(5)

OUTPUT 4

D
A
»
INPUT C

(13)

_
¢

—

OOUTPUT

B
C

(6)

(7)

OUTPUT 6

INPUT D O—Dc
(12)

B
C

D
A
C

Vee=PIN 16

(9)

GND=PIN 8

.
|

Do_ fg
=

(10)

'
OUTPUT 7

OUTPUT 8

(1) SuTPUT o

D
IC-0016

B-31

7450 DUAL 2-INPUT AND-OR-INVERT

O V¢c

$1.6K

-INPUTS{

34K
" '\

B.14

130K

C
OUTPUTY
D

—O GND
NOTES:

1. Component values shown are nominal.
2. Both expander inputs are used simultaneously
for expanding.
3. If expander is not used leave x and
X pins open.
4. A total of four expander gates can be connected

to the expander inputs.

1C-0075

Vee

1Y
8

GND

POSITIVE LOGIC: Y=(AB)+(CD)
+ (X)

1C-0076

B-32

,/"‘"\\

B.15 | 7489 64-BIT READ/WRITE MEMORY
Function Table
ME

Operation

Write

Complement of Data Inputs

Read

Complement of Selected Word

Inhibit Storage

Complement of Data Inputs

Do Nothing

High

dspdald

—

SELECT
INPUT
A

sS4

D3
s3}—

Condition of Outputs

RERER
2

MEM WRITE
DATA SENSE DATA SENSE
Y
” INPUT OUTPUT INPUT OUTPUT
ENABLES
1
1
2
2

GND

IC-0007

B-33

7492 FREQUENCY DIVIDER

L J”

p~J|

DUAL-IN-LINE PACKAGE (TOP VIEW)

—O

B.16

{

|NBPCUT

Vgc

Ro(1)

Ro(2)

1C-0087

B-34

B.17

7493 4-BIT BINARY COUNTER

TOGGLE

INPUT

PULSE

OuTPUT
2]

olo]lol]o

11o0lo]o

111]o0fo

olo|1]o

1{o]1|o

o|l1|[1]o0

1]l1]1]o

ojo]|

11of[o]1

11|01

—qT
K

—gT
O

—QIT
O

—qT
0

1|1

A2
RESET
ZERO

LOGIC DIAGRAM
14

GND

1
I
RESET

*TRUTH TABLE

* Applies When 7493 Is Used As 4-Bit
Ripple-Through

v3 ] va

ZERO

Vec

L JLJJeJJL

Counter.

LOCATOR

(TOP VIEW OF IC)

B-35

IC-0100

B.18 74121 MONOSTABLE MULTIVIBRATOR

(

TRUTH TABLE
tn INPUT |t,,4

INPUT

Atla2]| 8 |a1]|a2]| B

OUTPUT

olx|1]lolx]|o]|

TSI

iNnHIBIT

x|lo|l1]x|lolo]|

INHIBIT

o|{x|olo]|x]|1]|oNE sSHOT

TIMING PINS

Vee

NC -

ol Lo e | e

‘

__|

t{1]11o]|x]|1]|o0ONE SHOT

INmIBIT

olx|ol1|xlo]|

INHIBIT

x{oft|1[1]1]

INHIBIT

ofx

1]4]

INHIBIT

1{1|lolx|olo]|

INHIBIT

1]11]o]lolx|o|

iNHIBIT

1=Vin(1) 2 2V

t11|1|x]o]|1]|ONE sHOT

|1+

ol [ ‘ e

x|olo]lx|o|1]|ONE SHOT

x|lololx|1{o]|

0= Vin (0) < 0.8V

GND

<
)

1. th = Time before input transition.
2. th+1=Time after transition.

3. X'indicates that either a logical O or1 may be present.
1C-0081

B-36

B.19

74123 MONOSTABLE MULTIVIBRATOR

OUTPUT PULSE WIDTH
Vs

EXTERNAL TIMING CAPACITANCE

Ta=25°C

4 000
¢

2 000

£ 4000
700

;

‘

iy’

<y’

'60*9\ ! ”,//— A

Y S

LT[

—.

“any’

eSS

]

40
20

20 40

100200400 1000

Cext-External Timing Capacitance-pF
IC-0003

Vec
16

1 Rexts

Cext

CLEAR

|cLEAR

D 1

i C

—1Q

|CLEAR

CLEAR

——J

Cext

2 Rgyty GND

Cext

FUNCTIONAL LOGIC/PIN LOCATOR

TRUTH TABLE
INPUTS

NOTE:

| OUTPUTS

(oo

I sT

| L

H=high level (steady state), L= low level (steady state),

% = transition from low to high level, #=transition from
high to low level,

low-level pulse,

_I'L_= one high-level pulse, ~LI
= one
X= irrelevant (any input, including transitions).
IC-0156

B-37

74150 DATA SELECTOR/MULTIPLEXER

STROBE 4
ENABLE TM

Ep
©

Eqj0—

O
Ep

E3c

E4C

Eg 0—

O
Eg

DATA

INPUTS

[

E7G

OUTPUT
w

Eg 0—

Egc

Ei1p0—

Ejq0

E12 O

DATA

SELECT <
(BINARY)

B.20

IC-0005

B-38

B.20 74150 DATA SELECTOR/MULTIPLEXER

(Cont)

DUAL-IN-LINE PACKAGE
<

(TOP VIEW)
DATA SELECT

DATA INPUTS

|
Vv¢

2423}

2142019

1615

Eyy

Ei2

Eg FE5‘ Eq

Eo2

GND

6er7

)

DATA INPUTS

STROBE W
OUT

DATA

PUT SELECT

POSITIVE LOGIC

g+ ABCDE7
W=S|(ABCDEQ + ABCDE4 + ABCDEp +ABCDE3 + ABCDE4 + ABCDE 5+ ABCDE

(

+ABCDEg +ABCDE g + ABCDE+ABCDEY; + ABCDE 12+ ABCDE{3+ABCDE}4 + ABCDE1 5)

B-39

1C-0117

74151 DATA SELECTOR/MULTIPLEXER

STROBE G

4>-

)

[

)

*—

DATA_
INPUTS

OUTPUTS
Y

I |

—
|

D5
.

o—t—t
*—

——

[ S—

INPUTSY ©
\.

>°'**‘>°'

CONTROL

LOGIC DIAGRAM

|STROBE|ouTPUT

LOwW | LOW | LOW | Low
HIGH

LOW

LOW |

LOW | HIGH

LOW |

LOW

| HIGH |

LOW |

Low

HIGH

LOw

LOW | LOW

| HIGH | LOW

HIGH

| LOW

| HIGH |

Low

LOW | HIGH

| HIGH |

LOW

HIGH

| HIGH

DON'T

CARE
TRUTH

| Low |

V¢

GND

CONTROL INPUTS

EEEEEEER

B.21

L JLJLJLrJr
J0LJL ]
1

HIGH | HIGH

PIN LOCATOR

(TOP VIEW OF IC)

TABLE
1C-0097

B-40

B.22

74153 DUAL 4-TO-1 DATA SELECTOR

STROBE
16

(ENABLE) o

]

4 1cO (6)

:>—

1c1 (5)

*—

1C2 (4)

DATA 1+

1C3 (3)

. O-

B(2)

(7)

—*3_ ‘

1Y ]

;

ADDRESS{

(14)

oO—

- OUTPUTS

’_4>

[ 2c0(10)

:)_—

J2C1 ()
DATAZT

*—
c

2C2 (12)

(9)

- O

2C3 (13)

STROBE
26 _(15)

(ENABLE)

Vec =PIN 16

GND=PIN

LOGIC DIAGRAM

CONTROL

INPUT | STROBE | OUTPUT

LOW

HIGH | LOW

LOW

HIGH

| HIGH

HIGH

DON'T CARE
|

LOW

HIGH

LOW

TRUTH TABLE (EACH HALF)

STROBE

Vee

SELECT

DATA INPUT

16
r—'l

15
l_l

14
r—"l

13
[——I

{2
r—-l

Vee

203

202

‘G

OUTPUT

1
I'——I

10
l__]

9
|—|

201

GND

)

SELECT

STROBE

A
3

1cg

I
5

DATA INPUT

A
6

QUTPUT GND
ly

IC-0096

B-41

B.23

74154 4-TO-26 DECODER-

DEMULTIPLEXER

—_—

BI—

;

’

*—

L
3

*—

*r—

INPUTS 4 B ——Do—o—4>

*—

—
.

C —Do—-«r4{> C

|
-OUTPUTS

—

-—{>0—<?—4>D
|

*—

—

—o0

—_

13|

o—1

J
IC-0015

B-42

B.23

74154 4-T0O-26 DECODER-

DEMULTIPLEXER (Cont)

DUAL-IN-LINE PACKAGE (TOP VIEW)
INPUTS

OUTPUTS

VCC

24—

2322

2120

15114

T1ITL]

12}

11 p—

—Qq 0
1

OUTPUTS
1C-0044

B-43

B.24

74155 3-LINE TO 8-LINE DECODER

3-Line To 8-Line Decoder
Inputs

Select

Strobe 4

Outputs

(O)

2Y1

2Y2

2Y3

1Y0

1Y1

1Y2

1Y3
H

or Data

2Y0

- H

Signal/Pin Designation
Signal Name

Pin Designation

STROBE 1G

STROBE 2G

SELECT A

SELECT B

DATA 1C

DATA 2C

OUTPUT 1YO0

OUTPUT 1Y1

OUTPUT 1Y2

OUTPUT 1Y3

OUTPUT 2YO

OUTPUT 2Y1

OUTPUT 2Y2

OUTPUT 2Y3

B-44

B.24

74155 3-LINE TO 8-LINE DECODER (Cont)

~—FREE-- -S4
A

2¢C

ENABLE/DATA

STROBE 16 o—

ADDRESS SELECT

DATA 1C

ENABLE /DATA

:::::*F______OOUTPUT
1Y0

OUTPUT

1Y1

OUTPUT
1Y2

SELECT Bo———[:>x>——<»——c[:>>
|

OUTPUT

1Y3

OUTPUT

SELECT A w—Do—»—c{>

2Y0

OUTPUT
2Y1

DATA 2C
o

STROBE 26 o

OUTPUT
2Y2

cr““\

-0

OUTPUT
2Y3

11-1866

B-45

74157 2-TO-1 MULTIPLEXER

TRUTH TABLE
INPUTS

OUTPUT

ENABLE | SELECT |
H
X
L
L
L
L
H
L
L
H

A B
X X
L X
H X
XL

74157
L
L
H
L

74S158
H
H
L
H

X H

H=High level,L=Low level,X=Irrelevant

74157
1A
O

LOGIC

DIAGRAM

(2)
(4)
(3)

G(‘11)

C(‘IO)

(7)

(6)

‘\\‘\

14
C()

(12)
48

C}(13)

B.25

SELECT
ENABLE

(1)

Pin 16 = Ve, Pin 8= GND

1C-0086

B-46

B.26

74161 4-BIT BINARY COUNTER

Lo d'

Count Enable

Mode

(CEP - CET)

Count Up

No Change

Parallel Load

H= high level, L = low level, X = irrelevant
o

(9)

LOAD

(1)

CLEAR

VQA

CLOCK

(3)

DATA

(14)

(13

=P
(4
DATA o)

INPUTS
.

(12)

Jourputs

Q
CLOCK

(5)

(2)

9
ENABLE

CLOCK

(7)

DATA

(6)

10
ENABLE&Pl,

VL—

' —ceP

—CET

COUNT

[———CLOCK

(15)

)

Pin (16)=Vec(8)=
,Pin
GND

CARRY

__}————csp
—J CET

CEP

CARRY

J———CLOCK

CET

[——“CLOCK

—

RipPLE

~ CARRY

CARRY

[———CEP
CET

CARRY

J———CLOCK

11-1868

B-47

74174 HEX D-TYPE FLIP-FLOP

B.27

TRUTH TABLE
INPUT
tn

|OUTPUTS
Wl

H
L

L
H

tn = Bit time before

clock pulse.

tn+1=Bit time after

(2)

A
|

Da Qa[=—°0Qa
—

_OICLOCK
CLEAR

B c(j)

Qg —@OQB

clock pulse. -

Ol CLOCK

CLEAR

c &8

o qc

—-OICLOCK
CLEAR
¢

(10)

Dp Qp[—°Qp
—QICLOCK

CLEAR

E C( 3)

10 Qg '(-"'")0 Qe
alcLock

CLEAR

|
14

F c( )
(9)

CLOCK o———

)

T
DF . QF 0 QF
(15)

ocLock

—

CLEAR

CLEAR m(LC{>o—l—-4>———T
Pin (16)= Vcc, Pin(8)=GND

IC-0047

B-48

B.28

74175 QUAD D-TYPE FLIP-FLOP

TRUTH TABLE
INPUT | OUTPUTS

H
L

L
H

tnh =Bit time before
clock puise.

th+1=Bit time after

P ,‘-\\

clock pulse.

Q—TM

CLK E)A —O
CLEAR

(5)

Qg—>

QCLK 63 —O
CLEAR

(12)

Qcp——o

QCLK Q¢ }—o
CLEAR

c>“3)

(9)

CLOCK o—

Qp—>

QlCLK Qpf—o

—_J
CLEAR

CLEAR

(1)

Pin (16)= V¢, Pin (8)=GND

IC-0018

B-49

3 -IN o

74181 ARITHMETIC LOGIC UNIT (ALU)

hr—

v V T m()m
A3

LKAk

B.29

B-50

[

IDe
-

B.29

74181 ARITHMETIC LOGIC UNIT (ALU)

(Cont)

-k

DUAL-IN-LINE PACKAGE

(TOP VIEW)

INPUTS

Voo - Al

m»

OUTPUTS

242322}

{20}

19}

{1s

Cn+q

Cpuq

A=B

H 1sp{

A=B

—|BoO

F3p—
S3

Ss2

H:sH-HsHe

7ra

H1oH11

Cn M - FO

1
BO

S2 St
INPUTS

Fi Fz GND
OUTPUTS
IC- 0161

/x"

EE)

B-51

B.30

74193 SYNCHRONOUS 4-BIT UP/DOWN

COUNTER

BORROW
OUTPUT

CARRY
OUTPUT

DATA

INPUT A O

counNT ©

>°

count ©

:::>°

PRESET

CLEAR

’

OUTPUT Q,

oY U

DATA

INPUT B ©

J) |
PRESET

OUTPUT
Qg

-O

OUTPUT
Q¢

©O

OUTPUT Qp

o T

Qg
CLEAR

O
DATA

INPUT ¢ @

é)
PRESET

Qc
QT

Qg
Y

CLEAR

T )pt==7

DATA

INPUT D ©

CLEAR O—le

>_
PRESET

0 >

ofr

CLEAR

LOAD o———o[::>
IC-0002

B-52

B.30

74193 SYNCHRONOUS 4-BIT UP/DOWN

COUNTER (Cont)

OR N DUAL-IN-LINE PACKAGE (TOP VIEW)
INPUTS

»
OUTPUTS

v..
cc

DATA
A

DATA
C

DATA
D

CLEAR ~——A—— LOAD
- BORROW CARRY
14

CLEAR
CARRY
BORROW
LOAD

COUNTCOUNT

DOWN

Q¢

,’/./

INPUTS
.

1
DATA'
INPUT

elH3sHHsHHs
78
He
Qg

OUTPUTS

COUNT COUNT
DOWN

INPUTS

GND

OUTPUTS

LOGIC: LOW INPUT TO LOAD SETS Qp=A,Qg=B,Qc=C,AND Qp=D

1C-0047

B-53

B.31

74197 50 MHz BINARY

COUNTER/LATCH

)

‘

DATA A

COUNT/LOAD-

CLEAR

CLOCK | —

DATA B

Q¢

CLOCK 2 —

DATA C

} |

TRUTH TABLE

COUNT

0
|

OUTPUT

| Qpl|

Qc|Qg|

olojofo

ojlofo]1
olo|11}0

o101

of1}]o]o

DATA D

[11]o
| 1]

ijolofo

1{of1]o

o|o]|1

1
}1
t|1]0]0

13
14

1
[1]0]|1
t]1]1|o

I T

Qpconnected to CLOCK 2 input.

IC-0112

PIN LOCATOR

)

8
9
10
11
1r1r3rirg

13
14
(1A

Vec¢

CLEAR

DATA

CLOCK

COUNT/

DATA

CLOCK

GND

LOAD

L
1

JJoJeJL bt
2

7
1C-0113

B-54

//’m'

CLOCK
1 INPUT

8242 4-BIT DIGITAL COMPARATOR

B3
TRUTH

TABLE

rjimw

B.32

H{H|H
FUNCTIONAL
-

LOGIC

_DIAGRAM

(EACH GATE)
A

IC-0027

B-55

8266 2-INPUT 4-BIT DIGITAL MUX

- DATA lNPUTSJ
B2

» OUTPUTS

At
.

(
CONTROL INPUTS <

R
)

B.33

LOGIC DIAGRAM

CONTROL INPUT|OUTPUT
C

_l 11

LOW | HIGH

LOwW

Vee

LOW | Low
HIGH

HIGH | HIGH | HIGH

A1
|

TRUTH TABLE

B1
JL

Y1
L

Y2
L

B2
L

s
PIN

D
L

LOCATOR

GND
JT]

(TOP VIEW OF IC)
1C-0099

B-56

B.34

8271 4-BIT SHIFT REGISTER

D¢

- Dp

Rp
DSI

SHIFT >
—q

[TR

/s //.

SCD 1M—

LOAD

CLOCK—D
- LOGIC

DIAGRAM

1101
0M1
CONTROL

LOAD

SIGNAL

| REGISTER

SHIFT

| FUNCTION

LOW

HOLD

HIGH

Low

|PARALLEL

LOW

HIGH

SHIFT

HIGH

RIGHT

FUNCTION

Vee

D¢

SHIFT

LOAD

Y¢

Ya.

CLOCK

GND

TABLE:

[ JLJLJLJLJCJCT
2

(TOP

B-57

LOCATOR

VIEW OF IC)

1C-0098

B.35

DUAL BAUD RATE GENERATOR

(COMS5016)

frequency scheme from an internal crystal clock or

via an external input frequency. Address inputs may

The dual baud rate generator/programmable divider
(COMS5016)

N-channel

MOS/LSI

be strobed or DC loaded. Full duplex (independent

receive and transmit frequencies) operation is pos-

device

capable
of generating 32 externally selectable fre-

sible with the COM5016.

quencies from either an on-chip oscillator or an exter-

Utilization of one of the frequency outputs permits

- synchronous/asynchronous frequencies as shown
in

nal input frequency. The unit generates

generation of additional divisions of the master clock

Table B-9. Four address inputs select one
of 16 inde-

frequency by cascading COMS5016s. This may be

pendent receiver or transmitter frequencies (Figure
B-11).

accomplished by feeding frequency outputs into the

- XTAL/EXT input on a subsequent device.
The COMS5016 may be driven either by an external

The dual baud rate generator is essentially a pro-

crystal or TTL logic level inputs. COMS5016 pin

grammable 15-stage feedback register. An internal re- programmable ROM permits the generation of the

STT >

are described in Table B-10.

~ TB
T,

assignments are shown in Figure B-12; pin functions

D—LATCH

>—

FREQUENCY
<

REPROGRAMMABLE

AND

FREQUENCY SELECT

CONTROL

ROM

'DIVIDER

|—etfy

DIVIDER

|—sfq

XTAL/EXT: >——

OSCILLATOR

XTAL/EXT. >—

Rg >——

A D-LATCH '
R,

STR >—

BELAECEN

>—

anE |

m—

CONTROL

REPROGRAMMABLE

FREQUENCY

ROM

SELECT
|

I
Figure B-11

+5V

GND

’
+12V

11-4406

Block Diagram Dual Baud Rate Generator

B-58

1118 xTAL/EXT2

XTAL ZEXT 1 1]
+5v 2]
-

fr 3]

116 T,

R, 4]

115
Tg

Rg 5]

114 1

13 Tp

Rp 7]

|12 STT

STR 8]]

]11 GND

+2v 9]

110 NC

11-4405

Pin Assignments
Figure B-12 COMS5016

Table B-9

Dual Baud Rate Generator Address/Frequency Assignments
~ Theoretical

Actual

- Frequency

Frequency

Baud
Rate

16X Clock
kHz

Percent
Error

Cycle
- %

50
75
110
1345
150
300
600
1200
- 1800
2000
2400
3600
4800
7200
9600
19200

0.8
1.2
1.76
2.152

0.8
1.2
1.76
2.1523

—
—
—
0.016

50/50
50/50
50/50
50/50

Transmit/Receive

Address
D | C
B

—_

R, 00000000

0
10
0
0
1
1
1
1
0
0
0
0
1
1
1
1

{00
0
1
1
0
|1
1

0
0
0
1
1
|0
1
1
0
0
0
1
1
0
1
1
010
0
1
1
0
1
1

2.4
4.8
9.6
19.2
28.8
32.0
38.4
57.6
76.8
- 115.2
153.6
307.2

2.4
4.8
9.6
19.2
28.8
- 32.081
38.4
57.6
76.8
115.2
153.6
316.8

B-59

- Duty

—
—
—
—
—
0.253
—
—
—
—
—~
3.125

50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
48/52
50/50

Divisor

6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16

Table B-10
Dual Baud Rate Generator Pin Functions
Pin No.

Symbol

XTAL/EXT1
|

Name

Function

Crystal or External

This input is either one pin of the crystal package or

Input 1

one polarity of the external input.

Vcce

Power Supply

+5 V Supply

Receiver Output

This output runs at a frequency as selected by the

Frequency

Receiver Address.

RA, RB, Rc, RD

Receiver Address

|
8

STR

The logic level on these inputs, as shown in Table

B-9, selects the receiver output frequency, fR.

Strobe-Receiver

A high-level input strobe loads the receiver address

Address

(RA, RB, Rc, RD) into the receiver address register.
This input may be strobed or hard wired to a high-

level.

VDD

Power Supply

No Connectio'n

. GND

STT

| ~+12 V Supply |

Ground

" Ground

Strobe-Transmitter

A high-evel input strobe loads the transmitter address

Address

(TA,TB,Tc, TD) into the transmitter address register.
This input may be strobed or hard wired
to a highlevel.

13—16

Tp, Tc, T, TA

Transmitter Address

The logic level on these inputs, as shown in Table B-9,
selects the transmitter output frequency, fT.

XTAL/EXT?2

Transmitter Output

This output runs at a frequency as selected by the

Frequency

Transmitter Address.

Crystal or External

This inpfit is either the other pin of the cryStal

Input 2

package or the other polarity of the external input.

. B-60

()

APPENDIX C

SYNCHRONOUS SERIAL DATA HANDLING

This appendix contains a discussion of the principles

In serial transmission, the bits that represent a char-

of synchronous serial data transmission and recep-

acter are sent down a single wire one after the other.

tion, followed by descriptions of the synchronous
receivers and transmitters used in the DV11 Synchro-

Computers and other high-speed digital machines

nous Multiplexer.
C.1

generally operate on parallel data, so data is trans-

ferred in parallel between these devices wherever they

BINARY DATA TRANSFER METHODS

Bits of

binary

data

are

commonly

are in close physical proximity. However, as the dis-

transferred

tance between the devices increases, the multiple
wires not only become more costly, but the com-

between digital machines by changes in current or
voltage. Data may be transferred in serial over a
single line,
or in parallel over several lines at once.

plexity of the line dfivers and receivers increases, due

The transfers may be synchronous, in which the exact

receiving signals on long wires.

to the increased difficulty of properly driving and

departure or arrival time of each bit of information is
predictable, or they may be asynchronous, in which

Serial transmission is generally used where the cost of
the communication medium (wires) is sufficiently

case the data may be transferred at non-uniform

rates. Aspects and applications of these several data
transfer modes will now be discussed.
C.1.1

Parallel vs Serial

high that a relatively complex transmitter/receiver

system 1is justified. The more complex system will
serialize the bits that represent the character, send
them over a single line, and reassemble them
iin paral-

In parallel transmission, each bit of the set of bits that

lel form at the receptlon end.

represent a character has its own wire. An additional
T

wire called the ‘““strobe” or “‘clock” lead notifies the

Conversion from parallel-to-serial and from serial-to-

receiver unit that all of the bits are present on their

parallel is typically done with shift registers. In most

respective wires so that the voltages on the wires can

data communications applications, serial transmis-

be sampled. Figure C-1 schematically depicts the par-

sion is preferable to parallel transmission.

allel transfer of the 8-bit character 11000001.
3V

+3V

]

+3V

VAY

0oV

+3V

+?) v

Strobe

C.1.2

Asynchronous vs Synchronous

Because of the mechanism design in early serial tele-

printers, and to facilitate fail-safe operation, serial
teleprinter systems have adopted the convention that

an idle line (no data being sent) is one in which cur-

rent is flowing. Data transmission occurs when the

current in the line is interrupted in a specified fashion. By convention, the idle (current flowing) state is

+(3)

called the “I” state or “MARK” condition, and the
lack-of-current
“SPACE”

Figure C-1

state

condition.

is called
To

the

“0”

state,

start the receiving tele-

printer mechanism, the line is brought to the O state
for one bit time. (This is called the “START” bit.)

Parallel Data Transfer

C-1

For the next eight successive bit times, the line is conditioned to a 1 state or O state, as required, to represent the character being sent. To allow the receiving

teleprinter mechanism to coast back to a known posi-

tion in time for the beginning (START bit) of the
next character, one or more bit times of 1 state (idle)
are sent. ThlS perlod is called the “STOP” b1t
interval.

Except for the requirement that the line be idle for at

least the STOP bit interval, the transmission of the
next character can begin at any time. The lack of a

continuous

agreement between the

synchronous

transmitter and the receiver - specifically, the lack of
a clocking signal within or accompanying the data

channel - causes this type of transmission to be called

asynchronous, literally, “without synchronization.”

Although modern asynchronous receivers do not
require a stop interval for mechanism coasting purposes, they do not require a stop interval to guarantee
that each character will begin with a 1-to-0 transition,

even if the preceding character was all zero bits. This
requirement for a 1-to-0 transition, to indicate the
beginning of each character, causes a complete char-

~acter to require 10 bit times, only eight of which con-

tain real data. The other 20 percent of the line time is
used strictly for timing purposes.
The asynchronous
character format is shown in Figure C-2.
Synchronous communications require either a separate rate clock lead from the transmission point to the

reception point, in addition to the data lead, or a

modem that includes the clock information with the
data. In the case of a modem, the clock is recovered

from the signal sidebands by the modem and is

brought out of the modem as a separate lead; this
indicates to the data communications hardware (typi-

cally a computer interface) the appropriate instant to

A typical asynchronous receiver contains an internal
clock and a system for detecting the 1-to-0 transition
that indicates the beginning of a start bit. The internal clock delays one-half bit time, checks to see that
the start bit condition is still on the line and then
makes eight successive samples, one bit time apart, to
~determine the eight bits being sent.

sample the data on the “received data’ lead.
The inclusion of the clock in the data stream or
“besides” the data stream (separate lead) keeps the
transmitter and receiver in synchronism - hence, the
term synchronous communication. Synchronous

character format is shown in Figure C-3.

(LINE=1)

(LINE 0)
STOP

BITS

DATA

BITS

START

BIT

11-2233

Figure C-2

Asynchronous Character Format

(e I TIME
MODEM CLOCK

DATA

LSBI

|&———SYNC CHARACTER
|

I
11-2234

Figure C-3

Synchronous Character Format

C.1.3

Synchronizing at the Receiver

Typical synchronous receiver units are placed in a

Since start and stop bits are not required in synchro-

“sync search’ mode, by either hardware or software,

nous communications, all bits are used to transmit

whenever a transmission begins, or whenever a data

data; hence, there is not the 20 percent waste charac-

dropout has occurred and the hardware or software

‘teristic of asynchronous communication. However,

determines that resynchronization is necessary.

the character “framing” information provided by the
start and stop bits is absent, so another method of

Synchronization is accomplished by the hardware

determining which groups of bits constitute a charac-

shifting eight bits into a shift register, and comparing

ter must be provided.

those eight bits (as a parallel word) to the sync character which has been set in a register. If a match

In Figure C-4, bits 1-8 might be one character and

occurs, the receiver begins shifting in bits and raising

bits 9-13 part of another character, or bit 1 may be

a “Character Available” flag every eight bits. If no

part of one character, bits 2-9 part of a second char-

match is realized, the receiver shifts in a new bit from

acter, and bits 10-13 part of a third character, etc.

the line, shifts all bits recorded to date (thus shifting

The delimiting or framing of each actual character is

the “oldest’ bit off the end), and does a new parallel

accomplished by defining a ‘‘sync” character. The

comparison to the sync character. The process con-

sync character is usually chosen such that its bit

tinues until the sync character is framed.

arrangement is significantly different from that of

any of the regular characters being transmitted. Thus,

To decrease the probability that a receiver will syn-

when a sync character is preceded and followed by

chronize on a bit combination that is not the intended

tern of bits that equal the bit patterns of the sync

characters,

synchronous

character, except those eight bits that actually are the

arranged

synchronize

sync character.

characters.

regular characters, there is no possible successive pat-

sync character, but rather a combination of other
to

S 11-2931

Serial Bit Stream

C-3

are

successive

two

frequently
sync

|1|2,345678910111213

Figure C-4

receivers

APPENDIX D

PROTOCOLS FOR BINARY

SYNCHRONOUS COMMUNICATIONS

A protocol
is a set of rules which govern the sequenc-

ing, identification, and synchronization of data interchanged

between

data

terminals.

This

appendix

data terminal is capable of transmitting a fixed number of bits per second in each direction; the control
bits reduce the effective rate of information transfer.

describes the features of two popular protocols to
enable the user to select and plan for the implementa-

The ratio of the information bits to the total bits

“tion of the protocol best suited to his needs. This
appendix also provides the necessary background

The more control, header and error-checking charac-

‘data for understanding the data exchange require-

determines the one-way line utilization efficiency.
ters needed by a protocol, the less efficient the line.

ments which the DV11 was spemfically designed to

D.1.3

accommodate

Acknowledgement handling can affect line utilization

Acknowledgement Handling

- 1n two ways. First, if the acknowledgement is a sepa-

D.1

DATA CHANNEL UTILIZATION

The DV11 interchanges serial, synchronous, bytes or
characters with remote terminals via data channels or

lines. The maximum efficiency with which a channel
may be utilized is determined by the structure of the

protocol being used. Four factors inherent in any
protocol affect data channel utilization efficiency:

direction utilization

rate message, then both the acknowledgement and
the gaps between the acknowledgement and the data

blocks are part of Control Overhead. Second, more
overhead occurs if each message requires a separate
acknowledgement. Acknowledgements within blocks
containing

information

reduce the first overhead

because it usually takes fewer or no additional characters for normal conditions; only errors are
indicated by separate blocks. If the protocol defines a

control overhead

way

acknowledgement handling

response, the number of overhead bits is further

number of data terminals or stations per line.

reduced.

acknowledge

multiple

blocks

with

one

D.1.1 Divrection Utilization

A data channel between two ..iminals may physically

D.1.4

permit one-way or two-way transmission, called sim-

When the activity from one station on a lineis below

plex
or duplex operation, respectively. The two-way
transmission may alternate in direction of transmis-

sion, called half-duplex, or may provide simultaneous

two-way transmission, called full-duplex. Most phys-

- ical facilities are full-duplex, however, the protocol
being used may not take advantage of the physical
facility. It may be a half-duplex protocol (alternate
data transmissions), although the physical facilityis

full-duplex. To make the most efficient use of a fullduplex facility, a full- duplex protocolis requlred
D.1.2-

Control Overhead

Data transferred between terminals is comprised of
information, control and error-checking bits. All but

the information bits are Control Overhead bits. A

Stations Per Line

full utilization, the extra capacity can be utilized by

- putting additional stations on the line. This is similar
to telephone party lines and is called “multipoint” or
“multidrop.” When only two stations are involved, it
is called “‘point-to-point.” Most protocols support
both point-to-point and multipoint arrangements.

For multipoint operation, one station in the network
is designated as the Control Station. The remaining

- stations are designated as Tributary Stations. The
Control Station initiates data transfers by “polling”
and “‘selection” of Tributary Stations. Polling is an
invitation to send data, transmitted from a Control

Station
to a Tributary Station. Selection is a request
to receive data, to be sent from the Control Station to

the Tributary Station.

D.2

in that some printing characters are replaced by non-

DATA AND CONTROL CODES

The purpose of a data channel is to transfer data,

printing control characters and the parity is specified

unaltered, from a transmitter station (master) to a

to be odd. This code is readily adaptable to com-

receiver station (slave). The data to be transferred is

puter-to-computer communications.

embedded in control codes, which serve to identify

the type of data being transferred, and to provide for

Of the other existing codes, the most widely used are

synchronization and error detection. (Thus, the chan-

the Extended Binary Coded Decimal Interchange

nel is considered to consist of the physical facility

Code (EBCDIC), the 5-bit Baudot code, found in old

plus control codes. For this reason, the control codes may be referred to as Data Channel or Data Link
control codes.) Since both stations are operated in
accordance with the same protocol, the receiver station is able to differentiate between the several types
of control codes and data codes sent by the trans-

teleprinter equipment, the Four of Eight Code, the

IBM punched-card Hollerith code, the Binary Coded

Decimal (BCD) code, and the 6-bit Transcode.

EBCDIC is an eight-level code similar to ASCII,

except that while ASCII uses its eighth level for parity
bits, EBCDIC uses it for information bits, thereby

mitter, and can therefore act accordingly.

extending the range of characters to 256.

D.2.1

Types of Data

In the protocols to be described, all data are classed

D.2.2

‘into two types or categories: Transparent Data, or

Preceding

Character-Encoded Data.

binary

the data and control character is a
sequence of one or more synchronizing (SYN or

SYNC) characters, which have a protocol-defined bit

D.2.1.1 Transparént Data - It is often necessary to
transmit

Synchronization Codes

data,

floating-point

numbers,

pattern. The synchronization characters are used by
the receiver to synchronize, or get in phase with, the
characters in the continuous stream of bits, to deter-

packed-decimal data, unique specialized codes, or

mine where each character begins and ends. (This is

machine-language computer programs. In order to

the character- frammg process describedin Appendlx

do this, all data, including the normally restricted

C.)

Data-Link Control characters, are treated only as

specific bit patterns. Protocols differ in the methods

D.2.3

used to permit the use of all possible bit patterns as

The protocols to be described use error-detectlng

~data while still controlling the data channel. Tech-

codes provided for by the DV11: LRC, CRC-16, and

niques for achieving transparency are discussed sepa-

CRC-CCITT.

Error-Detectmg Codes

rately for each protocol described herein.
LRC is a Longitudinal Redundancy Check on the
Character Codes — Several character encod-

total data bits by message block (see Figure D-1). An

ing schemes are available. The codes differ primarily

LRC character is accumulated in both the sending
and receiving terminals during the transmission of a

D.2.1.2

in the number of bits used to represent characters and
the bit patterns which correspond to the characters.

block. This accumulation is called the Block Check

Characters are divided into graphic characters, repre-

- Character (BCC). The transmitted BCC is compared

senting a symbol, and control characters, which are

with the accumulated BCC at the receiving station for

used to control a terminal or computer function.

Although many codes are in use, the trend is toward

an equal condition. An equal comparison indicates a
good transmission of the previous block.

(American

Cyclic Redundancy Checking (CRC) is a more pow-

Standard Code for Information Interchange) code.

erful method of block checking than LRC.
A CRCis

the

universal 7-bit-plus-parity

ASCII

Standards

a division performed by both the transmitting and

Institute and has been accepted as the U.S. Federal

receiving stations, using the numeric binary value of
the message as a dividend, which is divided by a con-

ASCII was

introduced

by the U.S.A.

Standard. Techniques for transmitting transparent or
binary data also exist within the structure of the

- ASCII code. Special characters are set aside for Data

Channel control.

A variation of the ASCII code is the 8-bit Data Inter-

change_Code.. Primarily, this code differs from ASCII

stant.

performing

the division,

borrows

are

ignored. The quotient is discarded and the remainder
serves as the check character, which is then transmitted as the BCC. The receiving station compares
the transmitted remainder with its own computed
remainder, and finds no error if they are equal.

Polling and addressing on multipoint lines are han-

Bit Position

P6543210

Character 1

01111001

the header field. The text portion of the field is variable in length and may contain transparent data. If it

Character 2

0011000

is defined as transparent, it is delimited by DLE

Character 3

0O 000O0T1T11

or DLE ETB (End of Text Block) The blockis termi-

Character 4

0111

LRC-8 BCC

- Figure D-1

dled by a separate control message and not by using

(Data Line Escape) STX and DLE ET (End of Text),
nated by the BCC.

O000O0

00010110

Longitudinal Redundancy Checking

BSC protocol employs a rigorous set of rules for
establishing, maintaining, and terminating a commu-

nications sequence. A typical exchange between a

~data terminal and the DV11/PDP-11 on a point-topoint private line is illustrated in Figure D-2.
D.3.2

An infinite number of constants may be used to per-

Error Checking and Recovery

To detect and correct transmission errors, BSC uses

either VRC/LRC or CRC, depending upon the char-

form the CRC division. The DV11 makes available

acter code. If the code is ASCII, a VRC check is per-

two CRC computations: CRC-16 (which uses a polynomial of the form x!¢ + x!5 + x2 + 1), and CRC-

formed on each character and an LRC on the whole

CCITT (which uses a polynomial of the form x!¢ +

message. The LRC becomes one 8-bit BCC. If the

x'2 + x>+ 1). Each generates a 16-bit BCC.

code is EBCDIC, CRC-16 (x'¢ + x!5 + x? + 1) is
used, resultingin a 16-bit BCC.

D.3

BSC PROTOCOL (BISYNC)

One of the most widely used protocols is IBM’s Bina-

If the BCC transmitted does not agree with the BCC

ry Synchronous Communications (BSC). BSC, also

computed
by the receiver, or if there is a VRC error, a

known as BISYNC, has been in use since 1968 for

NAK sequence (shown in Figure D-3) is sent back to

transmission between IBM computers
and remote

the data source. BSC calls for the retransmission of

terminals of the batch and video display types.

the block when an error occurs.

BSC will typically

retry three times before concluding that the line is in

an unrecoverable state. BSC checks for sequence

LRC is the modulo 2 sum (exclusive-OR) of the bits
in each bit position of all characters in a message

errors by alternating positive acknowledgments to

block to produce a BCC. The figure shows the BCC

successive blocks. ACKO and ACK1 are the respon-

computation for four 8-bit characters using LRC.

ses to the even-numbered and odd-numbered blocks

Each character contains seven data bits and an odd-

in the message, respectively. These are sent in sepa—

parity bit.

rate control messages |

D.3.1

D.3.3

Controlling Data Transfers

Character Coding

BSC supports ASCII, EBCDIC, or 6-bit Transcode

The format of a BSC message is shown in Figure D-2.
BSC uses control characters to delimit the fields. The

Table D-1 lists and describes certain bit patterns in

header is optional; if it is used, it begins with SOH

~each set that have been set aside for the required BSC

- (Start of Header) and ends with STX (Start of Text).

control characters. Some BSC control codes are multi-character sequences.

The contents of the header are defined by the user.

SYN

SOH | HEADER

TEXT

STX

ETX

Bcc

11-2898

Figure D-2 BSC Data Message Format

D-3

TERMINAL

DV11/PDP-11

Terminal sends a message whose text

is a single control character: ENQ.

This means “I have some data to send
to you.”

@ DV11/PDP-11 receives ENQ. |
PDP-11 acknowledges terminal by responding

with a “Go Ahead” message (ACK 0).

Terminal Sends vBlock of Data.

DVl 1/PDP-11 receives block of data and
checks for data errors. If no error, jump

to 8.

If an error has occurred, PDP-11 sends a
control character (NAK or Negative
- ACKnowledgment) which means “Please

Terminal receives NAK and /|

retransmits last message.

Return to state 6.

retransmit last message.”

\ ‘:
PDP-11 responds with an acknowledgment

message (ACK) which says “I received that
OK — send me the next message.”

control character (EOT — for END-

OF-TRANSMISSION) which says
- “l am finished.”

DV11/PDP-11 receives EOT message and
goes into its closing sequence.

Figure D-3 Typical Data Exchange Using BSC (BISYNC)

control character to be recognized as a control func-

Table D-1

tion. When a bit pattern equivalent to DLE appears

BSC Data Channel Control Codes

within the transparent data, two DLEs are used to
permit transmission of DLE as data. When received,

Control
Code Mnemonic

Meaning

SYN

~ Synchronous Idle

SOH

Start of Heading

STX

Start of Text

ITB

one DLE is disregarded; the other is treated
as data.
-

This technique is called “character stuffing.”
~J

D.3.5

BSC transmission is half-duplex. The line must be
turned around rwice between each block (once for the
acknowledgment sequence and once for the data
block). All fields are delimited by control characters,

End of Intermediate Trans‘mission Block

Data Channel Utilization

and acknowledgments are handled by separate control
-

sequences.

acknowledgment

sequence

required for each block and for each acknowledg-

ETB

End of Transmission Block

ment sequence. A minimum of two character times is

ETX

-End of Text

both point-to-point and multipoint lines.

EOT

End of Transmission

D. 3 6

ENQ

Enquiry

ACKO/ACK1

‘Alternating Affirmative

~ WACK
NAK

Acknowledgments

required for each synchronization.

BSC supports

Synchromzatlon

BSC synchronizes on each block or- control sequence

by preceding the formatted block with the synchronizing (SYN) characters. Two synchronizing characters are required, but more (usually five) are sent.
'SYN is defined as a unique bit pattern in each of the

three information exchange codes available with
BSC. In addition, some BSC applications require that

Wait-Before-Transmit Positive

all 1s PAD characters follow messages.

Acknowledgments

D.4

Negative Acknowledgment

DDCMP PROTOCOL

DDCMP (Digital Data Communications Message

Protocol) was developed to provide full-duplex mes-

'‘DLE

- Data-Link Escape

RVI

Reverse Interrupt

TTD

Temporary Text Delay

The DDCMP message formatis shownin Flgure D-

Disconnect Sequence for a

message, and is the first character in the message.

DLE EOT
|

sage transfer over standard existing hardware.
D4.1 Controllmg Data Transfers

4. A single control character is used in a DDCMP
Three control characters are provided in DDCMP to

Switched Line

differentiate between the three p0331b1e types of
messages:

SOH - data message follows
D.3.4

Data Transparency

ENQ - control message follows

In BSC, the transparent mode is defined by starting

DLE - bootstrap message follows.

the text field with DLE STX. Once in transparency,
the only control character of significance is DLE.

Note that the use of a fixed-length header and mes-

Any Data Link control characters transmitted during

sage size declaration obviates the BSC requirement

the transparent mode must be preceded by a DLE

for extensive message and header delimiter codes.

D-5

SYN

|RESPONSE |SEQUENCE

COUNT | FLAG

SOH

14 BITS | 2BITS

| 8BITS | 8 BITS

ADDRESS | CRC-1

DATA

8BITS | 16 BITS | = (ANY NUMBER OF 8-8BIT

CHARACTERS UP TO 214)

CRC-2
16 BITS
-

11-2897

Figure D-4

DDCMP Data Message Format
16,383 bytes long. To validate the header and count

Figure D-5 shows a simple example of data exchange
between the DV11/PDP-11 and a data terminal.
More efficient procedures can be derlved after a

er characters are included in the CRC calculation.

study of DDCMP.

Once validated, the count is used to receive the data

field, it is followed by a 16-bit CRC-16 field; all head-

and to locate the second CRC-16, which is calculated
on the data field. Thus, character stuffing is avoided.
D.4.2

Error Checking and Recovery

DDCMP uses CRC-16 for detecting transmission

D.4.5

errors. When an error occurs, DDCMP sends a sepa-

DDCMP uses either full- or half-duplex circuits at

rate NAK message. DDCMP does not require an
acknowledgment message for all data messages. The

optimum efficiency. In the full-duplex mode,
DDCMP operates as two dependent one-way chan-

Data Channel Utilization

numberin the response field of a normal header or in

nels, each containing its own data stream. The only"

either the special NAK or ACK message, specifies

dependency are the acknowledgments which must be

the sequence

sent in the data stream in the opposite direction.

number

of the

last good

message

received. For example, if messages 4, 5, and 6 have
been received since the last time an acknowledgment

Separate ACK messages are unnecessary, reducing

was sent and message 6 is bad, the NAK message

the control overhead. Acknowledgments are simply

specifies number 5 which says “message 4 and 5 are

placed
in the response field of the next message for

good and 6 is bad.” When DDCMP operates in full-

the

duplex mode, the line does not have to be turned

received correctly before the terminal is able to send a -

around; the NAK is simply added to the sequence of

message, all of them can be acknowledged by one

messages for the transmitter.

opposite

direction.

several

messages

are

response. Only when a transmission error occurs or
when traffic in the opposite direction is light (no data

When

a sequence error occurs in DDCMP,

the

receiving station does not respond to the message.
‘The transmitting station detects, from the response

message to send) is it necessary to send a special

NAK or ACK message, respectively.

field of the messages it receives (or via timeout), that

In summary, DDCMP data channel utilization fea-

the receiving station is still looking for a certain mes-

tures include:

sage and sends it again. For example, if the next message the receiver expects to receive is 5, but 6 is

received, the receiver will not change the response

The ability to run on full- or half-duplex
data channel facilities.

field of its data messages, which contains a 4. This

says: “‘I accept all messages up through message 4

Low control chara'cter overhead.

No “‘character stuffing.”

DDCMP uses ASCII control characters for SYN,

No separate ACKs when traffic is heavy;

SOH, ENQ and DLE. The remainder of the message,

and I’m still looking for message 5.”
D.4.3

Character Coding

mcludlng the header is transparent
D.4.4 Data Transparency

DDCMP defines transparency by use of a count field

this saves on extra SYN characters and
inter-message gaps.

Multiple acknowledgments (up to 255)
with one ACK.

in the header. The header is of fixed length. The
‘count in the header determines the length of the
transparent information field, which can be zero to

The ability to support point-to-point and
- multipoint lines.

DV11/PDP-11

TERMINAL

Sends a STRT (START) message which
means:

‘I want to begin sending data

first message will be 1.”

OO,

to you and the sequence number of my

Receives STRT message.

Sendsa STACK (Start Acknowledge)
message which means: “OK with me;

here is the first sequence number (5) I

will use in sending data messages to you.”
Receives STACK.

Sends Data Messages with a response field

set to 4 and the sequence field set to 1,
which means:

“I am looking for your

message 1.”” Other messages may be sent
at this time (i.e., messages 2, 3, etc.)

without waiting for a response.

Receives Data Message 1 and checks it for
sequence and CRC errors. If there is a

sequence error, go to 12. If there is no
error, go t0 9.

A CRC error was detected. Computer B

sends a NAK message with the response
field set to 0, which means: “All messages

up to 0 (Modulo 256) have been accepted

and message 1 is in error.”

Computer A receives NAK, retransmits
Message 1 and any other messages sent

since (i.e., 2, 3, etc.) if already sent. \

Sends ACK response of 1 either in a separate
ACK message or in the response field of a

ol6

data message.

Receives ACK and releases Message 1.

Continues sending messages.
Discard message and wait for proper

Times out because of lack of response /
for Message 2. Sends a reply for
~

Message 2.

Retransmits Message 2 and
following messages.

—

- Send NACK response
of 1 in the
response field.

Figure D-5 DDCMP Sample Handshaking Procedure
D-7

D.4.6 Synchronization

DDCMP achieves synchronization through the use

sending PAD (all 1s) characters, the intermessage

interval must be at least 14 character times in length.

of two ASCII SYN characters preceding the SOH,.

ENQ, or DLE. It is not necessary to synchronize

D.4.7

between messages as long as no gap exists. Gaps are

DDCMP has a bootstrap message as part of the pro-

filled with SYN characters.
Two sync characters are

tocol. It begins with the ASCII control character

—

required, but more are usually transmitted. If syn-

DLE.

chronization between messages is deliberately lost by

reload programs and is totally transparent.

The information

field contains the system

Bootstrapping

APPENDIX E

GLOSSARY OF TERMS AND ABBREVIATIONS

Binary Synchronous Communications (BSC) — A uni-

ACK - Acknowledgment

ACK 0, ACK I (Affirmative A ckfiowledgment ) - TheSe

form discipline, using a defined set of control characters and control sequences, for synchronized

munications) indicate that the previous transmission

a data communlcatlons system. (Also called

block is accepted by the receiver and that it is ready

BISYNC))

to accept the next block of the transmission. Use of
ACK 0 and ACK 1 alternately provides sequential

BISYNC - Binary Synchronous Communications.

replies (DLE sequence in Binary Synchronous Com-

transmission of binary coded data between stations in

checking control for a series of replies. ACK 0 is also

an affirmative (ready to receive) reply to a station
selection (multipoint), or to an initialization sequence

Block Check Character (BCC) - The result of a transmission verification algorithm accumulated over a

(line bid) in point-to-point operation.

transmission block, and normally appended at the

-~ ASCII - American Standard Code for Information
Interchange. This is the code established as an Ameri-

can standard by the American Standards
Association.

end; e.g., CRC, LRC.

Byte— A binary element strlng operated upon as a
unit and usually shorter than a computer word, e.g.,

six-bit, eight-bit, or nine-bit bytes

Automatic Calling Unit (ACU) - A dialing device

Carrier — A continuous frequency capable of being

(Bell

modulated or impressed with a 51gnal

801

or equivalent) that permits a business

machine to dial calls automatlcally over the commun1cat10ns network

Baseband ~ In the process of modulatlon the basebandis the frequency band occupied by the aggregate

CCITT- Comite Consultatif Internationale Telegraphique et Telephonlque An international consultative committee that sets 1nternat10na1

communications usage standards.

of the transmitted signals when first used to modulate
a carrier.

Baud - A unit of signaling speed. One baud corresponds to a rate of one signal element per second.
Thus, with a duration of the shortest signal element

of 20 ms, the modulation rate is 50 baud.

Channel - (a) A path for electrical transmlssmn
between two or more points. Also called a circuit,
facility, hne, link, or path. (b.) The physical facility or

path plus control codes, within which the actual data
to be transferred is embedded.

Character - The actual or coded representatlon of a
digit, letter, or special symbol

Baudot Code - A code for the transmission of datain

which five bits represent one character. It is named

for Emile Baudot, a pioneer in printing telegraphy.

The name is usually applied to the code used in many
teleprinter systems and which was first used by Murray, a contemporary of Baudot.

CO - Carrier On.'

Communication Control Character — In ASCII, a
functional character intended to control or facilitate
transmission over data networks. There are ten control characters specified in ASCII which form the

basis for character-oriented communications control

BCC - Block Check Character (g.v.)

procedures. (See also: Control Character.)

Concentrator — A communications device that pro-

Data Link - An assembly of terminal installations

vides
a communications capability between many

and the interconnecting circuits operating according

low-speed, usually asynchronous channels, and one

to a particular method that permits information to be

or more high-speed, usually synchronous channels.

exchanged between terminal installations. Note: The

Usually different speeds, codes, and protocols can be

method of operation is defined by particular trans-

accommodated on the low-speed side. The low-speed

mission codes, transmission mode, d1rect10n and

channels usually operate in contention, requiring buffering. The concentrator may have the capability to

control

be polled by a computer, and may in turn poll

Data Set - A device that converts the signals of a

terminals.

business machine to signals that are suitable for

transmission over communication lines and vice ver-

Conditioning - The addition of equipment to leased
voice-grade lines to provide specified minimum values of line characteristics required for data transmission, e.g., equalization and echo suppression.

Contention— A condition on a communications chan-

sa.

It may also perform other related functions.

(Same as “modem.”).

DDCMP - Digital Data Communications Message

Protocol. A uniform discipline for the transmission
of data between stations in a point-to-point or multi-

nel when two or more statlons try to transmit at the

point data communications system. The method of

same time.

physical data transfer used may be parallel, serial

Control Character - (1.) A character whose occur-

synchronous, or serial aysnchronous.

rence in a particular context initiates, modifies, or

Demodulation — The process of retrieving an original

stops a control function. (2.)
In the ASCII code, any

signal from a modulated carrier wave. This technique

of the first 32 characters. (See also: Communications

is used in data sets to make communication signals

compatible with business machine signals.

Control Character.)

Control Procedure — The means used to control the

orderly communication of information between stations on a data link. Syn: Line Dlscnphne (See also:
Protocol.)

Dial-Up - The use of a dial or push-button telephone
to initiate a station-to-station telephone call.

Dibit — A pair of binary digits. Used to encode the
four carrier phase shifts required for binary modu-

CRC
- Cyclic RedundancyCheck (q.v.)

lation by modems.

Cross Talk- Unwanted insertion of signal from an

Direct Memory Access (DMA) - A facility that per-

mits 1/O transfers directly into or out of memory

adjacent communication channel

without passing through the processor’s general reg-

isters; either performed independently of the process-

CS - Clear to Send.

or or on a cycle-stealing basis. (Same as NPR.)

Cyclic Redundancy Check (CRC) - An error detection

schemein which the check characteris generated by

DLE (Data Link Escape) — (a.) A control character

taking the remainder after d1v1d1ng all the serialized

used in BISYNC to provide supplementary line-con-

bits in a block of data by a predetermlned blnary

trol signals (control character sequences or DLE

number.

sequences). These are two-character sequences where

the first character is DLE. The second character vari-

to identify the data sets (modems) manufactured and

es according to the function desired and the code
used. (b.) A control character used in DDCMP to
signal a bootstrap message.

Dataphone - A trademark
of the A.T.&T. Company
supplied by the Bell System for use in the transmission of data over the regular telephone network. It is

Duplex- In communications, pertaining to a simulta-

also a service mark of the Bell System that identifies

neous
. two-way, independent transmission in both

the transmission of data over the regular telephone

directions,

‘network (DATAPHONE Service).

(Contrast with half-duplex.)

sometimes referred

full-duplex.
»

' EBCDIC - Extended Binary Coded-Decimal Inter-

Idle Loop - See Executive Routine.

change Code. An 8-bit character code used primarily
in IBM equipment. The code prov1des for 256 differ-

ITB (Intermediate Text In Binary Synchronous Com-

ent b1t patterns

munications, Block) - A control character used to terminate an intermediate block of characters. The
block check character is sent immediately following

Echo — A portion of the transmitted signal returned
from the distant point to the source with sufficient

ITB, but no line turnaround occurs. The response fol-

magnitude and delay so as to cause interference.

lowing ETB or ETX also applies to all of the ITB

ENQ (Enguiry) - (a.) Used in BISYNC as a request
for

response

obtain

identification

and/or

checks immediately precedlng the block terminated
by ETB or ETX

indication of station status. ENQ is transmitted
as

L - Low.

part of an initialization sequence (line bid) in pointto-point operation, and as the final character of a

Line — See Channel.

selection or polling sequence in multipoint operation.
~

(b.) Used in DDCMP to signal a control message.

Link — See Channel.

EOT (End of Transmission) — Indicates the end of a

Longitudinal Redundancy Check (LRC) - A system of

transmission, which may include one or more mes-

error control based on the transmission of a Block

sages, and resets all stations on the line to control

Check Character (BCC) based on preset rules. The

mode (unless it erroneously occurs within a transmis-

check formation rule is applied in the same manner to

sion block). EOT is also transmitted as a negatlve

each character.

response to a polling sequence.

LRC - Longitudinal Redundancy Check.

ETB - End of Transmission Block.

Mark - Presence of a signal. In telegraphy, mark rep-

ETX (End of Text ) — Indicates the end of a message.

resents the closed condition or current flowing.

If multiple transmission blocks are contained in a

Equivalent to a binary one condition.

message in BSC systems, ETX terminates the last
Modem - Contraction of modulator-demodulator. A

block of the message. (ETB is used to terminate preceding blocks.) The block check character is sent

device that modulates and demodulates signals trans-

immediately following ETX. ETX requires a reply

mitted over communication facilities. (Same as data

indicating the receiving station’s status.

set.)

Executive Routine — A program that monitors system

Modulation - The process by which some character-

activity and transfers control to subordinate pro-

istic of a high-frequency carrier signal is varied in

grams for handling. When handling is complete, con-

accordance with another lower frequency ‘““‘informa-

trol is returned to the executive. When the system is

tion signal. This technique is used in data sets to

inactive, the executive spins in an idle mode.

make business-machine signals compatible with communication facilities. |

Facility — See Channel.

Multzplexmg The d1v1s1on of a transmission facfllty

Full-Duplex - See Duplex.

into two or more channels.

~ Multipoint Circuit — A circuit interconnecting several

H - High (positive).

stations.
Half-Duplex
- Pertaining to an alternate, one-way-at-

a-time

independent

transmission. (Contrast

NAK (Negative Acknowledgment) - Indicates that the

with

previous transmission block was in error and the

duplex.)

receiver is ready to accept a retransmission of the

erroneous block. NAK is also the ‘“‘not ready’ reply

" Header — The control information prefixed in a mes-

station

selection

(multipoint)

or to

initialization sequence (line bid) in point-to-point

sage text, e.g., source or destination code, priority, or

operation.

message type. Syn: Heading, Leader.

E-3

Non-Processor Request

(NPR) - High priority data

RS - Request to Send.

transfers to the PDP-11 Processor. These are direct

SDLC - Synchronous Data Link Control. A protocol

memory access type transfers, and are honored by the

processor between bus cycles of an instruction execu-

for the transfer of data between stations in a point-to-

tion. NPR data transfers can be made between any

point, multipoint, or loop arrangement, using syn-

two peripheral devices without the supervision of the

chronous data transmission techniques.

{)

processor. Normally, NPR transfers
are between a
mass storage device, such as a disk and core memory.

Seizure Line — Terminating a transmission line in a

An NPR device has very fast access to the bus and

DC path, causing a relay element in the telephone

can transfer at high data rates once it has control.

switching network to trigger and complete the circuit

The processor state is not affected by the transfer;

between the calling station and the called station.

therefore, the processor can relinquish control while

Voice or data is then inductively coupled between the

an instruction is in progress. (See DMA.)

transmission line and the terminal. Equivalent to tak-

Non-Transparent Mode — Transmission of characters

phone instrument or data set.

defined

character

format,

e.g.,

ASCII

ing the handset ““off the hook” of a conventional tele-

EBCDIC, in which all defined control characters and

Selective Calling — The ability of a transmitting sta-

control

tion to specify which of several stations on the same

character

sequences

are

recognized

treated as such.

and

line 1s to receive a message.

NS - New Sync.

Serial Transmission - A method of information trans-

fer in which the bits composing a character are sent
Parallel Transmisson — Method of information trans-

sequentially. (Contrast with parallel transmission.)

fer in which all bits of a character are sent simultaneously Contrast with serial transmission.

Signal- In communication theory, anintentional disturbancein a communication system. (Contrast w1th

Path See Channel

noise.)

points

to permit

them

—

Silb — A first-in, first-out hardware buffer, such
as the

Polling- A centrally controlled method of calling a
number of

transmit

RC Silo and the NSR in the DV11, which use the

information.

3341 Propagable Register 1.C., descrlbedin Appen-

dix B.

~ Priority or Precedence — Controlled transmission of
messages in order of their designated importance;

Simplex Mode - Operation of a channel in one direc-

€.g., urgent or routine.

tion only with no capability of reversing.

Private Line or Private Wire — A channel or circuit

Single-Address Message - A message to be dehvered

furnished to a subscrlber for his exclusive use (non

to one destination only.

dial-up).

Start of Heading (SOH) - (a.) In Binary Synchronous

Protocol — A set of rules which govern the sequencing,

identification,

and

synchronization

Communications (BISYNC), precedes a block of

data

heading characters. (b.) In DDCMP s1gnals a data

exchanged between data terminals.

message

RC - Received Character.

Station - One of the input or output points on a com-

* Reverse Interrupt (RVI) - In Binary Synschronous

munications system.

Stuff a DLE - Send a Data Link Escape character

Communications, a control character sequence (DLE

sequence) sent by a receiving station instead of ACK1

just prior to the character to be transmitted.

or ACKO to request premature termination of the

transmission in progress.

STX - Start of Text.

E-4

Synchronous Idle

(SYN) — Character used as a time
fill in the absence of any data or control character to

maintain synchronization. The sequence of two continuous SYNs is used to establish synchronization
(character phase) following each line turnaround.

System Unit — Three 8-slot connector blocks mounted
end-to-end and capable of accommodating up to four

hex modules (printed circuit boards). When two sys-

tem units are connected to form a double system unit,
up to nine hex modules may be accommodated.

TeletypeWriter Exchange Service (TWX) - An auto-

entry to and exit from the transparent mode is
indicated by a sequence beginning with a special Data

Link Escape (DLE) character.

TTD - Temporary Text Delay (q.v.).

Unibus - The single, asynchronous, high-speed bus
structure shared by the PDP-11 processor, its memory, and all of its peripherals.

Unibus Load - The electrical connection of two 8881
outputs and one 8640 input to a Unibus signal lead.

matic teleprinter exchange switching service provided

Unit Load - All inputs impose a load on the outputs

by Western Union.

driving them. A TTL unit load requires 1.6 mA at
ground and +40 uA at +3 V. The load imposed upon

Telex - An automatic teleprinter exchange switching
service provided by Western Union.
Temporary Text Delay

an output by an input can be defined as a number of

unit loads.

(TTD) - In Binary Synchro-

Vector - Two words, containing the value of the pro-

nous Communications, a control character sequence

gram counter and processor status word, respective-

(STX...ENQ) sent by a transmitting station to either
indicate a delay in transmission or to initiate an abort

ly, that direct the processor to a new routine.

of the transmission in progress.

Vector Address — The address of the location contain-

ing the vector words.
Term - Terminal.

Vertical Redundancy Check

Terminal - (a.) A point at which information can
enter or leave a communication network. (b.) AnI/O

device designed to receive or send source data in an
environment associated with the job to be performed.

Capable of transmitting entries to and obtaining output from the system of which it is a part.

Text - That part of the message which contains the

substantive information to be conveyed. Sometimes

(VRC) - A check or par-

ity bit added to each character in a message such that

the number of bits in each character, including the
parity bit, is odd (odd parity) or even (even parity).

Volatile — A storage device whose contents may be

altered by a power shut-off. The DV11 RAM is a volatile device.

VRC - Vertical Redundancy Check.

called “body” of the message.
WACK - Wait-Before-Transmit Positive AcknowlTransparent Mode - Transmission of binary data

- with the recognition of most control characters suppressed. In Binary Synchronous Communications,

edgments. In Binary Synchronous Communications,
this DLE sequence is sent by a receiving station to
indicate that it is temporarily not ready to receive.

DV11 COMMUNICATIONS

MULTIPLEXER

MAINTENANCE MANUAL

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EK-DV11-MM-002

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