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XX-947EA-8A-1

August 1978

24 pages

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Document:	700819 PDP-15 Floating-Point Processor
Order Number:	XX-947EA-8A
Revision:	1
Pages:	24
Original Filename:	http://bitsavers.org/pdf/dec/pdp15/memos/700819_PDP-15_Floating-Point_Processor.pdf

OCR Text

~DmDamD

INTEROFFICE

MEMORANDUM

8-0012-70
DATE:
TO:

Engineering Committee

August 19, 1970

FROM: Tom Holmes

":roc!1~ W.

DEPARTMENT: PDP-15 Engineering

The attached writeup is an introduction to the PDP-IS Floating-Point
Hardware project - E-15-0763S.

It serves as a brief orientation in

preparation for a presentation before the Engineering Committee on
August 20, 1970.

Included in the writeup are an opening introduction

from Marketing, a discussion of floating-point architecture, an estimate of cost and development schedule, and several explanatory appendices.

/jan
Enclosure

ENGINEERING COMMITTEE
K. Olsen
R. Cady

D. Chertkow
A. Kent
F. Wilhelm
L. Gale
J. Cudmore
R. Doane
R. Dow
J. Milton
D. Best
G. Butler
B. Melesky
E. Correll

PDP-15

FLOATING-POINT PROCESSING UNIT (FPU)
ARCHITECTURE

THOMAS G. HOLME$
2ll JULY 1970

EXT. 3440

TARL!: OF CUNTENTS

MARKET IN G !:\lTROorrtT I O~,

DE~IGN

GUIDELINES

ORGANI7ATION • • •

••••••••••••••••••••

..• • • • •

·.• • •
.................
•

• •

•

HARDVARE IMPLEMENTATION

Lt.

DEVELOPtlJENT gr",;HED'JLE AND M4\lUFACTURI,.\fG COST ESTIMATE • • •

APPEND I 'X A
I>J STqUCT I ON SET

• • • • • • •

· • • • • • • • • • • · At

APPENDIX B
HANDLING OF INTEHRtTPT EXCEPTIONS • • • • • • • • • • • B1
APPENDIX C
(jt>ERATHJG

FEATURES AND CO\iSTHAI\JTS

·• • • • • • •• •

APPENDIX D
EXAl.'1PLE PROGRtu'Vl CODING • • •

• • • • •

•

1:)1

MARKETING INTRODUCTION

PRODUCT DEF'I\JITION' AND CONCEPT
TH~

FLQATING-POINT PROCESSOR IS DESIGNED TO BE A SEPARATE HARDWARE
TO Lq INSTRUCTIO\JS PERFOHNIN~1 SINGLE AND DOUBLE

DEVICE HITB UP

'PRECISION ABITH!"1ETIC'.

f:~ ..

;')

THE UNIT IS DESIGNED 1'0 SIT ON fHE PDP-15 MEMORYRUS AND OPERATE
AUTONOMOUSLY FROM THE CENTRAL 'P'iOCESSH\JG 1JN1T;• . IT, THUS, ACTS AS
A SEPAHA'I'F: PiiOGESSOR PROVIDIMG THS USER t.TITH }tOUR Dr STli\JCT UN ITS:
~1EI\l10RY, CPU,
I/O, AND FLOATING-:;>OIhfT.
~

MAHKETING

THE FLOAT IN G- PO INT HARDtaJARE PROIJ I DE S A FURTHER COM?LEMENT TO THE
PDP-I5.

IT SERVES NA~JY MARKETS A~TD CONSTITUTES A NECESSARY PRODUCT
IT T..\;TILL ALSO HELP TO FURTHER DIFFERENTIATE PDP-I1

EL\lHANCEMENT.
A~D

PDP-IS PBOSPECTS.

t·1ARKE,TS THAT HILL BE AFFECTED BY THIS HARD~lA.R.E Ii\lCLUDE THE PHYSICS
AND ANALYTICAL Ii\JSTRUMENTATION \\'HERE .l\PPROXIMATELY 20)% (15:;"20% FOR
PHYSICS, 25% FOR AI) OF THE MACFH\iES ARE USED PRIMARILY FOB NlF.·1ERICt
ANALYSIS; THE HYBRID MARKET TJiHEFE ,ALl\10ST ALL MACHINES (90-100%)
REnUIHE THE CALCULATION SPEED E}TFEH FO''R PACI1\JG OR FOR DIGITAL
S I MULAT I ON ;A.t\JD OUR GENERAL SCIENTIFIC tiARKET r,JHERE HIGH SPEED
ARITH{\lETIC IS DESIRABLE TO ACHIEVE RETTE'R PROGR.A~1 THROUGHPUT (30%
OF MACHINES).
THE HIGH S?EEDCAPABILITY 11lHEt,f COMPLEMENTED BY FORTRt
SOFT~"AHE C{-\[\T REDUCE CALCULATION· TIME BY AN ORDER OF)~AGf\lITUDE AND MA
ALLOt,! THE PDP-15 TO ENTEH THE THAD I T IONAL COMPUTAT ION Mtf'RKET NO~·1

SERVED BY THE IBM 1130.
THE SCIENTIFIC r-vU\RKET IS
O~TION

PRESENT~Y

VERY TIGHT Ot\] FUNDS.

AN~.DD-ON.

i,rE THEREFOR

SCIENTISTS ABE ?RESENTLY
BUYING BASIC SYSTEt-'lSl LATER A.5 E\]D-OF-YEAR FUNDS AND A LOOSER ECONOt;.'j
PEB:"1IT, THE FLOAT.ING-POINT PROCESSOR "JILL BECO~IE A DESIRABLE ADD-ON.
~JJE EXPECT THAT THE DEMAND ~qILL STA RT '{.IP SLO~Jl, ACCELERATE AS THE
?OPULAT ION OF PDP-IS' S EXPANDS AtJD SLOl.T DO',,1'N AS THE PDP-IS I S PHASED
OUT.
THE PRODUCT LIFE IS ESSENTtALLY THAT OF THE PDP-15 ALTHOUGH
THF:RE SHOULD STILL BE SOME RESIDUAL ADD-ON LIFE 'PAST THE PDP-I5
SEE THIS

PHASE OUT.

AS PRIMARILY

~-!A f(DT:JARE t,.TI I.L ALLO~,! TI-P~ PDP- 15 TO PEH~F'ORI4 l:lELL
ON 'PENC}·F'1i1Hl{S.
G{TPBF.NTLY '.;~. gENCH~v'LA.R;{ POOPLY EVEN COrVJPARED TO
;'4ACHI~\)F:S ;.TITH sLoi\n~R CYCLE TINf'F DUE Til OUB SOFTtlTAHE FLO,4TING-POINT
.A?I'fHMETlr. F·1PL'E>1~NTEn UIA EAE.

F'LDAT F'lG-)O I.\IT

HFf,?T .. ETT 1:'I\r,YARD PA.S DF'MnN5T'RATT. D RUT \L')T YF.i DEL IVERED FLOATIN'f.':PO I ~lT HA ~D7"'1\ RE A-r~\1 Apn~o x I ;"1 A1 F: PP T~ i~ Or' S 20K.
DEl. T. ~ir.''!;>y T c:. PLANNED IN
tJA.:\lUAHY, 1971.
TJ-lE HARD~'7A~17 MTll P'KPFI)'Pl\1 TRIGONOMETRIC FUNCTIONS
AS !,TEL.1 . 1\ (: FL 0 A TIN G- POI N l' f\ D D, S trB T 'R ACT, MPL T I 'PL Y, . D I 'T! n F., Ai':\] D
NORMALI~E.
~
OTiP DpqDf.'SFD HAPDT.1l\R~ r,iILl. GIVE PS A q;IGNIFICAN1~ ADV,~NTAG)~ IN THE
00r-:f,> XDS A!\}D HONEY~~Ji'.:LJ. /[\11) HELP IN T}{1~ :'1ATCH '!7ITH HEvlLETT

'\·1I'f' I<f.<:T

DACHA 'PD.
THE HARDi,lfd-1E I '\JTF rER An I THiVj ET I C ALL01·YS US TO PERFOBr.l'OOUPLF: ;:n.;.;-:r.ISION Il\f,!·t'~('EF CALCUl.A'·IO£\~ AND THUS l\NS~JEPS ONE
OF' HO~lEYT'!ELL' S SELL ING r~PG!Ji\;~~N1'S.
IT ,':;'LSO PBOVIDES .AN EFFECTIVE
~~iARKET IN(~ TOOL I N ~OMPAF I so~ t·n TH TEE HE111LETT Pl\CKAHD HAPDt.1ABF..

t\T A SELL E\JG ,,:>? I CE OF $10-12K iYE EXPECT TO
oOI~T

SELL AROUND 2S{j) FLOATIN G-

PRUCESSORS.
1913

1972

Cl~

0:3

()4

()1

1)3

nLt

:~'?i

4;~

II (;1

'~5

l!(;j

ROBERT L. KATZ
'PDP-15 t'1ARKET ING

(PAGE 1)
1.

DESIGN GUIDELINES

THE FLOATING-POII'JT PROCESSOR t'-1nST BE l!BLE TO RUN THE EXI STli\TG
FORTRAN COMPILER AT AN II:viPROVEL·. SPEED A.ND 1,,fITH A MINIMLtrvt i\1UMBE:R OF
CHANGES TO THE COMP ILEB..
THI SIS ACCOMPL I SHED BY REPLACIi\JG EACH
FLOAT lNG-no INT SOFTt!TARE SUBROUT INE 1,rI TH AN EQUIVALENT HARDHA.RE
INSTRJJCTION.
GLENN \,JICKELGHEN' S MEI"1'JPANDtHvI OF JA[\JUARY 6" 1970,
SPECIFICATION FOR FLOATING"';POINT HARDTJ1J\RE FOR PDP-1S .. GIVES THE
;~t
FOLLOl~7 I'l\lG:'

"II.

FLOAT1NG-POINT

INSTRUC.TION FOR~lAT

THE FORTRAN IV COMPILER GENERA.TES A CALL, TO A SUBROUTINE 'FOR EA6.H
FLOATING OFERATION TO BE PEHFOHMED.

JCv1S SUB

.DSA ARG

THIS C.ALL LOOKS AS FeLLOi,TS:'

IFLOATING OPe
IARGUMENT
IRETURN

THE SUBROUTINE SUB IS DIFFEHENT FOR DOUBLE PRECISION ARGUtflENTS THA\1
IT IS FOR SINGLE PRECISION ARGU~ENTS.
THE ADDRESS ARG POINTS TO THE
FIF!ST ~I!ORD (IS THE ADDRE::;S OF THE FL~ST TIJORD) OF THE ARGUMENT OF THE
Fl.OATING-POINT OPERI-\TIO\J (15 BIT ADDHESS).
THE BITS (/}-2 OF THE
ARGUMENT p.nE?:EHO EXCEPT ~vHEN I~DIREGTION IS INVOLVED.
IF BIT (-) OF
THE ARGUMENT IS 1 THEN BITS 3-17 CONTAIN THE ADDRESS OF A LOCATION
PHOSE CONTl-:NTS (BITS 3-17) POINT TO THE FIRST \~OR.D OF THE ARGtF4ENT
(O\1LY 1 LEVEL OF INDIRECTION IS INVOLVED AND BITS 0-2 OF THI S ~.iORD
ivlUST BE. IGNORED).
AFTER THE 0 PERAT:r ON I SCOMPLETE.t CONTROL IS
RETURNED TO THE NEXT REGISTJ;:R FJLLO\\TING THE ARGUME~T ARG.
IF
FLOATING-POI~T HARDHARE IS TO O:)ERATE SUCCESSFULLY i·lITH THE C01VIPILER ..
A HARDT,'iAPE INSTHUCTION MUST BE ~V!,\ILl~BLE ',·JHI<;;H CAN REPLACE THE
I~STRUCT ION ( Jr~S SUB) r'lHICH TBA'lJSFEBS CONTROL TOSOFT~\!ARE' ROUTINES
l.iHI CH HANDLE THESE OPERAT I 01\1 S.
I ~ OTHER 'J10BDS AN lOT (OR OTHER OP
CODE) I{\lSTHtTCTION ~1UST REPLACE THESE ROUTH,lES.
THE HARDr·TABE FLOAT lNG-PO INT '0 AOCESSOR NU5T ALSO PERFORM TH! S O\JE
LEVEL OF INDIRECTION tllHECoJ DIREC fED."

THE NECESSITY OF EXECUTING IN-LINE CODE GENERATED BY
THE~

CO£v1P ILEB M,ADE IT i\JECESSARY TO PLACE THE FPO

O~\1

THE

~'lEMORY

BUS ..

IMSTEAD OF PLACING IT ON THE I I ) BUS.
THE FO~TRA~ COMPILE? HAS
DICTATED ~HAT CONSTITUTES THE F~U.
EARLIER DESIGNS OFFERRED A
?O\~lEr"FUL FLOAT! 'JG-PO!:\TT PAJl{f\GE, l~UT THE SERIOUS LH>1ITATION
THAT THE PRESENT FOR ..tRA\l C01'P ILEH COUt.D NOT TAKE AD'lA.NTAGE
f)F' SOCH A TTN!T HITHOTJT UNDERGOI ·.JG l\N FX'TENSIVE BEi·!RITF:.
ALTHOHGH
A CO;VjprLFP~r.:;,TRlTF T;JAS CONSIDER ~l), IT Pl\S RE(.J~~CTEn ."i~ P·1PBACTICAL
[:':IT THI S PO Ii\jT IN TI£V1E.
SI,\iCE T off: i"t('i~Jn!11 TY OF POP-15 nc;~;;RS"f DEAL
F:XCLflS rUT\LY i.TITE FORTRAN, THF: P =?Opi) SEn Di~S I GN i·TIl ... l,. OFFER ONLY ~. .THAT
C~;\l i:lE i'~I\.sILY I~1PLEr~~'i4:NTED IN TF!: pn:;:~:;":'\JT FORTRAN CGMPILEB.
THE
~F\H~T.F F:)((~~r.)TION TO THIS IS THE INCL.fJc,rCr\i OF INTFf:;SB,~RITHMETrC"
PHICH TAKf.:::S ADVAMTAGE OF MOST 0;- 1'F':;; FLOATING,l;.PotNT HARJ)\,TARF: AMO
PQn'i}~!)FS ",l/Y!~l{;:;:'rIl\TG if1ITHAN ATTR,~CTil.lE '\14TH PA~K!4GE TO D1 STIl\JGU,rSH
I T F'~Oi~ ITS CO~·1t)ET I T I O£-J •

MOHE
~\f{.\S

(PAGE 2)
2.

ORGANIZATION

INSTRUCTION FORMAT
THE FPU HAS BOTH S INGLE AND DOUBLE LENGTH INSTRUCTIONS.

FIRST WORD

,;;1

.c,' '

9 10
1112 13
J

5 6

I I1

SECOND WORD

ILlplFI

BITS 00-05 OF THE FIRST \\,ORD CONTAIN AN OCTAL "71" TO

SDEGIFY A
THF. CPU.
()?

F~U

INSTRUCTIO!\l.

BITS 06-09 DECODE I~TO SIXTEEN UNIQUE INS1'RUCTIONS

" BIT 10=(/), SINGLE: LENGTHqNSTRUCTION
BIT ,10= 1, DOUBLE LENGTH INSTRUCTION

BIT 11=(1, SINGLE FREe I S I O(\l
BIT 11 = 1" DOUBLE PRECISION

BIT 12=0, INTEGER FORi'1AT
BIT 12= 1.~ FLOATING FORMAT

BITS 13-17 MODIFY THE LOAD AND STORE INSTRUCTIONS
13
14

!UNA.SSIGNED
ROUND FROM DOUBLE TO

MAKE POSITIVE
MAKE NEGATIVE
COMPLEMENT

I
A

SINGLE PRECISION

BIT 0@=1 SPECIFIES INDIRECTION
BITS 1:3.1-11 SPECIFY THE ,ADDPESS OF THE FI;'RST "YORD OF

THE ARGUMENT

THE "71" APPEARS AS A NO-OPERATION

SEE ApoENDIX A

$
(PAG},

DATA FORMAT
THE FPU SINGLE AND DOUBLE PRECISION DATA FORMATS ARE THE
SAME AS THOSE IN THE EXISTING PDP-1S FLOATING-POINT

SOFT~']ARE.

DOUBLE PRECISION FLOATlhTG-POINT (54 BITS)

FIRST
WORD

1,1- - - -____________-----------11 I
\-------EXPONENT

(2'S COMPLBMENT)

SECOND
.ORD

~la~I--------~'
- _______~r
1----__________----~------17
p

" \ ' - - - - - - - HIGH ORDER MANTISSA
\

~·----------------------------SIGN

TRIRD
WORD
SINGLE PRECISION FLOATING-POINT (36 BITS)

FIRST
WORD

.~
_.

_',-____8_9_-_ _ _ _ _ _
_

EXPO..::r
( 2 • S .COMPLEMENT)
LOW ORDER MANTISSA

:~:ND

I~.~1----------------------------~----1-7~
I
I
.

·NJOTEI

THE

\ " ____- - - - - ' - - - - - - H I G H ORDER. MANTISSA.
SIGN

FLOATI_N_G-P-.QJNT~!ISSAl,S

FORMAT.

KEPI._ IN SLGt\l __ AN_D ItAGt.'\lITUDE

ALL OPERANDS t,RE ASSUMED NORMALIZED..

(PAGE 4)
INTEGER ARItHMETIC ALSO HAS BOTH SINGLE AND DOUBLE PRECISION.

DOUBLE PRECISION INTEGER (36 BITS)

FIRST
WORD
:-:

I'--~____________------~--1? I
'"------'HIGiIOBDBR OPBRARD
.;;

SECOND
WORD

j------____-~---'r-t--17

\------··LOW ORDER OPERAND

SINGLE PRECISION INTEGER (18 BITS)

NOTE:

THE INTEGER OPERAND IS IlV Tvl0' S COMPLEMENT FORMAT.

(PAGE 5)
(~PFRAT ION

CORE
MEMORY

-1~Fpul
PDP-IS
CPU

~rJ·f}.~ f~t.()ATING"'POINT SYST~r1 COt~FIGtJRATI(}N HA...S 'fHB :FPt.1 '·Bl~.AC·~
nO'{1f PHYC:: I CA.LLY OR' 0 ON TH~~ MEM) RY 'RfT S '8ET'iJEE\l CORE MEi'lfORYAND
T'..r;·~ DJ)P-l l )
(~pn.
THnS S ITTJATED, THE FPU MONITORS ALL INSTPucrIOt\J'5
F'f~T~H"Sn F"-10j-lj CORE AND EX!\M F\JF.S EACH' Ff)'Q THE "71 tt IN BITS 00-05.
THE "71" APPF:ARSASNO-OPE1~AT 10 \l IN THE CPU, BUT IT IMM)~::DIATEL. y
FI.~r,~ TPF: FPU TO ANNOUNCE ITS OGCUHBANCE.
THE FPfT ACK1\H)\~1FI..DGES BY
l)TSABLINC, THE CONT'ROL CIHcnrTBY ~IJHIG'a ALLOr.~S THE CPU TO MAKF. A
~"'I;,~:ViO~Y ~F(HTRST.
I/O MEMORY REhFJESTS ABE STILl. ALLO~,iEDACCESS TO
COlE.
THE
BITS TO THE RIGHT OF "71" PROVIDE If\!FORMATION ON THE
1\,S'fRUGTION TYPE, INSTRUCTION LENGTH, DATA PRECISION .. AND DATA Fq'RMAT.

IF A DOUBLE LENGTH It\JSTRUCTION IS SPECIFIED, THE C'PU IS
E;'lA~LF.D

TO ALLOl\T FOR ONE MEMORY ACCESS TO OBT.AIN THE SECOND WORD OF
THF: INSTRrrCTION.
THE CPU "be T·JILL I\JG'REMENT 'PAST THIS SECOND,l\TORD
f:'iNO BE GOHRECTLY POSITIONED FOR C9NTINUED EXECUTION t..THEN CONTROL
IS RETOR:\JED.
THIS TECHN[QUE OF ,ALIGi\lUJG THE PC REQUIHES THAT THE

SECOND WORD BE MADE TO LOOK LIKE A NO-OPERATION TO THE

cpu.

THE

ACTUP-tL SECO\lD l,10RD IS LOADED INTO THE FPU. THI SSECOND ~. fORD CAN BE
FITHER THE ADDRESS OF THE MEMOBY OPERAND (NO INDIRECTION) OR THE
(-i1)DRES5 POli.\lTING TO THE ADDRESS OF THE: MEMORY OPERAND (INDIRECTIOl\J).
EVENTUAL T~ANSFER OF THE OPERAND TAKES ONE, TWO, OR THREE ACC~SSES
TO CORE iV1EMOBY .. DEPENDING ON THEPREC I SION AND DA.TA-FORMAT TR.ANSFERRED.
THE LAST PHASE OF TI1E INSTRUCTI3N IS TO RELE'ASE THE HOLD ON THE CPU"

MEMORY nE9UEST CIRCUITRY.

(PAGE 6)
~.

H.A.RD\·iARE I MPLEM-r.:NT AT ION
SEVERAL MSI

(tvIEDIUt'1 SCtLE

I\TT:':GHATION)

DEVICES ARE PLAt\JNED

TO RE USED IN THE FPU.
OEC74181
DEC?Lll B2
DEC74153

4-RIT tRITHM£TIC LOGIC
C.ARPy LOOK AF~AD

U~IT

DEC74154

4-LINE TC
4-LINE TO

DEC7495
DEC?/.! 193

it-BIT SYi',iCHROi\lOUS HP/DO"JN COUNTER

4-BIT

I-LINE DATA SELECTOR
16-LINE DECODER

~HIFT

TI-ir?EE Gl~\1E~:;AL PURPOSE BO:~RDS HPVE: BEEN 1vlADE TO UTILIZE THE ABbl}E

Ie' s.

THO

16-PIN Ie's, ALL P![\lS BBOUGHT OUT .. POHER
16 A\JD 8, SEPAR/\TE GROUND LOOP FOR
EACH Ie, AVl-\ILARLE AS V961.
ONE 24-Plj\J Ie, ALL 'PINS BROUGHT OUT, POt~lEF
ON PINS 2L1 A\JD 12, AVA ILARLE A S '~1962.
T'VI0 14-P1N IC' S, ALL PINS BHOUGHT OUT .. P01,TER
ON PINS 14 A~D 7, SEPARATE GROUND LOOP FOR
KACH Ie, AVAILJ-\BLE AS i,!963.
;)j\)

PIN~

THE FIRST PROTOTYPE WILL MAKE EXTENSIVE USE OF THESE BOARDS
IN THE DESIGN.
Sl?ECIAL PARTITIONING HAS ALRJ~-:ADY '8EE~ DEVELOPED FOR'
THE SECOND PROTOTYPE HHICH \I,TILL corv1BINE SIX ·OF THESE SI~\lGLE HEIGHT
CAP.DS INT!] ONE DOt}BLE HEI GHT CARD.
THI S NEl,tJ CAPD lvILL BE USED TO
REDUCE Tl;~ 96 MODULE SLOTS HEQUIFED FOR REGISTERS AND ADDERS IN
PHOTOTyrjE I TO 32 rlIODULE SLOTS IN PROTOTYPE I I •
IF THE MODULE SLQTS
RECltTIRED F'OR CONTROL LOGIC CAN BE KEPT TO LESS THAIIJ 60% OF THE TOTAL
COrJi\lT, THE FPU CAN BE PA.CKAGED IN T'C!JO 1VIOUNTING PAr'lELS ('12H MODULE
SLOTS).
AS A COMPARISION~ THE PDP-15 CPU IS CONTAINED IN 2 1/4
(vlOiJNT ING oANELS AND USES 79 OF TJ-TO SE MODULE SLOT S FOR GON1~ROL.
IF
THE FPTJ C,AN BE CONSIDERED TO HE r\.o \'10RE CQi:wlPLEX (Ai.\JD/OR COMPLICATED)
THAN TH~-: CPU", THE LIKELIHOOD OF F'ITTING THE FPU IN THE ALLOTTED
SPACE IS GOOD.

I,\J !\ R r~ 1\) I .'j(J~T :'-'1 {'lI\IT JF .:"\ C T1: PI \1 (~ t; J c:. T, A\J ~ i}F~'R{\ r::4~ CJ(.~1' ;H"
DOLLAPC: DEP >,!onnt,r'; 7·;AS f,!'-F:i) F!.F;: F;XI c:.1 L,j(; .1]01rn.F,:':: (\"',.10 '.:)i~'t:.~{.~E··JT
I i\i T E:G f~AT~~n C I ';:;len I T CO c:T ~ T·:rE~ F' t-"' SF P T d r:~:! i'~ ~'vl I:\J r: ".' ~.j';,: CiJ c; 'I' 'J F\l ~;: 7,' "l") 1", '1. :,: ::.' •
I \JFORYIAT I (}.\i FPOi\,l THF: ':JTFH: H f:.I. C I \i c: n;~:,,·~ (\.,·T· .... ~;:,\ T 1:\] DIe !~.T !~: s 'i:'~.{ 6 T T H. ·:~:,.l ,; I
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~'( THE F' !T"~T I':)!JAliTEP OF F I SC!4L 1 C)7~·~.
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change 0
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-. . . . . . . .

FJ1~i~' .',¢ onlp' h?t t5.,' .·De
. -" s' :. I' ip.".,':.; Of.'.. 'C>f:,·pH,/t:e, t:. . . .. . .. . . .. ..... ~ ~ . . .. . . .. .' - .. . . .. . . . .. .. . . ... '. .. . .. . .. . .. . . . ~ .. .. . . .......":
:)';:?;?::;',
;t~~~.,::~:-...

t. •

~..;:;: -.""

~.'.';-':.~.~;'.~.:::':;::<~. ~ •.... ~.,:.~:~.:~. ~ ,:'.... ;". ;. .................. • .•• • .~ •• ' • • ~ .••" • ~ • • 4!' :• •' . • • • • .. • • • • • • • • • • • . • . . • • • • • • • ' • • • •"

•

':-.. ';

-.'

, " ' ,

....

.......~:. ~ .•,..•<......": .":.;"'~ ";' ~ •. ~ :•.• ~ .... ~ .............................
"";
.
,,
Estimot~d,q9fn?let.i,on
Dote: .. ~9..~~?~ ..........' .... Estimated Totat S·s:. $18.9...3 .................. .
i!"'>:~' '.
~~"~".;"?'

.'.~<

j "• • • • . :• . . • • • •!" . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . ..

- [,

F iseal Quarters

FY 71

., Qtr. 1

,.E .

.. ;', 0

3~4 .

I Mode.l Shop

325!..,orQftU19

:/ :"P . " .330 '.' ." Mechanical' Eng.
:f~_.

D' " ':l~9 '. ',' Process tnt]"
~~: ~T-'~:-~6t)~' :rYsterT~s-p;c;9;:o.mmin9
II

V , :.

]1
0

~
,;>

3~.. ,.·"'.' ..

t UiOgtlO.sHe

Programming

; ~7, .. ' . Production tOf).

~86

55'"

I Speci~l PfOiftct~
Manuals
Ho.rdwQfC

_~.
5 i.....
£ _Soft~a.-e. ~'ClolJcfs
.:Proollct Ltne Fng.

,.' Y..
f

0': ! ' : '

G. Gerelds

FY 71
Qt;::-T""

FY 71

Qtr:-r

FY 71
Qtr:-4-

20,.0

13.0
9.0

4.5

18.0

2.0

6.0

3.0

15.5

30.5

9.0

1.3

R. Melanson
t. Prentic.:e
'J. Srockebrand.
l. Portner

0.5

---r!

l. Portner
f~. Puffer"-

3. 7

18. 0

J. St.Amo_ur~~~~~~~~~~~_+~~~~~~~~~.~
4.U
3.8
J ... Betlontl~ni
3.0
3.0

G, .A.rnOI~_,+'~

9.0

----""-----i- -

- : -_ _ ._,_~,, __ .,._ ~_•._
-,

Advef'fisinq & P~~tion G ~ D'Annunzio
s.-_A_~~___........_P_t_·o._duct lin<.: !,.~':."ketin9
T

287'

---------~i~------·~---------+--------~------..
~----~----~-------------------------__--~I~------4-------~------_+-----..
~

TOTAl. fXPft..JSE

14.5

56.0

83.5

35.3

II thi) I~ 0 new ~'roi(·cl, Love Product line Monog~r 5(9" below cnd !tubm;t to A;:counting for
oss'9nplt~nt of n p1olec.t I)uml"e,. The appropriate Vice President should sign (or any proiects
shared by more fhun one Pi'oOuet Line.

"-\ppro·JeJ lJY: . , .' •.

• •••..........•••••••

. .. _......... , ..... Do te: ................. .

AIJthorazaticn ot thi:; proicct ~5'e$ not constitute budget approval. tach projecf must operate
within and under tht! control of 'heir appropriate Produ("t 1. ir1e und its bud~et.

,....rn?-,
~

......

. 4 1970

"' ' 'f'lD .. ......1
)II;,. ......."

----~~-"'

~--~

•." ' - ' -... -..... ....
"

-'"~

.._-.,---_._.-......_.

-.-.-~.

DECEMBER

NOVEHBER

LAYOUT AND DESIGN OF PROTOTYPE II

DOCUMENT

LAYOUT AND DESIGN OF PROTOTYPE I

'")

..__.....

OCTOBER

SEPTEMBER

AUGUST

JULY

JUNE

-.,--~,~.-.".

, 0...,'
. -_
_._._-_ _- _--------(''''n
Jr.. - _ • •

1971

•

...

I
I~mCHl\NIC.?\.L

I.SE IT

-1

lAJIRELIST
ID IT

ID IT

Ll\YOUT

l'..~rD

DE'S !c;~~

(IF

lev

SYSTE~~

rl- -_.

"'T1\TAL DESIGN

I
I

O.2E

O.IE O.SD
BUILD
PROTOTYPE I

SPECIFY PARTS

CHECKOUT OF PROTOTYPE I

O.ST

[

_II

O.ST

DIAGNOSTIC PROGRAtv1.MING
2PR

IPR

2PR

-1.6E
2.ST
l.SD IPR

IE
1 'It

1D
t

IE
O. 5'1'
lPR
.

I
I

1.SE
2T
2PR

2'1'

l.SE
1.ST

2PR

1.7E

OTR. 4 1971

QTR. 3 1971

-- ------.....
MARCH

FEBRUARY

JANUARY

·----·---·-----·---······1---------·-------·

~-----

APRIL

MAY~ JUNE

-...

DESIGN
PROTOTYPE II
1.SE IT

ENGINEERING SPECIFICATION
IE

WIRELIST
ID

BuILD PROTOTYPE II
D.ST

FINAL DRAWINGS

1 2 3 4 S -

:: I

LOGIC DESIGN REVIEW
MECHANICAL REVIEW
FINAL REVIEW
RELEASE TO BUILD
RELEASE TO PRODUCTION

6 PRE-PRODUCTION

CHECRO'G7

lev

2T lFS lTW lTNG

SYSTEMS
2PR

2PR

I
]

HARDWARE AND SOFTWARE MANUALS
ITW D.lE

lTW D.IE

ITW D.IE

lTW D.IE

ITW D.IE

1.GE
1.ST 1 rrW
ID 2PR

I.IE
IT ITW
4D 2PR

I.IE
IT lTW
3D 2PR

I.IE
2TW 2T ITNG
3D 2PR IFS

D.lE

lTW 2PR

('PA.GE Al)

APPENDIX A
INSTROCTION SET
INSTRiJCTI01\1 LENGTH
.ADD

STJHTRACT
R~-:'lEHSE

SqBTRA~T

DOUBLE
DOU8LE
DOUBL.E

;"HJLT IPLY
DIUIDE

DOUBLE

REVERSE ])1\1IDE

DOUBLE

LO,AD

SINGLE A:-JD DOfJRLE
DOUBLE
SINGLF':: AND DOUBLE
;; IN m.. F. AND DOU9LE

DOUBLE

STURE
FLOAT
FIX
D I (\CiL~O ST Ie
Si·jAP

DOUBLE
SINGLE

!'4()

UNASSIGNED
TF\lASS I GNET)
I Ti'J!\S S I Gl\lED
fL\lAS SIGNED

THE FIRST OPEHAND LOCATIO\1 IS A 5l1-BIT HA.'RDHARE ACCUt4tTIoJATOR
FOR DOUBLE LENGTH INSTY~UCTIONS THE SEC01\lD OPERAND IS
HELD IN GORE :Y}ENORY.
T,JHEN THE INSTRUCTION LEN(3TH IS SINGLE, THE FPU
HARDt·JARE ACClE'·1Ul.ATOR IS USED AS THE SECOi\JD OPERAND.
,;
IN FLOATING-POINT lVlULTI?LY THE NORMALIZED RESULT HAS THE
>10ST SIGNIFICANT BITS IN THE FP] HAHDr·.TARE ACCUMOLATORAND.'T'j-fE LEAST
SIGNIFICANT BITS IN THE FPU MQ.
THE MQ, A ~6-HIT EXTENSIO~' OF THE
H.A.RDFARE ACCUMULATOR, MAY BE AC~ESSED \>lITH THE DIAGNOSTIC AWD SWAP MQ
Ii"lSTRUCTIONS.
IN INTEGER !.'1ULTI ::>LY, THE LEA'ST SIGNIFICANT·BlTS, OF,!:.
'fHE RESULT ARE IN THE FPU HARD\v~RE ACCTJ'IH.n...ATOR AND THE MOST SIGt\JIFICANT
!'~ITS ARE IN THE FPU tV!O.
]'\1ULTIP~'.. leAT ION IS RETi,'IEEN TyTO 36-BIT OPERAND
PEGISTERS At-JD RESULTS AO?EAR IN THE 36-RIT MANTISSA PORTION OF THE
F'DU HARDl,,1ARE ACGUt-1ULATOR A[\JD TH~ 36-BIT FPU Iv1f-'1.
ROTH FLOATING-POINT DIUIDF: AND INTEGE:P DIVIDE RESULT r!TITH
TJ-lE gUOT I ENT IN THE 36-.8 IT l'v1ANT I SSA PORT ION OF THE HARD'~rAHE ACCUMULATOR'.'
t-Y\]1) THE REMAINDER IN THE 14Q.
IiJTEGER DIVISION I S ~IJHOL.E: l\TUMBER
DIVISION.
IF THE: DIVIDE:ND IS L~:SS THA.N THE DIVISOR, THE QUOTIENT

r'l THE FPU.

IS ZERO.

PROGRAM INTERRU?TIONS:
OVERFLO~·1

- >lAG~\1 ITUDE OF RESULT :i~X:~F:EDED t'1AXH"1Ul\1 REPRESENTABLE
Ni.H'-1BEH L I ;VI IT.
Ui\TnEBFI..O~ll - t4AGN ITUPE O}t. . RESULT EXCF:EDED MIN IMTJM REPRESENTABLE
NUfv1BER L IiYi IT.

DIVIDE -

DIVISION BY ZERO IS ATTEMPTED.

(PAGE A2)
ADD

THE SECOND OPERAND IS ADDED TO fHE FIRST OPERAt\JD,
PLACED IN THE FIRST ODERAND LOC~TIO\l.

AND THE SUM

PROGRAM INTERRuoTIONS:
O\iDERFLO~.'J

oVF.RFLOltJ
SUBTRACT
T HE SECOND O?ERAND IS SURTBACTE) FHO:v), THE FIR ST OPERAND,

A;\JD THE

DIFFERENCE IS PLACED IN THE FIRST OPERAND LOCATION •..

PROGRAM INTERRuoTIONS:
U:\JDEHFLO',!
OVERFLOl.]

REVERSE SUBTRACT
THE FIRST OPERAND IS SUBTR.4CTED FROf.vj THE SECOND OPERAND, A:\JD THE
DIFFERENCE IS PLACED IN THE FIRST OPERAND LOCATION.
PROGRAM

INTERRU~TIONS:

T.iNDEHFLOV
OiJERFLOl.T
MULTIDLY

T~~

i>?'OD'.lCT OF MULTIPLIER (THE SECOND OPERAND) AND MULTIPLICAND

(THE FIRST OPERAND) REPLACES TH;!: MULTIPLICAND.
~~OGRAM

INTERRU?TIONS:
'.J \JDERFLor,11
JVE'RFLOt~J

DIVIDE
F'Ht'.: !)Ii;T~:~.~>'i-~.· r'r4:-:'~ lTICfS'!, rJPEPA:'~~;f)) IS DltIIDJE:n BY TH£ T71\TiIsarp?(THg
SECOND OPERAND) AND REPLACED qy THE QU:JTIENT.
THE REMAINDER IS LEFT

IN THE Mq.
PROGRAM INTERRUPTIONS:
U~\lDERFLOt,·!
OVERFLO~lj

DIVIDE

(PAGE A3)
R~;VERSE

DIVIDE

THf.~

DIVIDEND (THE SECOND OPERAND). IS l)IVIDED BY THE DIVISOR (THE
FI'RST OPERAND).
THE QUOTIENT IS PLACED IN THE FIRST OPERAND LOCATION.

PROGRAM INTERRUPTIONS:
r1N DF.HFLOH
OVERFLO-r. J

DIVIDE
LOAD
THE SECOND OPE'R_I.\ND IS PLACED Ii-J THE FIRST OPERAND LOCATION.
13-17~

M, OPERATE ON THE SECOND OPERAND PRIOR TO THE LOAD.
THESE HITS CREA'rES A StT~SET OF i.... OAD INSTRUCTIONS:

BITS

USE OF

LOAD ROUNDED

LOAD POSITIVE
LOA.D NEGAT IVE
LOAD GOt4PLEi:4ENT

PROGRAM INTERRUPTIONS:
O\1ERFLO\~T

(OCCURS ONLY ON LOAD H)UNDED)

STORE
THE FIRST ODERA~'JD

IS STORED AT

rHE SECOl\JD OPERAND LOCA.TION.

OPERATE ON THE FIRST )PERAND PRIOF TO THE STORE.
THESE ~ITS CREATES A SUBSET OF STORE INSTRUCTIONS:
13-17~M~

BITS
USE OF

STORE HOUNDED
STORE POSITIVE

STORE NEGATIVE
STORE COMPLE'MENT
PROGRAM INTERRUPTIONS:
OVERFLOt,] (OCCU'R.s ON STORE ROUND~D AND \,JHEN POS I T I VE EXPONENT '81 TS
ARE LOST ON SINGLE PRECISION STi)BE)
TJNDEHFJ...Ot.! (NEGATIVE EXPO[\TENT BITS LOST ON SINGLE PRECISION ,STORE>'

NOTE:

LOAD ROtJMDED AND STORE FV)UN'DED CHANGE DATA PRECISION FROM
DOUBLE TO SINGLE BY ADDING 0(iJ00i~0:iJ00400 TO THE MANTISSA A'\fD

RE~\lORMAL I Z IN G.

(P~GE

A4.)

F'LnA.T

TH'~:

nATA FOP~·lt\.T OF THE srO:COhlD ()PERi~;\JD IS CHANGED FRO~I\ I:\JTEGER 1'''0
Fl..OA.T lNG-PO IN1.'.
THE: SECO~JD OPERA.ND I ~ A 1 g Ol:? 36-BIT INTEGER.
THE
?i;:Sf.iLT IS PLACE\) IN THE FIRST OPKRA\JD LOCATIor'J.

T',;'~~

1).-:1 T ,(\

IL'.1TE(3E1=?

F'OP;"~:,~T

OF THE SECO[\1D OPEHAND IS CHfl.;\iGED FBorli F'LOP'.T !NG-PO INT
PESTJLT IS A 1B OR 36-BIT INTEGER A!\ID IS PLACED IN THE
FIRST OPE?AND LOCATION.

PQOGRAM
OiJERF'LOH

TE~:

INTSBRU~TIONS:

(8IGf.\JIF'ICANT BITS LOST ON FOHNAT CHANGE)

D I AGi\lOST I r;

T"\-·IIS Il\JSTo,UCTION ~'.7iLL BE IMPLE""1ENTED TO DIAGNOSTIC PROGRA·~M!i\iG
SPECIFICA,TIOl\lS.
IN GENERAL .. IT \·.1ILL F.:!\jABLE THE DIAGNOSTIC ?ROGRA~1MER

TO ~PT THE FLOATING-POINT UNIT IN SINGLE-STEP CHECKOUT MODE AND
PROt/IDE ACCESS TO ALL ESSENTIAL CONTROL CIRCUITRY AND HAHDt\!ARE
PEGIST}O;:RS. 'THIS INSTRUCTION tIJI·... L ALSO SERVE T'·10 OTHEB FUNCTIO\\1S.
FIBS!, IT t~lILl... ALLOT,., TJSER INFOR¥1ATION IN THE F'PU TO BE SAVED OR
S~STORED

~ITH A SINGLE INSTRUCTION.
SECOND~ IT WILL BIVE ACCESS TO
INTERRnpT EXCEPTION REGISTEHtHHICH l'1AY BE EXA.MIl\JED TO DETERMIN
THE CA!JSE OF THE FLOATING-POINT INTE'RRUPT.
f~N

THE 36-BIT MANTISSA PORTION OF
36-BIT FPU MQ AHE S\vAPPED.
PROGRAM

INTERRUPT IONS:

NOt\lE

rHE FPU HA.RUT,JARE ACCUMULATOR AND THE

APPENDIX B

Ol;~~RFl..O'~i ('V1AGNITUDE OF 'RESULT EXCEFr)r-:T) 'v1AYIMUi'ij BFoPF.SEI\lTABLE
;\lU1BER LlYJTT.

rr·\JD1:;:nFLOf.i - 'i>1,~n'\J!TO))E: OF RESUl.T EXC'SF:DED MI;\JIM1P-1
\JrT:v18ER L !i'1 IT.
nT\lIn~
iTH~:;\J

A;'-j

7y..~P')

DT,rJc;r·)N nv
I\1Tj:."'l~~Pfj·:>T

.'\TTTO;·"1,~TIC4LLY

PEPh'F:SFi\~TA~LF:

IS ATTEtvIPTF.D.

E:Y~E0'T'TON

occnps ..

FORCES THE CPU TO

.)\'-IJ5

~';{t~CUTIO\l
STOoS ANT) TH~~ FOii
TO THE EXIT L\nnRES~.
THE EXIT

ADDRESS IS K~OT IN ~ 1s-nIT PEGISTER IN THE FPU, WHICH CAN BE ACCE5SED
ny THE PROGRAMM~R THROUGH USE OF THE DIAGNOSTIC I~STRUCTION.
UPON
CO;-1PLF.TI O\i THE

i~XIT

AnnR.~SS

I...OCA.TION r.lILL
I \JSTP,OCT ION

THF LAST HORD OF' THE L.AST FPU

A
A+l
E~IT

ADDRESS LOCATION

l·TI LL CO(\JTA 1(\1 ".4+3"

A+2
A+3

•
•

CO~TAIN

EXECTJTi~D

THE P-DDRESS OF
Pl.TJS Tl.tlO.

FLo.AT. ADD
ADDFESS OF ARG.

LAC 8
DAC C

•

PPEsrF'J!.\BLY, THE EXIT ADDHESS WI '.:.L PO INT TO THE ERROR HANDL ING
HOUT INE I,'OR FLOI\T H\l G-PO INT.
TH!: l) I A Gi\l 0 5T I C IN STRUCT I ON 'MAY BE USED
TO LOOK AT THE STATUS OF THE OV~RFLOH, UNDEHFL.O~~7, A[\JD DIU I DE

INTERRUPT FLOPS AND 'THE INSTRucrION LENGTH OF THE INTERRUPTED
I \J STRUCT I Ol'J.

(PAGE Cl)
APPE~DIX

OPERAT It'JGFEATtJHES AND C,)(\lSTRAIMTS
-~~---~--

~----~~~

~-~

-~~~-----~-

{v1 A. X I MU:f.l OF ONE: LEVEL OF INDIFECTION

OPl':RANDS t-1UST BE NORi'1AL. I 7,ED
RESULTS ARE ATJTOMATIC.Al..LY NOR\1ALIZED
IF A CALCPLATION RESULTS IN A ZERO lvIAGNIT(TDE, THE EXPONEr-lT
lERO'D AND TH~ SIGN MADE POSITIVE
NJ~GAT IUE ~E'10 I S NOT A.LLO'\tTED
THE ADDRESS OF' THE ARGTJMENT I S A l 7-BIT NUMBEF

ROUNDING TAl<:E';; PLACE AI:7TER ALIGNING AND AFTER

NOR~IJ.ALIZING (+1 IS
ADDED TO THE LEAST SIGi\TIFICANf BIT OF THE MA;'JTISSA IF THE NEXT
~IT OFF THE LSR END OF THE MA~TISSA IS 1)
I/O i·1E~v1U'RY REqUESTS ABE GIVEN PRIO~ITY OVER FPU ME~10RY REQUESTS

- THE PROGRAMMER MAY LOAD A 15-9IT REGISTER IN THE FPU WITH AN
INTERRUPT EXIT ADDRESS.
WHEN A FLOATING-POINT INTERRUPT OCCURS~
THE FPU AUTOMAT I CALl'::' V FORCES THE CPU TO JMS TO THE EXIT ADDRESS.
THE EXlT ADDRESS LOCATION WIL~ CO~TAIN THE ADDRESS OF THE LAST
FPO INSTRUCTION EXECUTED PLUS Tf~TO.

F:.G.
F-.:l(J

INTERRUPT OCCURS

EXIT ADDRESS LOGAT!ON
ILL CONTAIN "A+3"

FLOAT. ADD

A+l
A.+2
A+3

.ADDRESS OF ARG.
LAC B

llj

•

DAC C

•
•

(PAGE D1)
APPEMDIX D
J:--:'KAM~LE

PROGRAM COD ING

OF CODES USED:
;"1NEMONIC:

AD
LD

STD
q~1C~ 1 ~10
~1 r,) f} 1 ~'{~

LOAD=20, ADD=3~, STORE=70
DOUJ3LE PRECISION FLOATING-POINT ADD
DOIJBLE FREe I S 10:\1 FLOAT ING- PO INT LOAD

DOU$LE
;;>

PRECISIO~

FLOATING-POINT STORE

.LOC
TAD

10C.1
DATAl

DAC

STOR

NUMl

:. ) n 1 t~ 1

CJ (.~) ~.,:, 1 ~i) 2

3lH1112
k,)L! C'111 3
7123'4[1

r,) (.~ 0) 1 0 ~

()n01 1/-1

1 (7) 4 ;

,71~~7'~0

J.~.D

NUM2

q:l-?' 1 (,15
'-1(1(/)106

00:1}117
71 73/~0
00';1122

srD

.ANSH

2(1(~125

LAC

DATl\2

~JMP

r~}

(l(,)(~

v1f-F1107
000110
0) Qjf,;j 111·
0(1:1112

6f.J0126
1711107

'1'"1'1113

(1f1f100r.:)

DATAl
STOR

:0;, (!jf,11 111

(10(~~}Lt7

NUMl

(.7)01:'1115

36/1211

(1(1011 (,

37~648

000117

(il~10036

ICPU 1i\1 STR,UCT ION
ICPU INSTRUCTIOl.\!·
IDOUBLE PRECI SION F.P. LOAD
IASSEi-1BLES INTO TTJ,O IB-BIT \tJORDS

IDOUBLE PREC~SION F.P. ADD
I ASSEI'lBLES INTO THO 18-8 IT 1,.,ORDS
/DOUBL.E: PRECISIOi\}F.P. STORE
IASSEMBLES INTO T~"O 18-BIT vlORDS
ICPU INSTRUCTION
.
ICPU INSTnUCTION

101127
0

47
36l~~ 1 1

IEXPONENT
ISIGN AND HIGH ORt)ER MAl'JTISSA

373642

ILOW ORDE? MANTISSA

NUM~

36
207416
[177135

I EXpnr·.jENT
I SIGN AND HI GH ORDER l'4ANtI S5.A

.ANS\\i

0vH~120

~H~ 7!~ 16

(1(,:)(11'='1
(.JvH1122

477135
(.) (ij 0 ~J (!i fij

O(~0123

[.1(1)00v)0

(.11i1f-1 t 2 L!

O~1(i)()J0(1

q0'~ 125

Of:;100fi11

C:H;Jr~ 126

7 Lt. 0. (~ (i) 0

DATA2
·NEXT

/LO~'i OBDER tv1ANT I S~,A
IEXPONENT
ISIGN AND HIGH OPfiER tviANTtSSA
ILOH . ORDER MA't\JT I SSA

ICPU. IMSTRUGTION

•
•
WHEN TH~ INSTRUCTION AT LOCATION 000102 IS FETCHED, THE
PORDi 7123LH~, I', A NO-OPER,ATION IN THE CPU.
HO~ljE\lER, THE FPU
IMMEDIATELY HECI)GNI~ES THE "71" AS A FLOATING-POINT INSTRt':CTION
WORD.
AT THIS TIME; THE FPU DISABLES THE CPU FROM MAKING FURTHER
~"IEMORY REQUESTS, AI,,1}) THE REST OF THE FLOATING-POHJT INSTFH.ICTION
IS DECODED - 2340.
SINCE L=I# THE CPU IS ALLOWED TO MAKE ITS NEXT R~QUEST TO
l;\-lEY10FY.
THE CPU NO,\·, THINKS IT ISFETCHH\1G THE r\jEXT Il\iSTRt1'CTION
FQOM LOCATIOi\l 0f1tfJ103.
THE CONTENT OF 000103 IS REALLY l'ijEP·,NT rOBE

THE SECOND OPEBAND ADDRESS FOR fHE FLOATING-POINT INSTRUCTION.

CONSE~UENTLY, THE CPU Mus'r NEVER SEE THE uGARBA.GE" INSTRUCTION IN
00(,11(13.
THIS IS ACCOMPLISHED BY DISABLING THE CPU FROM STROBING
THE CONTENTS OF 00(1) 103 INTO ITS RUFFER.
RECAUSEOF ·THE "ST IMULUS-

(PAt3E D2)
RESPONSE" OPEPATION OF TFE CPU 'tlITP CORE tl.£EMORY, THE CPU ~JlILL l,..1AIT
IN LIMBO UNTIL IT IS ALLJ,,,TED T:- 5TROR;- THE MEMORY BUS IN,TO ITS
RUFFEP.
MEA>.\it'~HILE tHE FPU TAKE S OliER l~jHERE THE CPH LEFT OFF.. STROBES
THE CONTENT ,~~' 0001(,11 INTO THE F'PTT BU~"FER.. AND I SSUES THE NECESSARY
ACKNO~I.TLEDr,'ft: SIGNALS TO END THE MEt'4'IRY CYCLE.
A DtJf.4MY NO-OPERATION
I\iSTRUCTIO;\J r·TORD IS THEN PFT (}l\i THr~ MEMORY BUS BY THE FPU, FOLLOl~TED

ny A ST~OqE

~IeNAL

TO THE CPU.

THE

F~U

NO~

PLAYS THE ROLE OF A

CORE RANK I\l\ir) ! SSUE5 THE i.\lECES (A'RY SIGNALS TO THE CPU TO END THE
CYCLE.
AG'~It\1 .. THE FPU DISABLE!; THB~ CPU FROtvl MAKING A MEMORY

BEQUEST.

OP CODE
2'?l I~ A LOAD INSTpnCTION.
P
1 .AND F = 1,
COl'1PLI<::TE THE DESCRIPTIOi\J OF THE INSTRUCTIOi\J .. LABELING Irr DOUBLE
PHECISIO[\J FLOATING-POINT.
THE DESTINATION OF THE LOAD IS A 5Lt-BIT
F1'U HARDT']AR.E ACCUMULATOR.
THE Dr:STINATION ACCUtV1ULATOP. IS LOADED \·TlTH
THE EXPONENT .. SIGN AND HIGH OH')F'~ MANTISSA, Ar\JD THE LO\tT OHDER MANTISSA·
FROM LOCATIOl\lS 000114, f,J(ij0115 .. AND "(,1(1116 RES?ECTIVELY.
THE COr\]rENT
OF R['J01{!13 IS THE SECOND OPERAN·')~DDHESS.
SINCE BIT (~}=0, THERE IS NO
INDIRECTION .. A\JD THE EFFECTIVE- ADDPl4.:SS IS SIMPLY 0013113.
,.1HEN THE
INSTRUCTION IS FINISHED, THE C=>U IS ENABLED FOP MElv10RY ''REQUESTS A.t\JD
THE NEXT ~O~D FETCHED BY THE C~U IS FROM LOCATION 000104.
THE OTHER
FLOATING-POINT iNSTRUCTIONS ARE EXECUTED IN A SH-1ILA.R C>1ANNER.

NOTE:
1/0 MEMQRY REQUESTS ARE GIVEN PRIORITY OVER FPU REQUESTS
TO MEMORY.