Digital PDFs

EK-DUP11-OP-001

May 1976

60 pages

Original

2.9MB

view download

OCR Version

2.6MB

view download

Document:	DUP11 Bit Synchronous Interface User's Manual
Order Number:	EK-DUP11-OP
Revision:	001
Pages:	60
Original Filename:

OCR Text

DUP11 bit synchronous
|
interface
user’'s manual

EK-DUP11-OP-0061

DUP11 bit synchronous
interface

user’'s manual

digital equipment corporation - maynard, massachusetts

1st Edition, November 1976

Copyright © 1976 by Digital Equipment Corporation
The material in this manual is for infermational
purposes and is subject to change witheut notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this

manual.
Printed in US.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

PDP

DEC

DECtape

DECCOMM

DECUS

RSTS

DECsystem-10

DIGITAL

TYPESET-8

DECSYSTEM.20

MASSBUS

TYPESET-11
UNIBUS

CONTENTS

CHAPTER 1

INTRODUCTION

1.1

SCOPE

1.2

DUP11 GENERAL DESCRIPTION
SDLC AND DDCMPPROTOCOLS

1.3

Introduction

1.3.2

General Information

1.3.3

SDLC Protocol Description

1.3.3.1

Message Format

1.3.3.2

1.34

1.3.4.1

. .. .. . . . ...
. . . . . . . . . . oo
e e e e e e

e e e e e e e e

e e e e

. . . . . . . . i

1.3.1

e e e

e e ee

e e e e e

. . . o o e e e e e e e e e e e

oo n e

. . . . . . . . . ..o

oo oo

. . . . . . . . . o

o oo

. . . . . . . . . . ..

. . . . . . ...t o o e
. . o v i e e e e e e e e e e e e e e
.
.
.
Protocol
DDCMP
. . . ... ...............
~ Controlling Data Transfers
Abort Sequence

... ...

Error Checkingand Recovery . . . . . . . .. . ...
. . . . . . . . ¢ o i i v i i i
e
. . . . « « « v v v v v e
Data Transparency

1.34.2

CharacterCoding

1.3.4.3
1.3.4.4

e e e e

1.3.4.6

.
. . . . . . . . . .« .. ...
Data Channel Utilization
. . . . . . . . ... oo
Synchronization

1.3.4.7

Bootstrapping

1.3.4.5

CHAPTER 2

INSTALLATION

2.1

SCOPE

2.2

UNPACKING AND INSPECTION

. . o

. . ... ... ... .....

PRE-INSTALLATION SET UPPROCEDURES

INSTALLATION

. . .

2.5

VERIFICATION OF HARDWARE OPERATION

2.6

COMPATIBILITY

. . . . o

2.8
2.8.1
2.8.2
2.8.3

29
29.1
2.9.2

293

e i e e e e e e e

. . . . . . o v it

2.3

2.7

. . . . ... .. .. ...

e e e e e e e e e e e e e e e e e e e e e

Intfroduction

. . . . .« . it e

Introduction

. . . . . . .

. . . . . . . .. .. .. ... ..
Floating Device Address Assignments
e
e e
oo
. . . ..
.
.
.
.
.
.
.
Selection
Address
Device
e
e
e
e
e
e
e
e
e
e
e
e
e
VECTOR ADDRESSES . . . . . o

Floating Vector Address Assignment . . . . . . ... . ... ... ...
. . . . . . . . . ..o oo o e e
Vector Address Selection

MAJOR OPERATING FEATURES

3.14

Introduction

. . . . . . .

. oo

. . . . . . . ..

e e e e e e e e e e e e e e e e e e e

e e e e e e e e e e e e e
e
. . . . . . . i i
Modem Control
e
. . . . . . . . i e e e e e e e e e e e e e
Transmitter Section
e e e e e e e
. . . . & v v i i e e e e e e e e e e
Receiver Section

3.2

DUP11 REGISTERS AND DEVICE ADDRESS SELECTION

INTERRUPT VECTQORS

J.0

e e e

e e e e e e e e e e e e e e e e

3.1

3.1.3

e e

e e e e e e e e e e e e e e e e

OPERATING FEATURES AND REGISTER DESCRIPTIONS

3.1.2

vii oo
e e e e

v
. . . . . . . . . .
POWER REQUIREMENTS
e e e
e
e
e
e
e
e
. . . . . .
DEVICE ADDRESSES

CHAPTER 3

3.1.1

e e e e e e

e e e e e e e e e e e e e e

. . . . . . . . . . 0

..
. . . ...
-

CONTENTS (Cont)
Page

3.4

PRIORITY SELECTION

3.5

APPENDIX A

PDP-11 MEMORY ORGANIZATION AND ADDRESSING CONVENTIONS

. . . . . . . . . . . . .

. . . . . . . . . . .. ..

3-8

. . . ...,

3-8

ILLUSTRATIONS

Title

Figure No.

Page

1-1

SDLC Message Format

1-2

DDCMP Data Message Format

1-3

DDCMP Sample Handshaking Procedure

2-1

Redefining Secondary Transmit and Receive Lines

. . . . . . . . . . . .. .. ... .. ... .. ...
. .

. .

. ..

.. ... .......

. . . . .. ... ... .. .....

1-3
1-5

1-6

. . . . . ... ... ...

2-3

. . . . . . . ... .. ....

2-2

DUP11 (M7867 Module) Mounted in DD11-B

3-1

DUPI11 Register Configurations and Bit Assignments

3-2

Receiver Control and Status Register Format

3-3

Receiver Data Buffer Register Format

. . . . . ... ... ..

. . . . . . ... ... ... .. 3-15

. . . . .. .. .. .. ... ...... 3-18

Parameter Contrel and Status Register Format

3-5

Transmitter Control and Status Register Format

3-6

Transmitter Data Buffer Register Format

. . . . ..

... . ... ... 3-20

. . . . . ..

.. ...
.. 3-26

. . . . .. . .. .. ... ... .. 3-30

TABLES

Title

Table No.

Page

2-1

M7867 Jumper Configuration

2-2

Guide for Setting Switches to Select Device Address

. . . . . .. ... ...

2-7

2-3

Guide for Setting Switches to Select Vector Address

. . . . .. .. ... ..

3-1

DUPLI1 Registers

. . . . . . . . . . . . e

3-8

Bit Descriptions for Receiver Control and Status Register (RXCSR)

3-3

Bit Descriptions for Receiver Data Buffer Register (RXDBUF)

3-4

Bit Descriptions for Parameter Control and Status Register (PARCSR)

. .

3-5

Bit Descriptions for Transmitter Control and Status Register (TXCSR)

. . . . 3-21

3-6

Bit Descriptions for Transmitter Data Buffer Registet (TXDBUF)

. . . . .. . ... ... ... ... ...,

2-2

. . . . . 3-10

.. ...
. .. 3-16
. . 3-19

...
. .. 3-27

CHAPTER 1
INTRODUCTION

1.1

SCOPE

This manual provides the user with the information necessary to install and operate the DUP11 Synchronous
Line Interface. The manual is organized into three chapters and one appendix.

Chapter 1 - Introduction
Chapter 2 - Installation
Chapter 3 - Register Description
Appendix A - PDP-11 Memory Organization and Addressing Conventions
This chapter provides a general description of the DUP11 and a general discussion of the Synchronous Data

Link Control (SDLC) protocol and Digital Data Communications Message Protocol (DDCMP).
1.2

DUP11 GENERAL DESCRIPTION

The DUPI11 provides a data path between a synchronous modem and the Unibus. It operates under the discipline

of SDLC, ADCCP, DDCMP, and other similar protocols. Protocols of the BISYNC family can be used with
some loss of efficiency due to the additional software decisions required.
The DUPI1 provides parallel-to-serial conversion of data to be transmitted and serial-to-parallel conversion of
received data. Logic 1s provided to create a transparent data stream and to compute a CRC check character
during transmission. All information is handled in 8-bit bytes; VRC parity is not provided. CRC error detection
is provided during reception. Modem control and level conversion logic is provided also.

Interrupt control logic is used to generate requests for the transfer of data between the DUP11 and the PDP11 system memory via the Unibus. No direct memory access (DMA) logic is contained in the DUP11.
The DUP11 contains logic to perform the following functions.
1. Program control of secondary station address recognition. Primary station operation is used as the
default condition. (SDLC protocol family only.)
2. Programmable SYN character recognition (DDCMP and BISYNC protocol families.)
3. CRC characters computation and error detection. (SDLC and DDCMP protocol families.)
4. Automatic transmission of flag characters initiated by the program. (SDLC protocol family only.)

5. Program control of transmission of abort sequence and 16 zero sequence. (SDLC protocol family only.)
6. Hardware detection of received flags and abort sequences. (SDLC protocol family only).

The DUPI1, including level conversion, is contained on a hex module. The DUPI11 is connected to the modem
via a BCO5C cable and a BCO2 cable that support RS232-C specifications only. Current mode operation is not
supported by the DUP11 and it is not compatible with the DF11 series options.
The modem control logic is compatible with Bell 201, 208, and 209 series modems. There is no interlock between
the transfer of data and modem control. The program controls handshaking with the modem, if it is required.
Once the handshaking has been completed, the program can initiate the transfer of data. The modem control
logic includes secondary receive and transmit leads. These leads can be redefined by the Field Service engineer at
the user’s request (refer to Chapter 2, Figure 2-1).
1.3

SDLC AND DDCMP PROTOCOLS

1.3.1 Introduction
This discussion provides a general description of the SDLC and DDCMP protocols. It is the prerequisite to
a thorough understanding of the operation of the DUP11. Details of the SDLC, DDCMP, ADCCP and BISYNC protocols are found in the following documents.
2. Digital Data Communications Message Protocol (Digital Equipment 130-959-007-02)
3. IBM Binary Synchronous Communications General Information (GA27-3004-2)
4. ADCCP ANSI X3S34/475 DR7
5. ADCCP ANSI X3S34/584 DR1
1.3.2

General Information

Although the mentioned protocols are not identical, they are similar enough to operate with the DUP11.

The program directly controls the DUPI1 operation through the use of control and status registers. The program must provide a continuous flow of data to be transmitted. No intra message fill characters are allowed.
The program must also service the receiver data buffer within the prescribed time.

When transmitting in the SDLC or DDCMP family of protocols, the program must form the address and
command fields plus any other header information that is required. The program must maintain the transmitter data buffer and set marker bits to delimit the transmitted message.
When receiving in the SDLC or DDCMP family of protocols, the program must interpret the header information, service the receiver data buffer, and monitor the status bits associated with the received data.
Protocols such as BISYNC that achieve transparency by using special control characters are less efficient
than SDLC and DDCMP when used with the DUPI11. This occurs because of the increased program involvement required to maintain transparency and compute the CRC character. The CRC control logic in the

DUPII is not suited to protocols in which special control characters appear within the body of the message.
For these protocols, the CRC logic should be disabled by setting the NO CRC bit (PARCSR bit 9).
1.3.3

SDLC Protocol Description

1.3.3.1

Message Format

The CNT TM mmaogenge Farmat ia chAw
1V

OLs

LHVODdAaRV

1UlIlidt

ture for all transmissions.

diluw

FiLAG

ADDRESS

CONTROL

INFORMATION

01111110

8 BITS

8BITS

VARIABLE LENGTH

FRAME CHECK SEQUENCE
16 BITS

FLAG
01111110

11-3430

Figure 1-1

SDLC Message Format

The frame starts with the 8 bit flag sequence, 01111110, followed in order by the Address sequence, Control
sequence, Information sequence (if present), Frame Check sequence, and ends with another Flag sequence. In
some applications, the flag is preceded by a sequence of 16 zeroes.
Each sequence in the frame is discussed below with emphasis on related operational features of the DUP11, if
applicable.
FLAG CHARACTER

The flag character is a unique 8 bit character of the form 01111110. Flag characters are used to delimit the
message. They can be used to fill in between messages but cannot be used as fillers within messages. When
the transmitter initiates the start of a message by asserting the TSOM (transmitter start of message) bit, the
initial flag character is automatically transmitted. If the TSOM bit is still asserted at the end of the 1st flag
character, another flag character is transmitted. When the TXDONE (transmitter done bit) is asserted by the

DUPI11 subsequent to the program’s asserting of the TSOM bit, the program may respond by leading data
into the TXDBUF (transmitter data buffer) low byte, or leave the TSOM bit asserted and send another flag.

In some applications, the TSOM and TEOM bits are used to initiate a sequence of 16 Os. This sequence can be
initiated only from the idle state. To transmit this sequence, SEND must be asserted and TXACT must be
cleared. With these requirements met, the program simultaneously sets TSOM and TEOM, and the 16 Os are
transmitted. When the first 0 bit is presented to the serial output, TXDONE is set. Now, the program should
clear TEOM and, on the next transition of TXDONE, the program should clear TSOM. The first data character
can be loaded now. This point marks the start of the initial flag character. The first data character is transmitted
subsequent to the current flag character.
When the last character of a message has been loaded into the TXDBUF, that character is then transmitted.
Subsequent to loading the last character, the TXDONE bit is asserted again by the DUP11. This marks the start

of the transmission of the last character. At this time, the TEOM (transmitter end of message) may be asserted in

the upper byte of the TXDBUF. The character currently being serialized (i.e., the last character of the message) is
transmitted and followed by a CRC check character and the terminating flag character. This
concludes the message.
When the receiver logic is enabled by the software, it searches for flag characters. If the basic SDLC or

ADCCP message format is followed and the receiver is programmed to operate in the secondary mode, the
following actions occur.
The eight bits after the last received flag are compared to the secondary station address. If a match is not
found, the receiver continues to hunt for a flag. When the next flag character is located, this comparison of
addresses is reiterated.
If the character subsequent to the flag character matches the secondary station address, then characters re-

ceived subsequent to the address character cause the RXDONE (receiver done) bit to be asserted. The
RSOM (receiver start of message) bit is presented to the program along with the first data character.

When the secondary station receiver is actively transferring data, the following events occur when a termi-

nating flag character is detected. The receiver logic automatically resumes the address search as cited earlier.
Also, a status entry is made into the receiver data buffer, the REOM bit is asserted and the CRC error bit is
set if an error was detected. The lower byte of data in this entry is invalid.

1-3

When the receiver logic is programmed to operate as a primary station, all characters subsequent to the last

received flag character cause the RXDONE bit to be asserted. The first character of the frame is accompanied by the RSOM bit.
When the terminating flag character of a message is received, primary station operation is the same as cited
above for secondary station operation. When the next data character is received, the receiver logic again sets the

RSOM and RXDONE bits. The last two bytes preceding the flag were the receiver CRC bytes.

ADDRESS CHARACTER
The address character appears subsequent to the flag character and is eight bits long. This format supports a
maximum of 256 addresses.
The protocol has provisions for the recursive expansion of the number of addresses. This feature is not supported by the DUPI11 hardware. It must be maintained by the program.
In the secondary station mode, the program must load the address of the receiving station into the low byte
of the PARCSR.
CONTROL FIELD
The 8-bit control field follows the address character. This field is controlled by the program and is encoded
to indicate the commands and responses to control the data link. This field has three formats as described
below.

Nonsequenced Format — This format is used by the primary station primarily for data link management.
Such duties include activating and initializing secondary stations, controlling the response mode of secondary stations, and the reporting of procedural errors.

Supervisory Format - This format does not contain an information field but it is an adjunct to the informaion format. It is used by the primary station to poll the secondary stations. The secondary stations

use this format to provide acknowledgment to the primary station.
Information Format - This format is used by primary and secondary stations for the transfer of information fields.
INFORMATION FIELD

This field is used for the transmission of data or status information. This field contains an arbitrary number of
characters as specified by the documents covering the protocols. The DUP11 handles the data in this field as eight
bit characters.

When one character is transmitted from the transmitter shift register, another character is taken from the data

buffer. If the data buffer is empty, the transmitted data lead goes to a mark hold state. Also, a status bit is
asserted to indicate the data underrun condition in SDLC or ADCCP and an abort character is automatically

transmitted.

There are no restrictions on bit patterns that appear between flags in an SDLC frame. Therefore, the trans-

mitted data may contain six or more contiguous 1s and this pattern could be interpreted as a flag which

would inadvertently terminate an incomplete frame. To prevent this action and to maintain data transparency, the DUP11 contains O insertion and 0 removal logic that is active on all characters between the

flags. During transmission, when five contiguous 1s occur, the transmitter automatically inserts a 0 after the fifth

I. During reception, the 0 after five contiguous 1s is automatically removed. This applies to all fields except the

flag.

FRAME CHECK SEQUENCE (FCS) FIELD
This 16-bit field follows the information field and is also referred to as the Block Check Character (BCC) or
CRC check character. It is used in all SDLC frames to detect errors.
Logic to compute CRC check characters is included in the transmitter logic. Similarly, logic is included in
the receiver logic to check the results when the check character is received. This operation of computing and
verifying the CRC check is transparent to the program. Any error in the computation of the received check
character in SDLC type protocol operation is indicated by a status bit in the receiver data buffer. If
DDCMP operation is selected, the program must monitor a status bit to detect the desired accumulated
results.

Two CRC polynomials are supported by the DUP11. They are CRC 16 and CCITT. When the SDLC or

ADCCP mode of operation is selected, the CCITT polynomial is used and the internal CRC registers are effectively initialized to all 1s. During transmission, the complement of the accumulated CRC character is sent. If the
SDLC or ADCCP mode is not selected, the CRC 16 polynomial is used, providing CRC checking is not
inhibited.

1.3.3.2

Abort Sequence

An abort is the premature termination of a data line by the transmitting station. An abort is detected by the
reception of more than seven contiguous Is.
When the abort sequence is received, the message in progress is terminated. A flag (RXERROR) is set and

RXDONE is set also. If the program has set RXITEN, an interrupt request is generated when RXDONE is set.
A transmitting station can send abort sequences under program control by setting the TXABORT bit.
If the program response time to the TXDONE bit is excessive, the TXDATLAT bit is set and the transmitter
idles abort characters.
1.3.4

DDCMP Protocol

DDCMP (Digital Data Communications Message Protocol) was developed to provide full-duplex message

transfer over standard existing hardware.
1.3.4.1

Controlling Data Transfers

The DDCMP message format is shown in Figure 1.2. A single control character is used in a DDCMP message, and is the first character in the message. Three control characters are provided in DDCMP to differentiate between the three possible types of messages:
SOH - data message follows
ENQ -control message follows

DLE -bootstrap message follows.
Note that the use of a fixed-length header and message size declaration obviates the BSC requirement for exten-

sive message and header delimiter codes.

SYN

SOH

COUNT | FLAG
14 BITS | 28BITS

8BITS | 16 BITS

DATA

CRC-2

(ANY NUMBER OF 8-BIT
CHARACTERS UP TO 214)

16 BITS

11-2897

Figure 1-2

DDCMP Data Message Format

Figure 1-3 shows a simple example of data exchange between the DUP11/PDP-11 and a data terminal. More
efficient procedures can be derived after a study of DDCMP.

1-5

TERMINAL

DUP11/PDP-11

Sends 2 STRT (START) message which
means:

*l want to begin sending data

to you and the sequence number of my
first message will be 1.”

\ @ Receives STRT message.
@ Sends a STACK (Start Acknowledge)
message which means:

“OK with me;

here is the first sequence number (5) [

will use in sending data messages to you.”

Receives STACK.
Sends Data Messages with a response field
set to 4 and the sequence field set to 1,
which means:

“l am looking for your

message 1.7 Other messages may be sent
at this time (i.e., messages 2, 3, etc.)

without waiting for a response. \

Receives Data Message 1 and checks it for
sequence and CRC errors. If there is a
sequence error, go to 12, If there is no
error, go to 9.

A CRC error was detected. Computer B
sends a NAK message with the responsc

field set to 0, which means:

“‘All messages

up to 0 (Modulo 256) have been accepted

and message 1 is in error.”
Computer A receives NAK, retransmits
Message | and any other messages sent
since (i.e., 2, 3, etc.) if already sent. \

Sends ACK response of 1 either in a separate
ACK message or in the response field of a
data message.

Receives ACK and releases Message 1.
Continues sending messages.

e @

Times out because of lack of response /
for Message 2. Sends a reply for

Message 2.

Retransmits Message 2 and

following messages.

Discard message and wait for proper
Message 2.

Send NACK response of 1 in the
response field.

Figure 1-3 DDCMP Sample Handshaking Procedure

1-6

1.3.4.2

Error Checking and Recovery

DDCMP uses CRC-16 for detecting transmission errors. When an error
occurs, DDCMP sends a separate
NAK message. DDCMP does not require an acknowledgment message for all data
messages. The number in
the response field of a normal header or in either the special NAK or ACK
message, specifies the sequence
number of the last good message received. For example, if messages 4, 5, and 6 have
been received since the

last time an acknowledgment was sent and message 6 is bad, the NAK message specifies
number 5 which

says “‘messages 4 and 5 are good and 6 is bad.” When DDCMP operates in full-duplex
mode, the line does

not have to be turned around; the NAK is simply added to the sequence of messages

for the transmitter.

When a sequence error occurs in DDCMP, the receiving station does not respond to the message. The trans-

mitting station detects, from the response field of the messages it receives (or via timeout), that the receiving
station is still looking for a certain message and sends it again. For example, if the next message the receiver
expects to receive is 5, but 6 is received, the receiver will not change the response field of its data messages,
which contains 4. This says: “I accept all messages up through message 4 and I'm still looking for message
5.7

1.3.4.3

Character Coding

DDCMP uses ASCII control characters for SYN, SOH, ENQ and DLE. The remainder of the message, including the header, is transparent.
1.3.4.4

Data Transparency

DDCMP defines transparency by use of a count field in the header. The header is of fixed length. The count

in the header determines the length of the transparent information field, which can be zero to 16,383 bytes
long. To validate the header and count field, it is followed by a 16-bit CRC-16 field; all header characters are
included in the CRC calculation. Once validated, the count is used to receive the data and to locate the second CRC-16 which is calculated on the data field. Thus, character stuffing is avoided.
1.3.4.5

Data Channel Utilization

DDCMP uses either full- or half-duplex circuits at optimum efficiency. In the full-duplex mode, DDCMP op-

erates as two dependent one-way channels, each containing its own data stream. The only dependency are
the acknowledgments which must be sent in the data stream in the opposite direction.
Separate ACK messages are unnecessary, reducing the control overhead. Acknowledgments are simply placed
in the response field of the next message for the opposite direction. If several messages are received correctly
before the terminal is able to send a message, all of them can be acknowledged by one response. Only when
a transmission error occurs or when traffic in the opposite direction is light (no data message to send) is it
necessary to send a special NAK or ACK message, respectively.
In summary, DDCMP data channel utilization features include:
2. Low control character overhead.
3. No “‘character stuffing.”

4. No separate ACKs when traffic is heavy; this saves on extra SYN characters and inter-message gaps.
5. Multiple acknowledgments (up to 255) with one ACK.

6. The ability to support point-to-point and multipoint lines.

1.3.4.6

DDCMP

Synchronization

achieves synchronization through the use of two ASCII SYN characters preceding the SOH, ENQ),

or DLE. It is not necessary to synchronize between messages as long as no gap exists. Gaps are filled with
SYN characters. Two sync characters are required, but more are usually transmitted. If synchronization be-

tween messages is deliberately lost by sending PAD (all 1s) characters, the inter-message interval must be at
least 14 character times in length.
1.3.4.7

Bootstrapping

DDCMP has a bootstrap message as part of the protocol. It begins with the ASCII control character DLE.
The information field contains the system reload programs and is totally transparent.

1-8

CHAPTER 2
INSTALLATION

2.1

SCOPE

This chapter provides information for installing and checking out a DUP11 Synchronous Line Interface.
2.2

UNPACKING AND INSPECTION

The DUPI11 comes only in one version called the DUP11-DA. It consists of three items.
M7867 - Bit Sync Interface Module
BC05C-25 - Cable
BCO02-1D - Cable
H325 - Test Connector

Inspect these parts for visible damage. Report any damage or shortage immediately to the shipper and the
DEC representative.

2.3

PRE-INSTALLATION SET UP PROCEDURES

Before installing a DUPI11, the following four functions must be performed.

1. Examine the seven jumpers (W1-W7) on the M7867 module. Refer to the components location drawing
in the M7867-0-1 print set to identify the jumpers. Refer to Figure 2-1 for redefining the secondary transmit
and receive lines.

All M7867 modules are shipped with the standard jumper configuration described in Table 2-1. If a
non-standard configuration is to be used, the parameter dialog must be run prior to running the first
diagnostic.

In any event, all DUP11 diagnostics must be run on each M7867 in the standard jumper configuration.
After successfully completing the diagnostic testing in the shipped configuration, the M7867 may be reconfigured to meet the customer’s requirements. MAINDEC DZDPE (DUPI11 Quick Verify Test) should
then be run to verify operation of the new configuration.

2. The DUPI11 device address must be selected in accordance with paragraph 2.8.

3. The DUPI11 vector address must be selected in accordance with paragraph 2.9.
4. Confirm that a BRS priority card is installed in the module. The diagnostics assume a BRS priority
level. The priority level can be changed. If so, this parameter change must be entered into the diagnostic program.

Table 2-1
M7867 Jumper Configuration
Jumper

Normal

Number

Configuration

Installed

Function

Secondary Receive Enable. With this jumper installed, the state of the data set
Secondary Received Data line is received by the DUP11. This jumper is used

in conjunction with jumper W2. With this jumper removed, pin JJ of the Berg
header is available for some other function.
w2

Removed

Secondary Receive Disable. This jumper must be removed when W1 is installed.

Conversely, it must be installed when W1 is removed. When installed, the EIA
SEC REC receiver input is grounded; however, this has no effect on the Berg
header, cable or data set.
w3

Installed

Clear option. With this jumper removed, the following bits cannot be directly
cleared by DEVICE RESET or BUS INIT.

Secondary Transmit Data (RXCSR bit 3)
Request to Send (RXCSR bit 2)

Data Terminal Ready (RXCSR bit 1)
Some data sets may require that these connections be excluded from a device
reset function.
w4

Installed

Secondary Transmit Enable. With this jumper installed, the state of the
Secondary Transmit Data line is sent to the data set. With this jumper removed,
this signal is disconnected at the output of the EIA driver. Some data sets do
not use this signal.

Removed

A Data Set Control. With this jumper removed, positive transitions on the
Ring line and any transitions on the Clear to Send line set ADAT SET CH.
This flag requests a receiver interrupt if the DSITEN bit has been set by the
program. With this jumper installed, any transition on three additional lines
sets ADAT SET CH. They are:
Carrier

Data Set Ready

Secondary Received Data
[

A and B Data Set Control. With this jumper installed, transitions on the Carrier,
Data Set Ready, and Secondary Received Data lines set BDAT SET CH. This
signal is a flag only and does not request interrupts. With this jumper removed,
the BDAT SET CH flag (RXCSR bit 0) is inhibited.

Installed

NPR Latency Improvement. With this jumper installed, the NPR latency

improvement circuit in the interrupt control Logic is enabled. This jumper
should be removed only if the DUP11 is installed in a system using a KA1l
processor with no KH11 latency reduction option.

2-2

Remove jumper W1
and install W2
to disable EIA

SEC REC.

From flip flop.

Remove jumper
to disable EIA

Controlled by

SEC XMIT.

RXCSR bit 3.
Program

R/W.

‘_/ _I:D——?W“ o—EIA SEC XMIT_|FF.
|

EIA SEC REC

EIA NEW SYNC
R

Connect wire to

RATE SEL

EIA NEW SYNC
or DATA RATE

DATA

SEL

BERG
HEADER

NOTE:

Jumpers and logic are on sheet
BSI5 of prin1 set.

Figure 2-1

i1-4546

Redefining Secondi'«.lry Transmit and Receive Lines

CONNECTOR
A

2
SLOT

UNIBUS IN (NOTE 2)

G727

[

M7867 HEX MODULE {NOTE 1}

G727*

UNIBUS OUT {NOTE 3}

G727*
MODULE SIDE VIEW

*G727 GRANT CONTINUITY MODULE MUST BE INSTALLED IN EACH SLOT
IN WHICH AN INTERFACE MODULE 1S NOT INSTALLED.

NOTES
1.

M7867 can be mounted only in slot 2 or 3.

Can be M920 Unibus connector or BC11A Unibus cable.

Can be M920, BC11A, or M930 Unibus terminator.

Figure 2-2
2.4

11-3385

DUPL1 (M7867 Module) Mounted in DD11-B

INSTALLATION

The DUPI1 can be installed only in a DDI11-B System Interfacing Unit or equivalent type backplane. This unit
contains four slots, but the DUP11 can be installed in slots 2 and 3 only (Figure 2-2) because of the configuration
of the prewired backplane. Proceed with the installation as follows:
If the system unit is to be installed at this time (in addition to the M7867), perform the next steps. Otherwise, go to step 3.
WARNING

Turn all power OFF.

1. Before installing the system unit in the mounting box, install the GND, +5 V, +15 V, and -15 V
leads in the mounting box power harness to the corresponding Faston tabs on the pin side of the system unit. Make sure that the backplane wiring is not disturbed during this process.
2. Install the system unit in the mounting box.

3. Connect the female Berg connector on the BC02-1D cable to the header on the M7867 module and plug
the module into slot 2 or 3 of the system unit. Connect the female Berg connector on the BC05-25 cable to
the other end of the BC02-1D. Refer to the DUP11

print set for other configurations of the BC02-1D cable.

CAUTION
The maximum allowable length for the BCOSC cable is 50

feet.

4. Perform a resistance check between each power tab and ground tab to verify that there are no short
circuits between ground and each power tab (+5 V, +15V, and -15 V).
NOTE

If the system unit was just installed, it can be assumed that

the DUP11 will be the first module installed in it. Others
will be installed at a later date.
5. Connect the male Cinch connector on the BCO5C-25 cable to the modem or to the H325 test connector, which is the configuration assumed by the diagnostics.
6. Turn power ON,

2-4

2.5 VERIFICATION OF HARDWARE OPERATION
Verification of proper operation of the DUPI1 is performed by a series of diagnostic programs. Details on the

content and use of the diagnostics is contained in the diagnostic documentation package supplied with the
DUPI1.

Proceed as follows:

1. Run diagnostic DZDPE first. This is a confidence test that requires a dialog with the user to ensure
proper setting of DUP11 and system parameters. It offers a quick test to verify that the DUPI11 is
operational.

2. Run the following diagnostics in the order shown below:
DZDPB

Basic and Offline SDLC Transmitter Tests

DZDPC
DZDPD

Offline SDLC Receiver Tests and Offline Modem Control and Interrupt Tests
Offline SDLC and DECMODE Data and Function Tests

Each diagnostic must make three passes without an error.

Reconfigure the DUPI1 in accordance with the customer’s requirements (Table 2-1). Then run diagnostic
DZDPE (DUPI1 Quick Verify Test) to check the final configuration.

System testing consists of running DECX
11 module DXDPB to exercise all DUP11s in a system. Only four
DUPI 1s can be tested with one DECX11 module. Three passes without an error should be made.
2.6

COMPATIBILITY

The DUPI11 is compatible with Bell type 201, 208, 209 modems or equivalent.
2.7

POWER REQUIREMENTS

The DUPI11 requires the following power:
+5Vat36A

+15V at 325 MA
-15V at 600 MA

2.8
2.8.1

DEVICE ADDRESSES
Introduction

Starting with the DJ11, new communications devices are to be assigned floating addresses. The addresses for
current production devices are to be retained.

The word floating means that addresses are not assigned absolutely for the maximum number of each communications device that can be used in a system.
2.8.2

Floating Device Address Assignments

Floating device addresses are assigned as follows:

The

floating

designations).

address space starts at location

760010 and extends to location 764000 (octal

2. The devices are assigned in order by type: DJ11, DH11, DQ11, DU11, and DUPI1, and then the next
device introduced into production. Multiple devices of the same type must be assigned contiguous

addresses.
3. The first address of a new type device must start on a modulo 10; boundary, if it contains one to

four bus-addressable registers. The starting address of the DH11 must be on a modulo 203 boundary because the DH11 has eight registers.

4. A gap of 10s, starting on a modulo 103 boundary, must be left between the last address of one type
device and the first address of the next type device. A gap must be left for any device on the list that is

not used, if the device following it is used. The equivalent of a gap should be left after the last device
assigned to indicate that nothing follows.
5. No new type devices can be inserted ahead of a device on the list.

6. If additional devices on the list are to be added to a system, they must be assigned contiguously after
the original devices of the same type. Reassignment of other type devices already in the system may be
required to make room for the additions.

The following examples show typical floating device assignments for communications devices in a system.
Example 1: No DJ11s, 2 DHl1ls, 2 DQl11s and 1 DUP11
760010

DJ11 gap

760020

DHI11 #0 first address

760040

DHI1 #1 first address

760060

DHII gap

760070

DQI1 #0 first address

760100

DQI1 #1 first address

760110

DQI1 gap

760120

DUI1I1 gap

760130
760140

DUPI1 #0 first address
Indicates no more DUPI1s and no other devices follow.

Example 2: | DJ11, 1 DHI11, 2 DQl1s, and DUP11s

760010

DJI11 #0 first address

760020

DJI1I1 gap

760040

DHI1 #0 first address

760060

DHI1I gap

760070

DQI11 #0 first address

760100

DQI1 #1 first address

760110

DQI1 gap

760120

DUI1 gap

760130

DUPI11 #0 first address

760140

DUPIL1 #1 first address

760150

Indicates no more DUPI1s and no other devices follow.

Example 3: 1 DUPI11

760010

DIJ11 gap

760020

DHI1 gap

760030

DQI1 gap

760040

DUII gap

760050

DUPII1 #0 first address

760060

Indicates no more DUP1Is and no other devices follow.

2-6

2.8.3 Device Address Selection
In the floating address space (760010-764000), bits 13-17 are always s (function of PDP-11 processor). Appendix B shows the PDP-11 memory organization and addressing conventions. Bits 3-12 are selected by

switches in the address decoding logic (Table 2-2). With the switch on (closed), the decoder looks for a 0 on
the associated Unibus address line; conversely, with the switch off (open), the decoder looks for a 1 on the
associated Unibus address line. Bits 1 and 2 are decoded to select 1 of 4 registers. They determine the least
significant digit (octal) of the device address because bit 0 is not used for address decoding and is used to select
the proper byte during byte transactions.
Table 2-2
Guide for Setting Switches to
Select Device Address

Switch No. | 10

Device

Bit No.

(10

Address

X | 760010
X

760020

X | X | 760030
X

760040

X | 760050

[ X

| X | X | 760070

X
X
X

| X

760300
760400

X
| X

X |1 X | X
X
X
X

760100
760200

760060

760500
760600

760700
761000
762000

X
Notes:

1. X means switch off (open) to respond to logical 1 on the Unibus.

2. Switch numbers are physical positions in switch package 1.

763000

764000

SWITCH IDENTIFICATION

The device address selection switches are contained in one DIP switch package (SP#1). Refer to the components location drawing in the M7867-0-1 print set for the location of the package. All 10 switches in the
package are used. The correlation between switch numbers and bit numbers is shown in Table 2-2. The ON and
OFF positions and the switch numbers are marked on the package. The switches are rocker or slide type and are
pushed to the desired position.
The DUPI11 requires four addresses

76XXX0

76XXX2

Receiver Control and Status Register

Receiver Data Buffer Register (Read Only) and Parameter Control and Status Register (Write
Only)

2.9
2.9.1

76XXX4

Transmitter Control and Status Register

76XXX6

Transmitter Data Buffer Register

VECTOR ADDRESSES
Introduction

Communications devices are assigned floating vector addresses. This eliminates the necessity of assigning address absolutely for the maximum number of each device that can be used in the system.
2.9.2

Floating Vector Address Assignment

Floating vector addresses are assigned as follows:

1. The floating address space starts at location 300 and proceeds upward to 777. Addresses 500-534 are
reserved.

2. The devices are assigned in order by type: DC11; KL11/DLI11-A, B; DP11; DMI11-A; DN11; DM11BB; DR11-A; DR11-C; PA611 Reader; PA611 Punch; DTI11; DX11; DL11-C, D, E; DJ11; DHI11;
GT40; LPS11; VT20; DQI1; KWI11-W; DU11; DUPI1; DVI11.

3. If any type device is not used in a system, address assignments move up to fill the vacancies.
4. If additional devices are to be added to the system, they must be assigned contiguously after the original devices of the same type. Reassignment of other type devices already in the system may be required.
2.9.3

Vector Address Selection

Each device interrupt vector requires four address locations (two words) which implies only even-numbered
addresses. A further constraint is that all vector addresses must end in a O or 4. The vector address is specified as a three digit, binary-coded, octal number using Unibus data bits 0-8. Because the vector must end in
0 or 4, bits 1 and 0 are not specified (they are always 0) and bit 2 determines the least significant octal digit

of the vector address (0 or 4). The interrupt control logic sends only seven bits (2-8) to the PDP-11 processor to
represent the vector address.

The DUPI1 is shipped with a BRS priority selection plug installed in the interrupt control logic. This logic
generates two vector addresses: receiver interrupts generate vector addresses of the form XXO0, and transmitter interrupts generate vector addresses of the form XX4. For this method of operation, the state of bit 2
is selected by the logic not by a switch. The two most significant octal digits of the vector address are determined by switches in lines 3-8 (Table 2-3). With the switch OFF (open), a 0 is generated on the ussociated
Unibus data line; with the switch ON (closed), a 1 is generated on the associated Unibus data line. Also, the
NPR jumper (W7) in this logic is left in to improve NPR latency time.

2-8

Table 2-3
Guide for Setting Switches to
Select Vector Address
SwitchNo. |

Vector

Bit No.

Address

300

320

310
330

340
350

360

370
X

X
X

400

500

600

700

Notes:

1. X means switch off (open) to produce a logical 0 on the Unibus.
2. Switch numbers are physical positions in switch package 2.

SWITCH IDENTIFICATION

The vector address selection switches are contained in one DIP switch package (SP#2). Refer to the components location drawing in the M7867-0-1 print set for the location of the package. Only six of the eight
switches in the package are used. The corelation between switch numbers and bit numbers is shown in Table
2-3. The ON and OFF positions and the switch numbers are marked on the package. The switches are
rocker or slide type and are pushed to the desired position.

CHAPTER 3

OPERATING FEATURES AND REGISTER DESCRIPTIONS

3.1
3.1.1

MAJOR OPERATING FEATURES
Introduction

This paragraph discusses the major operating features of the DUPI11 at the functional level. The discussion is
divided into four sections as shown below.

Title

Par. No.

Modem Control

42.2.2

Transmitter Section

4223

Receiver Section

4224

Interrupt Handling

4.2.2.5

This discussion assumes that the DUP11 is operating in the user mode. The maintenance modes, which are
used to service the DUPI 1, are described in Chapter S MAINTENANCE.
3.1.2

Modem Control

In some systems, this handshaking is not neccessary. The transmitter is simply enabled and transmission starts
when the program sets the TSOM bit in the transmit data buffer register (TXDBUF). The receiver may start
searching for synchronization without first having been rung.
The modem control and status lines are monitored along with a flag to indicate a change in any line’s state
since the last time it was monitored by the program. Using these indicators, the program must determine
when it can transmit data. Once this has been established, the transmitter is enabled and transmission begins

when the first character is loaded into the data buffer.

In some systems, this handshaking is not necessary. The transmitter is simply enabled and transmission starts
when the program sets the TSOM bit in the transmit data buffer register (TXDBUF). The receiver may start

searching for sychronization without first ving been rung.
The flow of data is not interlocked with signals received from the modem. When modem control is being used in
a system, the program must monitor the received modem control signals contained in the RXCSR register.
The secondary receive and transmit leads are also included in the modem control section. While these leads have
no function in the Bell 201, 208, and 209 modems, they can be redefined for other user purposes at installation
time.

All clock signals used in conjunction with data received from or transmitted to the modem must emanate from
the modem and be in accordance with EIA RS 334 at a rate < 10 kHz. No external clock to the modem is

supplied by this interface. Maintenance mode clocking used to facilitate checkout and diagnostic engineering is
provided. This clocking is under program control and is intended to be used only when the DUPI11 is being

serviced.
3-1

3.1.3

Transmitter Section

The transmitter section provides the following functions.
1.

Buffers and serializes parallel data.

Generates CRC check characters.

Creates transparent data stream for SDLC and ADCCP protocols.

Transmits flag and abort sequences and leading zero sequences.

The transmitter section is enabled when the program asserts the SEND bit in the TXCSR transmitter control
and status register (TXCSR). The actual state of the transmitter logic is indicated by the TXACT bit in this
register.

A character or control bit may be loaded into the TXDBUF whenever the TXDONE bit is asserted. This occurs after an initialize pulse, device reset by the program, or when the logic completes transmission of a character. This bit is cleared when a character is loaded into the TXDBUF.
TRANSMIT OPERATION UNDER SDLC FAMILY PROTOCOL DISCIPLINE
Asssuming that the transmitter section is in the idle state (TXACT = 0) and is enabled by the SEND bit,

transmission of a message sequence begins when the TSOM bit in the TXDBUTF is detected. Upon detecting this
bit, the transmitter automatically transmits the initial flag character.
When starting from the idle state, the first bit of the flag character delayed for a period equal to two bit times.

The TXDONE and TXACT bits are asserted when this first bit is transferred to the serial line. At this point, the
first data character may be loaded into the TXDBUF. If the

TSOM bit is still asserted at the completion of the

flag character currently in progress, then another flag character is transmitted. Flags are sent until TSOM is
cleared.

The transmitter goes into the transparent state immediately following the transmission of the last initial flag

characters and also begins the accumulation of the CRC check character, providing that the CRC inhibit bit is
cleared in the PARCSR. When the transmitter is in the transparent state, the logic automatically inserts a 0
following five consecutive ones, to preserve the properties of the flag and abort characters.
Termination of a message is accomplished by asserting the TEOM bit in the TXDBUF. The character currently
being serialized in the transmitter shift register is completed. If CRC is not inhibited, the computed CRC check

character is automatically transmitted and followed by a terminating flag character. If CRC is inhibited, the
terminating flag character follows the character currently being serialized. The TEOM bit must remain asserted
until transmission of the terminating flag character starts. If the SEND bit is asserted when TEOM is asserted,

the start of the transmission of the flag is identified by the next transition of TXDONE. These events occur
simultaneously.

At this point, the program has three options.
1.

Clear SEND which allows the flag character currently being transmitted to be finished. At the end of

the flag, there is a delay of one and one half bit times after which the transmitter enters the idle state.
2.

Leave TEOM asserted, which allows continuous flag characters to be transmitted until option 1 or 3

is executed. In this option, Data Late errors do not occur. The number of flag characters sent can be

determined by counting the transitions (set state) of TXDONE. This bit is set when the TXDBUF
register is loaded. In this case, the program should keep TEOM set.

3-2

Initiate another data transfer by clearing TEOM and loading the data byte into the TXDBUF register. If TEOM is cleared during transmission of the first terminating flag, then only one flag separates

the SDLC frames. If TXACT is asserted, it is not necessary to set TSOM to start a subsequent
message. The recommended procedure is to load the new data and clear TEOM in the same operation
that accesses the TXDBUF. The TSOM bit should be used to initiate a message only when TXACT is
cleared.

If the SEND bit is cleared between the time that the TEOM bit is asserted and the transmission of the terminating flag has started, then the transition of TXDONE is deferred until the transmitter returns to the idle state.

This delay of half a bit time in most case insures the integrity of the last character before attempting to turn the
line around in half duplex situations; however, this is modem dependent and each modem manual should be
referenced for applicability.

if SEND is cleared and no transmitter control bits are set, the current character is transmitted and the trans-

mitter is shut down after a 1 1/2 bit delay.

In some instances it may be necessary, because of system or timing restriction, to transmit a given number of
ABORT characters subsequent to the last flag characters. This can be accomplished by asserting the TXABORT bit at the appropriate time. The SEND bit must remain asserted for this operation.
The TXABORT bit can be asserted when the last required flag character has begun transmission. The
earliest possible time that the TXABORT bit can be asserted (for this purpose) is immediately after the second assertion of the TXDONE bit subsequent to the setting of the TEOM bit.

The first assertion of the TXDONE bit subsequent to the setting of the TEOM bit occurs when the serialization of CRC check information begins. It is necessary to clear the TXDONE bit before the end of the transmission of the CRC character so that the second transition of the TXDONE bit can occur. This transition
marks the start of the transmission of the terminating flag character. This second transition can be created
by again setting the TEOM bit. The TXABORT bit can be set when the TXDONE bit asserts marking the
beginning of the terminating flag character.

TRANSMIT OPERATION UNDER DDCMP OR BISYNC PROTOCOL DISCIPLINE
Assuming that the transmitter is enabled by the SEND bit in the TXCSR, transmission starts when the
TSOM bit is set in the TXDBUF by the program. When the TSOM bit is asserted, the SYNC character
being used must be present in the lower byte of the TXDBUF. All transmitted SYNC characters must be
loaded into the TXDBUF. The TSOM bit must remain asserted until the start of the last SYNC character.
The TXDONE bit is asserted at the completion of each SYNC character. When it is necessary to count the
number of transmitted SYNC characters, the TXDONE bit can be cleared by again setting the TSOM bit.
This allows the next transition of TXDONE at the end of the character.

When the last SYNC character is transmitted, the TSOM bit is cleared and the first character of data is entered into the TXDBUF. This character and all subsequent data characters included in the transmitter’s
CRC computation,.

For protocols such as BISYNC, the CRC feature of this device must usually be inhibited. Protocols such as
DDCMP can make efficient use of the CRC logic. These protocols are characterized by the fact that no special control characters are embedded within the message that are not included as part of the CRC
computation.

The accumulated CRC check character is transmitted subsequent to the assertion of the TEOM bit. When
the character currently being transmitted is complete, the CRC check character is sent next, if the TEOM bit
is asserted. The TXDONE bit is asserted at the start of the CRC character transmission. This can be ignored
or cleared by again setting the TEOM bit.

The

DUPI1

does

not

provide the feature of automatically idling SYNC characters without program

intervention.
Data must be presented to the TXDBUF as 8-bit characters. The message length is not restricted.

TRANSMITTER CRC CHARACTER GENERATION

To enable the CRC logic, the program must clear NO CRC (PARCSR bit 9). Two cyclic redundancy checking

(CRC) codes are used. The SDLC family protocols use code CCITT which is represented by polynomial X6 +
X2 + X5 +1. The DDCMP family protocols use code CRC-16 which is represented by polynomial X!¢ + X15 +
X2 + 1. With CRC enabled, the accumulated CRC check character is a result of all data loaded by the program
into the TXDBUF. With the SDLC and ADCCP protocols, Os that are inserted into the message to maintain

transparency are not included as part of the calculation.
The transmitter CRC register is initialized (cleared) when TSOM is asserted, which is internally synchronized.
When initialized, the register reads all Os in the DDCMP mode and all 1s in the SDLC mode. Initializing the
register to all 1s provides protection against obliterating leading zeros which may not be detected if the register is
zero. In the DDCMP mode, the CRC check character is transmitted as is. In the SDLC mode, it is complemented
before it is transmitted.
TRANSMITTER LATENCY
The specifications of the SDLC, ADCCP and DDCMP protocols require that the flow of data be contiguous; that is, no intra-message fill characters are allowed.
Since the DUPII

is double buffered, one character time (and in some cases more) is allowed before data late

errors are encountered. The data late condition is indicated whenever the TXDBUF is not serviced within

the appropriate response time before assertion of the TXDONE bit.
This time can be expressed as follows:
(1/baud rate) 8 + n (secs)

n =number of inserted zeros.

(Applicable only for SDLC family protocols)
n<?2
When the current character has been transmitted, the absence of valid data in the TXDBUF causes the

TXDAT LATE bit to be asserted in the TXCSR, unless the TEOM bit was asserted in the TXDBUF. This
indication suggests re-transmission of the message. When this occurs, the transmitter automatically transmits
abort characters in the SDLC or ADCCP modes until a new message is presented to the transmitter, providing the SEND bit is asserted. In the DDCMP or BISYNC modes the line is held in the mark hold state. As-

sertion of the TSOM bit clears the TXDAT LATE bit.
3.1.4

Receiver Section

The receiver section provides the following functions.

1. Buffers and converts received serial data to parallel data.
2. Interprets transparent data stream in SDLC or ADCCP protocols.

3. Recognizes flag and abort sequences.
4. Recognizes secondary station addresses (SDLC mode) and SYNC characters (DDCMP mode).
5. Detects CRC errors.

3-4

The receiver section is capable of operating as either a secondary or primary station when the SDLC and
ADCCP protocols are selected. This is controlled by the state of the SEC MODE bit in the PARCSR. When

operating as a primary station, all received messages are presented to the program. In the secondary mode,
only messages that are prefixed with a secondary station address that matches the contents of the low byte of
the PARCSR are presented to the program.
If the DDCMP or BISYNC mode of operation is selected, the low byte of the PARCSR must be loaded
with the SYNC character being used by the system. All data received is handled as eight bit characters.

The receiver logic is controlled by the RCVEN bit in RXCSR. The state of the receiver is indicated by the

RXACT bit in the same register.
RECEIVE OPERATION UNDER SDLC FAMILY PROTOCOL DISCIPLINE

Once the initialization and any necessary modem handshaking have been completed, the RCVEN bit can be set.
When the RCVEN bit is asserted, the receive logic searches for initial flag character. When operation in the

primary mode, all data received subsequent to the last initial flag character is presented to the program. The first

character is accompanied by the RSOM in the RXDBUF. When operating in the secondary mode, the character
subsequent to the last flag character is compared to the contents of the iow byte of the PARCSR (any bits
inserted for transparency are stripped prior to performing the compare). If the comparison is not true, then the
search for a flag is reiterated. When this comparison is true, the RXACT bit is asserted in the RXCSR. The
RSOM bit in the RXDBUF is set to indicate the beginning of a new message. The received address character is
not presented to the program. The character subsequent to it is the first character to be presented to the program
along with the RSOM bit. When this character is transferred to the receiver data buffer, the RSDONE bit is also
asserted. Any character subsequent to this causes the RXDONE bit to be asserted with the receiver interrupt
enable bit asserted, the assertion of the RXDONE bit creates an interrupt request. When the program accesses
the RXDBUF, the RXDONE bit is cleared.
When the terminating flag character is received, the REOM bit is asserted in the RXDBUF and the RXDONE

bit is asserted in the RXCSR. The low order byte of the RXDBUF is invalid when the REOM bit is set.

If CRC checking is not inhibited, an error would be indicated only when the REOM bit is asserted. The check is

performed on all data received beginning with the secondary station address up until the first check character is
received. When CRC checking implemented, the last two bytes of information received by the program are the
CRC check characters.

Messages in progress can be aborted if the sending station transmits an ABORT sequence. When the receiver
detects the ABORT sequence, the RABORT bit in the RXDBUF is set along with the RXDONE bit in the
RXCSR. The receiver logic detects one ABORT sequence after receiving an initial or final flag character.

All data received is handled and presented to the program in eight bit characters.

Transparency is maintained at the receiver by searching the data stream for zeros inserted by the transmitter
and removing them.
RECEIVE OPERATION UNDER DDCMP OR BISYNC PROTOCOL DISCIPLINE

The DDCMP and BISYNC family of protocols are also handled by this device. In most BISYNC applications,

the software overhead is increased. This occurs because of the extra amount of character recognition or processing of message header information required. Also, in some cases, the CRC feature of the DUP11 may have to be
inhibited because of control characters embedded within the data stream.
The low byte of the PARCSR must be loaded with the SYNC character being utilized by the system before the

receiver is enabled. This character is loaded into the PARCSR and is used only by the receiver logic for comparison with data being received. This register is not used by the transmitter logic.

3-5

Once the initialization and any necessary modem handshaking have taken place, the program may assert the
RCVEN bit. With the RCVEN bit asserted, the first operation of the receiver logic is to search the data stream

for two consecutive SYNC characters. When two consecutive SYNC’s have been recognized, the receiver logic is
considered synchronized and any subsequent information is assembled as eight bit characters. When an eight bit
character is assembled, it is transferred into the RXDBUF and RXDONE bit is asserted conditional on the
character being received, and the state of the STRIP SYNC bit and RXACT bit. If the program has asserted the
STRIP SYNC bit, the character received matches the contents of the PARCSR low byte, and the RXACT bit has
not been set by the logic, the RXDONE bit is not asserted.

When the logic has located the first non-SYNC characters, the RXACT is asserted by the logic. This character
and all subsequent character are included in the receiver’s CRC computation. At this point, the function of the
STRIP SYNC bit is internally disabled.

The RCVEN bit in the RXCSR should be left asserted for the entire message, and cleared at the end of the
message. Clearing this bit re-initializes the receiver logic.
RECEIVER CRC CHARACTER CHECKING

CRC error detection is performed by the receiver logic if the NO CRC bit is cleared. The method of detecting errors and the polynomial used vary according to the mode of operation as controlled by the DEC
MODE bit in the PARCSR.

If the DEC MODE bit is cleared, then the CCITT polynomial (X'6 + X12 + X5 +1) is used and the logic
operates in a manner compatible with the SDLC and ADCCP protocols. The receiver CRC error detection
logic is effectively set to all ones when the RXACT bit is cleared.

The contents of the receiver CRC register are tested when a terminating flag is received in SDLC or ADCCP
mode. The register is tested for the following bit pattern: LSB 1 111 000 010 111 000 MSB. The absence of
this bit pattern causes assertion of the RCRC ERR + ZERO bit in the RXDBUF. The REOM bit is also
asserted at this time. This bit pattern is the result of all data received between the last initial flag character
and the terminating flag, excluding inter-message flags and zeros inserted for transparency.
The last two bytes (16 bits) of data presented to the program thru the RXDBUF comprise the received CRC
check character. The data received in the RXDBUF when the REOM bit is asserted is meaningless and
should be disregarded.

DDCMP compatible operation is enabled by asserting the DEC MODE bit. In this mode the CRC 16 (X6
+ X5 +X2 + 1) polynomial is used to generate the receiver check character. The receiver CRC register is
initialized to all zeros when the RXACT bit is cleared.

Once the receiver has been synchronized, the data received and presented to the program is included in the
computation of the check character. This occurs when the RXACT bit is asserted. Characters received during
the reception of a message (after RXACT is asserted) are included in the CRC computation even if they
match the contents of the PARCSR. The function of STRIP SYNC is internally disabled when RXACT is
asserted.

The RCRC ERR + ZERO bit is asserted in this mode when, during the reception of a message, the CRC
register is equal to zero coincidental with the end of the current character.

The program should only test the RCRC ERR + ZERO bit when the expected number of bytes including
CRC information have been received. It is entirely possible that during the reception of a message, this bit
may be asserted without having received the actual CRC check character. Normally the RCRC ERR +
ZERO bit is presented to the program along with the second CRC check character.

3-6

RECEIVER LATENCY

The program must respond to the RXDONE bit within a specified time frame in order to avoid overrun
errors.

If the program hasn’t read the contents of the RXDBUF within this time frame, the OVRUN FRR bit in
the RXDBUF is set. The contents of the data buffer contain the last received character. This error suggests
retransmission of the message.

Because this device is double buffered, the time lag in which the program must respond is as long as a full
character time and can be expressed as the following.
(1/baud rate) 8 + n (secs.)
n=number of inserted zeros. n€2.

(SDLC family protocols only)
INTERRUPT REQUESTS

In the RXCSR, there are two interrupt request enable bits; in the TXCSR, there is one. These bits can be
used to selectively allow interrupt requests that occur asynchronous to the operation of the program.
The Data Set Interrupt Enable bit (DSCITEN) allows interrupt requests to be generated on the receiver interrupt vector if the DATA SET CHANGE A bit is asserted. The Receiver Interrupt Enable bit (RXITEN)

also allows interrupts to be generated on this same vector if the RXDONE bit is asserted. If both interrupt

conditions exist simultaneously on the receiver vector, then the interrupt requests occur back to back and
there is no fixed scheme in which the requests should be serviced.

There is only one interrupt request made on the transmitter interrupt vector. This request is made if the
Transmitter Interrupt Enable bit (TXITEN) is set and the logic asserts the TXDONE bit.

All interrupt requests should be serviced at a processor status level equal to or above that of the device interrupt priority level. If simultaneous interrupt requests are generated on both the receiver and transmitter vec-

tors, the receiver request is honored first.
HALF DUPLEX OPERATION

The program can select half duplex operation. This can be done by asserting the HALF DUPLEX bit in the
TXCSR.

In this mode of operation, the receiver logic does not transfer data. It is completely disabled, if the SEND
bit i1s asserted in the TXCSR. All other characteristics of the interface are maintained.
3.2

DUP11 REGISTERS AND DEVICE ADDRESS SELECTION

The five registers used in the DUP11 are shown in Table 3-1. There is no conflict in assigning the same address

(76XXX2) to two registers because the RXDBUF is read only and the PARCSR is write only.

Communications devices are assigned floating device addresses in the range 760010 to 764000. Rules for assigning
floating device addresses are contained in Chapter 2,

3.3

INTERRUPT VECTORS

The DUP11 generates two vector addresses:

receiver interrupts (REQ A) generate vector addresses of the form

XX0, and transmitter interrupts (REQ B) generate vector addresses of the form XX4.

Communications devices are assigned floating vector addresses in the range 300 to 777 (500—534 are reserved).
Rules for assigning floating vector addresses are contained in Chapter 2.

3-7

3.4

PRIORITY SELECTION

The priority selection (BR level) for receiver and transmitter interrupts is selectable on the module via a plug-in
priority selection card. The DUPI11 is shipped with a priority 5 card installed that establishes BR5 as the bus
request level for interrupts.

3.5

Bit assignments for the five DUP11 registers are shown in Figure 3-1. Each register is described by showing a
bit assignment illustration and an accompanying table that discusses each bit in detail.

Table 3-1
DUP11 Registers

Name

Mnemonic

Address

Comments

Receiver Control and

RXCSR

76 XXX%0

Word and byte addressable.

Status Register

Receiver Data Buffer

Read /write.

RXDBUF

76XXX2

Word addressable. Read only.

Parameter Control and
Status Register

PARCSR

76XXX2

Transmitter Control and
Status Register

TXCSR

76 XXX4

Word and byte addressable.
Read/write.

Transmitter Data Buffer
Register

TXDBUF

76XXX6

Word and byte addressable.
Read/write.

3-8

Word addressable.
Write only.

DAT{}
C:AENGE

RING

CLR
TO

SEND
R

RCV | OVER

DATA |
ERR |

RUN
ERR

R/W

CRC

Ry | END | START

PAR
ERR

aponT|

OF
MESG

SECD

cRe

MODE

ford

ADRS

OF
| MESG

R/W

DATA

| SEND

R/W

RDY

R/W

RXCSR
T6XXX0

READ/WRITE

[

RXDBUF DATA
|

[

RXDBUF
7T6XXX2

READ ONLY

PAR

SEL

DATA
DSAJTA
TERM | S8

SECONDARY STATION ADDRESS
+

PARCSR
76 XXX2

WRITE ONLY

RECEIVER SYNC

15
TX

R/W

RfNRC

TTcl';C

'fih;'g?

ABORT|

R/W

ACTT"
DEVICE
IVE | RESET

DE:E

INTR
EN

SEND

;J‘;—Ifx

R/W

TXDNE

MESG

| MESG

R/W

00
TXCSR
76XXX4

READ/WRITE

END | START
OF

TXDBUF DATA
RIW

TXDBUF
TEXXX6

READ/WRITE

|
11-3343

‘Figure 3-1

DUPI11 Register Configurations and Bit Assignments

3-9

Table 3-2
Bit Descriptions for Receiver Control and Status Register (RXCSR)
Name

Bit

Description

ADAT SET CH

This bit is set when any of the following transitions occur on the data set

(Data Set Change A)

control lines.
1.

A positive transition on the Ring line greater than 10 ms.

Any transition on the Clear to Send line.

An optional jumper modification allows this bit to be set by any of the
following transitions. This modification is a field installation change
supported by diagnostics.
1.

Any transitions of the Carrier line.

Any transitions of the Data Set Ready line.

Any transitions of the Secondary Received Data line.

Normally these three transitions cause the Data Set Change B bit to be set
in this register. If the jumper modification is made, this bit is disabled.

If bit 05 (Data Set Interrupt Enable) of this register is set, the assertion of
this bit causes an interrupt to the receiver vector. This bit is program read

only and is cleared by INIT, device reset or when the RXCSR is read.
14

RING

This bit reflects the state of the modem Ring line. Any positive transition
of this line greater than 10 ms causes the Data Set Change A bit to be set.

This bit is program read only.
13

CLR TO SD

This bit reflects the state of the Clear to Send line of the modem. Any

(Clear to Send)

transition of this line causes the Data Set Change A bit to be set.
This bit is program read only.

CARRIER

This bit is a direct reflection of the modem carrier. Any change in the state
of this line causes Data Set Change B to be set unless the data set change

jumper modification has been made. (Refer to bit 15 of this register.)
This bit is program read only.

3-10

Table 3-2 (Cont)
Bit Descriptions for Receiver Control and Status Register (RXCSR)
Bit
11

Name

RXACT

(Receiver Active)

Description

The function of this bit is to reflect the current state of the receiver logic in
accordance with the selected mode of operation as defined by the contents

of the PARCSR.
SDLC or ADCCP Protocol:
In the SDLC or ADCCP mode of operation, (i.e., DEC MODE cleared) this
bit is set by the DUP11 logic when the first character of a message frame is
being received. CRC computation is performed for all data received, if not
inhibited.

If the SECD ADRS MS (Secondary Mode Address Select) bit in the PARCSR
is cleared, the receiver’s operating mode is that of a primary station. In this

mode of operation, the RXACT bit stays asserted until the terminating flag
character is received. At this time the RXACT bit is cleared and the REOM
bit is asserted. The internal receiver CRC register is tested for an error con-

dition and re-initialized at this time in preparation for the next message, if
CRC is not inhibited.

If an Abort sequence is not received prior to the terminating flag, the
RXACT bit is re-asserted when the first data character of the next message
is received. The RSOM bit will appear with this character. Any inter-message

flag characters are ignored by the receiver.
With the Secondary Address Mode Select bit asserted in the PARCSR, the

receiving station operates as a secondary station. The major difference
between the primary and secondary modes, as far as the DUP11 hardware
is concerned, is the character subsequent to the last initial flag character. In

secondary mode, this character must match the contents of the low byte of
the PARCSR; if not, the RXACT will not be set and the receiver logic searches
for the next flag sequence.

If extended secondary addressing is implemented in a system, (i.e. 16 bit

addresses), the second byte of address must be recognized by software.
DDCMP or BISYNC Protocol:
Setting the DEC MODE bit in the PARCSR causes the DUP11 to operate in
a manner compatible to the DDCMP or BISYNC family protocols.
The low byte of the PARCSR must be loaded with the SYNC character being
utilized by the system. This register is used only by the receiver logic for
comparison purposes. It is not utilized by the transmitter logic.

3-11

Table 3-2 (Cont)

Bit Description for Receiver Control and Status Register (RXCSR)
Description

Name

Bit
11

RXACT

(Cont)

(Receiver Active)

When the RCVEN bit is asserted, the receiver logic searches the received
data stream for two consecutive SYNC characters. When two consecutive

SYNC characters have been recognized, the receiver is to be considered

synchronized to the transmitting station. At this time, all characters subsequent to the two SYNC characters that caused the synchronization are
presented to the program (i.e. RXDONE is set) conditional on the character
and the state of the STRIP SYNC bit asserted by the program.

The RXACT bit is normally asserted when the first character is received subsequent to the synchronization process, unless the STRIP SYNC bit is set.
If STRIP SYNC is set, the assertion of RXACT by the DUP11 logic is delayed until the first non-sync character is received. Once RXACT is asserted,
the CRC detection logic is activated, provided it is not inhibited in the PARCSR
(bit 9) and the STRIP SYNC function is disabled internally.
When the completion of the message has been detected, the program must
clear the RCVEN bit to re-initialize the receiver. Clearing the RCVEN bit

causes the RXACT bit to be cleared also.
This bit is program read only and is cleared by INIT, device reset, an off

transition of RCVEN, and an ABORT sequence is received in the SDLC or
ADCCP mode.
10

SEC RCV

This bit reflects the state of the Secondary Received Data line from the

(Secondary Received

modem. Any transition on this line causes the Data Set Change B bit to

Data)

be set unless the data set change jumper modification has been installed.

Refer to bit 15 of this register.
Used with certain modems only.
This bit is program read only.
DAT SET RDY

This bit reflects the state of the Data Set Ready (or interlock) lead from the

(Data Set Ready)

modem. This line, when asserted, indicates that the modem is powered up,
is not in test, talk or dial mode. Any transition of this bit causes the Data

Set Change B bit to be asserted unless the data set change jumper modification has been instailed. Refer to bit 15 of this register.
Program read only.

STRIP SYNC

This bit is used only with the DDCMP or BISYNC family protocols.
Once the receiver has achieved synchronization, any characters received that
match the contents of the low byte of the PARCSR and are contiguous to the
initial SYNC characters, are not presented to the program (i.e., RXDONE will
not be set) if this bit is set.

3-12

Tabie 3-2 (Cont)

Bit Description for Receiver Control and Status Register (RXCSR)
Bit

Description

Name

STRIP SYNC

(Cont)

This is useful in stripping off any SYNC characters that are subsequent to
the SYNC characters that caused the actual synchronization of the receiver
logic.

NOTE: This bit must be cleared when the SDLC or ADCCP mode is invoked.
Failure to clear this bit disables the receiver logic.

This bit is program read/write and is cleared by INIT or device reset.
RX DONE

(Receiver Done)

This bit is set by the device when the RXACT bit is set and a character is
transferred from the internal receiver shift register into the RXDBUF
(receiver data buffer) for the programs acceptance.
This bit is also set whenever SYNC characters are received immediately subsequent to the actual synchronization SYNC characters, unless the STRIP
SYNC bit is set. This applies only to DDCMP or BISYNC modes.
In SDLC mode, this bit also is set when an ABORT sequence is
received or when the REOM bit is set in the RXDBUF. The
RABORT bit in the RXDBUF is asserted when an ABORT sequence
is received while the RXACT bit is asserted or when seven consecutive

1s are detected following a final flag character. In the latter case,
RXACT is clear when RXDONE is set and occurs only for the first
received ABORT sequence.

This bit is program read and is cleared by reading the RXDBUF, INIT, or
Device Reset.

An interrupt request is generated if the Receiver Done Interrupt Enable bit
is set when this bit is asserted.
RXITEN

When set, this bit allows interrupt requests to be made to the receiver vector,

(Receiver Interrupt

if the RXDONE bit is set.

Enable)

All interrupts should be serviced at a processor level equal to or higher than
the device Bus Request level which is shipped at level 5.
This bit is program read/write, and is cleared by INIT or device reset.

DSCITEN

When set, this bit allows interrupt requests to be made to the receiver vector,

(Data Set Interrupt

if the Data Set Change A bit is set.

Enable)

All interrupt requests should be serviced at a processor level equal to or higher
than the device interrupt request level which is shipped at level 5.
This bit is program read/write and is cleared by INIT or Device Reset.

Table 3-2 (Cont)

Bit Description for Receiver Control and Status Register (RXCSR)

Bit
4

Name

Description

RCVEN

This bit controls the operation of the receiver logic. When initially set, the

(Receiver Enable)

receiver is enabled to search for synchronization, irrespective of the DUP11’s
operating mode.
Once synchronization has been achieved, the reception of received data and
timing is controlled by this bit.

Clearing this bit at any time causes all receiver timing and control functions
to be reset asynchronously to the modem clock or the data stream currently
being received. The RXDONE bit is cleared by the off transition of this bit.

This bit is program read/write and is cleared by INIT and device reset.
3

SEC TX

This bit is connected to the Secondary Transmit line of the modem. Super-

(Secondary Transmit

visory data can be transmitted over this line at a reduced rate. This applies

Data)

to certain modems only.
This bit is program read/write and is optionally cleared by INIT or Device
Reset.

RTS

When set, this bit causes the Request to Send lead to be asserted at the

(Request to Send)

modem interface.
This bit is program read/write and is optionally cleared by INIT and Device
Reset.

DTR

When set, this bit causes the Data Terminal Ready lead to be set. For auto

(Data Terminal

dial and manual call origination it maintains the established call. For auto

Ready)

answer it allows handshaking in response to a Ring signal.

This bit is program read/write and is optionally cleared by INIT or device
reset.

BDAT SET CH

This bit is asserted when any of the following transitions occur on the

(Data Set Change B)

respective data set control lines.
1.

Any transition of the Carrier line.

Any transition of the Data Set Ready line.

Any transition of the Secondary Received Data line.

3-14

LQUIv

\\/Ulll}

Bit Description for Receiver Control and Status Register (RXCSR)

Bit
0

(Cont)

Name

Description

BDAT SET CH

Two optional jumper modifications can be made in the field with respect to

(Data Set Change B)

this bit, the normal jumper configuration is as cited above.
1.

Removing the data set change jumper inhibits the setting of the

Data Set Change B bit.

The Data Set Change B bit is inhibited and the signal transitions
cited above are combined with the signal transitions that set Data
Set Change A. In this case Data Set Change A is also set by the
transitions cited above.

These variations are supported by diagnostics.
This bit is program read and is cleared by INIT, device reset or by reading
the RXCSR.

RING

DATA SET
CHANGE

(ADAT SET CH)

CARRIER

| RECEIVER

| SECONDARY

STRIP

RECEIVER

RECEIVED

SYNC

INTERRUPT |

DATA

ENABLE

(SEC RCV)

(RXITEN)

DATA SET

REQUEST

ENABLE

TO SEND

| CHANGE

(RCVEN)

(RTS)

CLEAR TO

RECEIVER

DATA SET

RECEIVER

DATA SET

SECONDARY

DATA

SEND

ACTIVE

READY

DONE

INTERRUPT

TRANSMIT

TERMINAL

(CLR TO SD)

(RXACT)

(DAT SET RDY)

(RX DONE)

PATA

READY

ENABLE

(DSCITEN)

(SEC

TX)

|(BDAT SET CH)

(DTR)
11-3337

Figure 3-2

Receiver Control and Status Register Format

3-15

Table 3-3

Bit Descriptions for Receiver Data Buffer Register (RXDBUF)
Bit

Name

Description

RX ERROR

This bit is set if one of the three error bits in the RXDBUF is set. (Logical

(Receiver Error)

OR of bits 14, 12 and 10.)
NOTE: If the DEC mode bit is set, the setting of bit 12 does not cause
this bit to be set.

This bit is program read only and is cleared only when bits 14, 12 or 10 are
cleared.
14

REC OVERRUN

When the receiver logic detects an overrun condition, this bit is set. An

(Receiver Overrun)

overrun is caused primarily by poor program response time.

Once the RXDONE bit is set, the program must respond within (1/bps)
(8+n) (bit time) sec: if not, overrun occurs. This condition indicates the
loss of at least one character. This bit causes the error bit to be set.

This bit is set for a minimum of one character time. This bit is cleared
within one character time after the overrun condition has been relieved by

reading the RXDBUF. (i.e., When the next transfer from the internal re-

ceiver shift register into the RXDBUF occurs.)
The Receiver Error bit is set when this bit is set.

n = number of inserted zero bits (SDLC or Adccp only)
n<2

This bit is program read only and is cleared by INIT, device reset or by

clearing RCVEN,
Reserved.

13
12

RCRC ERR + ZERO

(Receiver CRC Error)

When the SDLC or ADCCP mode is selected, this bit is set when the re-

ceiver logic detects a CRC error upon termination of a message. The error
check is made only when the REOM bit is set in the RXDBUF.
When the DDCMP protocol is being used, this bit is set when the interns

receiver CRC register is equal to zero.
When this bit is set, it stays set for one character time or until the next

transfer is made into the RXDBUF from the internal receiver shift register.
The Receiver Error bit is set when this bit is set if the DEC MODE bit is
cleared in the PARCSR.

This bit is program read and is cleared by INIT, device reset, or by clearing
RCVEN.

3-16

Takla 2.2
1avilC

J-0

(M ned)

(VUllL)

Bit Descriptions for Receiver Data Buffer Register (RXDBUF)
Bit

Name

Reserved.

i1
10

Description

RABORT

When an SDLC or ADCCP abort sequence has been received, this bit

(Receiver Abort)

is set. All receiver timing, internal control and registers are reset. The
receiver logic detects ABORT sequences providing an initial or final
flag character has been received. The ABORT sequence is defined as
seven or more contiguous 1s. If multiple ABORT sequences are being
transmitted, the receiver indicates reception of only the first ABORT
of the sequence. If the RCVEN bit is left asserted, the receiver resumes
searching for a flag synchronization sequence.
The RXDONE bit is set when the abort sequence is received and the Receiver
Error bit is set also.

This bit is cleared by INIT, device reset, clearing RCVEN or reading the
RXDBUF.

REND MESG

This bit is functional only in SDLC or ADCCP mode. It is set when a

(End of Received

terminating flag character is received. This occurs when a flag character is

Message)

received. with the RXACT bit set. When this bit is set, bits 07 through 00
of this register are invalid.

This bit is set for a minimum of one character time. The next transfer from
the receiver shift register into the RXDBUF clears this bit.

This bit is program read and is cleared by INIT, device reset, or by clearing
RCVEN.
RSTR MESG

This bit is functional only in SDLC or ADCCP mode. When operating in

(Start of Received

the primary mode, this bit is set when the first data character is received.
When operating in the secondary mode this bit is set if the character following the last received flag matches the contents of the secondary station

Message)

address register.

This bit is set for a minimum of one character time. The next transfer from
the receiver shift register into the RXDBUF clears this bit.
This bit is program read and is cleared by INIT, device reset, or by clearing
RCVEN.
7-0

RXDBUF

(Receiver Data

This register contains the data received from the modem. All characters
that are presented to the program through this register are eight bits.

Buffer)

All characters in this register are right hand adjusted with bit 00 being the
least significant bit and bit 07 being the most significant bit.
-~

. C

nmderad

MAnconaa laid

20 an

Aata

thicg vacic

When the End of Received Message bit is set, the data in tnis register is not

3-17

Table 3-3 (Cont)
Bit Description for Receiver Data Buffer Register (RXDBUF)

Bit

Name

Description

7—0

If CRC checking is being used, the last two characters that proceed the

(cont)

setting of the End of Received Message bit are the CRC check characters
that were transmitted.
These bits are program read and are cleared by INIT, device reset, RABORT
or by clearing RCVEN.

RECEIVER DATA BUFFER (RXDBUF)
RECEIVER

RECEIVER

OVERRUN

CRC ERROR

RECEIVER | START

ABORT

(RCRC ERR) | (RABORT)
+ZERO)
RECEIVER

RESERVED

RECEIVED

MESSAGE
(RSTR MESG)

END

ERROR

RECEIVED

{RX ERROR)

MESSAGE
(REND MSG)
11-3338

Figure 3-3

Receiver Data Buffer Register

3-18

Format

Table 3-4
ar

Bit Descriptions for Parameter Control and Status Register (PARCSR)
Bit

Name

DEC MODE

Description

When this bit is set, the DUP11

logic operates in a manner compatible with

the DDCMP or BISYNC protocols. If this bit is clear then the device
operates as an SDLC or ADCCP station.

As a DDCMP or BYSYNC type interface, the receiver logic is synchronized

to the transmitting station when two or more consecutive SYNC characters
have been recognized.

The SYNC character used in the system must be loaded into the low byte
of the PARCSR before the RCVEN bit is set.

The transmitter logic has no ability to idle SYNC characters from the low
byte of the PARCSR. When it is required to transmit SYNC characters, the
program must load the SYNC character into the TXDBUF. The program
should also set the TSOM bit in the TXDBUF when the SYNC character is

loaded. This is done to inhibit the inclusion of the SYNC character in the
computation of the transmit CRC check character, if CRC is not inhibited.

Setting the TSOM also suppresses the setting of the TXDAT LATE (transmit data late) bit. This is useful if the need to idle SYNC’s existed. In

this case, the program would load the SYNC character into the TXDBUF
along with the TSOM bit, and the SYNC character would be transmitted
until the program initiated a new operation. During this period, the servicing of the TXDONE could be disregarded without causing the TXDAT
LATE error.

This bit is program write and is cleared by INIT or device reset.
Reserved

14,13
12

SEC MODE

Used with SDLC family protocols only. Cleared for DDCMP and BISYNC

(Secondary Mode

operation.

Select)

When this bit is cleared, the device operates as a primary station. All data
subsequent to the last received flag character is presented to the program
until the termination flag is received.

Secondary station operation is in effect when this bit is set. In this mode,
only messages that are prefixed with the correct secondary station address
are presented to the program. The Secondary Station Address must have
been loaded into the low byte of the PARCSR before the RCVEN bit was

set. The actual address character is not presented to the program in the
secondary mode.

If extended secondary addresses are used, (i.e., 16 bit address), the first

8 bits of the address can be detected by the hardware. The software must
confirm the next eight bits of address.

This bit is program write and is cleared by INIT or device reset.

Table 3-4 (Cont)

Bit Descriptions for Parameter Control and Status Register (PARCSR)
Bit

Name

Description

11,10

Reserved.

NO CRC
(CRC Inhibit)

When set, this bit
inhibits the transmission of the CRC check
character and testing of the CRC error detection logic during
reception.

This bit is program write and is cleared by INIT or device reset.
8

7-0

Reserved.

ADREC + SYNC

This register contains the desired secondary station address when operating

(Secondary Station

in the SDLC or ADCCP secondary mode. The contents of this register is

Address Register or

compared to the character received in the shift register (excluding zeros

Receiver SYNC

inserted for transparency) subsequent to the last received flag character.

This register is used by the receiver logic only.

Bit 00 is the least significant and bit 07 is the most significant.
These bits are program write and are cleared by INIT or device reset.

SECONDARY STATION ADDRESS
OR RECEIVER SYNC REGISTER

RESERVED | SECONDARY | RESERVED | RESERVED

(ADREC
+ SYNC)

MODE

SELECT

{SEC MODE)
DEC MODE

RESERVED

CRC
INHIBIT

(NO CRC)
1-3339

Figure 3-4

Parameter Control and Status Register Format

3-20

Table 3-5
A WPFAY

Bit Descriptions for Transmitter Control and Status Register (TXCSR)
Bit

Name

Description

TXDAT LATE

This bit is set by the transmitter logic when the program response time to

(Transmitter Data

the transmitter Done bit is longer than the specified time frame.

Late Error)
When this bit is set and the SDLC or ADCCP mode is selected, the transmitter idles abort characters until either a new message is started or the

Send bit is cleared.
In DDCMP mode, the line is held in the mark state until a new message is
initiated.

The program must respond to the TXDONE bit by loading the TXDBUF

within the following time frame:

(1/bps) 8 + N (bit time)
N = number of zeros inserted to maintain transparency, SDLC or ADCCP
mode only.
This bit is program read and is cleared by INIT, device reset, or by setting
the TSOM bit.
14

TX MAINT DATA OUT

The function of this bit is to provide a monitoring point of serial output

(Maintenance Transmit

data of the transmitter for the diagnostic program when using the internal

Data Out)

maintenance mode.

This bit is program read during internal maintenance mode only and is
cleared by INIT or device reset.
13

MAI SS CLK

This bit is used to simulate the transmitter and receiver clock for diagnostic

(Maintenance Clock)

purposes only. Using it in the internal maintenance mode, the diagnostic
has the ability to single step the interface with respect to the handling of

data.
A 0 to 1 transition of this bit causes the transmitter to transfer one bit of
information to the serial line.
A 1 to O transition of this bit causes the receiver to shift the contents of
the receiver shift register and sample the serial input line.

This bit must be cleared during the user mode.

This bit is program read/write and is cleared by INIT or device reset.
12,11

MAI SELB and MAI

These two bits are used together to select the maintenance mode of the

SELA (Maintenance

interface.

Mode Select B and A)

3-21

Table 3-5 (Cont)
Bit Descriptions for Transmitter Control and Status Register (TXCSR)

Bit
12,11 (cont)

Name

Description
Bit 12

Bit 11

(Select B)

(Select A)

0 User mode

1 External maintenance mode

0 Internal maintenance mode

1 System test mode

1 = bit set

0 = bit cleared.
The user mode is the normal operating mode with all level conversion

enabled. The modem is expected to provide all necessary clock signals

with a 50/50 duty cycle in accordance with the RS334 standard. The
maximum rate is 10 kHz.

External maintenance mode provides complete checking of all interface

components including level converts and cables.

The clocking for this mode is provided by a free running clock contained
within the interface at a 10 kHz + 20% rate asynchronous to the program.
This mode can be used in some circumstances to verify the operation of
systems software.

When this mode is utilized, the device is disconnected at the modem and a

maintenance turn-around connector (H325) is used in place of the modem
at the end of the cable.
The internal maintenance mode provides a means of analyzing ninety
percent of the interface without disconnecting the modem. The interface

to the modem cannot be diagnosed when this mode is used (i.e., level
converts and cables).
Fault isolation is greatly enhanced by this mode since the diagnostic pro-

gram supplies the data set clocking via the maintenance clock bit. Data
being transmitted can be monitored on a bit by bit basis at the Maintenance

Transmit Data Out bit. The receiver input can be simulated by either the
output of the transmitter or by the Maintenance Input Data bit.
The system’s test mode provides asynchronous bus interaction between this

device and other devices on the Unibus. Data set clocking is simulated by
a free running clock contained on the module at S kHz + 20%. This clocking
is asynchronous to the operation of the program. When this mode is used,
the device may remain connected to the modem.
Receiver and transmitter clocking and data level conversion is inhibited.
Modem control signals are not inhibited from being received or transmitted.

Transmitted data is internally looped from the transmitter output to the
input of the receiver. 1i’s assumed ihai sysiem iesi prograrns will uiilize
this mode.

3-22

T_LEi_

)

1avie 5>-5 {Loiitj

Bit Description for Transmitter Control and Status Register (TXCSR)

Bit

Name

11,12

Description
This bit is program read/write and is cleared by INIT or device reset.

(cont)
10

MAI DATA

When the internal maintenance mode is used this bit can be used as the

(Maintenance

receiver serial input.

Input Data)
When this bit is set and the maintenance clock bit makes a 1 to O transition,
a logical 1 is transferred into the receiver shift register.

This bit is program read/write and is cleared by INIT or device reset.
9

TXACT

The function of this bit is to indicate the current state of the DUP11

(Transmitter Active)

transmitter logic.

When the transmitter has been previously in the idle state, (i.e., SEND
cleared) and a new message is initiated, this bit is set after a one half bit
time delay subsequent to the presentation of the first bit to the serial line.
When this bit is clear, the transmitter logic is in the idle state and the serial

line is held in the mark state. The idle state can be entered by clearing the
SEND bit in this same register.

The idle state is entered synchronously with the data stream and is also
dependent on the DEC MODE, CRC INHIBIT and TEOM bits. Once the
idle state is entered, all transmitter timing and internal control logic is reset.
If the SEND bit is cleared and the TEOM bit is not asserted, the character
currently being transmitted from the transmitter shift register is completed
and the line goes to the mark state. The TXDONE bit is not asserted by
the completion of this character. After a one half bit time delay, the TXACT

bit is cleared by the DUP11 hardware. This off transition of TXACT causes
the TXDONE bit to be set.
The following description assumes that the SEND bit is being cleared within
the same character frame as the assertion of TEOM. In the SDLC mode, the

transmitted sequence consists of the CRC character (if enabled) and a terminating flag. In the DDCMP mode, the CRC character, if enabled, is transmitted.
If these conditions are met, the TXACT bit is cleared 1-1/2 bit times after the
last character of the sequence. The transition of the TXACT bit causes TXDONE
bit to be set.
If DEC MODE is selected and CRC is not inhibited, the character currently
being serialized is completed and followed by the automatic transmission

of the CRC check character. In this case, the CRC check character is

considered the last character of the sequence. If CRC is inhibited, the
character currently being serialized is the last character of the sequence.

3-23

Tabie 3-5 (Cont)
Bit Description for Transmitter Control and Status Register (TXCSR)
Bit

Name

9 (Cont)

Description
When the DEC MODE bit is cleared and CRC is not inhibited, the character

currently being serialized is completed. The CRC check character follows
this character. Subsequent to the check character, one terminating flag

character is transmitted. This flag character is considered the last character
of this sequence.
If the CRC INHIBIT bit is asserted, the CRC check character is omitted and
the flag character is transmitted subsequent to the character being serialized.
The flag character is the last character of this sequence.
The one half bit time delay involved with the assertion of TXDONE in this
case is useful in the manipulation of the Clear to Send line. At this time,

the Request to Send line can be cleared on most modems without losing
the last character.

If the transmitter is left enabled (SEND is asserted) and TEOM is also left asserted following the transmission of a sequence, continuous flag characters are

transmitted until SEND or TEOM is cleared. The current character being trans-

mitted is completed.

This bit is program read and is cleared by INIT or device reset.
DEVICE RESET

Device reset and the Unibus Initialize signal perform identical functions
with respect to the DUP11.
When this bit is set, all components of the interface are initialized unless
the optional clear jumper is removed. When this jumper is removed, the
modem control signals emanating from the device (SEC XMIT, ATS, and

DTR) are not affected. This bit is a 1 us one-shot and self clears.
With the optional clear jumper installed, all bits in the interface are cleared
with the exception of the transmitter Done bit. Program access should not
be made while this bit is set.
Both configurations of this jumper are supported by diagnostics.
This bit is program write and is cleared by INIT or device reset.

TX DONE

This bit is set when the transmitter data buffer is availabie for a new

{Transmitter Done)

character. This occurs either as a resuii of an INIT, device reset or when a

character is transferred from the TXDBUF into the transmit shift register.
If the transmitter is entering the idle state, (i.e., SEND is cleared during
the current message), the off transition of the TXACT bit causes TXDONE
to assert, not the completion of the current character.
The TXDONE bit also is set whenever a SYNC, FLAG, or ABORT character

has completed transmission, providing the SEND bit is asserted. The TX
DATA LATE bit will not assert if a FLAG or ABORT sequence is being
transmitted. The transitions of TXDONE can be used to count the number

of fill characters transmitted. If this is done, the TXDONE bit can be
cleared by reloading the TXDBUF with either TSOM if FLAGS or SYNCS
are being used to fill with, or TXABORT, if ABORT characters are used.

3-24

IR TN

Y7o

1aDi€ 5-3 Lomnt)

Bit Description for Transmitter Control and Status Register (TXCSR)
Bit

Name

7 (Cont)

Description
For timing information related to the TXDONE bit and its relationship to

the data stream and control bits, refer to the print set.

The program must respond to the assertion of this bit within the previously
cited time span in order to avoid data under run errors.
If the Transmitter Interrupt Enable bit is set, the setting of this bit creates
an interrupt request.

This bit is program read. It is cleared by writing into the TXDBUF and is
set by INIT, device reset or clearing TXACT.
TXITEN

When set, this bit allows a program interrupt request to be generated by

(Transmitter Interrupt

the TXDONE bit.

Enable)

All interrupt requests should be serviced at a processor level equal to or
greater than the devices Bus Request level which is shipped at level 5.

This bit is program read/write and is cleared by INIT or device reset.
Reserved.

SEND

This bit is used to enable the transmitter logic. Once enabled, the trans-

mitter starts transmission of a message when the TSOM bit is detected in
the TXDBUF.

This bit should remain set until the TEOM bit is loaded into the TXDBUF.
If this bit is cleared at any other time, the current character is finished and
the transmitter output goes to a mark hold state.
If SEND is cleared while TEOM is still asserted, the current character being
transmitted is completed. Following this character, and depending on the

protocol being used, any necessary CRC and/or control characters are transmitted.

For further information, refer to the TXACT bit in this same register.

This bit is program read/write and is cleared by INIT or device reset.
HALF DUP

When this bit is set, operation is in half-duplex mode. In half duplex mode, the

(Half Duplex/Full

the receiver is disabled if the SEND bit in the TXCSR is asserted.

Duplex)

This bit is read/write and is cleared by INIT or device reset.
2,1,0

Reserved.

3-25

j——‘

MAINTENANCE

TRANSMIT
DATA OUT

MODE
SELECT
A AND B

(TX MAINT
DATA OUT)

(MAT SEL B AND
MAISEL A)

TRANSMITTER

TRANSMITTER {TRANSMITTER | RESERVED
ACTIVE
(TXACT)

TM~

HALF

DONE
(TX DONE)

DUPLEX
FULL

DUPLEX
(HALF DUP)

MAINTENANCE

DEVICE

TRANSMITTER

DATA LATE

CLOCK

INPUT DATA

RESET

INTERRUPT

ERROR

(MAI SS CLK)

(MATI DATA)

SEND

ENABLE

(TXDAT LATE)

(TXITEN)

Figure 3-5

Transmitter Control and Status Register Format

3-26

RESERVED

Table 3-6
Bit Descriptions for Transmitter Data Buffer Register (TXDBUF)

Bit

Name

Description
Reserved.

RCRCTIN

This bit is provided for maintenance purposes only and is
enabled only in internal maintenance mode. The function of this bit
is to provide a higher degree of error isolation when diagnosing the

receiver CRC register.

RCRCTIN is the input to the least significant bit of the receiver CRC
register.

Refer to note 1 for further information.
This bit is program read during the internal maintenance mode only.
13
12

Reserved.
TCRCTIN

This bit is provided for maintenance purposes only and is

enabled only in internal maintenance mode. The function of this
bit is to provide a higher degree of error isolation when diagnosing
the transmitter CRC register.

TCRCTIN is the input to the least significant bit of the transmitter

CRC register.
Refer to note 1 for further information.
These bits are program read during the internal maintenance mode

only.

NOTE 1: The true state of these bits is dependent on the protocol
being tested.
The RCRCTIN and TCRCTIN bits are the XORed inputs to the
respective CRC shift register. Data from either the transmitter or
receiver data shift registers is presented as a logical 1 being the high
state to the XOR gate.

The state of data presented to the XOR gate from the most significant
bit of either CRC shift register depends on the state of the DEC MODE

bit.

3-27

Table 3-6 (Cont)

Bit Descriptions for Transmitter Data Buffer Register (TXDBUF)
Bit

Description

Name

When DEC MODE is set, a logical 1 output from bit 15 of the respective

CRC register is defined as being high. A logical 0 is defined as being low.

(cont)

When DEC MODE is cleared, a logical 1 output from bit 15 of the

respective CRC register is defined as being low. A logical 0 is defined as
being high.

MAINTT

(Maintenance Timer)

The function of this bit is to provide a known timing reference for diagnostic
programming purposes.only. This bit is enabled only in the external or
systems test modes. A transition of this bit occurs every 100 microseconds.
The frequency of this clock is 5 ke £ 20%.

This bit is program read in external or systems test mode. It is cleared by
INIT or device reset.
10

TXABORT

(Transmit Abort)

When this bit is asserted, an abort sequence is transmitted subsequent to
the serialization of the current character, if a character is in process. The
SEND bit should be asserted when the Abort sequence is to be transmitted.

The TXDONE bit is set at the end of each abort character. An abort character is defined as being more than seven contiguous 1 bits.

This bit is program read/write and is cleared by INIT and device reset.
TEOM

(End of Transmitted

Message)

The function of this bit is to terminate the message in progress. How the
message is terminated is dependent on the transmitter’s mode of operation
as controlled by the information contained in the PARCSR and the state
of the SEND bit.

If the transmitter is to enter the idle state after the completion of the
current sequence, the TEOM bit is set and SEND is cleared by the
program. Refer to the description of the TXACT bit.
Termination of a message in DDCMP or BISYNC mode (DEC MODE set)
should always cause the transmitter to enter the idle state.
Termination of a message in SDLC or ADCCP mode can be achieved in one

of two ways. Upon completion, the idle state is entered, or flag characters
are idled at completion of the message until the next message is initiated.
If upon completion of a message sequence, flags are to be idled, the SEND
and TEOM bits should remain set.

Flag characters are transmitted until a new message is initiated by
clearing the TEOM bit and loading the data. The recommended procedure is to load the new data and clear TEOM in the same operation
that accesses the TXDBUF.
This bit is program read/write and is cleared by INIT or device reset.

3-28

Table 3-6 (Cont)

Bit Descriptions for Transmitter Data Buffer Register (TXDBUF)
Bit

Name

Description

TSOM

The function of this bit is to initiate the start of a new message if the

(Transmit Start

transmitter is in the idle state (TXACT = 0).

of Message)
The assertion of this bit causes the internal transmitter CRC register to

be re-initialized. The reiniialization of CRC register and the transfer of
the first bit of information occurs within two bit times of the assertion
of this bit.

If the DEC MODE bit is asserted, the procedure for initiating the start of

the message requires that the SYNC character be loaded into the TXDBUF
along with the TSOM bit. The character loaded into the buffer is transmitted as the SYNC character until the TSOM bit is cleared. This character
is not included as part of the CRC computation. When the TSOM bit is

cleared, the SYNC character currently being serialized is finished and is
followed by data. All data characters are included in the CRC check character computation.

If the DEC MODE bit is cleared, the setting of this bit causes the initiation of
a message using the SDLC or ADCCP protocols. A flag character is automatically transmitted as long as this bit remains asserted. When data is to be transferred, this bit is cleared by the program and the data is loaded into the
TXDBUF. At the completion of the current flag character, the actual transmission of data begins.

This bit should not be set when another message is actively being transmitted.
Setting this bit also causes the TXDAT LATE bit to be cleared.
The TXDONE bit is asserted at the completion of each flag or SYNC character, when this bit is asserted.

This bit is program read/write and is cleared by INIT or device reset.
7-0

TXDBUF

This register is loaded with the information to be transmitted. All data is

(Transmitter Data

treated as eight bit characters.

Buffer)

If the DEC MODE bit is set, the SYNC character to be transmitted must be
loaded into this register prior to initiating the synchronization process.

The least significant bit of this register is bit 00. Bit 07 is the most significant.

These bits are program read/write and are cleared by INIT or device reset.

3-29

—

RCRCTIN

RESERVED

TCRCTIN

RESERVED

TRANSMIT

ABORT

START OF

(TXABORT)

MESSAGE
(TSOM}

MAINTENANCE

T1MER

(MAINTT)

TRANSMITTER

DATA

BUFFER {(TXDBUF)

END OF
TRANSMITTED

MESSAGE
(TEOM)

11-3341

Figure 3-6

Transmitter Data Buffer Register Format

3-30

APPENDIX A
PDP-11 MEMORY ORGANIZATION

AND ADDRESSING CONVENTIONS

The PDP-11 memory is organized in 16-bit words consisting of two 8-bit bytes. Each byte is addressable and
has its own address location: low bytes are even numbered and high bytes are odd numbered. Words are ad-

dressed at even numbered locations only and the high (odd) byte of the word is automatically included to
provide a 16-bit word. Consecutive words are therefore found in even numbered addresses. A byte operation
addresses an odd or even location to select an 8-bit byte.
The Unibus address word contains 18 bits identified as A(17:00). Eighteen bits provide the capability of addressing 256K memory locations each of which is an 8-bit byte. This also represents 128K 16-bit words. In
this discussion, the multipler K equals 1024 so that 256K represents 262,144 locations and 238K represents
131,072 locations. The maximum memory size can be used only by a PDP-11 processor with a memory man-

agement unit that utilizes all 18 address bits. Without this unit, the processor provides 16 address bits which
limits the maximum memory size to 64K (65,536) bytes or 32K (32,768) words.

Figure A-1 shows the organization for the maximum memory size of 256K bytes. In the binary system, 18
bits can specify 2!8or 262,144 (256K) locations. The octal numbering system is used to designate the address.
This provides convenience in converting the address to the binary system that the processor uses as shown
below.

The highest 8K address locations (760000-77777) are reserved for internal general registers and peripheral devices. There is no physical memory for these addresses; only the numbers are reserved. As a result, programmable memory locations cannot be assigned in this area; therefore, the user has 248 bytes or 124K words to
program.

A PDP-11 processor without the memory management unit provides 16 address bits that specify 2!5or 65,536
(64K) locations (Figure A-2). The maximum memory size is 65,536 (64K) bytes or 32,768 (32K) words. Logic
in the processor forces address bits A(17:16) to 1s if bits A(15:13) are all 1s when tne processor is master to
allow

generation of addresses in the reserved area with only 16-bit control.

(16

{ IS

|14

{13 | 12

|11

{10

[09

[O8

[0O7

{06

[0S

|04

{03 | 02

]

A-1

| O1]

1
1

OO {

AddressBit

0 | Binary
Octal

os|o7

l1s

le— 16 BIT DATA WORD —

000001

LOW BYTE

HIGH BYTE

000000

000002

000003

USER ADDRESS SPACE
AVAILABLE USING 18

|
|

ADDRESS BITS ON
PDP-11 PROCESSOR
WITH MEMORY

____A

MANAGEMENT OPTION.

]

INCLUDES 248K (253,952)
BYTES OR 124K (126,976)
WORDS.

757776

757777

760000

760001

HIGHEST 8K (8192)

/‘\

)
g BYTES OR 4K (4096)

WORDS RESERVED FOR

_,4"’_\‘

DEVICE REGISTER
ADDRESSES.

777776

*7 7777

LAST ADDRESS IS BYTE NUMBER 262,143,,

MAXIMUM SIZE WITH 18 ADDRESS BITS IS 256K(262,144) BYTES OR 128K {131,072} WORDS.
11-18890

Figure A-1 Memory Organization for Maximum Size Using
18 Address Bits

00
o08lo7
lis
le— 16 BIT DATA WORD —
LOW BYTE

HIGH BYTE

000001

000000

000003

000002

USER ADDRESS SPACE

AVAILABLE USING 16
ADDRESS BITS ON

PDP-11 PROCESSOR

WITHOUT MEMORY
MANAGEMENT OPTION.

.
_—]

INCLUDES 56K (57,344)
BYTES OR 28K (28,672}
WORDS.

157776

157777

160000

160001

i
ADDRESSES 160000177777 ARE CONVERTED

TO 760000 -777777 BY

.
T

—
j

THE PROCESSOR. THUS,
THEY BECOME THE

HIGHEST 8K (8192) BYTES
OR 4K(4096) WORDS

177776

*177777

RESERVED FOR DEVICE
REGISTER ADDRESSES.

LAST ADDRESS IS BYTE NUMBER 65,5354

MAXIMUM SIZE WITH 16 ADDRESS BITS IS 64K (65,536) BYTES OR 32K(32,768} WORDS.
t1-1689

Figure A-2

Memory Organization for Maximum Size Using
16 Address Bits

A-2

Bit 13 becomes a 1 first at octal 160000 which is decimal 57,344 (56K). This is the beginning of the last 8K
bytes of the 64K byte memory. The processor converts locations 160000-177777 to 760000-777777 which relccates these last 8K bytes (4K words) to the highest locations accessible by the bus. These are the locations
that are reserved for internal general register and peripheral device addresses; therefore, the user has 57,344
(56K) bytes or 28,672 (28K) words to program.

Memory capacities of 56K bytes (28K words) or under do not have the problem of interference with the reserved area, because designations less than 160000 do not have a binary 1 in bit A13. No addresses are converted and there is no possibility of physical memory locations interfering with the reserved space.

PDP-11 core memories are available in 4K or 8K increments. The highest location of various size core memories are shown below.

Memory Size

Highest Location

K-Words

K-Bytes

(Octal)

8
16

017777
037777

057777

077777

117777

137777

157777

A-3

Reader’s

DUP11 BIT SYNCHRONOUS INTERFACE

’

Comments

USER’S MANUAL

EK-DUP11-OP-001

Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of
our publications.

What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, weli
written, etc.? Is it easy to use?

CUT OUT ON DOTTED LINE

What features are most useful?

What faults do you find with the manual?

Does this manual satisfy the need you think it was intended to satisfy?
Why?

Does it satisfy your needs?

Would you please indicate any factual errors you have found.

Please describe your position.

Name

Organization

Street

Department

City

State

Zip or Country

FIRST CLASS

PERMIT NO. 33
MAYNARD, MASS.

BUSINESS REPLY MAIL

NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES
Postage will be paid by:

Digital Equipment Corporation

Technical Documentation Department
Maynard, Massachusetts 01754

digital equipment corporation

Printed in

U.S.A.