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XX-A0D63-82-1

May 1976

192 pages

Original

4.9MB

Document:	PDP-15/76 Hardware Familiarisation Student Guide
Order Number:	XX-A0D63-82
Revision:	1
Pages:	192
Original Filename:	http://bitsavers.org/pdf/dec/pdp15/hardware/PDP15-76_HardwareTraining_1976.pdf

OCR Text

ctH--0u~ tOrs/o y
PDP-lS/76
HARDWARE FAMILIARIZATION
Student Guide
R."iaion 1

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no rc- .
sponsibility for any errors which may appear in
this manual.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

FLIP CHIP
DIGITAL

PDP
FOCAL
COMPUTER LAB

COURSE:

- OF-3

PDP-15/76

.1\ 1

MONDAY
8: 15

9:00

......

SYSTEM
BLOCK DIAGRAM

10:00

EQUIPMENT

11:00

FAMILIARIZATION

12: 00

1:00

POWER
DISTRIBUTION

2:00 ..

LAB

til

3:00

PROJECT

4:00

#1
.•

5:00

TUESDAY

WEDNESDAY

LOGIC

CONSOLE
CONTROL
TIMING

FRIDAY

ME-IS
MEMORY (DIFFERENCE)

LOADING A
OOS RESTORE

IT[

USE OF EDIT

FAMILIARIZATION
CPU
BLOCK DIAGRAM.
CPU TIMING.
~
CPU DECODE
of MRI.

CONSOLE
SWITCH&BOARD
DISPLAY PANEL

MEMORY
{MM-15}

LOGIC FLO~'
OF A
DEPOSIT FUNCTION

E.A.E HARDWARE

PROGRAMMI NG
ASSIGNMENT

MRI
~
OPERATION FLOW
B.D. (DAC & LAC)

LAB

E.A.E FLOWS

LAB

CPU
~
INTERFACING WITH
MEMORY. LOGIC
DAC & LAC

PROJECT

IT:

CONSOLE
KEY FLOW

THURSDAY

USE OF ASSEMBLER
LOADING PROGRAMS

l1L

LAB

PROJECT

CPU
~
INSTRUCTION SET
a) MRI

b) OPERATE
REGISTER CONT.
d) IND~XR REGfSTER
X E INS .

USE OF
CONSOLE

EAE INST. SET

PROJECT

#3
SCOPE PROJECT

LOADING SYSTEM
SOFTWARE AND
USER PROGRAMS

COURSE:

BLOCK
DIAGRAM OF
PROGRAM CONTROL

~
PROGRAM

THURSDAY
HARDWARE
READ-IN

TTY
CONTROLLER

FRIDAY

fi4

lOT
10:00

INPUT OUTPUT

11:00

FACILITY

INTERRUPT

b) TRANSMITTER

FACILITY

BA-I5
BLOCK DIAGRAM
PC-15

AUTOMATIC

a) RECEIVER

DEVICES

9:00

WEDNESDAY

TUESDAY

MONDAY
~

8:15

WEEK 2 OF 3

PDP-15/76

PROGRAM
INTERRUPT

ll2.

L!2

MEMORY

POWER

PAPER TAPE
READER/PUNCH

PROTECT

FAIL
CONTROL

RELOCATE

9> 12:00

1:00

LAB

REAL

2:00

PROJECT

TIME
CLOCK

3:00

REVIEW

4:00

5:00

tOURSE:

PDP-15/76

MONDAY

TUESDAY

INTRODUCTION
TO
DATA CHANNEL

9:00

3 CYCLE

10:00

BREAK

THE
SYSTEM

11:00

DATI & DATa

BLOCK
DIAGRAM

12: 00

1:00

SINGLE

2:00

CYCLE BREAK

3:00

INC MB

5:00

ADD

XVM

TO
MEMORY
REVIEW

~
LAB

PROJECT

FRIDAY

THURSDAY

IE.

8: 15

4:00

WEDNESDAY

INTRODUCTION
TO
UNICHANNEL
BLOCK DIAGRAM

BLOCK DIAGRAM
OF
MEMORY CONTROL

TABLE OF CONTENTS

SECTION
1.

SYSTEM BLOCK DIAGRAM
EQUIPMENT FAMILIARIZATION
POWER DISTRIBUTION
LOGIC FAMILIARIZATION

CENTRAL PROCESSOR BLOCK DIAGRAM
A) MEMORY ORGANIZATION
'B) BLOCK DIAGRAM OF CPU INTERFACED TO MEMORY

CENTRAL PROCESSOR TIMING
A) MAJOR STATES, TIME STATES, PHASES
B) DECODING OF MEMORY REFERENCE INSTRUCTIONS
(GENERAL)

MM-15 MEMORY BLOCK DIAGRAM
A) ADDRESS SELECTION
B) MEMORY CONTROL
C) MEMORY CPU DIALOGUE

MEMORY REFERENCE INSTRUCTION DATA FLOW (B.D)
A) LAC - MEMORY READ OPERATION
B) DAC - MEMORY WRITE OPERATION

CENTRAL PROCESSOR INTERFACING WITH MEMORY
(LOGIC OPERATION)
A) LAC - READ INSTRUCTION
B) DAC - WRITE INSTRUCTION

CENTRAL PROCESSOR BLOCK DIAGRAM
A) MEMORY REFERENCE INSTRUCTION
B) OPERATE INSTRUCTION
C) REGISTER CONTROL INSTRUCTIONS

D) INDEX, REGISTER TRANSFER INSTRUCTIONS

TABLE OF CONTENTS

SECTION
8.

CONSOLE OPERATIONS
A) CONSOLE KEY FLOWS
B) CONTROL CONSOLE TIMING
C) SWITCH BOARD
D) DISPLAY BOARD
E) DETAILED FLOW OF A DEPOSIT FUNCTION

ME-IS MEMORY
THE DIFFERENCES BETWEEN THE ME-IS AND THE
MM-1S MEMORIES

10.

EAE INSTRUCTIONS
A) SET UP INSTRUCTIONS
B) SHIFT INSTRUCTIONS
C) NORMALIZE INSTRUCTIONS
D) MULTIPLY INSTRUCTIONS
E) DIVIDE INSTRUCTIONS

11.

E.A. E. HARDWARE
A) SHOW LOGIC
B) USE EAE FLOW CHART

12.

PROGRAMMING - USING THE FOLLOWING INSTRUCTION SETS
A) MEMORY REFERENCE INSTRUCTIONS
B) OPERATE INSTRUCTIONS
C) REGISTER CONTROL INSTRUCTIONS
D) INDEX, REGISTER TRANSFER INSTRUCTIONS

13.

BLOCK DIAGRAM OF PROGRAM CONTROLLED DEVICES
A) TTY RECEIVER
B) TTY TRANSMITTER
C) PAPER TAPE PUNCH

TABLE OF CONTENTS

SECTION

14.

INPUT
A)
B)
C)
D)

15.

PROGRAM INTERRUPT FACILITY
(PI)
A) PROGRAM INTERRUPT GENERAL INFORMATION
B) PROGRAM INTERRUPT BLOCK DIAGRAM
C) PROGRAM INTERRUPT LOGIC & TIMING
D) PROGRAM INTERRUPT FLOW CHART

16.

BA-IS
A)
B)
C)

17.

MEMORY PROTECT AND RELOCATE
A) MEMORY PROTECT
1. GENERAL INFORMATION ON MEMORY PROTECT AND
AND MEMORY PROTECT BLOCK DIAGRAM
2. TRAP CONDITIONS
3. MEMORY PROTECT FLOW DIAGRAM
B) MEMORY PROTECT AND RELOCATE
1. GENERAL INFORMATION ON MEMORY PROTECT & RELOCATE
AND MEMORY PROTECT RELOCATE BLOCK DIAGRAM
2. MEMORY PROTECT & RELOCATE FLOW CHART
C) TRAP LOGIC FAMILIARIZATION

OUTPUT, FACILITY
(lOT'S)
lOT'S GENERAL INFORMATION
lOT BLOCK DIAGRAM
GENERATION OF lOT DONE
lOT LOGIC & TIMING
E) lOT FLOW CHART

PERIPHERAL EXPANDER
BA-IS BLOCK DIAGRAM
BA-IS GENERAL INFORMATION
PAPER TAPE READER
1. ALPHA MOOE
2. BINARY MODE
D) FLOW DIAGRAM OF READER SELECT ALPHA
E) BASIC DIAGRAM OF THE PAPER'TAPE READER
F) HARDWARE READ IN

TABLE OF CONTENTS

SECTION
18.

19.

20.

AUTOMATIC PROGRAM INTERRUPT (API)
A) MI04 SIMPLIFIED
B) API BLOCK DIAGRAM
C) BLOCK DIAGRAM OF GRANT FUNCTION
D) API BLOCK DIAGRAM AND TIMING

POWER CONTROL
A) POWER FAIL CONTROL DIAGRAM
B) POWER FAI L UP DOWN SEQUENCE
1. PI ENABLED
2. API ENABLED
C) AUTOMATIC RESTART

REAL TIME CLOCK
A) I/O PROCESSOR BLOCK DIAGRAM
B) REAL TIME CLOCK FLOW CHART

(FLOWS)

TABLE OF CONTENTS

SECTION
21.

22.

DATA CHANNEL
A) GENERAL REQUIREMENTS OF DEVICES ON BUS
1. RF-15 FIXED HEAD DISC
TC-15 DEC TAPE
2. RP-15 DISC PACK
B) BLOCK DIAGRAM OF I/O PROCESSOR
C) BLOCK DIAGRAM OF DEC TAPE
D) 3 CYCLE BREAK DESCRIPTION
E) 3 CYCLE DCH IN TIMIKG DIAGRAM

UNICHANNEL
A) BASIC BLOCK DIAGRAM OF THE UNIBUS SYSTEM
B) BLOCK DIAGRAM OF MEMORY CONTROL PDP-15/76
C) BLOCK DIAGRAM OF MX15B MEMORY REQUEST CONTROL
D) PDP15 - READ OPERATION BLOCK DIAGRAM
E) PDP15 - WRITE OPERATION
F) BLOCK DIAGRAM OF UNIBUS SYSTEM EXPAND
INTERRUPT LINK.
G) BUS REQUEST BLOCK DIAGRAM
H) DETAILED BUS REQUEST BLOCK DIAGRAM FROM
THE DRIIC #1
I) BLOCK DIAGRAM - DATA IN TRANSFER
J) DATA CONTROL CHART
K) BLOCK DIAGRAM DATOB
L) API REQUEST
1. PDP-II GENERATES API REQ (JOB DONE)
2. BLOCK DIAGRAM DATOB
API ADDRESS
M) BLOCK DIAGRAM - MODIFY BYTE LOCATION IN COMMON
MEMORY
N) TIMING DIAGRAM OF A DATIP
TIMING DIAGRAM OF A DATOB
0) ADDRESS MODIFICATION MX15-B
1. ADDRESS CONSIDERATIONS
2. EXAMPLE OF PDP-II ADDRESS MODIFIED TO
ADDRESS COMMON MEMORY
3. BASIC BLOCK DIAGRAM OF ADDRESS MODIFICATION
4. DETAILED BLOCK DIAGRAM OF ADDRESS MODIFICATION
5. ADDRESSING CHART.

TABLE OF CONTENTS

SECTION
23

XVM

MAIN GOAL OF COURSE
Have field service engineer or customer install, fix, and maintain
PDP-IS systems.
1.

System Block Diagram of PDP-IS System Objectives:
a)

Using the block diagram of the PDP-IS system, define the function
of each block

Define the purpose of the OW-IS

List the devices in the BB-IS and explain their function

List the options installed in the 2B-ls

List the two general types of Data Transfers.

Define program'control transfers

List high speed block transfers devices

Define the type of data transfers high speed devices use.

Using the equipment layout prints for the PDP-IS system have the
student install this system on paper then check work against the
PDP-IS in the lab. Student correct his own work.

Define priority if any on the BUS

1-1

MEMORY

,,~

I
C P U [L
J~

T
E
R
M
I
N
A
T.

lOP U

Ell

POSITIVE I/O BUS

I
CONSOLE

TTY

P
(04)

R
(03'

BB-15
KM,KT,API
(17-55 )

I
BA-15

DW-15

RP-15
63,64

RF-15
72,70

I
S
K

S
K

NEGATIVE
BUS
I-'

I
!IV

TC-59
(75,76)

.~
BASIC PDP-IS SYSTEM BLOCK DIAGRAM

TC-15
76,75

CENTRAL PROCESSOR BLOCK DIAGRAM
OBJECTIVES:

List the registers in the central processor and
explain their functions.

Define in writing how the multiplexor in the central
processor works.

Define in writing the address scheme for the MM-15
memory.

4. "Draw the block diagram of the memory processor
interface.

2-1

EA[
I-~'-'

-M1 ~'i 5C

[)SW~~ DSI'l=~------.::=~---===-·LR

1/0 BUS
171--_ _ _ _ _ _ _-vl

, '1' ~"':fr
;. .. flq
~

I\IIL

. "T~
~

-SUM ellS
to"," HQ

S~U:T L.

L ~ ~T_RT

oiTL
~I.'~A

______ _

.., M:)l <;'I4I~T

~l'45Ht~

,----Nl
_ _ _ _ _ _ .A l

M
U
X

~__~------~*-J

I l

2 Li)C ......1
~

ACiUI

~ I't"

!:> /'It 17

7 - L

l. AC 10

a OVE~hOW

<t SUM BUS 00

--------------_----1,

Instruction Execution BlocK

CENTRAL PROCESSING TIMING
OBJECTIVES:
1.

Upon request be able to explain during which major
states the central processor can receive an instruction
from memory.

Upon request be able to explain in wha~ major states do~s
the central processor decode and process the instruction.

List the three ways in which the central processor,
running under program control, cna be halted.

List the GRP decodes for any given memory reference
instruction.

3-1

CPU-RUNNING INSTRUCTIONS
MAJOR STATES

FETCH

EAE

DEFER

INC

EXECUTE
INSTRUCTION

TSOI

FLOW CHART
KP 76

TS02

QUESTIONS:
When does the CPU
receive an instruction?

TS03
t

,1~FETCH

I, 1~FETCH

t 1 ......INC
11~DEFER

14EX·ECUTE t 1~INC

I
I
I

I l-"7EXECUTE I 1~FETCH

114 EXECUTE t

t t l

: 14EAE
I 14EXECUTE

, l~FETCH

3-2

When does the CPU
decode & process
the instruction?

DECODES FOR MEMORY REFERENCE INSTRUCTIONS
(MRI)

GROUPS
MRI

DAC

,/ ~

JMS
DZM

J/ y'''
J/ JI

LAC

XOR

ADO

TAD

V-

i/'

XCT

SAD

JMP
REGISTERS

CAL

ISZ
AND

DFCODES LOCATED ON

KP 30

'/vi" L

,/ ;/

I
/
.I

MI IR IR IR IR IR

3-3

CPU-RUNNING INSTRUCTIONS
MAJOR STATES

FETCH

IN<:

EAE

DEFER

EXECUTE
INSTRUCTION

TSOI

FLOW CHAR'r
KP 76

TS02

-TS03

t 1~ FETCH

I 1 ~ FETCH

t 1---? INC
f 1~ DEFER

,l~ FETCH

1~EXECUTE t

t 1 - EAE
f
I 1~EXECUT~

1-+INC

t 1~FETCH

t 1~ EXECUTE I

1~EXECUTE ,

I
I

DECODES FOR MEMORY REFERENCE INSTRUCTIONS
(MRI)
GROUPS
MRI

DAC

.J ,.;

JMS

.; ./

CAL

DZM
LAC

XOR
ADD
TAD
XCT

.; V

DECODES LOCATED ON
KP 30

vi
vi

.;
I
.; ..;
./ ..;
/

I
vi

..;

ISZ

AND

v'
v':

SAD

JMP

REGISTERS

MI IR IR IR IR IR

3-4

QUESTIONS:
When does the CPU
receive an instruction?
When does the CPU
decode & process
the instruction?

MEMORY - CENTRAL PROCESSOR BLOCK DIAGRAM

Name the regi~ters in the CPU and their functions
a)

PC - contains address in memory of next instruction to
be executed

OA - temporary storage of the operand address for all MRI

DS - console data switches

LR - used to set a limit on operations with the index register
or for storage

AC - retains results of arithmetic/logical operations program
controlled I/O transfers go thru AC

IR - 6 BITS 0-3 OPCODE BIT 4 indirect BIT
BIT 5 index BIT

MI - receives all data & instructions read from core

XR - used in indexed addressing operations, as a counter
or for storage

LINK - I BIT extension of accumulator

MO - contains all information going from CPU to memory data
lines

Memory Organization
a)

Bank Mode
Programs run in 8K partition

Page Mode
Programs run in 4K partition

Data paths between CPU and memory

4-1

MM-lS Memory Block Diagram
1.

Define a memory cycle

List the events that takes place in a read cycle

List the events that takes place in a write cycle

Draw a block diagram of rnemroy that can perform a
read, write cycle.

-Upon request be able to orally explain address decoding

Identify. the dialogue response to any signal on the memory
control lines (MeL).

4-2

RElID CURRENT

MEMORY

YES

WRITE CURRENT

CYCLE

ADDRESS
SELECTION

SELECTION

READ DATA
FROM CORE

DATA READ FROM
CORE LOST

SEND DATA

RECEIVES DATA
FROM CPU

TO CPU

WRITE
DATA BACK
INTO CORE

WRITE DATA
INTO
CORE

4-3

MEMORY BLOCK DIAGRAM
ADDRESS BITS

(MDT.I) ~

thrij

MM06

~ ~I

STROBE
MM06-MM09

MR8Q
ADR ACK
RD RST

ADDRESS
DECODING

MEMORY
COMTROL

MIlLS
DATA ACK

(

TIMING

)

INHIBIT
WRT CURRENT

)

MRLS ACK
DATA

MM09

ADDRESS
SELECTION

"Y" CURRENT
"X" CtJ2RENT

WRT
M

6 - 17

"X","Y"
CURRENTS

MEMORy BUSY

---,

MM06 -MM09

"CORE"

MDLte.....
STROBE

MM03-MM05

LD MB

)

INHIBIT
CURRENT

MM03-MMOS

DATA
BUFFER

DATA BIT A "0"
GENERATE INHIBIT
CURRENT

4-4A

MEMORY

MM19

KP27

MDL

<~~------~-------------KP59

KP26

PROCESSOR
SWITCH

MO-MDL

MO
KF
1...-----'32

CPU

MEMORY CPU INTERFACE

MUX

"y" SELECTORS

"y"

"x"

Q)
U)

1=1-)--U

MAOS(O)H

READ

TENS

::7

MAOS(O)H

RDX (1) H

S
a:I

II(

l!)

Selection

(+)

m£m
"X"

!xl

DRIVE

0238

..:

11 12

MA REGISTER

0164

DECODES 4096

CORE LOCATIONS
17

SELECTORS
D91

MA 05 (0) H
MA 05 (0) H ~ READ
RPX (1) H ~

READ

RIVE

DRIVE~RD
__Y
__(_I_)__
H_____

(+)

¥UPPER

I
U1

LOWER 4K LOGIC

STROBE

MA= 002542 for
DECODE

MB
17

QD
_so

LOGIC

MDL(I)L

RDRST:LDMI

BUS EN

READ CYCLE OF MEMORY - TAKES DATA OUT OF CORE, STROBES IT INTO THE Mill10RY
BUFFER, SENDS DATA TO CPU.

MEMORY CPU INTERFACE

CENTRAL PROCESSOR

MEMORY

MEMORY DATA LINES

(IS)

(BI-DIRECTIONAL)

"'I_~

' - ADDRESS
'----SELECTION

READ
REQ

...

MRD

READ
CONTROL

\WRITEI ----------__M_W_R__________~.~

......... - ...... - ...... --~-~--------

HOLD, CP ACTIVE
4. MO-- MDL
5. SET M REQ
6. CLEAR M REQ
7. CLEAR CP MEM REQ

READ/RESTORE

.....

M REQ

ADR ACK

.,.

HOLD

S. MDL--

WRITE
CONTROL

REQ

1. ADDRESS-- Me
2. SEND MRD
3. SET CP MEM REQ

tATA

f' "

------ --l. LOAD MA, CLEAR MB, SET
RD CON
2. SEND ADR ACK
3. READ DATA FROM CORE-- MB
4. CLEAR ADR ACK WHEN-M REO
5. MB-- MDL

RD RST

•

6. SEND RD RST
7. WRITE DATA TO CORE (MB-- CO RE)
S. SEND MRLS ACK

MRLS
.
9. SEND MRLS, CLR CP
ACTIVE
....
1 o. DATA ACK
~------------------------~.,~ 9. CLR BUS EN
1 l. CLEAR MRLS
4~~--~M~RL~S-A~C~K~------------~lO. REMOVE MB FROM MDL

-- - - - - -

l. ADDRESS--

CLEAR/WRITE

2. SEND MWR
3. SET CP MEM REQ
HOLD,CP ACTIVE
4. MO-MDL
5. SET M REQ
6. WAIT FOR ADR ACK
7. CLR M REQ. CP MEM
REQ HOLD
8. DATA-- MO-- MDL
9. SEND MRLS

1 o. CLR CP ACTIVE, CP
MRLS

M REQ

... 1. LOAD MA, CLEAR MB, SET WR CON

ADR ACK
4~1-----------_---1 2.

•

SEND ADR ACK

3. WAIT FOR MRLS

4. MDL--

4~~------------------------1 5. SEND MRLS ACK

6. WRITE DATA TO CORE
(MB-- CORE)

4-6

MEMORY REFERENCE INSTRUCTIONS
OBJECTIVES:

Using the central processor block diagram, describe
the flow of addressing core, receiving the data and
transfer it to the accumulator.

Using the central processor block diagram descirbe
the flow of addressing core, and transferring data
fram the accumulator into core.

List the address modes and describe their function.

MEMORY REFERENCE INSTRUCTIONS

LAC:

Contents of the memory location specified by the effective address
replaces the contents of the accumulator.

LAC:

o
(C) of HI

LOAD THE ACCUMULATOR
3 4 5

PC-A 01-05

SUM
BUS
Effective Address
"B"Bus

LD,MO,OA

MI
REG
DECODE
GRPl - MI
GRP3,5-IR
SML (START
MEMORY READ)

l-~[
MB

RD RST: LOAD MI

MI-B

00-17

NO SHIFT - D
Bus & Shift Bus
LOAD AC

5-2

1
CORE

MEMORY REFERENCE IMSTRO~lON
DAC - DEPOSIT ACCUMULATOR
The contents of the accumulator is deposited in the memory location
specified by the effective address. The accumulator remains unchanged.

"E" FIELD
~

(C)

of HI

of IR
BAC-+C BUS
(C)

6·

lL,.._O___4_.....LI_AD_R_F_I_E_LD_ _~1

......-------0

~ONLY

a---.......

A"
M

"A" BUS

O:ERAND ADDRESS
A

t----. . . .

--......

PC-A 1-5

MI-B
1'1
I
6

~_CORE

"B"

LJ ~WRITE

"B" BUS

INTO

CORE

DECODE

DAC

GRP l~M.I

GRP 2--+ IR
SMW -

MEMORY

START
WRITE

5-3.

ADDRESS

w----2. DATA

MEMORY REFERt;NCt;

(e)

of HI

OPCODE

I"E'J

IN~rl'RUC'l' IUN

6
ADDRESS

FIELD

0
7

0 08
7 78

ADDRESS

FIELD

15 MODE

9 MODE

~----------~~~--------------------------------~.$"

0
(C) OF MI

1 2
OPCODE

"E"

0
7

0 0 0 o 0 8 }
8K
1 7 7 778

E FIELD
BITS ~
a a
DIRECT ADR
1
INDEX ADR
0
0
INDIRECT ADR
1
1
INDEXED INDIRECT ADR
1

BITS 4

Determines addressing mode
Address field is the effective address.
Index REG(XR) + PC 1-5, m16-17 is the effective address.
PC 1-5, M16-17 is the address of the effective address.
PC 1-5, M16-17 is the address of an address. CPU reads (r
of the address into MI (Address of the address) then adds
the contents of the index register to this value the
result is the effective address

Direct Addressing
15 mode 4K
9 mode 8K
Index Addressing
15 mode 128K
9 mode can't use index addressing
Indirect Addressing
15 Mode 32K
9 Mode 32K

5-4

MEMORY REFERENCE INSTRUCTIONS
"15 MODE"
LAC

500

- Direct Ad~ressing - 200500

LAC

sOO,X

- Index Addressing

- 210500

LAC * 500

- Indirect Addressing

LAC * SOO,X

- Indirect Index Addressing

- 220500
- 230500

FETCH MAJOR STATE
TS01-MI

I :200:06 t--+ Decode Group 1
c

IR~

~ Decode Group 3,5

START MEMORY READ
PC

1-5

"DIRECT ADDRESSING"

M16-17

MO,OA

TS02

MREQ

TS03

Wait for Rd RST
loaded into HI
1

(SMR)
(effective ADR)

(Stop CLK hangs CPU INTS03& ~3

EXECUTE

EXECUTE MAJOR STATE
TS01

TS02

PC JAM TO MO

(SET FETCH)
START MEMORY RD
(GET THE NEXT INSTRUCTION)

MREQ
MI .... AC

TS03

Wait for RD RST (stop CLK hangs CPU in TS03&~3)
instruction loaded into HI register
1

FETCH

Always enter the FETCH majorstate with an instruction in the
MI Register

5-5

FETCH MAJOR STATE

TS01-MI

[____2_1_0_5_00________

DECODE GRP1

[~]

DECODE

START MEMORY READ

"INDEX ADDRESSING"

GRP3,5

(SMR)

PC 1-5, MI 6-17 PLUS XRO-17

= EFFECTIVE ADR

TS02

MREQ

TS03

WAIT for RD RST (STOP CLK - HANGS CPU IN TS03
OF EFFECTIVE ADDRESS LOADED INTO MI
1

* ~3)

(C)

) EXECUTE

EXECUTE MAJOR STATE
TS01

(SET FETCH)
MO
PC JAM
START MEMORY RD
(GET THE NEXT INSTRUCTION)

TS02

MREQ
MI~AC

TS03

WAIT FOR RD RST (STOP CLK HANGS CPU TS03
INSTRUCTION LOADED INTO MI REGISTER
1

* ~3)

) FETCH

ALWAYS ENTER THE FETCH MAJOR STATE WITH AN INSTRUCTION IN
THE MI REGISTER.

5-6

FETCH MAJOR STATE
HI

~__22_0_S_'O_O________~ DECODE GRPl

"INDIRECT ADDRESS"

TSOl
-------.)
START MEMORY READ

DECODE GRP 3,5
(SMR)

PC 1-5, M16-17-(THE ADDRESS OF THE EFFECTIVE ADORESS)~MO,OA

TS02

MREQ

TS03

WAIT FOR RD RST (STOP CLK-HANGS UP CPU IN TS03*~3)
(C)' EFFECTIVE ADDRESS NOW IN HI REGISTER
I~DEFER

TS01

START MEMORY READ (SMR)
PC I-i, M13-17~MO,OA

TS02

MREQ

TS03

Wait for RD RST

DEFER MAJOR STATE

(STOP CLK- HANGS CPU INTS03*~3)
DATA TO BE TRANSFERRED TO ACCUMULATOR NOW IN
REGISTER
l~EXECUTE

EXECUTE MAJOR STATE
START MEMORY READ
(SMR)
TSOI

PC,J~MO

TS02

MREQ

"SET FETCH"

MI~AC

TS03

WHAT FOR RD RST (STOP CLK HANGS CPU TS03*~3) INSTRUCTION
LOADED INTO HI REGISTER
l~FETCH

ALWAYS ENTER THE FETCH MAJOR STATE WITH AN INSTRUCTION
IN THE HI REGISTER

5-7

FETCH MAJOR STATE
INDIRECT, INDEXED ADDRESSING"

~ - - - - - -....
) DECODES

230500

DECODE

GRP 1

GRPS

3,5

TSOl
START MEMORY READ (SMR)
PC 1-5, M16-17
MO,OA (THE ADDRESS OF A LOCATION IN CORE)

TS02

MREQ

TS03

WAIT FOR RD RST (STOP CLK - HANGS UP CPU IN TS03*~3)
THE CORE LOCATION LOADED INTO THE MI REGISTER

l---.DEFER

DEFER MAJOR STATE
TSOI

PCl-2 MI 3-17
+XRO

RESULT - EFFECTIVE ADDRESS --~) MO

START MEMORY READ

(SMR)

TS02

MREQ

TS03

WAIT FOR RD RST (STOP CLK - HANGS CPU TS03 ~3)
DATA TO BE TRANSFERED
TO THE ACCUMULATOR IS NOW LOADED INTO THE MI REGISTER
l~EXECUTE

EXECUTE MAJOR STATE
TSOI

START MEMORY READ
PC JAM--tMO

TS02

MREQ

(SMR)

"SET FETCH"

MI~AC

TS03

WAIT FOR RD RST (STOP CLK HANGS CPU TS03 *
INSTRUCTION LOADED INTO MI REG.

~3)

l~FETCH

ALWAYS ENTER THE FETCH MAJOR STATE WITH AN INSTRUCTION IN THE MI REGISTER

5-8

CENTRAL PROCESSOR INTERFACING WITH MEMORY
OBJECTIVES:

Define how the central processor initiates a memory cycle.

List the ways the central processor waits for memory responses
a) read type instrqctions
b) wri te type instruction.s

Explain how the control signal MQ-MOL is made active.

oemonstrate ability to use instruction flow chart

Explain how an instruction is decoded & processed through
the central processor.

6-1

MEMORY REFERENCE READ FLOW

START READ
KP19
GRP 1 ENAB pc:
PC-A OlthruOS
KP47

GRPl*TSOl*
FETCH:

LOAD lR
KP32

FETCH
TSOI

CP MEM REQ
HOLD
KP24

(GRPl*TSOl*FETCH

CLK H : LAST HALF OF 03
ADDRESS LOADED

-I/O ACTIVE *
MPX (l) :
INACTIVE

CP ACTIVE
KP26

CP ACTIVE*HOLD
MO:MO~MDL

ADDRESS ON MDL LINES

KP26

START READ *
CP ACTIVE:

COMMAND TO DO
READ/RESTORE MEMORY CYCLE

KP26

TS02

START THE MEMORY CYCLE
M REQ

6-2

MHOl
MINT: LD MA
CLR MB

ADDRESS DECODING TAKES' PLACE

NO MEMORY
ACTION FOR THIS
BANK

MEMORY
TIMING

START MEMORY
CURRENT
GOES BACK TO THE CPU
MEMORY BUSY GOES ACTIVE

DROPS ADDRESS FROM MDL

LOSING MREQ RESETS ADDRESS ACK

CP ADR ACK:
O-CPMEM REQ HOLD
MM02
-HEM REQ:
o-ADR ACK

MEM DELAY

TS02 ~3

SONS STROBE
ADJ 2-40NS

MEM DELAY
CURRENT

6-3

MM02
DATA FR::>M CORE
STROBED UNTO MB

MM16

MM19

DATA ON
BUS

KP20

CPACT*TS03*START
READ*RD RST WAIT:
STOP CLOCK HANGS UP
CPU UNTIL RD RST OCCURS

TS03~3

CP ACTIVE * ~3 * TS03
CP RD RST

* RD RST:

DATA READ FROM CORE LOADED
INTO MI

O-+CP ACT

PROC DONE WITH MEMORY CYCLE

MRLS
. - DATA ACK RESETS BUS EN
TAKES DATA OFF THE MDL LINES.

MRLS*MRLS ACK
EN : MRLS ACK

O--'RD RST
1
BUS DONE

MRLS
O~ CP

MRLS

----. 0 - MRLS ACK MM02

WRITE CURRENT RESTORES
CONTENTS OF MB BACK INTO CORE.

6-4

END

FETCH MAJOR STATE
KP-21 lIS CLK (L)
KP21 HS eLK (H)

fH L1H
6SNS
It

HS CLK(L) GOES LOW
IONS BEFORE HS CLK(H)
GOES HIGH

~i~~ GROUP I DECODE (MI)
(

(PC-A)

f42

SB I

I4--TS01----....

ENABLE PC 1-5

177771117711777777707l777010lffTso1 OF NEXT FETCH (~1)

TS02

.1+---TS03

fll/111A
VOlOZ0077770mam7Z77Z7707Z77ZWmZlZlZZZzzffTS01 OF NEXT FETCH
t7Z/1111777777177711IZd

KP30 GROUP 3,5 DECODE
KP47 MI - B 6 17
KP24 LD MO, OA (CONTAINS ADD.)

0'\
I
U'1

jiJO

KP31 ID IR

KP32 START READ
KP32 CP MEM REQ HOLD
KP26 HOID MO
KP26 CP ACTIVE

LT II L 1H LIB L1H LJH LIH LIH LIH LIH LIH L I HI
,
,
,
,

iJ1111
WUIUI 171 «(Ill Il1lZll 11//////77 ///ZIII II I II 1/1Zllallllb

RlllOtl Uom
IIlIIllIIlIZIIIIIl/1/111,,"an

KP26 MO-MDL (ADD-MDL)
KP26 MRD

VII IIIIIII I I 17 II II I 1lllZI/llllllll10J
tlUZIUII

Wlwm

KP26 M REQ
MM01 MINT (LD MA, CLR MB)
MM01 ,02 START MEMORY, RD CON, MA HOLD
MM02 ADDRESS ACKNOWLEDGE
MM02 MBSY
MM06,07 "X" & "y n CURRENTS
MM02 BUS ENABLE
MM02 STROBE
(START ADJ 2-40 NS)
MM02 READ RST

fJIIlJ
V1I11IJ

v.m

~ANOTHER MREQ
WOllllll'"11Z1IIll{11IZlI111lIlZlllIlllllllll.
COULD BE HONORED

VID

(25'EI ' lS(jIStA

FUZWZIZIWlm

vmmowzwzzma,
. vm PW SONS

wUlW'UWll7llU4
V1lll1A
V1J1lJ

KP32 CP RD RST
KP32 CP MRLS & LD MI & END OF CP CYCLE

Un7Z~ELAYS

KP26 CP MRLS : MRLS AND DATA ACK
MM02 MRLS ACK
MM02 WREN: INHIBIT CURRENTS, START RESTORE CYCLE

f11I11A

MM02
MM02

tmnomomun

WR
INHIBIT

fiIIIitA

~/IIZIZZZ7ZZD"

1~200 NS---+I

ON BUS
30-S0NS

CENTRAL PROCESSOR BLOCK DIAGRAM
OBJECTIVES:

Explain what an instruction does .

Define by central processor block diagram how the
instruction or instructions will be processed.

OPCODE

JMS INSTRUCTION

JMP TO SUBROUTINE

INSTRUCTION

100 - 100500
101

NEUMONICS
JMS 500

FETCH MAJOR STATE
THE JMS INSTRUCTION IS DECODED.

THE EFFECTIVE ADDRESS IS:

TS01

PC 1-5 Ml-6-17-+MO,OA (000500)
SMW-MEMORY COMMAND

TS02
DATA-

MREQ
(0 1 2 3 ------- 17 ---+ MO ----. MB THEN WRITE
L B U\ 0
0 10~
IAU~

NNE
K K R

TS03
1~ EXECUTE

TS01

EXECUTE MAJOR STATE
OA + l~MO, PC
000500 + 1 = 000501-+ MO,OA
501 NOW IS THE EFFECTIVE ADDRESS
SMR

(READ COMMAND -

READ NEXT INS!'RUC'1'ION" MI REGISTER

1--. FETCH

MEMORY REFERENCE INSTRUCTIONS
OPCODE 44

ISZ INSTRUCTION
INCREMENT AND SKIP IF ZERO
FETCH MAJOR STATE

PC 1-5 MI 6-17
MO, OA~EFFECTIVE ADDRESS)
SMR ~ (READ COMMAND)
MREQ WILL BE SENT TO MEMORY AND STARTS THE MEMORY CYCLE
CONTENTS OF THE EFFECTIVE ADDRESS LOCATION ARE LOADED INTO
THE MI REGISTER IN THE CPU
l ..... INC
INCREMENT MAJOR STATE
OA-+ MO (EFFECTIVE ADDRESS)
SMW (WRITE COMMAND)
MREQ WILL BE SENT TO MEMROY AND START THE MEMORY CYCLE.
MI + CARRY INSERT (+1)...., MO
SEND THE UPDATED DATA AND LOAD IT BACK INTO THE
EFFECTIVE LOCATION IN MEMORY

SKn>: CARR;J=O

SKIP:CARRY=l
l~EXECUTE

(SET FETCH)
(
(PC+l

GO TO NEXT INSTRUCTION
PC, MO) + (PO JAM~MO)=(EFFECTIVE ADDRESS)
SMR (READ COMMAND)
MREQ WILL BE SENT TO MEMORY AND
START THE MEMORY CYCLE.

CONTENTS OF THE EFFECTIVE ADDRESS LOCATION ARE
LOADED INTO THE MI REGISTER IN THE CPU
l~FETCH

INSTRUCTION IN MI REGISTER

7-12

AND INSTRUCTION

Of CODE

THIS INSTRUCTION BEADS DATA IwrO THI HI REGISTER DURING
GO TO THE EXECUTE MAJOR STATE
THE FETCH MAJOR STATE.
AND READ IN THE NEXT INSTRUCTION.

·!XECUTE MAJOR STATE

AND. _ _ _.....

A
C

"SUM BUS"

MI 0
HI 1

= 1 * AC 0 = 1
= 0 * AC 1 = 1

LD AC WITH A tI l "
LD AC WITH A "0"

AND INSTROCTION CAN BE USED AS A MASK

7-13

OPCODE - 54

SAD INSTRUCTION

THIS INSTRUCTION READS DATA INTO THE MI REG DURING THE FETCH MAJOR STATE.
IF THIS DATA IS DIFFERENT THEN THE CONTENTS OF THE ACCUMULATOR SKIP
THE NEXT INSTRUCTION.
(PC+l-'PC-MO IN TS01 OF THE EXECUTE MAJOR STATE)
IF THIS DATA IS THE SAME AS THE CONTENTS OF THE ACCUMULATOR, DO rHE
NEXT INSTRUCTION.
(PC JAM-'MO IN TS01 OF THE EXECUTE MAJOR STATE)

;XECUTE MAJOR STATE

"c"

ZERO=H
DATA=L

U
S

(MI*AC SAME)
(MI*AC DIFFERENT)

AC
CBUS EQ OL
(-CBUS EQ 0 H)

KP 23

SAP____-t

TS01
EXECUTE

u---INC PC

(PC+1~ PC)

SKIP CONDITION
PC .....A

CARRY INSERT: LD PC AND MO

7-14

OPCODE,

JMP I!STlWCTION

THIS INSTRUCTION MODIFIES THE PC.
"nCB MAJOR STAT!:

'1'S01

PC r-S M16-17 "'MO,

LOAD

AND PC

QA,

KP 24

~~R~
CLOCKS

SMR

TS02

gi~ni_K;;.l_ _~ PC

(READ CYCLE)

MREQ

TS03 WAIT FOR RO RST
BUMP....PC

(LOADS INSTRUCTION INTO MI REGISTER)
(PC~A+1)~PC-

PAGE MODE: LOAD PC 6-17
BANK MODE: LOAD PC 5-17

l~FETCH

00-17

gpCOpES - 72, 73

lNDEX IN§TRUQlPNS f

ALLOWS PROGRAMMER TO TRANSFER INFORMATION BETWEEN
THE AC, LIMIT REGISTER, AND INDEX REGISTER, ADD A NUMBER
CONTAINED IN THE INSTRUCTION ITSELF (±256) TO THE AC,
LIMIT REGISTER, OR INDEX REGISTER AND TEST TO DETERMINE
IF THE INDEX REGISTER IS GREATER THAN OR EQUAL TO THE LIMIT
REGISTER.
MOVE TYPE INSTRUCTIONS
DECODES ON KP 29

.Ol?

CODE

721000

FROM
SOURCE

AC ... XR

TO
DEST.

AC :: 00
XR = 01

7 8
0 0 0 1
AC .... XR
5

AC = 00
XR = 01
LR = 10

"BUS CONTROL"

PAL INSTRUCTION
OP CODE 722000 : AC ...... LR
!U!§... 5678
o 0 l' 0
AC~ LIMIT REGISTER

~_______B_U_S___C_O_NT
__
R_O_L________________~~

L.:J .

7-16

LR~

rLX INeDUCTION

or CODE 731000: LR-' XR

Ul:§

5678
1001
LR....XR

~,~

rXA

or C9J?~

__________BU
__S___
C_ONTRO
____L__

_______LD
__x
__

INSTRUCTION

724000 : XR . . AC

JlI.§

5678
0100
XR~AC

_____________B_U_S__C_O_N_T_R_O_L______________

J. .

LO A C - -

PXL

INSTRUCTION
OP coo; 726000 : XR -+LR
.IlD
5678
0110
XR .....LR

_____________B_U_S__C_ONT
___R_O_L____________
LD

7-17

LR---~

INSTRUCTION

723n

ADD N TO ACCUMULATOR

(AAC+ n)

72 3+N (N c 9 BITS)
SIGN + 8 BITS.
NBGATIVE NUMBERS IN TWO', S COMPLEMENT FORM

N -

723 9thru17

---...,.---........-XG LD AC
......-_..............- EX ENAB AC L KP 19

KP47
MI -+
......B___at

'--

C -+A

KP-19

AXR + n

INSTRUCTION: ADD TO INDEX REGISTER
737 + N (n = 9 BITS)
MI

t - -.....-LD

9 thru 17

KP47
MI ...... B

- -.......- ......-_...

-_...

......-.....

....~- (AXR)

7-18

KP 47
XR 00-17~A

PIA INSTRUCTION
. 730000S

BITS

LR-'AC

5678
1000
~AC

__-________
B_U_S__C_O_NT
__
R_O_L____

~ ~
__

LDAC~

_______

INCREMENT TYPE INS'l'RUCTIONS
~

AXS(N)
AXS (lU

= SDITS + SIGN

INSTRUCTION IMPLIES ADD CR SUBTItACT THE tiN"

'10 THE IItDEX REGISTER AND SKIP IF E~AL TO OR
GREATER THAN THE LIMIT REGISTER

REG

INDEX

REG

TS02

ADDER

LIMIT

REG

INDEX

REG

1 -_ _
• PC

YES

PC+l-+ MO, PC

7-19

JAM .MO

CQMPABE or INpEX REGISTER AMP LIMIT ~GISTER

IISTJSUCIIO!Jr
.6l!!l

GIVEN:

XR a 000050, LR • 000050

XR-B

KP48

4-- CARRY INSERT

RESULT

= 000 000 + CARRY

KP49

TEST LR*TS03,--a.....

YES

Fl
1

Ll
23

ENAB

7-20

SK L

OfCODE - 74

OPERAtE INSTRY£TIQNS:

OPBlATE INSTRUCTIONS ARE USED TO SINSE AND/OR ALTER'TKE CONTENTS
OP 'ftII AC' AND LINX. THESE INSTllucrICIts CAR BE MICRO-PItOGRAMMED.

BIT 7=0
CIA
5

ADDITIONAL O=Or of
CLL ~ATE
l=And of

SNL

SZA

SMA

SZL

Stfl

SPA

1P .

...I.

- TS02

HL,

R'l'Q. I RTL
BIT '7=1

OAS

CML

CMA

RAR I RAL

MAIN ORDER OF· EVENTS
%

TS01 - SKIP CONDITIoNS
CLEAR AC
TS02 - CLEAR LINK
OPERA!'ION ON 'AC. AND LINK
'1'503 - HLT

ORDER OF

'1'S01

COWMN 1

EVENT~

LEVEL 1

SNL,SZA,SMA
SZL,SNA,SPA

LEVEL 2
LEVEL 3

COLUMN 2

NOTE:

COWMN 3

COLUMN 4

f CML

CIA, CLL

SKIP

• +-- TS03---'

t IJl.C
OAS CMA
RAR ~ ~L
RTR R'J'L OR SWHA

HLT

CAN'T COMBINE INSTRUCTIONS 00 DlFi'ERENT LEVELS
IF THEY ARE IN THE SAME COLUMN
CAN'T COMBINE CML AND lAC, (KP22 GATING OF LINKFF)
COMBINED ROTATES BECOMES A SWHA OR lAC

OPERA~E

SW HA

MI13, MI14 ON A (1)H * MI07 (l)H

lAC

MIl3, MI14 ON (l)H * MI07 (O)H

INSTRUCTIONS - FLOW CHART KP76
SReMS A MEMORY CYCLE.

THIS IS ONLY TO RETRIEVE

THE NEX'f .INSTRUCTION

7-21

OPERATE

INSTRUCTIONS

o ~0 0

OPERATE

4Y <Q <Q~ 0
v ~

'Q)~

1'. J! J'. ~ ~
V ~

.r$ <:).0
OPERATE INSTRUCTIONS MODIFY OR
CHECK THE STATUS OF THE LINK
OR THE AC A MEMORY READ
CYCLE IS INITIATED
SNLVSZAVSMAA~MI~8 V
SZLASNA A SPA 1\ MI~8:
SET OPR SKIP FIF
CLOCK:
OPRSKIP: PC+ 1 ~ MO PC
~CPP SKIP:JAM PC-'MO
M1~5:CLR AC
START MEMORY READ CYCLE

FATS 2
OPERATE ON AC OR LINK
SEE OPR TABLE
OPRATS~2 i\ CLOCK:

LOAD AC

CMA

740001

CML

740002

OAS

740004

RAL

740010

RAR

740020

lAC

740030

RTL

742010

• •
•• •
•
•

744000

STL

744002

RCL

744010

RCR

744020

CIA

750000

<:>

<:> ~

<:>

~c,

J!?
'J'. ~~ c? ~?- ~
~ ~

•

RESULT

!l"VAC-+AC

• "'L-+L

••

•

"Yfo

ACV DSW~AC
ACC»L ~Ac17 Acl1+Acn-1
Acn-lllAcn+1 Ac17 ..L

L~Aco

•

•
•

AC+1--+AC
Ac1-.L Ac~-Ac16 L AC16 Acn~A~2
~AC1

•

Ac17 Aco Acl6+L Ac~Acn~

~c~~8toAc9-17

AC9-17toAc¢-8

•
• • CLL L,! RAL
• CLL ! 'RAR
O~

•

FATS~3

UPDATE PC

GLK

750010

SET FETCHI\TS~3: PC-+A; CRY IN

TCA

740031

CLOCK: LOAD PC

<:>

O~L

•
LAS 750004

CLC

% -o/)~~
~ 4;-'
T,
:/ ~O t# ./';' ~~

•

742020

CLL

••

•
SWHA 742030
RTR

~v 'c.

~ ~0~0 ~~ ~c,

750001

•

•
•

•

•
•

•

;"'\I ~L

O--t'AC
ALL 1.~ s--. AC
O~AC

DSW-+ AC

O~AC

L--+AC17

AC + l--+AC

MI12 CLR RUN AND HALT
~MI 12
GO TO FETCH

7-22

CONSOLE OPERATION
OBJECTIVES:

Manu.lly load a program from t:he console switches.

Manually examine proqram

Run the program

Explain the functions of tae CQD~l $Witche,

Analyze console display

Load -and run a ha:rdware p.per tape read in.

8-1

.cONSOLE PDP-IS

CONSOLE LOGIC LOCATIONS

CONSOLE SWITCH BOARD

CONSOLE INDICATOR PANEL

KP-18 REGISTER -

KP-34 CONSOLE INTERFACE

KP-38,39,40,41,42,43 -

KP-44 CONSOLE CONTROL #1

KP-4S CONSOLE CONTROL #2

KP-46 MIS CONSOLE LOGIC

KP-72 SIGNAL CHART IND BUS

10.

KP-73 KEY FLOW

11.

FLOW CHART HANDOUT

I BUS
(CONSOLE TO PROCESSOR)
I BUS BITS 0-23

8-2

CONTROL CONSOLE TIMING

265

us
eLK INH

I II I I I I I 1

I I

HALF(l)H

ZERO(l)~~__________________

ONE(l)H

TWO (1) ; -.....
1 ___

COUNT

DISPLAY

L:12J2JlJ2J¢J
MISC

A
/C
T

REG

"'v-

DISPLAY REG.

E
........

A S
w D W
I D I
T R T
C E C
H S H
S
S

D
A

Note Active SW on
IBUS: CNT 3
1.

Deposit swjtch or what
ever switch depressed

Set 1 of l2ff to be
controllE'd by rotary

I
A T

C
H

sw.

AC selected sets 1st
ff and at a count of
one the register
lights display whats
in the AC.

SWITCHES ON
"I" BUS
0

DI
CY

SPL
CL

AY
E

SET

NOTE: ADDR SW to

Start CPU timing and do
the given operation.
(deposit)

Data switch are stored
in DS REG and

OPER

YES
NOTE:

8-3

raus: CNT4

TURN OFF DISPLAY LIGHTS
(PROTECTION)

(

ADSW
o

DSW
o 0

+5V
1

o
1

(X)

-6V

I BUS SWITCHES

I BUS

POS1

STROBE lERO

F/F

KP50 PI

REG NORM - + _......

8AC

KP46 I BUS f)s N1

MIse

¢s

REG
REG MAINT ____-.
A SUS 05-1'
(X)

I
U1

STROBE TWO_"fJ

EM
M I ¢5

I B US LIGHTS

,_W'..'",7

IAI$;"

;,,"~~:n.c,- ......4Cf4ts. .i(J!,,!U~.;Cla;&fP

(

SWITCr

IU.; ,.liltli,.J::;;'

"-"'hh't3·~f . .

i4LlJl.4i$ s W44A.,Q

qEG

0 I 2 3 4 5 6 ·7 8 9 10 I 1 12 13 14 15 16 17
;

AC4 Res ReG RC7 ReB RCq /lelo fie II RCIZ ACI3 RCI4 AC/5 RCIt;, RCI7
pC/7
PC4 PeS Pc~ PC7 pea PC9 pc 10 PCII PC 12 PC 13 Pc 14 A=/S pC
oA4 oAS OA6 0117 OilS 011 q OAIO OA II OAI2 01113 OA/i- DAIS' OA/6J 0A17
MQ MQ~ MQt MQ2 f103· l1a4 Mas ~atD !:107 I1QS flO Cf -Ma'o /1011 I1QJZ IiOl3 lI1QJi- !1QIS ~O16 .MQ 17
~PL
API:.
RPr
RPL
API.
API
RPI.
SC
5C
sc sc sc
sc:..
Sc
Rea ReQ APE.
REQ
REa
REQ
REQ
REGl
R£Q

INdAC RC(/J t:/C 1- /fC2 flC3
PC Pc rt! PC 1 PC2 PCo
011 ol1e 0111 0112 Of13

¢fZ>

ali.

¢z

ttJ3

{Z1~

I<A~5'

I<A~S

KA¢~

1Q1~5"

.KA~L

XR (!J

XR2

XQ,5

lR0

XR3
LR3

XI< ..,.

XR1
LR 1

lR 4
E

LRS
F

PL/SC

(0) #1

(o)H

Co) H

(0) H

KE.¢-t

KE~

KEe4-

J(£¢Jf

(0)

DS (l)

DS .1.

Ds2

KE¢4
DS3

DS4

0$5"

:r08

ToP)

:to i

Io2

:to 3

ro4

!os

PIE. '1:/08 1106

K8D

TeL~-

~INT

a11

(}}2..

FLAG-

FIRG-

Xl08

(JJ~

K4¢J

t~i

LR ~

XR 7
LR 7

)(R 8

~PS3

J<Ps'1

J<P5'3

I<P53

J<PGO

HP5"O

(65
KP53

KPS7

K"57

MO¢

flO .1.

Mo2

1103

,...,04- MOS

/'to ~

MO 7

RBus A~ A 1
B8as 8¢ B 1

A 2

A 3

A ~

A"~

c 7

D¢ Vi

83 84c 3 e "t
D3 D4

85 S ~

C i

82
c 2

A 1
B 7

SUM

(j\

C ¢
.... ,.6~

5tt1 ¢

Sftli

MULT
p",
SHIFT .5U,Fr

--+D

.-..D

I<Plq

KPIQ

MDL
MMfI

11MB

MST

-'tD
J<P/Cf

cfi,

U~ 8

"'0 g
AS

xR q
LR q

KE<13

KE(13

Ie;,
IS"
KSl3 Kc~3

KEIlI3

t(P!~

KP$'a.

NJct

tft)IO ipK;1I

KPS'Z. KffZ. KP5'L KPS'2 I<P~.#2 J<f'5~
f1)OI2 /fJo13 fYJ() 14 (Y)()JS I"lO/~ /fJO 17

A q
8 q
c q

A 10 A II

~/2.

1> 10 DJ(
~/O ~() I J

KP52

a JD e "
C 10

I>~

~()~

~o !)

~o to

rfp 7

IRS

~ct

SfYl3

51"14
RTL

S('f) 5

sm~

Str17

RTR
...... D

Il1O
SHII=T
~.D

"'D

-+A

KPIQ

I(PI Cf

KPlq

J<Plq

KPIQ

}(Plq

Lei

KPIQ

t<E.~3

.><RIO XR II
LRIO LR I'

z/.o3

RIU~
~D

)(£(13

sm8 Sl')q SI"1/0
XR
SWH~ Cbvs -CbcJs

C "

Sf')/1

F?E~D

A 13 AJ4 1J15
BJ2 SIs e J4- 8J{

ell
VIZ

CIs
V/~

CI4

c u;

R 17
B /6 8/7
Cl6 C 11

VJ+

1)15

D'~

D/7

r'D{i~

KDIJ5

rffli- r.;r15 L)/~ ~'7
SI'1/3 S/YI/+ Sf') 15 Sir) It;; 5M 17
DATA DRTR
OA
xI/, Fll>l> RJdR
IN
OUT
~A
~A ~A

~o12 ~Jf 13
~/2
SL~

'-'A

KP"

(TTY)

A/~

KPIQ

lJ(p,q

I<PICJ

Ld.
Lei
START START CP
Ld
BAC XR 1'/0 Bus XOR CPl'ttM
Ld
ReQ
-.c 46 A<:. ;'\0 Pc OA
><1< ~C ~e ~C ~C (GlITe)
RERP WR,Te MRLS
lR
~8
(1-5'
:~;~7
KP23 1<1'19 /(Plq I(Plq I<P24 KP24 I<P24 kP.24 /(P24- KP.24
KPJq I<PIf/ 1{P32. )(P32. kP32 KP32.
.....
J?1L ~ IYIL 1 /'IlL 2 ML 3 /'IJL 4- (I1L 5
mL
q
IIIL 10 lmL
l,ML
7
!fILS
II
f'1l
12 (tiL 13 f1II. It iYJL J5' /1Il /~ rtJt.. 17
(tiL "
I"JIlI5 I~ t Nl2 ~3 (11/1 4 mil 5" fYJl1 ~ N/7 ~B PM q f'IA /0 ~ /1 ~II 12 1t'fA J 3 /1'111/4- filII / S' [J'711 I~ tflA J 7
(fiB 2
H8 flJ 1MB f
/l1B 3 ft184 1'1/J :) /"'18 ~ !I~ 7 JIB 8 1'8 'I trJ810 M8 II 11812 M813 liB 14 1'18 15' t-f81fD f.1817
MDL MDL.
'WR
11 DR Bus RD
PRR
PRI?
R~AD WRIT
MRLS ME.N1
¢4
Me E>fIST
!leI<.
(11'5
EN
EN
RST
CON
f1CK SUS,!
Co"
tnfP'I(Jl f'7mJ61
f"IM0Z m,.,,'2
rnm~2. mmf12
mm#2. "'mIt.
~
1?
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17
1
2
4
6
3
10 1 1
7
14
13
8
15
16

SKIP -MI

SIl'l 2
RRL

OFL-O

XRI2 xRI3 XRI4- xR.15 XR./6 XR/7
LR 12. LRJ3 LRI4 LR 15 LR/6 LR/7
LOW
-D/V - ERE. -EIiE -EAE -ERE -ER£ -P/
-DIV
-Su -/'1UL SUII=T
Q OFLO - Fvl( - EAE. TAIJe.
NORMS l-RS
LLS RCLS SIGN
A.
NOSHF
KE __S
KEQ11KaliS" KE~3 It(lEU3 1<E.~4 SHO'tAIH
k"£ fI+ I(SC1+ t(1l_",
K~"4
KE. ".,. ~6~
D5/0 D~ II ])512 DsJ3 D5/4 [)S J 5' DSJ6 1)5/7
DS ~ OS7 PSB f)Sq
IoB 'b q IOIO 10 II tD 12 1013 l o li- 1015 Io/~ IO 11
Io~ !lb 7
CLI( 1:~8 lloB ~B !;b8 ~B I/oB 1/ 8 X/oB ~o8 :rIo 8
CLI<
0
FLAG EN
I(D
13
Ig!
IS"
¢q
II
121117
~B

XR6

STATLJ5

SI/FTBUS
I/O A

to) H
KE¢4

LR2

EAE
_DSR

C8US

00
1

L.r?

RND

Nor
PR£r5Nr
wheN
LIT"

CNT OF 5
DATA SWITCHES
OS REG

CNTS OF 0,1,
AND 2
DISPLAY CYCLES

NOTHING HAPPENS
GO THROUGH
CYCLE 3 & 4

CNT

of 4
(LAST HALF)

(TS03* SET FETCH
* DEPOSIT)*CF:
KEY ACTIVE

KP34

KEY ACTIVE * DEPOSIT:
KEY REQ WRT (KP34)
THIS SETS UP WRITE
COMMAND (SMW ON KP 32 )

KEY ACTIVE *
- RUN: START
RUN. CPU
LEAVES EXECUTE
MAJOR STATE
GOES TO FETCH
MAJOR STATE

KEY ACTIVE : INHIBIT
DECODES (KP48)

DEPOSTI*TSOI
*-NEXT:
ADR-SW-A ..
KEY ACT*TSOl:
FORCE FETCH

KP24

KEY ACT*TSOl*
NEXT PAGE

CLK H:

OA
8-7

KP31
CNT of 4
LAST HALF

FORCE FETCH:
. KEY ACTIVE*FF:
CLR~IR

(NO INSTRUCTION
IS LOADED)

~Ir

KP26

MEMORY CYCLE
STARTED:
TSOI *1"3: 1"
CP ACTIVE: l'
Me - . MDL- (ADR)

KP34
(DEPOSIT)*TS02:

t STOP TS RUN

SMW~MWR

TS02*~O:

MREQ

KP32
(CPACT*START WRT
*TS02*1"3 *-TRAP
*ADR ACK) : ~ CP
WRT ADR ACK •
. THIS IMPLIES LOAD
THE OS REG. INTO
THE MO REG. AND
TRANSFER IT TO MEM

KP34
TS03 * fiJI:
CLR KEY ACTIVE
TS03*1"1: CLEAR
KEYS * CLEAR
CONSOLE.
CLEAR CONSOLE:
~ DEPOSTI FF

TS03*~,: ~ RUN

- RUN:" STOP TS
RUN

8-8

~ TS03*~1: LD MI
(C) OF DATA SWITCHES

WILL BE DES PLAYED
IN TEH MB LIGHTS

CNTR

CONSOLE CLK

rtl

I 5 0 I1 I2 I3 I4 I5 0 I 1I 2I3 I4 I 5 )
I , I I II I I I I I I I t J t , I I , I , I , I I I , , , t

SWITCHFF

SWITCH ACTIVE

ACTIVEFF

BLOC1).F

DEPOSITFF

L-______________________
____ ______________________
SWITCH RETURNS TO HOME POSITION (lOOms?)
~

~'
--1

I
I
TS03*~1:CLR CONSOLE

(X)

I
\0

SWITCH INHIBIT

CF PULSE

~ PREVENTS SETTING CONTRO~F

~flL

DELAY .126 SEC

___________________________________
EXPAND-THIS IS WHERE THE ACTION IS.

~~A_I~L__________~~-------------------~f1L--------------------fl
' - - DSWITCHES

--.... DS REGISTER

KP46 CLK IN H
KP45 HALF (1) H
KP45 ZERO (1) H
KP45 ONE

(1) H

•

KP45 TWO (l)H
CONSOLE eLK. COUNT

(~(OOO)

KP45 STROBE ZERO

11(001)

(010)

(all,)

(100)

(l01)

DISPLAY MISC.

~(OOO)

____

______~IIIIIIIIIII~~I~F--RE--G-G~R-P~(~l~)--------------------------____________~11111
•
KP45 REG NORM STROBE _ _ _ _ _ _ IF REG GRP=W
KP45 REG MAINT STROBE

CD
I

......

KP46 STROBE ONE

______11111111111 DISPLAY MB

KP45 STROBE TWO
KP45 BANK 1 AVAIL
KP45 STOP AVAIL

_)h_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~illlllllllll~~D~IS~P~LA~Y~M~B__________________________________

_______________________________________I11III ACTIVE SW ON BUS
_______________________________________IIIIII~_I_F__________________________________

KP45 BANK 2 AVAIL

SW ON BUS

KP45 MISC AVAIL
DATA SW. ON BUS

KP45 AC AVAIL

CONTROL CONSOLE TIMING

ME-IS MEMORY BLOCK DIAGRAM

(11 MEMORY )

OBJECTIVE:
1.

List the functions of the M7l70 interface control

List the functions of the GI09-YA

List the functions of the G-231

Describe the dialogue between the PDP-IS and the ME 15
Me~ry

9-1

15 BITS 05 THRU 17

~ 13 THRU 1

M 7170
15 ADDR-,\
01,02,03,04)
V

1.0
I
N

GI09YA
~

SELECT
1 OF 2
M 7170

EACH 7170 CAN ADDR.
48K. 7170 SELECTS
A RANGE OF ADDRESSES
BETWEEN A STARTING
LOCATION (8K CHUNKS)
AND 48K LOCATIONS
UPWARD.

SELECTED
1 OF 6
8K
STACKS

f"W

SELECTS
ADDRESS

11 BUS
11 BITS USED IN SELECTION
OF A PARTICULAR GI09YA
BITS 17,16,15,14

t t t t

BITS

...

L...

CORE
"8K"

H 215

....

l.f\
•~ 11

G231

1, 2, 3, 4

DATI

DATlp

DATO

DATOB

Cl=O : READ
Cl=l : WRITE
CO IN CONJUNCTION WITH Cl:
WHAT TYPE OF READ + WRITE

TRUE BUS COMMAND
UNIBUS IS POSITIVE WITH LOGIC LEVELS OF:
OV (" 1" ), +3V (rr 0" )
WITH THE EXCEPTION OF BUS GRANT AND NPG,
3V (" 1" ), OV ( 0) .

UNIBUS IS LIMITED TO 20 "UNIT LOADS

= 1 RECEIVER AND 2 DRIVERS.

UNIT LOAD

7170
15MWR

15MRD

FUNCTION

llCO

lICl

H
L

L
H

READ
WRITE

o (L)
0

l(H)
0

l(H)
l(H)

l(H)
O(L)

READ/WRITE

1/0

% IH ~

DIALOGUE

P-2-32

(Ll

EAE INSTRUCTIONS

To be included .at a later date.

10-1

BAR RAED.ARE

be included at a later date.

11-1

ASSEMBLY LANGU~GE PROGRAMMING
To facilitate our programming efforts, we will make use of system programs
supplied with the. Disk Operating System (DOS). They will be the Editor
(EDIT). the assembler (MACRO) and the Peripheral Interchange Program (PIP).

The Editor

allows us to set up an area on the disk containing our
program (the "sour.ce" program). We use the Editor to
both create the text and to modify it because of typing
errors or changes in program design.

The Assembler

is'used to read the "source program" and translate it
into a format (the binary program) which can be load·
ed into memory and subsequently executed.

The PIP program

allows for manipulation and transfer of data fil~s from
any input to any output device.

In order to make use of these facilities. we must first load the Disk
Operating System's executive program (liThe Monitor") into memory so
that we can request the Editor and the Assembler through it.

12-1

DOSSAV OPERATING INSTRUCTIONS

DOSSAV is the save/restore system for DOS-IS.
DOSSAV saves and restores to/from DECdisk, Disk Cartridges, Disk Packs,
DECtape and magtape.

A DECdisk system can be saved on and restored

from DECtape, magtape, Disk Cartridge and Disk Pack.

A Disk Pack or

Disk Cartridge system can use DEC tape and magtape.
Once loaded, DOSSAV asks for all necessary information, such as input
and output device, unit numbers and, in the case of magtape, parity
and density • .
GENERAL INSTRUCTION:
The user must type a Carriage Return after all entries, including the
character typed to restart after errors.

For UClS system, start up

PIREX as indicated below.
To load PIREX, place the ABSll paper tape in the PDP-IS's paper tape
reader.

Place the ENABLE/HALT switch on the PDP-II in the HALT posi-

tion.

Press the STOP and RESET switches on the PDP-IS simultaneously.

Set the ADDRESS switches on the PDP-IS to
switch on the PDP-IS.

l77~~.

Press the READIN

When the readin operation is completed and the

PDP-IS has halted, set the PDP-II switch register to:
6~~~~
l~~~~~
12~~~~

for 4K local memory on the PDP-II
for 8K local memory on the PDP-II
for 12K local memory on the PDP-II

and depress the PDP-II LOAD ADDR switch, then set the ENABLE/HALT
switch on the PDP-II to ENABLE, and finally depress the PDP-II START
switch.
Remove ABSII from the paper tape reader, and reload it with the PIREX
paper tape.

Press CONTINUE on the PDP-IS.

program (which has two segments:

This will cause the ABSII

A PDP-II segment, and a PDP-IS seg-

ment) to read in PIREX (which is a PDP-II absolute binary tape) via
the PDP-IS segment and load it into PDP-II lower memory via the PDP-II
segment.

12-2

When the PIREX paper tape has been read in, the PDP-lS will halt, and
the PDP-II will be running PIREX. Remove the PIREX paper tape from the
reader. At this point the UNICHANNEL Peripheral Processor has been
loaded and is waiting for an I/O request from DOS-IS.
A.I

RESTORING SYSTEMS

The following examples illustrate how to put the systems distributed byDigital on DECtape or magtape onto a DEC~isk, Disk Pack or Disk Cartridge.
The user responses are underlined. ~e ~5 based systems st~rt up
PlREX as described in GENERAL INSTRUCTION, above, before starting up
D05SAV. DOSSAV resides on a paper t~pe, which must be (HRM) loaded
at 3772. (restart 3421').
1.

To restore a DECdisk system from D,ECtape (1 of 2 on Unit 1
and 2 of 2 on Unit 2)
DOSSAV Vnn
INPUT DEVICE? DT)
UNIT NO? 1)
OUTPUT DEVICE? DK)
DATE CREATED: 06~n 73
TAPE DONE. MOUNT ANOTHER

/NQte that if DK is typed no
/unit nUftlber is requested.
/At toi- point,
/type 2 O~ the key/board follow.d by Carriage
/RETtJRN.

To restore a DECdisk system from magtape (on Unit ~):
DOSSAV Vnn
INPUT DEVICE? MT)
UNIT NO? U
TRACR (7 OR 9)? 7)
DENSITY (2,5,8)? -e)
PARITY (E OR O)? OJ
OUTPUT DEVICE: DK~
DATE CREATED: O~UN-73
NOTE
All DOS-IS System Restore magtapes
distributed by Digital are 600 BPI,
odd parity. Par ~ track unita, DOSSAV
assumes. 8'(1 BPI.

To restore a Disk Pack system from DECtape (1 of 2 on Unit 1
and 2 of 2 on Unit 2):
DOSSAV Vnn
INPUT DEVICE? DT )
UNIT NO? 1.)
OUTPUT DEVICE? DP)
UNIT NO? ~ ~
DATE CREATED: 06-JUN-73
TAPE DONE, r.10UNT ANOTHER

At this point, type 2 on the
teleprinter followed by a
Carriage RETURN.

12-3

To restore a Disk Pack system from magtape (on Unit 1):
DOSSAV Vnn
INPUT DEVIC~? MT)
UNIT NO? I)
TRACK (7 0~9)? 7~
DENSITY (2,5,8)? -S~
PARITY (E OR O)? ~
OUTPUT DEVICE? DP~
UNIT NO?~)
DATE CREATED: 06-JUN-73

To restore a Disk Cartridge system from DECtapes on Units 1, 2, 3, and 47
DOSSAV Vnn
INPUT DEVICE? D~
UNIT NO? 1)
OUTPUT DEVICE? RK)
UNIT NO? .Q)
DATE CREATED:
~6-JUN-73
TAPE DONE.
MOUNT ANOTHER

2)
TAPE DONE.

f-.1OUNT ANOTHER

3)
4)

(The user mounted the next tape on
unit Number 4, then typed 4)
to continue)

DOSSAV Vnn
INPUT DEVICE?

(Operation complete)

TAPE DONE.

(The user mounted the next tape on
unit number 2, then typed 2~
to continue)
(The user mounted the next tape on
unit number 3, then typed 3)
to continue)

MOUNT ANOTHER

To restore a Disk Cartridge from magtape Unit 1:
DOSSAV Vnn
INPUT DEVIC5? ~
UNIT NO? 1
TRACK (7 OR 9)? 7)
DENSITY (2,5,8)? -8)
PARITY (E OR O)? 5)
OUTPUT DEV~CE? R~
UNIT #? ~)
DATE CREATED:
~6-JUN-73
DOSSAV Vnn
INPUT DEVICE?

(Operation complete)

It is possible to restore to the DECdisk a software system which was
created for a machine smaller (different number of DECdisk platters)
than the one being restored to.
ments of the SAT'sl.

DOSSAV does all the necessary adjust-

Thereforej the restore tapes issued by Digital

for a I-platter system c~n be restored to any system.

Note that this

should only be done with the master tape(s) which have block 1775 R
ISl\'1"!:;:

St(lrillJ{~

l\11ocCltion Tables - i.e., bit maps.

12-4

free. That block is needed during the restore for five or more DECdisk
platters. It is not possible to restore a software system which is
larger than the hardware.
(For example, one cannot restore a 3-platter
system onto a I-platter configuration.)
The system can then be bootstrapped from the appropriate disk.

See the

DOS Keyboard Command Guide (DEC-l5-0DKCA-A-D).
A.2

SAVING SYSTEMS

Once the user has tailored the system to his specific configuration, he
will want to save that system for future restorations. To do that,
simply reverse the procedure above. To illustrate, consider Example 1
above and the changes necessary to it to create a restore tape.
To save a DECdisk system to DECtape (on Units land 2):
DOSSAV Vnn
INPUT DEVICE? DK)
OUTPUT DEVICE? DTj
UNIT No? !l.
TAPE DONE. MOUNT ANOTHER

At this point, type 2 on the
keyboard followed by a Carriage
RETURN.

Note that DOSSAV allows for as many DECtapesand magtapes as are
necessary to hold the system.
A.3

ERROR CONDITIONS AND MESSAGES

Recoverable errors during command string decoding: If a question is
ariswered incorrectly, DOSSAV outputs an appropriate error message and
then repeats the question. These error messages are:
ILLEGAL DEVICE

An illegal device mnemonic was typed
(something other than OP, DK, RK,DT,
or MT) or an illegal combination of
devices was typed (i.e., input = DT and
output == MT) .

BAD TRACK

Something other than 7 or 9 was typed.

BAD DENSITY

Something other than 2 (200), 5 (556),
or 8 (800) was typed.

nAD PARITY

Something other than E (even) or 0 (odd) was
typed.

Recoverable errors during operations: If it is possible to recover
from an error, DOSSAV attempts to do it. The error message is output
to the console. After the problem has been corrected~ any character
on the keyboard follo\Oled by a Carriage RETURN resumes operation.
12-5

The DEC tape or magtape unit is off line

TAPE NOT READY

or not write enabled.
DISK NOT READY

DECdisk is write locked.

DISK PACK NOT READY

The Disk Pack or Disk Cartridge unit is not
ready.

Unrecoverable errors:
cannot recover.
restarts.

Primarily hardware errors, from which DOSSAV

After the error message has been output, DOSSAV

DOSSAV retries five times on parity error, before issuing

an unrecoverable error messaqe.
DECTAPE ERROR
MAGTAPE ERROR
DISK ERROR
DISK PACK ERROR
ATTEMPT TO RESTORE SYSTEM TO WRONG DISK
To protect users who have access
to more than one type of disk and
who may have several sets of
restore tapes, all restore tapes
are created with the mnemonic of
the disk type in the first SAT.
DOSSAV checks this code against
the output device code.
If they
differ, this message is output.
BLK 1775 OCCUPIED. NO 2ND SAT CREATED
A DECdisk system created for 4 or
fewer platters is restored to a machine
with 5 or more platters and block 1775
is already used. Therefore, no second
SAT is created. A master tape was not
used to make the restore.
XX ERR IGN
where xx

= DK or DP or RK.

This error is typed on the console,
and the PDP-IS halts.
This reports
that "Read/Write check" errors
occurred more than 12R time during
a save or restore process. The bad
block number is present in the PDP-15
AC. Users can continue the save or
restore process by pressing the
continue switch on the console of the
machine.

12-6

A.4

TAPE STRUCTURE

The restore tapes are structured as follows: The first SAT of the
system is the first block put on the tape. This SAT, which is never
restored to the disk, has two words modified: word 2 contains the
creation date (taken from .SCOM+47) and word 376 contains the device
mnemonic (.SIXBT, right justified). All the occupied blocks referenced
by this SAT are then put sequentially on the tape. The second SAT,
if there.is one, is then put on, and so on. This structure enables
use of magtape, which is a sequential only device.

A.S

DOSSAV Restrictions
1.

It is not possible to save or restore magtapes with even
parity.

DOSSAV fails when two DECtapes are on line with the same
unit number. It is necessary to restart under such
circumstances

12-7

MACRO-I5 SUMMARY
I.

INTRODUCTION

MACRO-I5 is a system program which facilitates wt'iting programs symbolically
because it converts symbolic representation to machine code.
INPUT:

ASCII text

OUTPUT:

Binary

.FULL

.ABS

Output to paper tape
for HARDWARE READIN

output to paper tape
for use with
Absolute Loader

12-8

MACRO-lS SUMMARY
II. FIELD DEPENDENT ASSEMBLER
A MACRO source program is composed of a sequence of source lines where each
line (terminated by a carriage return) may contain one or more assembly
language statements.' If several statements are written on a single line,
they are to be sepa,rated by semicolons.
STATEMENT
or'

STATEMENT; STATEMENT; STATEMENT
Statements may contain up to four fields that are separated by space(s) or
tab (but not both except between address and comment fields). The four fields
are: .
LABEL (OR TAG) field
OPERATION (OR OPERATOR) field
OPERAND (OR ADDRESS) field
COMMENTS field
and are identified by order of appearance and delimited by certain terminating
characters. The general format of a MACRO asseMbly language statement is:
LABEL or OPERATION FIELD or OPERAND FIELD or /COMMENTS
(ADDRESS)
where each field is delimited by a space{s) OR a tab and each statement is
terminated by a semicolon or carriage return. The comments field is preceded
by a tab or space{s) and forward slash (/). The label and comments field are
optional. The operation and operand fields are interdependent; either may be
omitted depending upon the contents of the other. However, blank lines are
illegal. (NOTE that if several statements are on a line, only the last may
have comnents).
FIELD CONTENTS
LABEL or
TAG FIELD

OPERATION FIELD

ADDRESS FIELD

COMMENT FIELD

Symbolic Label

Machine Mnemonic Instructions

Symbol

Direct Assignment

MACRO-l5 Assembler Directive

Number

Macro Name

Expression

Number
Symbol

Expression

12-9

............ .

MACRO-15 SUMMARY

LABEL FIELD

1- a label is a symbolic address created by the programmer to identify
the statement (usually for reference as addresses for jump instruct; ons, data
locations, and for debugging).
2- labels are optional but if present, a label always occurs first in a
statement (column 1)
3- a label takes as its numeric value, the address of the location it names
(the value of the current location counter is entered into the user defined symbol
table).
4- a label may be defined only once (therefore, a given label may be used on
only one statement).
5- note that even if a label is not used in a statement, the delimiter for
the label field still must be given.
OPERATION FIELD

1- the operation field follows the label field
2- the operation field may contain a(n):
--instruction mnemonic
--assembler directive
--number
--symbol
- -e xpress i on
--Macro Call
3- the operator may be preceded by none or one label and may be followed by
none,one or more operands and/or a comment.
4- when the operator is a macro call, the assembler inserts the appropriate
code to expand the macro. When the operator is an instruction mnemonic, it
specifies the instruction to be generated and the action to be performed on any
operand(s) that follow. When the operator is an assembler directive, it specifies
a certain function or action to be performed during assembly.
OPERAND FIELD

1- an operand is that part of a statement that is manipulated by the
operator.
2- an operand is usually a symbolic or numeric address of data to be accessed
when an instruction is executed or the arguments of an assembler directive or
Macro Call.
3- the interpretation of the operands depends upon the operation field.

12-10

Macro source statements may use the tab to align the statement fields according to
the following format:
label--

colurm 1

operation--colu.n 9
operand--

column 17

comment-- column 33
(tabs are set up to IIQve ntOdulo 8 spaces; col." 1,9,17.25,33.41,49,57 etc.)
EXAf4>LE

.LOC 10500
START

CLX
LAC

10600

IPICK UP NEG TAX RATE

DAC*

10601

IPUT IT IN TAX TABLE

LAC

MTAB

IPICK UP GROSS PAY

OAC

TAB,X

/STORE IT

HLT

DATAB

20000

INOT SO GOOD--OCTAl

.LOC 10600
62

TAXTAB
TAXTAB .BLOCl( 6
.ENO START

12-11

MACRO-15 SUMMARY
COMMENT FIELD
1 - a comment is a short explanatory note which the programmer adds to
a statement as an aid in later analysis, debugging or documentation.
2 -.comments are optional
3 - comments do not affect the assembly process or the object prOQram
(and hence do not affect program execution). They are merely
printed in the lising.
4 - the comment field must be preceded by a forward slash (/). The
slash may be the first character on a line (if the entire line
is to be taken as a comment) or may be preceded by:
a. space(s)
b. tab(s)
c. semicolon

12-12

'tC
$LOGI N C ES

nOS-15 V3A000

$A PP -13
$A LP ,..12
!I( ON

$EDIT

EOI TOR V3A0~e
>rlPEN 7 TABLE
rILE lTARLE SRC NOT rOUND.
I NPlJT

.ASS

LOOP

.Loe 1~0
LAC K '-00
DAC A
lAW -100
DAC C NT'
DZ- A
ISZ A
IS! C NT

ILOAD AC WI TH START I NG LOC
IDEPOS! T AC I NTC START! NG LOC
/lOAD AC WITH NO. Or LOC TO CLR
IDEPOSI T -C I NTO NO. C NTR
IZ ER 0 ClJ RREN 1 A!) !)R ES S
II NC AD9R£SS
I I NC NO. C OU fOT, SKI P I ' DON E
INOT DONE, GET NEXT ADORESS
IDONE

JMP LOOP

HLR\r
~08

~00

.END

EDIT

>EXIT
nOS-15

\(3A~A0

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~ N... 7.TA8l~
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SI7.E:~AI14
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DOS-15 V3A00rt9
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l2-13

pAG':
1
2

ZTABLE.

5
5
7

"- • 1 ~ '.'
.- 1 " ..
,! 1 ~ 1
;~.-\ 1 ;." 2
ii'?ll3
:11 7' 1 .,~ "

'.r, " 1 v' !)

~.'" ~/1

1/
11
12

13
14

1.·-

1 ~/~ n

Ii:' 1 ;." 7
,1 1 1 v.
,'1 i" 1 1 1
.? ~--1 12
v·~

S~C

2,' .,~ t 1 2

,_COP

C~~TU
~

I~Z

1"'(1

L r;nr;-

r,ll T
A

40~~

i\ ( .,~.

42(3

• E ~,I')

~, r~ .-4 ,~ ~i ;,'

S I l E 2I,,~ ~ 1 1 4

- Z"-,;,*

rSZ C~T

5 j~,~ 1 .,~ .a

o ~:,~4f,·(.:\

J(A~P.

74...,V4.:'
i~' ;" J! ~ )i l

1~?-

I At"...

- !.~ It.
A!. -1~'"
- A:

A 41~' 1 1 1

1777-,.' <'
~4i1-1 13
1 f5 :, 1 1 1
44\i] t 1 1
44:\ 1 1 "t

AoS
..Lur.

"If)

t:. J..' t' (i~' I. I :~F S

ILOA~ At. ~IT~ STAriTIN~ ~OC
/0EPOSIT AC I~TO STARTI'G ~nc
ILOAD AC ~ITH ~O. O~ LGC TC ~LR
IDEPOSIT AC I~TO ~O. rNTR
I Z t. Q L) CUR R E "I T A0 n~ E S~

III',C A['DRE'SS
I I !'l C I'J a • Co U NT, S t( I';'; IF Df! f'.J ~
'/",IOT 00";£, GET NExT ,Ai'ORf:S~
II)Q~,IE

OBJECT PROGRAM OUTPUT
The absolute (.ABS) pseudo-ops cause absolute, checksuirned binary code
to be output. If no value is specified in the address field and if the
output device is the paper tape punch, too asse.bler wi 11 precede the
output with the Absolute Binary Loader (ABL). which will load the punched
output at object time. The ABL is loaded via hantware readin into location
17720 of anY memory bank.

17720

.• ASS
LOA6ER
USER PROGRAM

.END START
To Load your program:
Set address switches to 17720
STOP, RESET

READIN

To start your Program:
Set Address Switches to your
PROGRAM STARTING ADDRESS
STOP, RESET
START

12-15

PAPER TAPE

PROGRAMMING ASSIGNMENT
Write at least one of the following programs:
A.

Write a program that will read two values from the console data
switches.
If equal
If Unequal
NOTE:

Halt with the AC = 0

~alt with the AC = -1

Use the two's complement version of -1, I.E. 777777.

Write a program which reads a value from the console data switches and
counts the number of bits that are set to 1 in the value.
Have the program'halt with the final answer left in the AC so that it
may be checked via the console switches.
Example:

DATA SWITCHES = 102376 OCTAL
NUMBER OF BITS SET = 11 OCTAL

Write a program which reads a value from the console switches and reverses
the octal number. Have the porgram halt with the reverse value in the AC so
that it may be checked via the console data switches.
Example:

DATA SWITCHES = 762415 reversed value = 514267

12-16

DEVICE: TTY RECEIVER
~---------~4~~~~~ERIAL

CPU~

TTY RECEIVER (KP64)

AL...

~~~------------~

IO'l'S

IOPU
,.... INT I O P 2 ' - - - - - - - - - ' - - '
*
~
50-03

PI FACILITY
(PROGRAM
I.
INTERRUPT)~~~----------~-----J

~
C3

riI
l

BUS IOP1

-KBS L

l.-

ll::
P'l

KSF 700301
(SKIP ON KEVBOARD FLAG)
EXECUTION TIME 2 to 3ms

KRB '00301
(READ KEYBOARD TO AC 10-17)
Aw.{,) CLBS THE FLAG.EXEC.TlME 3-4 ms

KRS 700332

700301
KSF (IS IT YOU)

.110

POLLING
ROUTINE
EXIT

......

r a-

(YES ITS ME)

><
.110

SERVICE
ROUTINE
FOR K!ID

EXIT ROUTINE
ION
RES/DaR
JMP*O

13-1

(REAl) FULL DUPLEX TO AC

AltO SELECT .READER.
EXEC.!'IME 3-4ms.

10-17)

DEVICE: TTY TRANSMITTER

'I~---==:f ____~==~~--~------.-----SERIALLY OUT

TLS

J1
.....,----.,.,

IOPU
--.. INT .-IOP4 1""-----SD 04

BUFFER

I IL

SHIFT

DON'T
~Y_E_S"""T"_"" SHIFT

FINISHED
,P.I. FACILITY
; PROGRAM
TELEPRINT
, INTERRUPT
~~~_F_LA
__
G~~__~____~________________~: ,~--+FLAG

700401
TSF (IS IT YOU)
----........- - - - r
BUS IOP111
POLLING
TTO SKIPL
ROUTINE
EXIT
..j..-..
__ ,

i---- I.-LI

,.-~r___-........r---(YES ITS ME)

•

SERVICE
ROUTINE
FOR TTY
TRANSMITTER

III(

lOTS'
1.

TSF 700401 - SKIP ON TELEPRINTER FLAG

TCF - 700402/ CLEAR TELEPRINTER FLAG

TLS - 700406/ CLEAR TELEPRINTER FLAG
LOAD TELEPRINTER BUFFER
AND PRINT.

•

TELETYPE TRANSMITTER (KP65)

EXIT ROUTINE
ION
RES/DBR
JMP*O

13-2

IOT*-DEVICE Xf'ER

A
C

h
r

I
I

RCVERS

I
I/O BUS 10-17

PC05 PUNCH

PC1S CONTROLLER

BAlS

PROCESSOR

~~--~~~~~~~~~~--------------------~~P

I
I

PUNCH HOLE 8

(OO:ALPHA

-ACll
LINE LOW WHEN BINARY SDOO(L).

I
I

PUNCH HOLE 7

/-----------------1 C

SUB DEVICE -

B
F

THRU 6~__r-------~D~E~V~IC~E~S~E~L=EC~T~E~D~{~0~2~)I~p~U~N~C~H----,__________________________________~
I--'
W

I
I

14
10P4
O-PUNCH
lSr-------~----------------------------------------------------------------~~__~

lOP 2

I
lOPl DEVELOPED AS
A RESUL'r OF, PSF
700201, AN lOT
INSTRUCTION IN THE
POOLING "ROUTINE.
THIS IS THE WAY THE
PROCESSOR FINDS OUT
WHO MADE THE PROGRAM
INTERRUPT REQUEST
(PI)

PROGRAM. INTF.RRUPT REQ

PUNCH FLAG

I
I

-- ~FLAG
l-PUNCH

ACTIVE)
CDELA'i-:)
' C P U N C H DONE:
~ PUNCH

~N~

C; t PUNCH FLAG

I~·---t-------~i----'--------------~f------~I:od-------SKIP REQUEST

lOp1

~r-~I______--~I------P-UN-C-H--S-K-I-P----------~t--------~.

I
I

,
I

lOT
OBJECTIVES:

Describe the format of lOT instructions.

Describe in general terms the function of
device select codes, sub-device select codes,
and lOP signals.

Describe the logical operation and timing of a
basic IOT instruction.

14-1

lOT FACILITY

lOTS USE:
1.

CHECK FOR SKIP CONDITIONS

PROGRAM CONTROLLED DATA TRANSFERS, TELETYPE,
PAPER TAPE READER & PUNCH, ETC.

- 3.

SETTING UP CONTROL OF BLOCK TRANSFER DEVICES.
DATA TRANSFERS FOR BLOCK TRANSFER DEVICES ARE
DONE BY THE DATA CHANNEL FACILITY

READ STATUS OF DEVICES ON I/O BUS

I/O BUS
"STATUS"

!DEVICBS

lOT INSTRUCTION

o 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

OP CODE

~~~,..-.~~

DEVICE SELECT SUB
DEV.
SEL.

TO
ADDRESSABLE I/O
BUS

A
C

-------------------

..----------~

CODE
FOR lOT

lOT CONTROL TIMING
BIT 17=1 GENERATE~Pl
BI T 16= 1 GENERATE -:tOP 2
BIT 15=1 GENERATE :1DP4
BITS 15&17=1 GENERATE
IOPI FOLLOWED BY IOP4
BITS 15&16=1 GENERATE
IOP2 FOLLOWED BY IOP4

THE ACCUMULATOR REGISTER IS USED IN CONJUNCTION WITH THE lOT.
ACCUMULATOR IS USED TO:
a) TRANSFER COMMANDS TO A PARTICULAR DEVICE
b) DATA TRANSFERRED TO A DEVICE. AC--. DEVICE
DATA TRANSFERRED FROM A DEVICE. DEVICE~AC

14-2

lOT BLOl.

JIAGRAM
NO

MI
7
0
0
3
0
1
~

INHIBIT MEMORY CYCLE
: INHIBIT INTERRUPTS
BIT 14:::1: CLR AC

....

T
D
E
C

...

lOT
.. . DONE

HANGS UP
CPU

J, ___

YES

TS03*~3

RELEASE CPU
.. ~ ~ INSTR

-.,

YES

...a

GENERATE
lOT REQ

....

.- I/O PRIORITY CHECK

I-OCH OPERATION IN PROGRESS
2-CLOCK OPERATION IN PROGRESS
3-IOT OPERATION IN PROGRESS

A t----t

Tl : SET lOT SYNCFF
START lOT TIMING
GENERATE APPROPRIATE
BUS lOP PULSES
'toP 1 ,:IOP2, ,JOP4

.... T4: SET lOT FF
DEVICE SELECT
BITS ON LINE.
SET UP AC FOR
DATA TRANSFER

lOT DONE BLOCK DIAGRAM

lOT
DONE

THIS CONDITION IS A NOP

lOT DONE TERMINATES THE
rOT OPERATION
GENERATE
BUS IOPI
CHECK FOR
SKIP
CONDITIONS

lOT
DONE

.....

YES

GENERATE
BUS IOP2
READ DATA
INTO AC

BIT 15 MUST
BE A 1
DATA USUALLY
SENT FROM
AC --. DEVICE
GENERATE
BUS IOP4

lOT
OONE

lOT
DONE

lOT DONE TERMINATES BY
THE FOLLOWING MANNER:
KP51 RESETS IOTpF
RESETS lOT SYNCFF
KP35 RESETS lOT REQFF
KP34 RESETS START RUN
KP21 ENABLES CPU TO START

RUN
KP76 SHOWS CPU GOES
TO EXECUTE MAJOR
STATE TO READ
IN THE INSTR. RD
RST IS USED TO
LO MI. AT THIS
TIME lOT DECODE
DROPS.

KP32

~30

KP32

TO KP26

HOLJ?u

MI
7

CP
~a..----...iiI~ CP PEO
M REQ
NOT SET.
THIS
HOLD
MEANS CP ACTIVEFF

EN CP MEM REQ HOLD H

"'INH D~....,..;~
-JCEY~......_ _.....
lOT

...

DECODE

n.~

USER MODE B(O)L

DOES NOT GET SET

"CAN'T START A
MEMORY CYCLE"

HS CLK
CAN'T GENERATE
AN INTERRUPT

KP21

KP3S

K13

SIGNAL NOW L

KP2I

KP21

"HANGS CPU IN
TS03* @3

KPSI
KP28
KP31 F*TSOI
K21 PHASE I

KPI9

LOW

PI -.-----

(I).uL-_~1

CLEAR AC

BITI4=1
LD AC

CPU LOGIC FOR lOTS
IOT_ lOT
-.
DECODl:.

INHIBITS-MEMORY CYCLE
- INTERRUPTS
AC
BIT=I-0

I NO
-po

CPU BLOCK DIAGRAM FOR lOTS'

GENRATE
IOTREQ

~KP5I

HANGS UP
CPU
TS03*~3

-...

lOT
DONE

YES

RELEASES CPU
GET NEXT INS'J;'RUCTION
AND GO

\arE:

lOT OONE S ETS
START RUN FF ON
KP34

WHICH ENABLES

RUNFF ON KP21
TO GET SET

KPS1

M2t:~~

CLK
32

DCH

TIME

lOT SYNC (O)H

-22

KPS1

lOT
~
~

KPS1

TIME 4P
KPS1

~
~

H
U

J2 0

KP.S5

I/O LINES
B H

KPS1
T4
10Pl(0)H L2
lOP2(0)H M2
10P4(0)H N2

.....
0I::I

KP-S1
KPS1
MOS
M106(1)L- _ _ _ _ _ _ ~ ____ 00

PRIORITY CHECK OPERATION

O~O~H~~~~~~~~~~~~~~~~~~~~~~~~~~~

MI07 (l)L- - - - ___ ~ ____ DS 01 H
MI08 (l)L- - - - - _ _ _H~ ____ DS 02 H
MI09 (l)L- _____ .J<~ ___ DS 03 H
MIIO(l)L----- ___M~ ___ DS 04 H
MIll(l)L- - - - __ Yl ___ DS 05 H
MI12 (l}L- ______T1 ___ SD 00 H
Mll3 (l)L::1 2 I.- _ - SD 01 H

TO ADDRESSABLE I/O BUS
(WHAT DEVICE DOES THE PROGRAM WANT TO TALK TO

ENABLE I/O LINES B H
)
'----ENABLE I/O LINES (1) H ~
ENABLES
"'-_ _ _-,ENABLE I/O LINES (1) L (
ADDRESS TO THE I/O BUS

"REMEMBER"
RDRQL
lOT INSTRUCTION
IS IN THE MI REGISTER

KP49

DEV
F2 TRANS L

KRBL

KP49

READ STATUS
EN I/O LINES(l)H
I/O STROBE AC EN USED FOR DATA TRANSFERS
COMING INTO THE ACCUMULATOR

_ _- L_ _

~D--~A~l~~ AC-I/O BUS

IF
BIT 17:1 { BUS IOPl
STK>BE IOPI

: I

'I IOP2 TIME

12pf TIME

I BUS IOP2

STROBE IOP2

lOT OONE (ONLY IF
-MORE)

lOT DONE

I I
0

IOP4 TIME

]

BUS IQP4

(ONLY IF
-MORE)

101' DONE

KP-sO
BUS
IOPl

I/O BUS
TO ALL

'-----I

FLAG

DEVICES ON BUS

LOGIC CHECKING

KP23

FOR SKIP CONDITlONS

SELECTED
DEVICE

PC ENABLES

KP19
INC PCL

KP19

ENA PC-A 03-04L
KP19
----flU'18~~

KP19

__~~

05 H

LD PC

06-17H

05 H

~ PC-A 01-02 H

15 MODE

KP19

PC-A 03-04 H
TS 0 1 +TS'C)3 * SET FETCH
CLOCKH 1 . -_ _ _ _--1
9MODE

-----to

05 H

TRANSFER FROM DEVICE TO ACCUMULATOR
BIT 14=1 ; CLR AC BEFORE THE XFER

KPSO
MOS

KPSO
BUS IOP2

IOP2 H
I 0 BUS DATO
'1

SELECTED
DEVICE (PTR

E
C-A BUS
I-'
~

KP24

I
00

KP19

KPI9

STROBE
I/O BUS-CH

EAE

I/O BUS-C L

(0). H

-OPR SHIFT H
-CLA*TSOI*F H
-SWHA*TS02*F H

NO SHIFT-D H

EAE NO SHIFT
F2
Kl

D2 _____. _

DEV TRANS L

DEV TRANS H

T2
U2
EN I/O LINES (1) H

PROGRAM CONTROLLED TRANSFER TO DEVICE

KPS3

KPSO

-OEV TRANS

MOS

EN I/O LINES (1)

IOP4 H

SELECTED
I/O DEVICE

PROGRAM CONTROLLED TRANSFER TO DEVICE
AC ---+ DEVICE
LOAD BUFFER WITH 10P4

lOT INSTRUCTION:

70 02 04

PUNCH ALPH

70 02 44

PUNCH

BINARY

KPSO

READ STATUS

KPS8

KP58

-INT DSOIH
-INT DS03H
INT DS04H

KPSO

1CP50

IORS

I HI

-!~ B§8~U

,
I

-INT SDOOH
-!NT LSOOH

MEM 15

+3V

I
L

I•

lOT 03

M771
N14

- - - - .- - - - - - -

KPSO
MOS

E3>'~2K.-

___T
..M......m_S........

_-U

I
I
NOTE; DEV TRANS L PREVENTS

AC ..... I/O BUS

"lOT INSTRUCTION"
70 03 14
LCLR AC

lOBUS
I-'

I-'

STATUS TO AC

DEV TRANS H

BITS THAT ARE USED TO SELECT A DEVICE "03" SPECIFIES THE CONSOLE TELETYPE KEYBOARD.
THIS DEVICE DOES NOT USE THE IOP4 SIGNAL.
IT IS ALLOWED TO GO OUT ON THE BUS BUT
NOTHING HAPPENS.
THE STATUS IS READ INTO THE ACCUMULATOR IN 10P2 TIME.

PROGRAM INTERRUPT
OBJECTIVES:
a)

DESCRIBE IN GENERAL TERMS THE PROCESSING OF A PROGRAM INTERRUPT
BY THE CENTRAL PROCESSOR.

STATE THE PROGRAMMING CONSIDERA'l'IOliS i.DCESSARY WHEN USING THE
PROGRAM INTERRUPT FACILITY.

DESCRIBE 'lllE LOGICAL OPERATION OF THE ION, lOF, .ANp DBR, RES
IOT INSTRUCTIONS.

EXPLAIN THE LOGICAL OPERATION MID 'l'lMIJIG Or' A PROGRAM
INTEl'UmPT USING THE LOGlC PlUWTS.

15-1

PROGRAM INTERRUPT FACILITY

(PI)

QUESTION:
WHAT IS THE PURPOSE OF THE PROGRAM INTERRUPT?
ANSWER-

00 AWAY WITH THE WAIT LOOP IN A SYSTEM PROGRAM.
WAIT LOOP
KSF

DEDICATED I/O

JMP.-1

TAKE NOTICE NOTHING ELSE HAPPENS EXCEPT THE PROGRAM HANGS
IN A TIGHT LOOP WAITING FOR THE DEVICE TO RAISE ITS FLAG.
WAIT LOOP

INEFFICIENT

QUESTION:
HOW OOES THE PROGRAM INTERRUPT IMPROVE OVER THE WAIT LOOP?
ANSWER-

BY ALLOWING THE MAIN PROGRAM TO RUN UNTIL THE DEVICE INTERRUPTS
THE MAIN PROGRAM TELLING THE PROCESSOR THE DEVICE NEEDS SERVICING.

MAIN PROGRAM

105 +-P1--.-...,
106

r--"'- "-"

DEV

QUESTION:
WHO MADE THE INTERRUPT ?
ANSWER - DON'T KNOW
QUESTION:
HOW CAN WE FIND OUT WHO MADE THE INTERRUPT?
ANSWER - BY SENDING OUT lOTS THAT CHECK THE FLAGS OF EACH DEVICE.
RESPONDING TO THE DEVICE THAT HAS ITS FLAG RAISED OR BY
READING STATUS (IORS)

15-2

PROGRAM INTERRUPT FACILITY

i!2l

105
106

(PI

I
I
I

DEV #11

II
IDEV #21

I DEV 13 1

I
I
I I

1 I
IDEV #4 ]

DEV 15

WHEN USING THE lOT SKIP CHECK PROCESS, A SKIP CHAIN IS USED.
IN THE
SKIP CHAIN PLACE THE DEVICES WHICH HAVE HIGHRST PRIORITY 1st AND LOWEST
PRIORITY LAST.
EXAMPLE OF SKIP CHAIN
PFSF· - 703201/SKIP ON PWR LOW FLAG
JMP. +2
JMP TO PWR FAIL ROUTINE
KPSF - 706301/SKIP ON DISK FLAG (RP-15)
JMP. +2
JMP TO DISK PACK SERVICE ROUTINE (ERROR + JOB DONE)
DTDF - 707601/SKIP ON DECTAPE FLAG
JMP. +2
JMP TO DECTAPE SERVICE ROUTINE (ERROR + JOB DONE)
MTSF - 700301/SKIP ON MAGTAPE FLAG
JMP. +2
JMP TO SERVICE ROUTINE FOR MAG TAPE (ERROR + JOB DONE)
KSF - 700301/SKIP ON KEYBOARD FLAG
JMP. +2
JMP TO KEYBOARD TTY SERVICE ROUTINE
JMP '1'0 ERROR ROUTINE

EXIT ROUTINE

KEYBOARD SERVICE ROUTINE
1.

SAVE REGISTERS THE MAIN PROGRAM
IS USING.

ION TURN PROGRAM INTERRUPT
FACILITY BACK ON.

KRB/READ THE BUFFER INTO THE
ACCUMULATOR

RES/DBR - SET UP RESTORING OF
L,B,UM

DAC INTO INPUT BUFFER

JMP*O - GET BACK TO LOCATION
106

JMP TO EXIT ROUTINE

15-3

PROGRAM INTERRUPT FACILITY

(PI)

NOW IT CAN BE SEEN WHAT HAS TO HAPPEN WHEN AN INTERRUPT IS RECEIVED.
1 - LET CPU FINISH INSTRUCTION
2 - HANDLE INTERRUPT (TURN OFF INTERRUPT FACILITY)
a)

b)
c)

d)
e)
f)

WRT L,BM,UM, PC3-17 INTO ADDRESS ZERO
GET NEXT INSTRUCTION - GET TO SKIP CHAIN
FIND OUT WHO RAISED THE FLAG
SERVICE DEVICE
EXIT THIS ROUTINE BY TURNING ON THE INTERRUPT
FACILITY & IF NEEDED RESTORE L,BM,UM
JMP * 0 GET THE NEXT ADDRESS AND PROCEED IN THE
MAIN PROGRAM.

15-4

PROGRAM INTERRUPT FACILITY
"'OPR

P.I.E
LIGHT
P.I.E

P.I

-API RQ

SET FETCH
I

~....---~II

TS02*~3

PRIVILEDGE
INSTR ?
IOT,JMS,
AL, XCT , NORM

l' INTRPT ACK:

SET FE'OCH

EHABLE

HANG CPU TS03*

*
'l'S03*CLK H

INTRPT

*-CPACT

T4:1'PI
T1: l'PI SYNC

PI
REQ

\Vr~

PI SYNC:J,P.I.E

:fpL3
INTERRUPT CW
I/O BUS

INTRPT STATE
TSOl:CLR IR
FORCE GRP2:
SMW

P.I.E
LIGHT

L;BM,
UH, pc..,..

3-17MO

Q OFF
L-P.I.E
---']

....._---_...#

CP ACT*
START WRT
*TS02*~3

-*-TRAP:
CP WRT ADD

INTO ADDRESS ZERO

T4*PI SYNC:
INTERRUPT STROBE:
FETCH*TSOI
J.INTRPT ACK
1'INTRPT STATE
... : INHIBIT
LD -MO, OA
DECCDES
WITH EROS
~PIFF
Tl *-PI: PIJ,SYNC

MRIS:
IDMB
PROCESSOR
RCVS MRLS ACK:
~CP ACT BY
END OF CP
CYCLE

l"'~

OA = 1 GET NEXT
INSTRUCTION
(SAVE REGISTERS
IN USE & GET TO
POLLING ROUTIME

EXECUTE
TSSJl

TSSJ2

TS~l

TS~3

I)! 1112 13 ~ 1112 b iJlIJ 21 3
-ME 4

rrS~2

1 2 3~ 1 2 3

TS~3
fiJ

EXE
TS~l

1 23 ~ 1 2 3

ITIME 1 ~-IME2ITIME3ITIME41TIME*IME2E?ME3rTIME 4 ...!{'IMJ:;1 TIME2

TIME3

KP51 PIE (1)
KP5~PROGRAM

FETCH

INTERRUPT -'

KP 35 INTERRUPT

KP35 INT.ACK (1)
KP35 EN INTERRUPT
KP35 PI REQ
KP51 PI (1)
KP51 PI SYNC (1)
KP35 INTERRUPT STB
......
U1

I
0\

KP35 INTERPT STATE (1)
KP48 INH DECODES
KP35 INTRPT CLR IR
KP30 GRP 4
KP19 L,BM,UM-A
KP24 LDMO, LDMA

I
I

~nhibit LD IR

____________________________________________

r-l~

131___________
________________________

____________________________________________~nhibit-C-A BUS

PROGRAM INTERRUPT TIMING

KP50

KP5I

KP50

M05
D
E
V
I
C
E

LIGHT THE LIGHT

V2
PROGRAM

PIR L

ROG INT

RQL

INTERRUPT

-AP

RQ H .

LIGHT.

S
STATEMENT;

DIS ABLE

DEVICE RAISES PROGRAM INTERRUPT SENTS TO PROCESSOR AND
IF AN API REQ IS NOT PRESENT AND THE INTERRUPT FACILITY IS
TURNED ON THE INTERRUPT CAN BE PROCESSED.

XCT ----'111'--"

-lOT

OPR HALT L

KP-5I

SET FETCH J2
TS02*$13

INTERRUPT

F2
FORCE FETCH(G}H
H2

J2
--~

.....

TRAP H

RESETS RUNn-

ON KP21.

...,J

INTERRUPT STBL H~...-__

CPU HARGS UP
TS~3*"3

STATEMENT:

CPU LOOKS FOR INTEftRUPTS. (INSTRUCTION HAS BEEN PROCESSED).
CHECK TO
SEE IF THE INSTRUCTION WAS A PRIVILEGED INSTRUCTION, IF SO, DON'T SET
INTRPT ACK, IF NOT A PRIVILEGED INSTRUCTION SET INTRPT ACK.

KP 51
SET FETCH * TS03 * eLK H T2
INTRPT ACK (1) H
U2
V2
CP ACTIVE(O)H
STATEMENT:

EN INTRPT L
)
F23_

~ EN INTIU'H

___

CPU IS DONE WITH THE MEMORY CYCLE GENERATE A PI REQ.

KP51 .~

INTRPT
STROBE

PRIORITY
PI

START RUN

KP35

TIME 1

31G)

TIME 4---

N22

Time 4

LD MO, OA
LOAD ZERO'S INTO OA, MO.

DECODES

TS03H Jl

D2
MAIN PROG
35

KP24

INT ACKL

"INHIBITS

~~__~~

PC+l TO PC

105
106

PC LOAD L

~4t----I-N-ST. AT 105 COMPLETED

INTRPT

PC STAYS AT 106

INTRPT ACK PREVENTS THE PC VROM BEING INCREMENTED
STATEMENT: PRIORITY CHECK MADE & SETTING PISYNC TURNS OFF PIE
FACILITY. THE NEXT T4: INTRPT STROBE
INTRPT STROBE:
LD MO, OA WITH ZERO
t START RUN ALLOW CPU TO GO TO FETCH MAJOR STATE
oJ,
INTRPT ACK

......

111

ex>

INTRPT S
(l)H
TSO 1 H

INT INH SET MO L

--"'I-""'"

R - -....... NTRPT

CLR IR

KP31
KP69

INTRPT STATE (1) H
JOo_ _
L_lo

~__~

[3>
MOl

H03

_M_l_ _ _
IN_T_+_AP_I_S_T_H_ _~)~.::...>-_ _t-JK~2L--t.r_ _ _ _ _--.l PRE
~

(KMIO)

CLR IR 00-05

J(PlO- INtI DECODES

ADDgESS - ZERO IS IN Me, OA

KP3Q

KP30

-START ......,........
2
__ Q:w2H.
U
(F+D}H V2

IItOO(O)H
IItOl(O)H
-KEY+RI J:NHIBIIH _ ..._~

(MEMORY C<HmND)

DO THE MEMORY CYCLE ROUTINE

KP19

GRP 4*TS02*(F+D)L

~2
L,
F14

.BM' UM-+A

KPOI

KP02

}(PO 3

~ABUS

KP47
-,....__C-A 01-02
R

KP 30

IROO(O
IRO 1 (O~)~~.....-~ JDI'o......
IRO) (O)'......--t.l1H

-KEY+Rl

EXECUTE MAJOR STATE

INHIBITH

OA + l-+MO
DO THE NEXT INSTRUCTION

KP30

GRP4
Rl

Sl(F+D)
TS02iM-~_

TOPIC

OBJECTIVES:

Upon completion of this unit the student will be able
to:
1.
2.
3.
4.

BA-IS PHERIPHERAL EXPANDER

state the function of the BA
Draw a block diagram of the BA
Construct the relationship between the BA & PC
Differentiate between the systems included in the BA

PERIPHERAL EXPANDER
1.

Purpose
BA is a-universal controller used to m~n~~ze bus loading
by serving as a contro~ for options that are infrequently
used.

Options
a)

PC-IS high speed paper tape/reader, punch
(1) Reads 300 characters/sec
(2) Punches SO characters/sec

LTlSA - Single teletype control
(1) Background/foreground

VPlS Display Console
(1) Interfaces various display devices
by providing D/A convertors and control
logic for X-Y positioning as well as
intensity.

Discuss the block diagram of the BA

16-1

-SA-IS

WRITE OPERATIONS

Uses Only

PUNCH

BITS 8-17

CONTROL

READER

BUFFER

READER

READ OPERATIONS

...

r--

BITS

CONTROL

con~rol

I/O
BUS

BLOCK DIAGRAM

LT-15
CONTROL

1'""-rY

B
A

...

STATtE
BITS

CONTROL

OOTA PATH

I
T
S

I/O

R
I

BtE .

E
S

I
I

.....

TTY

RCVR

LTIS
... BITS
r"

PAPE! TAPE

.di

DATA PATH

A
0

.....
.....

........

D
E
R

"An
8
U

"C"

B
U

I..A I/O BUS

.....

a,,- .........
15

Pc15

.......

PC-

.....

.....+~

~
L CONTROL LINES

* EN lOP 2 :BAC-+C BtE

orad with data on
Result loaded into AC

Contents of AC

EN 10P2*IOT RD2:1/0 BOS .... C BUS

I/O Bus.

PC15 - 2 Il¥:>des of reading RSA - 700104 - Select Aplhanumeric Mode
RSA - 700144 - Select Binary Mode

......

0'
I

TAPE FORMAT

DINAR! MOPE Assembles One 18 Bit Word

ALPHA Mode Assembles One 8 Bit Word
ALPlfA f«)DE

Bl NAlrl t«lDE
CHANNEL

• • • •••
•
•
• •

C
0
N

T
R
0
L

•

~TA

OfANNEL

•• •

•

If--- DATA FIELD

•
1JIi.

REAIER SELECT ALPHA -

700104

YES

IOT 0104

0-+ FLAG
GATE DATA

P -15

05
SERVICE
ROUTINE

0-+ FLAG
O~BUFFER

RUN

PC1S-03

TAPE MOVING

READER
INTERRUPT
NO

o ~ API REQ FF (02)
O~

Yf;S

:(~O:T~BE

RDR INTRPT

[

RUN

FLAG (03)
RDRINT (03)
}-+ RD DATA (03)

1......... FLAG

DATA IN BUFFER

PC
TO PROG INT
FACILITY

PC 15

YES

DEV TRANS
(AC INHIBITED FROM
I/O BUS

TO SKIP
l~FLAG

FLAG:
l~ READ DATA
1~ ROR

INTER

GATE DATAI/O BUS
RB10 & 11 FF
RB12-17 GATES

BACK TO
MAIN PROG

16-4

I/O BUS
.

SKIP

STROBE

~;::;

lOT
BITS
6-13
BITS
15-17

REO

BA-15

~~__~:~RMQB~S~K_T~P__~~ iOT. ~~~R
t OS

'
t

PC RDR SELECTED

.....D_E_V_ _ _S_E_LE_CT....,..BA,DS BITS ......- - t
SELECT BA SD~: BITS

{~ , ...J
~I

I
) 07 .

t SKIP REOUESf
I

7s0NSL
t
,t---------il
BA lOP!

BUS IOPI

,
I

1 " - -_ _ _ __

SKIP CHECK WHO MADE THE INTERRUPT
ANSWER THE PAPER TAPE READER

GO TO THE SERVICE ROUTINE FOR PAPER
TAPE READER RRB

(700112) READ READER BUFFER

16-5

AD R I/f) TAP~ Il

r------'

.,.,.

~."T ••

, T'-"

__":.II! _

1,.0fI0l(.

N7/S

11,11'

•

I-'

0\
I
0\

~----

a PWR(/)

0IfC

' -_ _ _......:._..J ~~~

It.

•

--/7

PAPER T.

MOVE BIN

PC05

PC15

...

READER

....

MOVE TAPE
"'t . .

R
E

.....

GIVE IT TOME ....

........

HERE IT IS

U
F
F'

R
.~

CNT=l

R
E

I/O BUS

A
1
5

......

.....

.......
t40VE TAPE
GIVE IT TO ME ....
-..
HERE IT IS

.....

DATA

....

r-"

....GCYr DATA
MOVE

.,......

TAPE

CNT=3

.....

HERE IT IS

......

SAME

.... GOT

...

DATA

•••

•...
••
••
•

GIVE IT TO ME_~

....

••
••

...
G
A

PHaro CELLS

SAME

.CNT=2

INTERRUPT

•••
••
••
•

r-- •

CONTROLLER

DEVICE

MOVE TAPE --..
GOT DATA
..GIVE IT TO ME --+
HERE IT IS
4-CONTROLLER SEQUENCE

READ NEXT
RDR FLAG
READ DATA
DATA

READ DATA :

ST~RTS

(1 OP4 )
(lOP2)

CONTROLLER SEQUENCE
DELAYS 125NS
1. READ STROBE: LD REG
2. DELAY 75NSiADV.STROBE#1-CNTS THE COUNTER
CHECKS FOR CNT OF 3*FLAG:RDR INTRPT
3. DELAY 50NSiADV.STROBE 2: NOT CNT 3 MOVE TAPE

PAPER TAPE FORMATS
Program tapes are supplied in one of two formats:
10

HRI (HRM) Hardware Read-In Mode (.FULL assembly parameter)

BINARY or ABS

(.ABS assembly parameter)

HRI Tapes consist of 18 bit data and instructions punched in binary mode
(PSB), which are loaded in sequential memory locations via the HARDWARE
READ-IN feature. The last word is an instruction which is to be executed
when read (i.e., HLT or JMp). The last word is indicated by hole #7 being
punched in the last line of that word.

•

•• • •• ••
•• •• •• •• •
•
•

••
••
•

•

••• e

•
•

••
• •
•
••
••
••• •e •• •• • •
•• • ••••
•• • ••• •
•• ••• • •
••• •••• •• • •
•• • •• •
•
••
•• •• ••
•
••
•
•

•
•

•

JOAD ADDRESS
"----SUPPLIED BY
ADDRESS SWITCH
REnISTER

16-8

• FULL

.LOC

10~

TEMP
TEMP

BEG

ABS or BIHARY paper tapes consist of 3 basic parts:
1.

ABS loader program in HRI

Data blocks

Start block

The ABS loader is a program in HRI format which when read via the READ-IN
key will load the remainder of the tape under program control (BIN LOADER).
The BINARY LOADER expects the rest of the tape to be in a block format.
DATA BLOCK -. consists of 3 control words:
1•

LOAD ADDRESS

WORD COUNT (not exceeding 25)

CHECKSUM

START BLOCK - A two word block at the end of tape. It is distinguished
from a data block because bit ~ of the first word is a one.
1.

STARTING ADDRESS (-l=hlt)

DUMMY WORD (not used)

16-9

•
•
•

••

•
•
•

•• • • • •
••• • •• •••••
•

END OF BrNARY
LOADER

•

LOJt 0 Jt DD IIESI
WO"D COUNT
CHECt<SUM

D4'" WO"D 1

•• • • ••

} DIaT ...

W."D 2

ETC.

••

•

•• •••
••• ••••
• •••
•• ••• •••••
•
•

•

STAf\T
6Le C Ie

•
•
•

•

•
•

•
•
•

.1185 PH PEft T({Pe: fOf\MAr
16-10
J) 1.- E .:to

SUBJECT:

HARDWARE READ-IN

SET ADDRESS IN SWITCHES
KP66·
KPSO
KP34

DEPRESS RE~ IN, SET PCO READ IN
PCO READ IN: DSOS*SDOO
peOSEL * BINARY
KEY ACTIVE * START RUN : ENABLE CPU TIMING TO RUN

KP66

KEY ACTIVE
PCC READ IN : RD IN START
RE IN START : I/O PWR CLR WHICH RESETS FLAG & RUN IN
PC05

KPSO

PCO SEL: ENABLE SET OF RI FF * PWR CLR : RIFF
RI * 10P2 : RI START
RI ~ART PULSE : RI STAXl' +( SET ALPH)
RI START + (SET ALPH) :
SELECT BINARY :
ALPHA FF
BESET CNTR TO A ~OUNT OF ZERO
CAUSE READ NEXT TO GO HIGH

PC03
PC02
PC03

THIS CHANGE GETS SENT TO THE DlNICE (READ NEXT WILL
BE SEEN AS A 10P4 WHICH FIRES A SINGLE SHOT AND PROVIDED YOUR NOT Otn' OF TAPE, IJ'HE FLAGFF WILL BE RESET
AND THE RUNFF WILL BE S!!T. THIS IMPLIES TAPE IS
MOVING.
FETCH
TS01

IN THE MEANTIME THE CPU HAS MOVED INTO TS01 OF
FETCH MAJOR STATE.

KP34

READ IN * (NEXT * TS01)
ADD SW-A
ADDRESS IS NOW ON SUM BUS

KP49

KEY AC'l'IVE

THE

KP48

+ READ IN (1) H: KEY + READ IN INHIBIT/
IN!IIBITS GRP 2,4
READ IN : INHIBIT DECODES

KP24·

TI~

STATE 1 * CLK H * KEY ACTIVE : LD MO & OA
THE ADDRESS ON SUM BUS BUT AT THIS TIME A START
~TE CYCLE IS NOT INITIATED BECAUSE OF THE INHIBIT
GROUP 2,4.
WI~

FETCH KP49
TS01 KP34
lG'21

READ IN * READ IN EXEC : RI PAUSE
READ IN PAUSE ENABLES "0" INPUT OF STOP TS RUN
TS02 SETS "STOP TS RUN"
S'I'Qi> TS RUN & OTHE~ LEVELS WILL CAUSE THE RUN FF TO
BE RESET, THE CPU HANGS UP IN TS03, 03.
WAITS FOR READER TO ASSEMBLE 3 FRAMES AND GENERATE
AN INTERRUPT
DURING THIS TIME TAPE HAS BEEN MOVING AND FOR EACH
FEED HOLE, PROVIDING IN THE DEVICE CONTROLLER THE
ENABLEFF IS SET, A STROBE WILL OCCUR WHICH GATES
WHAT EVER IS BEING READ INTO A BUFFER REGISTER AND
SETS THE FLAG FF (IN THE DEVICE)

16-11

THIS GOES OVER TO THE PC15-02 AS READER FLAG
AND IS CHANGED TO SET FLAG IN THE PC1S-02
PC1S-03
PC1S-02

SET" FLAG
FLAG FF
FLAG : READ DATA (DATA IS FOR THE TAKING)
READ DATA : 10P2 ON CABLE BACK TO PCOS
BACK IN THE PCOS THE 10P2 J. FLAG AND ENABLE THE DATA
FROM THE BUFFERS ONTO TIiJ! CABLE TO PC02 RBO THROUGH
RB7
RBO
RBI

HOLE 8
HOLE 7

THIS IS DATA
WITH MORE TO COME

REO
HOLE 8
THIS IS THE LAST WORD
RBI
HOLE 7
EXECUTE THE INSTRUCTION
READ SEQUENCE
PC1S-02 l2Sns AFTER READ DATA : READ STROBE
PC1S-03 READ STROBE * CNT OF 0 * ALPHA : STROBE 1
STROBE 1 : LOAD THE SIX DATA BITS FROM PCOS
BUFFER INTO RBOO THROUGH RBOS
PC1S-02
PC1S-03

200ns AFTER READ DATA : ADVANCE STROBE 1
ADVANCE STROBE 1 * RBO (HOLE 8) : eLK CNTR
CNT OF 1 : GOT THE FIRST 6 BITS

PC1S-02

PC1S-03

2S0ns AFTER READ DATA : ADVANCE STROBE 2 PULSE
ADVANCE STROBE 2 : DO WE HAVE A CNT OF "3" YET.
NO
AT THIS TIME READER NEXT GOES HIGH
AT THE PCOS THIS LEVEL FIRES THE
SINGLE SHOT
ADVANCE STROBE 2 : FLAG FF IN PC03

IN THE PCOS READER NEXT IS RECEIVED AS 10P4 WHICH
RESETS FLAG * SETS RUN TAPE IS NOW MOVING TOWARDS
THE SECOND CHARACTER.
RESETTING OF THE FLAGFF ON PC1S-03 REMOVES READ DATA
FROM ITS ACTIVE STATE (lOP2 AT PCOS REMOVES BUFFER
OUTPUT FROM LINES TO PC1S-02.)
NEXT FEED HOLE

* ENABLE : STROBE
STROBE : DATA IN PC OS BUFFER
RUN FF IN PCOS
FLAG

:+
:t

AS CAN BE SEEN THE SECOND 6 BIT FRAME IS NOW IN THE
BUFFER AND WE FOLLOW THE SAME SEQUENCE AS IN THE
PRECEEDING PAGE; EXCEPT WHEN READ DATA PUTS THE DATA
ON THE LINE.

16-12

STROBE
CNT OF 1
ALPH : STROBE 2 :
STROBE ALPH RB06 THROUGH RB11 WILL BE
LOADED
ADVANCE STROBE 1
ADVANCE STROBE 2

* 8 HOLE

CNT =2

CNT OF 3 ANSWER NO, FIRE
CKTRY TO SET RUN & RESET
FLAG IN THE PCOS. ALSO
CLEAR BUFFER IN PC-O S

PC03 RD START (L) RESETS FLAG
TAPE MOVING TOWARD LAST FRAME OF ONE COMPUTER
(18 BITS)

WO!U{

AS SOON AS FLAG COMES UP THE· PCOS THIS IMPLIES
DATA IS NOW IN THE PCOS BUFFER AND THE RUN
FF IS RESET
PC02 FLAG FROM PCOS GENERATES SET FLAG WHICH
IN TURN SETS THE FLAG FF ON PC03
PC03 FLAG : READ NEXT (10P2 to PCOS)
IN PCOS &

: ~ FLAG

ENABLE DATA ON LINES RBO THROUGH
RB7 to PC02
PC02

12S ns AFTER READ DATA : STROBE 1
DATA DOESN'T GET LOADED INTO ANY REGISTER
RB2
RB 3
RB 4

RB 12
RB 13
RB 14
RB IS
RB 16
RB 17

RB S
RB 6
RB 7

LAST 6 BITS THROUGH GATES

200 ns AFTER READ DATA : ADVANCE STROBE 1
ADVANCE STROBE 1

* FLAG : 1m INTERRUPT

PClS-03 eN'!' 3
PC1S-02

* HOLE 8 : CNT 3

MI04

RD INTERRUPT

* I/O SYNC : RDR AP 1 2, REQ

BA-OS RDR INTERRUPT

* RDR API 2 REQ : PROGRAM

INTERRUPT
NOTE:

1 MS AFTER RDR API 2 REQ AN IOP2 WILL
BE GENERATED

2S0 ns AFTER READ DATA

ADVANCED STROBE 2

PClS-03 ADVANCE STROBE 2

* CNT 3 * ALPH :

16-13

RDR START H : WILL NOT RESET FLAG FF (PClS-03)
RDR NEXT L : THE RUN FF WON I T GET SET

PClS-03

ADVANCE STROBE 2 : NO EFFECT
CNT OF 3 OVER RIDES

f 10P2

KPSI

READ IN READY * TIME 1 :

KP5S

ENABLE I/O LINES * 10P2 : DCH Rl IOP2

KPSO

DCH + Rl 10P2

BUS IOP2 (ONTO I/O BUS)

PClS-02

10P2 * PC SEL

lOT 0102

BAlS-04

lOT 0102 : RBOO-RB17 : BA BITOO~BA BIT 17

BAlS-03

DATA ON I/O BUS
I/O BUS 00 THRU 17

KP49

READ IN * 10P2: PCO I/O CONT
PCO I/O CONT

KP19

Rl ADV

I/O STROBE AC EN

I/O BUS - C

I/O BUS - C BUS : C-A DATA NOW ON SUM BUS
KP19

NO SHIFT - D BUS IS ACTIVE
THE ACCUMULATOR IS ENABLED AND AT STROBE 10P2 TIME
THE DATA WILL BE LOADED INTO THE ACCUMULATOR KP24
I/O STB AC EN * STROBE 10P2 : LD AC (KPSl 10P2 *
TIME 4 : STROBE 10P2
7S0 ns AFTER 10P2 INITIATION DATA IS TUCKED SAFELY
IN THE ACCUMULATOR RDR INTERRUPT ON PCIS-03
GOT RESET AS A RESULT OF lOT 01 02

KP66
KPSl

THIS MEANS ON BAIS-OJ pROG INTER
PROG INTRPT : READ IN READY
250 ns AFTER THE DATA HAS BEEN TUCKED AWAY IN
THE ACCUMULATOR THE NEXT TIME 1 THE 10P2 FF
WILL BE RESET.

PCIS-03

BAlOP2 * READ IN (1) L : GO THROUGH THE READER
CYCLE FOR ANOTHER CHARACTER
REMEMBER THE PROCESSOR HAS BEEN HUNG UP IN TS03 ~3

KP34

READ IN ADVANCE * STROBE 10P2 * RUN : START RUN

16-14

KP21

NEXT CLK :

t RUN

NEXT CLK : TS01 ~O

KP66

STORE

* TIME STATE 3 * 10P2 : . FIRST CHARFF

FIRST CHAR * PCO READ IN : RI STORE
KP30

RI STORE: GRP 2

KP32

START READ * GRP 2 F : (START WRT)
NOTE: ADDRESS FROM SWITCHES HAD BEEN LOADED INTO
MO & OA

TS02

FETCH * TS02

* RI STORE : DAC * TS02 (F + D) L

ACCUMULATOR CONTENTS MUST BE LOADED INTO THE MO REG

KP 24

SAC - C, C-A : ON SUM BUS
CP WR ADDR ACK : LD MO
DO THE WRT

TS03

KP49

RI STORE * TS03

* IOP2 * READ IN EXE

RI INC OA : RI

+ TEST LR CRY

KP48

RI + TEST LR CRY : CARRY INSERT

!<PIg

RI INCR OA : OA - A WITH CARRY INSERT UP DATES THE
ADDRESS

!<P24

RI INCR OA * CLOCK H * RL INCR OA : LDMO & OA
MO IS NOW SET UP FOR THE NEXT ADDRESS. THE ABOVE
INFO (PAGE 1 THRU 5) OCCURS FOR EACH CHARACTER OF
THE HARDWARE
876

1 READ IN

·0
.0

••

16-15

THE HANDLING OF THE LST CHARACTER, WHICH WILL BE A HLT OR
A JMP, WHICH GETS LOADED INTO THE ACCUMULATOR AS NORMAL IN
TS02 :'
FORCE A DAC TO STROE AC IN SPECIFIED LOC A WRITE OPERATION
IS PERFORMED
ACCUMULATOR

TS03

MQ-MDL * READ IN
EXECUTE *

TS03 * PHASE 1 : CP + Rl
RD RST
CP MRLS
R1 RD RST:
END CP CYCLE
KP66:
LD M1

GO TO FETCH IN INSTRUCTION IS IN THE MI DO IT "
TS01, 01 LOAD IR
SIGNAL USED TO TERMINATE ARE
PCIS-03

READ I N FIN ISH

BAIS-03

READ IN FINISH

KPSO

SKP REQUEST

KP66

PCO READ IN & SKP : ENABLE "READ IN EXECUTE FF"

R1 SKP

10P2 & TIME 3 : "READ IN EXECUTE FF"
NOTE

LAST INSTRUCTION READ INTO THE ACC AS NORMAL"

TSOI

00 THE NORM

TS02

FORCE THE DAC

TS03

KP32 MO - MDL

(WRT)

* READ IN EXE * TS03 * 01 : CP + Rl RD RST

Rl RD RST : CP MRLS, END OF CP CYCLE, LD MI, RL RESET
Rl RESET : READ IN, pea READ IN 1 - FETCH
XCT THE INSTRUCTION IN THE M1 REGISTER.

16-16

MEMORY PROTECT

OBJECTIVES:
A)· LIST THE USE AND FUNCTIONS OF THE MEMORY PROTECT
OPTIONS
B)

SHOWN THE BrocK DIAGRAM, EXPLAIN THE COMMUNICATION
SIGNAL SEQUENCE AND DATA F~ OF THE MEMORY
PROTECT OPTION.

EXPLAIN THE FORMAT AROUSE OF THE MEMORY PROTECT lOT
INSTRUCTIONS

LIST THE PROGRAMMING·CONSIDERATIONS NECESSARY WHEN
eSING THE MEMORY PROTECT OPTION.

EXPLAIN THE KM-MEMORY PROTECT FIDN DIAGRAM.
STATING THE LOGICAL
OPERATION OF A MEMORY PROTECT TRAP
CAUSED BY
1) BOUNDARY VIOLATION
2) ILLEGAL INSTRUCTION
3) NON-EXISTANT MEMORY

17-1

ISM - MEMQRY PRqrECT
PROVIDES PDP-IS THE CAPABILITY OF RUNNING
IN A BACKGROUND FOREGROUND ENVIRONMENT.
BACKGROUND
(C) of BOUNDRY-----.•. ~----------I
4REG. DETERMINES
WHAT ADDRESS
FOREIS THE BOUNDRY
GROUND
REFERENCE AT.

MEMORY

THERE IS A SPECIFIC SET OF INSTRUCTIONS TERMED ILLEGAL, BECAUSE THEY
INTERFERE WITH BACKGROUND FOREGROUND OPERATIONS.
INSTRUCTIONS ARE: OAS, lOT, HLT, AND XCT OF XCT.
ILLEGAL INSTRUCTIONS CAUSE TRAPS (INTERRUPTS). SO DO
1) REFERENCING BELOW THE BOUNDARY REGISTER-CHECK
ADDRESSES ON ALL WRITE INSTRUCTIONS, JMP, AND
ISZ INSTRUCTIONS.
2) REFERENCES TO NON-EXISTENT ~£MORY

MEMO~:~CTIBLO~RAM
MDL * MCL
BB 15
BB-lS

BR
LOWER
LIMIT

KT
API

LCPU

LD BR

J::~
70 1704

CPU

SET UP

17-2

I I

MPLD

r.n
REG

TRAP CONDITION

/
TRAP INVALID ADDRESS

KM-10

IN TS~3* PHASE 3, WITH SET FETCH ACTIVE, THE CENTRAL
PROCESSOR IS WAITING TO REC$IVE THE NEXT INSTRUCTION.
RD RST TELLS THE CPU THE INSTRUCTION IS ON THE MDL
TAD: IT.
IF THE MEMORY PROTECT OPTION IS IN THE SYSTEM THE
INSTRUCTION WILL ALSO BE LOADED INTO THE INSTRUCTION
REGISTER IN THE I<M LOGIC. THIS INSTRUCTION IS DECODED
AND CHECKED FOR VALIDI'l'Y, (NO "lOTS, HLT, OAS, XCT02),
IF INSTRUCTION IS INVALID TRAP. ASSUMING THE INSTRUC!'ION IS A VALID INSTRUCTION, EXAMPLE TAKE A DAC
INSTRUCTION, THE CPU GOES TO THE FETCH MAJOR STATE
AND PROCESSES THE DAC INSTRUCTION, SENDING TO MEMORY
TImOUGH THE MEMORY PROTECT LOGIC, THE ADDRESS AND
COMMAND (MWR,) FOLLOWED BY THE MREQ.

KM-12

THE COMMAND MWR: PHODE ENABLE (CHECK THE ADDRESS.)

KM13-14

THE ADDRESS ON MDL 1-9 + BOUNDARY REG 1-9 RESULTS IN
NO CARRY IMPLIES THIS ADDRESS IS VALID PROCESS THE
MEMORY CYCLE.
IF THE ADD RESULTS IN A CARRY, THIS
IMPLIES TRAP.

KP31

WRT.T~AP~MEM

TRap

MEllI TRAP: TRAP P A PULSE

•

lIONS.

KP26

TRAP P: ,

KP32

TRAP P:
AOR ACK"
TRAP PREVENTS CP WR ADR ACK FRCIt OCCURING. ADR ACK:
MREQ HOLDFF

MREQ

KP26

ADJt ACK: ~ HOLD MO

KP31

HEM TRAP*MREQ:

KP32

TRAP CLR MEMORY: END OF CP CYCLE

XP26

END OF CP CYCLE: ,CP ACTIVE

'- ~

TRAP CLR MEMORY

17-3

~ CP

TRAP CONDITION

TRAP INVALID ADDRESS
CPU TO MEMORY CONTROLFFARE NOW CLEARED.

(TS03*~1) *TRAP*FQRCE FETCH:

t INTRPT ACK

KP35

CLR KEYS

KP31

TRAP*TS03*~1:t TRAP ADDRESS EN IF P.I.E=O TRAP ADDRESS
EN: CAL ADDR EN THIS FORCES ADDRESS 20. IF P.I.E. IS
ENABLED GO TO LOCATION ZERO.

KPI9

TS03* INTRPT ACK: I/O ADDRESS TO "A" BUS
FETCH TS01

KP21

INTRPT ACK*TS03*~2*HS CLK:~ RUNFF.
CPU IN TS03, ~3.

KP20

TRAP*INTRPT ACK*TS03*CLK H: MS PWR CLR. WHICH CHANGES
THE CPU FROM THE FETCH MAJOR STATE TO THE EXECUTE
MAJOR STATE. SET FETCH ALSO GOES ACTIVE.

KP35

(SET FETCH*TS03*CLK H)* INTRPT ACK* CP ACTIVE:
ENABLE INTERRUPTS.

THIS HANGS THE

ENABLE INTERRUPT*TRAP: PI REQ

KP51

TlME4* PRIORITY CHECK OKAY:
PIFF
TIME 1 * PRIORITY CHECK OKAY: PI SYNCFF
PI SYNC:. P. I. E. FF
.

KP35

PI SYNC*TlME4: t INTERRUPT STROBE
INTRPT STB:
INTRPT STATE
INTRPT STB: ~ INTRPT ACK .

KP34

INTRPT STROBE * RUN : t START RUN

KP24

INTRPT STROBE: LD MO, OA

KP48

INTRPT STATE: INH DECODES

KP35

INTRPT ACK+INTRPT STATE: INH PC LOAD
THIS PREVENTS THE PC FROM INCREMENTING

KP31

INTRPT STATE + API STATE: • TRAPFF, J. PREFF, 1 UMFF
THIS TAKES THE SYSTEM OUT OF USER MODE AND ADDRESS 0
TAKES THE SYSTEM INTO MONITOR MODE

KP35

INTRPT STATE*TS01: INT. INH. SET MO.
INT. INH. SET MO: INTRPT CLR IR

FROM THIS POINT PROCESS AS IN PI
WRlTE-L,B,U, AND PC 3-17 INTO LOCATION 20 or ZERO.

17-4

t BLOCK DIAGRAM OF TRAP CONDITIONS
INSTRUCTION

FROM MEMORY
- ADR ACK

MOL~

SET
IR

FETCH

•

NEXM

LOl¥~IT

it-

BOUNDARY
REG

,It

(
.

DELAY

75 NS

JMP ..

DECODE

ISZ ..

--..
...

.....

ADDER
,~

CHECK
ADDRESS

BB-15

....30..

- ~~

~ ~
1004

:::

.- L

- - - - - - - - - ---

MREQ

~
~ 0
i
~ C)~
C,

~~---~

...:I

MEMORY

I ADDRESS

TRAP CONDITIONS CONTROL

MO REQ

CPU

•

17-5

'~.

t·

t.
. ::.....

--~--I

r·'&'-'-·-TR-A-.-.•f__J0. ".

~'''~EQ J.""

__- -I L _
I-NliOf
!.,.(;,.(....--1'","v
......_
_..-__

i.,:

. '.

C --_·--. . ----]
~,

I::

',".10

~---

IaEF'ICTON
_NI_IA'IQ.III.'

._ACK

.'.

... '.

NOT 1",,_.

.'"

'.{'"

' - - -....___J ..... :\

\L-__

'-_ _.....,..._ _..J ..m ','

,....--. . ---··.11

ti.
. ,'-,

~;;:
..'".,
. :.:/

'.:.~

,~ ','

FI.... 6-12 KM1' Memory Prot.ct Flow DIagram

17-6

. . . . . .11............. 3,

•

iet_

MEMORY RELOCATE - KM/K'1'

OBJECTIVES:
A)

LIST THE USE AND FUNCTIONS OF mE MEMORY RELOCATE
OPTION.

SHOWN THE BLOCK DIAGRAM, EXPLAIN THE C~ICATION
SIGNAL SEQUENCE AND DATA FLOW OF THE MEMORY PROTECT
OPtION.

E)Q>LAIN THE FORMAT AND USE OF THE MEMORY RELOCATE
onION.

LliT THE PROGRAMMING C~SIOERATIONS NECESSARY WHEN
USING THE MEMORY RELOCATE OPTIOi.

EXPALIN THE KT - MEMORY RELOCATE FIDW DIAGRAM.
STATING THE LOGICAL OPERATION OF A MEMORY RELOCATE
TRAP CAUSED BY
1) BOUNDARY VIOLATION
2) ILLEGAL INSTRUCTION
3) NON-EXISTANT MEMORY

•

,\.":

17-7

MEMORY PROTECT AND RELOCATE BLOCK DIAGRAM

- - - - - - CARRY L

UPPER LIMIT

~8
R ~--

[)_I

- - - - - - RA CARRY.:

t NEXM

(PREVENTS WRAP AROUND)
R

LOWER LIMIT

MOL-MDL
.... ~ _ _

MOL 1-9

MOLO, 10 THRU 17

BR-.

• ' - - - - - -.....

USER
PARTITION

MEMORY

RR+ADR 1-9

MONITOR

17-8

MDL1-9

c:;,;-;;--- ",~"
~

, ,"j
'..... ;'[f--;;""11'
'.
,""·Htl'r.
.

--.-

".,

f. .)".
.:'.:.

",:

--'

....

, :~ .

..........lTIlII4UI·T

1'1 ......

101.';"
',',..

"~'

TOPIC API

OBJECTIVES:
A)

EXPLAI~ ON A BLOCK DIAGRAM r..EVEL THE FUNCTIONAL
PARTS OF THE AUTOMATIC PRIORITY INTERRUPT OPTION.

LIST ON A BLOCK DIAGRAM LEVEL THE COMMUNICATION
SIGNAL SEQUENCE OF THE API OPTION.

STATE THE FUNCTIONS OF THE API. lOT INSTRUCTIONS.

STA"TE THE PROGRAMMING CONS I QEPTIONS NECESSARY

WHEN USING API.

18-1

•

. -., ,.... -. -.-. . . MI0 4 -'S IMP L f FI ED: .r·---i

"-~
·

H--------0------------i
Ha. - E": J\r
,~
,

EN OUT H .:

.,. 3V

't:!\ rL-..\.)
r-r A" (I)
H
O;'"\1/'"'\
"

-- --r-----·--·-i~. ~-.•

1/0 SY~'iC H

ENe

r---~<:

~ 1-:1"
.....' _ _ _t -_ __ _

•

~--

. ': I .

.. .
; ~

! •

.. .

-t3V

- :

~t ~.~~. ---~-i-;-~ ~
I'

__----------------------~----__ ! .

I .

i ..

(Pt

GRANT H_'----------+---~------4_----------~~--~

-·1.---

- --- t-

i .

i
· I

,,I .

.. "-"" .. . :. t .
· ;
·

DATA FLAG (0) L_'-----:...;:...-<...1
flO PV/R CLR H
170 SYNC

DATA FLAG'

I-

:.:::I.~ --.--.....---..I------~ : ~ -~ .
-----~---~-..
I

;

- I

r • .

j .
1 .'

.. t •.

.:I . ~
s

----~s ~------------~---

,.'

.~J_~-~_ __'.~j __ ~-~

ENe

ENA
Ei-:p

.. 1 : .

-.- .-.

tJ\

GRANT

... 3V .

REo...

V\)

i
•••
~--,----..

,i
.....- ._'-j-

API B#O£K DIAGRAa

yoGIC

CHANNEL 0

(52)

(57)

CHANNEL 1

SCAN INPUT

PL EN(O)H

API REQ

LINES

RP-15

(64)

TC-1S
(44)

DIS BRK (O}H
-TRAP
CHANNEL 2

...,

1--------.

(X)

PTR
NT

API SYNC

GIVE ME YOUR ADORES

(50)

~>------~....

API
STROBE

CHANNEL 3

REQ{l)
CLK OVFLO

(51)

LP-=-15
(56)

API

GIVE ME YOUR ADDRESS

USE M104 SLIDE 1ST

GRANT

MEMORY

M
A

R~.

~----------------------+--iE

I-'

(l)

I
~

~~
IR REG

FORCED XCT
XCT 64

400064

LOCATION 64

JMS TO SUBROlJI'INE FOR RP-lS

INSTRUCTION - 103000

3000

L,B,U, PC 3-17

(

(
\

DBR

JMP

* 3000

~ADDRESS

HARDtlARE WIRED FOR
SPECIFIC DEVICE

KP-35

KP 51

API FACILITY

I/O PRIORITY CHECK
API REQ L

INHIBIT PI
__
P_F.:..(5.;...;2;;..:)~';..;..AD~(..;;;.5..;..7",-'-....;C:;;.:HANN=::.;lE:.c:.:::,L~O_..... Tl REQ FROM DEVICE
•
CP API' REQ.... NO PRIV. INST. *SET FETCH*
RP15(64).TC-15{44)-cn_un~~ 1
T4*REQ*-PL
PTR ( 50) • VT' 'IS ( 54-(
2
TURN OFF SCAN
~
tt'S02*~3: INTRPT ACK
~
HAND CPU TS03*~3.
eLK ovflo(51),LP-15-CHANNEL3
GRANT-DEVICE
CLK H*CPAACT(O}H:
SFi,ND YOUR ADR.
lAP I
EN INTERRUPT
T4:
PLFFPREVENTS
EN INTRPT*APlREQ : APlREQ f - REQ
REQ FROM OTHER
API SYNC*T4:INTRPT.STB. LAPI SYNC
DEVICES ON THIS AN[
INTRPT. STB:
RUN
rLOWER CHANNELS
"'CPU TURNS ON •
GOES TO FETCH

1.OCH IN PROGRESS
2.CLK IN PROGRESS
3.IOTS IN PROGRESS
NO THEN
T4:"'t API FF

Tl:

t API SYNC

API

SYNC

I-'

a:>
I

( Tl

API REQ ON LINE

SCAN ON
LATCH REQFF (API FACILITY)

1 IT

2 IT

JT 4

IT 1 IT 2 IT 3

--1

------,
(SEND API REQ)

l
*~LAST CALL

APIFF

API SYNC

1,_ _ _ _ _-

GRANT

ENA (MI04)

SET PL FF

* INTRPT STB

SYSTEM POWER CONTROL
OBJECTIVES:
A)

TRACE THE ROUTE OF THW PWR OK BUS THROUGH THE
MAIN FRAME AND THE BACK DOOR RACK FROM THE
715 P.S.

EXPLAIN Hc.l A POWER FAIL G,f.NERATES AN INTERRUPT.

EXPLAIN THE DIFFEREltCE BE'lWEN -POWER OK L AND
POWER LOW.

EXPLAIN HOW CONSOLE LOCKED EFFECTS THE POWER
"FAIL SEQUENCE.

19-1

POWER UP

POWER DOWN

PROGRAM CONT.
UN T II.. POWIR

FAILURf
DETECTED

."',.\

WHEN PWR 1..0W
IS DETECTED

- - ' - - - - I A PI R!OUEST'

IS ISSUED

Ex£cuTt'
LOCATION
ZERO:- ,:,
(JMS SUBRQUTlHE)

TIME

sl~E

2 MS

ftEGISTERS

SUBROUTINE

STORES ACTIVE
REG. IN CORE AND

PLACES ,IMP RES"rART
~OUTINe:

IN LOC ()

1$· I) II.

19-2

POWER UP

CONSOLE LOCK

-~---"""'ON-

POWI" DOWN

. API ENA81t:D

WHi:N PWR LOW

~S DET[CT~O AN

A~I R£OUE'l'

IS91)£0

POWER FAIL IS
ON THE NIGHEST

LEVEL r# AP1
(LEVEL ZERO)

2 MS

POWER OFF

1,·01,?

19-3

+11

K2- (715 P.S.)
MEM PWR RELAY

-PWR OKL

K303
DELAY
7 50~ s

al.oL:3:5V'

K2 CONTACTS
SUPPLY-30V to
MEMORIES.

PWR ON H

PWR LOW

- PWR LOW DELAY H

K303

IN:
IN:

PCMER FAIL

H OUT IMMEDIATELLY NO DELAY

STAYS HIG! UNTIL THE DELAY TIMES OUT
THEN OUTPt1l' GOES L~

FAILURES IN THE REGULATORS, G821-G822-G823, DROP 'mE MEK>RY PWR RELAY
IMMEDIATELY TO POOTEcr THE MEMORY- "CAN'T SAVE ANY REG."
THE FAILURES IN THE REGULATORS ARE DETECTED BY THE SIGNAL PWR OK L.NDTE PWR FAILpp IS NOT SET.
G827 SAMPLES +11 V.
THIS IS 'mE VOLTAGE OFF THE CAPACITORS IN
715 PS.
IF THE + 11 VOLTS DROPS FOR ANY REASON, THE G827 GENERATES
A PWR LOW SIGNAL WHICH IMMEDIATELY SETS THE PWR FAIL FF •
SETS UP FOR INTERRUPT. TIME BEFORE THE MEMORY PWR RELAY
DROPS IS 25041 s THEREFOaE IT CAN BE SEEN IN THIS TIME CAN SAVE
A LOT OF REGISTERS.
IF CONSOLE LOCKED IS NOT ON PROCESS POWER OOWN AS IN CONSOLE
LOCKED POWER DOWN FLOW. HAVE TO USE MANUAL RESTART SEQUENCE.

19-4

POWER FAIL -

AUTOMATIC RESTART
ON PCMER DOWN THE LAST THING THAT HAPPENED WAS A
JMS TO START UP ROUTINE WAS ENTERED INTO LOCATION

ZERO.
KP-57

AUTO RESTARTpF

PWR

(C»i

LIS AFTER
PNR WAS OKAY

KP34

KP34,---r
RUN (0) H -

(+llV)

STAR'!' RUNFF ALLOWS CPU
FETCH MAJOR STATE

......_ . J

TO START IN
TSOI.

KP34
CONSOLE

LOCKED

- - -......_ J

SMR

KP48

KEY.ACT

="D-

FOacE FETCH

NOTHING IS ENABLED ON THE "An BUS AND THE "B" BUS: SUM BUS

INHIBIT
DECODES

= ZERO's

KP24

KEY ACTIVE*TSOl*CLJ( H: LD MO, OA THE ADDRESS OF ZERO IS LOADED
INTO THE Me AND OA REGISTER.
MEMORY CYCLE READS INTO THE CPU THE INSTRUCTION LOCATED AT LOCATION
ZERO (JMS TO START UP ROUTINE)

19-5

REAL TIME CLOCK
OBJECTIVES :

WRITE A PROGRAM UTILIZING THE REAL TIME CLOCK.

STATE HOW THE REAL TIME CLOC:K FACILITY IS SET UP.

LIS'!' nm SEQUENCE OP EVENTS THAT CAVSE A CLK PI.

20-1

•

MEJt

KD~4 "DSli- MOL

K p 32

r/o A DO R - MOL ----~~

KD04 STROBE DSR

ADD 1
K005 OSRt\)

o
I

t\)

KD04MDL-OSR

KPZ-17

MOL ~-17

KD04 VOADORESS-OSR
KP68 IloA 3-14
KOO3 VOAO 15-17

tlo 8US

....---

KD 04

CLK FACILITY

CLK SYNC:I/O CYCLE
REQ:
I/O M HOLD

LOCATION 7 LOADED
WITH A COUNT IN
2'. COMP. FORM

KP26
~,

KPS7

CLK SYNC*H.S.CLOCK
: . MPX THIS ALLOWS
TH$ PROCESSOR SW.
TO SET UP FeR
I/O TRANSnRS

t CLK EN

CLON:

~ +CLK FLAG
~~

KPS7

(CLK SW~NSOLE
!LOCKED) *CLK EN:
~N CLK RlQ

~,
r----.--.;;....

KD-04

I-

HOLD:

t WC ENA.

we * CA "" I/O M

KP-S7

EN CLl< RBQ *

,...-----

!'rICX OF 7HE eLK:
n eLK REQUEST"

KD-04

~L-DSR""I/O M

HOLD: I/O ADDR.
TO THE DSR

KP-51
~,

I/O PRIORITY
ICHBCKS GOOD

,----~-

~ACK-BACK: t

YES
~,

T4:
Tl:

KD-06

WC ENA* CT4*
STROBE ADDRESS

KP-Sl
CLKFF

"
~----:;-

KD-04

!STROBE ADDR:--~f--_"'"

~t"CLK SYNC

,
~,

STROBE DSR
(DSR=7) •
~ I/OM HOLD FF

KP-57

CU< SYNC:. eLK
rtmQUEST PF

KD-04

f?\

tI/O RD & I/O ~IRT~0
(R.P.W. CYCLE)

+
r======

~03

STROBE ADDR: ~
WC ENABLE

17 -+I/O BUS

r------&.-

WC ENABLE:
"WORD COUNT
CYCLE" :ADDI

KD 06
CLK SYNCs

"NO 3 CYCLE BREAK"

--------------~-

KD-04

.----'

~LK SYNC: ADDR

ENCA

20-3

KD04

I/O ADDR ACK:
I/O READ, WRITE FFS'

STROBE ADDR:
SET I/O M REQ

KD-04

KP26

I/O PROC. IS WAITING
FOR RD RST.

SET I/O M REQ:
I/O MREQFF

RD RST: MDL -+ DSR

yes

KD-03

CONTENTS OF
ADDER+ 1 TO THE
INPUTS OF THE DSR
"MPX* I/O , REQ*
tp ACTIVE: I/O
ACTlVEFF

CLK SYNC * WC OVLFO
: t FLAGFF
KD-06

KP26
I/O ACT*I/O
MREQ: I/O ADD-+
MDL (70N MOL)

I/O RD RST: 150NS
LATER (PAUSE)
PRE MRLS

KD-04

PRE MRLS:
I/O DATA ACK
(I/O DATA ACK
GOES TO MEMORY
AND RESETS
BUS EN. THIS
TAKES THE DATA
OFF THE MOL)

I/O RD*I/O ACT:
MRD
I/O WRT*I/O ACT:
MWR
"MEMORY DO A
READ PAUSE
WRITE"

KD-06

KP26
(I/O ENABLE*I/O
M REQ) * HS CLK:
M REQ

PRE MRLS:

+- MDL

START THE MEMORY CYCLE
20-4

SET DSR

__________~S~E~T DSR

KP26

... .

I/O AIl)R. ACK:
CLRREQ: ~
I/O M REQ (DROP
[AoDR. ON MDL)
k;LR REQ: •

;ET DSR .... MDL:
DSR-MDL

MDL
KD04

( INCREMENTED
CONTENTS OF DSR

IMREQ (INTURN

"lS ~SFERRED

......--+ 'flO THE MDL

IRESET ADDR A~)

KP.26

•

(I/O ACT*I/OM REQ)
*RD RSTs I/O
:aD RST. (THE
CONTENTS OF
LOCATION 7 ON

KD04,03

Sln' DSR-MDL:
STROBE DSR
(CONTENTS OF
~DDER LOADED
THE DSR)

THEMDL

INTO

(C' OF LOCATION 7
INCREMENTED BY 1

•

KP26

ttf SYNc* HS CLK

M PX
ALLOW CPU TO
CONTINUE AS SOON
AS I/O 1\CTIVEFF
GETS RESET

KD-06
SET DSR~MDL
DLEAYED 25NS:
RE~'i"ART

~,.

KP-51

RESTART* CLK SYNC:
• CLKFF

KP-2n

CLK SYNC

I/O MRLS: MRLS
(LOADS MB IN MEM.
ALSO ~ RD RST*
MRLS ACK:
I/O
ACTIVE

KD-06

SET DSR-MDL
DELAYED 75NS:
STROBE N.RLS

KD-04

MRLS ACK: ~
DSR-MDL, • I/O
DATA ACK, • I/O
MRLS

STROBE MRLS:

.....- - - -... I/O MRLS

START WRT CYCLE

~o-5

KP26

I/O MRLS ACK: ~
I/O ACTIVEFF

KP-26

I/O ACTlVE*MPX:
I/O INACTIVE

KP21

KP-21

AS SOON AS
CP ACTIVE GETS
SET* CLK OCCUR
STOP PHASE FF

CPU TIMING
IS
RUNNING

20-6

1('.1.'(.;

fLAG: OVFLO

-05

KP57

* AP I EN
(03) H: CLK PI

RTC FLAG*A~I(8)L

CLK FIAG

" t RQ "A"n

X'ni

FACILITY HANDLES

INTRPT.
"API ON" AND THE
API REQ DISJ\BLES
P-I_F_A_C_IL_I_T_Y_ _ _--.I

____ -..___

_DEA~

API FACILITY
PROCESSE.S THE
CLKM:Q
WAITING FOR
API 3 GRANT

RTC API BEQ A
API 03 GRANT:
RQ BFF

KA-06
RQ 8

* RQ SYNC

03: CLK ADDR
51
I/O A 12, 14, and
17 WILL SE ACTIVE

NOTE: CLK FLAG WI LL GET CLEA!(ED BY CLON + CLOF

20-7

RF 15-

3 CYCLE BReAK DEVICE
WC ADDRESS 36 (C) 36= TWO's COMP OF NUMBER OF WDS XFER
CA
37 (C) 37= LOAD INTO LOCATION 37 STARTING ADDRESS
MINUS O~.
API BREA~ ADDRESS - 63
SUGGESTED PRIORITY LEVEL 1
- SECTOR CONTAINS, 256, -18 BIT WDS

I~16. 4MS -:, I

18 BIT WD
PCH REQ * RD REQ : DEVICE XFER -l' MEMORY
DCH REQ * WRT REQ: MEMORY XFER ~ DEVICE
1.
2.
3.
TC 15

1 OP 2
10P4

SET UP
DCH XFERS / 1 WORD PER DCH REQUES'1'
JOB DONE OR ERROR - API OR PI
3 CYCLE B~K DEVICE

we lOCATION 30 (C) 30 = 2' s COMP. OF NO OF WDS XFER
CA LOCATION 31 (C) 31 = LOAD INTO LOCATION 31
STARTIWG ADDRESS MINUS ONE

AP I BREAl< ADDRESS 44
SUGGESTED PRIORITY LEVEL 1

t.-(- - - - 20Oms------aW'"----·· 20OmS _ _ _ _~~

' - - - XFER {18 BIT WD):.=/

1.
2.
3.

____----J~1
.-/

--------------------------------

SET UP
DCH XFERS / 1 WORD PER DCH REQUEST
JOB DONE OR ERROR - API OR PI

DCH REQ * RD REQ : DEVICE XFERTO MEMORY 10P2
DCH REQ * WRITE REQ: MEMORY XFER TO DEVICE 10P4

21-1

RP-15

SET UP

INSERT AND EXECUTE

INSERT 2'8 COMPL. OF NO OF WORDS
LOAD WORD COUNT REGISTER (18 BITS)

INSERT DISK ADDRESS
a) CYLINDER ADDRESS REGISTER
b) HEAD ADDRESS REGISTER
c) SECTOR ADDRESS REGISTER

(7 BITS)
(5 BITS)
(4 BITS)

INSERT INITIAL MEMORY ADDRESS LOAD CURRENT ADDRESS
REGISTER (17 BITS)

INSERT FUNCTION & GO
LOAD STATUS REGISTER "A"

(9 BITS)

21-2

RP15

CONTROLS UP TO 8 RP02 OR RP03 - DISK PACK

we SIZE - 36 BITS/WD
SECTOR CONTAINS

128, 36BIT WDS OR 256, 18 BIT WDS

HAS A WC REGISTER
HAS A CA REGISTER

1..

LOADED Dt1RIWG SE'tUP

USES SINGI..E CYCLE XFERS FOR ODD NUKBER OF XPERS
BACK TO BACK XFERS

FOR EVEN NUMBER OF XFERS

1~14.8ms4{

AP I BREAK ADDRESS 64

API LEVEL - SUGGESTED PRIORITY LEVEL 1

SET UP

DCH XFERS/

2 WDS -

(BACK~ BACK)

+
1
DCH REQ L

o
1

w.o

(SINGLE CYCLE)

SING CYL REQ L

FUNCTION
SINGLE CYCLE XFER OUT
SINGLE CYCLE XFER IN

1
1

IF SING CYL REQ L IS HELD ACTIVE AFTER GRANT
IS RESET,
FF
THIS IMPLI~S ANOTHER XFER IS CONING (BACK-+BACK)

21-3

MDL LINES

~
M

U
X

D
S
R

HARD WIRED ADDRESS
"30"

I/O ADDRESS LINES

D
D
E
R

DATA
FROM

DEVICE

ADD +1
I/O BUS

M
PRIORITY
CHECK
OKAY
A PI SYNC

DCHJ
lOP

M104

DCH RE
N
f-J

ENA

BACK-BACK(O H

GRANT

1~---------------------------------------J

R
A
N
T

BLOCK DIAGRAM OF DATA IN TRANSFER
3 CYCLE BREAK FROM THE DECK TAPE
DATA IN XFER.
':vORD COUNT CYCLE (WC)
2.:URRENT ADDRESS CYCLE (CA)
3 . Dll.TA CYCLE

ME'

KD~4 ·OS~- MOL

KP32 f/O AOOR-MOL

-----~~

Ko04 STROBE DSR

KC~" OSR OVERF-LOW

AOO 1

KD0s DSR-.h eus

KD04 MOL-DSR

KD04 VOAOO;:l.ESS-OSR

f
<PZ-17

-KP68 IloA 3~t4
KOO3 VOAO Is-rr

~!.D!... ~-!7

3 CYCLE BREAK

EXAMPLE:
DATA IN XFER FROM TC-15

WORD COUNT CYCLE
READ PAUSE WRITE
NEEDS A DCH REQUEST FROM THE DEVICE TO TRANSFER THE DATA
INTO MEMORY.
NEEDS ADDRESS FROM DEVICE 30 FROM TC-15

NEEDS COMMAND
I/O PROCESSOR GENERATES I/O READ*I/O WRT
THIS SETS MEMORY CONTROL TO SET UP FOR A READ-PAUSE WRITE
NEEDS MREQ
THIS LOADS THE ADDRESS IN MEMORY AND STARTS THE MEMORY
CYCLE.
NEEDS STOP THE CPU WHILE PROCESSING THE DEVICES DATA XFER.
CPU IS HUNG UP BY STOP PHASES
CPU DECODES INSTRUCTION IT IS GOING TO PROCESS AND
SMW: CPU HANGS IN TS02*~2
SMR: CPU HANGS IN TS03*~2
WORD COUNT MEMORY CYCLE CONTENTS OF LOCATION 30 INCREMENTED BY 1
WRITTEN BACK INTO LOCATION 30.

21-6

ec)

LOCATION 30 = 777523 = THE TWO' 5 COMPLEMENT OF 256 WDS.
BLOCK OF DATA TO BE XFERED.

ONE

777523 IS ON THE MDL
RD RST: MDL -.. DSR
ADD+l IS ALSO ACTIVE OUTPUT OF THE ADDER IS
777524
RD RST:

PRE MRLS:

DELAY 150NS (PAUSE) AND GENERATE PRE MRLS AND SET
DSR-MDL

I/O DATA ACK:
DATA ACK: ~ BUS EN
BUS EN RESET TAKES 777523 OFF THE MDL.

SET DSR-MDL:
DSR-MDL ALLOWS (C) OF DSR ___ MDL
: STROBE DSR 777524 IS CLOCKED INTO THE
DSR AND XFERED ONTO THE MOL.
(SET DSR-MDL* WC)*EN CA:
CA
STROBE DSR: CHECK THE ADDER FOR OVERFLOW. IF
OVERFLCM IS PRESENT THIS IMPLIES
256 WORDS HAVE BEEN TRANSFERED.
SEND OVFLO BACK TO DEVICE WHICH
TERMINATES BY RAISING A JOB
DONE FLAG.

SET DSR-MOL DELAYED

75NS: STROBE MRLS

STROBE MRLS:
I/O MRLS : MRLS
: MB LOAD
MB = 777524
I/O MRLS: WC
DELAY OF SONS: MRLS ACK:
RD RST AND START
THE WRITE TIMING IN MEMORY

MRLS ACK : (, I/O DATA ACK,

~ I/O MRLS,

+DSR-MDL,

+I/O ACTIVE

I/OMRLS: • MRLS ACK
MEMORY WRITE CYCLE FINISHES & DROPS MBSY

21-7

CURRENT ADDRESS CYCLE

(CA)

THE STARTING LOCATION TO STORE THE DATA WORD WILL BE LOCATION 500.
THEREFORE, THE PROGRAMMER PLACES IN LOCATION 31,000477.
STARTING ADDRESS MINUS ONE
2.

CA CYCLE
READ PAUSE WRITE
NEEDS ADDRESS 30 FROM DEVICE TO BE STILL ON THE LINE.
NEEDS ADD+1 ACTIVE WHICH IT STILL IS
NEEDS COMMAND
I/O PROCESSOR GENERATES I/O READ*I/O WRITE
THIS SETS MEMORY CONTROL TO SET UP FOR A READ,
PAUSE, YJRITE.
NEEDS MREQ
THIS LOADS THE ADDRESS IN MEMORY AND STARTS THE MEMORY
CYCLE.
NEEDS - CPU STILL HUNG UP BY STOP PHASES

CURRENT ADDRESS CYCLE
CONTENTS OF LOCATION 31 INCREMENTED BY 1
WRITTEN BACK INTO LOCATION 31
000477+1 = 000500 NOW UPDATED CONTENTS OF LOCATION
31 ALSO 000500 IS STILL STORED IN THE DSR. DSR CONTAINS
THE ADDRESS WHERE THE DATA WILL BE STORED.

21-8

(C)

LOCATION 31

= 000477

0004 77 IS ON THE MDL

RD RST:

MDL-DSR

ADD+l IS ACTIVE OUTPUY OF THE ADDER IS

000500

RD RST:

DELAY 150 NS
DSR-MDL

PRE MRLS:

(PAUSE) AND GENERATE PREMRLS AND SET

t I/O DATA ACK,: t DATA ACK: .. BUS EN
BUS EN RESET TAKES 000477 OFF THE MOL LINES

SET DSR-MDL:
SET DSR-MDL:

t DSR-MDL THIS ALLOWS (C) OF DSR-MDL
STROBE DSR 000500 IS CLOCKED INTO THE DSR
AND XFERED ONTO THE MDL

SET DSR-MDL

DELAYED

75 NS:

STROBE MRLS

STROBE MRLS:

t I/O MRLS, t MRLS : MB LOAD
MB :::: 000500
IOMRLS *DATA CYCLE:

WC*CA

.t. CA

ADD+l

MRLS DELAYED 50 NS: 'MRLS ACK :
IN MEMORY.
MRLS ACK: ~I/O DATA ACK,

oJ, RD RST AND START THE WRITE TIMING

I/O MRLS, ~DSR-MDL,

I/O MRLS: • MRLS ACK

MEMORY WRrTE CYCLE FINISHES AND DROPS MBSY

21-9

+1/0 ACTIVE

DATA CYCLE:

SETTING ur FOR TIlE DATA CYCLE $'l'AR'l'S DURIN'; 'rlJE we CYt' LI':. 'PHI'; '('1M}':
AS FAR AS A MEMORY IS CONCERNED IS ABOOT MHEQ 'rIME (TAIL END). MORE
SPECIFIC TIME IS THE I/O TIME
Tl: IF WC*ENCA*DATA IN*
DATA OUT:
ENB
THE DEVICE RECEIVES AN I/O SYNC PULSE (T1) WHICH SETS ENB IN THE M104.
AS A RESULT THE DEVICE SENDS RD REQ BACK TO THE I/O PROCESSOR.

T4:

t DATA IN, t IN XFER CYCLE, DCH EN 10P2, THIS OCCURS BEFORE
RD RST A SIGNAL FROM MEMORY.

T1:

10P2

SET DSR-MDL ~

75
NS

WC CYCLE

CA CYCLE

1L.

T4 _.;:;;.S..;.T;;.;;RO,;;.B;;;;.;E;;;,-.1.;...0~P_2 _ _ _ _ _ _ _

A SHORT TIME AFTER

THE I/O ADDRESS I~S BEEN RECEIVED STROB 10P2 GATES THE DATA
OFF THE BUS INTO THE I/O BUFFER.

CA * PRE MRLS :
NOTE:

t DATA CYCLE

THE UPDATED CURRENT ADDRESS WILL BE TRANSFERRED FROM
THE DSR-+MB 000477+1 ..... DSR = 000500~MDL~MB
,DSR = 500 THE STARTING ADDRESS

WC CYCLE

1/0 MRLS*DATA CYCLE

-------,I.t
/
CA CYCLE
L:......
PRE MRLS~

I DATA CYCLE
DCB DONE

21-10

DATA CYCLE

* I/O MRLS ACK: t I/O MREQ

(DATA CYCLE

* I/O MREQ) * DATA IN): t I/O WRITE

DSR CONTAINS 500

DATA CYCLE * I/O MRLS ACK:
I/O MREQ
NEXT HS CLK: 1 I/O ACTIVE
I/O ACTIVE * I/O MREQ: I/O ADDR-MDL
NEXT HS CLK: MREQ
LOADS 500 INTO MA & STARTS THE MEMORY CYCLE

(ADD-MEM * DATA CYCLE * DATA IN)

I/O ADDR ACK:
RETURN DATA
.
RETURN DATA: fDSR-MDL:
STROBE DSR
DSR CONTAINS A DATA WORD.
ALSO SET DCH DONE
SET DSR-MDL =
DSR-MDL
MDL=DATA
SET DSR-MDL DELAYED 75 NS : STROBE MRLS

STROBE ~:

t I/O MRLS: MRI.S: LD MB

50 NS LATER : ~ MRLS ACK, J, RD RST
ALSO START THE WRITE PORTION OF A MEMORY CYCLE

MRLS ACK. I/O DATA ACK, J, I/O MRLS, J, DSR-MDL
MRLS

+: '" MRLS ACK

MEMORY WRITE CYCLE FINISHES AND DROPS MBSY.

21-11

RESTARTING

CPU

(ADD-MEM * DATA CYCLE * DATA IN)
RETURN DATA

* I/O ADDR ACK:

RETURN-DATA * BACK TO BACK: DCH DONE
DCH DONE : J, DCHF F '

J, DCH SYNCFF

THE NEXT TICK OF THE HS CLK : 1 MPX
WHEN I/O MRLS ACK, COMES BACK FROM THE DATA
MEMORY CYCLE, IT ~ I/O ACTIVE
MPX * I/O ACTIVE 0: I/O INACTIVE
I/O INACTIVE : AS SOON AS CP ACTIVE IS SET AND THE NEXT
TICK OF THE HS CLK:'t STOP PHASE
THE NEXT TICK OF THE HS eLK CHANGES PHASE THE CPU IS NOW RUNNING.

21-12

"
"

?Cljcle DCH IN
Timing DiClsra.m, bll2/il

:
I

SINGLE - CYCLE BLOCK TRANSFER
CPU
PROGRAM INITIATES
WORD COUNT (WC) &
CURRENT ADDRESS
(CA) THEN ENABLES
THE DEVICE

DEVICE
DEVICE POST A
SINGLE CYCLE
REQUEST WHEN
READY

I/O PROCESSOR
DATA CHANNEL
GRANT IS ISSUED
WHEN I/O PROCESSOR IS READY

DEVICE SUPPLIES
CURRENT ADDRESS
AND DATA TO 1/0
BUS THEN
INCREMTS ITS
WORD COUNT AND
CURRENT ADDRESS

REQUEST
MEMORY AND
SUPPLIES CURRENT
ADDRESS AND
DATA IN
SEQUENCE

STOP NEXT REQUEST
IF WORD COUNT
OVERFLOWS

YES

JOB DONE
NOTIFY CPU

21-14

CENTRAL PROCESSOR
IPROGRAM INITIALIZES
IWORD COUNT AND
CUMENT ADDRESS
Il.OCATtON

pROGRAM INITIALIZES
a STARTS DEVICE
WITH INSTMJCTIONS

WHEN OEvtC£ HAS
DATA A[AOY 0"
' - - - - - -..... N£tDS DATA A A£-M--·--------~I
110 PROCESSOR
QUEST tS PLAttD
ON THE 110 BUS
WHEN THE 110 PROCaSOR IS READY A
GRANT IS ISSUED
TO REQUESTING
DEVICE

THE DEVICE
SUPPLIES TM( ADO" ' - - - - - -...... ft£SS OF THE .".0
COUNT,CURRENT
AOORESS PltR

J
!QEVICE CLEIIRS ITS
THE 110 PROCESSOR
IF WORD COUNT
ENABLE AFTl!R
FETCHES.INCRE OVERFLOW, THEN ~I--_...... CURRENT WORO
tMlNTS, a REPLACES t - - -.. OVERFL.OW IS SfHT
HAS BEEN
THE WORD COUNT
TO DEVICE
TR~ERR£O

THE 110 PROCESSOR
FETCHES, INCREMENTS,
a RESTORES THE
CURRENT ADDRESS

THE I/O PROCESSOR
TAKES DATA FROM
DEVICE AND
STORES IT IN
MEMORY LOCATION
SPECIFIED BY CA

-----<
NO

r--

•

SET A PROGRAM
INTERRUPT TO
INDICATE DONE

IS
DEVICE
ST1LL. ENA81.£0

1
YES
-~---

PROGRAM INTERRUPTED a NOTIFIED
THAT DEVICE IS
DONE

Figure 5-2

Mu~ticycle In Block Transfer, Flowchart

21-15

~ENTRAL PROCESSOR

IHITIA~IZEJ'S

GRAM
At) COUNT AND
CURRENT ADDRESS
LOCATION

PROGRAM INITIALIZES
a STARTS DEVICE
WITH INSTRUCTIONS

---

I
110 PROCESSOR
WHEN THE 1/0 PROCESSOR IS READY A
GRANT IS ISSUED
TO REOUESTING
DEVICE

I
!

~
110 PROCESSOR
FETCHES, INCRE -

MENTS, a REPlACES
THF. WORD COUNT

WHEN DEVICE HAS
DATA READY OR
NEEDS DATA A REQUEST IS PLACED
ON THE I/O BUS

THE DEVICE
SUPPLIES THE AOORESS OF THE WORD
COUNT,CURRENT
ADDRESS PAIR

-~
IF WORD COUNT
OVERFLOW, THEN A)4
OVI~RFLOW IS SENT
TO DEVICE

DEVICE CLEARS ITS
ENABLE AFTER
CURRENT WORD
HAS BEEN
TRANSFERRED

THE: 110 PROCESSOR
FElCHES,lNCREMENTS,
a RESTORES THE
MRENT ADDRESS

~
THE I/O PROCESSOR
FETCHES OATA
SPECIFIED BY THE CA,
PLA CES IT ON THE
9Uf

!
THE' DEVICE STROBES
THE DATA INTO ITS
REGISTER

C
SET A PROGRAM
INTERRUPT TO
INDICATE DONE

IS
DEVICE
STILL ENABLED

1
YES

PR')GAAM I NTERRUPTEO a NOTIFIED
THAT DEVICE IS
DONE
15 ·0004

Figure 5-1

Multicycle Out Block Transfer, Flowchart

...~

21-16

POp-IS MEMORY
&

(COMMON MEMORY)

MX-1S B
MEMORY
MULTIPLEXOR

UNIBUS

I
8K

LOCAL MEM

PDP-IS
CPU

11/05
CPU

INTERRUPT
LINK

BASIC BLOCK DIAGRAM

PDP-IS I/O BUS

BLOCK DIAGRPM OF MEMORY CONTROL

MEMORY
CONTROL

15 MEMORY
(MM-lS)

-'--

t ~

PDP-lS/76

io--

-_ ..

,
ADDR.
MODIFICATION

PDP-IS
CONTROL

MX 15-B

PDP 11/05
CONTROL

4~·

Cl
C;F.T ,P,f'TOF

t - -_ _ _

MOL

1"--__

t - -_ _ _ _ _ _

MCL
PDP-II/OS

~~ UNIBUS

MX15B

MEMOR

~EST

CONTROL

15 M REQ _-..,._.,..
15 REQ (0) H
ENA REQ (1) H
•

---=i

PDP 15 MREQ

11 CYCLE
ENAB REQ
DATIP

o NS

(0) H
(1) H
(0) H -___

ENA·REQ (1) L
DCH ACT

(0)

H -----,

......

MSYNC - - - - - - DC LO (H)

1
ENA

REQ
ADR ACK (l)B L

M REQ
STROBE

15 M REQ

--~-+~ c

11__________________~~~~--~~~--------------------------------

REQ
D

0t--_---,

11 MSYNC--.......--tC

1
-15 TIME OUT

11
REQ

PDP-II MREQ

0
+3

MRLS ACK

ADD-BUS

MSYN L

TIME OUT ( I ) H

PDP-IS

ADDRESS
MRD

M REQ

CP TO MEMORY

-- ~~-I

ENAB 15 CYCLE

...

..- --

- - -I

ADR ACK

ADDRESS

1-----

MRD

....
....

t-· --

ACK HOLD

YlD

t MEM-CPpp

Ct+-

15 REQ--.JD

t 15 CYCLEpF

.-.. RD RST

....

~.-- -

--- - -I

15 CYCI.E

.--q

ENA 15 CYCLE

MRLS ACK
MRLS

.-"'0.

RD CON
START MEMORY
TIMING

ADR ACK
r--

..,.. ~ ADR ACK

.. REQ ACTIVE

15 CYCLE

--.'

I
J LD MA

. NEW? ~
ENA REQ(MEMORY eYCI

l-- -

- - -I MEMORY TO CP

DATA

MRLS

...,

J---:MREQ

DATA ACK
.. MRLS * ~ DATA ACK

............ --.

-115 REQ * REQ ACTIVE

1-1
END OF CP CYCLE
tMRLS
, DATA ACK

15 MEMORY

... ---~t

ID MI

OPERATION

MXI5-B

CPU

O-MREQ *
DROP ADDRESS OFF MDL.

READ

t--1- --

CONTROL-CP TO MEM

- -I

15 CYCLE

-- ---e=

I!) CYCLE

DATA
r-

MRLS

1---J- -

........

J- - ~ONV

RST

:-'"'

DATA ACK

Loa

ACK
.., * t• MRL
RD RST

.......,

•

BUS EN

MRLS ACK
MRLS

...

• MRLS ACK

PDP-15

WRITE

OPERATION

\
CPU

MX 15 B
ADDRESS

ADR ACK*TRAP*TS02*
~3*START WRT*
CPACT : CP WRT ADR ACK

t..

-- ---I
.....

MREQ

!' - . ~-I

ADR ACK

J
I

L-..{C

3- lIONS LATER
GENERATE
MRLS
*
DATA ACK

DATA

MRLS

DATA ACK

MRLS ACK

MR'LS

- ---t

-..a.

.....

---1

-q

ADDRESS

1--- -

MWR

15 REQ * REQ ACTIVE

1----

MREQ

1--

ACK HOLD

t MEMORY TO CP

tENA REQI

_ _ loot.

ADR

..
-

--.

LD MA
tWR CON
START MEMORY
TIMING

ACK

I"'"'

M. REQ

10 t 15 CYCLEFF

MRLS

1- - --

CP ..... MEMORY

-- --I ENA 15 CYCLE

MWR

CP WRT ADR ACK :
I- ~ MREQ
2LD MO WITH
DATA

15 MEMORY

je-

.....

• ADR ACK

J.-

NEW ?CYCLE)

• REQ ACT
CP TO MEMORY

1- - --

DATA

15 CYCLE

)----

MRLS

--.

ENA 15 CYCLE

1----

DATA AC

....

CONTROL CP TO MEMORY

~50 J~

---I 15 CYCLE
L t 12~ CYCLE

ENABLE MB

LDMB & START
WRITING PROC ESS
MRLS ACK
• BUS EN

MRLS ACK

-- ~------------~~ ----

15 CYCLE

....
~

MRLS

--.

~ MRLS ACK

ADDRESS MODIFICATION

MXIS-B

THE ADDRESS CONSIDERATIONS ARE AS FOLLOWS;
1.

PDP-II ADDRESS BITS ARE
BUS A17 rHRU BUS A~
BUS A17 IS THE MSD
BUS Afl1 I S THE LSD
BUS Afl1 IS NOT USED FOR ADDRESS DECODE.
PDP-IS ADDRESS BITS ARE AS FOLLOWS;
MDL fl1fl1 THRU MDL 17
MDL fl1fl1 IS NEVER USED FOR ADDRESS DECODING

PDP 11 ADDRESSES ARE INCREMENTED BY 2.
PDP-IS ADDRESSES ARE INCREMENTED BY 1

PDP 11 CAN ADDRESS PDP-IS MEMORY THE SECTION OF
MEMORY THE PDP 11
CAN ADDRESS IS CALLED COMMON MEMORY.

PDP 11 SYSTEM ASSSUMES ANY ADDRESS ABOVE
I24K AS I/O ADDRESS.

PDP-II LOCAL MEMORY CAN BE 8K, 12K, 16K.

PDP-II ADDRESS 28K
AMOUNT OF CORE ADDRESSES
AMOUNT OF LOCAL CORE ADDRESSES
PDP-II CAN ADDRESS 20K OF COMMON MEMORY.

22-6

28K
8K
20K

PDP 11 ADDRESS 160 000 CAUSES
THIS ADDRESS TO BE MODIFY
IN THE PDP-II IF BITS 13, 14, and 15 are l's
JAM BITS 16 AND 17 TO A ONE.
ADDRESS 160 000 NOW BECCJt1ES ADDRESS
760 000 WHICH IS THE START OF I/O ADDRESSES.
PDP-II CAN ONLY ADDRESS COMMON MEMORY AND LOCAL MEMORY.
UNIBUS DEV.ICES CAN ADDRESS LOCAL MEMORY AND POP-IS MEMORY
LOCA~IONS UP TO 757776 WHICH' IS BLOCK 3 PAGE 4.

QUESTION:
IS THE PDP-II ADDREsS THAT WILL ADDRESS
LOCATION 50 IN COMMON MEMORY ?

WHAT

ANSWER:

15 ADDRESS X2 + LOCAL MEMORY SIZE = PDP-II ADDRESS
50 x 2 + 40000 =
120 + 40000 = 40120

PDP 11 ADDR = PDP 15 ADDR
40120
= 000050

11 ADDRESS RANGE -------+)

~------- PDP

210

000100000001010

000

(401208)

UNIBUS
ADDR.
40120

MX15-B
MODIFY ADDRESS
&

SHIFT
GENERATE MSYNC

* MSYNC BEING GENERATED:
o
o

9 10 11

13 14

ADDRESS IS COMMON MEMORY.
15 16 17

00000000

0 I

o 0

PDP-IS ADDRESS RANGE

MDL
ADDR
000050

PDP-IS ADDR X 2 + LOCAL MEMORY
SIZE = PDP-II ADDRESS

(COMMON MEMORY)

PDP-IS MEMORY

22-8

MX 15-B

:r::

:I:

ADDRESS MODIFICATION
ADDRESS IN 40120

G740
BO
2

Bl
B2
B3
M164 - ADDER

27:

JMPER E~ TO PIN 4

OUTPUTS OF G740
BO THRU B3 H
B4 L
THIS CONFIGURATION
IS FOR 8K OF
LOCAL MEMORY

BUS MSYNC
CARRY OUT H
PWR-OK L

ADD
TO
BUS
--~~--~~--~~~

MDL-O~

02,. ~3,

04..

12 13 14 15 16 17

0_:.~ 06,07

~---v--~

ADDRESS
OUT

TO MA

22-9

SHIFT
LOGIC

-11

15
1

"
\ \'-----1~~

BLOCK 3
128K

37
36
35
34
33
32
31
30

-11
UPPER

760000

WINDOW
SETTING

760000
740000
72
70
66
64
62
60

740000
72
70
66
64
62

BLOCK 2

96K

BLOCK 1
64K

BLOCK ~
32K

25
24
23
22
21
21

17
16
15
14
13
12
11
10

56
54
52
50
46
44
42
40

36
34
32
30
, 26
24
22
200000

07
06
05
04
03
02
01
00

128K - 15

128K

56
54
52
50
46
44
42
40

36
34
32
30
26
24
22
200000

160000
140000
120000
100000
060000
040000

- 37776

160000

140000
120000
100000
060000

- 57776

96K

I/O
RANGE

t
~

64K

140000
120000
100000
~

- 77776
-11 CPU

8K -11

RANGE

12K
22-10

-11
16K -11

TO Mf::MORV

MX15B

PDP-II

PDP-IS

CONTROL

MDL LINES

UNIBUS __~----~~--J
POP

11/05

- -

CPU &
IOPU

'-PDP 15
I/O BUS

EXPANDED INTERRUPT LINK

22-11

BUS REQUEST

...

BR 7
BG 7

PDP-11/0S

...

SACK

,..

BBSY
INTRPT
VECTOR (310)

row

3 .....
5

DR 11C
#1
O-BBSY
O-INTRPT
O-VECTOR
4l

SLAVE SYNC

DEVICE ASSERTS BR

I (1) GRANTED AT END OF INSTRUCTION

( 2) CPU ASSERTS ~
BUS GRANT

PRIORITY ARBITRATION WITH PSW
AND OTHER BRS
(BR 7-THRU BR4)

ASSERTS SACK
.... (3) DEVICE
DROP BR
REQ

CPU DROPS ....
BBSY & GRANT

(4)

(5)

(6)

DEVICE ASSERTS BBSY
DROPS SACK BRINGS UP
VECTOR ADDRESS AND INTRPT

?
CPU RECE IVES
VECTOR * INTRPT
PROCESSES INTRPT
IF PRIORITY IS
HIGH ENOUGH GO TO ROUTINE
THAT WILL READ IN
TCBP LOCATED IN
ADDR 767764.

SSYNC

22-12

0---+ BBSY
O--+INTRPT
0---' VECTOR

DR 1SC

BLOCK DIAGRAM
GENERATION OF A BUS REQUEST

L10R "'~L-...;.:TC~B~P:..-....1

11 C

* ~
* INTRPT ENA A

REQ A-

BR 7
.... UNIBUS

0 .... SACK

UNIBUS
SACK

B BSY

~*~ ~

__-.__ BBSY

"DR 11 C ASSERTS BBSY"

VECTOR=310

DRl1C#1
UNIBUS

O-+BBSY

SSYNC

0-+ VECTO-IIIII---------

·04INTRPl'

22-13

UNIBUS

DATA IN TRANSFER
GET THE TASK CONTROL BLOCK ADDRESS

767764 (ADDR)
PDP

co*el~DATAI

(()*())

DR lIe
#1

MSYNC

11/05

...

--.

DATA (C) OF INPUT G}\TES

S SYNC

PDP 11/05 READS' CONTENTS OF THE INPUT GATES
WHICH CONTAINS THE CONTENTS OF THE TASK
CONTROL BLOCK POINTER REGISTER IN THE DR-15C.

AC
TCBP

IN
BUS

READ INPUT
BUFFER

LI0R

DATA
CONTROL
A02
AOI

DArrA
XMITTED

:....J

el CO AO

A02 AOI

SELECT

J t

MYSNC

DRl1e #1 IS
SELECTED

ADDRESS
DECODER

UNIBUS
ADDRESS OF
TASK CONTROL
BLOCK

* READ IN LINES

A17 THRU A3

READS CONTENTS OF INPUT GATES
TO THE UNIBUS

READ IN LINE : DATA TRANSMITTED
DATA TRANSMITTED: tTRANSFER REQ IN DR15C
, DONE FF

22-14

DATA CONTROL CHART

DATA

IN
DATA IN
PAUSE
DATA
OOT

DATA OUT
BYTE

1
i

CONTROL

IN
IN

OUT

OUT LOW

OUT HIGH

22-15

OUT LOW
HIGH

HIGH

PDP-II

GENERATES

API

(JOB DONE)

REQ

TASK CONTROL BLOCK POINTER - . TO WORD ZERO OF THE BLOCK
LOW BYTE

HIGH BYTE
WORD ZERO

API PRIORITY
LEVEL 0,1,2,3

API
ADDRESS

WORD ONE

FUNCTION

WORD TWO

REQUEST EVENT VARIABLE

WORD THREE

WORD ZERO
WORD ONE

THRU 3=N

TASK CODE

DEPEND UPON PARTICULAR TASK

HIGH BYTE

LOW BYTE

001

200

FUNCTION:
INTERRUPT WHEN
JOB DONE

TASK CODE
RK 05

API LEVEL ONE ADDRESS IS ASSOCIATED WITH DR llC #1
OUTPUT BUFFER, WHOSE ADDRESS IS 767773, HIGH BYTE.

API
API
API
API

LEVEL ZERO
LEVEL ONE
LEVEL TWO
LEVEL THREE

DR llC HI LOW BYTE
DR llC#l HIGH BYTE
DR llC#O LOW BYTE
DR llC#O HIGH BYTE

OUTPUT BUFFER ADDRESS
767762
767763
767772
767773

DATO B

CI*CO

(DATOB)
HY'I'F

T -BYTE

I API ADDR Ii

ZERO I

PDP-II/OS

DATA

767763

ADDRESS

..
...

MSYNC
SSYNC

DR 11C#1

PURPOSE:

LOAD THE DATA OUT BUFFER HIGH BYTE
WITH THE API ADDRESS.
GENERATE API REQ ON CHANNEL ONE.
THIS GOES THRU THE API FUNCTION
WHICH WILL SEND BACK A GRAN'!' BY
WAY OF THE I/O BUS

CPU
40

I I MO

. l-LD
M6

API FACILITY

IR,
:
FORCE XCT :

I/O BUS
I/O ADDR LINES

DR ISC

"API IS ENABLED"
NEW DATA ROY H:
tAPI "I"PLAG:API"I"START

GRANT COMES BACK
ENA : SEND OUT 'I'HE
ADDRESS ON THE I/O BUS
I/O ADDR 11 THRU
I/O ADDR 17.

DRIIC#1
LOAD
ODB

~H.BYTEIL.BYTEJ
j~

THIS ADDRESS GOES
TO CPU (MO REG)
AND HARDWARE

WISE FORCE XCT.
UNIBUS
TH.l S MEANS f\S SOON A~ THE CPU ~~NTER~ THE l"E'rCfI

MAJOR STATE AND WORKS ON THE OPERAND XCT 200
ec) 200 = JMS TO SUBROUTINE TO HANDLE
THE JOB DONE INTERRUPT.

22-17

DATA OB
JOB DONE

(API REQUEST)

DR lSC
DRllC~l

NEW DATA
READY HIGH H

API 1
FLAG (1) H

OUT HIGH
DATA BUFFER-HI BYTE

SELECT 2

-API ENABLE

tv
tv

M 104

ENA
SELECT 0

I
I-'
00

API
ADDRESS

GRANT

A
~

______________~ T

I/O BUS

E
S

~------~

(0)

~-----+---I

MSYNC

ADDRESS DECODER

(2) API 1 REQUEST

A17
767763

ADDRESS
DATOB Cl

THRU

(1)

BYTE MODIFICATION IN COMMON MEMORY

DATIP
(C) OF MEMORY
LOCATION

UNI BUS

LOWER
BYTE

UPPER
BYTE
2 THRU 9

BYTE

10 THRU 17

A 00 H

BUS AOOL

_ _ A 00 L

UNIBUS BITS 017 - 08
(DOESN'T USE BITS
017 & 016 WHEN POP-II
CPU ACCESSES COMMON
MEMORY.

LOW

HIGH

UNIBUS BITS 07 - DO

I-'

SAME
MEMORY LOCATION
AS ABOVE.
RESULT MODIFIED
THE LOWER BYTE
AS A RESULT
OF THE PDP 11-05 ISSUING A "DATAOB"

HIGH BYTE
LOW BYTE

TO
MDLL

I\.J
I\.J

AOO = 1
AO
o

MOL - UNIBUS

REG.

AOO L HIGH BYTE
TO
~
MDLL

BUS LEVEL

CONTROL

MDL LINES

MC.DIFY IDW BYTE
ADDRESS BIT AOO=O : THE BUS LEVEL IS
HIGH THERE FOR GATE HI BYTE TO MDL *
LOW DATA TO MOL H

LOW

DATA~

TO
MDL H

DATIP

•

COMMON
MEMORY

-.-

MEMORY HANGS

PDP 11-05

ADDRESS
CO * Cl

DO A DATIP

MSYNC

DATIP CYCLE. )

(CPU ONLY ONE WHO USED

DATA

SSYNC
,

SSYNC

NOTE:

....

.-----.

MSYNC

DATIP ALWAYS FOLLOWED BY A DATO OR DATOs

DATOB
COMMON
MEMORY
N

I
N

~ MSYNC

PDP 11-05

l\DDRESS (SAME AS ABOVE)

RELEASE MEMORY WRITE DATA IN
CORE.
~ SSYNC

* Cl

DO A DATOB

MSYNC
DATA
SSYNC

MSYNC

.. , MSYNC

PDP 11-05

HAS DATA

XVM HARDWARE

be supplied at a later date.

23-1