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DEC-15-H3GB-D
October 1971
208 pages
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RP15
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DEC-15-H3GB-D
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208
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http://bitsavers.org/pdf/dec/pdp15/hardware/DEC-15-H3GB-D_RP15_Oct71.pdf
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Digital Equipment Corporation Maynard, Massachusetts PDP,·15 Systems Maintenance Manual Volume 1 RP15 Disk Pack Control DEC-lS-H3GB-D PDP-15 SYSTEMS RP15 DISK PACK CONTROL MAINTENANCE MANUAL VOLUME 1 DIGITAL EQUIPMENT CORPORATION • MAYNARD, MASSACHUSETTS First Printing January 1971 2nd Printing {rev} October 1971 Copyright © 1971 by Digital Equipment Corporation The material in this manual is for informational purposes and is subject to change without notice. The following are trademarks of Digital Equipment Corporation, Maynard, Massachusetts: DEC FLIP CHIP DIGITAL PDP FOCAL COMPUTER LAB CONTENTS Page CHAPTER 1 SYSTEM DESCRIPTION 1.1 General 1-1 1.2 RP15 Control 1-1 1.3 Disk System Characteristics 1-1 1.3. 1 Disk vs Drum 1-3 1.3.2 Disk Pack Effects on the Drive 1-3 1.4 RP02 System Characteristics 1-3 1.4. 1 RP02P Disk Pack 1-3 1.4.2 RP02 Disk Pack Drive 1-4 1.5 PDP-15 Computer System Characteristics 1-8 1.6 Single-Cycle Interface and I/O Bus 1-9 1.7 . Reference Documents 1-10 CHAPTER 2 CONTROLS AND OPERATIONS 2. 1 General 2-1 2.2 Controls and Indicators 2-1 2.3 Operati ng Procedures 2-11 2.3.1 Loading 2-11 2.3.2 Unloading 2-12 2.3.3 Storage 2-12 2.4 Special Operating Procedures 2-12 2.4. 1 Write Protection 2-12 2.4.2 Formatting a Disk 2-13 CHAPTER 3 PROGRAMMING 3. 1 General 3-1 3.1.1 RP02 Disk Pack Structure 3-1 3.1.2 lOT Selection 3-4 3.1.3 RP15 Status Faci I ity 3-7 3.2 Sequence of Operation 3-12 3.2. 1 Write Function 3-12 3.2.2 Read Function 3-16 3.2.3 Read All Function 3-17 3.2.4 Write All Function 3-18 iii CONTENTS (Cont) Page 3.2.5 Write Check Function 3-19 3.2.6 Idle Function 3-20 3.2.7 Seek Function 3-20 3.2.8 Recalibrate Function 3-21 3.3 Program Loop 3-22 CHAPTER 4 DRAWING CONVENTIONS 4. 1 F low Chart Symbology 4-1 4.2 Block Schematic Symbology 4-1 4.3 Logic Module Symbology 4-1 CHAPTER 5 PRINCIPLES OF OPERATION AND HARDWARE DESCRIPTION 5. 1 General 5-1 5.2 Detailed Block Diagram 5-1 5.3 Selecting the Controller 5-1 5.4 Status Monitoring and DCH DATA 5-5 5.5 Selecting the Drive 5-6 5.6 Selected Unit Cylinder Interrogation 5-6 5.7 Addressing the Pack 5-7 5.8 Cylinder Comparison 5-13 5.9 Sequencing the Memory 5-13 5.10 Commanding the Controller 5-14 5. 10. 1 Idle Function 5-16 5. 10.2 Read Function 5-16 5.10.3 Write Function 5-16 5.10.4 Reca I ibrate Function 5-16 5. 10.5 Seek Function 5-17 5. 10.6 Read All Function 5-17 5.10.7 Write All Function 5-18 5. 10.8 Write Check Function 5-18 5. 11 Determining Length of Transfer 5-19 5. 12 Maintaining Disk Format 5-20 5. 13 Processing the Data 5-21 5. 13. 1 Buffer Register 5-21 iv CONTENTS (Cont) Page 5. 13.2 Shift Register 5-23 5. 13.3 Longitudina I Parity Register 5-24 5. 14 Control I i ng Ma jor State 5-25 5.15 Commanding the Drive 5-31 5.16 Read Data Separation 5-41 5. 17 Maintaining Controller Format 5-55 5. 18 Control! ing Transfer Direction in the PDP-15 5-58 5.19 Control I ing Transfer Direction in the RP02 5-67 5.20 Controlling Transfer Direction in the RP15 5-72 5.21 Word Count and Current Address Control 5-94 5.22 Write Protection for the Drive 5-96 5.22.1 Entire Unit Protection 5-96 5.22.2 Partial Unit Protection 5-97 5.23 Status Control 5-99 5.24 Interrupt Control 5-106 5.25 Maintenance Control 5-107 5.26 Interfacing the Drive 5-111 5.27 Interfacing the I/O 5-111 CHAPTER 6 MAINTENANCE 6. 1 Introduction 6-1 6.2 Preventive Maintenance 6-1 6.2. 1 Test Equipment Required 6-1 6.2.2 Mechanica I Checks 6-2 6.2.3 Electrica I Checks 6-2 6.2.4 Margins 6-4 6.3 Corrective Ma intenance 6-4 6.3. 1 Genera I Corrective Procedures 6-5 6.3.2 Diagnostic Testing 6-5 6.3.2.1 RP 15 Instructi on Test 6-5 6.3.2.2 RP15 Formatter 6-8 6.3.2.3 RP15 Address Test 6-9 6.3.2.4 RP15 Random Data Exerciser 6-11 6.3.2.5 Vibration Tests 6-12 v CONTENTS (Cont) Page 6.3.3 Switch Panel Testing - LOCKOUT I LO I and LOA Switches 6-12 6.3.4 Changing Panel Indicator Bulbs 6-12 CHAPTER 7 SYSTEM SPECIFICATIONS 7. 1 General 7-1 7.2 Mechanical Description 7-1 7.3 Equipment Specifications 7-1 7.3. 1 Physical 7-1 7.3.2 Environmental 7-2 7.3.3 Electrical 7-2 7.3.4 Performa nce 7-5 CHAPTER 8 INSTALLATION 8. 1 General 8-1 8.2 Unpacking 8-1 8.2. 1 Special Handling 8-1 8.2.2 Inspection 8-1 8.2.3 Power Requ i rements 8-1 8.3 Insta IIation Procedure 8-3 8.3. 1 Converting to Another Power Source 8-3 8.3.2 Installing the RP15 Cabinet 8-6 8.3.3 Insta Iling Cables 8-6 8.3.4 Setting Unit Number Designator 8-9 8.4 Turn-On and Checkout 8-9 8.4. 1 Built-In Testing Without RP02 8-9 8.4.2 Testing With RP02 8-10 ILLUSTRATIONS Figure No. Title Art No. 1-1 RP15 Disk Pack Controller 5363-3 1-2 1-2 RP02P Disk Pack 5363-7 1-4 1-3 RP02P Disk Pack Sector and Index Pulse Generation 15-0441 1-5 1-4 RP02 Disk Pack Drive 5363-4 1-6 vi ILLUSTRATIONS (Cont) Figure No. Title Art No. Page 1-5 Latency vs Transfer Time in Normal and Back-To-Back Modes 15-0442 1-9 2-1 RP15/02 Controls and Indicators 5144-1 4830-1 5363-5 2-9 3-1 RP02 Disk Pack Structure 09-0343 3-2 3-2 RP02 Format for RP15 Controller 09-0342 3-3 3-3 RP15 Status Register A Bit Assignment 09-0341 3-8 3-4 RP 15 Status Register B Bit Assignment 09-0340 3-8 3-5 Insert a nd Execute Phase 09-0339 3-13 3-6 WRITE Function, SEEK State 09-0338 3-14 3-7 WRITE Function, Transfer/Write States 09-0337 3-16 3-8 READ Function, Read/Transfer States 09-0336 3-17 3-9 READ ALL Function, Transfer States 09-0424 3-19 3-10 WRITE ALL Function, Transfer States 09-0422 3-20 3-11 WRITE CHECK Function, Transfer States 09-0423 3-21 4-1 NAND Gate (M1l2) 15-0068 4-4 4-2 NAND Gate (M 113) 4-4 4-3 NOR Gate (M 112) 4-4 4-4 NOR Gate (M 113) 4-5 Inverter (M 111, M611) 4-4 4-6 Inverter (M 111, M611) 4-4 4-7 Basic Logic Relationships (M 121) 4-4 4-8 D Flip-Flop - Edge Triggered (M216) 15-0068 4-4 4-9 J-K Master-Slave Flip-Flop (M204) 15-0068 4-4 4-10 R-S Flip-Flop (M203) 4-11 Variable Clock (M401) 4-12 Pulse Amplifier (M602) 4-13 I/O Bus Receiver (M510) 15-0069 4-5 4-14 Binary to Octa I Decoder (M 161) 15-0069 4-5 4-15 Delays 15-0069 4-5 4-16 Connectors 15-0069 4-5 4-17 NAND Gate 15-0443 4-6 4-18 CLR HEAD Flip-Flop 4-19 Synchronizing Flip-Flop 15-0444 4-6 4-20 Signal Name Changes 15-0445 4-6 15-0068 4-4 4-4 15-0068 4-5 4-5 4-6 vii ILLUSTRATIONS (Cont) Figure No. Title Art No. Page 5-1 RP15 General Block Diagram 15-0514 5-3 5-2 Unit Selection Circuit 15-0447 5-6 5-3 SU Cylinder Interrogation Circuit 15-0448 5-7 5-4 Illegal Disk Address Decoding 15-0449 5-9 5-5 SAR Control Logic 15-0450 5-10 5-6 HAR, Simplified Schematic 15-0451 5-12 5-7 CAR, Simplified Schematic 15-0452 5-12 5-8 Cylinder Comparator, Simplified Schematic 15-0453 5-13 5-9 Function Register, Simplified Schematic 15-0454 5-15 5-10 Write Check Compare, Simplified Diagram 15-0455 5-19 5-11 Sector Word Counter, Simplified Diagram 15-0456 5-20 5-12 Buffer Register, Simplified Diagram 15-0457 5-22 5-13 Shift Register, Simplified Diagram 15-0458 5-23 5-14 Longitudina I Parity Register, Simplified Diagram 15-0459 5-25 5-15 Major State Control, Simplified Diagram 15-0460 5-26 5-16 Set Idle and Set Recal Logic, Simplified Diagram 15-0461 5-27 5-17 Set Seek Logic, Simplified Diagram 15-0462 5-28 5-18 Set Write and Set Inc Head Logic, Simplified Diagram 15-0463 5-29 5-19 Set Read Logic, Simplified Diagram 15-0464 5-31 5-20 Initiate Functions, Flow Diagram 15-0465 5-32 5-21 Read or Write Check Functions, Flow Diagram 15-0466 5-33 5-22 Write Function, Flow Diagram 15-0467 5-34 5-23 Read All Function, F low Diagram 15-0468 5-35 5-24 Write All Normal Function, Flow Diagram 15-0469 5-36 5-25 Write All Format Function, F low Diagram 15-0470 5-37 5-26 Tag and Bus Line Control, Simplified Diagram 15-0471 5-38 5-27 Tag and Bus Gate Logic, Simplified Diagram 15-0472 5-39 5-28 Tag and Bus Line Timing Diagram 15-0473 5-39 5-29 RP15/02 Read/Write Timing Waveforms 09-0334 5-42 viii ILLUSTRATIONS (Cont) Figure No. Title Art No. Page 5-30 RP15 VFO Control, Block Diagram 09-0321 5-43 5-31 RP02 Recording Characteristics 09-0320 5-44 5-32 VFO Timing Waveforms 15-0474 5-46 5-33 Synchronizing on CMPR (A 18F 1) during a Read All, Op Amp Error Voltage Waveform 5-48 5-34 Synchronizing on CMPR (A 18F 1) during a Read, Op Amp Error Vol tage Waveform 5-49 5-35 Synchronizing on CMPR (A18F1) during Read at X10 Expansion (Header Desired) 5-50 5-36 Synchronizing on CMPR (A 18F 1) during a Write, Op Amp Error Voltage Waveform 5-51 5-37 Synchronizing on CMPR (A 18Fl) during Write at X10 Expansion (Header Desired) 5-51 5-38 Clock Pulses In vs Clock Pulses Out, Proper Operation when Synchronizing on CMPR 5-52 5-39 Developed Clock (D17L2) vs Read Data Coax (E14Bl), Phase Adjustment 5-53 5-40 Clock Gate (D17Pl) vs Read Data Coax (E 146 1) during Read 5-54 5-41 RD Bit (C19E1) vs RD Data Coax (E14Bl), Identifying Header 5-55 5-42 Write Format Generator Count 5-56 5-43 BR/DCH Data Flow 09-0317 5-59 5-44 BR Control Logic, Simplified Diagram 15-0475 5-60 5-45 DCH Control Logic, Simplified Diagram 15-0476 5-63 5-46 TE Strobe Logic, Simpl ified Diagram 15-0477 5-64 5-47 BR Control Logic, Simplified Diagram 15-0478 5-65 5-48 BR Control Timing Diagram 15-0479 5-66 5-49 M 104 Block Diagram for DCH 15-0480 5-67 5-50 BR, SR and LPR Enable and Strobe Signals, Simplified Diagram 15-0481 5-68 5-51 LPR Control Signals, Simplified Diagram 15-0482 5-69 5-5t BR, LPR and SR Clearing Signals, Simplified Diagram 15-0483 5-71 5-53 Read/Write Sector Decoding Logic, Simplified Diagram 15-0484 5-73 5-54 Read All Function, Desired Data Field 15-0485 5-74 ix ILLUSTRATIONS (Cont) Figure No. Title Art No. Page 5-55 Timing Diagram Number 1 15-0486 5-77 5-56 Header and Data Field Logic, Simplified Diagram 15-0487 5-79 5-57 Timing Diagram Number 2 15-0488 5-81 5-58 Timing Diagram Number 3 15-0489 5-83 5-59 Word Plus Parity Decoding during Read, Simplified Diagram 15-0490 5-85 5-60 Word Plus Parity Decoding during Write, Simplified Diagram 15-0491 5-87 5-61 Timing Diagram Number 4 15-0491 5-89 5-62 Clock and Data Bit Decoding during Write, Simplified Diagram 15-0492 5-92 5-63 Clock and Data Bit Decoding in Read, Simplified Diagram 15-0493 5-93 5-64 WC and CA Control, Simplified Diagram 15-0494 5-95 5-65 Write Protection, Simplified Diagram 15-0495 5-97 5-66 Logic Operation of M121 Module 15-0496 5-98 5-67 H NF Status Control, Simplified Diagram 15-0497 5-100 5-68 Busy Status Control, Simplified Diagram 15-0498 5-101 5-69 PEE and EOPE Status Control, Simplified Diagram 15-0499 5-101 5-70 Longitudinal Error Status Logic, Simplified Diagram 15-0500 5-102 5-71 SUSU Status Control Logic 15-0501 5-103 5-72 Status Control Flag Logic, Simplified Diagram 15-0502 5-103 5-73 JB 0 N Status Control, Simpl ified Diagram 15-0503 5-104 5-74 Format Error/CMPR Status Logic, Simplified Diagram 15-0504 5-105 5-75 Word Error Status Logic, Simplified Diagram 15-0505 5-105 5-76 Write Check Error Status Logi c, Simpl i fied Diagram 15-0506 5-106 5-77 Priority Interrupt Status Logic, Simpl ified Diagram 15-0507 5-106 5-78 M 104 Block Diagram for API 15-0508 5-107 5-79 Maintenance Register, Simplified Diagram 15-0509 5-108 5-80 Register Control Logic, Simplified Diagram 15-0510 5-108 x ILLUSTRATIONS (Cont) Title Art No. Page 5-81 DPEM Decoding, Simplified Diagram 15-0511 5-110 6-1 RP15 Indicator Panels and Power Supplies 5363-8 6-14 7-1 Cable Particulars 15-0512 7-3 8-1 RP15/02 Overa" Dimensions 09-0347 8-3 8-2 RP15 Power Control 5363-6 8-4 8-3 RP15 Logic Power Supply Primary Wiring 5363-2 8-5 8-4 RP15 Cabinet Bolting Diagram 15-0513 8-7 8-5 RP02 Cable Connections to RP15 5363-1 8-8 Figure No. TABLES Title Table No. -- Page 2-1 RP15 Indicators 2-1 2-2 RP15 Controls 2-6 2-3 RP02 Indicators 2-7 2-4 RP02 Controls 2-8 3-1 Disk Pack lOT Instructions 3-5 3-2 AC Bit Assignment when Included in DPEM 3-6 3-3 DPLO and DPLZ Truth Tables 3-7 3-4 Status Register Bit Assignments 3-9 5-1 RP15 Function Arrangement 5-15 6-1 Test Equipment Required 6-2 6-2 RP15 Recommended Spares 6-4 6-3 AC Switch Options for Instruction Test 6-6 7-1 Cable Particulars 7-5 8-1 RP15 Checklist 8-2 8-2 RP 15/RP02 Interface Chart 8-8 8-3 RP15 I/O Interface Chart 8-9 xi CHAPTER 1 SYSTEM DESCRIPTION 1.1 GENERAL This chapter describes the RP15 System in general terms and presents some characteristics of memory storage systems. An overall description is provided of the RP02 Disk Pack System as it interfaces with the PDP-15 Computer System. The remainder of the chapter defines certain controller parameters as they relate to overall system performance. 1.2 RP15 CONTROL The RP 15 Disk Pack Controller interfaces from one to eight RP02 Disk Pack Drives to the PDP-15 Computer (see Figure 1-1). Each RP02, when equipped with an RP02P Disk Pack, provides the PDP-15 Central Processor with an additional 10.24 x 106 18-bit words of memory storage at an average data acquisition time of 50 ms (positional) and 12.5 ms (rotational). Data are transferred through the PDP-15 single-cycle data channel provided by the I/O bus. Transfers are double buffered to produce a transfer rate of 14.8 fJS for every two words and a latency time of 14.8 tJS. 1.3 DISK SYSTEM CHARACTERISTICS Modern computer systems use many methods to store information; each method has inherent advantages and disadvantages. Flip-flops and delay schemes are used for short-term data storage; magnetic devices are used for relatively long-term storage of data and instruction because once a magnetic state is established in the medium, it will remain, even after power is removed, until the state is modified or erased. Core memories provide relatively sma" storage capacity (4K to 32K words) in minimal space, and offer the advantage of almost instantaneous retrieval. Because of this fact, core memories are used to store data in various computation stages, as well as with instructions of the main operating program. However, rotating memories, such as magnetic tapes, provide greater capacity (150K to 8M words), but retrieval involves a search phase in a serial fashion by one fixed scanning device. For this reason, tapes are used for the storage of data that requires less frequent retrieval. 1-1 Figure 1-1 RP15 Disk Pack Controller 1-2 1 .3. 1 Disk vs Drum The larger rotating memories (drum and disk) provide massive storage capability but retain the disadvantage of search; access times are orders of magnitude better than for tape. As with tapes, these memories require a synchronizing or clocking scheme that serves as a constant indication of instantaneous scan speed, so that synchronization with the operating system may be achieved. Rotclting memories serve a "scratch pad" or "swapping" function in the overall scheme of the computer; and provide short-term storage of routines, subroutines, or blocks of data in some intermediate state of computation. These memories are also used for long-term storage of tabular functions, catalogues, dictionaries, and other reference material. In time-shared systems, rotating memories serve as temporary repositories of partially completed operations, thereby freeing the' other storage mediums to service a higher priority request. The drum is usually a non-removable device in which a set of fixed flying heads write the data in a particular format across the outside surface of the cylinder. It has particular application in vibrational environments or in installations where atmospheric conditions are not stringently controlled. The drum has a constant diameter and presents a fixed frequency response characteristic to the data being recorded. The response of the disk is directly proportional to its diameter, and the bit density of the innermost track is much greater than for the outermost track. This disadvantage can be overcome easi Iy and is a small consideration compared to the advantage of increased data capacity. 1 .3.2 Disk Pack Effects on the Drive The use of a removable media device, such as a disk pack, places some constraints on the design of the drive. Basically, the head design is affected because a movable head arrangement must be used so that the heads may be retracted while removing the pack. This requirement dictates that a set of single heads be held in vertical alignment by a common head tower which, in turn, must be actuated hydraulically, pneumatically, or by an electric positioning motor. Positioning means that extra logic must be provided for positioning comparators and servo control of head motion during these operations. The disadvantage of additional machinery and logic is minimal, however, when compared to the unlimited storage capacity provided by being able to remove and store many packs per drive. 1.4 RP02 SYSTEM CHARACTERISTICS 1 .4.1 RP02P Disk Pack The RP02P Disk Pack, shown in Figure 1-2, is the recording medium used with the RP15 Controller, and 'it is designed for mounting on an RP02 Disk Pack Drive. The RP02P is comprised of 11 aluminum 1-3 Figure 1-2 RP02P Disk Pack disks coated with magnetic oxide and mounted 1/2-in. apart on a common hub. Information is recorded on the 20 inner surfaces. The bottom disk is not used for recording and is notched to produce timing pulses for synchronization with the controller (see Figure 1-3). The disk contains 20 evenly spaced notches and a 21st notch called the index. The drive is equipped with a reluctance type pickup that senses these notches and sends a signa I to the controller where the pu Ises are frequency divided to produce 10 sector indicators. An additional circuit then separates the index pulse. Note that the sectors are numbered octally. 1.4.2 RP02 Disk Pack Drive The RP02 Disk Pack Drive is the mechanism controlled by the RP 15 Controller (see Figure 1-4). It comprises two major subassemblies: a. The spindle driving mechanism and b. The head positioning system. The spindle driving mechanism is made up of an ac motor I mounted below the baseplate that transmits a rotation of 2400 rpm to the disk pack by driving a conical spindle through a drive pulley and belt loop. The spindle secures the pack with a locking shaft within the spindle and washers below the spindle pulley. A mechanical lock is actuated by raising the cover. A pack-on switch disables spindle-drive motor power until a pack is installed. 1-4 5 5 \ 10~ CT OR / SECTOR 11 ~ / f o INDEX SLOT ~ ~ fI ! o / JI' R 7 5-,- T~ I NUMBERIN~\ S",,-/(SECTOR is OCTAL) S SEC I \ SE ~ "- - -~ // X 5 SE C T RELUCTANCE PiCKUP OR 1 /' ~-t-S S E T o S E C R 2 T o R 6/ 5 ,,/, / /\( / 5 ~SECTOR 4 / 15-0441 5 Figure 1-3 5 RP02P Disk Pack Sector and Index Pulse Generation The head positioning system consists of a linear positioning motor that moves a T-bar tower along a horizontal carriage, either toward or away from the center of drive motor rotation. When the T-bar is fully retracted, it is sensed by a microswitch and braking power is applied. The disk pack may then be removed. The T-bar is used to mount 20 back-to-back head assemblies that are unloaded by cammi'ng action when the linear motor is fully retracted. A detenting mechanism stops the head assembly over any cylinder position. The drive provides a means to monitor head position, drive speed, and rotational position. A cylinder transducer, made up of a 145 k Hz excited sensing transformer and a toothed rack that rides with the head assembly and passes the sensing transformer while heads are in motion, produces a modulated signal that is an indication of head position. This signal is fed to an up/down counter in the RP02 logic. Drive speed and rotational position are monitored by a dc reluctance pickup that senses slots in the bottom disk of the pack (see Figure 1-3). This signal is sent back to the controller, to indi cate disk position, and to a flip-flop rate sampler within the drive logic to generate an up-to-speed indication to' the controller whenever the drive reaches 70 percent of rated speed. Dynamic braking of the drive motor is accomplished by replacing ac power with dc power for approximately 12 seconds, whenever the STOP switch is depressed. Dynamic braking also occurs whenever the cabinet cover is lifted. 1-5 Figure 1-4 RP02 Disk Pack Drive The read/write heads contain two center-tapped coi Is (one for the read/write gap and one for the erase pole). Diode switching is used to place ground on the center tap of the selected head. The heads are 1-6 gimbal-mounted in the horizontal plane and leaf-spring loaded in the vertical plane; when the disk is up to speed, the heads fl y on a cushi on of air over the surface of the di sk • There are four basic operations performed by the drive under controller command. They are: Seek Write Read Recalibrate The Seek operation is initiated by the receipt of a cylinder address from the controller. The drive logic compares this address with its present address and determ"ines the direction in which the heads must move. Head motion is then accomplished and monitored by a difference count within the drive and is detented in position when the count reaches zero. The time required to locate the next cylinder address is limited to 100 ms by a time delay actuated at the start of the Seek. Failure to re-detent during this time results in a SEEK INCOMPLETE to the controller. When the new address is reached, and after a 3 .O-ms damping delay" the drive indicates to the controller its readiness to Read or Write. When Write is commanded, the controller supplies data to the write-selected head as a double-frequency non-return-to-zero pulse train, together with clock pulses for synchronization. The data and clock information are recorded as reversals in magnetic flux on a side-trimmed 0.006-in. wide track. When Read is commanded, the same head is read-selected to sense the previously recorded flux changes, producing current reversals in the head windings. This signal, which contains both data and clock pulses, is sent to the controller for processing. When Recalibrate is commanded, the heads are moved by a forced forward seek that sends the carriage to the forward stop. When the carriage reaches the stop, it executes a normal reverse seek to home position (cylinder 000). The drive signals the controller 3 ms after detent that it is ready for instructions. NOTE The sequence just described occurs as a "first seek II whenever the drive START switch is depressed and after the motor has reached 70 percent of rated speed. There are several safety circuits in the RP02 drive. These circuits protect data from being destroyed in the event of component failure. With the exception of ac/dc voltage failure, all conditions will issue a FILE UNSAFE indication to the controller; will deselect heads and terminate Read, Write, or Erase operations; will drop ready; and will light FILE UNSAFE on the panel. The FILE UNSAFE indication can be reset by switching START/STOP to the STOP position. Loss of primary power will remove all de voltages from the machine. This automatically prevents Write current. If any dc logic voltage is 1-7 lost, heads are deselected to prevent writing. If an unsafe condition is present when a drive is turned on, an indication of FILE UNSAFE is given immediately. If the heads are extended when primary ac power fails, STOP is depressed, or the disk compartment door is opened before depressing STOP; the heads will automatically retract. 1.5 PDP-15 COMPUTER SYSTEM CHARACTERISTICS The PDP-15 Computer System consists of three asynchronous subsystems: a. Central Processor (CPU) b. Memory c. I/O Processor (I/O PU). The PDP-15 is an lS-bit word length machine with a memory cycle time of SOO ns. Optional features include core memory expansion out to 131,072 words and a memory-protect system. The CPU conducts bidirecti onal communi cati on with both the memory and the I/O PU. It performs all required arithmetic and logical operations while controlling and executing stored programs. The core memory is the primary storage area for instructi ons and data. It is organized into pages and banks, with two pages comprising one bank. A page is capable of storing 4096 lS-bit words. The I/O PU provides the timing, control, and data lines between either the memory or the CPU, and the peripheral devices. In addition, it can contain a real-time clock and an automatic priority interrupt system. The I/O PU handles all peripheral data transfers. These transfers are accompl ished in three possible I/O modes as follows: a. Single-cycle block (up to a million words/second) b. Multicycle block (250,000 words/second input and lSS,OOO words/second output) c. Program-controlled (single word to/from CP Accumulator). The three subsystems operate together under console control. The console provides manual initiation of programs, monitoring of CPU and I/O PU registers, and manual examination and modification of memory contents. The RP 15 interfaces with memory through a single-cycle data channel break. The minimum PDP-15 configuration required for use with the RP 15 Disk Pack Controller is the PDP-15/10 augmented by SK of memory, and a PC 15 High-Speed Paper Tape Reader/Punch. This is the first level system. The configuration is expandable due to pre-wired facilities that allow additional memory and peripherals to be plugged in at any time. l-S 1.6 SINGLE-CYCLE INTERFACE AND I/O BUS The RP15 transfers data to and from the PDP-15 via the single-cycle data channel. During a singlecycle transfer, the RP15 keeps track of its own word count 0NC Register) and specifies the absolute address from or to which it wishes to transfer (CA Register). The PDP-15 Permits two modes of single-cycle operation termed "Normal ll and II Burst II • The Burst mode is used when the device can transfer a word every microsecond. In the RP15, all transfers are made in the Burst (or back-to-back) mode unless an odd number of words is to be transferred, in which case the last word is transferred in the Normal mode. Such transfers are made possible by a double-buffering scheme that allows assembly of two lS-bit words within the controller before they are transferred. This is done to achieve an economy of demand on the I/O bus that allows other devices access to the bus during RP15 assembly time (see Figure 1-5). LATENCY TIME 14.8 )JS I+- ON THE BUS o. BACK TO BACK !+-SYNCH .. I- ==\ TRANS. 2 WORDS ON THE BUS IO.8)Js 4)Js I J 4)Js OFF THE BUS I I ---I--- OFF THE BUS .. I J I 10.8)Js- I+- 4)Js TO TRANSFER TWO WORDS IN 4)Js OF BUS TIME ON THE BUS --4--0FF THE BUS-- b.NORMAL SYNCH =9:~ r I I 3)Js-~1+--4.4)Js-""-- r 3)Js --+t_- _---10.4)JS TO TRANSFER TWO WORDS ~ CONSUMING 6)Js OF BUS TIME --l Figure 1-5 15-0442 Latency vs Transfer Time in Normal and Back-To-Back Modes Because of the rotational speed of the RP02, the latency time for double-buffered transfers is 14.S !-Is, i.e., in this mode the RP15 must have access to the I/O bus every 14.SIJS, as long as it is transferring data on a two-word-per-break basis. If access is not granted in that time, a ti ming error will be raised. As shown in Figure 1-5a, the first two words use 4 !-IS of I/O bus time (2 IJS fixed synchronization + 1 !-Is/word). This leaves 10.8 fJS of bus time during which other devices may have access to the bus (provided, of course, their latency times are compatible). Figure 1-5b shows the transfer characteristics 1-9 for a single word transfer (last word in an odd number of words) in which the latency time is 7.4 ~. Note that what is termed the Normal mode of operation is the uncommon mode of operation for the RP15. If single buffering had been used in the RP15, all words would have been transferred on this one-word-at-a-time basis, and only 4.4 ~ of bus time would have been available for interlacing devices. In addition, 2 IJS of fixed synchronization time would have been wasted on every second word transferred. 1.7 REFERENCE DOCUMENTS The following documents contain information which supplements that contained in this manual: PDP-15 Interface Manual (DEC-15-HOAB-D) PDP-15 Systems Reference Manual (DEC-15-BRZA-D) PDP-15 Installation Manual (DEC-15-H2AB-D) PDP-15 Operator's Guide (DEC-15-H2CA-D) PDP-15 Module Manual (DEC-15-H2EA-D) 1-10 CHAPTER 2 CONTROLS AND OPERATIONS 2.,1 GENERAL This chapter contains information required to operate the RP15 Controller. Controls and indicators are also identified. 2.2 CONTROLS AND INDICATORS The RP15 indicators are located on the top front of the unit and are defined in Table 2-1. The controls are located on a logic panel inside the front door (refer to Table 2-2). The RP02 indicators and controls are located on its console panel and are explained in Tables 2-3 and 2-4, respectively. The contn:>ls and indicators for both units are shown in Figure 2-1. Power controls and indicators for the RP 15 are found on the Type 841B Power Control located inside the RP15 cabinet. These are not included in Tables 2-1 through 2-4, but are shown in Chapter 8. Table 2-1 RP 15 Indi cators Index No. Function Name 1 BUFFER REGISTER Thirty-six indicators that light on binary 1s to show the contents of the Buffer Register's two PDP-15 words. 2 CONTROL STATUS comprising: Nine indicators that show controller status as follows: DED One lamp that lights when the DO NE and ERROR flags are disabled from the Program Interrupt (PI) and the Automatic Priority Interrupt (API) system. ATD One lamp that lights when the ATTENTION flag has been disabled from the PI and API system. GO One lamp that lights when bit 08 of Status Register A is set, enabling the Function Register to be executed. 2-1 Table 2-1 (Cont) RP15 Indicators Index No. 2 (cont) 3 4 Name Function DISK FLG One lamp that lights when any error, attention, or job done flags have been raised. JOB DONE One lamp that lights when a function is complete. (Exceptions are Idle, Recalibrate, and Seek .) ATT FLG One lamp that lights on an attention flag which is raised whenever any unit attention is raised (OR of UAOO-07). ERR FLG One lamp that lignts when any error condition occurs (OR of all errors). BK RQ One lamp that lights when a request is made to access memory. BUSY One lamp that lights when the controller is busy (other than Idle). WORD COUNT Register comprising: Sixteen indicators that show the following: WC OVFLO One lamp that lights when a word count overflow has occurred, i.e., when the desired number of word transfers are comp Iete • WC 03-17 Fifteen lamps that show the 2 1s complement of the number of 18-bit words yet to be transferred from or to memory. FUNCTIO N Register FROO-02 Three indicators that light on binary ls in bits 03, 04, and 05 of Status Register A to show a 3-bit octal number corresponding to one of eight functi ons to be performed. o = Idle 1 = Read 2 = Write 3 = Reca librate 4 = Seek 5 = Read All 6 = Write All 7 = Write Check 5 UNIT SELECT Register UROO-02 Three indicators that light on binary ls in bits 00, 01, and 02 of Status Register A to show a 3-bit octal number corresponding to the unit (one of eight) selected. o = Unit 0 1 = Unit 1, etc. 6 UNIT STATUS Register comprising: Five indicators that show the status of the unit selected as follows: 2-2 Table 2-1 (Cont) RP15 Indicators Index No. 6 Name Function SUOL One lamp that lights when the selected unit has power and is placed on line by a switch on that unit console. SU RDY One lamp that lights when the selected unit is ready for data transfer. SUSU One lamp that lights when a seek is underway on the unit selected. SURO One lamp that lights when the selected unit is in READ ONLY mode as selected by a switch on that unit console. SULO One lamp that lights when the selected unit is locked out, i.e., LOCKOUT switch in LOCKOUT position, the Unit Select register is eql)al to the Lock-out register, and the CAR ~ LOA. (cont) 7 SWITCH MODE Register comprising: Three indicators that show the status of the control switches on the RP15 logic as follows: FMT One lamp that lights when the FORMAT/ NORMAL switch is in the FORMAT position. NORM One lamp which lights when the FORMAT/ NORMAL switch is in the NORMAL position. LOCKOUT One lamp that lights when the LOCKOUT switch is in the LOCKOUT position indicating that the LO and LOA switches are enabled. 8 CURRENT ADDRESS Register CAOl-17 Seventeen indicators that show bits 1-17 of the current memory address. 9 CYLINDER ADDRESS Register CAROO-07 Eight indicators that light on binary 1s showi ng the contents of the Cylinder Address register in the RP15. 10 HEAD ADDRESS Register (Surface Address) HAROO-04 Five indicators that light on binary 1s to show the current head address. 11 SECTOR ADDRESS Register SAROO-03 Four indicators that light on binary 1s to show the current sector address. 12 LOCKOUT Register comprising: Six indicators that I ight on binary 1s as follows: LOOO-02 Three Lockout Unit Lamps that indicate the unit number (0-7) on which writing cannot take place in or below the cylinder address indicated by the Lockout Address Indicators if the LOCKOUT switch is set. LOAOO-02 Three Lockout Address Lamps that indicate the cylinder address (in octal) in or below which 2-3 Table 2-1 (Cont) RP15 Indicators Name Index No. Function writing cannot take place on that unit displayed by the Lockout Unit Indicators if the LOCKOUT switch is set. 12 (cont) 13 SELECTED UNIT CYLINDER ADDRESS Register SUCAOO-07 Eight indicators that light on binary 1s from the Cylinder Address Register in the selected RP02, showing the address in that unit at which the heads are presently positioned. 14 CONTROL STATE Register cpmprising: Seven indicators that show the current state of the controller as follows: READ One lamp that lights when the control is in Read state. WRITE One lamp that lights when the control is in Write state. SEEK One lamp that lights when the control begins a Seek. CLR HEAD One lamp that lights when the control is in Clear Head state, i.e., head select register is cleared in RP02 Drive. INC HEAD One lamp that lights when the control is in Increment Head state, i . e ., when the current head is being disabled and the next head selected in the RP02 Drive. RECAL One lamp that lights when the control begins a Reca librate. IDLE One lamp that lights when the control is in Idle (non-busy state). 15 UNIT ATTENTION Register UAOO-07 Eight indicators that light on binary 1s showing the unit (0-7) from which ATTENTION has been raised as a result of a successfully completed SEEK command. 16 SECTOR WORD COUNT Register comprising: Eight indicator lamps that indicate the following: 17 SWC OVFLO One lamp that indicates that the sector word counter has overflowed, signal ing that the required number of 36-bit words have been transferred to or from the disk. SWCOO-06 Seven lamps that show the number of 36-bit words read or written in a single sector. FORMAT GENERATOR Register FMT GENOO-OS Nine indicators that I ight on binary 1s showing the state of the format generator. 2-4 Table 2-1 (Cont) RP15 Indicators Index No. Name 17 (cont) 18 19 Function This register controls formatting during WRITE, WRITE ALL, and FORMAT instructions. MAINTENANCE Register comprising: Seven indicators that show the following: MNT One indicator that lights when the controller is in the maintenance mode. MROO-05 Six indicators that show the binary contents of the Maintenance Register. ERROR STATUS comprising: Fourteen indicators that show that an error has occurred as follows: FE One lamp that indicates a Format Error has occurred due to a parity error in a header word. WE One lamp that indicates a Word Error has occurred due to a parity error ina data word. LE One lamp that indicates a Longitudinal Error has occurred due to a parity error in a bit position of a single sector. WCE One lamp that indicates a Write Check Error has occurred due to no comparison between two 18bit words read from memory and a paired data word read from the disk. TE One lamp that indicates a Timing Error has occurred due to a missed transfer of a data word to or from processor memory. PE One lamp that indicates a Programming Error has occurred due to an illegal series of RP15 instructions. HNF One lamp that indicates a Header Not Found error has occurred due to the traversing of a complete revolution of the disk while searching unsuccessfully for a header word (unique sector address) • WPE One lamp that indicates a Write Protect Error has occurred due to a violation of either of two Write Protect functions. NEC One lamp that indicates a Non-Existent Cylinder address has been commanded. This bit is present as long as an ill ega I cyl i nder address resides in the CAR. NEH One lamp that indicates a Non-Existent Head (surface) address has been commanded. This bit is present as long as an illegal head address resides in the HAR. 2-5 Table 2-1 (Cont) RP 15 Indi cators 19 (cont) Function Name Index No. NES One lamp that indicates a Non-Existent Sector address has been commanded. This bit is present as long as an illegal sector address resides in the SAR. EOP One lamp that indicates the End Of Pack point has been reached before the word count is complete. SUSI One lamp that indicates a Selected Unit Seek Incomplete error has occurred due to 100 ms passing while unsuccessfully seeking a particular cylinder address. SUFU One lamp that indicates a Selected Unit File Unsafe signal has been received from the selected RP02. 20 SHIFT REGISTER SROO-35 Thirty-six indicators that light on binary lis showing the contents of the Shift Register in the RP 15. This register assembles seria I data from the disk or serializes the data being transferred to the disk. 21 LONGITUDINAL PARITY REGISTER LPROO-35 Thirty-six indicators that light on binary ls showing the contents of the LPR in the RP15. This register accumulates bit position odd parity for each sector. Table 2-2 RP15 Controls Index No. Name Function 22 FORMAT/NORMAL Switch One two-position rocker switch that, in FORMAT positi on, enables the controller for formatting operations and, in NORMAL position, enables the control! er for norma I operati ons. 23 FORMAT/NORMAL Lamp One lamp that lights Clear when the FORMAT/ NORMAL switch is in FORMAT position. 24 LOCKOUT Switch One two-position rocker switch that, in LOCKOUT position, enables the controller to write protect disk addresses as selected by the LO and LOA toggle switches. The unmarked position is normal for "no lockout" condition. 25 LOCKOUT Lamp One lamp that lights Red when the LOCKOUT switch is in LOCKOUT position. 26 LOA 00-02 Switches Three toggle switches that determine the cylinder address (in octal) in or below which writing may not occur on the unit designated by the LO switches. 2-6 Table 2-2 (Cont) RP15 Controls Index No. 27 Name Function LO 00-02 Switches Three toggle switches that determine the unit (0-7) on which the LOA switches are applicable. Table 2-3 RP02 Indi cators Index No. Name 28 Unit Number/Ready Indicator 0-7 One static indi cator that shows the unit address of the disk pack which has been determined by its position on the bus. The number displayed can be manually changed within the unit. This indi cator lights Green when the drive has reached operational speed and the heads are positioned to track 000 on the initial load operation. The indicator goes off when the STOP switch is depressed or when system power is removed. 29 128, 64, 32, 16, 8, 4, 2, 1 (Access Position) Eight indicators that show the cyl inder to whi ch the heads have been positioned. 30 FILE UNSAFE Indicator One indicator that lights Red when an unsafe condition exists in the RP02 Drive. Manual intervention is required to clear the condition. Placing the START/STOP switch in the STOP position resets the indicator. 31 READ ON LY Indicator One indicator that lights Clear when the READ WRITE/READ ONLY switch is in the READ ONLY position and extinguishes when the switch is in the READ WRITE position. Function NOTE This light only indicates the position of the switch and is not necessari Iy an indi cation of whether or not the drive is write protected. (Refer to Table 2-4 under READ WRITE/READ ONLY switch.) 2-7 Table 2-4 RP02 Controls Index No. Name Function 32 START/STOP Switch One two-position rocker switch that in START position applies power to the drive motor if the main power switch to the unit is on, a pack has been loaded, and the cover is closed. When the disk pack speed is greater than 1700 rpm, and the pack stabilization delay of 60 seconds has expired, it loads the heads and positions them to cylinder 000. In STOP position, power is removed from the drive, the heads are retracted, and dynamic braking stops the spindle within 12 seconds. 33 ENABLE/DISABLE Switch One two-position rocker switch that in the ENABLE position places the RP02 on-line. When in the DISABLE position, the RP02 is sti lion-I ine until the unit has been deselected by the RP15. When the RP02 has been deselected with the switch in the DISABLE position, the unit is off-I ine and wi II remain off-I ine {even if reselected} unti I the switch is placed in the ENABLE position. 34 READ WRITE/READ ONLY Switch One two-position rocker switch whose mechanical position enables initialization of two possible modes, when that unit is selected by the RP15, but has no control over changing the mode until that unit is once again deselected by the RP15. NOTE Because of the above, the switch could be in the READ ONLY position with the READ ON LY indicator on, but if the unit had not been deselected from a Read/'Nrite mode, it would still be Read/'Nrite enabled a nd vi ce versa. 2-8 22 23 24 25 8 ~ 27 ~ 26 b. RP15 Switch Panel 1:3 33 34 28 32 29 16 19 21 a. RP15 Panel Indicators 31 30 c. RP02 Panel Figure 2-1 RP15/02 Controls and Indicators 2-9 2.3 OPERATING PROCEDURES In Normal operation, the FORMAT/NORMAL switch on the RP15 switch panel is put in the NORMAL position (see Figure 2-1). In the RP02, the ENABLE/DISABLE switch is put in the ENABLE position, the READ WRITE/READ ONLY switch is put in the READ WRITE position, and the START/STOP switch is set to START (see Figure 2-1). NOTE The RP02 START/STOP switch should be left in STOP position until an RP02P disk pack is loaded and the cover closed. 2.3. 1 Loading To load an RP02P Disk Pack on the RP02 Disk Pack Drive, proceed as follows: Procedure Put the START/STOP switch in the STOP position. 2 Hold the disk pack, enclosed in its plastic container, by the top handle; rotate the bottom cover latch and remove. NOTE The disk pack wi 1\ remain attached to top cover. 3 Raise the cover on the drive and lower the pack, with its cover attached, into the well provided, unti I the pack sits on its conical hub. 4 Rotate the top cover latch clockwise until the pack is properly seated and secure. CAUTION Do not overtighten; merely make it snug. 5 Rotate the top cover latch in the opposite direction, while lifting the plasti c cover out of the well. 6 Return top and bottom covers to storage. 7 Close the lid on the drive and place the START/STOP switch in the ST ART positi on. 2-11 2.3.2 Unloading To unload an RP02P Disk Pack from the RP02 Disk Pack Drive, proceed as follows: Procedure Step Put the START/STOP switch in the STOP position. 2 Wait for the automatic brakes to stop the drive. When stopped, raise the lid on the drive. NOTE If the I id is opened when the drive is powered, power is automatically removed and braking action is applied. 3 Remove the plastic top cover from the bottom cover and lower the top cover into the well over the disk pack. 4 Once it is seated, rotate the top cover latch counterclockwise until a clicking sound occurs. 5 Lift the pack out of the well • 6 Holding the bottom cover ready on the palm of the left hand, place the cover and pack assembly firmly on its bottom cover. 7 Rotate the bottom cover latch unti I snug and return the encased disk pack to storage. 8 Close the cover on the disk pack drive. 2.3.3 Storage Store the RP02P Disk Pack in its plastic container in the same ambient conditions as prevail at the drive. 2.4 SPECIAL OPERATING PROCEDURES The RP 15 can be operated under special conditions as described below. 2.4. 1 Write Protecti on To write protect any disk pack, proceed as follows: Procedure To read only from an entire disk pack, place the READ WRITE/ READ 0 NLY switch on the disk pack drive in READ 0 NL Y position. (continued on Page 2-13) 2-12 Step 2 Procedure To write protect only a certain block of addresses, set the READ WRITE/READ ONLY switch on the disk pack drive to READ WRITE position. On the RP15 switch panel, place the LOCKOUT switch in LOCKOUT position, set the LO toggle switches to the octal equivalent of the RP02 unit number, and set the LOA toggle switches to correspond to the upper cyl inder address I imit desired. 2.4'.2 Formatting a Disk To format a new disk pack, refer to the Formatter Program (MAINDEC-15-D5FA-D) supplied with each system. 2-13 CHAPTER 3 PROGRAMMING 3.1 GENERAL Programming the RP 15 i~ predicated upon the requirements imposed by the RP02 Disk Pack. A brief summary of the file is given as an introduction to programming considerations (see Figures 3-1 and 3-2). 3. 1 • 1 RP02" Disk Pack Structure The total capacity of the RP02 Disk Pack is 232,000,000 bits, which is equivalent to 12,900,000 18bit words. In actual practice, the two outside surfaces are not used; on all surfaces, tracks 200,201, and 202 are reserved for maintenance. When these conditions are recognized, along with the data required for two synchronization areas, word and longitudinal parity, and a header word for each sector, the relative characteristics (as called out in the Summary on Figure 3-1) yi eld a total data word capacity of 10,240,000 18-bit words. In the RP02, each disk contains 203 cylinders. Movable heads, connected to a common positioning actuator, access one cylinder at a time. Track-to-track, average, and maximum positioning times are 20,50, and 80 ms, respectively. Rotation speed is 2400 rpm (or a rotational time of 25 ms), providing average and maximum latency times of 12.5 and 25 ms, respectively. Data are recorded by a double frequency, non-return-to-zero technique. Data are formatted into 128 36-bit word sectors that are individually addressable; each word provides storage space for two 18-bit PDP-15 words. The RP02 has 20 read/write heads that record data at 2.5M bps. Recording densities are 1530 bpi for track 000 and 2228 bpi for track 202. Each RP02 track contains 10 sectors. Word transfer rate is 14.8 tJS for each 36-bit word or 7.4 tJS for each 18-bit PDP-15 processor word. Data formats for information recorded on the disks are arranged as shown in Figure 3-2. These consist of a 30-word IIpreamble", a one-word header, a four-word data sync area, a data field of 128 36-bit words, followed by a two-word tail or IIpostamblell. The preamble or VFO sync area comprises 1109 IIzeros ". This area is written by the control during 10 Write All Format mode and provides the time necessary for the VFO circuit to determine the nominal 3-1 WORD 255--\---l....-, **NOTE: CORRESPONDING TRACKS ON ALL SURFACES CAN BE CONSIDERED AN INFORMATION CYLINDER. TRACK 180 ON SURFACE 0 TRACK 180 ON SURFACE I •••••" . No.1 DATA SURFACE --i~ TRACK 180 ON SURFACE 2 * NOTE: etc. TRACKS 200,201, AND 202 ARE RESERVE D FOR MAINTENANCE ~!II••••I!!!!I'--No. 19 DATA SURFACE RP02 DISK PACK 2400 RPM DRIVE MOTOR SUMMARY 11 DISKS 20 DATA SURFACES 4000 TRACKS 40,000 SECTORS . 10,240,000 18 - 81T WORDS .. WORDS PER SECTOR 256 I SECTORS I WORDS X PER TRACK 10 = PER TRACK ! 2560 TRACKS PER SURFACE 200 != I SURFACES J WORDS WORDS X PER SURFACE PER PACK 512,000 20 = PER PACK 10,240,000 09-0343 Figure 3-1 RP02 Disk Pack Structure 3-2 SECTOR PULSES A ONE RP02 TRACK A A --1 I I I 2 0 AA-INDEX PULSE A 3 4 5 6 7 8 9 1- SECTORS PER TRACK , ••-------EACHsECToR-------.~ 128 WORDS \ W I W 31 ~~ ______ ~ ~~ ~ __ __ ______ ~~ 1718 ____'_8_Z_E_R_0_S____ 36 2526301323510------360 ~ ~ ~~~~~ ~~ ____ __ SYNCHR~NIZATION I~l'----NO-T---...U~S-E-D--....JI~J~ T~' CUE 1109 ZEROS I NDER ADDS 35360 ______ DATA CUE ~~ ________ ~ 4~~2}IT5 __ PARITY 1 BIT ADDS SECTOR S~AB~~ ADDS 37 35360 ~T5 I BI~ I~ 37~T5 DATA WORDS 1- 126 _DATAOWORD_ 0 WORD 127 36 36 ~ ~~ [~U~RD ) ' \ GAP HEAD (SURFACE) 3~0 360------------360 LPR BITS ' .LPR PARITY 3536 36 DATA BITS It- ~~~~TY T EACH DATA WORD Figure 3-2 RP02 Format for RP15 Controller 09-0342 disk pack density (frequency) during Read functions and to lock in on that frequency. The preamble area is followed by a 1 bit that cues the controller that the header word follows. The header is a one-word field. In the RP15 system, the first 18 bits are not used but are filled in with zeros. The second half is used for addressing; bits 18-25 contain the cyl inder address to which the heads are to be slewed, bits 26-30 designate the head to be enabled (surface address), and bits 32-35 provide the sector address. Bit 36 is a parity bit generated by the control at format time; bit 31 is wired as a spare for possible address expansion. The purpose of the header is to locate the desired sector by comparing the cyl inder, head, and sector address, as read from the header on the disk, with the cyl inder, head, and sector address deposited in their respective registers within the control. The header field is followed by a gap provided for turning off the Read function and turning on the Write functi on. This area is ignored by the controller since its contents are indeterminate. The third field is the VFO Data Sync Area that contains four words of zeros, with the last bit of the fourth word set to a 1. This area cues the control that the data fi eld follows and also gives the VFO ~ime to re-sync after the gap. The fourth (data) field contains 128 36-bit words, with each word followed by an odd parity bit (word parity) . NOTE Each 36-bit word transferred between controller and disk comprises two 18-bit words (256) when transferred between processor and controller. This controller only checks 36-bit word parity. The fifth and last field, called the tailor "postamble", contains two 37-bit words. The first word contains 36·bits of odd longitudinal parity, accumulated for each significant bit of the data field, followed by its own word parity. The second word contains 37 indeterminate guard bits that serve to disable write current, without destroying the longitudinal parity word. 3.1.2 lOT Selection A device selection code (63 or 64) from the PDP-15 provides the basic activating signal to the RP15 Disk Pack Controller's logic. Sensing of the device selection code by the logic circuits enables the receipt of lOP pulses from which the lOT pulses are internally generated to control operation of the disk pack. The functi~ns of the lOT pulses are listed in Table 3-1. NOTE In systems requiring more than one RP15 Controller, the system is easily modified by wiring changes to accommodate the second controller with two other available Device Select Codes. 3-4 Table 3-1 Disk Pack lOT Instructions Mnemonic Symbol Octal Code DPSF 706301 Skip on DISK flag. Skip the following instruction if either the JOB DONE, ATTENTION, or ERROR flags are set. DPOSA 706302 OR Status Register A into the AC. DPRSA 706312 Read Status Register A into the AC. DPLA 706304 Load the Cylinder Address Register from AC 0-7 (OOOS through 312S are legal). Load the Head Address Register from AC S-12 (OOS through 23S are legal). Load the Sector Address Register from AC 14-17 (OS through 11S are legal). DPSA 706321 Skip on ATTENTION flag. DPOSB 706322 OR Status Register B into the AC. DPRSB 706332 Read Status Register B into the AC. DPCS 706324 Clear the Status bits for Format Error, Word Parity Error, Longitudinal Parity Error, Write Check Error, Timing Error, Programming Error, Header Not Found, and End of Pack. DPSJ 706341 Skip the following instruction if the JOB DONE flag is set. DPOM 706342 OR the Maintenance Register into the AC. DPRM 706352 Read the Maintenance Register into AC 0-5. Clear AC 6-17. DPCA 706344 Load the Current Address Register from ACO-17. DPSE 706361 Skip the following instruction if an error condition is present. DPWC 706364 Load the 2 1s complement of the word count, contained in the AC, into the Word Count Register. DPEM 706401 Execute the maintenance instructions as defined by AC 9-17 (refer to Table 3-2). DPLM 706411 Clear the AC and leave maintenance mode. DPOU 706402 OR the Selected Unit Cylinder Address Register into the AC 10-17. DPRU 706412 Read the Selected Unit Cylinder Address Register into the AC 10-17. DPCF t 706404 Clear the Function Register. Select Unit O. Set Idle mode. Disable all interrupts. Set control to power clear state. Operati on Executed '0.. tAfter these instructions, another RP15 instruction should not occur for a minimum of 4~. 3-5 Table 3-1 (Cont) Disk Pack lOT Instructions Mnemonic Symbol Octal Code DPSN 706421 Skip the following instruction if FORMAT/NORMAL switch is in NORMAL position. DPOA 706422 OR the Cy Ii nder, Head, and Sector Address Reg isters into the AC. DPRA 706432 Read the Cyl inder, Head, and Sector Address Registers into the AC. DPLZ t 706424 Load the Accumulator zeros into Status Register A and execute bits 0-8 if GO bit is set (see Table 3-3). tt DPOC 706442 OR the Current Address Register into the AC. DPRC 706452 Read the Current Address Register into the AC. DPLO t 706444 Load the Accumulator lis into Status Register A and execute bits 0-8 if GO bit is set (see Table 3-3 tt). DPCN t 706454 Equivalent to a continue command. Clear the AC. Execute the Function Register. The FR is unchanged. tt DPOW 706462 OR the Word Count Register into the AC. DPRW 706472 Read the Word Count Register into the AC. DPLF t 706464 Load Status Register A from AC 0-8. Execute the new contents if the GO bit is set at completion of DPLF. Operati on Executed tAfter these instructions, another RP15 instruction should not occur for a minimum of 41-'s. ttWhen a DPLZ is issued with accumulator bits 0-8 equal to ones, the effect is the same as DPCN, with the exception that the accumulator is unchanged. Also, when a DPLO is issued, with accumulator bits 0-8 equal to zeros, the effect is the same as DPCN, with the exception that the accumulator is unchanged (refer to Table 3-3). Table 3-2 AC Bit Assignment when Included in DPEM Bit Description 09 Load the Maintenance Register from AC bits 12-17 of this word. AC bits 10 and 11 are ineffective when bit 09 is set. AC bits 12-17 are interpreted as data to be loaded into the six bit Maintenance Register. 10 Enter maintenance mode and interpret AC bits 11-17 as follows: (effective only when AC bit 09 is cleared). 11 Issue a maintenance Selected Unit Index Pulse. 3-6 Table 3-2 (Cont) AC Bit Assignment when Included in DPEM Bit Description 12 Issue a maintenance Selected Unit Sector Pulse. 13 Maintenance set JOB DONE. 14 Increment the Current Address Register. 15 Increment the Word Count Register. 16 Increment the Sector Address Register (overflow of SAR increments HAR, overflow of HAR increments CAR). 17 In a Read operation, one bit of data is transferred from the Maintenance Register to the Shift Register. In a Write operation, one bit of data is transferred from the Shift Register to the Maintenance Register. This instruction simulates one bit cell of data transfer through the same logic paths as normal data. Table 3-3 explains the operation of the DPLO and DPLZ instructions in Truth Table form. Table 3-3 DPLO and DPLZ Truth Tables DPLZ DPLO AC 1 SRA SRA AC 0 SRA SRA 0-8 V 0-8 0-8 0-8 V 0-8 0-8 0 + 0 0 0 + 0 0 + 1 1 0 + 1 1 + 0 1 1 + 0 1 + 1 1 1 + 1 = = = = = = = = 0 0 0 1 Note: SRA = Status Register A. 3.1.3 RP15 Status Facility The RP15 DISK flag appears on bit 12 of the PDP-15 IORS Register. Status conditions may be checked readily by observing certain lights on the RP15 indicator board. While operating the RP15, the interaction of the various conditions which raise these flags should be kept in mind, so that no confusion will result as to what caused the flags to be raised. In the RP15, there are two status registers designated Status Register A and Status Register B (see Figures 3-3 and 3-4, respectively). Table 3-4 relates bit position for each Status Register to the type of status indicated. 3-7 DONE AND ERROR FLAG INTERRUPT ENABLE ATTENTION FLAG INTERRUPT ENABLE GO WRITE PROTECT ERROR NON-EXISTENT CYLINDER ADDRESS NON-EXISTENT SECTOR ADDRESS _ _ _ _ _ _ _---l HEADER NOT FOUND UNIT SELECTED UNIT UNIT UNIT UNIT 4 UNIT 5 UNIT 6 = UNIT 7 UNIT 0 I 2 3 FUNCTION 0 I 2 3 0 I 2 3 4 4 5 6 7 5 6 SELECTED UNIT WRITE PROTECTED IDLE READ WRITE RECALIBRATE SEEK READ ALL WRITE ALL SELECTED UNIT SEEK INCOMPLETE-JOB DONE FLAG ERROR FLAG WRITE CHECK 09-0341 Figure 3-3 RP15 Status Register A Bit Assignment ATTENTION UNIT 0 ATTENTION UNIT I ATTENTION UNIT 2 A TTENTION UNIT 3 ATTENTION UNIT 4 ATTENTION UNIT ATTENTION 5 UNIT 6 ATTENTION UNIT 7 SELECTED UNIT FILE UNSAFE PROGRAMMING ERROR -------------~ END OF PACK TIMING ERROR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....J FORMAT ERROR ----------------~ WRITE CHECK ERROR WORD PARITY ERROR LONGITUDINAL PARITY E R R O R - - - - - - - - - - - - . . . . J SELECTED UNIT SEEK UNDERWAY SELECTED ------------1 UNIT NOT READY - - - - - - - - ' 09- 0340 Figure 3-4 RP15 Status Register B·Bit Assignment 3-8 Table 3-4 Status Register Bit Assignments Bits Assigned Status Reg. B A Error Status Type Attn. Sel. Unit Int. Func. ORed for Disk Fig 0 x x 1 x x 2 x x 3 x x 4 x x 5 x x 6 x x 7 x x 8 x 9 x x x 10 x x x 11 x x x 12 x x x 13 x x x 14 x 15 x 16 x 17 x x x x x x x x x x x x 0 x x x 1 x x x 2 x x x 3 x x x 4 x x x 5 x x x 6 x x x 7 x x x 8 x x 9 x x x 10 x x x 11 x x x 12 x x x 13 x x x 14 x x x x 3-9 x Table 3-4 (Cont) Status Register Bit Assignments Bits Assigned Status Reg. B A Error Status Type Attn. Sel. Unit 15 x 16 x x 17 x x Int. Func. ORed for Disk Fig. x x x There are five status categories: a. Error Status ho Selected Unit Status c 0 Attenti on Status d. Interrupt Status eo Functi on Status. The fourteen types of Error Status are: a. Format Error (Bit 12 of Register B) - The header word in each sector is parity checked when read. A parity error in the header word raises the format error status bit. Bit 17 of Register A is also raised. b. Word Parity Error (Bit 14 of Register B) - Each word in the data field is parity checked whi Ie reading. A word parity error raises the word error status bit. Bit 17 of Register A is also raised. c. longitudinal Parity Error (Bit 15 of Register B) - longitudinal parity is computed for each bit position of the data field. Errors that occur in longitudinal parity, while reading the data field, result in a longitudinal error status bit 0 Bit 17 of Register A is also raised 0 d. Write Check Error (Bit 13 of Register B) - Errors that occur in the comparison of data words during a write check function result in a write check error status bit 0 Bit 17 of Register A is also raised. e. Timing Error (Bit 11 of Register B) - Timing error status bit results from a missed data transfer between the PDP-15 and the RP15. The RP15 should be placed physically first on the positive I/O bus string to avoid this condition. f. Programming Error (Bit 09 of Register B) - There are three programming conditions that must be avoided in the RP15. When the RP15 is BUSY, the following instructions are illegal: DPlZ DPWC DPlOj DPlA ~PCN (or any instruction which simulates continue) DPCA DPlF IDPCS BUSY is defined either as 1. the time from the completion of a DPlZ, DPlO, DPCN, or a DPlF and 4 ~ later, if the function is an initiate type, i.e., Idle, Recalibrate, or Seek; or 20 the time from the completion of a DPlZ, DPlO, DPCN, or DPlF until the JOB DONE flag is raised, if the function is an execute type, i .eo, Read, Write, Read All, Write All, or Write Check. A violation of these conditions results in a programming 3-10 error, the illegal instructions are not executed, and Bit 17 of Register A is raised. There is a third programming condition that does not raise a programming error and therefore should be avoided. Following a DPLF, DPLZ, DPLO, DPCN (or any instruction which simulates a continue), or DPCF, another RP15 instruction should not occur for a minimum of 4 I-'s (RP 15 instructions are those with device code 63 or 64). g. Header Not Found Error (Bit 13 of Register A) - The Header Not Found is a status bit that is raised when the disk has made a minimum of one revolution while searching for a header word and has been unsuccessful in finding that word. Bit 17 of Register A is also raised. h. Write Protect Error (Bit 9 of Register A) - Write Protect Error is a status bit that is raised when a Write function is requested whose target is either in a Selected Unit Read Only mode or has been Selected Unit Lockout designated. Bit 17 of Register A is also raised. i• Non-Existent Cyl inder Address Error (Bit 10 of Register A) - This status bit is raised when the Cylinder Address Register is loaded with an illegal address (3138 through 3778)' It remains set until the illegal address is cleared. Bit 17 of Register A is also set. i. Non-Existent Head Address Error (Bit 11 of Register A) - This status bit is raised when the Head Address Register is loaded with an illegal address (248 through 378)' It remains set unti I the illegal address is cleared. Bit 17 of Register A is also raised. k. Non-Existent Sector Address Error (Bit 12 of Register A) - This status bit is raised when the Sector Address Register is loaded with an illegal address (128 through 178). It remains set until the illegal address is cleared. Bit 17 of Register A is also set. I. End of Pack Error (Bit 10 of Register B) - To the controller, each disk pack (or unit) appears as a continuous chain of sectors starting with cylinder 0008' head 008' and sector 008; continuing to cylinder 3128, head 238' and sector 11 8 , When a data transfer exceeds the upper limit before the word count has reached overflow, the JOB DONE flag (bit 16 of Register A) is set and the END OF PACK flag is raised. Bit 17 of Register A is also raised. m. Selected Unit Seek Incomplete Error (Bit 15 of Register A) - Selected Unit Seek Incomplete is a status bit that is raised when 100 ms have passed since a Seek was issued and the desired cylinder has not been found. Also, Bit 17 of Register A and the appropriate attention bit in Status Register B are raised. n. Selected Unit File Unsafe Error (Bit 8 of Register B) - Selected Unit File Unsafe is a status bit that is raised to indicate that a hardware failure has occurred in the selected unit. Bit 17 of Register A is also raised. The five types of Selected Unit Status are: a. Selected Unit Cylinder Address Status - An a-bit register called Selected Unit Cylinder Address, which can be read into the accumulator, indicates the current position of the heads in the unit presently selected. This is allowed only when the RP15 is not busy and the unit being interrogated is not presently executing a previously given command. This is feasible when more than one RP02 is controlled by the same RP 15. b. Selected Unit On-line Status - This bit indicates that power has been appl ied to the unit selected and that the heads are loaded. This bit can only be read from the indicator panel. c. Selected Unit Not Ready Status (Bit 17 of Register B) - SELECTED UNIT READY is raised when the selected unit has successfully completed a Seek. The "not-ready " condition, however, raises the status bit. d. Selected Unit Seek Underway Status (Bit 16 of Register B) - This bit indicates that the selected unit is in the process of seeking. 3-11 e. Selected Unit Write Protected (Bit 14 of Register A) - This bit indicates that the selected unit is "read-only" protected, or that the Unit Register is equal to the Lockout Register (UR = LO), the lockout switch is in the LOCKOUT position, and the Cylinder Address Register is equal to or less than the LOA register (CAR ~ LOA). The two types of Attention Status, indicated by bits 0-7 of Register B, designate the selected unit which raised the ATTENTION flag. They are indicated by the following: a. Bit 17 of Register B, cleared when the unit has successfully completed a Seek, indicating selected unit ready. b. Bit 15 of Register A, raised when the unit has unsuccessfully completed a seek, indicating selected unit seek incomplete. For Interrupt Status, the RP15 provides one flag that raises program or automatic priority interrupt requests (PI or API Interrupt Faci! ity). This flag is called the DISK flag. The DISK flag operates on API levelland port address 64. It is conditioned by the OR of the three sub-flags (JOB DONE, ERROR, and ATTENTION) and their interrupt enables (ATTENTION INTERRUPT, and JOB DONE/ ERROR INTERRUPT). These are described as follows: a. Job Done Flag Status (Bit 16 of Register A) - The JOB DON E flag is raised when (1) an execute type functi on has been successfu II y comp Ieted or (2) an execute type function has been aborted as a result of an error condition. b. Error Flag Status (Bit 17 of Register A) - The ERROR flag is an OR condition of all the error status conditions previously described. c. Attention Flag Status (Bits 0-7 of Register B) - The ATTENTION flag is an OR condition of attention bits 0 through 7 in Status Register B. d. Attention Interrupt Enable Status (Bit 7 of Register A) - Attention Interrupt Enable is a status bit that can be loaded with a DPLO, or DPLF instruction. When this bit is set, the ATTENTION flag is enabled for the interrupt system. e. Job Done and Error Interrupt Enable Status (Bit 6 of Register A) - The Job Done and Error Interrupt Enable status bit can be loaded with a DPLO, or DPLF instruction. When this bit is set, the JOB DO NE flag and the ERROR flag are enabled for the interrupt system. 3.2 SEQUENCE OF OPERA TIO N 3.2.1 Write Function To transfer data from the PDP-15 Memory to the RP02 Disk Pack, a Write function must be executed (see Figure 3-5). This is done by loading the RP15 Word Count Register with the 2 1s complement of the number of words to be written on the disk; then loading the RP15 Cylinder, Head, and Sector Address Registers with the location of the disk at whi ch it is to be written. Next, the initial address in memory of the data to be transferred is loaded in the Current Address Register. The ATTENTION INTERRUPT ENABLE and JOB DONE/ERROR INTERRUPT ENABLE are also set, depending on the type 3-12 @ ® INSERT INITIAL MEMORY ADDRESS INSERT DI SK ADDRESS \ I CURRENT ADDRESS REGISTER (17 BITS) CYLINDER ADDRESS REGISTER (7 BITS) ! \ HEAD ADDRESS REGISTER (5 BITS) WORD COUNT REGISTER (18 BITS) I RP15 SECTOR ADDRESS REGI STER (4 BITS) STATUS REGISTER A (9 BITS) CONTROLLER CD INSERT 2's COMPL. OFNO.OF WORDS \ ® INSERT FUNCTION a "GO" 09-0339 Figure 3-5 Insert and Execute Phase of interrupt service desired. Finally, the 3-bit octal code of the unit to be used, the 3-bit code of the function to be performed (Write), and the GO bit are set in Status Register A bits 0-8. This provides the GO signal to the RP15, instructing the controller to: a. Write the number of words, specified by the Word Count, from memory, starting with the initial memory address, which is specified by the Current Address Register, onto the disk at the location specified by the Cylinder, Head, and Sector Address Registers. b. When it is accompl ished, raise the JOB DO NE flag. c. If any errors are encountered in the process, raise the appropriate error flag and shut down. NOTE When loading the function and unit registers with a DPLF, if it is desired to inspect the selected unit status before the function is executed, the GO bit (bit 8 of Status Register A) may be left unset. Then, when ready, the GO bit can be set by the DPLO instruction, at whict time the RP15 will begin executing the instruction. When the function is loaded and the GO bit set, an 18-bit word is taken from memory and paralleltransferred through the I/O bus to the RP 15 Buffer Register, where it enters bits 18-35 (see Figure 3-6). This is designated the liB II half of the Buffer Register. A request is issued for another 18-bit word, while the first word is shifted to Buffer Register IIAII (bits 0-17), and the second word is loaded into bits 18-35. Each 18-bit word transferred from memory into Buffer Register IIBII increments the Word Count and Current Address Regi sters • 3-13 PDP-15 COMPUTER RP15 CONTROLLER MEMORY 18 BITS SINGLE CYCLE CONTROL 35 18 1/0 BUS 18-BIT WORDS BITS ,-- L-. CYLINDER ADDRESS REGISTER - 17 I I I I R E G 8 BITS F CYLINDER COMPARATOR R E G 4 BITS COMPARE -- I 0 T 5 BITS F F E R S H I SECTOR ADDRESS REGISTER B U 18 I I HEAD ADDR. REGISTER I I I I I I+- 14-- 35 35 I I I I I I I ¥ 36 36 BITS BITS I I I I I I I I I I I L 0 N G P A R A R E G I 0 0 8 BITS WRITE DATA COAX RP02 DISK PACK DRIVE HEAD SELECTION SELECTED UNIT CYLINDER ADDRESS REGISTER "HEADER" VIA RD DATA COAX 09-0338 Figure 3-6 WRITE Function, SEEK State During the time that data are being assembled from memory, a disk address comparison is made to determine if the heads require moving to another cylinder. A cylinder comparator within the RP15 looks at the Selected Unit Cylinder Address Register and checks it against its own Cylinder Address Register to determine if a change is required and in what direction. If they do not compare, a Seek function is performed until comparison is reached, at which time the RP02 sends back an "attention" signal indicating that the heads are now positioned in the proper cylinder. 3-14 On receipt of lIattention II, the proper head is selected by the Head Address Register, into which the desired address was previously loaded. This enables the head to begin reading header words from the disk. NOTE Although a Write function is being executed, the Read state must be enabled to find the proper sector. The proper sector is found by sensing sector pulses that come from a notched arrangement on the bottom of each disk pack. These pulses are the only means of timing sent back from the disk. When the sector pulse is received, the controller reads the preamble synchronization field of zeros which is used to lock in a phase-locked VFO within the RP15. This is followed by a IIcue ll bit (1) to signal the beginning of the header. As the header is read, it is compared with the desired address previously inserted in the RP15. If it does not compare, the process repeats on succeeding sector pulses until comparison is found, at which time the controller readies itself to begin writing following the header word. When the header is read, and during the gap period, the Read winding in the head is disabled and the Write winding is enabled. The controller then writes the post-header sync area consisting of 147 10 of zeros followed by a 1 bit. At this time, the 36 bits assembled in the Buffer Register are parallel- bits transferred into the Shift Register and then XORed into the Longitudinal Parity Register (LPR) from the Shift Register (see Figure 3-7). The 36 bits are then serially shifted (from bit 36 to bit 0) out onto the disk. As these bits are shifted out, each 1 bit complements a parity generator. As the last bit is shifted out, the resultant odd parity bit for that word is put on the disk in the 37th bit position and the cycle repeats. The next two data words, already loaded in the Buffer Register, load the Shift Register in two 18-bit bytes, are XORed into the LPR, and are also shifted out onto the disk in a steady flow of 128 36-bit words. At that time, the odd parity contents of the LPR (accumulated XOR of all 128 36-bit words, bit-for-bit) are transferred into the Shift Register and then out onto the disk as the 129th word, passing through the Bit Generator that generates odd parity for that parity word. If the Word Count has not as yet overflowed (more than one sector required for the entire transfer), the previous process repeats as the controller goes back into Read state, the next sequential header is compared, and the next two 18-bit data words fetched from memory are transferred. If the Word Count has overflowed, the operation is terminated and the controller is shut down. 3-15 PDP-15 MEMORY LONG. PARITY REG. DATA WORD #3 ONE RP02 DATA WORD .....;;;::::;:;=;;;..---- DISK 09-0337 Figure 3-7 WRITE Function, Transfer/Write States 3.2.2 Read Function To transfer data from the RP02 Disk Pack to memory, a Read function must be executed (see Figure 3-5). This is done by loading the RP15 Word Count Register with the 2 1s complement of the number of words to be read from disk, then loading the RP15 Cylinder, Head, and Sector Address Registers with the location on disk at which it is to be found. Next, the initial address in memory to which that data are to be transferred is loaded in the Current Address Register. The ATTENTION INTERRUPT ENABLE and JOB DONE/ERROR INTERRUPT ENABLE are also set, depending on the type of interrupt service desired. Finally, the 3-bit octal code of the unit to be used, the 3-bit octal code of the function to be performed (Read), and the GO bit are set in Status Register A bits 0-8. This provides the GO signal to the RP15, instructing the controller to a. Read the number of words, specified by the Word Count, into memory starting with the initial memory address, which is specified by the Current Address Register, from the disk beginning at the location specified by the Cyl inder, Head, and Sector Address Registers. b. When this is done, raise the JOB DONE flag. c. If any errors are encountered in the process, raise the appropriate error flag and shut down. 3-16 At this point, a disk address comparison is made, as described under the Write transfer sequence in Paragraph 3.2.1. Once comparison is found, the read head ignores the indeterminate information in the gap area, and is reenabled to read the data following the data IIcue II bit at the end of the VFO Data Sync Area (see Figure 3-2). A 36-bit word is then read from disk, serially assembled in the Shift Register (see Figure 3-S), parallel-transferred to the Buffer Register, and XORed into the LPR to check longitudinal parity. Each 36-bit word transferred from the Shift Register to the Buffer Register increments the Sector Word Count. When memory time is granted, the word is transferred to memory as two lS-bit bytes; for each lS-bit word transferred to memory, the Word Count and Current Address Registers are incremented. Parity, Sector Word Count, and Word Count are checked in the same manner as in Write (see Paragraph 3.2.1). When Word Count overflows, the transfer is understood to be complete and the controller shuts down. Any error along the way is flagged. 0 PDP-15 MEMORY L 0 N G. DATA P A R. ¥ R E G. 35 DATA WORD#8 DATA ONE RP02 L\ DATA WORD #11 <: , ~;;;;;;;;;;;;....- DISK Figure 3-S 09-0336 READ Function, Read/Transfer States 3.2.3 Read All Function A Read All function is executed by first loading the RP15 Word Count Register with the 2 1s complement of the words to be read from the disk. In Read All, header words are read and transferred; they must be included in the word count calculation. Next, the Cylinder, Head, and Sector Address Registers of 3-17 the RP15 are loaded with one sector less than the true location on the disk at which the data are to be found. The initial address in memory to which these data are to be transferred is loaded in the RP15 Current Address Register. ATTENTION INTERRUPT ENABLE and JOB DONE/ERROR INTERRUPT ENABLE are also set, depending on the type of interrupt servi ce desired. Finally, the 3-bit octal code of the unit to be selected, the 3-bit octal code of the function to be performed (Read All), and the GO bit are set in Status Register A bits 0-8. This provides the GO signal to the RP15, instructing the controller to, a. Read the number of words and headers, specified by the Word Count, into memory, starting with the initial memory address, which is specified by the Current Address Register, from the disk, beginning at the location following that specified by the Cylinder, Head, and Sector Address Registers. b. When this is done, raise the JOB DONE flag. c. If any errors are encountered in the process, raise the appropriate error flag and shut down. At this point, the cylinder comparator checks head positioning and, if necessary, the RP 15 enters a Seek operation. Once comparison has been found, the Read state is entered. When the desired Header Address is found, a header compare is indicated; since the specified address is one less than the true address, the data field associated with the header found is ignored. Then, on receipt of the next sector pulse, the read heads are turned on and every header and data field are read until Word Count overflows. These fields are serially assembled in the Shift Register, parallel-transferred to the Buffer Register, XORed into the LPR, and transferred to memory in 18-bit bytes in the same manner as Read, except that both header and data words are transferred (see Figure 3-9). In this function, because the address registers are loaded with one less than the true address, the method of incrementing these registers is modified. In other functions, the increment to head address is given on the sector address transition from eleven to zero, in Read All (and Write All) increment to head address is given on the ten to eleven sector address transiti on. At the end of each sector, word count is checked. When overflow is indicated, transfer to memory is stopped. If this should occur in the middle of a sector, the remainder of that sector is read for parity purposes, but is not transferred to memory. At the end of that sector, the RP 15 wi II termi nate the operation. Any error along the way is flagged. 3.2.4 Write All Function A Write All function is loaded in the same manner as a Read All function. At GO time, the decision to Seek or not is made. If a Seek is not necessary, the Read state is entered immediately. If cyl inder compare is not generated, Seek is performed before entering Read. 3-18 PDP -15 MEMORY 35 o 18 BIT WORD 18 BIT WORD IGNOREO { - - .:l~.,-.: :. 09-0424 Figure 3-9 READ ALL Function, Transfer States The Read state is entered in Write All simply to find the specified header that represents true sector address minus one (see Figure 3-10). When the header is found, the data field associated with that header is ignored but, at the next sector pulse, the RP15 enters the Write state and writes everything in that sector including pre-header sync, header, post-header sync, data field, and longitudinal parity. If, at the end of that sector, the word count has not overflowed, the controller remains in the Write state. When the next sector pulse is received, the RP 15 writes another entire sector. When Word Count overflows, transfer from memory ceases. If overflow occurs in the middle of a sector, the controller wi II fi II out that sector with zeros, for parity purposes, and then terminate. 3.2.5 Write Check Function The Write Check function is a combination of the Write and Read functions. As far as memory is concerned, the Write Check function is identical to Write. As far as the disk is concerned, it is identical to Read. Data words are transferred from the PDP-15 to the RP 15 and, at the same time, are read from the RP02 and transferred to the RP 15 (see Figure 3-11). In the RP 15, the two words are compared bit-for-bit. 3-19 a L a N WORD 129 G. p A R. .--+-----¥ 18 BIT WORD a 17 18 35 SHIFT REGISTER 18 BIT WORD 18 BIT WORD 18 BIT WORD LOCATED 09-0422 Figure 3-10 WRITE ALL Function, Transfer States Discrepancies raise a status bit called WRITE CHECK ERROR, which results in the appropriate interrupts. Data remain unchanged in memory, as well as on the disk. 3.2.6 Idle Function The Idle function is the no operation (NOP) state of the control and can be executed by loading its octal code into the function register. The Idle function is also entered when the PDP-15 is powered up, the I/O Reset key is depressed on the PDP-15 Console, a CAF (CLEAR ALL FLAGS) instruction is issued, or a DPCF instruction is issued. 3.2.7 Seek Function The Seek function is executed by loading its octal code into the function register. The purpose of the Seek function is to position the heads of the selected unit at.the cylinder address specified by the Cyl- 3-20 LONG. PAR. REG. ¥ weE 1 < 4 - - - - - ; I . . . . . - - - - r - -.... I I DATA WORD #0 I DATA WORD;16 1 I ,...-----'---, DATA WORD #2 DATA WORD #3 09-0423 Figure 3-11 WRITE CHECK Function, Transfer States inder Address Register. When a Seek function is executed, the unit attention line is cleared (provided the heads are not already positioned). This unit attention line is again raised when the Seek has been completed or 100 ms have expired and the Seek was unsuccessful. If the Seek is unsuccessful, a status line called SELECTED UNIT SEEK INCOMPLETE is raised and the appropriate interrupts occur. When a Seek function is successfully completed, the SELECTED UNIT READY status line is set. 3.2.8 Recalibrate Function The Recalibrate function is executed by loading its function code into the function register. The purpose of the Recalibrate function is to recover the head position after a SELECTED UNIT SEEK INCOMPLETE. When this function is completed, the heads are placed at cylinder 000 and UNIT ATTENTION 8 is raised with SELECTED UNIT READY. 3-21 3.3 PROGRAM LOOP The following program loop may be used to debug any execute-type function. The loop repeats the function selected in the data switches and ignores all errors. Data patterns should be loaded from the data switches starting at memory address 1000 , prior to the start of the program. If the pattern is 8 fixed, the REPT and DEPOSIT NEXT switches can be used. The 2 1s complement word count and the disk address should be loaded into memory addresses 200 and 201 , respectively, prior to starting the 8 8 program. 100/ 703302 CAF /CLEAR ALL FLAGS 200200 LAC WC /PLACE WORD COUNT INTO THE AC 706364 DPWC /LOAD THE WORD COUNT REGISTER 200201 LAC DA /PLACE DISK ADDRESS INTO THE AC 706304 DPLA /LOAD THE DISK ADDRESS 200202 LAC CA /PLACE CURRENT ADDRESS INTO THE AC 706344 DPCA /LOAD THE CURRENT ADDRESS 750004 LAS /GET THE FUNCTIO N UNIT, AND GO /BIT FROM THE DATA SWITCHES 706464 DPLF /LOAD THE FUNCTION REGISTER 700314 10RS /READ I/O STATUS 500203 AND OF /AND BIT 12 OF THE 10RS WORD /BIT 12 IS THE DISK FLAG 200/ 740200 SZA 600111 JMP .-3 706341 DPSJ 600115 JMP .-1 /WAIT FOR JOB DONE 600100 JMP 100 /START OVER /WASTE 4 ~s 000000 /Wc - WORD COUNT 000000 /DA - DISK ADDRESS 010000 /CA - CURRENT ADDRESS 000040 /BIT 12 - DISK FLAG The above routine may also be used for initiate-type functions (with the exception of IDLE), by replacing the DPSJ instruction with a DPSF. 3-22 CHAPTER 4 ORA WING CONVENTIONS 4.1 FLOW CHART SYMBOLOGY The flow charts presented have been prepared in accordance with conventions, all of which may not be familiar to the reader. In the flow diagrams, lines indicate flow; where arrows are not provided, the flow is presumed to be either down or to the right. Wherever a name is enclosed within an oval, a pulse amplifier is indicated. A line leaving the bottom of an oval indicates continuation of flow of control; a line leaving the right side of the oval indicates other actions caused by this pulse. Horizontal lines that are separated by a time specification indicate delays. The time given is measured through the delay only, and does not include delays through associated gating and pulse amplifier circuits; the time delay of a given operation cannot be determined by simply adding the delays specified. 4.2 BLOCK SCHEMATIC SYMBOLOGY In the RP15 print set, each logic block schematic has a coordinate system to aid in locating gates etc. Coordinates are numbered from right to left, horizontally from 1 to 8, and lettered from bottom to top vertically from A to D. A label at print coordinate A-1 identifies the logic diagram. The label has three parts: a. Print name - e.g., Status Control #2 b. Print size and type - e.g., D-BS which means D size, Block Schematic. c. Print number - e.g., RP 15-0-1 0 which means Print lOin the RP 15 print set. Connection dots are never used in block schematics. Instead, connections are shown by lines that stop on the line to which they are connected. lines that cross are not connected. 4.3 LOGIC MODULE SYMBOLOGY The logic modules used in the RP15 are DEC M-series, which is the integrated circuit, positive logic seri es • Voltages used are: 4-1 lOW(l) = OV (OV to +0.4V) HIGH (H) = +3V (+2 .4V to +3.6V) MIl-STD-806B logic symbology is used. The gating symbols use small circles at the inputs of gates to indicate that a low signal activates the function. Absence of a circle indicates that a high signal activates the function. The presence or absence of a circle at the output of a gate indicates that the output is low (l) or High (H), respectively, when the gate has been activated (its output is true). A gate's output is false if it is at a voltage different from that shown by the gate's polarity indicator (presence or absence of circle). Suffixes l or H indicate the low or high level of a signal when it is true or enabled. A low output polarity indicator from a gate directly connected to a high input polarity indicator of another gate indicates that the input of the fed gate exists only when the output from the feeding gate is not true. The same holds for the opposite set of conditions. Boolean functions are symbolized as follows: or * = logical AND + or V = logical OR (inclusive) ¥ = Exclusive OR - = logical negation (the vinculum is used only for expressions in text) The most commonly used gating symbols are the NAND (Figures 4-1, 4-2), NOR (Figures 4-3, 4-4), and Inverter (Figures 4-5, 4-6). Each figure shows both the symbol and a Boolean expression of the logical operation it performs. Some of the logic gates are made up of combinations of the basic functions. The operation of these gates can be determined by the combined use of the basic logical relationships (Figure 4-7). Figures 4-8, 4-9, and 4-10 illustrate the types of flip-flops used in the RP15. The flip-flop in Figure 4-8a requires a high data input when clocked to set; the one in 4-8b requires a low data input to be set. The D-type flip-flop is drawn to agree with the voltage level of the data input necessary to set it. Figure 4-9 shows the J-K flip-flop. This flip-flop has direct set and reset inputs and clock and clockgated set and reset inputs. If both gated inputs are high when the flip-flop is clocked, the flip-flop will complement. Figure 4-11 is a representation of the variable clock type M401. The flip-flop in Figure 4-10 is a set-reset flip-flop. A typical pulse amplifier, as used in the RP15, is shown symbolically in Figure 4-12. Figures 4-13 through 4-16 show other circuit symbols used throughout the RP 15. Each logic symbol is designated alphanumerically as to the following information (see Figure 4-17): 4-2 a. Type (M 112) b• Locati on (L 18) c. Input pins on specific module (P 1, R1) d. Output pin (Sl). Most flip-flop modules include a name in their designation (see Figure 4-18), but synchronizing flipflops do not (see Figure 4-19). In the RP15 schematics, a mnemonic convention enables the reader to identify the source print of every signal appearance. Examples are defined in the following: ~ Signal is generied ~ . Actual signal name on Dwg RP15-0-19 e~EAD ALL + WRITE ALL, Source Dwg / "' Actual signal name / - e~EAD ALL +~RITE ALL, Indicates the. NOT I form 0 f t he signa ' " Dwg Source ". Actual signal name When a signal originating from a flip-flop is inverted, the signal name is often changed to avoid possible confusion about where the signal actually originated (Figure 4-20). 4-3 A A L = D - - - xx H A A H = D - YY L BB L BB H AA U'BB L= XX H Figure 4-1 AA H>I'BB H =YY L 15-0068 Figure 4-2 NAND Gate (M 112) C C L = D - YY H C C H = D - xx L DO L DO H AA H Figure 4-4 NOR Gate (M112) ---(>- NOR Gate (M 113) BBL-{>-BBH AA L B B L· BB H AA H = AA L Figure 4-5 15-0068 CC L + DO L • YY H CCH+DDH=XX L Figure 4-3 NAND Gate (Ml13) Figure 4-6 Inverter (M 111, M611) ::~~ xx Inverter (M 111, M611) H CC L DD L (AA L+BB Ll*(CC L+DD L)· xx H ::~~ xx DATA INPUT CLOCK INPUT DATA INPUT CLOCK INPUT L c a CC H DO H CLEAR- (AA HIIBBH)+(CC HttDDH)= xx L Figure 4-7 b Basic Logic Relationships (M 121) Figure 4-8 GATED ( SET INPUTS D Flip-Flop - Edge Triggered (M216) 1~~~T=U1 CLOCK INPUT GATED ( RESET INPUTS 15-0068 Figure 4-9 15-0068 J-K Master-Slave Flip-Flop (M204) 4-4 RESET INPUTS Figure 4-10 R a R-S Flip-Flop (M203) TRIGGER INPUTS Figure 4-11 Variable Clock (M401) {~ H Figure 4-12 OI)TPUT Pulse Amplifier (M602) ENABLE INPUTS DECODING INPUTS INPUT ---{:L Figure 4-13 OUTPUTS OUTPUTS 15-0069 I/O Bus Receiver (M510) 15-0069 Figure 4-14 Binary to Octal Decoder (M161) (W028, W850) (G775) ~(M3121 ~(M3111 Figure 4-15 15-0069 15-0069 Delays Figure 4-16 4-5 Connectors T2 52 NAME TYPE OF MODULE LOCATION OF MODULE 15-0443 Figure 4-17 P1 Nl NAND Gate CLR HEAD Flip-F lop U1 D M216 D12 C 0 R1 Figure 4-19 Figure 4-18 51 RP08 DATA GATE (0) L N 1 P1 RP08 CLOCK GATE H 15-0444 15-0445 Synchronizing Flip-Flop Figure 4-20 4-6 Signal Name Changes CHAPTER 5 PRINCIPLES OF OPERATION AND HARDWARE DESCRIPTION 5.1 GENERAL The principles of operation of the RP15 are discussed from the hardware standpoint. A detailed block diagram followed by circuit descriptions of the functional blocks are included. In these discussions a knowledge of the PDP-15 I/O Bus, the Data Channel timing diagrams, and the RP02 Disk Pack operation is presumed. Reference is made to some undefined control signals; for the most part, these signals are self-explanatory and are defined when the control logic for that register is described. 5.2 DETAILED BLOCK DIAGRAM A detailed block diagram of the RP15 Controller is shown in Figure 5-1. This diagram serves a dual purpose by first showing the interrelation of all blocks and then providing a directory to text. The numbers appearing in each block refer to the number of the paragraph that describes that block in detai I. 5.3 SELECTING THE CONTROLLER (lOT Selection) The PDP-15 selects the RP15 Controller through its lOT selection circuit (see Figure 5-1 and Drawing RP15-0-20). The circuit comprises an AND and OR gate matrix configured to decode six device select bits (corresponding to bits 6 through 11 in the MB) and two subdevice bits (corresponding to bits 12 and 13 of the MB) coming from the PDP-15 I/O Cable. The device select codes, which are fed in as DSO-5, are ANDed in two places to yield 63 and 64 8 8 (decoded as SEL XX Land SEL YY L, respectively). These two signals are ORed to produce DISK SEL H. The signal DISK SEL H is then ANDed with IOP2 (B) H to produce RD RQ L. The SEL XX and SEL YY signals are also inverted to condition two sets of AND MATRIX gates. The subdevice select codes are decoded to produce SUB DEV 00-11 which also conditions both sets of AND MATRIX gates. The outputs of the first column in the matrix are ORed and then ANDed with IOP1 (B) H to produce a SKP RQ L. Column two and column three are conditioned by IOP2 (B) Hand IOP4 (B) H, respectively, to produce the remaining RP15 instructions. 5-1 FROM PDP-15 (5.27) I10 BUS XX (00~17) 5.21 - 8 > - - - I O B XX (00-17) I/O SYNC- I - I -110 SYNC (B) I rop X (1,2,4) - I CA CONT DPWC I I/O PWR CLR (B) ~IOP (B) X (1,2,4) SU CAR XX(1) (00-07) BR 5.18 SR 5.19 LPR DCH CONTROL ~----~ WC a I/O PWR CLR - 4 FROM RP02 (5.26) SU CAR XX (00-07) EC I 5.21 SURO 4 - DPCA I - SU READ ONLY SURDY 4 - - SU READY SUOL +- - SU ON LINE SU INDEX API1 GR- - APr GR (B) SUIP +- - RD STATUS- - RD STATUS (B) SUFU +- - SU FILE UNSAFE - DSX (B) (0-5) SUSI +- - SU SEEK INCOMPLETE - - . 110 RUN (1) SUEOC +- - SU END OF CYL INDER - - . SOX (B) (0, 1) SUSP +- - SU SECTOR OS XX (00-05) - IIO RUN ( B ) - V SO XX (00-01) - DCH GR 5.25 DPLM ATT XX DCH GR (B) BUS MUL TIPLEXOR (5.4) API I RQ ~ SKIP RQ.-READ RQ +PROG INT RQ +SING CY RQ +- I I - I I I TO RP02 (5.26) SU CAR (DPRU) wc (DPRW) CA (DPRC) SRA (DPRSA) SRB (DPRSB) CAR-HAR-SAR (DPRA) MR (DPRM) SR SU XX DPSJ DPSE DPCS I DPCF FUNCTION CONTROL 5.22 (SRA BITS 0-8) SELECT UNIT XX (00-071 WRT BIT (1) WR ITE DATA COAX XX (00-07) SU xx (00-07) API RQ (1) DPLO DPLF DPCN DPCF SKP RQ RD RQ PI RQ DCH RQ (1) TAG GATE 1 SET HEAD 5.15 SET HEAD EN a TAG ' - - - - - - - - - + t BUS LI NE CONTROL DCH RQ (1) SET CYLI NDER DPOSB DPOU DPRSS DPSF DPRU DPOSA DPRSA DPLZ DPCN API ENA TAG GATE 1 SEEK (1) RQ IN ~ (00~07) ~ (5.10) WRITE PROTECT LOGIC DCH RQ I/O ADR 12,13, 15 ATTENTION XX (00-07) t---------------------- READ DATA COAX (00-07) TO PDP-15 (5.27) 1/0 BUS XX (00-17) ~ (00-07)~ DPLA DPCA DPOC DPRC DPOA DPRA DPCS 8Ww DPLM DPSE DPOM DPRM TAG GATE 2 CONTROL BUS GATE 2 CAR XX (1) (00-07) DCH ENA (B) CAR STB 1/0 ADR XX CA XX (1) (SKIP RQ..-CA 01 WR RQ .... CA 02) DSX (B) (0-5) sox (B) (0, I) HAR XX (1 ) (00-04) UNIT BUS (00-07) HAR STB RD STATUS (B) liD BUS 12 DISK FLAG xx BUS GATE 02 (CONTROL SIGNALS) 15-0514 Figure 5-1 RP15 General Block Diagram 5-3 5.4 STATUS MONITORING AND DCH DATA (Bus Multiplexer) Monitoring of RP15/02 status, and data to the PDP-15 Single-Cycle Data Channel, is transferred through the RP15 Bus Multiplexer shown in Figure 5-1 and Drawings RP15-0-42,-43,-44, and -45. The various instructions received from the lOT selection circuit are inverted and then utilized to enable l8-bit sets of AN D gates that contain information to be loaded into the PDP-15 Accumulator. The instruction DPOW (OR the Word Count Register into the AC) places WCOO-17 (1) H on BUSOO-17 L where the result is then ORed into ACOO-17. The instruction DPOC (OR the Current Address Register into the AC) places CAOO-17 (1) H on BUSOO-17 L where the result is ORed into the ACOO-17. The instruction DPOSA (OR Status Register A into the AC), which is decoded as DPOF, places the various bits of the Function Register, the Unit Register, and Status Register A on BUSOO-17 L where the result is ORed into ACOO-17. The instruction DPOSB (OR Status Register B into the AC), which is decoded as DPOS, places the various bits of Status Register B on BUSOO-17 where the result is ORed into ACOO-17o The instruction DPOA (OR the Cylinder, Head, and Sector Address Registers into the AC) places the 8-bit Cyl inder Address Register on BUSOO-o7 L, the 5-bit Head Address Register on BUS08-12 L, and the 4-bit Sector Address Register on BUS14-17 L; where the result is ORed into ACOO-17. The instruction DPOM (OR the Maintenance Register into the AC) places the 6-bit Maintenance Register (MROO-05) on BUSOO-05 L where the result is ORed into ACOO-05. The instruction DPOU (OR the Select Unit Cylinder Address Register into the AC) places the 8-bit Selected Unit Cylinder Address Register (SUCAROO-07) on BUS10-17 L where the result is ORed into AC10-l7. The signal DCH DATA L is generated, as shown on Drawing RP15-0-45, during single-cycle breaks on lIin II transfers to memory (Read and Read All functions). This signal places the first 18 bits of the Buffer Register (BROO-17) on BUSOO-17 L where they are transferred via the I/O bus into the PDP-15 Memory. NOTE On Drawing RP15-0-45, the pull up resistors used on the collector ORing of the M149 Bus Multiplexer Module produce the standard logic level used in M-series logic. 5-5 5.5 SELECTING THE DRIVE (Unit Register) The RP15 is designed to interface up to eight RP02 units. These units are addressed by a 3-bit register, called the Unit Register (Drawing RP15-0-2l), whose octal content describes the unit presently selected. The octal unit number assigned to a unit depends on its physical location on the bus and is not logically assignable. Unit addresses are coded OOS through 07S. The Unit Register is decoded as shown in Figure 5-2. The output of the M622 Bus Driver is wired to the appropriate signal cable that connects to the RP02 unit (see Drawing RP15-0-53). I- - - - - - - -T :07L I I I I I SU 07 H t3V SU 07 L SU 06 H SU 06 L UR 00 (1) H SU 05 H SU 05 L ~~ ~: ~ UR 01 (1) H SU 03 H SU 03 L SU 02 H SU 02 L SU 01 H SU 01 L SU 00 H UR 02 (1) H I I I SU 00 L I I I O I I I SELECT UNIT 07 L I I I I II I I SUO~O I RP15-0-09 L ) - - --l SELECT UNIT 00 L RP15-0-46 -----~------------ I I J 15 -0447 Figure 5-2 5.6 Unit Selection Circuit SELECTED UNIT CYLINDER INTERROGATION (SUCAR) When a system is equipped with more than one RP02, it is often desirable to know the location of the heads in anyone unit. Their position can be determined by using the Selected Unit Cyl inder Address Register contained in each RP02: Step Procedure Select the unit to be interrogated. 2 Read the contents of that S-bit register into the accumulator. Step 2 is allowed only when it is permissible to change the Unit Select Register and the unit being interrogated is not executing a previously given command. The SUCAR is not a hardware register within the RP15 but is received from the unit presently selected via the unit bus cable. (See Figure 5-3 and Drawings labelled on the figure.) 5-6 T-------l I I I I I I I ~-t-- SU ~-+-- SU CAR 07 L CAR 06 L ~-+-- SU CAR 05 L ~-+--SU CAR 04 L """"::''-+-- SU CAR 03 L e---:--+-- SU CAR 02 L ~-+-- SU CAR 01 L ......,...,-+-- SU CAR 00 L I L Figure 5-3 5.7 I I I • • • • • • • • • I : I RP15-0-53 -y-- _~ SU CAR 07 (1) L SU CAR 07 L SU CAR 07 (1) H I I I • I I ___ ~ SU CAR 00 (1) L SU CAR 00 L~SU CAR 00 (1)H 1.. RP15-0-48 I J 1!I-044A SU Cylinder Interrogation Circuit ADDRESSING THE PACK (CAR, HAR, and SAR) The RP02P Disk Pack consists of 11 evenly spaced recording platters mounted on a single shaft. Because of this precarious arrangement, the top- and bottom-most surfaces are not used for recording; instead, a metal disk is attached to the bottom surface. The disk contains 20 evenly spaced notches and a twenty-first notch called the Index. A circuit, designed to detect these notches, rejects every other one of the twenty notches, thereby dividing the disk pack into ten equal sectors. These sectors are addressed by a 4-bit register called the Sector Address Register (SAR) (see Drawing RP15-0-30). The sector addresses are coded 00 through 8 11 , which leaves illegal codes 128 through 178 that may appear in the Sector Address Register. 8 When detected by the controller, illegal codes raise an error flag that results in the appropriate interrupts. A separate Read,/VVrite head is provided for each of the twenty inner recording surfaces. These heads, mounted in parallel and in vertical alignment to each other, are attached to a common head tower. The heads are selected by a 5-bit register called the Head Address Register (HAR) (see Drawing RP15-0-29). Head addresses are coded 00 through 23 • When detected by the controller, illegal 8 8 codes 248 through 378 raise an error flag that results in the appropriate interrupts. The position of all heads, vertically aligned with respect to the vertical axis that passes through the center of all surfaces, is called a cylinder. Head positioning is controlled by a linear positioning motor and detenting mechanism that is designed to stop the heads in 203 different cylinders. These cylinders are coded 00 through 3128 from the outer-most cylinder to the inner-most cylinder, respec8 tively. Cylinders are addressed by an 8-bit register called the Cylinder Address Register (CAR) (see 5-7 Drawing RP15-0-28). When detected by the controller, illegal codes 313 through 3778 raise an error 8 flag that results in the appropriate interrupts. The intersection of a cylinder, head, and sector address defines a unique sector that is the smallest addressable unit in the' system. Each sector has a data field of 128 36-bit words plus a header word that uniquely defines that sector. A word constitutes two PDP-15 data words during Read or Write operations. The decoding circuits for illegal cylinder, head, and sector addresses are shown in simplified form in Figure 5-4. Note that the AND gate that combines CAROO (1) with CAROl (1) enables all other inputs in the NECA equation; NECA must be a minimum of 3xx . This signal is then ANDed with CAR04 (1), 8 CAR06 (1), and CAR07 (1) to produce an equation stating: 1 CAROO (1) --..J 1 r x x 1 ) x 1 CAROl (1) CAR04 (1) CAR06 (1) ------~ CAR07 (1) _ _ _ _ _ _ _----J is illegal. This code includes the number 313 (among others). Note also that the conditions for the numbers 8 314 , 315 , 316 , and 3178 are decoded by the AND of the original equation [CAROO (1) and 8 8 8 CAROl (l)J and CAR04 (1) with CAR05 (1). 11 CAROO (1) --..J r xx 1 xx ) CAROl (1) CAR04 (1) CAR05 (1) ---------1 Two inputs remain which decode the numbers 320 to 337 , inclusive, and all numbers equal to, or 8 8 greater than, 340 . They are: 8 1 1 x CAROO (1) ~ 1 x j ) x x CAROl (1) CAR03 (1) 5-8 x and CAROO (1) CAROl (1) +j I 1 x x x x x CAR02 (1) ----------- . . . . -------1 CAR 04 (1) H - CAR 06 (1) H - - - - - r CAR 07 (1) H ----~J CAR 02 (1) CAR 03 (1) --.---t-, . ,/ H "l{>-NECAH CAR 04 (1) H ---1----......_ CAR 05 (1) H - - CAR 00 (1) L CAR 01 (1) L HAR 01 (1) H NEHA H HAR 00 (1) H HAR 02 (1) H NEHA L NESA L SAR 01 (1) H -~ 1 - SAR 00 (1) H SAR 02 (1) H L {>- NESA H ~ ___ _ 1~-0449 Figure 5-4 Illegal Disk Address Decoding 5-9 In this way, coding covers all numbers from 313 to 377 , inclusive, in the NECA equation. NEHA 8 8 and NESA may be decoded in the same manner. The Cylinder, Head, and Sector Address Registers comprise three incrementing ripple count registers formed from D-Type flip-flops. These registers are preset by DPLA ANDed with the corresponding lOB bit, and are cleared by CLR CAR, CLR HAR, and CLR SAR, respectively. Control logic for the Cylinder, Head, and Sector Address Registers is shown on Drawings RP15-0-28, -29, and -30, respectively. Incrementing the SAR is initiated by signals called SECTOR END L (generated after the completion of each sector) or MAl NT INC SAR L (see Figure 5-5). SECTOR END is conditioned by five signals: WEE (1), LEE (1), WCEE (1), TE (1), and NORMAL H. Any of the first four signals inhibits incrementing of the SAR if a word or longitudinal parity error was accumulated in a sector, or if a write check error or timing error occurred. The fifth signal inhibits incrementing of the SAR if the control is not in the NORMAL mode. When the controller is in the FORMAT mode, therefore, the SAR is not used. RP15- 0-30 CLEAR ~---~------~------~------~+1 ~----------~ CLR (B) L DPLA (B) L ~----~ "'>O--+-- C L R SA R L -CRY L NORMAL H MAINT INC SAR L +3V WEE (1) L ---4:Jr-_ _ LEE (1) L WCEE (I) L TE (1) L - ( ' ) 1 - - - CRY H INC HAR 15-0450 Figure 5-5 SAR Control Logic 5-10 The actual incrementing of the SAR is inhibited if SAROO (1) and SAR03 (1) are both true. This condition produces a signal called CRY H (the NOT condition is shown in Figure 5-5) which indicates that the maximum SAR count has been reached (11 ). If this condition had been true prior to a SECTOR END, the data side of the synchronizing D-Type flip-flop would have been enabled and would have allowed this flip-flop to set at the leading edge of SECTOR END. This flip-flop then enables a pulse amplifier (M606) that generates a pulse at the trailing edge of SECTOR END. This pulse is ORed with CLR (B) Land DPLA (B) L to clear the SAR with CLR SAR L. The process just described allows the SAR to increment from the maximum code 11a to OOa. If CRY H is true before SECTOR END, another decision is made. If the function being executed is not Read All or Write All, then INC HAR H is generated which, in turn, increments the HAR. Note that the SAR now counts from OOa to 11 , and then always back to OOa. At the transition of 11a to OOa' a the HAR is incremented providing the function is Read, Write, or Write Check. The HAR is also incremented during Read All and Write All functions, but only when the SAR contains a count of lOa before SECTOR END. This is done by ANDing READ ALL + WRITE ALL H with SAROO (1) Hand SAR03 (0) H 0 The HAR is shown in simplified form in Figure 5-6. Again, the maximum HAR count is decoded and used to disable incrementing of the HAR. The code is: HAROO (1) H HAR03 (1) H HAR04 (1) H. This is shown in Figure 5-6 in the NOT condition. In addition to disabling the HAR increment, this signal also enables the creation of INC CAR Land CLR HAR L. DPLA (B) Land CLR (B) L are also ORed to produce CLR HAR L. Assuming that the maximum HAR count is not present, INC HAR H (generated on Drawing RP15-0-30) wi II produce the incrementing signal for HAR. The CAR is shown in Figure 5-7. As with the SAR and HAR, the maximum CAR count is decoded and used to disable the incrementing of the CAR. The code is: CAROO (1) H CAROl (1) H CAR04 (1) H CAR06 (1) H. 5-11 -INC CAR L CLR(B)L ~----- CLR HAR L 1..-_---1 +3 V CLEAR DPLA (B) L HAR 00 HAR 01 HAR 02 HAR 03 +1 HAR 04 HAR 00 (0) L HAR 03 (0) L HAR 04 (0) L INC HAR H INC CAR H INC CAR L RP15-0- 29 15-0451 Figure 5-6 HAR, Simplified Schematic RPI5-0-28 END OF PACK H 'x:l~.......- CLR CAR L +3V CLEAR CAR 00 CAR 00 CAR 01 CAR 04 CAR 06 CAR 01 CAR 02 CAR 03 CAR 04 CAR 05 CAR 06 CAR 07 t 1 (0) L.--CJr--__ (0) L (0) L (0) L--CI&-~"': END OF PACK H ~---4~- END OF PACK L 15-04112 Figure 5-7 CAR, Simplified Schematic 5-12 This is shown in the NOT condition in the figure. This code is also used to create END OF PACK H, a signal that indicates to the controller that the physical end of pack has been reached. END OF PACK H is ORed with CLR (B) Land DPLA (B) L to produce CLR CAR L. Assuming that the maximum CAR count is not present, INC CAR H (created on Drawing RP15-0-29) will produce the signal necessary to increment the CAR. The CAR, HAR, and SAR are shown functionally in Figure 5-1. Note the connection between the CAR and the INT & STATUS CONTROL box. This connection represents END OF PACK. 5.S CYLINDER COMPARISON The RP15 Cylinder Comparator is shown in Drawing RP15-0-27 and in simplified form in Figure 5-S. The Cylinder Comparator maintains a check between the controller Cylinder Address Register and the Selected Unit Cyl inder Address Register. This logi c is used to determine if the Seek state should be entered. Each state of every CAR bit is ANDed with the opposite state of the same SUCAR bit. Each AND is ORed to one composite OR that issues -CYL CMPR L until all bits correspond. If CYL CMPR H is true, reading or writing proceeds and the Seek state is not entered. This is described in more detail in Major State Control, Paragraph 5. 14. CAR 00 (1) H SU CAR 00 (0) H CAR 00 (0) H S U CAR 00 (1) H - CYL CMPR H • • • • • • -CYL CMPR L • • • CAR 07 (I) H SU CAR 07 (0) H CAR 07 (0) H SU CAR 07 (I) H RP15-0-27 15-0453 Figure 5-S 5.9 Cylinder Comparator, Simplified Schematic SEQUENCING THE MEMORY (CA) Data transfers between the RP15 and the PDP-15 Memory use the single-cycle data channel. The RP15 contains an lS-bit Current Address Register (CA) that locates each data word transferred in consecutive 5-13 memory addresses. The initial address is specified by loading it into the Current Address Register before the command to execute a data transfer. The Current Address Register is automatically incremented after each data word is transferred from memory. The CA Register is made up of 18 D-Type flip-flops connected as a ripple counter (see Drawing RP15-0-32). NOTE The connection is actually broken in two places for reasons explained under Word Count and Current Address Control, Paragraph 5.21. Each flip-flop is preset by the DPCA signal ANDed with the corresponding lOB (I/O Bus) bit. The entire register is cleared with CLR CA L. Refer to Figure 5-1 for the functional flow position of the Current Address Register. 5.10 COMMANDING THE CONTROLLER (Functional Control - SRA Bits 00-08) The PDP-15 Computer uses the Function Register to tell the controller what function is to be performed. The controller then translates these commands to the drive through the Tag and Bus Line Control described in Paragraph 5.15. The RP15 Function Register is shown in Drawing RP15-0-21 and simplified in Figure 5-9. The register is arranged such that the instruction DPLF is ORed with either DPLO (Load AC 1s) or DPLZ (Load AC Os) to produce FR EN SET L or FR EN CLR L, and two FR strobes (A and B). The FR EN's are ANDed with their appropriate I/O bus bits (00-08) to inputs of JK flip-flops UROO-02, FROO-02, GO, ATD, and DED. These flip-flops are clocked at the trailing edge with one of two strobes; when DPLF is issued, the Function Control will reproduce the contents of I/O bus bits 00-08; when a DPLO is issued, only ls on the I/O bus will be set into the registers; when DPLZ is issued, only Os will be transferred. I/O bus bit 06 can be cleared to produce DED (Done and Error Flag Interrupt Disable), I/O bus bit 07, when cleared, wi II produce ATD (Attention Flag Interrupt Disable). When I/O bus bit 08 is set, it wi II produce GO (Enable Execution of the Function Register); bits 00-02 will load the Unit Register. The Function Register is loaded from I/O bus bits 03-05. The RP15 provides hardware for the performance of eight different functions. These functions can be categorized as either initiate- or execute-type functions (refer to Table 5-1). Initiate-type functions are described as those that require only 4 I-IS of controller time from the time of the command. During this time, the controller is held in the BUSY state. Although a Seek may require 50 ms for completion, the unit selected need only be selected for the BUSY period. Execute-type functions, however, require all the controller's time necessary to complete the function. The controller is BUSY for the entire operation; the unit requested must also be BUSY for the entire operation, and cannot be deselected to begin an initiate-type function. 5-14 RPI5-0-21 FR EN CLR L FR EN SET L rOB 00 L (IOB 03 L) -lOB 06 L FR STB B H -lOB 00 L (-lOB 03 L) lOB 06 L FR EN SET L FR EN CLR L CLR FR L FR EN SET L FREN CLR L IOB 01 L (lOB 04 Ll -lOB 07 L -lOB 01 L (-lOB 04 L) rOB 07 L FR EN CLR L FR EN SET L CLR FR L FR EN SET L lOB 02 L (rOB 05 L) -lOB 02 L (-lOB 05 L) -lOB 08 L FR EN CLR L CLR FR L DPLO L--~~ o P LF L - - ' - - O i FR t--_ _ _ _ _ __ 3=-D-- FR'TB B " D----<~-FRENCLRL DPLZ CLR (B) L L-----4~ CLR FR L 15-0454 Figure 5-9 Function Register, Simplified Schematic Table 5-1 RP15 Function Arrangement Function Code Type Idle Read Write Reca librate Seek Read All Write All Write Check 0 1 2 3 4 5 Initiate Execute Execute Initiate Initiate Execute Execute Execute 6 7 5-15 Functions are selected by loading the 3-bit Function Register with an octal number equal to the function code (refer to Table 5-1). 5.10.1 Idle Function (FR = 0) The Idle function constitutes the NOP state of the controller; it is executed by loading its octal code into the Function Register with a DPLO, DPLZ, or DPLF instruction. The Idle function is also executed when the PDP-15 is powered up, the I/O RESET key on the PDP-15 Console is pressed, a CAF (Clear All Flags) instruction is issued, or a DPCF instruction is issued. 5. 10.2 Read Function (FR = 1) The Read function is executed by loading its octal code into the Function Register with a DPLO, DPLZ, or DPLF instruction. Read transfers data from the RP02 to the PDP-15, starting with the memory location specified by the Current Address Register. Each data word transferred increments the Current Address and Word Count Registers. The contents of the Word Count Register at the beginning of the transfer determine the number of data words to be transferred. When the Word Count Register overflows, data transfer stops. The remainder of the present sector is read and parity is checked before the JOB DONE flag is raised. The Current Address Register contains the address of the last data word transferred plus one. At this point, a Continue may be effected by reloading the Word Count and/or Current Address Registers and issuing a DPCN instruction. 5. 10.3 Write Function (FR = 2) The Write function is executed by loading its octal code into the Function Register with a DPLO, DPLZ, or DPLF instruction. Write transfers data from the PDP-15 to the RP02, starting with the memory location specified by the Current Address Register. Each data word transferred increments the Current Address and Word Count Registers. The contents of the Word Count Register at the beginning of the transfer determine the number of data words to be transferred. When the Word Count Register overflows, data transfer stops. The remainder of the present sector is written with zeros and accumulated parity is written before the JOB DONE flag is raised. The Current Address Register contains the address of the last data word transferred plus one. At this point, a Continue may be effected by reloading the Word Count and/or Current Address Registers and issuing a DPCN instruction. 5.10.4 Recalibrate Function (FR = 3) The Recalibrate function is executed by loading its octal code into the Function Register with a DPLO, DPLZ, or DPLF instruction. The purpose of the Recalibrate function is to recover the head position 5-16 after a Selected Unit Seek Incomplete. When this function is completed, the heads are placed at cyl inder 000 and both UNIT ATTENTION and SELECTED UNIT READY are raised. 8 5.10.5 Seek Function (FR = 4) The Seek function is executed by loading its octal code into the Function Register with a DPLO, DPLZ, or DPLF instruction. The purpose of the Seek is to position the heads of the Selected Unit at that cylinder address which is specified by the Cylinder Address Register. When a Seek function is executed, the Unit Attention line is cleared (provided the heads are not already positioned). The Unit Attention line is again raised when the Seek has been completed or if 100 ms have expired and the Seek has been unsuccessful. If the Seek II unsuccessful, a status line called Selected Unit Seek Incomplete (SUSI) is raised and the appropriate interrupts occur. However, at the successful completion of a Seek function, the Selected Unit Ready (SU RDY) status line is set. NOTE Because the Seek is an initiate-type function, the target unit need only remain selected for 4 I-'s after its execution. A system that has several drives can start Seek operations in chain fashion provided a 4-l-'s hold exists after each Seek is executed. 5. 10.6 Read All Function (FR = 5) The Read All function is executed by loading its octal code into the Function Register with a DPLO, DPLZ, or DPLF instruction. The Read All function is identical to the Read function, except that the Sector Address Register must be loaded with the sector address minus one, and both the header word and data field are read into memory. The Word Count Register should be loaded to include the header word which consists of two data words. Note that "Sector Address Register must be loaded with the sector address minus one ••• II only refers to the sector address and not to any other. For example, if the des ired sector is Cylinder 2} Head 23 Sector 0, Entire Desired Address lIone ll should be subtracted from sector a to give sector minus one as follows: Cylinder 2} Head 23 Sector 11 Load CAR, HAR, and SAR with this. 5-17 Note that "one" was not borrowed from Head 23 as shown below, Cylinder 2 Head 22 Sector 11 DO NOT load CAR, HAR, and SAR with this for a Read All of sector address CYL 2, HD 23, { and SEC O. Note also, when subtracting, that sectors are numbered octally. 5. 10.7 Write All Function (FR = 6) The Write All function is executed by loading its octal code into the Function Register with a DPLO, DPLZ, or DPLF instruction. The Write All function has two subfunctions designated Write All Normal and Write All Format. The applicable subfunction is determined by the position to which the NORMAL/FORMAT switch on the logic panel is set. The Write All Normal subfunction is identical to the Write function, except the Sector Address Register must be loaded with the desired address minus one (see Read All function), and both the Header word and data field are written from memory. In loading the Word Count Register, the header word, which consists of two data words, should be included. The Write All Format subfunction is identical to the Write function, except an entire cylinder is written at a time, and the surface and sector address must be cleared. The entire sector is written, but only those header words required for one cylinder need be in memory. This instruction is used exclusively by the Formatter Diagnostic which initializes disk packs. 5.10.8 Write Check Function (FR = 7) The Write Check function is executed by loading its octa I code into the Function Register with a DPLO, DPLZ, or DPLF instruction. The Write Check function is a combination of the Write and Read functions and is entered in the same way as Write. Data words are transferred from the PDP-15 to the RP15; at the same time, data words are read from the RP02 and also transferred to the RP15. In the controller, the two words are compared bit-for-bit; any discrepancies will raise a status bit called Write Check Error which results in the appropriate interrupts. Data remain unchanged in both memory and disk. The RP15 Write Check Compare circuit is shown in simplified form in Figure 5-10 and Drawings RP15-0-24, -25, and -26. The Write Check Comparator comprises AND and OR gates feeding four ORs which, in turn, feed a common OR. When in Write Check mode, the controller reads back what has just been written on the disk, to make sure that no errors have occurred. To accomplish this check, each state of each BR bit (filled from memory) is ANDed with the opposite state of the same SR bit (fi lied from the RP02); in this way, if all SR bits match a II BR bits, no output is seen from the 5-18 comparator. If any bit state does not match, it results in -WCC H being sent to the Status Control (Drawing RP15-0-10) which is used to raise an error flag and an interrupt. In Figure 5-1, note the arrangement of the Write Check Comparator between the BR and SR blocks. 3R 00 (1) H 3R 00 (0) H BR 00 (0) H -~........ • SR 00 (1) H -weeOO-07L BR 07 (t) H SR 07 (0) H BR 07 (0) H SR 07 (t) H RP15 - 0- 24 BR 32 (1) H SR 32 (0) H BR 32 (0) H SR 32 (1) H - wee H BR 35 (1) H SR 35 (0) H BR 35 (0) H ______ I SR 35 (1) H -wee 16-23L -wee 08-15 L -wee 00 - 0 7 L RPI5-0-26 BR 24 (1) H SR 24 (0) H BR 24 (0) H SR 24 (1) H -wee 24-31 L BR 31 (1) H SR 31 (0) H BR 31 (0) H -..----.... SR31(t)H RPI5-0-25 15-0455 Figure 5-10 5.11 Write Check Compare, Simplified Diagram DETERMINING LENGTH OF TRANSFER 0NC) The length of each record transferred is controlled by an 18-bit Word Count Register (WC). Before the command is given to execute a transfer, this register is loaded with the 2s complement of the number of data words desired in one transfer. Any number from 1 to 262, 144 could be specified as a record 10 10 length, if it were not for the limiting factor of memory capacity. 5-19 In general, the smallest addressable unit is the sector; however, record lengths that 'are shorter than a sector may be transferred. Transfers will start at the beginning of the sector with the remainder of that sector filled with zeros (the unused word positions are wasted). Data transfers can only start at the beginning of a sector. NOTE The above is true also of multiple sector transfers ending within the sector. The RP15 Word Count Register is shown in Figure 5-1 and Drawing RP15-0-31. DPWC presets CD flipflops WCOO-17 from lOB bits 00-17. All 18 bits of the word count can be cleared by CLR WC L. The WC Register is also a ripple count register that can be incremented by INC WC H from the WC and CA Control. This causes the register to count down the desired word count each time a memory transfer occurs. 5.12 MAINTAINING DISK FORMAT (SWC) The RP15 Sector Word Count circuit is shown in Figure 5-11 and Drawing RP15-0-23. This circuit keeps track of the number of 36-bit data words the controller has either read from or written on the disk, and I imits that number to 128 words per sector. -SUSP L X > -_ _ CLR SWC L CLR+DPCS+FUNC DLY L CLEAR SWC 00 SWC 01 SWC 02 SWC 03 SWC 04 SWC 05 SWC 06 +1 - SR TO BR L SWC OVFLO (1) L SWC SWC SWC SWC SWC SWC SWC 00 01 02 03 04 05 06 (1) H +3V (1) H (1) H (1) H (1) H (1) H (1) H +3V INC SWC H DATA FIELD H WLB (1) H CLOCK DLYD H FMT GEN 01 (1) H FMT GEN 02 (1) H RPI5-Q-23 CLR SWC L Figure 5-11 15-04156 Sector Word Counter, Simplified Diagram 5-20 This register is a 7-bit ripple counter incremented by INC SWC H. The 1 states of SWCOO-06 are ANDed to the D-input of the SWC OVFLO (overflow) flip-flop. This flip-flop is set when all seven bits of the SWC are ls prior to INC SWC H. INC SWC H is produced under two conditions, each of which are ANDed and then ORed to produce the signal. In Write, these conditions are WLB (1) H (sets at the end of each word written), CLOCK DLYD H, and FMT GENOl-02 (1) H; at the end of writing each word, the sector word count is incremented. In Read, if DATA FIELD H is true and -SR TO BR L is received (trailing edge of SR TO BR H), the sector word count is incremented. At the end of 128 words, all SWC flip-flops will be on a 1; on INC SWC H, the SWC OVFLO flip-flop will be set. This latches INC SWC H so that when the LPR word is written or read the SWC is not again incremented. CLR SWC L clears both the SWC Register and the SWC OVFLO flip-flop. This signal is produced by the OR of the following: 5.13 -SUSP L (Trailing edge of Selected Unit Sector Pulse) CLR (Power clear, CAF (Clear All Flags lOT 3302), DPCF, or I/O RESET on the PDP-15 Console) DPCS (Disk Pack Clear Status) FUNC DLY (Produced after issuing DPLO, DPLZ, DPLF, or DPCN) PROCESSING THE DATA (BR, SR, and LPR) The RP15 contains three data registers that are not under program control but manipulate data within the controller and provides compatibility between RP02P Disk Packs used on the PDP-15 Computer System and those used on the PDP-l0 Computer System. These registers also provide the effect of double buffering between the PDP-15 and the RP15. 5. 13. 1 Buffer Register The Buffer Register is 36 bits in length. During Write operations data are transferred from the PDP-15, "in two 18-bit words, to the Buffer Register. This transfer is done in two consecutive memory cycles. During Read operations, the contents of the Buffer Register are broken into two 18-bit words that are transferred to the PDP-15 in two consecutive cycles. The RP15 Buffer Register is shown in Figure 5-12 and Drawings RP15-0-33, -34, and -35. The Buffer Register sits between the PDP-15 Processor and the RP 15 Controller. The register is divided into 5-21 quarters with BR STB A H clocking CD flip-flops BROO-08 and BR18-26, and BR STB B H clocking CD flip-flops BR09-17 and BR27-35. These strobes originate in the Buffer Register Control (Drawing RP15-0-13) and are described in Paragraph 5. 18. The BR fl ip-flops are cleared in I ike fashion by CLR BR A Land CLR BR B L which also originate in the Buffer Register Control. - -D - -D 1- BROO ,....---C - -D --C - 1- r-- BR17 BR18 0- T CLR BR A L 1- 0- .---- C T D 1 f-- BR 35 ,....--- COl-- 0- T T BRSTBAH~~~--------~----~~--------~~-----+-+---------4----~ n 9 p 1 I l..4---+--.........~ SNSRH ---+~--1---1_--------~~~+-~+---------~~--~--~------~ ENIOBH---+----~--~--------~--~*-~+_--------1_----~--+_------~--~ ENBRH---+--------~--------~--~--_+~--------~--------*-------_+--_+--_+~ SR 00 (t) H SR18(I)H BR01(1)H SRI7(1)H lOB 00 H SR 35 ( 1) H BR 00 (1) H lOB 17 H 15- 0457 RP15 -0-33,34,35 Figure 5-12 Buffer Register, Simplified Diagram Each BR flip-flop is set by an OR gate of three possible AND gate conditions. One set looks at associated bits in the Shift Register and is enabled by EN SR H. Another set looks at associated lOB bits and is enabled by EN lOB H. The third set of AND gates looks at the 1 state of each comparable bit in the second 18-bit half of the Buffer Register and is enabled by EN BR H. These enabling levels are generated in the Buffer Register Control. In Write operations, lOB bits from the PDP-15 are enabled into the buffer by EN lOB H and strobed by BR ST B A and B, in two consecuti ve memory cycl es (18-b it words). The fi rst word enters BR 18-35 and is transferred to BROO-17 by EN BR H. On the second memory cycle, IOBOO-17 enters BR18-35 and the entire 36 bits are parallel-transferred to the Shift and Longitudinal Parity Registers for further process i ng . In Read operations, the 36 bits, which have been serially assembled in the Shift Register, are paralleltransferred to the Buffer Register by EN SR H and the two BR strobes; from the Buffer Register they are 5-22 transferred to the PDP-15 in two 18-bit words during two consecutive memory cycles. This transfer is done by gating BROO-17 onto the I/O bus via the Bus Multiplexer. When the first word is accepted by the PDP-15 1/0,BR18-35 are shifted into BROO-17 by BR EN Hand BR STB (A and B). Again, BROO-17 are gated onto the I/O bus and the second word is transferred to the I/O. 5.13.2 Shift Register The Shift Register is 36-bits in length. For Write operations, the contents of the Buffer Register are loaded into the Shift Register where they are serialized and transferred to the disk. During Read operations, the serial data from the disk are assembled in the Shift Register and then transferred to the Buffer Reg i ster • The RP15 Shift Register is shown in Figure 5-13 and Drawings RP15-0-36, -37, and -38. The Shift Register sits between the Buffer Register and the Disk. The register is divided in half with SR STB A H clocking CD flip-flops SROO-17 and SR STB B H clocking CD flip-flops SR18-35. These strobes originate in the Shift and Longitudinal Register Control, Drawing RP15-0-15. The SR flip-flops are cleared in like manner by CLR SR A Land CLR SR B L also originating in the Shift and Longitudinal Register Control. RP15 -0-36, 37,38 • • • • • • • • CLRSRL------~+---~----_r--------------------~~--~ SRSTBH------~+---------4_-- • • • • • • • • • • • • • • • • • BRENH----~~--r+--_r------------------------~ LPR ENH----~r_--r+--~------------------------+_--~ SRENH----~~--r---~------- --------------__~--~--~ BR 00 (I) H LPR 00 (0) H Figure 5-13 BR 35 (,) H LPR 35 (0) H RDP (1) H Shift Register, Simplified Diagram 5-23 115-04&8 Each SR flip-flop is set by an OR gate of three possible AND gate conditions. One set of AND gates looks at associated bits in the Buffer Register and is enabled by BR EN H. Another set looks at associated bits in the Longitudinal Parity Register and is enabled by LPR EN H. The third set of AND gates looks at the 1 state of the next sequential SR bit and is enabled by SR EN H. These enabling levels are generated in the Shift and Longitudinal Register Control. In Write operations, BR bits are enabled into the register by BR EN H and strobed by SR STB A Hand SR STB B H. From the register they are serialized and transferred to the disk. Serialization is accomplished by SR EN Hand SR STB A and B shifting data out of the register. During Read operations, data enters SR35 via READ DATA COAX, RD BIT flip-flop and RDP (1) H from the Read/Write Control (Drawing RP15-0-05). When all 36 bits are assembled, they are paralleltransferred to the Buffer and Longitudinal Parity Registers for further processing. A thirty-seventh bit, which works in conjunction with the Shift Register, generates and checks word odd parity for both Write and Read operations. 5.13.3 Longitudinal Parity Register The Longitudinal Parity Register is 36 bits long. During Write operations, each 36-bit word of the Buffer Register is transferred to the Shift Register which then excl usive-ORs the word into the Longitudina Parity Register. At the end of each sector, the complement contents of the Longitudinal Parity Register are written on the disk. This word is actually a bit-position parity check. During Read operations, each assembled word of the Shift Register is exclusive-ORed into the Longitudinal Parity Register. At the end of each sector, the Longitudinal Parity Register is checked for comparison with the Longitudinal Parity Word written. Note that the RP 15 generates and checks both row and column parity in each sector. The RP15 Longitudinal Parity Register is shown in Figure 5-14 and Drawings RP15-0-39, -40, and -41. The register is divided in half with LPR STB A H clocking JK flip-flops LPROO-17 and LPR STB B H clocking JK flip-flops LPR 18-35. These strobes originate in the Shift and Longitudinal Register Control (Drawing RP 15-0-15). The LPR fl ip-flops are cleared in like manner by CLR LPR A Land CLR LPR B L, which also originate in the Shift and Longitudinal Register Control. Each LPR flip-flop is fed by an exclusive-ORing arrangement (when both the set and reset inputs of JK flip-flops are fed by the same signal, the resultant flip-flop state is the exclusive-OR of that signal). Flip-flops LPROO-17 are fed directly by SROO (1) H through SR 17 (1) H. Input to LPR 18-35 is taken from individual AND gates, each of which is fed by two ORs. One group of ORs looks at SR18-35 (1) L 5-24 RPI5-0-39,40,41 LPR STS A H-.----------------------------------------------~ LPR ••••••••••••••••••••••••••• 17 K o CLR LPR AL----~--~------------------------------------------~--~ SR 00 (1) H SR17(1)H SRTO LPREN L-.----------------------------------~ CAR 00 (1) L,---..L___ SAR 03 (1) L - - . . . _ SR 18 (1) L---'T'- SR 35 (1) L-...rT'- •••••••• ~DRTOLPRENL-*------------~~----~-------------~ LPR STB BH--------------~~----~, CLR LPR B L--------------------~~-----------------------------------~ 15-0459 Figure 5-14 Longitudinal Parity Register, Simplified Diagram and is enabled by SR TO LPR EN L which originates in the Shift and Logitudinal Register Control. The other group of ORs is used to look for a header and is enabled by HDR TO LPR EN L, which a Iso originates in the Shift and Longitudinal Register Control. In these ORs, CAROO-07 (1) L are wired to LPR lS-25, HAROO-04 (1) L feeds LPR26-30, and LPR32-35 looks at SAROO-03 (1) L (LPR 31 is not used in this application). The BR, SR, and LPR are shown functionally in Figure 5-1. It is important to keep in mind the data paths, especially through these registers. 5.14 CONTROLLING MAJOR STATE The RP15 Major State Control is shown in Figures 5-16, -17, -lS, -19 and Drawing RP1S-0-1S. For each function described in Paragraph 5. 10, there are various combinations of machine states through which the RP15 must pass to complete the function, e.g., the disk must read before it writes so that it can locate the addressed sector. This circuit controls each state of the many functions performed by the controll er. These sta tes are: IDLE RECAL SEEK CLR HEAD WRITE: INC HEAD READ. 5-25 SET IDLE L SEEK (1) L _ - - I " ' r - - " _ RECAL (1) L WRITE (1) L READ (1) L ----__'"---_ INC HEAD (1) L CLR HEAD ( I) L +3V • • • • SEEK (1) L RECAL (1) L READ (1) L INC HEAD (1) L CLR HEAD (1) L IDLE (I) L SET WRITE L _ ___ +3V RP15-0-19 10-0460 Figure 5-15 Major State Control, Simpli fied Diagram For each of these states, an associated "set" pulse is generated to put the controller in that state. The states are maintained by D-Type flip-flops shown on Drawing RP15-0-19 and Figure 5-15. On the clock input of each flip-flop there is an a-input OR gate (2 inputs unused) that ORs all the control states except the one to whi ch that gate feeds. The data side of each flip-flop is grounded. Because of this arrangement, if any of the states at the input are set, that state is cleared. For example, if Read state is set by SET READ L on the set side of the READ flip-flop, READ (1) L goes to the OR input of all other states to produce a positive edge at their clock inputs and consequently clear all other states. In this way, the control can be in only one state at a time. Note from Drawing RP15-0-19 that SET IDLE L is tied to the Clear side of all states except Idle, in which case it is tied to the Set side. This guarantees that at Power Clear time (CLR L) the control goes into the Idle state. The logic for SET IDLE L is shown in Figure 5-16. Six equations are ORed to produce SET IDLE L. The first is CLR L. CLR L is an OR of DPCF and I/O PWR CLR (B) L. I/O PWR CLR (B) L is generated in the PDP-15 when the processor is powered up, a CAF instruction is issued, or the I/O RESET key is pushed. JB DN (1) L is also an input to SET IDLE L. This flip-flop (shown on Drawing RP15-0-10) is set at the completion of a transfer, or the abortion of a transfer due to some error condition. The operation of JB DN is described in more detail in the discussion of Status Control (Paragraph 5.23) and Interrupt Control (Paragraph 5.24). 5-26 RP15-0-18 TAG REST ART H INITI.ATE FUNC H SET IDLE L READ ALL+WRITE ALL H INC HAR H WC OVFLO ( 1) H SECTOR END H IN SET IDLE L SECTOR END H TRANS FUNC H - READ ALL+WRITE ALL H RECAL + IDLE H INITIATE H IDLE (1) H --1--- RECAL + IDLE L SET RECAL L FR 02 (1) H - - '_ _ _ 15-0461 Figure 5-16 Set Idle and Set Recal logic, Simplified Diagram A third input to SET IDLE l is the equation: TAG RESTART· INITIATE FUNC Initiate-type functions only require one cycle of the Tag and Bus line timing chain. At the completion of this cycle (TAG RESTART), the Idle state is re-entered. A fourth input is the equation: WC OVFlO (1) . SECTOR END The signal SECTOR END is generated at the completion of each sector transferred. If, at the completion of a given sector, the WC OVFlO flip-flop is set, the Idle state is entered. A fifth input to SET IDLE l is the equation: (READ All + WRITE All) • INC HAR This equation states that if the Function Register is equal to a Read All or Write All, and the SAR is incremented from lOa to 11a (INC HAR is generated at this time), the control must then go back into the Idle state momentarily so that the Head Register in the RP02 can be reloaded. This is done by going back to the Idle state, then into Clear Head state, and finally into Read state (or Seek, if necessary). 5-27 The last input to SET IDLE L is the equation: -(READ ALL + WRITE ALL) . TRANS FUNC . SECTOR END The first two terms in this equation eliminate all functions except Read, Write, or Write Check. For any of these three functions, Idle is entered at the end of each sector. If WC OVFLO is not set, Idle state is only entered momentarily, after which time the control goes to the Clear Head state, the Seek state (if necessary), and then to the Read state. The logic for SET RECAL L is also shown in Figure 5-16. This signal is generated from the following equation: (RECAL + IDLE) . INITIATE· FR02 (1) • IDLE (1) To set the Recal state, the RECAL + IDLE instruction must be commanded, Function Register 02 must be on a 1 (tieing it down to a Recal), the controller must be in Idle, and an initiate function pulse must be received. Because Recal is an initiate-type function, the Idle state wi II be re-entered 4 fJS after SET RECAL L. The logic for SET SEEK L is shown in Figure 5-17. The signal SET SEEK L is the OR of two inputs, the first of which is IN SET SEEK L. This signal is disabled when Function Register 01 equals Function Register 02, and when Function Register 00 is on a 0, which is the equation for RECAL + IDLE L. (Note that RECAL + IDLE L is equivalent to -RECAL + IDLE H.) This means that the operation requested could be Seek, Read, Write, Read All, or Write All. In all these operations, the controller may want to perform a Seek. If a Seek operation is really required depends on whether or not the cylinders compare (-CYL CMPR H), the controller has come from a Clear Head state, and whether a TAG RESTART is received. RPI5-Q-18 FR 01 (0) L-~FR 02 (1) L ------..,. FR 01 (1) L-r..----'"-_ _ FR 02 (0) L-"'-&-_ IN SET SEEK L FRI E Q F R 2 H D FR 00 (1) H FR EQ SEEK L FR 01 (0) H SET SEEK L IDLE (1) H FR EQ SEEK L INITIATE H 15-0462 Figure 5-17 Set Seek Logic, Simplified Diagram 5-28 SET SEEK L can also be produced if the Function Register is set to the code for Seek (FR EQ SEEK L), if it is an initiate function, and if the controller is leaving the Idle state. The Clear Head state is entered for any EXECUTE L pulse as shown on Drawing RP15-0-19. This state clears the Head Address Register in the selected RP02; this is necessary because the Head Address Register in the RP02 can only be loaded by first clearing and then jamming 1s into it. The clearing is done during the Clear Head state; the 1s jamming is done at TAG GATE 1 time of a Read state, with SET HEAD EN (see Drawing RP15-0-47). Three types of Write functions are performed by the controller: a. Normal write, in which a data field is written b. Format write, in which the whole disk is formatted c. Write All Normal, in which the header word and data fields for a particular sector are written. Three AND gates are used to decode the Function Register, to see what type of Write is called for, and then to set the appropriate mode when it is time to do so. These gates are shown in Figure 5-18 and Drawing RP15-0-18. +3V - _ . r - -...... READ (1) H 0 -......- - WON SET WRITE L FR 00 (0) H FR 01 (1) H FR 02 (0) H CMPR(1)H CLOCK DLYD H --1---- SET WRITE L .r---_ +3 V _ _ WRITE (0) H READ (1) H 0 -.......-1-- WAN SET WRITE L FR 00 (1) H FR 01 (1) H - - i - - - FR 02 (0) H CMPR (1) H SUSP H NORMAL H SUSP H - - . r - -...... IDLE (0) H 0 - -......CYL CMPR H FR 00 (1 ) H - - " ' - - - FR 01 (1) H FR 02 (0) H - NORMAL H INDEX SYNC (I) H WAF SET WRITE L + 3 V - - . r - -...... WRITE(I)H D - - - - SET INC HEAD L INDEX SYNC (0) H FR 00 ( I ) H FR 01 (1) H FR O~ (0) H - NORMAL H SUSP H --1---- RP15-0-18 HI-0463 Figure 5-18 Set Write and Set Inc Head Logic, Simplified Diagram 5-29 In Write All Format mode, WAF SET WRITE L waits until the Selected Unit Sector Pulse is received before beginning to write, provided the control is not in the Idle mode and the cylinder to be formatted agrees with the Cylinder Address Register. In addition, the panel switch FORMAT/NORMAL must be in the FORMAT position (-NORMAL H) and the Index pulse must have just occurred [INDEX SYNC (1)] . In Write All Normal, WAN SET WRITE L only waits for the Sector Pulse, provided the panel switch is in NORMAL position, and the desired sector has been located in the Read state (CMPR (1) Hand READ (1) H). CMPR (Header Compare) is a flip-flop that is set when the header word read from the disk agrees with that located in the CAR, HAR, and SAR. In Write Data Normal, WDN SET WRITE L is conditioned by Read state (READ (l) H) and header compare (CMPR (1) H). However, WDN SET WRITE L is synchronized to a control timing pulse called CLOCK DLYD H. This signal is discussed in Read Data Separation, Paragraph 5. 16 (see Drawing RP15-0-0S). All of the above resultant mode signals are ORed to yield a common SET WRITE L. An additional AND gate combines conditions not unlike those for Write All Format to yield SET INC HEAD L, whi ch is used during the formatting of the disk. These conditions are characterized by the controller being in the Write state, the Index pulse having just passed (INDEX SYNC (0) H), the Function Register = 6 (110 or Write All), the panel switch in FORMAT position, and the occurrence S of Selected Unit Sector Pulse. During a formatting operation, the controller wi II shift from Idle state to Clear Head state, to Write state, then to an Inc Head state, then back to Write state, and again back to Inc Head state, and so on to the end of the cylinder. At that time, the controller will go into a Seek state so that it can move the heads over one track. Once that is accomplished, the Clear Head state wi II be entered for the next cyl inder; this sequence repeats unti I the entire disk is formatted. This logic is shown in Figure 5-1S and Drawing RP15-0-1S. SET READ L is generated from the OR of two inputs (see Figure 5-19 and Drawing RP15-0-1S). The first input implys that READ is entered if the function is not a SEEK, RECAL, or IDLE, provided the FORMAT/NORMAL switch is in the NORMAL position, the CAR equals the SUCAR (CYL CMPR H), the present state is CLR HEAD, and the Tag and Bus line cycle for CLR HEAD is complete (TAG RESTART H). This AND gate provides the means for the controller to enter the Read state directly from the Clear Head state. This happens only when a Seek operation is not necessary. If a Seek is required (-CYL CMPR L), IN SET SEEK will be generated to produce SET SEEK and to clear the syncrhonizing D-Type fl ip-flop shown in Figure 5-19. This fl ip-flop wi II remain cleared, thereby disabling the second input gate to SET READ L, until the leading edge of SU RDY H (Selected Unit Ready). When SU RDY occurs, the Seek wi II have been completed and SET READ is then generated. This gate is also conditioned by Seek state, NORMAL, and a function other than Seek (-FR EQ SEEK H). 5-30 RPI5-Q-18 -FR EQ SEEK H - RECAL+IDLE H TAG RESTART H NORMAL H - ; - - CYL CMPR H CLR HEAD (1) H SET READ L +3V--'----' +3V SEEK (1) H -___- ...... NORMAL H IN SET SEEK L 15-0464 Figure 5-19 Set Read logi c, Simpl ifi ed Diagram The major state flows for each of the functions that can be performed in the RP15 are illustrated in Figures 5-20 through 5-25. The states are shown in rectangles, decision points in diamonds, comments or appropriate signals appear in ovals, and physical delays or large time lapses appear between two horizontal lines. 5. 15 COMMANDING THE DRIVE (Tag and Bus line Control) The main function of the RP15 Tag and Bus line Control is to control the signals sent to the disk pack and to develop the timing for the disk (see Figures 5-26 through 5-28 and Drawing RP15-0-16). It tells the drive when to read, write, move its head, increment its head, or select a different head (among other commands); commands to the drive are translated for almost every function performed by the control. During formatting instructions, the disk begins with head zero on surface zero. At the end of that track, the control must switch to head one on surface one, etc., through the entire cyl inder. This switching is done by a signal called Increment the Head Address (INC HEAD (B) l). As shown in Figure 5-26, each time this signal is issued to the input of this control, it sets a cross-latched flip-flop (made up of two OR gates) that starts a timing chain which consists of three D-type flip-flops (TAG EN, TAG 1 and TAG 2). Note that this time chain can also be initiated by EXECUTE l, SET READ l, SET WRITE l, SET RECAll, SET SEEK l, or INITIATE l. Setting one of these inputs will enable the M401 module, which is a l-MHz clock. When it is enabled, the first clock sets TAG EN flip-flop and TAG 1 (10). 5-31 IDLE FUNCT ION 4" ..e (BUSY) RECAL FUNCT ION TAG RESTART L CLEARS BUSY SEEK FUNCTION INITIATE L SETS BUSY 4J.1.IIC TAG RESTART L CLEARS BUSY (BUSY) t!5-046!5 Figure 5-20 Initiate Functions, Flow Diagram Together the two TAG flip-flops constitute a "Gray Code" counter. The second clock pulse sets TAG 2 (11), the third pulse clears TAG 1 (01), the fourth clears TAG 2 (00), and the fifth clears TAG EN. At this point, counting ceases for that cycle. In decoding these states (see Figure 5-27), TAG 1 (1) H is delayed by 200 ns to produce TAG 1 DLYD Hand L. TAG 1 DLYD H is ANDed with TAG EN (1) H to produce BUS GATE 1 L. Also -TAG 1 DL YD H is AN Ded with the equation TAG EN (1) + [(RD + ER) . TAG GATE 2J to produce BUS GATE 2 L. The purpose of this equati on is explained later. 5-32 ---r--- (FR=7 FOR WRITE CHECK) EXECUTE L SETS BUSY JOB DONE L CLEARS BUSY NO YES 15-0466 Figure 5-21 Read or Write Check Functions, Flow Diagram TAG 1, TAG 2, and TAG EN are further decoded to produce TAG GATE 1 L and TAG GATE 2 L. These relationships are shown in Figure 5-28. TAG 1 is delayed to guarantee that BUS GATE 1 L completely surrounds TAG GATE 1 L. If this were not done, edge triggering in the RP02 would create marginal problems. A small disadvantage of this delay is the false BUS GATE 2 L that is raised for only 200 ns (see Figure 5-28); since this is followed by a real BUS GATE 1 L, which has time to set up the Bus Cable to the RP02, no harm is done by this false pulse. 5-33 4.11 S8C . NO YES APPROX. 2.0 rns 15-0467 Figure 5-22 Write Function, Flow Diagram 5-34 EXECUTE L SETS BUSY JOB DONE L CLEARS BUSY YES 15-0468 Figure 5-23 Read All Function, Flow Diagram Four important signals now exist: BUS GATE 1 L TAG GATE 1 L BUS GATE 2 L TAG GATE 2 L (Enable) (Strobe) {Enable} {Strobe} j Time 1 Time 2 These signals go to the Bus Disk Drivers, which decide what signals to send to the disk drive (see Drawing RP15-0-47). The bus gates raise the bus levels first, then (after the lines have had time to settle) decoding occurs and the tag lines strobe the information down the line to the drive. 5-35 EXECUTE L SETS BUSY YES 2.0-24.5ms ~~ Figure 5-24 Write All Normal Function, Flow Diagram 5-36 15-0469 EXECUTE L SETS BUSY YES NOTE' If the word count register is loaded with a word count greater than 40010 file unsafe will be set on the 20th pass of this loop. 1~-0470 Figure 5-25 Write All Format Function, Flow Diagram 5-37 RPI5-0-16 +3V~~--------------------------------~---------------------------------, TAG 2 (0) H CLRL~~----------------------------r---~----------------------------~--~ TAG 1 (1) L TAG 2 (1) L EXECUTE L---O'--__ INC HEAD (B) L SET HEAD L SET WRITE L SET RECAL L ---~--SET SEEK L INITIATE L TAG 1 (1) H TAG 2 (1) H CLRL -TAG GATE TAGEN(1)L 2 (B)L TAG EN (0) H TAG RESTART L TAG RESTART H 15-0471 Figure 5-26 Tag and Bus Line Control, Simplified Diagram The following signals are decoded on Drawing RP15-0-16 but are not shown in Figure 5-27: CAR STB = SEEK (1) . BUS GATE 1 RD + ER = READ (1) + ERASE GATE (1) HAR STB = (RD + ER) . BUS GATE 1 SET HEAD EN = (RD + ER) . NORMAL The signal CAR STB L functions to place CAR bits 00-07 onto the RP02 Bus Cable (see Drawing RP15-0-47) at BUS GATE 1 so that they can be strobed into the RP02 Cylinder Address Register at TAG GATE 1. This is done any time it is necessary to perform a Seek operation. 5-38 r-v-- TAG 1 DLYD L TAG I OLYO H BUS GATE 1 L TAG 1 DLYD H TAG1(1~H TAG EN (1) H TAG 2 (1) H TAG GATE 1 L ~---------------- BUS GATE 2 L -TAGIOLYOH-P TAG 1 (0) H TAG2(O)H TAG GATE 2 L TAG EN RD+ER H (1) L TAG GATE 2 L -TAG GATE 2 (B) L RP15-0-16 15-0472 Figure 5-27 Tag and Bus Gate Logic, Simplified Diagram 2rP5°-l IM401 CLOCK t 1).18 t 1).15 t 1).15 t 1~1 t TAGEN(1)H TAG 1 (1) H TAG 2 (1) H TAG 1 DLYD H BUS GATE 1 L U BUS GATE 2 L TAG GATE 1 L I ~200nl FALSE BUS GATE 2 L ----------~I TAG GATE 2 L TAG RESTART H ,,I ).,.. I y~ ---------------'1') f1--15-0473 Figure 5-28 Tag and Bus Line Timing Diagram 5-39 The signal RD + ER H comes up for the duration of either a Read or a Write operation. The ERASE GATE flip-flop is set with WRITE GATE (1) L and is cleared 20 tJS after the trailing edge of WRITE (1) H (see Drawing RP15-0-16); therefore, ERASE GATE is set at Write time and remains up 20 I-'S longer than Write. NOTE Because the Erase head is mounted physically behind the Write head, the Erase signal must be kept on longer to trim erose all of the track that has been written. For all operations, with the exception of Read or Write, BUS GATE 2 L is 2-l-'s wide; however, during a Read or a Write (RD + ER), BUS GATE 2 L is Ilatched" up for the duration of the operation. The equation TAG EN (1)+ [(RD+ ER)' TAG GATE 2] referred to earlier, serves this latching function. HAR STB L places HAR bits 00-03 onto the RP02 Bus Cable (see Drawing RP15-0-47) at BUS GATE 1 so that they can be strobed into the RP02 Head Address Register at TAG GATE 1. This is done for all Read or Write (RD + ER) operations. On Drawing RP15-0-47 SET HEAD EN L is ANDed with TAG GATE 1 L to produce SET HEAD L. SET HEAD L, in turn, is sent to the selected RP02 to strobe the information on Unit Bus 00-07 into the Head Address Register within the selected RP02. The information on Unit Bus 00-07 is HAR 00-03 which was gated there by HAR STB L. On Drawing RP15-0-47, note that SEEK (1) is ANDed with TAG GATE 1 L to produce SET CYLINDER L. This signal is sent to the Selected RP02 to strobe the information on Unit Bus 00-07 into the Cylinder Address Register within the selected RP02. The information on Unit Bus 00-07 is CAROO-07 whi ch was gated there by CAR ST B L. As shown on Drawing RP15-0-16, READ GATE and WRITE GATE flip-flops serve as buffering flip-flops that are set with the associated operation (Read or Write) ANDed with TAG 2 (1) H. These flip-flops remain set unti I the associated operation is cleared. At the completion of each Tag and Bus Line timing cycle, a TAG RESTART H pulse is generated. The purpose of this signal is to inform the Major State Control that the cycle is complete. Usually this signal is generated 4 I-'S after the signal that started the cycle: 5-40 EXECUTE L INC HEAD (B) L SET RECAL L SET SEEK L; however, if the operation is a Read or a Write, then TAG GATE 2 (B) H is up for the duration of the operation (2.5 to 25 ms). The trailing edge of TAG GATE 2 (B) H generates TAG RESTART H. 5.16 READ DATA SEPARATION (VFO) The recording technique used in the RP15 (Double Frequency NRZ) is dictated by the characteristics of the recording material used on the RP02 Disk Pack. The fact that it is a disk, and not a drum, renders the device speed-frequency sensitive, a sensitivity factor that becomes more critical as the recording head nears the center of the disk. (A drum is speed-frequency sensitive, but this sensitivity is a constant since diameter remains constant.) Add to this sensitivity the fact that any magnetizable material, is an imperfect medium, at best, due to its reluctance to change; the need for the technique used for Data Separation becomes apparent. The disk pack system is susceptible to a phenomenon termed "pulse c~owding". When a series of 1s are recorded on a track, they assume positions equally spaced from one another . If, however, a 1 bit is removed, the adjacent bits tend to fill the vacant cell. This effect is similar to lining up a series of bar magnets end-to-end. When a bar magnet located in the middle of the chain is removed, the adjacent magnets move in to fill the gap. Since the resultant locations can shift in either direction, a means must be provided to "read" through a precisely timed "window" so that the original timing may be recovered. The RP15 uses a double-frequency, non-retum-to-zero (NRZ) recording technique. A 5-MHz clock signal is divided to produce two 2.5-MHz signals with a 180 0 phase relationship (see Drawing RP15-0-08). When writing, the leading 2.5 MHz continuously records 1 bits on the disk surface, while the trai ling signal samples the data to produce data bits. If the data to be written are continuous Os, a 2.5-MHz signal is recorded on the disk surface. If the data to be written are continuous ls, then a 5.0-MHz signal is recorded. Therefore, for any given data cell, the recorded frequency is either 5-MHz for a 1 data bit, or 2.5 MHz for a 0 data bit. To recover dC/ta recorded in this manner, the Os rate frequency component must be removed; this is done by using a phase-locked osci lIator (VFO) that is simi lar to a sample-and-hold circuit. The VFO is capable of sampling the Os rate pattern in the preamble of each record; phase-locking on this pattern; and then maintaining phase through the record, making only minor corrections with the use of the Os rate component of each data cell. The VFO then removes the Os rate component with which it is fami liar, leaving only the recovered data. 5-41 The Os rate component (2.5 MHz) removed from the Read signal is also used. This signal and its Write counterpart are the main sources of timing in the RP15 Controller. Since the RP02 has no c lock track, this system provides self-clocking (see Figure 5-29). WRITE TIMING o CONTROLLER DATA WRITE DATA WRITE CURRENT _____ _ READ SIGNAL ______ _ 200 ns 1 BIT CELL TIME READ DATA (NOTE PHASE SHIFT BECAUSE OF PEAK DETECTION) RECOVERED DATA READ TIMING 09-0334 Figure 5-29 RP15/02 Read/'Nrite Timing Waveforms The RP15 VFO Control is shown in Figure 5-30 and Drawing RP15-0-0S. The circuit comprises a 5-MHz source, an M420 Module, a frequency divider flip-flop, and associated delays and gates. The RP02 Disk Pack has no clock track of its own; therefore, a means must be provided to record the timing on the disk with the data to be stored at the moment that data is recorded. In this way, a firm relationship between clock and data can be established at time of writing so that at time of reading that relationship can be reconstructed regardless of small differences in drive speed over a period of time. To accomplish this recording, a format has been set up to provide a synchronization period at the beginning of each sector (see Figure 3-2) consisting of no data (continuous Os). As shown in Figure 5-31a, this signal consists of a string of pulses recorded on the disk, at a frequency of 2.5 MHz, representing the Os rate component. This signal determines the 1s rate component and establishes the basic timing for information to be written on the disk or read from the disk, independent of drive-speed differentials between time of write and time of read. These 2.5-MHz pulses are recorded at the beginning of each data cell throughout the format, thereby maintaining the basic timing across the entire sector. 5-42 r-------------M:;O~~E------------~ I I I I I VFO SYNC ClK H VCO I r I VFO OSC H I I L _______________ _ I ---.I 5MHz CLOCK GATE H READ DATA COAX H 2.5MHz CLOCK GATE l -VFO ENABLE l CLOCK H lOOns 09-0321 Figure 5-30 RP15 VFO Control, Block Diagram During Write, the VFO is switched off and the synchronization area is generated in the RP15 from a self-contained crystal-controlled 5-MHz source; the output of this source is divided to produce two 2.5-MHz pulse trains, each of which bears a 180 0 phase relationship with each other. The leading 2.5-MHz signal produces the sync bits at the beginning of each bit cell time. The trailing 2.5-MHz signal establ ishes the middle of that bit cell. The recording system used in the RP02 is termed "double-frequency non-return-to-zero (NRZ); II this is to say that the state of magnetization of the disk material does not change except when excited with a 11111 bit, and then in the opposite polarity. The recording head is, in reality, a gap that constitutes discrete space; the actual shape of magnetization change wi" not be a square waveform, but rather some sinusoid that is an instantaneous function of field strength, field rate-of-change, gap width, surface reluctance, and drive speed (see Figure 5-31b). The waveform is a constant frequency for an all Os data pattern, but when 1I1 s11 are introduced (c), the sync bits tend to be displaced by the data bits. It is this displacement that increases with pulse density and is described as II pu lse crowding II • Because both data and sync bits can shift, when they are written and when they are read, the timing for Read must be based on a variable device that can be changed within the limits of expectable variance. The functions of the VFO are: 5-43 I c~~ C;- =!::=:j< \ 1:== ---+== (ZEROS RATE COMPONENT) 2.5MHz (ONES RATE COMPONENT) 5MHz~ L.+-DATA BIT (a) -----,l!FSYNC BI T ilL 2.5MHz 5MHz~ ~""'--SY-N-C-B-IT-"'L-_''''~-D-A-T-A-B-IT- '": B \ \ B - - ,- - - - . . . \ II • ONE BIT CELL I IN WRITE DATA A=200ns B=400n5 c'; 70 nS t \ I I \ \ I ± 15ns \ I RISETIME 30n5 \ ONE BIT CELL IN READ DATA ; A=200ns t B c 400ns t C=70 nS t I ±70ns ± 70n6 ± 15n8 \ \ \ \ lj \ \ ---I r- -, ~ FALL TIME 20n5 ~J :....j ' I ~ RISE TIME 45n5 FALL TIME 35n5 09-0320A (b) "ZEROS" DATA PATTERN ------, ~ 110 11 "0" 110 11 WRITE CURRENT - -__L.._ _ _ _J - - - - - I . ._ _ _ _ _. . . J - - - MAGNETI ZATION ON DISK --:""':="'- \ \ THEORETICAL - ' - - - "ONEs"a"ZEROS" (e) DATA PATTERN - - - - - - , WRITE CURRENT - - L_ _..1 09-03208 Figure 5-31 RP02 Recording Characteristi cs a. To sample the incoming clock bits received from the disk b. To establish an internal clock gate based upon the average leading edge of those clock bits c. Set up a reading window during which the condition of data is sampled, since the data variance will be relatively the same as clock variance. The heart of the VFO Control is the M420 Module, which is shown within the dashed lines in Figure 5-30. Basically, the module contains two D-Type flip-flops with their data inputs tied high; a clearing AND gate tied to the 1 side of both flip-flops; a differential amplifier, whose plus input 5-44 looks at the 'I side of one fl ip-flop and whose minus input looks at the 1 side of the other fI ip-flop; and a voltage-controlled osci Ilator, the output frequency of whi ch is controlled by the voltage output of the differential amplifier. As configured, the circuit will reproduce a recurring input for a period of time after that input has been removed. There are two inputs to the M420 (see Figure 5-30 and Drawing RP15-0-08). The generated clock pulse (VFO SYNC ClK H) from the VFO, which runs at approximately 2.5 MHz, sets the "A" flip-flop; the separated clock pulse (CLOCK PULSE (1) H) from READ DATA COAX H sets the "B" flip-flop. Theoretically, when both fl ip-flops are set, both are cleared. Figure 5-32a is a timing diagram of this operation. Assume that the frequency of clocks from the disk (CLOCK PULSE (1) H is slightly higher than VFO SYNC ClK H; the "B" flip-flop w'ill be set longer than the "A" flip-flop and the width of its 1 state will lengthen as it sets earlier and earlier before being cleared each time the "A" flip-flop sets. In Figure 5-32b, the opposite is true when the incoming clock pulse frequency (CLOCK PULSE (1) H) is lower than VFO SYNC ClK H. In this case, the "A" flip-flop is set longer and longer as it sets earlier in the cycle. In both cases, the "A" flip-flop reaches a point where it Iines up with the" B" flip-flop; at this point the cycle starts again. The up time of the "A" or "B" flip-flops will lengthen at some sinusoidal rate equal to the difference in frequency between CLOCK PULSE (1) Hand VFO SYNC CLOCK H. The output width of the flip-flop whose input is lowest in frequency will be very small (close to zero); the output width of the flip-flop whose input is highest in frequency will be finite. As such, the "A" and "B" flip-flops function together as a phase detector that feeds the differential amplifier with an error voltage on the higher frequency input, whether it be "A" or "B", that is proportional to the frequency of mismatch. The differential amplifier takes the difference of these two flip-flops, integrates that difference, and produces a plus or minus error voltage to the VFO that causes it to increase or decrease its frequency to match that which it received from the disk. At this point, an output from the M420 Module is seen; it is called VFO OSC H. This output is approximately 5 MHz and is fed through associated logic to produce DATA GATE CLOCK H, which is then tied to the DATA GATE flip-flop. The flip-flop functions to divide the output by 2, yielding two 2.5-MHz signals that are 180 0 out of phase with each other. The 1 state of the flip-flop is designated DATA GATE; the 0 state serves as the CLOCK GATE. The 5-MHz signal (DATA GATE CLOCK H) is also delayed approximately 100 ns to produce YFO CLOCK H which is ANDed with CLOCK GATE H, then inverted, to generate CLOCK H (see Figure 5-32c). CLOCK H occurs at a 2.5-MHz rate and falls in the middle of CLOCK GATE. Because of logic delays and the variability of circuit delays, the 100-ns delay is adjustable so that the leading edge of CLOCK H can be placed exactly in the middle of its gate. CLOCK H is further delayed approximately 40 ns to produce VFO SYNC CLOCK H which, in turn, is fed directly into the input of the M420 c1()sing the loop. 5-45 1-,--1____1--&..-1____I----&.-I-.&.1----,--1---,I~I,) (I 1 1 1 VFO SYNC CL K H (2.5 MHz) _____ 1----L.o1----,-1--I1'----A.o1----L.o1---L-1--,,1--,-1--1-1---'I') (I 1 I I CLOCK PULSE (1) H(>2.5MHZ)----L A (1) H ----,---I,,--I 1 1 -L-I--,--I--,--I 1 --L-I--A...\L) ..J...-....1..- --1..- B (1) H_·I&__..JL........J O. INCOMING VFO SYNC C L K H (2.5 MHz) CLOCK PULSE (1) H k 2.5 MHz) J-U 11TT FREQUENCY HIGH --....J11..........J.1----L1-----L..1-.L...1--,--I-JIL............I.I--LI~I,) "",","'II-----L........L.... _.L..I-..L.1---L1..........J1'---.l...1~I---LI..........J..........JIL...-..J.,() A (1) H _ - " -__U_IL......-' J-U 1rTT B (1) H b. INCOMING FREQUENCY LOW --LI.....LI. . .I. . . .I-'-I-'-I . _ _ _ _ 5 MHz VFO OSC _ _ _ ---IflfUlL.........____ DATA GATE (1)H _ _ _ _ CLOCK GATE U1fU ----l1t..-...L1_.L.1...-..J11...-____ 2.5 MHz CLOCK H _ _ _ _ c.DEVELOPMENT OF CLOCK H 15-0474 Figure 5-32 VFO Timing Waveforms During Read, the 1109 sync bits of the preamble are fed to the VFO via READ DATA COAX H for approximately 350 to 400 tJS. This is a sufficient sample to force the VFO to reproduce its input so that it can continue as a phase-locked loop through the remainder of the sector. During this synchroniza- tion period, -VFO ENABLE L is low; this allows everything on the Read Data Coax to enter the M420. Presumably this period in the format contains no data, but rather clock pulses which are then used to synchronize the VFO. Once the VFO is synchronized, -VFO ENABLE L goes high and the circuit depends on DATA GATE (0) L inverted (equal to CLOCK GATE H) to gate the Read Data Coax into the VFO. Because of the delays discussed, this occurs at the average of all clock pulses received from the disk; the VFO has essentially separated the clock pulses from the READ DATA COAX (CLOCK PULSE (1) H). In Figure 5-30, CLOCK PULSE (1) H is shown as the output of an AN D gate; this is a functional equivalent to actual hardware as shown in Drawing RP15-0-08. In reality, this is the CLOCK PULSE flip-flop whose data input is the OR of either DATA GATE (0) Lor -VFO ENABLE L, and is clocked by READ DATA COAX. When CLOCK PULSE sets, it clears itself, producing a pulsed input to the M420. In operation, the VFO operates similarly to a closed-loop AFC circuit. Once it is synchronized, the VFO locks in and remains in sync. 5-46 The 40-ns delay forces the clock pulses from the Read Data Coax to line up in phase with CLOCK H. Since READ DATA COAX must go through CLOCK PULSE flip-flop before entering the M420, and since CLOCK PULSE flip-flop can have a logical delay of between 0 and 50 ns, this variable delay adjusts for the difference and eliminates constant phase errors. Relating the simplified diagram shown in Figure 5-30 to the logic schematic in Drawing RP15-0-08, the output of the M420 Module is labelled YFO OSC H. This signal is sent to an M121 where a logic decision is made as to whether or not the controller is in the Read state (WRITE or READ (0) H). If it is not, the YFO is turned off (allowed to go into saturation) and the crystal clock is used as timing for the Write state. If it is in Read state, the output of the YFO is gated through the M121 to a pulse amplifier (PA); provided the controller is not in Maintenance mode (MAINT (0) H), an output called GATED YFO OSC L will be seen at the PA. This signal is fed to M311 to input a coarse adjustment on the centering delay. From the M31l, the signal emerges as DATA GATE CLK H and is used to complement the DATA GATE flip-flop. It is further delayed through the M311, then through a 40-ns variable delay M312, to yield YFO CLOCK H; from there it enters an M627 where it is gated with CLOCK GATE H to produce CLOCK L. NOTE This is shown in Figure 5-30 as the output of YFO OSC H going through a 100-ns delay and being gated with CLOCK GATE. The output CLOCK L which goes into another delay gives CLOCK H, the main timing pulse. CLOCK L is inverted to produce CLOCK H. CLOCK L is delayed by one variable 40-ns delay to yield YFO SYNC CLK H. This pulse is then fed back into the YFO closing the loop. The other input to the YFO is CLOCK PULSE (1) H, which comes from the CLOCK PULSE flip-flop. CLOCK PULSE flip-flop can be set by any pulse on the Read Data Coax during synchronization; after sync, it can be set by a pulse from Read Data Coax, whenever DATA GATE is on a 0 L (same as CLOCK GATE on a 1). When DATA GATE is on a 0, its output will indicate CLOCK GATE H, thereby separating clock pulses from data pulses on the Read Data Coax. The flip-flop output CLOCK PULSE (1) H is then fed through an M312 to clear itself; this is done to secure pulses from the flip-flop that are 50-ns wide (30 ns of fixed delay plus 20 ns of logic delay). During synchronization, -YFO ENABLE L at the input of CLOCK PULSE flip-flop will make the D-input high until the YFO has synchronized. Under this condition, every pulse coming off the Read Data Coax will set CLOCK PULSE. Unless glitches exist in the Sync field, they will all be clock 5-47 pulses that are required for synchronization. Once the VFO is synchronized, -VFO ENABLE L goes high. Now CLOCK PULSE will set only when DATA GATE is on a 0 L and the clock pulses from the disk are separated. A representative set of waveforms are shown in Figures 5-33 through 5-41. Figure 5-33 is a photograph of the Op Amp error voltage waveform (EllV2) synchronized on CMPR (1) H (A18Fl) during a Read All operation. The negative spikes represent the end of sectors; they are the result of that format area following the longitudinal parity called guard bits. This area consists of all 1s because that is what was left in the LPR when the pack was formatted. The number of guard bits written varies depending upon the room left in anyone sector. The area can be as short as 20 I-'s or as long as 80 I-'s. As the Data Gate input to the VFO is disabled and the VFO is opened up to all information coming in off of the Read Data Coax, the VFO attempts to synchronize to the all 1s pattern of the guard bits which is at a 5-MHz rate. As it does, the Op Amp error signal points toward 5 MHz, a somewhat lower voltage than its nominal 4V running level. TIME @ 2 ms/cm ENDS OF SECTORS OPAMP ERROR VOLTAGE @2v/cm RESULT OF GUARD BITS (ALL "15") 5MHz Figure 5-33 RESULT OF SECTOR PULSE PREHEADER SYNC AREA 1109 "0"5 RESULT OF DATA FIELD 2.5 MHz (LOCK-ON) RESULT OF PROGRAM CHECKING (SATURATION) Synchronizing on CMPR (A 18Fl) during a Read All, Op Amp Error Voltage Waveform When the Sector Pulse is received, the pre-header sync area is presented and the 1109 bits of zeros (a 2.5-MHz rate) cause the error voltage to return to the 4V point, where it finally locks on after a short period of overshoot and ringing. 5-48 As it locks on, the controller begins reading the data field and transferring what it is reading to memory. After 2.5 ms, the entire sector has been read and transferred. At this time, the program must check the data that have just been brought in; the controller shuts off the VFO during this period. When it is shut off, the VFO goes to its saturated level of 5.5V and stays there until checking is complete (approximately 3 ms). When the controller completes checking the transfer, it turns the VFO back on, bringing it down out of saturation, and again starts to sync on data. In Figure 5-33, the second data field is somewhat shorter than 2.5 ms, indicating that the program turned the control on in the middle of a data field. When the next guard bit field is seen, the error voltage spikes toward OV, again, and returns on the next sector pulse; at that time it reads the next header. This time the VFO does not saturate; this indi cates that, since this is a Read All operation, it has located the IIheader - P it is looking for. The VFO remains synchronized but passes over this data field. After the next sector pulse, the VFO reads that header and data field, saturates for checking, and starts looking for the next IIheader - 111. Figure 5-34 is also a photograph of the Op Amp error voltage wave.form (E11V2) synchronized on CMPR (1) H (A 18F 1); but this is as it appears during a norma I Read operation. Once again, the negative spikes represent the ends of sectors and are the result of guard bits and sector pulses. In this instance, the controller is reading one sector out of ten. As the trace begins, the VFO is in saturation at 5.5V; then it drops to 4.0V to read a header. Since this is not the header desired, the V\:O is left open and drops to a value between 2.0 and 2.5V as it follows the random bits in the data field. HEADERS TIME @ 5 ms/em PROGRAM CHECKING TRANSFER (SATURATION) SEE FIG.~35 OPAMPERROR VOLTAGE @ 2v/em DATA Figure 5-34 GUARD BITS & SECTOR PULSES Synchronizing on CMPR (A18F1) during a Read, Op Amp Error Voltage Waveform 5-49 In this particular case, the procedure is repeated nine times until finally the controller decides that the tenth header is the field it wantso Notice that the 4.0V level is much longer now than it was for a II other nine sectors, since this is the header desired and the controller remains synchronized throughout the data field for a full 2.5 ms. Following this, data are transferred into memory and the program checks the transfer, at which time the VFO saturates producing the spike up to 5.5V. Figure 5-35 provides a closer picture of the desired header. In this photograph, the time scale has been expanded by a factor of ten to blow up the circled area in Figure 5-34. During the first centimeter, the controller has just emerged from the last data field. The spike that results from guard bits and sector pulse is seen more clearly preceding the desired header. Near the end of the second centimeter, the results of header-to-data field gap may be seen as the indeterminant contents of that area momentari Iy shifts the Op Amp error voltage. The data field follows with the saturation excursion during check; after check, the cycle repeats as the controller seeks the next header desired. HEADER DESIRED TIME @ 0.5 ms/em SATURATION DURING CHECK SEEKING NEXT HEADER OPAMP ERROR VOLTAGE @2v/em FOLLOWING RANDOM DATA GAP Figure 5-35 DATA FIELD Synchronizing on CMPR (A 18Fl) during Read at Xl 0 Expansion (Header Desired) In Figure 5-36, the Op Amp error voltage is shown during a normal Write operation. This waveform can be compared to that of Read in Figure 5-34. The signals are similar; the controller remains in Read through nine sectors until it locates the header desired in sector 10. After reading the header, the VFO is turned off during the remainder of that sector, since it is not needed for writing. As in Figure 5-35, Figure 5-37 is an expansion of the circled portion of Figure 5-36 showing location of header desired, saturation during the time the controller is writing, resynching, and seeking the next header. 5-50 SATURATION TIME @ 5 ms/em CONTROLLER WRITING (SATURATION) SEE FIG. 5037 OPAMPERROR VOLTAGE @2v/em DATA GUARD BITS& SECTOR PULSES HEADER DESIRED Figure 5-36 Synchronizing on CMPR (A18Fl) during a Write 1 Op Amp Error Vol tage Waveform HEADER DESIRED TIME @ 0.5 ms/em SATURATION DURING WRITE SEEKING NEXT HEADER OPAMP ERROR VOLTAGE@2v/em FOLLOWING RANDOM DATA Figure 5-37 Synchronizing on CMPR (A 18Fl) during Write at X 10 Expansion (Header Desired) A means of determining proper VFO operation is shown in Figure 5-38; it is a dual-trace presentation of clock pulses in from the disk and clock pulses out of the VFO after they have been averaged. This is the first check a technician should make after installing a new VFO. There are no adjustments that can be made with this setup; it is merely a quick way of making certain that the circuit is operating as it should. The top trace (F11 E2) represents separated clock pulses from the Read Data Coax (CLOCK PULSE (l) H), showing at least ± 25 ns of jitter as the pulses come off the disk. The bottom trace is the averaged 5-51 TIME @ 0.1 /J.s/cm r-------_______ _______________ , A SEPARATED CLOCK PULSES FROM THE DISK INTO THE VFO. (F11E2) AVERAGED CLOCK PULSES OUT OF VFO. (F11H2) Figure 5-38 Clock Pulses In vs Clock Pulses Out, Proper Operation when Synchronizing on CMPR clock pulses (VFO SYNC CLOCK H) out of the VFO (F11H2), created by the VFO and synchronized to the jitter pulses. This is the smoothed signal that is used both for timing and as an input to the VFO. When operating correctly, the signal's leading edge I ines up with the average leading edge of the top trace. If something is wrong in the circuit, if the signals are not in phase or if they are not equal in frequency, then one signal cannot be used to trigger the other; therefore, the illustrated waveform will not be obtained. For this reason, it is used to verify proper operation. The dual trace in Figure 5-39 illustrates the setup used for the first adjustment in the VFO loop. The bottom trace represents raw data coming from the coax at E14B1; the top trace shows the clock pulses produced by the VFO (CLOCK H) at D17l2. This is the phase adjustment in which the leading edge of the developed clock is aligned with the average leading edge of raw data clocks. As such, it is the adjustment that removes the phase error introduced by the circuit. Clock pulses may be distinguished from data pulse because they have no base line; data pulses, being random, will always have some base line. When this adjustment is made, the degree of phase error must be determined. If too much delay exists in the circuit, a single wire running from D 17M 1 to Fll H2 (VFO SYNC ClK H) can be rerouted by removing the end connected to D17M1 and connecting it to E12S2. This cuts out two gate delays and allows the variable 4O-ns delay E12 to be adjusted to zero, if necessary, to achieve the desired results. NOTE These paragraphs are not intended to be an adjustment procedure for the VFO. To make these adjustments, refer to Paragraph 6.2.3 for specific steps to follow. 5-52 TIME @ 0.1 J.l.s/cm TO ADJUST PHASE ALIGN L.E. WITH AVERAGE LEADING EDGE OF RAW DATA CLOCKS DEVELOPED CLOCK (D17L2) READ DATA COAX (E14B1) (RAW DATA) DATA PULSES (SOME BASE LINE) Figure 5-39 Developed Clock (D17L2) vs Read Data Coax (E14Bl), Phase Adjustment If it were determined that more than 40 ns were required, the wire run from E12F1 to D17L 1 could be run from E12H 1 to D17L 1. This change would introduce a fixed delay of 30 ns that would add to the variable 40 ns and provide up to 70 ns of delay. When these adjustments are made, polarities should be observed since the required signal is a high-going pulse delayed from CLOCK. Further, the tie point chosen should result in the variable delay being set near the center of its range. Once phase adjustment is complete, the centering adjustment can be made (Figure 5-40). This adjustment centers the data and clock pulses under the data and clock gates, respectively, for best margins. Clock and data pulses are not individually adjustable for centering. If data pulses are adjusted under data gate, clock pulses are not necessarily adjusted; whereas, if clock pulses are adjusted under clock gate, data pulses will automatically fall under data gate. Since clock pulse positioning is more criti cal than data pulse location, the clock pulse is recommended for adjustment. The conditions shown in Figure 5-40 occur when the oscilloscope is externally synced on D22F1 (SHIFT ENABLE (1) H), when probe No.1 is connected to D17P1 (CLOCK GATE), and probe No.2 5-53 TIME @ 0.1 fJ.s/cm TO ADJUST CENTERING LOCATE AVERAGE L.E. OF RAW CLOCKS IN THE CENTER OF CLOCK GATE CLOCK GATE (D17P1) READ DATA COAX (RAW DATA) (E14B1) CLOCKS DATA Figure 5-40 Clock Gate (D17P1) vs Read Data Coax (E14B1) during Read is connected to E14B1 (READ DATA COAX). The associated tapped and variable delays then may be adjusted unti I the average leading edge of raw clock pulses (those without base line) is situated in the center of CLOCK GATE. When this adjustment is made, the variable delay C15 is first adjusted to the middle of its range. Then, the one wire run from E14L2 (DATA GATE CLOCK) is removed from the tapped delay D06J1 and is connected to either D06H 1, K 1, L1, or M 1; whichever one puts the waveform closest to the center of its gate. This action constitutes a coarse adjustment upon whi ch a small variable adjustment can be made to place the pulse exactly in the center. In extreme conditions, the N1 tap can be used; in any case, a tap is chosen that allows the C15 adjustment to be fairly near the center of its range. Figure 5-41 illustrates a visual method of identifying a particular header. By using this setup, it is possible to read the bits in any particular header and determine, by inspection, the cylinder, head, and sector designated. The upper trace is RD BIT (l) H (C 19E 1), the fl ip-flop that separates the data from the Read Data Coax; the lower trace is RD DATA COAX (E14Bl), the raw data coming from the disk. In the figure, only the last 18 bits of the header are displayed, the first 18 bits of Os are not shown. This display is setup by first setting the word count equal to two sectors. Then, using A delayed by B, the B sweep is externally triggered with CMPR (1) H (A18Fl). The A trace is externally triggered by FIRST DATA BIT H (D23F1), and the sweep is then moved to the FIRST DATA BIT H for the second header in the two sectors. Finally, with probes 1 and 2, look at RD BIT (C19E1) and RD DATA COAX (E 14B 1) and expand the second header in the two-sector record. 5-54 TIME @ 1 J,Ls/cm " RDBIT (C19El) RD DATA COAX (E14Bl) IIIIIIIIIIIIIIII IIIIIIIII 17 18 HEADER 36 ~ \0\0\0\0)0\1\0\0\0\0\1\0\1\0\0\011\110\0111011\01 , CYLINDER 205 ' ~ I~ I NOT USED HEADER WORD PARITY Figure 5-41 RD Bit (C19El) vs RD Data Coax (E14Bl), Identifying Header As can be seen, the clock pulses appear regularly with occasional pulses occurring between them. Notice that directly above these clumps a bit appears on the upper trace. These are 1 bits of data as separated by the RD BIT flip-flop. Where clumps do not appear, no bit exists on the RD BIT trace; these are 0 bits of data. The constructed word format then may be decoded at sight. Reading from right to left, with each format increment right-justified, it can be determined that Header Word Parity is 0 and the sector is number 5. The next bit position, 0, is not used in RP15. Continuing to the left, Head 3 and Cylinder 205 are identified. 5.17 MAINTAINING CONTROLLER FORMAT (Write Format Generator) The RP15 Write Format Generator is shown in Drawing RP15-0-22. The circuit contains three counting registers that keep track of the various parts of the format (Figure 3-2) during Write operations, and generate control signals to be used by the BR, SR, LPR, and R/'N controls (Paragraphs 5.18, 5.19, and 5.20). Referring to the drawing, the Write Format Generator is made up of a standard BCD counter (Flip-flops FMT GEN 05-08), two binary counters (Flip-flops FMT GEN 01-02 and FMT GEN 03-04), and an AND gate that generates FMT GEN 00 L when FMT GEN 01 or 02 are on a 1. The three registers are incremented by -INC FMT GEN L, which occurs each 37th bit of the format (once each word) during the bit cell time of Write Parity Enable (WPE (1) H) ANDed with VFO CLOCK H and DATA GATE H. 5-55 As shown in Figure 5-42, the BCD counter (FMT GEN 05-08) cycles three times through 30 words of the VFO Sync Area. The BCD counter then stops counting until cleared at Sector Pulse time by SUSP L. Step 1 2 3 4 5 6 7 8 9 10 11 I- Z ::::> o u z « 3: '- o I- Z ::::> o u Z o 3: 1 2 3 4 5 133 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 164 00 01 Format Generator Bit 02 03 04 05 06 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 ~~\.,,- BIN CT BIN CT Figure 5-42 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 07 08 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 Comments 10th Sync Word VFO Sync Area 20th Sync Word 30th Sync Word (Pre-header) Header Word (5,6,7,8 Stop Counting) -WDN Begins Here VFO Data Sync >- Last Post-header Sync Data Field (All Bits Stop Counting) _ _.............._ _--".J BCD COUNT Write Format Generator Count 5-56 The binary counter (FMT GEN 03-04) increments each time the BCD counter is full, i.e., on the 10th, 20th, and 30th sync word when FMT GEN 05 and 08 are both on a 1. On the 30th sync word, FMT GEN 03, 05, and 08 are all set by the process just described. These three conditions ANDed yield the signal PRE HEADER L that conditions 02 for setting and generates Write Sync Bit Enable (WSBE H). This signal says "we are writing the last word of one of the sync areas, II and is used to force a 1 bit at parity time, as described in the R/VV Control, Paragraph 5.20. On the next increment (Step 31), the Header Word is written on the disk, FMT GEN 03-04 step to a binary 3, FMT GEN 02 is set, and Format Generator Bit 00 is raised (FMT GEN 00 L). FMT GEN 03 and 04 now increment four times to produce the VFO Data Sync Area, and on the next increment stop counting (as the format enters the Data Field) until it also is cleared upon receipt of SUSP L. In Step 32, FMT GEN 01 and 02 increment to a binary 2 and stay there until Step 35, when the conditions for LAST POST HEADER SYNC L are met: FMT GEN 01 (1) H FMT GEN 02 (0) H FMT GEN 03 (1) H FMT GEN 04 (1) H. LAST POST HEADER SYNC L increments FMT GEN 01-02 to a binary 3, and generates WSBE H once again to force a 1 bit at the end of the VFO Data Sync Area. On the next increment (Step 36), the disk enters the data field. FMT GEN 01-02 are both set and FMT GEN 03-04 are reset. Note that the data field is decoded by conditions FMT GEN 00 Hand FMT GEN 1 + 2 L; when -FMT GEN 1 + 2 H is present, the disk is decoding everything else but a data field. NOTE The + sign used here and on the drawing does not mean OR, but rather FMT GEN 1 "and" 2 L. The process just described occurs whenever the control is in either a Write All Format (WAF) or a Write All Normal (WAN) mode. In Write Data Normal (WDN) mode, the count begins at Step 32, with the receipt of WDN SET WRITE L. The resultant signal, WDN CNT L, is used to preset FMT GEN 01 flip-flop. The conditions in Steps 5/36 prevai I throughout the rest of the format, through Steps 133/164, and reset upon receipt of the next sector pulse SUSP L. 5-57 5.1S CONTROLLING TRANSFER DIRECTION IN THE PDP-15 (BR and DCH Control) The RP15 BR/DCH Control is shown in Drawings RP15-0-13 and -14. This circuitry interfaces the RP15 to the PDP-15 Single Cycle Break faci lity and develops timing for memory. Referring to Figure 5-43, during Read, when a full word is in the Shift Register, it is transferred to the Buffer Register; at that time, the control will raise a break (BK RQ) request. When the request is granted, the first lS bits of the Buffer Register are transferred to memory; the last lS bits of the Buffer Register are shifted into the first lS-bit positions of the Buffer Register and are then transferred to memory in two back-to-back breaks. During Write, after a word has been shifted out onto the disk, another word is taken from the Buffer Register; at that time, a break request is raised for memory access so that two more words may be transferred from memory. When access is granted, memory wi" transfer lS bits into bit positions lS-35 of the Buffer Register. These bits wi II be shifted into bit positions 0-17, and another lS-bit word will be transferred from memory into bit positions lS-35 of the Buffer Register. The Buffer and Shift Registers are both 36-bit registers; on every transfer, in or out, two lS-bit words must be transferred at a time. The direction of transfer, in or out (IN = into memory, OUT = out of memory), is decoded by the following equations (see Figure 5-44): (OUT) (IN) -RQ IN = FROl (1) . TRANS FUNC RQ IN = FR01 (0) + TRANS FUNC Examining the OUT equation first, the equation states that the function must have a 1 in FR01 leaving the following functions: Write Recal Write All . Write Check 2 3 6 7 Further, the equation states the function should be a transfer function; that immediately eliminates Recal. It can be seen, then, that an OUT transfer is only necessary for functions that appear as Write functions to memory (Write Check appears as a Write function to memory and a Read function to the disk). Inspection of the IN equation shows that is is the NOT condition of the OUT equation, and that all functions are included except Write, Write All, and Write Check. Note that even initiate functions are included in this equation; this is acceptable since the direction of transfer signal is recognized only when a transfer is taking place, which means that the function 5-5S PDP-15 I I MEMORY BUFFER 17 0 , I I BUFFER 0 I REGISTER , 1718 I 35 I t I I I I SHIFT REGISTER 1718 0 DISK I 35 RP02 RP15 o. DATA FLOW DURING 'READ' PDP-15 I I MEMORY BUFFER 17 0 I I II I I L -l I BUFFER 0 t REGISTER 1718 I SHIFT I , I I REGISTER I 1718 0 J 35 I DISK 35 RP15 RP02 09-0317 b. DATA FLOW DURING 'WRITE' Figure 5-43 BR/DCH Data Flow would be a transfer or execute type. This is done by ANDing RQ IN L with DCH RQ (1) L to produce DCH RQ L, whi ch is interpreted in the PDP-15 I/O as the direction of transfer. When an OUT transfer function is executed, general flow is from the BR to the SR. The flow is indicated by three signals called: FORMAT BR TO SR FIRST BR TO SR BR TO SR. 5-59 SR TO BR L END BIT (I) H _ _. r _ -.... CMPR (I) H READ (I) H SWC OVFLO (0) H - - 1 - - _..... SR TO BR H ----1-- WLB ( I) H -SWC OVFLO EN H SWC OVFLO (0) H FMT GEN 02 (1) H - - 1 - - _..... FMT GEN 0 I (1) H NORMAL H BK RQ EN H RQ IN H FR 01 (I) H TRANS FUNC H +3V +3V WSBE H - - - r - - -...... WLB(IlH NORMAL H - PRE-H EADER H - - " ' _ __ _ RQ IN L FIRST BR TO SR L RP15-0-13 NORMAL W LH B(1lHPSWC OVFLO (0) H BR TO SR L FMT GEN 02 (1) H FMTGEN01(1)H WSBE H - - - - }- WLB(I)H~ PRE-HEADER H +3V _ FORMAT BR TO SR L +3V RP15-0-15 DCH REQ (1) L SING CY RQ L DCH RQ L RQ IN L RP15-0-49 15- 0475 Figure 5-44 BR Control Logic, Simplified Diagram The signal FORMAT BR TO SR is generated during Write All Normal or Write All Format functions and serves to transfer the header word from the BR to the SR. The signal is expressed as: FORMAT BR TO SR = WSBE· WLB(l)· PRE-HEADER The WLB (Write Last Bit) signal (created on Drawing RP15-0-06) is present for 400 ns during the time the last bit (bit 35) of each word is being written. The WSBE (Write Sync Bit Enable) signal (created on Drawing RP15-0-22) is present for the duration of the last word written in both the VFO Sync Area (see Figure 3-2) and the VFO Data Sync Area. PRE-HEADER is generated on Drawing RP15-0-22 and inverted on Drawing RP15-0-07. This signal is decoded as all words written prior to the header word. FORMAT BR TO SR is generated during the writing of the last bit before the header word for both Write All Normal and Write All Format Instructions; it transfers the header word from the BR to the SR when necessary. 5-60 The signal FIRST BR TO SR is similar to FORMAT BR TO SR except that it is conditioned by -PRE-HEADER and NORMAL. The signal is expressed as: FIRST BR TO SR = WSBE· WLB(l)· NORMAL· PRE-HEADER Conditions WSBE, WLB(l), and -PRE-HEADER qualify the gate for the last bit (bit 35) written in the YFO Data Sync Area before the first data word. NORMAL eliminates Write All Format functions be- cause the data field for this function does not come from memory. This equation transfers the first data word in the Data Field from the BR to the SR for Write and Write All Normal functions. The signal BR TO SR is also similar to FORMAT BR TO SR in that it includes WLB (1) and NORMAL in its equation: BR TO SR = WLB(l)·NORMAL·SWC OYFLO (O)·FMT GEN 01 (l).FMT GEN 02 (1) The ANDing of FMT GEN 01 (1) (Format Generator) with FMT GEN 02 (1) decodes the Data Field (see Drawing RP15-0-56 or Figure 5-42). SWC OYFLO (0) excludes the Longitudinal Parity Word; the equation then leaves a means to transfer all but the first data word from the BR to the SR for Write and Write All functions. When an IN transfer is executed, general flow is from the SR to the BR, as indicated by SR TO BR L, whi ch can be expressed as: SR TO BR L = END BIT (l)·CMPR (l)·READ (l)·SWC OYFLO (0) READ (1) indicates that the applicable functions are Read, Read All, and Write Check. CMPR (1) eliminates the header word (compare is set after the reading of the header word) and SWC OYFLO (0) "eliminates the Longitudinal Parity Word. END BIT is a signal that is present for 400 ns during the time the word read from this disk is completely assembled in the SR. This equation transfers the SR to the BR for Read and Read All functions. NOTE The SR is not transferred to the BR for Write Check functions; this condition is later gated out. Signals SR TO BR Land FI RST BR TO SR L are also two of the three inputs that create BK RQ EN H. The third input is generated from the equation: WLB(l).SWC OYFLO EN·SWC OYFLO (0)· NORMAL·FMT GEN 01 (l)·FMT GEN 02 (1) 5-61 Note that this equation is identical to BR TO SR with the addition of -SWC OVFLO EN. The latter is the NOT of the AND condition of all SWC bits on a 1. This condition occurs when the next to the last word is being read or written. In the case of BR TO SR, the signal SWC OVFLO EN means that the next to last word is being written a~d the last word is already in the BR; therefore, th~re is no need for another BK RQ in this sector. If the word count is not zero, then the next word wi II be requested at the beginning of the next sector. Before a transfer can be made to or from memory, a Break Request (BK RQ) must be raised. BK RQ is set by SET RQ L, which is generated from the OR of three inputs as shown in Figure 5-45. The first input is called INIT RQ L (Initial Request). This signal supplies the RP15 Buffer Register with the first (or initial) data word{s) for OUT transfers. BK RQ for the remaining data words is self-generating after the initial BK RQ is generated. OUT transfer functions comprise the fpllowing: Write Write All (Normal) Write Check. From the logic in Figure 5-45, the following equation for I NIT RQ L can be written: RQ IN·NORMAL·WC OVFLO (O) • [CMPR(1).FR02{1)+LAST POST HEADER SYNC·FR02(0)·WDE(1)J \ J ""'" \ ~ } READ READ ALL 1 - - - - - - - - - - - . WRITE CHECK ~----------------------------------------~ WRITE L - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- . . . . . WRITE ALL Note in the first expression inside the brackets that all odd functions that can result in CMPR (1) are included. Read and Read All, however, are eliminated because they are RQ IN functions. In the second expression, all even functions that can result in Last Post Header Sync are included; also, the function must be in NORMAL mode. This equation only leaves the functions Write, Write All Normal, and Write Check for which it produces the BK RQ for the first data word transferred from memory in each sector. The second input to SET RQ L is generated from the equation: WPE(O)· PRE-HEADER· [READ ALL + WRITE ALL] PRE-HEADER was described earlier as the time in which the last word of the VFO Sync Area is written. WPE is generated on Drawing RP15-0-06 and is up for 400 ns of each word written during the time the word parity bit is being transferred to the disk. (Note that since the operation is a Write, Read All is excluded.) The timing for this operation is such that an output from this equation is produced at the 5-62 +3V o -WC OVFLO EN H DCH GR (B) L DCH ENA (1) L 1 BACK TO BACK DISK DCH GR H C -SET RQ H 0 CMPR (1) L CLR H WOE (1) L LAST POST HEADER SYNC L FR02 (0) L SET RQ L INIT RQ L - RQ IN L - - - - - - - - - - d i -. . . . NORMAL H - - - - - - I WC OVFLO (0) H - - - - - I WPE (0) H - . . - - +3V PRE -HEADER H READ ALL + WRITE ALL H -~_ _ BACK TO BACK (,) H +3V DISK DCH GR H BK RQ EN H - . . - - DATA GATE H VFO CLOCK H WC OVFLO (1) H - - - - - - - - - - - \ - RQ IN L -----('1----.... BK RQ (1) L --+--~ CLR (B) L SWC OVFLO EN L -----<:L_~ CLR + DPCS +FUNC DLY L RP15 -0-13 15-0476 Figure 5-45 DCH Control Logic, Simplified Diagram trailing edge of the WPE signal that is generated for the Second to Last VFO Sync Area word (i.e., 14.0 tJS before the first bit of the header is written). The third and final input to SET RQ L is given by the equation: BK RQ EN . DATA GATE· VFO CLOCK· WC OVFLO (0) [RQ IN + SWC OVFLO EN] DATA GATE and VFO CLOCK only synchronize BK RQ with Read and Write timing. From the expression in the brackets, the function must either be an I N transfer or an OUT transfer, provided that SWC OVFLO EN is not true. This equation produces BK RQ signals for all words transferred in Read and Read All functions and for words 2-128 of Write and Write All Normal functions. SET RQ L direct sets BK RQ as shown in Figure 5-45, which enables the D-input of DCH REQ. The trailing edge of SET RQ L (-SET RQ H) is used to strobe the C-input of BACK TO BACK. If at this time -WC OVFLO EN H is true (WC = all ones), then BACK TO BACK is set. This condition is true when two or more words remain to be transferred. If, however, the last word of an odd word count (only one word) is all that remains, BACK TO BACK is not set. A short time after BK RQ (l), the PDP-15 I/O wi II respond with a DCH GR (B) H which generates DISK DCH GR H and clears BACK TO BACK (if set). If BACK TO BACK is set, the first DISK DCH GR H wi II keep BK RQ set and another break is requested that wi II result in a second DISK DCH GR H. The second DISK DCH GR H will then clear BK RQ. If BACK TO BACK were not set when the first DISK DCH GR H arrived, then BK RQ would have been cleared at that time. In short, if two or more words are left, BACK TO BACK is set to request two successive breaks. If only one word remains, BACK TO BACK is not set and only one break is requested. BACK TO BACK and BK RQ are cleqred with CLR. TE (Timing Error) is a flip-flop that is set if a break request is still up (BK RQ (1) L) from a previous SET RQ L when the condition for a new SET RQ L exists. The output of the PA, which strobes the C-input of the TE flip-flop, is actually the output of the three input OR gate (see Figure 5-46). TE is cleared with CLR + DPCS + FUNC DLY L. INIT ROLq602 • • Referring to Figure 5-47, another function of SET RQ L is to INTERNAL CONNECTION ~ SET REQ L I direct set BRS SYNC (Buffer Register Shift Sync). The purpose of BRS SYNC is to determine when it is time to shift BR18-35 into BROO-17. As shown in Figure 5-43, this happens for IN 15-0477 Figure 5-46 TE Strobe Logic, Simplified Diagram transfers after the first 18 bits (BROO-17) have been accepted by memory. The trailing edge of DISK DCH GR H (-DISK DCH GR L) fires a PA which is enabled by DCH ENA (1) H to produce 5-64 SET RQ L R P15 - 0 -13 -DCH ENA (B) H BR STB L BR STB A H -RQ IN H ADDR ACC H _~"" RQ IN H BR STB A H CLR L SR TO BR L BR STB B H SET RQ L EN BR L DCH ENA (1) L 50n5 CLR L 110 SYNC L BRS SYNC (0) H CLR BR EN L CLR BR A L INIT RQ L CLR BR B L RQ IN H - EN BR H ADDR ACC L -RQ IN H 15-0478 Figure 5-47 BR Control Logic, Simplified Diagram ADDR ACC L. ADDR ACC L is inverted (not shown) and ANDed with RQ IN H to produce a low signal at the C-input of BRS SYNC. At this time, the D-input of BRS SYNC will be low (-DCH ENA (B) H = DCH ENA (B) L), since DCH ENA was set with the leading edge of DCH GR (B) H. When the C-input of BRS SYNC goes high (trailing edge of ADDR ACC), BRS SYNC will be cleared. It is the actual clearing of BRS SYNC that shifts bits BR lS-35 to bits BROO-17; this operation is common to both IN and OUT transfers. How BRS SYNC gets cleared, however, depends on the direction of transfer; since the actual shifting of BR1S-35 to BROO-17 is common for both directions, it will be described here and referred to later. When BRS SYNC is cleared, BRS EN (Buffer Register Shift Enable) is set. BRS EN (1) H is inverted and parallel fed to both a delay I ine and two inputs of a power driver (M627). The output of the 50 ns delay I ine feeds the other two inputs of the power driver. As long as either of these sets of inputs is low, the 5-65 output EN BR H is true {also EN BR L after inverting}. Note, however, that the output of the delay I ine is ORed with CLR L and I/O SYNC L to produce a clear signal for BRS EN. The output of the delay line also fires a PA which produces BR STB L, BR STB A, and BR STB B. The timing diagram for this circuit is shown in Figure 5-48. Note particularly from this diagram, that all circuit delays are considered to be 0; otherwise, the leading edge of BR STB A and B H falls in the middle of EN BR H. As pointed out in Paragraph 5. 13, this is all that is necessary for the BR to transfer BR18-35 to BROO-17. BRS SYNC (0) H BRS EN (1) H ~ ~- 50 ns-I..._ _________ I _ 50 ns_I~50ns-1 r-~._____________ ENBRH~ BRSTBAaBH ____________ ~F==50ns==11...____________ 15-0479 Figure 5-48 BR Control Timing Diagram Again referring to Figure 5-43, it can be seen that this shift occurs for OUT transfers after the first 18-bit word is received from memory into BR18-35. The BR STB A H that strobes this first 18-bit word into the BR is ANDed with -RQ IN H {equal to RQ OUT} to produce a low pulse input to BRS SYNC. The other BR operations occur as follows: a. EN SR H, the enabling level for transfers from the SR to the BR, is decoded as RQ IN H and -EN BR H. During IN transfers, only two operations can take place in the BR: either it is being loaded from the SR, or the last 18 bits are being transferred to the first 18 bits; therefore, at all times other than EN BR, the operation must be EN SR. b. EN lOB H, the enabling level for transfers from the I/O bus to the BR, is decoded as a -RQ IN H and -EN BR H. During OUT transfers, at all times other than EN BR, the BR looks to the I/O bus for data. The signals EN SR and EN lOB by themselves, of. course, can do nothing. As explained in Paragraph 5. 13, they must be accompanied by BR STB A&B H. The BR STB A&B H for EN lOB is generated by the AND condition of DCH ENA (1) H and lOP 4 {B} H {produced by the PDP-15 I/O for all OUT transfer words}. The BR STB A&B H associated with EN SR is generated by the following equation: SR TO BR • SET RQ . RQ IN 5-66 As stated before, SR TO BR L, whi ch is generated for Write Check function, will be gated out in a later equation because the SR is not actually transferred to the BR in a Write Check function. Since a Write Check function produces a -RQ IN, the signal SR TO BR cannot produce an output from the above equation. In Figure 5-47, CLR BR A&B L is generated from the OR of CLR L, the trailing edge of I NIT RQ L, and the trailing edge ofCLR BR EN L which is described in Paragraph 5.19. Figure 5-49 shows a simplified block schematic of the M 104 I/O Bus Multiplexer module and the signal names that apply to the BR and DCH Control. A timing diagram and general description of this module are given in the PDP-15 Module Manual, DEC-15-H2EA-D. DCH REQ (I) H DCH ENA (1) H DCH GR (B) H -------------1----_-1 o BK RQ (1) H - - . - - - - - - - - - 1 DCH I REQ 1/0 SYNC (B) H -t-------~~_+--+-----------------+______,f___' CLR H -t----~~ DCH ENA (1) L ~---+__------------ DCH REQ (1) L +5V >----+-- DCH EN OUT H DCH EN IN H ~----"------I RP15-Q-14 15- 0480 Figure 5-49 5.19 M104 Block Diagram for DCH CONTROLLING TRANSFER DIRECTION IN THE RP02 (SR and LPR Control) The SR and LPR Control is shown in Drawing RP15-0-15 and in Figures 5-50 through 5-52. LPR TO SR L is generated from WLB (1) ANDed with SWC OVFLO (1) (see Figure 5-50). LPR TO SR is used to transfer the generated Longitudinal Parity Register word for a given sector into the SR, where it is then transferred to the disk. It is, therefore, obvious that the transfer should occur after the last bit (WLB) of the sector (SWC OVFLO (1» has been written. The inversion of LPR TO SR L generates LPR EN H, which gates the 0 sides of each LPR bit to the D-input of the SR. 5-67 WLB(1)H LPR EN H SWC OVFLO (I) H LPR TO SR L BRTOSRLDFIRST BR TO SR L FORMAT BR TO SR L BR EN H +3V SHIFT EN (I) L -t>-- SR EN H +3V L PR TO SR L --t"'!_ _ BR TO SR L FIRST BR TO SR L FORMAT BR TO SR L ----"'-_ _ STBSRAH VFO CLOCK H DATA GATE H SHIFT PULSE (I) L STB SR B H +3V RP15- 0-15 t!!-048t Figure 5-50 BR, SR and LPR Enable and Strobe Signals, Simplified Diagram In Paragraph 5. 18, the signals BR TO SR L, FIRST BR TO SR L, and FORMAT BR TO SR L were generated and used to initiate a BK RQ. In this paragraph, as shown in Figure 5-50, these signals are ORed to produce BR EN H, which gates each of the 36 BR bits to the D-inputs of the SR. The four signals just described are: LPR TO SR L BR TO SR L FIRST BR TO SR L FORMAT BR TO SR L These signals all occur at different times and for different reasons. However, they are ORed to produce a condition which, when ANDed with VFO CLOCK H and DATA GATE H, generates STB SR L and the appropriate STB SR A & B H. Recall from Paragraph 5. 13 that STB SR A & B H, and the appropriate enable (BR EN or LPR EN), are all that is required to transfer the BR or LPR to the SR. SHIFT EN (l) L (generated on Drawing RP15-0-05) is discussed in Paragraph 5.20. At this point, assume that SHIFT EN (1) L is true whenever it is desirable to shift the data in the SR. The signal SHIFT EN (1) is inverted to produce SR EN H which gates SR bit (N + 1) to the D-input of SR bit (N), i.e., SR35 to SR34, SR34 to SR33, etc.). 5-68 Before the SR can actually be shifted, STB SR A & B H must be generated at SR EN H time. SHIFT PULSE (1) L, generated on Drawing RP15-0-05, is set for 50 ns each time SR is shifted. This pulse is ORed (along with STB SR L) to produce the necessary STB SR A & B H for shifting. The control signals for the LPR are shown in Figure 5-51. As discussed in Paragraph 5. 13, the LPR can be IIloaded ll from two sources: CAR-HAR-SAR, or SR. The LPR has two basic functions: a. To generate longitudinal parity at Write 'time and generate a check longitudinal parity at Read time, or b. To compare the header word read from the disk with that contained in the CAR-HAR-SAR. FMT GEN 1 + 2 L = D - RPI5-0-15 LPR STB EN H LAST POST HEADER SYNC L - HDR TO LPR EN H VFO CLOCK H DATA GATE H LPR STB A H FIRST DATA BIT L HEADER H -i>: LPR STB L HDR TO LPR EN L - S R TO LPR EN H --d--------) RD WORD END L WPE (1) H SWC OVFLO (Q H - - - - - t _ _ §> - HDR TO LPR EN H _ LPR STB EN H -~----- -LPRSTO O L - 1 I ~._ _ _ READ GATE(1) H Figure 5-51 ~ --LJ' CLR SR L 15-0482 LPR Control Signals, Simplified Diagram The first LPR function (a.) requires an LPR STB for each word written or read in a sector. FMT GEN 1 + 2 L (Format Generator bit 01 and 02 both on a 1, see Paragraph 5. 17) is ORed with LAST POST HEADER SYNC L to decode the Data Field during Write operations, and is used to produce LPR STB EN H. LPR STB EN H is ANDed with WPE (1) and SWC OVFLO (0) to produce one of the two signals that generate -HDR TO LPR EN H (same as HDR TO LPR EN L). This signal is then inverted to produce SR TO LPR EN L (same as -SR TO LPR EN H). The other signal that will produce -HDR TO LPR EN H is RD WORD END L. This signal is generated on Drawing RP15-0-05 and is the AND of READ (1) and END BIT (1). Again, SR TO LPR EN L is produced, this time for READ, which now enables the SR bits to be XORed into the LPR if an LPR STB A & B H 5-69 were present. LPR STB A & B H is generated for this operation by the AND of -HDR TO LPR EN H, VFO CLOCK H, and DATA GATE H. At this point, note that the LPR is never IIloaded but rather XORed from either the CAR-HAR-SAR or li the SR. If the LPR were first cleared, then the effect would be a "Ioad ll • The signal CLR SR L is generated from the equation: LPR STB B . READ GATE (l) This equation states that CLR SR L is generated for any LPR STB B (actually the trail ing edge of LPR STB B which is -LPR STB B L) except those that are a result of a word written. Therefore, any word that is read from the disk and XORed into the LPR by LPR STB B will, in turn, clear the SR. The second LPR function (b.) requires the LPR to be cleared before reading the header word. Referring to Figure 5-52, every SUSP L clears the LPR. As shown on Figure 5-51, since no condition exists for -HDR TO LPR EN H, the HDR TO LPR EN L must be true. Approximately 350 I-'s after SUSP, the header latch is set, resulting in HEADER H (this is explained in detai I in Paragraph 5.20). As the read heads approach even closer to the header word, a sync bit is read, which results in FIRST DATA BIT L. (This is also explained in Paragraph 5.20.) FIRST DATA BIT L fires a PA, which is enabled by HEADER H to produce LPR STB A & B H. Since the LPR has previously been cleared, this results in loading the CAR-HAR-SAR into the LPR. The contents of the CAR-HAR-SAR are now in the LPR and the header word is being read and assembled in the SR. When the header is completely assembled in the SR, RD WORD END L produces (indirectly) SR TO LPR EN L, which results in LPR STB A & B H. This means that the header word, which has been read from the disk and is presently assembled in the SR, wi II be XORed in the LPR with the contents of the CAR-HAR-SAR. NOTE When the CAR-HAR-SAR was XORed into the LPR, the first 18 bits of the LPR remained clear, while the second 18 bits contained the contents of CAR-HAR-SAR. If the header read is equal to the desired header address, then the LPR will be all Os. This is expressed as: If CAR-HAR-SAR = Header Word, the CAR-HAR-SAR-¥- Header Word = Os. 5-70 CLR SR A L --1-- WLB (1) H - NORMAL H SWC OVFLO (0) H - PRE-HEADER H - - 1_ _ CLR SR L - - - 0 1 CLR L ~.....-.-ar CLRSRBL HDR END (0) L CLR LPRAL SUS P L - - i : l ' - _ " ' " +3V CLRLPRBL LPR STB B H MAINT (1) L STB SR L MAINT (0) L CLR BR EN L WC OVFLO (1) L - RQ IN L RPt5-Q-t5 '~-0483 Figure 5-52 BR, LPR and SR Clearing Signals, Simplified Diagram Actually only the last 18 bits are checked for comparison by a large AND gate shown on Drawing RP15-0-27. The output of this gate is LPR B EQ ZERO H. Figure 5-52 shows the clearing signals for the BR, LPR, and SR Registers. As pointed out previously, SUSP L generates CLR LPR A & B L as does CLR L. The third input to CLR LPR A & B is the trailing edge of HDR END (1) H (same as HDR END (0) L). HDR END is a signal that is present for 400 ns at the end of each header word read, as described in Paragraph 5.20. The trailing edge of HDR END (1) H also produces CLR SR A & B L as do CLR SR Land CLR L. The fourth input to CLR SR A & B L is the equation: WLB(l) • NORMAL· SWC OVFLO (0) • PRE-HEADER This equation decodes the end of each word in the data field. The equation is good for Write All format function and does not include the header words or LPR words; therefore, at the end of each data field word w.ritten, the SR is cleared. 5-71 CLR BR EN L is generated by the AND of two inputs. The first input is expressed as: MAINT (0) . LPR STB B + MAINT (1) . STB SR This equation is a result of timing considerations between maintenance and non-maintenance modes. Of interest is the non-maintenance input which, when ANDed with the second AND gate input, yields the following: MAINT (0) . LPR STB B . rNC OVFLO (1) + RQ IN) This equation can be divided to produce: a. MAINT (0) . LPR STB B • WC OVFLO (1) or it can be divided to produce: b. MAINT (0) . LPR STB B . RQ IN Equation a. states that in the non-maintenance mode each LPR STB B (which occurs once per word) after WC OVFLO (1) clears the BR. Equation b. states that the BR is to be cleared after each transfer of BR to SR, and after the SR is XORed into the LPR on Write operations. Therefore, a record that ends in the middle of a sector will be filled with Os. 5.20 CONTROLLING TRANSFER DIRECTION IN THE RP15 (R/'N Control) The Read/'Nrite Control is shown in Figures 5-53, -56, -59, -60, -62, and -63 and in Drawings RP15-0-05, -06, and -07. In addition, timing diagrams are included for quick reference (see Figures 5-55, -57, -58, and -61). Referring to Figure 5-53, FR01 EQ FR02 H, generated on Drawing RP15-0-18, is inverted to produce FROl EQ FR02 L. The NOT condition of this signal, -FROl EQ FR02 H, is ANDed with FROO (1) H to produce READ ALL + WRITE ALL L. This can be shown by decoding as follows: EQUATION (FROl EQ FR02). FROO(l) = READ ALL + WRITE ALL MEANING [FROO=lJ AND [FR011 FR02J FROO FROl o 1 FR02 1 o 5-72 = READ ALL = WRITE ALL FRI EO FR2 H READ ALL + WRITE ALL L FROO(O)HDFR 01 (1) H FR EO WRITE L FR 02 (0) H FR EO SEEK L TRANS FUNC H RECAL + IDLE L READ ALL+WRITE ALL H FR 01 (0) H SUSP H DATA FIELD EN H CMPR (1) H L...-.._ _ _ _ _----Q R TRANS FUNC H - - r - -........ -READ ALL+WRITE ALL H 0 -FR EO WRITE H CMPR (1) H - " ' - - - =L::i TAG RETART H ~ ) JB ON (0) H IDLE (1) H F R EN SET L TRANS FUNC H FR EN CLR L . _--L_..... 1. 5 JlS o I 0 III ~ FUNC DLY H • - FUNC DLY L INITIATE H RP09-0-07 15-0484 Figure 5-53 Read,/Write Sector Decoding Logic, Simplified Diagram This type of decoding can be used throughout this paragraph to decode the logic equations given. It is included here as an example for future reference. FR EQ WRITE L is given by the AND condition of FROO (0), FR01 (1), and FR02 (0). Two signals called FR EQ SEEK Land RECAL + IDLE L are also generated on Drawing RP15-0-1S. The signals are ORed to produce INITIATE FUNC H. The NOT condition of INITIATE FUNC H (-INITIATE FUNC L) is inverted to produce TRANS FUNC H. These four signals: READ ALL + WRITE ALL L FR EQ WRITE L INITIATE FUNC H TRANS FUNC H, are basically all that must be decoded directly from the Function Register (FR) to control the flow of Read and Write states once they have been entered. With these signals, it is possible to decode when 5-73 the information coming from the disk (Read State) is part of a Data Field Area. DATA FIELD EN is given by the OR of two equations, one of which is: TRANS FUNC·(READ ALL + WRITE ALL}.FR EQ WRITE·CMPR (1) After reading the desired header, the CMPR flip-flop is set. Note that this equation incl udes the Read and Write Check functions, but does not include the Read All function. This is because the desired Data Field for a Read All function is not that area that follows the header word which sets CMPR, but rather the area that follows the next header word in line as shown in Figure 5-54. I HEADER I AREA 14' 1 I AREA It' 2 HEADER CMPR (1) H SUSPH~~__________________~rl~___~_______________~ DATA FIELD EN H . DESIRED DATA FIELD 15-0485 Figure 5-54 Read All Function, Desired Data Field The first input to DATA FIELD EN H gives the above condition. The SET/RESET flip-flop is set with SUSP H AN Ded with CMPR (1) H. The 1 side high of this flip-flop is ANDed with FR01 (O) Hand READ ALL + WRITE ALL to produce DATA FIELD EN H. Actually, DATA FIELD EN H is not the decoding for Data Field, but rather the enable level. Data Field will be decoded later in this paragraph. Control remains in the Idle state unti I a DPLF, DPLO, DPLZ, or DPCN instruction is issued. At that time one of two (or both) signals are generated (shown on Drawing RP15-0-21), called FR EN SET L and FR EN CLR L. These signals will fire a 1.5-l-'s delay whose output is FUNC DLY H. When the delay times out, -FUNC DL Y L fires a PA, which is enabled by the SRA bit 08, GO (1) H. The output of the PA is gated with -ERR FLG; if an error were present, the signal would end at this point. However, if there is no error condition, the signal is further gated with TRANS FUNC H or INITIATE FUNC H to produce EXECUTE L or INITIATE L, respectively. These signals go to the Major State Control (Paragraph 5. 14) to perform their respective functions. 5-74 Note from Figures 5-21, -22, -23, -24, and -25, that an EXECUTE L signal always results in a Read or Write state. Also, note that one other way to fire FUNC DLY H (shown in Figure 5-53 and in the above figures) is the equation: TAG RESTART·JB DN (O).IDLE (l)·TRANS FUNC This event can occur many times in one transfer, depending upon how many sectors are required to finish the record. As previously stated, since this is a result of TRANS FUNC, EXECUTE L will result in Read or Write states. It is likely that Clear Head and Seek will be the states immediately after EXECUTE L. The timing diagrams for these states are shown in Figure 5-55. These states were discussed in detai I in Paragraphs 5.14 and 5. 15. In Paragraph 5.14, Figures 5-21 through 5-25 should be helpful in understanding these sequences and should be referred to frequently to avoid confusion. The ReadI'Nrite Control also defines the Header and Data Field areas; this logic is shown in Figure 5-56. When SUSP H arrives during a Read state, a 350-l-'s delay is fired. When this delay times out, it fires a PA which is conditioned by READ GATE (1) H. The output of this PA, SECTOR DLYD L, sets a crosslatched gate called HEADER H/L. HEADER L is ORed with DATA FIELD L to produce VFO ENABLE H. VFO ENABLE allows the VFO to separate the data pulses from the clock pulses on the Read Data Coax signal line. The data pulses are saved in a flip-flop called RD BIT, which will be described later in this paragraph. At this time, a flip-flop called END BIT is cleared, VFO ENABLE H is true and, when RD BIT is first set, a cross-latched gate called FIRST DATA BIT H/L is set. Figure 3-2 shows that this occurs one bit cell prior to the first bit of the header word. Thirty-six bit cells later, EN D BIT will be set. The AND condition of HEADER H and END BIT (1) H clears FIRST DAT BIT latch, enables the setting of HDR END, and fires a 50-l-'s delay. HDR END will be set 400-ns later with CLOCK H, and then be cleared again, in another 400 ns, with CLOCK H because END BIT will have been cleared. However, while HDR END is set for 400 ns, it in turn clears HEADER H/L, which results in -VFO ENABLE H. A glance at the last four paragraphs shows that HEADER H/L was set soon enough and long enough to look only for a header word. Also, the FIRST DATA BIT latch was set at the first sign of a nonsynchronizing area (Header or Data Field), and again cleared upon the entering of a synchronizing area. This timing is shown in detai I -in Figures 5-57 and 5-58. 5-75 r--I CLR HEAD (1) H _ _ _ _ _~ TAG RESTARTH _ _ _ _ _~r__l~ IN SET SEEK L r - - 1 J.lSec.---j J.lSec.---j DPLF _________________________________________________________________________________ L~ EXECUTE L U LATCH H I M401 CLK H t SET SEE K L _______----, LJ SEEK (1) H _ _ _ _ _~ ~ LATCH H _ _ _ _ _--' ~ M401CLKH _________t~ ______~t________~t________~t________~t_______________________________ TAG EN (1) H _ _ _ _ _--J ~ t t t ~ TAG EN (I) H TAG 1 (1) H TAG 2 (1) H TAG 1 DLYD H BUS GATE I L TAG 1 (Il H _ _ _ _ _--' TAG 2 (I) H _ _ _ _ _ _ _ _ _ _ _ _ U TAG GATE I L ~ BUS GATE 1 L _ _ _ _ _ _ _ _.., BUS GATE 2 L ~ TAG GATE 1 L _ _ _ _ _ _ _ _ _ _ _ _ _---, TAG GATE 2 L ~ CAR STB L ___________.., IL TAG RESTART H SET CV LIN DER L _ _ _ _ _ _ _ _ _ _ _ _ _---, EXECUTE (L) BUS GATE 2 L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..., U ~ CLR HEAD (1) H TAG GATE 2 L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _, r-r-- UNIT BUS 03 L UN IT BUS 02 L _______________________________..., CONTROL CONTROL L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-.., SURDY H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---. ~ + RESET HEAD REG IN RP02 RP02 PERFORMS SEEK MAX OF 80 ms~ ~ BUSY ~--------------------~)lrJ----~ SET READ L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __________________________ ~ LJ READ(I) H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 15-0486 CLR HEADS TAG GATE TIMING ~ ~ SEEK TAG GATE TIMING Figure 5-55 Timing Diagram Number 1 5-77 READ(l)HD SUSP H ~ o RD BIT (1) H END BIT (0) H VFO ENABLE H o p-- SEC~R O~O 350,. 1\111 >---,--- FIRST DATA BIT H 1-I I I L READ GATE (1) H -HE::R~ SECTOR DLYD L FIRST DATA BIT L HEADER H END BIT (1) H RP15-0-05 HDR END (1) L SET IDLE L L __ _ DATADFIELD L VFO ENABLE H HEADER L HDR DLYD L +3V I I -- -- --:AT::;;LD:-) HDR DLYD L I I L __ - - ::'A=D~ RP15-0-05 LP TEST (1) L SECTOR END L LP WRITE (1) L +3V RP15-0-07 SECTOR END L SET IDLE L 15-0487 Figure 5-56 Header and Data Field Logic, Simplified Diagram At this point in the sequence, the 50-l-'s delay mentioned above is sti II timing out. After this delay has timed out, it fires a PA that is conditioned by DATA FIELD EN H. The output of this PA, HDR DLYD L, sets a cross-latched gate called DATA FIELD H/L. DATA FIELD L is ORed with HEADER L to produce VFO ENABLE H. Again, VFO ENABLE H allows the first data bit (which comes along on the Read Data Coax line) to set FIRST DATA BIT H/L. However, this time, this bit is just one bit cell before the first bit of the Data Field as shown in Figure 3-2. DATA FIELD, VFO ENABLE, and FIRST DATA BIT all remain true until the Data Field has been completely read. When this happens, a fl ip-flop called LP TEST will be set for 400 nSi on its trai ling edge, a PA will be fired to produce SECTOR END L. (Note that SECTOR END L can also be produced by the trailing edge of LP WRITE.) SECTOR END L clears DATA FIELD H/L, resulting in -VFO ENABLE H (or VFO ENABLE L). VFO ENABLE L, in turn, clears FIRST DATA BIT H/L. 5-79 PRE-HEADER SYNC ~ ~14------------ HEADER WORD ------------.l-II4.---- POST HEADER SYNC -----~+14-- DATA AELD ~ SUSP SECTOR n. FORMAT H ~ READ (1) MARKER 2 n 3 18 ZEROS ~ WORD PARITY ~--~~r----~ ~ MARKER BIT __________________________ n ~ ~-------------- H --------------------------------~~----------------------------------------- 350)lS DELAY H - - -......... \~~-------------------------------------------------------------U SECTOR DLYD L - - - - - - - -... HEADER H _ _ _ _ _ _ _ _ _..1 VFO ENABLE H _ _ _ _ _ _ _ _..1 DATA GATE H _ _ _ _ _ _ _ _ _.... t t t t 1. t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t -t t t t t t t t t t t t t t t t t t t t t ___ t ____ t CLOCK H __________________ ~ ____ ~~ ____ ~ ___ ~ ___ ~ _ __L_ _ _ __L_ _ _ _ ~ ____ ~~ _ _ _ _L__ _ _ ~ ____ ~ ____ ~ ___ ~ ___ CLK DLYD H _ _ _ _ _ _ _ _ _ _ _ _ _~_ _~_ _~_ __ L_ _~_~-L---L---~---L---L--~--~~---~---LLAST MARKER RD BIT (1) H _ _ _ _ _ _ _ _ _.... RDP (1) H _ _ _ _ _ _ _ _ _ _MARKER _ _ _----' I 1 ( I ~ ____ ~ __ _L_ _ MAR KER-.f DATA BIT H ________________...... SH I FT EN (1) H _____________________----1 LAST DATA BIT n n ~ r--Jl0 SR35h END BIT (1) H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ n. MARKER B~ TO SR35 EXTRA SHIFT PULSE 'iL HDR END (1) H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~ -.fl MARKER BIT TO SR35 SHIFT PULSE (1) H _ _ _ _ _ _ _ _ ____ __ __ _ _ _...... FIRST DATA BIT TO SR35 ~ FI R ST ---=r-t TDATA B'f~:ARITY BIT MARKER:rr:=: ~~ .--------------'1) \-~- 50us DLY H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--------------------------------~ HDR TO LPR EN L ______________________________________________________ LPR STB L -------------------~r_------------------------------------------~r_--------------------------SR XOR LPR LOAD CYL,HEAD,SECTOR REG.TO LPR ZERO H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..1 CMPR (1) H ______________________________________________________ DATA PULSE (1) H ~ 2L~A~S~~ ~_IT_Y_B_IT_____________________________________ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~1 ~ I 1 L....J 2 ~ ~ L-J ~ PARITY (1) H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----1 PARITY BIT TEST PARITY H ______________________________________________~nL PARITY F/F MUST ALWAYS END UP ON A ONE ________________________________--------------------- DATA FIELD EN H _________________________________________________________________ HEADER DLYD L ~ LPR B EQ ~__i ---------------------------------------------------------------------------------,LJ DATA FIELD H ____________________________________________________________________.....1 CLR SR AND LPR _________________________________________________________________________~nL ____________________--------------------15-0488 HEADER TIMING Figure 5-57 Timing Diagram Number 2 5-81 POST HEADER SYNC-+! -l 400n5 r- """-t------LAST DATA WORD ----.~I.-----LONG PARITY W O R D - - - -....I MARKER BIT DATA GATE H ~ t t t__tL-~-L~_L-~-L~_~~_L~_L-~-L~_L-~-L~~ t t t t __tL-~t__t~~t__t~~t__t~~~t~t~~~~~~~ t t t t t t t t t t t t t t ~ rI t t t t __t~~~~ CLOCKH ____-Lt____~t____~t____~t~___t~__~~r--~--~~--~----~--~-__ ~ __ ~ ____ ~ ~ ~ ~_ trr t t t t t t t t t t t t t~ t )) tf( CLKDLYDH ____~t~___tL___~t____~t____~t____~,~--L---~----~----~--_L __--L---~----~ ____ ~___L ___ t ~t ~ t t t t t t t t t t t t II VFOCLOCKH __~t _ L_ _ _ _ __ ____ ____ L __ _ _ __ L_ _ _ _ ____ _ _ _ _L _ DATAFIELDH _________________________________________________________________________________________________________________ VFO ENABLE H ___________________________________________________________________________________________________________________ RD BIT (1) H ______~ RDP (1) H __________~ FIRST DATA BIT H ______~r-------------------------~f)~'------------------------------~f)~'-------------------------------------------D A TAP U L S E (1) H ____________---' PA R I T Y (I) H ____________---' SH 1FT EN (1) H ____________' SH 1FT PULSE (1) H ________________..... S R EN H ____________' END BIT (1) H ________________________________________________~r____l~ __________________________ TESTPARITYH ________________________________________________~n ~r____l~ n~ SRTO LPREN H ________________________________________________~r____l LPR STB L r____l~ ________________________ U~--------------------------- U Ur-------------------------- CLRSR L - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - , U SRTOSR L ________________________________________________ ________________________ _____________________________ ~~ ~~----------------------- BR STB L------------------------------------------------~U U~----------------------------- SET RQ L-----------------------------------------------------,U~------------------------------~U~--------------------------INC SWC H ________________________________________________~n~ ______________________________ OVFLO(I)H __________________________________________________________________________________ _Jn~ ____________________________ ~ READ TIMING 1--400n5-1 PARITY BIT DATA GATE H READ DATA COAX H CLOCK H ______-----'n~ _____ ____ n CLOCK DLYD H _______..... DATA PULSE (I) H ----.J ----.J PARITY --.J RD BIT (I) H (I) H L-.J L-J _______ ....In~ ~n~ n n ~ ______ ~n~ ___________ n . . . _________ _Jr----l~ ______________ RDP (1) H ________..... SHIFT BIT 33 SHIFT PU LSE (1) H n~. . SHIFT BIT 34 _ _ _ _~n SHIFT BIT 35 n~ ________~n~___________ END BIT (1) H ________________________________________---' TEST PAR I TY H ________________________________________---'n~ _________ r--------- ------------------------------~ AT THIS TIME PARITY ERROR WOULD BE DETECTED FOR THE WORD SETTING EITHER FEE OR WEE F/F WORD PARITY SENSE TIMING 15-0489 Figure 5-58 Timing Diagram Number 3 5-83 Note from the preceding paragraphs once again, that, DATA FIELD has been set soon enough, and long enough, to encompass only the Data Field. Also, VFO ENABLE H and FIRST DATA BIT H/L were true to enable the reading of the non-synchronizing areas ·only. The timing for the Data Field is shown in detail in Figure 5-58. Note that HEADER and DATA FIELD are cleared with SET IDLE L. In the discussion thus far, the Sector has been divided into Header and Data Field areas. Smaller segments of these areas (36-bit word plus parity bit) are decoded as shown in Figure 5-59. SR 00 (1) H RP15-0-05 SHIFT EN (1) H FIRST DATA BIT H FIRST WRITE (1) H CLOCK DlYD H WlB (1) H CLR H ClR(B) l SHIFT PULSE (1) H -............ +3V CMPR (1) H READ (1) H SWC OVFLO (1) H CLOCK H ClK (B) l RD WORD END l TEST PARITY l END BIT (1) H TEST PARITY H READ (1) H 15-0490 Figure 5-59 Word Plus Parity Decoding during Read, Simplified Diagram The D-input for SHIFT EN is conditioned by the OR of FIRST DATA BIT H or FIRST WRITE (1) H. For Read states, FIRST DATA BIT H is true for the entire Header or Data Field areas. Therefore, when in the Read state, SHIFT EN is set on the clock pulse (CLOCK H) following FIRST DATA BIT H and remains set until the clock pulse following -FIRST DATA BIT H (or FIRST DATA BIT L). Also, each clock pulse following the setting of SHIFT EN sets SHIFT PULSE which will then clear itself through a 50-ns delay. For Read state then, SHIFT PULSE (1) occurs at each CLOCK H during SHIFT EN. 5-85 Since the SR is cleared before reading a word, then END BIT will also be cleared, because SROO would be on a 0 at CLOCK H time. Also, just before reading a word, a 1 bit is placed in RDP (Read Data Pulse) which is the flip-flop that feeds SR35. This is done initially by the cue bit just prior to the Header or Data Field (see Figure 3-2). After that, this bit is recycled to produce the 1 bit at the beginning of each 36-bit word. RDP wi II be described later in this paragraph, but its function at this point in the sequence is to feed data to the SR (SR bit 35), the first bit prior to each word always being a1. Thirty-seven shifts later, END BIT will be set with the AND of SROO (1) H and SHIFT EN (1) H. Since everything following this first bit is either data or parity, the data word must now sit in the SR and the parity bit in the parity flip-flop. Because this operation cycles for each word, END BIT (1) H can be used to mark the end of a 36-bit word. END BIT (1) H is ANDed with READ (1) H to produce RD WORD END L, TEST PARITY L, and TEST PARITY H. Note that END BIT is used to generate SR TO BR H on Drawing RP15-o-13, which then generates INC SWC H on Drawing RP15-0-23. END BIT, therefore, keeps track of the number of 36-bit words read in a sector. END BIT also detects when it is time to test the longitudinal parity word. This is done by first detecting the following equation with the leading edge of END BIT (1) H: CMPR (l)·READ (l)·SWC OVFLO (1) This equation occurs when the parity bit of the longitudinal parity word has been read. Then, 400-ns later, LP TEST is set with CLOCK H. Note also from Figure 5-59 that SHIFT EN can be cleared by the following equation: CLOCK DLYD H·WLB (1) + CLR When in the Write state, the sector must also be broken into 36-bit words plus parity, in a manner similar to Read state. When the Write state is entered, the next CLOCK H sets FIRST WRITE (shown in Figure 5-60). One clock pulse later SHIFT EN is set as shown in Figure 5-59. SHIFT EN (1) L is then inverted on Drawing RP15-0-15 to produce SR EN H. Referring to Figure 5-60, SHIFT EN (1) L fires a PA that is enabled by FIRST WRITE (1) H to produce SET RDP L which sets the RDP flip-flop. One clock pulse later, WDE is set because of the AND condition of SR EN H and WRITE (1) H at the D-input. At this same clock pulse time, SHIFT PULSE is set and cleared to shift the bit in RDP into SR35 and SROO into END BIT, where it wi II then be written. Thirty-four more shift pulses wi II place the bit, which started in RDP, in bit 01 of the SR. All bits after the first 1 bit in RDP wi II be Os unti I the next SET RDP L signal. 5-86 I-Pl;:-;- - - - - - - - - 1 IDLE (0) H I WLB EN L SR 35 (0) H - _ - . • • • • SR02 (0) H WLB EN H I I I WLB (0) H WOE (I) H I +3V SUIP H I SUSP L I I L __ ::O::F::L~ _ _ _ _ J +3V SR EN H WRITE (1) L FIRST WRITE (1) H SWC OVFLO (1) H LP WRITE (1) L +3V------~------------~~-- WRITE (1) H WLB (1) H LP WRITE EN (1) L WLB (1)H CLR (B) L~+--_+_-----+_--+-----------+-----+-----l CLOCKH--+--------~-------------+-----~ '---------------- SHIFT EN (1) L - D - - - n - ~ FIRST WRITE (1) H Figure 5-60 SETROPL RP15-0-06 15-0491 Word Plus Parity Decoding during Write, Simplified Diagram At this point in the sequence, the conditions set are WRITE (1), SHIFT EN (1) (which produces SR EN H), FIRST WRITE (1), WDE (1), and WLB EN H/L. WLB EN H/L is present when SR bits 02 through 35 are cleared, WDE is set, and WLB is cleared (see Figure 5-61). Following this timing diagram, the next CLOCK H produces the 36th SHIFT PULSE (1) H whi ch sets WLB (disables WLB EN); at CLOCK DLYD H time (50 ns later), WLB (1) H clears SHIFT EN flip-flop. WlB (Write last Bit) means that the bit which started in RDP is now in bit SROO; therefore, the bit which was in SR35 must be in END BIT and in the process of being written. The next CLOCK H will now clear both WLB and WDE, set WPE (Write Parity Enable), and reset SHIFT EN; but there will be no SHIFT PULSE (1) H because SHIFT EN was on a 0 at CLOCK H time. However, at this time, the leading edge of SHIFT EN (1) L again fires a PA which is enabled by FIRST WRITE (1) H to produce SET RDP L. SET RDP L then sets RDP and the cycle repeats. NOTE Another CLOCK H would produce the~fj,rst SHIFT PULSE (1) H for the next word, which would then set WDE. 5-87 WRITE (HEADER PARITY BIT) READ DATA COAX H DATA GATE H TAG GATE TIMING a CONTROL READ TAG GATE ~~-------------------------------------------SET READ L VFO ClK H READ (1) H LATCH ClK H ClK DlYD H L M401 CLK SHIFT PULSE (I) H TIMING ~~------------------------------------~~ ~)-------------------- ~.--------------------------------------~~ ~)~--------------~~ ~,----------------------------~~ ~)----------------- t i t t t __~____L-__L-__~__-L______________________~~ ----1 H ----1 ~ ____________________ --;~ ~)---------------------- l~j ______________________ TAG EN (1) H END BIT (I) H TAG I (1) TEST PARITY H FIRST DATA BIT H TAG I DLYD H BUS GATE 1 L lPR STB l ~ TAG GATE 1 L lPR B EQ ZERO L ~\---------------------- L -________________________~) ~)---------------------- TAG 2 (1) H SHIFT EN (1) H L-______________________________~~ BUS GATE 2 L -------------'l~ ~~- - L-J~------------------------------~\ (~J---------------------______________________________~r L. L (_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~r___ )r TAG GATE 2 L HDR END (1) H __________________________~r L. ,r ________________~r___ Jr CMPR (1) H TAG RESTART H READ (1) H RO+ER H HAR STB L WRITE (1) H - - - - - - - - - - - - - - -..... LATCH L M401 CLK ~ t t SET HEAD L 1-- 11'5 --l t t t ~ ---, ------------------------------~) ~~---------------------- L-J-----------------------------~~ (~j------------------- . -__________________________________~~ l~j----------------,~ READ GATE (1) H UNIT BUS 01 L TAG EN (1) H UNIT BUS 05 L TAG 1 (1) H ____________________________~r l.( _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ L. J '" L ______________________________~r ~r-----------------.....lr--J I CONTROL TAG 2 (1) H - - - - - - - - - - - - - - - - - - - - - - ' _.....lr___ L -______________________ BUS GATE 1 L ~)~~----------------'r--- TAG GATE 1 l BUS GATE 2 L -----------------------------, TAG GATE 2 L -------------------------------~ WRI TE GATE (1) H ___________________----J ERASE (1) H ------------------~ HAR STB L SET HEAD L UNIT BU S 00 04 05 L ----------------------------, CONTROL L FIRST WRITE (1) H SET RDP L -----------------------~U'-------------------------------------------- ____________________ ~r__rL ________________________________ RDP (1) H WON CNT L u FMT GEN 01 (1) H - - - - - - - - - - - - - - - - - ' I FIRST CLOCK PULSE IN POST SYNC AREA WOE (1) H ---------------------------~ O~ WRT 0 BIT (1) H ___________________..J L.._ _....J L.._ _...J '-----' L.:_ _...J 1.::"----'1.:..1, I,-=~ L:~""" L_ _--' a.::~...... L;_ _ _ __ ______________________________________~r__l~______________ WLB EN H WLB (1) H ________________________________________ ---'r--l~ __________ Figure 5-61 Timing Diagram Number 4 _ ____________________________________________~r__l~_______ WPE (II H INC FMT GEN H CLR SHIFT EN _____________________________________________ ~rl~ _______ --------------------------------------------,Ur ------------- 5-89 The word that has just been written could be the first word in either the VFO Sync Area or VFO Data Sync Area. However, the process is the same for header or data field words. Actually, the format generator is incremented with each WPE (1) H and will soon reach the code for either a Header or Data Field area. At that point, the contents of the BR wi II be transferred to the SR during WLB (1) H. Once the Data Field ha~ been reached, each WLB (1) H increments the SWC to allow only 128 10 36-bit words. There must then be a means of detecting when it is time to write the longitudinal parity word. On the 128th WLB, SWC OVFLO (1) H is generated; in tum, it sets LP WRITE EN. At WLB time of the LP word, a synchronizing flip-flop is set that enables the D-input to LP WRITE. On the next CLOCK H (WPE time of the LP word), LP WRITE (1) L is generated which then fires a PA to produce SECTOR END L (see Figure 5-56). Figure 5-60 also shows two flip-flops called IPLS and INDEX SYNC. The purpose of these flip-flops is to synchronize the Write and Increment Head states during the formatting instruction (WRITE ALL FORMAT). When WRITE ALL FORMAT is executed, CLR + DPCS + FUNC DL Y L clears both flip-flops. The control state will be CLR HEAD until SUSP H sets IPLS which complements (or sets) INDEX SYNC. The leading edge of the next SUSP H will then set Write state (see Figure 5-18). The trailing edge of that same SUSP L will clear IPLS. The control will now remain in the Write state for one complete revolution, at which time the next SUIP H will again set IPLS which will complement INDEX SYNC to a O. The following SUSP will change the control state to Increment Head for one revol uti on. This operation repeats until one entire cylinder of the disk pack is formatted. This operation is described in detail in Paragraph 5. 14. Up to this point in the discussion, the disk has been divided into Sectors, then into Headers or Data Fields, then into words. Now, it must be separated into Clock and Data Bits. Considering the Write state first, shown in Figure 5-62, a four-input OR gate is provided whose output enables the D-input of WRT BIT (Write Bit). Also, a 5-MHz signal, called VFO CLOCK H, strobes the C-input. If at VFO CLOCK H time the D-input is true (High), then WRT BIT will be set for 50 ns and then cleared. The pulse output WRT BIT (1) L is shown on Drawing RP15-0-46 feeding one input of eight M622 drivers. The other input is conditioned by SU XX L (Selected Unit XX) which then directs the bit to be written to the appropriate unit. The first equation that will produce a true signal at the D-input of WRT BIT is: WSBE·WPE (l)·FIRST WRITE (l)·DATA GATE 5-91 +3V WSBE H-.....--...... WPE (1) H DATA GATE H FIRST WRITE (1) H - - ' - - - " FMT GEN 02 (1) H - - - -.... WPE (1) H DATA GATE H PARITY (0) H -.........- " FMT GEN 02 (1) H - - -...... WOE (1) H DATA GATE H END BIT (1) H - - ' - - - - FIRST WRITE DATA H WRITE (1) H RP15-0-06 CLOCK GATE H 15-0492 Figure 5-62 Clock and Data Bit Decoding during Write, Simplified Diagram The first two conditions define the parity bit of the last word in either the VFO Sync Area or VFO Data Sync Area. The last two conditions define a Write operation and Data time. This equation then produces the cue bits in both the VFO Sync Area and VFO Data Sync Area. The second equation is: FMT GEN 02 (l)·WPE (l)·DATA GATE· PARITY (0) The first two conditions of this equation define parity time of either a header or data field word. The third condition produces Data time; the fourth condition provides the value of the bit to be written for odd parity. The parity bit will be described later in this paragraph but note that a 1 is written for parity if the PARITY flip-flop is on a O. The third equation is: FMT GEN 02 (l)·WDE (l).DATA GATE· END BIT (1) This equation is the same as the second except that it now defines the Data bit time [WDE(l)J and writes the contents of END BIT • The last equation is: FIRST WRITE (1)·CLOCK GATE This equation provides for the writing of a 1 for each CLOCK GATE, which produces the basic 2.5-MHz Os rate signal (or Clock Bits) in the double-frequency NRZ writing technique. 5-92 WRITE DATA H is the inverted output of the third equation and is used in generating parity. Considering the Read case shown in Figure 5-63, each READ DATA COAX 00-07 L is ORed to produce READ DATA COAX H. (There can be pulses on only one line at a time.) The leading edge of any pulse on READ DATA COAX H, which occurs during DATA GATE H, will set RD BIT (Read Bit). Once RD BIT is set, it is latched-set with the AND condition of -CLOCK DLYD Hand RD BIT (1) Hand will only be cleared with the next CLOCK DLYD L, regardless of what appears on READ DATA COAX H during -DATA GATE L. RD BIT then separates Data bits from Clock bits on ROC (READ DATA COAX) and stores them unti I the next CLOCK DLYD signal. SET RDP L DATA FIELD H END BIT (1) H FI RST DATA BIT H SHIFT EN (0) H VFO ENABLE H CLR(B)L RD BIT (1) H +3V -CLOCK DLYD H o READ READ READ READ READ READ READ READ DATA DATA DATA DATA DATA DATA DATA DATA COAX 00 L CO AX 01 L COAX 02 L COAX 03 L COAX 04 L COAX 05 L COAX 06 L COAX 07 L _Tw--_ DATA GATE H FIRST DATA BIT L READ DATA COAX H RD BIT (1) H CLOCK DLYD L CLOCK L +3V WRITE DATA H VFO CLOCK H DATA PULSE (0 L SECTOR DL YO L TEST PAR ITY L WOE (1) L RP15-0-05 1S-0493 Figure 5-63 Clock and Data Bit Decoding in Read, Simplified Diagram 5-93 If the HEADER or DATA FIELD latch is set, producing VFO ENABLE H, then each RD BIT (1) H will condition one input of a 3-input OR gate which, in turn, makes the D-input of RDP (Read Data Pulse) true. On the following CLOCK DLYD H, the contents of RD BIT are strobed into RDP. The purpose of RDP is to de-skew RD BIT, which is following the jitter of RDC. Another input to the 3-input OR gate that conditions RDP is DATA FIELD ANDed with END BIT (1) H. When the first word of the Data Field is read, the cue bit is the first bit to reach RDP. From there, it is shifted down the SR unti I it reaches EN D BIT. Since the next bit to be read is not another cue bit, but rather a parity bit, a cue bit must be simulated to keep a known 1 bit circulating in the SR. This input serves that funct i on • DATA PULSE is simi lar to RDP in that it contains the contents of all RD BIT 1s except the cue bit read in prior to the first word. It must be remembered, that FIRST DATA BIT L is a result of the first RD BIT which is the cue bit. Therefore, FIRST DATA BIT L cannot condition the D-input to DATA PULSE soon enough to catch the first RD BIT (1) H. However, all following RD BIT (1) H 1s are stored in DATA PULSE until cleared by CLOCK l. Now, since DATA PULSE is only data bits, it can be used as one of the OR conditions that complement PARITY to calculate the parity of the word being read. Parity for Read is generated by first clearing PARITY with SECTOR DL YD L or TEST PARITY L (which occurs at the end of each word). Then, each bit read (DATA PULSE (1) L) complements PARITY. At the end of each word, TEST PARITY L strobes FEE and WEE (Format Error Enable and Word Error Enable) to see if PARITY is on a 1, which it should be. If PARITY is not on a 1, the FEE or WEE flip-flop is set indicating an error condition. This operation is described in more detail in Paragraph 5.23. Parity sensing timing for Read is shown in Figure 5-58. Parity for Write operations is generated by first clearing PARITY with WDE (1) l. Then, each WRITE DATA HANDed with VFO CLOCK H will produce the complementing pulse for PARITY. After the 36 bits of data have been strobed into WRT BIT, the complement of PARITY is written. This was described in the discussion concerning Figure 5-62. 5.21 WORD COUNT AND CURRENT ADDRESS CONTROL The RP15 Word Count (WC) and Current Address (CA) Control is shown in Figure 5-64 and on Drawing RP15-0-17. This control operates, with the Current Address Register (CA), to sequence the memory (see Paragraph 5.9), and with the Word Count Register (WC) to regulate the length of each transfer. 5-94 WC OVFLO EN L +3V ·· WC 00 (1) H _ WC 17 (1) H _ r _ _ -...... ADDR ACC H --L..._'" WC OVFLO (0) H INC CA H MAINT INC CA L CLR+DPCS+FUNC DLY L DP WC L CLR WC L DP CA L CLR CA L +3V CLR L WC OVFLO (1) L MAINT INC WC L -ADDR ACC L C A 12 (1) H CA 13 (1) H CA 14 (1) H C A 15 (1) H +3V ---r---.... >-----.- INC CA CRY A H --.J---'" CA 16 (1) H CA 17 (1) H +3V--~~----------~ INC CA CRY A L +3V --1.._ _CA CA CA CA CA CA INC WC H INC CA CRY A L INC CA CRY B L INC CA H INC CA H ..... 06 (1) H 07 (1) H 08 (1) H - -......- 09 (1) H 10 (1) H 11 (1) H INC CA CRY B L CLR CAL---~~---------~ RP15-0-17 1!I-0494 Figure 5-64 WC and CA Control, Simpl ified Diagram Since the CA is a ripple counter and since ripple counters can take considerable time in incrementing, provisions are made to speed up this process. As described in Paragraph 5.9, the register is broken into 6-bit sections, with the second two sections decoded before the first. This scheme eliminates the wait for the delay out of each. For example, bits 12-17 of the CA are always incremented; but bits 6-11 are incremented only if bits 12-17 are already on a 1 prior to INC CA H; bits 0-5 are incremented only if bits 6-17 are already on a 1 prior to INC CA H. This is done by creating two separate increments for CA bits 0-5 and 6-11 called CRY A (1) H and CRY B (1) H. The D-type fl ip-flops are used so that IN C CA H can be sampled at its leading edge. In this way, incrementing does not wait for 5-95 ripple delay, but rather utilizes an AND conditioning to achieve the same result; the worst-case delay is reduced to one-third of what it would be normally. In a sense, the need for incrementing is predicted in this design rather than waited for. INC CA H is generated from the following equation: MAINT INC CA + (ADDR ACC·WC OVFLO (0)) Note that in normal operation the CA can be incremented only if the WC is not yet complete. WC OVFLO flip-flop is set when WC bits 00-17 are all set prior to INC WC H, at which time WCOO-17 are all incremented to O. INC WC H is generated from the OR of MAl NT INC WC Land ADDR ACC. WC OVFLO (1) L also produces INC WC, so that once WC OVFLO is set, it remains set because there can be no more positive transitions on INC WC H unti I WC OVFLO is cleared by external means. Two AND/OR gate combinations decode DPWC L (Disk Pack Word Count) and DPCA L (Disk Pack Current Address). These signals are then ORed with CLR L to produce clearing signals for the Word Count Register (CLR WC L) and Current Address Register (CLR CA L). Note that these clear signals are about 50-ns wide. This is important because if a DPWC is issued (which is l-~s wide) the first 50 ns are spent clearing all WC bits. The remaining 950 ns are used to strobe the preset sides of those WC bits that correspond to existing lOB bits (see Drawing RP15-0-31). This is also true of the CA. If both CLR WC Land DPWC H were the same width, the WC register would be confused. CLR WC Land CLR CA L are also produced by CLR L. 5.22 WRITE PROTECTION FOR THE DRIVE The RP15 is equipped with two types of Write protection: both types inhibit the Write operation from occurring and raise the interrupt Write Protect Error via the enabling level WPEE. The logic for this capability is shown in Figure 5-65, Drawings RP15-0-09 and -10. 5.22. 1 Entire Unit Protection Each RP02 contains a Write Protection switch labelled READ WRITE;'READ ONLY (see Figure 2-1). As explained in Table 3-1, when this switch is placed in READ WRITE position, information may be both read or written on the disk; but when the switch is in READ ONLY position, information can be read from the disk, but cannot be written on it. When a unit which is set to this condition is selected for a Write operation, the appropriate interrupts are raised and the request is inhibited. 5-96 SULO L SULO H WPEE L SUWP H WPEE H SURO L CAR 05 (1) H LOA 00 (0) H CAR 05 (0) H LOAOO(I)H CAR 06 (1) H LOA 01 (0) H CAR 07 (0) H LOA 02 (1) H CAR 06 (0) H LOA 01 (1) H CAR 07 (1) H LOA 02 (0) H CAR 06 (0) H LOA 01 (1) H CAR 07 (0) H LOA 02 (1) H CAR 05 (0) H LOA 00 (1) H -----------------------T-----I LO 00 (0) H UR 00 (1) H RP15-0-10 I LO 00 (1) H UR 00 (0) H I LO 01 (0) H UR01(1)H I I LO 01 (1) H UR 01 (0) H I I LO 02 (0) H UR 02 (1) H I I LO 02 (1) H UR 02 (0) H RP15- 0-09 I I Figure 5-65 1~-049~ Write Protection, Simplified Diagram The logic for this is shown in Figure 5-65, in which the signal Selected Unit Read Only (SURO L) from the Write Protected unit results in Selected Unit Write Protect (SUWP H). This is ANDed with FR01 (1) Hand FR02 (O) H to raise WPEE H/L which, in turn, feeds Status Register A bit 14 and enables the interrupt. The Function Register Code used here ties the operation down to any Write operation except Write Check (not really a Write function). Note that when a unit is Write Protected it does not inhibit Write operations on other units in the string, but it does inhibit writing on all cylinders of the Disk Pack installed on that drive. 5.2.2 Partial Unit Protection Mounted on the lower right-hand corner of the RP15 logic panel, is a group of switches labelled as shown in Figure 2-1. To the right of the switch labelled LOCKOUT is a red indicator that lights when 5-97 the LOCKOUT switch is in that position. When this indi cator is off, if all Write Enable conditions are met, the selected unit is enabled for both Read and Write operations. When this indicator is on (LOCKOUT switch in LOCKOUT position), only the unit designated by the LO toggle switches is protected. On that unit, the number of cylinders which are Write Protected are cylinders zero through the cylinder described by the octal contents of the switch register labelled LOAOO-02. This feature is used to protect only cyl inders 0-7 within a single unit. Any unit can be so protected, but only 8 one unit at anyone time. Should a unit which has been Selected Unit Lockout designated be selected, and a Write function requested in those cylinders which are protected, the appropriate interrupts would be raised and the Write request would be inhibited. The logic for LOCKOUT operation is shown in Figure 5-65. Selected Unit Lockout (SULO L), which ORs with SURO L to produce SUWP H, is the AND function of CAROO-04 (0) H, LOCKOUT H, UR EQ LO H, and a composite comparison of CAR05-07 with the Lockout Address switches (LOAOO-02) • Since the RP15 can lockout only cylinders 0-7 , CAROO-04 must all be on a 0 for a WPEE to be raised. 8 Also, the LOCKOUT switch, shown on Drawing RP15-0-55, must be in LOCKOUT position (SSLO L) to set the M203 filter flip-flop and yield LOCKOUT H. This flip-flop serves to convert switch operation to logic levels. The level UR EQ LO H (Unit Register Equals Lockout' switches) is the result of comparing the contents of the Unit Register (the unit addressed) UROO-02 with the settings of the LO switches on Drawing RP15-0-55, as seen at the output of their respective EQUIVALENT M 121 ~L o. fl i p-fl ops. Referring to Figure 5-65, three sets of AND gates compare the High states of LOOO-02 (0/1) with the ~L = b. High states of UROO-02 (1/0), respectively, through three associated ORs. The M 121 AND/NOR gates, used in this application, comprise pairs of noninverting ANDs feeding single inverting ORs. Figure 5-66 shows the various level distributions for this type gate together with its equivalents. It can :t>L H :t>-" c. ~" L ./ L be seen that whenever the Lockout Register does ~ ~H ./ ~" L ~ d. not equal the Unit Register, the level distributions will be as shown in a or b of Figure 5-66; when they are equal, the levels wi II be as shown in c and d of 5-98 15-0496 Figure 5-66 Logic Operation of M121 Module Figure S-66. Note, then, that if LOOO differs from UROO, the output of its associated OR gate wi II be low, thereby inhibiting the AN D gate and preventing WPEE from being generated. The same is true for the other two Unit Register and Lockout switch digits. If all three digits are alike, all three OR gate outputs will be high and another condition will be met for the Write Protect Error Enable. The final condition required for the generation of SULO L is the comparison of the Cylinder Address Register (CAROS-07) with the settings of the Lockout Address switches (LOAOO-02) to determine if the cylinder address requested has been locked out for Write operations. The logic to determine this develops the following equation: CAROS-07 <LOAOO-02 This equation states: "See if the number in CAROS-07 is equal to or less than the number set in LOAOO-02. If so, raise SULO L. II This circuit is required to produce an output only if the CAR is equal to or less than the LOA. As configured, the circuit consists of an OR gate, fed by four AND gates. The four ANDs are fed by an arrangement of signals which checks for equality between all three sets of comparative bits, then checks each CAR bit against its comparable LOA bit to determine which is larger. Equality is checked by the three AND/NOR gate combinations that check CAROS-07 against LOAOO-02 in the same manner that LOOO-02 was checked against UROO-02. As shown in Figure S-6S, the four ANDs are fed in such a manner as to check for equality in all three digits through to a difference in the least significant digit. Since the outputs of the ANDs are ORed, any condition can enable SULO L, and, provided the Function Register bits are as indicated, Write Protect Error wi II be enabled. S.23 STATUS CONTROL The RP1S Status Control is shown on Drawings RP1S-0-09, -10, and -11. This control serves a status reporting function and controls the termination of an operation either immediately upon sensing an error or at the end of that sector through the control flip-flop JB DN. It also contains the logic for establishing the BUSY status. Referring to Figure S-67, the Header Not Found Error (HNF ERROR H) occurs when three consecutive index pulses (SUIP H) are received while looking for a header that has not been found. The expression that enables the counting of the two HNF flip-flops (HNF A and HNF B) is: (READ + WRITE)·HNF B (0)· NORMAL S-99 READ (1) L WRITE (1) L NORMAL H HNFB (0) H SUIP H CLR HNF L HNFA (1) L HNFB (0) L HNF ERROR L HNF ERROR H CMPR (1) H RP15-0-11 CLR+DPCS+FUNC DLY H 15-0497 Figure 5-67 HNF Status Control, Simplified Diagram Note that if CMPR is set, or if the operation is a format instruction (not Normal), then HNF A and HNF B cannot be counted. HNF A and HNF B are cleared by CMPR (1) or CLR + DPCS + FUNC DLY L. FUNC DLY occurs at the beginning of each function such as Read or Write. CMPR is set when the desired header is found" Therefore, HNF A and HNF B begin in the 0 state during a Read or a Write and increment in the following manner with each index pulse (SUIP H): HNFA HNFB o o o 1 1 1 o 1 o o (error condition) The error state is expressed as: HNF A (O)"HNF B (l)·CLR + DPCS + FUNC DLY + CMPR (1) If the error condition state is reached before CMPR is set, HNF ERROR L is raised and remains latched until the next CLR + DPCS + FUNC DLY L. The logic for BUSY is shown in Figure 5-68 as two sets of cross-latching OR gates. BUSY indicates that the control is actively performing a function and should not be interrupted. BUSY is set by either EXECUTE L or INITIATE L. One of these signals occurs at the beginning of each function. If it is an initiate-type function, BUSY is cleared a standard 4-1-15 later by TAG REST ART L. If it is an executetype function, BUSY is cleared with JOB DONE L at the completion of the function. BUSY is also cleared by the OR of CLR Hand MAINT (1) H. 5-100 EXCUTE L JOB DONE L BUSY L CLR H MAINT (1) H RP15-0-11 15-0498 Figure 5-68 Busy Status Control, Simplified Diagram The Programming Error Enable {PEE} flip-flop, shown in Figure 5-69, sets at lOP 4 {B} time on those instructions which are illegal during BUSY. They are: DPLZ DPWC DPLO DPLA DPCN {or any instruction which simulates continue} DPCA DPLF DPCS NOTE See Paragraph 3.13 for definitions. +3V SEL YY H SUB DEV 00 H WC OVFLO (0) H BUSY H DISK SEL H END OF PACK L C 0 CLR+DPCS+FUNC DLY L RP15-0-11 10-0499 Figure 5-69 PEE and EOPE Status Control, Simplified Diagram 5-101 The equation that enables the set of PEE is as follows: DISK SEL· BUSY· [SEL YY + SUB DEV 00] PEE and EOPE flip-flops are reset with CLR + DPCS + FUNC DLY L. The End of Pack Error flip-flop (EOPE), shown in Figure 5-69, wi" set on WC OVFLO (0) H if END OF PACK L is present, indicating the end of pack has been reached without WC overflow. END OF PACK L means an overflow occurred from the CAR in the middle of a record transfer. It occurs on the following count: CAR HAR SAR 3128 23 8 118 This wi" happen on an INC SAR and if WC has not as yet set. The Longitudinal Error Enable flip-flop (LEE), shown in Figure 5-70, is strobed by LP TEST (1) H which is set at the end of each sector during the word parity bit of the longitudinal parity word. During the reading of a sector, each 36-bit word is XORed into the LPR, including the longitudinal parity word. The result should be a" 1s in the LPR. The test for this condition is a 36-bit AND gate shown on Drawing RP15-0-26. If any bit is a 0 at this time, either -LPR A EQ ONES L or -LPR B EQ ONES L wi" be true. This condition enables setting of LEE flip-flop that wi" set on LP TEST (1) H, thereby enabling the set of the LE flip-flop at the end of that sector (SECTOR END H). Both LE and LEE are cleared by CLR + DPCS + FUNC DLY L. +3V - LPR A EQ ONES L LEE (1) H +3V >--_-I D -LPR B EQ ONES L LEE LP TEST (1) H C SECTOR END H 0 CLR+DPCS+FUNC DLY L I CLR+DPCS+FUNC DLY L RP15-0-11 RP15-0-10 15-0500 Figure 5-70 Longitudinal Error Status Logic, Simplified Diagram 5-102 As shown in Figure 5-71, the signal Selected Unit Seek Underway (SUSU L) is the result of the ANDing of Selected Unit On Line (SUOL H) with Selected Unit Not Ready (-SU RDY H) and Selected Unit Seek Not Incomplete (-SUSI H). This means that if the disk is on line, as long as it is not ready, and if a Seek Incomplete has not been raised, an SUSU will be indicated. The moment a disk is ready or an In- SUOL H - SU ROY H - SUS I H SUSU H complete Seek is detected, this indication will be term i nated . SUSU L RP15-0-09 The Status Control flag logi c is shown in Figure 15-0501 5-72. DISK FLAG H, which is sent to the inter- Figure 5-71 SUSU Status Control Logic rupt system to indicate termination of operation, is the OR of ERROR FLAG L, ATT FLAG L, or JOB DONE L. JOB DONE L is generated at the end of a sector and after the ERASE GATE flip-flop has cleared. ATT FLAG L is raised on an attention signa I from any drive. ERR FLAG L is raised when any of the error conditions shown as OR gate inputs on Figure 5-72 occur. FEE (1) L - - - - . TE (1) L WE (1) L LE (1) L ~IL--_ PEE (1) L NESA L NEHA L NECA L or WPE E L ---I"r--_ _ .".... HNF ERROR L EOPE (1) L ...... ",. WCE (1) L ---c..;L...-_ SUSI L SUFU L ATT 00 L -r._ ATT Ot L ATT 02 L ATT 03 L -----.L_ ATT 04 L ATT O~ L ATT 06 L ATT 07 L DISK FLAG H _. ~ RPlO-0-09 JB ON (1) H JOB DONE H ERASE GATE (0) H RP10-0-10 15-0502 Figure 5-72 Status Control Flag Logic, Simplified Diagram 5-103 As can be seen from Figure 5-73, JB ON flip-flop will set under two conditions: either immediately upon certain conditions (SET JOB DONE L) or at the end of a sector under other conditions (SECTOR END H). The flip-flop is reset by CLR + DPCS + FUNC DLY L. EOPE (1) L ~or--_ HNF ERROR L FEE (1) L MAINT SET JB ON L ~CJI--- ~---t~ SET JOB DONE L RP15-0-11 FEE (1) WEE (1) LEE (1) TE (1) L ~Cr-_ L L L WCEE (1) L WC OVFLO (1) L SECTOR END H +3V-.__a ) O - - - - - - - - - - - - - . . - C L R + O P C S + F U N C OLY l FUNC OlY H RP15-0-10 OPC F l ----(l!--_ _ 110 PWR ClR B l ClRtOPCS l ClR+OPCS H RP15-0-09 15-0503 Figure 5-73 JB ON Status Control, Simplified Diagram Those conditions that preset JB ON are: EOPE(1) + HNF ERROR + FEE(l) + MAINT SET JB ON Those conditions that merely enable it to set at the end of the present sector are: FEE(l) + WEE(1) + LEE(l) + TE(1) + WCEE(1) + WC OVFLO(l) The Format Error Enable flip-flop (FEE) (Figure 5-74) will be set-enabled when HEADER Hand PARITY (0) H are both present, indicating a parity error in a header word. The flip-flop is strobed with TEST PARITY H. FEE(1) L latches the FEE set until cleared by CLR + DPC + FUNC DLY L. If no format error exists, FEE(O) H will AND with LPR B EQ ZEROS H to set CMPR on the transition of HDR END to (0) L. CMPR will latch up upon setting and cannot be cleared unti I SET IDLE L. The Word Error Enable flip-flop (WEE), shown in Figure 5-75, sets on -HEADER H and PARITY (0) H when strobed with TEST PARITY H, which occurs at the end of each word read. When WEE sets, it indicates a parity error in a data word, it latches up until cleared by CLR + ope + FUNC DLY L, and it enables the setting of WE flip-flop, which then sets at the end of that sector. 5-104 +3V HEADE R H PARITY (0) H +3V FEE (I) L TEST PARITY L CLR +OPCS+FUNC LPR B EQ ZEROS H HDR END (0) L CMPR (I) L SET IDLE L RP15 -0-10 Figure 5-74 Format Error/CMPR Status Logic, SimplHied Diagram +3V WEE (1) H +3V - HEADER H PARITY (0) H SECTOR END H WEE (1) L TEST PARITY L CLR+OPCS+FUNC OLY L RP15-0-10 15-0505 Figure 5-75 Word Error Status Logic, Simplified Diagram As shown in Figure 5-76, the Write Check Error Enable flip-flop (WCEE) is set during a Write Check function (Function 7) if a corresponding 36-bit word read from the disk differs from the 36-bit word assembled in the Buffer Register. Comparison of the Buffer Register and the Shift Register is accomplished by a 36-bit wide XOR gate shown on Drawing RP15-0-24, -25, and -26. If the two registers differ, the signal -WCC H is generated (not Write Check Compare). WCEE flip-flop is strobed at the end of each 36-bit word read from the disk by LPR STB L, thereby setting WCEE if the function is a Write Check (FROO,Ol,02 (1) H) with CMPR set, and if the word read is other than a longitudinal parity word (SWC OVFLO (0) H). WCEE is latched when set and can only be cleared by CLR + DPCS + FUNC DLY L. When it sets, WCEE enables WCE flip-flop, which sets at sector end and enables JB DN to set at the same time. 5-105 +3V CMPR (I) H ---'------... SWC OVFLO (0) H -WCC H FROO (I) H - - - " 1_ _ WCEE(1l H FROI (1l H FR02 (I) H +3V WCEE (1) L LPR STB L CLR+DPCS+ FUNC DLY L ~~-----~'--~ SECTOR END H RP15-0-10 15-0506 Figure 5-76 5.24 Write Check Error Status Logic, Simplified Diagram INTERRUPT CONTROL (API) The RP15 Interrupt Control is shown in Figures 5-77 and 5-78, and in Drawing RP15-0-12. The API Control shown in the drawing consists of a standard M 104 Module. This module performs the necessary operations to synchronize a priority interrupt in the PDP-15 on receipt of DISK API RQ H from the status control logic shown in Figure 5-77. DISK API RQ H ERR FLAG H DED (0) H JOB DONE Ed=Y ATTFLAG • L~ ~ ~ . ~ RQ(1)H~PIRQL lAPI H---L..~ ATD (0) L RP15-0-09 15-0507 Figure 5-77 Priority Interrupt Status Logi c, Simpl ified Diagram The conditions for DISK API RQ H can be expressed as follows: DED(O)·(ERR FLAG + JOB DONE) + (ATT FLAG·ATD(O)) This expression states that a Disk API Request will be raised on either an Error Flag (ERR FLAG) or a Job Done (JOB DONE) flag, provided the Done and Error Flag Disable (DED (0)) has not been set, or, on an Attention Flag (ATT FLAG), if the Attention Flag Disable (ATD (0)) has not been set. DISK API RQ H then enables the API REQ flip-flop within the M104 (Figure 5-78) which, on receipt of I/O SYNC (B) H, is set to produce API RQ (1) H. This signal is then ANDed with DISK API RQ H in Figure 5-77 to yield PI RQ L. PI RQ L results in a PROG INT RQ to the PDP-15. 5-106 API REO (1) H API GR (8) H -------------~---_.__f D 1 DISK API RO H - - . - - - - - - - - - - - 1 API REO I/O SYNC (8) H - t - - - - - - - - -.........- - + - - - f - - - - - - - - - - - - -.........--+---f---J CLR H -+------....-----4 API ENA (1) L ' - - - - - - 1 - - - - - - - - - - - - - API REO (1) L +5V API REO (0) H >---- API 1 EN OUT H API 1 EN IN H ' - - 4 1 - - - - - - - - 1 +5V RPI5-0-12 15-0508 Figure 5-78 5.25 M 104 Block Diagram for API MAINTENANCE CONTROL The RP15 Maintenance Control circuit is shown in Drawings RP15-0-03 and -04. The Maintenance Control replaces the Disk Pack Drive for maintenance purposes by providing the looping logi c and storage facilities necessary to operate the RP15 without the disk as a load. The purpose of the 6-bit Maintenance Register MROO-05 is to look like a disk to the controller (see Figure 5-79). In Write mode, information from memory enters the Buffer Register in two 18-bit words; it is then transferred to the Shift Register and shifted out, one bit at a time. Normally, each bit would be placed on the disk; in Maintenance mode, it enters the Maintenance Register instead, entering at MR05 (MAINT DATA H) and shifting left (MR SHIFT EN H) as each additional bit is shifted in. The programmer has control of these shift pulses and can issue them one-at-a-time, at will, with the Maintenance Instruction. He must, however, keep track of the number of shifts so that after each six shifts he can pause and examine the contents of the MR for successful transfer. This register is a standard shifting register and operates in the same manner as the SR described in Paragraph 5. 13. The signal lOB TO MR EN H, applied to each lOB input AND gate, is the inversion of -MR SHIFT EN L which, in turn, is the result of the following (see Figure 5-80): SEL YY . lOB 09 . SUB DEV 00 5-107 lOB 12 H - - - - - - - - - - - - - + - - - - - f . . - ' \ t lOB TO MR EN H - - - -.. I I CLR L CLR H MR STB H I THRU I I I • • • • • • •• MR 01 (1) MR SHIFT EN H - - - - . MR 04 (1) • lOB 17 H-----------+---~--~~ 0 MR05 WR STB H C 0 MAINT DATA H - - - - - - - L - . / RP1!S-O-03 15 - 0509 Figure 5-79 END BIT (1) H WOE (1) H - - - - - ' , Maintenance Register, Simplified Diagram WRITE (1) L-....rYMROO (1) L,-__~~I Ir-.-MAINT DATA L PARITY (0) H----...' WPE (1) H - - - - CLOCKL=DMR STB H LOAD MAINT L RP15-0-03 READ DATA COAX 00 L RP15-0-04 SEL YY H lOB 09 H SOB DEV 00 H RP15-0-03 15-0510 Figure 5-80 Register Control Logic, Simplified Diagram 5-108 The register is cleared by MAINT CLR L, the inversion of CLR H, and is strobed by MR STB H, the OR of CLOCK L + LOAD MAINT L. The logic for MAINT DATA H is the result of the following equation (see Figure 5-80): READ(1)· MROO(l)+WRITE(l) [END BIT(l) ·WDE(l)+PARITY(O)· WPE(1)J This equation states that if the controller is doing a Read (READ (1) L) then MAINT DATA H looks at the state of MROO flip-flop; if the controller is performing a Write (WRITE (1) L), then MAINT DATA H is the result of either END BIT (1) H together with Write Data Enable (WDE (1) H) or PARITY (0) H ANDed with Write Parity Enable (WPE (1) H). MR STB H is the result of CLOCK L from the Data Separator Control (Drawing RP15-0-08) and LOAD MAINT L, which results from lOB 09 H (AC bit 09 (1)) and decoding of the instruction DPEM L from the lOT Selection circuit described in Paragraph 5.3. As shown in Figure 5-81, the Maintenance Instruction (DPEM - 706401) can perform various operations determined by AC bits 09 through 17 (lOB 9-17 H). The operations performed by these bits are described in Table 3-2. The programmer must set up these AC bits when the instruction is issued. For example, if the programmer issues DPEM, with AC bit 09 on a 1 (lOB 09 H), these conditions will yield LOAD MAINT L. This signal will raise MR STB H, permitting MROO-05 to be loaded with whatever is in bits 12-17 of that same word. NOTE lOB 10 and 11 are ineffective in this case, which means that MAINT flip-flop cannot be set and MAINT (B) L cannot enable the buffer gates shown on Drawing RP15-0-04. When the DPEM instruction is issued with AC bit 09 on a 0 (-lOB 09 H), AC bits 10-17 are then interpreted as maintenance signals to be described. When this condition exists it will AND with AC bit 10 on a 0 (-lOB 10 H) to clear the MAINT flip-flop, thereby disabling the AND gates that simulate the signals normally received from the drive. When AC bit 10 is set (lOB 10 H), the opposite is true; the MAl NT flip-flop is set and the gates are enabled. When bit 11 is set, the Selected Unit Index Pulse (MAl NT SUIP L) is simulated. Bit 12 simulates a Sector Pulse in the same manner. If bit 13 is set, the Maintenance Control wi II set JO B DON E. Setting bit 14 increments the Current Address Register; whi Ie bit 15, when set, increments the Word Count Register. If bit 16 is set, the Sector Address Register is incremented. Successive setting of this bit wi II cumulatively increment the HAR and CAR. 5-109 lOB 09 H OPEM L -lOB 10 H - - - - - - - 1 1 - - 1 CLR MAINT L lOB 10 H SET MAINT L lOB 11 H lOB 12 H lOB 13 H lOB 14 H lOB 15 H lOB 16 H ... It It ... "... • • • • • - - - _ _ MAINT SUIP L - - - - I t MAINT SUSP L - - - - " MAINT SET JB ON L - - - - - MAINT INC CA L - - - - " MAINT INC WC L - - - - " MAINT INC SAR L • lOB 17 H MAINT CLK L RP15-0-03 15 -0511 Figure 5-81 DPEM Decoding, Simplified Diagram When set, bit 17 results in lOB 17 H; this signal yields MAINT ClK l, which is the signal that shifts a single bit. As such, it is similar to a data cell. When this pulse is issued, the control will shift one single bit either from the MR into the SR, or from the SR into the MR, thereby simulating a Read or a Write operation, respectively. During Read, the bits in the MR can be made to cycle around on themselves, eliminating the need for continuous reloading. If the programmer loads a pattern such as 25 , the se8 quence circulates and simulates a disk pattern condition. The Maintenance Control Buffers are shown on Drawing RP15-0-04. In this logic, the various control signals, that are normally generated and sent to the disk, are ANDed with MAINT (B) l and then doubled back into the controller as the proper response usually received from the disk as a result of the signal generated. MAINT (B) l, shown on Figure 5-80, is the buffered version of MAl NT (1) l (same as MAINT (0) H). It is ANDed with MAINT DATA l to yield READ DATA COAX 00 L. Referring to Drawing RP15-0-04, the loads on the output of each driver terminate the cables to prevent ringing, and, during operation, provide the correct collector loads for the cable drivers. Note that READ DATA COAX 00 l is created from MAINT DATA l, which is shorted back to simulate information that would normally come from the disk. 5-110 S.26 INTERFACING THE DRIVE The RP1S interface to and from the RP02 Disk Pack Drive is shown on the right-hand side of Figure S-l and in Drawings RP1S-0-46, -47, and -48. The drivers used for this purpose are all type M622; receivers are all type MS10. Drawing RP1S-o-S3 is the cable diagram. S.27 INTERFAGING THE I/O The interfacing circuits between the RP1S and the PDP-1S I/O are shown on. the left-hand side of Figure S-l and in Drawings RP1S-0-49, -SO, and -Sl. The driver modules are all type M622; receivers are type MS10. Drawings RP1S-0-S2 is the cable diagram. S-lll CHAPTER 6 MAINTENANCE 6.1 INTRODUCTION RP15 maintenance philosophy conforms to that of other DEC equipment; i.e., an optimum amount of preventive procedures performed on a routine schedule eliminates many costly equipment breakdowns, and forecasts impending failures long before they occur. When a specific item does fail, the design of the equipment is such that quick replacement of modular elements restores the equipment to service in minimum time. In this chapter, procedures are divided into preventive and corrective categories. 6.2 PREVENTIVE MAINTENANCE Preventive maintenance consists of tasks performed at periodic intervals to ensure proper equipment operation and minimum unscheduled down time. These tasks include visual inspection, operational checks, cleaning, adjustment, and replacement of borderline, or partially defective, parts. Preventive maintenance scheduling is determined by the existing environmental and work-load conditions at the installation site. Under normal conditions, a schedule of preventive maintenance, consisting of inspection and cleaning every 600 hours of operation, or every four (4) months, whichever occurs first, is recommended. Relatively extreme conditions of temperature, humidity, or dust and/or abnormally heavy work loads demand more frequent maintenance. Preventive maintenance procedures for the RP02 Disk Pack Drive are not included in this manual. For those procedures, refer to the Memorex Maintenance Manual supplied with each RP02. 6.2. 1 Test Equipment Required Maintenance activities for the RP15 require the standard test equipment and special materials listed in Table 6-1, plus standard hand tools, cleaners, test cables, and probes. 6-1 Table 6-1 Test Equipment Required Manufacturer Designatton Multimeter Triplett or Simpson Model 630-NA or 260 Oscilloscope Tektronix Type 547 or 454 Plug-In-Unit Tektronix Type lA 1 Xl0 Probe Tektronix Xl Probe Tektronix Hand Unwrapping Tool Gardner-Denver H812A505 244-475 Hand-Operated Wire-Wrap Tool with 504221 bit for 30 AWG Wire and 500350 Sleeve Gardner-Denver 14H1C Modu Ie Extender DEC Type W982 Diagnosti c Self-Test Routines DEC MAINDEC-15-D5HA-D MAINDEC-15-D5DA-D MAINDEC-15-D5EA-D MAINDEC-15-D5FA-D Equipment 6.2.2 Mechanical Checks Inspect the RP15 Controller periodically as follows: Procedure Step Inspect the controller for completeness and general condition. 2 Clean the interior and exterior of the cabinet using a vacuum cleaner or clean cloth moistened in nonflammable solvent. 3 Inspect all wiring and cables for cuts, breaks, fraying, wear, deterioration, kinks, strain, and mechanical security. Tape, solder, or replace any defective wiring or cable covering. 6.2.3 Electrical Checks (Timing Adjustments) Each month proceed as follows: Procedure Step Power down system. Remove all cables in slots H19-H24 and in slots J19-J24. Cables should be marked with appropriate locations. 2 Remove M622 Modules located in H14, H15, and H16. Place them in slots H17, J23, and J24. (Continued on page 6-3) 6-2 Step Procedure 3 Power up system. Set accumulator switches to 760032. Load RP15 Instruction Test. After tape is loaded and the Teletype® bell rings, lower AC switch 00. 4 Set up oscilloscope for internal sync on probe no. 1. Place probe no. 1 on C24F2. Adjust top potenti ometer in slot C24 unti I trace on oscilloscope is a 1.5-l-'s high level. 5 Place probe no. 1 on C24T2. Adjust lower potenti ometer in slot C24 until trace on osci Iloscope is a 350-1-'5 high level. 6 Place probe no. 1 on C25F2. Adjust top potenti ometer in C25 until trace on osci Iloscope is a 50-l-'s high level. 7 Set accumulator switches to 760130. After bell rings, lower AC switch 00. 8 Place probe no. 1 on C07T2. Adjust lower potenti ometer in C07 until trace on oscilloscope is a 20-l-'s high level. 9 Place probe no. 1 on A05P2. Adjust potentiometer in C06 until trace on oscilloscope is a 4-1-'5 high level. 10 Power down system. Remove M622 Modules located in slots H17, J23, and J24. Replace them in locations H14, H15, and H16. 11 Replace all cables removed in Step 1. 12 Power up system. RP02 disk drive must be on line and ready. 13 Press I/O RESET. Place probe no. 1 on CLOCK H, 0 17L2. Place probe no. 2 on CLOCK GATE H, D17Pl. Adjust potentiometer in slot C 15 unti I leading edge of pulse on probe no. 1 falls exactly in the middle of the high level on probe no. 2. 14 Load the following program from the accumulator switches. Disk pack must be formatted correctly before this step. 100/ 0/ 703302 CAF 200000 LAC 0 706344 DPCA 777400 LAW-400 706364 DPWC 200001 LAC 1 706464 DPLF 706341 DPSJ 600107 JMP .-1 600100 JMP 100 010000 CA = 10000 011000 FUNCTION = READ & GO ®Teletype is a registered trademark of Teletype Corporatioh. 6-3 (Continued on page 6-4) Step Procedure 15 Start program at location 100. Place probe no. 1 on E14B1. Place probe no. 2 on FllE2. Measure the delay between the leading edges of probe no. 1 and probe no. 2. (Measure at the 50 percent points of the first pulses in trace only.) Record the delay on paper (R1 20 ns). 16 Place probe no. 1 on D17L2. Place probe no. 2 on F11H2. Adjust potentiometer in location E12 until the delay between probe no. 1 and probe no. 2 is equal to recorded delay from Step 15. 6.2.4 Margins Since the RP 15 contains integrated circuits, the standard margining techniques are not required. However, margining of other elements of the PDP-15 are required as called for in individual maintenance manuals. 6.3 CORRECTIVE MAINTENANCE Standard troubleshooting techniques should be adequate to isolate trouble quickly in the RP15. When an inoperative module is located, replace it with one from spares and return the defective module to DEC for repair or replacement. DEC offers an optional spare modules kit containing one spare for each module. Recommended Module Spares are given in Table 6-2. Table 6-2 RP 15 Recommended Spares Module Spares Module Spares Module Spares M002 1 M149 1 M312 1 Ml04 1 M160 1 M401 1 Mll1 1 M161 1 M405 1 M1l2 1 M203 1 M420 1 M113 1 M204 1 M510 1 M1l5 1 M207 1 M602 1 M117 1 M212 1 M606 1 M119 1 M216 1 M611 1 M121 1 M302 1 M622 1 M133 1 M311 1 M627 1 M135 1 M911 1 6-4 6.3.1 General Corrective Procedures Before beginning troubleshooting procedures, ensure that the PDP-15 processor is operating properly. Refer to the specific maintenance manual to determine status. Also examine the maintenance log to determine if the fault occurred before and note what steps were taken to correct the condition. Visually inspect the physical and electrical security of all cables, connectors, modules, and wiring. Particularly check the security of ground connections between the controller and the system. Defective grounds can produce a variety of faul ts. 6.3.2 Diagnostic Testing DEC provides special diagnostic programs (MAINDEC) to assist in local izing faults within the equipment. Functionally, the programs fall into two categories: diagnostic and reI iability. Diagnostic programs isolate genuine go/no-go type hardware fail ures that are easily recognizable; reI iability programs isolate failures that are more difficult to detect because they are marginal in nature and/or occur infrequently or sporadically. The family of test programs are written so that, when run successively, they test the equipment beginning with small portions of the hardware and gradually expanding until they involve the entire machine. To accomplish this, the test programs are built around instructions and portions of instructions whose demands upon equipment capabilities progress from simple transfers and skips to the most involved data manipulations and computations. As portions of the system are proven operable, they become available to succeeding tests for use in checking out unproven portions of the machine. 6.3.2.1 RP15 Instruction Test - This test utilizes the self-contained maintenance hardware that the RP15 Controller provides. It conducts an off-I ine test of data transfer paths as well as basic circuitry. In this paragraph, a brief summary of this test is given. For complete details refer to MAINDEC-15D5HB-D. To load the test: Step Proced ure Load tape into reader. 2 Place BANK MODE switch to BANK MODE. 3 Set address switches to 17700. 4 Press I/O RESET and then READ IN. 6-5 To start the test: Step Procedure Power down. 2 Remove all cables from slots H19-H24 and J19-J24 (all cables should be labelled). 3 Remove M622 Modules from slots H14, H15, and H16. 4 Insert M622 Modules just removed into slots H17, J23, and J24. 5 Power up. (The RP15 is now able to run using only the maintenance logic.) To place the RP15 back on-line, simply reverse Steps 1 through 5. 6 Set address switches to 200. 7 Select AC switch options from Table 6-3 (see NOTE below). 8 Press I/O RESET and then START. NOTE It is suggested that the following be done for the first complete pass of the program. Set AC switch 6 and clear all others (AC switch 4 should also be set if API is not available). This allows all failing tests in the program to make themselves known via TTY output. The failing tests should then be worked on one at a time, starting with the first that failed and working toward the last, using AC switch 0 to select each failing test. Table 6-3 AC Switch Options for Instruction Test AC Switch Function o Set to request a manual intervention at the completion of the test currently in progress, or at the beginning of the program. The program indicates when it has acknowledged the setting of the switch by ringing the TTY bell. At this time, the operator may select a specific test by setting the desired number in AC switches 12-17, and then clearing AC switch O. When set, it will cause a failing test to loop without halting (whether or not the test continues to fail). When cleared, and AC switch 6 is also cleared, the program wi II halt at the end of the failing test. The operator may press CONTINUE to repeat the test; or, if an oscilloscope loop has been provided for the failing test, he may load the starting address of the oscilloscope loop into the address switches, press I/O RESET and START. The osci 1I0scope loops provided attempt to duplicate the failing portion of a test in the simplest way possible. 2 When set, it will delete all TTY messages and cause the TTY bell to ring when an error is detected. 3 Set to delete ringing the TTY bell on detecting an error. 6-6 Table 6-3 (Cont) AC Switch Options for Instruction Test AC Switch Function 4 Set to indicate that API is not available. 5 Set to loop tests 67 to 150 (data transfer tests) after running tests 00 to 150 6 If AC switch 0 was not used to select a test, and AC switches 1-3 are not set, and a test fai Is whi Ie this switch is set, the program wi II output the error message and go on to the next test. 12-17 Set to indicate the test number desired. Used in the following manner: Procedure Step 1 Set AC switch o. 2 Set AC switches 12-17 to indicate desired test number. 3 Clear AC switch 0 The selected test will loop forever unti I interrupted by either an error or AC switch o. On starting, the program will output the question: WISH TO CHANGE 10TIS (TYPE Y OR N)? If the operator types Y, two additional questions will be output, one at a time, allowing the operator to change the two Device Select Codes (DSC) associated with the RP15 lOTs. Following each question, the operator must respond with the two digits that will replace that particular DSC. The two questions wi II appear as follows: CHANGE DSC 63 TO ? CHANGE DSC 64 TO ? If AC switch 4 is not set, the following question will be output: WISH TO CHANGE API CHANNEL ADDRESS (TYPE Y OR N)? If the operator types Y, the following will be output: CHANGE CHANNEL FROM 64 TO ? At this time, the operator must respond with the new two digit API channel address. The program wi II indicate the end of a pass by typing: END 6-7 In analyzing errors, the failing test number and additional information, when required, are output on the TTY. A complete document, with test descriptions and error explanations, is supplied with each MAINDEC. The function of each test is explained in the program listing along with a brief description of what caused the error. 6.3.2.2 RP15 Formatter - This program was designed to format RP02P Disk Packs and to perform a confidence cheok on both Header and Data Fields after formatting. In this paragraph, a brief summary is given of this test. For complete details, refer to MAINDEC-15-D5FB-D. To load the diagnostic: Step Procedure Load tape into reader. : 2 Place BANK MODE switch on BANK MODE. 3 Set address switches to 17700. 4 Press I/O RESET and then READ IN. NOTE The program is self-starting. On starting, the program will ask two basic questions via the TTY. The first will appear as follows: WISH TO CHANGE 10TIS (TYPE Y OR N)? If the operator types Y, two additional questions will be output (one at a time), allowing the operator to change the 2 DSCs associated with the RP15 lOTs. Following each question, the operator must respond with the two digits that will replace that particular DSC. The two questions will appear as follows: CHANGE DSC 63 TO ? and CHANGE DSC 64 TO ? The second basic question will appear as follows: FORMAT WHAT UNITS? The operator types the unit number of each drive containing a disk pack that requires formatting, and then a carriage return to terminate the line. If only one unit was selected, the operator is required to make one additional decision. The program responds to the one unit request by typing: WHAT CYLINDER? 6-8 If the operator desires to format and check only one cylinder on the unit selected, he may do so by typing the octal cylinder number and then a carriage return to terminate the line. If the entire disk pack is to be formatted and checked, the operator types only the carriage return. At this time, the status of the NORMAL/FORMAT switch is sensed and, if necessary, the program outputs the message: SET NORMAL/FORMAT SW TO FORMAT After completing the format portion, the program wi II output the message: SET NORMAL/FORMAT SW TO NORMAL The program indicates it is finished by typing: DONE The program then restarts. 6.3.2.3 RP1S Address Test - The RP1S Address Test is designed to verify all header words on an RP02 Disk Pack and provide a test of head motion. The test will not destroy any data; it is divided into two parts. The first part of the test is a sequential read of all header words on the pack. The second part is a head motion test that has both known patterns and random patterns. The test will exercise from one to eight units. In this paragraph, a brief summary of the test is given. For complete details, refer to MAl NDEC-1S-DSDB-D. To load the diagnostic: Step Procedure 1 Set the address switches to 17700. 2 Set BANK MODE switch to BANK MODE. 3 Set the data switches to 000000. 4 Press I/O RESET and then READ IN. NOTE The program is self-starting. After the initial typeout, set the Data Switches·as follows (normal setting is 000000 ): 8 SWOO= 1 Halt on Error Flag SW01=1 Ignore Error Flag 6-9 SW02= 1 Eli mi nate a II typeouts SW02= 1 Stay in presently selected cylinder and surface. NOTE The Disk Pack Drive must be running and on line. The FORMAT/NORMAL switch must be in NORMAL position. (The position of the write ENABLE/DISABLE switch is unimportant since no writing is done.) The starting address is 200. If the program starts at address 201, the random number generator initialization and the change lOT message are eliminated. Selecting lOT DSCs and the units are the only operator actions required; these are done from the keyboard. Starting by initial loading or at location 200, the following messages will be typed: --RP09/15 ADDRESS TEST-CHANGE lOT DEVICE CODES? TYPE Y OR N At this point, only Y for yes or N for no is acceptable. If no, the next message will be: TEST UNIT The expected reply is ° to 7, which indicates the Drive Number and sequence to be tested in. Up to eight inputs will be accepted. Any sequence is acceptable; e.g., 7,7,4,4,0,0,0,0, will test drive 7 twice, drive 4 twice, and drive 0 four times before repeating the sequence. The next question concerns the amount of iterations for random address searches before exiting that drive. Each iteration requires about three minutes. Any octal number up to six digits is acceptable as an input. Any number of iterations above seven will result in a further query to the operator as to his intentions. A carriage return terminates all answers. A rubout eliminates previous inputs. After a static controller check, the following message will be printed: START UNIT X At the completion of that unit the following is printed: END UNIT X If the lOT codes are to be changed, then the presently selected code wi II be typed; the expected reply will be two octal characters. This reply is followed by a second question, as there are two device codes for the RP 15 Control Ier • 6-10 6.3.2.4 RP15 Random Data Exerciser - The RP15 Random Data Exerciser is intended to provide a checkout of the RP15 Controller and up to eight RP02 Disk Packs. The Exerciser is segmented into various parts that test the surface and VFO. This paragraph gives a brief summary of the test. For complete details, refer to MAINDEC-15-D5EB-D. To load the diagnostic: Step Procedure Set the address switches to 17700. 2 Set the BANK MODE switch to BANK MODE. 3 Set the data switches to 000000. 4 Depress I/O RESET and then READ IN. The program is self-starting upon initial load. Location 200 is the starting address; location 201 will eliminate the initial dialogue. Normal position for the Data Switches is 000000. The operator must ensure that the drives are powered up and on-line. No attempt is made to preserve data. On each RP02 Disk Pack to be tested: Step Procedure Set ENABLE/DISABLE switch to ENABLE on drives to be tested. 2 Set READ WRITE/READ ONLY switch to READ WRITE. 3 Set START/STOP switch to START. On the RP15 Controller: Procedure Step Set FORMAT/NORMAL switch to NORMAL. 2 Set LOCKOUT switch to unmarked (normal) position. On the PDP-15 set the following: NOTE Normal setting of data switches is 000000. SWOO= 1 Halt on error flag SW01=1 Ignore error flag SW02=1 Print all data errors SW03= 1 Inhibit all typing SW04=1 Stay in random write/read test 6-11 SW05= 1 Do not ha It on a control Ier error SW17=1 Print error for maintenance operations 6.3.2.5 Vibration Tests - Many malfunctions can be located by performing a timing margin check on the PDP-15 while running a particular diagnostic. In addition, a vibration test may be performed on the RP15. To perform a vibration test: Step Procedure Check switches for immunity from vibration and shock by wiggling them and tapping them with the fingers. 2 Check modules for immunity from vibration and shock in two planes. To check the plane perpendicular to the module mounting plane, tap each module handle with the fingers. To check the plane parallel to the module mounting plane, slide a Teflon rod horizontally across the modules. This should be done slowly and twice in each direction. The Teflon rod should be 8-in. long, 3/8-in. in diameter, and should be held between the fingers 6-in. from the end that is applied to the modules. This test will indicate bad components and poor solder joints. CAUTION If vibration tests are applied too vigorously, damage to modules could result. After localizing the fault to within a functional logic element, run a diagnostic which uses all functions of that element. Trace signal flow through the suspected element with an osci Iloscope by synchronizing the oscilloscope sweep with control signals or clock pulses. Check for proper levels, durations, rise and fall times, and timing of all input and output signals. 6.3.3 Switch Panel Testing - LOCKOUT, LO, and LOA Switches Some isolated faults pertaining to lockout addressing can be located via the RP15 Instruction Test. Refer to the writeup supplied with MAINDEC-15-D5HB-D. 6.3.4 Changing Panel Indicator Bulbs To replace an indicator bulb when it burns out (see Figure 6-1): NOTE Panels are separately removable, but cables must be redressed in this case. 6-12 Step Procedure Power down the system. 2 Remove the indicator bezels from the front of the rack. (They snap out.) 3 Remove the two orange and black power supply pairs behind the rack from the indicator rack. 4 Remove the eight interconnecting cables from the module rack. 5 Remove eight screws that secure the indicator panels to the cabinet and carefully remove the two panels from the front. 6 After replacing faulty bulb{s}, reassemble in reverse order. CAUTION In reconnecting indicator power supply, be sure to connect black tabs to GND and orange tabs to +6.5V, labelled on the edge of the module. 6-13 INDICATOR PANELS REMOVE 4 SCREWS EACH SIDE REMOVE TWO PAIRS - UNPLUG 8 CABLES Figure 6-1 INDICATOR POWER SUPPLIES TYPE 716 RP15 Indicator Panels and Power Supplies 6-14 CHAPTER 7 SYSTEM SPECIFICATIONS 7.1 GENERAL This chapter contains the mechanical description of the RP15/02 System. The various equipment specifications, cable interconnections, and equipment supplied are included in tabular form. 7.2 MECHANICAL DESCRIPTION The RP15 is housed in an H963 cabinet that contains four H911 mounting panels. The logic utilizes M Series integrated circuit modules. Two indicator panels are located at the top of the unit; switches are located on a logic panel available inside the front door. These panels comprise monitoring and switch facilities for data and address indication and control. The unit contains built-in self-testing facilities, fan assemblies, power supplies for both logic and indicators, and a power control. The RP15 is shipped complete and factory-tested, including all interconnecting cables to the PDP-15 Computer System. Cables to the RP02 Disk Pack Drive{s) are provided as part of that unit. Two types of controllers are supplied depending upon requirements: the DEC Type RP15-A for 6O-Hz operation, and the RP15-B for 50-Hz operation. The PDP-15 Computer System, when equipped with an RP15 Control I er, can accommodate up to eight RP02 Disk Pack Drives per RP15 Controller. 7.3 EQUIPMENT SPECIFICATIONS The physical, environmental, electrical, and performance specifications for both the RP15 and the RP02 are listed below. 7.3.1 Physical Dimensions RP15 RP02 Height 72 in. 39 in. Width 21 in. 30 in. (Continued on page 7-2) 7-1 Dimensions RP15 RP02 Depth 30 in. 24 in. Weight 3051b 2951b Front 36 in. 36 in. Rear 36 in. 36in. Service Clearance 7.3.2 Environmental Satisfactory operation is achieved under normal conditions of humidity, shock, and vibration. Ambient RP15 RP02 Operating Temp. 55-100°F 60-90°F Humidity 25-95% ReI 8-80% ReI 7.3.3 Electrical Power requirements at line cord: RP15A = 110 Vac 1-ph, 60 Hz @7.0A Nominal, 25.0A Surge RP15B = 220 Vac 1-ph, 50 Hz @ 3.6A Nominal, 13.0A Surge RP02A = 208 Vac 1 of 3 phases, 60 Hz @ 6.0A Nominal, 25.0A Surge RP02B = 208 Vac 1 of 3 phases, 50 Hz @ 6.0A Nominal, 25.0A Surge • NOTE Three-phase AC power is wired to each unit, but an individual drive will draw current from one phase only. Phases are rotated in a multi -unit system to provide a balanced load. Power/Heat Dissipation: RP 15 = 805W, 2747 Btu;hr RP02 = 1250W, 4250 Btu/hr Internal Power: From two self-contained Power Supplies, Types H721 and H716, and one self-contained Type 841B, Power Control providing +10, +5, and -15 Vdc for logic power, 6.5 Vdc for indicator power, and 120 Vac for fans. Cable Lengths: See Figure 7-1 and Table 7-1 . 7-2 19 20 r? '? /H (5 ~ (5 II) II) II) II) 0 0 II) II) II) II) 0 0 0 0 0 0 0 « 0 0 « I « 0 0 r;- / 0 22 0 0 '? (5 21 « 0 r;- I'- I'- 0 0 I ,( 0 I 0 0 ~ ~ \ II) v\I) ............ \B80) \ 10 N .., t-- I--~ J 0 '? '? (3 0 '? (5 II) II) II) II) II) II) 0 0 0 0 0 0 0 0 0 0 a « 0 « " a 0 « 0 UNIT 1 ~RP02 RP02 D-AD-700646S-I-0 @ D-IA-7006463-2S-0 I:~ 't~-AD-7DD66DO-I-0 ,-------~~~- ~ 0 [..; ......... RPIS PDP-IS ~Q @ D-AD-7006601-2-0 - ; - - - f D-UA-RP1S-0-0 r:::::::::::~~~~r~ ____ t -__ 208 VAC 3 PHASE ® r- D-AD-7006464-0-0 p_ _ _J~ ~2 r----------------------------------- J 1---+-0-AD-700646S-1-0@ D - AD -7006601-3 - 0 UNIT 4 RP02 UNIT :3 RP02 RP02 .... ~'" 1/ D-AD-7006600-1-~1 ~~S~0:/6:0::H:Z::::::::::::::: ~::::::::::~:::::i:0~-A~OS-~7~0;0~6~60~1~-~3~-0~1~~~t-~ UNIT S II RP02 D:AQ-700646S-I-0 0 r;- 0 UNIT 2 UNITO I II) II) I'- I'- .~ ± 7 '? (3 I'- D-UA-RP02-0-0 -- I'- 0 ~ J3 ~ ~.,.u.II:. .=,\=::;:'-- ~ I I ( I~n, HI D-AD-7006601-3-0 ""- ~~ ~ ~rAD-700646S-I-~ ~ ~ ~~D-AD-70064iS-l-0':::::.. ~ ~g ~~ 'r-_t--~~£"":._D-_AO_-..... 7006~60..;.0-..;..I-..;.O--lro... """"\.,.....-+---~ t ,,~II=/~=:::t"/rr--0~ D-AD-7006601-3-0 I --.I D-AD-7006601-3-0~ D-UA-BC09B-X-0 (SEE NOTE 2) o D-AD-700646S-1-0-- H§ ~ I ~~ UNIT 6 1 I~ ~I~ UNIT 7 RP02 I '---....;.------~..,06----+-~-1+~....,.' O-AD -7006465~ 0 (,S) 9107673- 6-0 110/220 VAC 50160 Hz 0-IA-700S702-0-0 NOTES: I. For ACI DC power wiri ng of RPt5, refer to: D-UA- RPI5-0- 0 (sheet 2) . 2. For location from the PDP-15 and length of BC09B cable, refer to: D-AR-PDP-IS-0-2 (sheet 3814). ~ ~ ~D-AO-~:O~'-O ® ® 208 VAC :3 PHASE 50/60 Hz D-AD-7006464-0-0 F6 0-AD-7006464-0-0 @ RP02 D-AD-7006601-3-0 D-AD-7006601-3-0 208 VAC 3 PHASE 50/60 Hz ITEM NO, CABLE PART NO. CO D-IA-7006463-2S-0 UN IT NUMBER o CI-7 0-AD-7006465-1-0 DO D-AO-700660t-2- 0 01-7 D-AD-7006601-3-0 2 3 4 S 6 7 I FO, 3,6 0-AD-7006464-0-0 Ft,2,4,S,7 D-AD -7006600-1 - 0 ~ TERMINATOR 0-AC-70069:32-0-0 15-0512 3. Circled letters refer to table 7-t . Figure 7-1 Cable Particulars 7-3 Table 7-1 Cable Particulars Cable Interface (See Figure 7-1) Qty. Supplied With RP02-X RP15 From To Length Ft Std. Max. A 1 Yes OW15 RP15 50 7 B 1 Yes POP-15 RP15 50 7 CO 1 Yes RP15 RP02-0 100* 25 Cl-C7 1 Yes RP02-X RP02-X 100* 8 DO 1 Yes RP15 RP02-0 50 25 01-07 1 Yes RP15 RP02-X 50 40 E 1 RP15 outlet N/A 25 FO, F3, F6 1 Yes RP02-X outlet N/A 25 Fl, F2, F4, F5, F7 1 Yes RP02-X RP02-X N/A 8 Yes *Total length of CO through C7 must not exceed 100 ft. 7.3.4 Performance Word Transfer Rate = 7 .4 fJS/word (based on 18-bit word) Positional Access = 80.0 ms MAX 20.0 ms MIN 50.0 ms AVG Rotati ona I Access = 25 .0 ms MAX 0.0 ms MIN 12.5 ms AVG Latency Ti me = 62.5 ms AVG 105.0 ms MAX Capacity (in 18-bit words) = 80.92 x 106 MAX (8 drives) 10.24 x 106 MIN (1 drive) Words Available to a Single Addressing = 262, 144 MAX 1 MIN 7-5 CHAPTER 8 INSTALLLATION 8.1 GENERAL This chapter is concerned with installati on of the RP 15. Turn-on and checkout procedures are given to confirm operation of the equipment once it has been installed. Provisions are made for built-in testing of the RP 15 a lone. These procedures are a part of the checkout. 8.2 UNPACKING For particular procedures for unpacking, refer to Chapter 4 of PDP-15 Installation Manual, DEC-15H2AB-D. 8.2.1 Special Handling The RP15 is packed in accordance with best commercial practice. No special handling procedures are required beyond normal care afforded any piece of scientific equipment of comparable size and weight. Particular care should be exercised in the use of cranes or hoists to prevent damage to the unit. 8.2.2 Inspection On receipt, the equipment should be inspected for any visible damage in transit, such as dents and abrasions. For general inspection procedures, refer to DEC-15-H2AB-D. Inspect the logic modules for foreign matter which might have lodged in them during shipment. Any damage observed should be reported immediately to both the carrier and the manufacturer. Check the contents of the carton with the shipping document and with Table 8-1. Report any omissions immediately to the local DEC sales office. 8 .2 .3 Power Requ i rements The RP15 is supplied with its own self-contained power supplies and power control. The +10, +6.5, +5, and -15 Vdc requirements of the unit are provided by a DEC Type H721 Power Supply, two DEC 8-1 Type 716 Power Supplies, and a DEC Type 8418 Power Control. Differences for accommodating either 50 or 60 Hz are made within the basic unit, designated RP15A for 60-Hz and RP158 for 50-Hz operation. Power requirements at the main units are listed in Paragraph 7.3.3. The RP02 contains its own internal power supply for the transport mechanism and logic circuitry. Ac power for the unit is taken by daisy-chain jumper wiring. Units are wired in phase rotation to equalize ac loading. Power requirements at the main units are listed in Paragraph 7.3.3. Table 8-1 RP15 Checklist DEC': DATE: CUSTOMER: CHECKER: I. RP 15 A. I/O BUS CABLE (BC09-B) B. REMOTE POWER CABLE (EXTENSION CORD) C. DIAGNOSTIC TAPES, WRITE-UPS & LISTINGS 1. 2• 3• 4. D. E. F. G. H. I. J. II. Formatter Instructi on Test Address Test Random Data Test RP15 MAINTENANCE MANUAL RP15 PRINT SET RP02 CLEANING KIT TERMINATOR FOR LAST UNIT SYSTEM SOFTWARE ECO STATUS SHEET FUSE, 5 AMP SLO-BLOW (5) RP02 A. UNIT CABLE B. BUS CABLE C. POWER CABLE D. MAINTENANCE MANUALS (2) E. SPARE PACK FILTER (1 per pack) F. DISK PACK (RP02P) G. DISK PACK LOG H. INSERT KIT, FILE IDENTIFICATION I. KICK PLATE, SIDE (2) J. KICK PLATE FRONT & REAR (2) K. CUP, CASTOR (4) L. SCREW, BINDER HD. #8-32 x .30 (12) 8-2 8.3 INSTALLATION PROCEDURE Install the RP15 and RP02/s per site plan. Overall physical dimensions are given in Figure 8-1. [-------n I r------- - REAR -1 I 36 REAR T VIEW I 36" il .--_CL_E_A.... R_AN_C_E_... t I_I I I I I ",,1 VIEW i1t : RP02 - 1~30"-.! 11 I I~!I FRONT VIEW '+------+' 38" I 36" 1--1-- l CLEARANCE: I 1 RP15 ~2~1~ I 36" :- - ------: I : CLEARANCE : I FRONT : FRONT 24' I I I I ~24"~ FRONT VIEW 72" SlOE VIEW SlOE VIEW 1 I LJ 09-0347 Figure 8-1 RP15/02 Overall Dimensions 8.3. 1 Converti ng to Another Power Source Equipment is normally shipped with power supplies converted to each customer's requirements. If, however, it becomes necessary to convert the unit to another power source (e.g., from 110 to 220), proceed as follows (see Figures 8-2 and 8-3): 8-3 Step Procedure Remove all power from the PDP-15 and the RP15/02. 2 Remove the two orange jumpers located on the face of the 841 B Power Control. These jumpers are marked JUMPER for 110 Vac input (see Figure 8-2). 3 Remove the perforated top on the Logic Power Supply H721 (see Figure 8-2). 4 Remove the jumpers between points 1 and 3, 2 and 4, and 3 and 5, on the terminal block marked TB 1 (see Figure 8-3). 5 Add a jumper between points 2 and 3, and 4 and 5 of TB 1. REMOTE AC IN FROM PROCESSOR REMOVE THESE JUMPERS (HIDDEN) REMOTE AC OUT TO NEXT UNIT IN LINE Figure 8-2 REMOVE THIS PERFORATED TOP RP15 Power Control 8-4 TB1 Figure 8-3 RP15 Logic Power Supply Primary Wiring Five adjustments are provided in the logic power supply Type H721. They are: a. +5 .OV adjust b. +5.0V over-voltage adjust c. +5.0V over-current adjust (fold back) d. +10 .OV adjust e. -15V adjust. These adjustments are made at the factory. 8-5 8.3.2 Installing the RP15 Cabinet The RP15 Cabinet is provided with roll-around casters and adjustable leveling feet. It is not necessary to bolt the cabinet to the mounting floor unless conditions indicate otherwise (e.g., shipboard installation) . CAUTION Do not attempt installation until DEC has been notified and a Field Service Representative is present. ~ep Pro~dure 1 Remove power from a II systems. 2 Position the RP15 Cabinet as the first bay to the left of the PDP-15 Processor. 3 Remove the left-hand side panel from the PDP-15 Processor Cabinet and the right-hand side panel from the RP15 Cabinet. 4 Butt the cabinets together while holding the fi Iler strips in place; bolt through both cabinets and the filler strips (see Figure 8-4). Do not tighten the bolts securely at this time. 5 Lower the leveling feet, making sure that the cabinet(s) are not resting on the roll-around casters but are supported on the leveling feet. 6 Level both cabinets with a spirit level and ensure that all leveling feet are seated firmly on the floor. 7 Tighten the bolts that secure the cabinet groups together and then recheck the cabinet leveling. Again ensure that all leveling feet are seated firmly on the floor. 8.3.3 Installing Cables Normally DEC cabinet interconnecting cables are of standard lengths and are factory installed. In the case where an RP15 is added to a system after it has been installed, only the standard cables to connect the new equipment into the system are suppl ied. These cables are connected at the installation site, and the termination point of each cable is identified. Proceed as follows: Step Procedure Install the grounding cable between a bottom horizontal rack member and either the Processor Main Frame or to a system grounding bus. 2 Connect cables between the RP15 and the RP02 as listed in Table 8-2. NOTE When cables are installed, strain-relief cable clamps should be attached to the frame member as shown in Figure 8-5. 3 Tighten connectors, so equipped, into the cable retaining block as shown (Continued on page 8-7) in Figure 8-5. 8-6 Step Procedure 4 Connect cables between the RP 15 and the I/O as indicated in Table 8-3. NOTE Install the RP15 physically first on the positive I/O bus string. This is necessary to avoid timing errors. 5 Connect cables, supplied with each RP02, between each Drive in the string. NOTE The RP15 requires no margin checking; therefore, this cable is not supplied. 6 Install RP02 Terminator Plug in last RP02 in the string. 7 Connect all power cables including Remote AC lines as shown in Figure 8-2. 15-0513 Figure 8-4 RP15 Cabinet Bolting Diagram 8-7 Table 8-2 RP15/RP02 Interface Chart Cable Type Cable Lgh. (Ft) Max. +5V Terminator Voltage, Select Unit, Read & Write Coax, Attenti on. W028 50 Tag Lines, Bus Lines, Selected Unit On Line, Read Only, File Unsafe, Ready, Seek Incomplete, Index Pulse, Sector Pulse, Sequence Out, and Cylinder Address. W850 50 Between RP15 RP02 Function H/J-19,20 21, 22 J5 H/J-23,24 J3 TIGHTEN INTO CABLE RETAINING BLOCK STRAIN -RELIEF CABLE CLAMPS Figure 8-5 RP02 Cable Connections to RP15 8-8 Table 8-3 RP15 I/O Interface Chart RP15 DW15 Function Cable Type Cable Lgh. (Ft) Max. H-1/2 A-4/5 10 BUS, SYNC, lOPs, SKIP PROG INT, RD RQ, STATUS, PWRCLR, DS, SD BC09B 7 J-1/2 B-4/5 10 CONTROL SIGS, WRITE RQ, INC MB & CA, API RQ, API GR, API EN, DCH RQ, DCH GRANT, DCH EN Between 8.3.4 Setting Unit Number Designator Once installed, the large unit number designator for each RP02 in line should be set. This static designator is located on the RP02 control panel to the right of the READ WRITE/READ 0 NL Y switch. To set the unit number designator: Procedure Raise the top cover of the control panel by releasing the latch located at the back of the RP02. 2 Inside the cabinet, loosen the two thumb screws above the indicator housing and move the glass cover back to gain access to the housing. 3 Move the indicator logo manually to the proper designation for that unit. 4 Replace all hardware in reverse order. 8.4 TURN-ON AND CHECKOUT When the RP15 has been installed, operation may be verified by proceding as outlined below. 8.4. 1 Built-In Testing Without RP02 The RP 15 provides self-contained maintenance hardware. The equipment is designed to simulate the RP02, so that the RP15 can be tested and verified without the use of an on-line Disk Pack Drive: Step Procedure Power down the system. 2 Remove Bus and Unit Cables to RP02/s (Slots H19-H24 and J19-J24). 8-9 Step Procedure 3 Remove the M622 Modules in locations H14, H 15, and H16 on the RP15. 4 Replace these three modules in RP15 locations H17, J23, and J24. 5 Power up the system. 6 Load and run the RP 15 Instruction Test, MAINDEC-15-D5HA-D. 8.4.2 Testing With RP02 To perform a fi na I system test: Step Procedure Power down the system. 2 Replace the three M622 Modules, repositioned in Paragraph 8.4.1, in their normal positions: H14, H15, and H16. 3 Replace all cables removed in Paragraph 8.4.1. 4 Ensure that all switches are in their normal positions and that all equipment is powered. 5 Load and run the RP15 Random Data Exerciser, MAINDEC-15D5EA-D. 8-10 Digital Equipment Corporation Maynard, Massachusetts printed in U.S.A.
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