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DEC-15-H3AA-D

January 1971

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Document:	AD15
Order Number:	DEC-15-H3AA-D
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Digital Equipment Corporation
Maynard, Massachusetts

PDP-15 Systems
Maintenance Manual

AD15 Analog Subsystem

DEC-lS-H3AA-D

AD15
ANALOG SUBSYSTEM
MAINTENANCE MANUAL

DIGITAL EQUIPMENT CORPORATION. MAYNARD, MASSACHUSETTS

1st Edition January 1971

The material in this manual is for information purposes and is subject to change without notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
PDP
DEC
FOCAL
FLIP CHIP
COMPUTER LAB
DIGITAL

CONTENTS
Page
CHAPTER 1

BASIC DESCRIPTION

1.1

Purpose of Equipment

1-1

1.2

System Functional Description

1-1

1 .2. 1

Interface

1-4

1 .2.2

Multiplexer

1-4

1.2.3

Analog-to-Digital Converter

1-5

1.3

Physical Description

1-5

1 .3. 1

AD15 Minimum System Configuration

1-5

1.3.1.1

Frame and Wired Assembly

1-5

1 .3.1 .2

Amphenol Connector Assembly

1-7

1.3.1.3

H929B Filler Plates

1-8

1.3. 1.4

Analog Power Supply

1-10

1.3. 1.5

I/O Bus Cabl e Assembly

1-10

1 .3.2

System Expansion

1-10

1.4

Specifications

1-11

CHAPTER 2

DETAILED THEORY OF OPERATION

2.1

Modes of Operation

2-1

2.1.1

Program Contro I

2-1

2.1.2

PDP-15 Data Channel

2-1

2.1.3

Add-to- Memory

2-2

2.2

Program Interrupt

2-2

2.3

Automatic Priority Interrupt

2-3

2.4

Latency

2-3

2.5

Detailed Block Diagram Description

2-4

2.5.1

Power Suppl ies

2-4

2.5.2

Sync Logic

2-4

2.5.3

Analog Multiplexing

2-4

2.5.4

Gain Selection

2-4

2.5.5

Sample and Hold Amplifier

2-7

2.5.6

Analog-to-Digital Conversion

2-7

2.5.7

Flag Status and lOT Decoding

2-7

2.6

Detailed Logic Analysis

2-7

iii

CONTENTS (Cont)
Page
2.6.1

Status Register and Buffered Data Register

2-8

2.6.2

Multiplexer Channel Address Register

2-8

2.6.3

Flag Logic

2-9

2.6.3.1

Word Count Flag

2-9

2.6.3.2

API Flag

2-10

2.6.3.3

Memory Flag

2-10

2.6.3.4

Read/Write Logic

2-10

2.6.3.5

DONE Flag

2-11

2.6.3.6

DCH Flag

2-11

2.6.3.7

Flag Testing

2-11

2.6.4

Device Decoders, API and Data Channel Logic

2-12

2.6.5

Analog Subsection

2-12

2.6.5.1

Gain Switching

2-13

2.6.5.2

Sample and Hold Amplifier

2-13

2.6.5.3

Analog-to-Digital Converter

2-13

2.6.6

Binary-Octal Decoder and Analog Multiplexer

2-14

2.6.7

I/o Bus Drivers

2-15

2.6.8

Bus Receivers, Analog Inputs, and I/O Bus Interface

2-16

2.6.9

Expansion Unit AM01

2-16

CHAPTER 3

lOT INSTRUCTION FORMAT

3. 1

Equipment Turn-On/Turn-Off Procedures

3-1

3.2

Instruction and Data Formats

3-1

3.2. 1

lOT Timing

3-1

3.2.2

lOT Instruction Format

3-1

3.2.2.1

ADCV {convert} Octal Code 701304

3-2

3.2.2.2

ADRB {read data buffer} Octal Code 701302

3-2

3.2.2.3

ADRS (read status register) Octal Code 701342

3-2

3.2.2.4

ADCF {clear all AD15 flags} Octal Code 701362

3-2

3.2.2.5

ADSF {skip on A/D DONE flag} Octal Code 701301

3-2

3.2.3

Output Status Word Format

3-2

3.2.4

Data Word Format

3-3

3.2.4.1

WCSF (skip on word count overflow flag) Octal
Code 701341

3-3

CONTENTS (Cont)
Page
MSSF (skip on memory overflow flag) Octal
Code 701321

3-3

3.2.5

Input Status Word

3-3

3.3

Programming Examples

3-4

3.3.1

Program Control Mode

3-4

3.3.2

Data Channel Mode - Sequential Operation

3-5

3.3.3

Data Channel Mode - Random Operation

3-7

3.2.4.2

CHAPTER 4

INSTALLATION AND ADJUSTMENTS

4. 1

Installation Planning

4-1

4.2

Environmental Requirements

4-1

4.3

Installation Procedure

4-1

4.4

Adjustments

4-3

CHAPTER 5

MAINTENANCE

5. 1

AD15 MAINDEC-15-D6GA-D(D) Diagnostic Program

5-1

5.2

Preventive Maintenance

5-2

5.2.1

Preventive Maintenance Tasks

5-2

5.3

Corrective Maintenance

5-3

5.3. 1

Prel iminary Investigation

5-4

5.3.2

System Troub I eshooti ng

5-4

5.3.3

Logic Troubleshooting

5-4

5.3.4

Circuit Troubl eshooting

5-5

5.3.5

Validation Tests

5-7

5.3.6

Recording

5-7

5.4

Test Equipment

5-7

5.5

Module Handling and Repair

5-9

5.6

Spare Parts

5-9

CHAPTER 6

Engineering Drawings

6. 1

Draw i ng Cod es

6-1

6.2

Drawing Number Index

6-1

6.3

Signal Glossary

6-2

ILLUSTRATIONS

Title

Art No.

Page

1-1

AD15 Signal Interface Diagram

15-0440

1-2

AD15 System Block Diagram

15-0439

1-3

Analog Cabinet H963-P

15-0438

1-7

1-4

BCOl P-4 Cable Assembly

5316-2

1-8

1-5

BC01 N-4 Cable Assembly

5316-1

1-9

1-6

Wi ri ng of User Inputs

15-0437

1-9

2-1

AD15 Analog Subsystem Functional
Block Di agram

15-0428

2-5

2-2

Analog Addressing

15-0427

2-7

2-3

External Sync Timing Diagram

15-0426

2-13

2-4

Sequential Mode Timing Relationships

15-0424

2-14

2-5

Random Mode Timing Relationships

15-0425

2-15

3-1

lOT Instruction Format

15-0436

3-2

Output Status Word Format

15-0433

3-3

Data Word Format

15-0434

3-3

3-4

Input Status Word Format

15-0435

3-4

3-5

Exampl e of Program Control Input Status
Word

15-0431

3-5

3-6

Exampl e of Sequential Mode Status
Word

15-0432

3-6

3-7

Exampl es of Status Words - Random
Operation

15-0429

3-7

4-1

Jumper Connections for G729 Card

15-0423

4-3

5-1

IC Location

15-0430

5-6

5-2

IC Pin Location

15-0430

5-6

Figure No.

TABLES
Table No.

Title

Page

1-1

AD15 Equipment and Module Complement

1-6

1-2

AM01-A Equipment and Module Complement

1-10

1-3

System Expans ions

1-11

1-4

General Specifications

1-11

4-1

Adjustments

4-3

TABLES (Cont)

Table No.

Title

Page

5-1

Maintenance Equipment

5-7

5-2

Spare Parts List

5-9

6-1

List of AD15 Drawings

6-2

Signal Glossary

6-3

vii

FOREWORD

The AD 15 Analog Subsystem Maintenance Manual consists of six chapters that cover the following
genera I topi cs:
Chapter 1 contains a functional and physical description of the AD15
Analog Subsystem. It also describes system expansion capabi I ities,
options, and accessories. A list of pertinent system parameters and
specifications is included at the end of the chapter.
Chapter 2 contains a detailed block diagram description of the AD15
Analog Subsystem. Logic descriptions of complicated circuitry are also
provided at the end of the chapter.
Chapter 3 describes the AD15 lOT instructions, input status word and
output status word formats. Several programming examples are provided
to illustrate the capabilities of the AD15 Analog Subsystem.
Chapter 4 contains the installation and adjustment procedures for the
AD15.
Chapter 5 provides a description of the procedures required to maintain
and troubleshoot the AD15 Analog Subsystem.
Chapter 6 contains the engineering drawing set and complete signal
glossary for the AD 15.

The reader should be fami liar with and have access to the following documentation:
PDP-15/10 Software System
PDP-15/20/30/40 Advanced Monitor Software System
PDP-15 Maintenance Manual
PDP-15 Module Manual
PDP-15 Interface Manua I
DEC Logic Handbook
AD15 Engineering Specification
AD15 Acceptance and Calibration Procedure
AD15 MAINDEC Diagnostics

DEC-15-GR1A-D
DEC-15-MR2A-D
DEC-15-H2BB-D
DEC-15-H2EA-D
DEC-15-HOAB-D
042D 00370 AKa
A-SP-AD15-0-14
A-SP-AD15-0-15
DEC-15-D6GA-D(D)

CHAPTER 1
BASIC DESCRIPTION

1•1

PURPOSE OF EQUIPMENT

The AD 15 Analog Subsystem is a computer-controlled device capable of multiplexing a maximum of
12S analog channels onto a common bus for analog-to-digital conversion. A maximum of 25,000 conversions per second can be handled by the system. The analog input voltage range is ±10V. Typical
sources of analog input are: biomedical research, data accumulation on patients, and psychological
and scientific investigation. The system can detect analog inputs as low as ±300 fJV increments. The
AD15 is designed to operate with the lS-bit PDP-15 computer.

Both analog channel and gain selection

are under control of the PDP-15. Figure 1-1 illustrates all interface signals between the PDP-15 and
the AD15.

1.2

SYSTEM FUNCTIONAL DESCRIPTION

The AD15 Analog Subsystem consists of an interface, a single-ended multiplexer, and an analog-todigita I converter. Figure 1-2 shows the functional relationship of these units.
To initiate an analog-to-digital conversion, the accumulator in the PDP-15 is initially loaded with a
status word containing gain selection, analog channel selection, and certain designated control functions (refer to Chapter 3). This status word is transferred to the AD 15, using the input-output transfer
(lOT) instructions. Other lOT instructions allow the analog inputs, which have been converted to
digital data, to be transferred to the PDP-15 accumulator, or a Ilow status information such as channel
and flag selection to be transferred to the accumulator. The lOT instructions consist of an operation
code (70 )' a device and subdevice select code, and lOP pulses used for determining program skips and
S
direction of transfer. The lOT instruction uniquely addresses the AD15 with a device select code of

There are two basic operating modes in the AD15 subsystem: program-controlled transfers and data
channel (DCH) transfers. When operating in program control mode, data transfers occur between the
PDP-15 accumulator and the AD 15 under lOT control. When operating in the DCH mode, data transfers are made directly to and from memory under control of the PDP-15 I/O processor. Both sequential

1-1

I10BUSOO-17
I/O ADDRESS LINES 12-17
DATA OFLO
I/O OFLO
110 SYNC
rop I, rop 2, rOP4
I/O PWR CLR
DEVICE SELECT DSO-DS5
AD15
ANALOG
SUBSYSTEM

SUBDEVICE SELECT SDO, SDI

PDP-15
PROCESSOR

REOUEST LINES (6)

SKIP
REa
PI
REO
API REO
DCH REO
RD REO
WR REO

DC H GRANT

API 0 GRANT

..,;

DC H EN IN (FROM PDP-15 OR OTHER PERIPH ERAL)
APr 0 EN IN (FROM PDP-15 OR OTHER PERIPHERAL)
ANALOG INPUTS

DCH EN OUT
(TO NEXT PERIPHERAL)
API 0 EN OUT
(TO NEXT PERIPHERAL)

15-0440

Figure 1-1

AD15 Signal Interface Diagram

ADt5 ANALOG SUBSYSTEM

EXT SYNC
(CONVERT)

EXTII NT
SYNC

CONVERT PULSE

GAIN SWITCHING
ANALOG TO
DIGITAL
CONVERTER
AND SIGNAL
CONDITIQNING
CIRCUITS

DEVICE CODES AND lOP PULSES
INTERFACE AND
CONTROL LOGIC

CHANNEL ADDRESS
PDP -15
COMPUTER
I

CHANNEL ADDRESS
MULTIPLEXER

PI CONTROL SIGNALS

1 3 BIT 0 I G I TAL DATA
(12 BITS PLUS SIGN)
TO PDP-15 COMPUTER

API CONTROL SIGNALS
DCH CONTROL SIGNALS
MODE SELECTION-PROGRAM CONTROL,
DATA CHANNEL (DCH)

WC FLAG

}
SINGLE
ANALOG
OUTPUT

(FROM USER)

MEM FLAG

TO
PDP-15
COMPUTE R

AID DONE

MULTIPLE ANALOG INPUTS

15-0439

Figure 1-2

AD15 System Block Diagram

and random operations are possible in DCH mode. In sequential operation, analog channels are
converted successively; while, in random operation, preselected analog channels can be converted
without regard for any specific sequence.
An add-to-memory feature is employed in the AD15 whereby a converted value can be added to the
contents of an existing memory location. The add-to-memory feature is desirable for signal averaging
techniques.

1.2.1

Interface

The AD15 interface provides an address and data interface between the PDP-15 and the AD15; the
interface also contains additional control logic, which includes selection of external or internal sync.
When internal sync is selected, a convert pulse that initiates the conversion is internally generated
within the AD15. When external sync is selected, the convert pulse is supplied from an external source.
The AD15 interface also provides additional logic to initiate program interrupts (PI), automatic priority
interrupts (API), or data channel activity (DCH). The PI and API logic give the AD15 the capability
to interrupt the PDP-15 computer to request servicing. The data channel logic interrupts the PDP-15
on a cycle-stealing basis and allows direct data transfers between the AD15 and the PDP-15 memory.
For a detailed description of PI, API, or DCH, refer to the PDP-15 Maintenance Manual
(DEC-15-H2BB-D) .
Moreover, the interface logic decodes the lOT device code of 13

(which is used to uniquely address
8
the AD15), decodes the lOP pulses to determine if a skip is to be made, or determines the direction of
data transfer (to or from the AD 15). The status word is also decoded by the interface logi c to determine
the gain selected, the analog input channel selected, and the operating mode.

1.2.2

Multiplexer

The analog channel address supplied to the AD 15 from the PDP-15 is a 7-bit code capable of addressing
a maximum of 128 analog channels. The analog input signal, uniquely addressed by this 7-bit code
from the computer, is multiplexed onto a common output line. This signal is subsequently amplified by
a single-ended operational amplifier. A gain factor of 1, 2, 4 or 8 can be selected for increased dynamic range with unchanged accuracy. For example, if signals are in the range of ±1.25V, a gain of
8 is selected to provide a full-scale deflection of ±10V, as seen by the AID converter. A sample and
hold circuit is provided in the multiplexer to allow sufficient time for analog-to-digital conversion
when sampling rapidly fluctuating voltages.

1-4

1.2.3

Analog-to-Digital Converter

The amplified analog input is applied to an analog-to-digital converter module along with a start pulse.
The module produces 13 output bits corresponding to a 2's complement, right-justified digital value of
the input voltage. When the digital value of the 13 output bits has been determined, an AID DONE
pulse is generated, indicating completion of the conversion. The digital data from the output of the
analog-to-digital converter is then transferred to the PDP-15 where it is used for further processing
(such as signal analysis).
The input voltage range of the analog-to-digital converter is ±10V with an input resistance of 28 kQ.
Greater accuracy of small signals can be obtained by increasing the gain; consequently, these signa Is
approximate the maximum input voltage to the converter, i.e., the gain should be selected to maximize the reading as a percentage of full-scale.

1.3

PHYSICAL DESCRIPTION

A physical description of the AD15 Analog Subsystem is provided in the following paragraphs. A
minimum system 32-channel configuration is described first, followed by a description of increased
system capability in increments of 32 channels. The user can purchase any number of channels in increments of four; however, based on the modular design, the most economical configurations are in increments of 32 channels.

1 .3. 1

AD 15 Minimum System Configuration

When an AD15 subsystem is ordered, the user receives the items listed in Table 1-1. The frame and
wired assembly include all the modules necessary for operation, including one A124 Multiplexer
Module for the switch gain amplifier. Multiplexer modules intended for use with the analog channels
must be ordered separately. Each multiplexer module handles four channels; thus, if a user desires a
32-channel subsystem, he must order an AD15 and eight BA 124 Multiplexer Modules.

He will receive

the items listed in Table 1-1, and also the eight BA 124 Multiplexer Modules specified. The following
paragraphs describe each of the items shipped with the AD15.

1 .3. 1 . 1

Frame and Wired Assembly - The frame and wired assembly is the mounting frame used to

house all the modules and connector boards. The assembly incl udes all the modules I isted in Table 1-1 .
The modules are housed on H803 Connector Blocks (see DEC Logic Handbook for pin assignments); each
connector block has receptac les for eight single-height, single-width modules.
NOTE
Certain modules are double or quadruple height and correspondingly take up two or four module slots.
1-5

Table 1-1
AD15 Equipment and Module Complement

Nomenc lature

Part Number/Module

Module Locations

Frame and Wired Assembly

D-AD-7007029-0-0

Amphenol Connector Cable Assemblies

BC01P-4

Mounting Plate

H929A

Fi Iler Plates

H929B

Analog Power Supply and Chassis

H728

I/O Bus Cable Assembly

BC09B

Multiplexer

BA124

C13, C14, D12,
D13, D14, E12,
E13, F12, F13

Switch Gain Ampl ifier

A222

C12

Sample and Hold Amplifier

A405

A.12

Voltage Regulator

A708

A10

Analog-to-Digital Converter

A877

C10

Bus Data Interface

M101

Device Selector

M103

I/O Bus Multiplexer

M104

A6, A7

Inverter

Mll1

C7, E9

2-lnput NAND Gates

M113

B8, B9, B13, E1, E2

3-lnput NAND Gates

M115

E3, E4

4-lnput NAND Gates

M117

B7, E8

Binary-Octal Decimal Decoder

M161

Bi nary Counter

M211

Six D-Type FI ip-Flops

M216

D7, D8, D9, E6, E7

Dual Delay Multivibrator

M302

A8, A9, F8

I/O Bus Recei ver

M510

C1, C2, D3, C4

Data Bus Driver

M621

D1, D2, D3, D4,
D6

8-Bit Positi ve Input/Output Driver

M622

Ribbon Connector

M908

E14, F14

I/O Bus Connector

M912

A 1, A2, A3, A4

Bus Connector Module

M935

A14

Quantity

t One A 124 Module is supplied with the AD15 and is used by the Switch Gain Amplifier. For 32channel operation, eight additional BA 124 Modules must be ordered.

1-6

Three connector blocks strapped together constitute a system unit (see Figure 1-3). The 32-channel
minimum configuration AD15 contains three system units as shown.

AD15
SYSTEM UNITS

AM01-A UNITS
FOR INCREASED
CAPABILITY

H728 ANALOG
POWER SUPPLY

CONNECTOR PLATES
(PART OF 8C01P-4
CABLE ASSY.)

FILLER PANELS
(H929B)
(H929A) MOUNTING
PLATE AND CABLE
TROUGH

15-0438

Figure 1-3

1.3. 1.2

Analog Cabinet H963-P

Amphenol Connector Assembly - Two BCOl P-4 Amphenol Connector Assemblies are supplied

with the AD15 subsystem. Each cable assembly handles 16 channels. The cable assembly consists of a
user receptacle (Amphenol Series 26), a connector plate that is mounted in a 10-1/2 in. high connector panel, a woven twisted-pair cable, and an M908 Connector Board (see Figure 1-4). User inputs
are soldered to the user receptacle and are routed to the AD15 via the M908 Connector Board, which
plugs into module slots E14 and F14 (see Drawing D-AD-7007029-0-0).

1-7

Figure 1-4

BCOl P-4 Cable Assembly

NOTE
If the user installation employs BNC connectors, two
BCOl N-4 Cable Assembl ies (see Figure 1-5) must be
ordered, because they are notsupplied with the basic
system. The BCOl N-4 assembly is simi lar to the BCOl P-4;
it differs in that the panel houses the BNC connectors
rather than the 32-pin ribbon-type connectors. Customer
inputs are routed to the AD15 via the BNC connector
panel and the M908 Connector Card, which also plugs
into slots E14 and F14. The BNC connector panel is
clearly marked by channel number for wiring of customer inputs.

The user analog inputs can be wired to the AD15, using the Amphenol Series 26 connectors (see
Figure 1-6). Each connector contains 32 pins (one analog signal pin and one ground for each channel).

1.3.1.3

H929B Filler Plates - For the 32-channel minimum configuration AD15, six H929B Filler

Plates are included on the connector panel adjacent to the BCOl P-4 Cable Assembly Connector Plates.
As the system configuration is expanded, the required H929B Filler Plates are removed to allow the
added BCOl P-4 Cable Assembly Connector Plates to be installed.

1-8

Figure 1-5

BCDl N-4 Cable Assembly

PART OF BCOIP-4 CABLE ASSEMBLY
32-PIN RIBBON CONNECTOR
CHANNEL 0

17
18

CHANNEL16

PINS 1-16 ANALOG SIGNALS FOR
CHANNELS 0 THROUGH 15

PINS 17- 32 ANALOG GROUNDS

CHANNEL 15

CHANNEL 31

PINS 1-16 ANALOG SIGNALS FOR
CHANNELS 16 THROUGH 31

PINS 17-32 ANALOG GROUNDS

OTHER END OF CABLE
ASSEMBLY PLUGS
INTO SLOT F 14

OTHER END OF CABLE
ASSEMBLY PLUGS
INTO MODULE SLOT E 14

15-0437

Figure 1-6

Wiring of User Inputs

1-9

1.3.1.4

Analog Power Supply - The AD15 subsystem contains an H728 Analog Power Supply. This

power supply operates with 110V input and provides regulated outputs of 15 Vdc at 2A and 20 Vdc at
1.2A.

1.3.1.5

I/O Bus Cable Assembly - A BC09B I/O Bus Cable is supplied with the AD15 to interface the

AD15 to the PDP-15 computer. The BC09B Cable Assembly comprises two multiconductor cables with
two M912 Connectors at each end and associated hardware. The M912 is a double-height board and
connects to module slots A1, A2 and B1, B2. Module slot A3 is jumpered to A1, A4 is jumpered to A2,
B3 is jumpered to B1, and B4 is jumpered to B2 to provide a receptacle for another BC09B cable that
is daisy-chained to the next device. For a more detailed description of the BC09B Cable Assembly,
refer to the PDP-15 Interface Manual.

1 .3.2

System Expansion

The addition of an AM01-A system unit is required to expand the AD15 from 32 to 64 channels. The
AM01-A comprises two BC01 P-4 Cable Assemblies and the modules I isted in Table 1-2. The required
number of BA124 Multiplexer Modules must be ordered, as with the AD15 subsystem. Thus, to expand
a system from 32 to 64 channels, an AM01-A system unit and eight additional BA 124 Multiplexer
Modules must be ordered. The BC01P-4 Cable Assemblies connect the user's 32 analog channels to the
AD 15. Two of the H929B Fi lIer Plates are removed, and the 32-pin Amphenol Connector Plates (part
of the BC01 P-4) are mounted in place. If the user employs BNC connectors at his site, he must procure two BC01N-4 Cable Assemblies for each 32 channels; they are not supplied with the system.

Table 1-2
AM01-A Equipment and Module Complement

Quantity

Nomenclature

Part Number/Module

Module Locations

Amphenol Connector Cable Assemblies

BC01P-4

8t
1
1
1
2

Multiplexer
Jumper Card
Octal Decoder
Bus Receiver
Bus Connector Card

BA124
G729
M161
M510
M935

C1-C4, D1-D4
B3
B2
E1
A1, A4

t BA 124 Multiplexer Modules are not supplied with the AMOI-A and must be ordered separately.
For an additional 32 channels beyond the 32 channels in the AD15, eight modules must be
ordered.

1-10

Table 1-3 lists different system configurations and the equipment provided with each. The user can
tailor the system to his own individual needs using the examples provided.

Table 1-3
System Expansions

Channel

AD15

28
32
36
60
64
68
92
96
100
124
128

1
1
1
1
1
1
1
1
1
1
1

BA 124 Modul est

AMOl-A

7
8
9
15
16
17
23
24
25
31
32

0
0
1
1
1
2
2
2
3
3
3

t Excluding the A124 Multiplexer Module used with the Switch Gain Amplifier and suppl ied with the System.

1.4

SPECIFICATIONS

Table 1-4 lists the specifications of the AD15 Analog Subsystem.

Table 1-4
General Specifications

Description

Specification

PHYSICAL SPECIFICATIONS
Height - 17 in.
Depth - 1.5 in.
Width - 19 in.

Frame Dimensions

ENVIRO NMENT AL SPECIFICATION S
Cooling

Ambient air (forced)

Temperature range - operating
- storage

0° to 50°C
-25° to +85°C

Humidity

To 90% without condensation

1-11

Table 1-4 (Cont)
General Specifications

Description

Specification

POWER REQUIREMENTS
Input voltage and frequency

105 - 125 Vac
47 to 420 Hz single-phase

AC current

Less than lA

Power dissipation

Less than 100W

ACCURACY
±O.04%

System

±30 PPM/oC

Temperature coefficient
Sample and Hold

±O.02%

Multiplexer and Switch Gain Amplifier

±O.02%

Analog-to-Digital Converter

±O.015% ± 1/2 LSB

30 day long term stability
Temperature coefficient

±20 PPM/oC

RANGE OF INPUT SIGNALS
(gain = 1)
(gain = 2)
(gain = 4)
(gain = 8)

±10V full-scale
± 5V full-scale
±2.5V full-scale
±1 .25V fu II-scale
SAMPLING RATE

25 kHz

Sample and Hold
SYSTEM SPEED
ADC conversion

<351-1 s

ADC conversion, multiplexer, sample and hold
and amplifier settling

< 4O l-ls

Switch Gain Amplifier setting time including
100% overload recovery (x8 gain with 10V input)

<31-1 s

NUMBER OF CHANNELS
To a maximum of 128

Expandab lei n groups of 4
Basic system is 32 channels

1-12

Tab~e 1-4 (Cont)
General Specifications

Specification

Description

INPUT SPECIFICATION

---

Single-ended input
Impedance

Greater than 100 Mn in
parallel with 20 pf

NOISE
Less than ±4 mY peak-to-peak RTO

±3 sigma confidence level

CROSSTALK

78 db (32 channels, 180 Hz)

RESOLUTION

One part in 4096 full-scale

1-13

CHAPTER 2
DETAILED THEORY OF OPERATION

2.1

MODES OF OPERATION

The AD15 has two basic modes of operation: program control and data channel. All transfers made in
program control mode occur through the PDP-15 accumulator, whi Ie all transfers made using the data
channel are made directly to memory.

2. 1 . 1

Program Control

In program control mode, each analog input to be converted and stored requires a new set of instructions . Consequently, this method is not advantageous in the case of many conversions.

2.1.2

PDP-15 Data Channel

Two types of operation are possible using the PDP-15 data channel facility: sequential or random. In
sequential operation, only one set of instructions is required to convert successive analog channels and
store the results in sequential memory locations. To accomplish this, the programmer must load two
memory locations (26 and 27) in the PDP-15.

Location 26 is loaded in 2 1s complement notation with

the desired number of words to be converted (word count). Location 27 is loaded with the starting address minus one, where the first converted analog input is stored (current address). After each analog
input is converted, the word count is incremented. The incremented word count, in turn, causes the
current address to be incremented. This ensures that the next analog input to be converted wi II be
stored in the next sequential memory location. When the desired number of conversions have been
completed, a word count overflow flag is raised, because sensing aliOs in word count location 26
causes I/O OFLO to be generated and supplied to the AD15. I/O OFLO causes the word count flag
to be raised. This flag causes an interrupt, indicating completion of the required number of conversions.

Bit 10 of the input status word must be a logic 1 for sequential operation.
NOTE
When employing sequential operation, only one status
word is employed, and the data words are converted one
after the other automati cally. Therefore, it is necessary
to use the same fixed-gain for all channels in this mode.

2-1

Random operation is similar to sequential operation except that a separate status word (channel address,
gain, etc.) is associated with each analog channel. The status words are retrieved from one memory
table and the converted data words are stored in a second memory table. Memory locations 24 and 25
are reserved for the status words, and memory locations 26 and 27 are reserved for the data words.
Location 24 is loaded with one less than the 2 1s complement of the number of words to be converted,
and location 25 is loaded with the starting address minus one where the first status word is stored. Location 26 is loaded with the 2 1s complement of the word count value; location 27 is loaded with the
memory location minus one where the first converted data word is to be stored. Although random channels may be converted in this manner, note that the status words are sequentially stored in memory, and
the data words are also stored in successive memory locations. In this way, the word count and current
address cycles of the three-cycle data channel facility are utilized (refer to the PDP-15 Maintenance
Manual for a more detailed description of the three-cycle data channel).

Bit 10 of the input status

word must be a logic 0 for random operation.
NOTE
In sequential operation, one three-cycle data break
is required for each data word to be transferred into
PDP-15 memory. In random operation, however, two
three-cycle data breaks are required for each data
word. The first three-cycle break transfers the status
word to the AD15, and the second three-cycle break
transfers the converted data word to PDP-15 memory.
When word count overflow occurs, it is a result of
location 26 overflowing indicating that all data words
have been transferred.

2. 1 .3

Add -to-Memory

The add-to-memory feature of the PDP-15 computer allows an analog input (after it is converted to
digital) to be added to the contents ofa memory location. If the value added to memory is sufficient
to cause a sign change in the result, a data overflow pulse is generated. If the programmer desires to
cause an interrupt when a change of sign occurs, it is necessary for him to set the add-to-memory bit
(bit 9) of the input status word to a logi c 1 and to also set bit 6 of the status word to a logi c 1. Bit 6,
when set, enables the memory flag to cause a program interrupt. The add-to-memory feature is discussed in greater detail in the PDP-15 Maintenance Manual.

2.2

PROGRAM INTERRUPT

There are three sources of program interrupts: A/D DON E, data overflow (DATA OFLO), or word
count overflow (We OFLO). A/D DONE causes an interrupt under program control operation, data
overflow causes an interrupt during add-to-memory, if enab led, and word count overflow causes an

2-2

interrupt during the data channel mode. When the desired number of conversions have been
accomplished, the PDP-15 senses word count overflow (all Os in location 26) and issues an OFLO signal that raises the word count flag in the AD15. This flag raises the API flag, which is fed to the
Ml04 API Multiplexer Control Module. An output, designated API, is supplied to the PDP-15 via two
I/O bus drivers. One bus driver yields PROG INT RQ and the other yields API 0 RQ, If the PDP-15
does not have the API option installed, only the PROG INT RQ is recognized, The main program
traps to location 000000 as a result of the program interrupt, and the current contents of certain
8
PDP-15 registers is stored in this location. The instruction in location 0000018 is fetched and executed. This instruction is an entry to a skip chain that determines the peripheral device causing the
interrupt. When this is ascertained, the program enters a service routine to service the device. On
completion of servicing, control is returned to the main program.

2.3

AUTOMATIC PRIORITY INTERRUPT

If the AD15 is connected to the Automatic Priority Interrupt (API) System, it is assigned the trap address of 57 , Conversions are done on a cycle stealing basis, similar to that described in the program
8
interrupt section (see Paragraph 2.2). When the required number of conversions have been accomplished, the PDP-15 senses word count overflow in location 26 and generates an OFLO signal, causing
the word count flag to be raised in the AD15. This signal causes the API flag to be raised which, in
turn, causes API to be generated at the output of the Ml04 API Multiplexer Control Module. This
signal is applied to two bus drivers to yield PROG INT RQ and API 0 RQ. With the API option installed and enabled in the PDP-15, the API 0 RQ overrides PROG INT RQ and the main program in the
PDP-15 traps to location 57 (AD15 trap address). Location 57 contains a JMS to a service routine.
The first location of the service routine stores the contents of certain PDP-15 registers. Each device
associated with API has its own unique trap address; thus, it is not necessary to enter a skip chain to
determine the device that caused the interrupt. A small skip chain is necessary to determine the internal source (AjD DONE, we OFLO or MEM OFLO) of the interrupt. On completion of the servicing, a JMP * instruction returns control to the main program.

2.4

LATENCY

If there are many devices of higher priority than the AD15 operating on the data channel, the programmer should be concerned with I/O Latency Time. The I/O Latency Time must be considered because a
data word that has been converted to digital is available in the AD15 buffer register for a maximum of
approximately 40 fJS. If this data word is not transferred to the PDP-15 memory within this time, the
initial data word is lost as a result of the next data word being strobed into the buffer register.

2-3

2.5

DETAILED BLOCK DIAGRAM DESCRIPTION

The following paragraphs describe the AD15 power supplies, modes and types of AD15 operation, and
a detai led block diagram description.

2.5. 1

Power Supplies

The AD15 operates at 110V, 60 cycle input, and includes an analog power supply (designated H728)
operating with input power of 110V at 60 cycles. The power supply provides outputs of +15V and -20V
for the A877 Analog-to-Digital Converter, the A405 Sample and Hold Amplifier, the A222 GainSwitching Amplifier, and the A 124 Multiplexer Modules. In addition to the H728 Power Supply, the
H721 Power Supply, housed in the H963-P Analog Equipment Cabinet, provides +5 Vdc for all the
digital modules.

2.5.2

Sync Logic

In either program control or data channel mode, a convert pulse is generated (see Figure 2-1). This
pulse is coupled with a sync enable signal to generate internal sync. Internal sync initiates the timing
for the analog-to-digital conversion. This timing can also be initiated externally by an external sync
signal that serves as the convert pulse. With internal or external sync, a delay of 3.0 I-IS is timed out
before allowing the analog-to-digital conversion to take place. This delay provides sufficient time for
amplifier settling and for stabilizing of circuit elements. At the end of the delay, a start pulse is developed and applied to the analog-to-digital converter.

2.5.3

Analog Multiplexing

The computer-specified 7-bit address of the analog input to be converted is loaded in the AD15 channel address register via I/O bus lines 11 through 17. The 7-bit address is then converted to octal format
as shown in Figure 2-2. The octal addresses range from 000 to 177 in the maximum system configuration.
The channel address is then supplied to a 32-channel multiplexer (minimum system configuration) along
with the external analog inputs. The multiplexer logic selects the analog input specified by the channel address. The selected analog input is then multiplexed onto a common output line.

2.5.4

Gain Selection

The selected analog signal, after being multiplexed, is supplied to a single-ended gain switching amplifier with selectable gain of 1, 2, 4 or 8. The gain is selected on the basis of the voltage range of
the analog inputs. For voltages in the range of 10V, unity gain is selected, whereas voltages in the
range of 1. 25V require a gain of 8 for full-scale deflection.
2-4

DATA STROBE

PROGRAM CONTROL

OPERATING {
MODE
SELECTIONS
+IIDV
60"',50'"

+ll0V 60'"
(220V,SO""

r---

I/O BUS
LINES 11-17

L---'"
~~

Ie-

r--I--

RANDOM

+ 15V

ANALOG I DIGITAL
CONVERT AND
DATA STROBE
GENERATOR
ADI5-0-06

CONVERT

PROGRAM
POWER
SUPPLY
H721

SYNC ENABLE SIGNALS

EXT SYNC (CONVERT)

POWER
SUPPLY
H721

f----

---DIGITAL

BUS
DRIVERS
ADI5-0-09

PI REQ

API REQ

BINARY
CHANNEL ADDR

J
I

OCTAL

BINARY I OCTAL
DECODER
AD1S-0 -OB

I CHANNEL ADDR
I

BINARY CHANNEL ADDRESS (CAOO-CA06)

PROGRAM
INTERRUPT
lOGIC
ADI5 -0-06

MULTIPLEXER
CONTROL
ADI5-0-06

I----

DATA
CHANNEL
MULTIPLEXER
CONTROL
ADI5-0-06

I--

- -API
---

1-----

~
BUS
RECVR'S
ADI5-0-10

GAIN SWITCHING
lOGIC ADI5-0-07

EXTERNAL ANALOG INPUTS

DCH REQ

MUlTPLEXER
CHANNEL
ADDRESS
REGISTER
AD15-0 -04

SAMPLE SHOlD,
MULTIPLEXER,
AND SWITCH
GAIN AMP.
DELAY
AD15-0 -07

EXTERNAll
iNTERNAL SYNC
ADI5-D-07

START

ANALOG
TO
DIGITAL
CONVERTER
(FIRST
BUFFER)
ADI5-0-07

+5V

~ GAIN SWITCH ING INPUTS
BUS
RECVR'S
ADI5-0-10

PDP - 15
PROCESSOR

SEQUENTIAL

36 CHANNEL
MULTIPLEXER
(EXPAN.DABlE TO
128 CHANNELS)
ADI5-0-08

lSINGLE-ENDED
AMPLIFIER
ADI5 -0-07

DIGITAL DATA
BFB OO·BFB 12

DIGITAL DATA
(BITS 00-12)

SAMPLE AND
HOLD CIRCUIT
AD1S-0-07

SECOND
BUFFER
STAGES
ADI5-0-03

AID DONE

(RESET SAMPLE S HOLD)

BUS
DRIVERS
AD15 -0-09

DIGITAL DATA TO
PDP-15 VIA 1/0 BUS

FLAG AND
CONTROL
SIGNALS

WC FLAG
MEM FLAG

DEVICE SELECT
DSOO-05

ADRS (READ STATUS INTO AC)

ADRS
ADCF

SUBDEVICE
SELECT 500,501

L..

ADRB

WC FLAG
MEM FLAG

rOT
DECODER
ADI5 -0-05
ADI5-0-06

ADCV
lOT'S
ADSF

lOTI ,lOT 2 ,lOT 4
WCSF

NOTE:
Numbers in blocks refer to AD1,; block schematics.

MSSF
'~-042B

Figure 2-1 AD15 Analog Subsystem
Functional Block Diagram

2-5

ANA LOG CHANNEL
ADDRESS

THRU 7
LEAST
MOST
SIGNIFICANT
SIGNIFICANT
OCTAL DIGIT
OCTAL DIGIT
THRU 7

0.1
15-0427

Figure 2-2

2.5.5

Analog Addressing

Sample and Hold Amplifier

From the gain-switching amplifier, the amplified analog signal is supplied to a sample and hold amplifier that stores rapidly fluctuating analog signals to allow sufficient time for analog-to-digital conversion. The input is continually tracked in the sample mode and is stored in the hold mode for the length
of time needed to convert the signal from analog to digital. This time is approximately 35 I-'s. The
sample and hold amplifier is common to all analog channels and can sample any desired input.

2.5.6

Analog-to-Digital Conversion

The analog-to-digital converter provides a 12-bit digital equivalent of the analog input with a 13th
sign bit used to distinguish between positive and negative voltages. After conversion, the digital word
is supplied to a series of bus drivers. On coincidence of the digital word and a data strobe, the data
is strobed onto the I/O bus and transferred into the PDP-15 computer.

2.5.7

Flag Status and lOT Decoding

The PDP-15 computer can monitor the analog channel address and the status of word count overflow
and memory overflow flags by issuing an ADRS instruction, one of the seven lOT instructions used in
the AD15. This instruction is normally used for diagnostic purposes. The lOT instructions are decoded
from the I/O bus device and subdevice select lines, the lOP pulses, and word count and memory flag
status.

2.6

DETAILED LOGIC ANALYSIS

The following paragraphs provide additional detailed descriptions concerning the applicable logic
schematics. These paragraphs, with the system description, functional description, and signal glossary,
provide the user with adequate knowledge of system orientation and detailed theory of operation.

2-7

2.6.1

Status Register and Buffered Data Register

The upper half of block schematic AD15-0-03 represents the 13-bit buffer register (12 bits plus sign bit)
that receives the 13-bit digital data from the output of the analog-to-digital converter (see block
schematic AD15-0-07). This second stage of buffering stores the converted data word while waiting
for the PDP-15 to accept it and allows a second conversion to be started without destroying the contents of the first conversion. The buffer register is strobed by A/D DONE at the end of each conversion. If a memory overflow flag is raised (add-to-memory), the buffer register cannot be loaded because
MEM FLAG (1) H inhibits A/D DONE from strobing the register. This allows the programmer the capabi I ity of preserving the contents of the buffer register.

By preserving the contents of the buffer register,

the original value in memory before add-to-memory can be reconstructed. For example, assume the
memory location contained the value X and the value Y was added to it, resulting in the sum of Z with
a sign change. When overflow occurred, the original value (X) in memory is lost but by preserving Y
in the buffer register and knowing the value of Z it is possible to reconstruct the value X.
The lower portion of block schematic AD15-0-03 shows the various control flip-flops that are set or
reset by the control bits of the input status word. The fl ip-flops include sequential/random, add-tomemory, external/intemal sync, data channel/program control, memory enable/disable, and the two
gain switching flip-flops (GS01 and GS02). The control flip-flops are strobed by SELECT CLOCK,
which is generated during data channel, when no word count overflow occurs or when an ADCV lOT
instruction is issued under program control.

2.6.2

Multiplexer Channel Address Register

Block schemati c AD 15-0-04 shows the seven-stage channel address register employed. The register is
preset with the starting address and is incremented on completion of each conversion in sequentia I
mode. Note that the register uses jam transfer. Either the true (set) or complement (reset) version of
each address bit is present at the input to the register. Consequently, the input address can be properly loaded into the register regardless of the previous contents.
NOTE
The input bits are inverted on the I/O bus and inverted
a second time through the channel address register, restoring the bits to their original value.

The SEQ input to the register enables the register during sequential operation, and the COUNT signal
causes the register to increment after each conversion. The COUNT signal is generated on block
schematic AD15-0-05 as a result of A/D DONE, the DCH/PRG CTRL flip-flop in DCH mode, and

we FLAG (1) H.

2-8

The input address to the channel address register is strobed by SELECT CLOCK, which occurs as a
result of an ADCV instruction or a LOAD signal. LOAD occurs during direct memory access if no
word count flag is present and if IOP4 (PDP-15 to AD15 transfer) is present. During add-to-memory,
it is necessary to inhibit IOP4 from affecting certain logic in the AD15. This is accomplished when
both write (WR) and read (RD) signals are present; these signals occur only during add-to-memory.

2.6.3

Flag Logic

Block schemati c AD 15-0-05 shows the logi c necessary to implement the following flags:
a.

Word count flag

API flag

Memory flag

DCH flag

Done flag

In addition, the block schematic contains the read and write logic necessary to implement transfers to
and from the PDP-15.

2.6.3.1

Word Count Flag - The word count flag is employed during sequential and random operation.

In sequential mode, a word count location in PDP-15 memory (location 26) is preset with the 2's complement of the number of data words to be transferred. This location is incremented each time a word
is converted to digital. In random mode, memory location 24 is also preset with the 2's complement
of the number of data words to be transferred. In addition, however, memory location 24 is preset with
one less than the 2's complement of the number of data words to be transferred. Each time a data word
is transferred, location 26 is incremented; each time a status word is transferred to the AD15, location
24 is incremented. When location 26 increments from all 7s to aliOs, an overflow signal is generated
indi cating that the desired number of words have been converted. In addition to the overflow signal,
a data channel enable signal (DCH ENB) is required to raise the word count flag indicated by WORD
COUNT FLAG (0) H. The flag flip-flop can be reset by a power clear or ADCF lOT instruction, which
clears all flags. The word count flag, when raised, is supplied to the PDP-15 and to the lOT decoding
logic to enable a program skip, when executed. It is also supplied as an inhibit to the API, DCH,
and select clock logic.
NOTE
The word count flip-flop is delayed by 2 ~s due to the
delay multivibrators shown on block schematic AD15-0-04
(see DEL OFLO). The flip-flop is delayed by 2 ~s to
enable IOP2 to allow the last data word in a series of
conversions to be transferred.

2-9

2.6.3.2

API Flag - The API flag is designed to cause an API interrupt if the API option is installed in

the PDP-15. When the interrupt occurs, the program traps to location 57 , This location normally
8
contains a jump-to-subroutine (JMS), which stores the contents of the PDP-15 program counter in the
first address of the subroutine. The next instruction is the start of the AD15 service routine. On completion of the routine, a JMP * (jump indirect) returns control to the main program at the point where
the interrupt occurred. The API flag can be raised under any of the following three conditions:
a.

Word count overflow indicated by WORD COUNT FLAG (1) L.

Under program controlled transfers, when a data word has been converted
(A/D DONE), and

Under add-to-memory operation, when overflow occurs (MEM FLAG (0) H).

The API flag, when raised, is indicated as API FLAG (0) H and can be cleared by power clear, ADCF,
or clear API flag signals. The API flag is supplied to the M 104 API Multiplexer Control Module to
initiate an API request (API RQ 00), which is suppl ied to the PDP-15 via the I/O bus.

2.6.3.3

Memory Flag - The memory flag is raised when data overflow occurs during add-to-memory

operati on on Iy.

Data overflow occurs when the contents of an existing memory location is added to a

data word in the PDP-15 adder and the sum results in a change of sign. To raise the memory flag, bit
6 (memory enable overflow) must be set, and bit 9 (add-to-memory) of the input status word must be
set. These bits set the memory enable and add-memory flip-flops, respectively (see block schemati c
AD 15-0-03). The add-memory flip-flop must be set to initiate a write request during add-to-memory
operation. The write request sent to the PDP-15 causes the contents of the specified memory location
to be strobed into the PDP-15 adder, where it is added with the converted data word. If overflow
(change of sign) occurs, a DATA OFLO signal is generated in the PDP-15 and transferred to the AD15.
This signal and the memory enable (MEM EN) signal, generated by bit 6 of the input status word, cause
the memory flag to be raised. The flag can be lowered by power clear or the ADCF lOT instruction.
The memory flag is supplied to the PDP-15 computer via the I/O bus and is also applied to the lOT decoding logic to enable a program skip if memory overflow occurs.

2.6.3.4

Read/'Nrite Logic - The read/write logic on block schematic AD15-0-05 is used to request

a read (transfer to memory) or write (transfer from memory) cycle from the PDP-15. A read request is
generated under any of the following condition:
a.

Issuance of ADRS or ADRB lOT instructions,

Operating in sequential mode, or

Operating in random mode for a read operation.

2-10

A write request is generated under any of the following conditions:
a.

In add-to-memory mode, under sequential operation or when doing a read operation.

In random mode, when doing a write operation.

The WRITE flip-flop (M216-E05) is wired with a toggle input and is enabled when in random mode.
When the flip-flop is in the write state (reset) a status word is transferred to the AD15. When the
flip-flop toggles to the read state (set) on the next DCH ENA pulse, a data word is t'ransferred to the
PDP-15.

2.6.3.5

DONE Flag - The DONE flag is raised by A/D DONE, which occurs at the end of a con-

version. It is used in conjunction with the skip logic on block schematic AD15-0-06. The flag can be
cleared by ADRB, ADCV, or ADCF lOT instructions or by the PWR CLR signal.

2.6.3.6

DCH Flag - The data channel (DCH) flag can be raised as a result of A/D DONE during data

channel activity, providing word count overflow has not occurred. This flag is raised to allow the data
word to be transferred to PDP-15 memory. A second method of raising the DCH flag occurs during data
channel random operation. In this operation, it is necessary to transfer the first status word to the
AD15 by means of the ADC instruction. Subsequent status word transfers occur as a result of IOP2 of
the preceding data word transfer. The DCH flag can be lowered by PWR CLR or CLEAR DCH FLAG
signals or by the ADCF lOT instruction. The DCH flag is first applied to the M104 Data Channel
Multiplexer Control Module and then to the PDP-15 via the I/O bus as DCH REQ to initiate a data
channel request to the PDP-15.

2.6.3.7

Flag Testing - The following flags generated in the AD15 can be tested by the programmer:
Flag

Raised by

Lowered by

WC Flag

I/O OFLO

ADCF or PWR CLR

API Flag

WC Flag or A/D DONE
(under program control) or
MEM Flag

PWR CLR or ADCF or
CLEAR API FLAG

MEM Flag

DATA OFLO
(MEM EN Bit must be set)

PWR CLR or ADCF

DONE Flag

A/D DONE

ADRB or ADCV or
PWR CLR or ADCF

2-11

2.6.4

Device Decoders, API and Data Channel Logic

Block schematic AD15-0-06 contains the logic used to decode the various lOT instructions. Three of
the lOTs (ADSF, WCSF, and MSSF) cause a SKIP signal to be generated. This signal is supplied to the
PDP-15 to cause a skip of the next sequential instruction in the main PDP-15 program.
NOTE
The lOT instructions associated with transferring status
to the AD15 are enabled by an lOT 04 signal (bit 15 of
status word), and the lOT instructions associated with
transferring data to the PDP-15 are enabled by the
lOT 02 signal (bit 16 of the status word).

A complete description of the M 104 API and data channel multiplexer control modules can be found in
the PDP-15 Interface Manual or the PDP-15 Module Manual.
The convert (CNVT) pulse is applied to the analog-to-digital converter when internal sync is employed.
The convert pulse logic, shown on block schematic AD15-0-06, permits the convert pulse to be generated under any of the conditions below:
a.

In sequential mode, the first convert pulse is generated as a result of SEQ (1) H
and DEL ADCV H. AI I other convert pulses in this mode are generated as a result of A/D DONE, the DCH fl ip-flop being set, absence of the word count flag,
and absence of the memory flag.

In random mode, the convert pulse is generated as a result of the LOAD signal
(see block schematic AD15-0-06).

In program control mode, DEL ADCV (delayed from ADCV by 1.0 j-Is) causes the
convert pulses to be generated.

A signal, designated DCH STROBE, is generated on AD15-0-06 and is used to raise the DCH flag (see
AD15-0-05) in random mode. This signal allows input status words to be transferred to the AD15.

2.6.5

Analog Subsection

Block schematic AD 15-0-07 contains the internal/external sync logic, gain switching logic, sample
and hold amplifier, and analog-to-digital converter. Either internal or external sync is required to
initiate the timing for the analog-to-digital conversion. If internal sync is used, the convert pulse,
internally generated on AD 15-0-06, initiates the timing. A delay of 4.5 j-IS is necessary, before the
conversion is started, to allow for amplifier, multiplexer switch, and sample and hold settling. Two
M302 Dual Delay Multivibrators provide this function. If external sync is employed, the conversion is
not started unti I an external sync pulse is received (see Figure 2-3).

2-12

ADCV ____~fl~

________________________________--------

EXTSYNC __________

~fl~------~----~fl~--------~------I

14--40,l.lsec·-1

AID DONE

1 - 40 ,ll.seC·--+

n i

fl~_______
15-0426

Figure 2-3

2.!--.5.1

External Sync Timing Diagram

Gain Switching - Gain switching is accomplished by the A 124 Multiplexer, which selects

r)ne of four possible gains (l, 2, 4 or 8) for the A222 Operational Amplifier. The gain switching bits
(GSOO and GS01 of the input status word) specify the selected gain, as shown.
Gain

GSOO

GS01

1
2
4
8

0
0
1
1

0
1
0
1

NOTE
When an interrupt is issued, the EXT SYNC/INT SYNC
fl ip-flop is forced to I NT SYNC to prevent undesired conversions from occurring without the programmer's knowledge.
External sync pulses wi II cause conversions as long as the
EXT/INT SYNC flip-flop is on EXT SYNC. Therefore, it
is necessary to have this fl ip-flop on I NT SYNC for the
last conversion. This is accompl ished by the EXT ,lINT
SET L signal generated on drawing AD15-0-05.

2.6.5.2

Sample and Hold Amplifier - The amplified analog signal is then applied to sample and hold

amplifier A405, which samples and stores the input at 25 kHz, minimum. The sample and hold amplifier provides the capability of sampling and storing extremely rapid analog fluctuations, which could
not otherwise be accurate Iy measured.

2.6.5.3

Analog-to-Digital Converter - The output from the sample and hold amplifier is applied to

the A877 Analog-to-Digital Converter, where the analog signal is converted to a 13-bit digital word
(12 bits plus sign bit). Conversion time is approximately 35 jJS, and at the completion of this period,
an AID DONE signal is generated indicating the conversion is complete. In sequential mode, while
the first conversion is waiting to be transferred to the PDP-15 memory, the second analog signal is
being converted as a result of AID DONE, which enables the next convert pulse to initiate a

2-13

conversion. After the conversion, which takes approximately 35 ~s, AID DONE is issued which, in
turn, enables another convert pulse to be issued. The timing relationships for this interaction are shown
on Figure 2-4.

--'n ---i n-- - j n--- i

DATA TRANSFER _ _ _ _ _ _ _

FIRST
~
CONVERSION
BEING
TRANSFERRED

--I

SECOND
CONVERSION
BEING
TRANSFERRED

I--

--I cOJ:i:~ION IBEING
TRANSFERRED

15-0424

Figure 2-4

Sequential Mode Timing Relationships

In random or program controlled mode, a new status word must be loaded prior to another conversion.
The timing relationships for this mode of operation are shown in Figure 2-5. The AID DONE signal,
in addition to being supplied to the circuits previously described, is also applied to the sample and
hold amplifier as a reset to allow new analog inputs to be sampled and stored.

2.6.6

Binary-Octal Decoder and Analog Multiplexer

Block schematic AD15-0-08 shows the binary-to-octal decoder and a 32-channel multiplexer designated
A124. This logic is necessary for a 32-channel system. For each additional 32 channels added to the
system, an additional multiplexer is required; thus, 128 channels {maximum system configuration} requires four multiplexers. The multiplexers are specified by bits 0 and 1 of the analog channel address,
as follows.

2-14

0-31 channels
32-63 channels
64-95 channels
96-127 channels

ADCV

CAOO=O, CA01=0
CAOO=O, CAO 1= 1
CAOO= 1, CAO 1=0
CAOO= 1, CA01= 1

~________________________________________________

CNVT __

___

__________

____

______________

A/DDONE __-+__~__________~

DCH FLAG

IOP2-DCH ENB
( REA D DATA F ROM AD 15) ____

-+-+-__________---'

lOP 4 -DCH ENB (W RITE
STATUS WORD INTO AD15) _ _ _.....

WORDCOUNTFLAG __________________________________________

NOTE
S = STATUS
D = DATA
10- 0420

Figure 2-5

Random Mode Timing Relationships

Bits 2 through 6 of the analog channel address specify one of 32 channels within the multiplexer
designated by CAOO and CA01. For example, in the minimum 0- to 32-channel system, channel 19 is
addressed when bits 2, 5, and 6 are logic ls, and bits 3 and 4 are logic Os.
NOTE
The channel numbers shown by 32, with each new
AM01-A multiplexer added.

2.6.7

I/O Bus Drivers

Block schematic AD15-0-09 (sheets 1 and 2) contain the I/O bus drivers that provide the drive necessary
to transmit si gna Is down the I/O bus to the PDP-15 computer. The contents of the 13-stage buffer
register is strobed on the I/O bus when DATA STROBE occurs, whi Ie the analog channel address is
strobed on the I/O bus when the ADRS lOT instruction is issued. The ADRS also enables the PDP-15
to monitor the status of the word count and memory flags.

2-15

Sheet 2 of block schematic AD15-0-09 contains the drivers for the API Trap address, the word count
addresses (status and data words), and the various request signals. The API Trap address causes lines
12 and 14 through 17 to go low, and 13 to remain high. This represents the complement of the trap
address, which is inverted by the I/O bus receivers in the PDP-15 to yield the true address.

The data word count address (26) is enabled by a READ signal indicating a request to transfer information
to the PDP-15. The information in this case is the data word count address. I/O address lines 13, 15,
and 16 are driven low and 12, 14, and 17 remain high, representing the complement of the word count
address of 26. This complement is again inverted in the I/O bus receivers to yield the true version of
the address. The status word count address (24) is enabled during a write operation if the AD15 is in
random mode. I/O address lines 13 and 15 are driven low and 12, 14, 16, and 17 remain high, representing the complement of the word count address of 24. The complement is inverted by the I/O bus
receivers to yield the true version of the address.

2.6.8

Bus Receivers, Analog Inputs, and I/O Bus Interface

Block schematic AD 15-0-10 shows the I/O bus receivers that receive signals from the PDP-15 I/O bus
drivers. Both the true and complement versions of the signals are available at the receiver outputs.
Block schematic AD15-0-11 shows the connections from the external analog inputs to the AD15 subsystem. A more detailed description of these connections can be found in the physical description in
Chapter 1 of this manual.
Block schematic AD15-0-12 shows the I/O bus interface containing all the signals between the PDP-15
computer and the AD15 subsystem. Some of the signals shown are not used with the AD15. Figure 1-1
of this manual depicts the signals that are used and do interface between the PDP-15 and the AD15.

2.6.9

Expansion Un it AM01

Each AMOl (a maximum of three) provides the AD 15 with 32 additional channels for increasing the
system configuration.

Block schemati cs AM01-A-03 through AM01-A-05 show the AMOl circuitry.

Block schemati c AM01-A-03 shows the M908 Card that provides connections for 32 additional channels. Thus, each AM01 contains a M908 Connector to interface the PDP-15 to the external analog
sources.

Block schemati c AM01-A-04 contains an A 124 Mu Itiplexer that provides multiplexer capa-

bility for an additional 32 channels. Block schematic AM01-A-05 shows the M935 Bus Extender Card,
which is provided to jumper the operating voltages and the appropriate channel address bits to the
AM01. The right-hand section of the drawing shows the M510 I/O Bus Receivers used to increase the
fan-out capability for channel address bits CA05 and CA06.

2-16

CHAPTER 3
lOT INSTRUCTION FORMAT

3.1

EQUIPMENT TURN-ON/fURN-OFF PROCEDURES

There are no special turn-on or turn-off procedures associated with the AD15 subsystem. The normal
PDP-15 turn-on procedure is all that is required to initiate AD15 operation.

3.2

INSTRUCTION AND DATA FORMATS

The AD 15 Analog Subsystem uses a total of seven lOT instructions for system operation. These instructions provide transfer of status information and data between the PDP-15 computer and the AD 15 subsystem. The lOTs also provide clearing of flags and force program skips when certain flags are raised.
The lOTs are described in the following paragraphs and are followed by a description of the input
status word (from the PDP-15 to the AD15), output status word (from the AD15 to the PDP-15), and the
converted data word (from the AD 15 to the PDP-15).

3.2.1

lOT TIMING

For a description of lOT Timing, refer to the PDP-15 Maintenance Manual.

3.2.2

lOT INSTRUCTION FORMAT

The format for the lOT instruction is shown in Figure 3-1.

Bits

through 5 specify the lOT operation

code of 708; bits 6 through 11 are device select bits, and bits 12 and 13 are subdevice select bits. The
device select bits specify an octal code of 13 to uniquely address the AD15. These bits are also used
8
in con junction with the subdevi ce select bits to decode the various lOT instructions. Bit 14 is a mi croprogrammable bit that is used to c lear the PDP-15 accumulator.

Bits 15, 16, and 17 are the IOP4,

IOP2, and IOP1 pulses, respectively. These bits are also microprogrammable. IOP4 is employed in
the transfer of information from the PDP-15 to the AD 15. IOP2 is employed in the ~ransfer of information from the AD15 to the PDP-15. IOP1 is used for I/O skip instructions to test a device flag.
For transfers between the PDP-15 and the AD 15, the first 12 bits (operation code and devi ce select
code) are fixed (7013-- ).
8
transfer.

Bits 12 through 17 can be altered depending on the type and direction of

3-1

OPERATION
CODE (708)

lOP I (SKIP NEXT INSTRUCTION)

DEVI CE SELECT
CODE (138)

lOP 2 (TRANSFER TO PDP-15)
1...-_ _ _
L...-._ _ _ _

IOP4 (TRANSFER TO AD15)
CLEAR ACCUMULATOR
15-0436

Figure 3-1

3.2.2.1

lOT Instruction Format

ADCV (convert) Octal Code 701304 - This lOT instruction transfers the contents of the

PDP-15 accumulator (containing the input status word) to the AD 15 Analog Subsystem, clears the

AID DONE flag, and initiates timing for the analog-to-digital conversion.

3.2.2.2

ADRB (read data buffer) Octal Code 701302 - This lOT instruction transfers the converted

data from the AD15 data buffer to the PDP-15 accumulator and clears the A/D DONE flag.

3.2.2.3

ADRS (read status register) Octal Code 701342 - This lOT instruction transfer certain con-

tents of the AD15 status register to the PDP-15 accumulator (see Paragraph 3.2.3). The status register
contains selected gain data, analog channel address, and designated control functions, such as mode,
type of operation, sync selection, memory overflow, etc.

3.2.2.4

ADCF (clear all AD15 flags) Octal Code 701362 - This lOT instruction clears all AD15

flags. These flags include word count overflow, memory, A/D DONE and DCH flags.

3.2.2.5

ADSF (skip on AID DONE flag) Octal Code 701301 - This lOT instruction is a skip instruc-

tion that causes a program skip of the next sequential instruction if the AID DONE flag is raised.

3.2.3

Output Status Word Format

The output status word is a word in the AD15 containing information regarding analog channel selection,
and word count and memory sign overflow (see Figure 3-2). The AD15 status can be monitored by
transferring the output status word to the PDP-15 accumulator via an ADRS lOT instruction. Bits 0
through 3 of the output status word are not used. A logi c 1 in bit 4 indicates a word count overflow,
and a logic 1 in bit 5 indicates a memory sign overflow. Bits 6 through 10 are not used, and bits 11
through 17 represent the analog channel address.

3-2

MULTIPLEXER
CHANNEL ADDRESS

NOT USED

"I" INDICATES MEMORY SIGN OVERFLOW
"0" INDICATES NO MEMORY SIGN OVERFLOW

"I" INDICATES WORD COUNT OVERFLOW
"0" INDICATES

NO WORD COUNT OVERFLOW
15-0433

Figure 3-2

3.2.4

Output Status Word Format

Data Word Format

The format of the converted data word is shown in Figure 3-3. The converted word is a 12-bit, rightjustified, 2 1s complement, data word with extended sign bit {bits 0 through 5}. This data word represents the digital value of the analog word after conversion.

0 11

21 3 1415

61 7

EXTENDED SIGN BITS

Is I

91 '0

1121131141151161171

12-BIT DIGITAL DATA WORD
BIT 6 2 MSB
BITI7=LSB
15-0434

Figure 3-3

Data Word Format

3.2.4. 1 WCSF {skip on word count overflow flag} Octal Code 701341 - This lOT skip instruction
causes a program skip of the next sequential instruction, if the word count overflow flag is raised. The
raising of the word count overflow flag signifies that the desired number of words have been transferred.

3.2.4.2

MSSF {skip on memory overflow flag} Octal Code 701321 - This lOT skip instruction causes

a program skip of the next sequential instruction, if the memory overflow flag is raised. This flag is
raised during an add-to-memory operation where the value added to memory was of sufficient magnitude to cause a sign change.

3.2.5

Input Status Word

The input status word is the word that is initially loaded in the PDP-15 accumulator prior to the lOT
instruction. The lOT instruction causes the contents of the accumulator containing this word to be
transferred to the AD15 subsystem. The format of the input status word is shown in Figure 3-4. Bits 0
and 1 determine the gain selected. Bits 2 through 5 are not used. Bits 6 through 10 are control bits
and the function of each is defined in Figure 3-4. Bits 11 through 17 comprise the seven-bit analog
channel address which specifies one of 128 possible addresses.
3-3

I 1, I 2I 3 I 4 I 5 I I 7 I 81 1 1" 1,21,31,41,51,61,71
0

'--y----I'

I
BIT

o
o
o

BIT

ANALOG CHANNEL ADDRESS

NOT USED

GAIN

"1" INDICATES SEQUENTIAL OPERATION
"0" INDICATES RANDOM OPE RATION
"1" INDICATES ADD-TO-ME MORY MODE

GAIN

"0" INDICATES NORMAL MOD E

"I" INDICATES EXTERNAL SY NC

"0" INDICATES INTERNAL S YNC

"1" INDICATES DATA CHANN EL BREAK

"0" INDICATES PROGRAM C ONTROL
"I" INDICATES ENABLED ME MORY OVE R FLOW
"0" INDICATES DISABLED MEMORY OVERFLOW
15-0435

Figure 3-4

3.3

Input Status Word Format

PROGRAMMING EXAMPLES

The following paragraphs describe several programming examples that illustrate the capabilities of the
AD15 in the various modes and types of operation. These examples are described for illustrative purposes and are not intended to replace existing software.

3.3. 1

Program Control Mode

The following program is an example of a program controlled transfer, where channel 748 is to be converted from analog-to-digital, a gain of 4 is to be selected, and external sync is to be employed. The
results of the conversion are read into the accumulator.
000200/200210
000201/701304
000202/701301
000203/600202
000204/701312
000205/740040

LAC 210
ADCV
ADSF
JMP. -1
CLA! ADRB
HLT

000210/401074

INPUT STATUS WORD

The first instruction (LAC 210) loads the accumulator with the contents of location 210, which is the
input status word. The format of the input status word for this example (401074) is shown in Figure 3-5.
For those bits which are not used or are "don't cares", logic Os have been assumed. The results are the
same if logic 1s are assumed; the only difference is the octal value of the status word.
The computer has set up the status word specifying the various parameters for the conversion (see
Figure 3-5). The ADCV instruction then transfers the status word in the accumulator to the AD15,
clears the A/D DONE flag, and initiates timing for the conversion. The ADSF (skip on A/D flag) and

3-4

JMP. -1 instructions form a waiting loop that allows time for the conversion to be completed. On
completion of the conversion, the AID flag is raised and the ADSF instruction causes a program skip
of the JMP. -1 instruction. The CLAI ADRB instruction clears the accumulator and transfers the converted data word of channel 748 to the PDP-15 accumulator. The next sequential instruction (HlT)
halts the program. Thus, the analog signal in channel 748 has been converted to digital and transferred
to the PDP-15 accumulator.
o

o
5

7
11

4
14

GAIN=4

DON'TCARE
(ASSUMEO)

CHANNEL ADDRESS =748
DON'T CARE (ASSUME 0)
DON'T CARE (ASSUME 0)
' - - - - - EXTERNAL SYNC
' - - - - - - PROGRAM

CONTROL

~-------DON'T CARE (ASSUME 0)
15-0431

Figure 3-5

3.3.2

Example of Program Control Input Status Word

Data Channel Mode - Sequential Operation

The following program uses the sequential feature of the data channel mode of operation. The analog
inputs from 16 successive channels starting at location 378 are to be converted to digital data. The
8
converted data is to be stored in successive locations, starting at location 400. The following parameters
are to be selected:
Gain = 1
Add-to-memory feature
Enable memory sign overflow
I nterna I sync

Initially, it is necessary to preload the word count and current address locations (26, and 27, respectively). The word count location is loaded with 7777628 (2 1s complement of 16 ). The current address
8
location is loaded with one less than the starting address or 000377 , because the current address is
8
incremented before the first conversion takes place. Consequently, the first converted word is transferred to location 400, the second to location 401, etc.
Figure 3-6 shows the format of the status word associated with this example; this status word is initially
stored in location 000170.
The following sample program, starting at location 100, accomplishes the successive conversions previously stated.

3-5

000100/200170
000101/701304
000102/701341
000103/600102
000104/600350

LAC 170
ADCV
WCSF
JMP. -1
JMP 350

000170/006637

Input Status Word

The first instruction loads the status word stored in location 000170 (006637) into the accumulator.
The ADCV instruction transfers the status word to the AD15, clears the A/D DONE flag, and initiates
the timing for the conversion.
o

6
5

6
8

7
14

~~'----~--~

GAIN· 1

NOT USED

CHANNEL ADDRESS· 378
SEQUENTIAL OPERATION
ADD -TO - MEMORY
'------INTERNAL SYNC
L..--_ _ _ _

MULTICYCLE DATA BREAK

' - - - - - - - - - - ENABLED MEMORY OVERFLOW
15-0432

Figure 3-6

Example of Sequential Mode Status Word

The next two instructions (WCSF and JMP. -1) form a waiting loop for the conversion to be completed.
The PDP-15 can be programmed to execute normal program sequences during this time. At the conclusion of the conversion, the AD15 issues an AID DONE signal and requests a data channel break.
When the PDP-15 grants this request, the word count is incremented to 777763, the current address is
incremented to 400, and the converted data word is transferred to the PDP-15 and stored in location
400. While the AD15 is converting the next data word, the PDP-15 is free to operate normal program
sequences. After the data word is converted, another A/D DONE signal is generated and a second
data channel request is initiated. When the request is granted, word count is incremented to 777764,
current address is incremented to 401, and the data word is then transferred to memory location 401.
The process continues unti I the word count transitions change from all 7s to aliOs. The PDP-15 senses
this as word count overflow and generates an overflow signal. This signal is then sent to the AD 15 to
raise the word count flag. This flag causes a program interrupt, or automatic priority interrupt to occur
if these systems are enabled. The interrupt, when acknowledged, indi cates that the required number
of data words have been converted and stored in the PDP-15 memory. In the preceding example, when
the word count flag is raised, the WCSF instruction causes a program skip of the JMP. -1 instruction
and allows execution of the JMP 350 instructi on to occur.

3-6

3.3.3

Data Channel Mode - Random Operation

The following program illustrates random operation in the data channel mode. Convert the following
three channels using the control functions indicated:
a.

Channel 114 {octal} - gain of 1, add-to-memory mode, enabled memory overflow,
internal sync

Channel 002 (octal) - gain of 4, normal mode, disabled memory overflow, external
sync

Channel 021 (octal) - gain of 8, normal mode, disabled memory overflow, internal
sync.

The first status word is stored at location 600, and the first data word is to be stored at location 700.
The format of each of the status words is shown in Figure 3-7.
o
o

o
2

4
11

,
NOT USED

CHANNEL ADDRESS

ADD-TO-MEMORY
L - -_ _ _

INTERNAL SYNC

' - - - - - - - MULTICYCLE

DATA BREAK

' - - - - - - - - - ENABLED MEMORY OVERFLOW
CHANNEL 114 INPUT STATUS WORD

GAIN=4

3
8

2
14

NOT USED

' - - - - - - - - DISABLED MEMORY OVERFLOW
CHAN N EL 002 I N PUT STAT US WORD
6
0

II II

2
I

o 1

I o I 0 I 0

L---.;--"

GAIN = 8

NOT USED

~
.l1'

CHANNEL 'ADDRESS
RANDOM
NORMAL MODE
INTERNAL SYNC
MULTICYCLE DATA BREAK

' - - - - - - - - DISABLED
CHANNEL 021

MEMORY OVERFLOW

INPUT STATUS WORD
15-0429

Figure 3-7

Examples of Status Words - Random Operation
3-7

The status words and data words are stored as follows:
000600/006514
000601/403002
000602/602021

Status Words

000700;XXXXXX
000701;XXXXXX
000702;XXXXXX

Data Words

In addition to formatting the status words, word count and current address for both the status word table
and data word table must be pre loaded as shown below:
000024;777774
000025/000577
000026;777775
000027/000677

Word count (2's complement) status words plus one
Current address of first status word minus one
Word count (2's complement) data words
Current address of first data word minus one

The program, starting at location 100, is shown below:
000100;700042
000101/200600
0001 02;701304
000103;701341
000104/600103
0001 05;700002
000106/600350

ION
LAC 600
ADCV
WCSF
JMP. -1
IOF
JMP 350

The ION instruction turns the program interrupt facility on, so that interrupts can be acknowledged by
the PDP-15. The LAC 600 instruction loads the first status word (006514) into the accumulator.
NOTE
The LAC 600 instruction is a convenient means of establishing
DCH and RANDOM mode operating bits. The other information in the status word is ignored. The status word will be
retrieved during a data channel break, at which time the
whole word will be utilized.

The next instruction, ADCV, specifies the mode of operation to the AD15, clears the flags, and initiates the first DCH request. When the request is granted by the PDP-15, the DCH request causes the
word count and current address of the first status word to be incremented. LaC 24 is incremented to
777775, and LaC 25 is incremented to 000600. The first status word is then transferred to the AD15
from location 600, and the conversion on channel 114 is started. When the data is converted, the
AD 15 issues an AID DONE signal that causes a second DCH request. When the second request is
granted locations 26 and 27 are incremented to 777776 and 000700, respectively. The first data word
is then transferred to the PDP-15 and stored in memory location 700. The transfer of this data word

3-8

causes another DCH request to be raised and again, when granted, status word locations 24 and 25 are
incremented to 777776 and 000601, respectively. The second status word is now transferred to the
AD 15 from location 601, and the second conversion is started. When the data is converted the AD 15
again issues an AID DONE signal that raises another DCH request. When this request is granted the
data word locations (26 and 27) are incremented to 777777 and 000701, respectively. The second data
word is transferred to the PDP-15 and stored in location 701. The transfer of this data word causes
another DCH request to be raised; when granted, locations 24 and 25 are incremented to 777777 and
602, respectively. The third status word from location 602 is now sent to the AD15, and a conversion
on channel 21 is started. When the conversion is complete, the AD15 issues another AID DONE signal that raises another DCH request. Th is request, when granted, causes locations 26 and 27 to be
incremented to 000000 and 702, respectively. The third data word is now transferred to the PDP-15
and stored in LaC 702.
Because LaC 26 has incremented from all 1s to all Os, the PDP-15 senses word count overflow and generates an 1/0 OFLO signal that causes the AD15 logic to generate a program interrupt or automatic
priority interrupt. When word count overflow has been sensed, the process is complete and no further
DCH requests are raised.

3-9

CHAPTER 4
INSTALLATION AND ADJUSTMENTS

4.1

INSTALLATION PLANNING

The AD 15 is installed in the upper portion of the H963-P Analog Equipment Cabinet (see
D-AR-PDP15-0-2). The AD15 Wired Frame Assembly has the following dimensions:
Width
Depth
Height

19 in.
1.5 in.
17 in.

The associated H728 Analog Power Supply mounts on the left side of the cabinet.

4. 2

ENVIRONMENTAL REQUIREMENTS

The AD 15 and PDP-15 operate in identical environments; the operating environmental limitations are
listed in Chapter 1 of this manual.

4.3

INSTALLATION PROCEDURE

The following steps outline the recommended installation procedure for the AD15 Analog Subsystem:
Step

Procedure
Unpack the AD 15 from the shipping container and inspect the unit for
damage. Any damage claims should be made to the DEC district supervisor.
NOTE
DEC field service personnel should be available
for consultation on potential problems.

4-1

Step

Procedure

Remove the tape holding the modules and cables in place and verify that
the modules and connectors are seated in the proper connector slots (refer
to Drawing D-AD-7007029-0-0).
NOTE
If this is the first AD15 purchased by user, j.t
wi II be shipped in the Analog Equipment cabinet.

Mount the AD 15 Wired Frame Assembly in the assigned location (H963-P
Analog Equipment Cabinet), using the appropriate hardware.

Install the analog power supply and chassis subassembly in the assigned
location (refer to Drawing E-UA-AD15-0-0).

Connect the H728 Analog Power Supply cable from the power supply to
AD15 subsystem.

Determine where I/O bus is terminated; remove four M909 Terminator
Cards and install the BC09B I/O Bus Cable between this point and the
AD15. If the AD15 is the last device on the bus, install the M909
Terminator Cards in the AD15.

Perform the acceptance checkout of the AD15 logic and analog circuits
using the MAIN DEC 15-D6GA-D(D) Diagnostic Program and Acceptance
and Calibration Procedure A-SP-AD15-0-15.

Perform calibration procedure in accordance with A-SP-AD15-0-15.
NOTE
When the acceptance test and calibration procedure has been successfully performed, the system
is considered operational, and the user can connect his inputs to the system.

If user is not planning to use external sync, the external sync pin connection
(refer to logic diagram AD 15-0-07) should be grounded.
NOTE
Be certain to disconnect from ground the external
sync connection, if it is desired to use external
sync at some future date.

If the user's system is greater than the 32-channel configuration, involving
the addition of one or more AM01-A system units, jumper wires must be
connected for the various AM01-A units (see Figure 4-1).

If the AD15 subsystem is larger than the basic 32-channel configuration,
install the M935 Bus Connector Cards in slots Aland A4 of appropriate
AM01-A system unit expansion (refer to Drawing D-AD-7007029-0-0).

4-2

JUMPERS FOR
CHANNELS 64-95

JUMPERS FOR
CHAN NELS 32 - 63

SECOND AM01-A EXPANSION UNIT

FIRST AMOI-A EXPANSION UNIT
JUMPERS FOR
CHANNELS 96-127

THIRD AMOI-A EXPANSION UNIT
15 -0423

Figure 4-1

4.4

Jumper Connections for G729 Card

ADJUSTMENTS

AD15 adjustment should never be undertaken until it is confirmed that a failure is due to circuit aging
or misalignment, rather than component failure.

Replacement of certain components or correction of

an unsatisfactory environment may el iminate the need for adjustment.

If adjustments are necessary, Table 4-1 lists the items that are adjustable, their adjustments, and their
location.

Table 4-1
Adjustments

Adjustment

Location

Item

Nomenclature

H728 Analog Power Supply

+15 Vdc, -20 Vdc

Left side of
analog cabinet

A708 Voltage Regulator Card

+5 Vdc regulated

All, B11

M302 Dual Delay Multivibrator
(DEL ADCV) (AD 15-0-06)

Both potenti ometers ad justed
for 500 ns

F08

4-3

Table 4-1 (Cont)
Adjustments

Location

Item

Nomenclature

Adjustment

M302 Dual Delay Multivibrator
(DEL OFLO) (AD15-0-04)

Upper potentiometer adjusted
for 1. 5 JJS
Lower potentiometer adjusted
for 500 ns

A08

Upper potentiometer adjusted
for 4.5 JJS
Lower potentiometer adjusted
for 500 ns

A09

M302 Dual Delay Multivibrator
(CONVERT) (AD15-0-07)

4-4

A08

A09

CHAPTER 5
MAINTENANCE

When operated under normal conditions, the AD15 Analog Subsystem requires little maintenance
(periodic performance of diagnostic programs, cleaning, and inspection). If preventive maintenance
is required, follow the procedures outlined in this Chapter to return the equipment to optimum operating
efficiency.
If a module requires replacement, refer to the spare parts list outlined in this Chapter. Do not replace

a faulty component without first determining the cause of the failure. Refer to the block schematics
associated with each module to determine the location of the components in question.

5. 1 AD 15 MAINDEC-15-D6GA-D(O) DIAGNOSTIC PROGRAM
The AD15 diagnostic program is used to test the unique hardware features of the system that cannot be
tested with existing MAINDECs. The program is designed to facilitate troubleshooting by selectively
exercising circuits in the AD 15. Instructions and procedures for loading, operating, and interpreting
the results of diagnostic tests are written in clear, concise language for beginning maintenance personnel.
The program tests are divided into the following six separate tests:
a.

logic Test - This test consists of 60 subtests that completely check out the AD15
logic. Each test is looped 2048 times for reliability.

Noise Test - In this test, a count spread of approximately the average of ± 1-4
is requested. A total of 1024 conversions are taken on all available AID channels at a gain of 8. Any channel with a count spread greater than that requested
is considered in error.

Gain Test - This test is used to determine the accuracy of the AD 15 at different
gain settings. Eight positive and eight negative voltages are applied to channel
o. A total of 1024 conversions are taken for every voltage and gain setting, and
the average is compared against the true value for that specific setting. If the
average is more than ± two counts from the true value, it is considered in error.

5-1

5.2

Calibration Test - This test is designed to accept a channel and gain input from
the Teletype and to take continuous conversions, displaying the conversion results in the accumulator.

Was-Is Test - This test is used to determine the long-term stabi lity of the AD 15.
The test requests a channel and gain input via the Teletype and prints out the
conversion result. Then, continuous conversions are taken, and when the conversion value changes more than ± one count from the previous conversion value,
the value is printed out.

Recovery Test - This test is used to determine the settling times of the system.
With this test, both channel and gain can be changed simultaneously. A
channel and gain is first selected, with eight conversions being taken followed
by selection of a second channel and second gain with eight additional conversions.

PREVENTIVE MAINTENANCE

A systematic preventive maintenance program is a useful tool for averting system failures. Proper application of a preventi ve maintenance program is an aid to both servi ceman and user, because detection
and prevention of probable fai lures can substantially reduce maintenance and downtime.
Scheduling of computer usage should always include time for maintenance. Careful diagnostic testing
can indicate problems that may only occur intermittently during on-line operation.
Weekly program checks and thorough preventive maintenance should be followed, based on the following criteria:
electrical - 1000 hours
mechanical - 500 hours

or at least quarterly.

5.2.1

Preventive Maintenance Tasks

The following tasks should be performed quarterly:
Procedure
Clean the exterior and interior of the equipment cabinet using a vacuum
cleaner, air blower, or a brush with long soft bristles, and/or cloths
moistened in nonflammable solvent. If an air hose is used for cleaning,
do not disturb components or wiring.
2

Lubricate hinges, slide mechanisms, and casters, with a light machine
oil. Wipe off excess oil.

Visually inspect equipment for general condition. Repaint any scratched
area with DEC black paint or Krylon glossy white No. 1501.

5-2

Procedure
Inspect all wiring and cables for cuts, breaks, fraying, wear, deterioration,
kinks, strains, and mechanical security. Tape, solder, or replace any defective wiring or cable covering.

5.3

Inspect the following for mechani cal security: keys, switches, control
knobs, lamps, connectors, transformers, fans, capacitors, etc. Tighten
or replace as required.

Inspect all module mounting panels to ensure that each module is securely
seated in its connector. Remove and clean any module that may have
collected dirt or dust due to improper air filter service.

Inspect power supply components for leaky capacitors, overheated resistors,
etc. Replace any defective components.

Check the output voltages (+ 15V and -20V) and ripple content of the H728
Analog Power Supply as specified in Engineering Specification
A-SP-AD 15-0-14. Use a multimeter to make these measurements without
disconnecting the load. Use an oscilloscope to measure p-p ripple on all
dc outputs of the supply. The outputs of the supplies are adjustable; therefore, if any output voltages are not within the specified tolerance, readjust
the output voltages. If the desired output voltages are not attainable, initiate power supply maintenance. Refer to the block schematic associated
with the power supply in question. If ripple content is not within specifications, the power supply is considered defective, and corrective maintenance should be performed.

Run AD15 programs to verify proper equipment operation.

Enter preventive maintenance results in a log book.

While running the diagnostics, vibrate the modules and wiring panels.

While running the diagnostics, check all analog adjustments.

CORRECTIVE MAINTENANCE

The AD15 Analog Subsystem is constructed of highly reliable modules. The reliability of these circuits,
in conjunction with performance of the preventive maintenance tasks, ensures relatively little equipment downtime due to failure. If a malfunction occurs, maintenance personnel should analyze the
condition and correct is as indicated in the following paragraphs.
The best corrective maintenance tool is a thorough understanding of the physical and electrical
characteristi cs of the equipment. Persons responsible for maintenance should become thoroughiy familiar with the system concept, the block schematics, the operation of specific module circuits, and
the location of mechanical and electrical components. Diagnosis and remedial action for a faulty condition can be undertaken logically and systematically in the following phases:
a.

Preliminary Investigation

System Troubleshooting

Logic Troubleshooting
5-3

5.3. 1

Circuit Troubleshooting

Repair/Replacement

Validation Tests

Recording

Preliminary Investigation

Before commencing troubleshooting procedures, explore every possible source of information. Analyze
the problem before attempting to troubleshoot the system. Gather all available information from users
who have encountered the problem, and check the system log book for any previous references to the
problem.
Do not attempt to troubleshoot using complex system programs alone. Run the AD15
MAINDEC 15-D6GA-D(D) Diagnostic program and select the shortest, simplest program available
that exhibits the error conditions.

5.3.2

System Troubleshooting

When the problem is understood and the proper program has been selected, the logic section of the system at fault should be determined. Obviously, the program that has been selec ted gives a reasonable
idea of what section of the system is failing. However, faults in equipment that transmit or receive
information, or improper connection of the system, frequently give fault indications similar to those
caused by computer malfunctions.

5.3.3

Logic Troubleshooting

Before attempting to troubleshoot the logic, make certain that proper and calibrated test equipment is
available. Always calibrate the vertical preamp and probes of an oscilloscope before using. Make
certain the oscilloscope has a good ac ground and keep the dc ground from the probe as short as possible.
Use the oscilloscope to trace signal flow through the suspected logic element. Oscilloscope sweep can
be synchronized by control pulses or by level transitions that are available on individual module terminals at the wiring side of the logic.
CAUTION
When probing the logic, do not short between pins.
Shorting of signal pins to power supply pins may resu It in damage to componen ts .

5-4

5.3.4

Circuit Troubleshooting

Engineering schematic diagrams of each module used in the AD15 are available; refer to these diagrams
for detai led circuit information.
Visually inspect the module on both the component side and the printed wiring side to check for overheated or broken components or etch. If this inspection fails to reveal the cause of trouble or to confirm a fault condition observed, use the multimeter to measure resistances.
CAUTION
To avoid damaging components, do not use the lowest
or highest resistance ranges of the multi meter when
checking semiconductor devices. The Xl0 range is
suggested.

Measure the forward and reverse resistances of diodes; diodes should measure approximately 20Q forward and more than 1000Q reverse. If readings in each direction are the same and no parallel paths
exist, replace the diode.
Measure the emitter-collector, collector-base, and emitter-base resistances of transistors in both
directions. Short circuits between collector and emitter, or an open circuit in the base-emitter path,
cause most failures. A good transistor indicates an open circuit in both directions between collector
and emitter. Normally 50 to 100Q resistance exists between the emitter and the base, or between the
collector and the base in the forward direction, and an open circuit condition exists in the reverse
direction. To determine forward and reverse directions, consider a transistor as two diodes connected
back to back. In this analogy, PNP transistors would have both cathodes connected together to form
the base, and both the emitter and collector assume the function of an anode. In NPN transistors, the
base would be a common-anode connection, and both the emitter and collector, the cathode.
Multimeter polarity must be checked before measuring resistance, because many meters apply a positive
voltage to the common lead when in the resistance mode.
Because ICs contain complex integrated circuits with only the input, output, and power terminals
available, static mUltimeter testing is limited to continuity checks for shorts between terminals. IC
checking is best accomplished under dynamic conditions using a module extender to make terminals
readily accessible. Using AD15 block schematics and module schematics, proceed as follows to locate
an IC on a circuit board:

5-5

Procedure
Hold the module with the handle in your left hand; component side facing
you.
2

ICs are numbered starting at the contact side of the board, upper righthand corner.

The numbers increase toward the handle.

When a row is complete, the next Ie is located in the next row at the
contact end of the boards (see Figure 5-1).

The pins on each IC are located as illustrated in Figure 5-2.

BB
B

15-0430

Figure 5-1

IC Location

?;::::::
1234567

15-0430

Figure 5-2

IC Pin Location

5-6

5.3.5

Validation Tests

Always return repaired modules to the location from which they were removed. If a defective module
is replaced by a new module while repairs are being made, tag the defective module, and note the location from which it was taken and the nature of the failure. When repairs are completed, return the
repaired module to its original locat~on, and confirm that the repairs have resolved the problem by running all tests that originally exhibited the problem.
NOTE

If modules have been moved during the troubleshooting
period, return all modules to their original positions before run n ing the va Ii dat i on tests.

5.3.6

Recording

A log book (supplied) should be maintained regarding AD15 failures and corrective maintenance. All
maintenance should be recorded in this book. Record all data indicating the symptoms of the fault,
the method of fault detection, the component at fault, and any comments that would be helpful in
maintaining the equipment in the future.
The log should be maintained on a daily basis, recording all operator usage and corrective maintenance
results.

5.4

TEST EQUIPMENT

To service the AD15 Analog Subsystem, the equipment listed in Table 5-1 is recommended. If recommended equipment is not available, alternate equipment with the same performance specification
shou Id be used.

Table 5-1
Maintenance Equipment

Equipment

Specifi cations

Equivalent

Multimeter

10 kn/V - 20 kn/V

Triplett Model 310

asci Iloscope

dc to 50 mc with calibrated deflection factors from 5 mV to
10V/div. Maximum horizontal
sweep rate of O. 1 tJs/di v. Delaying sweep is desirable and
dual trace is a necessity.

Tektron ix Type 453

5-7

Table 5-1 (Cont)
Maintenance Equipment

Equipment

Probes

Spec i fi cat ions

Equivalent

Xl0 with response characteristics
matched to oscilloscope and a Xl
probe.

Tektronix Type P6010
Probe Type P6011

Recessed Probe Tip

Tektronix

Unwrapping tool for 30 AWG

Gardner-Denver
HS12A-505-244-475

Wire-Wrap Tool

Gardner-Denver
A-20557-29

30 AWG bit for wrap tool
(HS10)

Gardner-Denver
504221

Sleeve for 30 AWG bit

Gardner-Denver
500350

Flip-Chip Module Extender

DEC No. W9S0

Jumper Wi res

Assorted lengths affixed with 30 AWG
termipoint connectors

Null Meter Model MV100G
(Precision Power Supply)

Measurement Mode
Range: 0 to ± 11. 1110 Vdc
(resolution: lV)
Input Impedance: infinite at
null; 2 kQ off null.
Max. Sensitivity: 25 jJV/minor
division.
Zero Control: Front panel zero
meter control calibration
balances automati cally.
Output Mode
Range: 0 to ± 11. 1110 Vdc
(resol uti on: 1 jJ V)
Absolute Accuracy: ± .01% or
50 jJ V (of setting) High range
and .01% or ± 2 jJV (of setting) low range
Output Current: 10 mA
Power Requirements: 105 to
125 Vac; 50-65 Hz; 2W
Protection: Short circuit and
overload protected front
panel overload indicator;
recovery automati c.
Vernier: ± .001V (W/Disable
switch for zero)
Output Impedance: <.03 Q
on high range and <20 Q on
low range.

Pulse Generator

Data Pulse 101 or equivalent
5-S

Electronic Development Corp.

5.5

MODULE HANDLING AND REPAIR

To insert or extract modules, first turn off all power. To gain access to components on a module, remove
the module by exerting a straight, even pull on the module handle to prevent twisting of the printedwiring board. Insert a type W3S0 FI ip-Chip Module Extender into the vacated module mounting panel,
then insert the module into the extender.
For information on module repair, refer to Volume 1 of the PDP-15 Maintenance Manual. Do not attempt to repair, adjust, or calibrate the AS77 Analog-to-Digital Converter board except as noted in the
Acceptance and Calibration procedure (A-SP-AD15-0-15).
NOTE
Failure to follow this rule may violate the warranty.

5.6

SPARE PARTS

The customer should maintain a spare parts inventory of those modules listed in Table 5-2. For a list
of recommended ICs refer to Drawing A-SB-PDP15-0-1S.

Table 5-2
Spare Parts Li st

Quantity

Nomenclature

Module No.

Multiplexer
Switch Gain Amplifier
Sample and Hold Amplifier
Voltage Regulator
Analog-to-Digital Converter
Bus Data Interface
Device Selector
I/O Bus Multiplexer
Inverter
2-lnput NAND Gates
3-lnput NAND Gates
4-lnput NAND Gates
Binary-Octal Decimal Decoder
Binary Counter
Six D-Type FI ip-Flops
Dual Delay Multivibrator
I/O Bus Receiver
Data Bus Driver
S-Bit Positive Input/Output Driver
Ribbon Connector
I/O Bus Connector
Bus Connector Modu Ie

BA124
A222
A405
A70S
AS77
M10l
M103
M104
Mlll
Ml13
M1l5
M1l7
M161
M211
M216
M302
M510
M621
M622
M90S
M912
M935

1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

1
1

5-9

CHAPTER 6
ENGINEERING ORA WINGS

A complete set of drawings is supplied with each AD15 Analog Subsystem. If any discrepancies exist
between the drawings in this chapter and those supplied with the equipment, consider the drawing set
supplied with the equipment as the most accurate.

6.1

DRAWING CODES

Digital Equipment Corporation's engineering drawings are coded to designate drawing type, major
assembly, and series. A drawing number such as D-BS-AD15-0-01 contains the following information:

o
BS
AD15

o
01

Size
Type (Block Schemati c)
Equipment designation
Manufacturing variation
The drawing number of a series

The drawing type codes are designated as follows:
AD
BS
01
IC
MU
FD
ML
SP
TO
UA
WL

6.2

Assembly Drawing
Block Schematic
Drawirg Index
Interconnecting Cabling
Module Utilization Drawing
Flow Diagram
Master Drawing List
Spec i fi cat i on
Timing Diagram
Unit Assembly
Wire list

DRAWING NUMBER INDEX

Table 6-1 is an index to the engineering drawings contained in this manual.

6-1

Table 6-1
List of AD15 Drawings

Drawing Number

6.3

Title

Page

D-DI-AD15-0-01

Drawing Index List

6-7

D-BS-AD 15-0-03

Status and Buffered Data Register

6-9

D-BS-AD15-0-04

Multiplexer Address Register

6-11

D-BS-AD15-0-05

Flags

6-13

D-BS-AD 15-0-06

Device Decoder, API and DCH Logic

6-15

D- BS -AD 15-0-07

Analog Subsection

6-17

S-BS-AD 15-0-08

Multiplexer and Decoder

6-19

D-BS-AD 15-0-09

Bus Drivers (two sheets)

6-21

D-BS-AD 15-0-1 0

Bus Receivers

6-25

D-BS-AD15-0-11

Analog Inputs

6-27

D-IC-AD15-0-12

I/O Bus Interface

6-29

D-DI-AM01-A-01

Drawi ng Index

6-31

D-BS-AM01-A-03

Analog Inputs

6-33

D-BS-AM01-A-04

Multiplexer

6-35

D-BS-AM01-A-05

Multiplexer Address Decoder

6-37

D-AD-7007029-0-0

Wired Assembly {Includes Module Slot Locations}

6-39

SIGNAL GLOSSARY

A signal glossary is provided in Table 6-2 as a maintenance aid in detailed troubleshooting. The table
lists the signals in mnemonic form, followed by a brief description of each signal.

6-2

Table 6-2
Signal Glossary

Signal Mnemonic

Description

ADCF

Clears all AD 15 flags.

ADCV

Transfers contents of PDP-15 accumulator to the
AD15 status register, clears A/D DONE flag, and
i~itiates timing for the conversion.

ADD MEM (add-to-memory)

When bit 9 is a logic 1, the AD15 is in add-tomemory mode where the converted data is added
to the value in an existing memory location.

ADRB

Transfers contents of AD 15 data buffer to the
PDP-15 accumulator. Also clears A/D DONE
flag.

ADRS

Transfers contents of status register into the PDP-15
accumulator.

ADSF

Causes a program skip when an A/D flag is raised.

API ENA (Automatic Priority Interrupt Enable A)

Used to gate the API trap address onto the I/O bus.

API 0 EN IN, API 0 EN OUT

An enable signal daisy-chained from device to
devi ce. The API Multiplexer Control Module can
interrupt this level, inhibiting it from all devices
further down the bus. The devi ce recei ves
API 0 EN IN and transmits API 0 EN OUT.

API Flag

A flag raised indicating an API request to the API
Multiplexer Control Module.

API 0 GR (API 0 GRANT)

A signal from the PDP-15 indicating that the API
request from the AD 15 has been granted.

API 0

A signal from the AD15 occurring at I/O sync time
to request service from the PDP-15 on API priority
levelO.

API 0 RQ

Bus driver output of API o. (API level 0)

BFB 00 - BFB 12
(Buffered bits 00 through 12)

This is a second stage of buffering that permits a
second analog-to-digital conversion to begin without destroying the results of a previous conversion.

A/D DONE
(Analog-to-Digital Done)

A signal generated on completion of the analog-todigital conversion.

CA 00 - CA 06
(Channel address 00 through 06)

Represents address of 1 of 128 possible analog input
channels.

CNVT (Convert)

A pulse used with INT SYNC EN to start analog
conversion during internal sync operation.

Count

A signal applied to the multiplexer address register
to increment the register each time a conversion
is completed in sequential mode.

6-3

Table 6-2 (Cont)
Signal Glossary

Signal Mnemonic

Description

DATA OFLO (Data Overflow)

Used by the PDP-15 to indicate that a sign change
has occurred due to overflow during add-tomemory. The AD15 uses this signal to set the
memory overflow flag and generates an interrupt
when enab led.

DATA STROBE

An enable signal used to gate the converted data
onto the I/O bus.

DCH EN A
(Data Channel Enable A)

An enable signal used to gate the word count address onto the I/O bus during direct memory access
mode.

DCH EN B

An enable signal used to request the PDP-15 to
read, wri te, or add -to-memory.

DCH EN IN
DCH EN OUT

An enable signal daisy-chained from device to device. The DCH Multiplexer Control Module can
interrupt this level, inhibiting it from all devi ces
further down the bus. The devi ce recei ves
DCH EN IN and transmits DCH EN OUT.

DCH FLAG

A flag raised to request direct memory access via
data channel.

DCH GR

Issued by the I/O processor when it acknowledges
a request from the AD 15.

DCH

Generated in AD15, occurring at I/O sync time
to request a direct memory access data transfer.

DCH RQ

Bus driver output of DCH.

DEL ADCV (Delayed ADCV)

Delayed from ADCV to permit settling of registers.

DEL OFLO

Delayed by 2.0 I-'s from I/O OFLO to enable
IOP2; consequently, the last data word can be
transferred.

DCH/PROG CTRL

This fl ip-flop, when set, denotes data channel
operation in the AD 15. When reset, it indi cates
program-controlled operation.

DCH STROBE

Used to initiate a data channel request during random operation.

DONE FLAG

A flag raised as a result of A/D DONE being
generated.

DSO-DS5
(Device Select 0 through 5)

The six device select lines decoded from bits 6
through 11 of the lOT instruction.

EXT SYNC

Used when an external source of sync is desired
with the AD15.

6-4

Table 6-2 (Cont)
Signal Glossary

Description

Signal Mnemonic

EXT SYNC EN;t NT SYNC EN

Bit 8 of the I/O bus is used to load a control flipflop with EXT SYNC EN (flip-flop set) or INT
SYNC EN (flip-flop reset).

EXT/INT SET L

Used to force the EXT SYNC;tNT SYNC flip-flop
to internal sync on completion of conversions.

GSO, GSl (Gain Switching)

Two bits decoded into one of four possible gain
selections.

I/O ADDR 12-17
(Input/Output Address 12 through 17)

These lines constitute an input bus to the PDP-15
for delivering address data from the AD15. The
address is either an API trap address or data channel word count address.

I/O Bus 00-17

A set of lines connected between PDP -15 and its
peripherals for bidirectional data transfer.

I/O SYNC

A PDP-15 clock pulse issued every microsecond.
The signal is used to synchronize API RQ or
DCH RQ to the PDP-15.

I/O OFLO

Indicates to the AD15 that the desired number of
words have been transferred on the completion of
the transfer in progress. It is normally used to turn
off the AD 15 and to initiate an interrupt.

10Pl (Input/Output pulse 1)

A microprogrammable control signal decoded from
bit 17 of the lOT instruction. Used for I/O skip
instructions to test a device flag.

IOP2

A microprogrammable control signal decoded from
bit 16 of the lOT instruction, when in program
control mode. This signal can also be generated
during direct memory access mode when an AD15to-PDP-15 data transfer (read request) is desired.

IOP4

A microprogrammable control signal decoded from
bit 15 of the lOT instruction, when in program
control mode. This signal can be generated during
direct memory access mode when a PDP-15-toAD15 data transfer (write request) is desired.

10Tl (Input/Output Transfer 1)

Bus received version of 10Pl .

IOT2

Bus received version of IOP2.

IOT4

Bus received version of IOP4.

LOAD

Used to generate CNVT pulse during random operation.

MEM EN (Memory Enable)

Enables DATA OFLO signal to raise memory flag
when bit 6 is set to a logic 1.

6-5

Table 6-2 (Cont)
Signal Glossary

Description

Signal Mnemonic

MEM FLAG

This flag is raised during an add-to-memory operation when the quantity added to memory causes a
change of sign.

MSSF

Causes a program skip when the memory overflow
flag is raised.

PROG INT

A signal generated in the AD15 to request interruption of the program in progress so that the
AD15 can be serviced. This signal causes the program to trap to location 000000 where no higher
priority action is in progress. The instruction in
I ocati on 000001 is then fetched and executed.

PROG INT RQ

Bus driver output of PROG INT.

PWR CLR (Power Clear)

System clear signal. Used as initializing signal
for AD15 control flip-flops and registers.

RD (Read)

Used by the AD 15 to spec ify that a data word is to
be transferred from the AD15 to the PDP-15.

RD RQ

Bus dri ver output of RD.

SD 00, SD 01
(Subdevice code, 00, 01)

Two subdevice select lines decoded from bits 12
and 13 of the lOT instruction.

SELECT CLOCK

A control signal used to clock various control signals, gain switching and operating modes.

SEQ,lRAND (Sequential,IRandom)

If bit 10 is a 1, the AD15 is in sequential mode
where conversions are done in sequential multiplexer channels. If bit lOis a 0, the AD 15 is in
random mode where conversions are taken in random multiplexer channels.

SKIP

A PDP-15 instruction generated in the AD15 to
cause a program skip of the next sequential instruction.

SKIP RQ

Bus driver output of SKIP.

SYNC

Bus received version of I/O SYNC.

WCSF

Causes a program skip when the word count overflow flag is raised.

WC FLAG

A flag indicating word count overflow (desired
number of words have been transferred).

WR (write)

A signal used by the AD15 to specify to the
PDP-15 that a PDP-15-to-AD15 data transfer is to
be made.

WRRQ

Bus driver output of WR.

6-6

I,," I

DEPT USAGE

ettyDfDitQlE~Corporation.ndshli.notbe
Th"diaw;
. . • .. _ · - · ·.....

DEPT USAGE

~rocIucedorcopiedorUMdinwhole~inpartb

the basis fOI' th! rrgnufaetu... « lllie f1f n.nIl wtthaut
wntten 1*'fQ1HIOn.

C?
I

IND
NO.

REF
H%H

ANALOG
SUB-SYSIDl
A-PL-AOI5-lHl'

PLATE, CDVOR

ASSY

- \=ZOOZ1~

PART NO.

ANALOG SUB-SYSTEM (PL)

A-PL-ADI5-\1-1l'

FRAME & WIRED ASSY
FRAME& WI RED ASSY (PL)
FRAME, LOGIC MOUNTING

E-AD-7007125-ll-l
A-PL -7007125-0'-0'
E-I A-7408379-il'-0'

WI RED ASSY (AOI5)
WIRED ASSY (ADI5) (PL)

D-AD-7007029-0'-0
~-PL -7007029-0'-0

LOGI C FRAME ASSY TR I PLE
LOG I C FRAME ASSY TR I PLE (PL)
STRAP TRIPLE FRAME
CONN. BLOCK MTG FRAME
288 PIN CONN BLOCK WRAP TY PE

D-AD-7005884-0'-i<!

B-UA -H929- 3-0'

[

CABLE ASSY (BC0'1 P-4)

D-UA-BC01 P-~-liJ

PLATE ASSY, AMPH
PLATE ASSY, AMPH (PL)
PLATE, AMP

C-UA -H92 9-D-0
.~-PL -H929-D-0
C-I A-740837b-lil-il

POWER SUPPLY
BRKT ASSY

WIRED A5SY
(ADI5)
D-AD-7007125-IHI

/,,;;\y

(if

®-Y

f.7L~ROUGH
As~iliJY'
\!...;BEZEL & CABLE

PLATE ASSY. AMPH
C-UA-H929-D-II

Flc

IND
NO.
1.

A-PL -7005884-IHI
C-MD-7407513-liJ-0
D-I A-7407507-IH3
E-5C-1205348-1l'-0

D-UA-H929-A-0'

'----------'

UST

®-

LOGIC fRAME
ASSY TRIPLE
D-AD-700588'1-0-0

BC09B
CABLE ASSY

DESCRIPTION

PART NO.

ANALOG SUB-SYSTEM
MODULE UTILIZATION LIST
STATUS & IJ.JFFERED DATA REG
MUL TI PLEXER ADDRESS REG
FLAGS
DEV I CE DECODERS AP I & DCH LOG I
ANALOG SUB SECT I DN
MULT I PLEXER & DECODER
BUS DRIVERS
BUS RECE IVERS
ANALOG INPUTS
1/0 BUS INTERFACE
ENGINEER1NG SPECIFICATION
CALI BRAT I ON & CHECKOUT
PROCEDURE

A-ML-ADI5-0
K-MU/P L - ADI5-0-02
D-BS-ADI5-(l-03
D-BS-ADI5-IHI4
D-BS-ADI5-IHI5
D-BS-ADI5-i<!-0b
D-BS-ADI5-0-07
0-BS-ADI5-0'-08
0-BS-ADI5-0'-0'9
0-BS-ADI5-IH 0'
0-BS-ADI5-0'-11
0-1 C-AOI5-0'-12
A-SP-AD15-IH 4

ACC;::PTANCE

D-AD-7007095-0

,~y
0-

PROD

CAB roSy
I D-UA-H9bH-ll
I

AM & WIRED

DESCRIPTION

PROCEDURE

PROD CUST

Flc

~4-1g~~-;g:i1

WIRED ASSY (AD15)
WI RED ASSY (ADI5) (PL)
WIRE LIST

D-AD- 7007029-11-11
A-PL -7007029-Jil-1l
K-WL-ADI5-1i1-13

10.

SCHEMATI C

D-SC-1210040-0-0

.. -..

D-UA-BC09B-IHI

I-:~~:"::":"-"--"---.J

[32 CHANNEl flUX
A-PL -AM01-A-Iif
n-n l-ftMGI'-ft-Gl'

SWI TCH
BA12A

®-

11.

• 32 CHANNEL MUX (PL)
DRAWING INDEX LIST (AM01)

A-Pc -AM01-A-0
O-DI -AM01-A-0\

12.

'CABLE ASSY (BClllN-4)

O-UA-BC01 N-4-liJ

13.

PLATE ASSY, BNC
PLATE ASSY, BNC (PL)

C-UA-H929-C-0
A-PL -H929-C-(I

B
PLATE, BNC.
CONN
C-IA-7408374-il-0'

NOTES:

''1(7'f

A-PL-BC~9-"-0

D-AD-7007095-0-0
A-PL -7007095-0-0
A-OC-5309245-0-il'
E-I A-S309244-liJ-0

4 INPUT MULTIPLEXE1

CABLE ASSY
(BellI N-4)

D-UA-BC0'1 N-4-Iif

C-UA-H929-C-0

D-UA-BCfl9-6-0'

10.

PLATE ASSY, BNC

BCI<!9 B CABLE ASSY
8C09 8 CABLE ASS Y (PL)

14.

PLATE, BNC CONN
BNC CONN PLATE

C-I A-7408374-(l-liJ
B-SS-7408374-IH

15.

*'4 INPUT MULTI PLEXER SW ITCH

BA124

I. O£NO TES

SFE

e. FOR
TO

OPT/(J/'{$

/t015'.

1--.

MOt:J(/~E c/7'/~/Z/IT/O/,( (OPTltN")

MA X CONF'/GuRA'T'/OtV
D-~R- PDP/S-¢-Z.

flEPER

DRAWING
INDEX LIST

g
'"-<z

:I:
U

DEC FORM NCI
DRG 111

6-7

This.dravri.na:and~.heNiD.aretbtPropertyof Oisibl EquiprnentCorpontion and thai not be

reprodue.dorcopiedorl.Bllldlnwtu.arinpartlS

the bui5mrUwnanur.ct:un.Ol' .... ofitllms .
wrlttBapermission.

-ADI1l7 BIT I1lI1l H

AOl1l7 BIT 1112 H
BI

Cl
BI

BFB
I1lI1l
M216
01117

HI
H2

C
+3V EI1l2Ul H

+3V E0BVI H

Cl
Bl

+3V EI1lSVl H

BFB
1115
M216
01117

S2
51

E2
D2

BFB
07
M216
009

Jl
HI

BFB

09
L2

M216
D09
C

Nl
0

BFB
11
M216
D09

52
0

BFB
10
M216
009

12 H

H
J2

BFB
08
M216
009

+3V E02Vl H

AD07 BIT 09 H

BIT 1118 H
Ul

III

BFB
06
M216
009
C

0
BFB
1112
M216
DI1l7
C

ADI1l7 BIT 07
SI

HI
0

0
BFB
12
M216
D0S

+3V E02VI H

C
KI

A007 EOC H
AD05 MEMORY FLAG (1 lH
Kl

MIll
C07

MIll
CI1l7

B
-T~

+3V E08UI H

RDII1l BUS 10 H

CI
BI

______________________,F2
EI
ROl0 BUS 09 H

SEQ!
OlRND
1'12t6
E07

E2
D2

III

ROl0 BUS illS L

AOO
MEM
H216
E07
C

AD05 Dill IEXT SET L

Jl
HI

+3V E08UI H _-+'N""2_ _ _ _ _ _ _ _ _ _ _ _rR"-I_ _ _ _ _ _ _ _ _ _ _--,U2

]NT lEX
SYNC
EN
M216
E07
C
0

L1
A0111l BUS 1117 H

M2
L2

P2
ADII1l BUS 06 H

DCHI
PROG
CTL
M216
E07
C
III

PI
NI

ADI0 BUS I1lI1l H

MEM
EN
M216
E07
C

T2
52

III

+3V E02Vl H

V2
AD111l BUS III 1 H

GS III I
M216
E07
C

III

+3V E0SUI H_~R~I_ _ _ _ _ _ _ _ __r-----~A~I-------_+---~A~1------~---~K=2---_ _ _ _ _~---~K=2--------r_---"K2

E2
02

D
G5 00
M216
D0S

+3'v E02VI H

R00'1 SELECT CLOCK H

-PRODUCED BY THE AUTOMATED DRAFT]NG SYSTEM-

CHK

SCALE
SHEET

8________~_______7________~_______6________~______5________~_______4________~_______
J ______~________2________~____________ ~

L -_ _ _ _ _ _

6-9

ThiS drawingancl. specillcrtions, hereill. ..re the PAIP"
ertyofIJ9talEquipmenl:~.ndshliHnoI:be

reprodua!dort:tlpiedorusedinwhoilotinPlrtllS
tAeba$isforthemanIlfaduIWOf_ofltlmswlbout

ADI1l6 DCH ENB H
RD11l1 lOT 'I H
RD05 WORO COUNT FLAG (1 JH
51

-RDI1l5 I.IR L

RD0'1 LORD L
S2
RDI1l6 RDCV L

-R005 RD L

MIll
E09

AD0'1 SELECT CLOCK H

0
Jl

MIll
£09

-A0111l BU5 17 H
T2

CA 06 (01H
CR 06 (1 lH
eA 05 (01H
CR 0S (1 lH

RD10 BUS 17 H
U2

"'I

(11H
CR 03

-RD111l BUS 16 H

AD05 COUNT H
RDI0 BUS 16 H

Roo3 SEQ/RAND

(I lH

+3V E02Vl H

-RDI0 BUS 15 H
-RD10 OFLO L _=~

__
AD10 BUS 15 H

-RDI0 BUS 1'1 H
Roo'l DEL OFLO H
+3V E01Ul H!..l.-'-'''O'--/

RDI0 BUS 1'1 H

-RD1!lI BUS 13 H

HZ
RDI0 BUS 13 H

L2
-RDIIlI BUS 12 H

ADI0 BUS 12 H

-RDIIlI BUS 11 H

-PRODUCED BY THE AUTOMATED DRAFTING SYST£M-

CHK

6-11

AD0S CLEAR DCH FLAG L
)-.!.F...:.I_ _--!.:N!..CI--1 MIll
C07
ADllO PWR CLR

X:~~r_----------------------~Rl

AD06 ADCF

PI
ADliJ6 DCH ENB H

AD04 DEL OFLO H

MIl3
EliJ2

O_...:.N!..!I_ _.:...P2"C] MIll
C07

AD03 SEQ/RAND (10 lH
RD0S DEL FlDCV H
FlD03 DCH/PROG CTL (I lH

AD"'5 WORD COUNT FLAG (I lH

WORD
COUNT

AD05 MEMORY FLAG (1 lH

>-...:;R",2~-,",N:..:.I--1 ~~~~
EliJ6
C
0

AD0S DCH STROBE L

EI
SI
AD"'3 SEQ/RAND (0 IH

+3V E"'1 Ul H

K2
ADliJ6 ADRB L
AD(1I6 ADCV L

AD0!; CLERR API FLAG L

M2
AD07 AID DONE H

HZ
Nl

AD03 DCH/PROG CTL (0)1-!

AD07 A/D DONE H

API
FLAG
M216
E06
C

+3V E01UI H

AD1'" PWR CLR L
CI

MIll
E09

MIll
EliJ9

AD03 INT /EXT SET L

AD06 ADRS L

AD"'6 ADRB L

T2
PI
Rl
SI

AD10 B DATP. OFlO H
AD03 HEM EN (I IH

0
MEM
FLAG
M216
E"'6

ADliJ5 RD H

SI
0

I I

AD03 SEQ/RAND (1 lH

t<2
AD03 SEQ/RAND [0lH
M2

B
AD03 DCH/PROG CTL (I lH
AD06 DCH ENB H
AD03 ADD MEM (I JH

AD03 SEQ/RAND (1 lH

02
E2
F2
H2

M117
E08

ADIOS DCH ENA H
ADliJ3 SEQ/RAND (IiJ)H
N2

AD05 WR H

AD05 WR L

-PRODUCED BY THE AUTOMATED DRFlFTING SYSTEM-

CHK

6-13

-R006 FlOCV L

_=,.-_
T2

+3V f0IUl ,H~..I-~':1-_""1

AOOS DEL ADCV H

~~~--~~~~~

FlOle SYNC H
Fl010 PWR CLR H
R010 B API 00 GR H
ADI2 API 00 C:N :IN H
A00S API F"LRG (0 I H

M101

007

A00S 0
1'101..0
~01

El
Fl
PI
SI
J2
M2
U2
JI

AOHl SYNC. H
FlO I 0 PWR CLR H
RDI0 B OCH GR H

I'lOOS I'lPI ENR H
1'1006 RPI L
1'1006 RPI 00 EN OUT H

1'1012 OCH EN IN H
A00S DCH FlFIG I 0) H

Ml0i

ROO

A006 CLEAR API 'LAG L

AD06 DeH ENB H

PI
SI

AD06 OCH ENA 1-1

A006 OCH L
A006 DCH EN OUT H

H2
U2
JI

A006 Cl ERR DCH F"lFIG L

FLAG (01H
T lilt H
SSD 00 H

c
-ADt0 aso- 01 H
Floo~

OUNT'lFIG (01H
H

AD0S M
AOt

A006 SKIP L

~lAS --I-0-lH
·~II-I

A00G ROCF" L

V2
Fl00S COUNT H

ADIIlJ OCH/PROG CTL (0)H

A006 AOCV L

ADt0 lOT 01 H

AD0'1 LOFID l

A00S ROCV H

1'1003 SEQ/RRNO (1 IH
A010 BOS 00 l
AC10 80S 01 L
AD10 ~ 02 H
A010 BOS 03 L
ADt0 80S 0'1 H
AC10 80S 05 H

02
E2

AD06 DEL AOCV H
V2

.2
H2

J2
K2
L2
N2
AD10 BSC 00 H
-AD10 BSO 01 H

rr~J~2~

__________

___________________ A006 ADRS L

A005 WORD COUNT F"LAG (11H
A006 DeH ENB H
AD10 LOT 02 H

PI
Rl
51

}--"S"'2'-r-_ _ _ _ _1'1006 OFlTA STROBE H

Fl00S RORB l

AD10 lOT 02 H
-FlOI0 SSD 00 H

-PRODUCED BY THE I'lUTOMATED DRRFTING SYSTEM-

CHK

R
DEVICE DECODERS API
+ DeH LOG

SHEET

]

6-15

AD03 INT IEXT SYNC EN [0 lH

AD07 EXT SYNC H

ADI2I3 INT IEXT SYNC EN [1 lH
ADI2IS CNVT H

H2
N2
P2

AS77
Cl1
D11

CU1

N1
HI

+3V EI2I2VI H
BH2

,------------l
""RD",I2I",S,-A""N.!!:A",L""OG",-,IN".,P...,U""T'--t-,P,-,2'--1

~222
C12

+15V AD2
-15V RE2

+5V BA2

~~--------r---~------------------~

I
I

RD~3

GS I1ll [0lH
AD03 GS 00 (l2IlH

R4121S
A12
B12

AS2

BIT 00 H

DJ2

BIT 01 H

DK2

BIT 02 H

DL2

BIT 03 H

DM2

BIT

DN2

BIT 05 Ii

DP2

BIT 1216 H

DR2

BIT 07 H

DS2

BIT

DT2

BIT 1219 H

DU2

BIT 10 H

DV2

BIT 11 H

DJ1

BIT 12 H

.15V CD2
DFI

-15V CE2

OWl
RD07 AID DONE H

ADI2I7 EOC H
+3V B13UI H

4K I
.12I1~1

BF2
+5V

DA2

I
I

ADI2I3 GS 00 (1 lH
S2

BIT 0121 L

CJ2
RV2

~ W2

DE2
DF2

.~~~I

I
I

ADI2I3 GS 01 [1 lH

I
lK 1
.1211,;1
1

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _

1
1

.~~,;I

I
1

I
I
I
I
L ____________ -'

ll7

I17
E08

+3V EI2I8VI H

b:
Ul

... 3V EI2I2U1 H

t::

113
EI2I1

113
[02

'13
E02

E08

+3V EI2I8Ul H

"'3V E02V1 H

t::

113
B13

"'3V E01UI H

+3V B13U1 H
-PRODUCED BY THE RUTOMATED DRAFTING SYSTEM-

CHI<

6-17

-_ __ ...,. .. -

..._8_ oncI_
........ ...

rtprQducecIorCQClledOltllildltl ...... otlftpert.

=-..:::...lMIMIIIctureor ..

oI . . . . . . . .

~
J2
L2

A12'!
C 13

AOII

CH 01 H

CI3

CH 02 H

~ ~AOl1
P2

+3V E02VI H
CA 00 (0)H
A00~ CA 01 (0)H

AD04

9~
~~~
8~
81
S2

CH 03 H

CH 05 H

C14

~~ADll

C13

J2
L2 J

A011

CH 08 H

CH 06 H

ROll CH

~ ~ROl1

013

~ ~ADll
N2

AI24
011

D14

CH 09 H

~~ ~ADII

013

CH 10 H

CH07H

013

CH 13 H

D14

~ ~A01ICHllH ~ ~ROI1

e14

12 H

~ ~ADl1

el4

~~ADll
N2

A124
013

~ ~ROl1

CI3

~~ ~AD11
c

AD II CH 04 H

~ ~AOll
N2

JZ
L2

1;(2

CH 00 H

A124
C14

CH 11 1-1

014

CH 151-1

MI61
F09

~
LZ

.-J!L 2
A00'! CA 02 ( 11H

AD04 CA 03 (11H

AD01 CA 04 (11H

22
21
2

I
I

3~
~
2 r--#1

Wz-f:>tr

~
J2
L2

PHr---or-

0p-N-

J2
L2 J

E12

Fl12~

ROll

CH 16 1-11

~~RDll
H2

A124
E13

ADII

ROIl

CH 24 HI

1-1

~
J2
L2J

~ ~AOll

EI3

CH 21

A124
FI2

CH 17 H

CH 20 1-1
!

~ ~RDll

EI2

~
J2
L2

FI2

AOII

CH 28 1-1

jV2

~
HZ

CH 25 H

A121
F13

F13

I I

~
52

ADII

CH 29 1-1

B
r-

~~RDll
N2

~ ~ROll
P2

ADI2I8
ADI2I4
ADI2I4
ADI2I4
AD01

-~ ~ADll
N2

E12

CH 18 1-1

~~"'"
P2

E12

CHI9H

~~ ~RD11

EI3

CH 22 1-1

E13

~ ~ADll
P2

,"OJ,

ANALOG INPUT H
CA 05 (I 1H
CA 06 (01H
CA 06 (I lH
CA 05 (I2IJH

FI2

~~ ~RDII
N2

CH 26 1-1

F12

F1:J

H
j

NOTE:
I.
Al21 MODULES ARE OPTIONRL
INSERT AS REQUIRED
FOUR CHANNELS PER MODULf.

-PRODUCED BY THE RUTOMRTED DRAFTING S{STfM-

CHK

CH 30 H

~~"" '"""
P2

CH27H

Fl3

6-19

(1 )L

AD03 SEQ/RAND (13 lH

AD06 WRITE (I)L

ADel5 WRI1E (111 JH

flD0J SEQ/RAND

D_....:V-'=2~-'-'M"'2U HIlI

E09

D
flDel6 API ENA H
(571

ADel6 DCH ENA H
(26)
HZ

AD 12 I/O ADDR 16

i-I---+-1- - L J

I I
B

1
...

REVISIONS
CHK I

CHANGE NO.

l3. '/iJ~~/' ~/rj7" mamDDmoEQU
••
- ::~!;~~s~.~~ls~~
~ rrJ...JU I7'l>,p TITlE
R
I~

lPMENT

i REV.J
I
I

I~~')J< BUS DRIVERS
~/I

~?1J.z.
II'I!l E~
IFRt 11:-;1

~rr,.I!i_

. OSED 0lIl

PDP15

SIZEICODEI
NUMBER
D BS
AD15-0-09

~
SHEET

REV.

210

DlST. I

..1 J ..1 ..1 J ..1 J .1 ..1

6-21

-_ _-_..-. ....

...... --~

.....

~orcopiedorusedlnwholeorlnl*l.

=-~mmulal:bnarllllflll_~

D
AD03 BFBI2 101H
ADI1J6 DATA STROBE H

AD03 BFB 06 (01H
AD06 DATA STROBE H

AD03 BFB 00 (0JH
PDIII6 DATA STROBE H

01
02

ADI1J5 MEMORY FLAG (01H
AD0E. ADRS rl

E2
RD04 CR 06 (1 lH
ADI1JE> ADRS H

ADI1J3 BFB 11

RD04 CA 011J (1 1H
ADI1J6 ADRS H

(01H

AD03 BFB 05 (0 lH

ADI1J5 ~DRD COUNT FLAG (0 JH

AD04 CR 11J5 (1 lH

ADI2 1/0 BUS 05

ADI1I3 BFB 04 (III lH

ADI1J3 BFB ll1J (01H

AD04 CR 1114 (1 lH

AD03 BFB 11J9 (0 lH

ADI1J3 BFB 03 (0 lH

AD04 CR 1113 (1 lH

I I

II
AD03 BFB 08 (01H
AD03 BFB 02 (0 JH

AD04 CR 02 (1 1H

AD03 BFB 'l!1

AD03 BFB 07 [III JH

AD04 CR 01

(1II1H

(1 lH

-PRODUCED BY THE AUTOMATED DRAFTl'lG S(STEM-

momoamB ~~~i§.~~~~~~

CHK

~~~~~-G~~~TITlnLeE~--~~~----~~~~~R

t..;;~S'eoo::---I*f:,;;u.'-I BUS

DRIVERS

PDPIS
SCALE

SHEET

6-23

This drawing and speciftcdions, beNin, . . the propertYofDigitalEquipmeatCCtllOnltiOnandsbdnotbe
NpnXIuced otccpied or used in whotecrlnput ..

-...-

tt»basisfortMmMlllldUreor .... Ofillml'fllllllout

RDI0 BUS 08 L

BUS 16 L

AOl2 I/O BUS 08 L

AOl2 I/O BUS 16 L
RD1~

ROl2 110 PWR CLR H

BUS 08 H

ROl0 PWR CLR

BUS 16 Ii

_ _C_l_ AD10 PWR CLR H

A012 SO 001 H

M510
C01

R010 BSO 00 L

A010 BSO 00 H

R010 BUS 09 L

M510
Cl1Il

R012 OCH GR H

M510
C01

I
I

ROl2 API 00 GR H

ROl0 BUS 10 L
AOl2 OATR OFLO H
R010 BUS 10 H

R012 liD SYNC H

A010 BOS 0111 H

ROl2 OS 02 H

R0101 BOS 02 L

A0101 80S 02

M510
C04

R010 IOT 01 L
A012 IOP 01 H

AOII2I BUS 1J H

R010 BOS 0D
A012 OS 03 H

M510
CelD

M2
A010 BOS 011 H

R010 SYNC H

A012 liD BUS 13 L
R010 BUS 1211 H

M510
C04

R010 BOS 01 L

R010 BUS 13 L

R010 BUS 01 L

R010 BOS 0111 L
K2

R0101 OFLO H

ROIl11 BUS 12 H

AOl2 110 BUS 01 L

DATA OFLO

AOlO1 B RPI 0111 GR H

A010 SYNC L

R012 I/O BUS 12 L
R010 BUS 00 H

ORTR OFLO

R010

AOl2 OS 01 H

M510
C0D

R010 BUS 12 L

R010 BLiS 001 L

1'101111

M510
C04

A010 OFLO
A012 I/O OFLO H

11 H

R012 110 BUS 1110 L

R012 DS 00 H

M510
C0D

11 L
A012 I/O BUS 11 L

R010 B OCH GR H

R010 BUS 17 H

ROl2 110 BUS 1111 L
R010 BSO 01 H

R010 B OCH GR L

R010 B RPI 00 GR L

AO 12 110 BUS 1 7 L
A010 BUS 09 H

R010 BSO 01 L
AOl2 SO 01 H

R010 BUS 17 L

R012 110 BUS 0'3 L

R01!!! lOT 01 H

R010 BOS 03 H

B
R010 BUS 14 L

R010 BUS 06 L

R010 lOT 1212 L

R012 I/O BUS 14 L

AOl2 110 BUS 06 L

A012 IOP 02 H

A010 BUS 14 H

A010 BUS 1216 H

R012 OS 04 H

A012 IOP 1M H

R012 I/O BUS 15 L
R0101 BUS 15 H

A0101 BUS 07 H

LJl

R010 BOS 04

AOII21 BOS 04 H

M510
CI2IJ

ROl0 lOT 02 H

A010 lOT 04 L

R010 BOS 05 L

M510
C0J

RD10 lOT 014 H

A010 BOS 05 H

A010 BUS 15 L

R010 BUS 07 L
A012 110 BUS 07 L

M510
CI1I4

M
I

-PRODUCED BY THE AUTOMATED ORAFTING SYSTEMCHK I

REVISIONS
CHANGE NO.

mamamDEQU
. nTLE•• . ~~!!:~s~~~~~:!~ R

~ ':!!~-f.

~REV.J

~~.

I PM ENT

~.~~_t ~~;;

1Ell'
'Pft(

~I:,h.

""-.

EN~

~ ,;J,.
~r.I}1

:- ,...~

BLiS RECEIVE.RS

ARS 'U!IEiJ 01(]

POP15

/SCALE
SHEET
I

SIZE1COOj
NUMBER
o BS ROI5--0-10
1

O1ST_ I

I I I J JJ

6-25

REV.
00

I I I

_-_
-..

.._"IRP'
- .....

TNt. *-iIII1M ...................

..."

~OI'copiIId . . . . III . . . . . IIII*1 •

......................... " ..... "IIIIlIIIIt

M91118

M9I2l8

M91118

[l'!

1'1011 CH 16 H

FlOll CH 00 H

M935
R14

rl'!

1'1011 CH 17 H

ROll CH 01 H

ROll CH 2"1 H

CH 08 H

+15V H
-2111V H

1'1011 CH 18 H

FlOll CH 02 H

1'1011 CH 25 H

CH 1119 H
1'1011 CH 19 H

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6-35

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