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Document:	DU11 Single Line Programmable Synchronous Interface User's Manual
Order Number:	EK-DU11-OP
Revision:	001
Pages:	48
Original Filename:

OCR Text

DU11 single line
programmable

synchronous interface
user’'s manual

dlilgliltiall

EK-DU11-OP-001

(
|

DU11 single line

- programmable
-

synchronous interface
user’'s manual

digital equipment corporation « maynard, massachusetts

1st Edition, November 1976

The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes
no respon-

sibility for any errors which may appear in this
manual.

Printed in U.S.A.

'This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

DECtape

PDP

DECCOMM

DECUS

RSTS

DECsystem-10

DIGITAL

TYPESET-8

DECSYSTEM-20

MASSBUS

TYPESET-11
UNIBUS

CONTENTS
Page

CHAPTER 1
1.1

1.2
1.2.1

1.2.1.1

1.2.1.2
1.2.2

1.2.2.1

1.2.2.2
1.3
1.4
1.5

1.5.1
1.5.2

1.5.3

1.53.1
1.5.3.2

1.6
1.6.1
1.6.2
CHAPTER 2

INTRODUCTION

SCOPE .......... e e e e e e e e e e e e e e e e e e e e e e e e e e e e e
.. ..
DATA COMMUNICATION TECHNIQUES AND SYSTEMS . . . . . ... ...
oo
i
v
v
v
v
o
o
.«
.
.
.
.
.
.
.
.
Techniques
on
Data Communicati
e e e e e e e e e e e eP
Pulse Coding . ... ... .. e

e e e e e
Pulse Code TranSmission . . « « « v o v v v v v v o s e
e e e e
e
h
.o
o
.
.
.
.
.
.
.
.
Systems
on
Data Communicati
e e e e e e
e
e
e
e
e
e
e
e
e
e
.
.
.
.
.
Systems
Synchronous
PP
o
v
.ot
.
.
.
.
.
.
.
.
.
Computer Application
ee
e
e
e
e
e
e
e
e
e
e
e
....
...
...
..
.
N
GENERAL DESCRIPTIO
e e
e
e
e
e
e
e
e
t
e
e
e
itt
i
i
.
.
.
.
.
.
.
ON
PHYSICAL DESCRIPTI
e
e
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e
e
e
e
e
e
e
e
e
e
e
i
i
NS
e
e
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e
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i
i
ATIO
o
.
.
..
SPECIFIC
e e
e
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e
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e
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e
e
e
o
v
o
.
.
.
.
Environmental
e e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
o
o
Flectrical . . . . v
e e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
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s
o
o
v
PerfOrMANICE & « o
...
o0
v
e
v
v
v
v
¢
.
.
.
.
.
ns
Communicatio
Baud Rates for Synchronous
e e e
... e
Baud Rates for Isochronous Communications . . . .. ...
e e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
it
i
.
.
.
.
.
ENGINEERING DRAWINGS
e
e
e
e
i
i
vt
v
.
.
.
.
.
.
.
Basic Signal Names
INSTALLATION

2.2
CHAPTER 3

DEVICE REGISTERS AND INTERRUPT REQUESTS

2.1.1
2.1.1.1

2.1.1.2
2.1.2
2.1.3

2.1.4
2.1.5

3.1
3.2

1-1
1-3
1-3
£
1-5
1-5
1-6
1-6
1-6
1-6
1-6
1-6
1-6
1-6

Flip-Flop Signal Names . . . . « o v v v v v ee e e oo i e e 1-8

e e e e e e e e e
INSTALLATION . . o o e i e e e e e e e e e e e e e e e e e e e
v v oo oo e v v
v
v
v
v
.
.
.
.
.
.
.
.
.
Computer
the
in
DU11
the
Mounting
e e
e e
Standard Configuration . .+ « v v v vt i e
e
. . . . . . ¢« v v v v v v vt v
Current Mode Configuration
Installing the Modem Cable Harness . . . . . .« « o v v v v v v v oo v oo oo v v
Unibus and Interrupt Vector Address A881gnments ...................
Jumper ASSIgNMEnts . . . . . .. w e e e e e e e e e e e e e e e e
I
- Priority Assignment . . . . ... T
e e e e e s
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
o
o
o
.
.
.
TESTING
INITIAL

2.1

1-1
1-1
1-1
B

DEVICEREGISTERS

. . . o it i ittt i et

e e e e

2-1
2-1
2-1
2-1
2-1
2-5
2-5
2-6
2-6

e e 3-1

3.3

e 3-1
e
. . . . . . . .o .o oo
Register Address Assignments
3-1
e
oo
v
v
v
oo
.
.
.
.
.
.
.
Assignments
Bit
and
Title
Register
3-1
e
e
e
e
e
e
e
e
e
e
e
i
o
v
o
.
.
.
.
.
.
Assignments
Title
3-2
e
e
e
e
e
e
e
e
e
e
e
i
.
...
.
.
.
.
.
.
Bit AsSignments
3-10
e
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e
et
e
e
et
e
e
et
e
e
e
it
it
i
o
.
.
.
.
INTERRUPT REQUESTS

CHAPTER 4

PROGRAMMING REQUIREMENTS AND RECOMMENDATIONS

3.2.1
3.2.2

3.2.2.1
3.2.2.2

4.1
4.2
4.2.1

4.2.2

4.2.3

424

INTRODUCTION . . o o i e e e e e e e e e e e e e e e e e e e e e e e e e e e e e
PROGRAMMING THE TRANSMITTER IN THE SYNCHRONOCUS MODE . . . . .. ..
e
e
Loadingthe PARCSR . . . . . . . . . . o it it
ee
Enabling the Transmitter . . . . . . . . . . . oo ot vt e
Detecting the Last Character of the Message . . . . . .. ... .. ... ...
Transmitting Initial Sync Characters to Establish Synchronization . .. ... ... ..

4-1
4-1
4-1
4-1
4-1
4-1

CONTENTS (Cont)
Page
4.2.5

4.3

Transmitting Sync Characters to Maintain Synchronization

PROGRAMMING THE RCVR IN THE INTERNAL SYNCHRONOUS MODE

4-2

4.4

PROGRAMMING THE RCVR IN THE EXTERNAL SYNCHRONOUS MODE

4-3

4.5

PROGRAMMING THE XMTR IN THE ISOCHRCONOUS MODE

4.3

4.5.1

Loading the PARCSR . . . . . . . o

4.5.2

Enabling the XMTR

. . . . . . . . . . . .

4.3

4.6

PROGRAMMING THE RCVR IN THE ISOCHRONOUS MODE

APPENDIX A

REPRESENTATIVE MODEM FACILITIES AVAILABLE

APPENDIX B

ADDRESS ASSIGNMENTS

e e e

4-3
4-3

ILLUSTRATIONS

Figure No.

Title

1-1

Asynchronous Technique Format

1-2

Synchronous Format

Page

. . . . . . . . . . . . .. . i

. . . . . ... ... ... ...

..........

1-3

Typical Communication System Using the DU11 Interface

DU11 Major Components

. . . . . . . . . . 0

1-5

Flip-Flop Signal Names

. . . . . . . . . . . . .

2-1

Standard Configuration (DU11-DA) Using DD11-B Mounting Panel

1-6
e e e e e e e e e e e e e

1-2

1-3

e e e e e e e

1-7

1-8 2-2

2-2

DU11-DA (M7822 Module) Mounted in DD11-A

2-3

DU11-DA (M7822 Module) Mounted in DD11-B

2-3

Current Mode Configuration (DU11-EA) Using DD11-B Mounting Panel

2-5

DU11-EA (M7822 Module and DF11-G Converter) Mounted in DD11-B

2-5

2-6

BCO5C-25 Cable Harness Used to Connect DU11-DA to Bell 201 Modem

2-6

2-7

BCO1W-25 Cable Harness Used to Connect DU11-DA to Bell 303 Modem

2-7

2-8

DUI1 to Modem Connection

Modem Test Connection Installation

. . . . . . . . . .

e e e e e e e e e e e

2-8

. . . . . . . . . .. ...

0 i i

... .. ... .. ...,

2-8

3-1

Receiver Status Register (RXCSR)

. . . . . . . . .

3-2

Receiver Data Buffer (RXDBUF)

. . . . . . . . . . o

e e e

3-2

et e

3-5

e e e e

3-7

. ..

3-9

Parameter Status Register (PARCSR)

. . .

3-4

Transmitter Status Register (TXCSR)

. . ... ... ... ... ... ... e

3-5

Transmitter Data Buffer (TXDBUF)

3-6

. . . .. . . . . . . ...

TABLES

Table No.

Title

1-1

Representative Message Codes

1-2

Computer Communications Applications

. . . . . . . . . . . . . . .

. . . . .. e

2-1

Jumper Assignments

3-1

DUI11 Register Address Assignments

3-2

Receiver Status Register Bit Description

3-3

Receiver Data Buffer Bit Description

Parameter Status Register Bit Description

3-5

Transmitter Status Register Bit Description

3-6

Transmitter Data Buffer Bit Description .

e e e e e e e

e e e e e e

. . . ... ... ...

. . . . . . . . . . . . L0000
e
. . . . . . . . . . . . . ... .

. . .

.
-------------------------

-------------------------

6731-1

DU11 Programmable Synchfonous Interface

CHAPTER 1
INTRODUCTION

1.1

SCOPE

If, instead of using one binary digit for our character, we

This manual provides a complete description of the DU11
Line Interface, including installation and programming. The
level of discussion assumes that the reader is familiar with

choice for a two-bit code is four: 00, 01, 10, or 11. If we

basic digital computer theory.

choose a three-bit code, our choice is eight:* 000, 001, 010,

use two, we have more characters to choose from. Our

choice for a one-bit code was limited to two: O or 1. Qur

011, 100, 101, 110, and 111. It can
be shown that for a

This chapter contains introductory information. It includes

code with a character makeup of n bits, the number of

techniques and

“characters available will be 2". In communications parlance,

systems, a general description of the DUl1, a physical

instead of calling these codes one-bit codes, two-bit codes,

description

of data

communication

description of the DUI1, DUI11 specifications, and an

etc., they are called one-level codes, two-level codes, etc.

explanation of engineering drawing conventions.

Although any arbitrary meaning can be assigned to a code
character, it is more practical for the majority of operations

to let the characters represent numbers, punctuation marks,

1.2

DATA

COMMUNICATION

SYSTEMS

1.2.1

TECHNIQUES

AND

spaces, and letters of the alphabet. In addition to these,
some special codes use characters for other meanings.

Data Communication Techniques

There are several techniques used for the transfer of data

1.2.1.2

communication signals. Each has its particular advantages

code characters, it is necessary to arrange their elements
in

and disadvantages.

Pulse Code Transmission
— In order to transmit

a way that will allow their reception without uncertainty.
There are several techniques by which this may be done;

1.2.1.1

Pulse

Coding
— Standard

data

communication

messages are sent in some form of pulse code. There are

these techniques fall into two broad categories: serial data
transmission and parallel data transmission.

several varieties of pulsed codes used in the transferral of
data in digital form. Binary signals, by their very nature, are

Because the DUI11 is a serial communication interface, only

natural elements for digital data codes. Such codes are said

serial data transmission techniques will be discussed.

to be in ‘“‘binary format.”
There are

two basic techniques of serial data transmis-

A formatted binary code can represent different symbols

sion: asynchronous

only

allowing sufficient binary elements for each

niques as well as a third, isochronous, will be discussed in

If we

the following paragraphs.

symbol.

think

of one binary digit (or “bit”)

and

synchronous.

These

two

tech-

representing each symbol, we have only two choices: one
symbol represented by the ‘“on” state, the other repre-

sented by the “off” state. With such an arrangement, we

1.2.1.2.1

could let the “on” or one state represent “no” and the
“off” or zero state represent “‘yeés.” While it would be

nique enables data to be transferred as it becomes available.

difficult with such an

Asynchronous Serial Transmission — This tech-

This is possible by framing each data character with a begin

arrangement, we could convey

signal (START bit) and an end signal (STOP bit), so that

messages of a very limited nature from a remote station

the equipment receiving the data (the interface receiver)

(such as the answer to “Is the temperature at your station

knows when a data character is being presented on the

over 70° F?”).

communication line and when the line is inactive.

1-1

1) =—————
(LINE=
DATA

(LINE=0)

HP__A

{

LSB

s
e

—— |

[

BITS

STOP

DATA BITS
BIT

START

11-2233

Figure 1-1

Asynchronous Technique Format

~ Hence, each character consists of three parts: a START bit,
the data bits, and a STOP bit (Figure 1-1). A START bit is
a line state (usually a zero) that lasts for 1 bit time. The
data bits represent the actual binary character being
transferred. In many applications the characters are 8 bits
long with the least significant bit being sent out and

received first. A STOP bit is a line state (usually a one) that

The disadvantages of the asynchronous serial data trans-

mission technique are:

lasts for 1, 1.42, or 2 bit times; it indicates that character
transmission is complete. The STOP bit enables the
interface receiver to check synchronization after each

is not received
character transmission. If the STOP bit
immediately
line
the
on
presented
not
properly, i.e., it is
considered
is
received
character
the
bit,
after the last data
necessary.
is
erroneous and re-transmission

Clocking for the interface transmitter and interface receiver

during

asynchronous transmission

provided

two

different sources that are asynchronous to one another. The
transmitter clock is enabled when data is available for
transmission and clocks the character onto the line. The

receiver clock is enabled when a START bit is detected on
the line and samples the data bits as they are presented on

Separate timing required for both transmitter
and receiver.

Distortion
depends

sensitive
on

because

incoming

signal

the

receiver

sequences

sequences will affect the reliability with which

the character is assembled.
c.

Speed limited because a reasonable amount of
margin between characters must be built in to
accommodate distortion.

Inefficient because at least 10 bit times are

required to send 8 bits of data. If a 2 bit time
STOP bit is used, it takes

bit times to

transfer 8 bits of data.

1.2.1.2.2 Synéhronous Serial Transmission — This tech-

complete

character and a STOP bit are received (the receiver must

is preceded on the line by a synchronizing code. When the

know the number of bits per character), the receiver clock

interface receiver recognizes this code (henceforth referred

counts

the

character

bits

received. When

is disabled until the next START bit is detected.

(

become synchronized. Any distortion in these

nique does not use START and STOP bits to accomplish
-synchronization. Instead, the entire block of data (message)

the line. The receiver is also equipped with a counter that

to as sync characters), it locks in and, using a counter,

assembles the data characters which follow. Hence, as in the
asynchronous

The asynchronous serial data transmission technique has
the following advantages:

technique,

the

receiver

must know

the

number of bits per character.
This technique requires that the clocking for the interface
transmitter and interface receiver be provided by a common

Can be generated easily by electromechanical
:
®
~equipment (e.g., TeletypeTM keyboard).

clock source. The clock signal is provided to the transmitter

Can be used easily to drive mechanical equip-

transmitter, the clock signal serves to clock the data onto

ment (e.g., Teletype printer).

Characters can be sent asynchronously (as they
become available) because each character has its
own synchronizing information.

and receiver on lines separate from the data line. At the

the line. At the receiver, the clock signal gates the data in.
Figure 1-2 illustrates the timing for a synchronous commu-

nication system using modems.

®feletype is a registered trademark of Telety
pe Corporation.

|<-.| { BIT TIME
MODEM

CLOCK

DATA

LS8

{

le——— SYNC CHARACTER

OhOrL]Ofi

DATA

CHARACTER ——=i

11-2234

Figure 1-2 Synchronous Format |
C.

As shown in Figure 1-2, the modem provides the clock, the

The

common-carrier

equipment required

transmitter presents the data to the line on the positive

accommodate this mode of operation is more

going edge of the clock and the receiver samples the data on

expensive

the negative going edge. If the transmitter pauses at any

asynchronous modes of operation.

than the

equipment required

for

time and fails to inhibit the clock, the receiver will continue
to

sample

the

line,

synchronization

lost

and

the

The advantages of the synchronous serial data transmission
technique are:
a.

transmit

nique is essentially the transmission of asynchronous data
over a synchronous modem. Character synchronization is:

Modem timing sources can be used for both

‘achieved via START and STOP bits;a common timing.
source is used for both the transmitter and receiver.

Interface receiver does not require clock-

The isochronous technique does have advantages over the

synchronizing logic as the asynchronous tech-

asynchronous technique. Clocking for isochronous opera-

nique does.
c.

equipment cannot

1.2.1.2.3 Isochronous' Serial Trénsmission — This tech-

transmitter and receiver.

Mechanical

receive this format directly.

remainder of the message will be erroneous.

tions emanates from the modems and is synchronous to the

data;

Highly efficient because there are no bit times

hence,

the

receiver

does

not

require

clock-

synchronizing logic and distortion sensitivity is low making

wasted with the use of START and STOP bits.

higher speeds possible.

All bits on the line are data, with the exception

of the sync characters at the beginning of the

bit stream.
d.

1.2.2

Low distortion sensitivity because the timing is

1.2.2.1

provided along with the data.

demodulators (modems) have permitted a higher rate of

Higher speeds are achievable because of the low

grade facility. The nature of these transmission techniques

has also resulted in higher efficiency by eliminating the
need for synchronizing information with every character.

The disadvantages of the synchronous serial data transmission technique are:

The logic design of interfaces to a synchronous modem is

Characters must be sent synchronously, not

considerably easier than the design of an asynchronous

asynchronously (asynchronous transmission is

interface because there is no need for bit synchronization

and sampling hardware. Most synchronous modems supply

desirable for most real time and mechanical

all the timing necessary to receive each bit as it is made

applications).
b.

Synchronous Systems— Synchronous modulator-

data transmission than asynchronous modems over a voice

distortion sensitivity.

Data Communication Systems

available from the modem. The difficulty in designing a

One bit time added to or missing from the

synchronous modem interface is to design the capability of

data-bit stream can cause the entire message to

communicating in the message formats used in synchronous

be faulty.

communications.
1-3

Table 1-1

Representative Message Codes

Character

Meaning

|
|

Function

SYN

Synchronizing signal

SOH

Start of heading signal

Precedes block message heading characters

Establish character framing

STX

Start of text signal

Precedes block of text characters

ETX

End of text signal

Terminates a block of characters started with STX

ACK

Acknowledge signal

*Affirmative acknowledgment of message received

NAK

Negative acknowledge signal

*Negative acknowledgment of message received

*ACK and NAK are sent by the station that received the message to the station that originated the message.

It is not the purpose of this manual to discuss the format

for synchronous communication in detail. However, a brief

description of these formats is outlined below to facilitate

Idle Line

the reader’s understanding of synchronous interface design.

]

only bit recovery timing, there must be a way to establish

character framing and message framing. This is accom-

SYN

plished by using codes (usually ASCII) that are assigned for

SYN

synchronous message formatting purposes. Representative

ACK

message codes are 11sted in Table 1-1.

SYN

A typical message that might be sent between two dewces

(a terminal and a processor) follows.

SYN

SOH

To Terminal
No. 4

Terminal To Processor
-

SYN

SOH

STX

Balance is

User Terminal

N4
I

$100

SYN

o
LRC (check character)

STX
|

Req. Balance

of Account
No. 14325
'

LRC (check character)
-

|
-

~ Idle Line

Terminal To Processor

|
|

SYN
SYN

SYN

Idle Line

v
1-4

Because the synchronous transmission technique provides

Processor To Terminal

1.2.2.2 Computer Application — Electronic computers are

often connected into communication systems to help

version and is completely contained on the M7822 module.
The basic version is compatible with the Bell 201 synchro-

transmit and process digital data. By using computer

nous modem or equivalent. Model DU11-EA is simply the

over one voice grade facility, significant improvements can
be made in the efficiency of a data communication system.
Since most long-range communication systems are

DU11-EA version consists of the basic M7822 module plus

systems to concentrate data from many Jow-speed terminals

connected through common carrier facilities, a communication system using a computer should be interfaced to the
correct type facility. There are two basic types of common
carrier facilities to which computers must be interfaced: asynchronous serial and synchronous serial. We have

already pointed out the advantages and disadvantages of

these two types of facilities. Based on these advantages and
disadvantages, Table 1-2 shows typical speeds and applications of these two techniques.

As shown in Table 1-2, there are three basic communication

applications to be solved by the computer communications
|

engineer:

the DF11-G current mode converter. The DUI11-EA is
compatible with the Bell 303, wide band, synchronous
modem or equivalent. A typical communication system
using the DU11 is shown in Figure 1-3.

Interface operation is completely program controlled. The
mode of operation (synchronous or isochronous), character
if selected), parity
length (5, 6, 7, or 8 bits plus parity
enable and sense (odd or even), sync character configuration, and duplex mode (full or half) are all selected via
|

the program.

1.4 PHYSICAL DESCRIPTION

The DUI1 interface is completely contained on a single
M7822 Quad Integrated Circuit module (Figure 1-4). This

module can be mounted easily in the PDP-11 processor

Intercomputer communications.

small peripheral controller slot (exceptions noted in
Chapter 2) or in one of four slots in a DD11-A or DD11-B
|
peripheral mounting panel.

GENERAL DESCRIPTION

All DU11 operating power is provided by the mounting

Low speed terminal equipment, such as Teletypes.
|
Medium speed terminal equipment.

1.3

basic version adapted to current mode operation. The

The DU11 interface is a single line, program controlled,

double-buffered communication interface. It provides serial

to parallel and parallel to serial data conversion, EIA* to
TTL (transistor-transistor logic) and TTL to EIA voltage
level conversion and modem control for full or half duplex
communication systems.

The DU11 is compatible with all PDP-11 family computers

and is available in two models. Model DU11-DA is the basic

panel in which it is installed. The power is taken from the
mounting box power supply. For proper operation, the

module requires +5V @2.2 A,-15V@0.17 A,and +15 V
@ 0.07 A.

The mounting panel also connects the DU11 to the Unibus.
All Unibus input/output signals enter and leave the module

via the mounting panel pins. Refer to Chapter 2 for Unibus
“
to mounting panel connection.

- Table 1-2

- Computer Communications Applications

Asynchronous‘

Synchronous

keyboard printers and Teletypes.

Operations tend to be asynchronous at

0 to 300 baud

Electromechanical terminals such as

Medium

Unbuffered terminals such as paper

Buffered terminals such as displays,

and line printers.

configurations.

High

Not frequently used.

Intercomputer communications.

5000 baud and up

Speed
Low

300 to 3000 baud

tape readers and punches, card readers

*EIA — A standardized set of signal characteristics (time duration,
voltage, and current) specified by the Electronic Industries
Association.

these speeds.

buffered card readers, and line printer

COMMUNICATION FACILITIES

COMPUTER [TNTBUS

S DATA-

ERIAL [ | -\
BELL

201 0r [ 7
PATR olEQUIVALENT
Uit
INTERFACE
.

SERIAL

201oy feATA
EQUIVALENT

PARALLEL

DU11
INTERFACE

UNTBUS| COMPUTER

25f1

25f1t

11-2235

Figure 1-3

Major

DU11 components

are

also

Typical Communication System Using the DU11 Interface

labeled

Current mode operation (100K baud maximum) is possible

Figure

1-4: the rocker switches which are used to select the -

only with the DU11-EA. Current mode speed is limited by

interface Unibus address, the priority plug which deter-

DU11 logic.

mines the bus request (BR) priority level of the interface
(BRS

plug

normally

installed at

factory),

the

SAR

(receiver) and SAT (transmitter) chips, and jumpers W2,
W4—-W6, and W9—-W16 (a complete description of the
jumpers is provided in Paragraph 2.1.4).
1.5

Even though the DUI11 can receive and transmit information at such a high rate, it may, in most cases, be
impractical.

Since the

service of the data buffers relies

“solely on the program, little time if any would be left for
- other events. This problem would be compounded if the

SPECIF ICATIONS

interface were operating in full duplex mode.

Environmental, electrical, and performance specifications
for the DU11 are contained in the following paragraphs.

1.5.1

1.5.3.2

Environmental

Ambient temperature

Baud

Rates

for

Isochronous

Communica-

tions— EIA/CCITT baud rate (10K baud maximum) is

limited by. data set interface level converters. Current mode

10° to 50° C (50° to 122° F)

operation baud rate (100K baud maximum) is limited by
DUI11

Relative humidity

logic.

20% to 95% (without condensation)

1.6 ENGINEERING DRAWINGS

1.5.2 Electrical

A complete set of engineering drawings entitled DU11 Line
Interface,

DC voltage requirements

Engineering Drawings is provided with each

+5V@22A

interface. The general logic symbols used on these drawings

-15V@0.17 A

are described in the DEC Logic Handbook, 1972. Specific
symbols and conventions are also included in the PDP-11

+15V@0.07 A

system manuals. The following paragraphs describe the
Electrical Characteristics
Electrical

signal nomenclature conventions used in the drawing set.

characteristics

of this interface meet EIA

Basic Signal Names

standard RS-232C and PDP-11 Unibus Interface specifi-

1.6.1

cations.

Signal names in the DUI1 print set are in the following
basic form:

1.5.3

Performance

The following paragraphs discuss the baud rate limitations

SOURCE

SIGNAL NAME

POLARITY

of the DU11 and related program response time.

'SOURCE indicates the drawing number of the print from
1.5.3.1

Baud

Rates

for

Synchronous

Communica-

which the signal originates. The drawing number of a print
is located in the lower right-hand corner of the print title
block (D1, D2, D3, D4, D5, and D6).

tions— EIA/CCITT* baud rate (10K baud maximum) is
limited by modem and data set interface level converters.

*CCITT — The Consultive Committee International Telegraph and

Telephone is an advisory committee established under the United
Nations to recommend worldwide standards.

1-6

ROCKER

W13

SWITCHES

W12

PRIORITY

RECEIVER

TRANSMITTER

CHIP

W11

W10

W14

W16

PLUG
6843-2

Figure 14

DUI11 Major Components

Interface signals fed to or received from the Bell 303

SIGNAL NAME is the proper name of the signal. The
names used on the print set are also used in this manual for
correlation between the two.

modem via the mounting panel backpanel wiring and
DF11-G level converter are preceded by the M7822 module
pin number:

POLARITY is either H or L to indicate the voltage level of

AF1D6-DTR (1) H

the signal: H means +3 V; L means ground.

~ 1.6.2 Flip-Flop Signal Names
Flip-flop signal names add an extra dimension. Although

For example, the signal

flip-flops have only two outputs, four signal names are

DS- TX DONE H

~possible (Figure 1-5). The two real outputs are RX DONE

(1) H on pin 5 and RX DONE (0) H on pin 6. The two
additional outputs are simply the real outputs reidentified.

originates on sheet 5 of the engineering drawings and is
~ read, “When TX DONE is true, this signal is at +3 V.”

RX DONE (1) L is electrically the same as RX DONE (0)
H, and RX DONE (0) L is electrically the same as RX

DONE (1) H.
Unibus signal lines do not carry a SOURCE indicator. These
signal names represent a bidirectional wire-ORed bus; as a
tesult, multiple sources for a particular bus signal exist.
Each Unibus signal name is prefixed with the word BUS.

| 5 RX DONE (1) H

F/F

Interface signals' fed to or received from the Bell 201

—AC

modem via the Berg connector on the M7822 module are
preceded by the jack and pin number in parentheses:

RX DONE (1) L
&
|

S RX DONE (0) L.
6

—— RX

DONE (O) H

11-22386

(J1-DD) EIA DATA TERM RDY (This signal is
shown on engineering drawing D6.)

Figure 1-5 Flip-Flop Signal Names |

1-8

CHAPTER 2
INSTALLATION

2.1

INSTALLATION

Connect a wire between -A02N2 and CXXUI, .
where XX is to slot location of the M7822

2.1.1

module.

Mounting the DU11 in the Computer

There are two DUI1 1 installation configurations:
NOTE

The

standard

configuration,

which

the

J umper W16 must not be installed if the

DU11-DA interfaces with the Bell 201 syn-

- DUI11 is being mstalled in the DD11 B

chronous modem or equivalent.

The current mode configuration, in which the
DU11-EA interfaces with the Bell wide band

303 modem or equivalent.
2.1.1.1 Standard

Configuration
— In

mounting panel.

2112 Current Mode Configuration — In this configu‘ration, the DUI1-EA must be installed
in the DD11-B

mounting panel as shown in Figures 2-4 and 2-5.

this configuration,

the DUI1-DA can be mounted in the small peripheral
controller slot in the PDP-11/05, 10, 35, 40, 45, and 50
processors or in any one of four slots in the DD11-A or

The DD11-A mounting panel cannot be used in

“the current mode configuration because it will
not accommodate the DF11-G level converter.

DD11-B peripheral mounting panels (Figure 2-1). The

2.1.2 Installing the Modem Cable Harness

DD11-A mounting panel (Figure 2-2) is used in the
PDP-11/15 and 20 computers, while the DD11-B (Figure

A different cable is required to connect the DU11 to the
Bell 201 modem than to the Bell 303 modem. The

2-3) is used in the PDP-11/05, 10, 35, 40, 45, and 50
computers.

NOTE

The DU11-DA cannot be mountedin the small

BCO5C-25 cable harness (Figure 2-6) is used for the
DUI11-DA configuration; the BCOIW-25 cable harness
-

(Figure 2-7) is used for the DU11-EA configuration.

peripheral controller slotin the PDP- 11 /15 and
20 processors.

DD11-A and DD11-B mounting frequiréments are_Soméwhét

different. When using the DD11-B mounting panel, the

To install the cables, refer to Figure 2-8 and proceed as
-

when using the DD11-A, jumper W16 (engineering drawmg” |
D1) and module G8000 must also be installed. Jumper W16

Berg

Connect a wire between AO3V?2 and AQ2V?2.

the

DUIl1l

the

module

DF11-G

Align the Cinch connector (DU11-DA configuconfiguration) to the receptacle located on the
rear of the modem.

Install the G8000 module in slot AO2 of the
DD11-A.

configuration)

ration) or the Burndy connector (DU11-EA

proceed as follows:

connector

connector module (DU11-EA configuration).

converts the full-wave rectified +8 V/rms mounting panel
the EIA level converters. To install the G8000 module,

connector name and pin number markings are

~visible and mate it fully and squarely with the
(DU11-DA

bypasses a voltage dropping.résistdr"and the G8000 module

input signal to a positive dc voltage which is used to drive

Position the Berg connector such that the

DUI11 is simply installed in the mounting panel; however,

follows: -

Mate the connector and tighten the two hold~down screws using a screwdriver.

Lindg
3T1NAOI
(€28LIN)N

(V-1104)

SDLHO3IgNNHOODL)DIIWNIAOODW
ALINVILHNGOCD

2-2

T1NAON (L2LDO)
v-€v89

SECTIONS
A

(SEENOTE 2)

/
////////////////////

SLOTS

'
| 3

POWER

G727

(SEE NOTE 3)

erem

MOD»UVL'_.l»E SIDE VIEW |
- *GRANT Continuity Module (G727) must be installed in each slot that.does 5hot reéeiv"e an inter'falc‘:e It‘)g’ic' module.

NOTES:

1. Can be mou_nte& ifi slots 1,2, 3,or 4

Can be M920 or BC11-A

‘

3. Can be M920, BC11-A or M930

Figufe 2-2 'DU_l 1-DA (M7822 Module) Mduntévd*in DD11-A .
R

',“AF

(%EIEB%%TOEUQ)

)

G727§

- S T I /%/ / / / / / / / f,/,/,f,/,”, , ////
B

) "SECTIONSV'

B -

(ggllzBNUOST:iNé')‘ |

. !
2

SLOTS

]

// //M7822QUAD MODULE(/;40751

‘

6?27'

G727x . |

AR
MODULE

SIDE

VIEW
11-2238

*Grant Continuity Module (G727) must be installed in each slot that does not receive an interface logic module.

NOTES:
1.

Can be mounted inslots 1,2, 3,0r 4

2. Can be M920 or BC11-A
3.

Can be M920, BC11-A or M930

Figure 2-3

DUI11-DA (M7822 Module) Mounted in DD11-B

2-3

d3143ANOD
3T1NAON

S1O3INNOJ)01W3AOI
dOLJ3INNQD
ITNAON
dOL1LI3IN OD
O-Ld4da

BRELER

ALINILNOD

SECTIONS

Core

(NOTEZ‘)‘

(NOTE 2)

////////////////////////7/////

MODULE

SIDE

VIEW
11-2239

*Grant Continuity Module (G727) must be installed in each slot that does not receive an interface logic module.

PWONS

' NOTES:
Can only be mounted in slots 2 or 3
The DF11-G connector and converter must be mountedin the same slot as the M7822 module

Can be M920 or BC11-A
Can be M920, BC11-A or M930

Figure 2-5 DU11-EA (M7822 Module and DF11-G Converter) Mounted in DD11-B

2.1.3 Unibus and Interrupt Vector Address Assignments

The interrupt vector addresses are also floating and are

The Unibus and interrupt vector addresses must be deter-

established at the factory in accordance with the vector

mined prior to operating the

DU11. The Unibus address.is

addressing

scheme

switch selectable; the interrupt vector addresses are jumper

necessary

to change the vector address, simply change

selectable (Figure 14 for physical location).

described

Appendix

If. it

jumpers W9—-WI14 as required. Jumpers are cut to obtain a

logical zero. Jumpers W9—W14 are located in the interrupt

The Unibus address (also referred to as the device address)

control

logic (engineering drawing D4). These jumpers

is controlled by ten rocker switches located in the address
selection and mode control logic. The position of these

control vector address bits 08—03; hence, vector addresses

switches determines the required address state (0 or 1) of
bus address bits 12—03. If a rocker switch is set to ON, the
switch contacts are closed and an address state of O is

software requires that the vector address fall within the

can be generated within the range of 000 to 774; however,

floatmg address range of 300 to 777.

required on the related address bit to address the DUI11.

Hence, electrically the DU11 can have any device address
within the range of 760000 to 777777; however, Digital

NOTE

If a vector address is selected which falls

Equipment Corporation software requires that the device
address fall within the floating address range of 760010 to

outside the floating address range, the software
must be modified accordingly.

763776. Refer to Appendix B for a complete dlscussmn of
DU11 address asmgnments
2.1.4
NOTE

device

Jumper Assignments

Jumpers are used at various points in the DU11 circuitry to

address is selected which

falls

increase flexibility and to meet the floating vector address

outside the floating address range, the software

requirement described in Appendix B. For a complete

must be modified accordingly.

description of the DU11 jumpers, refer to Table 2-1.

2-5

25 FT HARNESS

MALE
-

CINCH

CONNECTOR

(DB-51226-1)

/ N

(CONNECTS TO

TO
(CONNECTS

FEMALE
BERG

- DU11 MODULE)

CONNECTOR

MODEM)

- (DEC NO. 1209941)

6808-3

- Figuf_e _2-6 BCOSC-Z-S. C‘abl,e.Harn.ess Used to Connect DU11-DA to
-

Bell 201 Modem -

~ The priority level is determined by the pnonty plug located -

'2 1.5 Prlorlty Assngnment

2.2 INITIAL TESTING
|
‘The DU11 must be tested prior to placing the unit into

on the DU11 module. The DU11 normally has a priority -

‘operation.

For

initial

test

procedures,

refer

level of BRS. However, the priority may be changed by

_engineering specification, A-SP-DU11-0-4, which is pro-

simply replacing the BRS plug with a plug wired for a

vided with each DU11 delivered.

| dlfferent pnonty level.
NOTE
~

Before runmng diagnostics on interface model
DU11-DA,

NOTE
|
|
If the priority level is changed, the software
-

must be modlfied accordmgly

disconnect

the

modem

cable

(BCO5C-25) from the rear of the modem and
_install the modem test connector as shown in

Figure 2-9.

the

——

TM~

25 ft

HARNESS

CONNECTS

CONNECTS TO

TO DU11

MODEM

MODULE

MALE

SURNDY
CONNECTOR

FEMALE
CONNECTOR

(DEC NO. 1209941)

6843-1

* Figure 2.7 BCO1W-25 Cable Harness Used
to Connect DU11-EA to
|

- Bell 303 Modem

2.7

MALE

BERG CONNECTOR

MALE

BCOSC-25

DU1I1

M7822

CINCH

CONNECTOR

/~ FEMALE BERG CONNECTOR \

BELL 201 MODEM

—]

CABLE
-

(REAR)

MODULE

a. DUI1-DA

FEMALE

CINCH

CONNECTOR

CONFIGURATION

MALE

FEMALE

BERG

BURNDY

CONNECTOR

BELL

*j::]

303 MODEM

e+«) (REAR)

BCO1W -25 CABLE
MALE

BERG

CONNECTOR
FEMALE BURNDY CONNECTOR

DFi1-G

CONNECTOR
- MODULE

b. DUI1—EA

CONFIGURATION
11-2333

Figure 2-8

DU11 to Modem Connection

MODEM

——

CABLE

(BCO5C-25)

CINCH

CONNECTOR
—

INSTALL CINCH
CONNECTOR
|

HERE

MODEM

TEST

—

CONNECTOR

6808-2

Figure 2-9

Modem Test Connection Installation

Table 2-1
Jumper Assignments

Jumper No. and Location

Normal Configuration

Function

w2/D5

Removed

This jumper may be installed to enable the receiver to

synchronize internally upon receiving just one sync

character, thereby negating the normal requirement of
receiving two contiguous sync characters to achieve
synchronization in the internal synchronous mode.
W4/D6

This jumper may be removed to disable CLR OPT L
(Clear Option), thereby preventing clearing of bits 03,
02, and 01 in the RXCSR (see Chapter 3 for bit

Installed

descriptions).
W5, W6/D6

These jumpers may be removed to disconnect the

Installed

secondary data channel between the modem and the

DU11. Removed at customers request.

W9-W14/D4

Floating

W15/D4

Installed

W16/D1

Removed

These jumpers control the receiver and transmitter

interrupt vector address (Paragraph 2.1 .3) bits:
Jumper

Address Bit

BUS D03

Wi0

BUS D04

Wil

BUS D05

W12

BUS D06

W13

BUS D07

Wwi4

BUS D08

This jumper may be removed to inhibit the BUS NPR L

input to the interrupt control logic. (Removed only if
PDP-11/20 processor is used without KH option.)

This jumper must be installed if the DU11 is mounted in
a

DDI11-A

2.1.1.1).

2-9

peripheral

mounting

panel

(Paragraph

3
CHAPTER

DEVICE REGISTERS

AND INTERRUPT REQUESTS
3.1

SCOPE

This chapter provides a complete description of the DU11
device registers and the interrupt requests employed to

facilitate the programmer’s understanding of the purpose of
each register relative to interface operation and to simplify
software preparation.

service those registers.

3.2.2.1

3.2

DEVICE REGISTERS

All software control of the DU11 is performed by means of
five device registers. These registers have been assigned bus
addresses and can be read or loaded (with the exceptions
noted) using any PDP-11 instruction referring to their
addresses. Address assignments can be changed via the
rocker switches to correspond to any address within the

the

interface; to communicate

interface

status, requests, and supervisory data to the
modem; and to monitor status and supervisory
data inputs from the modem.

RXDBUF — monitored (read only) to detect
interface RCVR status flags and RCVR parallel

data outputs.

The five device registers and associated DU11 addresses are
|

listed in Table 3-1.

RXCSR
— programmed and monitored (read/
write) to control the RCVR (receiver) portion

floating address range of 160010 to 163776.

3.2.1

Title Assignments — Register titles and functions

are listed below:

PARCSR — programmed

(write

only)

establish the overall operating parameters of the
DUI11, i.e., the mode of operation (synchro-

3.2.2 Register Title and Bit Assignments

Each of the five device registers plays a specific role in
controlling and monitoring DU11 operation. Register titles,

bit titles, and read/write capability labeling are intended to

nous or isochronous), word length (5, 6, 7, or 8
bits plus parity), parity (enabled or disabled),
parity sense (odd or even), and sync character
configuration.

Table 3-1

DU11 Register Address Assignments

* Mnemonic

Address

Program Capability

Receiver Status Register
Receiver Data Buffer

RXCSR
RXDBUF

16XXX0
16XXX?2

Read/Write
Read Only

Parameter Status Register

Transmitter Status Register
Transmitter Data Buffer

PARCSR

TXCSR

TXDBUF

16XXX?2

Write Only

16XXX6

Write Only

16XXX4

Read/Write

XXX = Selected in accordance with floating device address scheme described in Appendix B.

SR and monitored (read/
— programmed
TXC
write) to control the XMTR (transmitter)

The following figures and tables describe register content.
Figures 3-1 through 3-5 illustrate the register formats.
Tables 3-2 through 3-6 list bit descriptions.

portion of the interface, to control the resetting
and initialization of the interface, and to
control and monitor the maintenance mode

The mnemonic INIT is used frequently in the following
tables and refers to the initialization signal generated by the
processor. The processor will issue an INIT signal for any

operation of the interface.

TXDBUF — programmed (write only) to provide parallel data to the interface XMTR for
serial transmission to the modem.

one of the following conditions:

3.2.2.2 Bit Assignments — The bit names indicate the

or “write-only” are always read as 0. In the same respect,

During a power fail sequence, INIT is asserted when power
is going down and again when power is coming up.

bits have no effect on the bit.

CLR

[car-|

Rec | SEC

[DATA|sTrip|

mrx |

|PATA|

scw | SEC | REQ | DATA | ot

R/W

SCEHT RING SRD RIER| ACT DRAETCA Sg: SYNC | DONE [INTEB IEJE’EB SYNC gx.}; g% TRESYM USED
R

R/W

11-2244

Figure 3-1

Receiver Status Register (RXCSR)

Table 3-2

Receiver Status Register Bit Description

Bit
15

Name
DATSETCH

Description
When set, this bit indicates a modem status change.

(Data Set Change)

This bit is set by a transition of any of the following lines:
®

Ring

® (lear To Send
®

(arrier

Secondary Received Data

® Data Set Ready

If bit 05 of this register is set, the setting of this bit- will cause
a RCVR interrupt.

Read-only bit; cleared by INIT, Master Reset, and the DTI
SEL 0 (RXCSR read strobe).

RING
(Ring)

(]

The power fail sequence occurs.

attempts to program the “not used” bits or “read-only”

A programmed RESET instruction is processed.
The processor START switch is pressed.

a.
- b.

function of the bit. The bits that are defined as “not used”

DATA

(

This bit reflects the state of the modem Ring line. When set,
this bit indicates that a Ring signal is being received from the
modem. Read-only bit.

3-2

(

Table 3-2 (Cont)

Receiver Status Register Bit Description
Description

Name

Bit

CLR TO SD

(Clear to Send)

This bit reflects the state of the Clear to Send line from the
modem. When set, this bit indicates that the modem is on and
ready to accept data from the interface for transmission.
Read-only bit.

CARRIER

(Carrier)
REC ACT

(Receiver Active)

- This bit reflects the state of the modem carrier. When set, this
bit indicates the Carrier is up. Read-only bit.
When the internal synchronous mode is selected, this bit is set
when the proper number of contiguous sync characters (either

1 or 2, normally set for 2) have been received. If external

synchronous or isochronous mode is selected, this bit follows
the state of the Search Sync bit (bit 04 of this register). See

Paragraph 4.3 for RCVR synchronization information.

Read-only; cleared by INIT, Master Reset, and SCH SYNC (1)
H (Search Sync) making 1 to O transition.
10

SEC RCV DAT

This bit reflects the state of the Secondary Receive Data line

(Secondary Receive Data)

from the modem.

This bit provides a receive channel for supervisory data from
o
the modem to the processor. Read-only bit.
DAT SET RDY

(Data Set Ready)

This bit reflects the state of the Data Set Ready line from the
modem. When set, this bit indicates that the modem is
powered up and ready to transmit and receive data. Read-only
bit.

STRIP SYNC

This bit determines whether sync characters received from the

(Strip Sync)

modem are to be presented to the program for reading. When

this bit is set, receive characters that match the contents of the
Sync register do not cause a RCVR interrupt provided no
errors are detected, i.e., bit 15 of the RXDBUF is clear.

Read/write bit; cleared by INIT and Master Reset.
07

RX DONE

(Receiver Done)

This bit is set when synchronization has been achieved and a
character has been loaded into the RXDBUF,

provided the

STRIP SYNC bit is not set. If the STRIP SYNC bit
is set and

the received character is a sync character without errors, i.e.,
bit 15 of the RXDBUF is clear, this bit will not be set.
When

set,

this bit

will

cause a RCVR interrupt request

provided bit 06 of this register is set.

Read-only bit; cleared by INIT, Master Reset, and the DTI
SEL 2 (RXDBUF read strobe).

3-3

Table 3-24 (Coht’) |
Receiver Status Register Bit Description

- Bit

Name

‘Description

RX INTEB

- 'When set, allows a RCVR interrupt request to be generated

(Receiver Interrupt Enable)

when the RX DONE bit is set.

' Read/wr’ite bit; cleared by INIT and Master Reset.

DAT SET INTEB

(Data Set Interrupt Enable)

When set,' allows a RCVR interrupt request to be generated
when the DAT SET CH bit is set.

Read/writé bit; cleared by INIT of Master Reset.
04

- SCH SYNC

When set in the internal synchrono_u's”mode, enables the RCVR

(Search Sync)

synchronization logic and causes the RCVR to start comparing

incoming data bits to the contents of the Sync register in an
attempt to recognize a sync character

When set in the isochronous mode, enables thé RX DONE flag
generation logic.

When set in ther external synchronous mode, enables the RX
DONE flag generation logic and causes the RCVR to start
framingincoming characters

Read/write bit; cleared by INIT and Master Reset.

SEC XMIT

~ This bit reflects the state of the Secondary Transmit Data line

(Secondary Transmit Data) |

the

modem. This bit provides a transmit channel for

- supervisory data from the modem to the processor.

Read/write bit; optionally cleared b'y INIT or Master Reset.
02

REQ TO SD

When set, this bit causes the Request to Send line to the

(Request to Send)
|

modem to be asserted. The Request to Send line is a control
-

lead to the modem. This line must be asserted before the

interface can transmit data to the modem.

Read/write bit; optionally cleared by INIT and Master Reset.
01

DATA TERM RDY

When set, this bit indicates the interface is powered up,

(Data Terminal Ready)

programmed, and ready to receive data from the modem.

Setting this bit causes the Data Terminal Ready line to the
modem to be asserted. The Data Terminal Ready line is a

control lead for the modem communication channel. When
asserted, it permits the mterface to be connected to the
channel.

Read/write bit; optionally cleared by INIT and Master Reset.

|OVRN|

{{ «—————»
08

FRM | PAR

07 +——

+ 00

¢']

READ ONLY

|,<

'RCVR DATA

NOT USED

err | err | ERR | ERR

11-2240

Figure 3-2 Receiver Data Buffer (RXDBUF)

Table 3-3

~ Description

Name

Bit

RX ERR

Receiver Data Buffer Bit Description

(Receiver Error)

This bit is set whenever one of the three receiver error bits is set (logical
OR of bits 14, 13, and 12).

Read-only bit; cleared only when bits 14, 13, and 12 are cleared.

OVRN ERR
(Overrun Error)

When set, this bit indicates that the processor has failed to service the RX
DONE flag within the time required to load another character into the
RXDBUEF, i.e., (1/baud rate) X (bits per character) seconds. Hence, the

er (lost).
was over-written
previous charact

Read-only bit; cleared by INIT, Master Reset, and DTI SEL 2 (RXDBUF
read strobe).

FRM ERR
(Framing Error)

When set, indicates that character received was not followed by a valid
STOP bit. This error only occurs in the isochronous mode of operation.
Read-only bit; cleared by INIT, Master Reset, and DTI SEL 2.

PAR ERR' -

(Parity Error)

When set,' indicates that the parity of the received character does not agree

with the parity programmed (odd or even). If parity is not programmed,
this bit is always cleared.

Read-only bit; cleared by INIT, Master Reset, and DTI SEL 2.

07-00

RCVR DATA

(Receiver Data)
|
|

This register holds the received character for transfer to the program. The

buffer is right justified for 5, 6, 7, or 8 bits. If parity is received it is also
loaded into the -buffer at the next vacant higher order bit position.

Therefore, if a 5-bit character plus parity is framed by the RCVR, the
parity bit would be loaded into bit position 05 in the RXDBUF and

presented to the program for reading. If an 8-bit character plus parity is
bit would not be presented to the program for reading.
framed, the parity

Read-only buffer; cannot be cleared, INIT or Master Reset sets the buffer
to all ones.

3-5

14
_—

07 -

» 00
-

PAR

EncTH | PR | sen |
SEL

SYNC REGISTER

SEL

le—

WRITE ONLY

—

=l]

11-2241

Figure 3-3 Parameter Status Register (PARCSIR)

Table 3-4

Parameter Status Register Bit Description

Bit

Name

13 and 12

Description

MODE SEL

These bits control the mode of operation. Modes are selected as

“(Mode Select)

follows:

Bit 12

|
Mode
Internal Synchronous

‘Bit 13

External Synchronous

Isochronous

~ Any other mode select bit combinations will produce errors in
the interface.

Write-only bits.
11 and 10
|

WORD LEN SEL
(Word Length Select)

~ These bits control the length of characters received and
transmitted by interface. Word length (not including parity) is

selected as follows:

Bits per Character
|

Bit 11

Bit 10

Write-only bits.

- PARENB
(Parity Enable)
|
|

If this bit is set, parity will be generated by the XMTR and
checked by the RCVR. If character length is less than eight bits,
the parity bit is loaded into the RXDBUF for reading by the
program. If bad parity is detected at the RCVR, the parity error

flag is set (bit 12 of the RXDBUF).

- Write-only bit.

3-6

Table 3-4 (Cont)
Parameter Status Register Bit Description

Name

Description

- PAR SEN SEL
(Parity Sense Select)

When the Parity Enable bit (bit 09 of this register) is set, the
sense of the parity (odd or even) is controlled by this bit. When

Bit
08

this bit is set, even parity is generated by the XMTR and checked
for by the RCVR (the program does not have to provide a parity
bit to the XMTR). When this bit is cleared, odd parity is

generated and checked.
Write-only bit.

This register contains the sync character. The sync character is
used by the RCVR to detect received sync characters and thereby

Sync Register
|

07-00

achieve synchromzatlon

The sync character is used as a fill character by the XMTR when

operating in the synchronous mode. Fill characters are
transmitted when the program fails to provide characters to the
XMTR fasti enough to maintain continuous transmission, i.e.,

. (1/baud rate) X (bits per character) seconds - 1/2 (bit time).

)

15
.

|MAINT|

| MS

R/W

| MS |RX | NOT

|'MST | Tx

O06

HALF

| Tx | DNA

DNA |"oata | cx | o1 | 0o | Inp {usep | RsT |pone [InTEB|InTES| SEND | pup | NOTUSED |BREAK
R

R/W

11-2242

Figure 3-4 Transmitter Status Register (TXCSR)

Table 3-5
Transmitter Status Register Bit Description

Name

Description

- This bit is set by the XMTR when a fill character is

(Data Not Available)

transmitted. This applies only to the synchronous mode of

Bit

- DNA

operation and is caused by late program response toa TX
DONE interrupt request.

The processor response to TX DONE must be within
(1/baud

rate)
X (bits

per

character)

seconds- 1/2 (b1t

time). If not, the fill character is transmitted.
If bit 05 of this register is set, setting this bit causes an
XMTR interrupt request.

‘Read-only bit; cleared by INIT, Master Reset, and DTI SEL

4 (TXCSR read strobe).
3-7

Table 3-5 (Cont)
Transmitter Status Register Bit Description
Bit

Name

Description

MAINT DATA

This bit is used in the internal loop and external loop

(Maintenance Data)

maintenance modes by the diagnostic program to simulate

an input to the RCVR.

Read/write bit; cleared by INIT and Master Reset.

SS CLK

This bit is used in the internal loop and external loop

(Single Step Maintenance Clock)

maintenance modes by the diagnostic program to simulate
~

the XMTR and RCVR clocks.

Read/write bit; cleared by INIT or Master Reset.

12 and 11

MS01/MS00
(Maintenance Mode Select 01 & 00)
|

These bits are used to select the normal mode of operation
|

or one of three maintenance modes. Modes are selected as
|
|

follows:

Mode

Normal

Bit 12

Bit 11

Internal Maintenance Loop

External Maintenance Loop

System Test

Read/write bits; cleared by INIT and Master Reset.

RX INP

This bit monitors the RCVR input in the internal loop and

(Receiver Input)

external loop maintenance modes.
Read-only.

MSTRST

This bit is used to genera—te a CLR (Clear) pulse, which

(Master Reset)

initializes the registers and the XMTR and RCVR and

inhibits the BUS SSYN L (Slave Sync) signal.

Write-only.

TX DONE

This bit is set by INIT and Master Reset and when the first

(Transmitter Done)

bit of the character contained in the XMTR register is

placed on the XMTR output line. If bit 06 of this register is

set when this bit is set, an XMTR interrupt request is
generated.
Read-only bit; cleared by LD TXDBUF (TXDBUF load
strobe).

3-8

Table 3-5 (Cont)

Transmitter Status Register Bit Description

Descriptibn

- Name

Bit

TX INTEB

(Transmitter Interrupt Enable)

When set, this bit allows an XMTR interrupt requesf to be
generated by the TX DONE bit.

Read/write bit; cleared by INIT and Master Reset.

When »set, this bit allows a XMTR interrupt request to be

DNA INTEB

(Data Not Available Interrupt Enable) | generated by the DNA bit.

Read/write bit; cleared by INIT and Master Reset.

will
When set, this bit enables the XMTR and transmission
bit
This
TXDBUF.
the
into
loaded
is
character
a
when
start
If
transmitted.
is
message
entire
the
until
set
must remain
XMTR
the
in
currently
character
the
of
transmission
not,
register is completed and the XMTR will enter the idle

SEND

(Send)

state.

Read/write bit; cleared by INIT and Master Reset.

When this bit is set, operation will be in the half duplex

HALF DUP

mode. In this mode the RCVR is disabled whenever bit 04

(Half Duplex)

of this register is set.

by INIT and Master Reset..
Read/write bit; cleared

When this bit is set, the serial XMTR output is held in the

BREAK -

space (constant LOW) condition; otherwise, operation is

(Break)

normal. This bit is used by the diagnostic program in the
internal loop or external loop maintenance modes to inhibit
the XMTR output while inputting data to the RCVR via bit
14 of this register.

Read/write bit; cleared by INIT and Master Reset.

XMTR DATA

NOT USED

07 =

WRITE ONLY

]
>

11- 2243

Figure 3-5 Transmitter Data Buffer (TXDBUF)

3-9

Table 3-6

- Transmitter Data Buffer Bit Description

Bit
07-00

Descfipti-on

Name
XMTR DATA

(Transmitter Data)

This register is loaded by the program with the character to be
-

transmitted. Character length is from 5 to 8 bits. The character is
- right-hand justified. If a parlty bit is programmed it is generated by

the interface.
~ Write- only bits; an INIT or Master Reset places all ones in this
reglster

3.3

INTERRUPT REQUESTS

~The

cause a program interrupt, thereby causing the processor to

DUI1 ihterrupt

priority level is BRS.

However, the priority level can be changed by replacing the

The DU11 uses BR interrupts to gain control of the bus and
branch to a subroutine.

standard

- priority plug

The interface uses two interrupt vectors: one for the
RCVR section and one for the XMTR section. If simulta-

The DUI11 interrupt vector addresses are floating. Floating

~ vector addresses
are used for all options and are assigned

neous RCVR and XMTR interrupt requests occur, the

according to the scheme described in Appendix B. The

RCVR has priority.

vector addresses
can be changed via jumpers W9-W14 in

Both the XMTR and RCVR sections of the iritefrupt'

the interrupt control logic.

control logic handle. interrupt requests from two sources. A

XMTR interrupt request is generated by the setting of the

TX DONE bit or the DNA bit provided the TX INTEB and
the DNA INTEB bits are set.A RCVR interrupt request is -

NOTE

If the DU11 priority plug
or an interrupt vector

generated by setting the RX DONE bit or the DAT SET CH

address is changed, all DEC programs or other
software referring to the standard priority level

bit, provided the RX INTEB and DAT SET INTEB bits are

set.

changed.

3-10

interrupt

vector

addresses

must

also

CHAPTER 4
PROGRAMMING REQUIREMENTS

AND RECOMMENDATIONS

4.1

INTRODUCTION

4.2.3

Detecting the Last Character of the Message

To program the DUl1 in the most efficient manner, the

When it is necessary to know when the entire message has

programmer must understand fully the control signal and

been

timing requirements of the device. The following para-

follows:

graphs discuss DU11 operation from a programming point

transmitted,

of view and describe recommended programming methods.

the

DUll

may be

programmed as

|
Just prior to loading the last character of the

It is beyond the scope of this manual to provide detailed

message into the TXDBUF, clear the TX DONE

programming information. For more detailed information

INTEB bit and set the

programming

general,

refer

Software Programming Handbook,

the Paper-Tape

DEC-11-XPTSA-A-D,

and the individual program hstmgs

DNA INTEB bit.

When the last chéracfér_ is loaded into the

4.2

PROGRAMMING

THE

TRANSMITTER

SYNCHRONOUS MODE

THE

transmitter will transmit the sync character and
assert DNA, which causes an interrupt request.

4.2.1 Loading the PARCSR
Once the transmitter is initialized via the BUS INIT pulse or
MSTRST,

the PARCSR register must be

After the last character is transmitted, the

programmed

The DNA interrupt is notification to the
program

(loaded) to select the mode of operation (synchronous in

that

the

entire

message

has been

transmitted.

this case), character length, and parity. At this point the
Sync register will contain all ones.

4.2.4

Before any necessary

Transmitting Initial Sync Characters to Establish

handshaking is done with the modem, the program must

Synchronization

load the Sync register with the desired character. When the

The transmission of initial sync characters can be accomplished in one of two ways:

Sync register is loaded, the character will be used for both

XMTR and RCVR operation.
4.2.2

Enabling the Transmitter

The program may arrange its data buffer such

“that the required number of sync characters

Once handshaking is complete, the program can assert the

precede any messages. In this case, the Sync

SEND bit in the TXCSR. When SEND is asserted, the

XMTR is enabled but will not start transmitting data until
the first character is loaded into the TXDBUF. If SEND is

character. If the Sync register is not loaded, it
will contain all ones subsequent to a BUS INIT
|
|
or MSTRST.

cleared during transmission, the character currently being

may

not contain the sync

transmitted will be completed, the transmit line will go to a

mark hold state, the internal XMTR logic will enter the idle

Assuming that any necessary handshaking has

state, and synchronization with the RCVR will be lost.

been

When SEND is cleared, there is no guarantee that the TX

asserted, the program can commence trans-

DONE bit will be asserted when current character trans-

mission by loading a sync character into the

mission is complete.

TXDBUF. When the first data bit is transferred

4-1

completed

and

that

SEND

has

been

If the latter method is chosen, it can be programmed in ong”

to the communication line, the TX DONE bit

will be asserted. If the TX INTEB bit is set, an
interrupt

request

will be generated, and the

INTEB bit and clear the TX INTEB bit. The program would

program must load another sync character into

then ignore

the TXDBUF.

transmit a sync character and assert DNA. The program

guaranteed wunless

the

~response time to the TX DONE bit

is less than

XMTR would

would then respond to the TX DONE interrupt by loading

a message character into the TXDBUF, thereby terminating

-‘

time). This can be verified by the absence of

the transmission of sync characters. The second way would

be to clear the TX INTEB and DNA INTEB bits for a given

the DNA bit in the TXCSR.

period

allowing

the

thereby enabling the TX DONE interrupt. The program

program

(1/baud rate X bits per char) seconds - 1/2 (bit

and

of sync characters are transmitted, set the TX INTEB bit

into the Sync register, then synchronization

the TX DONE bit

would monitor the DNA bit and, when the desired number

If the sync character wa_s'not initially loaded
cannot

of two ways. The first way would be to set the DNA

The program can also enable transmission of

time

sync

during

message

characters

from

the

transmitted.

transmission

thereby

sync register to be

initial sync characters from the Sync register.

Assuming any necessary handshaking is com-

NOTE

The SEND bit in the TXCSR must remain set

plete and SEND is asserted, the program loads

the Sync register with a sync character, sets the

for the duration of the message; any on to off

DNA INTEB bit, and clears the TX INTEB bit.

transition will cause the XMTR to enter an idle

Th_e program then loads a sync character into
the TXDBUF and transmission begins. The TX

state

after

completion

current

(

character

transmission.

DONE interrupt is inhibited so the contents of

the Sync register are transferred to the XMTR

4.3 PROGRAMMING THE RCVR IN THE INTERNAL

SYNCHRONOUS MODE

the

first

character

sync

character.

then

The

transmitted

second

sync

Once

and

DNA

shaking, the receiver logic can be enabled. The program B

interrupt is generated notifying the program.

the

program has completed any necessary hand-

-enables the receiver logic by setting the SCH SYNC (Search\_

The program then allows the transmission of

Sync) bit in the RXCSR. Assuming a sync character has

sync characters to continue by simply monitor-

been loaded into the Sync register (this must be done in the

ing the DNA until the desired number have

internal synchronous mode), the receiver begins to compare

been transmitted. Note that DNA is reset each

incoming character bits with the character held in the Sync

time the program reads the TXCSR and set

again when the

first

bit

of the next sync

NOTE

character is placed on the communication line.

For the receiver to become synchronized with
XMTR

NOTE

either

one

two

contiguous

sync

characters must be received. The number of

It is suggested that a minimum of five

sync characters required is jumper selectable.

sync characters be transmitted. In sys-

The standard configuration requires two sync

tems that are prone to error because of

characters.

lost synchronization, as many as twelve
sync characters may be desirable.

NOTE

Though

the

DU1l1

may

jumpered

'synchronize on two contiguous sync characters,

When the desired number of sync characters have been

there is a situation which, if it develops, will

transmitted, the program sets the TX INTEB bit, thereby

enabling the TX DONE interrupt, and responds to the

prevent RCVR synchronization on only two

interrupt by loading a message character into the TXDBUF.

contiguous sync characters. If, while the DU11
is searching for synchronization, it recognizes a
sync character that is not followed con-

4.2.5

Transmitting

Sync

Characters

~tiguously

Maintain

Synchronization

a second sync character, the

RCVR internal logic resets, thereby inhibiting

After synchronization has been achieved, it can be main-

the RCVR bit detection logic for two bit times.

tained by the program by inserting sync characters into the

Should the first bits of a proper sync character

message or by ignoring the TX DONE bit, thereby allowing

sequence occur during that two bit time period,

sync characters from the Sync register to be transmitted.

- the RCVR will fail to achieve synchronization.
42

4.4 PROGRAMMING THE RCVR IN THE EXTERNAL

. When two contiguous sync characters are received, the REC
" ACT (Receiver Active) bit is set and any characters received
after that will cause RX DONE interrupt requests, provided
the RX INTEB bit is set and the STRIP SYNC bit is

SYNCHRONOUS MODE

The external synchronous mode enables the RCVR logic to
set to the synchronize state immediately upon the assertion
of the SCH SYNC (1) H input. This mode is designed for
use with communication equipment capable of accomplishing synchronization external to the DU11. When the
program sets the SCH SYNC bit, the REC ACT bit sets and
the RCVR starts framing characters on the very next bit
received. When the selected number of bits are received, the
received character is transferred into the RXDBUF and the
RX DONE bit is set causing an interrupt request. All other
features and parameters of the internal synchronous mode

cleared.

NOTE

The SCH SYNC bit must remain set for the
duration of the message. If not, the character
being received at the time of the on to off
‘transition will be lost along with synchroni-

zation.

apply to this mode also.

If the programmer wishes the RCVR to discard all sync
characters after synchronization is achieved, the STRIP
SYNC bit in the RXCSR must be set. The STRIP SYNC bit
inhibits the RX DONE interrupt whenever a sync character
is received with no errors; however, the sync character is

4.5 PROGRAMMING THE XMTR IN THE ISOCHRONOUS MODE

4.5.1

Loading the PARCSR

Once the XMTR is initialized via BUS INIT or MSTRST,
the PARCSR must be programmed to select the mode of

still held in the RXDBUF until the next character is
received.

operation (isochronous in this case), character length, and

parity. It is not necessary to load the sync register in this
mode as sync characters are not required to achieve
synchronization and the transmitter is not required to

If the program fails to read the RXDBUF in response to a

RX DONE interrupt, overrun errors will occur. When the
RXDBUF is not serviced in the time required to receive the

X bits per character)
~next character, ie., (1/baud rate

transmit continuously.

seconds, the character presently being held in the RXDBUF
is overwritten by the next received character and the
OVRN ERR (overrun error) bit is set in the RXCSR.

4.5.2

Enabling the XMTR

When the required handshaking is complete, the program
sets the SEND and TX INTEB bits and loads a character
into the TXDBUF. The XMTR adds the START and STOP
bits and transmits the character to the modem. As soon as
the first character bit is placed on the communication line

NOTE

The information in the following paragraph
must be strictly adhered to or RCVR synchronization problems will be encountered.

by the XMTR, the TX DONE bit is asserted and remains
asserted until the XMTR services the TXDBUF or clears the
SEND bit.

If the DUI11 is configured to achieve synchronization on
two contiguous sync characters then receiver operation may

4.6

PROGRAMMING THE RCVR IN THE ISOCHRO-

NOUS MODE

RCVR operation is initiated by the assertion of SCH SYNC.
When the program sets the SCH SYNC bit, the REC ACT

be terminated (after the entire message is received) by
simply clearing the SCH SYNC bit in the RXCSR. However,
if only one character is required to achieve synchronization,
receiver termination is a little more complex. If the SCH
SYNC bit is cleared while a sync character is present in the
RXDBUF, false synchronization will occur when the
receiver is enabled (SCH SYNC bit sct) to receive the next
message. The program must ensure that this does not

bit sets and the RCVR starts framing characters upon
receipt of the START bit from the XMTR. When the
selected number of character bits are received, the RCVR
tests the line for a valid STOP bit, transfers the received

character into the RXDBUF, and sets the RX DONE bit. If
the STOP bit is not detected, the FRM ERR (Framing
Error) bit is also set. If the program fails to service the
RXDBUF before the next character is framed, the OVRRN

happen by transmitting a pad character, i.e., a non-sync

character, immediately after the transmission of the termi-

ERR bit is set.

nating control character.

4.3

‘

APPENDIX A

REPRESENTATIVE MODEM

FACILITIES AVAILABLE
“Model

Manufacturer

Type of Line

- Speed -

Half or

|- Syncor - |

(Maximum)

Full Duplex

Async

Full Duplex
Full Duplex
Full Duplex
Full Duplex
Full Duplex
Either

Async
Async
Async

DDD
DDD

Async
Async
Sync

DDD
DDD
DDD

Either
Either
Either

Sync
Async
Async

Private
DDD
DDD

Bell System
Bell System
Bell System
Bell System
Bell System
Bell System

103A
103E
103F
113A
113B
201TA

300 baud
300 baud
300 baud
300 baud
300 baud
2000 baud

Bell System
Bell System
Bell System

201B
202B
202C

2400 baud
1800 baud
1200 baud

Comments

Similar to 103A

Private

Originate Only
Answer Only
Full Duplex on
|

2 calls

Full Duplex on
2 calls

Bell System
Bell System

202D

1800 baud
600 baud

205B

Either
Full Duplex

Async
Sync

Private
Private

Trans Only

Async

DDD

Private

1200 baud
2400 baud

Bell System

202E

1200 baud

Series
Bell System

301B

40.800

Either

Sync

baud

Bell System

303B,

C.D,E
|

Bell System

19.000 to
230.400

Private
Wide Band

Either

Sync

Private
Wide Band

Async

TWX

baud

811B

110 baud

Either

Network

Western

118-1A

180

Telegraph

1601-A

600

Voice

2121-A

1200

Voice

2241-A

2400

Either

Broad Band

100

200

Either

“Async

Voice

Union

Western
Union

Western

Union
Western

Broad Band

Union

Western
Union

|| Maximum) | FullDuplex| Asnc |
Union.

~Western

‘Union

~Rixon

| 300

| Either | Syne

40000 - f

Either.

“Rixon

| Sebjt48

~ General

Elec_:t'r_ic R

| Broad Band

| Either - | Voice

| Either

|Syne

TDM | 2400 .| Either

|- Either

22() R

| 4800

| 18000- .

FM:12 -{ 1200 -

ey ey

] Bell4A

| Voice

"Private

" Bell4B

|
|
D

APPENDIX B

ADDRESS ASSIGNMENTS
B.1

FLOATING VECTORS

These addresses are assigned in order starting at 760010 and

There is a floating vector convention used for commu-

~nications (and other) devices that interface with the PDP-11
computer. These vector addresses are assigned, in order,
starting at 300 and proceeding upwards to 777. Table B-1

proceeding upward to

763776.

Refer to Table B-2 for

floating address sequence.

shows the assigned sequence. It can be seen that the first

Table B-1

vector address, 300, is assigned to the first DC11 in the

Priority Ranking
for Floating Vectors

system. If another DC11 is used, it would then be assigned

(starting at 300 and proceeding upwards)

vector address 310, etc. When the vector addresses have

Rank

been assigned for all the DC11s (up to a maximum of 32),

Device

Vector

Size

addresses are then assigned consecutively to each unit of

| Max. No.

“(in octal)

the next highest ranked device (KL11 or DP11 or DM11,

etc.), then to the other devices in accordance with the
priority ranking (Table B-1).

If any of these devices are not included in a system, the

vector address assignments move up to fill the vacancies. If
a device is added to an existing system, its vector address
must be inserted in the normal position and all other
addresses must be moved accordingly. If this procedure is
not followed, DEC software cannot test the system.
NOTE

The floating vectors range from addresses 300
to 777, but addresses 500 through 534 are
reserved for special bus testers. In addition,

address 1000 is used for the DS11 Synchronous
Serial Line Multiplexer. Refer to Appendix A
of

the

PDP-11

Peripherals

Handbook,

DC11

KL11,DL11-A,DL11-C

DP11

DM11-A

DN11

DM11-BB

addresses.

B.2 FLOATING DEVICE ADDRESS

DR11-A

10*

32
32

DR11-C

10*

PA611 Reader

PA611 Punch

DT11

10*

DX11

10*

13 | DL11-C,DL11-D,DL11-E

DJ11

DHI11

GT40

LPSI11

30*

1973-1974, for a complete discussion of Unibus

DQ11

KW11-W

DU11

There is a floating address convention for communication

*The first vector for the first device of this type must always be on a

(and other) devices interfacing with PDP-11 computers.

(10), boundary.

B-1

Table B-2

Floatmg Address Sequence "
|

Address Boundary Startmg at 760010 o - Déwcc_») R Fn;rst Addrf:ss

)Joxafl+2

DQI1 1B | 10 X (N) * 2 (geto next 10 20, 30
B 40 5060, 7() or 100 boundary)

If, for example a eommumcatlon system is to contain two'

DHI1s, two DQl1s, two DU11s and no DJ11s. the floatlng', o
|

- 760100

__bun# | | _760130f :)

N = number Qf each devnce

addresses would be assxgned as shownin Table B3

- 760070

- DQII(GAP) 760110
DUIT #0
| 760120

| pul|
t lOX (N)+2(g0 to next 10 20 3()
'40 50 60 70 or 100
boundary)

760060

If a DULL in a SYStem is notPfeceded by Otherdevnces- L

in the floating vector area, itmust have a startmg ad' SR
o
|
dress of 1600 for zero

DHI1(GAP) |
|
S DQUH

Addresses

0000
|

| w?l)Jll(ChAP) ,”- 760010

| 20 X (N +2(go to next 20 40 60 or.__ DHI1
#0
760020
| 760040
~ DHi1#1
100 boundary)

.Number of |
Register

& B

| pH1I

Rank | Devnce

Table B- 3

Floatmg Devxce Address Assxgnments

Re ad e r’ S C ommen t S

DU11 SINGLE LINE PROGRAMMABLE

SYNCHRONOUS INTERFACE
USER’S MANUAL

EK-DU11-0P-001

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