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DEC-15-H0AB-D

November 1970

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Document:	IntfMan
Order Number:	DEC-15-H0AB-D
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OCR Text

Digital Equipment Corporation
Maynard, Massachusetts

PDP-15 Systems

Interface Manual

DEC-lS-HOAB-D

PDP-15
INTERFACE MANUAL

DIGITAL

EQUIPMENT

CORPORATION • MAYNARD, MASSACHUSETTS

1st Printing November 1969
2nd Printing (Rev) February 1970

The material in this manual is for information purposes and is subject to change without notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL

PDP
FOCAL
COMPUTER LAB

CQNTENTS
Page
. CHAPTER 1 PDP-IS LOOIC SYMBOLOGY
1.1

PDp· 15 System Organization

1-1

1.2

Logic Symbology

1-1

1.2.1

Logic Gates

1-1

1.2.2

Flip-Flops

1-2

1.2.3

Variable Clock

1-3

1.2.4

Pul~ Amplifier

1-3

1.2.5

Miscellaneous Logic Symbology

1-3

1.3

DesiJllators

1-4

1.3.1

Logic Designators

1-4

1.3.2

. Signal Designators

)-4

1.3.3

Signal Name Changes

1-5

1.3.4

The Dash

1-5

1.4

Line Connections

1-5

CHAPTER 2 PDP-IS INTERFACE MODULES
Measurement Defmitions
2.1

2-2

2.2

2-2

2.3 "
2.3.1
2.3.2

Modul~nescppiions

2-3

. M(()4 MUlttplexer_Modt\le

2-3

Ml94 Multiplexer Module

2-6

2.3.3

MSOO Negative Receiver Module

2-7

2.3.4

MSI0 Positive Receiver Module

2-8

2.3.5

M622 Positive Driver Module

2-9

2.3.6

M632 Negative Driyer Module

2-10

2.3.7

M909 Terminator Card

2-11

CHAPTER 3 INTRODUCTION TO PDP-IS INTERFACING
3.1

General Principles

3-]

3.2

Data Information

::t-]

3.3

Command and Status Information

3-2

3.4

Interrupts

3.5

The PDP-IS I/O Bus System

3-2

3.6

Summary of the PDP-IS I/O Processor

3-3

3.6.1

The CPU.I/O Controller

3-3

3.6.2

The Memory I/O Controller

3-4

CHAPTER 4 PDP-IS INTERFACING

4.1

Interfacing to the CPU I/O Controller

4-1

4.1.1

A CPU Interface with API

4-]

ii,

CONTENTS (Cont)
Page

4.1.2

The Logic

4.2

Interfacing to the Memory I/O Controller

4-9

4.2.1

nte Multi-eYc1e6ataOl~ruiel Peripheral

4-9

4.2.2

Increment Memory

4-15

4-3

·4.2.3

11leSingle~cle Dat~ Channel Device'

4-21

4.3

System' 'Priority Structures

4-27

4.4

SUmmaryi ~rl/O Bus'PuncHons

4-28

, CHAPTER 5 WIttING PRActICES

5.1

Wiring Rules

5-1

5.1.1

Single Line Waveform Degmdations

5-1

5.1.2

Termination Technique

5-1

5.1.3

~roSstalk in PitrallelLogicLines

5-2

5.2

Properties of #30 A WG Wire

5-3

5.3

5-3

5.3.1

The, Groun~ System
DC Ground System

5-3

5.3.2

AC Ground System

5-4

5.4

Cables in DigitalSystems .

5-5

5.4.1

,- Th'~ pbp:r3P6;itive1/(Y'D~s~C;ble

5-5

b:tietal Wire trifonna'tloJ1" '

$-6

5.5.1

Wire Types

5-6

5.5.2

Wire Insulation

5-6

5.5.3

Wire Insulation Stripping

5-7

5.5.4

Wire Data

5-8

5.6

Solderless Connections

5-11

5.6.1

Crimped Connections

5-11

5.6.2

Wire Wrap

5-13

S~S

5.7

Soldered Connections

5-16

5.7.1

Soldering Irons

5-\6

5.7.2

Solder

5-16

5.7.3

Soldered Connection Requirements

'\-16

Use of Stranded Wire

5-17

5.7.4

CHAPTER 6 THE I/O BUS SYSTEM
6.1

The DW IS Bus Adapter

h-l

6.2

PDP-lS I/O Bus Cables and Cable Assemblies

6-1

6.2.1

The BC09 Cable Characteristics

6-2

6.2.2

BC09A Assembly

6-2

6.2.3

BC09B Cable Assembly

6.2.4

Cable Lengths

Adding Peripherals to the I/O Bus

0-6

6.3

CONTENTS (Cont)
Page
6.3.1

The Electrical Characteristics of the Bus

6-6

6.3.2

Device Select Codes

6-6

6.3.3

Addresses

6-6

6.3.4

Timing Constraints

6-6

6.3.5

System Latency and Priorities

6-6

6.3.6

Cable Runs and Terminations

6-6

6.4

Designing PDP-IS Devices to Operate on the PDP-9

6-10

APPENDIX A DOCUMENTATION
A.l

Drawing Index List

A-I

A.2

Drawing Categories

A-I

ILLUSTRATIONS
NAND Gate

1-2

NAND Gate

1-2

1-3

NOR Gate

1-2

1-4

NOR Gate

1-2

1-5

Inverter

1-2

1-1

1-6

Inverter

1-2

1-7

Basic Logic Relationships

1-2

1-8

D Flip-Flop - Edge Triggered

1-2

1-9

J-K Master-Slave Flip-Flop

1-3

1-10

R-S Flip-Flop

1-3

1-11

Variable Clock

1-3

1-12

Pulse Amplifier

1-3

1-13

I/O Bus Receiver

1-3

1-14

Binary to Decimal Decoder

1-3

1-15

Delays

1-4

1-16

Connectors

1-4

1-17

NAND Gate

1-4

1-18

Read Flip-Flop

1-4

1-19

Signal Designators

1-4

1-20

Signal Name Changes

1-5

1-21

The Dash

1-5

2-1

Voltage Spectrum of Negative Logic Systems

2-1

2-2

Voltage Spectrum of TTL Logic

2-1

2-3

Voltage Spectrum for Positive PDP-IS I/O Bus Logic

2-1

2-4

MI04 Equivalent Circuit

2-3

2-5

MI04 Timing

2-4

2-6

M 104 Circuit Schematic

2-5

ILLUSTRATIONS (Cont)
Page
2-7

M 194 Equivalent Circuit

2-6

2-8

M500 Receiver Module

2-7

2-9

M500 Schematic

2-10

M510 Receiver Module

2-11

M510 Schematic

2-8
2-8

2-12

M622 Driver

2-9

2-13

M622 Schematic

2-9

2-14

M632 Driver Module

2-10

2-15

M632 Schematic

2-10

2-16

M909 Terminator Card

2-11

3-1

I/O Bus Schemes

3-2

4-1

lOT Instruction Format

4-1

4-2

Block Diagram of CPU Device with API

4-2

4-3

Logic Diagram of the CPU Device with API

4-4

Timing Diagram of the CPU Device with API

4-7
4-7

4-5

Block Diagram for Multicycle Data Channel Device

4-9

4-6

Multi-Cycle Data Channel Device Logic

4-13

4-7

Multi-Cycle Data Channel Timing

4-13

4-8

Block Diagram for Increment MemoIY

4-15

4-9

Increment Memory Device Logic

4-19

4-10

Timing Diagram for Increment Memory Devices

4-19

4-11

Block Diagram of Single-Cycle Data Channel Device

4-22

4-12

Logic Diagram of Single-Cycle Data Channel

4-25

4-13a

Timing Diagram for Singie-Cycle Device in Normal Mode

4-25

4-13b

Single-Cycle Asynchronous Timing

4-25

5-1

Terminating Long Wires

5-2

Capacitance and Inductive Crosstalk Components

5-2

5-3

The Ground System

5-4

Typical Ground Mesh System

5-4

5-5

Wire Distribution

5-5

5-6

Non Adjustable Wire Stripper

5- ,

5-7

Adjustable Wire Stripper (Use With Caution)

5-8

Stripping Damage

5-9

Crimped Connectors

5-11

5-10

Acceptable and Unacceptable Crimped Connections

5-1 1

5-11

Properly and Improperly Shrunk Spaghetti

5-12

Wire Wrap Terminology

5-13

Wire Wrap Post Location Standard

5-15

5-14

Examples of 30 and 24 Gauge Connectors

5-16

5-15

Example of Wire Joint Before Soldering

5-17

5-16

Example of Soldering Two Wires on a Post

5-18

ILLUSTRATIONS (Cont)
Page
5-17

Uses of Stranded Wire

5-18

6-1

The I/O Bus Cable System

6-1

6-2

BC09A Cable Assembly

6-2

6-3

Retaining Block Kits

6-3

6-4

I/O Connector W850

6-4

6-5

BC09B Cable Assembly

6-5

6-6

M9l2 PDP-IS I/O Bus Card

6-4

6-7
6-8
6-9

The PDP-IS I/O Bus Drive/Termination Scheme

6-9

The BC09C Cable

6-10

Cabling Converted PDP-IS Devices to the PDP-9 I/O Bus

6-11

A-I

Drawing Index List PDP-8/S

A-5

Drawing Index List PDP-8/S

A-7

A-2

TABLES
Summary of PDP-IS Input/Output Facilities

3-6

4-1

CPU Interface With API

4-6

4-2

Multi-Cycle Data Channel Device

4-12

4-3

Increment Memory Signals

4-18

4-4

Single-Cycle Data Channel Interface

4-24

4-5

Summary of I/O Bus Signal Functions

4-28

3-1

5-1

Recommended Maximum Wiring Lengths With Single Wires

5-1

5-2

Parallel Line Length Limits

5-3

Properties of Insulation Types

5-6

5-4

Solid and Stranded Wires

5-8

5-5

Wire Color and Application Chart

5-10

5-6

Wire Size, Connector Type and Tools To Use For Crimped Connections

5-12

5-7

Chart of Tools, Wire Size, and Wrapping Requirements for Connectors

5-14

6-1

BC09 Cable Specifications

6-2

BC09 Electrical Characteristics

6-2

6-3

Assigned PDP-IS lOT Device Selection Codes

6-4

API Addresses

6-7
6-8

6-5
6-6
6-7

Data Channel Addresses

6-8

Worst Case Latency, PDP-IS Peripherals

6-9

Worst Case Latency Figures

6-9

vii

SYSTEM REFERENCE MANUAL - Overview of
PDP-IS hardware and software systems and options,
instruction repertoire, expansion features and
descriptions of system peripherals. (DEC-IS-GRZA-D)
USER'S GUIDE VOLUME 1, PROCESSOR - Principal
guide to system hardware includes system and subsystem
features, functional descriptions, machine-language programming considerations, instruction repertoire and
system expansion data. (DEC-IS-H2DA-D)
VOLUME 2 PERIPHERALS - Features functional descriptions and programming considerations for peripheral devices. (DEC-IS-H2DA-D)
OPERATOR'S GUIDE - Procedural data..... including
operator maintenance, for using the operator's console
and the peripheral devices associated with PDP-IS
Systems. (DEC-lS-H2CA-D)

PDP-15/40 Disk-Oriented BACKGR:OUND
/FOREGROUND Monitor Software :System

- Background/Foreground Monitor in a disk oriented
environment is described; programs include language,
utility, and application types. (DEC-IS-MR4A-D)
MAINTENANCE MANUAL VOLUME 1, PROCESSOR

- Block diagram and functional theory of operation of
the processor logic. Preventive and corrective maintenance data. (DEC-IS-HB2A-D)
VOLUME 2, PROCESSOR OPTIONS - Block diagram
and functional theory of operation of the processor
options. Preventive and corrective maintenanee data.
(DEC-IS-HB2A-D)
VOLUME 3, PERIPHERALS (Set of Manuals): - Blol:;k
diagram and functional theory of operation of the
peripheral devices. Preventive and corrective maintenance data. (DEC-IS-HB2A-D)

PDP-15/10 SYSTEM USER'S GUIDE - COMPACT and

Basic I/O Monitor
(DEC-IS-GG lA-D)

operating procedures.

PDP-15/20 SYSTEM USER'S GUIDE Advanced Monitor System operating procedures. (DEC-lS-MG 2A-D)
PDP-15/30

SYSTEM

USER'S

GUIDE

- Background/Foreground Monitor System operating
procedures. (DEC-IS-MG3A-D)
PDP-15/40 SYSTEM USER'S GUIDE - Disk-oriented

Background/Foreground Monitor System operating procedures. (DEC-IS-MG4A-D)
PDP-15/10 SOfTWARE SYSTEM - COMPACT soft-

ware system and Basic I/O Monitor System descriptions.
(DEC-IS-GRIA-D)
PDP-15/20 ADVANCED Monitor Software
System -- Advanced Monitor System descriptions; pro-

grams include system monitor and language, utility and
application types; operation, core organization and
input/output operations within the monitor environment are discussed. (DEC-IS-MR2A-D)
PDP-15/30 BACKGROUND/FOREGROUND Monitor
Software System - Background/Foreground Monitor de-

scription including the associated language, utility and
applications programs. (DEC-IS-MR3A-D)

viii

INSTALLATION MANUAL - Power specifications,
environmental considerations, cabling and other :Information pertinent to installing PDP-IS Systems.
(DEC-IS-H2AA-D)
ACCEPTANCE TEST PROCEDURES - Step by st,ep
procedures designed to insure optimum PDP-IS Systems
operation.
MODULE MANUAL - Characteristics, specifications,
timing and functional descriptions of modules used in
PDP-IS Systems.
INTERFACE MANUAL - Information for interfacing
devices to a PDP-IS System. (DEC-IS-HOAA-D)
UTI LlTY PROGRAMS MANUAL - Utility programs

common to PDP-IS
(DEC-IS-YWZA-D)

Monitor

systems.

MAC R 0 -15 - MACRO assembly language for the
PDP-IS. (DEC-lS-AMZA-D)
FORTRAN IV - PDP-IS version of the FORTRAN l[V
compiler language. (DEC-IS-KFZA-D)
FOCAL-15 --- An algebraic interactive compiler level
language developed by Digital Equipment Corporation.
(DEC-IS-KJZA-D)

PDP-15 FAMILY OF MANUALS

HARDWARE

INSTALLATION
MANUAL

MODULE
MANUAL

ACCEPTANCE
TEST
PROCEDURES

SOFTWARE

OPERATORS
GUIDE

PDP-15/40

8/F,15/30/40

PDP-15/30

PDP-15/20

ADVANCED

PDP-15 110
SYSTEM USER'S
GUIDE

--+--1

1-1

PDP-15/10
SOFTWARE
SYSTEM

UTILITY
PROGRAMS
MANUAL

MACRO -15

FORTRAN TI[

FOCAL-15

8/15
TRANSLATOR

15-0040

>('

CHAPTER 1
PDP-IS LOGIC SYMBOLOGY

The purpose of this chapter is to explain the organization of the PDP-IS logic diagrams to aid the logic
designer or engineer involved in interfacing to a
PDP-IS System. The following topics will be discussed:

Print size and type - e.g., D-BS which means
D size, Block Schematic

Print number - This is section oriented; e.g.,
KPI 5-0-25 which means Print 25 of the Central
Processor section.

PDP-IS System organization

Logic Symbology

Designators

Line connections

1.1 PDP-IS SYSTEM ORGANIZATION

All PDP-IS systems, from the basic system (PDP-I 5/
10) through the disk-oriented background/foreground
system (PDP-l 5/40), are organized in three main
sections: Central Processor (CP), Memory (Internal
Storage), and Input/Output (I/O) Processor. The designations of these three sections are as follows: KP15
Central Processor, MMl5 Memory, KDl5 Input/Output Processor. All PDP-IS logic diagrams have been
drafted utilizing a computer controlled automated
drafting system (ADS), and therefore have similar
characteristics. The logic diagrams flow from leftto-right wherever possible.

Each logic print has a coordinate marking system to
help locate gates. The system is as follows:

Numbers 1-8, from right to left, across the top
and bottom margins.

Letters A-D, from bottom to top, on left and
right margins.

1.2 LOGIC SYMBOLOGY
The logic modules utilized in the PDP-IS are primarily
DEC M-series, which is the integrated circuit, positive
logic series. The voltages used are:
Low (L) = OV (OV -+O.4V)
High (H) = +3V (+2.4V -+3.6V)
(For specific information on operating frequencies,
loading etc., see the individual module specifications.)
The logic symbology used is MIL-STD-806B. The
gating symbols use small circles at the inputs of gates
to indicate that a low signal activates the function.
The absence of a circle indicates that a high signal
activates the function. The presence or absence of a
circle at the output of a gate indicates that the output
is Low (L) or High (H), respectively, when the gate
has been activated (its output is true). A gate's output is false if it is at a voltage different from that
shown by the gate's polarity indicator (presence or
absence of circle). Suffixes L or H indicate the low
or high level of a signal when it is true or enabled.

1.2.1 Logic Gates
Boolean functions are symbolized as follows:

A label at print coordinate A-I (lower right corner)
identifies the logic diagram. The label has three parts:

Print name - e.g., Indicator Strobes

* Logical AND
+ Logical OR (inclusive)
- Logical negation (the vinculum is not used)
1-1

l11e most commonly used gating symbols are the
NAND (Figures I-I, 1-2);NOR (Figures 1-3, 1-4), and
the Inverter (Figures 1-5, 1-6). Each figure shows
both the symbol and a Boolean expression of the
logical operation it performs.

ing figures illustrate the types of flip-flops used in the
PDP-IS System.
The flip-flop in Figure 1-8a requires a high data input
when clocked to set; the flip-flop in 1-8b requires a

CC H
AAL.=L)-

AAH-=D-

xx H

=D-XXL

YY L

DO H

BB H -

BB L

CCH+DDH:aXXL
AA H*BB H =YY L

AA L*BB L=XX H
15-0068

Figure 1-1 NANDGate

CC L
DO L

=D-

Figure 1-2 NAND Gate

AA L

AA H

YYH

Figure 1-3 NOR Gate

BB L

-{>-

CC L + DO L = YY H

AA H = AA L

B B L =BB H

Figure 1-5 Inverter

Figure 1-6 Inverter

15-0068

Figure 1-4 NOR Gate

DIRECT S E T -

AA L

BB L -~--

xx H

CC L
DO L
(AA U"BB U+(CC Lo~DO L)= xx H

DATA
INPUT
CLOCK
INPUT

DATA
INPUT
CLOCK _
INPUT

-DIRECT CLEAIR -

Figure 1-7 Basic Logic Relationships
1-8a

1-8b

Figure 1-8 D Flip-Flop - Edge Triggered
Some of the logic gates are made up of combinations
of the basic functions. The operations of these gates
can be determined by the combined use of the basic
logical relationships. (Figure 1-7.)

1.2.2 Flip-Flops
A major part of the work accomplished by the computer's logic is performed by flip-flops. The follow-

1-2

low data input to be set. The D flip-flop will be arawn
on the logic diagrams to agree with the voltage level
of the data input necessary to set the flop.
Figure 1-9 shows the J-K flip-flop. The flop has direct
set and reset inputs, and clock-gated set and reset inputs. If both gated inputs are high when the flop is
clocked, the flop will complement.

EtB H

1.2.4 Pulse Amplifier

DIRECT SET

A typical pulse amplifier as used in the PDP-IS is
shown symbolically in Figure 1-12.

GATED
(
SET INPUTS
CLOCK INPUT
GATED
{
RESET INPUTS

0
DIRECT RESET
TRIGGER {
INPUTS
-""""'"---_

15-0068

OUTPUT

Figure 1-9 J-K Master-Slave Flip-Flop

Figure 1-12 Pulse Amplifier

The flip-flop in Figure I-lOa can be reset by either
one of two inputs; the flip-flop in Figure I-lOb has
the OR gate on its set side.

1.2.S Miscellaneous Logic Symbology

SET
S
INPUT ----'"""
RESET
INPUTS

SET
INPUT

RESET _ _- - I ' l l
INPUT
R

OUTPUTS

INPUT

15-0019

I-lOa

I-lOb
Figure 1-13 I/O Bus Receiver

Figure 1-10 R-S Flip-Flop

1.2.3 Variable Clock

ENABLE
INPUTS

The PDP-IS uses variable clocks to generate timing
signals and to control gating functions. Figure I-II
shows a typical clock configuration.

ENABLING {
INPUTS
~___

"} OUTPUTS

DECODING
INPUTS

OUTPUTS

15 -0068

Figure 1-11 Variable Clock

15-0069

Figure 1-14 Binary to Decimal Decoder

1-3

=D----(C......a..II-~)

input pins on specific module (PI, R I)

output pin (S I).

15-00Sl
15-0069

Figure I-I 5 Delays

Figure 1-17 NANDGate

-::::
....

The flip-flop modules also have a name associated
with them, such as READ (Figure I-IS) .

....,
,..

-...
...,

,...
....,

1"'\

....
....,

,..
....,

D
READ
M205
K15

,..
...,

,..
....,

v
,..
v

,..
....,

NAME
TYPE OF MODULE
LOCATION OF
MODULE
N1

15-0069

-'-

15-0069

Figure I-IS Read Flip-Flop

Figure 1-16 Connectors
1.3.2 Signal Designators
1.3 DESIGNATORS
The llogic symbology used thus far has not shown any
literal designators. The following paragraphs will describe and discuss the information that accompanies
the logic symbols.

All logical expressions are broken into three parts
(Figure 1-19):

KP32 CP ACT (I)H H 1 ~-M133
KP32 RD RST H J1
K18

K1 KP32 CP R[) RST L

1.3.1 Logic Designators
Figure 1-19 Signal Designators

The NAND gate, Figure 1-17, contains the following
information:
a.
type (M II 2)
b.

1-4

location in the computer (LIS - of applicable
section - CP, I/O, or MEM)

Prefix - identifies where the signal originated
(KP32 - Print 32 of the central Processor).

Signal name - RD RST, CP ACT.

Polarity or voltage indicator (H or L). Note
that in the case of flip-flops, a (1) or (0) is
present to indicate the state of the flip-flop
necessary for the desired voltage. For example, KP32 CP ACT (1) H is the 1 side high
output of a flip-flop named CP ACT.

KP20 DEFER (1) H A1
- KP30 ISl H
- KP30 JMP H
- KP30 XCT H
1~·0069

Figure 1-21 The Dash

1.3.3 Signal Name Changes
When a signal originating from a flip-flop is inverted
through an inverter, the signal name will be changed
(Figure 1-20).

A dash (-) within a logical expression, and not in front
of it, does not indicate negation; it represents the
word TO and is used in expressions that perform a
transfer type function. KP32 MO - MDL H would
be read as MO TO MDL.

1.4 LINE CONNECTIONS
KP64 IN STOP 02 (I)L J1

15-0069

Figure 1-20 Signal Name Changes

The conventions used to indicate when lines merely
cross over each other, and when there is an electrical
connection are as follows:

This change in name avoids possible confusion about
where the signal actually originated.
b.

1.3.4 The Dash
Logical NOT or negation is shown by a dash (-) in
front of the logical expression. It is never used in
front of flip-flop designators. The gate in Figure 1-21
shows negated functions. A true output from the gate
is described by the following expression:
DEFER (1) * ISZ * JMP * XCT

Dotted junctions as shown below are not used.

Lines that merely cross each other on the logic
diagram are shown as follows:

+
c.

A junction of signal paths, or an electrical
connection is indicated as follows:

NOTE
The vinculum is used only for explanation purposes.

1-5

Figure 1-22a shows an example from the logic prints
with lines crossing and junction points. Figure 1-22b
has dots drawn at the junction points to show where

junction points are, although dots are never used in
the logic symbology.

J1
K1

L2
M2
N2

15 -0069

Figure 1-22a

1-6

Figure 1-22b

CHAPTER 2
PDP-IS INTERFACE MODULES

This chapter provides descriptions of special modules
used to interface the PDP-IS I/O Processor to peripheral devices, or PDP-IS devices to the PDP-9. Rules for
wiring these modules together are given in Chapter S.
DEC builds three series of compatible below-ground
logic (the B-, R- and S-series), two series of compatible above-ground logic (K- and M-series), an extensive
line of modules to interface different types of logic
(W-series), a line of special purpose modules (G-series),
and a line of support hardware for its module line
(H-series).
With few exceptions, the DEC below-ground logic
operates with logic levels of ground to -O.3V (upper
level and -3.2V to -3.9V (lower level) using diode
gates which draw input current at ground and supply
output current at ground. Figure 2-1 shows the voltage spectrum of negative logic systems.

whose outputs sink current at ground.
shows their voltage spectrum.

UPPER LEVEL

{ +3.6V
+2.4V

INDETER MINANT

{+2.0V

Figure 2-2

t--1---- - - - - -

+O.8V
~---

LOWER LEVEL { +O.4V
OV

15- 0070

Figure 2-2 Voltage Spectrum of TTL Logic

Finally, a set of special modules designed to operate
on the PDP-IS I/O bus are available. Figure 2-3 indicates the voltage spectrum that they operate in.
UPPER LEVEL {

-O.~~ ~----- ...
~-----

The DIGITAL Logic Handbook, C-I OS, is recommended reading for those not already familiar with
the basic principles of digital logic and the type of
circuits used in DEC logic modules.

-1.3V
INDETERMINANT { _ 2.2V
- 3.2V
LOWER LEVEL { _ 3.9V

15-0070

Figure 2-1

Voltage Spectrum of Negative
Logic Systems

UPPER LEVEL {

2.8V

r--- - - - - - - . . ,

2.0V

1------

I NDETERMINA NT {1.6V
1. 3V
LOWER LEVEL {O.8V
O.4V

The compatible above-ground logic generally operates
with levels of ground to +O.4V, (lower level) and +2.4
to +3.6V (upper level) using TTL or TTL-compatible
circuits whose inputs supply current at ground and

15 - 007 0

Figure 2-3 Voltage Spectrum for Positive
PDP-IS I/O Bus Logic

2-1

All modules used in the interface circuits of this
manual are M-series. Several are level converters designed to match positive logic to negative logic.

Input/output delay is the time difference between in··
put change and output change, measured from 50%
input change to 50% output change. Rise and fall de··
lays for the same module usually are specified sepa··
rately.

2.1 MEASUREMENT DEFINITIONS
Timing is measured with the input driven by a gate or
pulse amplifier of the series under test and with the
output loaded with gates of the same series, unless
otherwise specified.
Percentages are assigned as
follows: 0% is the initial steady-state level, 100% is
the final steady-state level, regardless of the direction
of change.

2-2

Risetime and falltime are measured from 10% to 90%
of waveform change, either rising or falling.

2.2 LOADING
Input loading and output driving are specified in
"units", where one unit is 1.6 rnA by definition. The
inputs to low speed gates usually draw 1 unit of load.
High speed gates draw 1-1/4 units or 2 rnA.

Input Pin

2.3 MODULE DESCRIPTIONS

Load (Units)

HI
E2
NI
F2

This is an M-series single-height module which contains
a single multiplexer subsystem. Its equivalent circuit
is shown in Figure 2-4. The inputs are standard TTL
voltages and have the following input pins and loads:

I
I
I

2.5

2.3.1 MI04 Multiplexer Module

6
3
I
1-1/4
68 Q Termination
I

K2
S2

82n

+5V

LH~~E-N--'N--H-------------------------=D~ ~~~
__

REQ(O)H

0
R
C

____

~I~6_8__n__~o
EN OUT H M2

1
ENB

S
D

ENA (1) L SI

ENA (1) H PI

HI SYNC H

0
ENB (1) L Fl

MI04
MULTIPLEXER

0
R
C

0
ENB (1) H El

ENA

0
REQ (1) L J2

0
REQ(1 ) H U2

GRANT H

\ CLEAR FLAG L J 1

LJ
30-200n5

PWR CLR H
0
R
C

REQ

1
S
D

CLR REQ L

0
FLAG(1) L S2
15-0088

Figure 2-4 M104 Equivalent Circuit
2-3

Outputs:

The output gates can drive as follows:

Output Pin

#Loads it can Drive

5
8
9
10
10
10
PDP-I 5 I/O Bus
Compatible (30 units)

12
PI
SI
EI
FI
M2
11

pulses are fed into SYNC of the M I 04 and immedi·
ately set the REQ flip-flop. The REQ flip-flop can be
monitored through pins 12, U2. The I/O processor
responds to a request with a GRANT, and ENA is set .
This flip-flop is usually used to gate any address infor··
mation onto the bus; e.g., the API trap address or the:
word count address of the multicycle data break.
Finally, the next SYNC pulse sets ENB.
The REQ flag can be reset through pin F2, called CLR
RQ, by the controller logic. Pin ·N1 should be tied to
power clear or its equivalent.

Power: I Watt
Application: The MI04 module has been designed
specifically for controllers of PDP-I 5 peripherals. It
is used in all controllers which make use of the API
or data channel facilities in the I/O processor. It
accepts a request from the controller logic at its FLAG
(1) H input and synchronizes this request to the I/O
SYNC H pulses issued from the I/O processor. These

I/O SYNC

1
0

FLAG (I) L

1
0

REQ

1
0

GRANT H

1
0

Finally, the enabling level ENABLE IN will hold REQ
off if it arrives as a negative level. When REQ is set
(if ENABLE IN is positive), then ENABLE OUT will
go negative and the next peripheral on the bus will
receive it ~s a negative ENABLE IN. In this way, the
MI04 establishes priorities among devices on the same
API level or among these that use the data channel.
A timing diagram is given in Figure 2-5 for the M104.

* 01

CLR REQ

ENA

1
0

ENB

1
0

*Jl IS ASSUMED TO BE WIRED TO F2
t5 -0087

Figure 2-5 M104 Timing

2-4

C8
100MMF

rV)Ql

lUUV,:>W/o
\1
II

2
H2

~ E3 " ' 6

EN IN H

CLR FLAG L

L~~
9
10_

FLAG H

+3V

R4
470

r - - U2

1 9

8
E2

+3V

R8
1K
DL1

JL:. 8
11 ~
C

El
ENA
2

r " lOOns '

Rl
330

"I' C7

R2
750
GND
C2,Tl

El
ENB
5
1 !----SI

UN L E~~ OTHERWISF INDICATED·
CAPACITORS ARE .0IMFD,tOOV,2%
RESISTORS ARE t/4W, 5%
El,E4 ARE DE7474N
E2 IS DEC7400N
E 3 IS DEC74H40N
PIN 7 ON EACH IC =GND
PIN 14 ON EACH IC = +5V

- -'lL+

..-.--

~~~6
C
0

+5V
A2
C5
6.8 MFD
35V.20%

l~ - - - - ~--- - - - - - _..J

R9
lK

.'1'

R12
lK

I
I

~II

1/2W

GRANT H

PWR CLR H

R5
68

> RIO
PA
I
3
6
470
K2~ I r----- C
Of-E4
Rll
DL2
I
220
13
E2
2
5
0
1
r \110005 J
I
C9
R3
I
""'--Jl
*1i'5000~~t%
lK
82
I

l....---...-4

;;, C2

F' Cl

r - - - - - - ----------,
0~~J2

12 0

C4
M2

~~
C

EN OUT

R7
470

12~

10 SYNC H

DEC3009B

R6
220

E4
REO
S2

12 0

15-0105

Figure 2-6 M 104 Circuit Schematic

Application:

2.3.2 M194 Multiplexer Module

The M194 module has been designed for PDP-IS
controllers which are to be used on the PDP-9. It
is used for exactly the same reasons as the M I 04.
Pins H2 and M2 are level converted from PDP-9
I/O bus levels (pin H2) to TTL, and then back to
PDP-9 levels at M2. All other inputs and outputs
are identical to those of the M I 04. Figure 2-7.
shows the MI94 equivalent circuit.

This :is an M-series single-height module which contains
a single multiplexer subsystem. It is pin-compatible
with the M I 04 module. Inputs and outputs have
identical loading and driving capabilities as the M104
module with the exceptions of pins H2 and M2.
Power dissipation is 1 watt.

IH~~E-N-IN-H------1[»+-----LEVEL CONVERTER

>-----------~
EN OUT H M2
LEVEL CONVERTER

REQ (0) H

o
R
C

ENB

1
S
0

ENA (1) L SI

cr-------.-------------------~--.~
H I SYNC H

0
ENA (1) H PI

0
E NB (1) L Fl

MI04
MULTIPLEXER

ENB (1) H El

x:::»------+-~~ R

0
REQ (1) L J2

0
REQ (1) H U 2

~-~~.-------_o

GRANT H

\ CLEAR FLAG L J 1

LJ
30-200ns

PWR CLR H

r---+--4..1 R

C
F2

CLR REQ L

RE Q

1
S

0
~-----------------------------o
FLAG( 1) L S2

Figure 2-7 M 194 Equivalent Circuit

2-6

2.3.3 MSOO Negative Receiver Module

Each M500 receiver has a negative input clamped to
The threshold switching level is -1.5V
with an input current of 100 p.A.

o and -3V.

This is an M-series single-height module containing
eight I/O bus receivers which can accept negative logic
levels and convert them to-.positive levels.

02
C1

Inputs:

Minimum input impedance at OV: 30 kn
Maximum current load to bus: 100 p.A
Inputs are standard negative logic levels
of 0 and -3V.

R2
T2

Outputs: Fan Out Output #1: 12 units
Output #2: 11 units
Input/Output #1 delay: 50 ns
Input/Output #2 delay: 40 ns

K2
51

M2
V2

Outputs are standard TTL logic levels.

Power Dissipation: 750 mW max from -15V
800 mW max from + SV

15-0073

POWER
..

Application: The MSOO module was designed to receive PDP-9 I/O bus signals for devices using positive
logic. It provides a high input impedance.

A2---+5V

- - - C2,T1 - - GNO

Figure 2-8 MSOO Receiver Module

+3V

OUTPUT NO.1
(INVERTING)
P
_ _ OUTPUT NO.2
' (NON-INVERTING)

L -_ _ _ _ _

- I .5 V -"V\Ar--t-1

3K
-15V
15-0074

Figure 2-9 M500 Schematic
2-7

2.3.4 M510 Positive Receiver Module

The MSI 0 module is an M-series single-height module
containing eight PDP-IS I/O bus receivers.

The receiver circuit consists of a two-stage emitter
follower with two TTL output buffer gates to supply
both inverted and non-inverted outputs.

J 1

Inputs:

Minimum input impedance: 22.S kU
Maximum current load to bus: 100 p.A
Inputs are standard PDP-IS I/O Positive
Bus levels.
52

Power Dissipation: 900 mW

Outputs:

Fan Out Output #1: 10 units
Output #2: 12 units
Input/Output #1 delay maximum: SO ns
Input/Output #2 delay maximum: 60 ns
Outputs are standard M-series levels.

15-0075

POWER

Application: The M51 0 module was designed to receive PDP-IS I/O bus signals for devices using positive
logic. It provides a high input impedance which yields
a switching threshold between the high and low levels
of the propogated signals. This feature reduces loading and noise problems.

4----- A2--'+5V
~C2,T1--GNO

Figure 2-10 MS 10 Receiver Module

r---------~N~1~OUTPUT
NO.1
(INVERTING)

100

IN PUT n..-AA,"-_-I--I
P2
74HOO
74HOO

30098

OUTPUT
NO.2
(NON -INVERTING)

+3V
15-0076

Figure 2-11 M510 Schematic

2-8

2.3.5 M622 Positive Driver Module

Outputs: Outputs are standard PDP-I 5 positive I/O
bus signals.

This is an M-series single-height module containing
eight positive bus drivers.

Risetime: 15 ns at the input to the cable.
Current sink = 100 rnA max. at Vee sat=
OAV

Each driver consists of an AND/OR integrated circuit
gate and a discrete component open-collector driver.

Falltime: IOns at the input to the cable.
Input - Output Delay = 30 ns max

~
~
~
~

M 622

~
~
S2

M 622

+SV

470

M 622

~
~

Power Dissipation: 1.05W max from +5V

M 622

+ 3V
C1

3009B
220

+ 3V

-=-

M 622

15-0078

15-0077

POWER
4--A2---+5V
. - - - C2,T1--GNO

Figure 2-13 M622 Schematic

Figure 2-12 M622 Driver
Inputs:

Inputs are standard TTL voltages.
The input load at OV is 1-1/4 units.

Application: The M622 module was designed specifically to drive PDP-I 5 I/O bus signals for devices which
use positive logic modules.

2-9

2.3.6 M632 Negative Driver Module

Outputs: Outputs are standard negative logic levels.

The M632 is an M-series single-height module containing eight driver circuits. It accepts positive logic signals
and converts them to negative logic levels.
Each driver consists of a TIL input gate and a negative open-collector output driver clamped to ground
and - 3V.

Inputs:

Standard TTL levels - input current load at
OV is 1-1/4 units.

~
~~
~

~
~
~
~
Ml

M632

M2
-

M632

P2
-

M632

Risetime: 15 ns
Falltime: 15 ns with 1.5kfl to -15V at output
Input - Output Delay = 50 ns max
Power Dissipation: 600 mW from -15V max
900 m W from + SV max
Application: This driver is used to convert positive
logic signals to negative logic levels that drive the
PDP-9 negative I/O bus. It is pin-compatible with the
M622.

+3V
Cl

36398

52
-

66~~

~--O-3V

VI
POWER
----A2-+5V

M632

~C2.Tl-GNO

Figure 2-14 M632 Driver Module

2-10

V2
-

15-0079

--I*-o-.6V
664
15-0078

Figure 2-15 M632 Schematic

2.3.7 M909 Terminator Card

Inputs:

There are 18 inputs - one to each
resistor.

This is a standard single-height M-series board with
18 terminating resistors of 68n each.

Outputs:

There are no outputs.

Pdwer Dissipation: 1.8W max

All resistors are 68-1 /4 W S%
Application: These boards should replace the output
cable of the last peripheral on the positive PDP-IS
I/O bus.

GND Pins are C2 F2 J2 L2 N2 R2 U2 Al CI FI KI
Nl RI Tl

M2 P2

15-0079

Figure 2-16 M909 Terminator Card

2-11

CHAPTER 3
INTRODUCTION TO PDP-IS INTERFACING

3.1

GENERAL PRINCIPLES

The input/output processor of the PDP-IS computer
is designed to handle the information flow between
the central processor, or its memory and a wide range
of peripheral devices. The nature of these peripheral
devices varies widely. Some, such as the typewriter,
are very slow and require, or give up information at
correspondingly slow rates. Others, such as the high
speed disk, deal with data at a rate of millions of bits
in a second. Although the information needs of such
diverse devices vary, their information can be classified into three general categories: commands, data,
and status. The nature of each will be illustrated with
the following example.

The DECtape system is a low speed 10 (ten) track digital tape recording peripheral. A single central control
handles up to eight tape transports. A transport can
read or write digital information in either direction of
tape movement in one of two modes, normal and continuous. It becomes immediately apparent that the
computer must specify a number of DECtape parameters before beginning to read or write its data.
These parameters include: the tape transport to be
used, where on the tape, in which direction and in
what mode the data is to be written. The information
written is data and the result of the operation - such
as the nature of any detected errors, (did it run out of
tape) or special status functions - is called status. The
computer commands DECtape to read or write data
and report its status.

3.2 DATA INFORMATION
Of the three kinds of information transfers that take

place in the I/O processor (commands, data and status), the command and status consist typically of one
transfer each. The data transfer is usually more complex, for it involves N transfers, where N is defined by
the program.

In a typical transfer of N words, the program specifies
a storage (starting) address, and a count of the number of words, N, to be transferred. The storage area
thus defined is referred to as a data buffer. During
the transfer, the I/O processor hardware or device
hardware keep track of the current address and data
count until all the desired words have been transferred
into the buffer. When I/O processor hardware controls the address and count, two locations in core
memory are assigned to the device for this purpose. If
the device is designed to manage the count and addressing it uses two of its own hardware registers. The
PDP-IS has facilities for either I/O processor controlled transfers called multi cycle data breaks, or
device controlled transfers called single cycle transfers.

Consider an example of an output transfer. The I/O
channel takes data out of the buffer (located in core
memory) in ascending sequential order and passes it
on to the peripheral (e.g., a disk) in the same order.
Two arithmetic operations are necessary for each
transfer to the peripheral. After reading data from
storage, the I/O processor (for a multi-cycle transfer)
or the peripheral (for a single-cycle transfer) add a
constant of + 1 to the register which specifies the current address, and then add a constant of -1 to the register which specifies the word count. When the word
count equals zero, the transfers are stopped. (In practice, the word count register is loaded with the 2's
complement of the count, and a +1 is added until
overflow.)

3-1

Input transfers are similar except data is written into
storage rather than read from storage.
Some peripherals which transfer data do so at stich
slow rates that the high speed capability of the multi
cycle or single cycle data channels is unnecessary. Examples of slow devices such as this are Teletypes and
oscilloscope controls. Devices in this class "farm out"
their I/O arithmetic to the central processor. This
delegation of responsibility slows down the execution
of the main program, however, since the program now
has to compete with the peripheral for the services of
the arithmetic section and the core memory where the
data is stored. However, the time lost is tolerable and
the hardware design of the device's interface greatly
simplified. Such transfers are called program controlled transfers.

3.3 COMMAND AND STATUS INFORMATION
Command information, which was used to select the
DECtape transport, the direction of data transfer and
the required operation in our example, also occurs infrequently, one word at a time. This type of transfer
is carried out by the PDP-IS in the same way as program controlled transfers. Usually, the program or operating system determines the commands, selects the
device and, through the central processor, transfers its
infonnation to the device's command register for interpretation.

and automatic priority interrupt (API) hardware
schemes have been devised for the PDP-IS I/O processor. These facilities allow the most urgent requests to
be serviced first and as quickly as possible. They are:
described in detail in the PDP-IS User's Handbook.

3.S THE PDP-IS I/O BUS SYSTEM
There are two types of bus systems in use on current
digital computers (Figure 3-1): the radial system
where each peripheral is connected to a physically separate cable or channel and the program identifies the
device by a number on that channel; and the paralIc]
system where one I/O cable goes to all peripherals. In
the parallel system the cable leaves the I/O processor
and is chained to each device on the channel in turn.
This distributes the cable connections along the bus,
and therefore reduces cable congestion at the proces-'
sor. There is one set of line drivers and receivers in the
processor instead of one set per device.

COMPUTER

PERI PHERALS
RADI AL BUS SYSTEM

A status information transfer is the reverse. The device requests software intervention at the end of one
of its operations, and the program reads a status word
into the central processor under program control. The
word is then analyzed by the program and further
commands are issued.

15-0080

COMPUT:I

(PDP-15~

3.4 l£NTERRUPTS
1/0 CABLES

Another type of command information referenced in
our examples, but not defined, pertains to the ability
of a device to request software intervention after it
completes an operation and needs further direction.
This is a way of interrupting the program from its normal routine, and forcing it to service the device. Again,
the program is slowed down while it identifies the requesting device and services it by transferring data under program control or by initializing the data channel
for a more complex transfer. In order to reduce the
identification period, elaborate program interrupt (PI)

3-2

PARALLEL BUS SYSTEM
15-0080

Figure 3-1 I/O Bus Schemes

The PDP-15 uses the parallel bus system where one
cable is chained from device to device. Commands
(other than program interrupt or automatic priority
interrupt) and status are transmitted on the same lines
as data, and these lines are used for both program control and data channel transfers. Data, command and
status words can be up to 18 bits.
A set of control lines accompanies the data lines· to
identify the activity on the lines. The control lines
identify data channel transfers, program controlled
transfers, status or command instructions, program interrupt or API commands or miscellaneous operations
such as a pulse to clear all registers prior to set up.
There are a total of 72 signals in the cable.
All devices on the I/O bus can be operated concurrently by means of a time-shared multiplexing arrangement wherein the data channel and API automatically
interleave services to the various subsystems; and the
operating program is designed to interleave services
during program-controlled data, command or status
transfers.
Essential to this multiplexing system is the idea of a
device number or device address. During multi-cycle
data channel or API operations, the peripheral transmits its device number to the I/O processor so that the
program can address the data buffer appropriate to
that device. For a transfer operation, the device number specifies the locations of the word count and current address. For an API request, this number specifies the location that the program must "trap" or
jump to. During single-cycle data transfers, the device
specifies the core address where it wishes to transfer
the current word.
- A device number is also used during program-controlled command status and data transfers. In this
case, the number is selected by the program through
an instruction called an lOT (input/output instruction). Each device is assigned a group of such instructions which include the device number. During the execution of the instruction, the device number is transmitted to each device. Only the correct device will
decode the number and carry out the intended transfer; all other devices remain inactive. This facility is
called the addressable I/O bus.
All signals on the cable, except afew, which are called
ENABLE signals, are broadcast to all devices in parallel. Each device passes on the signal it receives without

amplification, and in a similar fashion all input signals
are passed along, and the I/O processor sees a composite of all. Units that are not active transmit logical zeroes which do not cause interference between devices.
The ENABLE signal is not always passed on; it is the
key to the automatic multiplexing scheme used by the
data channel and API. This signal is wired in series
through each device. When a device receives the
ENABLE signal on API or data channel it decides
whether or not it wants to communicate with the I/O
processor.
If communication is desired it traps
ENABLE, preventing the signal from passing to the
next device on the chain. If no communication is desired it merely passes the signal on as it would any
other outbound signal.

3.6 SUMMARY OF THE PDP-IS I/O PROCESSOR
The PDP-15 I/O processor contains two basic subsystems; a CPU I/O controller* and a memory I/O controller*. The former handles all information transfers
between the I/O bus and the CPU; this includes any
program interrupts on PI or API, all program controlled transfers of data, command or status information and miscellaneous instructions such as CAF (clear
all flags).
The memory I/O controller carries out the single- or
multi-cycle data channel transfers of data, and includes a facility to either increment the content of a
device specified location or add a number to its contents. Data in 18-bit words can move in or out of
memory at speeds of 1 mHz during single-cycle transfers; 250 kHz during multi-cycle transfers.

3.6.1 The CPU I/O Controller
The PDP-I 5 CPU I/O controller handles all control and
data transfers between the central processor and devices on the I/O bus. It uses the following basic system elements:
a.

An addressable I/O bus which includes the
shared 18-line data path, 3 lOP control signals,
eight device-code lines and a line which specifies an input transfer called RD RQ L.

*Note that these subsystems are functional, and do not have any real
physical location.

3-3

A program interrupt request line (PROG INT
RQ L) used by the device to request program
intervention. When any device selects this line,
the central processor automatically traps to location 0 of bank 0, stores away important current registers under program control and proceeds to execute the contents of location I of
bank O.

Each device interfaced to the API option spec··
ifies (sends) its "trap address" or unique ser··
vice routine entry point to the processor when
granted an API break by the processor. Core
memory locations 40 8 through 778 are assign··
ed as these entry points. JMS or JMS I instruc··
tions contained in these locations provide link·
age to the actual service routines.

Skip and status lines which provide a way for
the computer to identify a device which causes
a program interrupt. This is important since all
devices share the same program interrupt line.
Having trapped to location 0 on a program interrupt, the program usually jumps to a routine which issues successive lOT SKIP instructions, one for each device. The device which
echoes back a pulse on its SKIP RQ L line is
identified as the requesting device. The edLoed pulse causes the program to skip its next
instruction which usually sends the program to
that device's service routine.

Of the 28 hardware channels, 3 are assigned
internally to the paper-tape reader, real-timt!
clock, and optional power-failure detection
system.
Each API priority takes precedence over low·
er API priorities, program interrupts, and tht!
main program. The highest priority program
segment interrupts lower priority program seg··
ments when activated. The data channel and
real-time clock hold highest priority.
The entire API system may be enabled or dis··
abled by a single lOT instruction.
The I/O bus contains 12 lines unique to tht!
API; these include an API RQ L (request), an
API GR H (grant) and an API EN H (enable)
line for each of the four levels. Other I/O bm;
signals used by the API include I/O PWR CLR
H, I/O SYNC H, and I/O ADDR 12 L-I/O
ADDR 17 L. The API RQ L lines are used by
the device to request an interrupt from the
computer at a particular priority level. The
API GR is the computer's response to an API
RQ L. The API EN signal indicates to a devict!
the status of another device on that interrupt
level. (There can be as many as eight devices
sharing any priority level.) I/O PWR CLR Hi:;
used to establish initial conditions, I/O SYNC
H is used for timing, and the I/O ADDR 12 L
to I/O ADDR 17 L specify the unique entry
point or trap address to a device service routine.

The status facility of the PDP-IS issues a pulse
called RD STATUS H. This is used by a device
to gate its status flags onto the I/O bus where
they are read into the central processor. This
signal can be issued by either an 10RS command or by a switch on the console (see
PDP-IS User's Handbook).

Automatic Priority Interrupt (API) Logic extends the PDP-IS program interrupt capabilities by providing interrupt servicing for as
many as 28 I/O devices with minimum programming and maximum efficiency. Its priority structure pennits high data-rate devices to
interrupt the service routines of slower devices
with a minimum of system "overhead". The
option pennits the device service routines to
access directly from hardware-generated entry
points, eliminating the need for time-consuming flag searches to identify the device that is
causing the interrupt.

3.6.2 The Memory I/O Controller
The option provides 32 unique channels, or entry points, for the device service routines, and
8 levels of priority. The four higher levels are
for fast access to service routines in response
to device-initiated service requests. Each of
these levels can be multiplexed to ~andle up to
8 devices assigned an equal priority, up to a
maximum of 28. The four lower levels are assigned to program-initiated software routines
for transferring control to programs or subroutines on a priority basis. Four of the 32 channels are reserved for these software levels.

3-4

The PDP-IS memory I/O controller handles all control
and data transfers between the internal core memory
and peripheral devices. It uses the following basic elements to do this:

The Addressable I/O Bus which includes th,~
shared I8-line data path, two lOP control signals (lOP 2 H and lOP 4 H) and two signals
signifying the direction of a transfer; RD RQ L
for a read into memory and WR RQ L for a
write out of memory.

The Multi-Cycle Data Channel Control Lines
which include a request line - DCH RQ L; a
command to the device to post its address
code - DCH GR H, and an ENABLE line DCH EN H. The multi-cycle facility will transfer data to or from memory at speeds of up to
250 kHz in 18-bit words along 18-line data
paths. The control lines also include 15 address lines to specify the address in memory
where the word count is stored.
The Single Cycle Data Channel Control Lines
which include the control signals used by the
multi-cycle data channel, plus one other to
signify a single-cycle request as opposed to a
multi-cycle request. This is called SING CY
RQ L. A device can operate with this facility
in one of two modes: burst mode or nonnal
mode. Burst mode allows a device to carry on
back to back transfers at 1 mHz in one direction only. If the device needs to either change

direction or slow down, it must drop back
into normal mode which requires resynchronization at each transfer and thus has a 3 to 5 J.Ls
latency.
An Increment Memory Control Line which,
when enabled, causes the I/O processor to increment the location normally specified in a
multi-cycle data channel request as the word
count. However, the cycle stops here. The
current address is not incremented and no data
is transferred. If the count overflows, the device is notified.
An Add to Memory Control Line which causes
the I/O processor to add the contents of the
18 data lines set up by the device on the I/O
address lines to the contents of a memory location specified by the device. Both words
must be of the same sign. If the sign of the
sum is different, then an overflow pulse is sent
to the device.

3-5

Table 3-1
Summary of PDP-IS Input/Output Facilities
Facility

Remarks
Data Transfers To/From Memory

Multi-Cycle Data Channel Input

Used to transfer data directly to core memory in up to
18-bit bytes at high speed (250 kHz). Cost is low but
memory overhead is high.

Multi-Cycle Data Channel Output

Used to transfer data directly from memory in lip to
18-bit bytes. Cost is low and memory overhead is high.
Maximum speed is 188 kHz.

Add to Memory

Used to add the contents of a device register to the contents of a specified core location in 18-bit bytes. Good
for signal averaging. Maximum speed is 188 kHz.

Increment Memory

This facility allows an external device to increment the
content of a core location by I. Useful for gentlrating
histograms. Maximum speed is 500 kHz.

Single-Cycle Data Channel Output

With this facility a device can transfer a burst of data
from core memory at I mHz in 18-bit bytes. It is expensive to interface to and should be used for very high
speed devices.

Single-Cycle Data Channel Input

Used to transfer a burst of data from a device to core
memory at I mHz per 18-bit word. It is expensive to interface to and should be used for very high speed devices.
Data Transfers To/From CPU

Addressable I/O Bus

With this facility, devices can transfer data in 18-bit bytes
to or from the central processor. Cost of interfacing is
minimal. A typical transfer rate is one transfer every

200 J.l.s.
Command and Status Transfers
Addressable I/O Bus

Command and status information can be transferred to
or from the CPU in the same manner as ordinary data.

Read Status

'This is a special facility designed to allow the user to
monitor all vital flags in the system. Each device is assigned a bit for its flag(s), which is read onto the addressable I/O bus and into the CPU when the Read Status
command is given. No two devices should use the same
bit. See the PDP-IS User's Handbook for bit assignments.

Skip

The addressable I/O bus allows the computer to test the
status of a flag (typically) by issuing a pulse which will
echo if the addressed flag is up. Every flag that posts a
program interrupt must be identifiable by the skip facility.
Interrupts

3-6

Program Interrupt

All devices share a common program interrupt line.
When a device posts an interrupt the computer is forced
to location 0, bank 0, and then on to a service routine
designed to identify the requesting device using the skip
facility. The process requires CPU and memory overhead and takes time.

Automatic Priority Interrupt

This facility reduces the time to service a requesting device and establishes a hierarcy among devices so that important interrupts can be handled quickly and without
in terference.

CHAPTER 4
PDP-IS INTERFACING

4.1 INTERFACING TO THE CPU I/O
CONTROLLER

a. Addressable I/O Bus

In general, devices rely on the CPU for control and
status information, and on memory for high speed
data. An extensive monitor system running in the
CPU usually commands the operation of the entire
computer complex. It can initiate a peripheral such as
a disk into the correct operating mode and start it
when the entire system is ready. The transfer rates
for these commands are low, so that the CPU can
afford to provide much of the basic control logic for
such transfers, thus simplifying device logic. It does
this with an instruction set called lOT instructions
(Figure 4-1). Control data or status information is
transferred to or from the accumulator of the CPU
from the I/O processor under lOT control. The I/O
processor passes the data on or off the I/O bus cable
to or from the selected device.

c. Status and Skip Facilities

b. Program Interrupt Facility

Any device which is to interface to the I/O processor
for CPU communications must satisfy the needs of
four elements:

d. Automatic Priority Interrupt System.

Although API is a system option, any device designed
for the I/O bus should always contain API logic to
allow for future expansion.
4.1.1 A CPU Interface with API
As an example of an interface for a device to the CPU
I/O controller, a very simple peripheral is chosen that
can receive into its data buffer an 18-bit word from
the accumulator of the CPU, or can transmit the states
of its 18 contacts back to the accumulator (Figure
4-2).
This example has five basic components: addressable I/O bus logic, data register logic, contact sensor
and transmitter logic, program interrupt skip and status
logic, and API control logic.

CLEAR
AC IF = 1

OCTAL CODE =70

DEVICE SELECTION
(6 BITS)

SUB DEVICE
SELECTION
(2 BITS)
15-0050

Figure 4-1 lOT Instruction Format

4-1

a SKIP RQ pulse to the processor is identified
as the requesting device.

The Addressable I/O Bus Logic - decodes the
unique device and subdevice code which originates in the lOT instruction. This device can
now respond to the lOP pulses 1, 2 or 4 issued
by the same lOT to transfer data or cause
some control function such as "skip on flag".

The status logic is used to notify the CPU iJf
the status of each device. By issuing an 10RS
(read flags) instruction, the CPU can monitor
the system status. 10RS issues a pulse at IOP-2
time.

The addressable I/O bus logic also contains
input buffers for the 18 data lines on which
data is transferred.

Data Register Logic - This 18-bit register accepts data from the addressable I/O bus. The
data is strobed off the bus with one of the
lOP control pulses issued by the lOT instruction.

Contact Sensor and Transmitter Logic -- 18
switches are sensed by the transmitter logic,
and their contents can be transferred to the
18 data lines of the addressable I/O bus logic.
An IOP-2 control pulse is used to strobe the
data onto the bus.

Each device should be designed to strobe the
"OR" of all its interrupt flags onto a unique
pre-assigned I/O bus line when the 10RS lOT
is issued. 10RS is similar to a read lOT in that
the data strobed onto the bus is loaded into
the accumulator. Since all devices receive
10RS simultaneously the I/O bus will see a
composite of all device flags, and therefore
the status of the entire computer system.

Program Interrupt Skip and Status Logic The device notifies the computer of its need
for CPU attention by posting a program interrupt. All devices share the same program interrupt line so, to determine which device caused
the signal, the CPU goes through a polling
routine or "skip" chain (refer to PDP-IS
User's Handbook) where it issues a skip lOT
for each device. The device which echoes back
110 BUS
f-CONNECTORS - - .
OUT

, -i/o -;;ROCESSoR -,

CPU

i l
I
I
\00------1----1 CPU 110
I

ACCUMULATOR

CONTROLLER

CONT~~[I

...--.w.t_____..

LINES

~_---l_

I~Ri~~~~[T 14---~----------_._-___I l~i~~:~~T
LOGIC

STATUS LOGIC

ICLOC K

---f

ME~/~RY
CONTROLLER

I
I
I

DEVICE a
SUBDEVICE I~---..w-----+l
SELECT LINES

lOP ',2,41.1-_---tU_-------.I
CONTROL LINES

I
I
I
I
I
L _______ ..J
I

ADDRESSABLE
110 BUS
LOGIC

lOP
CONTROL
PULSES

110 BUS 00-171Mt-----eW._-----+l
DATA LINES

I
I

I
I
I
I
I
f.------------- ---- PDP- 15 - - - - - - - - - + - - - 1 / 0 BUS CABLE--+--

I
DEVICE

Figure 4-2 Block Diagram of CPU Device with API
4-2

]

API
EN IN

~------~------ ___________ _

I.I---W------.I

I
I

OUT

PROGRAM
INTERRUPT
SKIP a STATusl_---J.I,t__---~----~LI NES
API
EN OUT
AUTOMATIC

This status facility is useful for checking
interrupts when API is not available on the
system.
The Automatic Priority Interrupt Logic There are four API levels assigned to peripherals on the I/O bus cable. They extend lthe
capabilities of the program interrupt facility
and save CPU time for polling. An API request at any level forces the CPU to jump or
"trap" to an address specified by the device.
In this way, the device is immediately identified and polling time is saved. The API logic
facilitates this option for the device, providled
the option is available in the I/O processor.

4.1.2

The Logic

able I/O bus logic and an lOT READ signal
strobes the contact switches onto the data
lines, I/O BUS OOL to I/O BUS 17L. It also
strobes a signal called RD RQ L which tells
the CPU of an IN transfer.

Figure 4-3 shows the detailed logic of each of the
blocks in Figure 4-2. The following descriptions relate
directly to this diagram.
This peripheral can be programmed to either read a
data word from the contact sensor switches or write
a word from the accumulator into the data buffer
according to the whim of its programmer. A clock
is provided to post interrupts or API requests at
regular intervals, to which the program can respond
by issuing read or write lOT's.
This device has no known practical application. It is
used here because it illustrates the logic and timing
necessary to mate more complex devices to the
PDP-l 5 , yet is relatively easy to understand.
The device works in the following way:
a.

The contact sensors are set to whatever word
is to be read.

The programmer selects his read or write subroutine.

The M401 clock is enabled.

The clock sets FLAG which enables the API
REQ flip-flop of the MI04 Multiplexer. On
the next I/O SYNC H, an API 0 RQ L and a
PROG INT RQ L signal are issued simultaneously. If API is available and enabled, then
the CPU will trap to memory location 44. If
API is not available, then a program interrupt occurs and the CPU traps to location
00. Each of the signals used by the API
control logic is listed in Table 4-1, and the
timing is given in Figure 4-4.

If the CPU responded to an API break, then
it is programmed to jump to its appropriate
read or write routine.
If the CPU could only respond to a program
interrupt request (because API was unavailable or disabled), it would jump to a polling'
routine where it would issue the lOT SKIP
instruction. When this lOT selected the device
and issued 10PI, then lOT SKIP would be
generated and an echo pulse called SKIP RQ L
would be sent back to the computer. The
CPU would be forced to skip its next instruction, and the program, recognizing this device,
could jump to the read or write routine.
If the programmer wants to read in, then the
program would issue an lOT with IOP2 selected. The lOT is decoded by the address-

If the programmer wants to write, then the
program would issue an lOT with IOP4 selected. The lOT is again decoded and an lOT
WRITE signal generated. This pulse strobes
the data from the accumulator to the data
register of this device.

When a transfer has been completed, an lOT
CLR FLG is issued and both API RQ and
FLAG are reset.

Detailed descriptions of each signal and its timing relationships to associated signals are given in Table 4-1
and Figure 4-4. These should be studied in detail before a design is attempted.
The designer should take note of the following points:

All I/O bus signals are received by an M51 0
module and transmitted by an M622 module
with the exception of API EN IN and API
EN OUT, which are handled by the MI04.

b.~

PROG INT RQ and API N RQ are anded together to generate PROG INT RQ. This technique gives each device the option of using
API or PI but guarantees that when API is
used, it will be honoured over the interrupt.
If PROG INT RQ were not gated with API
N RQ, then the I/O processor may see the
PI request before the API since the former is
asynchronous, and service it first.

The logic should be designed so that if the
MI04 is removed from the device because its
corresponding computer does not have the
API option, then the PI facility will still operate. This is effected by wiring a pull up resistor
of an M113 module to the input of the inverter
which drives the corresponding AND gate.
This forces a logical one to this gate when
the MI04 module is pulled.

It is good practice to gate the two sub device
bits into the MI03 module with the device
bits, when the sub device codes are not used.
This frees up remaining codes for other devices. Note that this practice was not followed
in our ¥i~aniple.

Make sure that all flags and registers are cleared
by I/O PWR CLR, or the device may post
4-3

spurious interrupts during power up. If the
device must be powered up while the computer
system is on, then an internal power clear
signal must be generated to avoid erroneous
flagging.

Do not clear the interrupt flag(s) with the
clear flag (11) signal in the MI04. Clear thi:;
flag(s) with an lOT. Otherwise the I/O processor may clear the flag before it acknowledges the request.

The following subroutine illustrates how this device can be programmed. It assumes for simplicity that the device dock
is enabled, and that no other programs or devices are operating on the system. If any switch is up on the console switch
register, then read operations are performed. Otherwise a write operation is carried out .

START

/Clear all system flags
/Clear the accumulator
/Enable the PI
/Set up the API control
word and enable API
/Wait loop
/Retum to the beginning

.LOCO
000000
JMP SKIP

/PI setup
/Go to skip chain

.LOC44
JMSDATA

/ API trap point

.LOC 2020
lOT SKIP L
HLT

JMSDATA
JMP * 0

/Check the flag
/This flag was not
up. Since there are no other
devices operating, something
is wrong.
/Go to service routine
/Go to beginning

DATA

000000
CLA
LAS
SZA
JMP READ
JMPWRITE

/Subroutine entry point
/Clear accumulator
/Load switch register
/Skip if AC=O
/Not zero, go to read
/Zero, go to write

READ

CLA
lOT READ
DAC TEMPI
DBR
JMP * DATA

/Clear the AC
/Read data in
/Store it
/Debreak and restore
/Retum

WRITE

CLA
LAC WORD
lOT WRITE
DBR
JMP * DATA

/Clear the AC
/Get the data word
/Write it
/Debreak and restore
/Retum

SKIP

4-4

.LOC 2000
CAF
CLA
ION
TAD (40000
ISA
JMP.
JMP START

This page intentionally left blank.

4-5

Table 4-1
CPU Interface With API

Signal
Mnemonic

Input Cable
Pin Number

API 0
ENH
(IN and OUT)

2BLl

This enable si gnal, one of four in the API system,
is a dc level 0 riginating in the I/O processor and
is daisy chaine d from device to device on the same
level. The MI 04 logic in each controller can
interrupt this level, cutting the level off all devices that foil ow it on the bus. A device receives
it as API 0 EN IN HI and transmits it as
API 0 EN OU TH.

Each device can post a request to its API level only
if the incoming API EN level is true. By posting a
request, the device immediately inhibits all controllers below it on the bus by removing the enable signal
to the next device. In this way, priorities on each
level are established when devices request simultaneously; the first device on this level will have highest priority, the second next priority, etc.

I/O SYNCH

2ABI

The I/O proce ssor clock pulse issued every microsecond. It is a I mHz 250-ns pulse.

This signal is used to synchronize API RQ to the
I/O processor.

API 0
GRH

2Bl1

One of four p ossibll! signals issued by the I/O
processor indi cating that it grants the API request
at the corresp on ding level, in this case level O.

The device uses this signal to gate the address of
its API level trap address onto the I/O ADDR
lines by posting the API ENA flag.

I/OPWR
CLRH

2ASI

System clear signal generated in response to I)
Power on or 0 ff; 2) CAF instruction; 3) I/O
RESET key. It is a I mHz, 250-ns pulse.

This signal is treated as an initializing signal for
all devices (controllers attached to the I/O bus).
All registers are reset to "initial" status.

5
..... 11

SDOH
.....DS5 H

2ATZ

The device an d subdevice select lines decoded
from I/O bits 6-13 of the lOT instruction .

These signals are decoded by the addressable I/O
bus to select the device.

lOP I H

2ADI

Micro-progra mmable control signal which is part
of an lOT inst ruction. Decoded from bit 17 of
the lOT.

Used for I/O skip instructions to test a device
flag or other control function. Cannot be used
to read a device buffer register.

IOP2H

2AE1

Same as lOP I except it is decoded from bit 16.

Usually used to effect a transfer of data from a
selected device to the processor, or to clear a device
register or flag, but may be used for other control
functions. May not be used to determine a skip.

IOP4H

2AHI

Same as lOP I H except it is decoded from
bit 15.

Usually used to effect transfer of data from the
CPU to the device or control. May not be used to
determine a skip condition or to effect a transfer
of data from a selected device to the CPU.

15 .....32

I/O BUS 00 L
.....1/0 BUS 17 L

IABI
IAV2

18 data lines which constitute the bidirectional
facility for tra nsferring data in bytes of up to 18
bits between t he device and the CPU (in this case).

These data lines (I/O BUS 00 L - I/O BUS 17 L)
convey data between the AC of the CPU (via the
I/O processor) and the device data register. This
is the most significant bit, 00.

33,34

I/O ADDR
12 L, 15 L

IBK2,
IBS2

One of fifteen lines which constiute an input bus
for devices th at deliver address data to the
processor.

This address bus in this case is used to deliver the
device's API trap address 44 during its API break.

API 0
RQL

2BHI

One of four API request signals on channels 0-3.
This signal is set by the device. The signal is
raised by the MI0410gic at I/O SYNC time only.

The device. uses this signal to inform the I/O
processor of its request for API priority level 0,
the highest of the four.

PROGINT
RQL

2ALI

This signal ca uses the program to trap to location
000000 if the priority interrupt system is enabled.
The instructio n resident in location 000001 is
fetched and e xecuted.

A device delivers this level to the I/O processor
to request interruption of the program in progress
in order that the device be serviced by the CPU.

SKIP
RQL

2Al1

The return of the signal to the I/O processor
during 10PI indicates that an lOT instruction
test for a skip condition has been satisfied. The
PC is subsequ ently incremented by one.

Used by a device to inform the program of the
state of its interrupt flag.

RD
STATUSH

2API

A signal issue d when the CPU issues an 10RS
instruction or when the console switch is placed
qnl/O STATUS.

Used by the device to gate its status onto the I/O
bus data lines (one line per status bit) which is
then read into the AC of the CPU.

RDRQL

2AMI

Indicates to t he processor that the device is
sending it a d ata word.

Used by the device to specify to the I/O processor
an input-to-CPU data transfer is required. its
absence is interpreted as an outgoing transfer.

Signal
Number

2AP2

Signal Definition

Signal Function

I
I

4-6

AUTOMATIC PRIORITY INTERRUPT CONTROL LOGIC

1
---------------1
I
M104

+sv ll

MULTIPLEXER

I
CD

INPUT CABLE

----~+--<)-----------..,,-RfQ-(-0I-H-1)-t2-........- - - o - - t - - - - - - - - - - A P I OENOUTH

API OfN IN H

APlOENOl1TH~2
... _

';0 SYNC "

~ENA(l)L

API ONA(I) H

API ENI(l)H

API RfO(l)L

API REQ(1) H

I
I
I
I
I
I
I
I

o
El

ClEAR FLAGL J1

';O,.....ClIH

FLAG (I)H

l/OADOl12l

M622

1;0 AllOR IS l

CLRRQ l

PROGRAM INTERRUPT SKIP AND STATUS FACILITIES

r.;;--------l
+JV

I
API REG

113

API RECl (1) l

~AP'ORQl

1111:>0-----,

(1) H

'ROG INT RQ l

SJ(!PRQ l

swtTCH~

OUTPUT CABLE

IT
OM", ,

I08U,02l

10 BUS 03 L

10 BUS 0... L

o""'"

~
IOM06l

,0,::::

ADDRESSABLE 110 BUS LOGIC

SDOH ~Srn.;t-S::F_~_HI~'
V

D,<oTAOf'LOH

lQOnOH

IOAOOS!WL

'o~'"''

O,",",'"

IOAOOROi! L

10 AbDR07 L

IQADOfI.ClEIL

CCR
ROl

II
Ml

ClR FLAG H

PWRClRl

DSO~, --f2D2
,
,

DS5i~
t-~~2
~N2
L2

®
@

~"~
'O"H-f'P I
OP4H

-+p L

DATA REGISTERS

C»~-------,---- - ------,

~ "'16 I, ___

,
:

CDC

M21. 0,

---~-~~~~~--+--~

IO'U'llOl

IOil:USOIL

I/O BUS 01BH

VO!US 17!H

@
I05l)S 17L

Figure 4-3 Logic Diagram of the CPU Device with API

AUTOMATIC PRIORITY INTERRUPT CONTROL LOGIC

INPUT CABLE

Q:.'~"
___

APiOENIN H

------+----( )--------------~

I
@

~ --.~:-;;;:-;,-;:;;;-;---l

H:2

0
An OENOUTH
APlteQ(O)H~ APlaENourH~

APlOENINH

I/O SYNC H

APlENA(1)l

API ENA(I) H

AP'Ie.ll(l)l

oFl

N'lENa(l)H

APlRfQ(1)L

+sv

J'....

I
I
I
I
I
,I

API0GRH

API REQ(1) H U2
CLfARRAGL Jl

iYt622

1/0 ADDl 12 L

""'12

1,0 MlO. 15 l

-, rSIGNAL
NO.

I/OIVII<CLRH

flAG (1)H

I
_J

SIGNAL
NAME

I/O
SYNC H

34
35

APIa RQL
PROG INT
RQ L

Fav~,-- A;'-;;(I~ - ,
~

Af'IORQl

API RfQ
(1)1<
'ROG INT RO l

32
33

6-11

_J
loaus 17L

L __ _

13
39

ADDRESSABLE VO BUS lOGIC

MS.! <';'D:dHFI---~---------_-_-_-HI~'1
~
Jl

I
I

II
Ml

CLR

VOWSOOL

I/O SUS 01 L

I
I

V08U517L

'" RQ l

~N2

'~"t+-G2
2H

10MOOL

TOtUS01L

2.5
0

(0)

API ENA
(1) H
1/0 ADDR
12 Sl5L

(1)

2.5

(0)

DS5 H
DSO H
SDO H

(I)

2.5

APIO
GRH

lOP 1 H
(SKIP RQ L
CLR RQ
CLR FLAG
IOP2 H
RD RQ L
(lOT READ)
lOP 4H
lOT WRITE

(0)

(I)

2.5

(0)

(1)

2.5

(0)

(1)

2.5

(0)

;

~2
~

.. "i"i

I..\.

~"i

))

tot

"i'\

(.(

"10"10

I J

))
_\

iii.

y\
l

(\) I I

. "<
.

r-750nS-1 ..--. ',de ,.:

7<=

'\"10

(.,

~?"''''1 •. ,

~"750ns..,t~ ... ~·"10'\

,. "c.'\"

\')

'};,

"i"i

\.\. I,

..I..

DATA STROBED HERE

)) I.

))

AC ON BUS

.r--k}~g

DATA ON
BUS

THIS TIME IS DETERMINED BY THE
SERVICING SUBROUTINE

K2
L2

10P4H--f'>

(0)

1 MEANS ASSERTION LTHIS TIME IS A FUNCTION OF
CPU AND I/O ACTIVITIES
o MEANS NEGATIVE

D"l~ t-:~

IO'

CU.fLAGH

PWR ClRL

2.5

(0)

I~D2

(I)

2.5

STATES
OF
110 BUS

ROL

DSOH~
I

(0)

(I)

5DL

SDOH

2.5

(1)

PROGRAM 'INTERRUPT SKIP AND STATUS FACILITIES

(1)

FLAG(IlH

CLlitQl

POLARITY
(VOLTS)

AC ON
BUS

LAC IS CLEARED HERE IF MB14 IS A ONE
NOTE THAT DATA CAN BE READ INTO THE AC FROM THE
DEVICE AND THEN READ BACK TO THE DEVICE AS A
CHECK.
15-0041

DATA REGISTERS

Figure 4-4 Timing Diagram of the CPU Device with API

I~~--------~-----------i

. M216 I, ___ i i jM216O
,

CDC

----~--~~~--~--~

1/0 IUS 178 H

Figure 4-3 Logic Diagram of the CPU Device with API
4-7

-Multi-Cycle Data Channel Logic is basically a single
DEC module Type M I 04 which handles the basic control and timing signals of the multi-cycle data channel.
Each device using the multi-cycle data channel is
assigned two memory locations; one for its word
count, and one for its current address.

4.2 INTERF ACING TO THE MEMORY I/O
CONTROLLER
The primary task 01' the memory I/O controller is to
serve as a high speed data path between memory and
storage peripherals such as disks, drums or magnetic
tape. It serves this function with two facilities; a
single-cycle data channel for very fast (up to 18 x 106
bits) transfers or a multi-cycle channel for slower (250
kHz per word) rates. However, the memory I/O controller also provides two other features: an increment
memory service with which a peripheral controller can
specify any PDP-IS internal memory location and
increment it by one at a maximum rate of 500 kHz;
and an add-to-memory feature where a peripheral can
add the contents of any PDP-IS memory location to
the contents of its data register at 188 kHz.

These registers are identified by a device as it requests
service by the control logic. Then, the memory I/O
controller increments each location during the multicycle operation.
Figure 4-6 is a detailed logic diagram of each of the
blocks in Figure 4-5. The following is a description of
the functions performed by it:

The peripheral is initiated manually by:
(1)

Setting the MODE switch to READ
or WRITE

(2)

Setting the data switches

4.2.1 The Multi-Cyc1e Data Channel Peripheral
Any device controller designed to use the multi-cycle
data channel needs six elements: the five used by a
device using the CPU I/O controller plus multi-cycle
data channel logic (Figure 4-5).

(3) Setting the ENABLE switch to ON

When enabled, the M401 clock sets DCH
FLAG which in turn enables DCH RQ of the
M104. The next I/O SYNC pulse sets DCH
RQ which then posts DCH RQ L back to the
memory I/O controller.

Each of the basic elements described Jor the CPU I/O
controller are used in this device, with only minor
differences in the logic.
110 BUS
r-CONNECTORS

.
' - 1 1 0 PROCEsSOR

I
I
CPU
ACCUMULATOR

I
~

CPU

1/0

CO~TB9LLER

I
I

II
I

I
I

MEMORY
1/0
CONTROLLER

--.. ""'--<0

DCH
FLAG

CLOCK

r?"0N
·OFF

. \.

READ

WRITE

_._.__ .._--- ._------"

AUTOMATIC
PRIORITY
INTERRUPT
CONTROL
LOGIC

----- .---_._._.

----

---------------

-1

- - - - - - -----

----------- -

PROGRAM
INTERRUPT
SKIP AND
STATUS
FACILITIES

FLAG

OVERFLOW

---~

DEVICE Ii
SUBDEVICE
SELECT LINES

I
I
I

ADDRE SSABLE
1/0 BUS
LOGIC

lOP 1,2,4
CON TROL LINES

110 BUS 00-17

DATA LINES

I
L ________ -.J

DATA REGI STER LOGIC

_-- 1-----

CONTACT SENSOR
AND
TRANSM I T LOGIC

I
I

1 . - - - - - - - - PDP-15

MODE
SWITCHES

OVERFLOW

API
CONTROL
LINES

I
I

DATA CHANNEL
CONTROL LI NES

.J-

I
I

;

" -'-

NORMAL

MULTI
CYCLE
DATA
CHANNEL
CONTROL
LOGIC

PROGRAM
INTERRUPT
SKI P a STATUS
LINES

INHIBIT

OUT

I
I
I

MEMORY

-IN

OUT

- - - - - - . . . j . . - I / O BUS CABLE .....0 i 4 I . - - - - - - - - - - - - DEVICE - - - - - - - - - -

Figure 4-5 Block Diagram for Multicycle Data Channel Device

4-9

The I/O controller responds (some time later)
with DCH GR H, setting DCH ENA of the
MI04and posting I/O ADDR 13L, 14L, which
signify address 30, the word count location.
On the next I/O SYNC pulse the M104 flipflop DCH EN B is set. Its purpose will be
explained later.

If this is the last transfer of a block, then the
preset word count register (location 30) overflows (clears to zero) and an I/O OFLO H
pulse sets the I/O OFLO flag. This flag then
causes either an API request on level 0, or a
program interrupt request. The result is the
same as the previous example.

The I/O controller increments location 30,
which is hardware specified, and sends I/O
OFLO back to the device if this location overflows (2's complement). Regardless, it increments location 31 (unless + I -+CA INH is
posted during DCH ENA), the current address,
and proceeds to transfer data.

If the INHIBIT switch is enabled, then DCH
EN A (I) L causes a signal +I -+CA INH L to
inhibit incrementing of the current address location. (This feature is used by the DECtape
control during a search).

If both WR RQ Land RD RQ L are enabled,
then the machine goes into an ADD TO MEMORY mode whereby data is strobed onto the
I/O bus with IOP2 (the RD RQ L part),and
added to the contents of the memory location
specified by the CA register. The sum is reread into the same location, and also tran~;
mitted back down the bus where it is strobed
into the data register with IOP4 (WR RQ L
part). If the sum is of a different sign than
the two words, then a DATA OFLO pulse
occurs to set the DATA OFLO flag.

If the MODE switch is set to READ (RD RQ L
gate enabled and WR RQ L disabled), then
DCH ENB (I) L will gate onto RD RQ Land
signify to the I/O processor that a transfer into
memory is required. The I/O processor issues
a pulse on the IOP2 line. DCH EN B enables
the MI04 module at its optional select pin U2.
IOP2 becomes lOT READ, and the data is
strobed onto the data lines I/O BUS 00 L I/O BUS 17 L, and into the location specified
by the contents of memory location 31.

If the MODE switch is set to WRITE (WR RQ L
gate enabled but the RD RQ L is not) then
DCB EN B (1) L gates onto the WR RQ lL
line and signifies to the I/O processor that a
transfer from memory is required. The I/O
processor issues a pulse on the IOP4 line and
DCH EN B enables the MI03 module at its
optional select pin U2. IOP4 becomes lOT
WRITE and the data is strobed off the bus
(placed there by the I/O processor) into the
data register.

Detailed descriptions of each signal and its timing relationship to associated signals are given in Table 4-2
and Figure 4-7. These should be studied in detail.

Note that all I/O bus signals are received by an M51 0
and transmitted by an M622 with the exception of the
API EN IN, API EN OUT or DCB EN IN, DCH EN
OUT, which are received and transmitted by their
respective MI04.

The following program will exercise the multi-cycle data channel device. It assumes that no other program or device is,
in operation within the system. Set the enable switch, specify read or write and go .

START

4-10

.LOC 2050
CAF
CLA
ION
TAD (4000DO
ISA
LAC (775777
DAC30
LAC (4000
DAC 31
lMP.
lMP START

/Clear the system flag and
/the accumulator
/Turn on PI
/Set up the API control
/word and enable API
/Set up the multi-cycle
/data channel word count
land current address to
/2Kg and 4K g
/Loop until an interrupt occurs
/Go back to beginning

.LOCO

SKIP

OFLO

000000

IPI setup

JMP SKIP

/Go to skip chain

.LOC 44
JMSOFLO

/ API trap point

.LOC 2100
lOT SKIP L
HLT
JMS OFLO
JMP * a

/Check the OFLO flags
/Wrong flag - error
/Go to overflow routine
/Go back to the beginning

000000
CLA
CLL
lOT RDSTA
DACTEMP
IOTCLROFLO
RAR
SZL
JMS DAFLO
CLA
CLL
LAC TEMP
RTR
SZL
JMS 10FLO
JMP * OFLO

DAFLO

000000

DBR
JM * DAFLO

Note also that if the + 1 -+CA INH had been enabled,
the current address would not have changed and each
word would have been transferred to the same address.
This feature is useful when hunting for a specific word
such as a block number on DECtape. Each number
is transferred to the same location and checked against
the number needed. This feature is also useful when

/Subroutine entry point
/Clear the AC
/Clear the link
/Read the flags
/Store this status
/Clear the flags
/Rotate right (l7-+L)
/Skip if L=O
/Go to data overflow routine
/Clear the AC
/Clear the link
/Bring in the status word
/Rotate twice (l6-+L)
/Skip if L=O
/Go I/O OFLO routine
/Retum to beginning
/Subroutine entry point
/ } The add to memory sum
/
has overflowed. This subroutine
/
should set up a double precision
/
add routine.
fPrime API
fRetum to beginning

trouble-shooting I/O problems on the multi-cycle
data channel.

Note that the data could also have been read or written
under program control as it was with the CPU device ..
This is often a useful maintenance tool.

4-11

Table 4-2 (Cont)
Multi-£ycle Data Channel Device

Table 4-2
Multi-£ycle Data Chanuel Device

Signal
Number
I

Signal
Mnemonic
OCH
EN H
(IN and OUT)

Connector

I Pin Number I

Signal Dei"lIldioa

2BV2

This enable signal is a de level which originates
at the I/O processor and is daisy chained from
device to device. The M I 04 logic in each device can interrupt this level. clitting the ievel
off all devices that follow on the bus. A device
receives it as DCH EN IN Hand transmils it as
OCH EN OUTH.

Si@aal fUllction

I Each device can place a DCH r,'quest only if the

incoming IX'H E:-.I lew I is true. By posting a requ~st. the devi~c iml,1cdiatcly inhibits all controllers below it on the bus. In this way priorities
on each level are established when devices request
sim ultaneously.

Signal
Number

Signal
Mnemonic

Connector
Pin Number

Signal function

Signal Definition

DCH RQ L

2BS2

A signal from a device to the I/O processor indicating a request for a multi-cycle data channel
transfer, raised at I/O SYNC time.

This signal is interpreted by the I/O processor. It
implies that some device wants to carry out a
multi-cycle transfer or an increment memory, or
add-to-memory.

+!-CA
INH L

2BEI

If the I/O processor sees this signal during multicycle transfers, it inhibits normal incrementing
of the device's assigned current address memory
location.

This facility is used by such peripherals as DECtape and magnetic tape when they search for
records. It is also very useful during device checkout to prevent writing throughout memory and
destroying the controlling program.

I/O SYNC
H

2ABI

The [(0 processor clock pulse issued every microsecond. It is a I mHz. 250-ns pulse.

This signal is lIsed to synchronize device control
timing sllch as Al'l RQ or DCH RQ to the I/O
processor.

DCHGRH

2BT2

Issued by the I/O processor when it acknowledges
a device's DCH RQ L.

The device uses DCH GR to gate the address of
its word count onto the If0 ADDR lines of the
I/O bus.

WRRQL

2BBI

Indicates to the I/O processor that the device
requires a transfer from memory.

The device use; this signal to inform the I/O
processor that it wants a word from memory
(during a multi-cycle data channel transfer).

API 0
ENH
(IN and OUT)

2BLl

This enable signal, a dc level originating 111 the
I/O processor and daisy chained from device to
device on the same level. The M I 04 logic in
each controller can interrupt this level, wtting
it off all devices that follow it on the bus. A
device receives it as API 0 EN IN Hand transmits it as API 0 EN OUT H.

Each device can post a request to its API level
only if the incoming API EN level is true. BY
posting a request, the device immediately inhibits
all controllers below it on the bus. In this way
priorities on each level are established when devices request sim ultaneously: the first device on
this level will have highest priority: the next, etc.

RDRQL

2AM!

Indicates to the I/O processor that the device
is offering it a data word.

Used by the device to specify to the I/O processor
that an input-to-CPU data transfer is required.

API 0 RQL

2BHI

One of four API request signals on channels 0-3.
This signal is set by the device. The signal is
raised by the M 104 logic at I/O SYNC time only.

The device uses this signal to inform the I/O
processor of its request for service on API
priority level 0, the highest of the four.

PROG
INTRQ L

2ALl

This signal can cause the program to trap to lo. cation
000000 when no higher priority action is

API 0
GRH

2BJI

One of four possible signals issued by the I/O
processor indicating that it grants the API request at the corresponding level.

The device uses this signal to gate the address of
its API level trap address onto the I/O AD DR lines.

I/OPWR
CLRH

2ASI

System clear signal generated in respon~e to I)
Power on or off; 2) CAF instruction; 3}, I/O
RESET key. It is a I mHz. 250-ns puIs;'

Treated as an initializing signal for all devices
(controllers attached to the I/O bus). All registers
are reset to "initial" status.

DSOH-DS5 H
SDOH

2AD2
2AT2

The six device select lines decoded from bits
6-11 of the lOT instruction, and the two subdevice select lines decoded from bits 12 and 13.

This signal together with DS I - DSS and SDO,
SD I, is decoded by the device select logic in the
controller. which responds to its unique code only.

lOP I H

2ADI

Micro-programmable control signal to effect an
lOT instruction-specified operation within a
device. Decoded from bit 17 of the lOT.

Used for I/O skip instructions to test a device flag
or other control function. Cannot be used to read
a device buffer register.

2AEI

Same as lOP I H. Decoded from bit 16,. It is
also issued during a multi-cycle data channel
transfer into memory.

Usually used to effect a transfer of data from a
selected device to the processor, or memory, or
to clear a device register or flag, but may be used
for other control functions. May not be used to
determine a skip.

Same as lOP I H. Decoded from bit 15. It is
also issued during a multi-cycIe data channel
transfer out of memory.

Usually used to effect transfer of data from the
CPU or memory, to the device or control. May
not be used to determine a skip condition or to
effect a transfer of data from a selected device to
the CPU.

7~13

17,34

41,35
42,36

4-12

IOP2H

IOP4H

2AHI

I/O BUS
OOL-I7L

IABIIAV2

18 data lines which constitute the bidirrctional
facility for transferring data in bytes of up to 18
bits between the device and the CPU or memory.

These data lines convey data between the data
register Of the device and either memory or the
AC of the CPU

I/OADDR
12 L, 13 L
14 L, 15 L

IBK2
IBS2

Those lines which consititute an input bus for devices which must deliver address data te the I/O
processor.

This address bus has two uses:
a. To deliver the device's API trap address
during its API break.
b. To deliver the device's word count address
during a muIti-cyc\e DCH transfer, or an
add to memory operation.

in progress. The instruction resident in location
000001 is fetched and executed.

A device delivers this level to the I/O processor
to req uest interruption of the program in progress
in order that the device be serviced.

SKIP
RQL

2AJI

The return of the signal to the I/O processor
during 10PI indicates that an lOT instruction
test for a skip condition has been satisfied. The
PC is subsequently incremented by one.

Used by a device to inform the program of the
state of its interrupt flag.

RD
STATUSH

2AP!

A signal issued when the CPU issues an 10RS
instruction or when the console switch is placed
on I/O STATUS.

Used by the device to gate its status onto the I/O
bus data lines (one line per status bit) which is
then read into the AC of the CPU.

I/O
OFLOH

lBEl

This sig."1al is issued during the first cycle of a
multi-cycIe data channel transfer, if the content
(2's complement) of the word count assigned the
currently active data channel device becomes .
zero when incremented.

This signal indicates to the device that the spedfied number of words have been transferred at the
completion of the transfer in progress. It is normally
used to tum off the respective device and to initiate
a program interrupt or API request.

DATA
OFLOH

IBDI

This signal is gated onto the bus by the I/O
processor during the third cycle of an add-tomemory operation, when the sum (l's complement) of two like-signed numbers has an opposite
sign.

This signal is used by the device to notify it an
incorrect sum occurred because of overflow, during
an add-to-memory operation.

MULTI CYCLE CHANNEL CONTROL LOGIC

o
OCH REQ(O) H

OCHENOllTH M2
DCH'NA(I)L

@IJOSYNCH
DCHEt'<A(')H

SYNC H

DCHENOUTH

~I"'AOO"JL @

~I/OAIlO'''L @
POLARITY
SIGNAL

t-N-'-'-U~M..:.B..:.E~R+_...,;,,:N__A..:.M;,:E:.-.+V--O:.:L:.:T-A:.:G:.:E+--:--------!

® DCH GI: H 1.""';.'",,0'--.,---o-----+---+-----...!-r-",-.~,--------c
£2

SIGNAL

DCH Gl4NT H

I I
SYNC H

o
1

DCH
FLAG

o
a

DCH

RQ L
DCH
GR H
CLEAR
FLAG L

PROGRAM

INlEIIRUPT

SKP

AND

STATUS

DCH
ENA (1) L

FACI.JTES
l/OBUSI6L

DCH
ENB (1) L

@
I/O BUS 17l

@ API 0 EN IN H ---I-~_:;~:;;:;;;------_:;:_:::==f)b-<D--1--_o_-___!'---

DATA OFtO (1) l

AJI1'REQ(O)H

VOAODR

API 0 ENA(1)H

o
o

A?lii ENS(ll L Fi

API 0 ENa(l) H El

OUTPUT CABLE

API 0 REQ(I) l

--+-__---J-r---.r

@APlOGltHMS;.;'O=----t_--()-_ _ _ _---1_ _ _
E2

API 0 REQ(11 H

Al'IGRANTH

CLEAR FlAG L Jl

ell 0fQ L

OR-O FLAG (I)H

--------------~SOL r-----------------,
i
CLRAPI RQ l

ADDRESSABLE' VO BUS LOGIC

oJ2

soot<

I
I
I

12L

10PI~--tP

lOP ,H--{32

IOP'H~

2.5

o
o

2.5 f - - - - - - - - . . l .

2,51---------

2,5

1
1

2,5

f--------

1-------

I/O

2.5

OFLO H

OFL 0
FLAG(l)H

2,5

i-- 1J,LS-i,.h
2a.5l--.h.-f

1/0

SYNC H

DCH
FLAG

DCH
RO L

DCH
GR H

CLEAR
FLAG L
CONTACT,SENSOR AND

DCH
ENA(l) H

TRANSMIT LOGIC

DCH

I/O BUS O~ L

2.5

o
2,5

2,5

o
a

2,5

lOP 4 H

I/O

2,5

OF La H
1/0 OR DATA

I/O BUS OOL

o FLO (1) H

IIIIIIIIIII~I

2,5 ~---l,.,'l
I J
a
~
2,5

DATA
ON BUS

L-....,

17_34

OSSH~~

",-----+:,'

tNa(lJL

~5 ..

IOP 2 H

DCH
ENB (I) H

O"H~02

1111111111
I _ _ _ _ _ _ _\~

VOBUS17L

I
I
I
I
I

(!)

2~5

SI<II'RGl@

I
I
I

1<:1 a.R

PROCINTR®

I
I

DATA REGISTER LOGIC

so H

VOAOOR:
ISL

205~.

2.5

2,5

lOP 2 H

DATA
OFLO H

2,5

f - - - - - - -........'1

1---------

STAT ES
( APPROX)
l'OTlO H

Ell
Fli
I
I

- - - - - - - - _______ J

IIoIU517L

Figure 4-6 Multi-Cycle Data Channel Device Logic

110 &us 178 H

MULn CYCLE CHANNEL CONTROL LOGIC

, -""7sv:-- -M~ :- ~ ~I-;:;-;;-; - --I
I
DCH ItEQ(O) H

0~S~CH r;~~--~o-----------------~~

DCHENOUTH~2 OCHENOUTH 0
OCH ENA(I) L

M622

J,A:l ADOR 13 l

DCH 'NA(I} H

PI '. .

M62,

1(0 AOO""

POLARITY

SIGNAL
N UMBER

SIGNAL
NAME

VOLTAGE

I/O
SYNC H

LM>:;;';;,:::...-,----<>----------t-------+-------4--r"""'l

DOt GO H

OCH GRANT H

4---=-=~-------~=:..-.:.-J
AUTOMATlC PRIORITY INTERRUPT

CONTROL LOGIC , -

""7SV:-'- - M~ :- ~ ~I-;:;-;;-; - --I

PROGRAII

INTERRU'T

STATUS

FACLITES
I/OBUS16L

DATAOfLO 0) l

1/0.A.DDR

SYNCH

9,
o
me ENS(1) l Fl

-----L---o-------------1r-'

""0 ENA(I) H

. p - - - - , API 0 ENI(1)H
APIC REQ(1)L

API 0 REQ(l)H

o
o
El

ClfARFtAGL JI

·IOIU5IO L

0VOI'WRCUtH

CLRR£QL

CL!!!L.~~

OR.O FlAG(l)H

r----~

----- :----:1-0.:1

I
I

0,,"

M>J.
!
~

IOPIH~

1H2

~~
L2

0
1

DCH
ENA(1 I L

0
1

DCH
ENBIIlL

0
1
1

2.5

0
1

2.5

SKIP""

IOP<H-[3P:

2(}
2~5

1,1

\"f

1.1

\- }

\ "~

I'"

~-~;--t----

..L II/O AOOR 13 L,14Ll"I·
\ ~'_~_--';,_(_I_/_O_A7D-D-R-13-L-,-14-L-~2:.r---7-(---~ (RD RO L 1 @ \ .'1...__..li\.......
~ (
(RD RO L 1 @
~

2.5

1\.-

o ~--------------------------------~I~~------------

2.5

o ~-----------------------------~------J
C

I--- TRANSBFAE : ~~~:C2'\;0 KHZ -----I

!--1jJ.s __ 1

2.5

DCH
FLAG

2~5o

DCH
RO L

DCH
GR H

0
0

CLEAR
FLAG L
CONTACT.SENSOR AND
TRANStIIT LOGIC

1
1

DCH
ENA( 1 I H

17-34

0
t

I
I

I/O Mool

0
0

DATA
ON BUS

lOP 4 H

I/O
OFLO H

"J'~·""--I/O BUSOll

IOP 2 H

DATA
OFLO H

Im",PL

b J :

STATES
(APPROXI

2~5

2.5

2(}
2 .5
0

2~5
o

2.5

0
1

2.5

1----* "'23P. s --------I

1-*"23P.S---!

.tl-.n.-.. .

IIIIIIIIIII~'"
;
"I

VAt
J"

.1- \

W1~~/(""I'IL-_f/ _____\+I ___---:(-.__-+// __
) ! ~ -'I
)
\
\

'UI~f ~
(

(I/O ADDR 13L,14Ll

~ (WRROLl

Y J"

J. J.

\. \

\ \

\..1 \'U~I...I~+--(~ll-/-o-----------'!:I"I
\

STROBE DATA HERE _

I
!

STROBE DATA HERE

2:5~-----------------------------------~(~~-L~/:O_::O_~F:L_:O:_:::_:~:~:~D:A~TA::O~F~L~O~::::::::

1
1
0

OR ADD TO MEMORY TRANSFER

0
0

>- MULTI CYCLE OUT TRANSFER

(RDROL)®

'----...

"L.._ _ _?-__

ADDR 13L,14Ll

"~(WRROL)

(RDROL1®

2.5 ~--------------------,I

t
I

0
1

I/O OR DATA
o FLO (1) H

Fli

,-.1

I/O
SYNC H

DCH
ENB{I)H

Ell

I,.41~_+-_ _ _ _++----_+_L-. __

2.5
o
2.5
o

I
CA

I DATA I

r---l _

I wc I

BACK TO BACK
TRANSFER RATE 188 KHZ

I lOTIO H

I I.

J/OBUS 17l

DEVJCESElECTOR.

2.5

lWlliIIIJ

SOL_I Mlt1

IOP2H--[3§>

OFL 0
FLAG(I)H

I
J

I
I
I

CLEAR
FLAG L

ISl@

\
2~5 ~---~"I'"

I/O
OFLO H

PROGINTR@j

DCH
''''il,l

OSOH~

2:5;",,-

DCH
GR H

lOP 2 H

1/0.00.

DATA REGISTER LOGIC

RGl

12<

DCH
RO L

____________ _

I
I
I
I
I
I
I
I

0
0

I/OBUST7L

~-<L:-----4----o---i'_--- APr 0 EN OUT H

APIIlfQ(O)H

AND

IIOOFLO(l)L

C!l

G) API 0 EN IN H --++---C~----------------------__;

SKF

-.,

DCH
FLAG
37

2.5

DURING THE ADD TO
MEMORY OPERATION BOTH
WR RO LAND
RD RO L ARE ENABLED

I DATA I
*THIS TIME FOR REFERENCE ONLY

!
ItO RUS 179 H

I
I

- - - - _ _ _ _ _ _ _ _ _ _ _ .J

Figure 4-7 Multi-Cycle Data Channel Timing

@) I/OBU501~

1/0 IUS 11L

Figure 4-6 Multi-Cycle Data Channel Device Logic
4-13

4.2.2 Increment Memory
The basic logic needed to increment memory in any
controller is very similar to the logic needed by a device which wants to transfer data on the multi-cycle
data channel. It uses increment memory control logic
to take care of the control and timing signals and the
usual API, program interrupt, skip and status logic to
handle its "bookkeeping" (Figure 4-8).

The CLK RQ flag sets and in turn enables DCH
REQ (of the increment memory control logic)
to set with the next I/O SYNC H pulse.

DCH REQ causes a DCH RQ L line to signal
the I/O processor which responds with DCH
GR H, setting DCH ENA.

DCH ENA gates the address lines onto the I/O
ADDR bus and also enables the INC MB L
level. It is this control line that signals the I/O
processor to go into an increment addressed
memory sequence rather than a normal transfer
routine.

If the specified location overflows (to zero),
then an I/O OFLO H pulse sets CLK FLG,
which then causes either an API 0 RQ L or a
PROG INT RQ L to inform the program. The
result is similar to previous devices. Complete
timing and signal descriptions are given in
Table 4-3 and Figure 4-10.

Since no data words are involved, the I/O BUS 00-17,
and the data register, contact sensors and transmit
logic are all absent.
Figure 4-9 is a detailed diagram of the logic for this
device. The following describes a typical sequence.

The controller is initiated under program control by setting the CLK EN flag and enabling
the M40l clock (clock logic).

110 BUS
rCONNECTORS

OUT

INCREMENT
MEMORY
CONTROL
LOGIC

DATA CHANNEL
CONTROL LINES

, - i/o PROCESSoR---'

MEMORY

CPU 1/0
CONTROLLER

API
CONTROL
LOGIC

I
I

API
CONTROL
LINES

1
CPU
ACCUMULATOR

$
RQ

OVERFLOW

PROGRAM
INTERRUPT
SKIP
STATUS
LINES

I
MEMORY
110
CONTROLLER

/+ I

t-$

(READ)
.. (WRITE)
OUT

OVERFLOW

DEVICE
SUB DEVICE
SELECT LINES

PROGRAM
INTERRUPT
SKIP AND
STATUS LOG IC

MODE

_ ADDRESSABLE
110 BUS
LOGIC

lOP 1,2,4
CONTROL LINES

J-I

CLOCK
LOG IC

L _______ ..JI

I
I

~.----- PDP-IS - - - - -__al-I. 110 BUS CABLE - < o a . j . , I . > - - - - - - - - - - - - - I N T O U T # 3
I

Figure 4-8 Block Diagram for Increment Memory

4-15

The following program is designed to exercise the increment memory device. Note that the computer has complete
control over this device. No operator switches are used .

START

SKIP

CLK FLG

.LOC 2150
CAF
CLA
ION
TAD (400000
ISA
LAC (775777·
DAC30

/Clear all flags and
/the accumulator
/Turn off PI
/Set up the API control word
land enable API.
/Set up the WC
/register to overflow after 2K g .

lOT SET CLK
JMP.
JMP START

/Turn on clock
/Wait in loop
/Go to beginning

.LOCO
000000
JMP SKIP

/PI setup
/Go to skip chain

.LOC44
JMS OFLO

/ API trap address

.LOC 2200
lOT SKIP L
HLT
JMSCLK FLG
JMP * 0

/Check the CLK FLG
/Wrong flag-error
/Go to CLK FLG routine
/Return to beginning

000000
lOT CLR CLK FLG
DBR
JMP * CLK FLG

/Subroutine entry point
/Clear API and CLK FLG
/Prime API
/Go to beginning

This device could be used as an external interval timer
or an external events counter. If the address were to
change (e.g., the output of an A/D converter) then a

4-16

distribution curve could be plotted in memory. Note
the minimal programming overhead .

This page intentionally left blank.

4-17

Table 4-3 ~Cont)
Increment Memory Signals

Table 4-3
Increment Memory Signals

Signal
Number

Signal
Mnemonic

Connector
Pin Number

DCH
ENH
(IN and OUT)

2BV::!

I/O
SYNCH

2ABI

DCHGRH

2BT2

API 0 EN
(IN and OUT)

2BLI

Signal Definition

Signal Function

Signal
Mnemonic

I Connector

INCMB L

2BDI

Forces the I/O processor to increment the
memory location specified by the IS-bit
address lines on the I/O bus.

This feature allows a device to increment memory
locations in one cycle without disturbing the CPU.

2BS2

A signal from a device to the I/O processor
indicating a request for a multi-cycle data
channel transfer, or an increment memory
request.

Thi~ signal is interpreted by the I/O processor

Signal Definition

Pin Number

Signal Function

The I/O processor clock pulse issued every
microsecond. This is a I mHz, 2SD-ns pulse.

This signal is issued to synchronize device control
timing such as API RQ to the 110 processor.

API 0
RQL

2BHI

One of four API request signals on channels
0-3. This signal is set by the device.

Issued by the I/O processor when it acknowledges a device's DCH RQ L.

The device uses DCH GR to gate the address of
its word count onto the I/O ADDR lines of the
I/O bus.

The device uses this signal to inform the I/O
processor of its request for API service on
priority level 0, the highest of the four.

PROG
ItJ RQL

2ALI

This signal can cause the program to trap to
location 000000 when no higher priority action
is in progress. The instruction resident in location 000001 is fetched and executed.

A device delivers this level to the I/O processor
to request interruption of the program in progress
in order that the device be serviced.

SKIP
RQL

2AJI

The return of the signal to the I/O processor
during 10PI indicates that an lOT instruction
test for a skip condition has been satisfied.
The PC is subsequently incremented by one.

Used by a device to inform the program of the
state of its interrupt flag.

I/O BUS 17L

IAV2

Data line 17.

Used to read the status of the clock flag into the
AC.

RD
STATUS H

2AP)

A signal issued when the CPU issues an 10RS
instruction or when the console switch is placed
on I/O STATUS.

Used by the device to gate its status onto the I/O
bus data lines (one line per status bit) which is
then read into the AC of the CPU.

I/O
OhOH

IBEI

This signal is issued during the first cycle of a
muIti-cycie data channel transfer or an incre~
ment memory cycle, if the content (2's camp lement) of the word count assigned the currently
active data channel device becomes zero when
incremented.

This signal indicates to the device that the specified number of words have been transferred at the
completion of the transfer in progress. It is normally used to turn off the respective device and to
initiate a program interrupt or API request.

This enable signal, is a de level origifiating in
the I/O processor and daisy chained from device to device on the same level. Th~ M 104
logic in each controller can interrupt this level,
cutting off all devices that follow it on the bus.
A device receives it as API 0 EN IN Hand
transmits it as API 0 EN OUT H.

Each device can post a req uest to its API level
only if the incoming API EN level is true. By
posting a request, the device immediately inhibits all controllers below it on the bus. In this
way priorities on each level are established when
devices req uest simultaneously.

2BJI

A signal issued by the I/O processor indicating
that the API request at level 0 is granted.

The device uses this signal to gate the address of
its API level trap address onto the I/O ADDR
lines.

I/O PWR
CLRH

2ASI

System clear signal generated in response to
I) Power on or off; 2) CAF instruction;
3) I/O RESET key. This is a I mHz, 250-ns
pulse.

This signal is treated as an initializing signal for
all devices (controllers) attached to the I/O bus.
All registers are reset to "initial" status.

DSOH-DS5 H
4SDOH,SDl H

2AD2
2AV2

Six device and two subdevice select lines
decoded from bit 6-13 of the lOT instruction.

This signal together with DS I-DSS is decoded by
the device select logic in the controller, which
responds to its unique code only.

lOP I H

2ADI

Micro-programmable control signal part of an
lOT instruction-specified operation within a
device. Decoded from bit 17 of the lOT.

Used for I/O skip instructions to test a device
flag or other control function. Cannot be used
to initiate loading or reading a device buffer
register.

lOP 2 H

2AEI

Same as lOP I H. Decoded from bit 16 of the
lOT.

Usually used to effect a transfer of data from a
selected device to the processor, or to clear a
device register. but may be used for other control functions. May not be used to determine
a skip.

IOP4H

2AHI

Same as lOP I H. Decoded from bit 15 of the
lOT.

Usually used to effect transfer of data from the
CPU to the device, or control. May not be used
to determine a skip condition or to effect a transfer of data from a selected device to the CPU.

17,18
21,22

I/OADDR
12 L, I3 L
14 L, IS L

IBK2 IBS2

Several of fifteen lines which consitute an
input bus for devices which must deliver address
data to the I/O processor.

This address bus has two uses:
a. To deliver the device's API trap address
during its API break;
b. to deliver the device's word count address
during a multi-cycle DCH transfer, an
increment memory operation, or add to
memory.

4-18

Each device can post a DCH request only if the
incoming DCH EN level is true. By posting a
request. the device immediately inhibits all controllers below it on the bus. In this way priorities on each level are established when devices
request simultaneously.

APIOGR H

Signal
Number

This enable signal is a de level originating at
the I/O processor and daisy chained from device to device. The M I 04 logic in each device
can interrupt this level, cutting the level off all
devices that follow on the bus. A device receives it as DCH EN IN H and transmits it as
DCHENOUTH.

7
413

I
20

DCH
RQL

that some device wants to carry out a multi-cycle
transfer or an increment memory.

INCREMENT MEMORY CONTROL LOGIC

INPUT CABLE

1---:OV:---M~:-~~I-;:;;;-;----1

r::::,
I ::::,:
A

DCH EN IN H-----J>+---<)-----------DO!-,EQ-(-O)-H--Ir-"I~_<t.:?:_-4.----<::>--+--------- DCH EN OUT H0

IO!RJS03l

I~ADDRI3l®

(3)
SYNC H

I/O SYNC H

I;\:lADDR 14l

INCMIIl

DCH .Q l

lil

DCH EN!(1) H El

:::::~

lji

..---d:£

DCHREQ(1)L~

!O.lDat~l

10 I\l)DIt 0.7 L

JOAOOlt(letL

3O-2oor'll

PH. CCR H --II---.()-....:..::::..::::::..:.:....--~_s:___.

. .:. ______

o SYNC"

IOPIH

10I'2H

IOP4H

':'R~::"G:: -.:.

1I<:1PRQL

1 ---------------1
I

AlITOMATIC PRIORITY INTERRUPT CONTROL LOGIC
+5V

M104

LJi

API 0 EN IN

MULTIPLEXER

SIGNAL
NUMBER

SIGNAL
NAME

:O:::H~:'
o

I~NH

API ENA(l) H

SYNC H

::::::: ~

OUTPUT CABLE

o."",

APllfQ(1)l

I
I
I

""'"

I/O ADD. 12l

I/OADDRI5l

0
I

2.5

DCH GR H

CLEAR FlG l

2.5

DCH RQU) L

M510

A.PI GRANT H

CLEAR FLAG L JI

DCH ENA

0
I

2.5

I/O OFlO H

I
ClK FLG

2.5
0

SKIP RQ l

ova

API REQ(1) H U2

CD APIOGRH

1/0 8US 16L

3O-2oons

RD
STATUS H

PWI/:CLlr.H

r- I~S-1

I/O SYNC H
ClK RQ(I) H

APIORQl

VOLTAGE
2.5

IOBUS02l
IOM03L

POLARITY

-'N-,-N-H-------APl-RE-Q(-O)-H--Ir-"Ii>---<:I>--4.---_<j---+--- APl 0 EN OUT H
API O

AF'lIRQl

H----J>+---<r--

""N""
M

PROGRAM INTERRUPT, SKIP AND STATUS FACILITIES

-1

MAX FREQUENCY
5(l0 KHZ

15-0090

,0"""",

l§

[Oi\D~~l

IOAODllr:7L

DEVICE SELECT LOGIC

SDOH~
~SOH

CLOCK LOGIC

r - - - - - - - - - - - - - - - - - ---.,

Ml03 DeV]CE5ElECTQR

7110- Kl

Figure 4-10 Timing Diagram for Increment Memory Devices

DS?H

I
I

--a
M510

OPTlON sELECT

lJ2

ENABLE

1--02

---v

'~
DslH

H2
J2

@'O""~
@IO'2H~1
@

10,. H

--GP

lOT SKIP l - + - - 4 - - - - -

SET/RESET elK EN H

L_____________~~I=-___ ~
Figure 4-9 Increment Memory Device Logic
4-19

4.2.3 The Single-Cycle Data Channel Device
The control logic for single-cycle data channel transfers
is very similar to that for multi-cycle breaks, with one
major exception. The number and destination/source
of transfers are parameters handled by the I/O processor and memory during multi-cycle breaks, whereas
during single-cycle transfers the device must remember
its own word count and specify the absolute address it
must transfer to/from (rather than the location of the
current address). Therefore, each single-cycle operating device will have its own word count and current
address register. The time it takes to complete a transfer in this manner is reduced by two cycles. Figure
4-11 shows a block diagram of a typical device operating in single-cycle data channel mode.
A single-cycle device operates under two conditions burst mode or normal mode. Burst mode is used when
the device can transfer a word every microsecond.
Typically, a slow device is double or triple buffered
and transmits the data in a burst of two or three
words. In burst mode, only the first word suffers the
time it takes to synchronize the device with memory
through the I/O processor. Then, each successive word
is transferred every microsecond until the last, after
which synchronization is lost. During a burst, the
transfer cannot change direction, and just before the
last word, the switch must be turned to normal.
In normal mode, each data channel request requires 3
to 5 J.ls to synchronize (unless it is the last transfer of
burst mode). The transfer rate, therefore, is reduced
considerably from burst mode.

DCH GR H sets DCH EN A which places the
contents of the current address register onto
I/O ADDR lines 03 through 17. Later, when
DCH GR H is reset, an address accepted or
data accepted pulse is generated which should
be used to increment the device's current address and word count register.

If the word count register in the device overflows signaling that the last transfer has been
completed, the register must issue an overflow
pulse to set the OFLO flag and cause an API
or program interrupt request in the usual way.

If the I/O processor has sensed a DATA OUT
transfer:
(1)

An lOT instruction is issued to set the DATA

MODE flag to DATA IN (lOP2 with SDO selected) or DATA OUT (lOP2 without SDO
selected). The word count and current address
registers are initiated (not shown). The M401
clock is switched on. The peripheral is set to
burst or normal mode.
b.

The DCH FLAG is set by the clock; it enables
SING CY RQ of the M104, which sets on the
next I/O SYNC H pulse.

It places the content of the memory lo-

cation specified by the current address
onto the I/O BUS 00 - 17 lines; then
(2) It issues an IOP4 which passes through
the WI03 becau3e DCH ENA (1) L has
asserted its option select line. IOP4
strobes the data off the lines into the device data register.
g.

If the I/O processor has sensed a DATA IN
transfer, then DCH ENA (1) H together with
DATA MODE (1) H gate the state of the
switch register onto the data lines. The I/O
processor then strobes them into memory.

If the peripheral is in normal mode, then the
DCH FLAG, DCH RQ are reset when DCH
ENA is set. In burst mode they are inhibited
from resetting.

In burst mode the peripheral must count the
number of DCH GR H's, and on the rising
edge of the last, it must reset to normal mode.
The M104 unripples in the usual way after the
last transfer. In the timing diagram of Figure
4-13b, it is assumed that four transfers occur.

A detailed logic diagram for this peripheral is given
in Figure 4-12. It works in the following way:

DCH RQ L is also posted, if it is to be a transfer into the computer (DATA IN). The I/O
processor begins to synchronize with memory
and issues DCH GR H.

The single-cycle device requires the same programming effort as the multi-cycle devices. Most of the work comes in
setting up the word count and current address registers (not shown) or setting modes. It is faster and uses less I/O processor time, however.

4-21

.LOC 2250
CAF
CLA
ION
TAD (400000

START

/
/
/

ISA
LAC (WC)
lOT SETWC
LAC (CA)
IOTSETCA
lOT SET MODE
JMP .

Same as previous devices

/Set up the
/WC, CA
/registers and the
/mode;
/then wait in
/a loop

.LOCO
000000
JMP SKIP

/
/

.LOC44
JMS OFLO
.LOC 2300
lOT SKIP L
HLT
JMS OFLO
JMP * 0
000000
IOTCLROFLO
DBR
JMP * OFLO

SKIP

OFLO

1/0 BUS
rCONNECTORS

Same as previous devices

/
/
/

OUT

~~~E~~C~~6~~TED ~ TO DEVICE CONTROLLER

OUT
NORMAL MODE

SI NGLE CYCLE
DATA CHANNELI4>I4--eoto~--+1
CONTROL LINES

r - i70 PROCESSOR -,

CPU

ACCUMULMOR

II
:

PROGRAM
INTERRUPT
SKIP AND
STATUS LOGIC

WORD COUNT OVERFLOW FROM
DEVICES WC REGISTER

~-fi

BURST MODE

AUTOMATIC
PRIORITY
INTERRUPT
CONTROL I + - - x - - - - . . . - - - - - - - - - - -.......
LOGIC

API
CONTROL
LINES

PROGRAM
. INTERRUPT
SKIP So STATUS
LINES

CPU 1/0
CONTROLLER

SINGLE
CYCLE
DATA
CHANNEL
CONTROL
LOGIC

DEVICE So
SUBDEVICE
SELECT LINES
MEMORY

CONT~gr ~{JE~ I~-'~--"'"

110
CONTROLLER

ADDRESSABLE

ICgG~~S

I
I

I
L ______ ..J

I
I

1-------- PDP-15 ------------t.+1.~1I0 BUS CABLE -+
I

I
I
- - - - - - - - - - - DEVICE-----------------------------~

Figure 4-11 Block Diagram of Single-Cyc1e Data Channel Device
4-22

This page intentionally left blank.

4-23

Table 44
Single.cyde Data Channel Interface

Signal
Number
I

Signal
Mnemonic
DCH
EN H

I,'
IPinConnector
Number
2BV2

Table 44 (Cont)
Single-Cycle Data Channel Interface

Signal Function

Signal Definition
I

This enable signal is a de level originating at the
I/O processor and daisy chained from device to
device. The MI 04 logic in each device can
interrupt this level, cutting the level off all de·
vices that follow on the bus, A device receives
it as DCH EN IN H and transmits it as DCH
EN OUT H.

I
I

Each device can post a DCH request only if the
incoming DC'H EN level is true, By posting a request, the device immediately inhibits all controllers below it on the bus. In this way priorities on each level are established when devices
request simultaneously.

I/OSYNCH

2ABI

The I/O processor clock pulse issued every
microsecond: a I mHz, 250-ns pulse.

This signal is used to synchronize device control
timing such as API RQ to the I/O processor,

DCHGRH

2BT2

Issued by the I/O processor when it acknowledges a device's DCH RQ L.

The device uses DCH GR to set ENA which gates
the memory address onto the I/O ADDR lines of
the I/O bus.

API 0 EN

2BLI

This enable signal, is a de level originating in
the I/O 'processor and daisy chained from device
to device on the same level. The M I 04 lOgic in
each controller can interrupt this level, cutting
the level off all devices that follow it on the bus.
A device receives it as API 0 EN IN Hand 'transmits it as API 0 EN OUT,H.

Each device can post a request to its API level
only if the incoming API EN level is true. By
posting a request, the device immediately inhibits
all controllers below it on the bus. In this way
priorities on each level are established when devices request simultaneously.

DCH
RQL

One of four possible signals issued by the 1(0
processor indicating that it grants the API
request at the corresponding level, O.

Signal Function

Signal Definition

2BS2

A signal from a device to the I/O processor,
when posted with a single cycle request, shows
that an input transfer must be effected.

This signal is interpreted by the I/O processor in
this way: if a single-cycle request (SING CY RQ L)
is posted, then it and DCH RQ L are ANDed to
inform the I/O processor that a transfer into memo
ory is to be effected in single-cycle mode; otherwise,
the I/O processor assumes an outgoing single-cycle
transfer is required.

API 0
RQL

2BHI

One of four API request signals on channels
0-3. This signal is set by the device at I/O
SYNC time.

The device uses this signal to inform the I/O
processor of its request for service on API priority
level 0, the highest of the four.

PROG
INTRQL

2ALI

This signal can cause the program to trap to 10'
cation 000000 when no higher priority action is
in progress. The instruction resident in location
000001 is fetched and executed.

A device delivers this level to the I/O processor
to request interruption of the program in progress
in order that the device be serviced.

SKIP
RQL

2A1I

The return of the signal to the I/O processor
during lOP I indicates that an lOT instruction
test for a skip condition has been satisfied.
The PC is subsequently incremented by one.

Used by a device to inform the program of the
state of its interrupt flag.

This device uses this signal to gate the address of
its API level trap address onto the I/O ADDR
lines.

RD
STATUSH

2API

A signal issued when the CPU issues an 10RS
instruction or when the console switch is
placed on I/O STATUS.

Used by the device to gate its status onto the
I/O bus data lines (one line per status bit) which
is then read into the AC of the CPU.

System clear signal generated in response to:
I) Power on or off; 2) CAF instruction; 3)
I/O RESET key; a I mHz, 250-ns pulse.

This signal is treated as an initializing signal for
all devices (controllers) attached to the I/O bus.
All registers are reset to "initial" status.

SD I H

2AV2

Same as SDO H - Decoded from bit 13 of the
lOT.

Same as SDO H.

2B1I

I/OPWR
CLRH

2ASI

7
13

DSO H·DS5 H
SDO H-SDI H

2AD2
2AV2

Six device and two subdevice select lines decoded from lOT instruction bits 6-13,

These signals are decoded by the device select
logic in the controller, which responds to its
unique code only.

lOP I H

2ADI

Micro·programmable control signal; part of
an lOT instruction-specified operation within a
device. Decoded from bit 17 of the lOT.

Used for I/O skip instructions to test a device flag
or other control function. Cannot be used to
read a device buffer register.

lOP 2 H

2AEI

Same as lOP I H. Decoded from bit 16 of the
lOT.

Usually used to effect a transfer of data from a
selected device to the processor or memory, or
to clear a device register, but may be used for
other control functions. May not be used to
determine a skip.

IOP4 H

2AHI

Same as lOP I H, and it is also issued during
an out·going single-cycle transfer. Decoded
from bit 15 of the lOT.

Usually used to effect transfer of data from the
CPU of memory to the device. or for control.
May not be used to determine a skip condition
or to effect a transfer of data from a selected
device to the CPU.

I/O BUS
OOL-17L

IABI IAV2

Eighteen data lines which constitute the bi·
directional facility for transferring data in
bytes of up to 18 bits between the device and
either the CPU or memory.

These data lines (I/O BUS 00 L - I/O BUS 17 L)
convey data between the AC of the CPU and a
selected device information buffer register or,
the bus bulTer of the I/O processor and a selected
device buffer register during data channel operations.

3549

I/OADDR
03 L - 17 L

IBHI IBV2

Fifteen lines which constitute an input bus for
devices which must deliver address data to the
I/O processor.

This address bus has two uses:
a. To deliver the device's API trap address during
its API break,
b. To deliver the device's word count address
during a multi-cycle DCH transfer, an increment
memory operation, add to memory, or singlecycle break,

SINGCY
RQL

2AS2

Indicates when a device wants to carry out a
single-cyde data transfer to memory,

The device uses this line to request from the I/O
processor a single-cycle transfer. If a DCH RQ L
signal is sent with it, the I/O processor responds
to an input (to computer) transfer; otherwise. it
determines an output transfer.

4-24

Connector

I Pin Number

API 0
GRH

Signal
Mnemonic

Signal
Number

SINGLE CYCLE DCH TRANSFER CONTROL LOGIC

r--:;v--------------I
I

M104

MULTIPLEXER

I
I

IlPUT CABLE

<D DCH EN!N H --~+--<J>----------DC-H-"-Q-'O-)H-r-"I»--<C>-~---o

TI
o~'~'

JC)klSOll

OCH ENA(1) H

ij
:::::

DOl ENB(I) L

110 SYNC H

DATA ACCEPTED}
(CHANGE O"'TA)

oFl

DCHRfQOlL

10_tIIIl

TO DEVICE
CONTROUER

DCH '.0(1) H

<a,

2.5 ......- - - -..... J
0
2.5

SING CY RQ L

DCH GR H

NORMAL MODE
BURST MODE
CLEAR
FLAG L

1
0
0

2.5 I---~~___--".."....",.+--I_+_-_+~~--I-_+------_l

~
M622

SING C'I lEO L

M622

DCHIIQL

rO~lIIIl

IO_lJ7t

BURST MODE.

2.5

o
2.5

DA.TA .YDOE{l) l
(DATA 11'1)

IO~Qll

o
o

DCH ENA
NO"",,MODe(I)H

ADDRESS

DOt ENA(I) H

CLEAR FLAG l Jl

::::::

o
2.5

O~--~----------~

IC:YtOH-

2.5

o
DCH ENa(l) H EI

I~~::

POLAe.RITY SINGLE CYCLE BURST MODE TIMING FOR .AN OUTPUT TRANSFER FROM
VOLTAGE THE COMPUTER (THREE TRANSFERS PER BURST)

10 IUS 001 ~

SIGNAL
NAME

DCH FLAG

IOMoh

DCH ENA(l)l

1/0""00'"

SIGNAL
NUMBER

on,o

10"1"

o
2.5 I-----------~ r---~

ACCEPTED

1
1

2.5

lOP 4 H

,..--__

r------~

*STROBE DATA HERE

101'."

A"",,~,:.::

a
i",,:',::

AUTOMATIC"

PROGRAM INTERUPT SKIP
AND STATUS FACILITES

PRIORITY
INTERRUPT
CONTROL LOGIC

10:C::

®
I/OADDR 12l
®

I/O ADDR ISl

®
ItO ADOR 16 L
SIGNAL
NUMBER

SIGNAL
NAME

lIO SYNC H

POLARITY SINGLE CYCLE BURST· MODE TIMING FOR AN INPUT TRANSFER TO
81
THE COMPUTER (THREE TRANSFERS PER BURST)
VOLTAGE

10",$Oll

DCH FLAG

101US03L

a
li

ItO PWRClRH

IOMl17l

'~::

100l'lOH

2.5

ADD.mf'~~

110 ~

Q) soot'.

.~=-+

__________

1
0

SING CY RQ L

0
0

2.5
0
2.5

DCH RQ L

1
1

DCH GR H
NORMALMODE

2.5

BURST MODE
CLEAR

FLAG L

0
0
1

DCH ENA

ADDRESS
ACCEPTED

0
1

2.5

DATA

2.5
0

D.LU,OFtOH

JOoloDOlIXJl

0
0

101US02l

:::::

2.5
0
2.5

APlOGRH

o.,,~,

CONTACT SENSOR AND TRANSMIT LOGIC

::::::
IO_llfit

1/0 BUS '7L

10_Wl

IOAtIOI:CIIl

VOWSOIL

@DSOH~I

~..
o""""

"""
"'

~
i'" "::,:::

DSSH

A ..,.:~.::

~."

10:C::
-1·U.INtH
~O.Ql

!---MAX RATE

API OENOUTH

'...e .... L

'J-C"'INHl

OUTPUT CABLE

lMHZ

~'":
I

-CZ+-~

IOPIH~

IOP'H~ I

@ IO"H~

RUSOOL

ACCEPTED
DATA REGISTERS

nlPs;n

-I

4ps*

.tl

rn 1H rrn..-l\

•,

}

~u
/ r

BURST MODE

®)\
/

iMHZ

\"lJ
~

IL ___________ -.J

@ I/OIUSOOL

~_-+

17l

Figure 4-12 Logic Diagram of Single-Cycle
Data Channel

I--MAX RATE

___..... D~~~~~ER

VOBUS 178H

Figure 4-13a Timing Diagram for Single-Cycle Device in
Nonna! Mode

@ 1!OIIUSOIl

NORMAL MODE

\~
-,r

* NOTE THESE TIMES FOR REFERENCE ONLY

.~.

--I

@) l/OIUS

1/0

2.5
0
2.5

15-0092

SIGNAL
NUMBER
1/O""DIt"L

4>.,---OC....H-'N-our-H"""' ?'
DCH ENA\1I L

DCH ENA(I) H

SIGNAL
NAME

110 SYNC H
DCH FLAG

DATA ACCEPTEC}
(CH,&NGE DATA)

o
DCHEN8(l)l Fl
o

TO DEVICE
CONTItOUER

DCH GR H

3
DCH REQ(1) l

SINGCY REaL

o
o

0
2.5
0

2.5 ~----....,J

0
0

CLEAR

2.5

{DATA-INI

DCH ENA
ADDRESS

2.5

DCH FLAG

2.5

SINGCY
RQ L

DCH GR H

CLEAR
FLAG L

2.5

DCH ENA

ADDRESS
ACCEPTEDL

2.5

IOP4H

2.5 ~---------.......;~ I--~]r---"

lOP 4 H

2.5

IIIO SYNC H

SINGLE CYCLE ASYNCHRONOUS TIMING FOR AN OUTP.UT TRANSFER FROM COMPUTER (NORMAL MODE)

VOLTAGE

ACCEPTED

2.5

1
0
0

DATA MODE(1) L

SIGNAL
NAME

2.5 ~------~Ir-+-~:u-+-""";.r+"""-----~

FLAG L

SIGNAL
NUMBER

f>$ 4 J,lS

NORMALMODE
BURST MODE

, 2.5o
o
, 2.5~------~--~~--~~~~rtrl---~-t.~~~~--~

SING CY RQ L

Deli ENB(!) H El

POLARITY

POLARITY SINGLE CYCLE BURST MODE TIMING FOR .AN OUTPUT TRANSFER FROM
VOL ~AGE THE COMPUTER (THREE TRANSFERS PER BURST)

2.5

-----------1
16

* STROB E DATA HERE

II "11111 I
I

f>$ 3ps ..

r:r

f>$ 3j.ls

)

(

\
.

)

-I

-s:

~W~~EERE --I

STROBE DATA HERE

MODE

L
I

NORMAL

I-- MAX RATE 333 K H Z - - - f

-.f

PROGRAM INTERUPT SKIP
AND STATUS FACILmES

1MHZ

!--MAX RATE

SINGLE CYCLE ASYNCHRONOUS TIMING FOR INPUT TRANSFER TO COMPUTER (NORMAL MODE)

o
AP'IOENOUT@
I/O.a..DDI;12l

APIORQL

®
2

@
TjOADDR1SL

PROGINTRQL

110 SYNC H

DCH FLAG

I/O ADOR 16 L

~---r-----T:P:-:O:-:-L--:A--:R:-:-IT=y::l SINGLE CYCLE BURST- MODE TIMING FOR AN INPUT TRANSFER TO

SIGNAL
NUMBER

?,------t
I

SIGNAL
NAME

VOLTAGE

SING CY RQ L

lit
~

I }II

DCH RQ L

1
NORMAL MODE
BURST MODE

CLEAR

FLAG L

I/OBUSOll

)ATA IEGISTERS

I/O BUSOOl

;

DCH GR H

INTACT SENSOR AND TRANSMIT LOGIC

Jr.lL-______~

1111111111.
2.5~______~~~\

0
0

,
,

~~______j____~~ @!/Al~~\
2.5
0
2.5

2.5
0
2.5

DCH ENA

ADDRESS

2.5

ACCEPTED

0
1

DATA

0
2.5

ACCEPTED

BURST MODE

SING CY
RO L

...

~5 ~

! ~5

lIO SYNC H
DCH FLAG

THE COMPUTER (THREE TRANSFERS PER BURST)
~
I~ 4J,1s*

/ r

DCH RQ L

DCH GR H
CLEAR
FLAG L

______

DCH ENA
ADDRESS
ACCEPTED
DATA
ACCEPTED

NORMAL MODE
MODE

U I

2.5

0
0

2.5

0
0
1
1
0
0

2.5

0
2.5

I--- f>$ 2jJs *

~
mrnrrmv

"IKI!
It

'-I

f>$2J,1S~

-I ..

V
I
I

JI'I

\"*'l

f1'\

\~
-y

v~\

J-'

)

.\
\-0

NORMAL

~ MAX RATE 500 KHZ

I-

15 0093

* NOTE THESE TIMES FOR REFERENCE ONLY
~

iMHZ

j.-MAX RATE

* NOTE THESE TIMES FOR REFERENCE ONLY

Figure 4-13b Single-Cycle Asychronous Timing
15-0092

Figure 4-13a Timing Diagram for Single-Cycle Device in
Nonnal Mode

, Single-Cycle
4-25

4.3 SYSTEM PRIORITY STRUCTURES
There are three classes of priorities within the PDP-IS
system:
a.

Class 1 is established if the I/O processor and
the central processor simultaneously request
a memory cycle. Under this condition, the
I/O processor is served first; this is necessary
to prevent the CPU from shutting out the I/O.

Class 2 occurs within the I/O processor itself.
The five subsystems which use the I/O processor, the data channel, real time clock, API,
PI and lOT instructions, are ordered from data
channel to lOT.
Classes 1 and 2 are discussed in more detail in
the PDP-IS System Reference Manual and the
User's Handbook.

Class 3 is the priority structure associated with
devices on the I/O bus which use the data
channel or the API.

There are four API levels, with three associated control
signals (API RQ, API EN and API GR); they are
ordered from the highest level 0 to the lowest level 3.
Any device of a higher level not only takes priority
over another of a lower level, but actively interrupts
that level during its service routine (see User's Handbook), thus making nested interrupts possible.

THIS CAN BE ANY ONE OF 5 LINES

Each API level can have up to eight devices using it,
although the system software allots only 28 memory
locations for this function. If any two devices on
the same level request interrupts simultaneously, the
device closest to the computer on the I/O bus is
serviced first. Figure 4-14 illustrates this process. If
device #1 and the device #2 post REQ flags together,
the API 0 EN level (for example) to device #2 is disabled by the REQ flag of device # I through the AND
gate of its MI04 Multiplexer. The disabled API 0 EN
flag grounds the direct clear of the REQ flip-flop in
device #2, and inhibits it until the API of device #1
is serviced.

If any device in the chain does not use API or data
channel, the respective ENABLE lines must be jumped
from the input to the output cable.

The data channel devices operate the same way on
only one ENABLE line. Up to eight devices can use
the data channel, four of which can be multi-cycle
devices and eight can be single-cycle devices. The restriction on cycle devices is a software constraint explained in Chapter 6. Because of the priority scheme
on the data channel, latency sensitive devices should
be placed closest to the I/O processor.

!~l?
~~
AP I 2 EN

AP I 3 EN
DCH EN

MI04
EN OUT

EN IN

EN OUT

ENIN

ENOUT

>-+--I>---+----t--o-----c>---r-- TO NEXT
DEVICE

PDP-15

DEVICE#2

DEVICEII'I

DEVICE#3

Figure 4-14

4-27

4.4 SUMMARY OF I/O BUS FUNCTIONS
Table 4-5 de.scribes I/O Bus signals and their functions.
Table 4-5
Summary of I/O Bus Signal Functions

---------------,---------------------------Signal
Mnemonic

4-28

Connector
Pin Number

Signal Definition

API 0
EN H

2BLI

This enable sign al. aile of four in the API system,
is a dc level ori ginating in the I/O processor and
daisy chained f rom dl~vice to device on the same
level. The M 10 4 logio: in each controller can
interrupt this Ie vel, cutting the level off all devices that folio w it on the bus. A device receives
it as API 0 EN IN H and transmits it as API 0 EN
OUTH.

Each device can post a request to its API
level only if the incoming API EN level is true.
By posting a request the device immediately
inhibits all controllers below it on the bus.
In th,i~ way priorities on each level are established when devices req uest sim ultaneously.

API I
ENH

2BSI

Same as API 0 ENH

Same as API 0 EN H

API 2
ENH

2BH2

Same as API 0 EN H

API 3
ENH

2BP2

Same as API 0 ENH

Same as API 0 EN H

API 0
GR H

2BJI

One of four po ssible signals issued by the I/O
processor indic ating that it grants the API request at the co rresponding level.

The device uses this signal to gate the address of
its APllcvcl trap address onto the [/0 ADDR
lines.

API I
GRH

2BPI

Same as API 0 GRH

Same as API 0 GR H

API 2
GRH

2BE2

Same as API 0 GRH

Same as API 0 GR H

API 3
GRH

2BM2

Same as API 0 GRH

Same as API 0 GR H

API 0
RQL

2BHI

One of four AP I request signals on channels
SYNC time.

The device uses this signal to inform the I/O
processor of its request for API priority level 0,
the highest of the fouf.

o ~ 3. This signal is ,et by the device at I/O

Signal Function

API I
RQL

2BMI

Same as API 0 RQL

Request API priority level I.

API 2
RQL

2BD2

Same as API 0 RQL

Request API priority level 2.

API 3
RQL

2BK2

Same as API 0 RQL

Request API priority level 3.

DATA
OFLOH

IBDI

This signal is ga ted onto the bus by the I/O
processor durin g the third cycle of an addto-memory ope ration when the sum (I 's
complement) 0 f two like-signed numbers
has an opposite sign.

This signal is used by the device to notify it
when an incorrect sum occurs, because of
overflow during an add-to-memory operation.

DCH
ENH

2BV2

This enable si gnal is a dc level originating
at the I/O proc essor and daisy chained from
device to device. Thl~ M I 04 logic in each device can interru pt this level, cutting the level
off all devices t hat follow on the bus. A device receives it as DCH EN IN H and transmits
it as DCH EN OUTH.

Each device can post a DCH request only if
the incoming DCH EN level is true. By posting a request, the device immediat(:ly inhibits
all controllers below it on the bus. In this way
priorities are established when devices request
sim ultaneously.

DCH
GRH

2BT2

Issued by the 1/ o processor when it acknowledges a device's DCH RQ L.

The device uses DCH GR to gate the address of
its word count onto the I/O ADDR for 3-cycle
transfers and gates memory address during l-cycle
transfers.

DCH
RQL

2BS2

A signal from a device to the I/O processor
indicating eithe r a request for a multi-cycle
data channel transfer or, when posted with a
single-cycle req uest; showing that an input
transfer must b e effected. The table below
shows how the two functions relate.

This signal is interpreted by the I/O processor in
in two ways:
If it is present without a single-cycle request,
it implies that some device wants to carry out
a multi-cycle transfer, an increment memory,
or add to memory.

Table 4-5 (Cont)
Summary of I/O Bus Signal Functions
Signal
Mnemonic

Connector
Pin Number

Signal Definition

DCH
RQL

SING
CY RQL

0
0

0
I

Multi-Cycle
Transfer (In
or Out)

Single-Cycle
Transfer In

FUNCTION

Single-Cycle
Transfer Out

Signal Function

If a single-cycle request is also posted, then
the two signals are ANDed to inform the I/O
processor that a single-cycle transfer into
memory is to be effected. Otherwise, the I/O
processor assumes an outgoing single-cycle
transfer is required.

DSO H

2AD2

The first of six device select lines decoded from
bit 6 of the lOT instruction.

This signal together with DS I DS5 is decoded
by the device select logic in the controller, which
responds to its unique code only.

DSIH

2AE2

The second of the six device select lines.

Sec DSO H

DS2 H

2AH2

The third of the six device select lines.

Sec DSO H

DS3 H

2AK2

The fourth of the six device select lines.

See DSO H

DS4H

2AM2

The fifth of six device select lines.

See DSO H

DSS H

2AP2

The sixth of six device select lines.

See DSO H

INC
MB L

2BDI

Forces the I/O processor to increment the
contents of the memory location specified
by the IS-bit address lines on the I/O bus.

TIlis featurc allows a device to increment memory
locations in one cycle without disturbing the CPU.

I/OADDR
03 L

IBHI

One of fifteen lines which constitute an input
bus for devices which must deliver address
data to the processors.

This address bus has two uses:
a. To deliver the device's API trap address
during its API break.
b.

To deliver the device's word count address
during a multi-cycle DCH transfer, an increment memory operation, or to add to memory. To deliver an absolute address during
single-cycle transfers.

I/OADDR
04 L

IBJI

Similar to I/O ADDR 03 L

I/OADDR
05 L

IBJI

Similar to I/O ADDR 03 L

I/OADDR
06 L

IBMI

Similar to I/O ADDR 03 L

I/O ADDR
07 L

IBPI

Similar to I/O ADDR 03 L

I/O ADDR
08 L

IBSI

Similar to I/O ADDR 03 L

I/OADDR
09 L

IBD2

Similar to I/O AD DR 03 L

Similar to I/O ADDR 03 L

I/OADDR
IOL

IBE2

Similar to I/O ADDR 03 L

I/OADDR
II L

IBH2

Similar to I/O ADDR 03 L

I/OADDR
12 L

IBK2

Similar to I/O ADDR 03 L

I/OADDR
13 L

IBM2

Similar to I/O ADDR 03 L

4-29

Table 4-5 (Cont)
Summary of [/0 Bus Signal Functions

.---Signal
Mnemonic

Connector
Pin Number

I/O ADDR
14 L

IBP2

Similar to I /0 ADDR 03 L

Similar to I/O ADDR 03 L

I/O ADDR
IS L

IBS2

Similar to I /0 ADDR 03 L

Similar to I/O ADDR 03 L

I/OADDR
16 L

IBT2

Similar to I /0 ADDR 03 L

Similar to I/O ADDR 03 L

I/OADDR
17 L

IBY2

Similar to I/0 ADDR 03 L

Similar to I/O ADDR 03 L

I/O BUS
00 L

IABI

The first of 18 data lines which constitute
the bidirect ional facility for transferring
data in byt es of up to 18 bits between the
device and either the CPU or memory. This
is the MSB.

These data lines (!f0 BUS 00 L through I/O
BUS 17 L) convey data between

Signal Definition

Signal Function

The AC' of the CPU and a selected device
information buffer register or

the bus buffer of the [/0 processor and
a selected device buffer register during
data dwnnel operations.

110 BUS
01 L

IADI

Data line t wo

See [/0 BUS DOL

I/O BUS
02 L

IAEI

Data line Ittree

See [/0 BUS 00 L

I/O BUS
03 L

IAHI

Data line f our

See I/O BUS 00 L

I/O BUS
04 L

IAJI

Data line fi vc

See [/0 BUS 00 L

I/O BUS
OS L

IALI

Data line si

See I/O BUS 00 L

I/O BUS
06 L

IAMI

D-dta line scvcn

See I/O BUS 00 L

I/O BUS
07 L

IAPI

Data line ei ght

See [/0 BUS 00 I

I/O BUS
08 L

IASI

D-dta line n me

Sec [/0 BUS 00 L

I/O BUS
09 L

IAD2

Data line t~'n

See [/0 BUS 00 L

I/O BUS
10 L

IAE2

Data line el even

See I/O BUS 00 L

I/O BUS
II L

IAH2

Data line t welve

Sec [/0 BUS 00 L

[/0 BUS
12 L

IAK2

Data line t hirteen

See I/O BUS 00 L

[/0 BUS
13 L

lAM:!

Data line f ourtcen

Sec I/O BUS 00 L

I/O BUS
14 L

lAP:!

Data line fi fleen

See I/O BUS 00 L

I/O BUS
IS L

IAS2

Data line si xll:en

See I/O BUS DOL

I/O BUS
16L

IAT2

Data line S~'venlcl·n

See I/O BUS 00 L

[/0 BUS
17 L

IAB2

Data line ei ghteen
This is the LSB

Sec [/0 BUS 00 L
.------~---------------------------------

4-30

Table 4-5 (Cont)
Summary of I/O Bus Signal Functions
Signal
Mnemonic

Connector
Pin Number

I/OOFLO
H

IBEI

This signal is issued during the first cycle of a
multi-cycle data channel transfer or an increment memory cycle, if the content (2's complement of the word count assigned the
currently active data channel device becomes
zero when incremented.

This signal indicates to the device that the
specified number of words have been transferred
at the completion of the transfer in progress. It
is normally used to turn off the respective device
and to initiate a program interrupt or API request.

lOP I H

2ADI

Microprogrammable control signal part of an
lOT instruction-specified operation within a
device. Decoded from bit 17 of the lOT.

Used for I/O skip instructions to test a device flag
or other control function. Cannot be used to read
a device buffer register.

Signal Definition

Signal Function

In general, a designer should be wary of using lOP
pulses for multiple purposes. Never clear and skip
on a flag, with the same lOT. for cxample!
lOP 2 H

2AEI

Same as lOP I H and it is also issued during
a multi-cycle data channel transfer into memory. Decoded from bit 16 of the lOT.

Usually used to effect a transfer of data from a selectcd device to the processor or memory, to dear
a device register. but may be used for other control
functions. May not be used to determine a skip.

IOP4H

2AHI

Same as lOP I H and it is also issued during
a multi- or single-cycle data channel transfer
out of memory. Decoded from bit 15 of the
lOT.

Usually used to effect transfer of data from the CPU
or memory to the device or control. May not be
used to determine a skip condition or to efTect a
transfer of data from a selected device to the CPU.

System clear signal generated in response to:

This signal is treated as an initializing signal for all
devices (controllers) attached to the I/O bus. All
registers are reset to "initial" status.

I/OPWR
CLRH

2ASI

I/O RUN
H

2BBI

This level becomes high when the CPU is
running.

Can be used to disable a device if the CPU stops.

I/O SYNC
H

2ABI

The I/O processor clock pulse issued every
microsecond; I mHz, 250-ns pulse width.

This signal is used to synchronize device control
timing such as API RQ and DC H RQ to the I/O
processor.

PROG
INT RQ L

2ALl

l1lis signal can cause the program to trap
to location 000000. The instruction resident
in location 000001 is fetched and executed.

A device delivers this level to the I/O processor to
request interruption of the program in progress in
order that the device be serviced.

RD
RQL

2AMI

Indicates to the processor that the device is
sending it a data word.

Used by the device to specify to the I/O processor
an input-to-CPU data transfer is required.

RD
STATUS H

2API

A signal issued when the CPU issues an 10RS
instruction or when the console switch is
placed on I/O STATUS.

Used by the device to gate its status onto the I/O
bus data lines (one line per status bit) which is
then read into the AC of the CPU.

SDOH

2AT2

The first of two subdevice select lines decoded
from bit 12 of the lOT instruction.

This signal and DS I H can be decoded by the
device for mode selection.

SDI H

2AY2

Same as SDO H except if it is decoded from
bit 13 of the lOT instruction.

Same 'as SDO H

SINGCY
RQL

2AS2

Indicates when a device wants to carry out a
single-cycle data transfer to memory.

The device uses this line to request from the I/O
processor a single-cycle transfer. If a DCH RQ
signal is sent with it. then the I/O processor responds
to an input (to computer) transfer. Otherwise it
determines an output transfer.

SKIP
RQL

2AJI

The return of the signal to thl' 1/0 processor
during 10pI indicates that an lOT instruction
test for a skip condition has been satisfied.
The PC is subsequently incremented by one.

Used by a device to inform the program of the
state of its interrupt flag.

WR
RQ L

2BBI

Indicates to the I/O processor that the device
requires a transfer from memory during a
multi-cycle data channel.

The devicc uses this signal to inform the I/O processor that it wants a word from memory (during
a multi-cycle data channl'l transfer).

+ I -+
CA INH L

2BEI

If the 1/0 processor sees this signal during
multi-cycle transfers. it inhibits normal incrementing of the device's assigned current
address memory location.

This facility is uscd by sudl peripherals as
OFCtape and magnl'tic tapt' when they
search for records. It is also useful during
devin' checkout.

I. Power on or off
2. CAF instruction
J. I/O RESET key

I mHz, 250-ns pulse width

4-31

CHAPTER 5
WIRING PRACTICES

Noise within a digital system can be minimized by
following simple wiring rules and using good working
practices. The following paragraphs detail some of the
common sources of noise and outline some rules
which, if followed, will eliminate most problems.

5.1 WIRING RULES
DEC uses both fast and slow TTL logic in its modules.
The slow 74-series modules have typical rise and fall
times of under 8 ns. The high speed 74H-series gates
show typical rise and fall times of under 5 ns. At the
frequencies contained in these edges, the effects of inductance, mutual inductance, and capacitance as well
as transmission line properties of the wiring become
effective. Noise is generated on single lines by ringing during a rising or falling edge, and between lines
through the coupling of mutual inductance and capacitance. Unwanted pulses generated by ringing and
crosstalk can endanger input gates if they exceed the
allowable input of 5.5V (Zener breakdown), or falsely trigger gates and flip-flops if they reach the threshold or band X region between 0.8V and 2.0V.

5.1.1 Single Line Waveform Degradations

The ringing problem in a single line can be reduced if
the line is shortened or the loading is increased since a
line with only a single load is more susceptible to ringing problems than one which is fully loaded. Further,
a short line which has less inductance and capacitance
is less vulnerable to ringing than a longer line. If it is
impossible to shorten a line which has a noise problem,
then it should be considered a transmission line and
properly terminated. Table 5-1 shows recommended
wire lengths for fast and slow gates under single and
full load.

5.1.2 Termination Technique

When lines longer than the lengths recommended in
Table 5-1 must be used, they should be terminated to
ensure clean transitions and fast settling times. Figure
5-1 shows one way that this can be done. To handle
the current drain of the termination and gate loading,
a module which uses a 74H40 gate or equivalent which
will drive 60 rnA in the 0 state, is suggested. This module has IOns rise and fall times, and a very low highstate output impedance.

The line can be terminated with a 120n resistor to
+5V and a 180n to ground (Figure 5-1). The 120n
resistor to +5V draws at a maximum of 44 rnA, and
the 180n resistor to ground does not allow the 120n
resistor to pull the high-state line potential any more
than +3V. The gate does not have to supply any current to the resistors during its high-state. Even when
terminated, 36 in. is the recommended maximum
length of a wire with either fast or slow gates.

Gate loading in this scheme is limited to 10 units for
reasons shown below.

Table 5-1
Recommended Maximum Wiring Lengths
With Single Wires
Maximum Line Lengths
TTL Series Gates 1 Unit Load Max Unit Load
74 Series (Slow)

21 in.

26 in.

74 Series (Fast)

11 in.

18 in.

5-1

10 unit load = 1.6 rnA max drain x 10 = 16 rnA
Standard 1200 ±5% resistor

5Vj114 = 44 rnA

74H40 = 60 rnA drive at OV

Total

= 60 rnA

+5V
120
:!:5 %
10
D-----~-----_a UN IT

LOAD
180
!5%

15-0082

Figure 5-1 Terminating Long Wires

It is good engineering practice to examine every signal

talk noise in digital systems. This phenomenon varies
with the high and low speed gates, the frequencies at
which the gates are operating, the length of the wires
involved, and even the relative positions of drivers and
receivers. Crosstalk occurs as a result of coupling between parallel lines through their mutual inductance
and capacitance. The coupling and noise injected from
active to quiescent circuits increases as lines run parallel to each other over greater distances. Those gates
which are faster respond to a greater bandwidth of
noise and so are more vulnerable. Higher signal frequencies couple more readily than lower frequencies;
and the relative position of the driver to the receiver
on either line affects the magnitude of crosstalk. If
both receivers and drivers of the two circuits are at the
same end of the lines, as shown in Figure 5-2a, then
capacitive and inductive crosstalk components cancel,
and one becomes dominant. Alternatively, if the
drivers and receivers oppose each other as in Figure
5-2b, then the components add, and the situation is
more precarious.

in a system for possible waveform degredations.

5.1.3

Another variable to consider is the state of the quiescent or receiving circuit. Since the output impedance
of the driving circuits is different for each state, it
would be expected that crosstalk would also vary.
Table 5-2 summarizes the recommended limits of parallel line lengths for digital circuits under the conditions outlined above. The effect of loading is also
considered.

Crosstalk in Parallel Logic Lines

The present trend toward fast transition times and
densely packed wiring adds to the probability of cross-

=0-:
=0DRIVER

C _.1_

-T-

RECEIVER

I
I

RECEIVER

DRIVER

Figure 5-2a

=0-,
DRIVER

-0-:

RECE I VER

DRIVER

RECEIVER

15-0082

Figure 5-2b
Figure 5-2 Capacitance and Inductive Crosstalk Components

5-2

Table 5-2
Parallel Line Length Limits
Limitations (Inches)
Loading
in Units

Slow Gates

Fast Gates

Noise Sensitivity

Environment

Zener Breakdown Danger (1,2)

Freq < 100 kHz

min
max

36
>36

18
>36

Freq 1 mHz

min
max

33
>36

6
14

Noise Injection to "Band X"
Region (3)

Lines running
same direction

min
max

18
>36

>36
>36

Quiescent Line (High) (4)

Lines running
opposite direction

min
max

5
5

Noise Injection to "Band X"
Region - Quiescent Line (Low)

Lines running
same direction

min

Lines running
opposite direction

min

max

Average of both
directions

(1) Zener Breakdown Endangerment is the potential breakdown of a receiver gate input diode
when the reverse voltage at the input is greater than 5.5V. Induced noise reaching this
potential results in the same endangerment.
(2) The noise generated when endangering Zener breakdown is frequency sensitive and not
line-reversing sensitive.
(3) "Band X" Region is the voltage range between a high state and a low state at which the
threshold level can be situated at any point in this range. The specification range is between 0.8V and 2.0V.
(4) The quiescent line is the line that the noise is induced on. The (low) or (high) designates
its static level.

5.2 PROPERTIES OF #30 AWG WIRE
The propogation delay of typical #30 AWG wiring
(used extensively in DEC systems) is 1.5 ns/ft (4.5
ns/m). Typical wiring has a characteristic impedance
of 120n and TTL voltage transitions are 2.5 to 4.0V
in amplitude, so that the current available at the end
of the wire for rising waveforms is 20 to 30 rnA until
reflections propogate, regardless of the source current
available.

operation. The following system is recommended
when the H900 Mounting Panel series is used.

Bus the ground pins C2, Tl in each module
row with 933 horizontal bussing strip.

Bus the power pins A2 in each module with
the same type of strip.

Tie the ground bus strips to chassis ground
about every 2 in., using solid wire with spaghetti insulation.

Wirewrap all grounded pins together for each
vertical module row.

5.3 THE GROUND SYSTEM
5.3.1 DC Ground System
A good dc ground system is essential to reliable logic

5-3

This ground mesh will form a stable box for satisfactory logic performance. Figure 5-3 illustrates the system.

Figure 5-3 The Ground System

5.3.2 AC Ground System
To keep electrical noise and potential differences under control, the following ground system is recommended although other grounding methods may prove
adequate.

When two cabinets are joined together, they should be
bonded together electrically by running a #4 gage conductor or several copper mesh straps between the two
cabinets. Ordinary stranded #4 gage wire is adequate
for this purpose, although #4 gage welding cable (extra flexible stranding) may be preferred by some.

Upon installation, the purchaser should supply a good
earth ground connection to the central processor
through #4 gage copper wire or equivalent. In general, an adequate earth ground is provided by a steel
beam of a building frame or a large water pipe. Auxiliary units such as the line printer and card reader
should be grounded to their associated control cabinets with #4 gage copper wire (#6 wire can be used in
this case if desired).

The type of the earth ground necessary depends on
the use of the system. A system involving a digitalanalog interface usually requires that the digital system ground be connected to the analog system ground
at a single point, often at the analog-digital interface.
A good ground connection is usually required in these
cases. In small systems where no analog interface is
involved, the grounding provided by a large electrical
conduit may be adequate, although electrical conduit
systems often are connected together poorly in terms
of a low resistance path to ground. In large systems,
additional connections to earth ground may also be
advisable. All of these ground co~nections are additions to (not substitutes for) the ground leads carried
along through the various signal buses (memory, I/O
multiplexer and channel) and the ground conductors
contained in the power (main) cables. The green wire
in the power cable must also be returned to ground,
usually through the conduit of the electrical distribution system.

In general, ground conductors should follow the path
of the data buses through the system (i.e., in parallel
to the memory buses, the I/O bus, the channel bus,
etc.), see Figure 5-4.

MULTISTATION
TTY
CONTROL

ADDITIONAL
PERIPHERAL
UNITS

TTY

9L-0032

Figure 5-4 Typical Ground Mesh System

5-4

5.4 CABLES IN DIGITAL SYSTEMS

Th,e PDP-IS I/O bus consists of two of these cables
terminated at either end by one set of double-height
double sided cards. The signals are distribu ted in the
two cables in the following manner.

The wiring rules of the previous section restrict single
wires to 36 in., when terminated, and certain parallel
runs to only 5 in. Signals to be transmitted 75 ft
down the PDP-IS bus, a set of parallel lines and therefore subject to all of the problems inherent in such
wires, present a special problem.

LAYER A

I/O SYNC H, 10Pl H, IOP2 H, IOP4 H,
SKIP RQ L, PROG INT RQ L.

It is possible to construct a cable which will allow

LAYERB

DSO H - DS5 H, SDO H, SDI H, RD
RQ L, RD STATUS H, I/O PWR CLR
H, SING CY RQ L.

LAYERC

I/O BUS 00 L - I/O BUS 17 L

LAYER A

WRRQ L,INC MBL,+ 1 ~CA INH L,
API 0 RQ L,API 0 GR H, API 0 EN H

LAYER B

API 1 RQ L, API 1 G R H, API 1 EN H,
API 2 RQ L, API 2 G R H, API 2 EN H,
API 3 RQ L, API 3 GR H, API 3 EN H,
DCH RQ L, DCH GR H, DCH EN H.

LAYERC

I/O RUN H, I/O OFLO H, DATA
OFLO H, I/O ADDR 03 L - I/O
ADDR 17 L.

pulses to travel 75 ft at 1 mHz, yet not interfere with
neighboring lines. This is done by establishing a tactical geometry of wires within the cable to isolate sensitive signals from critical transitions and setting up
twisted pair alternate grounding. It uses special insulation, well designed drivers and receivers, and, fjnally,
termination techniques.

5.4.1 The PDP-IS Positive I/O Bus Cable
There are three types of cable assemblies which can be
used on a PDP-IS system. The positive cable, called
the BC09B, is designed to run between PDP-IS positive logic devices. The other two, the BC09A and
BC09C are used when negative logic PDP-9 peripherals
are connected to the system. In this section, the
BC09B will be described. Chapter 6 describes the uses
of all three.

5.4.1.1 Cable Geometry - The BC09B cable (the
same cable as the BC09A and BC09C assemblies use)
contains 36 pairs of twisted wires, each with a characteristic impedance of 68Q. The wires are distributed
in three concentric layers shown in Figure 5-5. The
inside layer A contains 6 pairs, the middle layer B, 12
pairs, and the outer layer C, 18 pairs. Each layer is
twisted independently around the center core of the
cable. Layers A and B are twisted to the right, and
layer C to the left.

Figure 5-5 Wire Distribution

CABLE 1

CABLE 2

With this distribution of signals in the two cables, the
maximum amount of crosstalk picked up under normal operating conditions in any given wire is .45V,
with an average of about .22V. The cable is described
in more detail in Chapter 6.

5.4.1.2 Cable Connections and Terminations - Each
device on the PDP-IS I/O bus (positive) has an input
and an output cable. The two cards must be placed
next to each other and short wires run horizontally to
connect the output pins to the input pins (all except
the ENABLE signals that are being used). For the positive bus, the last device on the line should replace its
output receptacle with a 68Q Terminator Card, Type
M909.

5.4.1.3 Cable Drivers and Receivers - Signals are driven down the PDP-IS I/O bus by specially designed
type M622 modules, and are received by high input
impedance type M51 0 modules. The specifications for
each are given in Chapter 2.

5-5

When DEC logic is not used in the interface, it is important that the drivers and receivers used match the
specifications of the M622 and M51 0 modules.

5.5.2 Wire Insulation
There are three basic types of insulation used at
Digital: PVC (poly-vynal-chloride), TEF (teflon, type
E) and KYNAR.

5.5 GENERAL WIRE INFORMATION

5.5.1 Wire Types
The selection of the correct wire type is the primary
requirement for a properly made connection. There
are two basic types of insulated wire used at Digital.
Solid wire consists of a single copper conductor, usually plated with a coating of nickel, silver, or tin. Solid
wire is easy to use because it is easy to strip, form, and
it stays in place once formed. Its disadvantages are
that it breaks easily if bent sharply or if subject to
constant flexing or vibration. Solid wire, therefore,
should be used only on fixed panels or assemblies, and
never used in cables or to connect two different assemblies which may move or vibrate with respect to each
other.
Stranded wire consists of a series of small solid wires
twisted together. There are seven or nineteen separate
conductors in a typical stranded wire. It has the advantage of being very flexible and difficult to break and,
therefore, is ideal for cables, patch cords, and for making connections between moving assemblies. Stranded
wire's disadvantages are that it requires more ties and
clamps to hold the wire in place and more care in hand-,
ling, as the strands may become spread.

PVC is a rubber-like compound with fair mechanical
strength, low cost and excellent stripping characteristics. The major disadvantage of PVC is that it melts
easily and tends to draw from the heat source. For
these reasons, PVC should never be used in a soldered
connection.
Teflon is a greasy feeling plastic compound with good
mechanical properties, fair stripping characteristics,
and excellent resistance to heat. Its major disadvantages are low cut-through resistance and a tendency to
cold-flow. For these reasons, teflon is preferred for
soldered connections, but care must be exercised so
that it is not pulled tightly across sharp edges. The
cold-flow characteristic will cause the insulation to
move away from the point of pressure. Careless routing of teflon wire may result in exposed conductors
after an indeterminant period of time.
KYNAR is a plastic-like compound with good mechanical properties, average stripping characteristics,
and good resistance to heat. It has much higher resistance to cut-through than teflon and doesn't cold-flow.
KYNAR must be used where wires may be pulled over
sharp edges (Le., hand wire-wrap).
The qualities of these types of insulation are summarized in Table 5-3.

Table 5-3
Properties of Insulation Types
Property
Resistance to Soldering Temperature

5-6

PVC
Poor

Teflon

KYNAR

Excellent

Good

Mechanical Strength

Fair

Good

Resistance to Cut-Through

Average

Poor

Good

Resistance to Cold-Flow

Average

Poor

Good

Ease of Stripping

Excellent

Fair

Average

5.5.3 Wire Insulation Stripping
The correct stripping of insulation is one of the most
important steps in making an acceptable connection.
The insulation must be completely removed, yet the
conductor or conductors must not be nicked or cut.
Using the proper tools makes stripping insulation relatively easy. Diagonal cutters or knives are not the
proper tools. The use of either of these tools will
usually result in a damaged conductor.

the conductor if the proper size opening is used. The
second and more common type of wire stripper has
one opening and an adjustable set screw, see Figure
5-7. This type of cutter is easy to use but requires
constant checking to insure undamaged conductors.
With either type of tool, it is essential to regularly
check that the conductor is not being nicked. This is
easily done by stripping the wire twice and checking
the conductor for damage at the first point of stripping (see Figure 5-8).

The correct tool to use is a wire stripper. There are
two. preferred types available. One type has a fixed
adjustment with a different size opening for each wire
size (see Figure 5-6). It is virtually impossible to nick

A properly stripped piece of wire has no nicks, cuts or
frayed insulation. Under no circumstances can nicks
reduce the area of a conductor by more than 10%.
Stranded wire containing 19 conductors may have a
maximum of I broken conductor; stranded wire containing 7 conductors may have no broken conductors.

Figure 5-6 Non Adjustable Wire Stripper

Figure 5-7 Adjustable Wire Stripper (Use With Caution)

REJECT

ACCEPTABLE - - t - --.t--

REJECT

ACCEPTABLE

CON DUCTOR IS NICKED BY AN IMPROPERLY ADJUSTED WIRE STRI PPE R.

Figure 5-8 Stripping Damage
5-7

5.5.4 Wire Data
The standard wire sizes, colors, and insulation types
presently used at DEC are given in Table 5-4. The
table contains the AWG (American Wire Gauge) size,
the DEC part number, the colors stocked, the number
of strands in the stranded types, and the typical use of
each. Some wire types are available as a twisted pair;
that is, two different color wires of the same size
wound together. This is very handy for ac-power wiring and special uses. Most part numbers have a two
digit number at the end.

digit designates the color of the tracer stripe. A solid
colored wire is designated by both digits being the
same such as "-66" since (it is impossible to have a
blue wire with a blue stripe, etc.).

Digit

Color

Black
Brown
Red
Orange
Yellow
Green
Blue
Violet
Gray
White

3
4

6
7
8

All hook-up wire (excluding twisted pairs) will carry
the two digit class code "91", the five digit body code
and a two digit modifier.

The first digit of the modifier designates the base
color (0 = black, 1 = brown ..... 9 = white), the second

EXAMPLE: 91-07586-92 White wire
with a red stripe

Table 5-4
Solid and Stranded Wires
Stranded Wire (Teflon Type 'E' Insulation)
Size

Part Number

Color

Strands

#10

91-07390-00
91-07390-22
91-07390-66
91-07390-99

BLK
RED
BLU
WHT

19
19
19
19

#14

91-07370-00
91-07370-11
91-07370-22
91-07370-33
91-07370-44
91-07370-55
91-07370-66

BLK
BRN
RED
ORG
YEL
GRN
BLU

19
19
19
19
19
19
19

91-07440-04
91-07440-29
91-07440-09
91-07440-03
91-07440-35
91-07440-06

BLK/YEL
RED/WHT
BLK/WHT
BLK/ORG
ORG/GRN
BLK/BLU

19
19
19
19
19
19

91-07360-00
91-07360-11
91-07360-22
91-07360-33
91-07360-44
91-07360-55
91-07360-66
91-07360-99

BLK
BRN
RED
ORG
YEL
GRN
BLU
WHT

19
19
19
19
19
19
19
19

#18

5-8

Note

Twisted Pair
Twisted Pair
Twisted Pair
Twisted Pair
Twisted Pair
Twisted Pair

Table 5-4 (Cont)
Solid and Stranded Wires
Stranded Wire (Teflon Type 'E' Insulation)
Note
Twisted Pair

Size

Part Number
91-07430

Color
RED/WHT

#22

91-07350-44
91-07350-55
91-07350-66
91-07350-77
91-07350-90
91-07350-91
91-07350-92
91-07350-93
91-07350-94
91-07350-95
91-07350-96
91-07350-97
91-07350-98

YEL
GRN
BLU
WHT/VIO
WHT /BLK WHT /BLK
BRNWHT/BRN
RED
ORG
YEL
GRN
BLU
VIO
GRY

7
7
7
7
7
7
7
7
7
7
7
7
7

91-07420-40
91-07420-25
91-07420-29
91-07420-84
91-07420-15
91-07420-05
91-07420-21
91-07420-26
91-07420-39
91-07636-00
91-07636-11
91-07636-22
91-07636-33
91-07636-44
91-07636-55
91-07636-66
91-07636-91
91-07636-92
91-07636-93
91-07636-94
91-07636-95

YEL/BLK
RED/GRN
RED/WHT
GRY/YEL
BRN/GRN
BLK/GRN
RED/BRN
RED/BLU
ORG/WHT
BLK
BRN
RED
ORG
YEL
GRN
BLU
WHT/BRN
WHT/RED
WHT/ORG
WHT/YEL
WHT/GRN

7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7

Twisted Pair
Twisted Pair
Twisted Pair
Twisted Pair
Twisted Pair
Twisted Pair
Twisted Pair
Twisted Pair
Twisted Pair

91-07678-98

WHT/GRY

Twisted Pair

#26

Strands
19

Solid Wire
Size

Part Number

Color

Insulation

#24-

91-07470-10
91-07470-22
91-07470-33
91-07470-44
91-07470-55
91-07470-66
91-07470-99

BLK
RED
ORG
YEL
GRN
BLU
WHT

TEF(E)
TEF(E)
TEF(E)
TEF(E)
TEF(E)
TEF(E)
TEF(E)

91-07586-44

YEL

TEF(E)

Note

Wire Wrap Machine
Use only 50,000 ft drums

5-9

Table 5-4 (Cont)
Solid and Stranded Wires

Part Number
91-07497-09

Stranded Wire (Teflon Type 'E' Insulation)
Note
Color
Insulation
TEF(E)
BLK/WHT
Twisted Pair

91-07688-SS
91-07688-66
91-07688-99

GRN
BLU
WHT

KYNAR
KYNAR
KYNAR

ECO's Wire Wrap
Hand Wrap
GND Lug Wrap
Connection

#26

91-07694-44
91-07694-SS
91-07694-66
91-07694-99

YEL
GRN
BLU
WHT

KYNAR
KYNAR
KYNAR
KYNAR

Wire Wrap Machine
ECO's Wire Wrap
Hand Wrap
GND Lug Connection

#30

91-0S740-44
91-0S740-SS
91-0S740-66
91-0S740-99

YEL
GRN
BLU
WHT

KYNAR
KYNAR
KYNAR
KYNAR

Wire Wrap Hand Machine
ECO's Wire Wrap
Machine Wrap Repairs
GND Lug Connections

Size

Certain colors have been assigned to standard wire applications in all Digital products. They are summarized in Table S-5.
Table 5-5
Wire Color and Application Chart
Use
Hot
Neutral
AC power}
Cord
Machine Ground

Internal

with a solid covering

Red}

Twisted Pair

+ 1OV Fixed Power
+ 1OV Marginal Power
Ground
-1 SV Fixed Power
-1 SV Marginal Power

Red
Orange
Black
Blue
Green

,....
+ISor+30
+S
-I S
-30
Ground
Auto-Tap

Orange
Red
Blue
Green
Black
Blk & Wht

S-IO

All twisted together

White .
Black

..
PDP-8,8/S,

8/1,8/L

Note

Black
White
Green

Hot
Neutral
Machine Ground

}

Machine
AC Power

9,9/L, 10,
A,B,G,R,
>Sand W
Series
Modules ..

Color

Hand or machine wire wrap

Yellow

Wire-wrap ground lug connections

White

Wire-wrap ECO's

Green

Wire-Wrap Corrections

Blue

Also DC Ground

Twisted Pair

Done at time of
wrapping

5.6 SOLDERLESS CONNECTIONS

A solderless connection is a mechanical technique for
fastening a wire to a post of a lug. Two basic types of
solderless connections are used at Digital; crimped and
wire-wrap. Acceptable connections can only be obtained by the correct use of the proper tools.
5.6.1

Crimped Connections

'Crimped' connectors come in many sizes and shapes.
Typical crimped connectors are shown in Figure 5-9.

In all these connectors, a metal body is compressed
around the conductor. To guarantee a reliable joint it
is absolutely essential that the proper size wire, connector, and tool always be used, see Table 5-6.
The major cause of unreliable crimped connections is
too loose a crimp. A loose crimp occurs when hand
tools are used which can be released by the operator
before the joint is fully made. For this reason, only
ratchet type or air driven hand tools should be used.
Figure 5-10 shows the characteristics of acceptable
and unacceptable crimped connections.

IIFASTON II

~..;.----IISPLICEII

IIFLAG II

IIRING II
Figure 5-9 Crimped Connectors
CONDUCTOR
NOT VISIBLE

WIRE STRIPPED
TOO LONG.

REJECT

CONDUCTOR EXTENDING TOO FAR INTO ~-~
CONTACT AREA.
CONDUCTOR VISIBLE
AND PROPER LENGTH.

REJECT

ACCEPTABLE

I
BOTH CONDUCTOR
END OF CONDUCTOR
I I
AND INSULATION
MUST BE IN THIS AREA.·---.lli _ _ VISIBLE.

Figure 5-10 Acceptable and Unacceptable Crimped Connections
5-1 1

Table 5-6
Wire Size, Connector Type and Tools To Use For Crimped Connections
Connector
Type
FASTON
MALEFEMALE
ADAPTER

RING

Wire Size

Screw
Size

Mfg. Part Numb(~r

DEC Part No.

Tool

#10-#14

AMP-4150

90-07669

AMP-47417

#18--#22

AMP-62025-1

90-06997

AMP-47417

#10--#14

ARC-LESS
300H21A

90-07925

ARC-LESS 100Pl

#10

ARC-LESS 50368
(Yellow)

90-07926

ARC-LESS 50325
(Blue)

90-07927

ARC-LESS 100Pl

#10

ARC-LESS 50364
(Blue)

90-07928

ARC-LESS 50321
(Red)

90-07929

#10

ARC-LESS 50360
(Red)

90-07930

ARC-LESS 100Pl

#14

#18--#22

Pull Test
(Minimum ,Pounds)

SPLICE

#18

AMP-34071

90-06702

AMP-59250

FLAG

#14--#18

AMP-60102-2

90-07931

AMP-47417

Stripping length for all connectors above is 1/4 inch.
5.6.1.1 Insulating Crimped Connections - In many
applications it is necessary to place insulation around
the end of the crimped connection. The most commonly used insulation is heat-shrinkable spaghetti
(shrinky). Before putting a 'shrinky' over a crimped
connection, careful1y inspect the joint. Heat must be
applied carefully or the 'shrinky' will discolor and
crack. The correct tool to use is a heat gun made by

Master Appliance Corp., Model HG 501 Ig. The heat
gun should be held four to six inches from the work.

The spaghetti will be fully shrunk in about 4 seconds.
with the cover on the side of the heat gun fully open.
Figure 5-11 shows properly and improperly shrunk
spaghetti.

'JECT-"SHRIN KY "
POSITIONED IMPROPERLY.

REJECT- EXCESSIVE
HEAT USED.
ACCEPTABLE------;-~~+_

REJECT- MUTILATED
"SHRINKY."

REJECT- II SHRINKY" LOOSE,
INSUFFICIENT HEAT USED.

Figure 5-11 Properly and Improperly Shrunk Spaghetti
5-12

5.6.1.2 Tool Maintenance - Tool maintenance is very
important for insuring properly made crimped connections. It is essential to test the quality of the
crimped joints routinely. All tooling should be checked at least monthly or every 10,000 joints, whichever
occurs first. To test the tooling, crimp four samples
of each size lug, two on the largest and two on the
smallest size wire and perform a pull test. All the
joints must meet the minimum pull test requirement
which are spelled out in the list in Table 5-6.

5.6.2.1 Wire Wrap Requirements

The most important factor in making reliable
wire-wrap joints is the use of the correct tools.
Always use the bits and sleeves outlined in
Table 5-7.

Check the condition of the wire-wrap post
prior to making the connection. It must meet
the following requirements:
(1) No more than a 15° twist.
(2) No more than 10° from the vertical.
(3) No solder build-up over .003 inches.

5.6.2 Wire Wrap
Wire wrapping is used for fairly small (#24 to #30)
solid wire in repetitive applications. It evolved as the
only economical way to easily make the large number
of connections required in today's computers.

The wrap shall meet the following requirements:
(1)

(2)
(3)

A wire-wrapped joint is made by tightly wrapping a
bare conductor around a rectangular post. The post
has sharp edges which cut into the wire as it is wrapped. In a properly made joint, the pressures at the
edges of the post are high enough to cause a cold weld
to take place. For every complete turn around the
post, four welds are made, one at each corner. In a
typical joint, the wire makes six full turns and is therefore fastened to the post at twenty-four places.

(4)

(5)

(6)

Figure 5-12 illustrates the terminology used in wire
wrapping.

*Number of turns see Table 5-7.

I TAPERED TIP OF POST.

"CORNER" OF THE POST.

THIRD LEVEL

4-1/2 to 6 turns of bare wire for #24
wire (.031 x .062 post)*
7 to 9 turns of bare wire for #24, #30
wire (.025 x .025 post)*
1/2 to 2 turns of insulated wire at beginning of wrap.
Spacing between wraps; maximum 1/2
the stripped wire diameter.
No overlap of bare wire, one conductor
on top of another. The first wrap of insulated wire may overlap the last turn of
uninsulated wire in a wrap below.
The last turn of a third level wrap must
not extend into the tapered part of the
post.
The 'end tail' may not extend more than
one wire diameter beyond the wrapped
joint.

WRAP. ----+---...
WRAP OF INSULATION

SECOND
FIRST

LEVEL WRAP.

"END TAIL'~

LEVEL WRAP.-----i---"'''':''
WIRE

THE CONNECTOR BLOCK AND OTHER POSTS
PICTURE FOR CLARITY.

WRAP POST.

HAVE BEEN ELIMINATED FROM THE

Figure 5-12 Wire Wrap Terminology
5-13

The wire used shall meet the following requirements:

(4) The insulation must be 'KYNAR'. (Teflon acceptable for auto-wrapping.)

(1) Stripped length - See Table 5-7.
(2) Stripped conductor must be free from
any scrapes or nicks. The portion of a
conductor which has been removed from
a post may never be reused.
(3) The insulation must be free from nicks or
cuts.

(5) The color code below should be used for
all wire wrapping.
Ground Lugs

- White

Other Hand Wrap

- Blue

Automatic Machine Wrap - Yellow

Table 5-7
Chart of Tools, Wire Size, and Wrapping Requirements for Connectors

Wire
Gauge

#24

#26

#30

Stripping Gardener
Length
Denver
(Inches)
Bit#

Gardener
Denver
Sleeve #

Pull Test
RequireGardener
Denver
Turns of
Turns of
ments
Wire
Insulation
(lbs)
Unwrapping
Min Max Min Max Min Max
Bit

144 Pin (H800W)
Part #12-02244
*

1-1/2

26263

18840

4-1/2

1/2

500130-L-E

18 Pin (H802)
Part #12-02625
*

1-1/2

26263

18840

4-1/2

1/2

500130-L-E

288 Pin (H803)
Part #12-05348
**

1-1/2

505415

502129

1/2

500130-L-E

36 Pin (H807)
Part # 12-091 23
**

1-1/2

505415

502129

1/2

500130-L-E

144 Pin (H800W)
Part #12-02244
*

1-5/8

26263

18840

1/2

500130-L-E

18 Pin (H802)
Part #12-02625
*

1-5/8

26263

18840

1/2

500130-L-E

288 Pin (H803)
Part #12-05348
**

1-5/8

505415

502129

1/2

500130-L-E

36 Pin (H807)
Part #12-09123
**

1-5/8

505415

502129

1/2

500130-L-E

288 Pin (H803)
Part #12-05348
**

1-1/32

504221

500350

1/2

505084-L
505244-L-R

36 Pin (H807)
Part #12-09123
**

1-1/32

504221

500350

1/2

505084-L
505244-L-R

Connector
Type

*Cross Section of Pin .031 x .062 inches
**Cross Section of Pin .025 x .025 inches

5-14

(.1)

The wire must be p~sitioned such that
subsequent routing of the wire does not
tend to unwrap the joint.

(2) Wires should be routed for the shortest
practical length.
(3) Wires must start and end on the same
level. 'Level jumping' should not be allowed.
(4) Allow enough slack when routing a wire
around an unused post to allow a wire
wrap tool to be placed over the post without damaging the wire passing by.

tween an air-driven tool and the chassis
ground, and that AC-powered tools are
operated from an isolation transformer.

The routing of the wire must meet the following requirements:

All repairs, and rework should be performed
in the following manner:
(I) A wire-wrap joint should never be forced
to lower level.
(2) A wire-wrap joint should never be reused.
(3) When changing a wire-wrap joint, either
strip a new section of the wire or replace
it entirely.
(4) Always use the correct color KYNAR
wire.
(5) When working on a panel containing modules, be sure a drain wire is connected be-

5.6.2.2 Wire-Wrap Post Location Standard - It is necessary to be able to locate the 'from' and 'to' end of
any wire-wrap 'run'. The 'from' and 'to' is indicated
by a series of six letters and numbers such as 1A24F I.
The first number identifies the bay or cabinet
(lA24Fl). Since most small systems have only one
bay the first digit is usually not listed. The first letter
identifies the horizontal row (A24F 1). Refer to Figure 5-13. The rows are lettered starting with 'A' from
the top of the bay. The second and third digits identify the vertical column or 'slot' in a particular row
(A24FI). There may be as many as 40 or as few as 12
'slots' in a row. The second letter identifies the pin
(wire-wrap post) in a given row and column (A24Fl).
There are 18 letters used: A through V. The letters
G, I, 0, and Q are not used. There are twice as many
30 gauge pins as 24 gauge pins in a slot. The last digit
(lA24FI) identifies the left or right pin group in a 30
gauge socket (see Figure 5-14). A' l' indicates the left
hand group and '2' the right hand group. This last
digit is not listed for a 24 gauge connector.
A typical 'run' of 24 gauge wire would be:
From A24F to C13R (thus, a 24 gauge wire would
run from row A, slot 24, pin F, to row C, slot 13,
pin R).

COLUMN OR SLOTS

rr----------·----------~A~--------------------~\
1-4

5-8

9-12

13-16

17-20

21-24

25-28 29-32

(A24F)

J
B
HORIZONTAL
ROWS

\'\

/ 1\

(B13N)

(C13R)

\
Figure 5-13 Wire Wrap Post Location Standard

(017S)

12-0020

5-15

tl1 t1 SIDE

"SLO T 11!...-----.!!SLOT 4"
TOP HALF OF A 30 GAUGE
CONNECTOR(288wrap posts)

"SLOT 11-------ISLOT4"
TOP HALF OF A 24 GAUGE
CONNECTOR(144wrap posts)

CLOSE UP OF 30 GAUGE "SLOT 1"

Figure 5-14 Examples of 30 and 24 Gauge Connectors

A typical run of 30 gauge wire would be:
From Bl3Nl to DI7S2 (thus, a 30 gauge wire
would run from row B, slot 13, pin Nl to row D,
slot 17, pin S2).
Every fifth slot, starting at slot 5, is identified by a
piece of red spaghetti pushed over pin A 1. It is fairly
easy, therefore, to locate a particular slot by counting
from the nearest red marker.

5.7 SOLDERED CONNECTIONS
In a soldered connection, a metal alloy is melted,
flows around, and bonds to all parts of the joint. The
most commonly used alloy or solder is a 60% lead,
40% tin mixture. This type of solder is simply called
'sixty-forty'. Solder melts at a relatively low temperature, about 375 0 F. In a properly made joint, the
solder actually forms a chemical bond to all the metal
surfaces it contacts. A clean surface is essential to assure a good chemical bond. Since all surfaces become
contaminated by exposure to air, a cleaning agent is
necessary. These cleaning agents are called fluxes.
Most solder contains the flux. The flux is released
from the core of the solder as heat is applied. Since
the flux melts at a lower temperature than solder, it
cleans the surfaces of the joint just before the solder
flows. Rosin flux is the only acceptable type of flux
for hand soldering.

5.7.1 Soldering Irons
The heat required to melt the solder is usually gener-

5-16

ated by an electrical soldering iron. Many soldering
irons have a built in thermostat which automatically
regulates the temperature of the tip.
The temperature required to solder a joint is the same"
regardless of its size. A larger connection does, how··
ever, require a large soldering iron. The 'size' of a sol··
dering iron is measured by its wattage rating; a higher
wattage soldering iron is required for a larger connec·
tion.
The iron used most often at DEC is a Weller, 48W,
TCP-I with a Weller Model PU-I power unit. This unit
has a thermostat control, safety holder, isolation transformer and tip cleaner, all in one unit.

5.7.2 Solder
It is essential that only the proper type of solder be

used. Digital has standardized on a 63/37 (60/40),
rosin-core wire solder made by Alpha Metals, Inc. This
solder is available in five pound rolls. The wire solder
is the same diameter as #20 wire. This solder contains
a fairly mild flux, which is adequate for soldering all
reasonably clean joints. Solder containing stronger
flux should never be used. Flux is actually a mild cor·,
rosive and should always be cleaned from the joint.
Always check the label on the roB of solder. Never
use any solder which is marked acid core!

5.7.3 Soldered Connection Requirements
a.

The solder in a joint is necessary for electric

continuity, not mechanical strength. Prior to
soldering, a joint must be wrapped tightly and
all wires must contact at least three corners of
the lug or post. The joint must be tight enough
to keep the wire from moving while the solder
is cooling (see Figure 5-15).
b.

The wire must be dressed in such a manner as
to minimize strairi on the solder joint.

All wires on a joint must contact the post or
lug. Do not wrap layers of wire over other
wires (see Figure 5-16). The lower layer may
not solder and will be impossible to inspect.

5.7.4
a.

Use of Stranded Wire (See Figure 5-17)
Stranded wire must be 'tinned' before use.

ACCE'PTABLE'-TIGHTLY+------+
WRAPPED,CONTACTS
LUG IN FOUR PLACES
STRANDED WIRE IS
TINNED.

ACCE'PTABL E' - WI R E
ROUTED PROPERLY
PULLING ON THE WIRE
WILL NOT STRESS
THE SOLDER JOINT.

Tinning involves coating and impregnating the
wire with solder.
b.

Dipping the end of the wires in a solder pot is
the easiest way to 'tin' a large number of ends.
Always clean the residue (dross) off the surface of the molten solder before immersing the
wire.

When tinning, do not allow the solder to run
up under the insulation. This tends to trap
flux under the insulation which may eventually cause corrosion.

Tin only that portion of the wire which is
going to be in the joint. Tinning too much of
the wire makes it stiff and decreases its flexibility.

+----;-.RE'clE'CT- NOT WRAPPED
TIGHTLY, ONLY CONTACTS
LUG I N TWO PLACES
STRANDED WIRE NOT
TINNED.

RE'clE'CT- WIRE ROUTED
INCORRECTLY, PULLING
ON THE WIRE WILL
STRESS THE JOINT.

Figure 5-15 Example of Wire Joint Before Soldering

5-17

I_.-'

ACCEPTABLE- _ _ _ _ _ _r-

-"'l!!'

BOTH WI RES CONTACT
THE POST, NO OVERWRAP.

REJECT- BOTTOM WIRE
OVERWRAPPED, OTHER WIRE
NOT IN CONTACT WITH
POST.

Figure 5-16 Example of Soldering Two Wires on a Post

REJECT-------------~I

__
·_.

·I:---:....-ACCEPTABLETINNING IS
UNIFORM, SOLDER
STOPS AT INSULATION.

NOT TINNED.

REJECTPOORLY TINNED, SOLDER
IS UNEVEN, INSULATION
HAS BEEN MELTED.

Figure 5-17

Acceptable Joint Characteristics - The quality of a
solder can be easily determined by a simple visual inspection. Photos of characteristics of acceptable and

Uses of Stranded Wire

defective solder joints are shown in the following photographs.

_ - - - - - - - - - - - - - - - - , / REJECT-- INCOMPLETE:
SOLDER FILLET
ACCEPTABLEJOINT-OUTLINE
OF WI RE CLEARLY
VISIBLE, JUST
ENOUGH SOLDER.

5-18

REJECT- TOO MUCH
SOLDER-OUTLINE
OF WIRE NOT VISIBLE

REclECT-INSUFFIENT r-----------------.
SOLDER-CAUSED BY
USING TOO SMALL A
SOLDERING IRON ON
A LARGE (#10) WIRE.

ACCEPTABLE-SOLDER
SMOOTH AND SHINY.

ACCEPTABLE

EclECTINSUFFICIENT
SOLDER.

REJECT-SOLDER
PEAK, IRON REMOVED
TOO SOON

REJECT-COLD
SOLDER JOINT,
POUROUS JOINT.

5-19

ACCEPTABLEINSULATION NOT
ENTRAPPED.

REJECT- INSULATIOIN
RUNS INTO SOLDER
JOINT.

ACCEPTABLEJOI NT CLEAN, CAN
BE EASILY INSPECTED.

REJECT- EXCESSIVE
FLUX-JOINT CAN'T
BE INSPECTED.

REJECT- WIRE
STRIPPED TOO
LONG.

ACCEPTABLE
EXPOSED CONDUCTOR LESS THAN1/S~

-1/S"MAX.

5-20

CHAPTER 6
THE I/O BUS SYSTEM

The PDP-IS I/O bus system consists of a level converter, two types of cables and a line of peripherals.
The level converter, called the DWIS Bus Adapter,
changes the positive bus levels of the PDP-IS into
negative bus levels (B-, R-, W-series) of the PDP-9.
Since the two I/O buses (PDP-9, PDP-IS) are compatible in all but single-cycle or direct memory access
operations, most PDP-9 devices can be operated on
the PDP-IS through the DW-IS. The two types of
cables are necessary to interconnect:

positive logic devices (BC09B)

b.
negative logic devices (BC09A)
Peripherals added to a PDP-IS bus system will effect
its electrical characteristics, its decoding, its timing,
latency and priorities.

These parameters are studied in this chapter.
6.1 THE DWIS BUS ADAPTER

The DWIS converts positive PDP-IS bus levels to negative PDP-9 bus levels so that certain PDP-9 devices

will operate on the PDP-IS. To the PDP-IS I/O bus,
the DWIS is just another positive device, with Type
BC09B input and output cables. The positive output
cable attaches to the next positive device. However,
the adapter acts as a T-connector, for it also sprouts
two BC09A negative Output Cables. These attach to
the nearest negative peripheral. Succeeding negative
peripherals are interconnected with two standard Type
BC09A PDP-9 I/O bus cables. Figure 6-1 illustrates
the interconnection scheme. The DWIS automatically
gives API or DCH positive logic devices priority over
the negative logic devices by removing the ENABLE
level of the negative bus whenever a request comes up
on the positive bus.
6.2 PDP-IS I/O BUS CABLES AND CABLE
ASSEMBLIES
There are two types of cable assemblies used in
PDP-IS systems; each type has a different set of connector boards, but the same BC09 cable. The BC09A
cable assembly is used for interconnecting negative
logic devices and the BC09B cable assembly interconnects positive logic devices (Figure 6-1).

MAXIMUM LENGTH OF CABLE FOR----I
POSITIVEBUS=X+Y=75ft

POSITIVE LOGIC
PERI PHERALS

PDP-15
1/0 PROCESSOR

\~------~v~------~
NEGATI VE LOG IC
PERI PHERALS

I-

--------...1-1

MAXIMUM LENGTH OF CABLE TO
LAST NEGATIVE PERIPHERAL = X+Z = 30 ft

15-0083

Figure 6-1 The I/O Bus Cable Sy~tem
6-1

6.2.1 The BC09 Cable Characteristics

Table 6-2
BC09 Electrical Characteristics
Characteristic

Table 6-1 summarizes the physical characteristics of
the cable, and Table 6-2 lists the electrical characteristics. The electrical values shown are estimates, and
where such parameters are critical, it is recommended
that the user perform his own measurements.

Specification

Characteristic Impedance

68S1

Delay

1.8 ns/ft

Risetime

45 ns in 100 ft

Capacitance

25 pF/ft

6.2.2 BC09A Assembly

Table 6-1
BC09 Cable Specifications

36-Pair Cable

Specifications

-----------

Each Pair

24 AWG, 7-strand tinned copper
Type B 600V 105°C per MIL-W16878D

Twin

1.0 in. LHL

Cable
Core

I of filler

First Layer
Second Layer
Outer Layer

6 Pair
12 Pair
18 Pair

5.4 in. RHL
5.4 in. RHL
7.5 in. LHL

Typ~!

.001 in. Mylar tape spiral wrap
25: Overlap

Jacket

.035 in. wall black 802 C Polyvinylchloride

O.D.

Finished Nominal O.D.
.580 in. ± .020 in.

TIle BC09A Cable Assembly consists of one length of
BC09 cable with two Type W850 male connectors
(Figure 6-2). The W850 connectors consist of two
double-height FLIP CHIP boards. TIle size and weight
of the cable and its connectors require that retaining
blocks be used to fasten the W850 connectors to the
Type H800 female connector block of the 1943 panels.
These retaining blocks, designated as H003 and H004
kits, are shown in Figure 6-3. The H003 spans one
H800 block and allows two cables to be plugged into
it. The H004 spans two blocks and will receive four
cables. All the necessary hardware and installation
instructions are furnished with each kit.
The W850 connector has two diode-damping circuits
terminating the lines. The circuit schematic is shown
in Figure 6-4. All input W850 connectors must have
a normal power connection to pin B (-15V); output
connectors need not. Each cable draws 400 rnA of
current .
Two type BC09A cables are needed to complete a bus
connection between two negative devices. General
rules for connecting devices with the cables are given
in the PDP-9, PDP-9/L Interface Manual.

ASSEMBLIES

WITH
WB50
BOARDS

Figure 6-2 BC09A Cable Assembly
6-2

r--~

f---(
I

/' I

INTERNAL

TOO~Ai~~~

-~- ~9;#
J J L'J
nI II
I
1

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H003

•

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f----(

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~--/

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0111111111110

r- -71

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y r/-L - - -

t-1
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--0-8-"""1111111110

LOCK WASHER

FLAT WASHER

L_fl
H004

10-0023

H003, H004 Connector Retaining Block
Kits for 1943 Panels

Retaining Block for H9ll Panel

Figure 6-3 Retaining Block Kits

6-3

GNO
AC

g:"2

l' g~621
~

g:S2

~, g~S2J
R2
270
10'110
2'"

AC
aND

B',"

1 2
1

0--

034

L.&.OIS

OZ4 ...

014

023 ..

: 3
I
1

043

I
a,,"

AlO

T CI

2,"

BB,-15V

REO
BRN

... 012

021 .....
REO

VIO

.... 011

... 010

SLATE

020,.....

- - f--o
019

VIO

REO

I',"

8/10

AT
AU

::~~~(

' 066:! 1
,050 I
066:!,

0''"

GRN

OZ2 ...

APlr- f-~
AR

o--~-+------~-oBJ

,OS2

I
'049,:
Ie
088.~
~ R4 270
10'110

REO
..... 013

VEL

f--o SLATE

g~82
g~62

AB,-I'V

02S ,.....

AKO

g~82

RI
270
10'110
2,"

o - - - - -....-,0==3"""S-=044 c..

04
0682

G',"
,"HT

,.....018

J2B
SRN

028 .....

AB, -ISV

J2A
... 017

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OZ8

037 ...

REO
... 09

88,-I!5V

018

AVO

WHT
-3V STRATE

JIB

JI
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oa
0662

0..-

044

AS. -15V

,,
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034

043

... 033

0~2

... 032

041 ...

BF
BH
aJ

AkO>--~~=:Z=~~-+---o WHT

~C2

R2
270
10'110
2,"

r----

~GNO

'm2 ' f

.. 0 , , 1
0662
,050 I
oeS2 ,

049
8
068Z,
"'
R4
270
10'110
2'"

BB,-15V

---'--'---0 BK

-3V 8TRAT.[
04
oe82
03
DeS2

UNLESS o'rHERWISE INDICATEO:
DIODES liRE 0884
CAPACITIlR9 ARE .01 MFD,IOQV,200/0

g:S2

g~S2

AC ALO
ONo

... 013

022

SLATE

031

O,w---<>BL

BLK
..... 012

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AS

RI
270
10'110

021 ...

020 ...

._--"",-010

019,.....

... 030
RED

BLK

ORN

BLU

REO

VEL

1----0 GRN

ORN

039

BP
"-

029

0· ....

GRN

Oil ...
REO

AVO

BR
9S

0..-

..... 028

037 ...

... 027

o~e

AS,· I&V
,.....0.

GNO

REO

2,"

YEL

BU
BV

Figure 6-4 I/O Connector W850

6.2.3 BC09B Cable Assembly

--0----- C 1

O---E2

0---01

O---EI

O---H2

--0----- F 1

J2
0 - - - K2

Figure 6-6 shows the circuit schematic of the M912
connector.

The maximum length of the positive I/O bus is 75 ft,
and the combined length of the positive bus before
the DW15 and the negative bus after the DW15 cannot
exceed 30 ft. Figure 6-1 illustrates these constraints.

AI
0 - - - 81

------.0

This cable assembly is made up of two BC09 cables
with two M912 connectors at either end and some
associated hardware. It uses the retaining block shown
in Figure 6-3 for the H911 panel. Only one BC09B
assembly (Figure 6-5) is needed to interconnect two
positive logic devices.

6.2.4 Cable Lengths

C2
0 - - - 02

O---HI

-0

0--- J 1

O---M2

-O--KI

0 - - - Ll

O---P2

-0

~Ml

0 - - - S2

-O--NI

0 - - - PI

0 - - - T2

- 0 - - - - Rl

0--- S I

O---V2

-0---- T I

-'15-0085

Figure 6-6 M912 PDP-IS I/O Bus Card
6-4

12- - --,

g~'il

:, '
'e ' o45i-J'
I

047
OSE21
,046 I
oeul
oe.,21

R3
270
10'110
210

IB,-I!5V

Figure 6-5 BC09B Cable Assembly

6-5

6.3 ADDING PERIPHERALS TO THE I/O BUS
When another peripheral is added to a PDP-IS system,
it affects not only the electrical characteristics of the
I/O bus, but the rest of the peripherals, the speed of
the entire I/O complex, the software operating system;
and the memory map. How these parameters are
affected is described in the following paragraphs.

6.3.1 The Electrical Characteristics of the Bus
The positive I/O bus will electrically support SO devices which accept an input cable and pass on an output cable; if each device draws no more than 40 JlA
from a signal through its MS 10 receiver. Further, 16
devices can be added to the negative portion of the
bus. However, there are certain other system constraints which could limit the number of certain types
of devices.
\
I

6.3.2 Device selict Codes
Each PDP-IS peripheral is assigned a set of unique device select codes which are decoded from the lOT
instruction. There are 28 , or 2S6, such codes available
on the system, and it is vital that no two peripherals
have the same code. Obviously, two identical peripherals, such as Type TC IS DECtape Controllers, cannot
be added unless one is first modified to change its device select code. This also means that the system software (device handlers) must be changed to recognize
the new codes. A designer adding a special peripheral to a PDP-IS system must be careful that the device
codes selected are not used by a present or planned
peripheral.
Table 6-3 shows all codes presently used by standard
peripherals. Since there are a limited number of
codes, the peripherals on the system must acknowledge this constraint. It ~s recommended that the designer refer to the codes used by each device on his
system as listed in its respective manual, before committing himself to a design.

address (data channel). These addresses are recognized
by the system software according to Tables 6-4, 6-5.
The designer must be very careful that the addresses
he selects for his special system do not violate the
rules of his software operating system.
There are 28 addresses assigned for API devices, and 8
for multi-cycle data channel devices. This restricts the
number of API devices to 28, and multi-cycle data
channel devices to 4. This is another constraint 0][1
the number of devices which may be attached to the
I/O bus.

6.3.4 Timing Constraints
The number of devices which use anyone of the AP][
levels cannot exceed eight; if this number is exceeded
there may be timing errors due to the time it takes
the enabling level to propogate through the cable and
the MI04 modules in each device. This same COll-straint applies to data channel devices. Only eight de·vices which use the data channel (single- or multicycle) can operate on anyone PDP-IS system.

6.3.5 System Latency and Priorities
A design engineer may wish to know if the system will
respond quickly enough to his peripheral when it posts
a request for transfer, an error condition or an alarm.
This question can be answered only when the designelr
can indicate the state of the other peripherals (e.g., Is
the A/D converter transferring and possibly blocking
out the device?); the time it takes the operating system
to respond; and how long the peripheral can wait before the information is lost. Table 6-6 shows some figures for a typical PDP-IS system. Table 6-7 lists some
of the latency figures which assume in each case that
the device in question is not interfered with by any
other device. It is interesting to note that latencies
sometimes overlap in a system. Note that latency is
defined as the time between a request for data transfer
and the completion of the transfer.

6.3.3 Addresses

6.3.6 Cable Runs and Terminations

Each peripheral which uses the API or the multi-cycle
data channel facility is assigned unique core locations
for their trap address (API) or word count and current

The PDP-IS I/O bus originates at locations MN02 and
MN03 in the PDP-IS I/O processor and chains its way
from device to device to interconnect all peripherals.

6-6

Table 6-3
Assigned PDP-IS lOT Device Selection Codes
00 I RT Clock
2 Prog. Interrupt
4 RT Clock

40 LT19A
Line 1,2,3,4
Teleprinter

70 DEC Disk
RF15

01 PerforatedTape Reader
PC15

11 Analog-toDigital or
Digital-toAnalog
Converter

21 Relay Buffer 31 VT15
DR09A

41 LT19A
Line 1,2,3,4
Keyboard

02 PerforatedTape Punch
PC15

12 AID or
D/A
Converter

32 Power Fail
22 DB98 & 99
Grafpen
Interprocessor buffers

42 LT19A
Line 5,6,7,8
Teleprinter

72 DEC Disk
RF15

03 1 Key board
2 Keyboard
4 IORS

13 AID
Converter

33 1 33 KSR
Skip
2 Clear All
Flags
4 DBR,DBK

43 LT19A
Line 5,6,7,8
Keyboard

63 Disk Pack
RP15

73 Mag Tape Control
TC59D

04 Teleprinter

24 Incremental
Plotter Control XY15

44 LT19A
Line 9,10,11,12
Teleprinter

64 Disk Pack
RP15

74 Mag Tape Control
TC59D

05 Displays
VP15

45 LT19A
Line 9,10,11 ,1 2
Keyboard

55 Automatic 65 Automatic
Priority
Line Printer
Interrupt
LP15
KA15

75 DECtape Control
TC15

76 DECtape Control
TC15

i
I

06 VP15

46 LT19D
Line 13,14,15
Teleprinter
LT15A

66 Automatic
Line Printer
LP15

07 Display and
Light Pen
VP15BL

17 Memory
Protection
KM15

27 Memory
Parity
MP15

47 LT19D
Line 13,14,15
Keyboard
LT15A

67 Card Reader 77 Bank Addressing
Type CR03B
Instructions

I
0'.

30 VT15

Table 6-4
API Addresses

Channel
Number
(Octal)

Trap
Address

a
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37

40
41
42
43
44
45
46
47
50
51
52
53
54
55
56
57
60
61
62
63
64
65
66
67
70
71
72
73
74
75
76
77

Suggested
Priority
Level

Sta ndard Device

Soft war e channel a
Soft war e channell
Soft war e channel 2
Soft war e channel 3
DECtap e (TC15)
Magtape, (TC59)

Pap er T ape Reader
CIo ckO verflow
Pow er F'ail
Pari ty (MPI5)
VTl 5
Card Re·aders (CR03B)
Lin ePn'nter (LPI5)
A/ D(A FOI )
DB 99A /DB98A
Dat aLi nk to System 360
Dat a Ph one (DP09A)
RFI 5
RPI 5

4
5
6
7
1
1
1
1
2
3
0
a
2
2
2
0
3
3
2
1
1

3
3

Tel etyp e LT19D
Con trol LT19D
Vneassigned

Table 6-5
Data Channel Addresses
Device
Interprocessor Buffers
DB99,98

6-8

Word Count

Current
Address

22,24

23,25

Not presently assigned

DECtape TC15

Magtape TC59

Not presently assigned

RF15

I/O ADDR
Bits 12-17
lOa 000
100001
100010
100011
100 100
100 101
100 110
100 III
101 000
101 001
101 010
101011
101 100
101 101
101 110
101 III
110000
110001
110010
110011
110 100
110101
110110
110111
III 000
III 001
111010
111 011
111 100
111101
111110
111111

Table 6-6
Worst Case Latency, PDP-IS Peripherals
Allowable
Latency
(in /Js)

Maximum
Transfer
Rate

Device

Worse-Case Latency
in this system
(in fJ.S)
-7

RP 15 Disk Pack

130,000* word/second

RS 15 DECdisk

62,000 words/second

TU55 DECtape

5,000 words/second

200

LP15 Line Printer

1,000 lines/minute

40**

Real-Time Clock

1,000 cycles/second

1,000

PC15 Paper Tape System

300 characters/second (reader)

3,333

62 + subr

CR03 Card Reader

200 cards/minute

3,750

190

KSR 35 Teletype

10 characters/second

100,000

250
~~

*The RPI5 is double-buffered with two 36-bit registers. Two 18-bit words are transferred back-to-back on the I/O bus.
**The LP15 transfers two 18-bit words every 40 /JS. (Preliminary information)

Table 6-7
Worst Case Latency Figures (/Js)
Multi-Cycle Data Out (From Memory)

Multi-Cycle Data In

Add to Memory

Increment Memory

Single-Cycle Data Out (Normal Mode)

Single-Cyc1e Data In (Normal Mode)

Each cable enters a free standing cabinet from the
bottom, and connects devices from bottom to top.
The cabinets are about 6 ft high so that about IS ft
of cable per free-standing cabinet, or 9 ft per cabinet
if they are bolted together, should be anticipated if
more than three different devices are to be interconnected within a cabinet.
The last device on the positive I/O bus must plug a
Type M909 68[2 Terminator Card into the slots usually assigned to its output I/O bus cable. Figure 6-7
shows the I/O bus drive/termination scheme.

M909
+5V

TERMINATOR

6an
6an
PDP-15 I/O PROCESSOR

THIS TERMINATOR CARD
MUST BE PLACED IN
THE OUTPUT CABLE SLOT
OF THE LAST DEVICE
IN THE SYSTE M.
15 -0104

Figure 6-7 The PDP-IS I/O Bus Drive/Termination Scheme

6-9

6.4

DESIGNING PDP-IS DEVICES TO OPERATE
ONTHEPDP-9

Most PDP-15 peripherals will operate from a PDP-9
through its I/O bus provided the positive PDP-I 5 I/O
bus signals are converted to the corresponding negative
PDP-9 leveJs. The only exceptions are single-cycle
data channel devices, which have no PDP-9 equivalents.
All peripherals designed with DEC logic must use
M510 receivers and M622 drivers. In order to simplify the level converting needed to operate such
peripherals on the PDP-9, two level converting modules
(pin compatible with the M510 and M622) called the
M500 and M632, respectively, are available. These
modules conform to PDP-9 I/O bus requirements, and
convert negative output signals to positive levels, and
positive input (drive to computer) signals to negative
PDP-9 X!O bus levels.. They are described completely
in Chapter 2.
The M I 04 module is then replaced with an M194
which converts the EN IN and EN OUT levels to their
appropriate voltages.
All of these modules are described in Chapter 2.
Any PDP-IS device which is placed on the PDP-9
I/O bus must be cabled with either a BC09B cable

assembly if it is connected to other PDP-I 5 devices,
or with a special cable called the BC09C if it is connected to regular PDP-9 devices.
The BC09C cable assembly is a hybrid of the BC09A
and the BC09C cables. It has a BC09B(M912) termination at one end and two BC09A(W850) terminations
on the other. Two BC09 cables make up the rest of
the assembly.
The BC09B end of the BC09C cable is plugged into
the appropriate slot of the converted PDP-IS device.
The two BC09A terminations then go to the neighboring PDP-9 device.
Figure 6-8 shows the BC09C cable, and Figure 6-9
illustrates how it should be connected.
In summary, to convert a PDP-15 device to operate
on the PDP-9, it must first not use the single cycle
data break and then must submit to the following
operations:
1) Replace all M51 0 receivers with M500 receivers.
2) Replace all M622 drivers with M632 drivers.
3) Replace all M 104 multiplexers with M 194 multiplexers. Use BC09B cables to interconnect converted PDP-I 5 devices, and BC09C cable assemblies to interconnect converted PDP-15 devices
and PDP-9 devices.

ASSEMBLY WITH
M9t2 . BO~RDS

ASSEMBLIES WITH . - - - - . '
W850 BOARDS

BC09

Figure 6-8 The BC09C Cable
6-10

PDP-9
DEVICES

CONVERTED
PDP-15 DEVICES

r===:::-~-~

____

______

PDP-9
DEV I CE
~

PDP-9
NO
TERMINATION
REQU I RED
15-0103

Figure 6-9

Cabling Converted PDP-IS Devices
to the PDP-9 I/O Bus

6-11

APPENDIX A
DOCUMENTATION

Documentation practices become important when the
computer user attempts to understand or repair his
system. To facilitate these functions, the documentation provided must accurately and completely describe
each element and reflect the interrelationships of all
elements within the system. DEC provides the types
of engineering drawings listed and described in this
appendix to fulfill this requirement.

A.I DRAWING INDEX LIST

The Drawing Index List provides a pictorial and tabulated index of the manufactured components and
electrical drawings which comprise a product, subdivided into its complete assembly, subassemblies and
parts. These terms are defined below.

A.2 DRAWING CATEGORIES

The drawings themselves are divided into the following
categories:
AD

Depicts the assembled relationship of two or
more subassemblies and/or parts joined together to perform a specific function.
AP

Block Diagram Drawing (Reference)
Describes the overall concept and/or organization of a unit or system by the use of rectangular blocks, representing functions or groups
of functions, and by interconnecting lines
which show the relationship, information flow,
and sequence of operation between the blocks.

Block Schematic Drawings (Reference)
Shows, by means of lines and graphic symbols
located in sequence of functions, the logical
elements of a circuit or system of circuits.

Parts List - a tabulation of the names and drawing
numbers of the assemblies, subassemblies and parts
which make up the product.
CL

Figures A-I and A-2 show a complete drawing index
list for the PDP-8/S computer as an example.

Arrangement Drawing (Reference)
Shows any projection or perspective of items
to indicate their relationship. This type of
drawing normally does not contain any controlling dimensions.

Part - one piece or several pieces which are normally not subject to disassembly without destruction of the piece in use.
Find Number - an index number which identifies
the assembly or subassembly with its supplementary
information in the Drawing Index Parts List.

Appendage Document (Reference)
Supplements an existing wire list document;
normally machine-produced as an expedient
way to document minor variations.

Assembly - assembled relationship of two or more
subassemblies and/or parts joined together to perform a specific function.
Subassembly - two or more parts which form a
portion of an assembly. A unit replaceable as a
whole, but having a part or parts which are individually replaceable.

Assembly Drawing (Construction)

Cable List (Reference)
Describes, in tabular form on A-size or larger
sheets, the connecting points between connec-

A-I

and includes forms, dimensions, material finish, tolerances and other requirements as applicable.

tors or from logic to connectors. The list may
present wire color, length, type of connector,
location, type of cable, and signal names.
CP

Components List (Reference)

Circuit Schematic (Reference)
Shows, by means of lines and graphic symbols,
the components used in a circuit. The symbols
are so placed that the circuit can be traced in
sequence of functions.

Detail Assembly Drawing (Construction)

Inseparable Assembly Drawing (Construction)
Depicts items permanently joined together to
form an integral unit. The items mayor may
not have separate detail drawings.

the external wiring connection between different assemblies of a unit or between units of
a system such as cable diagrams and power
wiring.
KS

Mechanical Detail Drawing (Construction)
Delineates information to describe an item,

A-2

Printed Circuit Drawing (Reference)
Accurately scaled taped layout on a dimensionally stable material depicting the conductive pattern of electrical components.

Parts List (Reference)
Lower level assemblies - is a tabulation of
reference drawings, fabricated and purchased
parts necessary to manufacture and assemble
an end item.

Replacement Schematic Drawing (Reference)
Duplicate representation of a circuit schematic
having a different format and an Electronic
Industries Association (EIA) conversion chart
for transistors and diodes permitting customer
procurement of defective parts.

Key Sheet (Reference)
A site-orientated document which lists the unit
model numbers making up a customer system
and their serialized identification. This includes any over-all system drawings needed for
installation, maintenance, arrangement studies,
and functional explanation, programming and
maintenance manuals, test checkout and acceptance procedures and any over-all equipment or customer specifications.

Interconnection Drawing (Reference)
A foml of connection diagram which shows

Outline Drawing (Reference)
Shows over-all size of equipment, clearances,
mounting dimensions and other necessary
dimensions and notes to describe mechanical,
electrical requirements for installation purposes.

Flow Diagram Drawing (Reference)
Graphical presentation of equipment or system which explains the signal flow for individual instruction inputs or for classes of instruction inputs.

Module Utilization Drawing (Reference)
Depicts module type, location, and the name
of the logical elements being used for each
module represented.

An assembly drawing, which depicts some
items in detail on the drawing in lieu of preparing separate detail drawings.
FD

Master Drawing List (Reference)
Unit assembly level (highest level) - is a tabulation of engineering drawings such as block
schematics, flow diagrams, timing diagrams
and 1st level assemblies of a unit assembly.

Tabulates electrical components and their
value and connecting points, which are external to a mounting panel wiring plane.

Source Control Drawing (Construction)
Specifies the source which exclusively provides the performance, installation, and interchangeability characteristics of an item that
has been selected and tested for a specific application by Digital Equipment Corporation.

System Diagram Drawing (Reference)
A site drawing in outline, block or plan view
form and any details that include the name,
type and model designation to identify each

assembly, unit, and group of units of a system
arranged in approximate physical relationship
to each other.
SP

Wiring Diagram Drawing (Reference)
Line drawing which shows production the connecting points on the mounting panels for
each wire run tying together the modules of a
system. Components attached to the wiring
plane may be represented.

Silk Screen Drawing (Construction)
Accurately scaled layout on a dimensionally
stable material depicting the nomenclature for
identifying functional controls, reference designations and notes on panels, consoles, chassis, brackets, etc.

Unit Assembly Drawing (Construction)
Shows assemblage of any combination of two
or more parts, assemblies, subassemblies, and/
or units mounted together to form, as a whole,
predominantly wired equipment normally capable of independent operation in a variety of
situations.

Specifications (Reference)
Engineering documents intended primarily for
use in procurement and construction which
give clear, accurate descriptions of technical
requirements for items, materials and equipment characteristics.

Wire List (Reference)
Presents the same information as a wiring diagram in tabular form.

Timing Diagram Drawing (Reference)
Shows the timing relationship of important
pulses, levels and transitions throughout a unit.

Examples of these drawings are available in the prints
supplied with the PDP-IS.

A-3

Figure A-I

Drawing Index List PDP-Sis

A-5

MECHAN ICAl
FI ~(
NO

DESr.RI PTinN

DEP'
PART ND

TABLE IIOOEl POP-8S
TABLE MOOEL POP-8S (P. L. )
GU I DE. TOP COVER
SHiElD, FILTER CIRCUIT
SlOE BRU. SHROUD
SPACER. SHROUD
COVER. BOTTOM
AIR EXHAUST
FOOT. RUR
POSITIONING PLATE
PEZEl CASTING REtORK
SIDE POS. PLACE

O-UA-85-0-0
A-PL-85-0-0
l1-li0-7405405-0-0
C-II0-7405569-0-0
l1-li0-7405402-0-0
l1-li0-7405401-0-0
0-110-1405404-0-0
0-110-7405397-0-0
8-110-7405403-0-0
l1-li0-7405410-0-0
0-110-1405414-0-0
A-1IO-7406 I 90-0-0

TOP COVER

0-1 A-7405409-0-0

Stl TCH BOARO ASSY
SPACER~2 SII TCH BOARO
ROCKER SI pS-50-FB-PC (L T GRY)
ROCMER SI RI-50-FB-PC (BUR DAN)
~IOCMER SI R5-9-3-FB (BL'R ORN)
SPACER# I SII TCH BOARO

0-1 A-540lBl6-0-0
C-II0-55D3902-0-0
C-A0-54C4423-2.0
C=-AO-54D442l-3-0
C-AO-5404422-2-0
C-IIO-S5D3839-0-0

ETCH BOARD, SII TCHES
EPOXY BOARO
PRINTED CIRCUIT LAYOWT

0-1A-5003836-0-0
1405020-0-0
5003836-0- 2

CONTROL PAN£L ASSY
CONTIiOl PANEL ASSY (P, L. )
SIl~ SCREEN-STEPfl(GRAy)
SILK SCREEN-STEPH2(RUS.OAN)
SILK SCREEN-STEPH3(8URNT ORN)
SILK SCREEN-STEP#4(SLK)
GLASS PANEL

O-A0-7005191-0-0
A-PL-1005191-0-0
C-SS-7405621-0-0
1:-55-7405822-0-0
C-S5-1405623-0-0
I:-S5-1405289-0-0

I NO I CATOR LI GHT BOARD ASSY

ETCH BOARD II GHTS( POP-8S)
EPOXY .BOARD
PRINTEO CIRCUIT LAYOUT

p-I A-S0038 3S-0-0
1405019-0-0
5003835-0-2

GLASS SUPPORt

P-I A-7 4054 12-0-0

I
6

tiRING CASTING ASS'Y (4K)
tiRING CASTING ASS'Y (4K)(P.L.)
tiRING CASTING REIOA~
WIRED ASSY CASTING (C.P.)
liRE LIST POP-8S (8K)
tiRING CASTING ASSHBR)
IIRING CASTING ASS·Y(8K)(P.1.)
tI RING CASTI NG REIOR~
II RED ASSY CAST I NG (C. p • )
IIAE LIST POP-8S (BM)
MTG BAR ASSY (10 CONN. BLOCKS)
IITG BAR ASS'Y (10 CONN BLOCKS)

FIND
NO
15

DEPT

DESCRIPTION

PART NO.

REAR PANel ASSY 50 , 60 CYCLE
REAR PANEL ASSY 50 , 60 CYCLE
SUPPORT GUSSET (L.H.)
PI VOT BRKT
TOP COVER STOP
SUPPORT GUSSET (R H. )
FAN SCREEN
MARG CHK SCOTCHCALS
PROTECTI ON COVER
(TRANSFORIIER CHK LABEL
(50 CYCLES'ONLY)
INPUT POtER LABEL
(60 CYCLES)

O-A0-7005193-0-0
A-PL-7005183-0-0
C-IIO-7405 395- 1-0
iHlO-7405393-0-0

FAN MTG PLATE

1:-1 A-140S42S-0-0

COMPONENT IITG PLATE

0-1 A-74D539 1-0-0

SPACER. FAN

1:-1A-7405426-0-0

QUI C~ RELEASE lin PLATE

C-IA-1405386-0-0

SI DE SHROUO
SI DE SHROUD( l.H )
SIDE SHROUO(R.H.)

0-1 A-U05394-0-0
0-1 A-1405394-1-0
0-1 A-1405394-2-0

D-M}-74D54 I I -0-0

AI R 8AFFLE

E-IA-7405399-0-0

10-1 A-5403833-0-0

IITG BRKT. REAR PANEL

1:-1 A-7405400-0-0

K-Il-85-0-21
O-A0-1005327-0-0
I-PL-'7005327-0-0
-110-1405413-0-0
-CP-85-0-31
-IL-1I6--0-21
I-A0-7005099-0-0
I-PL-100S099-0-0

MTG BAR STD
IITG BAR

II-A0-1 ODS I 03-0-0
L1-1I0- 74050 3S-0-0

CAPAC I TOR HOUS ING ASSY
CAPAC I TOA HOUS I NG ASS' Y (PL)
JUIIPER (BLK)
JUIIPER (BlM)
JUIIPER (REO)
JUMPER (BLU)
CONN liRE (BlU)
CONN tl RE (BlK)
CONN "RE (RED)
CAP CONTAI HER
JUMPER {BLU)

-A0-7005190-0-0
A-PL-7005190-0-0
0-1 A-140S360-2-0
0-1 A-7405360-4-0
0-1 A-7 405360-S-0
0-1 A-7405360-1-0
0-1 A-7 405359-2-0
0-1 A-7405359-1-0
0-1 A-1405359-3-0
D-II0-1405401-0-0
0-1 A-7405360-3-0

CAP. HO LO-DOIN 8AU.

1:-1 A-140S406-0-0

POIER II AING HARNESS

0-1A-7405648-0-0

TELETYPE CONTROL PT06-A
TELETYPE CONTROL PT06-A (PL)
1943 MTG PANEl LABEl
lEFT END PANEl

D-UA-PT06-A-O
A-PL-PT08-A-O
55-100153-1
C-IIO-I943-0-1-0-2

PT08 II REO ASSEMBLY
PT08 11 RED ASSEIIBL Y (Pl)
1943 FRAIIE CAST REIORK

O-A0-1005304-0-0
A-PL-7005304-0-0
C-II0-740553 1-0-0

CONN CABLE 85-PT08

C-I A-1405600- 1-0

POUR CORD PT06-A TO POP8S
POIER CORD PT08-A TO PDP-8S (PL)

I:-A0-1005289-1-0
A-PL-1005289-0-0

CABLE 4915 TO 1070
CABLE 4915 TO 1070 (PL)

O-A0-7005286-1-0
A-PL-7005288-0-0

ASR TTY tI TH PT08-A OPTI ON
ASR TTY WITH PTOe-A OPTION (PL)
ASR 33 TELETYPE STANO (REWORK)
PROTECT I ON PLATE ASR 33

O-A0-7005043-0-0
A-PL-1005043-0-0
C-II0-1405529-0-0
1405292-0-0

4K MEMORY

NO # AVAILABLE

H281 IIEIIORY (8K)

O-SI:-3005120-0-0

OESCR I PT I ON

PART NO.

TABLE IIODEL POP-8S(4K)
WIRING CASTING ASS'!
IIRING CASTING ASS'Y
WI RE II ST POP-8S
IIEIIORY BLOC~ 0 I AGRAM
POP8S BLOCM 0 I ACRAII
m~NGs~mm TilliNG DIAGRAM

A-Ml-85-0
0-A0-7005265--0-0
A-PL-7005265-0-0
K-tl-85-0-6
O-B5-85-0-4
O-B0-85-0-2

liB
AceNT
BTG
IIA
lORD TillE GEII.
AODER
CONTROL
IR
110
MEIIORY
P.C. REGISTER
ACCUIIULATOR
10 CABLE SCHEDULES
IIEMORY BLOCK IIU( 4K)
MEIIORY BLOCK IIU( 4K)

55-100 I 04-1

E-I A-7405396-0-0

E~HP2:~82?i0-0

FIC

FINO
NO

C-IIO-7405389-0-0
I:-S5-IOBOI
iHl0-7404508-0-0
S5-100105-1

REAR PANEL

P-A0-700526S-0-0
iA-P l -1005265-0-0

PROD CUS

ELECTR I CAL

U AGE

~0-1405392-0-0
1:-1I0-7405395-~-0

MECHANI CAL

U~IIGE

PROD CUST FIC

TABLE 1I00El Af)P-8S(8K)
WIRING CASTING ASSY
II RE LI ST POF-SS( BK)

~a'~~l m~~ gm~~~(8K)

KEYS SIITCHES TilliNG 01 AGRAM
TIlliNG DIAGRlII
IB
ACCNT
BTG
MA
lORD TillE GEN
ADOER
CONTROL
IR

110

MEIIORY (81)
~.C. REGISTER
ACCUMULATOR
MEIIORY BLOCK MU( BK)
IIEIIORY BLOCK IIU( BK)
10 CABLE SCHEDULES
CABLE INTERFACE PDP-8/S

PROD

CUS

F/C

8:f8:=tg:~

O-B 5-8 5-0-9
0-85-85-0..10
0-85-85-0-11
0-85-85-0-12
O-B5-85-0-13
O-B5-85-0-14
0-85-85-0-15
0-85-85-0-16
0-85-85-0- 11
O-B5-8 5-0- 1B
0-85-8S-0-19
0-B5-85-0-20
O-Cl-85-0-5
0-IIU-B5-0-26
A-Pl-B5-0-26
A-IIL-8S-0
O-AO-l005327-0-0
K-Wl-8S-0-21

B:~~a~8:~3
0-TO-B S-O- I
0- TO-8S-0-3
0-85-85-0-9
O-BS-85-0-10
O-B5-85-0-11
O-B5-85-0-12
O-B5-85-0-13
0-85-85-0-14
O-B5-85-0-15
O-BS-85-0-18
O-B5-85-0-17
0-B5-85-0-22
O-B5-85-0-19
0-8S-8S-0-20
D-ll1I-85-0-25
A-PL-85-0-25

0-1 C-BS-0-32

REAR PANEL ASS'Y (SH 3 OF 3)

O-A0-1005193-0-0

TELETYPE CONTROL PT08-A
(IITG IN TELETYPE)
TELETYPE CONTROL PToe LOGIC
1I00UlE lOCATION TYPE PT08
MODULE LOCATION TYFE PT08
WIRING LIST TYPE PT08
PT06-A tI REO ASSEMBLY
TElETYPE 1100 (ASR-33)

O-B5-PT08-A-1
D-IIU-Pl08-A-2
A-PL-PT08-A-2
A-1l-PT06-A-3
C-A0-1005304-0-0
D-IC-7Sg516S-O-0

4K IIEMORY

NO # AVA ILABlE

HZ! 1 lIellORY (BK MEIiORy)

O-SC-3005 I 20-0-0

CIRCUIT SCHEM. LIGHT BD-

-SC-5003635-0-1

A-IIL-PT08-A-0

IQTY·I
I

Figure A-2

DESCRIPTION

P~RT NO.

liTEM
NO.

P~RTS LIST

Drawing Index List PDP-sis

A-7