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EK-DTE20-UD-003
July 1976
126 pages
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Document:
DTE20 Ten-Eleven Interface Unit Description
Order Number:
EK-DTE20-UD
Revision:
003
Pages:
126
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OCR Text
EK-DTE20-UD-003 DTE20 TEN-ELEVEN INTERFACE UNIT DESCRIPTION digital equipment corporation « marlborough, massachusetts I1st Edition, July 1975 2nd Edition (Rev), January 1976 3rd Edition (Rev), October 1976 The drawings and specifications herein are the property of Digital Equipment Corporation and shall not be reproduced or copied or used in whole or in part as the basis for the manufacture or sale of equipment described herein without written permission. - o - Copyright © 1976 by Digital Equipment Corporation The material in this manual is for informational purposes and is subject to change without notice. Digital Equipment Corporation assumes no respon- sibility for any errors which may appear in this manual. Printed in U.S.A. This document was set on DIGITAL’s DECset-8000 computerized typesetting system. The following are trademarks of Digital Equipment Corporation, Maynard, Massachusetts: DEC DECtape DECCOMM DECUS PDP RSTS DECsystem-10 DIGITAL TYPESET-8 DECSYSTEM-20 MASSBUS TYPESET-11 UNIBUS " CONTENTS INTRODUCTION .......................... DTE/1-10 — e DTE/1-9 DTE/1-10 DTE/1-10 N [N DTE/1-6 DTE/1-9 Diagnostic Bus Control Diagnostic Functions with 36-Bit Data Transfer DTE/1-12 WW W N o DTE/1-4 BYTE TRANSFER FUNCTION Diagnosing the KL10 PP ek s e pd ek et et et ek et ek ek e et DTE/1-1 DOORBELL FUNCTION ERROR OVERVIEW I ek ek ................. DIAGNOSTIC OVERVIEW R Dk ............................ BASIC PROGRAMMING OVERVIEW s et pmewk IS NSRS U S IS IS IS IR - - N it OVERVIEW Nt NEV IS SRV S SECTION 1 ek Page 0 Data Transfer DTE/1-13 Interrupt Requests DTE/1-13 DTE/1-14 Processor Interrupt Procedure DTE/1-14 Unibus Signal Lines DTE/1-17 DTE/1-17 DTE/1-17 DTE/1-18 Priority Transfer Lines Miscellaneous Control Lines EBus Signal Lines Priority Transfer Lines DTE/1-20 INTERFACE DATA AND CONTROL BUFFERING DTE/1-20 Addressable Register Summary DTE/1-35 BUS OPERATION PROGRAMMING EXAMPLES ..................... SECTION 2 FUNCTIONAL DESCRIPTION 2.1 BUS INTERFACING PDP-11 SIDE 2.2 BUS INTERFACING EBOX SIDE 2.3 DTE/1-12 INTERFACE COMMUNICATION DTE/1-36 DTE/2-1 DTE/24 INSTRUCTION AND DATA TRANSFER IMPLEMENTATION DTE/2-4 DTE/2-5 OVERVIEW-EBOX SIDE 24 INSTRUCTION IMPLEMENTATION PDP-11 SIDE 2.5 FUNCTIONAL OPERATIONS OVERVIEW ' 2.5.1 Deposit Overview 2.5.1.1 Deposit Operation DTE/2-6 DTE/2-6 DTE/2-8 252 Examine Overview DTE/2-17 DTE/2-17 25.2.1 Examine Operation 253 TO11 Transfer Overview. . . 2.5.3.1 254 TO11 Transfer Operation TO10 Transfer Overview iii . . . .. .. ... ... .. ..... DTE/2-18 ‘ DTE/2-23 DTE/2-26 CONTENTS (Cont) LOGIC DESCRIPTIONS DATA PATH ORGANIZATION . . .. .. . ... ... . ...... Random Access Memory (RAM) EBusDrivers EBus Receivers . . . .. ... .. ........ . . . . . . . . . . . . . . . Diagnostic Bus Drivers . . . DTE/3-1 DTE/3-1 e ... DTE/3-1 . . . ... DTE/34 . . . . . . ... ... DTE/34 . . . . . .. ... ... .. DTE/3-4 . . . . . ... .. ... .... DTE/34 Miscellaneous Mixers and Combinational Logic DTE/34 . . .. .. ... ....... DTE/34 Access ControlLogic . . . . .. .. .. ... ... .. .. .... DTE/34 3.2.2 KL10 EBus Dialogue . . . . e e DTE/3-5 323 PDP-11 NPR Dialogue . . . . . . . .. . ... DTE/3-5 3.24 PDP-11 BR Dialogue . . . . . .. .. ... ... ... .. .... 3.2.5 Control State Timing Logic w . . . .. .. . .. — Three Non-Addressable Registers ) - Four Addressable Interface Registers e e S NET IRPN Nb—fi)—-t-li—‘b—-lh—i:-‘ ot SECTION 3 w Page 3.2.6 3.3 CONTROL SECTION ORGANIZATION Data Control Register Logic ... ... ....... e DTE/3-5 . . . . . . .. .. ... .. ..... DTE/3-5 . . . . . . .. .. ... ... .... DTE/3-6 . . . . . .. . .. ... ... ..... DTE/3-6 . . . . . . .. ... .. .. ... ..... DTE/3-6 . . . . . . . . ... .. . ... ... ..., DTE/3-6 . . . . . . ... .. ... ... ...... DTE/3-8 BASIC BUS TRANSACTIONS 3.3.1 PDP-11 RingsDoorbell 3.3.2 Interrupt Dialogue 3.3.3 KL10 Rings Doorbell 334 Interrupt Dialogue . . . . . . . . . .. .. ... ... ... DTE/3-12 3.35 Doorbell Summary . . . . . . . .. .. ... e DTE/3-13 34 INTERFACE STATUS . . . . . . . e e e DTE/3-13 . . . . . . .. ... .. DTE/3-13 34.1 General Information 3.4.2 STAT10TOIODONEandIBit 34.2.1 TO10 Byte Transfers 343 STAT11 TOII DONEandIBit 343.1 TO11 Byte Transfers 344 345 3.5 Status Error Conditions .. ... ... .......... DTE/3-17 . . . ... ... e DTE/3-18 ... ... ............ DTE/3-18 . . . ... ... ...... R DTE/3-21 . . . ... ... .. e e e e DTE/3-21 NULLStop . ............. e DTE/3-21 RAM OPERATIONS OVERVIEW . . . . ... ... .. e DTE/3-23 3.5.1 RAM Access and Control 3.5.2 Write Access Overview . . . . . . . . . . ..... L DTE/3-26 3.5.3 Read Access Overview . . . . . . . . . .. ... ... e e DTE/3-26 354 3.5.5 3.6 3.6.1 3.6.2 3.7 3.8 3.8.1 3.8.2 3.8.3 APPENDIX A Write Access Timing . . . . . . . . .. .. DTE/3-23 . . . . . ....... R DTE/3-26 Read Access Timing . . . . . . . . . .. . . DTE/3-26 INTERFACE TIMING ANDCONTROL . .. ... ... ....... DTE/3-29 Clock and Major State Control . . . . ... .. ... ... .... DTE/3-29 Minor State Control and Inhibit Clock . . . . . . ... ... ... DTE/3-30 CONTROL STATE TRANSFERPDP-11 . . . . . . .. .. ... ... DTE/3-30 DTE DIAGNOSTIC MODE OPERATION . . . . .. .. ... ... .. DTE/3-33 Diagnosing the 10-11 Interface . . . . ... ... ... .. .... DTE/3-33 Diagnostic ControlLogic . . .. ..................DTE/336 Diagnostic Programming Synopsis ABBREVIATIONS AND MNEMONICS iv . . . . . . . . .. ... ... DTE/3-37 ILLUSTRATIONS Figure No. ek APl Word Format Page . . . . . .. .. .. ... ... .. DTE/1-2 . . . .. . ... ... ... . ... ... DTE/14 Examine Overview . . . . . . . . . . . . . DTE/1-6 . . ... ..... DTE/1-7 TO11 Byte Transfer Overview . . . . . . .. . .. ... ... ..... DTE/1-8 Diagnostic Overview . . . . . . .. ek bd bk d BR Sequence . . Load DLY Count DTE/1-11 DTE/1-13 .. ... DTE/1-15 . . . . . . . . . ... .. ... ... DTE/1-37 Ring KL10 Doorbell CONI Simplified .. .. . . . . . . . .. . ... ... ... ..... . . . . . . . .. ... . ... ... ... ..... . . . . . . ... . ... ... . . DTE/1-38 . . . . . ... . ... ... .. DTE/1-39 . . . . . . . .. ... . .. DTE/2-2 DTE Simplified Functional Block Diagram Simplified Control Block Diagram Deposit Simplified Functional Block Diagram . . . . . .. . ... .. .... ... . . . .. .. .. ... .. . . . . . . . .. Address Word Setup Deposit and Examine Words . . . . . . ... .. .. ... Simplified Flow Diagram RO Interrupt Dialogue Overview R . . . . . ... .. ... ... Deposit Data Word Setup B AJ RI N CONO Simplified Deposit Operation Including Address Setup 2-10 Examine Simplified Functional Block Diagram 2-11 Loading the E-Buffer (Examine) .. ... .. DTE/2-9 DTE/2-10 DTE/2-11 . . . . . . . .. .. ... ........ . . . Examine Operation Including Address Setup Simplified Flow Examine 2-14 E-Buffer Loaded fromthe EBus 2-15 TO11 ByteMode . . . . . ... .. ... ... . . . .. .. .. .. .. . . . . . .. .. .. 2-13 . . . . . DTE/2-3 DTE/2-7 DTE/2-8 ........ . . . . . . .. .. ... ... 2-12 2-16 DTE/1-37 . RO b . . . . . Master/Slave Relationship . . . . .. ... ... 8D 1O WM - ] PDP-11 Rings KL10 Doorbell et b b DTE/1-5 b . .. .. . ... . . . . . ... Deposit Overview et ek | ] |I ] 1 LI | [} t Oduaddhh ELL Ll obLbhhLs L Overview Communications Region b Title .. ... ... . . . . .. .. .. .. DTE/2-12 DTE/2-13 DTE/2-14 DTE/2-15 .. DTE/2-15 . ... ... ... ... ... .... DTE/2-16 . . . . DTE/2-18 .. . ... ... ....... . . . ... .. ... .. . .. ... DTE/2-20 TOI11 Transfer Simplified Functional Block Diagram . . . . . .. . . . DTE/2-21 2-17 TO11 Transfer Words 2-18 TOIl Transfer . . . . . . . . . . . .. .. . ... ... .... DTE/2-22 . . . . . .. .. ... .. .... DTE/2-24 DTE/2-25 . . ... ... .. ... .. ... DTE/2-27 . . . . . . . . .. . . 2-19 Simplified Flow TO11 Transfer 2-20 TOI0ByteMode 2-21 TO10 Transfer Simplified Functional Block Diagram 2-22 TO10 Transfer Words 2-23 TOIO Transfer 2-24 Simplified Flow TO10 Transfer .. .. .. 3-1 DTE20 Data and Address Paths Block Diagram . 32 Detailed Control Block Diagram 3-3 APl Word Format Vector Interrupt 34 EBox Interrupt Dialogue . 3-5 EBus and E-BufferMixers . . . . 3-6 KL10 Instruction Dialogue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTE/2-30 ... ... ...... DTE/2-31 DTE/2-32 . . . . . . . . DTE/2-29 . . . .. . ... .. ... ... . . . . . . .. . . . . . . . ... .. . . . . .. ... .. .. DTE/3-2 .... DTE/3-3 ...... DTE/3-11 DTE/3-13 ... DTE/3-14 . . . . ... .. DTE/3-8 . . . Bus Request . . . .. . ... ... ... ....... CONO Interface Bit Assignments . . . DTE/3-9 3-8 . . . . . . . . . . ... .. 3-7 . . . . . . . . . .. ... ... . . . . . ... .. ... ....... DTE/3-16 ILLUSTRATIONS (Cont) Title Figure No. Page 39 CONI Interface Bit Assignments 3-10 PDP-11 Status Word — DATI Configuration 3-11 PDP-11 Status Word — DATO Configuration 3-12 RAM Words and Registers 3-13 Hardware-Generated 10 Interrupts Simplified . . . . . . . . .. ... ... ....... . . . . . DTE/3-16 . . . ... ... ... ... DTE/3-16 .. . . . .. . ... ... . ... ... ... ... DTE/3-16 .... DTE/3-17 . . . . . . ... .. ... DTE/3-18 3-14 TO10 Byte Transfer Flow Diagram .... DTE/3-19 3-15 Program Generation and Clearing of 10 Interrupts Simplified . . . . . . DTE/3-20 3-16 Hardware-Generated 11 Interrupts Simplified . . .. .. DTE/3-20 3-17 TO11 Byte Transfer Flow Diagram .. ... ... ...... DTE/3-22 3-18 Program Generation and Clearing of 11 Interrupts Simplified . . . . . . ... ... ... . . . . . 3-19 Interface Address and Access Control Simplified 3-20 DATO to RAM Location 1 Timing 3-21 DATI to RAM Location 1 Timing 3-22 . .. .. . . .. . . . . DTE/3-24 ... ... ... .. DTE/3-25 ... ... ... ...... DTE/3-27 .. .. ... ........ DTE/3-28 Free Running and GatedClocks . . . . . . . . ... ... ....... DTE/3-29 3-23 Major State Sequencing . . DTE/3-30 3-24 Basic Clock and State Control Simplified . ... ... ... ... ... DTE/3-31 3-25 BasicClock Timing . . ... .. ... ...... DTE/3-32 3-26 NPR Sequence 3-27 Simplified Diagnostic Functional Diagram 3-28 DTE/Diagnostic Bus OperationFlow . . . . . . . . . . . . . . . . . . . ... oo . . . . . . . . . . . . . . . . . . . . e . . . . e DTE/3-34 . .. .. ... ... DTE/3-35 . . . . .. ... ... ...... DTE/3-38 TABLES Title Table No. 1-1 Data Transfer Signals 1-2 Data Transfer Operations 1-3 Data Transfer Signals 14 Data Transfer Commands 1-5 Priority Transfer Signals 1-6 Priority Transfer Commands 1-7 PDP-11 Device Registers 1-8 Addressable Register Summary Page . . . . . . . . .. .. ... ... ... ..... . . . . . . . . . ... .. .. ........ DTE/1-14 DTE/1-16 . . . . . . . . ... . . ... .. .. ...... DTE/1-18 . . . . . . .. . . . . . .. ... ..... DTE/1-18 . . . . . . ... ... ... ... ....... DTE/1-19 . . . . .. .. ... ... ........ . . . . . . . . . . . . . ... ... ...... . . . . .. .. ... ... ... .... DTE/1-19 DTE/1-20 DTE/1-21 1-9 Deposit or Examine Word Formats . . . . .. . ...... ... ... DTE/1-22 1-10 TO10 Transfer Word Format . . . TO11 Transfer Word Format . . . DATAO DTE Function . . . . . . CONIDTE Functions . . . . . . . CONO DTE Bit Function . . . . . DATO DTE Status Function . . . . . . . . . 1-11 1-12 1-13 1-14 1-15 . . . v . . .. ... . . . . . . . . . v v i e e ... .. . . . . . ... ......... DTE/1-23 . . . . . ... .... DTE/1-24 v ... DTE/1-25 s e e e o it DTE/1-26 ... ... .... DTE/1-27 . v v v v i v . DTE/1-28 1-17 DATI DTE Status Function . . . . . . ... ... ........... DTE/1-29 DATI/DATO DTEDIAGWord 1 . . . . . ... ... ... ...... DTE/1-30 1-18 DATI/DATODIAGWord 2 1-19 DATI/DATODIAGWord 3 1-16 . . . . . . . .. . . . .. .. DTE/1-32 . . . . . . . . . ... . .. ........ DTE/1-33 vi TABLES (Cont) Table No. Title 3-1 Typical Doorbell Sequence Abbreviated 32 Vector Addresses Page . . . . . . ... .. ... ... 33 . . . . . . . ... Generalized RAM Storage . . . . . .. . ... ... ... 34 RAM Cycle Functions 3-5 Select Lines and Data Control . . . . . . . . .. . ... ... ... ...... . . . . . .. . . . ... ... ...... vii DTE/3-7 DTE/3-12 ...... DTE/3-23 DTE/3-24 DTE/3-24 PREFACE This manual contains three levels of DTE theory descriptions. The three levels are: Overview — The overview introduces and identifies, in a simplified fashion, the basic hardware organization of the DTE Console Processor Interface. The major elements are present- ed without extensive details in order to provide a capsule view of the DTE structure. Functional Description - This section describes the primary DTE function, which is to interface “front end”” PDP-11 processors to the KL10 Central Processor. In such a system, several front end functions are thus provided, some of which are: fee o 1. Handling unit record equipment Handling communications equipment Diagnosing the KL10 Central Processor Bootstrapping the KL10 system. In addition to front end functions, the DTE features other capabilities. Some of these capabilities are: a. Examine and Deposit console functions b. Doorbell function, where the PDP-11 can interrupt the KL10 and vice versa c. High speed simultaneous two-way variable byte data transfer between the PDP-11 and KL 10 memory. The functional description is the most comprehensive part of the DTE theory. Here, the basic elements of the DTE are described in the context of how they implement the primary DTE operations, Logic Description - This section provides a detailed logic description of the DTE. The text is written to support the functional description. The logic description section is the most detailed part of the manual. This material is presented to expand the functional description so that the information provided in the functional description may be directly related to the engineering logic diagrams. SECTION 1 OVERVIEW Nk = 1.1 INTRODUCTION Each central processor in a KL10 system may have from one to four PDP-11 processors attached, each serving as a “front end” processor. Each PDP-11 is connected to the KL10 by a separate interface called the DTE20 Console Processor Interface, or simply the 10-11 Interface. The following are some of the possible front end functions: Handling unit record equipment Handling asynchronous communications equipment Handling synchronous communications equipment Providing a long term power line frequency clock Diagnosing the KL10 Central Processor and other functional components in the system Running a dedicated real-time data acquisition system Bootstrapping the KL10 system. In terms of basic features, the DTE20 generates parity for Deposit data and detects parity errors for both Examine data and byte transfers over the EBus. The DTE20 connects to the PDP-11 as a standard Unibus peripheral and communicates via interrupt or device address. Up to four DTE20s may be connected to a PDP-11. In a system consisting of four KL 10 Central Processors, there may be four PDP-11/40 processors, where each processor can communicate with all KL10s in the system. It is possible to have up to four DTE20s on each PDP-11 in the KL10 system, and each KL 10 processor may have 1, 2, 3, or 4 DTE20s connected to it via the EBus. The DTE20 uses the NPR (Direct Memory Access) and BR (Vector Interrupt) features of the PDP-11. In addition, the DTE20 contains logic to detect PDP-11 core memory parity errors during NPR transfers, provided that the memory being accessed contains the parity option (MFU11 UP). The DTE20 provides the following capabilities: 1. 2. Console functions at Examine and Deposit, restricted or unrestricted. Doorbell function, where the PDP-11 can interrupt the KL10 Central Processor and vice versa. 3. High speed simultaneous two-way transfer of variable byte data between the PDP-11 and KL10 memory. 4. 5. Diagnostic bus for the PDP-11 to diagnose the KL10. KLI10-initiated bootstrap startup of the PDP-11 mechanism (diagnostic bus) to load the microcode into the CRAM, execute PDP-10 instructions, and start or stop the KL10 Central Processor. DTE/I-1 The following terminology will give some perspective on the front end and its relationship to the DTE20. PDP-11 Communication Region - This region consists of an area of KL10 core memory defined by the deposit relocation and protection word in the Executive Process Table (EPT). This area is written by the PDP-11 using protected deposits, and read by the KL10. It is used for coordination of status, preparing for byte transfer operations, and passing limited amounts of data. Each PDP-11 in the system has a separate communication region in the KL10 memory, which it alone can modify. KL 10 Communication Region - This region is defined solely by the KL 10 software and is separate from the PDP-11 communication region. It can be written by the KL10, but may be read by the PDP-11 using protected Examines. This area is used to coordinate status, prepare byte transfer operations, and pass limited amounts of data (Figure 1-1). rlj ;I;‘ b "— KL-10 MEMORY —’I I-— PDP.11 MEMORY —.I ~ TO11 BYTE POINTER 140+8n ~ I TO10 BYTE POINTER KL10 FRONT END mea:h:‘::mnun SOFTWARE COMMUNICATIONS REGION RESERVED READ ONLY / 7 Y PDP-11 READS FROM PDP-11 THIS AREA BUT IS PREVENTED FROM WRITING INTO IT. oTe0 EXAM PROTECTION WORD BASE ADDRESS OF THIS AREA ~ // DEPOSIT PROTECTION WORD 7 DEPOSIT RELOCATION WORD 7] G of A N POP-11 POP-11 WRITES REGION ANY MAY ALSO COMMUNICATIONS INTO THIS AREA A AND Z 8 WORDS IDTE 1) N READ FROM IT. READ 8WORDS WRITE (DTE 3) P)I SERVICE ROUTINE 7 Figure 1-1 / EXAM RELOCATION WORD Overview Communications Region DTE/1-2 / / / v / 14748n l/ A Restricted Front End - A restricted front end is a PDP-11 system with a DTE20 that does not have diagnostic privileges. A restricted front end is prevented from using the diagnostic bus. A restricted front end can only access KL10 memory after the KL10 has performed a CONO (Conditions Out) to allow use of DTE PI0. After this has been done, the restricted front end can only examine or transfer bytes from the KL10 communication region and only deposit or transfer bytes to its own PDP-11 communication region. Privileged Front End - A privileged front end is a PDP-11 the diagnostic bus and perform unrestricted Deposits. attached to a KL 10 via a DTE20 that can use Protected Examine or Deposit - A protected Examine or Deposit is an Examine or Deposit that is relocated and range checked by the KL10. The relocation and protection for Examine is separate from that of Deposit. A privileged front end can override the Examine and Deposit protection checks. A restricted front end cannot override these checks. For addressing purposes, each controller is permanently assigned a unique device, or Controller Select (CS) code. A total of four Controlier Select codes has been assigned because up to four controllers (interfaces) can be implemented in a KL10 system. Each interface is also assigned a physical number according to the physical slots in which the interface module will reside. These are indicated below. Both of these are hard-wired on the KL10 backplane. The specific Controller Select (CS) codes and physical number (n) assignments are as follows: Interface Controller Select (CS) CodeS | Physical Number n,oyk 0 200 8 | 204 9 2 3 210 214 11 0 The device code is used to address the interface and the physical number is used to identify the inter- rupting interface. Eight locations are assigned to each DTE20 in the KL10 Executive Process Table as follows: Location . Name 140 + 8*n To 11 Byte Pointer 141 + 8*n To 10 Byte Pointer DTE20 Interrupt Instruction 142 + 8*n 143 + 8*n Reserved for DEC Hardware 144 + 8*n 145 + 8*n Examine Protect Word Examine Relocation Word 146 + 8*n Deposit Protect Word 147 + 8*n NOTE:n=0,1,20r3 Deposit Relocation Word Figure 1-2, API Word Formai, illustrates the basic‘format 6f this word. The DTE2O alldws the soft- ware to set the following fields of this 36-bit word: Address Space Field 0-2 Unused bits 11-12 Address Field 13-35. DTE/1-3 00 02 03 05 ADDRESS | spacg 06 . | FUNCTION | Q { H I ! i ‘ ADDRESS SPACE (AS SPECIFIED BELOW) ¢] EPT . PaveicaL 2,3,5-7 |UNDEFINED I LATEST MICRO CODE VIRTUAL ADDRESS QUALIFIER {AS SPECIFIED BELOW) o A CODE DEFINITION STANDARD INTERRUPT FUNCTION QBIT CODE INTERPRETATION 01,27 vecrornterroer| | | INCREMENT DATAO (EXAMINE) IGNORED 1=SUBTRACT * +1 4,5 1= APPLY PROTECTION 6 1=TO10BYTE TRANSFER AND RELOCATION DATAI (DEPOSIT) BYTE TRANSFER RESERVED FOR DEC LISTING FOR POSSIBLE 00 By PISYSTEM FUNCTICN (AS SPECIFIED BELOW!} * THESE BITS ARE MICRO CODE-DEPENDENT. 35 | FUNCTION DEFINITION 1213 ASSERTED NSO B WN = O CODE 1 CONTROLLER i | CODE ! 10 PHYSICAL i | ! ADR. 07 |T | 0=TO11 BYTE TRANSFER CHECK THE 10-1941 CHANGES.‘ Figure 1-2 API Word Format The Priority Interrupt (PI) board in the EBox supplies the physical controller number field [7-10]. The DTE20 asserts Qualifier (Q) bit 6, for all Examines and Deposits by a restricted front end, whether protected or not. The DTE20 asserts Qualifier for all protected Examines and Deposits by a privileged front end and does not assert it if the privileged front end makes an unprotected Examine or Deposit. 1.2 BASIC PROGRAMMING OVERVIEW To specify a 36-bit PDP-10 data word, three PDP-11 words are used. They are Deposit/Examine Data Word I, Deposit/Examine Data Word 2, and Deposit/Examine Data Word 3. To specify a 23-bit PDP-10 address, two PDP-11 words are used. They are Ten Address Word 1 and Ten Address Word 2. The high order part of Ten Address Word 1 is used for control. Ten Address Word | specifies whether an Examine or Deposit is to be done. For a privileged front end, the protect off bit in the Ten Address Word 1 can be set by the software to allow an unprotected Examine or Deposit. On unprotected operations, the space field specifies the type of address: Executive Process Table (EPT), Exec Virtual, or Physical Address, which may refer to core memory or ACs. The Examine or Deposit function is started when the PDP-11 program writes the Ten Address Word. No program interrupts are generated on the KL10 or the PDP-11 side to signal completion of the Examine or Deposit. Therefore, the PDP-11 program must check for completion by looking at the status DEXDONE bit. The DTE20 clears DEXDONE when the PDP-11 writes Ten Address Word 2, so the software never needs to. Data in TENAD1, TENAD2, DEXWDI1, DEXWD2, DEXWD3 remain intact after an operation. Therefore, the PDP-11 may perform repeated protected Examines or Deposits merely by writing the TENAD?2 word each time. An Examine followed by a Deposit (changing only TENADI! and TENAD?2) will result in moving data from one KL 10 core location to another. For unprotected operations, the PDP-11 must reload the protect off bit (PRTOFF) between each operation (Figures 1-3 and 1-4). DTE/1-4 ADR WORD 2 KL-10 WORD 1 UNIBUS : ADR o EBUS "SOQURCE ADR PDP -11 10/1 OF UNIBUS INTERFACE DATA" DATA "DESTINATION OF DATA DATA SOURCE OF WORD 1 DATA WORD 2 DATA WCRD 3 15 1312 ADDRESS SPACE M 1 PO 06 00 15 00 KL1O ADR 13 -19 FF KL10 ADDRESS ADR WORD 2 ADR WORD1 03 | 00 NOTE: KL10 DATA M- MODE BITS 0-3 DATA WORD 20- 35 M(1) 1 - DEPOSIT M(O)- EXAMINE POFF- PROTECTION OFF POFF (1) - PROTECTION AND KL10 DATA BITS RELOCATION 4-19 NOT IN EFFECT POFF(0) - PROTECTION AND DATA WORD 2 KL10 DATA RELOCATION IN EFFECT BITS 20- 35 DATA WORD 3 10-1787 Figure 1-3 ‘Examine Overview DTE/1-5 UNIBUS ADR PDP-11 SOURCE OF ADR" <.—DLA—> IADR WORD ¢ l I DATA WORD 1 | KL10 I I ADR WORD 2 | INATI N ON 10/11 INTERFACE <—_:> “DESTbara” EBUS UNIBUS " souac§£g DATA I DATA WORD2 I DATA WORD 3 I 10-1788 Figure 1-4 Deposit Overview 1.3 DOORBELL FUNCTION ‘ ‘ The doorbell function allows each KL10 to interrupt each PDP-11 connected by a DTE20 and vice versa. The doorbell consists of a programmable interrupt and a status bit. In order for the PDP-11 to interrupt the KL10, the PDP-11 sets the request 10 interrupt flip-flop (bit 08) in the PDP-11 status word. When this bit is set, the DTE20 generates an interrupt in the KL10 with a status bit set in the CONI word (bit 26) indicating that the PDP-11 CPU has programmed an interrupt of the KL 10 (Figure 1-5). This procedure works in a reversed but identical manner for the KL10 interrupting the PDP-11. The KL10 sets the 10 requesting 11 interrupt by doing a CONO to the DTE20. The PDP-11 discovers the cause for the interrupt by looking at bit TO10DB (bit 11) in status. Communication is done via a word (or words) in the communication region in KL10 memory. A word (or words) is chosen and Deposit and Examine features are used by the PDP-11 to gain access to these words (Figure 1-6). This mechanism is used by either processor to indicate to the other processor that it is powering down. For example, if the KL10 determines that its power is disappearing, it will set a bit in a word that is assigned for power failure notification. The KL10 then interrupts the PDP-11. The PDP-11, as part of its standard routine, will always check for the KL10 power fail bit in the communication region. In this way, the PDP-11 is notified that the KL10 power is disappearing. In a similar way the PDP-11 could interrupt the KL10 on every tick of the power line clock (50 or 60 Hz). DTE/1-6 > 10/11 w 2 INTERFACE v @ z =2 POP-11 Req Z "DATO DTE STATUS" BIT 08(1) |"seT" [10INT 146, +8,.n . DIALOG (( v EPT INT @ w PIN-7 |M > KL10 PII~7 . DIALOG <‘ > "FETCH v INTERRUPT INSTR." PI INSTR HANDLER "ENTER HANDLER" KL10 MEMORY - Figure 1-5 PDP-11 Rings KL10 Doorbell DTE/1-7 t0-1789 31A8 139 WYHOONd -4 3148 207v1a 3148 3148 1 8-8 139 Lot ,~ A"3navl- HOW3IN|WvY[|| |_ ! _ ! b ¥3d QHOM 16-2041 $5304d DTE/1-8 1AXsd 1.4 BYTE TRANSFER FUNCTION During the byte transfer function, the DTE20 transfers fields of information between the PDP-11 and the EBox. On the KL10 side, the fields are of variable length and are accessed through a PDP-10 byte pointer. On the PDP-11 side, the fields are either 8 bits wide and are stored in consecutive bytes or are 16 bits wide and are stored in consecutive words. If the field into which the information is being stored is narrower than the field from which it was read, as many of the rightmost bits as will fit are stored. If the field into which the information is being stored is wider than the field from which it was read, the information is right-aligned and padded with zeroes on the left. To perform a transfer, the following actions must be done: e The PDP-11 should specify the transfer rate (delay between transfers) and address bits 17-16 (this can be done once at system startup). If it is not specified, an undetermined transfer rate will occur to one of the four 32K memory regions. * The PDP-11 must specify whether byte or word mode is to be used in the PDP-11. ® The sender must specify the address of the source string. The KL10 controls the address of the data either to or from the KL10 via byte pointers in the EPT. The PDP-11 controls the address on its side via two locations in the DTE (one word for each direction of transfer). * The receiver must specify whether it alone (scatter write) or both CPUs are to receive normal termination interrupts (I bit = 1). Information in the form of bytes may be stored in the PDP-11 as either one variable sized byte per PDP-11 16-bit word (1 to 16 bits of data) or one variable sized byte per 8-bit PDP-11 byte (1 to 8 bits of data). Byte addresses are specified in the KL10 using regular KL10 byte pointers in the EPT. Byte pointers are interpreted in Exec Virtual Address space. CAUTION The index field of the byte pointers should be zero. Otherwise, the EBox will index using the current contents of the Executive or User Index register at the time of the transfer. Indirection should not be used because the indirect word will not be incremented as with all byte pointer operations. 1.5 ERROR OVERVIEW The DTE20 will generate/check parity on Deposit/Examine data (36 bits). It will not check or gener- ate parity for CONI, CONO, DATAO, or API words. The software will check for errors by examining the termination words. The parity scheme also imposes one restriction on the byte pointer used for TOI11 transfers. A byte size larger than 16 bits cannot be used unless the bits to the left of the rightmost 16 bits contain even parity. If a parity error occurs, the error termination bit status and the EBus parity error flag status will be set. If an Examine operation was in progress when a TO11 transfer operation has an error termination due to an EBus parity error, it is not possible for the software to determine if the Examine operation has a parity error. The EBus parity error is fatal, and is treated so by the Monitor. When a parity error occurs, the bad data is stored in the RAM and can be retrieved for error reporting. The DTE20 sometimes swaps the left and right bytes for byte mode prior to writing the bytes into the RAM. Therefore, the termination TO11 address word should be examined to determine if the left and right halves were swapped. If the termination address is even, the bytes were swapped. (This applies only to transfers in byte mode.) DTE/1-9 1.6 DIAGNOSTIC OVERVIEW The interface contains many features that enable diagnosing of the interface. It is designed to be diagnosed using three basic methods: 1. 2. 3. Without using or disturbing the EBus With loopback on the EBus but without the KL 10 or without the KL10 running With the KL 10 running. The interface is primarily checked out in a single-step manner. Full speed operation may only be checked with a running KL10; DIAG1 contains the Diagnose 10/11 Interface bit. When DIAG] is set, " the following occurs. The interface clock is disabled and single step operation commences. Interrupts are inhibited from being sent to the KL10. The interface operates in the normal manner except that EBus operations never complete because no interrupts are issued to the KL10. Therefore, a bit is provided that enables setting EBus Complete, allowing the operation to continue. The interface control is run by an up-counter and three decoders. The decoders are selected by the major state flip-flops. The up-counter is loadable by the rightmost four bits of DIAG Word 2. This enables any minor logic state to be executed. The major states are not loadable; however, they naturally cycle until a condition occurs that indicates the operation is ready to take place. These major state bits are readable. 1.6.1 Diagnosing the KL10 All KL10 diagnostic functions and console functions (except Deposit and Examine) are performed over the diagnostic portion of the EBus. This specification explains the operation of the diagnostic bus. The diagnostic bus contains the fdllowing ten signal lines: DS00-06 DIAG STROBE Diagnostic Select (DS) Lines - The PDP-11 sends encoded diagnostic functions to the KL10 on these lines. These lines can be read by the PDP-11 at any time, even while the rest of the EBus is active for other devices. Diagnostic Strobe - T’his line is asserted to indicate that the Diagnostic Select lines are stable, and that the indicated function should be performed. DFUNC Diagnostic Ffiunction - When true, this causes the KL10 to disable the (Actual basic CPU status from the DS lines, switch the translator (only for the Mnemonic is DS lines) to convert TTL to ECL, and put the EBus translator under Remove Status) control of DB bits 00 and 01. 1.6.1.1 Diagnostic Bus Control | Diagnostic CPU Status Read - All bits in DIAG Word 1 must be loaded with zeros. The CPU status may then be read from the DS lines after 1 us has been allowed for the lines to settle (Figure 1-7). Diagnostic Functions Only (i.e., no 36-bit transfers) - The desired function code bits should be set along with DIAG Command Start (DIAG1 PDCOMST) and Remove Status (DIAG1 [DFUNC])). This will result in the function being sent to the KL10. When DIAG Command Start is a zero, the function has been sent. All function bits must be loaded with the desired value each time a new command is sent. The DIAG Send bit has no effect upon this operation. DIAG KL 10 must not be set or a 36-bit data transfer will take place. This operation should not take more than 2.0 us. DTE/1-10 1. LOAD DIAG REGISTER O] WITH FUNCTION “TELLS EBOX TO REMOVE STATUS FROM EBUS" | "128,, FUNCTIONS POSSIBLE" I A S I I 0 EBOX S T /I DS00-06 ~ /771" % | sratus | | DIAG WORD 1 N EOM START 1 S ¢ | l U DATO, DTE, DIAG REMOVE PDP -1 PROCESSOR | s B DIAG g CLEARED s DIAG STROBE REGISTER IS WHEN THE FUNC IS TRANSMITTED DIAGNOSTIC | CONTROL i —1 A% L _ —— 1 [z rerrorm ERFORM DIAGNOSTIC oiacnoSTIC DEPOSIT (EFFECTIVELY LOAD LonD AR} AR DEPOSIT (EFFECTIVELY l £ I B I /} I A G D EBOX LOAD . EBUFFER ] || ApR woRD 2 1 SHIFT | S DEX @ CLOCK AND START b TIME STATE DEPOSIT | onTROL DEX MINOR T . E B s | P100 1S INHIBITED l DTE e — — — — | TRANSFER Ve l EBUF CLK INH DIAG KL10 (1) I DEPOSIT 1S DONE DEXON V DIAG KL1O DIAG REGISTER iS NOT CLEARED AFTER FUNCTION U SET| SET TO TELL PDP-11 CLK INH I | I DONE |— STATES CONTROL EBUFFER I | . (WRITTEN VIA DATO'S TO DTE BY PDP-11) pfCATAWORD! |/ 0ADING ADR WORD 2 STARTS THE DEPOSIT LOAD AND T l ADR WORD 1 @ EBUFFER CLK 9 | DATA WORD 2 @) BUBCIJET N I DATA WORD 3 EBUFFER | I ] RAM l s 1 STATUS REGISTER l "DATO DTE DIAG WORD 1", O) @ INHIBIT PIOO u N I e CONTROL S ® FROM PDP-14 l PROCESSOR NOTE: 4 Loading ADR1 is not necessary but 6 PDP-11 samples state, to determine loading ADR2 1s required to begin when deposit is done; then may issue the deposit operation diagnostic function “LOADAR"" causing EBOX to read the DATA 5 The clock and time state control trom the EBUFFER into the AR, loads and shifts DATAWORD 1, 2 and 3 See 1 into the EBUFFER which effectively discards ADR words 2 and 1 Figure 1-7 Diagnostic Overview DTE/1-11 10-1792 l 1.6.1.2 Diagnostic Functions with 36-Bit Data Transfer Sending Data to the KL10 — No other operations (i.e., byte string transfers) may be in progress while doing 36-bit diagnostic data transfers. The data should be loaded into DEX WD1-3 (same bit assign- ments as with a Deposit or Examine). DIAG KL10 should then be set and a Deposit operation should be started. When the transfer is complete (DEXDON SET), the diagnostic function should be loaded as described above, the DIAG KL10, DIAG Send, DIAG Command Start, and DIAG Function set, The operation is complete when DIAG Command Start is on a zero. Receiving Data From the KL10 - The diagnostic function should be loaded with DIAG KL10 set, DFUNC set (Remove Status), DIAG Send clear, and DIAG Command Start set. When DIAG Command Start is clear, the function is complete and the data is in DEX WD1-3. No other operations (i.e., byte string transfers) may be in progress during this operation. All the KL10 diagnostic functions are disabled when the privileged restricted mode switch is set to restricted mode. This bit can be tested by Reading Status (RM). When the switch is set to restricted mode, status (RM) is set (i.e., the device is restricted and cannot send diagnostic functions). 1.7 INTERFACE COMMUNICATION ‘ ; The DTE20 can communicate directly with three devices in the system: 1. 2. 3. EBox via EBus PDP-11 processor via Unibus PDP-11 memory via Unibus. This communication, when over the Unibus, is in a master-slave relationship (Figure 1-8). During any bus transfer, either the DTE20, the PDP-11 processor, or the PDP-11 memory has control of the bus. The controlling device is considered the bus master, and the device being controlled is considered the slave. Also, communication on the Unibus is interlocked between the DTE20 and either the PDP-11 processor or the memory. Each control signal issued by the master device must be acknowledged by a similar response from the slave device. Thus, communication is independent of bus length and of the response time between the master and the slave. When the DTE20 requests the bus, the handling of the request depends on the location of the interface in a priority structure. The following factors must be considered to determine the priority of the request: 1. The processor’s priority is set under program control to one of eight levels using bits 7, 6, 2. Bus requests from external devices, i.e., DTE20 can be made on any one of five request lines. A non-processor request (NPR) has the highest priority and its request is granted by the processor between bus cycles of an instruction execution. 3. When more than one device is connected to the same bus request line, the one that is elec- and 5 in the processor’s Status register. These three bits set a priority level that inhibits granting bus requests (BR) on the same or lower levels. trically closest to the PDP-11 processor has the higher priority. DTE/1-12 BUSY BUS |, NPR ~— NPG -0} MASTER BUS SLAVE SACK (DTE 20) —_— (POP-11 MEMORY} BUSY f—— BR(7:4) BUS MASTER (PDP-11 867:4) 7:4) —————» P— PROCESSOR) SACK BUS SLAVE (DTE 20} INTR 10-1793 Figure 1-8 Master/Slave Relationship 1.7.1 Data Transfer Direct memory access data transfers can be carried out by the DTE20 and memory without supervision. processor This type of transfer is called NPR level data transfer. Normally, NPR transfers are only made between memory and controllers. During NPR transfers, it is not necessary for the PDP-11 processor to transfer the information between the memory and DTE20. The bus structure is such as to enable device-to-device transfers. This allows special controllers to access other devices on the bus as well as memory. The DTE20 can transfer data at high rates once it gains control of the bus. In addition, the processor’s internal state is not affected by this type of transfer. Therefore, the processor can release the bus while an instruction is in progress. The DTE20 can transfer 16-bit or 8-bit bytes to memory at the same speed as the memory cycle time. 1.7.2 Interrupt Requests Once the DTE20 has gained control of the bus, it can take full advantage of the power and flexibility of the processor by requesting an interrupt. Note that interrupt requests can be made only if bus control has been gained through a BR priority level. An NPR level request cannot be used for an interrupt request. DTE/1-13 1.7.2.1 Processor Interrupt Procedure — Assume that the DTE20 is responding to a CONO from the EBox and this CONO is activating the doorbell feature for interprocessor communication. The DTE20 must then interrupt the PDP-11 to inform it that the EBox wishes to communicate. Refer to Figure 19. The following takes place: 1. Priorities permitting, the processor relinquishes bus control to the DTE20. 2. When the DTE20 gains control of the bus, it sends the PDP-11 processor an interrupt command and the starting address of the device service routine. This is called the Interrupt Vector Address. Immediately following this address is a word to be used as the new processor status (PS) word. 1.7.3 3. The processor pushes the current processor status word and then the program counter (PC) value onto the processor stack. The stack is pointed to by register 6. 4. The new PC and PS (the interrupt vector) are taken from the address specified by the DTE20 5. The service routine can cause the processor to resume the interrupted process by executing and the service routine is initiated. the return from interrupt (RTI) instruction, which pops the two top words from the processor stack and transfers them back to the PC and PS registers. Unibus Signal Lines The PDP-11 Unibus comprises 56 lines. All devices including the processor are connected to these lines in parallel. The bidirectional nature of 51 signal lines permits signals to flow in both directions. The remaining five lines are used for priority bus control. Table 1-1 lists the data transfer signals. Table 1-1 Data Transfer Signals Name Mnemonic No. of Lines Data D (15:00) 16 Address A (17:00) 18 Control Co, C1 2 Master Sync MSYN 1 Slave Sync SSYN 1 Parity PA,PB 2 Interrupt INTR 1 Total: DTE/1-14 41 VECTOR NEW PC BASE PROGRAM RUNNING IN PDP-11 MEMORY / INTERRUPT SERVICE NEW STATUS ROUTINE |_— - b PUSH 1 ] oLD pPC OLD STATUS PROCESSOR STACK |— P p—— ~ - .. PoP > DTE 20 BR ASSERTS BRp, ARBITRATES REQUEST Be DTE 20 RECEIVES BG SENDS PDP-11 PROCESSOR 5. DS SACK PDP-11 y Zzgggsson SACK _Basy DTE 20 ASSERTS BBSY BECOMES MASTER BBSY GRANT PDP-11 l PR y NEOCESSOR GATES BUSY BECOMES SLAVE INTR ADDR VECTOR PDP-11 SLAVE ACCEPTS VECTOR - BBSY DTE 20 POP-11 PROCESSOR NEGATES BUSY ASSERTS BUSY BECOMES SLAVE BBSY BECOMES MASTER EXECUTES INTR SEQUENCE 10-1794 Figure 1-9 BR Sequence DTE/1-15 Data Lines D(15:00) - The 16 data lines are used to transfer information between the DTE20 and either the PDP-11 processor or PDP-11 memory. The most significant bit is bit 15, the least significant is bit 00. Address Lines A(17:00) - The 18 address lines are used by the DTE20 to select the PDP-11 memory address used in the current data transfer. The reason for 18 address lines is to extend the total memory capability to 262,144 bytes. The extension bits are bits 17 and 16. The normal most significant bit is bit 15; the least significant bit is bit 00. Lines A(17:01) specify a unique 16-bit word. In byte operations, A0O specifies the byte being referenced. If a word is referenced as ADR (ADR must be even, because words can be addressed only on even boundaries), the low order byte can be referenced at ADR and the high order byte at ADR+1. Only 16 bits are supplied by programs as memory references. In the processor, lines A17 and A16 are asserted (forced to 1) whenever the program attempts to reference an address between 160000 and 177777. Thus, the processor converts the 16-bit to a full 18-bit address. Control Signals - The control signals are divided into three groups: signals that select data transfer operations, signals that allow the master and slave device to communicate, and signals used for parity checking. . Control Lines C(1:0) - These two bus signals are coded by the DTE20 as well as the PDP-11 processor to control the memory in one of four possible data transfer operations shown in Table 1-2. Table 1-2 Data Transfer Operations Cl1 co 0 0 DATI -- data in 0 1 DATIP -- data in pause 1 0 DATO -- data out 1 1 DATOB -- data out byte Operation 2. Master and Slave Synchronization - Master Synchronization (MSYN) is a control signal used by the master device to indicate to the slave device that address and control information is present. Slave Synchronization (SSYN) is the slave device response to the master. 3. Parity Error Indicators - The PA and PB are used to indicate that a memory parity error occurred on a memory read. The DTE sets the DPS5 MEM PAR ERR flag when a memory parity error is indicated during an NPR transfer initiated by the DTE. DTE/1-16 Interrupt (INTR) - This signal is asserted by the DTE20 to start a priority interrupt in the processor. 1.7.3.1 Priority Transfer Lines - The Unibus contains 12 lines classified as priority transfer lines. Four of these are priority bus request lines BR(7:4) and four are the corresponding grant lines BG(7:4); NPG, NPR, SACK, and BBSY complement the priority transfer lines. Each device of the same priority level passes a grant signal to the next device on the line, unless it has requested bus control; in this case, the requesting device blocks the signal from the following devices and assumes bus control. These 12 lines are described as follows: 1. 2. Bus Request Lines BR(7:4) - These four bus signals are used by the DTE20 to request contro: of the bus. Bus Grant BG(7:4) - These signals are the processor’s response to a bus request. They are asserted only at the end of instruction execution, and in accordance with the priority determination. 3. Non-Processor Request (NPR) - This signal is the bus‘ request from the DTE20 to the PDP- 4. Non-Processor Grant (NPG) - This signal is the processor’s response to an NPR. 5. 11 processor for a DMA-type bus cycle. Selection Acknowledge (SACK) - This signal is asserted by the DTE20 after receiving Bus Grant (BG). Bus control passes to the DTE20 as soon as the current bus master has com- pleted its operation. If SACK is not received by the processor within 28 us of issuing BG, a timeout occurs and the Bus Grant is cleared automatically by the processor. 6. Bus Busy (BBSY) - This signal is asserted by the master, either the DTE20 or PDP-11 processor, to indicate that the bus is being used. 1.7.3.2 Miscellaneous Control Lines Initialization (INIT) - This signal is asserted by the processor when the START key on the console is pressed, when a RESET instruction is executed, or when a power failure sequence occurs. In the later case, INIT is asserted following the power fail service routine while power is going down, and again when power comes up. 1.7.4 EBus Signal Lines ‘ The EBus consists of 60 signal lines. All devices, including the KL10, are connected to these lines in parallel. The bidirectional nature of 36 of the signals permits some information to flow in both directions. These are the data lines. The remaining 24 signal lines are used for control functions. Table 1-3 lists the signals necessary to effect a data transfer. Data Lines D(00:35) - The 36 data lines are used to transfer information between the EBox and the DTE20. The most significant bit is bit 00, the least significant bit is bit 35. Controller Select Lines CS(00:06) - These seven lines are used to select the desired controller for a data transfer. Each controller has a unique select code that is hard-wired on the backplane of the device. DTE/1-17 Table 1-3 Data Transfer Signals Mnemonic Name No.‘ of Lines_ Data D (00:35) 36 Controller Sel CS (00:06) 7 Function F (00:02) 3 Demand DEM 1 Acknowledge ACK 1 Transfer XFER 1 Function Lines F(00:02) - The function lines specify the type of data transfer or non-data transfer that is to take place. Table 1-4 lists the four implemented functions. Table 1-4 Data Transfer Commands F00 FO1 F02 Operation 0 0 0 CONO 0 0 1 CONI 0 1 0 DATAO 0 1 1 DATALI DEMAND (DEM) - This signal line causes the addressed controller to sample the CS lines and the F lines and to decode their meaning. Upon implementing the specified function, TRANSFER and ACKNOWLEDGE are asserted as a response, along with data being placed onto or taken from the EBus as specified by the decoded function. ACKNOWLEDGE (ACK) - This signal line is necessary to tell the DIA20 I/O Bus Adapter not to respond to the current operation. If the DIA20 does not see ACKNOWLEDGE some period of time after DEMAND is asserted, it will try to perform the transfer. It does not decode the CS lines, as do the standard KL 10 devices. TRANSFER (XFER) - This line is asserted by the selected controller when it is ready to execute the specified function as decoded in F(00:02). 1.7.4.1 Priority Transfer Lines - To perform priority interrupts between the KL 10 and its devices, the same basic set of signals is used in a slightly modified form. Table 1-5 lists the necessary signals. DTE/1-18 Table 1-5 Priority Transfer Signals Name Mnemonic Controller Sel CS (04:06) 3 Controller Sel CS (00:03) 4 Function F (00:02) 3 Demand DEM 1 Acknowledge ACK 1 Transfer XFER 1 No. of Signals Controller Select CS(04:06) - During interrupt arbitration, these three lines represent the octal encode of the interrupting channel. The range is 0 through 7. Controller Select CS(00:03) - These four lines specify the controller or device that the EBox will honor during this interrupt sequence. This is, of course, only a single device or controller, even though several may be interrupting on the same channel. This code will also correspond to the hard-wired physical device number of the appropriate controller or device. Function F(00:02) - Two functions are generated during the interrupt dialogue; refer to Table 1-6. The first is a code of 4 in F(00:02). It specifies to the interrupting controllers that those being addressed by channel number in CS(04:06) should send their physical controlier number by placing them onto the EBus upon sensing DEMAND. The second function is a code of 5 in F(00:02). It specifies to the interrupting controliers or devices that one has been selected. The selected one will see CS(00:03) as the same number as its physical controller number. Table 1-6 Priority Transfer Commands F00 FO1 F02 1 0 0 PI SERVED 1 0 1 PI ADDRESS IN Operation ACKNOWLEDGE (ACK) - Same as for data transfers. TRANSFER (XFER) - In the case of interrupts, the device selected for service by the EBox will place a special function on the EBus data lines D(00:35). Refer to Figure 1-2, API Word Format. The vector interrupt locations for the PDP-11 are as follows: 774, 770, 764, 760 for the first, second, third, and fourth interfaces on a single PDP-11 respectively. The high-order PDP-11 address bits are listed in Table 1-7. DTE/1-19 Table 1-7 PDP-11 Device Registers Interface Assignment 0 774400 1 774440 2 774500 3 774540 All of the necessary registers for implementing the specified types of data or non-data transfers have been included in the interface. In general, the majority of these registers are addressable by the PDP-11 for read or for write. They are not selectable from the EBox. 1.8 INTERFACE DATA AND CONTROL BUFFERING To facilitate efficient interprocessor data transfers, with minimum intervention by either the EBox or PDP-11 processors, a storage medium in the form of a semiconductor Random Access Memory (RAM) containing 16 words X 16 bits per word of storage has been included as a part of the interface. The access time of the RAM is about 125 ns. The available RAM storage is sufficient to contain all of the necessary control and data words used to perform the DTE20’s four major hardware operations as a free standing element. In addition, the RAM can be loaded and read under the direction of a diagnostic program resident in the PDP-11 processor and can also be used to control the DTE20 during diagnostic operations. 1.8.1 R Addressable Register Summary Table 1-8 provides a summary of all of the internal addressable locations within the DTE20. Sixteen locations are listed; twelve are RAM locations and the remaining four are register locations. Diagnostic Word 3 — This word can be read at any time from the PDP-11 processor. It consists of interface control signals and addresses, along with the TO10 byte mode bit. Status - This register consists of an EBox portion and a PDP-11 portion. The detailed bit assignments for both are given in Tables 1-13, 1-14, 1-15, and 1-16. Register bit assignments generally consist of Done and Error flags for the various operations, a flag for each processor to interrupt the other, and miscellaneous other flags. NOTE Each machine has its own separate copy of each status bit, except for the doorbells (e.g., there is a 10 TO10 Normal Termination flag and an 11 TO10 Normal Termination flag). Diagnostic Word 2 - This word is similar to Diagnostic Word 3 in that it can be read by the PDP-11 processor at any time simply by addressing the appropriate register within the DTE20. U nder diagnos- tic control, this word can be written to control the DTE20 minor states in a single pulse fashion. Also, because no real interrupts are sent to the EBox during diagnosis of the DTE20, a bit in this word can enable the appropriate flag to set to simulate a response from the EBox as if it responded to the interrupt. Finally, it can enable the current major state to lock out any changes in that state until such time as it is desired to do so. The femaining registers are RAM locations and are summariied, together with the DTE programining information, in Tables 1-9 through 1-19 of this section. DTE/1-20 Table 1-8 Addressable Register Summary Register Name DIAG3 STATUS Accessible By: PDP-11 BOTH PDP-11 PDP-11 INSTR DTE20 ADR KL10 INSTR FCN CODE . DATO. DATI XXX36 - - DATO. DATI XXX34 CONO, CONI 0.1 and KL10 DIAG2 PDP-11 DATO, DATI XXX32 - - DIAG! PDP-11 DATO, DATI XXX30 - - TO11 DATA PDP-11 DATO, DATI XXX26 - — TO10 DATA PDP-11 DATO, DATI XXX24 - TO11 ADR PDP-11 DATO, DATI XXX22 - - TO10 ADR PDP-1] DATO. DATI XXX20 — - TO11 BYTE CNT PDP-11 DATO, DATI XXX16 - - BOTH PDP-11 DATO, DATI XXX14 DATAO 2 TO10 BYTE CNT and KL10 ADDRESS WORD 2 PDP-11 DATO, DATI XXX12 - - ADDRESS WORD 1 PDP-11 DATO, DATI XXX10 - - DATA WORD | PDP-11 DATO, DATI XXX06 - - DATA WORD 2 PDP-11 DATO. DATI XXX04 - - DATA WORD 3 PDP-11 DATO. DATI XXX02 - - DELAY COUNT PDP-11 DATO. DATI XXX00 - - DTE/1-21 Table 1-9 Deposit or Examine Word Formats Word Bits Function DEXWD1 15-04 Must be zero, reserved by DEC 03-00 K110 data bits 0-3 DEXWD?2 15-00 KL10 data bits 4-19 DEXWD3 15-00 KL10 data bits 20-35 TENAD1 15-13 Address space 12 Deposit bit 1 = deposit 0 = examine 11 PRTOFF if 1 protection and relocation is off for examines and deposits for a restricted mode DTE TENAD?2 10-09 Must be zero, reserved by DEC 08-07 Must be zero, reserved by DEC 06-00 High order KL10 address bits (13-19) 15.00 Low order KL10 address bits (20-35) DTE/1-22 Table 1-10 TO10 Transfer Word Format Word Bits Function DLYCNT 15-14 Unibus address bits 17-16. Specifies two high-order bits of 18 bit PDP-11 address used in 18 bit byte transfer addresses. Transfer cannot cross a 32K boundary. TO10 and TO11 transfers must be in the same 32K bank. 13-00 NEGATIVE DLY COUNT — The software specifies how many 500-nanosecond units of delay are to occur between each byte on byte transfers in either direction. The delay also applies before the first byte. During the transfer operation the DTE up counts a copy of this count in the ABC register, once each 500 nanoseconds, until bit 13 = 0. NOTE The count is incremented by 1 and then the hardware tests bit 13 of ABC for = 0. Therefore both values of 17777 and 00000 are equivalent to no delay. TO10AD 15-00 Byte address of source string. This is updated by the DTE as each byte is transferred. At the end of a transfer, it points to the byte (word) which would have been transferred next from PDP-11 memory. The update is by +1 for byte mode and +2 for word mode. TO10BC 15 If a 1, this bit interrupts both processors at the completion of the current transfer. If a 0, it interrupts the -10 only. TO10DT 14-12 Must be zero, reserved by DEC. 11-00 Negative byte count. 15-08 High order byte PDP-11 byte mode: equal to 0 PDP-11 word mode: bits to become KL10 data bits 20-27 07-00 Low order byte bits to become KL10 data bits 28-25 DTE/1-23 Table 1-11 TO11 Transfer Word Format Word Bits DLYCNT 15-14 Same as for TO10 transfer — see Table 1-10. 13-00 Same as for TO10 transfer — see Tabie 1-10. TO11 15-00 Function Byte address in PDP-11 memory of where to store next byte received from EBox. This word is updated as each byte (word) is transferred. At the end of a transfer, it points to the byte (word) that would have been transferred next. The update is by +1 for byte mode and +2 for word mode. TO11BC 15 I Bit — If O, on normal termination interrupt only the PDP-11.If 1, on normal termination interrupt both the PDP-11 and EBox. If an error occurs, the 1 bit is ignored and both the PDP-11 and EBox always get an error termination interrupt. 14 Z Stop — If 1, stop on a null character received from the EBox, after storing it in PDP-11 memory. The TO11AD is not incremented so that the next transfer can start by overwriting the null character if desired. 13 TO11BM — If 1, set byte mode in the DTE, if 0, set word mode in the DTE for TO11 transfer. TO11DT 12 Must be zero, reserved by DEC. 11-00 Negative byte count 15-08 High order byte PDP-11 byte mode: KL10 bits 28-35 or 20-27 PDP-11 word mode: KL10 bits 20-27 07-00 Low order byte PDP-11 word mode: KL10 bits 28-35 PDP-11 byte mode: KL10 bits 20-27 or 28-35 DTE/1-24 Table 1-12 DATAO DTE Function Bits 0-22 23 ‘Function Must be zero, reserved by DEC ‘ TO111IB — This is the “I” bit. If 1 set TO10IB. If 0, clear TO10IB. If 1, the EBox has set the “I” bit for a TO10 byte transfer. Both the EBox and the PDP-11 will be interrupted on normal termination. If 0, the EBox has not set the “I”” bit for a TO10 byte transfer. Only the EBox will be interrupted on normal termination. The EBox may then reset the TO10 byte pointer, before reloading the TO10 byte count and performing a scatter read. 24-35 Negative Byte Count — The twos coinplement of the nurfiber of éharacters left to transfer until a TO10 normal termination occurs. A -1 will transfer one character to the EBox before_: a normal termination. A 0 will transfer O bytes before a normal termination. DTE/1-25 Table 1-13 CONI DTE Function Bits 0-19 20 Function Read as zeros RM — a 1 in this bit indicates that the DTE is in restricted mode, a 0 in this bit indicates that the DTE is in privileged mode. 21 DEAD11 —alin this bit indicates that the PDP-11 pbWer is not correct (the Unibus signal “AC LOW? 22 is asserted) and that no transfers can take place. TO11DB — a 1 in this bit indicates that the EBox has requested a PDP-11 doorbell interrupt and is waiting for the PDP-11 to take some action. 23-25 26 ' Read as zeros. TO10DB — a 1 in this bit indicates that the PDP-11 has requested a doorbell interrupt and is waiting for the EBox to take some action. 27 TOI1ER — a 1 in this bit indicates that an error occurred during a TO11 28 Read as zero 29 transfer. TO11DN — a | in this bit indicates that a TO11 transfer was completed and an error did not occur. The “I” bit had been set by the PDP-11. The transfer is completed if: 1. The byte count became equal to zero. 2. The PDP-11 had set the “Z” bit and a null character was encountered. or 30 TOIODN — a 1 in this bit indicates that the byte counter for the TO10 transfer became equal to zero and an error did not occur. 31 TOIO0ER — a 1 in this bit indicates an error (PDP-11 memory parity or Unibus timeout error, but not EBus Parity error) occurred during the TO10 transfer. 32 PIOENB — a 1 in this bit indicates that the DTE is enabled to perform examines, deposits and byte transfers at PI Level 0 by the EBox. NOTE The DTE is automatically enabled if the PDP-11 is privileged even though this bit is 0. 33-35 The current Pl channel assignment for doorbell interrupts, byte transfer normal and error terminations. DTE/1-26 Table 1-14 CONO DTE Bit Function Bits F}lnction 18-21 Must be zero, reserved by DEC. 22 TO11DB — causes a doorbell interrupt in the PDP-11, setting the 10 request interrupt flag in the DTE status register. This flag can only be cleared by the PI?P-I 1. 23 24 CR11B — clears the reload PDP-11 button in the DTE. SR11B — sets the reload PDP-11 button in the DTE. Setting this bit in the status register initiates the ROM bootstrap in the PDP-11. 25 Must be zero, reserved by DEC. 26 CL11PI — clear the PDP-11 requestifig 10 interrupt flag in the DTE status register. 27-28 Must be zero, reserved by DEC. 29 CLTO1!1 — clear both the TO11 normal termination, and alsq the TO11 error termination flags in the bTE. 30 CLTO10 — clears both the TO10 normal termination, and the TO10 error termination flags in the 31 PILDEN — loads the PI Interrupt Channel number from bits 33-35 and PI (Level 0 enabled from bit 32. 32 PIOENB — enables PI0. 33.35 PI Channel Number. Loaded if bit 31 is equal to 1. DTE/1-27 DTE. Table 1-15 DATO DTE Status Function Bits 15 Function DON10S — If 1, set TO10 normal termination status ("fOlODN). This bit is provided for diagnostic purposes only. Setting it via a DATO does not terminate a transfer in progress. 14 13 DONI10C — If 1, clear TO10 normal termination status (TO10DN). ERR10S — If 1, set TO10 error termination status (TO10ER). This bit is provided for diagnostic purposes only. Setting it via a DATO does not terminate a transfer in progress. 12 ERRI10C — If 1, clear TO10 error termination (TO10ER). 11 INT11S — If 1, set 10 request PDP-11 interrupt' (TO11DB). This results in a PDP-11 vector interrupt. 10 INT11C — If 1, clear 10 request ‘PDP-Il interrupt (TO11DB). This enables more doorbell interrupts to the PDP-11 to occur. 09 PERCLR — If 1, clear the PDP-11 memory parity error flag (1 1IMPE). 08 INT10S — If 1, set request 10 interrupt (TO10DB). This results in a vectored interrupt to EPT‘location 142+ 8 *n, 07 DONI1S — If 1, set TO11 normal termination flag (TO11DN). This bit is provided for diagnostic purposes only. Setting this bit does not terminate a transfer in progress. 06 DON11C —If 1, clear TO11 normal termination flég (TO11DN). ' 05 INTRON — If 1, enable DTE to generate PDP-11 BR requesfs. Clearing or setting this bit does not clear any interrupts waiting. 04 EBUSPC — If a 1, clear EBus parity error. 03 INTROF — If 1, disable DTE from generating PDP-11 BR requests. Clearing or setting this bit does not clear any interrupts waiting. 02 EBUSPS — If 1, set EBus parity error. 01 ERR11S —If 1, set TO11 error termination flag (TO11ER). This bit is provided for diagnostic purposes only. Setting it does not terminate a transfer in progress. 00 ERR11C —If 1, clear TO11 error termination flag (TO11ER). DTE/1-28 Table 1-16 DATI DTE Status Function Bits Function 15 TO10DN — The TO10 byte count became 0 or the PDP-11 program set DON10S. TO10DN will not be set if an error termination occurred, i.e., TO10ER. 14 Read as zero, this bit is unused. 13 TO10ER — an NPR Unibus parity error (DIAG3 [NUPE] ), PDP-11 memory parity (status [1 IMPE]), or a Unibus timeout (no bit) occurred during a TO10 byte transfer, or the PDP-11 program set the status bit (ERR108S). Status bit (TO10DN) will not be set, if an error termination occurred. Thus, PDP-11 programs must test for both TO10DN and TO10ER. 12 RAMISO — The data out of the RAM location is all Os. This bit is provided on a read for diagnostic purposes only. It has no meaning and is unpredictable unless the DTE is being single stepped. 11 10 TO11DB — The 10 has requested (via CONO DTEN) a PDP-11 doorbell interrupt. DEXWD1 — This bit is provided for diagnostic purposes only. It has no meaning and is unpredictable unless the DTE is being single stepped. 09 MPE11 — Indicates that the PDP-11 memory had a parity error during a data fetch for a TO10 byte transfer. Parity errors are detected only if the PDP-11 has the MF11UP or MP11LP memory parity option. 08 TO11DB — The PDP-11 has requested a 10 doorbell interrupt (INT108S) and the -10 has not yet cleared the bit (via CONO DTEN) using CL11PI. 07 TO11DN — The TO11 byte count became equal to 0 (TO11BC = 0), the transfer stopped on a MU11 character (status bit NULSTP = 1), or the PDP-11 program set status bit DON118. 06 EBSEL — E Buffer Select. This bit is provided for diagnostic purposes only. It has no meaning and is unpredictable unless the DTE20 is being single stepped. 05 04 NULSTP — Null Stop. The TO11 transfer stopped because the stop bit was set (TO11BC [Z Stop] ) = 1. B PAR ER — EBus Parity Error. The DTE detected an EBus parity error during a TO11 byte transfer or examine transfer. 03 RM — If 1, the attached PDP-11 is in restrictéd mode. If 0, the attached PDP-11 is in privileged mode. The value of this bit is determined by the setting of the privileged switch on the DTE20. 02 DEXON - The last deposit or examine operation has been completed. No interrupt occurs. The PDP-11 must watch for this bit to be set after every deposit or examine. The DTE20 clears status bit DEXON whenever a deposit or examine is started (by loading TENAD?2). 01 TO11ER — an error occurred during a TO11 byte transfer or the PDP-11 program sets the status bit ERR118S. Status bit TO11DN will not be set if an error termination occurred. Thus, programs must test for both TO11DN and TO!1ER. 00 INTSON — Interrupts on. If 1, the DTE is enabled for PDP-11 BR requests. If 0, it is disabled (INTRON enables, INTROF disables). DTE/1-29 Table 1-17 DATI/DATO DTE DIAG Word 1 Bits Function DS REMOVE STATUS FALSE DS REMOVE STATUS TRUE and all DS bits = 0 (Any DS bits = 1 are considered illegal) Receive processor status bits. Observe up to 128 DS bits asserted by the DTE. 15-12 Unused 11 DS04-1 = KL Clock Error Stop. The KL10 NOTE Unless the DS Bits are asserted without DCOMST internal clock (32 MHz) has frozen due to a Rardware malfunction of one of the following: (Diagnostic Command Start), this will always ~ CRAM, DRAM, Fast Memory Parity Error, or read as zeros because DCOMST clears the register at the end of a diagnostic cycle. Field Service test condition. 10 DS05-1 = RUN (1). The microcode examines this flag between functions. The microcode enters a Halt Loop if this flag is off. This flag is under control of the PDP-11, using two diagnostic functions. The KL10 cannot affect 09 DS06-1 = HALT (1). This signal is set when the microcode enters the Halt Loop and clears the Signal when it leaves the Loop. 08 DEX — Deposit or Examine major state. WRITE: Must be zero. READ: A 1, indicates interface major state is deposit or examine. 07 TO10 — READ: a 1, indicates interface major state is TO10 transfer. 0 indicates not in TO10 transfer state. DFUNC (Remove Status) — WRITE: A 1, causes the EBox to stop sending basic status on the so that a loopback test can be performed on the DS lines or a DIAG FUNC can be sent to the DS lines, EBox via the DS lines. If any of the DS lines are set (by the DTE) the result is an “OR” of the bits set in the and EBox status. 06 DTE TO11 — READ: A 1 means interface major state is TO11 transfer. WRITE: Must be zero, 05 D1011 — Diagnose 10/11 interface. READ: If a 1, the DTE is in 10/11 diagnostic mode, i.e., it will diagnose itself. If a 0, it is not in 10/11 diagnostic mode. WRITE: If a 1, set DTE to 10/11 diagnostic mode. This mode is used to diagnose the DTE itself. If a O, leave 10/11 diagnostic mode. DTE/1-30 Table 1-17 (Cont) DATI/DATO DTE DIAG Word 1 Bits 04 Function VEC04 — Vector Interrupt Address bit 4: READ: Vector interrupt address bit 4 PULSE-WRITE: If a 1, generate a single clock cycle. If 10/11 diagnostic mode (D1011 status bit) is also set. 03 DIKL10 — READ: This bit is read as zero. WRITE: If a 1, and the DTE is in privileged mode, put the DTE into KL10 diagnostic data transfer mode. Subsequent deposits and examines become diagnostic functions instead of accessing KL10 memory. If a 0, put the DTE in normal data transfer mode. 02 DSEND — READ: This bit is read as zero. WRITE: If a 1, send data (TO10) during a diagnostic bus transfer. If a 0, receive data (TO11) during a diagnostic bus transfer. 01 This bit is unused and must be zero on a write. It is read as zero. 00 DCOMST - Diagnostic command start. READ: If a 1, a diagnostic command is in progress. WRITE: If a 1, and the DTE is switched to privileged mode, diagnostic command start is set. If a 0, diagnostic command start is cleared. DTE/1-31 Table 1-18 DATI/DATO DIAG Word 2 Bits 15 Function RFMADO — RAM File Mixer Address 0. READ: The contents of RFM address 0. WRITE: Must be zero. 14 RFMAD] — RAM File Mixer Address 1. READ: The contents of RFM Address 1. EDONES — WRITE: If a 1, set EBus done. If a 0, cléar EBus done. 13 RFMAD?2 — RAM File Mixer Address 2. READ: The contents of RFM Address 2. WRITE: Must be zero. 12 RFMADR3 — RAM File Mixer Address 3. READ: The contents of RFM address 3. WRITE: Must be zero. 11-07 Unused — READ: Read as zeros. WRITE: Must be zero. 06 DRESET — DTE Reset. READ: Read as zero. WRITE: Ifa 1, reset the DTE. 05 Unused — READ: Read as zero. WRITE: Must be zero. 04-01 READ: Read as zeros. WRITE: Loads 04, 03, 02, 01 into minor state counter 8, 4, 2, 1 for diagnostic use only. (During normal operation must be zero.) 00 Unused — READ: Read as zero. WRITE: Must be zero. DTE/1-32 Table 1-19 DATI/DATO DIAG Word 3 Bits 15 Function SWSLLT — Swap Select Left READ: CNT1 [N] Swap Select LT. WRITE: Must be zero. 14 DPS4 [N] Parity (1)H READ: DPS4 [N] Parity flop is on a one. Diagnostic use only. WRITE: Must be zero. 13-08 Captured Unibus Parity Error Information. READ: Ann indicates Unibus register address bit, Dnn indicates Unibus data bit, when a Unibus parity error is detected. TIME UNIBUS DATA BITS Initially D15 D14 D13 D12 D11 A0O 1st Shift D10 D09 D08 D07 D06 AQO 2nd Shift D05 D04 D03 D02 D01 A00 3rd Shift 4th Shift D00 A04 A03 AO2 AO1 AOO ; D15D14D13 D12 D11 AOO WRITE: Must be zero. 07-06 Unused READ: Read as zeros.. WRITE: Must be zeros, 04 DUPE — DATO Unibus Parity Error. READ: If 1, a DATO Unibus parity error has been detected by the DTE. CDD — Clear DUPE and DURE error flags. DTE/1-33 Table 1-19 (Cont) DATI/DATO DIAG Word 3 Bits 03 Function WEP — Write even (bad) parity. READ: Read the status of the write even Unibus parity flip-flop. WRITE: If a 1, write even Unibus parity. Results in DTE generating even (bad) parity on all Unibus transfers which have parity. If a O, the DTE will generate odd (good) parity on all subsequent Unibus transfers which have parity. This bit is provided for diagnostic purposes to check the parity networks. 02 DURE — DATO Unibus receive error. READ: A Unibus receiver error has occurred. WRITE: Must be zero. 01 NUPE — NPR Unibus parity error. READ: If a 1, a Unibus parity error has occurred on an NPR (byte) transfer. CNUPE — WRITE: Clear NUPE. 00 TO10BM — TO10 byte mode. READ: Read as zero. WRITE: If a 1, TO10 byte transfers are to be performed in byte mode from the PDP-11 memory. If a 0, TO10 byte transfers are to be done in word mode from PDP-11 memory. DTE/1-34 1.9 BUS OPERATION Functionaily, the DTE20 operates in two ways. One way is an operation that fetches data; the other is an operation where the data must be loaded by an operating program. In the first method, a single bus operation may access the interface from the PDP-11 to read or write data (or control information) into the interface RAM file. Thisis done by using DATI and DATO instructions and involves the Unibus. This type of operation activates the Interface Control Logic long enough for the RAM access. No dialogue, other than the normal dialogue that would take place between the PDP-11 and any standard peripheral device, i.e., MSYN, SSYN, etc., occurs. Similarly, the PDP-11 can read or write status information to or from the interface using this same mode of operation. In the second method, the interface detects the loading of control information from the PDP-11, or from both the PDP-11 and KL10 processors, and begins processing this information. The interface initiates an internal timing sequence that includes the necessary interprocessor dialogue. The result of this operation is to transfer information between the two processors using both the EBus and the Unibus, where the direction of transferis a function of the operation being performed. The DTE20 performs four basic hardware operations: DEX (Deposit or Examine) TO1! Transfer/TO10 Transfer Interprocessor Doorbell. Diagnostic Functions Multiple transfers take place for both TO11 and TO 10 transfers; however, the source and destination differ. In the TO11 transfer, the source of the datais the KL10 memory and the destinationis the PDP11 memory. The situation is reversed for TO10 transfers; the source is the PDP-11 memory and the destinationis the KL10 memory. The DEX (Deposit or Examine) operation differs from a TO10 or TO11 transfer operation by the fact that a single transfer occurs. Also, no interrupt is generated to the PDP-11 upon completion of the operation. The interprocessor doorbellis unique in that it uses only the “peripheral bus control logic” (i.e., the BR Control and the EBus Dialogue Logic) and does not initiate the internal time state logic. Data entering the DTE20 on the EBox side does so in 36-bit words, which are converted into 16-bit words within the interface and stored in the RAM FILE. From there, the buffered data word can be transmitted to the PDP-11 under control of the Interface Control Logic by the NPR facility. Data entering the DTE20 on the PDP-11 side does so in 16-bit words that are stored in the RAM FILE. From there, the buffered word can be transmitted to the EBox under the control of the Interface Control Logic, using the interrupt control and the EBox side interrupt logic. This transfer also involves the E-Buffer register. Two basic classes of transfers can be performed in terms of implementation. Table 1-8 contains a list of PDP-11 addresses given to select the appropriate RAM address within the interface, the functional name for that particular RAM slot, and a description of that slot’s usage during the appropriate interface operations. The first classis Deposit and Examine and deals with an address in KL10 memory and a data word thatis either sent or received to or from KL10 memory as specified by the address word. These two operations involve five temporary RAM storage slots for address and data. DTE/1-35 The second class is TO11 transfer, or TO10 transfer, and deals with a Delay Count word, a Byte Count word, an address word, and a data word. All of these words must have storage space in the RAM FILE. Before transfers for either class of operation begin, the necessary words that control the particular transfer must be supplied, by the processor, to the RAM FILE. Refer to Figures 2-1 and 2-2. The PDP-11 can read or write all RAM locations and also the Diagnostic and Status registers via the Unibus. These registers have internal addresses (shownin brackets [ ]); for example the Status register is address [16]. To set up a transfer within the interface, the PDP-11 performs DATO instructions while addressmg the appropriate RAM locations. The EBox cannot address any of the RAM locations and, in fact, is only required to supply one piece of control information. This is the TO10 Byte Count word, necessary in the TO10 transfer operation. It is supplied by performing a DATAO DTE X instruction in the EBox. The TO10 Byte Count word will be placed into a temporary Buffer register, EB HOLD, where it will reside until the Interface Control Logic can store it in its slotin the RAM FILE. The Status register contains bits that allow both processors to communicate. Thisis necessary to negotiate transfers. The featureis referred to as *‘the interprocessor doorbell,” andis implemented via the appropriate interrupt logic, with the interrupt control and the Status register. To summarize, both processors communicate and negotiate the particular operation to take place. Next, the appropriate RAM slots are loaded by the PDP-11 or EBox accordingly and the interface, using detection logicin the data control, starts up the interface via the Interface Control Logic. At this time, the interface contains all the necessary informationin order to complete the specified transfer or transfers, including the ability to use either interrupt facility as necessary. 110 PROGRAMMING EXAMPLES Generally, the PDP-11 program sets up the interface by readmg status conditions and loading control parameters, and by performing the appropriate sequence of instructions. The format is: INSTR ADRI1, ADR2 where ADRI is the symbolic address of a particular PDP-11 general purpose register (one of eight) within the processor (R0O-R7). ADR?2 is the symbolic address of the‘memory location or device being addressed by this instruction. For example: MOV DLYCNT, @ RAMO. In this example, the MOV instruction moves the word in symbolic location DLYCNT into the loca- tion addressed by the number in symbolic location RAMO. The @ symbol indicates indirect addressing. : , If the contents of RAMOis the approprlate DTE20 address for the Delay Count word, i.e., XXXXOO then the value in DLYCNT will be moved (loaded) into the DTE20 delay count slotin the RAM (Figure 1-10). The interprocessor doorbell feature will allow the PDP-11 and KL 10 processors to talk to each other via the DTE20 interrupt facilities. To interrupt the EBox, the PDP-11 performs the following: MOV INTI10S,@ STATUS; Ring the KL10 doorbell. DTE/1-36 PDP-11 DLY CNT PROCESSOR IR [~ ] CALCULATE EFFECTIVE ADDRESS CONTROL LOGIC v a = ' B | RAM 2 ADDRESS XXX X00 l'_”‘x READ TO GET AT l—RAM 0— XX POP-11 MEMORY 10-1795 Figure 1-10 Load DLY Count Assume location Instruction +2 contains a single one in bit position 08; this is necessary in order to set the flag in the DTE20 that causes a programmed interrupt to the EBox. Also, assume location Status contains the address of the Status register in the DTE20, XXXX34. The execution of the MOV instruction by the PDP-11 processor causes the appropriate flag in the interface to set. This action initiates a programmed interrupt to the EBox (Figure 1-11). PDP-11 AL . PROCESSOR IR CALCULATE BIT 08 (1} EFFECTIVE ADDRESS CONTROL l LoGIC EBUS DATA 1] 2 INTERRUPT CONTROL o DIALOGUE LOGIC 5 | z T status ADDRESS "REQ 10 INT KL10" N FLAG SETS" [ v] STATUS XXXX34 T *INTERRUPT ADDRESS XXXX34 [—* xvz READ TO GET AT STATUS Xz POP -11 MEMORY 10-1796 Figure 1-11 Ring KL10 Doorbell DTE/1-37 Assume that the DTE20 has completed a series of transfers to the EBox and a flag in the DTE20 (TO11 TRANSFER DONE) sets. This indicates that the current series of data transfers is terminated and could require action from either or both processors. In the event the EBox is interrupted, the following could be the response: CONI DTE20,BITS; Read the Interface Status register . After evaluating the bits the service routine clears the interrupt CONO DT?ZO,CLTOII; Clear TO11 DONE removing the interrupt Once the priority interrupt logic has arbitrated the priorities and transferred control to the device service routine, this routine must determine what to do about the interrupt. Normally, it reads the Status register and tests the bit pattern, and then makes a determination based upon its findings. It - must also turn off the interrupt to enable any other devices on the same channel to use it. Figures 1-12 and 1-13 show the simplified sequence. AS A RESULT OF THE PRIORITY INTERRUPT ——-I VECTORING TO APPROPRIATE HANDLER ————— ~=-9 | o T pI1-7 AN i DECODER 1 ASSIGN || " CONT l r| PI —L—-— || | — s —| eBox CONI BEING EXECUTED - | CONTROL | " i controv | g | [ anp EBUS Losic | |I = ] @657‘“‘0 . e " ‘] PASS v PRIORITY INTERRUPT | | | | I i | ) | TO11 DONE (1) PI REG | | [ [ | I_.._._sfi”fi“___"__l STATUS WORD TO MBOX MBOX KL 10 CORE —I | TO 11 DONE NOW STORE WORD IN KL10 MEMORY THE PROGRAM IN KL 10 MEMORY WILL AND TURN OFF THE TEST THE TO 11 DONE —i | I I ] I_ _‘ I BIT DTE INTERRUPT Figure 1-12 CONI Simplified DTE/1-38 | | I I I CONO PI REG IR CONTROL r——— o — - — — — — ~ e —— — — ——de PRIORITY | PI | AND o | INTERRUPT te—s| EBUS > DROPPED | Losic | CONTROL L — REMAND o —— — | DECODER PI1 -7 ! ! i TRANSFER ) I CLEAR AR BIT TOCLR DONE A EBUS DOO- 35 BIT PLACED ON EBUS DATA LINES DONE " |, o ) 0 fe— STATUS REG -~ N i0-1798 Figure 1-13 CONO Simplified DTE/1-39 SECTION 2 FUNCTIONAL DESCRIPTION 2.1 BUS INTERFACING PDP-11 SIDE Refer to Figures 2-1 and 2-2. The Instruction and Register Decoder PDP-11 side is a functional com- ponent. It connects to the Unibus control lines, the interrupt logic, and the NPR logic. It produces the appropriate functional internal register block address and passes data as appropriate during DATO and DATI instructions. Each addressable register has its internal address given in brackets [ ], e.g., Status register [16]. This number is the internal octal address formed from the Unibus address lines A(04:01), a subset of A (17:00). The lines C(1:0) determine the type of instruction being performed, and data passes to or from the internal register block on the data lines D(15:00). A CROBAR signal is generated by the power controller when the KL10 system is powered up and asserts for approximately 5 seconds. It is passed to the DTE, where it disables the DTE from driving any signals onto the Unibus that might be incorrectly produced as power is asserted or disasserted. During interface transfer operations, data to be passed between the KL10 and PDP-11 is buffered first in the RAM portion of the Interface Control Logic (Figure 2-2). The data passes through the RAM portion to or from the PDP-11 processor using the NPR facility. In this way, the PDP-11 processor is free to carry on other non-Unibus functions, while DTE20 uses the Unibus for a transfer to or from PDP-11 memory. The Interface Control Logic informs the NPR logic that it would like to make a transfer involving PDP-11 memory. The NPR logic asserts NPR and a dialogue takes place between the PDP-11 and the Instruction and Register Decoder. If the PDP-11 processor or some other device is not using the Unibus, the DTE20 will receive NPG as a response to having asserted NPR. It next asserts SACK and then tests for BBSY SSYN. When this condition is not present from another device, the interface asserts (BBSY). The Address and Byte Count (ABC) register, one of the working registers. at this time holds the PDP-11 address and places it on the Unibus address lines. Normally, the address is held in one of the RAM locations until it is needed for a transfer. The two Status registers are a link between the two processors. All Status register bits are separate flipflops except for the interprocessor doorbell. Both Status registers can be addressed by either the KL 10 or the PDP-11 processor. By setting the TO10 doorbell or TO11 doorbell bit in the Status register, a handshaking will take place between the two processors using the interrupt dialogue. Thus, this mechanism, referred to as the “interprocessor doorbell feature” is a useful medium for communications between processors and transfers may be negotiated. To the EBox, the DTE20 appears in most respects as a KL10 peripheral. The EBox can perform conditions out (CONO) or conditions in (CONI) instructions, which can set, clear, or read status information from within the interface. The internal register block is essentially transparent to the EBox, with two notable exceptions. Both a Status register (as mentioned previously) and the E B HOLD register can be accessed by the EBox. Data is passed between the DTE20 and the EBox using the EBus data lines D(00:35). Device addressing is handled in a slightly different manner than was the case with the PDP-11 processor, because the EBus has a different structure than the Unibus. Each DTE20 in the system has a discrete physical number assigned to it. DTE/2-1 wcom C)-—-4€0C32567I>-C{:::> DPS3 DATI/O CONTROL REQ INT DIAG (9 BITS) 7 DATA 2 TIMING CONTE% INT PII-7 DIAGNOSTIC INTERRUPT CNT3 DPSS CONTROL ANY DONE 10 : NULL LOGIC DPS6 BONE CONDS DOORBELL OPFS INTERRUPT PID CONTROL ANY DONE 11 § 10 INT ACT DPS 5 11 INT ACT INT1 CNT4 CONDS €$00-06 O INTERNAL REG [N] *gp DATAO FO0-02 ABC > DIAGNOSTIC (14) m wcao | aoDRESS < DATO DATO/DATI - DATO/DATI 45, R DATO/DATI DIAG WORD 2,¢, STATUS DPS5 AND (0) (1) DECODING (2) REGISTER DONE & CONTROL STATE CONDS SACK [ RAM FILE 00-134 DPS4 - {4) DATO (5) N 23; < ONT3 [, CONI CNT6 i o ENT? DATAO . * 12) B 13) DATA DATAL (36 BITSL] cnT6 CONTROL cNTSITM DATO/DATI 1,5 TRANS DPS2 % SIMPLIFICATION [N]VARIABLE LENGTH REGISTERS OPENDS DTE Simplified Functional Block Diagram DTE/2-2 U MSYN S 1 NPG INT2| (16 BITS) TRANS/ CONTROL STOATE > ¢ NT1, SnT2 ] CoNTROL ? B RCV_DATA [sTART) | CONTROL LOGIC &NTa N INT1| DATA BUS INTERFACE CNT7 ¢ gurrer DPS6 TRANSFERS WR— EN ! c<1od CoNTEoL 1) CONO SSYN DECODING PDP-11 SIDE 10) F BBSY AND REGISTER 3) KL-10 SIDE {18 BITS) BG INSTRUCTION 2 D (XX) Figure 2-1 TRANSARCY PS6 TRANSFER DPS3 A<17:00) DPS2 DPS6 ACKN 1 INSTRUCTION |NTERFACE N/ N\ CONDS ¥EB HOLD /CONT CONO/CONI T STATE OPERATIONS DPS3 DEMAND DATA INTERRUPT CONTROL pps; 3 (17) DIAG WORD SP DATAD > INT2 INTERRUPT ) B8R IN[CE)STEJPT e A REQ TRANS CONDS NoR LOGIC INTI NPR INT2 E BUS CLK 10-1799 SWAP SEL LT SWAP SEL DATO ,DATI DPS4 SEL 2 DPS4 SEL1 :l FROM UNIBUS 15,14 ,1312,4,3,0 FCN STROBE CNT6 EMIX EN — UFNR;gL"fS CNT6 CONT SEND — i [STTS” DATA CNT 6 EBUF SEL CONTROL o o Nt = Q CNT5| CNT6 — CNT6 BUS SEL | - ' 15- 0 1 INTERRUPT : | PHYS #, ACK, TRANS | TRANSFER REQ —Jl REMOVE STATUS i ] |WRIWR " —»} STROBE > DS 0-6 — e e —— —— — — — — — — — — — —— LOCK MAJOR STATE | DEX MAJOR | —I - STATE | pECODE I DEPOSIT OR EXAMINE MINOR STATES l' Bl STATE COUNTER|— | STRS8 L 10 11 MAJOR STATE I I l I I I | ' al DECODE DIAG COM __J I INH - CLOCK —/ +2}| -9 CLK CNT 7 | CNT7 TO 10 TRANSFER MINOR STATES — — <04:0% SET [*SET L DECODE +1 T TT . ——— — — — — — — — — — TRANS | conT# E;’I DEMAND — Vo PIO-7 ALL MINOR SP DONE ACCESS CNT6 lzyg | ' \} STATUS FROM EBUS DPS5 <'—r—— CONO,CONI UNIBUS ADR FROM AT o4 DATO, DA | TI ] s VEC 2-4 = B8 BUS ST COMP CONTROL le—! BG e+l sACK B8R ‘g le—»! B8 BSY = INT 1 NPR REQ DIAG DATI wr| conTROL WRH CNT1 SH CNT4| I ~ DATO, F— ST I —l |+ [ ack STATES TO 11 TRANSFER ¢ | MINOR STATES - l | w CONDS | CLR !| VARIOUS Y ' UNBUS DATA } ol TRANSFER REQ ) FROM CNT3 w L | | e FO-2 W ._{ CSO -6 | clLtjojc|x TTT T T T EBUS CNT3 1 SP1ST|ST|ST|WR|WR|WR]|SH fc‘l CONTROL | b MAJOR | BUS I i| 1010 | WR D INT 2 T CNT2 UBDRMIX SEL1,2 NPG 4—->1| SSYN ol | MsYN »| le— DSO-6 le—{ SEND,10/11, DFUNC \/ j KL-10 DIAG EN | 10-1800 Figure 2-2 Simplified Control Block Diagram DTE/2-3 The Controller Select (CS) lines are hard-wired into the logic of each interface. Thus, the EBox must assert the CS lines in a particular configuration and cause the interface to look at these lines (DEM AND) before a transaction can take place between the interface and the EBox. In addition, the type of instruction is given by the function lines F(00:02), while the Controller Select is valid. 2.2 BUS INTERFACING EBOX SIDE Refer to Figures 2-1 and 2-2. The EBus connects functionally to the interface Instruction and Register Decoder. The decoder is logically driven from one of two sources. Interrupt Logic EBox (for instructions). During interrupts to the EBox, the interrupt logic asserts PI0-7 as the active interrupt line and waits for some response from the EBox. When the EBox is ready to select those controllers and devices on a particular channel for arbitration, it asserts the Controller Select lines CS(04:06) as the channel number (priority interrupt channel number), function lines F(00:02) as PI level serviced, and then asserts DEMAND. All controllers and devices interrupting on the interrogated channel place their physical controller or device number on the EBus data lines in a preassigned bit position (Dxx). Once again, the DTE20 waits for a response from the EBox. The physical controller numbers are given priority according to the weight of the bit position on the EBus. Physical number 0 has higher priority than physical number 1 and so forth. In the EBox, the priority interrupt logic arbitrates the incoming physical number, asserts CS(00:03) the physical controller or device to be honored (this is one unique device), CS(04:06) channel being served, and F(00:02) PI address in, and, finally, asserts DEMAND. When the DTE20 is the selected device, it places a special function word on the EBus data lines that identifies the type of service required from the EBox. This function is called the API FCN. The interface asserts ACKNOWLEDGE and TRANSFER to the EBox. Some time later, the EBox drops DEMAND, which detaches the decoder. The EBox responds to the API FCN by executing a DATAO or DATALI instruction in microcode and data passes over the EBus data lines through the E-Buffer and eventually to or from the internal register block. 2.3 INSTRUCTION AND DATA TRANSFER IMPLEMENTATION OVERVIEW-EBOX SIDE Data transfers over the EBus are implemented in a similar manner. Assume the EBox wishes to place a word of data into the EB HOLD register. The following dialogue occurs. The EBox places the device select code on CS(00:06). Four possible DTE20 device codes: 200, 204, 210, and 214, are used for the first through the fourth interfaces, respectively. The EBox places DATAO on F(00:02), places the data on the EBus data lines D(00:35), and asserts DEMAND. The interface Instruction and Register Decoder implements the DATAO function and then asserts ACKNOWLEDGE and TRANSFER. At this time, the data is in the EB HOLD register. This completes the DATAO instruction. By using a variation of the same procedure for a CONO instruction, a bit is set in the Status register that causes an interrupt to the PDP-11 processor. Refer to Figures 2-1 and 2-2. The dialogue between the DTE20 and the EBox takes place as with the DATAO instruction. The difference is that the function lines specify CONO in F(00:02). The EBox places a bit in bit position 23 on the EBus and asserts DEMAND. For detailed bit assignments, see Tables 1-12, 1-13, and 1-14. DTE/2-4 The interface Instruction and Register Decoder takes the bit from the bus and sends it directly to the Status register flip-flop. Setting the appropriate flip-flop (DPS5 10 REQUEST INT, in this case) constitutes the “doorbell.” The transition of this flip-flop to a 1 is passed into the interrupt control, where it raises the level DPS5 11 INT. This starts the interrupt logic on the PDP-11 side of the DTE20 and BR is asserted over the Unibus control lines. The interrupt condition is passed to the Instruction and Register Decoder, which carries on the appropriate dialogue with the PDP-11 processor. Upon receiving BR from the interface, the PDP-11 asserts BG, granting the bus. SACK is asserted and the DTE20 must test for (BBSY, SSYN) to ensure that no other device is still using the Unibus. As soon as the Unibus is free, BBSY is asserted and the vector address, as well as the interrupt line, is placed on the Unibus. Finally, the PDP-11 asserts SSYN, which terminates the bus dialogue. In a similar manner, CONI reads the Status register. Once again, the dialogue takes place between the DTE20 and the EBox. The function code for CONI is transmitted via F(00:02), together with CS(00:06), followed by DEMAND. The selected Status bits are selected and passed through the Instruction and Register Decoder to the EBus. When the DEMAND level is removed, the decoder is decoupled and the operation is complete. The E-Buffer is quite often being used and, therefore, cannot be guaranteed to be free when the EBox is loading the TO10 byte count into the DTE20. The E B HOLD logic was implemented to help enable the byte count loading. The EBox performs the DATAO to the DTE for this unique operation. Once the word (TO10 byte count) is stored in the E BHOLD register, the DATAO can be removed from ti.e EBus lines and the normal sequencing can continue, as the E-Buffer is not busy with the byte count. A flag in the Data Control register indicates that the Byte Count word was placed in the E B HOLD register. No provision is provided in the DTE20 to allow the EBox to perform DATAI instructions. Thus, the EBox responds with a function code of DATALI only in response to the reception of an appropriate API FCN from the DTE20. If a DATAI DTE is performed, 0 is returned. 2.4 INSTRUCTION IMPLEMENTATION PDP-11 SIDE By executing DATO or DATI instructions from the PDP-11 processor, and giving the appropriate address, all of the previously mentioned available registers in the register block can be accessed. Assume that it is desired for the PDP-11 to ring the EBox doorbell. To accomplish this, the Status register must be addressed via the Unibus address lines A(17:00) as logical register (16) in bits A(04:01). Also, the necessary control lines must be asserted. These include: BBSY - Assume, control of bus C(01:00) - Encoded DATO , MSYN - Tell device address and data if any are present. Bit 08 must be placed on‘the Unibus data lines D(:1£5:00) at the tirhe the Eontrol lines are active. The Instruction and Register Decoder passes bit 08 into the register block to the Status register, where a flip-flop named DPSS REQUEST 10 INT will be set, and generates a level into the interrupt control. Any of the RAM locations can be read in the same manner by executing a DATI instruction from the PDP-11, along with the appropriate RAM address. For example, to read RAM location (13), the following lines are activated: A(17:00) - The address of the desired RAM location BBSY - Assume control of the bus C(01:00) ~ Encoded DATI MSYN - Tell device address is present. DTE/2-5 In response to receiving these control signals, the Instruction and Register Decoder accesses the speci- fied RAM location (13) and places the contents of the Unibus data lines D(15:00) and generates SSYN to terminate the operation. Some time later the PDP-11 detaches from the bus. 2.5 FUNCTIONAL OPERATIONS OVERVIEW BN e This section describes the four basic DTE20 hardware operations: Diagnostic Operations Deposit/Examine TO!11 Transfer/TO10 Transfer Doorbell. The description of each operation includes a flowchart of the various steps and a sirfiplified functional block diagram similar to Figure 2-1. However, only those sections germane to the operation being described are included in the description. 2.5.1 Deposit Overview Each of the four DTE20 operations has a preliminary phase of operation. This is the loading of specific control information, or in some cases data, into the appropriate RAM locations. It is always done before the interface begins any operations. For the Deposit operation, the following words are loaded into the indicated locations in the RAM by the PDP-11 processor: oW N — RAM Address Word Loaded Data Word 3 Data Word 2 Data Word 1 Address Word 1 Address Word 2 For the exact format of these words, refer to Table 1-9. The purpose of the Deposit operation is to take information previously loaded into locations in the DTE RAM, in the form of three 16-bit words, and place them in a desired KL10 memory location. This address is in the form of the two words loaded in the interface. Address Word 1 contains a mode bit (12) that determines whether the operation is Deposit or Examine. If bit 12 is set, the operation is a Deposit and if clear, the operation is Examine. Bits 15-13 and bit 11 control the context of the KL10 address. For a privileged front end, the protection bit (bit 11) can be set by the software to perform an unprotected Deposit. For unprotected Deposits, the address space field (bits 15-13) specifies the type of address. Currently, three types of space may be specified as follows: Bits 15-13 Space 0 1 Executive Process Table Executive Virtual Address Space 4 Physical Address Space Note: See API Function Word. All other codes are reserved for future use by the hardware. DTE/2-6 Address Word 2 contains, in bits 15 through 00, bits 20 through 35 of the KL 10 physical address. The data word is a 36-bit word composed of three words loaded in the interface. Data Word 1 contains bits 00 through 03 of the KL10 data word in PDP-11 bits 03 through 00; the bits are right justified. Data Word 2 contains bits 04 through 19 of the KL10 data word in PDP-11 bits 15 through 00 and Data Word 3 contains bits 20 through 35 of the KL10 data word in PDP-11 bits 15 through 00. Loading the data words has no direct effect on the Interface Control Logic in terms of starting the operation. When Address Word 2 is loaded, the operation begins. Refer to Figure 2-3. Assume that the five words have been previously loaded into the interface. The Data Control register senses the loading of the key word. When Address Word 1 was loaded, the mode bit set a flag in the Data Control register. It is this flag that causes the interface to perform a Deposit, instead of an Examine, operation. When Address Word 2 is loaded, the interface begins the Deposit operation and, therefore, all other locations relating to the Deposit must be loaded prior to loading Address Word 2. Refer to the flow for Deposit. The significant events that occur at various points in the flow are listed on the flow (right side) to highlight the event taking place. All operations that occur in the interface are synchronous with a series of progressive time states. These are listed to the left of the event (or in some cases the events) that occur during that particular state. VAN PI 00 INTERRUPT CONTROL INTERNAL REG BLK €S04-06 ’ €$00-03 _ FOO-o02 INSTRUCTION DEMAND REé:\‘SDTER o [xx] DECODING 2 TRANS w API FCN [rs] - B *ADR WORD2 (5) +——-- bl *DATA WORD1 (3) E | *pata worD3 () D KL-10 SIDE ACKN A ¢ ] ) ADR WORD 1 "DATA WORD2 (4) | | | : (2) | | | I D(f)”loATA CONTROL REG |~ - -=-=-1 ¢ E£-BUFFER DEXADR 2 LOADED, EBUS SEND OP _________ } BEGIN TRANSFER OF ADDRESS 70 E BOX PISERVED INTERFACE CONTROL "DATAT" PIADRIN DATA (36 BITS) [ LOGIC e-surFeR CNT4 TRANS REQ :_ 00—1213—1920———-35_} ' [[apT T a : 00—03 04 ple ! [ ] B ] | 19 20 ——35 | o [ FORMAT e i ' *ROM LOCATIONS 10-1801 Figure 2-3 Deposit Simplified Functional Block Diagram DTE/2-7 2.5.1.1 Deposit Operation - The format of the words used for the Deposit operation are illustrated on Figure 2-5, Deposit and Examine Words; in addition, a functional flow (Figure 2-6, Simplified Flow Deposit) is included. These should be referenced while reading the functional description. The first part of this operation extracts the 22-bit KL 10 address from two RAM locations, ADR Word 1 and ADR Word 2, and places the adjusted address in the E-Buffer (Figure 2-4). - E BUFFER +| 0 35 ADR WORD 1 "L 0AD" ——e ADR WORD ¢ LOCATION 4 b f——RAM FILE ——] 19 20 ADR WORD 1 ADR WORD 2 “SHIFT" "LOoAD" ADR WORD 2 LOCATION 5 *— RAM FILE —+] 10-1802 Figure 2-4 Address Word Setup This is shown on Figure 2-3. The contents of RAM location (4) are read into the E-Buffer (shown in dotted lines). At this time, only what corresponds to bits 14-19 is loaded into the E-Buffer. The event occurs during “CNT 4 DEX ADR 1” time. Next, the contents of RAM location (5) are loaded into the position currently occupied by ADR Word 1. Simultaneously, that portion of the E-Buffer is shifted left. The flow indicates the final position of the address in the E-Buffer. Bits 0 through 03 contain zeros and bits 14 through 35 contain the KL10 physical address. To get this address to the EBox, it is necessary to use the interrupt facility in the interface. The Interface Control Logic generates a CNT 4 TRANS REQ into the interrupt control, which triggers the interrupt dialogue with EBus P100. The Interface Control Logic holds the interface in the “CNT 4 DEX ADR 2” state until the dialogue is at a point where the API FCN word has been taken by the EBox. Refer to Figure 2-7. When the Pl module detects that the interrupt request is true, it sends out a function that polls all devices on the highest interrupting channel to send the physical numbers. On the first interrupt, the PI module detects the highest level interrupt and starts servicing it. Once it determines which devices are interrupting on that channel, it decides which device should be served and sends out a second function: for a given physical controller on a given PI level, send its interrupt function code. The PI module then interrupts the main part of the processor and the processor executes the interrupt function code. DTE/2-8 DEPOSIT OR EXAMINE WORD 1 15 14 13 12 11 10 09 o8 07 06 05 04 03 02 00 02 03 L= J KL -10 DATA BIT POSITION DEPOSIT OR EXAMINE WORD 2 XXX04 15 14 13 12 11 10 04 | 05 |06 | O7T | 08 | 09 | 09 08 07 06 05 04 03 02 01 00 10 11 12 13 14 15 16 17 18 19 \ - KL—10 DATA DEPOSIT OR 15 XXX02 20 | EXAMINE WORD 14 13 12 11 21 22 23 24 BIT POSITION 3 10 | 25 09 o088 07 06 26 27 28 29 KL-10 DATA | | 05 04 30 | 13 03 | 32 | 02 01 33 34 00 | 35 AN J TEN ADDRESS 15 14 13 ADR SPACE XXX10 12 1 M 10 - P 07 ©06 05 04 03 02 ©01 00 //%Z/ 13 1 14 | 15 | 16 17 18 19 . ) - J KL -10 ADDRESS BITS 1= OFF 0= 0N 1- EXECVIRTUAL 4- PHYSICAL MODE 2-3-RESERVED 1= DEPOSIT [kL-10] 5-7-RESERVED 0= EXAMINE [KL-10] ADDRESS | 08 7 PROTECT 0- EPT 20 09 7 , L 15 POSITION WORD 1 ADDRESS SPACE TEN BIT WORD 2 ’ 14 13 12 11 2t 22 23 | 24 10 | 25 | 09 08 26 | 27 07 | 28 06 | 29 05 | 30 | 04 03 31 32 « 02 | 33 0% | 34 00 | 35 J KL-10 ADDRESS BIT 10-1803 Figure 2-5 Deposit and Examine Words DTE/2-9 START READ KL-10 ADDRESS BITS “CNT4 DEX ADR 1" E-BUFFER 20-35- (LOCATION 4) (LOCATION &) 1419 iINTO E BUFFER FROM RAM SHIFT E-BUFFER “CNT4 DEX ADR 2" LEFT AND LOAD BITS 20-35 INTO E BUFFER FROM RAM “CNT4 TRANS REQ" [ 20-35 E-BUFFER 20-35- (LOCATION 5} 0304 19 20 35 o GENERATE EBOX INTERRUPT (PI00] 4 “F00-02 - €S00-06 T “CLOCK INHIBITED” E-BUFFER 14-19- - DEMAND GENERATE BUS DIALOGUE DIXX} *PI SERVED *PI ADR IN N AP§ FCN ACKN - TRANSFER API FCN XMIT TO EBOX; CONTAINS 23 BIT KL10 ADDRF€SS IN BITS PASS INTO NEXT STATE CLKS DEX WD1 P~ a W 13.35 EBOX TAKES API “CLOCK STARTS FCN INTERFACE ONCE AGAIN" WILL SUPPLY 36 - DEMAND DECODED - DATAI WAITING b1 BIT DATA WORD F00-02 CS00—-06 v I E BUFFER 2035 - LOAD E BUFFER “CNT4 DEX WD1” FROM LOCATION 3 00 32 19 20 03 04 35 FROM RAM = BITS 00-03 I SHIFT E-BUFFER “CNT4 DEX wWD2" LEFT AND LOAD BITS 04-19 INTO 20-35 00 03 04 19 20 35 W b)] EBUFF FROM RAM E BUFFER 04-19 - E BUFFER 20--35 -- LOCATION 2 Y r E BUFFER 00—-03 -- 04--19 “CNT4 DEX WD3” SHIFT E-BUFFER E BUFFER 0419 - 20-35 LEFT AND LOAD E BUFFER 20-35 ~ (LOCATION 1) BITS 20-35 INTO E-BUFF FROM | GENERATE TRANSFER NOTE: THE DATAI AND DEMAND WERE PRESENT FROM SOME TIME AFTER THE E-BOX STROBED THE APl FCN. 00 03 04 ‘OO—OJI 19 20 04-19 35 20-35 l EBOX HELD UP AND IS WAITING FOR TRANSFER AND 36 BIT DATA WORD ACKN |, TRANSFER — - E-BOX DROPS DEMAND END 10-1804 Figure 2-6 Simplified Flow Diagram DTE/2-10 CONTROL E BOX ACTIVITY DTE 20 /—/H /_/H INTERNAL PRIORITY DTE 20 INTERRUPT INTERNAL 'L;)LGE'C PROCESSING IDLE E-BOX foe—ee OTHER DEV X CH = WITHANY g ARBITRATES he—— e OTHERDEV Y SENSE OTHER INCOMING INTERRUPT CH *= J#——— GENERATE Pi |asserTEDBY l IWISH TO XFER DTE 20 ABYTE] P PI'S - ALERT HAND SHAKE J@— THIS AND TRANSMIT DEV [DTE 20) PI SERVED -— i ee Ay le— DEMAND © “FUNCT 4" 70 OTHER DEVS E-BOX ARBITRATES TELL —®] DTE 20 DEMAND DTE 20DETECTS * PI SERVED AND ND — TRANSMITS ITS PHYSICAL PHYSICAL ASSERT b—- = TQ E-BUS ——~—g PHYSICAL SENSE CONTROLLER = PHYS = ——aqg»| CONTROLLER CONTROLLER = WITH ANY OTHER INCOMING =S. ONLY ONE OF THESE WILL BE SELECTED. AP FCN 10— BUS DTE 20 DETECTS THAT IT HAS BEEN SELECTED ACK g TELL DTE 20 AND GENERATES APl FUNCTION ] GRANT ASSERT SELECTED = CS 00-03 AS |IDTE-20 ONLY] —_] SELECTED = ——DEMAND j—— DEMAND XFER ACK: TELLS I/O BUS ADAPTER NOT TO RESPOND 36 BIT API ;FBL(;X *] FUNCTION TELLS E-BOX WHAT TO esox evaLuates f—runctoatar —e ecponse 1s* F—“FuncT baTar API FUNCTION AND ABYTE OF ACK ————g»} :AKES THE APPRO- Do XFER — DEMAND—— | RIATE ACTION, T IN THIS EXAMPLE TAKES A BYTE FROM E-BUS. < DATA | bemann BYTE FROM——‘ BYTE E.BUS ! PASSES FROM DTE 20 DTE 20 PLACES EBUFFER ONTO E-BUS THEN RELEASES E-BOX * n—xren—-—J IDLE ACCEPTS BYTE OF DATA ACK f—-—~——— PRIORITY INTERRUPT | XFER LOGIC IDLE INTERNAL le———— acx DTE 20 INTERNAL PROC 10-1612 Figure 2-7 Interrupt Dialogue Overview DTE/2-11 Upon detecting DEMAND for the second time with P ADR IN, the DTE20 places the API FCN on the EBus data lines D(00:35) and asserts ACKNOWLEDGE and TRANSFER to the EBox. The API FCN contains the information indicated on Figure 1-1. The function code in bits 3-5 specifies the type of service required and bit 6 specifies whether protection and relocation should be put in effect. At this time, two events are happening: the DTE20 is passing into the next state to set up the 36-bit data word in the E-Buffer to pass along to the EBox, and the EBox is preparing to implement a DATAI instruction in the microcode. The EBox asserts F(00:02) as DATAI, CS(00:06) as selecting the DTE20 and asserts DEMAND. The EBox must now wait until the DTE20 generates ACKNOWLEDGE and TRANSFER before it can detach from the EBus. The interface reads the word from RAM location 3 into the E-Buffer, refers to the flow at “CNT 4 DEX WD1”, and enters the next state “CNT 4 DEX WD 2”. The second part of the data word bits 04-19 is now read from RAM location 2 and loaded into the E-Buffer and simultaneously the E-Buffer is shifted left adjusting the words (Figure 2-8). 19 35 20 DATA WORD 1 "SHIFT" 19 "LOAD" 35 20 "SHIFT 19 T "SHIFT" LOCATION 3 T TL2 "LOAD" o DATA WORD2 35 20 DATA WORD 3 DATA WORD 2 DATA WORD 1 DATA WORD 1 7 DATA WORD 2 DATAWORD 1 |—= "SHIFT" L 1 LOCATION 2 g’ 1 "LOAD" = DATA WORD 3 3 LOCATION 1 7 10-180% Figure 2-8 Deposit Data Word Setup Referring to Figures 2-9 through 2-12 and the flow (Figure 2-13), bits 16-19 of the E-Buffer contain ‘ bits 00-03 of the previously loaded data word, and bits 20-35 of the E-Buffer contain bits 04-19 of the data ward. : The DTE20 now passes into the final state of the Deposit operation “CNT 4 DEX WD 3” and loads the E-Buffer from RAM location 1 while shifting the E-Buffer left once again. At this point, the EBuffer contains the entire 36-bit data word and this is placed onto the EBus. The DTE20 asserts ACKNOWLEDGE and TRANSFER and some time later the EBox drops DEMAND. For parity computation, see Section 3. DTE/2-12 1) USING ADR SUPPLIED WRITE DATA 1} USING ADR 1) READ OUT SUPPLIED LESS 8O0TH BIT 00, WRITE PARTS OF SUPPLIED INTO RAM DATA SUPPLIED INTO PROCESSING 4) READ OUT THREE PARTS OF DATA TO BE KL-10 ADR SERVICE FROM RAM ., o cc tie RAM LOCATIONS [41AND[S] -~ DTE20 2) CALL KL-10 FOR kY =) F98 THE 75 kL0 DEPOSITED AND PASS TO KL-10 fe-SETS UP DATA-+] 7, ¢ / RAM OPERATION #1 REQ OPERATION #2 ) . TRANSFER \ / 4 RAM 3 7 TAKES = TRANSMIT ADR DATA L L T INTERRUPT d KL-10 — Y/ WAITING / te—- PAGE CK OPERATION DONE () DEX / 7'/,’/ // //' % /“ DONE LSS C { 3 DATO OR DATI FROM ) Y * RAM (See note 2) N DATO TO DEX ADR 1 DATO TO DEX ADR (4] [s] DATA WILL GO 0 . MEMORY NOTES: 1. KL-10< Under program control 2. Assume DEX DATA WORDS 1,23 were previousiy written into RAM ¢\ OB kL-10 | 2 YlsSLA DATA |04 20 [20 1 pau 00-03}3 DATA 19)2 DATA 35| 1 VA by DATO'S 19]4 35]s 10-1806 Figure 2-9 Deposit Operation Including Address Setup DTE/2-13 PIOD INTERRUPT CONTROL €504-06 FPO-02 INSTRUCTION DEMAND REGISTER DECODING AND o [ 20X] ; A |, | KL-10 ACKN FCN SIDE __________ & *ADR WORD 1 (4) 8 Z | TRaNs API P p CSeP-03 BUFFER __________ *ADR WORD 2 (51| —————coc . c * (3) : 0 *DATA WORD 2 (2} I 3 - i DATA WORD 1t : | DATA WORD 3 (1) | E BUS ) SEND — op DATAO DATA (36 BITS) E'_‘] £ BUFFER 5 [ ! X 1 T : oep I | DATARE%NTROL ! ;l PI DEX ADR2 LOADED, BEGIN SERVED Meormar ORMAT . 00 I c — 13 14 API | 00 0304 I INTERFACE PI ADR IN | v CONTROL LOGIC TRANSFER CNT4 | OF ADDRESS TO EBOX [ —————-——— -~~~ ="e 0 TRANS REQ - TM 19 20 ; . 35 | A D ] B 1920 3 I 35 ' I | —————————— —— ————————————_1 *RAM LOCATIONS 10-1807 Figure 2-10 Examine Simplified Functional Block Diagram DTE/2-14 0 3 CNT2 EBUFF CLK CNT6 4 l EBUFF SEL (1) 19 20 l 35| E BUFFER ] 0 1 0 I 1_'6-19 l 1 0 20-35 ADR 1 ’ 15-00 08 07 ADR seace WORD 1o ADR WORD 2 ——+ 00 KL1O ADR BITS 13-19 |M|P f RAM KL!O ADDRESS BITS 20-35 I ____________ m FILE D l — ) = P % 10-1808 Figure 2-11 1) USING ADR 1)USING ADR Loading the E-Buffer (Examine) 1) READOUT BOTH 3) MUST WAIT 5) RECEIVE DATA SUPPLIED SUPPLIED PARTS OF KL-10 FOR DATA FROM KL-10 LESS LESS BIT 00, ADR FROM RAM FROM 10 SO RELEASE 10 WRITE DATA WRITE DATA LOCATIONS SUPPLIED INTO RAM SUPPLIED INTO RAM AND [5} BIT 00, [4] MEMORY AND STORE IN THREE PARTS IN RAM 4) WAITING 2)CALL KL-10 FOR SERVICE DTE20 PROCESSING IR S ;,////,/ &RAM OPERATION #1 S REQ RAM OPERATION #2 TRANSFER — KL-10 g LSS, I 4 TAKES N TRANSMITS "ApR DATA Iy N //// LSS, & ACCESSES DONE 1 DEX DONE — OPERATION KL-10 MEMORY ¢ S S S I p1 C 1) PDP11 READS THE DATA IN THREE DATI'S * DATO OR (l DATI TOOR FROM RAM 7 I (‘( ; L g DATO TO DATO TO DATI FROM ' {77/ ’ DEX ADR 1 DEX ADR 2 {41 151 15 * = UNDER PROGRAM CONTROL RAM 00 DATA WORD| WILL GO HERE |3 NOTES: SUPPLIED FROM } |DATA WORD 2 WILL GO HERE |2 RAM operation =1 - write the equ-valfzn( KL-10 MEMORY DATA WORD 3 WILL GO HERE |1 DATA of KL T0 ABR 14 -19 into RAM jocation {4) as supplied by DATO WILL BE ADR SENT TO KL-10 ) 5 (‘(‘ N DATI FROM - o L i DATI FROM DEX DATA WD1 DEX DATAWD2 DEX DATAWD3 tn 121 3 AM—— 19| 4 20 vy RAM operation #2 - write the equivatent of KL-10 ADR 20--35 into RAM location (5] as supplied by DATO 10 - 1809 Figure 2-12 Examine Operation Including Address Setup DTE/2-15 START “CNT4 DEX ADR1" READ KL 10 E BUFFER - ADDRESS BITS 20-35- 13-19INTO € BUFFER {LOCATION 4) € BUFFER CON- (LOCATION 4} 00 03 TAINS 36 BIT 04 19 20 35 FROM RAM “CNT4 DEX WD1” € BUFF 00-03 00 03 - (LOCATION 3) 04 19 20 35 DATA WORD FROM KL-10 00-03 MEMORY STORE 1319 E-BUFFER 00-03 INTO RAM SHIFT E BUFFER LEFY AND LOAD “CNT4 DEX ADR2” B8ITS 20-35 INTO E BUFFER FROM E BUFFER04-19- 20-35 £ BUFFER 20-35- (LOCATION 5} 00 03 04 19 RAM LOC 3 L 35 20 RAM 04-19 20-35 “CNT4 DEX WD2" GENERATE EBOX “CNT4 TRANSREQ" STORE E BUFFER 04-19 INTO RAM AND SHIFT LEFT 04-19- INTERRUPT 20-35 E BUFFER (4-19 (LOCATION 2) E BUFFER 041920-35 04 (P100] 19 20 35 04-19 RAM LOC 2 “CLOCK INHIBITED"” GENERATE BUS DIALOGUE *F 00-02 - CS 00-06 ~ I L DIXX} *PI SERVED 00 *PI ADR IN L A T T T DEMAND 03 04 19 20 35 APl FCN - 20-35 ACKN TRANSFER API FCN XMIT TO EBOX CON “SHIFT LEFT" - TAINS 238IT KL-10 ADDRESS INBITS 12-35 ) T EBOX TAKES AP{ “CLOCK STARTS ONCE AGAIN" FCN WILL SUPPLY TO INTERFACE 36 BIT DATA WORD 19 04 “CNT4 DEX WD3" F 00-02 - CS 00-06 - DEMAND - STORE E BUFFER 20-35 04-19 INTO RAM <.DECODED DATAO > END lid n T 7 RAM LOC 1 101810 Figure 2-13 Simplified Flow Examine DTE/2-16 2.5.2 Examine Overview The preliminary phase for the Examine operation is as follows. The PDP-11 processor loads the fol- lowing locations in the RAM: RAM Address Word Loaded 4 Address Word 1 5 Address Word 2 For the exact format of these words, see Table 1-9. The purpose of the Examine operation is to take information from KL10 memory in the form of one 36-bit word and place this information, in the form of three 16-bit words, into a specific PDP-11 memory location. The address is as with the Deposit operation, in the form of two words loaded into RAM locations in the interface. Address Word | and Address Word 2 are in the same format as for Deposit, the only exception being that the mode bit is not set. This indicates that the operation to be performed is not a Deposit, but rather an Examine. Because the EBox will produce the data word, nothing is loaded into RAM locations 1, 2, and 3 as with the Deposit operation. The interface begins the operation when it detects the loading of Address Word 2. 2.5.2.1 Examine Operation - The format of the words used for the Examine operation is illustrated on Figure 2-12, Examine Operation Including Setup of ADR. In addition, a functional flow Figure 213, Simplified Flow Examine, is included. These should be referenced while reading the functional description. ’ ' ' The first part of this operation extracts the 36-bit API word from two RAM locations (ADR Word 1 and ADR Word 2) and places the adjusted word in the E-Buffer. N NOTE See Figure 1-9 for exact format. This is shown in Figure 2-11. The contents of RAM location (4) are read into the E-Buffer (shown in dotted lines). At this time only what corresponds to bits 14-19 is loaded into the E-Buffer. The event occurs during “CNT 4 DEX ADR 1” time. Next, the contents of RAM location (5) are loaded into the position currently occupied by ADR Word | and simultaneously that portion of the E-Buffer is shifted left. The flow indicates the final position of the address in the E-Buffer. Bits 0 through 13 contain zeros and bits 14 through 35 contain the KL 10 virtual address. To get this address to the EBox, the interface interrupt facility is used. The Interface Control Logic generates a CNT 4 TRANS REQ into the interrupt control, which triggers the interrupt dialogue by asserting PI00. The Interface Control Logic holds the interface in the “CNT 4 DEX ADR 2” state until the dialogue is at a point where the API FCN has been taken by the EBox. When the bus dialogue begins, the interface asserts PI00 as the interrupting line. In response, the EBox arbitrates the line with any others it samples and responds to the highest. Assuming the DTE20 to be the one, the EBox asserts F(00:02) as PI Served, CS(04:06) as the interrupting channel, and finally asserts DEMAND. The DTE20 compares its channel to the one asserted and finding it the same, asserts (DX ) the physical controller number (for the DTE20). Once again, upon receiving the phys- ical controller numbers from those candidates selected by channel number, the EBox arbitrates among the physical numbers and selects the DTE20 as highest priority (lowest weighted value). The EBox asserts F(00:02) as P1 ADR IN, CS(04:06) as the interrupting channel, CS(00:03) as physical controller to be honored, and finally asserts DEMAND. DTE/2-17 Upon detecting DEMAND for the second time with PI ADR IN, the DTE20 places the appropriate API FCN on the EBus data lines D(00:35) and asserts ACKNOWLEDGE and TRANSFER to the EBox. The API FCN contains the 23-bit address for the EBox, as well as information telling the EBox which interface is talking to it, and a function code in bits 03-05 that effectively tells the EBox how to respond (i.e., with a DATAO or DATALI). In the case of an Examine operation, the EBox reads a 36- bit word from KL10 memory and executes a DATAQ using the microcode. The result is that the 36-bit word is placed on the EBus data lines D(00:35) and loaded into the E-Buffer (Figure 2-14). The DTE20 detects this event and asserts ACKNOWLEDGE and TRANSFER. o] 3 4 | CNT2 EBUFF CLK | 19 20 1 CNT6 EBUFF SEL (O) 7/_ 0 1 W 0 t € BUS <o } ! W i 314 35 | € BUFFER 0 1 ‘ f 19120 \ 35> 10-1811 Figure 2-14 E-Buffer Loaded from the EBus The interface enters the “CNT 4 DEX WD 1” state where the E-Buffer begins to be disassembled and written into the RAM. E-Buffer bits 00-03 are written into RAM location 1 and the next state is entered. During “CNT 4 DEX WD 27, the E-Buffer bits 04-19 are written into RAM location 2 and the E-Bufferis shifted left so that the next portion of the word will be positioned for writing. The last state is entered, “CNT 4 DEX WD 3” and the E-Buffer bits 04-19, which contain bits 20-35 of the Data word, are written into RAM location 3. This terminates the Examine operation. 2.5.3 TO11 Transfer Overview The preliminary phase for the TO11 transfer is as follows: the PDP-11 processor loads the following locations in the RAM: RAM Address 0 7 11 Word Loaded DLY Count TO11 Byte Count TO11 PDP-11 Address Bit 13 of the TO11 Byte Count word controls whether the DTE is in byte mode or word mode. When bit 13 is set, the DTE is in byte mode; when clear, the DTE is in word mode. If the DTE is in byte mode, transfers on the PDP-11 side are 8 bits long, while word mode transfers on the PDP-11 side are 16 bits long. Once bit 13 selects byte or word mode operation, the bit is written into the RAM and into a Control flip-flop. The bit written into the RAM is used only when the Byte Count word is read. Therefore, only the state of the last write operation is seen. This controls the positioning of the incoming byte in the RAM, which acts as a temporary buffer for the byte. The byte is always placed on the EBus in bits 28-35 for TO11 byte mode transfers. DTE/2-18 The DTE writes into the first location specified in the TO11 address. Refer to Figures 2-15 through 217. The byte in EBus bits 28-35 is stored into bits 07-00 of the RAM on the first transfer. From there, it is passed over the Unibus (on bits 07-00) and is stored in PDP-11 memory. Before each succeeding transfer, both the TO11 address and the byte count are incremented. The byte count holds a negative number equal to the number of bytes to be transferred. Actually the byte count is read, tested (for a field equal to zero), and then incremented. Again, a byte of data is placed onto the EBus in bits 28-35 by the EBox. This time, however, the byte is stored in bits 15-08 of the RAM. The TO11 address and byte count are incremented and the succeeding byte of data is transferred. The transfers continue until the byte count increments to zero. The byte count test for zero is performed before a data transfer, so an extra cycle is started after the last transfer of a particular transfer sequence. When the byte count is read and tested for zero, and the field is zero, the cycle is aborted. Then, the TO11 Done flag sets, which causes an interrupt to the PDP-11: optionally, the EBox can also be interrupted. When bit 13 of the Byte Count word is a zero, the DTE is in word mode. Information is placed on the EBus by the EBox in bits 20-35 and is stored in the RAM in bits 15-00. From there, it is passed to PDP11 memory over Unibus bits 15-00. When in word mode, the DTE writes into consecutive PDP-11 memory words, all of which are even locations. Writing is done in every PDP-11 word, as opposed to every PDP-11 byte (byte mode). After each transfer, the TO11 address is incremented twice. This updates the address for the next transfer and transfers continue until the byte count reaches zero. Two special provisions are furnished in the Byte Count word: one is to allow transfer termination upon detection of a NULL character during the transfer. This causes an interrupt to the PDP-11 processor, provided that bit 14 of the TO11 Byte Count word is set prior to beginning the transfer. The second provision (I bit; bit 15 of the TO11 Byte Count word) allows the receiver of data (only) the option of being interrupted. So, without reloading all of the parameters, another transfer can be started just by changing the address. The transfer in progress continues from the new address. In general, transfers are of the single-block type and the I bit is always set. Occasionally, multipleblock transfers (e.g., TO10) are implemented, resulting in more than one transfer. The last transfer, in such a case, always sets the I bit. Therefore, both the KL10 side and PDP-11 side recognize a Done Interrupt and, relative to the software, stay synchronized, believing the transfer is done. If the I bit is set, both the TO11 address and the TO11 Byte Count word must be reloaded. If it is not set, just the TO11 Byte Count word must be reloaded. The high order PDP-11 address bits (16-17) are controlled by the delay count. Therefore, the high order bits of the Delay Count word are bits 16-17 of the address space. All transfers are constrained to being in the same 32K space, but they can operate in a greater than 32K core machine; hence, the 18 bits worth of addressing. Similar to the TO11 Byte Count word, the TO11 Delay Count word holds a negative number. The DTE increments the word (toward zero) prior to any transfer of data. When bit 13 of the Delay Count word equals zero, the transfer begins. The net effect is to force the DTE to pause before starting each transfer, eliminating bursts of interrupts. During the transfers, R AM location (13) is used as a tempo- rary buffer for the data (byte or word) being transferred. The transfer from RAM location (13) is via the NPR facility to PDP-11 memory. DTE/2-19 RAM FILE |5 ’J BYTE MODE FLAG CONTROLS POSITIONING | OF BYTE IN SET WHEN TOH ABC 1S LOADED RAM RAM FILE BYTE XX1 1 XX0 T NOTE: Initial TO11 Address = XX1 DTE utilizes bit 13 of the TO11 byte count word, as a byte mode flag. 10-1812 Figure 2-15 TOI11 Byte Mode DTE/2-20 STATUS AND S TERBURY TRANSFER KL-10 INT REQ CONTROL 3 INT - LOGIC PG DONE INT REQ INT BR LOGIC DONE o PDP-11 INT REQ IF 1BIT SET REQ KL-10 INT ALSO A{17:00> ABC LOAD FOg-g2 DEMAND £ |«TRANS B D[XX] g ABC BIT13 DECOF..!3 ; o C T T T T T T DATA BYTE BUFFER ADR 567 API 9 [Fcn|@ 13 D 35 DLY COUNT (0) TO11 BYTE (7) TO1! ADDRESS (n TO11 DA TA (13) CNT BBSY PDP-11 MSYN SIDE . SSYN COUNT "paTO" BYTE CONDS DATA Z SACK AND REGISTER DECODING D<I5:00) NPR CONTROL / NPG c<1:0> TO11 TON BT%I}E BG INSTR ggr‘q’E STATUS DATAO 023 ( SET E BUFFER E - j j -~ KL-10 SIDE (36 BITS) ! le— ABC +1 ABC REGISTER AP1 FCN INTERNAL REG | [N] l INSTEL&%TION ACKN ] nCcw—2cC CS@PP-06 "REQ" LOCK MAJOR STATE NPR LOGIC NPR " le—— ABC =0 INTERFACE CONTROL “JAM API FCN" LOGIC RAM LOC13:=¢ , (IF NULL CHAR) EXT CLK N\ N NOTE PI board in E BOX supplies EPT address from selected DTE 0,1,2, or 3. 10-1813 Figure 2-16 TO11 Transfer Simplified Functional Block Diagram DTE/2-21 DELAY COUNT * XXX 00 15 14 2|5 2|4 00 2!3 2!2 FAY 2|0 29 28 27 26 2% 24 23 22 21 20 37777=NO DELAY ~N=DELAY of N X 500ns TOt1 BYTE COUNT Xxx 16} 15 14 13 I z 8 00 2" 210 2% 28 27 28 25 24 23 22 2! 20 NEGATIVE BYTE COUNT | P=WORD MODE 1:BYTE MODE 1=STOP ON A NULL @-NO EFFECT 1=SET TO11 DONE AND INTERRUPT BOTH THE PDP-i1 AND KL1O @=SET TO11 DONE AND INTERRUPT ONLY PDP-11 TO11 PDP-11 ADDRESS 15 XXX 22 00 215 214 213 2|2 -3 210 29 28 27 PDP-11 ADDRESS 26 25 24 23 22 2t B @=1BYTE/WORD 1= 2 BYTE/WORD TO11 DATA 15 00 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 20 | 21 | | 23 | 24 | | 26 | 27 e oE BN it SRR B B 22 25 28 | 29 | 30 [ 31 | 32 | 33 | 34 | 35 v KL-10 BIT POSITION KL-10 BIT POSITION LOW ORDER BYTE UPPER =2 BYTES/WORD LOWER=1 BYTE WORD %:= UNIBUS ADDRESS BITS 17-16. SPECIFIES HIGH ORDER 2 BITS OF 18-BIT PDP - 11 ADDRESS USED IN 18-BIT BYTE TRANSFER ADDRESSES. 10 - 1814 Figure 2-17 TOII1 Transfer Words DTE/2-22 EBus parity is sent with the data on TO1!l transfers. The parity computation is performed on the output of data written to the RAM. Therefore, if no parity error is indicated, the data was written into the RAM correctly (excluding double bit failures). This is because the parity is checked after the write strobe occurs and the output has changed on the RAM, reflecting the data written into the cells. If a byte pointer of larger than 16 bits is used (on the KL10 side), that portion of the byte greater than 16 bits is stripped off the byte (does not get into the RAM), causing erroneous parity errors. A software restriction specifies a 16-bit byte pointer maximum size; this permits 16-bit byte pointers to be used safely on all TO11 transfers. 2.5.3.1 TO11 Transfer Operation - The format of the words used for the transfer operation is illustrated on Figure 2-18, TO11 Transfer. In addition, a functional flow, Figure 2-19, Simplified Flow TO11 Transfer, is included. Reference these while reading the functional description. The first part of the operation is to read the TO11 Delay Count from RAM location (0) and load it into the Address and Byte Count (ABC) register. Here again, the high order address bits (16-17) are read out of the RAM and put into the address bits (on the data path module) for Unibus bits 16-17. The next flow state is CNT4 TO11 DLY INC. This state is maintained until the high order bit is incremented to zero; when this first occurs, the entire word becomes zero. Next, the TO11 Byte Count must be read from RAM locaton (7) into the ABC register and tested for a zero field. If the register iszero, the transfer terminates and an interrupt is given to the PDP-11 processor. If the ABC register field is non-zero, the CNT4 TO11 BYTE COUNT INC state is entered, which increments the ABC register by 1. The flow proceeds to a point where the updated byte count is written back into RAM location (7). Note that, referring to the flow, the content of ABC goes to the RAM (7). At this time, a byte of data is required from the EBox, so the DTE enters the CNT4 TO11 1/O FCN state. This initiates an EBus dialogue, which results in the byte of data being fetched and placed into the E-Buffer. A new KL10 API function is used to perform TO10 and TO11 transfers. It differs from the API function used in DEX operation. In the Examine operation, the function contained an address, as well as information about which DTE was interrupting and a function code. In the case ofa TO11 transfer, the data address for use on the KL10 side is contained in a byte pointer (in KL10 core) and is not supplied by the DTE exclusively on the interrupt function. However, the fact that a TO11 transfer is in progress and requires a byte of data must be conveyed to the EBox. A combination of the function code and the Q-bit indicates to the EBox the required service type. A function code of 6 (in bits 03-05) specifies a byte transfer operation. If Q=0, a TO11 byte transfer is specified; Q=1 specifies a TO10 byte transfer. At this time, the byte of data is in the E-Buffer. The flow enters the next state: CNT4 TO11 SHIFT, where the byte of data is adjusted for storage in the RAM. The rightmost E-Buffer bits do not have a direct data path available to the RAM; therefore, the byte must be shifted. The shift is performed during the TO11 address read operation from the RAM; no extra time is required to perform the shift. Referring to the flow, RAM location (11) is addressed and the ABC register is loaded with its contents, the TO11 address. During this period, the E-Buffer is also shifted. It is shifted left, placing the byte that was in bits 20-35 into bits 04-19. This is the normal position for writing into the RAM from the EBuffer. When writing into the high order bits in the PDP-11 (in byte mode), the two halves of the 16-bit word are swapped. During PDP-11 Unibus data operations, the transmitter of data (on byte operations) is responsible for putting bytes in the correct word halves, and should be thought of as putting *‘this half on that half, not this byte on that byte.” On the KL 10 side, a byte is generally right justified and the processor hardware takes care of all swapping. Bytes are thought of as being right justified. The PDP11 recognizes left and right bytes. But all bytes from the K110, because it uses byte pointers, come over DTE/2-23 right justified. So when an 8-bit byte is transferred, it is right justified and would appear so in PDP-11 memory. Yet byte modes operate ‘“‘right half, left half, etc.” If a destination is a left half, for example, the word halves must be swapped. This is one reason the TO11 address is read prior to writing the data into the RAM. The destination address must be known before the data can be written into the RAM. This takes care of the swapping. The result is that a single byte is now positioned in bits 15-08 on the input to location (13}, the TO11 data slot in the RAM. The adjusted byte is written during CNT4 TO11 EBUFF STORE. The DTE performs a standard PDP-11 NPR transfer to the data location. The Unibus dialogue begins. Refer to the PDP-11 Peripherals Handbook (EB 05961 76), Chapter 5 and Appendices A through D, for a complete description of the Unibus dialogue and a summary of Unibus addresses, miscellaneous data, and instructions. 1.)DLY CNT INC UNTIL BIT13:=0 2) CHECK BYTE COUNT ;%FEJ‘;:?“[()NTATE; TERMINATE INC BY1 1.)STORE BYTE IN RAM TEMPORARY STORAGE 1.) DLY CNT INC UNTIL BIT 13:0 2.) SETUP 11 ADR AND UPDATE 3)CALL E-BOX FOR SERVICE 2.) BYTE CNT INC BY 1 AND 3)CALL FOR BUS IF BYTE IS NULL AND NULL STOP {1) TERMINATE NOW NOW=0 TERMINATE BY 8Y INTERRUPTING PDP-11% REQ BYTE NEXT OPERATION ) NEXT OPERATION RECEIVE BYTE BYTE COUNT: O [TERMINATE] INTERRUPT \ KL-10 r WRITE BYTE WRITE BYTE ¢ 7 MEMORY \ NPR TO 11 ////% r INTERRUPT 11 S W////////A DLY CNT 9 o P~ TO 11 BYTE COUNT TO 11 PDP 11 ADR interrupt 10. Py ’r t - o 1t I fiog (1) can also .If TO 7 o o~ FROM KL-‘IO—. | [¢] 9 RAM TO PDP-1 13 e— MEMORY DATA WILL PASS THRU HERE L T 10-1818 Figure 2-18 ’11'01'1 Transfer DTE/2-24 - START *F00-02 - READ DELAY “CNT 4 TO11 DLY RD” CS00-06 — EBOX PLACES {LOCATION 0} — ABC COUNT INTO <E-BUFFER -~ BUS> ABC DEMAND — BYTE OF DATA D{0:35} ~ ON EBUS — ACKN — TRANSFER *DATAO READ TOMN INCREMENT DLY “CNT4 TO11 DLY INC” ABC+1 —~ ABC CNT BY 1 “CNT4 TO11 SHIFT"” ADDRESS INTO ABC, SHIFT E BUFF DATA LEFT {LOCATION 11) — ABC £ BUF 20-35 — 04-19 POSITION FOR WRITING INTO RAM LOCATION 13 ABC (B) =0 ABC=0 "“CNT4 TO11 BC RD" ? ABC=+ 0 WRITE THE BYTE READ BYTE “CNT4 TO11 E BUFF STORE" COUNT INTO ABC {LOCATION 7} -- ABC NECESSARY — LOCATION 13 I ABC REGISTER # 0 YES SWAP 15-08 -~ 07-00 SWAPPED IF NECESSARY)} *BYTE COUNT FIELD IN ABC REGISTER =0 TO11BY (1): INTO RAM LOC 13 ADJUSTED AS NO READ DATA BYTE “CNT4 TO11 FL RD” FROM RAM LOC 13 INTO UB MIXERS GENERATE NPR TERMINATE A-117:00 ~ — ABC 0<16:00~ - RAM LOC 13 NPR — NPG - BBSY TRANSFER GENERATE NPR SACK - MSYN - SSYN - DIALOGUE “NULL <. SET TO11 DONE INCREMENT BYTE - COUNT BY 1 : IF TO11 1 BIT (1) SET TO10 DONE, AND GENERATE INTERRUPT STORE UPDATED TO EBOX IN EITHER CASE ABC+1 - ABC {ABC) - LOCATION 7 RAM FILE MIXERS (RFM) BYTE COUNT IN SETTING TO11 DONE GENERATES NO =0 RAM A PDP-11 INTERRUPT I cKx* “CNT4 TO11 BC INCTM ] DURING NPR ABC IGENERATE PI00 INTERRUPT TO EBOX *F00-02 - CS00-06 - DEMAND D[XX] -~ *PI SERVED *P1 ADR IN “CNT4 TRANS REQ” NULL STOP BIT : APY-FCN XMIT MEMORY INCREMENT TO1? ADDRESS BY 1 : TO EBOX DATA WRITTEN : GENERATE BUS AP| FCN - D<15:00~ — RAM LOC 13 C<1:0~ DATO TO POP-11 MUST BE CHECKED DIALOGUE ACKN - A~ 17:00TM -- ABC ADDRESSING PDP-11 MEMORY & ABC + 1— ABC FOR EITHER BYTE OR WORD MODE : TRANSFER -- “CNT4TO11 IF WORD MODE “ONLY IF WORD ADDRESS AGAIN MODE" “CNT4 TON STORE UPDATED I TERMINATE THE TRANSFER : ABC + 1 — ABC INCREMENT TO11 ADR ADD"” ADR INC” TO11 ADDRESS IN RAM {ABC) —~ LOCATION 11 SET TO11 DONE GENERATE POP-11 “BRTM *EFFECTIVELY CONTINUE WITH OPERATION 10-1816 Figure 2-19 Simplified Flow TO11 Transfers DTE/2-25 In addition to the NPR transfer, another mode of operation is possible: terminate transfer on NULL character. The NULL STOP flag must be set to accommodate this transfer. When the NULL charac- ter is read (on NULL STOP), the data transfer occurs. A zero word is written into core, the transfer takes place and then the operation terminates. The TO11 address in the DTE is not incremented. It must be loaded, however. If another byte count is loaded, to continue the transfer after the NULL character, the NULL character is overridden. This mode does not dispose of the normal NPR transfer; the NPR transfer still takes place on the NULL character. The final state is CNT4 TO11 ADR INC. In byte mode, the address is incremented (in the ABC register) upon the return from the NPR transfer. In word mode, the address must be incremented twice. Once the ABC register is updated with the new address, the operation ends. 2.5.4 TOI10 Transfer Overview The preliminary phase for the TO10 transfer is as follows, the PDP-11 processor loads the following locations in the RAM: . RAM Address Word Loaded 0 10 TO10DLY Count TO10 PDP-11 Address The KL 10 program loads the following location in the RAM: 6 TO10 Byte Count In general, the TO10 transfer is quite similar to the TO11 transfer. With the TO10 transfer, the direction is opposite that of the TO11 transfer, and no NULL character is employed. Both states are identical except for reading the byte count from different RAM locations. After the byte count is read, the operations differ. On TO11 transfers, the KL10 is interrupted and an NPR occurs; on the TO10 transfer, an NPR fetches the data and then the KL10 is interrupted. The least significant bit of the DIAG Word 3 is used to enable the transfer of 8-bit bytes from PDP-11 memory to the EBox. This word must be loaded into the RAM prior to starting the transfer of a block of bytes. The state of DIAG Word 3 bit 00 is stored in the TO10 Byte Mode flag within the DTE. This flag controls the positioning of the incoming byte (by the LSB of the address in byte mode) in the RAM, which acts as a temporary buffer for the byte. Example: The first byte is read from an even-byte boundary. Refer to Figure 2-20, TO 10 Byte Mode. The first byte enters the interface over Unibus lines 07-00 and is stored in the RAM in bits 07-00. Bits 15-08 are loaded with zeros. Then, the byte is loaded into the E-Buffer as follows: bits 15-00 of the RAM (the location holding the byte) is loaded into E-Buffer bits 20-35. From the E-Buffer, the byte is placed onto the EBus as indicated. The 8-bit byte occupies bits 28-35, which corresponds to the position that bytes occupy during TO11 transfers in byte mode. In this way, both are compatible. DTE/2-26 0 ] 0 20 E BUS < E BUFFER 20 27 28 0 | BYTE 1 27 28 35 l ’ 3 15 RAM FILE 0 L / MIXER j(—~ SWAP ——— EVEN BYTE XX1 BYTE 2 = 7 PDP -11 0 MEMORY 20 E BUS < T 27 28 BYTE MODE FLAG SET WHEN CONTROLS POSITIONING | AD!AG 3 LOADS 35 2@ OF BYTE IN RAM 0 E BUFFER I / MIXER \ 15 RAM FILE 0 L/ 1] p=1 2 P4 l15-08 =1 0DD BYTE ; ' PDOP-11 BYTE 1 MEMORY XX0 NOTE: . Initial TO10 Address = XX 1 ~ DTE utilizes bit 00 of diag word 3, T as a byte mode flag. 10-1817 Figure 2-20 TO10 Byte Mode DTE/2-27 The address is incremented by |, in preparation for the next transfer. This is determined by testing the state of the TO!0 Byte Mode flag. In Figure2-20, notice the first byte is read from PDP-11 memory location X X0 and the second byte is not read using the updated address XX1. Remember, in byte mode, the PDP-11 memory appears as if composed of consecutive 8-bit bytes. These are in pairs; the low order bytein bits 07-00, and the high order bytein bits 15-08. The second byte enters the interface over Unibus lines 15-08 and is stored in an appropriate RAM location in bits 07-00. This is accomplished by a swapping technique. Bits 15-08 are swapped with bits 07-00 on the input to the RAM. This assures that the E-Buffer always receives the bytein bits 28-35. Finally, byte 2, the E-Buffer bits 20-35 containing the word 0, is placea onto the EBus for transfer to the EBox. Transfers continue until the byte count increments to zero. At that time, the TO10 Done flag sets, generating an interrupt to the EBox. Optionally, the PDP-11 may also be mterrupted If the least significant bit (bit 00)is a 1 when DIAG Word 3 is loaded into the DTE, the mtcrfaceis considered to bein word mode. Informationis placed onto the Unibusin bits 15-00 as a 16-bit word. From there it is temporarily stored in a RAM location in bits 15-00 for transfer to the E-Buffer. The word is transferred to E-Buffer bits 20-35 and then to the EBus bits 20-35 for transfer to the EBox. See Figures 2-21 and 2-22, TO10 Transfer Simplified Functional Block Diagram and TO10 Transfer Words. respectively. After each transfer, the address must be incremented by two, because in word mode, the PDP-11 memory appears as 16-bit words in consecutive even locations. Therefore, if the initial location is XXO0, the second word comes from XX2. As previously indicated, the number of words to be transferred is controlled by a byte count. The byte count comprises a negative number equal to the number of consecutive bytes to be transferred. It increments toward zero, just as in the TO11 transfer. No Z bit is in the TO10 Byte Count word (as in the TO11 Byte Count word) to generate an interrupt to the PDP11 upon detection of a NULL character. However, a provision is included to interrupt the PDP-11 upon setting the TO11 Done flag. The TO10 Delay Count is the same as that previously described for the TO11 transfer. During transfers, location (12) in the RAM is used as a temporary buffer for the word or byte being transferred. The transfer from PDP-11 memory to the RAM is via the NPR facility. The format of the words used for the transfer operation is illustrated on Figure 2-23, TO10 Transfer. In addition, a functional flow, Figure 2-24, Simplified Flow TO10 Transfer, is included. These should be referenced while reading the functional description. The first part of the operation is to read the TO10 Delay Count and load it into the ABC register. Then the ABC register is incremented and the result is tested for ABC bit 13=0. As with a TO11 transfer, the delay count is a 16-bit word, and ABC bit 13 equal to zero indicates the zero condition. The Interface Control Logic holds the CNT4 TO10 DLY INC state until this condition is satisfied. When the delay count reaches zero, the next state is entered and the byte count is read from RAM location (6) into the ABC register, where it is tested for bit 13 being equal to zero. If it contains a zero, the transfer is terminated and an interrupt is given to the EBox. In addition, if the I bit is set, the PDP11 also is interrupted. If the ABC register bit 13 is non-zero when checked, then CNT4 TO10 BC ADD is entered and the contents of the ABC register are updated by 1. The flow passes to a point where the updated byte count can be stored back into its siot in RAM location (6). DTE/2-28 [x ]a LdNH¥ILNT 30V4HINI aNv 9N1023S0Nyl 3_miHTa4wM8 sng 1 x 3 % 1 9 n W \ / J v 2In3i4g7 0OLIajsuel]payndwig lia Iv1va 3 DTE/2-29 ¥34n9 JV0L¥INVOGD 21907 1 0 H L I N O D — » { 2 : 0 8 Y Wvr IdV NO4 0OI1O0L1 3ALQE LNNOJD (90) 0101 z SANOD <9N130930 viva SNLViSNoa o c [TGo€a1vjeu~|o]ndunIYy0N1Y0y31oINvIjivgd93w4e_i(20d1N3)e]M=i|q113-d8dINT0S1V HHIia-Sn4NyQTdEDYRESTN1N1iAIT>vSSVVaWE<0R:o IP32N@8O1yQdaOv}o-l1%LINI 0Ho8LyNOD ‘3N0O3Q—4T1-1|d+08dT2I81NV3T8034 | INI oL8 1dNY 3ILNT H3I4SNVHL O INI 034 21901 INI 4181-014 NAS 21907 3J0OV4HINT %3HO12PV0L7AS DELAY COUNT * XXX 0@ 15 14 2'5 2!4 00 213 2!2 2!1 210 29 28 27 26 25 24 23 22 21 " 10 9 [ 7 6 5 a 3 2 2 ' 22 2‘ 20 37777:NO DELAY —N,=DELAY TO10 OF N X 500ns BYTE COUNT 15 XXX 14 by 00 ) 4 0, 2 2 2 2 2 2 2 2 2 2 2o NEGATIVE BYTE COUNT 1:SET TO10 DONE AND INTERRUPT THE 10 AND 11 @#=SET TO10 DONE ONLY TO10 PDP-11 ADDRESS 15 XXX 20 215 00 2!4 2‘3 212 211 2‘0 29 28 27 POP-11 ADDRESS 26 25 24 23 20 TO10 DATA 15 XXX 24 28 | 29 | S Ee SN 20 | 21 00 30 22 | 3 N | 23 32 | 33 N SO | 24 | 25 | 3¢ | 35 W0 I | 26 | 27 28 | 29 KL-10 | 30 | 3 32 | 33 | 34 | 35 ot 00 KL—10 BIT POSITION LOW ORDER BYTE BIT POSITION UPPER = 2 BYTES/WORD LOWER = 1 BYTE/WORD DIAG WORD 3 15 XXX 36 ) /,// 0 / & / 7 / // 8 // / 1 * WORD MODE _J @=BYTE MODE % = UNIBUS ADDRESS BITS 17-16. SPECIFIES HIGH ORDER 2 BITS OF 18-BIT ADDRESS USED IN 18-BIT BYTE TRANSFER ADDRESSES. Figure 2-22 TOI10 Transfer Words DTE/2-30 10-1819 1.) DLY CNT INC UNTIL=0 2.) BYTE CNT INC BY1 AND CHECK FOR TERMINATE 3) SETUP ADR AND UPDATE DTE 20 PROCESSING &S 1.) DLY CNT INC UNTIL=0 2.)BYTE CNT INC BYt AND 4} STORE BYTE IN RAM TEMPORARY STORAGE 0 T T REQ TRANSFER RECEIVE BYTE NOW =0 TERMINATE BY RECEIVE BYTE TRANSFER BYTE TRANSFER REQ TRANSFER L BYTE BYTE COUNT:=0 CTERMI INTERRUPT\ KL.-10 / READIBYTE READ BYTE Wewon\ L L INTERRUPT 11 \ 4 DLY 0 CNT a: :E TO10 ;z TO10 TO KL-10* 6 BYTE COUNT ~ PDOP 11 ADR 10 o o 12 «— DATA WILL PASS THRU HERE RAM :]; FROM PDP-11 MEMORY :]: * 1t TO10 I fiag (1) then also interrupt PDP-11 10-1820 Figure 2-23 TO10 Transfer DTE/2-31 START BBSY MSYN SSYN READ DELAY “CNT4 TO10DLY RD” (LOCATION 0} COUNT INTO - ABC ABC UPON COMPLE- ABC+ 1 TION OF NPR DONE FOR EITHER INCREMENT 1BYTE OR 2BYTES TO10 ADDRESS PER WORD - ABC 8y 1 “CNT4 TO10DLY INC” INCREMENT DLY ABC +1 CNT B8Y 1 {F 1 BYTE PER WORD: - ABC WRITE BYTE INTO RAM SWAPPED OR STRAIGHT 0 -15-08 IF 2 BYTE PER WORD WRITE ENTIRE WORD NO YES SWAP 15-08 .- 07-00 LOAD E-BUFFER READ BYTE “CNT4 TO10 BC RD” COUNT INTO “CNT4 TO10 FROM RAM E BUF - E BUF FILLTM (LOCATION 12) ABC + 1IF 2BYTE PER ALSO INC ABC WORD MODE IF 2BYTE) (LOCATION 6) - ABC ABC ABC REGISTER B!T 13=0 “CNT4TO10 ABC REGISTER BIT 137 0 E-8 REQ” NO STORE UPDATED TO10 ADDRESS TERMINATE TRANSFER INCREMENT BYTE BC ADD" COUNT BY 1 INTERRUPT TO ABC +1— ABC GENERATE BUS STORE UPDATED BYTE COUNT IN (ABC) - LOCATION 6 DIALOGUE TO EBOX {LOCATION 10) --ABC ADDRESS l A<17:00 > - ABC D<15:00 = -- PDP-11 MEMORY RAM LOC 12 - 0115:00 - GENERATE NPR DIALOGUE *PI SERVED PIADRIN API FCNACICN- | INTO ABC - D [XX] - AP FCN XMIT “CNT4 TO10 ADR" *F 00—02 CS 00-06 DEMAND | RAM READ TO10 “CNT4 TRANS REQ” EBOX i ; <SET TQ10 DONE - “CNT4 TO10 BC INCTM - LOCATION 10 4 “CNT4 TO10 IF TO10# BIT (1) SET (ABC) IN RAM GENERATE PI100 TO 11 DONE (LOCATION 12} TRANSFER- EBOX TAKES BYTE F00-02 OF DATA FROM €S00--06 BUS DEMAND -- “CNT4 TO10 FL WR"TM *DATI - ACKN — TRANSFER C<1:0>DATI NPR— NPG-— SACK— END 10-1821 Figure 2-24 Simplified Flow TO10 Transfer DTE/2-32 At this time, a byte of data is required from the PDP-11. The Interface Control Logic implements an NPR request to PDP-11 memory using the TO 10 address currently stored in RAM location (10). First, the state CNT4 TO10 ADR is entered, the address is read from the RAM into the ABC register, and then an NPR is issued. The dialogue is shown on the flow and the connections are shown on the block diagram. When the dialogue is completed, a byte of data from the addressed location in PDP-11 memory is at the input to RAM location (12), where it is temporarily stored. It is written into this location, as in a TOI11 transfer, either swapped or straight. Also, the contents of the ABC register, which were temporarily stored in RAM location (6), must be incremented by 1 and read into the EBuffer for transfer to the EBox. The ABC register is incremented again and the updated address is placed into its slot in the RAM location (10). An interrupt request is sent to the interrupt control from the DTE control logic at this time and the DTE/EBox dialogue ensues (refer to Section 2.5.3, TO11 Transfer CNT4 TO11 I/O FCN, for details). As a result of the dialogue, the EBox performs a DATALI and takes the data from the E-Buffer. Then, the DTE releases the EBox and the operation ends. DTE/2-33 SECTION 3 LOGIC DESCRIPTIONS 3.1 DATA PATH ORGANIZATION hanli s B This section introduces the DTE20 interface by describing the logical elements that comprise the two major portions of the interface and supporting diagrams, DTE20 Data Paths, Figure 3-1, and DTE20 Control, Figure 3-2. As shown on Figure 3-1, the DTE20 data path essentially contains the following: Random Access Semiconductor Memory (RAM) 16 words X 16 bits Bus Drivers and Receivers for both the Unibus and EBus Bus Drivers and Receivers for the Diagnostic Bus Four Addressable Registers a. b. c. d. 5. 6. 3.1.1 Diagnostic Word 1 Status Register Diagnostic Word 2 Diagnostic Word 3 Three Non-Addressable Registers a. E-Buffer Register b. c. Address and Byte Count Register E-Buffer Hold Register Various Mixers and Combinational Logic. Random Access Memory (RAM) (Figure 3-12) The RAM serves the 10-11 Interface both as a data buffer and as a control buffer. It is pre-formatted so that a given RAM location always contains specific functional information. Twelve of the 16 available words of RAM storage are used. The RAM can be addressed by the PDP-11 processor via the Unibus lines A(17:00), and can be read or written using DATI or DATO instructions, respectively. The KL 10 processor cannot directly access the RAM for read or write. 3.1.2 EBus Drivers The EBus data lines are fed from the E-Buffer mixer. The mixer can supply three basic types of information: 2. 1. Status Information Data 3. Interrupt Information. The second source is the Diagnostic register that is addressed as Diagnostic Word 1. This register can supply 128 functions to the KL 10 (EBox) as well as enable certain 10-11 Interface functions. DTE/3-1 VAN — EXTERNAL ENABLE c NT3 DIAG BUS E EN 0aT1 DIAG ¢ CNT2 SEL S (00:06) D15 00> 0¢00.35) ] 2 % " v 0 RAM(13:00> Y 2 STATUS 3 DIAG 2 1 01AG 3 0S00-06 CNT3 DATA 24-33 8uUS CONI SEND{-~ 1 SEL X (1) \ EMIX ENO- B A ' / X+ \ DIAG 1 STROBE —]| DIAGNOSTIC € B HOLD T6 DATAO START CNT2 p "ix[ o STAR NTZ UBMIX SEL2 € BUF oo 04-06 € 8UF 00-19 |00 CODES ozlos 00 |per DPSS MST CLR E BUS - oTHER wha 19f20 2223 PARITY ODD X DP32 CNT6 SP DATAO ser CNT3 DEMAND | pamiTy . 1 N CLR © RAM (15:00) “13TATUS [29 15 OPS4 RFM SEL 2 ~CNTI RAM i 08 MIX H | | FILE | OPS4 *See Notes [ i 3 2 [|15-08 [DATA HH 1 15-08 4 1219 sw| _ ~swlos 3 [07-04 € BUF 04-19 |DATA ADDRESS CONTROL ~sw 07-04 2 |oaTa LABC 03000 03-00 1 DPSe PARITY (0} € BUF 00-03 e CONQ o CONL <} UNIBUS PB DIS 21 POWR FAIL ) 22 10 REQ INT 26 REQ 10 INT 27 10 TO 11 ERR TERM® E BH CYC O 1 2 10 TO 10 ERR TERM® 3 PP EN(1) 4 E BUS PIa 4 S NULL STOP® PARITY T 11 TO 11 NORM TERM"" € € BUF SEL 38 PIAt e e ee e - DATO, DATI CNT3 -EXT DIAG BUS CON 32 —‘J STATUS 10° I T UNIBUS PB 1t INT EN*® 11 TO 11 ERR TERMTM" OEX START (0) 33 34 PIA 2 1| DEX WDI RAM FILE MIXER BITS 11-04 are disebled. 0(15:00> ~LUNIBUS FOR RAM (15:003 AND STATUS, NOTES: 2 On 1O 10 or TO 11 ADR SEL, RAM FILE MIXER DPS7 ABC INC ~EBH CYC oL oes? DPS4 PARITY 000 % SELECT ORDER APPLIES ONLY TO MIX 11:00 disodied. cNTe 00 31 T AND LOGIC 'b DATA PAR EVEN 29 10 TO 11 NORMAL TERM® 30 10 TO 10 NORMAL TERM® x LICLEH) NET REM DATA 13-14 ABC LOAD 15 aBc |oPse NPR BBSY DPSe PARITY (1)—ef UNIBUS PARITY I DPS4 PARITY 00D —od o3)sw_{oo 3 EVEN PAR U CNT1 DR 00-03 o3 | oo r CNTS wR 8BSY Mix |EB HOLD|DPSS NPG €8 a ¢ - \7/ MiX T €BUF [} . ! 4 \ A <04 OV Bu B mix [EB HOLOJDPSE 04-t1 04 MIX Mix € 8UF u ADR 04-01 00 |——CNT1 WR PULSE or o7 GO s I swlos tYC A 08 ) 07 OPS4 RFM SEL! DATO 35 |0 RFM DATA <15:00; 00 I STATE CLR 18]~ sw vECT 86 BBSY CNT2 E BUF cLx | ! EBDR DATA <00:35> RAM L o € BUS | snv——Z/ I 20-35 I 3 E BUF 0419 28 cuta con CNT6 BUS SEL Y 3 2 € B HOLD<11:00> | t ~DATA DISAB by 3:&;‘55 (t:gi;m 27 1 rFm pataas-00» T CNTZ UB Mix SEL 2 ~UB MIX SEL ' CNT2 o 35 t PAR CLK 8 oPsa 26 [ CNTE E BUF SEL 0PS2 E BUS 04-19 CNTR [ 23l l20 wcom DPSA BiTS 01-00 G o815 Tos 5 ore 3 0003 0PS54 PARITY | i OO DIAG DIAG SEL X os] o6 [ o7 -03 003y CNT2 UBMIX SEL 1 EN ~BUS 03] ix —{> ' o MiX| oo CNT6 DATAO 1 BUS SEL 2 (L) EBUS PARITY BT -4-- OTHER ! ' 0P CODE 1 1L} -- —e——t--fo}-{o 1 ' ] t EN UNIBUS STATUS 11** g;?&";;‘_‘ls - 1 ~ 0<15:00> 15:00 : N4 10- 1822 Figure 3-1 DTE20 Data and Address Paths Block Diagram DTE/3-2 TO1t NULL DATO, DATI FROM =— - TonIen TO11 BYTEM DCRG R UNIBUS 15,14,13,12,4,3,0 CONTROL s +—] TO 10 BYTE M <+—] ACKN CNTS DEX l DEP| p TO10| o] O I ‘I > TO1O| Tonl ToEl I oo CNT2 DEX oo CNT2 DIAG STRB —4; DEM LOGIC CONI LoGIC CNT6 DATAI "o 1" SEND IN CNT7 T CNT3 — 8 EBUS Z?_}Ns | EBUS <0:35> € P1AORIN E— | BUS SEL KL1O TRANS v ) M a TRRE o <01= 04> = S DEX ADR 2 5 DEX T_ E BUS LOOP (EFFECTIVELY) “INH CLOCK" EBUS CLK O TO 10 DLY RD 2 70 10 BC RD “RAM_CYCLE" 0-11 DsS<01:02> BusS COMPLETE 5 TO 10 ADR RD . E-BUF-FILL CNT4 REMOVE SeATUS sTROBE DIAG L — DIAG KL-10 DIAG DIAG COM START 70 11,BC 3-1 OUT Ic BG IN D <00:06> = <KL-10> 2 <DFUNC > O RAM <15:00> t DIAG 3 e 2 sTATUS a CNT2 UBMIX SEL 2 CNT2 UBMIX SEL 1 . — MIX SEL <1 <d BG oLy * EN BGSACK" SACK BG OR NPG . . TO 11 ADR ADD - SET DIAG CNT4 REQ COMMON BBSY OUT SEQUENCE LOGIC 10/ r—i INTI T . SER, EN NPG SACK - 1 _~]_BBSY IN < - _‘D BBSY OUT ) SSYN IN/OUT INT2 REQ IS BBSY IN 8G/ NPG . . " o oLy 3 * UBIC WR RAM LUBIC CLR CvCi 3 NPR TEST BBSY | \pR. NG NPR/NPG CLk 1 coms Lo‘;'fsc‘“[’ INT ! INT2 CLK 2 NPG CLK3 CLOCK leStX 4 e P INT2 INT2 B8SY CNT3 DATI,DATO “SEL DIAGY &1 !: l NPG ~J LOGIC N I_% ¢ <| OUT T I co.ct [} 1 Alcnosnc REGISTER CONTROL; 1 SEQUENCE coMB wn o TM N8R o, ¢t : MsN . DATA CNT3 N | _ SELOlAGY A <};A,, ] D <00: 06> ONT2 D<15:00>DATO <l, < FIG BR VECTOR 1% — UBIC DATO 2 "128,, POSSIBLE FCNS" 3 DIAG 2 PATHS LOGIC > OUT 1 t—=la TO 11 I/0 FCN 14 EBH /\ N INTR L VECT coms INC -— i DATA BR- - BG BBSY)nT 2 UBIC CLR CYC 2 CNT3 ] DS<00: 06> TO INTR OUT SEQUENCE t—{1 TO 11 DLY INC —+12 TO !t BC RD UBIC DATI ~d l T LOG IC DIAG STROBE REQ" TEST —— 3 TO1 ADR INC DIAG BUS EN DIAG REMOVE STATUS DIAGNOSTIC | BUS conTROL | EM REMOVE STATUS 1 REQ “BR CONQ CONT 8 T0 10 E-BUF-REQ |—»f —={ 3 [ INTR bPSS (DPS5 11 INT) Losic INT1 . DIAG 10-1 CNT4 WR CLK +1 STATUS CNT6 OR SP DONE {6 10 10 FL WR 10 DPS5 STATUS CNT “DONE T0 10 BC ADD TO NULL pr CNT2 NPR KL-10 DONE - CONTROL —»{4 TO 10 BC INC —*3 D <i5:00> DATO DATS l "RELEASE CLOCKS" CNT4 WR CLK <04:01> INT1 DATO INT! DATI ACCESS j SEND . —=11 _T0 10 DLY INC =18 T c‘|§c'2ws> woR W?IS:J t A 7 evre DONE t—={7 10 11 FL RD *cnre ALL MINORS 1 3 DEX WORD 2 r M t—>{5 TO 11 SHIFT ; |- swap SEL - =6 70 11 EBUF STORE - T sl LT SEL —={G_T0 (1 DLY RD cLock | CcLR Mix seL | SENO REQ _— » Z INH eaus | oMt i 7 z TO It set [EMIX EN DPS5 10 INTR ACT 38 ® 8US SELY ,SEND Looe CNT 4 DIAG Co @ voor —¥ I DIAGNOSTIC EBUS a1 S L a CNT6 EBUS T |— 1 O DEX ADR 1 4 DEX WORD3 ] |— SEL CNT6 PII-7 ' . BUF Mix u . SEL £BUF<04:19> ERROR e — COUNTER SEL o a - " [ 2_DEX WORD ! L 1010 EN SWAP oPs! 2 —of LEVOO CNT7 : O RFM DATA < 15:00> ) SENDOP, TOPSENT, = COMP2 | PHYS # SEL NS DEX — MIX "LOCK MAJOR STATE" w I COMP1 | cso-3 CNT4 CNTE 51> SELPILEV p——o PS4 . 2 E BUF HOLD<11:00> 3 4 AM LOGIC REQ" CNT 4 CONI cs 0-6| "TRANSFER PI AD SERVED COMBINATION 0I UNIB ABC <15:00> <I5:00> FIG 3-1 ‘ CNTS coms [eBus FCN_ |paTa0 08,910,111 | comp | prLeve| PECODE % oPs . DPS4 SEL 2| 19 pATA PATHS | STRB - cono . —*|Mix SEL TO10 ADR STRB ADR! - RAM FIl E EVEN PAR ] [> | DIAG 3 STRB CNT2 —» SINGLE PLS roa BC STRB CNT2 L wwrITE CNT3 TRANS *_[> 1O el CNT2 £0-2 ——{> “DEV £500-05 SEL CODE" EN < CNT3 WRITE "STROBE" 1n Figure 3-2 1823 Detailed Control Block Diagram DTE/3-3 3.1.3 EBus Receivers The EBus receivers can supply information to three destinations in the interface: 1. 2. 3. E-Buffer Input Mixers Status Register E-Buffer Hold Register. 3.1.4 Diagnostic Bus Drivers The diagnostic bus, on the EBus side, is a logical extension of the EBus. Its operation is under the control of PDP-11 diagnostic software. When the diagnostic bus is not actively used for diagnostic read, write, or console functions, its lines contain processor status information; the bus is never disabled. Reading vital processor status information (e.g., is the machine halted) is performed by just reading the specific Diagnostic register location. The register itself is not read, the bus is. When the register is written into, those bits are placed on the bus. Then the bus bits are read. The EBUS REMOVE DS STATUS signal is asserted when a diagnostic function to the DTE is performed. The signal controls removing the processor status information from the DS lines. 3.1.5 Four Addressable Interface Registers Twelve DTE locations reference the RAM and require a RAM cycle. This cycle is a larger and more complex interfacing cycle to perform than a regular cycle. Four DTE locations do not access the RAM, but are accessed by a simpler mechanism. The four locations are Diagnostic Word 2, Diagnostic Word 3, Diagnostic register, and the Status register. These locations should be used first in diagnosing problems because the simpler mechanism will probably fail less often than the more complex cycle mechanism. 3.1.6 Three Non-Addressable Registers In order to perform the necessary manipulations on internal data and control information, the 10-11 Interface uses three working registers: 1. 2. 3. 3.1.7 E-Buffer Register Address and Byte Count Register E-Buffer Hold Register. Miscellaneous Mixers and Combinational Logic The remainder of the logic in the Data Paths Logic provides the interconnections among the various elements pointed out in Sections 3.1.1 through 3.1.6 to facilitate proper interface data manipulation. 3.2 CONTROL SECTION ORGANIZATION Nk L= Refer to Figure 3-2. The 10-11 Interface control section essentially contains the following: Access Control Logic KL10 Interrupt Dialogue Logic PDP-11 NPR Dialogue Logic PDP-11 BR Dialogue Logic Control State Timing Logic DATA Register Control Logic Diagnostic Control Logic. 3.2.1 Access Control Logic The access control is driven from two basic sources: the first source is the clock and state control, which provides all the minor states from the three major states: DEX, TO11 transfer, and TO10 transfer. These minor states are gated against conditions arising in the interface and become the clocks DTE/3-4 i to provide synchronized control levels or pulses that are fed to various places within the interface and from the access control. Some of the functions performed from the Access Control Logic are: RAM File Address Selection WRITE Control RAM File Mixer Selection E-Buffer Loading ABC Register Loading and Increment Unibus No. 1 Enable Addressable Register Selection Generation of DONE Conditions and NULL STOP. The second source is from the Unibus. The high-order four of the least significant five PDP-11 address lines A(04:01) are passed to the access control along with the DATO/I level. Decodersin the access control decode the address lines and DATO/I into a discrete signal name depending upon its weight; i.e., 00 decodes CNT2 SEL DLY CNT. The decoding of a RAM address enables a RAM cycle, which vul] implement the appropriate write or read operation. Upon completion, the interface logic shuts down. 3.2.2 KL10 EBus Dialogue o The majority of this logic is shown on CNT6 and CNT?7 prints. The logic consists of a decoder for function as well as comparators for physical controller number and PI channel, control flip-flops to synchronize the events, and bus selection and mixer selection logic. The logic can be triggered by two basic events: 1. Control state interrupts; i.e., those that are interface generated. Also status interrupts; i.e., programmed interrupts. 2. The second type of event is the execution of an input/output instruction to the DTE20. 3.2.3 PDP-11 NPR Dialogue The NPR Control Logic is shown on the INT1 and INT2 prints. This logic is used by the DTE for sending or receiving data to or from PDP-11 memory via the Unibus. The address for this transferis always placed in the ABC register for use during the NPR transfer, but it is not an ABC register generated address. All control logic necessary to sequence an NPR transferis on the M8554 (INT) module. Therefore, if either an NPR or an interrupt does not function properly, this moduleis probably at fault. 3.2.4 PDP-11 BR Dialogue The BR (bus request) Control Logicis shown on the INT1 and INT2 prints. The DTE uses this logic when requestmg the following interrupts to the PDP-ll TO11 DONE TO10 DONE DOORBELL. 3.2.5 Control State Timing Logic (Figure 3-2) , The control state timing is responsible for the implementation of all the major and minor state timing levels. By monitoring the Data Control Logic, the Control State Logic determines when to begin a specific sequence; e.g., DEX, TO10 transfer, or TO11 transfer. The logic mainly comprises an external clock input (EBus clock), an 8-stage ring-counter that serves as the main clock, and a 3-stage ringcounter that serves as a major State register. Also, a 4-stage BCD counter governs the minor states for the DEX and TO10/TO!11 transfers. DTE/3-5 3.2.6 Data Control Register Logic The Data Control register logic is shown on the CNT4 and CNTS5 prints. The register contains operational Status flags: Operation Pair DEX CNTS DEP FF, CNTS DEX START FF TO11 Transfer CNT5 TO11 BC LD FF, CNT5 TO11 ADR LD FF TO11 Transfer CNT5 TO10 BC LD FF, CNT5 TO10 ADR LD FF The remaining five flip-flops remember the following: TO11 . If (1), ’8-bit byte fransfers | TO10 Byte * If (0), 16-bit byte transfers e If (1), 8-bit byte transfers ¢ If (0), 16-bit byte transfers TO1!1 NULL STOP * Stops transfers upon detecting NULL character ) ‘TOI11 I Bit ¢ Interrupt the PDP-11 to get a new Byte Count word when TO11 DONE (1) Single PLS * A diagnostic function; allows stopping the 10-11 interface after each clock pulse TO10 I Bit ¢ Interrupt both the PDP-11 and KL 10 when TO10 DONE sets The remainder of the logic controls the KL10 interrupt dialogue, and assures the proper EBus selection and EBus Mixer selection during interrupts. 3.3 BASIC BUS TRANSACTIONS To allow communication between the KL10 processor and the PDP-11 processor, the doorbell feature is included as part of the 10-11 Interface. Both processors can use this feature. To ring the doorbell, the appropriate processor must perform a specific input/output instruction, which will set the Doorbell flag in the interface. Table 3-1 lists the essential steps necessary in the process. 3.3.1 PDP-11 Rings Doorbell , Refer to Figures 3-1 and 3-2, and Table 3-1. As indicated in Table 3-1, to ring the KL10’s doorbell (i.e., generate a KL10 interrupt) the PDP-11 must execute a DATO instruction to the 10-11 Interface while addressing the Status register, and bit 08 on the Unibus will set the appropriate flag. In addition, at some previous time the KL10 must have assigned a channel number to the interface, via a CONO instruction. A standard Unibus dialogue continues. Refer to the PDP-11 Peripherals Handbook (EB 05961 76), Chapter S, for a complete description of the dialogue. 3.3.2 Interrupt Dialogue Refer to Figure 3-2. The setting of DPS5 REQ 10 INIT leads to the generation of DPSS 10 INTR ACT. This signal is passed to the EBus as the appropriate interrupt line, i.e., PI 1-7. The EBox must arbitrate this with other incoming interrupts from other devices. The following dialogue selects the device that the KL10 serves at this time (in this case, the interface). DTE/3-6 Table 3-1 Typical Doorbell Sequence Abbreviated Processor KL10 Function Action Ring PDP-11 CONO Negotiate byte XFER Doorbell PDP-11 Read Interface Turn OFF Doorbell Bit 22 Flag SET DPS510 REQ INT DATI Status Register PDP-11 Reason | DATO Determine reason ALL for INTERRUPT Relevant Answer the doorbell 10 and perform preliminary N.A. CLR DPS510 REQ INT setup for BYTE XFER Transfer is negotiated here PDP-11 Ring KL10 Doorbell | DATO Negotiate BYTE XFER | 08 SET DPS5 REQ 10 INT KL10 Read Interface CONI Status Register KL10 Turn OFF Doorbell CONO Determine Reason ALL for INTERRUPT Relevant Answer Doorbell and 26 perform preliminaries N.A. CLR DPS5 REQ 10INT Having arbitrated the priorities, and wishing to select as candidates those devices on channel (N), the EBox asserts the following: CS04-06; Channel No. (N) F00-02; PI Level Served DEMAND,; Activate Decoders. The 10-11 Interface Data Control (CNT3, CNT6 and CNT7) and Bus Control (CNT3 and CNT?7) Logic handle the decoding and dialogue. Upon detecting DEMAND, the interface compares its assigned channel number to that provided by the EBox as well as decodes function to be PI LEVEL SERVED. The result causes the interface, as well as any other devices on the same channel to assert their physical controller numbers EBus D (8, 9, 10, 11). Each control will place its physical controller number in a predefined bit position on the EBus. The EBox then strobes the EBus. Then, the EBox must decide which physical controller it wishes to service. In this case, assume the interface is to be serviced. The EBox asserts the following: CS00-03; Physical Controller No. CS04-06; Channel No. (N) F00-02; PI Address In DEMAND:; Activate Decoders. The interface, upon detecting DEMAND for the second time with P ADDRESS IN and physical controller number and channel number (N), asserts the appropriate bus select levels and EBus Mixer select levels, which cause the API function to be placed onto the EBus drivers. The API function format in this case is shown in Figure 3-3. DTE/3-7 00—02 03 05 06 ADDRESS | FUNCTION | o SPACE (2) 07 10 H—1213 33";’1“8%3 DEV PHYS # 35 o | VIRTUAL ADDRESS 10-1824 Figure 3-3 API Word Format Vector Interrupt Refer to Figure 3-4 (sheet 2 of 2); two tables are shown. The first shows the bus select levels X, Z, A, Y, and data disable. These levels ultimately select some combination of the E-Buffer or the E-Mixer as input to the EBus drivers. There are two possible states for each bus select level; High (H) or Low (L). As indicated, the inputs to EBus driver bits 0-2, 3-5, 20-22, 26, 27, and 29-35 are mixed. Either the EBuffer or some form of control or status information enabled into the EBus Mixer is provided as input. Note that the inputs to EBus driver bits 8-11, 12-19, 13-25 and bit 28 come directly from the corre- sponding E-Buffer bits. The second table (Figure 3-4, sheet 2 of 2) shows the E-Mixer selects, a select line, and the enable line provided. The four types of input provided are: E-Buffer Status Interrupt Information Nothing. For convenience, the EBus driver select and EBus Mixer selection logic are shown in a simplified form on Figure 3-4 (sheet 1 of 2), EBox Interrupt Dialogue. The interrupt sequence is indicated on the illustration by steps 1 through 7. The detailed breakdown on the EBus and E-Buffer Mixers is illustrated on Figure 3-5. On Figure 3-4, note that at 7, the signal EBUS SEND OP (send API word) enables Bus Select Z. This causes EBus bits 3-5 to be taken from the EBus Mixer bits 3-5 rather than the alternate, which would be Os in bits 3-5. On the second table at the top of Figure 3-4, (sheet 2 of 2), the EBus Mixer selection, with Bus Select Z(L) asserted, enables the EBus Mixer. The source input to the EBus Mixer is a function of Bus Select X(L). When Bus Select X(L) is true, the EBus Mixer selects E-Buffer bits 04-06; but during EBus SEND OP, Bus Select X(L) is false and the selection is from EBuffer bits 00-02. For function codes 4 or 5 the term “~OP CODEL!” is true, enabling the EBus Mixer to select the E-Buffer bits 00-02. For functions 2 and 6, the EBus Mixer is disabled and the address space field of the API word being placed on the EBus is forced to 0. This will be interpreted by the EBox as the Executive Process Table (EPT). The EPT contains the TO10 and TO11 byte pointer words used while performing function 6 and the vector interrupt instruction used while performing function 2. Also indicated on Figure 3-4, ~OP CODEI (true for Examine and Deposit API function codes 4 and 5) enables Bus Select A, which in turn enables Bus Select Y. This provides the virtual address in EBuffer bits 13-35 as input to the EBus. Bus Select X(L), when false, enables the Protection Off flip-flop in the DTE20 to become the Q bit (EBus bit 6) in the API word. 3.3.3 KLI10 Rings Doorbell Refer to Figures 3-1, 3-2, 3-4, and Table 3-1. As indicated in Figure 3-1, to ring the PDP-11’s doorbell (i.e., generate a PDP-11 BR interrupt), the KL10 must execute a CONO instruction to the 10-11 Interface while selecting the controller as the device, and bit 23 of the EBus will set the appropriate flag. Refer to Figure 3-2. The CONO is implemented as follows. The EBox asserts the following: CS§(04-06); Device Select F(00-02); CONO DEMAND; Activate Decoders. DTE/3-8 N DPS5 REQ 10 INT DPS510 TOI1 PIML<} EITHI @ P100 EITHER ] CAN NORM TERM DPS510 TO11 S SeeuR ERR TERM — DPS5 10 TO10 NORM TERM U OcCL OPS510 TOIO ERR TERM CONTROLLER | SEE NOTE 3 SELECT # EVENTS WITHIN DTE 20 £500-03 [N 'PHYSICA | L#seecteo’ . * HARDWIRED . & l CNT4 TRANS REQ (1} ® o £508-06 [N\ "ENCODED PI CHANNEL TO HONOR SEL . @6 - £BUSD COMPARE #2 34 COMPARE #1 LEV PHYS # SEL ® [8.9.10,11] ACKN ] PHYSICAL # SENT (HARDWIRED){ SEND CONTROL) | 'RESPONSE 70 10 BUS ADAPTER ~ TRANSFER<);"RESPONSE TO £EBOX" @ - DEMAND [: @ /C:)_LI @ EBUS SEND OP COMBINATIONAL| LOGIC ICOMBINATIONAL LOGIC [(T)gntmmzzen @ ® "ACTIVATE DECODERS” T010 TRANSFER] O~ CONO ¢ 1f— CONI | oL DECODED | WHEN EBOX 2} paTaQ [ EXECUTES THE . "€ NCODED INSTRUCTION DECODER| PT SERVED (ONO)] . DEPOSIT7 APPROPRIATE 3}-— DATA T FUNCTION" FOO-02 sPraRin ® ENABLES EBUFFER ‘ I 14 61— TOBE INPUT FROEA 1op 7 i) | —= gpyy EBUS DRIVERS FOR EXAMINE AND TOI! TRANSFERS g | EQUIVALENT TO ——_| TOI0 TRANS(I) AND IOP SENT (1 DEP TM 1010 ool f 9 f98E | WLl pata | I DATA CONTROL SET REGISTER (GENERIC TERM) ENABLES EBUFFER 0-35 TO EBUS DRIVERS FOR DEPOSIT OR TO10 TRANSFERS 0P dENT BUS SELECT X DATAI ————— EBL% DATA GATES 7 EBUS LOOP DIAG SEND Kt EBUS SEND OP @ [l Y S v - O A DEX (1) —x-1 N~ e 0P coDE! ’——r——— .\__i NOTES: |. TO1O DATA CYC = TOIO TRANS (1) A IOP SENT 2.(D- @ = Typicol interrupt sequence. To determine figure EMIX SELECT 3-5 the effect of BUS SELECT Z, refer to EBUS ond EBUFFER MIXERS 3 Fc‘v t?eposils, exomines, TOt1 and TO1O transfers this is PT LEVELO. EMIXEN - e XN EMIX SELECT — —— \ TO0 CONT SEND CONI - &S—CE DEMAND NI : SEND DEV SELECT CODE ______ 4 10~ 1828 Figure 3-4 EBox Interrupt Dialogue (Sheet 1 of 2) DTE/3-9 EBUS EBUS DATA GATES BUS SELECTS 0-2 3-5 6 7 BUS SEL X{Li 8 8-11 12-19 20-22 23-25 26 27 35 7 EBUFF 12-19 EBUFF EBUFF 23-25 ~ DATA DISABLE EMIX 0-2 ANDED WITH 8US SEL Z(L) EMIX 3 DATA DISABLE 0 0 0 ANDED WITH | ANDED WITH | ANDED WITH BUSSEL Z(L} | BUSSEL X(L) | BUSSEL A(L) o 0 EBUS MIXER SELECTION ggLS X(L) / % TRUE / FALSE FALSE / TRUS // TRUE / g / / Figure 3-4 NOPCODE 1 0-2 EBUFF TRUE TRUE 0-2 TRUE EBUFF ! 4-6 // / 2 TRUE TRUE Z TRUE FALSE 6 7 EBUFF EBUFF EBUFF TRANS ACT, PROT OFF(0) 0 3-5 OPCODE 1, OPCODE 2 6 / 8-11 ANDED WITH | BUSSEL Y(L) | EBUSMIX 27 | ANDEDWITH | BUSSEL Y(L) | EBUSMIX 29-35 0 0 0 0 0 23-25 2 27 28 29-35 STATUS EBUFF STATUS EBUFF 0 12-19 20-22 28 EBUD MIX 26 : 7 10P 6 DATAI STATUS EBUFF // V, / y / EBUFF 3-5 / EBox Interrupt Dialogue (Sheet 2 of 2) DTE/3-10 3-5 // / /] o EBUS MIX 20-22 EBUS DATA GATES ot ?_fLL, FUNCTION EBUS MIX EBUS MIX US SEL 2(L) BUS SEL YIL) EMix ENIL) 29-35 EBUFF 8-11 BUS SELA (L) cont SEND(H) 28 TRANS ACT, OPCODE 2 OPCODE 1, EBUFF 7 0 20-22 2 27 STATUS EBUFF 29-35 F UNCTION Y e We NA N ~DATA DISABLE 7 ~DATA DISABLE e N z IOP DATAL s N X e N A ~DATA DISABLE A LA ¥ ~DATA DISABLE A ~DATA DISABLE N Y ~DATA DISABLE EMIXEN(L) 1 8US SEL x(1) ~ BUS SEL X (H) : ¥ 02 00 ~0p »n T * o1 sl ZB(ULS) L L- /o3 05 B T CONI 1 osaus Mlx1 OEBUSM'X . CODE1{L) 2 »* = EBUFFER /fz_ AN A_‘; N 1 T ML 5 OP CODES 04-06 "ALWAYS | [SEND PROT SEE NOTE y = OFF (O} STATUS STATUS SEE TA?\LE AN STATUS SEE TAELE STATUS SEE TAgLE SEE TAELE ENABLED" CNT2 EBUF CLK - — — {00 EBUFFER oz}- {03 EBUFFER 05} - CNT4 EBUF SEL—- - -1 0 i -4 0 1 DPS2 06 03-05 |V -4 o -4 o EBUFFER T9}-- {20 EBUFFER 22}~ -[23 EBUFFER 25— -4 o 1t EBUFFER 24-27 08 -11 1 DPS2 EBUFFER 23 o7 1 DPS2 EBUFFER 22 06 o [ ESUFFER M} -{12 DPS2 EBUFFER 19-21 00-02 o7 EBUFFER 0 1 DPS2 EBUFFER 16-18 -- EBUFFER 0 1 -4 DPS2 EBUFFER ,— -4 o 1 -4 26 EBUFFER 0o 1 - 27 EBUFFER o 1 -4 - 28 EBUFFER 0 1 -4 -423 -4 o EBUFFER 35 DPS4 DPS4 DPS4 DPS4 oPS4 DPS4 15-13 12- 10 09 o8 07 06-00 DATA 27-35 12-19 -4 20-22 DATA 23-25 DATA DATA 26 DATA 27 28 DATA 29-135 DPS3 DATA 00-35 NOTE: —Fon—f 00 .. BUS SEL X {H) TABLE A E BUS MIXER ‘.l 8IT TYPE OF STATUS BUS SELECTS z WAYS OF GETTING THE SELECT 1) CNT6 EBUS SEND OP 1) CNT4 EBUS LOOP 2) CNT6 DIAG SEND V4 15 1 RAM FILE 7 2) BUSSEL X Q DEPOSIT ONLY CNT6 TRANS ACT EXAMINE DEPOSIT BYTE XFERS OP CODE 0P PC CODE 2 \ VECTOR INTERRUPT BYTE X FERS 20 ~EXT DIAG BUS EN 21 INT1PWR FAIL 22 2 27 DPS5 10 REQ INT DPS5 REQ 10 INT DPS5 10 TO11 ERR TERM 29 DPS5 10 TO11 NORM TERM 30 DPS5 10 TO10 ERR TERM 3 D PS5 10 TO10 NORM TERM 32 DPS3 PI0 EN 33 DPS3PIA 4 (1) = OPSIPIATTH 34 DPS3PIA 2 (1) X v 3) CNT6IOPSENT (1) A [CNT7 DATAIA CNT4 DEX (1)] ; SSEL X ) BUSSEL BUSSELA CNT6 E BUFFER SELECT 3) CNT6TO1GDATA CYC =CNT4 TO10 TRANS (1) A o 1) ~CNT6OP CODE 2) BUSSEL X 1) ~EXTDIAGBUSCON 2) k4 DATADISABLE | CNTG6 10P SENT E BUFFER 00-19 « EBUFFER 16-39 « £ BUFFER 20-35 RAM DATA 15-00 EBUS DATA DISABLE 1 « E BUFFER 00-35 EBUS 00-35 t0-1826 Figure 3-5 EBus and E-Buffer Mixers DTE/3-11 The interface, upon detecting DEMAND, decodes the device select as the 10-11 Interface and the function as CONO, and generates a strobe that leads the EBus bus (23) into the STAT 10 REQ INT FF (Figure 3-1). This flag leaves the Status register as BR REQUEST. Finally, the interface asserts ACKNOWLEDGE (ACK) and TRANSFER. This completes the dialogue on the KL10 side of the interface. 3.3.4 _ Interrupt Dialogue Refer to Figure 3-2, Figure 3-7A, Bus Request Simplified, and Figure 3-7B, BR Timing. The signal BR REQUEST from the Status register causes the Unibus control logic to issue a BR to the PDP-_ll processor. Refer to the PDP-11 Peripherals Handbook (EB 05961 76), Chapter 5, for a complete dis- cussion of the interrupt dialogue. The major difference in the implementation of instructions versus interrupts, as it applies to the bus dialogue, is in terms of the use made of the Controller Select lines. The device select codes available for the DTE20s are shown on Figure 3-6, at the right margin. The first interface would be assigned the code of 200, the next 204 and so forth. The physical number assignments are only used during interrupts. Assuming the KL10 is issuing a CONI to the DTE20, the dialogue is as follows: The EBox asserts the following: CS(00-06); Device Code to Select Device F(00-02); Function is CONI DEMAND; Activate Decoders. - The interface, upon detecting DEM AND, decodes the device select code as the appropriate DTE20 and the function as CONI. Refer to Figure 3-6. The combination of the decoded device select and function (CONI) enables E-Mixer Select 1 only. This selects those relevant bits from the Status register -and enables them onto the EBus. The table at the top of Figure 3-4, (Sheet 2 of 2), indicates that bits 20-22, 26, 27, and 29 through 35 are enabled. An important point to remember here is that the vector interrupts (KL10 device code and PDP-11 address assignments) are controlled by back panel wiring. No jumpers are used to differentiate them from slot to slot. . Each interface transfers to its preassigned vector address within PDP-11 memory. Refer to Table 3-2 for the various possibilities. After having received the interrupt line, the PDP-11 will assert SSYN. The interface, upon receiving SSYN, will drop BBSY as well as the vector address and interrupt line. This completes the dialogue. Table 3-2 Vector Addresses Interface No. Vector Interrupt 0 774 774400 1 770 774440 2 764 774500 3 760 774540 DTE/3-12 PDP-11 Device Register 3.3.5 Doorbell Summary In negotiating a transfer between the PDP-11 and the KL10, the doorbell is used to set up the necessary communications between the two processors. One of the operations that is performed by the PDP-11, with respect to the KL10, is to read information from a predefined area in the KL 10 main memory. It is this information that establishes how the PDP-11 operating system proceeds during various types of transfers. The block of information contains such items as pointers to sources of data or control information, destination addresses, and flags. 3.4 INTERFACE STATUS 3.4.1 General Information Figures 3-8 and 3-9 indicate the bit configurations for the CONO and CONTI instructions, respectively. Tables 1-13 and 1-14 list the purpose of each bit. Similarly, Figures 3-10 and 3-11 indicate the PDP-11 DATO and DATI bit configurations. The 10-11 Interface Status register plays an important role in most, if not all, interface bus operations. DTE DEV SEL IS HARDWIRED A DEV SEL | INTERFACE # <] TRANS A cS@@-03 g < E ACKN 200 0 210 2 214 3 204 G—l —‘{> ' DEVICE ; DTE "SELECTED" SELECT LOGIC cS@4-06 U s CNT & DEMAND N ENABLE i~ ENABLE CONO +—] l °Tcont 1 \ , | DATAO FEg-22 N "> DECODER 3 [— J\ /- \ \ 6 — FCN SIGNAL BASIC ACTION CONO CONO SET TOGETHER WITH APPROPRIATE _ CONI SEND 1 4 sl enT? T CONO SET J DATAO START EBUS BITS PERFORM THE FUNCTIONS INDICATED IN TABLE 1-14 CONi CON! SEND CAUSES THE INFORMATION INDICATED IN TABLE 1-13TO BE PLACED ONTOQ THE EBUS DATAO DATAQO START TOGETHER WITH APPROPRIATE EBUS BITS, PERFORM THE FUNCTIONS INDICATED iN TABLE 1-12 10-1827 Figure 3-6 KL10 Instruction Dialogue DTE/3-13 _ DPSS 1t INTERRUPT EN A DPS5 11 TOtt NORM TERM DPSS5 11 TON N\ ERR TERM } DPS5 11 INT IN\_ UNIBUS BR > DPS5 11 TOI0 NORM TERM DPS5 11 TOIO ERR TERM DPS5 10 REQ INT BG SYNC oLy "SET" | __~] UNIBUS BG IN INT2 -1 BG SYNC (1) \'SET" INT2 BG DLY INT2 BG INTY SACKOUT BG SACK SACK N L~ i——J— ~BBSY IN U N ~SSYN IN | — oo 3 SOLR B ~BG INT 2 " |BBSY B8BSY s INT1 BBSY OUT[N__UNIBUS BBSY _~1 uNIBUS SSYN IN\__UNIBUS INTR "SELECTION IS "VECTOR ADDRESS" JUMPERED" INTERFAC O -774 E (DTE 0) INTERFACE 1 - 770 (DTE 1) ‘ INTERFACE 2-764 (DTE 2) IN\_ \ INTERFACE 3-760 (DTE 3) 1/ CNT3 VECT 01-05 — f TYPE OF BR REASON FOR BT TYPE OF BR REASON FOR BT DPS5 11 TO11 ERR CNT2TO11 ERR SET IS ASSERTED FOR DPS5 11 TO10 ERR TERM (1) CNTZ TO10ERR SET IS ASSERTED FOR ONE OF THE FOLLOWING REASONS: TERM (D ONE OF THE FOLLOWING REASOHS: 1.} AN EBUS PARITY ERROR OCCURRED 13 DURING A TO11 TRANSFER 2) A UNIBUS ERROR OCCURRED DUR- 2) ING A NPR TRANSFER DURING A TO11 TRANSFER DPS5 11 TO11 NORM CNT1TO11 DONE SET IS ASSERTED FOR TERM ONE OF THE FOLLOWING (1) REASONS : DPS5 11 TO10 NORM CNT1 TO10 DONE SET IS ASSERTED FOK TERM (1) THE FOLLOWING REASON. CNT5TO111BIT (1) BC=0 AND A TO11 BYTE COUNT READ WAS PERFORMED BEEN SET PRIOR TO 2) TO11 NULL STOP WAS TRUE AND THE TO10 TRANSFER RAM=0 DURING A TO11 FILE READ DPSS5 10 REQ INT (1) DPS5 NULL STOP SETS AS A RESULT A UNIBUS ERROR OCCURRED DURING ATO10 TRANSFER 1) OPERATION SgCDJI-R]F:E%ESAS:IT\I(:AARI\:TN\Lgnflo’R TRANSFER THIS BIT MUST HAVE (DOOR BELL] 1) BC=0 AND A TO10 BYTE COUNT READ WAS PERFORMED SET BY CONO DTE STATUS WITH BIT 22 (1) MUST BE CLEARED BY PDP-11 WITH DATO AND UNIBUS BIT 10(0) 10-1828 A. Figure 3-7 Bus Request Simplified Bus Request (Sheet 1 of 2) DTE/3-14 CNT7 STATE CLK I l (0 1B | I CNT? GD,STATE CLK { (_ o)) 8C RD TO 10 { ¢ ’ RFM BC =g )7 46 EXAMPLE: ASSUME BC—@ ((_ IR CNT7 GD SHIFT CLK I | — (v SET DPS5 11 TO 10 DONE DPS5 11 o BIT14(1) CLEARS, H INT (o / INT2 11 INT (l UNIBUS BR [/ | 1) (L / R K {{ H ((— WAIT FOR BG - }) A 17 INT 2 UN BG (" A 1) INT2 BG SYNC m B INT2 BG 100 SACK INT2 BUS AVAILABLE //// UNIBUS BBSY UNIBUS DATA -2 UNIBUS VECTOR INTR ADR INTERRUPT LINE e WAIT FOR SSYN UNIBUS SSYN T ( | 1) PDP-11'ASSERT SSYN B. Figure 3-7 . . BR Timing Bus Request (Sheet 2 of 2) DTE/3-15 10-1829 22 23 24 25 26 ! SET RELOAD 10 REQUESTING 30 31 DONE AND INTERRUPT CLEAR CLR 11 34 35 — PI CHANNEL ASSIGNMENT BITS INTO BITS 33-35 CLR TO10 REQUESTING DONE 10 INTERRUPT 33 CHANNEL # TO11 ERROR RELOAD 11 32 CLR TO1 LOAD! PI i 1 11 29 PIO AND ENABLE TOt1 ERROR 10-1830 Figure 3-8 21 CONO Interface Bit Assignments 22 26 I 27 11 POWER 11 FAIL REQUESTING 29 TO11 30 31 I 32 33 I 34 35 —_— DONE | TO10 ERROR PI CHANNEL ASSIGNMENTS BITS 10 10 REQESTING 11 INTERRUPT TO11 TO10 DONE ERROR PIO ENABLE 10-1831 Figure 3-9 15 | 14 | 131 12 | 11 RAM:=0 STATH TO 10 | 10| CONI Interface Bit Assignments o9 *DEXWD1 | o8 | 07 | o6 | o5 | 0oa| 03 | 02| STAT REQ | "EBUF SEL | EBUS PAR PDP-11 MEM. 10 INT 0ot | oo DEXON | INTERRUPTS ERROR ON STATH TO STAT 10 STAT PAR STAT 4 TO11 STAT RESTRICTED STAT 11 TO1 10 ERROR REQ INT ERROR DONE NUgL MODE ERROR DONE STOP *DIAGNOSTIC SIGNALS 10-1832 Figure 3-10 15 14 13 12 PDP-11 Status Word - DATI Configuration 11 10 09 o8 o7 06 05 04 03 02 01 00 CLR TO10 CLR TO10 CLR 10 REQ STAT REQ CLR CLR EBUS SET EBUS CLR TON DONE ERROR 11 INT 10 INT TO N1 PAR ERROR [PAR ERROR ERROR DONE STAT 11 TO10 DONE STAT 11 TOt0 ERROR STAT 10 A1 REQ INT CLR PDP N MEM STAT 11 TO 11 DONE PAR ENABLE DISABLE DTE BR DTE BR REQUESTS REQUESTS STAT 11 TO1 ERROR ERROR 10-1833 Figure 3-11 PDP-11 Status Word - DATO Configuration DTE/3-16 For example, to implement the interprocessor doorbell feature, one of the two processors must execute an instruction that sets the Doorbell flag in the Status register (CONO from the EBox, and DATO from the PDP-11). Refer to Table 3-1, Section 3.3. Upon completion of either a TO10 transfer or TO11 transfer, the hardware sets appropriate Status flags to generate error or normal termination interrupts to one or both processors when done. Usually, one of the processors is unconditionally interrupted, and if an additional flag (I Bit) is set, the second processor is also interrupted. The reasons for the interrupts will become clear with some background information on just how the TO11 and TO10 transfers are set up. 3.4.2 STAT 10 TO10 DONE and I Bit In the case of TO10 transfer, the KL10 loads a negative byte count into the RAM FILE in a predefined location (Figure 3-12). The PDP-11 must now load, or have loaded previously, the TO 10 address into a similarly predefined RAM location. Upon detection by the interface that both the byte count and TO10-11 address have been loaded, the transfer starts. The interface reads from the RAM and increments the byte count, and checks to see if the result is zero. If the result is zero, no data is transferred and a flag in the Status register DPS5 10 TO10 DONE is set, causing an interrupt to the EBox. Figure 3-13 shows those Status flags that will cause 10 interrupts. If the byte count after incrementation was not equal to zero, the 10-11 Interface reads a byte of data pointed to by the TO10 PDP-11 addresses using the NPR facility. It then updates this address by one or by two, dépending on whether one or two bytes per PDP-11 word are being transferred. Next, the interface interrupts th- EBox, carries on some dialogue, and transmits to the API FUNCTION 6. This informs the EBox tl... it must take the byte of data. When carrying out continuous transfers, each time the byte count becomes zero, the EBox must supply the interface with a new byte count before transfers can continue. An optional bit (the DPSS 10 I Bit) enables using multiple byte counts between transfers. When a transfer is complete and DPS5 10 TO10 DONE is asserted, the PDP-11 will be interrupted if DPS5 101 Bit is also true. In this case, it is necessary for the byte count as well as the TO10 PDP-11 address to be reloaded. In addition, the TO 10 Byte Count Load flag and the TO10 Address Load flag will be cleared. RAM l.OCATlONS8 0 DELAY COUNT 1 DATA WORD 3 2 DATA WORD 2 3 DATAWORD 1 4 ADDRESS WORD 1 5 ADDRESS WORD 2 USABLE RAM 6 TO10 BYTE COUNT FILE LOCATIONS 7 TO11 BYTE COUNT 10 TO10 ADDRESS 1 TO11 ADDRESS 12 TO10 DATA 13 TO11 DATA . 14 P DIAGNOSTIC REGISTER 15 DIAGNOSTIC WORD 2 ADDRESSABLE 16 STATUS REGISTER REGISTERS 17 DIAGNOSTIC WORD 3 10-1834 Figure 3-12 RAM Words and Registers DTE/3-17 ‘Df DPSS 10 INTR ACT A DPSS5 10 TO1 ERR TERM DPSS 10 TO10 °"‘| ERR TERM "1 D CNT2 TO11 ERR SET 1 1 1 1 OPS5 10 TO10 DPS5 10 TOt1O NORM TERM "‘I NORM TERM c CNT2 TO10 ERR SET CNT1 TO10 DONE SET CNT5 TO11 IBIT (t) — CNT1 TO11 DONE SET 101835 Figure 3-13 Hardware-Generated 10 Interrupts Simplified 3.4.2.1 TOI10 Byte Transfers Basically, TOI10 transfers are performed in the following manner. Flow diagram Figure 3-14 com- plements the outlined procedure: 1. The PDP-11 writes the Delay Count word (DLYCNT) with t:he‘neg‘ative number of 500 ns intervals to delay between byte transfers across the DTE in bits 13-00. Bits 15-14 specify Unibus address bits 17-16 for both TO10 and TO11 byte transfers. The DLYCNT (15-00) may be written at system startup, because it is never reset by the hardware. The PDP-11 writes address of soufce string [TO10AD (15-00)]: The PDP-11 sets the PDP-11 byte or word mode bit (DIAG3 TO10MB). The KL 10 allocates core to receive the string. The KL10 sets up the byte pointer in EPT to receive the data. The KL10 sets negative byte count and indicates that both CPUs are to receive the normal termination interrupt. This starts the transfer. The DTE interface and EBox work as shown in Figure 3-14 during the transfer. 3.4.3 STAT 11 TO11 DONE and I Bit , In the case of a TO11 transfer, both the negative byte count and TO11 PDP-11 address are loaded into the specified RAM FILE locations (Figure 3-12) before the transfer can take place. Again, upon detecting that both the byte count and TO11 PDP-11 address have been loaded, the interface starts up. The byte count is incremented and checked to determine if it is equal to zero. DTE/3-18 BEGIN COPY DLYCNT (13-00) TO COUNTER {13:00} BEGIN DELAY LOOP COUNTER (13-00) _ 4 'NCREMENT COUNTER {13-00) +1 COUNTER - COPY BC {11-00} TO COUNTER (11-00) 500 NS YES TO10BC=0 NO NO rmanMENT TO10BC - TO10BC+1 | — =4 BYTE COUNT : PERFORM DE X BEGIN NORMAL | TERMINATION PERFORM NPR FETCH FROM -11 MEMORY COUNTER : (131 =0 TO10AD- TOV10AD +1 |- INCREMENT -11 ADDRESS |S : DEX COMPLETE DTE GENERATES I10P l INTERRUPT ON EBUS T INTERRUPT -10 REQUEST 100ONLY 0 | INTERRUPT BOTH CPUS YES GRANTED - END DTE EXECUTES IOP NORMAL =~ terminaTiON - API FCN 06 ] KL10 MICROCODE PERFORMS AN IDPB USING TO10BYTE POINTER (EPTTBP) 1 DEX TO11 READY DO DEX DO -11 CHAR I NOTE: IF DEX OCCURS DURING ABYTE TRANSFER. IT IS PERFORMED IMMEDIATEL Y AND DELAY END IS RESTARTED. 10-2526 Figure 3-14 TO10 Byte Transfer Flow Diagram DTE/3-19 If the result is zero, no data is transferred and a flag in the Status register (DPS5 11 TO11 DONE) is set, causing an interrupt to the PDP-11. Figure 3-16 shows those Status flags, which, when set by hardware conditions, will cause PDP-11 interrupts. If the byte count after incrementation was not equal to zero, the interface interrupts the EBox for a byte of data, using a hardware dialogue and API FUNCTION 6. The interface next performs an NPR to PDP-11 memory and updates the TOI1 address by one or two depending on whether one or two bytes per word are being transferred. When carrying out continuous transfers, each time the byte count becomes zero, the PDP-11 must supply a new byte count and possibly a new TO11 PDP-11 address. When a transfer is complete and DPSS 11 TO11 DONE is asserted, the EBox will also be interrupted if CNT5 TO11 I Bit is true. Refer to Figures 3-15 and 3-16. Upon receiving interrupts, the corresponding processor must execute the appropriate instruction to remove the interrupt by clearing the flag. In the case of DPS5 10 TO10 DONE (Figure 315), the EBox performs a CONO to the Status register with bit 30(1). This will clear DPS5 10 TO10 NORM TERM and remove the interrupt. Similarly, to remove the PDP-11 interrupt caused by DPSS5 11 TO11 DONE, the PDP-11 performs a DATO to the Status register with Unibus bit 6(1) and 7(0), to clear DPS5 11 TO11 DONE. ) UNIBUS > 8 \ DPS5 10 INT ACT 1 DPS5 10 NORM TERM K CNT6 CONO SET DPS5 10 NORM TERM C J T 1 K ?r = | DPSS REQ 10 INT J K C 1 = i = INT 1 30 CONO SET CLR | J STATUS LT {DATO> 30 26 E-BUS > 10-1836 Figure 3-15 Program Generation and Clearing of 10 Interrupts Simplified 1| ] 1 DPS5 11 TOM ERR TERM { F SET CNT2 ERR | DPS5 11 TO1i NORM TERM TON SET ! |,SET CNTt DPS5 11 TO40 ERR TERM | TO1Y DONE SET DPSS 11 INT 1 LSET DPSS 11 TO10 NORM TERM |[SET CNT2 TO10 ERR SET DPS5 TOt1O CNT1 TO10 DONE SET — IBIT {1)—] 10-1837 Figure 3-i6 Hardware-Generated 11 Interrupts Simplified DTE/3-20 3.4.3.1 TO1I Byte Transfers - Basically, TO1! transfers are performed in the following manner. Flow diagram Figure 3-17 complements the outlined procedure: 1. The PDP-11 writes the Delay Count word (DLYCNT) with the negative number of 500 ns intervals to delay between byte transfers across the DTE in bits 13-00. Bits 15-14 specify Unibus address bits 17-16 for both TO10 and TO11 byte transfers. The DLYCNT (15-00) may be written at system startup, because it is never reset by the hardware. 2. The KL10 writes address of source string (byte pointer in EPTEBP). 3. The PDP-11 allocates core to receive string. 4. The PDP-11 writes the TO11 receive data [TO11AD (15-00)]. 5. The PDP-11 writes the TO11 Byte Count word (TO11BC), which sets the following: a. b. Negative byte count [TO11BC (11-00)] Indicates that both CPUs are to receive the normal termination interrupt [TO11BC (INT10) = 1] ¢. d. Whether termination is also to occur on transfer of a NULL character [TO11BC (ZSTOP)], PDP-11 byte or word mode [TO11BC (TO11BM)] Writing TO11BC starts the transfer, providing TO11AD has also been written since the last normal or error termination. 6. The DTE interface and EBox work as shown in Figure 3-17 during the transfer. 3.4.4 Status Error Conditions Three error types can cause a transfer error condition that can be detected by the hardware. They are: 1. 2. 3. Unibus timeout errors PDP-11 memory parity errors Ebus parity errors. All of these errors set a general error bit [status (TO10ER) or status (TO11ER)]. Also, all of the errors except Unibus timeout errors have an additional error bit. A bus timeout is most likely caused by an NXM (non-existent memory error) reference, although it can be caused by a variety of hardware problems. 3.4.5 NULL Stop The DTE interface can automatically terminate TO11 transfers when a NULL character is detected. This facilitates the easy handling of string transfers that terminate in a NULL character (e.g., ASCII, MSG). When the DTE extracts the previously loaded byte from the RAM FILE TO11 data slot, it is checked for a NULL character. If it is found, DPS5 NULL STOP and TO11 DONE are both set, generating a bus request (BR) to the PDP-11. The PDP-11 then reads the DTS Status register, finds the NULL bit set and performs a DATO with bit 06 set. This clears the NULL STOP flag. DTE/3-21 BEGIN COPY DLYCNT (1300} TO COUNTER (13-00} BEGIN DELAY LOOP B COUNTER (13.00)- COUNTER (13-00) +1 i 500 NS COPY BC (11-00) TO COUNTER (11-00) NO ' TONIBC =0 TERMINATION TOV1BC. TO118C+1 p = — - INCREMENT l | PERFORM DEX BEGIN NORMAL |ot BYTE COUNT iy DTE PLACES 0P INT NO REQ ON EBUS COUNTER YES (13 =0 B INTERRUPT INTE RRUPT -11 ONt ONLY BOTH CPUS DEX COMPLETE REQUEST GRANTED DTE EXECUTES I10P ° APl FCN 06 | KL10 MICROCODE PERFORMS AN ILDB USING TO11 BYTE POINTER END (EPTEBP) — —=| NORMAL TERMINATION |- TO118C (ZSTOPI =1 FSTORES THE DTE PERFORMS NPR | _ ! BYTE OF DATA TN AN -11BYTE TRANSFER IN -11 ' oR WORD I DTE INCREMENTS TO11AD BY +10R +2 ‘ Figure 3-17 TO11 Byte Transfer Flow Diagram DTE/3-22 10-2525 3.5 RAM OPERATIONS OVERVIEW To perform any of the three basic interface operations, the PDP-11 processor must write control and/or data information into predefined locations in the RAM. Also, for some ofthese operations, the EBox must supply a portion of that information. Table 1-8 contains a list of all of the RAM words, together with an explanation of their basic functions and the PDP-11 address that addresses that location in the DTE interface. Table 3-3 gives a synopsis of the four types of interface operations. For each operation, it provides the following information: PDP-11 Addresses Generated RAM Addresses Generated Name of Each RAM Location Used. Table 3-3 Generalized RAM Storage PDP-11 Address RAM Location 2,4,6,10,12 1,2,3,4,5 Functional Name Operation Deposit or Examine Word Examine 3,2, 1 Ten Address Word 1,2. 2,4,6,10,12 1,2,3,4,5 Deposit or Examine Word Deposit 3,2, 1 Ten Address Word 1,2. 0, 14,20, 24 0,6, 10,12 Delay Count, TO10 Byte TO10 Transfer Count, TO10 11 Address, TO10 Data. 0.16,22,26 0,7,11,13 Delay Count, TO11 Byte TO11 Transfer Count, TO11 11 Address, TO11 Data. 3.5.1 RAM Access and Control , Refer to Figure 3-19, Interface Address and Access Control Simplified. The interface address and access control consists of the RAM, its input and output mixers, Address Selection Logic, input address decoding, outputs to the Data Control register logic, and those timing elements necessary to implement RAM read or write operations. The RAM is addressed via the Unibus, using the high-order four of the least significant five PDP-11 address lines A(04:01). All incoming Unibus addresses are checked to determine if they are interface addresses and if they are RAM addresses. The interface also contains four addressable registers (Section 3.1.5). When the address check detects an interface address and it is a RAM address, RAM Cycle Sync sets, enabling a RAM cycle to take place (Table 3-4). During the period of time that the Unibus address lines are asserted, decoders provide discrete levels to the Data Control register flip-flops. Three pairs of flip-flops synchronize the start of one of the interface operations. The select lines and Data Control register flip-flops are listed in Table 3-5. DTE/3-23 4 E-BUS ) 22 \ DPS5 11 INT 1 1 DPS5 11 TO1! ERR K DPS5 TERM c i 10 SET REQ INT J K c 1 DPS5 11 — DPS5 11 TO1! - J NORM K K J 1 10 T010 TERM c ERR J K 11 6 7 14 TERM o i CNT6 _| CONO SET 0 DPSS 11 TO10 NORM TERM C 1 J v 15 12 13 UNIBUS 10-1838 Figure 3-18 Program Generation and Clearing of 11 Interrupts Simplified / Table 34 RAM Cycle Functions RAM Cycle RAM Sync Cycle 0 0 IDLE 1 0 Synchronizing a request t 1 Reading or writing in RAM 0 | Return SSYN Function Table 3-5 Select Lines and Data Control Interface Operation CNT 2 Select Level CNTS5 Data Register Control FF SELECT ADRI CNTS5 DEP Unibus bit 12(1) SELECT ADR2 CNTS5 DEX START TO11 TRANSFER SELECT TO11 BC CNTSTO11 BCLD TO11 TRANSFER SELECT TO11 ADR CNT5TO11 ADRLD TO10 TRANSFER SELECT TO10 ADR CNT5TO10 ADR LD NOTE TO10BC is set as a result of DATAO from the EBox. This word may also be referenced by the PDP-11 for veri- fication in case of error. However, it is not normally loaded via the PDP-11 processor. DTE/3-24 2LINDSdQ‘b13§+ mKX_No:a_E%mo01vaX1W/fo I4N 0BJISU]S9VA4II0ND3P1vIYSPUE$SX3IW035Y710I[4ND01U0Hm)C3W.TOp1No8IaYzON_y93s19j.NlOod,UXzw_91i._SS182LND8NXIW73S2 % , o t o r f o r o r | w o t f w o | , 8 } | 3 0 | x 3 a 1 8 3 0 0 W 3 0 W ] | 4 0 1 5 AMH0¢W2)IoY2S9vNviLVIgViQ¢IS 930930—21&{1—|b|i—,]4w11133355850¥9oL1vLi+AOQ111i1voi8a —2]IN2DIN—DOVVIIQQ|9 WOQDv01O=VO3T8:038840S4H91VSIQHO9N3I4WW‘OIH14VLSSNIE1I8NUNN3I3TONIS3STNd 4 K w3 93yHAV (1=40VE0) —{9 135 04 01 28 1G239—v5ISQ 10 ¥av + ¥300230 13S VIA ] | ZIND DTE/3-25 dWY 31940 INAS VIND S<N4AI0NVA | 3540 %ATIVWHON 13 WYY SY 2In31§ 61-€ DZ—-mDW JO9OHINOD NIS IHA Y 2IND oOlva I1vg 2¥av vSdQ SNEiNN W Y y 3 l i g m 3o{IY10:IpNODZVE S0NV4BSYI3NILMIANOINYIHSAY3HAAVY ¥Ov £-0 Wy 2IND SdA ‘b 3S 21 S 1090>y ov L2 09 22ZiIINNNDDD 0001L8 OI3l1850¥AQHvVIS380415 2 I N D 9 v i Q € 3 8 0 H 1 S o uikx ——]] 113355 SovNi1gVi¢S SNBIN (1G4 <i020- yv Imsnua_inunsm.|_um Z1I3NDx80i XIW 934~ HOV v —{ 13s uav | 2—| {—s] 1133a5s y1ZMa oL oloL| |1 S04d LHYiS S I N D <0:4>D 0OLvad I1va o—{ 135 A0 IN OD 2LIND 08 38041S v1v0a8d |T OWHOMVLI|NsOnD0g8-H33|1S2199V3431a8| | 3048| WON e1¢m3—as 17830SV 2UX1BLxI38»NSD 1S40 $Sda y WYy <0:si>a V] 1lNndino y9H3AYV In addition. four other Data Control register flip-flops (generic term) are used during 10-11 interface operations: . 2. TOI11 I Bit - This bit enables the interface to interrupt the EBox upon completion of the TO11 transfer operation. TOI11 NULL STOP - This bit enables the interface to stop the transfer upon detecting a NULL character, and generates an interrupt to the PDP-11. 3.-4. TO11 BYTE MODE, TO10 BYTE MODE - These bits define the byte transfers as consisting of 8-bit or 16-bit bytes. TO11 BYTE MODE is set with Unibus bit 13(1) and CNT2 BC STRB. TO10 BYTE MODE is set with Unibus bit 0(1) and CNT2 DIAG 3 STRB. 3.5.2 Write Access Overview 3.5.3 Read Access Overview During DATO operations, the RAM FILE is input from the Unibus via the RAM input mixers. The RAM cycle assures that the RFM SEL 1 and 2 mixer select lines allow the input to come directly from the Unibus D(15:00). Because the operation is DATO, the RAM cycle enables a WRITE pulse at the appropriate time, to write the word from the Unibus into the selected RAM location. During DATI operations, the RAM FILE output is enabled to the Unibus via the UB mixers. The addressing and selection is the same as for DATO except that no WRITE pulse is generated. Whenever a RAM address is decoded in the Access Control Logic, the UB mix SEL 1, 2 select lines allow the addressed locations contents to the Unibus. 3.5.4 Write Access Timing Refer to Figure 3-20, DATO to RAM LOCATION 1. This timing diagram shows the DATO operation beginning with the assertion of the Unibus control and address until the 10-11 Interface generates SSYN, and releases the bus. The PDP-11 asserts the following: A(17:00) = XXXX02 C(1:0) = DATO D(15:00) = DATA. It waits approximately 150 ns, and asserts MSYN. At the interface, the address is checked to determine if it is a valid interface address. When this is true, DPS1 ADR SEL is asserted. The low-order five bits with bit 15 stripped off will be decoded as CNT2 DWI, i.e., A(04:01). The current shift clock sets CNT! RAM CYCLE SYNC, which enables the next shift clock to set RAM cycle. RAM cycle enables INHIBIT CLOCK to set on the next SP clock. This is necessary to prevent any gated clocks from effecting the state of the interface. In addition, RAM CYCLE (1), selects the proper mixer combination (RFM SEL 1) for the DATA on Unibus D(15:00) to be admitted to the RAM. During the cycle, A(17:00) decodes to the proper RAM location. The 10-11 Interface always strips bit 15 from the incoming address, thus the address 02 becomes 01. RAM CYCLE (1) enables the WR clock to write the DATA into the RAM. WR clock +1 removes CNT1 RAM CYCLE SYNC and asserts SSYN. Finally, the third WR clock clears RAM cycle and removes SSYN. Sometime later the PDP-11 drops C(1:0) A(17:00) D(15:00). . B 3.5.5 Read Access Timing By comparing Figures 3-20 and 3-21 it can be seen that the only difference between a WRITE access to the RAM (DATO) and a READ access from the RAM (DAT]) is the generation of CNT1 WR PLS which writes into the RAM. A complete timing diagram for a DATI to the RAM is included as Figure 3-21. DTE/3-26 3 L i u m , v i v a U M X D , L I B I H N I d 3 L V v O L S H T O 0dindiLgV0zo-f¢Wy OL0]v|2 woly Chi-dQd LLl |L L= i _ L] [1I18L(1-dQd0doipN1ASJW831A8p)U3IDI3pwoJj(SNOQLNIWVYWHY1307SIbNOILNY«N_ILS3\d_S3AI9MSL1d mzn_c:xS534pDSpD3jNASWAQsuQGLulwpupsboy NASW HHLIWINWAVN YA%V0 7130S21LNLIDND1U3sM IN3ma ZLND L4IHS AND L 31VIS X132 1LSNSA0BL-INvVA08, LLINDINWVDYH4JMADX73¥21ID+ LUND dS A1 A0 L IND WY OAD Vd03 VTW uoneso|durwi], C LANVDY DTE/3-27 3GI1WVvNON UZ21IINNDD vNAHSNI AANT0O S—| e Sd S vivad S!I 304N0S -L 1INDL UM STd =,302W0Y¥307, JAD ONAS l /L L N L wsi£ugqy 310N LANNDDL¥AM10Md0SE|E[1][ NIND2¥M37A0SWL+ ; L[ @|_ 7 | {\_.Y7$AHDQ5VI31H,4VWIQSLAONI _L1vS¥H4NSL0A’O3-IAMiNVv8A0,V _OJNADS _L%41IHN2SD JWLIvANVDH WLVIvNYD DTE/3-28 ) 3.6 INTERFACE TIMING AND CONTROL The 10-11 Interface timing and control section generates all the timing levels necessary to implement all interface operations. It includes the following: A Major State Generator A Minor State Generator A 3-Phase Gated Clock A 5-Phase Free Running Clock Miscellaneous Combinational Logic. 3.6.1 Clock and Major State Control Refer to Figure 3-22. The interface contains an externally driven, free-running clock. This clock has five phases. The first clock to occur after power up is always SP clock, followed by state clock, state clock +1, state clock +2, write clock, write clock -1, write clock +1, shift clock and the cycle repeats. Four of the eight phases will generate gated phases, providing inhibit clock is false. The gated phases are responsible for advancing major and minor states, shifting or loading DATA, or writing into the RAM. The five basic un-gated phases are necessary for synchronization at all events within the interface. Refer to Figure 3-23. The interface contains three major time states. The first to occur is always DEX followed by TO11 transfer which is followed by TO10 transfer. This sequence repeats in a cyclic fashion until STATE HOLD is present. STATE HOLD enables the appropriate time state to be locked into place and enables the minor state decoder to function. The Data Control Logic senses the conditions to lock the major state, and relays those levels to the State Hold Logic. "EIGHT PHASE cLock"” t0-1841 Figure 3-22 Free Running and Gated Clocks DTE/3-29 STATE HOLD ~ STATE HOLD STATE HOLD ~ STATE HOLD ~ STATE HOLD STATE HOLD 10-t842 | Figure 3-23 Major State Sequencing 3.6.2 Minor State Control and Inhibit Clock Refer to Figure 3-24. Assume that the necessary conditions are present from data control and register gating (CNTS5) at state hold to enable the locking of the TO11 transfer major state. At each GD STATE CLOCK the major state generator changes gates. When it next enters the TO11 transfer major state, this information is passed to the State Hold Logic, together with the input (from CNTS5). The next SP clock sets STATE HOLD. This action locks the interface in the TO11 transfer major state until such time as the transfer is completed, provided that no Deposit or Examine operations have been started. If the interface is locked in the TO11 major state and is in the minor state “CNT4 TO11 DLY CNT INC”, setting DEX START releases the major state and a Deposit or Examine cycle may be taken upon completion of the DEX operation. TO11 transfer sets once again. Having locked the major time state in place, the minor state generator begins to produce a series of sequential minor timing levels. At each GD STATE CLOCK, the minor state generator advances to the next minor state until INHIBIT CLOCK is asserted. This mechanism allows stopping the GD CLOCKS and locking the appropriate minor state. The INHIBIT CLOCK function is used during interrupts to the EBox and during BR or NPR, transfers to the PDP-11, as well as RAM cycles, and for certain diagnostic functions. It facilitates interlocked operation between the interface and the EBox or PDP-11. A more detailed diagram at the minor state decoding is shown on the DTE20 control drawing, Figure 3-2 and a detailed timing diagram of the clock is shown on Figure 3-25, Basic Clock Timing. 3.7 CONTROL STATE TRANSFER PDP-11 Refer to Figure 3-2. During both the TO11 and TO10 major states, data transfers are performed to or from PDP-11 memory. The NPR facility allows this to happen with a minimum of effort on the part of the PDP-11 processor. The abbreviated TO11 transfer sequence is: 1. Read and update delay count (from RAM). NOTE e Rl DEX cycle stealing is allowed at this time. Read and update byte count (from RAM). Send interrupt to EBox for a byte of data. Read TO11 PDP-11 address from RAM. Adjust the byte of data for storage. Store byte temporarily in RAM. Initiate NPR transfer to PDP-11 memory, using the TO11 PDP-11 address. Update the TO11 PDP-11 address as appropriate. DTE/3-30 VARIOUS CONDITIONS 8 PHASE CLOCK GENERATOR STATE CLK | zZ 13 1, yTERNAL 60ns CLOCK | |5 SHIFT CLK a WR CLK———¢ INRIBIT 1 CLOCK WR CLK+1 SP CLK dnnee GD WR CLK CLOCK GEN ._I ——= GD WR CLK H ) WHEN SET DGCLOCKS ATED L GD SHIFT CLK B GATED — STATE HOLD ENABLE LOCKING RELEASE LOCK GD STATE CLOCK ENABLES SWITCHING MAJOR MAJOR VARIOUS CONDITIONS STATES STATE STATE (CNTS) HOLD GENERATOR 6D ENABLES STATE ENARL FeoLD CLK TOI0 SWITCHING STAT STATES TRANS CONTROL STATE LOCKING CLR & MAJOR MINOR NOR DEX TOH_flEE\_\ TO1 SENERATOR — or TO10 DLY INC DISABLES gém%RRA_SrB/-\RTE TAT E MINOR MINOR c ONTR OL STATE ATE CL CLR GENERATOR 'NIENIE —_— DEX N MINOR STATES . " TO10 XFER MINOR STATES \ — . , TO11 XFER MINOR STATES \ VARIOUS MINOR STATE THROUGHOUT THE FUNCTIONS SENT INTERFACE TO CONTROL DEPOSIT, EXAMINE, TO1!4 TRANSFER, TO10 TRANSFER AND INTERRUPTS 10-1843 Figure 3-24 Basic Clock and State Control Simplified DTE/3-31 1 2 STATE CLK I 6D STATE CLK l SYNCHRONIZED EXT CLK GD STATE 1 8 1 | | I \ fl I 3 4 L l 5 | 6 7 j | 8 | l i 1M l 12 L 13 | 14 l 15 1 CLK +1 GD STATE CLK +2 WR CLK -1 [_| J_—l GD WR CLK -1 [_—l N 6D WR cu; WR CLK r—l l_—l fi I——] : WR CLK +1 7 I SHIFT CLK l GD SHIFT CLK - INH i CLK I g ~ Indicates pulse will be missing if CLK INH set. 10-1844 Figure 3-25 Basic Clock Timing Step 7 above occurs during the “TO11 FILE READ” minor state. The signal CNT4 REQUEST indicates that it is a control state byte of request. During this transfer, the GD CLOCKS are inhibited. The NPR/NPG combinational logic, NPG clock and BG/NPG Common Sequence Logic as well as Bus Complete Logic is used. Refer to Figure 3-1. The source of the Unibus address lines, A(17:00) during the NPR transfer is the ABC register. Only when the DTE20 has gained control of the Unibus is this address placed on the Unibus address lines, as indicated by the gating signal NPR BBSY. In the case of a TO11 transfer, the RAM is the data source. It is selected in the Unibus mixers by a select code of 00 in U-B MIX SEL 2 and 1. Direct control over the U-B MIXER SELECTS comes from the access control, and is merely a function of the current address lines. The default case is U-B MIX SEL 2(0) and U-B MIX SEL 1(0). Refer to Figure 3-26, NPR Sequence. The NPR transfer is started when CNT4 REQUEST is asserted. This places NPR on the Unibus and enables the DTE20 to look for a response (NPG). Receiving NPG sets NPG SYNC and 100 ns later, the DTE20 asserts NPG SACK. If DTE/3-32 the PDP-11 processor does not receive SACK within 10 us of issuing NPG, a timeout occurs and NPG is removed automatically by the PDP-11. Next, BBSY and SSYN are tested and if found negated, BBSY is asserted. NPG BBSY gates the contents of ABC (the address) to the Unibus address lines. NPR BBSY starts up the NPR CLOCK, initially for one pulse. This is necessary to generate MSYN and to enable successive NPR CLOCKS, upon receiving SSYN when the PDP-11 memory operation is completed. The reception of SSYN generates CLK RUN which allows a series of clock pulses to finish the operation. The second clock sets WR RAM, but this function is only useful for a TO10 transfer NPR. In that case, the memory reference would have read a byte and sent it to the DTE20. The WR RAM pulse would then write the data into the selected RAM location. The third clock sets CLR CYC 1, which removes MSYN and enables the fourth clock to set CLR CYC 2. CLR CYC 2 drops BBSY and sets BUS DONE. This allows re-synchronization with the main clock (state clock), which now sets BUS COMPLETE. BUS COMPLETE releases the inhibit clock function and the next minor state is entered. Finally. removing the inhibit clock also removes BUS DONE and BUS COMPLETE. The NPR operation during a TO10 transfer works in an almost identical manner. The impetus is from “TO10 FILE WRITE” minor state, which generates CLKS REQUEST. This triggers the NPR sequence. The main difference is that the byte is read from PDP-11 memory and then sent to the DTE20 to be written into the appropriate RAM address. 3.8 DTE DIAGNOSTIC MODE OPERATION In the third mode, (MODE 3), the interface is controlled by a diagnostic program resident in the PDP- 11 processor. In this mode the interface can be single stepped through its internal timing sequence, or placed into a time state and locked there for some period of time as controlled by the diagnostic program. In KL 10 diagnostic mode, the interface can be set up from the PDP-11 to transmit any of up to 128 functions over the diagnostic bus to the EBox in the KL 10, where the appropriate function will be performed in response to the function code sent via the interface. In normal use,the PDP-11 can address the diagnostic section over the Unibus by using DATO and DATI instructions and in this way exercise the interface logic and the EBox as well. Also the EBus can be made to loop back upon itself. Thus, the EBus logic can be effectively checked out within the KL 10. Refer to Figure 3-27. 3.8.1 Diagnosing the 10-11 Interface The interface contains many features that enable diagnosing of the interface. It can be diagnosed in three basic ways: 1. Without using or disturbing the EBus 2. With loopback on the EBus but without-the KL10 or without the KL 10 running 3. With the KL10 running. The interface is checked out primarily in a single-step manner. Full speed operation may only be checked with a running KL 10. DIAG Word 1 contains the Diagnose 10/11 Interface bit. When this bit is set, the following occurs: The interface clock is disabled and single step operation begins. Interrupts are inhibited from being sent to the KL10. The interface operates in the normal manner except that EBus operations never complete because no interrupts are issued to the KL 10. Therefore, a bit has been provided that allows setting of the EBus complete, allowing the operation to continue. The interface control is run by an up-counter and three decoders. The decoders are selected by the major state flip-flops. The up-counter is loadable by the rightmost 4 bits of DIAG Word 2. This enables any minor logic state to be executed. The major states are not loadable. However, they naturally cycle until a condition occurs that indicates that an operation is ready to take place. These major state bits are readable. The diagnostic can lock any major state on by bit 07 of DIAG Word 2. DTE/3-33 “NPR REQUEST” CONTROL STATE TON | REASON FOR NPR ( SYNC FROM 11 MEMORY FL RD | READ NPR N ) [~ NPG BYTE A TOIO F1 WR | WRITE BYTE J\JI NPG NG SACK NG > BBSY DLY TO11 MEMORY NPG Vs SACK ~BBSY SET L I it BBSY " N ! “ENABLE B CLK FOR s 1 PULSE" NPR CLK 1ST CLK SETS NPR CL R START SSYN CLK RUN SET] MSYN NG senD 1> MSYN * CLR . 2ND CLK SETS WR . 3RD . ? CLK SETS RAM BUS DONE |] sus | DONE COMP sgzl'?sETSESRED BY ABC cLrR cYe 2 BUS FROM 11" AS “BYTE TO OR g[: SETS CLR CYCH \7 |SET BUS coMP LSTATE CLK Figure 3-26 10-1845 NPR Sequence DTE/3-34 2IndiqLz-€payndungsnsouderq[euonounyweugei(q ,3HOHLSS~ISNVO0%0L 343181934 d344n8 (u/o)1— (6s10a) £4N0 H3ILSYN 3O7N0V4VGL~1i 34V Q@3SN Ilva > N \V v Ww oD N b} Od+—a DTE/3-35 "°2| AIxNn3vSi VVviivVa OWLOH34¥334SNnBd 41 ON3S {0) um ‘N2010 T0LH1ISN0dO3D02A19N0V7 aSON313I3s¥sH3N3nMHv4LI0QNL30831H3H1L7O31NI8IS¥Hv34NY433GA0N398V-sIH3QnLgI033 NLOIlSN3NV8GX3IN3S $I3dIaLv~s}INVa 010X3dLdd0NlYSHILNI 319077 9VIa‘17019VIA‘01I%<9:0>Q9VIQWOD1HVLUSM%070L+ ! <9:0>0 $“T301H8MvI-sN3IOyaD3snS8N-B3‘'XoSvNVIviQNHVOLGIML£OO0NVSDJGN3S 3snd 3—.wom3SS38s2aNinN1Oo<SaIwN3{LWL919VO03v8:INy1La0s5SS58n)E0a043Y1Smg93gm|-T]omoJ9uAViOIs—WQo3SI«cNrxeo3Sr8Nm018VI1wS5|AN3S|LI/0VNJLAYO1WS]|040O1T[02lSHW1yOLOv9NIi90DJ3N1vs1ON7VLDDI9gSV€ONN3391V0IGO0N1AS9S0O-N0OV8IdaQ43151934]s¥onvvg3iIIaNTnoJH430SN7H01I198I%1NNI1<Z1O0S008.D:hv5m1(>.Va)m__N_\oo D2Z-mOn o<ard 1 {l > LOZFHXOJ -—- 3.8.2 Diagnostic Control Logic Most of the diagnostic control logic along with the diagnostic bus is contained on the bus control print. The diagnostic bus contains 10 lines. Diagnostic select lines. The PDP-11 sends encoded diagnostic functions DS 00-06 to the KL10 on these lines. These lines can be read by the PDP-11 at any time even while the rest of the EBus is active for other devices. STROBE Diagnostic strobe. This line is asserted to indicate that the diagnostic select lines are stable, and that the indicated function should be performed. REMOVE STATUS When true, causes the KL10 to disable the basic CPU status from the DS lines, switch the translator (only for DS lines) to convert TTL to ECL, and put the EBus translator under control of DS bits 00 and O1. Four control bits are associated with the diagnostic logic. These may be set via the Unibus by a DATO to the Diagnostic register. 1. Diagnostic 10-11 controls: a. State hold in conjunction with DS00 b. Inhibit clock, in conjunction with single pulse C. EBus dialogue, i.c., A’CKNOWLEDGE, TRANSFER, DATAXX (PHYS CONT NO.) E-Mixer Select in conjunction with both DS02 which controls MIX SEL 1 and DSO1 which controls MIX SEL 2 This bit (although not pbart of the diagnostic bus) is used to check out the 10-11 Interface without disturbing the KL10. Diagnostic a. b. KL 10 controls: E-Buffer Select, in conjunction with DEX Address 2 Bus Selection (X, Y, Z, A), in conjunction with DIAG SEND PI0! -07 and KL10 stopped Can prevent CLK inhibit and/or CLKS TRANSFER REQ. This bit can be used with the 10/11 bit to check out the 10-11 interface and EBus logic. Diagnostic Command Start controls: a. Enables strobe for one diagnostic cycle, then clears Diagnostic Command Start, as well as the Diagnostic register in the DTE upon transmission of the diagnostic function to the KL10. DTE/3-36 4. DIAG Send controls: a. 3.8.3 Enables diagnostic data transfers via the EBus to the KL10. When clear, diagnostic data transfers from the KL 10 are possible. Diagnostic Programming Synopsis The following is a brief synopsis of how to proceed to program a 36-bit data transfer both to the KL10 and to the PDP-11. Also, Figure 3-28 presents an overview of the diagnostic bus operations. 1. Diagnostic Write - The DIAG KL10 bit should first be set. If it is not set, the interface will hang up waiting for interrupt service. A Deposit operation should be set up and performed. The address portion of the sequence may be loaded with any value as this information is not used. The interface will then load the E-Buffer with the data that was previously placed into the RAM Deposit data locations (DEX WD 1-3). Next, the appropriate diagnostic select bits, DIAG Send and DIAG Command Start, should be set. This will cause the data to be sent over the EBus to the KL10. 2. Diagnostic Read - A command with the appropriate diagnostic select bits should be sent. The DIAG KL10 bit and function code (DS00-06) to control the transfer. The diagnostic program must sample the DEX DONE bit before attempting to read or load information. When this bit is set, the data may be read from the interface using the same bit assignments as with an Examine or Deposit. DTE/3-37 DIAGNOSTIC BUS IS USED IN THREE WAYS DIAG CPU DIAG FUNCTION ONLY STATUS READ 1 DATA TO KL10 PDP.11/40 DOES A LOAD REGISTER OPERATION DIAG FUNCTION WITH 36-81T TRANSFER TO DIAG 1 WITH: UBUS DO07-00 = ~EBUS REMOVE STATUS, ALL OTHER UBUS D BITS = 0 PDP-11/40 LOADS DIAG 1 WITH {UBUS 15:09 PDP-11/40 MUST LOAD DEX WD1, WD2 DATA TO THE DESIRED FUNCTION: and WD3 KL 10 PDP-11/40 SETS DIAG KL10 IN DIAG1 DPS6 ADR 4:1: CNT2SEL DIAGY: CNT2 DIAG 1 STRB: ENABLE EBUS THE ENCODED FUNCTION IS PLACED DATA ON THE EBUS DS LINES. EBUS PDP-11/40 LOADS DIAG REG1 WITH THE CNT2 DIAG 1 STRB DIAG STRB IS THEN ASSERTED TO DIAG FUNCTION, DIAG KL10 (UBUS D03} CNT3 UN DAT 03 /ACNT2 DIAG 1 STRB: INDICATE THAT THE DS LINES ARE AND DIAG COM START {UBUS D0O!}. CNT3 DIAG KL10{1) | -DIAG 1) TO ENABLE BASIC CPU STATUS - UNIBUS CNT3 DIAG DS 00:06 - EBUS DS 00:06 CNT3 DIAG COM START (1} A CNT? WR CNT3 STROBE {1): EBOX CLOCK 1S EBUS DIAG STROBE UBUSD _ 00 15 0 1 =1 KL10 RUN FF 02 13 O NoT UseD RUNNING 04 05 0% 12 TO DEX MAJOR STATE DPS6 ADR 4:1 : CNT2 SEL ADR 2N\ PILEVEL IN PROGRESS CNT3 DIAG SEND {0} N\ CNT3 DIAG KL10: DROP STROBE CNT3 DIAG CLR {1}: CLRS DIAG REG? STROBE (0} CNT4 DEX/\CNT 5 DEX START {1} = LOCK 1S GENERATED AND NO AP1 WORD DECODED BY THE KL 10. THE REQUESTED DATA IS PLACED ON THE EBUS ' THE EBUS DS LINES = DIAG FUNCTION {DIAG FUNC 1S SPECIFIED) THE EBUF IS ENABLED - EBUS THE KL10 BY DIAG STROBE CNT3 DIAG KL10/\ CNT3 DIAG SEND: CNT6BUSSEL A, X, Y, 2 CNT3 DIAG CLR TIME THEREBY CNT4 DEX {1) ACNTS DEX START: COMPLETING THE OPERATION CNT4 STATE HOLD (1): LOCK DEX ! I rHiis 1s NOT A REAL CNT4DEX ADR 2 {1}/ ~CNT3 -KL10 DIAG KL10 (0} : NOINTERRUPT VIA TRANS REQ AND NO CLOCK INHIBIT. | WHEN DIAG COM START CLEARS, THE EXECUTED BY THE KL10 {BEGINS OPERATION) DIAG REG1 CLEARS ITSELF AT THE DIAG FUNCTION IS RECEIVED AND AND NO INTERRUPT 1S GENERATED DIAG FUNCTION IS 3} DIAG SEND (UBUS D02) 4) DIAG COM START (UBUS D00} IS SENT. CAN EVALUATE DATA CNT7 WR CLK +1: CNT2 DIAG CLR (0} AS USUAL AFTER DEX ADR 2 FOR BUS COMP, AS NO INTERRUPT INTO DEX MAJOR STATE THE DEX MINOR STATES ARE NOT HELD DIAG CLR IS DROPPED {WHERE TO STORE DATA} ALSO: UBUS D07=1 {REMOVE STATUS!} 2) SET DIAG KL10 (UBUS DO3) THE MINOR STATES ARE NOT HELD PDP-11/40 PROGRAM AT WR CLK +1 1) DIAG FUNC ON UNIBUS D15:00 (DIAG WD1) THE DIAG FUNCTION IS STROBED TO DTE LOCKS IN DEX MAJOR STATE. : CNT3STROBE (1)N\ CNT7 WR CLK (1} THE DEX DONE STATUS AND LOADS DIAG1 (FAKE DEPOSIT DOES THIS) CNT5 DIAG EXAM CNT5 DEX START (1) CNT3 DIAG COM START (0}: CNT3 ! CNT2 DATO : CNTS DEX START (1} CNT3SYNC (1): CNT5 DEP {0): CLEAR DIAG REGT AND THE POP-11/40 LOOPING PROGRAM SEES WITH THE FOLLOWING: AND EXAMINE CNT5 DIAG EXAM/\CNT7 STATE CLK + 2N 0 1 10 9 DEPOSIT OPERATION CLK (1): CNT3SYNC (1), USAGE (1) os 03 PDP-11/40 INITIATES A DTE IS FORCED TO LOCK CNT3SYNC {1)/ACNT7 WR CLK (1) STATUS BITS: CNT4 DEX DONE: CNTS DEX START (0) (DUMPS EBUS TO EBOX) TION SHOULD BE PERFORMED. AFTER 1 US, PDP-11/40 CAN READ OP (DAT! DPS6 ADR 4:1 : CNT2 SEL DIAG 1: STABLE AND THE INDICATED FUNC LINES WITH A DIAG REG 1 READ THE DEX START FF UBUS D00 = 1 (DIAG COMMAND XFER DATA FROM KL10 -DIAG 1 REG (CNT3) TO DEX DONE AND RESETS WORD - DS 00:06) AND START) ! - RAM WITH 36-BIT DEX MINOR STATE STEPS DATA AS PER DIAG FUNC_I INTERRUPT DIALOGUE, —| AS THE REAL | DIALOGUE REQUIRES LMlCROCODE TO EXIST. THE 36-BIT WORD IS LOADED REQUESTED DATA WILL BE IN RAM INTO THE E BUFFER DURING LOCATIONS DIAG WD1, WD2 AND WD3 MINOR STATES DEX WD2, | THE KL10 LOADS THE WD2, AND WD3 PDP-11/40 PROGRAM DOES DEX DONE AND FETCHES DATA 10-2827 Figure 3-28 DTE/Diagnostic Bus Operation Flow DTE/3-38 - ABBREVIATIONS AND A Address ABC Address and Byte Count ACLO AC Line Low ACT Active ACK Acknowledge ACKN Acknowledge ADR Address API Arithmetic Processor Interrupt BBSY BC BG Bus Busy Byte Count BR Bus Grant Bus Request C CLK CLR CNT CON CONI CONO CS CYC Control Clock Clear Control Condition Conditions In Conditions Out Control Select Cycle D DAT DATAI DATAO DATI DATO DCLO Data Data Data In Data Out Data In Data Out DC Line Low DEP DEPST DEX DIAG DIS Deposit Deposit and Examine Diagnostic Disable DLY DPS DS Deposit Delay Data Path and Status Device Select DTE/A-1 APPENDIX A MNEM ONICS EBH EBUF EBUS EMIX EN ERR EXAM Execution Buffer Hold Execution Buffer Execution Bus Execution Buffer Mixer Enable Error Examine Function GD Good High I BIT Interrupt Bit INC INH INIT INTER Increment Inhibit INTR IOP Initialize Interrupt Interrupt Input/Output Pulse Low LD LT Load Left MIX MSYN Mixer Master Master Sync NPG Non-Processor Grant NPR NULL Non-Processor Request ASCII Code of Zero OoP Operation PA PAR Parity Parity Parity Physical Priority Interrupt Priority Interrupt A ssignment Pulse Power MST PHY PI PIA PLS PWR RAM RD RDY REC REG REQ RFM RG ROM Random Access Memory Read Ready Receive Register Request Ram File Mixers Register Read Only Memory DTE/A-2 SACK SEL SHF SP SSYN Slave Acknowledge Select Shift Special Slave Sync ST STRB SW State Strobe Switch TO10 TOl1 TRAN TRANS To the KL10 (direction) To the PDP-11 (direction) UB UN WD Transfer Transfer Unibus Unibus Word WR Write XFER Transfer DTE/A-3 DTE MANUAL INDEX A ABC Register, 2-1, 2-23, 2-28, 2-33 Access Control Logic, 3-4 ACK, 1-18, 1-19 Acknowledge, 1-18, 1-19 Control Lines, 1-17 Control Section, 3-4 Access Control, 3-4 Data, 3-6 Diagnostic 3-36 KL10 EBus, 3-5 Address TO10, 2-26, 2-33 TOl11, 2-18 Addressable Register, 1-20, 1-21 Address Word, 1-35, 1-36, 2-6, 2-7, 2-17 Address Lines, 1-16 API Function, 2-4, 2-18, 2-23, 3-7, 3-8 Arbitration, 2-4 B BBSY, 1-17, 2-5 BG, 1-17 BR, 1-12, 1-13, 1-15, 1-17 Bus Dialogue, 2-17, 3-5, 3-12 Bus Interfacing, 2-1, 2-4 EBox Side, 2-4 PDP-11 Side, 2-1 Bus Operation Multiple, 1-35 Single, 1-35 Bus Transactions, 3-6 KL10 Rings Doorbell, 3-7, 3-8 PDP-11 Rings Doorbell, 3-6, 3-7 Byte Count, 2-5 Negative, 1-25 TO10, 2-26, 2-28 TOl11, 2-18, 2-19 Byte Transfer Functions, 1-9 C Clock, 3-29 Inhibit, 3-30 Major State, 3-29 PDP-11 BR, 3-5 PDP-11 NPR, 3-5 Timing, 3-5 Control State 3-30 CS, 1-16, 1-17, 1-19, 2-4 D Data Control Register, 3-6 Data Lines, 1-16, 3-1 Data Paths, 3-1 Data Transfer, 1-13 Control Buffering, 1-20 Implementation, 2-4 Signals, 1-16 Data Word, 1-36, 2-6, 2-7 DATAO DTE Function, 1-25 Delay Count, 2-18, 2-19, 2-23, 2-26, 2-28 Delay Count Word, 1-36 DEM, [-18, 2-4 Demand, 1-18, 2-17, 2-18 Deposit Data Word Setup, 2-8 Operation, 2-8 Overview, 2-6 Protected, 1-3 Word Formats, 1-22 Device Select Code, 2-4 DEX, 3-6 DIAG WD 1, 1-30, 3-1 DIAG WD 2, 1-32, 3-1, 3-4 DIAG WD 3, 1-33, 2-26, 3-1, 3-4 Diagnostic, 3-33 Bus Control 1-10 Bus Drivers, 3-4 Minor State, 3-30 Communication Control Logic, 3-36 CPU Status Read, 1-10 Functions, 1-10, 1-12 Interface, 1-12 Interprocessor, 1-14 KL10 Region, 1-2 PDP-11 Region, 1-2 CONI DTE Function, 1-26 Overview, 1-10, 1-11 Programming, 3-37 Word 1, 1-30, 1-31, 3-1 Word 2, 1-20, 1-32, 3-1, 3 -4 Word 3, 1-20, 1-33, 3-1, 3-1, 3 3-4 CONO DTE Function, 1-27 Control Buffering, 1-20 DTE/I-1 Dialogue EBox Interrupt, 3-9, 3-10, 3-12 KL10 EBus, 3-5 KL10 Interrupt, 3-8 PDP-11 BR, 3-5 PDP-11 Interrupt, 3-6 PDP-11 NPR, 3-5 Doorbell Function, 1-6, 2-5, 3-6, 3-8 Basic Transaction, 3-7 KL10 Rings, 3-8 PDP-11 Rings, 3-6 Summary, 3-13 E E-Buffer, 2-8, 2-23, 2-24, 2-26, 3-8 EBox Interrupt Dialogue, 3-9, 3-10 EBus Drivers, 3-1 Interrupt Dialogue, 3-12 KL10 Dialogue, 3-5 Priority Transfer Lines, 1-18 Receivers, 3-4 Signal Lines, 1-17 H Hardware Operations, 1-35, 2-6 I I Bit, 3-17, 3-18 Inhibit Clock, 3-30 INIT, 1-17 Instruction Implementation, 2-4, 2-5 Interface Communication, 1-12 Interface Control, 3-29 Interface Data, 1-20 Interface Status, 3-13 TO10 DONE, 3-17 TOI11 DONE, 3-18 Interface Timing, 3-29 Clock, 3-29 Inhibit Clock, 3-30 Major States, 3-29 - Minor States, 3-30 Interfacing EBox Side, 2-4 PDP-11 Side, 2-1 Interrupt, 1-17, 2-17 Dialogue, 2-11 EPT, 1-3 Error, 1-9, 3-21 Examine Operation, 2-17 Overview, 2-17 Protected, 1-3 Extension Bits 1-16 F Formats Deposit Word, 1-22 Examine Word, 1-22 TO10 Transfer Word, 1-23 TOI11 Transfer Word, 1-24 Front End, 1-1 Privileged, 1-3 Resricted, 1-3 Function, 1-19 Byte Transfer, 1-9 Code, 2-4 CONI DTE, 1-26 CONO DTE, 1-27 DATAO DTE, 1-25 DATI DTE Status, 1-29 DATO DTE Status, 1-28 Function Lines, 1-18 Functional Operations, 2-6 Functions KL10 Diagnostic, 1-10 EBox, 3-12 Facility, 2-17 Information, 3-1 K110 Dialogue, 3-12 Logic, 2-4 PDP-11 Dialogue, 3-6 Processor Procedure, 1-14 Requests, 1-13 Introduction, 1-1 K KL10 Diagnostic Functions, 1-10 L Logic \ Common Sequence, 3-32 Control State Timing, 3-5 Data Control Register, 3-6 Descriptions, 3-1 Interface Control, 2-1, 2-4, 2-8 M Major State Clock, 3-29 Major State Control, 3-29 Major State Sequence, 3-29 Minor State Control, 3-30 Minor State Inhibit Clock, 3-30 MSYN, 1-35, 2-5 DTE/I-2 N NPG, 1-17 NPR, 1-17, 2-22, 3-5, 3-34 NULL, 2-26, 3-21 0 Operation Register Addressable, 1-20, 1-21, 3-1, 3-4 Data Control, 3-6 Decoder, 2-5 Non-Addressable, 3-1, 3-4 Requests Interrupt, 1-13 Multiple Bus, 1-35 Single Bus, 1-35 Overview Byte Mode TOI10, 2-26 Byte Mode TO11, 2-18 Byte Transfer, 1-9 S SACK, 1-17 SSYN, 2-5 Status Information, 3-1, 3-13, 3-17 Error Conditions, 3-21 Interface, 3-12 TO10 DONE, 3-17 Communication Regions, 1-2 Data Transfer, 2-4 Deposit, 1-6, 2-6 TOI10 Transfer, 3-17 TOI11 DONE, 3-18 Diagnostic, 1-10 Error, 1-9 Examine, 1-5, 2-17 Functional Operations, 2-6 Interrupt Dialogue, 2-11 Programming, 1-4 RAM Operations, 3-21, 3-23 Read Access, 3-26 TO10 Transfer, 2-26 TOI!11 Transfer, 2-18, 2-19 TO11 Transfer, 3-18 Status Register, 2-5, 3-4 T Timing Inhibit Clock, 3-30 Interface, 3-29 Major State, 3-29 Minor State, 3-30 Word Mode TO10, 2-28 Word Mode TOI11, 2-19, 2-23 Write Access, 3-26 P Parrity Error, 1-16 Priority Interrupt, 1-4 Channel Number, 2-4 Level, 2-4 Priority Transfer Lines, 1-17, 1-18 RAM Read Access, 3-26 RAM Write Access, 3-26 TO10 DONE, 3-5, 3-17 TOI10 Transfer, 2-26 Byte Mode, 2-28 Overview, 2-26 Word Mode, 2-28 TOI11 DONE, 3-5, 3-18 TOI11 Transfer, 2-18, 2-19, 2-23 Byte Mode, 2-18 Processor (Front End), 1-1 Programming Operation, 2-23 Overview, 2-18, 2-19 Examples, 1-36 Overview, 1-4 R RAM, 1-20, 2-6, 2-17, 2-18, 2-19, 3-1 Access and Control, 3-23 Cycle Functions, 3-24 Data Control, 3-24 Word Mode, 2-18 Transfers, 1-18, 1-19 Control State, 3-29 Data, 1-13 Diagnostic Functions, 1-12 Interface Operations, 2-1 NPR, 1-12, 1-13, 1-16, 1-17 TO19Q, 2-26, 3-18 FILE, 1-35, 1-36 Operations Overview, 3-23 Read Access, 3-26 Select Lines, 3-24 Storage, 3-23 Timing, 3-23, 3-26 Write Access, 3-26 TO11, 2-18, 2-19, 3-21 U Unibus Priority Transfer Lines, 1-17, 1-19 Signal Lines, 1-14 DTE/I-3 A% Vector Interrupt Locations, 1-19 X XFER, 1-18, 1-19 W Word Formats API, 1-4, 3-8 \ - Deposit, 1-22, 2-9 Examine, 1-22, 2-9 PDP-11 Status, 3-16 TOI10 Transfer, 1-23, 2-30 TOI1 Transfer, 1-24, 2-21 DTE/I-4 Reader’s Comments DTE20 Ten-Eleven Interface Unit Description EK-DTE20-UD-003 Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of our publications. 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