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DEC-15-H2DC-B

September 1973

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Document:	PDP-15 User's Handbook Vol.1 Processor
Order Number:	DEC-15-H2DC-B
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Pages:	183
Original Filename:	http://bitsavers.org/pdf/dec/pdp15/DEC-15-H2DC-B_UsersHbkVol1.pdf

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Digital Equipment Corporation
Maynard, Massachusetts

PDP-15 Systems

User's Handbook
Vol.1 Processor

DEC-lS-H2DC-B

PDP-15 SYSTEMS
USER'S HANDBOOK
VOLUME 1 PROCESSOR

DIGITAL

EQUIPMENT

CORPORATION • MAYNARD, MASSACHUSETTS

1st Edition, September 1970
2nd Printing {Rev} November 1970
3rd Printing {Rev} April 1971
4th Printing, June 1973

The material in this manual is for information purposes and is subject to change without notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL

PDP
FOCAL
COMPUTER LAB

PDP-15 FAMILY OF MANUALS

HARDWARE

SOFTWARE

* Separate maintenance manuals are
available for peripheral equipment.

iii

SYSTEMS REFERENCE MANUAL - Provides overview
of PDP-IS hardware and software systems and options,
instruction repertoire, expansion features, and descriptions
of system peripherals. (DEC-IS-BRZC-D)

PDP-IS/30/40 BACKGROUND/FOREGROUND MONITOR SOFTWARE SYSTEM - Describes Background/Foreground Software System including the associated language,
utility, and applications program. (DEC-IS-MR3A-D)
RSX USER'S MANUAL - Describes the disk-oriented
real time system executive language and applications.

USER'S HANDBOOK VOLUME 1, PROCESSOR - Principal guide to system hardware includes system and subsystem features, functional descriptions, machine-language
programming considerations, instruction repertoire, and
system expansion data. (DEC-IS-H2DC-D)

MAINTENANCE MANUAL VOLUME 1, PROCESSORProvides block diagram and functional theory of operation
of the processor logic; lists preventive and corrective maintenance data. (DEC-IS-H2BB-D)

VOLUME 2, PERIPHERALS -Features functional descriptions and programming considerations of peripheral
devices. (DEC-IS-H2DC-D)

VOLUME 2, ENGINEERING DRAWINGS -Provides engineering drawings and signal glossary for the basic processor
and options. (DEC-lS-H2BB-D)

OPERATOR'S GUIDE - Lists procedural data, including
operator maintenance, for using the operator's console and
the peripheral devices associated with PDP-IS Systems.
(DEC-IS-H2CB-D)

INSTALLATION MANUAL - Provides power specifications, environmental considerations, cabling, and other
information pertinent to installing PDP-IS Systems.
(DEC-IS-H2AB-D)
ACCEPTANCE TEST PROCEDURES - Lists step-by-step
procedures designed to insure optimum PDP-IS Systems
operation.

PDP-IS/IO SYSTEM USER'S GUIDE - Features
COMPACT and Basic I/O Monitor operating procedures.
(DEC-IS-GG lA-D)

PDP-IS MODULE MANUAL - Provides characteristics,
specifications, timing and functional descriptions of modules used in PDP-IS Systems. (DEC-lS-H2EA-D)

PDP-IS/20 SYSTEM USER'S GUIDE - Lists Advanced
Monitor System operating procedures. (DEC-IS-MG2B-D)

INTERFACE MANUAL - Provides information for interfacing devices to a PDP-IS System. (DEC-IS-HOAB-D)

BACKGROUND/FOREGROUND MONITOR SYSTEM
USER'S GUIDE - Lists operating procedures for the DECtape and disk-oriented Background/Foreground monitors.
(DEC-IS-MG3A-D)

UTILITY PROGRAMS MANUAL - Provides utility programs common to PDP-IS Monitor systems.
(DEC-IS-YWZA-D)

PDP-IS/IO SOFTWARE SYSTEM - Describes COMPACT software system and Basic I/O Monitor System.
(DEC-IS-GRIA-D)

MACRO-IS - Provides MACRO assembly language for the
PDP-IS. (DEC-IS-AMZA-D)

PDP-IS/20/30/40 ADVANCED MONITOR SOFTWARE
SYSTEM - Describes Advanced Monitor System; programs
include system monitor language, utility, and application
types; operation, core organization, and input/output operations within the monitor environment are discussed.
(DEC-IS-MR2B-D)

FORTRAN IV - Describes PDP-IS version of the
FORTRAN IV compiler language. (DEC-IS-KFZB-D)
FOCAL-IS - D~scribes an algebraic interactive compiler
level language developed by Digital Equipment Corporation. (DEC-IS-KJZB-D)

CONTENTS
Page
CHAPTER 1

SYSTEM DESCRIPTION

1.1

System Software

1-1

1. 1. 1

Introducti on

1-1

1 • 1 .2

PDP-15/20 Advanced Monitor System

1-2

1 .1.3

PDP-15/30 Background/Foreground Monitor

1-3

1 . 1 .4

PDP-15/40 Disk-Oriented Background/Foreground System

1-4

1 .1.5

PDP-15/10 COMPACT Software System

1-4

1 . 1 .6

PDP-15/10E Basic I/O Monitor

1-5

1 • 1 .7

PDP-15/20 Advanced Monitor System

1-5

1. 1.8

PDP-15/30 Background/Foreground Monitor System

1-9

1 • 1 .9

PDP-15/35 Real-Time System Executive

1-10

1.1.10

PDP-15/40 Disk-Oriented Background/Foreground Monitor
System

1-10

1.1.11

Additional Systems Software

1-10

1.2

PDP-15 System Configurations

1-11

1 .2. 1

PDP-15/10 Basi c System

1-11

1.2.2

PDP-15/20 Advanced Monitor System

1-12

1.2.3

PDP-15/30 Background/Foreground System

1-13

1.2.4

PDP-15/35 Real-Time System Executive Disk-Oriented
System

1-13

1 .2.5

PDP-15/40 Disk-Oriented Background/Foreground System

1-13

1.3

System Organization

1-13

1 .3. 1

Central Processor (CPU)

1-14

1.3.2

Memory

1-14

1.3.3

I/O Processor (IPU)

1-15

1.3.4

Console

1-15

1.3.5

System Peripherals

1-15

CHAPTER 2

PROCESSOR ORGANIZATION

2. 1

Central Processor Description

2-1

2. 1 . 1

Internal Registers

2-1

2.1.2

Control Console

2-4

2.2

Central Processor Expansion Options

2-4

2.3

I/O Processor Organizati on

2-6

2.3. 1

Data Transfer Facilities

2-9

CONTENTS (Cont)
Page
2.3.2

I/O Processor Activities

2-11

2.3.3

I/O Processor Organizati on

2-12

2.4

Core Memory

2-14

2.4.1

Memory Data Transfer

2-15

2.4.2

Parity

2-15

2.4.3

Memory Modularity

2-16

2.4.4

Memory Addressi ng

2-16

2.4.5

Memory Port Switch

2-16

2.4.6

MX15-A Memory Bus Multiplexer

2-17

CHAPTER 3

INSTRUCTION FORMATS

3. 1

General

3-1

3.2

Memory Reference Instructi on Format

3-1

3.3

Augmented Instructi on Format

3-2

3.4

Timing

3-2

3.5

Memory Reference Instructi ons

3-3

3.6

Augmented Instructi ons

3-12

3.6. 1

Operate Instructi ons

3-12

3.7

Input/Output Transfer Instructi ons

3-28

3.7.1

PDP-15 lOTs

3-30

3.7.2

Teletype Keyboard

3-32

3.7.3

Teletype Teleprinter

3-32

3.8

Index Instructi ons

3-33

CHAPTER 4

ADDRESSING FEATURES

4. 1

Introduction to Memory Addressing

4-1

4.2

Types of Add ress i ng

4-1

4.3

Description of the Types of Addressing

4-3

4.3.1

Di rect Addressi ng - Bank or Page Mode

4-4

4.3.2

Indirect Addressing - Bank or Page Mode

4-4

4.3.3

Auto-Increment Addressing - Bank or Page Mode

4-5

4.3.4

Indexed Addressing - Page Mode Only

4-6

4.3.5

Indirect Indexed Addressing - Page Mode Only

4-8

4.3.6

Auto-Increment Indexed Addressing - Page Mode Only

4-9

CO NTE NTS (Cont)
Page
4.4

Special Addressing Cases

4-10

4.5

Processor Addressing

4-11

CHAPTER 5

I/O PROCESSOR SYSTEM

5.1

Genera I Descri pti on

5-1

5.2

I/O Processor Priority Structure

5-3

5.3

The Data Channel Controller

5-3

5.4

Multicycle Channel Block Transfer

5-3

5.5

Single-Cycle Block Transfers

5-8

5.6

Increment Memory

5-9

5.7

Add -To-Memory

5-9

5.8

Program-Controlled Transfer

5-9

5.9

Program Interrupt Faci I ity

5-11

CHAPTER 6

OPTIONS

6.1

KE15 Extended Arithmetic Element

6-1

6.1.1

EAE Mi croi nstructi ons

6-2

6.1.2

EAE Shifti ng Instructi ons

6-13

6.1.3

EAE Arithmeti c Instructi ons

6-20

6.2

KM 15 Memory Protect

6-33

6.3

KT15 Memory Protect and Relocate

6-37

6.4

MP15 Memory Parity

6-41

6.5

KF15 Power Fail Option

6-42

6.6

KW15 Real-Time Clock Option

6-42

6.7

KA 15 Automatic Priority Interrupt

6-46

6.7.1

API Hardware

6-47

6.7.2

API Instructi ons

6-48

6.7.3

Programming Considerations

6-49

6.7.4

Programming Examples

6-53

6.8

FP15 Floating-Point Processor

6-55

INSTRUCTION SUMMARY

A-l

APPENDIX A

vii

ILLUSTRA TIO NS

Title

Art No.

Page

1-1

PDP-15 System Organization

15-0174

1-14

1-2

System Organization

15-0017

1-16

2-1

Central Processor I Simplified Block Diagram

15-0002

2-2

PDP-15 System with Memory Protect Option

15-0175

2-6

2-3

Memory Protect Block Diagram

15-0179

2-7

2-4

Memory Protect and Relocate Block Diagram

15-0178

2-8

2-5

Data Transfer Facilities

15-0180

2-9

2-6

I/O Processor Block Diagram

15-0181

2-13

2-7

Memory Organization

15-0182

2-14

2-8

Physical Memory Organization

15-0183

2-16

2-9

Memory Addressing

15-0184

2-17

3-1

Memory Reference Instructi on Word

15-0188

3-1

3-2

Augmented Instructi on Format

15-0204

3-2

3-3

Instruction Bit Configuration

3-13

3-4

Allowable Microinstruction Combinations

3-14

3-5

lOT Instructi on Format

15-0203

3-28

3-6

lOT Instruction Timing

15-0176

3-29

5-1

Multicycle Out Block Transfer I Flowchart

15-0004

5-5

5-2

Multicycle In Block Transfer I Flowchart

15-0004

5-6

5-3

Multicycle Transfer Implementation

15-0005

5-7

5-4

Single-Cycle Block Transfer Flowchart

15-0006

5-8

5-5

lOT Instruction Timing

15-0176

5-11

6-1

EAE Setup Mi croi nstructi ons

15-0189

6-2

EAE Shift Microinstructions

15-0190

6-2

6-3

EAE Normalize Microinstructions

15-0191

6-3

6-4

EAE Multiplication Microinstructions

15-0192

6-3

6-5

EAE Division Microinstructions

15-0193

6-3

6-6

EAE Simplified Block Diagram

15-0177

6-4

6-7

Power Fai I Up/Down Sequence

15-0185

6-43

6-8

Power Fai I Up/Down Sequence

15-0186

6-44

6-9

Power Fai I Up/Down Sequence

15-0187

6-45

6-10

API System Simplified Block Diagram

15-0054

6-47

Figure No.

viii

TABLES

Table No.

Title

Page

2-1

PDP-15 I/O Capabi lities

2-10

3-1

PDP-15 Central Processor Cycle Times for Basic and
Expanded Configurati ons

3-3

4-1

Types of Addressing

4-1

5-1

I/O Capabilities

5-1

5-2

Total Execution Times for lOPs

5-10

6-1

EAE Microinstructions

6-5

6-2

EAE Microinstructions

6-6

6-3

KM15 Instruction Set

6-36

6-4

KT 15 Instructi on Set

6-39

6-5

MP15 Instruction Set

6-41

6-6

lOT Instructions for Real-Time Clock

6-43

6-7

API lOT Instructi ons

6-49

6-8

SPI Control Word Format

6-50

6-9

ISA Control Word Format

6-51

6-10

Mai ntenance Instructi on Status Word

6-52

A-1

Memory Reference Instructi ons

A-1

A-2

Operate Instructi ons

A-2

A-3

Index Register Transfer Instructi ons

A-4

A-5

EAE Instructions

A-5

A-6

Standard API Channel/Priority Assignments

A-6

A-7

PDP-15 lOT Device Selection Codes

A-7

A-8

Input/Output Transfer Instructions

A-8

PREFACE
The PDP-15 Users Handbook is the principal guide to the PDP-15 hardware.
This manual is presented in two volumes: Volume 1 PROCESSOR and Volume 2 PERIPHERALS. The PDP-15 Users Handbook includes system features
and specifications, functional descriptions, machine language programming
considerations, and a detailed description of the instruction repertoire. The
chari' and table on pages iii and iv show the relationships of the other
PDP-15 system documentation and give abstracts of their contents.

Chapter 1
System Description

1.1 SYSTEM SOFTvVARE
1 • 1 • 1 Introduction
The PDP-15 System is divided into a number of configurations; each configuration having a powerful
software package available. These software packages are designed to service the needs of a particular
system configuration.
The PDP-15/10 configuration software is governed by the COMPACT Software System, a complete
package including Assembler, Editor, Octal Debugging Technique, and mathematical and utility
routines, all designed to function in 4K or 8K systems.

COMPACT Software System
Assembler
Editor
ODT (Octal Debugging Technique)
Math Package
Utility routines:
Hardware Read-in Mode (HRM) punch routine
Paper tape handling routines
Teletype I/O routines
Octal dump routine
Memory scan routine
For PDP-15/10 Systems equipped with DECtape, the FAST (Fast Acquistion of System Tape) System is
provided to retrieve frequently-used programs from DECtape.
Installations with a minimum of 8K words of core memory and a high-speed paper tape reader/punch
can use the Basic I/O Monitor to extend system capabilities. The PDP-15/20 Advanced Monitor

1-1

System operates from mass storage devices (DECtape or DECdisk) and is device independent;
consequently programs need not be limited to the use of certain specified I/O devices.
Simple I/O statements control data handling; selection of physical devices is determined at load time
on the actual machine, not when the program is written. Real-time I/O level subroutines can easily
be integrated into the system as new devices are added.

1 .1.2 PDP-15/20 Advanced Monitor System
The PDP-15/20 Advanced Monitor is used for batch processing. In the primary (keyboard) mode, the
user has interactive access to a large set of system programs to facilitate program development and
testing.
All Advanced Monitor functions, as well as the many avai lable system software routines, are specially
designed to make the system as accessible as possible to users who want II hands-on II interaction; at
the same time, routine elements of programming can be handled simply and easily.

PDP-15/20 Advanced Monitor System
Keyboard Monitor
Teletype handler
Command decoder
Input/Output Programming System (lOPS) data handling, device handling,
and interrupt routi nes
Real-time clock handler
Error detector program
Device assignment tables
Batch processor (paper tape or card control)
FORTRAN IV
SYS TEM LOADER
FOCAL
MACRO-15 Macro Assembler
DDT-15 Dynamic Debugging Technique
Text Editor
PIP-15 Peripheral Interchange Program
Linking Loader
Chain and Execute
Patch

1-2

SGEN System Generator
Octal Dump (DUMP)
Library Update (UPDATE)
DECtape Copy (DTCOP)

1.1.3 PDP-15/30 Background/Foreground Monitor
Under control of the PDP-15/30 Background/Foreground Monitor, real-time tasks are executed in the
computer foreground and have immediate ca lion the system's resources. Unused background time,
avai lable between service calls for the real-time tasks, is useful in program development, testing, or
other lower-priority computation.
PDP-15/30 software encompasses all Advanced Monitor functions and capabilities (see list above).
In addition, the PDP-15/30 Background/Foreground Monitor contains all the supervisory controls
necessary for concurrent processing of background and foreground tasks.
PDP-15 System users can draw on the resources of the program library and the applications knowledge
of DECUS, the Digital Equipment Computer Users Society, in addition to the Advanced Monitor programs and routines. DECUS members share in the exchange of programs and technical papers at regularly scheduled meetings throughout the year; the proceedings of all DECUS society meetings are pub-

I ished under DEC sponsorship.

PDP-15/30 Background/Foreground Monitor System
Background/Foreground Monitor controls the use of the PDP-15 by two co-resident programs.
System loader
Command decoder
lOPS data~handl ing, device-handl ing, and interrupt routines
Real-time clock handler
Error dete~tor program
Device assignment tables
In addition to the above programs, the programs of the PDP-15/20 Advanced Monitor System are included in the 15/30 System.

1-3

1 .1.4 PDP-1S/40 Disk-Oriented Background/Foreground System
PDP-1S/40 Disk-oriented Background/Foreground Systems are responsive to the high demands of industrial
and engineering environments, where the need for a background/foreground mode of operation is compounded by the necessity of large random-access files. PDP-1S/40 Systems with 24,S76 words of core
memory, high-speed paper tape facilities, and DECtape storage, also incorporate a DECdisk control
and two random-access disk files. The disks, whose storage capacity is S24,288 18-bit words, can be
expanded to 2,097, lS2 wo~ds, permit high-speed overlays, chaining, and system and user loading.
The disk-oriented background/foreground monitor system handles all the functions of the PDP-1S/30
Background/Foreground Monitor in a high-speed disk environment.

PDP-1S/40 Disk-Oriented Background/Foreground Monitor System
Disk-oriented Background/Foreground Monitor
Systems loader
Command decoder
lOPS data-handl ing, devi ce-handling, and interrupt routines
Real-time clock handler
Error detector program
Device assignment tables
The programs in the PDP-1S/20 Advanced Monitor are included in this section.

1.1.S PDP-1S/10 COMPACT Software System
The PDP-1S/10 COMPACT Software System is a concise programming system that includes a symbolic
assembler, a text editor for creating programs on-I ine, debugg ing routines, util ity routines, and
mathematical routines. The COMPACT Software System is designed to operate in the 4K or 8K papertape input/output environment of the basic PDP-1S/10. PDP-1S/10 Systems with more than 8K of
core are not supported by the COMPACT Software System. Installations with a minimum of 8K of core
and a high-speed paper tape reader/punch can use the Basic I/o Monitor Software to extend system
capabi Iities.
Utility routines in the COMPACT Software System include a Hardware Read-in Mode (HRM), punch
routines, paper tape hand Iing routines, Teletype I/o routines, an octal dump routine, and a memory
scan routine used for scanning areas of memory for a parti cular bit configuration. For systems with
DECtape, the FAST system can retrieve frequently used programs from DECtape.

1-4

COMPACT Assembler - The two-pass COMPACT Assembler has a useful set of selected pseudo-ops
for functions; such as table formations, symbol table and variable control, and text handling.

COMPACT Debugging Routines - Debugging routines are included in the COMPACT Software System.
ODT (Octal Debugging Technique) is an aid to the user conducting interactive, on-I ine debugging
sessions using octal numbers and Teletype commands.

COMPACT Editor - The COMPACT Editor takes advantage of the powerful character string, search,
and modification commands developed for the larger systems. It provides for the creation and/or
identifi cation of source programs, other than ASCII text material, using keyboard commands. The
Compact Editor also offers an efficient method for on-line processing of paper tapes.

1.1.6 PDP-15/10E Basic I/O Monitor
The Basic I/O Monitor, for 8K configurations, provides a link between the call for I/O, by either
user or system programs, and the actual I/O execution. All I/O calls to system devices are serviced
by DEC-suppl ied device handlers which reside in the Input/Output Programming System (lOPS). The
device handlers actually move data between the program and the I/O devices. Device handlers
initialize the devi ces and perform all other functions pecul iar to a given I/O device, such as servic ing
interrupts in a real-time environment. User-suppl ied de vi ce handlers can be incorporated into the
system to perform the functions described above for special I/O devices.

1 .1.7 PDP-15/20 Advanced Monitor System
The PDP-15/20 Advanced Monitor combines the functions of the Basic Monitor with the executive
control of bulk storage devices (to provide automatic operation), which includes batch processing,
keyboard interaction f and real-time queuing. The Advanced Monitor has a large set of commands
that direct the operation of the system. These commands perform three major functions:
a.

Provide information about the system such as commands avai lab Ie and their functions;
error diagnostics; the standard logical-physical I/O device associations; I/O level
programs available (device handlers); special memory registers and their functions.

Permit the standard physical-logical device associations to be modified, thereby
enabling the dynamic allocation of devices at load-time. This is a natural extension
of device independence provided by the Basic I/O Monitor.

Supervise the loading and execution of all system and user programs, their associated
I/O device handlers, and library subroutines, in addition to generating error messages
and recovery procedures.

1-5

C.oupled with keyboard control of system programs, the Advanced Monitor enables the user to deal
with his entire problem (editing, assembl ing, compi ling, loading, debugging and running) in a
straightforward manner. The Advanced Monitor consists of command decoder, lOPS routines, realtime c lock hand ler, error detector routine, and device assignment table (DA T).
The system loader always resides in upper memory and is responsible for loading the Monitor into lower
memory. Return calls from system or user programs cause restoration of control to the Monitor.
The Monitor command decoder detects requests for system programs and loads the system loader, which
brings in the requested program. In response to control cards or keyboard commands, it also manipulates the device assignment table to provide device independence. The Monitor Input/Output Programming System (lOPS) routines include data handling subroutines, device handlers, and interrupt
service routines for the priority interrupt system, as well as the Teletype keyboard and printer.

All

other lOPS device handlers are stored on the system device until required by object programs.
The Monitor contains a device assignment for each table entry; because the contents of the table can
be altered by commands to the Advanced Monitor, actual I/O devices can be changed without altering the program references to these devices. The following system software is suppl ied with all
PDP-15/20 Advanced Monitor System.

FORTRAN IV - The PDP-15 FORTRAN IV compiler is a two-pass system which accepts statements
written in the FORTRAN language and produces a relocatable object code capable of being loaded
by the Linking Loader program. The PDP-15 FORTRAN IV compiler is compatible with USA FORTRAN
IV, as defined in the USA Standard X3.9-1966, modified to allow the compiler to operate in 8,192
words of core storage. The FORTRAN IV compi ler generates programs whi ch operate with the program
interrupt enabled and works with assembly language programs that recognize and service real-time
devices. Subroutines written in either FORTRAN IV or the MACRO Assembler language can be loaded
with and called by FORTRAN IV main programs. Source language diagnostics are produced during
compi lation, and a symbol table is generated for use in on-I ine debugging.

FOCAL - An on-line, interactive (conversational) algebraic language designed to aid scientists,
engineers, and students in solving numerical problems. The language consists of short, easy-to-Iearn
English imperative statements. Mathematical expressions are usually typed in standard notation.
FOCAL puts the full calculating power and speed of the PDP-15 under easy conversational control.
For example, FOCAL can be used to simulate mathematical models, to plot curves, to handle sets of
simultaneous equations in n-dimensional arrays, and to solve many other kinds of problems. FOCAL
runs in the Advanced Software Environment.

1-6

MACRO-15 Assembler - MACRO-15 Assembler enables the programmer to use mnemoni c symbols to
represent operation codes, locations, and numeri c data. The programmer can direct the MACRO
Assemblerls processing through use of a full set of pseudo-operations. An output listing can be obtained to illustrate the programmer IS source coding, as well as the binary object code produced by
the MACRO Assembler. An optional third pass by the MACRO Assembler provides a cross reference
listing. PDP-15 users can also make use of highly sophisticated macro generating and call ing fac iI ities
within the context of a symbolic assembler. Some features of MACRO-15 are as follows:
a.

The abi Iity to define and call nested macros

Conditional assembly based on the computational results of symbols or expressions

Repeat functions

Boolean manipulation

Optional symbolic listing cross reference

Two forms of radix control (octal and decimal) and two text modes (7-bit ASCII
and 6-bit trimmed ASCII)

Global symbols for easy linking of separately assembled programs

Choice of output format: relocatable, absolute binary (checksummed), or full binary
(unchecksummed), capable of being loaded via the hardware READ-IN switch.

The abi I ity to call I/o system macros that expand into lOPS call ing sequences.

Dynami c Debugging Technique DDT -15 - A versati Ie tool for dynami c program checkout and modification. An operator can load a program and run all or selected portions of it in a real-time interrupt
environment under ini'eractive supervision of DDT -15. The Teletype keyboard controls DDT and program examination and modification. The operator can insert a breakpoint, specify the number of
programiteration5 before interrupting the program, and start the program at any point using a simple
set of commands. The operator can examine or alter any location symbolically and then rerun the
program using other commands.

Text Editor - Using the PDP-15 Advanced Software System, an operator can create or edit symbolic
text utilizing any input or output device. A IIcontext ll method is employed throughout to identify the
block of data which the user wishes to modify; that is, the block is specified by its ASCII text rather
than by a numbering scheme imposed externally upon the text. The Text Editor operates on these lines
of ASCII text. Commands are available which facilitate insertion, deletion, and modification of data
in the object file.

1-7

PIP-15 Periphera I Interchange Program - PIP-15 faci Iitates the manipulation and transfer
of data files from any input device to any output device. It can be used to update file descriptions,
verify, delete, segment, or combine files, perform code conversions, and copy tape.

Linking Loader - The Linking Loader loads any PDP-15 FORTRAN IV or MACRO-15 object
program , in either relocatable or absolute format. Its tasks are loading and relocation of programs,
loading of called subroutines, retrieval and loading and relocation of the necessary symbol tables.

CHAIN and EXECUTE - The programs CHAIN and EXECUTE facilitate a user-generated system
of core overlays in the PDP-15 Advanced Monitor environment. This system of overlays consists of a
resident main program, other indicated resident routines, a resident blank COMMON storage area,
and a set of subroutines whi ch overlay each other, as directed by the user. These subroutines are
grouped into units caUed LINKS. Many, or all, LINKS can overlay each other, and several LINKS
can overlay a larger LINK without overlaying each other. Cascading of suboverlays is not limited.
A LINK is loaded into core when a subroutine within the LINK is called and remains resident until
overlayed. A LINK's core image is not recorded or "swapped out" when it is overlayed. The same
image is brought into core each time a LINK is loaded.
Subroutines are called and return control to the calling routine in the normal fashion. There is no
imposed order in which routines must be called, nor is there restriction of the routines callable by
any routine.
The program CHAIN is used to build an XCT file, and the program EXECUTE supervises core residency
during the execution of a CHAIN-bui It Overlay System.

PATCH - The user can conveniently examine and modify system program parameters and
system programs stored on mass storage devices (DECtape or DECdisk) using the uti Iity program PATC H.

UPDATE - The contents of binary library files on mass storage devices can be listed and
updated, by insertion, deletion, or replacement operations using the library update uti Iity program
UPDATE. A binary library file is defined as any set of relocatable programs stored together as one
unit in a single file. The PDP-15/20 Advanced Monitor System library file (.LIBR BIN) is a typical
example.

1-8

DUMP - The user has the capability to output, on any listing device, specified core locations
stored on the SAVE or QAREA of a mass storage device using the DUMP utility program. The listing
output of any block of mass storage (DECtape or DECdisk) is obtained through the DUMP program.

SRCCOM - The source compare (SRCCOM) uti I ity program compares any two symbol i c programs and I ists the differences between them. SRCCOM is useful in proofing an edited program and in
keeping track of symbolic changes.

SGEN - The system generator (SGEN) utility program is used to build resident mass storage
systems tailored to the customer IS installation. Operating in conversational mode, SGEN uses the
query/response technique to build the operating system to the customer's needs.

1.1.8 PDP-15/30 Background/Foreground Monitor System
The PDP-15/30 Background/Foreground Monitor system is an extension of the Advanced Monitor system
which enables the concurrent, time-shared use of the PDP-15/30 through protected, foreground user
programs with a background of batch processing, through program development, or through low-priority
user programs. The system handl es a vari ety of tasks, frorn high-speed data gathering appl ications such
als those in physics to thousand-channel input/output applications such as warehouse inventory control.
With the Background/Foreground Monitor the user can:
a.

Effectively have two computers: one for on-line data acquisition and control, one
for off-line program development, and data reduction at the price of one system;

Achieve 100% use of his system, independent of data rates.

The foreground programs are assumed to be checked out and to operate from requests to the program interrupt or priority interrupt facilities. At LOAD TIME, foreground programs have first priority over
core memory and I/O devices, and at EXECUTION TIME they have priority (according to their assigned priority levels) over processing time and shared I/O devices.
The background program (or sequential series of programs) is essentially the same as the single-user
program under the Advanced Monitor system; that is, it can be an assembly, a compilation, a debugging
run, a production run, an editing task, or batch processing. The background program can use whatever
facilities (core, I/O, processing time, etc.) are available and not required by the foreground programs.
The Background/Foreground Monitor can be used to direct the time-shared use of the PDP-15/30 by
the two coresidential programs and to perform the following functions:
a.

Schedules processing time

Protects the foreground job's core

1-9

Protects the foreground job1s I/O devices

Allows the sharing of multi-unit device handlers, such as DECtape, by both
foregr~und and background jobs

Directs the shared use of the system real-time clock to time specified intervals

Directs communication between background and foreground jobs via core-to-core
transfers.

1 .1 .9 PDP-15/35 Real- Time System Executive
The PDP-15/35 Real-Time System Executive (RSX) is a disk-based system designed for multi task , mul tiprogramming environments, where real-time interrupts, time interval task activation, and a priority
job queue must all be coordinated under a priority structure.

1.1.10 PDP-15/40 Disk-Oriented Background/Foreground Monitor System
The PDP-15/40 system uses a disk-oriented version of the Background/Foreground Monitor; it contains
all of the features described above in the PDP-15/30 Background/Foreground Monitor section. The
disk system enables high-speed overlays, chaining, and system and user program loading to occur. The
number of records that can be opened on the disk is limited only by available word space. The
PDP-15/40 system contains 524,288 words of disk storage, expandable to 2,097,152 words.

1 .1 • 11 Additional Systems Software
8TRAN - The 8TRAN translator is used to translate programs written for PDP-8 in PAL III,
PAL-D, or MACRO-8 assembly language to MACRO-15 assembly language. The purpose of the translator is not to produce a program which runs on the PDP-15 by simulating the PDP-8, but rather to do
the straight-forward portion of the translation and clearly indicate to the programmer those parts of
the code which require review in the I ight of the PDP-15 I s greater word length and more powerfu I instruction set.

STATPAC - STATPAC is a comprehensive and open-ended package of modular statistical
programs designed to operate under the PDP-15 Advanced Monitor. The user with I imited computer
knowledge can use STATPAC to obtain statistically meaningful results from data. STATPAC includes
modules for CONTROL, INPUT, DESCRIPTIVE STATISTICS, STEPWISE LINEAR REGRESSION, and
MUL TIPLE LINEAR REGRESSION functions.

1-10

1.2 PDP-15 SYSTEM CONFIGURATIONS
PDP-15 Systems offer comprehensive solutions to real-time data problems by combining new design
concepts with a wide variety of traditional DEC features. Through DEC's experience in the mediumscale scientific computer field, the PDP-15 System simplifies the user's tasks in a demanding real-time
environment.
Because certain data-handl ing tasks require specific hardware and software configurations, DEC has
developed four standard PDP-15 Systems, ranging in power from the modestly priced basic PDP-15/10
to the PDP-15/40 Background/Foreground Disk Monitor System. At every level, the capabilities of
the hardware are under the control of a monitor designed specifically for them.
The softWare systems are designed around the hardware with the user environment in mind. The principal design objectives are to provide (a) a system that is convenient for the user to implement and that
affords the user access to the full power of the hardware, (b) a system that allows the user to easily
integrate his appl ications program and special peripheral device handlers, and (c) a system that can
expand naturally. PDP-15 Systems software enables the user to move from a very basic machine to a
sophisticated system without the cost and complication of reprogramming at each upward step.
The hardware systems were designed with complete autonomy between central processor, input/output
processor, and memory, so that processing and I/o operations can occur concurrently in overlapping
cycles; TTL integrated-circuit construction for high reliability; fast internal speeds, including an 800-ns
memory cycle time, to meet the demands of real-time data processing; core memory expansion to
131,072 words for future growth; and a sophisticated memory protect system for multi-user integrity.
Peripheral device handling and interfacing to other instruments are easily accompl ished, and system
growth potential is virtually unl imited with the modular structure of PDP-15 Systems.

1.2.1 PDP-15/10 Basic System
The PDP-15/10 is the first level PDP-15 System. The system's design provides I imited budget users access to the power, speed, and 18-bit word I ength of PDP-15 hardware, in the expectation that the
system can later be expanded to take full advantage of the advanced software capabilities inherent in
the system's design.
Hardware includes 4,096 l8-bit words of core memory and a Model 33 ASR Teletype console teleprinter.
The system has the rapid PDP-15 800-ns memory cycle time which provides 1.6-jJS add capability.
Facilities for later expansion are prewired into the system; additional memory and peripherals can be
plugged in as required.

1-11

Software is governed by the COMPACT Programming System, a complete package including Assembler,
Editor, Octal Debugging Technique, and mathematical and utility routines. All are designed to function in a 4096 word system. The software offers complete upward compatibi lity at the source level and
field-proven rei iabi Iity. Programs written for execution under COMPACT can also run, with little
modification, within all PDP-15 System levels up through PDP-15/30 and PDP-15/40 Background/
Foreground Systems.

1.2.2 PDP-15/20 Advanced Monitor System
PDP-15/20 is an 8, 192-word mass storage-oriented system designed for research and engineering environments where real-time data acquisition and control tasks are combined with program development
and testing.
Program development, debugging 1 and modification are all handled under monitor control, virtually
ending intermediate operations. Unique real-time input/output routines can also be integrated into
the system monitor to accelerate set-up and recovery.
Users are spared the task of writing system software to handle input/outputs to all standard system
peripherals, since appropriate routines are suppl ied with the monitor. The net result is that even inexperienced computer users can get their applications programs lion the air" in a minimum amount of
time.
PDP-15/20 hardware facilities include not only, 8, 192-words of core memory and high-speed papertape facilities but also, a DECtape control unit and two tape transports for convenient mass-memory
storage. The extra-heavy duty 35 KSR Teletype unit is included in the PDP-15/20 configuration to
guarantee a high degree of rei iabi Iity under the strain of continued heavy use. Also incl uded is the
extended arithmeti c element described in Chapter 6. This unit fac il itates high-speed multipl ication,
division, shifting, normal ization, and register manipulation.
The 15/20 Advanced Monitor System permits two types of user interaction. These are (1) batch
processing for routine production jobs, and (2) keyboard interaction which enables the user to
operate the system with simple commands typed at the keyboard.
Other PDP-15/20 Advanced Monitor features that make use of processor options are: a real-time
clock control and a priority interrupt control.

1-12

1 .2.3 PDP-15/30 Background/Foreground System
The PDP-15/30 System is designed to meet the demands of research, engineering, and industrial
environments, where one or more real-time tasks typically require continuous responsiveness from the
computer, but do not use 100% of its capacity.
The PDP-15/30 Background/Foreground System requires a minimum of 16,384 words of core memory
and all the devices standard for the PDP-15/20. In addition, PDP-15/30 Systems are equipped with
a memory protect system, a real-time clock, automatic priority interrupt, two DECtape transports,
and a second on-I ine Tel etype for background use.

1 .2.4 PDP-15/35 Rea 1- Time System Executive Disk-Oriented System
The PDP-15/35 System contains 16,384 words of core memory, high-speed paper-tap~ facilities, two
DECtape transports, the automatic priority interrupt option, real-time clock, and a DECdisk file with
262,144 words of storage.

1 .2.5 PDP-15/40 Disk-Oriented Background/Foreground System
PDP-15/40 Disk-Oriented Background/Foreground System fulfills the demands of industrial and engineering environments where the need for a Background/Foreground mode of operation is compounded
by the necess ity for Iarge random-access fi Ies •
The PDP-15/40 System with 24, 576 words of core memory I high-speed paper-tape facilities, and
DECtape storage, also incorporates a DECdisk control and two random-access DECdisk fi les. The two
disks, whose storage capacity of 524,288 18-bit words can be expanded to 2,097,152 words, permit
high-speed overlays chaining and system and user loading.
Other hardware feaf'ures of the PDP-15/40 include a memory protect system, background Teletype,
and a real-time clock.
The PDP-15/40 Disk-Oriented Background/Foreground Monitor System handles all the functions of
the 15/30 Background/Foreground Monitor in a high-speed disk environment.

1.3 SYSTEM ORGANIZATION
The basic PDP-15 hardware is shown in Figure 1-1. Three autonomous subsystems, central processor,
memory, and I/O processor, operating together under console control define the PDP-15 System.

1-13

P~~~~~:~~4r---------~·l
___C_O_N_S_O_LE__~
(CPU)~
"

I
I

I
I
I

~PERIPzHERAl
15-0174

Figure 1-1

PDP-15 System Organization

An extensive line of peripherals including mass storage displays, data communication, and data acquisition equipment is coupled to the PDP-15 I/o processor and serviced under the supervision of the
monitor systems.

1 .3. 1 Central Processor (CPU)
The central processor functions as the main componenl" of the computer by carrying on bidirectional
communication with both the memory and the I/o processor. Provided with the capabil ity to perform
all required arithmetic and logical operations, the central processor controls and executes stored programs. It accompl ishes this with an extensive complement of registers, control I ines and logic gates.

1 .3.2 Memory
The memory, second of three autonomous subsystems, is the primary storage area for computer insJructions and system data. The memory is organized into pages which are paired into memory banks. Each
page has 4096, 18-bit binary words of high-speed, random-access magnetic core storage. Each bank
is an asynchronous unit of 8192 words. The central processor has provisions to address up to 131,072
words of core memory. Any word in memory can be addressed by either the central processor or the
I/O processor.

1-14

1 .3.3

I/o Processor (IPU)

The third autonomous subsystem handles peripheral data transfer. A diverse line of system peripherals
available to the PDP-15 require this processor to interface three modes of input/output:
a.

Sing le-cycl e block data transfer; blocks of data transfer at rates up to one mill ion
words per second.

Multicycle block data transfer; blocks of data transfer at rates up to 250,000 words
per second for input and 188,000 words per second for output.

Program-controlled data transfers; single-word transfers to/from the accumulator in
the centra I processor.

The I/O processor provides timing, control, and data lines for information transfers between memory
or the central processor and the peripheral devices; it also includes provision for such options as the
automatic priority interrupt system and the real-time clock.

1 .3.4 Console
The PDP-15 control console provides facilities for operator initiation of programs, monitoring of important CPU and IPU registers during program execution, and manual examination and modification of
memory contents.

1 .3.5 System Peripherals
The PDP-15 System peripherals range from simple input/output Teletypes to sophisticated interactive
display processors. These peripherals communicate with the PDP-15 I/o processor via one 72-wire
bidirectional cable called the common I/o bus.
Figure 1-2 depicts a large system showing the CPU and IPU options and some of the PDP-15 Systems.

1-15

AUTOMATIC
PRIORITY
INTERRUPT

REAL TIME
CLOCK

POWER
FAIL

EXTENDED
ARITHMETIC
ELEMENT

INPUT/OUTPUT PROCESSOR
DATA CHANNELS AND
ADDRESSABLE I/O BUS

CENTRAL PROCESSOR

UP TO 8 DATA CHANNEL
CONTROL FOR SINGLEOR MULT 1- CYC LE BLOCK
TRANSFERS

Q.
I

RP15
DISK PACK
CONTROL

_ _ _ _ _ _ --1

. r0~

_ _ _ _ _ _ --1I

RF15
DECDISK
CONTROL

B=J

VP15CRT
DISPLAY
CONTROL

PAPER TAPE STATION
TU20 OR TU30

P...
L - - -

rU56

TU20 OR TU30
TC15
DECTAPE
CONTROL

o
1--_ _-' -

••••••
_

_ _ --.J

...--___-'

NEG.

TO OTHER DEVICES

CR03B
CARD READER \4----1
AND CONTROL

XY15
PLOTTER

a CONTROL
TO LIN E UN ITS

TO
OTHER
DEVICES
15-0017

Figure 1-2

System Organization

1-16

Chapter 2
Processor Organization

2.1

CENTRAL PROCESSOR DESCRIPTION

The central processor (CPU) is the main component for control and execution of stored programs. By
coordinating its operation with other subsystems, it provides supervisory control over the entire PDP-15
System.
The central processor contains arithmetic and control logic hardware for a wide range of operations.
These include: high-speed, fixed-point arithmetic with a hardware multiply and divide option; extensive test and branch operations implemented with special hardware registers; high-speed input/output
instructions; and other arithmetic and control operations.
The PDP-15 central processor contains several major registers for processor-memory communications,
a program counter, an instruction register, an accumulator, an index register, and a I imit register.
The CPU performs calculations and data processing in a parallel binary mode through step-by-step
execution of individual instructions. Both the instructions and the data on which the instructions
operate are stored in the core memory of the PDP-15. The arithmeti c and logical operations necessary
for the execution of all instructions are performed by the arithmetic unit operating in conjunction with
central processor registers. Figure 2-1 shows a simplified block diagram of the central processor.

2.1.1

Internal Registers

Arithmetic Unit
The PDP-15 arithmetic unit handles all Boolean functions and contains an l8-bit, 85-ns adder. The
arithmetic unit acts as the transfer path for inter-register transfers and shift operations.
Instruction Register (IR)
The instruction register accepts the six most-significant bits of each instruction word fetched from
memory. Of these bits, the four most-significant constitute the operation code, the fifth signals when
the instruction indicates indirect addressing, and the sixth indicates indexing.
2-1

FROM MEMORY

TO MEMORY

MEMORY
OUTPUT
REGISTER

MEMORY
INPUT
REGISTER

PROGRAM
COUNTER

DATA SWITCH
REGI STER

OPERAND
ADDRESS
REG I STER

INDEX
REG I STER

14----FROM CONSOLE

LIMIT
REGISTER

FROM

I/O BUS

INPUT GATING
ARITHMETIC UNIT

,----------1
I

STEP
COUNTER

I
I
I
I EXTENDED
I ARITHMETIC

I
I

______ -I

l_i~~~T

15-0002

Figure 2-1

Central Processor, Simpl ified Block Diagram

2-2

Accumulator (AC)
This 18-bit ~egister retains (accumulates) the result of arithmetic or logical operations for storage
between instructions.
For all program-controlled input-output transfers, information is transferred between core memory and
an external device through the AC. The AC can be cleared and complemented. Its contents can be
rotated right or left with the link (see below). The contents of the memory, buffered through the memory input register, can be added to the contents of the AC with the result left in the AC. The contents
of both registers can be combined by the logical operations AND and exclusive OR, the result remaining in the AC. The inclusive OR can be performed between the AC and the DATA switches on the
operator console (through the data switch register) and the result left in the AC.
Data Switch RegistE~r (DSW)
The data switch register receives and buffers an 18-bit word through the console.

Li nk (L)
This 1-bit register is used to extend the arithmetic capability of the accumulator. In lis complement
arithmeti c, the Link is an overflow indi cator; in 2 1s complement arithmeti c, it logically extends the
accumulator to 19 bits and functions as a carry register. The program can check carry into the Link
to simplify and speed up single- and multi-precision arithmetic routines. The Link can be cleared and
complemented and its state sensed independent of the accumulator. It is included with the accumulator in rotate operations and in logical shifts.
Program Counter (PC)
The program counter determines the program sequence (the order in whi ch instructions are performed).
This 18-bit register contains the address of the memory location from which the next instruction is to
be taken. The least-significant 15 bits are used for addressing 32,768 words of core memory. Two
remaining bits provide the capability to address memory systems greater than 32,768 words.
Operand Address Register (OA)
The operand address register is a temporary holding register (not available to the programmer) which
contains the effective address of the last (or current) memory reference operand.
Memory Input and Output Buffer Registers (MI and MO)
Information is read from a memory location into the memory input register and is interpreted as either
an instruction, address, or a data word. Information is recld from the central processor into memory
through the memory output register and is interpreted as either an address or a data word. The use
2-3

of two lS-bit registers for memory buffer functions allows the processor to overlap with memory cycle
time to decrease execution time and to allow autonomous operation of the CPU and memory.
Index Register (XR)
This lS-bit register is used to perform indexing operations with no increase in instruction execution
time. An indexed operation adds the contents of the index register to the address field of the instruction operand producing an effective address for the data fetch cycle. The index value is a signed
l7-bit integer 131,072).
Limit Register (LR)
The .Iimit register enables a program to detect loop completion. The base address of a data array is
loaded into the index register and the ending address is loaded into the limit register. Within an indexing loop, add to index and skip (AXS) instruction, adds a signed value C±2S6) to the index register
and compares the sum in the index to the contents of the limit register. If the contents of the index
register are equal to or greater than those of the Iimit register, the next instruction is skipped.

2.1.2 Control Console
The PDP-1S control console contains the keys, switches, and indicators required for operator initiation,
control, and monitoring of the system. Up to twenty-four lS-bit registers can be displayed to provide
the user with visual indication of most registers and buses.
Some of the features of the console are:
a.

A READ-IN switch to initiate the reading of binary paper tapes.

REGISTER indicators and REGISTER DISPLAY switches for continuous monitoring of
key points in the system such as the accumulator, index register, I imit register,
multipl ier-quotient register, program counter, memory address, interrupt status,
input/output bus, input output address, and I/O status.

DATA switches to establ ish an lS-bit data or instruction word to be read into memory
by the DEPOSIT switch, to be entered into the accumulator by a program instruction,
or to be executed as an instruction by pressing the EXECUTE key.

EXAMINE switch initiates the manual examination of the contents of any memory
location specified by the ADDRESS switches.

2.2 CENTRAL PROCESSOR EXPANSION OPTIONS
The following additional expansions extend the processing capabi Iities of PDP-1S Systems.

2-4

Extended Arithmetic Element (EAE)
The extended arithmetic element (standard on PDP-15/20/30/40 Systems) facilitates high-speed
arithmetic operations and register manipulations. Installation of the EAE adds an 1a-bit multipl ierquotient register (MQ) to the system as well as a 6-bit step counter register (SC). EAE instructions
can be microcoded so that several operations are performed by one instruction to simplify arithmetic
programming and reduce execution time. Worst case multiplication time is 7.42 fJS; division time is
7.68 fJS. The EAE is optionally available for the PDP-15/10.
Multiplier-Quotient Register (MQ)
The multiplier-quotient register and accumulator perform as a 36-bit register during shifting, normalizing, multiplication, and division operations. The contents of the multiplier-quotient register are
displayed by the REGISTER indicators on the operator's console when the REGISTER DISPLAY control
is in the MQ position.
During the multiply instruction, the MQ receives the 18 least-significant bits of the double word product formed in the AC and MQ. During the divide instruction, the MQ is the least-significant 18 bits
of the double word DIVIDEND formed by the AC and MQ.
Step Counter (SC)
The step counter is used to count the number of steps in an EAE instruction. The step counter is preloaded, except during normal ize operations, with the numbers of steps specified by an instruction and
is counted down as the instruction is executed. When the SC reaches zero, the EAE operation is
terminated.
Memory Protection
The memory protection feature, standard on PDP-15/30 and 15/40 Systems, establishes a background/
foreground environment for PDP-15 processing activity by specifying the boundary between protected
(lower) and unprotected (upper) regions of system core memory. Allocation of memory locations (in
increments of 256 words) to the protected region is dynamic and program-controlled under the
Background/Foreground Mon itor. Figure 2-2 shows a PDP-15 System with the memory protect option.
The protect feature increases all memory cycle times by 30 ns and write cycles in user mode by an
additional 175 ns. Memory cycle times are specified in Table 3-1.
The protection option also provides a user/monitor mode of operation. When;'n user mode, attempted
execution of any privileged instructions results in a trap to the monitor and a corresponding error
message. These illegal instructions include lOT instructions, halts, chained executes, any references
to the memory protect option itself, or protected memory. In monitor mode, all instructions are
executable.
2-5

MEMORY

MEMORY BUS

(OR MEMORY RELOCATE
AND
PROTECT OPTION)

CONSOLE

PERIPHERAL
A

I
I
I
I
I

;=tJ
Figure 2-2

PERIPz"ERAL
15-0175

PDP-15 System With Memory Protect Option

The option is activated (set to user mode) with an I/o instruction, and when active, it monitors all
CPU/memory instructions and addresses for illegal conditions and provides ~n interrupt if such conditi ons occur. Figure 2-3 gives more detail on the contents of the memory protect option.
Memory Relocate and Protect
Memory relocation is optional on all PDP-15 Systems. This feature is installed with the memory protect option on the memory bus (see Figure 2-2) and provides a relocation register and an upper boundary register to permit hardware relocation of user programs. It allows the relocated program to execute
only within its specified boundaries, thereby providing protection for other programs resident in memory. Figure 2-4 shows a block diagram of the memory relocate and protect option. Note that it functions essentially the same as the basic protect hardware and gives the added capability to relocate
programs in increments of 256 locations.

2.3 I/O PROCESSOR ORGANIZATION
The I/o processor is an autonomous subsystem of the PDP-15 which supervises and synchronizes all
data and control transfers between the devi ces and the PDP-15 centra I processor and memory.

2-6

MEMORY BUS

ADDRESS TO MEMORY

---.
INSTRUCTIONS FROM MEMORY

SUBTRACTOR
PROTECT
V I OLATION '
IF SIGN
NEGATIVE
AND IN
USER MODE

-2:

INTERRUPT AND SKIP IF
DECODED WHILE IN USER
MODE.

BOUNDARY
REGISTER

N
I

ILLEGAL INSTRUCTIONS

""'-J

ADDRESS FROM CPU

INTERRUPT
AND SKIP

I
DATA

LOAD
J

I/O BUS
IN STRUCTIONS TO CPU

MEMORY BUS
FROM CpU

1/0 BUS

lIO BU S

FROM
PERIPHERALS

FROM
IPU
15-0179

Figure 2-3

Memory Protect Block Diagram

MEMORY BUS

ADDRESS TO MEMORY

SUBTRACTOR

ADDER

-~
---=---.,........

PROTECT
VIOLATION .......
IF SIGN
POSITIVE
AND IN
USER MODE

INSTRUCTIONS FROM MEMORY

I LLEGAL INSTRUCT IONS

I NTERRUPTS IF DECODE D
WHILE IN USER MODE.

'"
I

ex>

INTERRUPT
AND SKIP

DATA

LOAD

I/O BUS
IN STRUCTIONS TO CPU

110 BUS

FROM
PERIPHERALS

FROM

MEMORY BUS
FROM CPU

IPU
15-0178

Figure 2-4

Memory Protect and Relocate Block Diagram

The I/o processor contains sufficient arithmetic and control logic hardware to supervise all I/o device
activity. The IPU is, however, a passive subsystem: it responds to requests for activity from the devices or the CPU rather than initiating activity.

2.3.1

Data Transfer Facilities

The PDP-15 I/o processor contains a number of different facilities for handling I/o activity. Each
facil ity has been designed to serve a basic requirement of the I/O devices. All I/o device transfers
can be placed into one of the following catagories. (See Figure 2-5.)

Command Transfers - Command transfers from the CPU to a device initiate or stop all device
activity, and establ ish device operating modes, transfer directions, and other control parameters.

Status Transfers - Status transfers from a device to the CPU are usually initiated by the CPU
for the purpose of monitoring the progress (or status) of a previously initiated activity.

MEMORY

I
t

MEMORY
PORT SWITCH

...
....

IPU

DATA

I
1

.....

COMMAND
STATUS
INTERRUPT

CPU

ACCUMULATORI

4!1o

DATA ~~
COMM ANDSTATUS-

INTERRUPT
---yTO I/O DE V ICE S

15-0180

Figure 2-5

Data Transfer Facilities

2-9

Data Transfers - Data transfers take place between a device and memory or a device and
the CPU under program control, and information may be transferred in either direction. Transfers of
data from a device to the CPU are initiated by the CPU. Transfers of blocks of information from a
device to memory or from memory to a device are initiated by the CPU. However, the transfer of
individual words in a block is usually signaled by the I/o devices.

Interrupt Requests - Interrupt requests, from the I/o device to the IPU, signal the IPU that
the device needs service. The interrupt system rei ieves the processor of the task of continuously
polling each device's status to determine its need for service.
Several capabilities in each transfer category are available from the PDP-15 I/O processor: 1) maximum flexibility is afforded the user who wishes to interface special equipment to the PDP-15 and to
the programmer who writes the device handler; 2) simple, inexpensive devices such as the Teletype
can be easily interfaced to the PDP-15, and require total CPU supervision; 3) complex devices (such
as the LP15 line printer) that need only one instruction to initiate a complete block transfer are built
to minimize the amount of CPU supervision required. The trade offs between these extremes are device cost, transfer rates, and percentage of CPU time.
Table 2-1 shows the I/o capabilities of the PDP-15 under each transfer category.

Table 2-1
PDP-15 I/o Capabilities

Category

Command

Capability

lOT command instructions
lOT AC transfer instructions

Status

10RS system read status instruction
lOT skip instructions
lOT AC transfer instructions

Data Transfers

lOT AC transfer instructions
Multicycle data channel transfers
Single-cycle data channel transfers

Special Transfers

Add to memory and increment memory

2-10

2.3.2

I/o Processor Activities

The following paragraphs describe the uses of each of the I/O processor activities.

Note that some

facilities have multiple uses.

lOT Commands - lOT command instructions from the CPU initiate, stop, or set the mode of
the I/o device.

lOT AC Transfers - lOT AC transfer instructions from the CPU transfer up to 18 bits of data
or command information from the CPU accumulator to the device's data or command registers, or command up to 18 bits of data or status information from the device's data or status registers to the CPU
accumulator.

10RS Instruction - The 10RS (input/output read status) instruction transfers up to 18 bits of
status information (typically one bit from each device) to the CPU accumulator.

lOT Skip Instructions - lOT skip-instructions initiated by the CPU interrogate a specific flag
or status bit in one of the 256 allowable devices and increments the CPU's PC (skips the next instruction) if the bit interrogated is asserted.

Multicycle Data Channel Transfer - Multicycle data channel transfers are IPU supervised
transfers of data between the I/o device and sequential memory locations (in either direction). The
word count and current address are kept in a pair of preassigned memory locations, and the counting
and overflow detection is accompl ished by the I/O processor.

Single-cycle Data Channel Transfers - Single-cycle (Direct Memory Access) transfers are
device supervised transfers of information (up to 18 bits/word) between the I/o device and memory.
The I/o device must contain word count and current address registers and provide overflow (job done)
detection.

Program Interrupt - Program interrupt (PI) requests from the I/O devices cause the running
program (at the completion of the current instruction) to transfer to a common subroutine that polls
the devices to determine which device needs service. The program then transfers to the device service
subroutine, and when finished handling the device, returns to the program which was interrupted by
the request.

2-11

Automatic Priority In'~errupt - Automatic priority interrupt (API) provide the same faci Iity
as the program interrupt except eight levels of priority' are provided (4 software levels and 4 hardware
levels). Instead of interrupting to a common devi ce poll ing subroutine, the interrupting device provides a unique address of the subroutine call to its device handler. This eliminates the need for a device poll ing seguence and improves the interrupt response latency. Interrupts from different priority
levels are fully nested and a debreak and restore instruction provides for orderly priority level dismissal.

Add- To-Memory - Multicycle data channel, add-to~memory facil ities function in the same
manner as other multicycle data channel transfers except a data word provided by the device is added
to memory and the results are left in memory and transferred back to the device. Typical uses for this
facility are high-speed averaging and in-core up-down counting.

Increment Memory - Data channel increment memory transfers cause the contents of a device-specified memory location to be incremented by one. A typical use for this facility is an incore histogram updated by nuclear pulse height analyzer information.

2.3.3

I/o Processor Organization

The I/o processor has fully parallel arithmetic capabilities which provide autonomous I/o device
supervision without interruption of central processor activities. In this manner, the I/O processor
can perform an add-to-memory calculation initiated by an I/O device at the same time the CPU performs multiply or index instructions. To implement this capabi I ity, the I/o processor contains independent registers, adder, and control circuitry. Figure 2-6 is a block diagram of the I/o processor.

I/o Buffer
The I/O buffer is an l8-bit register which buffers input data from the I/o device.
I/O Adder
The I/o adder is an l8-bit adder which contain the basic arithmetic capabilities of the IPU.

DSR
The data storage register receives all output calculations from the I/O adder. It holds addresses or
data destined for use by the memory I and it also holds data for presentation to the I/O bus lines.
The mixer logic, at the input to the I/O adder switches I appropriates data to the inputs of the adder,
in order to perform the proper arithmetic operation. An example of the operation is as follows: during
the data cycle of the add-to-memory data channel transfer, the contents of the memory location are

2-12

TO MEMORY

~-~--MEMORY PORT SWITCH

TO CPU
GRANT

REQUEST

-- - - I
I
I
I

I
I
I
I
L ___

110 ADDER

-- - - - - - - -

MIXER LOGIC

-- - - - - - - REQUEST

CONTROL
AND
PRIOR ITIES
LOG IC

GRANT
REQUEST

}TO CPU

GRANT

~~------------------~---------+------~TO

CPU

I/O BU S
TO
I/O DEVICES
15- 0181

Figure 2-6

I/O Processor Block Diagram

2-13

presented to one input of the adder and the contents of the I/o buffer {which contains the devicespecified word} are placed on the other input to the adder. The 18-bit sum is strobed into the DSR
which presents the data to the memory and to the I/o bus.
Control and priority logic in the IPU synchronizes the requests from CPU or devices for IPU activity,
grants action to the activities in appropriate order of priority, and controls the process of the transfer.
Chapter 6 contains a more detailed description of the I/O processor and its faci! ities.

2.4 CORE MEMORY
The magnetic core memory is the primary storage facility of the PDP-15. It provides random-access
data and instruction storage for both the central processor and the I/o processor. The basic PDP-15/10
memory contains 4096 18-bit word locations. The contents of each location are avai lable for processing
in 400 ns. A parity bit can be added as an option to each word for parity checking during transfer of
information into or out of core memory. If the parity option is incorporated into a PDP-15 System, all
memory banks must contain that option and memory cycle time becomes 1. 1 tJs. The basic subsystem
of memory is the memory bank; it is organized into pages, and each bank has two pages of 4096 words
each for a total of 8192 words of 3D 3-wire cores. Further, every bank contains a data buffer, an address buffer, and all the necessary read/write and control circuitry to make it an autonomous unit
operating on a request/grant basis with either the central processor or I/O processor. Figure 2-7 illustrates the organization of a memory bank.
8K BANK MEMORY MODULE

4K/18 BITS
STACK

ELECTRON ICS

ELECTRONICS

MEMORY BUS
15-0182

Figure 2-7

Memory Organization
2-14

2.4. 1 Memory Data Transfer
The PDP-15 memory interacts directly with the central processor and the I/O processor through the
memory bus. Data and instruction words of each bank are read from and written into individual memory locations through a buffered register, referred to as the memory buffer.
Words in a memory bank are selected according to the address in the memory address buffer. The
capaci ty of the memory address buffer enabl es 8192 words to be referenced in each bank.
The memory address buffer receives the memory address from the central processor or I/o processor.
The address provides the coordinates for locating a word in a memory bank.
Decoding of the memory address to select a particular word location containing 18 bits is performed by
the memory selection logic. Bit 5 of the memory cell address selects the page of the location, and
the remaining bits select the X and Y coordinates of the location.
Bits 1 to 4 of the memory bus select I ines are used to select which bank of memory the word is in. Up
to four banks can normally be added to the PDP-15, but a special provision to expand memory up to
16 banks can be accommodated by the 18-bit address register in the cPU.

2.4.2 Parity
The memory parity option provides cor,e planes that have 19 bits for each word and parity checking/
generating control logic. When the parity option is present, the accuracy of transfers to and from
memory is verifi ed through parity checking. A parity bit is added to each word stored in memory, so
that the total number of 1 bits in the word, including the parity bit, is odd. For example, if the
18-bit word to be stored in memory contains an even number of 1s, the parity bi t is automatically made
a 1, and is stored with the word. When the word is later read from memory, the computed parity bit
is calculated on the basis of the content of the 18-bit word. The calculated and actual parity bits are
then compared, if they do not agree, the memory parity error alarm is initiated, causing a program
interrupt or automatic priority interrupt request, or a half'.

All 18 bits and the accompanying parity-check bit {when present} are transferred in parallel {simultaneously} between the core array and the memory buffer. The memory buffer is connected to the
memory bus, and therefore, to the rest of the PDP-15 System. This is also an 18-bit parallel transfer.

2-15

2.4.3 Memory Modularity
The PDP-15/10 System contains one page of 4096 memory words; however, additional, modules (pages)
can be added to the system. The basic system can accommodate up to 32,768 core memory words
(eight 4K pages) in the basic 19-in. cabinet. Expansion beyond 32,768 words requires the addition of
another cabinet to the system configuration. Memory communicates with the central processor and
the I/o processor on the bidirectional memory bus (see Figure 2-8).

UP TO FOUR BLOCKS PER PDP- 15 SYSTE M
32K WORD BLOCK
8K BANK

8K BANK

8K BAN K

J"::]

I I

PAGE

MEMORY
BUS

PAGE

15-0183

Figure 2-8

Physical Memory Organization

2.4.4 Memory Addressing
The PDP-15 memory system is broken down into four basic memory entities. The maximum configuration system contains 131,072 words of 18 or 19 bits and is subdivided into four blocks of 32K words.
Each block contains up to four banks of 8K words, which contain two pages of 4K words. Figure 2-9
shows breakdown of locations, pages, banks, and blocks within the PDP-15 System.
Note that all valid addresses are positive addresses, i.e., negative addresses with bit 0 set
(400000-777777) are illegal and cause the machine to wait indefinitely for memory response. Such
addresses can be generated by the CPU or IPU under certain circumstances, but are trapped if the
memory protect option is present.

2.4.5 Memory Port Switch
The memory port switch allows both the central processor and I/O processor to share core memory. In
the event that both request a memory cycle simultaneously, the I/O processor is serviced first and the
central processor must wait. However, if only one processor is using memory, both can process at the
same time. For example, the central processor can be executing an EAE instruction, while the I/O
processor transfers data out of memory to a DECdisk.

2-16

LOCATION

PAGE

BANK

BLOCK

0
PAGE 0
7777
10000

BANK 0

r--"

PAGE 1
17777
20000
PAGE 2
27777
30000

BANK 1
PAGE 3

37777
40000

BLOCK
0
PAGE 4

47777
50000

BANK 2
PAGE 5

57777
60000
PAGE 6
67777
70000

BANK 3

MEMORY ADDRESSING

PAGE 7
77777
100000

----- BLOCK
1

PAGE = 4K LOCATIONS
BANK = 8K LOCATIONS
BLOCK = 32K LOCATIONS
4 BLOCKS = MAX. CONFIGURATION

177777
200000
BLOCK
2

277777
300000
~~

- .....

BLOCK
3

377777
15-0184

Figure 2-9

Memory Addressing

2.4.6 MX15-A Memory Bus Multiplexer
The MX15-A Memory Bus Multiplexer is a multiport memory option. It provides three ports for multiprocessor configurations, direct memory access (DMA) faci Ii ti es, and the K P15-A Dual Bus Processor
option. The MX15-A is a prerequisite for systems with greater than 32K of core memory. A PDP-15
System can accommodate up to four MX15-A Memory Bus Multiplexers. Each port has its own set of
address switches that can be preset in any 8K increment. This feature enables one processor to address
an 8K bank of core memory as its lowest bank (bank 0). A second processor can access the same bank
of core memory through the MX15-A as its highest bank. The MX 15-A introduces a delay for each
memory cycle. Refer to the MX15-A Maintenance Manual for specific delay times introduced by the
MX15-A.

2-17

Chapter 3
Instruction Formats

3.1 GENERAL
The PDP-15 instruction set is divided into "memory reference instructions ," which address core memory,
and "augmented inst'ructions," which do not address core memory. Memory reference instructions address, either directly or indirectly, core memory locations for the purpose of retrieving, entering, or
modifying the contents. The augmented instructions are used to execute a certain action or actions.
This type of instruction is subdivided into four groups: operate instructions (I ink and accumulator
operations including rotates, skips, clears, and complements); lOT instructions (input/output transfer
of data , command and status between the central processor, and peripheral devices); EAE (extended
arithmetic element, optional hardware mul tiply, divide, shift, and normal ize); and index instructions
(accumulator, limit regisJer, and index register transfers, clears, additions, and skips).

3.2 MfMORY REFERENCE INSTRUCTION FORMAT
The memory reference insh:uction word consists of an operation code, an indirect address bit, an index
bit, and an operand address (see Figure 3-1). The operation code, bits 0 through 3, specifies one of
the 13 PDP-15 memory reference instructions. When the PDP-15 is in "page mode ," the indirect bit
indicates whether the 12-bit (bits 6-17) operand address is to be directly or indirectly (bit 4=1) addressed and the index bit determines whether or not the index register should be added to the operand
address. In "bank mode ," the indirect bit indicates whether the 13-bit (bits 5-17) operand address is

OPERATION CODE
00a- 6O a

INDEX BIT
(I=INDEXED)

3 14
5
6
1
1

'---y--J

y
OPE RAN D ADD RES S

IND I RECT
ADDRESS
(1 INDIRECT)
*USED AS A THIRTEENTH ADDRESS BIT IN BANK MODE

15-0166

Figure 3-1

Memory Reference Instruction Word

3-1

to be used as the direct address or the indirect address (bit 4=1). The operand address is used in
generating the effective address or the address in memory which will be referenced. Chapter 4 is a
detailed description of addressing.

3.3 AUGMENTED INSTRUCTION FORMAT
The augmented instruction word (see Figure 3-2) consists of an operation code and an instruction code.
The operation code designates whether the instruction is an extended arithmetic element instruction,
648 (bits 0-3), an Input/Output transfer instruction, 70 (bits 0-5), an Index instruction, 728 (bits 0-5)
8
or an operate instruction 748 (bits 0-3). The instruction code designates which action is to be taken
by the augmented instruction. An important and useful feature of the PDP-15 augmented instruction is
its microprogramming capability. Multiple instruction codes having the same operation code can be
combined to form one instruction word. Execution of all microprogrammed functions occurs during the
time allocated to the type of instruction (operate instructions require one machine cycle, lOTs require
two, three, or four cycles, EAE requires one or three, plus a variable time interval to complete their
function, and index instructions require two cycles). Thus, microprogramming decreases program running time, lessens the number of instruction words required, and simplifies programming efforts.
OPE RAT ION CODE
64 s =EAE
70S = rOT
728 = INDEX

74S = OPERATE

r~----~A~--------------~\

13 114115

'---____________-----y~----------------------------J
INSTRUCTION CODE
*THESE BITS USED AS PART OF THE INSTRUCTION CODE IN EAE AND
OPERATE INSTRUCTIONS
15-0204

Figure 3-2

Augmented Instruction Format

3.4 TIMING
The amount of time required to perform each instruction is expressed in the number of machine cycles.
The length of each mach ine cycle for various configurations is given in Table 3-1 •
Instructions which indirectly address memory require one extra machine cycle in order to fetch and
compute the indirect address. Only one level of indirect addressing is possible on the PDP-15.
Instructions which use the auto increment locations indirectly require two extra machine cycles; one
for the increment of the location, and one for the indirect address.

3-2

Table 3-1
PDP-15 Central Processor Cycle Times, Basic and Expanded Configurations*

Not In User Mode
Configuration

Read

In User Mode

Write

Read

Write

Max

Typical

Max

Typical

Max

Typical

Max

Typical

Basic

800

KM15 Memory Protect

830

800

830

800

830

800

975

920

KM15 Memory Protect and
KTl5 Memory Protect/Relocate

965

880

965

880

1165

1080

1165

1080

MP15 Memory Parity

1100

1050

1100

1050

1100

1050

1100

1050

MP15 Memory Parity and
KM15 Memory Protect

1130

1255

MP15 Memory Parity,
KM 15 Memory Protect and
KTl5 Memory Protect/Relocate

1155

1355

*AII times indicated in nanoseconds. Refer to MX15-A Maintenance Manual or KP15-A Supplement
for cycle times for MX15-A and KP15-A options.

3.5

MEMORY REFERENCE INSTRUCTIONS

In the memory reference instruction descriptions, and in succeeding paragraphs that describe other
types of instructions I the following symbols are used:
Symbol

Definition

The effective address of the memory location

Logic inclusive-OR'
Indicates contents transferred from reg ister or
location preceding arrow to register or location
following arrow.
Logic AND
Logic exclusive-OR
Overscore indicates complemented contents
of register or location

Addition

3-3

LOAD THE ACCUMULATOR

Mnemonic Name:

LAC

Octal Code:

Time:

2 cycl es

Operation:

The contents of the effectively addressed memory location, Y,
are read into the AC. The contents of Yare unchanged, the
previous contents of the AC are lost.

Symbolic:

Y -AC

DEPOSIT THE ACCUMULATOR

Mnemonic Name:

DAC

Octal Code:

Time:

2 cycles

Operation:

The contents of the AC are deposited in the effectively addressed memory location Y. The contents of the AC are
unchanged; the previous contents of Yare lost.

Symbolic:

AC -Y

3-4

DEPOSIT ZERO IN MEMORY

Mnemonic Name:

DZM

Octal Code:

Time:

2 cycles

Operation:

An all-zeros data word is deposited in the effectively addressed memory location Y. The previous contents of Yare
lost; the contents of the AC are unchanged.

Symbolic:

o ~Y

ADD (2 1s Complement)

I :<
Mnemonic Name:

TAD

Octal Code:

Time:

2 cycles

Operation:

The contents of the effectively addressed memory location Y I
are added to the contents of the AC f following the rules of
2 1s complement arithmetic. The result is left in the AC. An
arithmetic carry from ACO complements the link. The contents of Yare unchanged; the previous contents of the AC are
lost.

Symbolic:

Y + (L ,AC) ~ (L ,AC)

3-5

ADD (lIs Complement)

Mnemonic Name:

ADD

Octal Code:

Time:

2.3 cycles

Operation:

The contents of the effectively addressed location I Y I are added
to the contents of the AC I following the rules of lis complement arithmetic. The result is left in the AC. An arithmetic
overflow sets the I ink to the binary 1 state. The contents of the
AC is lost. The previous content of the I ink is lost. Overflow
occurs if the magnitude (absolute) of the algebraic sum of the
operands exceeds 2 17 _1; if the operands were of like sign and
the result is signed differently I overflow has occurred to set the
I ink. Overflow cannot occur if the operands are of different
sign.
NOTE
The I ink should be cleared prior to the ADD instruction I
if an arithmetic overflow check is desired.

Symbolic:

Y + AC ... AC
L V Overflow -+ L

3-6

INCREMENT AND SKIP IF ZERO

Mnemonic Name:

ISZ

Octal Code:

Time:

3 cycles

Operation:

The contents of the effectively addressed memory location, Y,
are incremented by one (in 2 15 complement arithmetic) and
tested. If Y now contains an all-zero word, the PC is incremented by one to skip the next instrucHon. If the contents of
Y, after being incremented, are other than zero, the next instruction is executed. The previous contents of Yare lost; the
contents of the AC are unchanged.

Symbolic:

If Y + 1 = 0, PC + 1 .... PC

Y+l .... Y

SK IP IF AC DIFFERS

Mnemonic Name:

SAD

Octal Code:

Time:

2 cycles

Operation:

The contents of the effectively addressed memory location, Y,
are compared with the contents of the AC. If they differ, the
PC is incremented by one to skip the next instruction. If they
are the same binary quantity, the next instruction is executed.
The contents of Y and the contents of the AC are unchanged.

Symbolic:

If Y t- AC, PC + 1 .... PC

3-7

BOOLEAN AND

Mnemonic Name:

AND

Octal Code:

Time:

2 cycles

Operation:

The contents of the effectively addressed memory location, Y,
are logically ANDed with the contents of the AC on a bit-bybit basis. The result is left in the AC. If corresponding, Y
and AC bits are in the 1 state, the AC bit remains a 1; otherwise, the AC bit is cleared to the 0 state. The contents of Y
are unchanged; the previous contents of the AC are lost.

Symbolic:

Y /\ AC -AC

AC
AND

3-8

EXECUTE THE INSTRUCTION AT Y

Mnemonic Name:

XCT

Octal Code:

Time:

1 cycle plus time of instruction at Y

Operation:

The computer executes the instruction located at the effectively
addressed memory location, Y. The contents of the PC are unchanged unless Y contains a JMS, CAL, JMP, or skip instruction,
each of which changes the contents of the PC to alter the program sequence. XCT could be thought of as a single- instruction
subroutine causing a quasi-jump to Y, execution of the instruction specified there, and return to the program sequence (i.e.,
execution of the instruction following XCT) if the instruction
has not changed the PC.
With the Memory Protect option installed, the XCT of an XCT
instruction is not allowed when in USER mode.

Symbolic:

3-9

BOOLEAN EXCLUSIVE OR

Mnemon i c Name:

XOR

Octal Code:

Time:

2 cycles

Operation:

The contents of the effectively addressed memory location, Y,
are exclusively-ORed with the contents of the AC, on a bitby-bit basis. The result is left in the AC. If corresponding Y
and AC bits are in the same binary state (i.e., 1 or 0), the
AC bit is cleared to the 0 state. If the corresponding bits differ
in state, the AC bit is set to the 1 state. The contents of Y
are unchanged. The previous contents of the AC are lost.
NOTE
The XOR instruction causes the operand to complement
its original content only in those bits that have lis in
the accumulator mask.

Symbolic:

Y ¥ AC -AC

AC
XOR

3-10

UNCONDITIONAL JUMP

Mnemonic Name:

JMP

Octal Code:

Time:

1 cycle

Operation:

A new address is computed from the operand address of the jump
instruction and transferred to the PC. The next instruction
fetched will be from the memory location specified by the new
address. The contents of the AC are unchanged.

Symbolic:

JUMP TO SUBROUTIN E

Mnemonic Name:

JMS

Octal Code:

Time:

2 cycles

Operation:

The contents of the PC and the I ink, and the status {on or off}
of bank mode and user mode are deposited in the effectively addressed memory location, Y. The next instruction is read from
the contents of memory location Y + 1, breaking the previous
program sequence and starting a new sequence from Y + 1. The
contents of the PC are changed, and the contents of the AC are
unchanged.
'
When not in the user mode, or when the memory protect option is
not installed, a free instruction follows the JMS. Therefore, a
PI or API break cannot occur after the execution of the JMS instruction, but may occur after the execution of the next instruction.

Symbolic:

L -Yo
BM .... Y1
UM -Y2
PC .... Y3-17
YS-17 + 1 .... PC

3-11

CALL (JUMP TO) SUBROUTINE

Mnemonic Name:

CAL

Octal Code:

Time:

2 cycles

Operation:

The CAL instruction is the equivalent of a JMS 20 instruction.
The contents of the PC and the I ink, and the status (on or off)
of bank mode and user mode are deposited in memory location
20. The next instruction is read from memory location 21,
breaking the previous program sequence and starting a new
sequence from 21. The contents of the AC are unchanged. If
the API option is present and enabled, priority level 4 will be
activated after the execution of a CAL instruction if no higher
priority I evel is set.
When not in user mode, or when the memory protect option is not
installed, a free instruction follows the CAL. Therefore, a PI or
API break cannot occur after the execution of the JMS instructi on,
but may occur after the execution of the next instruction.

Symbolic:

L -+200
BM -20

1
UM -+20
2
PC .... 20 _

3 17

"21" -PC

3.6 AUGMENTED INSTRUCTIONS
3.6.1 Operate Instructions
Operate instructions (operation code of 74 ) are used to sense and/or alter the contents of the AC and

8
I ink. Typical functions are: conditional or unconditional skips, complementing, setting, clearing,
or rotating the contents of the two registers jointly or independently and incrementing the AC. A

Halt (HL T) instruction is included. Operates are performed in one machine cycle, the actions being
specified by the microprogramming of the instruction code. Each bit of the 14-bit instruction code
can effect a unique response; hence, they are "microinstructions" to the computer. The important
feature of the operate class is its microprogramming capabi Iity, where two or three microinstructions

3-12

can be combined to form one instruction word and, therefore, be executed in one cycl~. Those
microinstructions that logically conflict and occur at the same time should not be microprogrammed.
Figure 3-3 illustrates the bit configuration of the instrudion code. Figure 3-4 shows the allowable
combinations of microinstructions.
When non inverted skip actions are microprogrammed (bit 8 is 0), the conditions to be met are
inclusively ORed.

For example, if SZA (740200) and SNL (740400) are combined (740600), the skip

takes place if either or both conditions are present (contents of the AC are 0 or the content of the
link is not 0).
When inverted skip actions are microprogrammed (bit 8 is 1), the skip occurs only if the AND of the
conditions is met. For example, when SNA (741200) and SZL (741400) are specified in a microprogrammed instruction (741600), the skip occurs only if both conditions are present (the contents of the
AC are other than 0 and the content of the I ink is 0).
Programming Note
The PDP-15 Symbolic Assembler accepts either HLT or XX
(see Figure 3-4) as a val id mnemoni c for the operate class
instruction to stop program execution •. The latter faci! itates
visual scanning of a program listing to determine the occurrence of program halts.

Bit 7=0
CLA CLL
5

Additional
Rotate

O=OR of
l=AND of

RAR RAL
SNL SZA SMA
OAS CML CMA
HLT
SZL SNA SPA
RTR I RTL
Bit 7=1
15
16
17
9
10
12 13 p4
11

NOTE: Bits 7, 13, and 14 set: SWHA
Bits 13 and 14 set: lAC
Figure 3-3

Instruction Bii' Configuration

3-13

Order of
Events

Column 1

Levell

SNL SZA SMA

Level 2

SZL SNA SPA

Level 3

SKP

Column 2

Column 3
OAS CMA

Column 4

I CML

I lAC

RAR or RAL

CLA CLL

HLT

RTR or RTL or SWHA

Combine instructions from left to right.

Any instructions in a box can be combined, except the rotate instructions.

Instructions on different levels cannot be combined if they are in the same column.
Instructions on any level can be combined if they are in different columns. (e.g.,
SZAISMAICLAIOASIHLT! is legal- SZAISPA is not legal.)

CML and lAC cannot be combined. Either one can be combined with OAS and/or
CMA (e.g., OASICMAICML or OASICMA!IAC).

Instructions occur in order from column 1 to column 4.
NOTE
Levell skips (SNL, SZA, SMA) will occur if anyone of the
combined tests is satisfied (an OR condition).
Level 2 skips (SZL, SNA, SPA) will occur only if all the combined tests occur (an AND condtion).
Combined rotates become a SWHA or an lAC, depending on
bit 7.
Figure 3-4

Allowable Microinstruction Combinations

NO OPERATION

740000

I
Mnemon i c Name:

NOP

Octal Code:

740000

Time:

1 cycle

Operation:

The program delays for one cycle before the next instruction is
fetched.

Symbolic:

Not applicable.

3-14

COMPLEMENT ACCUMULATOR

Mnemonic Name:

CMA

Octal Code:

740001

Time:

1 cycl e

Operation:

Each bit of the AC is set or cleared to the inverse of its current state. The previous contents of the AC are lost.

Symbolic:

AC "*AC

COMPLEMENT LINK

Mnemonic Name:

CML

Octal Code:

740002

Time:

1 cycle

Operation:

The link is setor cleared to the inverse of its current state.
It previous content is lost.

Symbolic:

r .. L

3-15

INCLUSIVE OR ACCUMULATOR SWITC HES

Mnemonic Name:

OAS

Octal Code:

740004

Time:

1 cycle

Operation:

The word set up by manual positioning of the DATA switches is
inclusively ORed with the contents of the AC on a bit-by-bit
basis. The resul t is left in ,the AC. If corresponding, AC and
DATA switch bits are in the binary 0 state, the AC bit remains O.
If either or both of the corresponding bits are in the binary 1
state, the AC bit is set to 1. The previous contents of the AC
are lost. The switch settings are not affected.

Symbolic:

AC V DATA switch -+ AC

INCREMENT THE ACCUMULATOR

Mnemonic Name:

lAC

Octal Code:

740030

Time:

1 cycl e

Operation:

The contents of the accumulator are incremented by one and
the resul'~s placed in the accumulator. The previous contents
of the accumulator are lost. When overflow occurs bit zero
complements the I ink.

Symbolic:

3-16

CLEAR THE LINK

Mnemonic Name:

Cll

Octal Code:

744000

Time:

1 cycle

Operation:

The content of the link is cleared to the binary 0 state.

Sym bo I ic :

0 -+ l

CLEAR THE ACCUMULATOR

750000

I >: : :< : :0; : :<: :< : :0; I

CLA

Mnemonic Name:

ClA

Octal Code:

750000

Time:

1 cycle

Operation:

Each bit of the AC is cleared to the binary 0 state. The previous contents are lost.

Symbolic:

0 -AC

3-17

HAL T PROGRAM

740040

I :7: : : 4: : : 0: : : 0: : : 4: : : 0: IHlT
Mnemonic Name:

HLT

Octal Code:

740040

Time:

1 cycle

Operation:

Program execution stops at completion of the current machine ~
cycle. The run indicator is turned off.

Symbolic:

o - RUN flip-flop

SWAP HALVES OF THE ACCUMULATOR

742030

I :< : >: : >: : :0; : >: : :0; I

SWHA

Mnemonic Name:

SWHA

Octal Code:

742030

Time:

1 cycle

Operation:

This instruction places the contents of AC bits O-S into AC
bits 9-17 and at the same time places AC bits 9-17 into AC
bits O-S. The previous contents of the AC are lost.

Symbolic:

AC _ .... AC _
9 17
OS
-ACoAC _
S
9 17

3-1S

SKIP ON MINUS ACCUMULATOR

740100 I

Mnemonic Name:

SMA

Octal Code:

740100

Time:

1 cycle

Operation:

Test the contents of the sign bit, ACO, of the data word in the
AC. If the bit is in the binary 1 state, the contents of the PC
are incremented by one to skip the next instruction. If ACO is
found to be in the 0 state, the next instruction is executed.
The contents of the AC are unchanged.

Symbolic:

If AC

= 1, PC + 1 ->- PC

SKIP ON ZERO ACCUMULATOR

Mnemonic Name:

SZA

Octal Code:

740200

Time:

1 cycle

Operation:

Test the contents of the word in the AC. If all bits are binary
Os, the quantity is taken to be zero (2 1s complement notation),
and the contents of the PC are incremented by one to skip the
next instruction. If any bit is in the binary 1 state, the next
instruction is executed. The contents of the AC are' unchanged.

Symbolic:

If A C=O, PC + 1 ->- PC

3-19

SKIP ON NON-ZERO LINK

Mnemonic Name:

SNL

Octal Code:

740400

Time:

1 cycle

Operation:

Test the content of the link. If the link is in the binary 1 state,
the contents of the PC are incremented by one to skip the next
instruction. If the link has a binary 0, the next instruction is
executed. The content of the I ink is unchanged.

Symbolic:

If L = 1, PC + 1 .... PC

UNCONDITIONAL SKIP

Mnemonic Name:

SKP

Octal Code:

741000

Time:

1 cycle

Operation:

The contents of the PC are incremented by one to cause an
unconditional skip of the next instruction.

Symbolic:

PC + 1 .... PC

3-20

SKIP ON POSITIVE ACCUMULATOR

Mnemonic Name:

SPA

Octal Code:

741100

Time:

1 cycle

Operation:

Test the contents of the sign bit, ACO, of the data word in the
AC. If the bit is in the binary 0 state, the quantity in the AC
is taken to be positive. Therefore, the contents of the PC are
incremented by one to skip the next instruction. If the bit is
found to be in the binary 1 state, the next instruction is executed. The contents of the AC are unchanged.

Symbolic:

If AC O = 0, PC + 1 ->- PC

SKIP ON NON-ZERO ACCUMULATOR

741200

I >: : :<: :<: >: : ;0: : >: I
Mnemon i c Name:

SNA

Octal Code:

741200

Time:

1 cycle

Operation:

Test the contents of the data word in the AC. If any bit is in
the binary 1 state, the quantity is taken to be unequal to zero
(2 1s complement notation only), and the contents of the PC are
incremented by one to skip the next instruction. If all bits are
found to be in the 0 state, the quantity is considered to be
zero and the next instruction is executed. The contents of the
AC are unchanged.

Symbolic:

If AC

t- 0, PC + 1

->-

3-21

SNA

SKIP ON ZERO LINK

741400

I
Mnemonic Name:

SZL

Octal Code:

741400

Time:

1 cycle

Operation:

Test the contents of the I ink ° If the I ink is in the binary 0
state, the contents of the PC are incremented by one to ski p
the next instruction ° If the I ink has a binary 1, the next instruction is executed ° The contents of the I ink is unchanged.

Symbolic:

If L = 0, PC + 1 - PC

ROTATE AC AND LINK LEFT

740010

I
Mnemonic Name:

RAL

Octal Code:

740010

Time:

1 cycle

Operation:

The contents of the AC and the I ink are rotated one bit position to the left with ACO entering the I ink and the I ink entering
AC 17
0

Symbolic:

AC.1 -AC.1- 1; ·-1
17
1- ,

-L
O
L -AC
17
AC

3-22

ROTATE AC AND LINK RIGHT

740020

I >: : :<: >: : ;0: : >: : ;0:
Mnemonic Name:

RAR

Octal Code:

740020

Time:

1 cycle

Operation:

The contents of the AC and the link are rotated one bit position
to the right with AC 17 entering the I ink and the I ink entering
ACO·

Symbolic:

AC i .... AC i +1; i=O,16
AC
.... L
17
L .... AC

ROTATE AC AND LINK TWO LEFT

Mnemonic Name:

RTL

Octal Code:

742010

Time:

1 cycle

Operation:

The contents of the AC and the I ink are rotated two bit positions to the left with ACO entering AC17, AC1 entering the
I ink, and the I ink entering AC 16.

Symbolic:

AC i .... AC i _ 2 ; 1=2,17

L .... AC
AC
AC

16
-AC

.... L

3-23

ROTATE AC AND LINK TWO RIGHT

742020

I
Mnemonic Name:

RTR

Octal Code:

742020

Time:

1 cycle

Operation:

The contents of the AC and the I ink are rotated two bit positions to the right with the'link entering AC1, AC17 entering
ACO, and AC16 entering the link.

Symbolic:

AC.1 -AC.1+2 i ·-0
15
1- ,

L -AC
AC
AC

17
16

1
-AC

-L

2'S COMPLEMENT ACCUMULATOR

740031

I >: : :< : >: : :< : :< : : : I

TeA

Mnemonic Name:

TCA

Octal Code:

740031

Time:

1 cycle

Operation:

A microcoded instruction combines the complement of the AC
and increments the AC, thereby, performing a 2's Complement
Operation on the contents of the AC and placing the result in
the AC. The previous contents of the AC are lost.

Symbolic:

AC + 1 -AC

3-24

SET THE LINK

744002

I >: : :<: :<: :< : :0; : >: I

STL

Mnemonic Name:

STL

Octal Code:

744002

Time:

1 cycle

Operation:

A microcoded instruction equivalent to CLL-tCML. The link
is first cleared to contain a binary 0; it is then complemented
to contain a binary 1.

Symbolic:

1 -+ L

CLEAR LINK, THEN ROTATE AC AND L LEFT

Mnemonic Name:

RCL

Octal Code:

744010

Time:

1 cycle

Operation:

A microcoded instruction equivalent to CLL+RAL. The link is
first cleared to the binary 0 state: then the contents of the AC
and the I ink are rotated one bit position to the left.

Symbolic:

AC.1 -AC.1- 1;1·-1 , 17
AC

o -L

o -AC 17

3-25

CLEAR LINK, THEN ROTATE AC AND L RIGHT

Mnemonic Name:

RCR

Octal Code:

744020

Time:

1 cycl e

Operation:

A microcoded instruction equivalent to CLL+RAR. The link is
first cleared to the binary 0 state; then the contents of the AC
and the I ink are rotated one bit position to the right.

Symbolic:

AC.I -AC.1+1; '=0
16
I
,
AC

-L

o -AC o

CLEAR AND COMPLEMENT ACCUMULATOR

750001

I >: : :< : ;0: : :< : ;0: : : : I
Mnemonic Name:

CLC

Octal Code:

750001

Time:

1 cycle

Operation:

A microcoded instruction equivalent to CLA + CMA. Each bit
of the AC is cleared to the binary 0 state. Then each bit is
set to the binary 1 state. The previous contents of the AC are
lost.

Symbolic:

777777 . . . AC

3-26

CLC

LOAD AC FROM ACCUMULATOR SWITCHES

Mnemonic Name:

LAS

Octal Code:

750004

Time:

1 cycle

Operation:

A microcoded instruction equivalent to CLA + OAS. Each bit
of the AC is cleared to the binary 0 state. Then the word set
up by manual positioning of the DATA switches is entered in the
AC. The previous contents of the AC are lost. The switch settings are not affected.

Symbolic:

DSW -+AC

GET THE LINK

Mnemonic Name:

GLK

Octal Code:

750010

Time:

1 cycle

Operation:

A microcoded instruction equivalent to CLA + RAL. Each bit
of the AC is cleared to the binary 0 state. Then the contents
of the AC and the link are rotated one bit position left with
the link contents entering AC17. The previous contents of the
AC are lost.

Symbolic:

L -AC

o -AC O_ 16
o -L

3-27

LOAD AC WITH "n"

Mnemonic Name:

LAW

Octal Code:

760000 + n {n = 13-bit number}

Time:

1 cycle

Operation:

A single-cycle instruction that loads itself into the AC for the
purpose of generating a negative number, n, of the range of
o~ n :$177778. Following the fetch, the computer enters the
contents of the MI (the LAW instruction word) in the AC. The
previous conten.ts of the AC are lost. The first five AC bits
will always be loaded with ls.

Symbolic:

MI -.AC

3.7 INPUT/OUTPUT TRANSFER INSTRUCTIONS
Input/Output transfer (lOT) instructions initiate transmission of signals via the I/o bus to control
peripheral devices, sense their status, and effect information transfers between them and the central
processor. PDP-15 lOT instructions contain the following information {see Figure 3-5}:
a.
b.

An operation code of 70 •
8
An 8-bit device selection code to differentiate between up to 256 peripheral devices
{selection logic in a device's I/O bus interface responds only to its preassigned code}.
In normal practice, bits 6 through 11 perform the primary device differentiation between up to 64 devices with bits 12 and 13 coded to select an operational mode or
subdevice. A number of these device codes are hardwired into the processor and cannot be used to control peripheral devices.

OPERAT ION CODE

70S

__________AA__________

CLEAR
AC

GENERATE
AN lOP 2
PULSE

,-A---,

DEV I CE
SELECTION

~,(~

__________

~A~

__________

13114115116117

'---y------J

'----y-l

"--y-J

SUB-DEVICE
SELECTION

GENERATE
AN rop 4
PULSE

GEN ERATE
AN rOP1
PULSE
15-0203

Figure 3-5

lOT Instruction Format

3-28

O-SONS MAX.-+!
CP RUN

..J
FETCH

11111111

1+- 60 NS

1II111111~

11111111

1+-160NS MAX.

800N!~\ ~

EXECUTE

)

~Ij~----------------------~I

lOT REQ. _ _~-

lOT

L..._ _ _: . . -

- 1- 1~&Y.I.Il l tJ0 T01~SEC

I
---1
lOT SYNC

1+-250 NS

I -+\

lOP 1

1--1~SEC

____~I~~I--~k________________~

-9)
I¥'

I
lOP 2

I- 1 SEC
I,

1
-9 )
--SOONS)
_____~I___________FTl~______~______
I......

lOP 4

lOT DONE

____i__

~r_-'~,__r-~:~~~~
__________
:

AC ON BUS

L- _ _ _ _ .L _ _ _ _ _ _ _ _ _ _ ..L.._ _ _ __

15-0176

Figure 3-6

lOT Instruction Timing

3-29

A command code (bits 14 through 17) capable of being microprogrammed to clear
the AC and issue up to three pulses via the I/O bus.

The four machine cycles required to execute an lOT instruction consists of decoding of the lOT from
the central processor1s memory input buffer synchronization of the central and I/o processors, issuing
three sequential cycles of 1 ~ each to ensure lOP pulses at event times 1, 2, and 4, and finally the
fetch of the next instruction to be executed (see Figure 3-6). Bit 14 can be programmed to clear the
accumulator at the start of an lOT instruction. Bits 15-17 can be microprogrammed in any manner to
produce a pulse on the I/o bus for each bit set. Bit 17 causes an lOP 1 pulse, or the first pulse generated, and is normally used for testing the device status flags. Bit 16 generates an lOP 2 pulse, the
second pulse, and can be used in transmitting to or from a device to the processors. On "In ll transfers,
data is ORed from the I/O bus into the accumulator; therefore, bit 14, clear the accumulator, is typically used when a load the accumulator from a device is needed.

Bit 15 produces lOP 4 pulse, the

third pulse, and is used for control and transfer of data from the accumulator to the device. A summary of lOP pulses is as follows:
a.

IOP1 is normally used in an I/O skip instruction to test a device flag; however,
it can be used as a command pulse or a load of a device. It cannot be used to
initiate a IIread from" a device.

IOP2 is usually used to transfer data from the device to the computer, or to clear
a devi ce information register; it cannot be used to determine a "skipll condition.

IOP4 is usually used to transfer data from the computer to the devi ce; it cannot be
used to determine a IIskipli condition or to initiate a read from a device.
Programming Note
Execution of an lOT instruction and the next instruction
in sequence cannot be interrupted; i.e., PDP-15 does
not grant an interrupt request unti I the instruction following an lOT (and which is not an lOT itself) has completed its function.

3.7.1 PDP-15 lOTs
The following are internal PDP-15 lOTs:
lOT

Basic lOT Command

700000

This instruction performs an lOT nop, i.e., it is an lOT which sets no device
select or subdevice select bits nor produces any lOP pulses.
Execution Time: 2-3 ~
10F

Turn Interrupt Off

700002

Disables the Program Interrupt system of the PDP-15.
Execution Time: 3-4 ~

3-30

ION

Turn Interrupt On

700042

Enables the Program Interrupt system of the PDP-15.
Execution Time: 3-4 fJS
10RS

I/O Read Status

700314

This lOT reads the status of various device flags into the AC. Figure
shows the device and the bit to which each device flag is assigned.

PROGRAM
INTERRUPT
ON

TAPE
PUNCH
FLAG*

TELETYPE
PRINTER
FLAG*

REAL TIME
CLOCK
OVERFLOW
FLAG*

TAPE
READER
NO TAPE**

DEC
TAPE
FLAG *t

DISK
PACK*

LI NE
PRINTER*

,.--A--.,

,---A--...

,.-"--...

14 I 5

'--y--J

'--y--l

TAPE
READER
FLAG!!

TELETYPE
KEYBOARD
FLAG"

LIGHT
PEN
OR
DISPLAY
FLAG*

REALTIME
CLOCK
ENABLED

I 9 110 111 112 I 13 1 14

TAPE
PUNCH
NO PUNCH

RESERVED FOR
SPECIAL USERS
DEV ICES

MAG TA PE*tt

DEC
DISK*

* WILL CAUSE A PROGRAM INTERRUPT

*t INCLUSIVE

OR OF TRANSFER COMPLETION

*tt INCLUSIVE OR OF MTF AND

AND ERROR FLAGS

15-0202

** CAUSES A PROGRAM INTERRUPT THROUGH THE READER FLAG

CAF

Clear All Flags

703302

CAF causes a power clear to be sent out on the I/O bus which will clear
all device flags which call for I/o interrupt service, and stop I/O bus
activity •
Execution Time: 3-4 fJS
SPCO

Skip if PC-15

703341

This instruction tests to determine whether a PC15 paper-tape reader unit
is connected to the PDP-15. If it is, a skip wi II occur; if not, the next
sequential instruction in the program will be executed.
Execution Time: 2-3 fJS
SK15

Skip if PDP-15

707741

This is an unconditional skip in the PDP-15 but not in a PDP-4, 7, or 9.
Execution Time: 2-3 fJS
SBA

Ski P if Bank Addressi ng

707761

This instruction wi II cause the next insi'ruction to be skipped if the PDP-15 is
in Bank Mode.
Execution Time: 2-3 fJS

3-31

DBA

Disable Bank Addressing

707762

Causes the PDP-15 to turn off Bank Mode and enter Page Mode. In Page Mode,
the index register may be added to operand addresses in forming effective
addresses.
Execution Time: 3-4 IJS
EBA

Enable Bank Addressing

707764

Causes the PDP-15 to enter Bank Mode and disables the index register from
being used in the calculation of effective addresses.
Execution Time: 4-5 IJS
3.7.2 Teletype Keyboard
KSF

Skip on Keyboard Flag

700301

Tests the Teletype keyboard flag and causes the next instruction to be skipped
if the flag is set, indicating that the keyboard control has assembled a character from the Tel etype.
Execution Time: 2-3 IJS
KRB

Read Keyboard Buffer

700312

This lOT clears the AC and then reads the contents of the keyboard buffer
into AC bits 10-17, and clears the keyboard flag.
Execution Time: 3-4 IJS
KRS

Keyboard Reader Sel ect

700332

This lOT clears the AC, reads the contents of the keyboard buffer into AC
bits 10-17 and enables the keyboard reader to advance another character.
Reading from the keyboard reader is done in full duplex mode {no character
echo}. This lOT can also be used to read, full duplex, from Teletype
keyboard.
Execution Time: 3-4 IJS

3.7.3 Teletype Teleprinter
TSF

Skip on Teleprinter Flag

700401

Tests the status of the teleprinter flag to determine if the last character has
been printed. If the flag is set the next instruction wi II be skipped.
Execution Time: 2-3 IJS

3-32

TCF

Clear Teleprinter Flag

700402

Clears the teleprinter flag which had been set at the completion of the
previous character.
Execution Time: 3-4 fJS
TLS

Load and Select Teleprinter

700406

Clears the teleprinter flag, loads the teleprinter buffer from AC bits 10-17
and initiates printing of the character. The flag is set when printing is
completed.
Execution Time: 4-5 fJS

3.8 INDEX INSTRUCTIONS
The index instructions enable the programmer to transfer information between the accumulator, limit
register, and index register, clear the I imit register and index register, add a number contained in
the instruction itself ( ±256) to the accumulator, limit register, or index register and test to determine
if the index register is greater than or equal to the limit register.
All index instructions require two central processor cycles, but only one memory cycle, thus, allowing
the central processor to perform operations a! the same time as the I/O processor.
PLACE ACCUMULATOR IN INDEX REGISTER

721000

I >: : :< : ;,: : >: : :0; : ;0: I
Mnemonic Name:

PAX

Octal Code:

721000

Time:

2 cycles (l memory cycle)

Operation:

The contents of the accumulator are transferred to the index
register. The contents of the accumulator remain unchanged.

Symbolic:

AC -+XR

3-33

PAX

PLACE ACCUMULATOR IN LIMIT REGISTER

Mnemonic Name:

PAL

Octal Code:

722000

Time:

2 cycles (1 memory cycle)

Operation:

The contents of the accumulator is transferred to the limit
register. The contents of the accumulator remain unchanged.

Symbolic:

AC -.LR

PLACE INDEX REGIS TER IN ACCUMULATOR

Mnemonic Name:

PXA

Octal Code:

724000

Time:

2 cycles (l memory cycle)

Operation:

The contents of the index register are transferred to the accumulator. The contents of the index register remain unchanged.

Symbolic:

XR -.AC

3-34

PLACE INDEX REGISTER IN LIMIT REGISTER

726000

I :< : :< : >: : :<: >: : ;0:
Mnemonic Name:

PXL

Octal Code:

726000

Time:

2 cycles (1 memory cycle)

Operation:

The contents of the index register are transferred to the limit
register. The contents of the index register remain unchanged.

Symbolic:

XR -LR

PLACE LIMIT REGISTER IN ACCUMULATOR

Mnemonic Name:

PLA

Octal Code:

730000

Time:

2 cycles (1 memory cycle)

Operation:

The contents of the limit register are transferred to the accumulator. The contents of the Iimit register remain unchanged.

Symbolic:

LR -AC

3-35

PXL

PLACE LIMIT REGISTER IN INDEX REGISTER

Mnemonic Name:

PLX

Octal Code:

731000

Time:

2 cycles (l memory cycle)

Operation:

The contents of the I imit register are transferred to the index
register. The contents of the limit register remain unchanged.

Symbolic:

LR .... XR

ADD n TO INDEX REGISTER AND SKIP IF EQUAL TO OR GREATER
THAN THE LIMIT REGISTER

Mnemonic Name:

AXS n

Octal Code:

725000 + n (n=9 bits)

Time:

2 cycles (l memory cycle)

Operation:

n, a signed 9-bit (8 bits plus sign) 2 1s complement integer is
added to the contents of the index register, and the result is
placed in the index register. If the sum is greater than or
equal to the contents of the limit register I then the program
counter is incremented by 1 and thus the next instruction is
skipped.

Symbolic:

XR + N .... XR
If X R ~ LRI PC + 1 .... PC

3-36

ADO TO INDEX REGISTER

737 + n

I :

< : >: : >: : >: : : : : : :

Mnemonic I'~ame:

AXR+n

Octal Code:

737000 + n (n=9 bits)

Time:

2 cycles (l memory cycle)

Operation:

n, a signed 9-bit (8 bits plus sign) 2 1 s complement integer is
added to the content of the index register, and the result is
placed in the index register.

Symbolic:

XR+N ~XR

I AXR + n

ADD n TO ACCUMULATOR

723+ n

I :< : >: : :< : :< : : : : : : I
Mnemoni c Name:

AAC+n

Octal Code:

723000 +n (n=9 bits)

Time:

2 cycles (l memory cycle)

Operation:

n, a signed 9-bit (8 bits plus sign) 2 1s complement binary number, is added to the content of the accumulator, and the result
is placed into the accumulator.

Symbolic:

AC + N ~AC

3-37

AAC + n

CLEAR THE INDEX REGISTER

Mnemonic Name:

CLX

Octal Code:

735000

Time:

2 cycles (1 memory cycle)

Operation:

The content of the index register is replaced with all Os.
Former content is lost.

Symbolic:

o -XR

CLEAR THE LIMIT REGISTER

736000

I :<: >: : :<: :0; : :0; : ;0: I

CLLR

Mnemonic Name:

CLLR

Octal Code:

736000

Time:

2 cycles (l memory cycle)

Operation:

The content of the Iimit register is replaced with all Os. The
former content is lost.

Symbolic:

o -lR

3-38

Chapter 4
Addressing Features

4.1 INTRODUCTION TO MEMORY ADDRESSING
The PDP-15 Memory Reference instructi ons are used to operate on data that is stored in memory
locations. A memory reference instruction consists of an operation code and an address (see
Figure 4-1). The operation code determines how data is to be modified, and the address portion is
used to refer to a memory location. The contents of the referenced location are operated on according to the operation code of the memory reference instruction. The address of a specifi c memory
location always remains the same, however, the contents of the location are subject to change depending on the type of memory reference instruction executed.

4.2 TYPES OF ADDRESSING
The PDP-15 enables six types of addressing (refer to Table 4-1). Indexed addressing is allowed only
when the PDP-15 is in Page mode.

Table 4-1
Types of Addressing

Address
Type

Addressable Memory locations
Page Mode
Bank Mode

Direct

4,096

8,192

Indirect

32,768

Auto-Increment

131,072

Indexed

131,072

Not used

Indirect - Indexed

131,072

Not used

Au to- Increment Indexed

131,072

Not used

4-1

The table indicates the two modes of addressing available, i.e., Page and Bank mode.

Either

mode can be enabled or disabled through program control, or with a console switch at program start
time.
Page mode addressing causes the PDP-15 to use 12 bits (bits 6 through 17) of the memory reference
instruction as the operand address.

The PDP-15 is, therefore, capable of directly addressing a max-

imum of 4096 memory locations. Indirect, Indexed, or Auto-increment addressing must be used to
reference an address not within the addressing range of the 12 bits.
Bank mode addressing causes the PDP-15 to use 13 bits (bits 5 through 17) of the memory reference
instruction as the operand address. The PDP-15 is, therefore, capable of directly addressing a maximum of 8192 memory locations in Bank mode. Indirect or Auto-increment addressing must be used
to reference an address not within the addressing range of the 13 bits.

PAGE MODE ADDRESS FORMAT
The memory reference instruction word format for Page mode operation is as follows.

I:::::::::::::::::I
I~[

OPERATION
CODE

INDICATES

INDICATES
INDIRECT ADDRESSING
WHE N SET

INDEXED
ADDRESSING
WHE N SET
12 BITS SPECIFY
AN OPERAND ADDRESS

4-2

BANK MODE ADDRESS FORMAT
The memory reference instruction word format for Bank mode operation is as follows.

I:::::::::::::::::I
OPERAJION

;

CODE

13 BITS SPECIFY
AN OPERAND ADDRESS

INDICATES
INDIRECT ADDRESSING
WHEN SET

4.3 DESCRIPTION OF THE TYPES OF ADDRESSING
The following discussion is simplified by using mnemonics for the memory reference instructions. The
brief programming examples use octal memory addresses. Also, the absolute address of a specific
memory location is referred to as the Effective Address (EFA).
The mnemonics for the memory reference instructions are repeated below for easy reference.
CAL
DAC
JMS
DZM
LAC
XOR
ADD
TAD
XCT
ISZ
AND
SAD
JMP

Call subroutine
Deposit accumulator
Jump to subroutine
Deposit zero in memory
Load accumulator
Logical Exclusive OR
Add, lis complement
Add, 2 1s complement
Execute
Increment and skip if zero
Logical AND
Skip if AC different from memory
Jump

The program counter (PC) always points to the next instruction to be executed. Thus, in Bank mode
the PC is able to increment 20000 (octal) locations from memory address 00000 through 17777 of the
8K bank which con'tains the program. Refer to Figure 2-9 which illustrates memory organization in
terms of 4K pages, 8K banks, and 32K blocks.

4-3

4.3.1

Direct Addressing - Bank or Page Mode

The PDP-15 uses bits 5 through 17 in Bank mode, or bits 6 through 17 in Page mode, as the EFA for
direct addressing.
The following example illustrates direct addressing.

Instruction

000100

202222

(LAC 02222)

In the example, the instruction fetched from location 000100 (located in page 0 of bank 0) specifies
II load the AC with the contents of location 222211 (located in page 0 of bank 0).

Direct addressing is

indicated, and the EFA is 002222.

4.3.2 Indirect Addressing - Bank or Page Mode
Indirect addressing is specified when bit 4 of a memory reference instruction is set. Some of the frequent uses of indirect addressing include building or retrieving blocks of data in core memory and
referencing memory locations outside of the page or bank containing the program.
The following examples illustrate indirect addressing (* specifies indirect addressing).

Instruction

000200

221111

(LAC * 01111)

The instruction fetched from location 000200 specifies IIload the AC with the contents of the memory
location specified by the contents of 01111 (located in page 0 of bank 0). II If location 01111 contained 000300, the EFA would be 000300, and the contents of 000300 would be loaded into the
accumulator.
Indirect addressing enables the user to reference memory locations within a 32K memory bank (000000
through 077777 octal). In the above example, memory location 300 can be referenced in any memory
page by specifying the page in address bits 3, 4, and 5:

Instruction

000200

221111

4-4

(LAC * 01111)

If location 01111 contains 070300, the contents of location 300 in page 1 of bank 3 are loaded into
the accumulator.

4.3.3 Auto-Increment Addressing - Bank or Page Mode
The PDP-15 has eight special registers located in page 0, bank 0, block O. The eight registers are
memory locations 000010 through 000017. Whenever these registers are indirectly referenced by a
memory reference instruction, the content of the register is incremented by one before it is used as
the operand. The registers are called auto-inc!ement registers. The auto- increment feature is performed only when the register is referenced indirectly. The registers act as any other memory location
when referenced directly.
An auto-increment operation can be initiated from any page, bank, or block of memory. The PDP-15
auto-increments whenever a memory reference instruction specifies indirect addressing, and the address
points to any location from 000010 through 000017.
NOTE
The auto-increment register is incremented before the
content is used as the operand address.

Programming examples:
Auto-increment from page 0, bank 0, block 0, and read the data word stored in location 001000 into
the accumulator.
Step 1

Set the auto-increment register to the operand address value -1.
In this case, 000777.

Step 2

Reference the auto-increment register with indirect addressing
specified.

Step 3

The auto-increment register increments by one, and the EFA
is now the new value (001000) in the register.

Steps 1, 2 and 3 are represented in assembly language form as:

Step 1

LAC
K777
lDAC
10
{L~C * 10

Steps 2,3
K777

/Auto-increment register 10
/C(001000) loaded into AC

000777

/Constant for initial ization

4-5

When operating from a memory bank other than bank 0, the initial contents of the auto-increment
register must be set up using indirect addressing. If direct addressing is used, locations 10 through 17
of the bank containing the program are referenced.

For example, if operating in bank 2, Step 1 in

the previous example must be modified as:
Step 1

Step 2,3

K777

Kl0

LAC
DAC*

K777
K10

LAC*

IDeposit in location 10 of page 0,
Ibank O.
Ic (001000) loaded into AC

000777
000010

IThese constants are located
lin the same memory bank
las the main program.

4.3.4 Indexed Addressing - Page Mode Only
The PDP-15 central processor has an 18-bit index register (17 bits + sign) and a 17-bit program counter
(no sign) with appropriate data path and adder circuitry to compute 17-bit effective addresses.
Indexed addressing can only be used in Page mode operation and is indicated when bit 5 of a memory
reference instruction is set. With this "type of addressing, the user gains access to 131,072 memory
locations (000000 through 377777 octal) without adding an additional memory cycle to compute the
effective address (as does indirect addressing).
When indexed addressing is indicated, the effective address is calculated by 2's complement addition
of the 18-bit index register to the current block, bank, and page address, and bits 6 through 17
(address bits) of the memory reference instruction. The block, bank, and page address is indicated
by the program counter bits 1 through 5.
For example:
(XR) + (PC - ) + (ADDR) = the effective address
l 5
Where XR is the index register; PC - is program counter bits 1 through 5; ADDR is the address portion
l 5
(bits 6 through 17) of the memory reference instruction.
The following example illustrates indexed addressing:

PC = 003000

LAC

1(210100 octa I)

100,X

XR = 000100

4-6

The instruction fetched from location 3000 specifies II load the AC with the content of the effective
address calculated by adding PC - (00), the XR (l00) and the address field of the instruction (l00)."
l 5
This results in an effective address of 000200, because:
000100
+000100
000200

(XR)
(PCl-5) + (ADDR)
(EFA)

If operating in an extended memory bank or block, indexed addressing can be used to reference other
pages, banks, or blocks above or below the operating area.
Programming example:
The program is operating in block 2, bank 0, page 1 and must reference location 1000 in block 3,
bank 3, page 1 (location 371000):
PC = 213000

LAC

/(211000 octal)

1000, X

XR = 160000

The EFA is cakulat'ed in the following manner:
160000
+211000
EFA= 371000

(XR)
(PCl-5) + (ADDR)
(block 3, bank3, page 1, location 1000)

The program is operating in block 2, bank 0, page 1, and must reference location 1000 in block 0,
bank 0, page 0 (location 001000).
PC = 213000

LAC

XR = 570000

(negative val ue)

/(213000 octal)

1000, X

The EFA is calculated by:

EFA=

570000
+211000

(XR)
(PCl-5) + (ADDR)

001000

(block 0, bank 0, page 0, location 1000)

4-7

NOTE
The XR contains a negative value. In this case, it is the 2 1s
complement value of the current block, bank, and page.
All 18 bits (17 bits + sign) of the XR are involved when using
indexed addressing.
The EFA of the last example can also be calculated in the
following manner.

PC = 213000

LAC

200, X

/(210200 octal}

XR = 570600
570600
+ 210200
001000

(XR)
(PC 1-5) + (ADDR)
EFA

4.3.5 Indirect Indexed Addressing - Page Mode Only
Indirect indexed addressing is implemented only in Page mode and is indicated when both the indirect
addressing indicator (bit 4) and the indexed address indicator (bit 5) of the memory reference instruction are set.
When indirect indexed addressing is indicated, the PDP-15 central processor first calculates the
address indirectly referenced. This calculation is done in exactly the same manner as described in
the Indirect Addressing section. The PDP-15 carries the address calculation one step further, when
indirect indexing is specified. The contents of the index register are added to bits 3 through 17 of
the data word which was retrieved indirectly.
The addition (2 1s complement) of the XR is always the last step to occur (post indexing).
The following example illustrates indirect indexed addressing:
PC = 203000

DAC* 100, X

/(070100 octal}

XR = 000100
location 200100 = 007000
The EFA is calculated as:
007000
+ 2
207000
+ 000100
207100

(Contents of location 200100)
( PC l-2)
(XR)
EFA

4-8

The instruction fetched from memory location 203000 specifies "deposit the contents of the accumulator
into the memory location calculated by retrieving the contents of memory location 200100 (location
100 of the current block, bank, and page) and add the contents of the index register to the contents
of memory location 200100. II
The indirect address pointer is calculated by appending bits 1 through 5 of the PC to the 12-bit address
(6 through 17) of the instruction word resulting in a 200100 address pointer. An additional memory
cycle is required to retrieve the contents (007000) of memory location 200100. Bits 1 and 2 of the PC
(current block) are then appended resulting in 207000. The contents of the XR are then added, resulti ng ina fi na I EFA of 207100.

4.3.6 Auto-Increment Indexed Addressing - Page Mode Only
Auto-increment indexed addressing can be implemented only when operating in Page mode. This type
of addressing is specified when the indirect address indicator (bit 4) and the indexed address indicator
(bit 5) of the memory reference instruction are both set and address bits 6 through 17 equal a value of
10 through 17 octal.
When this type of addressing is specified, the PDP-15 central processor performs the following steps
to calculate the EFA:
Step

Procedure
The contents of the auto-increment register are retrieved, incremented by one, and then restored in the register.

The new contents of the auto-increment register are used as an
address pointer.

The contents of the XR bits 0 through 17 are added (2 1s complement) to the address pointer.

The sum is used as the final, or effective address (EFA).

The following example illustrates this type of addressing:
PC = 170245
DAC * 15, X
000015 = 000777
XR = 001000

'
/(070015 octal)

4-9

Following the procedure given above, the EFA is calculated as:

}

000777
1
001000

contents of location 15
increment
new contents of location 15
used as address pointer

+001000

contents of XR

Step 3

002000

EFA

Step 4

Step 1

4.4 SPECIAL ADDRESSING CASES
Certain instructions in the PDP-15 cross bank, page, and block boundaries ina special case, and other
instructions have limitations when crossing blocks.
JMS and JMP * Instructions
The JMS instructi on saves a 15-bit address at the subroutine entry point. This means that JMS,X
across block boundaries saves the return location address within a block, but not the block number.
A JMP * exit from a subroutine entered from a different block is not possible. A computed JMP,X
must be used.
CAL Instruction
The CAL instruction always falls to location 20 of block 0, bank 0, page 0, regardless of which block,
bank, or page it is issued from. This instruction has the same I imitations as the JMS instruction.
Au to- Increment Ins tructi ons
All auto-increment instructions (indirect memory references to locations 10-17 of any page, bank, or
block) increment the auto-increment registers in locations 10-17 of page 0, bank 0, block O. The
content of location 10-17 can point to any page, bank, or block.
All 18 bits are used as address bits. If the 18-bit address in the auto-increment register points to a nonexistent memory location and the memory protect option is installed, a nonexistent memory (NEXM)
error occurs. If the memory protect option is not available, the machine will hang, waiting for memory to respond to the request.

If a skip instruction (0 PERA TE, ISZ, SAD, or lOT) is located in the next to last memory location of a
bank, in Bank mode, or a page, in Page mode, and a skip is affected, the program will not wrap
around within the bank or page. Instead, the PC will be incremented over the bank or page boundary
to the first location of the next bank or page of memory.
4-10

4.5 PROCESSOR ADDRESSING
Program Interrupts
Program interrupts always go to location 0, page 0, of block 0 and save a 15-bit address {mostsignificant address bits truncated} in the same fashion as CAL.
Automatic Priority Interrupts
Automatic priority interrupts can be directed through the I/O device to any location within block 0
using 15 bits of I/o address lines. The JMS or JMS * in the vector location is always to a location
within block 0 and the JMS ,X is relative to block o.
Three-Cycle Data Transfers
Three-cycle data transfers can transfer data anywhere within memory because the word count and current address registers are 18 bits in length, however, the WC,CA register pair must be located within
block 0 and are specified by a 15-bit I/O address from the I/O device.
Single-Cycle Data Transfers
Single-cycle data transfers can be made to a" of memory. The I/O device must specify a 15-bit address on the I/O address I ines and a 2-bit block number on the Program Interrupt Request and Skip
Request lines. These lines are dual purpose lines which act as the most significant address bits during
single-cycle transfers, only the increment Skip Request acts as address bit 1 and the Program Interrupt
Request as bit 2, bits 3-17 are represented by the I/O address lines. All single-cycle devices should
have provisions for generating 17-bit addresses.

4-11

Chapter 5
1/0 Processor System

5.1 GENERAL DESCRIPTION
The I/o processor is the communication link between a diverse line of peripherals and the PDP-15
main memory and CPU. The I/o processor system provides a number of facilities for data transmission.
These I/O facilities enable the I/o processor system to provide data transfers to/from memory, data
transfers to/from the CPU, command status transfers, and interrupts. The architecture design of the

I/o processor provides a number of benefits for the user:
a.

Special purpose equipment can be easily and inexpensively interfaced to the system.

Synchronous and asynchronous devices can be handled with equal ease.

Real-time appl ications are easily implemented because of the speed and efficiency
of the I/O processor.

The capabil ities of the I/o faci I ities are described in Table 5-1 •

Table 5-1
I/O Capabilities

Facility

Remarks
Data Transfers To/From Memory

Multicycle Data Channel Input

Used to transfer data to core memory in up to 18-bit
bytes at high speed (250 kHz) •

Multicycle Data Channel Output

Used to transfer data directly from memory in up to
18-bit bytes. Maximum speed is 188 kHz.

Add-to-Memory

Used to add the contents of a device register to the contents of a specified core location in 18-bit bytes. Good
for signal averaging. Maximum speed is 188 kHz.

Increment Memory

This faci I ity allows an external device to increment the
content of a core location by 1. Useful for generating
histograms. Maximum speed is 333 kHz.

5-1

Table 5-1 (Cont)

I/o Capabilities
Facility

Remarks

Data Transfers To/From Memory (Cont)
Single-Cycle Data Channel Output

With this DMA faci I ity a device can transfer a burst of
data from core memory at 1 mHz in la-bit bytes.

Single-Cycle Data Channel Input

Used to 'transfer a burst of data from a devi ce to core
memory at 1 mHz per la-bit word.
Data Transfers To/From CPU

Addressable I/O Bus

With this facility, up to 40 devices can transfer data in
la-bit bytes to or from the central processor. Cost of
interfacing is minimal. A typical transfer is one transfer every 200 f.IS.
Command and Status Transfers

Addressable I/O Bus

Command and status information can be transferred to or
from the CPU in the same manner as ordinary data.

Read Status

This is a special facility designed to aid the user in
monitoring vital flags in the system. Each device is assigned a bit for its flag (s), which is read onto the addressable I/O bus into the CPU when the Read Status
command is given. No two devices should use the same
bit.

Skip

The addressable I/o bus allows the computer to test the
status of a flag (typica"y) by issuing a pulse which will
echo if the addressed flag is up. Every flag that posts
a program interrupt should be identifiable by the skip
facil ity.
Interrupts

Program Interrupt

A" devices share a common program interrupt line.
When a device posts an interrupt the computer is forced
to JMS to location 0, bank 0, and then on to a service
routine designed to identify the requesting device using
the skip facility. The process requires CPU and memory
overhead and takes time.

Automatic Priority Interrupt

The automatic priority interrupt (API) fac il ity provides
priority servicing of many I/o devices with minimum
programming and maximum efficiency. Its priority
structure permits high data rate devices to interrupt the
service routines of slower devices, with a minimum of
system overhead.

5-2

5.2

I/o PROCESSOR PRIORITY STRUCTURE

All I/O related transfers function within the precedence of the following priority structure:
a.

Data Channel (DCH) requests (highest priority)

Real-Time Clock (RTC) (optional)

Automatic Priority Interrupts (API), 8 Levels (optional)

Program Interrupts (PI)

Main Program in Progress {lowest priority)

The data channel requests are the highest priority and will be serviced first, even if all other requests
are raised simul taneously. If a lower priority request is being serviced and a DC H request is generated,
the DC H request must wait until the end of the current I/o activity execution to be serviced.

5.3 THE DATA CHANNEL CONTROLLER
The data channel confToller provides the system user with one channel for high-speed data transmission.
This channel has the capacity for eight I/O devices, which are chained linked. Devices using either
single-cycle block transfer or multicycle block transfer can easily be intermixed on this data channel
in any configuration desired.

5.4 MUL TICYCLE CHANNEL BLOCK TRANSFER
The data channel controll er supervises the multi cycle channel block transfer function. When the
multicycle block transfer has been initiated, the data transfer becomes completely automatic and requires no access to the CPU. The CPU is free to do computation whi Ie the data channel is active.
The on Iy limitation on simultaneity Iies in sharing the main memory. Because the I/O processor has
first priority on memory requests, the CPU is effectively locked out for three cycles. As data channel
block transfers approach the maximum rate, (back-to-back breaks), the CPU can be completely locked
out.
To transfer data using the multicycle block transfer mode, the user must initialize two sequential core
locations. The contents of these core locations contain the word count and current address.
The word count represents the number of words to be transferred in the block. The current address
represents the location to which the data is to be transferred. The I/o processor contains the control
logic and I/o adder to automatically fetch the contents of these locations and increment the contents
of each.

5-3

The multicycle channel block transfer is a three-cycle sequence. Data is written into and read from
memory in three I/o processor cycles. The output cycle occurs during the third I/O processor cycle.
The I/o processor is stopped to allow settling of the I/O bus and control gates, prior to strobing
the data word into the device buffer register.
The multicycle block transfer is flowcharted in Figures 5-1 and 5-2. The data transfer is initiated by
an input/output instruction to the device after the two core locations have been initialized to minus
the word count and current address minus one. During the first cycle, the contents of the word count
location are incremented by one and restored. Dudng the second cycle, the current address is incremented by one and restored. The I/o processor continues to transfer data sequentiany unti I the word
count register reaches zero, at which time an interrupt is generated to notify the monitor that the block
transfer is complete.
Assuming initial ization of the two core locations has taken place, the data transfer from device to
memory (see Figure 5-2) occurs as follows:
a.

An instruction from the service routine enables the device controller. This allows
the device controller to request a data transfer from the I/O processor.

When the device controller's data buffer registers are full, the device issues a IIdata
channel request. II

The I/o processor acknowledges the request by returning a IIdata channel grant. II

The device controller then generates a fixed code pointing to the initial ized word
count core memory location. This fixed address is transmitted over the common I/O
bus address lines and is stored in the data storage register of the data channel controller.

The I/o processor then generates a "memory cycle request. II The address data, in the data storage
register, is then stored in the memory address register of the memory bank; the data (word count),
from the first word of the two locations that the MA is now pointing to, is transmitted out of memory
and into the data channel controller's adder. The word count data is incremented by one and stored
back in memory.
When the word count data register overflows, a signal 0/Vord Count Overflow) is sent to the device to
terminate all future block transfers. The monitor is also notified that this condition exists.
During the second I/O processor cycl e, the fixed code from the device controller is gated through
the I/o adder and is incremented by one. The memory address register then receives th is address.
The contents of this address are read out of memory, incremented by one, then restored in, memory.
The new contents, known as the current address, will be the location where the next data transfer
occurs.

5-4

CENTRAL PROCESSOR
PROGRAM INITIALIZES
WORD COUNT AND
CURRENT ADDRESS
LOCATION

l
PROGRAM INITIALIZES
STARTS DEVICE
WITH INSTRUCTIONS

I
I/O PROCESSOR
WHEN THE I/O PROCESSOR IS READY A
GRANT IS ISSUED
TO REQUESTI NG
DEVICE

DEVICE
WHEN DEVICE HAS
DATA READY OR
NEEDS DATA A REQUEST IS PLACED
ON THE I/O BUS

I
THE DEVICE
SUPPLIES THE ADDRESS OF THE WORD
COUNT,CURRENT
ADDRESS PAIR
J

THE I/O PROCESSOR
FETCHES, INCREMENTS,
REPLACES
THE WORD COUNT

IF WORD COUNT
~ OVERFLOW, THEN A'N
OVERFLOW IS SENT
TO DEVICE

DEVICE CLEARS ITS
ENABLE AFTER
CURRENT WORD
HAS BEEN
TRANSFERRED

~
THE I/O PROCESSOR
FETCHES,INCREMENTS,
RESTORES THE
CURRENT ADDRESS

~
THE I/O PROCESSOR
FETCHES DATA
SPECIFIED BY THE CA,
PLACES IT ON THE
BUS

~
THE DEVICE STROBES
THE DATA INTO ITS
REGISTER

1
SET A PROGRAM
INTERRUPT TO
INDICATE DONE
CPU

IS
DEVICE
STILL ENABLED

?
YES

PROGRAM I NTERRUPTED
NOTIFIED
THAT DEVICE IS
DONE

15-0004

Figure 5-1

Multicycle Out Block Transfer I Flowchart

5-5

CENTRAL PROCESSOR
PROGRAM INITIALIZES
WORD COUNT AND
CURRENT ADDRESS
LOCATION

•

PROGRAM INITIALIZES
STARTS DEVICE
WITH INSTRUCTIONS

DEVICE
-WHEN DEVICE HAS
DATA READY OR
NEEDS DATA A RE- rQUEST IS PLACED
ON THE I/O BUS

I
110 PROCESSOR
WHEN THE 1/0 PROCESSOR IS READY A
GRANT IS ISSUED
TO REQUESTI NG
DEVICE

THE 1/0 PROCESSOR
FETCHES,INCREMENTS,
REPLACES
THE WORD COUNT

.
THE DEVICE
SUPPLIES THE ADDRESS OF THE WORD
COUNT,CURRENT
ADDRESS PAIR

IF WORD COUNT
__ OVERFLOW, THEN AN
OVERFLOW IS SENT
TO DEVICE

DEVICE CLEARS ITS
ENABLE AFTER
-"'" CURRENT WORD
HAS BEEN
TRANSFERRED

THE I/O PROCESSOR
FETCHES, INCREMENTS,
RESTORES THE
CURRENT ADDRESS

!
THE I/O PROCESSOR
TAKES DATA FROM
DEVICE AND
STORES IT IN
MEMORY LOCATION
SPECIFIED BY CA

I
NO

•

SET A PROGRAM
INTERRUPT TO
INDICATE DONE
CPU

IS
DEVICE
STILL ENABLED

?
YES

PROGRAM I NTERRUPTED
NOTIFIED
THAT DEVICE IS
DONE

15-0004

Figure 5-2

Multicycle In Block Transfer, Flowchart

5-6

TO MEMORY BANKS

1
MEMORY PORT SWITCH

r--- - - - - - - - - - - - - - - - - - - - - - --- - - - - - ------,

.----

I
DATA
STORAGE
REGI STER

MEMORY
GRANT

MEMORY
REQUEST

I
L __
I/O ADDER

L
MIXER LOGIC

----~

CENT RAL
PROCE SSOR

REQUEST/
GRANT
LOGIC

-- -----

I
I

BUS BUFFER

I
I

110
PROCESSOR

L_ -- - - - - - - - - - - - - - - - - - - - - - - --- ___ ~~S!S2~-.J

l/OOFLO

FROM
I/O BUS
ADDRESS
LI NES

TO/FROM BIDIRECTIONAL
I/O BUS DATA LINES

DATA
CHANNEL
GRANT

'--

DATA
CHANNEL
REQUEST

~--------~----------~

TO
110 BUS
15 -000 5

Figure 5-3 Multicycle Transfer Implementation
During the third I/o processor cycle, the current address is read into the memory address register.
This address then points to the location where the I/O data word wi \I be transferred.
A memory request/grant synchronization again occurs, and the data in the storage register is strobed
into the memory location ending the cycle. Data output follows the same sequence, with the exception that one additional I/O processor cycle is required in order for the I/O bus to have sufficient
time to settle down before data from the bus is strobed into the device register.

5-7

5.5 SINGLE-CYCLE BLOCK TRANSFERS
Single-cycle block transfers (see Figure 5-4L are used by high-speed peripherals that normally
transfer complete records (blocks) of information, such as disks. A single cycle of the I/O processor
takes 1 fJS, a IIowing a maximum transfer rate.
Hardware reg isters, designed into the device controllers of the high-speed peripherals, store the
IIcurrent address II (the memory location where data is currently being transferred), and the IIword
count ll (the number of words remaining to be transferred in a block). These registers are loaded by
input/output transfer (lOT instructions issued by the CPU).
Device testing and initialization are handled by the CPU via lOTs to provide supervisory control. A
subsequent JOT initiates the data transfer. The I/o processor uses the current address information to
address core memory, then strobes the data between memory and the device controller buffer register.
Logic within the device controller then increments the current address register and the word
PROGRAM INITIATE
WORD COUNT(WC) a
CURRENT ADDRESS
(CA)THEN ENABLES
THE DEVICE

count register to provide sequential block
transfer.

DEVICE

When the word count register overflows at the

DEVICE POSTS A
SINGLE CYCLE REL---------I"QUEST WHEN
I/O PROCESSOR
READY

end of a block transfer, an interrupt is generated to allow the monitor system to take further

DATA CHANNEL
GRANT IS ISSUED
WHEN I/O PROCESSOR IS READY

action. This action includes disconnecting the
devi ce from the I/O bus, or reloading the de-

DEVICE SUPPLIES
CURRENT ADDRESS
'---_ _ _ _ _ _~AND DATA TO 1/0
BUS, THEN INCREMENTs ITS WORD
COUNTS
DATA CHANNEL
CONTROLLER REQUESTS MEMORY
AND SUPPLIES
CURRENT ADDRESS
AND DATA IN
SEQUENCE

vice controller registers for another block
transfer. The maximum number of transferrable
words in a single block is 131,072.
Figure 5-4 illustrates the method the data controller uses to handle a single-cycle transfer.
Assuming that the program has initiated the
word count and address of the device controller
and has then enabl ed it, the following occurs:
a.

The device controller sets a singlecycle data channel request to the
J/O processor.

b•

The I/o proc essor, as soon as it
becomes available, acknowledges
the request by returning a "data
channel grant. II The device then

15-0006

Figure 5-4

Single-Cycle Block Transfer
Flowchart

5-8

b.
(Cont)

strobes both its current address and its data onto the I/o bus and to the processor. The
data channel controller feeds the current address through its adder to the data storage
register. A memory cycle is requested, and this address is strobed into the memory address buffers. The data is then strobed off the 18 I/O data lines and into the memory location specifi ed by the current address. During this operation, the device increments its
own word count and disables itself on overflow. It then sends an interrupt to the monitor
to indicate that its operation has been completed.

5.6 INCREMENT MEMORY
The increment memory mode enables an external device to add to the contents of any memory location
in a single-cycle operation. The device controller suppl ies the core address and the I/o processor
simply goes through the word-count cycle of a multicycle channel transfer. This effectively adds 1
to the specified location. This feature is particularly useful for in-core scaling and counting in pulseheight analysis.

5.7 ADD-TO-MEMORY
Add-to-memory is a standard feature of the PDP-15 that adds unique capabilities to the already powerful I/o facilities.

In add-to-memory mode, the contents of an external register can be added to the

contents of a memory location in four cycles. This feature is extremely valuable in signal averaging
and other processes requiring successive sweeps for signal enhancement.
The add-to-memory operation is a combination of multicycle data channel input and output operations.
The data transmitted by the device is added to a word read out of memory as specified by the current
address, and the resul t is rewritten into the same location. It is simultaneously transmitted to the device via the I/O bus.

5.8 PROGRAM-CONTROLLED TRANSFER
Program-controlled transfers, implemented by input/output transfer (lOT) instructions, can move up to
18 bits of data between a selected device and the accumulator (AC) in the CPU. The devices involved
are connected to the addressable I/o bus portion of the I/o processor. A total of up to 42 device
controllers can be attached to 'this bus. lOT instructions are microcoded to effect response only for a
particular device. The microcoding includes the issuing of both a unique device selection code and
the appropriate processor-generated input/output pulses to initiate a specific operation. For an "out"
transfer, the program reads a data word from memory into the AC. A subsequent lOT instruction places
the data on the bus, selects the device, and transfers the data to the device.

For an "in" transfer, the

process is reversed: an lOT instruction selects the device and transfers data into the AC. A subsequent
instruction in the program transfers the word from the AC f'o memory.

5-9

As previously mentioned, lOT instructions are also used to initialize the single- and multicycle
channels and the transfer word count and current address information to the single-cycle controllers.
In addition, these instructions are used to test or clear device flags, select modes of device operation,
and control a number of processor operations.
The lOT instruction consists of the lOT fetch from core memory and three sequential cycles. The 10Pl
and IOP2 are 1 ~ intervals; the IOP4 is 500 fJS interval.

The positive assertion of the lOT signal is

variable from 0 to 1 fJS. Thi,s variation is caused by I/o processor synchronizing. Refer to Chapter 3
for lOT instruction formats.
The total time required to fetch and execute an lOT instruction is a maximum of 5.02 fJS and a minimum
of 3.96 fJS. The I/O processor allows the generation of an 10Pl only or an IOP1 and IOP2 only as required. When an out transfer is used generating the IOP4, the full sequence of 10Pl and IOP2 are
also generated. Refer to Table 5-2 for total execution times of lOPs.

Table 5-2
Total Execution Times for lOPs

Issue

Instruction

Total Time for lOT
Fetch and Execute
Min

Max

10Pl (only)

SKIP

2.21 fJS

3.27 fJS

IOP2 (only)

In Transfer

3.21 fJS

4.27 fJS

10Pl and IOP2

In Transfer

3.21 fJS

4.27 fJS

IOP4

Out Transfer

3.96 fJS

5.02 fJS

The 10Pl is normally used in an I/O SKIP instruction to test a device flag. The 10Pl can be used as
a command pulse, but cannot be used to initiate a IIread from ll a device. Because the CPU accumulator register is used for both data lIin ll and 1I0ut ll transfers, a lIc1ear AC II microinstruction (Bit 14)
can be used during the 1 ~ interval of the IOP1 •
The IOP2 is usually used to transfer data to and from the device to the computer, or to clear the device's information register. It cannot be used to determine a "skipll condition.
The IOP4 is normally used to effect programmed transfers of information from the AC to a selected
device.

5-10

0- 60 NS MAX.~

CP RUN

FETCH

11111111

--I \+-60 NS
111111111\

ImlllM

--I
EXECUTE

)
lOT REQ.

lOT

800

~-I~~lIIjjOT01~SEC

\+-250 NS

I
j+- 1 Il- SEC

.....,

lOP 1 ----~~I~---~,,~

________________~

-..J)

_ _----II~

1-1

~SEC

~, _ _~

-I ) I·

lOT DONE

N!I~"" ~

lOT SYNC

lOP 4

\+-f60 NS MAX.

____~I¥~----------------------------~I------~~_
I
.....J

lOP 2

l+-

500NS /

--------~--------------~~~----------~------

______________

~r~-_~~I__~r_-~~:__~r__l~

L____ 1__________ __________
~I

AC ON BUS

15-0176

Figure 5-5

lOT InstrucHon Timing

5.9 PROGRAM INTERRUPT FACILITY
The program interrupt (PI) system is standard on all PDP-15 Systems. The program interrupt (PI)
facility, when enabled, relieves the main program of the need for repeated flag searching byallowing the ready status of I/o device flags, to automatically cause a program interrupt. The CPU can
continue with execution of a program until a previously selected device signals that it is ready to
transfer data. At that time, the program in process is interrupted and the contents of the program
counter (15 bits), user mode (l bit), link (l bit), and bank mode are stored in location zero. The
instruction, in location 000001, is then executed, transferring control to an I/O service routine.
When completed, the routine restores the system to the status prior to the interrupt, enabl ing the

5-11

interrupted program segment to continue. Where multiple peripherals are connected to the PI line,
a search routine containing device - status testing {skipping} instructions must be added to determine
which device initiated the interrupt request. The program interrupt {PI} control is enabled or disabled by lOT instructions. When disabled, the PI ignores all service requests, but each request remains on line and is answered when the PI is enabled. The program interrupt is automatically disabled
when an interrupt is granted or when the I/O Reset Key {on the console} is depressed. The program
interrupt is temporarily inhibited while the automatic priority interrupt system is processing a priority
interrupt request. The PIE indi cator {on the console} is I ighted while the PI is enabled.
A free instruction follows the program interrupt and therefore, the instruction in location 1 will always
be executed immediately after the program interrupt.

5-12

Chapter 6
Options

6.1 KE15 EXTENDED ARITHMETIC ELEMENT
The extended arithmetic element (EAE) option adds the hardware necessary to implement the EAE
instructions. This c lass of instructions, identified by an operation code of 64 , performs high-speed
8
data manipulation and multiply-divide operations as specified by microprogramming of individual
instructions. Figures 6-1 through 6-5 illustrate the microinstruction capabilities for register setup,
data shift, normal ize, multiply, and divide.
The time required to execute a~ EAE instruction is a function of the operation and/or the shift, or
step count specified by programming. In general, the following considerations apply to the different
types of EAE operati ons.
1.

All set-up instructions require 1 .324 I-IS.

Long register shift instructions require a time e.qual to 2.915 IJS plus 0.133 IJS per
I n-1" bit-position shifts.
This count is specified by the addition of n(octal) to the instruction code. For example, the input of the symbol ic instruction LLS+ 14 to the PDP-15
assembler would result in an instruction code that specified a long left shift of the AC
and MQ (taken as a 36-bit register) 12 bit positions to the left. This instruction would
10
require 4.378 I-IS.

The ASL and ALSS instructions, respectively, AC left shift and AC left shift signed, also
require the specification of lin. II

The normalizing instructions, NORM and NORMS, require an execution time equal to
2.9 jJS plus 0.133 jJS per number of bit positions shifted to normalize (ACO =I AC1)
quantity. These instructions are microprogrammed to set the 6-bit step count to 448
(3610). Hence, -44+n8 (the step count is entered in 2 1s complement notation at execution) equals the biased scale factor of a normal ized quanti ty.

Multiply instructions require a time equal to 2.915 I-IS plus 0.265 I-IS per -1 lin II bit position
shifts. Multiply instructions are microprogrammed to set the step count to 228 (1810),
representing the multiplication of one 18-bit quantity (sign bit and 17 magnitude bits for
signed quantities) by another to produce a 36-bit product. The execution time is 7.420 jJS.
Where such precision is not required, the microprogrammed step count can be decreased
by subtracting the appropriate number lin II (octal) from the instruction code. The product
is always left justified in the AC, MQ. If II-nil is appended to a multiply instruction,
the IIn" low-order bits in the long register are meaningless.

6-1

Divide instructions require a time equal to 2.915 f..IS plus 0.265 f..IS per "n" bit position
shifts. Divide instructions are microprogrammed to set count to 238 (1910), representing
division of 9 36-bit dividend (actual or imp I ied) by an l8-bit divisor. The execution
time is 7.685 f..IS. Where such precision is not required, the microprogrammed step count
can be decreased by subtracting the appropriate number "n ll {octal from the instruction
code}. For example, the symbol ic instruction DIV-12 would result in a right-justified
quotient with the most significant bit in MQ9' The execution time is decreased in correspondence to the decrease in the step count.

6. 1. 1 EAE Mi croinstructions
Figure 6-6 and Tables 6-1 and 6-2 describe the EAE instructions and illustrate the microinstructions
of the EAE instructions. If an existing instruction is not satisfactory, the programmer can combine
the appropriate microinstructions to achieve the required result.

OPERATION
CODE 64
SPECIFYING EAE

CLEARS MQ
AT TIME
STATE B

CLEARS AC
AT TIME
STATE C

,-A---"

[

LOADS THE AC
WITH THE OR
OF AC AND
THE MQ AT
TI ME STATE C

UNUSED IN
SETUP

[ 9

[ 10

'-y---J

"-......--~yr----

S HI F TS
ACOO INTO
L AT TIME
STATE A

EAE COMM AND Os
FOR SETUP

[

14 [ 15 [ 16 [ 17 [
'-y---J

'-y-'

COMPLEMENTS
LOADS
THE MQ
THE AC
AT TI ME
WITH THE
STATE B
OROFTHE
CONTENT OF
THE AC AND
THE SC Ar
LOADS THE MQ WITH THE}
TIME STATE B
OR OF THE CONTENT OF
WHEN BIT 6 IS
THE AC AND THE MQ AT
A 1 AND BIT 7 IS
TIME STATE B
A O,THE NUMBER IN
SHIFTS ACOO INTO EAE AC
SIGN FLIP-FLOP AT

THE AC IS CHANGED TO
ITS ABSOLUTE VALUE

TIME STATE A
15 -0189

Note: Setup Instructions cannot be microprogrammed with
Normalize Multiplication or Division Instructions.
Figure 6-1

EAE Setup Microinstructions

OPERATION
CODE 64
SPECIFYING EAE

CAN BE USED IN
IN MICROPROGRAMMING
SAME FUNCTIONS AS FOR
SETUP INSTRUCTIONS

STEP COUNTER PRE-SETTING
(SET TO THE NUMBER OF
BINARY POSITIONS TO BE SHIFTED)

"----y--J

'-_-----..y,.---_--J

SHIFTS
ACOO INTO
LATTIME
STATE A
SIGNED
OPERATIONS

EAE COMMAND
5S= LONG RIGHT SH I FT
6S=LONG LEFT SHIFT

7S=AC LEFT SHIFT
15-0190

Figure 6-2

EAE Shift Microinstructions

6-2

OPERATION
CODE 64
SPECIFYING EAE

______

~A~

______

UNUSED WITH
NORMALIZE
COMMANDS

STEP COUNTER PRE -SETTING
(USUALLY 448~NORMALlZE)

r-------~A~--------~

'-----y----J
SHI FTS
ACOO INTO
L AT TI ME
STATE A FOR
SIGNED
OPERATIONS

EAE COMMAND
48 FOR NORMALIZE

15-0191

Figure 6-3

EAE Normalize Microinstructions

SHIFTS ACOO INTO E A E AC
SIGN FLIP-FLOP AT TIME
STATE A
LOADS THEl MQ WITH THE OR
OF THE CONTENT OF THE AC
AND THE MQ AT TI M E
STATE B

OPERATION
CODE 64
SPECIFYING EAE

EAE COMMAND
'8 FOR MULTIPLY
r------A--------.,

'---y----I

BIT41SA

IS A , SO
THAT LINK IS
NOT DISTURBED
AND MQ IS CLEARED
AT TIME STATE B

~--------------"yr-------------~

CLEARS AC
AT TI ME
STATE C

o AND BIT 5

STEP COUNTER PRE-SETTING
(USUALLY 228 FOR MULTI PLY)

15-0192

Figure 6-4

USED WITH
INTEGER
DIVIDE TO
CLEAR THE
MQ AT TI ME
STATE B

OPERATION
CODE 64
SPECIFYING EAE
r -_ _ _ _ _ _~A~

________--.,

EAE Multiplication Microinstructions

USED WITH
INTEGER
DIVIDE TO
LOAD THE
MQ WITH THE
CONTENT OF
THE AC AT
TIME STATE B

,.---A--,

4
'-y---J

EAE COMMAND
38 FOR DIVIDE
r -_ _ _---'A~____----,

5
~

'--y---J

UNUSED
USED WITH
SIGNED
IN DIVIDE
SO THAT
DIVISION
LINK IS
TO SET
NOT DISTURBED THE SIGN
EXCEPT FOR
OF THE
OVERFLOW
DIVIDEND
ACOO INTO
THE EAE
SIGN FLIP-FLOP

t2
~

____________

USED WITH
INTEGER
DIVIDE TO
CLEAR THE
AC AT
TI ME
STATE C

~y~

____________- J

STEP COUNTER PRE - SETTING
(USUALLY 238 FOR DIVIDE)

15-0193

Figure 6-5

EAE Division Microinstructions

6-3

: C BUS--A BUS:

C BUS

A BUS

L Il
I

~ C BUS- A BUS

.r---

1 - - - - - - - - - - - - - - - - - - --,
I

MEMORY
INPUT

I c;]

ACCUMULATOR

I
I
I
I
I

I I

STEP
COUNTER

I ~

SIGN

I
I

I
o

MULTIPLIER
QUOT lENT
REGISTER

NO SHIFT
SHIF,9RLOGIC

I
I
I
I
I
I
I
I

I
tI

L ___ ~X~~~~HMET~ ELEMEN2- _ _ _ _ _ _ -.J

MEM IN

NO SHIFT
OR
SHIFT LOGIC

I
15-0177

Figure 6-6

EAE Simplified Block Diagram

Table 6-1
EAE Microinstructions

EAE
TIME
STATES

I l' I 2 ~j~ ~~ V5~
0

I\.
I
I
I
I

'J'1

)

(64)

EAE OP CODE

COMMON EVENTS
(UNLESS
OTHERWISE
NOTED)

•• r

Q::;;

•

5.1D

ILl

0
0

EAE
COMMAND
000 Setup
000 Multiply
010
011 Divide
100 Normalize
10 1 LonO Rioht
1 10 Lono Left
111 AC Left

~I~ 1>=t
OC/)

1>
o

II
II ...

-0

rrl1>

J>O
11'10

AC -+ C BUS

C BUS -+ A BUS

/o/t'~~
/1
I
" J '21'31'4 )~~~~~

)

EAE COMMAND" 000
LOAD STEP COUNT

I
I
I
I

MQ -+ C BUS
C BUS -.. A BUS
LD MQ
MQ-.MQ

•
••

:.~

J>
ID

rrl

•• 01

~I~
DC/)

~ ~

DID

0
ID

rrl
1>
rrl

3:J>
DID
C
C/)

0
0

3:
3:

cC/)

---

I
I
I
I
I

(i)

0<
0
(i)

AC - .. C BUS
C BUS -.. A BUS
LD AC
: . AC -..AC

1>
ID

rrl
1>
(")

~
0
ID
cC/)

II
0
0
0

enrrl
-i

:.~ :.~

~,
~ ~ C/)o

OlD

3:0
DID

~~
1>

D I NO OPERATION
I

E,F

II
I

(EAE COMMAND
¢ 000)
ALL SHIFT,MULTIPLY AND DIVIDE
OPERATIONS
15-0422

6-5

Table 6-2
EAE Microinstructions

Bit
Positions

Binary
Code

Function

Enter the content of AC O in the link for signed operations.

Clear the MQ.

Read the content of ACO into the EAE AC sign register
prior to-carrying out a signed multiply and divide operation.

6,7

Take the absolute value of the AC. Takes place after the
content of ACO is read into the EAE AC sign register.

Indusive OR the AC with the MQ and read into MQ.

Clear the AC.

9,10,11

000

Setup. Accompanies code in bits 15, 16, and 17.

9,10,11

001

Multiply. Causes the number in the MQ to be multipl ied
by the number in the memory location following this instruction. If the EAE AC sign register is 1, the MQ is
complemented prior to multiplication. The exclusive OR
of the EAE AC sign and the I ink is entered in the EAE sign
register.
The product is in the AC and MQ, with the lowest order
bit in MQ bit 17. At completion, the I ink is cleared and
if the EAE sign is a 1, the AC and MQ are complemented.

9,10,11

010

Unused operation code.

9,10,11

011

Divide. Causes the 36-bit number in the AC and MQ to
be divided by the 18-bit number in the memory register
following the instruction. If the EAE AC sign is 1, the
MQ is complemented prior to starting the division. The
exclusive OR of ACO and the link is placed in the EAE
sign register. The AC portion of the dividend must be
less than the divisor or divide overflow occurs. In such
cases, the I ink is set and divide does not occur. Otherwise, the link is cleared. At completion of this instruction, if the EAE sign was a -1, the MQ is complemented.
Thus, the remainder has the sign of the dividend.

9,10,11

101

Long right shift. Causes the AC and MQ to be shifted right
together as a 36-bit register the number of times specified
in the instruction. On each step, the link fills AC bit 0,
AC bit 17 fills MQ bit 0, and MQ bit 17 is lost. The
I ink remains unchanged.

9,10,11

110

Long left shift. Causes the AC and MQ to be shifted left
together the number of times specifi ed in the instruction.
On each step, MQ bit 17 is fi lied by the I ink; the I ink remains unchanged. MQ bit fills AC bit 17, and AC bit
is lost.

6-6

Table 6-2 (Cont)
EAE Microinstructions

Bit
Positions

Binary
Code

9,10,11

100

Normalize. Causes the AC and MQ to be shifted left together unti I the step count is equaled or AC bit 0 I- AC
bit 1. MQ bit 17 is filled by the I ink; the I ink is not
changed. The step count of this instruction is normally
44 (octal). When the step counter is read into the AC, it
contains the number of shifts minus the initia I shift count
as a 2 1s complement 6-bit number.

9,10,11

111

Accumulator left shift. Causes the AC to be shifted I eft
the number of times spec ified in the shift count. AC bit
17 is filled by the link, but the link is unchanged.

Function

12-17

Spec ify the step count for a II EAE commands (9-11) except
the setup command.

The setup command only, causes the MQ to be complemented.

The setup command only, causes the MQ to be inclusively
ORed with the AC and the result placed in AC.

The setup command only, causes the AC to be inclusively
ORed with the SC and the results placed in AC bits 12-17.

BASIC EAE INSTRUCTION

Mnemon i c Name:

EAE+n

Octal Code:

640000

Time:

Depen ds on instruction

Operation:

The addition of "n" (octal) to the mnemonic converts the basic
instruction into a microcoded instruction to accompl ish a setup,
shift, or arithmetic operation not already in the instruction repertoire. Refer to Table 6-1 for descripti ons of the functional
use of the individual bits of an EAE instruction. The sole restriction for the development of "n" is that the microcoded operations must not occur during the same time state 1 if they logically confl i ct.

Symbolic:

No operation.

6-7

EAE SETUP
INCLUSIVE OR SC WITH AC

Mnemonic Name:

OSC

Octal Code:

640001

Time:

1 .325 fJS

Operation:

The contents of the AC are inclusively ORed with the 6-bit
contents of the step counter (SC) on a bit-by-bit basis. The
result is left in AC12-17. If corresponding SC and AC bits
are in the binary 1 state, the AC bit is set to 1. The previous
contents of the AC are lost. The contents of the SC are unchanged.

Symbolic:

SC V AC -+AC

INCLUSIVE OR MQ WITH AC

6400021
Mnemonic Name:

OMQ

Octal Code:

640002

Time:

1 .325 fJS

Operation:

The contents of the MQ are inclusively ORed with the contents of the AC on a bit-by-bit basis. The result is left in the
AC. If corresponding MQ and AC bits are in the binary 0
state, the AC bit is cleared to o. If either of the corresponding bits is in the binary 1 state, the AC bit is set to 1. The
previous contents of the AC are lost. The contents of the MQ
are unchanged.

Symbolic:

MQ V AC -AC

6-8

COMPLEMENT MQ

6400041
Mnemonic Name:

CMQ

Octal Code:

640004

Time:

1 .325 jJS

Operation:

Each bit of the MQ is set or cleared to the inverse of its current state. The previous contents of the MQ are lost.

Symbolic:

MQ .... MQ

LOAD AC FROM SC

Mnemonic Name:

LACS

Octal Code:

641001

Time:

1 .325 jJS

Operation:

This microcoded instruction clears each bit of the AC to 0 and
then enters the contents of the SC in AC 12-17' The previous
contents of the AC are lost. The contents of the SC are unchanged.

Symbolic:

SC .... AC

6-9

LOAD AC FROM MQ

ILACQ
Mnemonic Name:

LACQ

Octal Code:

641002

Time:

1 .325 !JS

Operation:

This microcoded instruction clears each bit of the AC to 0 and
then enters the contents of the MQ in the AC. The previous
contents of the AC are lost. The contents of the MQ are unchanged.

Symbolic:

MQ -AC

LOAD AC WITH ABSOLUTE VALUE TO AC

6440001

:< : :< : :< : :< : :< : :<

Mnemonic Name:

ABS

Octal Code:

644000

Time:

1 .325 !JS

Operation:

A microcoded instruction which complements the contents of
the AC (lis complement notation), if the content of AC O is 1.

Symbolic:

If AC

= 1, AC -AC

6-10

CLEAR MQ

Mnemonic Name:

CLQ

Octal Code:

650000

Time:

1 .325 jJS

Operation:

Each bit of the MQ is cleared to O. The previous contents
of the MQ are lost.

Symbolic:

o -MQ

LOAD MQ

Mnemonic Name:

LMQ

Octal Code:

652000

Time:

1 .325 jJS

Operation:

A microcoded instruction which clears each bit of the MQ to 0
and then enters the contents of the AC in the MQ. The previous
contents of the MQ are lost. The contents of the AC are unchanged.

Symbolic:

AC -MQ

6-11

GET SIGN AND MAGNITUDE OF AC

Mnemonic Name:

GSM

Octal Code:

664000

Time:

1 .325 jJS

Operation:

A micrododed instruction which enters the contents of the ACO
in the I ink and then complements the contents of the AC (lIs
complement notation), if ACO is a 1. The previous content of
th eli n k is los t.

Symbolic:

ACo -L
If ACO = 1 , AC - AC

6-12

6.1.2 EAE Shifting Instructions
NORMALIZE

Mnemonic Name:

NORM

Octal Code:

640444

Time:

2 .915 + O. 133 (n-l) * ~

Operation:

The contents of the AC and the MQ are shifted left (i .e.,
leading zeros are shifted out) with the AC and MQ functioning as a serial 36-bit register until the content of the ACO
does not agree with the con'tent of AC 1, i. e., the bits
differ in their binary states, or the contents of the step
counter reaches zero.
This 6-bit counter is initial ized to the 2's complement of
448 (3610 steps). The contents of the six low order bits of
the NORM instruction word specify the step count. For
each sh ift step, the contents of MQ O enter AC 17 and the
contents shifted out of ACO are lost. The content of the
link, usually initialized to zero, enters MQ17 to replace
the contents of vacated bits. If shifting halts because
ACO does not equal AC1, the contents of the step counter
reflect the number of steps executed to reach the condition.
The counter's contents (2's complement of the step count
plus the steps executed) are accessible through use of the
OSC or LACS instruction.
When not in user mode, or when the memory protect option is not
installed, two free instructions follow the execution of the NORM
instruction. A PI or API break cannot occur until the second instruction following the NORM instruction is compl eted.

Graphic:

17
ACCUMULATOR

17
MUL TIPLIER
QUOTIENT REGISTER

} - STOP SH I FTS
SC=O

~I~
15-0194

*This quantity is also 0 for n=O.
6-13

NORMALIZE, SIGNED

Mnemonic Name:

NORMS

Octal Code:

660444

Time:

2 .915 + O. 133 (n-l) * fJS

Operation:

The contents of AC O enter the I ink. Then, the contents of the
AC and the MQ are shifted left (i .e., leading zeros are shifted
out) with the AC and MQ functioning as a serial 36-bit register
unti I the contents of the AC O do not agree with the contents of
AC 1, i. e., the bits differ in their binary states, or the contents
of the step counter reaches zero.
This counter is initialized to the 2 1s complement of 448 (3610
steps). The contents of the six low order bits of the NORMS
instruction word specify the step count. For each shift step,
the content of MQO enters AC17 and the contents shifted out
of ACO are lost. The content of the link enters MQ17 to replace the contents of vacated bits. If shifting halts because
ACO does not equa I AC 1, the contents of the step counter reflect the number of steps executed to reach the condition.
The counter's contents (2 1s complement of the step count plus
the steps executed) are accessible through use of the OSC or
LACS instruction.
When not in user mode, or when the memory protect option is not
installed, two free instructions follow the execution of the NORMS
instruction. A PI or API break cannot occur unti I the second instruction following the NORMS instruction is completed.

Graphic:

AC O

Setup

LINK

Execution

ACCUMULATOR

SC=O

~STOP

MULTIPLIER
QUOTIENT REGISTER

SHIFTS

15-0195

*This quantity is 0 for n=O.
6-14

Programming Note
The EAE instruction set does not provide a convenient way
to restore the contents of the step counter. To obviate the
need to do so, the PDP-15 is designed to inhibit program
or automatic priority interrupts occurring for two instructions following the NORM or NORMS (normal ize, signed)
instruction. These two instructions are norma Ily a DAC followed by a LACS which saves the contents of the AC, then
puts the contents of the step counter in the AC. Thus, if
interrupt-accessed subroutines make use of the EAE, the AC
and MQ are the only registers which must be preserved during the interrupt, then restored in the EAE at the complet i on of the interrupt serv ice.

LONG RIGHT S'HIFT

Mnemonic Name:

LRS n

Octal Code:

6405XX +n

Time:
Operation:

2 .915 + O. 133 (n-l) !JS
The AC and MQ function as a 36-bit register to permit serial
shifting of their contents "n" bit positions to the right, "n"
being specified by the contents of the six low order bits of the
instruction word. Shifting halts when the contents of the step
counter, init~alized to the 2 1s complement of lin II , reach zero.
For each shift step, the contents of AC17 enter MQO and the
con tents sh ifted out of MQ 17 are lost. The contents of the Ii nk,
usually initial ized to zero, remains unchanged and enters ACO
at each step to replace the contents of vacated bits.

Graphic:

17
ACCUMULATOR

17
MUL TIPLIER
QUOTIENT REG ISTER

LOST
15-0196

tThis quantity is also 0 for n = O.

6-15

LONG RIGHT SHIFT, SIGNED

6605XX

Mnemonic Name:

LRSS n

Octal Code:

6605XX +n

Time:

2.915 + O. 133 (n-l) t f.IS

Operation:

The content of AC O is entered in the link. Then, the AC and
the MQ function as a 36-bit register to permit serial shifting
of their contents lin II bit positions to the right, lin II being
specified by the contents of the six low order bits of the instruction. Shifting halts when the contents of the step counter,
initialized to the 2 1s complement of IInll, reach zero. For each
shift step, the contents of AC 17 enter MQO and the contents
shifted out of MQ17 are lost. The content of the link remain
unchanged and enters ACO at each step to replace the contents
of vacated bits.

Graphic:
Setup
ACO

Execution

LINK

17
ACCUMULATOR

17
MULTIPLIER
QUOTIENT REGISTER

LOST
15 -0197

tThis quantity is also 0 for n = O.

6-16

LONG LEFT SHIFT

LLS n

Mnemonic Name:

LLS n

Octal Code:

6406XX +n

Time:

2 .915 + O. 133 (n-l) t iJS

Operation:

The AC and the MQ function as a 36-bit register to permit serial
shifting of their contents "n" bit positions to the left, "n" being
specified by the contents of the six low order bits of the instruction word. Shifting halts when the contents of the step counter
initial ized to the 2's complement of lin II , reach zero. For each
shift step, the contents of MQO enter AC17 and the contents
shifted out of ACO are lost. The content of the link, usually initialized to zero, remains unchanged and enters MQ17 at each
step to replace the contents of vacated bits.

Graphic:

o
LOST

17
MULTIPLIER
QUOTIENT REGISTER

ACCUMULATOR

15-0198

t This quantity is also 0 for n = O.

6-17

LONG LEFT SHIFT, SIGNED

6606XX

I
Mnemonic Name:

LLSS n

Octal Code:

6606XX +n

Time:

2 .915 + O. 133 (n-l) t fJS

Operation:

The content of AC is entered in the I ink. The AC and MQ
function as a serial 36-bit register to permit serial shifting to
their contents lin II bit positions to the left, IIn" being specified
by the contents of the six low order bits of the instruction word.
Shifting halts when the contents of the step counter, initial ized
to the 2 1s complement of "n", reach zero. For each shift step,
the contents of MQO enter AC17 and the contents shifted out
of ACO are lost. The content of the link remains unchanged
and enters MQ17 at each step to replace the contents of vacated bits.

Graphic:
Setup
ACo

H I
LINK

Execution
LOST

17
MUL TIPLIER
QUOTIENT REGISTER

ACCUMULATOR

15-0199

t This quantity is also 0 for n = O.

6-18

ACCUMULATOR LEFT SHIFT

Mnemonic Name:

ALS n

Octal Code:

6407XX +n

Time:

2 .915 + O. 133 (n-l) t jJS

Operation:

The contents of the AC are shifted IIn ll bit positions to the left,
IIn ll being specified by the contents of the six low order bits of
the instruction word. Shifting halts when the contents of the
step counter, initial ized to the 2 1s complement of lin II, reach
zero. For each shift step, "the content of the I ink, usually initialized to zero, enters AC 17 to replace the contents of vacated
bits. The contents shifted out of ACO are lost.

Graphic:
LOST

...-1. . __

A_CC_U_M_U_L_A_TO_R_---Ir-fLIN K

15-0200

ACCUMULATOR LEFT SHIFT, SIGNED

6607XX I

<: :< : :<: :<: >: : :<I

Mnemonic Name:

ALSS n

Octal Code:

6607XX +n

Time:

2.915 + O. 133 (n-l) t jJS

Operation:

The content of ACO enters the link. Then, the contents of the
AC are shifted IIn ll bit positions to the left, IIn ll being specified
by the contents of the six low order bits of the instruction word.
Shifting halts when the contents of the step counter, initial ized
to the 2 1s complement of IInlf, reach zero. For each shift step,
the content of the link remains unchanged and enters AC17 to replace the contents of vacated bits. The contents sh if ted out of
ACO are lost.

Graphic

ACo

Setup
Ex ec uti on

LOST

Hr--

.-jL...__

- N-K---L,

A_CC_U_M_U_L_A_T_O_R_......

LI NK
15-0201

tThis quantity is also 0 for n = O.
6-19

AlSSn

6. 1.3 EAE Arithmeti c Instructions
MUL TIPLY, UNSIGNED

6531221
Mnemonic Name:

MUL

Octal Code:

653122

Time:

7.420 I..IS

Operation:

Multiply the contents of memory register Y (the multiplicand)
by the contents of the MQ (the multipl ier), and place the resulting 36-bit product in the AC and the MQ with the more significant half appearing in the AC. The address of Y is taken to
be sequential to the address of the MUL instruction word. Prior
to this instruction, the contents of the link must be zero and the
multiplier must be entered in the AC. During the set-up phase
of MUL I the multipl ier is transferred to the MQ, the AC is
cleared to zero, and the step counter is initialized to the 2 1s
complement of 228 (1810 steps); the six low order bits of the
instruction word specify the step count. The arithmetic phase,
executed as multiplication of one unsigned quantity by another
(18 bits, binary point of no consequence), halts when the step
counter counts up to zero. The content of the I ink remains zero.
The contents of Yare unchanged. The program resumes as the
next instruction (memory register Y + 1).

Symbolic:

o -SC
Y • MQ -(AC, MQ)
o -L
PC+2 - PC

Data Structure:

C=A·B

Pre-execution:

Post execution:

AC
A
0

xxxx

B
17

AC,MQ

[QJ

6-20

INSTRUCTION SEQUENCE:
Register

Contents

Y-2
Y-l

LAC Multipl ier
MUL
Multipl icand
Next Instruction

Y
Y+l

MULTIPLY, SIGNED

6571221

>: : >: : :<: ;,: : :< : >: I

MULS

Mnemonic Name:

MULS

Octal Code:

657122

Time:

7. 420 l-'s

Operation:

Multiply the contents of memory register Y (the multiplicand)
by the contents of the MQ (the multiplier), and place the signed
product in the AC and MQ with the sign notation and more significant portion in the AC. Bits ACO and AC1 each receive the
sign of the product; the remaining AC and MQ bits represent the
magnitude of the product in lis complement form. The address of
Y is taken to be sequential to the address of the MULS instruction
word. The contents of the Yare taken to be the absolute value
of the mul tipl icand; the contents of the I ink are taken to be the
original sign of the multipl icand (MULS assume previous execution of an EAE GSM instruction, q.v.). Just prior to this MULS
instruction, the multipl ier must be entered in the AC. During the
setup phase of the MULS instruction, the multiplier is transferred
to the MQ and lis complemented if negative, the AC is cleared
to zero, and the step counter is initialized to the 2 1 s complement
of 228 (1810 steps); the six low order bits of the MULS instruction
word specify the step count. The arithmetic phase, executed as
multiplication of one signed quantity by another (sign bit plus 17
magnitude bits, binary point position of no consequence), halts
when the step counter counts up to zero. The I ink is cleared to
zero. The contents of Yare unchanged. The program resumes at
the next instruction (memory register Y + 1).

Symbolic:

o . . SC
Y • MQ .... (AC,MQ)
o .. L
PC+2 .... PC

Data Strucf'ure:

C=A·B

6-21

Pre-execution:
L

I S

Y
0

xxxx
17

*Original sign of B.
Post execution:
AC,MQ

I I
S

S = L ¥- Sign A :

INSTRUCTION SEQUENCE:
Register

Contents

Y-5
Y-4

LAC Multiplicand
GSM (take absolute
value and save sign in
link)
DAC Y
LAC Multiplier
MULS
Multiplicand (absolute
value)
Next Instruction

Y-3
Y-2
Y-1
Y
Y+1

6-22

DIVIDE, UNSIGNED

DIV

Mnemonic Name:

DIV

Octal Code:

640323

Time:

7.685 ~

Operation:

Divide the contents of the AC and the MQ (an unsigned 36-bit
dividend) by the contents of memory register Y (the divisor).
The resulting quotient appears in the MQ; the remainder is in the
AC. The address of Y is taken to be sequential to the address of
the DIV instruction word. Prior to this, the contents of the I ink
must be zero, and the dividend must be entered in the AC and MQ
(LAC least significant half). If the divisor is not greater than the
AC portion of the dividend, divide overflow occurs (magnitude of
quotient exceeds the 18-bit capacity of the MQ), and the link is
set to one to signal the overflow condition; data in the AC and
the MQ are of no value. A val id division halts when the step
counter, initialized to the 2 1 s complement of 238 (1910 steps),
counts up to zero (the six low order bits of the DIV instruction
word specify the step count). The contents of the Yare unchanged. The program resumes at the next instruction (memory
reg ister Y + 1).

Symbolic:

If Y ::;, AC, 1 -L (divide overflow)
If Y >AC,

o -SC
(AC,MQ)/Y -MQ (quotient), AC (remainder)

o -L
PC+2 -+ PC
Data Structure:

A = BQ + r

Pre-execution:
L

0
Post execution:

AC,MQ

(no overflow)
L

c=J

6-23

~17
0

Y
B
0

(overflow)
L

AC,MQ

meaningless

INSTRUCTION SEQUENCE:
Register

Contents

Y-4

LAC Dividend (least
significant half)
LMQ
LAC Dividend (most
significant half)
DIV
Divisor
Next instruction

Y-3
Y-2
Y-1
Y
Y+1

6-24

DIVIDE, SIGNED

Mnemonic Name:

DIVS

Octal Code:

644323

Time:

7.685 I-lS

Operation:

Divide the contents of the AC and MQ (a 36-bit signed dividend
with the sign in bits ACO and AC1 and the remaining 34 bits devoted to magnitude) by the contents of memory register Y (the
divisor). The resulting quotient appears in the MQ with the algebraically determined sign in bit MQl-17. The remainder is in
the AC with bit ACO containing the sign of the dividend and bits
ACl-17 containing the magnitude (l's complement). The address
of Y is taken to be sequential to the address of the DIVS instruction word. The contents of Yare taken to be the absolute value
of the divisor; the contents of the link are taken to be the original
sign of the divisor (DIVS assumes previous execution of an EAE
GSM instruction, q.v.). Prior to this DIVS instruction, the dividend must be entered in the AC and MQ (LAC of lease significant
half, LMQ, and LAC of most significant half). The MQ portion
of a negative dividend is 1s complement prior to the division. If
the divisor is not greater than the AC porti on of the dividend,
divide overflow occurs (magnitude of the quotient exceeds the
17-bit pi us sign capacity of the MQ), and the I ink is set to one
to signal the overflow condition; data in the AC and the MQ are
of no value. A val id division halts when the step counter, initialized to the 2's complement of 238 (1910 steps), counts up to
zero (the six low order bits of the DIVS instruction word specify
the step count). The content of the link is cleared to zero. The
contents of Yare unchanged. The program resumes at the next
instruction (memory register Y + 1).

Symbolic:

If Y S I AC
1 -+L (divide overflow)
If Y > I AC I,
o .. SC
(AC ,MQ)/Y .. MA (quotient) f AC (remainder)
o .. L
PC+2 .. PC

Data Structure:

I AI = B Q+r

6-25

Pre-execution:

AC,MQ

I sl1 S 2I A 35I

10 I
o 1

I BI I

*Original sign of B

Post execution:
(no overflow)

~
(overflow)

I S 1I

I 1I

(S=Sign A)

I! j I I J
IB

(S=Sign A ¥ L)

AC,MQ

Mean i ng less

I0 I I I
B

INSTRUCTION SEQUENCE:
Register

Contents

Y-7
Y-6
Y-5

LAC Divisor
GSM
DAC Divisor in Y
LAC Dividend (least
significant half)
LMQ
LAC Dividend (most
significant half)
DIVS
Divisor (absolute value)
Next Instruction

Y-4
Y-3
Y-2
Y-1
Y
Y+1

6-26

INTEGER DIVIDE, SIGNED

IIDIVS
Mnemonic Name:

IDIVS

Octal Code:

657323

Time:

7.685 ~

Operation:

Divide the contents of the AC and the MQ (AC is zero, MQ
contains a signed integer dividend) by the contents of memory
register Y (the divisor). The resulting quotient appears in the'
MQ with the algebraically determined sign in bit MQO and the
magnitude (lis complement) in bitsMQl_17' The remainder is
in the AC with bit ACO containing the sign of the dividend and
bits AC l - 17 containing the magnitude (lIs complement). The
address of Y is taken to be sequential to the address of the IDIVS
instruction word. The contents of Yare taken to be the absolute value of the divisor; the contents of the link are taken to be
the original sign of the divisor (IDIVS assumes previous execution of an EAE GSM instruction, q.v.). Prior to this IDIVS instruction, the dividend must be entered in the AC (the setup
phase of IDIVS transfers the dividend to the MQ, clears the AC,
and lis complements the MQ if the dividend is negative).
Divide overflow occurs only if division by zero is attempted;
i.e., the quotientls magnitude will not exceed the 17-bit plus sign
capacity of the MQ. The division halts when the step counter,
initialized to the 2 1s complement of 238 (l9 10 steps), counts up
to zero (the six low order bits of the IDIVS instruction word
specify the step count). The contents of the I ink are cleared to
zero. The contents of Yare unchanged. The program resumes
at the next instruction (memory register Y + 1).

Symbolic:

o ---SC
MQjY -MQ (quotient), AC (remainder)

o -L

PC+2 --- PC
Data Structure:

A = B Q+r

Pre-execution:

~ o

AC, MQ
A

[0 I I BI

I xxx

17 1

*Original sign of B

6-27

Post execution:

(s=Sign A)

(s=L ¥ Sign A)

If Y=O (overflow)
L

AC,MQ
meaningless

INSTRUCTION SEQUENCE:
Register

Contents

Y-5
Y-4
Y-3

LAC Divisor
GSM
DAC Divisor {absolute
value} in Y
LAC Dividend
IDIVS
Divisor (absolute value)
Next Instructi on

Y-2
Y-l
Y
Y-l

6-28

INTEGER DIVIDE, UNSIGNED

Mnemonic Name:

IDIV

Octal Code:

653323

Time:

7.685 fJS

Operation:

Divide the contents of the AC and the MQ (AC is zero, MQ contains a 18-bit integer dividend) by the contents of memory register Y (divisor). The resulting quotient appears in the MQ; the
remainder is in the AC. The address of Y is taken to be sequential
to the address of the IDIV instruction word. Prior to this instruction, the contents of the I ink must be zero, and the dividend must
be entered in the AC (the setup phase of IDIV transfers the dividend
to the MQ and clears the AC). Division overflow occurs only if
division by zero is attempted, i.e., the quotient's magnitude will
not exceed the 17-bit plus sign capacity of the MQ. The division
halts when the step counter, initialized to the 2's complement of
230 (1910 steps), counts up to zero (the six low order bits of the
IDIV instruction word specify the step count). The content of the
I ink is cleared to zero. The contents of Yare unchanged. The
program resumes at the next instruction (memory register Y+1).

Symbolic:

o -SC
MQjY - MQ (quotient), AC (remainder)

o -L

PC+2 - PC
Data Structure:
Pre-execution:

Post execution:

A = BQ+r

XXX

AC
0

[
17

B
17

If Y=O (overflow)

AC,MQ

meaningless

6-29

INSTRUCTION SEQUENCE:
Register

Contents

Y-2
Y-l
Y
Y+l

LAC Dividend
IDIV
Divisor
Next Instruction

FRACTION DIVIDE, UNSIGNED

6503231

Mnemonic Name:

FRDIV

Octal Code:

650323

Time:

7.685 !..IS

Operation:

Divide the contents of the AC and the MQ (AC contains an
18-bit fractional dividend, MQ is zeroed at stepup) by the
contents of memory register Y (the divisor). The binary point
is assumed at the left of ACO. The quotient appears in the MQ;
the remainder is in the AC. The address of Y is taken to be
sequential to the address of the FRDIV instruction word. Prior
to this instruction, the contents of the I ink must be zero, and
the dividend must be entered in the AC (the set-up phase of
FRDIV clears the MQ). If the divisor is not greater than the
dividend, divide overflow occurs (magnitude of quotient exceeds
the 18-bit capacity of the MQ), and the link is set to one to
signal the overflow condition; data in the AC and the MQ are
of no value. A valid division halts when the step counter,
initialized to 238 (19 10 steps), counts up to zero (the six low
order bits of the FRDIV instruction word specify the step count).
The contents of the link remain zero. The contents of Yare
unchanged. The program assumes at the next instruction (memory
register Y + 1).

Symbolic:

If Y .::; I AC I, 1 ..... L {divide overflow}
If Y >AC ,
o . . . SC
AC/Y -MQ (quotient), AC {remainder}
o -L
PC+2 -PC

Data Structure:

A = BQ+r

6-30

Pre-execution:
L

xxx

0
Post execution:

(no overflow)

l 17

(overflow)

[i]

AC,MQ

mean i ng less

INSTRUCTION SEQUENCE:
Register

Contents

Y-2
Y-1
Y
Y+1

LAC Dividend
FRDIV
Divisor
Next Instruction

6-31

FRACTION DIVIDE, SIGNED

Mnemonic Name:

FRDIVS

Octal Code:

654323

Time:

7.685 fJS

Operation:

Divide the contents of the AC and the MQ (AC contains a 18-bit
signed dividend with the sign in bits ACO and ACl and the remaining 16 bits devoted to magnitude, MQ is zeroed at setup) by the
contents of memory register Y (the divisor). The binary point is
assumed between ACO and AC1. The resulting quotient appears
in the MQ with the algebraically determined sign in bit MQO and
the magnitude (lIs complement) in bits MQl-17. The remainder
is in the AC with bit ACO containing the original sign of the dividend and bits ACl-17 containing the magnitude (lIs complement).
The address of Y is taken to be sequential to the address of the
FRDIVS instruction word. The contents of Yare taken to be the
absolute value of the divisor; the contents of the link are taken to
be the origi nal sign of the divisor (FRDIVS assumes previous execution of an EAE GSM instruction, q.v.). Prior to this FRDIVS
instruction, the dividend must be entered in the AC (the setup
phase of FRDIVS clears the MQ and lis complements the dividend,
if negative, prior to the division). If the divisor is not greater
than the dividend, divide overflow occurs (magnitude of the quotient exceeds the 18-bit capacity of the MQ) and the link is set
to one to signal the overflow condition. Data in the AC and the
MQ are of no val ue. A val id division halts when the step counter,
initial ized to the 2 1s complement of 238 (1910 steps), counts up to
zero (the six low order bits of the FRDIVS instruction word specify
the step count). The contents of the link are cleared to zero.
The contents of Yare unchanged. The program resumes at the
next instruction (memory register Y + 1).

Symbolic:

If Y S: AC, 1 - L (divide overflow)
If Y >AC,
o -SC
AC/Y -MQ (quotient), AC (remainder)
o -L
PC+2 - PC

Data Structure:

A = BQ+r

6-32

Pre~execution:

sis I A

XOX

o
35

*original sign of B
Post Execution:

(no overflow)
AC

I 71
oI s 1
(s=Sign A)
(overflow)
AC,MQ

Y
B

mean i ng less

o 1

INSTRUCTION SEQUENCE:
Register

Contents

Y-5

LAC Divisor
GSM
DAC Divisor (absolute
value) in Y
LAC Dividend
FRDIVS
Divisor (absolute value)
Next Instruction

Y-4
Y-3
Y-2
Y-l
Y
Y+l

6.2 KM15 MEMORY PROTECT
The KM15 provides the PDP-15 with the capability of running in a background/foreground environment.
This capability is accomplished through a programmable boundary register, which establishes the boundary between protected and unprotected areas of core memory. There is also a specifi c set of instructions termed illegal, because they would interfere with background/foreground operation.
A PDP-15, equipped with a KM15 Memory Protect option, has two modes of operation: User Mode
(KM 15 enabled) and Monitor Mode (KM 15 disabled).
When operating in User Mode, the KM15 monitors addresses and instructions to determine their legality
and prevent execution of anything illegal. When operating in Monitor Mode, operation is identical
to normal PDP'" 15 operation. When in User Mode, upon detection of a violation, a flag is raised,
User Mode is turned off, and a pseudo program interrupt is caused.

6-33

When enabled, the option traps the following:
OAS
lOT
HLT
XCT of XCT
References be low the boundary
References to nonexistent memory
User Mode is enabled by either placing the Protect switch on the console in the 11111 position and
depressing the Start key, or by issuing the lOT, MPEU.
User Mode is disabled in the following ways:

I/o Reset Key
Detection of ,a violation
CAL Instruction
Program Interrupt
API Interrupt
The state of the Protect Mode (a 11111 for User Mode) is stored in bit 2 of the storage word by those
operations that save the state of the machine (CAL, JMS, PI, and TRAP). For a violation, the Stored
Address is one more than the location containing the violation instruction, except for a JMP to a protected area. In this case, the stored PC equals the Protected Address.
Not all memory reference instructions are prevented from addressing below the boundary; any IIread ll
instruction with the exception of JMP and ISZ is permitted to address below the boundary, because a
read instruction cannot modify core. All write instructions and JMP and ISZ are prevented from addressing below the boundary.
A nonexistent memory violation is one in which a reference is made to a memory location which does
not exist in that particular system. When running in User Mode, such a violation causes the Protect
violati on flag and the nonexistent memory flag to get set and the computer proceeds through the trap.
When running in Monitor Mode, a reference to a nonexistent memory causes the nonexistent memory
flag to get set and the computer hangs up waiting for memory to respond. Because a memory with that
address is not present, the computer remains hung until manually reset by depressing Stop and Reset at
the same time.
All violations trap to address 20 where the state of the machine is saved. The instruction in 21 is then
executed.

However, if the program interrupt faci! ity is enabled prior to the trap, the trap goes to ad-

dress 0 where the state of the machine is saved and location 11111 is executed. The program interrupt
faci lity is disabled as when servicing any program interrupt.
Some special cases of importance are explained as follows.

6-34

The API, if present, is raised to Level 3.

CAL Instruction
When in User Mode and the CAL is executed, User Mode is disabled (Monitor Mode envoked). The
CAL goes to location 20 as usual and saves the state of the machine.

No violation occurs.

Program Interrupt
When a program interrupt occurs, User Mode is disabled. The interrupt goes to location 0 and saves
the state of the machine.

No violation occurs.

Automatic Priority Interrupt
An API break causes Monitor Mode to be entered. The instruction in the address specified by the I/o
device is executed. No violation occurs. The instruction in this address is usually a JMS, JMS I, or
a CAL to the device handler. The device handler entry receives the state of the machine.
Data Channel
Data channel operations do not cause violations, even though they can reference addresses below the
boundary. They do, however, produce a nonexistent memory violation, if nonexistent memory is
referenced.
Real-Time Clock
The real-time clock increments address 7, which is below the boundary. No violation occurs.

How-

ever, attempts to reinitialize address 7 must be done in Monitor Mode.
Auto Increment Register
The auto increment register can be used while in User Mode.

No violation occurs, unless the address

to which the register points is below the boundary., Reinitialization of these registers must be done in
Monitor Mode.
DBR and RES Instructions
The DBR and RES instructions can be used to return to User Mode from Monitor Mode. This is accomplished by issuing DBR or RES and then a JMP I to the subroutine entry. If bit 2 is a "1" in the indirect
location, User Mode is restored. The instruction set for the KM15 option is listed in Table 6-3.

NORM Instruction
In User Mode, the execution of a NORM instruction wi II not cause two free instructions following the
NORM.

6-35

Table 6-3
KM 15 Instruction Set

Mnemonic

Octal Code

Operation Executed

MPSNE

701741

Skip on Nonexistent Memory flag

MPSK

701701

Skip on Protect Violation flag

MPEU

701742

Enter User Mode. Actual entry
occurs after the start of the next
instruction.

MPCV

701702

Clear Protect Violation flag

MPCNE

701744

Clear Nonexistent Memory flag

MPLD

701704

Load the boundary register with
the contents of AC 01-09.

The following are sample programs which demonstrate how to program the KM 15 option:

1•

How to enter User Mode.
.LOC

100
LAC X
MPLD
MPEU
JMP * Y

/x=value to be set into boundary reg.
/Ioad boundary reg.
/ enter User Mode
/Y contains starting address of User's
/program. Should be greater than
/value in X.

What happens when violating instruction occurs in program •
• LOC

500
LAC Z

/Z is above the boundary

lAC
DAC 200
.LOC
.LOC

20
100503

/200 is below the boundary
/DAC does not get executed
/User Mode and address + 1 saved

21
MPSNE
SKP
JMP NEXMER
MPSK
SKP
JMP PVER

/Check NEXM flag
/No
/Yes, Handle it
/Check PV flag
/No
/Yes, Handle it

6-36

How to get back into program after interrupt •
• LOC

o
100510
JMP PISERV

.LOC

150
DBR or RES
JMP * 0

/Bit 2=11111 User Mode was on.

/End of PI service routine
/User Mode wi II be restored.

6.3 KTl5 MEMORY PROTECT AND RELOCATE
With the KTl5, the PDP-15 has the capabil ities of a programmable core allocation register or upper
boundary register for specifying protected areas of core, a programmable relocation register for specifying a base address to which all addresses from the CPU are added producing a relocated address and
an illegal instruction set. The KTl5 also provides a detection network for detecting addressing of
nonexistent memory.
A PDP-15, equipped with a KTl5 Memory Protect and Relocate option, has two modes of operation:
User Mode (KTl5 enabled) and Monitor Mode (KTl5 disabled). In Monitor Mode, the relocation and
protect hardware are disabled and the machine functions as it' would without a KTl5. A program running in Monitor Mode addresses real locations within the system. In User Mode, the relocation and
protect hardware is enabled. The machine is programmed as though the user had the machine all to
himself. His memory begins from location 0 and goes up to and includes the last 256

word page
10
specified by the core allocation register (upper boundary register). In the real machine, the program
is located from the contents of the relocation register up. In User Mode, addresses and instructions
are checked for their legal ity. Anything illegal is trapped (hardware activated JMS).
Trap is a condition where the execution of an illegal instruction is inhibited and the systems monitor
takes control.
The definition of a real machinc: in reference to the memory and relocate option is a machine having
an absolute addressable bank 0 memory. While a virtual machine is defined as having a relative bank 0
addressing capacity.
The following instructions are trapped in User Mode.
OAS

lOT
HLT
XCT of XCT
References above the boundary
References to nonexistent memory

6-37

User Mode is enabled by either placing the Protect switch on the console in the 11111 position and
depressing the Start key, or by issuing the lOT MPEU.
User Mode is disabled in the following ways:
I/O Reset Key
Detection of a violation
CAL instruction
Program Interrupt
API Interrupt
The state of User Mode is stored in bit 2 of the storage word (a 11111 for User Mode, a 110 11 for Monitor
Mode) by those operations that save the state of the machine (CAL, JMS, PI, and TRAP).
A nonexistent memory violation is one in which a reference is made to a memory location which does
not exist in that particular system. When running in User Mode, such a violation causes the protect
violation flag and the nonexistent memory flag to get set; the computer proceeds through the trap.
When running in Monitor Mode, a reference to a nonexistent memory causes a nonexistent memory
flag to set, and the computer hangs up waiting for memory to respond. Because a memory with that
address is not present, the computer remains hung until manua lIy reset by depressing Stop and Reset
at the same time.
All violations trap to address 20 in the real machine where the state of the machine is saved. The
instruction in real 21 is then executed. However, if the program interrupt facility is enabled prior to
the trap, the trap goes to real address 0 where the state of the machine is saved and real location 11111
is executed. The program interrupt facility is disabled, as it is when servicing any program interrupt.
The API, if present, is raised to Level 3.
Some special cases are defined below.
CAL Instructi on
When in User Mode with the CAL instruction given, the User Mode is disabled (Monitor Mode envoked).
The CAL goes to location 20 in the real machine (not the relocated machine) and saves the state of the
machine. The PC saved is the virtual PC. The virtual PC is equivalent to the PC, if the program were
operating from location 0 up.
Program Interrupt
When a program interrupt occurs, the User Mode is disabled and the interrupt goes to real location O.
The state of the machine is saved in real 0 and real 1 is executed.

6-38

Automatic Priority Interrupt
When in User Mode, an API break causes Monitor Mode to be entered, and an instruction in the real
machine address, specified by the I/o device, is executed. This instruction is usually a JMS, JMS I,
or a CAL to the device handler. The device handler runs in Monitor Mode. The device handler entry
receives the state of the machine.
Data Channel
Data channel operations are never relocated.
Real-Time Clock
The real-time clock always increments real location 7. Attempts to reference the contents of location
7 in the real machine must be done in Monitor Mode.
Auto Increment Register
Each user has a complete set of auto increment registers located in locations 10 to 17 of the user's virtual machine. In addition, 10 to 17 in the real machine may be used in Monitor Mode •
. DBR and RES Instructions
The DBR and RES instructions may be used when returning from Monitor Mode. The protect bit in the
indirect location causes relocation if it is a 11111. Since CAL, PI, API, JMS, and TRAP save the virtual PC, returns are sent to the correct location in memory. The virtual PC is restored and User Mode
is envoked.
The instruction set for the KTl5 is listed in Table 6-4.

Table 6-4
KTl5 Instruction Set

Mnemonic

Octal Code

Operati on Executed

MPSK

701701

Skip on Protect Violation flag

MPCV

701702

Clear Protect Violation flag

MPLD

701704

Load core allocation register
(boundary register) with contents of
AC or 01-09.

MPSNE

701741

Skip on Nonexistent Memory flag

MPEU

701742

Enter User Mode

6-39

Table 6-4 (Cont)
KTl5 Instruction Set

Mnemonic

Octal Code

Operation Executed

MPCNE

701744

Clear Nonexistent Memory flag

MPLR

701724

Load relocation register with contents
of AC 01-09.

The core allocation register of boundary register specifies the amount of core available to the user.
An example of how to set the BR (boundary register) follows.
If the User is allotted 4K of core", the AC is loaded with bits 6, 7, 8, and 9. The lOT MPLD then
loads the BR with those bits. Because bits 10-17 are not included in the BR and therefore not checked,
addresses up to and including 7777 are legal. Address 10000, however causes a violation. Thus, the
user was allotted 4K of core. The user can be allotted as little as 256

10
to all zeros. Then, addresses 0 to 377 are legal; address 400 is illegal.

locations by setting the BR

A few simple programming examples are given below.
1.

Sequence for entering User Mode.
.LOC

100
LAC X
MPLD
LAC Y
MPLR
MPEU
JMP 0

Example 1

/X= 017400
/Set BR for 8K
/Y = 010000
/Set relocation register for base
/of 10000.
/Enter User Mode
/0 gets relocated to 10000

The user was alloted 8K of core and his storage area started
in real address 10000. If the actual starting address of the
user's program was an address other than 0, the JMP instruction should be modified to refl ect this.

What happens when violating instruction occurs in a program? (Operating under
Example 1 conditions.)
Relocated 200/ LAC * Z

/Z=020000

Rea I 20/ 100201

/User Mode and virtual
/address +1.

Real 21/

/Check NEXM flag
/No
/Yes, Handle it

MPSNE
SKP
JMP NEXMER

6-40

MPSK
SKP
JMP PVER
3.

/Check PV flag

/No
/Yes, Handle it

How to return after interrupt. (Operating under Example 1 conditions.)
Real 0/

100300
JMP PI SERV

/User Mode was on
/Go service interrupt

Real 150/ End of PI service
DBR or RES
JMP * 0

/User Mode will be restored.
/Return will go to 300 relocated.

6.4 MP15 MEMORY PARITY
The MP15 enables the PDP-15 to continuously check information being read from core memory, and to
determine whether information has been erroneously picked up or dropped. It does this by first monitoring all information as it is being sent to the memory for storage. If there are an even number of bits
in the data word, the MP15 control causes memory to write the parity bit, thus making the total number of bits odd. If there are an odd nu.mber of bits in the da'ta word, the MP15 control inhibits the
memory from writing the parity bit. Again, the word is stored with an odd number of bits. When information is read from core, the parity control checks to see that an odd number of bits are read. If
it finds an even number, then a parity error has occurred. The parity error flag can be used to cause
an API interrupt, a program interrupt, a skip request, or an immediate stop of the processor.
Table 6-5 contains the instruction set for the MP15.
The MP15 uses API channel address 53 and is on priority level O.
When using the read-in feature, the last instruction on the paper tape (which is executed by the
processor) will not be written into the next sequential memory location. That location, however, will
be loaded with data that may contain wrong parity. This location should be restored by the program
before an attempt is made to read from it. Otherwise, a parity error will occur.
Table 6-5
MP15 Instruction Set

Mnemonic

Octal Code

SPE

702701

Skip on Parity Error flag

ePE

702702

C Iear Par i ty Error fl ag

FWP

702704

Force wrong parity (maintenance only)

Operati on Executed

6-41

Mounted in the BB15 Peripheral Expander (slot A19) is a W714 switch card containing two microswitches.
The top switch is used in conjunction with the MP15. When the switch is placed in the "up" position,
a parity error causes an API interrupt, a program interrupt, or a skip request. With the switch in the
"down" position, a parity error causes the processor to halt.
When using the program interrupt facility, the SPE instruction must be included in the skip chain used
to determine the flag that causes the interrupt. When using the API facility, address 53 must contain
a JMS to a parity error service routine. In all cases, before returning to the main program, the parity
error flag must be cleared through use of CPE or CAF.

6.5 KF15 POWER FAIL OPTION
The Power Fail Option is designed to offer maximum protection to programs during power failure turn
off, and recovery of power after failure. The option enables the PDP-15 System to store active registers in memory before power diminishes to a point beyond which data will be lost. The computer can
be in one of three conditions when a power fai lure occurs: (l) the console lock has not been turned
on (manual function), (2) the console lock is on and the program interrupt facility (PI) is also enabled,
or (3) the console lock is on and the automatic priority interrupt fac iI ity is enabl ed •
Figures 6-7, 6-8, and 6-9 illustrate the power fail sequence.

6.6 KW15 REAL-TIME CLOCK OPTION
The real-time clock option gives the user a time reference capabil ity to use in control processing. The
real-time clock produces clock pulses at the rate of one every 16.7 ms for 60 Hz systems. When the
real-time clock is enabled by an lOT instruction (CLaN); the occurrence of each pulse initiates a
request for a break at the compl etion of the current instruction.
At the grant of the break, the contents of the clock counter register (memory location 00007) are
incremented by one. This memory location is program initialized to contain the 2's complement of the
desired number of clock pulses. Clock breaks continue to be requested until the memory location
00007 overflows (reaches the all zeros condition).
At this time, the CLOCK flag is set to initiate interruption of the program in progress. The CLOCK
flag is interfaced to the program interrupt control and to the API system. The real-time clock has
priority over the API and PI requests.

6-42

The following lOT instructions are, provided for use with the real-time clock.

Table 6-6
lOT Instructions for Real-Time Clock

Mnemonic

Octal Code

Function

CLON

700044

Clock on. This lOT instruction enables the realtime clock; the clock increments location 00007,
and the CLOCK flag is cleared.

CLOF

700004

Clock off. This lOT instruction disables the
real-time clock; the clock does not increment
location 00007, and the CLOCK flag is cleared.

CLSF

700001

Skip on CLOCK flag. The next instruction is
skipped if the CLOCK flag is set.

A number of sources can be used as the clock time source.
a.
b.

PDP-15 real-time clock (standard with option)
DEC positive logic clocks, both RC and crystal type.

r--_P_O_W_E_R_U_P_--1 CON SOLE LOC K
NOT ON

POWER DOWN

PROGRAM CONT.
UNTIL POWER
FAILURE
DETECTED

15-0185

Figure 6-7

Power Fail Up/Down Sequence

6-43

POWER UP

CONSOLE LOCK

POWER DOWN

r - - - - - - - - - - - t ON -

PI ENABLED

PROGRAM CONT.
UNTIL POWER
FAILURE
DETECTED

WHEN PWR LOW
IS DETECTED
A PI REQUEST
IS ISSUED
EXECUTE
LOCATION
ZERO
(JMS SUBROUTINE)

TIME

SX~E

2 MS
REGISTERS

SUBROUTINE
STORES ACTIVE
REG. IN CORE AND
PLACES JMP RESTART
ROUTINE IN LOC 0

POWER OFF

15-0186

Figure 6-8

Power Fai I Up/Down Sequence

6-44

POWER UP

CONSOLE LOCK

POWER DOWN

~----------~ON-

API ENABLED

PROGRAM CONT.
UNTIL POWER
FAILURE
DETECTED

WHEN PWR LOW
IS DETECTED AN
API REQUEST
I S ISSUED

POWER FAIL IS
ON THE HIGHEST
LEVELOFAPI
(LEVEL ZERO)

2 MS

POWER OFF

15-0187

Figure 6-9

Power Fail Up/Down Sequence

6-45

6.7 KA 15 AUTOMATIC PRIORITY INTERRUPT (API)
The API option extends the PDP-15 capabilities by providing priority servicing for as many as 28 I/o
devices, with minimum programming and maximum efficiency. The API priority structure enables high
data rate devices to interrupt the service routines of slower devices with a minimum of system "overhead. II With the API option, the device service routines can enter directly from hardware-generated
entry points, eliminating the need for time-consuming flag searches to identify the device that is
causing the interrupt.
The API option gives the PDP-15 System 32 unique channels, or entry points, for the device service
routines, and 8 levels of priority. The four higher levels are for fast access to service routines in
response to device-initiated service requests. Each of these levels can be multiplexed to handle up
to eight devices, assigned an equal priority level. The four lower levels are assigned to programinitiated software routines for transferring control to programs or subroutines on a priority basis. Four
of the 32 channels are reserved for these software levels.
Each device interfaced to the API option specifies (sends) its unique service routine entry point to the
processor when granted an API break by the processor. Core memory locations 408 through 778 are
assigned as these entry points I in PDP-15 System Software. JMS or JMS * instructions contained in
these locations provide linkage to the actual service routines.
Of the 28 hardware channels, three are assigned internally to the optional real-time clock, optional
power failure detection system, and optional memory parity. The API interface logic for these devices is contained in the BB15 option panel.
Each software level services one interrupt and .uses a single address (locations 408 to 43 ). The soft8
ware requests are initiated by a program issuing an ISA instruction with the appropriate AC bits set
(refer to Table 6-9).
The I/O interrupts permit the asynchronous operation of many devices, each at its proper priority level.
The software priority levels are used to establ ish a priority queue for the processing of real-time data
without inhibiting the hardware interrupts to service devices.
Each hardware API priority takes precedence over lower API priorities, program interrupts, and the
main program. The program segment of highest priority interrupts lower priority program segments
when activated. The DCH and RTC are above all these in priority.

6-46

6.7. 1 API Hardware
Figure 6-10 relates the activity of the automatic priority interrupt system from the initiation and
acceptance of the request, to the servic ing of the accepted request, and the debreak from the serviced priority level.

PRIORITY LEVEL ACCEPTANCE
....1 - - - - - - DEBREAK API - - -.....

PRIORITY STATE

5
~--------------------~
PRIORITY LEVEL 6

PRIORITY LEVEL 7

.....

REQUEST REGISTER
HARDWARE
REQUEST

SOFTWARE
REQUEST
15-0054

Figure 6-10

API System Simpl ifi ed Block Diagram

The request register contains eight levels; four levels are activated by the devices (hardware) on the
I/O bus, and four are activated under software supervision. The hardware requests are assigned the
highest priority and are demonstrated as requests 0, 1, 2, and 3. The software requests are initialed
by requests 4, 5, 6, and 7.
The priority level (PL) bars depict the priority level selected by the ISA instruction, or raised by the
API control when it has granted a request on that specific level. The PL bars indicate that any request equal to, or less than (in priority) the priority level selected, wi II not be accepted. At the end
of the subroutine currently being performed by an active request, a debreak and restore instruction is

6-47

issued to lower the priority to the next selected priority level. The ball, representing the priority
debreaking, wi II fall as long as there is no bar present (i .e., no priority level set). If a lower
priority level is set, the debreaking ceases at that level.
The API request register (RR) buffers inputs from the hardware interrupt on levels 0 through 3 and the
inputs from the monitors on levels 4 through 7. Up to eight interrupts can be attached to a single
level. If two or more of these make simultaneous interrupt requests, the interrupt closest to the processor on the I/O bus is given priority. An interrupt request sets a bit in the RR according to its preassigned priority level. When the scanner detects that bit, the API system signals the CPU to stop
execution at the completion of its current instruction. The API system then gates the I/O processor's
15 address lines, which contain the address of the interrupt's unique core location, into the CPU
memory output register. The CPU then requests a memory cycle and executes the instruction it fetched
from that location. During this operation, the program counter remains unchanged.

The API system

also sets a bit in the PL corresponding to the level of the interrupt. This prevents interrupts on the
same level or lower levels from interrupting the current interrupt. The scanner continues to sample
the higher levels so that higher priority devices can interrupt lower priority devices. At the completion of the interrupt subroutine, a debreak and restore (DBR) instruction must be issued to reset the bH
in the PL and in .the RR.
The API hardware ensures that simultaneous requests by multiple devices are handled in the proper
priority sequence. If interrupt requests occur at different priority levels, the highest priority requests
are serviced first.

Higher priority devices can interrupt lower priority devices. The entire API system

can be enabled or disabled with a single instruction; however, most devices provide facilities to connect and disconnect their flags from the interrupt separately. If the API system is disabled, the device automatically signals the program interrupt to obtain a response at that priority level.

6.7.2 API Instructions
The API logic adds six lOT instructions to the basic PDP-15 repertoire. Table 6-7 briefly describes
these instructions, and programming considerations for their use follow.

6-48

Table 6-7
API lOT Instructions

Mnemonic

Octal Code

DBK

703304

Debreak. Releases the highest currently active
priority level.

DBR

703344

Debreak and restore. Releases the highest currently active priority level and provides for restoration of the LINK, Bank Mode, and User Mode
status to the interrupt program at the next indirect
reference (typically JMP *).

RES

707742

Restore. Provides for restoration of the LIN K,
Bank Mode, and User Mode status to the interrupted
program.

SPI

705501

Skip on priorities inactive. Tests for the successful raising of' a ISA-initiated priority level.

RPL

705512

Reads API status bits from API logi c into the AC.

ISA

705504

Initiate selected activity. Requests service at a
software priority level or raises the currently active
priority to a higher level. Also, enables or disabl es the API system.

Description

6.7.3 Programming Considerations
DBK Instruction (703304)
The DBK instruction is used in a currently active API service routine to return the routine to its normally assigned priority level, after the need for its temporary raising (by ISA or CAL) has been satisfied.

DBK is not normally used to terminate an API or Program Interrupt service routine because it

does not enable the PDP-15 to restore LINK, Bank Mode, and User Mode status to the interrupted
program.

DBR)nstruction (703344)
The DBR instruction also returns the currently active API routine to its normally assigned priority level.
Additionally, it enables the PDP-15 System to restore the LINK, Bank Mode, and User Mode to the
status they occupied at the time of interrupt. The status of these modes is stored in core memory by
JMS; the interrupt program count is also stored in core memory when the API service routine is entered.
Normally the next to the last instruction in the service routine, DBR is followed by a JMP * to the
interrupted program, which performs the actual restoration of the -program count and the status

6-49

information. As for all lOT instructions, another interrupt cannot occur until execution of the
subsequent instruction, i.e., JMP * , is completed. Restoration actually occurs at the first indirect
instruction after the DBR.
RES Instruction (707742)
The RES instruction restores the status of the LINK, Bank Mode, and User Mode, at the first indirect
instruction after it is executed. It does not, however, affect the API priority levels.
SPI Instruction (705501)
The SPI instruction tests for the successful ISA- initiated raising of a priority and uses a control word
previously placed in the AC (by LAC) to test the priority I evel of the currently active API service
routine. In the API logic, the control bits are compared with corresponding API status conditions.
The program skips the next instruction if any corresponding API conditions for the set control bit are
true (refer to Table 6-8).

Table 6-8
SPI Control Word Format

AC Bit

API Condition Tested

API ENABLE (1)

01-09

Not Used

Priority level 0 inactive (highest)

Priority levelland higher inactive

Priority level 2 and higher inactive

Priority level 3 and higher inactive

Priority level 4 and higher inactive (software)

Priority level 5 and higher inactive (software)

Priority level 6 and higher inactive (software)

Priority level 7 and higher inactive (software)

ISA Instruction (705504)
The ISA instruction controls the status of API priorities. It initiates the activity specified by a control word placed in the AC by a previous LAC instruction. Table 6-9 shows the control word format.
Within lower priority service routines, it may be necessary to raise the service routine's priority level
in order for it to continue without interruption by any higher priority API request; for example, this

6-50

may be necessary because of some calculation within the service routine. By issuing the ISA
instruction (w ith the proper bit set in the AC), the priority of the servi ce routine is raised, and no
'instruction in a channel address is executed. The service routine continues at the higher priority
level. Thus, the two priority levels are currently active to restore the routine to its original priority
level; a DBK releases the highest currently active priority level. ISA instructions cannot be used to
lower the priority of a currently active service routine because the logic does not recognize the
request.

Table 6-9
ISA Control Word Format

Activ.ity Specified

AC Bit

Enable API (disable if 0)

Not Used

Test Request level 0 (Maintenance Only)

Test Request level 1 (Ma intenance On Iy)

Test Request level 2 (Maintenance Only)

Test Request level 3 (Maintenance Only)

Request servi ce at priority level 4 (software)

Request service at priority level 5 (software)

Request service at priority level 6 (software)

Request service at priority level 7 (software)

Raise priority to level 0

Raise priority to level 1

Raise priority to level 2

Raise priority to level 3

Raise priority to level 4

Raise priority to level 5

Raise priority to level 6

Raise priority to level 7

In addition to its normal function, the ISA instruction is also used to test API hardware levels in the
API test program.
Because a PDP-15 and API option can be obtained with no hardware devices on levels 0 through 3, bits
2 through 5 of the AC, when executing a ISA, are used to set test requests which check out the

6-51

operation of the API.

Therefore, under normal program operations, if any of these bits are set, a

break occurs from one of the test requests and results in an error.
RPL Instruction (705512)
The RPL instruction is used to read API status bits (refer to Table 6-10) from the API logic into the AC
through the Input Mixer.

Table 6-10
Maintenance Instruction Status Word

Status Bit

Status Of

Status Bit

Status Of

API ENABLE

API7 RQ

Not used

PLO

APIO RQ

PL1

API 1 RQ

PL2

API2 RQ

PL3

API3 RQ

PL4

API4 RQ

PL5

API5 RQ

PL6

API6 RQ

PL7

CAL Instruction with API
The CAL instruction can be used in conjunction with the software API levels and, when executed,
raises priority level 4, provided no hardware levels are set. This function can be used to prevent
other software levels from interrupting the level currently active.

No break, other than the actual

CAL instruction, occurs at this time. CAL must not be used when servicing hardware level interrupts.
Program Interrupt with API
Whenever a program interrupt occurs in the PDP-15, priority level 3 is raised, giving the program
interrupt a priority between the hardware levels and the software levels. Program interrupts can
occur whi Ie software priority levels are set, but do not occur when hardware levels or requests are
enabled. A DBR instruction in the interrupt service routine is used to release the system from priority
level 3.

6-52

Dynamic Priority Re-allocation
Three distinct methods for dynamic priority re-allocation are described below.
a.

Device-Dependent - Because channel number and priority level are independent,
a device can be designed to interrupt at anyone of several priority levels without grossly affecting programming. In a control appli cation, the device raises
its priority under program control when the data rate increases.

Program-Generated Service Requests - The program can generate interrupt requests on
any of four software priority levels. If the level is below the currently active priority,
the request is honored when the higher priority levels are released. If the level is
higher than the currently active level, the request is honored immediately. The JMS
instruction in the software priority channel is executed, storing the current program
count and entering the new program segment.

Programmed Priority Changes - For an interruptable program to change parameters in
an interrupt service subroutine, the priority interrupt system is turned off while the
changes are effected. Unfortunately, al t interrupts are shut out during this time,
including those that indicate machine errors or are vital in controlling real-time
processes. Thus, the API has been designed to enable a program segment to raise its
priority only high enough to shut out those devices whose service routines require
changes. This method of raising and lowering priority requires the least amount of
time. By issuing the ISA instruction with the proper bits set in the accumulator, the
priority of the currently active program segment is raised. No instruction in a channel is executed, and the program continues on at its higher priority level. To restore
the program segment to its original priority level, a DBK instruction is issued.
For example, a priority 2 routi.ne is entering data in memory locations A through A + 10;
however, based on a calculation made by a priority 6 routine, it becomes necessary to
move the data to memory locations B through B + 20. The changes in the routine at
level 2 must be completed, without interruption, once begun. It is possible to complete the changes having the level 6 program raise itself to level 2 (devices on the
same or lower priority may not interrupt), complete the changes, and debreak back
to level 6.

6.7.4 Programming Examples
Input Ten Words from A/D Converter - A service routine INAD inputs 10 words to a
FORTRAN array for later processing. The core location of the A/D channel contains a JMS INAD.
The basic components of INAD are:
INAD

o
DAC SAVAC
lOT

lOT
LAC SAVAC

/ENTRY POINT
/SAVE AC
/READ A/D BUFFER
/STORE IN ARRAY
/TEST FOR LAST WORD-IF YES, INITIATE
/SOFlWARE INTERRUPT TO ACCESS DATA
/FORMATTING ROUTINE
/ELSE, START NEXT CONVERSION
/RESTORE AC

6-53

lOT
DBR
JMP * INAD

/CLEAR DEVICE FLAG
/DEBREAK AND RESTORE
/RETURN

The program segment to start the conversion is as follows:

lOT

/INITIALIZE INAD
/SELECT CONVERTER FOR FIRST CONVERSION
/CONTINUE WITH PROGRAM

If INAD were active, it could be instructed to input an additional 10 words with the following
segment:
LAC ()
ISA

DBK

/CONTROL WORD
/RAISE PRIORITY TO
/LOCK OUT INAD
/CHANGE INAD PARAMETERS
,/RESTORE PRIORITY TO ORIGINAL LEVEL

Simulation of Hardware Interrupt - A hardware interrupt can be simulated by:
LAC ()
ISA
JMSINAD

/CONTROL WORD
,/RAISE TO HARDWARE PRIORITY
/ENTER INAD

Use of Software Levels - An organizational example of a program using five levels is as
follows:
Interrupt level 0

Highest priority alarm conditions,
computer or processor malfunctions.

Interrupt level 1

Control process A/D-D/A, sense and
control input/output routines.

Interrupt level 2

Teletype I/O routines for operator
interface, operator can query or demand changes as required. Program
interrupt.

Interrupt level 3

FORTRAN subroutines to calculate process control input/output data. Direct
digital control routines.

Main Program

Lowest Priority, operator interface programming, requested readout, etc.

Queueing - High priority,./11igh data rate/short access routines cannot perform complex calculations based on unusual conditions without holding off further data inputs. To perform the calculations,
the high priority program segment must initiate a lower priority {interruptable} segment to perform the
calculation. Because in general, many data handling routines are requesting calculations, there is a
queue of calculation jobs waiting to be performed at the software level. Each data handling routine
must add its job to the appropriate queue and issue an interrupt request (ISA instruction) at the corresponding software priority level.

6-54

6.8

FP15 FLOATING-POINT PROCESSOR

The FP15 Floating-Point Processor performs single- and double-precision floating-point arithmetic,
and integer arithmetic operations. The FP15 is a hardware option for PDP-15/20, -15/30, -15/35,
and -15/40 systems that can perform arithmetic operations ten times faster than existing software rou.
It features 9 - d·Iglt
: precIsion
. . ant
. h
· on num b
· h·In t he 10- 131 , 072 to 10 131 , 071 range.
tmes.
metlc
ers Wit
The FP15 is a complete processor, with its unique instruction set, that interfaces directly with up to
128K of core memory. It monitors every instruction fetched by the KP15 central processor. When it
recognizes a floating-point instruction, the FP 15 inhibits the KP15 and begins the specified function.
Basically, FP15 operations consist of memory transfers to obtain and store data and arithmetic operations within the FP15. Memory cycle time and I/O processor operations, as well as data channel latency, are not affected by the FP15 option. Thus, block transfers to and from memory via the I/O
processor may occur simultaneously with FP15 operations. However, program and priority interrupts
are inhibited.
Because the FP15 Floating-Point Processor executes a set of more than 100 instructions, the complete
description of the purpose and use of this option is provided in a separate manual--FP15 FloatingPoint Processor Programmers Reference Manual, DEC-15-HQEB-D.

6-55

Appendix A
Instruction Summary

Table A-l
Memory Reference Instructions

Mnemonic
Symbol

Octal
Code

Machine
Cycles

Operation
Executed

CAL Y

Call subroutine. The address portion of
this instruction is ignored. The action is
identical to JMS 20.

DAC Y

Deposit AC. The content of the AC is deposited in the memory cell of location Y.

JMS Y

Jump to subroutine. The content of the
PC and the content of the L are deposited
in memory cell Y. The next instruction is
taken from cell Y + 1 •

DZM Y

Deposit zero in memory. Zero is deposited
in memory cell Y.

LAC Y

Load AC. The content of Y is loaded into
the AC.

XORY

Exclusive OR. The exclusive OR is performed between the content of Y and the
content of the AC, with the result left in
the AC.

ADD Y

2.3

Add (l's complement). The content of Y is
added to the content of the AC in l's complement arithmetic and the result is left in
the AC.

TAD Y

2's complement add. The content of Y is
added to the content of the AC in 2's complement arithmetic and the result is left in
the AC.

XCT Y

Execute. The instruction in memory cell Y
is executed.

A-l

Table A-1 (Cont)
Memory Reference Instructions

Mnemonic
Symbol

Octal
Code

Machine
Cycles

Operation
Executed

ISZ Y

Increment and skip if zero. The content of
Y is incremented by one in 2 1 s complement
ari thmeti c • If the resu I tis zero, the next
instruction is skipped.

AND Y

AND. The logical operation AND is performed between the content of Y and the
content of the AC with the result left in
the AC.

SAD Y

Skip if AC is different from Y. The content
of Y is compared with the content of the AC.
If the numbers are different, the next instruction is skipped.

JMP Y

Jump to Y. The next instruction to be executed is taken from memory cell Y.

Table A-2
Operate Ins'tructions

Mnemonic
Symbol

Octal
Code

Operation
Executed

OPR
or
NOP

740000

Operate group or no operation. Causes a singlecycle program delay.

CMA

740001

Complement accumulator.
complemented.

CML

740002

Complement link.

OAS

740004

Incl usive OR ACCUMULATOR switches. The word
set into the ACCUMULATOR switches is OR combined with the content of the AC, the result remains in the AC.

RAL

740010

Rotate accumulator left. The content of the AC
and L are rotated one pos i ti on to the I eft.

RAR

740020

Rotate accumulator right. The content of the AC
and L are rotated one position to the right.

lAC

740030

Increment the accumulator.

TCA

740031

2 1s complement AC.

A-2

Each bit of the AC is

Table A-2 (Cont)
Operate Instructions

Mnemonic
Symbol

Octal
Code

Operation
Executed

HLT

740040

Halt. The program is stopped at the conclusion of
the cycle.

SMA

740100

Skip on minus accumulator ~ If the content of the
AC is negative (2's complement) number the next
instruction is skipped.

SZA

740200

Sk ip on zero accumulator. If the content of the
AC equals zero (2's complement), the next instruction is skipped.

SNL

740400

Skip on nonzero Iink. If the L contains a 1, the
next instrucf'ion is skipped.

SKP

741000

Skip. The next instruction is unconditionally
skipped.

SPA

741100

Skip on positive accumulator. If the content of
the AC is zero (2's complement) or a positive
number, the next instruction is skipped.

SNA

741200

Skip on nonzero accumulator. If the content of
the AC is not zero (2's complement), the next
instruction is skipped.

SZL

741400

Skip on zero link. If the L contains a 0, the
next instruction is skipped.

RTL

742010

Rotate two Ieft. The content of the AC and L
are rotated two positions to the left.

RTR

742020

Rotate two right. The content of the AC and L
are rotated two positions to the right.

SWHA

742030

Swap halves of the AC.

CLL

744000

Clear Iink. The L is cleared.

STL

744002

Set link. The L is set to 1.

RCL

744010

CI ear Iink, then rotate Ieft. The L is cleared,
then the Land AC are rotated one position left.

RCR

744020

Clear link, then rotate right. The L is cleared,
then the Land AC are rotated one position right.

CLA

750000

Clear accumulator.

CLC

750001

Clear and complement accumulator.
the AC is set to contain a 1.

LAS

750004

Load accumulator from switches. The word set
into the ACCUMULATOR switches is loaded in to
the AC.

A-3

Each bit of the AC is cleared.
Each bit of

Table A-2 (Cont)
Operate Instructions

Mnemonic
Symbol

Octal
Code

Operation
Executed

GLK

750010

Get link. The content of L is set into AC 17 •

LAW N

76XXXX

Load the AC with 76XXXX.

Table A-3
Index Register Transfer Instructions
Operation
Executed

Mnemonic
Symbol

Octal
Code

Memory
Cycle

PAX

721000

Place accumulator in index register.

PAL

722000

Place accumulator in limit register.

PXA

724000

1 (1)

Place index register in accumulator.

PXL

726000

PI ace index register in I imit register.

PLA

730000

Place limit register in accumulator.

PLX

731000

Place I imit register in index register.

Table A-4
Register Control Instructions

Mnemonic
Symbol

Octal
Code

Memory
Cycle

Operation
Executed

AXS n

725 + n

Add n to index register and sk ip if ~
limit register.

AXRn

737 + n

Add n to index register.

AAC n

723 + n

Add n to accumulator.

CLX

735000

Clear index register.

CLLR

736000

C Iear I imit register.

*For these twelve instructions, although only one memory cycle is required, the CPU
requires another cycle to compl ete the operation.

A-4

Table A-5
EAE Instructions

Mnemonic
Symbol

Octal
Code

EAE

640000

1.325

Basic EAE Command

LRS

640500

2.915 + .13h*

Long right shift

LRSS

660500

2.915 + .13h*

Long right shift, signed

LLS

640600

2.915+.13h*

Long left shift

LLSS

660600

2.915 + .13h*

Long left shift, signed

ALS

640700

2.915 + .13h*

Accumulator left shift

ALSS

660700

2.915 + .13h*

Accumulator left shift, signed

NORM

640444

2.915 + .13h*

Normal ize, unsigned

NORMS

660444

2.915 + .13h*

Normal ize, signed

MUL

653122

2.915 + .26L ***

Multiply, unsigned

MULS

657122

2.915 + .26L***

Multiply, signed

DIV

640323

2.915 + .26m**

Divide, unsigned

DIVS

644323

2.915 + .26m**

Divide, signed

IDIV

653323

2.915 + .26m**

Integer divide, unsigned

IDIVS

657323

2.915 + .26m**

Integer divide, signed

FRDIV

650323

2.915 + .26m**

Fraction divide, unsigned

FRDIVS

654323

2.915 + .26m**

Fraction divide, signed

LACQ

641002

1.325

Load AC with MQ

LACS

641001

1.325

Load AC with SC

CLQ

650000

1.325

Clear MQ

ABS

644000

1.325

Load AC with

GSM

664000

1.325

Get sign and magnitude

OSC

640001

1.325

OR SC to AC

OMQ

640002

1.325

ORMQ to AC

CMQ

640004

1.325

Complement MQ

LMQ

652000

1.325

Load MQ from AC

Execute
Time (jJS)

Operation
Executed

*Where "h" is the number of steps, the instruction must carry out 0::;,n::;,36
**Where "m" is the number of steps, a divide instruction carries out O:s,m::;, 19
***Where ilL II is the number of steps, a multiply instruction carries out 0::;. L~ 18

A-5

Table A-6
Standard API Channel/Priority Assignments

Channel

Device

Option Number

Priori ty

Address

Software Priority

----------------

Software Priority

------

DECtape

TC02 or TC15

Magtape

TC59

Not assigned

Paper Tape Reader

PC15

Clock Overflow

KW15

Power Fail

KF15

Parity

MP15

Display (Lightpen Flag)

VP15

Card Readers

CR03B

Line Printer

LP15 C/F

A/D

AD15

DB99A/DB98A

DB09A

Not assigned

Dataphone

DP09A

Disk

RF15

Disk

RP15

Plof'ter

XY15

Not assigned

Teletype Keyboard

LTl9/LTl5A

Teletype Printer

LTl9/LTl5A

DECtape (DCH
Channel 36)

TC02 or TC15*

Dataphone

DP09*

*Channel allocated for systems with more than one of the above options.

A-6

Table A-7
PDP-15 lOT Device Selection Codes

1 RT Clock
2 Prog Interrupt
4 RT Clock

10 AFC-15
UDC-15

PC15
High Speed
Paper Tape
Reader

Analog-to- Dig ital 21
or
Digital-to-Analog
Converter

PC15
High Speed
Paper Tape
Punch

AID or

1 Keyboard
2 Keyboard
4 laRS

Tel eprinter

14 AM03 & AM09
SDO,l SYS I
SD2,3 SYS II

Incrementai
Plotter Control
XY15

DP09A
Data
Communication

»I
.......

05 VP15A, B, BL
C, CL

DIA Converter

AID

30 VT15
Graphic
Processor

40 LT19
line 1, 2, 3, 4
Teleprinter or
LT15A

Rei ay Buffer
DR09A

VTl5
Graphic
Processor

41 Line 1,2,3,4
Keyboard or
LTl5A

IPB
DB09A

SDO - KF15
SDl-3 - VT09
Display Option

42 Line 5,6,7,8
Teleprinter

1 33 KSR Skip
2 Clear All Flags
4 DBR, DBK

43 Line 5,6,7,8
Keyboard

Disk Pack
RP09/RP15

Magnetic Tape
Control
TC59

44 Line 9,10,11;12
Teleprinter
DC01EB #102

Disk
RP09/RP15

,1V\agnetic Tape
Control
TC59

45 Line9,10,l1,12
Keyboard
DC01EB #304

Line Printer
LP15 C/F

DECtape
Control

20 AFC-15
UDC-15

Converter

VP15A B
BL CL

VP15A, B,
BL, CL

17 Memory
Protect and
Relocate
KM15
KT15

DP09A
Data
Communi cation

Memory
Parity
MP15

DECdisk
RF15

I
I

46 Line 13,14,15,16 56
Tel eprinter

AAOl

Automatic
Priority
Interrupt
KA15

DECdisk
RF15

TC02/TC15
66

Line Printer
LP15 C/F

DECtape
Control

TC02/TC15
47 Line 13,14,15,16 57
Keyboard

Card Reader
Type CR03B

61 Skip on Bank Mode
62 Disable Bank Mode
64 Enable Bank Mode

Table A-8
Input/Output Transfer Instructions

Mnemonic
Symbol

Operation
Executed

Octal
Code

Program Interrupt
IOF

700002

Interrupt off. Disable the PIC.

ION

700042

Interrupt on. Enable the PIC.
KW15 Real-Time Clock

CLSF

700001

Skip the next instruction, if the CLOCK flag is set to 1.

CLOF

700004

Clear the CLOCK flag and disable the clock.

CLON

700044

Clear the CLOCK flag and enable the clock.
PC15 High Speed ,Paper Tape Reader

RSF

700101

Skip, if READER flag is a 1.

ReF

700102

Clear READER flag, then inclusively OR the contents of
the reader buffer into the AC.

RRB

700112

Read reader buffer. Clear READER flag and AC, and then
transfer content of reader buffer into AC.

RSA

700104

Select reader in alphanumeric mode. One 8-bit character
is read into the reader buffer.

RSB

700144

Select reader in binary mode. Three 6-bit characters are
read into the reader buffer.
PC15 High Speed Paper Tape Punch

PSF

700201

Skip, if the PUNCH flag is set to 1.

PCF

700202

Clear the PUNCH flag.

PSA or
PLS

700204
700206

Punch a line of tape in alphanumeric mode.

PSB

700244

Punch a line of tape in binary mode.
I/O Equipment

10RS

700314

Input/output read status. The content of given flags replaces the content of the assigned AC bits.

TTS

703301

Test Teletype, and skip if 33 KSR Teletype is connected
to computer.

CAF

703302

Clear all flags.

SPCO

703341

Skip, if a PC15 is connected to the system.

SK15

707741

Skip, if processor is a PDP-15.

A-8

Table A-8 {Cont}
Input/Output Transfer Instructions

Mnemonic
Symbol

Octal
Code

Operation
Executed

I/O Equipment {Cont}
SBA

707761

Skip, if processor is in Bank Mode.

DBA

707762

Disable Bank Addressing {enter Page Mode}.

EBA

707764

Enable Bank Addressing
Teletype Keyboard

KSF

700301

Skip, if the KEYBOARD flag is set to 1.

KRB

700312

Read the keyboard buffer. The content of the buffer is
placed in AC 10-17 and the KEYBOARD flag is cleared
{half-duplex operation}.

KRS

700332

Read keyboard buffer and select keyboard reader {fullduplex operation}.
Teletype Teleprinter

TSF

700401

Skip, if the TELEPRINTER flag is set.

TCF

700402

Clear the TELEPRI NTER flag.

TLS

700406

Load te lepri nter buffer. The content of AC 10-17 is placed
in the buffer and printed. The flag is cleared before transmission takes place and is set when the character has been
printed.
VP15A Storage Tube Display

CXB

700502

Clear X-coordinate buffer

CYB

700602

Clear V-coordinate buffer

LXB

700504

Load X-coordinate buffer from AC8-17

LYB

700604

Load V-coordinate buffer from AC8-17

EST

700724

Erase storage tube

SDDF

700521

Skip on DISPLAY DONE flag.

CDDF

700722

Clear DISPLAY DONE flag.

LXBD

700564

Load X-coordinate buffer and display the point specified
by XB and YB {store mode}.

LYBD

700664

Load Y -coordinate buffer and display the point specified
by X Band Y B (store mode).

LXDNS

700544

Load the X-coordinate buffer and display the point specified by X Band YB (nonstore mode).

A-9

Table A-8 (Cont)
Input/Output Transfer Instructions

Mnemonic
Symbol

Octal
Code

Operation
Executed

VP15A Storage Tube Display (Cont)
LYONS

700644

Load' the V-coordinate buffer and display the point specified by XB and YB (nonstore mode).

VP15B (RM503), BL (RM503 and Lieht Pen), C (VR12)
and CL (VR12 and Light Pen)
DXL

700504

Load the X-coordinate buffer from AC8-17

DXS

700544

Load the X-coordinate buffer and display the point specified by the XB and YB.

DYL

700604

Load the V-coordinate buffer from AC8-17.

DYS

700644

Load the V-coordinate buffer and display the point specified by the XB and YB.

DXC

700502

Clear the X-coordinate buffer.

DYC

700602

Clear the V-coordinate buffer.

DLB

700704

Load the brightness register from bits 16-17 of the AC.
This instruction clears the display flag associated with
the light pen.

DSF

700501

Skip, if DISPLAY (light pen) flag is a 1 •

DCF

700702

Clear DISPLAY (light pen) flag.
VP15M Storage Tube Display Multiplexer

LUDU

700764

Load unit designation register from AC 10-17.
KM15 Memory Protect

MPSK

701701

Skip on PROTECT VIOLATION flag.

MPCV

701702

Clear PROTECT VIOLATION flag.

MPLD

701704

Load core allocation register.

MPLR

701724

Load relocation register.

MPSNE

701741

Skip on nonexistent MEMORY flag.

MPEU

701742

Enter User Mode.

MPCNE

701744

Clear nonexistent MEMORY flag.
KTl5 Memory Relocate

MPSK

701701

Skip on PROTECT VIOLATION flaa.

MPCV

701702

Clear PROTECT VIOLATION flag.

A-10

Table A-8 (Cont)
Input/Output Transfer Instructions

Mnemonic
Symbol

Operation
Executed

Octal
Code

KT15 Memory Relocate (Cont)
MPLD

701704

Load the boundary register with the contents of AC 01-09.

MPSNE

701741

Skip on nonexistent MEMORY flag.

MPEU

701742

Enter user mode.

MPCNE

701744

Clear nonexistent MEMO RY flag.
MP15 Memory Parity

SPE

702701

Skip on PARITY ERROR flag.

CPE

702702

Clear parity error.

PNP

702704

Force wrong parity.
VT15 Graphic Processor

RS1

703002

Read status 1

RS2

703022

Read status 2

RS3

703142

Read status 3

RYP

703042

Read Y register

RPC

703062

Read program counter

RXP

703102

Read X register

SSA

703122

Single-step advance (Debugging)

SPSF

703001

Skip on STOP flag.

SPLP

703021

Skip on LIGHT PEN flag.

SPPB

703041

Skip on PUSHBUTTON flag.

SPEF

703061

Skip on EDGE flag.

SPDF

703101

Skip on any flag.

SPDI

703121

Skip on any interrupting flag.

SSLP

703141

Skip on SLAVE LIGHT PEN flag (Multiplexer with more
than one VT04-374).

SPES

703161

Skip on external stop (Check STPD accompl ished).

LSD

703004

Load and start display (Initial izes VT15)

SIC

703024

Set initial conditions.

STPD

703044

External stop display (PDP-15 stops displ ay).

RES

703064

Resume display after flag.

A-ll

Table A-8 (Cont)
Input/Output Transfer Instructions

Mnemonic
Symbol

Operation
Executed

Octal
Code

K F15 Power Fail Option
SPFAL

703201-

Skip, if POWER-LOW flag is set.
KA 15 Automatic Priority Interrupt

DBK

703304

Debreak

DBR

703344

Debreak and restore.

SPI

705501

Skip on priorities inactive.

RPL

705512

Read API status

ISA

705504

Initiate selected activity

ENB

705521

Enab Ie breaks

INH

705522

Disabl e breaks

RES

707742

Restore
RP15 Disk Pack Control

DPSF

706301

Skip on DISK flag.

DPOSA

706302

OR the status register A into AC.

DPRSA

706312

Read the status register A into AC.

DPOU

706402

OR the unit cylinder address register into the AC.

DPRU

706412

Read the unit cylinder address register into the AC.

DPSA

706321

Skip on Attention flag.

DPOSB

706322

OR status register B into the AC.

DPRSB

706332

Read status register B into the AC.

DPLZ

706424

Load the accumulator zeros into status register A bits 0
through 7 and execute.

DPLO

706444

Load the accumulator ones into status register A bits 0
through 7 and execute.

DPeN

706454

Execute the function register.

DPLF

706464

Load the status reg ister A and execute.

DPLA

706304

Load the cy Ii nder, head, and sector address reg isters from
the accumulator.

DPCA

706344

Load the current address register.

DPWC

706364

Load the word count register.

A-12

Table A-8 (Cont)
Input/Output Transfer Instructions

Mnemonic
Symbol

Octal
Code

Operation
Executed

RP15 Disk Pack Control (Cont)
DPOA

706422

OR the cyl inder, head, and sector address register into the
AC. AC bits 13 through 17 are ORed with the sector.

DPRA

706432

Read the cyl inder, head, and sector address into the AC.

DPOC

706442

OR the current address register into the AC.

DPRC

706452

Read the current address register into the AC.

DPOW

706462

OR the word count register into the AC.

DPRW

706472

Read the word count register into the AC.

DPCS

706324

Clear status.

DPCF

706404

Clear function register.
RP15 Maintenance lOTs

DPSJ

706341

Skip, if the JOB DONE flag is set.

DPSE

706361

Skip, if an error condition is present.

DPOM

706342

OR the six-bit maintenance register into AC.

DPRM

706352

Read the six-bit maintenance register into AC.

DPEM

706401

Execute maintenance instruction.

DPLM

706411

Leave maintenance mode. The AC is left cl eared.
LP15C/F Line Printer Controls

LPSF

706501

Causes a skip request, if done or error is set.

LPPM

706521

Initializes the control, sets header; sets multiline.

LPP1

706541

Initial izes the control, sets header; does not set multi line.

LPRS

706542

Read status.

LPEI

706544

Sets the ENABLE INTERRUPT flop.

LPDI

706561

Clears the ENABLE INTERRUPT flop.

LPCD

706621

Clears DONE flag.

LPCF

706641

Clears STATUS and ERROR flag.
Line Printer Maintenance lOTs

MRVFU

706502

Read VFU register.

MCVFU

706504

Clear VFU register.

A-13

Table A-8 (Cont)
Input/Output Transfer Instructions

Mnemonic
Symbol

Operation
Executed

Octal
Code

Line Printer Maintenance lOTs (Cont)
MSM

706524

Set maintenance control.

MRDB1

706562

Read data buffer 00-17 •

MCDB

706564

C Iear data buffer.

MCM

706601

Clear maintenance control.

MRDB2

706602

Read data buffer 18-35.

MLDB1

706604

Load data buffer 0-17 from AC.

MRM1

706622

Read maintenance word 1 •

MLDB2

706624

Load data buffer 18-35 from AC.

MRM2

706642

Read maintenance word 2.

MLS

706644

Load status.
CR03B Card Reader

CRCS

706704

Clear status register and data buffer.

CRSI

706721

Skip on CARD READER flag.

CROR

706712

Load data buffer and machine status into AC.

CRSC

706722

CI ear the status reg ister and data buffer; sel ect a card.

CRLA

706724

Load status and data register from AC.
RF15 DECdisk Control

DSSF

707001

Skip on DISK flag.

DRBR

707002

OR the contents of the buffer register with the AC.

DLBR

707004

Load the contents of the AC into the buffer register.

DSCC

707021

Clear the disk control and disable the "freeze" status of
the control.

DRAL

707022

OR the contents of the address pointer 0 (APO) into the
AC. Bits 0 through 6 contain the track address 1 and bits
7 through 17 contain the word address of the next word to
be transferred.

DRAH

707062

OR the contents of the disk number (APl) into the AC.
Bits 15, 16, and 17 contain the disk number. Bit 14 is
read back if a data transfer exceeded the capacity of the
disk control. (Causes a NED error status.)

A-14

Table A-8 (Cont)
Input/Output Transfer Instructions

Mnemonic
Symbol

Octal
Code

Operation
Executed

RF15 DECdisk Control (Cont)
DLAL

707024

Load the contents of the AC into the APO.

DLAH

707064

Load the contents of the AC (15, 16, 17) into the disk
number (AP1).

DSCF

707041

Clear the function register, interrupt mode.

DSFX

707042

XOR the contents of AC bits 15-17 into the function
register (FR).

DSCN

707044

Execute the condition held in the FR.

DLOK

707202

OR the contents of the 11-bit disk segment address (ADS)
into the AC.

DGHS

707204

Generate simulated head signals.

DGSS

707224

Generate simulated disk signals.

DSCD

707242

Clear the status register and DISK flag.

DSRS

707262

OR the contents of the disk status register wi th the AC.

Type TC59 Magnetic Tape Control lOT Instructions
MTTR

707301

Skip on tape transport ready (TTR).

MTCR

707321

Skip on tape control ready (TCR).

MTSF

707341

Skip on ERROR flog or MAGNETIC TAPE flag (EF and MTF).

MTAF

707322

Clear status and command registers and EF and MTF.

LCM

707324

Inclusively OR content of AC _

MTLC

707326

Load content of ACo-11 into command register.

. MTCC

707356

Terminate write continuous mode.

707342

Inclusively OR content of status register into AC _

MTRS

707352

Read content of status register into ACo-11 •

MTRC

707312

Read command register into AC _

MTGO

707304

Set "go II bit to execute command in command register.

O ll

into command register.

O 11

TC15 DECtape Control
DTCA

707541

Clear status register A.

DTRA

707552

Read status register A.

DTXA

707544

XOR status register A.

A-15

•

Table A-8 (Cont)
Input/Output Transfer Instructions

Mnemonic
Symbol

Operation
Executed

Octal
Code

TC15 DECtape Control (Cont)
DTlA

707545

load status register A.

DTEF

707561

Skip on ERROR flag.

DTRB

707572

Read status B.

DTDF

707601

Skip on DECtape flag.
AD 15 Analog Subsystem

ADCV

701304

load status register from accumulator, clear A/D done
flag, and initiate conversion.

ADRB

701302

Read data buffer into accumulator and clear A/D done
flag.

ADRS

701342

Read status register into accumulator.

ADCF

701362

Clear all AD15 flags.

ADSF

701301

Skip on A/D flag.

WCSF

701341

Skip on word count overflow flag.

MSSF

701321

Skip on memory overflow flag.
UDC-15 Universal Digital Control

UMOD

701001

Set UDC mode

USINT*

702002

Interrupt Select

ULA*

702024

load address.

URA*

702012

Read deferred address.

URD*

702032

Read data in.

USCAN*

702021

Start interrupt scan.

USNB*

702041

Skip if not busy.

URCG

701072

Clear AC, read COS gates.

UlD

701064

load data out.

UlPS

701044

load previous status.

USI

701041

Skip on immediate flag.

USD

701061

Skip on deferred flag.

URAA

701052

Read immediate address.

*The UMOD lOT must be issued before these lOTs will be decoded as UDC-15 lOT instructions.

A-16

Table A-8 (Cont)
Input/Output Transfer Instructions

Mnemonic
Symbol

Octal
Code

Operation
Executed
AFC-15 Automatic Flying Capacitor

FCMOD

701021

Set AFC mode.

FCEI*

702004

Enable AFC interrupt.

FCDI*

702001

Disable AFC interrupt.

FCLAG*

702024

Load address.

FCRB*

702032

Read A/D buffer.

FCSD*

702041

Skip on A/D done flag.

FCRA*

702012

Read AFC address register.
BD-15 Maintenance

MCLK

702044

Maintenance clock.

MSM

701004

Set maintenance mode.

MCM

701022

Clear maintenance mode.

MLS

701024

Load status register.

MRS

701012

Read status register.

FCCV

702021

A/D convert.

*The FCMOD lOT must be issued before these lOTs will be decoded as AFC-15 lOT instructions.

A-17