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December 1975

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Document:	DH11 Asynchronous 16-line Multiplexer Maintenance Manual
Order Number:	EK-0DH11-MM
Revision:	3
Pages:	201
Original Filename:

OCR Text

DH11 asynchronous

16-line multiplexer

maintenance manual

EK-ODH11-MM-003

DH11 asynchronous

16-line multipl_exer.
maintenance manual

digital equipment corporatioh - maynard, massachusetts

1 st Edition, December 1973

2 nd Printing (Rev), April 1975

The material in this manual is for informational
purposes. and -is subject to -change without notice.
Digital Equipment Corporation assumes no respon-

sibility for any errors which may appear in this
manual.

The following are trademarks of Digital Equipment

Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

UNIBUS

Page

CHAPTER 1

GENERAL DESCRIPTION

1.1

INTRODUCTION

. . . . .

1.1.1

DH11-AA and -AC Line Interfaces

1.1.2

DHI11-AB Line Interfaces

1.1.3

e e

. . . . . . . . . . .. ..

DH11-AD and -AE Line Interfaces

e e e

. . . . .. . ... .. ... .. .. ... .....

...

. . ... ... ... e

e e

1-2
1-2

PHYSICAL DESCRIPTION

1.2.1

Configurations

1.2.2

Multiplexer Distribution Panel and Power Supply

. . . . . . ... . ... L. e
e e

123

General Specifications

FUNCTIONAL DESCRIPTION

1.3.1

Receiver Operation

13.2

SiloOperation

....... e

e e

. . . . . . . .. .. ...
. . . . . . . . . . . e

. . . . . . . . . . . . o

. . . . . . . ...

1-7

1-7
1-7

Transmitter Operation

. . . . . . . .. . .. ... ..

Auto-Echo Operation

. . .. ... ... ... ..... e

1.3.5

Interrupts

13.5.1

e e

1-8

. . . . ..
e
e

Receiver Interrupts

. . . . . . . . .. .

Transmitter Interrupts

CHAPTER 2

INSTALLATION

CHAPTER 3

PROGRAMMING

3.1

INTRODUCTION

3.2

. . . . . . . .. L. oL

. . . . . .

3.2.1

e e

. . . . . . . .

. . . . . . . .. .. .

e e e e e e

3-1

o Lo

Next Received Character Register
Line Parameter Register

. . . . . . . . . ...

324

Current Address Register

. . . . . . . . . . . ...

3.2.5

Byte Count Register

3.2.6

Buffer Active Register

. . .. .. ....... e

e e e e e e e e e e

3.2.7

Break Control Register

. . . . . . . . . . .. .

3.2.8

Silo Status Register

.. .

3-5

L e

e e

OPERATIONAL FEATURES WITH PROGRAMMING SIGNIFICANCE

3.3.1

Introduction

Floating Device and Vector Addresses

3-6

. . . ...
.. ..

. . ... ........ O
. . . . . . .. .. . ...

3-6

. . . . . . . ..
e

3.3.2

3-1

3.2.2

. . . . . . . . . . . .

...

. . . . . . . .. ..

323

3.3

1-5
1-7

13.3

1-2
1-2

1.3.4

1352

1-1

1-2

. et
st

1.2

. . . . . .

1-1

3-6
3-7

3-7

e e e e

e e

3-8

333

Double-Buffered Receivers and Transmitters

. . . . ... ... e

334

SHlo

3-8

3.3.5

ZeroBaud . .. ............... e e e
Break Signals . . . . v . i i e
e e e e

39
39

3.3.6

. . .

3.3.7

Initialize Signal

3.3.8

Maintenance Bits SCR09 and SSR15

4.1

INTRODUCTION

4.2

ADDRESS SELECTOR AND GATINGCONTROL

. . .

e e ...

. . . . . . . . . . . . .

DETAILED DESCRIPTION

e e

e e e e

. ...

4-1

. . . ... ... ... . ... .....

4-1

oL oo

. . ... ... ......... e
e e e e e
. . . . . . . . o . o i o i e
Address Response Inhibiting Logic . . . . . . ... ... ... . L0000

4-3
44
4-8

Address Assignment

4.2.2

Device Decoding

4.2.3

Gating Control Logic

4.24

e e

. . . . . . . . . . . L

CHAPTER 4

4.2.1

e e

. . . . ... oL

CONTENTS (Cont)
Page

4.3

CLOCKMODULE M4540

43.1

Introduction

4.3.2

Counter Functional Descriptions

43.2.1

General Information

43.2.2

74H74 Flip-Flops

43.2.3

7490 Decade Counter

43.24

7492 Divide by 12 Counter

4.3.2.5

7493 4-Bit Binary Counter

4.3.2.6

74161 Synchronous 4-Bit Counter

4.3.3
4.4

4.4.1

. . . . . . . . .

- Count Down Sequence

e e

4-8

. . . . .. . . .. ... ... ... .. ... ...

. . . ... . ... ...

4-8
4-9
4-9

. . . . . . . . e
. . . . . . . . . .. ...
. . . . . . . . . ... L.

4-9
4-9
49

. . . . . . . . .. ... .. ... 4-11
. . . . . . ... ... ... ... ...... 4-12

. . .. ... ... ... ... 4-14

LINE PARAMETER CONTROL MODULEM7288
Introduction

e e e e e

. . . . . . . ...
e
e

. .. .. ... ... .......... 4-16

. . . . . . L.
e 4-16

44.2

Signal Buffering

. . . . . . . . . ... 4-17

443

Overall Operation

. . . . . . . . . . . . e 4-19

444

Transmitter Speed Selection

4.4.5

Receiver Speed Selection

4.4.6

Auto-Echo Enable and Half/Full Duplex Control Signals

4.5

TRANSMITTER SCANNER

4.5.1

Introduction

452

Functional Description

453

Logic Description

4.6

. . . . . . . .

. . . . . ...

...

L. 4-20
4-20

. . . ... ... ...... 4-23

o . 4-23

L e 4-23

. . . . . . . .. ...

. . . . . . . . . ..

...

L 4-23

e 4-25

CURRENT ADDRESS REGISTER AND CONTROLLOGIC

. . ... ........... 4-27

4.6.1

Introduction

4.6.2

Current Address Register

. . . . . . .. 4-27

. . . . . e

4.6.2.1

Functional Description

4.6.2.2

Components

e e e e e e e e e e e

e e e e e e e e 4-27

. . . . .. . ... .. ... ...

... 4-27

. . . .. . ... .. 4-27

4.6.2.3

Loadingthe CAR

46.2.4

Incrementingthe CAR

4.6.2.5

Readingthe CAR

4.6.3

. . . . . . ... .

. . . . . . . . . ... . ... ... ...

CAR Control Logic

. . . . . . . .. . .. . 4-29
. . . . . . . ..

. . . . . . . . . .

o o 4-29

4-30

. . . . . . . . . o e 4-30

4.6.3.1

Loadingthe CAR

4.6.3.2

Incrementing the CAR

. . . . . . ... ... ... ... 4-32

4.6.3.3

Loading the BC Register

. . . . . . .. ... ... ... ... . ........ 4.32

4.6.4

High Byte/Low Byte Selection Logic

4.7

BYTE COUNT REGISTER

4.7.1

Introduction

4.7.2

Byte Count Register

. . . . . . . . . . .

. . . .. .. .. ... ... ... . ...... 4-35

. . . . . . . . . e 4-35

. . . ... ... L 4-35

. . . . . . . . ... ... ... 4-37

4.7.2.1

Functional Description

4.7.2.2

Components

. . . ...
... .. e

Loading and Incrementing the BC Register

4:7.2.4

BC Register Output Logic

4.8

RECEIVER SCANNER

4.8.1

Introduction

e e e e

e e 4-37

. . . . . . . . . ... 4-37

4.7.2.3

. . . . . ... ... ... ..... 4-37

. . . . .. . . . . . . .. ... ... .. ..... 4-37

. . . . . . . e 4-39

. . . . . . ... 4-39

4.8.2

Receiver Scanner and Receiver Sequencer

4.8.3

Status Sampling Logic

4.8.4

Auto-Echo Feature

4.8.4.1

... . 4-31

Introduction

. . . . . .. ... ... ... ....... 4-39

. . . . . . . . ... L 4-44

. .. ... ... .. e

e e e e e e e e

e 4-45

. . . ... ... . 445

4.8.4.2

Functional Description

4.84.3

Normal Auto-Echo Operation

4.84.4

Use of ABANDON Signal to Prevent Auto-Echo Operation

. . . . . . . ... .. .. ... ... .. .. ... 4-45

. . . . . . ... .. ... ... .. ....... 4-46
. . . ...
... .. 4-48

CONTENTS (Cont)
Page
4.9

49.1
4.9.2
4.9.3
404

Tes/ X

4.9.5

4.10
4.10.1
4.10.2
4.103
4.104

4.11
4.12
4.12.1
4.12.2
4.12.3
4.12.4
4.12.5

4.12.6
4.12.7
4.13

4.13.1

FIFOBUFFER

. . . . . .

e e e

e e e e e e

e e 4-48

Introduction . . . . . . .. ..o
e R
448
FIFO Buffer Functional Description . .. .. .. .. e 448

FIFO Input Logic
. . . . ... . . ... ... P 449
ILoadingthe FIFO(SILO) . . . . . . . . . .
i
o 4-50

Reading the FIFO(SILO)
. . . . . . . .. . ... . .
i i 4-52
SYSTEM CONTROL REGISTER
. . .. ... ... ... ..... e
e e e e e e 4-52
General Information . . . . . . . . . .. e 4-52
Receiver Interrupt Bits . . . . . . . . . .o o 4-53
Transmitter Interrupt Bits
. . . . . ... ... ... ... e
e e
e e 4-53
Maintenance Mode . . . . . . . . . . L. L
e
e
e
e
e e
e 4-56
HALF/FULL DUPLEX CONTROL LOGIC . .. ... ... .. ... .. .. .. ..., 4-56
REGISTERS AND BYTE COUNT MODULEM7278
. . . . .. ...
... ... ..... 4-58
Introduction . . ... ... ... .00 e
e e e e e e e e e
e 4-58
Unibus Data Line Receiversand Buffers . . . . . . . ... ... ... ... ... 4-58
Line Parameter Register
. . . .. . ... ... ... ... ... ...
... 4-59
Buffer Active Register . . . . . . . . . .. 4-59
Break Control Register . . . . . . . . . . . .
o
e
e 4-60

Silo Status Register
. . . . . . . . . . . e 4-60
Output Multiplexer and Unibus Drivers
. . . . . . . .. ... ... 4-61
M7280 MULTIPLEUARTCARD . . . .. ... .. . i 4-61
Transmitter Input Data and Data Strobe Signal
. . . ... ... ... ... PR 4-61

4.13.2

Receiver Output Data and Received Data Enable Signal

4.13.3

Reset Data Available Signal

. . . .. ... .. . 4-61

4.14.4

L L oo 4-61
Status Signals
. . . . .. L L
e
e 4-62
BUS TRANSACTIONS USEDWITHTHEDHI11
. . . ... ... ... ... ....... 4-62
Introduction . . .. .. .. .. e
e e e e e e e
e
e
e 4-62
DATI, DATO, and DATOB Transactions (Processor Master) . . . . ... ... .... 4-62
DATI Transaction With DH11 Master
. . . . . ... . .. ... ...
... 4-66
Interrupt Transaction
. ... ....... e
e e e 468

CHAPTER 5

MAINTENANCE

4.134
4.14
4.14.1

4.14.2
4.14.3

5.1
5.2
5.3
54
54.1

54.2
543

5.5
5.5.1

5.5.2
553

554
555

5.5.6
5.5.7

. . . . . . . . ...

e s s e e e
e e
e e e e e e e e e e
INTRODUCTION . . . .
INTERNAL LOGIC TESTS(PART 1) . . . . . . . . . i
e
e e
e e
ON-LINETESTS (PART 2) . . . . . o o o it
GENERAL CONFIGURATION INFORMATION . . . . ... ... ... ... .. ..
e e
e e e e e e e e
e
e e e e
Introduction . . . . . . . e e
e e
. . . . . o .o i
DMII-BBOption
DM11-DC Line Adapters . . . . . . . . . .. ... o e e
e e
. . . . . . . o
DIAGNOSTIC TESTS SUMMARY
DZDHA DHI11 Static Logic Test . . . . . . . . . . .. oo
DZDHB DH11 Memory Test . . . . . . . o o o it
DZDHC DH11 Transmitter and Receiver Basic LogicTest . . . . . . ... .. .. ..
. . . . .. . ... ... ... ......
DZDHD DHI11 Speed Selection Logic Test
DZDHE DH11 Character Length and Basic Data Test . . . . .. ... ... ... ..
. . . . ... ... [
DZDHF DH11 Single Line Data Test
...
. ..
DZDHG DHI11 Multi-Line Data Test . . . .. . . . .. ..

5-1
5-1
5-3
5-3
5-3
5-3
53
54
5-4
54
5-5
5-6
5-6
5-6
5-7

5.5.8

DZDHH DH11 Auto-EchoTest

559

DZDHI DH11 Break and Half-Duplex Test

5.5.10

DZDHIJ Echo Test

5.5.11

DZDHK DHI11-AD Modem Control Test

5.6

. . . . . . . . . . ... ... ... ... ......

DIAGNOSTIC FAILURE ANALYSIS

5.6.1

DZDHA Failures

. . . . . . ... ... ... ... ....

. . . . . . . . . .

. . . . . . . . ... ... ... .......

. . . .. . . ... . ... .....e

. . . . . . . .

e e

e e e e

56.2

DZDHB Failures

. . . . . . . . . . e

5.63

DZDHC Failures

. . .. ... ...... e e

5.64

DZDHD Failures

. . .. .. .. .. .. ... ..... e

5.6.5

DZDHE Failures

. . . . . . . . . e

e e e e

e e

5.6.6

DZDHF Failures

. . . . . . . . . .

5.6.7

DZDHG Failures

. . . . . . . .

5.6.8

DZDHH Failures

. . . . . . . . . . . e

5.69

DZDHI Failures

. . . . . . . . .

APPENDIX A

e e

FLOATING DEVICE AND VECTOR ADDRESSES FOR COMMUNICATIONS DEVICES

INTRODUCTION

DEVICE ADDRESS

. . . . .

e e

. . . . . . e

APPENDIX B

PDP-11 MEMORY ORGANIZATION AND ADDRESSING CONVENTIONS

APPENDIX C

INTEGRATED CIRCUIT DESCRIPTIONS

C.1

INTRODUCTION

C.2

1488 QUAD LINEDRIVER

. . . .

.. ... ... e

. . ..

e e

... ... ... e

. . . . . . . .. ..

e e e e

1489 QUAD LINE RECEIVERS

3341 4-BIT X 64-WORD PROPAGABLE REGISTER (FI/FO)

. . ... ... .......
. . . . ... ... ... ..

CS5

4007 DUAL-BINARY-TO—-ONE-OF-FOUR LINE DECODER

C.6

4015 QUAD TYPED FLIP-FLOP

C.7

8266 2-INPUT 4-BIT MULTIPLEXER

C.8

8271 4-BIT SHIFT REGISTER

C.9

QUAD2INPUTNOR, 8640

C.10

8838 QUAD BUS TRANSCEIVER

C.11

8881 QUAD 2 INPUT NAND GATES

. . . . . . . ... .

C.12

7442 4-LINE to 10-LINE DECODER

. . . . . . . . . .. .. ...

. . . . . . . . . . ..

. . . .. e

C.13

7474/74H74 DUAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
7481 16-BIT ACTIVE-ELEMENT MEMORIES
7485 4-BIT MAGNITUDE COMPARATOR

7489 64-BIT READ/WRITEMEMORY

...

. . ..

C.14

C.15

. .. .

. . . . . . ..

C.16

e e

. . . . . . . . . .

. . . . . . ..

...,

. . .. .. ... .. ..

. . . . ... ... ... . ........

. . . . . .

... ...

... .. ...

. . . . ... . ... ... .. ..........

C.17

7490 DECADE COUNTER

C.18

7492 DIVIDE BY 2 AND DIVIDE BY 6 COUNTER

. . . . . . . . . .

C.19

7493 4-BIT BINARY COUNTER

C.20

74121 MONOSTABLE MULTIVIBRATOR

. . . . ... ... ... ......

. . . . . . . .. .. .

. . . . .. .. ... ..

...
... .. ....

C.21

74123 RETRIGGERABLE MONOSTABLE MULTIVIBRATOR WITH CLEAR

C.22

74151 8-LINE TO 1-LINE MULTIPLEXER

C.23

74154 4-LINE TO 16-LINE DECODER DEMULTIPLEXER

C.24

74155 DUAL 2-LINETO 4-LINEDECODER

. . . ..

. . . .. ... .. .. ... .........
. . .. .. ... .. ....

. . . . . ... ... ... .........

C.25

74157 QUAD 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER

C.26

74161 SYNCHRONOUS 4-BIT COUNTER

. . ...
.. ..

. . . . . ... ... .. ... .. ......

C.27

74174 HEX/74175 QUAD D-TYPE FLIP-FLOPSWITHCLEAR

C.28

74193 SYNCRHONOUS 4-BIT UP/DOWN COUNTER (DUAL CLOCK WITH CLEAR)

C.29

74197 50-MHz PRESETTABLE DECODE AND BINARY COUNTERS/LATCHES

. . ... ... ... ..

APPENDIXD

UNIVERSAL AYSNCHRONOUS RECEIVER TRANSMITTER (UART)
e

et e

. . . . . .

D.1

INTRODUCTION

D.2

UART FUNCTIONAL DESCRIPTION

APPENDIX E

DH11-AD MODEM CONTROL INTERFACE

e e

. . . . . . ..

E.l

GENERAL DESCRIPTION

E.2

FUNCTIONAL DESCRIPTION

PHYSICAL DESCRIPTION

EA4

ENVIRONMENTAL LIMITS, PERFORMANCE SPECIFICATIONS, AND

E.S

DETAILED DESCRIPTION

. . . .. ... . ... ... ...... e

. . . . . . .

INTERFACE SPECIFICATIONS
ES]

INtrodUCtion

e e i

. . ... .. e

. . . . . . .

. -« v v e e e e

e e

Address Selector Logic

Interrupt Control Logic

E.54

Scan LOogic

ESS

Modem Control (MUX) Logic

. . . . . .. . . .

OPERATIONAL PROGRAMMING

. . . . . . . o . oo

E.6
E.6.1

E.6.2

e e

e e.

E.53

. . . . . . ..o
. . . . ... . ... ... ..... e
e e

e e
e
e

. . . . o oo e

Maintenance Mode

e e

ettt

E.5.2

E.5.6

e e

. . . . . . .. . ..

. . . . . .. . ...

e e.
e

Control Status Register (CSR) (Address: 770XX0) . . .. ... ... ... ... ..
Line Status Register (LSR) (Address: 770XX2) . . . . . .. . . ... ... ...

e e e e e

e e e e e e e e

E.6.3

System AdAIesses

. . . . o e e

E.6.4

Interrupt VECtors

. . . . . . . . e

E.6.5
E.7

Timing Considerations

. . . . . . . . . . . . . ...

MAINTENANCE . . . .. ... ........... e
. . . . . . .

E.7.1

Introduction

E.7.2

Testing Configurations

...

E.7.2.1

Off LINE

. . . . o i i e e e e e e e e e

E.7.2.2

OnLine

. . . . . . .

APPENDIX F

. . . . . . . . . .. ...
e e e e e e e e e e e e

e e

MODEM TIMING AND FLOW DIAGRAMS

ILLUSTRATIONS
Figure No.
1-1

1-2
1-3
2-1

2-2

2-3
2-4

2-5

2-6

2-7
2-8

Title

e e
. . . . . . .« oo oo
DHI11 System Applications
e
e
e
e
e
e
oo
v
v
o
v
-« « o
DHITMUItIPIEXET

e e e e e e
e

. . . . . . . . . -« o o v e e e e e
Distribution Panel Module Utilization Diagram
e e e
Backplane to 7009561 Cable Interconnection . . . .. . oo v v v e
oo oo e e e
oo
o
.
.
.
.
.
.
.
.
Diagram
nection
Intercon
AC
DHI11-AA, AB, and
e e
DH11-AD and AE Interconnection Diagram . . . . . . . - . .« oo oo

e
e
n . . . . . . -« « o o oo
Diagram
DH11 Module Utilizatio
o
BCO8S-15 Cable Polarization Diagram . . . . .« « « o o oo o

. . . . ... oo

Strapping on H317B Distribution Panel

Cinch-Connector Strapping on H317B Distribution Panel

DH11-AD, AE Wire Location Diagram

. . . . .. .. oo v e

. . . . . . . .« oo oo e v

vii

E-1

Modem Control Block Diagram

. . . . . . .. . .

Modem Control Hardware Configuration
E-3

Scan Functional Block Diagram

E-4

Test Configurationwith H861

.. ...

. . . . . . .. .. ... ... ... .......

. . . . . .. . ... ... ... .. .. ... . ... ...

. . . . . . . .. . ... . ... .. ... . ... ... ..

E-5

Test Configuration, Distribution Panel and Test Connector

E-6

Test Configuration (ON LINE Modem Loop Back)

E-7

Test Configuration (ON LINE Modem to Terminal)

F-1

Data Set 103A Channel Establishment Sequence

. . . . . . . . ... .. ...

. . . .. ... ... ... ......
. . . ... ... . ... PP
. . . . . . . ... ... . ........

E-2

Data Set 103A Space Disconnect Sequence

F-3

Data Set 103F Timing Sequence

. . . . . . . . . ... ...

F-4

Data Set 103E Type Sequence Chart for a Call Originated in the

. . . . . . . . . .. .. ... ... ... .. ... ...,

Semiautomatic Manner and Answered Automatically

. . . .

Data Set 103E Type Detailed Disconnect Sequences

Establishment of

a202C Call

.. ... ... .. .. ...

. . . . . . .. .. .. ... ......

. . . . . . . . .. . . ...

Turn Around In Data-Phone Service 202C

. . . . . . . .. . .. ... . ... ... ...,

811B Originating and Answering Flow Chart for CPT for 3 or 4 Row

TWX Service Data Set Tone Detection without EON

. . . . .. ... .. ... ... ...

811B Originating and Answering Flow Chart for CPT for 3 or 4 Row
TWX Service Data Set Tone Detection with EON

. . . . .. ... ... .........

TABLES

Table No.

Title

4.1

Unibus Transactions for DHI1

4.2

DHI1 Register Address Sequence

4.3

Gating Control Signals

. . . ... ... ... .. .. ... .. ... ... .. ...
.......

.......

Clock Output Signals

4.5

. . . . . .. ... ... ... .
States of Status Flip-Flops E10 and E18

4-6

NRC Bit Identification

4.7

Line Parameter Register Components

4-8

Buffer Active Register Components

4.9

.......

. . . . . ... ... ... ... ...
..............

..............

Break Control Register Components

4-10

Silo Status Register Components

C-1

Integrated Circuits

--------------

..............

...

D-1

. . . . ... .. ...
UART Signal Functions

E-1

Glossary

..............

.......

E-2

..............

............

viii

INTRODUCTION
This manual provides the user with information concerning the installation, operation, and maintenance of the
DHI11 Asynchronous 16-Line Programmable Multiplexer.

Although signals are transferred between the DH11 and the PDP-11 Unibus, this manual does not provide detailed
information on the operation of the Unibus. A detailed discussion of the Unibus is contained in the PDP-11
Peripherals Handbook.

Five chapters and four appendices comprise this manual:
Chapter 1

General Description

Chapter 2

Installation

Chapter 3

Programming

Chapter 4

Detailed Description

Chapter 5

Maintenance

Appendix A

Floating Device and Vector Addresses for Communications Devices

Appendix B

PDP-11 Memory Organization and Addressing Conventions.

Appendix C

Integrated Circuit Descriptions

Appendix D

Universal Asynchronous Receiver Transmitter (UART)

Appendix E

DH11-AD Modem Control Interface

Appendix F

Modem Timing and Flow Diagrams

CHAPTER 1

GENERAL DESCRIPTION

INTRODUCTION

1.1

The DHI11 ASynchronous 16-Line Programmable Multiplexer connects the PDP-11 with 16 asynchronous serial
communications lines operating with individually programmable parameters. These parameters are:
-

Character Length: 5, 6,7, or 8 bit

Number of Stop Bits: 1 or 2 for 6, 7, 8 bit characters
1 or 1.5 for 5 bit characters

Parity Generation and Detection: odd, even, or none
Operating Mode: half duplex or full duplex

Transmitter Speed and Receiver Speed: 0, 50, 75, 110, 134.5, 150, 200, 300, 600,

1200, 1800, 2400, 4800 or 9600 Baud plus Ext A, Ext B
Breaks: May be detected or generated on each line.

The DH11 multiplexer uses 16 double-buffered MOS/LSI receivers to assembly the incoming characters. An
automatic scanner takes each received character and the line number and deposits that information in a first-in,
first-out buffer memory referred to as the silo. The bottom of the silo is a register which is addressable from the
Unibus.

The transmitter in the DH11 also uses double-buffered MOS/LSI units. They are loaded directly from message tables
in the PDP-11 memory by means of single-cycle direct memory transfers (NPR). The current addresses and byte
counts for each line’s message table are stored in semiconductor memories located in the DH11. This reduces the
Unibus time taken for the NPR transfers to one NPR cycle per character transmitted. The NPR cycle used is
lengthened slightly.

As many as 16 DH11s may be placed on a single PDP-11 processor, creating a total capacity of 256 lines. Figure 1-1
shows some typical DH11 system applications.

1.1.1

DH11-AA and -AC Line Interfaces

Four DM11-DAs are connected to a DH11-AA or AC. Each DM11-DA provides line conditioning for four serial

communications devices using 20 mA current loops. Such devices include a Teletype®, LA36 or VTOSA or B.

Four DM11-DBs are connected to a DH11-AA or AC. Each DM11-DB provides line conditioning for four

EIA/CCITT devices not requiring modem control.

®Teletype is a registered trademark of Teletype Corporation.

1-1

Four DM11-DCs are connected to a DM11-BB Modem Control which in turn is connected to a DH11-AA or AC.

Each DM11-DC provides line conditioning for four EIA/CCITT devices equipped with data set control.

1.1.2

DH11-AB Line Interfaces

A DCO8 Telegraph Line Interface is used with two DH11-ABs to provide line conditioning for 32 telegraph lines.
1.1.3

DHI11-AD and -AE Line Interfaces

The DH11-AD and -AE use the H317-B distribution panel which provides 16 EIA/CCITT lines for devices with or

without data set control.

1.2 PHYSICAL DESCRIPTION
1.2.1

Configurations

The DH11-AA multiplexer is available in four variations as shown in Figure 1-2:
The DHI1-AA consists of a double system unit, all modules necessary to implement a 16-line
asynchronous

multiplexer, a 5-1/4 inch level conversion and distribution panel with its own power supply,
and a data cable

between the logic in the double system unit and the level conversion/distribution panel. The
modules for level

conversion are not included,

so that the type and quantity of lines may be customized to the customer’s
requirements. The power supply for the distribution panel is also 5-1/4 inches high. Generally,
it can be mounted on

the rear of the rack in a position opposite the distribution panel, which is usually mounted on the

front of the rack.

The DH11-AB is the same as the DH11-AA, but does not include the level conversion/distribution
panel or its

associated power supply. Instead of a data cable to a distribution panel, a data cable to
the DCOSCS Telegraph

Converter Panel is supplied.

The DHI1-AC is the same as the DH11-AA, except that the power supply on the level conversion/dist
ribution panel
is arranged for 240V, 50 Hz operation. (There is no need for a 50 Hz version of the DH11-AB
because it is a
processor-powered option).

All of the above versions of the DH11 include pre-wired slots in the double system unit for
the insertion of a

DM11-BB Modem Control option.

The DH11-AD consists of a double system unit, all modules necessary to implement a 16-line
asynchronous
multiplexer, EIA level conversion for the data lines, modem control with EIA conversion, and a 16-line
EIA

distribution panel.

The DH11-AE is the same as the DH11-AD except the modem control is not included.
CAUTION
The DH11 uses hex modules and thus cannot be mounted in a

BA11 CS or ES Expander Box. The 11/35,11/40,11/45 type
boxes must be used (BA11-B, D, F series).

1.2.2

Multiplexer Distribution Panel and Power Supply

The DH11-AA and AC providea

panel for level converters and cables for the individual lines. The panel uses a

WS}

standard H911 style rack, but only 6 connector blocks are used.

UNIBUS

POP-11

IVMEMORY

]DH11-AB

DH11-AA OR AC

DH11-AD OR AE

DH11-AA ORAC

H317-B

DM11/DM11{DM11[DM11

DM11|{DM11|{DM11 [DMIN

DM11-BB

[T TTIT 110

TIT TTTT TTIT 177

DMI1|DM11/DM11/ DM

“DA

TIT

TT I TTIT 111

{-DA

|-DA

UP TO 16

CHANNELS

|-DB

- —— - - — — — — —in

- - -]- - — — ——~ -

M- —— =~ -

|-DB | -DB

-DB

UP TO 16

CHANNELS

-DC

TR
NULL

H312A
NULL

MODEM

|-DC | -DC

T T

e o 11VP 0200 .
|

MODEM

|-DC

UP TO 16

bcos

CHANNELS

TELEGRAPH
LINE

MODEM{ | \nNTERFACE

MODEM

———
e
UPTO16

)

CHANNELS

(ONE DHI11-AB USES

LINES AVAILABLE

LA 36

3
gsg

THE

DCO8)

VTOS5A

VTO5B

REMOTE

LOCAL

REMOTE

LA36

TERMINAL

LOCAL

TERMINAL

LA36

TERMINAL

REMOTE

VTOS5B

)

. TERMINAL
LA36

1-2335

Figure 1-1

DHI11 System Applications

DH11 MODULES
IN BACKPLANE

POWER

SUPPLY

DISTRIBUTION
PANEL

6581-3

Figure 1-2

DHI11 Multiplexer

IYEY4]
!

M971

CABLE®2[1CABLE

M9 71

M594

@2|1CABLE®2|1

2/1

LINEO8
THRU

[LINE 12
THRU

M594 | M594
=2t

2|t

M594 | M594 { M594
2|1

2{t

M394 | M594
2|t

M594

2|1

M594 | M594
20

2|1

M594
2t

]

MS94 | M594
2f1

2|1

M594 | M594

2]t

[

2|1

%x¥xkz2

|LINE OO JLINE O1]LINE 02 |LINE O3 |LINE O4|LINE O5 LINE OB|LINE O7LINE
O8|LINE O9|LINE 10 [LINE 11|LINE 12 |LINE 13|LINE 14 LINE 15 { LINEOS
|CONTROLICONTROL{CONT ROL [CONTROL [CONTROLICONTROUCONTROLICONTROL|
CONTROL CONTROL |CONTROLICONTROLICONTROL[CONTROLICONTROL |CONTROL|
THRU
LINE 11 |LINE 15 | LEADS | LEADS | LEADS | LEADS
LEADS | LEADS | LEADS | LEADS | LEADS | LEADS | LEADS | LEADS
|LEADS
LEADS
|LEADS
[LEADS
|LINE 1

MS71

M9 71

HEEE

M974

ICABLEes2li CABLE®2[1

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LINE15S

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2|1

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[

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O1 { LINEO2 | LINEO3 | LINEO4 [ LINEOS
THRU

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)
2|1

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O3 | LINEO7

k%2t

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UINEQ6 |LINEO7 | LINE OB LINEO9ILINE 10

|QUTPUT [OUTPUT |OUTPUT |OUTPUT GUTPUT|OUTPUT

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LINE12
THRU
LINE15

Kx¥ 21

|
LINE Q4
THRU
LINEO7

* LEVEL CONVERSION OF CONTROL LEADS. ONE SLOT PER LINE. JSE M594
ONéLY WHEN DM11-BB IS IMPLEMENTED.
IF DM11-DB IS USED REPLACE M594 WITH W404-A{SUPPLIED WITHDM11-DB)
. |F DM11-DA 1S USED LEAVE BLANK.

¥* USE

M594 FOR DM11-DB

¥%% USE M596

FOR

DM11- DA

® USE ONLY IF DM11-BB

IS IMPLEMENTED

e ¢ DATA CABLE FROM DHII-AA CONTROL LOGIC

A 16 CABLE SLOTS ONE PER LINE FORDMII-DA USE M973, FORDMN1-DB USE BCO1R—-25

A
A JUMPER CARD

USED FOR DIAGNOSTIC PROGRAMS ONLY, REMOVE FOR NORMAL
OPERATION
1-2206

Figure 1-3

Distribution Panel Module Utilization Diagram

The slot assignments follow the DF11 format which is the standard level conversion and cable slot for PDP-11

Communications Products (Figure 1-3). Slots A0O6 through A21 are used for level conversion modules. Slots B06
through B21 are used for cable termination. Other slots provide inputs or special purpose outputs. The distribution
panel mounts on a standard 19-inch cabinet and connects to the DH11 logic by means of a BCO8-S Data Cable.

Power for the distribution panel is provided by the H758 Power Supply mounted on the rear of the cabinet. Some
units in the field use H739 or H751 supplies which are generally equivalent to an H758 supply. The H758 provides
the voltages listed below:
+t15V@2A

-15V@2
A
+5V@4
A

Power drain of the distribution panel depends on the type of level conversion used. The maximum drain on the
+15V and -15 V occurs when DF11-BB modems are used, at which time the full rated output of a 2 A is used. The

maximum +5 V drain occurs when all lines are arranged for full modem control (four DM11-DC options); the
current used is then 1.7 A.
The level conversion types can be mixed on a 4-line basis by using different converters on slots A4, A5, B4, and BS.

Also, level converters can be mixed on a single line basis by using slots A6 through A21 for level conversion on a
single line basis. Consult Figure 1-3 for specific details.

The DH11-AD and AE options use a 16-line EIA distribution panel. This panel requires no power of its own. It
mounts in a standard 19 inch cabinet and connects to the DH11-AD and AE logic by means of two BCO8S data
cables and four BCOSR modem control cables.

BCO5D-25 cables may be ordered separately to connect from the EIA distribution panel to the modem.
1.2.3

General Specifications

Environmental:

Temperature: +50° F to +110° F
Humidity: O to 95 percent non condensing

Power Consumption:

The power consumption of the DH11-AA, AB, and AC logic
(excluding the level conversion modules, which run off the
level conversion/distribution panel power supply) is:

+5V:

8.4 A (DH11 alone)**

11.2 A (DH11 plus DM11-BB Modem Control)**

-15V:

240 mA

The power consumption of the DH11-AD and AE is:

DHii-AD
+5V:

10.8 A**

+15V:

400 mA

-15V:

645 mA

**Add 0.2 A if this is the last option on the Unibus.

(The Unibus terminator consumes 0.2 A)

1-5

DHI11-AE
+5V:

8.6 A**

+15 V:

100 mA

-15V:

340 mA

**Add 0.2 A if this is the last option on the Unibus.
(The Unibus terminator consumes 0.2 A)

Receivers:

The DHI1 receiver units provide serial to parallel conversion
of 5, 6,7, or 8 bit code with one start bit and at least one stop
bit.

An extra data bit is added

selected.

The

allowable

input

when parity operation is

distortion is 43.75 percent

assuming no speed distortion. The maximum allowable speed

distortion is 4.8 percent for 8-bit characters.
The

DHII1

transmitter

units

provide

parallel

serial

conversion of 5, 6, 7, or 8 bit code with one start bit and one,

one and a half (5 bit only), or two (6, 7, or 8 bit only) stop

units. An extra data bit is added if parity operation is selected.
The number of bits per character, the number of stop marks,
and parity mode are selectable on a per-line basis, but must be

the same as the corresponding receiver. The serial data rate is
determined by a crystal clock and is program controllable on a
per-line

basis.

controlled

The

transmitter

independently

the

speeds

may

receiver speeds.

program
Output

distortion is less than 2 percent.

Interface:

Interface to and from the control section. There are 16 output
data lines and 16 input data lines at TTL levels using negative

logic (mark = 0).
The input leads from the level conversion/distribution panel
are equipped with pull up resistors which place lines not
equipped

with level

conversion in a permanently spacing

condition. Logic in the DHI1 receivers prevents this condition
from

assembling

Bus Loading:

null

characters

continuous

basis,

however.

The DH11 presents two bus loads to the Unibus. If a Modem
Control is added, an additional bus load is added.

1-6

1.3

FUNCTIONAL DESCRIPTION

1.3.1

Receiver Operation

Reception on each line is by means of Universal Asynchronous Receiver/Transmitters (UARTSs). These are 40-pin
MOS/LSI devices that perform all the necessary functions for double-buffered asynchronous character assembly.
The receiver section of the UART samples the line at 16 times the bit rate of the signals to be received on that line.
Upon detection of a mark-to-space transition, the UART counts 8 clock pulses and checks the state of the line again.
This sampling occurs in the center of a normal start bit. If that sample is a mark, the receiver returns to its idling
state, ready to detect another mark-to-space transition. If the sample is a space, the receiver entersthe data entry

condition and samples the state of the line at subsequent sample points spaced at multiples of 16 clock ticks from
the center of the start bit. The number of samples taken is determined by the character length information entered
into the UART via the Line Parameter Register. If parity checking has been enabled for this line, the receiver
computes the parity of the character just received and compares it with the parity sense specified for reception on
that line. If the parity sense differs, the parity error bit is set.

The character length, parity sense, number of stop bits, etc., that are used by the UART to perform the above
operations, are stored within each UART in a Control Bits Holding Register. The Control Bits Holding Registers of
each UART are addressable, on a write-only basis, from the Unibus, by first setting the line selection bits of the

System Control Register and then loading the desired line parameters into the Line Parameter Register, from which

they are automatically transferred to the Control Bits Holding Register of the designated UART. It is important that
no interrupt handling routine intervene and change the contents of the System Control Register during the above
operation.

1.3.2

Silo Operation

The silo is an MOS/LSI digital storage buffer that is 16 bits wide and 64 words deep. A 16-bit word is entered at the
top and automatically bubbles down to the lowest location that does not already contain an entry. The bottom of
the silo is the Next Received Character Register (NRC).

There are three registers associated with the silo. One is the Next Received Character Register. It is a read-once

register because it is the bottom of the silo, and reading it extracts that character from the silo and causes all other
entries to bubble down one more position.

The other two registers are byte-size registers and are contained within the Silo Status Register. Oneis the high byte,
which is read-only and contains the status of an up-down counter, giving the actual fill level of the silo. The second
register, the low byte, is read/write and is used by the program to specify that silo fill level beyond which the
program wishes to receive interrupt notification.

| 1.3.3 Transmitter Operation

In the transmit mode, the program picks the desired line and selects the transmitter operating parameters. The
program then loads the Current Address Register (CAR) with the memory address of the first character to be
transmitted on the selected line. It also loads the Byte Count Register (BC) with the number of characters in the
message and sets the bit of the Buffer Active Register (BAR) associated with the selected line. When the transmitter
scanner finds a Transmitter Buffer Empty (TBMT) flag high for the selected line, it stops and a character is
transferred from memory to the UART for transmission.

Transmission on each line is by means of UARTs that perform all the necessary functions for double-buffered
asynchronous character transmission. The transmitter section of the UART holds the serial output line at a marking
state when idle. When the transmitter loading leads have been conditioned with the character to be transmitted and

the data strobe lead has been brought high (these functions are performed by the NPR control), the UART
commences generation of a start space within one sixteenth of a bit time. The start space and all subsequent data
bits are a full bit time each. The start space is followed by M data bits, where M is 5, 6, 7, or 8, as determined by the

1-7

Control Bits Holding Register. The data bits are presented to the line least significant bit first.
The parity bit, if

parity generation is enabled, is calculated by the transmitter and affixed after the last data

marks.

bit, but before the stop

The stop bit or bits depend in quantity upon the setting of the control word. If the transmission of 6, 7, or 8 bits
has
been selected, the program may select either one or two stop bits. If the transmission of 5 bit code has
been selected,
the program may select either one or one and a half stop bits.

If the transmitter’s holding register has been loaded while a character was being transmitted, the second character

has its start bit commence immediately at the end of the preceding character’s stop bit(s).

1.3.4

Auto-Echo Operation

The DHII contains provision for the hardware to echo received characters without software
intervention. The
feature may be enabled on any line by conditioning the line selection bits in the System Control
Register and then

setting the appropriate bits in the Line Parameter Register, including bit 15 (Auto Echo

Enable).

The auto-echo hardware is part of the receiver scanner and operates as follows:
a.

If the receiver scanner finds a received character for a line upon which auto-echo is
not enabled, it
simply dumps that character into the silo and resumes scanning.
If the receiver scanner finds a received character for a line upon which auto-echo is enabled, it examines

the error flags associated with that character.

If a framing error is detected, the remote terminal is trying to gain the attention of the

processor by sending a break. In this case, the auto-echo hardware dumps the
received

character and associated flag into the silo so that the system software is alerted. The break is
not echoed to the remote terminal.

If an overrun error is detected, the remote terminal is trying to gain the attention of the
processor by typing characters. This case is treated identically to b1, above.

If the receiver scanner finds a received character from a line upon which auto-echo is enabled and

there

are no error flags of the type mentioned above, the receiver scanner and auto-echo
logic attempts to

echo the character. First, however, certain tests of internal logic conditions must be made.
1.

The UART transmitters are all loaded from a common internal data bus.
Therefore, the
auto-echo hardware must first check to see that no NPR cycles are in progress, loading
a
UART transmitter from that bus. If a conflict is indicated, the receiver scanner is restarted

and the process is tried again on the scanner’s next rotation.

If the above test indicates no problem, the one remaining check is to see if the Transmitter

Holding Register for the line upon which the character was received is available. If it is
not,
the scanner is restarted. If it is available, auto-echo commences.
It is not advisable to transmit messages on a line and auto-echo characters received
on that line
simultaneously. It is not possible to receive characters on a line at 30 characters per second,
echo them

back by auto-echo at 30 characters per second, and transmit an independent message at 30 characters
per second, all on the same line. The auto-echo hardware will interlock these functions to

some degree,

but if more than two characters are received on a line while the scanner is waiting for the transmitter

holding buffer to become available, a data overrun occurs and characters are lost.
Auto-echo and
software-driven transmission should not be attempted on the same line simultaneousl
y, if input from

that line is expected.

1-8

1.3.5

Interrupts

1.3.5.1 Receiver Interrupts — There are two kinds of receiver interrupts; they are enabled by bits 6 and 12 of the
System Control Register.

Receiver Interrupt (System Control Register bit 7) — This interrupt, when enabled, occurs whenever the number of
entries in the silo exceeds the silo status alarm level that the program has stored in the low byte of the Silo Status
Register and SCR bit 6 is set. (The program can examine actual silo fill at any time by examining the high byte of
:

the Silo Status Register.)

Storage Overflow Interrupt (System Control Register bit 14) — This interrupt, when enabled, occurs when the
character storage silo is full and the DH11 hardware needs to store an additional character and SCR bit 12 is set.
Should this situation occur, it does not necessarily mean that data has been lost.

1.3.5.2 Transmitter Interrupts — There are two kinds of transmitter interrupt; both are enabled by bit 13 of the
System Control Register.

Transmitter Interrupt (System Control Register bit 15) — This interrupt, if enabled, occurs whenever one or more

lines have finished the transmission of a complete string of characters. Specifically, it occurs after the NPR cycle that
to be transmitted (and hence incremented the byte count to 0).
loaded the last character
Non-Existent Memory Interrupts (System Control Register bit 10) — This interrupt, when enabled, occurs whenever
the DH11 addresses non-existent memory. Specifically, this interrupt occurs if the DHI1 enters an NPR cycle, places
an address on the Unibus, and fails to receive a slave sync response for the location addressed within 20 us.

1-9

CHAPTER 2
INSTALLATION

This chapter provides information for installing and testing a DH11. The information is given in procedural steps.
After unpacking, check that all parts are present for the particular configuration listed below.
List A

7009180 Wired Backplane Assembly
7009561 Power Harness

G727 Grant Continuity Card

BR 5 Jumpers (5408778)
M7821 Interrupt Control Modules

'M796 Unibus Master Control Module
M4540 Crystal Clock Module

M7277 Current Address and Address Selection Module
M7278 Registers and Byte Control Module
M7279 FIFO Buffer Module
M7280 Multiple UART Cards
M7288 Line Parameter Control Module

M7289 System Control and Receiver Scanner Module

.—lj—l)—l)—AN

List B
M971 Cable Card (type BCO8SR)
BCO08S Cable

7008456 Distribution Panel (7008443 Logic with End Panels)
7008493 Power Harness

H758A or H739A Power Supply

O T N )

H315 Test Connector

BCO8S Cables

List C

H8611 Test Connectors

M5906 Priority and EIA Conversion Module
H317B EIA Distribution Panel (5410260 EIA Distribution Panel, 7410667-2 Cover,

two 7410668 Cable Clamps, and a 7410666 Mounting Plate)

DH11-AA: The items in lists A and B, one G7360 Priority Selector Card, and one M974 Maintenance
Board.

2-1

DH11-AB: The items in list A, one G7360 Priority Selector Card, one M974 Maintenance Board,
and a

7008423 (M972 to dual W077) Cable.

’

DH11-AC: The items listed for the DH11-AA, but with an H758B or H739B (220 V) Power Supply
substituted for the H758A or H739A Power Supply shown in list B. The DH11-AC is the 220 V version

of the DH11-AA.

DH11-AD: The items in lists A and C, one M7807 Mux and Bus Control Module, one M7808 Mux and

Scan Control Module, and a H861 Test Connector (Modem Control).

DH11-AE: The items in lists A and C.
In addition to the material mentioned above, the following items should be included.

For each DM11DA ordered:

MS596 TTL to 20 mA Level Converter

M973 Mate-N-Lok Cards

For.each DM11DB ordered:
1

M594 TTL to EIA Level Converter

BCOIR Cable Assembly

W404 DTR Jumper Card

For each DM11DC ordered:
4

M594 TTL to EIA Level Converter

BCO1R Cable Assembly

Refer to the unit assembly drawing (D-UA-DH11-0-0) in the DH11 Print Set. Install the DH11 9-slot
double system unit containing the wired logic in a convenient spot in the expander box or processor

box. With all power off, install the 7009561 Power Harness, being very careful to install the Faston

connectors on their respective tabs without catching against or cutting any of the nearby backplane
wiring. In early units, the long axis of the tabs is in line with the long axis of the double system unit. In

this case, the power tabs must be bent so that they clear both the pins of the wired logic and the power

supply regulators. The proper connections are listed on the backplane etch and their relative positions
are shown in Figure 2-1. The DH11 interconnection diagrams are shown in Figures 2-2 and 2-3. When

using the backplane with tabs whose long axis is perpendicular to the long axis of the system unit, the

7009561 Power Harness is used without alteration.

Secure the ground wire from FO2T1 to one of the mounting screws. Do not plug in the white connector

of the 7009561 until step 9.

AcLom
DCL

O
M

158

GND B

+5
1B

+15
8
+5 1

11-2204

Figure 2-1

Backplane to 7009561 Cable Interconnection
2-2

OUTPUT CABLES ARE EITHER BCO1R-25 FOR EIA OR M973

MATE-N-LOCK

CONNECTOR CARD FOR PDP-11 TTY.
NOTE: NEITHER ITEM SUPPLIED WITH DHI11-AA,

‘Bos

B21

_
7008423

AC DATA CABLE
DH11-AA,

DM11 DISTRIBUTION PANEL
WIRED

DCO8-CS

TELEGRAPH

DH11-AB DATA CABLE

16 OUTPUT CABLES

LINE SYSTEM
OPTION

BC08S-15

(NOTE 2)

ASSY

D-AD-7008443-0-0

GND +5 -15 +15

(NOTE 1)

* DM11 CONTROL CABLE:

NOTE: USE ONLY WHEN
-BB IS IMPLEMENTED
DM11-BB

|PowER HARNESS
008493

BO7

———

I (W

PDP11 OR BA11

GND +5 -15 +15

EXTENSION BOX THAT
CONTAINS THE DH1!

H758-A POWER SUPPLY 115V
OR

CONTROL LOGIC WIRED

ASSY-D-AD-7009180-0-0

H758-B POWER SUPPLY 230V
Il

(NOTE 1)

NOTES:
1.

Distribution panel 7008443 and power supply
H758 provided only with CH11-AA or DH11-AC.

DCO8 CS must be ordered separately. DH11-AB

data cable plugs into slots A31, A32 of DC08 CS

for lines 00 to line 15. A second DH11-AB plugs
into the DCO8
CS at slots B31, B32 for lines 16

TO SWITCHED
AC POWER

to 31.

11-2195

Figure 2-2 DHI11-AA, AB, and AC Interconnection Diagram
BCO5D OUTPUT CABLES
4

JOO

Jis

J20

DHII-AD and AE DATA CABLE BCO8S-15

Ji7
J16
EIA

DISTRIBUTION PANEL | V'8
D-CS-5410260 -0-1 | J19
J21

CONTROL
MODEM
M Le BCOBR
USED
ONLY WHEN DH11- AD

IS IMPLEMENTED

J2 | J1

M7807 !

M7808 l

M5906

PDP-11 OR BA!1 EXTENSION BOX
THAT CONTAINS THE DHI11
CONTROL LOGIC WIRED ASSY
D-AD-7009180-0-0
-

AC POWER CORD
OR
PDP -11

POWER LINE
11-2893

Figure 2-3 DH11-AD and AE Interconnection Diagram
2-3

Install the modules in their proper locations according to the module
utilization list (D-MU-DH11-3-0).
Figure 2-4 is the module utilization diagram. It is helpful to
place the Unibus connectors, Unibus

terminator (if used as last unit), and any modules with cables

attached first. Beware of the tendency of

hex modules to bow in the middle and for hex module extractor
handles to catch on adjacent
conventional handles.

Be sure that the G7360 or M5906 card has both priority plugs in

place. BRS is standard for the DH11.

The DH11 uses floating addresses and is located after the DJ11s in the
floating address space that begins
at location 160010. Because the DH11 has eight registers, it must
be assigned an address that is a
multiple of 20 (octal). All DH11s in a system should have consecutiv
e addresses.
Example 1: A system with no DJ11s, but two DH1 Is:

160010 Cannot use for DH11s because not multiple of 20

160020 First DH11

160040 Second DH11

160060 DH11 Gap (indicates that there are no more DH1 1s).

Example 2: A system with one DJ11, two DH11s:
160010 First DJ11
160020 DJ11 Gap (indicates that there are no more DJ11s).

160030 Cannot use for DH11s because not a multiple of 20.

160040 First DH11

160060 Second DH11

160100 DH11 Gap (indicates that there are no more DH1 Is).
The DH11 vectors (2) follow those of the DJ11 in the floating

vector space that starts at address 300.
The vectors starting at 300 are used in the following order: DC11;
KL11/DL1 1-A,B; DP11; DM11-A;
DN11; DM11-BB; DR11-A; DR11-C; PA611 Readers; PA611 Punches;
DT11; DX11; DL11-C,D,E;
DJ11;DHI11.

Of the two vectors, the receiver vector is the lower numbered vector.

The priority of the receiver and

transmitter interrupts are individually selectable by means
of two standard PDP-11 priority jumper

plugs. If both are the same, the receiver has interrupt priority because
it is electrically closer to the

processor.

If one or more DM11-BB options are ordered with the DH11s in a system,
the DM11-BBs and associated
DM11-DCs should be installed in the DH11s that have the lowest addresses
(i.e., DH11-AA and ACs).
The DH11s should be in order of increasing address as follows:

DHI1ls with DM11-BB and full complement of DM11-DCs

DHI11-ADs

DHIls with DM11-BB and a partial complement of DM11-DCs

DH11s without modem control, but EIA conversion for data lines only (DM11-BBs or

DH11-AEs)

sLoT
1

M920

M7821

M7278

M7277

M7289

M7821

M7360

M7288

M920

CABLE

ROW

UNIBUS

A | CONNECTOR|

(NOTE #3)

CABLE

NPR

CNTL

REG &

| CURRENT | SYSTEM | INTRCNTL|

|BYTE CNT | ADDRS & | CNTL &

ADDRS

SELECT

| RCV SCAN

M405

M796

PRIORITY

LINE

(NOTE #9)

CNTL

UNIBUS

SELECTOR | PARAMETER | CONNECTOR

(NOTES#1

& #2)

M9 71
CABLE

UNIBUS

EXTERNAL |DATA CABLE

CNTL

(NOTE #5) | & # 9)

MASTER

M7247

C | CONTROL | CONTROL

B CLOCK

[(NOTES#6

M7280

MULTIPLE | MULTIPLE

MUX LINES |MUX LINES
8-15
0-7
(NOTE #7) | (NOTE #8)

UART
LINES
0-7

UART
LINES
8-15

M7279

FIFO
BUFFER

M105

M7246

¥*

M405

e | ADDRESs | coNTROL
SELECTOR|
SCAN

EXTERNAL
A CLOCK

(NOTE #7) | (NOTES#4

(NOTE #5)

8# 8)

M782]

M4540

INTR CNTL

DH11 DCH

F | (NOTE#7)

CLOCK

VIEW

FROM WIRING

SIDE

NOTES:
1.
2.

11-2194
f end of bus, replace M920 with M930.

Module slots provide for additional clock rates.

1f last unit in basic box, replace M920 with BC11A

For diagnostic checkout of DH11-AA, AB,

cable when expanding to peripheral box.

or AC, replaces M971 with M974.

if first unit in expander box, replace M920 with

This slot contains Modem Control Module

BC11A cable.

M7807 with DH11-AD.

E02 must be G727 grant continuity if modem con-

This slot contains Modemn Control Module

trol module set is not installed. * denotes DM11-B8

M7808 with DH11-AD.

modem control option, with DH11-AA or AC.

This slot contains EIA Converter and Priority
Module M5906 for DH11-AD or AE.

Figure 2-4

DH11 Module Utilization Diagram

2-5

DH11s with EIA and 20 mA mixed

DH11s with 20 mA only

The above order is preferred for RSTS systems.
If the customer has other desires, he is the final
authority.
The DH11 requires two M7821 modules. One of these modules (A06) is used to generate interrupts and
must have its vector bit jumpers cut to provide the selected vector address.

Both sections of the M7821 are set to the same priority level (BRS) and each one generates an interrupt.
Section A is used for receiver interrupts which assert the vector addresses of the form XX0, Section B is
used for transmitter interrupts which assert vector addresses of the form XX4. To accomplish this, the

bit 2 jumper must be left in. (If a DM11-BB is installed, its M7821 module (slot FO1) must have the bit 2
jumper cut.) The other jumpers (bits 3—8) are cut as shown below to select the desired vector address.
The jumper for vector bit 2 (W2) on the M7807 module must be out.

Jumper

Vector

Address

1 X

300

X i X

310
X

320

330

| X

340

350
X

360

370
X1

XXX

| X!

| X

400
410

420
430

440
450

X | X

460
470

X | X

500

520

510

530

X | X

540

550

NOTES:

560
570

1. X means remove jumper (cut)
2. Cut only the jumpers shown. Leave

the NPR jumper installed.

2-6

- 8.

The M7277 module, located in slot 04, contains the address selection logic. The following jumper cut

table indicates which jumpers should be cut to get the addresses indicated.

Jumper
8

Device
5

None

Address

160000

160020

160040

X | X

160060

160120

160100

X
X

160140

|X | X

160160

160200

X | X

160220

160240
160260

| X

160300

160340

(X | X

160360

160420

160320

160400

160440
| X

160460

160520

160500

| X

1 X

I'X

160540
| X

160560
160600

160620

| X

160660

160640

160700
X

I X

160720
160740

| X

160760

NOTE: X means remove jumper (cut).

The numbers identifying the jumpers are located on the M7277 etch right underneath the jumpers. In

the set of five jumpers located near the center of the board, the order from top to bottom
is: 8-11-12-10-9. In the set of four jumpers located near the edge of the board, the order from top to
bottom is: 7-4-5-6.

2-7

Measure the resistance between the following pins on the backplane with the white plugs of the 7009561

cable hanging free (not plugged in):
+5 V to GND must be 0.4 ohm to 10 ohms

-15 V to GND must be 50 ohms to 500 ohms

+15 V to GND must be 50 ohms to 500 ohms
If the resistance is less than the lower limit indicated, check for a short. If the resistance exceeds the high
limit, it may indicate an open circuit. Measure the resistance using the X1 scale. For the first
measurement, place the red (+) probe on the +5 V terminal and the (-) lead on the GND terminal. In the
second measurement, place the red (+) probe on the -15 V terminal and the black (-) lead on the GND
terminal. For the third measurement, place the red (+) probe on the +15 V terminal and the black (-)

lead on the GND terminal. If the above resistances are OK, connect the white plugs in accordance with
D-UA-DH11-0-0.

10.

Install the 7008456 Distribution Panel as indicated in D-UA-DH11-0-0 for the DH11-AA or AC. Be sure
to install the module restraining bar across the back to hold the modules in case of cable strain. If
installing a DH11-AD or AE panel, go to step 14.
-

11.

Install the H758 or H739 Power Supply as shown in D-UA-DH11-0-0. Make sure the toggle switch is in
the OFF position. Check the fuse with an chmmeter. Plug the power plug into the receptacle strip on

the cabinet or other processor switched outlet. Position the 7008493 Power Harness by running it up to

the top of the cabinet, forward, then down to the distribution panel terminals. It is necessary to gain
side access to do this. Mount the H758 on the rack. Do not mount the H758 on the door; you will be

unable to close the door. The H739 can be mounted on the doer: Be careful that the Faston tabs on the

end of the distribution panel do not touch the frame.

12.

Install an M971 cable module at each end of the BCO8S cable and install the M971s thus equipped in the
locations

indicated in the D-MU-DH11-0-3 module utilization for the basic logic and in the
D-MU-DM11-A-3 module utilization for the distribution panel. These are locations BO7 in the DH11 and

BO1 in the distribution panel.

Install the M974 Maintenance Card in location B0O3 of the distribution panel. Be sure to remove it before
starting the on-line tests. If installing the DH11-AA, AB, or AC, go to step 19.
14.

For

DHI11-AD

and

AEs, install

the

H317-B

EIA

distribution

panel

assembly

as indicated in

D-UA-DH11-0-0.
15.

For DH11-AD or AE installation, refer to Figure 2-3 for cable interconnections and to Figure 2-5 for
proper insertion of the BCO8S cables. These cables connect the data lines to the distribution panel and

should not be installed until after all the off-line tests have run. The M5906 module should have H8611
test connectors in plugs J1 and J2.

CAUTION

Cables are neither marked nor keyed and if improperly
connected can damage equipment. On the H317, the

rib

side of the cable must be away from the board. On the

M5906 the smooth side of the cable must be away from

the board.

16.

The H317-B EIA Distribution Panel provides for

several jumper selections (Figures 2-6 and 2-7). The
DTR and REQUEST TO SEND leads (Figure 2-6) are
normally strapped to a positive ON voltage for the
DH11-AE. This strapping must be removed for lines
that use a full modem control arrangement in which
the modem control signals are combined with the data
signals on the distribution panel. This is the case
when modem control is used with the DH11-AD.
:

2-8

DISTRIBUTION

PANEL

&
UNMARKED BERG

RIB SIDE

UpP

:
BCO8S-15

CABLE

NOTE:

This applies to both BCO8S-15
cables on all options.

SMOOTH
SIDE UP

UNMARKED BERG
-

OUTPUT BOARD
11-1809

Figure 2-5

BCO08S-15 Cable Polarization Diagram

H317B

J16

I‘

s (CCCCEC
LEFT-HAND END|

I‘

J18

Il,us

€ QCCCCCEC

CCCCCeC

J20

LINE [S1G

LINE|SIG

[DTR

|RTS

[DTR

|RTS

[RTS

|RTS

|DTR

|RTS

{DTR

|DTR

|RTS

|DTR

|RTS

|DTR

|RTS

|DTR

|RTS

10 [DTR

[RTS

|DTR

15_|DTR

|RTS

6 |DTR

€ CCCeeee

LINE| SIG

|DTR

J21

|RTS

14 |DTR| RIGHT-HAND
END

11-18]0

Figure 2-6

Strapping on H317B Distribution Panel

MODEM

CINCH
CONNECTOR

103A

CASES

103F

| 300 BAUD FULL DUP

1134

| 300B8AUD

NOTE:
In special cases, any given signal from
the

MODEM should be put on whatever pin

represents

that signal on the DJ1l dist.

panel with jumpers

1,2,3, or 4.

MODEM schematic and compare

Check
it

with

this figure.

|||

1/2 DUP

%|%]|%

TWX

%)%

EIA

| RS232-C

(SEE BELOW)

[ouT IN|

JUMPERS

PIN 11 TO

PIN 12 TO 16

JUMPERS

MODEM

REQ

SEC TRANS DATA

TO SEND

} BELL

| SEC REC'D DATA

202

TRANS

IN fout]

12 TO 17

SIGNAL

|SEC

[IN

PIN 25 TO
4

JUMPERS

PIN NO.

| LOW SPEED

JUMPERS

IN|

ORIGINATE
0%

811B

CARE

*| %

300 BAUD FULL DUP

202C,D | 1800 BAUD

% DON'T

1121314

| 300 BAUD FULL DUP

103E,6,H|

BELL 0R<
EQUIV

JUMPERS

DESCRIPTION

TYPE

DATA

| SEC REC'D DATA

| RESTRAINT

| BUSY

E1A

8118

103E,G,H
1-181

Figure 2-7
17.

Cinch-Connector Strapping on H317B Distribution Panel

The customer may implement the following options when installing the modem control into the
DH11-AD.

A null modem (H312A) may be connected to a line.
Bus initialization of the modem control modules (M7807 and M7808) can be inhibited by
removing DH11 backpanel wire FO2B2 to ground.
Interrupts for all lines may be inhibited for CARRIER, RING, SEC RX, or CLEAR TO SEND by
removing the wires listed below:
DH11 Wire Removed

Status

E02A1 to D02B1

CARRIER
RING

E02C1 to DO2F2

SEC RX

E02B1 to D0O2A1

CLEAR TO SEND

E02D1 to D02C1

2-10

18.

Figure 2-8 is a wire location diagram for the DH11-AD, AE to assist in the troubleshooting of individual

lines up to the outputs on the distribution panel.

19.

Turn on the power. Toggle in the Bootstrap and load the Absolute Loader, if not already done. The
addresses and contents of the Bootstrap Loader are listed below.

Address

Contents

NOTE

—744

016 701

Memory size determines the

—746

000 026

first three digits

~750

012

—752

000 352

017 for

037 for

=754

702

005

211

057 for 12K

—756

105 711

077 for 16K

-760

100 376

117 for 20K

137 for 24K
157 for 28K

—762

116162

—764

000 002

-770

005 267

—766

—

400

—772

177 756

—774

000 765

—776

177 560 (keyboard)
or

177 550 (high speed reader)

20.

Run the diagnostics in accordance with the instructions contained therein. Helpful information may be
found in the DH11 Module Test Procedure, A-SP-DH11-0-11. One course of action not mentioned in the
procedure is worthy of attention: if a diagnostic does not run, try a couple of other diagnostics before
assuming that the diagnostic tape is no good. If both DZDHG and DZDHH run, the DH11 is operational;
however, all diagnostics are important and should be run.

21.

Run the On-Line Test, DZDHJ, in accordance with the instructions therein. Be sure to remove the M974
from the distribution panel.

DH1I

m7807
.

GROUND {

CABLE

DISTRIBUTION PANEL

M7808

116/218

DH11
M5906

419/J21 | CONNECTION PINS

17/420 | BCO8S

-4 A

| A

B{B

|[B

wul

OUTPUTS

ojp

TT{

JooTOJO7

FIF

ss|ss

mR|

J08 TO J15

«klk

[Mm

31742

4 E

- F

- H

FlF

H |H

pepipP

mM|

oMM

sis

uvlu

viv

NN| NN NN
MM

~ NN

PPlPP

- RR

RRIRR

| E

L7 —¢>—1
{SIGGND)

RING

CABLE

| EIA OUTPUT

sz
] 8coeR

LINES

CARRIER4

045812

cTs

SECTX

- W

wiw

SECRX

RTS

DTR

- M

eplp

(PWR GND}

zfz

[BB

|BBE

oo|pp

bbb

|pD

|—

| K

b—22

88|

|—8

EE|EE

|EE

|!s

op|

bbb

|—s5

HH|HH

[HH

2!z

[—11—€ >—1a

KK KK|KK

|KK

x !l x

«x

»—12|:::t16

MM MMM

PPIPP

[—

FF|

FF [—a I:::::E

U sk RR|RR

|RR

—

GROUND

W, FF) | (W.FE} | (W, FF} —TX DATA g’m FF - LINES 4, 12

b—20——

a.L

PIN W — LINES 0,8

ja,u

(A, L)

—RX DATA /PIN A — LINES
0, 8

PIN L — LINES 4, 12

RING

AA | AA

LINES

CARRIER-]

KK|KK

159,13

cTS

< HH

j—8

HH{HH

N | N

+—5
}—11e—gd>—1a

SEC TX

wiuw

| B

SEC RX

ss|ss

bp|{D

|—a

OTR

-~ CC

cctcec

26 ———0

o——

PINY -~ LINES 1,9

(Y, J}

(Y, JJ}

{y, a3

—TX DATA { PIN JJ — LINES 5, 13

C,N)

{C, N}

—RX DATA

/PINC — LINES 1,9

PINN — LINES 5, 13
L

p}—22

LINES

CARRIER— V

RING

AA|

+—38

2,6,10,14

cTS

cc|{

}—s

SECTX

—11—
14

SECRX

RTS

EE | EE

—4E2

DTR

< N

HH|

|—20——¢
>
¢

PIN AA — LINES 2, 10

{AALL)

[{AA, LL)

(AA, LL)

—TX DATA ( PINLL — LINES 6, 14

(E, R)

(E, R}

{E,R)

—RX DATA { PINE
— LINES 2, 10
PINR — LINES 6, 14

RING

|BB
L

| U

[—22
}—8

LINES

CARRIERS

| K

3,7,11,15

cTs

—4

|—s

SECTX

o TT

TT|TT

l¢c

F—1n—6 v>—12a

SEC RX

~ VV

VWiV

| A

——12Ex16

RTS

4 FF

FFElFF

{ P

DTR

4 op

DD | DD S

—4-‘j:—zs

RTS COMMON (E+)

$ —20—<b
2

—{

T ot oTToTT T OTT J-DTR COMMON {E+)
SS SS[ SS ss| s§ ss—-[

[CCNN) | (CCNN) | (CCNN} —TX DATA {PIN CC - LINES 3, 11
PIN NN — LINES 7, 15

H,T)

(H,
T}

—RXDATA({

PINH
— LINES 3, 11

M7807 — LINES 8 TO 15:

J1-8T0 11;42-12T0 15

M7808 —~ LINESOTO 7:

J1-07T0 3; J2-4TO
7

DISTRIBUTION PANEL 16 LINES!

NOTES:

PIN T — LINES 7,15

M5906 (16 DATA LINES)

J16-0TO3

J19-8TO 11

J21-12To1s )

CONTROL

J17-0707

J20-8TO15

DATA

418-4T07

—

J1-8TO 15;J2-0TO 7
11-2922

Figure 2-8

DH11-AD, AE Wire Location Diagram

2-12

CHAPTER 3

PROGRAMMING

3.1

INTRODUCTION

This chapter contains general DHI1 programming information. It is divided into two sections; one lists the bit
assignments and functions of the eight registers and the other discusses several DH11 operational features and
programming constraints.

3.2
3.2.1

The System Control Register is a byte-addressable register. The register format is shown in Figure 3-1.

STORAGE

NON-EX

|CLEAR NON-EX|

—

J\.

MEMORY
EXTENSION

RECEIVER

LINE
SELECTION

INTERRUPT l INTERRUPT | MEMORY | MEM INTER |INTER ENABLE
TRANSMITTER

INTERRUPT

ENABLE

TRANS &

NON-EX

MEM INTER

MASTER

CLEAR

MAINTENANCE

RECEIVER

INTERRUPT
11-2199

Figure 3-1

System Control Register Format

Bit

Function

00, 01, 02, 03

Line Selection — Each of the 16 lines served by the DHI11 has

its own storage for line parameter information, current

address, and byte count. These storage locations are loaded by
the program via the Line Parameter Register, Current Address
Register, and Byte Count Register, but the hardware must first
be told which line is to have its line parameters, current

address, or byte count changed. This routine is accomplished

by setting the line selection bits. These bits are read/write.

3-1

Bit
04, 05

Function

Memory Extension — The information stored in these bits
becomes bits 16 and 17, respectively, of any current address

loaded by the program into the Current Address Register.
These bits are read/write, but when read, represent only the
status of bits 4 and 5 of we System Control Register, not the

status of the 16th and 17th address bits of the selected line.

(See Paragraph 3.2.8 for further information.) The reason for
this arrangement is to permit interrupt service routines to save

the contents of the System Control Register accurately.
06

Receiver

Interrupt

Enable

—

This bit, when set, enables

receiver interrupts (bit 07).

Receiver Interrupt — This bit, when set, indicates that the
number of characters stored in the silo exceeds the alarm level
specified by the low byte of the Silo Status Register. This bit
is

read

only,

except

maintenance

mode,

when

read/write. When set, this bit generates an interrupt if bit 06 is
also set.

Clear Non-Existent Memory Interrupt — This bit, when set,
clears the non-existent memory interrupt flip-flop (bit 10) and
clears itself. This bit is read/write.

Maintenance (Read/Write) — This bit, when set, places the
DHI1 in maintenance mode.

Non-Existent Memory — This bit is set whenever the NPR
hardware within the DH11 addresses a memory location from

which no slave sync signal is received within 20 us. This
indicates that the addressed location or device does not exist.

This bit causes an interrupt if bit 13 is set also. This bit is
read-only, unless in maintenance mode, at which time it is

read/write.

Master Clear — This bit, when set, generates the initialize
condition within the DH11, clearing the silo, UARTS, and
registers. This bit is read/write.

Storage Interrupt Enable — This bit, when set, permits the
setting

bit

read/write.
13

generate

interrupt.

This

bit

Transmit and Non-Ex-Mem Interrupt Enable — This bit, when
set,

permits

the

setting of bit

to generate

interrupt. This bit is read/write.

Storage

Interrupt — This bit is set whenever the receiver

scanner has found a receiver holding buffer with a character in

it and desires to store that character in the silo but cannot do
so at this time because of a lack of space. When set, this bit
causes an interrupt if bit 12 is set. This bit is read-only, except

in maintenance mode, at which time it is read/write.

3-2

Function

Bit

Transmitter Interrupt — This bit is set whenever the DHI11
concludes an NPR cycle that incremented a byte count to 0,
indicating the loading of the last character in a message buffer
into a UART transmitter holding register. This bit, when set,
causes an interrupt if bit 13 is set. This bit is read/write. It is
set during an NPR cycle so no hardware/software

synchronizing problems occur.

3.2.2 Next Received Character Register

The Next Received Character Register is read-only and is word addressable. The register format is shown in Figure
3-2.

LINE NUMBER
DATA

OVERRUN
VALID DATA
PRESENT

01 _ 00

NEXT RECEIVED CHARACTER

PARITY

ERROR

FRAMING
ERROR

11-2197

Figure 3-2 Next Received Character Register Format
Function

Bit

00 — 07

These bits contain the next received character, right justified.

The least significant bit is bit 00. Unused bits are 0. The parity
bit is not shown.

08 — 11

These bits contain the line number upon which the character

Parity Error — This bit is set if the sense of the parity of the

was received. Bit 08 is the least significant.

received character does not agree with that designated for that
line.

Framing Error — This bit is set if the received character did

not have a stop bit present at the proper time. This bit is
usually interpreted as indicating the reception of a break.

Data Overrun — This bit is set if the received character is
preceded by a character that was lost due to the inability of
the receiver scanner to service the UART receiver holding
buffer.

Valid Data Present — This bit indicates that the data presented

in bits 14 — 00 is valid. It permits the use of a character

handling program that takes characters from the silo until
there are no more available. This is done by reading this
register and checking bit 15 until one obtains a word for which
bit 15is 0.

3-3

3.2.3

Line Parameter Register

This register should be loaded only after the System
Control Register has had its line selection bits arrange
d to select
the line to which these line parameters are to apply.
The register format is shown in Figure 3-3. This register
is

write-only.

1009

—

HALF DUPLEX/

RECEIVER

SPEED

CHARACTER

SPEED

lFULL DUPLEX

AUTO—ECHO
ENABLE

TRANSMITTER
.

ENABLED

0DD PARITY

LENGTH

PARITY

TWO STOP
BITS
11-2198

Figure 3-3

Line Parameter Register Format

Bit

Function

00 — 01

Character Length — These bits are set to receive and
transmit
characters of the length (excluding parity) shown below.

Two

Stop

Bits

—

Bit

5 bit

6 bit

7 bit

8 bit

This

bit,

when

set, conditions a line

transmitting with 6, 7, or 8 bit code to
transmit characters

having two stop marks. If the line is transmitting
5 bit code,
assertion of this bit causes the characters to
be transmitted

with 1.5 stop marks. If this bit is not asserted, 1
stop mark is

sent.

Reserved (Not used)

Parity Enabled — If this bit is set, characters transmit
ted on
the line have an appropriate parity bit affixed,
and characters

received on the line have their parity checked.

Odd Parity — If this bit and bit 4 are set, characte
rs of odd

parity are generated on the line and incomin
g characters are
expected to have odd parity. If this bit is not
set, but bit 4 is
set, characters of even parity are generated
on the line and

incoming characters are expected to have even parity.

is not set, the setting of this bit is immaterial.

3-4

If bit 4

Bit

Function

— 09
06

Receiver Speed — The state of these bits determines the
operating speed for the receiver of the selected line. The speed
table below is applicable.

10— 13

Transmitter Speed — The state of these bits determines the
operating speed for the transmitter of the selected line. The
speed table below is applicable.

Speed Table for Receiver and Transmitter Speeds

(Receiver bits)

(Transmitter bits)

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1

0
1.
0
1
©
1
0
1
0
1
0
1
0
1
0

Zero Baud
50 Baud
75 Baud
110 Baud
134.5 Baud
150 Baud
200 Baud
300 Baud
600 Baud
1200 Baud
1800 Baud
2400 Baud
4800 Baud
9600 Baud
External Input A

External Input B

Half Duplex/Full Duplex — If this bit is set, the line is
conditioned to operate in half-duplex mode. If this bit is clear,

the line is conditioned to operate in full-duplex mode. In this
application half duplex means that the DHI11 receiver is

blinded during transmission of a character.
15

Auto-Echo Enable — When this bit is set, characters received
on the line are to be hardware echoed.

3.2.4 Current Address Register

the
This register should be loaded only after the System Control Register has had the appropriate bitsbitsset00to select
are
15
—
address
line number to which this current address is to apply. When this register is Joaded,
bits
Address
transferred into semiconductor memories in the DH11 from bits 00 — 15, respectively, of this register.
Register.
Control
System
the
of
5
—
4
bits
from
DH11
the
in
memories
ctor
16 — 17 are transferred into semicondu
When this register is read, it indicates the current address of the line selected by the System Control Register. Bits 16
and 17 appear in the Silo Status Register.

3-5

3.2.5

Byte Count Register

In the same fashion as the Line Parameter and Current

Address Registers, this register should not be loaded or read
without first selecting a line number by means of the lower
order four bits of the System Control Register. This

line. The Byte Count Register is read/write.
3.2.6

the number of characters (bytes) to be transmitted on

that

Buffer Active Register

This register contains one bit for each line. The bits are set individua

lly. using BIS instructions Setting a bit initiates

transmission on the associated line. The bit is cleared

by the hardware when the last character to be transmitt

that line is loaded into the transmitter Data Holding Register

ed on

of the UART for that line. It should be noted that

while the clearing of a BAR bit does indicate that a
new message may be sent, it does not indicate that the
last
characters from the preceding message have been complete
ly sent. Specifically, two more characters are sent after
the BAR bit clears. These are the last two characters
of the message; one of them is starting when the BAR
is
cleared, and one is the final character loaded into the
holding register, thus clearing the BAR bit. This effect
is a
normal consequence of double-buffered transmission
and is mentioned here for the benefit of programmers
who

want to write programs that control such modem

leads as Request To Send. Clearly, Request To Send

dropped until at least two character times after the BAR

bit for a given line clears.

Clearing a BAR bit should not be used to abort transmission

sent to 0. In this way, a transmitter interrupt is generate

should not be

on a line. Rather, the byte count for that line should be

d. The Buffer Active Register bits are read/write.

3.2.7

Break Control Register

This register contains one bit for each line. Setting a bit in
this register immediately generates a break condition on
the line corresponding to that bit number; clearing the bit terminate
s the break condition. The break condition may
be timed by sending characters during the break interval, since
these characters never actually reach the line.
3.2.8

Silo Status Register

This register is actually two byte-sized registers. The register

////

format is shown in Figure 3-4.

—

SILO

FILL LEVEL

—

READ EXTENDED

MEMORY

SILO ALARM LEVEL

SILO
MAINTENANCE
-2196

Figure 3-4

Silo Status Register

Format

Bit

Function

00 - 05

Silo Alarm Level - The program writes a number
corresponding to the desired silo alarm level into this
location

(see Paragraph 3.3.4, Silo, for programming considerations). When the number of characters stored in
the silo
exceeds that number, an interrupt (System Control
Register bit 7) is generated, if enabled (System Contro
l Register
bit 6 is 1). These bits are read/write.
3-6

Function

Bit

06 — 07

Read Extended Memory — These bits are read-only and

contain the Al16 and A17 bits of the current address for the
line to which the line selection bits of the System Control
Register are pointing.

08 — 13

Silo Fill Level — These bits represent an up-down counter that

indicates the actual number of characters in the silo. It should
be noted that there are six binary digits; hence numbers
between O and 631, can be represented. A full silo has 64,0
entries and appears as 00000, but one may easily tell the
difference between an empty silo (00000) and a full silo
(00000) by checking the storage overflow bit (bit 14 of the

System Control Register). These bits are read-oniy.

Reserved

Sijlo Maintenance — Each time this bit is set, a fixed binary
pattern (1010101010101010) is sent to the silo once for
checking during maintenance. Clearing and setting loads
’
another copy of the pattemn.

33 OPERATIONAL FEATURES WITH PROGRAMMING SIGNIFICANCE
3.3.1

Introduction

significance.
This section includes the discussion of several operational features of the DH11 that have programming
The discussion covers the DH11 device and vector address requirements, the double-buffered feature of the UARTS,
operation of the silo, use of break signals, and the function of the maintenance bits.
3.3.2 Floating Device and Vector Addresses

space that begins at
The DHI1 uses floating device addresses that are located after the DJ11s in the floating address
of 20 (octal).
multiple
is a

location 160010. Because the DH11 has eight registers, it must be assigned an address that
All DH11s in a system should have consecutive addresses.

Example 1: A system with no DJ11s, but two DHl11s:

160010 Cannot use for DH11s because not multiple of 20.
First DH11
160040 Second DH11

160020

160060 DHI11 gap (indicates that there are no more DHI 1s).

Example 2: A system with one DJ11, two DHi s:
160010

First DJ11

160020 DIJ11 gap (indicates that there are no more DJ1 Is).
160030 Cannot use for DH11s because not multiple of 20.
160040 First DH11
160060 Second DH11

160100 DH11 gap (indicates that there are no more DH1 1s).

3-7

The DH11 requires two vector addresses which follow
those of the DJ11 in the floating vector space that
starts at
address 300. The vectors starting at 300 are used
in the following order: DC11;KLI 1/DL11-A,B;
DP11; DM11-A;
DN11; DM11-BB; DR11-A; DR11-C; PA611 Readers
; PA611 Punches; DT11; DX11 ; DL11-C,D,E; DJ11;
DH11.
Of the two DHI11 vectors, the receiver vector
is the lower numbered vector. The priority of
the receiver and

transmitter interrupts are individually selectable

by means of two standard PDP-11 priority jumper

plugs.

333 Double-Buffered Receivers and Transmitters
The receiver and transmitter sections of the UART
are double-buffered, that i, each section contams
a Shift
Register and a Holding Register. For the receiver, the
serial input character goes to the Shift Register which
performs

a serial-to-parallel conversion and transfers the

character in parallel to the Holding Register. At

(Received Data Available) flag goes high. In the DH11,

this point, the DA

the DA flags of the 16 UART: are sampled by the receiver

scanner. If the scanner finds a high DA flag,
it copies the data from the receiver Holding
Register into the silo, if
space is available. If space is not available,
the Storage Interrupt bit in the CSR is set
and a teceiver interrupt is
generated, if enabled. This does not mean that
the data has been lost. Rather, it indicates that
the data in this or any

other receiver Holding Register will be lost if the
scanner cannot move the data to the silo before
an additional
character arrives on the line. Actual data loss is
apparent to the program when characters are received
with the
DATA OVERRUN bit set.
For the transmitter, the Holding Register can
be loaded in parallel with a character to be transmi
tted when the
TBMT (Transmitter Buffer Empty) flag goes high.
The character is automatically transferred to the
Shift Register
when this register becomes empty. The desired start,
stop, and parity bits are added to the character and
serial

transmission begins. At the end of a charact

er transmission, the EOC (End of Character)

in this state until transmission of a new character

3.3.4

begins.

flag goes high and remains

Silo

The silo, actually more similar in design to a grainery
, is a first-in, first-out buffer store. A parallel loaded
16-bit
word (see Paragraph 3.2.2 for the format) automat
ically propagates downward into the first locatio
n not already

containing a word. When the silo is empty,

the word propagates directly into the Next

The propagation time from the top of the silo to

is arranged such that the receiver interrupt is

Received Character Register.

the bottom may be as much as 32 us. For this reason,

not generated until the number of characters

the hardware

in the silo exceeds the silo

alarm level and there is at least one character in the
bottom of the silo. This arrangement is necessary
because the
up-down counter that indicates the number of characte
rs in the silo indicates exactly that: the number of
characters
in the silo, which includes those resting in the bottom
and those propagating downward.

While the hardware arrangement protects the
case where the silo is empty and the alarm level
is zero, the number of
characters in the silo and the number actuall
y available to be serviced may differ due to the
propagation time. If
having at least one character in the bottom of the
silo was not made a condition in the interrupt generati
on, the
program would receive an interrupt while the

single character in the silo was propagating

downward. For this reason,

character handling programs should not assume
there are some particular number of characters
in the silo

servicing begins. Rather, the program should

extract a character, check the valid data present

the character; then the program should extract the

as a 1. At that time, the silo may be assumed
to

On very fast processors, such as the PDP-11 /45,
Register more often than once per us, as it takes

next character and repeat the process until bit 15 no

er propagating

be terminated until another receiver interrupt is

received.

the program should avoid reading the Next Receive

d Character

one ks for characters in the silo to shift downwa

Since the typical program checks bit 15 and moves
requirement will not pose a problem.

longer tests

be empty (although there may be another charact

downward) and the character handling routine may

when

bit (bit 15) and handle

rd one position.

the character to some location, it is anticipated
'

3-8

that this speed

The silo alarm level can be set to any number from 0 through 63. However, care should be taken that an
appropriate alarm level be chosen to suit software /hardware timing and system throughput requirements. At

any silo alarm level, once the program enters the receive interrupt routine it is best to read all words from the
NRC, checking bit 15 of each one, until a word is encountered with bit 15 equal to a zero. This implies that the

silo is empty, and will maximize the usefulness of the silo alarm feature.
The programmer must be aware that new characters may enter the silo as it is being emptied, so that the silo
alarm level is not meant to indicate the exact silo fill level except at the moment it interrupts. It is recommended that the receiver interrupt service routin. which reads the NRC be run at a priority level equal to or

higher than that of the DH11. If the receiver is able to interrupt its own service routine while the silo is being
emptied, extra interrupts will be generated due to interaction of incoming data, the silo fill level, and the silo
alarm level.
3.3.5

Zero Baud

A speed selection of 0 Baud is provided so that the program may turn off any line. This is useful should excessive
circuit noise on an unused line cause the receipt of annoying quantities of bogus characters.

3.3.6

Break Signals

When the Break Control Register has been conditioned to transmit a break signal on a particular line, DHI1 logic
immediately forces the output on that line to the space (0) condition.

The generation of a transmitter interrupt occurs when the last character of a message has been loaded into a UART
transmitter from a message table in the PDP-11 memory. It is thus appropriate at that time for the program to set up
a new message in memory and to load the appropriate current address and byte count so that the new message can

begin when the old one is finished.
It is important to note that the former message is not finished when the transmitter interrupt is given; rather, the use

of the memory table is finished. In terms of the actual serial communications line, there are two more characters left
to go. One of these characters is in the UART transmitter’s Shift Register; the other is in the UART transmitter’s
Holding Register.

The consequence of the above condition is that to send a break signal, one should load two nulls (all ones) and wait

for a transmitter interrupt before setting the appropriate bit in the Break Control Register. In this way, generation of
a break does not interrupt the transmission of any printing characters. In like manner, when using characters to time

the transmission of a break signal, nulls should be used so that when the break condition is terminated by clearing
the bit in the Break Control Register, no printing characters are produced from the UART Shift and Holding

Registers.
3.3.7

Initialize Signal

The Initialize signal clears the silo, UARTS, and all registers except the Current Address and Byte Count Registers.
All scanners are forced to line 00 but continue operation from there.
3.3.8

Maintenance Bits SCR 09 and SSR 15

Setting bit SCR 09 (Maintenance) causes the following action:
Enables the ability of the program to write SCR 07 (Receiver Interrupt), SCR 10 (Non-Existent Memory

Interrupt), and SCR 14 (Storage Overflow Interrupt) bits. This write capability is normally not enabled as it

can produce hardware/software synchronization problems unless carefully done.

The following precaution must be observed in the maintenance mode. If the program reads bit 7 of the SCR

and finds that it is a 1, the program must perform a Bit Clear instruction on bit 7 before reading the NRC. This
is required because in the maintenance mode, bit 7 is an OR function of the output of a program-controlled

flip-flop and a signal from the silo alarm circuit. If SCR bit 7 is read, and is found to be a 1, and the Bit Clear
instruction is not performed, the flip-flop is set during the restore portion of the Unibus read cycle. Because of

the OR function, the flip-flop masks the transitions of the silo alarm circuit that occurs when the NRC is read.
These transitions are required for proper operation of the M7821 Interrupt Module.

Loops the transmitted data leads (serial out line 00 — 15) to the received data leads (serial in line 00 — 15),

Setting bit SSR 15 (Silo Maintenance) causes the inputs of the silo to be set to a 1010101010101010 bit pattern,
and a single 16-bit character made up of this pattern to be loaded into the silo. Successive clears and sets of SSR 15

repeat this procedure. All receiver speeds should be set to 0 Baud and the silo emptied before this is done, so that no

data from the incoming serial lines is placed in the silo while it is under test.

3-10

4.1

INTRODUCTION

This chapter provides a detailed description of the DH11 logic. The discussion is keyed to the DH11 print set that
is
supplied as a separate bound volume. Additional illustrations are included in the discussion which is divided
into 11
parts.

Discussion

Paragraph

Address Selector and Gating Control

4.2

Clock Module M4540

4.3

Line Parameter Control Module M7288

4.4

Transmitter Scanner

4.5

Current Address and Control Logic

Byte Count Register
Receiver Scanner

4.8
:

System Control Register

Half/Full Duplex Control Logic
Registers and Byte Count Module M7278

4.2.1

4.7

FIFO Buffer

4.2

4.6

4.9

4.10

4.11
4.12

ADDRESS SELECTOR AND GATING CONTROL

Address Assignment

Each DHI11 multiplexer is assigned eight consecutive addresses that are decoded to generate control signals for

enabling eight registers in the DH11.

A specific number of memory addresses in each PDP-11 system are reserved for communications
devices. The space
that includes the DHI11 device addresses extends from 760020 — 764000 (octal designation). These
locations are

termed floating addresses. The conventions used for assigning floating addresses are discussed in Appendix A.

Location 760020 is assigned as the first address of the first DH11 in the system; actually, the DH11

requires eight

consecutive locations (760020 — 760036). A maximum of 16 DH11s are allowed per system. The addressing

for the maximum number of DH11s is shown below, assuming that the system contains no DJ11s.

4-1

space

760020

Ist register of 1st DHI
1

760022
760024

760026
760030
760032

760034

760036

Sth register of ist DHI1

760040

1st register of 2nd DH11

760042
760044
............

760416

8th register of 16th DHI11

The address selection and gating control logic is shown in. drawing D-CS-M7277-0-1, sheets 3, 4, and 5.
When the program desires to read from or write into a DH11 register, it must address the register and indicate the
type of operation to be performed. This is accomplished by placing the proper binary information on Unibus address
lines A(17:00) and Unibus control lines C(01:00) and asserting BUS MSYN L. These signals are decoded by the
DH11 logic to generate the enabling signal for the addressed register. This allows data from the Unibus data lines

D(15:00) to be written into the register, or it allows the contents of the register to be placed (read) onto the Unibus
data lines.

Bits C(01:00) and AOO are decoded to indicate the type of operation or Unibus transaction to be performed (Table
4-1). The DATIP transaction is not used with the DHI11.

Bits A(17:04) are decoded to indicate the device address of the DH11. Each DH11 in a system has a different device

address. The device address is hardwired by jumpers that are associated with bits A(12:04). Bits A(03:01) are
decoded to select the desired register in the DH11.
Table 4-1

Unibus Transactions for DH11
C Bits

Name

Mnemonic

Co1

C00

Bit A0O

Data In

DATI

Function
Data transmitted from DHI1 to processor
on D(15:00).

When DH11 is master, data is

transmitted in bytes from memory to DH11.

Bit AGO = O gives low order byte. Bit AOO =
1 gives high order byte.

Data Out

DATO

Data transmitted from processor to DH11

on D(15:00).

Data Out,
Byte

DATOB

Data transmitted from processor to DHI1
on D(07:00) which is low byte.

Data transmitted from processor to DH11

on D(15:08) which is high byte.
*X = irrelevant

4-2

The address format is shown in Figure 4-1. The example used is 760020, which is the address of the first designated
register in the first DH11 installed in the system. The binary representations of the two least significant octal

digits

of all eight registers are shown to illustrate how device address bits A(17:04) remain unchanged and bits A(03:01)
change for each register.

/_———REGISTER SELECTION

ala

DEVICE ADDRESS

NOT USED FOR

ADDRESS SE! ECTION

Pwwiltcus

JoeCw

ADDRESS BIT

BINARY

NO.

0CTAL

ADDRESS BITS

ADDRESS

05 04 03 02 01 00

117

0lo

2({7

2{0

3/7

4/01

4(7

6/{0

5/7

0[O0

00O

6,7

686

2/01

7|7

4/0

8|7

00 3 6/01

00
1

11 10

)\—L REGISTER SELECTION
A(17:04)

CONSTANT FOR

A SPECIFIC DH11
1-1686

Figure 4-1

Address Word Format

422 Device Decoding
Unibus address bits A(17:04) are used to specify the device address. They are sent from the Unibus to type 380
Unibus receivers which are 2-input NOR gates (drawing D-CS-M7277-0-1, sheet 4). They are shown as logically

equivalent negated-input AND gates. Twelve receivers are used for bits A(17:04). Bits A16 and A15 go to receiver
E22 pins 11 and 12, and bits Al4 and A13 go to receiver E22 pins 6 and 7. Bits A(12:04) go to individual receivers

E22 (1), E15 (4), and E8 (4) and the other input of each of these receivers is connected to ground. Bit A17 is
combined with BUS MSYN L in receiver E22 pins 9 and 10.
Eleven receivers are used for bits A{16:04). The output of each receiver is sent to one input of type 8242 2-input
exclusive NOR gates E21 (3), E14 (4), and E7 (4). These gates are used as digital comparators. The gate output is

high only when both inputs are identical (both high or both low). The 8242s have open collector outputs and all the
outputs are connected together and retumed to +5V via an external resistor to form a wire-OR function. The
common output is high only when all the 8242 gates produce high: outputs.

Using a PDP-11 processor with a maximum limit of 64K bytés (32K words), bits A17 and A16 are forced to 1s if

bits A(15:13) are all 1s when the processor is master. This allows generation of addresses 76000 — 777777 with
control for only 16 address bits. This 8K byte (4K word) area is reserved for peripheral device addresses. This action
relocates the last 8K addresses to the highest 8K locations accessible by the bus. See Appendix B for more details
concerning this function.

4-3

To avoid confusion, the reader should be aware that the Unibus uses negative logic for all signals except BG(07:04)
and NPG. The definitions of positive logic are shown below:

Negative Logic

Signal Asserted:

Low = Logical 1

Signal at Rest:

High = Logical 0 =+3 V

=0 V'

Positive Logic
Signal Asserted:

High = Logical 1 =+3V

Signal at Rest:

Low = Logical 0 =0V

In this discussion, 760020 is used as the device address. Bits A(17:13) are all 1s (Figure 4-1). These bits are Unibus
signals so they are all low at the inputs of their associated receivers. Bits A16 and AlS5 go to receiver E22 pins 11 and
12, and bits Al4 and A13 to receiver E22 pins 6 and 7. Each receiver output is high and it is sent to one input of its
associated 8242 comparator. The other input of each 8242 is held high by +5 V via resistor R24, and both 8242
outputs are high. Bits A(12:04) go to separate receivers, each of which has its other input grounded (low). These
receivers act like inverters and apply the inverted Unibus address signal to one input of its associated 8242
comparator. The other input to each 8242 can be held high or low by installing or removing a jumper. With the
jumper out, the input is held high through a connection to +5 V via a resistor. With the jumper installed, the input is
dropped to ground. The jumpers are arranged to make the DH11 respond to a specific device address. With a jumper
installed, the decoder responds to a 0 on the associated Unibus address line; it responds to a 1 if the jumper is out.
Using the example (Figure 4-1) and remembering the negative logic convention for the Unibus, examine bits AO4
and AO05 (Figure 4-2). Bit A04 is a 1, which is a low on the Unibus. This puts a high on one 8242 input and the other
input is high because the jumper is removed. The inputs match so the 8242 output is high. Bit A0S is a 0, which is a
high on the Unibus. This puts a low on one 8242 input and the other input is low because the jumper is instalied.
The inputs match so the 8242 output is high.

This action is repeated for bits A(12:06), all of which have jumpers installed, so that ail 11 8242 outputs are high.
The DHI11 device address has been successfully decoded and this high signal is sent to 4-input NAND gate E72.
Another input to E72 comes from receiver E22 pin 14. One input (pin 10) of E22 is bit A17 which is low. When the
processor asserts BUS MSYN L, the other input (pin 9) of E22 goes low and its output is high. Assume that the
other two inputs of E72 are high. These inputs are controlled by other functions of the DH11 and will be discussed
in subsequent paragraphs. With all four inputs high, the low output (pin 6) of E72 is sent to the gating control logic.

The output of E72 is also double inverted by two Unibus drivers to assert BUS SSYN L, which is the DH11’s
response to the processor that it has decoded the device address. The BUS SSYN L signal is inverted by E28 to
produce SSYN H, which is used as an input to Unibus Master Control Module M796.

4.2.3

Gating Control Logic

The gating control logic generates the enabling signals for the eight registers and the Unibus drivers that place the |
data to be read on the Unibus. These enabling signals are a function of the selected register and the type of Unibus
transaction desired. A prerequisite is that the device address has been properly decoded.

4-4

BUS

AO4 L

;

\ 2

< COMMON COLLECTOR

q__/

380

3 RESISTOR R1

8242

I, S

—» TO E72 PIN 4

J5
4

BUS

AOS5 L

{

>
s | E8

\ 3

b q——/

380

9
—

L ASSERTED ONLY IF

8242

ALL

8242 OUTPUTS ARE HIGH

IDENTICAL CIRCUITS
FOR

BITS AO6-A{2
ALL OF WHICH

TRUTH TABLE

8242

JUMPERS

AlB|cC

HAVE

EXCLUSIVE NOR

LIH]L

H|lL|L
H

| H|n

8242 USED ASA DIGITAL
| COMPARATOR.

OUTPUT

HIGH ONLY WHEN

ASSIGNED
17

ADDRESS
15

INPUTS MATCH.

760020
13

05.

111110»000

o0f

ADDRESS

BIT

00001000OB

INARY

0
.

0
BITS

AO4

SELECTED

JUMPER

OCTAL

-A12

BY JUMPERS

IN —»=
O

JUMPER OUT

BUS

—1

11-1687

Figure 4-2

Device Address Decoding Logic

Table 4-2 lists the registers and their address
assigned different addresses but the register

es for the example used in the discussion. Additio

nal DH11s would be

order remains the same.

Table 4-2

DH11 Register Address Sequence

Order

Address

Name

Type

760020

System Control (SCR)

760022

Next Received Character (NRC)

760024

760026

Line Parameter (LPR)
Current Address (CA)

760030

Byte Count (BC)

760032

Buffer Active (BAR)

760034

Break Control (BCR)

760036

Silo Status (SSR)

Read/Write High and Low Bytes
Read-Only

Write-Only
Read/Write

Read/Write

Read/Write
Read/Write

Read/Write
High Byte Only
4-5

The gating control signals, or register enabling signals, are listed in Table 4-3. The signal name, source, and function

are indicated. Register selection is performed by decoding bits A(03:01) and using them as the binary code to
control 7442 4-ine-to-10-line decoder E51. In this case, only8 of the 10 outputs are used. Three of the four inputs
(DO, D1, and D2) are used as the binary code and the fourth input (D3) is used as a strobe or enabling signal. Bit
AO03 goes to D2 as the most significant bit; bit A02 goes to D1 and bit AO1 goes to DO. The D3 input comes from
gate E72 which produces the low enabling signal when the DHI1 device address is decoded and BUS MSYN L is
asserted. The 7442 decoder functions as a 3-wire binary-to-octal decoder (Figure 4-3). When the strobe (D3 input) is
low. the octal data is taken from outputs 0 — 7. The output of the 7442 decoder is sent to one input of the gate
associated with the desired register control signal. Output 0 of the decoder goes to E34 pin 5 and E34 pin 3 to allow
bytes to be written into the System Control Register. One input (pin 2) of gate E53 comes from 3-input NAND gate

E55 (shown as negated-input NOR) whose inputs come from outputs 3, 4, and 7 of the 7442 decoder. These outputs

represent selection of the Current Address Register, Byte Count Register, or Silo Status Register. When a read
operation is desired for any of these registers, the read enabling signal is generated at ES3 pin 3.

Table 4-3

Gating Control Signals

Source*

Signal

Function

- (Gate Output)

LOADCAH

Gate E58 pin 13

Write into Current Address Register

LOAD BCH

Gate E69 pin 4

Write into Byte Count Register

LOAD LPRH

Gate ES8 pin 1

Write into Line Parameter Register

LOAD SCR HIGH BYTE H

Gate E34 pin 4

Write into high byte of System Control Register

LOAD SCR LOW BYTE H

Gate E34 pin 1

Write into low byte of System Control Register

LOAD BAR LB or HB L

Inverter E35 pin 4

Write into low byte or high byte of Buffer

LOAD SSR LOW BYTE H

Gate E34 pin 13

Write into low byte of Silo Status Register

LOAD SSR HIGH BYTE H

Gate E34 pin 10

Write into high byte of Silo Status Register

LOAD BCR H

Gate E69 pin 13

Write into Break Control Register

READ CA or BCor SSRL

Gate E53 pin 3

Read Current Address Register, Byte Count

READ NRCH

Gate E58 pin 4

Read Next.Rec'eived Character Register

DATATOBUSH

Gate E58 pin 10

Enable Unibus drivers

Active Register

*All gates are shown on drawing D-CS-M7277-0-1, sheet 4.

4-6

FOP—— SSR

F1 P—— BCR

7442 DECODER USED AS A 3 WIRE
BINARY TO OCTAL DECODER.OUTPUT
ENABLED LOW WITH STROBE LOW.

1
1

o
o
1

1
X

110

111

]

Fa D—Oi— BAR

11111

—B8C | sigNALS

O] =]

Lh: D1

CONTROL

F3p—

OUTPUTS

p3|o2[o1[polFo[F1][r2[F3]Fa[Fs]Fs[F7

O] =]|

|oq

11111

111411
1111
ol

a2l a2

—

ll\)

—

A Ol L

BUS

P———
cA | REGISTER
Taerapo

—\

»—3q

Fsb

TRUTH TABLE

INPUTS

- | 2|

3],

BUS A Q2L —O

F6p—— NCR

~|o|lo]lo|o|o|o]|o]o

BUS A 03 L—Gom

F7-22— scR Y

X|=>|O|={O|—=[O}|
=10

—'eqp3

Xlalalal=]lololo

STROBE

111

1,01
11110

1)1
1-1688

Figure 4-3

Selection of Register Gating Signals

The other input of each register selection gate is qualified as a function of the decoded Unibus transfer using bits

C(01:00) and AOO (Table 4-1). The gates are qualified in groups as shown below.
Unibus Transaction

Gates Qualified

DATI

All READ gatés plus DATA TO BUS Gate

DATO

All LOAD gates

DATOB, Low Byte

All LOAD gates except LOAD SCR HIGH

BYTE and LOAD SSR HIGH BYTE gates
DATOB, High Byte

All LOAD gates except LOAD SCR LOW

BYTE and LOAD SSR LOW BYTE gates

The output of gate E58 (LOAD LPR H) goes to pins 3 and 4 of type 74121 one-shot E54 (drawing D-CS-M7277-0-1,
sheet 3). Pin 5 of this one-shot is held high by +3 V. Under these conditions, a negative edge at either pin 3 or 4

triggers the one-shot. Prior to triggering, the 1-output (pin 6) is low and the O-output (pin 1) is high. When it triggers,
a positive pulse is generated at the 1-output and a negative pulse is generated at the O-output. The pulse duration is

300 ns and when it terminates, the outputs return to their original states. When LOAD LPR H is low (non-asserted)
the one-shot is not triggered because its input (pins 3 and 4) reacts only to a negative edge transition. When the
program desires to write into the Line Parameter Register, gate ES8 pin 1 is asserted and LOAD LPR H goes high.

This positive edge transition does not trigger the one-shot, but when LOAD LPR H goes low again after BUS MSYN

L is cleared, a negative edge transition is generated which triggers the one-shot. The low pulse from the 0-output of
the one-shot enables inputs on the type 74152 4-line to 16-line multiplexer E47 and it selects the proper line to

which the line parameters are to apply. An enabling pulse of approximately 300 ns is required to ensure that the line
parameters are loaded into the UARTS from the Line Parameter Register. The proper line is selected by bits 00 — 03
(SCR 00 H — SCR 03 H) from the Line Selection Register to the BCD decoding inputs of the 74154.

The 1-output of one-shot E54 is fed back to the device selection logic to prevent the DH11 from responding to

another LOAD LPR or LOAD SCR instruction while the 300 ns pulse is being issued (Paragraph 4.2.4).
The outputs of the A(03:01) receivers are buffered by type 7417 non-inverting buffers and sent to the data select

inputs of 16 type 74151 8-line to 1-ine multiplexers shown in drawing D-CS-M7278-0-1, sheets 5, 6, 7, and 8. These
signals are identified as DATA SOURCE C H, DATA SOURCE B H, and DATA SOURCE A H.

4-7

The output of the eight DH11 registers are sent to the inputs of the 16 multiplexers. During a DATI transaction, the

data from the register being read is multiplexed to Unibus drlvers and enabled to the Unibus by the DATA TO BUS
H signal from gate E58 pin 10.
4.2.4

Address Response Inhibiting Logic

Three one-shots are used to inhibit response to an address under certain conditions.

The first condition concerns disabling the register control signals as part of the initialization process caused by
setting bit 11 of the System Control Register. When the program sets bit 11 of the System Control Register, signal
SCR 11 is high and is sent to pin 5 of NAND gate E53 (drawing D-CS-M7277-0-1, sheet 3). The other input of this
gate becomes high when the instruction that set SCR 11 is concluded. When the output of E53 goes low, the
negative transition triggers one-shot E60 and sends a negative pulse of 2.4 us duration to pin 2 of gate E72. The

output of E72 is driven high which prevents the generation of DEVICE RESPONDING L and thus prevents
generation of SSYN L for the duration of the 2.4 us initialization pulse generated by E60. In this way, the DH11

will not accept new instructions until at least 2.4 us after the end of the initialization instruction. This allows time

for the UART: to be cleared.

The negative pulse from one-shot E60 is also sent to 4-input NAND buffer E71 and is inverted to produce INIT A H.
This signal is inverted by NAND buffer E71 to produce INIT A L. It is also inverted by NAND buffer E66 to
produce INIT B L. The output of this buffer is inverted to produce INIT B H. These four signals are used throughout

the DH11 logic to clear the registers, UARTSs, and silo.
When the program desires to perform a complete initialization of all devices on the Unibus, BUS INIT L is asserted
on the Unibus. This signal is sent to pin 6 of Unibus receiver E28, is inverted, and sent also to NAND buffer E71 to

generate the four Initialize signals. BUS INIT L is asserted by the PDP-11 processor during the power up sequence,

during a RESET instruction, or when the processor console START switchis pressed.
The second condition concerns inhibiting response to an address for 300 ns after the previous NPR transaction has
been cleared. This is accomplished by sensing the END CYCLE L signal from the M796 Unibus Master Control
Module. This signal is a 100 ns pulse that is generated when certain M796 signals are cleared to indicate the end of
the current NPR transaction. The leading negative edge of the END CYCLE L pulse triggers one-shot E61 and sends
a negative pulse of 300 ns to pin 1 of gate E72. The address decoding logic is inhibited by this low input to E72 for
the duration of the one-shot pulse. This delay ensures completion of the current operations within the DHI1

incrementation of the Current Address and Byte Count Registers and occurs after every transaction in which the
DHI11 is master.

The third condition concerns inhibiting response to an address during the 300 ns interval that the 74154 multiplexer
is enabled. This allows the UART control and data inputs to settle. When the Line Parameter Register (LPR) address
is decoded and BUS MSYN L is asserted, LOAD LPR H is generated at gate E58 pin 1 and loads the information on
the Unibus data lines into the LPR. The address decoder asserts BUS SSYN L and the processor clears BUS MSYN L.

Signal LOAD LPR H now goes low and this negative transition triggers one-shot E54. The 1-output of one-shot E54
is sent to pin 9 of 2-input NAND gate E53 as CONTROL STROBE INHIBIT (1) H. The other input (pin 10) of E53
is also high because gate E72 is high due to BUS MSYN L being cleared. The output (pin 8) of gate E53 goes low and
this negative transition fires one-shot E61 and sends a negative pulse of 300 ns duration to pin 1 of gate E72. This

pulse inhibits the decoding logic for the duration of the one-shot pulse.
4.3

CLOCK MODULE M4540

4.3.1 Introductioh
The M4540 Clock Module generates 16 different pulse trains that are used to control the speed of the UART
receiver and transmitter. Expressed in Baud, they are: 50, 75, 100, 110, 134.5, 150, 200, 300, 600, 1200, 1800,
2400, 3600, 4800, 7200, and 9600. All but 100, 3600, and 7200 are program selectable, using the Line Parameter

4-8

Register. The UART receiver and transmitter clocks must be 16 times the value of the desired Baud rate since the
UART samples incoming data 16 times per second. The frequency in Hz of any of these 16 Baud rates is found by
multiplying the Baud rate by 16. For example: 110 Baud X 16 = 1760 Hz; 2400 Baud X 16 = 38,400 Hz or
‘

38.4 kHz.

The clock module consists of a 20.277 MHz crystal controlled oscillator whose output is divided by a series of
counters to produce 16 different pulse trains.

74H74 High Speed D-Type Flip- Flops

7493 4-Bit Binary Counters

The frequency division or count down function is performed by the following ICs:

74161 Synchronous 4-Bit Counters

7490 Decade Counter
7492 Divide-by-12 Counters

Because of the various operating modes possible with these counters, the operation of the count down function is
not obvious from an examination of the clock logic print (D-CS-M4540-0-1, sheet 2). The functional operation of
each counter is discussed first and then the complete count down function .is discussed with reference to the logic
print.

4.3.2 Counter Functional Descriptions

432.1 General Information — The counters used in the clock are standard TTL Medium Scale Integration (MSI)

devices. The symbols used on the logic print are from the DIGITAL IC Dictionary. The input/output designations
within the symbols are different than those used in the manufacturers IC catalog; however, the pin numbers are the
same as those shownin the IC catalog.

4.3.2.2 74H74 Flip-Flops — Two 74H74 high speed D-type flip-flops are used to divide the oscillator output by 2
and 4. These flipflops are contained in a single package designated EO4. Figure 44 shows the fhp-flops and
associated timing diagram.

The 20.277 MHz oscillator output is inverted by gate EQ9 and applied to the clock input of flip-flop A. Triggering
occurs at a voltage level on the positive edge of the clock pulse and is not related to the transition time of the edge.
The (0) output (pin 06) of the flip-flop is fed back to its D-input so that the flip-flop changes state at each positive
edge of the clock pulse. This action produces complementary pulse trains at the (1) H and (0) H outputs that have a
frequency of 10.138 MHz. Flip-flop A divides the oscillator frequency by 2. Flip-flop B is connected in a similar
manner except that its clock input is the 10.138 MHz signal from the (0) H output (pin 6) of flip-flop B. Flip-flop B
divides this signal by 2 to produce complementary 5.069 MHz signals at its 1 and O outputs. The clear and preset
inputs of both flip-flops are disabled by connecting them to +3 V.

4.3.2.3 7490 Decade Counter — One 7490 counter is used and it is identified as EQ1 (Figure 4-5). Output R3 (1)
provides a divide by 5 function for the input to CLK BO. A separate divide by 2 function is provided at output RO
(1) for the input to CLK 0. Inputs SET 9 and CLR are disabled by connecting them to ground.

4.3.2.4 7492 Divide by 12 Counter — Four 7492 counters are used and they are identified as E06, E10, E11, and
E12 (Figure 4-6). All four are used as divide by 6 counters with a separate divide by 2 function. Simultaneous
frequency divisions of 3 and 6 are provided at outputs R2 (1) and R3 (1) for the input to CLK BC. A separate divide
by 2 function is provided at output RO (1) for the input to CLK 0. Input CLR is disabled by connecting it to
ground.

OSCILLATOR

f=20.277MHz

INVERTED OSCILLATOR
OUTPUT FROM EO9 PIN 03

T
I I

D~ INPUT OF FLIP FLOP A
FED BACK FROM O-OQUTPUT

FLIP FLOP A

1-OUTPUT OF FLIP

FLOP A

=10.137MHz

O-OUTPUT OF FLIP FLOP A
TO CLOCK INPUT OF
FILIP FLOP

D-INPUT OF FLIP FLOP B

FED BACK FROM O-OUTPUT
OF FLIP FLOP B

1-OUTPUT OF

FLIP FLOP B

3= 5-068MHz

0-OUTPUT OF FLIP FLOP B

I
+3v

+3v

dl)

PRE

EO4
OSCILLATOR OUTPUT

f=20.277 MHz

oa.

)

E09

03|,

7490

EO1

SET 9

CLR

+3V

R3(1)

DIVIDE BY 5 FOR CLK BO

)

02
.

2
RO(M)}—2
— DIVIDE BY 2 FOR CLK O

CLR
CLK

BOCLK

CLOCK.
INPUTS
NOTES

1. Ciear (CLR) and preset 9 (SET 9) Inputs are disabled.
2. Provides two count down functions.
11-1693

Figure 4-5

7490 Divide by 5 and Divide by 2 Counter

4-10

5.068MHz

09
o——

0 08

R1n}—22

E04

05
OO—

10.137MHz

PRE

—D

Divide Function Performed by Flip-Flop E04

r2(

+3V

Figure 4-4

11-1891

7492

EO6

E‘fi

R3(1)

AND
E12

R2(1)

) clR

DIVIDE BY 6

Rt (1)

FOR CLK BC
DIVIDE BY 3

RO(M|'2

DIVIDE BY 2 FOR CLK O

CLK BC CLK O

cLock [

T 14

io1

iNPUTS \—
NOTES

1. Clear (CLR) input is disabled.
2. Provides three count down functions.
1-1632

Figure 4-6

4.3.2.5

7492 Divide by 6 and Divide by 2 Counter

7493 4-Bit Binary Counter — Three 7493 counters are used and are identified as E02, EQ5, and E07 (Figure

4-7). One (E02) is used as a 4-bit ripple-through counter and two (EOS5 and EQ7) are used as 3-bit ripple-through
counters with independent modulo 2 counters.

7493

EO5

AND

7493

R3(1)

R2(1)

CLEAR 1S

ODZ’ISABLED

02
=

)

R1(1)

CLR

RO(1)

E02

DIVIDE BY 8
DIVIDE BY 4)FOR CLK BC

CLOCK

io1

R2(1)

CLEAR IS

DIVIDE BY 2
o

DISABLED
03

DIVIDE BY 2 FOR CLK.O

CLK BC CLK O

R3(1)

)

R1(1)

CLR

DIVIDE BY 8

RO(1)}—4%—

DIVIDE BY 4

FOR CLK O

DIviDE BY 2

CLK BC CLK O

Io1

INPUTS

DIVIDE BY 16

]

CLOCK INPUT

3 BIT RIPPLE- THROUGH COUNTER AND MODULO 2

COUNTER

4 BIT RIPPLE-THROUGH COUNTER
1H-1694

Figure 4-7

7493 4-Bit Binary Counter

In the 4-bit ripple-through configuration, output RO (1) is connected to CLK BC and the input signal is sent to CLK

0. Simultaneous frequency divisions of 2, 4, 8, and 16 are provided at outputs RO (1), R1 (1), R2 (1), and R3 (1) for
the input to CLK 0.

In the 3-bit ripple-through configuration, no external interconnection is used. Simultaneous frequency divisions of 2,

4, and 8 are provided at outputs R1 (1), R2 (1), and R3 (1) for the input to CLK BC. A separate divide by 2
function is provided at output RO (1) for the input to CLK 0.
In both configurations, the CLR input is disabled by connecting it to ground.

4-11

4.3.2.6 74161 Synchronous 4-Bit Counter — Three 74161 counters are used and they are identified
as EQ3, E08,
and E13 (Figure 4-8). One (E03) is preset to provide a divide by 11 function and two
(EO8 and E13) are preset to
provide a divide by 7 function.

v D
06

DATA
INPUTS
PRESET

GIVE PROPER
COUNT
DOWN

FUNCTION

loz

115

ENBCN

RCRY

D3(MSB)

R3(1)

74161

EO3

ENG

E13

93 fho

To1
+3V

DIVIDE BY 11 WHEN PRESET TO 5
DIVIDE BY 7 WHEN PRESET TO 9

R1(1)

rRo( H
CLR

CLOCK

R2()

CLK ENB CR

09 |o2 110

+3V

INPUT

NOTES
1. Clear (CLR) input disabled.
2 . Both count enable inputs (ENBCR and ENBCN) are held high so the counter
is permanently enabied .
1H-1695

Figure 4-8

74161 Synchronous 4-Bit Counter

In both configurations, the clear (CLR) input is disabled and both count enable
inputs (ENB CN and ENB CR) are
held high (+3 V) so that the counter is permanently enabled. Also, the carry
output (RCRY) is fed back to the load
input (LD) to preset the counter on the count of 15.
To provide a divide by 11 function, inputs D3, D2, D1, and DO are preset to
the count of S by connecting D1 and
D3 to ground (logical 0) and connecting DO and D2 to +3 V (logical 1).
D3

(LSB)

The counter involved is EO3 and the divide by 11 function is provided at output R3
(1) which is the most significant
bit of the counter. Figure 4-9 shows a truth table and waveform for this function. The
counter is preset to a count of
5 by the carry pulse that is generated on a count of 15. This high pulse is inverted
by NAND gate EQ9 and sent to
the load input (LD). A low signal to the LD input conditions the counter such that
the outputs agree with the data

inputs after the next pulse. Reference to Figure 4-9 shows that output R3 (1)
generates a negative transition (and a
positive transition) in a period equivalent to 11 input clock positive transitions.
Thus, the divide by 11 function is
provided at output R3 (1).

Counters E08 and E11 both provide a divide by 7 function. This is accomplishe
d by presetting the inputs

count of 9 and picking the signal from output R2 (1). The operation is similar

function. Figure 4-10 shows a truth table and waveform for the divide by 7 function.

4-12

to the

to that described by the divide by 11

CARRY OUTPUT PULSE
GENERATED AT COUNT 15

!
l

L]
5

[

11 COUNTS

-0

=
=

—_

_h_no_n

—-

0O
=
-

O
=

[

O—D_A_h

-0
= -

—-h_.o_h

—
-~ O
O

LSB RO(1)

R1(1)

R2(1)

MSB R3(1)

TO PRESET COUNTER TOS

bt}

PROVIDES DIVIDE BY 11 FUNCTION.
ONE POSITIVE TRANSITION OF
R3 (1) OCCURS FOR EVERY 1}
POSITIVE CLK TRANSITIONS.

Figure 4-9

11-1696

Divide by 11 Function of 74161 Counter EO3

CARRY OUTPUT PULSE

GENERATED AT COUNT 15
TO PRESET COUNTER TO 9

MSB R3(1)

R2(1)

Ri(1)

LSB RO(1)

R2 (1)

7 COUNTS

PROVIDES DIVIDE BY 7 FUNCTION.

OF R2 (1)
ONE POSITIVE TRANSITION
OCCURS FOR EVERY 7 POSITIVE CLK
TRANSITIONS.
11-1697

Figure 4-10 Divide by 7 Function of 74161 Counter E08

4-13

4.3.3 Count Down Sequence
This discussion traces the oscillator output through the clock logic print (D-CS4540-0-1, sheet 2) to show how

and

where the 16 Baud rates are generated. Additional aids include Figure 4-11 which is a smphfied block diagram of

the clock, and Table 44 which lists the clock output signals and sources.

75 BAUD

100 BAUD

——150 BAUD

200 BAUD

300 BAUD

50 BAUD

o5 — ,
8,24

6FroAND -

AND + 2

15.086kHz

- ‘:2‘ -

‘_]

74161

6ForAND S 7832EL | s.8kHz | 7490:

— - ‘_‘2‘ -

110 BAUD

- - ‘;2‘ ]

]1.267MHz

“;2‘ 1633.6kHz

316.8 kHz

2.534 MHz

L 74161

105.6 kHz

134.5 BAUD

9.6 kHz

5.068 MHz

600 BAUD
74H74

EO04
=2

3600BAUD

9600 BAUD

lf 7200BAUD

— 48008AUD

7493

[
——— 1200 BAUD

=11

AND

_——

NO 2

’; +2

t—-— =2

57.6 kHz

Figure 4-11

Simplified Block Diagram of Clock

Table 4-4

Clock Output Signals
Signal Source

Frequency

Pin No.

Period

Device

Baud

(Hz)

(us)

E12 pin 08

9600

153,600

6.5

E02 pin 08

7200

115,200

8.8

E12 pin 12

4800

76,800

130

EO2 pin 11

3600

57,600

174

EO07 pin 09

2400

38,400

260

EQ7 pin 12

1800

28,800

34.7

52.1

EO7 pin 08

1200

19,200

EO7 pin 11

600

9,600

104

EOS5 pin 09

300

4,800

208

E10 pin 09

200

3,200

313

EOS pin 08

150

2,400

417
465

E13 pin 12

134.5

2,152

EO1 pin 11

110

1,760

568

E10 pin 08

100

1,600

625

EOS pin 11

1,250

833

E10 pin 12

800

1250

NOTE: Frequency in Hz is 16 times Baud.

4-14

2400 BAUD
—— 1800

BAUD

The crystal controlled oscillator starts operating when +5 V power is applied. Once started, it is free running and
supplies a 20.277 MHz signal to pin 01 of gate EQ9. This gate inverts the signal and sends it to the clock input (pin
03) of flip-flop E04. This clock input is divided by 2 and appears at the complementary flip-flop outputs as a
10.138 MHz signal. The (1) H output (pin 05) of the flip-flop is sent to the CLK input of counter E03. This type
74161 counter functions as a divide by 11 counter. Its output signal, which is 921.6 kHz, is taken from the R3 (1)
output and sent to the CLK 0 input of counter E02 and the CLK BC input of counter E12.

Counter EQ2 is a type 7493 that functions as a 4-bit ripple-through counter. Output R2 (1) represents a divide by 8
function that produces a 115.2 kHz s1gna1 This is the 7200 Baud signal and is brought out to module pin C1.
Output R3 (1) represents a divide by 16 function that produces a 57.6 kHz signal. Thisis the 3600 Baud signaland
is brought out to module pin Al.

Counter E12 is a type 7492 that operates as a divide by 6 counter and a divide by 2 counter. The CLK BC input
(921.6 kHz) is divided by 6 to produce a 153.6 kHz signal at output R3 (1). This is the 9600 Baud signal and is
brought out to module pin B1. Output R3 (1) is also fed back to the CLK O input. It is divided by 2 to produce a
76.8 kHz signal at output RO (1). This is the 4800 Baud signal and it is brought out to module pin N1.

The 3600 Baud output of counter EQ2 is sent to the CLK 0 input of counter EO7; and the 4800 Baud output of
counter E12 is sent to the CLK BC input of counter EQ7. Counter EQ7 is a type 7493 that functions as a 3-bit
ripple-through counter and a modulo 2 counter. Outputs R3 (1), R2 (1), and R1 (1) are the outputs of the 3-bit
ripple-through counter associated with the CLK BC input (4800 Baud or 76.8 kHz). These outputs represent the
followmg functions:

Divide by 8 at R3 (1) generates 600 Baud (9.6 kHz)
Divide by 4 at R2 (1) generates 1200 Baud (19.2 kHz)
Divide by 2 at R1 (1) generates 2400 Baud (38.4 kHz)

These signals are brought out to the following module pins: pin S1 for 600 Baud, pin J1 for 1200 Baud, and pin D1
for 2400 Baud.

Output RO (1) of counter EO7 represents a divide by 2 function for the CLK O input. This produces the 1800 Baud
(28.8 kHz) signal that is brought out to module pin U2.

At this point in the discussion, refer back to the first divide by 2 function performed by flip-flop E04. The (O)H

output (pin 06) of this flip-flop is sent to the clock input (pin 11) of the other E04 flip-flop. Another divide by 2
function is performed by this flip-flop and its (0) L output signal, which is 5.068 MHz, is sent to the CLK 0 input of
counter E05. The CLK BC input of E05 is supplied with the 600 Baud (9.6 kHz) signal from counter EQ7.
Counter E05 is a type 7493 that functions as a 3-bit ripple-through counter and a modulo 2 counter. Qutputs R3
(1), R2 (1), and R1 (1) are the outputs of the 3-bit ripple-through counter associated with the CLK BC input (600
Baud or 9.6 kHz). These outputs represent the following functions:

Divide by 8 at R3 (1) generates 75 Baud (1.2 kHz)
Divide by 4 at R2 (1) generates 150 Baud (2.4 kHz)
Divide by 2 at R1 (1) generates 300 Baud (4.8 kHz)

These signals are brought out to the following module pins: pin F1 for 75 Baud, pin K1 for 150 Baud, and pin L1
for 300 Baud.

Output RO (1) of counter EO5 represents a divide by 2 function for the CLK 0 input. This produces the 2.534 MHz
signal that is sent to the CLK O input of counter E06.

4-15

The 600 Baud (9.6 kHz) signal from counter EQ7 is also sent

to the CLK BC input of counter E10. This type 7492

counter operates as a divide by 6 counter and a divide
by 2 counter. The divide by 6 counter

is associated with the

CLK BC input and output R3 (1), R2 (1), and RI (1). Output
R3 (1) represents a divide by 6 function that
produces the 100 Baud (1.6 kHz) signal that is brought out to
module pin T2. Output R2 (1) represents a divide by
3 function that produces the 200 Baud (3.2 kHz) signal that is brought
out to module pin R1. Output R3 (1) is also
fed back to the CLK 0 input. It is divided by 2 to produce the 50
Baud (800 Hz) signal at output RO (1) that is
brought out to module pin P1.
Counter E06 is a type 7492 that operates as a divide by 6 counter
and a divide by 2 counter. Input CLK 0 is fed by
the 2.534 MHz signal from output RO (1) of counter E05. Input CLK
BC is fed by the 316.8 kHz signal from output
RO (1) of counter EO1. The divide by 6 counter is associated with
the CLK BC input and produces a divide by 6
function (52.8 kHz) at output R3 (1) and a divide by 3 function (105.6
kHz) at output R2 (1). The divide by 2
counter is associated with the CLK O input and produces

a 1.267 MHz signal at output RO (1). The R3 (1) output

(52.8 kHz) is sent to the CLK BC input of counter E11 ; the R2 (1)

and the RO (1) output is sent to the CLK 0 input of counter

E11.

output is sent to the CLK input of counter EOS;

Counter E11 is a type 7492 that operates the same as counter

06. It provides a divide by 6 function (8.8 kHz) at
output R3 (1) and a divide by 2 function (633.6 kHz) at output
RO (1). The R3 (1) output is sent to the CLK BO
input of counter EO1 and the RO1 (1) output is sent to the CLK 0
input of counter EO1.

Counter EO1 is a type 7490 that operates as a divide by 5 counter
and a divide by 2 counter. The CLK BC input
(8.8 kHz) is divided by 5 and appears at output R3 (1) as the
110 Baud (1.76 kHz) signal and is brought out to
module pin H1. The CLK 0 input (633.6 kHz) is divided by 2 and
appears at output RO (1) as a 316.8 kHz signal
that is sent to the CLK BC input of counter E06.
The R2 (1) output (105.6 kHz) of counter E06 is sent to the CLK
input of counter EO8. This type 74161 counter
functions as a divide by 7 counter. Its output signal, which is 15.086
kHz, is taken from the R2 (1) output and sent
to the CLK input of counter E13. Counter E13 is also a type
74161 that functions as a divide by 7 counter. Its

output signal is taken from output R2 (1). It is the 134.5 Baud

V2.

(2.155 kHz) signal and is brought out to module pin

The outputs of the clock module are sent to the M7288 Line Parameter
Control Module where they are switched to
the appropriate UART receivers and transmitters on the M7280 Multiple
UART cards.
The 5.068 MHz signal from flip-flop E4 pin 9 is sent to the M7279
FIFO Buffer Module. The 2.534 MHz signal from
the RO (1) output of counter E5 is sent to the M7289 System Control and
Receiver Scanner Module.
4.4

44.1

LINE PARAMETER CONTROL MODULE M7288

Introduction

The M7288 Line Parameter Control Module contains Jogic that performs the

by the System Control Register (SCR):
Selects transmitter speed
Selects receiver speed

Selects half duplex or full duplex operations

Enables auto-echo feature

4-16

following functions for the line selected

Signals for controlling these functions come from the outputs of the Line Parameter Register (LPR) and the control

strobe generation logic on the Current Address and Address Selector Module M7277. The function signals are sent
from the M7288 Line Parameter Control Module to the appropriate UART inputs. Signals for controlling other
UART functions are sent directly from the LPR to the UARTs. These other functions include character length,
number of stop bits, parity enable, and odd or even parity.

The physical layout of the M7288 module corresponds with the nine sheets of logic (drawing D-CS-M7288-0-1,
sheets 3 — 11) as shown in Figure 4-12. Sheet 3 contains the buffers for incoming signals. Transmission speed

selection logic is shown in the following sheets:
Sheet 4 for lines 00 — 03

Sheet 6 for lines 04 — 07
Sheet 8 for lines 08 — 11

Sheet 10 for lines 12 — 15

Logic for receiver speed selection, half duplex or full duplex selection, and auto-echo enable is shown in the

4.4.2

Sheet 5 for lines 00 — 03

following sheets:

Sheet 9 for lines 08 — 11

Sheet 7 for lines 04 — 07
Sheet 11 for lines 12 — 15

Signal Buffering

Nearly all the signals sent to the M7288 module are buffered before being used. Buffering is necessary to provide

adequate drive for the multiple use of these signals.

All the buffering is provided by 11 type 7437 2-input NAND buffers that are shown in print D-CS-M7288-0-1, sheet
3. Each of the 16 selectable transmitter/receiver speeds is buffered twice. This requires 32 buffers or 8 type 7437
packages (E66, E67, E69, E70, E72, E73, E74, and E75). For example, signal 50 BAUD H on module pin FP1 is
buffered by E69 to provide TOP BUFF 50 BAUD H and by E66 to provide BOT BUFF 50 BAUD H. The TOP

BUFF signals are inputs to the top row of 16 type 74150 multiplexers and the BOT BUFF signals are inputs to the

bottom row of 16 type 74150 multiplexers (Figure 4-12).

The speed signals are inverted by the buffers; however, this fact is not revealed in the signal designation. The level
designation for the buffer input and output signals are both represented as highs (H). This is done to obtain
consistency in showing the interconnections between the buffers and other devices. This should not cause any
confusion because the speed signals are clock signals in which edge transitions are more significant than logic levels.

Bits LPR 06 L — LPR 15 L from the LPR are also buffered. Ten buffers or two and one half 7437 packages are used
(E65, E68, and 1/2 of E71). The remaining two gates in package E71 are used to buffer INIT A H from the M7283
module to produce BUFF INIT A L and BUFF INIT B L. These two buffered signals are used to provide adequate
drive for the multiple use of the initialize (INIT) signal.

4-17

|
E70

]

E74

E60
TO1

I—

=67 I £62

]
E72

I
E66 I

—

E44
RO1

El Hl E47

—

E52
I E48
TO3 | ROO

SHEET 8

E58

TO8

TO9

E54

T10

I
|

E40
RO2

I
|

E43

RO8

E42

RO9

E39 E35

R10

Figure 4-12

E31

' T2

E27
— _

DI
]

|
I

El2
RO5

E23 |

-~ SHEET (0
E26

E22

E18
T15

T
|

RO6

RO7

_ _ _ _

e¢

SHEET 7

E20
| El6
TO7
RO4
I

|
E

E24
TO6

E34 | | &30
R11

E28
TO5

E38

SHEET 6

]

E36
| E32
RO3 || | To4

SHEET 9

E50 | E46

SHEET 5

SHEETS |£es I
E

E56
T02

£69 I

—

SHEET 4

. || E64
TOO
E75

— e

SHEET Ii

E14| | E10

| R12

R13

R14

R15

|
|

|
.t Fl

Component Layout of M7288 Module

11-1734

4.4.3

Opverall Operation

Associated with each of the 16 lines is a transmitter clock multiplexer and a receiver clock multiplexer (Figure 4-13).

Each multiplexer is a type 74150 that selects 1 of 16 data inputs. The 16 data inputs are the buffered speed signals
that are sent to all 32 multiplexers. Input selection is determined by the four multiplexer select lines that select on
an equivalent number basis; for example, if the select lines represent decimal 5, input DO5 is selected and enabled to
the output. The select lines are controlled by signals from the LPR that specify transmitter and receiver speed. For
transmitter speed selection, signals BUFF LPR 10 H — BUFF LPR 13 H are used; and for receiver speed selection,
signals BUFF LPR 06 H — BUF LPR 09 H are used. These buffered LPR signals are sent to 4-bit flip-flop registers

associated with each mult1plexer For the transmitter multlplexers the reg1sters are type 74175 quad D-type
flip-flops. For the receiver multiplexers, the registers are type 74174 hex
D-type flip-flops. The two extra

used for the auto-echo enable signal and the half duplex, full duplex selection signal.

The flip-flop outputs are enabled to the mu]tiplexer select inputs when the flip-flops are clocked. Sixteen clock
signals are used (one for each line). They are generated on the M7277 module as a function of the line selected by
the System Control Register and are called CONTROL STROBE LINE 00 H, 01 H, etc. The 74175 package
associated with the transmitter multiplexer for a particular line, and the 74174 package associated with the receiver

multiplexer for the same line, use a common clock signal. Thus, the desired transmitter and receiver speeds are sent
to the appropriate UART when the selected clock (Control Strobe) signal is enabled.

l__?;
STB

E48

74150

> CLOCK [P~LINE OO H
RECEIVER

RX CLOCK

SPEED
MUX

STB

E64
74150

16 BUFFERED[

TRANS

SPEED SIGNALS

CLOCK

SPEED
MUX

£63
74175

BUEE LER 19 H- :> QUAD
FLIP

FLOP

TX CLOCK

SELECT INPUTS
BITS 10-30

]

BITS 06-09
.

o6
BUFF LPR 06 H-

E47
78174

AND BUFF LPR 14 H)
15 H

FLIP
FLOP

BUFF LPR 09 H

CLR CLK

BUFF INIT A L

SELECT INPUTS

PLINE 00 H

HEX

CLR CLK

}—

AE ENAB OO H

HALF DUPLEX 00 H

BUFF INIT B'L ———T

CONTROL STROBE
LINE OO H
H~-1730

Figure 4-13

Block Diagram of Transmitter and Receiver Speed Selection for Line 00

4-19

As previously stated, one bit of the 74174 hex flip-flop package is used to enable the auto-echo feature. The
selection signal for this function is bit 15 from the LPR (BUFF LPR 15 H). Also, one bit is used to select half
duplex or full duplex operation. The selection signal for this function is buffered bit 14 from the LPR (BUFF LPR

14 H). The auto-echo enable and half/full duplex function signals are taken from the output of the 74174 and sent

to logic on the M7289 module.
4.4.4

Transmitter Speed Selection

‘This discussion covers selection of a particular transmitter speed for a desired line. Only one example is discussed

because the process is the same for all 16 lines. The example shows the selection of 110 Baud for the transmitter
used on line 00 (Figure 4-14).

E64 is a type 74150 multiplexer that selects 1 of 16 data inputs. These inputs are the buffered speed signals from
- drawing D-CS-M7288-0-1, sheet 3 (TOP BUFF signals only). Inputs DO1 — D13 are speed signals that originate on

the M4540 Clock Module. Input DOO is the 0 Baud signal-and inputs D14 and D15 are external inputs. The user

can

connect an external clock to these inputs, D14, or D15. Signals of 100, 3600, and 7200 Baud from
the clock module

can be connected to the external inputs or an M401 or M405 Clock Module may be installed in slot EO9 or slot
BO6.
These signals are available on the clock module but are not program selectable except through the external inputs.
First set SCR bits 0 — 3 to all Os to select line 00. Assume that the operation starts with flip-flop register E63
cleared
(all outputs are 0). This selects 0 Baud which turns off the transmitted clock for line 00. Now, it is desired to select
110 Baud for the transmitter on line 00. The program selects the states of the LPR bits to request 110 Baud
as

follows:

LPR Bit

State

These bits are written into the LPR, which is a flip-flop register with complementary outputs. Bits 10 — 13 are taken

from the O-output of the flip-flop.

These signals (LPR 10 L — LPR 13 L) are sent from the M7278 module to the M7288 module and inverted by the

type 7437 NAND buffers to produce BUFF LPR 10 H — BUFF LPR 13 H (drawing D-CS-M7288-0-1,
sheet 3).

These buffered signals are sent to the D inputs of type 74175 quad flip-flop E63. The 1-outputs of this device are
connected to the select inputs (SO — S3) of type 74150 multiplexer E64. When E63 is clocked, the select input
states are the same as those selected by the program to pick the 110 Baud signal.

The clock signal for E63 is CONTROL STROBE LINE 00 H from the Current Address and Address Selector Module
M7277. Normally, this signal is low. When the System Control Register selects line 00 and the program loads the
LPR, the trailing edge of the LOAD LPR H signal triggers 300 ns one-shot E61 on Module 7277 and causes

CONTROL STROBE LINE 00 H to go high. This positive transition clocks E63 and its 1-outputs are sent to the

select inputs of E64. These inputs represent decimal 3 which selects input D03 (TOP BUFF 110 BAUD H). This
signal is enabled to the output of E64 in complemented form as TX CLOCK LINE 00 L which is sent to the
transmitter clock input of the UART for line 00.

4.4.5

Receiver Speed Selection

Receiver speed selection is very similar to transmitter speed selection. This discussion shows the selection of 600
Baud for the receiver used on line 03 (Figure 4-15). The discussion is not detailed because of the similarity to the
transmitter speed selection covered in Paragraph 4.4 .4.

Multiplexer E36 is used for line 03 and its associated flip-flop register (E35) is a type 74174 that contains six D type

fiip-flops.

4-20

SENT TO INPUTS OF ALL
16 74150S FOR

HELD LOW TO ENABLE

TRANSMITTER SPEED

E64 CONSTANTLY

SELECTION

£c>9_-1=16

TOP BUFF EXT B BAUDH

TOP BUFF EXT A BAUD H

TOP BUFF 9600 BAUD H

TOP BUFF 2400 BAUDH
TOP BUFF 1800 BAUD H

D14

DI2

DIO

TOP BUFF 1200 BAUD H

TOP BUFF 600 BAUD H

TOP BUFF 300 BAUD H

TOP BUFF 200 BAUD H

TOP BUFF 150 BAUD H

TOP BUFF 134.5BAUDH

TOP BUFF 110 BAUD H

TOP BUFF 75 BAUDH

TOP BUFF 50 BAUD H

TOP BUFF ZO BAUDH

UART TRANSMITTER

CLOCK INPUT

DI5

TOP BUFF 4800 BAUDH

SELECTED SPEED TO

STB

74150 TRUTH TABLE

INPUTS | INPUT/BAUD

£64

oIS

s3Ts2ls1 lso] SE-ECTED

24150

o| o| o| o|bpoo-zeErO

10EU2

008

f o—— Tx cLoCK

LINE OOL

DO7

D06

0|1|O|DO2-75

°l0

03-110

o{1]|0]|0|D04-1345
o|1|0]|1|D05-150

o|1!1]|0|D06-200

pos

o|1|1]|1 |po7-300

Do4

DO3

1|0|

D02

poo
s3

1 | DO1-50

olo

505

o|pos-600
-

1]0]|0/1|D09-1200

0]|D0O-1800

10|

1|1}

0|o0]|DI2-4800

11o]1]1|p1-2400
SO

1t11]0]1|013-9600

|15

1|1

1]1]|0|DI4-EXTA

111]1|1]|p5-EXT
B

12
05
04

D2 ge3

74175

15
R3(1)
|10
R2(1)

R1(1)

GENERATED ONM7277 UNDER

ro(1)1-22

CONTROL OF SCR TO SELECT

DESIRED LINE. ONLY DESIRED

CLR

oLk

74175 1S CLOCKED.

L CONTROL STROBE LINE OOH
09

BUFF LPR10O H

4BIT BUFFERED BCD WORD FROM

BUFF LPR 11 H

LPR TO SELECT DESIRED SPEED.

BUFF LPR 12 H

SENT TOALL 16 74175S.

BUFF LPR 13H
BUFF INITA L

CLEARS ALL 16 7#4175S
SIMULTANEOUSLY WHICH
SELECTS ZERO BAUD

11732

Figure 4-14

Typical Transmitter Speed Selection Circuit

4-21

SENT TO INPUTS OF ALL
16 74150S FOR RECEIVER
SPEED SELECTION.

HELD

TOP

BUFF EXT B BAUD

TOP

BUFF EXT A

TOP BUFF 9600

TOP

pis

17
BAUD H——1"d

pig

BA
H UD
— 8| p13

74150

SELECTED SPEED

BUFF 2400

BAUD
H

TOP BUFF 1800

BAUD
H

TOP BUFF 1200

BAU
H —221
D pog

600

300 BAUDH — 2 po7

TOP

200

BAUDH —23] pos

150 BAU
H ——93]
D pos

TOP BUFF

134.5 BAUD
— 2%
H pog

TOP BUFF

110 BAUDH —95] po3

TOP BUFF

75 BAUD
H

TOP BUFF

50 BAUD H —27 po

TOP BUFF

10 ¢cv2 Rx cLock

pos

TOP BUFF

RECEIVER

INPUT

pio

TOP BUFF

BAUDH——221

UART

CLOCK

TOP BUFF
BUFF

—2 pj2
211

CONSTANTLY

STB

H ——°|

TOP BUFF 4800 BAUDH

LOW TO ENABLE

E36

LINE O3L

z0 BAU
H —281{
D poo
S3

TRERTRE

SENT TO LOGIC
M7289

IMPLEMENT

THE DESIRED FUNCTION

R35

74174

14 1ps

13104
L1l e
081 p,
041 p

CP2

rRa () H2
r3() O

CRS _ \ALF DUPLEX 03H

r2( }O7
R |25

03|

RS (1) |2

row
CLR

[

AE ENABLE O3H

GENERATED ON M7277 UNDER

192

CONTROL OF

SCR TO SELECT

DESIRED LINE. ONLY DESIRED

CLK

74174

09
CONTROL STROBE

BUFF LPR ISH}
BUFF LPR 14H
BUFF

1S CLOCKED.

LINE O3H
CONTROLS AUTO ECHO ENABLE
AND

HALF/FULL DUPLEX OPERATION

LPR O6H

BUFF LPR O7H
BUFF LPR O8H
BUFF

LPR O9H

BUFF

INIT BL

4 BIT

BUFFERED

BCD WORD

SENT

TO ALL 16

741745

FROM

LPR TO SELECT DESIRED SPEED.

CLEARS

ALL 16 74174
S

SIMULTANEOUSLY

SELECTS

ZERO

WHICH
BAUD
11-1731

Figure 4-15

Typical Receiver Speed Selection Circuit

4.22

To select 600 Baud, the program first sets SCR bits 03 — 00 to 0011 to select line 03 and then writes into the LPR
as follows:

LPR Bit

State

These bits are taken from the O outputs of the LPR and inverted by the M7288 buffers. This produces signals BUFF
LPR 06 H — BUFF LPR 09 H which are sent to E35 to control the select inputs of E36. When E35 is clocked, the
select input states represent decimal 8 which selects input DO8 (TOP BUFF 600 BAUD H).
The clock signal for E35 is CONTROL STROBE LINE 03 H which is generated on module M7277 at the conclusion
of the instruction that loaded the LPR. The output of E36 is RX CLOCK LINE 03 L which is sent to the receiver
clock input of the UART for line 03.

4.4.6

Auto-Echo Enable and Half/Full Duplex Control Signals

The auto-echo enable and half/full duplex control signals for each line are taken from the type 74174 flip-flop
register associated with the receiver speed selection logic. LPR bit 14 is the half/full duplex control signal and LPR

bit 15 controls the auto-echo enable bit. If the program sets LPR bit 14, half duplex operation is selected. If the
program sets LPR bit 15, the auto-echo feature is enabled.

These signals are taken from the O outputs of the LPR and inverted by the M7288 buffers. This produces signals
BUFF LPR 14 H and BUFF LPR 15 H which are sent to all 16 type 74174 hex flip-flop registers.

For a specific example, assume that it is desired to select full duplex operation and enable the auto-echo feature for
line 03. First, the program loads the SCR to select line 03. Next, the LPR is loaded to select full duplex (LPR bit 14
is cleared) and auto-enable (LPR bit 15 is set). The complements of bits 14 and 15 are taken from the LPR, inverted
by the M7288 buffers, and applied to flip-flop register E35. BUFF LPR 14 H, which is low, is sent to E35 input D4.
BUFF LPR 15 H, which is high, is sent to E35 input D5 (drawing D-CS-M7288-0-1, sheet 5). At the end of the LPR
load operation, CONTROL STROBE LINE 03 H is generated to clock E35. Signal HALF DUPLEX 03 H is low and
signal AE ENAB 03 H is high. These signals are sent to logic on the M7289 module to implement the requested
functions; that is, to operate line 03 in full duplex and to enable the auto-echo feature on line 03.
4.5

4.5.1

TRANSMITTER SCANNER

Introduction

The transmitter scanner logic is located on the M7277 Current Address and Address Selector Module (drawing
D-CS-M72770-1, sheet 4). This discussion deals with the detailed operation of the scanner.
4.5.2

Functional Description

Part of the process used to initiate transmission requires that the bit in the Buffer Active Register (BAR) associated
with the selected line be set. This bit is ANDed with the Transmitter Buffer Empty (TBMT) flag from the associated
UART (Figure 4-16). This flag is set when the UART data bit Holding Register can be loaded with a message
character. The TBMT flag and BAR bit are ANDed for all 16 lines (AND gate E70 shown for line 15). The AND gate
outputs are sent to the inputs of E45 which is a type 74150 16-to-1 multiplexer. The E45 select inputs are

controlled by the outputs of counter E49 which is a type 74193 synchronous 4-bit binary counter. It is connected
to count up from decimal O to 15. If no line has its BAR bit set, the scanner continually scans the lines sequentially.
When it is desired to initiate transmission on a particular line, its BAR bit is set by the program after first having
loaded a current address and byte count for that line. The UART associated with this line sets its TBMT flag when it
is ready to accept a character for transmission.

4-23

AE GO L

Dc
E35

TBMT

LINE 15

H ——

STB

BAR 15 H—

D15

D14

D13
D12

D11
D10
D09

po8

Each input is an

AND of a BAR bit

DO7

and TBMT flag for
the associated line

E45

74150

f P—

DO6

DO5
D04

D03
D02

DO1
.

DOO

(%%

. S3

+3V

Lfl')
Eoo

PRE

1 8
TIMEOUT (1) L

E73

T4H74

1 c

o 9

INIT L

AE GO L — E72

=
=

1 6
E73

CLR

T4HT74

TRAN scan 3 |
CLK

FREQUENCY

DIVIDEC

E49

74193

R2(1)
R1(1)
RO(1)

CUP CDN

CLR

INITA H

+3V

CLR
4

+3V

XMIT STATUS L

INIT L

NPR COMPLETE L :.‘—_
ti-1770

Figure 4-16

Transmitter Scanner Logic

The ANDing of BAR XX H and TBMT LINE XX H puts a high on input XX of the multiplexer. When line XX is
scanned, a low signal is generated at the multiplexer output. This signal is sent to the D-input of the SCANNER
STOP flip-flop which is a redefined flip-flop. When the SCANNER STOP flip-flop sets, SET REQUEST H goes high.
This signal is sent to the M796 Unibus Master Control Module to initiate the action that allows the DH11 to become
bus master and take the message to be transmitted from memory. A low signal from the SCANNER STOP flip-flop
0O-output disqualifies gate E72 and puts a high on the D input of the FREQ DIV C flip-flop. This redefined flip-flop
is reset and it stays in this state as long as E72 is disabled. This eliminates the source of clock pulses for the E49
counter. When a character has been loaded into the UART from memory, NPR COMPLETE L is asserted which

clears the SCANNER STOP flip-flop and allows the scanner to restart. It scans until another line is found that has its
BAR bit set. When the transmission on a line is complete, the BAR bit is cleared. NPR COMPLETE L occurs once

per character. The BAR bit is cleared once per message.
4.5.3

Logic Description

To understand the basic operation of the scanner, assume that no transmitters are activated and a previous
transmission has just been completed. No BAR bits are set which means that bits BAR 00 H — BAR 15 H are all low.
As a result, the outputs of all 7408 AND gates are low (Figure 4-16). These 16 low signals are sent to the inputs of

E45 which is a type 74150 16-to-1 multiplexer. Input selection is determined by the four multiplexer select lines (SO
— 83) which constitute a 4-bit BCD word. Selection is made on an equivalent number basis; for example, if the select
lines represent decimal 6, input D06 is selected and enabled to the output. The multiplexer is enabled by a low signal
to the strobe (STB) input. This signal is AE GO L and is inverted by E35 before being applied to the strobe.
Normally, AE GO L is high, and after inversion, supplies the required low strobe signal. When the auto-echo feature
is enabled, AE GO L is low and the multiplexer is disabled (output is high).

The multiplexer select inputs (SO — S3) are controlled by the outputs of counter E49. It is a type 74193
synchronous 4-bit up/down counter. In this application, it is connected to count up only by sending the clock signal
to the count up (CUP) input while the count down (CDN) input is held high. The data inputs (DO — D4) are not
used and the load input (LD) is disabled by connecting it to +3 V. The counter cannot be preset so it counts up from

decimal 0 — 15, overflows, and continues up counting and overflowing as long as clock pulses (positive transitions)

are supplied.

Under the assumed condition that no transmitter is activated, all inputs to the multiplexer are low. As the counter is

incremented and each low input is scanned, the multiplexer output (f) remains high. Note that the output is the
complement of the selected input. This signal is sent to the D input of the redefined SCANNER STOP flip-flop. This
flip-flop controls the scanner operation by allowing or disallowing clock pulses to be sent from the FREQUENCY
DIVIDE C flip-flop 1-output to the counter clock input. When the multiplexer output is low, the scanner stops;
when the multiplexer output is high, the scanner continues to increment.

Assume that the SCANNER STOP flip-flop has been cleared by NPR COMPLETE L. In this state, the 1-output (SET
REQUEST H) of the SCANNER STOP flip-flop is low, which means that no action is taken by the M796 module to
make the DH11 bus master. The O-output of the SCANNER STOP flip-flop is high and is sent to E72 which is a
4-input NAND gate. The other inputs to E72 are: the O-output of the FREQUENCY DIVIDE C flip-flop,
TIMEOUT (1) L, and AE GO L. The last two mentjoned signals are normally high. When either signal is low, the
scanner stops. The operation of TIMEOUT (1) L and AE GO L are described in subsequent paragraphs. For now,
assume that they are both high.

The FREQUENCY DIVIDE C flip-flop is connected to operate in the toggle mode. The O-output of the flip-flop is
fed back to the D input via gate E72 so that the flip-flop changes state at each positive edge of the clock signal
(TRAN SCAN CLK H = 1.2 MHz). This produces pulse trains at the flip-flop 1 and O outputs that have a frequency
of 600 kHz.

4-25

The 1-output of the FREQUENCY DIVIDE C flip-flop is sent to
the count up (CUP) input of counter E49. These
pulses increment the counter (transmitter scanner). The l-output
is also sent to pin 4 of 2-input AND gate E64 via
the 30 ns delay line DL3. The O-output of the FREQUENCY DIVIDE
C flip-flop is sent to gate E72 and to the other
input (pin 5) of gate E64. The output of E64 is a positive pulse of
approximately 30 ns that starts on the negative
transition of the
FREQUENCY DIVIDE C flip-flop output. This sequence is illustrated
in the timing diagram shown
in Figure 4-17. The output of E64 is the clock signal for the SCANNER
STOP flip-flop.

f— 833ns —]
TRAN SCAN CLK H
TO E73 PIN 3

f=1.2MHz

$=600KHz

D INPUT E73 PIN 2

———
1 QUTPUT E73 PIN 6

TODL3 PIN 1

166ps

——

___|
—=|

|+——30ns

OUTPUT DL3 PIN 3

TOE64PIN 4 ____|

0 OUTPUT E73 PIN 5

TO E64 PIN 5

SCAN STOP CLK

E64 PIN 6

ANDed at E64

to generate
—————— | SCAN STOP CLK

l
—I

_-I
tH-1762

Figure 4-17

Timing Diagram for Generation of Scanner Stop Flip-Flop Clock Signal

To summarize, as long as the multiplexer output is high, the SCANNER
STOP flip-flop is cleared and the
FREQUENCY DIVIDE C flip-flop continues to toggle. Counter E49
is incrementing and the scanner is operating.
Assume now that transmission is desired on line 12. BAR 12 H is
set by the program and UART number 12 asserts
TBMT LINE 12 H. This occurs whenever the transmitter holding buffer
in UART number 12 is empty. Input D12 of
multiplexer E45 is now high. When counter E49 reaches the count
of 12, input D12 is enabled to the output of E45
which now becomes low. This puts a low on the D input of the SCANNER
STOP flip-flop. On the next positive edge
of the SCANNER STOP clock signal, the flipflop is set. Its 1-output
(SET REQUEST H) is high which initiates

action in the M796 module to make the DHI1 bus master. The
SCANNER STOP flip-flop O-output is low which

disables gate E72. This puts a high on the D input of the F REQUENC
Y DIVIDE C flip-flop. On the next positive
edge of the clock signal (TRAN SCAN CLK H), the flip-flop is reset.
The FREQUENCY DIVIDE C flip-flop remains
in the reset condition which inhibits the clock signal to counter E49
and inhibits the generation of clock signals to
the SCANNER STOP flip-flop which remains in the set condition. The
scanner stops at input D12 until the loading
of the character to be transmitted is complete, at which time NPR
COMPLETE L clears the SCANNER STOP
flip-flop and allows the scanner to resume operation.
The scanner can be stopped when TIMEQUT (1) L to gate E72
is asserted. This occurs when the current address
logic tries to address non-existent memory. It is also stopped when
AE GO L is asserted. This occurs when the

auto-echo feature is enabled.

4-26

4.6

CURRENT ADDRESS REGISTER AND CONTROL LOGIC

4.6.1

Introduction

The Current Address Register (CAR) and associated control logic are located on the M7277 Current Address and
Address Selector Module (drawing D-CS-M7277-0-1, sheets 5 and 6). This discussion deals with the detailed
operation of this logic and is divided into three parts. The first part describes how the CAR is loaded, incremented,
and read. The second part describes the logic that controls the operation of the CAR. The third part describes the
byte control logic which is associated with the CAR.
4.6.2

Current Address Register

4.6.2.1 Functional Description — In the transmit mode, the program loads the Current Address Register (CAR)
with the memory address of the first character of the message to be transmitted on the selected line. The program
also loads a byte count and sets a BAR bit. Using an NPR, the DHI11 becomes Unibus master and places the CAR
address on the Unibus address lines. A DATI is performed which brings the desired character (as a byte) from the
memory to the DH11. During this transaction, the CAR is incremented by 1 so that it contains the address of the
next character to be retrieved from memory during the next DATI transaction. This process continues until the last
character is transferred. The CAR can be read by the program.

4.6.2.2 Components — The CAR consists of the following major components (drawing D-CS-M7277-0-1, sheets 5
and 6):

Five type 7489 64-bit read/write memories (E4, E11, E18, E25, and E31), with common address lines

Five type 74193 synchronous 4-bit counters (E5, E12, E19, E26, and E32), cascaded to provide an

and enabling inputs to form a 16-word by 18-bit memory.

18-bit counter.

Five type 74157 quad 2-line to 1-ine multiplexer (E6, E13, E20, E27 and E33) with a common select
signal to provide an 18-bit multiplexer.

A multiplexer, counter, and memory are interconnected to accommodate 4 bits of the CAR. All but 2 bits of one
group of devices (E31, E32, and E33) are used to handle the 18-bit capacity of the CAR. A typical 4-bit section of
the CAR is shown in Figure 4-18.

E4 is a type 7489 64-bit read/write semiconductor (TTL) memory organized in 16 4-bit words. The 16 words are
addressed by the 4-bit binary word sent to address lines AO — A3. The 4-bit data word is sent to inputs DO — D3.In
this application, the enabling input (ENB) is permanently held low; therefore, for a selected word, a write operation
is performed when the write (WR) input is low and a read operation is performed when the write (WR) input is high.
A write operation places the input data into the selected word. In a read operation, the complement of the
information that has been written into the selected word is non-destructively read out at the four outputs.

E5 is a type 74193 synchronous 4-bit counter. The data inputs are DO — D3 and the corresponding outputs are RO

(1) — R3 (1). It is operated in the count up mode by holding the count down (CDN) input permanently high while
applying clock pulses to the count up (CUP) input. The positive (trailing) edge of the clock pulse increments the

counter. The outputs can be preset to any state by entering the desired data at the data inputs while the load (LD)
input is low. Counters are cascaded in the CAR by connecting the carry (CRY) and borrow (BRW) outputs to the
count up (CUP) and count down (CDN) inputs, respectively, of the succeeding counter.

E6 is a type 74157 quad 2-line to 1-line multiplexer. The four outputs (fO — f3) represent either the A word input or
the B word input as selected by the state of the select (SO) input. The strobe (STB) input is permanently held low,
which enables the multiplexer; with SO low, the A word is selected and with SO high, the B word is selected.

4-27

TO CDN input of
Next Counter

ADRS TO BUS L
———

—

BUS DATA O3 L

c[>6
E10
-

120_fl

)

BUS DATA 02 L r‘:fl9\
E4

BUS DATA Of L

%%
O

BUSDATAGO L | 4

1
=

M7278 MODULE

—

~_| BUF

l/ 3

es
|
N
!

B——-{>—!
s

—— ——

02 H
—

3————D
s

]

TO CUR
foow
Coun'er—l

From
CAR Control
Logic E50 pin 1‘1

——-—-——g?\
g? :
—
CAO2H

A3 74157
E6
A2

MUX

E’:

CRY BRW

74193
R2(1)

DO
CLR

R1(1)

RO(1)

CON

CUP

J_"

M3(1) D——l{/\

£3

7489
D2

COUNTERj

R3(1)

WR ENB

M2(1)

M1 (1) D—f{>
€3

MO(1) D——fiD
A2

13 BUS AO3 L

10 BUS AO2

MEMORY

£z

‘
- E2

» ) 1_BUS AOO L

+3V

Z>E3

DATA STROBE H :I@o——‘
LOAD CA H

END CYCLE H

SCR 03

ADRS TO BUS L ———

& 10

MEM ADD SOURCE SEL

—l

H ————— B0

MEM ADD D H

MEM

MEM ADD B H

MEM ADD A H

XMIT SCAN 03 H————————a0

SCR 02

H ———————{B1

74157

XMIT SCAN 02 H —————— a1

MEM

SCRO1

H————————
183

XMIT SCAN O1 H ———————
{23
SCR 00

H —————— B2

XMIT SCAN 00

H ———— a2

MUX

ADD C H

HNn-1774

Figure 4-18

Logic Diagram of One Section (Bits 00 — 03) of Current Address Register

) 4 BUS AO1 L

8¢
¥

—— e e e

Figure 4-18 shows another type 74157 multiplexer (E48) whose outputs are sent to the address lines of all five type
7489 memories. This multiplexer is used because the address of the selected word has two sources: the transmitter
scanner which is used during NPR transfers, and the System Control Register which is used when the program reads
or writes into the CAR.

4.6.2.3 Loading the CAR — Assume that a transmit operation is to be performed and the System Control Register
(SCR) has selected the desired line. The line selection bits (SCR 00 H — SCR 03 H) of the SCR are sent to the B
input of multiplexer E48.

The program now desires to load the CAR with the 18-bit memory address of the first character of the message to be
transmitted on the selected line. The processor addresses the CAR, asserts the Unibus control lines for a DATO
transaction, and places the data on Unibus data lines D(15:00). This data represents 16 bits of the 18-bit address
required. Bits 16 and 17 are determined by signals SCR 04 H and SCR 05 H from the SCR which has been
previously loaded by the program. They are sent directly from the SCR to CAR multiplexer E33 (drawing
D-CS-M72770-1, sheet 5). Unibus bits D(15:00) are picked off the bus by type 380 bus receivers, buffered, and sent
to CAR multiplexers E6, E13, E20, and E27 as signals BUF DATA 00 H — BUF DATA 15 H. Signal ADDRS to BUS
L is high because this is a programmed CAR load, not an NPR. It is inverted and sent to the select (S) inputs of the
five CAR multiplexers. This enables BUF DATA 00 H — 15 H, SCR 04 H, and SCR 05 H to the inputs of the five
counters.

The processor addressing the CAR has caused the gating control logic on the M7277 module to assert LOAD CA H.
This signal is sent to the CAR control logic to provide three functions:

Puts a high signal (MEM ADD SOURCE SEL) on the select (SO) input of multiplexer E48 which enables
the B input word (SCR 00 H — 03 H) to the output. The 4-bit binary output fO — {3 represents the
number of the line selected for address loading. This output is sent to the address lines of the 7489
memory to select the proper word into which the address is to be written.

Puts a low on the load (LD) input of the counter which enables the input to the output. This places the

Puts a low on the write (WR) input of the memory which performs a write operation. This operation

current address on the input of the CAR memory.

places the input data (current address) into the selected word.

The output of the memory is the complement of the data just written into it. These 18 bits are inverted and fed
back to the B word input of the CAR multiplexer to be used in incrementing the CAR.

Each bit of the CAR is also inverted and sent to one input of a type 8881 Unibus driver. All 18 drivers are enabled
by a common signal (ADR TO BUS L) when the DHI1 is bus master. This action is described in the following
paragraph.

4.6.2.4 Incrementing the CAR — Assume that the CAR has been loaded with the current address of the first
character to be transmitted. The DH11 becomes bus master through an NPR in order to transfer the character from
memory to the appropriate UART for transmission.

When the DH11 becomes master, signal ADRS TO BUS L is asserted by the M796 module. This signal is inverted and
enables all 18 Unibus drivers to place the current address on the Unibus A lines. The current address to be applied to
the Unibus A lines is selected by signals MEM ADD A H through MEM ADD D H, which are the address selection
bits for the CAR 7489 memory. They are the outputs of multiplexer E48 and are enabled from the A word input
because the select input (MEM ADD SOURCE SEL) is low. The A word consists of signals XMIT SCAN 00 H
through XMIT SCAN 03 H from the transmitter scanner. They represent the position of the scanner or the number
of the line from which the transmission is to occur.

4-29

The current address is also sent to the B word input of the CAR multiplexer. An inverted ADDRS TO BUS L signal

selects this information as inputs to the CAR counter.

The M796 module asserts DATA STROBE H which enables the load (LD) input of the counter which transfers

information into the counter.

The M796 module asserts END CYCLE L which is buffered and sent to the count up (CUP) input of CAR counter
ES associated with current address bits 00 — 03 (drawing D-CS-M7277-0-1, sheet 6). The counter is clocked by the
positive edge of the END CYCLE L pulse. This counter is incremented by 1 and this count, if necessary, is rippled

through the rest of the counters. The counter output, which is the memory input, now represents the current

address plus 1. The CAR control logic provides a delayed path for the END CYCLE L pulse to the write input (WR)
of the CAR memory. This input is driven low and the memory performs a write operation that places the input data
(CA + 1) into the selected word. This operation is delayed to allow time for the counter outputs to settle after
incrementation.

The current address has been incremented and stored awaiting the next NPR cycle. This process is repeated until

last character has been transmitted.

the

4.6.2.5

Reading the CAR — Assume that the program desires to read the current address on the line selected
by the
SCR. The processor asserts the Unibus control lines for a DATI and addresses the CAR. When the CAR address
is
decoded, the M7277 module asserts READ CA L, DATA TO BUS H, and DATA SOURCE AH, BH, CH.

Signal READ CA L puts a high on the select (S) input of multiplexer E48 which enables the B word
input
H — 03 H) to the address lines of the CAR memories. This selects the desired memory word as
a

(SCR 00

function of the

SCR. The write (WR) input of the memory is high (disabled) which indicates a read function. This places
the

complement of the contents of the selected word on the memory output. All 18 bits are inverted and sent

to module

M7278. Bits 00 — 15 are identified as CA 00 H — CA 15 H. Bits 16 and 17 are identified as SSR 06 H and SSR 07

respectively.

The M7278 contains a multiplexer that muitiplexes all 16 bits of the 8 DH11 registers and enables them to
16
Unibus drivers. The multiplexer consists of 16 type 74151 8-ine to 1-line multiplexers. Figure 4-19 shows the
select

input logic and the section for bit 00 (multiplexer E43). Bit 00 from each of the DH11 registers is sent to
inputs DO
— D7. Input selection is made by signals DATA SOURCE AH, BH, and CH which are sent to select inputs
S0, S1,
and S2, respectively. Only the 1-output (pin 05) is used. It is connected to a type 8881 Unibus driver that is enabled
when DATA TO BUS H is asserted.

In this case, when the CAR address is decoded, DATA SOURCE AH, BH, and CH select input D3 and DATA

TO
BUS H enables this input to the Unibus. This transaction reads only BUS A 00 L — BUS A 15 L that are represented

by signals CAOOH — CA 15 H. Bits BUS A 16 L and BUS A 17 L are represented by SSR 06 H and SSR 07 H which
must be read by performing a DATI on the SSR.

4.6.3

CAR Control Logic

In the previous discussion of the CAR loading, incrementing, and reading operations, certain control signals are

mentioned

but

not

described.

This

paragraph

describes

the

logic

that

generates

these

signals

(drawing

D-CS-M72770-1, sheets 5 and 6). Loading the Byte Count (BC) Register is also described because it shares

the CAR control logic, with the few exceptions that are described in Paragraph 4.7.

some of

Figure 4-20 is a detailed diagram of the CAR control logic plus timing diagrams for the CAR loading and

incrementing operations. The discussion is divided into three parts: Joading the CAR, incrementing the
CAR, and

loading the BC register.

\V/

NATATO BUS H

SSR 00 H —={ D7

BAR OOH
BC

—05

E43

74151

OOH——D4
]
OOH——D3

LPR 00 H — 2 D2
NCR 00 H —> b1
scr 00 H — po

M7278 MODULE

_______

f [0—— UNUSED
6

_—

BUSAOIL

[s2 181

IgAPTUAT

180

0{0|0|DOSCR
o|o|

1]|D1 NCR

DATASOURCE | O | 1| O|D2LPR
ol1]1|D3cA
BH
1|o0{o{pasc

E44

_q g1 }2

INPUTS

—

L
BUS AO2

—41
[

—

DATA SOURCE

E44
e El

SELECT

M7277 MODULE

L
BUS AO3

1 Bus pATAOOL

L‘fl

sTE

&—DATA SOURCE

él

E44

1]0]|1|D5BAR
1/1|0|06BCR
11111107 sSR

L
1-1763

Figure 4-19 Logic Diagram for Bit 00 of Registers Multiplexer

4.6.3.1 Loading the CAR — During the CAR loading operation, as described in Paragraph 4.6.2.3, signal LOAD CA
H is asserted. It is sent to pin 3 of NOR gate E57 whose output (pin 1) sends a low to the load (LD) input of the
CAR counter.

When LOAD CA H goes high, the positive transition clocks the WRITE CA flip-flop. The D input of this redefined
flip-flop is connected to ground (logical 0). Therefore, it is set and its (1) L output (pin 9) is sent to ES5 pin 9,
where it is inverted and sent to the select (S) input of multiplexer E48. This causes the CAR memory address lines to
be connected to signals SCR 00 H — SCR 03 H.

The (1) L output (pin 9) of the WRITE CA flip-flop is also sent to pin 12 of gate E5O0. This low signal partially
qualifies E50; its other input (pin 11) is connected to the 0-output of one-shot E63 which is high because E63 is not
triggered.

LOAD CA H is inverted by pins 11 and 13 of gate E57 and sent to the input (pins 3 and 4) of one-shot E62. The
negative edge at this input triggers E62. A 90 ns positive pulse is produced at the 1-output (pin 6) of E62 and is sent
to the input (pins 3 and 4) of one-shot E63. When the 90 ns pulse times out, the negative edge triggers E63. A 60 ns
negative pulse is produced at the (1) L output (pin 1) of E63 and is sent to pin 11 of ES0. This qualifies E50 and its

high output (pin 13) is inverted by another E5SO gate and sent to the write (WR) input of the CAR memory. This
signal is delayed approximately 90 ns from the time that LOAD CA H goes high, allowing the buffered data leads to

settle at the inputs of the CAR location selected by SCR 00 H — SCR 03 H.
4-31

ADDRS TO BUS L [@© l

{ (-

[
pATA sTROBE H (D)

ese | ©

|12

WRITE

LOAD BCH

100ns

END CYCLEL @

220ns

—

e D BC MEM

WRITE
(To BC

ofP—

10
min-JIRN.

To 8 Input

INITIALIZE H

of word
gddrene

\fl 60ns

1-shot EG8

0 output pin 1 @

READ CA+BC+SSR
L

{=shot E67
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"
®

E87

Deiay iine DLZ

input pin { @

Delay

D D

—-|30an—

line DL
2

yInpuf pin.3 @
—
Gate

ANDegd

E62 | |

+3V—

74121

gss

S0ms | ¢

intput pin 13 @

—0

° °_?

E53

71 i

s@ - E50/

t‘

)

£ E50

Do To WR input

ES?

of CAR cpounfer

inpu

of CAR memory

Gate ES3
output pin 11

12_

NPR COMPLETE L (@

';_
.

Timing Diagram For Incrementing Operation

LOAD CAH

1 D'g——

ESE

WRITE | o
| caA

Ti0
@
LOAD CA H

DATA STROBE H

LOADBCH

j:”

To LD input of

module

o
ADRS TO BUS L

90ns

1-shot E63
1 output pin 6

60ns

1-shot E63
O output pin 1

+3V—

E6?

320m

END CYCLE H
—END

Delay line DL1
intput pin 1

E69

—{

CYCLE

AL ®
1

To enable unibus

drivers

‘D )
E3

A(17:00)

Z:RS input of

) v _)

réve

‘

60ns

To CUP inpu!

of CAR counter

30ns |

To LD input

BC counter

3 % On 7278

WRITE CAff EB6
O output pin 9

1-shot E62
1 output pin 6

opP—

)

E74

> -® mma
1

ES3

NPR

COMPLETE L

Delay line DL1

output pin 3
——————

ANDed to

fgive

NCTE:
Circled numbers correspond to

waveforms on timing diagrams

Gate E64
input pin12

1M-1768

Gate E64

output

pin11

30ns
i-1766

Timing Diagram For Loading Operation

Figure 4-20 CAR Control Logic and Timing Diagrams

4-33

The (1) L output of oneshot E63 is also sent to the input of a pulse generator consisting of inverter E74, 30 ns

delay line DL1, and 2-input AND gate E64. The output (pin 11) of E64 is low when one-shot E63 is not triggered
and during the period that E63 is triggered. However, when E63 times out, and for 30 ns after, E64 pin 11 is high.

This signal is inverted by ES7 and sent to the clear input (pin 10) of the WRITE CA flip-flop.
4.6.3.2

Incrementing the CAR
— During the CAR incrementing operation, the M796 module asserts three

signals: ADDRS TO BUS L, DATA STROBE H, and END CYCLE L. Refer to the timing diagram for the
incrementing operation shown in Figure 4-20.

ADDRS TO BUS L, is asserted first, inverted by E3 pins 3 and 4 and E3 pins 5 and 6 to enable the current address

to the Unibus. It is also inverted by E10 pins 5 and 6 and sent to the select (S) input of the CAR multiplexer, to
connect the CAR memory outputs to the CAR counter inputs.
DATA STROBE H is asserted next and inverted by E57 pins 2 and 1. This low signal is sent to the load (LD) input
of the CAR counter, thus loading the current address into the counter.

END CYCLE H is asserted last, inverted by E69, and sent to the count up (CU) input of the CAR counter. This
signal is also sent to the input (pins 3 and 4) of one-shot E67. The negative edge at this input triggers E67. A 220 ns

positive pulse is produced at the 1 output (pin 6) of E67 and sent to the input (pins 3 and 4) of one-shot E68. When

the 220 ns pulse times out, the negative edge triggers E68. A 60 ns positive pulse is produced at the 1-output (pin 6)
of E68. It is inverted by E50 pin 1 and sent to the write (WR) input of the CAR memory. This signal is delayed
approximately 220 ns from the time that END CYCLE H is asserted to allow time for the CAR counter to reach the
incremented address before the 60 ns pulse writes that value into the CAR location.
The 60 ns negative pulse from the (1) L output of one-shot E68 is sent to the input of a pulse generator consisting of
inverter E74, 30 ns delay line DL2, and 2-input NAND gate E53. This circuit operates like the one described in the

CAR load operation. It produces a 30 ns negative pulse at ES3 pin 11 which is NPR COMPLETE L and is used to
restart the transmitter scanner.
4.6.3.3

Loading the BC Register — Most of the CAR control logic used in the CAR loading operation is used in the

BC register loading operation. An additional flip-flop (WRITE BC) and three gates are used exclusively for the BC
operations.

When LOAD BC H goes high, the positive transition clocks the WRITE BC flip-flop. The D input of this redefined

flip-flop is connected to ground (logical 0); therefore, it is set and output (1) L (pin 5) is low. This signal is sent to
pin 10 of E55, inverted and sent to the select (S) input of the memory address multiplexer (E48) whose outputs are
also used by the BC register memory to select the byte count for the line indicated by signals SCR 00 H — SCR 03
H.

During the BC loading operation, signal LOAD BC H is asserted. It is sent to pin 2 of NOR gate E47 which is located

on the M7278 module. The signal is inverted by E47 and sent to the load (LD) input of the BC counter to load the
present byte count into the byte count counter.

The (1) H (pin 6) output of the WRITE BC flip-flop is high. This signal is sent to pin 9 of 2-input AND gate E64.
The other input (pin 10) of ES50 is qualified when one-shot E63 is triggered. The sequence for triggering E63 is the
same as that described in the CAR loading operation except that the sequence is initiated by LOAD BC H rather
than LOAD CA H. The high output (pin 8) of E50 is inverted by E57 pins 5 and 4 and sent to the write input (WR)
of the BC memory as signal BC MEM WRITE ENAB L. Again E62 produces a 90 ns delay to allow for the byte
count memory data selection and counter loading action described in the previous two paragraphs.

As in the case of the CAR loading operation, when E63 times out, a 30 ns positive pulse is produced at the output

(pin 11) of E64. It is inverted by E57 pins 9 and 10 and sent to the clear input (pin 4) of the WRITE BC flip-flop
which clears it.

4-32

4.6.4

High Byte/Low Byte Selection Logic

When the DH11 becomes bus master and performs a DATI operation, the 18-bit current address is enabled to Unibus

address lines A(17:00). This address specifies a byte (8 bits) of information stored in memory. A low byte consists
of data bits D(07:00) and it has an even address (last binary digit is 0). A high byte consists of data bits D(15:08)
and it has an odd address (last binary digit is 1). The byte, which is the character to be transmitted, must be taken
off the Unibus data lines and sent to the selected UART. The byte control logic selects the proper byte but before it
is sent to the UART it passes through another multiplexer. This multiplexer is controlled by the auto-echo circuit.
During normal operation, it allows the selected byte from memory to pass to the UART for transmission. During the
auto-echo mode of operation, it allows received data to pass to the UART for transmission back to the source.

The byte control logic is shown in Figure 4-21 and drawing CS-D-M7277-0-1, sheet 6. In this discussion, and as
shown in Figure 4-21, the auto-echo selection logic is also included.

Byte identification is determined by sampling the least significant bit (00) of the CAR. Physically, the sampling is
made at the bit 00 output of the CAR memory (E4 pin 5). This bit is connected to pin 5 of gate E50. The other
input (pin 6) of this gate is ADDRS TO BUS L, which enables the current address to the Unibus A lines. The output
(pin 4) of E50 is connected to the select (S) input of the byte selection multiplexer that consists of two type 74157
quad 2-line to 1-line multiplexers (E40 and E43). When the select (S) input is low, input word A or the low byte is
selected; when the select (S) input is high, input word B or the high byte is selected.

Assume that bit 00 of the CAR is a 0 (low) which indicates an even memory address (low byte). This is the actual
state of the bit as stored in the CAR memory. When it is read out, the complement of bit 00 appears at E4 pin 3.
ADDRS TO BUS L is low at this time because it is gating the current address to the Unibus A lines. Under these
conditions, E50 pin 5 is high and E50 pin 6 is low. The output (pin 4) of E50 is low which selects input word A or
the low byte of the multiplexer (E40 and E43). BUFF DATA 00 H — 07 H are sent to input word B of the AE
multiplexer which is also composed of two type 74157 quad 2-line to 1-line multiplexers (E39 and E42). Input word
A of the AE multiplexer consists of the eight received data bits of the UART selected for operation in the auto-echo
mode. The select input of the AE multiplexer is connected to AE GO L which is high when the auto-echo mode is
not enabled. Such is the case in this example. With the select (S) input high, the B word is selected by the AE
multiplexer; this is BUFF DATA 00 H — 07 H.
These bits are sent to the transmitter Data Holding Register for the selected UART. This byte is now identified as
TRANDATA 1 H -8 H.

With the auto-echo feature enabled, AE GO L is low and input word A is selected. This word represents the eight
bits of the selected UART data out lines that are to be transmitted back to the source.

These bits come from the output of eight 2-input NOR gates (4 each E38 and E41). Each gate has two inputs: one
is UC1 RCV DATA XL and the other is UC2 RCV DATA XL. Signal UC1 RCV DATA XL represents a specific bit
from the received data bus on one UART card (UC1). Signal UC2 RCV DATA XL represents the same bit on the

other UART card (UC2). Each of these signals represents the bussing of eight RCV DATA X lines from the eight

RCV DATA X lines from the eight UARTSs on the card; together, they represent the RCV DATA X lines of all 16
UARTSs. During a receiving sequence, only one UART has its Received Data Enabled.
4.7

4.7.1

BYTE COUNT REGISTER

Introduction

The Byte Count (BC) Register and associated output logic are located on the M7278 Byte Count and Master

Registers Module (drawing D-CS-M7278-0-1, sheets 3 and 4). The BC register is loaded similarly to the CAR and
shares the CAR control logic. The BC register is incremented in the same way and at the same time that the CAR is
incremented.

Because the BC register is functionally similar to the CAR, this discussion deals primarily with the unique features of
the BC register.
4-35

When low,selects

low

High when notin auto echo mode.

byte ( Aword).

Selects B word

When high,selects high byte (B word).

/
BUS
DATAO8B8L

—_——

To transmitter holding

}-——

BUF DATA 08 H

BUF DATA A OO
H

*¥Input similar to BUS
DATA

AE GO L

BUF

DATA

09 H

ATA

Of H

BUF DATA

10 H

BUF DATA

11 H

08 L

B3
A3
B2

DATA 03 H

BUF

DATA 12 H

[ORO8H

.« x
E43

BYTE

BUF DATA 02 H B!
SELECTION
T
At
MUX

BUF

BUF DATA

|OR OSH

BUF DATA 02

[OR 1O H

BUF DATA 03

|OR il

AOQ

B3
A3
B2

Ea2

MUX

TRAN

DATA 2 H

TRAN

DATA 3 H

TRAN

DATA 4 H

TRAN

DATA 5 H

TRAN

DATA 6 H

TRAN

DATA

7 H

TRAN

DATA

8 H

TRAN DATA 1 H

Bit 00 from CAR

9¢-v

memory

ESO

—o___J
ADRS

BUS

BUF DATA 04

BUF DATA

05 H

BUF DATA

BUF

DATA OT H

BYTE

BUF DATA 05 OR 13 H

14 H

BUF DATA 07 OR

15 H

MU X

UC! RCV DATA 8 L

a3
f2
E39

74157

MU X

xx — At

BO
8

UC2 RCV DATA 8 L | E38

BUF DATA 06 OR

wx 2]

E40
24157

From bus on UART
card { or UART card 2

DATA 04 OR 12 H

BUF DATA 06 H B1 SELECTION f!
BUF DATA

BUF

H
fO

** Input similar to RCV DATA 8 L

Data Word

HighByte

0dd address.

Last binary d igit
of address is 1.

[

08|07

Byte Control Logic

]

'Even address.

:Lost binary digit
:of address is O.

[

Figure 4-21

Low Byte

11-1773

4.7.2

Byte Count Register

4.7.2.1 Functional Description — In the transmit mode, the program loads the BC register with the 2’s complement

of the number of characters (bytes) to be transmitted. This may be done by means of a MOV # - N, BC instruction,
where N = number of characters to be transmitted and BC is the address of the Byte Count Register. SCR 00 — SCR
03 must first be selected for the appropriate line. During each NPR transaction that brings a character from meinory

to the DHI1, the BC register is incremented. The BC counter is counting the number of characters transferred.

Because it has been loaded with the 2’s complement of the number of characters, the BC counter increments

towards overflow which it reaches when the desired number of characters have been transferred. At overflow, the BC
register output logic generates a signal that clears the BAR bit for the selected line. This indicates that the last
character to be transmitted on that line has been loaded into the transmitter Holding Register of the associated
UART.

4.7.2.2 Components — The BC register consists of the following major components (drawing D-CS-M7278-0-1,
sheets 3 and 4):

Four type 7489 64-bit read/write memories (E31, E32, E33, and E34) with common address lines and

enabling inputs organized to form a 16-word by 16-bit memory.

Four type 74193 synchronous 4-bit counters (E24, E25, E26, and E27) cascaded to form a 16-bit
counter.

Four type 74157 quad 2-line to 1-line multiplexers (E16, E17, E18, and E19) with a common select

signal to provide a 16-bit multiplexer.

The interconnection and function of these devices are the same as those used in the CAR and described in Paragraph
4.6.2.2.

4723 Loading and Incrementing the BC Register — The BC register is loaded with the 2’s complement of the
number of characters (bytes) to be transmitted. This allows the BC counter to be preset to a count that is less than
overflow by the number of characters selected. During each NPR, the counter is incremented and when the last
character is transferred it overflows.

The overflow is used to generate a signal that clears the BAR bit for the selected line. This action is described in the
following paragraph.

4.7.2.4 BC Register Output Logic — The logic that uses the counter overflow to clear the BAR bit is shown in
Figure 4-22 and drawing D-CS-M7278-0-1, sheet 3.

When the BC counter overflows, all 16 outputs (bits 00 — 15) are 0. These 16 signals are sent to four type 8815
4-input NOR gates (E22 and E23) that are shown symbolically as logically equivalent negated input AND gates. The
high output of each of these gates is sent to an input of 4-input NAND gate E15. The output of E15 is driven low
and this negative transition triggers one-shot E14. A 40 ns negative pulse (XMIT FINISHED PULSE L) is generated

at the (1) L output (pin 1) of E14 and sent to both strobe inputs (STBO and STB1) of E48 which is a type 74154

41ine to 16-ine decoder. The low signals on inputs STBO and STBI enable E48, and 1 of 16 mutually-exclusive

outputs is decoded from BCD inputs DO — D3. These decoding signals are MEM ADD A H through MEM ADD D H
from the memory address multiplexer (E48) on the M7277 module. These address lines are the same ones that select
the byte count memory location and represent the transmitter scanner position or the line being serviced. The
appropriate low output from decoder E48 is sent to one input of a type 7408 2-input positive AND gate which is
shown symbolically as a logically equivalent negative OR gate. The other input to the 7408 gate is the inversion of
INIT B H which is high because INIT B H is low (not asserted) at this time. The 7408 output is low and a CLR BAR
XX L signal is asserted. This signal clears the BAR bit for the selected line.

4.37

INIT B H

CLR BAR 15 L

E48

f14

p—

74154

f13

p—

FROM MEMORY
ADDRESSES MUX
E48 ON M7277
REPRESENTS
TRANSMITTER
SCANNER
POSITION

4-TO-16
DECODER

f12

p——

b—

f10

p—

f09

p—

TYPICAL OF
ALL OUTPUTS

fo8 p—
f07

égUBNITlS_:RF%OM
T
UTPUT

ALL Os AT

OVERFLOW

ASSER

WHEN

Cf\gEAgggEssE
NON-EXISTANT
MEMORY

B'ITI 15 —O

MEM ADD CH

——]p2

fO5 p—

MEMADD BH

~—{D1

f04 p—

MEM ADD

——DO

—o

E§

—9

—— E@w

BIT 00

+ 3y —2

E14

74121
40ns

|
)

STB1

TIMEOUT (1) L

E22

—Oe2s

f02

p—

{01

b—o

£00 p—

|
|

fO3 p—

% E22

p—

—9
6
:g E23

6
[1

STBO

XMIT FINISHED PULSE L

DG_

TO SCR 15
CR

FLIP-

FLOP ON M7289

1-1733

Figure 4-22

BC Register Output Logic

A selected BAR bit is cleared also when TIMEOUT (1) L is asserted at the input of one-shot E14. This occurs when
the current address logic tries to address non-existent memory.

The 40 ns XMIT FINISHED PULSE also sets bit 15 of the System Control Register. In normal DH11 operation,

only this pulse sets SCR 15 to generate a transmit complete interrupt (if enabled). Clearing the BAR bit by program
action does not set SCR 15 or generate an interrupt. Clearing the byte count by program action does generate XMIT

FINISHED PULSE, clear SCR 15, and generate the interrupt. Therefore, the latter course of action (setting BC to 0)
is the recommended procedure for aborting transmission.
4.8

RECEIVER SCANNER

4.8.1

Introduction

The receiver scanner logic is located on the M7289 System Control and Receiver Scanner Module (drawing
D-CS-M7289-0-1, sheets 3 and 4). This discussion is divided into three major parts:

4.8.2

Basic operation of the receiver scanner and receiver sequencer

Operation of the status sampling logic

Operation of the auto-echo feature.

Receiver Scanner and Receiver Sequencer

This discussion first covers operation of the receiver scanner and receiver sequencer in servicing a character. Assume
that the silo can accept a character and data is available on the selected line.
The major component of the scanner is counter E25 (drawing D-CS-M7289-0-1, sheet 3). It is a type 74193

synchronous 4-bit up/down counter. In this application it is connected to count up by sending FREQUENCY
DIVIDE clock pulses to the count up (CUP) input while the count down (CDN) input is held high. The data inputs

are not used (DO — D3 connected to ground) and the load (LD) input is permanently held inactive by connecting it
to +3 V. The counter cannot be preset so it counts up from decimal 0 — 15, overflows (returns to 0), and continues

upcounting and overflowing as long as clock pulses are supplied. The counter outputs are buffered by type 7417
non-inverting buffers and sent to both M7280 UART Modules as RCV SCAN leads. They are identified as RCV

SCAN A, RCV SCAN B, RCV SCAN C, and RCV SCAN D which is the most significant bit. These signals are sent to
several decoders on the UART cards. In this case, the appropriate one is E18 which is a type 74151 data selector

(drawing D-CS-M7280-0-1). E18 is shown in Figure 4-23. The eight inputs to E18 are BUF DA LINE 0 — BUF DA
LINE 7. Each signal is from the received data available output of each UART on the card. This output goes high
when a character has been received and transferred to the UART receiver Holding Register. Signal RCV SCAN D is

sent to the strobe (STB) input of decoder E18 which enables it. Signals RCV SCAN C, RCV SCAN B, and RCV
SCAN A are sent to the select inputs (S2, S1 and SO) of E18. These inputs select 1 of the 8 inputs to E18. As it
counts, the scanner counter, through its outputs (RCV SCAN lines), scans the eight BUF DA LINE signals. If a
selected UART has received data available, its BUF DA LINE goes high, which in turn drives the output of E18

(MASTER DA) high. MASTER DA is sent to the receiver scanner logic. The function of MASTER DA is described
subsequently.
At

this point, the

discussion digresses to explain a note concerning the Receiver Scan D signal on drawing

D-CS-M7289-0-1, sheet 3. The drawing shows both D and its inversion D with a note that one UART card uses D and
the other uses D. The reason for this arrangement is shown graphically in Figure 4-24. The example shows only the
DA line decoders but it is applicable to the other decoders on the UART cards.

4-39

TO RECEIVER SCANNER

LOGIC. SIGNAL IS HIGH

7
e

AVAILABLE OUTPUT OF
EACH UART. THIS LINE

GOES HIGH WHEN A

CHARACTER HAS BEEN

5101

102

=1 PO

12] 06

MASTER DA

]

D— NOT USED

FROM OUTPUT | RoV SCAN D
OF SCANNER

WITH DATA AVAILABLE.

EI8

TO THE RECEIVER HOLDING

RECEIVED AND TRANSFERRED

FOR SELECTED LINE

STB

5100 a1t

FROM THE RECEIVED DATA | BUF DA LINE O

RCV SCAN C

Sl
1o

SO
[#

COUNTER E25 | RCV SCAN B

RCV SCAN A
11-1727

Figure 4-23

UART Data Available Line Decoder

Each UART card contains eight UARTs whose DA lines are decoded by a type 74151 data selector (E18) that uses
the RCV SCAN outputs from the receiver scanner counter for enabling and selection. By sending the RCV SCAN D
signal to one UART card and the inverted RCV SCAN D

signal to the other UART card, each E18 decoder is

enabled for a successive 8 count sequence from 0 — 7. This allows interchangeability of the two UART cards in their
assigned slots.

The discussion now returns to the operation of the receiver scanner logic. As previously mentioned, counter E25 is
clocked by signal

FREQUENCY DIVIDE. This signal has a frequency of 633 kHz and is obtained by performing a

divide by 4 function on the 2.534 MHz signal from counter EOS on the M4540 Clock Module. The 2.534 MHz signal

is sent to the clock input of FREQ DIV A flip-flop (drawing D-CS-M7289-0-1, sheet 4). The (0) H output of FREQ
DIV A is fed back to its D input so that the flip-flop changes state at each positive edge of the clock pulse. This
produces complementary signals at the FREQ DIV A flip-flop outputs that have a frequency of 1.267 MHz. The

(1)H output of

FREQ DIV A is TRAN SCAN CLK H which is sent to module M7277 to clock the FREQ DIV C

flip-flop in the transmitter scanner logic. The (0)H output of FREQ DIV A is used to clock the FREQ DIV B

flip-flop. The (0)H output of this flip-flop is fed back to its D input through 2-input AND gate E40. Assume that the
other input of E40 remains high. This produces complementary signals at the FREQ DIV B flip-flop outputs that

have a frequency of 633 kHz. The (1)H output of this flip-flop is the FREQUENCY DIVIDE signal that clocks the
receiver scanner counter (E25). The positive edge of the signal is used to clock the counter and this occurs when
FREQ DIV B is set (goes to 1 state). When FREQ DIV B is reset cleared, delay network (DL2 and E40) generates a
30 ns positive pulse at E40 pin 3. As FREQ DIV B flip-flop toggles, it generates a positive 30 ns pulse approximately

every 1.6 us. These pulses are used to clock the SCAN STOP flip-flop. The state of this flip-flop is determined by its
D input which is a function of received data available in a selected UART and space available in the silo. The

functions are sensed at inputs 9 and 10 of AND gate E30 whose output (pin 8) is sent to the D input of the SCAN
STOP flip-flop.

Determination of the availability of received data is indicated by the MASTER DA H signal from UART card
number 1 or 2. UC1 MASTER DA H from UART card 1 and UC2 MASTER DA H from UART card 2 are ORed at

gate E9 pins 5 and 6. If the scanner samples a selected line which has its Received Data Available flag high, one of
the two MASTER DA H signals is asserted. It is double inverted by E9 and E5 and sent as a high signal to pin 10 of
E40.
Determination of space available in the silo is indicated by the READY IN L signal from the silo (M7279 module).

READY IN L is asserted (low) when space is available. When READY IN L goes from high to low, the delay network

(E33, DL1, and E40) generates a 30 ns positive pulse at E40 pin 11 that clocks the SILO READY flip-flop. This

4-40

[m———————————

UART CARD
|

N_ &

RCV SCAND

| FOR LINES 00-07

N__RCV SCAN
D | N2

MASTER
4[00STB |3 DA

N_4

RCV SCANC

8uF oA

1p2

| SIGNALS
|
FROM ALL

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YN

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usep

COUNTER
OUTPUTS
11-1724

Figure 4-24

Receiver Scan Lines to UART Cards

441

redefined flip-flop is set and its (1)H output puts a high on pin 9 of E40. The other input
(pin 10) of E40 is already
high so its output (pin 8) goes high. This places a high on the D input of the SCAN STOP
flip-flop which sets when
the next 30 ns clock pulse arrives. The (0)H output of SCAN STOP puts a low on pin
4 of E40 which in turn puts a
low on the D input of FREQ DIV B. This action prevents FREQ DIV B from toggling and
holds it in the O state. The

clock signal (FREQUENCY DIVIDE) for counter E25 is inhibited and the counter stops.

stopped and is pointing to the line that has a UART with received data available.

The receiver scanner is now

With SCAN STOP set, its (1)H output puts a high on pin 11 of 3-input NAND gate E43.
Assume that the other two
inputs of this gate are high also. This requires that the RESTA SCAN flip-flop is not set; ABANDON
L is not
asserted; and flip-flop RO(1) in E21 is not set. The output (pin 8) of E43 is low
and is sent to the D input of the

redefined RECV DATA flip-flop. On the next positive transition of the 2.5 MHz clock, RECV

(1H output is high. This signal is RECV DATA EN (1)H and is sent to the UART card as an

DATA is set and its

enabling signal for the

received data enable decoder (E9). This device is a type 74155 dual 2-line
to 4dine decoder that is connected to

operate as a 3-line to 8-line decoder. Figure 4-25 contains a block diagram,
truth table, and notes that describe the
operation of decoder E9. The four RCV SCAN outputs (D, C, B, A) from
the receiver scanner counter are the select
inputs for decoder E9. Since the scanner has been stopped, these lines point
to the selected UART that has received

data available. When RECV DATA EN (1) H is asserted, decoder E9 asserts the

output. This low signal is sent to the STB RD input (pin 4) of the appropriate

onto the UART received data bus as BUF RCV DATA 01 — BUF RCV DATA

input to await subsequent loading into the silo.

proper BUF RDE LINE signal at its
UART and places the received data

08. These data bits are sent to the silo

Signal RECV DATA EN (1) H also initiates operation of the receiver sequence that performs
a series of functions in

sequence, terminating with a silo load operation and restart of the receiver

scanner. Before discussing the sequencer,

let us back track and examine the operation of the scanner logic in the event that
received data available or the silo was full.

RCV

SCAN D—

the selected UART did not have

DATA

ENMH

TRUTH TABLE
14

STBB STBA(a3b®
6 siGNALS TO THE RECEIVED
9

RCV SCAN c—e-2gDB

8 BUF RDE LINE

INPUT OF
82Pp1%—1 DATA
EaCH ENABLE
UART WHEN
LOW,

£9

THIS SIGNAL PLACES THE

fB1P——2 RECEIVED DATA ON THE

isopl2_
3 OUTPUT LINES.

[CIEC
1
TN

tazp®
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SCAN

l l

[O]|1]2]|3|4|5]|6]|7

X{X{X]

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Lit|{H|

{H|L{H/H|H|H|H|H

LIH{Lt| L

|H|H|L|H|HIH|H|H

l ] l I l l ]

Tolulnlalalnlaln

LIH|H|

|H|H|/H{L|H|H|H|H

HIL|L|

|[H{H|/H[H|L|{H|H]|H

HILIH|

{H!/H|/H/H|/H|L|H|H

HIH|L|

[H|{H|H|H|H|H|L]|H

HiH|H

HiHIHIHIH|H|H]|L

RCV SCAN B
RCV

OUTPUTS

C|{B|A|STB

fab—s

seLs seLAPOP—7
!3

SEL

X = IRRELEVANT

NOTES:
1 . Device is connected as a 3-line to 8-line decoder.
2 . Third select line (C)is obtained by connecting inputs
DA and DB together.
3 . Strobes are connected together for enabling.

1-1725

Figure 4-25

UART Received Data Enable Decoder

4-42

If the selected line does not have received data available, both UC1 MASTER DA H and UC2 MASTER DA H are
low. The output (pin 4) of NOR gate E9 is high. It is inverted by ES and sent to pin 10 of AND gate E40. This gate
is disqualified and its low output is sent to the D input of the SCAN STOP flip-flop. This holds SCAN STOP in the O
state and the scanner continues to operate.

If the selected line has received data available (MASTER DA H is asserted) and the silo is full, the scanner continues
to operate but signal STORAGE OVERFLOW L is generated to indicate a full silo.

Under these conditions, READY IN L from the silo logic is high which indicates no available space in the silo. This
prevents clocking of the SILO READY flip-flop so it remains in the O state. The (1)H output of SILO READY
disqualifies AND gate E40 and thus holds the SCAN STOP flip-flop in the O state. The scanner continues to operate,

s0 30 ns positive pulses are produced at E40 pin 3 which is connected to E43 pin 1 as well as to the SCAN STOP
flip-flop clock input. When a 30 ns positive pulse appears at E43 pin 1, all three inputs are high which drives its

output (pin 12) low to produce a STORAGE OVERFLOW L pulse. This signal is sent to the present input (pin 10)

of the SCR 14 flip-flop in the System Control Register (drawing D-CS-M7289-0-1). This is the storage interrupt flag
(bit 14) of the SCR. When set, this bit causes an interrupt if the SCR storage interrupt enable bit (12) is also set.
The discussion now returns to the point at which RECV DATA EN (1) H s enabled and the received data bits are at
the silo input to await subsequent loading into the silo. The RECV DATA EN (1) H is sent to pin 1 of AND gate
E17to initiate operation of the receiver sequencer.

The receiver sequencer consists of one type 74174 hex flip-flop package E21, six 2-input AND gates and two output
inverters (drawing D-CS-7289-0-1, sheet 4). Assume that signal ABANDON L is not asserted and the six sequencer
flip-flops (E21) are cleared. These conditions drive E13 pin 11 high which puts a high on one input of the six
sequencer input AND gates (E17 pin 2, E17 pin 4, E17 pin 13, E17 pin 9, E13 pin 1, and E13 pin 4). Signal RECV
DATA EN (1) H has been asserted and sent to pin 1 of gate E17. The other input (pin 2) is also high so its output
(pin 3) goes high. This signal is sent to the D5 input of E21. The next 2.5 MHz clock pulse sets flip-flop 5 and its
output R5 (1) goes high. This signal is sent to E17 pin 5 which is the input AND gate for flip-flop 4. It puts a high
on D4 and this flip-flop is set on the next 2.5 MHz clock pulse. Similar connections allow flip-flops 3, 1,2, and O to
set on successive 2.5 MHz clock pulses. Figure 4-26 is a timing diagram for the receiver sequencer.

We are still discussing the operation of the receiver scanner in servicing a character. Auto-echo is not enabled and the
hardware requires only a signal to load the silo and start the receiver scanner. SAMPLE STATUS H is the first signal
generated by the sequencer and has no effect on this operation.
—-—I

|4—T=400ns

MM
[
2ssammzciock M
]

scaN sTOP()H - _ [T

RCV DATA EN(1)H

ALLOWS TIME FOR
DATA EN(I)H
{RECV
L
| TO TAKE EFFECT
)

E21 RS (1)

SAMPLE STATUS H

DETERMINE NEXT H
LOAD UART AND/

—

OR SILO H

E21 R2(1)

[

E21 RO(1)

[ ALLOWS TIME FOR

LOAD UART AND/OR SILO

TO TAKE EFFECT

RESETS SEQUENCER
1-1726

Figure 4-26 Timing Diagram for Receiver Sequencer
443

DETERMINE NEXT H is asserted next and is sent to three
E2 NAND gates (drawing

gate under consideration in this case is E2 pin 10. The other

D-CS-M7289-0-1, sheet 3). The

input (pin 9) of this gate is high also because auto-echo

is not enabled. E2 pin 8 goes low and is sent to pin 12 of E1.
LOAD UART AND/OR SILO L is asserted by the

sequencer and sent to the other input (pin 11) of E1. The

output (pin 13) of E1 goes high and is inverted by another

El gate. The output of this gate (pin 10) is LOAD SILO L
and is sent to the silo logic to initiate a silo load

operation. The high output of E1 pin 13 is RESET DATA
AVAIL H and is sent to the UART

Data Available flag on the selected line. When flip-flop O of the

boards to clear the

sequencer sets, its high output is inverted by E5 pin

2 which drives the output (pin 11) of E13 low. This disqualifie
s all the sequencer input AND gates; disqualifies E43
and puts a high on the D input of RECV DATA, and puts
a low on the D input of RESTA SCAN. On the next
2.5 MHz clock pulse, all five sequencer flip-flops (0, 1, 2, 4,
and 5) are reset; RECV DATA is reset which clears
RECV DATA EN (1) H; and RESTA SCAN is set and its (1)
L output directly clears SCAN STOP which starts the

receiver scanner. The received character has been serviced
and the receiver scanner has resumed operation. After

400 ns DETERMINE NEXT H (sequencer flip-flop 3)
is cleared which allows appropriate data hold time for
auto-echo hardware to load the UARTS.

4.8.3

Status Sampling Logic

The SAMPLE STATUS H signal that is asserted by the
receiver sequencer is used to clock two type 74175 quad
flip-flop packages E10 and E18. Six of the eight flip-flops in these
two packages sample various conditions in the
DHI! hardware. The status of the conditions is stored in the
flip-flops and their outputs are sent to control logic

associated with the receiver scanner. These status signals are
used primarily to condition the control logic prior to
assertion of the DETERMINE NEXT H signal when using the
auto-echo feature.

This discussion covers the generation and purpose of the status
signals. Their use in the receiver scanner logic is

described in Paragraph 4.8.4.

The following conditions are sampled.
Master Overrun (E18 input D0)

A UART generates a high BUF OR LINE signal if the previousl
y received character is not read (BUF DA LINE not
reset) before the present character is transferred to the receiver
Holding Register. The BUF OR LINE signal from
each UART on a card is sent to a type 74151 data selector (E15)
that is operated by the outputs of the receiver

scanner counter. When the scanner stops, these leads

(RCV SCAN A — RCV SCAN D) point to the selected

BUF OR LINE signal associated with the selected line is enabled
are two such signals:

line. The

to the data selector output as MASTER OR. There

UC1 MASTER OR for card 1, and UC2 MASTER OR for
card 2. These two signals are

the receiver scanner logic (drawing D-CS-M7289-0-1, sheet 3).

sent to

They are ORed at E9 pins 2 and 3. The output of E9

is inverted by ES and sent to the DO input of E18. If the selected
line indicates an overrun condition, MASTER OR
is high and DO is high. The positive edge of the SAMPLE STATUS
H pulse sets the flip-flop. Conversely, the flip-flop
is reset if there is no overrun condition.
Auto-Echo (E18 input D1)

Auto-echo is enabled by setting bit 15 of the LPR of the selected
line. When selected, a flip-flop on the M7288 LPR
module is set and it sends an AE ENAB XXH signal to type
74150 multiplexer E12 in the receiver scanner logic.

Selection is provided by the receiver scanner counter leads (RCV
SCAN A — RCV SCAN D) which point to the
selected line. If auto-echo is enabled for the selected line, the multiplex
er output is low. If auto-echo is not enabled,
the multiplexer output is high. This output is sent to input D1 of
E18. When clocked by SAMPLE STATUS H, this
flip-flop is set when auto-echo is not enabled and it is reset when auto-echo
is enabled.
Transmitter Scanner (E18 input D2)

The operating status of the transmitter scanner is required because
auto-echo is not allowed if that scanner is

stopped.

444

The status of the scanner is indicated by signal XMIT STATUS L. This signal is low if the scanner is stopped and it is
high if the scanner is operating. This signal is sent to input D2 of E18. When clocked by SAMPLE STATUS H, this
flip-flop is set when the scanner is operating and it is reset when the scanner is stopped.
Transmitter Buffer (E18 input D3)

The status of the Data Holding Register must be known because, during auto-echo operation, a received character is

loaded in the UART for transmission back to the sending location.

A UART generates a high TMBT LINE signal when the Data Holding Register can be loaded with a character. All 16
UARTSs send their TMBT LINE XXH signals to the inputs of a type 74150 multiplexer (E30) in the receiver scanner
logic. Selection is provided by the receiver scanner counter leads (RCV SCAN A — RCV SCAN D) which point to
the selected line. If the Data Holding Register can accept a character, the multiplexer output is low. If the register
contains a character, the multiplexer output is high. This output is sent to input D3 of E18. When clocked by
SAMPLE STATUS H, this flip-flop is set when the Holding Register is full and is reset when the register is empty.
Bus Request (E10 input DO)

The status of REQUEST BUS (1) H must be known because auto-echo is not allowed if an NPR cycle is in process or

is being requested. During auto-echo, a received character is loaded into the UART Holding Register via the eight
BUF TRAN DATA lines. These same lines are used during an NPR to bring a character from memory to the UART
Holding Register. It is not desirable to attempt auto-echo and programmed transmission on the same line
simultaneously. REQUEST BUS (1) H is generated by the transmitter scanner logic and is high when the DH11 is
requesting the bus to perform an NPR cycle. It stays high during the NPR cycle. REQUEST BUS (1) H is sent to
input DO of E10. When clocked by SAMPLE STATUS H, this flip-flop is set when an NPR cycle is in process or is
being requested, and it is reset when an NPR is not in process nor being requested.
Master Framing Error (E10 input D2)

A UART generates a high BUF FE LINE signal if the received character has a framing error; that is, if it does not
have a valid stop bit. The BUF FE LINE signal from each UART on a card is sent to a type 74151 data selector
(E16) on the M7280 UART card that is operated by the outputs of the receiver scanner counter. The BUF FE LINE
signal associated with the selected line is enabled to the selector output as MASTER FE. There are two such signals,
UC1 MASTER FE for UART card 1 and UC2 MASTER FE for UART card 2. These two signals are sent to the
receiver scanner logic. They are ORed at E1 pins 2 and 3. The output (pin 1) of E1 is inverted by E9 and sent to the
D2 input of E10. If the selected line has a framing error, MASTER FE is high and D2 is high. Under these
conditions, SAMPLE STATUS H sets the flip-flop. Conversely, the flip-flop is reset if there is no framing error.
Table 4-5 lists the states of flip-flops E18 and E10 for the various conditions sampled.
4.8.4

Auto-Echo Feature

484.1 Introduction — The auto-echo feature is discussed here because it is closely related to the operation of the

receiver scanner. The first part of the discussion covers the normal operation of the auto-echo feature. The second
part discusses how auto-echo, when enabled, can be abandoned if certain qualifying conditions are not satisfied.

4.8.4.2 Functional Description — The auto-echo feature allows received characters to be transmitted back (echoed)
to the sending terminal without program intervention. The characters are also loaded into the silo. It is primarily
intended for computer controlled high speed systems as a means of confirming successful reception.

If the receiver scanner finds a received character for a line which has auto-echo enabled, it examines the framing
error and overrun error flags associated with that character. If either error is present, the character and associated

error flag are loaded into the silo so that the system can be alerted when the NRC register is read.

4-45

The received character is auto-echoed providing three conditions are met:
a.

No bus request is in progress.

The transmitter scanner is operating.

Space is available in the transmitter Holding Register.

Table 4-5

States of Status Flip-Flops E10 and E18
Associated Flip-Flop

Condition Sampled

UART Overrun

Status

Overrun

Desig

State

E18-D0

Set

RO(1) High

Reset

RO(1) Low

No Overrun
Auto-Echo

Enabled

E18—D1

Not Enabled
Transmitter Scanner

Operating

E18-D2

Output

Reset

R1(0) High

Set

R1(0) Low

Set

R2(1) High

R2(0) Low
Stopped

Reset

R2(1) Low

R2(0) High
UART Transmitter

Full

E18-D3

Holding Register

Set

R3(1) High
R3(0) Low

Empty

Reset

R3(1) Low

R3(0) High
Bus Request

Requesting

E10-DO

Set

RO(1) High

RO(0) Low

Not Requesting

Reset

RO(1) Low

RO(0) High
UART Framing Error

Framing Error

E10-D2

No Framing Error

Set

R2(1) High

Reset

R2(1) Low

4.8.4.3

Normal Auto-Echo Operation — During normal auto-echo
operation, the following conditions exist.
Assume that SAMPLE STATUS H is asserted and sample status flip-flops
E10 and E18 have been clocked (drawing
D-CS-M7289-0-1, sheet 3).
a.

The auto-echo enabled flip-flop for the selected line is set.
Signal AE ENAB XX H is asserted and

flip-flop E18—D1 is reset.

No bus request is in process. Signal REQUEST BUS (1) His low and flip-flop

The transmitter scanner is operating. Signal XMIT STATUS L is high
and flip-flop E18—D2 is set.

Space is available in the UART transmitter Holding Register for the

asserted and flip-flop E18—D3 is reset.

4-46

E10—DO is reset.

selected line. TMBT LINE XX H is

Conditions a, b, and ¢ qualify NAND gate E6 by putting high signals on pins 1, 2, and 3. The output (pin 12) of E6
goes low, is inverted by ES5, and applied to one input each of two 2-input NAND gates: E14 pin 4 and E14 pin 2.
Condition d puts a high on E14 pin 1. The output (pin 3) of this gate goes low, is inverted by E2 pin 3, and puts a
high on E2 pin 4. The other input of this gate (pin 5) goes high when DETERMINE NEXT H is asserted. This drives
its output (pin 6) low which generates AE GO L. DETERMINE NEXT H s also sent to two other E2 gates: E2 pin

12 and E2 pin 20. Gate E2 pin 9 is high because conditions a, b, ¢, and d drove E6 pin 8 high. The resulting low at
E2 pin 8 is sent to E1 pin 12 to qualify this gate for assertion when LOAD UART AND/OR SILO L is generated by
w

ol
=

Lot

o
=

Conditions a, b, ¢, and d disable E6 pin 6 whic

the sequencer.

normal auto-echo operation.

When asserted, AE GO L performs the following functions.

AE GO Lis sent to the transmitter scanner logic (drawing D-CS-M7277-0-1, sheet 4) to stop the scanner.

AE GO L is sent to multiplexers E39 and E42 that select either the output of the byte control logic or
the 8 received data bits from the UART cards (drawing D-CS-M7277-0-1, sheet 3). In this case, with AE
GO L asserted, the 8 received data bits are selected. They represent the character to be echoed. These
bits become TRAN DATA 1 — TRAN DATA 8 at the multiplexer output. They are sent to the
transmitter data bus on the UART cards and hence to the input of the transmitter Holding Register of
each UART. Subsequently, these bits will be loaded into the transmitter Holding Register of the UART
that is teceiving the character to be echoed. This action is provided by the AE STROBE signal and is
explained below.

AE GO Lis sent to the select (S0) input of multiplexer E34 (D-CS-M7289-0-1, sheet 3). Signal AE GO L
determines whether the TRAN SCAN A, B, C, D leads are controlled by the transmitter scanner (normal

case) or the receiver scanner (auto-echo case). In this case, with AE GO L asserted, the receiver scanner
lines are selected. These lines are the four buffered outputs of receiver scanner counter E25 which are
RECV SCAN A, B, C, and D. These bits become TRAN SCAN A, B, C, and D. These signals are sent to

the DS line multiplexer (E6) on each UART card to select the Data Strobe signal (BUF DS LINE X)
which loads the transmitter Holding Register. The TRAN SCAN lines are a function of the RECV SCAN
lines so they point to the same UART that is receiving the character to be echoed. The loading operation
does not occur until multiplexer E6 is enabled by TRAN STROBE H.

When LOAD UART AND/OR SILO L is asserted, AE STROBE H is asserted at E1 pin 4. It is sent to the M7278
module, double inverted by E47 pin 13 and E39 pin 2, and sent as TRAN STROBE H to the UART cards to enable
the DS line multiplexer E6. The selected BUF DS LINE X signal is thus generated and it loads TRAN DATA 1

through TRAN DATA 8 into the transmitter Holding Register of the UART that received the character to be
echoed. The received character is thus transmitted back to the sending terminal.

Signal LOAD UART AND/OR SILO L also generates a high at E1 pin 13 that is sent to the RDA decoder (E12) on
the UART card which sends a BUF RDA LINE X signal to the reset data available input of the selected UART. This

signal resets the UART Received Data Available flag (BUF DA LINE X).

Signal RESET DATA AVAIL, which is high, is inverted by E1 pin 10 to generated LOAD SILO L. This signal is sent
to the silo control logic to initiate a load operation that places the received characters and status information into
the silo.

4-47

4.8.4.4

Use of ABANDON Signal to Prevent Auto-Echo Operation — Even if auto-echo is enabled, assertion of

ABANDON L can halt the auto-echo procedure if any one of three conditions is not satisfied. The conditions that

can halt auto-echo are:
a.

A bus request is in process. Signal REQUEST BUS (1) H s asserted which causes flip-flop E10—DO to be

set when clocked by SAMPLE STATUS H.
b.

The transmitter scanner is stopped. Signal XMIT STATUS L is asserted which causes flip-flop E18—D2

to be reset when clocked by SAMPLE STATUS H.
¢.

The UART transmitter Holding Register is full. Signal TMBT LINE XX H is low. This causes flip-flop

E18-D3 to be set when clocked by SAMPLE STATUS H.
Assume that a bus request is in process. Flip-flop E10—DO is set and its RO(1) ouiput is high. This signal

is sent to

E14 pin 12 whose other input (pin 13) is high because auto-echo is enabled. The output (pin 11) of E14 goes
low
and is sent to E6 pin 4. This produces a high at E6 pin 6 that is sent to E2 pin 13. When DETERMINE NEXT
H is

asserted, the other input (pin 12) of E2 is high and its output (pin 11) goes low. This signal is ABANDON L. It is
sent to E13 pin 12 (drawing D-CS-M7289-0-1, sheet 4) which drives the output (pin 11) of this gate low, which in
turn disables E43. This action allows the next 2.5 MHz clock pulse to disable the sequencer, clear RECV DATA EN

(1) H, and set the RESTA SCAN flip-flop. Auto-echo operation is halted and the receiver scanner resumes operation.

If the transmitter scanner is stopped, the same result occurs except that it is initiated by a low signal at E6 pin 5. If
the transmitter Holding Register is full, the same result occurs except that it is initiated by a low signal at pin 3.
4.9

FIFO BUFFER

4.9.1

Introduction

The

FIFO buffer and associated control logic is located on the M7279
D-CS-M7279-0-1, sheets 2 and 3). This discussion is divided into four major parts:

4.9.2

Functional description of the FIFO

Operation of the FIFO input logic

Loading the FIFO

Reading the FIFO.

FIFO

Buffer

Module

(drawing

FIFO Buffer Functional Description

The first-in/first-out (FIFO) buffer is commonly referred to as the silo. It is a serial memory device that allows the
first data entered to be the first data removed, regardless of the quantity of data stored.

The FIFO buffer or silo is composed of four type 3341 64-word by 4-bit FIFO serial memory devices E3, ES, E13,
and E17 (drawing D-CS-M7279-0-1, sheet 3). The four 3341s are connected to provide a buff. that is 16-bits
wide
and 64-words deep. All four devices use common load and unload control signals. The Ready In flags of all 3341s are
ANDed to provide READY IN L at E9 pin 6. All the Ready Out flags are ANDed to provide READY OUT

pin 8.

L at E9

Actually only 15 silo bits are used. They are identified as NRC 00 H — NRC 14 H and, together with NRC 15 H
from the silo control logic, they constitute the Next Received Character (NRC) Register. Except for bit 15, the NRC

4-48

Table 4-6

NRC Bit Identification

Input

Output

Remarks

RCVDATA 01 H

NRC 00 H

RCV DATA 02 H

NRCO1 H

RCV DATA 03 H

NRC 02 H

RCV DATA 04 H

NRC 03 H

RCV DATA 05 H

NRC 04 HY)

RCV DATA 06 H

NRC 05 H

RCV DATA 07 H

NRC 06 H

RCV DATA 08 H

NRC 07 H

RCV SCAN A H

NRC 08 HY

RCV SCAN B H

NRC 09 H

RCV SCANCH

NRC 10 H

MASTER PE H

NRC 12 H

MASTER FE H

NRC 13 H

MASTER OR H

NRC 14 H

RCVSCANDH

—

From FIFO E3

From FIFO E8

From FIFO E17

NRC 11 H

From FIFO E13

NRC 15 H

From NRC 15 H Flip-Flop

High signals are used to load and unload the silo. Simultaneous loading and unloading of the silo is prevented by the
control logic.
4.9.3

FIFO Input Logic

The inputs to the silo are obtained from four type 74157 quad 2-line to 1-line multiplexers. Each multiplexer (E2,
E7, E12, and E16) chooses between two 4-bit input words (drawing D-CS-M7279-0-1, sheet 2). The A word contains
data. The B word contains a fixed binary representation that is obtained by connecting the BO and B3 inputs to

ground and connecting the Bl and B2 inputs to +3 V. If the B word is selected by the input multiplexers, the NRC

even-numbered bits (00, 02, 04, etc.) are forced to 0 and the NRC odd-numbered bits (01, 03, 05, etc) are forced to
1.

The input word selection is controlled by signal SSR 15 H that is connected to the select (SO) input of each
multiplexer. Signal SSR 15 H is the maintenance bit in the Silo Status Register (SSR). During normal operation it is
low and the A word or data word is selected. When it is desired to check the silo for maintenance purposes, the
program sets bit 15 of the SSR. Signal SSR 15 H goes high and the B word or fixed test pattern is selected.
Multiplexers E2 and E7 provide the eight received data bits (RCV DATA 01 H — RCV DATA 08 H). The inputs to
these multiplexers come from the received data bus on the UART cards. Corresponding bits from each card (UC1
and UC2) are ORed and sent to the appropriate A word input.

Multiplexer E16 provides the receiver scanner signals (RCV SCAN A, B, C, and D). The inputs to the multiplexer
come from the output of the receiver scanner counter (E25) on the M7289 module.

Multiplexer E12 provides the Parity Error flag (MASTER PE H), the Framing Error flag (MASTER FE H), and the
Overrun Error flag (MASTER OR H). The inputs to E12 come from decoders on the UART cards that send the
status of these flags for the received character. Corresponding flag signals from each UART card (UC1 and UC2) are
ORed and sent to the appropriate A word input.

4-49

4.9.4

Loading the FIFO (SILO)

A silo loading operation is initiated by the receiver scanner when it asserts LOAD SILO L. This signal is inverted by

E15 pin 2 and clocks the LOAD REQ flip-flop. This redefined flip-flop has its D input permanently connected to

ground so it is set by the clock pulse. The (1) H output of LOAD REQ is high and is sent to the D input of the

LOAD flip-flop. This flip-flop and the UNLOAD flip-flop are both clocked by the outputs of the PHASE flip-flop.
Simultaneous loading and unloading of the silo is possible but not allowed. It is prevented by connecting the PHASE
flip-flop in a toggle configuration and clocking the LOAD and UNLOAD flip-flops with the complementary outputs
of the PHASE flip-flop (Figure 4-27). The LOAD flip-flop is clocked when the PHASE flip-flop goes to the O state

and the UNLOAD flip-flop is clocked when the PHASE flip-flop goes to the 1 state.

—qo

ip=>

UNLOAD

74H74

74H74
¢

PHASE O

5.068MH

2.534 MHz

0 0_8—

opg-

POSITIVE EDGE OF THESE

CLOCK SIGNALS DISPLACEDBY

1/2

WITH RESPECT TO PHASEFF QUTPUTS
2.534MH:z
9
12
—b

TIMING DIAGRAM

T4H74

5.068 MHz
.

Dle

PHASE D INPUT

8
o=
LOAD

r_L__J—

PHASE (1)H OUTPUT (PIN9)

CLOCKS UNLOAD FLIP FLOP

PHASE(O) H OUTPUT(PIN 8)

CLOCKS LOAD FLIPFLOP

op2o=

‘

11-1729

Figure 4-27

Generation of Clock Pulses for LOAD and UNLOAD Flip-Flops

In this case, with the D input of the LOAD flip-flop high, the next time the PHASE flip-flop goes to the O state, the

LOAD flip-flop is clocked which sets it. The (1) L output of LOAD, which is low, triggers the LOAD STROBE
one-shot. A 170 ns positive pulse is generated at the (1) H output (pin 6) of LOAD STROBE which is sent to the

load input (pin 3) of the silo.

At the end of the 170 ns pulse, the (0) H output (pin 1) of LOAD STROBE comes high again. This signal is sent to a
delay network (E4, DL1, and E14) that generates a 30 ns negative pulse at E14 pin 11 called LOAD PULSE L. This
signal restarts the receiver scanner. The positive trailing edge of LOAD PULSE L also increments the silo level
counter that is composed of two cascaded type 74193 synchronous counters (E24 and E20). LOAD PULSE L is also

double inverted by E15 pin 4 and E26 pin 4 to clear the LOAD REQ flip-flop. This is the end of the load cycle.

The six binary outputs of the silo level counter (E20 and E24) represent the number of characters in the silo. They
constitute bits 08 — 13 of the Silo Status Register (SSR) and can be read by the program. Six binary bits give 64

counts (2° = 64); however, the states of these bits indicate 0 through 63;,. A full silo contains 64 characters and is

represented as 000000. An empty silo is represented as 000000 also. The program can tell the difference by reading

SCR 14 which is high when the silo is full and is the storage interrupt bit.

4-50

The silo level counter outputs go to two type 7485 4-bit magnitude comparators (Figure 4-28). They are
cascaded to provide comparison of two 6-bit words. The counter outputs are the A input word, and SSR bits
00-05 and the B input word. SSR 00-SSR 05 are the silo alarm level bits. They are program selectable to
determine at what silo fill level a receiver interrupt is to be requested. When the number of characters in the
silo exceeds the silo alarm level, an interrupt is requested provided the receiver interrupt enable bit in the
System Control Register (SCR 06) is set.

7485

E19

A=B ——

A<B H—

SSR 05 H ———— B1

SSR 13 H — A1
SSR 04

H ———BO

EAO

SSR 12 H

IN>

SSR 03 H

SSR 02 H

[IN<

413 2

53 Eos

SSR 11

IN=

SSR 10 H
SSR 01 H

| A2
B1

ASB 2
A= -8

SSR 09 H

A<B

SSR OO H

SSR 08 H

AO
IN>

IN=

IN<

+3V

NOTES:

1 .:Vshse:o?ns‘cuded,the 7485 handling the least significant bits must be permanently connected

2 .Word A consists of bits SSR 08 H-SSR 13 H which represent the number of characters in the
silo as indicated by the silo character counter (E20 and E24).

3 .Word B consists of bits SSR OOH-SSROSH which represent the siio alarm level (0,1,2,4,8,
16 or 32) as determined by the program.

11-1728

Figure 4-28 Silo Fill/Alarm Level Comparator

In the silo control logic, when the number of bits in the silo (A word) exceeds the silo alarm level (B word),
output A >B of E19 goes high. This signal is sent to E14 pin 1. Assume that a character is available at the silo
output. READY OUT L is asserted at E9 pin 8, is inverted by E22 pin 8, and is sent to E14 pin 2. The output (pin
3) of E14 goes low, is inverted by E22 pin 2, and clocks the DATA READY flip-flop. This redefined flip-flop is set
and its (1) L output (pin 5) is low, which is DATA READY L. This signal is sent to the SCR output logic on module
M7289 to initiate a receiver interrupt.

4-51

4.9.5

Reading the FIFO (SILO)

Assume that the program desires to read the NRC register in response to the DATA READY flag.
When the NRC register is addressed, signal READ NRC H is asserted by the M7277 module. When READ NRC
H
goes high, it clocks the NRC 15 flip-flop. A character is available at the silo output so READY OUT
L is asserted at

E9 pin 8. This puts a low on the D input of the NRC 15 flip-flops. When clocked by READ NRC H, this redefined

flip-flop is set. This means that when the instruction to read the NRC register is issued, valid data

READY OUT L is asserted.

is available because

Signal NRC 15 H is asserted at the (1) H output (pin 8) of the NRC 15 flip-flop. NRC 15 H is inverted
10 to clear the DATA READY flip-flop. This clears the Data Ready flag (DATA READY L). NRC

high on E14 pin 5. The other input (pin 4) of this gate remains low until READ NRC H goes

by E26 pin

15 H also puts a

low again after the
NRC register has been read. Then pin 4 is high and E14 pin 6 goes low and is sent to the D input
of the UNLOAD
flip-flop. The next time that the PHASE flip-flop goes to the 1 state, its (1) H output clocks the UNLOAD
flip-flop
which sets it. The (1) L output (pin 5) of the UNLOAD flip-flop triggers the UNLOAD STROBE
one-shot. The (1)
H output (pin 6) of UNLOAD STROBE provides a 100 ns positive pulse that is sent to the unload
input (pin 15) of
the silo. This action shifts out the NRC character that has just been read and lets the next character
fall into the last

position in the silo.

At the end of the 100 ns pulse, the (0) H output (pin 1) of UNLOAD STROBE comes high again.
This signal is sent
to a delay network (E4, DL2, and E14) that generates a 30 ns negative pulse at E14 pin 8. The positive
trailing edge
of this signal decrements the silo level counter. This signal is also double inverted by E22 pin 4 and E26 pin 13
to
clear the NRC flip-flop.

If there is another character
in the silo, the action of that character falling into-the Jast position-in-the silo-causes

READY OUT L to be asserted at E9 pin 8. If the silo fill level remains in excess of the silo alarm
level, E14 pin 1

high and E14 pin 2 is high. This action sets the DATA READY flip-flop again and another receiver
interrupt is

generated provided the receiver interrupt enable bit (SCR 06) is set.

4.10

SYSTEM CONTROL REGISTER

4.10.1 , General Information

The System Control Register (SCR) is contained on the M7289 System Control and Receiver Scan

M7289-0-1, sheet 6).

Module (drawing

The SCR contains 16 bits and is byte addressable. The low byte (bits SCR 00 — SCR 07) is clocked
by LOAD SCR
LOW BYTE H and the high byte (bits SCR 08 — SCR 15) is clocked by LOAD SCR HIGH BYTE H.
All 16 bits are stored in D type flip-flops. Two type 74175 quad flip-flop packages are used for
8 bits; E7 for bits
SCR 00 — SCR 03 and E47 for bits SCR 09 and SCR 11 — SCR 13. Four type 7474 dual flip-flop
packages are used
for the other 8 bits; E11 for SCR 04 and SCR 05, E19 for SCR 06 and SCR 07, E41 for SCR 08 and SCR 10, and
E50 for SCR 14 and SCR 15.
The D input to each flip-flop comes from a correspondingly numbered Unibus data line whose signal has passed
through a Unibus receiver and noninverting buffer on module M7278. Each bit is under program control but
several

bits are also under DH11 hardware control. In addition, the SCR contains logic that allows interaction between

various SCR bits and the DH11 hardware. The interaction is primarily with respect to the
generation of interrupts.

Only SCR outputs SCR 00 H — SCR 05 H and SCR 11 H are used directly without interaction with

4-52

other SCR bits.

Outputs SCR 00 H — SCR 03 H are the line selection bits. They are sent to the control strobe logic (drawing
D-CS-M7277-0-1, sheet 3) to generate the LPR clock signals. These bits are also sent to the CAR (drawing
D-CS-M7277-0-1, sheet 6) as the address selection bits for the CA memory.

Outputs SCR 04 H and SCR 05 H are sent to the CAR (drawing D-CS-M7277-0-1, sheet 5) as bits 16 and 17 of the
current address.

Output SCR 11 H is sent to the address selection logic (drawing D-CS-7277-0-1, sheet 3) to generate an initialize
signal within the DH11.

The remainder of the SCR outputs are interactive and are discussed with respect to the functions that they perform;

primarily, the generation of receiver and transmitter interrupts.
4.10.2

Receiver Interrupt Bits

Bits SCR 06, SCR 07, SCR 12, and SCR 14 are related to the generation of a receiver interrupt. For clarity, a

simplified logic diagram (Figure 4-29) is used to show only these bits and associated logic.

In normal operation, the maintenance bit (SCR 09) is cleared by the program and SCR 09 H is low. This signal is
sent to the pin 5 input of two type 74121 one-shots; SCR 07 LOAD (E23) and SCR 10 LOAD (E25). A low on this
input inhibits the operation of the one-shot. As a result, the SCR 07 flip-flop and SCR 14 flip-flop cannot be
clocked when their respective load signals are generated. These signals are LOAD SCR LOW BYTE H for SCR 07 and
LOAD SCR HIGH BYTE H for SCR 14.

There are two kinds of receiver interrupts. One is generated when the program has set the receiver interrupt enable
bit (SCR 06) and a character is available in the silo. The other is generated when the program has set the storage
interrupt enable bit (SCR 12) and the silo is full at the time that the DHI1 needs to store an additional character
there.

Assume that the receiver interrupt enable bit (SCR 06) is set. This is accomplished by the program as follows. BUF
DATA 06 H is asserted at the D input of the SCR 06 flip-flop. The processor addresses the SCR register with an
instruction to write into the low byte. The address selection logic generates LOAD SCR LOW BYTE H which clocks
the SCR 06 flip-flop and its (1) H output (pin 9) goes high. This signal is sent to E31 pin 9. Assume that the SCR 07
flip-flop is cleared. If this flip-flop is not cleared, the act of DATA READY L going low does not produce the

transition of RCV INT REQ H needed to cause the M7821 to start an interrupt sequence. Its (1) L output (pin 6) is
high and is sent to E31 pin 12. When the number of characters exceeds the silo level limit, DATA READY L is
asserted by the silo logic to indicate that a character is available. DATA READY L is sent to E31 pin 13 and the
output (pin 11) of this gate goes high and is sent to E31 pin 10. The output of this gate (pin 8) goes low and is
inverted by E31 pin 5 to generate RCV INT REQ H. This signal is sent to the M7821 module in slot AO6 to initiate
the receiver interrupt sequence.

" Assume that the storage interrupt enable bit (SCR 12) has been set by the program. This produces a high at output
R3 (1) of flip-flop E47 that is sent to E31 pin 1. When the receiver scanner has found a character to be stored but
the silo is full, STORAGE OVERFLOW L is asserted and sent to the preset input (pin 10) of the SCR 14 flip-flop

which sets it. The (1) H output (pin 9) of the SCR 14 flip-flop is high. It is sent to E31 pin 2 and the output (pin 3)
of this gate goes low. This signal is inverted by E31 pin 4 to generate RCV INT REQ H.

4.10.3

Transmitter Interrupt Bits

Bits SCR 10, SCR 13, and SCR 15 are related to the generation of a transmitter interrupt. For clarity, a simplified

logic diagram (Figure 4-30) is used to show only these bits and related logic.

4-53

STORAGE OVERFLOW L ——l
10
12

BUF DATA 14 H——D
LOAD SCR HIGH BYTE H

¢
E36

SCR

SN
.

F‘“{

SCR

(Sito

Full)

)

LOAD

14 H

STORAGE INTERRUPT

SCR

CLR

READY IN
PULSE H 12

74121

*To A Master Control Section of
M7821 inslot AO6 to initiate a
receiver interrupt.

BUF DATA 06 H——D

1 4

SCR

12504

8
E31

SCR O7 H

INTERRUPT

RECENVE

)

®— INTERRUPT

(Choructe)r
Availabi

DATA READY L
13
BUF DATA O7 H ——
LOAD SCR
___
¢
LOW BYTE H

SCR
07

1E31

JE31

YSRCVINT REQH

vatiabe

MAINT

SOC7R

RECV INTR

7474

BuUFDATA 12H—D3

R3(1)
E47

17.21A2[2

SCR 12 H

oRasE
ENABLE

74175

BUF DATA 09 H—>{p1

R1(ML

e
NcE

CLK

LOAD SCR HIGH BYTE H———’

H-177

Figure 4-29

Simplified Logic Diagram of SCR Receiver Interrupt Circuitry

TIME OUT (1)L

I]O

oRE

BUF DATA 10H—D

INIT H

SCR 10
H NON

EXISTANT MEMORY INTR

HIGHBYTEH

7474

5
SCR O8H CLEAR
}——— NON EX MEMORY
1
3

2
BUF DATAO8H — D

61,

7474
LOAD SCR
HIGH BYTE H

LOAD SCR

E36

+3v

SCR

CI?ESAR

2lc cr of—

74121

16"CCLR0

scr
3CF

Y13

LOAD
74121

)®
as
3

]
5

XMIT FINISHED

PULSE H

XMIT

INTREQ
H

SSv

2
BUF DATA
15 H—{p

To B master control section

|,
‘

7474

of M7821inslot AOG6 to

interrupt

|5
1

SCR

initate a transmitter

PRE

E48

2
|
__SCR 15H

XMIT

INTR
c

BUF DATA 13H —{D2

R2(D)

o XMIT INTR

ENABLE
E47
74175

BUFF DATAO9H—{ DI

RXI)

SCR
09 H
MAINTENANCE

CLK

11-1772

Figure 4-30 Simplified Logic Diagram of SCR Transmitter Interrupt Circuitry

In normal operation, the maintenance bit (SCR 09) is cleared by the program and SCR 09 H is low. This signal
inhibits the operation of the SCR 10 LOAD one-shot. As a result, the SCR 10 flip-flop cannot be clocked when
LOAD SCR HIGH BYTE H is asserted.

There are two kinds of transmitter interrupts and their generation is dependent on the transmitter and nonexistent
memory interrupt enable bit (SCR 13) being set by the program. One interrupt is generated when one or more lines
has finished transmission. The other interrupt is generated when the DH11 addresses nonexistent memory.
Assume that the transmitter interrupt enable bit (SCR 13) is set. Signal SCR 13 H, which is high, is sent to one input
each of two E48 NAND gates. At the end of the NPR cycle that loads the last character to be transmitted, the Byte

Count Register overflows (goes to 0) and this event generates signal XMIT FINISHED PULSE L. This low signal is
sent to the preset (pin 4) input of the SCR 15 flip-flop which sets it. The (1) H output (pin 5) of the SCR 15

flip-flop goes high. It is sent to E48 pin 1 which drives the output (pin 3) of this gate low. This signal is inverted by

E48 pin 6 to generate XMIT INT REQ H. This signal is sent to the M7821 module in slot A06 to initiate the
transmitter interrupt sequence.

Assume now that the DH11 is performing a DATI transaction but the CAR places a nonexistent memory address on
the Unibus. Because it is an erroneous address, no SSYN response is generated and, after 20 us, the TIME OUT

flip-flop on the M796 Unibus Master Control Module is set. The DATI transaction is discontinued. Signal TIME OUT
(1) L is asserted by the M796 module and sent to the preset (pin 10) input of the SCR 10 flip-flop which sets it. The

(1) H output (pin 9) goes high and is sent to E48 pin 9. The other input (pin 10) of this gate is also high because the

transmitter interrupt enable bit (SCR 13) is set; therefore, the output (pin 8) goes low. This signal is inverted by E48

pin 6 to generate XMIT INT REQ H.

During normal operation, the SCR 10 flip-flop is read-only. Once set, it can be cleared only by the program via bit

SCR 08. The program sets flip-flop SCR 08 and its (1) L output, which is low, is sent to the input of one-shot SCR
08 CLEAR. This signal triggers the one-shot and a 40 ns positive pulse from its (1) H output (pin 6) is inverted by

E49 pin 10 and sent to the clear input (pin 13) of flip-flop SCR 10 which clears it. This signal also directly clears the
SCR 08 flip-flop and the TIME OUT flip-flop on the M796 module.

4.10.4

Maintenance Mode

In the maintenance mode, the program can generate the receiver and transmitter interrupt request signals. The
program selects the maintenance mode by setting the maintenance bit (SCR 09). Signal SCR 09 H is sent to input

pin 5 of one-shots SCR 07 LOAD and SCR 10 LOAD which qualifies them. Now, if the program desires to generate
a receiver interrupt request signal, it sets Unibus data bits D06 and DO7. When LOAD SCR LOW BYTE H is asserted,

it clocks the SCR 06 flip-flop and sets it. This load signal is inverted by E12 pin 6 which triggers one-shot SCR 07.

The positive pulse from this one-shot clocks the SCR 07 flip-flop and sets it. The (1) L output from the SCR 07

flip-flop is inverted by E31 pin 11 and puts a high on E31 pin 10. The other input of this gate (pin 9) is high also
because the SCR 06 flip-flop is set. The output (pin 8) of E31 goes low and is inverted by E31 pin 6 to generate
RCV INT REQ H.
If the program desires to generate a transmitter interrupt request signal, it sets Unibus data bits D13 and D10 or D13
and D15. The generation of the transmitter interrupt request signal XMIT INT REQ H occurs in the same way as

that described in Paragraph 4.10.3 except that flip-flops SCR 10 and SCR 14 are clocked via one-shot SCR 10

LOAD under program control rather than being directly set by the hardware.

4.11

HALF/FULL DUPLEX CONTROL LOGIC

The logic for controlling half/full duplex operation is contained on the M7289 System Control and Receiver Scan
Module (drawing D-CS-M7289-0-1, sheet 5). Logic is also provided to allow local looping of a transmitted character
for maintenance purposes.

4-56

The logic consists of four type 74157 quad 2-line to 1-line multiplexers and three gates for each of the 16 lines.
Figure 4-31 shows the logic for line 07 which is typical of all lines. Multiplexer E27 chooses between two 4-bit input
words labeled A and B. The B word is SERIAL OUT LINE 07 which is the transmitted character from the UART.
This word is selected during the maintenance mode. The A word is the output of the half/full duplex control logic.
This word is selected during normal operation and can be TTL DATA IN 07 or it can indicate a break condition.

CUH¥SIE DIV

'/
TTL DATA IN O7

pPUHIGT

Space =0 =High

data

Mark ={=Low 7

SERIAL OUT LINE O7

Received
data to UART

74157
Ber

HALF DUPLEX O7 H

~_Space=0=Low
Mark=1=High

END OF CHAR LINE 07 Jcb—fi

L
3

SERIAL IN

LINE O7

ST8
_?_15

SO
—_

Transmitted
from UART

Received data after
passing through

E36
SCR 09

SO =L selects A3
SO =H selects B3

11-1765

Figure 4-31

Typical Haif/Full Duplex Line Control Logic

Word selection is provided by signal SCR 09 H which is sent to the selected (S0) input of multiplexer E27. SCR 09 is
the maintenance bit of the System Control Register. When it is high, the DH11 is placed in the maintenance mode
and input word B is selected. When SCR 09 H is low, the DH11 is placed in the normal operating mode and input
word A is selected.

Assume that the maintenance mode (word B) is selected. A transmitted character is sent serially from UART number
7 as SERIAL OUT LINE 07 to the B3 input of multiplexer E27. It is enabled to the output (f3) of E27 as SERIAL
IN LINE 07 which is sent to the receiver input of UART number 7. In this mode, a character can be looped back to

check portions of the DH11 for maintenance purposes.

In the normal operating mode, SCR 09 H is low and word A is selected. If the system is to be operated in the full
duplex mode, the program clears LPR bit 14 which makes HALF DUPLEX 07 H low. This drives the output (pin
11) of E32 high which in turn is sent to pin 12 of E28. The other input (pin 13) of E28 is TTL DATA IN 07 which
is received data that has passed through the level conversion/distribution panel. During conversion, the received data
is inverted; however, it is restored by another inversion as it passes through E28.

From the output (pin 11) of E28, it enters input A3 of rultiplexer E27 and leaves via output f3 as SERIAL IN

LINE 07. This line is connected to the serial data input of the receiver in UART number 7.

If the system is to be operated in the half duplex mode, the receiver for line 07 must be blinded when the
transmitter for line 07 is sending a character. In the half duplex system, the output data from both terminals is
ORed and presented to both terminal receivers. The sending terminal receives its own transmission. In the DHI1,
this is prevented by blinding the UART receiver so that it does not receive its own transmission (Figure 4-32). In this
way, the computer does not process its own transmission as received data.

4-57

TTL

DATA IN O7

E27

HALF DUPLEX O7
H

L E32

END OF

LIN
Cng
l>
£ o1

E28

B _|

MAINT

APNORMAL
/r&

PORTION OF
MULTIPLEXER

E36

SHOWN AS SWITCH
4

SERIAL

R%%ETVOJR

TRleJrfiSRJI'?;ER

SERIAL OUT

EITHER

STATION CAN SEND,BUT NOT

STATION

RECEIVER

TRANSMITTER

STATION

SIMULTANEOUSLY.
11-1764

Figure 4-32

Half Duplex Connection and Maintenance Logic

Operation in the half duplex mode requires that HALF DUPLEX 07 H be asserted. This puts a high on E32 pin 13.

The other input (pin 12) is the inversion of END OF CHAR LINE 07. This signal comes from the UART and goes
low whenever a character is being transmitted on this line. When UART transmitter 07 is sending a character, END
OF CHAR LINE 07 is low. It is inverted by E36 and puts a high on E32 pin 12. The output (pin 11) of E32 goes
low and is sent to E28 pin 12. With this pin held low, the output of E28 remains high regardless of the state of the
other input which is TTL DATA IN 07. This high signal, which represents an idle line condition, is sent to UART

receiver 07 and blinds it.

4.12

4.12.1

REGISTERS AND BYTE COUNT MODULE M7278

Introduction

The M7278 module contains the Byte Count Register (BC), Line Parameter Register (LPR), Buffer Active Register
(BAR), Break Control Register (BCR), and portions of the Silo Status Register (SSR). It also contains the Unibus
data line receiver and drivers and a multiplexer circuit for reading all DH11 registers. The Byte Count Register has

been described previously in Paragraph 4.7.
4.12.2

Unibus Data Line Receivers and Buffers

The inputs to the registers on the M7278 module come from the Unibus data line signals D(15:00). Each Unibus
signal (BUS D XX L) is sent to a type 380 Unibus receiver whose output is buffered by a type 7417 non-inverting
buffer. This buffered signal (BUF DATA XX H) is sent to the appropriate input of each register. The receivers and

buffers are shown in drawing D-CS-M7278-0-1, sheets 3 and 4.

4-58

4.12.3

Line Parameter Register

The Line Parameter Register (LPR) is composed of four type 74175 quad flip-flop packages as shown in Table 4-7.
Table 4-7
Line Parameter Register Components

LPR Bit

Device Desig

Location

12-15

ES2

Sheet 5

8—11

E37

Sheet 6

4-7

E59

Sheet 7

0-3

E61

Sheet 8

Each 74175 contains four D-type flip-flops with complementary outputs. Signals BUF DATA 00 H through BUF
DATA 15 H are sent to the D inputs. To write into the LPR, signal LOAD LPR H is generated by the address
selector when the LPR address is decoded. LOAD LPR H is used to clock the LPR flip-flops. The 1 output of each

bit is sent to the D2 inputs of the register read-out multiplexer. The 0 output of each bit is sent to other DHI1 logic
as described below.

Bits 00 through 05 are buffered and inverted by type 7437 NAND buffers and sent to the M7280 UART
cards to select character length, number of stop bits, and parity function.

Bits 06 through 09 are sent to the M7288 Line Parameter Control Module to control the speed of the
selected receiver.

Bits 10 through 13 are sent to the M7288 Line Parameter Control Module to control the speed of the
selected transmitter.

Bits 14 and 15 are sent to the M7288 Line Parameter Control Module to control the half/full duplex and
auto-echo modes.

4.12.4

Buffer Active Register

The Buffer Active Register (BAR) is composed of eight 7474 dual D-type flip-flops as shown in Table 4-8.
Table 4-8

Buffer Active Register Components

Device Desig

Location

14 and 15

E55

Sheet 5

12 and 13

E54

10and 11

E63

8and 9

E62

6 and 7

E70

4 and 5

E71

2 and 3

E79

Oand 1

E78

BAR Bit

Sheet 6
Sheet 7

Sheet 8

Each 7474 contains two D-type flip-flops with complementary outputs. Signals BUF DATA 00 H through BUF
DATA 15 H are sent to the D inputs. To write into the BAR, signal LOAD BAR LB + HB L is generated by the
address selector when the BAR address is decoded. This signal is sent to two 7437 NAND buffers, E73 pin 12
(drawing D-CS-M7278-0-1, sheet 7) and E73 pin 2 (drawing D-CS-M7278-0-1, sheet 5). The E73 gates invert and

4-59

buffer LOAD BAR LB + HB L to generate the clock signals for the BAR. These signals are LOAD
BAR A H which
clocks bits 00 — 07 and LOAD BAR B H which clocks bits 08 — 15. Only the (1) H output of the
BAR flip-flops is
used. Each output is sent to the D5 inputs of the register read-out multiplexer. These signals (BAR
00 H - BAR 15

H) are also sent to the transmitter scanner on the M7277 module.
4.12.5

Break Control Register

The Break Control Register (BCR) is composed of four 74175 quad flip-flop packages as shown in Table 4-9.

Table 4-9
Break Control Register Components
BCR Bit

Device Desig

12--15

8—11

Location

E5l

Sheet 5

E38

Sheet 6

4-7

E67

Sheet 7

0-3

E60

Sheet 8

Each 74175 contains four D-type flip-flops with complementary outputs. Signals BUF
DATA 00 H through BUF

DATA 15 H are sent to the D inputs. To write into the BCR, signal LOAD BCR H is generated
by the address
selector when the BCR address is decoded. LOAD BCR H is used to clock the BCR flip-flops. The
1 output of each
bit is sent to the D6 inputs of the register read-out multiplexer. The 0 output of each bit is ANDed
with the serial

data (SERIAL OUT LINE XX) from the UART transmitter of the correspondingly numbered line.
Type 7400

2-input NAND gates are used. The output of each gate (TTL DATA OUT XX) is sent to the
conversion panel.

Setting a BAR bit generates a break condition at the output of the gate corresponding to that bit number.

4.12.6

Silo Status Register

Only bits 0 — 5, 14, and 15 of the Silo Status Register (SSR) are contained on the M7278 module.
This portion of
the SSR is implemented by three 74175 quad flip-flop packages as shown in Table 4-10.
Table 4-10

Silo Status Register Components
SSR Bit

Device Desig

Location

14 and 15

E53

4 and 5

E68

Sheet 7

0-3

E69

Sheet 8

- Sheet 5

The other SSR bits are: 8 — 13 which represent the silo fill level and are located on
the M7279 module; and

which represent current address bits A16 and A17 and are located on the M7277

6 and 7

module.

The SSR is byte addressable; therefore, two clocking signals are used (one for each byte).
To write into the SSR,
signal LOAD SSR LOW BYTE H or LOAD SSR HIGH BYTE H is generated by the address
selector when the SSR
address is decoded with the desired byte requested (DATOB low byte or DATOB high byte).
Each bit of the SSR is

sent to the D7 inputs of the register read-out multiplexer.

Bits SSR 00 H — SSR 05 H from the 1 outputs of the SSR flip-flops are sent to the silo logic
on the M7279 module.
When set, bit SSR 15 H triggers one-shot E77 (drawing D-CS-M7279-0-1, sheet 5) to generate
SILO MAINT PULSE
L. SSR 15 H is sent to the silo multiplexers (module M7279) to generate a test pattern to check
the silo during

maintenance. SILO MAINT PULSE L is sent to the receiver scanner (module M7289) to initiate

a SILO LOAD.

4.12.7

Output Multiplexer and Unibus Drivers

When a DH11 register is read, its output is placed on the Unibus data lines via 16 type 8881 drivers that are enabled
by DATA TO BUS H. This signal is generated by the address selector when a read operation (DATI) is selected.
All registers share the same 16 Unibus drivers. This is accomplished by multiplexing the outputs of the registers.
Sixteen type 74151 8-line to 1-line multiplexers are used. The same numbered bit from each register is sent to one

multiplexer (16 multiplexers total). The single output of each multiplexer is sent to a Unibus driver. Figure 4-19
shows the arrangement for bit 00. The desired register is selected by signals DATA SOURCE A H, DATA SOURCE

B H, and DATA SOURCE C H which are buffered Unibus address line signals BUS
A 01 L, BUS A 02 L, and BUS A
03 L.

‘

The read output multiplexers are located on the following sheets of the D-CS-M7278-0-1 drawing.
Sheet 5: E35, E28, E20, and E12
Sheet 6: E13, E21, E29, and E36

Sheet 7: E66, E58, E50, and E44

Sheet 8: E65, E57, E49, and E43
4.13

M7280 MULTIPLE UART CARD

The M7280 card is a quad-size module that contains eight UARTS and associated decoding, multiplexing, and gating
logic for specific control and flag signals. It also contains a —-12
V supply composed of discrete components
operating on a -15 V source. Refer to Appendix D for a description of the UART.

Figure 4-33 shows the logic for decoding and multlplexmg selected signals. Only one UARTis shown but it is typical

of all eight UARTS on the card.

4.13.1

Transmitter Input Data and Data Strobe Signal

The data to be transmitted (TRAN DATA 1—8) is sent in parallel to 7408 buffers and then to all UARTSs as BUF
TRAN DATA 1-8. The data is used only by the selected UART when its Data Strobe signal (BUF DS LINE X) goes
high to place the data in the transmitter Data Holding Register.

The Data Strobe signal for a particular UART is selected by external logic. These external signals are used to control

a multiplexer (E6) so that the Data Strobe signal for any one of the eight UARTS can be selected. For the DHI1, the

transmitter scanner logic selects the appropriate Data Strobe signal. E6 is a 74155 dual 2-line to 4-line multiplexer
that is connected as a 3-line to 8-line decoder (Paragraph 4.8.2).
4.13.2

Receiver Qutput Data and Received Data Enable Signal

The parallel received data outputs (BUF RCV DATA 1--8) from all UARTS are wire-ORed to form a bus. Only data

from the selected UART is placed on the bus when its Received Data Enable signal (BUF RDE LINE X) goes low.
The bus data is inverted and sent as RCV DATA 1-8 to external logic for processing. In the DH11, these data bits
go to the FIFO logic. The received Data Enable signal for a particular UART is selected by external logic. These
external signals are used to control a multiplexer (E9) so that the Received Data Enable signal for any one of the
eight UARTs can be selected. For the DHI11, the receiver scanner logic (Paragraph 4.8) selecis the appropriate
Received Data Enable signal. E9 is a 74155 multiplexer that operates identically to E6 described in Paragraph
4.13.1.

4.13.3

Reset Data Available Signal

The Reset Data Available signal (BUF RDA LINE X) is driven low to reset the Received Data Available line after the
external logic has accepted the received data from the selected UART. Multiplexer E12 is used to select the proper

Reset Data Available Signal as a function of external logic. For the DH11, it is the receiver scanner logic. E12 is a

74155 multiplexer that operates identically to E6 described in Paragraph 4.13.1.

4-61

BUF TRAN DATA{1-R

TRAN SCAN D —{ -7

TRAN DATA1-8 |

TRAN STROBE
(H) —2 7440
1

—1 7408

BUFFERS

BUERCY

XD1-7

DATA 1-8

RDO-7

7404

INVERTERS

RCV DATA 1-8

14
STBB

PE ERR

STBA

9 BUF DS LINEO
B3 p—

TRANSCAN C —

UART LINEO

Qo8

fB2 P—— BUF DSLINE 1

fB1p—— BUF DS LINE2

1
fBOP—

74155

fA3 p—

FE ERR —
OR ERR
15

LD XD

STBRD

R DONE

CLRR DONE

BUF DS LINE3

BUF DS LINE 4

fA2 p— BUF DS LINE 5
5

— —1paA

fA1J0— BUF DS LINE6
4

fAO Pp— BUF DS LINE 7
SELB

SELA

TRAN SCAN B —J
TRAN SCAN A

RCV SCAND
l

[

RCV DATA

ENABLE —

13{>£

17400

‘

517400

STBA |

iq DB

STBB

[o—* BUF RDE LINEO

fB2 ofi_ BUF RDE LINE1

Ec bB

fB1 p— BUF RDE LINE2

74155

B8O DL BUF RDE LINE3
FA3 pr— BUF RDE LINE4
tazpS— BUF RDE LINES
fFAY 05—— BUF RDE LINE6
4

SELA

STBA|

fB2 10

4
BUF RDA LINEO

BUF RDA LINE1

fB 1 o1 BUF RDA LINE 2

fAO p—— BUF RDA LINE?7
SELB
3

RCV SCAN C

NOTE: Signals with

SELA
13

MASTER OR

5 7

12
E12 fBO p——
BUF RDA LINE3
74155 fA3 b BUF RDA LINE4
a2 p-& BUF RDA LINES
5
{1
{Al P—— BUF RDA LINEG

f AO p—— BUF RDE LINE7
SELB

fB3 p—4-

SCANA

MASTER DA

fB3

RCV

SCAN

STBB

SCANB

E10

RCV

1
14

RCV

BUF

BUF DA LINE
O

BUF DA LINE 1

STB

BUF DA LINE 2 ——{ D2

BUF DA LINE 3 ——1p3
El8
BUF DA LINE 4 — 15
7] pg 4151
BUF DA LINE 5 —— ps
13
_|
e
BUF DA LINE 6 ——— D6
f p—
1

BUF DA LINE
.

7 —— D7
S2
Jg

BUF OR LINE
O

[11

STB

BUF OR LINE1

BUF OR LINE2

BUF OR LINE 3
BUF OR LINE4
BUF OR LINES
BUF OR LINES®

D3
15
” D4
D5
13
D6
12

4
.

BUF

BUF FE LINE 1

g15

74151

f p—

SO
11

FE LINE 7

4
.

BUF FE LINE 3 ——— D3
15
BUF FE LINE 4
”
D4
BUF FE LINE 5
D5
13
BUF FE LINE 6
" D6
BUF

STB

FE LINEO

BUF FE LINE 2

D7
S2

BUF OR LINE7
S1

MASTER FE

g4¢

74151

_ls

f p—

o7
S2
19

S1
10

BUF PE LINEO

BUF PE LINE |

BUF PE LINE 2

BUF PE LINE 3
BUF PE LINE 4
BUF PE LINE 5
:
BUF PE LINE 6
BUF

PELINE 7

MASTER PE

;

STB
DO

D3
15
"
D4
D5
13
> D6

74151

f p—

SO
10

|11

a BUF prefix originate

on the UART card

and do not

leave if.
1-2215

Figure 4-33 Block Diagram of Single UART Showing
Decoding of Control Signals and Multiplexing of

Flag Signals

4-63

4.13.4

Status Signals

Four UART status signals are sampled and sent to external logic.
a.

Received Data Available (BUF DA LINE X), which goes high when a complete
character has been

transferred to the receiver Data Holding Register.

Overrun (BUF OR LINE X), which goes high if the previously received character

present character is transferred to the receiver Data Holding Register.
¢.
d.

is not read before the

Framing Error (BUF FE LINE X), which goes high if the received character has no valid
Receive Parity Error (BUF PE LINE X), which goes high if the received character

with the selected parity.

Each status signal is handled in the same way. The Overrun signal is discussed
as a

signal from each UART is sent to the input of a 74151 data selector (E15).

stop bit.

parity does not agree

typical example. The Overrun

External signals are used to control the

data selector. For the DHI1, the receiver scanner logic selects the appropriate Overrun
signal. The data selector picks
one of eight Overrun signals and sends it to the external logic as MASTER OR. Sixteen
UARTSs (two UART cards)
are used in the DH11 so that the MASTER OR signals from both cards are ORed to provide
a 1 of 16 selection.
4.14

BUS TRANSACTIONS USED WITH THE DH11

4.14.1

Introduction

This section discusses the types of bus transactions used with the DH11. Specific items include:
a.

DATI, DATO, and DATOB transactions with the processor as master to read or write into
the DHi1
registers.

DATI transaction with the DHI11 as master to obtain a message character (byte) from memory.

Generation of an interrupt transaction by the DH11.

This discussion does not include Unibus theory and operation or details of the bus transactions. This information
covered in the PDP-11 Peripherals and Interfacing Handbook.

4.14.2

DATI, DATO, and DATOB Transactions (Processor Master)

With the processor as master, the DH11 registers can
be read (DATI) or written into on a word basis (DATO)
or a
byte basis (DATOB). Examples of these transactions are
shown below.

DATI Transaction
As an example of a DATI transaction, assume that the processor desires to read the contents

Character (NRC) register.
a.

of the Next Received

The processor places the address of the NRC register on address lines A(17:00) and

asserts control lines

C1 = CO = 0. These signals are received by the M7277 module. Address bits AQ1 , AO2, and
AO3

generate
signals DATA SOURCE A, B, and C that are sent to the registers multiplexer on the M7278
module to

select the 16 bits of the NRC register for transfer to the Unibus data lines.

The address has been decoded but no control signals can be generated until the processor

asserts MSYN

After asserting the address and control lines, the processor waits a minimum of 150 ns and, if the bus is
free (SSYN L is clear), it asserts MSYN L.

When the M7277 module receives MSYN L, the address selection logic generates DATA TO BUS H,
READ NRC H, and SSYN L. The NRC register output is connected to the input of the registers
multiplexer that was selected by signals DATA SOURCE A, B, and C. The multiplexer output is
connected to the Unibus drivers on module M7278. Signal DATA TO BUS H s sent to these drivers and

enables the NRC to the Unibus data lines D(15:00). Signal READ NRC H is sent to the silo (module
M7279) to set a flip-flop (see step h). Signal SSYN L is the DH11’s response to the processor that data is
availallda

avdallauvle.

The processor receives SSYN L and the data. After a minimum delay of 75 ns, the processor strobes the
data and clears MSYN L.

After another minimum delay of 75 ns, the processor clears the A and C lines.

When the DH11 receives the cleared MSYN L signal, the address selector logic clears SSYN L and control
signal DATA TO BUS H which clears the D lines.

The processor receives the cleared SSYN L signal which signifies the end of the current bus transaction.
After completion of the bus transaction (steps a — g), the M7279 flip-flop that was set in step ¢ causes a
silo unload operation. This shifts out the just read NRC word and allows the next word in the silo to fall
into the last position which is the NRC register.
DATO Transaction

As an example of a DATO transaction, assume that the processor desires to write into both bytes of the System
Control Register (SCR).
a.

The processor places the address of the SCR on address lines A(17:00), the data on the D lines, and
asserts control lines C1 = 1 and CO = 0. These signals are received by the M7277 module. The address
selection logic decodes the address but no control signals can be generated until the processor asserts
MSYN L. The data is picked up by Unibus receivers on module M7278, buffered, and sent to the D
inputs of the flip-flops that comprise the SCR (module M7289).
After asserting the address and control lines, the processor waits a minimum of 150 ns and, if the bus is
free (SSYN L is clear), it asserts MSYN L.

When the M7277 module receives MSYN L, the address selection logic generates LOAD SCR LOW
BYTE H, LOAD SCR HIGH BYTE H, and SSYN L. Signals LOAD SCR LOW BYTE H and LOAD SCR
HIGH BYTE H are sent to the M7289 module and clock the data into the SCR. The SSYN L signal is the
DHI11’s response to the processor that it has received the data.

The processor receives SSYN L and clears MSYN L. After a minimum delay of 75 ns, the processor
clears the A, C, and D lines.

When the DHI11 receives the cleared MSYN L signal, the address selection logic clears SSYN L and
control signals LOAD SCR LOW BYTE H and LOAD SCR HIGH BYTE H.

The processor receives the cleared SSYN L signal which signifies the end of the current bus transaction.

4-65

DATOB Transaction

As an example of a DATOB transaction, assume that the processor desires to write into the low byte of the System

Control Register (SCR).

The sequence of events is the same as that described in the DATO transaction with the following exceptions:
In step a, the processor asserts C1 = CO =1 and A0O = 0.
In step c, the DH11 address selection logic (M7277 module) generates LOAD SCR LOW BYTE H only which

clocks the SCR low byte (bits 00 — 07).
4.14.3

DATI Transaction With DH11 Master

When the transmitter scanner finds a line that wants to transmit a character, it initiates a request for a non-processor
request (NPR) transaction via the M796 Unibus Master Control Module and the M7821 Interrupt
Control Module in

slot AO2. The M7821 requests the NPR, and when it is granted, the DH11 is bus master. The M7821
sends a
triggering signal to the M796 which initiates a DATI transaction that transfers the character from memory
to the

DHI11.

The sequence of operation is described below and is referenced to Figure 4-34 which is a block diagram

of the M796
and M7821 modules. The DH11 print set contains detailed logic diagrams of the M796 (drawing
D-CS-M796-0-1)

and M7821 (drawing D-CS-M7821-0-1).
a.

The. transmitter scanner on M7277 finds a line that wants to transmit a character. The scanner
stops

which sets the SCANNER STOP flip-flop and asserts SET REQ H.
b.

Signal SET REQ H is sent to pin V2 of M796. This is the clock signal for a redefined D type flip-flop

that is set to assert REQUEST BUS (1) H.

¢.

Signal REQUEST BUS (1) H is sent from pin V1 of M796 to pins Ul and V1 of M7821. These pins are
the inputs to the A master control section of the M7821 module and when they are high, bus request

signal BUS NPR L is asserted at pin U2.

If BUS SACK L is clear on the Unibus, the processor asserts the grant signal BUS NPG IN H. This

is received at pin B1 of M7821.

signal

Signal BUS NPG IN H clears BUS NPG OUT H which stops the bus request at this device
(DH11). It also
asserts BUS SACK L and clears the bus request signal BUS NPR L.

The processor receives BUS SACK L and drops the grant signal BUS NPG IN H. When the current

bus

master completes a data transfer, it clears BUS BBSY L. BUS MSYN L and BUS SSYN
L are also

cleared. Under these conditions, the M7821 asserts BUS BBSY L at pin D1 indicating that the DHI11 is

now bus master.
g

Simultaneous with the assertion of BUS BBSY L, the M7821 asserts MASTER NPR L at pin N1.

Sig: MASTER NPR L is sent to pins N2 and H1 of M796 to initiate the DATI transaction that brings a

cz:2aacter (byte) from memory to the DH11.

Signal ADDR TO BUS L is asserted and BUS C1 L and BUS CO L are both driven high. These
C lines
indicate the control code for a DATI transaction. The DHI1 performs only DATI transactions because

the inputs to the C control logic (pins C1 and J2) are permanently connected to ground. Signal
ADDR

4-66

TO BUS L is sent to the Current Address Register (CAR) on module M7277 to enable the bus drivers
and place the current address on Unibus address lines A(17:00). The current address specifies the
location (byte) in memory that contains the character to be transmitted.

Approximately 200 ns after MASTER NPR L is asserted, the M796 asserts BUS MSYN L on pin El.

The memory has already decoded the current address and, when it receives BUS MSYN L, it places the
data (character) on Unibus data lines D(15:00) and asserts BUS SSYN L.

The DH11 receives the data via Unibus data lines D(15:00). The byte control logic on module M7277
chooses the proper byte and sends the character to the Data Holding Register leads of the selected
UART transmitter awaiting DATA STROBE H. When the M796 receives BUS SSYN L, it asserts DATA
1

WAIT L on pin S2.
m.

Signal DATA WAIT L is fed back to pin S1 on M796 and is the trigger input of a 150 ns one-shot. The
positive-going trailing edge of DATA WAIT L, which occurs 150 ns after this signal is asserted, triggers
M2 which
the one-shot and it asserts DATA STROBE L at pin T2 of M796 and DATA STROBE H at pin
clocks the Unibus data into the Data Holding Register of the selected UART transmitter.

Signal DATA STROBE Lis fed back to pin L2 on M796. This signal starts the operation that clears BUS

MSYN L, ADDR TO BUS L, BUS C1 L, and BUS CO L. When these signals are cleared, END CYCLE Lis
generated at pin N2 of M796 and sent to M7277 to restart the transmitter scanner.

When the memory receives the cleared BUS MSYN L signal, it clears BUS SSYN L and the D lines. The
cleard BUS SSYN L signal signifies the end of the current bus transaction.

M7821

M796

lNT‘ég;UPT

p: vz USI%ZUS D1p—BUS CiL
=

ct MASTER k2 p—bBuUs cOL

—— g2

MODULE £y b ADDRS TO BUS L | gus npe — Bt

BI [—ADDRS TO BUS H | o /& B8 | v

H1
—
g
L

P2 |—END CYCLE H

SSYN H

N2 p—END CYCLE L

INIT B H

E1 p—BUS MSYN L

OuT A H

UT
L1 F——TIMEO(1)H

K1 —— TIMEOUT (O} H

BUS SSYN L—| C1

N1 p——MASTER NPR L
D1 o—BUS BBSY L

T2 p— BUS SACK L

—oJ2

CLR REQ L —¢——Q D2
E: P1

CONTROL U2 p—BUS NPR L

M2 ——DA1T_'A SsTT:é)BE H
DATA

BE L

:,21 A REQUEST BUS (D) H

i_ 311

b o war

‘,E_O R1

H
SET REQUEST

11-1803

Figure 4-34 Block Diagram of M796 and M7821 Modules Used for DH11 Master Control

4-67

If the DHI1 addresses non-existent memory, BUS SSYN L is not asserted by
the memory. If no BUS SSYN L

response occurs within 20 us of the assertion of BUS MSYN L, signal
TIME OUT (1) L is asserted at pin K1 on

M796. The DATI transaction is discontinued. Signal TIME OUT ( 1) Lis sent to

the System Control Register (SCR)

on the M7289. Bit SCR 10 is set and a request for transmitter interrupt
is generated, if the transmitter

enable bit (SCR 13) is set. Signal TIME OUT (1) L is also sent to the
M7278 module and

interrupt

generates a signal that

clears the BAR bit for the selected line. The program clears bit SCR 10 via bit SCR
08. When bit SCR 10 is cleared,
it sends a signal to pin D2 of M796 to clear TIME OUT (1) L.
4.14.4

Interrupt Transaction

Four conditions are used by the DH11 to request an interrupt. Two are termed receiver interrupts.
One is requested
when the program has set the receiver interrupt enable bit (SCR 06) and a character is available in the
silo. The other

is requested when the program has set the storage interrupt enable bit (SCR 12) and

the silo is full at the time the
DHI11 needs to store an additional character. The remaining two interrupts are termed
transmitter interrupts. Both
are dependent on the transmitter and non-existent memory interrupt enable
bit (SCR 13) being set by the program.
One is requested when one or more lines has finished transmission and the
other is requested when the DH11
addresses non-existent memory. Both receiver interrupts are requested by RCV
INT REQ H and both transmitter
interrupts are requested by XMIT INT REQ H. RCV INT REQ H is sent
to the A Master Control section of the
M7821 Interrupt Module in slot A06. XMIT INT REQ H is sent to the B Master Control section
of the same module.
Both sections respond to the same bus request level but Section A (receiver interrupt)
is electrically closer to the

processor so it has the higher priority. A G7360 Priority Selector Card is installed
in slot AQ7 to select the bus

request level. Figure 4-35 shows a G7360 card wired for a bus request level of 5.

The M7821 module in slot A06 is used to generate these interrupts. A simplified
block diagram

shown in Figure 4-36.

Pin J2 is grounded because this section is used for BR requests. The NPR jumper associated

BUS NPR L is wired to pin J1 to improve NPR latency time.

of this module is

with pin J1 is left in and

The interrupt sequence is described below.
a.

Assume that a transmitter interrupt has been requested and XMIT INT REQ H is asserted

on the M7289

XMIT INT REQ H is sent to pins K2 and H2 of the M7281 Interrupt Module. This asserts

BUS REQ B L

module.

at pin P1 which goes to the G7360 Priority Selector Card and out to the processor as

a request for bus mastership.

BUS BRS L. This is

The processor examines BUS BR5 L and if it has the highest priority, the processor asserts
BUS BGS5 IN
H provided BUS SACK L is clear. BUS BGS5 IN H passes through the G7360 card,
the A Master Control

section of the M7281 module, through the G7360 card again to pin E1 of the

M7281 module where it is
identified as BG IN B H. This signal clears BG OUT B H at pin Al which blocks the bus
grant signal and

Signal BG IN B H causes BUS REQ B L to be cleared and BUS SACK L to be asserted
at pin T2.

The processor receives BUS SACK L and clears BUS BG5S IN H which prevents
the issuance of further
grants from the processor during this interrupt transaction.

prevents it from reaching any following devices of the same BR level on the Unibus.

When the current bus master completes its transaction, it clears BUS BBSY L
and BUS SSYN L. In
response to this action, the M7281 asserts its own BUS BBSY L at pin
DI and clears BUS SACK L.

When BUS BBSY L is asserted signal

B MASTER L is asserted at pin S2 and is sent to pin P2 which is B
START INTR L. This asserts BUS INTR L at pin M1 and places the vector address
on Unibus data lines
BUS DATA 02 — 08 L. The DH11 is now bus master.

4-68

G7360 Priority Selector
Card in slot AO7

BUS BR4 A L

" BUS BR6 A L

BUSBR5S AL

TO UNlBUSfi

BUS BG4 IN A H

L BUS BG7 IN AH

Hl BUS BR4 B L

F1 BUS BR5 B L

BUS BR7 A L

~ BUS BG5 IN AH
" BUS BG6IN A H

El BUS BR6 B L

AW
o

D1 BUS BR7 B L

TO UNIBUS

L1 BUS BG7 OUT H

N1 BUS BG6 OUT H
Rl BUS BG5 OUT H

P2
M2

T1 BUS BG4 BC H

V1 BG OUT B H

Ul BG IN B H

J1 BUS REQ B L

691

|N2

|R2

|L2
BG7 AB

BG6 AB H

,,*

B MASTER
CONTROL

(TRANSMITTER
INTERRUPT)

[s1

BG5 AB H

D
h

BG OUT AH

BUS REQ A L
BG IN A H

A MASTER

D
Bl

CONTROL
(RECEIVER
INTERRUPT)

BG4 AB H

Notes

Connection shown for priority level 5 (BRS)
for both receiver and fransmitter interrupts.

% ToM7821inslot FO1if DM11-BB is used;

otherwise to 6727 Bus Continuity card inslot EO2

Figure 4-35 DH11 Priority Level Selection Interconnection Diagram (BRS Selected)

M7281 Moduie
in siot AO6

n-1797

The processor receives BUS INTR L, reads the vector address, and responds by asserting BUS SSYN L

In response to BUS SSYN L, the M7821 asserts B INTR DONE H at pin M2 which is sent to B MASTER
CLEAR H at pin S1. This clears BUS BBSY L, B MASTER L, BUS INTR L, and the vector address. This
constitutes active release of the bus to the processor which clears BUS SSYN L when it receives the
cleared BUS INTR L signal. The processor goes to the interrupt service routine at the specified vector
'

address.

Mrset

|LA MASTER CLEAR H

RCV INTR REQ H _T— ut I%%‘?UELgEETM b A MASTER L
V1

BG IN A H

BG OUT A H

T2 b—— BUS SACK L

—9 2

p—— BUS BBSY L

P1 p——
BUS REQ B L

B MASTER L

p—— BUS INTR L

BUS SSYN L

——d C1

XMIT INTR REQ H

—T: K2

£2 b—— BUS DATA 02 L

BG INBH ——E1

BUS NPR L —————0) J1
B MASTER CLEAR H
s1

B START INTR L

p—— BUS DATA O3 L

p—— BUS DATA 05 L

F2 b—— BUS DATA 06 L
H1 p—— BUS DATA O7 L

>0 D2

N2 p—— BUS DATA 04 L

BG OUT B H ———{ At

A START INTR L

U2p—— BUS REQA L

K1 p—— BUS DATA 08 L

dro

A INTR DONEH

0 p2

B INTR DONE H=

1-1804

Figure 4-36 Block Diagiam of M7821 Module Used for Interrupts

4-70

CHAPTER 5

MAINTENANCE

5.1

INTRODUCTION

This chapter provides information for testing and troubleshooting the DH11 using diagnostic programs (MAINDECs)

to assist in fault isolation.

The test procedure is divided into two parts: Part 1 verifies the internal logic with the DH11 operating in the
maintenance mode: and Part 2 verifies the output interface logic with the DHI11 operating on-line (driving signals to
a terminal),

Diagnostic programs DZDHA through DZDHK are required. Each program consists of a tape and printout that
contains an annotated program listing. The printout contains a descriptive abstract of the purpose of the test and
instructions for its use.

Required equipment includes a PDP-11 System and a Tektronix 454 oscilloscope or equivalent.

5.2 INTERNAL LOGIC TESTS (PART 1)
A.

Programs Required

DH11 logic tests DZDHA through DZDHI
DH11-AD Modem Control Test DZDHK
Procedure

For DHI11-AA, AB, and AC — Assemble the unit and install the M974 Maintenance Card in location BO3
of the distribution panel. The panel does not have to be powered. Other level converter cards should not
be installed.

For DH11-AD and AE — Assemble the unit and install an H8611 test connector into plugs J1and J2 on

the M5906 module in location ABO7 of the DH11 backplane.

Using the oscilloscope, verify that a pulse train exists at each of the M4540 Clock Module outputs. The
period at each output is listed below. Note that these signals are not square waves.

Baud Rate

Period

3600

17.4 us

9600

6.4 us

7200

8.8 us

2400

E1l

26 us

2.54 MHz

400 ns

800 us

110

568 us

1200

52 us

150

417 us

300

208 us

5.068 MHz

200 ns

4800

13 us

1250 us
313 us

200

600

104 us

100

626 us

1800

34.7 us

134.5

465 us

NOTE: Do not attempt to verify the frequency
tolerance to a fine degree. Merely verify the
presence of the signals and confirm whether

not they are reasonably correct, i.e., not off

a factor of two,

etc. These

frequencies are

crystal controlled (confirm that the crystal
is

marked 20.277 MHz) and are more accurate
than any oscilloscope measurement.

If any of the above signals are not present, check the M4540

drawing).

Load logic test DCDHA. Refer to the diagnostic document

divider chain (sheet 2 of the M4540 logic

for the startup procedure.

Run the unit. If errors occur, refer to Paragraph 5.6.2 DZDHA

Failures.

Repeat steps 4 and 5 above, running DZDHB, DZDHC, DZDHD,
DZDHE, DZDHF , DZDHG, DZDHH,
and DZDHI. Paragraph 5.5 gives an outline of each of
these tests. For each of these tests there is a

portion of Paragraph 5.6 that gives a suggested course

of action in the case of fajlure of that test.

Run the above diagnostics DZDHA through DZDHI, and
correct fault conditions so that all diagnostics
run without error for one pass with iterations.

If testing a DH11-AD, check out the modem control modules (M7807
and M7808) by running DZDHK.
To do this, connect four BCOSR cables to J1 and J2 on the
M7808 and M7807, and insert the other ends
into a H861 test connector. (All four plugs on the H861
are identical.) Run test O for 2 passes with
iterations.
Once the unit has passed test Part 1, proceed to test Part

5-2

ON-LINE TESTS (PART 2)

Programs Required

5.3

DHI11 logic test DZDHG

DH11 on-line terminal test DZDHJ

Procedure (For DH11-AD or AE start with step 4)
1.

Connect the H758-A Power Supply to the distribution panel. If an H758-B Power Supply is provided, it

must be plugged into 220 V (H739-A and 739-B are equivalent to H758-A and H758-B).
2.

Remove the M974 Test Jumper Card from location BO3 of the distribution panel.

Install the DM11-DA, DB, DC Line Adapter Cards in accordance with the module utilization drawing for

the distribution panel. Note that DM11-DA and DB line adapters use the master slots for level converter
cards and Bxx slots for cable cards. In the DM11-DC line adapters, the master slots are not used, but
rather the level converter card M5xx goes into the A slot above the cable card M9xx associated with that
converter.

Remove the H8611s from the M5906 module in slot ABO7. Connect two BCOS8S cables from J1 and J2

on the M5906 module to J20 and J17 respectively on the distribution panel.
CAUTION
Read and follow the cable insertion procedure shown in
Figure 2-5 of this manual.
5.
6.

Refer to Figure 2-6 and step 16 in Chapter 2 for the jumper configurations on distribution panel.
Run the DZDHJ on-line test in accordance with the instructions given in that diagnostic. If difficulty is
experienced, the transmit portion of the level converters may be checked by running the DZDHG

diagnostic and observing the pins of the transmit sections of the level converter cards and the output
pins of the cables. Tests are now complete.

5.4
5.4.1

GENERAL CONFIGURATION INFORMATION
Introduction

This section discusses general configuration information primarily related to addressing requirements.

A complete discussion of the DH11 addressing requirements and explanation of the bit assignments and functions
for aii eight DH11
54.2

registers are found in Chapter 3.

DMI11-BB Option

If one or more DM11-BB options are ordered along with the DH11s in a system, the DM11-BBs should be installed
in the DH1 1s that have the lowest addresses and vectors.
5.4.3

DMI11-DC Line Adapters

If DM11-DC line adapters (four EIA/CCITT lines equipped with dataset control features) are ordered, they should
be installed in the distribution panels associated with those DHI1s that have been equipped with the DM11-BB
Modem Control options.

5-3

If less than four DM11-DC line adapters (i.e., 16 lines) are ordered for use on a DH11 equipped with a DM11-BB, use
of PDP-11 RSTS programs require that any DM11-DB line adapters ordered for use in this system be installed in that
DHI11 to bring the total number of level-converted lines to 16. This may mean that one of the DH11s not equipped

with DM11-BBs will not be fully equipped with level converters. If so, it should be the DH11 with the highest
address that is partially equipped.
5.5

DIAGNOSTIC TESTS SUMMARY

5.5.1

DZDHA DHI11 Static Logic Test

Running time:

1 second without iterations, 35 seconds with iterations. Switch settings:

Switch

Action if Set to 1

Halt on error

-Loop in the current test

Inhibit error typeout

Inhibit iterations

‘

Escape to next test on error

Loop with current data

Restart program at selected test

Reselect vector and control register
address after program restart

Tests 01 through 10 (octal) test each register of the DH11

for response.

Tests 11 through 14 test to make sure that the SCR, LPR, BCR, and SSR register can be cleared.

Tests 15 through 27 test the ability to set and clear bits 0, 1, 2, 3,4, 5, 6V, 9,12, 13, and 15 (decimal) of the SCR.
Tests 30 through 34 test the ability in maintenance mode to set and clear bits 7, 8, 10, 11, and 14 (decimal) of the
SCR.

Tests 35 through 37 test to make sure that bits 7, 10, 14 can only be cleared while in maintenance mode.

Tests 40 through 56 test the ability to set and clear bits of the Line Parameter Register one at a time.
Tests 57 through 76 test the ability to set and clear the bits of the Break Control Register one at a time.
Tests 77 through 105 test the ability to set and clear bits 0, 1, 2, 3, 4, 5, 15, of the Silo Status Register one at a
time.

Tests 106 through 124 set the Line Parameter Register to all 1s and clear the bits one at a time.

Tests 124 through 144 do the same for the Break Control Register.

Tests 144 through 153 do the same for the Silo Status Register bits 0, 1, 2, 3,4, 5, 15.
If a failure occurs, refer to Paragraph 5.6.1, DZDHA Failures.
5.5.2

DZDHB DHI11 Memory Test

Running time: 2 seconds without iterations, 25 seconds with iterations. Switch Settings: Same as DZDHA.

Test 1 is the bus address memory addressing test. It loads each location in the bus address memory with the address
of that location. The address is repeated every four bits. The test verifies that each location in the bus address
'
memory was addressed.
Test 2 does the same thing to the byte memories as test 1 did to the current address memories.

Tests 3 through 22 set a 177777 address in bus address memory location 0, verify it, clear it, verify that it is clear,
then repeat for location 1, etc.

Tests 23 through 42 do the same for the byte count memory locations.

Test 43 is similar to tests 3 through 22 except that in addition to verifying that the selected location was set to

177777, a check is made to make sure that no data has appeared in any of the other bus address memory locations

(they should all be clear except the one set to 177777).

Test 44 is the same as test 43 but uses 125252 as the test word.

Test 45 is the same as test 44 but uses 52525 as the test word.

Tests 46, 47, 50 are the same as tests 43, 44, 45 but are applied to the byte count memories.

Tests 51 and 52 set all locations for the bus address memories (51) or byte count memories (52) to 177777 and then

set selected location to 0. No other location should change.

Tests 53, 54, and 55 test the ability to set and clear the memory extension bits.
In case of failure, refer to Paragraph 5.6.2, DZDHB Failures.
5.5.3 DZDHC DH11 Transmitter and Receiver Basic Logic Test

Running time: 23 seconds without iterations, 32 seconds with iterations. Switch settings: Same as DZDHA.
Test 1 sets character available interrupt enable and verifies that no interrupts occur.

Test 2 is the same as test 1, but silo overflow interrupt enable.
Test 3 is the same as test 2, but transmitter done interrupt enable.

Test 4 sets character available interrupt enable, then (in maintenance mode) sets character available, and then verifies
that an interrupt occurs.

Test 5 is the same as test 4, but silo overflow.

Test 6 is the same as test 4, but transmitter interrupt enable/non-existent memory.
Test 7 is the same as test 4, but transmitter interrupt enable/transmitter done.

Tests 10 through 27 set byte count for line 0, set BAR bit for line 0, verify BAR bit for line O clears, verify
transmitter done set. This is done for line 0, then 1, then 2, etc.

Tests 30 thrdugh 47 set byte count for all lines to 1, then set BAR bit for line 0, verify that byte count for line 0

goes to 0, that bus address for line 1 is incremented, and that all other byte counts and bus addresses are unchanged.
This is done for line 1, line 2, etc.

5-5

Test 50 tests the silo maintenance mode by forcing a 1010101010101010 into the silo and verifies that the character

available

bit is set, that a character available interrupt occurs, that NRC bit 15 is
1010101010101010 pattern appears correctly in the Next Received Character (NRC) Register.

set,

and

that

the

Test 51 verifies that the silo up counter counts up correctly.

Test 52 verifies that the silo down counter counts down correctly.

Test 53 tests the silo alarm level for 0, 1, 2, 4, 8, 16, and 32 characters to see that the alarm goes off (i.e., an
interrupt occurs) at the proper fill level.
If a failure occurs, refer to Paragraph 5.6.3, DZDHC Failures.

5.5.4

DZDHD DH11 Speed Selection Logic Test

Running time:
DZDHA.

15 seconds without iterations, 1 minute 55 seconds with iterations. Switch settings: Same as

Test 1 tests to see that there is a clock for speed 1. It then sends three characters at a selected speed on line 0. It
verifies that transmitter done occurs at that selected speed and that the amount of time taken is less at this speed
than at the previously selected speed. This is done for 15 (octal), 13 (decimal) speeds at increasing speeds.
Tests 2 through 15 are the same as test 1, but for lines 1, 2, 3, etc., up through line 14 (octal).

Tests 16 through 32 are similar to tests 1 through 15, but for one character, and receiver done is checked and timed
rather than transmitter done.

If a failure occurs, refer to Paragraph 5.6.4, DZDHD Failures.
5.5.5

DZDHE DHI11 Character Length and Basic Data Test

Running time:

1 second without iterations, 20 seconds with iterations. Switch settings: Same as DZDHA.

Tests 1 through 100 transmit an all 1s character at 9600 Baud, changing first the character length (5 bit, 6 bit, 7
bit,

8 bit) on line 0, then doing the same on line 1, etc.

If a failure occurs, refer to Paragraph 5.6.5, DZDHE Failures.
5.5.6

DZDHF DH11 Single Line Data Test

Running

time: 50

minutes

seconds

without

iterations,

settings: Same as DZDHA.

52 minutes 25 seconds with iterations. Switch

Tests 1 through 20 transmit all 8-bit characters one at a time on lines 0, 1, 2, etc.
Tests 21 through 40 transmit a block of 400 (octal) characters on line O; character length is 8 bits. Line speeds start
at 50 Baud and are incremented to 9600 Baud. A block of 400 characters is transmitted at each speed. This process

is repeated for lines O through 17 (octal).

Tests 41 through 60 transmit a block of 400 (octal) characters on line 0; speed is 9600 Baud; character length is 5
bits for the first 400 characters and is then changed to 6 bits, 7 bits, and 8 bits for future blocks of 400 characters.

This process is repeated for lines O through 17 (octal).

If a failure occurs, refer to Paragraph 5.6.6, DZDHF Failures.

5-6

5.5.7

DZDHG DH11 Multi-Line Data Test

Running time: 4 seconds without iterations, 5 minutes 33 seconds with iteration. Switch settings: Same as
DZDHA.

Test 1 — In this test the silo alarm level is set to 0. The receiver is to be serviced on a per character basis in interrupt
mode. Transmitter interrupts are disabled. A binary count pattern of 400 (octal) characters is sent on all lines.
Character length is 8 bits for all lines.

Test 2 — Same as test 1, but all lines are tun at 9600 Baud. Silo alarmlevel is set as high as possible. No receiver
interrupt servicing, but rather characters are read from the silo as quickly as possible, testing the valid data bit of the
JRPP.S
NS P

ado laid

~L 4ln

If a failure occurs, refer to Paragraph 5.6.7, DZDHG Failures.
5.5.8

DZDHH DH11 Auto-Echo Test

Running time: 10 seconds without iterations, 2 minutes 40 seconds with iterations. Switch settings: Same as
DZDHA.

Tests 1 through 20 enable auto-echo on line 0, transmit an 8-bit character on that line at 9600 Baud, receive and
verify that character. This continues until 64 characters have been received. Then disable auto-echo. Exactly one
more character should be received. This is done for all 16 lines.

Tests 21 through 40 are similar to tests 1 through 20, but the data checked is a binary count pattern on all lines
except that for which the auto-echo is being run. Lines are auto-echoed one line at a time while other transmissions
take place.

Test 41 transmits one character on each line with auto-echo enabled. Each line receives 64 characters.
If a failure occurs, refer to Paragraph 5.5.8, DZDHH Failures.
5.5.9

DZDHI DH11 Break and Half-Duplex Test

Running time: 10 seconds without iterations, 3 minutes 25 seconds with iterations. Switch settings: Same as
DZDHA.

Tests 1 through 20 test the break facility by first flushing the UART transmitter for a line by transmitting two nulls
and setting the break bit for that line. A binary count pattern is transmitted. Only one character should be received
and that should be a break character. This is done for each line sequentially.

Tests 21 through 40 set half-duplex on a line. A binary count pattern is transmitted. No characters should be
received. This is done for each line sequentially.

If a failure occurs, refer to Paragraph 5.5.9, DZDHI Failures.
5.5.10

DZDH]J Echo Test

This diagnostic contains a test which verifies that all characters (0—377 octal) will echo on each line (0—17 octal)
with standard DH11 terminal attachments (TTY 33, 35 or VTO5 etc.) using ASCII asynchronous code (110 baud
with two stop bits and 300, 600, or 1200 baud with one stop bit).
The starting address is 000200 octal.

5-7

Operational switch settings are:
SW15=1

Halt on error

SW13=1

Suppress error typeout

SW02=1

Reselect line number and baud rate

SW00=1

Change parameters at program restart

5.5.11

DZDHK DH11-AD Modem Control Test

This program is a test of the modem control multiplexer used with the DH11-AD option. The program is divided
into functional test groups as follows:
Group 0: All line scanner and line multiplexer functions are tested using the H861 test connector.

Group 1: A single line is tested using the modém cable and an H315 test connector.
Group 2: Connect-disconnect tests for 103A modems.
Group 3: Connect-disconnect tests for 202C modems.
The starting address is 000200 octal.
Operational switch settings are:

5.6

SW15=1

Halt on error

SW14=1

Loop on current test

SW13=1

Suppress error typeout

SW11=1

Suppress iterations

SW10=1

Escape to next test on error

SW09=1

Freeze data

DIAGNOSTIC FAILURE ANALYSIS

5.6.1

DZDHA Failures

If the following message is received:

01346 REGISTER DID NOT RESPOND
ADDRESS

760020
this indicates that the PDP-11 processor did not receive a slave sync response from the DH11. The following
checks should be made.

Was the address entered correctly when responding to the questions asked in the opening dialogue of
diagnostic DZDHA? The M7277 module (located in slot 04) is normally supplied with all nine address
jumpers in place, making the DH11 address 160000. The following jumper cut table may be of use in
verifying that the address cut into the M7277 matches the address typed into the diagnostic.

Jumpers Cut

Address

None

160000

160020

160040

160060

160100

160120

6-5

160140
160160

6-54

160200

7
74

160220

7-5

160240

7-5-4

160260

7-6

160300

7-6-4

160320

7-6-5

160340

7-6-54

160360

etc.

The numbers identifying the jumpers are located on the M7277 etch, right underneath the jumpers. For
the set of five jumpers located near the center of the board, the order top to bottom is: 8-11-12-10-9. In
the set of four jumpers located near the edge of the board, the order top to bottom is: 7-4-5-6.
'If the address entered in the opening dialogue of the diagnostic agrees with the jumpered-in address,
reload the diagnostic, making sure that there is no check sum error (i.e., that the bus data lights on the
computer console are all out when the tape loading finishes). Now try the diagnostic again.

If the problem stili exists, look at M7277 E72 pin 4. A positive pulse about 1/2 us long and occurring
approximately every 5 us should be observed when the following toggled-in program is run.

5000/

12706

5004/

12737

5010/
5012/

4
12737

5002/

5006/

1000

SETUPSTACK
|

5014/

s030 ~ SETUPFORTRAP
|

5016/

5020/ .

o0
5024/
5026/
5030/

340

5737

1600xx

137
5020
2

SET UP

FOR TRAP
TEST

DH REGISTER*
JUMP
TO 5020
RTI

*The number used in location 5022 of the toggle-in program should be the address cited in the error
message (Paragraph 5.6.1).

If the pulse mentioned above occurs, use it as a trigger source while observing with a second scope

channel, E72 pins 1, 2, and 5. There should be a high at each pin during the time that pin 4 is high. If
these conditions are met, a negative pulse that is the complement of the positive pulse on pin 4 should
appear as the output (pin 6). A shorter negative pulse should appear at E29 pin 10 along with some
other pulses. Observing E29 pin 10, without using a trigger source such as E72 pin 4, provides useless
information because the slave syncs on the Unibus are observed. The slave sync that corresponds to the
positive pulse (but is shorter) on E72 pin 4 is the desired signal.

If the following message is received:
002312 MASTER CLEAR ERROR

EXP

REC

ADDRESS

000000

771377

760020

this indicates that master clear was unable to clear the register named. The following

made.
1.

checks should be

The failure of master clear to clear a register is the result of one of several things. It could be that

master

clear is not being generated; that the register is not being cleared despite the receipt of an Initialize
signal; or that the register is actually being cleared, but that the output of the register is not
being

properly presented back to the Unibus. The following procedures attempt to ascertain

effects is occurring.

which of these

Begin by toggling in the following program which generates a programmed Unibus Initalize:

Look

5000/

RESET

5002/

137

JUMP

5004/

5000

at M7277

TO 5000
pins EF2 and FV2 for Initialize high, a pulse about 20ms long
that occurs

approximately every 60 ms. Also look at pins FR2 and FM2 for
an Initialize low pulse. If neither of

these pulses can be found, look at pin AA1 to see if Initialize is being generated
on the Unibus. If all of
these points show the proper signals, generate DH11 Initialize by toggling in
the following program:

5000/

RESET

5006/

5002/

160020

52737

BIS

5010/

5004/

137

4000

BIT 11IN

5012/

5002

THE SCR
JUMP
TO 5002

Check the pins mentioned above for the signals mentioned above (but slightly longer — about 2.4 us).

If
these pulses are not seen at any of the above points, check pin FC1 for negative pulses of
2.4 us
duration. Check EL2 for positive pulses.
If M7277 pins EF2, FV2, FR2, and FM2 do show the proper signals, check the following logic:
SCR not cleared: check M7289 E7, E11, E19, E41, and E50.
LPR not cleared: check the M7278 E37, E52, E59, and E61.
BCR not cleared: check the M7278 E38, E51, E60, and E67.
SSR not cleared: check the M7278 E53, E68, and E69.
For the ICs cited above, ensure that the Initialize signal arrives (run the toggle program from
step B2

above) and produces the proper clearing action.

Run the diagnostic and loop on the current test when reaching the error-producing test. Repeat step 5

above. If the bits cited by the diagnostic as being not cleared are in fact being cleared at the ICs
mentioned above, the problem must be in the 74151 multiplexers in the M7278, the 8881s associated

with those multiplexers, or in the data source selection leads. On the M7278 print, signal DATA TO BUS
HIGH (pin AB1) may be used as a trigger source while looking at the 8881 inputs for the bit that the

diagnostic claims is not being cleared.

5-10

The remainder of the DZDHA test sets and clears the bits of the aforementioned registers one at a time. The
following error message is typical:

002610

SYSTEM CONTROL REGISTER ERROR

EXP

REC

ADDRESS

000001

000000

760020

In the case of such a message referring to the System Control Register (SCR), check the M7277 pins CP1
and CT2 for positive pulses while running the diagnostic on a loop of the failing test. These pins should
have positive pulses somewhat shorter than 0.5 us. If these pulses are observed, check M7289 E7,E11,
E19, E41, E47, E50 for proper clocking, proper input data, and proper operation. The input data comes
from the buffered data buffers on the M7278.

In the case of the Line Parameter Register (LPR), check pin EP2 of the M7277 for positive pulses of less
than 0.5 us duration, while looping on the current failing test. Check EH2 for a 300 ns pulse. Also check
ED1, EC1, EAl, etc., for the appropriate Control Strobe signal for the line in question. Use the pulse at
EH?2 as a trigger source. If the appropriate pulses are found, check M7278 E37,E52, E59, and E61 for

proper clocking, proper input data, and proper operation. To check input data, use Control Strobe as the
trigger.

NOTE

All problems encountered in running DZDHA must be
solved before running any other diagnostics.

Etch shorts, pads that touch, etc., are more common
than bad ICs.

To check input data at a flip-flop, use the clock lead to
that flip-flop as a trigger (provided there is a signal on
that clock lead), otherwise all of the buffered data
signals from the Unibus will be observed.

In the case of the break control register (BCR), check M7277 pin FU1 for positive pulses, and check

M7278 E38, E51, E60, and E67 for proper clocking, input data, and operation.

In the case of the silo status register, check M7277 pins CP2 and CR1 for positive pulses, and M7278
E53, E68, and E69 for proper clocking, input data, and operation.

If proper results are obtained in following the procedure outlined above, check the 74151 multiplexers

and 8881s as described in Paragraph 5.6.1 step Bé.

5.6.2

DZDHB Failures

Itis assumed that diagnostic DZDHA has been run successfully.

5-11

If the following message is received:
001376

~ BUS ADDRESS MEMORY ERROR

EXP

REC

ADDRESS

010421

010420

this indicates failure to properly read or write the currrent address memories. If the
following message is

received:

001514

BYTE COUNT MEMORY ERROR

EXP

REC

ADDRESS

010421

010420

this indicates failure to properly read or write the byte count memories.
It is often useful to arrange the PDP-11 console switches to escape to the

next test on error by setting switch
10 to the 1 state. After accumulating several error messages and writing
down the received and expected data
in binary instead of octal, conclusions can be drawn.
Diagnostic Output (Octal)
Expected

Received

Binary Representation
Expected

Received

004376

004356

006233

0000010011111110

006213

0000010011101110

0000110010011011

0000110010001011

Notice that bit 04 is being dropped. If the problem is this simple, or involves a few adjacent

bits, go to step I.

If the received data is consistently all Os, it would be wise to look at M7277 pin EN2 DATA
TO BUS HIGH
while running the following program that reads the current address:

5000/

52737

BIS

5016/160026

5002/

4000

OF CA TO RO

BIT111IN

5020/

5004/

137

160020

JUMP

THE SCR

5022/

5006/

5000

13737

MOV CONTENTS

5010/

177570

OF SRTO

5012/

160026

THE CA

5014/

13700

MOV CONTENTS

TO 5000

If pin EN2 does have a signal (several hundred nanosecond positive pulse every few microseconds)
, run the
diagnostic in a loop on the current (failing) test and look at EN2. The signal should still
be there, but not

occurring so often. Using this signal as a trigger source, examine the 74151 multiplexers

drivers (M7278).

and the 8881 Unibus

If the received data is not all Os but appears to bear little if any relationship to the expected

procedures outlined in steps E, F, G and H.

data, follow the

For current address memory failures, run the toggled-in program from step D. Look at the
M7277 E48 pin 1.
There should be positive pulses here, each several hundred nanoseconds long and occurring
every few

microseconds.

For byte count memory failures, repeat step E, but use the following toggled-in program:
5000/
5002/
5004/
5006/

52737
4000
160020
13737

5010/177570
5012/160030
5014/ 13700
5016/160030

5020/
5022/

137
5000

and look for pulses again at M7277 E48 pin 1. This test and the test in step E ensure that the current address
and byte count memories are receiving their selection information from the proper point. It is also important
to loop the program on the failing test and ensure that bits SCR 00, 01, 02, 03 progress properly from the
System Control Register (M7289) to the inputs and outputs of M7277 E43.
G.

For current address errors, run the toggle-in program from step D which loads one Current Address Register.
Look at E57 pin 1 for positive pulses of several hundred nanosecond duration. If the pulses are there, use them
as a trigger to look at E50 pin 1 for 60 ns pulse that beings 90 ns after the E57 pin 1 pulse begins. This 60 ns
pulse is the write enable pulse to the current address memories.

For byte count errors, run the toggle-in program from step F which loads the Byte Count Registers.

Look at M7278 pin CJ1 for positive pulses and at M7278 pin BT2 for 60 ns pulses occurring 90 ns after the
CJ1 pulses begin. These are the write enable pulses for the byte count memories.

When performing either test G or H, it is important to look at M7277 pin FK1 where 30 ns positive pulses
should occur at the conclusion of current address memory write enable pulses and byte count memory write
enable pulse. Those 30ns pulses clear the WRITE CURRENT ADDRESS and WRITE BYTE COUNT
flip-flops.

If, as explained in step C, a particular bit is incorrect, examine the logic associated with that bit. If the faulty
bit is in a current address, examine the M7277. If it is in a byte count, examine the M7278. Run either the
toggle program from step D for current addresses or the toggle program from step F for byte counts and check
to see that load pulses are reaching the 74193 being used by the bit in question. Also make sure that a write
enable pulse is reaching the 7489 involved.

Run the diagnostic, looping on the failing test, while examining the data paths for proper operation. Use the
load pulse terminal (pin 11) of the 74193 as a trigger source while looking at data inputs to the 74157 (also be
sure that 74157 pin 1 is high) and at the data inputs to the 74193.
5.6.3

DZDHC Failures

If the following message occurs:

001446

UNEXPECTED INTERRUPT

CONTROL REGISTER CONTENTS
000300

000000

a failure in the character available, silo overflow, and transmitter done interrupt circuitry is indicated. This
logic is located on the M7289. Loop on the failing test and observe pin DD1, which should be high. E19 pin 6
should also be high. E50 pin 9 and pin 5 should be low.

If DD1 was low, examine the logic of the M7279 Silo Buffer. The M7279 should also be examined if the signal
at E50 pin 10 was not a constant high. Signals on E50 pin 4 come from the M7278 E14, and should be
constantly high at this point in the testing.

5-13

If the following message occurs:

002202

NO INTERRUPT

a failure in the interrupt generation circuitry is indicated. Loop on the failing test. If it is test 4, look at E31
pin 8 on the M7289. If the failing test is test 5, look at M7289 E31 pin 3. If the failing test is test 6, look at
M7289 E48 pin 8. If the failing test is test 7, look at M7289 E48 pin 3. In each of the above cases, negative

pulses (signal normally high, occasionally going down to 0) should be observed. The signal must not be either
always high nor always low, as transitions are necessary for successful operation of the M7821 Interrupt

Control module. If negative pulses are found, look at pins DP1 and FM1 for positive pulses. If those pulses are
found, try a new M7821 after examining the inputs to the M7821 for proper inputs and proper vector
jumpering. Remember that the M7821 jumpers are left in to assert 1s on the bus and removed to assert Os. For
failures in the character available and silo overflow interrupts, be sure that there are positive transitions on

M7821 pins Ul and V1. For transmitter done and non-existent memory interrupts, be sure that there are
positive transitions on M7821 pins K2 and H2. The M7821 referred to is that located in slot A06.
If a failure message such as that below occurs:

003150

NO INTERRUPT

003160

TRANSMITTER DONE NOT SET

determine the line number and then verify that the BAR bit for that line actually gets set. This may be done
by looping on the failing test and examining the BAR register on the M7278. Check for the generation of the
transmitter finished pulse by running the following toggle-in program which sets the byte count for each line

to all 1s and then to all Os.

5000/

52737

BIS

5020/

160030

TO BC

5002/

4000

BIT 11

5022/

137

JUMP

5004/

160020

INSCR

5024/

5000

5006/
5010/

12737
777777

MOVE
ALL ONES

5012/

160030

TOBC

5014/

12737

MOVE

5016/

000000

TO 5000

ALL ZEROES

Note that a permanent low on M7278 pin AS2 would cause the E14 one-shot to not fire. Pin AS2 should be
always high. Look for transmitter finished pulses on pin AR1. Also look at the CLEAR BAR bit signal
appropriate to the line in error. Verify that the signal from AR1 causes pin FR2 of the M7289 to go high

and/or stay high.
If the following failure message occurs:

EXP

010120

BYTE COUNT ERROR
REC

777777

000000

loop on the current test and examine the BAR bit (M7278) appropriate to the line for which the error is
reported. This BAR bit should change back and forth between 1 and O during the test looping.

In the case of the following message:

013330

SILO DATA ERROR

EXP

REC

725252

706400

the silo test pattern was not properly received. Loop on the failing test and lock at M7278 pin CN2 which
should have positive pulses. Observe pin FV2 for 1 us negative pulses that occur as the result of the CN2
pulses. Look at M7279 pin AR1 for the same pulses that were observed on M7278 pin CN2, Using those pulses
as a trigger, look at pins 4 and 9 of the following ICs on the M7279: E2, E7, E12, and E16. These points
should be low for at least the duration of the pulses on AR1. Look at pins 7 and 12 of these same ICs for highs
occurring for at least as long as the AR1 pulses. These checks confirm that the proper test pattern is being
prepared for entry into the silo, that the silo maintenance bit is being set, and that the silo maintenance pulse

is being generated.
The silo maintenance pulse is used in the DH11 receiver logic to simulate the finding of a Data Available flag,
thus causing the silo logic to by cycled.

Observe pin FF1 on the M7289 for the same 1 us negative pulses that were previously observed on pin FV2 of

the M7278. Using these pulses as a trigger source, observe pin AJ2 (LOAD SILO L) where negative pulses
should occur about 2 us after the FF1 pulse. There will be a varying time between the FF1 pulse and the AJ2

pulse because the receiver scanner/receiver logic has to wait for a tick of the 2.54 MHz clock before
commencing operation (make sure that there is such a clock signal arriving at the M7289) and this clock is in
no way related to the instruction that set the silo maintenance bit and thus generated the silo maintenance
pulse that appears on FF1.

Notice that the function of the FF1 pulse is to set SCANNER STOP and thus cause the receiver sequencer

(M7289 E21) to generate LOAD SILO L.
Confirm the existence of LOAD SILO L pulses at pin BJ2 of the M7279.

Be sure that there is a 5.068 MHz (period = 200 ns) clock signal at pin BN1 of the M7279.
Be sure that there is =15 V at pin AB2 of the M7279.
Check pin BV2 of the M7279 to make sure that the LOAD REQUEST flip-flop is being set and cleared. It is

set by the LOAD SILO L pulses (see step G).
Check BK2 for 30 ns negative pulses occurring about 170 to 370 ns after LOAD REQUEST sets. (One can use
the 5.068 MHz signal as a trigger and turn up the scope intensity). Since these pulses clear LOAD REQUEST,
the negative transition of BV2 might also be a good trigger source.

Look at pin BK1 for positive pulses about a half microsecond wide. These pulses are the program reading the
NRC register and hence cycling a character out of the silo.

Observe pin AL1 for negative pulses, occurring throughout the looping on the failing test. If these pulses only
occur when starting the program, the silo is probably being filled up, perhaps indicating failure in the unload
circuitry.

Observe BL1 for positive pulses. These rely upon E9 pin 8 being low at times.
Observe BV1 for negative pulses. Trace the effects of these pulses through the M7289 logic.

5-15

5.6.4

DZDHD Failures

Be sure that the lead entitled Z0 Baud is ground and hence that the TOP BUF Z0 BAUD H and BOT BUFF Z0

BAUD H signals are permanently high. Refer to the M7288 circuit schematic.
Check all TOP BUFF and BOT BUFF signals at M7288 E66, E67, E69, E70, E72, E73, E74, E75. Use the

table on the first page of the M4540 circuit schematic to determine the proper periods for the various Baud
rates. Using an oscilloscope the period can be measured only approximately; however, specific clock signals

can be identified to verify that no two are crossed or interchanged.
Ensure that the aforementioned signals reach E4 and E2 at the appropriate pins.
Looping on the failing tests, make sure that the proper BUFF LPR signals exist at the inputs, that the Control
Strobe signal occurs (300 ns), that there is no noise on the Control Strobe signal, and that the outputs of the
74174 and 74175 of the failing line are being properly set.

Beware of the fact that the diagnostic detects problems by comparing the time it takes to transmit at one
speed with the time it took at a previous speed. When an error is reported, it may be the speed tested prior to
the present speed that was in error.
Example: Assume the speeds should be 110, 134.5, 150 and that they are actually 110, 300, 150. The

diagnostic will determine that things happened faster at the second speed than at the first speed (300
compared to 110), but when it gets to the third speed (150) it will report an error. The actual problem is the
second speed where one finds 300 instead of 134.5.

5.6.5
A.

DZDHE Failures
While looping on the failing test, look at CD2 of both UART cards for a 300 ns Control Strobe signal. Check

the CH2, CJ1, CF2, CJ2, CF2 pins for proper parameter data.
B.

Refer to Paragraph 5.6.7, DZDHG Failures, for further tests.

5.6.6

DZDHF Failures

In most cases it should be possible to create failures at a faster rate using the DZDHG diagnostic. If fewer or
no failures occur running the DZDHG for a time equal to that during which the DZDHF ran, the problem
most likely concerns the loading of line parameters, since the DZDHF changes the line parameters whereas the

DZDHG does not.

It will generally be beneficial to try the same procedures for troubleshooting DZDHF as DZDHG so it is
recommended to follow the procedures below, even if the DZDHF is running.
5.6.7
A.

DZDHG Failures

If difficulties occur with one line only, swap M7280 UART cards and see if the problem moves from line 1

(octal) to line 11 (octal), etc.
Be sure that the Transmit Strobe signal to the UARTS is long enough. It must be 250 ns or more. Note that

this requires an added capacitor on the M796 to generate a wider DATA STROBE. (This capacitor is 100 pF.)
If difficulties occur on several lines, but only on one bit, check the buffered data leads, tran data leads, silo
inputs, silo outputs, M7278 multiplexers, and M7278 Unibus drivers. Also check the auto-echo switch (M7277

E39 and E42) and the byte switch (M7277 E40 and E43).

5-16

Receipt of a character that is one lower than that expected may be a failure of the current address up counter
system to function properly or a failure of the byte switch (see above).

Receipt of a character one higher than expected might be a silo unloading problem; perhaps caused by noise
on the read NRC line or perhaps by improper one-shot times.

Check all one-shots for accuracy. They should be no more than 20 percent longer or 10 percent shorter than
their nominal values. This is particularly true if they are on the short side and the unit is running in high
temperatures.

Be sure that there is no crosstalk on the control strobe leads.

5.6.8

DZDHH Failures

If all of the previous diagnostics have run error-free, failures of this test can only be in a limited area.

Loop on the failing test and examine the M7288 Line Parameter Module for the presence of a high on AE
ENAB for the failing line.

Make sure that the above signal reaches the E22 74154 multiplexer on the M7289. The following toggle-in
program sets auto-echo enable on one line and allows the receiver scanner to run continually.

5000/

52737

BIS

5022/ 137

JUMP

5002/

4000

BIT 11

5024/5006

TO 5006

5004/

160020

IN SCR

5006/

13737

MOV CONTENTS

5010/

177570

OF SR

5012/

160020

TO SCR

5014/

52737

BIS

5016/

10000

BIT 15 (AE ENAB)

5020/

160024

INLPR

Look at pin 10 of E22 on the M7289 for negative pulses (i.e., the signal is almost always high, but has

occasional excursions down to nominal 0 V).
Again operate the diagnostic, looping on the failing test. Look at M7289 E18 pins 2 and 6 and E10 pins 3 and

4 for highs. Look at E18 pins 10 and 14 for high. Some of these may be alternately high and low, but what is
important now is that they are high at least sometimes.
Look at M7289 E14 pin 3 for low pulses, E2 pin 3 for high pulses, E2 pin 6 for low pulses, and E1 pin 4 for

high pulses. If E2 pin 3 checks out but the rest do not, check E2 pin 5 for being high at the same time as pin 4
(this should occur). Check E1 pin 5 for being low at the same time as pin 6 (this should occur). If the proper
signals cannot be found on E2 pin 5 or E1 pin 5, examine the receiver sequencer E21.

The E21 waveforms can only be observed if the SCANNER STOP flip-flop E44 pin 5 is setting and clearing

(i.e., the receiver scanner mechanism is servicing characters). See Figure 4-26.

5-17

M7289 E21 Waveforms
Pin

Duration

2400 ns

2000 ns

1600 ns

1200 ns

800 ns

400 ns

Trace the AE GO L lead and make sure that it causes M7289 E34 to switch the UART transmitter scan leads
and that it causes M7277 E39 and E42 to switch the data source leads for the UART transmitters.

If the problem occurs with one line only, try swapping the M7280 UART cards to see if the problem
follows — i.e., see if the problem that used to be reported on line 7 (octal) is now found on line 17 (octal).

5.6.9

DZDHI Failures

If the following message is received:
001504

MORE THAN 1 CHARACTER RECEIVED

001524

BREAK DATA ERROR

EXP

REC

EXP

REC

000400

000000

720000

700000

it indicates that the break circuitry did not function pro'perly.
Check the M7278 E38, E51, E60, and E67 to make sure that the break bit is being set for the failing line. Do

this while looping on the failing test. Check M7278 E45, E46, E75, E76 to see if the setting of the break bit
produces the appropriate high on the TTL DATA OUT lines. The 7400 gates E45, E46, E75, E76 are normally
kept qualified by the high state of the Q outputs from the 74175s that comprise the Break Control Register.

Setting of a bit in the Break Control Register brings the appropriate Q output to the low state, disabling the
7400 gate and placing a permanent high on the TTL DATA OUT lines is such that a high = space =0 =
BREAK.
If the following message is received:

006244 RECEIVER NOT BLINDED

it indicates that the half-suplex logic did not function correctly.
While looping on the failing test, check the M7288 to make sure that the half-duplex bit for the failing line is

being set.
Check the M7289 to make sure that END OF CHARACTER is being received from the UART that serves the
failing line. If in doubt, swap the M7280 UART cards and see if the diagnostic now reports the error on line 11
instead of 1, 12 instead of 2, etc. (The diagnostic reports line numbers in octal).
Also check the M7289 ES8, E20, E32, E42 to make sure that the half-duplex enable and end of character
signals are disabling the E4, E16, E28, E39 gating appropriate to the line in error. END OF CHARACTER is

low while the UART is transmitting a character and comes high very briefly between characters. Loop on a
test of a working line if it is desired to see what it should look like.

Make all of the above examinations while looping on the failing test, unless otherwise instructed.

5-18

APPENDIX A

FLOATING DEVICE AND

VECTOR ADDRESSES FOR

COMMUNICATIONS DEVICES
A.1

INTRODUCTION

Starting with the DJ11, new communications devices are to be assigned floating addresses. The addresses for current
production devices are to be retained.

The word floating means that addresses are not assigned absolutely for the maximum number of each
communications device that can be used in a system.
A.2

DEVICE ADDRESS

Floating device addresses are assigned as follows:
1.

The floating address space starts at location 760010 and extends to location 764000 (octal
designations).

The devices are assigned in order by type: the DJ11 first, followed by the DH11, and then the next
device introduced into production. Multiple devices of the same type must be assigned contiguous
addresses.

The first address of a new type device must start on a modulo 10 boundary.

A gap of 10g, starting on a modulo 10g boundary, must be left between the last address of one type
device and the first address of the next type device. A gap must be left for any device on the list that is
not used, if the device following it is used.

No new type device can be inserted ahead of a device on the list.

If additional devices on the list are to be added to a system, they must be assigned contiguously after the
original devices of the same type. Reassignment of other type devices already in the system may be
required to make room for the additions.

The starting address of the DH11 must be on a modulo 203 boundary because the DH11 has eight
registers.

The following examples show typical floating device address assignments for communication devices in a system.

A-1

Example 1:

No DJ11 but two DH11s

760010

Cannot be used for DH11

760020
760022
760024

DH11 #0 first address
DH11 #0
DH11 #0

760026

760030

760032
760034

760036

DH11 #0

DHI1 #0

DH11 #0

starting address

DH11 requires

ecight addresses

DH11 #0

DH11 #0 last address

760040

DH11 #1 first address

760042

DH11 #1

760044

DH11 #1

760046

DHI11 #1

760050

DH11 #1

760052

DHI11 #1

760054

DH11 #1

760056

DHI11 #1 last address

760060

DH11 Gap (Indicates that there are no more DH11s)

Example 2:

One DJ11, one DH11 and two XX11s (future device with two registers)

760010
760012

DJ11 #0 first address
DJi1 #0

DJ11 requires

760014

DJ11 #0

four addresses

760016

DJ11 #0 last address

760020

DJ11 gap

760030

Cannot be used for DH11 because it is not a modulo 203 boundary.

760040
760042
760044
760046

DH11 #0 first address
DH11 #0
DH11 #0
DH11 #0

760050

DH11 #0

760052

DH11 #0

760054

DHI11 #0

760056

DH11 #0 last address

760060

DH gap

760070

XX11 # first address

XX11 requires

760072

XX11 #0 last address

two addresses

760100

XX11 #1 first address

760102

XX11 #1 last address

760110

XX11 gap

A.3

VECTOR ADDRESSES

The floating vector addresses are assigned starting at 300 and proceed upward. The addresses are assigned to devices
in the following order: DC11; KL11/DL11-A,B; DP11; DM11-A; DN11; DM11-BB; DR11-A; DR11-C; PA611
Readers; PA611 Punches; DT11;DX11;DL11-C,D,E; DJ11; DH11.
New devices are added as they are introduced into production.

APPENDIX B

PDP-1 MEMORY ORGANIZATION
)

AND ADDRESSING CONVENTIONS

The PDP-11 memory is organized in 16-bit words consisting of two 8-bit bytes. Each byte is addressable and has its
own address location: low bytes are even numbered and high bytes are odd numbered. Words are addressed at even
numbered locations only and the high (odd) byte of the word is automatically included to provide a 16-bit word.
Consecutive words are therefore found in even numbered addresses. A byte operation addresses an odd or even
location to select an 8-bit byte.

The Unibus address word contains 18 bits identified as A(17:00). Eighteen bits provide the capability of addressing
256K memory locations, each of which is an 8-bit byte. This also represents 128K 16-bit words. In this discussion,
the multiplier K equals 1024 so that 256K represents 262,144 locations and 238K represents 131,072 locations.
This maximum memory size can be used only by a PDP-11 processor with a memory management unit that utilizes
all 18 address bits. Without this unit, the processor provides 16 address bits which limits the maximum memory size
to 64K (65,536) bytes or 32K (32,768) words.

Figure B-1 shows the organization for the maximum memory size of 256K bytes. In the binary system, 18 bits can
specify 2'3 or 262,144 (256K) locations. The octal numbering system is used to designate the address. This provides
convenience in converting the address to the binary system that the processor uses as shown below.

{16

115

{14

{13

{12

{11

|10

|09

|08

|07

{06

[O5

|04

{03 | 02 | 01|

OO | AddressBit

0 | Binary

Octal

Address Word Format

The highest 8K address locations (760000—777777) are reserved for internal general registers and peripheral devices.
There is no physical memory for these addresses; only the numbers are reserved. As a result, programmable memory
locations cannot be assigned in this area; therefore, the user has 248K bytes or 124K words to program.

A PDP-11 processor without the memory management unit provides 16 address bits that specify 2'® or 65,536

(64K) locaqtions (Figure B-2). The maximum memory size is 65,536 (64K) bytes or 32, 768 (32K) words. Logic in
the processor forces address bits A(17:16) to 1s if bits A(15:13) are all 1s when the processor is master to allow
generation of addresses in the reserved area with only 16-bit control.

B-1

l15

08|07

le— 16 BIT DATA WORD —s»
HIGH BYTE

LOW BYTE

000001

000000

000003

000002

USER ADDRESS SPACE

AVAILABLE USING 18
ADDRESS BITS ON

/’—_\J

PDP-11 PROCESSOR
WITHOUT MEMORY

MANAGEMENT OPTION,
INCLUDES 248K (253,952)
BYTES OR 124K (126,976)

WORDS.
757777

757776

760001

760000

r—_fig

J
"

HIGHEST 8K (8192)

BYTES OR

4K (4096)

WORDS RESERVED FOR
DEVICE REGISTER
ADDRESSES.

*777777

777776

4LAST ADDRESS IS BYTE NUMBER 262,14310
MAXIMUM SIZE WITH 18 ADDRESS BITS IS

256K(262,144) BYTES OR 128K (131,072) WORDS.
1-1690

Figure B-1

Memory Organization for Maximum Size Using 18 Address Bits

08107

[+— 16 BIT DATA

HIGH BYTE

00
WORD ——»

LOW BYTE

000001

000000

000003

000002

USER ADDRESS SPACE

AVAILABLE USING 16
ADDRESS BITS ON

PDP-11

PROCESSOR

WITHOUT MEMORY
MANAGEMENT OPTION.

INCLUDES 56K (57,344)
BYTES OR 28K (28,672)
WORDS.

157777

157776

160001

160000

ADDRESSES 160000177777 ARE CONVERTED
TO 760000 -~777777 BY

THE PROCESSOR. THUS,

THEY BECOME THE

HIGHEST 8K (8192) BYTES

OR 4K(4096) WORDS

*177777

RESERVED FOR DEVICE
REGISTER ADDRESSES.
177776

LAST ADDRESS IS BYTE NUMBER 65.53510
MAXIMUM SIZE WITH 16 ADDRESS BITS IS

64K (65,536) BYTES OR 32K(32,768) WORDS.
ft-1689%

Figure B-2

Memory Organization for Maximum Size Using 16 Address Bits

B-2

Bit 13 becomes a 1 first at octal 160000 which is decimal 57,344 (56K). This is the beginning of the last 8K bytes of
the 64K byte memory. The processor converts locations 160000—177777 to 760000—777777 which relocates these
last 8K bytes (4K words) to the highest locations accessible by the bus. These are the locations that are reserved for
internal general register and peripheral device addresses; therefore, the user has 57,344 (56K) bytes or 28,672 (28K)
words to program.

Memory capacities of 56K bytes (28K words) or under do not have the problem of interference with the reserved
area, because designations less than 160000 do not have a binary 1 in bit A13. No addresses are converted and there
is no possiblity of physical memory locations interferring with the reserved space.

PDP-11 core memories are available in 4K or 8K increments. The highest location of various size core memories are
shown below.

Highest Location

Memory Size

K-Words

K-Bytes

(Octal)

4
8
12
16
20
24
28

8
16
24
32
40
48
56

017777
037777
057777
077777
117777
137777
157777

B-3

APPENDIX C

INTEGRATED CIRCUIT DESCRIPTIONS

C.1

INTRODUCTION

The MSI and LSI integrated circuits shown in the engineering drawings are discussed in the following paragraphs.

The descriptions include a pin/signal designation diagram, simplified logic diagram, and truth table. These
descriptions are intended as maintenance aids for troubleshooting to the IC level. Table C-1 lists the ICs by part
number, name, and paragraph number.
Table C-1
Integrated Circuits

Manufacturer

Name

Paragraph

Part Number

1488

Quad EIA Line Driver

C.2

1489

Quad EIA Line Receiver

C.3

3341

4-bit X 64 FIFO Buffer

4007

Dual-1 of 4 Line Decoder

C.s5

4015

Quad D-type Flip-flop

C.6

8266

2-input, 1 of 4 Line Multiplexer

C.7

8271

4-bit Shift Register

C.8

8640

Quad 2 Input NOR, Unibus Receiver

C.9

8838
8881
7442

Quad Bus Transceiver
Quad 2 Input NAND with Open Collectors
4 to 10 Line Decoder

C.10
C.11
C.12

7474/74H74

Dual D-type Flip-flop

C.13

7481
7485

16-bit Active Element Memories
4-bit Magnitude Comparator

C.14
C.15

7489
7490
7492

64-bit Read/Write Memory
Decade Counter
Divide by 2 and by 6 Counter

C.16
C.17
C.18

7493
74121
74123
74151
74154
74155
74157
74161
74174/74175
74193
74197

4-bit Binary Counter
Monostable Multivibrator
Monostable Multivibrator
8 to 1 Line Multiplexer
4 to 16 Line Decoder
Dual 2 to 4 Line Decoder
Quad 2 to 1 Line Multiplexer
Synchronous 4-bit Counter
Hex/Quad D-type Flip-flops
Syncrhonous Up/down 4-bit Counter
50 MHz Binary Counter/Latches

C.19
C.20
C.21
C.22
C.23
C.24
C.25
C.26
C.27
C.28
C.29

C-1

1488 QUAD LINE DRIVER

12 O—

O—

11
13

0—

40—

{TOP VIEW)

50—

11-0486

—07

—
—

V+ -

—
014

V- -

-0

O—
11-0459

vVt 140—

282K
<

INPUT 4 O—j¢—¢

*
62K

50—jg—4

j" |

INPUT

370

Y
b

300

GND
GND
70‘1

3.6K

AMA—0
6 QUTPUT

C.2

‘)

310K

f
V-

10—

$7¢

$70

NOTE'
1/4

circuit shown.
11- 0760

C-2

C.3

1489 QUAD LINE RECEIVERS

1::?—0 3 130

40—

(TOP VIEW)

l'I—I—I—I—rl“rl
1

_I_

10 ?:P—O 8

O 14

Vi -

()__J

11-0486

11-0460

14 V¥
9K

25K

2K
3 OUTPUT

RESPONSE

CONTROL

‘
v

INPUT 1 0—AAA
4K

iOK
.

o 7

GROUND

NOTE:
1/4

of circuit shown.
11-07614

7400 QUAD 2-INPUT POSITIVE NAND GATE

Vee

-4B

NOTE:

Component values are typical.
11-0461

POSITIVE

LOGIC: Y=AB
11-0762

C-3

C.4

3341 4-BIT X 64-WORD PROPAGABLE REGISTER (FI/FO)

The 3341 is a 64-word X 4-bit memory that operates in a first in/first out (FI/FO) mode. Inputs
and outputs are
completely independent (no common clocks). The device is used in the DH11 as an asynchronous buffer referred
to
as the FIFO or silo. When both INPUT READY and SHIFT IN are high, the four bits on DO through D3 are
loaded

into the first bit position where they stay until INPUT READY and SHIFT IN go low. This causes the
bits to
propagate to the second bit position (if empty) where they are propagated to the bottom of the silo by
internal
control signals.
'
When data has been transferred to the bottom of the memory, OUTPUT READY goes high indicating the presence

of valid data. When both QOUTPUT READY and SHIFT OUT are high, data is shifted out of the silo. This causes
OUTPUT READY to go low. Data is maintained until both OUTPUT READY and SHIFT OUT are low. At this time
the bits in the adjacent upstream cell are transferred into the last cell causing OUTPUT READY to go high

the silo has been emptied, OUTPUT READY will stay low.

LOGIC

BLOCK DIAGRAM

Do —

D -—fls
|;LFUOT
!
D2 —GD STAGE
03

—pT

LOGIC

CONTROL LOGIC

]

SHIFT IN —»]

MASTER

) 15
TL f— UTeUT meADY
COOL:\IT:I'PRUO
ONTRO
14
et our

MAIN REGISTER

VSS=P|N 16
Vpp=PIN

12 a
> 4y
STAGE 1 Qs

MAIN REGISTER

: céfi?k’&

OS’:’E’ST

64 WORD x 4B!T

INPUT READY <—

9
RESET

VgGg=PIN

'
PIN

CONFIGURATION

LOGIC SYMBOL

o —|INPUT

(TOP

SHIFT

READY

ouT

3 — sHiFTiIn

OUTPUTL
READY

Vee

INPUT READY [ 2

SHIFT IN[] 3

3341

VIEW)

16 [] Vss
15 ] SHIFT ouT
14 [] OUTPUT READY

0o [ 4

137 o

a4 — b,

Qo — 13

121

5 —{ D,

Q b—12

—

7 —] D3

—

0z []7

10[7] @3

Voo [ &

o[ ] —
TMR

Q3 f— 10
MASTER RESET

T9
VSS =PIN 16 +5V

VDD= PIN 8 GND
VGG=PIN

{

again. If

—12V

11-1851

C.5 4007 DUAL-BINARY-TO-ONE-OF-FOUR LINE DECODER

ENABLE

4 (12) Q0

—

D—:i H

b—<>3 (13) Q1

[

I_n\—q? {14) Q2
L

D—u (15) Q3

1/2 of device shown

11-0742

TRUTH TABLE

E=0

1 = High State
0 = Low State

LOW-LEVEL GATE

0 Vee

.d
aK

T Applies only to
input gate

HIGH-LEVEL

el fesl fral frs] [fie] [vi] [ro] [5]

GATE

OVee

]

X {10}
&

11-0743

11-0744

4015 QUAD TYPE D FLIP-FLOP

LOW

LEVEL GATE

—O0 V¢e
4K

4K
——O
:

inputs

RESET

3
HIGH

—

3 Diodes onty on

CLOCK

LEVEL

connected

external

points

GATE

SET

% Diode only on
nput
fo

connected

external

point

tTtar

C.6

t1.g7al

TRUTH TABLE

174

CLOCK

AND RESET
18

GND=PIN

COMMON TO ALL FOUR

Qn-1

Q.1 = time period prior to clock

OF DEVICE SHOWN

Vee=PIN

pulse

FLIP-FLOPS

Q,
11-0739

pulse

= time period following clock

C.7

8266 2-INPUT 4-BIT MULTIPLEXER

The 8266is a 2-input 4-bit digital multiplexer that has the capability of choosing between two dlfferent 4-bit input
sources as controlled by one selection input while the other input is held to O.
TRUTH TABLE

Output

——

]

I
I

I
I
I
I

I
I

I
I
I
I
I

1
|
l

I
I
I

|
I

f, (0,1,2,3)

I
L
— —

I
|
I
.

Select Lines

t11-0479

12°'11

Vcc A3 33 Fa Fp B2 A so

Ap Bp Fo Fy By Ay Sy gnp
1

8
11-0485

C-7

)

JALSIODAY LAIHS LId-¥ [LC8 8D

CLOCK@

——Q o

t.oAD

i12-0327

82718

TRUTH TABLE

Shift

Hold

Parallel Entry

Shift Right

()

Load

Shift Right

—

Control State

Vee

109

D¢

Agyr CLOCK

Boyr

GND

SHIFT Doyt Doyt LOAD Cout

12-0322

C.9 QUAD 2 INPUT NOR, 8640
Is used as a Unibus receiver.
4

GND =Pin 1
IC-0144

C.10

8838 QUAD BUS TRANSCEIVER

The 8838 consists of four identical receiver/driver combinations in one package for use on the PDP-11 Unibus. Data
from the equipment on DATA IN 1, e.g., appearing on pin 2 will be driven out of pin 1 (BUS 1) to the Unibus (if
enabled). A BUS 1 signal received from the Unibus on pin 1 will be fed out of pin 3 (DATA OUT 1) to the
equipment,

Signal/Pin Designations
Signal Name

- BUS

Circuit
1

DATA IN

DATA OUT

ENABLE

GROUND

BUS 1 —

vVee

DATA IN1 —2
DATA OUT 1 ——
BUs 2

DATA IN 2 =
5

DATA OUT 2 —]
7

BUS 4
DATA IN 4

135
—

//—i—_l BUS1

pataouT 4
BUS 3

DATAIN 3

ENABLE A 7

DATA OUT 3

GROUND —

ENABLE B

- = -~

ENABLE A—T

ENABLE B

DATAINI—2

>°_

DATA QUT|

ONE OF FOUR
1866

8838 Quad Bus Transceiver

C.11

8881 QUAD 2 INPUT NAND GATES

Vee

1.2K

+
:
1
:

|
| ®
e

v
|

|
i
|

4
NOTE:
1/4 of unit shown. Component values are typical.

*|SOLATION DIODE
11-0480

A, F

PACKAGE

*No pull-up provided

1-0758

C-10

C.12 7442 4LINE to 10-LINE DECODER

In the DH11, the 7442 is used as a 3-wire binary to octal decoder. Input D is used as a strobe and when it is low,

INPUT B%

37539
o

INPUT C m——Do

INPUT

Vec=PIN 16

GND:=PIN 8

—

(2)

YWYy I

(14)

OUTPUT O

1
OUTPUT

(3)

OUTPUT 2

OUTPUT 3

OUTPUT 4

O.OUTPUT 5

(7)

OUTPUT

TV¥

—e

INPUT AO—DC

o loilmilz (o [ol|lol|Pilolo |o |2 oo |jo |2 oo (o]
2 jol|o|@s) {o)|olo 3 [oljol]o
i |ojoljm P [ooljol|
2|

data is taken from outputs 0—7.

OUTPUT 7

(10)

OUTPUT 8

010 suTPUT
14-0734

TRUTH TABLES

Octal Output

BCD Input

0
0
0
0
0
0
0
0
1

0
0
0
0
|1
1
1
1
X

0
0
1
1
0
0
1
1
X

0
1
0
1
0
1
0
1
X

0
1
1
1
1
1
1
1
1

1
0
1
1
1
1
1
1
1

1
1
0
1
1
1
1
1
1

1
I
1
0
1
1
1
1
1

i
1
1
1
0
1
1
1
1

1
1
1
1
1
0
1
1
1

1
1
1
1
1
1
0
1
1

1
1
1
1
1
1
1
0
1

X = Irrelevant

C-11

INPUTS

OUTPUTS

Voo

16|

[15]

[1a]

[13]

[12]

[

l—\

)

GND

OUTPUTS
11-0733

C.13

7474/74H74 DUAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

The 7474/74H74 D-type flip-flops are triggered by the positive edge of the clock pulse. They feature direct-clear
direct-preset inputs and complementary outputs.

Vee

CLEAR

CLOCK

PRESET

—]0

CLEAR

CLOCK

L PRESET

JcLock

l‘ PRESET _]

CLEAR

Q@
Q

1
CLEAR

1
CLOCK

1
PRESET

GND

POSITIVE

LOGIC:

LOW

INPUT TO PRESET

LOW

INPUT TO CLEAR

PRESET

AND CLEAR

SETS
SETS

Q TO

LOGICAL 1

Q TO LOGICAL O

ARE INDEPENDENT OF CLOCK
11-0766

Truth Table (Each Flip-Flop)

tn+1

Input

Output

Notes:

1.t , = bit time before clock pulse.

2. t . = Dbit time after clock pulse.

C-12

and

7481 16-BIT ACTIVE-ELEMENT MEMORIES

SENSE-O LINE

_ TO O OUTPUT OF
-

15 FLIP-FLOPS

VWA

*
AAA.

)

{?L
x

ADDRESS

EIGHT SHOWN)
GND

— A

Y
Wo WRITE AMPLIFIER

AMPLIFIERS

izl

AMPLIFIER IS SAME)

(Sq1

(5
TO

Yo
Sp SENSE AMPLIFIER

WRITE 1

AND SENSE 1

—

Y
MEMORY FLIP-FLOP

AMPLIFIER IS SAME)

REMAINING

(15 FLIP-FLOPS

(ONE OF 18 SHOWN)
11-0729

WRITE
1
A

SENSE
1

SENSE
0

(Wq

;

(Tluzugg

i:>

WRITE INPUTS

+—o Ve

SENSE

0 ouTpuT

C.14

X4
Y1

Yaq
11-0731i

WRITE

SENSE

WRITE

x, W1

So Woy, |-

[1%3 X2

L_|
|

Y273

Vee

|
Y4

POSITIVE LOGIC: SEE LOGIC DIAGRAM
11-0730

C-13

C.15

7485 4-BIT MAGNITUDE COMPARATOR

The 7485 performs magnitude comparison of straight binary or straight BCD codes. Three
fully decoded
decisions (A>B, A<B, A = B), about two 4-bit words (A,B), are made and are externally available
at three

outputs.

DATA INPUTS
A

Vec

f15|

[1a]

Ji3]

|12]

[11]

li0]

A<B
IN

A=B
IN

A>B
IN

A>B
OuT

A:=B
OuT

A<B
OouT

B3
A<B
A=B
A>B
A>B
A:=B
A<B
DATA —
N
v
,
INPUT
CASCADING
OUTPUTS
INPUTS

GND

11-2202

TRUTH TABLE

COMPARING

CASCADING

INPUTS

NOTE:

INPUTS

]

OUTPUTS

A3, B3

A2, B2

A1, B1

A0, BO

A>B

A<B

A3 > B3

A=B

A>B

A<B

A3 < B3

A3=8B3

A2>B2

A3=8B3

A2<B2

A3=8B3

A2=B2

| A1>8B1

A3=B3

| A2=B2

| A1< BT

A3=B3

A2=B2

A1=B1

| AD.BO

A3=B3

A2=B2

| A1=B1

| A0<BO

A3-83

A2-B2

| A1=B1

A3=B3

A2=B2

| A1=B1

A3=B3

A2-B2

| A1=B1 | A0=BO

A=B

A0-=BO

| A0=8B0

looL

]

H = high level, L = low level, X = irrelevant

C-14

(15)
B3

(1)

=
(5)

%{} T

(13)
-

A>S

t14)

LA<B1IN

LA<B1 IN

(3)

Al
B1

(12)
(11)

4)
LA<B1 IN o

(7)

(10)
(9) -

BO o

1-1854

Pin (16)=V¢c, Pin (8)=GND

C-15

A<B

C.16

7489 64-BIT READ/WRITE MEMORY

The 7489 is a TTL array of 64 flip-flop memory cells organized as 16 words of 4 bits each Each wo is addressed in
straight binary code with full decoding on the chip. Read out is nondestructive.

Function Table
ME

Operation

Condition of Outputs

Write

Read

Complement of Data Inputs
Complement of Selected Word

Inhibit Storage

Complement of Data Inputs

Do Nothing

High

DATA

SENSE

DATA

SENSE

SELECT INPUTS

Vee

| NPUT OUTPUT INPUT OUTPUT

s3 —]
ME

SELECT

MEM WRITE

DATA

SENSE

DATA

SENSE

GND

ENABLES

INPUT “——————"" INPUT OUTPUT INPUT OUTPUT

1-1117

C-16

C.17

7490 DECADE COUNTER

The 7490 is a decade counter internally interconnected to provide a divide by 2 counter and a divide by 5 counter.

In the DH11, the 7490 is used in this way. Input A (pin 14) is the clock for the divide by 2 counter. The output is A
(pin 12). Input BD (pin 01) is the clock for the divide by 5 counter. The outputs are B, C, and D. All four reset
inputs (pins 02, 03, 06 and 07) are connected to ground to inhibit the preset function.

DUAL-IN-LINE PACKAGE (TOP VIEW) -

{13

|1l

lo]l]s

]

—olcP

[

cH—

LR
—o|cP

O
X

o—]

Yo [=]]

aAH

]

IW_fz'

GND

o
»

A
INPUT Ro(1)

Ro2)

Raqn)

Reqa)

11-1855

C-17

C.18

7492 DIVIDE BY 2 AND DIVIDE BY 6 COUNTER

The 7492 is internally interconnected to provide a divide by 2 counter and a divide by 5 counter. Output A (pin 12)
provides a divide by 2 count using input A (pin 14) as the clock. Using input BD (pin 01) as the clock, divide by 3
and divide by 6 counts are available at outputs C and D respectively. The Clear inputs (pins 06 and 07) are
connected to ground to inhibit the clear function.

DUAL-IN-LINE PACKAGE (TOP VIEW)

GND

j3]

J2l

o]l

v A v sp{i ¢ J Dj
cP

—oICP

- cp

"-18566

C-18

C.19

7493 4-BIT BINARY COUNTER

The 7493 is internally interconnected to provide a divide by 2 counter and a divide by 8 counter. Qutput A (pin 12)

provides a divide by 2 count using input A (pin 14) as the clock. Using input B (pin 01) as the clock, divide by 2, 4,
and 8 counts are available at outputs B, C, and D, respectively.

The 7493 can be used as a 4-bit ripple-through counter by externally connecting output A to input B and using
input A as the clock. Divide by 2, 4, 8, and 16 counts are available at outputs A, B, C, and D, respectively. Both
configurations are used in the DH11 and in both cases the clear inputs (pins 02 and 03) are connected to ground to
inhibit the clear function. The truth table is shown for the 4-bit ripple-through configuration.

Truth Table (4-Bit Ripple-Through)
Count
.

DUAL-IN-LINE PACKAGE (TOP VIEW)

Output

;

INZUT NG
14

7
8

0
1

]
0

1
0

14
s

-olcp

Lolcp

Lalcp

]

GND

INPUT
R Ro) R Ror2)
2T

7
|

V cc

11-1857

C-19

C.20

74121 MONOSTABLE MULTIVIBRATOR

The 74121 is triggered by positive or gated negative-going inputs. The duration of the complementary outputs is
determined by external timing components connected to pins 9, 10, and 11.

TRUTH TABLE
ty INPUT

[tn,q

INPUT

ouTPUT

SHHANRE:

A1la2]| B

|a1|a2]

o|x|1lolx|o]|

INHIBIT

x|o[1|xlo|lo]

inHiBIT

TIMING PINS

Vce

o|x|{o]o|x|1]|ONE SHOT

e TH e
NC

H
_J

x{o|o]|x|o|1t]|oONE SHOT

t11]1|x]0o]|1]|ONE SHOT

x{olo|x|1]|o| inHiBIT

t{1]/1]0]|x]|1]|ONE SHOT

o|lx|ol1|x|o|

iNnmiBIT

x|ol1l1[1]1]

olx|1

4|4

WriBIT

1{1]lolx{o|o|

INnHIBIT

1l1]lolo|x|o]|

iNnHIBIT

1*Vin (1) =2V

0= Viq (0) € 0.8V

GND

1. tnh = Time before input transition.

2. th+1=Time after transition.

3. X indicates that either a logical O or 1 may be present.
11- 1119

C-20

C.21 74123 RETRIGGERABLE MONOSTABLE MULTIVIBRATOR WITH CLEAR
The 74123 Multivibrator provides dc triggering from gated low level active (A) and high level active (B) inputs. It
also provides overriding direct clear inputs and complementary outputs. The retriggering capability simplifies
generation of extremely long duration output pulses. If the input is triggered before the output pulse is terminated,
the output pulse is extended. An overriding clear feature allows any output pulse to be terminated at a
predetermined time, independent of timing components.

‘

JORN DUAL-IN-LINE OR

W FLAT PACKAGE (TOP VIEW)

1Rext

Vec
4

Cext

|15

|1l

1@
1

Cext

TRUTH TABLE

INPUTS | OUTPUTS

B|Q

X|L

L|L

$i 0L

H|IL

{n]|o

] L

) .Q

‘

CLEAR

]

2
CeXf

2R ext

GND

ext

positive logic

Low input 10 clear resets Q to low

level and inhibits dotoinputs

11-1864

74123 Retriggerable Monostable Multivibrator With Clear

C-21

olololojolololololo|clolololole|~

| e

When used to indicate an input, x = irrelevant.

C-22

)

Dg
Dg
Dg
D;
A
B

ol—jol—=|lo|=~|lo|=lo|=|o|=|lo|=|c|—-]|—

13!

—lo|=le[=|o|=|e|={leo|=|e
|- |o|=|o|°

~oxxxxx¥x><><><><><><><><

L R L N L

L R R A L

Yee

SELECT

DATA

Toe [oe {3 | 3¢ {3 |

[

3¢

I T

J OR N DUAL-IN-LINE
W FLAT PACKAGE (TOP

doe [oe

Dy | Dy

B S

ol el - R

DATA INPUTS

| 5=

| | |

EVE [FVN EVN FVR PV

INPUT

|| [ |oe

—

e | | —

[e=]

[oe

[

oe [oe |

Poe | oe |

—_

[

e [

oo [ oe | oe | e

|¢

DATA

[

foe oe | oe | 5¢ {oe

| oo [oe [oe [ e [ ¢

e | e Loe [oe [ oe [

Poe [ oe |5

—|—lo|lo|~|—~|olo|=]|~|lo|lo|=|~o|lo]|x

ABCD7)

=]l —lOlOojO|O|—|—~|—~|—|jCjo]|o|O]|x

— ||

]

===

=== ]|olololo|olc|o|
o] =

Strobe

C.22
74151 8-LINE TO 1-LINE MULTIPLEXER

The 74151 selects one of eight data sources for multiplexing the output onto one line. The multiplexer is enabled

when the strobe input is low.

VIEW)

GND

e
__
_ _POSITIVE LOGIC
_
_
Y=S(ABCD(+ABCD1+ABCD2+ABCD3+ABCD4+ABCDs+
ABCDg

ouTpuTs STROBE

W=Y

it-0634

TRUTH TABLE

Inputs
Outputs

STROBE (7)

(ENABLE)

YL
TYY

(DO 0(4)

(3)

Dy
©

(2)

{1)

DATA

INPUTS j

(14)

(13)

Dg o

]

{(15)

Dq O

CL‘IZ)

SELECT <

(BINARY)

(10)

B o——
(9)

[0
.

(6) OUTPUT W

Vee =PIN 16

GND=PIN 8

DATA

(11)

v|v|vl

Y Y Y

5
(5)
OUTPUT Y

11-0635

C-23

Ws9SHHHHHLHHHHHH

XT0OST4TCX|TTO¢lISTiOAsTlDOSrBIIST(RrONITISNSIdooSTlmdeSIIeSTdITmdTIorTXTiIXIS«AT(rU2IOITIWdromlIdIA[odIRTm(dR|SNO]TI~=l
TI»eTslTnileIIwilfITTslieTolileTsSlDolIieoliItTeTwilleToficTolTB«QRISIoolileIs«IeIwieIIoliteIe|wN-|I+
oI»rTwelslelZsloir«lTAcoilfilleTBxmicolZINoE<loTs=i«lBoABl¥NiI<leoSoTfsilcossZfi«leTsoloilflcXIsofoillZecwoofiT«lecosolifilifeceoaTlfiitlec«rIonffiifficc«ooffviifleTcrofoiIlfceoeliTl«eSeBejaMovhdlLl

oOrOIXM-TTx7TOXIDR-raO-TTHXzLORxTHBIXRTSUrNSSaSIL3BRUTIErH9BRRTETHL-SUxI3rSRNTxBHLTRrBL(ZTa(SR2HHSSTR~AHSIUATHaUDRzAHITTBRHHTSN9IIRBSTTeHHZ[IeI<iHX[|l2TSm5NXH
C.23
74154 4-LINE TO 16-LINE DECODER DEMULTIPLEXER

In the DHI11 the 74154 is used to decode 4 binary coded inputs into 1 of 16 mutually exclusive outputs when both

strobe inputs (G1 and G2) are low.

DUAL-IN-LINE PACKAGE

Vee

H= high,

L = low, X
2322

T
IEEHHHHEEH
E
Y

irrelevant

C-24

(TOP VIEW)

INPUTS
A

OUTPUTS
Al

212019
18
1716
1514

G2
G1
15
13

;

ouTPUTS

GND

i-0636

TRUTH TABLE

C.24

74155 DUAL 2-LINE TO 4-LINE DECODER

The 74155 consists of two 1-line to 4-line demultiplexers with individual strobes and common binary address inputs.
It has several applications, and in the DHI11 it is connected as a 3-line to 8-line decoder. The two strobe inputs are connected together and the third select input (Select C) is obtained by connecting the two data inputs together.

DATA

sTrRoge

SELECT

Ve¢

2¢

is|

ial

OUTPUTS
2Y2

2Yi

2Y0

12|

|11

2Y3

2Y2

2Yi

2Y0

i3]

)}

2G 2C

]

BBAA

BBAA
16

DATA STROBE SELEC
1C

2Y3

1Y2

INPU

1Yt

1Yo

1Y1

1YO

—

GND

OUTPUTS
11-2200

3-Line To 8-Line Decoder

Inputs

Select

Outputs

Strobe | (0)

(1)

(2)

(3)

(6)

(7)

2Y1

2Y2

2Y3

1Y0

1Y1

1Y2

1Y3

or Data

G**

2Y0

H
H

* Inputs 1C and 2C connected together
** Inputs 1G and 2G connected together

C-25

2Y0

2v1

2v2

2v3

1Y0

1v2

1Y3

2¢

ENABLE/DATA

ADDRESS SELECT

ENABLE

1C
/DATA

L OUTPUT

STROBE 16 o——————f\

DATA 1C o—-Do—q

1Y0
OUTPUT

OUTPUT

SELECT Bo——{>o——4>-—<{>

1Y2

OUTPUT
1Y3

800

]

OUTPUT
2Y0

SELECT A o—->0—4>—4>

OUTPUT
Y1

OUTPUT
2yY2

DATA 2C o————-———ch

STROBE 26 o———q

OUTPUT
2Y3

11-1866

C.25

74157 QUAD 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER

INPUTS
——A

OUTPUT

Vcc STROBE 4A

INPUTS
——A

SELECT

3Y
9

OUTPUT

]

GND

“'—W_'—J;—‘(————J

INPUTS

QUTPUT

INPUTS

OUTPUT
t1-2203

TRUTH TABLE

INPUTS

OUTPUT Y|OUTPUT W

ENABLE | SELECT|

A B

74157 | 745158

X X

L X

H X

X L

X H

H=High level, L=Low level,X=Irrelevant

74157

LOGIC

DIAGRAM

1A 0(2)

(4)

L
18 O (3)

o—

oA O (5)

{7)

(9)

2B Or( )
6

2a OlI1)
*

38 C‘fi“O)
o

(14}

aA O

4B O

*—

(13)

(12)

o—

SELECT

ENABLE 002

»—Do—
Pin 16 =V, Pin 8 = GND

—b

1H-131

C-27

C.26

74161 SYNCHRONOUS 4-BIT COUNTER

In the DHI11, the 74161 counters are used to provide a divide by 11 function and a divide
by 7 function. These
functions are obtained by presetting the data inputs. The carry output (pin 15) is fed back to the load input (pin
09)
to preset the counter on the count of 15. In both configurations, the clear input and both count enable
inputs

~ (Enable T and Enable P) are connected to +3 V. This keeps the counter enabled and disables the clear function.

OUTPUTS

CARRY

Q¢

ENABLE

LOAD

|13

121

GENA

Vee outpur

ia|

CARRY

OUTPUT

ENABLE

CLEAR

CLOCK

CLEAR CLOCK

LOAD
ENABLE
D
P

ENABLE

GND

A
a

DATA INPUTS
11-2201

]

CLEAR

{3
o

(mw
Qu

’ CLOCK

DATA

113t

008

1
{4

’ CcLOCK

DATA

[

1124

INPUTS
€

{5}

DATA

{2)

P OUTPUTS

CLOCK

—

CLOCK
4

(1)

EN:BLE

DATA

: |

fl_‘x

cHO‘
ENABLE

__l:'_\

| —Y—

h.J

C 28

(15

-0

RIPPLE

CARRY

C.27 74174 HEX/74175 QUAD D-TYPE FLIP-FLOPS WITH CLEAR

The 74174 contains six flip-flops with single-rail outputs (Q only). The 74175 contains four flip-flops with
double-rail outputs (complementary Q and Q). Both devices have common clock and clear inputs.

TRUTH TABLE
INPUT

ACE——Da Qa0

|OUTPUTS

H
L

L
H

tn = Bit time before

clock pulse.

TRUTH TABLE

INPUT | OUTPUTS

—____olcLock

CLEAR

H
L

L
H

B c(f)

tn"‘1

tn =Bit time before
clock pulse.

Qg -—(E)OQB

tnt1=Bit time after
clock pulse.

tnh+1=Bit time after

clock pulse.

CLOCK

CLEAR

|
6
c &8

(4)
o—————
Dp

Qo ac

———OCLK Qpf—>

—QJICLOCK

CLEAR

‘7
(11

(10}

Qpf—>Qp

(5)

7
(12)

LT
D

c>(13)

(15)

Qp[—20QFf
(9)

cLock ot

CLOCK o—

acLock

—

CLEAR

CLEAR @

L—j

(10)

Qcf—>

CLEAR

(14)

CLK Q¢ pb—o

QICLOCK

o—

Qgf—=

CLEAR

QCLK Qgl——o

—QJCLOCK

13
g &)

Qa—TM°

CLEAR

(1)

__\

Q>
~

—QICLK Q

CLEAR

Pin (16)=V¢c, Pin (81=GND

Pin (16)= V¢, Pin (8)= GND

in-in3

-tz

74175 Diagram

74174 Diagram

C-29

C.28

74193 SYNCHRONOUS 4-BIT UP/DOWN COUNTER (DUAL CLOCK WITH

The 74193 is incremented or decremented by a low to high level transition

other
is held high. The outputs can be preset by applying the desired

input low. A high on the clear input forces all outputs

cascaded.

at the appropriate clock input while the

information to the data inputs with the load

low. The borrow and carry outputs allow the counters to

OR N DUAL-IN-LINE PACKAGE (TOP VIEW)
INPUTS

INPUTS

OUTPUTS

DATA

CLEAR

——A——

BORROW CARRY

LOAD

DATA

CLEAR _ CARRY
BORROW
LOAD

DATA
B

INPUT

QUTPUTS

CLEAR)

COUNT COUNT

DOWN

COUNT COUNT

bown

Q¢

GND

up 6 ©

INPUTS

QUTPUTS

LOGIC: LOW INPUT TO LOAD SETS Qa=A,QE=B,Q¢=C,AND Qp=D

ji-0640

C-30

Vee= PIN 16

GND:=PIN 8

(13)

) BORROW
OUTPUT

(2) 12)carry

OUTPUT

rag

DATA
INPUT A

V1o

PRESET

pown (4
°—| >0
COUNT

{3)

-0 OUTPUT Qp

up (9)

COUNT

CLEAR

pata !

‘

INPUT B

PRESET

(2)

—o OUTPUT Qg

-QT

CLEAR

37'
DATA J10)

‘

INPUT C

PRESET

()
-0 OUTPUT Q¢

Q¢

CLEAR

[

3"
(9)

INPUT D
CLEAR

(14)
.

PRESET

7)
:
0 OUTPUT Qp

CLEAR

LOAD

(1)

| >
11-o064|

C-31

C.29

74197 50MHz PRESETTABLE DECODE AND BINARY COUNTERS/LATCHES

J ORN DUAL-IN-LINE

W FLAT PACKAGE

(TOP VIEW)
*

DATA INPUTS
Vee

CLEAR

[

CLEAR

[

)

el 5]

[

COUNT/

CLOCK i

Q¢

[

LOAD

[51

COUNT/LOAD

CLOCK
1

b
Qq

—————

CLOCK 2

CLOCK

GND

DATA INPUTS

ASYNCRONOUS INPUT:

LOW INPUT TO CLEAR SETS Qp

QB.Qc

AND

Qp LOW.

*Pin assignments for these circuits are the same for all packages,
11-0482

74197 TRUTH TABLE

(See Note A)

Count

Output
o
o

NOTE A: Output Q4 connected to clock-2 input.

C-32

74197 50-MHz PRESETTABLE DECODE AND BINARY COUNTERS/LATCHES (Cont)

DATA

A 0—

COUNT/LOAD »—:3_\

=D,

CLEAR o—l——Dq
CLOCK 1 o

DATA B

QB
CLOCK 2

DATAC

-0 QB

O0——

PRESET

CLEAR

DATAD oO-

PRESET

QI—°
Qp

CLEAR

11-0481

C-33

APPENDIX D

F]C}

NIVER SA L ASYNCHRONOUS

Y
D.1

IVER T RANSMITTER (UART)
T

rTIrTITY
T S

INTRODUCTION

This appendix provides a functional description of the UART. It includes a table of UART signal functions and
simplified block diagrams and timing diagrams of the UART receiver and transmitter.
D.2 UART FUNCTIONAL DESCRIPTION

The UART is a MOS/L‘SI device packaged in a 40-pin DIP. It is a complete subsystem that transmits and receives
asynchronous data in duplex or half duplex operation. The receiver and transmitter can operate simultaneously. The
transmitter accepts parallel binary characters and converts them to a serial asynchronous output.

Thereceiver accepts serial asynchronous binary characters and converts them to a parallel output. The receiver and
transmitter clocks are separate and must be 16 times the desired Baud rate. The allowable clock rate is DC to
160 kHz.

Control bits are provided to select: character length of 5, 6, 7, or 8 bits, (excluding parity) mode, odd or even
parity, and one or two stop bits for 6, 7, or 8-bit characters. For 5-bit characters, 1 or 1-1 /2 start bits are used. The
format of a typical input/output serial word is shown in Figure D-1.

Both the receiver and transmitter have double character buffering so that at least one complete character is always
available. A register is also provided to store control information.

NEXT
CHARACTER

FIRST CHARACTER

MARK (1)

SPACE(0)

START DATA1 DATA2 DATA3 DATA4 DATAS DATA6 DATA7 DATA8 PARITY STOP1 STOP2 START DATA1
rL;BT--l-—T__I_—T-—:_-TIN;I-SB__——|
I

]

r-—'

I
11-2205

Figure D-1

Format of Typical Input/Output Serial Character

D-1

A block diagram and simplified timing diagram for the UART transmitter are shown in Figure D-2. The transmitter
data buffer (holding) register can be loaded with a character when the TBMT (Transmitter Buffer Empty) line goes

high. Loading is accomplished by generating a short negative pulse on the DS (Data Strobe) line. The positive-going
trailing edge of the DS pulse performs the load operation. The character is automatically transferred to the UART
transmitter Shift Register when this register becomes empty. The desired start, stop and parity bits are added to the

data and transmission begins. One sixteenth of a bit time before a complete character (included stop bits) has been

transmitted, the EOC (End of Character) line goes high and remains in this state until transmission of a new

‘character begins.

PARALLEL

DATA INPUT

(bB1-DB8)

DATA STROBE (DS)

TRANSMITTER BUFFER

EMPTY (TBMT)

START

ASYNCHRONOUS

sTop START

SERIAL OUTPUT (SO)

l I

END OF CHARACTER

(EOC)

DATA

I l i

NO.'STOP BITS—fiD

CONTROL

NO PARITY——

DATA

n
TRANSMITTER

EVEN PAR. SEL.—=2s»{

sToP

TIMING

DIAGRAM

HOLDING

BITS/CHAR, 2128,

CONTROL STROBE‘——T

PAR

TMTM cen [

BDO6 —<»]
BDOS——-D;

BITS

DECODER

0kl HOLDING
XMTR

BDO3——%

SERIAL

* QUTPUT

ouTPUT
LOGIC

33
BDO7 7"
—

DaTa </8004

END OF

» CHARACTER
(EOC)

SNIET

BDO2 —=—»
BDO1
—

8000 22+
DATA

STROBE

LOAD SHIFT

[

2> TRANSMITTER
» BUFFER
EMPTY

F/F

CLOCK

Tming

GENERATOR

INPUT =l

B
1t-2207

Figure D-2

UART Transmitter, Block Diagram and Simplified Timing Diagram

D-2

A block diagram and simplified timing diagram for the UART receiver are shown in Figure D-3. Serial asynchronous
data is sent to the SI (Serial Input) line. The UART searches for a high to low (mark to space) transition on the SI
line. If this transition is detected, the receiver looks for the center of the start bit as the first sampling point. If this
point is low (space), the signal is assumed to be a valid start bit and sampling continues at the center of the
subsequent data and stop bits. The character is assembled bit by bit in the receiver Shift Register in accordance with
the control signals that determine the number of data bits and stop bits and the type of parity, if selected. If parity
is selected and does not check, the PER (Receive Parity Error) line goes high. If the first stop bit is low, the FER .
(Framing Error) line goes high. After the stop bit is sampled, the receiver transfers in parallel the contents of the
receiver Shift Register into the receiver data buffer (holding) register. The receiver then sets the DA (Received Data
Available) line and transfers the state of the framing error and parity error to the Status Holding Register. When the

DH11 accepts the receiver output, it drives the RDA (Reset Data Available) line low which clears the DA line. If this
line is not reset before a new character is transferred to the receiver Holding Register, the OR (Overrun) line goes
high and is held there until the next character is loaded into the receiver Holding Register.
START

STOP

START .

sToP

[

]

(0)
WAILABLE

RESET DATA

AVAILABLE(RDA)

L
RECEIVER

TIMING DIAGRAM

1-2209

REC

REC DATA
AVAILABLE

OVERRUN

DATA BITS
N

ENABLE

BDOO

il
——»

FRAMING
ERROR

STATUS

14 WORD
ENB
16

AND GATES

REC
DATA

BDO7

PARITY
ERROR

EEEE RN
AND GATES

RESET

2l R
DATA—

AVAIABLE

OVERRUN

PARITY

FRAME
¢

)

DATA HOLDING REGISTER
[

SERIAL
DATA
INPUT

»q

cLock

INPUT

RECEIVER SHIFT REGISTER

CONTROL LOGIC

Tss

T35

EVEN
PARITY
SELECT

NO
PARITY

T37

DATA AVAILABLE

I:?ilr; ERRORO
Y

ING ERROR

Tss

NB2
NB1
NUMBER OF
BITS/CHARACTER

11-2208

Figure D-3 UART Receiver, Block Diagram and Simplified Timing Diagram
D-3

Figure D-4 is a pin/signal designation diagram for the UART. The function of each signal is given in Table D-1. In the

Function column, the references to high and low signals are with respect to the pins on the UART. This information

is used during servicing of the device. Programmers should refer to the DH11 register descriptions (Chapter 3) for

information concerning the function of these signals.

18
RESET DATA AVAILABLE »—0Q RDA
16
SATUS WORD ENABLE »—¢ SWE

19
DA — RECEIVE DATA AVAILABLE
16
OR ———— OVERRUN

RECEIVED DATA ENABLE —-»——0 RDE

FER ——— FRAMING

RECEIVER CLOCK - 17 RCP

PER

20
SERIAL INPUT »— Sl
33

( ——]

———

—>—

——

DATA BIT INPUTS‘

[
————
S

—

—_—d

DB8

RD8 |

oB7

RD7 |

DB6

RD6

DBS

RDS

DB4

RD4

DB3

RD3

DB2

RD2

DB1

RDt

DATA STROBE —»—Q
40
TRANSMITTER CLOCK —#———]

ERROR

13
. RECEIVE PARITY ERROR

TBMT

}RECEIVED DATA BITS

2+> SERIAL OUTPUT
L
» TRANSMITTER BUFFER EMPTY

24
EOC L~
» END OF CHARACTER

TCP

XR CS NB2NB1 NP PE2 SB

EXTERNAL RESET -o———’

37 38

Pintz=+5V

[—

Pin2=-{2V

NO. OF BITS PER CHAR\

PARITY

SELECT

39 |36

NOTE:

CONTROL STROBE »———

NO PARITY

Pin 3= GROUND
o

TWO STOP BITS —»
11~-2214

Figure D4

UART Signal/Pin Designations

D-4

Table D-1

UART Signal Functions

5-12

RD1-RD8

Function

Name

Pin No. | Mnemonic

Received Data

Eight data out lines that can be wire ORed. RD8 (pin 5) is

the MSB and RD1 (pin 12) is the LSB. When 5, 6, or 7 bit
character is selected, the most significant unused bits are
low. Character is right justified into the least significant
bits.

PER

Receive Parity

Goes high if the received character parity does not agree

Error

with the selected parity.

FER

Framing Error

Goes high if the received character has no valid stop bit.

Overrun

Goes high if the previously received character is not read

SWE

Status Word Enable

When low, places the status word bits (PE, OR, TBMT, FE,

RCP

Receiver Clock

Input for an external clock whose frequency must be 16

RDA

“Reset Data

When low, resets the received DA (Data Available) line.

(DA line not reset) before the present character is
transferred to the receiver Holding Register.

and DA) on the output lines.

times the desired receiver Baud rate.

Available

Received Data

Goes high when an entire character has been received and

Available

transferred to the receiver Holding Register.

Serial Input

Input for serial asynchronous data.

External Reset

After power is turned on, this line should be pulsed high

which resets all registers, sets serial output line high, sets
end of character line high, and sets transmitter buffer
empty line high.

Goes high when the transmitter Data Holding Register may

TBMT

Transmitter
Buffer Empty

be loaded with another character.

Data Strobe

Pulsed low to load the data bits into the transmitter Data

Holding Register during the positive-going trailing edge of
the pulse.

EOC

End of Character

Goes high each time a full character, including step bits, is
transmitted. It remains high until transmission of the next

character starts. This is defined as the mark (high) to space
(low) transition of the start bit. This line remains high when
no data is being transmitted. When full speed transmission
occurs, this lead goes high for 1/16 bit time at the end of
each character.

D-5

Table D-1 (Cont)
UART Signal Functions

PinNo.
25

| Mnemonic
SO

Name
Serial Output

~ Function
Output for transmitted character in serial asynchronous

format. A mark is high and a space is low. Remains high
when no data is being transmitted.

26-33

DB1-DB8

Data Input

Eight parallel Data In lines. DB8 (pin 33) is the MSB and
DB1 (pin 26) is the LSB. If 5, 6, or 7 bit characters are
selected, the least significant bits are used.

Control Strobe

When high, places the control bits (POE, NP, SB, NB1 and

NB2) into the control bits Holding Register.
35

No Parity

When high, eliminates the parity bit from the transmitted
and received character and drives the received parity error
(PER) line low. As a result, the receiver does not check
parity on reception and during transmission the stop bits

immediately follow the last data bit.

2SB

Two Stop Bits

Selects the number of stop bits that immediately follow the
parity bit. A low inserts 1 stop bit and a high inserts 2 stop

bits.
37,38

NB2, NB1

Number of Bits

Select 5, 6, 7, or 8 data bits per character as follows.

per Character

(Excluding Parity)

POE

Even Parity Select

Bits/

NB2

NB1

Char

(37

(38)

Selects the type of parity to be added during transmission

and checked during reception. A low selects odd parity and

a high selects even parity.

TCP

Transmitter Clock

Input for an external clock Whose frequency must be .16
times the desire transmitter Baud rate.

APPENDIX E

DH11-AD MODEM CONTROL INTERFACE

E.1

GENERAL DESCRIPTION

The DH11-AD modem control unit is comprised of the M7807 and M7808 module sets (Figure E-1). It is used to
interface the modem control signals between the modem and processor. Data is handled by the DH11-AD
asynchronous 16-line multiplexer. The modem control unit multiplexes 16 asynchronous modem interfaces. The

unit provides necessary control signals and levels to interface with Bell 103A/E/F/G/H, 202C/D, and 811B modems

or their equivalents. The interface levels are EIA/CCITT compatible for data set operations. Table E-1 is a glossary of

modem control terms.

‘

N\
BR

ERRUPT |etnih

A<17.00>

Ccs 0-15

SCAN

CONTROL

RING

0-15

LINE ENO-15

£SS

MODEM

LINES 0-3

LINES4-7

CO 0-15

A<i7:00>

SECRX 0-15

LINE #

MUX

LINES

AND

L INES 8-11

LINES 12-15

CCITT

CONVERTER

D<15:00>

DRIVERS
N

RECEIVERS

EIA

pisTRiBuTION]
PANEL

EIA/

H3178

:
15

MODEM

11-2894

Figure' E-1 Modem Control Block Diagram
E.2

FUNCTIONAL DESCRIPTION

The modem control signals for up to 16 lines are connected to the M7807 and M7808 through the H317B EIA

distribution panels. Level conversion for all lines is provided by these moduies.
11

1°

The modem control unit scans the SEC RX, CLEAR TO SEND, CARRIER, and RING lines for each modem line
sequenced by a line counter in the logic. When a transition
is detected on a line, for the modem line selected by the

line counter, an interrupt condition is generated. If interrupt enable and line enabled are both true, the interrupt
request logic asks for control of the Unibus. Likewise, the address selection logic allows the processor to send SEC

TX, REQUEST TO SEND, and TERMINAL READY to the modem designated by the line counter. The line counter
enables the particular signal to be asserted on the line designated. The line counter is sequenced through the ring
counter, which is clocked internally and enabled by the program controlled scan enable and step conditions.

E-1

Table E-1

Glossary
Modem Control Terms

Definitions

Test Point

SEC RX

Secondary Received Data (202)

CARRIER or CO

Received Line Signal Detector (CF)

Clear to Send (CB)

RING

Ring Indicator (CE)

LINE CNT

Line Count

CNTR

Counter

LSB

Least Significant Bit

MSB

Most Significant Bit

Enable

INI

Initialize -

INTR

Interrupt

HOLD (Ring, CO, CS, SEC RX)

Holding register for last known status (not current)

REQUEST TO SEND or RS
SEC TX

Request to Send (CA)

Secondary Transmitted Data (202)

TERM RDY

Data Terminal Ready (CD)

LINE EN

Line Enable

X DCDR

X Decoder for Memory

Y DCDR

Y Decoder for Memory

BUSY

Force Busy (103E)

There are two basic types of modem control: Transmit (to the modem) and receive (from the modem). The
transmit control functions are: Terminal Ready, Request to Send, and Secondary Transmit. The receive control

functions are: Clear to Send, Carrier, Secondary Receive, and Ring. The sequential usage of these control leads for
the various modems can be determined by using the modem timing diagrams shown in Appendix F. For example, a
typical channel establishment sequence for the 103A modem would be as follows:
a.

103A originate mode channel establishment (Figure F-1, Appendix F).

Setting the Data Terminal Ready lead to 1, followed by dialing via the DN11 Automatic Dialing

Unit or by manual means initiates a call to the remote modem.
2.

When the data link is established by the remote modem answering the call, Carrler Detect and

Clear to Send make the transition to the ON state.

If the modem control’s Line Enable for the line is set and Interrupt Enable and Scan Enable are

set, the transitions of Carrier and Clear To Send are detected and an interrupt is generated to the

Unibus.
4.

this time,

the

DH11-AD

may

transmit

and/or

receive data over the established data

communications link.

103A answer mode channel establishment (Figure F-1, Appendix F). Line Enable, Scan Enable, and

Interrupt Enable are assumed true.
1.

A Ring signal is forwarded from the modem to the modem control. This OFF

detected by the scanner and forwarded to the Unibus as an interrupt condition.

to ON transition is

The data link may then be established with the calling modem or line by setting Data Terminal
- Ready.

When the transitions of Carrier and Clear To Send occur (OFF to ON), the communications data
link is established and an interrupt condition is presented to the Unibus.

The DH11-AD may now transmit and/or receive data.

E.3 PHYSICAL DESCRIPTION

Modem control occupies two system unit module slots (1/2 system unit) in the DH11-AD (Figure E-2). This
scan-operated modem control for 16 asynchronous modems, uses the following parts:

Qfiantity

Part

Description

1
1

M7808
M7807

Data MUX (8 Lines), Scan Control
Data MUX (8 Lines)
Address Selector
Interrupt Control

1
1

BCO8R-12
H861
H315

Mylar Cable (4 Lines)
Test Connector (16 Lines)
Modem Test Connector

The interconnection of the parts is shown in Figure E-2. The cabling for the modem level converters is part of the
-

modem control.

E.4 ENVIRONMENTAL LIMITS, PERFORMANCE SPECIFICATIONS, AND INTERFACE SPECIFICATIONS
The environmental limits, performance specifications, and interface specifications are listed in Table E-2.
E.5

DETAILED DESCRIPTION

E.5.1

Introduction

The modem control consists of four basic logic units. They are the Address Selector Logic, Interrupt Control Logic,
Scan . Logic, and the Data Multiplexer Logic (MUX). These units are discussed in detail in the following paragraphs.
Refer to Figure E-3 for the functional scan block diagram. Also, the maintenance mode of operation is discussed.
E.5.2

Address Selector Logic

The address selector logic (M7807) is jumper-prepared to recognize the two register addresses assigned to the modem
control. When the bus designates either of these addresses, they are recognized by the selector logic and, according
to the bus operation (DATO, DATI, DATIP, or DATOB), SELECT, IN and OUT signals are generated. DATI or
DATIP bus operations designate the IN selection signal for gating to the bus; DATO or DATOB designate the OUT
selection signal for gating from the bus. SELECT 0 and OUT LOW load the CSR, while SELECT 0 and IN gate the

CSR to the bus. SELECT 2 and IN gate the MUX TERM RDY, MUX LINE EN, MUX RQ TO SEND, and MUX SEC
TX to the bus along with MUX SEC RX, MUX CLEAR TO SEND, MUX CARRIER, and MUX RING. Signals
SELECT 2 and OUT LOW enable the generation of the clock for MUX transmitting to the modem lines.

E-3

MODEM

H315 MODEM
TEST CONNECTOR

(1 LINE)

LINES 0-3

LINES O-7

LINES 4-7

LINES 8-15

LINES 12-15

DATA

J16

\11

J20

J21

ZH3ITB ETA PANEL
HE61

—J

(16

TEST MODULE
/M

]

(16 LINES)

LINES)

>
o

BCO8BR-~12

Ja |

o Lnes

|B o

\_r

M7807
M7808

—————————
O

(4 LINES EACH CABLE)

DHi1- AB
(DOUBLE

SYSTEM UNIT)

M7808

MUX 8 SCAN CONTROL

M7807

MUX &

BUS

CONTROL

|je—LINES 0-7

|e— LINES 8-15
F

1-2895

Figure E-2
E.5.3

Modem Control Hardware Configuration

Interrupt Control Logic

The M7307 Interrupt Control logic enables the unit to gain control of the bus (become bus master) and perform an

interrupt operation. This is accomplished through a bus request (BR) at BR level 4. Detection of a transition
in

CARRIER, SEC RX, CLEAR TO SEND, or RING signal lines from any modem, designated by the modem
line

counter, generates an interrupt request through the interrupt logic as long as INTR EN has been set by the program.

Any of these conditions causes the interrupt control to generate the BR to the processor requesting bus control.
E.5.4

Scan Logic

The scan logic (engineering drawing D-CS-M7808-0-1, sheets 2 and 3) includes the control logic for the modem

control and the Unibus receivers and drivers. The Unibus receivers and drivers are standard for the PDP-11 and meet

all requirements for connection to the Unibus. The control logic performs the programmable functional conditions
of the CSR. The principal logic units of the scan logic are the ring counter, line counter, scan memory logic, and

interrupt logic.

the

Table E-2
Specifications
Environmental Limits

Power requirements

+5V,24 A

Humidity (relative)

Up to 90% (non-condensing)

Temperature

10° C to 50° C

Performance Specifications

CARRIER, SEC RX, CLEAR TO SEND, and RING

Interrupts

transitions cause interrupts.

Modem status maximum rate change

10,000 Hz for both receive and transmit circuits.

Scan rate

Tests

line

conditions

for interrupts

rate

1 MHz * 10% or one line per 1.2 us, approximately.
Scan control

Programmable to allow scan to run free (SCAN EN) or
to sequentially step through Scan line by line (STEP).

LINE cdunter

Line numbers (LINE #) may be accessed by program

sequentially or randomly, without concern for internal
synchronization.

The Scan cannot be halted and the line number changed
with one instruction due to the Read/Write cycles of the
Scan’s memory. Also, the program must wait for CLR
SCAN (programmable) to ripple through the control

Scan limitations

memory logic. -

Hard-wired to level 4 (BR4).

Interrupt bus request

Interface Specifications

Presents one unit load to the bus and meets all Unibus

Unibus

electrical specifications.

Provides modem control leads compatible to modem

Modem interface

types 103A, 103F, 103E (G and H), 202C/D, and 811B.
(Types may be mixed over the 16 lines available.) These
lines are EIA RS-232-C and CCITT compatible.
Condensed EIA RS-232-C Electrical Specifications

Driver output logic levels with 3K to 7K load

I5V>,,25V
SV

P15V

Driver output voltage with open circuit

V<25V

Driver output impedance with power off

20 > 300 ohms

E-5

Table E-2 (Cont)
Specifications

Condensed EIA RS-232-C Electrical Specifications (Cont)
Output short circuit current

/IO/ <05A

Driver slew rate

dv<30Vus

dt
Receiver input impedance

7k > R, >3k

Receiver input voltage

*15 V compatible with driver

Receiver output with open circuit input

Mark

Receiver output with +3 V input

Space

Receiver output with -3 V input

Mark

LOGIC “0” = SPACE — CONTROL ON

)

AARNRNRNRRNNY

AAMANNNNNNNN

Noise margin

Transition region
Noise margin

LOGIC “1” = MARK = CONTROL OFF

Initiation of the modem control is achieved through the program-controlled device registers. Initialization is achieved
through the CLR SCAN signal from the program and BUS INITIALIZE. These signals combine to clear the logic

flip-flops and counters, while setting CLEAR CYCLE. Signal CLEAR CYCLE puts a low to the direct clear inputs of
the HOLD flip-flops (SEC RX HOLD, CS HOLD, CO HOLD, and RING HOLD) and inhibits inputs from the MUX
to scan memory while the memory is being cycled through all lines. The CLEAR CYCLE flip-flop is then cleared

when all scan memory locations have been written with Os. The modem control is now initiated by setting the SCAN

EN bit. SCAN EN with DONE clear (no interrupt conditions present) inputs the 8271 Ring Counter. The CLOCK
cycles the ring counter through four states; that is, the ring counter increments the LINE CNTR (LINE INCR), loads

the HOLD flip-flops with the last known contents of memory (at LINE #) (LD HOLD), transfers the current status

of the LINE # to the memory section (IN WRITE), and tests the contents of the HOLD flip-flops and the memory

section (at LINE #) for interrupt-causing conditions (INTR TEST). This four-state ring counter sequence is repeated
for each line (LINE #), sequentially, as long as the SCAN EN condition with DONE clear is present to the ring
counter. The programmable flip-flop STEP can also enable the ring counter, but for only one count; STEP enables
one clock of the ring counter to increment the LINE CNTR (LINE INCR) which feeds back to clear STEP. The ring
counter sequences the other three steps (LD HOLD, IN WRITE, and INTR TEST) before coming to rest.

The LINE CNTR is programmable for loading with a desired line count from the bus (BUS DATA 00 through BUS

DATA 03). The LINE CNTR outputs provide line selection for testing, sensing, and modifying the line status on a
per line basis. The LINE CNTR output also inputs the memory to select the memory locations in the 7489 for each

line’s SEC RX, CS, CO, and RING status. When the ring counter sequences the WRITE IN signal, the status of each

E-6

INITIALIZE—O

BR4 TO BUS

INTERUPT

ENABLE

DONE

INTERRUPT TEST

RING

COUNTER

CLOCK —

SCAN ENABLE

D
INCR LINE

HOLD

)

HOLD

LD HOLD

CNTR

(MEM—»| HOLD)

){_/(

COUNTER

—

LINE EN
0~-15

MUX-»MODEM STATUS

TERM RDY
0-15

RS
0-15

SEC TX
0-15

WRITE

(STAT—>MEM)

0-15

Figure E-3

RING

0-15

MUX—»MODEM STATUS

‘

R/W FROM (TO)BUS

CcS

SEC Ry

ww
v—

)~£

i-0749

Scan Functional Block Diagram

of the RING, CARRIER, SEC RX, and CLEAR TO SEND lines for the particular modem (LINE #) is loaded into
the memory location of the 7489s designated by the LINE CNTR inputs.

During INITIALIZE, when the X- and Y-decoders are loaded from LINE 0000, the decoder’s LSB (least significant
bit) output combines with the ring counter WRITE IN sequence signal to clear the CLEAR CYCLE flip-flop. The
HOLD flip-flops can now be input from the 7489 memory. For each line selected through the X- and Y-decoders,
the states of the MUX SEC RX, MUX CLEAR TO SEND, MUX CARRIER, and MUX RING are loaded into the
respective memory locations by the WRITE IN signal from the ring counter. When WRITE IN is unasserted, the
memory presents the state for the respective LINE # to HOLD flip-flops. Each time the ring counter sequer.ces LD
HOLD for each line, the HOLD flip-flops are loaded with the contents of the respective memory location.. The

memory contents are the last known state or status designated by the LINE CNTR. When the ring counter sequences

WRITE IN, the new status is loaded into memory for the particular line. This new status (SEC RX, CLEAR TO

E-7

SEND, CARRIER, and RING) is then compared with the contents of the respective HOLD flip-flops in the
Exclusive OR gates for SEC RX, CLEAR TO SEND, and CARRIER and the AND gate for RING. This gating
operation detects transitions in the line status each time the LINE # is sequenced. A (low to high) transition of any
of the conditions for a particular line generates an interrupt condition. A (high to low) transition also generates an

interrupt condition for all lines except RING which is compared to the previous line state by an AND gate. This is
tested when the ring counter sequences INTR TEST. The presence of an interrupt condition at INTR TEST with the

MUX LINE EN present (see MUX description) sets DONE. DONE set, with INTR EN set by the program, generates
an interrupt condition to the interrupt control logic, which generatés a bus request to the processor. An interrupt
will not occur if the program has modified the LINE CNTR and the ring counter has not cycled. For example, if the

Scan last tested LINE #5, followed by the program’s modification of the LINE CNTR to LINE #8, for example, the

HOLD flip-flops now contain the line status of LINE #5, while the memory is at LINE #8 and inputting the
transition gates for LINE #8. Therefore, any transitions detected are a function of LINE #5 and LINE #8 and are

not valid interrupt conditions.

E.5.5 Modem Control (MUX) Logic
The modem control (MUX) logic contains the status selector logic for each line interfaced (engineering drawing
D-CS-7808-0-1). The status to the modem is Read/Write and the status from the modemis Read Only. Read/Write
status control signals are LINE EN, TERM RDY, RQ TO SEND, and SEC TX. The Read Only status control signals

are RING, CARRIER, CLEAR TO SEND, and SEC RX. For any Read Only status to be read, the respective LINE
EN must be on. If this is not the case, RING, CARRIER, CLEAR TO SEND, and SEC RX are blinded to the line
status from the scan control logic.

The MUX Write is clocked by the LINE DCDR. The LINE DCDR is input with the LINE CNTR output and WRITE

SEL. WRITE SEL is initiated by the selection logic through OUT LOW and SELECT 2, and thus program-controlled.
Also, WRITE SEL reflects the LINE CTR GROUP 0—7 or GROUP 8—15 signals that enable the respective LINE

DCDR of each MUX module. The LINE DCDR provides a CLOCK signal for each line’s status signal selector. Each
CLOCK for each line inputs a respective 74175 for clocking in LINE EN and either SEC TX, TERM RDY, or RQ TO

SEND to be transmitted on the respective modem line. The data bits for LINE EN, SEC TX, TERM RDY, and RQ
TO SEND input the 74175 from the receivers (D00 to D03). CLOCK enables the 74175s to output to the respective

modem lines.

Three of the LINE CNTR outputs provide enabling signals for the 74151 selectors in the MUX. The states of these
inputs according to the LINE #select the proper line to be enabled at the selectors from the respective modem lines.

For the signals coming from the modems, the RING SELECTOR, CARRIER SELECTOR, CLEAR TO SEND
SELECTOR, and SEC RX SELECTOR are enabled at the current LINE # by INTR STATUS. INTR STATUS is
asserted to enable the receiver selectors when CLEAR CYCLE is not set and MUX LINE EN is present. The receiver
selectors output MUX RING, MUX CARRIER, MUX CLEAR TO SEND, and MUX SEC RX to the memory section

of the scan logic to test for interrupts. MUX LINE EN is generated in the transmit selector when the programmable
LINE EN is set for the respective LINE #, enabling the selector from the LINE CNTR. These transmit selectors are
enabled by R/W STATUS, which asserts to the respective MUX module for either Lines 0—7 (GROUP 0—7, from

LINE CNTR) or Lines 8—15 (GROUP 8-15 from the LINE CNTR). The control signal status conditions are
available to the program with the receive conditions handled by the scan logic for interrupt conditions and the
transmit conditions for each line sent to the respective modems.

E.5.6

Maintenance Mode

The maintenance mode of operation in the modem control is achieved by the programmed setting of the MAINT
MODE flip-flop of the CSR. Setting MAINT MODE forces MUX SEC RX, MUX CLEAR TO SEND, MUX

CARRIER, and MUX RING low, asserting a transition for the line designated by the line counter. These conditions
can then be checked by the program through the CSR and allowed to cause interrupt conditions.
E.6

OPERATIONAL PROGRAMMING

The two programmable device registers and their specific bit assignments are listed in the following paragraphs.

E.6.1 Control Status Register (CSR) (Address: 770XX0)

Description

Status

Bit

The LINE # bits are the binary addresses for the 16 lines (0—15) as follows:
W

LINE #

Line #

03:00

Bit

1111

If the Scan is cleared by INITIALIZE or CLR SCAN, the Line # Register will
settle in 16 us + 10%. When settled, the Line # Register will be set to Line #
0 (0000).
NOTE

When the Scan is enabled (or STEP) the next line to be
tested will always be Line # +1. These bits are Read/Write
and are cleared by INITIALIZE and by CLR SCAN.
04

BUSY

BUSY provides a program indicator that is set to 1 when the Scan is cycling.

This bit is particularly useful to determine when a CLR SCAN (bit 11)
completed the task of cycling Os into the Scanner’s memory elements.

has

In addition, this b1t must be tested for O if SCAN ENABLE was turned off
preparatory to changing the Line #.
In Interrupt Mode, this procedure guarantees that detected transitions are
serviced before the Line # is changed. (If functioning with interrupts OFF,
then DONE should be tested after BUSY is found to be 0.)

The SCAN ENABLE flip-flop allows the scan to “free run,” i.e., testing all
lines sequentially if the DONE flip-flop is cleared.

When the SCAN EN flip-flop is set to 1 and DONE is 0, a ring counter is
allowed to cycle in the following order (from Rest):
o

SCAN EN

Increment line counter.

Write current modem status into memory.

Store contents of memory (Line # Address) in the HOLD flip-flop.
Compare HOLD and contents of memory for Interrupt conditions.

E-9

Bit

Status

05 (Cont)

Description
The ring counter continues to cycle (a to d) if DONE remains 0 and SCAN

EN is set. If the SCAN EN flip-flop is negated while the ring counter is
cycling (i.e., DONE not set) the ring counter will come to rest in 1.2 us + 10%

(MAX). The line # Register must not be changed until BUSY (bit 04) is
found to be 0. This bit is Read/Write and cleared by INITIALIZE and CLR
SCAN.
INTR EN

If set to 1, Interrupt Enable allows DONE to cause an interrupt on priority

four. This bit is Read/Write and cleared by INITIALIZE and CLR SCAN.
07

DONE

The DONE flag, when set to 1, indicates that the hardware Scan has detected
a transition on CARRIER, SEC RX, CS, or the RING Modem Status leads.

Additionally, DONE freezes the Scan which makes the following available to
the programmer:
a.

The Line # that caused the interrupt

The state of the flags (4 bits)

Modem status (8 bits)

This bit is Read/Write and cleared by INITIALIZE and CLR SCAN.
08

STEP

STEP, when set to 1, causes the Scan to increment the Line # and test that
line for interrupts causing transitions. STEP can be used in place of SCAN
EN, but

care

(milliseconds)

should

be exercised that the Scan rate is great enough

that

double

carrier

transitions

will

detected.

Additionally, DONE does not inhibit STEP. A STEP requires 1.2 us + 10% to
execute. This bit is Write is only.
MAINT MODE

When the MAINT MODE flip-flop is set to 1, it conditions the Scan Input

(RING, CLEAR TO SEND, CARRIER, and SEC RX) to a 1 or ON state.
Utilizing STEP or SCAN EN with MAINT MODE exercises 100 percent of the

scan logic (not the data multiplexers). This includes the interrupt circuits and
the address selector.
This mode provides a diagnostic feature as well as on-line test facility for the
DM11-BB’s interaction with the Unibus. This bit is Read/Write and cleared by
INITTALIZE and CLR SCAN.
10

CLEARMUX

CLEAR MUX clears the REQUEST TO SEND, TERMINAL READY, SEC
TX, and LINE EN flip-flops for all lines, when this bit is set to 1. This bit is

Write 1s only.
11

CLR SCAN

CLEAR SCAN clears all active functions (Line #, SCAN EN, etc.) and the
memory

logic

when

18.8 us* 10% to

this

cycle

bit

set

The memory logic requires

a CLEAR through the memory locations. This

function is especially useful if the programmer requires knowledge of the ON
states of CARRIER, CLEAR TO SEND, RING and SEC RX. When the Scan

is enabled (or STEP) following a CLR SCAN, an interrupt will occur for all
ON states as they will appear (to the logic) as OFF to ON transitions.

E-10

Description

Status

Bit

SEC RX

The SECONDARY RECEIVE flag is 1 if an ON to OFF or an OFF to ON
transition has occurred on this modem lead. This bit is redefined as
RESTRAINT when the 811B Modem is used. This bit is not valid if the
program has changed the LINE # and the Scan has not cycled for one or
more lines. This bit is Read Only and presents 0 when INITIALIZED or CLR

Tha (T AD Tn QEND flagic 1 if an NN
nr
‘_0 ON tran S 1
Ul +
Of OFF
Uil
WG flF‘F‘
VN +n~

[

(98]

SCAN.
L€ CLOARN

1U OCIND 1@ 18 1 11 all

(l)

occurred on this modem lead. This bit is not valid if the program has changed
the LINE # and the Scan has not cycled for one or more lines. This bit is
. Read Only and presents 0 when INITIALIZED or CLR SCAN.
14

The CARRIER flag is 1 if an ON to OFF or OFF to ON transition has
occurred on this modem lead. This bit is not valid if the program has changed
the LINE # and the Scan has not cycled for one or more lines. This bit is
Read Only and presents 0 when INITIALIZED and CLR SCAN.

RING

The RING flag is 1 if an OFF to ON transition has occurred on this modem
lead. This bit is not valid if the program has changed the LINE # and the Scan
has not cycled for one or more lines. This bit is Read Only and presents O
when INITIALIZED and CLR SCAN.

E.6.2 Line Status Register (LSR) (Address: 770XX2)

Description

Status

Bit

LINE EN

The LINE ENABLE flip-flop, when asserted, enables RING, CO, CS, and SEC
RX to be sampled (line status) by the program, and to be tested for
transitions.

This bit is Read/Write and cleared by INITIALIZE and CLEAR MUX.
01

TERM RDY

Controls

switching

the

data communications

equipment to

the

communication channel (via modem).

Auto-Dial and Manual Call origination: Maintains the established call.

Auto-Answer: Allows “handshaking” in response to a RING signal.
This bit is Read/Write and is cleared by INITIALIZE and CLEAR MUX.
02

When REQUEST TO SEND is set to 1, it conditions the modem for transmit

if the communications channel has been established (switched network).
When the DM11-BB is used to interface with 103E (or equivalent) modems,
this lead is redefined as FORCE BUSY (RS=1=FORCE BUSY “ON”). This
bit is Read/Write and is cleared by INITIALIZE and CLEAR MUX.

E-11

Bit

Status
SEC TX

Description

The SECONDARY TRANSMIT (202) flip-flop, when 1, presents a MARK to

the modem’s secondary transmit lead. This bit is Read/Write and is cleared by
INITIALIZE or CLEAR MUX.

SEC RX

The state of the modem’s Secondary Receive lead, when 1, is a MARK state.
The SEC RX bit is inhibited when the LINE EN flip-flop is 0. When the
DM11-BB is used to interface with the 811B modem, this lead is redefined as
RESTRAINT. This bit is Read Only.

This bit reflects the current state of the modem CLEAR TO SEND lead. An
ON indicates that the modem is ready to transmit data. This lead is most
often the result of the REQUEST TO SEND lead. The CS bit is inhibited
when the LINE EN flip-flop is 0. This bit is Read Only.

This bit reflects the current state of the modem carrier control lead. An OFF

indicates that no signal is unsuitable for demodulation. The CO bit is
inhibited when the LINE EN flip-flop is 0. This bit is Read Only.
07

RING

This bit reflects the current state of the modem’s ring lead. The RING bit is
inhibited when the LINE EN flip-flop is 0. This bit is Read Only.
NOTE

The Line Status Register bits 07:04 are inhibited when
LINE EN is 0.
E.6.3

System Addresses

Addresses are assigned for sixteen DH11-AD modem controls per system and are assigned as follows:
Ist control

Address

770500

770502

2nd control

Address

770510
770512

16th control

Address

770670

770672
E.6.4

Interrupt Vectors

Each control requires one interrupt vector. The vector addresses are assigned upward from 300 to 777. The modem
control falls in behind the DN11 in contiguous assignments from 300. The sequential list leading to the modem
control is:

DC11
KL11

DP11
DM11-AA
DN11

DM11-BB or DH11-AD modem control

The DM11-BB option and the DH11-AD’s modem control module set share the same address and vector space. Both

may be in a single system since they are software compatible.
E.6.5

Timing Considerations

The control’s timing considerations consist of scan control and CLR SCAN operations. Scan control through the
CSR allows the scan to either run free (SCAN EN) or to be sequentially stepped through the line counter line by line
(STEP bit of CSR). The Read/Write cycles of the scan logic force the program to wait after issuing CLR SCAN, until
it has cycled through the memories. Also, the scan’s Read/Write cycles prevent halting the scan and changing the line
number with one machine cycle.
E.7

MAINTENANCE

E.7.1

Introduction

Maintenance consists of running two diagnostic software tests: the ON LINE and OFF LINE tests. The ON LINE
diagnostic tests 100 percent of the scan logic, interrupts, and the Unibus interface. Additionally, 70 percent of the
data multiplexer may be tested. The OFF LINE test uses a test connector to test 100 percent of the modem control,
up to the point of demarcation at the modem interface. Paragraph E.7 provides instructions for running the tests as
well as the hardware configurations for the respective tests.
E.7.2 Testing Configurations

The test/diagnostic procedures provide for four test configurations, two fo_r the OFF LINE and two for the ON
LINE tests are as listed:

OFF LiNE (used for production test and acceptance)
a.

Modem control with H861 termination

Modem control terminated with H315

ON LINE (limited data flow)

Modem loop back configuration (used for production test and acceptance procedures during the first six

Remote or local terminal via modem

months of production shipments)

E.7.2.1 Off Line — The OFF LINE test/diagnostic procedures exercise 100 percent of the modem control hardware
up to the point of demarcation at the modem interface. The OFF LINE test requires two configurations (Figures E-4
and E-5) to achieve 100 percent testing.

Hardware requirements are as follows:
1 PDP-11 with > 4K core

1 DH11-AD System Unit (modules not required)
1 Modem Control Module Set (M7807 and M7808)
1 H861 Test Connector (16 lines)
1 H315 Modem Test Connector (1 line)
4 BCO8R Cables

1 BCO5D-25 modem cable

1 MAINDEC-11-DZDHK

E-13

SEC TX

SEC RX

TERM RDY

{

—

H861

vl FOR ONE
~

LINE

co
RS

RING

N
|
B
U

LINES

0-3

LINES 4-7

fjb

LINES 8-11

H861

(16 LINES)

LINES 12-15
M7807 and M7808

Figure E4

11-2889

Test Configuration with H861

OFF LINE — Terminated with H861

Step

Procedure

Assemble hardware per Figure E4.

Operate MAINDEC-11-DZDHK per MAINDEC procedures.

Five or more passes is considered a valid test.

Assemble hardware per Figure E-5.

Operate MAINDEC-11-DZDHK per MAINDEC procedures.

Five or more passes is considered a valid test.

E.7.2.2

On Line — The ON LINE Test/Diagnostic will function with limited configurations and is intended
to
perform a confidence test, in that the control will adapt to 103, 202, and 811B (or equivalent) type
modems. The
811B configuration is left out as the 202 satisfactorily exercises all of the active elements used
with the 811B

Interface.

The ON LINE test utilizes two configurations as illustrated in Figures E-6 and E-7. Figure

they may be either two 103As or two 202Cs.

E-6 utilizes two modems:

Figure E-7 provides an ON LINE test for up to 16 lines to a local or remote terminal. In this configuration,
the
modem control is operated in the Auto-Answer mode. The modems connected are 103 As, while those
connected to
the terminal may be 103As or acoustic couplers.

E-14

______

JUMPER ON CABLE
MODULE (M970).

RESTRAINT

SECTX

SEC RX

TERM RDY

]

CS
CO
RS

RING

FORCE BUSY

( 0
]

LINES 0-3

U
N

|
|
|

LINES 4-7

[

LINES 8-11

LINES 12-15

|
|

M7807 and M7808

——L{][D H315 MODEM TEST CONNECTOR
H317B

DISTRIBUTION
PANEL

11-2890
Figure E-5

Test Configuration, Distribution Panel and Test Connector

H317B

DISTRIBUTION
PANEL

LINEO-3

LINE 4 -7

LINE

LINE 12-15

8-11

1. Line zero remains stationary

NOTES:

MODEM

—————

SWITCHED

NETWORKC)_—

103A/202C

(R
.

M7807 and M7808

MODEM

103A/202C

I|
|

F—==="

—
I

2. The modem for line ONE,following completion of the test,is then moved to line Two---then Three---to line Fifteen.

(or to whatever number of lines are implemented).
n-2891

Figure E-6

Test Configuration (ON LINE Modem Loop Back)

E-15

OR
H317B

REMOTE

DISTRIBUTION

PANEL

MODEM

wCw—2C

LINE 0-3

NETWORK

MODEM

103A/COUPLER

{
[

LINE 8 - 11

LINE 12-15

r=—--=7

MODEM

[ _

>___

L lo3are0ee|

v
Figure E-7

LINE 4 -7

M7807 and M7808

SWITCHED

103A

1-2892

Test Configuration (ON LINE Modem to Terminal)

The hardware required is:

1 PDP-11 with > 4K Core

1 DH11-AD
1 modem control module set (M7807 and M7808)

4 BCO8R Cables

A/R Modems (103
A or 202C)
ON LINE — Modem Loop
Step

Procedure

Assemble hardware per Figure E-6.

Connect a modem (originate) to Line 0.
A second modem (answer) should be connected to any line that requires a test

(Lines 1 through 15).
4

Operate MAINDEC-11-DZDHK per MAINDEC procedures.

Five or more passes is considered a valid test.

ON LINE — Modem to Terminal

Step
1

Procedure

Assemble hardware per Figure E-7.
Connect modem (103
A) as required to lines O through 15. These modems should be
connected for Auto-Answer mode of operation.
NOTE

The terminal should originate all communications channels.

E-16

Step

Procedure

Operate MAINDEC-11-DZDHK per MAINDEC procedures.

Satisfactory transfers to (from) the terminal(s) is considered a valid test.

APPENDIX F

MODEM TIMING AND FLOW DIAGRAMS

This appendix provides the timing and flow diagrams for some modems utilized with the modem control. Diagrams
are for reference information and are as follows:

A Channel Establishment Sequence
Data Set 103

Figure F-1

A Space Disconnect Sequence
Data Set 103

Figure F-2

Data Set 103F Timing Sequence

Figure F-3

Data Set 103E Type Sequence Chért for a Call Originated in the

Figure F-4

Semiautomatic Manner and Answered Automatically

Data Set 103E Type Detailed Disconnect Sequences

Figure F-5

Figure F-6

Establishment of a 202C Call
:

Tum Around In Data-Phone Service 202C
811B Originating and Answering Flow Charts for CPT for 3 or 4 Row

TWX Service Data Set Tone Detection without EON

811B Originating and Answering Flow Chart for CPT for 3 or 4 Row

TWX Service Data Set Tone Detection with EON

F-1

Figure F-7

Figure F-8

Figure F-9

ORIGINATION STATION

COMMENTS
TO DS

CUSTOMER TURNS

CD LEAD ON
LIFT HANDSET

DIAL TONE HEARD IN

HANDSET RECEIVER

DIAL NUMBER

RINGBACK HEARD

ANSWERING STATION

INTERFACE CIRCUITS
BA

LINE SIGNALS

FROM D/S

ON-HOOK|

S
N

NORMAL IDLE STATE

AUTO (ANSWER) KEY

OPERATED

DIAL

RINGING HEARD - RING

\\\

RINGING — CUST. TURNS

DIALING | pivaine

JONE

\\\\

§
N

—

DATA TERMINAL READY

CD) ON, IF NOT ALREADY

RING-

BACK

OFF-HOOK

%
\

D sec. |+ F2m

UNCLAMP RECEIVE

DATA (BB) LEAD

\\\

-—

INDICATOR (CE) FOLLOWS

DEPRESS DATA KEY

\\\

DATA LAMP LIGHTS

I —

RECEIVER

F2M RECEIVED AND

HOOK

COMMENTS

FROM D/S

OFF-

HEARD IN HANDSET

INTERFACE CIRCUITS
TOD/S

CALL ANSWERED — DATA

SET IN DATA MODE —

1500

DATA SET READY {CC)

)
LIGHTS

+500 | TURNSONDATA LAMP

150:50

\\\

355?&

F IM RECEIVED
ORIGINATING DATA SET

SENDS F1M

CARRIER DETECTOR (CF}

|®FM

FiM

s | UNCLAMP RECEIVE

pes

AND CLEAR TO SEND

DATA LEAD (BB)

265+

50750

(CB) LEADS TURN ON

«—F2DATA

DATA TRANSMITTED

F1.DATA—

AND RECEIVED

SPACE OR OFF

MARK OR ON

AND CARRIER DETECTOR

&5Mms | (CF) LEADS TURN ON

SEQUENCE COMPLETE

CLEAR TO SEND (CB)

SEQUENCE COMPLETE

DATA TRANSMITTED
AND RECEIVED

m DATA PRESENTED 1S NOT EFFECTIVE

@ DATA TRANSMITTED OR RECEIVED
150 MS PERIOD IN WHICH

MARK HOLD

DATA MAY BE RECEIVED

BEFORE CARRIER DETECTOR (CF) TURNS ON
1-0770

Figure F-1

Data Set 103A Channel Establishment Sequence

STATION RESPONDING TO DISCONNECT

STATION INITIATING DISCONNECT

T0 D/S

DATA TRANSMITTED

o ‘B8

AND RECEIVED

FROM D/S

T0 D/S

CE CF
B

COMMENTS

INTERFACE SIGNALS

LINE SIGNALS

INTERFACE SIGNALS

COMMENTS

FROM D/S

CE CF
T

k&—— DATA —»

READY (OD)
SeMINAL
OFF — REC. DATA (BB)
CLAMPED — DATA SET

SENDS LONG SPACE
(3000 MS) SIGNAL

o'ms

sPACE —

TIMED FOR
RACEIVED.
1500 MS

1500
Ms

*CUSTOMER MAY

\
\

AFTER 50 MS

TURN CD ON AGAIN

3000

SPACE —

ALAwe
o | O
TRANS. CARRIER OFF ~

TRANSMITTED CARRIER

§
§

\
N
N

- DATA SET DISCONNECTS

N
N

{CC) TURNS OFF — DATA

LAMP GOES OUT

\\\

LINE — DATA SET READY

¥
0MS

le— ONHOOK —

DATA SET DISCONNECTS

OFF, DATA SET DISCONNECTS LINE.

N
N
\
N
N
N

’\
N
\

\
N

N
N

KEY

D SPACE OR OFF

[m] DATA REPRESENTED IS INEFFECTIVE

I MARK OR ON

@ " DATA TRANSMITTED OR RECEIVE

§
N

11-0771

MARK HOLD

Figure F-2 Data Set 103A Space Disconnect Sequence

F-3

te————— INITIATE SEQUENCE — (CA} ON

CIRCUIT

DESIGNATION

FUNCTION

(DATA SET READY)

?
|G
:
L

CA (REQUEST TO SEND)
CB (CLEAR TO SEND)
-cr {CARR. DET.)
BA (SEND DATA)

>
»
»
»

DATA

te—— 265 ——sle—e MESSAGE —f

START END OF SEQUENCE — (CA) OFF

(RECEIVE DATA)

[DATA SET READY}

;
'|v‘
:
r
o

CA
CB
CF
BA
BB

{REQUEST TO SEND)
(CLEAR TO SEND}
(CARR.DET)
(SEND DATA)
(RECEIVE DATA)

>
>
>
>————m
e~ 200

>
>
>
—>
>

—fe-+65

[~ SEQUENCE TERMINATED

*65 MS PERIOD IN WHICH DATA MAY BE RECEIVED (NOT RECOMMENDED)}
VARIABLE TIME BETWEEN “END OF MESSAGE"” AND STARTING OF
TERMINATING SEQUENCE — ALL TIMES IN MILLISECONDS; NOT TO

SCALE - PROPAGATION TIMES IGNORED

LEGEND
TRANSMITTED SIGNAL

NONE

CIRCUIT BB

CIRCUITS C-

e MARK HOLD

— OFF

[] wnce
- MARK

I e
- MARK

W DATA FROM BA

W DATA

RECEIVED FROM

OTHER END

1i-0769%

Figure F-3

Data Set 103F Timing Sequence

ARNSWERING

ORIGINATING

TOD/S

NORMAL IDLE

STATE

T‘ Y

CD 'BB

ON-HOOK

AN
N
%

TONE
DIAL
HEARD THRU

\\\\N

DEPRESS DATA

KEY WHILE

SPEAKER

FROM D/S

—1

oN-HOOK|ON-HOOK|

DIALING

RINGBACK

F2M RECEIVED

THRU LOUD-

SPEAKER

115¢30

Fom

LOUDSPEAKER
PUTS FIM ON

AUTO ANS KEY—

RINGING HEARD

}\\‘
\\

N
§

CE FOLLOWS

RINGING, CUST.

TURNS CD — ON

£15
SEC.

F2M

D/S PUTS
LINE, ABORT
ON

TIMER STARTED

§
N

F2M + FIM

-—

MUTED — D/S

NORMAL IDLE

435:65
MSEC.

AND HEARD

nEnEE

OFF-HOOK

FROM D/S

ainG. [FNGING

N
\

CD BB

DIAL 1

HEARD

"BA

l n

§
\

DIAL NUMBER

ToD/S

OFFHOOK
<« CNE

COMMENTS

INTERFACE CIRCUITS

LINE SIGNALS

INTERFACE CIRCUITS

COMMENTS

—

\
%

LINE

1151 30

F1M RECEIVED

MSEC.

’\

2002100

35:25

MSEC.

60:40
MSEC.

HANDSHAKING

F2-DATA + Fit

COMPLETED
ABORT TIMER

STOPPED

HANDSHAKING

F2DATA +

COMPLETED

F1-DATA

DATA

|
.

NOTES:

SPACE OR OFF
MARK OR ON

flm DATA PRESENTED IS NOT EFFECTIVE

1. TIMING SHOWN IS FOR “CR.CF
INDICATIONS SEPARATE"”
OPTION, FOR “CB-CF iINDICATION COMMON" OPTIONS
OF TURNS ON WITH CB.

2. CHART FOR STATION USING

CE ON" OPTION.

g DATA PRESENTED BY CUSTOMER ON
BA IS TRANSMITTED AND RECEIVED

MARK HOLD
11-0772

Figure F4

Data Set 103E Type Sequence Chart for a

Call Originated in the Semiautomatic Manner and Answered Automatically

F-5

DISCONNECT INITIATED BY EITHER
A} BUSINESS MACHINE TURNING CKT. CD OFF
B}

ATTENDANT DEPRESSING CLEAR KEY, OR

C} AUTOMATIC-CALLING UNIT SIGNALING DATA SET

TO DISCONNECT

INTERFACE CIRCUITS

g
%,
NOTE 4

774
7

FOR ANS MODE STATION WITH “CE-ON” OPTION,

IF THE OTHER STATION IS WIRED TO DISCONNECT ON SPACE, CF

TIME SHOWN IS FOR “SEND DISCONNECT-YES" OPTION.

WILL GO OFF DURING THIS INTERVAL.

TIME FOR "SEND DISCONNECT-NG” OPTION IS 3020 MSEC,

IF DISCONNECT IS INITIATED BY CD OFF., OTHERWISE

Ead

TIME IS AS SHOWN.
SEQUENCING OF TURN-OFFS MAY BE EITHER CF, CC, CE, OR CC, CR,

CE,OR CC, CE, CF.
o

NOTES.

IDLE STATE

TIME SHOWN IS FOR "CB-CF INDICATIONS SEPARATE* OPTION,
FOR "CB-CF INDICATIONS COMMON" OPTION, CF TURNS OFF

WITH CB.

Figure F-5

Data Set 103E Type Detailed Disconnect Sequences

F-6

CALLING STATION

LINE CONDITION

CALLED STATION

APPROXIMATELY 15 SEC. IF ACUS01C APPROX 1 SEC.

SET UP TIME

TIME REQ'D IF MANUAL OR WITH ACU 801A

[ DIAL

STATION GOES OFF-HOOK ——————
>—

VARIES FROM A FEW SECONDS ON LOCAL CALLS
TO 25 SECONDS OR SO: TYPICALLY 10TO 15
SECONDS

Cq L ‘957‘0
“Up

CE TURNED ON ONCE PER
SIX SECONDS UNTIL CALL
RING

MANUALLY ANSWERED OR CD
TURNED ON

wrass

TALK

ANSWER

IF UNATTENDED ANSWER FEATURE
IS USED, THIS STEP IS OMITTED

DATA BUTTON IS DEPRESSED IF

CALL IS ATTENDED. CC GOES ON
CD MUST BE ON OR CALL WILL
BE DROPPED. CA IS ALSO TURNED ON

RECOG. & DISAB. SIGNAL

CF COMES ON 40 * 10 MILLISECONDS
CB 1S TURNED ON BY DATA SET
200 + 20 MSEC AFTER MARK SIGNAL

MARK SIGNAL

NOT ON. IF REVERSE CHANNEL FEATURE
IS NOT USED TRANSMISSION CAN BEGIN
AFTER WAITING LONG ENQUGH FOR THE

CALLING STATION TO GET INTO THE DATA
MODE

NO DATA TRANSMITTED BECAUSE SB

44— SBON
MARK AND
REVERSE CHANNEL

«4———

{
T

]

BUSINESS MACHINE REACTION TIME

RECEPTION OF REV. CHAN

(

DATA AND REVERSE
CHANNEL SIGNALS

TRANSMISSION OF DATA

SIGNALS

SAME TIME

MARK SIGNAL TURNED ON BECAUSE
CAISON

TIME

AND DISABLING SIG.

RECEPTION OF RECOG.
BB BECOMES UNCLAMPED AT THE

MARK SIGNAL

—

AFTER RECEIPT OF SIGNAL

{3 SECONDS)
3515

WAS TURNED ON

RECEPTION OF DATA

CF COMES ON 50 + 10 MILLISEC

SIGNAL

SIGNAL FOR ACU AT CALLING STATION

(

CIRCUIT SA MUST BE ON

(

DROPPED. CC WiLL BE TURNED ON.

- §

CD MUST BE ON OR CALL WILL BE

TRANSMISSION OF REVERSE CHANNEL

ACU PUTS DATA SET IN DATA MODE

OR OPERATOR PUSHES DATA BUTTON.

AND DISABLING

RECEPTION OF MARK

TIME

PLANT {1.1 SECOND}

DISABLED. PROVIDES RECOGNITION

RECOGNITION

| |
= |

OPERATOR OR ACU REACTION

OF TELEPHONE SWITCHING

CAUSES ECHO SUPPRESSORS TO BE

VARIABLE UP TO 50 MILLISEC. —————»

PROPAGATION

DELAY

PERMITS PROPER OPERATION

NOTE: IT IS ASSUMED FOR THE PURPOSE
OF THIS EXAMPLE THAT THE CALLED

PARTY WILL TRANSMIT FIRST.

11-0774

Figfire F-6 Establishment of a 202C Call

—>

fa]

RCVE EOT

(SA ON)

e
Q
il

—

REACTION TIME

I 40 + 10

[

]

200+ 25

SUPP

»
k]

CF ON IF NO ECHO

CA ON

[xd

RCVE RC

CA OFF

SEND RC

RCVE DATA

[=]

PROPAGATION

Q
[+

TIME

STATION 2

22
%o

STATION 1

200

—

__//

CF ON IF ECHO SUPP

-«

so!

——

“

CSON

LiX

QO
[+ 4

<
h

e
>

Q
4

DATA

]

1-0775

Figure F-7

Turn Around In Data-Phone Service 202C

F-8

ANSIWER

PWION

CDON

DLO OFF

{ACL TO CPT) ORIGINATE (ACU TO CPT)

(CPT TO DAS 811B)
|

CRQON

GROUND START ACU’S

[

[CPTTO ACLY)

COON

DLOON

(CPT TO DAS 8118)

{ACU TO CPT)

CE ON-OFF

WITH RINGING

(DAS 8118 TO CPT)

OFF HOOK

TEL. LINE TO

)

ACU AND DATA

SET
DETECTION

ook

CRTS

{ACU TO CPT)

ccon

DLOO

15SEC.

(DAS 8118 TO CPT)

(ACU TO CPT)

(DS‘)L

RECYCLES UNTIL NUMBER'IS OUTPULSED

FIMARK

{

FIMDE.

DPR ON

CEIVED WITHIN

WITHIN 8 SEC.

8 SEC.

DATA SET

)

BY ACU

PLACED IN ORIG.

MODE BY ACU

PND OFF

(ACU TO CPT)

MON F2M

(08)

DPR OFF

(CPT TO Acu)

CCON

TIMER
(DS}

(DS)

DSSON

(ACUTO CPT)

DAS 81183 +811B4 | DAS 81181
+ 81182

po!

]

| 20070 400 MS

{ACU TO CPT)

MONITOR

BS UNBLINDED

FORLONG

(DS}

SPACE

FIMSENT

(DS)

20070 400 MS
8, cF

{VIA DAS 811B)

ACU LOOSES

CONTROL OF LINE

[

DAS 81183 +81184 | DAS 81181+ 81182

TO DATA SET ONLY

—— == -

(oS}

DS)

ANS.-BACK

MESSAGE

DSS ON

MONITOR
FOR LONG

SPACE

8, CF

c8,cF

1 on

I
°

UNBLINDED
(DS)

(.
|

(0s)

DISCONNECT

SEQUENCE

F2M RECEIVED

F2M DETECTED

INITIATE

AUTO.DISC.

©S)

(DAS 8118
TO CPT)

RESET

TECTED

)t
ON FIRST PULSE

DIGIT OUT PULSED

F1M NOT RE-

RECEIVED

08}

—
AUTO. DISC, TIMING CKT. (D.S.)

(CPT TO ACU)

[

(DS}

DIGIT LEADS
SET BY CPT

TEL. LINE

MON. F1M

[

F2MSENT

;
!

(ACU TO CPT)

PY
’

PND ON

SFG.
!

ACU DET ECTS DIAL “GO-AHEAD"*
“GO-AHEAI

DLO ON

LOOP START ACU'S
*

]

|
1

;

CB.CF |
l

SENT (CPT)

]

MONITOR

FOR ANS_BACK

CRQ OFF

{CPT}

{CPT TO Acu)a

ANS.-BACK
RECEIVED

*IN SOME ACU’S DLO TURNS ON BEFORE PND.,

SET AFTER DSS ON” IS PROVIDED.

Figure F-8

i el -

IN OTHERS, PND TURNS ON BEFORE DLO

4ONLY IF OPTION “TERMINATE CALL VIA DATA

‘

MESSAGE

1-0776

811B Originating and Answering Flow Chart

for CPT for 3 or 4 Row TWX Service Data Set Tone Detection without EON

F-9

ORIGINATE

1
PWI ON

DLO OFF

D ON

(ACU TO CPT)

(CPT TO DAS 8118

{ACU TO CPT)

ANSWER

1
I

GROUND START ACU'S

CRQON
ICPT TO ACU}

!
|

€D ON

DLO ON

—

(ACUTO CPT)

TEL. LINE

(DS}
LOOP START ACU'S
i
hd
ccon
DLOON
{ACU TO CPT)
(165‘35‘3- (DAS 8118 TO CPT)
SEG.

ACU DETECTS DIAL

[*— -GoAHEAD"*

DLO ON

!
!
!
!

{ACU TO CPT)

DIGIT LEADS

CPT SETS DIGITS

SETBY CPT

!
1

(CPT TO ACU)

488 (EON INDICATION}

PR ON

{CPTTO ACL)

DIGIT OUTPULSED
BY ACU

|
ACUPLACES

PND OFF

(ACU TO CPT) DATA SET

{ACU TO CPT)

IN ORIGINATE

MODE {OFF HOOK)

OPR OFF

|CPT TO ACU) AND RELEASES

DSS ON

FM SENT

FORLONG

(DS)

IACU TO CPY)

(DS}

BSEC.

!
RESET

(Ds)

S8 ON

200 TO 406 MS

3?4 CF

]

UN-

(o)

gc? 00 MS

c8. CF

{

200

(ACUTO

cPT)

MONITOR

FOR LONG

DAS81183+81184 | DAS811B1+ 81182

SPACE (DS)

B CF
oN

;
;

ANS, BACK

MESSAGE

SENT (CPT!

)

DAS B11B1 + 811B2

DAS 81183 + 81184

{DS)

(ACUTOCPT) BLINDED

SPACE {DS)

INITIATE

DISCONNECT
SEQUENCE

(DS)

pm————=

F1M NOT RECEIVED WITHIN

l
i

F2m RECEIVED (DS

BB UNBLINDED

F1M RECEIVED
WITHIN
8 SEC.

MONITOR

MON F2M (DS)

AUTO. DISC. TIMING CKT. (D.S.)

FIMDE. Ay10. DISC.
TECTED 1imeR

1
TEL.

LINE

ACU LOOSES

TODATA CONTROL

SET ONLY

OF LINE

IVIA DAS 8118)
CRG OFF
(CPT TO ACUI~

]
I

1
l

!
i
i
1

MONITOR FOR

[

ANS BACK (CPT)

|
]

*iN SOME ACU'S DLO TURNS ON BEFORE PND.

SET AFTER DSS ONTM 1§ PROVIDED

|
)
|
|

ADNLY IF DPTION “TERMINATE CALL WiA DATA

F2M DETECTED (DS}

os)

FIMRECEIVED |

LINE TO DATA SET

MON. F1M

{CPTTO ACU)

VIA DAS 8118

N OTHERS, PND 1 URNS ON BEFORE 01O

F2m SENT
0%

RECYCLES UNTIL LAST DIGIT IS OUTPULSED

»-

|
!

(ACU TO CPT}

(DAS 8118 TO CPT)

(DAS811B TOCPT)

OFF HOOK

OFF-HOOK

DPR OFF

i ol

TO ACU

PNDOFF

CE ON-OFF

(CPTTODASB11B) |

___________ i

]

MESSAGE

ANS .BACK
RECEIVED

t1-Q777

Figure F-9 811B Originating and Answering Flow Chart
for CPT for 3 or 4 Row TWX Service Data Set Tone Detection with EON

F-10

DH11 ASYNCHRONOUS 16-LINE

MULTIPLEXER MAINTENANCE MANUAL
EK-O0DH11-MM-003

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