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MAINDEC-12-D3GA-D

May 1970

129 pages

Original

5.2MB

Document:	PDP-12 Tape Control Test Part 2 of 2
Order Number:	MAINDEC-12-D3GA-D
Revision:	0
Pages:	129
Original Filename:	http://bitsavers.org/pdf/dec/pdp12/diagnostics/02_03_MAINDEC-12-D3GA-D_May70.pdf

OCR Text

IDENTIFICATION
PRODUCT CODI::

MAINDEC-12-D3GA-D

PRODUCT NAME:

P0P-12 TAPE CONTROL TEST
(PART 2 OF 2)

DATE CREATED:

MAY 1, 1970

MAINTAINER:

DIAGNOSTICS GROUP

AUTHOR:

JAMES KELLY

Page 1

ABSTRACT
The tape control diagnostics Part 2 is designed to test
all Controller Logic not tested by Part 1.

Specifically

this includes, Inter-Processor Signals, Tape Control
States and Instruction, Tape States, Tape Trap and the
Transfer of Data between the Computer and the Tape
Controller via the Data break facilities.

It should be

noted that Part 1 of this diagnostic should have been
successfully run prior to running Part 2, because Part 2
assumes th;::i.t the logic associated with Part 1 is functioning
normally.
2.

REQUIREMENTS

2.1

Equipment

2.2

A Standard Basic PDP-12

At least 1 Linc-Tape Transport

An ASR-33 Teletype or Equivalent

TC-12, PDP-12 Linc Tape Controller

storage
Thi~

program is designed to run in MemoryField ~ only and it

occupies virtually all of Field Ji1 not occupied by the Binary

and Rim Loaders.
2.3

Preliminary ~rogfams
All PDP-8 and 12 mode basic instruction diagnostics and
exerci~ers

must have been ~uccessfully rtin prior to running

the program.

Page 2

LOADING PROCEDURE

3.1

Method
This program must be loaded with the binary loader.

If you

are unfamiliar with the proper binary loading procedures refer
to Appendix A of this document, otherwise precede with the
following:
A)

Set the teletype reader switch to FREE.

Open the teletype reader and insert the program tape so
that the arrows on the tape are visible to and pointing
toward the operator.

Close the reader and set the reader switch to START.

Set the teletype front panel switch to START.

Set the left switches to 7777.

Set the tight switches to 4~~~-

Set the mode switch to 8 mode.

Depress I/O preset.

Depress start LS.

When the program tape has been read in the ACCUMULATOR
must be

~~~~'

if it is not, a read-in error has occurred

and one might try reloading the binary loader.
See Appendix A.
K)
4.

Remove the program tape from the reader.

STARTING 1 ;PROCEDURES
This preliminary set up procedure is critical and any omission
will .result in an error.

r·age 3

Set one and only one of the Linc-tape transport
number thumbwheels to ~ - on some transports the ~
position is actually represented by

Set all other transports, if available, to all different
numbers i.e. no two transports have the sunte unj t

111_·

IJo 'rRANSPORT may se to unit 1 as this number is us...:,,
generate a non-select signal.

Set the WRITE ENABLE switch on every transport to the
disabled condition.
tran~port

Set all

H.emovc any Linc-tapes

Set the left switches to ~2~~.

l~)

Set the right switches to ~~~~.
UOTE:

switches to OFF.
currently on the transport.

Setting the right switches to configurations

other than ~~~~ will cause the domputer to scope loop,
. halt oh error, and perform other options.

'I'hese options

are discussed later.

Set the MODE switch to 8 mode.

Depress I/O preset.

Depress START LS.

The program is running.
4.1

Cohtrol Switch Settings
A set of 6 optional mode switches consisting of right switches

0-6 has been included for the convenience of the test en9ineer,

they ·are:

Page 4

SROO
SROl

i·supprcss error halts

= 1 suppress type outs ring bell 011 error

SR02

1 scope loop on a failing test

SR03

1 scope loop on a non-failing test

SR04

1 unit does not have extended tape fields (unused in

SROS

1 suppress the bell

part 2)
SR06
1 suppress tiie pass counter.
The switches have an order of precedence associated with

thel"".

..,e'?'" •'."'al".pl.:., i:f the o!')tion

9~·~i tche!'=J T·~ere

set so

CflUCI~

a typeout and an error halt, it is obvious that the typeout
must precede the halt.

Right switch 00 if set to a one will

prevent the computer from halting when an error is detected.
Depending on the condition of the other switches, we may:
1)

go on to the next test after typing out a message

stay in the same test.

Right switch 01, if set to a one, will prevent the computer
from typing anything out and instead causes a bell to ring
at every detected error.

The purpose of this is merely to

inform the operator that an error has occurred and nothing more.
Right switch 02, if set to a one, will prevent the computer
from exiting the current failing test.
Using switches 00, 01, 02 several use full combinations of
error analysis present themselves:
SRO

SRl

SR2

Explanation

Type error data and halt

Ring bell and halt

Continuous typing of data with no halt

Ri,ng bell at every failure

Continuous typing of data in current test

Page 5

In general, an error halt is useful for scoping status of
the machine immediately following an error.
Right switch 03, if set to a one, will cause the program to
remain in the current test, so long as no failures ')Ccur.
Right switch 04, if set to a one, wi 11 cause the progra;..
not to test the extended tape field register.

(4K System)

Right switch 05, if set to a one, will inhibit the bell fr1.m
ringing.

Under normal operation the program will ring the

bell about once every 1 and 1/2 minutes.
::>.

MESSAGE

FORMAT

The message format is designed to yeild the maximum
possible information with the minimum amount of typing.
To that end the following format has been selected as the
best of both worlds; i.e., amount of information vs.
the amount of typing.
r::xample:
LTR

RWB

)JfJfJl

fJfJflfJ

$J!JfJ2

f"fJ{LffJ

LTR 2)

RWB

(VIA TB) Failed

The first item typed, in this case LTR, refers to the

logic page on which the logi0 which is being tested is
drawn.
unde~

In this case the message tells us that the logic
test is located in the (LTR) Linc Tape Register logic.

Page 6

It should be understood that the trouble is associated
with the Linc tape register logic but not necessarily on
the page

ref~renced.

For example, on this test the data

transfered may not have gotten from the computer to the
tape control or it may not have been read back properly.
Both of these problems would cause a typeout such as this,
indicat:i.img a bad register, when in fact, the trouble was
in getting data to or from a register.
AC RWB 3)

The second items typed AC RWB indicate that the

two registers involved, the AC, referring to the computer
AC, and the RWB, referring to the tape control read write
buffer, are involved in the test.
(VIA TB) 4)

The third item, enclosed in brackets, is a modifier.

In this example, the p~ogram is capable of loading the RWB
in one of three (3) ways, from the tape transport, from
the AC serially via a maintenance gate, and from the AC
via the TB.

Obviously three different trouble shooting

techniques are required depending on which of the three
data paths are bad.

The rnodif ier is this case points out

which one of three data paths failed.
FAILLD 5)

The word "failed" is typed to be sure the operator

understands that this message indicates trouble and is not
interpreted as a status report.
AC RWB 6)

The two registers whose data are shown are named on

the second line of the typeout to ensure that the operator
is aware that the data type out is AC and RWB and not the
TB.

Usually the registers involved do not have their names

typed out unless there is a possibility of confusion.

Page 7

~{JfH

fO!OfOJO 7)

The numerical datu type outs also in a

special format.
When more than one number is typed the first number is always
the source number.

In this typeout the

16/0!0l is the numl.•:?L

in the AC after the contents of the RWB
the AC.

were read back

n ':.

An engineer must always refer to this document and

locate the exact type in order to properly interpret any
message or data typeout.
6.

MONITORS
This program contains two monitors, and error monitor and a
non-error monitor.

The error monitor handles scope looping

on errors, message typeouts, and determines what data shall
be used in a failing test.

The non-error monitor is an

extremely simple subroutine whose only function is to allow
a test to loop continuously even when no error exists.
The following example will be used to illustrate a typical
coding sequence, involving the comparing of a true number
with the actual results of an operation.

TESTX,

'fAD

REGB

/Fetch Received data

CIA

TAD

REGA

/Subtract from sent number

SNA

CLA

/Were they equal

JMS

NERROR

/AC was eero, t:i1ey were equal

tJ )

JMS

ERROR

/Sent Data Received data unequal

GOOF

/Message TAG

HLT

/:Lrrnr

SKP CIA

/EXIT

10)

TE STX

/Scope Loop Pointer

/Negate

IIl~L'r

Page 8
The numbers shown in the left margin are for reference purposes
only and are not part of the coding.
The first three lines performed in order (1) fetch the
resultant of the test from "REGB".

This could have been any

memory register or any hardware register which can be read
under computer control.

The test data is converted to twos'

complement form (2) and subtracted from the correct results
(3) The test of the data (i.e. were they equal) takes place on
line (4) and based on this test we go either to the non-error
(NERROR) subroutine or if the ACCUMULATOR is not zero the
error (ERROR) monitor.

It should be obvious that any

decision making instruction can be used to ascertain which
monitor we hand control too.
~ines

(5),

Line (7)

(6), are the actual monitor calling instructions.

(GOOF) is the address of the first memory location

of the error message which will be typed out in case of a
failure.

Line (8) is an error halt.

If an error should

occur ru1d the switches are set so as to ·allow an error
halt this address will be the one at which it will halt.
Line (9) is an exit.

If an error halt occurs, pressing continue

will cause the computer to execute the skip and exit to the
next test.
Line (19) contains the address at which this test is begun again.
For example, after completing one pass thru this test routine
the monitors will execute an effective Jump
contents of line

(l~)

Indirect tlle

and redo this test routine.

Page

6.1

Non Error Monitor
The non error monitor has two functions.
increrttent "REGA".
4~96

count

The first is to

"REGA" is a cominan tally register usc,d to

passes thru a test and to notify the non-errr. ·

monitor via an "ISZ" loop when the required number of p< · :. _~
have been perfomned and thereby causing an exit.

The second

function is to examine RSW ~3 and if set, inhibit exiting to
the next test.
In some tAst.s, r·::.lr cicularly those associated with time delays,
or med1anica:i. de.lays it becomes prohibitive to make
4~96

passes thru a test.

To circunvent this it is possible

to preset "REGA" to "7777" so as to only make a single pass
thru a test, or any number of passes from 1 through
6.2

4~96.

Error Monitor
The error monitor is the major monitor responsible for all
modes of communicating errors to the operator.

The usage of

switch inputs has been completely discussed under part 4.1
control switch setting~ and, will not be discussed here.

Several

salient features of the error monitor are as follows.

The first

"scope loop on failing test"

(SR~2=1),

is designed to cause

the monitor to inhibit incrementa.tion of "REGA", and to inhibit
the advance of the random number generator.

An example of its

use might be in testing any of the 12 bit registers.

Assume

tha.t bit ~O can never be set to a one because of some as yet

unknown hardware error.
first time the number

This malfunction will become known the

4~~~

is loaded into it because the read

back will show ~~~~ - normally the next number to tried will be
4~fH,

4~~2

etc. with each being typed out and each causing

Page 10

different data to be

t~ansferred.

To facilitate scope testing

of this problem, we must eliminate type outs and prevent the
data from changing.

This is easily accomplished as explained

under switch settings.
An error message is always formatted such that all of the non
numeric characters are typed out first followed by the numerics.
'rhe contents of some memory register, other than those selected

by the programmer, may be of interest to the field engineer.
For example, in a random data transfer test it is impossible
to determine the number of successful data transfers, because
only the errors are typed out.

Lets presume that the engineer

wishes to type out the pass counter i.e. "REGA" memory
JfJJ4.

addr~ss

It is necessary to modify the message type out string

as follows:
BEFORE
GOOF,

AFTER

lfOll

f&f&Jl

GOOF, f!Yf(JfOl

fJJJl

12[&3

~n~J3

1213

{iJ2J3

EX I TA

7777

EX I TA

7777

REGB

lfJfiJ5

REGB

lfJl5

REGC

llf06

REGC

fJ{JfJ6

EXIT

fHHJJ

REGA
EXIT

,,,4
fJfJ ' '

The following shows the before and after type out.

ABC 7351 735[0

ABC 6773 6253 Jl37

The type out on the right shows the contents of the pass counter
and will indicate if all random numbers failed or if only some
of them

f~ile~.

It is absolutely necessary to restore the

Page 11
toggled in modifications to the message type out in order
to prevent erroneous type outs in other messages.
7.

MAii~TENANCE

INSTRUCTION SET

M.NEMONIC

CODE

MODE

OPERATION

LMR

6151

PDP-8

Load maint0nance
register

AC
~

TO MA INT INST REG

TO MAINT INST REG

CLEAR TAPE DONE FLOP

SKIP ON TAPE DONE

GENERATE A SIMULATED TTO, TTl, TT2, PULSES

GENERATE A SIMULATED TT3, ·rT4, PULSES

SIMULATE MARK INPUT

SIMULATE DATA 1 INPUT

SIMULATE DATA 2 INPUT

SIMULATE DATA 3 INPUT

rO i'·L:UNT INST REG

Bits /J,,1,2,3
The contents of ACCUMULATOR bits

1, 2, 3, are loaded as a

commaqd into the maintenance instruction register.

The command

will be executed if and only if the XFR IOT {6154) is generated;
tiw function of these commands are discussed later.

Bit 4

EXecuting the LMR command with'AC bit 4 Ef@t will unconditionally
clear the tape done flag.

Page 12
Bit 5

Executing the LMR command with AC bit 5 set will cause the
computer to skip the next instruction in sequence if the
tape done flip-flop were set.
Example:

CLA CLL

/Clear AC,

TAD KJHS¢

/Set Bit 5

LMR

/IOT 6151

HLT

/Tape done was zero

HLT

/Tape done was one

It should be noted that these commands are not designed to be
microprogrammed; for example, setting both Bit 4 and 5 and
executing LMR in an attempt to SKIP and clear on the tape
done flag is unwise.
uit 6
Executing the LMR command with AC bit 6 set will generate in
order the timing pulses TT¢, TTl, TT2 regardless of the state
of the tape control logic.
Bit 7
Executing the instruction LMR with bit 7 set will generate in
order TT3 and TT4.

It should be noted that to generate an

entire timing stream consisting of pulses TTS, TTl, TT2, TT3,
and TT4, it is necessary to generate TTJ, TTl, and TT2 first
followed by a serpond command to generate TT3 and TT4.
JJit 8
Ia usQd to

s1'.mul~te

9, lS, 11 below.

an input to the mark window, see bi ts

Page 13

Bi ts 9, 1,0, 11
ExGcuting the instruction LMR with data in AC bi ts 9,

l~.,

will simulate reading data of the data heads into the Readwrite buffer.

This feature is useful in testing the tape control

without a transport.
TRC 615-2

PDP-8

Tape Register Clock

Generate tape preset

Shift RWB once left with no end around
carry

Transfer TB to RWB

Add TB and TAC place the results in TAC

.0 Tape word flip flop

Set Forward

Set unit 1

Set Backward

Set write sync flip flop

Set 8 mode tape motion

1,0

Select 8 tape mode

ACll

LTP8 Write if ACl{J is set

The tape register control command TRC (6152) in conjunction with
selected bits in the AC can perform a number of direct nonconditional operations.

Several of tl1.e commands are useful

primarily for logic testing the rest although·they are tested,
are used in normal machine operation.

Page 14
Bit ~:
Executing the-. command tape register control TMR (6152) in
conjunctioh with AC bit ~ set to a one generates the internal
signal tape preset.

Tape preset, in general, sets all control

flops to a null state, which may be either a one or a zero.
Bit 1:
'11 MR

in conjunction with AC bit 1 will cause the Read-write

buffer (RWB) to be shifted once to the left, observing it from
the computer accumulator, or once up on the logic drawings.
Data shifted out of RWB is lost and a logic ~ is shifted into
the low order bit.
Bit 2:
TMR in conjunction with AC Bit 2 will cause the contents of the
TB to be copied into the RWB.

The previous contents of the RWB

are lost, the TB remains unchanged.

It should be noted that the

only path by which the RWB may be loaded in parallel is via
the TB register.
Bit 3:
AC bit 3 causes the contents of the TB register to be added to
the contents of the TAC register, with the resultant being
retained in the TAC.
Example:
BEFORE
TB = 7321

TB =7321

TAC = ~412

TAC = 773

ait- 4:

Clear the tape word flip flop.

This bit generates an

unconditional clear.
Bit 5:
S2t forward.

The direction flip flop is set to a one

unconditionally.

This command is useful for diagnostics.

clit 6:

Set unit 1.

When executed this command will select tape

transport unit 1.
only

~elect

unit

It should be noted that this command can
~ ,

if the extended transport select register

(part of extended operations register bits lf, 11) are set
to a zero.

If the extended transport select register is

not zero, the appropriate odd numbered unit is selected.
Bit 7:
Set Backward.

The direction flip flop is set to zero

unconditionally.

This command is useful for diagnostics.

Bit 8:
Set write sync.

This command unconditionally sets the write

sync flip flop.
Bit 9:
Set 8 tape motion is used with the TC12-F option.

This opt:.on::

allows the reading and writing of tapes written in PDP-8 Linc
tape format.
Bit lf:
Set 8 write selects 8 tape mode.
Bit 11:
Sot LTP8 write, AC bit 11 is provided as a data input to the 8
tape write flip-flop.
into the flop.

If AC bit 10 is set, the bit is clocked

Page 16

XFR

6154

PDP-8

rrransfer

Maintenance register
AC to TB
AC to TBN
AC.tb TAC
11

AC to TMA

TMA setup to AC

TBN to AC

TB to AC

RWB to AC

Mark window to AC

States to AC

Units and motion to AC

Tape instruction register to AC

Misc status 1 to AC

Misc status 2 to AC

TMA to AC

Unused, returns all zeros to AC

In general all data transfers into the AC using maintenance
conunands are l's transfers, that is,.they do not clear the AC
prd.or to inserting data.

All data transfers from the AC into

tape control register are jam transfers.
in a tape control register is lost.

Any data which was

~f1

/;C to TB

'J.'l11.! curr<!llt

contents of the AC are transferred into the 'L,

(rl'ape Buffer).

'l'he AC data is unaffected the previous

contents of the TB are lost.
,0'1 AC

to TBN

The current contents of the AC are transferred into the TBN
(Tape Block Number) .

'rhe AC is unaffected, the previous

contents of the TBN are lost.
10 AC to TAC

The curi.L. :.

. .~ents of the AC are transferred into the TAC

(Tape Accwnulator).
of the

TAC are

The AC is unaffected, the previous contents

lost.

11 AC to TMA

The contents of the AC are transferred into the TMA (Tape
Memory Address) •

'I'he AC is unaffected the previous contents

of the TMA are lost.
2~

TMA setup to AC

The contents of the TMA setup register is "OREO" into the AC.
The contents of the TMA setup register is unaffected.
21 TBN to AC

The contents of the TBN register is "OREO" into the AC.
The contents of the TBN are unaffected.
3~

TB to l:,C

•1 hc contents of the TB register is "OREO" into the AC.
1

The

contents of the TB is unaffected.
31 HWB to AC

The contents of the RWB (Read write buffer) is "ORED" into
the AC.

The contents of the RWB are unaffected.

Page 18
4~

Mark Window to AC

The contents of the tape mark window and its associated
mark decoding gates are "OREO" into the AC.

The contents

of the Mark window register is unaffected.

The data format

is as follows:
AC
~~

Window shade

Windo·.;

Window ~l

)13

Window ~2

)14

Window ~3

End Zone mark

Check mark

Guard mark

)18

Data mark

Final mark

lfJ

Block mark

Intermediate zone mark

41 States to AC
The contents of $everal flops and the levels of several
gates are "ORED" into the AC. Reading the data does not
affect its state.

The data format is shown below:

fJfJ

TAC = 7777

)01

IDLE Mode = 1

)02

Search mode

)03

Block Mode = 1

Y14.

Ch~ck word mode = 1

Yf 5

Tu in around mode = 1

.06

Wr:'.te f .~op

fJ7

Write cycle flop = 1

[48

Acip delay not timed out

!09

Tape timing OK

lfO

Timing OK gate set

Tape fail delay

5JO; Uni ts + MTN to AC
The data concerning transport selection, I11ot.\on, direction, unit
select, and write enable is "ORED" into the AC.
AC

UNIT fJ

Selected

UNI'l' 1

Selected

fJ2

UNIT 2

Selected

f03

UNIT 3

Selected

µ4

UNIT 4

Selected

UNIT 5

Selected

-'f

Page 20
~6

UNIT 6

Selected

UNIT 7

Selected

MOTION FLOP

DIRECTION FLOP

UNIT SELECT

WRITE ENABLE

Bit

(1)

Unit Select

This bit indicates that one and only one unit is selected at a
time.
51 TINST to AC
The contents of the tape instructions register decoder, the
I bit and the group register are transferred to the AC.

The

contents of these datum are unaffected; however, the previous
contents of the AC are lost.
AC
~~

RDC

RCG

ROE
i

MTB

WRC

WRE

WRI

CHK

I BIT

GP~

GP 1 (l}

GP 2 (1)

(1)

Page 21
6~

Misc Status 1 to AC

This conunand transfers the status of several important levels
to the AC.

The f::,rmat is shown below:

P~iAS~

!61

PROGRESS FLOP (1)

f62

f6f6 (1) Line Counter

f61 (1) Line Counter

MARK CHANNEL WRITE

f65

DATZ\ CHANNEL 1

f66

DATA CHANNEL 2

f67

DATA CHANNEL 3

f68

GP CNT = GP FLOP

f69

GP CNT f6 (1)

GP CNT 1 (1)

GP CNT 2 (1)

GATE

f:il Misc Status 2 to AC
Bit f6 of the Ac. is set to a one if the LTP8 tape select
flip-flop is set.
7~

TMA to AC

The contents of the TMA register is transferred to the AC.

The

contents of the TMA are unchanqed,the origin.al contents of the
AC is lost.
71 Unused

Page 22

General Information
This program will test the PDP-12 tape control logic on a
gate by gate basis.

This was made possible by including a

16 instruction maintenance register in the basic desing.
The line tape maintenance register (LTMR) facilitates
examination of all major registers and the majority of status
bits, control levels etc., associated with the tape control.
It is usually possible to isolate the fault to no more than
one or two modules by analizing the diagnostic type out and
referring to the appropriate logic diagram.
This program is written in several major and minor sections
designed to point to a failure on an appropriate page in the
logic drawings.
1)

The four major sections in order are:

Test out, in so far as possible, the maintenance logic.

includes the maintenance mode

This

flop, maintenance instruction

This group of tests are a

necessary preliminary diagnosis in order to be reasonably
certain that the following tests fail because of

logic failures

and not because of failures in the maintenance instruction registez
2)

Test out the 12 bit registers TAC, TB, TMA, TMA setup, RWB

and TBN.

Two tests are performed on each register; the first

test is a binary up count sequence; the second a random number
sequence.

The binary sequence ascertains that all flops can be

both set to a one··and set to a zero.

In addition it also proves

mutual independence of the data paths i.e. the flops can move
independently of one another and the input and output data paths

Page

a::e not shorted in any way.

The random number test causes

each bit of the registers to toggle at a relatively high speed,
in contrast to the binary sequence wherein only the low order
bits toggle at high speed.

A second useful effect or the

random number sequence is that it leaves the tested tegister
in a random state, a technique sometimes useful for discoverin'.:;
grossly illogical wiring errors.
3)

Test all minor registers; i.e., registers with less than

12 bits.

These include unit select registers, mark window,

extendetl

__ tions register, etc.

In this series of tes~ an

attempt is made to diagnose all flops and all sequenceable
flops such as the major state generator.

In most cases random

number tests are not performed due to the fact that an unknown
state in any control flop might have an adverse affect on the
succeeding tests.
4)

Test all gates using as many as possimle input combinations.

Fo~

example, :'..ll.ND ·gates are first tested with all inputs true to

determine if the gate will function.

Next each individual input

is set false in turn to see if each input is expressed in the
output.

OR gates are tested by allowing at least one input and

maybe more to become true and monitoring the output for a true
condition.

This is followed by setting all inputs to false

monitoring the output for false, followed by setting each
input in turn to true and checking the output.

Page 24

A significant number of gates in the tape control can not be
directly tested tape state logic TC12-~-LTS, for example.
'l1hese untest.able gates are evaluated indirectly by logical
deduction; i.e., all testable inputs to these gates are tested
as inputs to

other gates.

An example:

Block mark (BM) is a functional input to the LTS logic.

previously stated it is extremely difficult to prove that a
correct (BM) appears at the LTS logic, however, it is each to
prove that a correct

(BM)

signal itself is functional, that

other gates using the (BM) signal function, and that the
(BM) signal is not shorted, either to logical low or logical
high.

The technique used to circumvent the apparent difficulty

in testing multilevel logic is as follows:
a)

Attempt to set all inputs to a group of logic to a state

which will cause a true output at some software observable point.
b)

Attempt to disqualify the output by causing one input at a

time to change to a state which will cause the output to
become flase.
c)

In many cases a gate will be qualified or disqualified,

as the case may be

for a specific period of time regardless of

what the diagnostic program does.

An example of this is any

gate whose inputs are a function of tape delays.

The following four (4) error messages ar::i ~. . ssociated with tests
of the :

'l'APE DONE FLOP

LIP TAPE DONE FAILED TO SET
The LIP TAPE DONE M216 C31 flip-flop failed to set.
The tape done flop is set by toggling the progress
flop from a 1 to a

This test is accomplished by

setting progress via MTP Setup, clearing progress via
MTB, BM, ACIP-NOT and TP2, and testing the TAPE DONE
flop via the TAPE SKIP Maintenance Instruction.
LIP MTP SETUP FAILED TO CLEAR TAPE DONE
Th~

signal, MTP

flop.

6ETU~,

failed to clear the Tape done

The tape done flip-flop was set as discussed

above, and cleared via direct clear input, by MTP
SETUP.

The results are checked via the TAPE SKIP

Maintenance Instruction.
LIP TAPE PRESET FAILED TO CLEAR TAPE DONE
The signal,TAPE PRESET, failed to clear the tape done
flop.

The tape done flip-flop was set as discussed above,

and c1~ared via direct clear input, by TAPE PRESET.

~he

results are checked via the TAPE SKIP Maintenance Instruction.
LIP CLEAR TAPE DONE FAILED
'I'he signal, CLEAR TAPE DONE, failed to clear the tape done
flo~.

ihe tape done flip-flop was set as discussed above,

and cleared via direct clear input, by CLEAR TAPE DONE.

The

results are check via the TAPE SKIP Maintenance Instruction.

The following three (3) messages are associated with the Linc mode
coromand STD, STD i and Tape interrupt .

. . . IP STD FAILED TA.PE DONE :::: 1
The Linc' mode command STD (¢416) failed to SKIP or STD i
(~436)

skipped in error when the TAPE DONE flop was on a

LIP STD FAILED TAPE DONE = ¢
The Linc mode command STD !.(¢436) failed to skip when the
TAPE DONE flop was on a ¢.
,.IP

TAPE INTERRUPT FAILED INT ENB = l
The tape processor failed to cause a tape interrupt.

The

TAPE DONE flop and the INTERRUPT ENABL~ flop in the extended
operations register were both set to a 1.

The

follo~ing

eight

CS) m~ssages are asco .1a.Jd with tests of

the PROGRESS and IN-PROGRESS flops.

Spncifically whether

MTP SETUP sets the flops and tl.l::i:L the clock input g :.~ting will
zero the flops.
LIP M'1'P SETUP FAILED TO SET IN-PROGRESS
A non-paused tape instruction was executed to set the
IN-PROGRESS M216, Dl9 flop.

The resulting state of the

flop is checked by reading it back into the AC, bit /Jl
via a Misc status 1 to AC Maintenance Instruction.
LIP TAPE

PRESET FAILED TO /J IN-PROGRESS

The IN-PROGRESS flop was set via a non-paused tape instruction
then cleared via a TPAE PRESET.

The resulting state of the

flop is check by reading it back into the AC, bit /Jl via a
Misc status 1 to AC Maintenance Instruction.
LIP LCS (MTB * BM * SEARCH) FAILED TO ~ IN-PROGRESS
The IN-PROGRESS flop was set via a non-paused MTB tape
instruction.

The Mark window was loaded to BM (16) and a

simulated TPl pulse was generated to set search mode.

The

transition from IDLE mode to SEARCH mode.
LIP Mll5 C25 PIN S2 FAILED TO /J IN-PROGRESS
The IN-PROGRESS flop was set by a MTP SETUP and an attempt
was made to clear it via END INST signal which is generated
by

qate MllS, C25, PINS N2, P2, R2 and S2.

LIP END INST FAILED TO ~ PROGRESS
The progress flop was set by a MTP SETUP and an attempt was
made to clear it via END inst signal generated as discussed
in the previous type out.
LIP CHK OK FAILED TO

PROGRESS

The progress flop was set by a MTP SETUP and an attempt was
made to clear it via CHK OK generated by Mll9 C22 PIN P2.
The resulting state of the progress flop is detected by
examining the TAPE DONE flop to see if the transition
of progress to a zero did in fact set TAPE DONE.
LIP Mll3, Cl6, Hl WRITE CYCLE (yJ) FAILED TO ~ IN PROGRESS
This test as in the previous test ascertains if the signal
LIP CHK OK can in fact

the in progress flip-flop.

In this

case the ±nput to g~te Mll3 Cl6 PIN Jl is disabled i.e. LIN
TINR 9 {l) and LCS write cycle (yJ) PIN Hl is true.
LIP STW FAILED TAPE WORD = l
The tape word flip-flop is tested by the Linc conunand STW
(457)

and STW I

(477).

The tape done flop is kept in the

one state during this test.
LIP STW FAILED TAPE WORD = yJ
The tape word flip-flop is tested by the LINC conunand STW
(457)

and STW I

(477).

The tape done flop is kept in the

zero state during this test.

LIP TAPE WORD TOGGLES FAILED
The Tape Word flop failed to toggle as the result of the
action of line counters LC~l, LCfOfO on the clock and data
inputs.
LIP DATA BREAK FAILED
JJ116

~~~~

nroro

The DATA BREAK facility has failed.

The first number typed

is the address in memory which was referenced by the tape
control this is always address {0176.

It was necessary to

use a fixed address rather than all addresses because almost
any error in data break will wipe out the controlling program.
'l'he second number typed is the data which was transferred from
the tape control to the computer.

The last number is the actual

number received.
l..CX

MARK FLOP

~~fOro rororo~

An attempt was made to set the mark flip-flop.

The first

number typed i'ndicates the data sent to the extended operations
register this number is either •fJl/f'fOfO or f02fl~.

The second number

typed indicates the status of the mark flop as read back from
the ·extended operaitions register this number also is either
·fJ~~fO

or f02·fO'fO.

'rhis error may als·o indicate that the operator

fai.Lt;d 'to set the mark key.

LCX MARK FLOP TAPE PRESET FAILED
~~~~

An attempt was made to clear it

The mark flip-flop was set.
via a tape preset pulse.
LIN TAC=7777, DIR= REV FAILED

The program attempted to set the tape control major state
generator to the Blcok state.

In order to go from Idle to

search to block, it is necessary for the TAC register to
equal 7777 and the direction to be forward.

In this

case we have purposely set the direction flop to a reverse
condition so that the major state generator should be inhibited
from going from search to block.
~IN

TAC = ~~~~ DIR = FWD FAILED
Same as the previous test except that we are testing to see
if TAC not equal to 7777 will inhibit going to the Block
state.

LIT MARK CLOCK FAILED TO GENERATE TP3

An attempt was made to see if the mark clock can generate
computer timing.

The

LC~l

Line counter is on a zero, the mark

window is set ot a Block mark, and sufficient time is allowed
for the mark clock to generate TP3, TP4 to set LC~l.
will fail if the mark key is not set.

This test

i,CS IDLE

SEARCH FAILED

An attempt was made to change the major state generator
transfer from idle to search.
LCS SEARCH

BLOCK FAILED

The major state generator is ihitially set to Idle.

routine is executed to set the generator first to search
then to block.

The primary test is from search to block,

because the Idle to search has already been tested.
LCS SEARCH

TURN .AROUND FAILED

An attempt was made to go from the Idle to the search, to
the turn around major state.
LCS TURN AROUND

IDLE FAILED

The major state generator was set to the turn around state
as in the previous test.
to IDLE was made.

An attempt to go from turn around

The gate MllS A32 PIN H2 was used to

generate the timing to cause the transition to the IDLE
state.
LCS BLOCK

CHK WRD FAILED

The major state generator was set to block mode in a manner
similar to the search Block Test previously discussed and
a~tempt

was made to;go from Block to CHK WRD Mode.

LCS CH. ~

IDLE :;: ,'.~II·ED

J;UJ

•rhe major state generator was set. to CHK WRD mode and
attempt was tnade: to Idle mode via gate Ml6,0, B29, PIN
V2.
LCS SEARCH

IDLE (MTB+I) FAILED

The major state generator was set to search mode with the
(I) bit set.

This test tries to set idle mode using LIN I

(1) and LCS MTP END at gate M16,0, B29 PINS Vl, U2 and V2.
LRL; LRE; EN TAC, EN TB, OR LOAD TAC
This. type out indic;:i.tes an error in the function TB+TAC
to TAC.

The adders and this function have previously been

tested using the maintenance logic in tape control test PART 1.
We can therefore_ preaum.e that the trouble on}.y occ.urs when
the controller

performs under its own control.

names typed out indicate the suspected logic.

The four (4)
The three (3)

numbers typed out indicate in order the contents of the TB,
TAC and TAC after the addition has been pe.rformed.
LTS PHASE GATE FAILED
Each of the two gates which generate the PHASE signal a:re
tested individual1y first with both inputs false. then with
each input set true in turn.
and LC,02.

The two inputs aansist of CffK WRD

:UWN MARY v·nJ..'fE GATE FAILED

The mark write test is similar :in J1d.nciple to the phase
gate test above .
.LTR DATA CHAN'FE:L RWB fJ, 4, 8 FAILED
421)3

~16fJ

The Data channel output from the RWB was tested and failed.
Bits fJ, 4, 8 of the RWB are alternately set to all ones
then all zeros.
set to ones.

The first number typed out shows bits fJ, 4, 8,

The second number shows them as they are read

back via the data channel on bits 5, 6, 7.
LTT MARK CLOCK FAILED 'i'O GENERATE TPfJ

The timing logic is tested to ascertain if the mark clock
can generate TPfJ, TPl, TP2.

The results are detected by

determining if TP2 will set the GP=GPC flip-flop.
LTS LINE COUNTER FAILED TO COUNT

nfJfJ
The 3 Line counter flops were set to all ones an attempt was
made to ripple a carry thru it i.e. set is to all zeros.

The

nwnber printed in bits fJ2, fJ3 indicate the value of LCfJfJ,
and LC."1.
LMU TURN AROUND BM FAILED TO fJ MOTION
~he

motion f lip-f lo~ was set via a Linc tape instruction.

TllC:.:: .rt..i.jor state generator was set to turn around the window
to block mark and time pulses fl, 1, 2 were used to try to clear
the motion flop,

Ll1U TAPE PRESET FAILED TO ~ MOTION
The motion flip-flop was set as discussed above.

An attempt

was made to clear it by generating a tape preset.
LMU CLR PROGRESS FAILED TO ~ MOTION
The tape flop was set an attempt was made to clear it using
CLR progress.

CLR is made up of MTB, I

(ft1) and BM

LRR 'rP3 FAILED TO SHIFT R~lB
%%~%

ft1%%ft1
The RWB was set to the value of the first number typed.

TP3 pulse was used to shift RWB.

The second number is

the resulting value of the RWB.

It should be noted that the

shift logic i.e. the logic which handles the data which is
being shifted has previously been tested.

So a failure will

be indicated by no shifting rather than bad data.
LRL EN WR!TE LD RWB FAILED TO SHIFT RWB
~~ft1~ ~ft1~ft1

A test of the RWB shift logic has failed.

The two numbers

indicate the before and after contents of the RWB.
LRL TB+TAC=TAC FAILED
~~~ft1 ft1~~¢ ~ft1ft1~

¢¢ft1ft1

The add function of the Tape processor is tested.

The numbers

typed are in order TAC, TB RESULTANT and the resultant as
computed by the central processor.

LRL LOAD TAC FAILED TP3, SEARCH

ft1J:Jn
The TAC register was set to 7777.
was set to search.
generate.

The major state generator

TP3 was used to try to clear TAC ie.

L02\D TAC with no data on the BUSS.

The number

typed out indicates taht data which was left in the TAC
after the transfer.
LCS WRITE CYCLE FLOP TEST FAILED
The write cycle flop was both set and cleared with the result
read-back and t~sted after each change.
LTS TIMING OK GATE FAILED
The timing OK gate failed to indicate that all machine
timing·was OR after the program had set all inputs to the
timing OK gate to true.
TMA failed to increment during tape break

was

A tape break was eiXeC'l,1.ted; at the completion of the break cycle, the
TMA was not equal to the previous address plus one.
TC12-Part 2 Pass--(PASS)
The octal number indicates the number of completed passes executed
since the last 11 Start 2[4".

1P~a
1

2
3
4

5
6
j

8
Q

h_.£ CONTROL TEST PART II 1 MAIN.Ol:C U•D.~GA•L
IPOP•ll TAP£ CONTROL TEST PART Jla MAlNDEC 12.w03GA·~
/COPy~ICHT 1978, DlGttAL-t~Ut~MENT CO~P,, MAYNARD, HASS,
I

/AUTHOR& JAMES K£L~Y
I
.
/THIS PROGRAMt OPERATING IN BOTH 8 ANq LINC HOOE.
/IS OESJGN&D TO COMPL.ETE CHEC~OUT or TME POP•11
/TAPE CONTROL LOGIC, TAP£ CONTROL TEST PART J
/MUST RUN SUCC~SS,ULLY PRIOR TO EXECUTION OF PART II

/THIS PORTION~
I
/SPEC.1.A.J. l NS' ~\J.CTl.ONi'

I
I
I
I

,,tMOVE J. IN.CUPU FROM A'-'L. OR l VU

2, · S.tT TROHlPORT THUMBWMe;tL..S T~O "O'F' I. IN£"
3, IET TRANSPORT S.~\,Ef;T SW l.TCH..U TO "O~F'"
4, DEPRU.S A~O HOL.0 T"iE M4RK ttl:V

I 5,

110 P~tStT tO 8 HQDE

I 6, DE·PRESS START 2. t
I
/THE !EST IS CONTROJ.. '-ED .BY A HON UOR ~i:S l..O.tNT

/lN PAGE 24, O'TIONAL SETTINGS ARE AVAl,1.AJt.E
,,OR HaD!F'lCATICN or'tRROR-CONTA.OL·.
I

/SWITCM SETTlNOSI
I

/RSWS~•11
/RSwe1~1.

~NORM~LLY ~118)

INHIBIT tRROR HALT,
INH18lT £R~OR TYPEOUT.

/RSW0~~1. sco~E LOOP ON ERROR;
/ASW0h1, SCOPf; .L.OOP ON NONE:R~OR,

/RSW0'•11 !NH(llT ·$£~Lt
/RSW0~•11

INHIBIT PA$,S _COUNTER

TY~Eour.

/AT THE COM~~ETlON or A PA~s, THE CON!£NTS
/OF THE PASS COUNlER WILL aE TYPtO puT,

I
I

3?
4~

41
42
4.S

45
46
47
48
49
5~

51
52

'~
54

,,,6,8
55

0001
,,02

•1

0900
4000

RETURN, HU
40U
K•0001

0015

0250

0006
00217

02'"
74211

0~17

0001
0002
0003
0004

~~00

7400

K~'Hl'
K121250•

K14101
K~~17•

RETURN

3401

"~17

/COMMAND IOENTlric•TlON

6;•1
9900

7717

0002

L.INC"~141

UtTllU"
EX IT A!177'1
PDP•0"12

61'2

U4R•6~'1
TRC11161!2

0-116

$TO•S!J.6

6ih
6154

0i11

)('lt•6;,.

COH•S~S.7
A>C0•'1J~IU

'~
6!

21@81

eH3

TACIS,13

21~~1

Cl.R•0!U

64
6$

0H4

61
62

JMP l

1~57

0"21

STW1110411

XOA•0B21

nr·e~e•

1P••;2 TAJ:I: CQNT~,OJ. TJ.IT PAR! JI' MA.lHDIO U•DJGA~1...
6~

67
6~

0"10
0010

•UI

0~00

PINT1

0"20

•20

"~""'

69
70
71
72
73
7 •,

0021

76
71

0026
0027

61'2

7i::l

0030

79
80

1200

121031

542,

00.32

3134

H3J
H34

:&016

3144

K~-16'
L.OAOR1

L.CADS

0035

eS40

K08401

0148

K01S2•
K016fh

11.12

ei
8~

85
86

9!'
91
92

93
94
95

21020

0022

0023
0024

0025

0036

7300
306'
5423
~177
0000
01Z100

eU7

5i21

1840
H41
H42
H43

0002

0044

0045
21046

JMP I

die

'IH

3"40

5216
0000

7000

lRC

,JMP l

MAINn, MAJ NT~

K,2181

KHH•
RAN,
REGE,

Kaus,
K70~0,

K70301

0051
0052

1771
3334

K7777 •

0053
0054

4140
711~
0100
k'200
k11'0

ui
102
U3
104

11215
106
Ull

109

0055
0056

0057
006121
0061
0062
012163
0064
0065
0066
0067
0070

04s0

3027
1~~2
3133

5054
0000

M4444 •
K414ih

::001
;;·141
;-:.ANDOH
00H
7090

71311

r11;

e4444
4140
7770

Kt~U01

01ru1
0200

K02001
K~150•

PNTA,

PNTB 1
PNTC,
PNTJ,

01,'0

L.OCA

WRCF'L,8

1..occ

L.OCJ
OUTPAS, ASC 11
0H0
PASS,

2000

K20~H~,

2000

6040
6000

6el40
6000

K·d~I?? 1

0077

111

0071

100~J

04~0

ll~
11~

0072
0073
0074

l!J077
7740

M40,

e.+o~
~ti•

K777i,,

K60401
K6000•
K1000•
K ~~ 400 1

11~

0~16

N£RROR 1 NtRRO·~
£RROR• ERAORI

7030

0000

Cl.A

1~00

0400

. . ,0

.......,.

~···. •.•· ~

. ..t.!.'f ~-t

YPEPRE

•• : • . . .

,•...•. PAIE

/THIS LOCAT!ON MAY POINT TO ANY TEST
ITME 9PERATOR CESl RES

ClA CLL C'MI. R~~Pf: p~~ s~-t

0047
<.?1050

,•1

1,.STEAR, UH
TPEPR~,

vi~i

/START 20

0177

7330

5000

CL.A CL.L.
PASS
DCA

PAj.11

:~"

)
')

lP~.~.;,~z .TAjE. -OC:NT~OL.
115
11~
U7
116

119
120
121
12~

123
124
12~
120

0075
HJ76
0077
0Hl0
0101
0102
0103
CH04
~105

TUT PAR! tt. HAIND!C 11•03GA•L

0240

K240, . · 2~0

7774

K77741

1026

K10261

0215

K0215'

0212

KQl2121

0117

!5200

0201
52!0
0000

K01 ?7 •

8£1.LAt
K02071
TVPE,

SPACE•

12~

0106
0107
0110
0111
0112

130

0113

e000

131

0H0
00013

R£G01

13.S
134
13~

0114
0115
CH16
0117

R£GC1

13~

0120
1121

0000
0H0
0'1100

137

1122
0123
0124
0125

127
12~

132

13~
13~

140

141

0050
0020

1<00201

7173

K77731

8@~0

0~'16

K"050r
K~~UJ•

TEMPS•

REGA,
REGB,

0?15

BELi.

0207
TYPOUT
0000
0050

0s20
7773

0'1"
0010
HH

""""
HU

0001

REG,,
00111
L.IAH!, LilH!
4441
31111

7~00

K37H1
H04H'

,99419

'1000

MlBHt Riue
DEi.AV•

0~00

IH26

0~00

143
14~
H5

0127
U30
0131

1162

TAO
OCA

3025
U24

OCA

K1137

TPEPRE

I.STERR
l.STERR

146
147

fHJ2

2024
5132

JMP

14~

01~3

0134
0135

lSl

TPEPRE

0136

5526

JMP
JMP

OEl.AY

0137

0p1

l4Y

150
15~

a~-s~P·1•

0212
U77

K4~48r

142

v~u

1714
1026

4440

3700

P~L11

l Si!

2~25
51~3

K171,

177

• "1

/GET TALLV
/SU TALl.Y

/I 1.A~T ERROR
/WAIT

/WAIT

1 s2

/WAIT

roR ACIP TO TIME OUT

uast

PAGE 4

,,,,.11 f AJE ceNt~o~ T!JT 'A•T u, MAINO!~ 11•031A•L
152

U40

1'3

"14~

15~

0Hl
0142
"143

15~

157
15~

0144

161

'11145
0146
0147
01'0

163

0151
0192

159
160
16~

•140

7117

?717

5543

JMP 1
LOCTRP

pOp

0e02.

3105

c0050,

1~00

K1~00•

0013

J6'00

1(011!13,
K 3 0 £If!"

0H0

0eu
1100

Mv.:>1001

7600

M20001
M02001

6000

01H
1154

0•11

01'5

6120

1~il0

3H0

"~100

.. iue

·"221"
HU

3'~0

K00111
K;'S440 I

167

•1,6
lli7 ?940

0187

169

0161

"""'
0ii2

K01J071
K78401

d12

110

0161
0162

?737

3"20

Ke.012 I
K30201
K7737 •

0803
3420

Kl4201

''"1

RNA,
RN8,

16~

16!:>

a6
16~

171
172
113
174
115
116
11'1

17~
17~

1163
1164

8165
116~

3~27

1167 -.... eete
8171 0116
0111 7~56
"172 2224

.PAl.1'

K6i201

K~'113t

Kl4271

Cil1761

3440

6iae
7141

3020
77J7

0113
:s~2a

3417

eeu

0mee

0116

K73561

7~56

LWA10~,

L.W910~

'. 2.

/P MOQE
/EXIT

V1'1

2••stft•71

i'•"

PAGE 9

1PCP~12

hit CONTROL.. JH'r ,ART 111 HAINDlC 13·0~GA•L

18!
le~

182
183

0p6

•176
LOC17~,

18~

0176
0177

1777

185

8200

4503

18~

18?
1a8

8201

44~4

4126

197
196
19~

9287
•210

210
211
212
213
21~

205

206
21?
288

219
21~
211

?330

0224

0225
0226
1227
8230

TAO

I.MR

/WUT F'OR AClft

6141

L.INC
1713

9@02
1033

TPEPRE
KUIH

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SNA CL.A

0056
7~50
4436

44H
6347
?'4k'2

L.WB10,,

/NOPE ERROR
IGE'\J TP3
;READ STATUS

SNA CL.A

f 056

/SAVE MARK WRITE

/DID IT SET

/LOAD MAINT R E:G

LMR
CLA CLL.

.,34

1377
1378

i36~
1369
137"'

L.WA104
1(6020

2215

2204

> EVERVT H 1''I G ~· TO IDLE MOLE

/SET wlND ;i:rn ( 1)
/SET WINDOW BIT k'J0
/GET STATUS TO AC
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K0200

ANO

l'l

;READ MARK WRITE

C~A

JMP I

7650
5572

137~

136~

CL·A··cl..t..
XF'R

615~

2210
2211
2212
2213
2214
i215
2216
2217
2220
2221
2222
2223
2224
2225
2226

1367

TPE?RE

/SAVE ~ARK WRITE
IDIO IT STAY iERO
ttJOPE ERROR

/0 wIND
;TRY TO GET OUTPUT rROM WIND00•PHA~£
/LOAD MAINT REG
/CL.EM~

AC1L.
/READ STATUS

K0200

/SAvE MARK wRITE
1'T'EST IT

L.WA104
1(~020

/ER~OR

/RESET LC02 ( 1)
ILOAO MAJNT REG
/CLEAR AC1L
/REAC' STATUS

K'120~

NERROR
JHS I
ERROR
JMS 1
LWM104
HLT
SKP CLA
LWN104

/SAV£ MARK
/TEST
/TEST OKAY

~RITE

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/~ESSAGE

TAG

tERROH HALT
/EXIT
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/tl•·~t

tm CQHtlO&. Tl.ST •41H U1 MAIHOl.C: ~,i•D.H....

U.7.~

1381

1382

/DOES CATA CHANNEL. RWB 01418 WORK

13,8".~

1385

2231

1386

2232

4025
1042

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1.38?

223:.3

3~16

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13&8

221A'

6151
:S.116

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139~

22.~6
22~7

tl54
1300

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i39i

1~93

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1315
1.39~

1397

22•
22•

6152

Z2d'
22414

:tJf1e

141·1

22.•
22.51

i4d

io3

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22'2
22tJ
225'4

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a~~1

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7~40

52'14

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111~

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6152

141~

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226:3

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1412

2264

61!'4

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226:5

0041
31.l.7
1117
?041
104-1
76,{1
4436
4437

142~

2273
2274
2275
2276
2277

1424

2300

1421

1422

6366

7~02
7~11:~

2231

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142~

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31117

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re > RWB
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· /CLt.EAR AC1L.
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10.71

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22,46

2266
2267
2270
2271

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trl.51

2255

141~
141~

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1406
1401
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14219

2257

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1<4210

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aa•a ,100

1399

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1J71

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22.4'4
22.+7

139.~

2••S~P·1t

138~

139;·2

vi•i.

IL TS I C12""0"'t.. TS

1.38f

138~

,..~,,.,

K6000

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REGC

K0160

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JM$ 1
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/GET MISC STATUS 1 TO AC
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;SAVE DATA CHAN\;[L SITS
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ERROR

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IF'ETCH IT
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10.lT

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L:10P

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)

1PDP"'ll TAJ! CONTAOL, TEST PARJ !Jr HAINOEC 12•03GA•L.

PAL.10

V141

15155

24-SEP"n

1425
i42~

1427
1426

/DOES THE MARK Ct..OCK GENERATE T 11"' I NG

1429

2311J1

4025

143~

2302
2303

1056

1431

1432
1433
1434

1435
143?.
143/

i43~

1439
14416

2304
2305
2306
2317

2310
2311

2312
2313

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6154

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JMS I
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6414
7402

1446

2321

2322

7~10

2323

231211

14•7

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I Cl.. E AFC MA RK FLOP

ANO

2320

rcro1, Tcz.:. ANli :'"lA~K FLOP i<

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IL. MOi:lE

~112

4437

ISE:T MARK rl.O?

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1010

1444
1445

144.3

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2315
2316
2317

1441

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HL.T
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;GET MISC 1 TO AC
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/MESSAGE TAG

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GP £ i..;

PAu' 40

1,?Qft-.11 htt£ CONi'"Q~ f!ST P'Aftf 111 MA l NOtt U*D~A•t.

14!~

1455
14,.6
149~
14,~·

2324

23i~

23.2'6·

23.7

4025
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i33f 6151
233l

7~00

146~

i~;t,~.

:i,;a1"

14·62:-

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1464
146:,

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2~~2~
2li~

14·4~
146.~

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6:·t''4
'l,145
:?:116

146:7

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1472

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147~

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TAO
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146~

23:3; .

L. rs10;, JMS

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144'~

1451
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144§:
14~f'

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l.,.Mft

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NERROR
JM$ I

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l. TM1il1
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?610
N24

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ERROR

/0 ) E. VERYTH I "JG
/SET BirOCK MARK

/SET H'4RK wlNDOW TO r<EVERSE'.
/SET l_.IP FOR TP4
/SET L.Ch ,.~0 TO ONES
/SET AC F'OR TP0
/SET l.C02 ( 1)
/SET AC FOR TP1
11..0AD MAI NT REG
/CL.EAR AC ,i.
IStT UP F'OR Ml SC l

1LJ1AO ~•·INT REG
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1Rtl·O OAT4'
/$ A'V E 1.1 f'-4 E COUNTER

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/F'ETCH IT

/TEST

/TEST Ci<AY

/TEST rAIL.ED

/ME:SSAGE TAG

/ERROR HAL. f'

/EXIT

/SCOPE l.OOP

1'''"' PAGE

4'·1

1?0P·12 TAPE CONTROL TUT PAR! II t HAINDEC 12•D3GA'L
1475
1476
1U7
147~

1479

148"

.J.48i
1482
1483
1484
1485
1486
1487

1438

1489
1496'

149i
1492

1493

1494
1495
1496

1497

1498

2354
23'5

2356

2357
2360

2361
2362
2363

2364
2365

2366
2367
2370
2371

2372
H73
2374

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2375
2376

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2377
2400

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1300
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0112
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1~35

1598
150~

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1511
i512
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1!)1.4

1515
1516

1517
1516
1519
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:522
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~52~

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7~10

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/TEST
/TEST Ol<AY

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/MESSAGE TAG
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HLT

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/SCOPE LOOP

SKP CL.A

MOTST1

2354

/P MOOE
/GET B~OCK MARK
tSET MARK wINDOW TO BLOCK MAR;(
/SET t31T FOR TP~1TPl1TP2
/l.OAO MAINT REGISTER SET TUR~J ARQUt..;D
/ADO Ut" I TS + MTN TO AC
!TRY TO i!ERO MOTlOf\i
!CLEAR ACd.. INK
1READ OATA

/DOES TAPE PR~SET 0 > THE MOTi ON F'l.OP

i516

1ser7

/MOVE TOWARD BLOCK

TAO

4~36

MAlNT FLOP

t..MR
CL.A

A~O

2402
2403
2404

2405
2406
24"07
2410

2411
2412

2413
2414
2415
2416
2417
2420
2421
2422
2423
2424

4025
4432
6~~1
0100
700f!

MOTST2, JMS
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61:;1
7;500
6154
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I
I
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I
10 EVERYTHING
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61.41
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1584
15115

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Ant•1f tA;I CQN-,_ Tt•'T l'AR1'

u, HAtMot11 12 -oac~·t.

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I

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I

152~~

153;8

242'5

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l,32

242~6

402'5
72411

2427

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153~

2431
243:1
243.'2

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6151

i533
153~

1!33~

1537
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1'~9

154~

1,41

1'42
154~

154'4

i545
i,46

243~

24~1

244:0
24':!.
244'2
2443
24-44
244'9

1553

15,4

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15'6

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1556

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7300
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2451
245.2

2454
2455
24'6
2457

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44~7

1561

7~02

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2466

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246J
2464

15~?
156~

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/~T BM
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246.2

i56i

/SET AC00

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II. MOCt
/MTi

ANO
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SNA CL.A
• +4
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1559

4436

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/GET AC>TAC
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2461

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2~47

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L.INC

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1552

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184~

1549
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240

1551

7330

243.4 . 6154
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Cl.A CMA
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thff

PAGE

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PA\.,10

V~41

24·S£P-70

1564

1565
1566
1567
1568
156Y
i570
1571
157?
1573
1574
157~

1576

1577
1576
1579
1580

15ai
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1583
1584
1585
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1587

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1589
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1592

1593
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/DOES H113 82~ PINS 021E2rF2 ?HirT Rw8

2467

4025

2470

4432

2471

2472
2473
2474
2475
2476
2477
2500

2501
2502

2503

2504

25e5
2586

25"7
2510
2511

2512
2513
2514
2515
2516
2517

2520

?240

6154

7~00

1011

6152

TPEPRE
REG004, JMS
MAlNTl
JMS l
CLA CMA
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731il0

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7240
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4436
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6556

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7402

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2576

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4436
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1.601

2577

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PAGE 46

- /PCP0:.12 h-~ CONTROL T!ST PART !11

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1958
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CONTROi. TUT PART ll 1 MAINDtC 12eD3GA•L
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26H
2634
2635
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2637
2638
263?

2640
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2643
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2645
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6261

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6262

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6263

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0~01

1104

1i04

6271

1405
4050

1'405
4050
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02'3
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6273
6274

6275
6276
6277
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L.WH101, 0014
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7340
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6311
6312
6313

160
2401

1640

0!t'13

24"1

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2402
5440
1722

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6322

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6324
6325

266~

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6316
6317

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2671

6327

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2672

6330

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6332

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266~
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6306
6307
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26&1
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2664
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6266
6267
6270

2647
2648
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0000

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0701
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2422
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0117
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2424
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L. TM00~, 0014
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/PDP.12 TAPE CONTROL TEST PART II' MAINCEC 12-03GA•L

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2752
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2759
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2766
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2770
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2772

2773
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6444
6445
6446
6447
6450
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6461
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6466
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MOTT1M, 0014

1525
4024
2522
1640

0122

6472

16'14

6473
6474
6475

5440

1604
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2900

2901
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2903

29"J4
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2917

2908
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291i
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2912
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2921
2921

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2931
293i
2932
2933
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2937
2938
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6673
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6675

7777
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6677

0361

6703
6784
6705

22101
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6711

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4444

6712
6713
6714
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240.5

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6722
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6255
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1911

1913

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618

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