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EK-DRVWA-UG-002

April 1986

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Document:	DRV11-WA General Purpose DMA Interface User's Guide
Order Number:	EK-DRVWA-UG
Revision:	002
Pages:	64
Original Filename:

OCR Text

EK-DRVWA-UG-002

DRV11-WA

General Purpose
DMA Interface
User's Guide

Prepared by

Computer Special Systems

2nd Edition, April 1986

The information in this document is subject to change without notice and should not be
construed as a commitment by Digital Equipment Corporation. Digital Equipment
Corporation assumes no responsibility for any errors that may appear in this document.

Printed in U.S.A.

This document was set on a DIGITAL DECset Integrated Publishing System.

The following are trademarks of Digital Equipment Corporation:

Eflaunanw

DECUS

RSTS

DEC
DECmate
DECset
DECsystem-10
DECSYSTEM-20

MASSBUS
PDP
P/OS
Professional

ULTRIX
UNIBUS
VAX
VMS

Rainbow

DECwriter
DIBOL

RSX
Scholar

Work Processor

CONTENTS

Page

LITERATURE

® & & & & & &6 6 & & & > & s & 0 O 6 & > & 6 5 o v 0 *

CONSIDERATIONS

I
Y R

.eeeeeceosococsoseos

IbJSTALLATION ® ®© 6 & & & & & & & 6 & & 0 0O & >
Installing the DRV11-WA in an LSI-11

Installing

the

Enclosure

(MICRO-11/MicCroVAX)

DRV11-WA

Installing

the

(MICRO-11/MiCroVAX)

TURN"‘ON

the

Enclosure
INITTAL

DRV11-WA

JUmMPETY

Mode

Interprocessor Link Mode Jumper ....
Independent Interrupts Jumper ...ee...

Burst

BA23
.eeeeese

the

BA123
.«eeeeesen

® 06 & 0 6 5 0 06 06 0 0 0 0 0 00 5 0 0 0 0 o0

2-11
2-12
2-13
2-14

Running

MDM

.....cee.e. ceeecscnne oo

MDM

Diskette

MDM

Tape

MDM

Examples

BASIC

Boot

BOOt

® & & & o o ® & & ¢ & & & ¢ o o

® & ¢ & & & ¢ 5 & o O & 6 b O O O 6 4> e

® 6 & & ¢ & & & o o & o &

® & o o & o o

2-14

2-14
2-15

2-16

OPERATION

GENERPA[J

® & @ &5 6 & & & 5 5 0 6 0 6 0 & O 0 O B O O

s s 000

DRV].].-WA Registers ® o » e 0o 0 o ¢ 6 0 0 0 0 0 0 @
Word Count Register (WCR)
.eeeeeeosese
Bus Address Register (BAR)
.ceeeeeees

Extended Bus Address Register
Control/Status Register (CSR)

iii

(BAE)
..eoe.

|
W

......

CONFIGURATION

AN UL W

SWITCH

Device Address Selection ...ceceeses
Interrupt Vector Address Selection .
Addressing Mode Selection ...eeeeees

MODULE
N

AND

Space RequirementsS s.eeeececocecenss
USER I/0 CABLES teceescevscocsoscccsaos
User Termination Connector ..eececes
JUMPER

..ceeeo ceceee s

LSI-11 Bus Loading ...eeeeeeeo. ceese
Power RequirementsS ....cececesecccscs
Priority Requirements .....ceeeeeeses

[

SYSTEM

INSTALLATION
GENERAL

o 0 0

® & & o 06 & & 06 &6 & & 2 6 s ¢ 0 0 o

wWwwww

W WNNDNDNDN

® & o & & 0 & 0 06 0 & & 0 & o o 0

® & & & & o 0 ® & 6 5 0 % ¢ & » O s

b
b

DESCRIPTION

—

[]
L]

SPECIFICATIONS

T UTUL b

o
o

INTRODUCTION
GENERA.L

CHAPTER
NN NNDNDMNMDNDNDNDNDNDDNDNDNDNDDNDDNDDNDN

w N

=
b

CHAPTER

(Cont)

CONTENTS

Page

3.2.1.5

Input

and

Output

Data

Buffer

Registers

3.2.2

(DBRS)
et eeeeeens csess
s c e s s es e e
e cesccssene
User Interface LinNesS ...eeeeeeen c et e e et
ee e e

3-3
-3
3-5

3.2.3

LSI-11

BUS

LiNES

3.2.4

User's

I1/0

Device

3.2.4.1

(DATO or DATOB)
tuveeeeesw cee oo et
e e s es e eeee
InterruptsS
...ttt eeeeeeeeeosessssanosansnsos

3.2.5

LLSI-11

Memory

(DATIO

3.3

CHAPTER

TIMING

. ceeeeceeccocnccssoscssaes Ceoco e

DATI)

Q-Bus

User's
«eesse

Memory

Device

Transfer
3=7
3-R

Transfers

e e s s e e e s s e e e s e e s e

e a0

3-9

¢ eeeeeesocososceoscscasssscosssccscssss ceesone

3-11

PROGRAMMING

4.1

GENFRAL

s s e e oo

4-1

4.2
4.3

PROGRAMMING INSTRUCTIONS .cececooese ee s s s e s e e e e
DRVI1-WA REGISTERS «evevveneenn C et
te e

¢ieetecocecsccncesoe c s s e e s e s e

4-1
4-1

4.3.1

WCR

4t eeeecocsossscossscssssscsscess cecesesscennas

4-1

4.3.2

BAR

.ieevnesee Gttt
e s e et eece
e et e ce

ce e .

4-1

4.3.3

BAE
CSR

it et eeeoosscoscsostsesosssessccssasssscscccsnce
.t vieevoonccoa ceeeen
e Gt e ee
e et
st eesen
o ceeoaene

4-2

DBRS

ittt eeveecsessscossacosssnsconsocss ceeeceres oo

4-2

4.3.4

4.3.5
4.4

PROGRAM

4.4.1

Word

4.4.2

CSR

INTERRUPTS

Count
ERROR

4.5

FUNCTION

4.6

PROGRAMMING

CHAPTER

5.1

5.2
5.2.1

5.2.3

BUrst

5.3.4

(Bit

STATUS
EXAMPLE

..eeeeceeececses ceesaeaeese eo
15)

tieeeosecoceces cesecs
o e

BTTS

.tcevesescocoscscscsnsce c e o

4t e o eeoocccoocsos c s e es s ee e

Cycle
Mode

PROGRAMMING

4-2

A4-2
4-2

4-3

4-5

e ans

5-1
5-1
5-2

5-4

e e v e e

5-5

LINKS

GENERAL ..... e e 6 e e s e s e
e s s e s e s e
s e
eesee s
OPERATING MODES .t ceceeceocscsccccos R
WOord Mode .eeeeeeees ce e e eecoens c e s es e ce

Single

5.3.1
5.3.2
5.3.3

AND

INTERPROCESSOR

5.2.2
5.3

.+.ceeeceocens ¢ s e es s e secesses
e

OVerflow
Bit

ens

..i.vee... c e s e ecc et e s eses e sss s

....eieeceeoescosccccss e e s e s e e e

5-6

Word Count Register (WCR)
eeeeeeceeees ceecesass
Bus Address RegisteY (BAR)
teeeeeceoococcccnsase
Output Data Buffer Register/Input NData
,

DH=6
5-6

Buffer

.eceeee c e e e e e e e ee.

5-6b

(CSR)

5-6

Control

' eeeeo
e c e e s s e e s e s s e s s s e

and

(ODBR/IDBR)
Status Register

s es

e s s

eceeeeoosoeos .

FIGURES

NN
I

Figure No.

Title
DRV11-WA

Simplified

DRV11-WA

Connector

DRV11-WA

Device

DRV11-WA

TInterrupt

Diagram

Switch

Address

Select

Vector

...

Locations

Format
Select

Address

..'........'..........'...0...

DRV11-WA

Connector

DRV1I1-WA

Block

DMA
DMA

[

Wwww

Format

Interface
and

DATO/DATOB
DATIO/DATI

Diagram

Assignments
...eeeeeoooeeos

Data

Flow

Diagram

.,...

Data

Flow

Diagram

....

DRV11-WA

3-7

DRV11-WA

3-6

3-5

DRV11-WA Single Cycle, User-Initiated, Timing
DIAJLAM 44 eeoeescocecaooeseosoasnessasscenss
DRV11-WA Single Cycle, Program-Initiated,
Timing

Diagram

DIiAGYAM

Burst

t.ueeeeeeeeeseeeeonooosceeeas
User-Initiated,
Timing

Mode,

44 eeseeeeoooaoooossssssasosassssssaes
Burst

Mode,

Program-Initiated,

DATIO

Timing

=Y
B =
3-8

DRV11-WA

4-1

CSR

FOrmMat

5-1

Interprocessor

5-2

Interrupt

5-3

Diagram

...ceceeees

vueeeeeeeooeseosonoossaes

Link

Sequence

Block
for

Program

Word

Mode

Interprocessor

Link

..eeeoeeeecese

Internrocessor

Link

...

Single

Cycle

Transfer

Sequence

for

eceseess

TABLES

Title

Interprocessor
Independent

DRV1I1-WA
CSR

Bit

Assemblies

.....

..ceeeonoovcoees

Link

Mode

InterruptsS

Jumper

.vuveeeeeoess

Diagnostic
FUNCLIiONS

Correlation

Interprocessor

TestsS .eeeee..
teeeeeeoenconean

CSR
Link

Function

and

Operation

Status Bits in
...eeeeeecesecosss

Cable
JUMDEY

Mode

~Jd~Jd

Recommended
Burst

Page

=11

No.

S
WN

Table

CHAPTER

INTRODUCTION
-

1.1

GENERAL

The

DRV11-WA

terface

DESCRIPTION

for

general-purpose

transferring

Q-bus memory and

16-bit

user's

Direct

Memory

data

words

I/0 device.

Data

Access

directly

Transfer

(DMA)

in-

between

the

Out

Data

(DATO)

Transfer In
(DATI)
takes place over the Q-bus after a DMA request,
once the DRV11-WA becomes bus master.
Burst modes
(four-:
word or continuous), byte addressing, and read-modify-write opera- .

tion

(DATIO)

tures

are

possible

switch-selectable

connectors,

and

ing

user's

both

standard

There

The
BAR,

the

are

one

and

six

registers
Count

Bus

Address

Extended

Control/Status

)

Input

CSR

and

connector

device.

extended

Word

DRV11-WA

the

and

2-pin

I/0

and

with

device

the

DRV11-WA.

Address

(CSR),

Buffer

word-addressable.

and

interfaccompatible with

are

with

the

under

2's

program

whereas

control

complement

transfers,

Loading
which

3.
Data

DMA

the BAR and BAE with the first
data is to be transferred, and

transfers

logic.

follows:

(DBRs).

byte-addressable,

initialized

WCR

They

Registers

word-

the

simple

and

are

fea-

40-pin

(BAE),

only

two

(BAR),

are

operation

provide

DRV11-WA

DBRs

BAE

DRV11-WA

(WCR),

Output

that

(The

The

addresses,

Q-buses.)

Bus

and

DRV11-WA. ;

vector

the

CSR

with

may

now

proceed

the

desired
under

the

function
control

WCR,

by:

the

address

the

number

from

bits.
of

the

DRV11-WA

Figure

1-1

shows

the

primary

interface

DRV11-WA and the user's 1/0 device.
(DATO) data transfers take place when

signals

between

DMA input
(DATI)
or
the processor clears

the

output
READY.

For a DATO cycle (DRV11-WA to memory transfer), the user's I1/0 device first presets the CONTROL BITS (word count increment enable,

bus address increment enable, Cl, C@, A@g, and ATTN), and then asWhen CYCLE REQUEST
serts CYCLE REQUEST to gain use of the Q-bus.
is asserted, input data is latched into the input DBR, the CONTROL

BITS are latched into the DRV11-WA DMA control, and BUSY goes low.
(A DATI cycle memory to DRV11-WA transfer is handled in a similar
manner, except that the output data is latched into the output DBR
during

When

the

formed

the

BAR

bus

cycle.)

DRV11-WA becomes bus master,

directly
and

BAE.

from

the

end

DATO or

Q-bus memory

each

cycle,

DATI

location
the

cycle

WCR

per-

BAR

are

specified
and

incremented and BUSY goes high while READY remains low.
A second
DATO or DATI cycle is performed when the user's 1/0 device again

DMA transfers will continue asynchronously
asserts CYCLE REQUEST.
until the WCR increments to zero, at which time READY goes high

and

the

DRV11-WA

generates

set)

the

processor.

Q-bus

I1f

continuous

the

specified

CYCLE

REQUEST

burst

mode

number

interrupt

selected

data

words.

required

(if

interrupt

enable

only

one

for

the

(SINGLE

complete

CYCLE

low),

synchronous

transfer

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1.2

SPECIFICATIONS

The following specifications and particulars are for informational

purposes and are subject to change without notice.
Physical

Dual height, single width, extended length module.
Dimensions:
Plus

Circuit Card

Length: 21.6 cm (8.5 in)
Height: 12.7 cm (5.0 in)
1.3 cm ( .5 in)
Width:

Length: 22.8 cm (8.9 in)
Height: 13.2 cm (5.2 in)
1.3 cm ( .5 in)
wWidth:

Weight:

215

grams

Two 40-pin connectors, one 2-pin connector

User I/0 Connections:

Mounting Requirements:

Plugs directly into Q-bus backfilane or

O0-bus

expansion backplane.

Electrical

Logic Power Requirements:

1.8 A @ +5V + 5%

Presents one bus load

LSI-11 Bus Loading:
User

Handle

Circuit Card

Loading:

Input Data Lines

1 TTL unit

load each

HIGH = Logic one
LOW = Logic zero

Input Control

Lines

1 TTL unit load each
HIGH = Logic one
LOW = Logic zero

output Data Lines

1¢ TTIL unit loads

HIGH = Logic one
LOW = Logic zero

(drive)

Output Control Lines

10 TTL unit loads

HIGH = Logic one
LOW = Logic zero

(drive)

(nominal)

Module Type:

M7651

Operational:

Transfer Mode: DMA or program-controlled with interrupts
Data Transfer

Rate:

cycle mode
Up to 25¢,000 16-bit words per second in singlemode*
Up to 400,080 l16-bit words per second in burst
Environmental

Temperature:

Storage: —402 to 668C (_4gQ to IBgOF)

Operating:

to 5@ C

(41

to 122 F)

Relative Humidity: 10% to 95% noncondensing
1.3

RELATED LITERATURE

In addition to the M7651 print set

(MP@1582), the Microcomputer

Processor Handbook and the Microcomputer Interface Handbook contain useful information for installing and operating the DRVI1-WA

general-purpose DMA interface.

Handbooks may be ordered from the

nearest Digital Equipment Corporation Sales Office.

While doing continuous burst mode transfers, the DRV11-WA be-

comes bus master and holds the bus until the entire transfer iss
This action may potentially lock out other device
complete.
This
from accessing the bus while the transfers are ongoing.
the
of
ion
operat
the
with
mode of operation is consistent
18-bit predecessor product, DRV11-B.
1-5

CHAPTER

INSTALLATION

GENERAL

2.1

Installation of the DRV11-WA general-purpose DMA interface consists of selecting the device and interrupt vector addresses,
selecting mode of operation (18- or 22-bit addressing), selecting
functional operating modes as necessary
(independent
interrupts,
four-word or continuous burst mode, interprocessor
link mode), and
then
inserting
the
interface
into
an
LSI-11/MicroVAX
processor
system.

2.2

SYSTEM

CONSIDERATIONS

Before installing the DRV11-WA into a Q-bus system, consideration
must be given to bus loading, power, priority, and space requirements.

2.2.1
The

LSI-11

Bus

DRV11-WA

presents

loads

can

handled

mine

the

existing

one

bus

the

Q-bus;

Q-bus

load

the

Q-bus.

therefore,

when

the

installing

Fifteen

user

bus

must

deter-

additional

Q-bus

modules.
2.2.2
The

Power

Requirements

DRV11-WA

requires
obtained

1.8

from

the

2.2.3
Priority Requirements
Each device on the Q-bus has
on

its

relative

priority
bus

along

priority,

position

device.
with

the

Since

other

user

interrupt

the

user

may

that

use

bear

(nominal).

system

from

devices

must

+5V
Q-bus

power

and

mind

for

DMA

priority

The

DRV11-WA

processor.

install

Power

the

same

that

when

the

supply.

DRV11-WA

interrupt

vice
1is
requesting
service,
the device
electrically
Q-bus processor has the highest priority and will

than

based
is

the

DMA

one

de-

nearest
the
serviced

first.
In

addition,

systems),

the

for

detailed

REV1l

DMA

refresh

must

Refer

the

information

DRV11-WA.

2.2.4
Space
The DRV11-WA

the

REV11

Requirements
requires one

the

double

option

priority

Microcomputer

REV11l

level

used

Processor

options.

height

module

(for

higher

slot.

LSI-II

than

that

Handbook

I1/0 CABLES

USER

2.3
The

DRV11-WA

the

recommended
nect

has

two

that

cable

user's device.

the

DRV11-WA

40-pin

Two

connectors

cable

assemblies
the

which

provide

assemblies

user's

from

interface

required.

2-1

Table

device,

the

are

The

used

listed

con-

cables

are

terminated
(one or both ends)
with
H856
4¢0-pin
connectors
that
mate with the connectors on the DRV11-WA.
Cable selection is determined by the type of connections used on the user's device.

The desired cable length
(XX)
must be specified when ordering.
(Lengths longer than 25 feet are not recommended for use with the
DRV11-WA.)
Cables may be ordered from the nearest Digital Equipment Corporation Sales Office.
Non-standard length cables may be
ordered

additional

cost.

2.3.1
User Termination Connector
The DRV11-WA has one 2-pin connector
user

provide

than

the

one

Cable

No.

BCOB8R-XX

additional

listed

Table

2-1

used.

Recommended

Type

H856

Shielded

H856

optionally

termination

Connectors
to

which

signal

Cable

when

the

other

Assemblies

Standard
flat

allows

cables

1¢,

Lengths
12,

20,

(ft/m)
25

(p.305, 1.838,
3.050,
3.660,
6.100,
7.625 m)

2.4

The

JUMPER

AND

SWITCH

DRV11-WA contains

CONFIGURATION

two

DIP

(dual

in-line

package)

switch

units

(E49 and ES@)
and a number of jumpers that allow the user to select the module features desired.
The location of the switch
units and jumpers is shown in Figure 2-1.
The address selection
switch (E5@) consists of ten switches that let the user select the

device address.
The second switch unit (E40) consists of ten
switches that let the user select the interrupt vector address and
18-bit or 22-bit addressing mode.
2.4.1
Device Address
The DRV11-WA contains
WCR
BAR
BAE

CSR

Input
Output

DBR
DBR

Selection
six registers:

These registers must be addressed for data and status transfers
between the DRV11-WA and the LSI-11/MicroVAX processor.
The BAR
The two DBRs use the same address.
and BAE use the same address.
The register addresses are sequential by even numbers and are as
follows.

BBS7

WCR
BAR
BAE

1
1
1
1
1

CSR
DBRs

The

assigned

DMA

Octal

Address

Hex

XXXXXJ
XXXXX2
XXXXX2
XXXXX4
XXXXX6

Address

3FF508
XXXXXA
XXXXXA
XXXXXC
XXXXXE

interface base address

77241@8,

3FF508,

The

user selects a base address for assignment to the WCR and %gts the

device address selection switches on the DRV11-WA module to decode
this address.
The remaining BAR, BAE, CSR and DBR addresses are
then properly decoded by the module as they are received from the
processor.

LLSI-11

Figure

2-1

shows

the

location

the device

address

selection

address

have

switches on the DRV11-WA module.
Switches are set to the ON
(closed) position for bits to be decoded as "ONE" bits in the base

address.

switches

dress
for

Bits

set

select

the

device

decoded

the

(open)

format

OFF

and

address

"ZERO"

bits

position.

presents

selection

the

Figure

2-2

switch-to-bit

switches.

shows

their

the

ad-

relationship

LINK MODE

DEVICE ADDRESS

VECTOR ADDRESS, Q22/Q18

SELECTION SWITCHES

BURST MODE

SELECTION JUMPER

SELECTION JUMPER
h

w3Q

O0O0O0
~—

[

w6 O

E40

WsO

E50
j—

ATTENTION INTERRUPT

SELECTION JUMPER
CS-4720

Figure

2-1

DRV11-WA

Connector

and

Switch

Locations

DECODED FOR
10F4

DECODED BY BBS7
—

SELECTED BY SWITCHES

~—

DEVICE

SWITCHES

—

appress | ON
SELECTION § OFF l

REGISTERS

10
l

BYTE —]

CONTROL

OFF = “"ZERO
ON

= “ONE”
CS-3958

Figure

2-2

DRV11-WA

Device

2-4

Address

Select

Format

2.4.2

Interrupt

Vector

Address

Vector addresses 0-1774,
are
DRV1I1-WA 1is assigned vector
interrupt

Selection

reserved for Q-bus system users.
address
124 .
The user selects

vector

The
the

address by means of swifches on the DRV11-WA mod2-1 shows the location of the vector address selection switches.
Vector address selection switches are set to the
ON
(closed)
position for bits to be encoded as "ONE" bits in the
vector address.
Bits encoded as "ZERO" bits in the address have
their switches set to the OFF
(open)
position.
Figure 2-3 shows

ule.

Figure

the

address

ship

for

select

the

format

vector

and

address

presents

the

selection

switch-to-bit

relation-

switches.

NOTE

The

DRV11-WA

designed

to be compatiwith the DRV11-B; therefore, its assigned base address is 772410 (8).
How-

ble

ever,

under

treated,

DR11-W.

Therefore,

autoconfigure
the

vector

the

(OFF=0)

dressing

selects
for

(see

for

the

correctly,

de-

you

set

the

interrupt

and
rank

40,

device

both

space.

Selection

22-bit

18-bit

Figure

address

Mode
18-

address
and
interto
those reserved

namely,

rank

address

floating
Addressing

address

DR11-W;

DRV11-WA

order

vector

OFF

device

the

possible,

set

address

user

vice

for

2.4.3

much

must
rupt

The

MicroVMS,

addressing

addressing,

setting
(ON=1)

E40

for

2-3).

switch

22-bit

4TH

1ST

OCTAL

DIGIT

2ND

3RD

OCTAL

DIGIT

(O OR 4)

PREASSIGNED

DIGIT

06 05

AS ZEROS

VECTOR

ADDRESS
SELECTION

[ON!
|

2
|

switcHes |OFF
OFF = "ZE.R(?“
ON

3
|

9
|

10
l

’
4
I

5
6
11

7
|

8
|

NOT _}

"ONE

USED

ON = 22-BIT ADDRESS
OFF

18-BIT

ADDRESS

Cs-39589

Figure

2-3

DRV11-WA

Interrupt

Vector

Address

Select

Format

19
ad-

Jumper

Mode

Burst

2.4.4

The DRV11-WA will, by default
(W2 jumper installed), relinquish
and re-request bus mastership after every four DMA transfers.
The
user

may

select

continuous

push-on

jumper

from

2-2

Figure

2-1.)

and

burst

and

mode

installing

transfers

Wl.

removing

(Refer

the

Table

NOTE

If continuous burst mode is selected,
the DRV11-WA will not relinquish the bus
until the entire transfer
is complete.
This action is not recommended as it may
potentially lock out other devices from
gaining access to the bus while the
transfers are ongoing.

Mode

Burst

2-2

Table

Jumper

Factory

Jumper

Function

Setting

Module 1s backward compatible with the
DRV11-B and will perform continuous burst
mode transfers and will
bus until all transfers

Module
bus

Removed

Installed

2.4.5

will

after

Interprocessor

The user may operate

another

stalling
the

DRV11-WA

it at wW4.

recommended

relinquish

every

four

Link

not
are

and

DMA

Mode

(Refer

setting

re-request

Jumper

setting

(W3

the

2-3

link

interprocessor

push-on

Table

use

release the
completed.

cycles.

the DRV11-WA as
removing

jumper

and

DRV11-WA

from

Figure
as

2-1).

with

and

This

in-

1nterprocessor

link.

the

default

jumper

installed),

the

DRV11-WA

backward compatible with the DRV11-B and will not function as an
interprocessor link unless one of the processors acts as the
Use of the DRV11-WA
slave, and the other acts as the master.
within this configuration (W3 jumper installed) for interprocessor
link

not

recommended.

Table 2-3

Interprocessor

Link Mode Jumper

Factory

Jumper

Function

Setting

Module is backward compatible with DRV11-B
and should not be used as an interprocessor

link.

i
i

Module may be used
l1ink

two

interprocessor

DRV11-WA modules.

Removed
Installed

2.4.6

While
not

between

Independent

the

Interrupts

default

necessary

for

Jumper

interrupt

the

READY

mode

bit

(CSR

(W5

jumper

Bit

installed),

CLEAR

for

1is
the

DRV11-WA to interrupt.
With the IE bit (CSR Bit 6) set, the
DRV11-WA will interrupt when the ATTN bit (CSR Bit 13) or the NEX
bit

(CSR

Bit

For

backward

14)

set.

compatibility

the push-on

jumper

from W5

bit

CSR

with

the DRV11-B,

the

and install
it at Wé.

user

may

(Refer

remove

Table

2-4 and Figure 2-1).
1In this setting, the DRV11-WA will only interrupt when the READY bit (Bit 7) cf the CSR is set, and the IE
(Bit

the

Table

2-4

set.

Independent

Interrupts

Factory

Jumper

Function

With the CSR IE bit set, module will
interrupt when CSR ATTN or NEX bits are
set, independent of the READY bit being

Setting

set.

Module is backward compatible with DRV11-B.
With the CSR IE bit set, module will
interrupt only when the READY bit is set.
Removed

Installed

2.5

MODULE

INSTALLATION

The

type

the

following

CPU

and

its

current

configuration

must

performed.

procedures

determines

which

2.5.1
1Installing the DRV11-WA in an LSI-11 CPU
With the exception of the first two/four slots (the LSI-11 processor always occupies the first two/four slots depending on CPU
type), the DRV11-WA can be installed into any 022 slot /(see Section 2.2.4)
of
the LSI-11 backplane.
However,
1f REV11l
DMA reREV11.

make

sure

that

used,
When

the

1/0

connect

the

connectors.

DRV11-WA

inserting

deep

connector block rib.
power applied.
After

2.8),

the

notch

must

the

module

the

into

module

lower
the

seats

Do not insert or remove the
performing the 1nitial turn-on

user's

Connector

1/0 cables

locations

Figure 2-1.
Pin assignments
and are specified in Chapter

for

for J1 and
1, Section

the

option

than

0 0)

fresh

and

the

against

the

module with
(see Section

the

DRV11-WA

are

shown

J2 are
1.2.

priority

backplane,

shown

Figure

in
2-4

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)

—r

Remove the ac power cable from the wall outlet.

Remove the

cover

and all

retaining

for

reinstallation

Loosen

the

two

screws

any

internal

later.

open

assembly

the

Swing

bly.

Label

external cables.

rear

cables

(MICRO-11/

Enclosure

BA23

the

the DRV11-WA

ling
2.5.2
1Install
MicroVAaXx)

assem-

T1/0 panel

the rear

and

retaining

both

remove

all

straps.

Disconnect

I1/0 panel

cables

orientation of the connector
rear I/0 panel assembly.

each

the back

cable.

Connect

the

BC@8R-XX

ribbon

the

insert

user's

I/0

cables

later.

When

serve
the

TLabel

installing

the

CPU

Slide
8.

Reconnect

Replace
closed.

module
any

rules

manual(s).

into

the

internal

connection

BAZ3

the

I/0
the

enclosure,

ob-

outline

backplane
from

the

guidelines

removed

desired

for

1in

slot.

the

I/0

panel.

the retaining straps and swing the I/0
Tighten the two panel retaining screws.

1. Do not replace the rear cover at this time.
external

the

appropriate

cables

Remove

from

the

and

the

and

assemblies

connectors

DRV11-WA

configuration

technical

the

cables

connector

insert

module

and

location

specific

Set the device and vector address switches
jumper options (refer to Section 2.4).

panel.

attached

Note their

assembly.

panel

Replace all

cables.

11.

Connect

the

12.

Perform

the

initial

13.

Connect the user
blies on the I/0

I/0 cables
panel.

14.

Replace

cover.

the

power

rear

cord.

turn-on

procedures
to

the

(Section

insert

2.6).

connector

assem-

2.5.3

1Installing

the

DRV11-WA

power

rear

door.

MicroVAX)

Remove

Open

Loosen

the

rear

4.,

the

captive
of

the

cable

from

screw that

the

enclosure

BAl123
the

Enclosure

wall

fastens

(MICRO-11/

outlet.

the

right-side panel

frame,

Pull out
releases

on the bottom of the right-side panel until it
from the two snap fasteners holding
it to the

bottom

the

Lift
the

the

the
1lip

Release

swing

frame.

panel
at

the

far

enough

top

clasps

door

open,

the

and

release

from

the

slot

frame.
front

remove

the

card-cage

door,

it,.

Set
the device and vector
address
switches
jumper options (refer to Section 2.4).

Connect the BCO8R-XX ribbon cables from J1 and J2 on
module to the insert connector assemblies on the

the
I/0

panel.

the

enclosure,

ob-

Label

user's

When

serve
the

the

insert

I/0 cables

later.

installing

the

CPU

the

DRV11-WA

rules

configuration

technical

connectors

and

for

the

and

desired

connection

Bl1l23

guidelines

outlined

manual(s).

Slide the module into the appropriate backplane slot.
1#.

Do not replace
this time.

the

11.

Connect

the

power

12.

Perform

the

initial

13.

Connect the user I1/0 cables
blies on the I/0 panel.

Replace

and

14,

versing

the

card-cage

right-side

panel

cord.

turn-on procedures

card-cage door

steps

door

through

the

insert

the

this

(Section

2.6).

connector

assem-

right-side panel,

section.

re-

TURN-ON

INITIAL

2.6

After

completing the module installation, turn-on the LSI-11/
MicroVAX and initialize the system.
With no I/0 cables connected
and usin g the console terminal and operating procedures, perform

the

following

quick

operational

verification.

LSI-11
1.

Load

the

addresses

the WCR,

BAR,

nal

will

indicate

the

following:

22-Bit

AND

DBRs

through

The termi-

18-Bit

cC ontents

BAR

¢ ontents

will be 000000
will be 000001

BAE

¢ ontents

will

100000

CSR

c ontents

DBR

¢ ontents

will
will

be
be

127200
177777

WCR

CSR,

the system terminal and examine the locations.

WCR contents will
BAR contents will

be 000000
be 000001

CSR contents
DBR contents

be
be

will
will

127200
177777

The
can

WCR, BAR, and BAE (if 22 bit addressing is selected)
be loaded with data from the system terminal and the
corresponding data read back on the terminal.
BAR bit 0
will read as a one (1) with no I/0 cables connected.
NOTE

BAE (ADDRESS xxxxx2)
is read by first
examining the BAR
(ADDRESS xxxxx2)
and
then examining ADDRESS xxxxx2 again to
access

the

BAE.

Microvax
l.

Enter
The

MicroVAX

console

mode

prompt

mode

(see

">>>".

MicroVAX

Owner's

Manual).

Examine the addresses of the WCR, BAR, CSR, and DBRs
(refer to Section 2.4.1) through the system console using the
console-mode commands shown in Example 2-1.
This example
shows the expected contents of the registers, assuming the
assigned base device address for the module is used.
The
hex addresses used in the example were determined as follows:

22-bit register address:
22-bit I/0 space base address:
1/0 address offset:

32-bit

I/0

32-bit

physical

>>>

space

E/W/P

BE/W/P

29) ¢
address:

!WCR

@000

2000150A<Returnd>

2000150A

8000

P
>>>

2007%150C
AES8Q
E/W/P 2000 150E<Return>

2000150F

2000150C<Return>

Module

contents

!CSR
" contents
!DBRs

FFFF

2-1

E/W/P

Example

contents

! BAE

>>>

! BAR

0a01
'
2000150A<Returnd>

E/W/P

20000000

20015nn

2000150A

>>>

15nn

(bit

3FEGOQ

20001508<Returnd

20001508

>>>

select

3FF5nn
-

Check

contents

dn'MicroVAX

NOTE
For

explanation

the

commands,
refer
Technical Manual (s).

sole

The

user's

(Figure

I/0

device

cables

can

2-1).

MicrovAX

the

now

con-

MicroVAX

connected

the

DRV11-WA

2.7

DIAGNOSTIC PROGRAM - LSI-11
_
check procedure performed
in
Section
2.6 does
not completely
verify the operation of
the DRV11-WA.
Complete module operation
The

can

verified

AC-T974C-MC.
means

nance

cable

output

plete

any

(not

than

for

you

ware

Switch

loadable

input

description

When

use

can

longer

DBR

the

prodram

standard

the

plementation

through

The

the

provided

ft)

hardware

(SW12)

Switch

diagnostic

the
10-E490.

22-bit

The

diagnostic

18-bit

control

T1/0

software

BCO6R

data

program

system

loop

the

DBR

com-

its

im-

path.

program

mainte-

and

you must select softcorrespond with your selection
must be ON
(ON=1)
to enable 22-

SW12

enable

18-bit

address

test-

SW12 of Diagnostic

addressing

BCAS5L

required

the

software

LS1-11

diagnostic,

SWR

S10-E4D

OFF

the

AC-T974C-MC.

bit address testing, or OFF (OFF=0)
ing.
The default setting is OFF.

into

checking

diagnostic

device.

exec
the AC-T97
ut
4C-MC
e
12

the

loaded

addressing

will

character.

OFF

continue

Enable

22-bit

Disable

run

until

address

testing

22-bit

address

terminated

testing

with

2.8
The

DIAGNOSTIC
DRV11-WA

PROGRAM

MicroVAX

diagnostic

called

MDM (MicroVAX Diagnostic Monitor).
tests listed in Table 2-5.

Table

2-5

Test

The

DRV11-WA

Diagnostic

Function/Component

1
2

WCR

NADRAE

and

diagnostic

runs

under

comprises

the

Tests

Tested

(Word Count Register)
(Bus Address Register)

BAR

BAE

(Extended

CSR

(Control

Bus

Address

CSR

Byte/Word

6
7

CSR GO, READY, FUNCTION 1:3, and STATUS A:C bits
Read/Write to the DBR (Data Buffer Registers)

READY

DBR

and

Status

addressing

controls

BAR

clocked

BIT @
the cycle

interrupts

bit

Memory
Device

to
to

device
memory

single-word
single-word

Memory

device

multiple-word

transfers

Device

memory multiple-word

transfers

Memory
Device

to
to

device multiple-word
memory multiple-word

burst
burst

13
14

Maintenance bit control of Cl1
NXM (Non-existent memory) bit

NPR

transfers

transfers
transfers

and

(DATI)
(DATO)

mode
mode

single

transfers
transfers

cycle

functionality

maintenance mode

The MDM VERIFY mode
(see Example 2-2)
runs tests 1 through 4, and
requires
no
loopback.
SERVICE mode
runs
all
15
tests,
and
requires the digital loopback to be installed.
The loopback should

be installed
input (J2).

the

bulkhead

2.8.1
Running MDM
DRV11-WA MicroVAX

The

nostics

ferent

boot

the

appropriate

MDM

procedure,

2.8.1.1

MDM

Diskette

Insert

the

press

supplied

tape.

Fach

media

detail

described

MDM

Boot

Halts

II
The

are

automatically.

(J1)

the

diag-

requires

Chapter
H-3,

dif-

page

the

H-2).

diskette

MicroVAX

RESTART.

output

one

II Technical Manual(s)
(Table
procedures are as follows.

boot

Set

connecting

MicroVAX

the

diagnostic

diskette

Briefly,

panel,

power

diskette

drive

switch to 1
(turn power on),
will boot as follows:

diagnostic

disabled,

the

diagnostic

will

Dboot

Halts

are

sole

mode

boot

the
>>>

enabled,

and

diagnostic
B

MicroVAX

the

from

console

will

enter

prompt.

con-

Manually

DUAl:

DUAL

Several

information

prompts

diskettes,

the

display

screens

enter

date

and

continue.

to
will

and

MAIN

Select

item

display

Select

item

enter

The

MDM

will

then

displayed

Respond

The

prompt

then

will

time,

followed

insert

the

prompts.

the

remaining

displayed:
the

Service

system

Menu.

commands.

displayed:

MDM>
>

Examples

2-2

they

are

used.

MDM

Tape

Boot

Push

the

Fixed-disk

fixed-disk
Set

the

Tnsert

Push
as

through

the

show

the

MDM

commands

and

how

place

the

unit(s)

MicroVAX

the

2-5

MDM

Ready

pushbutton(s)

off-line.

power

tape

switch

cartridge

Load/Unload

into

pushbutton.

(turn

tape

The

power

drive

on).

diagnostic

will

boot

follows:

TIf

Halts

are

disabled,

the

diagnostic

will

boot

auto-

will

enter

con-

matically.
b.

TIf

Halts

mode

boot

the
>>>

Several
prompts
to

are

sole

the

enabled,

and

diagnostic
B

the

display

the

from

MicroVAX

console

prompt.

MUA®G:

MUA?®

information screens will be
to enter date and time, and

displayed followed by
to continue.
Respond

prompts.

Manually

The

MAIN

will

then

displayed:

Select

item

display

Select

item

enter

the

system

Service

Menu.

commands.

The

MDM

prompt

will

then

displayed:

MDM>>>

Examples

2-2

they

used.

2.8.1. 3

entered

MDM>
>

MDM

are

through

Examples

display

2-5

Example

list

show

2-2

the

shows

current

MDM

how

commands

the

and

how

HELP

command

(all

units)

commands.

HELP<Return>

Current

Commands

are:

CONFIGURE

SELECT

Diag

Configure system
Select a diagnostic

name

DISABLE Diag name
ENABLE Diag name
SET

DETAILED
DETAILED

MODE

Prevent

diagnostic

from

a diagnostic to run
Display detailed messages
DO NOT display detailed messages
Set verify mode tests
Set service mode tests

OFF

SERVICE
PROGRESS

OFF

Display

progress

messages

PROGRESS

BRIEF

Controller

progress

messages

PROGRESS

FULL

Controller and
Set functional

TEST

FUNCTIONAL
UTILITY

Set

utility

EXERCISER

Set

exerciser

ALL

Run

all

enabled

X X

Run

only

test

Run

tests

for

PASSES

START

ALL

test

progress

test

section

test

section

tests

number

Start

selected

Start

all

tests

enabled

system

SHOW

DEFAULT

Show

default

settings

SHOW

DEVICE

Show

utility

titles

SHOW

ERRORS

Show

reported

2-2

MDM

HELP

running

tests

Show

MDM>
>

passes

CONFIGURATION

UTILITIES

messages

section

test

SHOW

Example

run

Allow

VERIFY

SECTION

running

configuration

errors

Command

information

Example

2-3

shows

that

commands

mand

uniquely

same

typing

the

can

defaults

identify

SHOW

it.

the

DRV11-WA

typing

only

diagnostic.

enough

For

example,

typing

SHOW

DEFAULT

Command

Note

the

DEF

com-

the

DEFAULT.

MDM>>

CONFIG<Return>

MDM>>

SHOW

CONFIG<Return>

MDM>>

SEL

DRV11WA<Return>

MDM>>

DEF<KReturn>

Selected

1
Mode

for

abbreviated

device:

DRV11IWA

Enabled

SERVICE

Selection is FUNCTIONAL
Number of passes is:
1
No time limit
Tests

run:

Continue
Detailed

error

message

Progress

message

1is

Off
Off

2-~-3

MDM

ALL

MDM>
>

Example

The SHOW DEFAULT command shows
parameters.
The "real" defaults

only

when

changed
can
For

only

the

diagnostic

with

MDM

changed

example,

changed

the

current

first

in Example
booted
and
no

commands.
by

The parameter
of
a
entering the command with

default

typing

MDM>>

SET

SEC

MDM>>

SET

SEC

setting

(shown

test

either:

SECTION

default

2-3)
are listed
parameters
are

specific command
a new parameter.

FUNCTIONAL

and

can

only

Example

2-4

shows

the

commands

run

the

full

tests.

MDM>>

CONFIG<KReturn>

MDM>>

SEL

DRV1I1IWA<K<Return>

MDM>
>

SET

PROG

MDM>>

SET

DET

MDM>
>

SET

MODE

SERVICE<Return>

MDM>>

SET

SECT

FUNCTIONAL<KReturn>

MDM>>

ST<Return>

FULL<KReturn>
ON

DRV11WA started.
Please follow instructions

testing

will

Please attach
to input (J2)
Press

RETURN

Thank

you,
pass

DRV11WA

done

loopback cable from
CKDRV1-KA connector
when

you may continue your testing
started.
1 test number

DRV1 1WA

pass

test

number

DRV11WA

pass
pass

1
1

test
test

number
number

DRV1 1WA

pass

test

number

DRV11WA

pass

test

number

DRV1 1WA

pass

test

number

DRV11WA

pass

test

number

DRV1 1WA

pass

test

number

DRV11WA

pass

test

number

Start

DRV11WA

of
of

DATI
DATO

pass

Start

DATI

Start

DATO

DRV11WA

Start
Start

pass

of
of

output

completed...

DRV11WA

Start

carefully!
from the bulkhead

DATI
DATO

section
section
test

of
of

number

OO JHhUT
&~ wWwN

All

started.

started.
started.

started.
started.
started.

started.

test
test

started.

section

test

section

test

number

section
section

of
of

started.

test
test

DRV1 1WA

pass

test

number

started.

DRV1I1WA

pass

test

number

started.

Start

DATI

section

Start

DATO

section

DRV11WA
Start

DRV1 1WA

pass

DATI

test

number

section

test
test

started.

test

passed.

MDM>
>

-18

(J1)

set

functional

Example

2-5

shows

how

the

UTILITY

MDM>>

CONFIG<Return>

MDM>>

SEL

DRV11WA<Return>

MDM>>

SET

DET

MDM>>

SET

PROG

BRIEF<KReturn>

MDM>>

SET

MODE

SERVICE<KReturn>

MDM>>

SET

SECT

UTILITY<Return>

MDM>>

ST<Return>

section

run.

ON<Return>

DRV11WA

started.

DRV11WA

pass

DRV11WA

passed.

test

number

started.

MDM>
>

Example

2-5

MDM

Commands

the

UTILITY

Run

the

UTILITY

Section

NOTE

run

must

set

and

installed.

Section,

the

SERVICE

digital

Mode

1loopback

CHAPTER

BASIC

3.1

OPERATION

GENERAL

This chapter contains a functional description of
the DRV11-WA.
The DRV11-WA registers are described
as well as user device and
bus operations necessary to perform DMA transfers.
Figure 3-1 1is
a block diagram of the DRV11-WA.
All descriptions are written to
this diagram.
The chapter ends with a brief description of the
timing associated with DMA transfers.
3.2

FUNCTIONAL

3.2.1
The

DRV11-WA

DESCRIPTION

Registers

contains

six

registers:

®
°

Word Count Register (WCR),
Bus Address Register .(BAR),

°
°
°

Extended Bus Address Register (BAE),
Control Status Register (CSR), and
Input and Output Data Buffer Registers

(DBRs).

3.2.1.1 Word Count Register
(WCR)
-- The WCR is a 16-bit read/
write register that controls the number of transfers.
This register is loaded
(under program control)
with the 2's complement
(negative number)
of the number of words to be
transferred.
At
the

end of each transfer,
the word count register
is
incremented
(if WC INC ENB is high).
When the contents of the WCR is incremented to zero, transfers are terminated, READY is set, and if the

interrupt
is

enable

bit

word-addressable

3.2.1.2

set,

interrupt

requested.

The

WCR

only.

_Bus Address Register

(BAR)

The

BAR

15-bit

read/

write register.
This register
is loaded
(under program control)
with a bus address
(not including address bit @)
that specifies
the location to or from which data is to be transferred.
The BAR
is
incremented after each transfer
(if BA INC ENB is high),
and
can be incremented across 32K memory boundaries by means of the
extended address feature of the DRV11-WA.
Systems with only 16
address bits will "wrap-around" to location zero when the extended
address

bits

are

incremented.

systems

with

extended

ing, an overflow in the BAR will increment the
the CSR when in Q18 mode or
the BAE register
The BAR is word-addressable only.

XAl6,
when

3.2.1.3

The

Extended
Bus Address Register

read/write

is selected.
bits 16-21 of

6-bit

accessible
when extended addressing mode

(Q22)

This register
a bus address

only.

BAE

is loaded (under program control)
that specifies the location to or

which data is to be transferred.
If
increment the extended address bits in
addressable

(BAE)

address-

XAl7 bits in
in Q22 mode.

with
from

the BAR overflows, it will
Q22 mode.
The BAE is word-

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3.2.1.4

Control/Status

gister used
interface.

contrel

dress

(Q22)

(CSR) -+ The CSR is a 16-bit
functions and monitor the status of

the

rethe

Bit 00 is a write-only bit and always reads as a zero.
Bits 0¢1-06, 78, and 12 are read/write bits, while bits 07, 09-11,
and 13-15 are read-only bits.
Bit
14
can be written
to a
=zero.
Bits 04 and 05 are the extended addressing bits.
TIf extended adCSR

mode

functions

byte-

and

1is

are

selected,

fully

bits

described

and

Chapter

are

read-only

The

CSR

bits.

both

word-addressable.

3.2.1.5
Input and Output Data Buffer Registers (DBRs)
-- The two
DBRs are 16-bit registers.
The input DBR is a read-only register;
the output DBR is a write-only register.
Data is loaded into the
input

DBR

memory

under

DMA

Q-bus

processor.

the

put

DBR

program

the

from

memory

control

device.

user's

device

control

and

the

Conversely,

under
the

DMA

subsequently

DRV11-WA,

or
is

data

control
by the
processor,
and

Q-bus

transferred

under program control
written into the outDRV11-WA,
or
under
read
by
the
user's

The

input and output DBRs interface to the user's device
by means of two separate 40-pin I/0 connectors.
These connectors
may be cabled together
(for maintenance purposes)
to function as a

read/write register.
and are byte-

The

input

and

word-addressable.

3.2.2

User

Lines

There

are

address

Interface
50

interface

these

and

output

DBRs

the

same

bus

lines
(25
per
connector)
between
the
DRV11-WA and
the user's
1/0 device.
Of
these
lines,
32
are
1/0
data lines, three are for status, and 15 are for control.
A brief

description

interface

lines

follows.

Mnemonic
@g

OUT

Description

OUT

1IN

TTL

data

One

high.

TTL

lines from the DRV11-WA.
Correspond to ODBR <G0:15>.

data

device.
<A@A:15>.
STATUS

output

Three

input

One

lines

high,

from

the

Correspond

user's

1IDBR

‘

TTL

status

input

1lines

from

the

user's device.
The function of these lines
is defined by the user.
Correspond to CSR
<9:11>
FUNCT

Three

TTL

vice.

The

fined

<A1:03>
INIT

(Table

One

TTL

user's

4-1).

output

lines

function
the

user.

(Table

4-1).

output

line;

device.

the

these

user's

lines

Correspond

used

de-

1is

de-

CSR

initialize

the

Description

Mnemonic
INIT

One

TTL

output line; present
or when FUNCT
2
1is
Used for interprocessor

asserted
one.

when

INIT 1is
to
a
buffer appliwritten

cations.
One TTL input line from the user's device.
This
line is normally low for word
transfers.
During byte transfers this line con-

AQ0

trols

address

bit

00.

One TTL output line to the user's device.
BUSY is low when the DRV11-WA DMA control
logic is requesting control of the Q-bus or

BUSY

when a DMA cycle is
in progress.
to-high transition indicates end of

One TTL output line to the user's device.
When the READY line goes low, DMA transfers

READY

may

initiated

Two

user's

device.

from the user's
the Q-bus cycle

transfers.

and

codes

possible

cycles

are

listed

bus

Bus

and

normal

for

the

DMA
four

Codes

DATI
DATIO

Y]
1

a
a

DATO

DATOB

DMA

device.

follows.

Cco

eration,
user's

Cycle

One TTL input
This line is

CYCLE

the

TTL input lines
These lines control

C@d

SINGLE

A lowcycle.

line from the user's device.
internally pulled high for

transfers.

SINGLE

CYCLE

For

burst

driven

mode

low

op-

the

device.
CAUTION

When SINGLE CYCLE
is driven 1low, total
system operation is affected because the
Q-bus becomes :dedicated to the DMA de-

vice; other

memory

devices,

refresh

including...the

function,

cannot use

MOS

the

bus.
WC

INC

ENB

One TTL input line from the user's device.
This line is normally high to enable incrementing the DRV11-WA word counter.
Low inhibits

incrementing.

3-4

Description

Mnemonic
BA

INC

ENB

One

TTL

input

This
line
crementing

from

normally

the

One

TTL

input

One

TTL

input

This

bus

line

transfers,

transfers.

3.2.3
There
these
16
38

bits.

lines are
bus lines

Six

lines

used for
follows.

are

used

control

the
of

this

user's

device.

line

from

the

user's

device.

driven

set

high

READY,

Corresponds
:

for

BDAL

line

ini-

terminate

DMA

and

request

an
enable bit
is
to execute DMA

CSR

<13>

(Table

the DRV11-WA;
16 of
that carry data and

extended

signals.

Mnemonic

Low

from

LSI-11 Bus Lines
are 38 LSI-11 bus signal lines used by
are multiplexed and bidirectional lines

address

in-

counter.

interrupt
if
the
interrupt
set.
This line must be low
4-1).

device.

enable

line

A low-to-high transition
tiates a DMA request.

ATTN

user's

high

address
incrementing.

inhibits

CYCLE REQUEST

line

address

A brief

bits,

description

while

the

Description
BDAL

16 bus data/address lines.
An address 1is
first placed on these lines followed by the
data.
These lines are asserted when driven
low.

BDAL

16,

Two

bus

memory

BDAL

18-21

lines
by

used

the

asserted

when

Four

lines

bus

memory.

address

DRV11-WA.

beyond

These

32K

lines

of
are

low.

used

These

address

lines

are

beyond

128K

asserted

when

low.

BDOUT

One
bus
1line;
when
cates
that data
is
lines and an output
to

BRPLY

One

the
bus

bus

master)

line;

for

taking

asserted

BDIN
or
BDOUT
and
transactions.
It is
device

asserted
(low),
indiavailable
on
the
BDAL
transfer
(with respect

address

(low)

place.
in

response

1in
response
to
generated by the

recognition.

BIAK
slave

Mnemonic

Description
One
bus
1line;
when
asserted
(low)
during
BSYNC time,
indicates an
input
transfer
(with respect to the bus master).
Requires

BDIN

BRPLY
response.
BDIN
is
asserted
the bus master is ready to accept data
the

slave.

When

indicates
that
occurring.

asserted

interrupt

One bus line; asserted
master
to
indicate
that

BSYNC

address

the

progress

BDAL

until

from

BSYNC,

operation

(low)
by the bus
it
has
placed
an

lines.

BSYNC

The

transfer

negated

(high).

One bus line; asserted (low) during address
time
to
indicate
that
an
output
sequence
(DATO or DATOB)
is to follow.
BWTBT 1is

BWTBT

also asserted during data
dresing during a DATOB.
One bus line;
line when
its
request,
and

BIRQ

BIRQ
vice
BIAKI,

without

when

BIAKO

time

for

byte

ad-

device asserts
(low)
this
interrupt enable,
interrupt
ready
flip-flops
are
set.

informs the LSI-11
is requested.

processor

that

ser-

Two bus lines; one is interrupt acknowledge
in, the other is interrupt acknowledge out.
BIAKI is generated by the LSI-11 processor
in response to BIRQ.
The processor asserts
(low)
BIAKO which
1is
routed
to
the
BIAKI
pin of the first device on the bus.
1If the

device
BIAKO

1s
is

not

requesting

passed

(as

BIAKI)

an
to

interrupt,

the

de-

vice.

One bus line; asserted (low) by the LSI-11
processor when addressing a device for pro-

BBS7

gram-controlled
transfers.
The
DRV11-WA
can assert BBS7 and address other devices
on the LSI-11 bus without processor intervention.
BDMGI,

BDMGO

Two

bus

lines;

one

DMA

grant

in,

the

other
is DMA grant out.
The LSI-11 processor dgenerates BDMGO which
is
routed to

the

BDMGI

the

device

pin
is

the

first

requesting

bus

the

device.
bus,

1f
will

inhibit passing BDMGO to the next bus
vice.
1If the device is not requesting

dethe

bus,

the

it will
device.

3-6

pass

BDMGO

(BDMGI)

Description

Mnemonic
processor

connected

BSACK

One

bus

line;

LSI-11

BSACK

clear

initialize
the

by the LSI-11

(low)

asserted

line;

One bus

BINIT

devices

bus.

asserted

(low)

DMA device 1in response to the LST-11 processor's BDMGO signal, indicating that the
DMA device 1s bus master.

a device asserts this signal

One bus line;

BDMR

and

DMA requests

for

to become bus master.

User's I/0 Device to Q-Bus Memory Transfer

3.2.4

(DATO or DATOB)

Data transfers from the user's I1/0 device to the QO-bus memory are
Figure -2 1illustrates the data flow for a DMA
DMA transfers.

Referring to Figure 3-1, DMA transfers are
DATO or DATOB cycle.
initialized under program control by loading the DRV11-WA WCR (in
2's complement) with a count equal to the number of words to be
transferred;

(and BAE if Q22

loading the BAR

for word storage;

starting memory address

is selected)

with the

for

and setting the CSR

transfers.

The user's

1/0 device must

set ATTN low

the CSR is written to a "one",

device

(high

conditions

for

Section

normal

3.2.2),

the

DMA

and

are

causes

DRV11-WA

INC

transfers),

then

(C@,

BITS and control bits
INC ENABLE)

A0,

latched

asserts

ENB,

and

the

into

INC

the C#,

CYCLE

REQUEST.

bus master,

assert

then

then,

asserting

address

BSYNC.

The

the DRV11-WA removes

INPUT

BDMR,

BDAL

LSI-11

¢to

DATA

BA INC ENABLE, WC

the

processor

asserts

(at

BDMGO

The DRV11-WA becomes bus master

the DRV11-WA performs a DATO or

the memory

The

CYCLE

(refer

lines

CYCLE RENUEST sets CYCLE and

asserts BSACK and negates BDMR.
The processor
bus grant sequence by negating BDMGO.

SINGLE

ENB,

the respective DRV11-WA registers

is received as BDMGI.

placing

then the GO bit of

Cl and SINGLE CYCLE,

the high-to-low transition of BUSY).

which

(ZERO),

READY goes low and the user's 1/0

lines,

then

from

and

the

DATOB bus

cycle by

the

address;

asserting

BWTBT,

and

BDAL

lines,

neg-

memory decodes

the address

terminates

the

ates BWTBT (BWTBT will remain active for a DATOB) and then places
Memory
the user's input data on the BDAL lines and asserts BDOUT.
In response to BRPLY, the
receives the data and asserts BRPLY.

DRV11-WA negates BDOUT and then removes the user's input data from

Memory now negates BRPLY, the bus cycle is terthe BDAL lines.
minated, and the bus is released when the DRV11-WA negates BSACK
and

BSYNC.

the end

the

first

transfer,

the DRV11-WA WCR and

BAR are

in-

cremented

(for normal DMA transfers), BUSY goes high, while READY
remains low.
With BUSY high and READY low, the user's I/0 device
can initiate another DATO or DATOB cycle by again asserting CYCLE

REQUEST.

DMA

transfers

zero and generates
bit is set.

can

continue

interrupt

until

request,

the

increments

interrupt

USER'S
DEVICE

DRV11-WA

<«— DATO OR DATOB <——

LSI-11 BUS

enable

[

WCR

the

\L> DATA FLOW —»

<::

::>

MEMORY

LSi-11

PROCESSOR

CS-3962

Figure

3-2

Flow Diagram

DMA DATO/DATOB Data

3.2.4.1
Interrupts -- When the WCR increments to zero, READY goes
high and the DRV11-WA generates an interrupt request (if the interrupt

the

circuits

interrupt

(interrupt

are

request

enabled).

The

(BIRQ)

asserting

acknowledge).

response places a
and negates BIRQ.

BIAKI

Q-bus

received

processor

BDIN
by

responds

followed

the

vector address on the BDAL lines,
The Q-bus processor receives the

DRV11-WA

BIAKI

and

asserts BRPLY,
vector address

and negates BDIN and BIAKI.
The DRV11-WA now negates BRPLY, while
the procesor exits from the main program and enters a service program

for

the

DRV11-WA as

indicated

3-8

the

vector

address.

Interrupt

requests

from

the

DRV11-WA

occur

for

the

following

con-

ditions:

When the WCR'increments to zero.
rupt

the

end

designated

This is a normal

number

inter-

transfers.

When

the user's
I1/0 device asserts ATTN.
This is a special condition
interrupt which overrides
the WCR or,
if
the independent
interrupt jumper
is
installed,
may
inde-

pendently

cause

interrupts.

When

a
non-existent memory
location
is
DRV11-WA.
This
condition
interrupt
is
BRPLY is received from the 0Q-Bus memory.

Interrupts

are

explained

greater

detail

addressed
by
the
produced
when
no

Chapter

this

manual.
NOTE

As of module CS Revision C, the DRV11-WA
module will no longer generate an inter-

rupt

one

the

bit

without

the

CSR

written

simultaneously

setting
the GO bit.
In earlier module
revisions,
setting the
IE bit without setting
the GO bit
simultaneously would
generate

spurious

written to
ignore
should be modified

interrupt.

this
to

Software

first

process

interrupt
the

inter-

rupt.

3.2.5

OQ-Bus

DMA

transfers

manner

Memory

User's

from

the

Q0-Bus

similar

memory

transfers.

DATIO

DATI

first

word

The

user's

CSR

set,

C#,

I/0

Transfers
(DATIO
the user's I/0

described

3-3

Under

program

with

count

BAR

loaded

come.

device
goes

must

data

control,

equal

the

CSR

set

for

ATTN

low

(zero).

set

and

user's

the

with

The

low

for

illustrates

loaded
will

READY

lines

that

Figure

cycle.

(Figure 3-1)
is
fers, while the
the

Device
memory

the

DATI)
occur

device

I/0

device

flow

for

the

DMA

DRV11-WA

WCR

number

starting

user's

I/0

trans-

address from
transfers.

device

Then,

which

with

the

conditions

the

(refer

to
Section 3.2.2)
for a DATI or a DATIO,
and
conditions the WC INC ENB, BA INC END, SINGLE CYCLE (high for normal DMA transfers),
and asserts CYCLE REQUEST.
BUSY from the
DRV11-WA goes low and the user's control bits are latched into the
DRV11-WA.
quest.

3.2.4,

When

the

performed

the

The

When

DRV11-WA
(the

the

becomés

the

BDAL

becomes

following

then

request

DRV11-WA

address

taken

DRV11-WA
the

bus

bus
reSection

master.

master,

location

and

BDMR,
which makes a
as
described
in

arbitrated

describes

memory
lines

asserts

DATI

DATI).

DATIO

The

bus

cycle

DRV11-WA

places

from which
the
first
word
is
asserts
BSYNC.
Memory
decodes
and

3-9

latches

the

BDAL

the

address.

lines

BDAL

lines

gates

BRPLY and

data
the

bus

and

the memory

accepted
cycle

The

asserts

the

and

the

DRV11-WA
BDIN.

and

then

Input

the memory

DRV11-WA

and

DRV11-WA negates

release

the

bus.

removes

data

asserts

the

now

BRPLY.

BDIN

BSACK

and

BSYNC

OUTPUT

DATA

The

address

placed

negated.

The

from
the

input

Memory

ne-

terminate

BITS

user's I/0
register.

device are stored in the DRV11-WA output data
These bits can be read by the user's device

low-to-high

transition

for

the

buffer
at the

BUSY.

At the end of the first transfer,
the DRV11-WA WCR and BAR
(or
BAE,
if extended
addressing
is
selected)
are
incremented,
BUSY
goes high, while READY remains low.
The user's device can initiate another DATI or DATIO cycle by again setting CYCLE REQUEST.
DMA transfers to the user's device can continue until the WCR increments to zero and causes an interrupt request to be generated
(see Section 3.2.4.1).

<
—»

DATIORDATIO

—»

DEVICE

USER'S

LSI-11 BUS

(

> DRV11-WA

—C

&L DATA FLOW <—
<

|
>

MEMORY

LSi-11
PROCESSOR

CS-3963

Figure

3-3

DMA

DATIO/DATI

Data

Flow

Diagram

3.3

TIMING

Input

and

through
gle

output

3-8.

cycle

and

timing

for

timing

diagrams

The

burst

user-initiated.

mode

the

DRV11-WA

show

operations

user

which

shown

Figures

3-4

signal

timing

for

can

either

program-

sin-

LOAD WCR

LOAD BAR

INT ENABLE

——————/

cocs

INC ENABLE

]

READY

W\ \)

CYCLE REQ

s MIN

‘p(
)G
)i
DATA FROM DRV11-WA 7///////////‘/4 E‘_ 2403
DATA FROM USER

(IF DATO(B))

(IF DATI OR DATIO)

WORD TRANSFER

BYTE TRANSFER
CS-4722

Figure

3-4

DRV11-WA

Single

Cycle,

User-Initiated,

Timing

Diagram

LOAD WCR

‘7

LOAD BAR

INT ENABLE

_.____/
sS

WC/BA

INC ENABLE

SINGLE C.YCLE

%/////A

READY

\
(W

VAR A
|

DATA FROM DRV11-WA %//////////—/{X i‘*m "y

S
X

¢
X

(IF DAT! OR DATIO)

WORD TRANSFER

BYTE TRANSFER
€S-4723

Figure

3-5

DRV11-WA
Diagram

Single

Cycle,

Program-Initiated,

Timing

LOAD WCR

LOAD BAR

INT ENABLE

————-/7

Co.C1

////M

INC ENABLE
N

SINGLE CYCLE

Z////A

READY

Tus MIN

7////71\?\

DATA FROM USER

—

fi
e

(IF DATO(B))

DATA FROM DRV11-A /////////////fi e f,.“.fl " X

(IF DATI OR DATIO)

o .

CYCLE REQ

WORD TRANSFER

BYTE TRANSFER

* NOTE: If W2 jumper is installed, the DRV11-WA will relinquish bus mastership and re-request
mastership after every four words transferred.

CS-4724

Figure

3-6

DRV11-WA Burst

Mode,

User-Initiated,

Timing

Diagram

LOAD WCR

LOAD BAR

ATTN

Z Z ZZX

INT ENABLE

-——-——/
X

4_/\(:/

J—\

/_\

j—\__

WC/BA
INC ENABLE

SINGLE CYCLE

READY

BUSY

DATA FROM USER

?7///”&

(IF DATO(B))

DATA FROM DRV11-WA ///// /
/
//
/‘% = AN nix

X
|

(IF DATI OR DATIO)

WORD TRANSFER

BYTE TRANSFER

* NOTE: IFW2 jumperis installed, the DRV11-WA will relinquish bus mastership and re-request
mastership after every four words transferred.
CS-4725

Figure 3-7

DRV11-WA Burst Mode,

Program-Initiated,

Timing Diagram

cveeqrn

LD IDB H

160 nS —P'{

A\
r

RDIDB L

OUTPUT DATA (READ DATA FROM MEMORY) LATCH TIMING TO.
THE USER'S DEVICE (ODBR).

NOTE:

DATA OUTPUT STARTS HERE.

READ DATA (WRITE TO MEMORY) INTERNAL LATCH TIMING (IDBR).

*1 AND *2 CANNOT BE ACKNOWLEDGED FROM USER SIDE. TIMING FROM
*1 TO *2 1S APPROXIMATELY 150 nS.
CS-4904

Figure

3-8

DRV11-WA

DATIO

Timing

Diagram

CHAPTER

PROGRAMMING

4.1
This

GENERAL
chapter

presents

basic

programming

information

for

the

DRV11-WA.
The types of programming instructions,
the use of the
registers, program interrupts, and special program considerations
are presented.
4.2
All

PROGRAMMING INSTRUCTIONS
programming instructions used

used

for

programming

4.3

DRV11-WA

Six

registers

The

for

are

used

Word

Count

Bus

Address

the

(Q-Bus

the

(WCR),
(BAR),

(BAE),

Input

(DBRs).

and

while

addressing

mode

address.

access

BAR.

WCR
4,3.1
Load the 16-bit

the

DMA data

Output

output

WCR,

DRV11-WA:

Address Register
Control/Status (CSR), and

input

may

Bus

and

processor

DRV11-WA.

REGISTERS

Extended

dress

the

Data

data

BAR,

buffer

and

(Q22)

access

Buffers

CSR

unique

selected,

the

BAE

for

The

BAR

and

BAE

WCR

with

transfers.

registers

have

the

2's

the

end

INC

ENB

one

(if

made,

the

WCR

incremented

quested.

The

WCR

not

the

BAR

and

BAE

reading/writing,
are

cremented

read/written

complement

each

zero

ad-

the

must

same

first

alternately.

number)

the WCR

the

bus

extended

(negative

When

and

I1f

you

DMA cycle,

high).

same

addresses.

last

in-

transfer

interrupt

re-

byte-addressable.

4.3.2
BAR
Load the
15-bit
BAR with
the address
that
specifies
the memory
location into which the first word is written, or from which the
first word is read.
Following the transfer of each word, the BAR

incremented

higher

two,

sequential

INC

memory

(if

word

the BAR overflows,
the

CSR

it will

ing

(022)

the

and

"wrap-around"

and

transfers,

"wrap-around"

mode,

addressable.

if
to

driven

increment

BAR

location

the

zero.

user's

high)

the extended

overflows,

location

ENB

location.
zero.

the

mode,

1if

address

bits

extended

will

increment

the

BAE

bit

AG®

used

for

byte

The

BAR

Address

device.

point

18-bit

address-

not

byte-

BAE

4,.3.3

is selected,

(Q22)

If extended addressing mode

load the 6-bit BAFR

with the address that specifies the memory location into/from
the

written/read.

first word

the

which

overflows,

BAR

will increment the BAE extended address bits and "wrap-around" to
As of module CS
The BAE is not byte-addressable.
location zero.
"one".
a
Revision C, BAE bit 15 will always read as
4.3.4

CSR

Table

4-1.

The 16-bit CSR is monitored for interface status and loaded with
Figure 4-1 shows the
The CSR is byte-addressable.
control bits.
The function of each bit is described 1in
CSR bit assignments.
DBRs

4.3.5

the user's
1/0 drive

4.4

I1/0 device

(output DBR).

(input

words

DBR),

Both DBRs

byte-addressable.

and

are word-

data

16-bit

the

hold

DBRs

The

PROGRAM

from memory

INTERRUPTS

the

user's

the CSR

.
address and

(IE)

from

memory

share the same bus

interrupts are enabled by setting bit

DRV11-WA

transfer

for

Interrupts can occur when the READY
(Figure 4-1 and Table 4-1).
interrupts are enabled when ATTN is
independent
if
or
set,
bit is
set.

The

Word

CSR

4.4.1

Word

READY bit

READY

4.4.2

count

overflow

ERROR bit

interrupt

zero

Count

the

CSR at

the

CSR ERROR Bit

When

CSR bit

and

within

200

Bit

will

set

generated

(NEX)

the

set

(special

when

the DRV11-WA WCR

the

reasons:

set,

set.

non-existent

addressed

(NEX)

location

memory

cycle

does

not

occur

ERROR bit

when

the

user's

the

increments

WC OFLO sets

DMA cycle.

CSR

1is

condition).

overflow).

two possible

for

(ATTN)

from

interrupt).

(word count

15)

set

when

end

(Bit

can

bit

location

ad-

not

received

20
u

performing

ATTN bit

drives

15)

WC OFLO
and produces

When

(normal

Overflow

CSR bit

(bit

request

The CSR ERROR bit

dressed

when:

set

DATO

bus

DATIO bus

cycle.

sets

CSR

ATTN high.

the

I1/0

after

device

ATTN
an

user-defined

independent

enabled,

function

interrupt

that

request.

can

When

utilized

independent

generated

regardless

generate

interrupts

the

are

state

READY.

4.5

FUNCTION

AND

STATUS

BITS

There are three function bits (FNCT 1, 2, 3) and three status
(STAT A, B, C), which the user can employ (at his option) to
trol and indicate the status of the DMA transfers and/or the

bits
conuser

interface.
The function bits (CSR bits @1, @2, and @3) can be
used to transfer control data to the user's interface by means of
the OUTPUT DATA BIT lines of the DRV11-WA.
The status bits (CSR
bits @99, 19, and 11) can be used to indicate the status information

the

DRV11-WA

INPUT

DATA BIT

R |[R/WO| R |R/W| R

W
R | R/W|R/W|R/W|R/W|R/W|R/W|
R |R/W|

NEX

XAD 16

FNCT 1

FNCT 3

XAD 17
|

CYCLE

STAT B

MAINT

READY

STATA | STATC

ATTN

'ERROR

lines.

FNCT 2

LEGEND:

R = READ ONLY
R/W = READ/WRITE

R/WO = READ/WRITE TO O
W = WRITE ONLY. ALWAYS READS AS A 0.
CS-3969

Figure

Table

4-1

CSR Bit

Bit

Format

Functions

Function

GO:

]

g1,

CSR

@02,

Write-only bit;

always

sent

Causes

READY

Allows

DMA operaticn.

FNCT
1.

indicating

Three

the

zero.

user's

device,

issued.

Read/write bits.

output

Cleared

that a command has been

bits

functions.

reads as a

INIT.

available

for

user-defined

Table

4-1

CSR

Bit

a4,

Functions

(Cont)

Function

XADl6,

17:

write bits.
Bits 04 and

the

standard

Q-Buses,

selected,

(Q-Buses

(non-Q22).

Rgad/

Two bits used for extended addressing.
05 increment with the address count when

"wraps-around"

BAR

dressing

For

these bits

For

zero.

extended

addressing

read-only.

are

ad-

mode

1is

¥E: Read/write bit.
1.

Enables

interrupts

occur

when

READY

set.

FEnables

interrupts

occur

when

ERROR

set.*

3. Cleared by INIT.
a7

g9, 19, 11

READY:
is able

Read-only bit.
to accept a new

Set

by WCOFLO.

Set

Cleared

See

Section

(bit

Read/write

bus

cycle:

Set

Cleared

CYCLE

DRV11-WA

00).

bit.

CYCLE

DMA

cycle

Read-only bits.

input bits that indicate
B,
and C user
signals.
the

used

prime

REQUEST.

during

sTAT A,B,C:

INIT.

‘Thrée device

the state of
These bits

status

the DSTAT A,
are
set
and

user.

MAINT:
Read/write bit.
Maintenance
with the MAINDEC diagnostic.

bit

for

use

ATTN:

state

the

ATTN

the

FERROR.

DMA

that

INIT.

CYCLE:

cleared

Tndicates
command:

Read-only

user

4.4.2.

signal;

bit.

sets

Indicates

READY,

the

ERROR.

Table

4-1

CSR

Bit

(Cont)

Function

NEX:
1.

Read/write

ter,

DATIO

Sets

Cleared

ERROR:

See

Section

4.6

LSI-11

The

following

SAMPLE

the

NEX

ATTN

was

INIT

indicates

that

did

not

completed.

receive

bus

mas-

BRPLY

that

READY

(bit

set.

NEX

ATTN

zero.

the

following

special

and

causes

interrupt

removing

the

special

cleared
by writing

cleared

the

bit

user

condition

zero.

device.

4.4.2.

programs

NPR

FOR
DATA

EXAMPLE

‘

are

sample

Q18

BIT

programs

for

the

DRV11-WA.

MODE

TRANSFER

172410
172412

DRVDBR=

172414
172416

PRO=

condi-

13)

(bit

Cleared
follows:

writing

14)

(bit

bit.

one

(bit

Sets

DRVCSR=

WAIT:

cycle

Read-only

DRVBAR=

START:

bit.

memory;

DRV11-WA

~Indicates
tions:

PROGRAM

DRVWCR=

zero

ERROR.

PROGRAMMING

200

Non-existent

Functions

MOV

#-200.,8#DRVWCR

;WILL

MOV

#DBUF , @#DRVBAR

;SET

MTPS

#PRO

; ENABLE

MOV
BIS

#101,@#DRVCSR
#400,@#DRVCSR

;SET IE & GO
; SET CYCLE

WAIT

;WAIT

200

XFER'S

BUFFER
INTR

HERE

ADDRESS

;* SAMPLE PROGRAM FOR 022 BIT MODE
+*

DO A 200 NPR DATA TRANSFER

DRVWCR=
DRVBAR=
DRVBAE=

1724149
172412
172412

PRO=

172414
172416

DRVCSR=
DRVDBR=

START:

WAIT:

MOV

$#-200.,@#DRVWCR

sWILL DO 200@ XFER'S

MOV

#DBUF1,@#DRVBAE

:SET UP EXTENDED BUFFER ADDRESS

TST
MOV
MTPS
MOV
BIS

@DRVWCR
#DBUF ,@#DRVBAR
#PRO
#101,Q@#DRVCSR
#400,Q#DRVCSR

WAIT

:CLEAR BAE FLAG *
:SET UP BUFFER ADDRESS
; ENABLE INTR
;SET IE & GO
; SET CYCLE

;WAIT HERE

* By accessing the BAR, a flag gets set to a one (1) (BAEFLAG=1).
regisThis flag automatically gets cleared by accessing theon BAE
next
your
ter. To ensure that you will be accessing the BAR
m.
progra
your
in
flag
attempt, it is advisable to clear the BAE
(that
ers
regist
This can be done by accessing any of the other
is,

TST

@DRVWCR).

CHAPTER

INTERPROCESSOR

5.1
The

GENERAL
DRV11-WA

can

configured

for

operation

data transfer
link between
two computer
systems
installing jumper W4 and removing jumper W3.
The

DMA

LINKS

parallel-

(Figure 5-1)
link operates

by
in

a half-duplex communications mode; that is,
it has the capability
of transmitting data bidirectionally between the two computer systems,

but

only

5.2

OPERATING

From

word

direction

time.

MODES

hardware

modes:

one

standpoint,

mode,

single

the

cycle

link

mode,

can

and

operate

burst

one

three

mode.

In word mode, information can be passed between two computers in a
word-by-word
sequence controlled by an
interrupt-driven program.
In

the

single

cycle

and

burst

modes

(which

sentially
identical),
the
1link
transmits
a
memory data from one computer to the other.

in
of

the

software

both machines.
The principal difference between
operation is that
in the single cycle mode,
the

obtain

and

burst

mode,

received,

release
the

until

the

bus

DRV11-WA

the

for

holds

requested

each
onto

data
the

4-cycle

transfer

bus

are

once

N-cycle

the two modes
DRV11-WA must
made.

the

bus

transfer

BCO8R CABLE

25 FT MAX.

£
J2

DRV1I1-WA

DRVII-WA

|«—>] 3

—_—

V
Figure

CS-4905

5-1

1Interprocessor

Link

Block

Program

the

grant

pleted.

es-

contiguous
block
of
DMA transfer is used

com-

dent

control

puters must
information

control
the

its

own

interface.

written

word

count

the

flow

indepen-

in the link configuration maintains

Each of the computers

direction,

The

programs

ensure

setting

for

the

two

compatibility

terms

bus

respective

address

computer

com-

registers,

interfaces

and

with

DRV11-WA.

the

environment

linked

provided

computers

CSR

configuration.

CSR

bits

(#3:01)

Table

5-1

shows

are

Bit

the

CSR

correlation

Status

links.
Bits

Meaning of CSR Bit

DR11-W/DRV11-B
Function

Bit

Single

Status

at Transfer-Initiating
Computer

Cycle/

Set

Burst NPR

Transfer

Clear

INTR

Set

(Interrupt)

(STAT B)

into

functional

CSR Function and
Link Operation

(STAT A)

(ENCT

and

Transfer-

Responding
Computer

(7#3:71)

the DRV11-WA interprocessor

Correlation of
Interprocessor

Initiating
Computer

(FNCT

the

bits

loaded

CSR Bits

Transfer-

recom-

in the other DRV11-WA of the

link

5-1

means

(and

between

information appears

When

these bit relationships for
Table

software

communication

Figure 4-1 and Table 4-1 for

the

VAX-system

the

(see Chapter 4,

this

one DRV11-WA,

the

established

respectively

(11:09),

systems)

PDP-11

the

for

mended

Single

cycle

NPR

transfer
-

Burst

NPR

transfer

Interrupt

re-

sponding computer

Request

Bit

1
(FNCT

Bit

9
(STAT

5.2.1

Setting

Word

CSR bit

DRV11-WA.
rupt

all

puter,
ATTN

and

ATTN generates
is

(as

Set Clear

the

transmitting

(ATTN)

CSR bit

ERROR,

DATO

which

DATI

DRV11-WA

the

sets

both

receiving

turn generates

inter-

set.

transfer

ACLO

modes,

transmitted

described

word-mode

ODBR until

(FUNC

(STATUS

three

and

During

Mode

CSR bit
2

DATI/DATO

above)

transfers,

when

power

causes
the

failure

the other
an

data

read by the other computer.

occurs

computer,

where

one

com-

the

sets

interrupt.
must

maintained

1In general,

this operation

requires
that
the
receiving
computer
send
back
a
"handshaking"
signal to indicate that it has read the data, and that the transmitting computer cannot modify the data in its ODBR.

The

interrupt

capability

conjunction with the ODBR
a word-transfer interrupt

incorporated

the

CSR

can

to pass information between
sequence (Figure 5-2).

TRANSFER - INITIATING COMPUTER
1.

LOAD ODBR WITH FIRST WORD.

SET CSR BIT 2*.

in
in

TRANSFER - RESPONDING COMPUTER

used

computers

ENTER INTR SERVICE ROUTINE.

READ CSR.

READ IDBR.

SET CSR BIT 2.

ENTER INTR SERVICE ROUTINE.

LOAD ODBR WITH SECOND WORD.

CLEAR, THEN SET CSR BIT 2.

> REPEAT.

REPEAT.

*BIT2 CALLS FOR FAR - END INTR.
CS-4906

Figure

5-2

1Interrupt

Sequence

for

Word

Mode

Interprocessor

Link

Single Cycle
5.2.2
NPR transfers by the

may

flow

either

link may be

direction.

requested

The

NPR

by either

cycles

computer,

always

occur

and

pairs: the first cycle is a DATI
(read from memory) by the transmitter; the second cycle is a DATO (write into memory) by the receiver.
These alternating pairs of cycles repeat until the entire
buffer has been transmitted.
The computer
generate the
by

hardware

The

designated as a link transmitter sets GO and CYCLE to
first NPR cycle.
Subsequent NPR cycles are generated
handshaking

programming

given

Figure

between

sequence

used

the

DRV11-WAs.

initiate

block

transfer

5-3.

When the transmitter has read the data word from its memory and
loaded the word onto its ODBR, BUSY is deasserted.
BUSY is connected to CYCLE RQ at the receiving DRV11-WA.
The trailing edge
of BUSY triggers an NPR cycle that writes the data word into the
receiver's

memory.

Completion

the

write

cycle

deasserts

BUSY

in the receiving DRV11-WA.
BUSY returns to the transmitting
DRV11-WA as CYCLE RQ A.
This alternating sequence continues until
the word count register overflows and halts the block transfer.

TRANSFER - INITIATING COMPUTER

TRANSFER - RESPONDING COMPUTER

TRANSMITS MESSAGE DESCRIBING DATA

ACKNOWLEDGES DATA TO BE

TO BE EXCHANGED (LENGTH, DIRECTION, ETC.)

EXCHANGED.

NS
L
DATA TRANSMITTER

DATA RECEIVER

SETS UP ITS OWN WC AND BA.

LOADS CSR:

SETSGOTO1 TO CLEAR

READY.
®

READY.

CLEARS FNCT1TOO

TO INDICATE DATI.
®

SETSFNCT1TO1TO
INDICATE DATO

SETSFNCT3TO1TO

INDICATE SINGLE CYCLE

SETSFNCT3TO1TO
INDICATE SINGLE CYCLE

TRANSFER.

SETSGOTO 1 TO CLEAR

TRANSFER.

SETSCYCLETO1TO
INITIATE FIRST NPR CYCLE.
CS-4907

Figure

5-3

Single

Cycle

5.2.3
Burst Mode
The
NPR burst mode

DRV11-WAs.

The

Transfer Sequence

requires

programming

that

FNCT

procedure

for

Interprocessor

cleared

similar

the

Link

both

single

cycle.

Clearing FNCT 3 drives SINGLE CYCLE H low on the other DRV11-WA.
During the first NPR cycle, the SINGLE CYCLE flip-flop clears and
stays

clear

When the
bus from

the

last

NPR

cycle,

single cycle
releasing.

until

flop

cleared,

during

which

NOTE

N-cycle burst mode
VAX/DRV11-WA link.

not

WCOF

effectively

supported

occurs.

holds

the

5.3

PROGRAMMING

The

programming

basically
However,

the

characteristics

same

when

two

registers

those

of
the
interprocessor
1link
are
a
single DRV11-WA configuration.

DRV11-WAs are interconnected,
the programming of
slightly modified,
as explained
in the following

sections.
5.3.1
The

Word

Count

WCR

function

ever,

the

INC

ENB

(WCR)

the

signal

same

asserted

the

non-link

continually

mode.

link

Howmode.

5.3.2
Bus Address Register
(BAR)
The basic
function of
the BAR
is unchanged when
the DRV11-WA
is
operated in link mode.
However, since
' the hardware configuration
of the link permanently sets bit 00 to 0, interprocessor transfers
are for full words only.

5.3.3

Output

Data

Buffer

the

ODBR/IDBR

link

mode.

Data

(ODBR/IDBR)
The

basic

DRV11-WA
5.3.4

function

operated

Control

and

Status

remains

Buffer

unchanged

when

the

(CSR)

In interprocessor link operation,
the CSR bits are defined somewhat differently than in link operation.
The differences are:
BIT

(GO)

When

BITS

set

transmit

1,2,2

FNCT

(FMNCT

itself,

receive

conditions

the

DRV11-WA

for

either

transfer.

1,2,3)

receiving

DRV11-WA.

the

other

set

DRV11-WA,

DRV11-WA.

one

and

DRV11-WA,

initialized

transmitting

cleared
1in

the

soft-

ware.
FNCT

Sends
sets

interrupt

STATDS

puter,

thereby

computer's

TIE

request

ATTM,

causing

bit

to the companion computer:
RFADY in
the companion com-

and

set,

interrupt

request

the

and

interrupts

are

ATTN

enabled.
FNCT

FNCT

transfers

the

companion

computer

cycle
BITS

4,5

(XBA

The

functions

non-1link
tions.

16,

the

companion

burst

mode;

performs

computer

DMA

FNCT

performs

DMA

the

transfers

a
in

single-

mode.
17)

modes.

these

bits

Refer

are

Chapter

the

same

Table

both

4-1

for

1link

and

defini-

BIT

The function of this bit is the same in both link and nonlink modes.
Refer
to
Table 4-1
for
bit definition.
When
set, this bit permits the DRV11-WA to generate an
interrupt
request 1f STATUS B sets
the companion computer.
BIT

being

set

of this bit is the same in both link and nonRefer to Chapter 4,
Table 4-1 for bit defini-

This

bit

initiate

the

associated

DRV11-WA

set

used
in

conjunction

single

with

cycle

the
bit

and

burst

transmitter.

(GO),

transfers

When

immediate

this
NPR

occurs.

19,

(STATUS

STATUS

This bit is read by the computer initiating the
transfer.
1If Status C is set, the responding computer initiates a DATO; if the bit is cleared, the
responding computer initiates a DATI.

- STATUS

Reads FNCT 2 of the companion computer.
When set,
this bit indicates that an interprocessor interrupt

STATUS

has

been

requested

also

sets

and

request

ATTN
if

the

Bit

11
(STATUS A)
transfer;
if bit
transfer

bit
rupt

the

companion

READY,

and

bit

set.

indicates

computer.

causes

This

inter-

a burst mode
single cycle

NPR
NPR

indicated.

(ATTN)

The function of this bit is the same in
modes.
ATTN is also set by either FNCT
panion computer.
ATTN generates ERROR.
BIT

FNCT

when
cycle

BIT

result

(CYCLE)

bit

BITS

(READY)

The function
link modes.
tion.
BIT

the

link

ACLO

and

non-1link

the

com-

both

link

and

non-

both

link

and

non-

The

link

function

modes.

this

bit

the

same

this

bit

the

same

Refer

Chapter

Table

4-1

for

bit

defini-

tion.
BRIT

(ERROR)

The

link

function

modes.

Refer

Chapter

tion.
5-7

Table

4-1

for

bit

defini-

DRV11-WA GENERAL PURPOSE
DMA INTERFACE
USER’'S GUIDE

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