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EK-DRVWA-UG-001

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Document:	DRV11-WA General Purpose DMA Interface User's Guide
Order Number:	EK-DRVWA-UG
Revision:	001
Pages:	42
Original Filename:

OCR Text

EK-DRVWA-UG-001

DRV11-WA

General Purpose
DMA Interface
User's Guide

Prepared by Computer Special Systems’
of
Digital EqQuipment Corporation

1st Edition, August 1984

The information in this document is subj ect to change without notice and should not be
construed as a commitment by Digital Equipment Corporation. Digital Equipment

Corporation assumes no responsibility for any errors that may appear in this document.

Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation:

dlifoli[t/a]1 M=t

RSX.

DEC

DIBOL

DECmate

MASSBUS

UNIBUS
VAX

DECset

PDP

VMS

DECsystem-10
DECSYSTEM-20

P/OS
Professional

VT
Work Processor

Rainbow

CONTENTS

Page

o
s
o

DEVICE ADDRESS
INTERRUPT

SELECTION

VECTOR

ADDRESSING MODE
MODULE

ADDRESS

SELECTION

INSTALLATION

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i

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Priority RequirementsS ....ceceecececccccsscccesss
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INSTALLATION

SYSTEM CONSIDERATIONS

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INTRODUCTION

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DESCRIPTION

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Extended Bus Address Register (BAE) .ccceceeccesn
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PROGRAMMING INSTRUCTIONS
DRV11-WA REGISTERS
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FIGURES

Title

DRV11-WA

wWN

Figure No.

DRV11-WA Device
DRV11-WA
Format

Interface

and

Address

Select

Interrupt Vector
5

Diagram

.....

Switch Locations

Format

Address Select
S

BSED

DRV11-WA Connector Pin Assignments ..ceeee.
DRV11-WA Block Diagram ...cceceescoccesccesses
DMA DATO/DATOB Data Flow Diagram ...eeeeeo.

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W
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Simplified

DRV11-WA Connector

" DRV11-WA as Interprocessor Link ...ceeececececscses
DRV11-WA Single Cycle, User-Initiated, Timing
Diagram
&

DRV11-WA
Timing

CSR

BSEeEDSNeN

Program-Initiated,

User-Initiated,

Timing

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'DRV11-WA Burst Mode,
Dlagram

Diagram'Q’U'VO’.'#Ufl"‘0'00*‘0."00'.*.'0.0‘

DRV11-WA Burst Mode,
Dlagram

Single Cycle,

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#® ® @ B & 0 & 5 © # B * B & B S G & & H B & @ & & 0 B S 6

Format

Program-Initiated, Timing

& & B " b & B0 b
B

TABLES

Table
2-1

4-1

Title

No.

Page

Recommended Cable Assemblies
CSR Bit Functions
®

e s @
&

2"’"‘2
4-3

CHAPTER 1
INTRODUCTION

GENERAL DESCRIPTION

l.1

The DRV11l-WA 'is a general-purpose Dlrect Memory Access (DMA) interface for transferring 1l6-bit data words directly between the
LSI-11/23, LSI-11/23-PLUS (includes Micro PDP-11), and LSI-11/73
memory, and a user's I/0 device.
Data Transfer Out (DATO) or Data

- Transfer In (DATI) takes place over the LSI-1l1l bus after a DMA request, once the DRV11-WA becomes bus master.
Burst modes, byte
addressing, and read-modify-write operation
(DATIO)
are possible
with the DRV11-WA.
The DRV11-WA features switch-selectable device
and vector addresses, and two 40-pin connectors that provide simple interfacing
to the user's I1/0 device.
(The DRV11-WA is compatible

There

with

are

both

six

standard

registers

and extended

LSI

in the DRV11-WA.

They are

WordwCQufit Register (WCR),

Bus

Exténded Bus Address Register (BAE) ,

Control/Status

Input

Address

and

Data

(CSR),

Loading the
transfers,

Buffer

initialized

WCR

with

Registers

the

under

(DBRs).

2's

the

Data transfers
DMA logic.

may

CSR with
now

the

complement

proceed

desired
under

whereas

program control

Loading the BAR and BAE with the first
- which data is to be transferred, and

follows:

and

The CSR and DBRs are word- and byte-addressable,
BAR, and BAE are only word-addressable.

DRV11-WA operation

(BAR),

Output

buses.)

control

WCR,

by:

the

address

function

the

number

from

bits.
of

the

DRV11-WA

Figure

1-1

" DRV11-WA

(DATO)
For

shows

and

data

the

transfers

DATO cycle

primary

user's

I/0

take

interface

device.

place

(DRV1I1l-WA

when

memory

vice presets the CONTROL BITS
address
increment enable,
Cl,

signals

DMA

input

the

processor

transfer),

(word

count

DATI

cycle memory

manner,

except

during

the bus

that

the

DRV11-WA

user's

the

output

READY.
I1/0

de-

enable,

bus

ATTN),
and
When CYCLE

asserts
REQUEST

into the input DBR, the CONTROL
DMA control, and BUSY goes low.

transfer

output data

cycle.)

clears

the

increment

C@,
A@9,
and
the LSI-11 bus.

CYCLE REQUEST to gain use of
'is asserted, input data is latched
BITS are latched into the DRV11-WA

between

(DATI)

handled

latched

into

the

similar

output

DBR

When

the DRV11-WA becomes bus master,
a DATO or DATI cycle is performed directly to or from the LSI-11 memory location specified by
the BAR and BAE.
At the end of each cycle, the WCR and BAR are
incremented and BUSY goes high while READY remains low. A second

DATO

asserts

until

DATI

cycle

CYCLE

REQUEST.

the

and

the

set)

WCR

performed
DMA

when

transfers

the

user's

will

continue

I/0

to zero, at which time READY
generates an interrupt
(if
interrupt

LSI-11

SPECIFICATIONS
following specifications

purposes

and

Physical
Dual height,

are

again

goes high
enable
is

processor.

If
burst mode
is
selected
(SINGLE
CYCLE
low),
REQUEST is required for the complete synchronous
specified number of data words.
1.2
The

device

asynchronously

increments

DRV11-WA
the

subject

only
one
CYCLE
transfer of the

|
and

particulars

are

for

informational

to change without notice.

single width,

s
|
extended length module.

Dimensions:

Circuit Card
Length:
Height:
Width:

Weight:

21.6
12.7
1.3

|
cm
cm
cm

|
(8.5
(5.0
( .5

Circuit Card Plus Handle
in)
in)
1in)

Length:
Height:
width:

22.8
13.2
1.3

cm
cm
cm

(8.9
(5.2
( .5

in)
in)
in)

215 grams

User I/0 Connections:
Mounting

Two 4@-pin connectors

Requirements:

Plugs

directly

into

LSI-11

LSI-11 expansion backplane.
Electrical

Logic

Power

LSI-11

Bus

Requirements:
Loading:

1.8

Presents

+5V + 5%

one bus

1-2

load

(nominal)

backplane

30IA30

ASNg

ieobewjiesj1ulg

STO01HLNO8D

JOV4H3LNI
.

SNdTOHLNOD

S3HAQV/Viva-91S1i8

1FS130NA3DY

S118 SN1V1S

AQV3Y

sSN8 1L 1-1$1

1-3

User

Loading:
Input Data

Lines

1 TTL unit load each
HIGH = Logic one
LOW

Logic

zero

~Input Control

Lines

TTL unit load each

HIGH = Logic one
LOW = Logic zero
Output

Data

Lines

10 TTL unit loads (drive)
HIGH = Logic one
LOW = Logic zero

Output Control

Lines

13 TTL unit loads
HIGH = Logic one
LOW = Logic zero

Module Type:

each

(drive)

each

M7651

Operational:

Transfer Mode: DMA or programécontrolled with interrupts
Data

Transfer

Up
Up

to
to

Rate:

250,000
500,000

16-bit words
words

16-bit

per
per

second

in burst mode*

single cycle mode

Environmental

Temperature:

Storage: -49° to 66°C («-~4gO to 15g°F)
operating: 5° to 50°c (41° to 122°F)

Relative Humidity:

While

doing

master

and

10%

burst

holds

to 95%

mode

the

bus

noncondensing

transfers,
until

the

entire

DRV11-WA

becomes

transfer

bus

complete.

This action may potentially
lock out other devices from accessing the bus while the transfers are ongoing.
This mode of
operation is consistent with the operation of the 18-bit predecessor

product,

DRV11-B.

1.3
RELATED LITERATURE
In addition to the M7651 print

set

(MP@1582-01),

the Microcomputer

Processor Handbook and the Microcomputer Interface Handbook contain useful information for installing and operating the DRV11-WA
general-purpose DMA interface.
Handbooks may be ordered from the
nearest

Digital

Equipment Corporation

Sales

Office.

CHAPTER

INSTALLATION

2.1
GENERAL
Installation of the DRV11-WA general-purpose DMA interface consists of selecting
the device
and
interrupt vector
addresses,
selecting mode of operation (18- or 22-bit addressing), and then
inserting the interface into an LSI-11 processor system.
2.2

SYSTEM CONSIDERATIONS

- Before

1nsta111nq

tion must be given
quirements.

the

DRV11-WA

to bus

into

loading,

LSI-11

power,

system,

priority,

and

consideraspace

re-

2.2.1
LSI-11 Bus Loading
DRV11-WA presents one bus load to the LSI-11 bus.
Fifteen bus
loads can be handled by the LSI-11 bus; therefore, the user must
determine the existing LSI-11 bus load when installing additional
The

LSI-11 modules.

2.2.2
The

Power

DRV11-WA

Requirements
requires

DRV11-WA is obtained
2.2.3

1.8

|
A

+5V

(nominal).

from the LSI-11 system power

Power

for

supply.

the

Priority Requirements

Each device on the LSI-11 bus has an interrupt and DMA
based on its relative position from the processor.
Since

priority
the user

may

install the DRV11-WA on the bus along with other devices that
use the same interrupt or DMA prlorlty, the user must bear in mind
that when more than one device is requestlng service, the device

electrlcally nearest
the
LSI-11 microprocessor
has
the highest
priority and will be serviced first.
In addition,
if the REV1l
DMA refresh option is used, the REV11l must be at a priority level
higher
than
that of the DRVll«WA.
Refer
to
the Microcomputer
Processor Handbook

for detailed

information on

the REV1l

options.

2.2.4
Space Requlrements
The DRV11-WA requires one double height module slot.

2.3
The

USER I/0 CABLES
DRV11-WA has two 40pln connectors which provide the interface
to the user's device.
Two cable assemblies are required.
It is
recommended that cable assemblies from Table 2-1 be used to connect the DRV11-WA to the user's device.
The listed cables are
terminated
(one or both ends)
with H856 40-pin connectors that
mate with the connectors on the DRV11-WA.
Cable selection is determined by the type of connections used on the user's device.
The desired cable length
(XX)
must be specified when ordering.
(Lengths longer than 25 feet are not recommended for use with the
DRV11-WA.)
Cables may be ordered from the nearest Digital Equipment

Corporation

ordered

Sales

additional

Office.

cost.

Non-standard

length

cables

may

Table

2-1

Recommended Cable Assemblies

Cable No.

Connectors

Type

BCO8R-XX

H856 to H856

Shielded

BCO4Z-XX
|

H856 to open
end

Shielded

2.4

Standard Lengths

(ft/m)

flat

25 ft

flat

6, 10, 15, 25 ft
(1.839, 3.9506, 4.575,

10,

12,

24,

(4.3065, 1.830, 3.0549,
3.660, 6.109, 7.625 m)

7.625 m)

DEVICE ADDRESS SELECTION

The DRV11-WA contains
l.
2.
3.
4.
5.
6.

six

registers:

The WCR,
The BAR,
The BAE,
The

CSR,

The

input DBR,

The

output

and

DBR.

registers must be addressed

These

for data

and

the LSI-1l1l processor.

and

the DRV11-WA

between

status

transfers

The BAR and BAE

use the same address.
The two DBRs use the same address.
register addresses are sequential by even numbers and are as

The
fol-

lows.

BBS7

WCR
BAR
BAE
CSR
DBRs

1
1
1
1
1

Octal Address
XXXXX0
XXXXX2
XXXXX2
XXXXX4
XXXXX6

The assigned DMA interface base address
1is 77241@8.
The user
selects a base address for assignment to the WCR and sets the device address selection switches on the DRV11-WA module to decode
this address.
The remaining BAR, BAE, CSR and DBR addresses are
then properly decoded by the module as they are received from the
LSI-11

processor.

Figure 2-1 shows the location of the device address selection
switches on the DRV11-WA module.
Switches are set to the ON
(closed) position for bits to be decoded as "ONE" bits in the base

address.

switches

dress
for

Bits

set

select

decoded

the OFF

format

and

the device address

"ZERO"TM

(open)

bits

position.

in the

address

presents the switch-to-bit

selection

switches.

have

Figure 2-2 shows

their

the ad-

relationship

VECTOR ADDRESS, Q22/Q18
SELECTION SWITCHES

DEVICE ADDRESS
SELECTION SWlTCHES

E40

E50
m

C8-3970

DRV11-WA Connector and Switch Locations

Figure 2-1

DECODED FOR
1 0F4

DECODED BY BBS7

’

SELECTED BY SWITCHES
13

DEVICE
1
appress | ON

SELECTION | OFF
SWITCHES |

REGISTERS
05

]

I
2

CONTROL

OFF = “ZERO"
ON = “ONE"
CS-3958

Figure 2-2

DRV11-WA Device Address

Select Format

2.5

INTERRUPT VECTOR ADDRESS

Vector

addresses

module.

Figure

0@-1774

SELECTION

are

reserved

for

the

location

LSI-11

system

users.

The DRV11-WA is assigneg vector address 124
The user selects
the interrupt vector address by means of swigches on the DRV11-WA
2-1

shows

the

vector

address

se-

position.

Figure

2-3

lection switches.
Vector address selection switches are set to
the ON (closed) position for bits to be encoded as "ONE" bits in
the vector address.
Bits encoded as "ZERO" bits in the address

have

their

shows

the

switches

address

relationship for
2.6

set

select

the vector

the

OFF

format

(open)

and

address

presents

the

selection switches.

SELECTION

ADDRESSING MODE

switch-to-bit

The user selects 18- or 22-bit addressing by setting E40 switch 10
OFF (OFF=@) for 18-bit addressing, or ON (ON=1) for 22-bit addressing
2.7

(see Figure

MODULE

2-3).

INSTALLATION

With the exception of the first two/four slots

(the LSI-11 proces-

sor always occupies the first two/four slots depending on CPU
TYPE), the DRV11-WA can be installed into any slot (see Section
However, 1if REV11l DMA refresh
2.2.4) of the LSI-11 backplane.

option is used, the DRV11-WA must be at a lower priority than the
REV11l.
When inserting the module into the backplane, make sure
that

the

deep

notch

the module

seats

and

the

J1 and J2 are shown
1, Section 1l.2.

against

the

connector

block rib.
Do not insert or remove the module with power applied.
After performing the initial turnon (see Section 2.8), connect the
user's

I/0

cables

DRV11-WA

I/0

connectors.

Connector locations for the DRV11-WA are shown in Figure 2-1.
assignments for
fied in Chapter

Figure

2-4

and

are

speci-

4TH

OCTAL

1ST

OCTAL

DIGIT

2ND

3RD

OCTAL

DIGIT

DIEIT

09 '08

DIGIT

(OOR 4)
PREASSIGNED
1

AS ZEROS

06 05
04 03 02 01 00

T I T T TTTT T

|ON1
SELECTION
|
switches |OFF

ADDRESS

OFF = “ZERO"

NOT __? | l

ON = “ONE"

USED

ON = 22-BIT ADDRESS
OFF
= 18-BIT ADDRESS
CS-3959

Figure

2-3

DRV11-WA

Interrupt Vector Address Select Format

2-4

HWrN WHN |r

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@inbia§-Z VYM-ITA¥A103o9uo)urdsjuswubrssy
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*—e

o—=o

3mwl.l..".H.VH—I.SEF7.pNT1.LO0-.NVlAILdDS
11 SS

1l SS

INITIAL TURN-ON

2.8

After completing the module installation, turn on the LSI-11 and
With no I/0 cables connected and using the
initialize the system.
LSI-11 terminal and operating ptocedures, perform the following
quick operational verification.

Load the addresses of the WCR, BAR, CSR, AND DBRs through

minal

will

examine

and

terminal

system

the

locations.

the

ter-

indicate
the following:

22-Bit

18-Bit

WCR contents will be 000000
BAR contents will be 0600001
BAE contents will be 0000030

WCR contents will be 000000
" BAR contents will be 0060001

CSR contents will be 127200
DBRcontents will be 177777
2.

The

)

CSR contents will be 127200
DBR contents will be 177777

The WCR, BAR, and BAE (if 22 bit addressing is selected)
can be loaded with data from the system terminal and the
corresponding data read back on the terminal.
BAR bit @
will read as a one (1) with no I/0 cables connected.
NOTE

xxxxx2)

BAE

(ADDRESS

then

examining

the

access

BAE.

the

BAR

1is

ADDRESS

read

(ADDRESS

first

xxxxx2)

again

Xxxxxx2

and

The user's I/0 device cables can now be connectea Eo;the DRV11-WA
(Figure 2-1).

2.9

DIAGNOSTIC

PROGRAM

The check procedure performed

Section 2.8

does not completely

Complete module operation

verify the operation of the DRV11-WA.

can be verified through the use of the diagnostic software program

AC-T974B-MC.

The program can be loaded into the LS1-11 system by

output

DBR

means of any standard loadable device.
nance cable (not longer than 25 ft) is
to

the

input

for

checking

AC-T974B-MC.

A BC@5Lor BC@6R mainterequired to loop the DBR

the

1/0

data

path.

plete descr1pt1on of the diagnostic software program and its
plementation

is provided

com-

im-

When you execute the AC-T974B-MC diagnostic, you must select soft-

ware Switch 12 (SW12) of the SWR to correspond with your selection
SW12 must be ON (ON=1) to enable 22of hardware Switch 10-E44.

bit address testing, or OFF (OFF=0) to enable 18-bit address testing.

The default

setting

S10-E40

ON = 22-bit addressing

OFF = 18-bit addressing

is OFF.

SW12 of Diagnostic

ON = Enable 22-bit address testing

OFF = Disable 22-bit address testing

The diagnostic
control

will

character.

continue

run

until

terminated

with

CHAPTER
BASIC

GENERAL
3.1
This chapter

The
bus

contains

functional

DRV11-WA registers are
operations necessary to

description

All descriptions

this diagram.
The chapter ends with
timing associated with DMA transfers.

the

DRV11-WA.

brief

are written

description

to
the

FUNCTIONAL DESCRIPTION

3.2.1

The

described as well as user device and
perform DMA transfers.
Figure 3-1 is

a block diagram of the DRV11-WA.

3.2

OPERATION

DRV11-WA Registers

DRV11-WA contains six

)
®
°
®
®

registers:

Word Count Register (WCR),
Bus Address Register (BAR),
Extended Bus Address Register (BAE),
Control Status Register (CSR), and
Input and Output Data Buffer Registers

(DBRs).

3.2.1.1
Word Count Register (WCR) -- The WCR is a 16-bit read/
write register that controls the number of transfers.
This register
is
loaded
(under
program
control)
with
the
2's complement
(negative number)
of the number of words to be transferred.
At
the end of each transfer, the word count register is incremented.

When the contents of the WCR is incremented to zero,
terminated,

interrupt

READY

set,

and

is requested.

the

interrupt

The WCR is

transfers are

enable bit

set,

word-addressable only.

3.2.1.2
Bus Address Register (BAR) - The BAR is a 15-bit read/
write register.
This register is loaded (under program control)
with a bus address (not including address bit @)
that specifies
the location to or from which data is to be transferred.
The BAR
is incremented after each transfer and can be incremented across
32K memory boundaries by means of the extended address feature of
the

DRV11-WA.

around"
mented.

BAR will

Systems

with

only

address

bits

will

"“wrap-

to location zero when the extended address bits are increOn systems with extended addressing, an overflow in the

increment

the BAE.

The BAR

word-addressable only.

3.2.1.3
Extended Bus Address Register (BAE) -- The BAE is a 6-bit
read/write register accessible when extended addressing mode (Q22)
is selected.
This register is loaded (under program control) with
a bus address that specifies the location to or from which data is
to

transferred.

extended

address

bits.

the

BAR

overflows,

The

BAE

will

word-addressable

increment

only.

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3.2.1.4
gister

Control/Status
used

interface.

Bits

Bit 00

01-06,

and

13-15

"Bits

control

08,

are

and

The CSR is

and monitor

is a write-only bit and
12

are

read-only

(CSR)

functions

are

the

read/write

bits.

Bit

extended

16-bit

status

always reads as a

bits,

the

can

addressing

while bits

07,

written

bits.

rethe

zero.

09-11,

zero.

extended

ad-

dress mode
(Q22)
is selected, bits 04 and 05 are read-only bits.
CSR functions are fully described in Chapter 4.
The CSR is both
" byte-

and

'3.2.1.5
DBRs are
the

word-addressable.

Input and Output Data Buffer Registers (DBRsS) -- The two
16-bit registers.
The input DBR is a read-only register;

output

input

DBR

the

memory under

the

DBR

program

The

by the

the

and

Data

DRV11-WA,

LSI-11

under

data

and

interface

The

input and output

address

are byte-

and

word-addressable.

Lines

and

3.2.2

User

Interface

There

are

1interface

1lines

(25

per

the

program

read

the

DBRs

these

interface

lines

Mnemonic
gg

oUT

the

user's

device

These connectors
to function as a

the

connector)

same bus

between

FUNCT

15 oUT

INIT V2

follows.

B, C

16 TTL data output
One = high,

TTL data

device.

Three

input

One =

TTL

lines

from

lines

the

from

DRV11-WA.
.

the user's

high.

status

input

lines

from

the

user's device.
The function of
is defined
by the user.

these

Three

user's

de-

1lines

initialize

the

TTL

vice.
defined
INIT

the

are 1/0
A brief

Description

@ IN - 15 IN
STATUS A,

the

under

user's

DRV11-WA and the user's 1/0 device.
Of these lines, 32
data lines, 3 are for status, and 15 are for control.
description of

control

into

DRV11-WA,

by means of two separate 40-pin I/0 connectors.
may be cabled together (for maintenance purposes)

read/write register.

into

transferred

written

by the

processor,

DBRs

loaded

DMA control

output

subsequently

Conversely,

under

input

device

processor.,

from memory

control

device.

write-only

user's

DMA control

LSI-11

output

lines

The
function
by the user.

One TTL output
user's device.

line;

One TTL output line;
asserted or
one.
Used

plications.

to the

of these

lines

used

present when INIT is

when FUNCT 2
is written to a
for
interprocessor buffer
ap-

Mnemonic

Description
One TTL input line from the user's device.
This line is normally low for word transfers.
During byte transfers th1s llne

AQQ

controls
One

BUSY

TTL

address b1t
output

line

G@
to

|
the

user's

device.

BUSY is low when the DRV11-WA DMA control
logic is requesting control of the LSI-11

bus

or when

low-to-high
cycle.

DMA cycle
is

transition
|

vice.

Two

A
of

TTL

vice.
for
ed

input

These

cycle

for

the
as

DMA

four

lines

the

user's

de-

the

LSI-11

bus

and

codes

possible bus cycles

are

list-

follows.

and

Cl Codes

Bus Cycle

DATI

)

DATI®
DATO
DATOB

1
@
1

@
1
1

One TTL input
This
1line is

CYCLE

from

control

transfers.

SINGLE

end

One TTL output line to the user's device.
When the READY line goes low,
DMA transfers may be
initiated
by the user's de-

READY

cg,

in progress.

indicates
|

normal

DMA

line from the user's device.
internally pulled high for

transfers.

eration, SINGLE CYCLE
user's device.

For

burst

is driven

mode

op-

low by

the

CAUTION

When

SINGLE

system

LLSI-11

CYCLE

operation

bus

becomes

driven

affected

dedicated

1low,

total

because

the

DMA

device; other devices, including the MOS
memory refresh functlon, cannot use the
bus.
~
WC

INC

ENB

One

‘This

TTL

input

line

crementing

inhibits

line

from

normally

the

high

the DRV11-WA word

incrementing.

user's device.

enable

counter.

inLow

Mnemonic
BA

INC

Description

ENB

One TTL input line from the user's device.
This line is normally high to enable in-

crementing

inhibits
CYCLE

REQUEST

One TTL input
A low-to-high

tiates
ATTN

|
:

the

One

TTL

bus

address

counter.

incrementing.
line from the
transition of

DMA request.
input

line

from

the

Low

user's device.
this line ini-

user's device.

This line is driven high to terminate DMA
transfers,
to
set
READY,
and
request
an

interrupt

the

interrupt

enable

bit

set.

3.2.3
LSI-11 Bus Lines
There are 38 LSI-11 bus signal lines used by the DRV11-WA; 16 of
these are multiplexed and bidirectional lines that carry data and
address bits.
Six lines are used for extended address bits, while
16 lines are used for control signals.
A brief description of the
38 bus lines follows.

Mnemonic
BDAL

|
BDAL

Description
15

bus

data/address

lines.

first placed
on
these
the data.
These lines
driven low.
BDAL

16,

18-21

Four

asserted

bus

One

bus

when

lines

of memory.
low.
BDOUT

address

Two bus lines used to address beyond 32K
of memory by the DRV11-WA.
These
lines
are

BDAL

lines followed by
are asserted when

used

These

line;

low.

address

lines

when

are

asserted

beyond

128K

asserted

when

(low),

indi-

cates that data is available on the BDAL
lines and an output transfer (with respect
to the bus master)
is taking place.
BRPLY

One

bus
line;
asserted
(low)
in
response
to BDIN or BDOUT and in response to BIAK
transactions.
It
is
generated
by
the
slave device for address recognition.

Mnemonic

Description
One bus line; when asserted
(low)
during
BSYNC
time,
indicates
an
input
transfer
(with respect to
the bus master).
Re-

BDIN

quires
when

a BRPLY response.

the

bus

master

BDIN is asserted

ready

data from the slave.
out
BSYNC,
indicates

operation

One

BSYNC

When asserted withthat
an
interrupt
occurring.
|

bus line;

asserted

(low)

by the bus

master to indicate that it has placed an
address on the BDAL lines.
The transfer
is
1in
progress
until
BSYNC
is
negated

(high) .

One bus line;
asserted (low)
during address time to indicate that an output se-

BWTBT

quence

(DATO

DATOB)

follow.

BWTBT is also asserted during data
for byte addresing during
a DATOB.

One bus line;
device asserts
(low)
this
line when its interrupt enable, interrupt
request,
and
ready
flip-flops
are
set.
BIRQ
informs
the
LSI-11 processor
that

BIRQ

service
BIAKI,

time

BIAKO

is requested.

Two bus
lines;
one is
interrupt acknowledge in, the other is interrupt acknowledge out.
BIAKI
1is
generated by
the
LSI-11 processor in response to BIRQ.
The
processor

asserts

(low)

BIAKO

which

1is

routed to the BIAKI pin of the first device on the bus.
If the device is not requesting an interrupt, BIAKO is passed (as
BIAKI)

One bus

BBS7

the

line;

device.

asserted

(low)

by the LSI-11

processor when
addressing
a
device
for
program-controlled
transfers.
The
DRV11-WA can assert BBS7 and address other

devices on the LSI-11
sor intervention.
BDMGI,

BDMGO

bus

without

proces-

Two bus lines; one is DMA grant in, the
other is DMA grant out.
The LSI-11 processor generates BDMGO which is routed to
the BDMGI pin of the first bus device.
1If
the device is requesting the bus, it will
inhibit passing BDMGO to the next bus device.
If the device is not requesting the
bus, it will pass BDMGO as (BDMGI)
to the
next device.
3-6

Mnemonic

Description

BINIT

One bus line; asserted (low) by the LSI-11
processor to
initialize or clear devices
connected to the LSI-11 bus.

BSACK

One

bus

line;

DMA device

BSACK

asserted

response

the

(low)

cessor's BDMGO signal, indicating
DMA device is bus master.
BDMR

3.2.4

User's

Data

transfers

DMA

transfers.

DATO

bus

line;

for

DMA

requests

I/0 Device

DATOB

initialized

One

from

the

cycle.

under

3-2

and

asserts

device to
illustrates
the

control

Figure

that

this

prothe

signal

to become bus master.

I/0

Referring

program

device

LSI-11 Memory Transfer

user's

Figure

LSI-11

(DATO or

the

LSI-11
data
flow

3-1,

DMA

the

DATOB)

memory

are

for

DMA

transfers

are

DRV11-WA

WCR

(in

with

the

CSR

for

When the GO bit of the CSR is written to
and the user's I/0 device conditions the
ENB, ATTN,
SINGLE CYCLE
(high for normal

a "one", READY goes
A@G@, BA INC ENB, WC

low
INC

DMA

transfers),

C@,

and

then

the

2's

complement)

transferred;

with

starting memory

count

the

BAR

address

for

equal

(and

word

BAE

the

number

Q22

storage;

and

words

selected)

setting

the

transfers.

lines

(refer

REQUEST.

The

INPUT

CYCLE,

INC

ENABLE,

DATA
WC

Section
BITS
INC

and

3.2.2),
control

ENABLE)

are

bits

(C@,

latched

and

asserts
Cl

into

and
the

CYCLE

SINGLE
respec-

tive DRV11-WA registers
(at the high-to-low transition of BUSY).
CYCLE REQUEST sets CYCLE and causes the DRV11-WA to assert BDMR,
the processor asserts BDMGO which is received as BDMGI.
The

DRV11-WA becomes bus master and asserts BSACK and negates BDMR.
The processor then terminates the bus grant sequence by negating
BDMGO.

bus master, the DRV11-WA performs a DATO or DATOB bus cycle by
placing
the memory address on BDAL
lines,
asserting
BWTBT,
and
then asserting BSYNC.
The LSI-11 memory decodes the address;
then, the DRV11-WA removes the address from the BDAL lines, neg-

ates

BWTBT

(BWTBT

will

remain

active

for

DATOB)

and

user's

input

then

places

the user's input data on the BDAL lines and asserts BDOUT.
Memory
receives the data and asserts BRPLY.
In response to BRPLY,
the

- DRV11-WA

negates

the BDAL lines.
minated, and the
and BSYNC.

BDOUT

and

Memory
bus is

then

removes

the

now negates BRPLY, the bus
released when the DRV11-WA

data

from

cycle is ternegates BSACK

At the end of the first transfer, the DRV11-WA WCR and BAR are incremented (for normal DMA transfers), BUSY goes high, while READY

remains low.
can initiate
REQUEST.

DMA

With BUSY high
another DATO or
transfers

can

and READY low,
DATOB cycle by

the user's I/0 device
again asserting CYCLE

continue

the

3-7

until

WCR

increments

and
is

generates

interrupt

request,

the

interrupt

’

> DRV11-WA

[]

4N
<

\K——» DATA FLOW —»

[sa]

oevice

USER'S

]

«¢—— DATO OR DATOB =w——

17y

enable

set.

zero

bit

MEMORY

LSI-11
PROCESSOR

Cs-3962

Figure 3-2

DMA DATO/DATOB Data Flow Diagram

3.2.4.1
Interrupts -- When the WCR increments to zero, READY goes
high and the DRV11-WA generates an interrupt request
(if the interrupt circuits are enabled).
The LSI-11 processor responds to
the interrupt request (BIRQ) by asserting BDIN followed by BIAKI
(interrupt acknowledge).
BIAKI is received by the DRV11-WA and in
response places a vector address on the BDAL lines, asserts BRPLY,
and negates BIRQ.
The LSI-11 processor
receives
the vector
address
while

and negates BDIN and BIAKI.
the procesor exits from the

vice program for

the DRV11-WA

The DRV11-WA now negates BRPLY,
main program and enters a ser-

indicated by

the vector

Interrupt requests from the DRV11-WA occur for

ditions:

address.

the following con|

When the WCR increments to zero.
This is a normal interrupt at the end of a designated number of transfers.

When the user's I/0 device asserts ATTN.
This is a
cial condition interrupt which may be defined by the
to override the WCR.

When a nonexistent memory location
1is addressed by the
DRV11-WA.
This condition interrupt is produced when no
BRPLY is received from the LSI-11 memory.

Interrupts
are

explained

greater

detail

Chapter

speuser

this

manual.

3.2.5
LSI-11 Memory to User's Device Transfers (DATIO or DATI)
DMA transfers from the LSI-11 memory to the user's I/0 device occur in a manner similar to that described for user's I/0 device to
memory transfers.
Figure 3-3 illustrates the data flow for a DMA
DATIO or DATI cycle.
Under program control, the DRV11-WA WCR
(Figure 3-1)
is loaded with a count equal to the number of transfers, while the BAR is loaded with the starting address from which
the first word will come.
The CSR is set for transfers.
With the CSR set, READY goes low and the user's I1/0 device conditions the C@, Cl lines
(refer to Section 3.2.2)
for a DATI or a
DATIO,
and conditions the WC INC ENB,
BA INC END,
ATTN,
SINGLE
CYCLE (high for normal DMA transfers), and asserts CYCLE REQUEST.
BUSY from the DRV11-WA goes low and the user's control bits are
latched into the DRV11-WA.
The DRV11-WA then asserts BDMR, which
makes

bus

Section

When

the

When

(the

address

following

the

request

arbitrated

described

the DRV11-WA becomes bus master,.

DRV11-WA becomes

performed
the

request.

3.2.4,

the

bus

master,

describes

memory

location

DATI

DATI).

from

which

DATIO

The

bus

cycle

DRV11-WA

the

first

places

word

taken on the BDAL lines and asserts BSYNC.
Memory decodes and
latches the address.
The DRV11-WA then removes the address from

the BDAL

lines and

BDAL

lines

data

negates

the

asserts BDIN.
and

accepted

DRV11-WA

BRPLY

the

and

the

Input data

memory

DRV11-WA

memory

is now placed

BDIN

Memory

BSACK

and

asserts

BRPLY.

and

negated.

negates

BSYNC

The

the

input

termi-

nate the bus cycle and release the bus.
The OUTPUT DATA BITS for
the user's I/0 device are stored in the DRV11-WA output data

buffer
the

low-to-high

These

bits

transition

can

read

the

user's

device

BUSY.

At the end of the first transfer,
the DRV11-WA WCR and BAR
(or
BAE,
if extended addressing
is
selected)
are
incremented,
BUSY
goes high, while READY remains low.
ate another DATI or DATIO cycle by

The user's device can initiagain setting CYCLE REQUEST.

DMA transfers to the user's device can continue until the WCR
increments to zero and causes an interrupt request to be generated
(see

Section

3.2.4.1).

—» DATIORDATIO —»
2]

DEVICE

> ;DW“\”WA

‘

USER'S

<*—

DATA FLOW

MEMORY

LSI-11
PROCESSOR

CS-3963

Figure 3-3

DMA DATIO/DATI

Data

Flow Diagram

3.2.6
Using DRV11-WAs as Interprocessor Links
When you connect two LSI-11 processors together

using

DRV11l-WAs,

you have to initiate the DMA from transmit side, while the receive
side waits for CYCLE to be set.
When BUSY goes high on the transmit side, CYCLE is set on the receive side (see Figure 3-4).

At the transmit side, when you set the GO bit,

READY goes low,

and

CYCLE REQUEST is asserted,
CYCLE REQUEST sets CYCLE and causes
the DRV11-WA to assert BDMR, which makes
an LSI-11 bus request and
causes BUSY to go low.
The transmit DRV11-WA then takes the data
from memory, puts it into the ODBR, and negates BUSY H.
At

BAR

the

(or

end of

BAE

the

first

extended

transfer,

the transmit

DRV11-WA

addressing

are

selected)

WCR

and

incremented,

transmit BUSY goes high, while transmit READY remains low.
BUSY
high at the transmit side sets CYCLE at the receive side and
causes receive BUSY to go low.
With receive BUSY low, the receive
DRV11-WA starts DMA and receives the data into the input DBR for
subsequent

DRV11-WA,

transfer

under

memory

program

under

control

3-10

DMA

control

the

LSI-11

the

receive

processor.

the

sets

end

the

CYCLE

first

the

receive,

transmit

the

side.

receive

This

DRV11-WA to initiate another transfer.
until

the

transmit WCR

increments

BUSY goes
causes

high,

the

DMA transfers can continue

zero

and

generates

rupt request,
if the interrupt enable bit is set.
If

you

"data

initiate

that

1is

the

stored

DMA

from

transmit DRV11-WA takes

the

receive

side,

inter-

you

will

receive

from memory and

puts

transmit

the data

which

transmit

DRV11-WA

ODBR

the

before

the

Figures

3-5

into

the

ODBR.

TRANSMIT

RECEIVE

BUSY H

»| CYCLE H

CYCLE H |

‘

BUSY H

DRV11-WA

DATA

CS-3964

Figure 3-4
3.3

Input

TIMING

and

output

through 3-8.

DRV11-WA as Interprocessor Link

timing

for

the

DRV11-WA

shown

The timing diagrams show user signal timing for sin-

gle cycle and burst mode
mer user-initiated.

operations

3-11

which

can

either

program-

LOAD WCR

-V

LOAD BAR

INT ENABLE

Co.,C1

WC/BA
INC ENABLE

AOO
b

SINGLE CYCLE
s

READY
1us MIN

'CYCLE REQ

BUSY

DATA FROM USER
(IF DATO(B))

DATA FROM DRV11-WA
(IF DATI OR DATIO)

WORD TRANSFER

BYTE TRANSFER
CsS-3965

Figure

3-5

DRV11-WA

Single

Cycle,

User-Initiated,

Timing

Diagram

W%%

LOAD WCR

LOAD BAR

WC/BA
INC ENABLE

A0O

SINGLE CYCLE

READY

—
—

/
—--"""'><

INT ENABLE

7/////]

o e I \l =
_1 s MIN

WORD TRANSFER

BYTE TRANSFER
CS-3966

Figure

3-6

DRV11-WA Single Cycle,
Timing Diagram

Program-Initiated,

LOAD WCR

LOAD BAR

INT ENABLE -

WC/BA
INC ENABLE

AQO

SiNGLE CYCLE o 7///// )

CYCLEREQ

/////
‘j\

BUSY

DATA FROM USER - W
(IF DATO(B))

—ix
—

DATA FROM DRV11-A ////////;////_q
zwnsx

_ - X

(IF DATI OR DATIO)|

WORD TRANSFER
|

Figure

3-7

DRV11-WA Burst

Mode,

—

BYTE TRANSFER

User-Initiated,

Timing

CS-3967

Diagram

LOAD WCR

LOAD BAR

INT ENABLE

/|
X

’7/////X

- coc

INC ENABLE
SINGLE CYCLE

[

\
N\

. READY

cveue REa

7///////:;///////////////////////////

BUSY

/////M

DATA FROM USER

(IF DATO(B))

}I—\

/—\

[—\

/_\

(IF LATI OR DATIO)

WORD TRANSFER

BYTE TRANSFER
CS-3968

Figure

3-8

DRV11-WA Burst

Mode,

Program-Initiated,

3-15

Timing Diagram

CHAPTER

PROGRAMMING

4.1
GENERAL
This chapter

presents

DRV11 -WA.

The

registers,

program

are

types

basic

programming

interrupts,

presented.

and

information

instructions,

special

program

the

for

use

the

considerations

4.2

PROGRAMMING INSTRUCTIONS
programming instructions used for
used for programming the DRV11-WA.
All

4.3
Six

the

LSI-11

processor

may

DRV11-WA REGISTERS
|
registers are used by the DRV11-WA:
Word Count (WCR),
Bus Address (BAR),
Extended Bus Address Register
Control/Status (CSR), and
Input and Output Data Buffers

(BAE),
(DBRs).

The input and output data buffer registers share the same bus address while WCR, BAR, and CSR have unique addresses.
If extended
addressing mode (Q22)
is selected, the BAR and BAE share the same
address.
To access the BAE for reading/writing, you must first
access

the

BAR.

The

BAR

4.3.1
WCR
Load the 16-bit

|
WCR

with

and

BAE

are

read/written

alternately.

the 2's complement (negative number)
of
the end of each DMA cycle, the WCR is inthe last transfer is made, the WCR is inan interrupt is requested.
The WCR is not

DMA data transfers.
At
cremented by one.
When

cremented to zero
byte-addressable.
- 4.3.2

and

BAR

Load the 15-bit BAR with the address that specifies the memory
location into which the first word is written, or from which the
first word is read.
Following the transfer of each word, the BAR
is incremented by two, to point to the next higher sequential mem-

ory

word

increment
zero.

increment
A@@

used

BAR is
4.3.3

location.

the

extended

the
for

1In

extended

addressing

BAE and
byte

18-bit

mode,

address

bits

the

and

BAR

overflows,

"wrap-around"

mode,

the

"wrap-around"

location

transfers,

not byte-addressable.

driven

BAR

the

overflows,

zero.

user's

will

location
it

will

Address bit
device.

The

BAE
If extended addressing mode (Q22)
is selected, load the 6-bit BAF
with
the
address
that
specifies
the memory location
into/from
which the first word is written/read.
If the BAR overflows,
it

increment the BAE extended address bits and

will

‘location
4.3.4

The

zero.

CSR

16-bit CSR

The BAE is not byte-addressable.

is monitored

for

interface

"wrap-around"

status

and

loaded

with

Figure 4-1 shows the
The CSR is byte-addressable.
control bits.
is described 1in
bit
each
of
function
The
assignments.
CSR bit
Table 4-1.

DBRs

4.3.5

The

hold

DBRs

the user's
1/0 drive

the

16-bit data words

I/0 device

(output DBR).

to memory from

transfer

for

(input DBR), or

from memory to the user's

Both DBRs share the same bus address and

are word- and byte-addressable.
4.4

PROGRAM

INTERRUPTS

DRV11-WA interrupts are enabled by setting bit 06 (IE) of the CSR
when the GO bit (bit 08) is issued (Figure 4-1 and Table 4-1).
Interrupts can occur for the following reasons:

Word count overflow (normal

interrupt), and

CSR ERROR bit

(special condition).

(bit 15)

set

4.4.1

Word Count Overflow

4.4.2

CSR ERROR Bit (Bit 15)

An interrupt request is generated when the DRV11-WA WCR increments
WC OFLO sets
to zero and produces WC OFLO (word count overflow).
READY in the CSR at the end of the DMA cycle.
The CSR ERROR bit can set for two possible reasons:

(NEX)

When bit 14

When CSR bit 13

of the CSR is set, or

(ATTN)

is set.

CSR bit 14 is set when a nonexistent (NEX) memory location is ada

dressed

and

within

20 us.

reply from

the

addressed

location

is not

received

us
Bit 14 will set if a DATO bus cycle does not occur 20

performing

after

a DATIO bus cycle.

ATTN bit 13 sets the CSR ERROR bit when the user's I/0 device
ATTN is a user-defined function that can be
drives ATTN high.
utilized to generate an interrupt request.
4.5

FUNCTION AND STATUS BITS

There are three function bits (FNCT 1, 2, 3) and three status bits
(STAT A, B, C), which the user can employ (at his option) to control and indicate the status of the DMA transfers and/or the user
The function bits (CSR bits @1, 02, and 0@3) can be
inter face.
used to transfer control data to the user's interface by means of

the OUTPUT DATA BIT lines of the DRV11-WA.
4-2

The status bits

(CSR

bits
tion

@9, 14, and 11) can be used to indicate
is on the DRV11-WA INPUT DATA BIT lines.

15,14
13

09,08

Inln/wo R |RW| R | R
ATTN

ERROR

06,05

RlR/W R

status

03,02

informa-

R/WR/WR/WIR/WR/WH/W wl

MAINT

NEX

the

STATB

CYCLE

XAD 16

FNCT 2

LEGEND:

R = READ ONLY
R/W = READ/WRITE
R/WO = READ/WRITE TO O
W = WRITE ONLY. ALWAYS READS AS A 0.
CS-3969

Figure 4-1

Table 4-1

Format

CSR Bit Functions

Bit

Function

g1,

CSR

GO:

@62,

Write-only bit;

Causes

Allows DMA operation.

indicating

FNCT 1,
1.

READY

Three

always

that a

reads as a

sent

command

the

zero.

user's

has been

device,

issued.

Read/write bits.

output

bits

available

for

user-defined

functions.

g4,

Cleared by

XAD16, 17:
For standard LSI buses (non-Q22).
Read/
write bits.
Two bits used for extended addressing.
Bits

@04

the

BAR

and 05

dressing

selected,
26

INIT.

IE:

increment with the

"wraps-around"
LSI

buses,

zero.

extended

address count when

For

extended

addressing

mode

ad-

these bits are read-only.

Read/write bit.

Enables

interrupts to occur when READY is set.

Cleared by

INIT.

4-3

1is

Table 4-1

Function

Bit

Read-only bit.

WCOFLO,

ERROR:;

CYCLE:

Read/write bit.

able

13
14

new

command.

Set

(bit 09).

CYCLE

used

prime

Read-only bits.

Three device

the state of
These bits

input bits that indicate
B, and C user signals.

status

the DSTAT A,
are set and

user.

Maintenance bit

bit.

MAINT:

Read/write

ATTN:

Read-only bit.

with the MAINDEC diagnostic.

Indicates

sets READY,

signal;

the

ERROR.

state

for

use

the

Read/write to zero bit.

NEX:

Nonexistent memory;‘indicates that as bus mas-

ter,

the DRV11-WA did

not

receive BRPLY or

Sets

ERROR.

Cleared by INIT or by writing

a DATIO cycle was not completed.

ERROR:
1.

INIT.

SsTAT A,B,C:

ATTN user

INIT,

set by CYCLE REQUEST, cleared during

cleared by the

cleared by GO

DMA bus cycle;

DMA cycle by

Indicates that the DRV11-WA

READY:
is

29, 16,

(Cont)

CSR Bit Functions

that

it to a zero.

Read-only bit.

Indicates

one

tions:

NEX

ATTN

(bit

the

following

special

condi-

14)

(bit 13)

Sets READY

(bit 7)

(bit 6)

set.

Cleared

and causes an interrupt if IE

removing

the

special

condition

follows:

NEX is cleared by writing bit 14 to

ATTN is cleared by the user device.

zero.

4.6

PROGRAMMING

following programs are

;*
; *

SAMPLE PROGRAM FOR Q18 BIT MODE
DO A 200 NPR DATA TRANSFER

DRVWCR=
.

172412

DRVCSR=

172414

DRVDBR=

172416

PRO=

for

the DRV11-WA.

START:

MOV
MOV
MTPS
MOV
BIS

$-200.,@4DRVWCR
#DBUF , @#DRVBAR
#PRO
#101,@#DRVCSR
4400 ,@4DRVCSR

sWILL DO 20¢ XFER'S
;SET UP BUFFER ADDRESS
s ENABLE INTR
sSET IE & GO
s SET CYCLE

WAIT:

WAIT

;WAIT

;¥

PROGRAM FOR Q22 BIT MODE
200 NPR DATA TRANSFER
172410

SAMPLE

DRVBAR=
DRVBAE=

172412
172412

DRVCSR=
DRVDBR=

172414
172416

PRO=

START:

MOV
TST

#-200. ,@#DRVWCR
@DRVBAR

sWILL DO 200 XFER'S
;CLEAR BAE FLAG *

MOV

#DBUF ,@#DRVBAR

SET

#DBUF1,@#DRVBAE
#PRO

sSET UP
sENABLE

MOV
BIS

#101,Q@#DRVCSR
#4000 ,@#DRVCSR

;SET IE & GO
;SET CYCLE

WAIT

sWAIT

accessing

the

This
ter.

BAR,

flag

gets

BUFFER

ADDRESS

EXTENDED BUFFER
INTR

ADDRESS

HERE

set

one

(1)

(BAEFLAG=l).

flag automatically gets cleared by accessing the BAE regisTo ensure that you will be accessing the BAR on your next

attempt,
This can
is,

HERE

MOV
MTPS

WATIT:

|
¢

sample programs

172410

DRVBAR=

DO A
;*
DRVWCR=

EXAMPLE

The

TST

it is advisable to clear the BAE flag in your program.
be done by accessing any of the other registers (that

Q@DRVWCR)
.

& =

DRV11-WA GENERAL PURPOSE

Reader's Comments

DMA INTERFACE

USER’'S GUIDE
EK-DRVWA-UG-001

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