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January 1987

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Document:	DECrouter 200 Technical Guide
Order Number:	EK-DR200-TG
Revision:	001
Pages:	133
Original Filename:

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DECrouter 200
Technical Manual
Order No. EK-DR200-TG-001

January 1987

The DECrouter 200 Technical Manual provides ganeral operating instructions, detailed hardware
logical functions, and diagnostic software information.

Supersession/Update Information:

‘

dlilgliltiall

This is a new manue!

EK-DR200-TG-001
First Printing, January 1987

Tha information in this document is subject to change without notice and shouid not be construed as a commitment by Digital
Equipment Corporation. Digital Equipment Corporation assumes no responsibility tor any errors that may appear in this document.

No responsibility is assumed for the use or reliability of software on equipment that is not supplied by Digital Equipment Corporation or its affiliated companies.

Printed in U.S.A.
The postage-prepaid Readers Comments form on the last page of this document requests the user's critica! evaluation to

assist us in preparing future documentation.
The following are trademarks of Digital Equipment Corporation:

DEC

Micro/RSX

TOPS-10

DECconnect
DECmate
DECnet

MicroVAX
MicroVMS
POP

TOPS-20
ULTRIX-32
ULTRIX-32m

DECsarver
DECtape
DECUS

P/OS
Professional
Rainbow

RSTS

UNIBUS
VAX
VAXmate
VAXcluster

DIBOL

RSX

VAX/VMS

DECwriter

MASSBUS

MicroPDP-11

ThinWire

Work Processor

Bell is a trademark of Bell Telephone Companies.

IBM is a registered trademark of International Business Machines Corporation.
MC680J0 is a trademark of Motorola, Inc.
PC/XT and Personal Computer AT are trademarks of International Business Machinas Corporation.
Tefion is a trademark of E.1. du Pont de Nemours & Company, Inc.

This manual was produced by Networks and Commc ications Publications.

Contents
Proface
DECrouter 200
1.1

DECrouter 200 Introduction. . ... ...

1.1.1

T o1+ S

1.1.2

Programmable Timers ...

... i

1-2

1.2

Ethernet Interface System. ......... ...t

1-2

1.2.1

Local Area Nerwork Controller for Ethernet (LANCE) . ...........
... ...,

1-2

1.2.2

Serial Interface Adaprer (SLIA) ...

1-2

1.2.3

Service Nodeand Load HOSL ... i

1-2

1.2.4

Firmwareand Software . ...

.. e

1-2

1.3

Connector Panel Element Description...............
... ... ....ocoiinns.

i-3

1.3.1

Controls and CONMNECLOS ... . ..ottt

eaaaeans

1-3

1.3.2

)27
10 3 1.

1-4

133

Asynchronous Ports J1 = J8). ...
i
e

1-4

1.3.4

Ethernet Transceiver POrt . ... ...

1-4

1.35

AC Line Voltage Input SelectorSwitch...............

...l

1-4

1.3.6

ACPowerCordReceptacle ..................ocoiieiiine. e

1-4

1.3.7

ACCircuitBreaker.................. ... B

1-4

1.3.8

Power-Up and Initialization......................

...

1-§

1.39

Initialization Sequence. . . ... ..

1-5

1.4

Ethernet Systems . .. ... ... e

1-5

1.4.1

SYStemM EICMENTS ... ... e
e

1-6

1.4.2

Configuration Criteria .. ...... ... . ...

.. .. i

1-8

143

CommunicationsMethods ............ .. .. ... .. ... e

1-9

1.4.4

Network Access and CommunicationProtocol . .................. ... ...

1-9

1.4.5

NEtWOTK ACCOSS . ... ... .ttt
et e
et
e

1-9

1.4.6

Collision Detection ... ... e

1-9

1.4.7

Data Frame FOImMat .. ... . ... i
e

1-10

1.4.8

Ethernet Characteristics .

I-11

...

ittt

citerteai e

. e

1-1
1-1

Self-Test
2.1

General ...
e

2-1

2.2

Self-TestOperatingModes . ...

2-1

2.2

Normal Mode ... ...

2-1

222

ManufacturingMode . ....... . ... e

2-2

223

Inmitialized Mode. ...

... .

2-2

224

Fatal Error Mode . ... . e

2-3

2.2.5

ErrOr Ty PeS ..o

2-3

226

NON

Al BrrOrS. ...
e

2-3

227

Nonfatal Error Status. ...
e

2-3

228

Fatal (Hard) Errors . ...

2-5

229

Using the Diagnostic LED (D2)........

2-5

i
...

Contents-1

2.2.10
2.2.10.1
2.2.10.2
2.2.103
2.2.10.4
2.2.105
2.2.106

Self-Test Program Tests ... .......... ... vt
Processor Register Test — STSCPU_REG_J.....................oonn.
Self-Test UN~JAM Test — ST8JAM_TEST_J................ ..o,
RAM Quick Verify Test — STSQUICK_RAM__J...............cooiiiiinnn,
Extended RAM Test — STSEXTENDED_RBRAM__J .............................
Stuck-at Interrupt Test — STESTUCK__INTERRUPTS_J......................
...
Refresh Timer Test — STSREFRESH_TIMER ............................

2-5
2-6
2-6
2-7
2-7
2-7
2-7

LANCE Register Test —LANSREG_TEST ................. ...
Watchdog Timer Test — STSWD_TIMER ............................n.
General Purpose Timer Test — STSGP_TIMER ............................ols
TestLoader —STSLOADER ........ ... i
PROMCRCTest —STSPROM_CRC ...
NI Address PROM Checksum Test — STSNI_ADDRESS ......................
Parity Logic Test —STOPARITY ...
EEPROM Read/Write Test — STSEEPROM_RW .............................
Reset to Factory Test — STSRESET_TO__FACTORY.........................
EEPROM Checksum Test — STSEEPROM__CS ...............................
Modem Control Signais Test —STSMODEM__CS .............................

2-7
2-7
2-7
2-7
2-7
2-7

2.2.10.18
2.2.10.19
2.2.10.20
2.2.10.21
2.2.10.22
2.2.10.23
2.2.10.24
2.2.10.25
2.2.10.26
2.2.10.27
2.2.10.28

Request-to-Send — Test STSRTS__CTS..................oiin,
LANCE Reject Physical Address Test — LANSREJECT_PHY ..................
1.ANCE Accept Physical Address Test — LANSACCEPT_PHY ................
LANCE Force Collision Test — LANSCOLLISION ..........
... E
Receive CRC Logic Test -—— LANSRCV_GOOD__CRC....................... .
Transmit CRC Logic Test — LANSXMT_CRC...........................0
Rececive Bad CRC Test — LANSRCV_BAD_CRC.............. ..............
LANCE Broadcast Address and Byie Swap Tesi — LANSBROADCAST ........
LANCE Muiticast Address Test — LANSMULTICAST ..........................
External Loopback Test — LANSEXTERNAL_LOOP .........................
Lengrh, Parity, Initialize Sequence — RTSCHAR_LENGTH ...............
..

2-8
2-8
2-8
2-8
2-8
2-8
2-9
2-9
2-9
2-9
2-9

2.2.10.29
2.2.10.30

DUART Transmit/Receive Break Test — RT$BREAK .......................... 2-9
Force Framing Error Test — RTSFRAMING. .................... ... 2-9

2.2.10.31
2.210.32

Force Overrun Error, FIFO Depth Check Test — RTSOVERRUN.............. 2-9
Baud Rates Test —RTSBAUD_RATE .....................................
... 2-9

2.2.10.33

System Exerciser Test — STSEXERCISER .. ... ................
... .......... 2-9

2211

Self-Test ErrorCodes .. .. ... e 2-10

22107
2.2.10.8
2.2.109
2.2.10.10
2.2.10.11
2.2.10.12
221013
2.2.10.14
2.2.10.15
2.2.10.16
2.2.10.17

2-7
2-7
2-8
2-8
2-8

Initialize Program
3.1
3.2

INtroducCtion .. ... . 3-1
Down-Line Load ... .. ... ...
3-1

3.21
322
3.23
3.24
325

Down-Line Load Messages . ..............
.. ... 3-2
Down-LineLoadProcedure........
... ... ... 3-2
Up-LineDump ...
3-3
Up-LineDumpMessages ..............................
i ... 3-3
Up-LineDump Procedure. ............. ... ... ... i 3-3

Status and Error MeSSaBES . . .. ...t 3-4

331
332

Ethernet Loopback Error Messages . ......................ocooiii
i 3-4
NONFatal BrrOrS. . . e 3-4

333
334

335

336
337

Contents-2

... ... 3-5
Load Fazilure or Timeout Error Message . ...........................

Fatal Bugcheck ErrorMessage ...

Timeout, Abort Dump MeSSage ... .......ooooiiuiiaiiiiii

3-S5

i 3-7

Load or Dump Failure Message ... 3-7
Bad Image File Message . ......... ... 3-7

On-Line Debugging Tool (ODT)
4-1
4-1
4-1
4-1
4-2

4.1
4.1.1
4.1.2
4.1.2.1
4.1.22

On-Line Debugging ToOL. . ...
Indtial ReqQUIirements ............oooiiii
Entering ODT ...
Entering ODT from the Self-Test ManufacturingMode ........................
Entering ODT from Router Operating Software ...............................

4.2.1
4.2.2
43
4.3.1
43.1.1

e 4-2
.ooiiiiiiii
Command INPUtEFTOrs . ........i
Command SUMMACY . ..........itiieiiiat
ettt iiiae e eeraans 4-2
Accessing Router Address Space ... 4-4
Memory and Device Register Commands .................. ... 4-5
Examine (E)Command...........
... .o 4-5

4.2

431.2
4313
4.3.2
4.3.2.1

ODT Command FURCHIONS . ........ooiiiiiiii it 4-2

Examine Byte (EB)Command............... ...
Examine Indirect (E@)Command ..................oiiitiiiiiiiiii
CPURegisterCommands ....................
...
i,
CPU Address Register (§An)Command ....... ... ... S

4-5
4-6
4-6
4-6

4322
4.3.2.3

CPU DataRegister ($Dn)Command ....................................
... 4~7
CPU Status Register ($SR)Command........................................... 4-7

433

DumpCommands. ........... ..ot

4-7

4.33}
4332
4.3.33
4.4
4.4.1

Memory Dump(D)Command ..............
... ...
Halt Dump (CTRL/C)Command ........................ oo,
RegisterDump(RD)Command ....................... ...t
ProgramminginODT ...................
Program ControlCommands .................
... ..ol

4-7
4-8
4-8
4-8
4-8

44.1.1

Go(G)Command ........... e 4-8

44.13

Single Step Disable (NS)Command ... 4-9

4.4.2
4.4.2.1
4422
4423
44.24

BreakpointCommands ................. ... 4-9
BreakpointSet (Bn)Command................................ e 4-9
Breakpoint Clear (BCn)Command . ... 4-9
Display Breakpoints (§B)yCommand ...... ................
.. e
4-10
Breakpoint Message . ... ... ... i 4-10

4.4.1.2

Single Step Enable (SS) Command. ... .. e 4-8

Functional/Logic Description
5.1

GEMETAl .
e 5-1

5.2
5.2.1

Microcomputer Logic .. ......... e 5-2
CPUandDataAddressBus ........................ ............ .. e 5-2

5.23

CPU and Data/Address Bus Signal Description................................. 5-4

5.2.4

Power-Up Sequencer LOGIiC ...

5.25

Beset CitCUIITY ... oot

5.2.6

WarmResel .. ... .. S

5.2.7

Reset TOSUME. ... ... o e 5-7

528

System Clock LOGIC .. .. ...

529
5.2.10

Bus Arbitration Logic .. ................ 5-9
Interrupt Control ... ... ...
5-9

52.11
53

Interrupt Vector Addresses ...................
i 5-10
Modem ControlandInterrupts ................
.. ...
i 5-11

5.3.1

Gate Array (DCT7053). . oo 5-12

5.3.2

533

Modem CONMECHION. . ... ..o e= 5-13

5.2.2

Device AdAresses . .........oii it

e 5-2

5-7

e 5-7
5-7
5-8

Contents-3

5.3.4
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
54.8
549
5.4.10
5.4.11
54.12
5.4.13

i 5-14
eii
Null Modem CONNECHION. . . ..ottt
Router Memory SubSystem ............oooiiiiiiiiiiiii 5-16
Address Selection ............oooiiiiii i 5-18
Power-Up Addressing......... ...t 5-20
DUART and LANCE Register Addressing.......................oov
it 5-21
Program Randofa AccesS MEMOTY ............cooiiiiiiiiiiiii
e §5-21
CPU-Initiated Transfer. . ... ...t 5-21
LANCE-Initiated Transfer. ...ttt 5-21
DataTransfer Cycle.........ooiiiiniiiiiiii
i
e 5-22
Dynamic RAM. ... ..o o
et i e 5-22
Erasable Program ROM(EPROM) .......... ..o 5-23
Physical Address Programmable ROM(PAPROM)............................ 5-23
Electrically Erasable Programmable ROM (EEPROM) ......................... 5-23
Write Inhibit . ... 5-23

5.4.14

Asynchronous INerface ..........c.ovvriiiiiiiii it 5-23
DUART Signal Descriptions. . . ........oooiiiiiiiii
i
eanns 5-24

54.15

Receive and Transmit Registers . ... 5-27

MRnA and MRnB Mode Registers .............
... ... 5-28

5.5.1
55.3

MRIA 2and MRIBBit AsSignMENtS. ...t iiiiiiiiiininieanens 5-28
SRA and SRB Status Registers ... 5-30
CSRA and CSRB Clock Select Registers ..........................ocoiiiiin... 5-32

5.5.4

RHRA and RHRB Receive HoldingRegisters .................................. 5-33

5.5.5
557

THRA and THRB Transmit Holding Registers...............................
.. 5-34
Auxiliary Control Register ACR<O7> ..............oiiiiiiinnn
., 5-34
Input and Output Port Registers .................
.. ..o 5-34

558

Input Port Change Register (IPCR) ..., 5-35

5.5.9
5.5.10

Auxiliary Control Register (ACR<03:00>) ...t 5-35

55.11

Output Port Configuration Register (OPCR) .......................ooiiln, 5-36

5.5.12

Output Port Regisier (OPR) ..............oo
i
Interrupt Control and Counter/Timer Registers ..............................
Auxiliary Control Register (ACR<06:04>) .............cooiiiiiienn
e,
Interrupt Status Register (ISR). ...
e

5.5.2

5.5.6

5.5.13

5.5.14
5.5.15

5.5.16
55.17

5.5.18

.. B 5-36

5-37
5-37
5-38
5-39

Interrupt Mask Register .. .. ... ... .. i 5-40
CTUR and CTRL Counter/Timer Registers .. ......................ooei. 5-41
Counter/Timer Startand StopCommands ........................onl
L. 5-41

5.6
5.6.1
56.2

EthernetInterface.......
... ... 5-42
Serial Interface Adapter (SIA) ... 5-42
Loca! Area Network Controller for Ethernet (LANCE) ............
... ... 5-44

5.6.3

Ethernet Interface Features ............ ... oo 5-40

5.6.3.1
5.6.4

DMA Transfers with ProgramRAM .. ................iiiiiiiiiiiiinn, 5-46
Ethernet OperatingModes . ...t 5-47

565
5.6.6
5.9.7

568
5.6.9
5.6.10
5.6.11

Control and Status Register 1 (CSRI)...........
... ..o iiiis, 5-51

5.6.12
5.6.13

5.6.14
5.6.14.1
5.6.14.2

Contents—4

Input Port Status Register (IPSR) ................ ...

Control/Status Register O (CSRO) .. ........oooiiiiiiiii

e 5-49

Control and Status Register

Z(CSK2)..............ooii

Control and Status Register

3(CSR3)...........

i 5-51

...l 5-52

Buffer Management Protocol ...... ...t 5~52
Initialize Block .......... ..
5-53

Mode Register (MODE). . ... ..ottt 5~-54
Physical Address Register (PADR)...................ciiiiiiiiiiiiiiin
it 5-56
Logical Address Filter Register (LADRF) ..., 5-56
Receive Descriptor Ring Address Register (RDRA)............................ 5-56

5.6.14.3
5.6.15
5.6.16

Transmit Descriptor Ring Address Register (TDRA) ..................c.t 5-56
Receive Descriptor Ring ...t 5-57
Transmit Descriptor Ring. ... 5-60

Hardware Description
6.1
6.2

General ... e 6-1
Port Devices Supported By DECrouter 200. .. ..., 6-1

6.5
6.6
6.6.1
6.6.2
6.6.2.1

Device Cables ... .. ... e
DECrouter 200 Specifications ....................o i
PO
T.o
e
ENVIFOMIMENT . ...
e
i
e
TOMPETAIULE . . .ottt
et

6.2.1
6.2.2
6.3
6.4

6.6.2.2

Ordering INFOrMAatION. ...........ooiiiiiiiiiiii
i
e
DECrouter 200 Country Kits. . ........ ...t
DECrouter 200 ACCESSORIES . . ......oieeiiirintii
ittt
eeriearaaeianas
Transceiver Cables. ... .. ... e

6-2
6-2
6-3
6~4

6-5
6-6
6-6
6-6
6-6

0.6.23
6624
663

Altitude .

6-7
Relative HUMIAItY . ... ..o 6-7
Physical Dimensions of the DECrouter 200 System............................ 6-7
Space REQUITEMENTS. ... .. ... i 6-7

Figures

‘

1-1

DECrouter 200 Name Panel View...............
.. e

1-1

1-2

1-3

DECrouter 200 Cable ConnectionPanel ...

1-4

1-4
i-5
5-1

The DECrouter in a Small Office/Computer Room Environment .............. 1-8
Ethernet Data Frame Format. ............ ... ... 1-10
DECenmter 200 LOGIC . ..o 5-3

5-2
5-3
5-4
5-5

DC705. L'ackDiagram. ... .. ... o
DTE-to-DC*® Hardware Configuration ............................ooo
i
Null Mc~em Hardware Configuration . .................... ...,
DECrouter 200 Address Space Allocation. . .............................

5-6

CPU Selection of Router AddressSpace...................ooiiviinnn 5-19

5-7

DUART Receive and Transmit RegisterFormats .............................. 5-27

5-8
5-9

DUART Input and Output Port Register Bit Settings . ......................... 5-35
DUART Inierrupt Control and Counter/Tim:. r Register Settings............
.. 5-38

5-10

$1A Connection to an Ethernet Transceiver..........................o
ol 5-42

5-11

LANCERAPand CSRBIt Settings ..................cooiiiiiiiiiinininnnn. 5-49

5-12

LANCE Initialize Block Format. ....................
.. ... 5-53

5-13

LANCE Receive Descriptor RingEntry................
... ... ... ... 5-58

5-14

LANCE Transmit DescriptorRing . .................. e 5-60

6-1

DECrouter in a Large Office/Computer Room Environment................... 1-7

5-12
5-14
5-15
5-17

Dimensions of the DECrouter 2008ystem . .........................c.
iy 6-8

Tables
1-1

ConnectorPanelElements ..................
...
i

1-2

Ethernet Characteristics ..................c.

1-11

1-3

2-1

Initialized Mode ParameterByte ............... ...

2-2

Nonfatal Error LOnBwWOrd .. ... ... ot 2-4

Contents-5

2-3

2-4

Self-Test DispatchTable ... 2-5
Self-TestErrorCodes ... 2-10

4-1

e 3-6
Router Crash ErrorCodes. .............oooii i
ODT COMMANMS . ... ..oventit ettt et
in
et
renes 4-3
Router Address Ranges. .. ...t 4~4

5-1

Daia Strobe Controlof DataBus ......... ...

5-2

5-8

Reset SignalsandFunctions .. ... 5-7
SystemClockFunctions ..........................o0 e 5-8
Input Modem RegisterFormats ... 5-13
Output Modem Register Formats ...l 5-13
DTE-to-DCE Connection Signals............. e 5-13
DTE-to-DTE Connection Signals..........................n 5-15
Programmable Array Logic Functions ...l 5-20

5-9

Summary of DUART Register Functions ..............................oooleL. 5-24

5-10
5-11
5-12

MRIAand MRIBBit Assignments. ...,
Mode Register MR2A and MR2ZB Bit Assignments .............................
Status Register SRA and SRB Bit Assignment .................................
Clock Select Register CSRA and CSRB Bit Assignments .. ... e
Clock SelectRegistersAandB ...
Auxiliary Control Register ACR<07> . ...................... e
IPCR Port Change Register BitSettings .......................................

5-29
5-30
5-31
5-32
5-33
5-34
5-35

5-24

Auxiliary ControlRegister ................... ...
Output Port Configuration Register (OPCR) .........................
Auxiliary Control Register ACR<05:04> ... .. P
Interrupt Status Register (ISR)..............
...
i
SIA and Ethernet Transceiver InterfaceSignals ...............................
LANCE and SIA Interface Signals. . ...l
LANCE Operating and Data/Address Bus Signals. . ............................
Control and Status Register O(CSRO)............. ...
.

5-36
5-30
5-39
5-40
5-43
5-43
5-45
5-50

5~-25

Control and Status Register 1 (CSR1).........................

5-26
5-27

Control and Status Register

5-28

Mode Register Bit SEttings ...t 5-55

5-29

Receive Descriptor Ring Address (RDRA) Bit Settings ........................ 5-56

5-30

Transmit Descriptor Ring Address (TDRA)Bit Settings .....................
.. 5-57
Receive Message DescriptorOBitFunctions . .......................... e 5-58

3-1

5-4
5-5

5-6
5-7

5-13

5-14
5-15

5-16

5-17
5-18
5-19
5-20
5-21
5-22

5-23

5-31
5-32

.. 5-51

2(CSR2).....................l 5-51

Control and Status Register 3(CSR3)...................coii
. 5-52

Receive Message Descriptor 1 BitFunctions . ................................. 5-59

5-33
5-34

Receive Message Descriptor 2 Bit Functions . ...............................
.. 5-59
Receive Message Descriptor 3 Bit Functions . .. .................... ..., 5-59

5-35

Transmit Message Descriptor 0 Bit Functions. ................. e 5-60

5-36
5-37

Transmit Message Descriptor § Bit Functions..................... ......... .. 5-61
Transmit Message Descriptor 2 Bit Functions. .. ... T e 5-61
Transmit Message Descripior 3BitFunctions.. ............................... 5-62
DECrouter 200 Hardware Units ... 6-2
DECrouter 200 Country Kits. .. ............ ... i 6-2

5-38
6-1
6-3
6—4

Contents~6

6-§

DECrouter 200 ACCESSOTIS .. ... ...ttt
i 6-3
DECrouter 200 Power Ratings .................
...
i 6-6

Preface

The DECrouter 200 Technical Manual provides ger - ral operating instructions, detailed hardware
logical functions, and diagnostic software information. The DECrouter 200 is also referred to as
the router throughout this manual.

intended Audience
The inanual is for use in training, field service, and manufacturing. The depth of technical information requires previous training or experience with Ethernet networks and with Digital VAX-11 or
PDP-11 architecture.

Manual Organization
The manual is divided into the following six chapters:

Chapter 1

Introduces the DECrouter 200 and the Ethernet communications system.

Chapter2

Explains the self-test program diagnostic modes and test sequences.

Chapter 3

Describes how the initialize program handles down-line loading and up-line dumping. Chapter 3 also explains status messages and error messages.

Chapter4

Explains the on-line debugging tool (ODT) commands and how the commands are
used.

Chapter 5

Provides block diagram level and register address-level descriptions of the
DECrouter 200 logic.

Chepter 8

Provides lists of router hardware and cable options and the physical and electrical
specifications.

DECrouter 200 Documents
®

DECrouter 200 Hardware Installation/Owner’s Guide

DECrouter 200 Software Installation Guide (VMS/MicroVMS)

DECrouter 200 Software Installation Guide (ULTRIX-32/32m)

DECrouter 200 Management Guide

DECrouter 200 Ideniification Card

Preface-1

Assocleted Documents

The Etbernet-A Loca! Area Network-Data Link Layer and Physical Layer Specifications

Etbernet Installation Guide

Ethernet Netwcrks: Ethernet Products and Services Catalog

H4005 Digital Etbernet Transceiver Installation Manual

H4005 Digital Ethernet Transceiver Technical Manual

DELNI Installation/Owner Manual

Installing Etherjack

Motorola Microprocessor Data Manual

Routing and Networking Overview

Preface-2

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DECrouter 200

1.1

DECrouter 200 introduction

The DECrouter 200 system is an Ethernet-based device that allows network connection for ap to
eight asynchronous devices. The primary use for the router is to connect 1BM personal computer
nodes running DECnet-DOS, specifically, the IBM Personal Computer/AT and the IBM PC/XT, to

the Ethernet and to wider DECnet networks, using existing office wiring. The router also connects
the Digital Rainbow 100 series, and the Digital Professional 300 series of personal computers to the
Ethernet and wider area networks, using existing office wiring. The DECrouter 200 also connects
any DECnet nodes using asynchronous DDCMP with or without modem control. DECrouter 200

has two interfacing capabilities: from devices or dial-in modems to the Ethernet; or from computer
svstems or dial-out modems to the Ethernet. Figure i~1 shows the name panel of the router.

Figure 1-1:
1.1.1

DECrouter 200 Name Panel View

Firmwere

Two kilobyies of EEPROM store all terminal default parameters and some system default parameters for each communication line. The EEPROM has a limited life of 10,000 write cycles per byte

and must be protected from indiscriminate write cycles. Write cycles, which are signaled by an
enable bit to the EEPROM, permit a single write cvcle, and are only read by the router ROM code.

For a detailed description of EEPROM and its functions, see Sections 5.4.11and 5.4.12.

1-1

1.1.2

Programmable Timers

Four 2681 communications dual asynchronous receiver transmitters (DUARTSs) provide four 16-bit
timers (DUARTS 0 - 3) with the following functions:
o

DUARTO - Processor interrupt timer for dynamic memory refresh

DUART] - General purpose timer/set to 25 milliseconds

DUART2 - Watchdog timer for fatal (nard) errors

DUART3 ~ Timer for LED status indicators

For a detailed description of programmable timers, see Sections 5.5.13 through 5.5.18.

1.2

Ethernet Interface System

The hardware interface between the DECrouter 200 and the Ethernet is controlied through a chip

set consisting of a Local Area Network Controller for Ethernet (LANCE) and a Serial Interface
Adapter (SIA). The chip set converts Manchester encoded serial data at 10 Mbits per second into

paraliel, 16-bit data for memory storage.

1.2.1

Local Area Network Controller for Ethernet (LANCE)

The LANCE is a master/slave. direct memory access (DMA) device that converts 10 MHz of serial
data into 16-bit words of parallel data. The LANCE, in slave mode, allows direct memory access

from the 68000 data bus. For a detailed description of the LANCE, see Section 5.6.2.
1.2.2

Serial Interface Adapter (SIA)

Thc SIA is a Manchester encoder/decoder with IEEE and Ethernet specifications. The SIA links the
LANCE to the Ethernet transceiver cable and acquires clock signals and data from the Manchester
output at 10 MHz. For a detailed description of the SIA, see Section 5.6.1.

1.2.3

Service Node and Load Host

Processors supporting the DECrouter 200 on an Ethernet system provide service nodes that:
e

Implement DECnet Phase 1V software

Serve as load hosts to down-line load the DECrouter software image to any requesting router

1.2.4

Firmware and Software

Following is a list of the Programmable Read Only Memory (PROM) code on the DECrouter 200
printed circuit board:
e

Self-test program

[nitialize program — down-line loading and up-line dumping

On-line debugging tool (ODT)

1-2

DECrouter 200 Technical Manual

The following down-line load procedure explains how the router acquires the router software
image from a load host. The software image is stored in program random access memory (RAM).
Upon power-up, the Self-test program performs a series of diagnostics and signals for the initial-

ize program.

The initialize program signais a request for a down:-line load, based on the router physical

address.

The DECrouter then loads from the first properly configured Phase IV DECnet system that
responds to the request.

When loaded, the router software operates until the next power-up sequence. When the router
parameters are properly set, data can be routed between nodes on the Ethernet and nodes connected to asynchronous ports.

1.3
1.3.1

Connector Panel Element Description
Controls and Connectors

Figure 1-2 is a view of the router showing cable connectors, switches. and LEDs. The information
in Table 1-1 explains the function of each LED.

Tahle 1-1:

Connector Panel Elements

The four LEDs on the back of the router function as follows:

State

Condition

DC voltage OK 5V power

OFF

DC voltage problem 5V power

Selftest OK

OFF

Fatal error or test in progress

BLINKING

Non-fatal (soft) error

Operating software loaded, no error

OFF

Down-line load in progress

BLINKING

Loading failed, will-try-again

Ethernet

Network active

Carrier — D4

OFF

Network not active

Power — D1

Diagnostic — D2

Software ~— D3

NOTE
Soft errors do not hinder minimum operation of the system. Hard errors hinder
overall operation of the system. The software LED is only valid when the diagnostics are done.

DECrouter 200

1-3

1.3.2

Switch S1

The switch is not functional on the router.

Figure 1-2:
1.3.3

DECrouter 200 Cable Connection Panel

Asynchronous Ports (J1 - J8)

Through the eight 25-pin male connectors, the router can accommodate up to eight personal computers or any computer systems that have asynchronous DDCMP protocol. Chapter 6 contains a

complete list of standards and protocols for interfacing serial lines and the Ethernet.

1.3.4

Ethernet Transceiver Port

The Ethernet transceiver connector, a 15-pin female type, ‘s on the bottom right corner of the rear

panel. The device connects the router t+; a Digital Ether et transceiver or 2 DELNI transceiver
cable

1.3.5

AC Line Voltage input Seiector Switch

The line voltage input selector switch is to the right of the: AC power receptacle. The switch allows
the installer to set the router for 47-63 Hz input speed a; follows:
e

120 Vac, 90 Vrms to 128 Vrms, single phase, 3-wire

240 Vac, 176 Vrms 10 268 Vrms, single phase, 3-wire

1.3.6

AC Power Cord Receptacle

A country-specific power cord is supplied with the router.

1.3.7

AC Circuit Breaker

The server has a resettable circuit breaker to the right of the power receptacle on the rear of the
Server.

1-4

DECrouter 200 Technical Manual

1.3.8

Power-Up and initialization

After installation and power application, a terminal can be plugged into J1 to check for Self-test
error messages or for down-line load messages. The terminal must be set to the following default

characteristics:

Transmit/Receive = 9600

Charactersize

= 8 bits

Parity

= None

1.3.9

Initiafization Sequence

Application of an AC power source initiates the following power-up sequence:

The power LED lighis.

Self-test begins, and if no soft errors are detected, the Self-test LED lights.

The down-line code is invoked and the router software image is down-line loaded. After successful down-line lvading, LED2 lights.

The router image begins execution.

The unit is functioning.

1.4

Ethernet Systems

The Ethernet, as a local area network (LAN), is 2 communication method based on joint specifications from Digital, Intel Corporation, and Xerox Corporation. For extensive hardware descriptions, vefer to The Ethernet — A Local Area Network - Data Link Layer and Pbysical Layer Specifi-

cation.

DECrouter 200

1-5

The LAN communication system supports a 10-MHz data rate over interconnected coaxial cables.
The Ethernet specification defines the physical properties of the coaxial cable, the transceiver, and
some of the peripheral hardware. The specification also defines basic rules for network access,
device addressing, and data frame format.
1.4.1

Sysiem Elements

Figure 1-3 shows the DECrouter used in a large office and computer room environment,
DECrouter 200 RTRDEYV in Figure 1-3 offers:
e

Connection to personal computers

Connection using existing twisted-pair wiring

Modems in office area accessing remote personal computers

DECrouter 200 RTR2 in Figure 1-3 offers:
®

Connection to large DECnet systems

Modem connections to remote facilities

Modems in a computer room for access to the network by remote nodes

1-6

DECrouter 200 Technical Manuai

REMOTE

PERSONAL

PRO

COMPUTER

3567220

l““"ww 100

MicroVAX

REMOTE
PERSONAL
COMPUTER
PCAXT

DECrouter

VAX 780

DECnet

VAX86800

200

ROUTING

NODE

NODE
JOSH

wan

3
DISKS

PRINTERS

VAX 780

LKG-0535

Figure 1-3:

DECrouter in a Large Office/Computer Room Environment

Figure 1-4 shows a DECrouter 200 used in a small office environment 1o connect 2 few workstations to an office computer. The configuration shows personal computers used as workstations
connected to a network that uses a DELNI as the Ethernet.

DECrouter 200

1-7

REMOTE

{RAINBOW 100

PRO

PERSONAL

350/380

COMPUTER

MicroVAX

REMQTE
PERSONAL

COMPUTER
PCIXT

ETHERNET

VAX 780

VAX 8600

VAX 8800

LKG-0534

Figure

1-4:

The DECroutei in a Smaii Office/Computer Room Environment

1.4.2

Configuration Criteria

Following are the configuration criteria for optimum network performance on an Ethernet:
®

Each coaxial cable segment can be any length up to 500 meters (1640 feet) and must be term nated at both ends at 50 ohms impedance.

A maximum of 100 stations can be installed on a single cable length. Transceivers must be at
least 2.5 meters (8.2 feet) apart.

Transceiver cables can be any length up to 50 meters (164 feet).

A repeater can extend the system by connecting two coaxial cable segments through two transceivers.

The network can be extended using two remote repeaters with an optical point-to-point link of
up to 1,000 meters (3.281 feet) as shown in Figure 1-5.

1-8

DECrouter 200 Technical Manuali

A maximum of two repeater of remote repeater combinations can be used between any two
poiits on the system.

A maximum of 1,024 stations can be connecicd to an extended network. Such a network must
be configured with no more than 2.80 km (1.74 miles) separating any two stations on the network, including point-to-point links and transceiver cables.

1.4.3

Communicetions Methods

Ethernet uses a branching bus topology with 2 coaxial cable as the transmission mediui. Each station transmits 2 prcamble at its start. Receiving stations synchronize and acquire timing from the
preamble. The preamble information reduces problems with line skew or variations in carrier frequency. During transmission, a station calculates a cyclic redundancy check (CRC) value, which is
appended to the erd of the transmission.

1.4.4

Network Access and Communication Protocol

The router supplies power to the Ethernet transceiver on one swisted pair of transceiver cable.
Communications between the router and the transceiver are on the following signal pairs:
e

Transmit pair — The routc: encodes and sends Manchester serial data on the transmit pair.

®©

Receive pair — The router receives Manchester-encoded serial data on the receive pair.

NOTE
The router, operating in half-duplex mode, must be in either transmit mode or
receive mode at a given time. When the router is receiving data, the transceiver
monitors the coaxial cavle for signals and reports the start of a transmission.
e

Collision pair — The transceiver reports a collision condition with another station by sending a
10-MHz carrier to the router on the collision pair. The transceiver also tests for router collision

detection circuits by sen

ag 10-MHz frequency for approximateiy 2 microseconds after every

transmission. This is called a heartbeat check.

1.4.5

Network Access

There is no priority arbitration for access to an Ethernet. All systems and nodes have equal access

Access is gained using a line contention/collision detection protocol called Carrier Sense Multiple
Access with Collision Detection (CSMA/CD).

1.4.6

Collision Detection

Two or more stations transmitting at once nets a collision, which destroys data. When a collision is

detected. the transmitting stations continue transmission for a predetermined time. The continuation of transmission is detected by all stations on the network.

DECrouter 200

1-9

Following are frequently used collision detection terms:
Deference — When a collision is detected, all transmitting stations, and/or stations waiting to
transmit, wait for an integral number of slot times, which are determined by an exponential
binary backoff algorithm, before trying to transmit again. Each subsequent collision and
backoff reduces the possibility of further collisions. This way all stations gain access at random
intrrvals and can complete transmissions.

Slot Time — The maximum time, 51.2 microseconds, in which collisions are apt to occuron a
network. Slot time represents the maximum time from when 2 station starts to transmit to the
timze that it detects a collision with another transmitting station on the network. Any collision
detected beyond 51.2 microseconds is flagged as a late collision error.
Collision Circuitry Test (Heartbeat) — For the transceiver: Tests the router collision detection
circuitry by sending a 10-MHz frequency load for approximately 2 microseconds after a normal
transie (ssion. A collision circuit failure is recorded as a nonfatal hardware error.

1.4.7

Deta Frame Format

Each station transmits 2 frame of serial data in the format shown in Figure 1-5. Each data-byte is
right-shifted within the format.

PREAMBLE

DEST
aooress | SOURCE
aoomes | PROTOCOL
ool

8 BYTES

6 BYTES

6 BYES

2 BYTES

o fl

DATA FIELD

CRC

INTERFRAME
GAP

46 T0 1500 BYTES

4 9YTES

96 pus

MK VESOsIs

Figure 1-5:

1-10

Ethernet Data Frame Format

DECrouter 200 Technical Manual

Table 1-2:

Ethernet Characteristics

Characteristic

Valve/Definition

Topology

Branching bus

Transmission Medium

Coaxial cable using Manchester-encoded digital baseband signaling

Data Rate

10 million bits per second (10 MHz)

Maxzimum Separation

2.80 km (1.74 miles)

of Stations

Mazimum Number
of Stations

1,024 stations

Network Control

Multi-access with equal distribution to all stations

Access Control

Carrier sense multiple access with collision detection (CSMA/CD)

Data Frame Format

72 to 1526 bytes, including a preamble, with a variable data ficld of 46 to
1500 bytes

The follow:ng list identifies and describes each of the seven Ethernet data frame ficlds.
1

Preamble — A 64-bit (8-byte) pattern of a2lternating 1s and Os that allows the receiver circuits to

settle. The last two bits are transmitted as 1s for synchronization, indicating that all following
information is interpreted as data.

Destination Address — A 48-bit (6-byte) address that specifies the destination station. Each
station has a unique Ethernet address and examines the field to determine if it should accept or
reject the data frame.

If the high order bit of the first byte is a2 0, the destination address is unique to each particular
station. If the high order bit is a 1, a logical group of recipients or devices can be specified in a
multicast address. A broadcast address of all 1s indicates that all stations on the network are to
accept the data frame.

Source Address — a 48-bit (6-byte) address that identifies the transmiiiting station.

Protocol Type — A 16-bit (2-bvte) code that identifies the client layer protocol associated with
the frame when multiple higher level protocols are sharing the network. Protocol type is not
interpreted at the Data Link layer.

Data Fleld — The data field can have from 46 to 1500 bytes. The 46-byte minimum ensures that
all recipients are able to recognize valid data frames and discard smaller sequences as collision
fraginents.

Cyclic Redundancy Check (CRC) — A CRC-16 calculation performed on all fields except the
preamble and appended to the end of the frame.

interframe Gap — Every station must supply an interframe gap of at least 9.6 microseconds on
a multiple-frame transmission.

1.4.8

Ethernet Characteristice

The information in Table 1-2 explains the major characteristics of an Ethernet system.

DECrouter 200

1-11

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Self-Test

General

2.1
A

2 REBD

~blmensro
\-l.flvl\

¢ descri

st diagnostics residing in PROM. Self-test can operate in one of

four modes:
®

Normal Mode

Manufacturing Mode

[nitialized Mode

Fatal Error Mode

Normal Mode, Manufacturing Mode, and Initialized Mode test router hardware. Fatal Error Mode
reports fatal router errors.

2.2
2.2.1

Self-Test Operating Modes
Normal Mode

The diagnostic mode under which Self-test typically runs. for example at a customer site, is called
Normal Mode operation.

Self-test starts when power is applied to the router. When no fatal errors are detected, Self-test signals, lighting D2, and transfers control to the router firmware. In Normal Mode, Self-test executes
in less than 15 seconds.

The primary indication for a fatal error is that D2 does not light. When a fatal error is detected, Selftest enters Fatal Error Mode.

2.2.2

Manufacturing Mode

Self-test checks whether or not the Manufacturing Mode jumper is connected. If the jumper is connected, the following changes occur in the test modes:

The Self-test program loops continually.
NOTE
D2 lights after the first successful pass of Self-test, and remains on as the program
loops, until a fatal error is detected.

Dynamic memory is more extensively tested.

The Ethernet port and all terminal ports are tested in the external loopback mode.

Due to a limited life of approximateiy 10 K writes per byte, the read/write tests of EEPROM are
disabled after the first pass.
®

All errors are fatal, causing Self-test to tvrn off D2 and halt execution.

Seif-test executes in less than 35 seconds.

Manufacturing mode is terminated by removing the jumper and recycling power to the router.

2.2.3

Initialized Mode

Initialized Mode is entered from the router software when Self-test is called by the INITIALIZE
command in Privileged Local Mode. Initialization control information is saved, and the Self-test
parameters are used or changed as needed. Self-test is accessible from the Load/Dump microcode
after an unsuccessful load.

In entry mode, the upper 256 bytes of RAM contain the router data called Initialized-RAM. Initialized Mode starts at the first test module a.d operates under the paraineters specified in the Initialized Mode Parameter Byte. Self-test execution time depends on the parameters specified in this
byte. Table 2~1 describes tuie information in the Initialized Mode Parameter Byte.

Table 2-1:

Initialized Mode Parameter Byte

Bits

Mode Name

Test Description

<07>

Long

When set, enables the extended RAM test

<02:00>

LOOPMODEn

Select one or a combination of the following test modes:

Bit

Test Mode Selection

<00>

Loop Self-test — Enables the self-test to loop on itself for a specified number

of passes
<01 >

External Loopback Terminal — Enables ~~vternal loopback tests of the ter-

minal ports
<02>

Disable NI External Loopback — Disables external loopback tes .ng of the
LANCE and SIA chips

2-2

DECrouter 200 Technical Manual

2.2.4

Fatel Error Mode

Self-test enters Fatal Error Mode w hen a fatal error is detected. All errors are fatal in Manufacruring
Mode.
'
The error routine writes the test it error to a byte location in EEPROM and is cieared by the powerup reset procedure.

2.2.5

Error Types

Errors detected by Self-test are classified as either nonfatal or fatal:
e

Nontatal errors are failures that interfere with normal operation or cause the router to operate
at decreased capacity. At completion, Self-test causes D2 to blink if 2 nonfatal error is detected.

The error status parameter is written to initialized-RAM, and identifies the error for evaluation
by the router software.

Fatal errors can disable the router or cause erratic operation. For fatal errors, D2 remains off
and error mode is entered. Unexpected traps and all Manufacturing Mode failures are fatal or
“hard’’ errors.

2.2.6

Nonfatal Errors

The following list explains nonfatal errors:

EEPROM Checksum Error — EEPROM is divided into several functional areas with a parameter checksum maintained in each area. Bad data in any or all of these areas are considered nonfatal.

LANCE Error (heartbeat or external loopback error) — When Self-test detects an error while
testing the LANCE in external loopback mode, it flags the nonfatal error in the status longword.

The external loopback test is disabled by selecting the internal loopback mode in the Initialized
Mode Parameter Byte.

Asynchronous Port Errors (on usable ports) — Self-test flags port errors to the router firmware in the status longword. Router software disables ports after a down-line load. If errors are

detected on all eight ports, the router is not usable. This is a fatal error condition.

Modem Control Signal Error — Indicates a modem control signal error on one or more ports.

2.2.7

Nonfatal Error Status

Two nonfatal status longwords are written to Initialized-RAM, in the upper 256 bytes of RAM, by

Self-test. The first longword contains the EEPROM checksum error status.
The router has 2 K-bvtes of EEPROM. There is a checksum field in each of the 22 sections of
EEPROM. Sections are divided as follows:
¢

Router parameters that comain 173 bytes in 1 section

Diagnostics that contain 20 bytes in 1 section

Hardware revisions that contain 3 bytes in 1 section

Self-Test

2-3

Port parameters that contain 1120 bytes in 8 sections

Service parameters that contain 700 bytes in 10 sections

Encryption parameters in 1 section

In normal mode, checksum errors are nonfatai. A checksum eriof is indicated when any one of the
following bits is set:
e

Bit <00>

Checksum error in the router parameter section

PBit <01>

Checksum error in the diagnostic section

Bit<02>

Checksum error in the hardware revision section

Bit <10:03>

Checksum error in the port parameter sections

Bit <20:11>

Checksum error in the service parafiieter sections

Bu<2l>

Checksum error in the encryption parameter section

NOTE

When no fatal errors are detected in Self-test, the two longwords are returned to the

load/dump microcode. The following table gives the mnemonic and the function of
each bit in the second nonfatal error status longword.

Table 2-2:

Nonfatal Error Longword

Bit

Mnemonic

Function

<18>

RTF

Reset to Factory is a status bit; when set. it indicates that the contents of
EEPROM was reset to the factory default parameters.

<17>

Network Interconnect indicates a heartbeat error was detected while operating
the LANCE.

<16>

XLB

This indicates that the External Loopback Test has failed.

<15.08>

MCS

Modem Control Self-test indicates that the modem control hardware on a chan-

nel has failed Self-test. In the longword there is a bit for each channel, which is
set if the channel fails. MCS errors are always nonfatal because the router always
operates when the data leads on the channel still function.

<07:00>

CHAN

Channel Failure; when bit 2 in the fongword is set, channe! 2 failed Self-test.
CHAN errors are nonfatal if at least one channel functions. Failure of all eight
channels to pass Self-test indicates a fatal error.

2-4

DECrouter 200 Technical Manual

2.2.8

Fatal (Hard) Errors

All errors that are not considered nonfatal, are fatal. Following are some typical fatal errors:
*»

Program RAM Data Error — Any program RAM data error detected by any memory test

Program ROM Cyclic Redundancy Check (CRC) Error — An error detected on the CRC calculation of the PROM

Timer Error — Any failure detected by the refresh or watchdog timer tests

LANCE Error — Any error detected during initialization or on an internal loopback operating
test

Terminal Port Error — When no terminal ports are usable, leaving the router inoperable

2.2.9

Using the Diagnostic LED (D2)

Self-test indicates its status using D2. After executing, Self-test leaves D2 in one of three states: ON,
OFF, or BLINKING.
e

D2 ON - Self-test has completed without detecting any hardware errors.

D2 OFF - A fatal hardware error was detected.

D2 BLINKING - A nonfatal hardware error was detected; an error message displays on the console terminal. See the DECrouter 200 Management Guide for a complete description of the
diagnostic error messages.

In Normal Mode. Self-test executes in under 15 seconds. In Manufacturing Mode, it takes at least 35
seconds. In Initialized Mode, the executior time varies according to the parameters selected in the
Initialized Mode Parameter Byte.

2.2.10

Self-Test Program Tests

There is one locp that calls each test, in order. After a test is run, the test returns to the loop. Tests
are executed from both RAM z2nd ROM.
Following is the dispatch table, which shows each test by number. The table also shows how each

test is invoked, where the test executes. and the test name:

Table 2-3:

Self-Test Dispatch Table

Tesal

inVOokeD by

Exscution

MName

Jjump

ROM

STSCPU REG)

Jump

ROM

ST$)AM TEST
)

Jump

ROM

STSQUICK RAM

Jump

ROM

STSEXTENDED RAM)

Juinp

ROM

STESTUCK INTERRUPTS
{continued on next page)

Self-Test

2-5

Tabie 2-3 (cont.):
invoked by

Exacution

Name

Call

ROM

STSREFRESH TIMER

Call

ROM

LANSREG TEST

Jump

ROM

STSWD TIMER

ROM

STSGP TIMER

Call

ROM

STSLOADER

Call

ROM

STSPROM CRC

Call

ROM

STSNI ADDRESS

Call

ROM

STSPARITY

Call

ROM

STSEEPROM RW

Call

ROM

STSRESET TO FACTORY

Call

ROM

STSEEPROM CS

Call

ROM

STEMODEM CS

Call

ROM

STSRTS CTS

Call

RAM

LANSREJECT

RAM

LANSACCEPT PHY

RAM

LANSCOLLISION

RAM

LANSRCY GOOD CRC

RAM

LANSXMT CRC

KAM

LANSRCYVY BAD CRC

RAM

LANSBROADCAST

RAM

LANSMULTICAST

RAM

LANSEXTERNAL LOOP

RAM

RTSCHAR LENGTH

RAM

RT#BREAK

RAM

RTSFRAMING

RAM

RTSOVERRUN

RAM

RTSBAUD RATE

RAM

STSEXERCISER

FalPs

2.2.10.1

Self-Test Dispatch Table

Processor Reglster Test — STSCPU_REG_J

—

Verifies that there 2re no stuck-

Verifies that the resetp state is

at faults in the CPU registers.

2.2.10.2

Seif-Test UN--JAM Test — STSJAM_TEST_J

cleared. When the router is powered up, the hardware reset signal causes PROM to map to a RAM
address space where the CPU fetches its reset vectors and starts execution. Clearing the reset

allows the mapping of PROM 1 its correct address.

2-8

DECrouter 200 Technical Manual

2.2.10.3 RAM Quick Verify Test — STSQUICK__RAM__J — Verifies that each RAM location is addressable and that no locations have stuck-at faults. The algorithm also yields full coverage of shorted or open address lines.

2.2.10.4 Extendsd RAM Test — STSEXTENDED__RAM_J — Provides extensive Program
RAM tests; the test executes only when in Manufacturing Mode, or when calied from LAT software
with extensive memory testing enabled. This test identifies stuck-at faults and coupling faults, and
ensures that all calls exist.

2.2,10.5

Stuck-atinterrupt Test — STSSTUCK _INTERRUPTS.__J

Verifies that no pro-

cessor interrupts are pending. Processor interrupts can be caused by malfunctioning interrupt

2.2.10.6

Refresh Timer Test — STSREFRESH_TIMER

—~

Verifies that the refresh timer

(DUAR I0) interrupts at the correct Interrupt Priority Level (IPL) and the correct vector, and that
the timer is running in free running mode.

2.2.10.7

LANCE Register Test — LANSREG_TEST

—

Vernifies that the

CPU correctly

accesses the LANCE registers, and ensures that there are no stuck-at favlts in the LANCE registers,
and that the LANCE is correctly reset.

2.2.10.8

Watchdog Timer Test — STSWD_TIMER

—

Ensures that the Watchdog Timer

resets the module. This function of the Watchdog Timer is tested only on the first pass of Self-test;
subsequent passes check whether or not the watchdog timer expires. Resetting of the modaule is not

allowed. Before rxiting, the watchdog subsystem is initialized, so that when any porticn of Selftest hangs, the timer expires, causing 4 fatal error.

2.2.10.9

General Purpose Timer Test — STSGP_TIMER

—

Verifies that the general pur-

pose timer (DUART
) interrupts at the correct IPL and that the timer and the correct vector, and

that the timer is in free runr.

2.2.10.10

'2 mode.

TestLoader — STSLOADER

To simulate normal router operation, several

tests execute in RAM rather than in PROM. The STSLOADER test copies these tests to RAM and

verifies that they were correctly copied.

2.2.10.711

PROM CRC Test — STSPROM_CRC

—

Performs a Cyclic Redundancy Check

(CRC) on the entire contents of the PROM; compares PROM contents with the value CRC stored in

the last longword of the PROM.

2.2.10.12

NI Address PROM Checksum Test — STSNI_ADDRESS

—

Performs

checksum calculation on the 32-byte NI Address PROM that holds the router Ethernet address and
compares the result with the checksum stored in the PROM.

2.2.10.13

Parity Logic Test — STSPARITY

—

Ensures that the parity logic correctly detects

and reports various parity errors.

2.2.10.14

EEPROM Rsad/Write Test — STSEEPROM_RW

—

Verifi~s the read and write

funcrions of EEPROM and tests the write-enable and write-disable logic. EEPROM has a limited life

cycle, and writes to the area should be used discriminately. Looping on the portion of the test that
writes to EEPROM is not allowed.

Self-Test

2-7

2.2.10.15 Reset to Factory Test — STS¢RESET__TO_FACTORY — During

power-up. ‘

when all the LEDs are on, the reset switch (S1) is polled. A flag is set true if the reset switch is

pressed during a .5-second interval. This test examines the flag and, if true, the remainder of the
test executes.

The contents of EEPROM are restored to its factory default settings. Default parameters in ROM are

copied to the EEPROM, and new checksum calculations are performed and included in EEPROM.

2.2.10.16

EEPROM Checksum Test — STSEEPROM__CS

—

EEPROM is divided into these

sections:

Router parameters

LANCE, ECO, and revision parameters

Diagnostic parameters

Separate areas for each of the eight terminal ports

This test verifies the accuracy of all but the diagnostic parameter section of EEPROM.

2.2.10.17

WModem Control Signals Test — STSMODEM_CS

—

Checks modem conirol sig-

nal logic, ensuring that each bit in every modem control repister can be set and cleared; tests each
change-detect and interrupt generation circuit for proper functioning.

2.2.10.18

Request-to-Send — Test STSRTS__CTS

—

Verifies that the request-to-send and

clear-to-send flow control logic functions properly.

2.2.10.19

LANCE Reject Physical Address Test — LANSREJECT_PHY

—

Transmits

internal loop packet with a destination address that differs from the LANCE address; checks that
the packet is correctly rejected by the LANCE.

2,2.10.20

LANCE Accept Physical Address Test — LANSACCEPT__PHY

—

Transmits an

internal loop packet with a destination address equal to the LANCE address; verifies that the packet
is correctly transmitted and received.

2.2.10.21

LANCE Force Collision Test — LANSCOLLISION

—

Checks the LANCE collision

detection logic. By setting the RTRY bit in the transmit descriptor. the test verifies that 2 collision
can be forced and reported. A packet is sent in internal loopback. promiscuous mode. with the collision bit set; this enables the LANCE to detect collisions. Transmission is attempted 16 times before

the LANCE signals a retry error and terminates the attempt.

2.2.10.22

Receive CRC Logic Test
— LANSRCV_GOOD_CRC

—

Ensures

that

the

LANCE receives a correct CRC without flagging CRC errors. Packets are transmitted in promis-

cuous, internal loopback mode. Transmit CRC generation is disabled, and a calculated CRC is
appended to the packet. The receiver checks the CRC against the CRC that it caiculated as the

packet is received.

2.2.10.23

Transmit CRC Logic Test — LANSXMT_CRC

—

Ensures that the LANCE gener-

ates and appends a CRC on transmission. A packet transmits in promiscuous, internal loopback
mode. The transmitter generates the CRC; the receiver does not check the validity of a received

CRC. A CRC is manually calculated, and checked against the CRC that the transmitter appended to

the packet.

2-8

DECrouter 200 Technical Manuel!

2.2.10.24 Recelve Bad CRC Test — LANSRCV_BAD_CRC — Ensures that the LANCE
detects bad CRCs. Pzckets are transmitted in promiscuous, internal loopback mode with a bad CRC
appended to the packet. The receiver flags CRC errors.

2.2.10.25

LANCE Broadcast Addreas and Byte Swap Test — LANSBROADCASY

-—

Ens-

ures ihai ihe LANCE accepts an internal loopback packet with a destination address equal to the

broadcast address. This test is run in Byte Swap Mode.

2.2.10.26

LANCE Muiticast Address Test — LANSMULTICAST

Ensures that the LANCE

accepts or rejects frames based on group logical addresses.

2.2.10.27 External Loopback Test — LANSEXTERNAL_LOOP — Ensures that the LANCE
can correctly transmit and receive external loopback packets. This also tests the Serial Interface
Adapter (SIA).

2.2.10.28

Length, Parity, initlalize Sequence — RTSCHAR_LENGTH

—

Tests each chan-

nei for the correct interrupting sequence, character length, and parity generation. The receivers
are initialized to interrupt on RXRDY. The receiver identifies the different character lengths znd
the different parity types of the four characters that are transmitted.

2.2.10.28

DUART Transmit/Receive Break Test — RTSBREAK

—

Tests the ability of each

of the Receive/Transmit channels to detect and accurately report a break character.

2.2.10.30

Force Framing Error Test — RTSFRAMING

—

Tests the ability of each channel

to detect various framing errors and executes only in external loopback mode.

2.2.10.31

Force Overrun Error, FIFO Depth Check Test — RTSOVERRUN

—

Tests

that

each DUART channel accurately reports a receive overrun esror.

2.2.10.32

Baud Rates Test — RTSBAUD_RATE

—

Tests that each channel transmits and

receives at several different baud rates.

2.2.10.33

System Exerciser Test — STSEXERCISER

—

Exercises much of the router sys-

tem hardware. Data transmits and is received on each terminal port and the network interconnect

(N1) port while modem control interrupts are posted. The following devices are active while this
test executes:

General Purpose (GP) Yimer — Interrupts every 10 milliseconds.

Refresh Timer — Interrupts every 3.8 milliseconds.

EEPROM — Accessed 1o read data from EEPROM. The write inhibit circuitry is exercised withoul periorming a write.

RAM and Parity Detection/Generation — The DUART and LANCE buffers are in RAM, and the
RAM and parity detection/generation logic is used during testing.

NiIPROM, PROM, and I/0 Blocks — Accessed during testing.

Watchdog Timer — Active during testing.

LANCE — Accessed while in operation.

Salf-Test

2-9

2.2.11

Seli-Test Ervor Codes

Error information is stored in Initialized-RAM, with the error information start address at $8014A.
A Failing Test byte indicates the test in which an error is detected. For example, if STEQUICKRAM
J Ty ac
T chown
TEEWS
YT BS ang
Sawa number
SI:TIArE
fails, test number 3 is written to the Failing Test byte
in Table 2-2 The error

identifies the part of the test in which an error is detected. A test can generate decimal error codes
from 1 to 99.
The ERROR DATA section contains test specific data, for example, when RAM TEST detects an
error while writing to location 8 1040. Error data contains the address of the failures, and the bits in
error.

Table 24 categorizes and defines the various Self-test error codes.

Table 2-4:

Code

Self-Test Ervor Codes

flessage

Deseription

Pase/Feil Error Codes

oo
01

st8k__success
st$k__ failure

Operation successful
Operation failed

General Error Codes
1

err |

First error check failed

err2

Second error check failed

err 3

Third error check failed

err 4

Fourth error check failed

errS

Fifth error check failed

err 6

Sixth error check failed

err”

Seventh error check failed

err 8

Eighth error check failed

err9

Ninth error check failed

DUART Error Codes
11

riSk__xmi__timeaut

A transmit interrupt did not occur on time

risk__rci _timeou!

A receive interrupt did not occur on ume

ri8k_rco__char__err

A had character was received

ri8k__vci__stat__err

A bad status was received

ri8k_cum__failure

Ali ports failed

risk__icnl__err

Number of interrupts incorrect

(continued on naxt page)

2-10

DECrouter 200 Technical Manual

Table
2-4: (Cont.)

Self-Test
Error Codes

Description

ilesasnre

Code

LANCE Ervor Codes
21
22
23

lansk__no_read___init
The initialize block was not read
lansk__rcv_desc__erv
The error bit is set in the receive descriptor
landk__rcv__desc__timeout A timeout occurred for possession of the descriptor

langk__yrcv__timeous

A receive interrupt did not occur

lans. __diff._buffers

The transmit and receive buffers are different

27
28
29
2A
2B

lan$__bad__rcv__buff__crc An incorrect CRC is stored in the receive buffer
lang__xmi__desc__err
The error bit is set in the transinit descriptor
lan$__xmit_desc.__timeout Atimeout occurred for possession of the descriptor
lans_xmt__timeout
A transmit interrupt did not occur on time
lang __csr0__err
An error bit is set in CSRO

lang__no__stop

LANCE did not stop

lans__no__exp__err

LANCE did not flag an expected error

lans__diff_buf). _size

The transmit and receive buffers are different in size

Asynchronous Error Codes
70

S18k _usi__err

Unexpected interrupt error

siSk_par__err

Parity error

St8k__unx__rt__int

Unexpected DUART interrupt

st8k__warm__err

llegal warmstart reset

st8k_warm__err

Illegal warmstart and a bad stack

NOTE
Typical asynchronous errors are unexpected interrupts and parity errors. Error

codes are written to EEPROM under Error Number. Following is an example of an
EEPROM error display when Self-test fails:
Failing Test:

03 @ 8014B

Error Number:
Error Data:

71 @ 8014D
00 @ BOl4F

This indicates that Test 3 (STSQUICK__RAM) failed due to a parity error, 7 1(hex).

Self-Test

2-11

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Initialize Program

3.1

Introduction

The initialize program is in the Program ROM and starts on compleiion of the Self-test program or
on detection of a fatal bugcheck error.

After Self-test, the initialize program transmits a request for 2a down-line load of the router image

from a load host. When Self-test detects a fatal hardware error or the Ethernet loopback test failed.
no request is sent. An active DECnet Phase IV host is needed to operate the router.

The initialize program is started by the router manager and the program issues a request for an upline dump of Program RAM on a fatal bugcheck. The watchdog timer also initizlizes up-line dump
requests.

The initialize program supports the following router start-up and operating functions:

Part 1 - transmits a request program load message on the Ethernet for a down-line load of the
router software image.

Part 2 - processes down-iine ioad records from the load host, stores the router software in program RAM, and displays the load status on the terminal.

Part 3 - displavs a fatai bugcheck message on ihe terminai when a fatal error condition is
detected by the operating software.

Part 4 - when enabled, transmits an up-line dump of all router program RAM locations to a
dump host after a fatal bugcheck.

3.2

Down-Line Load

The initialize program displays me_sages on the terminal to show the progress of a down-line load
procedure.

3-1

3.2.1

Down-Line Load Messages

When Self-test does not detect errors, LED 3 lights and stays on. When a software error occurs, LED
3 blinks signaling that operating software has not been loaded. When the load starts, the router
Ethernet address and firmware version number is displayed. A second message gives the status of
the image load. 'The second message repeats every 30 seconds when the load fails, or when a load
host volunteer is not availabie.

The following sequence of messages appears on the terminal screen at 30-second intervals:
Local
Local

-901- Initializing DECrouter 08-00-2B-00-XX-XX ROM BL? H/W REV A A
-902- Waiting for

image

load

When 2 load host volunteer responds, the load procedure is started and the following message,
which identifies the load host Ethernet address, is displayed:
Local

-903-

from 08-00-2B-00-XX-XX

When the load procedure is interrupted, or the down-line load message is not received within 30

Locai

-912-

Load

failure.,

timeout

On compietion of the load, the following message is displayed and the program control transfers to
the router software, or to ODT, if enabled:
Locat

-804-

Image

load

complete

3.2.2

Down-Line Load Procedure

The down-line load procedure runs under the standard Maintenance Operations Protocol (MOP).
The process between the router and the load host volunteer follows this sequence:

With Self-test complete, and without a hard error or an Ethernet loopback failure, the router
transmits a request program load message to the load assistance volunteer multicast address.

Host systems that support down-line load search the DECnet database for the router Ethernet

address and try 1o load the file defined in the database entry.

The router selects the first assistance volunteer it receives and retransmits the request program
load message. addressed to the selected assistance volunteer. which is the load host.

The load host initiates the down-line load by sending the router 2 memory load message with

the first record of the router software image file.

The router loads the first memory load message and sends a request memory load message to
the linked load host.

3-2

DECrouter 200 Technical Manual

6. The linked load host sends subscquent memory load messages containing sequential router
softrware records. The router responds to each memory load message with a request memory
load message.

7. When all recorde ace loaded in the router, the load host sends the parameter load with a transfer
address message and terminates its down-line load process.

8. The router responds with a final request memory load message and starts the acquired router
software as fully operational.

3.2.3

Up-Line Dump

The router manager enables the up-line dump parameter. The initialize program sends an up-line

dump request to the original load host on a fatal bugcheck. The watchdog timer can also issue an
up-line dump request.

During up-line dumping, the initialize program transmits an image of the entire router memory

contents, including the router software. using MOP. The procedure also displays a series of messages on the terminal that report the progress of the dump.

3.2.4

Up-Line Dump Messages

Following is the message displayed when the router requests an up-line dump:
Local

-905- Waiting

for

image dump

When the dump host responds and the up-line dump is started, the following message is displayed
to identify the dump host Ethernet address:
Local

-906- Dumping to

host

AA-00-00-00-00-00

On compietion of 2 dump, the following message is displayed and the program control transfers to
the Self-test program, or to ODT if enabled:
Local

-907-

Image dump

complete

3.2.5

Up-Line Dump Procedure

The up-line dump process between the router and the dump host is based on the following
sequence:

Toinitiate a dump, the initialize program sends a request dump sarvice message to the original
load host. When the original load host services the request, the host sends a request memory

dump message to the router and goes to step 5 in the sequence, eliminating steps 2, 3, and 4.
2.

If the original load host does not respond to the request dump service message within 15 seconds, the router retransmits the reques: dump service message to the load assistance volunteer
multicast address.

Host systems that support the request dump service message first verify if they support dumps
from the requesting router. Dump hosts that volunteer send an assistance volunteer message to
the router.

Initialize Program

4. The router selects the first assistance volunteer that responds and retransmits the request dump
service message, which is addressed to the selected assistance volunteer.
5. The linked dump host starts the up-line dump sequence by sending a request memory dump
message to the router.

The router responds to each request memory dump message from the host with a sequential
memory dump record containing the image data of each section of program RAM. All router
memory contents are dumped.

The linked dump host receives each memory dump message, stores the image in sequential

rccords in a router dump file, and sends another request memory dump message to the router
8.

The process continues until the router receives 2 dump complete message from the dump host,
and the dump host terminates its up-line dump process. The router enters ODT, if enabled for
postdump analysis, or enters the Self-test program.

3.3

Status and Error Messages

Following down-line load, the router software controls and starts operation by displaying any non-

fatal, software errows reported by the Self-test. Certain types of Self-test failures may cause the
down-line load procedure to abort or restart.

3.3.1

Ethernet Loopback Error Messages

When an Ethernet loopback test fails under the Self-test,

adown-line load is not started, and the fol-

lowing message is displayed:
Local

-910-

Image

ioad

not

attempted,

A power-up or router reinitialization

network

communications

failure

is needed to clear the condition.

Error message 910 indicates that the router cannot access the Ethernet, maybe due to transceiver or

cable problems. Pressing YR reinitializes the router and starts another down-line load request.
Reinitialization occurs only when down-line load fails. Pressing

has no effect if the router

software starts successfully after a down-line load. This prevents unauthorized users from
reinitializing the router during operation or during a down-line load.

3.3.2

Nonfatal Errors

When Self-test does not detect any errors, LED 3 lights, and the initialize program is flagged.
When any nonfatal errors are detected, LED 3 blinks and the initialize program is flagged. The initialize program displays the following message:
Local

3-4

-911- WARNING -- Nonfatal

hardware

error detected

DECrouter 200 Technical Manual

For port errors tire foliowing error messages are d

teralanemd.

Local

-820- Parameter checksum error on port

3.3.3

Load Fallure or Timeocut Error Message

Loca! -921- Factory-set parameters applied to port =

When a load procedure is interrupted or the down-line load message is not received from the host
within 30 seconds, the following message displays and the load procedure restarts:
Loca!

-912-~ Load failure,

timeout

3.3.4

Fate! Bugcheck Error Message

A fatal bugcheck displays as:
............

where:
PC=

is the contents of the CPU program counter

SP=

is the contents of the CPU stack pointer

HEM=

is the illegal memory address on an addressing error or the address of the instruction that
caused the error

Initialize Program

s the reason for the failure (see Table 3-1)

“w

CODE=

Teble 3-1:

Router Crash Error Codes

Code

Description

DATE>O®
LAV SNN

CPU Exceptions
Bus error

Address error
Hiegal instruction
Divide by 2ero
CHK instruction

TRAPYV instruction
Privilege violation
Trace

Line 1010 emulator
Line 111] emulator
Other
Spurious interrupt

Seif-Test Bugchecks - Program ROM

NI port hardware memory error

NI port initialization timeout error

14
15

NI port transmit buffer error
Stack value incorrect in idle loop

Unlink error

Unable to allocate XCB
Commiand completion error

Local output completion error

Router Software Bugchecks ~ Program RAM

200

Router software checksum error

211
212

NI port hardware memory error
NI port initialization

214
215

NI port transmit buffer error

Stack value incorrect in idle loop

216

Unlink error

217

Deallocate error

218
219
220
221
222

Unable to allocate XCB
Command completion error
Local output completion error
EEPROM write block error
Entry on output queue with no slots

223

Transmit too long

224
z25

Cannot find status
No available circuit control blocks

228

Low pool allocation error

227

Iiicgal tocal output state

228

Service defined with rio nodes

229

Duplicate node/service name found

3-6

DECrouter 200 Technical Manual

3.3.5

Timeout, Abort Dump Message

When timeout occurs during an up-line dump, the following error message dispiays and the dump

aborts. Program control transfers to the Self-test, or to ODT when enabled.
Local

-914- Timeout,

dump aborted

3.3.6

Loador Dump Feliure Message

The following error message displays when a2 down-line load or 2n up-lint dump process fails to
transmit a load or 2 dump message after 10 attempts:
Local

-915- Transmission

failure after

10 attempts

For a down-line ioad, the procedure restarts. For up-line dumping, the process is aborted and program control transfers to the Self-test, or ODT when enabled.

3.3.7

Bad image File Message

The error message:
Local

-916-

Invalid

image

file,

load

aborted

is displayed on either of these two conditions:
¢

A down-line load memory load message specifies an odd memory address or an addruss in the
interrupt vector area.

A parameter load with a transfer address message specifies an odd trans{er address.

Initialize Program

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00.4

On-Line Debugging Tool (ODT)

4.1

On-Line Debugging Tool

The on-line debugging tool (ODT) is a specialized console program that resides in the router firmware (ROM). The user enters ODT only at the console terminal, either from the router operating
software or from Self-test manufacturing mode. When enabled, ODT is also accessible after a
down-line load or a fatal bugcheck.

ODT provides the local input language for router managers or router personnel and takes the place
of most of the keys and switches normally on a computer front panel. ODT is for diagnostics specialists for ongoing reliability test (ORT) procedures. ODT is also for authorized router, system, or
network managers in isolating hardware network problems.

4.1.1

Initial Requirements

The following must be met before using ODT.

When entered from the Self-test manufacturing mode, the default console terminal, port 1.
must be configured to the factory-set characteristics stored in EEPROM: 8-bit characters with
no parity at 9600 baud.

From the router software, ODT uses the preset characteristics for the console terminal.

4.1.2

Entering ODT

ODT is started from any of the conditions or procedures in the following sections. When involed,
ODT returns :he asterisk (*) prompt.

4.1.2.1

Entering ODT from the Self-Test Mar.ufacturing Mode —

manufacturing.

the

operator enters ODT by pressing < CTRL/SHIFT/S > on the conscle keyboard: the (D and GHFT
keys are held down while pressing the @key. The operator can then run single-step, or loop on the

Self-test program. The operator can also set test parameiers and loop on errors.

4-1

4.1.2.2

Entering ODT from Router Operating Software — Before entering ODT, the operator

issues the following command to the router configuration program:
DRCP> ENABLE 0DT

See the DECrouter 200 Management Guide for more information on the configuration program.
Note that this guide does not describe the ENABLE ODT command.

While enabled, ODT executes on any of the following conditions:
®

A CEEERR key is typed at the console

A system crash

A router reirdtialization - when enabled

The execution of a previously set ODT breakpoint

4.2

ODT Command Functions

The ODT user can issue ODT commands. one to three characters long. at the asterisk (*) prompt. 2
carriage return or a line feed terminates the command ODT interprets commands and outputs
vaiues in hexadecimal.

4.2.1

Command input Errors

On a command input error, ODT responds with one of the following error message codes:

RE (Range Error) - This means either the lower memory dump address is higher than the
highest specified address or the specified CPU register address is out of range (0 - 7). A range
error also indicates the ODT user is trying to examine 2 nonexistent location in RAM any
address from 60000 10 “FFFF

CE (Command Error) - This indicates that an unrecognized command was issued

422

CommeandSummary

All ODT commands are in one of the following groups:
e

Memory and device register commands

CPU register commands

Dump commands

Program control commands

Breakpoin' commands

Table 4-1 describes the ODT commands

4-2

DECrouter 200 Technical Manual

Teble 4-1:

Command

ODT Commands

Nemo

Function

AMemory and Device Register Commands
Ev

Examine

Opens and displays the contents of a word address where r
is the address of the word being examined. An odd address
is masked to produce an even address.

BBy

Examine Byte

Opens and displays
the contents of a byte address where r
is the even or odd address of the byte being examined.

EBr

Examine Indirect

Opens and displays the contents of 2 longwond address
where r is the address of the longword address being ¢xam-

ined. An odd address is masked to produce 2n even address.
&D

Carriage Return

Terminates an ODT command or closes an open address.

012

Line Feed

Closes the open address and displays the next sequential
address

Escape

Causes the current data displayed in the E@ command to be

vsed as an address {or the next E@.
CPU Register Commands

$Anor §Dn

Open Register

Opens and displays the contents of 2 CPU address or data
register, where n specifies the register number 0 - 7.

$SR

Open Status Register

Opens and displays the contents of the CPU status register

(SR).
Dump Commands

Drk

Memory Dump

Displays the contents of a block of memory addresses. In

the display. ris the first address of the block and & is the last
address of the block.

(o 1; 10

Halt Dump

Halts 2 memory dump and returns to the ODT prompt (*).

Displays the contents of the internal CPU registers.

Program Conitrol Commands

Starts or continues program execution after a program or

breakpoint halt. Execution starts at location r. If r is omitted, execution continues from the current PC address.
8S

Single Step Enable

Enables the single step mode which allows program execution one step at a time.

Single Step-Disable

Disables the single-step mode.

(comtinued on next page)

On-Line Debugging Too! (ODT)

4-3

Table 4-1 (cont.):
Command

ODT Commands

Name

Function

Breakpoint Commands

Brar

Breakpoint Set

Sets or changes a breakpoint where n is the breakpoint
number, 0 ~ 7, and r specifies the memory address for the
breakpoint.

Breakpoints 0 - 7 allow a software trap from up to 8 locations.

BCn

Breakpoint Clear

Clears breakpoint nn, 0 - 7; if n is not specified, all eight
breakpoints clear.

éB

Display Breakpoints

Displays the first breakpoint table entry. The other seven
entrics contain the second through the seventh breakpoint
addresses and can be displayed in sequence using the (IP)
key.

4.3

Accessing Router Address Space

The router manager or any privileged operator has access to all terminal router memory and device
addresses shown in Table 4-2

Table 4-2:

Router Address Ranges

Router Memory

Phyeical Address

or Device

Ranges in Hexadecimal

Program RAM

000000 - O7FFFF

EEPROM

080001 - 080OFFF

DUARTO

100001 - 10001F

DUARTI

100021 - 10003F

DUART2

100041 -~ 10005F

DUART3

1003661 - 10007F

MODEM

1000A1 -~ 1000AB

CONF REG

1000C1

LANCE

100080 ~ 100082

EPROM

180000 - 187FFF

ADPROM

1C0001 ~ 1CO03F

An ODT command accepts up to 6 hexadecimal digits in the address specifier. Chapter 5 gives the
procedures to follow for accessing PROM, Program RAM, DUART, and LANCE internal registers.
CPU internal registers are not part of the external memory or device address space; the ODT user

accesses internal registers separately through ODT

DECrouter 200 Technical Manual

4.3.1

Memory and Device Reglster Commands

Only one memory or device register location can be opened at a time to display contents for examination or changes. Opening a register location while another is open closes the first register location.

4.3.1.1 Examine (E) Command — Type E, a space, and the address to open 2 word location.
Typing an odd address masks the low-order bit and opens the even word address. Press the GED key
to terminate the command.

Example:
°E 1000 @D

- Entry

001000 = 0123

- Response

When command location 1000 is open, and no change is required. press (ET) to ciose the iocation.

To change the contents of the open word location, type the new contents before pressing BED to
close the location.

Example:
°*E 1000

- Entry

001000 = 0123 3210 BED

- Response and change

Press the Line Feed OB key instead of @D key to close the open word location and to open the
sequential word location.

Example:
*E 1000 ®ED

~ Entry

001000 = 01233210 @ED

- Response

001002 = 4567

- Response

4.3.1.2

Examine Byte (EB) Command — To open a byte iocaiion. type EB. a space, the

address, and @ED.

Example:
*EB 1000 BED

-Entry

001000 = 23

-Respcnse

*EB 1001

-Entry

€01001 = 0}

~Response

if the command location 1000 is open and no change is needed, press @D to close the location.

ODT issues the prompt (°) and the user can issue a command.
When the contents of the open byte location are changed, type the new contents before closing the

iocation.

[

Example:
“EB 1000

-Entry

001000 = 23 54

~Response and change

On-Line Dsbugging Tool (ODT)

4-5

Press Line Feed (IP) instead of BED to close the open byte location. This opens and displays the next

sequential byte location.

Example:
*EB 1000 @ED

001000 = 230D
001001 = 01

4.3.1.3

-Entry

-Response
-Response

Examine indirect (E@) Command — To examine an address, type E@, space, and the

hexadecimal value of the address you need to examine.

NOTE
The Examine Indirect command is terminated with @D, D, or (D). Change the
or 0P.
contents of a location by using
The following example shows address examination using ODT:
*E@ 1000 BED

~Entry

2000 = 100

~-Response

100

= 800

-Response

800

= 1000

~Response

1000 = 20000D

~Response

1004 = 800 @ED

-Entry

~Response

The following example shows address location modification using ODT:
"E@ XYXY&E:D

-Entry

1000 = 2000 800 (5D

~Response

800

~Response

= 1000 2000 EsD

2000 = 1001804 TP

-Response

2004 = 5000 @ED

-Response

4.3.2

CPU Reglster Commends

4.3.2.1

CPU Address Register ($An) Command — The following command format opens

and displays the CPU address registers AQ - A7:
*$Am

-Where n is an address register 0 - 7

Example:
"8AS

~Entry

AS = QUODIFFF

-Responce (contents of address
register AS)

4-6

DECrouter 200 Technical Manual

1
Pm e

4.3.2.2

CPU Data Register (§Dn) Command — The following command format opens and

displays one of CPU data registers DO - D7:
*$Dn @D

~Where n is a data register 0 -7

Exemple:
*D0 @D

-Entry

DO = 00001234

~Response (contents of data register DO)

When these registers are open, the contents are visible. To change the register contents type 2 new
value before pressing @F) or BED as described under the Examine (E) command.

Any value for n outside the specified range of 0 - 7, produces a range error (RE) message, followed
by the prompt °*.

4.3.2.3

CPU Status Register ($SR) Commend — Open the CPU status register with the follow-

ing command format:

*SRED

-Entry

SR = 2701

~Response

Use the same procedure 1o change the status register.

4.3.3

Dump Commands

Dump commands, in troubleshooting. display program and hardware status.

4.3.3.1

Memory Dump (D) Command — The D command dumps both the contents of a block

of terminal router memory and the contents of DUART address registers. LANCE address space can

be included in a dump. LANCE registers are not accessed with the D command and are always read
as zefros.

A memory dump is initiated by typing a D. a space, the low address. a space, and the high address,
as shown in the following format:

~-Where r is the address of the first location and &, the

‘rk @D

address of the last location

The specified addresses are then dumped in word format as shown in the following example:
*D 1000 102EED

~Entry

001000

mnmn

nnnn

AREN

BANRNK

BARN | 1NN

dcadaacdaacacaaan

001010

mmmm

npnn

#AnRER

BRNRN

BRBN

BANRN

AA2AGRAAARAAAAAAA

001020

mnmn

nann

nRnn

ARRN

ARRR

ANRBR

ANNN

AAAGGRAARAARAAAAA

In the example, n represents the hexadecimal value for each nibble (4 bits) of the dumped memory
locations. Each a represenis the ASCII value of each n-pair or byte. A period in any a position indicates a2 nonprinting character.

The word address of the first location dumped on 2 line is displayed at the start of each line. A maxi-

mum of eight sequeniial words are dumped per line. If 2an odd word address is issued. the low-

order bit is masked to make an even address. If the low address issued is greater than the high
address, the Range Error (RE) message is displayed and the prompt for another command is given.

On-Line Debugging Too! (ODT)

4-7

4.3.3.2 Haelt Dump (CTRL/C) Command — If an error is made while typing in an address range, ‘
press {ETRIAD to halt 2 memory dump and ODT returns to the prompt °.

4.3.3.3

Regleter Dump (RD) Command — Use the RD command to dump the word (16 bits)

conicais of the following CPU internal registers:
e

Address registers (A0 - A7)

Data Registers (D0 - D7)

Program Counter (PC)

Status Register (SR)

*RD @D
A0

munnnnnn

nanannnn

nanannann A3

nanannnan A7

maanannn

nnnnnann

nnanannan

DO =

nmanannnn

pannannn

D2 =

pannsnnn

D3 =

annnannn

D4 =

mmmmnnnn

DS =

nnnnaann

DO =

nannnunn

D7 =

annnannn

nannnnnn

SR =

nnnn

In the example, » represents a hexadecimal digit. Register A7 is always the supervisor stack point

because the Self-test and LAT programs execute in Supervisor Mode. None of these registers are
opened for changes: the CPU register commands must be used to change register contents.

4.4

Programming in ODT

The following several sections describe ODT command functions for debugging under the Self-test
program o the LAT operating software.

4.4.1
4.4.1.1

Program Control Commaeands
Go(G)Command — Start the program or continue its operation after a breakpoint or

program halt by issuing the Go command:

*GrEzn

~-Where r is the location to begin the program. If the r is
omitted, the program begins at the address specified by

the current PC. Issuing an odd address as the new PC
forces the masking of the low order bit to produvce an
even address.

4.4.1.2

Single Step Enable (SS) Command — When single step is enabled. enter each instruc-

tion in sequence using the following format:
°SS @D

-Entry

After each step, ODT displays a message in the following format:
SSr

4-8

~Where ris the value of the current PC

DECrouter 200 Technical Manual

The Go (G) comm;nd can be used to start Or to continue program execution.
Example:

*SS @D
°G 1000

-Entry - single step command
-Entry Go starts the program at location 1000

§5 001002
°G

-Response - Go executes on instruction, and displays §S,
then the updated PC value
-Entry - Go continues, executing the next command

$S 001004

-Response

-Prompt for next command

4.4.1.3

Single Stop Disable (NS) Command —~ The following command disables single step:

*NSED

4.4.2

-Entry - ODT lezves single step mode

Breakpoint Commands

The ODT program maintains a breakpoint table that can be displayed but not opened for changes.
Defined breakpoint commands must be used to make changes in the breakpeint table.

Eight breakpoints, from O to 7, can be set. Breakpoints allow the router software to trap and sus-

pend operation from up to eight locations. A breakpoint can be set in any location acquired from
program RAM as an instruction but not as data. When a breakpoint is set, ODT replaces the contents of the breakpoint location with a trap instruction that suspends program operation and
returns to ODT.

4.4.2.1

Breakpoint
Set (Bn)Command — Set or change breakpoints by using the following

command:

*Brnr

~-Where n is the breakpoint number and r is the
breakpoint location

Exemple:
*B2 1000

~-Breakpoint entry - program halts operation when
fetching at location 1000

4.4.2.2

Breakpoint Clear (BCn) Command — Clear breakpoints by using the following com-

mand:

*BCn @D

-Where n is the number of the breakpoint to be cleared ~
if the issued value for » is not within the range, ODT
gives the Range Error > > RE prompt.
If n is not specified. all breakpoints are cleared.

On-Line Debugging Tool (ODT)

4-8

4.6.2.3 Uisplay Breakpoints ($8) Command — Use the 8B command to display the first entry
in the breakpoint table. All following breakpoints are then displayed in sequence using Line Feed

5 immis

-Entry

BK 1 = 00I0FO@D

-Response and
0P entry

BK 2 = 001200

-Response

terminates the command

4.4.2.4 BGrealipoint Message — When the program reaches a breakpoint, ODT restarts and displays a message, such as:
BKrer

-Where n is the breakpoint and r is the breakpoint address

Examge:
BK 1 G010F0

-Displays breakpoint message

-Returns the ODT prompt

In the example, the program halts after reaching breakpoint 1 at location 10F0. ODT issues the

asterisk prompt and waits for a command.

4-10

DECrouter
200 Technical Manual

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Functional/Logic Description

General

This chapter is an in-depth functional description of the DECrouter 200 logic. Descriptions
are written at the block diagram level and should be used with the maintenance print set, Document P/N MP01827~01.

The following is an outline of the DECrouter 200 subsystems. The router 2s a system is illustrated in
Figure 5-1.

Microcomiputer Logic:

MC68000 Central Processing Unit (CPU)
Data/address bus

Power-up reset logic
System clock logic
Bus arbitrator logic

Interrupt control logic

Counters and timers

Router Memory:
Address decode 1ogic

512 KB of DRAM
32 KB of ROM

2 KB of EEPROM

5~1

Terminal Interface:

Four 2681 Dual Asynchronous Receiver/Transmitters (DUARTS)

Eight RS-232-C/CCITT V.24 compaiiblc driver/reccivers or onc DEC423 pont

Ethernet Interface (chip set):

Local Area Network Controller for Ethernet (LANCE)

Serial Interface Adapter (SIA)

ESD/EOS protection circuitry

Octal drivers and receivers

Modem Control

DC7053 chip: four modem control interrupt lines

DUARTs 0-3; one modem control interrupt line

5.2
5.2.1

WMicrocomputer Logic
CPU and Data Addrese Bus

For a block diagram of the DECrouter 200 impicmentation of the MC68000 CPU. sec the print set

NOTE
The abbreviations MC68000 and CPL are synonymous throughout this chaptes

The MC6G8000 is a 16-bit microprocessor that contains cight 32-bit data registers, eight 32-bit

address registers. one of which is the special purpose stack pointer. a 32-bit program counter. an 8-

bit status register. an ALU. and conditional branching logic In the DECrouter 200. the MC68000

performs arithmetic and logic functions and handles most data and address transfers. In the status
register. the low byte is the user bvte. and the high byte is the system byte

For detailed information and complete instruction sets on the CPU. see the Motorola Micro
processors Data Manual

5.2.2

Device Addresses

Following are the hexadecimal addresses derived from the 20-bit address bus for the DECroute:

200 hardware subsvstems.
®

RAM Address

00000 - O"FFFF

EEPROM Address

80001 - OBOFFF

DUARTO Address

100001 ~ 10001F

DUART! Address

100021 - 10003F

DUART2 Address

100041 - 10005F

5-2

DECrouter 200 Technical Manua

DUART3 Addsess

100061 - 106007F

LANCE Address

100080 (Cata Register)
100082 (Address Register)

MODEM Address

1000A1 - 1000AB

CONFG REG Address

1000C1

EPROM Address

180000 ~ 187FFF

ADRPROM Address

1C0001 - 1CO03F

POWE

BEne

ANE W sm

serele

" 13

SRR
s

[ Ve

:“;

D(COOE
$35°uinsa

a- -:’. i

\3_

8uUy
ARBTRA OTM

DRAM T OR TR, S DRaM

Musa.ouamTe

LIAs d 4 oee

—o
[1

Figure 5-1:

DECrouter 200 Logic

Functional/L.ogic Description

5-3

5.2.3

CPU end Data/Address Bus Signal Description

Thie router uses two data buses, one buffered, and one nonbuffered. The following devices are
accessed through the buffered data bus:
o

EEPROM

EPROM

ADRPROM

DUARTS 0 through 3

The following devices are accessed through the nonbuffered data bus:
®

68000 CPU

LANCE

DRAM

Configuration Latch

Gate Array

Following are the signal names and the CPU and data/address signals in the DECrouter 200.
¢

Data/Address Bus Signals

Address Bus (BUS_A01_H throug:. BUS__A20_H) — BUS<A20:A01> H — The
router uses 20 of the 23 three-state address lines to provide direct addressing for up to two
megabytes of data. These lines are drive-only for the CPU.

The router does not use BUS__AGO__H, but the CPU and the LANCE both use internal

address bit < A0 > 10 generate BUS UDSL or BUS LDS L on a byte transfer. Both signais are
generated on a word transfer. The CPU uses the complement of <A00> for byte transfers.
<A00>onalasseris BUSLDSL; <A0O> onaQasserts BUSUDS L.

Data Bus Nonbuffered (BUS__D00__H through BUS__D15__H) — This 16-bit, bidirectional three-state bus is the main data path fo. all transfers with memory and device address
space.

Data Bus Buffersd (BBUS__D00__H through BBUS_D15__H) — This 16-bit, bidirectional, three-state bus is used for slower devices.

Asyncbronous Bus Control Signals

Address Strobe (ASTRB__L) — This signal is asserted by the CPU to initiate a register
transfer with an external device, such as the LANCE or 2 DUART. This signal also indicates
that the CPU has a valid address asserted on the address bus.

Read/Write (WRT__L) — This is 2 wire-OR signal. WRT__L is asserted by the CPU or the
LANCE to define a bus transfer.
Negated (High) = Read

Asserted (Low) = Write

5-4

DECrouter 200 Technical Manual

Upper/l.ower (Byte) Data Strobe (URS__L/LDS__L) — The CPU uses either or both of
these signals with WRT_L to control bus transfers. Table 5-1 shows how the valid data

bytes for a read or a write transfer are indicated.

Table 5-1:

Deata Strobe Control of Data Bus
Velid Deta
BUS_D

Asgerted
on
88U_D

Ubs__L

LDS_L

WRT__L

<15:08>

<07:00>

o
0
1

0
1
0

0
0

No
No
Yes

No
Yes
No

Yes

(0 = Negated High, 1 = Asserted Low)

NOTE
As a bus slave, the LANCE ignores UDS__L and LDS_L and accepts word transfers. Wire-OR signals are driven by the LANCE and the CPU at different times
and are buffered at the CPU as:

input

Buffered Output

AS__L

BASTRB__L (LANCE not used)

WRT__L

UDS__L

BWRT__H,_L
BUDS__H,._L

LDS_L

BLDS__H,_L

Data Transfer Acknowledge (DTACK L) — Asserted by the selected device in response to
the ASTRB__L from the CPU. DTACK L is asserted by the following signals:
DATA__ACK__L from the PAL — This signal is asserted during all CPU transfers with
devices other than the LANCE.

LAN_ACK_L from the LANCE — This signal is asserted during CPU transfers with
LANCE registers.

Interrupt Control Signals

Interrupt Priority Level (IPL. <2:0> L) — This signal is asserted by the interrupt priority
logic for the highest asserted intesrupt request. Any asserted code, other than zero, generates a program interrupt request in the CPU.

The CPU contains 2 3-bit interrupt mask in the system byte that indicates the current processor IPL and holds an interrupt, pending whenever its priority level is higher than the

requesting device. The CPU issues the interrupt when its current IPL is lower than the
requesting device. The only excepticn is the IPL7, which allows an unmasked interrupt for
the program RAM parity error.

During the interrupt cycle, the CPU asserts the IPL of the device being serviced on address
bus lines, BUS__A01-A03. The CFU asserts ail other address bus lines high.

Functional/Logic Deseription

5-5

Bus Arbitration Signals

Bus Request (BR__L) — This signal, asserted for the LANCE by the bus arbitrator, gzins
access to the data/address bus and performs a DMA transfer with program RAM.

Bus Grant (BG__L) — This CPU response to a bus request indicates that the CPU reicases
control of the bus at the end of the current bus cycle.

Bus Grant Acknowiedge (BGACIK __L) — This signal, asserted for the LANCE by the bus
arbitrator, is in response to 2 bus grant. The LANCE assumes control of the data/address bus
when the arbitrator asserts BGACK__L and LAN_HLD__ACK__L.
Processor Control Signals

Hait (HALT L) — The CPU asserts this bidirectionai iine to external devices. When this line
is driven by an external device, it causes the processor to stop at the completion of the current bus cycle.
In the DECrouter 200, the halt and reset lines are asserted together as a system reset.

Claar (CLR L) — The CPU asserts this bidirectional line to initialize externai devices wiih 2
RESET instruction. The CPU initializes when this line asserts externally.

CLR__L is asserted on power up for 2 minimum of 100 milliseconds. When this signai
negates, the CPU starts program execution in memory location O, and the
POWER__LED__L signal is asserted. This causes D1, on the outside of the router, to light.
Function Code (FC < 2:0 > H) — This signal indicates to external devices the type of reference being executed by the CPU.

The CPU has two levels of access privileges: supervisor level and user level. Only level 7 is

used by the DECrouter 200. The reference types are defined as follows:
FC<2:0>

Value

Reterence Type

User data

User program

Supervisor data

Supervisor program
Interrupt Acknowledge (INTR_ACK__L)

CPU Cloek (CPU_CLK__H, 10 MHz) — The TTL-compatible input is buffered internally to
create the CPU clocks.

DECrouter 200 Technical Manual

5.2.4

Power-Up Sequencer Loglc

At power up. the hardware reset signal is held high for 100 milliseconds minimum, resetting the
68000, the LANCE, the DUARTSs, and other logic. Table 5-2 gives the reset signals and their functions.

Teble5-2:

Reset Signals and Functions

Sipnal

Function

EEPROM_CLR__L

Prevents false writes to EEPROM at power up and power down.

CLE_L

Regers the madule and the 68000,

WARM_CLR_L

Resets the module except the 68000 CPU, which is put into the Bus Error
Exception Processing Mode. In this mode, errors are reported instead of being
cleared.

POWER__FAIL__L

Reserved for use during manufacturing tests to generate power-off/power-on
cycle resets

WATCH__DOG__L

The Waichdog Timer from DUART3 gencrates 2 power-up reinitialization if
not periodicaily cleared by the program.

5.2.5

Raset Circultry

The reset circuitry monitors the Vcc voltage level. sensing when the module is powered up or powered down. During power changes. the circuitry generates 2 clear signal to the EEPROM for protection from data corruption. An RC network provides a delay to reset the CPU and the LANCE.
Hysteresis thresholds on the reset circuitry determine when a signal is asserted: a clear signal is
asserted when power is applied to the inoduic. The Vcc level then raises to 4.6 volts, and a 100-millisecond RC timeou: begins. The RC timer then issues a timeout, and the clear signal is deasserted.

The clear signal is then reasserted when power is removed. and the Vcc level drops below 4.5 volts.
§.2.6

Warm Reset

In normal operation a2 warmstart circuit allows the module to recover from unexpected processor

halts and from a misaligned program counter. During warmstart reset, the memory contents are

up-line loaded to a host computer, and examined for potential problems. After the up-line load. the
unit starts initialization to recover from errors.

§5.2.7

Resat Testing

The analog circuitry in the reset device is not tested by Seif-test: the digital circuitry is tested. The
digital circuitry includes 2 Watchdog Timer in DUART2, a flip-flop, 2 one-shot, and control bits
from the Configuration Register. These devices generate the WARM__CLR__L signa! that provides
a warrn reset to the module.

Functional/Logic Description

5-7

Self-geer checks s logic by triggering the Warchdog Timer. The timer output signals the flip-flop
to latch. The flip-flop output signals the one-shot to genmerate a 1.3 microsecond reset

(WARM__CLR__L). The reset clears the circuitry except the MC68000. The WARM__CLR__L signal
interrupts the CPU at the BERR_L input, causing an interrupt service routine. Seif-test checks that
the circuit is active, by verifying interrupt service routine execution and that the flip-flop is in its
latched state.

Self-test can read the state of the flip-flop by testing the WARM__START__L signal on DUARTO.
Self-test can also clear the flip-flop by toggling the WARM__START_CLR__H signal on the configuration register. The RESET__DIS__H signal on the configuration register can block or can disable a
reset signal while allowing testing of the flip-flop.

§.2.6

System Clocklegle

The router implements five clocks:

TCLK — a 10-MHz clock from the SIA
2.

RCLK ~— a 10-MHz clock from the SIA

A 3.6864-MHz baud rate for the DUARTSs

A !.84-MHaz clock to generate the DRAM refresh timer and general purpose timer

A refresh timer to generate the waichdog timer and the LED timer

TCLK generates two 10-MHz clocks in opposite phase of each other: CPU_CLK__H and
CPU_CLK__L. Both clocks are used for the MC68000, the DRAIN, the BUS arbitration, and the
address decoder circuits.

The DUART oscillator operates at a base frequency of 29.4912 MHz. A frequency divider produces
the 3.6864-MHz and the 1.84-MHz frequencies.
Table 5-3 gives the functions of the three system clocks.

Table 5-3:

System Clock Functions

Signal Name

Frequency

Funection

CPU_CLK_H

10 MHz

Provides the time base for the CPU, the PAL. the bus arbitra-

CPU_CLK L

10 MHz

tor, and drain circuits

DUART_CLK_H

3.68 MH2

Provides the tranzmit and receive time base for the DUARTSs

TIMER__CLK__1

1.84 MH2

Provides the counter/timer clock for DUARTs O and 1

5-8

DECrouter 200 Technical Manual

§.2.9

Bus Arbitration Loglc

The bus arbiteation logic provides communication between the LANCE and the MC68000 for bus
master. A DMA transfer is initiated as follows:
o

The LANCE deasserts a HOLD (BLAN__HLD__L)signal.

The bus arbitration asserts a bus request (BR__L) signal.

e The MC68000 deasserts a bus grant (BG__L) and finishes the bus cycle.
o

The MC68000 asserts an address strobe (ASTRB__L).

The bus arbitration asserts a bus grant acknowledge (BGACK__L) to the MC68000 and 2 hold
acknowledge to the LANCE.

The BGACK signuis the 68000 that the bus is in use, and LAN_HLD__ACK__L signals the
LANCE to start 2a DMA.

5.2.10

Interrupt Control

The MC68000 has seven hardware interrupt priority levels (IPLs), which are expandable by external logic. Level 7 has the highest priority and level 1 the lowest. When an intetrupt is not being processed, the CPU executes instruction. at level 0. Priority 1 has 8 transmit levels. Each of the eight
serial signals has 2 unique interrupt vector that is generated on a character-for-character basis.
Interrupts are asserted pending the following conditions:
e

The DUARTS transmitter is enabled.

The OPCRs in the DUARTS are configured for interrupts.

There are no characters in the transmit hold registers.

At IPL 2 there is a general timer interrupt. The interrupt is asserted pending the following conditions:

The correct timer value is in the counter register (CTUR, CTRL) in DUART1.

The counter timer source in the ACR is set for TIMER EXTERNAL (IP2).

The output port (OPCR) bit 3 is set as a timer output.

The timer is set.

The timer expires.

An interrupt terminaies when the timer restarts by reading address 10003D.

IPL 3 is the LANCE interrupt, which is asserted pending the following conditions:

The LANCE has completed the initialization block, the transmit descriptor rings, or the receive
descriptor rings.

The INEA bit in CSRO is set.

QOne of the bits in CSRO is set: BABL, MISS, MERR, RINT, TINT, or IDON.

Functional/Logic Description

5-9

The interrupt terminates when a 1 is written to the corresponding error bit in CSRO.
Priority 6 contains a refresh timer interrupt that asserts when the following parameters are met:
The appropriate timer value is in the Counter Register CTUR/CTRL, in DUARTO.
The counter timer source in the ACR is configured for TIMER EXTERNAL — IP2.
Output port bit 3 in the OPCR is designated as the timer output.
The timer is active.

The timer expires.

IPL 6 asserts every 3.8 milliseconds to refresh the Dynamic RAM. This interrupt terminates by reading address 10001D. which restarts the cour.ter timer.

NOTE
In order to execute from DRAM: *he counter timer must be active, and the interrupt
address vectors and interrupt service routine must be set up.

IPL 7 holds the parity error interrupt. This interrupt asserts during a read cycle by either the CPU or
by the LANCE when the parity checker finds a data error from Program RAM or from the parity
memory. When a parity error generates during 2 LANCE memory cycle, the LANCE resets and the
CPU acquires the data bus. The CPU then processes the level 7 exception. The interrupt clears
when the CPU executes the interrupt acknowledge cycle for the exception.

5.2.11

(interrupt Vector Addresses

The vector addresses for the DUART transmit signals, priority 1, follow. All vectors are in hexadecimal.
TXINTO - Vector 120

TXINT1 -~ Vector 124
TXINT2 - Vector 128
TXINT3 - Vector 12C

TXINT4 - Vector 130
TXINTS - Vector 134
TXINTG - Vector 138
TXINT? - Vector 13C

Other vector addresses are for:
The general use timer, priority 2,
GENERAL__TIM - Vector 15C

5-10

DECrouter 200 Technical Manual

¢ The LANCE vector, priority 3,
LANCE__INT - Vector 17C

The modem-control interrupts, priority 4,
DSR_PROC_INTR - Vector 180

CD_PROC__INTR - Vector 184

!
{

RI__PROC_INTR

- Vector 188

CTS_PROC__INTR - Vector 18C
SMI_PROC__INTR - Vector 190
3>

The DUART receive vectors, priority 5,

RXINTO - Vector 1A0

RXINT] - Vector 1A4

{

RXINT2 - Vector 1A8

RXINT3 - Vector 1AC

RXINT4 - Vector 1BO

RXINTS - Vector 1B4

! ’

RXINTG - Vector 1B8

§
]

RXINT? - Vector 1BC
®

The refresh timer, priority 6,
REFRESH__TIM - Vector 1DC

The vector for the parity error, priority 7,
PARITY__ERR - Vector - 1FC

The warmstart, bus error.
VWARM__ERR - Vector 8 Internal vector

5.3

HModem Control and Interrupts

Interrupt priority levels 4 and 5 are for modem control. There age eight modem interrupt signals,

one for each modem. The eight interrupt signals account for 40 interrupts from five sources.
Modem interrupts are only needed for input signals. Four of the interrupts are generated from a
DC7053 gate array. The fifth interrupt (CTS) is generated from each of the four DUARTS. Figure

5-2 is a block diagram of the DC7053.

The modem logic latches input signals from a change detect circuit, and detects each transition of
the signal. A change in state causes an interrupt. Transmitted modem control signals, except TXD,

are not interrupt driven. Interrupt priority signals IP6 and IP7 are software driven.

Functional/Logic Description

5-11

Qate Array (DC7053)

6.3.1

The DC753 is an 84-pin CMOS gate array. The device contains six registers: four input registers
for read access and two output registers for write access. All six registers are accessed through the
data bus. The input registers are dual-rank synchronizers. The clock for the synchronizers is
strobed from the MC68000 every 400 nanoseconds. Each synchronizer uses 2 unique, modified
version of address strobe. Each register generates a unique version of address strobe and a unique
interrupt.

—{
> DSRS(L)

-{—> DTR(L)

1> DSR(L)

SMI (L) >~
DC7053
MODEM CONTROL

MEMORY ">
MEMORY

CONTROL (L) EI_>IL)
ADDRESS

pecobe >
ADDRESS [

—{> RESET (L)

~{_> RESET CTRL(H)

—~{> cow)
MODEM SEL (L)

BUS (H)

BUS

—{"> DATABUS (H)

—{"> MODEM PROC
INT (L)

LKG-0578

Figure 5-2:

5.3.2

DC7053 Block Diagram

Table 5-4 shows the register formats for each of the four received modem-control signals. Each
receive register produces an interrupt.

§-12

DECrouter 200 Technical Manual

Table 5-4:

Input Modem Reglster Formate
BiTo

BiT1

BiT2

BIT3

BiT4

BITS

8Ivs

BIT7

DSRO

DSR1

DSR2

DSR3

DSR4

DSR5

DSR6

DSR?

Detect

CDo

CD1

CD2

CD3

CD4

CDs

CD6

CD?

Ring
Indicator

RIO

RI1

RI2

RI3

Rl4

RIS

RI6

RI7

SMI0

SMii

SMI2

SMI3

SMi4

SM15

SM16

SMI7

Data Set

Ready
Carrier

Speed Mode

Indicator

Table 5-5 shows the register formats for the output modem-control signals.

Table 5-5:

Output Modem Regilster Formats

BiTo

BiT2

BiT3

BIT4

BITS

BiT8

BIT7

DTRO

DTR1

DTR2

DTR3

DTR4

DTRS

DTR6

DTR?

DSRS0

DSRS1

DSRS2

DSRS3

DSRS4

DSRSS

DSRSH6

DSRS?

Data Terminal

Ready
Data Signal

Rate Select

5.3.3

lModem Connection

Figure 5-3 shows the hardware configuration for the connection of data terminal equipment (DTE)

o data communications equipment (DCE) that is standard for modem use. The signals in Figure 5-3
function in the DECrouter 200 as listed in Table 5-6.

Table 5-6:

DTE-t0-DCE Connection Signals

Signal Name

DECrouter 200 Function

TXDRXD

Indicates data exchange

RTS/CTS

Indicates continuous activity/programmable

DSR/DTR

Indicates 2 device is on line

Indicates on line activity

Indicates incoming call/automatic answer

Establishes a2 local loop test with the DCE

Estzblishes a remote loop test with the DCE

DSR/SMI

Indicates switch between high-speed and low-speed

for devices using specified option

Functional/Logic Description

5-13

)

DEVICE

)

DECrouter 200

TMD

|2 O

-2 | TXD

RXD

{3 O

O3 | RXD

RTS

CTS

|5 O=

CTS

DSR

|6 O

O6 |

DSR

DTR

{200

=0 20|

DTR

{8 O

-G8

€D

{22

O 22]

DSRS

{23 (O-

() 23]

GND

Q7 |

GND

-=( 4 | RTS

DSRS

LKG-0%518

Flgure 5-3:
5.3.4

DTE-to-DCE Hardware Configuration

WNull Modem Connection

Figure 5—-4 shows the hardware configuration for 2 DTE-10-DTE connection to use the DECrouter
200 as a virtual DCE. Table 5-~ shows the signals in a DTE-to-bUTE connection.

5-14

DECrouter 200 Technical Manual

Table 5-7:

DTE-t0-DTE Connection Signals

Gignal Name

BECrouter 200 Function

TXD/RID
RTS/ICTS

InGicates data exchange
Indicates flow control

RTS

Is controlled functionally as CTS in software

CTs

is controlled functionally as RTS in software

DSR/DTR

Indicates flow control or on-line device

DSR
DTR

Is controlled functionally 2s DTR in sofiware
Is controlied functionally as DSR in software

Is ignored

Is controlled functionally as Rl, establishing calls as 2a DCE

RL
DSRS/SM1

Is controlled functionally as CD, indicating an active network
Indicates a switch between high-speed and low-speed for devices using specified
option

DECroutss 200

DEVICE

GND 70-

@ GND

TXD

20~

’AXD

RTS

4 O

CcTS

DTR

00—

DSR

6 Oo—vs j

K
r

I—

—X

—0 2

TXD

=0 3

RXD

=) 8

-~ 4

RTS

=) 5

CTS

-0 20

DTR

+) 6

DSR
Ri

LKG-0517

Flgure 5—4:

Nuli Modem Hardware Configuration

Functional/Logic Description

5-15

8.4

Router Memory Subsystem

The addressing logic in the DECrouter 200 allows the CPU, under program coatrol, to access the
following:
o

The DUART and the LANCE internal registers

512 KB of dynamic program RAM

32KB of PROM

2KB of EEPROM

32 bytes of physical address PROM (PA FROM)

The addressing logic also allows the LANCE to perform direct memory access (DMA) transfers with
RAM. Figure 5-5 illustrates memory allocation in the DECrouter 200.

5-16

DECrouter 200 Technical Manual

000000

PROGRAM RAM
128K X 16

0-07FFFF (ROUTER)
080000

EEPROM
2K X 8

O0BOFFE
1000071

DUART 0
DUART 1

10001F
100021

10003F
100041

DUART 2

DUART 3

LANCE

10005F
100061

10007F
100080
10002

MODEM

1000A1

10007F

CONFIG REGISTER | 0000
180000

EPROM
16K X 16
:

1B7FEF
100001

ADRPROM
32X8
1COO03F

LKG-0578

Figure 5-5:

DECrouter 200 Address Space Allocation

Functional/Logic Description

5-17

5.4.1

Address Selection

Asynchronous device address space is selected by the program address bit, BUS

<A20:A00> . Fig-

ure 5-6 shows the CPU selection of the DECrouter 260 address space.

5-~18

DECrouter 200 Technical Manual

7IR

[Pyo

vyFrR

wero B A el

e ISR
00
NN T 7/

L
oo (TA

o s (7L L1
L7
w777
D
N S /R

Flgura 5-8:

cvom TR0

0 K K No

CPU Selection of Router Address Space

Functional/Logic Description

5-19

The address decoder contains 2 fusabie-link array device called Programmable Array Logic (PAL),

programmed as shown in Table 5-8.

Table 5-8:

Programmable Array Logic Functions

Signal

Device Selected

ROM_SEL__L

Program ROM

EEROM_SEL_ L

EEPROM

ADR__PROM__SEL_L

Ethernet Address

DUART _SEL__L

DUART Register

LANCE _SEL__L

LANCE Slave

MODEM__SEL_L

DC7053 Gatz Array

CONFIG__LAT__L

Configuration Register

DATA__ACK __L

Acknowledge Memory Cycle

PAL_STATE__2_ L

Enable Writes to EEPROM

BBUS_ENA_L

Enable Bus Transceivers

NOTE
The Enable Bus Transceivers signal is for access of data over the buffered data bus.

RAM addresses are not selected with the PAL. The RAM logic has an internal address
decoder.

The CPU uses the complement of address bit < A00> on a byte transfer.
Also:
< AGQ> on 0 = Selects data bits BUS DAL< 15:08>
<AGO> on ! = Selects data bits BUS DAL<07:00>

As bus slave, the LANCE is accessible only on word boundaries. As bus master, LANCE uses the standard Digital convention in selecting the upper or lower byte, which is:

<A00> on 0 = Selects data bits BUS DAL<07:00>
<A00> on 1 = Selects data bits BUS DAL< 15:08 >
=
225

devices are accessible only un the lower byte.

5.4.2

Power-Up Addressing

When the signal clear (CLR__L) is negated following the power-up sequence, the CPU fetches its
program counter (PC) and stack pointer (SP) from memory location 0.

Location O is usually defined in program RAM address space. But the PAL logically swaps the program ROM and program RAM address space, selecting program ROM under the following powerup conditions:

§-20

Technical Manual
200uter
DECro

1. Output port 2 of all four DUARTS asserts the complement of output-port register bit OPR<2>
as 0, active low.

2. DRAM__ENA__L, OP2 from the fourth DUART, is asserted high to the PAL.

3. Location 4 of Program ROM points to the Self-test power-up routine. RAM_ENA__L is then
negated or asserted under program control.

Self-test starts program execution in ROM. Self-test enables RAM, and starts executing tests in
sequence. Some test routines are copied to, and operate in RAM. Self-test then jumps to the initialize program, which transmits a request for 2 down-line load of router operating software from 2
load host volunteer. Chapier 3 provides a detailed explanation of down-line loading.
£.4.2

DUART and LANCE Register Addreasing

The CPU selects the DUART and the LANCE internal registers by asserting address bus bits BUS
<A20:A01 >, as follows:

With BUS <A20:A19> H equal to 10, the PAL asserts DUART/LANCE L, enabling the address
decoder.

2. BUS < A07:A05> to the address decoder selects 2 DUART or the LANCE by asserting one of the
signals PJC ENB <3:0> L or PJCENB LANCE L.

DUART register selects BUS

<A04:A01> for a read or a write transfer.

The LANCE internal latching Register Address Port (RAP) selects one of four Control and Status
Registers (CSRs).

5.4.4

Program Random Access Memory

The router uses up to 512 KB of dynamic RAM as the operating main memory from where the
fouter operating software is executed. Program RAM uses 2 multiplexed 9-input row and columnaddressing method selected and clocked by a delay line as shown in the print set.

5.4.5

CPU-initiated Transfer

The CPU starts a transfer with program RAM as follows:

1. The CPU asserts an address on BUS<A20:A21> and asserts buffered address strobe
(BASTRB__L).

With BUS<A20:A19> equal to 00, combinational logic circuitry asserts RAM__ENA__L.
enabling the signal inpus 10 the delay line.

5.4.6

LANCE-Initlated Transfer

The LANCE starts a transfer with program RAM as follows:

When the LANCE gains access to the bus, the arbitrator asserts LAN_HLD__ACK__L, enabling
the LANCE input to the delay line.

Functional/Logic Description

5-21

2. The LANCE asserts an address on address BUS <A16:A01 > and asserts address latch enable
(ALE__H, ASTRB__L and ADR__ENA__H), which opens the address tatch for BUS <A15:A01>.
5.4.7

Deata Transfer Cycie

The data cycle of 2 DMA transfer initiated by the CPU or the LANCE follows this sequence:
1. A buffered write (BWRT__L) defines the transfer 2s a read or 2 write.

2. When the CPU asserts buffered address strobe (BASTRB__L), or the LANCE deasserts ALE_H,
the high-to-low transition to the delay line generates row address strobe (HBT__RAS__L and
LBT__RAS_1).

3. Onalow-to-high transition on the delay line input, the row and column addresses are loaded to
program RAM, selecting the transfer address as follows:
¢

The address value on BUS
< A08:A01> is asserted on MA1 to MA9 from the address multiplexer and is clocked to the program RAM row address register by HBT__RAS_L and
LBT

5.4.8

_RAS_L.

When RAM acknowledge (RAM_ACK__H) is asserted by the delay line. the address value
on BUS< A16:A09> is asserted on MA1 to MA9 from the address multiplexer.

Dynamic RAM

There are four 12&5-KB banks in DRAM. Any bank can be depopulated to decrease its memory size.
There are also two 256 K X 1 memory chips, used for parity, that cannot be depopulated.

Dynamic RAM requires refresh, and causes the router software to interrupt every 3 8 milliseconds.
During the interrupt. the CPU reads 512 consecutive bytes of DRAM, updating al! the memory cells
in the four bariks of RAM and the parity chips.

Dynamic RAM has two parity bits for each word. The low-byte (DO to D7), has even parity, and the
high-byte (D8 to D15) has odd parity. Write cycles generate and store parity, while read cycles
interrupt the CPU when errors are read.

NOTE
e

The router software initializes all DRAM on power up because reading unused
memory locations may indicate parity errors.

The write cycle generates the parity, and the read cycle tests parity that is written by the write cycle.

Parity error interrupts occur on IPL 7, are always fatal, and are not masked by the software. The
software can prevent interrupts by completely disabling parity. The software can also force parity
errors by changing bit states on the DUART output ports, which enables testing of the parity logic.
When the CPU or the LANCE asserts BUS UDS L and/or BUS LDS L, then MA1 to MA9 are clocked to
the RAM column address register by either or both of these signals:
e

Upperbyte column address strobe (HBT__CAS__L)

5~22

DECrouter 200 Technical Manual

Lowerbyte column address strobe (LBT_CAS__L)

On a read, the program RAM data lines are enabled as data outputs by HBT__CAS__L and/or
LBT__CAS__L.

5.4.9

Erzsable Program ROM (EPROM)

The router uses 32 KB of EPROM for storing the loader for the Load/Dump code. The EPROM is
also used for Self-test, for diagnostics, and for the Online Debugging Tool (ODT).

5.4.10

Physici? Address Programmable ROM (PA PROM)

Every router has 2 unique physical Ethernet address in 32 bytes of PA PROM.
The address PROM locations are selected as follows:
1.

With BUS<A20:A19>

equal to 11 and BUS<AI18> equal to 1, the PAL circuit asserts

ADR__PROM__SEL__L and selects the physical address PROM.

BUS<A05:A01 > then selects one of 32 byte locations i the low-byte position. Bus selection is
enabled by BLDS__L.

5.4.11

Electrically Erasable Programmabie ROM (EEPROM)

The router has 2 KB of nonvolatile EEPROM in which to store the terminal default, the modem-

control. and the system default parameters for each communication line. These parameters can be
changed by 2 user and stored either permanently in EEPROM or temporarily in DRAM. During
power up and power down, the reset circuit protects the EEPROM from data corruption by assert-

ing the CTRL signal, which holds the EEPROM Output Enable input low.

5.4.12

Write Inhibit

The EEPROM circuit has acrive low inputs and output signals are low. The write protect bit should

be read as 1 to verify that the EEPROM writes are disabled. Thist it can be read from input port bit §
(IP5) of DUARTO.
The EEPROM internal write process takes up to 10 milliseconds. The address, the data. and the con-

trol signals are internally latched by the EEPROM. and the processor write cycle takes 600 ns. This
allows the CPU to execute other programs during the internal write process. During a write cvcle.

read cycles yield random data. The read/write address range for EEPROM is 080001 to O80FFF.
The EEPROM locations are selected as follows:

With BUS<A20:A19> egualto 01.the PAL asserts EEPROM__SEL__L. which selects EEPROM.

BUS<AI11:A01> selects one of 2,000 byte locations in the lower byte position. Selection of a

byte location is enabled by BLDS__L.

5.4.13

Asynchronous interface

The four DUART chips used for external interface are operated under program control through
interrupts. The CPU selects the DUART internal registers on address bus bits: BUS< A20:A19> and
BUS<AOTM:A05>.

Functional/Logic Description

5-23

In the program, address bit <A00> must be set to select the lower byte for data transfer.
BUS<A04:A01> then selects the hexadecimal address to read or to write. Table 5-9 gives the
DUART registers, the hexadecimal addresses, and the read/write functions. A dash (-) means function undefined.

Table

o £

5-9:

Bus

[

PPy

Summary of DUART Regisier Functions

Address

Read Function

Write Function

1060001
100003
100005
100007
100009

Mode Register A
Status Register A
RX Holding Register A
Input Port Change Register

Mode Register A
Clock Select Register A
Command Register A
TX Holding Register A
Aurxiliary Control Register

10000B
16000D
10000F

Interrupt Status Register
Counter/Timer Upper Register
Counter/Timer Lovwer Register

Interrupt Mask Register
Counter/Timer Upper Register
Counter/Timer Lower Register

100011

Mode Register B

100013

Status Register B

Clock Select Register B

100015
100017
100019
10001B
10001D

RX Holding Register B
Input Port State Register
Start Counter/Timer Command

Command Register B
TX Holding Register B
Output Port Configuration Register
Set Output Port Register Bits

10001 F

Stop Counier/Timer Command

Clear Output Port Register Bits

NOTE
The addresses in Table 5-9 select DUARTS. To select DUART 1, an offset of 20 must
be added. To select DUART2, an offset of 40 must be added. To select DUART3, an

offset of 60 must be added.

5.4.14

DUART Signal Descriptions

The following list describes the router implementation of the DUART operating signals.
Data/Address Bus Signals

Address Bue (BUS
< A04:A01>H) — The internal DUART registers are selected by the CPU
with four of the three-state address bus lines. These are receive-only lines for the DUARTS that

can only be bus siaves.

Date Bus (BUS DAL <07:00> H) — The lower byte of the bidirectional three-state data bus is
used to transfer internal register data on 2 CPU-initiated transfer with 2 DUART.

5-24

DECrouter 200 Technical Manual

Asynchronous Bus Control Signals

Ensble n (DUARTn_SEL__L) — Sclects one of four DUARTs on a CPU-initiated transfer,

Write Enable (DUART_WRT__L) — Enables the input of the selected register to receive write

where n is the DUART number, 0 to 3.

data from the da?a bus.

Read Enable (DUART__RD__L) — Enables the three-state data bus output and asserts read data
.

from the selected register.

Channels A and B Receive and Transmit Signals

Receive Data n (RDXn__L) — Accepts serial data from the receive-level converters, where n is
the asynchronous port number, 0to 7.

Tranamit Data n (TXDn__L) — Applies serial data to the transmit-level converters, where n is
the asynchronous port number 0 to 7.

Clock input X1 (DUART __CLIK__L 3.68 MHz) — Provides the base clock (16X) from which the
transmit and receive baud rates are derived for cach channel.
Outpet Port Signals

Qutput Ports OPE/OP7 (TXINTn__L) — OP6 and OP7 assert 2 transmit interrupt request from
channels A and B (TX RDY A and TX RDY B) to the priority encoder, where n is the asynchronous port number, 0to 7.

Output Ports OP4, OPS (RXINTn_L) — OP4 and OPS assert a receive interrupt request from
channels A and B (RX RDY A and RX RDY B) to the priority encoder, where n is the asynchronous port number, 0to 7.

QOutput Port OP3 — OP3 asserts the following counter/timer signals from each DUART:

DUARTO — REFRESH__TIM__L from the refresh timer interrupts the CPU to refresh the
dynamic program RAM. This signal is also used to clock the watchdog timer and the LED
timer.

- DUART{ — GENERAL__TIM__L from the counter/timer is used as the slot timer by the program.

DUART2 — WATCH__DOG__L from the warchdog timer interrupts the CPU (o reinitialize
the router and to reload the router software if the timer is not periodically cleared by the
program.

DPUART3 — LED__H from the counter/timer activates, by blinking. the LED indicator on
nonfatal Self-test errors and leaves the LED lit for 2 no-error condition.

Functional/Logic Description

5-25

Output Port OP2 — OP2 asserts selection signals from each DUART:

DUARTO — SET__HBT__PAR__1 forces parity errors on data bits DO8 to D15.

DUART1 — EEPROM__WRT__H enables writing to EEPROM.

DUART2 — SET_LBT_PAR__L forces parity errors on data bits DOO to DO7.

DUART3 — DRAM__ENA__L selects program ROM on a power up by swapping program
ROM and RAM address space.

Output Port OPO and OP1 — OP0 and OP1 are used for generating the RTSn__L signals, where
n is the port number.
Input Port Signals

input Port IP2 — IP2 in each DUART accepts the following signals:

DUARTO — TIMER__CLK__H, 1.84 MHz H is the refresh timer clock.
LK__H, 1.84 MHz H is the general purpose timer clock.

DUART2 — REFRESH__TIM__L is the watchdog timer clock.

DUART3 — REFRESH__TIM__L is the LED timer clock.

Reset Signal

The DUARTS are reset when the configuration latch is reset and the . )UARTM reset signal is disabled on the first write to the latch The DUARTSs remain in reset mode nntil the first write is
done. The reset signal:

Clears the internal registers

Stops the counter/timer

Clears the output ports GP <~:0>

Sews channels A and B to inactive states

Sets channels A and B output to active high

Each DUART provides the following three sets of function registers:

Receive and Tranamit Registere — Each DUART provides two full-duplex serial asynchronous channels: channels

Aand B.

The receive and transmit registers for channels A and B are described in the following section
Each channel connects to an approved asynchronous device through transmit (TX) and receive
(RX) level converters that conform to EIA RS-232-C and to CCITT V.24 specifications.
input and Output Port Registers — The input/output ports and registers are used for general
functions or are configured for specific 1/0 functions.

5-26

DECrouter 200 Technical Manual

([nterrupt Contro! and Counter/Timer Reglaters — The interrupt control and counter/timer
registers are described in Section 5.2.10.

§.4.15

Receive and Tranamit Registers

Figure 5-7 shows the register formats, the hexadecimal addresses, and the read/write functions for

channels A and B.

The register functions are the same for both channels. The mnemonics for the bits start with the letter A or B to identify the channel.

100001 - MR1A

MODE REGISTER ADDRESS 1

AX ATS

RX WNT

SEL A8

ERR MODE

166011 -R1B § ENAB

100001 - MRZA

SEL AB

SEL AE

ers

READ/MWRITE

00
,

STOPBITLGTHASB

STATUS AEGISTER A/8

8PC SELAB

[

CONTROL | ENABLE AB

@
PAR TYPE

MODE ADDRESS REGISTER 2

mars

SELAB

PAR M0DE

SEL AB

CHNL MODE

100011 - MR2B

)

FFULL
AL

READWRITE

)
axRoY | ogan
AR

COMMAND SELECT REGISTER A‘B

o7
100903-CSRA

10001 3CSRB

[+x]

RCV CLK SEL A/B

XMTCLK SEL AB

WRITE

COMMAND REGISTER ADDRESS & 8

100005-CRA
103015-CRB

MUSY BE

WHSC CUND A8

ZERO

OIS
P TX

ENTX
o

OIS AX

EN RX

[+2]

DELTA

WRITE

AUXILIARY CONTROL REGISTER

00009-ACR

Flgure 5-7:

B8RG

SEL

[

COUNTER/TINER

MODE AND SOURCE

:?,

P INT

PO INT

WRITE

DUART Recelve and Transmit Reglster Fonmats

Functional/Logic Description

5-27

5.5

MRnA asnd MRnB Mode Registers

Both channels contain two mode registers that are designated and are selected as:
Channel A — Mode Registers 1 and 2; MR1A and MR2A
Channel B — Mode Registers 1 and 2; MR1B and MR2B

Regleter Polnter

MR1A and MR1B are both selected by a pointer that is cleared on 2 power-up sequence. When
MR 1n is accessed for either channel, the pointer is set, selecting MR2n for all subsequent reads or
writes to the channel address. The pointer remains set until the router is initialized or the Reset
Pointer command is issued from the command register for that channel. MR2A is pointed to after
reading or writing MR1A.

§.5.1

MR1A and MR1B Bit Assignments

Table 5-10 describes the read/write bit assignments for MR1A and MR 1B, and Table 5-11 describes
the bit assignments for MR2A and MR2B:

5-28

DECrouter 20¢ . echnical Manual

Table 5-10:

WMR1A and WR18 BR Assignments

Bits

Name

Description

<07>

Receive Request to Sead

With bit set, cutput ports OP0 and OP1 assert these states:

Enable

(RX RTS EN A/B)

OPO = RXRTSA

OP1 = RXRTSB

Each output is negated on 2 full FIFO buffer and is asserted
when an empty FIFO location becomes available for the channel

Outputs OPO and OP1 can also be enabled for other functions
<06>

Receive Interrupt Select

Enables ISR <05> and <01 > 10 assert cither the RX RDY or

(RX INT SEL A/B)

the FFULL flag as follows:

R INT SEL A/B BRt
Onad
Onat

ISRBIT

<05>

ISR <01>

RXRDYA

FFULLA

ISR <05>

RXRDYB

FFULLB

Eeror Mode Select

Selects the error mode as:

(ERR MODE SEL A/B)

0-Ci

cter

1 - Block

<04:03>

Parity Mode Select
(PARTYPESEL A/B)

Selects the parity check mode as:
0 - With Parity
1 - Force Parity
2 - No Parity
3 - Multidrop

<02>

Parity Type Select

Selects the parity type as:

(SPC SEL A/B)

0 - 5 bits

1 -G bits
2 -7 bits
3 -8 bits

Functional/Logic Description

5-29

Table 5-11:

WMode Reglster MR2A and MR2B Bit Assignments

Bits

Name

Description

<07:.06>

Channel Mode Select

Selects the transmit mode as follows:

(HNL MODE SEL A/B)

0 - Normal (full duplex)

1 - Auto Echo (transmitter uses recciver clock)
2 - Local Loopback (receiver uses transmitter clock)
3 - Remote Loopback (transmitter)
<05>

Transmit Request to Send

When bit set, output ports OPO and OP1 assert the follow-

Select

ing states:

(TX RTS SEL A/B)

OPO = TXRTSA

OP1 = TXRTSB
>
<04

Transmit Clear to Send

When bit is set. output ports OP0 and OP1 assert the fol-

Sewect

lowing states:

(TXCTSSELA/B)

OPO = TXCTSA
OP1 = TXCTSB

<03:00>

Stop Bit Length

(STOPBITLGTH A/B)

Sets the length of the stop bit in bit~-time increments The
DECrouter 200 supports the following stop bit values
- 1.000
F-2000

The vendor specification provides 2 complete list of the bit
time values.

5.5.2

SRA and SRB Status Registers

Table 5-12 describes the status flag and the read functions for SKA and SRB

5-30

DEC router 200 Technical Manual

Table 5-12:

Status Regleter SRA and SRB Bit Asslgnment
Description

Bits
<07>

Received Break
(RCVD BRK A/B)

<06>
<05>

Indicates that an all-zero character was received without a stop
bit, using only one FIFO ocation. This bit set also enables BRK B

A flag in ISR < 06> or <02>.
CHNG or the CHNG BRK

Framing Error

Indicates that a stop bit was not detected when 2 received char-

(FRAM ERR A/B)

acter was clocked to the FIFO.

Parity Error

Indicates incorrect parity on a received character when the With
Parity or Force Parity mode is enabled (sec MR1A and MR1B

(PAR ERR A/B)

<04:03>.
<04>

<03>

(OVRN ERR A/B)

Indicates that a character was received with 2 full FIFO and input
character buffer, data has been lost.

Transmit Empty

Sct after the last stop bit of a character is shifted from the serial

Overrun Error

(TX EMPTY A/B)

transmit register when no other character is avaiiabie in THRA or
THRB. The bit is cleared when the holding register is loaded or
when the transmitter is disabled.

<0Z>

Transmit Ready

indicates that THRA or THRB is empty and is ready to accept

(TX RDY A/B)

another character for transmitting. The bit is set when the transmitter is enabled, and is cleared when the holding register is
loaded or the transmitter is disabled.

<01>

<00>

(FULL A/B)

Set when 2 third received character is loaded to the FIFO buffer
for RHRA or RHRB. The bit is cleared when a character is read,
unless another bit is available in the receive shift register.

Receive Ready

Indicates that a received character is clocked to the FIFO for

(RX RDY A/B)

RHRA or RHRB. The bit is cleared when all characters are read.

FIFO Full

Functional/Logical Description

5-31

8.5.3

C8RA and CSRB Clock Select Reglsters

The information in Tables 5-13 and 5-14 explains the write functions for CSRA and CSRB.
Each register selects receive and transmit baud rates for its channel from one of two sources,
depending on the state of the auxiliary control register bit: ACR<K07>.

Table 8-13:

Clock Select Register CSRA and CSRB Bit Assignments

Bits

Name

Description

<07:04>

Receive Clock Select

Sets the receive clack for the channel to one of the baud

{RCV CLK SEL A/B)

rates listed below.

Transmit Clock Seleci

Sets the transmit clock for the channel to one of the baud

(XMT CLK SEL A/B)

rates listed below.

<03:00>

Two ranges of baud rates are selected for either channel by
the following states of ACR<07>:

RCVIAT
CLKSEL

Sat6
(ACR<0O7>

SET1
(ACR<O7>

110

1345

3
4

200
300

equais 0)

equals
1)

150
300

5
6

600
1200

1050

2400

4800

7200

9600

%600

38400

19200

Timer

IP<6:3>-16X IP<6:3>-16X

IP<6H:3>-1X

1IP<6H:3I>-1X

Table 5- 14 shows the bit settings in clock select registers Aand B.

5-32

DECrouter
200 Technical Manua!

Aend B
Table 6-14: Clock Select Registers
s

Kame

Deecrigtion

<07>

Must Be Zero (MBZ)

Unused
and must be zero

<06:04>

MISCCMNDA/B

Writing this field with a 3-bit code issues one of the following
commands to the channel:
0 ~ No Command

or MR1B)
1 ~ Reset Pointer (selects MR1A
2 - Resct Receiver

3 - Reset Transmitter
4 - Reset Error Status

3 - Resen Beeak Change Interrupt
6 ~ Start Break
7 - Stop Break

<03>

DISTX A/B

Disables the channel A or B transmitter. Resets
the TX EMPTY

and TX RDY status bits, SRA or SRB<03:02>, see Table
5-12.

<02>

ENTXA/B

Enables the channel A or B transmitier. Sets the TX RDY status
bit, SRA or SRB<
02 >, see Table 5-12.

<01>

DISRX A/B

Disables the channel A or B receiver, except for the multidrop

<00>

ENRX A/B

Enables the channel A or B receiver. The DUART special
wake-up mode is not used in the DECrouter 200 configura-

>, sce Table 5-10.
mode MR1A or MRIB <04:03

tion.

5.5.4

RHRA and RHRB Recelve Holding Registers

Registers RHRA and RHRB are Receive Data Read registers.

FIFO Buffer - Both RHRA and RHRB have 2 three-byte FIFO that acts as a cache for up to four characters, including the serial receive input data buffer. Each FIFO location also stores the received
character status: parity error, framing error, and received break.

The RX RDY A or the RX RDY B bit is set, SRA or SRB bit <00 > . when one to four characters are
available, and remains set until the FIFO is empty.

The FFULL A or FFULL B status bit is set, SRA or SRB bit <01 >, if all three locations for the channel
are full. Reading a character empties a FIFO location and negates FFULL, unless a character is waiting in the serial input buffer.

RX RDY or FFULL can be used to assert 2 program interrupt request. RX RDY is used in the
DECrouter 200

5-33

5.5.5

THRA end THRB Trensmit Holding Regleters

Registers THRA and THRB are for transmit data write functions. When a register is loaded by the
CPU, the byte is parallel loaded to the Transmit Shift Register from where the byte is shifted out as
serial data to a device.

5.5.6

Auxiliary Control Reglster ACR< 07>

Table 5-15 describes the write functions for ACR bit ACR<07
>, which is used with CSRA and
CSRB.

Table 5-15:

Bits

Auxiillary Control Reglster ACR< 07>

Name

<07>

Description

Baud Rate Generator

Sclects one of two transmit and receive baud rate ranges as

Select

described for CSRA and CSRB bit fields <07:04> and

BRG SEL

<03:00>.

<06:04>

Used with the counter/timer register.

03:00

Used with the input port change register

§.5.7

Input and Qutput Port Registers

Figure 5-8 shows register settings. hexadecimal addresses. and read/write functions for the Input
Port (IP) and Output Port (OPj registers.

5-34

DECrouter 200 Technical Manuai

100080

CHNG

1#3

CHNG

PUT
PORT CHANGE REGISTER (ACTIVE MIGH)

CHNG

STATE

192

STATE

CHNG

)
1P

state | READ

AUXILIARY CONTROL REGISTER

BRG

160089

04
COUNTER/TIMER

SEL

[}
PICHNG

840DE & SOURCE

T EN

INT EN

P2 CHNG

INTEN

P11 CHNG

O CHNG

INTEN

WRITE

WPUT PCRT CHANGE REGISTER

100078

)

[ 4]

1?3

[ 4]

100078 | TXRDYB | TXRDvA

CUTPUT POAT CONFIGURATION REGISTER

B UL

e
1=

RXC

READ

00
0= TXCA

10=TX

11 e AXCA

WRITE

(LlN24

Figure 5-8:
§.5.8

DUART input and Output Port Registar Bit Settings

Input Port Change Register (IPCR)

Table 5- 16 describes the read functions for the IPCR

Table 5-16:

(PCR Port Change Register Bii Settings

Bits

Mame

Degcription

<07:03>

IP<03>CHNG

A bit is set by 2 signal change on corresponding input port All
bits are cleared. including ISR < Q7 > when register is read at
address 4

0300

5.5.9

IP< 3.0>STATE

These bits assert the states of signals on inpus ports IP<03>

Auxillary Control Register (ACR<03:00>)

Table 5- 1~ describes the write functions for ACR < 03:00
> that are used with the IPCR.

Functional/Logic Description

5-35

Teble5-17:

Auxiilary Control Register

Bite

dame

Deseription

<07>

Used with the clock select registers.

<06:04>

Used with the counter/timer register.

<03:00>

Input Port

<3:0>

Change Interrupt
Enable (IP <3:0>

When 2 bit is set, and the corresponding
bit is set in IPCR
<07:04>, ISR <07> is also set. The INTR output is also
asserted high, and is unused in the router.

CHNG INT EN)

5.5.10

Input Port Status Register (IPSR)

The signal states connected to input ports IP <6:0> are read bits IPSR < 06:00>; IP<7> is not
used and IPSR<07 > isalwaysreadasa 1.

§.5.11

Output Port Configuration Register (OPCR)

Table 5-18 describes the write functions for the OPCR, which controls the function of output
ports OP<7:0>.

Table 5-18:

Output Port Configuration Register (OPCR)

Bita

Name

Description

<07:04>

Output Port<7:4> Select

Control output ports OP < 7:4> in one of the following two

(OP<7:4>SEL)

ways.

Cleared:

Each clear bit enables the complement of the corresponding
OPR bit to output port OP<7:4 > .
Set:

Each set bit causes the corresponding output port to assert the
following signal:
OP7 - Asserts channel B transmit interrupt request, the com-

plement of TX RDY B.
OPO - Asserts channel A transmit interrupt request, the complement of TXRDY A.
OP5 - Asserts channel B receive interrupt request, the com-

plement of RX RDY B.

OP4 - Asserts channel A receive interrupt request, the complement of RXRDY A,

5-36

DECrouter 200 Technical Manusl

Teble 5-78 (cont.):

Oulput Port Configuration Regleter (OPCR)

Bits

Name

Description

<03:02>

Output Port 2 Select

Enables output port OP3 or OP < 3:2>> to assert one of the fol-

(OP3 SEL)

lowing signals:

0 - Output ports OP3 and OP2 assert the complement of output port register bits <03:02>.

1 - Asserts the counter/timer output at the programmed frequency in timer mode, or in overflow counter mode.
<03:02>

2 - Asserts the 1X clock output for the channel B transmiitter.
3 - Asserts the 1X clock output for the channel B receiver.

<01:060>

Output Port 2 Select

Enables output port OP2, or OP1 and OPO, to assert the fol-

(OP2 SEL)

lowing signals:

0 - Output ports OP
< 1:0> assert the complement of output
port register bits OPR<01:00> .

1 - Asserts the 16X character clock output for the channel A
transmitter as follows:

CSRA < 3:0> = E. assert 16X character clock
CSRA<3:0> = F, assert 1X character clock

2 - Asserts the 1X clock output for the channel A transmitter
3 - Asserts the 1X clock output for the channel A receiver.

§.5.12

Output Port Register (OPR)

The OPR can be used as a general purpose register or as a control register. The register is written

with ones at either of two addresses that set or that clear the selected bits as follows:
®

Address 10001D (bits set) - Writing a byte to the address sets the selected bits as:
1 = Set the bii

0 = Nochange

Address 10001F (clear bits) - Writing 2 byte to the address clears the selected bits as:
1 = Clear the bit

0 = No change

5.5.13

Interrupt Control and Counter/Timer Registers

Figure 5-9 shows the register bit settings, hexadecimal addresses, and read/write functions for the
interrupt control and counter/timer registers.

Functionai/Logic Description

5-37

CONTROL

BRG

INTERAUFT

BAK B

AX ADY B

AEGISTER

04 03

(]

ALIKELIARYY

COUNTER/TIMER MODE

SEL

AND SOURCE SELECT

P3P0
04

wRITE

”

CNTR

o | srune | TXPOYE | gy

BAK A

RX ADY A

o | sruna | TXROVA | READ

()

Status

CHNG

WERRUPT |
REGISTER

0?7

UPPER

ggz’;?szfl WAER

COUNTER/TIMER CT. 1508 -

READ'WRITE

LowER

%N:ERRMER

COUNTERTIMER C/T. 07 0C

READWRTE

ISTER

0
10000 STARTC Y

1000F STOP C11

Figure 5-9:

§.5.14

oc
]

COUNTER/TIMER COMMANDS

REAL

DUART Interrupt Control and Counter/Timer Register Settings

Auniliary Control Register (ACR < 06:04 >)

Table 5- 19 shows the write functions for ACR bits ACR
< 06:04 > . which are used with the counter/umer

5-38

DECrouter 200 Technical Manual

Auxiliary Control Register ACR < 06:04 >

Teble 5-19:
]

Bite

Neme

Description

<07>

Used with the clock select registers.

<06:04>

Counter/Timer Mode
Source Select and

Sets the counter/timer register to the selected clock source a«
follows:
:

(CTMS SEL)

Code

tode

Clock Source

Counter

External input (IP2)

Counter

TXCA channel A 1X the trans-

Counter

TXCB channel B 1X the trans-

Counter

Crystal

Tim or

External input (i1P2)

Timer

External input (IP2) divided by

Timer

Crystal or external clock

mit clock
mit clock

divided by 16

external

clock

Timer

Crystal

external

clock

divided by 10 and used with the
inpw port registers

<03.00>
8.5.15

Interrupt Status Register (ISR)

Table 5-20 shows the read functions for the ISR status flags. The ISR is 2 summary register that
reflects the states of the interrupt flags.

Interrupt signal outpui is asserted from the DUART when the corresponding flag bit is set in the

20 e

IMR.

Functional/Logic Description

5-39

Table 5-20:

interrupt Status Reglster (I8R)

Bits

Name

Description

<07>

IP CHNG

Reads as 2 1 when any IPCR <07:04 > bit is set and the corresponding bit is set in <ACR03:00> . The INTR output is also

asserted from the DUART and is unused in the router.

<06>

Channel B

indicates the channel B receiver reached end of a break.

BRK B CHNG

Cleared by the reset break change detected in the beginning or
at the end of
a break command from command register B.

<05>

Receive Ready B or

FIFOFull B
RX RDYB/FFULLB

Asserts either of the following states, depending on the state
of MRIB< 06> :
MR1B<0&> = 0asserts
SRB bit <00> (RX RDY B)

MRIB<O06> = 1asserts SRBbit <01> FFULLB
<04>

<03>

Transmit Ready B

Asserts the state of SRB bit <02> TX RDY B OP4 - Asserts

TXRDYB

channel A receive interrupt request.

Counter Ready

Set by the counter/timer register. depending on the register
mode.

Counter Mode:

Set when the upcount register reaches the count value.
Cleared by the stop counter command; steps at the counter.
Timer Mode:

Set each time the downcount register reaches a 2ero count.

Cleared by the stop counter command; stops the counter The
counter is reload=d from the holding register on each zero
count

<02>

<01>

Channel A

Indicates that the channel A recciver detected the beginning

Change in Break

or the end of abreak. This is cleared by the reset break change

BRK A CHNG

interrupt command from Command Register A

Receive Ready A or

Asserts either of the following states, depending on the state

FIFO Full A

of MR1A <06>:

RXRDY A/FULL A

MRI1A <006> = Oassertsbit <0>,RXRDY A

MR1IA <06> = 1 asserts SRAbit <01>, FFULLA.
<00>

Transmit Ready A

5.5.16

Interrupt Mask Register

Asserts the state of SRA bit <02>
,
TXRDY A

Writing 2 1 to a bit in the Interrupt Mask Register enables the interrupt signal (INTR) for the corre-

sponding flag in the Interrupt Status Register.

DECrouter 200 Technical Manuyal

§.5.17

CTUR end CTRL Counter/Timer Reglaters

The counter/timer has two 16-bit registers, a holding register and a count register. The count register function depends on whether it functions in counter mode or timer mode.
CTUR and CTLR are holding registers that store the upper-byte and the lower-byte vaiues as shown
in Figure 5-9. The register addresses are write-only to the holding registers in the counter mode.
The register addresses are read only in the timer mode. The minimum load value is 0002 hexadecimal.

Counter Mode - The counter mode is 2 down counter that sets the interrupt status register bit,
< 03> CNTR RDY, when the counter reaches its final value of 0000 (hex). Output port OP3 is programmable to assert the ISR state <03>.

The commands affect the counter mode as follows:

$Stop Counter - This stops the Count Register and clears ISR <03>.

Start Counter - This loads the Count Register with the holding register contents and starts the
count register.

Timer Mode - The Count Register is a binary up-counter that runs continuously, generating a
square wave twice the time stored in the holding register.

Each overflow sets interrupt status register bit

<03 >, CNTR RDY, and reloads the count register

from the holding register. OP3 can be programmed to produce a square wave.
The commands affect the timer mode as follows:

Stop Timer - This clears the ISR <03 >, but does not stop the count register.

Start Timer - This terminates the timing cycle, loads the count register with the holding register contents, and starts a new timing cycle.

5.5.18

Counter/Timer Start and Stop Commands

Reading either of the following addresses, issues one of these counter/timer commands:
For DUARTO:
®

Address 10001D - Start counter/timer

Address 10001F - Stop counter/timer

For DUART1:
¢

Address 10003D - Start counter/timer

Address 10003F - Stop counter/timer

For DUARTZ:

Address 10006D - Start counter/timer

Address 10C0G6F - Stop counter/timer

Functional/Logic Description

5-41

For DUART3.

Address 10007D - Start counter/timer

Address 10007F - Stop counter/timer

5.6

Ethernet interface

Interfacing the DECrouter 200 to the Ethernet is handled with two chips:
e

Local Area Network Controller for Ethernet (LANCE)

Serial Interface Adapter (SIA)

The chip set converts Manchester-encoded serial data to 16-bit parallel data at 10 Mbps.
The following sections summarize the signals and protocol supported by the LANCE and the SIA,
inciuding internal register formats and functions.

5.6.1

Serial Interface Adapter (SIA)

Figure 5-10 is a block diagram of the SIA, which shows the interface between the logic signals of

the LANCE and the differential signals of the Ethernet transceiver.

Sla

A _D_H o——

IVE
RCLK_ M <— RECE
DECODER |

RYX_DATA__H.L

ISION
CLSN_H @—— COLL
CETECTOR

COLL_HL

RENA_ H o

LAN_TX_ D

H —ef

RANSMIT

uan_ena_w —! Euconen

ETHERNET

XCVR

T DAT
ATA_H.L

TOLK __H o

2004H2

+ 12V REY
LrG 0B

Pigure 5-10:

542

SiA Connection to an Ethernet Transcelver

DECrouter 200 Technical Manual

e
00
00 G
e
OB 2w 2

the tnterface cable.

Table 5-21 shows the differential signals passed between the SIA and the Ethernet transceiver on

Table 5-21:

SIA end Ethernet Transcelver interface Signals

Signai Name

Description

Power

The power pair supplies regulated 12 Vdc power to the transceiver.

(+ 12V, RET)

Transmit Data

{FMTEXDATAH L)

Fa
1341

The transmit data pair carries 2 10-MHz Manchester-encoded differential signal from the SIA ransmit encoder to the Ethernet transceiver
cable driver.

Receive Data

(PIMRX DATAH.L)

The receive data pair carries 2 1 0-MiHz Manchester-encoded differential signal from the Ethernet transceiver cable receive to the SIA
receiver decoder.

The collision pair carries a 10-MHz collision comparator in the
Ethernet transceiver 1o the SI1A collision detector. This occurs on a col-

Collision
(PJM COLL H.L)

lision or on completion of 2 normal transmission, 2 heartbeat check.
Table 5-22 shows the logic interface signals between the LANCE and the SIA.

Table 5-22:

LANCE and SIA Interface Signals

Signal Name

Description

LANCE Recedve Signals

Collision

Asserted by the SIA to indicate a collision on the Ethernet.

(PIM CLSN H)
Receive Enable

Asserted by the SIA to indicate 2 valid signal on the Ethernet The SIA

(PIMRENA H)

receiver/Manchester decoder synchronizes and produces the RCLK
and RX D signals.

Receive Clock

A 10-MHz clock produced by the SIA. the synchronizing clock for the

(PJM RCLK H»

LANCE serial data receiver.

Receive Data

A serial data strezm produced by the SIA. which is asserted to the

PIMRXDH)

LANCE serial data receiver. where it is clocked by RCLK.

LANCF Transmit Signais
Transmit Clock

A 10-MHz clock from the SIA, which is the main clock for the LANCE

(PIMTCLK H)

microprocessor and the synchronizing clock for the LANCE serial data
iransmiatier.

Transmit Enable

Asserted by the LANCE to enable the SIA transmitter/driver to the

(PIKLANTXDH)

Ethernet transceiver

Transmit Data

The serial transmit data stream produced by the LANCE. which is

(PIKLANTXDH)

asserted to the Manchester data encoder in the SIA. where the data is
encoded and sent to the Ethernet transceiver.

Functional/Logic Description

A 20-MEHz crystal osciliator provides the SIA main timing reference. The timing reference is divided
by two, producing a 10-MHz clock as a time base for the LANCE internal state machine and serial
data transmitter. The 20-MHz and the 10-MHz clocks both drive the Manchester data encoder to
produce the transmissions in the encoded data stream.

5.6.2

Local Area Network Controlier for Ethernet (LANCE)

Table 5-23 shows the LANCE data/address bus operating signals. Three-state signals are normally
disabled, in high-impedance state.

Table 5-23:

LANCE Operating end Data/Address Bus Signals

Signal Name

Description

Data/Addross Bus Signals

Address Bus

The LANCE uses 16 of the 23 three-state address bus lines to access

(BUS<AI16:A01>H)

program RAM as bus master. These are drive-only lines for the LA 'CE.
The LANCE asserts BALE during the address cycle of 2 DMA transfer.

The LANCE forms 2 bus address by opening the address latch. enabling
the three-state outputs, and asserting 2 memory address on BUS A16
and on the data bus The LANCE then closes the laich, ending the
address cycle and leaving the address asserted on BUIS

<A16:A01 >H.

Data Bus

The 16-bit bidirectional three-state data bus is the data path for DMA

(BUSDAL<15:00>H)

data transfers by the LANCE, as bus master, or for CPU-initiated register transfers with the LANCE, as 2 bus slave. As the bus master on a

DMA cycle. the LANCE first asserts an address on these lines during the
address crle, and loads it 10 the address latch. The LANCE then uses
the lines tor the transfer of data on the data cycle
Bus Arbitration Signals

Buffered LANCE Hoid

Asserted by the LANCE when requesting access to the data/address

(PJK BLANHLD L)

bus

BLANHLD initially asserts a bus requesi io the CPL but is held

asseried for the transaction

When negated. LANCE terminates the

DMA cycle, releasing the bus
Bus Grant Acknowledge

Asserted by the bus arbitrator in response 10 2 bus grant from the CPU

(PID BGACK [
LANHLD Acknowledge

Grants bus access to the LANCE for @ DMA transfer. LHLDA enables

(FLLHLDA H.L)

the three-state outputs of the address latch, 2nd asserts LANRDY tothe

LANCE to indicate that program RAM is ready to perform the transfer.
Asyncbronous Bus Control Sigr.als

LANCE Enable

Asserted by the CPU to select the LANCE for a register transfer.

(PJC ENB LANCEL)

Buffered Address Latch Enable

Asserted by the LANCE on the address cycle of 2 DMA transfer. BALE

PIK BALE H)

opens ihe address iatch to receive bits < 15:01> of the memory

address asserted BUS DAL
< 15:01 >

When negated. BALE closes the

\atch that holds the address asserted on BUS <A15:A01 >
(continued on next page)

5-44

DECrouter 200 Technical Manual

Taible
5-23 (cont.):

LANCE Operating end Date/Address
Bus Signals
Description

Asynchbronous
Bus Contvol Signals
Da1a Serobe

Bus Master: Asserted by the LANCE on the data cycle of 2 CPU transfer.

(FIKE BDAS L)

Write data asserted by the LANCE is stable on the high to low transition of BDAS. The LANCE clocks read data on the low-to-high transition of BDAS.
Bus Slave: Received from the CPU on the data cycle of a2 CPU transfer,
BDAS selects the LANCE register address port or register data port for
the transfer, depending on the state of address bit BUS <01>:
BUS <A01> = O Register
data port

BUS <A01
> = O Register address port
LANCE Ready

Bus Master: Asseried by LHLDA on 2 DMA cycle, LANRDY indicates to

(PJK LANRDY L)

the LANCE that program RAM is ready to transfer data.
Bus Slave: Asserted by the LANCE on 2 DMA cycle, LANRDY indicates

that the LANCE has assented read data on the data bus, or has clocked
write data from the data bus.
Write

Defines the bus operation as 2 read or write transfer with respect to

(BUSWRTL)

the bus master:

Write = Asserted low

Read = Asserted high

As bus master, the LANCE drives this signal on a DMA transfer. As bus
slave, LANCE receives the signal on 2 CPU transfer with a LANCE register.

Upperbyie/Lowerbyte

As bus master, the LANCE asserts these signals on DMA transfer to

Data Steobe

specify the valid byte(s) for a read or a write transfer:

(BUSUDS L/BUSLDSL)

Valid Data is on BUS BUS BUS DAL BUS DAL UDS LDS <15:08>
<07:00>

00 NoNoO 1 NoYes
10Yes
No

11Yes Yes

(0 = negated. | = asserted)
As bus slave, the LANCE ignores these signals and assumes word trans-

fers.

Thesc are wire-OR signais and are driven by the LANCE and the CPU at
different times. The signals are buffered in the CPU logic, providing
the following outputs:

(continued on next page)

Functional/Logic Description

5-45

Teble 5-23 (cont.):

LAKCE Cpersting end Deta/Address Bus Signals

8ipnal Name
input Bufjered Output

Description
BUSWRTLPJABWRTH.L
BUSUDSLPJABUDSH,L

BUSLDSLPJABLDSH.L

LANCE Interrupt
(PJK LANINT L)

Asserted to IPLS of the priority encoder to request a program interrupt for any six LANCE status flags. Signal is cleared by the interrupt
service routine.

Indtialize Signals

Reser

A low signal on the reset input halts the LANCE, clears its logic, and
LANCE enters an idle state.

Power-up (P}) PUP L) from the power-up logic.

LANCE initialize (PJH LINIT L) under program control from
DUART 0.

5.6.3

Ethernet Interface Features

The LANCE operates at 10 MHz and performs the data-link-level Ethernet protocol. LANCE features
include 2 storage data FIFO buffer (SILO) that allows back-to-back transfers of up to eight words
with program RAM on a single DMA cycle.

After the CPU loac's the LANCE control and status registers {CSRs). the LANCE performs 2 DMA
break to program RAM to retrieve the initialize block with the LANCE operating parameters. In

operation, the LANCE rakes the receive or transmit descriptor rings. The LANCE descriptor rings
contain the memory data buffer parameters for transfers between the Ethernet and program RAM
through the LANCE

5.6.3.17 DMA Transfers with Program RAM — The LANCE and the CPU are the only devices
that gain access to and that usc the data/address bus as 2 bus master. The LANCE accesses the bus
through bus arbitration logic. and performs a direct memory access (DMA) transfer with program
RAM.

Bus Arbitration Cycle - The LANCE first arbitrates and accesses the data bus as follows.
1.

The LANCE asserts LANCE hold (LAN_HLD__L)to the bus arbitrator, which asserts bus request
(BR__L)to the CPU.

2.
3.

After releasing the bus, the CPU returns bus grant (BG__L) to the arbitrator.
When address strobe (BASTRB__L) is deasserted by the CPU, the arbitrator returns bus grant

acknowledge (BGACK__L) to the CPU, which negates bus grant (BG_L).

The arbitrator asserts LANCE hold acknowledge (LAN_HLD__ACK__L) to the LANCE and
negates bus request (BR__L) to the CPU.

5. With the bus cvcle completed. the LANCE negates LAN_DHLD__L and BGACK__L. which
releases the bus.

5-46

DECrouter 200 Technical Manua

ddreas Cycie - With bus control, the LANCE initiates selection
of a program

RAM location as fol-

lows:

LANCE enables three-state data control outputs — WRT__L, UDS__L, and LDS__L — with the
correct states for the transfer.

The LANCE enables three-state outputs to the data bus and enables the three-state outputs of its
address latch to the address bus.

3. The LANCE asserts a memory address on the data bus and on three-state address bus bit
< A16> and opens the address latch by asserting address latch enable (ALE__H).

Deata Cyele ~ The foliowing events transfer data with the selected program RAM location:
1.

The LANCE defines the data cycle by asserting buffered daia strobe (DAS_L). To write, the
LANCE enabiles its three-state outpuis and asserts data on the data bus.

The LANCE negates buffered data strobe (DAS__L). To read. LANCE also clocks data from the

data bus.
3.

The LANCE disables all three-state outputs and puts the signals in high-impedance (high-Z)

state.

LANCE negates buffered LANCE hold (LAN__HLD__L) to the bus arbitrator, which negates bus
grant acknowledge (BGACK__L)and LANCE hold acknowledge (LAN_HLD__ACK__L). terminating the transaction.

5.6.4

Ethernet Operating Modes

The LANCE provides three major operating modes on the Ethernet:

Transmit Mode - In transmit mode. the LANCE initiates 2 DMA cycle that acquires a transmit
descriptor ring from memory Further DMA cycles acquire data from a transmit buffer in memory
and the LANCE shifts the data out io the Ethernet system in serial data frame format.

The LANCE prefaces each data frame with a preamble pattern of binary data, allowing the receive
circuits o settle and the Manchester encoders to synchronize. The LANCE calculates 4 32-bit cyclic
redundancy check (CRC) on the source address and destination address fields, and the type and

daia fields. The LANCE appends the final CRC value to the end of the data frame. On multipie datatransmissions. the preamble provides an interframe gap of 9.6 microseconds after the CRC.

On data collision. the LANCE increases its defer time according to an exponential binary backoff
algoritbm contained in its internal microprocessor protocol.

Recelve Mode ~ When a carrier is on the Ethernet cable, the preamble allows the SIA receiver circuits to settle. The Manchester decoder synchronizes and produces a separate clock and separate

data pulses from the encoded signal carrying the incoming data frame.

Functional/Logic Description

5-47

The LANCE calculates the following:

The CRC on the received source address and destination address fields

The data type and data fields

The received CRC value

When a czalculation produces 2 1, an error bit is set in the LANCE, generating an interrupt to the
CPU.

Recelved Address Modes ~ Each of the following modes compares the received destination
address with a pre-selected value, and determines whether the LANCE should accept or should
reject the incoming data frame:
1.

Physical address moGe - The Jata frame is accepted when the destination address matches
the router Ethernet node address.

Broadcast address mode - A destination address of all 1s specifies a2 broadcast address, and
the data frame is always accepted.

Logical address mode - Accepts all data frames addressed to one type of device or to a set of
devices. Addresses are selected using a logical address filter.

§.6.5

Reglster Address and Data Ports

The CPU selects the LANCE from the address bus. Address bit < A00> must be set to select the

lower byte for a word transfer. As a bus slave, the LANCE is only zccessed on word boundaries.
BUS < AO01 > selects either the register address port (RAP; or the register data port (RDP) for a read
or a write transfer as follows:

Address 100080 ~ Selects the RDP
Address 100082 ~ Selects the RAP
Figure 5-11 shows the register address port and control/siatus register bit settings. CSRO has bit set-

tings that allow access to it any time during normal operation. All other CSRs are read/write registers that are only accessible when the STOP bit is set in CSRO.

5-48

DECrouter
200 Technical Mammsal

Iy me
CONTROL SEQUENCE REGISTER 0

CONTROL SEQUENCE REGISTER 1

o)) L

IADR IADR< 1501 >
CONTROL SEQUENCE REGISTER 2

CONTROL SEQUENCE REGISTER 3

CSR3

08 07

LRG-0373

Flgure 5-11:
5.6.6

LANCE RAP snd CSR Bit Settings

Reglster Address Port (RAP) and Latch

When BUS<AO1> is set, the CPU loads the RAP. When BUS< A0l > is cleared. it latches and

asserts bits RAP<01:00> that select one of four CSRs

The RAP is a read/write register that selects a CSR to access through the RDP. RAP is cieared by
STOP or by bus RESET.

5.6.7

Control/Status Register 0 (CSRO)

When address bit < A01> is cleared, the CPU loads the CSR selected by the RAP register through

the register data port. All subsequent transfers take place with the selected CSR until the RAP value

is changed.
The function of each bit in CSRO, described in the following text. is true when the bit is set. The bits
are controlled by the operating program according to these access definitions.
®

Read/¥W'rite ~ The bit can be read. can be set, or can be cleared by writing to it.

Read Only - The bit can only be read.

Rea /Set - The bit is read-only but can ve set by writing a 1 to it.

Functional/Logic Description

5-49

Read/Clear - The bit is read-only but can be cleared by writing a 1 to it.

Write Only - This is 2 write-only bit and 2 LANCE function is done by writinga 1 to it.

All register bits are cleared by setting the STOP bit or by asserting the reset input except for bit
< 02>, which is the STOP bit in CSR0. CSR1, CSR2, and CSR3 can only be read to when the STOP

bit in CSRO is set. These CSRs must 2lso be initialized after a reset or stop operation.

Table 524 identifies. gives the mnemonic and bit-types and describes the function of all the bits in
CSRO.

Table 5-24:

Control and Status Register 0 (CSRO)

Name

Description

Bit Type

<15>

Error
(ERR)

Asserts an OR summ.ry of error bits < 14:11>
Read as 0 when bits are clear.

Read-Only

<14>

BABL

Indicates 2 transmit error. The transmitter is enabled

Read/Clear

longer than necessary to send the 1529-byte packet
maximum

<i3>

CERR

Indicates a collision error. The collision test signal,

Read/Clear

the heartbeat. was not acquired within 2
microseconds of 2 norma! data transmission

<i2>

MISS

Indicates a missed data packet The receiver lost
a data packet due to lack of receive buffer

Read/Clear

acquisition: SILO is overflowed

<il>

MERK

Indicates 2 memory error. LANCE did not
receive LANRDY within 25 6 microseconds

Read/Clear

of address assertion on the dat bus.

<i0>

RINT

Indicates a receiver interrupt. The bit is set
after the LANCE updates an entry in the receive

Read/Clear

descriptor ring

<09>

TINT

Indicates 2 rransmit interrupt. The bit is set

after the LANCE updates an entry in the transmit
descriptor ring.

<08>

IDON

Indicates initialize done The LANCE has read the

Read/Clear

initialization block and has stored the parameters

<07 >

INTR

Identifies an interrupt condition for BABL, MISS.

Read-Only

MERR. RINT, TINT, or IDON

<06>

INEA

<05>

RXON

Enables an interrupt when <07 > is set

Read/Write

Indicates that the receiver is enabled. The bit is set

Read-Only

when STRT is active and DRX is 0 in the mode register

(continued on next page)

5-50

DECrouter 200 Technical Manual

Table 5-24 (cont.):
8r

Name

<04 >

TXON

Control and Status Reglater 0 (CER0)
Description

B8t Type

Indicates the transmitter is enabled. The bit is set

Read-Only

when STRT is enabled, DTX is 0 in the mode register

in the initializauon block, and the INIT bit is set in
CSRoO.

<03>

TOMD

Indicates transmit demand When set, the

Read-Only

LANCE acquires the transm.: descriptor ring
without waiting for 2 politime interval to elapse.
<02>

STOP

STOP bit for the LANCE. When set, all external

Read/Set

activity is disabled and internal logic is cleared.
<01 >

STRT

Start bit Start enables the LANCE 1o send and

Read/Set

receive data packets. to perform direct memory

access. and to manage the buffer
<Q0>

INIT

Initialize bit Setring this bit enables LANCE

Read/Set

initialization. and access to the LANCE initializz block

5.6.6

CSR1< 15:C1 > stores the lower bits of the first initialize block address. Table 5-25 identifies. gives

the mnemonic and describes the functions of all bits in CSR1

|
!

Control and Status Register 1 (CSR1)

Tabie 5-25:

Control and Status Register 1 (CSR1)

Bits

Name/Description

<1501>

IADR. The low order 16 bits of the address of the first word. lowest address. in the initialize
block

<00>

5.86.9

MBZ This bit must be zero and is not used

Control and Status Register 2 (CSR2)

CSR2 < 07:00 > stores the upper bits of the first initialize block address. Table 5-26 identifies. gives
the mnemonic and describes the functions of all bits in CSR2

Table 5-26:

Control and Status Register 2 (CSR2)

e ]

Name/Description

<15:08>

Reserved

<0TM00>

IADR The high order 8 bits of the address of the first word. lowest address. in the initialize
block

é
0
e

Functional/logic Description

5-51

‘

5.6.10 Control and Status Register 3 (CSR3)
CSR3 controls the byte swap functions and pin definitions of the bus master interface. Table 5-27
identifies, gives the mnemonic and describes the functions of all bits in CSR3.

Table 5-27:

Control and Status Register 3 (CSR3)

Bite

Noms

Deacription

<15:03>

Reserved.

<02>

BWSP

Byte Swap allows the LANCE to start on an odd byte address. Data bits
< 15:01 > are swapped with <07:00> on 2 DMA transfer.

<0t>

ACON

Address Line Enable defines the asserted state of the LANCE from the STOP
bit as.

ACON = 0 ALE is asserted high
ACON = 1 ALE is asscrted low

<00>

BCON

Byte Control redefines the byte mask and holds 1/0 pins as:
Pin 17 Pin 16 Pin 15
BCON = O LANHLD BUS UDS BUS LDS
BCON = 1 BUSACK BYTE BUSRQ

5.6.11

Buffer Management Protocol

The router operating software maintains data buffer areas in memory for the temporary storage of
Ethernet data from the LANCE. The software aiso contains tables in memory that LANCE acquires
under DMA. LANCE uses these tables to access the data buffers under DMA transfers.
The LANCE buffer management protocol uses several table structures to handle the data table and
the memory buffers, including:

Data buffers - The receive and transmit data buffers reside in rontiguous memory space and
can start on arbitrary byte boundaries.

initialize biock - The initialize block is 2 table in memory that stores the LANCE operating

mode, the addressing parameters, and the pointers to the base addresses for the receive and
transmit descriptor rings The initialize block starts on a two-byte boundary.

Desecriptor rings - The receive and transmit descriptor rings are tables in memory that LANCE
uses to access the receive and transmit data buffers in memory. Each descriptor ring has at least
one entry and starts on a four-word boundary.

The descriptor rings provide an information path between thie LANCE and the operating program for filling and emptying a data buffer in memory.

fMessage descriptors - Each descriptor ring entry has four words called message descriptors.
Message descriptors supply the following information to access one buffer:
-~

Point to the base address of the buffer

Specify the length of the buffer

5-52

DECrouter 200 Techinical Manual

Specify method of data frame processing

Specify LANCE action on error or on change in status

Multiple entries are required when a transfer exceeds the size of the buffer in memory. Multiple
data frame transmissions are required for transfers that exceed ihe maximum data frame iengih.
Router operations begin when the operating program sets the LANCE initialize bit (INIT
CSRO
< 00> ). The LANCE acquires the initialize block from memory, starting at the address specified in CSR1 and CSR2, and stores the information in its internal parameter registers. This enables
the LANCE to start transfer operations when the operating program asscmbles the receive and the
transmit descriptor rings in memory.

5.6.12

Initialize Block

The initialize block has 12 contiguous words in memory, starting on a two-byte boundary, as
shown in Figure 5~12.

<23:16>

TLEN-TDRA

IADR<23:00> +26

<15:00>

TDRA

IADR < 23:00> +24

<23:16>

RLEN-RDRA

IADR<23:00> +22

<15:00>

RDRA

{ADR < 232:00> +20

LADRF

<B63:48>

IADR <23:00> + 16

LADRF

<47:32> | IADR<23:00> +14

LADRF

<31:16> § 1ADR<23:.00> + 12

LADRF

<15:00> | I1ADR<23:.0> +10

<47:32>

PADR

JADR <23.00> + 06

<31:16>

RLEN PADR

IADR<23:00> + 04

PADR
< 15:00
>

IADR<23:00> + 02

MODE

1ADR <23:00> + 00

LKG-0570

Flgure 5-12:

LANCE Initialize Block Format

Functional/Logic Description

5-53

The router software assembles the initialize block before initializing the LANCE. When initialized,
the LANCE performs a DMA cycle that acquires the {~llowing operating parameters from the initialize block and stores the parameters in registers.

lword -

Mode(MODE)

3words -

Physical Address (PADR)

4words ~

Logical Address Filter (LADRF)

2words -~

Receive Descriptor Ring Address (RDRA)

2words -

Transmit Descriptor Ring Address (TDRA)

Station Addressing - The LANCE uses the Physical Address (PADR) Register and Logical Address
Filter (LADRF) register to determine whether to accept or to reject incoming data frames.

Physical address - When the first bit of an incoming address is 0, the incoming address is physical. If the address maiches the contents of the PADR register, the data frame is accepted.

Broadcast address - The first bit must be 1 for the broadcast address decoder or the logical

address filter to be enabled. A destination address with all 1s is the broadcast and the data frame
is always accepted.
®

[Logical address - For any other address where the first bit is 1, data frames are accepted according to the LADRF register. The operating software handles final filtering.

VWhen all 48 bits of an incoming address pass through the CRC circuitry, tl. . Lix high-order bits
of the 32-bit CRC are clocked to a register that selects one of 64 bit positions in the LADRF register. When the selected filter bit is 2 1, the data frame is accepted.

When the LADREF is ali Os. ail incoming logical addresses are rejected except for the broadcast

address.

Minimum Data Frame Length - Incoming data messages must be at least 64 bytes long to be valid.
Messages shorter than 64 bytes are not updated in the LANCE receive message descriptor pointing

to the buffer. The contents are saved for the next data frame.

$.6.13

Mode Register (MODE)

MODE
< 15:00 > bits are cleared during normal operation. These bits allow the LANCE operating
parameters to change for maintenance functions, as shown in Table 5-28.

5-54

DECrouter 200 Technical Manual

Tabile 5-28: (Mode Reglster
Bit Settings
Bits

Hame

Desgcription

<i5>

Promiscuous

When this bit is set, the LANCE accepts all incoming data frames

PROM

with any destination address.

<14:07>

Reserved.

<06>

Internal Loopback

This is valid only when bit <02>LOOP is set; INTL selects the

INTL

LANCE loopback path:
INTL = 0 External loopback
INTL = 1 Internal loopback

With INTL set, the data frame size is limited by the 48-byte SILO.

The data is 32 bytes long with CRC disabled, and 36 bytes long
with CRC enabled.
<08 >

Disable Retrv

When set, the LANCE tries only one transmission. A collision on

DRTY

a first try. sets the retry error bit, RTRY < 10>, in transmit message descriptor 3, TMD3

<04>

Force Collision

This is valid only in internal loopback mode, and is set for testing

FCOL

the collision logic. The LANCE makes 16 transmission attempts

before setting the retry error bit, RTRY < 10> in TDM3.
<03>

Disable Transmit CRC

When clear, the transmitier generates 2 CRC and appends the

DTCR

CRC o the data frame. On a loopback test with DTCR clear. the
receiver cannot check the CRC. The CRC is written to memory

and checked by software.

When set. the CRC logic is used by the receiver. On 2 loopback
test with DTCR set. the software must generate and append the
CRC. The receiver CRC logic checks and reports any receive
errors.

<02>

Loopback

LOoOP

Sets the LANCE operation to full-duplex mode for testing. Due to
the 64-byte minimum on Ethernet data frames, the minimum
data frame filter is disabled.

The LANCE holds until the full message is in SILO before data
transmission. Incoming data follows outgoing data and is passed
to memory when the transmission is complete.
<01>

Disable transmitter

DTX

When set. this disables LANCE access 1o the transmit descripior

ring The CSRObit < 10> TXON is disabled and transmits are not
attempted.

<00>

Disable Receiver

DRX

When set. this disables LANCE access to the receive descriptor

ring. The CSRO bit <05>RXON is disabled and all incoming
daua frames are rejected

Functional/Logic Description

5-55

6.6.14

The PADR
< 47:00> bits store the router Ethernet node address that was generated by the PA
PROM. PADR <00 > must be 0.

6.6.14.1

Logicel Address Filter Reglster (LADRF) — LADRF<63:00> bits form a 64-bit

mask used to accept incoming logical addresses.

5.6.14.2 Recelve Descriptor Ring Address Register (RDRA) — The RDRA
< 31:00> bits are
described in Table 5-29.

Teble 5-29:

Receive Descriptor Ring Address (RDRA) Bit Settings

Blite

HKams

Deseription

<15:13>

Receive Ring Length

The three high-order bits specify the number of receive descrip-

(RLEN < 2:0>)

tor ring entries as 2 power of IWo:

<12:08>

<07:00>

RLEN Blts

biumber of

<2:0>

Entries

128

Reserved.

Receive Ring Address

Specify the receive descriptor ring base address

(RDRA< 15:03>)
<02:00>

Must be Zeros

Receive descripior rings are aligned on four-word boundaries

(MBZ)

§.6.14.3

Tranemit Descriptor Ring Address Register (TDRA) ~ The TDRA<31:00>

bits

have the functions described in Table 5-30.

5-58

DECrouter 200 Techrical Manual

ible 5-30:

Transmit Descriptor Ring Address (TORA) Bit Settings

bams

Deseription

<15:13>

Transmit
Ring Length
(TLMN<2:0>)

The three high-order bits specify the number of transmit descriptor ring entrics as a power of two:
TLEN Bits
<2:0>

Numaber of
Entrisc

b
6

32
64

128

<12:08>

Reserved.

<07:060>

Transmit Ring Address

Specify the transmit descriptor ring base address.

(RDRA<15:03>)

<02:00>

Must be Zeros

Transmit descriptor rings are aligned on four-word boundaries.

(MBZ)

5.6.15

Recelve Descriptor Ring

A receive descriptor ring has at least one entry in memory, as shown in Figure 5-13. Each entry
points to a receive data buffer and defines how data is used.

Functional/l.ogic Description

5-57

RECEIVE MESSAGE DESCRIPTOR 0

00
LADR

RECEIVE MESSAGE DESCRIPTOR 1

Cwi f ERR | FRAMOFLOE

CRC

FBUFF|

STP | ENP

HADR

RECEIVE MESSAGE DESCRIPTOR 2
5

00
BCNT

RECEIVE MESSAGE DESCRIPTOR 3
00

RESERVED

MCNT

LKG-0572

Figure 5-13:

LANCE Recelve Descriptor Ring Entry

:ch ent:
v has four words called receive message descriptors (RMDs) and is accessed on a four-

wo.
" poundary. The follow
ng four tables show: the bit settings in each descriptor.

Table §-31:

Receive Message Descriptor 0 Bit Functions

Bits

Mame

Description

<15.00>

Low Address

These bits are the low-order base address bits for the receive data buffer

LADR< 15:00>

selected by the descripior ring entry. LADR is written by the host and is

vnchanged by the LANCE

5-58

DECrouter 200 Technical Manual

Tuble 5-32;: Recelve Message Descriptor 1 Bit Functions

Bits

Reme

Description

<15>

OWN

This bit indicates ownership cf the enry:
0 = Owned
by HOST, router software

! = Owned
by LANCE

The following bits are set by LANCE and cleared by the HOST:

<14>

ERR

An OR summary of error status bits < 13:10>.

<i3>

FRAM

This indicates that the reccived data frame has a noninteger multiple of
eight bits and a CRC error.

<i2>

OFLO

Indicates that all or pant of a received data packet was lost when LANCE
could not access the buffer and store the data before the SILO overflowed.

<il>

CRC

<10>

BUFF

|
|

Indicates the LANCE has used all allocated buffers or did not acquire the

next entry status before 2 SILO overflow.
<09>

STP

This indicates that an entry has the pointer to the firs: data buffer for the

<08 >

ENP

This indicates the last buffer used by LANCE for the packet. With STP and
ENP both set in one entry. the data packet fits into onc buffer and no

indicates that 2 CRC error was detected on a data frame.

packet This is used for chaining buffers.

chaining is in effect
<0":060>

HADR

Table 5-33:

These are the 8 high-order address bits of the buffer pointed to by the

descriptor This is written by the HOST.

Receive Message Descriptor 2 Bit Functions

Bite

Neme

Dascription

<15:12>

MBO

This field is written by the HOST and is ucaffected by LANCE

<11:00>

BONT

BCNT is the length of the buffer pointed to by the descriptor expressed as

a two's complement number Field is written by the HOST and is unaffected by LANCE.

Tabie 5-34:

Receive lMessage Descriptor 3 Bit Functions

Bite

Name

Desgceription

<i812>

Reserved and read as zeros.

<11:00>

MUNT

MCNT is the length. in bytes, of the received message This is written by

the LANCE and is cleared by the HOST

Functional/Logical Description

5-59

Tranamit Deacriptor Ring

5.6.16

A wransmit descriptor ring has a minimum of one entry in memory, as shown in Figure 5-14.

TRANSMIT MESSAGE DESCRIPTOR 0
0

LADR

TRANSMIT MESSAGE DESCRIPTOR 1

OWN | ERR | RES

12
1MORE]

)

ONE | DEF | STP | ENP

HADR

TRANSMIT MESSAGE DESCRIPTOR 2

00
BCNT

TRANSMIT MESSAGE DESCRIPTOR 3

BUFF [ UFLO]

RES

JLCOL

jLCAR | RTBY

TOR

LxG-057¢

Figure 5-14:

LANCE Transmit Descriptor Ring

The following four tables describe the bit settings in the four transmit descriptor rings.

Table 5-35:

Transmit Message Descriptor 0 Bit Functions

Bits

Neme

-Description

<15:00>

LADR<I15:00>

These bits are the low-order base address bits for the transmit data buffer
selected by the descriptor ring entry. LADR is written by the host and is
unchanged by the LANCE

DECrouter 200 Technical Manual

Table 5-36:

Transmit Message Descriptor 1 Bit Functions

Blits

Hame

Deecription

<15>

OWN

This bit indicates ownership of the entry:
0 = Owned by HOST, router sofiware
1 = Owned by LANCE

The HOST sets the OWN bit after filling the transmit data buffer. The
LANCE clears the buffer after transmitting the packet.
The following bits arc sct by LANCE and cleared by the HOST.

<14>

ERR

An OR summary of LCOL, LCAR, UFLO, or RTRY. ERR is set by LANCE
and cleared by the HOST.

<i3>

Reserved, LANCE writes this bit as a zero.

<12>

This indicates that more than one retry was nceded to send 2 packet.

<il>

ONE

This indicates that a2 transmission was completed on one try.

<10>

DEF

This indicates that LANCE has deferred a transmission due to Ethernet

trafiic.
<09>

STP

This indicates that an entry has the pointer to the first data buffer for the

packet. This is used for chaining buffers.
< 08>

ENP

This indicates the last buffer used by LANCE for the packer. With STP and

ENP both set in one entry, the data packet fits into one buffer and no
chaining is in effect.
<07:00>

HADR

These are the 8 high-order address bits of the buffer pointed to by the

descriptor. This is written by the HOST.

Teble 5-37:

Tranemit Message Descriptor 2 Bit Functions

Bits

Name

Degeription

<15:12>

MTMMBO

This field is writien by the HOST and is unaffected by LANCE

<11:00>

BCNT

BCNT is the length of the buffer pointed to by the descriptor ¢xpressed as

a two's complement number. Field is written by the HOST and is unaffected by LANCE.

Functional/Logical Description

5-61

Table 5-38:

<15>

Transmit Message Descriptor 3 Bit Functions
Wame

Description

BUFF

This bt is set by LANCE during transmission when the ENF TMD2
bit< 08> is not set for the buffer and LANCE does not use the next
bhuffer

<l4>

UFLO

This indicates that daia was lost due to lack of data from memory. This
indicates that SILO has emptied before the end of a packet was received

<ls>

Reserved

LANCE writes this as zero.

<izZ>

Late Collision

This indicates 2 collision after the allowed slot time.

<li>

LCAR

This indic21es that the carrier input negated during LANCE initialization
The chip will not retry on loss of carrier

<10>

RTRY

This indicates that LANCE has tried and failed 16 times to transmn a

packet When RTRY is a 1. in the mode register. retry sets after one failure

<09-00>

TDR

This indicates the state of an internal LANCE counier from the start of a
packet transmussion to a collision detection.

The state of the counter is useful for determining the approximate distance to a coaxial cable fault

5-82

DECrouter 200 Technical Manual

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Hardware Description

6.1

General

The DECrouter 2¢- svstem is a stand-alone communications device. The router can be wallmounted or table-.op mounted. Table-top mounting requires a minimum <] 6 inches clearance on
all sides for ventilation, and ample clearance in the back for cable access and servicing.
For detailed instructions on installation and site preparation. see the DECrouter 2(X) Hardware
Installation/Ouner’s Guide.

6.2

Port Devices Supported By DECrouter 200

This scction lists port devices supported by the DECrouter 200 system. For the latest listing ~f supported devices. see the DECrouter 200 Software Product Description that applies to your vperating system.

Devices supported by the DECrouter 200 system inciude

Personal Computers — Digital and non-Digital personal computers running DECnet Phase IV,
including:
Professional 300 series

Rainbow 100 series

Non-Digital personal computers. including:
-

IBMPC

IBM PC/XT

1BM Personal Computer AT

20oan

6-1

Modems — Full-duplex modem control and all asynchronous, full-duplex Digital modems in

both dial-in and dial-out modes, including:
-

DFO02 (300 bps)

DF03 (300/1200 bps)

DF112(300/1200
bps)

DF124 (1200/2400 bps)

DF224 (300/600/1200/2400 bps)

Non-Digital modems supported include modems compatible with BELL 103} and BELL 212A,
and modems that conform to CCITT V.21, V.21 bis, V.22 and V.22 bis.

6.2.1

Ordering Informsation

Table 6~1 lists order codes for DECrouter 200 related hardware products. See your Digital sales
representative to purchase equipment

For a listing of software options, see the DECrouter 200 Software Product Description that applies
10 your operating system.

Table 6-1:

DECrouter
200 Hardware Units

Description

Order Code

120 Vac (includes DSRVC-K
A country kit)

DSRVC-AA

240 Vac

DSRVC-AB

6.2.2

DECrouter 200 Country Kits

Each of the following kits includes a power cord. the documentation, an Ethernet loopback connector, and 2 rack mount kit Table 6-2 shows the order codes for DECrouter 200 country kits

Table 6-2:

DECrouter 200 Country Kits

Country

Order Code

Australia

DSRVC-KZ

Belgium

DSRCV-LA

Canada (English and French)

DSRVC-KA

Denmark

DSRVC-KD

Finland

DSRVC-LA

France

DSRVC-LA

Germany

DSRVC-KG
(continued on next page)

6-2

DECrouter 200 Technical Manual

Table -2 (cont.):

DECrouter 200 Country Kite
Ovder Code
DSRVC-LA
DSRVC-KI

DSRVC-L)

israel

DSRVC-KT

Japan

DSRVC-K)

New Zealand

DSRVC-KZ

NoTway

DSRVC-1A

Spain

DSRVC-LA

Sweden

DSRVC-LA

Switzerland (French and German)

DSRVC-LB

United Kingdom

DSRVC-KE

United States

DSRVC-KA

6.3

DECrouter 200 Accessories

Table 6-3 gives the router accessorirs by order numbers.

Teble 6-3:

DECrouter 200 Accessories

Deacription

Order code

Ethernet turnaround connector — For testing

H4080

transceiver and transceiver cable

Ethernct loopback connector — For loopback

12-22196-901

testing the DECrouter 200 Ethernet port and

transceiver cable
Port loopback connector — For loopback

12-15336-08

testing the DECrouter 200 device ports

Etherjack kit — For covering and securing

DEXJK

transceiver cable connections
¥ all/partition mounting bracket kit — For mounting

HO039

the DECrouter 200 to walls or office partitions
Rack mount kit — For mounting the DECrouter 200

HO41-AA

in standard rack cabinets

Hardware Description

6-3

Transcelver Cables

6.4

The BNE3x-xx transceiver cable is available in FEP versions, for use in return 2ir conduits, and in
PVC versions, for use in nonenvironmental airspaces. The large diameter of this cable results in 2
lower signal loss per length of cable than the smaller diameter office transceiver cable. Two styles
of connectors are available: a straight connector and a right-angle connector.
The following cables are available:

BNE3A-xx PVC, straight-connector transceiver cable

BNE3B-xx PVC, right-angle connector transceiver cable

BNE3C-xx FEP, straight-connector transceiver cable

BNE3D-xx FEP, right-angle connector transceiver cable

BNE3H-xx PVC, straight-connector, 802.3-compliant transceiver cable

BNE3K-xx PVC, right-angle connector, 802.3-compliant transceiver cable

°©

BNE3L-xx FEP, straight-connector, 802.3-compliant transceiver cable

BNE3M-xx FEP, right-angle connector, 802.3-compliant transceiver cable

All these cables are available in lengths of 5 meters (16.41.

), 10 meters (32.8 feet), 20 meters (65.6

feet), and 40 meters (131.2 feet).
The BNE4x-xx office transceiver cable is available in PVC versions for use in nonenvironmental air-

spaces. The smaller diameter of this cable makes it suitable for use in office environments. The
smaller diameter of this cable results in 2 cable signal loss that is four times greater than that of
BNE3x-xx transceiver cables. Two styles of connectors are available: a straight connector and a
right-angle connector.
The following cables are available:

BNE4A-xx PVC, straight-connector transceiver cable

BNE4B-xx PVC, right-angle connector transceiver cable

BNE4C-xx PVC. straight-connector. 802. 3-compliant transceiver cable

BNE4D-xx PVC. right-angie connector, 802.3-compliant transceiver cable

The preceding cables are available in lengths of 2 meters (6.6 feet) and 5 meters (16.4 feet).

DECrouter 200 Technical Manual

6.5

Device Cables

The following device cables are available:

Null modem cabie, round, 10-wire, fully shielded, EIA RS-232-C/CCITT V.28, female-to-female
molded connectors:

Length

Order Code

02 fi (0.6 m)

BC17D-02

10 ft (3.0 m)

BC17D-10

25ft(7.6m)

BC17D-25

50£(15.2m)

BC17D-50

£t (30.5 m)
100

BC17D-A0

Null modem cable, round. 6-wire, fully shielded, EIA RS-232-C/CCITT V.28, female-to-female
molded connectors:

Length

Order Code

10ft(3.0m)

BC22D-10

25 ft (7.6 m)

BC22D-25

35 ft(10.7 m)

BC22D-35

50 ft (15.2 m)

BC22D-50

75ft(22.9m)

BC22D-75

100 ft (30.5 m)

BC22D-A0

150 ft (45.7 m)

BC22D-A5

200ft (61.0m)

BC22D-B0

250t (76.2 m)

BC22D-B5S

Modem cable. round, 16-wire, fully shielded. EIA R$~232-C/CCITT V.28, male-to-female molded
connectors:

’.

Length

Order Code

10ft (3.0 m)

BC22E-10

25ft(7.6m)

BC22E-25

35£t(10.7 m)

BC22E-35

50ft(15.2m)

BC22E-50

75t (22.9m)

BC22E-75

100 ft (30.5 m)

BC22E-A0

150 ft (45.7 m)

BC22E-AS

200 £t (61.0m)

BC22E-BO

250ft(76.2m)

BC22E-B5

Hardware Description

6-5

Full modem cable, round, 25-wire, fully shielded, EIA RS-232-C/CCITT V.28, male-to-female

molded connectors:

Length

Order Code

10 ft (3.0 m)

BC22F-10

25 fi (7.6 m)

BC22F-25

35 £¢(10.7 m)

BC22F-35

50 ft (15.2 m)

BC22F-50

75 ft (22.9 m)

BC22F-75

100 £t (30.5 m)

BC22F-A0

150 ft (45.7 m)

BC22F-AS

200 ft (61.0 m)

BC22F-B0

250 ft (76.2 m)

BC22F-B5

6.6

DECrouter 200 Specifications

This section lists the DECrouter 200 specifications.

6.6.1

Power

Table 6—4 shows the power requirements for the DECrouter 200 system.

Table 6-4:

DECroutsr 200 Power Ratings

Requirements

DSRVC-AA

DSRVC-AB

Factorv-set

100 Vac to 120 Vac

220 Vac to 240 Vac

nominal voltage

3-wire. single phase

IN+PE

Frequency

4" Hzto 63 Hz

47 Hzto 63 Hz

Line current

1.0A

05A

Power

75 watts

6.6.2

Environment

The following three sections provide environmental specifications for the router.
§.6.2.1

Temperature —

Operating:5°Ct050° C(41°Fto 122°F)

Nonoperating: -40° C to 66° C (-40° Fto 151° F)
Maximum temperature change per hour: 20° C(36° F)

Rapid temperature changes can affect operation. A router should not be mounted near heating or
cooling devices, large windows, or doors that open to the outside.

6-8

DECrouter 200 Technical Manual

62
6
G
ED

6.6.2.3

If the router is operating above 2.4 kilometers, the operating temperature must be decreased by
1.8°Centigrade/ 1000 meters (1 ° Fahrenheit/1000 feet).

Nonoperating: 9.1 km (30,000 ft)

Ralative Humidity — Operating: 10% to 95% (noncondensing)

Nonoperating: 95% maximum

Low humidity can cause static electricity that can affect router operation. A humidifier is suitable
to correct the dew point of an environment.

6.6.2.4

Physical Dimensions of the DECrouter 200 System —

Following are the dimensions

of the router.
Width:

49.3cm(19.4in.)

Height:

11.7cm(4.6in.)

Depth:

31.2cm(12.3in.)

Weight:

5.9kg (13.01b)

6.6.3

Speace Reguirements

Allow for 15 centimeters (6 inches) of airspace around the router air vents, and place the router at
least 45 centimeters (18 inches) above the floor. This allows adequate ventilation for cooling fans

and reduces exposure to excess dust from foot traffic.
Figure 61 shows the DECrouter 200 system dimensions.

Hardware Description

6-7

LKG-0676

Figure 6-1:

-8

Dimenslons of the DECrouter 200 System

DECrouter 200 Technical Manual

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Index

A
Address space
accessing router address space, 4-4
Asynchronous errors, 2-11
error ranges, 2-11

Asynchronous poris
transmit and receive speeds, -5

Augxiliary Control Register ACR06:04 bit settings,
5-381t065-39

Data frame, 1-10
characieristics, 1-11

destination address, 1-11
Data transfer

data transfer cycles, 5-22
Data transfers
CPU-initiated transfers, 5-21

LANCE-initiated transfers. 5-21
DECrouter 200
asynchronous DDCMP connection, -1

Bugcheck errors. 3-5
Bus control
address strobe. 5-4
asynchronous signals. 5-4
bus arbitration logic, 5-9

bus arbitration signals. 5-6
data bus

data strobe, 5-5
read write control, 5-4

C
Clocks

clock select registers, 5-32
refresh timer. 5-8
system clock logic. 5-8

Collision detection. 1-9
heartbeat, 1-10

slot time, 1-10
Comrmunications methods, 1-9
Conivol signals
halt and reset signals, 5-6
processor control, -6

Counters

counter mode, 5-41

start counter, 5-41
stop counter, 5-41

CPU
and dawa transfers, 5-21
CRC, 2-7

checked by self-test, 2-7

collision detection, 1-9
communications methods. 1-9
configuration criteria, 1-8

connecting to large DECnet systems. 1-6
conpecting to personal compiters, 1-6
Digital personal computers supported. 6~ 1

modems supported, 6-2
network access, 1-9

network access and protocol, 1-9
non-Digital personal computers supported. ¢

-1

ordering information, 6-2
port devices supported, 6-1
software options, 6-2
system clements, 1-6

DECrouter 200 country kits, 6-2 10 6-3
DECrouter 200 system, 1-1

device cables, 65 10 6-6
function logical description, 5-1
internal hardware introduction, 5~1
overview, 1-1

physical description, 6-1
specifications, 6-6 1o 6-8
altitude, 6-7

environment. 6-6
humidity, 6-7
power, 6~6
space requirements, 6-7

transceiver cables, 6-4
DECrouter 200 sysiem hardware units, 6-2
Device addressces, $-2

index-1

Direct Memory Access (DMA), 3-46

Ethernet (cont.)

transfers with Program RAM, 5-46

characteristics, 1-11

Down-line load

general description, 1-$

and router software, 3-2

imterface

image lozd, 3-2

LANCE, 1-2

load failure, 3-2

interface festures, 5-46

messages, 3-2

operating modes, 547

MOP, 3~-2

router hardware for ~onnection to, 5~42

overview, 3-1

service types, 1-2

procedure, 3-2

lozd types, 1-2

transfer of program control, 3-2

Dual Asynchronous Receiver Transmitter
see DUART

status efrors, 34

transceiver connector, 1-4

Ethemet interface

DUART, 2-10
DUARTs

DUARTO timer addresses, 5-41

chip set, 5-2
Ethernet operating modes

broadcast address mode, 5-48

DUART1 timer addresses, 54 1

logical address modce, 5-48

DUART2 timer addresses. 5-41

physical address mode, 5-48

NUART 3 timner addreyses, 542

receive made, $—47

seaeral information, $-24

received address modes. 5-48

input/output port register formats, 5-35

oscillator frequencies, 5-8

transfer mode, -4~
External hardware, 1-2, 6-1

reset signais, 5-26

AC circuit breaker, 1-4

signal descriptors. ®-24 10 5-26

AC line volizge input selector. 1-4

summary of regiszer furnictions, 5-24

AC power cord receptacle, 1-4

Dynamic RAM, 5-22

Etherjack kit. 6-3

parity, 5-22

Ethernet transceiver connector, 1-4
Ethernet turmaround connector. 6-3

LED D2

during self-test. 2-%

EEPROM, 2-11
error codes written to EEPROM. 2-11

when blinking. 2-3, 2-5

internal write process, $-23

when off, 2-2, 2-§

wkrnon, 2-§

nonvolatile memory. 5-23

LED2. -2

write inhibit, 5-23

Electrically Esasable Programmable Read Only

LED3

Memory see EEPROM

when blinking. 3-4

EPROM. 5-23

when lit. 3-4

LEDs

with ODT, §-23

Error codes. 2-10. 3-§

functions of all four 1-3

DUART errors, 2-10

loopback connector, 6-3

fatal (hard) errors, 2-§

modem connection, 5-13

general errors, 2-10

null moder

initialize, 3-5

panel clements, 1-3

connection, 5-14

LEDs. 1-3

LANCE errors. 2~-11
load failure and time-out errors. 3-§

port connections. 1-4

pass/f2il errors, 2-10

port loopback connector, 6-3

self-test. 2-10

RS-232-C drivers/receivers, 5-2
Serial Interface Adapter (S1A), 1-2

system crash error codes, 3-6

Error messages

switch 1, 1 -4

terminal interface, 5-23

nonfatal error longword, 2-4

Error modes. 2-1

fatal and nonfaral described. 2-1
Errors

asynchronous, 2-11
Etherner, 1-2

index-2

Firmware, 1-1, 1-2

EEPROM, 1-1, 23, 2~11

address allocation, 2-3

Pirmware {cont.)

nonfaeal ervor longword, 2-4
RBead Only Memory (ROM), 2-5
ROM and ODT, 4-1
self-test dispatch table, 2-5
test initiated from ROM, 2-5

)
Interrupt control (cont
RAM refresh, IPLS, 5-10
vector addresses, §-10

DUART vectors, 5-11
use timer, 5-10
general

LANCE vector, 5-11
modem control vecior, 5-11

Image file
bad image, 3-7

invalid imnage file, 3-7
Initialization
power up. 1-5

Initialize

down-line load

uransfer of program control, 3-2

error codes, 3-5

load failure, 3-5

parity error vectof, 5-11

refresh timer vector, 5-11
warmstart vector, 5-11

Interrupts, 2-7, $-5
fatal interrupts, $5-22

interrupt control signals, 5-5

Interrupt Mask Register, $-40
Interrupt Priority Levels (IPLs)

IPL7. 5-6

interrupt priority levels (IPLs), 5-5

IPL2, 5-5

roster problems. 3~-5

Interrupt Status Register (ISR), 5-39

time-out error, 3-5

sclf-test interrupts, 2-7

irmage load. 3-2

initialize sequence. 1-5

router software bugchecks, 3-6
initialize program

and down-line loading, 3-1

LANCE, 2-3

CRC calculating source address, $—48
dara buffers

and Self-test. 3-1

buffer management protocol. §-52

and up-line dump. 3-1

descriptor rings, 5-52

down-line load
image load complete, 3-2
error codes

initialize block, $-52
message descriptors, 5~52

dara transfers, 5-21

abort dump messages. 3-"

Direct Memory Access (DMA), 5-54

fatal bugcheck. 3-5

error codes, 2-11

timeout. 3-7

general infremation, 1-2

transmission failure, 3-~

Logical Address Filter Register (LADRF). 5-56

nonfatal errors, 3-4

Physical Address Register (PADR), 5-56

operating functions. 3-1
overview, 3-1

Receive Descriptor Ring Address Register (RDRA).
5-56

status and error messages. 3-4

Receive Descriptor Ring entries. 5-57 10 $5-59

Ethernet error. 3-4
internal hardware. 2-2. 5-1

DC7053 gate array, 5-12

Control and Status Register 0. 5-49 10 5-51

disconnecting manufacturing mode jumper,

Control and Stztus Register 1, 5-51

2-2

Ethernet chip set. 5-42

Control and Status Register 2, 5-51
Control and Sta2tus Register 3, 5-52

Ethernet interface chip set. $5-2

station addressing, 5-%4

hardware memory addressing. 5-2

Transmit Descriptor Ring Address Register

jumper connection for manufacturing mode.
2-2

(TDRA), 5-56105-57
Transmit Descriptor Ring entries, $- 60 t0 5-62

memory subsystem, 5-1

LANCE Initialize block, 5-53

Programmable Array Logic (PAL). 5-20

Load failure, 3-5

router subsystems, 5-1

Local Area Neitwork Controller for Ethernet

Serial interface Adapier (SIA), 542
interrupt control, 5-9

modem control interrupts, 5-11
parity error interrupt. IPLTM. 5-10

(LANCE), 5-44
operating signals, 5-45

Locai Area Metwork Controller for Ethernet
see LANCE

index-3

On-line Debugging Tool
Maintenance Operations Protocol (MOP), 3-2
Maintenance print set

see ODT
Operating modes

Ethernet operating modes, 5-47

part number, 5-1

initialized mode

MC68000

in Self-test, 2-2

bus arbitration logic, 5-9

parameter byte, 2-2

interrupt conirol, 5-9

normal mode operation, 2-5

logic definition, 5-2

MC68000 CPU, 5-1
Microcomputer logic
CPU data address bus, 5-2

MC68000 architecture, 5-2
Microprocessor logic

data/address bus signal description, 5-4
Modem consrol
DC7053 gate array, 5-2
interrupts, 5-11

signal testing, 2-8

STSRTS__CTS test. 2-8
Modems, 6-2
modem signal error. 2-3

MOP
see Maintenance Operations Protocol

Self-test fatal error mode, 2-3

P
Parity error interrupts, §-22
Personal computers, 1-1

IBM PC/XT, 1-1
IBM Personal computer/AT, 1-1
types supported by DECrouter 200, 1-1

Physical Address Programmable ROM (PA PROM),

5-23
Pointers

addressing. 5-20

initialization, 1-5

Sequencer logic, 5-7
Program RAM, 5-21

Network access. 1-9

Network access and protocol, 1-9
Network initialize

DMA transfers and bus arbitration, 5-46 to 5-47
PROM, 2-7

CRC testing, 2-7

see N1

Ni. 2-7

checksum test, 2-°
Nonbuffered devices. 5-4

RAM, 2-2
allocation of, 5-22

extended test, 2-7
in server entry mode, 2-2

ODT. 4-1

and accessing router address space. 4-4
command functions, 4-2
command input errors, 4-2

command summary. 4-2
commands, 4-3 to 4-3
entering ODT

from operating software, 4-2
from ODT, 4-1

from self-test manufacturing mode, 4-1}
from self-test mode, 4-1
initial requirements, 4-1
privileged commands. 4-2
programsming in ODT, 4-8 to 4-10

range error, 4-2

ODT commands

CPU register commatids. 4-6 10 4-7
dump commands, 4-7 t0 4-8

the Examine commands, 4-5 io 4-6

index-4

initialized RAM, 2-2
program RAM, 2-5

error modes, 2-5

quick verify test, 2-7
test initiated from. 2-5
Random Access Memory

see RAM
receive and transmit register formats, 5-27

Augxiliary Control Register ACRO”, 5-34
CSRA and CSRB bit assignments, 5--32
CTUR and CTRL counter/timer registers, 5-41

DUART and LANCE registers, 5-21

in ODT.4-5
input and output port registers. 5-34
Input Port Change Register (IPCR)

format, 5-35
Input Port Status Register (IPSR), 5-36

Registers (cont.)
interrupt Control and Counter/Timer

Scif-test (cont.)
LANCE testing (cont.)

Registers, 5-37

Interrupt Status Register (ISR), 5~-39

LANSRCV__BAD__CRC test, 2-9
LANSRCV_GOOD__CRC test, 2-8
LANSREJECT__PHY, 2-8

MRnA and MRnB bit assignments, 5-29 to

RTSBAUD_RATE test, 2-9

Interrupt Mask Register, 5-40

RTSBREAK test, 2-9
RTSCHAR_LENGTH test, 2-9

5-30
Output Port Configuration Register (OPCR),

5-36

RTSFRAMING test. 2-9
RTSOVERRUN test, 2-9

Output Port Register (OPR), 5-37

receive and transmit

STSEXERCISER test, 2-9

MR1A and MR1B, 5-28

LANCE testing LANEXMT__CRC test, 2-8

receive and transmit register formats

modem signal test, 2-8

MRnB and MRnB, 5-28

nonfatal error status, 2-3

RHRA and RHRB receive holding registers,

operating modes, 2-1

5-33

manufacturing mode, 2-2

FIFO cache, 5-33

normal mode, 2-1

SRnA and SRnB bit assignments, 5-30 to 5-31

program tests, 2-5

THRA and THRP receive holding registers,

ST$CPU_REG_
) test, 2-6
STSEEPROM__CS test, 2-8

5-34
Reset, 5-26

STSEEPROM__RW test, 2-7

signal for DUARTS, 5-26

STSEXTENDED RAM test, 2-7

Reset circuitry, 5-7

STSGP_TIMER test, 2-7

and EEPROM, 5-23

ST8JAM__) test, 2-6

reset testing, 5-7

STSLOADER test, 2-7
STSNI_ADDRESS test, 2-7

circuitry, 5~7
warm reset, 5~7

STSPARITY test, 2-7

Router logic

illustration of, 5-3

STSPROM__CRC test, 2-7
ST$QUICK__RAM__] test, 2-7

MC68000, 5-1

STSREFRESH__TIMER test, 2-7

nonbuffered devices, 5-4

STSRESET_TO__FACTORY (est. 2-8

reset circuitry, 5-7

STS$STUCK _INTERRUPTS__J test, 2-7

ROM, PROM, and EEPROM. 5-1

STSWD__TIMER test, 2-7

router subsystems. 5-~1

terminal port errors, 2-3
Serial Interface Adapter (SI1A), 1-2

SIA, 1-2

clock and timing reference, 5-44

Self-test, 2-1
bugcheck, 3-6

S O ©

B 2o

checksum errors, 2-4

CRC test, 2-7

Time-out error, 3-5

dispatch table, 2-5

Timers, 2-7

error cades, 2-10

counter/timer start and stop commands, 5-41

error types, 2-3

DUARTO counter/timer addresses, 5-41

fatal errors, 2-3

DUART
1! counter/timer addresses, 5-41

nonfatal errors, 2-3

DUART2 counter/timer addresses, 541

fatal error mode, 2-3

DUART3 counter/timer addresses, 5-42

general description, 2-1

general purpose timer test, 2-7

initialize program. 3-1

programmaoic, 1-<

LANSREG__TEST test, 2-7

vefresh time¢ - ( 2st, 2-7

LANCE testing

timer mode, 5-41

LANSACCEPT__PHY test, 2-8

start timer, 5-41

LANSBRODCAST test, 2-9

stop timer, 5-41

LANSCOLLISION test, 2—-8

watchdog timer test, 2-7

LANSEXTERNAL__LOOP test, 2-9

LANSMULTICAST :est, 2-9

index-5

U
Up-line dump, 3-3

from watchdog timer, 3-3

maeso 3‘3

dumping to host, 3-3
image dump complete, 3-3
waiting for image dump, 3-3

procedure, 3-3
User commands

the INITIALIZE command, 2-2

W
Watchdog timer, 2-7

index-6