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EK-DR11W-UG-004

June 1987

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Document:	DR11-W Direct Memory Interface Module User's Guide
Order Number:	EK-DR11W-UG
Revision:	004
Pages:	138
Original Filename:

OCR Text

EK-DR11W-UG-004

DR11-W

Direct Memory Access

Interface User's Guide

Prepared by Educational Services

of
Digital Equipment Corporation

4th Edition, June 1987

The information in this document is subject to change without notice and should
not be construed as a commitment by Digital Equipment Corporation. Digital
Equipment Corporation assumes no responsibility for any errors that may
appear in this document.

Printed in U.S.A.

This document was set on a DIGITAL DECset Integrated Publishing
System.

Class A Computing Devices:

Notice: This equipment generates, uses, and may emit radio frequency energy.
The equipment has been type tested and found to comply with the limits for a
Class A computing device pursuant to Subpart J of Part 15 of FCC Rules, which
are designed to provide reasonable protection against such radio frequency interference
when operated in a commercial environment. Operation ofthis equipment in a
residential area may cause interference in which case the user at his own
expense may be required to take measures to correct the interference.
The following are trademarks of Digital Equipment Corporation:

Enflflanw

DECwriter

RSX

DIBOL

Scholar

DEC
DECmate
DECset
DECsystem-10
DECSYSTEM-20
DECUS

MASSBUS
PDP
P/OS
Professional
Rainbow
RSTS

ULTRIX
UNIBUS
VAX
VMS
VT
Work Processor

CONTENTS

INTRODUCGTION ... ..ttt
eeiee e esir e e e e eevreeeeeearraesessrsreesesnreeas
MODULE LAYOUT ..ottt
sttiree e ssattraaas e e s s s snanneaasaeens
BASIC BLOCK DIAGRAM ..ottt
DATA TRANSFER TECHNIQUES ..........coiiiviiiiiiiee
e eerere e
Programmed I/O. ...t
Interrupt Driven I/O . .....oooooiiiiiiiiiiceeeeeee
e
Direct Memory Access I/O ..ot
BURST MODES ...ttt
e e e e e saarbeae e s s e s essrraeaaeeeeannns
DATA TRANSFER RATES TO USER DEVICES..........coooviiieviieeeeee
DATA TRANSFER RATES ACROSS A LINK ...ccooicviiiiiiiiiiiieec
e
SPECIFICATIONS. ..ottt
e erarre s s s sesastbbreaeeeeene

e Y o

Go
DN =

e N S Gy Sy Gy VPG W

GENERAL INFORMATION

NN UBARRRWLN—

CHAPTER 1
U

PREFACE

CHAPTER 2

SETUP, INSTALLATION, AND TESTING

2.1

GENERAL......ttiei
et
e bt re e s bn e e e s iraee e s ssreeeeesebeees
UNPACKING ..oooiiii ettt
e e ree e s et ree e s sibbae e s enabbeeeessanneeas
ANTI-STATIC PRECAUTIONS......oooiree
e
SETUP....... ettt
e e e e e b e e e e e sebeee e saebaaeeessbasaeeessnbeeeessnnnes
Selecting the UNIBUS AdAress ......oooooeeeeeeiiiiiicciiiriirrrreereeee
e e
Selecting the Interrupt Vector AdAress......vvvvveeieieiiiiiiieeeeee
e
Setting the E10S5 SwitChpack.......ccccviviiiiiiiiiiiiiiiiecc
e
Selecting the Correct BUSY Signal .......cccvvviiiiiiiiiiiiiniieieee
s
Setting UNIBUS Address Bit <00> Suppression.........ccccceevvveceveveeeeenn.
Selecting Error and Information Register (EIR)Suppression................
Setting the Burst-Size Toggle SWItCh ......ccoooviiiiiiiiiii
e,
Selecting the UNIBUS Time-Out Value........cccoovvviiiiiiiiiiiiiiiieceneeenininnnns
Selecting the Burst Release Time-Out Value .........vvvvveiiiiviiiiiiieeeiiiinniinnnnnnn,
Selecting the UNIBUS Interrupt Priority .......ccccovvvviiviiieiieiieneeeeeneeeeninnennnnn.
INSTALLATION AND CHECKOUT ......ooviiiiiiiiiriiieeeeennieeeeecee
e ninnceceen s
Installing the DR11-W in a Compliant System ........ccccceveeeeeeiminiiiieeininnnnne
Mounting the Bulkhead In the Existing Picture Frame........ccocccveeeieinnnnnne
Installing the DR11-W in a Non-Compliant SyStem ..........cccceeevveeeeernnirinnnns
Installation Without the Bulkhead Pane.........cccccoovveeviiiiniiiiiniiniiinnnn,
CABLE WRAP-AROUND TESTING ......ooiiiiiiiieiiiiieeeniteeenrieec
e
LOGIC WRAP-AROUND TESTING .......cooiiiiiiieiiiiieetieee
et
LINK-MODE TESTING......cccovttii
ittt ettt esireeseeiiiteesesntreeessinreeesennenes
FINAL INSTALLATION.....ooiii ittt
eetee et
ee e s

2.2
2.3
2.4
24.1
2.4.2

243
2.4.3.1

2.4.3.2
2433
244
2.4.5
2.4.6
2.4.7
2.5

2.5.1
2.5.2
2.5.3

254
2.6
2.7

2.8
2.9

ii1

1-1
1-3
1-4
1-5
1-5
1-5
1-5
1-5
1-9
1-9
1-9

2-1
2-1
2-1
2-1
2-2
2-2
2-3
2-3
2-3
2-5
2-5
2-6
2-7
2-8
2-8
2-10
2-10
2-11
2-11
2-12
2-14
2-15
2-17

CHAPTER 3

~1ONWN
O

LogIC REfErence ...ccooiiviiiiiiiieieei
e
Transmission DISTANCE ...........covvvviiiiiiiiiiiiiriire
et
DATA FORMAT.....oooo oottt
e e s s sbanaee e e e s ssaaanss s
DIRECTION OF DATAFLOW DURING PROGRAMMED l/0....................
DIRECTION OF DATAFLOW DURING DIRECT MEMORY ACCESS
(DA L/O ettt
e e et e e e e e e e e s se s et eaen e rreeeeeesasesssssiensasses
INPUT SIGNAL FUNCTIONAL DESCRIPTION ......cccooiiiiiriieiiicciiiirceeenn,
Data INPULS.....cooiiii e
ee s
STATUS IIPULS....iiiiiiiiie e
rre e s s e e
BUS CONEIOL. ..ottt
et e e e s esse s
eereaes et et e e e esae s
INTEITUPL oo
OUTPUT SIGNAL FUNCTIONAL DESCRIPTION......cccceveiiiiieiieieeieeeen,
Data OULPULS ...cooiiiiiiieieciccccrr
e e e e e e e e e e s e s s sesssssssssassssnraarbaraeeee e
FUnction OULPULS.......cooeieiiiiiiicciirirrrrr
i rrrrrrerreeee e e e e s s s s essssssnassaannsasaas s
BUS CONIOL...coviiieiiiei
e rere s e s e ee e s s e s s s stbanesasseseesnns
MISCEIIANEOUS ... uuicieiiiiitiee et
eeee e ree s s e e eareenee e e e eteransasseeaasnes
DMA CYCLES IN GENERAL ......ooveeeeennrreeeeentirae
e
A SINGLE CYCLE IN DETAIL....oooviiiiriiiieereirerenrrenrersseeeaee
s
POSSIBLE FAILURES ...ttt
ettt rrerne s e e s s esiibbreeee s

W W W
1]

PG
DN
VS I\
E

NBEWRDNNRDNNDND—O

s
et et
—

Lo
DN —

ootN

[

ek
kot
ek
ok

(US|

~J ~J ~1 ~J

OO0 OO0

OO0 O0
00
\D

Lo Lo Lo W
o

et e

Lo Lo Lo LW

—

INTRODUCGCTION ..cooiiiiiiiiiiiieccrterrrrert
e eee e e s e ee e s
serasbssss bt a e e eseeees
PH Y SIC AL
et ee e e e e e e e e e e s s e s s
eaaseaas bt e bt e s e e e e e e e eeees
ELECTRICAL ..ottt
ettt n e e sbaab s s eiaaba s
OULPUL CIFCUIL ..vviveiiiiiiiee et
es
e sbrs e e st ne s e eaaanes
INPUL CirCUIL.....ooiiiiiiiceee et
ae e
TEIININALOTS ©evvveeeeee e et
r s e e s e e e e e e e eeeeeeeereeerenssreaebb b
eenes
Cable CharaCteriStICS......coeeevieeeiirrrriiieiererireereteteeeeeeessssssnssnererasrsresaetaereseesesens
LOZIC LEVEIS .uvvvieeiiiiiiee ettt
s
LOZIC POLATItY ...ttt

W
o Lo

ek ek et
e

Lo L2 Lo Lo Lo Lo LI
Lo L2

USER DEVICE INTERFACING

PROGRAMMING THE DR11-W

4.1

INTRODUCGCTION ..ottt
er e e e e e e e e e e e e s s s s aessrreerasaaeesesasesenenenss
REGISTERS .. ...ttt
e e e s et eeeeeeeaessesssssssnnnn
Word Count ReEgISIET .....vvuieiiiieiiiiieeeeeeecee
e
eerere e s seeeaaarae s e
Bus Address REZISLET ....uuuuuuiiiieeeiiiii
e
e s s e eeeeeeeseeeeaneenee
Shared AdAress 772 414
ererer e e eeeeees
Control and Status ReIStEr........uuiiviiiiriiiiiieeeiiiiirreeee
e rreeee e eereneeeeen
Error and Information REGIStEr........cccoviiiiiiiiiiiiirrrrceeneeee
e

4.2.1
4.2.2

4.2.3

4.2.4
4.2.5

3-5
3-5
3-6
3-8

3-9
3-11
3-12
3-12
3-12
3-13
3-14
3-15
3-15
3-15
3-15
3-15
3-16
3-20
BYTE TRANSEFERS ... .ot
eers e e erere e e e eseeneeeenss 3-21
Reading Bytes from MeEmOTY ..cooccovciiiiiiiiiiiiieieiieeeeeceeeeinnnes
e 3-21
Simplest and SIOWESt ......cccoooviiiiiiir
e 3-21
A Faster Harware-Based Approach.........cccccovvviciiiinmiiinnennreeicennnecececenenn. 3-21
More Complex and Fastest.........ccovviviiiereiiiiiiiiiiiiiiriciierereiereereereeeeeens 3-21
WIING BYLES oooeviiiiiiiieee
e e e s e reeener et e bere e rs
s 3-23
Simplest and SIOWESt ........cccoiiiiii
e 3-24
A Faster Hardware-Based Approach........ccccococvvviiiiiiiininceceeneeeneeneenens 3-24
More Complex and Fastest.........cccoviiviiiiieeiiiiiiininniiniierereeeieeeneeeeeen 3-24
PROCESSOR CONTROL OF TRANSFER DIRECTION ......ccccccceviviiniieeeenn. 3-24
PROCESSOR CONTROL OF BURST MODE .......ccccooviieiiiiiriieeeeeeeciieeeeen, 3-25
USER DEVICE CONTROL OF BURST MODKE...........ccociiiiirrreeereeeceeeeenn 3-26

CHAPTER 4

4.2

3-1
3-1
3-1
3-1
3-1
3-1
3-1
3-4
3-5

4-1
4-1
4-1
4-2
4-3
4-3
4-8

4.2.6
4.2.7
4.3
4.4

Input Data RegISter.......ccooiiiiiiiiiiiiiiiiicirreerrre
s se e e
ran e
Output Data RegIStEr......ccoiiiieeiiiiiiiiiciiiiiriirrrrrrrerre
ee e e s e
DATA DESKEW ...ttt
s e e s s s s bbaae e e s s e abasanae s
USING PROGRAMMED /O ....coviiiiiiiiiiiiiiiieciiiiieee ittt e

4-9
4-10
4-10
4-12

4.5
4.6
4.7

USING INTERRUPT DRIVEN I/O.....cccoiiiiiiiiiiiiiceiieeec e
STARTING A DMA TRANSFER ...ttt
DEVICE DRIVERS....ttt
seiit et re e s s
eee e

4-13
4-14
4-14

CHAPTER 5

LINKS

5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.7.1
5.7.2
5.7.3
5.8
5.9
5.10
5.11
5.12
5.13

INTRODUCGTION ...ttt
ettt e eectreee e s rtvreeesnreeaeesseaaeesessnaneessssseesssssneeeesns
LINKING TWO DRIL-WS. .ottt ecctireeeeevreeeeeetiaaeeesnenaesssineaesssssvneasns
LINKING A DR11-W TO A DRV11-B OR DRVI1I-W .....ccccceiviiiiiiiiiinee
REDEFINITION OF SIGNALS AND CSR BITS ...
REDEFINITION OF BAR BIT <003 .......cooovviiiiiiiiieeeieireeeeeiieee
e eriree seineeeeens
SPECIAL INTERRUPT CONDITIONS........ootiiiiiieeeeiier
et
eeiree e
BASIC PROGRAMMING TECHNIQUES.........cooviiiiireee
it
Programmed I/O......ccoviiiiiiiiiee
et
Interrupt Driven I/O ..ot
DMA T/O ottt
e st e e eeees
LINK ARBITRATION.........cccevvvviieinnennset
——t e e e e e e araeeearraaeasSRR
INITIATING-END VERSUS SENDING-END ......ccoooviiiiiiiieiiiiiec
v
STARTING A DMA TRANSFER....... ett eeeesiirateeeaaereeee
e ——raeeabreeeearareesatres
STARTING ORDER .......ooiitiiieiiciiiee
ettt sevee s ssiree e s esbtaeessianeeessaibeeeenan
UNIBUS BANDWIDTH CONSUMPTION.......cccoiiiiririieeeiiiereeriiieee e
BURST MODE ......coioiiiiiiiiee ettt ettt et e e erae s e s ssnaae e s snsebraeessanbseeessnbeeeessanee

CHAPTER 6

DMA OPERATION IN DETAIL

6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.17.1
6.17.2
6.17.3

INTRODUCTION .....ottiiiiiiiiiiiiitee
e eeriiirreee e e s s sierreeeeessessmbrsareseessessbransseesssssiranaes
OVERVIEW ...ttt
reee e e e e e e s e
READY LOGIC ...ttt
WORD COUNT OVERFLOW ...t
eeeeesiiiniensnseneeae
CYCLE AND BUSY LOGIC ......ccooiiiiiiiiiiercceeeireeccc
e
MULTICYCLE REQUEST ...c.oiiiiiiiiiiiieee ettt
ceineven e
THE CYCLE DELAY LINE .....cooiiiii et
CYCLE INHIBIT FLIP-FLOP.......ccciitiiiiieeeeiniiieeeceeeiniteeccesnieneeee
e
THE NPR REQUEST FLIP-FLOP........cccocccvviiiiiniiiiieee
e rrrrreeteeeererereasenes
THE NPR ARBITRATOR.......oocoiiiiiiiiiiie
et
UNIBUS TIMING LOGIC ......ooiiiiiiiiiiiiireeeeeiirieee
e
sssiraeeee e ssnanans
SLAVE SYNC FOR WRITE OPERATIONS ........ccccceiimiiiiiiiiiiie
e,
SLAVE SYNC FOR READ OPERATIONS ...ttt
BURST OPERATION ......iiiiiiiiiiiiiiiirireerreeerteeeeeeeseessesssisbessssssssaeierseeessseseees
N-CYCLE LED ....ccooooiviiiiinireeeeeee et rerebertbtrrrrarrteeaaeetataeeeteaaan
e aaaaenrbneenene
BURST RELEASE TIMER........cccccoiiiiiiiiiieteeecce
e
ERRORS ..ottt
e st e e e s s sbb e e e e s s e ssanrebee e e s e sasnbas
AC LO EITOT oot
ee
e
Parity Brror.. ...
Non-Existent Memory Error.....ccoocvvieieiiiiicieeiiiieeeiinnniine

5-1
5-1
5-3
5-3
5-4
5-4
5-4
5-5
5-5
5-5
5-5
5-5
5-6
5-6
5-7
5-8

6-1
6-1
6-1
6-1
6-2
6-3
6-4
6-5
6-5
6-6
6-7
6-10
6-10
6-11
6-11
6-12
6-12
6-12
6-13
6-13

6.17.4
6.17.4.1
6.17.4.2
6.18

YN RTS) 118 (0) ¢ PUUUURTUTOT U
TP
Attention t0 the CSR ...oeeiiiiiiiii
e
Attention Causing an Interrupt .......cccovvveeiiieiriciiiii
INTERRUPT LOGIC ..ot
riinrein s sannnanee e

APPENDIX A

THE VAX/VMS XADRIVER

FIGURES

-1
1-2
-3
1-4
I-5
-6
1-7
2-1

2-2

DR11-W Block Diagram OVerVIEW.........coovviiiiiiriiiiiiireiirirneeerrreeeeeeeneeesessisnssnsenns
Overview Block Diagrams of DR11-W Links .....cccccoovviiiiiiin,
DR11-W Module Physical Layout.......ccccccoevriiiiiiiiiiiiiirereeeeereecee e
DR11-W Basic Block Diagram ..........ccccoiiiiiiiiiiiiciiiiirrererereeeeee
e ee e e
Single-Cycle UNIBUS Transfer Timing Block Diagram .........ccccoccveinniiinninnnn.
Two-Cycle UNIBUS Transfer Timing Block Diagram ........cccccovviiiiiiiiiiinnnnnnnn,
N-Cycle UNIBUS Transfer Timing Block Diagram.......ccccoccccoiniiiiiiininnnnnn.,
Burst Release Time Waveform ........cccccoiiviiiiiniiiniiieeeeeceeccen
s

2-4

Installing the DR11-W in an FCC-Compliant System (Showing a PDP-11/24
or a PDP-11/44 and a BA11-A in an H9642 Cabinet) .........cccceeevveeiniieerennns
Installing the DR11-W in a Non-Compliant System (H9642 Cabinet, 871-C
Power Controller, and Add-On Picture Frame).......cccccccoevivviiinineeieicccciineninn,
Installing the DR11-W Without the Bulkhead Panel (H9642 Cabinet, 871-C

2-5
2-6
2-7

Power Controller, and USer DeviCe)......covovviviiiiiiiiiiiiiiiiiieirrreeeicrsee
e
Cable Wrap-Around Testing Configuration............ccccovvverevninieciiiiiincnnieeenen,
Logic Wrap-Around Testing Configuration ............ccccoveviiieiniiiecenniiecinneneennnnne
Link Testing Configuration ..........ccccovvirrereiriiiimiieeeeriieeee
e s

3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11

Typical DR11-W Output Circuit Diagram......ccc.ccoeevireivriiiiiiiiieeeiieecceeeeieeeenn
Typical Dr11-W Input Circuit Diagram ........oceeriiieiimiiiiiiiiin
e,
Unused Input Configurations ..........ccccccciiiiiiiiiiiiiiineiiiiiereeiieeeerreeeeeeee
ee e e
s
The UNIBUS Address Space Map for a Series of 8-Bit Bytes.......ccccccevnvnnneeees.
UNIBUS Address Space Map for a Series of 16-Bit Words...........coovvieeernnnnen.
Eighteen-Bit UNIBUS Address Configuration ........c.coeeeeieviiveeeeenieeennnnneennnnnee.
UNIBUS Data Interpreted as @ Word........ccoevveeeeiiiiiiiiiciree
e
UNIBUS Data Interpreted as Two Bytes.....oooocviieeiiiiiiiiiiiiiieneiieeeeee
e,
Processor Writing Output Data Register Diagram..........cccccvveeeriiieieeeennennenncinnnnenns
Processor Reading Input Data Register Diagram........cccccccvviviiiiiieiereeeeneerenineennnns
Data from Memory to User (DATI) Diagram .......cc.ocvveeiiiiieeniniiceeiiiieneceneen,

2-3

3-12

Data from User to Memory (DATO) Diagram.........cccccceeeeiiiiiiiiiiinieiiiiiiinenes
e

3-13
3-14
3-15
3-16
3-17
3-18
3-19

J1 and J2 Connector Pin Identification ..........cccccoeevveviiiiiiiiiiiiiiceeeereeceee
DR11-W Input MUX and Latch Block Diagram .........cccccccvviiiiiiiiniiiinnnnnnnn.
Cycle and Busy Logic Diagram .........cc.ccooviiviiiiiiiiiieneireiereee et
Simplified Read-Cycle Timing Diagram..........ccccccveevviiiiiiceieniiniiiere
e
Simplified Write-Cycle Timing Diagram ..........ccccoevvvirrieiiiiiiiiiiiiiieeeeieercnreere
e
Unpacking a Buffer Prior to Reading Bytes from Memory........cccccvveevivereeeneennn.
Logic Diagram of User-Supplied Hardware to Read One Byte
PET DMA CYCIE ...ttt ettt
e e e s e e e eaeeenaens

3-20

Logic Diagram of User Supplied Hardware to Read Two Bytes per

DIMA CYCIR.. ittt
e e e e e et et ettt e e e e e s e s esabs bbb b s saraaaaeeeaaeeaeneas
Packing a Buffer After Writing Bytes to Memory ........cccoocveveiviiieeevncneee
e
Connections for Processor Control of Transfer Direction ............cccveeeevevvereeenneen.
Connections for Processor Control of Burst Mode ..........cevvvveeviiiiiiinininiiiiiiinn,
Circuit for a User Device Which Never Uses Burst Mode.........ccccooeveivriivereennnns

3-23
3-24
3-25
3-25
3-26

3-26

Circuit for a User Device Which Always Uses Burst Mode..........cccoovciivnnnnnnnnnnn,
Circuit for a User Device Which Dynamically Uses Burst Mode ........................

3-27
3-27

3-21
3-22

3-23
3-24

k'thLIhklth

Configuration for Cross-Cabling Two DR11-Ws to Create a Link ......................
Connection Diagram for Half of a DR11-W Link......cccccccoiiiiiiiiiniiniiineenns
Link DMA Operation Flow Diagram.........ccccccooiviiiiiiiiiiiiiiiiininreeeeeeeeeeeeennneeennnne
Busy Signal Relationship During Link DMA Operation.........c.cccccoeeiivinieeceeennnns
Busy Signal Relationship During Link Operation with Added Delays..................

5-1
5-2
5-6
5-7
5-8

DMA CyCle LOZIC ...ciiiiiiiieeeiiiiiiiieectitrr
et e e e e e e e e e e e e s s s s s
eseeeeeeees
REAAY LLOZIC. ..ot
e e st e e e et eee e s st e e e e s
Cycle Request and Busy Logic Diagram ..............oovvvvviiiiiiiiieeeeecee
Cycle Delay Line LOZIC. ...t
NPR Arbitration LOZIC ......cooiiviiiiiiiiiiiiiiiee
et
e e e e e e s e eeeeeeeenenannneaes
UNIBUS Timing LOZIC.....iiiiiiiiiiiiiiiiiiieeee
ittt eeeee e e e e e e e
UNIBUS Write Logic and Timing Diagram .........c.ccovecvviririeinniiiiiiieeeeenieieeeen.
UNIBUS Read Logic and Timing Diagram...........cocovvviiiiiiieniiiiiiieeesniniieeeeee
BUISE LLOZIC 1oviiiiiiiiiiiiieiee ettt
eee
et e e e s ettt e e e e e et e e e s
|25 g o) gl I 4 LRSS
PP
ATEENTION LOZIC..ociiiiiiiiiiiii et
ess
eee
Interrupt Arbitration LOZIC ....ccooiiiiiiiiiiiir
e

6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-11
6-13
6-14
6-16

o
— O

(U, R S

~1ON

—

-b-lk-b-lk-llk-h-lk-b-l}-

Word Count REZISTET .......cooiiiiiiiiiiiiei et e e e e e e e e e e e e e e e s e e s
benees
4-1
Bus Address Register.........c.ccevvveeeeviriiiiinnninnninneerenes. iereessesseessetieeseresernretersttennen
4-2
Formation of an 18-Bit UNIBUS Address......ccccccoeeiiiiieieeiiiiiiciiiiieeeeesriieneeeee
4-2
CSR/EIR FLP-FIOP ....citiiii ittt
eete e et e e e et eesnaeeees
4-3
Control and Status RegISter .........oooiiiiiiiiiiiiiiiccc
s
e
4-4
Error and Information REgIStEr ......cccociiiviiiiiiiiiiiiiiireeeeeeeee e
4-8
Input Data RegISter....cccocviiiiiiiiiiiiiiiiieiee
e et e e e e e e e s e s
4-9
Output Data REGISIET ..ooeiiiiiiiiiiiiii e
et e e e e s e e s s e s e 4-10
Shewing of SiZNalS.......cccooiiiiiiiiiiiiiii
e e e e e e e e e e e et e eereereenane 4-11

O\O\O\O\Q\OI\O\O\O\O\O\O\
s D 00 I N Bt

3-25

TABLES

DR 11-W DMA Speed in Various COmMPULETS .....oovvvvvriirereerriiiiriireeeeenniininieeeeeen

1-8

AdAress SelECtION. . ..uiiiiiei it
e e e e e e e e et e e earieaneaas
Interrupt Vector Address Selection..........ccveviiviiiiiieriiiiiiiniiiiniiiie
e
Busy Signal SeleCtion.......cccocuviiiiiiiiiieeiiiiiiiieeeiie i
AQO SUPPIESSION ...eeieiieiiirreeeeiiiireeeeiiiteet
e e ietee e s ittt s ettt e e e iatre s s rbre s e e ssbraaeesnseeas
Error and Information Register Suppression .........veeeeeeeeccciiniiin,

2-2
2-3
2-4
2-4
2-5

vii

BUISt SI1Z6 Sl
T ION ouuieeeeiiieeeiteeeeteeeeueesennesssanserenteensernserssrsrrinesssesesrrnessssiesennsnes
Slave Sync Time-Out SEleCtion........coeevcvieiieeirieeerniiiiiiiiir
e
Burst Release Timer Adjustment..........coevvvvveeeneeceeineeinnnnnn brrrrrreraraaaaaeeaaaaaaaaaanas
BR Level Plug Part NUMDEIS.........covviireireeiiiiiiiiiiiiniiinec
e

2-6
2-7
2-9
2-9

Cable Stock Part INUMDEIS .......uvvvviiiiiririiiiiieirrieereeeeeee et
Locic Voltage Level Requirements .........cccccceveivviiieiiiciiiinmiiiiiiieeee
e,
DMA Data FIOW DIr€CHIONS ......covvviiiiiiiiiiiiiiiiiieieeeeneneennnnaniecsinirininereeerrieseeeeseeeenns
DR11-W User Input Signals .......ccccccvvviiiiiiririierierinieiiniininiineee
e
UNIBUS Cycle SEleCtion ........cceeiiiiieiniiiiiireeeereeeiiinreeeseeininenieeeeenessainnereeessssnnnees
DR11-W User Qutput Signals ........cccvvviiiieieeiiiiiiiieeee
et snerrneree s eesiineeees

3-4
3-4
3-10

viil

3-11
3-13
3-14

PREFACE

The DRI1-W Direct Memory Access Interface User’s Guide describes the installation, testing, and use of

the DR11-W in both the PDP-11 and VAX-11 environments.

Chapter 1 describes the DR11-W in general and cites its specifications.
Chapter 2 describes the configuration, installation, and testing of the DR11-W.

Chapter 3 describes the physical interface presented to a user device connected to the DR11-W.
Chapter 4 describes DR11-W programming in general, and the specific programming considerations
which exist when the DR11-W is connected to a user device.

Chapter 5 describes the additional hardware and software considerations which exist when two DR 11-Ws
are cross-connected to form a high-speed, computer-to-computer data link.
Chapter 6 describes in detail those inner workings of the DR 11-W which may be of concern to the system
implementer.

Appendix A provides a listing of the Macro-32 source for the VAX/VMS XADRIVER.
The manual assumes that you have a basic knowledge of the UNIBUS as well as PDP-11 or VAX-11
assembly language. All programming examples are given using PDP-11 code since that should be intelligible to both the PDP-11 and the VAX-11 programmer.
The UNIBUS is described in detail in the 1985 UNIBUS Processor Handbook; other details of the
processors may be found in either the PDP-11 Architecture Handbook (EB-23657-18) or the VAX-11

Architecture Handbook (EB-26115-46).

This, the fourth edition, is all new and supersedes the previous three editions. A few terins have been
redefined. Most are self-evident but two changes should be noted in particular.

Operating Modes

The first through third editions referred to three operating modes for the DR11-W:
1.

Word mode

Block mode

Burst mode (either two-cycle or n-cycle)

known as nonIn the fourth edition, block mode refers to the various DMA modes: one-cycle burst (also
g operating modes:

burst), two-cycle burst, and n-cycle burst modes. The fourth edition defines the followin
I.

Word mode

a.
b.
2.

Using programmed I/O
Using interrupt /O

Block Mode

a.
b.
c.

Using one-cycle bursts
Using two-cycle bursts
Using n-cycle bursts

S
This form is in keeping with the rest of the DR11-W related documentation, in particular, the VAX/VMS
VAX/VM
for
XADRIVER description contained in the Guide to Writing a Device Driver
(AA-Y511A-TE).

Burst Data Late

Additionally, all references to burst data late have been changed to burst release. This is to eliminate
confusion with the data-late error (which a burst release does not represent).

CHAPTER 1

GENERAL INFORMATION

1.1

INTRODUCTION

The DR11-W is a general-purpose module used whenever a UNIBUS PDP-11 or VAX-11 computer must

be interfaced to another device or computer and transfer parallel binary information. The DR11-W
provides the logic to interface this binary data to the UNIBUS.

Data is transferred on the UNIBUS as 8-bit bytes or 16-bit words. The user device may connect to

between 1 and 16 bits of this data. Separate lines are used for data input and data output (see Figure 1-1).

—

=
=

DR11-W

DMA
INTERFACE

16-BIT OUTPUT

DATA

e 16-BIT INPUT
DATA

MKV86-0904

Figure 1-1

DRI11-W Overview Block Diagram

1-1

Two DR11-Ws may be cross-connected to form a high-speed link between two UNIBUS computers. The

DR11-W may also be cross-connected with the DRV11-B or DRV11-W, used on the Q-bus. Together,

these devices allow any PDP-11, VAX-11, or MicroVAX systems to be linked together (see Figure 1-2).

J2
DR11-W

DR11-W

D le

[ 42

DR11-W

DRV11-B

DRV 11-W

»|

UNIBUS

_
y

UNIBUS

%
MKV86-0903

Figure 1-2

Overview Block Diagrams of DR11-W Links

1-2

1.2

MODULE LAYOUT

Figure 1-3 shows a DR11-W module. All of the user-interface features
are called out.

BURST DATA LATE
TIMEOUT POT.

N—CYCLE BURST LED (RED)

(4--30usec MAX)

HA/NDLE

(10—15 usec, NOM)

2-CYC

N-CYC

105

ATTENTION LED (RED)

D2 ,/

R8O

D1 i

TP1(BDL TIMEQOUT TEST POINT)

OPERATIONAL MODE

SWITCHPACK E105
(5 SWITCHES)

2.//

INPUT

OUTPUT

EVVFE’JHMBOPE

CONN.

BUS ADDRESS

c’

]

SWITCH PACK E120

cs8

HANDLE

CONN.

40-PIN

(10 SWITCHES)

MALE CONNECTORS

EEN

VECTOR ADDRESS

LEVEL PLUG E62

SWITCHPACK E15

(FACTORY SUPPLIED AS BR5)

(8 SWITCHES)

BCO6R-XX

INTERCONNECT CABLES

H 855 40-PIN

(DR11-W TO USER DEVICE,
DRV11-B,

‘

ANOTHER

BUS-REQUEST PRIORITY

DRV11-W OR

FEMALE

NNECTORS

DR11-W)

NS
H855 CONNECTORS

BCO5L-1C MAINTENANCE
CABLE (FOR WRAPAROUND MODE)

MKV86-0932

Figure 1-3

DR11-W Module Physical Layout

1-3

1.3 BASIC BLOCK DIAGRAM

The basic block diagram of the DR11-W is illustrated in Figure 1-4.

N\
'NPéJETG%TT’EgUS
!

'NF';’E’C;SDT‘E;A

«——

STATUS A

«————

STATUS C

e STATUSB

e DATA-IN 00-15

UNIBUS

DMA ENGINE:

l«————
e

WC REGISTER

e
.

CSR

BA REGISTER
EIR

|e——

_______»

OUTPUT DATA
REGISTER

CYCLE REQUESTS
O, C1 CONTROL
WC, BA INC ENB
AQO

END CYCLE, BUSY
GO, READY

INTERRUPT

DATA-OUT

LOGIC

——

ATTENTION

00-15

OUTPUT COMMAND | ——
————
REGISTER
TS

FUNCTION 1
FUNCTION 2
FUNCTION 3

MKV86-0913

Figure 1-4

DR11-W Basic Block Diagram

1-4

1.4
DATA TRANSFER TECHNIQUES
The DR11-W may transfer data between the computer and the user device using:

®
e
e

Programmed I/O
Interrupt-driven 1/0
Direct memory access (DMA) I/0O

The first two techniques are collectively referred to as word mode since the processor must participate in
the transfer of every individual word. The third technique is referred to as block mode since the processor
need only participate to set up the transfer of an entire block of data. These three techniques vary in speed
and programming complexity. A typical application uses a mix of techniques.

1.4.1 Programmed 1/0
Using this technique, a program simply moves data to the output data register or reads data from the input
data register. Some means must be provided for synchronizing the movement of the data with the
operation of the user device. This is often done using the function outputs and status inputs.
This technique can be quite fast and powerful, particularly for short transfers. However, it can consume up
to 100 percent of the processor’s time.

1.4.2

Interrupt-Driven 1/0

Using this technique, the DR11-W transfers one word in or out each time an interrupt is generated by the
user device. For relatively slow data rates, this causes much less processor overhead than programmed
I/0, while maintaining the same flexibility.
Interrupt 1/O typically has the lowest transfer rate of the three techniques.

1.4.3

Direct Memory Access 1/0

This is the principal application of the DR11-W. Using this technique, the DR11-W is pointed at a block
of the PDP-11 or VAX-11 memory. Then, without further interaction by the processor, the DR11-W can

read words out of this memory and transfer them to the user device, or take words supplied by the user

device and transfer them into memory. At the end of the block, an interrupt is usually generated.
For mid- to large-sized blocks of data, this is the fastest transfer method.

1.5 BURST MODES
The right to use the UNIBUS for a data transfer is decided by a priority-arbitration process. Before a
DMA device (such as the DR11-W) can transfer data on the UNIBUS, it must first win this priority
arbitration. While the UNIBUS arbitration process is concurrent with data transfers (so that the overall
throughput of the UNIBUS is improved), the need to arbitrate does increase the latency for any one
UNIBUS device.

1-5

Normally, a DMA device arbitrates for use of the UNIBUS, transfers one word of data, and then releases

ARBITRATION

SECTION OF

THE UNIBUS

DATA TRANSFER
SECTION OF
THE UNIBUS

the UNIBUS (see Figure 1-5).

DR11-W

/
\

NEXT DEVICE

one

WORD

DR11-W

\
NEXT DEVICE

TIME ———>
MKV86-0925

Figure 1-5

Single-Cycle UNIBUS Transfer Timing Block Diagram

If a device has a lot of data to move quickly, it often helps to transfer more than one word each time the
device becomes the master of the UNIBUS. In DR11-W terminology, this is called burst mode.
The DR11-W hardware supports the transferring of two words per UNIBUS mastership. This is called
two-cycle burst mode (see Figure 1-6). The DR11-W can also be configured to transfer an unlimited
number of words per UNIBUS mastership. This is referred to as n-cycle burst mode (see Figure 1-7). In ncycle burst mode, the DR11-W can use the entire UNIBUS forever, to the exclusion of all other
prospective users. This mode is sometimes referred to as bus hog mode.

ARBITRATION

NEXT DEVICE

DR11-W

SECTION OF

——

THE UNIBUS

DATA TRANSFER
SECTION OF
THE UNIBUS

NEXT DEVICE

>"———

TIME ————
MKV86-0961

Figure 1-6

Two-Cycle UNIBUS Transfer Timing Block Diagram

1-6

ARBITRATION
SECTION OF

DR11-W

THE UNIBUS

NEXT DEVICE

(MAYBE NEVER!)

DATA TRANSFER
SECTION OF
THE UNIBUS

3RD
DR11-W

WORD

TIME —

MKV86-0962

Figure 1-7

N-Cycle UNIBUS Transfer Timing Block Diagram

Table 1-1

DR11-W DMA Speed in Various Computers
Bandwidth in
Kilobytes/Second
Burst Size

Configuration

993
1394
697

1192
1748
874

936
1192
607

1057
1598
728

943
1202
601

1032
1394
697

799
1024
512

936
1394
697

862
1024
512

1024
1394
697

427
528
264

479
602
301

PDP-11/34 with MS11-L Memory:

DATI (reading memory)
DATO (writing memory words)
DATOB (writing memory bytes)
PDP-11/44 with MS11-P Memory:

DATI (reading memory)
DATO (writing memory words)
DATOB(writing memory bytes)
PDP-11/44 with MS11-M Memory:

DATI (reading memory)
DATO (writing memory words)
DATOB (writing memory bytes)
PDP-11/84 with MSV11-R Memory,
UBMAP Off or DMA Cache Off:

DATI (reading memory)
DATO (writing memory words)
DATOB (writing memory bytes)
PDP-11/84 with MSV11-R Memory,
UBMAP and DMA Cache On:

DATI (reading memory)
DATO (writing memory words)
DATOB (writing memory bytes)
VAX-11/780,

Direct Data Path (DDP):

DATI (reading memory)
DATO (writing memory words)
DATOB (writing memory bytes)

1-8

1.6

DATA TRANSFER RATES TO USER DEVICES

Direct memory access programming techniques generally provide the fastest possible transfer rate. In this
mode, the maximum speed of the DR11-W is largely determined by the speed of the memory that the
DR11-W is accessing.

Table 1-1 documents the fastest observed rates on various UNIBUS processor and memory combinations,
using optimum programming and the fastest possible user device.
NOTE
The speeds listed in Table 1-1 are actual speeds
measured on hardware systems — your system may
vary +5% or more from the values shown in the
table.

1.7

DATA TRANSFER RATES ACROSS A LINK

When operating as a cross-connected link with no additional buffering, the transfer rate is about one-half
of the rate obtained by averaging the speed of each individual end. The exact formula is indicated below.
For example, if the link is reading words from a PDP-11/24 and writing them to a PDP-11/44, the
maximum transfer rate is:

LINK

——
=

1
R

PDP-11/24 READ

PDP-11/44 WRITE
MKV86-0963

1.8

SPECIFICATIONS

The general specifications for the DR11-W are listed below.
e

Data format presented to the user:

Binary parallel words of up to 16 bits

Data format presented to the UNIBUS:
Binary parallel 8-bit bytes or 16-bit words

Transfer methods:

Programmed 1/0O
Interrupt-driven 1/0

Direct memory access 1/0

1-9

UNIBUS characteristics:

Capable of DMA to the full 256K byte UNIBUS address range
Maximum single transfer of 64K bytes or words
All UNIBUS data cycles supported:
—

DATI (read)

DATO (write word)

DATOB (write byte)

—

DATIP (read with write intent)

Three jumper (capacitor) selectable time-out values:
-

Twelve microseconds

Thirty-three microseconds

Forty-five microseconds (as shipped from factory)

Four plug-selectable UNIBUS interrupt priority levels:
-

BR7

BR6

—
-

BR4

BRS5 (as shipped from factory)

Three user-selectable burst DMA modes:

-~
—

One word transfers
Two word bursts
N word bursts

Automatic release of UNIBUS if transfers stop in mid-burst
User interface characteristics:
Two, 40-pin, flat-cable connectors:
—~

Twenty-five output lines, plus grounds

Twenty-eight input lines, plus grounds

All signals driven with UNIBUS drivers or received with UNIBUS receivers for maximum
noise immunity

| All signals terminated into 120 ohms and 3.3 volts
Sixteen-bit parallel data inputs and outputs
Three-bit parallel control outputs

Three-bit parallel status inputs
User-selectable logic-high or logic-low busy signal

1-10

Physical characteristics:

Single hex module - 21.6 cm X 38.1 cm (8.5 in X 15.0 in)
Powered by 3.7 A (nominal) of +5 Vdc
Temperature range:

59 to 50°C (41° to 1229F) operating
—40° to 66°C (—40° to 151°F) storage

Humidity range:
~

10 to 90%, allowing no condensation

Two indicator LEDs:
-

ATTN (interrupt)

N-cycle burst transfer in progress

Programming characteristics:
Six registers occupying four addresses in the I/O page:
—
—
—
—
-

Bus address register
Word (or byte) count register
Control and status register
Error and information register
Input data buffer register
Output data buffer register

Some program compatibility with DR11-B
Errors detected by the DR11-W:

—
-

UNIBUS time-out
Memory parity error
User data overrun/underrun error
Power failure during transfer

Software available:

PDP-11 stand-alone diagnostic program — CZDRL
PDP-11 stand-alone link diagnostic - CZDRK

VAX-11 stand-alone diagnostic program (includes link tests) - ESDRE
VAX-11 on-line confidence check - ESDRB
VAX/VMS sample device driver - XADRIVER

1-11

Related documentation:

DRI1-W Field Maintenance Print Set (MP00693)
PDP-11 UNIBUS Processor Handbook (EB-26077-41)
PDP-11 Architecture Handbook (EB-23657-18)

RSXI11-M Guide to Writing an 1/0 Driver (AA-2600E-TC)
RSX11-M+ Guide to Writing an 1/0O Driver (AA'-H267B-T‘C)
VAX-11 Architecture Handbook (EB-26115-46)

Guide to Writing a Device Driver for VAX/VMS (AA-Y511A-TE)

CHAPTER 2

SETUP, INSTALLATION, AND TESTING

2.1

GENERAL

2.2

UNPACKING

The DR11-W is installed and tested like most other modules. Off-line diagnostic programs are provided
for both the PDP-11 and VAX-11 families of processors. In addition, the VAX-11 family provides an
on-line confidence check program, which uses the VMS sample driver program (XADRIVER).

The DR11-W may have been factory installed in your system. If so, go to Section 2.6. If the DR11-W has
not already been installed in your system, it is shipped in a corrugated cardboard carton. To unpack the
DR11-W, perform the following procedure.

Check that the carton is sealed and undamaged. Report any damage to Digital Equipment

Remove the sealing tape that holds the carton closed. Be careful not to damage the module as

Corporation or to the shipping carrier.

you do this.

Remove the DR11-W module from the carton, keeping it in its anti-static bag. Do not remove
the module from the anti-static bag until you are at an anti-static workstation.

Inspect the DR11-W module for visible damage. Report any damage to Digital Equipment
Corporation.

2.3

ANTI-STATIC PRECAUTIONS

Like most computer modules, the DR11-W contains components which can be damaged by static
electricity. As long as the module remains inside its plastic bag, it is protected.
Outside of its protective plastic bag, the module should only be handled at an approved static-free
workstation. A wrist strap connected to earth ground through a safety resistor should be worn by the user
whenever handling the DR11-W.
2.4

SETUP

The DR11-W must be set up for each individual application. For each DR11-W module in the system, this
setup consists of:

Selecting the UNIBUS address of the registers.
Selecting the interrupt vector address.
Setting the E105 switches.
Setting the burst-size toggle switch.

2-1

Three other setups may or may not matter, depending upon the application:
e
e
e
2.4.1

Selecting the UNIBUS time-out value.
Sectting the burst release time-out value.
Selecting the UNIBUS interrupt priority.
Selecting the UNIBUS Address

Each DR11-W in the system contains six registers which the software uses to control the operation of the
DR11-W. Every DR11-W in the system must have a unique address for this group of registers and this
address must match the address expected by the software. This address is selected on each DR11-W
module by the E120 switchpack on that module. See Figure 1-3 for the location of E120.

The address of the DR11-W is actually the address of the first register in the group of six. The other
registers follow in ascending order. By convention, the first DR11-W in the system is assigned to UNIBUS
address 772 410. This is actually the address of the DR11-W word count register. For this DR11-W, the
bus address register is found at address 772 412, and so forth.

Table 2-1 documents the relationship between the E120 switches and the address assigned to the DR11-W.
Note that each switch selects one bit of the UNIBUS address that this particular DR11-W will respond to.
A switch set to OFF corresponds to a 1 in the UNIBUS address. The conventional settings for the first two
DR 11-Ws are also shown. Additional DR11-Ws are assigned addresses from the floating address space (as
shown in the PDP-11 and VAX-11 architecture handbooks).

Address Selection

Table 2-1
UNIBUS

Address Bit

E120 Switch
First DR11-W

(772 410)

Second DR11-W

(772 430)
Key:

2.4.2

On = Switch ON
= Switch OFF
~

Selecting the Interrupt Vector Address

Each DR11-W in the system also uses one unique address that contains a pointer to the interrupt service
routine for that DR11-W, if any exists. By convention, these vector addresses are also unique to each
DR 11-W, although it is not mandatory that they be so. Once again, this vector address must match that
expected by the software. The vector address is selected on each DR11-W module by the E15 switchpack
on that module. See Figure 1-3 for the location of E15.

Only the first DR11-W in the system is assigned a fixed vector address. By convention, it is UNIBUS
address 000 124. Any other DR11-Ws are assigned vectors from the floating vector space (also described
in the PDP-11 and VAX-11 architecture handbooks).

Table 2-2 documents the relationship between the E15 switches and the interrupt vector address assigned to
the DR11-W. Note that each switch selects one bit of the interrupt vector address assigned to the DR11-W.
A switch set to OFF corresponds to a 1 in the interrupt vector address. Switch 1 of the E15 switchpack is
used in link-mode applications. In link mode, switch 1 should be ON (closed); otherwise switch 1 should be
OFF (open).

Table 2-2

Interrupt Vector Address Selection

Interrupt
Vector

Address Bit

E15 Switch

First DR11-W
(000 124)

Key:

On = Switch ON
-

= Switch OFF

2.4.3 Setting the E105 Switchpack
The E105 switchpack selects three independent features:

e
®
®

The polarity of the BUSY signal.
Whether or not UNIBUS address bit (00) is suppressed.
Whether or not the error and information register is suppressed.

Each of these features is described on subsequent pages.

2.4.3.1 Selecting the Correct BUSY Signal — Three switches on the E105 switchpack select from three
different versions of the DR11-W BUSY signal. Figure 1-3 shows the location of E105 and Table 2-3 lists
the settings of switches S1, S2, and S3.
For connection to a user device, either the BUSY H or BUSY L signal can be selected, as required by the
particular user device.
For connection to another DR11-W, the BUSY L signal must be selected. Whenever the cable wraparound test is performed, the BUSY L signal setting must also be used.
Finally, special timing is required for the DR11-W to participate as one end of a DR11-W to DRV11-B, or
DR11-W to DRV11-W link. This special timing is provided by the third setting.
2.4.3.2 Setting UNIBUS Address Bit (00) Suppression — By itself, the DR11-W is capable of performing only word transfers on the UNIBUS. A small amount of additional logic within a user device
allows the DR11-W to transfer bytes on the UNIBUS.

2-3

Table 2-3

Busy Signal Selection

E105 switches

Busy Signal

Use

BUSY H

Off

Asserts the busy signal as a logic-high signal.

BUSY L

Off

Asserts the busy signal as a logic-low signal.

This setting is always used for DR11-W to
DR11-W links and cable wrap-around
testing.

D7 CYC INH(1) L

Off

Asserts the busy signal using the particular

timing required by the DRV11-B. This setting is always used for DR11-W to DRV11B or DRV11-W links.

Memories attached to the UNIBUS are always word-oriented. During UNIBUS DATOB (write byte)
operations, these memories use UNIBUS address line 00 (A00) to indicate which of the two bytes of the
memory word should be updated. During all other UNIBUS operations, AOO should be ignored by the
memory. A0O is directly supplied by the user device, not the DR11-W.

If you are using a memory which fails to ignore A0O for word operations, the AOO H input to the DR11-W
may be disabled by placing switch 4 of the E105 switchpack in the ON position. See Figure 1-3 for the
location of E105 and Table 2-4 for the switch settings. Normally, E105-4 is left in the OFF position.
Table 2-4

A00 Suppression

UNIBUS Address
Bit <00>

E105 Switch 4

Enabled
Forced to 0

Off
On

If you are running the cable wrap-around diagnostics, E105-4 must be in the OFF position.

If you are connecting your DR11-W as part of a DR11-W to DR11-W (or DRV11-B or DRV11-W) link,
you may leave E105-4 in either position. Placing the switch in the OFF position allows bus address bit (00)
to follow the status of the ready bit within the DR11-W at the far end of the link. This allows the program
at the near end of the link to tell whether the DR11-W at the far end of the link is ready simply by reading
BAR (00). Placing the switch in the ON position disables this indication.

2-4

2.4.3.3 Selecting Error and Information Register (EIR) Suppression — Certain older software packages
are not programmed to handle the error and information register of the DR11-W. Setting switch 5 of
E105 to OFF allows this register to be turned off (that is, it becomes invisible to the program). See Figure
1-3 for the location of E105 and Table 2-5 for the switch settings.

Table 2-5

Error and Information
Register Suppression

EIR

E105 Switch §

Suppressed
Enabled

Off
On

Operation with switch 5 off is loosely named DR 11-B mode, since the DR11-B does not contain an error

and information register. This position, however, does not provide exact software compatibility with the
DR 11-B.

Setting switch 5 on E105 to ON allows this register to be used by the program. This is named DR11-W
modes. It is recommended that all new software be developed to run in DR11-W mode.
Setting the Burst-Size Toggle Switch

2.4.4

Arbitrating for the use of the UNIBUS requires some finite time, so the UNIBUS specification allows a
device to transfer more than one word each time it becomes the UNIBUS master. Without additional
(external) logic, the DR11-W is capable of transferring one, two, or an unlimited number of words each
time it becomes the master of the UNIBUS. This is referred to as the burst size.

When the DR11-W is transferring one word per UNIBUS mastership, it is said to be operating in

one-cycle or non-burst mode.

When the DR11-W is transferring more than one word per UNIBUS mastership, it is said to be operating
in burst mode. The DR11-W internal logic implements two distinct types of burst mode:
e
e

Two-cycle burst mode (two transfers per UNIBUS mastership).
N-cycle burst mode (unlimited transfers per UNIBUS mastership).

The user device selects between burst and non-burst mode. If burst mode is selected, a toggle switch on the
DR 11-W further selects between two-cycle and n-cycle modes. See Figure 1-3 for the switch location and
Table 2-6 for the switch settings. Placing the switch handle towards the edge of the module selects twocycle burst. Placing the handle towards the middle of the module selects n-cycle burst.
NOTE
Allowing the DR11-W to transfer an unlimited number of words may lock out all other users of the
UNIBUS, so n-cycle mode is also known as bus hog
mode. For this reason, n-cycle bursts are not sup-

ported on the VAX-11/780, VAX-11/782, VAX11/785, VAX 8600, and VAX8650. However, ncycle bursts will operate under certain restricted
conditions (for example, if the DR11-W is the only
device connected to the UNIBUS adapter and the
UNIBUS).

Table 2-6

Burst Size Selection

Toggle

Burst Size

Switch Handle
Towards:

Two-Cycle
N-Cycle

2.4.5

Edge of board
Middle of board

Selecting the UNIBUS Time-Out Value

The UNIBUS is an asynchronous bus. This means that transactions on the UNIBUS are not synchronized
by any master clock. Within certain limits, a device can operate as quickly or as slowly as necessary.
All UNIBUS interfaces which perform direct memory access must contain a feature known as UNIBUS
slave-sync time-out. This feature sets the maximum time that the interface will wait for a slave device to
respond on the UNIBUS. Without it, accessing a non-existent device could stall the UNIBUS indefinitely.
The DR11-W allows you to select from three different values of slave-sync time-out. This is done by
optionally cutting out either capacitor C7 or capacitor C8. See Figure 1-3 for C7 and C8 locations and
Table 2-7 for their values. The DR11-W is shipped set to the longest setting (that is, both capacitors
installed). Normally, C8 should be removed (so as to use the shortest setting). Systems where the DR11-W
is connected to a VAXBI bus through a DWBUA require the middle setting. Finally, if the system makes
use of multiported memory, it may be necessary to select one of the longer time-out settings in order to
avoid a false indication of a non-existent memory (NXM) error.

If the three supplied settings do not provide a long enough time-out, you can add a larger capacitor to the
DR 11-W module, parallel with either C7 or C8.

2-6

Table 2-7

Slave Sync Time-out Selection

Timeout in

Microseconds

Used With

Nothing

Out

Most systems

Out

Out
In

VAXBI systems

Out

Multiport memory

NOTE
Use the shortest setting which provides error-free
operation.
If the system is a VAX-11/780, VAX-11/782,
VAX-11/785, VAX 8600, or VAX 8650 the timeout value must be less than 50 microseconds. Longer
values will cause the VAX UNIBUS adapter to
falsely report a hung UNIBUS.
2.4.6 Selecting the Burst Release Time-Out Value
The DR11-W is capable of transferring one, two, or n words each time it becomes the master of the
UNIBUS. This is referred to as the burst size.

Burst mode is used to increase the overall UNIBUS throughput. It is only effective if the user device can
deliver data rapidly (so that the UNIBUS does not sit idle while the DR11-W waits for the user’s data).

If the DR11-W has become the UNIBUS master and has transferred at least one word of a two- or n-cycle
burst, a timer is started. If the user device supplies the next word of data before the timer expires, the
timer is started again. If, however, the user device fails to supply the data and the timer expires, then the
DR11-W releases the UNIBUS.

This situation is harmless. The time-out ensures that the DR11-W does not continue to occupy the
UNIBUS if the user device fails or momentarily stalls.

The burst release timer is adjustable by means of a trimpot, R80. See Figure 1-3 for the'R80 location and
Table 2-8 for timing adjustments. The minimum setting of the timer is 4 microseconds while the
maximum setting is 30 microseconds. Like the slave-sync timer, additional capacitance can be added in
parallel with the timing capacitor (C9), if needed.
Both the PDP-11 and VAX-11 off-line diagnostic programs contain a specific routine used to adjust the
burst-release timer. For the VAX system, this is done using EVDRE Test 32. The correct command to

invoke the test is:

DS> STA/SEC:BURST
For the PDP-11 system, this is done using CZDRL routine BRSTDL, invoked by answering YES to the
question asking whether you wish to do burst data-late calibration.

2-7

In both cases, an oscilloscope should be connected to test point 1 (TP1). See Figure 1-3 for the location of
TP1. The burst release time is the time during which the TP1 waveform is logic-low. Figure 2-1 shows the
waveform viewed with an oscilloscope connected to TP1.

OSCILLOSCOPE

)
[
H BURST RELEASE TIME

_J
MKV86-0933

TP1
Figure 2-1

Burst Release Time Waveform

Selecting the UNIBUS Interrupt Priority

2.4.7

Every device on the UNIBUS that can generate interrupts has a specific interrupt priority level. The
overall priority scheme is described in the UNIBUS chapter of the PDP-11 Architecture Handbook. In
general, it is a combination of the device’s bus request level (BR level) and the device’s position along the
UNIBUS.

The specific BR level of the DR11-W is set by a jumper plug installed at E62. See Figure 1-3 for the
location of the BR plug. The DR11-W is shipped from the factory with a BRS plug installed. Other plugs
may be ordered and installed to select BR7, BR6, or BR4. BR7 is the highest priority; BR4 is the lowest
priority (see Table 2-9).

2.5

INSTALLATION AND CHECKOUT

Once the module setup is complete, the DR11-W may be installed in the system. Before installing, check
that:

A hex SPC slot is available in which to mount the module.

At least 3.7 A of +5 Vdc are available from the power supply powering that SPC slot.

The NPG jumper wire has been removed from backplane pins CA1 and CBI1 of that slot. This

The grant continuity card (G727, G7270, or G7273) has been removed from that slot.

is usually a short blue wire. It may already have been removed.

The system that you are installing the DR11-W in may or may not be FCC compliant. (The United States
Federal Communications Commision has established rules and regulations regarding the amount of radio
and television interference which a computer may legally emit.) The installation of the DR11-W into your

system varies depending upon whether or not your system is FCC compliant.
2-8

Table 2-8

Burst Release Timer
Adjustment

Timer

(Microseconds)

R80 Position

4
30

Fully CCW
Fully CW

Table 2-9

BR Level Plug Part Numbers

Plug Part

Other Devices
Normally at

BR Level

Number

This Level

BR7

54-08782

None

BR6

54-08780

Real-time clocks

BRS (standard)

54-08778

Disks, tapes,

BR4

54-08776

multi-line
synchronous comm

2-9

Single-line

asynchronous comm,
printers

2.5.1

Installing the DR11-W in a Compliant System

If your system is already FCC compliant, you must install the DR11-W in such a fashion so as to maintain
this compliance. This is done by routing the DR11-W user cables through a bulkhead panel at the rear of
the mounting cabinet (see Figure 2-2). This bulkhead panel filters the DR11-W signal lines in order to
contain the high frequencies within the computer cabinet. The bulkhead connector also provides a more
convenient place to connect the user cables, resulting in a neater, more maintainable installation.
The interface presented at the outside of the bulkhead panel is identical to the interface presented at the
DR 11-W module itself.

,\ DR11-W CABLES

(NOTE RED STRIPE)

—

fi\frfi\\

% g\
L

DR11-W CABLES
’1

(NO

TE RED STRIPE

) TRANSITION CABLES

—

BULKHEAD

BA11-A

BOX

(TYPICAL)

RED STRIPE

/o
i

—
0

CABLE TO J1

H9642

PANEL

CABLE TO J2

CABINET
MKV86-0957

Figure 2-2

2.5.2

Installing the DR11-W in an FCC-Compliant System (Showing a
PDP-11/24 or a PDP-11/44 and a BA11-A Box in an H9642 Cabinet)

Mounting the Bulkhead in the Existing Picture Frame
Locate an unused opening in the picture frame. Remove the screws which hold the cover plate in place,
then remove the cover plate itself.

Ensure that both the picture frame opening and the bulkhead connector that you are about to install are
each clean and free of corrosion.

Dress the BC06-R cables (which connect to the DR11-W) out through the opening in the picture frame.
Connect each cable to an adapter (part number 70-21988), then connect the adapter to one of the
connectors in the bulkhead panel.

When you have connected both cables and adapters to the bulkhead panel, and have verified that the
connections are correct and secure, place the bulkhead panel in the opening and install and tighten
the mounting screw. Ensure that the screws are tight (so that the best possible ground connection is made).
2.5.3
Installing the DR11-W in a Non-Compliant System
If your system is not FCC compliant, you can still take advantage of the convenience gained by use of the
bulkhead panel (see Figure 2-3). In this case, the system may not already contain the picture frame which
holds the bulkhead panels. Figure 2-3 shows the use of a single-hole picture frame which allows the
bulkhead to be mounted. This does not make the system FCC-compliant.

[ oo

[;]El

H9642

—cammer

871-C POWER

@@ ©00

0O @A//CONTROLLER

mIm

@ (9 6 6D

MKV86-0958

Figure 2-3

Installing the DR11-W in a Non-Compliant System

(H9642 Cabinet, 871-C Power Controller, and
Add-On Picture Frame)

Once again, the interface presented at the outside of the bulkhead panel is identical to the interface

presented at the DR11-W module itself.
2.5.4

Installation Without the Bulkhead Panel

It is also possible to install the DR11-W without using the bulkhead panel. In this case, the cables are run

directly from the connectors on the DR11-W module to the user device (see Figure 2-4).
This is only possible if your system is exempt from the FCC regulations.

2-11

REAR OF PDP-11/44/24

|~ BAT1-A BOX

/ H9642 CABINET

')E |

USER DEVICE IN
SAME CABINET

871-C

|_—" POWER CONTROLLER
/

@@
@@

@EMO
DEEO

MKV86-0959

Figure 2-4

2.6

Installing the DR11-W Without the Bulkhead Panel
(H9642 Cabinet, 871-C Power Controller, and User Device)

CABLE WRAP-AROUND TESTING

This testing essentially verifies all of the logic in the DR11-W. It should be performed upon initial
installation and anytime the results of the logic wrap-around test are inconclusive.
If the cable wrap-around test is not to be performed, go to Section 2.9.

2-12

During this test, the user cables are disconnected from the DR11-W and a single cable is connected from
the output connector on the DR11-W back to the input connector (see Figure 2-5). This covers the
remainder of the DR11-W logic not tested in the logic wrap-around mode (primarily, the user-input
receivers). This test also provides a convenient method of testing the user cables. Just connect them, one at
a time, as the wrap-around cable.

If you are using the recommended BCO6-R flat gray cables, be sure that the color stripe is oriented
towards the module handle at both connectors. If you are using a short, unshielded cable (like the
BCO05-L), the cable orientation is unimportant so long as there are no twists in the cable.

____A4h

t~—a AN

="
J1

DO 00
H

DI 00
H

< &
J2

|
MKV86-0927

Figure 2-5

Cable Wrap-Around Testing Configuration

The DR11-W performs the cable wrap-around test by connecting the data from the output connector to

the input connector. Figure 2-5 shows how one bit (D00 H) is connected. All data bits (DOO H through
D15 H) and control signals are similarly connected. This connection method provides maximum diagnostic

coverage, including input receivers untested by the logic wrap-around test.
To perform the test:

Unplug the external cables from the two user connectors on the DR11-W.
NOTE

If the DR11-W is installed in a system using the
FCC bulkhead, and you desire to test the cables
between the DR11-W and the bulkhead, then unplug
the user cables at the outside of the bulkhead rather
than at the DR11-W module itself.

Plug the maintenance wrap-around cable into both user connectors on the DR11-W or the FCC
bulkhead. If the cable has a colored stripe, ensure that the stripe is facing the module handle.
For the FCC bulkhead, ensure that the colored stripe is facing upwards or rightwards.

Record the current settings of E105 switches 1, 2, 3, 4, and 5.

2-13

- o

Set the E105 switches:
-

(Carefully plug the DR11-W into the desired slot.

Apply power to the system and run the appropriate stand-alone diagnostic program:

—
—

2.7

1 to OFF
2to ON
3 to OFF
4 to OFF
5 to ON

ESDRE for the VAX-11 family
CZDRL for the PDP-11 family

If desired, perform the burst release time-out adjustment as directed by the diagnostic.

Remove power from the system.

Reset the E105 switchpack to the original settings.

LOGIC WRAP-AROUND TESTING

This testing verifies most of the logic in the DR11-W, excluding only a few user-interface drivers and
receivers. It should be performed upon initial installation and anytime the operation of the DR11-W is in
doubt.
With no cables attached to the DR11-W, the diagnostic internally disconnects the user inputs, connects the
user outputs back to the user inputs, and runs the appropriate tests (see Figure 2-6).
The DR11-W performs the logical loopback by sampling the data appearing at the ouput connector (J1) of
the DR11-W. Figure 2-6 shows how one bit (D00 H) is connected. All data bits (D00 H through D15 H)
and the busy signal are similarly connected. This connection scheme was chosen to get maximum
diagnostic coverage, up to and including the output drivers.
However, this connection scheme also means that if the user cables are left connected to the DR11-W,
they may cause the diagnostic to fail if: the user cable is shorted, the user cable is excessively capacitive, or
the user device is forcing the outputs to one state or the other.
CAUTION
Since the output signals are still driven while running
the logic wrap-around test, the DR11-W produces
unpredictable signals at the user connectors. You
must take care that these signals do not cause dam-

age to the user device (by commanding illegal or
destructive operations, etc). It is recommended that
the user device be disconnected during any DR11-W
testing.

DO 00 H

> J2

DI 00 H

MKV86-0928

Figure 2-6

Logic Wrap-Around Testing Configuration

To perform the test:
®

Disable, power-down, or disconnect the user device. See the caution above.

Apply power to the system and run the appropriate diagnostic program:
-

ESDRE for the VAX-11 family running stand-alone

—
-

CZDRL for the PDP-11 family

ESDRB for the VAX-11 family running on-line

2.8 LINK-MODE TESTING
Additional diagnostics must be run on DR11-W links. If you are not using your DR11-W as part of a link,
go to section 2.9,

When testing a DR11-W to DR11-W (or DR11-W to DRV11-B) link, each DR11 should first be
individually tested. When each has individually passed, the two DR11s may be tested together as a link.
Both ends of the link must be running cooperating saftware (such as ESDRE or CZDRK). Using DEC
diagnostics, the link is cabled normally. One end is started as the slave, then the other end is started as the
master (these definitions basically describe who speaks first; the definitions are exchanged at the end of
each pass of the diagnostic). The full functionality of the link is tested. Figure 2-7 illustrates how one data
bit is connected in each direction, forming a full link.
NOTE
If any of the tests report the dropping of data bit

(15), suspect that either or both BC06-R cables are
installed with the colored-stripe away from the module handle. This attempts to drive the cable’s ground

plane as bit (15). The ground plane is capacitive,
and as result, bit (15) is slow. This causes it to be
lost during high-speed transfers.

2-15

M-1143a Z#
ir

L= |% NV YV V¥
Lr

LA-1#HQ

2-16

2.9

FINAL INSTALLATION

Once the DR 11-W has been diagnosed as error free, you may perform the final installation of the module.
e

Ensure that the E105 settings are correct.

Connect the user or link cables. If the cables have a colored stripe, be sure that the stripe faces
the module handle.

Install the DR11-W in the desired slot.

Apply power to the system and test the application, using your software.

CHAPTER 3
USER DEVICE INTERFACING

3.1

INTRODUCTION

This chapter describes the hardware interface between the DR11-W and your device. The case of a
DR11-W linked to another DR11-type device is covered separately in Chapter 5.

3.2 PHYSICAL
All connections to your device are made through the two 40-pin connectors mounted on the DR11-W

module.

‘

If your system is FCC compliant, then the two connectors of the DR11-W are exactly duplicated at the
bulkhead mounted at the rear of the cabinet.
3.3 ELECTRICAL
All user signals are received using standard UNIBUS receivers and are transmitted using standard
UNIBUS open-collector drivers. All signals are terminated at the DR11-W module into 120 ohms and
+3.3 Vdc (that is, the Thevenin resistance and voltage is 120 ohms and +3.3 Vdc). In order to minimize
reflections, noise, and crosstalk, the signals should be connected to the user device using 120 ohm cable.
The user device should use the same receivers, drivers, and terminators as are used on the DR11-W.
3.3.1

Output Circuit

Figure 3-1 illustrates a typical DR11-W output circuit. The driver used is an 8881 open-collector UNIBUS
driver. Early DR11-Ws terminated each line with a pair of discrete resistors (as shown); more recent

DR 11-Ws use hybrid terminators. The user device should receive DR11-W output signals with a UNIBUS
receiver: either an 8640 quad receiver chip or an 8641 quad transceiver (with the transmitter section
disabled).
3.3.2

Input Circuit
Figure 3-2 illustrates a typical DR11-W input circuit. The receiver used is an 8640 low-leakage UNIBUS
receiver. As in the output circuits, early DR11-Ws terminated each line with a pair of discrete resistors (as
shown); more recent DR11-Ws use hybrid terminators. The user device should drive DR11-W input
signals with a UNIBUS driver: either an 8881 quad driver chip or an 8641 quad transceiver.

3.3.3 Terminators
The terminators on the DR11-W module ensure that any input left completely unconnected is seen as a
clean logic-high. However, this cannot be guaranteed if the line is run through the user cables and left
unconnected and unterminated at the user device. An undriven, unterminated line is susceptible to the
pickup of noise and crosstalk (see Figure 3-3).
3.3.4

Cable Characteristics

In order to minimize reflections, crosStalk, and noise pickup, the DR11-W user interface signals should be
transmitted using cables with a characteristic impedance of 120 ohms to ground.

3-1

+5 VDC

180 OHMS

USER CONNECTOR

390 OHMS

DEC 8881

UNIBUS DRIVER
MKV86-0950

Figure 3-1

Typical DR11-W Output Circuit Diagram

+5 VDC

180 OHMS

USER CONNECTOR
390 OHMS

DEC 8640

UNIBUS RECEIVER
MKV86-0926

Figure 3-2

Typical DR11-W Input Circuit Diagram

3-2

[

M
1

BAD - CONNECTED BUT NOT
TERMINATED

[

GOOD - CONNECTED AND

TERMINATED

[

BEST - NOT CONNECTED
AT ALL
MKV86-0951

Figure 3-3

Unused Input Configurations

3-3

BC06-R flat grey MASSBUS cables meet this requirement and are available from Digital Equipment
Corporation in a wide variety of lengths. You can also assemble your own custom cables using equivalent
raw cable stock. Table 3-1 lists a few vendors and their part numbers for equivalent raw stock. All cables
listed in Table 3-1 are AWM UL Style 2682.
NOTE
All of the cables listed in Table 3-1 contain an integral ground plane. This ground plane must connect
to pin A on each of the DR11-W user connectors.

If cables other than those listed above are used, their characteristic impedance must be specified or
measured to ensure best performance.
3.3.5 Logic Levels
Correct dc logic levels are essential for the correct operation of the DR11-W. Table 3-2 documents the
logic level limits for both the drivers and receivers.
‘

Table 3-1

Cable Stock

Part Numbers

Cable Stock
Vendor

Part Number

DIGITAL

17-00034-00

Tensolite
Spectrastrip
3iM

81-25-00-4000
N/A
N/A

Brand Rex

N/A

Table 3-2

Logic Voltage Level Requirements

Parameter

Value

For drivers:

Volts maximum

0.7 Vdc @ 70 mA!

[oh maximum

25 uA @ 5 Vdc

For receivers:
Vil range

0.0 to 1.3 Vdc

Vih range
Iih max

80 uA

1.7 to 5.0 Vdc

INewer drivers also achieve 0.9 Vdc @ 100 mA

3-4

3.3.6 Logic Polarity
All inputs and outputs from the DR11-W are logic-high (that is, asserted when near +3 Vdc) except
BUSY and BURST RQ L. The polarity of the busy signal is switch-selectable.
Since BURST RQ L is a logic-low signal, if no connection is made to this pin, then the DR 11-W operates
in non-burst mode. If the signal is hard grounded, then the DR11-W operates in two-cycle or n-cycle burst
mode. Of course, like any other input signal, the user device can dynamically drive this pin.
3.3.7 Logic Reference
The DR11-W uses single-ended drivers and receivers. It is imperative for both the safety and proper
operation of the equipment that the user device be at the same logic reference level (ground) as the
DR11-W. More than a few millivolts of ground potential can cause improper operation. More than a few
hundred millivolts can damage the equipment.
One way to ensure that the DR11-W and the user device share the same logic reference is to mount the
user device and the DR11-W in the same cabinet, referenced to the same ground. It is recommended that

the user device always be mounted in the same cabinet (or the same series of cabinets bolted together) as
the DR11-W.
If the user device is mounted in a cabinet separate from the DR11-W, a solid logic reference must be
provided. This may be accomplished by connecting the cabinet frames together with copper cable of
number two gauge or larger. This is similar to the technique used with the MASSBUS (a differential bus).
Digital Equipment Corporation Computer Special Systems sells an adapter module (DR11-WC/WD)

which converts the DR11-W’s single-ended signals to differential signals. This adapter module can be used
in difficult cases of ground noise and ground potential.
3.3.8 Transmission Distance
The UNIBUS drivers and receivers used in the DR11-W are specified for a maximum transmission
distance of 15.25 m (50.0 ft). This distance includes all cabling, including the cable used between the
DR11-W module and the FCC bulkhead. This limitation is imposed both by the maximum allowable dc
voltage drop in the signal cables and by the maximum allowable signal skews.

As the signals propagate through the conductors of the cable, the resistance of the cable causes a loss of

voltage (known as an IR drop). This voltage loss subtracts from the available noise margin. When an
insufficient noise margin remains, transmission errors can occur.
Also, all signals in the two user cables do not propagate at exactly the same speed. The difference in arrival
time between any two signals is referred to as skew. The DR11-W DMA engine accounts for a limited
amount of skew by providing deskew time at the beginning of each transfer. If the skew in the data signals
exceeds this deskew time, errors will occur. Increasing the deskew time reduces the maximum transfer rate
of the DR11-W.
Neither of these limits is a hard and fast rule — bigger conductors in the cable can reduce IR losses while
additional logic in the user device can accommodate additional skew. However, this is clearly a case where
you must understand the rules before violating them.
The Computer Special Systems differential driver module (DR11-WC/WD) can be useful in extending
the transmission distance of the DR11-W. The differential transmission technique used combined with
increased deskew times allows distances of at least 300 m (1000 ft).

3-5

3.4

DATA FORMAT

The UNIBUS is a bus with 16 data lines and 18 address lines. The address space (as viewed from the
UNIBUS) may be viewed as a linear series of 262144 (256K) bytes, each with its own unique address (see
Figure 3-4). Addresses on the UNIBUS are always the address of a particular byte.

000007
000006

000005

000004

000003
000002
000001

000000
MKV86-0912

Figure 3-4

The UNIBUS Address Space Map
for a Series of 8-Bit Bytes

The address space may also be viewed as a series of 131072 (128K) words, each composed of two bytes
(see Figure 3-5). The address of the word can be specified by the address of either byte in the word, but the
convention chosen for the UNIBUS is to use the address of the less significant byte. This means that for all
word accesses on the UNIBUS, address bit (00) is equal to zero (A00=0). This use of address bit (00) leads
to the less significant byte being referred to as the even byte (A00=0) while the more significant byte is
referred to as the odd byte (A00=1).

000017

000016

000015

000014

000013

000012

000011

000010

000007

000006

000005

000004

000003

000002

000001

000000
MKV86-0911

Figure 3-5

UNIBUS Address Space Map
for a Series of 16-bit Words

Address bits on the UNIBUS are numbered from right to left in order of increasing significance (sce
Figure 3-6). The address bits are named AQO through A17. Remember, the address presented on the
UNIBUS is always the address of a byte of memory.

In the DR11-W, address bits (17) through (01) are supplied by the software program via the control and
status register (CSR) and the bus address register (BAR), while address bit (00) is provided by the user
device via the A0O H input line.

Data bits on the UNIBUS are numbered from right to left in order of increasing significance. The data
bits are named D00 through D15 (see Figure 3-7).

A UNIBUS data word can also be construed as representing two bytes (see Figure 3-8). When interpreting
the data in this fashion, the bytes appear exactly as pictured in Figure 3-5. Data from bytes at even
addresses (that is, with address bit (00)=0) always appears on data lines 07-00. Data from bytes at odd
addresses (that is, with address bit (00)=1) always appears on data lines 15-08. Odd byte data never
appears on D0O7-DO00.

This representation of words and bytes allows for the easy processing of both, without much specialized
hardware. Further discussion may be found in Section 3.12.

)

FROM CSR

FROM BAR

FROM AOO H
MKV86-0924

Figure 3-6

Eighteen-Bit UNIBUS Address Configuration

MKV86-0901

Figure 3-7

UNIBUS Data Interpreted as a Word

DATA FROM THE EVEN BYTE
(LE., AOO=0)

DATA FROM THE ODD BYTE
(LE., AOO=1)

MKV86-0902

Figure 3-8

UNIBUS Data Interpreted as Two Bytes

3-7

3.5

DIRECTION OF DATAFLOW DURING PROGRAMMED 1/0
During programmed I/O operations (or, by extension, interrupt-driven 1/0), the processor is entirely in
control of the data transfer (that is, the processor is the UNIBUS master) and the direction of dataflow is
intuitive (see Figures 3-9 and 3-10). When the processor writes to the output data buffer, data appears on
the data out wires and is presented to the user device. When the processor reads from the input data
buffer, data from the user device is sampled from the data in wires.

DATAQUT TO
DATA DEVICE

UNIBUS
PROCESSOR
WRITES

ODR

DR11-W

PROCESSOR

Figure 3-9

MKV86-0955

Processor Writing Output Data Register Diagram

DATA IN FROM
USER DEVICE

UNIBUS

PROCESSOR

READS
IDR

DR11-W

PROCESSOR
MKV86-0956

Figure 3-10

Processor Reading Input Data Register Diagram

3-8

3.6 DIRECTION OF DATAFLOW DURING DIRECT MEMORY ACCESS (DMA) 1I/0
During DMA I/0O operations, the processor is not involved. Now, the DR11-W is the UNIBUS master and
directly controls main memory (see Figures 3-11 and 3-12). The DR11-W has two ports — the UNIBUS
port and the user port. While data is flowing in one port, it must be flowing out the other. This can lead to
confusion in the naming of the dataflow direction. The direction of dataflow is always stated with regards
to the DR11-W’s UNIBUS port.

When data is flowing from memory to the user device, the data flows from memory in to the DR11-W’s
UNIBUS port, and then from the DR11-W’s user port out to the user device. The operation that the
DR 11-W performs as the UNIBUS master is referred to as a data-in or DATI. This is the reverse of what
intuition (and the programmed I/O case) would suggest.

When data is flowing from the user device to memory, the data flows from the user device in to the

DR11-W’s user port, and then from the DR11-W’s UNIBUS port out to memory. The operation that
the DR11-W performs as the UNIBUS master is referred to as a data-out or DATO.

Table 3-3 summarizes this description. Note that the table only makes reference to DATI and DATO. The
DR11-W actually implements two additional operations: DATIP and DATOB. DATIP (data-in, pause) is

a variant of DATI while DATOB (data-out, byte) is a variant of DATO.

DATAQGUTTO
USER DEVICE

MEMORY

UNIBUS

DR11-W
MKV86-0972

Figure 3-11

Data from Memory to User (DATI) Diagram

3-9

ouT

MEMORY

DATA IN FROM
USER DEVICE

UNIBUS

DR11-W
MKV86-0973

Figure 3-12

Data from User to Memory (DATO) Diagram

Table 3-3

DMA Data flow
Directions

Direction of

Operation

Data flow

Name

From memory

to user device

DATI

From user device
to memory

DATO

3-10

3.7 INPUT SIGNAL FUNCTIONAL DESCRIPTION
The DR11-W takes 28 signals as inputs from the user device. They are listed in Table 3-4 and subsequent-

ly described in detail.

Table 3-4
Signal Name

DR11-W User Input Signals

Function

DI 00 H

J2-UU

Input data bit (00)

DI 01 H

J2-SS

Input data bit (01)

DI 02 H

J2-PP

Input data bit (02)

DI 03 H

J2-MM

Input data bit (03)

DI 04 H

J2-KK

Input data bit (04)

DI 05 H

J2-HH

Input data bit (05)

DI 06 H

J2-EE

Input data bit (06)

DI 07 H

J2-CC

Input data bit (07)

DI 08 H

J2-DD

Input data bit (08)

Data inputs:

DI 09 H

J2-FF

Input data bit (09)

DI 10 H

J2-JJ

Input data bit (10)

DI 11 H

J2-LL

Input data bit (11)

DI 12 H

J2-NN

Input data bit (12)

DI 13 H

J2-RR

Input data bit (13)

DI 14 H

J2-TT

Input data bit (14)

DI 15 H

J2-VV

Input data bit (15)

J1-L
JI-R
JI-T,

User device status bit (1)
User device status bit (2)
User device status bit (3)

Status Inputs:

STATUS A H
STATUS B H
STATUS C H

J1-

Bus Control:

CYCLERQ AH
CYCLE RQ BH
BURST RQ L
CO CNTL H.
Cl1 CNTL H
AQ00 H
BA INC ENB H
WC INC ENB H

J1-B
J1-Z
J1-K
J2-N
J2-T
J2-F
J2-J
J1-J

DMA cycle start signal A
DMA cycle start signal B
Use burst mode
UNIBUS cycle selection
UNIBUS cycle selection
Low-order UNIBUS address bit
Allow bus address register to increment
Allow word count register to increment

J2-D

Interrupt the processor

Interrupt:

ATTN H

Most of the input signals are connected to the DR11-W via J2. The rest are connected via J1. Figure 1-3
shows the physical location of the two connectors and Figure 3-13 the individual pins and their designations for each connector.

VvV /-——PO O=-—— U
00

\AY) uu

O 0
O 0

NN
LL

MM
KK

O 0
O
o o0

JJ
FF
DD

(o Je]

[oJe)
(o Jie)

X
Vv

[oJie)

O 0
(o BN e)
0O 0

R
N
L

P
M
K

0 0
00

F
D

E
C

B —mm»
0 O0ew————
A

EE
AA

MKV86-0935

Figure 3-13

3.7.1

J1 and J2 Connector Pin Identification

Data Inputs

These 16 lines supply data to the DR11-W. They are logic-high lines. They are sampled and latched into
the DR11-W each time the input data register is read, and approximately 200 nanoseconds after the rising
edge of either CYCLE RQ A H or CYCLE RQ B H. Data must be stable at those times in order to be
correctly read. Refer to Section 3.4.
3.7.2

Status Inputs

These three lines are used as general purpose inputs to the DR11-W, and can be read by the program at

any time. They are sampled and latched into the DR11-W each time the control and status register is read,
and approximately 200 nanoseconds after the rising edge of either CYCLE RQ A H or CYCLE RQ B H.
Data must be stable at those times in order to be correctly read. Whatever presented at these inputs is
immediately visible in the control and status register, regardless of the state of the DR11-W.

A common use of these lines is for handshaking between the user device and the software. They can also

be used to provide the software with the status of the user device.
3.7.3

Bus Control

These signals are all used to initiate and control the DMA cycles performed by the DR11-W. All of these
signals (except CYCLE RQ A H and CYCLE RQ B H) are latched into the DR11-W approximately 200

nanoseconds after the rising edge of CYCLE RQ A H or CYCLE RQ B H.
3-12

If the software has set up a DMA transfer, then the rising edge of either CYCLE RQ A H or CYCLE RQ
B H sets the cycle flip-flop, starting a DMA cycle (assuming that the other input is deasserted and that the
cycle flip-flop is not already set). The busy flip-flop is also set at this time. Since both CYCLE RQAH
and CYCLE RQ B H perform identical functions, throughout this manual they are frequently referred to
collectively as CYCLE RQ x H (that is, either CYCLE RQ A H or CYCLE RQ B H).

CO CNTL H and C1 CNTL H select the type of UNIBUS cycle to be performed (see Table 3-5). These

signals must be driven by the user device or hard-wired to the desired logic state.

Table 3-5

ClH

COH

0
1
0
1

0
1

UNIBUS Cycle Selection

Cycle
Name

Description of Cycle

DATI
DATIP
DATO

DATOB

Read word or byte from memory
Read with write intent
Write word to memory
Write byte to memory

BURST RQ L is used to determine whether this cycle should be performed in burst or non-burst mode.
A00 H is used during DATOB (write byte) cycles as the least significant bit of the UNIBUS address. It
determines which of the two bytes of the UNIBUS data word should be written. For read operations, word
writes, and writes to even byte addresses, AOO H must remain unasserted. Only during writes to odd byte
addresses should A0OO be asserted by the user device.
BA INC ENB H controls whether or not the.bus address register is incremented at the completion of the
present DMA cycle. This signal is normally asserted (high), allowing the bus address register to increment

with each transfer. If the cycle is a DATIP (read with write intent) or a DATOB (write byte) to the low
byte of the word, then the bus address register should remain unchanged until after the next cycle. In this
case, the user device should deassert BA INC ENB H by pulling it to ground.
WC INC ENB H performs the same function for the word count register. In the case of DATOB,
however, it may be more convenient to treat the word count register as a byte count register. In this case,
the register can be allowed to increment with every transfer.
More details on the use of A00 H, BA INC ENB H, and WC INC ENB H can be found in Section 3.12.

3.7.4 Interrupt
‘
The rising edge of ATTN H causes the attention interrupt flip-flop in the DR11-W to be set. No further
DMA cycles are started and the DR11-W becomes ready and interrupts the processor if the interrupt
enable flip-flop is set.
;
-

This signal also sets the attention flip-flop. This flip-flop holds the attention indication for display in the
control and status register.

3-13

3.8

OUTPUT SIGNAL FUNCTIONAL DESCRIPTION

The DR11-W provides 25 signals as outputs to the user device. They are listed in Table 3-6 and
subsequently described in detail.

Table 3-6

Signal Name

DR11-W User Qutput Signals

Function

J1-UU
J1-SS
J1-PP
J1-MM
J1-KK
J1-HH
J1-EE
J1-CC
J1-DD
J1-FF
J1-JJ
JI1-LL
JI-NN
J1I-RR
JI-TT
J1-VV

Output data bit (00)
Output data bit (01)
Output data bit (02)
Output data bit (03)
Output data bit (04)
Output data bit (05)
Output data bit (06)
Output data bit (07)
Output data bit (08)
Output data bit (09)
Output data bit (10)
Output data bit (11)
Output data bit (12)
Output data bit (13)
Output data bit (14)
Output data bit (15)

J2-V
J2-R
J2-K,

User device command bit (1)
User device command bit (2)
User device command bit (3)

Data Outputs:

DO 00 H
DO 01 H
DO 02 H
DO 03 H
DO 04 H
DO 05 H
DO 06 H
DO 07 H
DO 08 H
DO 09 H
DO 10 H
DO 11 H
DO 12 H
DO 13 H
DO 14 H
DO 15 H
Function Outputs:

FNCT 1 H
FNCT 2 H
FNCT 3 H

J2-L

Bus Control:

END CYCLE H

BUSY

J1-X

DMA cycle about to end

J1-D
J1-N

FNCT 2 or’d with UNIBUS AC LO
The DR11-W is being initialized
The DR11-W is ready
The DR11-W go bit was just set

DMA cycle in progress

J2-B

Miscellaneous:

UACLO FNCT 2 H
INIT H
READY H
Go H

J1-F
J2-X

3-14

Most of the output signals are connected from the DR11-W via J1. The rest are connected via J2. Figure
1-3 shows the physical location of the two connectors while Figure 3-13 shows the individual pins on each
connector.

3.8.1

Data Outputs

These 16 lines supply data to the user device. They are logic-high lines. They are driven from latches

which are loaded each time the output data register is written or whenever a DMA read is finished. Refer
to Section 3.4.
3.8.2

Function Outputs

These three lines are used as general purpose outputs from the DR11-W and can be set by the program at
any time. Whatever is written into the control and status register function bits is immediately visible at the
function outputs.
:
A common use of these lines is for handshaking between the user device and the software. They can also
be used to provide functional commands to the user device.
3.8.3

Bus Control

END CYCLE H is a pulse which occurs just prior to the clearing of the DR11-W busy signal. Fast user

devices can use this signal as a warning that the next word of data must shortly be presented to the DR11W, or taken from the DR11-W. Slower user devices need not use the END CYCLE H signal.
BUSY is a level which indicates that a single DMA cycle is ongoing. The polarity of the busy signal is
selected via the E105 switchpack. BUSY asserts when the cycle flip-flop is set; BUSY deasserts when the
DMA cycle is completed. There is one complete cycle of the busy signal for each DMA transfer,
regardless of the burst mode used. That is, the transfer of each word or byte is accompanied by a complete
cycle of the busy signal.

3.8.4 Miscellaneous
UACLO FNCT 2 H is the logical OR of two signals: FNCT 2 H and UNIBUS ACLO. UNIBUS ACLO
is the UNIBUS signal which indicates an impending power failure. Therefore, UACLO FNCT 2 H is
asserted anytime that FNCT 2 is asserted or there is an impending power failure on the UNIBUS.
INIT H is asserted anytime the DR11-W is initialized. This can occur whenever UNIBUS INIT is
asserted, or whenever the DR11-W maintenance flip-flop is cleared. This output may be used to signal that
the user device should also be initialized, or to indicate to intelligent user devices that the logical
connection with the processor should be re-established.

READY H is derived from the DR11-W ready flip-flop. This signal is asserted whenever the DMA engine
of the DR11-W is idle (that is, asserting CYCLE RQ A H or CYCLE RQ B H does not start a transfer).

GO H is a 160 nanosecond pulse indicating that the DR11-W’s DMA engine has just been armed.
Simultaneously, READY H deasserts. Subsequent assertions of CYCLE RQ x H start a transfer.
3.9

DMA CYCLES IN GENERAL

The software must set up each block of DR11-W DMA cycles. This procedure is described in detail in

Chapter 4. Once the go bit has been set, the DR11-W is ready to transfer data.
The fact that the go bit has been set is indicated to the user device in two ways. The ready line deasserts

(ready is actually an indication to the software that the DR11-W is ready to accept the next software
command). The go line also asserts for 160 nanoseconds.

3-15

Now, the user device controls the operation of the DR11-W. Each time the user device asserts either
CYCLE RQ x H line, the DR11-W performs one DMA cycle. The type of DMA cycle (DATI, DATIP,
DATO, or DATOB) is selected by the user device. The CPU does not control the direction of the data
transfer.

As each DMA cycle begins, the DR11-W asserts the busy signal. This indicates that the DMA cycle is
ongoing. Near the completion of the DMA cycle, END CYCLE H pulses. Shortly after that, BUSY
deasserts, indicating that the DR11-W has completed the DMA cycle.

If the DR11-W is not yet ready (for the next software command), then another DMA cycle can be started
using either CYCLE RQ x H input.

Each DMA cycle (except for a DATIP cycle) is independent of any other cycle. That is to say, the user
device can freely intermix read cycles, write word cycles, and write byte cycles (although mixing cycle
types within a block is not normally done).

DATIP (read with write intent) leaves the selected memory bank locked up. Only a DATO or DATOB
(write word or write byte) to the same address can unlock the memory bank. Therefore, each DATIP must
be followed by a DATO or DATOB to the same address as the DATIP.

3.10

A SINGLE CYCLE IN DETAIL

Assume that the DR11-W has been started by the software: the READY H line is deasserted and the GO
H pulse has been seen.

Refer to Figure 3-14. The user device must set up the following lines:
e
e

COCNTLH
CICNTLH

In addition, if the transfer is writing a word to memory, the data inputs must also be set up:
e

DI 15 H to DI 00 H (assuming this transfer writes memory)

Finally, if any of the following lines are in use, they must be set up as well:
A00 CNTL H
WC INC ENB H
BA INC ENB H
BURST RQ L

3-16

LOGICAL
WRAP-AROUND
MULTIPLEXER

CO CNTL H ——
C1 CNTL H ———»]

WC INC ENB H ————»

LATCHES

BA INC ENB H —TM
AOO H —

DIOO
H

———» D10 CO CNTL
H
——»

DI 16 H

D10 C1 CNTL
H

L
» D10 WWC INC ENB H
— D10 WBA INC ENB H

—— D10 WAOO H

D4 WDI 00 H

D4 WD

LOGICAL

WRAP-AROUND

15 H

SIGNALS

D10 MAINTA (0) H
D7 NPR RQ(1) H

MKV86-0936

Figure 3-14

DR11-W Input MUX and Latch Block Diagram

Once these lines have been correctly set up (asserted or not asserted), then the user device should assert
one of the two CYCLE RQ x H lines (see Figure 3-15). The other CYCLE RQ x H line must be held
unasserted. Both lines perform identically and either may be used.

3-17

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READ L OR DIO WCI CNTL H

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MKV86-0929

Figure 3-15

Cycle and Busy Logic Diagram

The DR11-W logic then allows approximately 200 nanoseconds for the deskew of all of the inputs
mentioned above. The cycle flip-flop is then set and the DMA cycle starts (see Figures 3-16 and 3-17).
CYCLE RQ x H need not be held until this occurs, but a minimum pulse width of 125 nanoseconds is
recommended. There is no maximum time limit on CYCLE RQ x H (other than the fact that it must be
deasserted before it can be reasserted).

CYCLE RQ x H also sets the busy flip-flop, driving the busy signal. This sigrial stays asserted until the
DR 11-W is ready to accept the next assertion of CYCLE RQ x H.

All of the user inputs mentioned above are latched approximately 200 nanoseconds after CYCLE RQ x H
has been asserted. After this time, the user inputs may be removed or updated. If the cycle is a write to
memory, this includes the user data inputs (DI 00 H to DI 15 H).

3-18

The DR11-W DMA engine begins the DMA cycle by asserting the UNIBUS signal BUS NPR L. This

indicates that the DR11-W would like to become the UNIBUS master in order to perform a DMA datatransfer cycle. Eventually, the signal BUS NPG H is returned to the DR11-W, indicating that it is the next
sclected UNIBUS master. The interval between the requesting and the granting of the UNIBUS is
dependent upon the DR11-W’s position in the UNIBUS priority chain as well as the overall 1/O load on
the UNIBUS.
Once the DR11-W receives BUS NPG H, it asserts BUS SACK L, indicating that it acknowledges
selection as the next UNIBUS master. The DR11-W then waits for the current UNIBUS master to
complete its transactions. To do this, the DR11-W monitors the UNIBUS line BUS BBSY L. When BUS
BBSY L deasserts, the current UNIBUS master is finished. The DR11-W then asserts BUS BBSY L for
itself, indicating that it is the current UNIBUS master.

CONTROL INPUTS

INPUTS:

SAMPLED

COH

C1H

AOO H

BA INC ENB H
WC INC ENB H
m

CYCLE REQ x H

)

(

DR11-W
BUILT-IN
<— DESKEW TIME —»

OUTPUTS:

BUSY H

END CYCLE H

)

DATA OUTPUTS
VALID

MKV86-0937

Figure 3-16

Simplified Read-Cycle Timing Diagram

CONTROL AND DATA

COH

AOO H

atia

INPUTS SAMPLED

INPUTS:

C1H
BA INC ENB H

WC INC ENB H
)
{

(

)

DI xx H

S)
K

CYCLE REQ x H

DR11-W
BUILT-IN

—DESKEW TIME—»|<«—FIXED DELAY —
OUTPUTS:

BUSY H*

J_—\_

END CYCLE H*

)

*FOR WRITE CYCLES, UNLIKE READ CYCLES, NO FIXED TIMING
RELATIONSHIP EXISTS BETWEEN BUSY H AND END CYCLE H.
MKV86-0938

Figure 3-17

Simplified Write-Cycle Timing Diagram

The DR11-W DMA engine can now perform the actual DMA requested by the user.

If the DMA cycle is a read from memory, the completion of the DMA cycle clears the busy flip-flop,
deasserting the busy signal to the user. It is also at this time that the valid data is present on the DR11-W
output lines (DO 00 H to DO 15 H). The data remains valid until the next time that CYCLE RQ x H is
asserted by the user.

If the DMA cycle is a write to memory, the busy signal clears prior to the completion of the cycle. In this
case, the END CYCLE H pulse indicates that the actual DMA cycle has been completed. Note that for
write cycles you may still reassert CYCLE RQ x H as soon as busy clears — the DR11-W holds your
request until it is finished with the current DMA cycle.

3.11

POSSIBLE FAILURES

If the DR11-W is attempting to access memory which does not exist, the DMA engine detects that failure
and causes the DR11-W to become ready and not busy. Once the DR11-W becomes ready, asserting
CYCLE RQ x H does not start further DMA cycles. The software is explicitly told that a non-existent
memory error occurred — the user device is not told.

3-20

Similarly, if the DR11-W reads from a memory location which contains bad parity, the DMA engine
detects that failure as well. Once again, the DR11-W becomes ready and refuses further assertions of
CYCLE RQ x H. The software is explicitly told that a parity error occurred — the user device is not told.

[f the user device mistakingly reasserts CYCLE RQ x H while the DR11-W is still in the midst of a
previous DMA cycle (that is, busy is still asserted), then a multi-cycle error is declared. This, like all other

errors, stops the DR11-W and is indicated to the software. Multi-cycle error is roughly analagous to the
data-late errors reported by disk and tape controllers.

If the user device asserts ATTN H, the DR11-W .stops and an attention error is reported. This may or may
not really represent an error, depending on your application.

Finally, if an impending power failure is detected on the UNIBUS (indicated by the assertion of BUS

ACLO L), then the DR11-W is stopped and an AC LO error is reported. The occurence of this error is
visible to the user device via the UACLO FNCT 2 H line.
The expiration of the burst release timer is not an error which will stop the DR11-W. It simply results in

the release of the UNIBUS (until the next CYCLE RQ x H). If the software is polling the EIR, the fact
that the timer timed out can be seen. The burst release timer is described further in Chapters 2 and 6.
3.12
BYTE TRANSFERS
By itself, the DR11-W is not capable of transferring single bytes of data to and from memory. This
becomes possible with the addition of some hardware in the user device. Refer to Section 3.4.

3.12.1
Reading Bytes from Memory
The UNIBUS does not implement a specific read byte operation, since the read word operation is
adequate for the job. Three approaches are possible for reading byte data.

3.12.1.1 Simplest and Slowest — The simplest approach to byte transfers is to ignore them (that is, treat
all transfers as word transfers). If the data rate is low enough, the DR11-W can be allowed to transfer full
words to or from memory, where only half of the word contains the useful data. This requires absolutely
no hardware but does require that the processor software unpack the DR11-W’s data buffer before
starting the transfer, and that the data buffer be twice as large (see Figure 3-18).
3.12.1.2 A Faster Hardware-Based Approach — See Figure 3-19. This circuit enables the reading of
bytes, one byte per UNIBUS cycle. Note that this circuit assumes that every block transfer starts on an
even UNIBUS byte address and all transfers are byte transfers. The flip-flop presetting logic must be
changed to accommodate starting at an odd byte.
3.12.1.3 More Complex and Fastest — The circuit shown in Figure 3-19 requires one UNIBUS cycle per
byte transfered. This wastes the other byte that is produced by every UNIBUS cycle. A more complex
circuit latches the unused byte, saving it for the next cycle. This cuts the DR11-W’s UNIBUS traffic in
half. Also, since the second byte is already in local storage, it can be produced very quickly.
When designing a circuit like this, caution must be taken to ensure that old data stored in the latches from
a previous cycle is never presented, masquerading as new data. This requires careful attention to the
handling of boundary conditions and any transfer errors which may arise.

3-21

BUFFER AFTER

BUFFER BEFORE

PACKING

-0-

-0 -

BYTE7

-0 -

BYTE 6

.0 -

-0 -

BYTE
5

-0-

BYTE4

BYTE 7

BYTE 6

-0 -

3
BYTE

BYTE 5

BYTE 4

-0 -

2
BYTE

BYTE 3

BYTE 2

_0-

BYTE1

BYTE 1

BYTE O

-0-

O
BYTE
MKV86-0908

Figure 3-18

Unpacking a Buffer Prior to Reading Bytes from Memory

C1CNTL H

AND

AOO H

BYTE SELECT HOLD

BYTE SELECT

FLIP-FLOP

—» BA INC EN

BUSY H-- c Q

c aQ
Q

D15-D08

MUX
D07-DO0

D7-DO

]

MKV86-0939

Figure 3-19

Logic Diagram of User-Supplied Hardware to Read One Byte per DMA Cycle

3-22

The circuit shown in Figure 3-20 implements such a design. Like the circuit shown in Figure 3-19, it uses

the simplifying assumption that all transfers begin on an even byte address. The circuit also assumes that
USER CYCLE RQ H lasts at least until the DR11-W busy signal asserts.

OUTPUT DATA PATH

DRITW DO15 H

DRI W DOOS H

DR22W DOO7 H

DR11W DOOO

DSH= i
%

USER DO7 H
'

SEL=0¢

SER

USER DOOH

INPUT DATA PATH

USER D17 H

DR1TW DI H

—_(_]L,K_'—:

USER DIO H

DWI1W DIO8 H

273

DR11W DIO7 M

CLK

J
DR11W DIOO H

DR11W BUSY H

USER BUSY H

o —D}—L

BUSY SIGNAL SYNTHESIZER
0HIGHQ

—]

WRITE H

BYTE

—[
76 nS

DRY1W CYCLE REQ X H

1
READ H

USER CI
CNTL H

WRITE H
WRITL

DR11W C1 CNTLH

READ H

WRITE H
DRITW CO CNTL H

USER LAST BYTE H@

PURGE

/J7——————»DR\1WA00

USER CYCLE REQ H>~—

MXVEE-DYBO

Figure 3-20

Logic Diagram of User-Supplied Hardware to Read Two Bytes per DMA Cycle

3.12.2 Writing Bytes
Writing bytes is similar, and the same three alternatives exist for writing bytes as for reading them.

3-23

3.12.2.1 Simplest and Slowest — Once again, the simplest approach to byte transfers is to ignore them.
This time, the processor must pack the DR11-W’s data buffer after the transfer completes, and the data
:

buffer must still be twice as large (see Figure 3-21).

BUFFER AFTER

BUFFER BEFORE

PACKING

-0 -

BYTE 7

.0 -

_0-

-0 -

BYTE 6

_0-

-0 -

BYTE 5

-0 -

-0-

-0 -

BYTE 4

-0 -

-0-

-0 -

BYTE 3

BYTE 7

6
BYTE

-0 -

BYTE 2

BYTE 5

4
BYTE

-0 -

BYTE 1

BYTE 3

2
BYTE

-0 -

BYTE O

BYTE 1

O
BYTE

MKV86-0907

Figure 3-21

Packing a Buffer After Writing Bytes to Memory

3.12.2.2 A Faster Hardware-Based Approach — The same circuit illustrated in Figure 3-19 also works
for writing bytes to memory. Here, no data demultiplexer is required — the byte of data from the user

device may simply be duplicated onto both bytes of the DR11-W input data. That is, user data bit (7)
should be presented on both DI 15 H and DI 7 H. Logic in the addressed UNIBUS slave device decides
which byte to update, based on A00. The same simplifying assumptions still apply to the circuit: every
transfer starts on an even UNIBUS byte address and all transfers are byte transfers.

3.12.2.3 More Complex and Fastest — A similar leap in complexity allows two byte writes to be
compressed into one word write. Here, boundary and error conditions take on even more significance than
when reading bytes since it is imperative that a latched byte actually get written to memory, not thrown
away if the DMA happens to end on the wrong boundary.

3.13.

PROCESSOR CONTROL OF TRANSFER DIRECTION

The UNIBUS signals BUS CO0 L and BUS C1 L select which type of UNIBUS transfer will be performed
(DATI, DATIP, DATO, or DATOB) and therefore which way the data will be moved. The DR11-W
drives these signals based on the user inputs CO CNTL H and C1 CNTL H. This allows the user device to
select for each and every individual DMA cycle what type of cycle will occur. Sometimes this level of
sophistication is not needed and it would be just as easy to let the processor make the choice. This can be
done by choosing one of the FUNCT x H outputs and connecting it back to the C1 CNTL H line. See
Figure 3-22. This FUNCT x H output then selects read or write cycles. If the FUNCT x H bit is 0, then
the DR11-W reads words from memory. If the FUNCT x H bit is 1, then the DR11-W writes words to
memory.

3-24

DR11-W

OUTSIDE WORLD

J2-V, R, OR K

FUNCT x H

— >

C1 CNTLH

—

J2-T
€

MKV86-0909

Figure 3-22

Connections for Processor Control of Transfer Direction

This will only work for the basic DATI (read) and DATO (write word) cycles. If CO must be

the user device must contain additional hardware.

3.14
PROCESSOR CONTROL OF BURST MODE
In a similar fashion, the processor can be made to control BURST RQ L. Once again, this can

controlled,

be done by
choosing one of the FUNCT x H outputs and connecting it back to the burst RQ L line (see Figure
3-23).
This FUNCT x H output then selects burst or non-burst cycles. (The toggle switch on the
DR11-W
module still selects whether the burst cycles are two-word or n-word bursts.) If the FUNCT x
H bit is 0,
then the DR11-W operates in burst mode. If the FUNCT x H bit is 1, then the DR11-W operates
in
non-burst mode.

DR11-W

OUTSIDE WORLD

J2-V, R, ORK

FUNCT x

———>
>

J1-K

BURST RQ L

< &—

MKV86-0910

Figure 3-23

Connections for Processor Control of Burst Mode

3-25

3.15 USER DEVICE CONTROL OF BURST MODE

DR11or the UNIBUS is busy. Burst mode causesthethesystem
Burst mode is useful whenever the data rate isit high
’s
es
improv
This
.
master
US
becomes the UNIB
W to transfer two or more words each timearbitra
S.
UNIBU
the
ng
releasi
and
ing,
ting for, acquir
overall throughput, since less time is spent
e of delivering data to the DR1 1-W as quicklS,y
Burst mode should only be used if the user device is capabl
S. If the DR11-W idles while holding the UNIBU

on the UNIBU
as the DR11-W can transfer that datamance.
then burst mode hurts system perfor

line at the
connection need be made to the BURST RQTL RQ
If you decide to never use burst mode, then anoflat
L pin),
(which must connect to the BURS
DR11-W user connectors. If you are using termincable
T
BURS
let
ator for this line (see Figure 3-24). Do not
then the user device should provide a pull-up
RQ L float at the user device-end of the cable.

USER DEVICE

DR11-W
+5 VDC

BURST RQ L

+5 VDC
l

S
<

J1-K

< e__qL

<>
<

/7L7
MKV86-0953

Figure 3-24 Circuit for a User Device Which Never Uses Burst Mode

BURST RQ L at the user device (see
If you decide to always use burst mode, then simply ground
te bursts when the overall transfer ends (for
Figure 3-25). The DR11-W contains sufficient logic to termina
number of words, the DR11-W is smart
example, if you are using two-cycle bursts and transfer an odd
to come along and even up the count).
word
enough to get off the UNIBUS, not wait forever for the next
approach is to control burst mode dynamically,
If your device uses a first-in, first-out silo (FIFO), a useful
the silo remains relatively empty, the silo
long
As
based on how full your silo becomes (see Figure 3-26). mode. Ifasthe
begins to fill, the silo logic asserts
st
logic causes the transfers to be performed in non-bur rred each timesilo
the DR11-W becomes master of the
BURST RQ L so that more than one word is transfe
UNIBUS. This allows the silo to empty faster.

Remember, in order to use burst mode effectively, your device must be able to respond quickly to the
DR11-W each time the DR11-W completes a DMA cycle.

3-26

DR11-W

USER DEVICE

[

+5 VDC

BURST RQ L

MKV86-0954

Figure 3-25

Circuit for a User Device Which Always Uses Burst Mode

USER DEVICE

DR11-W

+5 VDC

J1-K

BURST RQ L

< €

SILO LEVEL LOGIC

MKV86-0952

Figure 3-26

Circuit for a User Device Which Dynamically Uses Burst Mode

3-27

CHAPTER 4
PROGRAMMING THE DR11-W

4.1
INTRODUCTION
.
This chapter covers the programming of the DR11-W in general, and specifically when used to interface to
a user device. Specific considerations for links are discussed in Chapter 5.

4.2 REGISTERS
The DR11-W is controlled by six registers occupying four UNIBUS addresses. These registers are:
The word or byte count register.
The bus address register.
The control and status register.
The error and information register.
The input data register.
The output data register.
4.2.1
Word Count Register
The word count register limits the number of DMA cycles to be performed (see Figure 4-1). Prior to
setting the go bit, this register must be loaded with the twos-complement (negative) of the number of
words or bytes to be transferred. If the DR11-W is transferring one word per UNIBUS DMA, then this
register acts as a word-count register. If the DR11-W is transferring one byte per DMA, and the user
device never drives WC INC ENB H, then the register acts as a byte count.

DRWC

T7TT

172410
|
|, |

NEGATIVE COUNT OF DMA TRANSFERS
MKV86-0922

Figure 4-1

Word Count Register

This register is a read/write register located at 772 410 for the first DR11-W in the system.

count register must be written to as an entire word using word instructions.

4-1

The word

Bus Address Register

4.2.2
are
The bus address register provides UNIBUS address bits (15) through (01) (see Figure 4-2). These bits
the
by
(provided
H
A00
and
register)
status
and
combined with XBA17 and XBA16 (found in the control
Figure
(see
performed
be
to
transfer
DMA
next
user device) to form the complete UNIBUS address of the
4-3). Prior to setting the go bit, this register must be loaded with the address of the first word to be
-

transferred.

DRBA

172 412

{

[

{

ADDRESS OF THE NEXT DMA TRANSFER

Figure 4-2

MKV86-0923

Bus Address Register

AOO H
FROM USER
CEVICE

(FROM CSR)

(FROM DRBA BUS ADDRESS COUNTER)

(XBA 17:16)

(DRBA 15:01)

—_ CTR —

DRBA

(DRBA 00)

UNIBUS ADDRESS

MKV86-0921

Figure 4-3

Formation of an 18-Bit UNIBUS Address

4-2

This register is located at 772 412 for the first DR11-W in the system. Bits (15:01) are read/write. Bit
(00) is a read-only bit that may reflect the state of the AOO H input from the user connectors (see Section
2.4.3.2) . The program cannot directly control this bit.

The bus address register must be written to as an entire word using word instructions.
4.2.3

Shared Address 772 414

Two registers use offset address 4 (772 414 for the first DR11-W in the system). One register is the control
and status register; the other is the error and information register.

Writing to address 772 414 always writes the control and status register. The bits in the error and
information register cannot be directly written into.

What happens when the software réads from address 772 414 depends on the setting of E105 switch 5.
If E105 switch 5 is open, then reading from address 772 414 always reads the control and status register. It
is just as though the error and information register did not exist at all.

However, if E105 switch 5 is closed, then reading from address 772 414 may read either the control and
status register or the error and information register, depending on the state of an internal DR11-W flipflop (see Figure 4-4). Writing bit (15) of the combined register sets or clears this flip-flop. The flip-flop’s
state is displayed by reading bit (00) of the combined register.

[SW 5]

CSR/EIR

SELECT

FLIP-FLOP
MKV86-0920

Figure 4-4

4.2.4

CSR/EIR Flip-Flop

Control and Status Register

The control and status register is the principal register used by the software to command the DR11-W
(and the user device) and to obtain the status of the DR11-W (and the user device). See Figure 4-5.

The control and status register is located at offset address 4 (that is address 772 414 for the first DR11-W
in your system). Writing to this address always writes the control and status register. Reading from this
address may read the control and status register or the error and information register. Refer to Section
4.2.3 for details.

The CSR may be written to using either word or byte instructions.

4-3

DRCSR
772 414

A
1

T
'

T
3 ,

02
2

T
,

]

ERROR

R/C:

NON-EXISTENT
MEMORY

R/C:

ATTENTION

R/W:

MAINTENANCE

RO:

STATUS <A:B:C>

R/W:

CYCLE FLIP-FLOP

RO:

READY

R/W:

INTERRUPT ENABLE

R/W:

EXTENDED BUS ADDRESS «17:16>

R/W:

FUNCTION <3:2:1>

EIR/CSR FLAG

KEY:

R:
W:
R/W:

READ
WRITE
READ/WRITE

RO:

READ ONLY

R/C:

READ/CLEAR BY WRITING O

Figure 4-5

KVE6.0919

Control and Status Register

The description of the bits of the control and status register follows:

CSR Bit (15)
Error

Reading this bit presents the logical OR of all possible error conditions.

If E105 switch 5 is open, then writing to this bit has no effect.
If E105 switch 5 closed, then writing to this bit selects whether the CSR
or the EIR is displayed at this address.
[Reading bit 00 (the go bit) displays the contents of the flip-flop which
selects CSR versus EIR.]

Writing a 1 to bit (15) causes the EIR to be read from address xxxxx4.
Writing a 0 to bit (15) causes the CSR to be read from address xxxxx4.
Partially for this reason, you must never use a read/modify/write instruction (that is, INC, BIS, BIC, etc) directly on the CSR. If the error bit (bit
(15)) is set, writing that 1 back to the CSR inadvertently switches to the
EIR.

4-4

Similarly, if the EIR flag (bit {00)) is set, writing that 1 back to the go bit
causes the DR11-W to begin a DMA transfer. An example of bad code:
MOV
BIC
MoV

@*DRCSR, RO
#100, RO
RO, @*DRCSR

Get

the

CSR

We’ll clear the ‘IE’ bit
Writeback the modified CSR

:
:

To avoid inadvertantly setting bits, the code must always write to the CSR
with Os in bit positions (15) and {(00) (unless you really want to switch to
the EIR or set go). An example of code that works:

RO,

Get

MOV

RO
RO

@*DRCSK

the

CSR

We’ll clear the ‘IE’ bit,
and stay with the CSR
Writeback the modified CSR

@*DRCSR,
#100101,

MOV
BIC

When E105 switch 5 is open, using R/M/W instructions does not cause

this problem. Read the discussion under CSR bit (13) to understand a
problem that R/M/W instructions can still cause, even with E105 switch
5 open.

CSR Bit (14)
Non-Existent
Memory

This read/clear bit indicates that the DR11-W attempted to access nonexistent memory during the last DMA cycle.

The bit can be cleared by writing a 0 to it, by asserting go, by the
UNIBUS signal BUS INIT L, or by a DR11-W internal reset (caused by
clearing the maintenance bit).
Writing a 1 to this bit has no effect.

CSR Bit (13)
Attention

This read/clear bit indicates that the user device requires service from the
software. Attention causes the DR11-W to interrupt the processor if
the interrupt enable bit is set.

Upon the rising edge of the ATTENTION H signal, the DR11-W latches
two copies of the attention bit. One is used to generate the interrupt while
the other is used for presentation in the CSR. Both are cleared by writing
a 0 to bit (13) of the CSR. These flip-flops are thus read/clear. In
addition, the CSR also receives the attention signal directly. This allows
the user device to simply pulse the attention line (rather than having to
hold it for handshaking). Unfortunately, it also allows the software
to easily lose an attention interrupt by simply writing the CSR with a 0 in
bit-position (13). Partially for this reason, you must never use a

read/modify/write instruction (that is, INC, BIS, BIC, etc) directly on the
CSR. In fact, you must be careful even while simulating a R/M/W
instruction. An example of bad code:

Mav
BIS
mav

@*DRCSR, RO
#4, RO
RO, @#DRCSR

;

:
:

Get

the

CSR

We’ll set
Writeback

the ‘F2Y bit
the modified

4-5

CSR

If attention asserted after we read the CSR, but before we wrote it back,

RO,

RO
RO

@#DRCSR

#010004,

Get the CSR
We’ll set the

@*DRCSR,

BIS

but

MOV

wus

the write-back would destroy the attention bit and attention interrupt. To
eliminate this, the code must always write to the CSR with a 1 in bit
position (13). One solution:

Writeback

don’t

‘F2’

clear
the

_
bit,

ATTN

modified

CSR

Before you code this, read the discussion under CSR bit (15). If you are
using the DR11-W with E105 switch 5 closed, the techniques explained

@*DRCSR,
#010004,

BIC
mov

#100001, RO
RO, @*DRCSR

RO
RO

BIS

MOV

under that heading must also be applied. An example of the combination:

Get the CSR
We’ll set ‘F2’ without
killing ATTENTION
Stay with the CSR, no ‘GO’
Writeback

the

modified

CSR

Another alternative may be to write to the CSR with byte instructions
directed at the low byte. Then, the only risk is from the EIR flag in bit
(00). But since you are not going to inadvertantly select the EIR, the EIR
flag should stay clear.
Note that additional attention interrupts can be generated prior to the
software clearing the attention bit in the CSR. Each time a rising edge
occurs on the attention H line, the DR11-W initiates an interrupt (unless
an interrupt is already pending).

CSR Bit (12)
Maintenance

Setting this read/write bit establishes an internal wrap-around of the
output data to the data inputs. This allows testing without a turn-around

cable. The function bits are also incremented with each word DMAed.
This causes read and write cycles to alternate, as well as burst and nonburst cycles.
CAUTION
All of the DR11-W outputs remain enabled. Unpredictable data patterns are generated during testing.

Clearing the maintenance bit performs an internal DR11-W reset,
analagous to the effects of the UNIBUS signal BUS INIT L. The internal
reset lasts approximately 600 nanoseconds. A fast processor can clear the
maintenance bit and attempt another access to the DR11-W during the
internal reset. Do not expect reasonable results if you access the DR11-W
during its reset. The maintenance bit need not be used for most cable
wrap-around tests.

CSR Bits (11:09)
Status (A:B:C)
(for user devices)

Three general-purpose, read-only input bits. During link operation, these
bits have specific uses. See Chapter 5 for details.

CSR Bit (08)

Cycle Flip-Flop

This read/write bit controls the cycle flip-flop within the DR11-W.
Writing a 1 to this bit always sets the cycle flip-flop (similar to the user
inputs cycle RQ x H, which set the cycle flip-flop if the DR11-W is not
ready).

Writing a O to this bit always clears the cycle flip-flop.
Reading this bit indicates the state of the cycle flip-flop.

Rule: Because the user device is able to asynchronously set the cycle flipflop (using CYCLE RQ x H), the software should never write to the CSR
once the go bit is set. There is no fixed timing relationship between
CYCLE RQ x H, XBA17 and XBA16, the software, and the DR11-W
hardware so there is no way for the software to predict whether it should
write a 1 or a 0 to the cycle bit.

CSR Bit (07)
Ready

Exception to the rule: For links, the sending end must set CYCLE once
after the go bit has been set. See Chapter 5 for details.

This read-only bit indicates that the software may set up the DR11-W
registers for the next DMA transfer. Ready is also provided to the user
|

device.

CSR Bit (06)

Interrupt Enable

Setting this read/write bit allows the DR11-W to interrupt the processor
cach time the ready bit sets.

Setting interrupt enable while an attention interrupt is being requested
(that is, while attention is set) immediately results in an interrupt.

CSR Bits (05:04)
XBA17, XBA16

These two read/write bits are combined with the bits in DRBA and the
A00 H line from the user device to form a full 18-bit UNIBUS address.
These bits are incremented as the DRBA overflows. Refer to the description under cycle bit CSR bit (08).

CSR Bits (03:01)
Function (3:1)

These three read/write bits provide three general-purpose output lines to
the user device. When used as part of a link, these bits have specific uses.
See Chapter 5 for details.

CSR Bit (00)

Go/EIR Flag

Writing a 1 to this bit while the error bit is clear causes the DR11-W
DMA engine to be enabled, and the ready bit cleared. A 160 nanosecond
pulse is provided to the user device. Subsequently setting software cycle
(bit (08)) or asserting CYCLE RQ x H causes one DMA cycle to begin.
Writing a 1 to this bit while the error bit is set clears the error bit,
immediately causes the DR11-W to become ready again, and requests an
interrupt if interrupt enable is set. The GO H pulse is still sent to the user
device.

Writing a O to this bit has no effect.

4-7

Reading this bit indicates whether the CSR or EIR is being displayed at
this address. If the CSR is being displayed, this bit is read as a zero. If the
EIR is being displayed, this bit is read as a one.
Partially for this reason, you must never use read/modify/write instructions with the CSR/EIR. If the EIR is currently being displayed, you
might inadvertantly set the go bit. Read the discussion under CSR Bit
(15).

4.2.5 Error and Information Register
The alter ego of the control and status register is the error and information register.
If E105 switch 5 is
closed, the program can select this register to be read in place of the CSR. Writing
to the address still
writes the CSR (see Figure 4-6).

The description of the bits of the error and information register follow:

DREIR

772 414

ololo|olo]o]o

ERROR

NON-EXISTENT

MEMORY

ATTENTION

MULTI-CYCLE REQUEST

ACLO DURING TRANSFER

PARITY ERROR

BURST RELEASE TIMER EXPIRED

N-CYCLE BURST SWITCH

EIR/CSR FLAG

KEY:

READ

NOTE
WRITING ANY BIT ALWAYS WRITES THE

Figure 4-6

CSR BIT.

Error and Information Register

4-8

MKV86-0918

EIR Bit (15)
Error

Same as CSR bit (15). It is duplicated in the EIR for easy access.

EIR Bit (14)
Non-Existent Memory

Same as CSR bit {14). It is duplicated in the EIR for easy access.

EIR Bit (13)

Same as CSR bit (13). It is duplicated in the EIR for easy access.

EIR Bit (12)
Multicycle Request

This bit indicates if the user device requested that another transfer
be started while the previous transfer was still in progress. This is
analogous to the classical data-late error.

EIR Bit (11)

This bit indicates if a power failure occurred on the local

AC LO

UNIBUS during the last transfer.

EIR Bit (10)

This bit indicates if the DR11-W read from memory a word with

Parity Error

incorrect parity or an uncorrectable ECC error.

EIR Bit (09)
Burst Release
Timer Expired

This bit indicates if the user device is supplying data too slowly to
justify the DR11-W staying the UNIBUS master. If set, the
DR 11-W has temporarily relinquished the bus. This is a non-fatal
condition. The time-out value is adjustable on the module.

EIR Bit (08)
N-Cycle Burst Switch

This bit indicates the position of the burst-size toggle switch. One
indicates that the switch is in the n-cycle position. Zero indicates
that the switch is in the two-cycle position.

EIR Bits (07:01)
Unused

EIR Bit (00)
Register Flag

These bits read as 0 any time the EIR is being displayed.
The DR 11-W signals that the EIR is being displayed (rather than
the CSR) by displaying a 1 in bit position (00). Any time the CSR
is being displayed, bit (00) reads as a 0.

4.2.6

Input Data Register

The input data register is a read-only register sharing its address with the output data register (a write-only
register) (see Figure 4-7).

DRIDR
772 416

DATA FROM USER DEVICE

MKV86-0916

Figure 4-7

Input Data Register

4-9

Data is latched into the IDR any time a DMA write cycle is started or the IDR is explicitly read. If the
CSR/EIR is currently displaying the EIR, explicitly reading the IDR does not clock in new data. This
allows the program to read the last word transferred in by the DMA (ordinarily this data would be invisible
to the program). If the EIR is disabled (via E105 switch 5), then the IDR. always clocks in new data
whenever explicitly read.
4.2.7

Output Data Register

The output data register is a write-only register sharing its address with the input data register (a read-only
register). See Figure 4-8.

DRODR
772 416

DATA TO USER DEVICE
MKV86-0917

Figure 4-8

Output Data Register

The outputs of the register are driven directly onto DO 15 H through DO 00 H. The register is updated
each time a DMA read cycle is concluded, as well as by explicit writes to the register.
The output data register may be written to using either byte or word instructions.
4.3

DATA DESKEW

Electrical signals do not all travel at a uniform speed. If you simultaneously write multiple bits (in the

ODR) or multiple function bits (in the CSR), there is no guarantee that they will all appear simultaneously
at the other end of the cables. Similarly, if the user device simultaneously sends multiple bits (to the IDR)
or multiple status bits (to the CSR), there is no guarantee that they will all arrive at the DR11-W at the
same time. Some bits may lead others by a few nanoseconds or tens of nanoseconds. This is called skewing
(see Figure 4-9).
Normally, skew is of no consequence. The DMA engine contains hardware to compensate for skew during
DMA transfers. If you are using an interrupt to signal data availability, the interrupt latency is many times

the maximum possible skew. Even if you signal the presence of data in the ODR or IDR by means of the
function or status bits, you will avoid skew problems so long as you write the data into the ODR prior to
setting the function bit, which signals its availability. Conversely, the software should test for the data
available flag in the status bits prior to reading the data from the IDR. The delay between the instructions
is still more than adequate delay to deskew the data.

4-10

OSCILLOSCOPE

RES

Jlee

>———O—

|
SIGNAL
FLOW

-W
DR11-W

USER DEVICE

MKV86-0934

Figure 4-9

Skewing of Signals

its availability.
Skew can be a problem if you use the same instruction to place the data and to signal
via the ODR,
device
user
the
to
byte
a
move
to
intends
Consider the following (bad) example. The user
and uses bit (08) of the ODR to signal that data is available to the user device:
CLR
MOVB
BIC

@*0DR
RO
DATA,
#177400, RO

Mov

RO, @*#O0DR

BIS

#400,

; Signal ‘no data yet’
: Get the data from wherever
; Save just the data byte

: .0R. in the ‘data-available’
;

flag

: Write that all to the ODR

If bit (08) travels just slightly faster than any of the data bits, the user device may read the data just a few

nanoseconds too soon. In doing so, it may miss a few of the data bits. Here, the programmer must consider

and correct for the effects of skew. A technique that you can apply at the sending side:

CLR
MOVB
1¢:

BIC
Mav

@#0DR
DATA,
RO
#177400, RO
RO, @*#O0DR

BIS

#400,

MoV

RO,

i
;
i
;

Signal ‘no data yet’
Get the data from wherever

the user device
.0R.
in the ‘data

;5
H

@#0DR

;

Save

just

the

5end

the

data

available’

Write

that

data
to

byte

fla

all

the

ODR

Now, at 1§, we write the data two instructions before we write the data-available’ flag. This allows plenty
of time for all of the data bits to propogate to the user device.

A similar technique could be applied at the receiving end of the data. A non-deskewed example of a
receiver:

1¢$:

MOV

@*IDR,

BIT
BEG

#400,
1¢

Get

Is the
Branch

MOVB

RO, DATA

the

IDR
data
back

‘available’?
if

; It’s there -5

store

the

not

data

That will not work unless the sender is deskewing. We read the entire IDR all at once. Bit (08) may have
just arrived, but there is no guarantee that bits (07:00) have. A receiver with deskewing:
1$:
2$:

BIT
BEQ
MOVB

#400,

@*IDR

1¢
e@*IDR,

DATA

i
s
;

Is data available yet
Branch back if not
Now get the data

Now we again guarantee two instruction times for the data to all arrive. Note that only one end of the
system (data sender or data receiver) needs to deskew, but if both ends deskew, the only harm done is
slight loss of speed.
Remember that you may need to deskew either the ODR/IDR or the function/status bits.
4.4 USING PROGRAMMED 1/0
The simplest way to use the DR11-W is via programmed 1/O. Based on some synchronization method,
data words are simply written by the processor to the output data register or read from the input data
register.
The key to successful use of programmed I/0 is the synchronization method. The DR11-W is optimized

for DMA 1/0, not programmed I/O (unlike some other DR11s such as the DR11-C), so no special
hardware support for synchronization exists.
It is, however, quite easy to define a protocol using the function and status bits. The program fragment

below is sending data to the user device using such a protocol. In this case, function 1 is used to indicate
that the DR11-W has presented valid data in the ODR. Status A indicates that the device has accepted the
data.

4-12

In this example, the DR11-W and the user device have a formal handshaking protocol. Each device takes

only one step and then waits for an acknowledgement from the other end.

The DR11-W software asserts data in the output data register, followed by function 1.

The user device observes the assertion of function 1, strobes in the data, and returns status A.

The DR 11-W software must hold the data and function 1 asserted until it sees status A come
back from the user device. The DR11-W software then clears function 1.

Upon seeing function 1 clear, the user device must clear status A.

Upon seeing status A clear, the DR 11-W software can assert new data, followed by function 1.

PIOOUT

1$:

MoV
BISB

DATA,
#FUNCT1,

@#DRODR
@#DRCSR

BIT

#STATA,

@#DRCSR

3%:
4¢$:

BICB
BIT

#FUNCT1,
#STATA,

@*#DRCSR
@#DRCSR

user
if

Wait

ready

begin?

not

ACK’ed

Has

user

Wait

not:

Wait

not

Clear FUNCTION 1
Has user De-ACK’ed?

BNE

data to user
Assert FUNCTION 1
(deskewing!)

Assert

BEQ

#STATA,

BNE

@#DRCSR

BIT

PIOOUT:

NOTE

The keen-eyed reader will note that bit sets and bit
clears (read/modify/write instructions) are liberally
sprinkled throughout this code. We can do this
because we are using byte instructions directed at
the low byte of the CSR. So long as the CSR rather
than the EIR is selected, there is no danger here in
using the R/M/W instructions.

This example might be more robust, but much less

legible, if coded with the simulated BIS and BIC
instructions shown earlier in this chapter.

4.5

USING INTERRUPT DRIVEN 1/0

Here, the synchronization protocol is probably much simpler: every time an interrupt is generated, do
something.

Often, an interrupt is used to catch the attention of the software, then one or more data words are
exchanged quickly via programmed 1/0.

4-13

4.6

STARTING A DMA TRANSFER

Once the software has determined that a large block of data is to move via DMA, it is an easy task to set

#-DMALEN,

@#DRWC

#DMABUF,

@#DRBA

Mov

#DMBFHI,

BIS
MoV

#101,
RO,

RO
@#DRCSR

<wherever)>

MOV
MOV

Setup the word count
Setup the low bits
of the UNIBUS address
Get BA17 and BA16
‘OR’-in ‘IE’ and ‘GO’
Load the CSR, clearing
all

It’s

other

running

bits

DMAGO:

up the DR11-W. The program fragment below illustrates such a setup.

Later, when the transfer ends and the completion interrupt is generated, a typical piece of service code

WE
S

R2
@#DRCSR

@#DRCSR

WUE
WS

@#DRCSR
R1

JUE

@*DRCSR

999%
#020000,
DRATTN
@#DRCSR,
~ #100000,
@#DREIR,
@#DRIDR,
~ #010000,
~ #000000,
ERRLOG

@#DRCSR

TST

BEQ
BIT
BNE
MOV
MOV
MOV
MOV
MOV
MOV
BR

Did any error
We’re done if

occur?
not
Is it ATTN ‘error’ ?
Go service the ATTN
Hold the CSR for logging
Switch to EIR, clear NXM +
Hold EIR for logging
Hold last IDR for logging
Set MAINTENANCE
Clear MAINT,
INITing DR
Go log the error

ATTN

RTI

Dismiss

the

interrupt

999¢%

DRINT:

might be:

4.7

DEVICE DRIVERS

A sample driver (the XADRIVER) is distributed with every VAX/VMS system. This driver is adequate
to run the VAX/VMS on-line diagnostics, and serves to illustrate how the DR11-W may be programmed
ina VAX/VMS system. You may use this driver as it stands, modify it to suit your needs, or simply use it
as an example. The XADRIVER is documented in Guide to Writing a Device Driver for VAX/VMS

(order code AA-Y511A-TE), part of the VAX/VMS documentation set. A source listing of this driver is
also included in this manual in Appendix A.
No sample driver is available for any other VAX-11 or PDP-11 operating system.

CHAPTER 35
LINKS

5.1 INTRODUCTION
uter link.
This chapter explains the use of the DR11-W module to create a high-speed, computer-to-comp
software
special
the
and
ions
considerat
The topics covered in this chapter are both the special hardware

considerations required for DR11-W links.

Be sure that you have read and understand the previous chapters before you begin this chapter.
NOTE

When operating the DR11-W in the link mode,
switch 1 on switchpack E15 must be ON (closed).
Refer to Section 2.4.2.

LINKING TWO DR11-Ws

5.2

to create a
A DR11-W can be cross-cabled with another DR11-W or a DR11-W compatible interface
at rates
words
high-speed, computer-to-computer link (see Figure 5-1). This link can move 16-bit

y. 4

approaching 500,000 words per second.

[

Tl
T

SECOND DR11-W

FIRST DR11-W

o
n r. 1
M.

N {M o N

MKVB6-0949

Figure 5-1

Configuration for Cross-Cabling Two DR11-Ws to Create a Link

into your computer; the
For the rest of this chapter, the local DR11-W refers to the DR11-W pluggedlink.
the
of
end
far
the
at
r
compute
the
into
buddy refers to the interface plugged

5-1

Note that J1 on the first DR11-W is cabled to J2 on the second DR11-W and vice versa.
The pin-out of
the user connectors was specifically chosen so that this would connect the data outputs of
each DR11-W to
the data inputs of the other. All the necessary clocking, function, and status bits are also
cross connected
(see Figure 5-2). Remember that all of these connections are made in each direction.

ONE DR11-W

THE OTHER DR11-W

DO 15 H

DI15H

DO :OO H

—

DI 0:0 H

—

STATUSCH

FNCT 2 H

—

STATUS B H

ACLO OR FNCT 2 H

ATTNH

FNCT 3 H

STATUS AH

—=

BURSTRQ L

—

CYCLERQ AH

FNCT 1 H

C1CTLH

BUSY L

CONNECTIONS WHICH
ARE USED
CONNECTIONS WHICH
ARE UNUSED

READY H

AOO H*

WC INC ENB H

BA INC ENB H

INIT H

GO H

END CYCLE H

CO CNTL H

GROUND L

CYCLERQ B H

*THE CONNECTION OF READY H TO AOO H MAY BE USED IN SOME

SYSTEMS. SEE THE TEXT FOR FURTHER DISCUSSION.

Figure 5-2

MKVE6-0905

Connection Diagram for Half of a DR11-W Link

5-2

5.3

LINKING A DR11-W TO A DRV11-B OR DRV11-W

If the buddy is a Q-bus computer (such as a MicroPDP-11 or MicroVAX), a link can easily be constructed
with the DR11-W installed in the UNIBUS computer and a DRV11-B or DRV11-W installed in the Q-bus
computer.

Both the DRV 11-B and DRV11-W are similar to the DR11-W, both in the user interface presented to the

external world and in the programming interface presented to the software system.

The DRV11-W is a dual-height, Q-bus module implemented using programmed, logic-array technology,
while the DRV11-B is an older, quad-height Q-bus module using standard TTL technology. Both program
and cable identically with each other, and differ only in their size and level of integration.
The following differences and restrictions are important if you intend to build a DRVI11-x
to DR11-W link:

Neither the DRV11-B nor the DRV11-W terminate all signals. This means that the transmission distance must be restricted. The maximum transmission distance is dependent upon the

cabling used and must be determined by testing.

The burst mode implemented by the DRV11-B and the DRV11-W is not compatible with the
DR11-W. Therefore, the DR11-W must be programmed so as to keep the DRV11-B or
DRV11-W in non-burst (one-cycle burst) mode. This is done by setting the function 3 bit in the
DR11-W CSR. The DR11-W may be operated in any appropriate burst mode (as controlled by
the function 3 bit in the DRV11-B or DRV11-W).

5.4

REDEFINITION OF SIGNALS AND CSR BITS

Cross coupling gives specific meaning to the function and status bits, which are undefined when the
DR11-W is used to interface to a user device.
CSR Bit (11)
Status A

(for links)

This bit indicates the contents of the buddy’s function 3 bit (that is,

whether the buddy is forcing us into burst-mode DMA). See the discussion
under CSR bit (03).

CSR Bit (10)
Status B

(for links)

This bit indicates the contents of the buddy’s function 2 bit (that is,

whether the buddy is asserting our attention input. See the discussion

under CSR bit (02).
CSR Bit (09)
Status C

(for links)

This bit indicates the contents of the buddy’s function 1 bit (that is,

whether the buddy is writing to memory on its UNIBUS or Q-bus). See
the discussion under CSR bit (01).

CSR Bit (03)
Function 3

(for links)

When configured as a link, the DR11-W uses function 3 as the signal for

the buddy to operate using two- or n-cycle burst DMA. Function 3 must
be held cleared for the duration of any transfer during which the buddy

5-3

should use burst-mode DMA. Function 3 must be held set for the duration
of any transfer during which the buddy should use non-burst mode (singlecycle) DMA.
If the buddy is a DRV11-B or DRV11-W, this bit must be set in the
DR11-W so that the DRV11-B or DRV11-W does not attempt to use
burst mode. In the DRV11-B or DRV11-W, this bit may be set or cleared
depending upon whether or not you want the DR11-W to operate in burst
mode.

CSR Bit (02)
Function 2
(for links)

When configured as a link, the DR11-W uses function 2 as the signal to
interrupt the buddy. Function 2 may be asserted, then immediately

removed, or held asserted until acknowledged somehow. If the buddy is a
DR11-W, then attention will be latched at the buddy. Function 2 must be
cleared prior to the time it is next used.

CSR Bit (01)
Function 1
(for links)

When configured as a link, the DR11-W uses function 1 as the link

direction control. Function 1 must be held asserted for the duration of any
transfer where the local DR11-W should be writing to memory on its
UNIBUS (in which case we hope that the buddy is reading from memory
on its UNIBUS or Q-bus).
5.5 REDEFINITION OF BAR BIT (00)
When the DR11-W is connected as a link and switch E105-4 is OFF, bus address register bit (00) has
special meaning. This bit may be used to indicate the status of the buddy’s ready bit.

Thus, when bar (00) is 1, the buddy is ready (that is, not armed for DMA). When bar (00) is a 0, the
buddy is not ready (that is, is armed for DMA).
If Switch E105-4 is ON, this feature is disabled and bar (00) always reads as a 0.
5.6

SPECIAL INTERRUPT CONDITIONS

Two conditions can cause the local DR11-W to be interrupted by the buddy. These are:
®
®

The buddy setting function 2.
A power failure on the buddy’s bus (UNIBUS or Q-bus).

Either of these conditions cause the local DR11-W to be interrupted. Assuming that the buddy holds
function 2 set until acknowledged in some way, these two conditions can be distinguished by whether or
not status B is set at the local DR11-W. If set, then the interrupt was explicitly requested by the buddy
setting function 2. If status B is not set at the local DR11-W, then the attention interrupt must have been
caused by a power failure at the buddy.
For systems where the buddy is connected to a UNIBUS or Q-bus, a power-failure interrupt is generated
when the buddy powers down and when it powers up.

5.7 BASIC PROGRAMMING TECHNIQUES
The three basic programming techniques work for links as well as user devices.

5-4

5.7.1

Programmed 1/0

Using function 1 (status A) and function 3 (status C), the two ends of the link can exchange data using
programmed I/O techniques. In this case, function 2 (status B) is probably not a good choice since that bit
is also wired to the attention interrupt logic on the other DR11-W.

Remember that either the transmitter or the receiver of the data must provide deskew of the data.
During programmed I/0, data may be exchanged on a full-duplex basis. That is, both ends of the link may
be sending data simultaneously.

5.7.2 Interrupt Driven 1/0
Since each end of the link can interrupt the other by asserting function 2, interrupt driven I/0O is easy to
use.

Interrupt driven 1/0 is also a full-duplex technique.
|

DMA 1/0

5.7.3

Once the two ends of the link have established that a large transfer is to take place, then each end can be
set up for direct memory access. The entire data block can then be sent without further action by either
processor.

Since the DR11-W contains only one DMA engine, data can only be moving in one direction at a time
during DMA 1/0 (that is, DMA 1/0 is a half-duplex technique). The link software must have some means
of deciding on the data direction before starting the DMA. Both ends of the link must agree on the
direction (since each end controls the direction of its own transfer). One DR11-W must read from memory
while the other DR11-W writes to memory.
5.8

LINK ARBITRATION

If one end of the link is clearly the master, and the other end is clearly the slave, no arbitration for the
DMA engine is required. The master end simply informs the slave (by the use of programmed 1/O or
interrupt-driven 1/0) what transfer is next, and the slave must obey.

If, on the other hand, the two ends of the link are competing as equals, then there must be some method of
resolving the situation where both ends desire use of the DMA engine. Three possible schemes (out of
many) are listed below:

Round-robin (alternate) priority

Message priority with deadlock resolution

First-come, first-served with deadlock resolution (tie-breaking

Remember, all full-duplex use of the link must be ended prior to starting the DMA engine at either end of
the link.

5.9

INITIATING-END VERSUS SENDING-END

In a symmetrical link, where both ends operate as equals, either end can initiate a transfer. This in no way

implies the direction that the hardware will move data.

The initiating-end could ask that data be read from the buddy, or written to the buddy.

This chapter uses the phrase sending-end to indicate the end of the link that is reading data from memory.
Receiving-end indicates the end of the link that is writing data into memory.

5-5

5.10 STARTING A DMA TRANSFER
Starting a DMA transfer on a link is not very different from starting a DMA transfer to a user device. As
always, the word count and bus address registers are pointed to the memory buffer, and the go is bit set
(see Figure 5-3).

SENDING
DR11-W

RECEIVING
DR11-W

SETUP WCR, BAR

SETUP WCR, BAR
SET GO

SIGNAL 'READINESS’

SET GO
SET CYCLE

BUSY ASSERTS
(DMA READ OCCURS)
BUSY DEASSERTS
——m

CYCLE REQUEST

BUSY ASSERTS

(DMA WRITE OCCURS)

CYCLE REQUEST
BUSY ASSERTS
(DMA READ OCCURS)
BUSY DEASSERTS

BUSY DEASSERTS

—»

.
.
CYCLE REQUEST

BUSY ASSERTS

(DMA WRITE OCCURS)

CYCLE REQUEST

S ———

BUSY DEASSERTS

[]

MKV86-0915

Figure 5-3

Link DMA Operation Flow Diagram

Now, however, there is no user device to issue cycle requests. Once the go bit has been set at both ends of
the link, each DR11-W waits for the other to begin.

In order to get the transfer rolling, one additional step must be taken at the sending-end (that is, the end of
the link which will be reading memory). Bit (08) in the CSR (the cycle bit) must be set. This causes the
sending-end to perform one DMA cycle. As this cycle is performed, BUSY L asserts and then deasserts.
When BUSY L deasserts (goes high), it acts as a CYCLE RQ A H at the receiving-end of the link. The
receiving-end then performs a DMA cycle, asserting and releasing its busy signal. At the end of that cycle,
the sending-end is triggered again.
This oscillation between sender and receiver continues until the word count expires at either or both

ends. This oscillation between busy at one end and busy at the other end is shown again in Figure 5-4.
5.11
STARTING ORDER
In order for the receiving-end to not miss the first CYCLE RQ A H, the receiving-end’s software must set
go before the sending-end’s software sets cycle. This means that some form of handshake (such as an
attention interrupt) should be sent to the sending-end to indicate that it can now set cycle and start things

5-6

running. Alternatively, you can insist that the receiving-end take only a certain amount of time to set
things up. Then, once this time has elapsed, the sending-end’s software can set cycle, confident that the
receiving-end is ready for the first word of data.
At the transmitting end, go and cycle may be set using the same instruction, or go may be set prior to
cycle.
§

Once cycle has been set, neither end’s software should write to its DR11-W CSR again until the DR11-W
becomes ready. The cycle flip-flop could inadvertantly be set or cleared by the software, disrupting the
correct operation of the link. Once go has been set, and the sending-end first sets cycle, there is no way to
synchronize the operation of the software with the operation of the link hardware short of aborting the link
transfer.
5.12 UNIBUS BANDWIDTH CONSUMPTION
The DR11-W does not contain any kind of hardware throttle regulating DMA cycles. Once the link is
started, DMA cycles alternate between the two ends, as fast as the respective busses will allow (as
previously shown in Figure 5-4). Typically, this means that 50% of the UNIBUS bandwidth will be
consumed by each DR11-W while the link is running.

BUSY AT THE
LOCAL END

BUSY AT THE

\J
=

BUDDY

MKV86-0906

Figure 5-4

Busy Signal Relationship During Link DMA Operation

You can reduce the amount of bandwidth consumed by adding additional hardware to the link. This
hardware should introduce delay between the deassertion of BUSY at one end of the link and the assertion
of CYCLE RQ A H at the other end. This is shown in Figure 5-5. Usually, the same delay is added in each
direction.

BUSY AT THE

LOCAL END

DELAY ... \

BUSY AT THE
BUDDY

MKV86-0914

Figure 5-5

Busy Signal Relationship During Link Operation with Added Delays

5.13 BURST MODE
Burst mode is not generally useful during link operations, since, by definition, the ends of the link alternate
DMA cycles and any given end of the link will be idle 50% of the time. Burst mode may be useful if:
e

The UNIBUS would otherwise sit idle.

There is a lot of contention for the UNIBUS, and the DR11-W data is of high priority.

There is a large latency between DMA request and grant (as exists on many VAX-11 UNIBUS
adapters).

Remember that it is the buddy that selects whether or not the local DR11-W will operate in burst mode.

5-8

CHAPTER 6
|
DMA OPERATION IN DETAIL

6.1

INTRODUCTION

This chapter explains in detail the direct memory access (DMA) operation of the DR11-W. This is done to
aid you in understanding what the DR11-W can do for you and how you can optimize your design. This
chapter is not a general discussion of DR11-W theory of operation. This manual does not cover that topic.
The drawings in this chapter are derived from the DRI1-W Maintenance Print Set (MP00693) but are
reorganized for improved clarity. In addition, some signals which are un-named in the maintenance
print set have been given names in this manual.

Please note that the maintenance print set refers to the burst release logic as the burst data-late logic.
6.2

OVERVIEW

The DR11-W DMA mechanism can be visualized as having three layers (see Figure 6-1). Each lower level
is dependent upon the levels above it.

The ready logic controls the cycle timing chain; the cycle timing chain controls the UNIBUS timing chain.
6.3

READY LOGIC

At the topmost level is the ready flip-flop (see Figure 6-2). When ready is set, the DR11-W is idle and
ready to be set up by the software. When ready is clear, the DR1 1-W has been started by the software and
the rest of the DMA logic is enabled.
The ready flip-flop is set whenever:

The DR11-W is initialized.

The word count register overflows to 000 000.
An error occurs during DMA operation.
ATTENTION H is asserted during DMA operation.

The ready flip-flop is cleared only by writing a 1 to the go bit.

that it
Both ready and go are available to the user device. The go bit is first passed through a one-shot so bit.
the
writing
processor
the
of
speed
UNIBUS
the
of
always has a standard pulse width, regardless
6.4

WORD COUNT OVERFLOW

is,
When the DR11-W word count register reaches 000 000, D3 WCOF L returns to the deasserted (that
cannot
H
x
RQ
CYCLE
and
started,
are
cycles
DMA
further
No
set.
is
bit
ready
the
and
logic-high) state
set the cycle or busy flip-flops. This is the normal way that the transfer of a data block completes.

6-1

READY
LOGIC

DELAY
LINE

CYCLE

L Q

CHAIN

DELAY

UNIBUS

ARBITRATION

LOGIC

UNIBUS

vming
CHAIN

(||
T

)
T

MKV86-0940

Figure 6-1

DMA Cycle Logic

6.5 CYCLE AND BUSY LOGIC
The clearing of ready (by the software asserting the go bit) enables the DMA logic. Ready is presented

the data input to both the cycle and busy flip-flops (see Figure 6-3).

Both CYCLE RQ A H and CYCLE RQ B H are first ORed together, then passed
through the
maintenance multiplexer (this logic is not shown in the figure). Then the combined cycle request
is passed
through a 125 nanosecond delay line. This delay line provides part of the delay required to deskew
all of
the user inputs to the DR11-W. Once the combined cycle request emerges from the delay line,
it causes
both the cycle and busy flip-flops to set.

The busy output of the DR11-W asserts at this time, indicating to the user device that a DMA
cycle has
begun.
The cycle flip-flop may also be direct-set or direct-cleared by the software writing to the CSR. During

link
operation, the software must direct-set the cycle flip-flop to start the first DMA in a block
transfer.
Generally, there is never any reason for the software to clear the cycle flip-flop, and doing so might
cause
improper operation of this circuitry. It is for this reason that the software must never write to the
CSR
once the go bit has been set (or the first DMA cycle of a link transfer has begun).

6-2

The cycle flip-flop may be read by the software, however, its operation is completely asynchronous with
respect to the software so the results of reading the flip-flop usually are not meaningful.
6.6

MULTICYCLE REQUEST

Refer to Figure 6-3. If the user device requests another DMA cycle while busy is still asserted from the
previous cycle, the multicycle flip-flop is set. This error is analagous to the data-late errors detected by
classical disk and tape controllers. The user device is demanding words faster than the DR11-W can obtain
them from memory, or the user device is presenting words faster than the DR11-W can write them to
memory.

Like all of the error conditions described later, multicycle error stops the DR11-W at the end of the
current DMA cycle and the DR11-W becomes ready.

D8 INTERRUPT (0) H — %

D7 NPR RQ (0) H —131 74L521
3] E73

D7 MULTICY RQ (1) L
D7 ACLO (1} L
(E127-5)
D7 PAR ERR (1) L

D7 COMBINED ATTN L
(E123-10)

DI WINIT H

ég?

D7 ERROR H

D7 NEX {1} H

9 2’1"83

D7 READY B(1)L

READY

—q
23(7)4
=

D3 WCOF L

FROMR\E%?SRTDE%OUNT_\

D9 BD 00 H—>]
4
D10 LOAD CSR LOW H——

R127
82PF
AAA— 5V
—
R
A

D7 GO H

112

)

D8 INTRUPT (1) H

E78

'—7D7 WGO L

-8
S b7 READY (0) H

TO USER DEVICE

[O——

9602

6 | p7READY (1) H

D7 WGO H

160 NS + 15%

O
3

MKV86-0943

F3V
Figure 6-2

Ready Logic

6-3

€1

R126
5 1K

82PF

+ BV

09 8008

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=740 \a8 V0T 9602

D10 LOAD CSR HIGH H12] E93

160 NS :15%

CYCLE
6
[

CYCLEH

7474

E80

0‘5‘—'

D5 MCYCLE RQ H—2

7400

09 8OO L—14] E93

D7 MCYCLE DLY H

D1WINIT L

rav

D8 BUSY (WL—0) ;3

D7 READY (0} H

D7 READY OIL—2¢ E94

v
CYCLE
+2 00 NS H

E111-8)

17408

E109

1moo2

MULTICYCLE

REQUEST

111—
s D7 MULTICY RQOH

9 Ja7q [P~ D7 MULTICY RaoL

E104

6
b

[INIT 4 60]

D7 READY (OlL

7432

€82

(NOT

MAINTENANCE )

25
7474
E104

D10 MAINTA(OH

BUSY

13
.

D6 BUSY (1)H
0-2—
D6 BUSY (1)L
8
9

D10 MAINT B(1}H

D6 BUSY(O)H

{MAINTENANCE)
D1 WINIT H

D7 CCORST H

READ L OR DIO WCI CNTL H

D6 XFER CMPT LS

7402 \ 4

WRITE PATH

READ PATH

E123
MKV86.0929

Figure 6-3

Cycle Request and Busy Logic Diagram

6.7 THE CYCLE DELAY LINE
Once the cycle flip-flop sets, a rising edge begins propagating down the cycle delay line (E100) (see Figure
6-4). Five outputs are generated:
D7 GATED CYCLE L - This output is used to clear the burst release timed-out flip-flop.
D7 50 nS - This output is used to set the NPR request flip-flop, causing the DR11-W to request

use of the UNIBUS for a non-processor request (NPR) operation. It is also used to retrigger the
burst release timer.
D7 WC CLK H - This output is used to increment the word count register.

D7 200 ns — This output sets the cycle inhibit flip-flop and is wrapped around to clear the cycle
flip-flop. This means that the pulse traveling through the delay line is approximately 200

nanoseconds long.
D7 CCO RST H - If the user has requested a write to memory, this signal clears busy.

6.8

CYCLE INHIBIT FLIP-FLOP

Once the cycle flip-flop has cleared, it could be set again by the user device reasserting CYCLE RQ x H.
Cycle inhibit locks-out any new pulses from traveling down the cycle delay line.

This eliminates any errors which might arise if the user immediately sets cycle again while busy is still set
(which, of course, causes a multicycle error). This also handles the case of write operations, where busy
clears before the DR11-W is actually finished. In this case, the user device can present the new data and
assert CYCLE RQ x H while the cycle inhibit flip-flop holds off the start of the new cycle until the DR11W is ready to begin.

If the DR11-W is linked to a DRV11-B or DRV11-W, cycle inhibit is also used to provide a busy signal
which has the particular timing that the DRV11-B or DRV11-W needs.
6.9

THE NPR REQUEST FLIP-FLOP

The NPR request flip-flop is set 50 nanoseconds after the cycle pulse begins traveling down the cycle delay
line.

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MKVEE-0946

Figure 6-4

Cycle Delay Line Logic

6-5

This flip-flop notifies the UNIBUS NPR arbitrator (located at the front-end of the UNIBUS in the
processor or UNIBUS adapter) that the DR11-W needs the UNIBUS. This flip-flop also provides
the signal which latches the user inputs:
DIOO to DI15
BURST RQ L

STATUS A H to STATUS CH
CO0 CNTL H and C1 CNTL H
AO00 H
BA INC ENB H
WC INC ENB H
The NPR request flip-flop is cleared 100 nanoseconds after the UNIBUS data cycle begins.
When reading the circuit schematics, take care not to confuse the timing signals coming from the cycle
delay line (for example, D7 200 NS H) with the signals from the UNIBUS delay line (for example, D6
200 NS H). These are separate signals.

6.10

THE NPR ARBITRATOR

See Figure 6-5. The NPR arbitrator works with the UNIBUS arbitrator (at the front end of the UNIBUS)
and the rest of the UNIBUS devices to establish the priority of the DR11-W.

NPR
ARBITRATION

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MKVB6-0947

Figure 6-5

NPR Arbitration Logic

When the NPR request flip-flop sets, request is asserted at the DC013 chip. This causes the chip to assert

BUS NPR L, the UNIBUS signal that indicates that the DR11-W would like to use the UNIBUS to
perform an NPR (DMA) cycle.
The BUS NPR L signal is monitored by the UNIBUS arbitrator at the front end of the UNIBUS. When
the UNIBUS arbitrator is willing to allow an NPR cycle, it issues BUS NPG H (non-processor grant).

6-6

NPG propagates back along the UNIBUS towards the DR11-W. Each device, in turn, receives the NPG
and considers whether it needs to use the UNIBUS. If so, the device blocks the grant. If not, the device
retransmits the grant towards the back of the UNIBUS. Eventually, it reaches the DR11-W.

The DCO13 chip receives the NPG and asserts the signal D8 NPR MASTER L. This signals that the
DR 11-W has become the master of the UNIBUS and may perform one or more UNIBUS data cycles.
Any of three conditions causes the DCO13 chip to release the UNIBUS:
e

The DRI11-W is initialized.

The end cycle pulse occurs and the DR11-W has reached the end of a burst (of however many
words).

The burst release timer expires while the DR11-W is not presently in the middle of a UNIBUS
data cycle.

6.11

UNIBUS TIMING LOGIC

See Figures 6-6, 6-7, and 6-8. Once the DR11-W has become the master of the UNIBUS, this logic
produces the timing signals required to transfer one word of data.

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UNIBUS Timing Logic

6-7

H
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MEVH6-0942

The UNIBUS operation starts as both the address-to-UNIBUS and mastersync enable flip-flops set. This
occurs if:
e
o

The DR11-W is the UNIBUS master.
The NPR request flip-flop is still set.

There is no slave sync (BUS SSYN L) left over on the UNIBUS from a previous transfer.

As soon as address-to-UNIBUS sets, the DR11-W drive the contents of the bus address register (and the
CSR’s XBA17 and XBA16 and the user’s AOOH) onto the UNIBUS address liries. UNIBUS protocol then
requires that the master wait 150 nanoseconds (minimum) for the address to reach all points on the
UNIBUS and be decoded.
[f the DR11-W is writing data to memory, D6 DATA TO BUS L is also asserted, causing the DR11-W to
gate the contents of the input data register onto the UNIBUS data lines.

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D8 ADRS TO BUS H

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MKV86-0931

Figure 6-7

UNIBUS Write Logic and Timing Diagram

6-8

the UNIBUS
Meanwhile, the rising edge produced by the mastersync enable flip-flop is propagating down
This
asserted.
is
L
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BUS
tap,
nd
nanoseco
200
the
reaches
timing delay line. When the rising edge
is a
this
If
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now
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UNIBUS
the
on
address
the
that
UNIBUS
signal informs all other devices on the
receives
device
write cycle, BUS MSYN L also indicates that the data on the UNIBUS is valid. As each that
that device
addresses
of
set
the
against
d
compare
is
device
the
by
BUS MSYN L, the address received
is responsible for. If there is a match, then that device is referred to as the selected slave.

edge of mastersync
Once the DR11-W asserts BUS MSYN L, the DR11-W begins waiting. The risingselected
device on the
the
enable may or may not reach the end of the UNIBUS timing delay line before
UNIBUS responds.

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MSYN ENBL|-

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D6 ADRS TO BUS H

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Figure 6-8

UNIBUS Read Logic and Timing Diagram

6-9

6.12

SLAVE SYNC FOR WRITE OPERATIONS
If the address issued by the DR11-W is recognized by another device on the

U NIBUS, then that device
latches in the data that the DR11-W has placed on the UNIBUS. Once the data
is securely latched, the
selected device asserts BUS SSYN L (slave sync).
When the DR11-W receives BUS SSYN L, the mastersync enable flip-flop is cleared.
This causes a falling
edge to begin propagating down the UNIBUS timing delay line.

The DR11-W immediately deasserts BUS MSYN L. This informs all devices
on the UNIBUS that the
address and data lines no longer contain valid information. However, if the DR11-W
were to simultaneously remove the address from the UNIBUS address lines, some devices on the
UNIBUS might see the
address change before they received the negation of BUS MSYN L. Using
this changed address, they
might falsely be selected. To avoid this, the UNIBUS specification requires that
the address lines be held
valid for 75 nanoseconds (minimum) after the negation of BUS MSYN L. Therefore,
the DR11-W does
not clear address-to-UNIBUS until 100 nanoseconds after the deassertion of
BUS MSYN L.
D6 END CYCLE H (at time T+100 nanoseconds) clears address-to-UNIBUS.
The DR11-W now
removes both the address and the data from the UNIBUS. D6 END CYCLE
H is available to the user
device.

The clearing of address-to-UNIBUS is also used to increment the bus address register

the next transfer).

(thus preparing it for

Finally, D6 XFER CMPT H (that is, transfer complete) is produced from T+200
to T+250 nanoseconds.
This signal wraps around and clears the cycle inhibit flip-flop.
6.13 SLAVE SYNC FOR READ OPERATIONS
Read operations are similar to write operations. One additional step is required.

If the address issued by the DR11-W is recognized by another device on the UNIBUS,
then that device
reads the requested data word and places it on the UNIBUS data lines. At
the same time, the selected
device asserts BUS SSYN L (slave sync).
Once again, when the DR11-W receives BUS SSYN L, the mastersync enable flip-flop
is cleared, causing
a falling edge to begin propagating down the UNIBUS timing delay line.
Because the slave device asserted BUS SSYN L at the same time as it
asserted the UNIBUS data, the
DR11-W must allow some time for all of the data to reach the DR11-W (that
is, the DR11-W must
deskew the UNIBUS data). E42 is responsible for this delay. D6 DATA FROM
BUS H is produced
100 nanoseconds after mastersync enable clears. This pulse stores the data
in the output data register.
At the same time (T+100 nanoseconds), BUS MSYN L is deasserted
by the DR 11-W. The slave device is
now free.
D6 END CYCLE H is produced from T+200 to T-+300 nanoseconds.

Finally, D6 XFER CMPT H (that is, transfer complete) is produced from
T+300 to T+350 nanoseconds.
This signal wraps around and clears the busy and cycle inhibit flip-flops.
Note that relative to the write cycle, all of the operations are delayed
by the 100 nanoseconds spent
deskewing the received data.

6-10

6.14 BURST OPERATION
Two additional flip-flops and two one-shots are used to implement the various burst modes (see
Figure 6-9).

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Burst Logic

The DCO13 NPR arbitrator chip stays master of the UNIBUS until instructed to release it. This
instruction normally comes in the form of D7 SAC RL L (that is, sack release L).
D7 SAC RL L is asserted if:
®

The user device has not asserted BURST RQ L.

The user device has asserted BURST RQ L, the two-cycle/n-cycle toggle switch is in the
two-cycle position, an NPR cycle is requested, and the DR11-W is already UNIBUS master.

If neither of these conditions are met, the DR11-W stays UNIBUS master (n-cycle mode).
6.15

N-CYCLE LED

N-cycle mode hogs the UNIBUS, and requires you to design a system which can withstand this hogging.
Just to alert you that you are using n-cycle mode, the DR11-W module contains a light-emitting diode
(LED) which illuminates whenever n-cycle mode is in use.

If the DR11-W is operating in n-cycle mode, the E61 one-shot is fired each time the DR11-W stays master
of the UNIBUS. This one-shot stretches the signal to 230 milliseconds (minimum) so that you can see it.

6-11

6.16

BURST RELEASE TIMER

A failure in the user device may cause the user device to stop issuing CYCLE RQ x H. Ordinarily, this
would not cause a system problem. However, if the DR11-W is in the midst of a two-cycle or n-cycle
burst, the DR11-W would continue to be master of the UNIBUS, possibly forever. This would certainly
cause the rest of the system to fail.

The burst release timer (E83) eliminates this possibility. As long as DMA cycles are occuring at a rate
faster than the time-out period of the one-shot, the one-shot stays set and the burst is allowed to continue
(the normal two-cycle logic can still end the burst after two cycles).

If, however, the DMA cycles pause or stop, the one-shot may time out. In this case, the burst release
timed-out flip-flop is set and the DR11-W releases the UNIBUS. No error has occurred — the DR11-W
has simply vacated the UNIBUS since it had no useful work to perform. This allows other devices in the
system to use the UNIBUS.

When the user device makes the next cycle request, the DR11-W once again arbitrates to use the
UNIBUS.

The burst release timer is adjustable. Setting the burst release timer is described in Chapter 2.
6.17 ERRORS
The DR 11-W detects five error conditions which can also terminate a data block:
Multicycle error
AC LO error
Parity error

Non-existent memory error
Attention error

Your particular application may or may not define attention as an error, however, it does set the error bit
and terminate the data block (see Figure 6-10).
Multicycle error has already been discussed.
6.17.1

AC LO Error

If an ac (main) power failure is detected by any of the devices connected to the UNIBUS, that device
asserts the signal BUS AC LO L. This signals to all other devices on the UNIBUS that power is about to
fail, and that action should be taken to save the state of the system.
The action taken by the DR11-W is to “get out of the way”. It does this by setting the AC LO flip-flop,
completing any DMA cycle already in progress, and then terminating the data block by setting ready.
The fact that a power failure has occurred is also signaled to the user device via the user AC LO flip-flop.
This flip-flop can be set anytime (regardless of whether or not the DR11-W is ready).
Both flip-flops can be cleared by initializing the DR11-W or by setting the go bit.

6.17.2

Parity Error

Certain UNIBUS slaves (for example, memories) contain logic to generate and check parity upon the data
that they have stored. Upon reading that data, they can use the UNIBUS line BUUS PB L to signal whether
or not a parity error was detected. Note that actual data traveling on the UNIBUS is not parity-checked.

6-12

If the DR11-W is reading data from memory, and the memory asserts BUS PB L (saying that the accessed
word has bad parity), then the parity flip-flop is set. The current DMA cycle is completed and the
DR11-W becomes ready. The bus address register points to the word beyond the word containing the
parity error.
6.17.3

Non-Existent Memory Error

The UNIBUS is an asynchronous bus: although the order of events in a UNIBUS data cycle is fixed, there
is no fixed schedule with which the events must occur. When the DR11-W issues a UNIBUS address
accompanied by BUS MSYN L, the DR11-W begins waiting for some slave to become selected and reply
with BUS SSYN L. If the DR11-W were to issue an address that did not correspond to any real slave
device, then, in this scenario, the DR11-W would wait forever for BUS SSYN L.
Fortunately, this is not the way it works. The system designer establishes an absolute maximum waiting
time for BUS SSYN L. This is generally referred to as the bus time-out value although it is more properly
known as the slave sync time-out value.

When the DR11-W issues BUS MSYN L, it also fires the E78 one-shot. If this one-shot times-out before
D6 END CYCLE L occurs, then the DR11-W concludes that there is no slave device at that address and
the non-existent memory (NEX) flip-flop is set. The current DMA cycle is forced to completion and the
DR11-W becomes ready. The bus address register points to the word beyond the word which did not
respond.

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Figure 6-10

Error Logic

6-13

The value for the NEX timer is generally set at 12 microseconds. This is adequate for most systems.
However, if the system contains multiported memory or other devices with potentially slow SSYN
response times, this timer may need to be increased. An additional capacitor on the DR11-W module
allows for longer settings. If this is insufficient, you can add additional capacitance. Setting this timer is
described in Chapter 2.
6.17.4

Attention

Your application may or may not consider ATTENTION H to be an error indication, however, the
DR 11-W hardware treats it the same as the other error conditions so it is described as though it was an
error (see Figure 6-11).

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Figure 6-11

Attention Logic

The rising edge of D5 MATTN H (derived from the user signal ATTENTION H) sets both halves of the
E125 flip-flop. The attention signal now travels through two separate paths: one path goes to the attention
bit in the CSR while the other path causes an interrupt.

6.17.4.1

Attention to the CSR - The attention bit presented in the CSR is the logical OR of two sources:

The D5 MATTN H

signal, coming (almost) directly from the user device.

The attention hold flip-flop (E125-8).

As long as the user device holds ATTENTION H asserted, the attention bit in the CSR reads as 1. If the
user device merely pulses ATTENTION H, then the attention hold flip-flop holds that pulse until the
flip-flop is cleared. As long as attention hold stays set, the attention bit in the CSR reads as a 1.

6-14

The attention hold flip-flop may be cleared by:
®

®
®

Initializing the DR11-W.
Setting the go bit.
Writing a 0 to the CSR’s attention bit.

If the user device is only pulsing ATTENTION H, then care must be taken in programming the DR11-W
or the attention hold flip-flop may be accidentally cleared. See Chapter 4 for details.
6.17.4.2 Attention Causing an Interrupt — The attention interrupt flip-flop (the lower half of the
E125 flip-flop) is used to hold ATTENTION H until an interrupt can be generated. Whether the user
drives ATTENTION H with a pulse or a level, the action is unchanged.
Assuming that the flip-flop is not already being direct cleared, the attention interrupt flip-flop (E125-6)
sets upon the rising edge of D5 MATTN H. If the interrupt enable flip-flop (not shown) is also set, the
DR11-W requests that the processor be interrupted. The attention interrupt flip-flop remains set until one
of four things happens:
The interrupt actually occurs.
The DR11-W is initialized.

The go bit is set.
The CSR’s attention bit is written with a O.

The first path is the method by which the attention interrupt flip-flop is normally cleared. When the
DR11-W becomes the UNIBUS master and transmits its interrupt vector to the processor, the signal
D8 BR SACK H is asserted. This signal clears the attention interrupt flip-flop.
The last method is the path by which the software can accidentally clear the attention interrupt flip-flop.
The same cautions that apply to the attention hold flip-flop apply to the attention interrupt flip-flop as
well.
6.18 INTERRUPT LOGIC
The final piece of logic is the interrupt logic. This logic is responsible for the DR11-W interrupting the
PDP-11 or VAX-11 processor and passing the interrupt service vector on the UNIBUS (see Figure 6-12).

Three conditions may set the interrupt request flip-flop:
®

The ready bit setting while interrupts are enabled.

The software setting the go bit while an error condition still exists.

The user device asserting ATTENTION H while the DR11-W is ready (sitting idle).

When the interrupt request flip-flop sets, the request is passed to the DC013 BR arbitration chip. All of
the logic required by the DR11-W to arbitrate for the UNIBUS is contained in the DC013 chip.
The DCO013 can only process one request at a time, so if the DCO013 is presently the UNIBUS master (and
finishing the previous request), E98-6 blocks the next request momentarily.

Once a request is made of the DC013, the DCO013 asserts D8 BRx to PLUG L. This signal is routed to the
BR-level selection plug, where it is connected to one of the four UNIBUS interrupt request lines (either
BUS BR4 L, BUS BR5 L, BUS BR6 L, or BUS BR7 L).

6-15

INTERRUPT IF

GO IS SET WHILE
AN ERROR EXISTS
2

Il 74LS51

D7 WGO H

D7 ERROR H
D7 READY (1H

£68

D7 LINK ATTN (1)H ———

O--

7432
E94

INTERRUPT IF

ATTENTION ASSERTS

INTERRUPT IF

reapvserwe

([ iles

ERROR OCCURS)

07 READY (NH-—C

]

DI WINIT H —5
s | 7902
E88

o[~

180

[

7400

O———

D8 INTRUPT (O)H

L 5

R86

D8 INTRUPT (OH

7474

OVERFLOW OR AN

15V

D10 INT ENB (1)H

WHILE READY

INTERRUPT

REQUEST

+5V

BR
ARBITRATION

DCO13 (BR)

;

£107

REQUEST

D8 BUS NPR L————a—O BUS NPR

S R34

3 > 180

REQUEST 8US [Or 2
BUS GRANT OUT

] BUS GRANT IN

R8T
390

DI WSSYN L

BUS SACK -

f—fio CLR SACK ENB
—

D8 BGX TO PLUG H

SACK|—>

—50 STEAL GRANT
D8 BGX FROM PLUG H

DB BRX TO PLUG L

b——

DB DRIVE BSACK L

BUs BBsY PO

BUS SSYN

BIJS BBSY L

-Cl MASTER CLR

MASTER D

DB B8R MASTER L

a é;‘gg

——-D8 SEND MASTER H

Ol WINIT H

MKV88-0969

Figure 6-12

Interrupt Arbitration Logic

When the processor wishes to grant the interrupt, the processor sends the appropriate bus-grant signal (for
example, BUS BGS5 H in response to BUS BR5 L). The BR-level selection plug intercepts this signal and
routes it to the DCO13. Upon seeing the bus grant signal, the DCO013 asserts BUS SACK L (via
D8 DRIVE BSACK L). BUS SACK L (selection acknowledge) informs the central UNIBUS arbitrator
that the grant was picked up (acknowledged) by an interrupting device. The DCO013 then waits until the
data section of the UNIBUS is idle. When the data section next becomes idle, the DC013 asserts BUS
BBSY L and deasserts BUS SACK L. Asserting BUS BBSY L indicates that the data section of the
UNIBUS is once again busy. Deasserting BUS SACK L indicates to the central arbitrator that the DR11W is willing to let the arbitrator select the next UNIBUS master. The DR11-W is now master of the
UNIBUS.

Once the DR11-W becomes the UNIBUS master, the signals D8 BR MASTER. L, D8 BR MASTER H,
and D8 SEND INTR H are all asserted, in that order. D8 BR MASTER L asserts the DR11-W’s
interrupt service vector address onto the UNIBUS, after which D8 SEND INTR H causes the UNIBUS
signal BUS INTR L to be asserted. This signal strobes the vector into the processor. The processor then
replies with BUS SSYN L, which causes the DC013 to end the transaction.

6-16

APPENDIX A

THE VAX/VMS XADRIVER

This Appendix contains a listing of the Macro-32 source for the VAX/VMS XADRIVER - the device
driver for the DR11-W. This driver is included with all VAX/VMS systems.

This is the listing from VAX/VMS version 4.4 and is subject to change. It is provided in this manual as an
example.

.TITLE

XADRIVER
“X-57

. IDENT

- VAX/VMS DR11-W AND DRV11-WA DRIVER

xR E SRR R R R R E R RS R AR AR E R E KRR EE R B R A S AR
X S
s
1

7
.

ALL

[]

7
.

7
-

7
1

CORPORATION.

[

7
.

SOFTWARE

ON EQUIPMENT WHICH

RELIABILITY OF

IS NOT SUPPLIED BY DIGITAL.

ITS

Y Y Y SIS EEEEE R RN ER R RN R RN R R R

R R EE R E

R R E

R E R

B AR

AR R

7
.

FACILITY:

[]

7
.

VAX/VMS

Executive,

I/0

Drivers

]
.

ABSTRACT
:

7
.

)
.

7
.

)

#*
*
*

*
*

LR R R *

?
.

sk
sk

k)
.

DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE

*
*

SUBJECT TO CHANGE WITHOUT NOTICE
THE INFORMATION IN THIS SOFTWARE IS
A COMMITMENT BY DIGITAL EQUIPMENT
CONSTRUED AS
BE
NOT
SHOULD
AND

TRANSFERRED.

k ok

RESERVED.

THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED
AND WITH THE
LICENSE
SUCH
OF
TERMS
THE
ACCORDANCE WITH
ONLY IN
OTHER
ANY
INCLUSION OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE OR
COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
HEREBY
SOFTWARE IS
THE
NO TITLE TO AND OWNERSHIP OF
OTHER PERSON.

RIGHTS

1
-

This module contains the driver for the DR11-W (Unibus) and
Since the driver was originally written for
DRV11-WA (Q-bus).
the DR11-W, many inline comments refer to the '"DR11-W" and "Unibus"
but apply equally well to the DRV11-WA and the Q-bus.

ENVIRONMENT
:

Kernal

Mode,

Non-paged

AUTHOR:
C.

Sameulson

10-JAN-79

MODIFIED

BY:

V04-005

DGB0127
Clean up

Donald G. Blair
document MicroVAX Il

and

19-Sep-1985
support.

vV04-004

DGB0124
Add support

for

Donald G. Blair
the DRV11-WA on

MicroVAX

25-Jul-1985
I1.

V04-003

DGB0112
Donald G. Blair
31-Jan-1985
Move the I0$M_RESET bit to a new location so it no
longer coincides with the ITO$M_INHERLOG bit.

V04-002

DGB0106
Donald G. Blair
07-Dec-1984
Fix synchronization problem which occurs in the
cancel routine if an 1/0 completes while we’re irying

UGS

uME

WME

WUE

Tables for loading and dispatching
Controller initialization routine
FDT routine
The start 1/0 routine
The interrupt service routine
Device specific Cancel 1/0
Error logging register dump routine

cancel

it.

V04-001

JLV0395
Add

AVL

Jake
bit

VanNoy

6-SEP-1984

DEVCHAR.

vV03-006

TMKOO0O0 1
Fix

Todd

broken

Katz

P7-Dec-1983

branch.

transfers

vV03-005

has

been

fixed.

vV03-004

KDM0059
Kathleen D. Morse
Change time-wait loops to use new
Add $DEVDEF.

V03-003

KDMO0O0OO02

14-Jul-1983
TIMEDWAIT macro.

Added

$DYNDEF,

Kathleen
$DCDEF,

and

MUE

M
T

JLV0304
Jake VanNoy
24-AUG-1983
Several bug fixes. All word writes to XA_CSR now have
ATTN set so as to prevent lost interrupts. Attention
AST list is synchronized at device IPL in DEL_ATTNAST.
Correct status is returned on a set mode ast ihat
is returns through EXE$FINISHIO. REQCOM’s are always
done at FIPL.
Signed division that prevented full size

A-2

Morse
$SSDEF.

28-Jun-1982

.SBTTL

External

and

local

symbol

symbols

$ACBDEF
$CRBDEF
$DCDEF
$DDBDEF
$DEVDEF
$DPTDEF
$DYNDEF
$EMBDEF
$ IDBDEF
$ IODEF
$ IPLDEF
$ IRPDEF
$PRDEF
$PRIDEF
$SSDEF
$UCBDEF
$VECDEF
$XADEF

;

Local

;

Argument

AST

control block
Channel request block
Device types
Device data block
Device characteristics
Driver prolog table
Dynamic data siructure types
EMB offsets
Interrupt data block
I/0 function codes
Hardware IPL definitions
I/0 request packet
Internal processor registers
Scheduler priority increments
System status codes
Unit control block
Interrupt vector block
Define device specific
characteristics

symbols
list

(AP)

offsets

for

device-dependent
ue

12
16

Other

20
s

10
65535
€<2+9>/10>

1
.

7
.

7
»

|
-

DR11-W

QI0

parameters

First QIO parameter
Second QGI0 parameter
Third QIO parameter
Fourth QI0 parameter
Fifth QI0 parameter
Sixth QIO parameter

constants

XA_DEF_TIMEOUT
XA_DEF_BUFSIZ
XA_RESET_DELAY

;

definitions

***NUTE***

that

ORDER

follow
OF

THESE

the

10 second default device
Default buffer size
Delay

N microseconds after RESET
(rounded up to 10 microsecond
intervals)

standard

UCB

timeout

FIELDS

UCB
IS

fields

ASSUMED

$DEFINI

$DEF

UCB
.=UCB$L_DPC+4
UCB$L_XA_ATTN
1

$DEF

. BLKL
UCB$W_XA_CSRTMP

. BLKW
UCB$W_XA_BARTMP
. BLKW
UCB$W_XA_CSR
. BLKW
UCB$W_XA_EIR
. BLKW
UCB$W_XA_IDR
. BLKW
UCB$W_XA_BAR
. BLKW

$DEF
$DEF
$DEF

$DEF
$DEF

Attention

AST

listhead

Temporary

storage

CSR

image

Temporary

storage

BAR

image

Saved

CSR

interrupt

Saved

EIR

interrupt

Saved

IDR

interrupt

Saved

BAR

1
1
1
1
1

A-3

interrupt

UCB$W_XA_WCR
.BLKW
UCB$W_XA_ERROR

$DEF

. BLKW

UCB$L_XA_DPR

$DEF

. BLKL

UCB$L_XA_FMPR
- BLKL
UCB$L_XA_PMPR
.BLKL
UCB$W_XA_DPRN
. BLKW

$DEF
$DEF
$DEF

$DEF

Bit

;

Saved

;

Data

Path

Regisler

contents

;

Final

Map

contents

;

Saved Datapath Register Number
And Datapath Parity error flag
Temporary storage of BAE (DRV11-UWA

;

. BLKW

;

UCB$W_XA_BAE
. BLKW

positions
$VIELD

for

;

device-dependent

:
s
3
.

device

Map

only)

field

status

UCB

device

ATTN

AST

flag

contents

(DRV11-WA

Saved BAE

stat us

UCB,0,<<ATTNAST, ,M>, ~
<UNEXPT, ,M>, <IGNORE_UNEXPT, ,M>, -

interrupt

Saved WCR

UCB$W_XA_BAETMP

$DEF

;

3
1

only)

UCB

specific

bit

definitions

requested

Unexpected interrupt received
Ignore initial interrupt on DRV11-WA

UCB$K_SIZE=.
$DEFEND

;

Device

UCB

$DEF

$DEFINI
XA_WCR

$DEF
$DEF

XA_BAR
XA_BAE

$DEF

XA_CSR

offsets

from CSR addres

.
.
JBLKW

;

Bit

positions
$EQULST

.BLKW

for

device

:
:

Buffer

definitions

Control/status

Buffer

address

extension

(DRV11-WA)

control/status

XA$K_,,0,1,«-

T)
ST
Sy
IEVY
IRTT
L
L
N
TyR Y
Y
~e

A-4

bit

values

Define CSR STATUS bit values

XA_EIR

FNCT

<Ga, ,M>, <FNCT,3,M>,
<XBA,2,M>,

<MAINT, ,M>, <ATTN, ,M>, <NEX, ,M>, <ERROR, ,M>, -

CSR

Define

XA_CSR,0,<-

<IE, ,M>, <RDY, ,M>, <CYCLE, ,M>, <STATUS,3,M>,

$DEF

count

<FNCT1,2><FNCT2,4><FNCT3,8><STATUSA,2048> <STATUSB, 1024> ¢<STATUSC,512>-

$VIELD

DR11-W

Start
Word

Control/status

Start device
CSR FNCT bits

Extended address bits
Enable interrupts
Device ready for command
Starts slave transmit
CSR STATUS bits
Maintenance bit
Status from other processor
Nonexistent memory flag
Error or external interrupt

Error

information

$DEF
$DEF

XA_IDR
XA_ODR

. BLKW

.SBTTL

Device Driver Tables

DPTAB

we
ue
W
U
U
WS
M

Error

information register

Flags whether EIR or CSR is accessed
-

Unused

spare

Burst mode transfer occured

Time-out for successive burst xfer
Parity error during DATI/P

Power fail on this processor
Multi-cycle request error
ATTN - same as in CSR
NEX - same as in CSR
ERROR - same as in CSR

Input Data Buffer register
Output Data Buffer register
End of DR11-W definitions

$DEFEND

table

Driver prologue

¢<REGFLG, ,M>, <SPARE,7,M>,
¢<BURST, ,M>, «<DLT,,M>,<PAR, ,M>, <ACLO, ,M>, , M>,,
<MULTI
CATTN, ,M>, <NEX, ,M>, ¢ERROR, ,M>, -

XA_EIR,0,<-

$VIELD

; Bit positions for error information

END=XA_END,
ADAPTER=UBA,
FLAGS=DPT$M_SVP,

DPT-creation macro

;

Adapter

UCBSIZE=UCB$K_SIZE,
NAME=XADRIVER
INIT

DPT_STORE

End of driver

DPT_STORE UCB,UCB$B_FIPL,B,8
DPT_STORE UCB,UCB$B_DIPL,B,22
DPT_STORE UCB,UCB$L_DEVCHAR,L,<-

DEV$M_AVL! DEVS$M_RTM! -

label

: Allocate system page table
1
;

UCB size
Driver name

.
:
:
s

initialization table
Device fork IPL
Device interrupt IPL
Device characteristics

Start

load

Available
Real Time device

Error Logging enabled

DEV$M_ELG! -

DEV$M_IDV!DEV$M_ODV>

type

input device
output device

; Device class
IME
DPT_STORE UCB,UCB$B_DEVCLASS,B,DC$_REALT
R11W ; Device Type

D,XA_CONTROL_INIT

DEVNAM=XA,
START=XA_START,

FUNCTB=XA_FUNCTABLE,
CANCEL=XA_CANCEL,

e
G
WE
U
ue

DDTAB

Start of reload
initialization table
Address of DDT

Address of
service

interrupt

routine

table

Driver dispatch

size

tables

END

buffer

Address of controller
initialization routine
End of initialization

DPT_STORE

XA_INTERRUPT

DPT_STORE CRB,CRB$L_INTD+VEC$L_INITIAL,

DPT_STORE DDB,DDB$L_DDT,D,XA$DDT
DPT_STORE CRB,CRB$L_INTD+4,D,

Default

XA_DEF_BUFSIZ
DPT_STORE REINIT

DPT_STORE UCB,UCB$W_DEVBUFSIZ,W,

DPT_STORE UCB,UCB$B_DEVTYPE,B,DT$_D

DDT-creation macro
Name of device
Start 1/0 routine
FDT address
Cancel 1/0 routine

REGDMP=XA_REGDUMP, DIAGBF=¢<15%4>+¢<¢3+5+1>*4>>, -

;
;

ERLGBF=<<15*4>+¢1%45+<EMB$L_DV_REGSAV>>

;

Error

log

buffer

size

;

Function

dispatch

table

XA_FUNCTABLE:

FUNCTAB

) =

;

FDT

;

Valid

for

driver

I/0

functions

<READPBLK,READLBLK,READVBLK,NRITEPBLK,NRITELBLK,NRITEVBLK,SETMODE ,SETCHAR, SENSEMODE , SENSECHAR>

FUNCTAB
FUNCTAB

XA_READ_WRITE, -

;

Device-specific

buffered

functions

FDT

<READPBLK,READLBLK,READVBLK,NRITEPBLK,NRITELBLK,NRITEVBL
K)
+EXE$READ, <READPBLK,READLBLK,READVBLK>

FUNCTAB
FUNCTAB
FUNCTAB
FUNCTAB

+EXESWRITE , <WRITEPBLK,WRITELBLK,WRITEVBLK>
XA_SET
, <SETMODE,
MOD
SETCHAR>
E
+EXE$SEN
, <SENSEMOD
SEMO
E , SENSECHAR
DE
>

.SBTTL

XA_CONTROL_INIT,

Controller

initialization

4+
3
7

XA_CONTROL.-INI T,

power

failure

Called

when

driver

loaded,

system

booted,

recovery.

7
2

Functional

Description:

3
.

7
]
-

3
.

]

1)
2)
3)
4)

Allocates the direct data path permanently
Assigns the controller data channel permanently
Clears the Control and Status Register
If power recovery,
requests device time-out

?
.

HoHonon

address

CSR

address
address
address

of
of

1DB
DDB

CRB

k]
.

]
-

3
7
]

VEC$V_PATHLOCK bit
UCB address placed

set in CRB$L_INTD+VEC$B_DATAPATH
into IDB$L_OWNER

7
-

b}
.

XA_CONTROL_INIT:
MOVL
MOVL
BISW
CPUDISP

IDB$L_UCBLST(RS),R0
; Address of UCB
RO, IDB$L_OWNERCRS)
; Make permanent
#UCB$M_ONL INE ,UCB$W_STSCRO)
«<<UV1,3%>,
-

<UvV2,5¢>>, -

CONTINUE=YES

3¢%:
S¢:

BRB

Set

UNSUPRTCPU,FATAL

status

:
"on-line"TM

;

branch

handle

MicroVAX

;

handle

else

MicroVAX

continue

for

all

other

processors

9
#DT$_XA_DRV11KWA, UCB$B_DEVTYPECRO)

device

owner

;
s

BUG_CHECK
MOVB

;

controller

;

DRV11-WA

;s
;

not

this 1is a
a DRV11-WA

supported
Q-bus,
rather

then
than

MicroVAX
this is
a DR11-W.

On the DRV11-WA, the interrupt enable bit normally remains sel at all
times since an interrupt is generated if the bit makes a low-to-high
Since ihe
transition when there isn’t a DMA transfer in progress.
device has the IE bit clear at power-up, an interrupt will be generated

Therefore, we tell the interrupt service
when we set the IE bit.
routine to ignore the first unexpected interrupt that occurs.

BBS

#XA_CSR$V_IE, -

BBSS

#UCB$V_IGNORE_UNEXPT,-

XA_CSR(R4),9%

UCB$W_DEVSTS(R0),9%

: Br if IE bit already set.
3 Else interrupt will occur.

1f powerfail has occured and device was active, force device time-out.
TimeThe user can set his own time-out interval for each request.
out is forced so a very long time-out period will be short circuited.
9¢:

10 $:

BBS

#UCB$V_POWER,UCB$W_STS(RO0),10$

BISB

#VEC$M_PATHLOCK,CRB$L_INTD+VEC$B_DATAPATH(RS)

BSBW

XA_DEV_RESET

.SBTTL

XA_READ_WRITE,

powerfail

Branch

Permanently allocate direct datapatlb

;

Reset DR11W

Done

FDT for device data transfers

GE W s we 8 U8 ME NS Wl U A W8 UE WP ME U M U WF ST MR MUE U MR M SR G ue ue [T IIRY IEREY Y ITY IEVY Y]

RSB

;

XA_READ_WRITE, FDT for READLBLK ,READVBLK,READPBLK,WRITELBLK,WRITEVBLK,
WRITEPBLK

Functional

description:

1) Rejects QUEUE 1/0’s with odd transfer count

2) Rejects QUEUE 1/0’s for BLOCK MODE request to UBA Direct Data
PATH

odd

byte

boundary

3) Stores request time-out count specified in P3 into IRP

4) Stores FNCT bits specified in P4 into IRP
5) Stores word to write into ODR from PS5 into IRP
6) Checks block mode transfers for memory modify access
Inputs:

R3 =
R4 =
RS =
R6 =
R8 =
AP =

Address
Address
Address
Address
Address
Address
P1 =
P2 =

of IRP
of PCB
of UCB
of CCB
of FDT
of P1
Buffer
Buffer

routine
Address

size

in bytes

P3 = Request time-out period (conditional on I0O$M_TIMED)

P4 = Value for CSR FNCT bits (conditional on IO$SM_SETFNCT)
PS5 = Value for ODR (conditional on IO$M_SETFNCT)
P6 = Address of Diagnostic Buffer
Outputs:

RO = Error status

if odd transfer count

IRP$L_MEDIA = Time-out count for this request
IRP$L_SEGVBN = FNCT bits for DR11-W CSR and ODR image

XA_READ_WRITE:
The

umE

TO$M_INHERLOG ("inhibit error logging") function modifier was not
intended to be used by this driver.
However, since the definition for
the I0$M_RESET modifier used to be the same as that for
I0$M_INHERLOG,
the error logging routines incorrectly used the IO$M_RESET bit to

determine whether it should log errors.
definition for IO$M_RESET was changed.

manually

move

bit

its

new

#I0$V_INHERLOG, IRP$SW_FUNCCR3), 1%

BISW

s br
#TO0$M_RESET, IRP$W_FUNC(CR3)

old

reset

bit

not

set

;

set

#S5SS5¢$_BADPARAM,RO

Branch

IRP$W_FUNC(R3),R1
P3CAP),IRP$L_MEDIA(R3)
#10$V_TIMED,R1,15%

;

Set

Abort

s
;i
;

Fetch 1/0 Function .code
Set requesti specific time-out
Branch if time-out specified

P2CAP),10%

G"EXE$ABORTIO

new

reset

error

bit

transfer

status

request

count

code

even

#XA_DEF_TIMEOUT,IRP$L_MEDIACR3)

EXTZV
ASHL

; physical
I/0 read or write
20¢
#10$_WRITEPBLK,R1
20¢%
#5S$_NOPRIV,RO
i No privilege for operation
5¢
i Abort request
#0,#3,P4(AP),RO
; Get value for FNCT bits
#XA_CSR$V_FNCT,R0, IRP$L_SEGVBN(R3)

MOVW

;1
PSCAP),IRP$L_SEGVBN+2(R3)

BEQL

MOVZWL
BRB

not the
whether

this

decide

whether
not

word

count

#I0$V_DIAGNOSTIC,R1,20%

BEQL
CMPB

For

; Else set default timeout value
; Branch if not maintenance reqeust
#]10$V_FCODE,#I0$S_FCODE,R1,R1
3 AND out all function modifiers
#10$_READPBLK,R1
s
If maintenance function, must be

BBC
EXTZV
CMPB

20$:

RESET

BBCC

BLBC
MOVZHWL
JMP
MOVZIWL
MOWVL
BBS
MOvL
15¢:

the

To solve this problem, the
For the sake of old programs,
location.

block

;

into position for CSR
Store ODR value for later

mode

transfer, check buffer for modify access
function is read or write.
The DR11-W does
to read or write,
the users device does.
requests, return to read check or write check.

this

use,

check

mode

Shift

not

25%:
30¢:

word

BLOCK
the

MODE
data

aligned,

request
buffer

reject

and

the

address

the

UBA

for

Direct

word

Data

#10$V_WORD, IRPSW_FUNC(R3),30%$

BBS

; Branch if word
#XA$V_DATAPATH,UCB$L_DEVDEPEND(RS5),25$

BL.BS

P1CAP), 2%

G"EXES$SMODIFY

.SBTTL

XA_SETMODE,

Mode,

mode

;
;

Branch if Buffered
DDP, branch on bad

;

Return

;

Set

is
buffer

request.

BBS

JMP
RSB

Path

alignment.

Set

Checke buffer

transfer
Data

Path
alignment

for modify access

characteristics

FDT

P+

;

XA_SETMODE,

FDT

routine

process

SET

A-8

MODE

and

SET

CHARACTERISTICS

use

Functi onal

description:

If IO$M_ATTNAST modifier is sel, queue attention AST for device

7
.

I1f I0$M_DATAPATH modifier is set, queue packet.

7
.

finish

Else,

I1/0.

Inputs:

?
.

7
.

R3
R4
RS

=
=

?
.

1/0 packet address
PCB address
UCB address
CCB address
Function code

AP = QIO Paramater

list address

Dutputs:

attention AST
1f I0O$M_ATTNAST is specified, queue AST on UCB
to driver.

If I0$M_DATAPATH is specified, queue packet
Else, use exec routine to update device characteristics

7
.

?
.

list.

)
.

:
XA_SETMODE

IRP$W_FUNCC(R3),R0

MOVZWL

#I10$V_ATTNAST,R0,20%

BBC

entire function code

Get

: Branch if not an ATTN AST

Attention AST request

#"M<R4,R7>

PUSHR

MOVAB

UCBS$L_XA_ATTN(RS),R7

: Address of ATTN AST control block

JSB
POPR

G "COMS$SETATTNAST .
#"M<¢R4,R7>

Set

Branch

BISW

#UCB$M_ATTNAST ,UCB$W_DEVSTS(RS)
;s

Flag

Set

RO,50¢

BLBC

10¢:

up attention AST
if

error

ATTN AST expected.

#UCB$V_UNEXPT,UCB$N-DEVS+S(R5),10$
Deliver AST if unsolicited interrupt
’
DEL_ATTNAST
status

BBC
BSBW

#SS$_NORMAL,RO

MOVZBL

GM"EXESFINISHIOC

JMP

: Thats.all for now (clears R1)

IO$M_DATAPATH 1is set,

1f modifier

order with other

; queue packet.

20¢%:

list

The data path is changed
requests.

driver

level

preserve

BBS

S*"#10$V_DATAPATH,R0,30%

1f BDP modifier set, queue packet

JMP

G"EXE$SETCHAR

;

Set

device characteristics

: This is a request to change data path useage, queue packet
30¢%:

Error,

45% :

50¢%:

CMPL

BNEQ
JMP
abort

#10$_SETCHAR,R7?

45¢$
G "EXE$SETMODE

H Set characteristics?
:
3

No, must have the privelege
Queue packet to start I/0

MOVZWL

#SS$_NOPRIV,RO

No priv for

JMP

G"EXE$ABORTIO

Abort

CLRL

operation
error

XA_START,

Start

I/0

routines

ME UE UE U M G U G U U U NB U ME US UE LS ME M W wE we aE -E uE wE us

.SBTTL

XA_START

Functional

Start

routine

Start
or

block

the
2)

data

transfer,

set

characteristics,

enable

ATTN

AST.

Description:

This

has

1/0

two

major

transfer.

mode.

The

transfer

count
the

are

read

Characteristics.

new

data

path

This

FNCTN

Set

and

functions:

zero,

request

flag

transfer

bits

the

can

the

DR11-W

STATUS

bits

in
in

completed.

the

set

function
the

either

CSR are

change

the

word

set.

DR11-W

CSR

data

UCB.

path,

the

Inputs:
R3
RS

Address

the

Address

1/0

the

UCB

request

packet

Outputs:

RO = final status
R1 = value of CSR
Device errors are
Diagnostic buffer

.ENABL

and

number of bytes transferred
STATUS bits and value of input data
logged
is filled

buffer

LSB

XA_START:

Retrieve

the

ASSUME
MOVL
MOVL

address

the

device

CSR

IDB$L_CSR EQ 0
UCB$L_CRB(RS),R4
;s Address
@CRB$L_INTD+VECS$L_IDB(R4),R4
;

Fetch

the

1/0

MOVZWL
MOVW
EXTZV
ws
us
we
s

CMPB

CSR

code

IRP$W_FUNC(R3)>,R1
; Get entire function code
R1,UCB$W_FUNC(RS)
; Save FUNC in UCB for Error Logging
#ID$V_FCDDE,#ID$S_FCDDE,R1,R2 s Extract
function field

;

SET

CHARACTERISTICS

Process

Set

#I10$_SETCHAR,R2
3%

Set

will

word

characteristics?

Characteristics

QIO

function

INPUTS:

XA_DATAPATH

bit in
to use.
If bit is
direct datapath.

Device

one,

Characteristics

use

buffered

uUe

CRB

Dispatch on function code.
If this is SET CHARACTERISTICS,
select a data path for future use.
If this is a transfer function,
it will either be processed
or block mode.

BNEQ

function

Address

A-10

specifies which data path
data path.
If zero, use

OUTPUTS:

CRB is

flagged as

DEVDEPEND bits

to which datapath

->
->

1
0

XA_DATAPATH
XA_DATAPATH

is updated

buffered data path in use
direct data path in use

1o use.

in device characteristics

IRP$L_MEDIACR3),UCB$B_DEVCLASS(R5)

MWere we right?

;

#VEC$SM_PATHLOCK,CRB$L_INTD+VEC$B_DATAPATH(RO)
R1

buffered

Set

Return Success

for device reset

S*"#I0$V_RESET,R1,4$
XA_DEV_RESET

be a data

transfer

function

;

Branch

;

Reset

i.e.

one

set,

not

device

READ

;

If so, only set CSR FNCT bits and return STATUS from CSR

4%
:

to see

this

is a zero

length

TSTW
BNEQ
BBC
DSBINT
MOVIW

UCB$W_BCNT(RS)
10¢
S*"#I0$V_SETFNCT,R1,6$

MOVZIWL
BICW
BISW
BISW

XA_CSR(R4),R0

MOVIW
BBC
BICW3

reset

WRITE

This must

Check

here

DR11-W

datapath

;

,RO
#5S$_NORMAL

subfunction modifier
BBC
BSBW

datapath

direct

Assume

;

CLRL
MOVZWL
REQCOM

3%:

; Set device characteristics

#XA$V_DATAPATH,UCB$L_DEVDEPEND(RS),2%

2%:

Get CRB address

#VEC$M_PATHLOCK,CRB$L_INTD+VEC$B_DATAPATH(RO)

BBC
BICB

UCB$L_CRB(R5),R0

MOVL
Mmova
BISB

transfer.

Is transfer count zero?
No, continue with data transfer
Set CSR FNCT specified?

:
:
;

IRP$L_SEGVBN+2(R3),XA_0ODR(R4)
s

Store

word

0ODR

#¢XA_CSR$M_FNCT!XA_CSR$M_ERROR>,R0
IRP$L_.SEGVBN(R3),R0

#XA_CSR$M_ATTN,RO

:
H

Force ATTN on to prevent lost
interrupt

RO, XA_CSR(R4)

#XA$V_LINK,UCB$L_DEVDEPEND(RS),5%

#XA$K_FNCT2,R0,XA_CSR(R4)

;

Link mode?

: Make FNCT bit 2 a pulse

S$:

Build

CSR image in RO for

10¢:

MOVZWL
DIVL3
7

;

U
WS
WD

Fetch DR11-W registers
If error, then log it
Log a device error

Fill diagnostic buffer if specified
Return
Return
Enable

Request

CSR and EIR in R1
status in RO
device interrupts
done

later use in starting transfers

UCB$W_BCNT(R5),R0

#2 ,R0,UCB$L_XA_DPR(RS)

Set up UCB$W_CSRTMP used for

MOVZWL

UCB$W_XA_CSR(RS5),R1
UCB$W_XA_ERRORC(R5),R0
#XA_CSR$M_IE,XA_CSR(R4)

G"10C$DIAGBUFILL

XA_REGISTER
RO,7¢%
G"ERLS$DEVICERR

7%:

BSBW
BLBS
JSB
JSB
MOVL
MOVZHWL
BISB
REQCOM

ENBINT
6%:

XA_CSR(R4),R0

;

Fetch byte count

; Make byte count into word count
loading CSR later

20%:

#"C<XA_CSR$M_FNCT>,R0

BISW

#XA_CSR$M_TE'XA_CSR$M_ATTN,RO

;

Interrupt

Set

BICW

#¢<XA_CSR$M_FNCT>,RO

;

Yes,

BISB

BBC

IRP$L SEGVBN(R3),R0

Sh#10$V_ DIAGNDSTIC R1, 23$

BISW

#XA_CSR$M_MAINT,RO

;7
;

Check for maintenance function
Set maintenance bit in CSR image

mode

block

mode

Clear

new

CSR?

and

word

bits

Enable

S"#I0$V_SETFNCT,R1,20%

FNCT

Set

BBC

this

23%:
s

BICW

FNCT

bits

value

request?

MOV

RO,UCB$N_XA_CSRTMP(R5)

; Save CSR image in UCB

BRW

WORD_MODE

;

BBC

ATTN

S*"#10$V_WORD,R1,BLOCK_MODE

;

Check

Branch

word

handle

block

word

mode

BLOCK

MODE

FUNCTIONAL

Process

This

routine

and

function

address,

registers

Start

Block

Mode

(DMA)

the

buffer

transfer

request

DESCRIPTION:

Set

takes

modifier

allocates
and

fields

the

starts

UBA

the

address,
from

map

the

buffer
IRP.

registers,

size,

fucntion

calculates

loads

the

code,

the

DR11-W

UNIBUS

device

request.

UBA
transfer

BLOCK_MODE
:
i

T0$M_CYCLE

subfunction

specified,

set

CYCLE

bit

CSR

CYCLE

bit

CSR?

#10$V_CYCLE,R1,25%

BISW

#XA_CSR$M-CYCLE,UCB$N_XA_CSRTMP(R5)

Allocate

UBA

data

path

and

map

;

Set

BBC

;

yes,

image
or

into

CSR

image

registers

25¢%:

REQDPR
REQMPR
LOADUBA
;

Calculate

;

map

;
;
;

the

UNIBUS
address

MOVZWL
MovL
INSV

100¢%:

transfer

address

and

offset.

byte

Request UBA data path
Request UBA map registers
Load UBA map reqisters

for

the

DR11-W

from

UCB$W_BOFF(R5),R1

;i Byte offset in
UCB$L_CRB(R5),R2
; Address of CRB
CRBSL_INTD+VEC$W_MAPREG(R2),#9,#9,R1

first

EXTZV

#16,#2,R1,R2

;
s

Insert page number
Extract bits 17:16

CMPB

#DT$_DR11W, -

BEQL
MOVW
CLRL

UCB$B_DEVTYPE(RS)
100$
R2,UCB$W_XA_BAETMP(RS)
R2

:
;

then branch.
Save value of BAE

;

Clear

ASHL

#XA_CSR$V_XBA,R2,R2

;

this

XBA

Shift

the

UBA

page

bus

xfer

address

DR11-W,

bits

extended

prior

memory

bits

transfer

for

CSR

BISW
BISW
BICW3

#XA_CSR$M_GO,R2
Set "GO" bit into CSR image
R2,UCB$W_XA_ CSRTMP(RS)
; Set into CSR image we are building
#<XA CSR$M_GO!'XA_CSRs$M_ CYCLE) UCB$W_XA_CSRTMP(R5),R0

BICW3

; CSR imaqge less
#XASK_FNCT2,UCB$W_XA_CSRTMP(RS5),R2
: CSR

MOVIW

R1,UCB$W_XA_BARTMP(RS)

this

Save

BAR

juncture:

;

CSR

image

low

CSR

image

less

bits

less

"GO"

and

“CYCLE"TM

transfer

bus

FNCT

bit

A-12

address

for

"GO" and "CYCLE"
image less FNCT bit

error

logging

UCB$L_XA_DPR(RS) = transfer count in words

UCB$W_XA_CSRTMP(RS) = CSR image to start transfer with

Set DR11-W registers and start

transfer

wuE

DR11-W CSR.
Note that read-modify-write cycles are NOT performed to the
tently setting
inadver
s
prevent
This
into.
y
The CSR is always written directl
the EIR select flag (writing bit 15) if error happens to become true.
: Disable interrupts (powerfail)
DSBINT
UCB$L_XA_DPR(RS5), XA_WCR(R4)
; Load negative of

MNEGW

MOVW

#DT$_DR11W, -

CMPB

UCB$B_DEVTYPE(RS)

200¢

BEQL

200¢:
26$:

transfer count

: Load low 16 bits of bus address

R1,XA_BAR(R4)

MOVW

UCB$W_XA_BAETMP(RS5), -

MOVW

RO, XA_CSR(R4)

MOVW
BRB

R2,XA_CSR(R4)
126$%

XA_BAE(R4)

If this is a DR11-W,

‘

then branch.

: Load high bits of bus address

#XA$V_LINK,UCB$L_DEVDEPEND(R5),26% ; Link mode?

BBC

; Only if link mode in dev characteristics

UCBS$W_XA_CSRTMPC(RS),XA_CSR(R4) ; Move all bits to CSR
: Wait for transfer complete interrupt, powerfail, or device time-out

126%:

MOVW

WFIKPCH XA_TIME_OUT,IRP$L_MEDIA(R3) ; Wait for interrupt

Device has

interrupted,

FORK

s+ FORK to lower IPL

I0FORK

R1,UCB$L_XA_DPR(RS)

EXTZV

#VEC$V_DATAPATH, -

#VEC$S_DATAPATH, -

BEQL

300¢

BRB

310¢

EXTZV
INSV
CMPW
BGTR
MOVL
CLRL

DECL

CMPV

BGTR

MOVL

Purge UBA buffered data path

Branch if no datapath error
Flag parity error on device
Flag PDR error for log

Save .data path register in UCB

Get Datapath register no.
For Error Log

: Save for later in UCB
#9,#7,UCB$W_XA_BAR(R5),R0 ; Low bits, final map register no.
: If this is a DR11-MU,
#DT$_DR11W, -

RO,UCB$W_XA_DPRNCR5)

MOVZWL

;

Assume success, store code on stack
Clear DPR number and DPR error flag

CRB$L_INTD+VEC$B_DATAPATH(R3?,R0

MOVB

EXTZV
CMPB

300¢%:
310¢:

e
N

MOVL

#SS$_PARITY,(SP)
UCB$W_XA_DPRN+1(R5)

WME

RO,27$

mMovzZWL
INCB

27¢%:

BLBS

PURDPR

#SS$_NORMAL,-(SP)
UCB$W_XA_DPRNC(RS)

MOVZWL
CLRW

; Handle request completion, release UBA resources, check for errors

UCB$B_DEVTYPE(RS)

,R1
UCB$W._XA_BAE(RS)

then branch.

; Fetch high bits of map register no.

#4 ,#2 UCB$W_XA_CSR(R5),R1 ; Hi bits of map register no.
; Entire map register number
R1,#7,#2,R0
: Is map register number in range?
RO, #496
s No, forget it - compound error
28%
; Save map register contents
PR(R5)
" (R2)L[RO1,UCB$L_XA_FM
; Assume no previous map register
UCB$L_XA_PMPR(RS)
: Was there a previous map register?
RO
#VEC$V_MAPREG, #VEC$S_MAPREG, CRB$L_INTD+VEC$W_MAPREG(R3),R0

28¢

; No if gtr

(R2)IR01,UCBS$L_XA_FMPR(RS)
; Save previous map register contents

A-13

28%:

RELMPR

;

Release

UBA

RELDPR

Check

30¢%:

35¢:

for

errors

and

return

resources

status

TSTW
BEGL
MOVZWL

30¢

BBC

#XA_CSR$V_ERRDR,UCB$N_XA_CSR(R5),35$

UCB$W_XA_WCR(RS)

;

All

words

#SS$_OPINCOMPL,
(SP)

3
;i

Yes
No,

flag

transferred?
operation

;

Branch

not

complete

CSR

error

bit

MOVZWL

UCB$W_XA_ERRORCRS)
(SP)
,

BSBW
BLBS

XA_DEV_RESET
(SP),40¢

;
i

Reset DR11-W
Any errors after

CMPW
BNEQ

(SP),#S5S$_OPINCOMPL
37%
'

;
;

Log the error, unless this is
a DRV11-WA running in link mode
and the operation is incomplete,
in which case it is an expected
error and notl worth logging.

CMPB

JSB

40% :

BSBW

Flag

#DT$_DR11W, -

3
;

*XA$V_LINK, -

;
UCB$L_DEVDEPEND(RS5),40$

G"ERL$DEVICERR
DEL_ATTNAST

JSB

G"IOC$DIAGBUFILL

MOVL

(SPY+,R0
#2 ,UCB$W_XA_WCRC(RS),R1

MULW3
ADDW

INSV
MOVL
BISB
REQCOM
.DSABL

UCB$W_BCNT(R5),R1
R1,#16,#16,R0
UCB$W_XA_CSR(R5),R1
#XA_CSR$M_IE,XA_CSRC(R4)
LSB

for

controller/drive

error

status

UCB$B_DEVTYPE(RS)
37¢

BEQL
BBS

37%:

;

all

this?

...

;

Log

the

error,

;

Deliver

Fill

;
;

Get final
Calculate

outstanding

diagnostic

Insert

;

Return

1
i

Enable
Finish

ATTN

buffer

device status
final transfer

AST’s

count

into

high byte of I0SB
and EIR in 10SB
interrupts
request in exec

CSR

WORD

MODE

Process

word

mode

FUNCTIONAL

(interrupt

per

word)

transfer

DESCRIPTION:

IEVT

APEY

IPET

T4+
4

Data

one

word

time

with

uR
ae
W
U
WU

wails

WS
M
W

Dispatch

CMPB

for

DR11-W

interrupt

and

the

IDR

for

transferred

WORD

MODE

into

LSB

separate

loops

READ

#10$ _READPBLK,R2
30¢

WRITE

;

Check

;++

interrupt

If the unsolicited interrupt flag is set,
the first word
directly into memory withou waiting for
an interrupt.

BEQL

each

word.

The request is handled separately for a
write (from memory to DR11-W
and a read (from DR11-W to memory).
For a write, data is fetched from memory,
loaded into the ODR of the
DR11-W and the system waits for an interru
pt.
For a read,
the system

.ENABL
WORD_MODE
:

;

transferred

WRITE

Write

Coutput)

word

mode

for

read

function

memory.

transferred

FUNCTIONAL

DESCRIPTION:

Transfer the requested number of words from user memory to
the DR11-W ODR one word at a time, wait for interrupt for each

word.

10¢:

; Get two bytes from user buffer
i Lock out interrupts

BSBW
DSBINT

MOVFRUSER

MOVW
MOVIW
BBC
BICW3

; Move data to DR11-W
R1,XA_0ODR(R4)
UCB$W_XA_CSRTMP(RS),XA_CSR(R4) ; Set DR11-W CSR
#XA$V_LINK,UCB$L_DEVDEPEND(RS),15¢% ; Link mode?
#XA$K_FNCT2,UCB$W_XA_CSRTMP(R5),XA_CSR(R4)

interrupt

expected

;

Flag

;
;

Clear interrupt FNCT bit 2
Only if link mode specified

15%:

; Wait for interrupt, powerfail, or device time-out
WFIKPCH XA_TIME_QUTW, IRP$L_MEDIA(R3)

i Check for errors, decrement transfer count, and loop til complete
I0FORK
CMPB

#DT$_DR11W, -

BEQL

17%

BBC

17¢:

BRW

BITW’

UCB$B_DEVTYPE(RS)

#XA_CSR$V_ERROR, -

UCB$W_XA_CSR(R5),20¢%
40¢
#XA_EIR$SM_NEX!-

: DRV11-WA - check ERROR bit in CSR.
Branch on success.
Branch on error.

:
:+

XA_EIR$SM_MULTI!XA_EIR$M_ACLO!
XA_EIR$M_PAR!

BRUW

XA_EIR$M_DLT,UCBSW_XA_EIR(RSE) ; Any errors?
: No, continue
20¢
: Yes, abort transfer.
40¢$

BNEQ

10¢

BEQL

20¢%:

s Fork to lower IPL
:+ Branch if this is a DR11-W

DECW

UCB$L_XA_DPR(RS)

; No,

: All words trnasferred?

loop until finished.

: Transfer is done, clear iterrupt expected flag and FORK
Finish 1/0.
: All words read or written in WORD MODE.
RETURN_STATUS:

22%:

G"IOC$DIAGBUFILL

MULW3
SUBW3
INSV

#2,UCB$L_XA_DPR(R5),R1
R1,UCB$W_BCNT(RS5),R1
R1,#16,#16,R0

MOVL
BISB

REGCOM

4+
P+

Fill diagnostic buffer if present
Deliver outstanding ATTN AST’s

JSB

BSBW
MOVZWL

DEL_ATTNAST
#SS$_NORMAL,RO

Complete

success

status

i Calculate actual bytes xfered
: From requested number of bytes
s And place in high word of RO
3

: Return CSR and EIR status
UCB$W_XA_CSR(R5),R1
; Enable device interrupts
R(R4)
_IE,XA_CS
#XA_CSR$M

: WORD MODE READ -- Read (input)

;

Finish request in exec

in word mode

A-15

w3l

DESCRIPTION:

FUNCTIONAL

OIS

Transfer the requested number of words from the DR11-W IDR into
user memory one word at a time, wait for interrupt for each word.
If the unexpected (unsolicited) interrupt bit is set, transfer the
received)

word

memory

without

;

out

waiting

for

first (last
interrupt.

30¢:

DSBINT
;

;

for

;

waiting

UCB$B_DIPL(RS)

unexpected
this
for

(unsolicited)

READ
an

BBCC

request

and

Lock

interrupt

return

has

value

interrupts

occurred,

user

assume

buffer

without

interrupt.
#UCB$V_UNEXPT,
-

UCB$W_DEVSTS(RS5),32%
ENBINT

BRB

37%

SETIPL

#IPL$_POWER

;

Branch

;

Enable

interrupts

unexpected

continue

interrupt

32%:
35¢%:
;

Wait

for

interrupt,

WFIKPCH
;

Check

for

powerfail,

device

time-out

XA_TIME_OUTW,IRP$L_MEDIACR3)

errors,

decrement

itransfer

count

I0OFORK

and

Fork

;

Branch

loop

until

lower

done

IPL

37$:

CMPB

#DT$_DR11W, -

BEQL

UCB$B_DEVTYPE(RS)
1037%

BBC

#XA_CSR$V_ERROR, -

UCB$W_XA_CSR(RS5),1038¢%
1037¢:

BRW

40¢%

BITHW

#XA_EIR$SM_NEX!
-

;

Send

this

DRV11-WA

Branch

XA_EIR$M_MULTI!
XA_EIR$M_ACLO!
XA_EIR$M_PAR!
XA_EIR$M_DLT,UCB$W_XA_EIR(RS)
i038¢:

;

errors?

Yes,

abort

BSBW

MOVTOUSER

;

Store

two

sender.

Acknowledge

got

DR11-W

ERROR

Any

;

bit

CSR.

success.

error.

40%

back

check

BNEQG

interrupt

transfer.
bytes

into

last

word.

user

DSBINT
MOVW
BBC
BICW3

UCB$W_XA_CSRTMP(R5) ,XA_CSR(R4)
#XA$V_LINK,UCB$L_DEVDEPEND(RS5),38% ; Link mode?
#XASK_FNCT2,UCB$W_XA_CSRTMP(R5) ,XA_CSR(R4)
; Yes,

DECW

UCB$L_XA_DPR(R5S)

buffer

clear

FNCT

38¢%:

Error

BNEQ
35¢
ENBINT
BRW
RETURN_STATUS
detected in word mode

40¢:

Decrement

;

Loop

until

all

;

Finish

request

ATTN
reset

transfer

words
in

count

transferred

common

code

transfer

BSBW

DEL_ATTNAST

;

Deliver

BSBW

XA_DEV_RESET

;

Error,

JSB

G"I0C$DIAGBUFILL

A-16

Fill

AST’s
DR11-W

diagnostic

buffer

presetn

JSB
MOVZHWL
BRW

G"ERL$DEVICERR

.DSABL

LSB

Log device error

;

: Set controller/drive status in RO

UCB$W_XA_ERRORCRS),R0
22%

MOVFRUSER - Routine to fetch two bytes from user buffer.

INPUTS:
=

address

UCB

OUTPUTS:

R1 = Two bytes of data from users buffer
Buffer descriptor in UCB is updated.
LSB

.ENABL
MOVFRUSER:

3.- il AE WS WME U M AU UR US W U Wl

Address of temporary stack loc

-(SP),R1

MOVAL
MOVZBL
JSB
MOVL
BRB

Fetch two bytles

#2,R2

G"I0OC$MOVFRUSER

; Call exec routine to do the deed

208

; Update UCB buffer pointers

Retreive the bytes

(SP)+,R1

MOVTOUSER - Routine to store two bytles into users buffer.
INPUTS:

UCB

address

UCB$W_XA_IDR(R5) = Location where two bytes are saved
OUTPUTS:

Two bytes are stored in user buffer and buffer descriptor in
UCB

OVTOUSER:
MOVAB
MOVZBL
JSB

20%:

ADDW
BICW
BNEQ
ADDL

updated.

: Address of internal buffer

UCB$W_XA_IDR(RS5) ,R1
#2,R2

G"10C$MOVTOUSER

;

Call

exec

Update buffer pointers

in UCB

s Add two to buffer descriptor

#2 ,UCB$W_BOFF (R5)

#*C<"X01FF>,UCB$W_BOFF(R5)

; Modulo the page size

s If NEQ, no page boundary crossed

30¢

;

#4 ,UCB$L_SVAPTE(RS)

Point to next page

30¢%:

RTY IR Y

IEPEY

JEPTY

BVY

BRVY|

RSB

.DSABL

LSB

.SBTTL

DR11-W DEVICE TIME-OUT

DR11-W device TIME-OUT

If a DMA transfer was in progress,

release UBA resources.

For DMA or WORD mode, deliver ATTN AST’s, log a device timeout error,

and do a hard reset on the controller.
Clear

DR11-W

CSR

Return

error

status

Power

failure

will

appear

device

time-out

.ENABL.
XA_TIME_OUT:

LSB

SETIPL
PURDPR

;

Time-out

;
i
;
;
s

Lower
Purge

Release UBA
continue

Time-out

UCB$B_FIPL(RS)

RELMPR

RELDPR
BRB

10¢%

XA_TIME_QUTW:

SETIPL
MOVL

10%:

BSBW

XA_REGISTER

JSB

GTM"IOC$DIAGBUFILL

JSB

G"ERL$DEVICTMD

BSBW
BSBW
MOVZWL
BBC

transfer

Read

;

Log

F1l1l

data

for

FORK

DR11-W

mode

transfer

IPL
of

CSR

registers

diagnostic

device

path

WORD

address

UBA

time

buffer
out

DEL_ATTNAST
; And deliver the AST’s
XA_DEV_RESET
; Reset controller
#SS$_TIMEOUT,RO
;i Assume error status
#UCB$V_CANCEL,
UCB$W_STS(RS5),20$
; Branch if not cancel
#SS$_CANCEL,RO
;7 Set status
R1
#UCB$M_ATTNASTYUCB$M_UNEXPT,UCB$SW_DEVSTS(R5)

:
MOVZWL

20%:

;

DMA

to FORK IPL
buffered data path in
Release UBA map registers

UCB$B_FIPL(RS)
; Lower
UCB$L_CRB(R5),R4
;s Fetch
@CRB$L_INTD+VEC$L_IDB(R4),R4

MOVL

for

CLRL
BICW

s Clear unwanted flags.
#<UCB$M_TIM!UCB$M_INT!UCB$M_TIMDUT!UCB$M_CANCEL!UCB$M-PDNER>,—

BICW

UCB$W_STS(RS)

REQCOM

;

.DSABL

LSB

.SBTTL

XA_INTERRUPT,

Interrupt

Clear unit status flags
Complete I/0 in exec

service

routine

for

DR11-W

s+ +
7

XA_INTERRUPT,

Handles

interrupts

generated

DR11-W

1
7

Functional

description:

7
»

1
.

7
-

?
.

7
[

1
.

1
"

7
.

This routine is entered whenever an interrupt is generated
by the DR11-W.
It checks that an interrupt was expected.
If not,
it sets the unexpected (unsolicited) interrupt flag.
All device registers are read and stored into the
UCB.
If an interrupt was expected,
it calls the driver back at its
For Interrupt point.
Deliver ATTN AST’s if unexpected interrupt.

3
.

]

Inputs:

]
.

7
.

]
)

7
.

7
-

?
-

1
-

)]
.

7
-

7
.

00(SP)

Pointer

04(SP)

=
=

saved
saved

RO
R1
R2

08(SP)
12(SP)

16(SP)
20(SP)

24(SP)
28(SP)
32(SP)

saved

=
=

saved
saved

RS
PSL

saved

address

the

device

IDB

Wait

JUE

OQutputs:

The

driver

The

current

was

called

expected.

value

its

Wait

For

Interrupt

the DR11-W CSR’s

are

point

stored

the

UCB.

interrupt

XA_INTERRUPT:
MOVL
MOVa
;

Read

the DR11-W device

into

UCB.

BSBW
;
s

;
;
:

@(SP)+,R4
(R4),R4

registers

XA_REGISTER

;

Clear

208$:

unexpected

BBCC

interrupt

flag.

BAR,

;

CSR,

EIR,

IDR)

and

store

Read device registers

request active or not
for Interrupt point and

#UCB$V_INT,UCB$W_STS(R5),25%$
;s If

Interrupt expected,

;

(WCR,

Check to see if device transfer
If so, call driver back at Wait

Interrupt service for DR11-W
Address of IDB and pop SP
CSR and UCB address from IDB

clear,

interrupt

expected

clear unexpected interrupt flag and call driver

back.

#UCB$M_UNEXPT,UCB$W_DEVSTS(RS)
i Clear

BICW

:
;s

UCB$L_FR3(R5),R3
@UCB$L_FPC(RS5)

MOVL
JSB

unexpected

interrupt

Restore drivers R3
Call driver back

flag

30¢

BRB

: Deliver ATTN AST’s if no interrupt expected and set unexpected
flag.

interrupt

;

25¢%:

BISW

#UCB$M_UNEXPT,UCB$W_DEVSTS(RS)

UCB$W_DEVSTS(R5),30%

DEL_ATTNAST
#XA_CSR$M_IE,XA_CSR(R4)

;
i

Restore registers
Return from interrupt

.SBTTL

XA_REGISTER - Handle DR11-W CSR transfers

#*M¢RO,R1,R2,R3,R4,R5>»
,

XA_REGISTER - Routine to handle DR11-W register transfers
INPUTS:

; Set unexpected interrupt flag

Deliver ATTN AST’s
Enable device interrupts

POPR
REI

30%:

;
;

(DRV11-WA only.)

Restore registers and return from interrupt

;

Ignore spurious interrupt -

#UCB$V_IGNORE_UNEXPT, -

BSBW
BISB

;

BBSC

R4
RS

DR11-W CSR address
UCB address of unit

e
B

CSR,

EIR,

The

DR11-W

OUTPUTS:

WCR, BAR, BAE,
IDR, and status are read and stored into UCB.
is placed in its initial state with interrupts enabled.

.true.

hard

error

(cannot

clear

ATTN)

the

CSR

ERROR

bit

set

and

the

associated

condition

can

cleared,

then

the error is transient and recoverable.
The status returned is SS$_DRVERR.
If the CSR ERROR bit is set and cannot be cleared by clearing the CSR,
then

this is a hard
SS$_CTRLERR.

error

and

cannot

recovered.

The

returned

status

.false.

destroyed,

all

other

registers

preserved.

RO,R1

XA_REGISTER:

55¢:

MOVZWL
MOVZWL
MOV

#SS$_NORMAL,RO
XA_CSR(R4),R1
R1,UCBSW_XA_CSR(RS)

BBC

#XA_CSR$V_ERROR,R1,55¢%

;

Branch

MOVZWL

#SS$_DRVERR,RO

;

Assume

'"drive"

BICW
CMPB

57¢%:

59¢:

60¢:

70¢%:

#"C<XA_CSRS$SM_FNCT>,R1

;
3

#DT$_XA_DRV11UWA, -

UCB$B_DEVTYPE(RS)

Assume success
Read CSR
Save CSR in UCB

Clear
If

all

later

this

57%

BISB

#¢<XA_CSR$M_ERROR/256>,XA_CSR+1(R4)

;

MOVIW

XA_EIRCR4)> ,UCB$W_XA_EIR(RS)

EIR

59¢%

BISW

#XA_CSR$M_IE,R1

then
;

error

for

DRV11-WA,

branch.

Save

Set

EIR

flag

UCB
if

;

the

DRV11-WA,

0->1

transition

Spurious

;

Therefore,

;

times.

;

Clear

;

Flag

XA_CSR(R4),R1
#XA_CSR$V_ATTN,R1,60¢%

MOVZWL

#SS$_CTRLERR,RO

MOVIW
MOVIW
CMPB

XA_IDR(R4) ,UCB$W_XA_IDR(R5) ; Save IDR
XA_BAR(R4) ,UCB$W_XA_BARC(RS)
#DT$_DR11W, ; If this is a

BEQL
MOV

UCB$B_DEVTYPE(RS)
:
708
:
XA_BAE(R4) ,UCB$W_XA_BAE(RS)

MOVIW
MOVIW

XA_WCRC(R4) ,UCB$W_XA_WCR(RS)
RO,UCB$W_XA_ERROR(CRS)
; Save

leave

EIR flag and
Read CSR back
If attention still
hard

the

while

interrupt

MOVUW
MOVW
BBC

R1,XA_CSR(R4)

error

uninteresting bits

BEQGL

BRB

makes

high

errors

set,

hard

error

UCB

RSB

Cancel

1/0

routine

XA_CANCEL,

Cancels

I/0

Functional

description:

operation

progress

Flushes Attention AST queue
If transfer in progress, do
request.

Clear

interrupt

expected

for

the

device

flag.

LT]

.SBTTL

A-20

user.

reset

DR11-W

all

DR11-W,

then branch.
; Save BAE in

status

bit

generated.

controller

READY=1,

and

finish

the

negated value of channel
address of current IRP

:
3

R2
R3

=
=

= address

;

Outputs:

index

R4 = address of the PCB requesting the cancel

;

the device’s

UCB

XA_CANCEL:
#UCBS$V_ATTNAST,

BBCC

ATTN

Finish all

UCB$W_DEVSTS(R5),20%
AST’s

ithis

for

R2,R6
UCB$L_XA_ATTN(RS) ,R7
G"COM$FLUSHATTNS
#"M¢R2,R6,R7>

POPR

ATTN AST enabled?

process.

#"M¢R2,R6,R7>

PUSHR

MOVL
MOVAB
JSB

; Set up channel number
i Address of listhead
3 Flush ATTN AST’s for process

Check to see if a data transfer request
for this process on this channel

:
i

20¢:

DSBINT
BBC

JSB

Force

ue
WU

I/0 not

in progress

G"IOC$CANCELIO

Check

UCB$W_STS(R5),30%

Branch if not for

#UCB$M_TIMOUT,

UCB$W_STS(RS)

;

ENBINT

if transfer going
'

this guy

DEL_ATTNAST,

Deliver

Clear timed out

Lower to FORK IPL

Return

ATTN AST’s

DEL_ATTNAST, Deliver all outstanding ATTN AST’s

WE
U
WU
dE
S
U

;s clear timer
UCB$L_DUETIM(RS)
#UCB$M_TIM,UCB$W_STS(RS) ; set timed

.SBTTL

Functional

description:

This routine is used by the DR11-W driver to deliver all of the
It is copied from COM$DELATTNAST in
outstanding attention AST’s.
the saved value of the DR11-W CSR
places
it
addition,
In
the exec.
and Input Data Buffer Register in the AST paramater.

WME

: Lock out device interrupts
br

RSB

Inputs:

in progress

timeout

BICW

UCB

DR11-W

unit

is5

;

#UCB$V_INT, -

#UCB$V_CANCEL, -

CLRL
BISW
30¢

UCB$B_DIPL(R5)
UCB$W_STS(R5),30%

BBC

I1/0

Cancel

A-21

Outputs:

Destroyed
Preserved

RO,R1,R2
R3,R4,R5

DEL_ATTNAST:

108 :

DSBINT

UCB$B_DIPL(R5)

BBCC

#UCB$V_ATTNAST ,UCB$W_DEVSTS(RS5),30%

PUSHR

#"M¢R3,R4,R5)>

MOVL

MOVAB
MOVL
BEQL
BICW

8CSP),R1

AST

)

ATTN

AST’s

expected?

Save R3,R4,RS5

. Get address of UCB

of ATTN AST listhead
of next entry on list
entry, end of loop

MOVIW

UCB$W_XA_CSR(R1),ACB$L_KAST+4(R5)

PUSHAB

B"10$

;

fork

interrupt

Store

IDR

AST

paramater

CSR

AST

paramater

Store

Set

return

;

FORK

for

address

this

for

flag

FORK

AST

procedure

MOvVa

ACB$L_KAST(RS5),ACB$L_AST(R5)

MOVB

;i
Re-arrange
ACB$L _KAST+8(R5),ACB$B_RMOD(RS)

ACB$L_KAST+12(R5),ACB$L_PID(CRS)
ACB$L _KAST(RS)
#PRI$_I10COM,R2
;i Set up

JMP

G"SCH$QAST

20$:

POPR

30¢:

ENBINT
RSB

#"M¢R3,R4,R5)>

;

‘

XA_REGDUMP

DR11-W

Queue

entries

priority

the

AST

increment

;

Restore

registers

Enmable

interrupts

Return

dump

routine

-SBTTL
+

Any

i Clear unexpected
(R5),(R2)
; Close list
UCB$W_XA_IDR(R1) ,ACB$L_KAST+6(R5)

CLRL
MOVZBL

IPL

MOVL
MOV

MOVL

XA_REGDUMP

DR11-W

dump

routine.

This routine is called to save the controller registers in a specified
buffer.
It is called from the device error logging routine and from the
diagnostic buffer fill routine.
Inputs:

RO
R4
RS

Address
Address
Address

of
of
of

Outputs:
The

controller

registers

are

saved

the

specified

CSRTMP

BARTMP

WUE

Device

UCB$L_XA_ATTN(R1),R2
Address
(R2),R5
Address
20¢
;i No next
#UCB$M_UNEXPT,UCB$W_DEVSTS(R1)

FORK
.

The

last command written to
by the driver.
The last value written into
the

driver

during

A-22

block

the
the

mode

buffer.

DR11-W

CSR

DR11-W

BAR

fransfer.

CSR - The CSR
EIR - The EIR
IDR - The IDR
BAR - The BAR

WCR

Word

image
image
image
image

count

the
the
the
the

at
at
at
at

last
last
last
last

interrupt
interrupt
interrupt
interrupt

ERROR - The system status al request
PDRN

UBA Datapath

DPRF

Flag
0 =

number

completion

UGS

DPR - The contents of the UBA Data Path register
FMPR - The contents of the last UBA Map register
PMRP - The contents of the previous UBA Map register
datapath
datapath

for purge
no purger

error
error

MNP

1 = parity error when datapath was purged
v
BAETMP - The last value written to the BAE by the
driver during a block mode transfer (DRV11-WA only)
BAE - The BAE image at the last interrupt (DRV11-WA only)

Note that the values stored are from the last completed transfer
operation. If a zero transfer count is specified, then the
values are from the last operation with a non-zero transfer count.

:
XA_REGDUMP

#8,R2

;
;1
;

15 registers are stored.
Get address of saved register images

SOBGTR
MovZBL
MOVZBL

R2,10%

Move

#3,R2

SOBGTR
MOVZBL
MOVZWL

R2,20¢

#15,(R0O) +
UCB$W_XA_CSRTMP(R5),R1

MOovZBL
MOVAB
MOVZBL

10¢$:

20¢$:

(R1>+,(RO)+

MOVZWL

UCB$W_XA_DPRN(R5),(R0)+

XA_DEV_RESET - Device

reset DR11-W

And 3 more here

Move UBA register contents

DR11-W Device

reset

routine

XA_DEV_RESET

This routine
the required

raises IPL to device IPL, performs a device reset
controler, and re-enables device interrupts.

.SBTTL

them all

Save Datapath Register number

UCB$W_XA_DPRN+1(R5),(R0)+ ; Save Datapath Parity Error Flag
UCB$W_XA_BAETMP(R5),(R0)+ ; Save BAE stored prior to xfer
: Save BAE store following xfer
UCB$W_XA_BAE(RS), (RO)+

MOVZWL
RSB

Inputs:

R4 - Address of Control and Status Register
R5

Address

UCB

Outputs:

Controller is reset, controller interrupts are enabled

WME

WSE

;

(R1)+,(RO)+

MOVL

;

Return 8 registers here

A-23

XA_DEV_ RESET:

PUSHR

#"M¢RO,R1,R2>

DSBINT

CMPB

#DT$_DR11W, -

;

BEQL

UCB$B_DEVTYPE(RS)
20¢

;
;

MOVW

#XA_CSR$M_IE,XA_CSR(R4)
;
#XA_CSR$M_RDY, XA_CSR(R4);

BITB
BNEQ
MNEGW

BRB

#1,XA_WCR(R4)
#XA_CSR$M_CYCLE/256,
XA_CSR+1(R4)
30¢

MOVB
CLRB

XA_CSR+1(R4)

MOVB

«
1

K XH®

30¢:

Must

interrupts

then branch.
Clear all writeable bits but
If not READY then no xfer in

IE.

progress,

So no need to reset device
Tell it only 1 byte left to
and complete the transfer.

xfer

#¢(XA_CSR$M_MAINT/256>,XA_CSR+1(R4)

delay

TIMEDWAIT
MOVB

40¢$:

40$

Save some registers
Raise IPL to lock all
If this is a DR11-W,

ENBINT
POPR

here

depending

reset

interval

TIME=#XA_RESET_DELAY

;

No.

#XA_CSR$M_IE,XA_CSR(R4)

;

Re-enable

;

Restore
Restore

#"M¢RO,R1,R2>

micro-sec

device interrupts
IPL
registers

RSB
XA_END:

End
.END

A-24

intervals

driver

label

wait

INDEX

8640 quad receiver chip, 3-1
8641 quad transceiver, 3-1

8881 open-collector UNIBUS driver, 3-1
A

AQ00 H, 3-7, 3-13, 4-2, 6-6
AC LO
bit, 4-9
error, 3-21, 6-12
flip-flop, 6-12

data-late logic, 6-1
DMA modes, 1-10

mode (for links), 5-8
mode, 2-5, 2-7, 5-3
mode, processor control, 3-25
mode, user control, 3-26
modes, 1-5
operation, 6-11
size, 2-5, 2-7

adapter module, DR11-WC/WD, 3-5
address
bits, 3-7
lines, 3-6

address-to-UNIBUS flip-flop, 6-8
anti-static precautions, 2-1
attention
bit, 4-5, 6-14
error, 3-21
flip-flop, 3-13
hold flip-flop, 6-15

size toggle switch, 2-5

burst release
logic, 6-1
time, 2-8

time-out value, 2-7
timer, 2-7, 3-21, 6-7, 6-12
timer expired bit, 4-9

BURST RQ L, 3-5, 3-13, 3-25, 3-26, 6-6, 6-11
bus

address register (BAR), 3-7, 4-2, 6-8
address register bit <00>, 5-4

interrupt flip-flop, 3-13, 6-15

ATTENTION H, 4-5, 4-6, 6-14, 6-15
ATTN H, 3-13, 3-21

BA INC ENB H, 3-13, 6-6

bandwidth consumption, UNIBUS
(for links), 5-10
BAR bit <00>, 5-4

basic programming techniques for links, 5-4
BCO06-R flat grey MASSBUS cables, 2-13, 3-4
block mode, 1-5
BR level, 2-8

BR-level selection plug, 2-8, 6-16
buddy, 5-1

burst

control, 3-12, 3-15
grant signal, 6-16
hog mode, 1-6, 2-6
time-out value, 6-13

BUS ACLOL, 3-21, 6-12
BUS BBSY L, 3-19, 6-16
BUS CO L, 3-24
BUS Cl1 L, 3-24
BUS INIT L, 4-5
BUS INTR L, 6-16

BUS MSYN L, 6-7, 6-10, 6-13
BUS NPG H, 3-19, 6-6
BUS NPR L, 3-19, 6-6
BUS PB L, 6-13

BUS SACK L, 3-19, 6-16
BUS SSYN L, 6-10, 6-13

BUSY, 2-3, 3-5, 3-15, 3-16, 5-6, 5-7

bulkhead connector, 2-10
bulkhead panel, 2-11

INDEX-1

busy and cycle logic, 6-4
busy flip-flop, 3-18, 3-20
busy output, 6-2
byte count register, 4-1
byte transfers, 3-21, 3-24
-

data
bits, 3-7
block termination, 6-15
buffer, 3-21
deskew, 4-10
flow, 3-9
format presented to UNIBUS, 1-9
format presented to user, 1-9
format, 3-6

CO0 CNTL H, 3-13, 3-16, 3-24, 6-6
C1 CNTL H, 3-13, 3-16, 3-24, 6-6
cable characteristics, 3-1
cable color stripe, 2-14, 2-22
cable wrap-around
diagonistics, 2-4

inputs, 3-12
lines, 3-6
outputs, 3-15

transfer rates across a link, 1-9
transfer rates, 1-9
DATI, 3-9

test, 2-3, 2-12

color stripe on cable, 2-13, 2-17
computer-to-computer link,

5-1

DATIP, 3-9, 3-13, 3-16
DATO, 3-9, 3-16
DATOB, 3-9, 3-13, 3-16

control and status register (CSR), 3-7, 3-12,
3-13, 4-2, 4-3, 4-5, 4-8
control and status register function bits, 3-15
cycle and busy logic, 6-2

cycle

delay line, 6-4
flip-flop, 3-15, 3-18, 4-7, 5-7, 6-2, 6-3
inhibit flip-flop, 6-5, 6-10
timing chain, 6-1
CYCLE RQ A H, 3-12, 3-13, 3-15, 5-6, 5-7,

6-2
CYCLE RQ B H, 3-12, 3-13, 3-15, 6-2
CYCLE RQ x H, 3-15, 3-16, 3-17, 3-18, 3-20,

3-21, 4-7, 6-1, 6-5, 6-12
CZDRL diagnostic program, 2-14, 2-15
CZDRL routine BRSTDL, 2-7

D
D3 WCOF L, 6-1
D5 MATTN H, 6-14, 6-15
D6 DATA FROM BUS H, 6-1
D6 DATA TO BUS
L, 6-8
D6 END CYCLE H, 6 10
D6 END CYCLE L, 6- 13
D6 XFER CMPT H, 6- 1 0
D7 200 ns, 6-4

D7 50 ns, 6-4
D7 CCO RST H, 6-4
D7 GATED CYCLE L, 6-4
D7 SACRL L, 6-11
D7 WC CLK H, 6-4
D8 BR MASTER H, 6-16
D8 BR MASTER L, 6-16

D8 BR SACK H, 6-15
D8 BRX TO PLUG L, 6-16
D8 NPR MASTER L, 6-7
D8 SEND INTR H,
6-16

DCO13 BR arbitration chip, 6-7, 6-16
deskew, 3-18, 4-12
deskew time, 3-5
device drivers, 4-13
differential driver module DR11-WC/WD, 3-5
differential signals, 3-5
direct memory access 1/0, 1-5
direct memory access, 5-1
DMA cycle, 3-15, 3-16, 3-18
DMA device, 1-5
DMA engine, 3-19, 3-20, 3-21, 4-7, 4-10,
5-5, 6-1
DMA 1/0 (for links), &DMA operation, 6-1
DMA transfer on a link, start, 5-7
DR11-C, 4-12
DR11-W to DR11-W link, 2-4
DR11-WC/WD adapter module, 3-7
driver logic levels, 3-4
DRVI11-B, 5-1
DRV11-W, 5-1
DWBUA, 2-6

E
E105 switchpack, 2-3, 2-13, 3-15, 4-3
E120 switchpack, 2-2
E15 switchpack, 2-2

ECC error, 4-9
EIR, see error and information register (EIR)
END CYCLE H, 3-15, 3-16
error and information register (EIR), 2-5, 4-3,
4-4, 4-8

error bit, 4-7
errors that terminate data block, 6-12
errors, detected, 1-11

INDEX-2

ESDRB diagnostic program, 2-15
ESDRE diagnostic program, 2-14, 2-15

EVDRE test 32, 2-7
even addresses, 3-7

J1, 3-12, 3-15
J2, 3-12, 3-15
jumper selectable time-out values, 1-10
L

FCC compliant, 2-8
FIFO, 3-26
final installation, 2-17
FNCT 2 H, 3-15
full-duplex, 5-5
FUNCT x H, 3-25

function 1 bit (for links), 5-4
function 2 bit (for links), 5-4
function 3 bit (for links, 5-3

function bits, 4-7

function bits, control and status register, 3-20
function outputs, 3-15

less significant byte, 3-6
link arbitration, 5-5
link-mode testing, 2-20
:
linking a DR11-W to a DRV11-B or
DRVI11-W, 5-3
linking two DR11-Ws, 5-1
links, 5-1
link transfer rates, 1-9
local DR11-w, .5-1
logic levels, 3-4
logic reference level, 3-5

logic wrap-around test, 2-14
logical loopback, 2-14

go bit, 3-15, 6-1
GO H, 3-15,3-16
GO/EIR flag, 4-7
grant continuity card, 2-8
H

half-duplex, 5-5
handshaking protocol, 4-13
I

IDR, 4-13, 4-15
INIT H, 3-15
input
circuit, 3-1
data buffer, 3-8

data register, 3-12, 4-9
signals, 3-12
installation and checkout, 2-8

internal wrap-around of output data, 4-6
interrupt

driven I/O (for links), 5-5
driven 1/0, 1-5, 4-13

enable bit, 4-7
enable flip-flop, 3-13, 6-15
latency, 4-10
logic, 6-15
priority, 2-8
priority levels, 1-10
request flip-flop, 6-15
vector address, 2-2

maintenance
bit, 4-6
flip-flop, 3-15
multiplexer, 6-4
wrap-around cable, 2-13

master (for links), 5-5
mastersync enable flip-flop, 6-8, 6-10
maximum transmission distance, 5-3
module layout, 1-3
more significant byte, 3-6
multi-cycle
error, 3-21
flip-flop, 6-3

request, 4-9, 6-3
N

n-cycle
burst mode, 1-6, 2-5
burst switch, 4-9
LED, 6-11
NEX timer, 6-14

non-burst mode, 2-5
non-existent memory
flip-flop (NEX), 6-13
bit, 4-5
error (NXM), 2-8, 3-20, 6-13
non-processor request (NPR), 6-4
NPG jumper wire, 2-8
NPR arbitrator, 6-6
NPR request flip-flop, 6-4, 6-5, 6-6

INDEX-3

odd addresses, 3-7

output

circuit, 3-1

data buffer, 3-8
data register, 3-15, 4-10
data, internal wrap-around, 4-9
lines, 3-20
signals, 3-14

parity

error bit, 4-9
error, 3-21, 6-12

flip-flop, 6-13
physical characteristics, 1-11
picture frame, 2-10
power failure, 3-15, 3-21, 4-9
priority chain, 3-19
processor control of burst mode, 3-25
processor control of transfer direction, 3-24

programmed I/O (for links), 5-5
programmed 1/0, 1-5, 3-8, 4-12
programming, 4-1

characteristics, 1-11
techniques for links, 5-6

Q-bus, 5-3

Q
R

R80 trimpot, 2-7
read operations, slave sync, 6-10
reading bytes from memory, 3-21
ready

skew, 3-5, 4-10
slave (for links), 5-5
slave sync

for read operations, 6-10
for write operations, 6-10
time out, 2-6
time-out value, 6-13
software available, 1-11
special interrupt conditions (for links), 5-4
specifications, 1-9
starting a DMA transfer on a link, 5-6
status A bit (for links), 5-3
STATUS A H, 6-6
status B bit (for links), 5-3
STATUS B H, 6-6
status C bit (for links), 5-3
STATUS C H, 6-6
status inputs, 3-15
T
temperature range,

terminators, 3-1
.
time-out value, jumper selectable, 1-13
transfer direction, processor control, 3-24
transfer methods, 1-9
transfer rates accross a link, 1-9
transmission distance, 3-5
two-cycle burst mode, -6, 2-5

U
UACLO FNCT 2 H, 3-15, 3-21
UNIBUS ACLO, 3-15
UNIBUS

address bit <00>, 2-3
address line 00 (A00), 2-3
address lines, 6-8
:

bit, 4-7, 6-1
flip-flop, 3-15, 6-1
line, 3-15

address selection, 2-2
arbitrator, 6-7
bandwidth consumption (for links), 5-7
characteristics, 1-10
INIT, 3-15
NPR arbitrator, 6-5

logic, 6-1
READY H, 3-15, 3-16
receiver logic levels, 3-4
receiving end (for links), 5-5
register flag, 4-9
registers, 1-11, 4-1
related documentation, 1-12
round-robin priority, 5-5

S
selected slave, 6-7
sending end (for links), 5-5
signal termination, 3-1
significant byte, 3-9
silo, 3-26

1-11

port, 3-9

time-out value, 2-6
timing chain, 6-1
timing logic, 6-7
unpacking, 2-1
user cables testing, 2-13
USER CYCLE REQ H, 3-23
user device control of burst mode, 3-26
user interface characteristics, 1-10
user port, 3-9

INDEX-4

VAX/VMS XADRIVER, A-1
A%

WC INC ENB H, 3-13, 4-1, 6-6
word count overflow, 6-1

word count register, 3-13, 4-1, 6-1
word mode, 1-5

write operations, slave sync, 6-10
writing bytes, 3-23

XADRIVER, 4-13, A-1
XBA16 bit, 4-7
XBA17 bit, 4-7

INDEX-5

DR11-W Direct Memory Access
Interface User’s Guide

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EK-DR11W-UG-004

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