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Document:	DR11-W Direct Memory Interface Module User's Guide
Order Number:	EK-DR11W-UG
Revision:	001
Pages:	74
Original Filename:

OCR Text

EK-DR11W-UG-OOI1

DRI11-W

Direct Memory
Interface Module
User’s Guide

EK-DR1IW-UG-OOI

DRI11-W

Direct Memory

Interface Module
User's Guide

Prepared by Educational Services
of
Corporation
Equipment
Digital

1st Edition, December 1980

2nd Edition, April 1981

The material in this manual is for informational purposes and is

subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:

DIGITAL

DECsystem-10

MASSBUS

DEC

DECSYSTEM-20

OMNIBUS

PDP

DIBOL

0S/8

DECUS

EDUSYSTEM

RSTS

UNIBUS

VAX

RSX

VYMS

IAS

Page

24.1
242
2.5

INTRODUCTION ..ottt
ve e e
eea e
GENERAL. ...ttt
ettt e et e e vt e e ar e e s saaessesaae s nsaeessnsaseseasenseaenns
SUPPORTING DOCUMENTATION.......ooooiiiee ettt
FUNCTIONAL DESCRIPTION ...ttt
MAINTENANCE MODES ....................e e
COMPATIBILITY OF DR11-Band DRI1I-W....coooiiiieeieete
e,
PHYSICAL DESCRIPTION. ...ttt
ettt et

1-1
1-1
1-1
1-1
1-6
1-6
1-7

SOFTWARE INTERFACE............oooicreet ettt
GENERAL ...ttt
ettt e e e e ee e e teeesaae s ss e e s sne e s esnse e e e baaanabaesenneesane
WORD COUNT REGISTER (WCR) ..ottt
BUS ADDRESS REGISTER(BAR).......ooiieeeeeeeteeeeeeee et
INPUT DATA REGISTER/OUTPUT DATA REGISTER
(IDR/ODR) ittt
ettt s s et
Input Data Register (IDR) ...c.ccoiviiiiiiiiieeeeeeccccececcese
e,
Output Data Register (ODR).....cooeiiiiiiiiiiiieieeeeieeereereeeeereeerreeennne
CONTROL AND STATUS REGISTER/ERROR AND
INFORMATION REGISTER (CSR/EIR) ...ccccoiiiiiiiiiinieeiciireeceeeecnee,.

2-1
2-1
2-1
2-1
2-2
2-2
2-2

2.5.1

Control and Status Register (CSR)......cvevvvvreveveieerereeeereeeeeenna, e

2-2

2.5.2

Error and Information Register (EIR) .......c.cooviiiiiiiiiieececee

2-2

CHAPTER 3

I/O SIGNALS ...ttt
ettt s sa s s s

3-1

CHAPTER 4
4.1
4.2

THEORY OF OPERATION.........oocoiiieecteete
e
seee e
enaes
GENERAL. ...ttt
ee e e e et e s aa e s e e s rae e s are e e s
aeeesennesennnesengassasaees
PROGRAMMED DATA TRANSFERS ...t
INTERRUPT OPERATION ...t
eeeee et
DMA OPERATION ...ttt
ettt e e te e e s s e se e e et e e s s be e sseeeenreeeeaee

4-1
4-1
4-1
4-5
4-5

5.53

INTERFACING AND PROGRAMMING CONSIDERATIONS..........ccceeveeenen.
USER-DEVICE CABLES.......oo ettt
ese e
USER-DEVICE SIGNAL INTERFACE.........ccoooiiiiieieeeeeeeeeeeeeneees
I/O SIGNAL TIMING ..ottt
SIGNAL INTEGRITY ..ottt
ettt st
s
ssan e
PROGRAMMING CONSIDERATIONS ...ttt
cine s
DRIT-W MOGE oottt
seeeen e ee e e et e e e e s rs s
TIIMIIIE .
..ttt
rr e et e e e e e s e e e e s e e e s ssaet e e s sssa s e e sesranssnnnesennes
Programming EXample.........cooooiiiiiiiiiiiniiiniccceceerceciee e

5-1
5-1
5-1
5-1
5-2
5-3
5-3
5-4
5-4

CHAPTER 6
6.1
6.1.1
6.1.2
6.2
6.3

INSTALLATION ..ottt
eee e st e e st eebae e s b e seneeesmnesennnes
UNPACKING AND INSPECTION ...ttt
UNPACKING....cceieieeiieeieree ettt
ree s
INSPECLION. ..ceeeieeiie ettt et e e s ee e e ne e s et e s ba s e s saa s e ra e e eanneenna e
INSTALLATION PROCEDURE ...ttt
ACCEPTANCE TESTING. ...ttt
s enans

6-1
6-1
6-1
6-1
6-1
6-8

4.3

4.4

CHAPTER 5

5.1
5.2
5.3
54
5.5
5.5.1
5.5.2

1ii

CHAPTER 7
7.1
7.2

INTERPROCESSOR LINKS ...t
GENERAL ... .ottt
e e e e e e eeeeeens
OPERATING MODES ...ttt
WOTd MOGE.......oiiniiiieeeeeee

7-1
7-1
7-1

7-2

BIOCK MOdE......ooeieee et
BUTSt MOGE ...ttt
PROGRAMMING ...ttt
et ene

7-2
7-4
7-4

7.3.1

Word Count Register (WCR).....ccooooviiiiiiiieeceeceeceeeeeeeeeeeeeeeeseeeea

7.3.2

Bus Address Register (BAR)......cc.ooiuiiomiiiiceeceeeeeee
e
Output Data Register/Input Data Register
(ODR/IDRY) ittt
ettt
eae e et e e e e eee
Control and Status Register (CSR) ......ooouiiiiiiieeeeeeeeeeeeeeeeeeeeeeee
e,
Error and Information Register (EIR) .........ccooovviuiiiiiiieeeeeeeeeeeee
e,

7-4

7.2.1

7.2.2
7.2.3

7.3

7.3.3
7.3.4

7.3.5

7-4
7-4
7-6

CHAPTER 8
8.1

MAINTENANCE.......ooieeee

e e e e eee s e e ees

8-1

GENERAL ...ttt
e e ee et e eeeeeeeeaean

8-1

8.2

ABSTRACTS OF DIAGNOSTIC PROGRAMS ...

8-1

Programs for PDP-11 ..ot

8-1

Programs fOr VAX ... .ot
ee see ees

8-2

8.2.1
8.2.2

APPENDIX A
APPENDIX B
APPENDIX C

ettt

I/O SIGNAL PIN ASSIGNMENTS ..o A-1
SIGNAL CROSS-REFERENCE (DR11-B/DRI1-W) ....ccooooviiiiiiiieceeeeens B-1
DR11-B/DR11-W FUNCTIONALITY COMPARISON.......cooeoeeeeeeeeeeeenn. C-1

FIGURES
Figure No.

Title

1-1

DR11-W DMA Module M8B716.......ccccooiiiiieieiececeeeceeeeeeeeeeee
et
Simplified Block Diagram of DR11-W Used as
Interface for UNIBUS and User Device ..........oouviviiuiieeiveiieeeeeeeeeeeeeeee
e,
Interface ConfigUrations.........cc.cceceeieiiieeiiiii
et e e
Control and Status Register (CSR) .......oouviiiiiiiieeeeeeeeeeeeeeeeeeeeeeee
e
e
Error and Information Register (EIR) .......cccocviiuiiieiiiiiieiee oo eeans
DRIT-W I/O LINES....cooutiiitiienieceeteeeceeeeeeeee ettt
eee e ene e
Output Connector J1: Signal Pin ASSIgNmeENts..........cooveveuieeieeeeeeeeneeeeeeeeeeeeannas
Input Connector J2: Signal Pin ASSIZNMments............coouevveeeceeceeeeeereeeeeereeeresreeanns
DR11-W BIOCK Dia@rami......cccveeeeriieeiieceeeeeeeeeeceeeeectiee
et et
ee s e e s s e s
Addressing Decoding LOZIC .....ccocoireeureieiieieieeteeeeeeeeeeceeeee ettt

\l\l\lO\?\O\O\UI
LOLELLLE

el ~ G PO I N6 IR

SI N

PRPRPE
R @D

1-2

Page

INEEITUPE LOZIC. .. ittt
ettt e e e e

Interrupt Flow Diagram......c.ccooivioiieoieeieceeceeceeeeeee
et
Interface Circuits for Optimizing DR11-W
Signal-To-INO0ISE MATZIN....cc.eouiiiieieieceieeeececeeeeee
et
ae e eeeeeeeeneas

Setting and Clearing FNCT2 and GO Bits...........ccooieiiiiiieeeeeeeeeeeeeeeeeeeee
e
Bus-Request, Priority-Level Plug/Socket Assembly............. e rerte et e e e e e sraaeaas
Bus Address and Vector Address SwitChpacks..........ccceeevvveeeivineeneeeeereireeeeeenenne.
Operational Mode Switchpack E105.........c..cooiimeioiiieieiceeece
et
Burst Mode SWitCh Bl ..o
Interprocessor Link Block Diagram..........ccccooveeiiiiiieiiiicicicce e,
Interrupt Sequence for Word Mode Interprocessor Link.........ccccovevreiiiiennnnen..,
Block Transfer Sequence for Interprocessor Link ........ccccovieieveereeveereereeeeeeeennn,

1-3

1-4
1-5
2-3
2-5

3-2
3-5
3-6
4-2
4-4
4-6
4-8
5-3

5-4
6-3

6-4
6-7
6-8
7-1
7-3

7-3

TABLES
Table No.

Title

1-1

DR11-W Performance SpecifiCations........cccoueveveriieeiiirereeeecreeceeeeneesiressseeene
e
Nominal Transfer Rates for Typical Processor
CONFIZUTALIONS. ... etieeieeeieeeteeecteeseteeesie
e et e e s tees e e esseae st eessae s sseesastassnaeeansaaansnesssanas
CSR Register - Bit Functions.............. ereeeeeteeeeneeeeeeeeeseteeasaeeeesansteeassreeaannreasnraennns
EIR Register - Bit FUNCLIONS........coccoiiiiiiiiiiiiiiie et
Input Signals from User DeviCe.......coceeeiiiiiiiiiiiiiiieiiiniiiiiiicccicceeeeeecee
e
Output Signals t0 User DeviCe.....cooieriiiiiiiiiiieeiiintiee ettt
Available Bus-Request Priority-Level PIugs......cccccoeviiriiiniviiniiiiiiceeeeeeeee,
Switch Settings for Bus-Address Switchpack E120........ccccoviiciiiiniiiciiieeieeeee.
Switch Settings for Vector Address
SWItCHPACK E15 ..ottt
Switch Settings for Operational Mode
SWItChPACK E105 ...ttt
ettt s re e e st eae s
Correlation of CSR Function and Status Bits
in Interprocessor Link Operation.........c.ccceeviereiiiiriieneiiteeieeeeeeeteeeteeesiee
e eaea e
Signal Cross-Reference DRI11-B DRII-W it
DR11-B/DR11-W Functionality COmparison.........cccueeeereuircnienrecineeeneeeeenee
e

1-2

EXAMPLES
Example No.

Title

5-1

Typical VMS Coding Sequence for Loading the CSR
in 2a DR11-W/VAX System Configuration ...........cccoceeiiiiiiiniinciincnenencnrenrenncnes
Typical VMS Coding Sequence for Reading the
DR11-W CSR After Interrupt in the DR11-W/VAX
System COonfigUIAtion .......c..coviveeeiieiriiieiieriieereeste
et eseeesereesete e s e e s eeasseassseesses
Typical Coding Sequence for Loading the DR11-W
CSR in a DR11-W/PDP-11 System Configuration...........cccccecerernienicenenenneenuenne.
Typical Coding Sequence for Reading the CSR
After Interrupt in the DR11-W /PDP-11 System
CONFIGUIALION ...ttt
e e e ste e s et e e s e e eba e e e e ssnreeeessseeeennsenas

5-2

5-3
5-4

CHAPTER 1
INTRODUCTION

1.1

GENERAL

The DR11-W DMA Interface Module M8716 User’s Guide provides the following information:

General Introduction
Programming Details (Software Interface)
Description of I1/O Signals

Theory of Operation
Interface Considerations
Installation Procedures
Interprocessor Lines (Link Mode Operation)
Corrective-Maintenance Diagnostics Listing
1.2 SUPPORTING DOCUMENTATION
Two support documents are available for use with this User’s Guide:

1.3

Field Maintenance Print Set (MP00693)

PDP-11 Bus Handbook (EB17525-20/79-07-14-55)

FUNCTIONAL DESCRIPTION

The DR11-W is a general-purpose, UNIBUS, direct memory access (DMA) device whose principal
performance characteristics are listed in Table 1-1. The DR11-W (Figures 1-1 and 1-2):
1.

Provides the means to connect a user device to the UNIBUS of a PDP-11 or VAX computer
in either single- or multiple-DR11-W system configurations.

Provides the means to link a PDP-11 or VAX system with other PDP-11 or VAX systems.

Can be connected to a DRV11-B to provide a UNIBUS to Q-Bus system link.

An unlimited number of DR11-Ws can be used in a system if the addresses and vector selected for each
device do not conflict with the addresses and vectors of other devices.
The DR11-W is designed for installation in a single hex small peripheral controller (SPC) slot of a
system backplane located within the same enclosure, and is connected to the user device, a DRV11-B,
or another DR11-W by not more than 50 feet of cable.
In response to software commands, the DR11-W is capable of crossing 32K boundaries to transfer a

maximum block of 64K 16-bit words. Table 1-2 gives nominal transfer rates for typical processor con-

figurations (Figure 1-3.)

1-1

Table 1-1

Item

DR11-W Performance Specifications

Description

Data Transfer:
Format

16-bit word (parallel transfer)

Modes

Programmed data

Types

DATI (Read word)

Addressing capacity

128K words

Maximum block size

64K words (can cross 32K UNIBUS boundaries)

Transfer rate

See Table 1-2

DMA block (1 cycle, 2 cycles or N cycles per bus grant)

DATIP (Read word with Write to same address to follow)
DATO (Write word)
DATOB (Write byte)

User Burst Data Late Timeout

Adjustable from 4 to 40 usec to accommodate input data rate (10 to 15 usec is a

Bus Timeout

18 usec, nominal

Bus Interrupt Priority

Plug selectable for BR4 to BR7 (BRS is supplied with DR11-W)

nominal setting)

Switchpacks:

Operational Mode Selection
Bus Address
Vector Address

Switchpack E105 — 5 switches
Switchpack E120 — 10 switches
Switchpack E15 - 8 switches

I/0 Signal Lines:
To User Device
From User Device

Cables:

DR11-W/User Device
Interconnect

2 BCO6R-XX 40-conductor, 120-ohm, 1524 cm (50 ft), max.

Maintenance Wraparound

1 BCO5L-1C 40-conductor, 120-ohm 38 cm (15 in.)

Temperature:

Ambient Operating
Storage

Humidity

DC Power

5 to 50°C (41 to 122°F)
—40 to 669C (—40 to 151°F)

10 to 90% noncondensing with max. wet bulb 32°C (90°F) and minimum dew point

20C (369F)

+5 Vdc @ 3.7 A, nominal

1-2

‘H0M-ILLISHANa3)A H‘493-IHLOANYHQ

e /Nw

OADZ OADN~ ¢d.\ fiE

NIid-0t

2angy1-1 -1da@MVIA PINPOIN9T1L8IN

jtk:,j

XX-H9004

N9Hid-O8F ERA4LE! SHOLO3INOD

084y

! {SIHOLIMSG)
$S3nHAdV

1-3

GMIVd1HOL3IMS

(SAdY3GO1714Vd0Nd9S)

UNIBUS

DR11-W
(M8716)

DATA

CONTROL

DATA

USER
=P

DEVICE

CONTROL

TK-5027

Figure 1-2

Simplified Block Diagram of DR11-W Used as

Interface for UNIBUS and User Device

Table 1-2

Nominal Transfer Rates for Typical
Processor Configurations

DR11-W
UNIBUS

DR11-W
UBA

DRVI11-B
LSI Bus

500K wps

300K wps

250K wps

300K wps

400K wps

250K wps

Not applicable

DR11-W

UNIBUS
DR11-W

UBA
DRVI11-B

LSI BUS

Figure 1-2 is a simplified block diagram showing the DR11-W used in a configuration with a UNIBUS
and a user device. Figure 1-3 summarizes the DR11-W’s use in more complex arrangements that enable
use of a VAX or PDP-11 with another VAX or PDP-11. Figure 1-4 is a simplified functional block
diagram for these applications of the DR11-W,
The DR11-W can be operated in either a programmed /O or DMA mode. In programmed I/O, data is
moved to or from the user device under CPU program control. When operated in DMA mode, the
DR11-W becomes bus master via an NPR request and operates directly on the memory to satisfy
requests originated at the user device.

UNIBUS-11

DR11W

USER

DEVICE

VAX-11 UBA
2.

DR11-W

USER

»|

UNIBUS-11

DR11-W

DEVICE

UNIBUS-11

VAX-11 UBA

DR11-W

VAX-11 UBA

DR11-W

UNIBUS-11
5.

DR11-W

VAX-11 UBA
-

UNIBUS-11

DRV11-B

VAX-11 UBA
7.

DR1T-W

DR11-W

Q BUS-11

DR11-W

Q BUS-11
|

DRVI11-B

NOTE: CONFIGURATIONS 3 THROUGH 7 ARE INTERPROCESSOR
LINK SYSTEMS.
CONFIGURATIONS 6 AND 7 CANNOT PERFORM NPR
DATA TRANSFERS IN THE BURST MODE.

Figure 1-3

TK-5028

Interface Configurations

A normal DMA operation transfers one word per UNIBUS arbitration. However, DMA operation can

be extended to include transfers in either standard or nonstandard burst modes. In the standard burst
mode, two words are transferred at the completion of each UNIBUS arbitration in which the DR11-W

is granted the bus. In nonstandard burst mode operation, an unlimited number of words can be transferred after receipt of each bus grant.
The DR11-W detects memory parity errors during DATI (read word) and DATIP (read word with

intent to write same address) DMA transfers only. Error detection generates an interrupt at the end of
the current cycle and terminates the DMA operation. The error is cleared at the start of the next DMA
transfer.
For burst mode operation, optimization of DMA latency for each application is individually effected
using a screwdriver-adjusted potentiometer on the M8716 board.
DR11-W interruption of the CPU at any one of four priority levels (BR4 — BR7) is possible. A BR plug
(normally supplied as BRS for the DR11-W) provides this interrupt capability.

1-5

—

LSI-11

2
>

—_—

————

\/
PDP-11

—»| USER
DEVICE

pd
o

\/
PDP-11
OR

VAX

VAX
TK-5029

Figure 1-4

Simplified Block Diagram for DR11-W Used in
Typical Configurations

1.4 MAINTENANCE MODES
The DR11-W can be tested in either of two maintenance modes:
1.
2.

Logic wraparound
Cable wraparound

In logic wraparound testing, UNIBUS data applied to the module is gated back to the UNIBUS for

comparison checking. In this mode, all DR11-W components, except the I/O connectors and transceivers, are checked for satisfactory operation.
NOTE
Since random external patterns are generated during

this operation, the user device may need to be isolated from the DR11-W until testing is completed.

In cable wraparound testing, a BCOSL test cable (see Paragraph 1.6) is installed between the J2 input
connector and the J1 output connector, so that data is looped back to the module. This provision checks
the 1/0 connectors and transceivers of the DR11-W.
1.5 COMPATIBILITY OF DR11-B AND DR11-W
The DR11-W has two modes of operation: DR11-B mode and DR11-W mode. Both modes are set by
DIP switch 5 (E105 in Figure 1-1). In its DR11-B mode, the DR11-W is both functionally and software
compatible with the DR11-B; refer to Appendix C for mincr differences between the two interface
modules.
The DR11-W mode provides additional error-condition monitoring and enables the interprocessor link
capability. Programming the device in DR11-W mode is only slightly different from its programming in

the DR11-B mode.

For PDP-11, the DR1 1-W is supported in both modes by diagnostics for the User-Device and inter-

processor-link applications. Like the DR11-B, there is no operating system support for the DR11-W.

For VAX, the DR11-W is supported (in DR11-W mode only) by diagnostics and the VAX/VMS oper-

ating system.
1.6

PHYSICAL DESCRIPTION

Figure 1-1 shows the relative location of the DR11-W components whose adjustment or indicator status
is significant to the user during operational setup and troubleshooting. The DR11-W is configured as a
standard hex-height, multilayer, high-density module carrying the designation M8716.

The DR11-W connects to the user device via two BCO6R-XX cables. Each end of each cable is terminated by a 40-pin connector; cable impedance is 120 ohms. The BCO6R-XX cable is 1524 c¢cm (50 ft)
long, the maximum recommended length for this application.

NOTE
Approved interface cables other than DEC standard
BCO6R-XX (bare cable DIGITAL P/N 17-0003400) are Tensolite (P/N) 81-25-00-4000) or an
equivalent cable from Spectrastrip, 3m, or Brand
Rex.

The DR11-W components whose settings or status indications are of interest to the user during installation, operation, and troubleshooting are (Figure 1-1):
1.

Three dual in-line switchpacks:

E15 - vector address (eight switches, but switch 1 not used)
E105 - operational mode (five switches)
E120 - bus address (ten switches)
2.

Burst mode toggle switch B1 (2 Cycle/N cycle)

N-cycle burst LED (Red)

ATTENTION LED (Red)

E62 priority jumper (normally supplied for BRS5 priority)

Burst data late timeout potentiometer

Burst data late calibration test point (TP1)

Six programmable registers:

Address

TXXXXO0

word count register (WCR)

TXXXX2

bus address register (BAR)

TXXXX4

control and status register (CSR)

TXXXX4

error and information register (EIR) (DR11-W mode only)

TXXXX6

input data register (IDR)

TXXXX6

output data register (ODR)
1-7

The names of the vector address switchpack (E15), and the bus address switchpack (E120), denote
their functions. The operational mode switchpack (E105) permits user selection of BUSY, CYCLE INHIBIT, READY, and DR11-B/DR11-W mode.

The burst mode toggle switch is set for standard (2-cycle) or nonstandard (N-cycle) mode, as desired.

The switch position for each mode is indicated by lettering on the component side of the board adjacent
to the switch.
The N-cycle burst LED illuminates whenever the burst mode switch is set to the N-cycle position and
an NPR transfer is in progress.
The ATTENTION LED illuminates whenever a user device generates an attention signal, or the
DR11-W input cable is disconnected from the DR11-W or the user device.
The burst data late timeout potentiometer is adjustable over the range of 4 to 40 usec.

NOTE
For the VAX operating system to handle UBA zerovector interrupts, timeout should not exceed 20 usec.
Priority plug E62 enables selection of priority level BR4, 5, 6 or 7. BRS is the standard plug supplied
with the DR11-W module.

1-8

CHAPTER 2

SOFTWARE INTERFACE

2.1

GENERAL

The DR11-W uses six programmable registers (see Paragraph 1.5 for their respective addresses). The
IDR and ODR, being at the same physical address, are grouped under a single main heading below. For
the same reason, the CSR and EIR are grouped under a common main heading. The WCR and BAR,
at different addresses, are discussed under separate main headings.
2.2

WORD COUNT REGISTER (WCR)

The WCR is the first register on the DR11-W. If the DR11-W is addressed at 772410, the WCR address is also 772410. The WCR can be read or written by the CPU, and is cleared during initialization.
Prior to a data transfer, the WCR is loaded with the two’s complement of the total number of words to
be transferred. During subsequent transfers, the WCR is incremented by one for each word transferred.
Upon transfer of the last word, the WCR overflows and causes the READY flip-flop in the DR11-W
control logic to set, an action that tells the user that his transfer is complete. If DR11-W interrupts are
enabled, an interrupt occurs at this time.
2.3

BUS ADDRESS REGISTER (BAR)

The BAR, like the WCR, is word-addressable only. Continuing our example of the addressing hierarchy
(see Paragraph 2.2), if the DR11-W is addressed at 7#2410, the address of the BAR will be 772412.
The BAR can be read or written by the CPU, and is cleared during initialization. This register supplies
15 of the 18 bits used as the UNIBUS address during NPR transfers by the DR11-W. The full 18-bit
address, BA(17:00), is derived as follows:

1.
2.

Bits BA(17:16) are provided by CSR bits 5 (XBA17) and 4 (XBA16), respectively.
Bits BA(15:01) are provided by BAR bits (15:01), respectively.
BA(00) is generated by the User Device as A0O.

In link operation, the READY output of each DR11-W is coupled to the AOO input of the other DR11W. To prevent operation at an odd address, switch 4 of the operational mode switchpack E105 is set to
ON, thereby grounding the AOO input.

The BAR is normally incremented by two after an NPR data transfer, so that succeeding transfers are
made to consecutive words; i.e., the bus address is advanced by two byte-address increments after each
transfer. A user device can also select byte transfers by sending the following control signals to the
DR11-W: A00 H, CO CNTL H, and BA INC ENB H.

When the BAR overflows to all 0’s, extended bus address bits XBA17 and XBA16 are incremented.

This provision enables transfers across 32K word boundaries.

2-1

2.4 INPUT DATA REGISTER/OUTPUT DATA REGISTER (IDR/ODR)
The input and output data registers share the same address. Continuing our example (in Paragraphs 2.2
and 2.3), if the DR11-W is addressed at 772410, the address of the IDR/ODR is 772416. Writing to
this address loads the ODR; reading from this address gives the contents of the IDR. This register is

cleared during initialization.

2.4.1
Input Data Register (IDR)
During writes to the memory, the IDR buffers data received from the user device. In the programmed

I/O mode, the program can obtain this data by reading the IDR. The IDR is read to the bus as

DI(15:00).

Upon completion of a data transfer, the CPU can examine the last word transferred by reading the

IDR. This can only be done by writing a 1 to bit 15 of the CSR register to set the EIR ENB flip-flop in
the control logic. If the IDR is read with EIR ENB cleared, new data will be sampled from the user

device and clocked into the IDR. The CPU then reads this new data. Note that EIR functionality is
available in the DR11-W mode only (it is inhibited in DR11-B mode to effect compatibility).
During operation in the maintenance-logic wraparound mode, the contents of the ODR are clocked into
the IDR at the end of the DATI cycle. This data is therefore available for the subsequent DATO cycle.
2.4.2 Output Data Register (ODR)
The ODR can be written to, but not read. When the CPU writes to the IDR/ODR address, the ODR is
loaded. This register is also loaded during NPR transfers whenever the DR11-W reads from memory.
The ODR contents are read to a user device as DO(15:00) H. The ODR is cleared during initialization.

2.5 CONTROL
(CSR/EIR)

AND

STATUS

AND

INFORMATION

The CSR and EIR share the same address. Continuing our example (Paragraphs 2.2, 2.3 and 2.4), if
the DR11-W is addressed at 772410, the CSR/EIR address is 772414. Writing to this address always

writes to the CSR; the EIR is a read-only register. Reading from this address accesses the content of
either the CSR or EIR, as described below. Note again that the EIR is enabled in DR11-W mode only.
In writing to bit 15, the following rules apply:
1.

Writing a 0 results in:
a.
b.

The CSR bits are read

Bit O from this address always reads 0

Writing a 1 results in:
a.
b.

The EIR bits are read

Bit 0 always reads as a 1.

2.5.1
Control and Status Register (CSR)
Figure 2-1 shows the bit configuration of the CSR; the name and function of each bit is given in Table
2-1.

2.5.2 Error and Information Register (EIR)
Figure 2-2 shows the bit configuration of the EIR; the name and function of each bit is given in Table 22.

STATUS

AB,C***

XBA

1716

FNCT

321

T
NEX***I

ERROR*

CYCLE

ATTN ***
MAINT

READYTM**

NOTES:

1.
2.

BITSWITH NO ASTERISK ARE READ/WRITE
BITSWITH A SINGLE ASTERISK CAN BE WRITTEN AS
“1” BUT ARE ALWAYS READ AS ZERO (“0”)

BITSWITH A DOUBLE ASTERISK ARE READ ONLY

BITSWITH A TRIPLE ASTERISK ARE READ/CLEAR.
TK-5030

Figure 2-1

Control and Status Register (CSR)

Table 2-1

CSR Register: Bit Functions

Bit

Name

Function

This bit is written under program control and is always read to the bus as zero. Setting this
bit causes the DR11-W to begin its transfer.

(3:1)

FNCT 3
FNCT 2
FNCT 1

These function bits are user-defined, and specify the operation the user intends to perform.

They are read/write, and cleared during initialization.
(5:4)

XBA17
XBA16

These bits generate extended BUS
A(17:16) for NPR transfers, and are incremented when the bus address register overflows.

They are read/write, and cleared during initialization.
6

The interrupt enable (IE) bit, when set, allows an interrupt to occur if:

A GO pulse is generated after an error has been detected.

The word count register overflows at the end of a transfer.

An error condition signal is detected (i.e, ERROR, NEX, ATTN, ACLO, MULTICY
RQ, or PAR ERROR) during an NPR transfer.

A user device error signal (ATTN) is sent to the DR11-W.

IE is a read/write bit and is cleared during initialization.
7

READY

READY is a read/write bit. When set, it indicates that the DR11-W has completed the

previous operation and is ready to accept a new command. The ERROR bit must be check-

ed to determine whether or not the transfer was successful. Any error condition must be
cleared before a new command can be executed. READY is cleared by setting GO or by
initialization.

2-3

Table 2-1

Bit

CSR Register: Bit Functions (Cont)

Name

Function

CYCLE

The CYCLE bit can be set under program control to initiate one NPR operation upon setting the GO bit. CYCLE is a read /write bit that is cleared during initialization, and at the
start of a bus cycle.

(11:9)

STATUS A
STATUS B

STATUS C

These user-defined bits indicate user device status, are stored by the DR11-W, and are
read-only.

MAINT

MAINT allows diagnostic testing of the DR11-W in the logic wraparound mode. When the
MAINT, CYCLE, and GO bits are set, the DR11-W starts data transfers that continue
until the word count register overflows. During maintenance-mode testing, the DR11-W
does alternating DATI/DATO transfers at consecutive locations; i.e., a DATI from location X is followed in sequence by a DATO to location X+
2, a DATI from location X +4,
etc.. During a DATI cycle, the ODR is loaded by bus D(15:00). This data is transferred to
the IDR at the end of the cycle, where it is available for the DATO to follow. The MAINT
bit can also be used for software reset. When set, the maintenance mode is entered; when
cleared, the DR11-W is initialized. The MAINT bit is read/write and is cleared by initialization.

ATTN

The user device controls the ATTN signal and, by its assertion, indicates the on-line presence of the device. When ATTN is set, an ERROR flag is generated in the DR11-W. If IE
has been set, it causes an interrupt and, if a DMA transfer is in progress, the transfer is
stopped at the completion of the current cycle. ATTN is a read/write bit that is cleared
during initialization or at the start of the next DMA transfer. Thus, GO can be set while
ATTN is set.

NEX

NEX (nonexistent memory) indicates that the DR11-W is attempting a transfer to or from
a nonexistent bus address. NEX sets when the DR11-W asserts MSYN, but does not receive SSYN within 18 usec. NEX causes ERROR, terminates DMA operation, and if IE is
set, causes an interrupt. NEX is a read/write bit that is cleared during initialization by
writing a 0 to it, or by starting the next DMA transfer.

ERROR

ERROR is a read-only bit and is the inclusive-OR of ATTN, NEX, MULTICY RQ,
ACLO, and PAR ERROR. When ERROR s asserted, it sets READY and prevents further DMA cycles. If IE is set, an interrupt occurs. The ERROR bit can only be cleared by
removing the conditions that caused it to be set; i.e., ATTN, NEX, ACLO, MULTICY
RQ. These bits are cleared at the start of the next DMA transfer. However, ATTN and
NEX can also be cleared by writing a 0 to bits 13 and 14, respectively.

aA
=

NOT

USED

NEX***
ERROR**

BURST
N—CYCLE

MULTICY
RQ**

PAR

BURST

ERR** SW=**

NOTES:

1.
2.

3.
4.

BITSWITH NO ASTERISK ARE READ/WRITE
BITSWITH A SINGLE ASTERISK CAN BE WRITTEN AS
“1"” BUT ARE ALWAYS READ AS ZERO (“0")
BITSWITH A DOUBLE ASTERISK ARE READ ONLY
BITSWITH A TRIPLE ASTERISK ARE READ/CLEAR.
TK-5031

Figure 2-2

Error and Information Register (EIR)

Table 2-2

EIR Register: Bit Functions

Bit

Name

Function

(07:01)

Unassigned

N-CYCLE BURST When set, bit 08 flags that the N-CYCLE/2-CYCLE burst mode switch is set in its N-

CSR, is being read.

Unassigned these bits are not used in the DR11-W. They read as 0 when the EIR is read.
CYCLE (nonstandard) position. When 'the DR11-W is configured to operate in burst
mode, the N-CYCLE LED (see Figure 1-1) is lit whenever operation in burst mode is in
progress.

BURST DLT

When bit 09 (burst data late) is set, it indicates that the user device has not supplied or
removed data within the established time limit, and that the UNIBUS has been relinquished. The DR11-W is still ready to accept further cycle requests.

PAR ERR

Bit 10 (parity error) is set whenever the DR11-W detects a memory parity error during a
memory read. Bit 10 clears at the start of the next DMA transfer.

ACLO

ACLO indicates that a powerfailure occurred during a DMA transfer. ACLO sets the error. It is cleared at the start of the next DMA transfer, or during initialization.

MULTICY RQ

Bit 12 (multicycle request) is caused by a user device that sends CYCLE RQ (A or B) to
the DR11-W while the DR11-W is still processing a previous transfer. MULTICY RQ sets
ERROR and is cleared at the start of the next DMA transfer.

15:13

ERROR, NEX,

ATTN

Bits 15:13 are functionally the same as bits (15:13) of the CSR, but are displayed in the
EIR for immediate access.

CHAPTER 3

1/0 SIGNALS

Figure 3-1 shows the DR11-W I/O signal lines. Table 3-1 identifies and describes the functions of the
28 signals a user device sends to the DR11-W. Table 3-2 identifies and describes the functions of 25

signals a DR11-W sends to a user device.

NOTE

For the logic levels referenced in Tables 3-1 and 3-2,
logical H is +3 V and logical L is 0.0 V (ground).

Figures 3-2 and 3-3 give the pin identifications for I/O output connector J1 and I/O input connector

J2, respectively.

3-1

DR11-W

D(15:00)

p2<

COCNTL H

CICNTLH

INPUT

A{17:00)

(28)

DATA

UNIBUS

SIGNALS 4 J1

TRANSFER

DI<15:00>H

DEVICE
USER

CYCLE RQAH

CYCLE RQOBH
ATTN H

STATUS A H

STATUS B H

MSYN

STATUS C H

SSYN

WC INC ENB H

BBSY

BA INC ENB H

INTR

AQ0H

BURST RQ L

NPR

BR7
BR6

BR5

BR4
NPG

> ARB ITRATION

BG7

BG6

OuUTPUT
SIGNALS

BGb

8G4
SACK

INIT

ACLO

(25)

}INITIALIZATION

DO<15:00>

INIT H

ENCT 1 H

FNCT 2 H

FNCT 3 H

READY H

BUSY H

ACLO FNCT 2 H

GOH

END CYCLE H

NOTE: ALL 1/O SIGNALS ARE
ASSERTED H EXCEPT
BURST RO L
TK-5021

Figure 3-1

DR11-W I/O Lines

Table 3-1

Input Signals from User Device

Signal

Function

DI (15:00) H

User device data is transmitted to the DR11-W as DI(15:00). This data, buffered by the IDR in the

COCNTL H

C1 CNTL H

DR11-W, may be read by the CPU or written to the memory in a DMA operation.

User device encoding of these signals C1 determines which of the four possible types of bus cycle the
DR11-W performs when it becomes bus master. These signals correspond logically to UNIBUS signals

CO and C1. The type of transfer is coded as follows:

CYCLERQAH

CYCLE RQBH

ATTN H

CO CNTL H

C1 CNTL H Cycle Performed

DATI (Read word)

DATIP (Read word with write to same address to follow)

DATO (Write word)

DATOB (Write byte)

These signals (OR’ed together) are used independently to tell the DR11-W that the user device is requesting or presenting data.

ATTN (a user-defined signal) indicates that a user device error exists. When the current UN IBUS

cycle is completed, ATTN causes ERROR to set, which in turn causes READY to set. ATTN can be
read from the CSR as bit 13.

STATUS A H
STATUS B H

STATUS CH

WC INC ENB H

BA INC ENB H

These three signals indicate user device status; their application, however, is user-defined. They are
read as part of the CSR.

The word count increment enable signal allows the WCR to be incremented during each NPR transfer.
If DATIP/DATOB cycles are performed, WC INC ENB should be negated for the duration of the
DATIP cycles, or the even byte of the DATOB cycle, and every alternate cycle thereafter.
The bus address increment enable signal causes the BAR to be incremented after each NPR transfer to
conform with user requirements. Transfers may be made to the same location by holding this signal
negated. If DATIP/DATOB cycles are performed, BA INC ENB must remain negated for the duration of the DATIP transfers or for the even bytes of the DATOB transfers.

AO0 H

BURST RQ L

A00 specifies UNIBUS address bit <<00> for NPR transfers. Thus, a user device can specify even or
odd byte addresses. This signal must be negated for sequential word addressing.

If this signal is held asserted, the DR11-W operates in the NPR burst mode after it has become bus
master.

Table 3-2

Output Signals to User Device

Signal

Function

DO (15:00) H

Data is transmitted from the DR11-W’s output data register (ODR) as DO (15:00). When the DR11W does a DATI, the ODR is loaded with data read from memory. This data is then sent to the user

device.

INIT H

The initialization signal is sent by the DR11-W during power turn on/off, during the execution of a
reset instruction, when the CPU is initialized from its front panel, or when the MAINT bit in the CSR

is cleared.

FNCT 3 H

FNCT 2 H
FNCT1 H

These signals from the DR11-W to the user device are based on CSR bits 3, and 1, respectively. They
are user-defined, and specify a user device operation.

READY H

This signal corresponds to CSR bit 7 (READY).

BUSY H

BUSY H requires that switch 1 of operational mode switchpack E105 be set to ON, switch 2 set to
OFF, and switch 3 set to OFF (see Table 6-4 and Figure 6-3). When BUSY H is at a logical 0 (L), it
indicates to the user device that a DR11-W bus cycle has just been completed, and that the next user
device request can be made. When BUSY is at a logical 1 (H), it indicates that a DR11-W bus cycle 1s

in progress, and that no further requests can be made.

ACLO FNCT 2 H

This signal, generated by the DR11-W control logic, occurs only during a powerfail sequence, or when
FNCT 2 is set. ACLO FNCT 2 indicates to the user device that a powerfail is about to occur. If a
DMA transfer is in progress, an ERROR is generated. If an interrupt enable has been set, an interrupt

will occur after the completion of the current cycle; any further DMA transfers are inhibited. If a
DMA transfer is not in progress, ACLO FNCT 2 prevents any DMA transfers from being initiated.

GO
H

GO is a 200 ns positive pulse that results from writing a 1 into the GO bit (bit 00) of the CSR. The GO
pulse indicates that a new operation is to be performed.

END CYCLE is a 100 ns pulse that indicates the completion of a DR11-W UNIBUS cycle.

END CYCLE H

DO 12
H

DO11H
DO 10H

DOO9H

DOO8H

STATUSCH

INITH

STATUS AH

STATUSBH

ACLO FNCT 2 H

CYCLERQAH

WC INCENBH

READY H

DOO2H
DOO3H
DO 04 H

DOO5H
DOO6H
DOO0O7
H

> GROUND

BURST RQ L
-

> GROUND

END CYCLEH

DOO1H

—
34 <
X

GROUND

CYCLEROGBH

DO 13 H

DOOOH

DO 14
H

29?2 7292 °%29?29?29%2°%9?2°%°?2°%?°¢X9

L2
DO15H

iy,

TK-50286

Figure 3-2

Qutput Connector J1: Signal Pin Assignments

3-5

;/////////////A

DITBH

os—UU

DIOOH

DI14H

oe}— SS

DIOTH

DI13H

o+4— PP

DI 02 H

DI12H

;

DI1TH

LL ;

o+—MM

DIO3H

o4—KK

DI 04 H

;

o+4—HH

DIO5H

DIO9H

FF ;

o+—EE

DI 06 H

DIOSH

DD ;

o+4—CC

DIO7H

DI1OH

GROUND{ BB Ho5
GO H

of-AA|

s
g

FNCT1H

;

CICNTLH
FNCT2H

T ;
R

—S
—P

FNCT3H

L f

AOO H

;

—E

ATTN H

;

BUSY H

COCNTLH N-H

-y

>» GROUND

BA INC ENB J g

—C

A
D

TK-5025

Input Connector J2: Signal Pin Assignments

Figure 3-3

CHAPTER 4
THEORY OF OPERATION

4.1

GENERAL

Figure 4-1 illustrates the DR11-W signal flow. As a general purpose DMA device, the DR11-W communicates directly with the memory by moving data between the UNIBUS (or UBA) and the user
device. The DR11-W can also be used as an interprocessor link between two computer systems (see
Figure 1-2 and Chapter 7, Interprocessor Links).

A user device receives UNIBUS data via the DR11-W output data register. DR11-W control signals
are received from the UNIBUS via the DR11-W control logic. User device-generated data is routed
through the 1/0 data multiplexer, input data register, and output multiplexer. This data is then applied
to the UNIBUS via the bus drivers.

The control and status signals received by the DR11-W from the user device are applied to the I/O
eontrol multiplexer. Multiplexer outputs go to the input control register and the control logic.
The DR11-W has three operating modes:

4.2

Programmed data transfers, in which the CPU reads, or writes to, the DR11-W registers.

DRI11-W interrupt of the CPU via a conventional bus request/bus grant sequence.

DMA data transfers to or from the memory with the DR11-W functioning as bus master
after a nonprocessor request (NPR) and bus grant sequence.

PROGRAMMED DATA TRANSFERS

Programmed data transfers are basically program controlled. In this operating mode, the DR11-W
functions as a slave to the CPU. The address of the DR11-W is defined by the settings of the bus address switchpack (E120) (Figure 4-2).

In the DR11-W address selection logic, REG SEL H is applied as an enabling input to a decoder that
converts CPU coding of BA(02:01) H into one of four possible register select signals: LOAD BA L,
LOAD WC L, SEL 4 L, or SEL 6 L. After the register is selected, CPU coding of BUS CO L and C1 L
determines whether a DATI/P or DATO/B transfer is to be performed. Only the CSR can be bytewritten.

4-1

BR, NPR, BG OUT, NPG OUT, SACK, BBSY, INTR

BR MASTER

AND
INTERRUPT

NPR MASTER

INIT, READY, CYCLE CMPT

LOGIC

READY, XFER END, BURST DLT

FNCT 1,2,3; ACLO FNCT 2 {zj
MCYCLE RQ, MBURST RQ, MATTN

VECTOR
-

CONTROL

READY, MULTICY RQ, ATTN. NEX,

LOGIC

CYCLE, ERROR, DATA TO BUS

INPUT CONTROL

REG SEL

WDI<15(1):00(1)>

INPUT DATA
(IDR)

D<08:02>

1/0 DATA
/o~

D4 <—[

WSTATUS A, B, C

D SIB00> | e

<16:00>

MUX

UNIBUS

D10

D6 D7

D <08:02> | VECTOR

DO <15:00>

ENCT 1,2,3; [E

fil:j

XBA <17(1):16(1)>

MUX

MAINT

]

WC <15(1):00(1)>

D <15:09> & <01:00>
D9

5o e BAIE(1):01(1)>

WA00, WCO
ADRS TO BUS,
MSYN
XBA
<17(1):16(1)>

BUS A <17:00>
A <17:00>

BUS

BA <15(1):01(1)>

ADDRESS

01
BUS ADDRESS

AND

(BAR)

CONTROL

LOAD B

BUS ACLO, SSYN, Msyn| TRANSCEIVERS Ba 47,01
BUS CO, C1, INIT
_,

SSYN
o1

08|07

WORD COUNT

CONTROL AND

STATUS REGISTER

(WCR)

‘

{CSR)

oA nC
ADRS

CD, C1, MSYN, SSYN

p3, D7, D10

OUTPUT DATA

D10

‘

SgL .

SELECT

[

OUT HB
ouUTLB

<16:00>

RECEIVERS

BUS D <15:00>

TK-5039

Figure 4-1

DR11-W Block Diagram (Sheet 1 of 2)

5 ARG RARC R
3

FNCT 1,2,3 ACLO FNCT 2

L MCYCLE RQ, MBURST RQ, MATTN

5 |l DI<15:00>

INIT, READY, CYCLE CMPT

OUT |
CONTROL

DRIVERS

1/0 CONTROL

—

RECEIVERS

‘
RECEIVERS

MUX

CONTROLIN
D5

4 ©
|

DI <15:00>
D4

<15:00
JROS19:00>

DRIVERS

RECEIVERS
-

2
u

w8
—

D0<15:00>

o10|

D10

|
|

|
!

(J1)|
-,

L -l

TK-5040

Figure 4-1 DR1I-W- Block Diagram (Sheet 2 of 2)

W MSYN H

REG

—

\SEL H|
[/

125 NS

DELAY

|ssynH

LINE

DRIVER
>

BUSSSYNL

[9
@

BA 17:15 H

(BUS 17:15 L)

BA <14:13>H

COMPAR—

ATOR

(BUS <14:13> L)

I ASSERTED WHEN

ADDRESS (12:03) =

SWITCHPACK
SETTING

+3V ——

LOAD BA L

»| SEL

———— —— » TO BUS ADDRESS REGISTER

PRCOPER [ LoapweL » TO WORD COUNT REGISTER

BUS
ADDRESS

SEL6L

SWITCH
PACK

SELAL

BA<02:01>H
BA <12:03> H

+»

TO OUTPUT DATA REGISTER

1o CSR/EIR (VIA
CONTROL LOGIC)

{BUS <02:01> L)

(BUS A<12:03> L)
i

HIGH/LOW

BYTE
.

BUS C1,C0 L~ CONT_ROL

LOGIC

SELECTION

SIGNAL

(OUT HB/LB H)
Lt

BUS ADO L

-—

17116

la.
[

{16

{14

(13

|12

{11

[10 | 09|08

|07

|06

[05

|04

DR11-W MODULE ADDRESS

|03

|02

01]/00

REG.

SEL.

|BYTE

SELECTION
TK-6023

Figure 4-2 Address Decoding Logic

INTERRUPT OPERATION
4-4 is the logic flow. The DRI 1-W interrupt level
Figure 4-3 shows the DR11-W interrupt logic; Figure
-select plugs are available (priority levis user-selected by means of a priority-select plug. Fourthepriority
DR11-W. The selected plug is inserted into
els BR4, BR5, BR6 and BR7); BRS is supplied withof interru
pt operation assumes that the plug (Part
socket E59 on the module. The following description

4.3

No. 54-8778) for priority level 5 (BRS5) has been installed.

(ACLO, PAR ERR, MULTICY RQ, ATTN,
The outputs of the six flip-flops used for indicating errors
ANDed with the output of the interrupt enable (IE)
LINK ATTN, and NEX) are ORed together, then
flop to initiate an interrupt request. Note that, at the end of a transfer, the word count register (WCR)
overflows and generates WCOF, which also causes an interrupt.

causes an interrupt request to be generated. All
When an error is detected, the interrupt flip-flopprovid
ed by a single DCO13 chip. When the request
DR11-W logic for processing interrupt requests is priorit
y interrupt plug. If the CPU is operating at
is generated, the DCO13 asserts BUS BRS L via the
completion of the current instruction. Then, if no
priority level 4 or less, the signal BGS H is asserted onsignal
BUS GRANT propagates to the DR11-W.
higher-priority BR5 device is requesting service, the BUS SACK
L to acknowledge its selection as the
Upon receipt of BUS GRANT, the DR1 1-W asserts
next bus master.

44 DMA OPERATION
the transfer of data between a user
The DR11-W becomes bus master (by generating an NPR) toofeffect
device and the UNIBUS. The user device controls the type data transfer (DATI, DATIP, DATO or

DATOB) by suitably coding control signals CO0 and C1.

e (non-

There are three DMA operating modes: block mode, 2-cycle (standard) burst mode, and N-cycl
standard) burst mode.

NOTE

N-cycle burst mode is not compatible with the VAX
architecture, and therefore should not be used in any
DR11-W/VAX configuration.

in burst mode,
then release the bus for each word transferred;
In block mode, the DR11-W must obtain, control
transfers;
data
of
, then holds it for a complete string

the DR11-W merely obtains bus master

i.e., for two cycles or an unlimited number of cycles (N cycles).

interleave their data transfers with those of the
The block mode enables other devices on the bus tofined
until the specified number of words has
DR11-W. Transfers normally continue at a user-decurrentrate
revision status of the DR11-W are included
been transferred. (Timing diagrams reflecting the
in the DR11-W print set.)

GO H,
logic sends control signals (END CYCLE H, J1.
During DMA transfers, the DR11-W control via
The
tor
connec
output
W
lines leaving DR11BUSY H, and READY H) to the user deviceThis the
the
via
lexer
multip
data
W
data reaches the DR11user device responds with data DI(15:00) H.
signals
several
tes
genera
also
input control lines to connector J2 and the 1/O receivers. The user deviceare:
that are applied to the DR11-W 1/0O control multiplexer. These signals
C0 CNTL H
C1 CNTL H

CYCLE RQ A (or B)
WC INC ENB H

BA INC ENB H, and
BURST RQ L.

4-5

DCO13 (NPR)

D7 NPR RQ (1) L———LfREQUEST

kB3

olsTeaL GRANT

D7 BURST DLT (1) H

DI WINIT H

H—IC

FDi gys gasyY L

MASTER [0 D8 NPR MASTER L

INIT

BUS BBSY D2

_{MASTER cLR

bg- D CveLe L-Sgf

sAck

DI WSSYN L ——20lBUS SSYN

P g s NPR L
Bl Bus NPG OUT H

BUS SACK JoZ—

D7SAC RL L—30ciRsACKENE

?880

BUS GRANT OUT}—

_JBUSGRANTIN

390

)

REQUEST BUS |2

2OlBUSNPR

180

BUS NPG IN H -CAT

E106

D7 SAC RL L—da ias‘/

BUS BG4 OUT H-212
BUS BG4
IN H 252

Y-y

D7 WGO H

D7 ERROR H

D7 READY (1) H

D7 LNK ATTN {1} H

4
2
3

N R
LA
5 | SOCKET [12

BUS BGS OUT H-2R2

Job

17_DD2 pyspr7L
15_DE2 g58R6L
14
DF2 grgrs .

BUS BG
5 IN H-2E2

BUS BG5S OUT H 2N2

_DBK2 pusBG 7 INH

DL2 5581

7 0UTH

DM2 & s BH 6 IN H

D10 INT ENB (1) L
.y

D10 INT ENB {1) H—2]

I'_

D8 INTRUPT

1474 D-="— D7 NPR RQ (0)

79 | 4

D7 READY (1) H—11

O5— D8 INTRUPT

0 H

(1)

H—4]

E98

—“ »

DCO13 (BR)
k6

7400

Rog

+5 V—AAA

R87 |
390
DI WINIT H=2
D8 BR MASTER H

7402

ESS

E107

T’) REQUEST

REQUEST BUS

L—
2 olBUSNPR BUS GRANT OUT

—2
Ol STEAL GRANT

I
9

”

3_JBUSGRANTIN

BUS SACK]o-Lsuseasy o2

24BUsssYN
”
MASTER CLR

Q1K

AA—+5 V

127

)
K

SACK }—2-Dg BR SACK H

_—"20lcLRsackens

R84
180

20t

4 1

MASTER

INIT

__]13
DI WINIT H

MASTER L

D8 BR MASTER H

Figure 4-3

Interrupt Logic (Sheet 1 of 2)

TK-5038

|
|

FT2

BUS SACK L

o
l4

Fmi BUS INTR L

L‘®—6

|12
I

|
|

{ Do

10 D8 WPB H
15

;
ZD_
L

8641

CS| BUSPB L

CcC

L BUS PA L

E95

TK-56396

Figure 4-3

Interrupt Logic (Sheet 2 of 2)

SET BY
PROGRAM

YES

PREVIOUSLY

SET

MULTICY RQ—
ATTN

ERROR

ACLO

OCCURS

YES

NEX

PAR ERR —
A

IE
PREVIOUSLY

READY

SET

CLEARED

!
READY
CLEARED
BY
GO

!
DMA

TRANSFERS

OCCUR

ERROR
OCCURS
DURING A
JRANSFER

WAIT FOR

CURRENT
TRANSFER

INT REQ
GENERATED

COMPLETION

WCOF

OCCURS

!
READY

SET BY
WCOF L

'
i

DMA

OPERATION
ENDS

INTERRUPT
GENERATED

TK-5024

Figure 4-4

Interrupt Flow Diagram

4-8

The user device generated data is transmitted to the UNIBUS through

the input data register (IDR).

DMA operation begins when the DR11-W sends GO L and
READY L to the user device. These signals
are generated in the control logic, within which the READY
flip-flop is cleared by a GO pulse if no
ERROR condition exists. The BUSY flip-flop in the control
logic is cleared by CPU initialization

(BUS INIT L) or by completion of the previous NPR operation,.

To initiate a DMA operation, the user device checks BUSY L to determin
e whether or not the DR11-W
is in a busy cycle. If BUSY L is not asserted (i.e., the DR11-W
is not busy), the user device can initiate
a transfer.
.
Fifty ns after the delay line is triggered via MCYCLE RQ H,
the burst DLT multivibrator in the control logic is turned on, and the NPR RQ flip-flop is set. Setting this
flip-flop clocks BURST RQ L if the
user device has requested a burst transfer. Receipt of NPR RQ
by the bus master logic asserts BUS
NPR on the UNIBUS while simultaneously inhibiting the interrup
t logic from generating BUS INTR
L. NPR RQ also prevents the control logic from generating
an ERROR L output that could also cause
an interrupt.

150 ns after the control logic delay line is triggered by the CYCLE
RQ (A or B) input, WCLK H is sent
to the word count register (WCR). WC CLK H increments
the WCR. If the final transfer is in progress, the WCR generates WCOF L, which sets the control
logic READY flip-flop.
200 ns after the control logic delay line is triggered, the CY
INH flip-flop is set. Flip-flop output then
inhibits further triggering of the delay line and resets the CYCLE
flip-flop.
At 400 ns after the control logic delay line is triggered, CO
RST clears BUSY. The DR!1-W BUSY
output then goes high, enabling the user device to execute
another transfer request. The user device can

then send a second CYCLE RQ (A or B), together with appropri
ate data and control signals, even
though the preceding transfer is still in progress.
If a second CYCLE RQ is made while BUSY is asserted, the
MULTICYCLE flip-flop in the control
logic is set, and in turn, sets ERROR. Upon completion of the
first data transfer, the control logic CY
INH flip-flop is cleared. The delay line is then no longer inhibited
, and a second data word can be
transferred.

CHAPTER 5

INTERFACING AND PROGRAMMING CONSIDERATIONS

5.1

USER-DEVICE CABLES

Two identical cable/connector assemblies are required for interfacing the DR11-W with a user device.
The recommended BCO6R cable assembly is terminated at both ends with H855 40-pin female connectors that mate with the J1 (output) and J2 (input) connectors of the DR11-W. The use of cables
longer than 1524 cm (50 ft) BCO6R is not recommended. If a longer cable is used, satisfactory DR11W performance cannot be quaranteed. Note that the recommended BCO6R cable assemblies are optional equipment items.

5.2

USER-DEVICE SIGNAL INTERFACE

The DR11-W uses 8881 I/0 signal drivers and 8640 receivers, both of which terminate into a 120-ohm
impedance. It is recommended that the 8881 and 8640 also be used in the user device. They may be
purchased from DIGITAL by specifying DIGITAL part numbers 957 and 956, respectively.
NOTE

User 1/0 receivers and drivers should be grounded,
capacitor by-passed, and physically positioned within 10.2 cm (4 in) of the inboard end of the module

“fingers.”

5.3

1/0 SIGNAL TIMING

User device operation with the DR11-W may be initiated any time after the READY and BUSY signals to the user device are cleared; clearing indicates that the DR11-W is ready for DMA operation.
READY is cleared by the GO pulse; BUSY is cleared during initialization or on completion of a previous cycle.

After READY and BUSY are cleared, the user device may initiate data and control signals for the
DR11-W. When the user device has data ready for transfer, the following group of signals must be
asserted simultaneously, and as discrete pulses or signal levels:
DI (15:00) H

CYCLE RQ (A OR B)/BURSTRQ L*
C0O CNTH H; C1 CNTL H¥
A00 H
WC INC ENB H

BA INC ENB H

*Either or both of these signals are asserted, depending upon transfer conditions.

+These signals are always used together as a 2-bit code (see the functional description of DR11-W input signals in Table 3-1).

5-1

CYCLE RQ A (or B) must be held for 120 ns after assertion; the data and
other control signals in
listed group must be held for 250 ns after assertion. BURST RQ L, however,
must be
i
entire string of transfers is completed. Note that the burst request signal
is the only DR11-W
asserted low at any time.

NOTE
The DR11-W automatically compensates for skew

times introduced

by drivers,

connect cables.

receivers, or inter-

The user device data and control signals to the DR11-W are buffered

by the IDR and the ICR, respectively. During a DATO/B cycle, new user data and control signals
may be sent to the DR11-W upon
receipt of the trailing edge of the low-to-high BUSY signal if READY
is still cleared. Similarly, the
leading edge of the BUSY pulse may be used to strobe the contents
of the ODR into the ODR drivers
during the DATI/P cycle.

If another CYCLE RQ A (or B) H is received while a bus cycle is in progress,

signal is generated in the DR11-W. If an IE has already been generate

MULTICY RQ H causes an interrupt request to be generated at the

a MULTICY RQ fault

d in the DR11-W control logic,

completion of the current cycle.

When data is transferred in burst mode, each cycle cannot exceed
the limit established by the data late
timeout setting (adjustable from 4 to 40 usec, maximum, and 10
to 15 usec nominal). If this timeout
limit is exceeded, the bus is automatically released, and must be
regained by means of the established
bus request/bus grant sequence before another data transfer can be
effected.
5.4 SIGNAL INTEGRITY
The DR11-W is designed to perform as a DMA interface for user
devices located in the same enclosure
as the DR11 itself. For this type of application, an enclosure is defined
as a mounting framework consisting of one or more cabinets bolted together to form a complete
assembly. The electrical bonding
within the enclosure is expected to be adequate for assuring a uniform
electrical reference for both the
DR11-W and the user device.

NOTE
The interface circuits used in the DR11-W are
single-ended (not differential), and therefore must

operate in an environment that provides the same

reference at both ends of the interconnecting cable.

Furthermore, it is unwise to dress cables outside of
the enclosure unless they are designed for this pur-

pose. Failure to observe these recommendations can
result in increased system sensitivity to environmen-

tal noise and consequent reduction in system relia-

bility.

The interface circuits of the DR11-W are designed for optimized
signal-to-noise margin. They feature
current drive, threshold control, and input/output impedan
ce characteristics that enhance the reliability of the DR11-W /user interface. The same circuits must be
designed into the user device if the full

value of the designed-in noise immunity is to be realized in the
system operation. The recommended
circuits are illustrated in Figure 5-1.

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TK-5612:

Figure 5-1

Interface Circuits for Optimizing DR11-W

Signal-to-Noise Margin

5.5

PROGRAMMING CONSIDERATIONS
Individual consideration of programming requirements may be necessary in connection with:
e

e
e

DRI11-W operating mode
C(Cable length, and
Timing relationships.

5.5.1
DR11-W Mode
In general, read/modify/write (R/M /W) instructions should not be used when addressing the CSR in
DR11-W mode operation. This restriction is necessary because, when writing, bits 15 and 0 have different meanings than when reading. This difference is due to the presence of the EIR in the DR11-W

)

mode, a consideration that does not apply when operation is in the DR11-B mode.

8872

.....

Timino
Timing

The user device must have sufficient time to receive and decode the function bits prior to executing
commands. To meet this requirement, either the software or the user hardware must delay GO long
enough to allow cable deskew and function decode. The software may deskew, by first setting the function bits (Figure 5-2), then asserting both the function and GO bits. This provision allows at least one
instruction time for the function bits to be propagated and decoded.
In a link situation, if FNCT 2 was asserted (thereby interrupting the responding processor), the FNCT
2 bit should be cleared after the GO bit has been set, as shown in Figure 5-2.
5.5.3 Programming Example
The following programming examples for the PDP-11 and VAX applications for the DR11-W illustrate
the two concepts outlined in Paragraph 5.5.2. Note that an R/M/W has been used in the interrupt
service code. BIS (an
R/M /W instruction) is a usable (and, in fact, desirable) instruction in this case
because bit 15 is going to be set regardless of its present state. (Bit 15 is the bit that might accidentally
be modified by an R/M/W.) The example also uses the byte form of instruction (BISB) to avoid any
interaction with the GO bit contained in the low byte.

Example 5-1 gives a typical VMS coding sequence for loading the CSR in a DR11-W/VAX system
configuration. Example 5-2 gives the coding sequence for reading the CSR after interrupt in this configuration. Examples 5-3 and 5-4 give a similar pair of examples for a VAX/PDP-11 system configuration.

[

SET BY PROGRAM

IN LINK OPERATION,

—~ THE PROGRAM MUST
CLEAR FNCT 2, IF
SET

FUNCTION BITS

GO BIT

CLEARED BY DR11-W
SET BY PROGRAM

®
Figure 5-2

©,
Setting and Clearing FNCT2 and GO Bits

5-4

TK-5882

we
W

INPUTS:

TRANSFER.COUNT

BUS.ADDRESS

Address

CSR.CONTENTS

location

number_of words to
of

location

containing

negative

transfer.

containing

low

Address

load

location

containing

value

into DR11-W CSR.

;

bits

Unibus address of data buffer.

Includes:

Functions

Extended

Interrupt

bit

Contains

FUNCTIONAL

routine
registers
to

its

contents

bit

since

1loads
start

are
the

stabilize.

including
Finally,
step

MOVW

BICW3

MOVW

BICW3

the
the

set

LINK

MOVW

DR11-W

enable

3:1)
bits

bit

(bit

set.

DESCRIPTION:

This

isn't

address

(bits
address

CSR

optional,

specified
values
in
transfer.
In the case

written first to
"“FUNCTION
BITS"
the

"GO"

twice)

MODE.

the
a

CSR

bit

written

and

less

written

the

with

start
"GO"

w“TRANSFER;COUNT,(R4)

W”BUSLADDRESS,Z(R4)

#1, W“CSRLCONTENTS,4(R4)
W‘CSRLCONTENTS,4(R4)
#S,W“CSR;CONTENTS,4(R4)

bit

(so

this

whether

last

the

DR11-W

the

transfer

Load

low

bits

bit

:
used

count

bus

address

Load

CSR

Load

CSR,

Load

CSR

less

"GO"

assert

less

bit

"GO"

and

This

final

LINK

operation

step

Typical VMS Coding Sequence for Loadin
g the CSR
in a DR11-W/VAX System Configuratio
n

5-5

wvalues,

transfer.

This

"FNCT"

Example 5-1

all

the

"FUNCTION BIT"

depending

DR11-W
the CSR,

CSR less the
"GO"
must
be
allowed
to

actually
less

the
of

the

bits

TMo

(bit

bus
5:4)

(bits

WMo e Ne WNE Ne We Wy %o we W, WE We N N % wNe Ny wy s NP WMe my Wy we

for

only.

INPUTS:

R4 - Address of DR11-W register set
OUTPUTS:

ss Register
DR.BAR - Final contents of DR11-W Bus Addre
Register
Count
Word
-W
DR11l
of
nts
conte
DR.WCR - Final
ter
Regis
Data
Input
W
DR.IDR - Final contents of DR11s
Statu
and
ol
Contr
-W
DR11l
of
nts
conte
DR.CSR - Final

Mo We

Wmp we We We Wo we

W2 -e

Coding sequence for reading DR11-W CSR after interrupt

DR.EIR - Final contents of DR11l-W Error Information

;

MOVW

4 (R4) ,W"DR.CSR

;

Read Control and Status

BISB

$128,5(R4)

;

Set EIR flag

MOVW
BICW3

MOVW
MOVW
MOVW

4 (R4) ,W'DR.EIR

;

Read Error Information

;

4 (R4)

;

Write CSR, clearing all

(R4) ,W'DR.WCR
2 (R4) ,W DR.BAR
6 (R4) ,W"DR.IDR

;
;
;

#"C<l4>,W“DRLCSR,

;

status except FNCT bits

Save Word Count Register
Save Bus Address Register
Save Input Data Register

Example 5-2 Typical VMS Coding Sequence for Reading the DR11-W
CSR After Interrupt in the DR11-W/VAX System Configuration

TRANSFER.COUNT

Address

of
CSR.CONTENTS

location

Unibus

Address

load

into

W N
N ME Me N
Ve

ME NE

containing

address
location

data

negative

low

bits

buffer.

containing

value

DR11-W CSR.

Contains

address

routine

NE Mo

its

to
contents

ME N

bit

since

stabilize.

1loads

the

start

Function

Extended bus
(bits 5:4)

Interrupt

isn't

DR11-W

MOV

(bit

bits

(bits

3:1)

address

enable

set
is

are
the

"FUNCTION

twice)

optional,

specified

the

and

CSR

bit
to
written
less

TRANSFER.COUNT, (R4)
BUS.ADDRESS, 2 (R4)

bits

bit

(bit

set.

to
BITS"

values

the

case

with

all

DR11-W

the

CSR,
the CSR less the
"GO"
must
be
allowed
to

written

values,

actually
start
the
transfer.
less the "GO" bit (so this bit

"FUNCTION

depending

LINK MODE.

MOV

bit

transfer.
written first

including
the
"GO"
Finally, the CSR is

DESCRIPTION:

registers

step

l)
2)

BIT"

whether

the

This

last

DR1l1-W

used

;

Load

the

transfer

count

Load

1low

bits

bus

RO,
4 (R4)

BIC

#5,R0

MOV

RO,
4 (R4)

Example 5-3

MOV

#1,R1
R1,
4 (R4)

Load

BIC
MOV

Fetch CSR value
Copy CSR value
Clear "GO" bit

Load

CSR.CONTENTS,
R0

Clear

RO,R1

CSR
CSR,

value

Load

"FNCT"

This
LINK

less

"GO"

assert

"GO"

and

"FNCT"

bit

"GO"

and

for

"GO"

MOV

WME

MOV

address

WME

M ME

This

Ve W

location

Includes:

FUNCTIONAL

BUS.ADDRESS

Address

number of words to transfer.

WMy

N Ne N W

INPUTS:

CSR

1less

bit

final

step

operation

only.

Typical Coding Sequence for Loading the DR11-W CSR
in a DR11-W/PDP-11 System Configuration

- Address

DR1l1l-W

set

OUTPUTS:

WMs

WMy

INPUTS:

DR.BAR - Final

contents of DR11-W Bus Address Register

DR.WCR - Final contents of DR11l-W Word Count Register

DR.IDR - Final contents of DR11l-W Input Data Register
Status
and
DR.CSR - Final contents of DR1l-W Control
Register

DR.EIR

Final

contents

DR11-W
\

Error

Information

Status

$#°C<16>,R0
R@,4 (R4)

MOV

2 (R4) ,DR.BAR

MOV

(R4) ,DR.WCR

6 (R4) ,DR.IDR

W
WO
WMo
WMo

BIC
MOV

Set

#200,5(R4)
4 (R4) ,DR.EIR

BISB
MOV

Read
Save

Wme

4 (R4) ,RO
R@,DR.CSR

MOV
MOV

Read

Control

and

CSR contents
EIR flag

Error

Information Register

Clear all status except "FNCT" bits
Write CSR, clearing status bits
Save Word Count Register

Save Bus Address Register

Save

Input Data Register

Example 5-4 Typical Coding Sequence for Reading the CSR After
Interrupt in the DR11-W/PDP-11 System Configuration

5-8

CHAPTER 6
INSTALLATION

6.1

UNPACKING AND INSPECTION

6.1.1
Unpacking
To unpack the DR11-W, perform the following procedure:

Check that the shipping container is sealed.

Check the shipment against the packing list to ensure that the correct number of containers
has been received. If the shipment is incorrect, notify DIGITAL.
NOTE
The customer should first check with the carrier to
try to locate the missing item(s).

Check all contajners for external damage. If any damage is found, notify DIGITAL.

Open containers one at a time. If there is more than one, start with the container
labeled
“Open Me First.” Inventory the contents of each package by comparing it with
its packing
slip.

NOTE
Packing materials such as foam fillers and plastic
inserts should be retained if reshipment is a possi-

bility.
6.1.2

Inspection
Inspect each component for damage, e.g., scratches or breaks. Report any damage
to DIGITAL.

6.2
INSTALLATION PROCEDURE
To install the DR11-W, carry out the following procedure:
1.

Ascertain that the system +5 V power supply can handle the additional

ed by the DR11-W.

load (3.7 A) present-

See that the system power is OFF.

Remove the grant continuity card (G727A) from the backplane SPC slot
in which the
M8716 DR11-W module is to be installed.
]

Remove the NPG jumper from the slot to be occupied by the DR11-W module.
This jumper
is a backplane wire connecting pins CA1 and CBI.

6-1

If the DR11-W is to be operated at a BR level other than BRS, the standard BRS piug (PN
54-8778) illustrated in Figure 6-1 should be replaced with the appropriate plug (see Table 61).

Set the bus address by means of switchpack E120 (Figure 6-2) and in accordance with the
switch settings given in Table 6-2. The switchpacks used in the DR11-W are of two types:
rocker and slide. The individual switches comprising a switchpack are set to logical 0 by setting them to their ON position as indicated by the OFF-ON lettering at one end of the switch
package. For both types of switchpacks, ON represents logical 0; OFF is logical 1. The
switchpack with slide-type switches poses no problem in address setting. Each switch lever is

merely pushed in the ON or OFF direction (Figure 6-2) to set it for logical 0 or 1, as desired.

To set any switch of the rocker type to ON (logical 0), depress the switch at its ON end (do
not be concerned with the red bars at each end of the switch lever). Similarly, to set the
switch to logical 1, depress the end of the switch at its OFF end.

Set the vector address by means of switchpack E15 (Figure 6-2) and in accordance with the
switch settings given in Table 6-3. Vector addresses must be assigned from available floating
vector space (rank = 42).

For link-mode operation, set the switches of operational mode switchpack E105 (Figure 6-3)
in accordance with the switch settings in Table 6-4.

For diagnostic runs, set burst mode selection switch B1 (Figure 6-4) for 2-cycle or N-cycle
operation in burst mode, as desired. The switch position for each mode is etched adjacent to
the switch on the module.

NOTE

When the DR11-W is used as the functional equivalent of the DR11-B, switch 5 of operational mode
switchpack E105 (Figures 1-1 and 6-3) should be set
to OFF, so that BIT SET and BIT CLR instructions
can be sent to the DR11-W CSR.
NOTE

When looking at the component side of the M8716
module, the 2-CYC position of switch B1 is toward
the operational mode switchpack E105 (Figure 6-4).
10.

Install the DR11-W in the backplane.

6-2

oOT

Figure 6-1

Bus-Request, Priority-Level Plug/Socket Assembly

6-3

BUS ADDRESS SWITCHPACK E120

VECTOR ADDRESS
SWITCHPACK E15

NOTE: SWITCH 1 1S
NOT USED

NOTE: ON=0 OFF=1 (BOTH SWITCHES)
TK-5035

Figure 6-2

Bus Address and Vector Address Switchpacks

Table 6-1

Priority Level

Available Bus-Request Priority-Level Plugs

BR Plug Part Number

BR7

54-8782

BR6

54-8780

BRS5

54-8778

BR4

54-8776

Table 6-2

Typical Switch Settings for Bus-Address
Switchpack E120

Bus Address Bits

OFF

BA(12:03)
Switch Number

Typical Switch Settings for:
DR11-W Module #1

(77241X)
DR11-W Module #2

(77243X)

DR11-W Module #3

(77245X)
DR11-W MODULE #4
(77247X)

Notes:
1.

A switch is set to OFF for logical 1, and to ON for logical 0.

X is used for the register number (0 = WCR; 2 = BAR; 4 = CSR/EIR; 6 = IDR/ODR).

The user may employ additional DR11-Ws if he wants; these are set to addresses in user floating address space.

For floating addresses, the CSR address is rank 19.

6-5

Swiich Seitings for Yecior Address Switchpack Ei5

Table 6-3

Vector Address Bit

Switch Number

Switch Setting*

1248

OFF

3008

OFF

NOTE

Vector address floating = rank 42

*Settings in this example are for octal address 124
Legend:

X = Don’t care
ON = Logical 0
OFF = Logical 1

Switch Settings for Operational Mode Switchpack E105

Table 6-4

CYC INH

READ INH A00

MODE SEL

OFF

USER SEL

| USER SELTT

OFF

USER SEL

OFF

Switch Number

Name

BUSY

User Device

Maintenance

Cable Mode

DR11-W to

DR11-W Link

Mode

DR11-W to
DRV11-B Link

Mode

*Switch 4 is set to ON for link mode operation to prevent odd addressing when the device uses address line A0Q; when set to OFF, switch 4
ungrounds the AOO line upon assertion of READY.

+Switch 5 is set to ON to select the DR11-W mode; OFF selects the DR11-B mode. The DR11-B mode provides software compatibility with
the DR11-B general purpose interface. The DR11-B mode disables the EIR and allows execution of read-modify-write instructions.

+1For VAX systems, only the DR11-W mode (switch set to ON) is supported. For PDP-11 systems, both DR11-W mode (switch set to ON)
and DR11-B mode (switch set to OFF) are supported.

6-6

S3 (CY INH)

S4 (READY INH AQ0)

S2 (BUSY)

S5 (DR11-B/DR11-W MODE)
S1 (BUSY)

TK-5022

Operational Mode Switchpack E105

Figure 6-3

BURST MODE SWITCH B1

OPERATIONAL MODE

SWITCHPACK E105

TK-5034

Figure 6-4

6.3

ACCEPTANCE TESTING

Burst Mode Switch Bl

Acceptance testing of the DR11-W is performed by running the appropriate diagnostic program for the
DR11-W system configuration under test. Refer to Chapter 8 of this manual for the DR11-W diagnostic programs provided. To run the program, perform the following procedure:
1.

Connect the wraparound test cable BCOSL between output connector J1 and input connector

J2 on the DR11-W (Figure 1-1).

Connect an oscilloscope probe to test point TP1 on the DR11-W.

Turn on system power.

Start diagnostic run.

6-8

Upon instruction from diagnostic, calibrate BURST DLT TO (burst data late timout) for 12
usec (typical)* by adjusting potentiometer R80 (Figure 1-1), and the oscilloscope connected
in step 2.

Run remaining portion of diagnostic applicable to the system configuration under test.

NOTE
For PDP-11 installations, a single program is run

straight through. For VAX-11/UBA installations,
the maintenance wrap/cable wrap diagnostic is run
for fault detection only; a second (stand-alone) diagnostic is run to support detailed testing of the DR11W at the hardware level. Refer to Chapter 8 for further details.

Remove the BCO5L maintenance/wraparound cable connecting J1 and J2.

Connect the two BCO6R cables (Figure 1-1) to J1 and J2, respectively, and to the user device.

If the DR11-W has passed the above tests, proceed with system operation.

CAUTION
Prior to starting diagnostic testing, ensure that the
user device has been powered down, and that the two

BCOG6R cables for DR11-W user device interconnect
have been unplugged.

*Or for whatever time is appropriate to the user device.

6-9

CHAPTER 7
INTERPROCESSOR LINKS

7.1

GENERAL

The DR11-W can be configured for operation as a DMA parallel-data transfer link between two computer systems (Figures 1-3 and 7-1). The link operates in a half-duplex communications mode; i.e., it
has the capability of transmitting data bidirectionally between the two computer systems, but in only
one direction at a time. Link applications require that the DR11-W be set in the DR11-W mode (Table
6-4).
7.2 OPERATING MODES
From a hardware standpoint, the link can operate in either of three modes:

1.
2.
3.

Word mode
Block mode
Burst mode

BCO6R CABLE

1524 CM (50 FT), MAX.

In word mode, information can be passed between two computers in a word-by-word sequence controlled by an interrupt-driven program. In the block and burst modes (which to the software are essentially identical), the link transmits a contiguous block of memory data from one computer to the other.
DMA transfer is used in both machines. The principal difference between the two modes of operation is
that in the block mode, the DR11-W must obtain and release the bus for each data transfer made. In
the burst mode, the DR11-W holds onto the bus, once the bus grant is received, until the requested 2cycle or N-cycle transfer is completed.

[4p]

s
o

DR11-W

P
=

DR11-W

DRV11-B

T
i

%
2

prea
2

N
TK-5032

Figure 7-1

Interprocessor Link Block Diagram

7-1

Each of the computers in the link configuration maintains independent control of its own interface. The
programs for the two computers must be written so as to ensure compatibility in terms of information

flow direction, setting bus address registers, and control of word count at the respective computer interfaces with the DR11-W.
In the environment provided by the VAX-system software (and recommended for the PDP-11s) the
communication between the linked computers is established by means of CSR bits {03:01) and (11:09),

respectively (see Figure 2-1 and Table 2-1 for this register). When CSR bits (03:01) are loaded into the

CSR of one DR11-W, the information appears in the other DR11-W of the link configuration. Table 71 shows the functional correlation of these bit relationships for the DR11-W and DRV11-B interprocessor links.
‘

Table 7-1

Correlation of CSR Function and Status Bits in Interprocessor Link Operation

CSR Bits

Transfer-Initiating

Transfer-Responding

Computer

DR11-W/DRV11-B
Function

Meaning of CSR Bit Status
at Transfer-Initiating Computer

Bit 3

Bit 11

Block/Burst NPR Transfer

Set

Bit 2

Bit 10

INTR (Interrupt) Request

—

Block NPR transfer

Clear —

Burst NPR transfer

Set

Interrupt of responding

computer

Bit 1

Bit 9

DATI/DATO
.

7.2.1

Set

DATO

Clear —

DATI

Word Mode

Setting CSR bit 2 (FUNC 2) in the transmitting DR11-W sets both CSR bit 10 (STATUS B) and CSR

bit 13 (ATTN) in the receiving DR11-W. ATTN generates ERROR, which in turn generates an interrupt if IE is set.
In all three transfer modes, when powerfailure occurs in one computer, an ACLO is transmitted to the
other computer, where it sets ATTN and (as described above) causes an interrupt.

During word-mode transfers, the ODR functions as a write-only register for data transmitted to the
other computer. The data must be maintained in the ODR until read by the other computer. In general,

this operation requires that the receiving computer send back a “hand shaking” signal to indicate that it
has read the data and that the transmitting computer can not modify the data in its ODR.
The interrupt capabiljty incorporated in the CSR can be used in conjunction with the ODR to pass

information between computers in a word-transfer interrupt sequence (Figure 7-2).
7.2.2 Block Mode
NPR transfers by the link may be requested by either computer, and may flow in either direction. The
NPR cycles always occur in pairs: the first cycle is a DATI (read from memory) by the transmitter; the
second cycle is a DATO (write into memory) by the receiver. These alternating pairs of cycles repeat
until the entire block has been transmitted.

The computer designated as link transmitter sets GO and CYCLE to generate the first NPR cycle.
Subsequent NPR cycles are generated by hardware hand-shaking between the DR11-Ws.
The programming sequence used to initiate a block transfer is given in Figure 7-3.
7-2

TRANSFER - INITIATING COMPUTER

TRANSFER - RESPONDING COMPUTER

1. LOAD ODR WITH FIRST WORD.

2. SET CSR BITS 1 AND 2*,
* 1. ENTER INTR SERVICE ROUTINE.
2. READ CSR.

3. READ IDR.
4. SET CSR BIT 2.

1. ENTER INTR SERVICE ROUTINE.

2. LOAD ODR WITH SECOND WORD.
3. CLEAR, THELN SET CSR BIT 2.

—» REPEAT.

REPEAT.
*BIT 1

INDICATES WORD MODE.

BIT 2 CALLS FOR FAR - END INTR.

Figure 7-2

Interrupt Sequence for Word Mode
Interprocessor Link

TRANSFER - INITIATING COMPUTER

TRANSFER - RESPONDING COMPUTER

TRANSMITS MESSAGE DESCRIBING DATA

TO BE EXCHANGED (LENGTH, DIRECTION, ETC.)

ACKNOWLEDGES DATA TO BE

EXCHANGED.

DATA TRANSMITTER

DATA RECEIVER

1. SETS UP ITS OWN WC AND BA.

2. LOADS CSR:

LOADS CSR:

* %EETDGYO TO1TOCLEAR

® SETSTOTO 1 TO CLEAR

® CLEARSFNCT1T0OO

® CLEARSFNCT1TOOTO

)

READY.

TO INDICATE THE BLOCK

INDICATE THE BLOCK MODE

MODE TO BE USED.

TO BE USED.

® SETSFNCT3TO1TO

® SETSFNCT1TOOTO

INDICATE NPR BLOCK

INDICATE NPR BLOCK TRANSFER.

TRANSFER.
® SETSCYCLETO1TO

INITIATE FIRST NPR CYCLE.

Figure 7-3

Block Transfer Sequence for Interprocessor Link

7-3

When the transmitter has read the data word from its memory and loaded the word onto its ODR,
BUSY is deasserted. BUSY is connected to CYCLE RQ at the receiving DR11-W. The trailing edge of
BUSY triggers an NPR cycle that writes the data word into the receiver’s memory. Completion of the
write cycle deasserts BUSY in the receiving DR11-W. BUSY returns to the transmitting DR11-W as
CYCLE RQ A. This alternating sequence continues until the word count register overflows and halts
the block transfer.
NOTE

When the DR11-W forms a link with the DRV11-B,
the DR11-W must clear FNCT 3 to 0 while the
DRV11-B must set it to a 1, regardless of which
computer is the transmitter and which the receiver.
7.2.3

Burst Mode

The NPR burst mode can be operated between two DR11-Ws only, and requires that FNCT 3 be
cleared on both DR11-Ws. The programming procedure is similar to the block mode.
Clearing FNCT 3 asserts BURST RQ on the other DR11-W. During the first NPR cycle, the BURST
RQ flip-flop sets and stays set until the last NPR cycle, during which WCOF occurs. When the
BURST RQ flop is set, it effectively holds the bus from releasing.

The timing of the burst data late one-shot on each DR11-W should be set to accommodate the speed of
its companion computer. If one-shot timing is so short as to cause bus drop, link throughput will naturally be degraded.
NOTE

Bursi mode cannoi be used where a DRV1i-B is
linked with a DR11-W (see the reference to FNCT
bit 3 in the note at the end of paragraph 7.2.2). Ncycle burst mode is not supported in a VAX/DR11W link.

7.3

PROGRAMMING

The programming characteristics of the interprocessor link are basically the same as those of a single
DR11-W configuration. However, when two DR11-Ws are interconnected, the programming of the registers is slightly modified, as explained below.
7.3.1

Word Count Register (WCR)

The function of the WCR is the same as in the nonlink mode. However, the WC INC ENB signal is
asserted continually in link mode.
7.3.2

Bus Address Register (BAR)

The basic function of the BAR is unchanged when the DR11-W is operated in link mode. However,
since the hardware configuration of the link permanently sets bit 00 to 0, interprocessor transfers are
for full words only.

7.3.3

Output Data Register/Input Data Register (ODR/IDR)

7.3.4

Control and Status Register (CSR)

The basic function of the ODR/IDR remains unchanged when the DR11-W is operated in link mode.
In interprocessor link operation, the CSR bits are defined somewhat differently than in link operation.

The differences are:

BIT 00 (GO)

When set by itself, GO conditions the DR11-W for either a transmit or a receive transfer.
7-4

BITS 1,2,3 (FNCT 1,2,3)

FNCT 1

Is 1 to a receiving DR11-W, and O to a transmitting DR11-W. If set in one
DR11-W, it is cleared in the other DR11-W. It is initialized by the software.

FNCT 2

Sends an interrupt request to the companion computer; sets STATUS B,
ATTN, and READY in the companion computer, thereby causing an interrupt
request if the computer’s IE bit is set.

FNCT 3

Has two possible meanings:
e

In back-to-back DR11-W systems, if FNCT 3 is a 0, the companion computer performs DMA transfers in the burst mode; if FNCT 3 is a 1, the
companion computer performs DMA transfers in single-cycle block mode.

In DRI11-W to DRV11-B configurations, FNCT 3 must be written to 0 by
the DR11-W. Refer to the note at the end of Paragraph 7.2.2.

BITS 4,5 (XBA 16, 17)
The functions of these bits are the same in both link and nonlink modes. Refer to Table 2-1

for definitions.
BIT 6
The function of this bit is the same in both link and nonlink modes. Refer to Table 2-1 for bit
definition. When set, this bit permits the DR11-W to generate an interrupt request if STA-

TUS B sets as a result of FNCT 2 being set in the companion computer.
BIT 7 (READY)

The function of this bit is the same in both link and nonlink modes. Refer to Table 2-1 for bit
definition.
BIT 8 (CYCLE)
This bit is used to initiate block and burst transfers when the associated DR11-W is the transmitter. When this bit is set in conjunction with bit 00 (GO), an immediate NPR cycle occurs.
The CYCLE bit is also set each time the companion computer requests a bus cycle via
CYCLE RQ, and is cleared when the cycle begins.
BITS 9, 10, 11 (STATUS C, B, A)

STATUS C

This bit is read by the computer initiating the transfer. If Status C bit is
set, the responding computer initiates a DATO; if the bit is cleared, the
responding computer initiates a DATI.

STATUS B

Reads FNCT 2 of the companion computer. When set, this bit indicates
that an interprocessor interrupt has been requested by the companion
computer. This bit also sets ATTN and READY, and causes an interrupt
request if the IE bit is set.

STATUS A

This bit functions somewhat differently in a DR11-W to DR11-W link

and a DR11-W and DRV11-B link.
DR11-W t¢c DR11-W Link

In this configuration, bit 11 (STATUS A) at 0 indicates a
burst mode NPR transfer; if bit 11 is a 1, a block mode NPR

transfer is indicated.
DR11-W to DRV11-B Link

In this configuration, bit 11 must be set in the DR11-W by

the DRV11-B; it must be cleared in the DRV11-B by the
DR11-W.
7-5

BIT 13 (ATTN)

The function of this bit is the same in the link and nonlink modes. ATTN is also set by either
FNCT 2 or ACLO of the companion computer. ATTN generates ERROR. ATTN and ERROR can be cleared by writing 0 to bit 13 of the CSR, or by initialization.
NOTE
ATTN and ERROR cannot be cleared if
the companion computer is set.

FNCT 2 of

The function of this bit is the same in both link and nonlink modes. Refer to Table 2-1 for bit
definition.
BIT 15 (ERROR)
The function of this bit is the same in both link and nonlink modes. Refer to Table 2-1 for bit
definition.
7.3.5 Error and Information Register (EIR)
The function of the EIR is the same in both link and nonlink modes. See Table 2-2 for bit definitions.

7-6

CHAPTER 8
MAINTENANCE

8.1 GENERAL
For corrective maintenance operations, four diagnostic programs are available for the DR11-W. These
programs are:

For DR11-W in PDP-11 applications:

CZDRL

CZDRK
2.

Interprocessor exerciser link-mode program.

For DR11-W in VAX applications:

ESDRB
ESDRE
8.2

Repair-level program (general NPR interface) used in nonlink mode.

On-line (user mode) level 2 program.
Repair-level program for nonlink or link mode.

ABSTRACTS OF DIAGNOSTIC PROGRAMS

8.2.1

Programs for PDP-11
CZDRL (Nonlink Mode)
This program: (1) is XXDP compatible, (2) permits multiple-board testing by using a table generated
by the user, (3) provides for burst data late calibration at a suitable point in the program, and, (4)
permits independent use of maintenance wraparound and/or cable wraparound when using the DR11W in nonlink mode.

CZDRK (Link Mode)
This program provides interprocessor diagnostic testing of the DR11-W and DRV11-B when used in the
following link combinations:
PDP-11 UNIBUS/DR11-W
PDP-11 UNIBUS/DR11-W
PDP-11 UNIBUS/DR11-W
LSI-11 BUS/DRV11-B

~
~

PDP-11 UNIBUS/DRI11-W
LSI-11 BUS/DRVI1I-B
VAXUBA/DRII-W
VAXUBA/DRII-W

For each configuration, the CZDRK (exerciser) program is loaded into each PDP-11. In the two links
containing a VAX, the ESDRE program is loaded into the VAX system as described below.

8.2.2 Pregrams for VAX
ESDRB (Nonlink Mode)
This diagnostic, written in BLISS-32, is for the DR11-W when used with a VAX. The program runs
under control of the DIGITAL Diagnostic Supervisor and XA driver to provide an on-line mechanism
for determining the logic functionality of the DR11-W by means of a two-part test. The program executes the part or parts specified by the user; i.e., maintenance wrap or (if cable is installed) cable wrap.
If neither part is specified, the mainenance-wrap portion is run by iiself.

ESDRE (Nonlink or Link Modes)
This repair-level program provides diagnostic support for the DR11-W when used with a VAX in either
of two modes; (1) maintenance wrap/cable wrap for nonlink operation and (2) link mode. Since link
mode does not support detailed testing of the DR11-W, it is recommended that mode 1 testing be performed prior to link testing. The following link configurations are valid for ESDRE testing:
VAX UBA/DR11-W
VAX UBA/DR11-W
VAX UBA/DR11-W

~
~
-~

VAXUBA/DRI1-W
PDP-11 UNIBUS/DRI1-W
LSI-11 BUS/DRVI1I-B

When linked to PDP-11s, the PDP-11 should run CZDRK.

8-2

APPENDIX A

[

I/0 SIGNAL PIN ASSIGNMENTS

GND
GND
GND
GND
D5BURSTRQL

__x A
——__xC
_____x E
—__ _x H
—
x K

Bx
Dx
Fx
Jx
Lx

——
DSCYCLERQAH
—
_D5ACLOFNCT2H
—
D5SREADYH
——_DSWCINCENBH
— DSSTATUSAH

GND —___x M
GND __x P
GND xS

Nx
Rx
Tx

——— _DSINITH
—___DSSTATUSBH
——_ DSSTATUSCH

GND e
x U
GND o
x W
GND __xY
GND ——__ xAA
D1I0ODO0OTH —
xCC

Vi
———— D5S5STATUSCH
XX ee——_DSENDCYCLEH
Zx —__DSCYCLERQBH
BBx
— __ _GND
DDx __DIODOO8H
—

DIODO06
H ——
xEE
DIODOOSH ——
xHH
DIODO04H ——_ xKK
DIODOO3H xMM
———
DIODOO02H —___ xPP

FFx
——
DI0DO 09
H
Jx
— DIODO10H
LLx
—
_DIODO11H
NNx —
DIODO12H
RRx —___DIODO13H

DIODOOIH
DIODOOOH

TIx ——_DIODO 14H
Vv ___DIODO15SH

—
——

xSS
xUU

GND —___x A
GND ——__xC

Bx
Dx

—
_D5SBUSYH
—_ _DSATTNH

GND ___x E
GND ——___x H
DSFNCT3H e
x K

Fx
JX
Lx

—___DSA0OOH
—————_DSBAINCENBH
—
_D5FNCT3H

GND ____x
e
M
GND ___xP
GND xS

Nx
Rx
T

—
_DSCOCNTLH
e
__DSFNCT2H
—__D5CICNTLH

x U

_DSFNCTI1H
—

GND M
x W
GND e xY

XX
ZX

—0_

GND

GND ____xAA
D4DIO7TH ——
_xCC

—

_D5SGOH
GND

BBx
GND
DDx D4 DIO8H

D4DIO6H —__xEE

FFx

—_D4DIO09H

D4DIOSH ——_xHH

———_D4DIIOH

D4DI0O4H —_xKK
—

LLx

—__D4DII11H
—

D4DIO3H

—

xMM

NNx

—— _D4DI12H

D4DI02ZH

—

xPP

RRx

—

D4DIOIH ————xSS
D4DIOOH —xUU

D4DII3H

TTXx —
D4DIi4H
VVx D4 DIISH

APPENDIX B

SIGNAL CROSS-REFERENCE
DR11-B DR11-W

Table B-1

Signal Cross-Reference DR11-B DR11-W

SLOT C
DR11-B
PIN

SIGNAL

CYCLE REQUEST A H

DR11-W

SIGNAL

CYCLERQAH

END CYCLE OUT H

END CYCLEH

GND

A-C

GND

Cli

DATO0 IN H

DIOOH

GND

E-H

GND

DATO1 IN H

DIOI H

DATO02 IN H

DIO2 H

DATO3 IN H

DIO3 H

DATO04 IN H

DI04 H

Fl1

DATOS IN H

DIOSH

DATO6 IN H

DI 06 H

DATO07 IN H

DI0O7H

DATO8 IN H

DIO8 H

DATO09 IN H

DIO9H

DATI0IN
H

DI10H

DATI1 INH

DI11H

DATI2 INH

DI12H

L1
L2

DSTAT BH
DATI3 INH

J1
J1

R
RR

STATUSBH
DI13H

M1l

ATTN H

ATTNH

M2
N1

DATI4INH
GND

J1
J1

TT
M-P

GND

DATI5 INH

\A'Y%

DII5SH

GND

S-U

GND

P2
R1

DSTAT A H
NO LOCK H

STATUSAH

R2
Si
S2
Tl

DSTATCH
GND
BUSY H
GND

J1
J1
J2
J1

T-V
W-Y
B
Z-AA

STATUS
GND
BUSY H
GND

AOOH

AO0 H

J1
U2
V1

+3
INITH
ECINCENBH

INITH

WCINCENBH

GND

B-1

DI 14
H

Table B-1

Signal Cross-Reference DR11-B DR11-W (Cont)

SLOT D
DR11-B

DR11-W

SIGNAL

BA INC ENBH

BA INC ENB H

SPARE
J2

A-S

GND

J2
J2

C-U
E-W

GND
GND

GND

Ci
C2
D1
D2
El

SPARE
GND
GND
SPARE
GND

H-Y

GND

FNCT1 H

FNCT1H

Fl1

CO CONTROL H

COCNTL H

F2
H1
H2

C1 CONTROL H
FNCT2 H
SINGLE CYCLE H

J2
J2
J1

T
R
K

ALCOFNCT 2 H

READY H

FNCT3 H

L-K

FNCT 3 H

K1
K2

DATI11 OUTH
DAT15 OUT H

J1
J1

LL
Vv

DO 15H

DATO09 OUT H

DO 09 H

DAT14 OUT
H

DO 14
H

M1
M2
N1

DATO07 OUT H
DAT13 OUTH
DATO05 OUT H

J1
J1
J1

CC
RR
HH

DO 07 H
DO 13 H
DOO5H

DAT12 OUT
H

DO 12 H

Pl
P2
R1

DATO03 OUTH
DAT10OUT H
DATO1 OUT
H

J1
J1
J1

MM
JJ
SS

DO O3 H
DO 10 H
DO 01 H

R2
Si

DATO08 OUT H
DAT00 OUT H

J1
J1

DD
Uu

DO 08 H
DO 00 H

EE
M-Z

GND

C1 CNTL H
BURSTRQL

DO11H

DATO06 OUT H

GND

DO 06 H

DATO04 OUT H

DO 04 H

CYCLE REQUEST BH

CYCLERQBH

DATO02 OUT H

DO 02 H

Vi
V2

GOH
GND

J2
J2

X
P-AA-BB

GOH
GND

APPENDIX C
DR11-B/DR11-W FUNCTIONALITY COMPARISON

Table C-1
ITEM

DR11-B/DR11-W Functionality Comparison*

DR11-B

DR11-W

COMMENTS

FUNCTIONALITY
1

Packaging

4-slot SU

Standard four layer hex

module
2

No. of chips

User 12 M-series

125 1Cs

modules

UNIBUS
approved
DRS/RCV on

On UNIBUS interface
only. 7400 series TTL
logic on user interface.

Yes

both UNIBUS

and external power.

After initial power
up, an interrupt

Since there is no impact
on user software, this

will occur if IE is

functionality was

set

eliminated on DR11-W.

It has no usefulness on
user application.
5

No. of user signal

The signal does not exist
in DR11-B and is added
to DR11-W for link
mode.

Specify cable, its

None specified.

length and

BCO6R with 120 ohms
and 50 ft max

termination

between user and
interface

Capable of

Yes

overlapping

The DR11-W is designed
so that when doing a

DATO cycles

DATO, it can, in same
cycle, receive user

data/control of next
word while processing
current one.

Capable of
buffering all user

signals

Yes

All user signals must be
asserted through entire
cycle in DR11-B. DR11W stored them at
beginning of each cycle.

* This table only shows functions that differ in the two interfaces. For any functions not listed, assume the performance to be
the same in both interfaces.

ITEM

DR11-B

DR11-W

COMMENTS

IDR, ICR and EIR were
added to DR11-W;

FUNCTIONALITY

No. of resisters
required

requires no additional
UNIBUS address.

20% faster than DR11-B

Cycle repetition
rate between user
and interface in

This is accomplished by
item 7.

DATOs

Interprocessor link

Block and burst
transfers in
interprocessor link

Method of
checking

maintenance mode

Cannot operate link
mode with another

DR11-B. The link
requires DA11-B which
consists of 2 DR11-Bs, 2
cables and 2 M7229
modules.
DA11-B does block
transfers only.

Use diagnostic with test
module in SU. This
requires FS call.

operation

No. of user signals
untested in
maintenance mode

User signals
CYCLERQAB

Can operate link mode
with another DR11-W or
DRV-11B. The link

requires 1 DR11-Ws (or
1 DR11-W and 1
DRV11-B) and 2 cables.
Can do both.

DR11-W can do either
two-cycle or N-cycle
burst in link mode.

User diagnostic with
logically built-in
maintenance mode (no
FS call). Use diagnostic
with jumper cable on
moduie (FS cali
required).

The methods used in
DR11-W reduce FS

None

These eight signals are

calls.

either tied to gnd, +3
Vdc, or left unconnected.

Must be received as a
low-to-high going pulse
only.

May be received as a
low-to-high going pulse
or level.

The trailing edge of
CYCLE RQ causes
DMA transfers in DR11B.

Implementation
method of

Use hard wire jumpers.

Use switches.

UNIBUS and
vector address

Replace with another

Alteration of BR
priority level

Rewire SU backplane.

AC Loads

9.1

4.2

Reliability delay
line vs RC circuits

Uses RC circuits to
generate SSYN MSYN

Uses delay lines to
generate SSYN MSYN
and other critical signals.

plug.

and other critical signals.

Release Bus

If powerfailure occurs in

gracefully upon
powerfail

CPU, it does not allow
its bus BBSY to be

released. The bus is only
released by INIT,
resulting in unexpected
DMA termination.

DR11-W will terminate

its DMA transfers and
release its Bus BBSY at
end of current transfer, if
powerfail occurs

Table C-1

DR11-B/DR11-W Functionality Comparison (Cont)

ITEM
FUNCTIONALITY

DR11-B

DR11-W

BIT 00 GO

BIT 00 GO/REG FLAG

Additional
functions

performed by

1. Causes a pulse to be

1. In addition to do what

CSR bits 00, 13,
14 and 15

sent to user, indicating a
new command has been

DR11-B does, it is used
to indicate a register

issued.

flag. When set, EIR is
read, and clears, CSR is

2. Always read as a 0.

read.

BIT 13 ATTN

1. Set and cleared by

user only.

user. It is also latched so
it is processed at

2. If ATTN is received
during a transfer, DMA

appropriate time and is

operation is abruptly

transfer, or writing a 0 to
it.

terminated and bad data
may result.
3. No visual indication
displayed, when it is

asserted (either by
disconnecting user cable
from SU or ATTN has

cleared at start of next

2. If ATTN is received

during a transfer, DMA
operation will terminate
at end of current
transfer; no bad data
should result.

been stuck high).
3. ATTN, LED, when
lit, indicates that this bit

is asserted either by
disconnect of user cable

from module, or by
ATTN being stuck high.
21

BIT 14 NEX

1. Set by nonexistent

memory, which indicates

that DR11-B did not
receive a SSYN response
20 us after asserting

that DR11-W did not

MYSN; cleared by
writing a 0 to it.

receive a SSYN response
13 us (UNIBUS) or 38
ps (11/780 or UBA)
after asserting MSYN;
cleared by writing a 0 to
it or at start of next
DMA transfers.

BIT 15 ERROR

1. Indicates an error

condition; ATTN or
NEX.

conditon; (ATTN, NEX,

2. Clear by removing
error conditions; ATTN
is cleared by user and

or PAR ERR).

NEX by writing a 0 to it.

are cleared by GO at the
start of the next DMA

MULTICY RQ, ACLO

2. Clear by removing
error conditons; all errors

transfers. In addition,
ATTN and NEX can

also be cleared by
writing a 0 to bits 13 and
14 respectively.

COMMENTS

Tabie C-1

ITEM
FUNCTIONALITY
22

=wr

DR1i1-B/DR11-W Funciionaiity Comparison (Cont)

DR11-B

DR11-W

BRrequest

Allows an interrupt to

Allows an interrupts to

initiation

occur when IE sets and

one of the following
conditons is met:

one of the following
conditions is met:

1) NEX or ATTN is

1) NEX,

generated;

2) ATTN,

2) IN NPR environinent.

3)
MULTICY RQ,
4) ACLO, or

COMMENTS

5) PAR ERR
is generated in NPR

environment.

Reading ODR for

When doing a block of

last word of a
block of transfers

DATO, CPU can

Possible bus hang
in burst mode

When doing a block
DATO, CPU can

The CPU is guaranteed
to retrieve last word in

examine last word of the
block transfers by
reading 7724X6.
However, CPU may or
may not set last word
because user data may
have already negated.

examine last word of the

DR11-W. If user has not

block transfers by
reading 7724X6. This

negated its last word,
EIR ENB does not have

can only be done by
writing a 1 to bit 15 of

to be set; therefore, there

It is possible for DR11-B

DR11-W eliminates this
possibility by BURST

to hang bus if SINGLE

CSR. The last word has
been latched.

CYCLE signal is held
asserted and successive
CYCLE RQ has not

DLT time out. The bus is
relinquished

come.

time out.

is no impact on user
software.

unconditionally at end of

An ERROR and

Add another CSR

INFORMATION

added.
26

DMA burst
transfers

It is capable of doing Ncycle burst only with no
LED indication.

It is capable of doing Ncycle and two-cycle

bursts. The N-cycle
operation is indicated by
a LED.

Violate UNIBUS
Spec

When operating burst

mode, BUS SACK is
negated immediately
after BUS BBSY is
asserted.

mode, BUS SACK is
negated during the last
cycle of a block of
transfers.

Negating BUS SACK at
the beginning of a block
of transfers does not
allow CPU to make a
true bus arbitration.

Reader’'s Comments

DR11-W Direct Memory Interface Module M8716 User’s Guide
EK-DR11W-UG-001

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