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Document:	DR11-K Interface User's Guide and Maintenance Manual
Order Number:	EK-DR11K-MM
Revision:	001
Pages:	46
Original Filename:

OCR Text

DR11-K interface
user’s guide and
maintenance manual

dlilgliltiall

EK-DR11K-MM-001

DR11-K interface

user’'s guide and

“maintenance manual

~digital equipment corporation - maynard. massachusetts

Ist Edition, March 1975

The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any errors which may appear in this

“manual.

Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

"PDP

DEC
FLIP CHIP

DIGITAL
UNIBUS

FOCAL

COMPUTER LAB

~ CONTENTS
Page

INTRODUCTION

CHAPTER 1

1.1

INTRODUCTION

1.2

GENERAL DESCRIPTION

. .. ... ... ... S
P

1.3

PHYSICAL DESCRIPTION

...
.. .. e

1-3

. . .. ... ... ...... e

ELECTRICAL SPECIFICATIONS

141

//—\\

Inputs

e e e eS e

. . .. e e

. ... .. ....... e

e e

e ee e

e e e e e e e e

1.4.2

Outputs

1.4.3

Power Requirements

1.44

Connectors . . . .. .. ... ...

e e e e

. . . ... ...... B e e

SPECIFICATIONS SUMMARY

CHAPTER 2

SOFTWARE INTERFACE

... ... e e e

SCOPE

. . . .. e e e

2.3

OUTPUT REGISTER

. . . . . .

STATUSREGISTER

. ... .. ... ... ......e

2.6.2

e e

e e e

- REGISTER AND VECTOR ADDRESS ASSIGNMENTS
e

'OUTPUT PROGRAMMING

CHAPTER 3

USER INPUT/OUTPUT SIGNALS

3.1

SIGNALLIST

3.2

CABLING

2-1
2-2

e e e st

s
e

e e

e e e e

2-4

......... e e

...

e ee
e e

4.1

JINTRODUCTION

. . oo oo

e e

4.2

4.3

INTERRUPT CONTROL

4.4

STATUS REGISTER

. o+o o o

4.5

OUTPUT BUFFER

. .« . v ittt

4.6

INPUT BUFFER

CHAPTER 5

INSTALLATION AND CHECKOUT

o
e e oL

5.1

INSTALLATION

. .

ee e

. . ... ... ...

... ....... EPSEPEERY

. ... ... ........... e e e e e e i e e
e

e e
i

e e e e

5 I

4-5
46

... ..... A ..

. . . . . ... ..t e

. . . ... ....... BT

5.1.2

Input Definition Selection

. . . ... ... .. e

513

Interrupt Enable Selection

. . . ... ...... e

Device Selection Addresses

. . . . . ... ..

5.1.7

4.1

s 4.5

it e i

Input Data Path Selection

5.2

5.1.1

5.1.6

. . . .. .......... e .25

......... e e

" THEORY OF OPERATION

5.14

2-3

. ......... L, 32

CHAPTER 4

5.1.5

2-1

e e e

e e e e ee e T e

Input Interrupting by Buffered Input Reglster Bit

2.7

e ee

e e e e e e

e e e e e e e e e e e e et

Input Interrupting by Control Llnes

130

1-3

. .. ................ PR SO

INPUTPROGRAMMING

1-3

INPUT REGISTER

2.6.1

2.2

2.6

e e

0L, ..

1-3

e e e 13

............. ee ...

2.1

2.5

e e

. . . . ... ... ... ... ..

1.5

e e e e

1-1

5-1

e e e e ...

e e e e

5-2

..o

5-2

~ Vector Address Selection
. ., .. ...e e
e
e
e e
Control Line Polarity Selection
. . . ... ... ..................

5-3
5-4

Coulter Model “S” Selection

. . . . . . . . . o .

MAINTENANCE AND CHECKOUT

. ... .. R

e e e e e

5-1

i it

AL T TE U PR

5-5

CONTENTS (Cont)
Page
CHAPTER 6

DR11-K EXAMPLES

6.1

6.2
6.2.1
6.2.2
6.2.3

6.3

6.3.1

6.3.2
6.4

INPUTEXAMPLES . .\ oottt
e it e e et et e e e i e e e i i i e e 61
Input Example 1 . . .. ... e e e e e e e e e e e e 2
e e . 61
e
e e e
e
Input Example 2 . .. . . o . o o
Input Example 3 . ... ... e e P

"OUTPUT EXAMPLES .. ... ... e e e
Output Example 1 . . .. ... .... e

62
62

e e ..
e
.
e e
e
e e e e

Output Example2 . . ... ... ... ... e e e

COULTER MODEL “S” BLOOD COUNTER INT ERFACING e

e e

6-3

e e

ILLUSTRATIONS

Title

Figure No.

1-1

1-2
1-3
1-4

1-5

1-6
2-1
2-2

3-1

32
4-1
4-2
4-3

44
4-5

4-6

5-1

52
5-3

6-1
6-2
6-3

6-4
6-5
6-6

DR11XK System Block Diagram

DR11-K Input Block Diagram

DR11-K Output Block Diagram

Page

. UL
. . . .. ...

v v e oR
. . .+« v v v v v v oo
. . . .. .. L

.12

. . .. ... ... ...... e e
M7843 HexModule
DRIl-KInputCircuitry PP

144
£5

DRIlKRegmterAsmgnments S|
Status Register Data Flow (twrite/dread) . . . .. ... ... .
..
..., .. ... 22

DRI11K Used With H322Panel

DR11-K Long Cable Arrangement
DR11XK Interface Block Diagram

. . ... ... ....vuuuuuunennnnnon. .
. ee
. . . ...
. . .. ... ... e
e e e

e
e e

Address Selection Logic, Sunphfieleagram e
e
FOrmat . . . . v v o v v v v vt i e e i e
Select Address ce
Interfa

e
e
e

34
42

. 43
. 44

£
Status Register I/O Gating (Representatlve B1t) P
. . .. .. .. - N
Data Outputting Timing Diagram

Data Input Timing Diagram . . ... .. ', e e
e e
e e.. 4T
Representative Input Line Block Diagram . . . .. ... ... D9
Control Line Output Time Variation (R118, R120, and R121) .
P
M7843 Module with Maintenance Cable . . . . . S
e
e
. . v . . v v v ino e e
Block Diagram of Input Example 1

R
62

...

Block Diagram of Input Example2
Block Diagram of Input Example 3

. . . . .. e e e

ee e e e

. . . . .. .. .. ..t

vivn

e co. 62

an . 63
Block Diagram of Output Example1 . . . . . ...« cv v v v v i i i e e e
o
Block Diagram of Output Example 2 . . . . .. ... .. PO
DR11-K/Coulter Interface . ... ........, .. e e e
of
Block Diagram

TABLES

Table No.
1-1

1-2

2-1

- 2-2
3-1

3-2
3-3

4-1
5-1

5-2
5-3

5-5

5-6

5-7

- Title

Page

Input Hysteresis Specifications . . . . .. ... ....... e e e e e e .
. . . . .+« c ot it oot ieieeeee...
DR11K Specifications Summary
.
Status Register Bit Assignments . . . . . . . . ... .. oL .o
DR11-K Address Asmgnments ..... e e e e e e e e e e e e e e e e e e e
- User Input Signals . . ... .......... P

User Output Signals

. . . . . [P e e e

Input and Output Signals

e e

. . ., . .. ... .. .. .... e

e i e
e

e ..

e ee

1-5
1-6
23
2-4
3-1

e e e e e e e e ...
Gating Control Signals . . . . . e
Input Data Path Jumper Selection . . .. ... ...e [

44
S §

Input Lines 15:12 Jumper Configurations . . . . .. . ... ... ...
...
e e e e e e
... e e e e
Interrupt Enable Switch Chart . . . . . ...
e e e e e .
e e e
Device Selection Address Lines . . . . ... .. ..... e

Vector Address Selection Lines

. . . v o v v v v it

e e

5-2
5-3
53

. ... PO £
. . ...
Control Line Polarity Selection
..o 55
Coulter Model “S” Input Configuration . . . . . . .. . . ..

CHAPTER 1
.

INTRODUCTION

The DR11-K is a general purpose digital input/output interface capable of the par‘allel transfer of up to sixteen bits
of data, under program control, between a PDP-11 Unibus computer and an external device (or another DR11-K).

12 GENERALDESCRIPTION

The DR11 K interface cohmsts of three functlonél areas address selectlon loglc 1nterrupt control loglc and deV1ce
S

)

mterface loglc (Figure 1- 1)

HYSTERESIS

INPUT

RECEIVERS

EXT_DATA READY.

INT DATA ACCEPT

INITIALIZE
DATA PATH

INPUT

JUMPERS

INPUT

INTERRUPT

SWITCHES |

CLEAR

MULTI-

PLEXER

—

CONTROL

LOAD STATUS —

IN/OUT
BUS

READ STATUS —#

MULTIPLEXER

EXT DATA ACCEPT

INITIALIZE

HI INT DATA READY
3 | LO INT DATA READY

OUTPUT .
§

DRIVERS

(5;%

OUTPUT

PROTECT

o~ )

<15:00>

)

17:00> w3 goz= &9"

A7:

C <102

SSYN

S’é[eggFlsoN

‘

INITIALIZE

DRI-K FLOW DIAGRAM

- Figure 1-1

DR11-K System Block Diagram

1-1

11-2858

The address selection logic determines if the interface has been selected for use, which register is to be used, whether

a word or byte .Operation' is to be performed- and what type of transfer (input or output) is to beperformed.

The interrupt control logtc permlts the interface to gain bus control and perform program interrupts to specific

vector addresses Interrupt enable brts are under program control; 1nterrupt bits are under control of the external
~
|
device.

- The DR11-K mterface logrc consists of three registers: status register, input regrster, and output register. Operation
is initialized under program control by addressrng the DR11-K to specify the regrster and the type of operation to be
performed

The status reglster is a 16-bit register, of which six bits are used for control and monitor functions. Two of these are

two are interrupt enable bits that
flags that reflect the status of the DR11-K with respect to the external device,
for maintenance to generate an
solely
used
are
two
and
condition,
1nterrupt1ng
interact with the Unibus on an
interrupt to the Umbus.

The 1nput regrster is a 16bit buffer between an external device and the Unibus (thure 1- 2), and includes assorted

option hardware selectable by solder jumpers and microswitches (described more fully in Chapter 5). Two control
lines are available for full duplex control communication between the DR11-K input control logic and an external
device. Each input is protected from excessive voltage and current; has hysteresis receivers for greater noise
rmmunity, can be read either directly or from a buffer register to the Unibus; can be selected to interrupt the Unibus

- from its respective buffer regrster bit; and can be used to bit-clear data from the buffer regrster

~ The output regrster is a 16 brt buffer between the Unibus and an external dev1ce (Figure 1-3). Four control lines are

‘available for full duplex control between the DR11-K output control logic and an external device. The control lines
are paired to permrtbyte operations. Each output is protected from excessive voltage and current (outputs gated for
~ logical zero). A maintenance cable supplied with the DR11-K makes it possible to check internal logic by loadmg the
1nput buffer reg1ster drrectly from the output buffer register, rather than from the external dev1ce

———

DEVICE

N INPUT
TO INTERRUPT

EXT DATA READY

~ INT DATA ACCEPTED~[CONTROL
INPUT REG READ
~ 11-2872

| Figur'el'-2‘f DRII-K Input Block Diagram

. DEVICE
-

_INT DATA READY HIGH |

le— glég"fgm

DELAY :]—

INT DATA READY LOW<e—{pgLAY

[

_EXT _DATA ACCEPTED

.TO INTERRUPT

CONTROL

11-2873

.Figure 1-3 DRI 1-K Output Block Diagram
1-2

,,,,,,

The DR11-K can also be used as an interprocessor buffer to allow two PDP-11 processors to transfer data between
themselves. One DR11-K is connected to each processor bus, after which the two DR11-Ks are cabled together
output-'to-input to permit the processors to communicate. (Refer to the example in Chapter 6.)
1.3

PHYSICAL DESCRIPTION

The DR11-K is packaged on a single M7843 hex module (shown in Frgure 1 4) desrgned for use in one of the center
SPC slots of a DD11-A or DD11-B. Various user--selected options can be implemented by PC-mounted microswitches
and by solder-type jumpers, both of whrch are marked on the module to assist in identification. These are discussed
'

in Chapter 5 of this manual.

1.4

ELECTRICAL SPECIFICATIONS

14.1

Inputs

All input lines to the DRll K are TTL—compatrble Each 1nput has a 47 ohm fusible resrstor that opens when the

current exceeds 250 mA and has recoverable over-Voltage protection up to +15 Vdc or -10 Vdc. A logical 1 is
represented by O V.on an input line (except for input lines 15:12, which are optionally redefrned) A linemust sink
a minimum of 3.5 mA and maintain a voltage of less than 1.0 V at the receiver end for a logrcal 1. Frgure 1-5 shows
|

the basic input crrcurtry

Input lines have hysteresrs for both high and low thresholds allowrng the DR11-K a high degree of noise 1mmun1ty

Table 1-1 shows the 1nput voltage specrficatrons 1.4.2

Outputs

All output lines from the DRll Kare drrven by open collector logrc Each can srnk 30 mA of current to OV for a
logical 1 output and source 5 mA of current to +4 V for a logical 0 output. Figure 1-6 shows the basic output
circuitry.Each output has a fuse that opens when current exceeds 250 mA and has overvoltage protection whenina
Zero state

1.4.3

Power Requlrements :

14.4

Connectors

The M7843 module requrres +5 Vdc at 2. 5 A maximum (2 A statrc) from the Unibus power distribution.

The M7843 module contains’ two 40prn H854 mput/output connectors for all user input/output signals. Pin

assignments for these connectors are shownin crrcurt schematic.D CS M7843 0 1, sheet D8 or Figure 3-3.
1.5

SPECIFICATIONS SUMMARY

The specifications for the DRll -K 1nterface are summarrzedin Table 1 2

1-4

2In3L -1

:.Mv.feu.T?hfsrfl,:..‘w.nrf.ifriu“ dux}...r;?.r .
B

—

TFmnEeGETEL

Mw..%wfl%...S

S6LL

+|5V

an
47o OHMS

OHMS

: :
M——

2 3.3
$330
1
D

RECEIVER

T 820PF

| - 2861

Figure 1-5 DRI11-K Input Ci'rcuitry'

Table 1-1

Input Hysteresis Specifications

MIN.

'High Threshold Input

Low Threshold Input

1.0

20V

r |

10V

14V

MAX.

1.4

+5V

OPEN

‘

$470 OHMS
1

COLLECTOR—-—DC :
— |
% |
DRIVER

1/4AFuUsSE

ono——=
OUTPUT
Iy

11-2862

- Figure 1-6 DR11-K Output CifC‘Uith'

24V

T'able‘ 1-2

- DR11-K Specifications Summary

Specifiéation

Usage |

Description

| 'General purpose data inp_ut/outpfit

Input/Qutput Levels

logic 1 =0V (less than 1.0 V)

logic0=+4V

Optionally redefined

Inputs 15:12 only

Addressing
Status Register

167 770

Input Register

167 772 t (Base address may be changed)

Output Register

167 774

Unibus Interface

Interrupt Vector Address
- Input Vector Address

Floating
300

Output Vector Address
Priority Level

- 304
)

}(Base address may be changed)

BR4 (May be changed)
One bus load

Bus Loading

Mounting

One SPC slot

Size

Hex module

Input Current
Environment

25 A2 Astatic)@+5V

Operating Temperature

Relative Humidity

«v“"'s\

Mechanical

+5° C(41° F)t0 43° C(110° F)
20%
to 80%, noncondensing

Miscellaneous
Inputs

TTL-compatible

Overvoltage protection from -10 Vdc to +15 Vdc by 47-ohm fusible resistors that open when current exceeds 250 mA.

Hysteresis for both high and low thresholds
QOutputs

All driven by open collector logic.

Overvoltage-protected and current-protected by fuses that open when
current exceeds 250 mA when in a zero state.

Data Outputs
-

Maintenance Mode

16-bit word from user’s device

16-bit word from Unibus, either as full word or 8-bit byte (either high
or low)

' A maintenance cable supplied with the DR11-K jumpers the output to
the input register for testing.

1-6

/”’\

Data Inputs

CHAPTER?2

SOFTWARE INTERFACE

2.1 SCOPE

This chapter presents a detailed description of the DR11-K registers (Figure 2-1). These regrsters are assigned bus
“addresses, and can be read or loaded using any instruction that refers to their addresses. The mnemonic INIT refers
|

to the initialization signal issued by the processor. Initializationis caused by any of the following:

‘a.

Issuance of a programrned RESET instruction.

Occurrence of a power-up or power-down condition of a system power supply

b. Pressrng of the START switch on the processor console.

The addresses assocrated with 1nd1vrdua1 regrsters can be changed by alterrng the microswitches in the address
selection logic. However, any programs or other software referring to those addresses must be modified to reflect the

—~

- alterations: Paragraphs 2.2 through 2.4 describe the operation of the individual regrsters

Unused regrster bits are always read as logrcal Os; loadrng unused or read-only bits has no effect on the bit position.
-

2.2

INPUT REGISTER

The input register is a 16-bitregrster that receives data from anexternal device for transmission to the Unrbus The

external device places the data onto the DR11-K data input lines, where it is read by a DATI sequence either directly

off the input lines or from the buffer register, depending on the option selected. There are two methods of
interrupting; erther by the control lines or by the buffer register bits through their respective interrupt switches. If

OUT | SET

;fl{g INTR | INTR

ENB | ouT

O08

IN | SET

FlflewlNTR INTR |
ENB | IN

15
OUTPUT DATA BUFFER

INPUT DATA BUFFER
11-2864

Figure 2-1 DRI11-K Register Assignments

2-1

,,,,,,

the control lines are used, the interrupt to the Unibus for a DATI sequence is produced by the EXTERNAL DATA
READY line. When the data is read, the DR11-K notifies the external device on the INTERNAL DATA ACCEPTED

line. If the buffer register bits are used for interrupting, the interrupt to the Unibus for a DATI sequence is produced
by presenting the correct transition on the input line that corresponds to the bit selected to interrupt. The input
buffer register is bit-cleared by performing a write to the register with the bits to be cleared. In order to interrupt the
Unibus, the Input Enable bit of the status register must be set; the bit is cleared when the Unibus accepts the

interrupt. Any unused 1nput line will read as a logical 0.
‘When the mamtenance cable is used, the input reglster receives data from the output register rather than from the
external device. This permits checking of the interface logic by loading a word from the bus into the output register
and verifying that the same word appears in the input register.
Examples of the way in which the input register is used in specific applications appear in Chapter 6 of this manual.
2.3

OUTPUT REGISTER

The output buffer is a 16-bit read/write register that may be read or loaded from the Unibus. Data can be loaded

into this register under program control in either byte or word format. After the data is loaded,
a pulsed signal
(INTERNAL HIGH DATA READY or INTERNAL LOW DATA READY) permits the external transfer of data to
either or both of two 8-bit devices. The output of the buffer is fed directly to the bus data lines. If 16-bit transfer is

desired, either line can be used. When the external device has accepted the data, it sends back a pulsed signal

(EXTERNAL DATA ACCEPTED), which causes an interrupt to the Unibus if the Output Interrupt Enable bit

(status register bit 14) is set. When the interrupt is accepted by the Un1bus, the bit is cleared. The contents of the
output register may be read at any time by means of a DATI.

When the maintenancecableis used,the data from the output reg1ster is apphed to the mput buffer reg1ster makmg ~

it poss1b1e to check the operation of the interface logic.
2.4

STATUS REGISTER

The status register is used to enable interrupt logic, cause maintenance interrupts, and provide defined status
functions from the external device. Input and Output flags react to signals from the external device, two Enable bits

permit interrupts to occur when external signals are received, and two maintenance bits activate the interrupt logic.
Figure 2-2 shows bit ass1gnments and the status register data flow Table 2 1 prowdes a brief descr1pt1on of each bit

in the status register.

lrFLaG

INTR|

SET

[ out | OUT[MAIN

09 08 O7T
|

FLAG

05 04

| IN_[MAIN

02 Ol

INTR | SET

UNIBUS
11-2863

Figure 2-2 Status Register Data Flow ({write/read)

”

Table 2-1

Status Register Bit Assignments

Bit

Title

OutputFlag

|
|

Description

This bit sets when an EXTERNAL DATA ACCEPTED has been

received from an external device.

~ Output Interrupt Enable

* This bit enables an interrupt to occur when an EXTERNAL DATA

ACCEPTED has been received. It is cleared when the interrupt is
accepted by the Unibus.

Set Interrupt Out

| This bit is used for maintenance only. When the DR11-K receives

Input Flag
o

this bit, an output interrupt to the Unibus is generated.

This bit sets when an EXTERNAL DATA READY has been received
from an external device.

Input Interrupt Enable

"I’hjs bit enables an interrupt to occur when an EXTERNAL DATA
-

READY has been received. It is cleared when the interrupt is
accepted by the Unibus.

Set Interrupt In

* This brt is used for maintenance only. When the DRll -K receives
this bit, an input interrupt to the Unibusis generated.

2.5 REGISTER AND VECTOR ADDRESS ASSIGNMENTS
Register and vector addresses are configured prior to shipment to standard configurations, but may be changed by
means of switches on the M7843 module. Chapter 5 describes the procedures in detail. Regrster address lines are

swrtched on for a logical 0; vector address lines are switched on for a logical 1.

The DRII -K has floating addresses to allow the use of more than one DR11-K in a system, or to avoid any device
address conflict with other options. The register address is selected by switches on the M7843 module representmg
address lines A12: A03. The standard register addresses selected for the DR11-K are:

167770
167772

Status Register Address
Input Address

167774

Output Address -

The vector address is selected by swrtches on the M7843 module representrng vector lines (Unrbus “D” lines)
- D08:D03. The standard vector addresses seleeted for the DR11-K are:
~

300
304

Input Veetor Address
Output Vector Address

Floating register and vector addresses are listed in Table 2-2.

Table 22
DR11-K Address Assignments

No. of DR11-Ks

Reglster Addresses .

Vector Addresses

DR11-K No. 0 -

167774 — 167770

300, 304

167764 — 167760

310,314

167754 — 167750

320,324

167704 — 167700

370, 374

DRI1KNo.1

DRI1-KNo.2

DR11-KNo.7

DR11-K No. 15

167604 — 167600

470, 474

The addresses in the table assume that the system contains only DR11-Ks, and no DR11-As. Addresses must be |

assigned for any DR11-A

interfaces present in the system before DR11 K addresses are ass1gned The floatmg vectors

e Al o

. Startmg at 300 and proceedl_ng upward,.all- DCl 1s.

of the DR11 K are assignedin the following sequence:

Any DR11-As.

Any extra KL11s called for (VTOS, VT06, LC11). .
Any DP11s.

Any DM11s.

Any DN11s.

Any DM11- BBs.
Any DR11-Ks.
NOTE

Some devices use only one vector address.

The M7843 is normally shipped W1th a pr1or1ty level configuration of BR4; th1s level may be changed by replacmg
the jumper module for another level.

2.6 INPUT PROGRAMMING
2.6.1

Input Interrupting by Control Lines

Input interrupts can be generated by the control lines, starting when the external device sends an EXTERNAL

DATA READY signal to the DR11-K. That signal generates an interrupt to the Unibus if the Input Interrupt Enable

is set, and sets the Input Flag of the status register. When the Unibus accepts the interrupt, the Input Interrupt

2-4

Enable bit is cleared. The program is vectored to a subroutine, where the data is read. If the input register is used for
data inputting, it must be cleared before new datais sent by the external device. The program for input 1nterrupt1ng
by control linesis as follows:

MOV #00100, Status

WAIT

INVECTOR

BRINPUT

INPUT

/Set up IN INTR ENAB.

[WAIT for EXT DATA READY to generate 1nterrupt

/IMP to input subroutine.

MOV #00100, Status
MOV INPUT, Memory

/Set up IN INTR ENAB & CLR IN FLAG.
/Read and store the input data. This will generate an
/INTERNAL DATA ACCEPT.

2.6.2 Input Interrupting by Buffered Input Register Bit
When the input register bits are set up to interrupt, an external device can generate interrupts by setting any of these
bits. If the Input Interrupt Enable is set, an interrupt is generated to the Unibus. When the Unibus accepts the
interrupt, the Input Interrupt Enable bit is cleared. The program is vectored to a subroutine, where the input data
register is read. Individual register bits can be cleared by performing a Write to the input register. The program for
input interrupting by register bitsis as follows:

MOV #177777 Input
MOV #000100, Status

WAIT,
IN VECTOR,
INPUT

2.7

WAIT
BR INPUT
MOV Input, Memory
MOV Memory, Input
MOV #000100, Status
HLT or BRWAIT

[Clear input register.
/Set up IN INTR ENAB.

/WAIT for a bit to generate an interrupt.
/Branch to input subroutine.
/Read and store input register.
[Clear bits that INTR.
/Set up IN INTR ENAB.
/Halt or go back to WAIT for other interrupt.

OUTPUT PROGRAMMING

When data is loaded into the output register, a byte-oriented control 31gnal (INTERNAL DATA READY)is sent to
the external device requesting it to read the output lines of the DR11-K. The external device does so and sends a
control signal (EXTERNAL DATA ACCEPTED) to the DR11-K which generates an interrupt to the Unibus, if the
Output Interrupt Enable is set, and sets the Output Flag of the status register. When the Unibus accepts the
interrupt, the Output Interrupt Enable bit is cleared. The program is vectored to a subroutine, ‘where new data can
/TN

be loaded into the output register.

The program for transferring data to an external device is as follows:

OUTPUT
|
OUT VECTOR

MOV #040000 STATUS REG

/Set up OUT INTR ENAB.

MOV #177777 OUTPUT REG

/Loads data into output register.

|
[WAIT for EXT DATA ACCEPT to generate 1nterrupt
[EXT device read data.

WAIT
HLT

2-5

3.1

3
CHAPTER

USER INPUT/OUTPUT SIGNALS

SIGNAL LIST

Tables 3-1 and 3-2 list the sign’_als.that permit the DR1 IQK to interact with an external device. Table 3-3 references

‘those "signalsvtO the two H854 connectors located on the M7843 module.
Table 3-1
User Input Signals

Signal

IN15 through INOO

| o

Description

Thé-se‘ 16 lines are used to transfer data from an external device into the

DR11-K.

EXTERNAL DATA READY ;

'INTERNAL DATA ACCEPTED

This control line is used to indicate that data from an external device is

're'ady‘.for transfer to the DR11-K.

_This'cvzozntrol line is used to indicate to an external device that the data

has been read off the '_‘input lines by the DR11-K, and that new data can
|
|
be sent.

Table3-2

User Output Signals

Signal

'OUT15 through OUT00
R
|

| These 16 lines are used to transfer data from the DR11-K to an external
|
|
device.
'

EXTERNAL DATA ACCEPTED =

(21lines)

Description -

These two contfol' lines are used to indicate to the DR11-K that data

- has been read off the output lines by the external device and that new
data can be sent.

INTERNAL LOW DATAREADY
|

‘

This control line
is used to indicate that data in DR11-K output register

bits 07—00 is ready for transfer. This line is activated when a LOAD
LOW BYTE or LOAD OUTPUT REGISTER occurs.

| INTERNALVHIGH DATA READY
|

INITIALIZE

This control line is used to indicate that data in DR11-K output register

_- |

‘bits 15:08 is ready for transfer. This line is activated when a LOAD
'HIGH BYTE or LOAD OUTPUT REGISTER occurs.

This line is used to indiéate to the external device that the PDP-11 has

been turned ON/OFF or the system has been initialized by the
_software.

3-1

3.2

CABLING

The signal distribution of the DR11-K interface is designed to minimize cross-talk. Alternate grounds are used to
separate signal lines when a BCO8-R flat cable is used. Up to fifty feet of BC08 R cable can be used between the
DR11- K and the external device.

If longer cabling is necessary, a distribution panel, such as an H322 is recommended to distribute the lines of two
BCOS8-R cables to 80-screw terminals, making it possible to distribute both input and output lines from this panel.
Figure 3-1 shows the M7843 module plugged into a system unit and connected to an H322 distribution panel.

Twisted-pair-with-shield-type cable (such as BELDON No. 8777, 8755, 8725, or equivalent) is recommended to
carry the DR11-K signals from the H322 panel to an external device up to 300 feet away, as shownin Figure 3-2.
.

Table 3-3

Input and Output Signals

Inputs

Signal

INOO

INO1
INO2
INO3

|
|

INOS

INO6

IN12

IN13

IN14

IN15

EXT DATA RDY

EXT DATA ACC

OUT00

Connector

ourTO1
OUTO02.
OUT03

|
|

J2
12
J2

M
P
S

OUTO04

)

ouTo05

OUTO06

)

ouTo7

T
R
N
L

ouTo8
OUT09
OuUT10
OUT11

2
J2
J2
L
J2

CC
EE"
HH
KK

‘OUT12

~ ouT13

OUT14

Signal

)
J1
J1

Jj..
FF
DD

J1
|

Outputs

INO7

Pin . |

J1
o J1
J1r

INO4

INO8
'INO9
INIO
IN11

‘

Connector

NN,RR

. OUT15

o
|

J2
|

~ INT HI DATA RDY

INT DATA ACC

~ INTLODATARDY |

INIT
INIT

3-2

18]9)

\AY

J2
J1

#G8H

3-3

ouT

DRI1-K
BCO8-R

USER

DEVICE

LT4

SHIELDED cm%

SHIELDED CABLE

USER
DEVICE
11-2865

Figuré 3-2 DRi 1-K Long Cable Arrangement

CHAPTER 4

THEORY OF OPERATION

4.1

INTRODUCTION

This chapter provides a detailed description of the DR11K interface. The DR11-K may be divided into five major
functional areas: address selection logic, interrupt logic, status register, input register, and output register. F1gure
4-1 shows the interaction of these areas. The basic purpose of each area is as follows:
Address Selection. Logic

Determines if the DR11-K interface has been selected for use, which register

is to be used, whether a word or byte operation is required, and what type of
transfer (DATI or DATO) is to be performed.

Interrupt Logic

Permits the DR11-K to gain bus control and perform a program interrupt.

~ Status Register
|

A 16-bit register that provides status of the DR11-K with respect to the
extemal

device;

includes

interrupt

interrupt.

- Input Register

enable

and

generates maintenance

A 16-bit register that receives data from the external device for transmission
_' ~ to the Unibus.

Output Register
|

)

A 16-bit read/write register that can be loaded or read from the Unibus. Once

the register is loaded, the data is available
for transfer to the external device.

4.2 REGISTER ADDRESS SELECTION

The address selection logic (circuit schematic D-CS-M7843-0-1, sheet D3) decodes the incoming address information

from the bus and provides the select lines and gating signals that determine which register has been selected and
whether an input or output function is required. Switches on the logic are arranged so that the module normally
responds only to device register addresses 167770, 167772, and 167774. These addresses have been selected
arbitrarily by Digital Equipment as standard assignments for the DR11-K interface. The user may change the

switches to any address desired; however, any MAINDEC or other software program that references the DR11-K
standard address assignments must be modified correspondingly if other than standard assignments are used Chapter
5 discusses the technlques for modification of the address assignment bits.

The fiISt five octal digits of the address (16777—) indicate that the DR11-K has been selected as the device to be
used. The final octal digit, consisting of address lines A02, AO1, and AQO, determines which register has been
selected and whether a word or byte operation is to be performed. The two mode control lines, C1 and CO,
determine whether the data in the selected register is to be the subject of a BUS DATA IN or a BUS DATA OUT
function off the Unibus.

4-1

INPUT
PROTECT

|_EXT DATA READY
INT DATA ACCEPT

INITIALIZE

INPUT

INTERRUPT
SWITCHES

INPUT
CLEAR

MULTIPLEXER

INTERRUPT
CONTROL

LOAD STATUS —
IN/OUT

READ STATUS —#{

‘BUS

DATA

“MULTI-

STATUS

PLEXER

|
.

HI INT DATA REQDY
LO INT

DATA READY

" QUTPUT

OUTPUT

‘

r\ EXT DATA ACCEPT
,
H854

INITIALIZE

DRIVERS

PROTECT

20"

“ADDRESS

‘SELECTION

]
INITIALIZE

DR11-K FLOW DIAGRAM

‘

11-2858

Figure 4-1 DRI 1-K Interface Block Diagram
Address lines A02 and AO1 are decoded to produce select line signals that select the register to be used. The two
mode control lines produce BUS DATA IN and BUS DATA OUT signals that determine whether the bus cycle is a
DATI or DATO. A BUS DATA IN signal is provided for all three registers because all three can be read from the bus;

a BUS DATA OUT signalis provided for all three registers because all three can write from the bus.

There are two BUS DATA OUT signals, OUT LO and OUT HI, that refer to the low and h1gh bytes of a reglster,

respectively. The basic functions of the BUS DATA IN and BUS DATA OUT signals are:

The DR11-K responds by placing data from the seleCted registér’f onto the Unibus data lines.

OUTLO

The DR11K loads the low byte of the selected rvegis'tér from théfUnibus data lines.

OUT HI

The DR11-K loads the high byte of the selected register from the Unibus data linflés.

Note that both BUS DATA OUT LO and BUS DATA OUT HI are active when a full 16-bit wordis being loaded into
a register.

A s1mp11fied block diagram of the address selection logic appears in Figure 4-2. Note that BUS DATA IN and BUS
DATA OUT are always used with reference to the master (controlling) device. Thus, BUS DATA OUT transfers
represent transfers of data out of the Unibus and into the DR11-K; s1m11ar1y, BUS DATA IN transfers represent data
transfers from the DR11-K to the Unibus.

BUS

I
EE"‘
-

BUS MSYN L

BUS A7 L
{l

" CONTROL

EV ENABLE |

EE 2J,|

ED 2
| Em:l
\Y|

EK 2,,.

EC
EL |

$3-2 |
s3 3
ADDRESS

543

_EP1s

COMPARATOR

54 8

/—\\

_‘-4__8‘
S4- 5

7
34

EU1

S4- s

:' S4 - 2
54-1

BUS AO3L

BUS AOO L

_EH2]

BYTE CONTROL

BUS C1L

BUS AO1I L

GATING

STROBE

OUT LO

—

OUT Hi

DECODER
N UX

SELECT

‘ :

STROBE

VBUS' COoL

DECODER

SELECT

I
ADDRESS SELECTION LOGIC

LD INPUT HI-

| Lo INPUT LO

l LD OUTPUT HI
| Lo ouTPUT LO

' LD STATUS HI

| LD sTATUS LO

| RD OUTPUT H
|

{ RD INPUTH

' RD STATUS H
EXT GND

— — —

.}
EF1

BUS AO2 L

SWITCH ON= o
SWITCH OFF-1

11-2877

Figure 4-2 Address Selection Logic, Simplified Diagram

Input signals of the address selection logic consist of 18 address lmes (A17:A00), two bus control lines (C1, C0), and
a master synchronization (MSYN) line. The address selection logic decodes the incoming address as descnbed below,
according to the format shownin Figure 4-3. (All input gates are standard bus receivers.)

In Figure 4-3:

a. | Line AQO is used for byte control.
b.

Lines A0l and AO2 are decoded to select one of the four addressable dev1ce registers (only three are
used).
:
A,

Decoding of lines A12:A03 is determined by switches. To the address log1c a swflch OFF
=1, and a
switch ON
= 0.

Address lines A17:A13 must be all 1s, specifying an address W1th1n the top 8K byte address bounds for
device registers.

SELECTED

BY JUMPERS

MUST BE ALL 1's

DECODED FOR 1 OF 4 REGISTERS <
BYTE CONTROL

“1-0029

Figure 4-3 Interface Select Address Format

Table 4-1 indicates the gating control signals that determine the bus sequences to be initiated.
Table 4-1

~ Gating Control Signals

Mode Control

Byte Control

- CO

A00

Gating Control

Bus Sequence

Signals True
(*+3V)

0
0

0
1

DATI
DATI

0
0
1

1
1
0

0
1
0

IN
IN
OUT LOW

DATIP
DATIP
DATO

OUT HIGH

1
1

OUT LOW

1
1

OUT HIGH

OUT LOW
-OUT HIGH

4-4

DATO
N

DATOB

4.3

INTERRUPT CONTROL

The interrupt control logic permits the DR11-K to gain control of the bus (become bus master) and perform an

interrupt operation. The switches and jumpers on this logic can be arranged so that vector addresses can be assigned
other than those configured as standard on the module for alignment. (Refer to Chapter 5 for details.) The interrupt
control logic consists of a dual interrupt request and grant acknowledge circuit for establishing bus control.
One method of causing interrupts to the Unibus employs the two control lines between the DR11-K and the

external device. If the Input Interrupt Enable (bit 06 of the status register) is set, a negative transition (+3 V to

ground) of the EXTERNAL DATA READY pulse will generate an interrupt to the Unibus, with a vector address of
300. (Refer to circuit schematic D-CS-M7843-0-1, sheet D5.) A bus request is made on the BR level that corresponds
with the level of the priority plug in the logic (sheet D2). (The standard level for the DR11-K interface is BR4; this
may be changed on the priority plug if desired.) When the priority arbitration logic in the processor recognizes the

request and issues a bus grant signal, the master control circuit acknowledges
with a SACK signal. The control line
method of interrupting is logically ORed into the DR11-K interrupt control,
and is disabled by internal clamping

circuitry if not desired.

The second method of mterruptmg is by using the individual input lines. Each 1nput (IN15:INOO) is buffered by a
flip-flop that will set on a negative transition (+3 V to ground). (Refer to circuit schematic D-CS-M7843-0-1, sheet
D6.) Switches for the buffered bits on the M7843 module make it possible to wire-OR each bit onto a common
interrupt line; when the Input Interrupt Enable (bit 06 of the status register) is set and a switch is on, the transition

of the associated bit causes an interrupt to the Unibus. The bits are read under program control by reading the input
register, and are cleared by moving data 1s to the bits to be cleared. The Input Interrupt Enable is cleared when an
‘input interrupt is accepted by the Unibus; when reset, it will retrigger the interrupt circuit if any other input bits
were set during the program service subroutine, so that new interrupting bits will not be lost.

When data is loaded into the output register in byte or word format, a pulse on INTERNAL HIGH DATA READY

or INTERNAL LOW DATA READY permits the user to transfer data to two 8-bit devices or to a 16-bit device
(sheet D7). Upon accepting the data, the external device sends EXTERNAL DATA ACCEPTED, causing an
interrupt to the Unibus, vector address 304, if the Output Interrupt Enable (bit 14 of the status register)is set. The
enableis cleared when the Unibus accepts the interrupt.

Vector addresses are determined by bits D08:D02. Bits D08:D03 are selectable by PC-mounted micfoswitches, as
“described in Chapter 5, to determine the two most significant octal digits of the addresses (sheet D2). D02
determines the least significant digit, so that all vector addresses end
in either O (input) or 4 (output). When the bus
AT

indicates an output transfer, assertion of D02 causes a vector at locatlon 304; for an input transfer, the unassertion
of D02 causes a vector at location 300.

‘

If the DR11-K is not issuing a request for an interrupt, the BG IN signal is allowed to pass through the logic to BG

OUT (sheet D2). The ANDing of the request and the enable is necessary to request bus use. These levels must be true
until the Unibus interrupt service routine clears one or the other. Bus control is maintained until the processor

responds with BUS SSYN after it has strobed in the interrupt vector; the logic then inhibits further bus requests
from that source until either the request or the enable is dropped and then reasserted, preventing the logic from

reasserting the request line. This prevents multiple interrupts when the master control is used to generate interrupts.
4.4

STATUS REGISTER

The status register (sheet D4) is a 16-bit register used to report the status of the external control lines, enable
interrupts, and generate mamtenance interruptsto the Umbus (Flgure 2-2 shows the status register data flow and

gating.)

‘Four of the bits (06 07, 14, and 15) are read/wnte bits under program control and can be read or loaded from the
bus. The other two bits (05 and 13) are write- only bits used for maintenance only, and are applied directly to the

interrupt control logic to initiate an interrupt sequence. The read/write capability is accomphshed by the BUS

DATA IN and BUS DATA OUT gating logic shown on sheet D4. A simplified version of a representative bit (bit 06)

is shown in Figure 4-4. The other three read/write bits function similarly.
4.5

—-—-\‘ BUS DATA 06»

READ STATUS

BUS DATA 06
-

ENABLE INTERRUPT IN

LOAD STATUS LO
INITIALIZE
L
CLEAR
7
IN
INTERRUPT

(from Bus Control)

11-2689

Figure 4-4 Status Register I/O Gating (Representative Bit)

When the status register is addressed for reading, READ STATUS from the address selection logic gates the ENABLE
INTERRUPT IN output of the flip-flop to bus data line 06 for reading (Figure 4-4).

If it is desired to load the status register, the appropriate level is placed on bus line BUS D06 and serves as the data

input to the flip-flop. The clock input becomes true when the register is addressed for loading.

The flip-flop outputs of bits 06 (ENABLE INTERRUPT IN) and 14 (ENABLE INTERRUPT OUT) are applied as an

in Paragraph 4.3.
enabling level to the interrupt control logic described
4.5

OUTPUT BUFFER

The output buffer is a 16-bit read/write register that can be read or loaded from the Unibus. When this buffer is

addressed for loading, the LOAD OUT HIGH and LOAD OUT LOW signals are true, and applied to one-shot delays

that are set up for an output of 1 us (sheet D7). (In user applications involving long cabling, the added capacitance
may require more time. By increasing the resistance factor by a value of up to 50 kilohms, as discussed in Chapter 5,

it is possible to increase the one-shot delay by up to an additional 4 us.) The resulting INTERNAL HIGH DATA
READY or INTERNAL LOW DATA READY signal is transmitted to the external device to inform the user that the
output buffer register has been loaded in byte or word format. These signals load the output buffer close to their

leading edges; to allow for long cabling, the user’s logic should sample the data lines on the trailing edges of the
pulses (Figure 4-5). The output buffer can be loaded with a full 16-bit word (DATO), or with either a high-order or
low-order 8-bit byte (DATOB). Selection of a DATO or DATOB depends on the incoming address and the address
selection circuits described in Paragraph 4.2.

4.6

INPUT BUFFER

The 16-bit input register receives data from an external device for transmission to the Unibus. Each input has its
noise immunity increased by receivers with hysteresis, and has overvoltage and current protection circuitry. The
input register can be either read off the input lines or buffered by a 16-bit buffer register, which is selectable by
solder jumpers (Chapter 5). When the input register is read off the input lines, each bit is represented by a logical 1
as a Low (less than 1 V) and by a logical 0 as a High (+3 V). When data is read from the input buffer register, each

buffer bit is set by a negative transition on the associated register input line. Bits 15—12 can also be selected (by
solder jumpers) to be set by positive transitions or by either positive or negative transitions (Chapter 5).

There are two control lines associated with the input register, EXTERNAL DATA READY and INTERNAL DATA

ACCEPT. The external device places data on the input lines and, after transients have had time to settle (Figure 4-6),
activates the EXTERNAL DATA READY signal line, generating an interrupt to the Unibus (Paragraph 4.3). When
ACCEPTED line to notify the external device that it
DATA NAL
the data is read, the DR11-K activates the INTER
can send new data. If these lines are not used, internal clamping will disable them. The buffer register bits can also be
~
by microswitches to generate interrupts to the Unibus (Paragraph 4.3 and Chapter 5).
selected
4-6

[

LOAD OUTPUT REGISTER

HIGH BYTE (PROGRAM)

LOW BYTE (PROGRAM)

OUTPUT

DATA
1

1))

))

l
X
_J1

X
—

INTERNAL HIGH DATA
READY (DR11-K)

]

LOAD OUTPUT REGISTER

‘

({

's.,5psec

‘

INTERNAL LOW DATA
READY (DR11-K)

‘

|
|

DATA LOADING EDGE

EXTERNAL DATA ACCEPTED
LINE (DEVICE)

< .Spusec

INTERRUPT GENERATED

TO UNIBUS (DR11-K)

WAIT F OR
UNIBUS TO ACCEPT

NEW DATA
SEQUENCE

INTERRUPT

Figure 4-5

(DEVICE)

FOR SETTING

INTERRUPT GENERATED

TO UNIBUS (DR11-K)

’

)

‘

I__J

)

I
I

)3
[

I
I

) )

|O W

I
|
TO DATA IN SUBROUTINE I
|

PROGRAM 1S VECTORED

=5 peec
-

EXTERNAL DATA
READY (DEVICE)

DATA ON LINE °
(DEVICE)

TO ACCEPT INTERRUPT

INTERNAL DATA
ACCEPTED (DRit-K)

WAIT FOR UNIBUS

INPUT DATA READ

(PROGRAM)

1-2875

Data Outputting Timing Diagram

1 ALLOW

LOADS DATA

)

Y
"\

))
R

11
L
=Susec

|
|

NEW DATA
SEQUENCE
11-2874

Figure 4-6 Data Input Timing Diagram

CHAPTER D
INSTALLATION AND CHECKOUT

INSTALLATION

The DRI 1-K interface is designed for use in one of the center SPC slots of a DDll A or DD11-B. Before the M7843

‘module is installed, all of the jumpers and microswitches should be configured to select the desired options. The
switches and jumpers are marked on the module itself for easy identification. The paragraphs that follow discuss the

switch and jumper configurations and the options that they control.
If other than standard eonfiguratrons are selected, all MAINDEC and other software programs referencing the

standard assrgnments must be modrfied to reflect the new configurations.
5.1,1

Input Data Path Selectlon

Each input 11ne can be configured so that its data can be read directly off the hne or from the buffer register,

depending on the configuration of jumpers W5 through W20. Table 5-1 indicates the solder-type jumper
configurations that will select each input data path. The module is normally shipped with the jumpers configured to
select buffer register input on all lines. Figure 5-1 contains a block diagram of a representative input line, showing
the data inputting and interrupting paths.

Table 5- 1

Input Data Path Jumper Selection
-

Jumpers for Readlng

Input

Line

Direct Line

Input

W5-B

W6-B

W7-B

‘W8B

W9-B

10
9

W10-B
W11-B

Wi2-B

-7
6

W13-B
‘Wi14-B

‘Wi1s-B

Wi16-B

3
2

W17-B
W18-B

W19-B

W20-B

Buffer Regrster InputTM

Ws-A
:

W6-A

W7-A

WS8-A

Wo-A

WI10A
W11-A
Wi12-A

WI13-A
WI4-A

Wi15-A
|

W16-A

W17-A
W18-A

|
|

W19-A
-

*Normal configuration for shipment.
5-1

W20-A

INPUT

LINE X

(W5-w20)
B
o

INPUT

~~x0——— TO DATA BUS

PROTECT

TRANSITION

“A

- 2p———» BUFFER

CLEAR

TRIGGER

EXT DATA READY
INT
o

FROM OTHER
BITS

4 A(W1-W4)|

i-‘

INTERRUPT

' ENABLE
SWITCH

’

INTERRUPT
|

EXT%?NAL

INTERRUPT
GONTROL

DATA ACCEPTED

1-2860

Figure 5-1 Representative Input Line Biock Diagra»m‘
5.1.2

Input Definition Selection

The input definition of lines 15 through 12 can be further selected to be set by a posmve trans1t1on, a negative

transition, or either a positive or a negative transition. These options are controlled byjumpers W1 through W4, as
Table 5-2 indicates. The module is normally shipped W1th these jjumpers configured for a negatwe trans1t1on (+3 V to
|

ground).

Table 5-2

Input Lines 15: _12 Jumper Configuration

Negative Input

wi-A

W3-A

w2-A

W4-A

)

'POSitive' I‘nput' B

Positive or Negative Input

WILB

- WIC

- W2-B

W3-B

w4B

- W2-C

- W3-C
W4C

standard

5.1.3

Jfflfi\

Input Line

Interrupt Enable Selection

Each bit in the buffer register can be selected to generate an 1nterrupt to the Unibus. This selectlonis controlled by

microswitches on the module. Table 5-3 indicates which switch enables each bit to generate an interrupt.

5.1.4 Device Selection Addrésses

The DR11-K requires three device selection addresses, for the input, output, and status reg1sters These addresses are
selectable by microswitches marked on the M7843 module as A12 through A3. Table 5-4 indicates the selectable

address bits and the associated switches. The moduleis normally shipped with these bits configured for an address of
16777x. The least significant octal digit is software-controlled by bits A02, AO1, and A00O, and is always O for the
status register address, 2 for the input address, and 4 for the output address. A switch OFF= logical 1, and a switch

= logical 0.
ON

5-2

Table 5-3

Interrupt Enable Switch Chart

Input Register Bit

15
14

Switch

S1-4
S1-1
S1-3

S1-2

S1-6

S1-5

S2-5

S2-6

S1-7

S1-8

S2-8

S2-7

S2-1

S2-2

S2-4

S2-3

Table 5-4

Dei?ice Selection Address Lines
UNIBUS ADDRESS LINES

A15|A14 |A13 | A12| A11]| A10| A09 | A0S | AO7 |AO6 | AO5 | AO4 |AO3 | AO2 | AOT |A0O
Bits Which

lare Selectable
Module Standard

Configuration

Switch ID

| X

‘

|X
-

ON | OFF| OFF| OFF| OFF| OFF |OFF| OFF| OFF |OFF

93.21S3-3| $4-3| S4-8| $4-4 | $4-5 | S4-7| S4-6 | $4-2 | $4-1

5.1.5 Vector Address Selection

The DR11-K requires two vector addresses, one for the data input vector and the other for the data output vector.

The two most significant octal digits of these addresses are controlled by microswitches marked on the module as V8

through V3, which correspond to bits D8 through D3. Table 5-5 shows the selectable bits and the standard

configuration in which the module is usually shipped, which selects a vector address of 30x. (A switch ON = a logical
1, and a switch OFF = a logical 0.) The least significant octal digit of the vector address is hardware-controlled by bit

D2, so that the standard input vector address is 300 and the standard output vector address is 304.

5-3

Table 5-5

Vector Address Selection Lines

UNIBUS DATA LINES

D15|D14|D13|D12|D11{ D10 DO9 D08 |D07 | D06 | D05 |D04 | DO3 | D02 | DO1 | DOO
Bits Which

are Selectable

Module Standard

Configuration

OFF| ON | ON | OFF| OFF| OFF

Switch ID

$3-8| $3-7| $3-1] $3-5| $3-4| $3-6

5.1.6 Control Line Polarity Selection
The DRI11-K output control lines (INTERNAL DATA ACCEPTED, INTERNAL HIGH DATA READY, and
INTERNAL LOW DATA READY) are generated by one-shot delays normally configured for an output of 1 us

(circuit schematic D-CS-M7843-0-1, sheet D7). By increasing the resistance for each one-shot, it is possible to

increase the output time of the signal up to 5 us (Figure 5-2) for user applications in which long cabling and the
resultmg capacitance necessitate added delay. Itis possible to select the polarity of the control signals by solder-type
jumpers, according to Table 5-6.
b S€C
5

APPROXIMATE CURVE
(Cx =330PF)

-3

10K

20K

MIN

30K

[

40K

50K

;

MAX

— > RESISTANCE
11-2876

| Fi'gur‘eVS-Zh Control Line Output Time Variation (R118, R120, and R121)
Table 5-6
Control Line Polarity Selection

Jumper Selection
-

INT DATA

INT HIGH

. INT LOW

DATA READY

Positive

W23-B

‘W21-B

W22-B

Negative

W23-A

W21-A

W22-A

Output fl

Output —l_'—

Standard

5.4

Standard

5.1.7

Coulter Model “S” Selection

‘To use the DR11-K as an interface to the Coulter Model “S”, the four most significant bits are set up for
~ interrupting on an input change, and all lines are configured for direct line input. Table 5-7 shows this configuration.

Table 5-7

/—s\\‘

Coulter Model “S” Input Configuratron
‘Data

Jumpers for Data

Interrupt Enable

Jumper for Input

Line

R Input Paths S

Switch

Buffer Setting Edge

ws B

"~ S1-40N

W1-C

W6-B

S1-1 ON

W2-C

'S1-30N
S1-20N

W3-C
- W4-C

W11-B

~ S1-6 OFF
S1-5 OFF
- S2-5 OFF

Wi3-B

‘S1-70FF

06
05

Wi4-B
Wi15B

S1-8 OFF ~ S2-8 OFF

—
—

S82-70FF

—

13
12

- W7-B
W8-B

11
10

W9-B
"W10-B

Wi12B

03
.02

01
00

S2-6 OFF

‘Wi16-B

.
.

—

WI17-B

$2-1 OFF

WIi8B.

.S8220FF |

W19-B
W20B

- S24 OFF
$2-3 OFF

~
-

MAINTENANCE AND CHECKOUT

Checkout and testing areaccomphshed by usmg the maintenance cable supplied with each DR11-K interface. That
- cable (a one-foot BCO8-R cable)is connected to both of the 40-pin H854 connectors as shownin Figure 5-3, so that

the output lines of the DR11-K are jumpered to its input lines, and any 16-bit word loaded into the output register
is fed back into the input register. If the word read.is identical to that loaded the input buffer, output buffer, and
associated circuits may be presumed to be operatmg properly

Installat1on testmg may be performed by runmng DRll-K D1g1ta1 I/0 Test (MAINDEC-11-DZDRG). If performance
of this test fails to dlsclose any errors it may be assumed that the DR11-K is operational, and that it has been

correctly installed.

5.5

vwm.

Shinae
ST

S
T

i
RNt

5-6

oo
2

;

CHAPTER
6

DR11-K EXAMPLES

6.1 INTRODUCTION

This chapter contains examples of some of the applications er,Which the DR11-K can be adapted.
-

6.2 INPUT EXAMPLES

~ The paragraphs below include examples of possible configuratidns that use the DR11-K. Paragraph 6.4 discusses in
more detail a specific input application.

6.2..1 Input Example 1
An external device with 15-bit binary output and two control lines. When the device has
placed data on the data lines, it generates a signal on one of the control lines and holds
the data on the data lines until it receives a data acknowledgment on the other control

Application:

line.

Because the external device has only a 15-bit output and the DR11-K has a 16-bit input,

Solution:

the sixteenth bit is left unconnected, and is disabled by internal clamping circuitry so that

it reads as a logical 0 to the software. The data input of the DR11-K should be set for |
of holding data on the data
direct line input (Table 5-1), as the external device is capable
|

lines (Figure 6-1).

6.2.2 Input Example 2
Application:

Solution:

An external device with 16-bit binary output and two control lines; the data is strobed

onto the device output lines. Because the data is strobed onto the data lines, some type of
holding register is needed. When the data has been strobed onto the lines, a signal is
- generated on one of the control lines, after which the external device waits for a data
acknowledgment on the other control line before strobing new data onto the data lines.

~ The bits of the DR11-K input buffer register are edge-triggered, so that the data on the

data line will set each register bit on a negative transition (+3 V to ground) and will be

~ held until the software clears the register. The data input of the DR11-K should be set up
for a register input (Tables 5-1 and 5-2). Figure 6-2 shows this example graphically.

6-1

|
USER
DEVICE|DATA ON LINE

DR11-K

EXT

DATA ACKNOWLEDGE _ _ INTERNAL DATA'I
"~

ACCEPTED

11-2870

Figure 6-1 Block Diagram of Input Example 1

'USER

DEVICE

|DATA SENT _ EXTDATA READY | DRII-K
ATA ACKNOWLEDGE _INT DATA
~ ACCEPT

|
11-2871

Figure 6-2

Block Diagram of Input Example 2

6.2.3 Input Example
3

Application:

Three devices, each connected to a DR11-K as in Example 1, and each with three
pushbutton switches, s1gn1fy1ng
Test Start
Test Stop

New Segment of Data Control

User software is such that it needs to be kept aware of these control functions. Signals
produced by the switches are TTL-compatlble and are avallable off a separate connector

on the back of each device.

Solution:
|

~In this example, the input lines are used to generate interrupts (Figure 6-3). The input
~ jumpers (Table 5-1) should be set for a register input, so that the software can read the
interrupting bits. Each interrupt enable switch is turned ON, allowing any input bit to
generate an interrupt.

6.3

OUTPUT EXAMPLES

6.3.1

Output Example
1

Application:

Solution:
.

Transferring data between two PDP-11s via DR11-Ks.

The DRI1 lK is designed so that the output lines of one DR11-K can communicate to the
input lines of another and vice versa (Figure 6-4).

6-2

DATA

—

DEVICE

CONTROL FUNCTIONS >
|

DATA

DEVICE
#2

URANEL

DISTRIBUTION|

__DATAINPUT > DRN-K #4
A

CONTROL FUNCTIONS

Aih oos >

DATA

DEVICE

# 3

CONTROL FUNCTIONS >
‘

—

11-2869

@ _

- Figure 6-3 Block Diagram of Input Example 3

OUTPUT>--INPUT

DR11-K

DRII K

_INPUT

2" ouTPUT
>

)

1-2867

Figure 6-4 Blcck Diagram of Outpu’t Example -1 |
-

6.3.2

Output Example 2

Applicatilon':
Solution:

- Transferring data to two 8-bit d'evices°
The output of the DR11-K can be byte-separated to transfer data to two 8-bit devices
(Figure 6-5).

6..4 COULTER MODEL “S” BLOOD COUNTER INTERFACING
- The dual transitional characteristic of input bits 15 through 12 was designed specifically for interfacing with a
Coulter Model “S” Blood Counter. This interfacing provrdes a good example of the combined use of the input lines
for data inputting and interrupting.

6-3

INT DATA READY HIGH BYTEi ' ~

DEVICE
. # 1

EXT DATA ACCEPT

DR11=K

USER

EXT DATA ACCEPT

AR
.
INT DATA READY LOW BYTE

DEVICE
o

H-EEGB

Figure 6-5 Block Diagram O'f Output Example 2

The Coulter Model “S” has sixteen data output lines, twelve of which are designated as S lines (S12:801) and

provide a 3-digit BCD value for reporting test data. The remaining four lines are designated as Q lines (Q4:Q1), and
provide a BCD digit that indicates the test number corresponding to the data currently being reported on the S lines.
To transfer data to the PDP-11 from the Coulter Model “S” via the DR11-K, an interrupt must be generated when
new data is ready on the S lines. The Model “S” does not have a signal line specifying that data is ready; because the
Q lines is used
Q lines indicate the test number and change when new data is available on theS lines, a change on the
of data on
loading
the
and
lines
Q
the
on
change
the
between
difference
time
no
is
There
to generate the interrupt.
the S lines; therefore, the software must allow sufficient delay to permit the S lines to settle.

To accomplish this, input bits 15:12 are selected for positivé/negative trigger, so that any transition of the lines

generates an interrupt. All sixteen data inputs are selected for direct line input (Table 5-7). Figure 6-6 shows the
input characteristics for this application. The BC11-M option is a cable used to connect a DR11-K to a Coulter.

A change on any of the Q lines signifies that there is a test number change in process. The DR11-K then monitors

the lines for a change and interrupts the processor when it occurs. The software must allow time for the Coulter data
lines to settle. The following program example shows how the software reads data from the Coulter.
VECTOR ADDRESS,

COULTER

| BR COULTER

/Coulter interrupf has occurred.

MOV Input, Memory

/Store the data on the DR11-K input.

/Go to 50-ms delay subroutine and return.

JSR PC DELAY

[Clear the interrupts (Bits 15:12).
/Set up interrupt enable for next input interrupt.

MOV #170000 Input
MOV #040000 Status
RTI

MogEL

-Q4

/Restore program.

1512

COUNTER @ - @--- {DATA BUS
L
J si-siz
Figure 6-6

~ T 00-11

11-2866

Block Diagram of DR11-K/Coulter Interface
6-4

DR11-K INTERFACE USER’S GUIDE

AND MAINTENANCE MANUAL

EK-DR11K-MM-001

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