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Document:	DR11-C General Device Interface User's Manual
Order Number:	EK-DR11C-OP
Revision:	001
Pages:	34
Original Filename:

OCR Text

DR11-C
general device interface
user’'s manual

EA36020

EK-DR11C-OP-001

DR11-C

general device interface
user’'s manual

digital equipment corporation - maynard, m assachusetts

1st Edition, September 1976

Copyright © 1976 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this

manual.
Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000

computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

DECtape

DECCOMM

DECUS

PDP
RSTS

DECsystem-10

DIGITAL

TYPESET-8

DECSYSTEM-20

MASSBUS

TYPESET-11
UNIBUS

CONTENTS
Page

CHAPTER 1

INTRODUCTION

1.3

s e e e
e e e e e e s e e e e e e
INTRODUCTION . . . . o o
GENERAL DESCRIPTION . . . . . . . o e e e e e e e e e e
e
oo i et e e
PHYSICAL DESCRIPTION . . . . . . . .

CHAPTER 2

SOFTWARE INTERFACE

1.1
1.2

2.1

SCOPE

. . . . . @

i e

i i i i

e [

2-2
2-2
2-2
2-2

3-1
3-3
3-3

2.5

CHAPTER 3

USER INPUT/OUTPUT SIGNALS

3.1
3.3

e
e e e e e e e e e e e e e
e
SIGNAL LIST . . . . o o
e
e e e e e e e e e e e
. . . . .
VARIABLE SIGNALS
e e e e e e e e s e e
e
e
. . . .
CONNECTORS

CHAPTER 4

DR11-C APPLICATIONS

4.1

4.4

e
. . . . . .
BASIC INTERFACE
. .
INTERRUPT SERVICED INTERFACE
.
LEVELS
LINE
REQUEST
GENERATING
.
.
.
.
.
.
.
INTERPROCESSOR BUFFER

APPENDIX A

USE OF BB11

2.3

2.4

3.2

4.2

4.3

2-1

e e e e
... .. e
. .. ... ... ... ..
. . . . .. ... .. ...
. . ... ... . ... ..

. ...
INPUT BUFFER REGISTER (DRINBUF)
. .
(DROUTBUF)
REGISTER
OUTPUT BUFFER
CONTROL AND STATUS REGISTER(DRCSR) .
. . .
ADDRESS AND VECTOR ASSIGNMENTS

2.2

1-1
1-1
1-2

e
e e e et e e e e
. . . . .. . ... ... ....
. . . . .. ... ... .. ...
..
.
. . . .

4-1
4-2
4-2
4-2

ILLUSTRATIONS
Figure No.
1-1
1-2

2-1
3-1
3-2

4-1
4-

43
4-4

Title

System Block Diagram
. . . . . . . . .. ..o oo
Typical M7860 Quad Module Mountingin a DD11-A . . . .. .. ... ...
. o oo
DR11-C Register Assignments . . . . . . . . . .«
M7860 Module Interconnect Diagram When the Optional
. . . . . . . . . . ..o
M971 Connectorsare used
Berg Connector
. . . . . . . . ...
e
e e e e e
Basic Interface . . . . . . . . . . .
e e e e e e e e e
e
.00
...
..
.
.
.
.
.
.
.
.
Interface
Serviced
Interrupt
Request Line Control Logic . . . . . . . . . . . ... ... ...
Interprocessor Buffer, Simplified Diagram
. . . . . . . . . .. .. .. ...

ii1

Page

1-1
1-3
2-1
|

3-4
3-5
4-1
4-3
4-4
4-4

- TABLES

Title

Table No.

Page

1-1

DR11-C Specifications

2-1

Standard DR11-C Register Asmgnments

2-2

DRCSR Bit Assignments

2-3

Address AsSignments

3-1

User Input Signals

3-2

User Output Signals

. . . . . . . . . . . .

. e

1-4

e e e e e e e e e e

2-1

. . . . . . . ... ...

o e

. . . ... e e e

. . . . . . . . . . .

e e e e

. .,

. . . . . .. ... .. ... e e e

e e e e

3-3

External Capacitor Values

. . . . . . . . . . .. .. .. ... ... ...

Input and Output Signals

. . . . . . . . . . . . ...

3-5

Pin Connections

. . . .

e e

oL,
e

3-1
3-2

3-3

.. .. e

2-4

e e e

3-4

. . .. .

2-3

3-6
3-6

CHAPTER
1

INTRODUCTION

1.1

INTRODUCTION

The DR11-C is a general-purpose interface between the PDP-11 Unibus and a user’s peripheral (Figure 1-1). The
DR11-C provides the logic and buffer register necessary for program-controlled parallel transfers of 16-bit data

between a PDP-11 System and an external device. The interface also includes status and control bits that may be
controlled by either the program or the external device for command, monitoring, and interrupt functions. The

DR11-C is software compatible with the DR11-A.

4/}
CONTROL

DATA

PDP-11

SYSTEM

u
N
|

is|

ADDRESS

SELECTION

COMMAND

INTERRUPT CONTROL

DATA

OR11-C

CONTROL

]
| 16-BIT
DATA

]

—

USER's

|
|

psERs

S—

|
It-1048

Figure 1-1

1.2

—

INTERRUPT REQUESTS |

System Block Diagram

GENERAL DESCRIPTION

The DR11-C interface Consists of three functional sections: address selection logic, interrupt control logic, and
device interface logic.

The address selection logic determines if the interface has been selected for use, which register is to be used, if a

word or byte operation is to be performed, and what type of transfer (input or output) is to be performed.
The interrupt control logic permits the interface to gain bus control and perform program interrupts to specific
vector addresses. The interrupt enable bits are under program control; the interrupt bits are under control of the

user’s device.
The DR11-C interface logic consists of three registers:

control and status, input buffer, and output buffer. Oper-

ation is initialized under program control by addressing the DR11-C to specify the register and the type of operation to be performed.

I-1

If an output operation is specified, information from the Unibus is stored in a 16-bit register. Once this register
has been loaded under program control (e.g., MOV RO, OUTBUF), the outputs are available to the device until

the register is loaded with new data from the bus. The register can also be read onto the bus. Upon transfer of

data to the buffer register, NEW DATA READY control signals are supplied to indicate to the user’s device that
data has been loaded by means of a DATO or DATOB bus cycle and is read by means of a DATI or DATIP bus

cycle.

When an input operation is specified, the DR11-C provides 16 lines of input to Unibus transmitters. This permits
data from the user’s device to be read onto the bus. A control signal, DATA TRANSMITTED, informs the device that the input lines have been read. The input lines, which are not buffered, can be read by a DATI bus cycle
(e.g., MOV INBUF, RO).

The control and status register provides six bits that can be used to control and monitor user functions. Two of

these bits are interrupt enable (INT ENB) bits under control of the program. Two bits (REQ A and B) are under
direct control of the user’s device and can only be read by the program. These bits can be used either to initiate

interrupt requests or to provide flags that can be monitored by the program. The remaining two bits (CSRO and

CSR1) are read/write bits that can be controlled by the program to provide command or monitoring functions.
In the maintenance mode, they are also used to check operation of the interface.

A maintenance cable, which is supplied with the interface, permits checking of the DR11-C logic by loading the

input buffer from the output buffer rather than from the user’s device. Thus, a' word from the bus is loaded into
the output register and the same word appears when reading the input buffer, provided the interface is function-

ing properly.

The DR11-C can also be used as an interprocessor buffer (IPB) to allow two PDP-11 processors to transfer data
between each other. In this case, one DR11-C is connected to each processor bus and the two DR11-Cs are
cabled together, thereby permitting the two processors to communicate. A description of the DR11-C used as an
interprocessor buffer is provided in Chapter 4. DEC does not supply software for this configuration.
1.3

PHYSICAL DESCRIPTION

The DR11-C interface is packaged on a single M7860 quad module that can easily be plugged into either a small
peripheral slot in the processor or into one of the four slots in a DD11-A Peripheral Mounting Panel (Figure 1-2).
Appendix A shows the method of installing the DR11-C in a BB11 Blank Mounting Panel. Power is applied to
the logic through the power harness already provided in the BA11 mounting box. The required current is approximately 1.5A at +5V. No -15V power source is needed.

The M7860 module has two Berg connectors for all user input/output signals. Two M971 connector boards,

which are not supplied with each interface, can be used to bring all input/output lines to individual pins on a
back panel via two BCO8R cables. Note that this cable is a ‘““mirror image” rather than a straight one-to-one cable
(Figure 3-1).

Specifications for the basic DR11-C are given in Table 1-1. The DR11-C interface is available in the following
standard configuration:

one M7860 interface module

one BCO8R-1 maintenance cable

applicable documentation

The following accessories are available for interfacing and may be ordered separatély:
a.

BCOS8R (Berg-to-Berg) flat cable. Available in lengths of 1, 6, 8. 10, 12, 20, and 25 feet. When ordering, the dash number indicates the desired cable length; e.g., BCOSR-1 or BCO8R-25.

M971 connector board. A single-height by 8-1/2 in. board that brings the signals from one Berg connector to the module fingers.

H856 Berg connector. Includes an H856 Berg connector and 40 pins. Crimping tools are available

from: Berg Electronics, Inc., New Cumberland, Pa. 17070.

BUS
ouT
A

UNIBUS

(SEE NOTE 2)

POWER

RESERVED

'
B

- UNIBUS
(SEE
NOTE 3)
|

BUS
IN

//
///
//
W%
(NOTE”/
NOTE:

1. Can _be mounted in slot 1,2,3,0r4
2.Can be M920,BC11-A,or M930
3.Can be MS20 or BC11-A

1-1049

Figure 1-2

Typical M7860 Quad Module Mounting In a DD11-A

1-3

Table 1-1

DR11-C Specifications
Registers

Status and Control Register (DRCSR)
Output Buffer Register (DROUTBUF)
Input Buffer Register (DRINBUF)

DRCSR — 767770

Addresses

DROUTBUF — 767772

may be changed by user

DRINBUF — 767774
Interrupts

Priority = BR5 (may be changed by jumper plug)
Vector = 300, 304 (user selectable)

Types = REQUEST A, B (function defined by user)
Control and

Controlled by program = INT ENB A, B; CSR0, CSR1

Status Bits

Controlled by device = REQUEST A,B

Inputs

One standard TTL unit load; dicde protection clamps to ground and +5V

Outputs

TTL levels capable of driving 8 unit loads except for the following:
NEW DATA READY = 30 unit loads
DATA TRANSMITTED = 30 unit loads

INIT (initialize) = common signal on both connectors driven by one 30-unit
load driver

Signals

NEW DATA READY — drives 30 unit loads, _positive pulse, 400-ns wide unless
width changed by an external capacitor

DATA TRANSMITTED — drives 30 unit loads, positive pulse, 400-ns wide unless
width changed by an external capacitor

INIT (initialize) — common signal on both connectors driven by one 30-unit load
driver

" NEW DATA READY LO H — drives 30 unit loads, positive pulse, 400-ns wide
unless width is changed by an external capacitor (only on etch revision E or later)

NEW DATA READY HI H — drives 30 unif loads, positive pulse, 400-ns wide

unless width is changed by an external capacitor (only on etch revision E or later)

Data Inputs
Data Outputs

16-bit word from the external device

16-bit word from the Unibus. Either a full word or an 8-bit byte (either high or
low) may be loaded from the bus.

Maintenance

A MAINT cable (supplied with basic system) jumpers the DROUTBUF outputs

Mode

to the DRINBUF inputs and forces bits 15 and 07 to read as CSR1 and CSRO,
respectively.

Size
Mounting

Consists of a single quad module (M7860)

M7860 module occupies 1/4 of a DD11-A (or equivalent) or one of two controller
slotsin a KA11, KC11, or other PDP-11 processor system unit.

Power

~]1.5A @ +5V (derived from power supply in mounting box where DR11-C is installed)

1-4

CHAPTER 2

SOFTWARE INTERFACE

2.1

SCOPE

This chapter presents a detailed description of the three DR11-C registers (Figure 2-1).

These registers are as-

signed bus addresses and can be read or loaded (with the exceptions noted) using any instruction that refers to
their addresses. The mnemonic INIT refers to the initialization signal issued by the processor. Initialization is

caused by one of the following: issuing a programmed RESET instruction; depressing the START switch on the
processor console; or the occurrence of a power-up or power-down condition of a system power supply.

15
DRCSR
767770

REQ

CSR1

|CSRO

DROUTBUF
767772

OUTPUT

DATA

BUFFER

DRINBUF
767774

INPUT DATA BUFFER
11-1050

Figure 2-1

DRI11-C Register Assignments

The device registers and associated addresses are listed in Table 2-1. Note that these addresses can be changed by
altering the jumpers on the address selection logic. However, any programs or other software referring to these
addresses must also be modified accordingly if the jumpers are changed. Paragraph 2.5 discusses priority levels

and the addressing scheme when more than one DR11-C is used.
Table 2-1
Standard DR11-C Register Assignments

‘Mnemonic*

Address

Control and Status Register

DRCSR

767770

Output Buffer

DROUTBUF

767772

Input Buffer

DRINBUF

767774

* First two letters of mnemonic (DR) refer to DR11-C interface; the remaining letters represent the mnemonic of a specific register.

2-1

Paragraphs 2.2 through 2.4 describe operation of the DR11-C registers.

Note that unused bits are always read

as 0s. Loading unused or read-only bits has no effect on the bit position.

2.2

INPUT BUFFER REGISTER (DRINBUF)

The input buffer is a 16-bit read-only register that receives data from the user’s device for transmission to the Unibus. Information to be read is provided by the user’s device on the data IN signal lines. Because the input
buffer
consists of gating logic rather than a flip-flop register, the data IN lines must be held until read

onto the bus. The

register is read by a DATI sequence and the data is transmitted on the Unibus for transfer to the processor or
some other device. When the input lines are read during a DATI sequence, a pulsed signal (DATA TRANSMITTED) is sent to the user’s device to inform it that the transfer has been completed. The trailing edge
of the
positive-going pulse indicates that this transfer is completed.

Whenever the maintenance cable is used, the input buffer register receives data from the output buffer

rather than from the user’s device. This permits checking of the interface logic by loading a word from
the bus

into the output register and verifying that the same word appears in the input buffer.

2.3

OUTPUT BUFFER REGISTER (DROUTBUF)

The output buffer is a 16-bit read/write register that may be read or loaded from the Unibus. Information
from
the busis loaded into this register under program control. At the time of loading, pulsed signals (NEW
READY) are generated to inform the user’s device that the register has been loaded. The trailing

tive pulse should be used to allow the data to be loaded and settle on the user’s input lines.
is transmitted to the user’s device on the data OUT lines by means of a DATO or DATOB

DATA

edge of the posi-

Data from the buffer

bus cycle.

The contents of the output buffer register may be read at any time by means of a DATI or

DATIP bus cycle.

During the read operation, the output of the buffer is fed directly to the bus data lines.

Whenever the maintenance cable is used, the data from the output buffer is also applied to the

input buffer regis-

ter. This permits checking operation of the interface logic.

The DROUTBUEF is cleared by INIT.

2.4

CONTROL AND STATUS REGISTER (DRCSR)

The control and status register is used to enable interrupt logic and to provide user-defined

command and status

functions for the external device.
Two REQUEST bits, which are under device control, may be used to provide device status

indications, or may be

used to initiate interrupts when used with associated INT ENB (interrupt enable) bits which

are under program

control. Two other bits (CSRO and CSR1) are controlled from the Unibus and serve as command bits.
Although the REQUEST and CSR bits can be used for any function the user desires, standard
conventions attempt to allocate bit 15 for error conditions and bit 07 for ready indications

PDP-11

interface

and both of these bits

can generate interrupt requests. In addition, bit 00 is normally used for start or go commands.

Table 2-2 gives the bit assignments and provides a brief description of each bit in the control and status

2.5

ADDRESS AND VECTOR ASSIGNMENTS

The register address and vector address assignments are listed in Table 2-3. Note that four addresses
are allotted

for each DR11-C even though only three addresses are used.

2-2

Table 2-2

DRCSR Bit Assignments
Bit

Name

REQUEST B

Meaning and Operation

This bit is under control of the user’s device and may be used to initiate
an interrupt sequence or to generate a flag that may be tested by the
program.

When used as an interrupt request, it is set by the external device and initiates an interrupt provided the INT ENB B bit (bit 05) is also set.
When used as a flag, this bit can be read by the program to monitor external device status.

When the maintenance cable is used, the state of this bit is dependent on
the state of CSR1 (bit 01). This permits checking interface operation

by loading a 0 or 1 into CSR1 and then verifying that REQUEST B is
the same value.

Read-only bit. Cleared by INIT.
14-08
07

Unused

Not Applicable

REQUEST A

Performs the same function as REQUEST B (bit 15) except that an interrupt is generated only if INT ENB A (bit 06) is also set.

When the maintenance cable is used, the state of REQUEST A is identical to that of CSRO (bit 00).

Read-only bit. Cleared by INIT.
06

INT ENB A

Interrupt enable bit.

When set, allows an interrupt sequence to be ini-

tiated, provided REQUEST A (bit 07) becomes set.

Can be loaded or read by the program (read/write bit). Cleared by INIT.
05

INT ENB B

Interrupt enable bit.

When set, allows an interrupt sequence to be ini-

tiated, provided REQUEST B (bit 15) becomes set.

Can be loaded or read by the program (read/write bit). Cleared by INIT.
04—02

Unused

Not Applicable

CSR1

This bit can be loaded or read (under program control) from the Unibus
and can be used for a user-defined command to the device (appears only
on Connector No. 1).

When the maintenance cable is used, setting or clearing this bit causes
an identical state in bit 15 (REQUEST B). This permits checking operation of bit 15 which cannot be loaded by the program.

Read/write bit (can be loaded or read by the program). Cleared by INIT.
00

CSRO

Performs the same function as CSR1 (bit 01) but appears only on Connector No. 2.

When the maintenance cable is used, the state of this bit controls the
state of bit 07 (REQUEST A).

Read/write bit. Cleared by INIT.

2-3

Table 2-3
Address Assignments

No.of DR11-Cs

DR11-C No. 0

767776 — 767770

DR11-C No. 1

767766 — 767760

310, 314

767756 — 767750

320, 324

DR11-C No. 7

767706 — 767700

370, 374

DR11-C No. 15

767606 — 767600

470, 474

DR11-C No. 2

Vector Addresses
300, 304

The addresses in the above table were assigned assuming that the system contains only DR11-Cs and no DR11-As.
If DR11-A interfaces are present in the system, addresses must be assigned for them before assigning DR11-C addresses.

The DR11-C has floating vectors which are assigned in the following sequence:
a.

Starting at 300 and proceeding upward, assign all DC1 1s.

Then any extra KL11s called for (VT05, VT06, LC11).

Then any DP11s

Then any DM11s

~e.

Then any DN11s

Then any DM11-BBs

Then any DR11-As

Then any DR11-Cs

NOTE

Some devices use only one vector address.
The register address and vector address assignments are implemented by changing jumpers on the M7860 module.
The register address lines are jumpered for a O; the vector address lines are jumpered for a 1.

The priority level of both interrupts must be the same, with interrupt A (REQUEST A) on a higher sublevel than
interrupt B (REQUEST B). REQUEST A uses the vector block with the least significant octal digit equal to 0 and
REQUEST B uses the vector block with the least significant octal digit equal to 4 (i.e., REQUEST A using 430 and

REQUEST B using 434). The M7860 module contains a priority jumper plug which is normally set at the BRS level.

This priority level may be changed by changing the jumper plug. (Levels of BR4 through BR7 are available.)
Direct memory access (NPR request) is not possible with a DR11-C interface.

2-4

CHAPTER 3

USER INPUT/OUTPUT SIGNALS

3.1

SIGNAL LIST

Tables 3-1 and 3-2 list the signals available to the user’s device. Input loading refers to the number of TTL unit
loads the input signal must drive. A unit load is defined as:
2.4V < Input high voltage < 5.0V @ 40 pA
0.0V < Input low voltage < 0.4V @-1.6 mA

where current flow is defined as positive into the driven gate. All inputs are one standard TTL unit load and have
diode protection clamps to ground and +5V.

Table 3-1
User Input Signals

Name

No. of Signals

INOO through

| Loading
1 each

IN15

Description
Data input from user device. The levels presented on these

lines can be examined by reading the input buffer register
(DRINBUF) with an instruction such as MOV DRINBUF,
RO. This data is transferred to the Unibus when the
DR11-C responds to a DATI bus cycle.
Because the input buffer register consists of gating logic,
the device must hold the IN lines asserted until read onto

the Unibus. This is indicated by the trailing edge of the
DATA TRANSMITTED pulse.
Logic levels are: +3V=1;0V =0.

REQUEST A, B

I each

Two request lines that can be asserted (+3V) by the external device to initiate an interrupt sequence or to generate

a flag that can be tested by the program.
These request lines must be levels that are held asserted for
the entire interrupt sequence and would normally be

cleared by NEW DATA READY or DATA TRANSMITTED.
Although the external device controls these request lines,
an interrupt sequence can only be started by the program

because of the associated interrupt enable (IE) bits under
program control.

Methods of generating these request levels in the user’s device are described in Chapter 4,

Logic levels are: +3V =1;0V =0.

3-1

Table 3-2
User Output Signals

Name

No. of Signals | Driving Capability

OUTO0O0 through

Description

7 each

Data output to user’s device. These signals represent

OUTI15

the contents of the output buffer register

(DROUTBUF), which
is loaded under program control (e.g., MOV RO, DROUTBUF).

Logic levels are: +3V=1;0V =0.
All lines are cleared to 0 by INIT.

NEW DATA

This pulsed signal is generated when either byte of

READY

the DROUTBUF is loaded to indicate to the user’s
|

device that the buffer is loaded with data from the

Unibus. The signal is true (+3V) as soon as the
DROUTBUEF has been addressed for loading and
remains true for approximately 400 ns; therefore,

the trailing edge of this pulse should be used for
sampling the lines at the user’s end of the cable.

This duration can be changed as described in
Paragraph 3.2.

NEW DATA

This pulsed signal is only generated when the low

READY LO

byte of the DROUTBUF is loaded. The signal is
only available on M7860 modules of etch revision

E or later. Otherwise, the description for NEW
DATA READY applies.

NEW DATA.

This pulsed signal is only generated when the high

READY HI

byte of the DROUTBUF is loaded. The signal is
only available on M7860 modules of etch revision

E or later. Otherwise, the description for NEW
DATA READY applies.
DATA

This pulsed signal is generated when the DRINBUF

TRANSMITTED

‘register is read by a DATI sequence to inform the

user’s device that the transfer has been completed.

The signal is true (+3V) as soon as the DRINBUF has

been addressed for reading and remains true for approximately 400 ns; therefore, the lines should be
held until the trailing edge of this signal. This dura-

tion can be changed by the user as described in Paragraph 3.2.

CSRO, 1

7 each

Device status bits O and 1. The levels applied to these
lines appear as bits 00 and 01 in the control and status register (DRCSR).

These two lines can be loaded or read from the Unibus (under program control).

When the DR11-C is used as an interprocessor buffer, these bits are used for communication between
the two processors.
Logic levels are: +3V =1;0V=0.
|

INIT

Cleared by INIT.

30 (one driver for | This line is true (+3V) whenever the Unibus is initialthe signal on both | ized, which occurs during any one of the following

of the cables)

conditions: a programmed RESET instruction is issued, the console START switch is depressed, or a
power-up or power-down condition occurs.

3-2

All outputs are TTL levels capable of driving seven unit loads with the following exceptions:
NEW DATA READY — 30 unit loads

NEW DATA READY LO — 30 unit loads
NEW DATA READY HI — 30 unit loads
DATA TRANSMITTED - 30 unit loads
INIT — a common signal on both connectors which is driven by one 30-unit load driver
The NEW DATA READY and DATA TRANSMITTED signals are described more fully in Paragraph 3.2.

3.2

VARIABLE SIGNALS

The NEW DATA READY signals are positive pulses which load the output buffer register on the leading edge of
the pulse. The DATA TRANSMITTED signal is also a positive pulse and is generated when the input buffer reg-

ister is read by a DATI sequence.

Both of these signals are approximately 400 ns in duration. However, this duration can be changed by adding an
external capacitor between back panel pin EB1 and ground. Some typical capacitor values and resultant pulse

widths are listed in Table 3-3. The effect of the additional capacitance results in lengthening the bus-cycle. This
is, therefore, a factor in NPR latency considerations.

Table 3-3
External Capacitor Values

3.3

External Capacitof

NEW DATA READY

DATA TRANSMITTED

none

350 ns

470 pF

500 ns

600 ns

820 pF

600 ns

750 ns

450 ns

CONNECTORS

Figure 3-1 illustrates the layout for the M7860 module, the Berg connectors, and the M971 connector modules

referenced in Tables 3-4 and 3-5.

The input and output signals are listed in Table 34 and indicate the Berg pin on the M7860 module. Table 3-5
lists all pin connections (in pin number order) for the Berg header on the M7860 module, the Berg header on the
M971, and the M971 board pins. Figure 3-2 illustrates the physical location of the pins on the Berg connector.

3-3

3-4

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48008

VL6

1SO!-L}

11- 1650

Figure 3-2

Berg Connector

3-5

Table 3-4

Input and Output Signals

~ Inputs
Signal

Outputs

Connector

INOO

OuUTO00

INO1

OUTO1

Signal

Connector

INO2

OUTO02

INO3

OUTO03

INO4

OuUTO04

L
N

INOS

OUTO0S5

INO6

OUTO06

INO7

OuUTO07

INO8

OUTO08

INO9

\W%

OuUTO09

IN10

OUTI10

IN11

OUTI11

AA
BB

IN12

OUTI12

IN13

OUT13

IN14

OUTI4

IN15

OUT15

REQ A

NEW DATA RDY*

REQ B

\AY%

DATA TRANS.*

CSRO

CSR1

INIT

RR, NN

* Pulse signals, approximately 400-ns wide. Width can be changed by user.

Table 3-5
Pin Connections

M971

Board

M7860

Berg Header

PinConnect(;;ai(;. 2

M971

C(I)\?;itor No. 1 Pin

Berg Header

Board

OPEN

\A"

GND

OPEN

- Uu

INOO

OUTO00

GND

OPEN

INITH

NEW DATA RDY HI

GND

OPEN

INITH

NEW DATA RDY LO

GND

INOI

OuUTO01

INO4

OUT04

Cl1
|

GND

INOS5S

OuUTO05

OPEN

INITH

(continued on next page).’
3-6

Table 3-5 (Cont)
Pin Connections

Board | Berg Header
P1
N2
N1
M2
M1
L2
L1
K2
K1
J2
J1
H?2
H1
F2
F1
E2
El
D2
D1
C2

Cl
B2
Bl

A2
Al
A2
Al

M971

M7860

M971

R
S
T
U
\%
W
X
Y
Z
AA
BB
CC
DD
EE
FF
HH
JJ
KK
LL
MM
NN
PP
RR
- SS
TT
[8]8]
\'AY

CO;I::;OI No. 1 Pin

PinConnect(I)\;alr\In(;. 2
EE
DD
CC
BB
AA
Z
Y
X
\WY
\Y
U
T
S
R
P
N
M
L
K
J
H
F
E
D
C
B
A

INO6
GND
INO7
INO3
GND
INO8
INO9
GND
IN10
IN11
IN12
GND
REQ B
GND
IN13
IN14
IN15
GND
CSRO
GND
INO2
OPEN
OPEN
OPEN
DATA TRANS.
OPEN
OPEN

OUTO06
GND
ouTO07
OUTO03
GND
OouUTO08
OuUTO09
GND
OuUTI10
OUT11
OUT12
GND
CSR1
GND
OuUT13
OUT14
OUT15
GND
REQ A
GND
OuUTO02
GND
OPEN
GND
OPEN
GND
NEW DATA RDY

3-7

R
S
T
U
\%
W
X
Y
Z
AA
BB
CC
DD
EE
FF
HH
JJ
KK
LL
MM
NN
PP
RR
SS
TT
UU
VV

Berg Header

Board

EE
DD
CC
BB
AA
Z
Y

F2
H1
H2
J1
J2
K1
K2

H
F
E

T2
T1
T2

X
W
\%
U
T
S
R
P
N
M
L
K
J

L1
L2
M1
M2
N1
N2
Pl
P2
R1
R2
S1
S2
T1

D
C
B
A

Vi
U2
Ul
V2

CHAPTER 4

DR11-C APPLICATIONS

4.1

BASIC INTERFACE

Figure 4-1 illustrates a typical user’s device interface, consisting of a basic control section and a data assembly
register.

DR11-C OUTPUT SIGNALS
CSRO

: USER DEVICE LOGIC

: DR11-C INPUT SIGNALS

CSR1

FUNCTION

DATA TRANSMITTED

'DONE

NEW DATA RDY

}

l
|

DEVICE

CONTROL

ERROR

.
DATA OUT< 15:00>

LOADED

:"fi'agég

AN
1

DATA
ASSEMBLY

DATA

ROM

USER'S EQUIPMENT

Figure 4-1

REQUEST

> REQUEST A

N DATA IN<15:00>
.
,>

I
I
I

1-1082

Basic Interface

Operation of the interface is initiated by the GO level. The

FUNCTION bit informs the device whether it is to

perform a read or write operation. When data is ready for transfer to the Unibus or data is required from the
Unibus, a low-to-high transition on DATA REQUEST activates the REQUEST A line. The REQUEST A line initiates an interrupt sequence provided the INT ENB A bit in the DR11-C status register has been set. If the desired function is to load data into the user device, a LOADED (NEW DATA READY) pulse informs the device
control when the data is ready for transfer. If a write function has been selected, a DONE (DATA TRANSMITTED) pulse informs the device control when the DR11-C has completed strobing of the data. The ERROR

line becomes true if some type of error condition occurs in the device. This ERROR line (REQUEST B) can
either be monitored by the program or can be used to initiate an interrupt sequence (provided INT ENB B is set)

to cause the program to branch to an error handling routine.
With the signals available to the user, there are many possible variations to this basic interface. For example, the
two CSR bits (CSRO and CSR1) could provide a 2-bit code to select one of four operations to be performed by
the external device.

Another possibility would be to use one REQUEST line for interrupts and the other REQUEST line for a flag
(associated INT ENB not used) in order to inform the program of the desired operation to be performed on the
data.

A third possibility might be to use the two CSR bits as a selection code and have DONE (NEW DATA READY)
serve as a start command so that device operation begins as soon as the DR1 1-C output buffer has been loaded
from the bus.

4.2

INTERRUPT SERVICED INTERFACE

Figure 4-2 is an example of an interrupt serviced interface that employs a DR11-C to interface an analog-todigital converter (ADC) to the Unibus. This interface allows the processor to concurrently execute instructions
of another program while the ADC performs a cycle of operation. The processor responds to a READY (CONVERSION COMPLETE) signal from the ADC by interacting with the device and analyzing the data after it has
been collected. This interface eliminates the necessity of having the processor spend time testing for a ready
signal.

Note that this example uses only the REQUEST A line. The available REQUEST B line can be used as an ERROR
indicator, if desired, and the two CSR lines could be used to initiate other actions within the external device.

A similar, and more detailed, example of this type of interface is given in the PDP-11 Peripherals Handbook.
However, the example presented in this handbook uses a DR11-A which does not have all of the capabilities of
the DR11-C interface.

4.3

GENERATING REQUEST LINE LEVELS

Two request lines (REQUEST A, B) are furnished and may be asserted (+3V) by the user’s device to initiate an
interrupt sequence or to produce a flag that can be tested by the program. The request lines must be levels and

must remain asserted for the entire interrupt sequence. Typically, they are generated in the user’s device by a
REQUEST flip-flop which is set by the device when an interrupt is requested and cleared by the interrupt service routine by means of the NEW DATA READY or DATA TRANSMITTED signals.

Figure 4-3 represents the control circuit necessary to generate the REQUEST A H and REQUEST B H signals.
Similar logic could be used if it is desired to have CSR0O H and CSR1 H control the clearing of the REQUEST
lines.

4.4

INTERPROCESSOR BUFFER

Two DR11-C interfaces can be interconnected to allow data transfers and intercommunication between two
PDP-11 Systems. Figure 4-4 is a simplified diagram of this interconnection.

The two interconnecting cables are the same as the MAINT cable and may be procured in either 1-ft or 25-ft
lengths. Maximum allowable cable length is 25 ft.

4-2

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SET REQ A L
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{

[

]

REQUEST

CONN
No. 1

~-—-4
[AVAY)

:
1

]

DR-3 NEW DATA READY H

DR-3 REQUEST A H

DR11-C

INTERFACE

(M7860)

SET REQ B L

]

REQUEST
B

]

CONN
~-—-

DR-3 DATA TRANSMITTED H

DR-3

No. 2

I
]

REQUEST B H

L o eEzEp emp ommy emmd ey GRS J
11-1054

Figure 4-3

Request Line Control Logic

CONNECTOR No.1

U';'

DRI1-C

INTERFACE

—

DR11-C

H856 CABLE
—

INTERFACE

B
S

CONNECTOR No.
2

CONNECTOR No.2

CONNECTOR No.
1

No.2

No.1

I1-1055

Figure 4-4

Interprocessor Buffer, Simplified Diagram

The Connector No. 1 of the first DR11-C is connected to Connector No. 2 of the second DR11-C This causes all
of the output lines (OUTO00 — OUT15) of the first interface to be connected to the corresponding input lines
(INOO — IN15) of the second interface (refer to pin connections given in Table 3-5). The CSRO and CSR1 lines
of the first unit are connected to the REQ A and B lines, respectively, of the second unit.

Connector No. 2 of the first unit is connected to Connector No. 1 of the second unit. This connects the IN lines

and REQ lines of the first unit to the OUT lines and CSR lines of the second unit.
With the two PDP-11 buses interfaced in this manner, setting a CSR bit in one interface activates the REQ line in
the other interface to initiate an interrupt sequence. Data can then be loaded from the bus into the DROUTBUF

of the first unit for transfer to the DRINBUF of the second unit.

When DR11-Cs are used as interprocessor buffers, a power fail situation on either Unibus must be handled by
the software. The software routine would be entered from the power fail trap vector and, by use of the
REQUEST lines, would inform the other DR11-C that power is failing.

4-5

APPENDIX A
USE OF BB11

The BB11 Blank Mounting Panel is a prewired system unit designed for general interfacing. Figure B-1 illustrates
the method of mounting a DR11-C interface into a BB11 system unit, assuming that the BB11 has slot 1 wired
as a DD11-A or equivalent.

The first step is to mount the DR11-C in one of the four slots. Two of the remaining slots are used for the two
M971 Cable Connector modules. This leaves 12 double-height slots available for mounting user interface logic.

000000000000000

I %%%%

[= 7////.//////__
UUUUUU

MMMMMMMMMMMMMMM

Figure A-1

DRI11-C Mounted in BB11 System Unit

A-1

Reader’s Comments
DRI11-C GENERAL DEVICE

INTERFACE USER’S MANUAL

EK-DR11C-0OP-001

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