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Document:	QMA DPV11 Serial Synchronous Interface Technical Manual
Order Number:	EK-DPVQM-TM
Revision:	001
Pages:	108
Original Filename:

OCR Text

EK-DPVQM-TM-001

QMA DPV11
Serial Synchronous
Interface
Technical Manual

dlilglitiall}

EK-DPVQM-TM-001

QMA DPV11
Serial Synchronous
Interface
Technical Manudl

Prepared by Educational Services
of

Digital Equipment Corporation

Ist Edition, January 1984

The information in this document is subject to change without notice and should not be
construed as a commitment by Digital Equipment Corporation. Digital Equipment

Corporation assumes no responsibility for any errors that may appear in this document.

Printed in U.S.A.

This document was set on a DIGITALDECset Integrated Publishing System.

The following are trademarks of Digital Equipment Corporation:

nn Enm

DECUS

RSTS

DEC

DIBOL

DECmate
DECset
DECsystem-10
DECSYSTEM-20

MASSBUS
PDP
P/OS
Professional

UNIBUS
VAX
VMS
VT
Work Processor

11]9]1]L

DECwriter

Rainbow

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CONTENTS

Page

PREFACE

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CHAPTER 1

INTRODUCTION
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TR 1-1
QMA DPV11 GENERAL DESCRIPTION.......ootitiiiiiiiiieieeiciirrerreeeeeeeeeeeee
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QMA DPV11 OPERATION....ttt
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QMA DPVI11 FEATURES ...t
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GENERAL SPECIFICATIONS. ... . 1-2
Environmental SpecifiCations..............covviiiiiiiiiiiiiiiieiiiicieeicceeeeeeeeeeeeee 1-2
Electrical SpecifiCations ...........ccccvuviiiiiiiiiiiieeeiececceiree e 1-3
Bus Loading .........cooovemiiiiiiiiiiiiiiee
eeeeeeeeeeeeeeerreraa—————— 1-3
Performance Parameters.......ccovveiieeiiieieiiiiiieeeeee
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e eeenenes S 1-3
QMA DPV11 CONFIGURATIONS.... .o
e 1-3
EIA STANDARDS OVERVIEW (RS-449 vs RS-232-C).......ocoiiiiiiiiiicennnns 1-4

INSTALLATION

2.1

2.2
2.3
2.4
2.4.1
2.4.2
243
2.4.4
2.5

INTRODUCGTION .....cieecceeccceieieeeceeerreeeeeeeeseeeas e e e s e
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sanseennns 2-1
UNPACKING AND INSPECTION......oiiiiiiiirivenetraersrnnresnnsisnnsssnsssensssennes 2-1
PREINSTALLATION REQUIREMENTS ... evvevaasasaeaans 2-1
INSTALLATION ....ooooeiieiieieieetieeereeeeeteeerteeesteeeeraesssreasstessraessrereresessrrresrrerrrrsrersrranseees 2-7
[/O BUIKREAQ .....ceeveeieeeeeeeeeceeeeceeee
et ner e ee e e e e e e e e e seensans 2-7
Distribution Panel Installation.............ccooooiiiiiiiiiiii
e 2-8
Verification of Hardware Operation .........c.cccevvvveiiiiiiierieeeeriiccieeeeeeeeevieene
e 2-9
Connection to External Equipment/Link Testing.........c..cccooooooiiiiiiiiiiiiinnnnnn.. 2-10
TEST CONNECTORS ...t
e e e e 2-10

CHAPTER 3

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CHAPTER 2

INTRODUCTION........... FetesressstetsssessstresssEsssssesssEessststassestsntEARNERASNLLRnrEAnnnrrnntrrnnnsrrannes 3-1
QMA DPV11 REGISTERS AND DEVICE ADDRESSES ..., 3-1
REGISTER BIT ASSIGNMENTS.......o
o reerrteerrenerrrnerrsnnnrseanrranasesaanes 3-2
Receive Control and Status RegiSter........cccovieeiiiiiiiiiciicccc
s 3-2
Receive Data and Status Register ..........ccccvvvveevevevviieeveineerieeeneee, ceeevernnnrennraan—. 3-2
Parameter Control Sync/Address RegISter ...........uuvueeireeeeiiinriiineeineennreennnsannns 3-2
Parameter Control and Character Length Register ...........cccoovvveviiieiiiiiniinnnnnen.3-2
Transmit Data and Status Register ... 3-2
DATA TRANSFERS ...t
ae e e e e 3-19
RECEIVE DatA ...ccceviiieiiiiiieiiiie ettt
eser e s e s s e e sn s e e esaa e s e enneen 3-19
Transmit Data .........oooeeiiiiiiiiiiiiiieeeeeee eteeeeeerereeeereeeeeeeriaeeeernreeennnan 3-20
INTERRUPT VECTORS............ e eeeerteeesesersessesesestttentttantttantttatattttart———————————antatannas 3-21

i1l

CONTENTS (Cont)

CHAPTER 4

TECHNICAL DESCRIPTION

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Data Set Change Circuit
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CONTENTS (Cont)

CHAPTER §

MAINTENANCE

5.1
5.2
5.3
5.4
5.5
5.5.1
5.5.2
5.5.3
5.5.3.1
5.5.3.2
5.5.3.3

SCOPE. ...
as e e e e e e e e e e eeeeeeteeeas s e e s s raesssassasaesesassasenseeanes 5-1
TEST EQUIPMENT RECOMMENDED.........coooiiiicrceeeeeeee
e 5-1
MAINTENANCE PHILOSOPHY ....cotiiiiiiiiiieeeeeeeeeeeeeeett
e e ee e e s e e a e e 5-2
PREVENTIVE MAINTENANCE ...
s 5-2
CORRECTIVE MAINTENANCE .........cccee.c.......eeerreeeeeeereeeeeeeeerereera———————————————— 5-2
Maintenance MOAE.........coovviiieiiiiiiieeeeeeeeree e
e e e e e e e e e ser e eeeeeeesasanes 5-2
Loopback Connectors.............cc.......... e ereerertterareterararataatettereteteetetetieretienereerienens 5-2
DAAGNOSHICS...cciiiiiiiiiiiiiiciriicrr
et eer
s e se s s s s e e s e e e e e e e e eeeaaesasennstannsnnnennnneaeees 5-2
CVDPYV Functional DIagnostiC.......cccuvuueiiiirrieeieierierrriinseriieees sesnsvesersessssesseseens 5-3
DEC/X11 CXDPV ModUIE ...
e e 5-4
Data Communications Link Test CVCLH (DCLT) ..ccovvvrivviiiiiiieiiieeeeeeeennnnn.. 5-4

APPENDIX A

DIAGNOSTIC SUPERVISOR SUMMARY

A.l
A.2
A.3
A4
Ad.l
A4.2
A.5

INTRODUCGTION ...t
e e e e e s e e s s e b s e s eesssenssnnsananenas A-1
VERSIONS OF THE DIAGNOSTIC SUPERVISOR ........................................... A-1
LOADING AND RUNNING A SUPERVISOR DIAGNOSTIC ..., A-1
SUPERVISOR COMMAINDS ...ttt
ss e s e s s e e e e s s e e A-3
Command SWILtCHES......ccccoevriiiiiiiieiiiecceeeeeeeeeeeeeeeeeeee eerrenereeeeeeerrarra———— A-4
Control/Escape Characters Supported ...........ooovvuuiiieiiiieiiiiiiiceeeeeeeeeeeevvennaees A-4
THE SETUP UTILITY ..ottt
ee e s e s e s e e e e s s e seeeas A-5

APPENDIX B

USYNRT DESCRIPTION

APPENDIX C

QMA DPV11 OPTIONS AND CABINET KITS

APPENDIX D

PROGRAMMING EXAMPLES

GLOSSARY

FIGURES
Figure No.
1-1
2-1
2-2
2-3
2-4
2-5
2-6
3-1
3-2

Title

Page

QMA DPVI11 System.................... vensesarrseartessteseesitantesntatennsteerasnnrarennrrasnressrresessestrseane 1-1
QMA DPV11 Jumper LOCAtiOnS.........cciieeiieiiiiiieiiiiiieiieieeeeriianiveseressssseaeeaeeeesesananns 2-4
I/O Bulkhead in @ PDP-11/23 System .......cccoeiiiiiiiiiiiiiiieieeiieersseeeee
e e e e eeeeees 2-8
Distribution Panel Installation ............uueiiiiiiiiiiiiiiiiiiccceceeee
e
e eenaaae 2-9
H3259 Turnaround Test COonNECLOr ..........cuvieiiiieiiiiriceeeeeiceeeeeeeeeee e eeeneeeseanens 2-11
RS-423-A with H3259 Test COnnecCtor ..........covveiiiiiieieeeeeeeiiecee
e
2-13
H3260 On-Board Test CONNECLOT .........uuieeiiiiieiiieiiceeeeeeeeeeeverceeeeeee
e eeerraaeeeeeeens 2-14
QMA DPV11 Register Configurations and Bit Assignments...........c...cccecevvvevvvvennnn. 3-3
Receive Control and Status Register (RXCSR) Format.........ccoeevvveeciviieiiieeeeeeeennn. 3-4

FIGURES (Cont)

Figure No.

Title

Page

Receive Data and Status Register (RDSR) Format .........ooeveeeeiveiieeeeeeeeeeeeeenven, 3-8
Parameter Control Syric/Address Register (PCSAR) Format........ooovevveveeeveveniin, 3-11
Parameter Control and Character Length Register (PCSCR) Format................... 3-13
Transmit Data and Status Register (TDSR) Format......coooooeeeooooeneiieeeeeeeeeeeeeeenn 3-17
QMA DPV11 Block Diagram.........cooocviiiiiiiiiiiiiiiiceee
e 4-2
Simplified Functional Diagram ............c..cccovvuiiiiiiiiiiiccieec
et
ee e 4-4
ReGIStEr DECOUE ...t
e e e e, 4-8
Timing for Read Operation..........cccocooiiiiiiiiiiiciiiiccee
e 4-9
Timing for Write OPeration.........cccciieciieeiiiiiiiieeeiieee ettt e e e e e 4-10
Typical XXDP+ Diagnostic Supervisor Memory Layout..........ccceeoevveeevovovnennnne.... A-2
Terminal Connection (Identification) Diagram (2112517-0-0 Variation).................. B-2
5025 Internal Register Bit Map (2112517-0-0 Variation).........cceoevveeeeeeeeeeveeernnnnnn.. B-3

TABLES

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olels
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B0 =t A
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Title

Page

CK-DPVI1 A* Cabinet KitS ....ccc.vvvrieeiiiiiiiiiiiiiiieeeieeeee
et ee e e eaveeees- 1-4
Configuration ShEet.........cccociiiiiiiiiiiiiiiece
e
e e s re e s s esnabaeeeens 2-1
Vector AdAress SeleCtiON.......coiieiiieiiiiieeeeeeeeeeeeeeee
et
e e ee e
2-5
Device Address SEleCtiOn .............ccoovieiiiiiiiiiiieee
e eeeeeeee e et e e e e e e e e e 2-6
Voltage REQUITEIMENLS .........ccoiiiiiiiiiiiiiiiiie
et 2-7
H3259 Test CONNECtiONS ........ccoeveeieiiiiiiiiiiiiiiiiiceeeceeeeeeeeeceeeeeeeeeee viveserbererrrons 2-12
QMA DPV11 REZISTEIS. ...tttSR 3-1
Receive Control and Status Register (RXCSR) Bit Assignments............ccccceeeennnnn. 3-5
Receive Data and Status Register (RDSR) Bit Assignments............cccceeeevvevmmueennnnn. 3-8

Parameter Control Sync/Address Register (PCSAR) Bit Assignments ................. 3-11
Parameter Control and Character Length Register (PCSCR) Bit Assignments..... 3-14
Transmit Data and Status Register (TDSR) Bit Assignments..........ccocccevvennnn.... 3-17
Register SEleCtion ........coieciiiiiiiriiiiiiiieiecrc
et e e e ee e eeree e ssnneeceseneenes 429
USYNRT ReEZISLEr SEIECT ... uuuiiiitcic ettt aneeeenes 4-9
Test Equipment Recommended ............cooooeiiiiiiiiiiii
e, 5-1
Field Upgrade OPtions .....cccoooiiiiiiiiiiiieiiiee et
eraree e e s e e e C-2
CK-DPV11-A Cabinet KitS.......ccooeeeeeiiiiiiiiiiiiiiiiiiiiiee
ee
e eeer——e
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C-2
Miscellaneous ........uvuieciiieeniiieeeiieree e, reeeeteeeniaeeeeranraeeetartraaeeaerrrannnes C-3

PREFACE

The Qualified Modular Assembly (QMA) DPV11 serial synchronous line interface module has been tested
and meets the requirements of the FCC and DEC Standard 103 that limit electromagnetic interference.
This manual has been written to satisfy the needs of Field Service and Educational Service training
personnel.

It contains the following categories of information:

General description including features, specifications, and configurations;

[nstallation;

Programming;

Technical description; and

Maintenance.

The manual also contains an appendix that includes diagnostic information and programming examples.
Chapters 1, 2, and 3 of this manual contain the same information as Chapters 1, 2, and 3 of the QM
A
DPVI1 User’s Guide. The QMA DPV11 Engineering drawings (MP00919) contain additional
information.

vii

CHAPTER 1
INTRODUCTION

1.1

SCOPE

This chapter contains introductory information about the QMA DPV11 interface module. It includes a
general description and a brief overview of the QMA DPV11 operation, features, general specifications,
and configurations.

1.2

QMA DPV11 GENERAL DESCRIPTION

The QMA DPV11 is a serial synchronous line interface for connecting an LSI-11 bus to a serial
synchronous modem that is compatible with EIA RS-232-C interface standards and EIA RS-423-A and
RS-422-A electrical standards. EIA RS-422-A compatibility is provided for use in local communications
only (timing and data leads only). The QMA DVP11 is intended for character-oriented protocols such as
BISYNC, byte count-oriented protocols such as DDCMP, or bit-oriented data communication protocols
such as SDLC. The QMA DPV11 does not provide automatic error generating and checking for BISYNC.
The QMA DPV11 consists of one double-height module and may be connected to an EIA RS-232-C
modem through a cabinet kit (CK-DPV11-A*). See Paragraph 1.6.

The QMA DVPI11 is a bus request device only and must rely on the system software for service. Interrupt
control logic generates requests for the transfer of data between the QMA DPV11 and the LSI-11 memory

by means of the LSI-11 bus.

TELEPHONE

opv11

el rs-232.c | LINE
BC22%¢ | MODEM

LSI -BUS

FCC DISTRIBUTION

PANEL ASSEMBLY
CPU

MEM

TK-10736

t This cable is not part of the option. See Paragraph 1.6.

Figure 1-1

QMA DPV11 System

1-1

1.3 QMA DPV11 OPERATION
The QMA DVPI1 is a double-buffered program interrupt interface that provides parallel-to-serial conversion of data to be transmitted and serial-to-parallel conversion of received data. It can operate at speeds up
to 56K bits/s.* The QMA DPV11 has five 16 bit registers, which can be accessed in word or byte mode.
These registers are assigned a block of four contiguous LSI-11 bus word addresses that start on a boundary

with the low-order three bits being zeros. This block of addresses is jumper-selectable and may be located
anywhere between 160000g and 177776g. Two of these registers share the same address. One is accessed
during a read from the address, the other during a write to the address. For a detailed description of each
of the five registers, refer to Chapter 3. These registers are used for status and control information as well
as data buffers for both the transmitter and receiver portions of the QMA DPV11.

1.4 QMA DPV11 FEATURES
Features of the QMA DPV11 include:

Full-duplex or half-duplex operation;

Double-buffered transmitter and receiver;

EIA RS-232-C compatibility;

All EIA RS-449 Category I modem control;

Partial Category II modem control to include incoming call, test mode, remote loopback, and

local loopback;

Program interrupt on transitions of modem control signals;

Operationg speeds up to 56K bits/s (may be limited by software or CPU memory);

Software-selectable diagnostic loopback;

Operation with bit-, byte-count, or character-oriented protocols;

Internal cyclic redundancy check (CRC) generation and checking (not usable with BISYNC);

Internal bit-stuff and detection with bit-oriented protocols;

Programmable sync character, sync insertion, and sync stripping with byte count-oriented

protocols; and
®

Recognition of secondary station address with bit-oriented protocols.

1.5 GENERAL SPECIFICATIONS
Environmental, electrical, and performance specifications for the QMA DPVI11 are included in the
following paragraphs.
1.5.1
Environmental Specifications
The QMA DPVI11 is designed to operate in a Class C environment according to DEC Standard 102

(Extended).

Operating temperature range — 5° to 60°C (41° to 140°F)

Relative humidity — 10 to 90% with a maximum wet bulb temperature of 28°C (82°F) and a

minimum dew point of 2°C (36°F)

The actual speed realized may be significantly less because of limitations imposed by the software and/or CPU memory
refresh.

1-2

Electrical Specifications

1.5.2

The QMA DPV11 requires the following voltages from the LSI-11 bus for proper operation.
+12V at 0.30 A maximum (0.15 A typical)
45Vatl.2 A maximum (0.92 A typical)

e
e

The interface includes a charge pump to generate a negative voltage required to power the RS-423-A

drivers.

Bus Loading - The QMA DPV11 presents one (1) ac load and one (1) dc load to the LSI-11 bus.

1.5.2.1

Performance Parameters

1.5.3

Performance parameters for the QMA DPV11 are listed as follows.
Operating Mode:

Full- or half-duplex

Data Format:

Synchronous DDCMP, SDLC, and BI-SYNC

Program selectable (5-8 bits with character-oriented pro-

Character Size:

tocols and 1-8 bits with bit-oriented protocols)

Maximum Configuration:

16 DPV11 modules for each LSI-11 bus

Maximum Distance:

15.24 m (50 ft) for RS-232-C; 60.96 m (200 ft) for RS-

423-A and RS-422-A. Distance depends directly on
speed, and 60.96 m (200 ft) is a suggested average. (See
the RS-449 specification for details.)

Maximum Serial Data

Rates:

56K bits/s (may be less because of software and memory

refresh limitations).

1.6 QMA DPV11 CONFIGURATIONS
There are two QMA DPV11 configurations, the M and AP.

DPVI11-M is an unbundled version consisting of:

MB8020 module, and
Documentation.

DPVI11-AP is a bundled version consisting of:
—

—~
—~

M8020 module,
H3259 turnaround connector,

CK-DPV11-A* Cabinet Kit (See Table 1-1),
User Manual (EK-DPVQM-UG-001), and
Field Maintenance Print Set (MP00919).

Turnaround connectors, cables, and documentation may be purchased separately. The following cables are
available but are not part of the option:

BC22D - FCC compliant null modem cable for EIA applications. Female connections on both

ends.

1-3

BC22E - FCC compliant extension cable for limited modem control. Male connection on one
end and female connection on the other end.

BC22F - FCC compliant extension cable for full modem control. Male connection on one end
and female connection on the other end.

1.7 EIA STANDARDS OVERVIEW (RS-449 VS RS-232-0)
The most common interface standard used in recent years has been the RS-232-C. It does, however, have
serious limitations for use in modern data communication systems; the most critical is speed and distance.

For this reason, the RS-449 standard has been developed to replace RS-232-C. It maintains a degree of
compatibility with RS-232-C to accommodate an upward transition to RS-449.

The most significant difference between RS-449 and RS-232-C is the electrical characteristics of signals
used between the Data Communication Equipment (DCE) and the Data Terminal Equipment (DTE). The
RS-232-C standard uses only unbalanced circuits and the RS-449 uses both balanced and unbalanced
electrical circuits. The specifications for the types of electrical circuits supported by RS-449 are contained
in EIA standards RS-422-A for balanced circuits and RS-423-A for unbalanced circuits. These new
standards permit greater transmission speed and allow greater distance between DTE and DCE. The
maximum transmission speeds supported by RS-422-A and RS-423-A circuits vary with cable length; the
normal speed limits are 20K bits/s for RS-423-A at 60.96 m (200 ft) and 2M bits/s for RS-422-A at
60.96 m(200 ft).
Another major difference between RS-232-C and RS-449 is that additional leads are needed to support
the balanced interface circuits and some new circuit functions. Two new connectors have been specified to
accommodate these new leads. One connector is a 37-pin CinchTM that accommodates the majority of data
communication applications. The other is a 9-inch CinchTM used in applications requiring secondary
channel functions. Some of the new circuits added in RS-449 support local and remote loopback testing
and standby channel selection.

Table 1-1

CK-DPV11-A* Cabinet Kits

Kit Number

Application

CPU

Contents

CK-DPV11-AA

EIA Compliant

PDP-11/23-S

21-inch cable, 7018209 panel assembly,
and H3259 test connector

CK-DPV11-AB

EIA Compliant

MICRO 11

12-inch cable, 7018209 panel assembly,
and H3259 test connector

CK-DPV11-AC

EIA Compliant

PDP-11/23+

30-inch cable, 7018209 panel assembly,
and H3259 test connector

CK-DPV11-A3

EIA Non-Compliant

Five
|

9007031-00

cable

ties,

five

9008264-00 cable mounts, one BCO3L-

2F cable, and one H3259 test connector

CinchTM is a trademark of TRW, Inc.

1-4

CHAPTER 2
INSTALLATION

2.1

INTRODUCTION

This chapter provides all the necessary information for the installation and checkout of the QMA DPV11
interface module. Included are instructions for unpacking and inspection, preinstallation, installation, and
verification of operation.

2.2 UNPACKING AND INSPECTION
The QMA DPV11 interface module is packaged in accordance with commercial packing practices. First
remove all packing material and verify that the following are present.
M8020 module
H3259 turnaround connector

CK-DPV11-A* Cabinet Kit (asterisk is kit variation)
User Manual (EK-DPVQM-UG-001)
Field Maintenance Print Set (MP00919)

Inspect all parts carefully for cracks, loose components, and other obvious damage. Report damages or
shortages to the shipper immediately, and notify the DIGITAL representative.

2.3 PREINSTALLATION REQUIREMENTS
Table 2-1 (Configuration Sheet) provides a convenient reference for configuring jumpers.

Table 2-1

Configuration Sheet

(W1-W2) Driver Attenuation Jumper
Normal*

Alternate*

Driver

Configuration

Option

Description

Terminal
Timing

W1 to W2

Not connected

Bypasses
attenuation
resistor.
Jumper must be removed for certain modems to operate properly.

(W3-W11) Interface Selection Jumpers

Input

Normal*

Signals

Configuration

SQ/TTM

W5 to W6

(PCSCR-5)

DM (DSR)

Not connected

Alternate*

Option

Description
Signal quality

W7 to W6

Test mode

W10 to W9

Data mode return for RS-422-A

(RXCSR-9)

*Normal configuration is typically RS-423-A compatible. Alternate option is typically RS-422-A compatible.

2-1

Table 2-1

Configuration Sheet (Cont)

(W3-W11) Interface Selection Jumpers (Cont)

Output
Signals

Normal*
Configuration

SF/RL
(RXCSR-0)

W3 to W4

Local

Alternate*
Option

Description
Select frequency

W5 to W3

Remote loopback

W8 to W9

Not connected

Local loopback

Not connected

W8
to Wl

Local loopback (alternate pin)

Loopback

(W12-W17) Receiver Termination Jumpers

Receiver

Normal*
Configuration

Alternate*
‘Option

Description

Receive Data

Not connected

Wi12toWI3

Connects

Send Timing

terminating

resistor

for

RS-422-A compatibility

Not connected

W14 to WIS

Not connected

W16 to W17

Receive
Timing

(W18-W23) Clock Jumpers

Normal*

Alternate*

Function

Configuration

Option

NULL MODEM

W20 to W18

Sets NULL CLK MODEM CLK

CLK

to 2 kHz.

W21 to W18
Clock Enable

Description

W19 to W21
W22 to W23

2-2

Sets NULL MODEM CLK to

50 kHz.

Always installed except for factory
testing.

Table 2-1

Configuration Sheet (Cont)

(W24-W28) Data Set Change Jumpers
Modem Signal
Name

Normal*
Configuration

Alternate*
Option

Data Mode (DSR)

W26 to W24

Not connected

Connects the DSCNG flip-flop to

Clear to Send

W26 to W25

Not connected

for transition detection.

Incoming Call

W26 to W27

Not connected

Note: W26 is input to DSCNG flip-

Receiver Ready

W26 to W28

Not connected

Description
the respective modem status signal

flop

(Carrier Detect)

*Normal configuration is typically RS-423-A compatible. Alternate option is typically RS-422-A compatible.

Device Address Jumpers

GND
W29

Al2
W3l

All
W30

Al10
W36

A9
W33

A8
W32

A7
W39

A6
W38

A5
W37

NOTE

The address to which the DPV11 is to respond is
daisy-chain jumpered to W29 (GND).
Vector Address Jumpers

W43

W42

W4l

W40

W44

W45

Source

W46

NOTE
Vector address to be asserted is daisy-chain jumpered to W46.

NOTE

Table 2-1 shows the recommended normal and alternate jumpering schemes. Any deviation from these
will cause diagnostics to fail and require restrapping
for full testing and verification. It is recommended
that customer configurations that vary from this
scheme not be contractually supported.

A4
W34

A3
W35

Before installing the QMA DPV11 interface module, the following tasks must be performed.
1.

Verify that the following modem interface wirewrap jumpers are installed (Figure 2-1).
a.
b.
C.
d.
e.
f.
g

W26 to W25 to W24 to W28 to W27
W22 to W23 and W19 to W21
W18 to W20
W5 to Wé
W3 to W4
W8 to W9
WI1toW2

\
_

J1
_

W12

346567

TERM!NAL/ 012

TIMING

OCDOO

891011

‘QNTERFACE

O13 [ TERMINATING

SELECTION

JUMPERS

O14 \ RESISTOR

O1s
O16

[ JUMPERS
FOR RS-422-A

017

gO»
W18

CLOCK JUMPERS

0]oYeYoXo)

26% 28

DATA SET CHANGE JUMPERS

*W26 IS INPUT TO DSCNG FLIP FLOP

SHIPPED

ADDRESS

VECTOR

160010

300
r'*s.__-/\._.-—-\‘

W2930 3234 36 38

Q00000
OO0
e)

3133353739

40 42 44

0000
00O

41 43 45

JUMPERS ARE
DAISY CHAINED

pd
B

l,
A

MK-1338

Figure 2-1

QMA DPV11 Jumper Locations

2-4

This is the shipped configuration. Some of these jumpers may be changed when the module is
connected to external equipment for a specific application. The RS-423-A NULL MODEM
CLOCK is set to 2 kHz as shipped.
|

Based on the LSI-11 bus floating vector scheme or user requirements, determine the vector
address for the specific QMA DPV11 module being installed and configure jumpers W40
through W46 accordingly (Table 2-2). The floating vector ranking is 22.

Table 2-2

Vector Address Selection

DPV11 (M8020) VECTOR ADDRESSING

MSB

6I5

4,3‘2

JUMPERS
T
'
:

| X

VECTOR
ADDRESS

300

X | x
X

0‘

L
I

w42 | wa1jwao|waa|was

LSB

l 170 0 | O I
!

JUMPER
NUMBER

| X

X | x

| x

| x|

| x

J x|

310
320

| X

330
340

350
360

370
400

| x|

500

600

700

X" INDICATES A CONNECTION TO W46.

W46 IS THE SOURCE JUMPER FOR THE VECTOR ADDRESS
JUMPERS ARE DAISY CHAINED.

MK 1341

Based on the LSI-11 bus floating address scheme or user requirements, determine the device
address range for this QMA DPV11 module and configure W30 through W39 accordingly
(Table 2-3). Devices may be physically addressed starting at 160000 and continuing through
177776; however, there may be some software restrictions. The normal addressing convention is
shown in Table 2-3. The floating address ranking is 44.

Table 2-3

Device Address Selection

DPV11-XX (M8020) DEVICE ADDRESSING
MSB

LSB

13 | 12 I 11

]10]

9 | g8 | 7 | 6 l 5 | 4 | 3

JUMPERS

B l 0

JUMPER

NUMBER

W31§

——

sat—

W30|W36{W33

W32} W39 | W38

DEVICE

W37 W34 |W35

ADDRESS

760010

760030
760040

X X X X

760020

760050

X
X

760060
X

760070

760100

760200
-

760300
.
-

760400
-

760500
760600

760700
-

X
X

761000
|

762000

763000
-

764000

“X" INDICATES A CONNECTION TO W29. W29 IS TlED TO
GROUND. JUMPERS ARE DAISY CHAINED.
MK-1339

2-6

2.4 INSTALLATION
The QMA DVPI11 interface module can be installed in any LSI-11 bus-compatible backplane such as
H9270. LSI-11 configuring rules must be followed. Proceed with the installation as follows. For additional
information, refer to the PDP-11/03 User Manual (EK-LSI11-TM) or the LSI-11 Installation Guide
(EK-LSI11-1G).
1.

Configure the address and vector jumpers at this time if they have not been done previously
(Paragraph 2.3).
WARNING
Turn all power OFF.

Connect the female BergTM connector on the 7018209 panel assembly to J1 on the M8020
module*, and plug the module into a dual LSI-11 bus slot of the backplane.
CAUTION
~ Insert and remove modules slowly and carefully to
avoid snagging module components on the card
guides.

Perform resistance checks from backplane pin AA2 (+5 V) to ground and from AD2 (+12 V)
to ground to ensure that there are no shorts on the M8020 module or backplane.

Turn system power ON.

Check the voltages to ensure that they are within the specified tolerances (Table 2-4). If
voltages are not within specified tolerances, replace the associated regulator (H780 P.S.)

Table 2-4

Voltage

Max.

Voltage Requirements

Min.

Backplane Pin

AA2

+5V

+35.25

+4.75

+12V

12.75

+11.25 | AD2

2.4.1 1/0 Bulkhead
The 1/0 bulkhead, mounted at the rear of the PDP-11/23 system enclosure, is used in both the DPV11-M
and DPV11-AP applications. The I/O bulkhead and distribution panels have been designed to meet FCC
requirements for limiting electromagnetic interference (EMI) leakage. The bulkhead contains six cutouts

for mounting various distribution panels and/or filter assemblies. Whenever a distribution panel is not
used, the cutout is covered with a blank metal panel that is secured to the bulkhead with screws to prevent
any EMI leakage.

The I/O bulkhead mounts on a tab at the rear of the enclosure and it is secured to the enclosure with two
screws through the tab on the left of the bulkhead. Figure 2-2 shows the bulkhead mounted at the rear of a
PDP-11/23 enclosure.

Paragraph 2.4.2 describes the installation procedures for the distribution panels and/or filter assemblies

into the bulkhead.
*

If a 7018209-0 panel assembly and H3259 turnaround connector are not available, an on-board test connector (H3260) can be
ordered separately. See Paragraph 2.5.

BergTM is a trademark of Berg Electronics,
Inc.

FCC

BULKHEAD

iO)

@ @

@l | )OO

DISTRIBUTION PANEL
AND FILTER ASSEMBLY
70-18209

TK-10735

Figure 2-2

2.4.2

1/0 Bulkhead in a PDP-11/23 System

Distribution Panel Installation

The distribution panel is part of a filter assembly. This assembly consists of:

The distribution panel,
The filter assembly,
The connector(s), and
The cable.

Install the DPV11-AP distribution panel and filter assembly (7018209-0) as follows (see Figure 2-3):

Remove the four screws that secure the blank panel covering one of the two elongated slots at
the bottom of the 1/0 bulkhead;

Remove the blank panel;

From the front of the bulkhead, insert P1 of the cable and the filter assembly through the
opening in the bulkhead until the mounting panel, containing the filter assembly and connector
P2, is flush against the bulkhead;

Secure the mounting panel to the bulkhead from the front of the bulkhead with four screws;
and

With the QMA DVPI11-AP module installed in the backplane, insert P1 of the 7018209 cable
into J1 of the module.

2-8

DISTRIBUTION PANEL.

CONNECTOR

FILTER ASSEMBLY

FCC

BULKHEAD**

(REAR VIEW)

BC26L

P/O 70-18209
ASSEMBLY
V resu—— 1

M8020

A -_jJ

___5“

SYNCHHONOUS LINE

INTERFACE

A be—

*BLANK PANELS

SEE APPENDIX A FOR FCC BULKHEAD DESIGNATION

Figure 2-3

TK-10734

Distribution Panel Installation

Verification of Hardware Operation

2.4.3

The M8020 module is now ready to be tested. This is accomplishcd by running the CZDPV diagnostic.
Additional information on the QMA DPV1l dlagnostlcs is contained in Appendix A and Chapter 5.
Proceed as follows.

Connect the H3259 t turnamund connector to the EIA connection on the I/O bulkhead. The

jumper W1 on the H3259 turnaround connector must be removed.

If a BC26L-25 cable and H3259 turnaround connector are not available, an on-board test connector (H3260) can be ordered

separately. See Paragraph 2.5.

2-9

Load and run CZDPV. Three consecutive error-free passes of this test is the minimum requirement for a successful run. If this cannot be achieved, check the following items:

a
b.
C
d

Board seating,
Jumper connections,
Cable connection, and
Test connector.

If a successful run is still unachievable, corrective maintenance is required (See Chapter 5).
3.

Load and run the DEC/X11 System Exerciser configured to test the number of QMA DPV11s
in the system.

Each CXDPV DEC/X11 module tests up to eight consecutively addressed QMA DPV1 Is.
CXDPYV uses a software switch register. Refer to the DEC/X11 Cross-Reference (AS-FO55C-

MC) for switch register use.
The DEC/X11 System Exerciser is designed to achieve maximum contention with all devices
that comprise the system configuration. The CXDPV module runs in this environment. Its
purpose is to isolate QMA DPV11s that adversely affect the system operation.
For information on configuring and running the DEC/X11 System Exerciser, refer to the
DEC/X11 User Manual (AS-FO503B-MC) and the DEC/X11 Cross-Reference (AS-F055CMC).

2.4.4 Connection to External Equipment/Link Testing
The QMA DPV11 interface module is now ready for connection to external equipment.

If the connection is to a synchronous modem, remove the H3259 connector and connect the modem cable

to the panel assembly and to the modem.
Configure jumpers W1 through W28 in accordance with the operating requirements (Table 2-1).
Load and run DCLT (CZCLH) if a full linkis available. DCLT can also be run with a test connector ora
modem analog loopback. This checks the final configuration and isolates failures to the CPU the
communications link, or the modem.

If the connection to external equipment uses RS-422-A, the user must provide the cable and test support.

2.5 TEST CONNECTORS
|
The only test connector provided with the QMA DPV11 module is the H3259 turnaround connector
(Figure 2-4). Table 2-5 and Figure 2-5 show the relationship between pin numbers, signal names, and
register bits when the H3259 is connected by means of the panel assembly to the M8020 module.

2-10

NULL MODEM

24 @

15 @—=

17 @—=

RCP

:———]

SEC XMIT

S ELECT FREQ

»—4

11 @

TCP

14 @

19 @

23 @
@
12

16 @—=

SEC REC

21 @
o

REMOTE LOQP
(SIGNAL QUALITY)

25 &=~

rsTmooe

2 @

3 @—e

REC DATA

‘@

RTS.

XMIT DATA

@—=

8 @—=

wWi'o0——

———g

OY“...“‘.'.‘]O
U3 B BN BN BN BN BE BE BE BN N

CTS
RR

‘
H3259

LOCAL LOQP

18
@
B

6 o—

DATA MODE

WI IS CUT FOR TESTING DPV11
.

20 @

DTR.

22 @ =

INCOMING CALL

MK-1329

Figure 2-4

H3259 Turnaround Test Connector

The following are accessories available for interfacing and may be ordered separately.
e

H3259 turnaround connector

HB856 BergTM connector that includes the H856 BergTM connector and 40 pins. Crimping tools
are available from:
Berg Electronics, Inc.
New Cumberland, PA. 17070

H3260 on-board test connector (includes RS-422 testing)

211

The H3260 on-board test connector (Figure 2-4) may be used to test the M8020 circuitry in its entirety.
RS-422-A circuitry is not tested with the H3259 cable turnaround connector. The H3260 on-board test
connector is shipped configured for testing RS-422-A. It may be configured to test RS-422-A or RS-423A as follows.

RS-422-A

RS-423-A

W1-W2 out

W1-W2 installed

W3-W6é installed

W3-W6 out

The connector is installed into J1 with the jumper side up.
Because the H3260 on-board test connector does not test the cable, the DPV11 should be tested with a
turnaround connector at the modem end of the cable if possible.

Table 2-5

H3259 Test Connections

From

Signal Name

Pin No.
H3259

Pin No.
J1

Pin No.
H3259 | Signal Name

SEND DATA

RECEIVE DATA

REQUEST TO SEND
(RTS) (RXCSR-2)

BB&T

5&8

CLEAR TO SEND
(CTS)(RXCSR-13),
RECEIVER READY
(RR) (RXCSR-12)

LOCAL LOOPBACK
(LL) (RXCSR-3)

DATA MODE
(DM) (RXCSR-9)

SIGNAL QUALITY/
TEST MODE
(SQ/TM) (PCSCR-5)

SELECT FREQ/REMOTE |23/21]
LOOPBACK
(SF/RL) (RXCSR-0)

RR/MM | MM/C

21/25

NULL MODEM

15&17 | RCV CLOCK
TX CLOCK

DATA TERMINAL
READY (DTR)
(RXCSR-1)

N&R

2-12

INCOMING CALL
(IC) (RXCSR-14)

—

H3259

! aal

{

E38

“ond

"’\

TY
N

10
$ 0

RCV CLOCK

prmer—

/
.

G| 7
t

£39

READY

CLEAR TO SEND

*
D

L4
M

flg

RECEIVER READY

RXCSR-12 (RR)

ilg

4 o

163

REQUEST TO SEND

“<

RSCSR-2 (RTS)

.18

¢ <

§\

RSCSR-13 (CTS)

NEGATIVE INPUT TO DIFFERENTIAL

RECEIVERS OMITTED FOR CLARITY

—INd

N
MK 1336

Figure 2-5

RS-423-A with H3259 Test Connector

2-13

MUST BE
REMOVED WHEN

23,7 | TESTING A DPV11

DATA TERMINAL

RSCSR-1(DTR)

- PP

« " »

Wit

21| 1 THIS JUMPER

12/
11

| W10 __W9 | = U

vx'{w

N
w

RXCSR-14 (INCOMING 11
CALL

7 4

\\w[/N\

RXCSR-3 (LL)
LOCAL LOOP BACK

(

JJ
TFF

w4 ge
j

—

W3 .~

/ 6

DATA SET

7
N\25|

& —i

P
PP

| \..l.‘é..

SF/RL
RXCSR-0

)

[

PCSCR-5

TN
NN

SQ/TM

£40

‘
CLK
LOCAL

TCP

—.1

RECEIVE DATA

TX CLOCK

\tm

SEND DATA

TEST MODE

SIGN QUAL

MM
o

SF/RL

RR
o

w1
SEND DATA
RX DATA

SEND DATA

AAC

(RS422)
TERM TIMING

deTA——

F O-

W2
[TM

SEND TIMING

N o

RX TIMING

TERM TIMING

W o

(RS422)

CLEAR TO SEND

REQ TO SEND

RX RDY

BBO

5013970A

RS422

RS423
TM

INCOMING CALL
TERM RDY

X o

DD O

DATA MODE

20O

DATA MODE RET

U o

(LOCAL LOOP)

SEND TIM RET

T
O

RX TIM RET

SSo

TERM TIM RET

(RS422)
SEND DATA RET
RX DATA RET

KK
o

So
H3260 TEST CONNECTOR
NOTE: 1. W1 & W2 IN

W3-W6 OUT
2. W1 & W2 OUT

W3-W6 IN

} RS-423-A TESTING
} RS-422-A TESTING
MK-1464

Figure 2-6

H3260 On-Board Test Connector

2-14

CHAPTER 3
REGISTER DESCRIPTIONS
AND PROGRAMMING INFORMATION

3.1

INTRODUCTION

This chapter describes the bit assignments and programming considerations for the QMA DPV11. Some
typical start and receive sequences for both bit- and character-oriented protocols are included.
3.2 QMA DPVI11 REGISTERS AND DEVICE ADDRESSES
The five registers used in the QMA DPVI11 are shown in Table 3-1. Note that two of the registers
(PCSAR and RDSR) have the same address. This does not constitute a conflict, however, because the
PCSAR is a write-only register and the RDSR is a read-only register. These five registers occupy eight
contiguous byte addresses that begin on a boundary where the low-order three bits are zero, and they can
be located anywhere between 160000g and 177776g.

Table 3-1

QMA DPV11 Registers

Mnemonic

Address

Receive Control and Status

RXCSR

16xxx0

Receive Data and Status

RDSR**

16xxx2

PCSAR**

16xxx2

Word or byte addressable.
Write-only.
T

PCSCR}

16xxx4

Word or byte addressable.

Parameter Control Sync/Address

Comments
|

Word or byte* addressable.
Read/write.

Word or byte* addressable.

Read-only.

Parameter Control and Character

Length

Transmit Data and Status

Read/write.

TDSR**

16xxx6
|

Word or byte addressable.
Read/write.

* Reading either byte of these registers, clears data and certain status bits in other bytes. See Paragraphs 3.3.1
and 3.3.2.

** Registers contained within the USYNRT.
T It is not possible to do bit set or bit clear instructions on this register.
1 The high byte of this register is internal to the USYNRT.

The QMA DPV11 uses a universal-synchronous receiver/transmitter (USYNRT) chip, which accounts for
a large portion of the QMA DPV11’s functionality. The USYNRT provides complete serialization,
deserialization, and buffering of data to and from the modem.

3-1

Most of the QMA DPVI11 registers are internal to the USYNRT. Only the receiver control and status
register (RXCSR) and the low byte of the parameter control and character length register (PCSCR) are
external.

NOTE
When using the special space sequence function, all
registers internal to the USYNRT must be written
in byte mode.
3.3 REGISTER BIT ASSIGNMENTS
Bit assignments for the QMA DPV11 rchsters are shownin Figure 3-1. Paragraphs 3.3.1 through 3.3.5

provide a d@scnptxon of each register using a bit assngnmcnt illustration and an accompanying table with a
detailed dcscnptmn of cach bit.
3.3.1

Receive Control and Status Register (RXCSR) (Address 16xxx0)

Figure 3-2 shows the format for the receive control and status register (RXCSR). Table 3-2 is a detailed description of the register. This register is external to the USYNRT.

|
NOTE
- The RXCSR can be read in either word or byte

mode. However, reading either byte resets certain

status bitsin both bytes.

- 3.3.2 Receive Data and Status Reglster (RDSR) (Address 16xxx2)
Figure 3-3 show the format for the receive data and status register (RDSR). Itis a read-only register
and shares its address with the parameter control sync/address register (PCSAR) whichis write-only.
Table 3-3 is a detailed description of the RDSR.

NOTE
The RDSR can be read in either word or byte mode.

However, readmg either byte resets data and certain
status bitsin both bytes of this register as well as
bits 7 and 10 of the RXCSR.

3.3.3 Parameter Control Sync/Address Register ( PCSAR) (Address 16xxx2)
The parameter control sync/address register (PCSAR)is a write-only register which can be written in
either byte or word mode. Figure 3-4 shows the format and Table 3-4is a detailed description of the
PCSAR. This register shares its address with the RDSR.

NOTE
Bit set (BIS) and bit clear (BIC) instructions cannot be executed on the PCSCR, since they execute
using a read-modify-write sequence.
3.3.4 Parameter Control and Character Length Register (PCSCR) (Address 16xxx4)
The parameter control and character length register (PCSCR) can be read from or written into in
either word or byte mode. The low byte of this register is external to the USYNRT and the high byte is
internal. Figure 3-5 shows the format and Table 3-5 is a detailed description of the PCSCR.
3.3.5 Transmit Data and Status Register (TDSR) (Address 16xxx6)
The format for the transmit data and status register (TDSR) is shown in Figure 3-6 and Table 3-6 is a
detailed description. The TDSR is a read/write register which can be accessed in either word or byte
mode with no restrictions. All bits can be read from or written into and are reset by Device Reset or
Bus INIT except where noted.

3-2

RXCSR
16 XXX0

READ/WRITE
15

©O07

|rw!lrw!|ew!|erw!|erw!|erw!|rw

DATA
SET
CHANGE

CLR
T0
SEND

RCV
ACTIVE

DATA
MODE

RCV
DATA
READY

DATA
SET
INTR

LOCAL
(LL)
LOOP

DATA
TERM
RDY

INCOMING
CALL

RCVR
READY

RCVR
STATUS

SYNC
OR

READY

RCV
INTR

FLAG

RX
ENA

DETECT

REQ
TO

SF/RL

SEND

RDSR

16XXX2

MK-1504

READ ONLY
15

ASSEMBLED
N
'

ERROR

RCVR

CHECK

OVER

RUN

MESG

]

‘

RECEIVE DATA BUFFER

END

RCV

START

ABORT

MESG

PCSAR

MK-1505

16 XXX2
WRITE ONLY
1

ERROR
DETECTION
SELECTION
l

ALL

STRIP

IDLE

PARTIES

SYNC OR

MODE

LOOP

SELECT

ADDR

'SECONDARY
‘
'
' +
STATION
i

{

RECEIVER SYNC

MODE
PROTOCOL

SECD

SELECT

ADRS
MODE

SEL
MK-18506

Figuré 3-1 QMA DPV11 Register Configurations and Bit Assignments (Sheet 1 of 2)

3-3

PCSAR
16XXX4
READ/WRITE
15

{

R'W
,

R/W

R/W|R/W|RW|RW

09
{

R/W
|

R/W]/|

{

R'W | R/W|

R'W | R’'W |

TRANSMITTER

EXTD

RECEIVER

CHARACTER LENGTH

ADDR

CHARACTER LENGTH

RSVD

SQ/TM

FIELD

MAINT

XMTR

MODE

ACTIVE

SELECT
EXTD

XMIT

XMTR

DEVICE

CONT

INTR

ENAB

BUFFER

RESET

FIELD

EMPTY
MK-1507

TDSR
16 XXX6

READ/WRITE
15

13
I

[
XMIT

1
i

]
%,

12
|

R'W | R'W

| R'W | R/W

|R'W

R/W

l
w4

RESERVED

R/W

XMIT

END

LATE

AHEAD

MESG

R/W

DATA

R/W

]

R/W

]

R/W

]

|
v

TRANSMIT DATA BUFFER

ABORT

START

OF
MESG
MK-1508

Figure 3-1

QMA DPVI11 Register Configurations and Bit Assignments (Sheet 2 of 2)

RDAT | RX

DS
RX
RY** | ITEN | ITEN | ENA

15
DS

CNG

RTS

SF/RL

|RSTA"*

CTS

| Ac7

IRy

SFD

* THIS BIT IS RESET BY READING EITHER BYTE OF THIS REGISTER.
** THESE BITS ARE RESET BY READING EITHER BYTE OF RSDR.
MK-1327

Figure 3-2

Receive Control and Status Register (RXCSR) Format

3-4

Table 3-2 Receive Control and Status Register (RXCSR) Bit Assignments
Bit

Name

Description

Data Set Change

This bit is set when a transition occurs on any of the following

(DSCNG)

modem control lines:
Clear to Send
Data Mode
Receiver Ready
Incoming Call

Transition detectors for each of these four lines can be disabled
by removing the associated jumper.

Data Set Change is cleared by reading either byte of the
RXCSR or by Device Reset or Bus INIT.

Data Set Change causes a receive interrupt if DSITEN (bit 5)
and RXITEN (bit 6) are both set.
14

Incoming Call

(IC)

This bit reflects the state of the modem Incoming Call line. Any
transition of this bit causes Data Set Change bit (bit 15) to be
asserted unless the Incoming Call line is disabled by removing
its jumper. This bit is read-only and cannot be cleared by software.

Clear to Send
(CTS)

This bit reflects the state of the Clear to Send line of the
modem. Any transition of this line causes Data Set Change (bit
15) to be set unless the jumper enabling the Clear to Send signal
is removed.

Clear to Send is a program read-only bit and cannot be cleared
by software.
12

Receiver Ready
(RR)

This bit is a direct reflection of modem Receiver Ready lead. It
indicates that the modem is receiving a carrier signal. For external maintenance loopback, this signal must be high. If the line is
open, RR is pulled high by the circuitry.
Any transition of this bit.causes Data Set Change (bit 15) to be
asserted unless the jumper enabling the Receiver Ready signal
is removed.

Receiver Ready is a read-only bit and cannot be cleared by software.

Receiver Active
(RXACT)

This bit is set when the USYNRT presents the first character of
a message to the DPV11. It remains set until the receive data
path of the USYNRT becomes idle.
Receiver Active is cleared by any of the following conditions: a
terminating control character is received in bit-oriented protocol
mode; an off transition of Receiver Enable (RXENA) occurs; or
Device Reset or Bus INIT is issued.

3-5

Table 3-2
Bit

Receive Control and Status Register (RXCSR) Bit Assignments (Cont)

Name

Description

Receiver Active is a read-only bit which reflects the state of the
USYNRT output pin 5.
10

Receiver Status
Ready (RSTARY)

This bit indicates the availability of status information in the
upper byte of the receive data and status register (RDSR). It is
set when any of the following bits of the RDSR are set: Receiver
End of Message (REOM); Receiver Overrun (RCV OVRUN);
Receiver Abort or Go Ahead (RABORT); Error Check
(ERRCHK) if VRC is selected.

Receiver Status is cleared by any of the following conditions:
reading either byte of the RDSR; clearing Receiver Enable (bit
4 of RXCSR); Device Reset, or Bus Init.
When set, Receiver Status Ready causes a receive interrupt if
Receive Interrupt Enable (bit 6) is also set.
Receiver Status Ready is a read-only bit which reflects the state
of USYNRT pin 7.

Data Mode (DM)
(Data Set Ready)

This bit reflects the state of the Data Mode signal from the
modem.

When this bit is set it indicates that the modem is powered on
and not in test, talk or dial mode.
Any transition of this bit causes the Data Set Change bit (bit
15) to be asserted unless the Data Mode jumper has been removed.

Data Mode is a read-only bit and cannot be cleared by software.

Sync or Flag
Detect (SFD)

This bit is set for one clock time when a flag character is detected with bit-oriented protocols, or a sync character is detected with character-oriented protocols.
SFD is a read-only bit which reflects the state of USYNRT pin
4.

Receive Data
Ready (RDATRY)

This bit indicates that the USYNRT has assembled a data character and is ready to present it to the processor.

If this bit becomes set while Receiver Interrupt Enable (bit 6) is
set, a receive interrupt request will result.
Receive Data Ready is reset when either byte of RDSR is read,
Receiver Enable (bit 4) is cleared, or Device Reset or Bus INIT
is issued.

'RDATRY is a read-only bit which reflectes the state of USYNRT pin 6.

3-6

Table 3-2
Bit

Receive Control and Status Register (RXCSR) Bit Assignments (Cont)

Name

Description

Receiver Interrupt
Enable (RXITEN)

When set, this bit allows interrupt requests to be made to the
receiver vector whenever RDATRY (bit 7) becomes set.

The conditions which cause the interrupt request are the assertion of Receive Data Ready (bit 7), Receive Status Ready (bit
10), or Data Set Change (bit 15) if DSITEN (bit 5) is also set.
RXITEN is a program read/write bit and is cleared by Device
Reset or Bus INIT.

Data Set Interrupt
Enable (DSITEN)

This bit, when set along with RXITEN, allows interrupt
requests to be made to the receiver vector whenever Data Set
Change (bit 15) becomes set.
DSITEN is a program read/write bit and is cleared by Device
Reset or Bus INIT.

Receiver Enable
(RXENA)

This bit controls the operation of the receive section of the USYNRT.

When this bit is set, the receive section of the USYNRT is enabled. When it is reset the receive section is disabled.
In addition to disabling the receive section of the USYNRT, resetting bit 4 reinitializes all but two of the USYNRT receive
registers. The two registers not reinitialized are the character
length selection buffer and the parameter control register.
Local Loopback

(LL)

Asserting this bit causes the modem connected to the QMA
DPV11 to establish a data loopback test condition.
Clearing this bit restores normal modem operation.

Local Loopback is program read/write and is cleared by Device
Reset or Bus request to Send is program read/write and is
cleared by Device Reset or Bus INIT.

Request to Send
(RTS)

Setting this bit asserts the Request to Send signal at the modem
interface.
Request to Send is program read /write and is cleared by Device
Reset or Bus INIT.

Terminal Ready (TR)
(Data Terminal
Ready)

When set, this bit asserts the Terminal Ready signal to the
modem interface.

For auto dial and manual call origination, it maintains the established call. For auto answer, it allows handshaking in response to
a Ring signal.

3-7

Table 3-2
Bit

Receive Control and Status Register (RXCSR) Bit Assignments (Cont)

Name

Description

Select Frequency
or Remote
Loopback (SF/RL)

This bit can be wire-wrap jumpered to function as either select
frequency or remote loopback. When jumpered as select frequency (W3 to W4), setting this bit selects the modem’s higher
frequency band for transmission to the line and the lower frequency band for reception from the line. The clear condition selects the lower frequency for transmission and the higher frequency for reception.

When jumpered for remote loopback (W5 to W3), this bit, when
asserted, causes the modem connected to the DPV11 to signal
when a remote loopback test condition has been established in
the remote modem.

SF/RL is program read/write and is cleared by Device Reset or
Bus INIT.

RECEIVE DATA BUFFER

ASSEMBLED
BIT COUNT

ERR
CHK

10°

lFIEC
ovrun| AEORT| REOM |RSOM
MK-1326

Figure 3-3

Table 3-3

Receive Data and Status Register (RDSR) Format

Receive Data and Status Register (RDSR) Bit Assignments

Bit

Name

Description

Error Check
(ERR CHK)

This bit when set, indicates a possible error. It is used in conjunction with the error detection selection bits of the parameter
control sync/address register (bits 8—10) to indicate either an
error or an all zeros state of the CRC register.

With bit-oriented protocols, ERR CHK indicates that a CRC
error has occurred. It is set when the Receive End of Message
bit (RDSR bit 9) is set.

With character-oriented protocols ERR CHK is asserted with
each data character if all zeros are in the CRC register. The
processor must then determine if this indicates an error-free

3-8

Table 3-3
Bit

Receive Data and Status Register (RDSR) Bit Assignments (Cont)

Name

Description

message or not. If VRC parity is selected, this bit is set for every
character which has a parity error.

ERR CHK is cleared by reading the RDSR, clearing RXENA

(RXCSR bit 4), Device Reset or Bus INIT.

TM~

= O

All bits are valid
One valid bit
Two valid bits
Three valid bits
Four valid bits
Five valid bits
Six valid bits
Seven valid bits

et O

Number of Valid Bits

— O

D bk ek OO
ek

)

000
—_————_0

Used only with bit-oriented protocols, these bits represent the
number of valid bits in the last character of a message. They are
all zeros unless the message ends on an unstated boundary. The
bits are encoded to represent valid bits as shown below.

pod

Assembled Bit
Count (ABC)

14-12

These bits are presented simultaneously with the last bits of
data and are cleared by reading the RDSR or by resetting
RXENA (bit 4 of RXCSR).

Receiver Overrun
(RCV OVRUN)

This bit is used to indicate that an overrun situation has occurred. Overrun exists when the data buffer (bits 0—7 of RDSR)
has not been serviced within one character time.

As a general rule, the overrun is indicated when the last bit of
the current character has been received into the shift register of
the USYNRT and the data buffer is not yet available for a new
character.

Two factors exist which modify this general rule and apply only
to bit-oriented protocols.

The first factor is the number of bits inserted into the data
stream for transparency. For each bit inserted during the formatting of the current character, the controller’s maximum response time is increased by one clock cycle.
The second factor is the result of termination of the current
message. When this occurs, the data of the terminated message
which is within the USYNRT is not overrunable. If an attempt
is made to displace this data by the reception of a subsequent
message, the data of the subsequent message is lost until the
data of the prior message has been released.

3-9

Table 3-3

Receive Data and Status Register (RDSR) Bit Assignments (Cont)

Bit

Name

Description

Receiver Abort or
Go Ahead (RABORT)

This bit is used only with bit-oriented protocols and indicates
that either an abort character or a go-ahead character has been
received. This is determined by the Loop Mode bit (PCSAR bit
13). If the Loop Mode bit is clear, RABORT indicates reception
of an abort character. If the Loop Mode bit is set, RABORT
indicates a go-ahead character has been received.

The setting of RABORT causes Receiver Status Ready (bit 10
of RXCSR) to be set.

RABORT is reset when the RDSR is read or when Receiver Enable (bit 4 of RXCSR) is reset.

The abort character is defined to be seven or more contiguous
one bits appearing in the data stream. Reception of this bit pattern when Loop Mode is clear causes the receive section of the
USYNRT to stop receiving and set RSTARY (bit 10 of
RXCSR). The abort character indicates abnormal termination
of the current message.

The go-ahead character is defined as a zero bit followed by seven consecutive one bits. This character is recognizeéd as a normal
terminating control character when the Loop Mode bit is set. If
Loop Mode is cleared this character is interpreted as an abort
character.

Receiver End of
Message (REOM)

This bit is used only with bit-oriented protocols and is asserted if
Receiver Active (bit 11 of RXCSR) is set and a message is terminated either normally or abnormally. When REOM becomes
set, it sets RSTARY (bit 10 of RXCSR).
|

REOM is cleared when RDSR is read or when Receive Enable
(bit 4 of RXCSR) is reset.

Receiver Start of
Message (RSOM)

Used only with bit-oriented protocols. This bit is presented to
the processor along with the first data character of a message
and is synchronized to the last received flag character. Setting
of RSOM does not set RSTARY (RXCSR bit 10).

RSOM is cleared by Device Reset, Bus INIT, resetting Receiver Enable (RXCSR bit 4), or the next transfer into the Receive Data buffer (low byte of RDSR).
7-0

Receive Data

Buffer

The low byte of the RDSR is the Receive Data buffer. The se-

rial data input to the USYNRT is assembled and transferred to
the low byte of the RDSR for presentation to the processor.
When the RDSR receives data, Receive Data Ready (bit 7 of
RXCSR) becomes set to indicate that the RDSR has data to be
picked up. If this data is not read within one character time, a
data overrun occurs.

The characters in the Receive Data buffer are right-justified

with bit 0 being the least significant bit.

3-10

SYNC CHARACTER OR
i

SECONDARY STATION ADDRESS

APA

gzlc_)’r g';'g
|

ADR | IDLE |
MDE

SEC

l
|

{

ERR DET SEL
MK-1330

Figure 3-4

Table 3-4

Parameter Control Sync/Address Register (PCSAR) Format

Parameter Control Sync/Address Register (PCSAR) Bit Assignments

Bit

Name

Description

All Parties
Addressed (APA)

This bit is set when automatic recognition of the All Parties Addressed character is desired. The All Parties Addressed character is eight bits of ones with necessary bit stuffing so as not to be
confused with the abort character.

Recognition of this character is done in the same way as the secondary station address (see bit 12 of this register) except that
the broadcast address is essentially hardwired within the receive
data path. The logic inspects the address character of each
frame for the broadcast address. When the broadcast address is
recognized, the USYNRT makes it available and sets Receiver
Start of Message (bit 8 of RDSR).
If the broadcast address is not recognized, one of two possible
actions occurs.
1. If the Secondary Address Select mode bit (bit 12) is set, a
test of the secondary station address is made.
2. If bit 12 is not set or the secondary station address is not
recognized, the receive section of the USYNRT renews its
search for synchronizing control characters.
14

Protocol Select
(PROT SEL)

This bit is used to select between character- and byte count-oriented or bit-oriented protocols. It is set for character- and byte
count-oriented protocols and reset for bit-oriented protocols.

Strip Sync or
Loop Mode
(STRIP SYNCO)

This bit serves the following two functions.
1. Strip Sync (character-oriented protocols) — In character-oriented protocols, all sync characters after the initial synchronization are deleted from the message and not included in the
CRC computation if this bit is set. If it is cleared, all sync characters remain in the message and are included in the CRC computation.
3-11

Table 3-4
Bit

Parameter Control Sync/Address Register (PCSAR) Bit Assignments (Cont)

Name

Description

2. Loop Mode (bit-oriented protocols) — With bit-oriented protocols, this bit is used to control the method of termination. If it
is set, either a flag or go-ahead character can cause a normal
termination of a message. If it is cleared, only a flag character
can cause a normal termination.
12

Secondary
Address Mode
(SEC ADR MDE)

This bit is used with bit-oriented protocols when automatic recognition of the secondary station address is desired. If it is set,
the station address of the incoming message is compared with
the address stored in the low byte of this register. Only messages
prefixed with the correct secondary address are presented to the
processor. If the addresses do not compare, the receive section
of the USYNRT goes back to searching for flag or go-ahead
characters.

When SEC ADR MDE is cleared, the receive section of the
USYNRT recognizes all incoming messages.
11

Idle Modc Select
(IDLE)

This bit is used with both bit- and character-oriented protocols.
With bit-oriented protocols, IDLE is used to select the type of
control character issued when either Transmit Abort (bit 10 of
TDSR) is set or a data underrun error occurs. If IDLE is set,
flag characters are issued. If IDLE is clear, abort characters are
issued.
With character-oriented protocols, IDLE is used to control the
method in which initial sync characters are transmitted and the
action of the transmit section of the USYNRT when an underrun error occurs. IDLE is cleared to cause sync characters from
the low byte of PCSAR to be transmitted. When IDLE is set,
the transmit data output is held asserted during an underrun error and at the end of a message.

10-8

Error Detection
Selection

(ERR DEL SEL)

These bits are used to determine the type of error detection used
on received and transmitted messages. In bit-oriented protocols,
the selection is independent of character length. In characterand byte count-oriented protocols, CRC error detection is usable only with 8-bit character lengths. The maximum character
length for VRC is seven. The bits are encoded as follows.

CRC Polynomial

x16+x12+x5+1 (CRC CCITT) (Both CRC
data registers in the transmit and receive sections are set to all ones prior to the computation.)

3-12

x16+x12+x5+1 (CRC CCITT) (Both CRC
data registers set to all zeros.)

Table 3-4
Bit

Parameter Control Sync/Address Register (PCSAR) Bit Assignments (Cont)
Description

Name

Not used

x16+x154+x241 (CRC 16) (Both CRC regis-

Odd VRC Parity (A parity bit is attached to

ters set to all zeros.)

each transmitted character.) Should be used
only in character-oriented protocols.

Even VRC parity (Resembles odd VRC ex-

cept that an even number of bits are generated.)

7-0

Not used.

Allerror detection is inhibited.

The low byte of PCSAR is used as either the sync character for

Sync Character

character-oriented protocols or as the secondary station address

or Secondary
Address

for bit-oriented protocols.

The bits are right-justified with the least significant bit being bit
0.

EXTERNAL TO THE USYNRT

6
X
rRsvD | INT

|SQ/TM|TXENA

3
2
Mm | T8

seL | emry

TXACT

[TXACT|RESET

INTERNAL TO THE USYNRT

(15
14
TRANSMITTER

10
9
g )
RECEIVER
CHARACTER LENGTH EXADDIEXCON CHARACTER LENGTH |
|

MK-1325

Figure 3-5

Parameter Control and Character Length Register (PCSCR) Format
3-13

Table 3-S

Parameter Control and Character Length Register (PCSCR) Bit Assignments

Bit

Name

Description

15-13

Transmitter
Character Length

These bits can be read or written and are used to determine the
length of the characters to be transmitted.
They are encoded to set up character lengths as follows.
15

Character Length

Eight bits per character

Seven bits per character

Six bits per character

Five bits per character (bit-oriented protocol
only)

Four bits per character (bit-oriented protocol
only)

Three bits per character (bit-oriented protocol

only)
0O

Two bits per character (bit-oriented protocol
only)

One bit per character (bit-oriented protocol
only)

These bits can be changed while the transmitter is active, in
which case the new character length is assumed at the completion of the current character. This field is set to a character
length of eight by Device Reset or Bus INIT. When VRC error
detection is selected, the default character length is eight bits
plus parity.
12

Extended Address
Field (EXADD)

This bit is used with bit-oriented protocols and affects the address portion of a message in receiver operations. When it is set,
each address byte is tested for a one in the least significant bit
position. If the least significant bit is zero, the next character is
an extension of the address field. If the least significant bit is
one, the current character terminates the address field and the
next character is a control character.
EXADD is not used with Secondary Address Mode (bit 12 of

PCSAR).

EXADD is read/write and is reset by Device Reset or Bus
INIT.
11

Extended Control
Field (EXCON)

This bit is used with bit-oriented protocols and affects the control character of a message in receiver operations. When EX3-14

Table 3-5 Parameter Control and Character Length Register (PCSCR) Bit Assignments (Cont)
Bit

Name

Description
CON is set it extends the control field from one 8-bit byte to
two 8-bit bytes.
EXCON is not used with Secondary Address Mode (bit 12 of
PCSAR)

EXCON is read/write and is reset by Device Reset or Bus
INIT.

10-8

Receiver
Character Length

These bits are used to determine the length of the characters to
be received.
They are encoded to set up character lengths as follows.

Character Length

Eight bits per character

Seven bits per character

Six bits per character

Five bits per character

Four bits per character (bit-oriented protocols

only)
0O

Three bits per character (bit-oriented protocols only)

Two bits per character (bit-oriented protocols
only)

One bit per character (bit-oriented protocols
only)

Reserved

Not used by the DPV11

Transmit Interrupt
Enable (TXINTEN)

When set, this bit allows a transmitter interrupt request to be
made to the transmitter vector when Transmit Buffer Empty
(TBEMTY) is asserted. Transmit Interrupt Enable (TXINTEN) is read/write and is cleared by Device Reset or Bus
INIT.

Signal Quality or
Test Mode (SQ/TM)

This bit can be wire-wrap jumpered to function as either Signal
Quality or Test Mode.
When jumpered for signal quality (W5 to W6), this bit reflects
the state of the signal quality line from the modem. When asserted, it indicates that there is a low probability of errors in the
received data. When clear it indicates that there is a high probability of errors in the received data.

3-15

Table 3-S5
Bit

Parameter Control and Character Length Register (PCSCR) Bit Assignments (Cont)

Name

Description
When jumpered for the test mode (W6 to W7), this bit indicates
that the modem has been placed in a test condition when asserted.
The modem test condition could be established by asserting Local
Loopback (bit 3 of RXCSR), Remote Loopback (bit 0 of
RXCSR), or other means external to the QMA DPV11.
&

When SQ/TM is clear, it indicates that the modem is not in test
mode and is available for normal operation.

SQ/TM is program read-only and cannot be cleared by software.

Transmitter
Enable (TXENA)

This bit must be set to initiate the transmission of data or control information. When this bit is cleared, the transmitter will
revert back to the mark state once all indicated sequences have
been completed. TXENA should be cleared after the last data

character has been loaded into the transmit data and status register (TDSR). Transmit End of Message (bit 9 of TDSR) should
be asserted when TXENA is reset (if it is to be asserted at all)
and remain asserted until the transmitter enters the idle mode.
TXENA is connected directly to USYNRT pin 37. It is a

read/write bit and is reset by Device Reset or Bus INIT.
Maintenance Mode
Select (MM SEL)

When this bit is asserted, it causes the USYNRT’s serial output

to be internally connected to the USYNRT’s serial input. The
serial send data output line from the interface is asserted and
the receive data serial input is disabled. Send timing and receive
timing to the USYNRT are disabled and replaced with a clock
signal generated on the interface. The clock rate is either

49.152K b/s or 1.9661K b/s depending on the position of a
jumper on the interface board.

Maintenance mode allows diagnostics to run in loopback without disconnecting the modem cable.
MM SEL is a read/write bit and is cleared by Device Reset or
Bus INIT. When it is cleared, the interface is set for normal operation.
Transmitter Buffer
Empty (TBEMTY)

This bit is asserted when the transmit data and status register
(TDSR) is available for new data or control information. It is
also set after a Device Reset or Bus INIT.

The TDSR should be loaded only in response to TBEMTY
being set. When the TDSR is written into, TBEMTY is cleared.
If TBEMTY becomes set while Transmit Interrupt Enable (bit
6 of PCSCR) is set, a transmit interrupt request results.

TBEMTY reflects the state of USYNRT pin 35.

3-16

Table 3-5

Parameter Control and Character Length Register (PCSCR) Bit Assignments (Cont)

Bit

Name

Description

Transmitter

This bit indicates the state of the transmit section of the US-

Active (TXACT)

YNRT. It becomes set when the first character of data or control information is transmitted.
TXACT is cleared when the transmitter has nothing to send or
when Device Reset or Bus INIT is issued.

TXACT reflects the state of USYNRT pin 34.

Device Reset
(RESET)

- When a one is written to this bit all components of the interface
are initialized. It performs the same function as Bus INIT with

respect to this interface. Modem Status (Data Mode, Clear to
Send, Receiver Ready, Incoming Call, Signal Quality or Test
Mode) is not affected. RESET is write-only; it cannot be read
by software.

I
I

RESERV!—E‘D
l

TRANSMIT DATA BUFFER

|
11

TERR

I
10

TGA |TM*

ABORT

|
9

| TEOM| TSOM
MK-1331

Figure 3-6

Table 3-6

Bit

Transmit Data and Status Register (TDSR) Format

Transmit Data and Status Register (TDSR) Bit Assignments

Name

Description

Transmitter

This is a read-only bit which becomes asserted when the Transmitter Buffer Empty (TBEMTY) indication has not been serviced for more than one character time.

Error (TERR)

When TERR occurs in bit-oriented protocols, the transmit section of the USYNRT generates an abort or flag character based
on the state of the IDLE bit (PCSAR bit 11). If IDLE is set, a
flag character is sent. If it is reset, an abort character is sent.

When TERR occurs in character-oriented protocols, the state of
the IDLE bit again determines the result. If IDLE is set, the
transmit serial output is held in the MARK condition. If it is
cleared, a sync character is transmitted.

3-17

Table 3-6
Bit

Transmit Data and Status Register (TDSR) Bit Assignments (Cont)

Name

Description

TERRis cleared when TSOM (TDSR bit 8) becomes set or by
Device Reset or Bus INIT.

Clearing Transmitter Enable (PCSCR bit 4) does not clear
TERR and TERR is not set with Transmit End of Message.
14-12
11

Reserved
Transmit Go
~ Ahead (TGA)

Not used by the QMA DPV11

This bit, when asserted, modifies the bit pattern of the control
character initiated by either Transmit Start of Message
(TSOM) or Transmit End of Message (TEOM). TSOM or
TEOM normally causes a flag character to be sent. If TGA is
~set, a go-ahead character is sent in place of the flag character.

TGA is only used with bit-oriented protocols.
10

Transmit
Abort (TXABORT)

This bit is used only with bit-oriented protocols to abnormally

terminate a message or to transmit filler information used to establish data link timing.

When TXABORT is asserted, the transmitter automatically
transmits either flag or abort characters depending on the state
of the IDLE mode bit. If IDLE is cleared, abort characters are
sent. If IDLE is set, flag characters are sent.
Transmit End of
Message (TEOM)

This control bit is used to normally terminate a message in bitoriented protocol. It also terminates a message in character-oriented protocols when CRC error detection is used. As a secondary function, it is used in conjunction with the Transmit Start of
Message (TSOM) bit to transmit a SPACE SEQUENCE. Refer to the TSOM bit description (bit 8 of this register) for information regarding this sequence.

With bit-oriented protocols, asserting this bit causes the CRC
information to be transmitted, if CRC is enabled, followed by
flag or go-ahead characters depending on the state of the Transmit Go Ahead (TGA) bit. See bit 11 of this register.
With character-oriented protocols, asserting this bit causes
CRC information, if CRC is enabled, to be transmitted followed
by either sync characters or a MARK condition depending on
the state of the IDLE bit. If IDLE is cleared, sync characters
are transmitted.
The character following the CRC information is repeated until
the transmitter is disabled or the TEOM bit is cleared.

A subsequent message may
be initiated while the transmit section of the USYNRT is active. This is accomplished by clearing
the TEOM bit and supplying new message data without setting

3-18

Bit

Table 3-6
-

Transmit Data and Status Register (TDSR) Bit Assignments (Cont)

Name

Description
the Transmit Start Of Message bit. However, the CRC character for the prior message must have completed transmission.

Transmit Start
of Message
(TSOM)

This bit is used with either bit- or character-oriented protocols.
As long as it remains asserted, flag characters (bit-oriented protocols) or sync characters (character-oriented protocols) are

transmitted.

With bit-oriented protocols, a space sequence (byte mode only)
of 16 zero bits can be transmitted by asserting TSOM and
TEOM simultaneously provided the transmitter is in the idle
state and Transmit Enable is cleared. This should not be done
during the transfer of data, and must only be done in byte mode.
NOTE
When using the special space sequence functmn, all registers internal to the USYNRT must be written in byte mode.

Normally at the completion of each sync, flag, go-ahead or
Abort character, the TBEMTY indication is asserted. This allows the software to count the number of transmitted characters. In certain applications, the software may elect to ignore the
service of the Transmitter Buffer Empty (TBEMTY) indication.
Normally during data transfers, this would cause a transmit
data late error. The TSOM bit asserted suppresses this error
and provides the necessary synchronization to automatically
transmit another flag, go-ahead or sync character.

7-0

Transmit Data
Buffer

Data from the processor to be transmitted on the serial output
line is loaded into this byte of the TDSR when Transmitter Buffer Empty (TBEMTY) is asserted. If the transmitter buffer is
not loaded within one character time, an underrun error occurs.
- The characters are right-justified, with bit 0 being the least significant bit.

3.4

DATA TRANSFERS

Paragraphs 3.4.1 and 3.4.2 discuss receive and transmit data transfers as they relate to the system

software.

3.4.1 Receive Data
Serial data to be presented to the QMA DPVI11 from the modem enters the receiver circuit and is

presented to the USYNRT. Recognition by the USYNRT of a control character initiates the transfer.
When a transfer has been initiated, a character is assembled by the USYNRT and then placed in the low
byte of the receive data and status register (RDSR) when it is available. If the RDSR is not available, the
transfer is delayed until the previous character has been serviced. This must take place before the next
character is fully assembled or an overrun error exists. Refer to the description of bit 11 in Table 3-3 for
more details on Receiver Overrun.

3-19

Servicing of the RDSR is the responsibility of the system software in response to the Receive Data
Ready (RDATRY) signal. This signal is asserted when a character has been transferred to the RDSR.
The setting of RDATRY would also cause a receive interrupt request if Receive Interrupt Enable
(RXITEN) is set. The software’s response to RDATRY is to read the contents of the RDSR. At the
completion of this operation, the new information is loaded into the RDSR and RDATRY is reasserted. This operation continues until terminated by some control character. The upper byte of the
RDSR contains status and error indications which the software can also read.

The QMA DPVI11 handles data in bit-, byte count- or character-oriented protocols.
With bit-oriented protocol, only flag characters are used to initiate the transfer of a message. Information inserted into the data stream for transparency or control is deleted before it is presented to the
RDSR. This means that only data characters are available to the software. The first two characters of
every message or frame are defined to be 8-bit characters and the USYNRT will handle them as such

regardless of the programmed character length. All subsequent data is formatted in the selected character length. When CRC error detection is selected, the received CRC check characters are not presented
to the software, but the error indication will be presented if an error has been detected.
If the secondary address mode is implemented, the first received data character must be the selected
address. If this is not the case, the USYNRT will renew its search for flag or go-ahead characters.
Refer to the description of bit 12 of the PCSARin Table 3-4.

With byte count- or character-oriented protocols, two consecutive sync characters are required to synchronize the transfer of data. The sync characters used in the message must be the same as the sync
character loaded by the software into the low byte of the parameter control sync/address register
(PCSAR). If leading sync characters subsequent to the initial two syncs are to be deleted from the
data stream, the Strip Sync bit (bit 13) must also be set in the upper byte of the PCSAR. The character length of the data to be received should also be set in bits 8, 9, and 10 of the parameter control and
character length register (PCSCR). Sync characters and data must have the same character length

and only characters of the selected length will be presented to the receive buffer. Sync characters
following the initial two will be presented to the buffer and included in the CRC computation unless
the Strip Sync bit is set. If vertical redundancy check (VRC) parity checking is selected, the parity bit
itself is deleted from the character before it is presented to the buffer.
3.4.2

Transmit Data

System software loads information to be transmitted to the modem into the transmit data and status
.register (TDSR). This does not ordinarily include error detection or control character information.
Loading of the TDSR occurs in response to the Transmitter Buffer Empty (TBEMTY) signal from the
USYNRT. The character length of information to be transmitted is established by the software when
it loads the transmit character length register (bits 13, 14, and 15 of the PCSCR). The default length
of eight is assigned when the transmit character length register equals zero. The length of characters
presented to the TDSR should not exceed the assigned character length. When the information in the
TDSR is transmitted, the TBEMTY signal is again asserted to request another character. The setting
of TBEMTY also causes a transmit interrupt request if Transmit Interrupt Enable is set.
Byte count- or character-oriented protocols require the transmission of synchronizing information normally referred to as sync characters. The sync characters can be transmitted when Transmit Start of
Message (TDSR bit 8) is set. This happens in one of two ways depending on the state of the IDLE bit
(PCSAR bit 11). When the IDLE bit is cleared, the sync character is taken directly from the common
sync register (PCSAR bits 7-0). The sync register would have been previously loaded by the software.
If the IDLE bit is set, the sync character must be loaded into the TDSR by the software when it is to
be transmitted. If multiple sync characters are to be transmitted, the TDSR must only be loaded with
the first one of the sequence. This character will be transmitted until data information is loaded into
the TDSR. The TBEMTY signal is asserted at the end of each sync character but the TSOM signal
allows it to be ignored without causing a data late error.
3-20

With bit-oriented protocols, the USYNRT automatically generates control characters as initiated by
the software and inserts necessary information into the data stream to maintain transparency.
Typical programming examples in bit- and byte count-oriented protocols appear in Appendix D.
3.5 INTERRUPT VECTORS
The QMA DPV11 generates two vector addresses, one for receive data and modem control and the other
for transmit data.

The receive and modem control interrupt has priority over the transmit interrupt and is enabled by
setting bit 6 (RXITEN) of the receiver control and status register (RXCSR).
If bit 6 of the RXCSR is set, a receiver interrupt may occur when any one of the following signals is
asserted.

®
®
®

Receive Data Ready (RDATRY)
Receive Status Ready (RSTARY)
Data Set Change (DAT SET CH)

The signal DAT SET CH only causes an interrupt if bit 5 (DSITEN) of the RXCSR is also set.
It is possible that a data set change interrupt could be pending while a receiver interrupt is being
serviced, or the opposite could be true. In either case, the hardware ensures that both interrupt
requests are recognized.
NOTE
The modem status change circuit interprets any
pulse of two microseconds or greater duration as a
data set change. This ensures that all legitimate
transitions of modem status are detected. However,
on a poor line, noise may be interpreted as a data set
change. Software written for the QMA DPVI11
must account for this possibility.

A transmitter interrupt request occurs if Transmit Interrupt Enable (TXINTEN) is set when Transmit
Buffer Empty (TBEMTY) becomes asserted.

3-21

CHAPTER 4
TECHNICAL DESCRIPTION
4.1

INTRODUCTION

4.2

FUNCTIONAL DESCRIPTION

This chapter provides a 2-level dlscussmn of the QMA DPV11. Paragraph 4.2 mcludes a description of
the QMA DPV11 logicin functional groups at the block diagram level. At this level, a general operational
overview is also discussed. The second level of discussion is the detailed description, which covers the
complete QMA DPV11 logic at the circuit schematic level, as shown in the QMA DPV11 print set.

4.2.1

Logic Description

For discussion purposes, the QMA DPV11 loglcis divided into the ten sections shownin Figure 4-1. The
sections are describedin Paragraphs 4.2.1.1 through 4.2.1.10.

4.2.1.1 Bus Transceivers — The interface for data, and address on the LSI-11 bus consists of four bus

transceiver chips (DCO005). These function as bidirectional buffers between the LSI-11 bus and the QMA
DPV11 Logic. These transceivers provide isolation, address comparison, and vector generation.
4.2.1.2 Read/Write Control — The read/write control logic consists of a DC004 protocol chip and its
associated logic. It provides the control signals for accessing registers and strobing data. It controls
reading from and writing into registers in both word and byte mode, and provides the deskew delays for
these operations.When data has been placed on or picked up from the LSI-11 bus or when vector
information has been placed on the LSI-11 bus, the read/write control logic notifies the processor by
asserting BRPLY.

4.2.1.3

USYNRT and Bidirectional Buffer — The USYNRT provides a large portion of the

functionality of the QMA DPV11. The USYNRT is installed in a socket for ease of replacement. It
provides complete serialization, deserialization and buffering of data between the modem and the LSI-11
bus. The USYNRT also provides logic support, via program parameter registers, for basic protocol
handling and error detection.

The tri-state bidirectional buffer provides the fan-out drive to accommodate the number of circuits the
USYNRT feeds.

4.2.1.4 Receive Control And Status Register (RXCSR) - This register contains most of the control
and status information pertaining to receiver operation, including the status of the lines to and from the
data set. The receive and data set interrupt enable bits are also contained in this register, but the receive interrupt enable is actually generated by the interrupt logic. The high byte of the RXCSR is
read-only and the low byte is read/write. RXCSR is both word- and byte-addressable.
4.2.1.5 Transmit Control And Status Register — This register is the low byte of the parameter control
and character length register (PCSCR). (The high byte is internal to the USYNRT). It contains most
of the control and status information pertaining to transmit operations. The maintenance mode bit is
also a part of this register. The register is read /write and can be accessed separately as the low byte of
the PCSCR or in word mode when the entire PCSCR is accessed.

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Interrupt Logic — Most of the logic for interrupts is contained in a single DCO003 interrupt

chip. The chip contains two interrupt channels: one for receive and one for transmit interrupts. The
circuit generates a receive interrupt when the Receiver Interrupt Enable bit (RXITEN) is set and one
of the following signals becomes asserted.
Receive Status Ready (RSTARY)
Receive Data Ready (RDATRY)
Modem Control Interrupt Request (MCINT)

MCINT requires that DSITEN (RXCSR bit 5) also be set.

If the Transmit Inierrupt Enable bit (PCSCR bit 6) is set, a transmit interrupt is generated when the

Transmit Buffer Empty signal (TBEMTY) is asserted.

Receive interrupts have priority over transmit interrupts.

4.2.1.7 Data Set Change Logic — This logic is used to determine if the modem had a change in status.
Jumpers can be removed or installed to allow any or all of the following signals to set the Data Set
Change bit (RXCSR bit 15).
RS-232-C

RS-449

Clear to Send (CTS)

Carrier Detect (CD)

Receiver Ready (RR)

Data Set Ready (DSR)

Data Mode (DM)

Ring Indicator (RI)

Incoming Call (IC)

If the Data Set Interrupt Enable bit and Receiver Interrupt Enable (RXCSR bits 5 and 6) are both
set, Data Set Change causes the interrupt logic to generate an interrupt request.

4.2.1.8 Clock Circuit — The clock circuit consists of a 19.6608 MHz off-the-shelf oscillator and two
741.S390 dividers to provide the clock signals for the QMA DPV11.
4.2.1.9 EIA Level Converters — These circuits contain drivers and receivers necessary for converting
from TTL levels to EIA levels and from EIA levels to TTL levels. There are drivers and receivers to
accommodate both RS-422-A (RS-449 compatible: limited to clock and data) and RS-423-A (RS-232C compatible) electrical standards. Selection of RS-422-A or RS-423-A interface standard is provided
by wire-wrap jumpers.

4.2.1.10

Charge Pump - This circuit converts the + 12 volts to a negative voltage to power the RS-

423-A drivers.

4.2.2

General Operational Overview

This discussion describes the relationship between the different sections of the block diagram from a
simplified operational viewpoint. It is assumed for the purpose of this discussion that the QMA DPV11
will be operated with the interrupts enabled. A simplified diagram that emphasizes the functions of the
USYNRT (Figure 4-2) is referenced for both the receive and transmit operations. Bit-oriented protocol
(BOP) and byte count- or character-oriented protocols (BCP) are not discussed in detail here.
4.2.2.1

Receive Operation — Serial data from the modem enters the EIA receiver where it is con-

verted from EIA to TTL level. This TTL data is then presented directly to the receive serial input of

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the USYNRT. At the same time the EIA receiver converts the receive timing signal from the modem
to TTL level and presents it to the USYNRT. The USYNRT uses the timing signal to control the
assembling of the incoming data characters. As the information enters the USYNRT, sync-detect and
flag-detect circuits check for FLAG (BOP) or SYNC (BCP) until there is a match. When a match
occurs, assembling of data characters begins. Error circuits check for errors while the data is being
assembled. When a character is assembled in the receive data shift register, it is then transferred to the
receive data buffer, and the USYNRT timing and control logic generates the signal receive data ready
(RDATRY). Interrupt logic uses this signal to produce an interrupt request to the processor. When the
processor responds to the interrupt request, the interrupt logic causes the bus transceiver circuits to
assert the associated vector and the interrupt sequence takes place.

The processor now retrieves the data from the receive data buffer which resets the interrupt condition.
To do this the processor asserts the address of the buffer and the necessary control signals on the bus.
The bus transceivers recognize the address and enable the read/write control logic. The read/write
control logic then generates the necessary control signals to select and read from the receive data buffer (low byte of RDSR). Data in the buffer is sent through the bidirectional tri-state buffer to the LSI11 bus transceivers where it is enabled onto the LSI-11 bus and picked up by the processor. The USYNRT is double-buffered so that while the processor is picking up the character from the receive data
buffer, the receive data shift register is already assembling a second character. This process is repeated
until the entire message is received.

4.2.2.2 Transmit Operation - When the processor wishes to send data to the modem, it first places
the address of the transmit buffer (low byte of TDSR) and the necessary control signals on the LSI-11
bus.

The bus transceivers recognize the address and enable the read/write control logic which selects the
register. The processor then places the parallel data on the LSI-11 bus and the read/write control logic
gates it through the bus transceivers and writes it into the transmit buffer. When a character is written
into the transmit data buffer, the USYNRT transfers it to its transmit shift register and asserts
TBEMTY. Once the character is in the shift register, the USYNRT begins to serialize and send it by
means of the serial output line to the EIA drivers. Here it is converted from TTL to EIA level and sent
to the modem.

TBEMTY causes the interrupt logic to generate an interrupt request to the processor. At the completion of the interrupt sequence, the processor repeats the process of addressing the transmit buffer
and sending another character. This operation continues until the entire message has been sent.
4.3

DETAILED DESCRIPTION

The circuit operation is described in Paragraphs 4.3.1 through 4.3.9.
4.3.1

Bus Transceivers

Data, address and control signals move between the LSI-11 bus and the DPV11 by means of a group of
bus transceivers. The bus transceivers are contained in four DC0O0S5 transceiver chips and perform the
following functions.

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Address selection/decode
Data transfers to and from the LSI-11 bus
Vector generation

4.3.1.1 Address Selection - Each QMA DPV11 is assigned four consecutive addresses that are decoded
to generate control signals to enable five registers in the DPV11. Four addresses are able to access five
registers because two of the registers (RDSR and PCSAR) share the same address. RDSR is a read-only
- register and PCSAR is a write-only register. Refer to Chapter 2 for address assignments.

When the software communicates with the QMA DPV11, it does so by placing the address of the register

it wishes to access and the necessary control signals on the LSI-11 bus. The DPV11 checks the address to
see if it is within the range assigned to it. If so, access to the register is allowed. Paragraphs 4.3.1.2 through
4.3.1.4 describe the decoding of the address.

4.3.1.2 Address Decode — Address decoding is accomplished in the DCOO0S5 chips where a comparison
is made of the BDALO3 through BDAL12 lines with the states selected by the address jumpers W29
through W39. (Refer to Chapter 2 for address selection and jumper connections). Each DC005 chip
looks at three address lines and compares each of them against a corresponding jumper connection.
When each address line agrees with its jumper input, the DCO0O0S5 asserts pin 3 high. If all four DCO005
chips have pin 3 asserted, the address on the bus is within the range assigned to this DPV11. When this
condition exists, the register decode circuit is enabled to allow access to the specific register being
addressed. Notice that BDALQO through BDALO2 are not used in the address compare. Line zero is
used in byte selection and lines one and two are used to select a particular register. Register selection
and byte operation are discussed in Paragraph 4.3.2.

4.3.1.3 Bus Data Transfers — Once the address has been accepted and access to the selected register
has been granted, data transfers can take place on the bus. The DCO00S5 chips handle this function too.
Consider first the operation in which the processor is sending data to a register in the DPV11. In this
case, the DC00Ss would be placed in receive mode by a high on pin 4. This is a result of control signals
placed on the bus by the processor. In the receive mode, data on the BDALO through BDALI1S lines is
passed through the DC005 and made available to the register on the DAOQ through DA15 lines.
When the processor is requesting information from one of the QMA DPV11 registers, the DC005s are

placed in transmit mode by a high on pin 5. In the transmit mode, data from the selected register is
presented to the DC005s on the DAO through DA15 lines. The DCO005s then pass this data to the bus on
the BDALO through BDALI1S lines.

4.3.1.4 Vector Generation — A third function of the DC00S chips is vector generation. This is accomplished by daisy-chain strapping W40 through W45 to W46 in the proper configuration for the vector
address desired. Refer to Chapter 2 for information on vector assignments and jumper connections.
W46 is high when the vector is to be sent to the processor. The signal VECTOR H is asserted by the
interrupt logic during an interrupt sequence. W45 corresponds to BDAL3 and W43 corresponds to
BDALS.
4.3.2

Read/Write Control Logic

The read /write control logic contains circuits for controlling register decoding, USYNRT operations,
and BRPLY. A description of each follows.
4.3.2.1 Register Decode (Figure 4-3) — The selection
of individual registers within the QMA DPV11 is
accomplished by a DC004 protocol chip and its associated logic. This circuit is enabled by an address
match from the DC00S5s. When enabled, the DC004 decodes address lines 1 and 2 to produce one of four
select signals. These select lines, however, do not directly select the registers. Two registers share the same
address; one is a read-only and the other is a write-only register. One entire register and the low byte of
another are external to the USYNRT. For these reasons, additional gates are used with the select lines to
properly select the one register in five to be accessed. These gates use byte and write signals to aid in the
register selection. Table 4-1 shows the register selection based on the three low-order address bits.

NOTE
|
All registers can be accessed in either word or byte
mode. However, reading either byte of the RXCSR
resets certain status bits in both bytes.

4-6

Reading either byte of the RDSR resets data and
certain status bits in both bytes of this register as
well as bits 7 and 10 of the RXCSR.
NOTE

The address inputs to the DCO004 are inverted,
thereby causing a reverse order on the select lines.
Pin 17 corresponds to select 0 and pin 14 corresponds to select 6. This applies also to the OUTLB
(pin 13) and OUTHB (pin 12).

4.3.2.2 USYNRT Control - Most of the control signals for the USYNRT are generated by the
DCO004 and its associated logic. This paragraph describes the control signals and their functions.
ADRO, ADR1, and ADR2 are used to select a register within the USYNRT. They are encoded as
shown in Table 4-2. ADRO is used in conjunction with BYTE OP to select a byte.

WRITE USYNRT is used to control writing into or reading from registers within the USYNRT.
When it is asserted, a write operation is indicated. When it is not asserted, a read operation is indicated. WRITE USYNRT is generated by ORing the OUTLB and OUTHB signals from the DCO004.
OUTLB and OUTHB are used to write data into the low byte, high byte or both bytes of a selected
register. They are generated by the DC004 in response to the bus signals BWTBT, BDOUT, and
BDALO. OUTLB and OUTHB do not directly control byte selection for the USYNRT but are used to
generate ADRO and BYTE OP.

BYTE OP is used to indicate to the USYNRT that a byte operation is to be performed on the selected
register. It is generated during a write operation when either OUTLB or OUTHB but not both are
asserted.

DPENA (Data Port Enabled) is used to enable the tri-state data bus of the USYNRT and supply the
necessary timing for transactions between the USYNRT and the external circuits. DPENA strobes the
data for write or read operations. It is generated from the register select signals and the output of pin 8
of the DC004 chip which results directly from BDIN or BDOUT. Deskew delay is accomplished by
using a 74L.S164 serial to parallel shift register. Pin 8 of the DC004 is used as the serial input to the
shift register which is clocked by a 100 ns clock. Initially the serial input is high and the shift register
outputs are all high. 100 to 200 ns after the serial in goes low, DPENA becomes asserted to strobe the
USYNRT. DPENA remains asserted for at least 300 ns as determined by pin 10 of the shift register.
For read operations, DPENA will remain asserted until BDIN becomes not asserted. This is to ensure
that the data is on the bus when the processor strobes it. For write operations DPENA will be asserted
for 300 ns.

BRPLY (Bus Reply) indicates to the processor that the QMA DPV11 has placed data on the bus or has
received data from the bus. It is generated from the same circuit as DPENA and is asserted 300 ns after
DPENA. BRPLY remains asserted until the processor responds by negating BDIN or BDOUT.

Figure 4-4 shows the timing for the generation of DPENA and BRPLY for a read operation. Figure 4-5
shows the timing for a write operation.

4.3.3

USYNRT, RXCSR, and PCSCR

Most of the registers used in the QMA DPV11 are contained within the USYNRT. The receive control
and status register (RXCSR) and the low byte of the parameter control and character length register
(PCSCR) are external to the USYNRT. The USYNRT and the external registers are discussed in
Paragraphs 4.3.3.1 through 4.3.3.3.

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Table 4-1

0
0
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1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
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RXCSR (high byte)
RDSR (read) or PCSAR (write)
RDSR or PCSAR (high byte)
PCSCR (word or low byte)
PCSCR (high byte)
TDSR (word or low byte)
TDSR (high byte)

Table 4-2

B SYNCL
REGISTER

SELECT

BDIN L

USYNRT Register Select

ADR2

ADR1

0
0
1
1

0
1
0
1

RDSR (read only)
TDSR
PCSAR (write only)
PCSCR (high byte)

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4-9

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4.3.3.1
USYNRT - The universal synchronous receiver/transmitter (USYNRT) functions as a large
scale integration (LSI) subsystem for synchronous communications. The USYNRT provides the logic
support, by means of program parameter registers, for basic protocol handling and error detection.
Protocol handling by the USYNRT conforms to standards imposed by these protocols, but is slightly
different in each version of the USYNRT. The 5025 (2112517-00) is implemented in the QMA DPV11.
For more details on the USYNRT, refer to Appendix B or to the A-PS-2112517-0-0 Purchase
Specification.

4.3.3.2 Receive Control and Status Register (RXCSR) - The RXCSR is described in detail in Chapter 3. It is a buffer and line driver consisting of two 741.S244 chips and one 74LS174 hex D flip-flop.
The low byte can be read or written into but the high byte can only be read. The write operation occurs
on the positive transition of WREGQO. The register can be read when RREGQO is asserted low.
4.3.3.3 Parameter Control and Character Length Register (PCSCR) - This register is described in
Chapter 3. Its upper byte is internal to the USYNRT and its low byte is external. Three bits (0, 3, and
4) of the low byte of this register are directly program-writable with bit zero being write-only. Bit 6 is
program writable but is a function of the interrupt circuit.

4.3.4 Interrupt Logic
Most of the logic for interrupts is contained in a single DC003 interrupt chip. The chip contains two
interrupt channels: one for receiver and modem control interrupts and one for transmitter interrupts.

The receive and modem control interrupt has the higher priority and may occur when receive interrupt
enable (RX INT ENA) is set and any of the following signals become asserted.
Receive Data Ready (RDATRY)
Receive Status Ready (RSTARY)
Data Set Change (DAT SET CH)

Notice that DAT SET CH requires that MC INT ENA (RXCSR bit 5) also be asserted.

4-10

When a register in the receive section (RXCSR or RDSR) is accessed; i.e., when servicing a receive
interrupt request, the receive interrupt request is disabled for 600 ns by the output on pin 5 of the
741L.S74 flip-flop. This is done to ensure that any modem control interrupt request that might have
occurred while servicing the receive interrupt request, is recognized. When the flip-flop is reset by the
600 ns signal, a negative to positive transition is recognized on pin 17 of the DC003 if a modem control
interrupt request is present.

A transmitter interrupt is generated by the DC003 if the TBEMTY signal is asserted when transmitter

interrupt enable (bit 6 of PCSCR) is set.

Both the TX INT ENA and RX INT ENA bits are located physically in the DC003 interrupt chip
although they are functionally part of the PCSCR and RXCSR respectively.
The bus interrupt request (BIRQ) is asserted by the DCO003 for either a receive or transmit interrupt
request. The processor responds to BIRQ by asserting BIAKI and BDIN. BIAKI is the interrupt acknowledge signal. It is passed down the priority chain until it reaches the section of the interrupt chip
that initiated the request.

When the interrupt logic receives both BDIN and BIAKI, it asserts the signal VECTOR. VECTOR
enables the assertion of the vector address by the DS00S5s. If the interrupt is a transmitter interrupt,

the RQSTB signal would assert vector address bit 2.

Data Set Change Circuit (Transition Detector)

4.3.5

The data set change circuit consists of a 74LS273 D-register, exclusive NOR gates and two flip-flops.
Setting of the Data Set Change bit (DAT SET CH) is determined by the configuration of jumpers
W24 through W28. Any or all of the following modem signals can set DAT SET CH if its associated

jumper is installed.

RS-232-C

RS-449

Clear to Send (CTS)

Carrier Detect (CD)

Receiver Ready (RR)

Data Set Ready (DSR)

Data Mode (DM)

Ring Indicator (RI)

Incoming Call (IC)
NOTE

The modem change circuit interprets any pulse of
two microseconds or greater duration as a modem
status change. This ensures that all legitimate
modem status changes are detected. However, on a
poor line, noise may be interpreted as a modem status change. Software written for the QMA DPV11
must account for this possibility.
4.3.6

Clock Circuit

The clock circuit consists of an off-the-shelf 19.6608 MHz crystal oscillator, and two 74LS390
counters. The 19.6608 MHz signal is divided by the counter circuits to produce the following four
clock signals.

LOCAL CLK (49.152 kHz) — Normally jumpered to NULL MODEM CLK (W18 and

W21) and used as the data clock.

4-11

DIAG CLK (1.9661 kHz)— Nonsymmetrical clock available for diagnostic purposes (nut
recommended for local communications). It becomes the transmit clock when the DPV11 is
placedin diagnostic mode. DIAG CLK can also be jumpered to LOCAL CLK for 50 kHz
opcratwn but some of the tests must be omitted.

SR CLK (9. 8304 MHz) Used to clock the shift register to establish delays for DPENA
and BRPLY.

Charge PUMP CLK (491.52 kHz) — Used by the charge pump circuit and transition detector.

4.3.7 USYNRT Timing - USYNRT timing for the transmit and receive sections originates with the
modem and is gated through the AND-OR inverter to the USYNRT.

During normal receive data transfers, the 74L.S51 gates receiver timing from the modem as receive
clock pulse (RCP) to the USYNRT. If the modem clock stops with the last valid data bit, Receiver
Rcady becomes not asserted. The next positive transition of the NULL MODEM CLK causes 74L.S74
pin 8 to go hlgh thus substituting NULL MODEM CLK for modem receive timing. In this way, the
USYNRT receives the ncccssary 16 clock pulses to complete its operation after the modem has
stopped sending.

During normal transmit data transfers, timing for the USYNRT is gated from the modem through the
74LS51 pin 6 to the USYNRT.

In maintenance mode, the signal MSEL disables the modem timing and enables the DIAG CLK as the

clock for the USYNRT.

4.3.8 EIA Receivers
26L.S32 quad differential line receivers are used to accept signals and data from the modem. Jumpers
W12 through W17 are terminating resistors Wthh may be connected for RS-422-A but must be disconnected for RS-423-A.
4.3.9 EIA Drivers
|
‘Two types of drivers are used to send signals and data to the modem. 9638 drivers are used for RS-422‘A and 9636 drivers are used for RS-423-A.

4.3.10 Maintenance Mode
|
The USYNRT is placed in maintenance mode by setting Maintenance Mode Select (bit 3 of the
PCSCR). When this happens, the serial output of the transmit section is internally looped back as
serial input and the transmit serial output is held asserted. All clocking of both the receive and transmit sections is controlled by the transmitter clock input. This signal is derived from the 2 kHz clock as
determined by the 74L.S51 AND-OR inverter.

4-12

CHAPTER 5
MAINTENANCE
5.1

SCOPE

This chapter provides a complete maintenance procedure for the QMA DPV11 and includes a list of
required test equipment and diagnostics. The maintenance philosophy and procedures for preventive and
corrective maintenance are discussed.

5.2

TEST EQUIPMENT RECOMMENDED

Maintenance procedures for the QMA DPV11 require the test equipment and diagnostic programs listed
in Table 5-1.

Table 5-1

Test Equipment Recommended

Equipment

Manufacturer

Designation

Multimeter

Triplett or Simpson

Model 630-NA or 260 or

equivalent

Oscilloscope

Tektronix

Type 453 or equivalent

X 10 Probes (2)

Tektronix

P6008 or equivalent

Module extenders

DIGITAL

Cable turn-around

W984 (double)

DIGITAL

H3259

DIGITAL

H3260

connector

On-board test
connector

Bfeakout box

IDS

LIB kit

DIGITAL

ZJ314-RB

Document only

Document and
paper tape

ZJ314-RZ

ZJ314-RB

Paper tape only
Fiche

ZJ314-PB
|

ZJ314-FR

5-1

5.3 MAINTENANCE PHILOSOPHY
The basic approach to QMA DPV11 fault isolation is the use of stand-alone diagnostic programs and
maintenance mode features supported by the hardware.
|

Typical applications of the QMA DPV11 do not allow lengthy troubleshooting sessions; therefore, the
maintenance philosophy in the field is module swapping. The defective module is returned to the factory
for repair.

5.4 PREVENTIVE MAINTENANCE
There is no scheduled preventive maintenance for the QMA DPV11. Preventive maintenance for the
QMA DPV11 is integrated into its corresponding system preventive maintenance and consists of checking

the power supply voltage. Whenever the module or cables have been disturbed, diagnostics (specifically,
DEC/X11 and DCLT) should be run to verify proper operation.

5.5 CORRECTIVE MAINTENANCE
Since the field replaceable units are the M8020 and the cables, all diagnosis should be directed to
isolation of one of these components.

NOTE
The operating jumper configuration of the DPV11
module being serviced should be recorded prior to
any changes for maintenance purposes. This will facilitate reconfiguring the module when the service activity is complete.
5.5.1
Maintenance Mode
To aid in troubleshooting, the QMA DPV11 has a software-selectable maintenance mode that causes the

serial output of the USYNRT to be internally connected to its serial input. In the maintenance mode,
serial data from the modem is disabled and the send and receive timing from the modem are replaced with
a clock signal generated on the M8020 module. The clock rate is 2K bits/s.

The diagnostics normally operate with and without the Maintenance Mode Select (MSEL) bit set. In

this way the USYNRT chip can be isolated from the remainder of the circuitry.

5.5.2 Loopback Connectors
The cable loopback connector shipped with the QMA DPV11-M is the H3259. When it is used, this
connector is attached to the modem end of the 70-18209 cable and cabinet kit CK-DPV11-A*. No cables

or test connectors are shipped with the DPV11-M. An on-board connector (H3260) can be purchased

separately for connecting to J1 on the M8020 module. (See Paragraph 2.5 and Figure 2-4.) It provides for
the testing of all M8020 logic.

5.5.3 Diagnostics
|
QMA DPV11 diagnostics aid in the isolation process and should be run when a malfunction is indicated.
Diagnostics should also be run to verify operation after repair.

NOTE
To ensure that all M8020 logic circuits are checked,
the on-board test connector (H3260) must be used.
However, the QMA DPV11 system is not thoroughly checked unless the DIGITAL supplied cable is
also tested.
Diagnostics must be run with a cable turnaround
connector (H3259) at the modem end of the BC26L25 cable.

5-2

The following diagnostics are available to aid in the isolation and verification process.
5.5.3.1 CVDPV* Functional Diagnostic - CVDPV* is designed to verify the functionality of the
DPV11. No resolution to the chip is intended. CVDPV* is a stand-alone program that must be executed under control of the PDP-11 diagnostic supervisor (DS). Errors are reported as they occur in the
program, unless they are inhibited, and conform to the DS error report format. For information on
loading and running of the DS see Appendix A.

CVDPV* is compatible with XXDP+, ACT/SLIDE, APT or ABS. It consists of a number of tests
which function as follows.

Test No.

Description

Verifies that addressing the RXCSR does not cause a nonexistent memory trap.

Verifies that the QMA DPV11 may be prdperly initialized by a Master Clear or LSI-11

Writes and reads data pattéms into all writable bits to verify bit validi‘ty and address-

Enables and ensures that the transmitter is activated.

Verifies that TBEMTY is asserted and cleared properly for all possible conditions.

Verifies proper operation of the transmit interrupt.

Enables and ensures that the receiver is activated, and RDATRY is asserted properly.

Verifies proper operation of the receive interrrupt for the reception of data.

Verifies proper operation of RSTARY for all possible conditions.

Verifies proper operation of the receive interrupt for status.

Ensures that both transmit and receive interrupts are recognized.

Reset.

ing paths.

Verifies proper operation of all modem status bits and ensures that DSCNG is set when

a transition occurs.
13

Verifies that an interrupt is received when DSCNG is set.

Verifies that if a DSCNG occurs during a receive interrupt, it will be recognized.

15-20

Verifies proper operation with bit-oriented protocols (BOP).

21-23

Verifies proper operation with byte count-oriented protocols (BCP).

24-28

Verifies CRC and VRC functions.

Verifies maintenance mode noninterrupt data operations.

30-36

Verifies BOP data operation.

37—-40

Verifies BCP data operation.

5.3

42
43

Verifies DDCMP message protocol and message transmission.

Verifies high-speed BCP data operation.
Verifies high-speed BOP data operation.

5.5.3.2 DEC/X11 CXDPV Module - CXDPV exercises up to six consecutively addressed QMA DPV11
synchronous interfaces as they relate to the total system configuration. It is useful in determining whether
a QMA DPV11 is the failing component among other system components in a system environment. It is a
system exerciser and does not operate as a stand-alone test. It must be configured and run as part of a total
system exerciser.
The DEC/X11 System Exerciser must be run after the stand-alone diagnostic CVDPV* has been run. It
determines if the QMA DPV11 or another device adversely affects the total system operation. For more
information on DEC/X11, refer to the DEC/X11 User Manual (AC-F053B-MC) and the DEC/X11
Cross-Reference (9AC-F055C-MC).
5.5.3.3 Data Communications Link Test CVCLH* (DCLT)
- DCLT is a communications equipment
maintenance tool designed to isolate failures to the interface, the telephone communication line, or the
modem. It exercises QMA DPV11 to QMA DPV11 links.

DCLT is XXDP+ or APT compatible and runs under control of the diagnostic supervisor (DS) (see
Appendix A). It requires 24K of memory. For more information on DCLT refer to CVCLH* document AC-F582A-MC.

APPENDIX A
DIAGNOSTIC SUPERVISOR SUMMARY
A.1

INTRODUCTION

The PDP-11 diagnostic supervisor is a software package that performs the following functions.

®
®

Provides run-time support for diagnostic programs running on a PDP-11 in stand-alone mode
Provides a consistent operator interface to load and run a single diagnostic program or a
script of programs

Provides a common programmer interface for diagnostic development

Imposes a common structure upon diagnostic programs

Guarantees compatibility with various load systems such as APT, ACT, SLIDE, XXDP+,
ABS Loader

®
'A.2

Performs nondiagnostic functions for programs, such as console I1/0O, data conversion, test
sequencing, program options

VERSIONS OF THE DIAGNOSTIC SUPERVISOR

File Name

Environment

HSAA **SYS

XXDP+

HSAB **.SYS

APT

HSAC **.SYS

ACT/SLIDE

HSAD **.SYS

Paper Tape (Absolute Loader)

In the above file names, “**’’ stands for revision and patch level, such as “A0”.
A.3 LOADING AND RUNNING A SUPERVISOR DIAGNOSTIC
A supervisor-compatible* diagnostic program may be loaded and started in the normal way, using any
of the supported load systems. Using XXDP+ for example, the program CVDPVA
BIN is loaded and
started by typing .R CVDPVA.

The diagnostic and the supervisor will automatically be loaded as shown in Figure A-1 and the program started. The program types the following message.
DRS LOADED

DIAG.RUN-TIME SERVICES
CVDPV-A-0

* To determine if diagnostics are supervisor-compatible, use the List command under the‘ Setup utility (see Paragraph A.S.).

A-1

XXDP+/ DIAGNOSTIC SUPERVISOR MEMORY LAYOUT

ON A 16KW (MIN MEMORY) SYSTEM
ADDRESS

100000 (0)
XXDP+

070000
(0)

DIAGNOSTIC

SUPERVISOR
( 6KW)

040000 (0)

DIAGNOSTIC
PROGRAM

( 7.5KW)

002000
(0)

000000 (0)

MK-2216

Figure A-1

Typical XXDP+ /Diagnostic Supervisor Memory Layout

DIAGNOSTIC TESTS
UNIT IS DPV11
DR>
DR> is the prompt for the diagnostic supervisor routine. At this point a supervisor command must be
entered (the supervisor commands are listed in Paragraph A.4).

Five Steps to Run a Supervisor Diagnostic
1.

Enter Start command.

When thé prompt DR> is issued, type:
STA/PASS:1/FLAGS:HOE <CR>

The switches and flags are optional.

Enter number of units to be tesied.
The program responds to the Start command with:

# UNITS?
At this point enter the number of devices to be tested.

Answer hardware parameter questions.
After the number of devices to be tested has been entered, the program responds by asking a

number of hardware questions. The answers to these questions are used to build hardware

parameter tablesin memory. A series of questions is posed for cach device to be tested. A
“Hardware P-Table”is built for each device.

Answer software parameter questions.
When all the “Hardware P-Tables” are built, the program responds with:
CHANGE SW?

If other than the default parameters are desired for the software, type Y. If the default pa- |

rameters are desired, type N.

If you type Y, a series of software questions will be asked and the answers to these will be
entered into the “Software P-Table” in memory. The software questions will be asked only
once, regardless of the number of units to be tested.

Diagnostic execution.
After the software questions have been answered, the diagnostic begins to run.
What happens next is determined by the switch options selected with the Start command, or
errors occurring during execution of the diagnostic.

A.4

SUPERVISOR COMMANDS

The supervisor commands that may be issued in response to the DR> prompt are as follows.
®

Start — Starts a diagnostic program.
Restart — When a diagnostic has stopped and control is given back to the supervisor, this
command restarts the program from the beginning.
Continue — Allows a diagnostic to continue running from where it was stopped.
Proceed — Causes the diagnostic to resume with the next test after the one in which it halted.
Exit — Transfers control to the XXDP+ monitor.
Drop — Drops u]nits‘ spgcified until an Add or Start command is given.

Add - Adds units specified. These units must have been previously dropped.

Print — Prints out statistics if available.

Display — Displays P-Tables.

Flags — Used to change flags.

ZFLAGS - Clears flags.

All of the supervisor commands except Exit, Print, Flags, and ZFLAGS can be used with switch options.

A-3

A.4.1
Command Switches
Switch options may be used with most supervisor commands. The available switches and their function
are as follows.

./TESTS: — Used to specify the tests to be run (the default is all tests). An example of the
tests switch used with the Start command to run tests 1 through 5, 19, and 34 through 38
would be:

DR> START/TESTS : 1-5: 19 : 34-38 <CR>

./PASS: — Used to specify the number of passes for the diagnostic to run. For example:
DR> START/PASS : 1
In this example, the diagnostic would complete one pass and give control back to the superVISOT.

./EOP:
— Used to specify how many passes of the diagnostic will occur before the end of pass
message is printed (the defaultis one).

./UNITS: — Used to specify the units to be run. This switch is valid only if N was entered in
response to the CHANGE HW? question.

./FLAGS: — Used to check for conditions and modify program execution accordingly. The
conditions checked for are as follows.
:HOE —Halt an error (transfers control back to the supervisor)

:LOE - Loop on error

‘

:IER — Inhibit error reports
:IBE - Inhibit basic error information

:IXE — Inhibit extended error information
:PRI — Print errors on line printer

:PNT - Print the number of the test being executed priot to execution
:BOE - Ring bell on error

:UAM - Run in unattended mode, bypass manual intervention tests |
:ISR — Inhibit statistical reports

:IOU - Inhibit dropping of units by program
A.4.2 Control/Escape Characters Supported
‘The keyboard functions supported by the diagnostic supervisor are as follows.

CONTROL C (]C) — Returns control to the supervisor. The DR> prompt would be typed in
response to CONTROL C. This function can be typed at any time.

CONTROL Z (1Z) — Used during hardware or software dialogue to terminate the dialogue
and select default values.

CONTROL O (JO) — Disables all printouts. This is valid only during a printout.

CONTROL S (IS) — Used during a printout to temporarily freeze the printout.

CONTROL Q (1Q) — Resumes a printout after a CONTROL S.

A.5 THE SETUP UTILITY
Setup is a utility program that allows the operator to create parameters for a supervisor diagnostic
prior to execution. This is valid for either XXDP+ or ACT/SLIDE environments. Setup asks the
hardware and software questions and builds the P-Tables.

The following commands are available under Setup.
List — list supervisor diagnostics
Setup — create P-Tables
Exit — return control to the supervisor
The format for the List command is:

LIST DDN:FILE.EXT

Its function is to type the file name and creation date of the file specified if it is a revision C or later
supervisor diagnostic. If no file name is given, all revision C or later supervisor diagnostics are listed.
The default for the device is the system device, and wild cards are accepted.
The format for the Setup command is:

SETUP DDN:FILE.EXT=DDN:FILE.EXT
It reads the input file specified and prompts the operator for information to build P-Tables. An output
file is created to run in the environment specified. File names for the output and input files may be the
same. The output and input device may be the same. The default for the device is the system device
and wild cards are not accepted.

APPENDIX B

USYNRT DESCRIPTION

5025 Universal Synchronous Receiver/Transmitter (USYNRT)
The data paths of the USYNRT provide complete serialization, deserialization and buffering. Output
signals are provided to the USYNRT controller to indicate the state of the data paths, the command
fields or recognition of extended address fields. These tasks must be performed by the USYNRT controller.

The USYNRT is a 40-pin dual-in-line package (DIP). Figure B-1 is a terminal connection (identi|
fication) diagram.

Data port bits DP07:DP00 are dedicated to service four 8-bit wide registers. Bits DP15:DPO08 service

either control information or status registers. The PCSCR register is reserved. (See Figure B-2.)

Purchase Specification 2112517-0-0 provides a detailed description of the 5025 USYNRT.

TSO| 38

|RSI

|RXCLK

]

TBEMTY | 35

39 |TXCLK

TXACT|

37 |TXENA

—

TERR|

34
B

RDATRY | 06
RSTARY | 07
RXACT | 05

—

|RXENA

SYNC +| 04
ADR COMP

DP15[17

DP 14|16

23 | DPENA

DP 13115
pP12]

DP 11|13

DP 10|12

19 |ADR SEL
2

DPO9 11
DP 08|10

20 | ADR SEL
1

pp 07|24

21 |ADR SELO

DO 06| 25

22 | BYTE GP

DP 05126
DP 04}

18
40

WR
TO LSI

OLS

SEL

33 | RESET

HINES

pDP 03|28
DP 02]

|MAINT

BIDIRECTIONAL
> 1/O TRI STATE

Spot1]a0 '
.~

DPOO "?"1"")

GND

Vcc

Vpp

09'

32|

01l

NOTE: A) PIN 32 +5V POWER SUPPLY
+10% AT 100mA.

B) PIN 01 +12V POWER SUPPLY

+12

+10% AT 100mA.
C) PIN 9 = GROUND
MK-1415

Figure B-1

Terminal Connection Identification Diagram (2112517-0-0 Variation)

B-2

DP15 |

ERR
o

e
,
ASSY BIT ACCOUNT

| REOM |

RsoM

ABORT

OVER
U

OR
GA

rRo

| mo

mo |

rRo | RO | RO

DPOO

RX DATA

R/O

RDSR

TERR

TGA

| TABORT|

R/O

ADRO

TEOM | TsoMm

R/W

TX DATA

RwW

R/W

TDSR

MK-1502

Figure B-2

5025 Internal Register Bit Map (2112517-0-0 Variation) (Sheet 1 of 2)

B-3

cop

LOOP

SEC

ST‘;lP

ADRS

MODE | sync

MODE

[«

ERRTYPE SEL——»

R/O

R/0

R/O

R
TX RX SYNC

RX SEC ADRS

R/W

R/W
ADR4

«—— TS DATA LEN SEL—»{

EXADD | EXCON

}«——RX DATA LEN SEL—»

R/W

RESERVED

PCSCR

ADR 6
MK-1503

Figure B-2

5025 Internal Register Bit Map (2112517-0-0 Variation) (Sheet 2 of 2)

APPENDIX C
QMA DPV11 OPTIONS

AND CABINET KITS

C.1 INTRODUCTION
This appendix lists the various options and cabinet kits available with the QMA DPV11 serial synchronous
interface module. Also listed is information on how the various options and cabinet kits are designated, and
information on the various types of FCC bulkheads that are available with these options.

The communication option designations enable DIGITAL customers to obtain communication options that
are tailored to their particular needs. FCC regulations require that all system cabinets manufactured after
October 1, 1983 and intended for use in the United States be designed to limit electromagnetic interference (EMI). Because both shielded and unshielded cabinets exist in the field, DIGITAL provides separate
communication options for each cabinet type.
C.2 OPTION DESIGNATION CONVERSION
When former DPV11 configurations are discontinued or changed to MAINTENANCE ONLY status,

the new option designations must be used to obtain the necessary equipment. Table C-1 can be used to
determine which communication option designations to use when designing or expanding a computer
system.

Communication options may be obtained by customers either at the time a system is purchased (a factoryinstalled system option) or as an upgrade to a system existing in the field (a field upgrade).
C.2.1

Factory-Installed System Optmns

C.2.2

Fleld Upgrade Optwns

A factory-installed system option is identified by a single option designation. when this designation is
specified (see Table C-1), the appropriate module(s), cable(s), distribution panels, and hardware are
installed in the particular system being constructed.
A field upgrade is identified by two option desxgnatlons a base option designation and a cabinet kit

designation (see Table C-1).

C.2.2.1

Base Options — The base option designation specifies the electronic module(s), turnaround test

connector, and option documentation.

C.2.2.2 Cabinet Kits — The cabinet kit designation specifies the internal cable and the distribution panel.
An adapter bracket for installing the distribution panel in a non-FCC compliant cabinet may be included
in some cabinet kits for unshielded cabinets. External cables needed to connect to a modem or other
external device usually are not included.

Table C-1

Field Upgrade Options

Option

Description

QMA DPVI1I-M

M8020 module
Documentation

QMA DPVI11-AP

M8020 module
Cabinet kit CK-DPV11-A¥*
H3259 turnaround connector
Documentation

*Refer to Table C-2 for specific cabinet kit designations.

NOTES
A “P” as the second letter after the dash in the
option designation indicates that the option is
system integrated.

A single letter after the dash in the option
designation indicates that the option is a generic option (module only).

Refer to Table C-2 for specific cabinet kit
designations.

Table C-2
Kit Number

Application

CK-DPVI11-AA

EIA Compliant

CK-DPV11-A* Cabinet Kits

CPU

Contents

PDP-11/23-S

21-inch cable, 7018209 panel assembly,
and H3259 test connector

CK-DPV11-AB

EIA Compliant

MICRO 11

12-inch cable, 7018209 panel assembly,
and H3259 test connector

CK-DPV11-AC

EIA Compliant

PDP-11/23+

30-inch cable, 7018209 panel assembly,
and H3259 test connector

CK-DPVI11-A3

EIA Non-Compliant

Five

9007031-00

cable

ties,

five

9008264-00 cable mounts, one BCO3L2F cable, and one H3259 test connector

C-2

C3 OPTION CONFIGURATION SUMMARY
Communication option designations ensure that the proper cable(s), I/O connector panels, and adapter
brackets (if necessary) are shipped with each base option.
The basic designation types refer to:
e
e

System options (factory installed), and
Base options and cabinet kits (field upgrades).

System options are installed at the factory and are configured for the particular cabinet in which the option

is being installed.

Base options and cabinet kits are ordered as upgrades to systems existing in the field. A base option and
cabinet kit together make a complete field upgrade option (that is, a base option designation and a cabinet
kit designation must both be specified to obtain a complete field upgrade.)
NOTE
A field upgrade option alone does not make an
unshielded cabinet FCC compliant. Shielded
cabinets are specially constructed to limit EMIL.

QMA DPV11 CABINET KITS

There are four different cabinet kits that may be used with system-integrated QMA DPV 11 units. These
cabinet kits are listedin Table C-2.
C.5

EXTERNAL CABLES

Miscellaneous cables are used externally to a QMA DPV11 option. These cables generally are used in
other options and are listed in Table C-3.

Table C-3

Cable

Miscellaneous

Description

BC22D

A null modem cable for compliant EIA applications (P/N 17-00313-05). Female-

BC22E

An extension cable for limited modem control: compliant (P/N 17-00322-04).

BC22F

An extension cable for full modem control: compliant (P/N 17-00323-**). Male-

Female.

Male-Female.

Female.

C.6 CABINET KIT DESIGNATIONS
The characters that make up the cabinet kit number have the following meaning:
CK-DPV11-**

CABINET KIT
OPTION
INTERFACE VARIATION
VARIABLE FIELD (internal cable length)

C-3

HNITVZZOR=ITOOO®
>

Interface Variation

RS-322 with full modem control
V.35
Integral modem
RS-232 (limited modem control)

RS-422/RS-449
RS-423/RS-449
20 mA
Fiber optic
Ethernet
Multifunctional device
Generic option (module only)
Generic option (module only)
Generic option (module only)
Reserved
DECnet interface
T1 carrier interface (Telephone Company
DIGITAL carrier equipment)

Variable Field
A

Internal cable mount, 53.54 cm (21 inch), with a 7.62 ¢cm (3 inch) by 5.08 cm (2
inch) or 2.54 cm (1 inch) by 10.16 cm (4 inch) insert.

Internal cable mount, 30.48 cm (12 inch), with a 7.62 c¢m (3 inch) by 5.08 cm (2
inch) or 2.54 cm (1 inch) by 10. 16 cm (4 inch) insert.

Internal cable mount, 76.20 cm (30 inch), with a 7.62 ¢cm (3 inch)
by 5.08 cm (2
inch) or 2.54 cm (1 inch) by 10.16 cm (4 inch) insert.

Internal cable, 3.048 m (10 ft) in an H9544 shielded I/O bulkhead.

Internal cable, 2.1336 m (7 ft) in an H9544 shielded I/O bulkhead.

Internal cable, 0.9144 m (3 ft) in an H9544 shielded I/O bulkhead.

Internal cable, 3.6576 m (12 ft) in an H9544 shielded I/O bulkhead.

J-Z

Reserved

Internal cable, 3.048 m (10 ft), mounted in an H9544-SJ or 74-27292 noncompliant mounting bracket.

Internal cable, 3.048 m (10 ft), mounted in an old distribution panel (H317 type).

Internal cable, 7.62 m (25 ft), mounted in an old distribution panel or a system

4 -7

Reserved‘

8§ -0

Nonstandard. Does not fall into a commonly used category.

without a distribution panel (BC0O5C-25 to terminal).

C-4

APPENDIX D

PROGRAMMING EXAMPLES
Two examples are included in this appendix. The first is an example for bit-oriented protocols, and the
second is an example for byte count-oriented protocols.

These are only examples and are not intended for any other purpose.
NOTE
The following examples were written for the DPV11
but are valid for the QMA DPV11 as well.

D-1

DPV11

/X00/

DPV-11

DDM

FOR

BIT

ORIENTED

PROTOCOLS

.TITLE

.IDENT

DIGITAL

(C)

1980

BY
CORPORATION,

MAYNARD,

MASS.

DEVICE

DEFINE

THE

HARDWARE

DEFINE

THE

CCB

DEFINE

THE

MODEM

DEFINE

LINE-TABLE

REGISTERS

OFFSETS
CONTROL

SYMBOLS

TEMPLATE

OPERATORS

CHARACTERISTICS

DEFINED

~D.DCHR-

LINE

INDICATOR

POBB29

DC.ADR

QoC042

DC.SPS

PeRe13

DC.S55S

PoEo33

DC.SEC

geoela

DC.MPT

HALF-DUPLEX

PROTOCOL

MULTI-POINT

WMy

Aeeea7

MULTI-POINT SECONDARY MODE

00uoal

STATION

DC.HDX
DC.PRT

SDLC

PRIMARY

CCBDFS
MDCDF$
TMPDFS
DEVICE

SDLC

SECONDARY

SELECTION

(WORD

FIELD

CONFIGURATION

ADDRESS

#0)

(WORD

#1)

(WORD

#1)

(WORD

#1)

(WCRD

#1)

BITS

STATION

(COMPOSITE)

STATION

(COMPOSITE)

DEVICE

STATUS

201
2
oo

CF.EOM

DD.SOM

CF.SOM

DD.ABT

(I
|I
| I
o

DD.ENB
DD.STR

DD.EOM

DD.SYN

DD.TRN
DD.ACT

DD.DIS

FLAGS

p20
CF.SYN

CF.TRN
200
DD.ENB!DD.ST

m‘t Tsg WE e WE WE TME Wy

DEFINED

ZERO,

LINE

HAS

BEEN

ENABLED

ZERO,

LINE

HAS

BEEN

STARTED

-—(UNUSED—)

-—- (UNUSED)
-TRANSMIT

ABORTED

TRANSMIT

SYNC-TRAIN

TRANSMIT

LINE

TRANSMITTER
;

INITIAL

DUE

UNDERRUN

REQUIRED

TURN-AROUND

READY

STATUS

FOR
=

REQUIRED

FRAME

DISABLED,

STOPPED

[

SEL
0 ]

-—

MODEM

CONTROL

BITS

wmy
s
wy
Ty
Tmay
WMe

gegLal

PoRee2

MODEM
DATA

wMe

- pPooo4

CLEAR

CARRIER

DATA

0egole

SET

INDICATOR

REQUEST

YwWE

DSSEL

goRa40

01000

DATA
RING

DATA

DSDTR

| A

DSRTS

| AN |

DSLOOP

DSITEN

DSMODR

P28000

210020

1IN

DSCTS
DSCARY

1020040
240000

DSRING

| I

DSCHG

SELECT

CHANGE
SEND

INDICATOR

READY
SET

INTERRUPT

SET

LOOPBACK
TO

ENABLE

SEND

TERMINAL

READY

FREQUENCY

REMOTE

LOOPBACK

SEL

]

RECEIVER

CONTROL

BITS

s
e
wmyg
wmsg

0B0200
0Re1a0
200020

RECEIVER

INTERRUPT

RECEIVER

ENABLE

ACTIVE

STATUS
FLAG

DONE

READY

DETECT

ENABLE

RXREN

pep4o09

RECEIVER

RXDONE

RXITEN

004000
002009

RXFLAG

RXACT

RXSRDY

]

-—

RECEIVER

STATUS

INPUTS

CRC

04000

RECEIVER

ASSEMBLED

RXOVRN

1000080

27000¢
212000

RECEIVER

BUFFER

RXBFOV

RXERR
RXABC

|I |

SEL

DRIVER

HWDDF$,$INTSX,$INTXT,MDCDF$,CCBDF$,TMPDFS,ASYRET,SYNRET

HWDDFS$

.MCALL

OF AN APPLICATION RSX-11M BIT ORIENTED DPV-11
*** NOTE - THIS IS NOT A RUNNING DRIVER

EXAMPLE

EQUIPMENT

RECEIVER

DATA

ERROR

BIT

OVERRUN

D-2

COUNT

OVERFLOW

(SOFTWARE

ERROR)

RXABRT

002000

;

RECEIVED ABORT

RXENDM
RXSTRM

=
=

001000
000400

;
;

RECEIVED END OF MESSAGE
RECEIVED START OF MESSAGE

;

[

DPAPA
DPDECM
DPSTRP
DPSECS
DPIDLE
DPCRC
DPADRC
INPRM

=
=
=
=
=
=
=
=

;

SEL

TCLEN
EXADD
EXCON

]

MODE CONTROL OUTPUTS

190000
Q40000
020000
010000
004000
3%490
Q00377
DPSTRP!DPCRC

SEL 4

[

;

=--

]

;
;
;
;
;
;
;
;

ALL PARTIES ADDRESSED
DDCMP / BISYNC OPERATION
STRIP SYNC OR LOOP MODE
SDLC / ADCCP SECONDARY STATION SELECT
IDLE MODE SELECT
USE CRC 16 ERROR DETECTION
STATION ADDRESS OR SYNC CHARACTER
INITIAL STARTUP PARAMETERS

TRANSMITTER STATUS AND CONTROL

=
=
=

(10009

004000

s+
;
;

TRANSMIT CHARACTER LENGTH
EXTENDED ADDRESS FIELD
EXTENDED CONTROL FIELD

=
=
=
=

(03400
000100
000020
000010

;
:
;
;

RECEIVE CHARACTER LENGTH
TRANSMITTER INTERRUPT ENABLE
TRANSMITTER ENABLE
MAINTENANCE MODE SELECT

TXDONE

(¢godo4

;

TRANSMITTER

TXACT

gopon2

;

TRANSMITTER ACTIVE

TXRES

0000l

DEVICE

RCLEN
TXITEN
TXREN
TXMAI

150000

DONE

RESET
|

;

[

;

SEL

]

TRANSMITTER OUTPUT CONTROLS

TXLATE

100000

;

TRANSMITTER DATA LATE

TXGO
TXABRT
TXENDM

=
=
=

@P4000
002000
@01000

;
;
;

TRANSMITTER GO AHEAD
TRANSMITTER ABORT
TRANSMIT END OF MESSAGE

(UNDERRUN)

TXSTRM

@2Q@400

TRANSMIT START OF MESSAGE

;

PROCESS

DISPATCH

;

SDXPTB: :

TABLE

|
.WORD
.WORD

$SDASX
$SDASR

;
;

.WORD

SSDKIL

;

-WORD

$SDCTL

;

.WORD

$SDTIM

;

.SBTTL

SSDPRI

TRANSMIT ENABLE
RECEIVE
ENABLE
KILL I/O ENABLE
CONTROL ENABLE
TIME OUT

RECEIVE

INTERRUPT

(ASSIGN BUFFER)

SERVICE

ROUTINE

; +

;

FUNCTION:

’

;

THE

;

CALLING

;

DEVICE

INTERRUPT

IS VECTORED BY THE

DEVICE LINE TABLE. THE 'S$SDPRI'
SEQUENCE

HARDWARE TO THE

LABEL IS ENTERED VIA A

IN THE LINE TABLE AT OFFSET

'D.RXIN'.

ENTRY:

;

H
;
H

@ (SP)
2(SP)
4 (SP)

= ADDRESS OF 'D.RDBF'

IN THE LINE TABLE

= SAVED RS
= INTERRUPTED PC
= INTERRUPTED PS

;

OUTPUTS:

;

R5 = ADDRESS OF
D.RVAD =

'D.RDB2'

RECEIVER STATUS

IN THE LINE TABLE

BITS

FROM CSR

D-3

[SEL

REGISTERS

Wme

Wwe

@ (R5)+,
R4
# RXABC,
R4

MOV
BIC

SAVE

GET

R4 ,- (SP)

R3,-(SP)

MOV
MOV

SSDPRI::

DON'T WORRY

CHARACTER

AND

FLAGS

ABOUT

ASSEMBLED

BIT

COUNT

(R5) +,KISARG

KISAR6,- (SP)

SAVE
MAP

MOV
MOV

.IF DF MS$SMGE
CURRENT
TO

DATA

MAP
BUFFER

we
WS

s
a1l

R4,@ (R5) +

MOVB

DPRCP

BNE

GET

#RXSRDY,
- (R3)

ERROR

YES

POST

CSR+2

BYTE

COUNT

POST

COMPLETE

ADDRESS
END-OF-MESSAGE

RECEIVE

2(R5) ,R3.

BIT

BUFFER

OVERFLOW

STORE

RESTORE
Wy

MOV

DECREMENT

BUFFER

ADVANCE

BUFFER

DPRBO

+
(R5)

BMI

wmg

DEC

-—e

LIFTF

CHARACTER

RESTORE

REGISTERS

COMPLETE

RECEIVE

BUFFER

JIFT

(SP)+,KISAR6

MOV

MAPPING

- (R5)
(SP) +,R4

WwE

MOV

(SP)+,R3

wmy

wmp
e
-

BUFFER

SET

END-OF-MESSAGE

|
e ]

ADDR

RECEIVER

RESTORE

WMy

WMe

OCCURRED

INDICATOR

ERROR

STATUS FLAGS
CSR+2

AND

CLEAR

WME

SAVE
GET

HAS

ERROR

INDICATION

DO A TRICKY

'D.RVAD'

POINT

INTERRUPT

'SINTSV'

'D.RPRI'’
ENABLE

HAPPY

SINTSV

(R5

SAVED BUT NOT

R4)

CHECK

FOR

ERRORS,

POST

RECEIVE

COMPLETE,

ASSIGN

NEW

BUFFER

BIC

#61777, (R5) +

TME
Mg
WE
e

Wws

Wmae

Wy
WE

D.RABT-D.RDB2
(R5

409

INC

BCC

RCVERR-2
(R3) ,R3

TMI

MOV

USE

COMPUTE
SET

PLACES

FRAME

CCB

NOT

RBFUSE

RE-INITIALIZE

605

RE-ENABLE

BIS

,R3
C.STS(R4)

MOV

R3,-(SP)

CALL

RBFSET

mgy

INCLUDE

STATUS
RECEIVE

wyg

(SP) +,R3

POST

RECOVER
ASSIGN

INDEX

- POST
THE

COMPLETE

FRAMES
SAME

FOR

STATUS,

REPORTED

BUFFER

NEXT
IF

ANY

DLC

COMPLETE

COMPLETION

D-4

O.K.

FLAGS

ABORTED

WITH

RE-SYNC

NEW

STATUS

C-BIT

TABLE

INTERRUPTS

SAVE

SDDRCP

COUNT

BYTE

COMPLETE

INTO
AS

ABORTED

NUMBER

CALL

FRAME

COMPLETION

STATUS

MOV

POPPED)

DUAL

RIGHT

INDICATORS

;COUNT

RESI

RECEIVED
FOR

INDICATORS...

'RXABRT'

THE

RECEIVE

ERROR

NOW

REPORTED

POST

-y

(R5)+,R3

BACK

ERRORS

AN ADDITIONAL
ADDRESS

MOVB

..+ TWO

SHIFT

+
(R5)

- (R53)

ASR
ASRB

SHIFT

WME

- (R5)

ASR

ANY

499

e’ Wy

BEQ

wmy

CLR

SUB

1#[)0 cm:bqqp""[)mvFz(:(:EB'-PzE;
(R5)+,C.CNT1
(R4)

ADD

SAVE
CCB

-~y

(R5) ,R4

R3,-(SP)

40S:

MOV

MOV
SINTSX

R4, (R5) +
(R5)+,R4
- (R4)
$RXITEN,
(SP)+,R4
(SP)+,R3

MOV

.ENDC

MOV
BIC
MOV

OVERRUN

(SOFTWARE)

RESTORE PREVIOUS MAPPING

(SP)+,KISAR6G

MOV

LIFT

ADDRESS

INTERRUPT

e
wmy

LT )

DPRCP:

THE

#RXBFOV,
R4

BIS

DPRBO:

EXIT

SINTXT

INC
MOV

LIFTF

CCB

STATUS
THE

RECEIVER

FRAME

COUNT

605:
-

DREXIT
R3
DRCLRA

MOV

-(R5) ,R3

:+: YES - DISABLE RCVR FOR RE-SYNC

$RXITEN, - (R3)

BIS

DREXIT:

FAILED - LEAVE RECEIVER INACTIVE
. WAS AN ERROR REPORTED TO DLC 2

BCS
TST
BMI

(SP)+,R3

MOV

;s RECEIVER CSR [SEL 2] TO R3

RE-ENABLE RECEIVER INTERRUPTS
v
|

:+ RESTORE REGISTER R3

;;

RETURN

EXIT TO THE SYSTEM

; +

DRCLRA:

;

MOMENTARILY RESET 'RXREN' FLAG IN ORDER TO FORCE RECEIVER
THIS IS REQUIRED FOR ANY ERROR WHICH
RE-SYNCHRONIZATION.
TERMINATES THE RECEIVE OPERATION IN MID-FRAME.

;
;
;
H

ENTRY:

'D.RCCB'

RS = ADDRESS OF

;

(SP)= SAVED R3 VALUE

IN THE LINE TABLE

R4 = ADDRESS OF 'C.STS' IN THE NEWLY-ASSIGNED CCB

;

DRCLRA:

MOV
BIC

-(R5) ,R3
#RXREN, - (R3)

:: RCVR CSR ADDRESS [SEL 2] TO R3
.» RESET RCVR ENABLE FOR RE-SYNC

BIS
BR

#RXREN!RXITEN, (R3)
DREXIT

s RE-ENABLE THE RECEIVER
;s RESTORE R3 AND EXIT

_SBTTL

$SDPTI

#CS.RSN, (R4)

BIS

:s SET RE-SYNC IN CCB 'C.STS'

TRANSMIT INTERRUPT SERVICE ROUTINE

FUNCTION:

THE DEVICE INTERRUPT IS VECTORED BY THE HARDWARE TO THE

DEVICE LINE TABLE. THE 'S$SDPTI' LABEL IS ENTERED VIA A

CALLING SEQUENCE IN THE LINE TABLE AT OFFSET 'D.TXIN'.
ONCE FRAME TRANSMISSION IS INITIATED, EACH INTERRUPT IS
HANDLED BY THE ROUTINE ADDRESSED VIA THE 'D.TSPA' WORD.

;
;

;

ENTRY:

;

g (SP)

= SAVED R5

2(SP) = INTERRUPTED PC
4(SP) = INTERRUPTED PS

;
;
H

= ADDRESS OF 'D.TCSR' IN THE LINE TABLE

EXIT:

;

R5 = ADDRESS OF 'D.TCCB' IN THE LINE TABLE

;-—u

SSDPTI::

;

R4 ,-(SP)

MOV

MOV
TST
JMP

(R5) +, R4
(R4) +
@ (R5) +
B

CURRENT STATE =

;;; SAVE R4

::; GET TRANSMITTER CSR ADDRESS
::: POINT TO [SEL 6] + TEST UNDERRUN
s:; GO TO CORRECT STATE PROCESSOR
-

-H

MONITOR CSR FOR 'CLEAR TO SEND'

;

;””““““””““”“““““”“““” ””””””””””” M

TISCTS:

BIT
BNE
BITB
BEQ

#DSCTS,-6 (R4)
TISIFL
4DD.SYN,D.FLAG-D.TCNT(R5)
TISIFX

D-5

ss: IS 'CLEAR TO SEND' ACTIVE YET ?
::: YES - START TO SEND THE FRAME
;;; SYNC-TRAIN REQUIRED ?
;:; NO —— SEND FLAGS UNTIL 'CTS'

;

MOV

#TXSTRM!

TISEXT

TXENDM, (R4)

;77

START

END

SENDS

SYNC

mmmmmmmmmmmmmmmmmm

mmmmmmmmmmmmmmmm

CURRENT

STATE

SEND

INITIAL

FRAME

STRING

;‘

'FLAG'

;

e
S A T
T
I
;

TISIFL:

’

MOV

‘

#TISTRT,*(RS)

;;:;

STATE

MOV

#TXSTRM, (R4)

;::

SEND

TISEXT

TISIFX:

SEND

ADDRESS

SDLC

FLAG

CHARACTER

BYTE

e
e
;
H
CURRENT STATE =
SEND ADDR EYTE FOLLOWING
'FLAG‘
:
1=

TISTRT*

DEC
MOV

MOV

D.TADC-D.TCNT(RS5) , (R4)
#TISDAT,- (R5)

TISEXT

,
(R5)

CURRENT

STATE

;7:

DECREMENT

;+:

SEND

ADDR,

CLEAR

:::;

STATE

COUNT

FOR

;

ADDR

BYTE

'TXSTRM'

DATA

TRANSFER

FRAME

DATA

BYTES

TISDAT*

BMI

TISLAT

DEC

(R5) +

BMI

TISEND

UNDERRUN
DECREMENT

ALL

;::;

SAVE

;i:;

MAP TO THE

.IF DF MS$SSMGE
MOV

;7
:7;

ABORT
DATA

AND

BYTE

SEND

RE-TRANSMIT
COUNT

END-MSG

SEQUENCE

KISAR6,~(SP)

MOV

DONE

(RS)+,KISARG6

.IFTF

CURRENT

-INC

(R5)

;:;

ADVANCE

MOVB

@ (R5)+, (R4)

;73

MOV

(SP)+,KISARG6

RESTORE

::;

COMMON

MOV

(SP)+,R4

;::;

RESTORE

:3:;

EXIT

«1FT

TISEXT:

SINTXT

MAPPING

TRANSMIT BUFFER

THE

BUFFER

CHARACTER

LEVEL-7

ADDRESS

SENT

MAPPING

INTERRUPT

EXIT

INTERRUPT

SERVICE

i
i
e
;
H

CURRENT

STATE

DATA

BYTE- COUNT

EXHAUSTED

;

TISEND*

MOV

#TXENDM, (Rd)

INC

;+:

TRANSMIT

- (R5)

MOV

+3:;

ADJUST

#TISFLG, - (R5)

ASLB

:+¢+

D.FLAG-D.TSPA (R5)

;:;

STATE

TEST

FOR

IDLE

LINE

773

#TISPAD, (R5)

-——

IDLE

THE

;73

YES

SEND

TISEXT

PADS,

=
T

SEND
s

LINE

PAD
e

FLAGS

DISABLE

;

AFTER
e

(ASSUMED)

WITH

THEN

'ABORT'
e

'D.TCNT!

FLAGS

TURN-AROUND

TISEXT

STATE

SEQUENCE

CLEAR

BPL

CURRENT

TISPAD:

AND

MOV

e
;

END-OF-MSG

'FLAG?;
e

- ;

CLRB

D.FLAG-D.TCNT(R5)

::;:;

MOV

#TISCLR,- (R5)

MOV

;33 NEXT

#TXABRT, (R4)

TISEXT

RESET

SET

THE

STATE

DEVICE

'"TXABRT'

FLAG

SEND

BYTE

SECOND

SEND

PAD

e
e e
T
R I
;

;

CURRENT

STATE

SEND

SECOND

‘ABORT'

mmmmmmmmmmmm

TISCLR:

MOV

PAD

mmmmmmmmmmmm

#TISRTS
- (R5)
,

mmmmmmmmm

i i;

STATE

DROP

'REQUEST

;

SEND'

TISCLX:

MOV

$ TXABRT, (R4)

;;;

SETUP TO SEND ANOTHER 'ABORT'

BIC

#TXREN, - (R4)

;::

DISABLE

TISEXT

A
TISRTS:

== -=-=-==-=-=-==-"= -- H

STATE

DROP

REQUEST

SEND

EXIT

;

#DC.HDX,D.DCHR-D.TCNT(R5)
TISDON
|
#DSRTS, -6 (R4)

;;;
::;
;:;;

HALF-DUPLEX CHANNEL ?
NO —— LEAVE 'RTS' ACTIVE
DROP 'REQUEST TO SEND' LINE

TISDON

:s;

POST TRANSMIT COMPLETE

CURRENT STATE =

CHAR

TRANSMITTER

BIT
BEQ
BIC

e
TISLAT:

;

CURRENT

THE

TRANSMITTER DATA UNDERRUN

;

e H

MOV

$#TISDON, - (R5)

;:: NEXT STATE = RE-TRANSMIT

MOVB

#DD.ABT,D.FLAG-D.TSPA(R5)

;;;

INC
BR

D.TURN-D.TSPA(R5)
TISCLX

::: COUNT THE ERROR EVENTS
;s: SEND PAD, DISABLE TRANSMITTER

FRAME WAS

ABORTED

e,
-’

CURRENT STATE

THIS

IDLE FLAGS

BETWEEN

FRAMES

;

=== ;

TISFLG:

MOV
MOVB

$TXSTRM, (R4)
#DD.ACT,D.FLAG-D.TCNT(R5)

;3
;;;

CLEAR 'TXENDM', IDLE FLAGS
TRANSMITTER IS ACTIVE

; mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm

CURRENT STATE

T
T
TISDON:

ADD
BIC
MOV

=
e

POST COMPLETE
-

#D.TPRI-D.TCNT,R5
#TXITEN,- (R4)
(SP) +, R4

SINTSX

;;;
;;;
:::;

ADJUST LINE TABLE POINTER
DISABLE 'TXDONE' INTERRUPTS
RESTORE R4 FOR PRIORITY DROP

;::

'"SINTSV'

W/0 R4

(POPS

R3,-(SP)

;;

SAVE

(R5) ,R4
(R5) +

::
;:

ACTIVE CCB ADDRESS TO R4
THIS CCB IS NO LONGER ACTIVE

BITB
BNE
TST

$DD.ABT,D.FLAG-D.TCBQ(R5)
TRSTRT

;;
;:
::

WAS THE FRAME ABORTED ?
YES
- SETUP RE-TRANSMISSION
TRANSMIT KILL IN PROGRESS ?

BNE

CKILLT

YES

CLR

CALL
MOV

SDDXMP
(R5) ,R4

FIRST CCB

BEQ

TREXIT

;;

NONE

MOV

(R4) , (RS)

;;

REMOVE

;;

SET

COMPLETION

ADDITIONAL

R5)

MOV

D.KCCB-D.TCBQ (R5)

SAVED

MOV
CLR

Hla

;

OR RE-TRANSMIT

-H

RETURN
STATUS

CCB'S
=

TO THE

POST TRANSMIT COMPLETE TO THE
ON SECONDARY CHAIN
THERE

CCB

TRANSMITTER

FROM

DLC

SUCCESS

SECONDARY

DLC

IDLE

CHAIN

-e H

CURRENT
e

STATE

START

FRAME

TRANSMISSION

;

e H

TRSTRT:
CLR

(R4)

;

MOV

R4 ,- (R5S)

TST

- (R5)

SKIP

BACK

ADD

$C.FLG1,R4

POINT

(R4),D.FLAG-D.TPRI(R5)

;;

SAVE

FLAGS

BICB

$DD.ABT,D.FLAG-D.TPRI
(R5)

;MAKE

SURE

MOV
CLR
MOV

-(R4) ,D.TCNT-D.TPRI(R5)
- (R5)
-(R4) ,-(R5)

BISB

;

;;
;;
;:

CLEAR

CCB

LINKAGE

WORD

SETUP AS THE ACTIVE CCB
OVER
THE

'D.TPRI'

CCB

FOR

BUFFER

LEVEL-7

'ABORT'

FLAG

FLAGS

USE

OFF

SET TRANSMIT BYTE COUNT
INITIALIZE 'D.TADC' WORD
SET TRANSMIT BUFFER ADDRESS

.IF

M$SMGE

MOV

-(R4) ,- (R5)

;;

SET

MOV

KISAR6,- (SP)

;;

SAVE

TRANSMIT

MOV

(R5) +,KISARG

MAP

MOVB

@ (R5) +, (R5)

;; MOVE

MOV

(SP)+,KISAR6

;; RESTORE

THE
TO

BUFFER

CURRENT

THE

RELOCATION

APR6

TRANSMIT

MAPPING

BUFFER

.IFTF
ADDRESS

BYTE

'D.TADC'

APR6

MAPPING

PROCESSOR

LIFT
.ENDC

20%:

40$:

ADD

#D.TSPA-D.TADC,R5

;;

BACK

TSTB

D.FLAG-D.TSPA(R5)

THE

STATE

BPL

209

;;

—-

MOV

#TISTRT, (R5)

;;

INITIAL

40%

;;

ENABLE

MOV

-2(R5) ,R3

;; TRANSMITTER CSR

[SEL

BIS

#DSRTS,-4 (R3)

;;

ASSERT

'REQUEST

BIS

BTXREN, (R3) +

;;

ENABLE

THE

MOV

$TISCTS, (R5)

;;

INITIAL

BIS

$TXITEN,@- (R5)

;; RE-ENABLE

MOV

(SP) +,R3

TRANSMITTER

ENABLE

IT,

STATE

READY

THEN
SEND

INTERRUPTS

CELL

NOW

START
ADDR

AND

BYTE

EXIT

TO R3

SEND'

TRANSMITTER

STATE

WAIT

TRANSMIT

FOR

'CTS'

INTERRUPTS

TREXIT:
ASYRET

;

CURRENT

STATE

;;

RESTORE

;;

EXIT

TRANSMIT

KILL

FROM

WHEREVER

ENTRY

APPROPRIATE,

TIMEOUT

;

R T
e
;

CKILLT:

MOV

#CS.ERR!CS.ABO,-(SP)

;; TRANSMIT

COMPLETION

STATUS

CKTTMO:

20$:

#TXREN,@D.TCSR-D.TCBQ(R5)
(R5) , (R4)

; ;

ADD

;;

DISABLE

CLR

(R5) +

;;

CLEAR

MOV

(SP) ,R3

;;

COMPLETION

MOV

(R4) ,- (SP)

;;

CCB

ADDRESS

CLR

(R4)

; ;

MAKE

SURE

LINK

CALL

$DDXMP

;;

POST A

SECONDARY

MOV

(SP) +, R4

;;

CCB

BNE

;;

TO GO

TST

(SP) +

;;

CLEAN

CHAIN

STATUS

CCB

TRANSMITTER

CHAIN

TO
TO

WORD

PRIMARY
POINTER

R3
STACK
IS

ZERO

COMPLETE W/ERROR

ADDRESS

CONTINUE

STATUS

OFF

THE

ADDRESS

MOV

(R5) ,R4

;;

KILL

CCB

BEQ

TREXIT

;;

NONE

RESTORE

AND

CLR

(R5)

;;

KILL

LONGER

PROGRESS

CLR

;;

STATUS

R4
EXIT

SUCCESSFUL

CMPB

$FC.KIL,C.FNC(R4)

;;

KILL-I/O

BNE

403

;;

CONTROL

CALL

$DDKCP

;;

POST

TREXIT

;;

RESTORE

CONTROL

POST

KILL-I/O
R3

CALL

$DDCCP

;;

POST CONTROL

TREXIT

;;

RESTORE

.SBTTL

$SDASX

|
STACK

FUNCTION

COMPLETE

AND

EXIT

COMPLETE

AND

EXIT

TRANSMIT

ENABLE

ENTRY

(VIA THE

DISPATCH TABLE)

FUNCTION:

40$:

BIC
MOV

'$SSDASX'

ENTERED

D-8

TO QUEUE A

ASYNC

TRANSMITTING

THE

NEW FRAME.

wE
Ws

IF THE

TRANSMITTER IS BUSY, THE CCB IS QUEUED TO THE SECONDARY
IF NOT, THE TRANSMITTER IS ENABLED TO START
CCB CHAIN.

CCB CONTAINING AN SDLC FRAME TO BE TRANSMITTED.

ENTRY:

= ADDRESS OF TRANSMIT ENABLE CCB
RS = ADDRESS OF DEVICE LINE TABLE
PS = PRIORITY OF CALLING DLC PROCESS

EXIT:

ALL REGISTERS ARE UNPREDICTABLE
-

:
$SDASX:

MOV
MOV
BIC

R3,- (SP)
D.TCSR(R5)
,R3
$TXITEN, (R3)
#D.TCCB,R5

ADD

20$:

;;
;;
;;

SAVE R3 FOR EXIT VIA 'TRSTRT'
TRANSMIT CSR ADDRESS [SEL 4] TO R3
DISABLE TRANSMITTER INTERRUPTS

POINT TO ACTIVE

CCB ADDRESS CELL

TST

(R5) +

;;

IS THERE AN ACTIVE CCB ?

BEQ

TRSTRT

NO --

MOV

R4, - (SP)

;;

SAVE

MOV

RS, R4

;;

COPY THE CCB ADDRESS TO R4

BNE

20$

;;

MOV
CLR
BIS

(SP) +, (R4)
@ (R4) +
#TXITEN, (R3)

;;
;;
;;

LINK NEW CCB TO END OF CHAIN
MARK NEW END OF CCB CHAIN
RE-ENABLE TRANSMITTER INTERRUPTS

TREXIT

;;

RESTORE

.SBTTL

$SDASR

MOV

(R4) ,RS

;;

START UP

THE

TRANSMITTER

POINTER TO FIRST CCB

ADDRESS

OF THE NEXT CCB TO RS
LOOP UNTIL WE FIND THE END

R3 AND

EXIT

RECEIVE ENABLE AFTER BUFFER WAIT

; +
[

FUNCTION:

;
’

:
:
:

THIS ROUTINE IS CALLED BY THE BUFFER POOL MANAGER WHEN
A BUFFER ALLOCATION REQUEST CAN BE SATISFIED, FOLLOWING
AN ALLOCATION FAILURE AND A CALL TO 'S$RDBWT'.

ENTRY:

R4 = ADDRESS OF CCB AND RECEIVE BUFFER

;

= ADDRESS OF DEVICE

EXIT:

R4 = ADDRESS OF 'C.STS'
(SP)= SAVED VALUE OF R3

LINE TABLE

= ADDRESS OF

'D.RCCB'

IN THE

LINE TABLE

IN THE CCB

:
SSDASR:

ADD
CALL

#D.RDB2,R5
RBFUSE

;;
;;

MOV
JMP

R3,-(SP)
DRCLRA

;; PUSH R3 FOR EXIT AT 'DREXIT', ABOVE
;; RESET AND ACTIVATE THE RECEIVER

#CS.BUF, (R4)

;;

PREV.

ALLOC.

$SDSTR

START UP DEVICE AND LINE ACTIVITY

BIS

POINT TO SECOND RCVR-CSR WORD
ASSIGN BUFFER TO THE RECEIVER

D-9

FAILURE TO CCB 'C.STS'

:
$SDSTR:

205:

60S:

BITB

#DD.ENB,D.FLAG (R5)

;»

HAS

BNE

60S

;;

THE
--

LINE BEEN ENABLED ?

REJECT

THE

MOV

D.RDBF(R5) ,R3

;;

RECEIVER CSR ADDR

MOV

D.STN(R5),(R3)

;;

SET

BIS

#RXREN, - (R3)

;;

ENABLE

MOV

R5,—- (SP)

;;

SAVE LINE TABLE START ADDRESS

ADD

#D.RDB2,R5

:»

ADJUST

CALL

RBFSET

;;

ASSIGN

BCS

208$

;;

FAILED - START THE TRANSMITTER

BIS

#RXITEN, (R3)

;:;

ENABLE

ADDRESS

THE

BYTE

[SEL

'START'

FOR

BUFFER

RECEIVE

CCB

ROUTINE
AND

INTERRUPTS

LINE TABLE

(SP) +,R5

: ;

RECOVER

D.FLAG (R5)

LINE

HAS

BEEN

BIT

#DC.HDX,D.DCHR(R5)

;;

CHECK

CTLCMP

;;

CORRECT

BIS

#DSRTS, (R3)

;;

ASSERT

'REQUEST

CTLCMP

...AND

POST

;;

STATUS

-3:;

RETURN

ERROR

#CS.ERR!CS.DIS,R3

DP.NOP:

;;

CONTROL

;;

STATUS

THAT
-

ASSUMPTION
STARTUP

COMPLETE

START

LINE

FUNCTION

START

STARTED

BNE

CTLERR

BUFFER

RECEIVER

MOV

R3
MODE

RECEIVER

CLRB

MOV

OPERATING

SEND'

LINE

COMPLETE

DISABLED
W/COMPLETION

NO-OPERATION

CTLCMP:

CLR

MOV

(SP)+,R4

SUCCESSFUL

CTLERR:
SYNRET

.SBTTL
e

;
P

e e e

S$SDSTP

e e e e e e e e e

*"'sS

VALUE

LINE ACTIVITY

;
H

;;

$DSDTR, - (R3)

;;

DISABLE

RECEIVER,

CLR

4 (R3)

;;

DISABLE

TRANSMITTER

MOV

D.RCCB(RS),R4
208
SRDBRT

;

FUNCTTION

D.RDBF(R5) ,R3

[SEL
LEAVE

TO R3

'DSDTR'

ACTIVE

;; ACTIVE RECEIVE CCB TO R4

;; NONE THERE - SKIP IT
;; RETURN BUFFER TO THE POOL

CLR

D.RCCB(R5)

;;

NO RECEIVE

CLR

;;

CLEAR

BISB

D.SLN(R5) ,R4

;;

SET

CALL

SRDBQP

;;

PURGE

CCB ASSIGNED

FOR

SYSTEM

PARAMETER

LINE

USE

NUMBER

BUFFER WAIT QUEUE

BISE

#DD.STR,D.FLAG(R5)

;;

LINE

D.TCCB(R5)
CTLCMP

;;
;;

IS THERE AN ACTIVE
NO —-— POST CONTROL

MOV

(SP)+,D.KCCB(R5)

SAVE THE CONTROL CCB FOR TIMEOUT

MOVB
ASYRET

#1, (R5)

;;
;3

MAKE SURE THE TIMER IS ACTIVE
RETURN WITH ASYNCHRONOUS COMPLETION

T T T T T e e e

T T T T T T

e e

S$SDENB
e e

-L

T e

e e e e

THE

LONGER

INE

A
e

STARTED
TRANSMIT
COMPLETE

CCB

LINE AND DEVICE

ENABTULE
e

ENABLE

e e e e

REQUESTS

TST
BEQ

:
P

e e

RETURN

MOV

.SBTTL
T

STOP DEVICE AND

CONTROTL

SAVED

|
RECEIVER CSR ADDR

BEQ
CALL

20S:

RECOVER

SYNCHRONOUS

- ————— e

TOP"

SSDSTP: :
“
MOV

;;
;;

ND
e

———————————— :

DEVICE
e

;

e e e ;

SSDENB:
:
MOV

D.RDBF(R5) ,R3

; i

RECEIVER

BIS

#TXRSET, 2 (R3)

RESET

THE

D-10

CSR

ADDRESS

DEVICE

[SEL

(1-US

SINGLE-SHOT)

;;
;;
;;

BIC

# “C<DPADRC>,
(R5)

BIS

$#INPRM, (R5)

#DC.SPS, (R5)
409

;
;;

’

BEQ

#DC.SSS, (R5S)
60S
#DPSECS, 2 (R5)

CMPB

BNE
BIS

Ny
WE
e

;;
;;
;;

SDLC PRIMARY-STATION MODE ?
YES - FLAGS ARE SETUP AS IS

wme

#DC.ADR,- (R5)

BIC

CMPB

;CLEAR HIGH-ORDER BYTE OF 'D.STN' WORD
SETUP INITIAL PARAMETERS
ADDRESS-SIZE NO LONGER SIGNIFICANT

SDLC SECONDARY-STATION MODE ?
NO —- OPERATING MODE INVALID
ENABLE STATION ADDRESS CHECKING

SWAB

16-BIT STATION ADDRESS ?
NO -- SHOULD BE ALL SET
USE THE HIGH-ORDER BYTE IN DPV-11

wme

BEQ

POINT TO CHARACTERISTICS WORD #1

BIT

-E

#DC.ADR, (R5) +
2059
(RS)

wma

;;

#D.DCHR+2,R5

ADD

#DSDTR,-(R3)
;; ASSERT 'DATA TERMINAL READY' LINE
#DD.ENB,D.FLAG-D.DCHR-2(R5) ;; LINE IS ENABLED
;3 POST CONTROL FUNCTION COMPLETE
CTLCMP

BIS

#CS. ERR!CS DEV,R3
s
CTLERR

.SBTTL

$SDDIS

MOV

BITB

#CS.ERR!CS.ENB,R3
(R5)
#DD.STR,D.FLAG

BEQ

CTLERR

;; ERROR STATUS - INVALID PROTOCOL
;; POST CONTROL COMPLETE WITH ERROR

BICB

MOV

D.RDBF (R5) ,R3

DISABLE THE LINE

- (R3)
$DD.ENB!DD.STR,D.FLAG(R5)
CTLCMP

CLR
MOVB
BR

ADDRESS OF RECEIVER CSR

;;
;;
:;

mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm ;

ENSE

;

STATUS

MODEM

I sttt ;

:
SSDMSN:

D.RDBF(R5)
,R3

208$:

40S:

FOR RETURN CODES

CLEAR R4

ADDRESS OF RECEIVER CSR
IS

[SEL 2]

THE DATA-SET READY ?

BIT

$DSDSR,-(R3)

BEQ

20%

BIS

$#MC.DSR,R4

;;

YES - SET

BIT

#DSRING, (R3)

BEQ

49$

NO —--

BIS

#MC.RNG, R4

;;
;;
;;

YES - SET INDICATOR IN R4

BIT

#DSCARY, (R3)
60S
#MC.CAR,R4

13
;;
;;

IS THERE CARRIER PRESENT ?
NO -- POST COMPLETE
YES - SET INDICATOR IN R4

R4, (SP)
CTLCMP

;;
;;

RETURN RESULTS IN (SAVED) R4
POST CONTROL FUNCTION COMPLETE

BEQ
BIS

60S:

;;

MOV

;;

NO —--

INDICATOR IN R4

IS THE PHONE RINGING

. END

DPV

/X008/

BYTE

ORIENTED

DPV-11

DEVICE

.TITLE
.IDENT

DIGITAL

(C)

1980

CORPORATION,

MAYNARD,

EQUIPMENT

D-11

[SEL 2]

DISABLE RECEIVER + TURN DTR OFF
LINE NO LONGER ENABLED
CLEAR CARRY AND EXIT

SENSE MODEM STATUS

$SDMSN

ERROR CODE IF NOT STOPPED
IS LINE STATE CORRECT ?
NO -- REJECT THE DISABLE

MOV

MASS.

DRIVER MODULE

EXAMPLE

OF AN APPLICATION RSX-11M

BYTE

MDCDFS$
CCBDFS
TMPDF$
CHADFS

LINE

DEVICE

TABLE

SYMBOLS

OFFSET

MACROS

DEFINITIONS

TINIT=

(00010
Q@0020

TXINT=

000100

TXACT=

0000802

TSOM=

0P2400

TEOM=

201090

¥1

FLAGS

TXENA=

INITIAL

TRANSMIT

ENABLE

STATUS

TRANSMIT

INTERRUPT

TRANSMIT

ACTIVE

TRANSMIT

START

TRANSMIT

END

(HALF

DUPLEX)

ENABLE

MESSAGE

;

RECEIVE

CSR

FLAGS

RCVEN=

(00020

;

RECEIVE

ENABLE

RXINT=

000100

;

RECEIVE

INTERRUPT

CRC=

3%400

;

RECEIVE

CRC

SSYN=

(020000

;

STRIP

PROSEL=

040000

;

PROTOCOL

RINIT=

RXINT!RCVEN!DTR

;

INITIAL

"INPRM=

SSYN!PROSEL!CRC

;

INITIALIZATION

ENABLE

CHECK

SYNC
SELECTION

RECEIVE

(BYTE)

STATUS
FLAGS

;

MODEM

STATUS

FLAGS

RTS=

pRLRA4

;

REQUEST

CTS=

220C00

CLEAR TO SEND
DATA TERMINAL

DTR=

PeRRL2

;
;

DSR=

Q01000

;

DATA

RING=

P4apRa0Y

;

RING

SET

SEND

LEAD

READY

INDICATOR

’

;

DPV11l

DEVICE

DRIVER

DISPATCH

TABLE

DPASX

;

TRANSMIT

«WORD

DPASR

;

RECEIVE

- WORD

DPKIL

;

KILL

.WORD

DPCTL

;

CONTROL

. WORD

DPTIM

;

TIME

ENABLE

(ASSIGN

BUFFER)

I/0
INITIATION

OUT

**-SDPVRI-DPV11l

RECEIVE

INTERRUPT

SERVICE

ROUTINE

: .WORD
SDPVTB:

THE

;

DEVICE
THE

INTERRUPT

HARDWARE

;

'"JSR R5,$DPVRI'

;

TABLE.

AND

VECTORED

THIS

ROUTINE

TO THE DEVICE

LINE

INSTRUCTION AT THE

ENTERED

BEGINNING

;

INPUTS:

;

STACK::

;

@(SP)

SAVED

;

2(SP)

INTERRUPTED

4 (SP)

INTERRUPTED

;

6 (SP)

INTERRUPTED

ADDRESS

DEVICE

LINE

TABLE

RS
BIAS

;

DRIVER

CHARACTERISTICS

TRANSMITTER

DEFINE

DEVICE

OFFSETS

wmy

;

SYMBOL

CONTROL

CCB

LOCAL

MODEM
THE

;

DEFINE
DEFINE

MDCDFS$
CHADFS

.MCALL
.MCALL

SINTSX,SINTXT,INHIBS,
ENABLS
CCBDF$, TMPDFS$,SLIBCL

.MCALL

ORIENTED DPV-11

;

OUTPUTS:

D-12

OF THE

TABLE

LINE

s
wmy
e

SDPVRI::
MOV

R4,-(SP)

;::

MOV

(R5) +,R4

:::;

SAVE R4
GET ADDRESS

MOV

(R4) ,R4

;:;

GET CHARACTER AND FLAGS

DPRHO

BMI

ANY

ERROR

RECEIVER

DATA

BUFFER

OVERRUN

SAVE
MAP

;

STORE CHARACTER IN RECEIVE BUFFER

RESTORE

;

LTI

(R5) +,KISAR6

KISAR6,- (SP)

MOV
MOV

b1]

MSSMGE

.1F

;;;

CURRENT
TO

DATA

MAP
BUFFER

R4,@(R5)+

MOVB

.IFTF

-y

(SP)+,KISARG6

MOV

LIFT

MAPPING

. ENDC

(R5)"

DEC

;;;

BEQ

DPRCP

INC

- (RS)
(SP)+,R4

MOV

SINTXT

;;;

DECREMENT REMAINING BYTE COUNT
IF

RECEIVE

COMPLETE

3 ::; ADVANCE BUFFER ADDRESS
;;; RESTORE REGISTERS
e

EXIT

THE

INTERRUPT

EXCEPTIONAL

RECEIVE

SERVICE

ROUTINES

HARDWARE

OVERRUN

LSB

ADD

#<RCNT-RDBF-2>,R5

MOV

#100001,RFLAG-RCNT(RS5)

;;;

POINT TO COUNT CELL

MOV

;;; CLEAR RECEIVE
#CS.ERR+CS.ROV,RSTAT-RCNT(R5)
;;;

;;;

SET

FLAGS

TO COMPLETE

REQUEST AND

ACTIVE ON EXIT
SET OVERRUN STATUS

RECEIVE

BYTE

COUNT RUNOUT

wms

DPRHO:

. ENABL

DPRCP:

MOV

R4, (R5)+

MOV
BIC
MOV

RDBF-RPRI
(R5) ,R4 ;;; GET RECEIVE DATA BUFFER ADDRESS
$RXINT,-(R4)
;:;; CLEAR RECEIVER INTERRUPT ENABLE
(SP) +, R4
;:; RESTORE R4 SO 'SINTSV' IS HAPPY

SINTSX

FLAG

AND

PRIORITY

(R5) +

POINT

(R5) +
20$

;;
;;

LOAD C-BIT FROM FLAGS (BIT 0)
IF CS DATA, POST COMPLETION

;:;

GET

TST

(R5) ,R4
|

MEB

FLAGS

PRIMARY

CCB

PRESAVED BUT NOT R4)

WORD

ADDRESS

SLIBCL

HDRA-RPRIM,RS5,S$DDHAR,SAV

.NLIST

MEB

TST
BMI
BEQ
ADD
MOV

R3
;;
10$
;;
78
:;
#2,R3
;;
R3,RPCNT-RPRIM(R5)

-2 (R5)

ADDITIONAL

(R5

SAVE

SINTSV

POINT

DO A TRICKY

ASR
BCS

ROR

CRC

;;;
R3,-(SP)

.LIST

SAVE

:;;

MOV

:;:;

SAVE

;;
|

CALL DDHAR THROUGH

'FINAL SEEN'

IN FLAGS

LINE TABLE

(BIT 15 SET)

EXAMINE BYTE COUNT FOR THIS MESSAGE
IF MI AN INVALID HEADER RECEIVED
IF EQ SET TO RECEIVE REST OF HEADER
ACCOUNT FOR BCC IN CURRENT COUNT
;; SAVE DATA COUNT UNTIL HEADER CRC

D-13

wmg

#RCNT-RTHRD,
R5
R3, (R5)

INC

- (R5)

POINT

SET
MOVE

BUFFER

GET

ADDRESS

RECEIVE

DATA

BUFFER

ADDRESS

RECEIVE

DATA

BUFFER

WMy
W

INCLUDE

ADD
MOV

.IF

ADD

HEADER

MARK

- (R5)

CHECKED

REMAINING

INC

GET

#5,R3

MOV

DATA

PROGRESS

CURRENT

COUNT

CURRENT

FLAGS

(BIT

TOTAL

COUNT

SET)

COUNT

BYTE

COUNT

ADDRESS

PAST

BCC

MSSMGE

MOV

-4 (R5) ,R3

-~
e 1]

FINISH

Wmg

MESSAGE

;

RECOVER

SET

GET

wme

MOV

cIFF

- ENDC

INVALID

HEADER

e 1

REXT®

COMMON

CODE

RECEIVED

BIT

#CS.MTL,R3

BNE

318

;

MOV

(R5) +,R4

CALL

BUFUSE

MOV

RDBF-RPRIM(R5S)
, R3

403

;

;;

; ;

SET

TOO

YES,

LONG

POST

COMPLETION

PRIMARY

CCB

ADDRESS

THIS

CCB

AGAIN

POINTER

REC.

CLEAR

RECEIVE

(CLEARS

DAT.

ACTIVE

'RSTAT')

BUFF.

FORCE

RESYNC

POST

COMPLETION

RECEIVE

COMPLETE

Wws

p—t Ne

we W

POINTS

PRIMARY

CCB

ADDRESS

RCNT-RPRIM(R5)

25%

MI,

YES

MOV

#CS.ERR+CS.DCR, R3

; ;

ELSE

CRC

319

SET

H ;

RETURN

BEQ

309

;

ADD

RPCNT-RPRIM(RS)
,

REXT1

403

CLR

RPCNT-RPRIM(RS)

BIS

$#RXINT,- (R3)

REXT1:

MOV

(SP)+,R3

=
W\

RETURN

wfiuwyg

-y

REXT:

my
Wy
s

CSR

GOOD

POST

RECEIVE

ACTIVE

FORCE

Whk

ADDRESS

RECEIVE

CCB

RECEIVE

PARTIAL

COUNT

RESTORE
RETURN

DAT

BUFFER

RECEIVER

R3
TO

LABEL

RESYNC

BUFFER

D-14

HEADER

COMPLETION

CLEAR

ENABLE

NON

BUFFER

ADDRESS
STATUS

Wy
s

RECEIVE

CCB

ADDITIONAL

REF

EXIT

ADDRESS

MARK

;;

COUNT

STATUS

RESET

TOTAL

EXIT

PICK

CLEAR

FOR

PRIMARY

SET

CHAR

BCS

BACK

LAST

COMMON

GET

SET

BUFSET

SYNC

GET

;;

CALL

SET REMAINING COUNT

RDBF-RSTAT
(RS) , R

GET

DLC

MESSAGE

WE W

‘$DDRCP

MOV

TAKE

FOR

;;

CALL

BNE

(a3
s me ws (T TM

(R5) ,R3

BIS

GET

R3
(R5)+,R4

;;

STATUS

BIT

CLR
MOV

PUT

INCLUDE

VALID

TME

REXT

END

ERROR

BUFFER

RDBF-RPRIM(R5)
,R

FORCE

MOV

CRC

RTHRD-RPRIM(RS5)

RADD-RPRIM(R5)

RFLAG-RPRIM(R5)

INC

NONE

ROL

REXT@:

IS CRC ERROR FLAG SET ?

H ;

RPCNT-RPRIM(R5)+ R CNT-RPRIM(R5)

MOV

SEC

30$:
31S:

25$:

TST
BMI

E Wy WE

20S:

|
SYSTEM

DATA

BUFFER

AVAILABLE

TURN

ACTIVE
TO

INTERRUPTS

OFF

RECEIVER

RESYNC

'RPRIM'

R5 = ADDRESS OF

;
;

DPCRA:

CLR
BIC

- (R5)
#RCVEN,
- (R3)
RPCNT-RFLAG (R5)

CLR

;

’

CLEAR

FLAGS

CLEAR

RECEIVE

RESET

#CS.RSN,RSTAT-RF L AG (R5)
ENABLE
#RINIT, (R3)
;

REXT1

.DSABL

LSB

FINISH

;

WORD

ACTIVE

FOR RESYNC

PARTIAL COUNT
;;
INDICATE A RESYNC

BIS

;

RECEIVER
IN

COMMON

CODE

**-SDPVTI-DPV11l

;

TRANSMIT

INTERRUPT SERVICE

;

THIS ROUTINE IS ENTERED ON A TRANSMITTER INTERRRUPT VIA
A "JSR R5,DPVTI' WITH R5 CONTAINING THE ADDRESS OF THE
DEVICE LINE TABLE OFFSET BY 'TCSR'.

;

INPUTS:

;
;

;

R5 = ADDRESS OF DEVICE LINE TABLE +

;

STACK

CONTAINS:

;
;
:

@ (SP)
2(SP)
4 (SP)
6 (SP)

;

'TCSR'

= INTERRUPTED R5
= INTERRUPTED BIAS
= INTERRUPTED PC
INTERRUPTED PS

;

OUTPUTS:

;
;

ETC.

;
;

—

SDPVTI::

.ENABL

LSB

MQV

R4 ,-(SP)

.IF DF

MSS$SMGE

MOV
MOV

MOV
TST
BMI
DEC
BEQ

:::

SAVE R4

KISAR6,- (SP)
(RS) + ,KISAR6

:::
;;;

SAVE CURRENT MAPPING
MAP TO DATA BUFFER

@ (R5)+, (R4)

::;

OUTPUT A CHARACTER

(SP)+,KISAR6

; ;;

RESTORE PREVIOUS MAPPING

(R5) +, R4
(R4) +
108S
TCNT-TCSR-2(R5)
208

;:;; GET TRANSMITTER CSR ADDRESS
::; TEST FOR UNDERRUN
;3; IF MI, UNDERRUN - WAIT FOR TIMEOUT
;;; DECREMENT COUNT
:3; IF EQ, BYTE COUNT RUNOUT

.IFTF

MOVB
JIFT

MOV
.IFTF

INC

MOV

- (R5)

(SP) +, R4

;;;

UPDATE BUFFER ADDRESS

;;;

RESTORE

SINTXT
TRANSMITTER

DISABLE

UNDERRUN

TRANSMITTER

INTERRUPTS

AND

WAIT

FOR

D-15

TIMEOUT

BISB

#TSOM/40@,1(R4)

MOV

#TUNST, TSTAT-TCSR-2(R5)

;;;

CLEAR UNDERRUN
;;;

SET

BIT

STATE

|
TO

DISABLE

TRANSMITTER

10$:

BYTE

COUNT

RUNOUT

TRANSMIT

STATE

PROCESSING ROUTINES:

ADDRESS

TRANSMITTER

CSR

ADDRESS

THREAD WORD

CELL

OUTPUT

208 :

ADD

#TPRI-TCSR-2,R5

BIC

BTXINT, - (R4)

MOV

;;;

POINT TO PRIORITY

;;;

RESTORE

DATA

;:3; CLEAR INTERRUPT ENABLE

(SP) +, R4

SINTSX

:SAVE WITH

'SINTSV'

STACK

HAPPY

BUT NOT R4

.IFT

MOV

KISARG, - (SP)

SAVE CURRENT MAPPING

MOV

R3, - (SP)

MOV

TCSR-TSTAT(R5)
,R3

CALLR

@ (R5) +

.DSABL

LSB

;

SAVE

;;

GET

ADDITIONAL

TRANSMITTER

DISPATCH

CSR

PROCESSING

ADDRESS
ROUTINE

**-DPASX-ASSIGN

THIS
QUEUE

ROUTINE
A

CCB

IS
FOR

TRANSMIT

ENTERED

BUFFER

VIA

THE

MATRIX

SWITCH

TRANSMISSION.

INPUTS:
=

ADDRESS

CCB

ADDRESS

DEVICE

QUTPUTS:

THE

TRANSMITTER

INITIATED;

OTHERWISE,

THE

END

TRANSMIT
LINE

IDLE,
THE

SECONDARY

TABLE

TRANSMISSION

CCB

(OR

CHAIN)

QUEUED

CHAIN.

ms Ws

REGISTERS

ME WMy

WS W

R4
R5

ME TM

Wa ms we ws Ws Wy

WE Me g

e e W

.IFTF

R3,

MODIFIED:

R4,

AND

DPASX:

|
MOV

“
;

GET

BIC

TCSR(R5) ,R3
#TXINT, (R3)

;

DISABLE

ADD

#TPRIM,RS

;

POINT

KISAR6,-(SP)

;

SAVE

CURRENT

TRANSMITTER

CSR

TRANSMITTER

PRIMARY

CELL

+IFT

MOV

MAPPING

.IFTF
MOV

R3,-(SP)

;

SAVE

TST

(R5) +

;

PRIMARY

ASSIGNED

D-16

ADDRESS

INTERRUPTS

BNE

109

IF NE,

YES - QUEUE TO SECONDARY CHAIN

CALL

TBSET

;

SET

PRIMARY

BIT

# TXACT, (R3)
STSTR

:
;

TRANSMITTER ACTIVE ?
IF EQ, NO - START IMMEDIATELY

MOV

$STSTR, - (R5)

;

SET

STATE

WAITI

WAIT

FOR

MOV
MOV

R4,- (SP)

SAVE POINTER TO FIRST CCB

RS, R4

;

COPY

MOV

(R4) ,R5

;

GET

BNE

20$

IF NE,

KEEP GOING

MOV

(SP)+, (R4)

;

FINISH

BEQ

10$:
205 :

**_STSTR-STARTUP

STARTUP

POINTER
NEXT

CCB

COMMON

CODE

PROCESSING

BIS

#RTS,-4(R3)

;

ASSERT

REQUEST TO

BIS

#TXENA, (R3)

;

ENABLE

TRANSMITTER

MOVB

TIMS-TTHRD(R5)
, TIME-TTHRD(RS5)

START

TIMER

;

SEND

**-STCTS-WAIT

FOR

CLEAR

SEND

STATE

PROCESSING

Wme

STSTR:

STATE

FOR

INTERRUPT

LINK NEW CCB CHAIN TO LAST CCB

;

TEXT2

STCTS:

BIT

$CTS,-4(R3)

BNE

STSYN
#STCTS,-(R5)

3
;

# SPADB, R4
$#TSOM,- (SP)
TEXTI1

;
;
;

MOV
MOV
MOV

**-STSYN-SYNC

CLEAR TO

SEND

IF NE, YES - START
SET STATE FOR CTS

?
SYNC

TRAIN

SET ADDRESS OF PAD BUFFER
SET TSOM, CLEAR TEOM
FINISH IN COMMON CODE

TRAIN REQUIRED STATE PROCESSING

Twa

MOV

$STDAT, - (R5)

. SET STATE FOR DATA

MOV

#SSYNB, R4

;

MOV

$TSOM,-(SP)

;

SET TSOM,

CLEAR TEOM

TEXTH

;

FINISH

COMMON

**-STCRC-SEND

. ENABL

CODE

PRCCESSING

LSB

CRC

BNE

MOV

19S5
IF NE, NOTHING MORE TO SEND
#STDAT,~- (RS)
ASSUME NEXT STATE IS SEND SYNC'S
#CF.SYN,C.FLG-C.BUF(R4) ; ARE SYNC'S REQUIRED ?
208$
; IF EQ, NO - LEAVE ASSUMED STATE
#STSYN, (R5)
; ELSE CHANGE STATE TO SEND SYNC'S

208

MOV

$}STIDL,- (R5)
#TXENA, (R3)

BEQ

BIC

SET UP NEXT CCB

Wwa

SEND

POST COMPLETION AND

;
g

BIT

#TEOM,2(R3)
TPOST

BIS
CALL
MOV

19$:

STATE

STCRC:

CRC

SET ADDRESS OF SYNC BUFFER

WAIT

FOR CRC TO BE

SENT

SET STATE TO IDLE
SHUT

DOWN

STSYN:

D-17

TRANSMITTER

**-WAITI-WAIT

FOR

INTERRUPT

;
|

MOV

#1, TCNT-TSTAT(RS5)

MOVB

TIMS-TSTAT
(R5) ,TIME-TSTAT (R5)

;

WAIT FOR ONE INTERRUPT

TEXT2

**-STIDL-IDLE

STATE

;

FINISH

DROP

REQUEST

START

COMMON

TIMER

CODE

PROCESSING

wWE

WAITI:

STIDL:

BIC

#RTS,-4(R3)

;

TST

- (R5)

;

SEND

CLRB

TIME-TSTAT(RS)

;

CLEAR

TIMER

TEXT3

;

FINISH

.DSABL

LSB

RUN

STATE

COMMON

CODE

**-TUNST-TRANSMIT

DATA

UNDER

WMy

WTMy

wmy

30$:

ALL

TRANSMIT

BUFFERS

HIGHER

LEVEL

- *

RETURN

TUNST:

ADD

#-TTHRD, R5

CLRB

(R5)

;s TIMEOUT

EXPECTS

; iRESET

CALL

DPTIM

MOV

#STIDL,TSEC-TSTAT (R5)

; ;SET

;;FAKE

TEXT3

; i TAKE

**-STDAT-DATA

STATE

LINE

TABLE

POINTER

TIMEOUT

STATE

RETURN

BUFFERS

IDLE

COMMON

EXIT

PROCESSING

DDM

TIMER

STDAT:

MOV

ADD

19S$:

GET

;

TST

(R4) +

;

LAST

109

;

CALL

TPOST

MOV

#STDAT, - (R5)

BIT

MOV

CLR

ADDRESS

UPDATE

BPL

BEQ
205:

(R5) ,R4
;
#C.FLG-C.STS,
(R5)

BUFFER

PL,

FLAGS

WORD

FROM

THREAD

POINTER

THIS

CCB

(BIT

SET)

SET

CCB

FOLLOWING

THIS

BUFFER

;

POST

;

ASSUME DATA CONTINUES

COMPLETION

#CF.EOM,C.FLG-C.BUF(R4)

20'$

THREAD

;

SEND

AND

CRC

; IF EQ, NO - LEAVE ASSUMED STATE

#STCRC, (RS)

;

ELSE

CHANGE

- (SP)

STATE

FOR

;

CLEAR TSOM,

CLEAR

TEOM

CRC

SENT

;

**-TEXT@-COMMON

;
;
;

**-TEXT1**-TEXT2**-TEXT3-

EXIT

ROUTINES

;

TEXT@:

MOVB

TEXT1:

ADD

TIMS-TSTAT
, TIME-TSTAT(R
(R5)
5) ;
#TCSR-TSTAT+2,R5

;

POINT

START TIMER

CURRENT

BUFFER

CELL

. IFT
MOV

(R4)+, (R5) +

.IFF
TST

;

COPY

RELOCATION

BIAS

(R4) +

|
;

SKIP

OVER

D-18

RELOCATION

BIAS

CCB

+, (R5) +
(R4)

(R4)
, (R5)

MOV
MOV

LIFTF

COPY

VIRTUAL

AND

THE

ADDRESS

BYTE

COUNT

-4 (R5) ,KISARSG

MAP

MOV

BUILD

CHARACTER

.IFT
TO

DATA

BUFFER

UPDATE

VIRTUAL

.IFTF

MOV

(SP)+,2(R3)
$#TXINT, (R3)
(SP)+,R3

TEXT2:

BIS

TEXT3:

MOV

OUTPUT

ADDRESS

-2 (R5)

OUTPUT

CHARACTER AND

WUE

@-2(R5), (SP)

INC

ENABLE

TRANSMITTER

BISB

RESTORE

LIFT

D-19

FLAGS

INTERRUPTS

GLOSSARY
Asynchronous Transmission
Transmission in which time intervals between transmitted characters may be of unequal length.
Transmission is controlled by start and stop elements at the beginning and end of each character.
Also called start-stop transmission.
BDIN
Data Input on the LSI-II bus.

BDOUT
Data Output on the LSI-II bus.
BIAKI

Interrupt Acknowledge.
Bit-Stuff Protocol

Zero insertion by the transmitter after any succession of five continuous ones designed for bitoriented protocols such as IBM’s Synchronous Data Link Control (SDLC).
Bits per Second (b/s)

Bit transfer rate per unit of time.
BIRQ

Interrupt Request priority level for LSI-11 bus.
BRPLY

LSI-11 Bus Reply. BRPLY is asserted in response to BDIN or BDOUT.
BSYNC

Synchronize — asserted by the bus master device to indicate that it has placed an address on the
bus.
|
Buffer

Storage device used to compensate for a difference in the rate of data flow when transmitting
data from one device to another.

BWTBT

Write Byte.

CCITT
Comite Consultatif Internationale de Telegraphie et Telephonie — An international consultative
committee that sets international communications usage standards.
Control and Status Registers (CSRs)
Communication of control and status information is accomplished through these registers.

GLOSSARY-I1

Cyclic Redundancy Check (CRC)
An error detection scheme in which the check character is generated by taking the remainder
after dividing all the serialized bits in a block of data by a predetermined binary number.
Data Link Escape (DLE)
A control character used exclusively to provide supplementary line control signals (control char-

acter sequences or DLE sequences). These are 2-character sequences where the first character is
DLE. The second character varies according to the function desired and the code used.

Data-Phone DIGITAL Service (DDS)
A communicaitons service of the Bell System in which data is transmitted in digital rather than
analog form, thus eliminating the need for modems.

DIGITAL Data Communications Protocol (DDCMP)

DIGITAL’s standard communications protocol for character-oriented protocol.

Direct Memory Access (DMA)

Permits I/O transfer directly into or out of memory without passing through the processor’s general registers.

Electronic Industries Association (EIA)

A standards organization specializingin the electrical and functional characteristics of interface
equipment.

Full-Duplex (FDX)

Simultaneous 2-way independent transmission in both directions.

Field-Replaceable Unit (FRU)

Refers to a faulty unit not to be repairedin the field. Unitis replaced with a good unit and faulty

unit is returned to predetermined location for repair.
Half-Duplex (HDX)

An alternate, one-way-at-a-time independent transmission.

LARS

Field Service Labor Activity Reporting System.

Non-Processor Request (NPR)

Direct memory access-type transfers, (see DMA). |

Protocol

A formal set of conventions governing the format and relative timing of message exchange be-

tween two communicating processes.
RS-232-C

EIA standard single-ended interface levels to modem.

RS-422-A

EIA standard differential interface lcvels to modem.

RS-423-A
EIA standard single-ended interface levels to modem.

GLOSSARY-2

RS-449

EIA standard connections for RS-422-A and RS-423-A to modem interface.
Synchronous Transmission
Transmission in which the data characters and bits are transmitted at a fixed rate with the transmitter and receiver synchronized.
V.35

(CCITT Standard) — Differential current mode-type signal interface for high-speed modems.

GLOSSARY-3

QMA DPV11 Serial Synchronous Interface

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